Reminder: Mark Oskin seminar this morning

[Sheila D Clark]

Wednesday, July 7 
10:30am, B02 CSL

Mark Oskin 
University of Washington http://www.cs.washington.edu/homes/oskin/

"WaveScalar: Scalable Processor Design with Dataflow Computing"

For the next decade silicon technology will continue to follow Moore's 
Law and provide an exponential increase in the availability of raw 
transistors.  Effectively translating this resource through 
architectural design into application performance, however, is an open 
challenge.  Several factors combine to frustrate architects: (1) the 
ever-increasing disparity between computation and communication 
performance -- fast transistors but slow wires; (2) the increasing cost 
of circuit complexity, leading to longer design times, schedule slips, 
and more processor bugs; and (3) the decreasing reliability of circuit 
technology, caused by shrinking feature sizes and the continued scaling 
of the underlying material characteristics.  In particular, superscalar 
processors will not scale because they are built from inherently 
centralized execution algorithms and thus require vast infrastructures 
of slow broadcast networks, associative searches, and complex control 
logic.

The WaveScalar project is an effort to design an execution system that 
addresses the scaling problems facing silicon technology.  
Fundamentally WaveScalar diverges from mainstream superscalar design by 
basing its execution algorithm on dynamic tagged-token dataflow.  
Unlike prior dataflow machines, however, WaveScalar executes arbitrary 
imperative language code, such as C, by way of its wave-ordering memory 
interface.  WaveScalar binaries execute on an intelligent memory 
system.  Conceptually each instruction in a WaveScalar binary executes 
in place in the memory system and explicitly communicates with its 
dependents in dataflow fashion.  WaveScalar architectures cache 
instructions and the values they operate on in a WaveCache, a simple 
grid of ``alu-in-cache'' nodes.  By co-locating computation and data in 
physical space, the WaveCache minimizes long wire, high-latency 
communication.  By using a simple tiled grid architecture it is easy to 
design, verify, and make fault tolerant.

In this talk I will describe the WaveScalar ISA and WaveCache 
microarchitecture.  Performance results from the Spec2000 and 
Mediabench benchmark suites demonstrate a 3X performance gain for 
single-threaded applications compared to a superscalar with near 
unlimited and idealized resources.  Being dataflow, WaveScalar is 
naturally multithreaded, and performance from the Splash2 benchmark 
suite demonstrate in excess of 110 IPC.  After describing current work 
I will provide a broad overview of the future of WaveScalar research 
including our current efforts on compiler design, operating system 
construction, and fault tolerance mechanisms.

Bio:

Mark Oskin is an Assistant Professor at the University of Washington in 
the Department of Computer Science and Engineering.  His interests 
include scalable processor design and architectural support for quantum 
computers.