Architecture Seminar: Torres, 6/3, 2pm

[Sheila D Clark]

Architecture Seminar
Friday, June 3, 2005
2pm, 4405 SC

Enrique Torres

"Store Buffer Design in First-Level Multibanked Data Caches"
This work will appear in ISCA 2005.


The paper focuses on how to design a Store Buffer (STB) well suited to 
first-level multibanked data caches. Our goal is to forward data from 
in-flight stores to dependent loads with the latency of a cache bank. 
For that we propose a particular two-level STB design in which 
forwarding is done speculatively from a distributed first-level STB 
made of extremely small banks, while a centralized, second-level STB 
enforces correct store-load ordering a few cycles later. To that end we 
have identified several important design decisions: i) delaying 
allocation of first-level STB entries until stores execute, ii) 
deallocating first-level STB entries before stores commit, and iii) 
selecting a recovery policy well-matched to data forwarding 
misspeculations. Moreover, the two-level STB admits two enhancements 
that simplify the design leaving performance almost unchanged: i) 
removing the data forwarding capability from the second-level STB, and 
ii) not checking instruction age in first-level STB prior to forwarding 
data to loads. Following our guidelines and running SPECint-2K over an 
8-way out-of-order processor, a two-level STB (first level with four 
STB banks of 8 entries each) performs similarly to an ideal, 
single-level STB with 128-entry banks working at the first-level cache 
latency.

Short Bio
Enrique F. Torres is an Assistant Professor at the University of 
Zaragoza, Spain, where he has been since 1996. He plans to complete the
Ph.D. program in June 2005. He received his M.S. in Computer Science
from the Polytechnic University of Catalonia (UPC), Spain, in 1994. His
research 
interests are in microarchitectural techniques that optimize
performance, power, reliability and complexity, with a particular focus
on the first level memory hierarchy.