Architecture Seminar: Moshovos, 12/7

[Clark, Sheila D]

Architecture Seminar
Friday, December 7, 2007
4pm, 4405 SC

Andreas Moshovos
University of Toronto

"Predictor Virtualization and RegionTracker: Two Ways of Exploiting
Multi-Megabyte Caches"

Modern on-chip caches continue to grow in size with multi-megabyte
caches being the norm today. Two techniques that revisit the design and
role of on-chip caches will be presented: Predictor Virtualization and
RegionTracker.

Predictor Virtualization can drastically reduce the cost or improving
the accuracy and effectiveness of predictor-based techniques. Instead of
demanding large, dedicated resources, Predictor Virtualization spills
metadata in the memory hierarchy. It will be shown that a virtualized
state-of-the-art memory prefetcher needs about 1KB of dedicated
resources compared to the 70KB needed without virtualization. A number
of additional opportunities facilitated by Predictor Virtualization will
be discussed.

RegionTracker, is a framework for implementing coarse-grain
optimizations in the on-chip memory hierarchy. As several recent works
have demonstrated, coarse-grain information and management can improve
performance and power in the on-chip memory hierarchy. RegionTracker
aims at eliminating the area and complexity costs associated with
existing ways of implementing such coarse-grain optimizations. To
demonstrate the potential of RegionTracker, it will be shown that it
improves the effectiveness of a broadcast elimination technique "for
free", that is without requiring any additional resources compared to a
conventional block-based cache of the same capacity. Implementing
Stealth Prefetching over RegionTracker will also be discussed.

BIO: Andreas Moshovos is an Associate Professor at the Department of
Electrical and Computer Engineering of the University of Toronto. Along
with several students he has been developing performance and power
optimization techniques for high-end processors some of which have been
implemented in commercial designs.