From johnny.chen at apple.com Mon Feb 21 15:24:49 2011 From: johnny.chen at apple.com (Johnny Chen) Date: Mon, 21 Feb 2011 21:24:49 -0000 Subject: [Lldb-commits] [lldb] r126144 - in /lldb/trunk/source/Plugins/Instruction/ARM: EmulateInstructionARM.cpp EmulateInstructionARM.h Message-ID: <20110221212450.061BA2A6C12C@llvm.org> Author: johnny Date: Mon Feb 21 15:24:49 2011 New Revision: 126144 URL: http://llvm.org/viewvc/llvm-project?rev=126144&view=rev Log: Add emulation methods for "TST (immediate)" and "TST (register)". Plus modified EmulateANDImm/Reg to delegate to TSTImm/Reg for Thumb2 32-bit instructions when Rd == '1111' and setflags is true. Modified: lldb/trunk/source/Plugins/Instruction/ARM/EmulateInstructionARM.cpp lldb/trunk/source/Plugins/Instruction/ARM/EmulateInstructionARM.h Modified: lldb/trunk/source/Plugins/Instruction/ARM/EmulateInstructionARM.cpp URL: http://llvm.org/viewvc/llvm-project/lldb/trunk/source/Plugins/Instruction/ARM/EmulateInstructionARM.cpp?rev=126144&r1=126143&r2=126144&view=diff ============================================================================== --- lldb/trunk/source/Plugins/Instruction/ARM/EmulateInstructionARM.cpp (original) +++ lldb/trunk/source/Plugins/Instruction/ARM/EmulateInstructionARM.cpp Mon Feb 21 15:24:49 2011 @@ -4444,9 +4444,9 @@ Rn = Bits32(opcode, 19, 16); setflags = BitIsSet(opcode, 20); imm32 = ThumbExpandImm_C(opcode, APSR_C, carry); // (imm32, carry) = ThumbExpandImm(i:imm3:imm8, APSR.C) - // TODO: Emulate TST (immediate) + // if Rd == '1111' && S == '1' then SEE TST (immediate); if (Rd == 15 && setflags) - return false; + return EmulateTSTImm(eEncodingT1); if (Rd == 13 || (Rd == 15 && !setflags) || BadReg(Rn)) return false; break; @@ -4529,9 +4529,9 @@ Rm = Bits32(opcode, 3, 0); setflags = BitIsSet(opcode, 20); shift_n = DecodeImmShift(Bits32(opcode, 5, 4), Bits32(opcode, 14, 12)<<2 | Bits32(opcode, 7, 6), shift_t); - // TODO: Emulate TST (register) + // if Rd == '1111' && S == '1' then SEE TST (register); if (Rd == 15 && setflags) - return false; + return EmulateTSTReg(eEncodingT2); if (Rd == 13 || (Rd == 15 && !setflags) || BadReg(Rn) || BadReg(Rm)) return false; break; @@ -5470,6 +5470,139 @@ return true; } +// Test (immediate) performs a bitwise AND operation on a register value and an immediate value. +// It updates the condition flags based on the result, and discards the result. +bool +EmulateInstructionARM::EmulateTSTImm (ARMEncoding encoding) +{ +#if 0 + // ARM pseudo code... + if ConditionPassed() then + EncodingSpecificOperations(); + result = R[n] AND imm32; + APSR.N = result<31>; + APSR.Z = IsZeroBit(result); + APSR.C = carry; + // APSR.V unchanged +#endif + + bool success = false; + const uint32_t opcode = OpcodeAsUnsigned (&success); + if (!success) + return false; + + if (ConditionPassed()) + { + uint32_t Rn; + uint32_t imm32; // the immediate value to be ANDed to the value obtained from Rn + uint32_t carry; // the carry bit after ARM/Thumb Expand operation + switch (encoding) + { + case eEncodingT1: + Rn = Bits32(opcode, 19, 16); + imm32 = ThumbExpandImm_C(opcode, APSR_C, carry); // (imm32, carry) = ThumbExpandImm(i:imm3:imm8, APSR.C) + if (BadReg(Rn)) + return false; + break; + case eEncodingA1: + Rn = Bits32(opcode, 19, 16); + imm32 = ARMExpandImm_C(opcode, APSR_C, carry); // (imm32, carry) = ARMExpandImm(imm12, APSR.C) + break; + default: + return false; + } + + // Read the first operand. + uint32_t val1 = ReadCoreReg(Rn, &success); + if (!success) + return false; + + uint32_t result = val1 & imm32; + + EmulateInstruction::Context context; + context.type = EmulateInstruction::eContextImmediate; + context.SetNoArgs (); + + if (!WriteFlags(context, result, carry)) + return false; + } + return true; +} + +// Test (register) performs a bitwise AND operation on a register value and an optionally-shifted register value. +// It updates the condition flags based on the result, and discards the result. +bool +EmulateInstructionARM::EmulateTSTReg (ARMEncoding encoding) +{ +#if 0 + // ARM pseudo code... + if ConditionPassed() then + EncodingSpecificOperations(); + (shifted, carry) = Shift_C(R[m], shift_t, shift_n, APSR.C); + result = R[n] AND shifted; + APSR.N = result<31>; + APSR.Z = IsZeroBit(result); + APSR.C = carry; + // APSR.V unchanged +#endif + + bool success = false; + const uint32_t opcode = OpcodeAsUnsigned (&success); + if (!success) + return false; + + if (ConditionPassed()) + { + uint32_t Rn, Rm; + ARM_ShifterType shift_t; + uint32_t shift_n; // the shift applied to the value read from Rm + uint32_t carry; + switch (encoding) + { + case eEncodingT1: + Rn = Bits32(opcode, 2, 0); + Rm = Bits32(opcode, 5, 3); + shift_t = SRType_LSL; + shift_n = 0; + case eEncodingT2: + Rn = Bits32(opcode, 19, 16); + Rm = Bits32(opcode, 3, 0); + shift_n = DecodeImmShift(Bits32(opcode, 5, 4), Bits32(opcode, 14, 12)<<2 | Bits32(opcode, 7, 6), shift_t); + if (BadReg(Rn) || BadReg(Rm)) + return false; + break; + case eEncodingA1: + Rn = Bits32(opcode, 19, 16); + Rm = Bits32(opcode, 3, 0); + shift_n = DecodeImmShift(Bits32(opcode, 6, 5), Bits32(opcode, 11, 7), shift_t); + break; + default: + return false; + } + + // Read the first operand. + uint32_t val1 = ReadCoreReg(Rn, &success); + if (!success) + return false; + + // Read the second operand. + uint32_t val2 = ReadCoreReg(Rm, &success); + if (!success) + return false; + + uint32_t shifted = Shift_C(val2, shift_t, shift_n, APSR_C, carry); + uint32_t result = val1 & shifted; + + EmulateInstruction::Context context; + context.type = EmulateInstruction::eContextImmediate; + context.SetNoArgs (); + + if (!WriteFlags(context, result, carry)) + return false; + } + return true; +} + EmulateInstructionARM::ARMOpcode* EmulateInstructionARM::GetARMOpcodeForInstruction (const uint32_t opcode) { @@ -5547,6 +5680,12 @@ { 0x0fe00000, 0x03800000, ARMvAll, eEncodingA1, eSize32, &EmulateInstructionARM::EmulateORRImm, "orr{s} , , #const"}, // orr (register) { 0x0fe00010, 0x01800000, ARMvAll, eEncodingA1, eSize32, &EmulateInstructionARM::EmulateORRReg, "orr{s} , , {,}"}, + // tst (immediate) + { 0x0ff0f000, 0x03100000, ARMvAll, eEncodingA1, eSize32, &EmulateInstructionARM::EmulateTSTImm, "tst , #const"}, + // tst (register) + { 0x0ff0f010, 0x01100000, ARMvAll, eEncodingA1, eSize32, &EmulateInstructionARM::EmulateTSTReg, "tst , {,}"}, + + // move bitwise not { 0x0fef0000, 0x03e00000, ARMvAll, eEncodingA1, eSize32, &EmulateInstructionARM::EmulateMVNRdImm, "mvn{s} , #"}, // asr (immediate) @@ -5703,6 +5842,12 @@ // orr (register) { 0xffffffc0, 0x00004300, ARMvAll, eEncodingT1, eSize16, &EmulateInstructionARM::EmulateORRReg, "orrs|orr , "}, { 0xffe08000, 0xea400000, ARMV6T2_ABOVE, eEncodingT2, eSize32, &EmulateInstructionARM::EmulateORRReg, "orr{s}.w , , {,}"}, + // tst (immediate) + { 0xfbf08f00, 0xf0100f00, ARMV6T2_ABOVE, eEncodingT1, eSize32, &EmulateInstructionARM::EmulateTSTImm, "tsts} , #"}, + // tst (register) + { 0xffffffc0, 0x00004200, ARMvAll, eEncodingT1, eSize16, &EmulateInstructionARM::EmulateTSTReg, "tst , "}, + { 0xfff08f00, 0xea100f00, ARMV6T2_ABOVE, eEncodingT2, eSize32, &EmulateInstructionARM::EmulateTSTReg, "tst.w , {,}"}, + // move from high register to high register { 0xffffff00, 0x00004600, ARMvAll, eEncodingT1, eSize16, &EmulateInstructionARM::EmulateMOVRdRm, "mov , "}, Modified: lldb/trunk/source/Plugins/Instruction/ARM/EmulateInstructionARM.h URL: http://llvm.org/viewvc/llvm-project/lldb/trunk/source/Plugins/Instruction/ARM/EmulateInstructionARM.h?rev=126144&r1=126143&r2=126144&view=diff ============================================================================== --- lldb/trunk/source/Plugins/Instruction/ARM/EmulateInstructionARM.h (original) +++ lldb/trunk/source/Plugins/Instruction/ARM/EmulateInstructionARM.h Mon Feb 21 15:24:49 2011 @@ -707,11 +707,11 @@ // A8.6.230 TST (immediate) - Encoding A1 bool - EmulateTSTImmediate (ARMEncoding encoding); + EmulateTSTImm (ARMEncoding encoding); // A8.6.231 TST (register) - Encoding T1, A1 bool - EmulateTSTRegister (ARMEncoding encoding); + EmulateTSTReg (ARMEncoding encoding); // A8.6.262 UXTB - Encoding T1 bool From johnny.chen at apple.com Mon Feb 21 17:42:44 2011 From: johnny.chen at apple.com (Johnny Chen) Date: Mon, 21 Feb 2011 23:42:44 -0000 Subject: [Lldb-commits] [lldb] r126160 - in /lldb/trunk/source/Plugins/Instruction/ARM: EmulateInstructionARM.cpp EmulateInstructionARM.h Message-ID: <20110221234244.E91A62A6C12C@llvm.org> Author: johnny Date: Mon Feb 21 17:42:44 2011 New Revision: 126160 URL: http://llvm.org/viewvc/llvm-project?rev=126160&view=rev Log: Add emulation methods for "EOR (Immediate)", "EOR (register)", "TEQ (immediate)", and "TEQ (register)" operations. Modified: lldb/trunk/source/Plugins/Instruction/ARM/EmulateInstructionARM.cpp lldb/trunk/source/Plugins/Instruction/ARM/EmulateInstructionARM.h Modified: lldb/trunk/source/Plugins/Instruction/ARM/EmulateInstructionARM.cpp URL: http://llvm.org/viewvc/llvm-project/lldb/trunk/source/Plugins/Instruction/ARM/EmulateInstructionARM.cpp?rev=126160&r1=126159&r2=126160&view=diff ============================================================================== --- lldb/trunk/source/Plugins/Instruction/ARM/EmulateInstructionARM.cpp (original) +++ lldb/trunk/source/Plugins/Instruction/ARM/EmulateInstructionARM.cpp Mon Feb 21 17:42:44 2011 @@ -5302,6 +5302,176 @@ return true; } +// Bitwise Exclusive OR (immediate) performs a bitwise exclusive OR of a register value and an immediate value, +// and writes the result to the destination register. It can optionally update the condition flags based on +// the result. +bool +EmulateInstructionARM::EmulateEORImm (ARMEncoding encoding) +{ +#if 0 + // ARM pseudo code... + if ConditionPassed() then + EncodingSpecificOperations(); + result = R[n] EOR imm32; + if d == 15 then // Can only occur for ARM encoding + ALUWritePC(result); // setflags is always FALSE here + else + R[d] = result; + if setflags then + APSR.N = result<31>; + APSR.Z = IsZeroBit(result); + APSR.C = carry; + // APSR.V unchanged +#endif + + bool success = false; + const uint32_t opcode = OpcodeAsUnsigned (&success); + if (!success) + return false; + + if (ConditionPassed()) + { + uint32_t Rd, Rn; + uint32_t imm32; // the immediate value to be ORed to the value obtained from Rn + bool setflags; + uint32_t carry; // the carry bit after ARM/Thumb Expand operation + switch (encoding) + { + case eEncodingT1: + Rd = Bits32(opcode, 11, 8); + Rn = Bits32(opcode, 19, 16); + setflags = BitIsSet(opcode, 20); + imm32 = ThumbExpandImm_C(opcode, APSR_C, carry); // (imm32, carry) = ThumbExpandImm(i:imm3:imm8, APSR.C) + // if Rd == '1111' && S == '1' then SEE TEQ (immediate); + if (Rd == 15 && setflags) + return EmulateTEQImm(eEncodingT1); + if (Rd == 13 || (Rd == 15 && !setflags) || BadReg(Rn)) + return false; + break; + case eEncodingA1: + Rd = Bits32(opcode, 15, 12); + Rn = Bits32(opcode, 19, 16); + setflags = BitIsSet(opcode, 20); + imm32 = ARMExpandImm_C(opcode, APSR_C, carry); // (imm32, carry) = ARMExpandImm(imm12, APSR.C) + // if Rd == '1111' && S == '1' then SEE SUBS PC, LR and related instructions; + // TODO: Emulate SUBS PC, LR and related instructions. + if (Rd == 15 && setflags) + return false; + break; + default: + return false; + } + + // Read the first operand. + uint32_t val1 = ReadCoreReg(Rn, &success); + if (!success) + return false; + + uint32_t result = val1 ^ imm32; + + EmulateInstruction::Context context; + context.type = EmulateInstruction::eContextImmediate; + context.SetNoArgs (); + + if (!WriteCoreRegOptionalFlags(context, result, Rd, setflags, carry)) + return false; + } + return true; +} + +// Bitwise Exclusive OR (register) performs a bitwise exclusive OR of a register value and an +// optionally-shifted register value, and writes the result to the destination register. +// It can optionally update the condition flags based on the result. +bool +EmulateInstructionARM::EmulateEORReg (ARMEncoding encoding) +{ +#if 0 + // ARM pseudo code... + if ConditionPassed() then + EncodingSpecificOperations(); + (shifted, carry) = Shift_C(R[m], shift_t, shift_n, APSR.C); + result = R[n] EOR shifted; + if d == 15 then // Can only occur for ARM encoding + ALUWritePC(result); // setflags is always FALSE here + else + R[d] = result; + if setflags then + APSR.N = result<31>; + APSR.Z = IsZeroBit(result); + APSR.C = carry; + // APSR.V unchanged +#endif + + bool success = false; + const uint32_t opcode = OpcodeAsUnsigned (&success); + if (!success) + return false; + + if (ConditionPassed()) + { + uint32_t Rd, Rn, Rm; + ARM_ShifterType shift_t; + uint32_t shift_n; // the shift applied to the value read from Rm + bool setflags; + uint32_t carry; + switch (encoding) + { + case eEncodingT1: + Rd = Rn = Bits32(opcode, 2, 0); + Rm = Bits32(opcode, 5, 3); + setflags = !InITBlock(); + shift_t = SRType_LSL; + shift_n = 0; + case eEncodingT2: + Rd = Bits32(opcode, 11, 8); + Rn = Bits32(opcode, 19, 16); + Rm = Bits32(opcode, 3, 0); + setflags = BitIsSet(opcode, 20); + shift_n = DecodeImmShift(Bits32(opcode, 5, 4), Bits32(opcode, 14, 12)<<2 | Bits32(opcode, 7, 6), shift_t); + // if Rd == ???1111??? && S == ???1??? then SEE TEQ (register); + if (Rd == 15 && setflags) + return EmulateTEQReg(eEncodingT1); + if (Rd == 13 || (Rd == 15 && !setflags) || BadReg(Rn) || BadReg(Rm)) + return false; + break; + case eEncodingA1: + Rd = Bits32(opcode, 15, 12); + Rn = Bits32(opcode, 19, 16); + Rm = Bits32(opcode, 3, 0); + setflags = BitIsSet(opcode, 20); + shift_n = DecodeImmShift(Bits32(opcode, 6, 5), Bits32(opcode, 11, 7), shift_t); + // if Rd == '1111' && S == '1' then SEE SUBS PC, LR and related instructions; + // TODO: Emulate SUBS PC, LR and related instructions. + if (Rd == 15 && setflags) + return false; + break; + default: + return false; + } + + // Read the first operand. + uint32_t val1 = ReadCoreReg(Rn, &success); + if (!success) + return false; + + // Read the second operand. + uint32_t val2 = ReadCoreReg(Rm, &success); + if (!success) + return false; + + uint32_t shifted = Shift_C(val2, shift_t, shift_n, APSR_C, carry); + uint32_t result = val1 ^ shifted; + + EmulateInstruction::Context context; + context.type = EmulateInstruction::eContextImmediate; + context.SetNoArgs (); + + if (!WriteCoreRegOptionalFlags(context, result, Rd, setflags, carry)) + return false; + } + return true; +} + // Bitwise OR (immediate) performs a bitwise (inclusive) OR of a register value and an immediate value, and // writes the result to the destination register. It can optionally update the condition flags based // on the result. @@ -5458,7 +5628,7 @@ return false; uint32_t shifted = Shift_C(val2, shift_t, shift_n, APSR_C, carry); - uint32_t result = val1 & shifted; + uint32_t result = val1 | shifted; EmulateInstruction::Context context; context.type = EmulateInstruction::eContextImmediate; @@ -5470,6 +5640,135 @@ return true; } +// Test Equivalence (immediate) performs a bitwise exclusive OR operation on a register value and an +// immediate value. It updates the condition flags based on the result, and discards the result. +bool +EmulateInstructionARM::EmulateTEQImm (ARMEncoding encoding) +{ +#if 0 + // ARM pseudo code... + if ConditionPassed() then + EncodingSpecificOperations(); + result = R[n] EOR imm32; + APSR.N = result<31>; + APSR.Z = IsZeroBit(result); + APSR.C = carry; + // APSR.V unchanged +#endif + + bool success = false; + const uint32_t opcode = OpcodeAsUnsigned (&success); + if (!success) + return false; + + if (ConditionPassed()) + { + uint32_t Rn; + uint32_t imm32; // the immediate value to be ANDed to the value obtained from Rn + uint32_t carry; // the carry bit after ARM/Thumb Expand operation + switch (encoding) + { + case eEncodingT1: + Rn = Bits32(opcode, 19, 16); + imm32 = ThumbExpandImm_C(opcode, APSR_C, carry); // (imm32, carry) = ThumbExpandImm(i:imm3:imm8, APSR.C) + if (BadReg(Rn)) + return false; + break; + case eEncodingA1: + Rn = Bits32(opcode, 19, 16); + imm32 = ARMExpandImm_C(opcode, APSR_C, carry); // (imm32, carry) = ARMExpandImm(imm12, APSR.C) + break; + default: + return false; + } + + // Read the first operand. + uint32_t val1 = ReadCoreReg(Rn, &success); + if (!success) + return false; + + uint32_t result = val1 ^ imm32; + + EmulateInstruction::Context context; + context.type = EmulateInstruction::eContextImmediate; + context.SetNoArgs (); + + if (!WriteFlags(context, result, carry)) + return false; + } + return true; +} + +// Test Equivalence (register) performs a bitwise exclusive OR operation on a register value and an +// optionally-shifted register value. It updates the condition flags based on the result, and discards +// the result. +bool +EmulateInstructionARM::EmulateTEQReg (ARMEncoding encoding) +{ +#if 0 + // ARM pseudo code... + if ConditionPassed() then + EncodingSpecificOperations(); + (shifted, carry) = Shift_C(R[m], shift_t, shift_n, APSR.C); + result = R[n] EOR shifted; + APSR.N = result<31>; + APSR.Z = IsZeroBit(result); + APSR.C = carry; + // APSR.V unchanged +#endif + + bool success = false; + const uint32_t opcode = OpcodeAsUnsigned (&success); + if (!success) + return false; + + if (ConditionPassed()) + { + uint32_t Rn, Rm; + ARM_ShifterType shift_t; + uint32_t shift_n; // the shift applied to the value read from Rm + uint32_t carry; + switch (encoding) + { + case eEncodingT1: + Rn = Bits32(opcode, 19, 16); + Rm = Bits32(opcode, 3, 0); + shift_n = DecodeImmShift(Bits32(opcode, 5, 4), Bits32(opcode, 14, 12)<<2 | Bits32(opcode, 7, 6), shift_t); + if (BadReg(Rn) || BadReg(Rm)) + return false; + break; + case eEncodingA1: + Rn = Bits32(opcode, 19, 16); + Rm = Bits32(opcode, 3, 0); + shift_n = DecodeImmShift(Bits32(opcode, 6, 5), Bits32(opcode, 11, 7), shift_t); + break; + default: + return false; + } + + // Read the first operand. + uint32_t val1 = ReadCoreReg(Rn, &success); + if (!success) + return false; + + // Read the second operand. + uint32_t val2 = ReadCoreReg(Rm, &success); + if (!success) + return false; + + uint32_t shifted = Shift_C(val2, shift_t, shift_n, APSR_C, carry); + uint32_t result = val1 ^ shifted; + + EmulateInstruction::Context context; + context.type = EmulateInstruction::eContextImmediate; + context.SetNoArgs (); + + if (!WriteFlags(context, result, carry)) + return false; + } + return true; +} + // Test (immediate) performs a bitwise AND operation on a register value and an immediate value. // It updates the condition flags based on the result, and discards the result. bool @@ -5676,10 +5975,18 @@ { 0x0fe00000, 0x02000000, ARMvAll, eEncodingA1, eSize32, &EmulateInstructionARM::EmulateANDImm, "and{s} , , #const"}, // and (register) { 0x0fe00010, 0x00000000, ARMvAll, eEncodingA1, eSize32, &EmulateInstructionARM::EmulateANDReg, "and{s} , , {,}"}, + // eor (immediate) + { 0x0fe00000, 0x02200000, ARMvAll, eEncodingA1, eSize32, &EmulateInstructionARM::EmulateEORImm, "eor{s} , , #const"}, + // eor (register) + { 0x0fe00010, 0x00200000, ARMvAll, eEncodingA1, eSize32, &EmulateInstructionARM::EmulateEORReg, "eor{s} , , {,}"}, // orr (immediate) { 0x0fe00000, 0x03800000, ARMvAll, eEncodingA1, eSize32, &EmulateInstructionARM::EmulateORRImm, "orr{s} , , #const"}, // orr (register) { 0x0fe00010, 0x01800000, ARMvAll, eEncodingA1, eSize32, &EmulateInstructionARM::EmulateORRReg, "orr{s} , , {,}"}, + // teq (immediate) + { 0x0ff0f000, 0x03300000, ARMvAll, eEncodingA1, eSize32, &EmulateInstructionARM::EmulateTEQImm, "teq , #const"}, + // teq (register) + { 0x0ff0f010, 0x01300000, ARMvAll, eEncodingA1, eSize32, &EmulateInstructionARM::EmulateTEQReg, "teq , {,}"}, // tst (immediate) { 0x0ff0f000, 0x03100000, ARMvAll, eEncodingA1, eSize32, &EmulateInstructionARM::EmulateTSTImm, "tst , #const"}, // tst (register) @@ -5837,13 +6144,22 @@ // and (register) { 0xffffffc0, 0x00004000, ARMvAll, eEncodingT1, eSize16, &EmulateInstructionARM::EmulateANDReg, "ands|and , "}, { 0xffe08000, 0xea000000, ARMV6T2_ABOVE, eEncodingT2, eSize32, &EmulateInstructionARM::EmulateANDReg, "and{s}.w , , {,}"}, + // eor (immediate) + { 0xfbe08000, 0xf0800000, ARMV6T2_ABOVE, eEncodingT1, eSize32, &EmulateInstructionARM::EmulateEORImm, "eor{s} , , #"}, + // eor (register) + { 0xffffffc0, 0x00004040, ARMvAll, eEncodingT1, eSize16, &EmulateInstructionARM::EmulateEORReg, "eors|eor , "}, + { 0xffe08000, 0xea800000, ARMV6T2_ABOVE, eEncodingT2, eSize32, &EmulateInstructionARM::EmulateEORReg, "eor{s}.w , , {,}"}, // orr (immediate) { 0xfbe08000, 0xf0400000, ARMV6T2_ABOVE, eEncodingT1, eSize32, &EmulateInstructionARM::EmulateORRImm, "orr{s} , , #"}, // orr (register) { 0xffffffc0, 0x00004300, ARMvAll, eEncodingT1, eSize16, &EmulateInstructionARM::EmulateORRReg, "orrs|orr , "}, { 0xffe08000, 0xea400000, ARMV6T2_ABOVE, eEncodingT2, eSize32, &EmulateInstructionARM::EmulateORRReg, "orr{s}.w , , {,}"}, + // teq (immediate) + { 0xfbf08f00, 0xf0900f00, ARMV6T2_ABOVE, eEncodingT1, eSize32, &EmulateInstructionARM::EmulateTEQImm, "teq , #"}, + // teq (register) + { 0xfff08f00, 0xea900f00, ARMV6T2_ABOVE, eEncodingT1, eSize32, &EmulateInstructionARM::EmulateTEQReg, "teq , {,}"}, // tst (immediate) - { 0xfbf08f00, 0xf0100f00, ARMV6T2_ABOVE, eEncodingT1, eSize32, &EmulateInstructionARM::EmulateTSTImm, "tsts} , #"}, + { 0xfbf08f00, 0xf0100f00, ARMV6T2_ABOVE, eEncodingT1, eSize32, &EmulateInstructionARM::EmulateTSTImm, "tst , #"}, // tst (register) { 0xffffffc0, 0x00004200, ARMvAll, eEncodingT1, eSize16, &EmulateInstructionARM::EmulateTSTReg, "tst , "}, { 0xfff08f00, 0xea100f00, ARMV6T2_ABOVE, eEncodingT2, eSize32, &EmulateInstructionARM::EmulateTSTReg, "tst.w , {,}"}, Modified: lldb/trunk/source/Plugins/Instruction/ARM/EmulateInstructionARM.h URL: http://llvm.org/viewvc/llvm-project/lldb/trunk/source/Plugins/Instruction/ARM/EmulateInstructionARM.h?rev=126160&r1=126159&r2=126160&view=diff ============================================================================== --- lldb/trunk/source/Plugins/Instruction/ARM/EmulateInstructionARM.h (original) +++ lldb/trunk/source/Plugins/Instruction/ARM/EmulateInstructionARM.h Mon Feb 21 17:42:44 2011 @@ -563,11 +563,11 @@ // A8.6.44 EOR (immediate) bool - EmulateEORImmediate (ARMEncoding encoding); + EmulateEORImm (ARMEncoding encoding); // A8.6.45 EOR (register) bool - EmulateEORegister (ARMEncoding encoding); + EmulateEORReg (ARMEncoding encoding); // A8.6.58 LDR (immediate, ARM) - Encoding A1 bool @@ -699,11 +699,11 @@ // A8.6.227 TEQ (immediate) - Encoding A1 bool - EmulateTEQImmediate (ARMEncoding encoding); + EmulateTEQImm (ARMEncoding encoding); // A8.6.228 TEQ (register) - Encoding A1 bool - EmulateTEQRegister (ARMEncoding encoding); + EmulateTEQReg (ARMEncoding encoding); // A8.6.230 TST (immediate) - Encoding A1 bool From johnny.chen at apple.com Mon Feb 21 19:01:04 2011 From: johnny.chen at apple.com (Johnny Chen) Date: Tue, 22 Feb 2011 01:01:04 -0000 Subject: [Lldb-commits] [lldb] r126172 - in /lldb/trunk/source/Plugins/Instruction/ARM: EmulateInstructionARM.cpp EmulateInstructionARM.h Message-ID: <20110222010104.2A0562A6C12C@llvm.org> Author: johnny Date: Mon Feb 21 19:01:03 2011 New Revision: 126172 URL: http://llvm.org/viewvc/llvm-project?rev=126172&view=rev Log: Add emulation methods for "MVN (immediate)" and "MVN (register)". Modified: lldb/trunk/source/Plugins/Instruction/ARM/EmulateInstructionARM.cpp lldb/trunk/source/Plugins/Instruction/ARM/EmulateInstructionARM.h Modified: lldb/trunk/source/Plugins/Instruction/ARM/EmulateInstructionARM.cpp URL: http://llvm.org/viewvc/llvm-project/lldb/trunk/source/Plugins/Instruction/ARM/EmulateInstructionARM.cpp?rev=126172&r1=126171&r2=126172&view=diff ============================================================================== --- lldb/trunk/source/Plugins/Instruction/ARM/EmulateInstructionARM.cpp (original) +++ lldb/trunk/source/Plugins/Instruction/ARM/EmulateInstructionARM.cpp Mon Feb 21 19:01:03 2011 @@ -714,12 +714,10 @@ return true; } -// Bitwise NOT (immediate) writes the bitwise inverse of an immediate value to -// the destination register. It can optionally update the condition flags based -// on the value. -// MVN (immediate) +// Bitwise NOT (immediate) writes the bitwise inverse of an immediate value to the destination register. +// It can optionally update the condition flags based on the value. bool -EmulateInstructionARM::EmulateMVNRdImm (ARMEncoding encoding) +EmulateInstructionARM::EmulateMVNImm (ARMEncoding encoding) { #if 0 // ARM pseudo code... @@ -746,7 +744,6 @@ if (ConditionPassed()) { uint32_t Rd; // the destination register - uint32_t imm12; // the first operand to ThumbExpandImm_C or ARMExpandImm_C uint32_t imm32; // the output after ThumbExpandImm_C or ARMExpandImm_C uint32_t carry; // the carry bit after ThumbExpandImm_C or ARMExpandImm_C bool setflags; @@ -754,14 +751,16 @@ case eEncodingT1: Rd = Bits32(opcode, 11, 8); setflags = BitIsSet(opcode, 20); - imm12 = Bit32(opcode, 26) << 11 | Bits32(opcode, 14, 12) << 8 | Bits32(opcode, 7, 0); - imm32 = ThumbExpandImm_C(imm12, APSR_C, carry); + imm32 = ThumbExpandImm_C(opcode, APSR_C, carry); break; case eEncodingA1: Rd = Bits32(opcode, 15, 12); setflags = BitIsSet(opcode, 20); - imm12 = Bits32(opcode, 11, 0); - imm32 = ARMExpandImm_C(imm12, APSR_C, carry); + imm32 = ARMExpandImm_C(opcode, APSR_C, carry); + // if Rd == '1111' && S == '1' then SEE SUBS PC, LR and related instructions; + // TODO: Emulate SUBS PC, LR and related instructions. + if (Rd == 15 && setflags) + return false; break; default: return false; @@ -779,6 +778,88 @@ return true; } +// Bitwise NOT (register) writes the bitwise inverse of a register value to the destination register. +// It can optionally update the condition flags based on the result. +bool +EmulateInstructionARM::EmulateMVNReg (ARMEncoding encoding) +{ +#if 0 + // ARM pseudo code... + if (ConditionPassed()) + { + EncodingSpecificOperations(); + (shifted, carry) = Shift_C(R[m], shift_t, shift_n, APSR.C); + result = NOT(shifted); + if d == 15 then // Can only occur for ARM encoding + ALUWritePC(result); // setflags is always FALSE here + else + R[d] = result; + if setflags then + APSR.N = result<31>; + APSR.Z = IsZeroBit(result); + APSR.C = carry; + // APSR.V unchanged + } +#endif + + bool success = false; + const uint32_t opcode = OpcodeAsUnsigned (&success); + if (!success) + return false; + + if (ConditionPassed()) + { + uint32_t Rm; // the source register + uint32_t Rd; // the destination register + ARM_ShifterType shift_t; + uint32_t shift_n; // the shift applied to the value read from Rm + bool setflags; + uint32_t carry; // the carry bit after the shift operation + switch (encoding) { + case eEncodingT1: + Rd = Bits32(opcode, 2, 0); + Rm = Bits32(opcode, 5, 3); + setflags = !InITBlock(); + shift_t = SRType_LSL; + shift_n = 0; + if (InITBlock()) + return false; + break; + case eEncodingT2: + Rd = Bits32(opcode, 11, 8); + Rm = Bits32(opcode, 3, 0); + setflags = BitIsSet(opcode, 20); + shift_n = DecodeImmShift(Bits32(opcode, 5, 4), Bits32(opcode, 14, 12)<<2 | Bits32(opcode, 7, 6), shift_t); + // if (BadReg(d) || BadReg(m)) then UNPREDICTABLE; + if ((BadReg(Rd) || BadReg(Rm))) + return false; + case eEncodingA1: + Rd = Bits32(opcode, 15, 12); + Rm = Bits32(opcode, 3, 0); + setflags = BitIsSet(opcode, 20); + shift_n = DecodeImmShift(Bits32(opcode, 6, 5), Bits32(opcode, 11, 7), shift_t); + break; + default: + return false; + } + uint32_t value = ReadCoreReg(Rm, &success); + if (!success) + return false; + + uint32_t shifted = Shift_C(value, shift_t, shift_n, APSR_C, carry); + uint32_t result = ~shifted; + + // The context specifies that an immediate is to be moved into Rd. + EmulateInstruction::Context context; + context.type = EmulateInstruction::eContextImmediate; + context.SetNoArgs (); + + if (!WriteCoreRegOptionalFlags(context, result, Rd, setflags, carry)) + return false; + } + return true; +} + // PC relative immediate load into register, possibly followed by ADD (SP plus register). // LDR (literal) bool @@ -5993,8 +6074,10 @@ { 0x0ff0f010, 0x01100000, ARMvAll, eEncodingA1, eSize32, &EmulateInstructionARM::EmulateTSTReg, "tst , {,}"}, - // move bitwise not - { 0x0fef0000, 0x03e00000, ARMvAll, eEncodingA1, eSize32, &EmulateInstructionARM::EmulateMVNRdImm, "mvn{s} , #"}, + // mvn (immediate) + { 0x0fef0000, 0x03e00000, ARMvAll, eEncodingA1, eSize32, &EmulateInstructionARM::EmulateMVNImm, "mvn{s} , #"}, + // mvn (register) + { 0x0fef0010, 0x01e00000, ARMvAll, eEncodingA1, eSize32, &EmulateInstructionARM::EmulateMVNReg, "mvn{s} , {,}"}, // asr (immediate) { 0x0fef0070, 0x01a00040, ARMvAll, eEncodingA1, eSize32, &EmulateInstructionARM::EmulateASRImm, "asr{s} , , #imm"}, // asr (register) @@ -6174,8 +6257,11 @@ // move immediate { 0xfffff800, 0x00002000, ARMvAll, eEncodingT1, eSize16, &EmulateInstructionARM::EmulateMOVRdImm, "movs|mov , #imm8"}, { 0xfbef8000, 0xf04f0000, ARMV6T2_ABOVE, eEncodingT2, eSize32, &EmulateInstructionARM::EmulateMOVRdImm, "mov{s}.w , #"}, - // move bitwise not - { 0xfbef8000, 0xf06f0000, ARMV6T2_ABOVE, eEncodingT1, eSize32, &EmulateInstructionARM::EmulateMVNRdImm, "mvn{s} , #"}, + // mvn (immediate) + { 0xfbef8000, 0xf06f0000, ARMV6T2_ABOVE, eEncodingT1, eSize32, &EmulateInstructionARM::EmulateMVNImm, "mvn{s} , #"}, + // mvn (register) + { 0xffffffc0, 0x000043c0, ARMvAll, eEncodingT1, eSize16, &EmulateInstructionARM::EmulateMVNReg, "mvns|mvn , "}, + { 0xffef8000, 0xea6f0000, ARMV6T2_ABOVE, eEncodingT2, eSize32, &EmulateInstructionARM::EmulateMVNReg, "mvn{s}.w , {,}"}, // compare a register with immediate { 0xfffff800, 0x00002800, ARMvAll, eEncodingT1, eSize16, &EmulateInstructionARM::EmulateCMPRnImm, "cmp , #imm8"}, // compare Rn with Rm (Rn and Rm both from r0-r7) Modified: lldb/trunk/source/Plugins/Instruction/ARM/EmulateInstructionARM.h URL: http://llvm.org/viewvc/llvm-project/lldb/trunk/source/Plugins/Instruction/ARM/EmulateInstructionARM.h?rev=126172&r1=126171&r2=126172&view=diff ============================================================================== --- lldb/trunk/source/Plugins/Instruction/ARM/EmulateInstructionARM.h (original) +++ lldb/trunk/source/Plugins/Instruction/ARM/EmulateInstructionARM.h Mon Feb 21 19:01:03 2011 @@ -417,10 +417,6 @@ bool EmulateMOVRdImm (ARMEncoding encoding); - // A8.6.106 MVN (immediate) - bool - EmulateMVNRdImm (ARMEncoding encoding); - // A8.6.35 CMP (immediate) bool EmulateCMPRnImm (ARMEncoding encoding); @@ -629,9 +625,13 @@ bool EmulateMUL (ARMEncoding encoding); - // A8.6.107 MVN (register) - Encoding T1, A1 + // A8.6.106 MVN (immediate) + bool + EmulateMVNImm (ARMEncoding encoding); + + // A8.6.107 MVN (register) bool - EmulateMVNRegister (ARMEncoding encoding); + EmulateMVNReg (ARMEncoding encoding); // A8.6.113 ORR (immediate) bool From johnny.chen at apple.com Mon Feb 21 19:56:31 2011 From: johnny.chen at apple.com (Johnny Chen) Date: Tue, 22 Feb 2011 01:56:31 -0000 Subject: [Lldb-commits] [lldb] r126178 - in /lldb/trunk/source/Plugins/Instruction/ARM: EmulateInstructionARM.cpp EmulateInstructionARM.h Message-ID: <20110222015631.B621D2A6C12C@llvm.org> Author: johnny Date: Mon Feb 21 19:56:31 2011 New Revision: 126178 URL: http://llvm.org/viewvc/llvm-project?rev=126178&view=rev Log: Add ARM encoding entries for "CMP (immediate)" and "CMP (register)" operations. Add ARM/Thumb encoding entries for "CMN (immediate)" and "CMN (register)" operations, with the EmulateCMNImm()/Reg() methods not implemented yet for now. Modified: lldb/trunk/source/Plugins/Instruction/ARM/EmulateInstructionARM.cpp lldb/trunk/source/Plugins/Instruction/ARM/EmulateInstructionARM.h Modified: lldb/trunk/source/Plugins/Instruction/ARM/EmulateInstructionARM.cpp URL: http://llvm.org/viewvc/llvm-project/lldb/trunk/source/Plugins/Instruction/ARM/EmulateInstructionARM.cpp?rev=126178&r1=126177&r2=126178&view=diff ============================================================================== --- lldb/trunk/source/Plugins/Instruction/ARM/EmulateInstructionARM.cpp (original) +++ lldb/trunk/source/Plugins/Instruction/ARM/EmulateInstructionARM.cpp Mon Feb 21 19:56:31 2011 @@ -2157,9 +2157,132 @@ return true; } -// CMP (immediate) +// Compare Negative (immediate) adds a register value and an immediate value. +// It updates the condition flags based on the result, and discards the result. +bool +EmulateInstructionARM::EmulateCMNImm (ARMEncoding encoding) +{ +#if 0 + // ARM pseudo code... + if ConditionPassed() then + EncodingSpecificOperations(); + (result, carry, overflow) = AddWithCarry(R[n], imm32, '0'); + APSR.N = result<31>; + APSR.Z = IsZeroBit(result); + APSR.C = carry; + APSR.V = overflow; +#endif + + bool success = false; + const uint32_t opcode = OpcodeAsUnsigned (&success); + if (!success) + return false; + + uint32_t Rn; // the first operand + uint32_t imm32; // the immediate value to be compared with + switch (encoding) { + case eEncodingT1: + Rn = Bits32(opcode, 10, 8); + imm32 = Bits32(opcode, 7, 0); + case eEncodingA1: + Rn = Bits32(opcode, 19, 16); + imm32 = ARMExpandImm(opcode); // imm32 = ARMExpandImm(imm12) + break; + default: + return false; + } + // Read the register value from the operand register Rn. + uint32_t reg_val = ReadCoreReg(Rn, &success); + if (!success) + return false; + + AddWithCarryResult res = AddWithCarry(reg_val, ~imm32, 1); + + EmulateInstruction::Context context; + context.type = EmulateInstruction::eContextImmediate; + context.SetNoArgs (); + if (!WriteFlags(context, res.result, res.carry_out, res.overflow)) + return false; + + return true; +} + +// Compare Negative (register) adds a register value and an optionally-shifted register value. +// It updates the condition flags based on the result, and discards the result. +bool +EmulateInstructionARM::EmulateCMNReg (ARMEncoding encoding) +{ +#if 0 + // ARM pseudo code... + if ConditionPassed() then + EncodingSpecificOperations(); + shifted = Shift(R[m], shift_t, shift_n, APSR.C); + (result, carry, overflow) = AddWithCarry(R[n], shifted, '0'); + APSR.N = result<31>; + APSR.Z = IsZeroBit(result); + APSR.C = carry; + APSR.V = overflow; +#endif + + bool success = false; + const uint32_t opcode = OpcodeAsUnsigned (&success); + if (!success) + return false; + + uint32_t Rn; // the first operand + uint32_t Rm; // the second operand + ARM_ShifterType shift_t; + uint32_t shift_n; // the shift applied to the value read from Rm + switch (encoding) { + case eEncodingT1: + Rn = Bits32(opcode, 2, 0); + Rm = Bits32(opcode, 5, 3); + shift_t = SRType_LSL; + shift_n = 0; + break; + case eEncodingT2: + Rn = Bit32(opcode, 7) << 3 | Bits32(opcode, 2, 0); + Rm = Bits32(opcode, 6, 3); + shift_t = SRType_LSL; + shift_n = 0; + if (Rn < 8 && Rm < 8) + return false; + if (Rn == 15 || Rm == 15) + return false; + break; + case eEncodingA1: + Rn = Bits32(opcode, 19, 16); + Rm = Bits32(opcode, 3, 0); + shift_n = DecodeImmShift(Bits32(opcode, 6, 5), Bits32(opcode, 11, 7), shift_t); + default: + return false; + } + // Read the register value from register Rn. + uint32_t val1 = ReadCoreReg(Rn, &success); + if (!success) + return false; + + // Read the register value from register Rm. + uint32_t val2 = ReadCoreReg(Rm, &success); + if (!success) + return false; + + uint32_t shifted = Shift(val2, shift_t, shift_n, APSR_C); + AddWithCarryResult res = AddWithCarry(val1, ~shifted, 1); + + EmulateInstruction::Context context; + context.type = EmulateInstruction::eContextImmediate; + context.SetNoArgs(); + if (!WriteFlags(context, res.result, res.carry_out, res.overflow)) + return false; + + return true; +} + +// Compare (immediate) subtracts an immediate value from a register value. +// It updates the condition flags based on the result, and discards the result. bool -EmulateInstructionARM::EmulateCMPRnImm (ARMEncoding encoding) +EmulateInstructionARM::EmulateCMPImm (ARMEncoding encoding) { #if 0 // ARM pseudo code... @@ -2183,6 +2306,9 @@ case eEncodingT1: Rn = Bits32(opcode, 10, 8); imm32 = Bits32(opcode, 7, 0); + case eEncodingA1: + Rn = Bits32(opcode, 19, 16); + imm32 = ARMExpandImm(opcode); // imm32 = ARMExpandImm(imm12) break; default: return false; @@ -2203,9 +2329,10 @@ return true; } -// CMP (register) +// Compare (register) subtracts an optionally-shifted register value from a register value. +// It updates the condition flags based on the result, and discards the result. bool -EmulateInstructionARM::EmulateCMPRnRm (ARMEncoding encoding) +EmulateInstructionARM::EmulateCMPReg (ARMEncoding encoding) { #if 0 // ARM pseudo code... @@ -2226,33 +2353,44 @@ uint32_t Rn; // the first operand uint32_t Rm; // the second operand + ARM_ShifterType shift_t; + uint32_t shift_n; // the shift applied to the value read from Rm switch (encoding) { case eEncodingT1: Rn = Bits32(opcode, 2, 0); Rm = Bits32(opcode, 5, 3); + shift_t = SRType_LSL; + shift_n = 0; break; case eEncodingT2: Rn = Bit32(opcode, 7) << 3 | Bits32(opcode, 2, 0); Rm = Bits32(opcode, 6, 3); + shift_t = SRType_LSL; + shift_n = 0; if (Rn < 8 && Rm < 8) return false; if (Rn == 15 || Rm == 15) return false; break; + case eEncodingA1: + Rn = Bits32(opcode, 19, 16); + Rm = Bits32(opcode, 3, 0); + shift_n = DecodeImmShift(Bits32(opcode, 6, 5), Bits32(opcode, 11, 7), shift_t); default: return false; } // Read the register value from register Rn. - uint32_t reg_val1 = ReadCoreReg(Rn, &success); + uint32_t val1 = ReadCoreReg(Rn, &success); if (!success) return false; + // Read the register value from register Rm. - // The register value is not being shifted since we don't handle ARM for now. - uint32_t reg_val2 = ReadCoreReg(Rm, &success); + uint32_t val2 = ReadCoreReg(Rm, &success); if (!success) return false; - AddWithCarryResult res = AddWithCarry(reg_val1, ~reg_val2, 1); + uint32_t shifted = Shift(val2, shift_t, shift_n, APSR_C); + AddWithCarryResult res = AddWithCarry(val1, ~shifted, 1); EmulateInstruction::Context context; context.type = EmulateInstruction::eContextImmediate; @@ -6078,6 +6216,10 @@ { 0x0fef0000, 0x03e00000, ARMvAll, eEncodingA1, eSize32, &EmulateInstructionARM::EmulateMVNImm, "mvn{s} , #"}, // mvn (register) { 0x0fef0010, 0x01e00000, ARMvAll, eEncodingA1, eSize32, &EmulateInstructionARM::EmulateMVNReg, "mvn{s} , {,}"}, + // cmp (immediate) + { 0x0ff0f000, 0x03500000, ARMvAll, eEncodingA1, eSize32, &EmulateInstructionARM::EmulateCMPImm, "cmp , #"}, + // cmp (register) + { 0x0ff0f010, 0x01500000, ARMvAll, eEncodingA1, eSize32, &EmulateInstructionARM::EmulateCMPReg, "cmp , {,}"}, // asr (immediate) { 0x0fef0070, 0x01a00040, ARMvAll, eEncodingA1, eSize32, &EmulateInstructionARM::EmulateASRImm, "asr{s} , , #imm"}, // asr (register) @@ -6262,12 +6404,17 @@ // mvn (register) { 0xffffffc0, 0x000043c0, ARMvAll, eEncodingT1, eSize16, &EmulateInstructionARM::EmulateMVNReg, "mvns|mvn , "}, { 0xffef8000, 0xea6f0000, ARMV6T2_ABOVE, eEncodingT2, eSize32, &EmulateInstructionARM::EmulateMVNReg, "mvn{s}.w , {,}"}, - // compare a register with immediate - { 0xfffff800, 0x00002800, ARMvAll, eEncodingT1, eSize16, &EmulateInstructionARM::EmulateCMPRnImm, "cmp , #imm8"}, - // compare Rn with Rm (Rn and Rm both from r0-r7) - { 0xffffffc0, 0x00004280, ARMvAll, eEncodingT1, eSize16, &EmulateInstructionARM::EmulateCMPRnRm, "cmp , "}, - // compare Rn with Rm (Rn and Rm not both from r0-r7) - { 0xffffff00, 0x00004500, ARMvAll, eEncodingT2, eSize16, &EmulateInstructionARM::EmulateCMPRnRm, "cmp , "}, + // cmn (immediate) + { 0xfbf08f00, 0xf1100f00, ARMvAll, eEncodingT1, eSize32, &EmulateInstructionARM::EmulateCMNImm, "cmn , #"}, + // cmn (register) + { 0xffffffc0, 0x000042c0, ARMvAll, eEncodingT1, eSize16, &EmulateInstructionARM::EmulateCMNReg, "cmn , "}, + { 0xfff08f00, 0xeb100f00, ARMvAll, eEncodingT2, eSize32, &EmulateInstructionARM::EmulateCMNReg, "cmn , {,}"}, + // cmp (immediate) + { 0xfffff800, 0x00002800, ARMvAll, eEncodingT1, eSize16, &EmulateInstructionARM::EmulateCMPImm, "cmp , #imm8"}, + // cmp (register) (Rn and Rm both from r0-r7) + { 0xffffffc0, 0x00004280, ARMvAll, eEncodingT1, eSize16, &EmulateInstructionARM::EmulateCMPReg, "cmp , "}, + // cmp (register) (Rn and Rm not both from r0-r7) + { 0xffffff00, 0x00004500, ARMvAll, eEncodingT2, eSize16, &EmulateInstructionARM::EmulateCMPReg, "cmp , "}, // asr (immediate) { 0xfffff800, 0x00001000, ARMvAll, eEncodingT1, eSize16, &EmulateInstructionARM::EmulateASRImm, "asrs|asr , , #imm"}, { 0xffef8030, 0xea4f0020, ARMV6T2_ABOVE, eEncodingT2, eSize32, &EmulateInstructionARM::EmulateASRImm, "asr{s}.w , , #imm"}, Modified: lldb/trunk/source/Plugins/Instruction/ARM/EmulateInstructionARM.h URL: http://llvm.org/viewvc/llvm-project/lldb/trunk/source/Plugins/Instruction/ARM/EmulateInstructionARM.h?rev=126178&r1=126177&r2=126178&view=diff ============================================================================== --- lldb/trunk/source/Plugins/Instruction/ARM/EmulateInstructionARM.h (original) +++ lldb/trunk/source/Plugins/Instruction/ARM/EmulateInstructionARM.h Mon Feb 21 19:56:31 2011 @@ -419,11 +419,11 @@ // A8.6.35 CMP (immediate) bool - EmulateCMPRnImm (ARMEncoding encoding); + EmulateCMPImm (ARMEncoding encoding); // A8.6.36 CMP (register) bool - EmulateCMPRnRm (ARMEncoding encoding); + EmulateCMPReg (ARMEncoding encoding); // A8.6.14 ASR (immediate) bool @@ -549,13 +549,13 @@ bool EmulateBXJ (ARMEncoding encoding); - // A8.6.32 CMN (immediate) - Encoding A1 + // A8.6.32 CMN (immediate) bool - EmulateCMNImmediate (ARMEncoding encoding); + EmulateCMNImm (ARMEncoding encoding); - // A8.6.33 CMN (register) - Encoding T1, A1 + // A8.6.33 CMN (register) bool - EmulateCMNRegister (ARMEncoding encoding); + EmulateCMNReg (ARMEncoding encoding); // A8.6.44 EOR (immediate) bool From johnny.chen at apple.com Mon Feb 21 20:00:13 2011 From: johnny.chen at apple.com (Johnny Chen) Date: Tue, 22 Feb 2011 02:00:13 -0000 Subject: [Lldb-commits] [lldb] r126179 - /lldb/trunk/source/Plugins/Instruction/ARM/EmulateInstructionARM.cpp Message-ID: <20110222020013.2CFEB2A6C12C@llvm.org> Author: johnny Date: Mon Feb 21 20:00:12 2011 New Revision: 126179 URL: http://llvm.org/viewvc/llvm-project?rev=126179&view=rev Log: Add ARM encoding entries for "CMN (immediate)" and "CMN (register)" operations. Modified: lldb/trunk/source/Plugins/Instruction/ARM/EmulateInstructionARM.cpp Modified: lldb/trunk/source/Plugins/Instruction/ARM/EmulateInstructionARM.cpp URL: http://llvm.org/viewvc/llvm-project/lldb/trunk/source/Plugins/Instruction/ARM/EmulateInstructionARM.cpp?rev=126179&r1=126178&r2=126179&view=diff ============================================================================== --- lldb/trunk/source/Plugins/Instruction/ARM/EmulateInstructionARM.cpp (original) +++ lldb/trunk/source/Plugins/Instruction/ARM/EmulateInstructionARM.cpp Mon Feb 21 20:00:12 2011 @@ -6216,6 +6216,10 @@ { 0x0fef0000, 0x03e00000, ARMvAll, eEncodingA1, eSize32, &EmulateInstructionARM::EmulateMVNImm, "mvn{s} , #"}, // mvn (register) { 0x0fef0010, 0x01e00000, ARMvAll, eEncodingA1, eSize32, &EmulateInstructionARM::EmulateMVNReg, "mvn{s} , {,}"}, + // cmn (immediate) + { 0x0ff0f000, 0x03700000, ARMvAll, eEncodingA1, eSize32, &EmulateInstructionARM::EmulateCMNImm, "cmn , #"}, + // cmn (register) + { 0x0ff0f010, 0x01700000, ARMvAll, eEncodingA1, eSize32, &EmulateInstructionARM::EmulateCMNReg, "cmn , {,}"}, // cmp (immediate) { 0x0ff0f000, 0x03500000, ARMvAll, eEncodingA1, eSize32, &EmulateInstructionARM::EmulateCMPImm, "cmp , #"}, // cmp (register) From johnny.chen at apple.com Tue Feb 22 13:01:12 2011 From: johnny.chen at apple.com (Johnny Chen) Date: Tue, 22 Feb 2011 19:01:12 -0000 Subject: [Lldb-commits] [lldb] r126234 - /lldb/trunk/source/Plugins/Instruction/ARM/EmulateInstructionARM.cpp Message-ID: <20110222190112.2AAD32A6C12C@llvm.org> Author: johnny Date: Tue Feb 22 13:01:11 2011 New Revision: 126234 URL: http://llvm.org/viewvc/llvm-project?rev=126234&view=rev Log: Fix the 'variants' field of "CMN (immediate)" Encoding T1 entry, it should be ARMV6T2_ABOVE, not ARMvAll. Modified: lldb/trunk/source/Plugins/Instruction/ARM/EmulateInstructionARM.cpp Modified: lldb/trunk/source/Plugins/Instruction/ARM/EmulateInstructionARM.cpp URL: http://llvm.org/viewvc/llvm-project/lldb/trunk/source/Plugins/Instruction/ARM/EmulateInstructionARM.cpp?rev=126234&r1=126233&r2=126234&view=diff ============================================================================== --- lldb/trunk/source/Plugins/Instruction/ARM/EmulateInstructionARM.cpp (original) +++ lldb/trunk/source/Plugins/Instruction/ARM/EmulateInstructionARM.cpp Tue Feb 22 13:01:11 2011 @@ -6409,7 +6409,7 @@ { 0xffffffc0, 0x000043c0, ARMvAll, eEncodingT1, eSize16, &EmulateInstructionARM::EmulateMVNReg, "mvns|mvn , "}, { 0xffef8000, 0xea6f0000, ARMV6T2_ABOVE, eEncodingT2, eSize32, &EmulateInstructionARM::EmulateMVNReg, "mvn{s}.w , {,}"}, // cmn (immediate) - { 0xfbf08f00, 0xf1100f00, ARMvAll, eEncodingT1, eSize32, &EmulateInstructionARM::EmulateCMNImm, "cmn , #"}, + { 0xfbf08f00, 0xf1100f00, ARMV6T2_ABOVE, eEncodingT1, eSize32, &EmulateInstructionARM::EmulateCMNImm, "cmn , #"}, // cmn (register) { 0xffffffc0, 0x000042c0, ARMvAll, eEncodingT1, eSize16, &EmulateInstructionARM::EmulateCMNReg, "cmn , "}, { 0xfff08f00, 0xeb100f00, ARMvAll, eEncodingT2, eSize32, &EmulateInstructionARM::EmulateCMNReg, "cmn , {,}"}, From gclayton at apple.com Tue Feb 22 13:32:07 2011 From: gclayton at apple.com (Greg Clayton) Date: Tue, 22 Feb 2011 19:32:07 -0000 Subject: [Lldb-commits] [lldb] r126235 - /lldb/trunk/source/Plugins/Process/Utility/RegisterContextLLDB.cpp Message-ID: <20110222193207.C433A2A6C12C@llvm.org> Author: gclayton Date: Tue Feb 22 13:32:07 2011 New Revision: 126235 URL: http://llvm.org/viewvc/llvm-project?rev=126235&view=rev Log: Remove an assertion that was causing a crash. Modified: lldb/trunk/source/Plugins/Process/Utility/RegisterContextLLDB.cpp Modified: lldb/trunk/source/Plugins/Process/Utility/RegisterContextLLDB.cpp URL: http://llvm.org/viewvc/llvm-project/lldb/trunk/source/Plugins/Process/Utility/RegisterContextLLDB.cpp?rev=126235&r1=126234&r2=126235&view=diff ============================================================================== --- lldb/trunk/source/Plugins/Process/Utility/RegisterContextLLDB.cpp (original) +++ lldb/trunk/source/Plugins/Process/Utility/RegisterContextLLDB.cpp Tue Feb 22 13:32:07 2011 @@ -113,8 +113,18 @@ if (addr_range.GetBaseAddress().IsValid()) { m_start_pc = addr_range.GetBaseAddress(); - assert (frame_sp->GetFrameCodeAddress().GetSection() == m_start_pc.GetSection()); - m_current_offset = frame_sp->GetFrameCodeAddress().GetOffset() - m_start_pc.GetOffset(); + if (frame_sp->GetFrameCodeAddress().GetSection() == m_start_pc.GetSection()) + { + m_current_offset = frame_sp->GetFrameCodeAddress().GetOffset() - m_start_pc.GetOffset(); + } + else if (frame_sp->GetFrameCodeAddress().GetModule() == m_start_pc.GetModule()) + { + // This means that whatever symbol we kicked up isn't really correct + // as no should cross section boundaries... We really should NULL out + // the function/symbol in this case unless there is a bad assumption + // here due to inlined functions? + m_current_offset = frame_sp->GetFrameCodeAddress().GetFileAddress() - m_start_pc.GetFileAddress(); + } m_current_offset_backed_up_one = m_current_offset; } else From johnny.chen at apple.com Tue Feb 22 13:48:23 2011 From: johnny.chen at apple.com (Johnny Chen) Date: Tue, 22 Feb 2011 19:48:23 -0000 Subject: [Lldb-commits] [lldb] r126236 - /lldb/trunk/source/Plugins/Instruction/ARM/EmulateInstructionARM.cpp Message-ID: <20110222194823.20B9B2A6C12C@llvm.org> Author: johnny Date: Tue Feb 22 13:48:22 2011 New Revision: 126236 URL: http://llvm.org/viewvc/llvm-project?rev=126236&view=rev Log: Add "cmp.w , #" emulation to EmulateCMPImm() method, and implement EmulateCMNImm() and EMulateCMNReg() methods. Modified: lldb/trunk/source/Plugins/Instruction/ARM/EmulateInstructionARM.cpp Modified: lldb/trunk/source/Plugins/Instruction/ARM/EmulateInstructionARM.cpp URL: http://llvm.org/viewvc/llvm-project/lldb/trunk/source/Plugins/Instruction/ARM/EmulateInstructionARM.cpp?rev=126236&r1=126235&r2=126236&view=diff ============================================================================== --- lldb/trunk/source/Plugins/Instruction/ARM/EmulateInstructionARM.cpp (original) +++ lldb/trunk/source/Plugins/Instruction/ARM/EmulateInstructionARM.cpp Tue Feb 22 13:48:22 2011 @@ -2182,8 +2182,10 @@ uint32_t imm32; // the immediate value to be compared with switch (encoding) { case eEncodingT1: - Rn = Bits32(opcode, 10, 8); - imm32 = Bits32(opcode, 7, 0); + Rn = Bits32(opcode, 19, 16); + imm32 = ThumbExpandImm(opcode); // imm32 = ThumbExpandImm(i:imm3:imm8) + if (Rn == 15) + return false; case eEncodingA1: Rn = Bits32(opcode, 19, 16); imm32 = ARMExpandImm(opcode); // imm32 = ARMExpandImm(imm12) @@ -2196,7 +2198,7 @@ if (!success) return false; - AddWithCarryResult res = AddWithCarry(reg_val, ~imm32, 1); + AddWithCarryResult res = AddWithCarry(reg_val, imm32, 0); EmulateInstruction::Context context; context.type = EmulateInstruction::eContextImmediate; @@ -2241,13 +2243,11 @@ shift_n = 0; break; case eEncodingT2: - Rn = Bit32(opcode, 7) << 3 | Bits32(opcode, 2, 0); - Rm = Bits32(opcode, 6, 3); - shift_t = SRType_LSL; - shift_n = 0; - if (Rn < 8 && Rm < 8) - return false; - if (Rn == 15 || Rm == 15) + Rn = Bits32(opcode, 19, 16); + Rm = Bits32(opcode, 3, 0); + shift_n = DecodeImmShift(Bits32(opcode, 5, 4), Bits32(opcode, 14, 12)<<2 | Bits32(opcode, 7, 6), shift_t); + // if n == 15 || BadReg(m) then UNPREDICTABLE; + if (Rn == 15 || BadReg(Rm)) return false; break; case eEncodingA1: @@ -2268,7 +2268,7 @@ return false; uint32_t shifted = Shift(val2, shift_t, shift_n, APSR_C); - AddWithCarryResult res = AddWithCarry(val1, ~shifted, 1); + AddWithCarryResult res = AddWithCarry(val1, shifted, 0); EmulateInstruction::Context context; context.type = EmulateInstruction::eContextImmediate; @@ -2306,6 +2306,11 @@ case eEncodingT1: Rn = Bits32(opcode, 10, 8); imm32 = Bits32(opcode, 7, 0); + case eEncodingT2: + Rn = Bits32(opcode, 19, 16); + imm32 = ThumbExpandImm(opcode); // imm32 = ThumbExpandImm(i:imm3:imm8) + if (Rn == 15) + return false; case eEncodingA1: Rn = Bits32(opcode, 19, 16); imm32 = ARMExpandImm(opcode); // imm32 = ARMExpandImm(imm12) @@ -6412,9 +6417,10 @@ { 0xfbf08f00, 0xf1100f00, ARMV6T2_ABOVE, eEncodingT1, eSize32, &EmulateInstructionARM::EmulateCMNImm, "cmn , #"}, // cmn (register) { 0xffffffc0, 0x000042c0, ARMvAll, eEncodingT1, eSize16, &EmulateInstructionARM::EmulateCMNReg, "cmn , "}, - { 0xfff08f00, 0xeb100f00, ARMvAll, eEncodingT2, eSize32, &EmulateInstructionARM::EmulateCMNReg, "cmn , {,}"}, + { 0xfff08f00, 0xeb100f00, ARMV6T2_ABOVE, eEncodingT2, eSize32, &EmulateInstructionARM::EmulateCMNReg, "cmn , {,}"}, // cmp (immediate) { 0xfffff800, 0x00002800, ARMvAll, eEncodingT1, eSize16, &EmulateInstructionARM::EmulateCMPImm, "cmp , #imm8"}, + { 0xfbf08f00, 0xf1b00f00, ARMV6T2_ABOVE, eEncodingT2, eSize32, &EmulateInstructionARM::EmulateCMPImm, "cmp.w , #"}, // cmp (register) (Rn and Rm both from r0-r7) { 0xffffffc0, 0x00004280, ARMvAll, eEncodingT1, eSize16, &EmulateInstructionARM::EmulateCMPReg, "cmp , "}, // cmp (register) (Rn and Rm not both from r0-r7) From johnny.chen at apple.com Tue Feb 22 15:17:52 2011 From: johnny.chen at apple.com (Johnny Chen) Date: Tue, 22 Feb 2011 21:17:52 -0000 Subject: [Lldb-commits] [lldb] r126247 - in /lldb/trunk/source/Plugins: Instruction/ARM/EmulateInstructionARM.cpp Process/Utility/ARMUtils.h Message-ID: <20110222211752.4757C2A6C12C@llvm.org> Author: johnny Date: Tue Feb 22 15:17:52 2011 New Revision: 126247 URL: http://llvm.org/viewvc/llvm-project?rev=126247&view=rev Log: Add two convenience functions: DecodeImmShiftThumb() and DecodeImmShiftARM() to ARMUtils.h. Use them within EmulateInstructionARM.cpp to save repetitive typing. Modified: lldb/trunk/source/Plugins/Instruction/ARM/EmulateInstructionARM.cpp lldb/trunk/source/Plugins/Process/Utility/ARMUtils.h Modified: lldb/trunk/source/Plugins/Instruction/ARM/EmulateInstructionARM.cpp URL: http://llvm.org/viewvc/llvm-project/lldb/trunk/source/Plugins/Instruction/ARM/EmulateInstructionARM.cpp?rev=126247&r1=126246&r2=126247&view=diff ============================================================================== --- lldb/trunk/source/Plugins/Instruction/ARM/EmulateInstructionARM.cpp (original) +++ lldb/trunk/source/Plugins/Instruction/ARM/EmulateInstructionARM.cpp Tue Feb 22 15:17:52 2011 @@ -829,7 +829,7 @@ Rd = Bits32(opcode, 11, 8); Rm = Bits32(opcode, 3, 0); setflags = BitIsSet(opcode, 20); - shift_n = DecodeImmShift(Bits32(opcode, 5, 4), Bits32(opcode, 14, 12)<<2 | Bits32(opcode, 7, 6), shift_t); + shift_n = DecodeImmShiftThumb(opcode, shift_t); // if (BadReg(d) || BadReg(m)) then UNPREDICTABLE; if ((BadReg(Rd) || BadReg(Rm))) return false; @@ -837,7 +837,7 @@ Rd = Bits32(opcode, 15, 12); Rm = Bits32(opcode, 3, 0); setflags = BitIsSet(opcode, 20); - shift_n = DecodeImmShift(Bits32(opcode, 6, 5), Bits32(opcode, 11, 7), shift_t); + shift_n = DecodeImmShiftARM(opcode, shift_t); break; default: return false; @@ -2128,7 +2128,7 @@ Rn = Bits32(opcode, 19, 16); Rm = Bits32(opcode, 3, 0); setflags = BitIsSet(opcode, 20); - shift_n = DecodeImmShift(Bits32(opcode, 6, 5), Bits32(opcode, 11, 7), shift_t); + shift_n = DecodeImmShiftARM(opcode, shift_t); break; default: return false; @@ -2245,7 +2245,7 @@ case eEncodingT2: Rn = Bits32(opcode, 19, 16); Rm = Bits32(opcode, 3, 0); - shift_n = DecodeImmShift(Bits32(opcode, 5, 4), Bits32(opcode, 14, 12)<<2 | Bits32(opcode, 7, 6), shift_t); + shift_n = DecodeImmShiftThumb(opcode, shift_t); // if n == 15 || BadReg(m) then UNPREDICTABLE; if (Rn == 15 || BadReg(Rm)) return false; @@ -2253,7 +2253,7 @@ case eEncodingA1: Rn = Bits32(opcode, 19, 16); Rm = Bits32(opcode, 3, 0); - shift_n = DecodeImmShift(Bits32(opcode, 6, 5), Bits32(opcode, 11, 7), shift_t); + shift_n = DecodeImmShiftARM(opcode, shift_t); default: return false; } @@ -2380,7 +2380,7 @@ case eEncodingA1: Rn = Bits32(opcode, 19, 16); Rm = Bits32(opcode, 3, 0); - shift_n = DecodeImmShift(Bits32(opcode, 6, 5), Bits32(opcode, 11, 7), shift_t); + shift_n = DecodeImmShiftARM(opcode, shift_t); default: return false; } @@ -4588,7 +4588,7 @@ Rn = Bits32(opcode, 19, 16); Rm = Bits32(opcode, 3, 0); setflags = BitIsSet(opcode, 20); - shift_n = DecodeImmShift(Bits32(opcode, 5, 4), Bits32(opcode, 14, 12)<<2 | Bits32(opcode, 7, 6), shift_t); + shift_n = DecodeImmShiftThumb(opcode, shift_t); if (BadReg(Rd) || BadReg(Rn) || BadReg(Rm)) return false; break; @@ -4597,7 +4597,7 @@ Rn = Bits32(opcode, 19, 16); Rm = Bits32(opcode, 3, 0); setflags = BitIsSet(opcode, 20); - shift_n = DecodeImmShift(Bits32(opcode, 6, 5), Bits32(opcode, 11, 7), shift_t); + shift_n = DecodeImmShiftARM(opcode, shift_t); // TODO: Emulate SUBS PC, LR and related instructions. if (Rd == 15 && setflags) return false; @@ -4752,7 +4752,7 @@ Rn = Bits32(opcode, 19, 16); Rm = Bits32(opcode, 3, 0); setflags = BitIsSet(opcode, 20); - shift_n = DecodeImmShift(Bits32(opcode, 5, 4), Bits32(opcode, 14, 12)<<2 | Bits32(opcode, 7, 6), shift_t); + shift_n = DecodeImmShiftThumb(opcode, shift_t); // if Rd == '1111' && S == '1' then SEE TST (register); if (Rd == 15 && setflags) return EmulateTSTReg(eEncodingT2); @@ -4764,7 +4764,7 @@ Rn = Bits32(opcode, 19, 16); Rm = Bits32(opcode, 3, 0); setflags = BitIsSet(opcode, 20); - shift_n = DecodeImmShift(Bits32(opcode, 6, 5), Bits32(opcode, 11, 7), shift_t); + shift_n = DecodeImmShiftARM(opcode, shift_t); // TODO: Emulate SUBS PC, LR and related instructions. if (Rd == 15 && setflags) return false; @@ -5651,8 +5651,8 @@ Rn = Bits32(opcode, 19, 16); Rm = Bits32(opcode, 3, 0); setflags = BitIsSet(opcode, 20); - shift_n = DecodeImmShift(Bits32(opcode, 5, 4), Bits32(opcode, 14, 12)<<2 | Bits32(opcode, 7, 6), shift_t); - // if Rd == ???1111??? && S == ???1??? then SEE TEQ (register); + shift_n = DecodeImmShiftThumb(opcode, shift_t); + // if Rd == '1111' && S == '1' then SEE TEQ (register); if (Rd == 15 && setflags) return EmulateTEQReg(eEncodingT1); if (Rd == 13 || (Rd == 15 && !setflags) || BadReg(Rn) || BadReg(Rm)) @@ -5663,7 +5663,7 @@ Rn = Bits32(opcode, 19, 16); Rm = Bits32(opcode, 3, 0); setflags = BitIsSet(opcode, 20); - shift_n = DecodeImmShift(Bits32(opcode, 6, 5), Bits32(opcode, 11, 7), shift_t); + shift_n = DecodeImmShiftARM(opcode, shift_t); // if Rd == '1111' && S == '1' then SEE SUBS PC, LR and related instructions; // TODO: Emulate SUBS PC, LR and related instructions. if (Rd == 15 && setflags) @@ -5820,8 +5820,8 @@ Rn = Bits32(opcode, 19, 16); Rm = Bits32(opcode, 3, 0); setflags = BitIsSet(opcode, 20); - shift_n = DecodeImmShift(Bits32(opcode, 5, 4), Bits32(opcode, 14, 12)<<2 | Bits32(opcode, 7, 6), shift_t); - // if Rn == ???1111??? then SEE MOV (register); + shift_n = DecodeImmShiftThumb(opcode, shift_t); + // if Rn == '1111' then SEE MOV (register); if (Rn == 15) return EmulateMOVRdRm(eEncodingT3); if (BadReg(Rd) || Rn == 13 || BadReg(Rm)) @@ -5832,7 +5832,7 @@ Rn = Bits32(opcode, 19, 16); Rm = Bits32(opcode, 3, 0); setflags = BitIsSet(opcode, 20); - shift_n = DecodeImmShift(Bits32(opcode, 6, 5), Bits32(opcode, 11, 7), shift_t); + shift_n = DecodeImmShiftARM(opcode, shift_t); // TODO: Emulate SUBS PC, LR and related instructions. if (Rd == 15 && setflags) return false; @@ -5957,14 +5957,14 @@ case eEncodingT1: Rn = Bits32(opcode, 19, 16); Rm = Bits32(opcode, 3, 0); - shift_n = DecodeImmShift(Bits32(opcode, 5, 4), Bits32(opcode, 14, 12)<<2 | Bits32(opcode, 7, 6), shift_t); + shift_n = DecodeImmShiftThumb(opcode, shift_t); if (BadReg(Rn) || BadReg(Rm)) return false; break; case eEncodingA1: Rn = Bits32(opcode, 19, 16); Rm = Bits32(opcode, 3, 0); - shift_n = DecodeImmShift(Bits32(opcode, 6, 5), Bits32(opcode, 11, 7), shift_t); + shift_n = DecodeImmShiftARM(opcode, shift_t); break; default: return false; @@ -6090,14 +6090,14 @@ case eEncodingT2: Rn = Bits32(opcode, 19, 16); Rm = Bits32(opcode, 3, 0); - shift_n = DecodeImmShift(Bits32(opcode, 5, 4), Bits32(opcode, 14, 12)<<2 | Bits32(opcode, 7, 6), shift_t); + shift_n = DecodeImmShiftThumb(opcode, shift_t); if (BadReg(Rn) || BadReg(Rm)) return false; break; case eEncodingA1: Rn = Bits32(opcode, 19, 16); Rm = Bits32(opcode, 3, 0); - shift_n = DecodeImmShift(Bits32(opcode, 6, 5), Bits32(opcode, 11, 7), shift_t); + shift_n = DecodeImmShiftARM(opcode, shift_t); break; default: return false; Modified: lldb/trunk/source/Plugins/Process/Utility/ARMUtils.h URL: http://llvm.org/viewvc/llvm-project/lldb/trunk/source/Plugins/Process/Utility/ARMUtils.h?rev=126247&r1=126246&r2=126247&view=diff ============================================================================== --- lldb/trunk/source/Plugins/Process/Utility/ARMUtils.h (original) +++ lldb/trunk/source/Plugins/Process/Utility/ARMUtils.h Tue Feb 22 15:17:52 2011 @@ -51,6 +51,20 @@ } } +// A8.6.35 CMP (register) -- Encoding T3 +// Convenience function. +static inline uint32_t DecodeImmShiftThumb(const uint32_t opcode, ARM_ShifterType &shift_t) +{ + return DecodeImmShift(Bits32(opcode, 5, 4), Bits32(opcode, 14, 12)<<2 | Bits32(opcode, 7, 6), shift_t); +} + +// A8.6.35 CMP (register) -- Encoding A1 +// Convenience function. +static inline uint32_t DecodeImmShiftARM(const uint32_t opcode, ARM_ShifterType &shift_t) +{ + return DecodeImmShift(Bits32(opcode, 6, 5), Bits32(opcode, 11, 7), shift_t); +} + static inline uint32_t DecodeImmShift(const ARM_ShifterType shift_t, const uint32_t imm5) { ARM_ShifterType dont_care; @@ -216,11 +230,11 @@ } // (imm32, carry_out) = ARMExpandImm_C(imm12, carry_in) -static inline uint32_t ARMExpandImm_C(uint32_t val, uint32_t carry_in, uint32_t &carry_out) +static inline uint32_t ARMExpandImm_C(uint32_t opcode, uint32_t carry_in, uint32_t &carry_out) { - uint32_t imm32; // the expanded result - uint32_t imm = bits(val, 7, 0); // immediate value - uint32_t amt = 2 * bits(val, 11, 8); // rotate amount + uint32_t imm32; // the expanded result + uint32_t imm = bits(opcode, 7, 0); // immediate value + uint32_t amt = 2 * bits(opcode, 11, 8); // rotate amount if (amt == 0) { imm32 = imm; @@ -234,21 +248,21 @@ return imm32; } -static inline uint32_t ARMExpandImm(uint32_t val) +static inline uint32_t ARMExpandImm(uint32_t opcode) { // 'carry_in' argument to following function call does not affect the imm32 result. uint32_t carry_in = 0; uint32_t carry_out; - return ARMExpandImm_C(val, carry_in, carry_out); + return ARMExpandImm_C(opcode, carry_in, carry_out); } // (imm32, carry_out) = ThumbExpandImm_C(imm12, carry_in) -static inline uint32_t ThumbExpandImm_C(uint32_t val, uint32_t carry_in, uint32_t &carry_out) +static inline uint32_t ThumbExpandImm_C(uint32_t opcode, uint32_t carry_in, uint32_t &carry_out) { uint32_t imm32; // the expaned result - const uint32_t i = bit(val, 26); - const uint32_t imm3 = bits(val, 14, 12); - const uint32_t abcdefgh = bits(val, 7, 0); + const uint32_t i = bit(opcode, 26); + const uint32_t imm3 = bits(opcode, 14, 12); + const uint32_t abcdefgh = bits(opcode, 7, 0); const uint32_t imm12 = i << 11 | imm3 << 8 | abcdefgh; if (bits(imm12, 11, 10) == 0) @@ -281,28 +295,28 @@ return imm32; } -static inline uint32_t ThumbExpandImm(uint32_t val) +static inline uint32_t ThumbExpandImm(uint32_t opcode) { // 'carry_in' argument to following function call does not affect the imm32 result. uint32_t carry_in = 0; uint32_t carry_out; - return ThumbExpandImm_C(val, carry_in, carry_out); + return ThumbExpandImm_C(opcode, carry_in, carry_out); } // imm32 = ZeroExtend(i:imm3:imm8, 32) -static inline uint32_t ThumbImm12(uint32_t val) +static inline uint32_t ThumbImm12(uint32_t opcode) { - const uint32_t i = bit(val, 26); - const uint32_t imm3 = bits(val, 14, 12); - const uint32_t imm8 = bits(val, 7, 0); + const uint32_t i = bit(opcode, 26); + const uint32_t imm3 = bits(opcode, 14, 12); + const uint32_t imm8 = bits(opcode, 7, 0); const uint32_t imm12 = i << 11 | imm3 << 8 | imm8; return imm12; } // imm32 = ZeroExtend(imm7:'00', 32) -static inline uint32_t ThumbImmScaled(uint32_t val) +static inline uint32_t ThumbImmScaled(uint32_t opcode) { - const uint32_t imm7 = bits(val, 6, 0); + const uint32_t imm7 = bits(opcode, 6, 0); return imm7 * 4; } From gclayton at apple.com Tue Feb 22 15:21:04 2011 From: gclayton at apple.com (Greg Clayton) Date: Tue, 22 Feb 2011 21:21:04 -0000 Subject: [Lldb-commits] [lldb] r126248 - /lldb/branches/apple/calcite/lldb/source/Plugins/Process/Utility/RegisterContextLLDB.cpp Message-ID: <20110222212104.F0C382A6C12C@llvm.org> Author: gclayton Date: Tue Feb 22 15:21:04 2011 New Revision: 126248 URL: http://llvm.org/viewvc/llvm-project?rev=126248&view=rev Log: assertion can cause LLDB to crash when doing backtraces Modified: lldb/branches/apple/calcite/lldb/source/Plugins/Process/Utility/RegisterContextLLDB.cpp Modified: lldb/branches/apple/calcite/lldb/source/Plugins/Process/Utility/RegisterContextLLDB.cpp URL: http://llvm.org/viewvc/llvm-project/lldb/branches/apple/calcite/lldb/source/Plugins/Process/Utility/RegisterContextLLDB.cpp?rev=126248&r1=126247&r2=126248&view=diff ============================================================================== --- lldb/branches/apple/calcite/lldb/source/Plugins/Process/Utility/RegisterContextLLDB.cpp (original) +++ lldb/branches/apple/calcite/lldb/source/Plugins/Process/Utility/RegisterContextLLDB.cpp Tue Feb 22 15:21:04 2011 @@ -113,8 +113,18 @@ if (addr_range.GetBaseAddress().IsValid()) { m_start_pc = addr_range.GetBaseAddress(); - assert (frame_sp->GetFrameCodeAddress().GetSection() == m_start_pc.GetSection()); - m_current_offset = frame_sp->GetFrameCodeAddress().GetOffset() - m_start_pc.GetOffset(); + if (frame_sp->GetFrameCodeAddress().GetSection() == m_start_pc.GetSection()) + { + m_current_offset = frame_sp->GetFrameCodeAddress().GetOffset() - m_start_pc.GetOffset(); + } + else if (frame_sp->GetFrameCodeAddress().GetModule() == m_start_pc.GetModule()) + { + // This means that whatever symbol we kicked up isn't really correct + // as no should cross section boundaries... We really should NULL out + // the function/symbol in this case unless there is a bad assumption + // here due to inlined functions? + m_current_offset = frame_sp->GetFrameCodeAddress().GetFileAddress() - m_start_pc.GetFileAddress(); + } m_current_offset_backed_up_one = m_current_offset; } else From gclayton at apple.com Tue Feb 22 15:22:58 2011 From: gclayton at apple.com (Greg Clayton) Date: Tue, 22 Feb 2011 21:22:58 -0000 Subject: [Lldb-commits] [lldb] r126249 - in /lldb/branches/apple/calcite/lldb: lldb.xcodeproj/project.pbxproj resources/LLDB-Info.plist tools/debugserver/debugserver.xcodeproj/project.pbxproj Message-ID: <20110222212258.DDD012A6C12C@llvm.org> Author: gclayton Date: Tue Feb 22 15:22:58 2011 New Revision: 126249 URL: http://llvm.org/viewvc/llvm-project?rev=126249&view=rev Log: Bumped Xcode project version to lldb-51 and debugserver-135. Modified: lldb/branches/apple/calcite/lldb/lldb.xcodeproj/project.pbxproj lldb/branches/apple/calcite/lldb/resources/LLDB-Info.plist lldb/branches/apple/calcite/lldb/tools/debugserver/debugserver.xcodeproj/project.pbxproj Modified: lldb/branches/apple/calcite/lldb/lldb.xcodeproj/project.pbxproj URL: http://llvm.org/viewvc/llvm-project/lldb/branches/apple/calcite/lldb/lldb.xcodeproj/project.pbxproj?rev=126249&r1=126248&r2=126249&view=diff ============================================================================== --- lldb/branches/apple/calcite/lldb/lldb.xcodeproj/project.pbxproj (original) +++ lldb/branches/apple/calcite/lldb/lldb.xcodeproj/project.pbxproj Tue Feb 22 15:22:58 2011 @@ -2976,9 +2976,9 @@ buildSettings = { ALWAYS_SEARCH_USER_PATHS = NO; COPY_PHASE_STRIP = NO; - CURRENT_PROJECT_VERSION = 50; + CURRENT_PROJECT_VERSION = 51; DYLIB_COMPATIBILITY_VERSION = 1; - DYLIB_CURRENT_VERSION = 50; + DYLIB_CURRENT_VERSION = 51; EXPORTED_SYMBOLS_FILE = "resources/lldb-framework-exports"; FRAMEWORK_SEARCH_PATHS = ( "$(inherited)", @@ -3033,11 +3033,11 @@ buildSettings = { ALWAYS_SEARCH_USER_PATHS = NO; COPY_PHASE_STRIP = NO; - CURRENT_PROJECT_VERSION = 50; + CURRENT_PROJECT_VERSION = 51; DEAD_CODE_STRIPPING = YES; DEBUG_INFORMATION_FORMAT = "dwarf-with-dsym"; DYLIB_COMPATIBILITY_VERSION = 1; - DYLIB_CURRENT_VERSION = 50; + DYLIB_CURRENT_VERSION = 51; EXPORTED_SYMBOLS_FILE = "resources/lldb-framework-exports"; FRAMEWORK_SEARCH_PATHS = ( "$(inherited)", @@ -3120,7 +3120,7 @@ isa = XCBuildConfiguration; buildSettings = { COPY_PHASE_STRIP = YES; - CURRENT_PROJECT_VERSION = 50; + CURRENT_PROJECT_VERSION = 51; DEBUG_INFORMATION_FORMAT = "dwarf-with-dsym"; FRAMEWORK_SEARCH_PATHS = ( "$(inherited)", @@ -3156,11 +3156,11 @@ buildSettings = { ALWAYS_SEARCH_USER_PATHS = NO; COPY_PHASE_STRIP = YES; - CURRENT_PROJECT_VERSION = 50; + CURRENT_PROJECT_VERSION = 51; DEAD_CODE_STRIPPING = YES; DEBUG_INFORMATION_FORMAT = "dwarf-with-dsym"; DYLIB_COMPATIBILITY_VERSION = 1; - DYLIB_CURRENT_VERSION = 50; + DYLIB_CURRENT_VERSION = 51; EXPORTED_SYMBOLS_FILE = "resources/lldb-framework-exports"; FRAMEWORK_SEARCH_PATHS = ( "$(inherited)", @@ -3214,7 +3214,7 @@ buildSettings = { CODE_SIGN_IDENTITY = lldb_codesign; COPY_PHASE_STRIP = NO; - CURRENT_PROJECT_VERSION = 50; + CURRENT_PROJECT_VERSION = 51; FRAMEWORK_SEARCH_PATHS = ( "$(inherited)", "\"$(SYSTEM_LIBRARY_DIR)/PrivateFrameworks\"", @@ -3253,7 +3253,7 @@ ); CODE_SIGN_IDENTITY = lldb_codesign; COPY_PHASE_STRIP = YES; - CURRENT_PROJECT_VERSION = 50; + CURRENT_PROJECT_VERSION = 51; DEBUG_INFORMATION_FORMAT = "dwarf-with-dsym"; FRAMEWORK_SEARCH_PATHS = ( "$(inherited)", Modified: lldb/branches/apple/calcite/lldb/resources/LLDB-Info.plist URL: http://llvm.org/viewvc/llvm-project/lldb/branches/apple/calcite/lldb/resources/LLDB-Info.plist?rev=126249&r1=126248&r2=126249&view=diff ============================================================================== --- lldb/branches/apple/calcite/lldb/resources/LLDB-Info.plist (original) +++ lldb/branches/apple/calcite/lldb/resources/LLDB-Info.plist Tue Feb 22 15:22:58 2011 @@ -17,7 +17,7 @@ CFBundleSignature ???? CFBundleVersion - 50 + 51 CFBundleName ${EXECUTABLE_NAME} Modified: lldb/branches/apple/calcite/lldb/tools/debugserver/debugserver.xcodeproj/project.pbxproj URL: http://llvm.org/viewvc/llvm-project/lldb/branches/apple/calcite/lldb/tools/debugserver/debugserver.xcodeproj/project.pbxproj?rev=126249&r1=126248&r2=126249&view=diff ============================================================================== --- lldb/branches/apple/calcite/lldb/tools/debugserver/debugserver.xcodeproj/project.pbxproj (original) +++ lldb/branches/apple/calcite/lldb/tools/debugserver/debugserver.xcodeproj/project.pbxproj Tue Feb 22 15:22:58 2011 @@ -460,7 +460,7 @@ i386, ); COPY_PHASE_STRIP = NO; - CURRENT_PROJECT_VERSION = 134; + CURRENT_PROJECT_VERSION = 135; GCC_WARN_ABOUT_RETURN_TYPE = YES; GCC_WARN_UNUSED_VARIABLE = YES; STRIP_INSTALLED_PRODUCT = NO; @@ -478,7 +478,7 @@ x86_64, i386, ); - CURRENT_PROJECT_VERSION = 134; + CURRENT_PROJECT_VERSION = 135; DEAD_CODE_STRIPPING = YES; GCC_WARN_ABOUT_RETURN_TYPE = YES; GCC_WARN_UNUSED_VARIABLE = YES; @@ -498,7 +498,7 @@ x86_64, i386, ); - CURRENT_PROJECT_VERSION = 134; + CURRENT_PROJECT_VERSION = 135; DEAD_CODE_STRIPPING = YES; GCC_WARN_ABOUT_RETURN_TYPE = YES; GCC_WARN_UNUSED_VARIABLE = YES; @@ -515,7 +515,7 @@ buildSettings = { "CODE_SIGN_ENTITLEMENTS[sdk=iphoneos*]" = "source/debugserver-entitlements.plist"; COPY_PHASE_STRIP = YES; - CURRENT_PROJECT_VERSION = 134; + CURRENT_PROJECT_VERSION = 135; DEBUG_INFORMATION_FORMAT = "dwarf-with-dsym"; FRAMEWORK_SEARCH_PATHS = $SDKROOT/System/Library/PrivateFrameworks; "FRAMEWORK_SEARCH_PATHS[sdk=iphoneos*][arch=*]" = ( @@ -556,7 +556,7 @@ "CODE_SIGN_ENTITLEMENTS[sdk=iphoneos*]" = "source/debugserver-entitlements.plist"; "CODE_SIGN_IDENTITY[sdk=macosx*]" = lldb_codesign; COPY_PHASE_STRIP = YES; - CURRENT_PROJECT_VERSION = 134; + CURRENT_PROJECT_VERSION = 135; FRAMEWORK_SEARCH_PATHS = $SDKROOT/System/Library/PrivateFrameworks; "FRAMEWORK_SEARCH_PATHS[sdk=iphoneos*][arch=*]" = ( "$(SDKROOT)/System/Library/PrivateFrameworks", @@ -597,7 +597,7 @@ "CODE_SIGN_ENTITLEMENTS[sdk=iphoneos*]" = "source/debugserver-entitlements.plist"; "CODE_SIGN_IDENTITY[sdk=macosx*]" = lldb_codesign; COPY_PHASE_STRIP = YES; - CURRENT_PROJECT_VERSION = 134; + CURRENT_PROJECT_VERSION = 135; DEBUG_INFORMATION_FORMAT = "dwarf-with-dsym"; FRAMEWORK_SEARCH_PATHS = $SDKROOT/System/Library/PrivateFrameworks; "FRAMEWORK_SEARCH_PATHS[sdk=iphoneos*][arch=*]" = ( From scallanan at apple.com Tue Feb 22 15:52:56 2011 From: scallanan at apple.com (Sean Callanan) Date: Tue, 22 Feb 2011 21:52:56 -0000 Subject: [Lldb-commits] [lldb] r126251 - /lldb/trunk/source/Expression/ASTResultSynthesizer.cpp Message-ID: <20110222215256.3B9842A6C12C@llvm.org> Author: spyffe Date: Tue Feb 22 15:52:56 2011 New Revision: 126251 URL: http://llvm.org/viewvc/llvm-project?rev=126251&view=rev Log: Fixed a hang in the expression parser's result synthesizer that occurs when the function generated for the expression is completely empty except for a NULL_STMT. This happens sometimes when the parser returns errors. Modified: lldb/trunk/source/Expression/ASTResultSynthesizer.cpp Modified: lldb/trunk/source/Expression/ASTResultSynthesizer.cpp URL: http://llvm.org/viewvc/llvm-project/lldb/trunk/source/Expression/ASTResultSynthesizer.cpp?rev=126251&r1=126250&r2=126251&view=diff ============================================================================== --- lldb/trunk/source/Expression/ASTResultSynthesizer.cpp (original) +++ lldb/trunk/source/Expression/ASTResultSynthesizer.cpp Tue Feb 22 15:52:56 2011 @@ -238,6 +238,10 @@ last_stmt_ptr--; last_stmt = *last_stmt_ptr; } + else + { + return false; + } } Expr *last_expr = dyn_cast(last_stmt); From gclayton at apple.com Tue Feb 22 16:59:30 2011 From: gclayton at apple.com (Greg Clayton) Date: Tue, 22 Feb 2011 22:59:30 -0000 Subject: [Lldb-commits] [lldb] r126257 - /lldb/trunk/test/dotest.py Message-ID: <20110222225930.BC4962A6C12C@llvm.org> Author: gclayton Date: Tue Feb 22 16:59:30 2011 New Revision: 126257 URL: http://llvm.org/viewvc/llvm-project?rev=126257&view=rev Log: Make logs threadsafe (add the -t option) when logging API stuff. Modified: lldb/trunk/test/dotest.py Modified: lldb/trunk/test/dotest.py URL: http://llvm.org/viewvc/llvm-project/lldb/trunk/test/dotest.py?rev=126257&r1=126256&r2=126257&view=diff ============================================================================== --- lldb/trunk/test/dotest.py (original) +++ lldb/trunk/test/dotest.py Tue Feb 22 16:59:30 2011 @@ -629,7 +629,7 @@ else: lldb_log_option = "event process expr state api" ci.HandleCommand( - "log enable -T -n -f " + os.environ["LLDB_LOG"] + " lldb " + lldb_log_option, + "log enable -t -T -n -f " + os.environ["LLDB_LOG"] + " lldb " + lldb_log_option, res) if not res.Succeeded(): raise Exception('log enable failed (check LLDB_LOG env variable.') @@ -641,7 +641,7 @@ else: gdb_remote_log_option = "packets process" ci.HandleCommand( - "log enable -T -n -f " + os.environ["GDB_REMOTE_LOG"] + " process.gdb-remote " + "log enable -t -T -n -f " + os.environ["GDB_REMOTE_LOG"] + " process.gdb-remote " + gdb_remote_log_option, res) if not res.Succeeded(): From gclayton at apple.com Tue Feb 22 17:08:31 2011 From: gclayton at apple.com (Greg Clayton) Date: Tue, 22 Feb 2011 23:08:31 -0000 Subject: [Lldb-commits] [lldb] r126260 - /lldb/trunk/test/dotest.py Message-ID: <20110222230831.DFB792A6C12C@llvm.org> Author: gclayton Date: Tue Feb 22 17:08:31 2011 New Revision: 126260 URL: http://llvm.org/viewvc/llvm-project?rev=126260&view=rev Log: Don't enable thread safe logging as it currently deadlocks logging. Modified: lldb/trunk/test/dotest.py Modified: lldb/trunk/test/dotest.py URL: http://llvm.org/viewvc/llvm-project/lldb/trunk/test/dotest.py?rev=126260&r1=126259&r2=126260&view=diff ============================================================================== --- lldb/trunk/test/dotest.py (original) +++ lldb/trunk/test/dotest.py Tue Feb 22 17:08:31 2011 @@ -629,7 +629,7 @@ else: lldb_log_option = "event process expr state api" ci.HandleCommand( - "log enable -t -T -n -f " + os.environ["LLDB_LOG"] + " lldb " + lldb_log_option, + "log enable -T -n -f " + os.environ["LLDB_LOG"] + " lldb " + lldb_log_option, res) if not res.Succeeded(): raise Exception('log enable failed (check LLDB_LOG env variable.') @@ -641,7 +641,7 @@ else: gdb_remote_log_option = "packets process" ci.HandleCommand( - "log enable -t -T -n -f " + os.environ["GDB_REMOTE_LOG"] + " process.gdb-remote " + "log enable -T -n -f " + os.environ["GDB_REMOTE_LOG"] + " process.gdb-remote " + gdb_remote_log_option, res) if not res.Succeeded(): From johnny.chen at apple.com Tue Feb 22 17:42:58 2011 From: johnny.chen at apple.com (Johnny Chen) Date: Tue, 22 Feb 2011 23:42:58 -0000 Subject: [Lldb-commits] [lldb] r126265 - in /lldb/trunk/source/Plugins/Instruction/ARM: EmulateInstructionARM.cpp EmulateInstructionARM.h Message-ID: <20110222234259.034CD2A6C12C@llvm.org> Author: johnny Date: Tue Feb 22 17:42:58 2011 New Revision: 126265 URL: http://llvm.org/viewvc/llvm-project?rev=126265&view=rev Log: Add emulation methods for "RSB (immediate)" and "RSB (register)". Plus add missing break stmts for "case" blocks. Modified: lldb/trunk/source/Plugins/Instruction/ARM/EmulateInstructionARM.cpp lldb/trunk/source/Plugins/Instruction/ARM/EmulateInstructionARM.h Modified: lldb/trunk/source/Plugins/Instruction/ARM/EmulateInstructionARM.cpp URL: http://llvm.org/viewvc/llvm-project/lldb/trunk/source/Plugins/Instruction/ARM/EmulateInstructionARM.cpp?rev=126265&r1=126264&r2=126265&view=diff ============================================================================== --- lldb/trunk/source/Plugins/Instruction/ARM/EmulateInstructionARM.cpp (original) +++ lldb/trunk/source/Plugins/Instruction/ARM/EmulateInstructionARM.cpp Tue Feb 22 17:42:58 2011 @@ -630,6 +630,7 @@ // if !setflags && (d == 15 || m == 15 || (d == 13 && m == 13)) then UNPREDICTABLE; if (!setflags && (Rd == 15 || Rm == 15 || (Rd == 13 && Rm == 13))) return false; + break; default: return false; } @@ -831,8 +832,9 @@ setflags = BitIsSet(opcode, 20); shift_n = DecodeImmShiftThumb(opcode, shift_t); // if (BadReg(d) || BadReg(m)) then UNPREDICTABLE; - if ((BadReg(Rd) || BadReg(Rm))) + if (BadReg(Rd) || BadReg(Rm)) return false; + break; case eEncodingA1: Rd = Bits32(opcode, 15, 12); Rm = Bits32(opcode, 3, 0); @@ -1441,6 +1443,7 @@ switch (encoding) { case eEncodingT1: imm32 = ThumbImmScaled(opcode); // imm32 = ZeroExtend(imm7:'00', 32) + break; case eEncodingT2: imm32 = ThumbExpandImm(opcode); // imm32 = ThumbExpandImm(i:imm3:imm8) break; @@ -2112,6 +2115,7 @@ setflags = !InITBlock(); shift_t = SRType_LSL; shift_n = 0; + break; case eEncodingT2: Rd = Rn = Bit32(opcode, 7) << 3 | Bits32(opcode, 2, 0); Rm = Bits32(opcode, 6, 3); @@ -2186,6 +2190,7 @@ imm32 = ThumbExpandImm(opcode); // imm32 = ThumbExpandImm(i:imm3:imm8) if (Rn == 15) return false; + break; case eEncodingA1: Rn = Bits32(opcode, 19, 16); imm32 = ARMExpandImm(opcode); // imm32 = ARMExpandImm(imm12) @@ -2254,6 +2259,7 @@ Rn = Bits32(opcode, 19, 16); Rm = Bits32(opcode, 3, 0); shift_n = DecodeImmShiftARM(opcode, shift_t); + break; default: return false; } @@ -2306,11 +2312,13 @@ case eEncodingT1: Rn = Bits32(opcode, 10, 8); imm32 = Bits32(opcode, 7, 0); + break; case eEncodingT2: Rn = Bits32(opcode, 19, 16); imm32 = ThumbExpandImm(opcode); // imm32 = ThumbExpandImm(i:imm3:imm8) if (Rn == 15) return false; + break; case eEncodingA1: Rn = Bits32(opcode, 19, 16); imm32 = ARMExpandImm(opcode); // imm32 = ARMExpandImm(imm12) @@ -2381,6 +2389,7 @@ Rn = Bits32(opcode, 19, 16); Rm = Bits32(opcode, 3, 0); shift_n = DecodeImmShiftARM(opcode, shift_t); + break; default: return false; } @@ -4583,6 +4592,7 @@ setflags = !InITBlock(); shift_t = SRType_LSL; shift_n = 0; + break; case eEncodingT2: Rd = Bits32(opcode, 11, 8); Rn = Bits32(opcode, 19, 16); @@ -4747,6 +4757,7 @@ setflags = !InITBlock(); shift_t = SRType_LSL; shift_n = 0; + break; case eEncodingT2: Rd = Bits32(opcode, 11, 8); Rn = Bits32(opcode, 19, 16); @@ -5646,6 +5657,7 @@ setflags = !InITBlock(); shift_t = SRType_LSL; shift_n = 0; + break; case eEncodingT2: Rd = Bits32(opcode, 11, 8); Rn = Bits32(opcode, 19, 16); @@ -5815,6 +5827,7 @@ setflags = !InITBlock(); shift_t = SRType_LSL; shift_n = 0; + break; case eEncodingT2: Rd = Bits32(opcode, 11, 8); Rn = Bits32(opcode, 19, 16); @@ -5864,6 +5877,161 @@ return true; } +// Reverse Subtract (immediate) subtracts a register value from an immediate value, and writes the result to +// the destination register. It can optionally update the condition flags based on the result. +bool +EmulateInstructionARM::EmulateRSBImm (ARMEncoding encoding) +{ +#if 0 + // ARM pseudo code... + if ConditionPassed() then + EncodingSpecificOperations(); + (result, carry, overflow) = AddWithCarry(NOT(R[n]), imm32, '1'); + if d == 15 then // Can only occur for ARM encoding + ALUWritePC(result); // setflags is always FALSE here + else + R[d] = result; + if setflags then + APSR.N = result<31>; + APSR.Z = IsZeroBit(result); + APSR.C = carry; + APSR.V = overflow; +#endif + + bool success = false; + const uint32_t opcode = OpcodeAsUnsigned (&success); + if (!success) + return false; + + uint32_t Rd; // the destination register + uint32_t Rn; // the first operand + bool setflags; + uint32_t imm32; // the immediate value to be added to the value obtained from Rn + switch (encoding) { + case eEncodingT1: + Rd = Bits32(opcode, 2, 0); + Rn = Bits32(opcode, 5, 3); + setflags = !InITBlock(); + imm32 = 0; + break; + case eEncodingT2: + Rd = Bits32(opcode, 11, 8); + Rn = Bits32(opcode, 19, 16); + setflags = BitIsSet(opcode, 20); + imm32 = ThumbExpandImm(opcode); // imm32 = ThumbExpandImm(i:imm3:imm8) + if (BadReg(Rd) || BadReg(Rn)) + return false; + break; + case eEncodingA1: + Rd = Bits32(opcode, 15, 12); + Rn = Bits32(opcode, 19, 16); + setflags = BitIsSet(opcode, 20); + imm32 = ARMExpandImm(opcode); // imm32 = ARMExpandImm(imm12) + // if Rd == '1111' && S == '1' then SEE SUBS PC, LR and related instructions; + // TODO: Emulate SUBS PC, LR and related instructions. + if (Rd == 15 && setflags) + return false; + break; + default: + return false; + } + // Read the register value from the operand register Rn. + uint32_t reg_val = ReadCoreReg(Rn, &success); + if (!success) + return false; + + AddWithCarryResult res = AddWithCarry(~reg_val, imm32, 1); + + EmulateInstruction::Context context; + context.type = EmulateInstruction::eContextImmediate; + context.SetNoArgs (); + + if (!WriteCoreRegOptionalFlags(context, res.result, Rd, setflags, res.carry_out, res.overflow)) + return false; + + return true; +} + +// Reverse Subtract (register) subtracts a register value from an optionally-shifted register value, and writes the +// result to the destination register. It can optionally update the condition flags based on the result. +bool +EmulateInstructionARM::EmulateRSBReg (ARMEncoding encoding) +{ +#if 0 + // ARM pseudo code... + if ConditionPassed() then + EncodingSpecificOperations(); + shifted = Shift(R[m], shift_t, shift_n, APSR.C); + (result, carry, overflow) = AddWithCarry(NOT(R[n]), shifted, '1'); + if d == 15 then // Can only occur for ARM encoding + ALUWritePC(result); // setflags is always FALSE here + else + R[d] = result; + if setflags then + APSR.N = result<31>; + APSR.Z = IsZeroBit(result); + APSR.C = carry; + APSR.V = overflow; +#endif + + bool success = false; + const uint32_t opcode = OpcodeAsUnsigned (&success); + if (!success) + return false; + + uint32_t Rd; // the destination register + uint32_t Rn; // the first operand + uint32_t Rm; // the second operand + bool setflags; + ARM_ShifterType shift_t; + uint32_t shift_n; // the shift applied to the value read from Rm + switch (encoding) { + case eEncodingT1: + Rd = Bits32(opcode, 11, 8); + Rn = Bits32(opcode, 19, 16); + Rm = Bits32(opcode, 3, 0); + setflags = BitIsSet(opcode, 20); + shift_n = DecodeImmShiftThumb(opcode, shift_t); + // if (BadReg(d) || BadReg(m)) then UNPREDICTABLE; + if (BadReg(Rd) || BadReg(Rn) || BadReg(Rm)) + return false; + break; + case eEncodingA1: + Rd = Bits32(opcode, 15, 12); + Rn = Bits32(opcode, 19, 16); + Rm = Bits32(opcode, 3, 0); + setflags = BitIsSet(opcode, 20); + shift_n = DecodeImmShiftARM(opcode, shift_t); + // if Rd == '1111' && S == '1' then SEE SUBS PC, LR and related instructions; + // TODO: Emulate SUBS PC, LR and related instructions. + if (Rd == 15 && setflags) + return false; + break; + default: + return false; + } + // Read the register value from register Rn. + uint32_t val1 = ReadCoreReg(Rn, &success); + if (!success) + return false; + + // Read the register value from register Rm. + uint32_t val2 = ReadCoreReg(Rm, &success); + if (!success) + return false; + + uint32_t shifted = Shift(val2, shift_t, shift_n, APSR_C); + AddWithCarryResult res = AddWithCarry(~val1, shifted, 1); + + EmulateInstruction::Context context; + context.type = EmulateInstruction::eContextImmediate; + context.SetNoArgs(); + if (!WriteCoreRegOptionalFlags(context, res.result, Rd, setflags, res.carry_out, res.overflow)) + return false; + + return true; +} + // Test Equivalence (immediate) performs a bitwise exclusive OR operation on a register value and an // immediate value. It updates the condition flags based on the result, and discards the result. bool @@ -6087,6 +6255,7 @@ Rm = Bits32(opcode, 5, 3); shift_t = SRType_LSL; shift_n = 0; + break; case eEncodingT2: Rn = Bits32(opcode, 19, 16); Rm = Bits32(opcode, 3, 0); @@ -6207,6 +6376,10 @@ { 0x0fe00000, 0x03800000, ARMvAll, eEncodingA1, eSize32, &EmulateInstructionARM::EmulateORRImm, "orr{s} , , #const"}, // orr (register) { 0x0fe00010, 0x01800000, ARMvAll, eEncodingA1, eSize32, &EmulateInstructionARM::EmulateORRReg, "orr{s} , , {,}"}, + // rsb (immediate) + { 0x0fe00000, 0x02600000, ARMvAll, eEncodingA1, eSize32, &EmulateInstructionARM::EmulateRSBImm, "rsb{s} , , #"}, + // rsb (register) + { 0x0fe00010, 0x00600000, ARMvAll, eEncodingA1, eSize32, &EmulateInstructionARM::EmulateRSBReg, "rsb{s} , , {,}"}, // teq (immediate) { 0x0ff0f000, 0x03300000, ARMvAll, eEncodingA1, eSize32, &EmulateInstructionARM::EmulateTEQImm, "teq , #const"}, // teq (register) @@ -6388,6 +6561,11 @@ // orr (register) { 0xffffffc0, 0x00004300, ARMvAll, eEncodingT1, eSize16, &EmulateInstructionARM::EmulateORRReg, "orrs|orr , "}, { 0xffe08000, 0xea400000, ARMV6T2_ABOVE, eEncodingT2, eSize32, &EmulateInstructionARM::EmulateORRReg, "orr{s}.w , , {,}"}, + // rsb (immediate) + { 0xffffffc0, 0x00004240, ARMvAll, eEncodingT1, eSize16, &EmulateInstructionARM::EmulateRSBImm, "rsbs|rsb , , #0"}, + { 0xfbe08000, 0xf1c00000, ARMV6T2_ABOVE, eEncodingT2, eSize32, &EmulateInstructionARM::EmulateRSBImm, "rsb{s}.w , , #"}, + // rsb (register) + { 0xffe08000, 0xea400000, ARMV6T2_ABOVE, eEncodingT1, eSize32, &EmulateInstructionARM::EmulateRSBReg, "rsb{s}.w , , {,}"}, // teq (immediate) { 0xfbf08f00, 0xf0900f00, ARMV6T2_ABOVE, eEncodingT1, eSize32, &EmulateInstructionARM::EmulateTEQImm, "teq , #"}, // teq (register) Modified: lldb/trunk/source/Plugins/Instruction/ARM/EmulateInstructionARM.h URL: http://llvm.org/viewvc/llvm-project/lldb/trunk/source/Plugins/Instruction/ARM/EmulateInstructionARM.h?rev=126265&r1=126264&r2=126265&view=diff ============================================================================== --- lldb/trunk/source/Plugins/Instruction/ARM/EmulateInstructionARM.h (original) +++ lldb/trunk/source/Plugins/Instruction/ARM/EmulateInstructionARM.h Tue Feb 22 17:42:58 2011 @@ -655,11 +655,11 @@ // A8.6.141 RSB (immediate) - Encoding T1, A1 bool - EmulateRSBImmediate (ARMEncoding encoding); + EmulateRSBImm (ARMEncoding encoding); // A8.6.142 RSB (register) - Encoding A1 bool - EmulateRSBRegister (ARMEncoding encoding); + EmulateRSBReg (ARMEncoding encoding); // A8.6.144 RSC (immediate) - Encoding A1 bool From johnny.chen at apple.com Tue Feb 22 18:07:09 2011 From: johnny.chen at apple.com (Johnny Chen) Date: Wed, 23 Feb 2011 00:07:09 -0000 Subject: [Lldb-commits] [lldb] r126267 - in /lldb/trunk/source/Plugins/Instruction/ARM: EmulateInstructionARM.cpp EmulateInstructionARM.h Message-ID: <20110223000710.0FB222A6C12C@llvm.org> Author: johnny Date: Tue Feb 22 18:07:09 2011 New Revision: 126267 URL: http://llvm.org/viewvc/llvm-project?rev=126267&view=rev Log: Add emulation methods for "RSC (immediate)" and "RSC (register)" operations. Modified: lldb/trunk/source/Plugins/Instruction/ARM/EmulateInstructionARM.cpp lldb/trunk/source/Plugins/Instruction/ARM/EmulateInstructionARM.h Modified: lldb/trunk/source/Plugins/Instruction/ARM/EmulateInstructionARM.cpp URL: http://llvm.org/viewvc/llvm-project/lldb/trunk/source/Plugins/Instruction/ARM/EmulateInstructionARM.cpp?rev=126267&r1=126266&r2=126267&view=diff ============================================================================== --- lldb/trunk/source/Plugins/Instruction/ARM/EmulateInstructionARM.cpp (original) +++ lldb/trunk/source/Plugins/Instruction/ARM/EmulateInstructionARM.cpp Tue Feb 22 18:07:09 2011 @@ -5080,7 +5080,7 @@ addr_t address; // offset = Shift(R[m], shift_t, shift_n, APSR.C); -- Note "The APSR is an application level alias for the CPSR". - addr_t offset = Shift (Rm, shift_t, shift_n, Bit32 (m_inst_cpsr, CPSR_C)); + addr_t offset = Shift (Rm, shift_t, shift_n, Bit32 (m_inst_cpsr, APSR_C)); // offset_addr = if add then (R[n] + offset) else (R[n] - offset); if (add) @@ -6032,6 +6032,139 @@ return true; } +// Reverse Subtract with Carry (immediate) subtracts a register value and the value of NOT (Carry flag) from +// an immediate value, and writes the result to the destination register. It can optionally update the condition +// flags based on the result. +bool +EmulateInstructionARM::EmulateRSCImm (ARMEncoding encoding) +{ +#if 0 + // ARM pseudo code... + if ConditionPassed() then + EncodingSpecificOperations(); + (result, carry, overflow) = AddWithCarry(NOT(R[n]), imm32, APSR.C); + if d == 15 then + ALUWritePC(result); // setflags is always FALSE here + else + R[d] = result; + if setflags then + APSR.N = result<31>; + APSR.Z = IsZeroBit(result); + APSR.C = carry; + APSR.V = overflow; +#endif + + bool success = false; + const uint32_t opcode = OpcodeAsUnsigned (&success); + if (!success) + return false; + + uint32_t Rd; // the destination register + uint32_t Rn; // the first operand + bool setflags; + uint32_t imm32; // the immediate value to be added to the value obtained from Rn + switch (encoding) { + case eEncodingA1: + Rd = Bits32(opcode, 15, 12); + Rn = Bits32(opcode, 19, 16); + setflags = BitIsSet(opcode, 20); + imm32 = ARMExpandImm(opcode); // imm32 = ARMExpandImm(imm12) + // if Rd == '1111' && S == '1' then SEE SUBS PC, LR and related instructions; + // TODO: Emulate SUBS PC, LR and related instructions. + if (Rd == 15 && setflags) + return false; + break; + default: + return false; + } + // Read the register value from the operand register Rn. + uint32_t reg_val = ReadCoreReg(Rn, &success); + if (!success) + return false; + + AddWithCarryResult res = AddWithCarry(~reg_val, imm32, APSR_C); + + EmulateInstruction::Context context; + context.type = EmulateInstruction::eContextImmediate; + context.SetNoArgs (); + + if (!WriteCoreRegOptionalFlags(context, res.result, Rd, setflags, res.carry_out, res.overflow)) + return false; + + return true; +} + +// Reverse Subtract with Carry (register) subtracts a register value and the value of NOT (Carry flag) from an +// optionally-shifted register value, and writes the result to the destination register. It can optionally update the +// condition flags based on the result. +bool +EmulateInstructionARM::EmulateRSCReg (ARMEncoding encoding) +{ +#if 0 + // ARM pseudo code... + if ConditionPassed() then + EncodingSpecificOperations(); + shifted = Shift(R[m], shift_t, shift_n, APSR.C); + (result, carry, overflow) = AddWithCarry(NOT(R[n]), shifted, APSR.C); + if d == 15 then + ALUWritePC(result); // setflags is always FALSE here + else + R[d] = result; + if setflags then + APSR.N = result<31>; + APSR.Z = IsZeroBit(result); + APSR.C = carry; + APSR.V = overflow; +#endif + + bool success = false; + const uint32_t opcode = OpcodeAsUnsigned (&success); + if (!success) + return false; + + uint32_t Rd; // the destination register + uint32_t Rn; // the first operand + uint32_t Rm; // the second operand + bool setflags; + ARM_ShifterType shift_t; + uint32_t shift_n; // the shift applied to the value read from Rm + switch (encoding) { + case eEncodingA1: + Rd = Bits32(opcode, 15, 12); + Rn = Bits32(opcode, 19, 16); + Rm = Bits32(opcode, 3, 0); + setflags = BitIsSet(opcode, 20); + shift_n = DecodeImmShiftARM(opcode, shift_t); + // if Rd == '1111' && S == '1' then SEE SUBS PC, LR and related instructions; + // TODO: Emulate SUBS PC, LR and related instructions. + if (Rd == 15 && setflags) + return false; + break; + default: + return false; + } + // Read the register value from register Rn. + uint32_t val1 = ReadCoreReg(Rn, &success); + if (!success) + return false; + + // Read the register value from register Rm. + uint32_t val2 = ReadCoreReg(Rm, &success); + if (!success) + return false; + + uint32_t shifted = Shift(val2, shift_t, shift_n, APSR_C); + AddWithCarryResult res = AddWithCarry(~val1, shifted, APSR_C); + + EmulateInstruction::Context context; + context.type = EmulateInstruction::eContextImmediate; + context.SetNoArgs(); + if (!WriteCoreRegOptionalFlags(context, res.result, Rd, setflags, res.carry_out, res.overflow)) + return false; + + return true; +} + // Test Equivalence (immediate) performs a bitwise exclusive OR operation on a register value and an // immediate value. It updates the condition flags based on the result, and discards the result. bool @@ -6380,6 +6513,10 @@ { 0x0fe00000, 0x02600000, ARMvAll, eEncodingA1, eSize32, &EmulateInstructionARM::EmulateRSBImm, "rsb{s} , , #"}, // rsb (register) { 0x0fe00010, 0x00600000, ARMvAll, eEncodingA1, eSize32, &EmulateInstructionARM::EmulateRSBReg, "rsb{s} , , {,}"}, + // rsc (immediate) + { 0x0fe00000, 0x02e00000, ARMvAll, eEncodingA1, eSize32, &EmulateInstructionARM::EmulateRSCImm, "rsc{s} , , #"}, + // rsc (register) + { 0x0fe00010, 0x00e00000, ARMvAll, eEncodingA1, eSize32, &EmulateInstructionARM::EmulateRSCReg, "rsc{s} , , {,}"}, // teq (immediate) { 0x0ff0f000, 0x03300000, ARMvAll, eEncodingA1, eSize32, &EmulateInstructionARM::EmulateTEQImm, "teq , #const"}, // teq (register) Modified: lldb/trunk/source/Plugins/Instruction/ARM/EmulateInstructionARM.h URL: http://llvm.org/viewvc/llvm-project/lldb/trunk/source/Plugins/Instruction/ARM/EmulateInstructionARM.h?rev=126267&r1=126266&r2=126267&view=diff ============================================================================== --- lldb/trunk/source/Plugins/Instruction/ARM/EmulateInstructionARM.h (original) +++ lldb/trunk/source/Plugins/Instruction/ARM/EmulateInstructionARM.h Tue Feb 22 18:07:09 2011 @@ -653,21 +653,21 @@ bool EmulatePLIRegister (ARMEncoding encoding); - // A8.6.141 RSB (immediate) - Encoding T1, A1 + // A8.6.141 RSB (immediate) bool EmulateRSBImm (ARMEncoding encoding); - // A8.6.142 RSB (register) - Encoding A1 + // A8.6.142 RSB (register) bool EmulateRSBReg (ARMEncoding encoding); - // A8.6.144 RSC (immediate) - Encoding A1 + // A8.6.144 RSC (immediate) bool - EmulateRSCImmediate (ARMEncoding encoding); + EmulateRSCImm (ARMEncoding encoding); - // A8.6.145 RSC (register) - Encoding A1 + // A8.6.145 RSC (register) bool - EmulateRSCRegister (ARMEncoding encoding); + EmulateRSCReg (ARMEncoding encoding); // A8.6.150 SBC (immediate) - Encoding A1 bool From johnny.chen at apple.com Tue Feb 22 18:15:56 2011 From: johnny.chen at apple.com (Johnny Chen) Date: Wed, 23 Feb 2011 00:15:56 -0000 Subject: [Lldb-commits] [lldb] r126271 - in /lldb/trunk/source/Plugins: Instruction/ARM/EmulateInstructionARM.cpp Process/Utility/ARMDefines.h Message-ID: <20110223001556.6AA0B2A6C12D@llvm.org> Author: johnny Date: Tue Feb 22 18:15:56 2011 New Revision: 126271 URL: http://llvm.org/viewvc/llvm-project?rev=126271&view=rev Log: Renamed macro definition of CPSR_C to be CPSR_C_POS to avoid confusions and subtle bugs. Modified: lldb/trunk/source/Plugins/Instruction/ARM/EmulateInstructionARM.cpp lldb/trunk/source/Plugins/Process/Utility/ARMDefines.h Modified: lldb/trunk/source/Plugins/Instruction/ARM/EmulateInstructionARM.cpp URL: http://llvm.org/viewvc/llvm-project/lldb/trunk/source/Plugins/Instruction/ARM/EmulateInstructionARM.cpp?rev=126271&r1=126270&r2=126271&view=diff ============================================================================== --- lldb/trunk/source/Plugins/Instruction/ARM/EmulateInstructionARM.cpp (original) +++ lldb/trunk/source/Plugins/Instruction/ARM/EmulateInstructionARM.cpp Tue Feb 22 18:15:56 2011 @@ -24,8 +24,8 @@ using namespace lldb_private; // Convenient macro definitions. -#define APSR_C Bit32(m_inst_cpsr, CPSR_C) -#define APSR_V Bit32(m_inst_cpsr, CPSR_V) +#define APSR_C Bit32(m_inst_cpsr, CPSR_C_POS) +#define APSR_V Bit32(m_inst_cpsr, CPSR_V_POS) #define AlignPC(pc_val) (pc_val & 0xFFFFFFFC) @@ -7226,12 +7226,12 @@ const uint32_t overflow) { m_new_inst_cpsr = m_inst_cpsr; - SetBit32(m_new_inst_cpsr, CPSR_N, Bit32(result, CPSR_N)); - SetBit32(m_new_inst_cpsr, CPSR_Z, result == 0 ? 1 : 0); + SetBit32(m_new_inst_cpsr, CPSR_N_POS, Bit32(result, CPSR_N_POS)); + SetBit32(m_new_inst_cpsr, CPSR_Z_POS, result == 0 ? 1 : 0); if (carry != ~0u) - SetBit32(m_new_inst_cpsr, CPSR_C, carry); + SetBit32(m_new_inst_cpsr, CPSR_C_POS, carry); if (overflow != ~0u) - SetBit32(m_new_inst_cpsr, CPSR_V, overflow); + SetBit32(m_new_inst_cpsr, CPSR_V_POS, overflow); if (m_new_inst_cpsr != m_inst_cpsr) { if (!WriteRegisterUnsigned (context, eRegisterKindGeneric, LLDB_REGNUM_GENERIC_FLAGS, m_new_inst_cpsr)) Modified: lldb/trunk/source/Plugins/Process/Utility/ARMDefines.h URL: http://llvm.org/viewvc/llvm-project/lldb/trunk/source/Plugins/Process/Utility/ARMDefines.h?rev=126271&r1=126270&r2=126271&view=diff ============================================================================== --- lldb/trunk/source/Plugins/Process/Utility/ARMDefines.h (original) +++ lldb/trunk/source/Plugins/Process/Utility/ARMDefines.h Tue Feb 22 18:15:56 2011 @@ -67,32 +67,32 @@ } // Bit positions for CPSR -#define CPSR_T 5 -#define CPSR_F 6 -#define CPSR_I 7 -#define CPSR_A 8 -#define CPSR_E 9 -#define CPSR_J 24 -#define CPSR_Q 27 -#define CPSR_V 28 -#define CPSR_C 29 -#define CPSR_Z 30 -#define CPSR_N 31 +#define CPSR_T_POS 5 +#define CPSR_F_POS 6 +#define CPSR_I_POS 7 +#define CPSR_A_POS 8 +#define CPSR_E_POS 9 +#define CPSR_J_POS 24 +#define CPSR_Q_POS 27 +#define CPSR_V_POS 28 +#define CPSR_C_POS 29 +#define CPSR_Z_POS 30 +#define CPSR_N_POS 31 // Masks for CPSR #define MASK_CPSR_MODE_MASK (0x0000001fu) -#define MASK_CPSR_T (1u << CPSR_T) -#define MASK_CPSR_F (1u << CPSR_F) -#define MASK_CPSR_I (1u << CPSR_I) -#define MASK_CPSR_A (1u << CPSR_A) -#define MASK_CPSR_E (1u << CPSR_E) +#define MASK_CPSR_T (1u << CPSR_T_POS) +#define MASK_CPSR_F (1u << CPSR_F_POS) +#define MASK_CPSR_I (1u << CPSR_I_POS) +#define MASK_CPSR_A (1u << CPSR_A_POS) +#define MASK_CPSR_E (1u << CPSR_E_POS) #define MASK_CPSR_GE_MASK (0x000f0000u) -#define MASK_CPSR_J (1u << CPSR_J) -#define MASK_CPSR_Q (1u << CPSR_Q) -#define MASK_CPSR_V (1u << CPSR_V) -#define MASK_CPSR_C (1u << CPSR_C) -#define MASK_CPSR_Z (1u << CPSR_Z) -#define MASK_CPSR_N (1u << CPSR_N) +#define MASK_CPSR_J (1u << CPSR_J_POS) +#define MASK_CPSR_Q (1u << CPSR_Q_POS) +#define MASK_CPSR_V (1u << CPSR_V_POS) +#define MASK_CPSR_C (1u << CPSR_C_POS) +#define MASK_CPSR_Z (1u << CPSR_Z_POS) +#define MASK_CPSR_N (1u << CPSR_N_POS) } // namespace lldb_private From gclayton at apple.com Tue Feb 22 18:35:02 2011 From: gclayton at apple.com (Greg Clayton) Date: Wed, 23 Feb 2011 00:35:02 -0000 Subject: [Lldb-commits] [lldb] r126278 - in /lldb/trunk: include/lldb/Core/ include/lldb/Target/ lldb.xcodeproj/xcshareddata/xcschemes/ source/API/ source/Commands/ source/Core/ source/Expression/ source/Host/common/ source/Host/macosx/ source/Plugins/Disassembler/llvm/ source/Plugins/Instruction/ARM/ source/Plugins/ObjectContainer/BSD-Archive/ source/Plugins/ObjectContainer/Universal-Mach-O/ source/Plugins/ObjectFile/ELF/ source/Plugins/ObjectFile/Mach-O/ source/Plugins/Process/MacOSX-User/source/ source/Plugins/Process/MacOSX... Message-ID: <20110223003502.CB25B2A6C12C@llvm.org> Author: gclayton Date: Tue Feb 22 18:35:02 2011 New Revision: 126278 URL: http://llvm.org/viewvc/llvm-project?rev=126278&view=rev Log: Abtracted all mach-o and ELF out of ArchSpec. This patch is a modified form of Stephen Wilson's idea (thanks for the input Stephen!). What I ended up doing was: - Got rid of ArchSpec::CPU (which was a generic CPU enumeration that mimics the contents of llvm::Triple::ArchType). We now rely upon the llvm::Triple to give us the machine type from llvm::Triple::ArchType. - There is a new ArchSpec::Core definition which further qualifies the CPU core we are dealing with into a single enumeration. If you need support for a new Core and want to debug it in LLDB, it must be added to this list. In the future we can allow for dynamic core registration, but for now it is hard coded. - The ArchSpec can now be initialized with a llvm::Triple or with a C string that represents the triple (it can just be an arch still like "i386"). - The ArchSpec can still initialize itself with a architecture type -- mach-o with cpu type and subtype, or ELF with e_machine + e_flags -- and this will then get translated into the internal llvm::Triple::ArchSpec + ArchSpec::Core. The mach-o cpu type and subtype can be accessed using the getter functions: uint32_t ArchSpec::GetMachOCPUType () const; uint32_t ArchSpec::GetMachOCPUSubType () const; But these functions are just converting out internal llvm::Triple::ArchSpec + ArchSpec::Core back into mach-o. Same goes for ELF. All code has been updated to deal with the changes. This should abstract us until later when the llvm::TargetSpec stuff gets finalized and we can then adopt it. Modified: lldb/trunk/include/lldb/Core/ArchSpec.h lldb/trunk/include/lldb/Target/Target.h lldb/trunk/lldb.xcodeproj/xcshareddata/xcschemes/lldb-tool.xcscheme lldb/trunk/source/API/SBDebugger.cpp lldb/trunk/source/Commands/CommandObjectDisassemble.cpp lldb/trunk/source/Commands/CommandObjectFile.cpp lldb/trunk/source/Commands/CommandObjectImage.cpp lldb/trunk/source/Commands/CommandObjectProcess.cpp lldb/trunk/source/Core/ArchSpec.cpp lldb/trunk/source/Core/Debugger.cpp lldb/trunk/source/Core/Disassembler.cpp lldb/trunk/source/Core/Log.cpp lldb/trunk/source/Core/Module.cpp lldb/trunk/source/Core/ModuleList.cpp lldb/trunk/source/Expression/ClangExpressionParser.cpp lldb/trunk/source/Host/common/Host.cpp lldb/trunk/source/Host/macosx/Host.mm lldb/trunk/source/Host/macosx/Symbols.cpp lldb/trunk/source/Plugins/Disassembler/llvm/DisassemblerLLVM.cpp lldb/trunk/source/Plugins/Instruction/ARM/EmulateInstructionARM.cpp lldb/trunk/source/Plugins/ObjectContainer/BSD-Archive/ObjectContainerBSDArchive.cpp lldb/trunk/source/Plugins/ObjectContainer/Universal-Mach-O/ObjectContainerUniversalMachO.cpp lldb/trunk/source/Plugins/ObjectFile/ELF/ObjectFileELF.cpp lldb/trunk/source/Plugins/ObjectFile/Mach-O/ObjectFileMachO.cpp lldb/trunk/source/Plugins/Process/MacOSX-User/source/MacOSX/MachThreadContext_i386.cpp lldb/trunk/source/Plugins/Process/MacOSX-User/source/MacOSX/MachThreadContext_x86_64.cpp lldb/trunk/source/Plugins/Process/MacOSX-User/source/ProcessMacOSX.cpp lldb/trunk/source/Plugins/Process/Utility/ArchDefaultUnwindPlan-x86.cpp lldb/trunk/source/Plugins/Process/Utility/ArchVolatileRegs-x86.cpp lldb/trunk/source/Plugins/Process/Utility/ArchVolatileRegs-x86.h lldb/trunk/source/Plugins/Process/Utility/StopInfoMachException.cpp lldb/trunk/source/Plugins/Process/Utility/UnwindAssemblyProfiler-x86.cpp lldb/trunk/source/Plugins/Process/Utility/UnwindMacOSXFrameBackchain.cpp lldb/trunk/source/Plugins/Process/gdb-remote/GDBRemoteCommunication.cpp lldb/trunk/source/Plugins/Process/gdb-remote/ProcessGDBRemote.cpp lldb/trunk/source/Plugins/Process/gdb-remote/ThreadGDBRemote.cpp lldb/trunk/source/Symbol/SymbolContext.cpp lldb/trunk/source/Target/Target.cpp lldb/trunk/source/Target/TargetList.cpp lldb/trunk/test/dotest.py Modified: lldb/trunk/include/lldb/Core/ArchSpec.h URL: http://llvm.org/viewvc/llvm-project/lldb/trunk/include/lldb/Core/ArchSpec.h?rev=126278&r1=126277&r2=126278&view=diff ============================================================================== --- lldb/trunk/include/lldb/Core/ArchSpec.h (original) +++ lldb/trunk/include/lldb/Core/ArchSpec.h Tue Feb 22 18:35:02 2011 @@ -13,37 +13,86 @@ #if defined(__cplusplus) #include "lldb/lldb-private.h" +#include "llvm/ADT/StringRef.h" #include "llvm/ADT/Triple.h" namespace lldb_private { +struct CoreDefinition; + //---------------------------------------------------------------------- /// @class ArchSpec ArchSpec.h "lldb/Core/ArchSpec.h" /// @brief An architecture specification class. /// -/// A class designed to be created from a cpu type and subtype, or a -/// string representation. Keeping all of the conversions of strings -/// to architecture enumeration values confined to this class allows -/// new architecture support to be added easily. +/// A class designed to be created from a cpu type and subtype, a +/// string representation, or an llvm::Triple. Keeping all of the +/// conversions of strings to architecture enumeration values confined +/// to this class allows new architecture support to be added easily. //---------------------------------------------------------------------- class ArchSpec { public: - // Generic CPU types that each m_type needs to know how to convert - // their m_cpu and m_sub to. - enum CPU + enum Core { - eCPU_Unknown, - eCPU_arm, - eCPU_i386, - eCPU_x86_64, - eCPU_ppc, - eCPU_ppc64, - eCPU_sparc + eCore_alpha_generic, + + eCore_arm_generic, + eCore_arm_armv4, + eCore_arm_armv4t, + eCore_arm_armv5, + eCore_arm_armv5t, + eCore_arm_armv6, + eCore_arm_armv7, + eCore_arm_xscale, + + eCore_ppc_generic, + eCore_ppc_ppc601, + eCore_ppc_ppc602, + eCore_ppc_ppc603, + eCore_ppc_ppc603e, + eCore_ppc_ppc603ev, + eCore_ppc_ppc604, + eCore_ppc_ppc604e, + eCore_ppc_ppc620, + eCore_ppc_ppc750, + eCore_ppc_ppc7400, + eCore_ppc_ppc7450, + eCore_ppc_ppc970, + + eCore_ppc64_generic, + eCore_ppc64_ppc970_64, + + eCore_sparc_generic, + + eCore_sparc9_generic, + + eCore_x86_32_i386, + eCore_x86_32_i486, + eCore_x86_32_i486sx, + + eCore_x86_64_x86_64, + kNumCores, + + kCore_invalid, + // The following constants are used for wildcard matching only + kCore_any, + + kCore_arm_any, + kCore_arm_first = eCore_arm_generic, + kCore_arm_last = eCore_arm_xscale, + + kCore_ppc_any, + kCore_ppc_first = eCore_ppc_generic, + kCore_ppc_last = eCore_ppc_ppc970, + + kCore_ppc64_any, + kCore_ppc64_first = eCore_ppc64_generic, + kCore_ppc64_last = eCore_ppc64_ppc970_64, + + kCore_x86_32_any, + kCore_x86_32_first = eCore_x86_32_i386, + kCore_x86_32_last = eCore_x86_32_i486sx }; - - static void - Initialize(); //------------------------------------------------------------------ /// Default constructor. @@ -54,30 +103,22 @@ ArchSpec (); //------------------------------------------------------------------ - /// Constructor with cpu type and subtype. + /// Constructor over triple. /// - /// Constructor that initializes the object with supplied cpu and - /// subtypes. + /// Constructs an ArchSpec with properties consistent with the given + /// Triple. //------------------------------------------------------------------ - ArchSpec (lldb::ArchitectureType arch_type, uint32_t cpu, uint32_t sub); - + ArchSpec (const llvm::Triple &triple); + ArchSpec (const char *triple_cstr); //------------------------------------------------------------------ - /// Construct with architecture name. + /// Constructor over architecture name. /// - /// Constructor that initializes the object with supplied - /// architecture name. There are also predefined values in - /// Defines.h: - /// @li \c LLDB_ARCH_DEFAULT - /// The arch the current system defaults to when a program is - /// launched without any extra attributes or settings. - /// - /// @li \c LLDB_ARCH_DEFAULT_32BIT - /// The 32 bit arch the current system defaults to (if any) - /// - /// @li \c LLDB_ARCH_DEFAULT_32BIT - /// The 64 bit arch the current system defaults to (if any) + /// Constructs an ArchSpec with properties consistent with the given + /// object type and architecture name. //------------------------------------------------------------------ - ArchSpec (const char *arch_name); + ArchSpec (lldb::ArchitectureType arch_type, + uint32_t cpu_type, + uint32_t cpu_subtype); //------------------------------------------------------------------ /// Destructor. @@ -92,40 +133,19 @@ /// /// @param[in] rhs another ArchSpec object to copy. /// - /// @return a const reference to this object + /// @return A const reference to this object. //------------------------------------------------------------------ const ArchSpec& operator= (const ArchSpec& rhs); //------------------------------------------------------------------ - /// Get a string representation of the contained architecture. - /// - /// Gets a C string representation of the current architecture. - /// If the returned string is a valid architecture name, the string - /// came from a constant string values that do not need to be freed. - /// If the returned string uses the "N.M" format, the string comes - /// from a static buffer that should be copied. + /// Returns a static string representing the current architecture. /// - /// @return a NULL terminated C string that does not need to be - /// freed. + /// @return A static string correcponding to the current + /// architecture. //------------------------------------------------------------------ const char * - AsCString () const; - - //------------------------------------------------------------------ - /// Returns a string representation of the supplied architecture. - /// - /// Class function to get a C string representation given a CPU type - /// and subtype. - /// - /// @param[in] cpu The cpu type of the architecture. - /// @param[in] subtype The cpu subtype of the architecture. - /// - /// @return a NULL terminated C string that does not need to be - /// freed. - //------------------------------------------------------------------ - static const char * - AsCString (lldb::ArchitectureType arch_type, uint32_t cpu, uint32_t subtype); + GetArchitectureName () const; //------------------------------------------------------------------ /// Clears the object state. @@ -144,107 +164,33 @@ uint32_t GetAddressByteSize () const; - void - SetAddressByteSize (uint32_t byte_size) - { - m_addr_byte_size = byte_size; - } - - CPU - GetGenericCPUType () const; - //------------------------------------------------------------------ - /// CPU subtype get accessor. + /// Returns a machine family for the current architecture. /// - /// @return The current value of the CPU subtype. + /// @return An LLVM arch type. //------------------------------------------------------------------ - uint32_t - GetCPUSubtype () const; + llvm::Triple::ArchType + GetMachine () const; //------------------------------------------------------------------ - /// CPU type get accessor. + /// Tests if this ArchSpec is valid. /// - /// @return The current value of the CPU type. - //------------------------------------------------------------------ - uint32_t - GetCPUType () const; - - //------------------------------------------------------------------ - /// Feature flags get accessor. - /// - /// @return The current value of the CPU feature flags. - //------------------------------------------------------------------ - uint32_t - GetFeatureFlags () const; - - //------------------------------------------------------------------ - /// Get register names of the current architecture. - /// - /// Get register names of the current architecture given - /// a register number, and a flavor for that register number. - /// There are many different register numbering schemes used - /// on a host: - /// @li \c eRegisterKindGCC - gcc compiler register numbering - /// @li \c eRegisterKindDWARF - DWARF register numbering - /// - /// @param[in] reg_num The register number to decode. - /// @param[in] flavor The flavor of the \a reg_num. - /// - /// @return the name of the register as a NULL terminated C string, - /// or /c NULL if the \a reg_num is invalid for \a flavor. - /// String values that are returned do not need to be freed. - //------------------------------------------------------------------ - const char * - GetRegisterName (uint32_t reg_num, uint32_t flavor) const; - - //------------------------------------------------------------------ - /// Get register names for a specified architecture. - /// - /// Get register names of the specified architecture given - /// a register number, and a flavor for that register number. - /// There are many different register numbering schemes used - /// on a host: - /// - /// @li compiler register numbers (@see eRegisterKindGCC) - /// @li DWARF register numbers (@see eRegisterKindDWARF) - /// - /// @param[in] cpu The cpu type of the architecture specific - /// register - /// @param[in] subtype The cpu subtype of the architecture specific - /// register - /// @param[in] reg_num The register number to decode. - /// @param[in] flavor The flavor of the \a reg_num. - /// - /// @return the name of the register as a NULL terminated C string, - /// or /c NULL if the \a reg_num is invalid for \a flavor. - /// String values that are returned do not need to be freed. - //------------------------------------------------------------------ - static const char * - GetRegisterName (lldb::ArchitectureType arch_type, uint32_t cpu, uint32_t subtype, uint32_t reg_num, uint32_t flavor); - - //------------------------------------------------------------------ - /// Test if the contained architecture is valid. - /// - /// @return true if the current architecture is valid, false + /// @return True if the current architecture is valid, false /// otherwise. //------------------------------------------------------------------ bool - IsValid () const; + IsValid () const + { + return m_core >= eCore_alpha_generic && m_core < kNumCores; + } - //------------------------------------------------------------------ - /// Get the memory cost of this object. - /// - /// @return - /// The number of bytes that this object occupies in memory. - //------------------------------------------------------------------ - size_t - MemorySize() const; //------------------------------------------------------------------ - /// Change the CPU type and subtype given an architecture name. + /// Sets this ArchSpec according to the given architecture name. + /// + /// The architecture name can be one of the generic system default + /// values: /// - /// The architecture name supplied can also by one of the generic - /// system default values: /// @li \c LLDB_ARCH_DEFAULT - The arch the current system defaults /// to when a program is launched without any extra /// attributes or settings. @@ -253,25 +199,43 @@ /// @li \c LLDB_ARCH_DEFAULT_64BIT - The default host architecture /// for 64 bit (if any). /// + /// Alternatively, if the object type of this ArchSpec has been + /// configured, a concrete architecture can be specified to set + /// the CPU type ("x86_64" for example). + /// + /// Finally, an encoded object and archetecture format is accepted. + /// The format contains an object type (like "macho" or "elf"), + /// followed by a platform dependent encoding of CPU type and + /// subtype. For example: + /// + /// "macho" : Specifies an object type of MachO. + /// "macho-16-6" : MachO specific encoding for ARMv6. + /// "elf-43 : ELF specific encoding for Sparc V9. + /// /// @param[in] arch_name The name of an architecture. /// - /// @return true if \a arch_name was successfully transformed into - /// a valid cpu type and subtype. + /// @return True if @p arch_name was successfully translated, false + /// otherwise. //------------------------------------------------------------------ - bool - SetArch (const char *arch_name); - - bool - SetArchFromTargetTriple (const char *arch_name); +// bool +// SetArchitecture (const llvm::StringRef& arch_name); +// +// bool +// SetArchitecture (const char *arch_name); + //------------------------------------------------------------------ - /// Change the CPU type and subtype given new values of the cpu - /// type and subtype. + /// Change the architecture object type and CPU type. /// - /// @param[in] cpu The new CPU type - /// @param[in] subtype The new CPU subtype + /// @param[in] arch_type The object type of this ArchSpec. + /// + /// @param[in] cpu The required CPU type. + /// + /// @return True if the object and CPU type were sucessfully set. //------------------------------------------------------------------ - void - SetMachOArch (uint32_t cpu, uint32_t sub); + bool + SetArchitecture (lldb::ArchitectureType arch_type, + uint32_t cpu, + uint32_t sub); //------------------------------------------------------------------ /// Returns the byte order for the architecture specification. @@ -280,78 +244,88 @@ /// the architecture specification //------------------------------------------------------------------ lldb::ByteOrder - GetByteOrder () const - { - return m_byte_order; - } + GetByteOrder () const; + //------------------------------------------------------------------ + /// Sets this ArchSpec's byte order. + /// + /// In the common case there is no need to call this method as the + /// byte order can almost always be determined by the architecture. + /// However, many CPU's are bi-endian (ARM, Alpha, PowerPC, etc) + /// and the default/assumed byte order may be incorrect. + //------------------------------------------------------------------ void - SetByteOrder (lldb::ByteOrder b) + SetByteOrder (lldb::ByteOrder byteorder); + + Core + GetCore () const { - m_byte_order = b; + return m_core; } + uint32_t + GetMachOCPUType () const; + + uint32_t + GetMachOCPUSubType () const; + + //------------------------------------------------------------------ + /// Architecture tripple accessor. + /// + /// @return A triple describing this ArchSpec. + //------------------------------------------------------------------ llvm::Triple & GetTriple () { return m_triple; } - + + //------------------------------------------------------------------ + /// Architecture tripple accessor. + /// + /// @return A triple describing this ArchSpec. + //------------------------------------------------------------------ const llvm::Triple & GetTriple () const { return m_triple; } - - void - SetTriple (const llvm::Triple &triple) - { - m_triple = triple; - } - void - SetElfArch (uint32_t cpu, uint32_t sub) - { - m_type = lldb::eArchTypeELF; - m_cpu = cpu; - m_sub = sub; - } + //------------------------------------------------------------------ + /// Architecture tripple setter. + /// + /// Configures this ArchSpec according to the given triple. At a + /// minimum, the given triple must describe a valid operating + /// system. If archetecture or environment components are present + /// they too will be used to further resolve the CPU type and + /// subtype, endian characteristics, etc. + /// + /// @return A triple describing this ArchSpec. + //------------------------------------------------------------------ + bool + SetTriple (const llvm::Triple &triple); + bool + SetTriple (const char *triple_cstr); + //------------------------------------------------------------------ /// Returns the default endianness of the architecture. /// /// @return The endian enumeration for the default endianness of - /// the architecture. + /// the architecture. //------------------------------------------------------------------ lldb::ByteOrder GetDefaultEndian () const; - - lldb::ArchitectureType - GetType() const - { - return m_type; - } - protected: - //------------------------------------------------------------------ - // Member variables - //------------------------------------------------------------------ - lldb::ArchitectureType m_type; - // m_type => eArchTypeMachO eArchTypeELF - uint32_t m_cpu; // cpu type ELF header e_machine - uint32_t m_sub; // cpu subtype nothing llvm::Triple m_triple; + Core m_core; lldb::ByteOrder m_byte_order; - uint32_t m_addr_byte_size; - -private: - - void - MachOArchUpdated (size_t macho_idx = ~(size_t)0); - + + // Called when m_def or m_entry are changed. Fills in all remaining + // members with default values. void - ELFArchUpdated (size_t idx = ~(size_t)0); + CoreUpdated (bool update_triple); }; Modified: lldb/trunk/include/lldb/Target/Target.h URL: http://llvm.org/viewvc/llvm-project/lldb/trunk/include/lldb/Target/Target.h?rev=126278&r1=126277&r2=126278&view=diff ============================================================================== --- lldb/trunk/include/lldb/Target/Target.h (original) +++ lldb/trunk/include/lldb/Target/Target.h Tue Feb 22 18:35:02 2011 @@ -153,7 +153,7 @@ GetDefaultArchitecture (); static void - SetDefaultArchitecture (ArchSpec new_arch); + SetDefaultArchitecture (const ArchSpec &arch); void UpdateInstanceName (); @@ -534,6 +534,11 @@ static SettingEntry global_settings_table[]; static SettingEntry instance_settings_table[]; + ArchSpec & + GetArchitecture () + { + return m_default_architecture; + } protected: lldb::InstanceSettingsSP Modified: lldb/trunk/lldb.xcodeproj/xcshareddata/xcschemes/lldb-tool.xcscheme URL: http://llvm.org/viewvc/llvm-project/lldb/trunk/lldb.xcodeproj/xcshareddata/xcschemes/lldb-tool.xcscheme?rev=126278&r1=126277&r2=126278&view=diff ============================================================================== --- lldb/trunk/lldb.xcodeproj/xcshareddata/xcschemes/lldb-tool.xcscheme (original) +++ lldb/trunk/lldb.xcodeproj/xcshareddata/xcschemes/lldb-tool.xcscheme Tue Feb 22 18:35:02 2011 @@ -72,11 +72,11 @@ @@ -88,6 +88,20 @@ ReferencedContainer = "container:lldb.xcodeproj"> + + + + + + + + GetTargetList().CreateTarget (*m_opaque_sp, file_spec, arch, NULL, true, target_sp)); target.reset (target_sp); @@ -440,7 +440,7 @@ } SBTarget -SBDebugger::CreateTargetWithFileAndArch (const char *filename, const char *archname) +SBDebugger::CreateTargetWithFileAndArch (const char *filename, const char *arch_cstr) { LogSP log(lldb_private::GetLogIfAllCategoriesSet (LIBLLDB_LOG_API)); @@ -448,31 +448,28 @@ if (m_opaque_sp) { FileSpec file (filename, true); - ArchSpec arch = lldb_private::Target::GetDefaultArchitecture (); + ArchSpec arch; TargetSP target_sp; Error error; - if (archname != NULL) - { - ArchSpec arch2 (archname); - error = m_opaque_sp->GetTargetList().CreateTarget (*m_opaque_sp, file, arch2, NULL, true, target_sp); - } + if (arch_cstr) + arch.SetTriple (arch_cstr); else - { - if (!arch.IsValid()) - arch = LLDB_ARCH_DEFAULT; + arch = lldb_private::Target::GetDefaultArchitecture (); - error = m_opaque_sp->GetTargetList().CreateTarget (*m_opaque_sp, file, arch, NULL, true, target_sp); + if (!arch.IsValid()) + arch.SetTriple (LLDB_ARCH_DEFAULT); - if (error.Fail()) - { - if (arch == LLDB_ARCH_DEFAULT_32BIT) - arch = LLDB_ARCH_DEFAULT_64BIT; - else - arch = LLDB_ARCH_DEFAULT_32BIT; + error = m_opaque_sp->GetTargetList().CreateTarget (*m_opaque_sp, file, arch, NULL, true, target_sp); - error = m_opaque_sp->GetTargetList().CreateTarget (*m_opaque_sp, file, arch, NULL, true, target_sp); - } + if (error.Fail()) + { + if (strcmp (LLDB_ARCH_DEFAULT, LLDB_ARCH_DEFAULT_32BIT) == 0) + arch.SetTriple (LLDB_ARCH_DEFAULT_64BIT); + else + arch.SetTriple (LLDB_ARCH_DEFAULT_32BIT); + + error = m_opaque_sp->GetTargetList().CreateTarget (*m_opaque_sp, file, arch, NULL, true, target_sp); } if (error.Success()) @@ -485,7 +482,7 @@ if (log) { log->Printf ("SBDebugger(%p)::CreateTargetWithFileAndArch (filename=\"%s\", arch=%s) => SBTarget(%p)", - m_opaque_sp.get(), filename, archname, target.get()); + m_opaque_sp.get(), filename, arch_cstr, target.get()); } return target; @@ -503,16 +500,16 @@ Error error; if (!arch.IsValid()) - arch = LLDB_ARCH_DEFAULT; + arch.SetTriple (LLDB_ARCH_DEFAULT); error = m_opaque_sp->GetTargetList().CreateTarget (*m_opaque_sp, file, arch, NULL, true, target_sp); if (error.Fail()) { - if (arch == LLDB_ARCH_DEFAULT_32BIT) - arch = LLDB_ARCH_DEFAULT_64BIT; + if (strcmp (LLDB_ARCH_DEFAULT, LLDB_ARCH_DEFAULT_32BIT) == 0) + arch.SetTriple (LLDB_ARCH_DEFAULT_64BIT); else - arch = LLDB_ARCH_DEFAULT_32BIT; + arch.SetTriple (LLDB_ARCH_DEFAULT_32BIT); error = m_opaque_sp->GetTargetList().CreateTarget (*m_opaque_sp, file, arch, NULL, true, target_sp); } @@ -563,9 +560,7 @@ if (m_opaque_sp && filename && filename[0]) { // No need to lock, the target list is thread safe - ArchSpec arch; - if (arch_name) - arch.SetArch(arch_name); + ArchSpec arch (arch_name); TargetSP target_sp (m_opaque_sp->GetTargetList().FindTargetWithExecutableAndArchitecture (FileSpec(filename, false), arch_name ? &arch : NULL)); sb_target.reset(target_sp); } Modified: lldb/trunk/source/Commands/CommandObjectDisassemble.cpp URL: http://llvm.org/viewvc/llvm-project/lldb/trunk/source/Commands/CommandObjectDisassemble.cpp?rev=126278&r1=126277&r2=126278&view=diff ============================================================================== --- lldb/trunk/source/Commands/CommandObjectDisassemble.cpp (original) +++ lldb/trunk/source/Commands/CommandObjectDisassemble.cpp Tue Feb 22 18:35:02 2011 @@ -185,7 +185,7 @@ if (disassembler == NULL) { - result.AppendErrorWithFormat ("Unable to find Disassembler plug-in for %s architecture.\n", arch.AsCString()); + result.AppendErrorWithFormat ("Unable to find Disassembler plug-in for %s architecture.\n", arch.GetArchitectureName()); result.SetStatus (eReturnStatusFailed); return false; } Modified: lldb/trunk/source/Commands/CommandObjectFile.cpp URL: http://llvm.org/viewvc/llvm-project/lldb/trunk/source/Commands/CommandObjectFile.cpp?rev=126278&r1=126277&r2=126278&view=diff ============================================================================== --- lldb/trunk/source/Commands/CommandObjectFile.cpp (original) +++ lldb/trunk/source/Commands/CommandObjectFile.cpp Tue Feb 22 18:35:02 2011 @@ -145,7 +145,7 @@ if (target_sp) { debugger.GetTargetList().SetSelectedTarget(target_sp.get()); - result.AppendMessageWithFormat ("Current executable set to '%s' (%s).\n", file_path, target_sp->GetArchitecture().AsCString()); + result.AppendMessageWithFormat ("Current executable set to '%s' (%s).\n", file_path, target_sp->GetArchitecture().GetArchitectureName()); result.SetStatus (eReturnStatusSuccessFinishNoResult); } else Modified: lldb/trunk/source/Commands/CommandObjectImage.cpp URL: http://llvm.org/viewvc/llvm-project/lldb/trunk/source/Commands/CommandObjectImage.cpp?rev=126278&r1=126277&r2=126278&view=diff ============================================================================== --- lldb/trunk/source/Commands/CommandObjectImage.cpp (original) +++ lldb/trunk/source/Commands/CommandObjectImage.cpp Tue Feb 22 18:35:02 2011 @@ -42,9 +42,9 @@ if (module) { if (width) - strm.Printf("%-*s", width, module->GetArchitecture().AsCString()); + strm.Printf("%-*s", width, module->GetArchitecture().GetArchitectureName()); else - strm.PutCString(module->GetArchitecture().AsCString()); + strm.PutCString(module->GetArchitecture().GetArchitectureName()); } } @@ -183,7 +183,7 @@ { strm.PutCString ("Sections for '"); strm << module->GetFileSpec(); - strm.Printf ("' (%s):\n", module->GetArchitecture().AsCString()); + strm.Printf ("' (%s):\n", module->GetArchitecture().GetArchitectureName()); strm.IndentMore(); section_list->Dump(&strm, interpreter.GetDebugger().GetExecutionContext().target, true, UINT32_MAX); strm.IndentLess(); Modified: lldb/trunk/source/Commands/CommandObjectProcess.cpp URL: http://llvm.org/viewvc/llvm-project/lldb/trunk/source/Commands/CommandObjectProcess.cpp?rev=126278&r1=126277&r2=126278&view=diff ============================================================================== --- lldb/trunk/source/Commands/CommandObjectProcess.cpp (original) +++ lldb/trunk/source/Commands/CommandObjectProcess.cpp Tue Feb 22 18:35:02 2011 @@ -310,7 +310,7 @@ if (error.Success()) { - const char *archname = exe_module->GetArchitecture().AsCString(); + const char *archname = exe_module->GetArchitecture().GetArchitectureName(); result.AppendMessageWithFormat ("Process %i launched: '%s' (%s)\n", process->GetID(), filename, archname); result.SetDidChangeProcessState (true); @@ -328,7 +328,7 @@ if (synchronous_execution) { state = process->WaitForProcessToStop (NULL); - if (!StateIsStoppedState(state)); + if (!StateIsStoppedState(state)) { result.AppendErrorWithFormat ("Process isn't stopped: %s", StateAsCString(state)); } @@ -777,12 +777,12 @@ if (!old_arch_spec.IsValid()) { - result.AppendMessageWithFormat ("Architecture set to: %s.\n", target->GetArchitecture().AsCString()); + result.AppendMessageWithFormat ("Architecture set to: %s.\n", target->GetArchitecture().GetArchitectureName()); } else if (old_arch_spec != target->GetArchitecture()) { result.AppendWarningWithFormat("Architecture changed from %s to %s.\n", - old_arch_spec.AsCString(), target->GetArchitecture().AsCString()); + old_arch_spec.GetArchitectureName(), target->GetArchitecture().GetArchitectureName()); } } return result.Succeeded(); Modified: lldb/trunk/source/Core/ArchSpec.cpp URL: http://llvm.org/viewvc/llvm-project/lldb/trunk/source/Core/ArchSpec.cpp?rev=126278&r1=126277&r2=126278&view=diff ============================================================================== --- lldb/trunk/source/Core/ArchSpec.cpp (original) +++ lldb/trunk/source/Core/ArchSpec.cpp Tue Feb 22 18:35:02 2011 @@ -21,1937 +21,597 @@ using namespace lldb; using namespace lldb_private; -#define ARCH_SPEC_SEPARATOR_CHAR '-' +#define ARCH_SPEC_SEPARATOR_CHAR '-' +namespace lldb_private { -//---------------------------------------------------------------------- -// A structure that describes all of the information we want to know -// about each architecture. -//---------------------------------------------------------------------- -struct ArchDefinition -{ - ByteOrder byte_order; - uint32_t addr_byte_size; - uint32_t cpu; - uint32_t sub; - const char *name; -}; + struct CoreDefinition + { + ByteOrder default_byte_order; + uint32_t addr_byte_size; + llvm::Triple::ArchType machine; + ArchSpec::Core core; + const char *name; + }; +} -static const char *g_arch_type_strings[] = +// This core information can be looked using the ArchSpec::Core as the index +static const CoreDefinition g_core_definitions[ArchSpec::kNumCores] = { - "invalid", - "mach-o", - "elf" -}; - -#define CPU_ANY (UINT32_MAX) - -//---------------------------------------------------------------------- -// A table that gets searched linearly for matches. This table is used -// to convert cpu type and subtypes to architecture names, and to -// convert architecture names to cpu types and subtypes. The ordering -// is important and allows the precedence to be set when the table is -// built. -//---------------------------------------------------------------------- -static ArchDefinition g_mach_arch_defs[] = -{ - { eByteOrderInvalid, 0, CPU_ANY, CPU_ANY , "all" }, - { eByteOrderLittle, 4, llvm::MachO::CPUTypeARM, CPU_ANY , "arm" }, - { eByteOrderLittle, 4, llvm::MachO::CPUTypeARM, 0 , "arm" }, - { eByteOrderLittle, 4, llvm::MachO::CPUTypeARM, 5 , "armv4" }, - { eByteOrderLittle, 4, llvm::MachO::CPUTypeARM, 6 , "armv6" }, - { eByteOrderLittle, 4, llvm::MachO::CPUTypeARM, 7 , "armv5" }, - { eByteOrderLittle, 4, llvm::MachO::CPUTypeARM, 8 , "xscale" }, - { eByteOrderLittle, 4, llvm::MachO::CPUTypeARM, 9 , "armv7" }, - { eByteOrderBig, 4, llvm::MachO::CPUTypePowerPC, CPU_ANY , "ppc" }, - { eByteOrderBig, 4, llvm::MachO::CPUTypePowerPC, 0 , "ppc" }, - { eByteOrderBig, 4, llvm::MachO::CPUTypePowerPC, 1 , "ppc601" }, - { eByteOrderBig, 4, llvm::MachO::CPUTypePowerPC, 2 , "ppc602" }, - { eByteOrderBig, 4, llvm::MachO::CPUTypePowerPC, 3 , "ppc603" }, - { eByteOrderBig, 4, llvm::MachO::CPUTypePowerPC, 4 , "ppc603e" }, - { eByteOrderBig, 4, llvm::MachO::CPUTypePowerPC, 5 , "ppc603ev" }, - { eByteOrderBig, 4, llvm::MachO::CPUTypePowerPC, 6 , "ppc604" }, - { eByteOrderBig, 4, llvm::MachO::CPUTypePowerPC, 7 , "ppc604e" }, - { eByteOrderBig, 4, llvm::MachO::CPUTypePowerPC, 8 , "ppc620" }, - { eByteOrderBig, 4, llvm::MachO::CPUTypePowerPC, 9 , "ppc750" }, - { eByteOrderBig, 4, llvm::MachO::CPUTypePowerPC, 10 , "ppc7400" }, - { eByteOrderBig, 4, llvm::MachO::CPUTypePowerPC, 11 , "ppc7450" }, - { eByteOrderBig, 4, llvm::MachO::CPUTypePowerPC, 100 , "ppc970" }, - { eByteOrderBig, 8, llvm::MachO::CPUTypePowerPC64, 0 , "ppc64" }, - { eByteOrderBig, 8, llvm::MachO::CPUTypePowerPC64, 100 , "ppc970-64" }, - { eByteOrderLittle, 4, llvm::MachO::CPUTypeI386, 3 , "i386" }, - { eByteOrderLittle, 4, llvm::MachO::CPUTypeI386, 4 , "i486" }, - { eByteOrderLittle, 4, llvm::MachO::CPUTypeI386, 0x84 , "i486sx" }, - { eByteOrderLittle, 4, llvm::MachO::CPUTypeI386, CPU_ANY , "i386" }, - { eByteOrderLittle, 8, llvm::MachO::CPUTypeX86_64, 3 , "x86_64" }, - { eByteOrderLittle, 8, llvm::MachO::CPUTypeX86_64, CPU_ANY , "x86_64" }, -}; - -//---------------------------------------------------------------------- -// Figure out how many architecture definitions we have -//---------------------------------------------------------------------- -const size_t k_num_mach_arch_defs = sizeof(g_mach_arch_defs)/sizeof(ArchDefinition); + { eByteOrderLittle, 4, llvm::Triple::alpha , ArchSpec::eCore_alpha_generic , "alpha" }, + { eByteOrderLittle, 4, llvm::Triple::arm , ArchSpec::eCore_arm_generic , "arm" }, + { eByteOrderLittle, 4, llvm::Triple::arm , ArchSpec::eCore_arm_armv4 , "armv4" }, + { eByteOrderLittle, 4, llvm::Triple::arm , ArchSpec::eCore_arm_armv4t , "armv4t" }, + { eByteOrderLittle, 4, llvm::Triple::arm , ArchSpec::eCore_arm_armv5 , "armv5" }, + { eByteOrderLittle, 4, llvm::Triple::arm , ArchSpec::eCore_arm_armv5t , "armv5t" }, + { eByteOrderLittle, 4, llvm::Triple::arm , ArchSpec::eCore_arm_armv6 , "armv6" }, + { eByteOrderLittle, 4, llvm::Triple::arm , ArchSpec::eCore_arm_armv7 , "armv7" }, + { eByteOrderLittle, 4, llvm::Triple::arm , ArchSpec::eCore_arm_xscale , "xscale" }, + + { eByteOrderLittle, 4, llvm::Triple::ppc , ArchSpec::eCore_ppc_generic , "ppc" }, + { eByteOrderLittle, 4, llvm::Triple::ppc , ArchSpec::eCore_ppc_ppc601 , "ppc601" }, + { eByteOrderLittle, 4, llvm::Triple::ppc , ArchSpec::eCore_ppc_ppc602 , "ppc602" }, + { eByteOrderLittle, 4, llvm::Triple::ppc , ArchSpec::eCore_ppc_ppc603 , "ppc603" }, + { eByteOrderLittle, 4, llvm::Triple::ppc , ArchSpec::eCore_ppc_ppc603e , "ppc603e" }, + { eByteOrderLittle, 4, llvm::Triple::ppc , ArchSpec::eCore_ppc_ppc603ev , "ppc603ev" }, + { eByteOrderLittle, 4, llvm::Triple::ppc , ArchSpec::eCore_ppc_ppc604 , "ppc604" }, + { eByteOrderLittle, 4, llvm::Triple::ppc , ArchSpec::eCore_ppc_ppc604e , "ppc604e" }, + { eByteOrderLittle, 4, llvm::Triple::ppc , ArchSpec::eCore_ppc_ppc620 , "ppc620" }, + { eByteOrderLittle, 4, llvm::Triple::ppc , ArchSpec::eCore_ppc_ppc750 , "ppc750" }, + { eByteOrderLittle, 4, llvm::Triple::ppc , ArchSpec::eCore_ppc_ppc7400 , "ppc7400" }, + { eByteOrderLittle, 4, llvm::Triple::ppc , ArchSpec::eCore_ppc_ppc7450 , "ppc7450" }, + { eByteOrderLittle, 4, llvm::Triple::ppc , ArchSpec::eCore_ppc_ppc970 , "ppc970" }, + + { eByteOrderLittle, 8, llvm::Triple::ppc64 , ArchSpec::eCore_ppc64_generic , "ppc64" }, + { eByteOrderLittle, 8, llvm::Triple::ppc64 , ArchSpec::eCore_ppc64_ppc970_64 , "ppc970-64" }, + + { eByteOrderLittle, 4, llvm::Triple::sparc , ArchSpec::eCore_sparc_generic , "sparc" }, + { eByteOrderLittle, 8, llvm::Triple::sparcv9, ArchSpec::eCore_sparc9_generic , "sparcv9" }, + { eByteOrderLittle, 4, llvm::Triple::x86 , ArchSpec::eCore_x86_32_i386 , "i386" }, + { eByteOrderLittle, 4, llvm::Triple::x86 , ArchSpec::eCore_x86_32_i486 , "i486" }, + { eByteOrderLittle, 4, llvm::Triple::x86 , ArchSpec::eCore_x86_32_i486sx , "i486sx" }, -//---------------------------------------------------------------------- -// A table that gets searched linearly for matches. This table is used -// to convert cpu type and subtypes to architecture names, and to -// convert architecture names to cpu types and subtypes. The ordering -// is important and allows the precedence to be set when the table is -// built. -//---------------------------------------------------------------------- -static ArchDefinition g_elf_arch_defs[] = -{ - { eByteOrderInvalid, 0, llvm::ELF::EM_M32 , 0, "m32" }, // AT&T WE 32100 - { eByteOrderBig, 4, llvm::ELF::EM_SPARC , 0, "sparc" }, // Sparc - { eByteOrderLittle, 4, llvm::ELF::EM_386 , 0, "i386" }, // Intel 80386 - { eByteOrderBig, 4, llvm::ELF::EM_68K , 0, "68k" }, // Motorola 68000 - { eByteOrderBig, 4, llvm::ELF::EM_88K , 0, "88k" }, // Motorola 88000 - { eByteOrderLittle, 4, llvm::ELF::EM_486 , 0, "i486" }, // Intel 486 (deprecated) - { eByteOrderLittle, 4, llvm::ELF::EM_860 , 0, "860" }, // Intel 80860 - { eByteOrderBig, 4, llvm::ELF::EM_MIPS , 0, "rs3000" }, // MIPS RS3000 - { eByteOrderBig, 4, llvm::ELF::EM_PPC , 0, "ppc" }, // PowerPC - { eByteOrderBig, 8, 21 , 0, "ppc64" }, // PowerPC64 - { eByteOrderLittle, 4, llvm::ELF::EM_ARM , 0, "arm" }, // ARM - { eByteOrderLittle, 4, llvm::ELF::EM_ALPHA , 0, "alpha" }, // DEC Alpha - { eByteOrderLittle, 4, llvm::ELF::EM_SPARCV9, 0, "sparc9" }, // SPARC V9 - { eByteOrderLittle, 8, llvm::ELF::EM_X86_64 , 0, "x86_64" }, // AMD64 + { eByteOrderLittle, 8, llvm::Triple::x86_64 , ArchSpec::eCore_x86_64_x86_64 , "x86_64" } }; -//---------------------------------------------------------------------- -// Figure out how many architecture definitions we have -//---------------------------------------------------------------------- -const size_t k_num_elf_arch_defs = sizeof(g_elf_arch_defs)/sizeof(ArchDefinition); - -//---------------------------------------------------------------------- -// Default constructor -//---------------------------------------------------------------------- -ArchSpec::ArchSpec() : - m_type (eArchTypeMachO), // Use the most complete arch definition which will always be translatable to any other ArchitectureType values - m_cpu (LLDB_INVALID_CPUTYPE), - m_sub (0), - m_triple (), - m_byte_order (lldb::endian::InlHostByteOrder()), - m_addr_byte_size (0) +struct ArchDefinitionEntry { -} + ArchSpec::Core core; + uint32_t cpu; + uint32_t sub; +}; -//---------------------------------------------------------------------- -// Constructor that initializes the object with supplied cpu and -// subtypes. -//---------------------------------------------------------------------- -ArchSpec::ArchSpec (lldb::ArchitectureType arch_type, uint32_t cpu, uint32_t sub) : - m_type (arch_type), - m_cpu (cpu), - m_sub (sub), - m_triple (), - m_byte_order (lldb::endian::InlHostByteOrder()), - m_addr_byte_size (0) +struct ArchDefinition { - if (m_type == eArchTypeMachO) - MachOArchUpdated (); -} + ArchitectureType type; + size_t num_entries; + const ArchDefinitionEntry *entries; + uint32_t cpu_mask; + uint32_t sub_mask; + const char *name; +}; -//---------------------------------------------------------------------- -// Constructor that initializes the object with supplied -// architecture name. There are also predefined values in -// Defines.h: -// LLDB_ARCH_DEFAULT -// The arch the current system defaults to when a program is -// launched without any extra attributes or settings. -// -// LLDB_ARCH_DEFAULT_32BIT -// The 32 bit arch the current system defaults to (if any) -// -// LLDB_ARCH_DEFAULT_32BIT -// The 64 bit arch the current system defaults to (if any) -//---------------------------------------------------------------------- -ArchSpec::ArchSpec (const char *arch_name) : - m_type (eArchTypeMachO), // Use the most complete arch definition which will always be translatable to any other ArchitectureType values - m_cpu (LLDB_INVALID_CPUTYPE), - m_sub (0), - m_triple (), - m_byte_order (lldb::endian::InlHostByteOrder()), - m_addr_byte_size (0) -{ - SetArch (arch_name); -} -//---------------------------------------------------------------------- -// Destructor -//---------------------------------------------------------------------- -ArchSpec::~ArchSpec() -{ +#define CPU_ANY (UINT32_MAX) + +//===----------------------------------------------------------------------===// +// A table that gets searched linearly for matches. This table is used to +// convert cpu type and subtypes to architecture names, and to convert +// architecture names to cpu types and subtypes. The ordering is important and +// allows the precedence to be set when the table is built. +static const ArchDefinitionEntry g_macho_arch_entries[] = +{ + { ArchSpec::eCore_arm_generic , llvm::MachO::CPUTypeARM , CPU_ANY }, + { ArchSpec::eCore_arm_generic , llvm::MachO::CPUTypeARM , 0 }, + { ArchSpec::eCore_arm_armv4 , llvm::MachO::CPUTypeARM , 5 }, + { ArchSpec::eCore_arm_armv6 , llvm::MachO::CPUTypeARM , 6 }, + { ArchSpec::eCore_arm_armv5 , llvm::MachO::CPUTypeARM , 7 }, + { ArchSpec::eCore_arm_xscale , llvm::MachO::CPUTypeARM , 8 }, + { ArchSpec::eCore_arm_armv7 , llvm::MachO::CPUTypeARM , 9 }, + { ArchSpec::eCore_ppc_generic , llvm::MachO::CPUTypePowerPC , CPU_ANY }, + { ArchSpec::eCore_ppc_generic , llvm::MachO::CPUTypePowerPC , 0 }, + { ArchSpec::eCore_ppc_ppc601 , llvm::MachO::CPUTypePowerPC , 1 }, + { ArchSpec::eCore_ppc_ppc602 , llvm::MachO::CPUTypePowerPC , 2 }, + { ArchSpec::eCore_ppc_ppc603 , llvm::MachO::CPUTypePowerPC , 3 }, + { ArchSpec::eCore_ppc_ppc603e , llvm::MachO::CPUTypePowerPC , 4 }, + { ArchSpec::eCore_ppc_ppc603ev , llvm::MachO::CPUTypePowerPC , 5 }, + { ArchSpec::eCore_ppc_ppc604 , llvm::MachO::CPUTypePowerPC , 6 }, + { ArchSpec::eCore_ppc_ppc604e , llvm::MachO::CPUTypePowerPC , 7 }, + { ArchSpec::eCore_ppc_ppc620 , llvm::MachO::CPUTypePowerPC , 8 }, + { ArchSpec::eCore_ppc_ppc750 , llvm::MachO::CPUTypePowerPC , 9 }, + { ArchSpec::eCore_ppc_ppc7400 , llvm::MachO::CPUTypePowerPC , 10 }, + { ArchSpec::eCore_ppc_ppc7450 , llvm::MachO::CPUTypePowerPC , 11 }, + { ArchSpec::eCore_ppc_ppc970 , llvm::MachO::CPUTypePowerPC , 100 }, + { ArchSpec::eCore_ppc64_generic , llvm::MachO::CPUTypePowerPC64 , 0 }, + { ArchSpec::eCore_ppc64_ppc970_64 , llvm::MachO::CPUTypePowerPC64 , 100 }, + { ArchSpec::eCore_x86_32_i386 , llvm::MachO::CPUTypeI386 , 3 }, + { ArchSpec::eCore_x86_32_i486 , llvm::MachO::CPUTypeI386 , 4 }, + { ArchSpec::eCore_x86_32_i486sx , llvm::MachO::CPUTypeI386 , 0x84 }, + { ArchSpec::eCore_x86_32_i386 , llvm::MachO::CPUTypeI386 , CPU_ANY }, + { ArchSpec::eCore_x86_64_x86_64 , llvm::MachO::CPUTypeX86_64 , 3 }, + { ArchSpec::eCore_x86_64_x86_64 , llvm::MachO::CPUTypeX86_64 , CPU_ANY } +}; +static const ArchDefinition g_macho_arch_def = { + eArchTypeMachO, + sizeof(g_macho_arch_entries)/sizeof(g_macho_arch_entries[0]), + g_macho_arch_entries, + UINT32_MAX, // CPU type mask + 0x00FFFFFFu, // CPU subtype mask + "mach-o" +}; + +//===----------------------------------------------------------------------===// +// A table that gets searched linearly for matches. This table is used to +// convert cpu type and subtypes to architecture names, and to convert +// architecture names to cpu types and subtypes. The ordering is important and +// allows the precedence to be set when the table is built. +static const ArchDefinitionEntry g_elf_arch_entries[] = +{ + { ArchSpec::eCore_sparc_generic , llvm::ELF::EM_SPARC , LLDB_INVALID_CPUTYPE }, // Sparc + { ArchSpec::eCore_x86_32_i386 , llvm::ELF::EM_386 , LLDB_INVALID_CPUTYPE }, // Intel 80386 + { ArchSpec::eCore_x86_32_i486 , llvm::ELF::EM_486 , LLDB_INVALID_CPUTYPE }, // Intel 486 (deprecated) + { ArchSpec::eCore_ppc_generic , llvm::ELF::EM_PPC , LLDB_INVALID_CPUTYPE }, // PowerPC + { ArchSpec::eCore_ppc64_generic , llvm::ELF::EM_PPC64 , LLDB_INVALID_CPUTYPE }, // PowerPC64 + { ArchSpec::eCore_arm_generic , llvm::ELF::EM_ARM , LLDB_INVALID_CPUTYPE }, // ARM + { ArchSpec::eCore_alpha_generic , llvm::ELF::EM_ALPHA , LLDB_INVALID_CPUTYPE }, // DEC Alpha + { ArchSpec::eCore_sparc9_generic , llvm::ELF::EM_SPARCV9, LLDB_INVALID_CPUTYPE }, // SPARC V9 + { ArchSpec::eCore_x86_64_x86_64 , llvm::ELF::EM_X86_64 , LLDB_INVALID_CPUTYPE }, // AMD64 +}; + +static const ArchDefinition g_elf_arch_def = { + eArchTypeELF, + sizeof(g_elf_arch_entries)/sizeof(g_elf_arch_entries[0]), + g_elf_arch_entries, + UINT32_MAX, // CPU type mask + UINT32_MAX, // CPU subtype mask + "elf", +}; + +//===----------------------------------------------------------------------===// +// Table of all ArchDefinitions +static const ArchDefinition *g_arch_definitions[] = { + &g_macho_arch_def, + &g_elf_arch_def, +}; + +static const size_t k_num_arch_definitions = + sizeof(g_arch_definitions) / sizeof(g_arch_definitions[0]); + +//===----------------------------------------------------------------------===// +// Static helper functions. + + +// Get the architecture definition for a given object type. +static const ArchDefinition * +FindArchDefinition (ArchitectureType arch_type) +{ + for (unsigned int i = 0; i < k_num_arch_definitions; ++i) + { + const ArchDefinition *def = g_arch_definitions[i]; + if (def->type == arch_type) + return def; + } + return NULL; } -//---------------------------------------------------------------------- -// Assignment operator -//---------------------------------------------------------------------- -const ArchSpec& -ArchSpec::operator= (const ArchSpec& rhs) +// Get an architecture definition by name. +static const CoreDefinition * +FindCoreDefinition (llvm::StringRef name) { - if (this != &rhs) + for (unsigned int i = 0; i < ArchSpec::kNumCores; ++i) { - m_type = rhs.m_type; - m_cpu = rhs.m_cpu; - m_sub = rhs.m_sub; - m_triple = rhs.m_triple; - m_byte_order = rhs.m_byte_order; - m_addr_byte_size = rhs.m_addr_byte_size; + if (name.equals_lower(g_core_definitions[i].name)) + return &g_core_definitions[i]; } - return *this; + return NULL; } -//---------------------------------------------------------------------- -// Get a C string representation of the current architecture -//---------------------------------------------------------------------- -const char * -ArchSpec::AsCString() const +static inline const CoreDefinition * +FindCoreDefinition (ArchSpec::Core core) { - return ArchSpec::AsCString(m_type, m_cpu, m_sub); + if (core >= 0 && core < ArchSpec::kNumCores) + return &g_core_definitions[core]; + return NULL; } -//---------------------------------------------------------------------- -// Class function to get a C string representation given a CPU type -// and subtype. -//---------------------------------------------------------------------- -const char * -ArchSpec::AsCString (lldb::ArchitectureType arch_type, uint32_t cpu, uint32_t sub) +// Get a definition entry by cpu type and subtype. +static const ArchDefinitionEntry * +FindArchDefinitionEntry (const ArchDefinition *def, uint32_t cpu, uint32_t sub) { - if (arch_type >= kNumArchTypes) + if (def == NULL) return NULL; - switch (arch_type) - { - case kNumArchTypes: - case eArchTypeInvalid: - break; - - case eArchTypeMachO: - for (uint32_t i=0; icpu_mask; + const uint32_t sub_mask = def->sub_mask; + const ArchDefinitionEntry *entries = def->entries; + for (size_t i = 0; i < def->num_entries; ++i) + { + if ((entries[i].cpu == (cpu_mask & cpu)) && + (entries[i].sub == (sub_mask & sub))) + return &entries[i]; } - - const char *arch_type_cstr = g_arch_type_strings[arch_type]; - - static char s_cpu_hex_str[128]; - ::snprintf(s_cpu_hex_str, - sizeof(s_cpu_hex_str), - "%s%c%u%c%u", - arch_type_cstr, - ARCH_SPEC_SEPARATOR_CHAR, - cpu, - ARCH_SPEC_SEPARATOR_CHAR, - sub); - return s_cpu_hex_str; -} - -//---------------------------------------------------------------------- -// Clears the object contents back to a default invalid state. -//---------------------------------------------------------------------- -void -ArchSpec::Clear() -{ - m_type = eArchTypeInvalid; - m_cpu = LLDB_INVALID_CPUTYPE; - m_sub = 0; - m_triple = llvm::Triple(); - m_byte_order = lldb::endian::InlHostByteOrder(); - m_addr_byte_size = 0; + return NULL; } - - - -//---------------------------------------------------------------------- -// CPU subtype get accessor. -//---------------------------------------------------------------------- -uint32_t -ArchSpec::GetCPUSubtype() const +static const ArchDefinitionEntry * +FindArchDefinitionEntry (const ArchDefinition *def, ArchSpec::Core core) { - if (m_type == eArchTypeMachO) + if (def == NULL) + return NULL; + + const ArchDefinitionEntry *entries = def->entries; + for (size_t i = 0; i < def->num_entries; ++i) { - if (m_sub == CPU_ANY || m_sub == LLDB_INVALID_CPUTYPE) - return m_sub; - return m_sub & 0xffffff; + if (entries[i].core == core) + return &entries[i]; } - return 0; + return NULL; } +//===----------------------------------------------------------------------===// +// Constructors and destructors. -//---------------------------------------------------------------------- -// CPU type get accessor. -//---------------------------------------------------------------------- -uint32_t -ArchSpec::GetCPUType() const +ArchSpec::ArchSpec() : + m_triple (), + m_core (kCore_invalid), + m_byte_order (eByteOrderInvalid) { - return m_cpu; } -//---------------------------------------------------------------------- -// This function is designed to abstract us from having to know any -// details about the current m_type, m_cpu, and m_sub values and -// translate the result into a generic CPU type so LLDB core code can -// detect any CPUs that it supports. -//---------------------------------------------------------------------- -ArchSpec::CPU -ArchSpec::GetGenericCPUType () const +ArchSpec::ArchSpec (const char *triple_cstr) : + m_triple (), + m_core (kCore_invalid), + m_byte_order (eByteOrderInvalid) { - switch (m_type) - { - case kNumArchTypes: - case eArchTypeInvalid: - break; - - case eArchTypeMachO: - switch (m_cpu) - { - case llvm::MachO::CPUTypeARM: return eCPU_arm; - case llvm::MachO::CPUTypeI386: return eCPU_i386; - case llvm::MachO::CPUTypeX86_64: return eCPU_x86_64; - case llvm::MachO::CPUTypePowerPC: return eCPU_ppc; - case llvm::MachO::CPUTypePowerPC64: return eCPU_ppc64; - case llvm::MachO::CPUTypeSPARC: return eCPU_sparc; - } - break; - - case eArchTypeELF: - switch (m_cpu) - { - case llvm::ELF::EM_ARM: return eCPU_arm; - case llvm::ELF::EM_386: return eCPU_i386; - case llvm::ELF::EM_X86_64: return eCPU_x86_64; - case llvm::ELF::EM_PPC: return eCPU_ppc; - case 21: return eCPU_ppc64; - case llvm::ELF::EM_SPARC: return eCPU_sparc; - } - break; - } - - return eCPU_Unknown; + if (triple_cstr) + SetTriple(triple_cstr); } - - - -//---------------------------------------------------------------------- -// Feature flags get accessor. -//---------------------------------------------------------------------- -uint32_t -ArchSpec::GetFeatureFlags() const +ArchSpec::ArchSpec(const llvm::Triple &triple) : + m_triple (), + m_core (kCore_invalid), + m_byte_order (eByteOrderInvalid) { - if (m_type == eArchTypeMachO) - { - if (m_sub == CPU_ANY || m_sub == LLDB_INVALID_CPUTYPE) - return 0; - return m_sub & 0xff000000; - } - return 0; + SetTriple(triple); } - -static const char * g_i386_dwarf_reg_names[] = +ArchSpec::ArchSpec (lldb::ArchitectureType arch_type, uint32_t cpu, uint32_t subtype) : + m_triple (), + m_core (kCore_invalid), + m_byte_order (eByteOrderInvalid) { - "eax", - "ecx", - "edx", - "ebx", - "esp", - "ebp", - "esi", - "edi", - "eip", - "eflags" -}; + SetArchitecture (arch_type, cpu, subtype); +} -static const char * g_i386_gcc_reg_names[] = +ArchSpec::~ArchSpec() { - "eax", - "ecx", - "edx", - "ebx", - "ebp", - "esp", - "esi", - "edi", - "eip", - "eflags" -}; - -static const char * g_x86_64_dwarf_and_gcc_reg_names[] = { - "rax", - "rdx", - "rcx", - "rbx", - "rsi", - "rdi", - "rbp", - "rsp", - "r8", - "r9", - "r10", - "r11", - "r12", - "r13", - "r14", - "r15", - "rip" -}; +} -// Values take from: -// http://infocenter.arm.com/help/topic/com.arm.doc.ihi0040a/IHI0040A_aadwarf.pdf +//===----------------------------------------------------------------------===// +// Assignment and initialization. -enum +const ArchSpec& +ArchSpec::operator= (const ArchSpec& rhs) { - eRegNumARM_DWARF_r0 = 0, - eRegNumARM_DWARF_r1 = 1, - eRegNumARM_DWARF_r2 = 2, - eRegNumARM_DWARF_r3 = 3, - eRegNumARM_DWARF_r4 = 4, - eRegNumARM_DWARF_r5 = 5, - eRegNumARM_DWARF_r6 = 6, - eRegNumARM_DWARF_r7 = 7, - eRegNumARM_DWARF_r8 = 8, - eRegNumARM_DWARF_r9 = 9, - eRegNumARM_DWARF_r10 = 10, - eRegNumARM_DWARF_r11 = 11, - eRegNumARM_DWARF_r12 = 12, - eRegNumARM_DWARF_r13 = 13, // SP - eRegNumARM_DWARF_r14 = 14, // LR - eRegNumARM_DWARF_r15 = 15, // PC - - eRegNumARM_DWARF_f0_obsolete= 16, - eRegNumARM_DWARF_f1_obsolete, - eRegNumARM_DWARF_f2_obsolete, - eRegNumARM_DWARF_f3_obsolete, - eRegNumARM_DWARF_f4_obsolete, - eRegNumARM_DWARF_f5_obsolete, - eRegNumARM_DWARF_f6_obsolete, - eRegNumARM_DWARF_f7_obsolete, - - eRegNumARM_DWARF_s0_obsolete = 16, - eRegNumARM_DWARF_s1_obsolete, - eRegNumARM_DWARF_s2_obsolete, - eRegNumARM_DWARF_s3_obsolete, - eRegNumARM_DWARF_s4_obsolete, - eRegNumARM_DWARF_s5_obsolete, - eRegNumARM_DWARF_s6_obsolete, - eRegNumARM_DWARF_s7_obsolete, - eRegNumARM_DWARF_s8_obsolete, - eRegNumARM_DWARF_s9_obsolete, - eRegNumARM_DWARF_s10_obsolete, - eRegNumARM_DWARF_s11_obsolete, - eRegNumARM_DWARF_s12_obsolete, - eRegNumARM_DWARF_s13_obsolete, - eRegNumARM_DWARF_s14_obsolete, - eRegNumARM_DWARF_s15_obsolete, - eRegNumARM_DWARF_s16_obsolete, - eRegNumARM_DWARF_s17_obsolete, - eRegNumARM_DWARF_s18_obsolete, - eRegNumARM_DWARF_s19_obsolete, - eRegNumARM_DWARF_s20_obsolete, - eRegNumARM_DWARF_s21_obsolete, - eRegNumARM_DWARF_s22_obsolete, - eRegNumARM_DWARF_s23_obsolete, - eRegNumARM_DWARF_s24_obsolete, - eRegNumARM_DWARF_s25_obsolete, - eRegNumARM_DWARF_s26_obsolete, - eRegNumARM_DWARF_s27_obsolete, - eRegNumARM_DWARF_s28_obsolete, - eRegNumARM_DWARF_s29_obsolete, - eRegNumARM_DWARF_s30_obsolete, - eRegNumARM_DWARF_s31_obsolete, - - eRegNumARM_DWARF_s0 = 64, - eRegNumARM_DWARF_s1, - eRegNumARM_DWARF_s2, - eRegNumARM_DWARF_s3, - eRegNumARM_DWARF_s4, - eRegNumARM_DWARF_s5, - eRegNumARM_DWARF_s6, - eRegNumARM_DWARF_s7, - eRegNumARM_DWARF_s8, - eRegNumARM_DWARF_s9, - eRegNumARM_DWARF_s10, - eRegNumARM_DWARF_s11, - eRegNumARM_DWARF_s12, - eRegNumARM_DWARF_s13, - eRegNumARM_DWARF_s14, - eRegNumARM_DWARF_s15, - eRegNumARM_DWARF_s16, - eRegNumARM_DWARF_s17, - eRegNumARM_DWARF_s18, - eRegNumARM_DWARF_s19, - eRegNumARM_DWARF_s20, - eRegNumARM_DWARF_s21, - eRegNumARM_DWARF_s22, - eRegNumARM_DWARF_s23, - eRegNumARM_DWARF_s24, - eRegNumARM_DWARF_s25, - eRegNumARM_DWARF_s26, - eRegNumARM_DWARF_s27, - eRegNumARM_DWARF_s28, - eRegNumARM_DWARF_s29, - eRegNumARM_DWARF_s30, - eRegNumARM_DWARF_s31, - - eRegNumARM_DWARF_f0 = 96, - eRegNumARM_DWARF_f1, - eRegNumARM_DWARF_f2, - eRegNumARM_DWARF_f3, - eRegNumARM_DWARF_f4, - eRegNumARM_DWARF_f5, - eRegNumARM_DWARF_f6, - eRegNumARM_DWARF_f7, - - eRegNumARM_DWARF_ACC0 = 104, - eRegNumARM_DWARF_ACC1, - eRegNumARM_DWARF_ACC2, - eRegNumARM_DWARF_ACC3, - eRegNumARM_DWARF_ACC4, - eRegNumARM_DWARF_ACC5, - eRegNumARM_DWARF_ACC6, - eRegNumARM_DWARF_ACC7, - - eRegNumARM_DWARF_wCGR0 = 104, // These overlap with ACC0-ACC7 - eRegNumARM_DWARF_wCGR1, - eRegNumARM_DWARF_wCGR2, - eRegNumARM_DWARF_wCGR3, - eRegNumARM_DWARF_wCGR4, - eRegNumARM_DWARF_wCGR5, - eRegNumARM_DWARF_wCGR6, - eRegNumARM_DWARF_wCGR7, - - eRegNumARM_DWARF_wR0 = 112, - eRegNumARM_DWARF_wR1, - eRegNumARM_DWARF_wR2, - eRegNumARM_DWARF_wR3, - eRegNumARM_DWARF_wR4, - eRegNumARM_DWARF_wR5, - eRegNumARM_DWARF_wR6, - eRegNumARM_DWARF_wR7, - eRegNumARM_DWARF_wR8, - eRegNumARM_DWARF_wR9, - eRegNumARM_DWARF_wR10, - eRegNumARM_DWARF_wR11, - eRegNumARM_DWARF_wR12, - eRegNumARM_DWARF_wR13, - eRegNumARM_DWARF_wR14, - eRegNumARM_DWARF_wR15, - - eRegNumARM_DWARF_spsr = 128, - eRegNumARM_DWARF_spsr_fiq, - eRegNumARM_DWARF_spsr_irq, - eRegNumARM_DWARF_spsr_abt, - eRegNumARM_DWARF_spsr_und, - eRegNumARM_DWARF_spsr_svc, - - eRegNumARM_DWARF_r8_usr = 144, - eRegNumARM_DWARF_r9_usr, - eRegNumARM_DWARF_r10_usr, - eRegNumARM_DWARF_r11_usr, - eRegNumARM_DWARF_r12_usr, - eRegNumARM_DWARF_r13_usr, - eRegNumARM_DWARF_r14_usr, - - eRegNumARM_DWARF_r8_fiq = 151, - eRegNumARM_DWARF_r9_fiq, - eRegNumARM_DWARF_r10_fiq, - eRegNumARM_DWARF_r11_fiq, - eRegNumARM_DWARF_r12_fiq, - eRegNumARM_DWARF_r13_fiq, - eRegNumARM_DWARF_r14_fiq, - - eRegNumARM_DWARF_r13_irq, - eRegNumARM_DWARF_r14_irq, - - eRegNumARM_DWARF_r13_abt, - eRegNumARM_DWARF_r14_abt, - - eRegNumARM_DWARF_r13_und, - eRegNumARM_DWARF_r14_und, - - eRegNumARM_DWARF_r13_svc, - eRegNumARM_DWARF_r14_svc, - - eRegNumARM_DWARF_wC0 = 192, - eRegNumARM_DWARF_wC1, - eRegNumARM_DWARF_wC2, - eRegNumARM_DWARF_wC3, - eRegNumARM_DWARF_wC4, - eRegNumARM_DWARF_wC5, - eRegNumARM_DWARF_wC6, - eRegNumARM_DWARF_wC7, - - eRegNumARM_DWARF_d0 = 256, // VFP-v3/NEON D0-D31 (32 64 bit registers) - eRegNumARM_DWARF_d1, - eRegNumARM_DWARF_d2, - eRegNumARM_DWARF_d3, - eRegNumARM_DWARF_d4, - eRegNumARM_DWARF_d5, - eRegNumARM_DWARF_d6, - eRegNumARM_DWARF_d7, - eRegNumARM_DWARF_d8, - eRegNumARM_DWARF_d9, - eRegNumARM_DWARF_d10, - eRegNumARM_DWARF_d11, - eRegNumARM_DWARF_d12, - eRegNumARM_DWARF_d13, - eRegNumARM_DWARF_d14, - eRegNumARM_DWARF_d15, - eRegNumARM_DWARF_d16, - eRegNumARM_DWARF_d17, - eRegNumARM_DWARF_d18, - eRegNumARM_DWARF_d19, - eRegNumARM_DWARF_d20, - eRegNumARM_DWARF_d21, - eRegNumARM_DWARF_d22, - eRegNumARM_DWARF_d23, - eRegNumARM_DWARF_d24, - eRegNumARM_DWARF_d25, - eRegNumARM_DWARF_d26, - eRegNumARM_DWARF_d27, - eRegNumARM_DWARF_d28, - eRegNumARM_DWARF_d29, - eRegNumARM_DWARF_d30, - eRegNumARM_DWARF_d31 -}; + if (this != &rhs) + { + m_triple = rhs.m_triple; + m_core = rhs.m_core; + m_byte_order = rhs.m_byte_order; + } + return *this; +} -// Register numbering definitions for 32 and 64 bit ppc for RegisterNumberingType::Dwarf -enum +void +ArchSpec::Clear() { - eRegNumPPC_DWARF_r0 = 0, - eRegNumPPC_DWARF_r1 = 1, - eRegNumPPC_DWARF_r2 = 2, - eRegNumPPC_DWARF_r3 = 3, - eRegNumPPC_DWARF_r4 = 4, - eRegNumPPC_DWARF_r5 = 5, - eRegNumPPC_DWARF_r6 = 6, - eRegNumPPC_DWARF_r7 = 7, - eRegNumPPC_DWARF_r8 = 8, - eRegNumPPC_DWARF_r9 = 9, - eRegNumPPC_DWARF_r10 = 10, - eRegNumPPC_DWARF_r11 = 11, - eRegNumPPC_DWARF_r12 = 12, - eRegNumPPC_DWARF_r13 = 13, - eRegNumPPC_DWARF_r14 = 14, - eRegNumPPC_DWARF_r15 = 15, - eRegNumPPC_DWARF_r16 = 16, - eRegNumPPC_DWARF_r17 = 17, - eRegNumPPC_DWARF_r18 = 18, - eRegNumPPC_DWARF_r19 = 19, - eRegNumPPC_DWARF_r20 = 20, - eRegNumPPC_DWARF_r21 = 21, - eRegNumPPC_DWARF_r22 = 22, - eRegNumPPC_DWARF_r23 = 23, - eRegNumPPC_DWARF_r24 = 24, - eRegNumPPC_DWARF_r25 = 25, - eRegNumPPC_DWARF_r26 = 26, - eRegNumPPC_DWARF_r27 = 27, - eRegNumPPC_DWARF_r28 = 28, - eRegNumPPC_DWARF_r29 = 29, - eRegNumPPC_DWARF_r30 = 30, - eRegNumPPC_DWARF_r31 = 31, - - eRegNumPPC_DWARF_fr0 = 32, - eRegNumPPC_DWARF_fr1 = 33, - eRegNumPPC_DWARF_fr2 = 34, - eRegNumPPC_DWARF_fr3 = 35, - eRegNumPPC_DWARF_fr4 = 36, - eRegNumPPC_DWARF_fr5 = 37, - eRegNumPPC_DWARF_fr6 = 38, - eRegNumPPC_DWARF_fr7 = 39, - eRegNumPPC_DWARF_fr8 = 40, - eRegNumPPC_DWARF_fr9 = 41, - eRegNumPPC_DWARF_fr10 = 42, - eRegNumPPC_DWARF_fr11 = 43, - eRegNumPPC_DWARF_fr12 = 44, - eRegNumPPC_DWARF_fr13 = 45, - eRegNumPPC_DWARF_fr14 = 46, - eRegNumPPC_DWARF_fr15 = 47, - eRegNumPPC_DWARF_fr16 = 48, - eRegNumPPC_DWARF_fr17 = 49, - eRegNumPPC_DWARF_fr18 = 50, - eRegNumPPC_DWARF_fr19 = 51, - eRegNumPPC_DWARF_fr20 = 52, - eRegNumPPC_DWARF_fr21 = 53, - eRegNumPPC_DWARF_fr22 = 54, - eRegNumPPC_DWARF_fr23 = 55, - eRegNumPPC_DWARF_fr24 = 56, - eRegNumPPC_DWARF_fr25 = 57, - eRegNumPPC_DWARF_fr26 = 58, - eRegNumPPC_DWARF_fr27 = 59, - eRegNumPPC_DWARF_fr28 = 60, - eRegNumPPC_DWARF_fr29 = 61, - eRegNumPPC_DWARF_fr30 = 62, - eRegNumPPC_DWARF_fr31 = 63, - - eRegNumPPC_DWARF_cr = 64, - eRegNumPPC_DWARF_fpscr = 65, - eRegNumPPC_DWARF_msr = 66, - eRegNumPPC_DWARF_vscr = 67, - - eRegNumPPC_DWARF_sr0 = 70, - eRegNumPPC_DWARF_sr1, - eRegNumPPC_DWARF_sr2, - eRegNumPPC_DWARF_sr3, - eRegNumPPC_DWARF_sr4, - eRegNumPPC_DWARF_sr5, - eRegNumPPC_DWARF_sr6, - eRegNumPPC_DWARF_sr7, - eRegNumPPC_DWARF_sr8, - eRegNumPPC_DWARF_sr9, - eRegNumPPC_DWARF_sr10, - eRegNumPPC_DWARF_sr11, - eRegNumPPC_DWARF_sr12, - eRegNumPPC_DWARF_sr13, - eRegNumPPC_DWARF_sr14, - eRegNumPPC_DWARF_sr15, - - - eRegNumPPC_DWARF_acc = 99, - eRegNumPPC_DWARF_mq = 100, - eRegNumPPC_DWARF_xer = 101, - eRegNumPPC_DWARF_rtcu = 104, - eRegNumPPC_DWARF_rtcl = 105, - - eRegNumPPC_DWARF_lr = 108, - eRegNumPPC_DWARF_ctr = 109, - - eRegNumPPC_DWARF_dsisr = 118, - eRegNumPPC_DWARF_dar = 119, - eRegNumPPC_DWARF_dec = 122, - eRegNumPPC_DWARF_sdr1 = 125, - eRegNumPPC_DWARF_srr0 = 126, - eRegNumPPC_DWARF_srr1 = 127, - - eRegNumPPC_DWARF_vrsave = 356, - eRegNumPPC_DWARF_sprg0 = 372, - eRegNumPPC_DWARF_sprg1, - eRegNumPPC_DWARF_sprg2, - eRegNumPPC_DWARF_sprg3, - - eRegNumPPC_DWARF_asr = 380, - eRegNumPPC_DWARF_ear = 382, - eRegNumPPC_DWARF_tb = 384, - eRegNumPPC_DWARF_tbu = 385, - eRegNumPPC_DWARF_pvr = 387, - - eRegNumPPC_DWARF_spefscr = 612, - - eRegNumPPC_DWARF_ibat0u = 628, - eRegNumPPC_DWARF_ibat0l = 629, - eRegNumPPC_DWARF_ibat1u = 630, - eRegNumPPC_DWARF_ibat1l = 631, - eRegNumPPC_DWARF_ibat2u = 632, - eRegNumPPC_DWARF_ibat2l = 633, - eRegNumPPC_DWARF_ibat3u = 634, - eRegNumPPC_DWARF_ibat3l = 635, - eRegNumPPC_DWARF_dbat0u = 636, - eRegNumPPC_DWARF_dbat0l = 637, - eRegNumPPC_DWARF_dbat1u = 638, - eRegNumPPC_DWARF_dbat1l = 639, - eRegNumPPC_DWARF_dbat2u = 640, - eRegNumPPC_DWARF_dbat2l = 641, - eRegNumPPC_DWARF_dbat3u = 642, - eRegNumPPC_DWARF_dbat3l = 643, - - eRegNumPPC_DWARF_hid0 = 1108, - eRegNumPPC_DWARF_hid1, - eRegNumPPC_DWARF_hid2, - eRegNumPPC_DWARF_hid3, - eRegNumPPC_DWARF_hid4, - eRegNumPPC_DWARF_hid5, - eRegNumPPC_DWARF_hid6, - eRegNumPPC_DWARF_hid7, - eRegNumPPC_DWARF_hid8, - eRegNumPPC_DWARF_hid9, - eRegNumPPC_DWARF_hid10, - eRegNumPPC_DWARF_hid11, - eRegNumPPC_DWARF_hid12, - eRegNumPPC_DWARF_hid13, - eRegNumPPC_DWARF_hid14, - eRegNumPPC_DWARF_hid15, - - eRegNumPPC_DWARF_vr0 = 1124, - eRegNumPPC_DWARF_vr1, - eRegNumPPC_DWARF_vr2, - eRegNumPPC_DWARF_vr3, - eRegNumPPC_DWARF_vr4, - eRegNumPPC_DWARF_vr5, - eRegNumPPC_DWARF_vr6, - eRegNumPPC_DWARF_vr7, - eRegNumPPC_DWARF_vr8, - eRegNumPPC_DWARF_vr9, - eRegNumPPC_DWARF_vr10, - eRegNumPPC_DWARF_vr11, - eRegNumPPC_DWARF_vr12, - eRegNumPPC_DWARF_vr13, - eRegNumPPC_DWARF_vr14, - eRegNumPPC_DWARF_vr15, - eRegNumPPC_DWARF_vr16, - eRegNumPPC_DWARF_vr17, - eRegNumPPC_DWARF_vr18, - eRegNumPPC_DWARF_vr19, - eRegNumPPC_DWARF_vr20, - eRegNumPPC_DWARF_vr21, - eRegNumPPC_DWARF_vr22, - eRegNumPPC_DWARF_vr23, - eRegNumPPC_DWARF_vr24, - eRegNumPPC_DWARF_vr25, - eRegNumPPC_DWARF_vr26, - eRegNumPPC_DWARF_vr27, - eRegNumPPC_DWARF_vr28, - eRegNumPPC_DWARF_vr29, - eRegNumPPC_DWARF_vr30, - eRegNumPPC_DWARF_vr31, - - eRegNumPPC_DWARF_ev0 = 1200, - eRegNumPPC_DWARF_ev1, - eRegNumPPC_DWARF_ev2, - eRegNumPPC_DWARF_ev3, - eRegNumPPC_DWARF_ev4, - eRegNumPPC_DWARF_ev5, - eRegNumPPC_DWARF_ev6, - eRegNumPPC_DWARF_ev7, - eRegNumPPC_DWARF_ev8, - eRegNumPPC_DWARF_ev9, - eRegNumPPC_DWARF_ev10, - eRegNumPPC_DWARF_ev11, - eRegNumPPC_DWARF_ev12, - eRegNumPPC_DWARF_ev13, - eRegNumPPC_DWARF_ev14, - eRegNumPPC_DWARF_ev15, - eRegNumPPC_DWARF_ev16, - eRegNumPPC_DWARF_ev17, - eRegNumPPC_DWARF_ev18, - eRegNumPPC_DWARF_ev19, - eRegNumPPC_DWARF_ev20, - eRegNumPPC_DWARF_ev21, - eRegNumPPC_DWARF_ev22, - eRegNumPPC_DWARF_ev23, - eRegNumPPC_DWARF_ev24, - eRegNumPPC_DWARF_ev25, - eRegNumPPC_DWARF_ev26, - eRegNumPPC_DWARF_ev27, - eRegNumPPC_DWARF_ev28, - eRegNumPPC_DWARF_ev29, - eRegNumPPC_DWARF_ev30, - eRegNumPPC_DWARF_ev31 -}; + m_triple = llvm::Triple(); + m_core = kCore_invalid; + m_byte_order = eByteOrderInvalid; +} -// Register numbering definitions for 32 and 64 bit ppc for RegisterNumberingType::GCC -enum -{ - eRegNumPPC_GCC_r0 = 0, - eRegNumPPC_GCC_r1 = 1, - eRegNumPPC_GCC_r2 = 2, - eRegNumPPC_GCC_r3 = 3, - eRegNumPPC_GCC_r4 = 4, - eRegNumPPC_GCC_r5 = 5, - eRegNumPPC_GCC_r6 = 6, - eRegNumPPC_GCC_r7 = 7, - eRegNumPPC_GCC_r8 = 8, - eRegNumPPC_GCC_r9 = 9, - eRegNumPPC_GCC_r10 = 10, - eRegNumPPC_GCC_r11 = 11, - eRegNumPPC_GCC_r12 = 12, - eRegNumPPC_GCC_r13 = 13, - eRegNumPPC_GCC_r14 = 14, - eRegNumPPC_GCC_r15 = 15, - eRegNumPPC_GCC_r16 = 16, - eRegNumPPC_GCC_r17 = 17, - eRegNumPPC_GCC_r18 = 18, - eRegNumPPC_GCC_r19 = 19, - eRegNumPPC_GCC_r20 = 20, - eRegNumPPC_GCC_r21 = 21, - eRegNumPPC_GCC_r22 = 22, - eRegNumPPC_GCC_r23 = 23, - eRegNumPPC_GCC_r24 = 24, - eRegNumPPC_GCC_r25 = 25, - eRegNumPPC_GCC_r26 = 26, - eRegNumPPC_GCC_r27 = 27, - eRegNumPPC_GCC_r28 = 28, - eRegNumPPC_GCC_r29 = 29, - eRegNumPPC_GCC_r30 = 30, - eRegNumPPC_GCC_r31 = 31, - eRegNumPPC_GCC_fr0 = 32, - eRegNumPPC_GCC_fr1 = 33, - eRegNumPPC_GCC_fr2 = 34, - eRegNumPPC_GCC_fr3 = 35, - eRegNumPPC_GCC_fr4 = 36, - eRegNumPPC_GCC_fr5 = 37, - eRegNumPPC_GCC_fr6 = 38, - eRegNumPPC_GCC_fr7 = 39, - eRegNumPPC_GCC_fr8 = 40, - eRegNumPPC_GCC_fr9 = 41, - eRegNumPPC_GCC_fr10 = 42, - eRegNumPPC_GCC_fr11 = 43, - eRegNumPPC_GCC_fr12 = 44, - eRegNumPPC_GCC_fr13 = 45, - eRegNumPPC_GCC_fr14 = 46, - eRegNumPPC_GCC_fr15 = 47, - eRegNumPPC_GCC_fr16 = 48, - eRegNumPPC_GCC_fr17 = 49, - eRegNumPPC_GCC_fr18 = 50, - eRegNumPPC_GCC_fr19 = 51, - eRegNumPPC_GCC_fr20 = 52, - eRegNumPPC_GCC_fr21 = 53, - eRegNumPPC_GCC_fr22 = 54, - eRegNumPPC_GCC_fr23 = 55, - eRegNumPPC_GCC_fr24 = 56, - eRegNumPPC_GCC_fr25 = 57, - eRegNumPPC_GCC_fr26 = 58, - eRegNumPPC_GCC_fr27 = 59, - eRegNumPPC_GCC_fr28 = 60, - eRegNumPPC_GCC_fr29 = 61, - eRegNumPPC_GCC_fr30 = 62, - eRegNumPPC_GCC_fr31 = 63, - eRegNumPPC_GCC_mq = 64, - eRegNumPPC_GCC_lr = 65, - eRegNumPPC_GCC_ctr = 66, - eRegNumPPC_GCC_ap = 67, - eRegNumPPC_GCC_cr0 = 68, - eRegNumPPC_GCC_cr1 = 69, - eRegNumPPC_GCC_cr2 = 70, - eRegNumPPC_GCC_cr3 = 71, - eRegNumPPC_GCC_cr4 = 72, - eRegNumPPC_GCC_cr5 = 73, - eRegNumPPC_GCC_cr6 = 74, - eRegNumPPC_GCC_cr7 = 75, - eRegNumPPC_GCC_xer = 76, - eRegNumPPC_GCC_v0 = 77, - eRegNumPPC_GCC_v1 = 78, - eRegNumPPC_GCC_v2 = 79, - eRegNumPPC_GCC_v3 = 80, - eRegNumPPC_GCC_v4 = 81, - eRegNumPPC_GCC_v5 = 82, - eRegNumPPC_GCC_v6 = 83, - eRegNumPPC_GCC_v7 = 84, - eRegNumPPC_GCC_v8 = 85, - eRegNumPPC_GCC_v9 = 86, - eRegNumPPC_GCC_v10 = 87, - eRegNumPPC_GCC_v11 = 88, - eRegNumPPC_GCC_v12 = 89, - eRegNumPPC_GCC_v13 = 90, - eRegNumPPC_GCC_v14 = 91, - eRegNumPPC_GCC_v15 = 92, - eRegNumPPC_GCC_v16 = 93, - eRegNumPPC_GCC_v17 = 94, - eRegNumPPC_GCC_v18 = 95, - eRegNumPPC_GCC_v19 = 96, - eRegNumPPC_GCC_v20 = 97, - eRegNumPPC_GCC_v21 = 98, - eRegNumPPC_GCC_v22 = 99, - eRegNumPPC_GCC_v23 = 100, - eRegNumPPC_GCC_v24 = 101, - eRegNumPPC_GCC_v25 = 102, - eRegNumPPC_GCC_v26 = 103, - eRegNumPPC_GCC_v27 = 104, - eRegNumPPC_GCC_v28 = 105, - eRegNumPPC_GCC_v29 = 106, - eRegNumPPC_GCC_v30 = 107, - eRegNumPPC_GCC_v31 = 108, - eRegNumPPC_GCC_vrsave = 109, - eRegNumPPC_GCC_vscr = 110, - eRegNumPPC_GCC_spe_acc = 111, - eRegNumPPC_GCC_spefscr = 112, - eRegNumPPC_GCC_sfp = 113 -}; +//===----------------------------------------------------------------------===// +// Predicates. -static const char * g_arm_gcc_reg_names[] = { - "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", - "r8", "r9", "r10", "r11", "r12", "sp", "lr", "pc", - "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", - "cc", "sfp", "afp", - "mv0", "mv1", "mv2", "mv3", "mv4", "mv5", "mv6", "mv7", - "mv8", "mv9", "mv10", "mv11", "mv12", "mv13", "mv14", "mv15", - "wcgr0","wcgr1","wcgr2","wcgr3", - "wr0", "wr1", "wr2", "wr3", "wr4", "wr5", "wr6", "wr7", - "wr8", "wr9", "wr10", "wr11", "wr12", "wr13", "wr14", "wr15", - "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", - "s8", "s9", "s10", "s11", "s12", "s13", "s14", "s15", - "s16", "s17", "s18", "s19", "s20", "s21", "s22", "s23", - "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31", - "vfpcc" -}; -//---------------------------------------------------------------------- -// Get register names for the current object architecture given -// a register number, and a reg_kind for that register number. -//---------------------------------------------------------------------- const char * -ArchSpec::GetRegisterName(uint32_t reg_num, uint32_t reg_kind) const +ArchSpec::GetArchitectureName () const { - return ArchSpec::GetRegisterName(m_type, m_cpu, m_sub, reg_num, reg_kind); + const CoreDefinition *core_def = FindCoreDefinition (m_core); + if (core_def) + return core_def->name; + return "unknown"; } - -//---------------------------------------------------------------------- -// Get register names for the specified CPU type and subtype given -// a register number, and a reg_kind for that register number. -//---------------------------------------------------------------------- -const char * -ArchSpec::GetRegisterName (ArchitectureType arch_type, uint32_t cpu, uint32_t subtype, uint32_t reg_num, uint32_t reg_kind) +uint32_t +ArchSpec::GetMachOCPUType () const { - if ((arch_type == eArchTypeMachO && cpu == llvm::MachO::CPUTypeI386) || - (arch_type == eArchTypeELF && cpu == llvm::ELF::EM_386)) - { - switch (reg_kind) - { - case eRegisterKindGCC: - if (reg_num < sizeof(g_i386_gcc_reg_names)/sizeof(const char *)) - return g_i386_gcc_reg_names[reg_num]; - break; - case eRegisterKindDWARF: - if (reg_num < sizeof(g_i386_dwarf_reg_names)/sizeof(const char *)) - return g_i386_dwarf_reg_names[reg_num]; - break; - default: - break; - } - } - else if ((arch_type == eArchTypeMachO && cpu == llvm::MachO::CPUTypeX86_64) || - (arch_type == eArchTypeELF && cpu == llvm::ELF::EM_X86_64)) + const CoreDefinition *core_def = FindCoreDefinition (m_core); + if (core_def) { - switch (reg_kind) + const ArchDefinitionEntry *arch_def = FindArchDefinitionEntry (&g_macho_arch_def, core_def->core); + if (arch_def) { - case eRegisterKindGCC: - case eRegisterKindDWARF: - if (reg_num < sizeof(g_x86_64_dwarf_and_gcc_reg_names)/sizeof(const char *)) - return g_x86_64_dwarf_and_gcc_reg_names[reg_num]; - break; - default: - break; + return arch_def->cpu; } } - else if ((arch_type == eArchTypeMachO && cpu == llvm::MachO::CPUTypeARM) || - (arch_type == eArchTypeELF && cpu == llvm::ELF::EM_ARM)) - { - switch (reg_kind) - { - case eRegisterKindGCC: - if (reg_num < sizeof(g_arm_gcc_reg_names)/sizeof(const char *)) - return g_arm_gcc_reg_names[reg_num]; - break; + return LLDB_INVALID_CPUTYPE; +} - case eRegisterKindDWARF: - switch (reg_num) - { - case eRegNumARM_DWARF_r0: return "r0"; - case eRegNumARM_DWARF_r1: return "r1"; - case eRegNumARM_DWARF_r2: return "r2"; - case eRegNumARM_DWARF_r3: return "r3"; - case eRegNumARM_DWARF_r4: return "r4"; - case eRegNumARM_DWARF_r5: return "r5"; - case eRegNumARM_DWARF_r6: return "r6"; - case eRegNumARM_DWARF_r7: return "r7"; - case eRegNumARM_DWARF_r8: return "r8"; - case eRegNumARM_DWARF_r9: return "r9"; - case eRegNumARM_DWARF_r10: return "r10"; - case eRegNumARM_DWARF_r11: return "r11"; - case eRegNumARM_DWARF_r12: return "r12"; - case eRegNumARM_DWARF_r13: return "sp"; - case eRegNumARM_DWARF_r14: return "lr"; - case eRegNumARM_DWARF_r15: return "pc"; - case eRegNumARM_DWARF_s0_obsolete: case eRegNumARM_DWARF_s0: return "s0"; - case eRegNumARM_DWARF_s1_obsolete: case eRegNumARM_DWARF_s1: return "s1"; - case eRegNumARM_DWARF_s2_obsolete: case eRegNumARM_DWARF_s2: return "s2"; - case eRegNumARM_DWARF_s3_obsolete: case eRegNumARM_DWARF_s3: return "s3"; - case eRegNumARM_DWARF_s4_obsolete: case eRegNumARM_DWARF_s4: return "s4"; - case eRegNumARM_DWARF_s5_obsolete: case eRegNumARM_DWARF_s5: return "s5"; - case eRegNumARM_DWARF_s6_obsolete: case eRegNumARM_DWARF_s6: return "s6"; - case eRegNumARM_DWARF_s7_obsolete: case eRegNumARM_DWARF_s7: return "s7"; - case eRegNumARM_DWARF_s8_obsolete: case eRegNumARM_DWARF_s8: return "s8"; - case eRegNumARM_DWARF_s9_obsolete: case eRegNumARM_DWARF_s9: return "s9"; - case eRegNumARM_DWARF_s10_obsolete: case eRegNumARM_DWARF_s10: return "s10"; - case eRegNumARM_DWARF_s11_obsolete: case eRegNumARM_DWARF_s11: return "s11"; - case eRegNumARM_DWARF_s12_obsolete: case eRegNumARM_DWARF_s12: return "s12"; - case eRegNumARM_DWARF_s13_obsolete: case eRegNumARM_DWARF_s13: return "s13"; - case eRegNumARM_DWARF_s14_obsolete: case eRegNumARM_DWARF_s14: return "s14"; - case eRegNumARM_DWARF_s15_obsolete: case eRegNumARM_DWARF_s15: return "s15"; - case eRegNumARM_DWARF_s16_obsolete: case eRegNumARM_DWARF_s16: return "s16"; - case eRegNumARM_DWARF_s17_obsolete: case eRegNumARM_DWARF_s17: return "s17"; - case eRegNumARM_DWARF_s18_obsolete: case eRegNumARM_DWARF_s18: return "s18"; - case eRegNumARM_DWARF_s19_obsolete: case eRegNumARM_DWARF_s19: return "s19"; - case eRegNumARM_DWARF_s20_obsolete: case eRegNumARM_DWARF_s20: return "s20"; - case eRegNumARM_DWARF_s21_obsolete: case eRegNumARM_DWARF_s21: return "s21"; - case eRegNumARM_DWARF_s22_obsolete: case eRegNumARM_DWARF_s22: return "s22"; - case eRegNumARM_DWARF_s23_obsolete: case eRegNumARM_DWARF_s23: return "s23"; - case eRegNumARM_DWARF_s24_obsolete: case eRegNumARM_DWARF_s24: return "s24"; - case eRegNumARM_DWARF_s25_obsolete: case eRegNumARM_DWARF_s25: return "s25"; - case eRegNumARM_DWARF_s26_obsolete: case eRegNumARM_DWARF_s26: return "s26"; - case eRegNumARM_DWARF_s27_obsolete: case eRegNumARM_DWARF_s27: return "s27"; - case eRegNumARM_DWARF_s28_obsolete: case eRegNumARM_DWARF_s28: return "s28"; - case eRegNumARM_DWARF_s29_obsolete: case eRegNumARM_DWARF_s29: return "s29"; - case eRegNumARM_DWARF_s30_obsolete: case eRegNumARM_DWARF_s30: return "s30"; - case eRegNumARM_DWARF_s31_obsolete: case eRegNumARM_DWARF_s31: return "s31"; - case eRegNumARM_DWARF_f0: return "f0"; - case eRegNumARM_DWARF_f1: return "f1"; - case eRegNumARM_DWARF_f2: return "f2"; - case eRegNumARM_DWARF_f3: return "f3"; - case eRegNumARM_DWARF_f4: return "f4"; - case eRegNumARM_DWARF_f5: return "f5"; - case eRegNumARM_DWARF_f6: return "f6"; - case eRegNumARM_DWARF_f7: return "f7"; - case eRegNumARM_DWARF_wCGR0: return "wCGR0/ACC0"; - case eRegNumARM_DWARF_wCGR1: return "wCGR1/ACC1"; - case eRegNumARM_DWARF_wCGR2: return "wCGR2/ACC2"; - case eRegNumARM_DWARF_wCGR3: return "wCGR3/ACC3"; - case eRegNumARM_DWARF_wCGR4: return "wCGR4/ACC4"; - case eRegNumARM_DWARF_wCGR5: return "wCGR5/ACC5"; - case eRegNumARM_DWARF_wCGR6: return "wCGR6/ACC6"; - case eRegNumARM_DWARF_wCGR7: return "wCGR7/ACC7"; - case eRegNumARM_DWARF_wR0: return "wR0"; - case eRegNumARM_DWARF_wR1: return "wR1"; - case eRegNumARM_DWARF_wR2: return "wR2"; - case eRegNumARM_DWARF_wR3: return "wR3"; - case eRegNumARM_DWARF_wR4: return "wR4"; - case eRegNumARM_DWARF_wR5: return "wR5"; - case eRegNumARM_DWARF_wR6: return "wR6"; - case eRegNumARM_DWARF_wR7: return "wR7"; - case eRegNumARM_DWARF_wR8: return "wR8"; - case eRegNumARM_DWARF_wR9: return "wR9"; - case eRegNumARM_DWARF_wR10: return "wR10"; - case eRegNumARM_DWARF_wR11: return "wR11"; - case eRegNumARM_DWARF_wR12: return "wR12"; - case eRegNumARM_DWARF_wR13: return "wR13"; - case eRegNumARM_DWARF_wR14: return "wR14"; - case eRegNumARM_DWARF_wR15: return "wR15"; - case eRegNumARM_DWARF_spsr: return "spsr"; - case eRegNumARM_DWARF_spsr_fiq: return "spsr_fiq"; - case eRegNumARM_DWARF_spsr_irq: return "spsr_irq"; - case eRegNumARM_DWARF_spsr_abt: return "spsr_abt"; - case eRegNumARM_DWARF_spsr_und: return "spsr_und"; - case eRegNumARM_DWARF_spsr_svc: return "spsr_svc"; - case eRegNumARM_DWARF_r8_usr: return "r8_usr"; - case eRegNumARM_DWARF_r9_usr: return "r9_usr"; - case eRegNumARM_DWARF_r10_usr: return "r10_usr"; - case eRegNumARM_DWARF_r11_usr: return "r11_usr"; - case eRegNumARM_DWARF_r12_usr: return "r12_usr"; - case eRegNumARM_DWARF_r13_usr: return "sp_usr"; - case eRegNumARM_DWARF_r14_usr: return "lr_usr"; - case eRegNumARM_DWARF_r8_fiq: return "r8_fiq"; - case eRegNumARM_DWARF_r9_fiq: return "r9_fiq"; - case eRegNumARM_DWARF_r10_fiq: return "r10_fiq"; - case eRegNumARM_DWARF_r11_fiq: return "r11_fiq"; - case eRegNumARM_DWARF_r12_fiq: return "r12_fiq"; - case eRegNumARM_DWARF_r13_fiq: return "sp_fiq"; - case eRegNumARM_DWARF_r14_fiq: return "lr_fiq"; - case eRegNumARM_DWARF_r13_irq: return "sp_irq"; - case eRegNumARM_DWARF_r14_irq: return "lr_irq"; - case eRegNumARM_DWARF_r13_abt: return "sp_abt"; - case eRegNumARM_DWARF_r14_abt: return "lr_abt"; - case eRegNumARM_DWARF_r13_und: return "sp_und"; - case eRegNumARM_DWARF_r14_und: return "lr_und"; - case eRegNumARM_DWARF_r13_svc: return "sp_svc"; - case eRegNumARM_DWARF_r14_svc: return "lr_svc"; - case eRegNumARM_DWARF_wC0: return "wC0"; - case eRegNumARM_DWARF_wC1: return "wC1"; - case eRegNumARM_DWARF_wC2: return "wC2"; - case eRegNumARM_DWARF_wC3: return "wC3"; - case eRegNumARM_DWARF_wC4: return "wC4"; - case eRegNumARM_DWARF_wC5: return "wC5"; - case eRegNumARM_DWARF_wC6: return "wC6"; - case eRegNumARM_DWARF_wC7: return "wC7"; - case eRegNumARM_DWARF_d0: return "d0"; - case eRegNumARM_DWARF_d1: return "d1"; - case eRegNumARM_DWARF_d2: return "d2"; - case eRegNumARM_DWARF_d3: return "d3"; - case eRegNumARM_DWARF_d4: return "d4"; - case eRegNumARM_DWARF_d5: return "d5"; - case eRegNumARM_DWARF_d6: return "d6"; - case eRegNumARM_DWARF_d7: return "d7"; - case eRegNumARM_DWARF_d8: return "d8"; - case eRegNumARM_DWARF_d9: return "d9"; - case eRegNumARM_DWARF_d10: return "d10"; - case eRegNumARM_DWARF_d11: return "d11"; - case eRegNumARM_DWARF_d12: return "d12"; - case eRegNumARM_DWARF_d13: return "d13"; - case eRegNumARM_DWARF_d14: return "d14"; - case eRegNumARM_DWARF_d15: return "d15"; - case eRegNumARM_DWARF_d16: return "d16"; - case eRegNumARM_DWARF_d17: return "d17"; - case eRegNumARM_DWARF_d18: return "d18"; - case eRegNumARM_DWARF_d19: return "d19"; - case eRegNumARM_DWARF_d20: return "d20"; - case eRegNumARM_DWARF_d21: return "d21"; - case eRegNumARM_DWARF_d22: return "d22"; - case eRegNumARM_DWARF_d23: return "d23"; - case eRegNumARM_DWARF_d24: return "d24"; - case eRegNumARM_DWARF_d25: return "d25"; - case eRegNumARM_DWARF_d26: return "d26"; - case eRegNumARM_DWARF_d27: return "d27"; - case eRegNumARM_DWARF_d28: return "d28"; - case eRegNumARM_DWARF_d29: return "d29"; - case eRegNumARM_DWARF_d30: return "d30"; - case eRegNumARM_DWARF_d31: return "d31"; - } - break; - default: - break; - } - } - else if ((arch_type == eArchTypeMachO && (cpu == llvm::MachO::CPUTypePowerPC || cpu == llvm::MachO::CPUTypePowerPC64)) || - (arch_type == eArchTypeELF && cpu == llvm::ELF::EM_PPC)) +uint32_t +ArchSpec::GetMachOCPUSubType () const +{ + const CoreDefinition *core_def = FindCoreDefinition (m_core); + if (core_def) { - switch (reg_kind) + const ArchDefinitionEntry *arch_def = FindArchDefinitionEntry (&g_macho_arch_def, core_def->core); + if (arch_def) { - case eRegisterKindGCC: - switch (reg_num) - { - case eRegNumPPC_GCC_r0: return "r0"; - case eRegNumPPC_GCC_r1: return "r1"; - case eRegNumPPC_GCC_r2: return "r2"; - case eRegNumPPC_GCC_r3: return "r3"; - case eRegNumPPC_GCC_r4: return "r4"; - case eRegNumPPC_GCC_r5: return "r5"; - case eRegNumPPC_GCC_r6: return "r6"; - case eRegNumPPC_GCC_r7: return "r7"; - case eRegNumPPC_GCC_r8: return "r8"; - case eRegNumPPC_GCC_r9: return "r9"; - case eRegNumPPC_GCC_r10: return "r10"; - case eRegNumPPC_GCC_r11: return "r11"; - case eRegNumPPC_GCC_r12: return "r12"; - case eRegNumPPC_GCC_r13: return "r13"; - case eRegNumPPC_GCC_r14: return "r14"; - case eRegNumPPC_GCC_r15: return "r15"; - case eRegNumPPC_GCC_r16: return "r16"; - case eRegNumPPC_GCC_r17: return "r17"; - case eRegNumPPC_GCC_r18: return "r18"; - case eRegNumPPC_GCC_r19: return "r19"; - case eRegNumPPC_GCC_r20: return "r20"; - case eRegNumPPC_GCC_r21: return "r21"; - case eRegNumPPC_GCC_r22: return "r22"; - case eRegNumPPC_GCC_r23: return "r23"; - case eRegNumPPC_GCC_r24: return "r24"; - case eRegNumPPC_GCC_r25: return "r25"; - case eRegNumPPC_GCC_r26: return "r26"; - case eRegNumPPC_GCC_r27: return "r27"; - case eRegNumPPC_GCC_r28: return "r28"; - case eRegNumPPC_GCC_r29: return "r29"; - case eRegNumPPC_GCC_r30: return "r30"; - case eRegNumPPC_GCC_r31: return "r31"; - case eRegNumPPC_GCC_fr0: return "fr0"; - case eRegNumPPC_GCC_fr1: return "fr1"; - case eRegNumPPC_GCC_fr2: return "fr2"; - case eRegNumPPC_GCC_fr3: return "fr3"; - case eRegNumPPC_GCC_fr4: return "fr4"; - case eRegNumPPC_GCC_fr5: return "fr5"; - case eRegNumPPC_GCC_fr6: return "fr6"; - case eRegNumPPC_GCC_fr7: return "fr7"; - case eRegNumPPC_GCC_fr8: return "fr8"; - case eRegNumPPC_GCC_fr9: return "fr9"; - case eRegNumPPC_GCC_fr10: return "fr10"; - case eRegNumPPC_GCC_fr11: return "fr11"; - case eRegNumPPC_GCC_fr12: return "fr12"; - case eRegNumPPC_GCC_fr13: return "fr13"; - case eRegNumPPC_GCC_fr14: return "fr14"; - case eRegNumPPC_GCC_fr15: return "fr15"; - case eRegNumPPC_GCC_fr16: return "fr16"; - case eRegNumPPC_GCC_fr17: return "fr17"; - case eRegNumPPC_GCC_fr18: return "fr18"; - case eRegNumPPC_GCC_fr19: return "fr19"; - case eRegNumPPC_GCC_fr20: return "fr20"; - case eRegNumPPC_GCC_fr21: return "fr21"; - case eRegNumPPC_GCC_fr22: return "fr22"; - case eRegNumPPC_GCC_fr23: return "fr23"; - case eRegNumPPC_GCC_fr24: return "fr24"; - case eRegNumPPC_GCC_fr25: return "fr25"; - case eRegNumPPC_GCC_fr26: return "fr26"; - case eRegNumPPC_GCC_fr27: return "fr27"; - case eRegNumPPC_GCC_fr28: return "fr28"; - case eRegNumPPC_GCC_fr29: return "fr29"; - case eRegNumPPC_GCC_fr30: return "fr30"; - case eRegNumPPC_GCC_fr31: return "fr31"; - case eRegNumPPC_GCC_mq: return "mq"; - case eRegNumPPC_GCC_lr: return "lr"; - case eRegNumPPC_GCC_ctr: return "ctr"; - case eRegNumPPC_GCC_ap: return "ap"; - case eRegNumPPC_GCC_cr0: return "cr0"; - case eRegNumPPC_GCC_cr1: return "cr1"; - case eRegNumPPC_GCC_cr2: return "cr2"; - case eRegNumPPC_GCC_cr3: return "cr3"; - case eRegNumPPC_GCC_cr4: return "cr4"; - case eRegNumPPC_GCC_cr5: return "cr5"; - case eRegNumPPC_GCC_cr6: return "cr6"; - case eRegNumPPC_GCC_cr7: return "cr7"; - case eRegNumPPC_GCC_xer: return "xer"; - case eRegNumPPC_GCC_v0: return "v0"; - case eRegNumPPC_GCC_v1: return "v1"; - case eRegNumPPC_GCC_v2: return "v2"; - case eRegNumPPC_GCC_v3: return "v3"; - case eRegNumPPC_GCC_v4: return "v4"; - case eRegNumPPC_GCC_v5: return "v5"; - case eRegNumPPC_GCC_v6: return "v6"; - case eRegNumPPC_GCC_v7: return "v7"; - case eRegNumPPC_GCC_v8: return "v8"; - case eRegNumPPC_GCC_v9: return "v9"; - case eRegNumPPC_GCC_v10: return "v10"; - case eRegNumPPC_GCC_v11: return "v11"; - case eRegNumPPC_GCC_v12: return "v12"; - case eRegNumPPC_GCC_v13: return "v13"; - case eRegNumPPC_GCC_v14: return "v14"; - case eRegNumPPC_GCC_v15: return "v15"; - case eRegNumPPC_GCC_v16: return "v16"; - case eRegNumPPC_GCC_v17: return "v17"; - case eRegNumPPC_GCC_v18: return "v18"; - case eRegNumPPC_GCC_v19: return "v19"; - case eRegNumPPC_GCC_v20: return "v20"; - case eRegNumPPC_GCC_v21: return "v21"; - case eRegNumPPC_GCC_v22: return "v22"; - case eRegNumPPC_GCC_v23: return "v23"; - case eRegNumPPC_GCC_v24: return "v24"; - case eRegNumPPC_GCC_v25: return "v25"; - case eRegNumPPC_GCC_v26: return "v26"; - case eRegNumPPC_GCC_v27: return "v27"; - case eRegNumPPC_GCC_v28: return "v28"; - case eRegNumPPC_GCC_v29: return "v29"; - case eRegNumPPC_GCC_v30: return "v30"; - case eRegNumPPC_GCC_v31: return "v31"; - case eRegNumPPC_GCC_vrsave: return "vrsave"; - case eRegNumPPC_GCC_vscr: return "vscr"; - case eRegNumPPC_GCC_spe_acc: return "spe_acc"; - case eRegNumPPC_GCC_spefscr: return "spefscr"; - case eRegNumPPC_GCC_sfp: return "sfp"; - default: - break; - } - break; - - case eRegisterKindDWARF: - switch (reg_num) - { - case eRegNumPPC_DWARF_r0: return "r0"; - case eRegNumPPC_DWARF_r1: return "r1"; - case eRegNumPPC_DWARF_r2: return "r2"; - case eRegNumPPC_DWARF_r3: return "r3"; - case eRegNumPPC_DWARF_r4: return "r4"; - case eRegNumPPC_DWARF_r5: return "r5"; - case eRegNumPPC_DWARF_r6: return "r6"; - case eRegNumPPC_DWARF_r7: return "r7"; - case eRegNumPPC_DWARF_r8: return "r8"; - case eRegNumPPC_DWARF_r9: return "r9"; - case eRegNumPPC_DWARF_r10: return "r10"; - case eRegNumPPC_DWARF_r11: return "r11"; - case eRegNumPPC_DWARF_r12: return "r12"; - case eRegNumPPC_DWARF_r13: return "r13"; - case eRegNumPPC_DWARF_r14: return "r14"; - case eRegNumPPC_DWARF_r15: return "r15"; - case eRegNumPPC_DWARF_r16: return "r16"; - case eRegNumPPC_DWARF_r17: return "r17"; - case eRegNumPPC_DWARF_r18: return "r18"; - case eRegNumPPC_DWARF_r19: return "r19"; - case eRegNumPPC_DWARF_r20: return "r20"; - case eRegNumPPC_DWARF_r21: return "r21"; - case eRegNumPPC_DWARF_r22: return "r22"; - case eRegNumPPC_DWARF_r23: return "r23"; - case eRegNumPPC_DWARF_r24: return "r24"; - case eRegNumPPC_DWARF_r25: return "r25"; - case eRegNumPPC_DWARF_r26: return "r26"; - case eRegNumPPC_DWARF_r27: return "r27"; - case eRegNumPPC_DWARF_r28: return "r28"; - case eRegNumPPC_DWARF_r29: return "r29"; - case eRegNumPPC_DWARF_r30: return "r30"; - case eRegNumPPC_DWARF_r31: return "r31"; - - case eRegNumPPC_DWARF_fr0: return "fr0"; - case eRegNumPPC_DWARF_fr1: return "fr1"; - case eRegNumPPC_DWARF_fr2: return "fr2"; - case eRegNumPPC_DWARF_fr3: return "fr3"; - case eRegNumPPC_DWARF_fr4: return "fr4"; - case eRegNumPPC_DWARF_fr5: return "fr5"; - case eRegNumPPC_DWARF_fr6: return "fr6"; - case eRegNumPPC_DWARF_fr7: return "fr7"; - case eRegNumPPC_DWARF_fr8: return "fr8"; - case eRegNumPPC_DWARF_fr9: return "fr9"; - case eRegNumPPC_DWARF_fr10: return "fr10"; - case eRegNumPPC_DWARF_fr11: return "fr11"; - case eRegNumPPC_DWARF_fr12: return "fr12"; - case eRegNumPPC_DWARF_fr13: return "fr13"; - case eRegNumPPC_DWARF_fr14: return "fr14"; - case eRegNumPPC_DWARF_fr15: return "fr15"; - case eRegNumPPC_DWARF_fr16: return "fr16"; - case eRegNumPPC_DWARF_fr17: return "fr17"; - case eRegNumPPC_DWARF_fr18: return "fr18"; - case eRegNumPPC_DWARF_fr19: return "fr19"; - case eRegNumPPC_DWARF_fr20: return "fr20"; - case eRegNumPPC_DWARF_fr21: return "fr21"; - case eRegNumPPC_DWARF_fr22: return "fr22"; - case eRegNumPPC_DWARF_fr23: return "fr23"; - case eRegNumPPC_DWARF_fr24: return "fr24"; - case eRegNumPPC_DWARF_fr25: return "fr25"; - case eRegNumPPC_DWARF_fr26: return "fr26"; - case eRegNumPPC_DWARF_fr27: return "fr27"; - case eRegNumPPC_DWARF_fr28: return "fr28"; - case eRegNumPPC_DWARF_fr29: return "fr29"; - case eRegNumPPC_DWARF_fr30: return "fr30"; - case eRegNumPPC_DWARF_fr31: return "fr31"; - - case eRegNumPPC_DWARF_cr: return "cr"; - case eRegNumPPC_DWARF_fpscr: return "fpscr"; - case eRegNumPPC_DWARF_msr: return "msr"; - case eRegNumPPC_DWARF_vscr: return "vscr"; - - case eRegNumPPC_DWARF_sr0: return "sr0"; - case eRegNumPPC_DWARF_sr1: return "sr1"; - case eRegNumPPC_DWARF_sr2: return "sr2"; - case eRegNumPPC_DWARF_sr3: return "sr3"; - case eRegNumPPC_DWARF_sr4: return "sr4"; - case eRegNumPPC_DWARF_sr5: return "sr5"; - case eRegNumPPC_DWARF_sr6: return "sr6"; - case eRegNumPPC_DWARF_sr7: return "sr7"; - case eRegNumPPC_DWARF_sr8: return "sr8"; - case eRegNumPPC_DWARF_sr9: return "sr9"; - case eRegNumPPC_DWARF_sr10: return "sr10"; - case eRegNumPPC_DWARF_sr11: return "sr11"; - case eRegNumPPC_DWARF_sr12: return "sr12"; - case eRegNumPPC_DWARF_sr13: return "sr13"; - case eRegNumPPC_DWARF_sr14: return "sr14"; - case eRegNumPPC_DWARF_sr15: return "sr15"; - - case eRegNumPPC_DWARF_acc: return "acc"; - case eRegNumPPC_DWARF_mq: return "mq"; - case eRegNumPPC_DWARF_xer: return "xer"; - case eRegNumPPC_DWARF_rtcu: return "rtcu"; - case eRegNumPPC_DWARF_rtcl: return "rtcl"; - - case eRegNumPPC_DWARF_lr: return "lr"; - case eRegNumPPC_DWARF_ctr: return "ctr"; - - case eRegNumPPC_DWARF_dsisr: return "dsisr"; - case eRegNumPPC_DWARF_dar: return "dar"; - case eRegNumPPC_DWARF_dec: return "dec"; - case eRegNumPPC_DWARF_sdr1: return "sdr1"; - case eRegNumPPC_DWARF_srr0: return "srr0"; - case eRegNumPPC_DWARF_srr1: return "srr1"; - - case eRegNumPPC_DWARF_vrsave: return "vrsave"; - - case eRegNumPPC_DWARF_sprg0: return "sprg0"; - case eRegNumPPC_DWARF_sprg1: return "sprg1"; - case eRegNumPPC_DWARF_sprg2: return "sprg2"; - case eRegNumPPC_DWARF_sprg3: return "sprg3"; - - case eRegNumPPC_DWARF_asr: return "asr"; - case eRegNumPPC_DWARF_ear: return "ear"; - case eRegNumPPC_DWARF_tb: return "tb"; - case eRegNumPPC_DWARF_tbu: return "tbu"; - case eRegNumPPC_DWARF_pvr: return "pvr"; - - case eRegNumPPC_DWARF_spefscr: return "spefscr"; - - case eRegNumPPC_DWARF_ibat0u: return "ibat0u"; - case eRegNumPPC_DWARF_ibat0l: return "ibat0l"; - case eRegNumPPC_DWARF_ibat1u: return "ibat1u"; - case eRegNumPPC_DWARF_ibat1l: return "ibat1l"; - case eRegNumPPC_DWARF_ibat2u: return "ibat2u"; - case eRegNumPPC_DWARF_ibat2l: return "ibat2l"; - case eRegNumPPC_DWARF_ibat3u: return "ibat3u"; - case eRegNumPPC_DWARF_ibat3l: return "ibat3l"; - case eRegNumPPC_DWARF_dbat0u: return "dbat0u"; - case eRegNumPPC_DWARF_dbat0l: return "dbat0l"; - case eRegNumPPC_DWARF_dbat1u: return "dbat1u"; - case eRegNumPPC_DWARF_dbat1l: return "dbat1l"; - case eRegNumPPC_DWARF_dbat2u: return "dbat2u"; - case eRegNumPPC_DWARF_dbat2l: return "dbat2l"; - case eRegNumPPC_DWARF_dbat3u: return "dbat3u"; - case eRegNumPPC_DWARF_dbat3l: return "dbat3l"; - - case eRegNumPPC_DWARF_hid0: return "hid0"; - case eRegNumPPC_DWARF_hid1: return "hid1"; - case eRegNumPPC_DWARF_hid2: return "hid2"; - case eRegNumPPC_DWARF_hid3: return "hid3"; - case eRegNumPPC_DWARF_hid4: return "hid4"; - case eRegNumPPC_DWARF_hid5: return "hid5"; - case eRegNumPPC_DWARF_hid6: return "hid6"; - case eRegNumPPC_DWARF_hid7: return "hid7"; - case eRegNumPPC_DWARF_hid8: return "hid8"; - case eRegNumPPC_DWARF_hid9: return "hid9"; - case eRegNumPPC_DWARF_hid10: return "hid10"; - case eRegNumPPC_DWARF_hid11: return "hid11"; - case eRegNumPPC_DWARF_hid12: return "hid12"; - case eRegNumPPC_DWARF_hid13: return "hid13"; - case eRegNumPPC_DWARF_hid14: return "hid14"; - case eRegNumPPC_DWARF_hid15: return "hid15"; - - case eRegNumPPC_DWARF_vr0: return "vr0"; - case eRegNumPPC_DWARF_vr1: return "vr1"; - case eRegNumPPC_DWARF_vr2: return "vr2"; - case eRegNumPPC_DWARF_vr3: return "vr3"; - case eRegNumPPC_DWARF_vr4: return "vr4"; - case eRegNumPPC_DWARF_vr5: return "vr5"; - case eRegNumPPC_DWARF_vr6: return "vr6"; - case eRegNumPPC_DWARF_vr7: return "vr7"; - case eRegNumPPC_DWARF_vr8: return "vr8"; - case eRegNumPPC_DWARF_vr9: return "vr9"; - case eRegNumPPC_DWARF_vr10: return "vr10"; - case eRegNumPPC_DWARF_vr11: return "vr11"; - case eRegNumPPC_DWARF_vr12: return "vr12"; - case eRegNumPPC_DWARF_vr13: return "vr13"; - case eRegNumPPC_DWARF_vr14: return "vr14"; - case eRegNumPPC_DWARF_vr15: return "vr15"; - case eRegNumPPC_DWARF_vr16: return "vr16"; - case eRegNumPPC_DWARF_vr17: return "vr17"; - case eRegNumPPC_DWARF_vr18: return "vr18"; - case eRegNumPPC_DWARF_vr19: return "vr19"; - case eRegNumPPC_DWARF_vr20: return "vr20"; - case eRegNumPPC_DWARF_vr21: return "vr21"; - case eRegNumPPC_DWARF_vr22: return "vr22"; - case eRegNumPPC_DWARF_vr23: return "vr23"; - case eRegNumPPC_DWARF_vr24: return "vr24"; - case eRegNumPPC_DWARF_vr25: return "vr25"; - case eRegNumPPC_DWARF_vr26: return "vr26"; - case eRegNumPPC_DWARF_vr27: return "vr27"; - case eRegNumPPC_DWARF_vr28: return "vr28"; - case eRegNumPPC_DWARF_vr29: return "vr29"; - case eRegNumPPC_DWARF_vr30: return "vr30"; - case eRegNumPPC_DWARF_vr31: return "vr31"; - - case eRegNumPPC_DWARF_ev0: return "ev0"; - case eRegNumPPC_DWARF_ev1: return "ev1"; - case eRegNumPPC_DWARF_ev2: return "ev2"; - case eRegNumPPC_DWARF_ev3: return "ev3"; - case eRegNumPPC_DWARF_ev4: return "ev4"; - case eRegNumPPC_DWARF_ev5: return "ev5"; - case eRegNumPPC_DWARF_ev6: return "ev6"; - case eRegNumPPC_DWARF_ev7: return "ev7"; - case eRegNumPPC_DWARF_ev8: return "ev8"; - case eRegNumPPC_DWARF_ev9: return "ev9"; - case eRegNumPPC_DWARF_ev10: return "ev10"; - case eRegNumPPC_DWARF_ev11: return "ev11"; - case eRegNumPPC_DWARF_ev12: return "ev12"; - case eRegNumPPC_DWARF_ev13: return "ev13"; - case eRegNumPPC_DWARF_ev14: return "ev14"; - case eRegNumPPC_DWARF_ev15: return "ev15"; - case eRegNumPPC_DWARF_ev16: return "ev16"; - case eRegNumPPC_DWARF_ev17: return "ev17"; - case eRegNumPPC_DWARF_ev18: return "ev18"; - case eRegNumPPC_DWARF_ev19: return "ev19"; - case eRegNumPPC_DWARF_ev20: return "ev20"; - case eRegNumPPC_DWARF_ev21: return "ev21"; - case eRegNumPPC_DWARF_ev22: return "ev22"; - case eRegNumPPC_DWARF_ev23: return "ev23"; - case eRegNumPPC_DWARF_ev24: return "ev24"; - case eRegNumPPC_DWARF_ev25: return "ev25"; - case eRegNumPPC_DWARF_ev26: return "ev26"; - case eRegNumPPC_DWARF_ev27: return "ev27"; - case eRegNumPPC_DWARF_ev28: return "ev28"; - case eRegNumPPC_DWARF_ev29: return "ev29"; - case eRegNumPPC_DWARF_ev30: return "ev30"; - case eRegNumPPC_DWARF_ev31: return "ev31"; - default: - break; - } - break; - default: - break; + return arch_def->cpu; } - } - return NULL; + return LLDB_INVALID_CPUTYPE; } -//---------------------------------------------------------------------- -// Returns true if this object contains a valid architecture, false -// otherwise. -//---------------------------------------------------------------------- -bool -ArchSpec::IsValid() const +llvm::Triple::ArchType +ArchSpec::GetMachine () const { - return !(m_cpu == LLDB_INVALID_CPUTYPE); + const CoreDefinition *core_def = FindCoreDefinition (m_core); + if (core_def) + return core_def->machine; + + return llvm::Triple::UnknownArch; } -//---------------------------------------------------------------------- -// Returns true if this architecture is 64 bit, otherwise 32 bit is -// assumed and false is returned. -//---------------------------------------------------------------------- uint32_t ArchSpec::GetAddressByteSize() const { - if (m_addr_byte_size > 0) - return m_addr_byte_size; - - switch (m_type) - { - case kNumArchTypes: - case eArchTypeInvalid: - break; - - case eArchTypeMachO: - if (GetCPUType() & llvm::MachO::CPUArchABI64) - return 8; - else - return 4; - break; - - case eArchTypeELF: - switch (m_cpu) - { - case llvm::ELF::EM_M32: - case llvm::ELF::EM_SPARC: - case llvm::ELF::EM_386: - case llvm::ELF::EM_68K: - case llvm::ELF::EM_88K: - case llvm::ELF::EM_486: - case llvm::ELF::EM_860: - case llvm::ELF::EM_MIPS: - case llvm::ELF::EM_PPC: - case llvm::ELF::EM_ARM: - case llvm::ELF::EM_ALPHA: - case llvm::ELF::EM_SPARCV9: - return 4; - case llvm::ELF::EM_X86_64: - return 8; - } - break; - } + const CoreDefinition *core_def = FindCoreDefinition (m_core); + if (core_def) + return core_def->addr_byte_size; return 0; } -//---------------------------------------------------------------------- -// Returns the number of bytes that this object takes when an -// instance exists in memory. -//---------------------------------------------------------------------- -size_t -ArchSpec::MemorySize() const +ByteOrder +ArchSpec::GetDefaultEndian () const { - return sizeof(ArchSpec); + const CoreDefinition *core_def = FindCoreDefinition (m_core); + if (core_def) + return core_def->default_byte_order; + return eByteOrderInvalid; } -bool -ArchSpec::SetArchFromTargetTriple (const char *target_triple) -{ - if (target_triple) - { - const char *hyphen = strchr(target_triple, '-'); - if (hyphen) - { - std::string arch_only (target_triple, hyphen); - return SetArch (arch_only.c_str()); - } - } - return SetArch (target_triple); -} -void -ArchSpec::SetMachOArch (uint32_t cpu, uint32_t sub) +lldb::ByteOrder +ArchSpec::GetByteOrder () const { - m_type = lldb::eArchTypeMachO; - m_cpu = cpu; - m_sub = sub; - MachOArchUpdated (); + if (m_byte_order == eByteOrderInvalid) + return GetDefaultEndian(); + return m_byte_order; } -void -ArchSpec::MachOArchUpdated (size_t idx) +//===----------------------------------------------------------------------===// +// Mutators. + +bool +ArchSpec::SetTriple (const llvm::Triple &triple) { - // m_type, m_cpu, and m_sub have been updated, fixup everything else - if (idx >= k_num_mach_arch_defs) - { - for (size_t i=0; icore; + m_byte_order = core_def->default_byte_order; + + // If the vendor, OS or environment aren't specified, default to the system? + const ArchSpec &host_arch_ref = Host::GetArchitecture (Host::eSystemDefaultArchitecture); + if (m_triple.getVendor() == llvm::Triple::UnknownVendor) + m_triple.setVendor(host_arch_ref.GetTriple().getVendor()); + if (m_triple.getOS() == llvm::Triple::UnknownOS) + m_triple.setOS(host_arch_ref.GetTriple().getOS()); + if (m_triple.getEnvironment() == llvm::Triple::UnknownEnvironment) + m_triple.setEnvironment(host_arch_ref.GetTriple().getEnvironment()); } else { - assert (!"Unknown mach-o architecture"); - m_byte_order = lldb::endian::InlHostByteOrder(); - // We weren't able to find our CPU type in out known list of mach architectures... - if (GetCPUType() & llvm::MachO::CPUArchABI64) - m_addr_byte_size = 8; - else - m_addr_byte_size = 4; - m_triple = llvm::Triple(); + Clear(); } -} -void -ArchSpec::ELFArchUpdated (size_t idx) -{ - if (idx >= k_num_elf_arch_defs) - { - for (size_t i=0; icore; +// CoreUpdated(true); +// } +// return IsValid(); +//} +// +bool +ArchSpec::SetArchitecture (lldb::ArchitectureType arch_type, uint32_t cpu, uint32_t sub) +{ + m_core = kCore_invalid; + bool update_triple = true; + const ArchDefinition *arch_def = FindArchDefinition(arch_type); + if (arch_def) + { + const ArchDefinitionEntry *arch_def_entry = FindArchDefinitionEntry (arch_def, cpu, sub); + if (arch_def_entry) + { + const CoreDefinition *core_def = FindCoreDefinition (arch_def_entry->core); + if (core_def) + { + m_core = core_def->core; + update_triple = false; + m_triple.setArch (core_def->machine); + if (arch_type == eArchTypeMachO) { - // We have a cputype.cpusubtype format - str = end + 1; - if (*str != '\0') - { - m_sub = strtoul(str, &end, 0); - if (*end == '\0') - { - MachOArchUpdated (); - // We consumed the entire string and got a cpu type and subtype - return true; - } - } + m_triple.setVendor (llvm::Triple::Apple); + m_triple.setOS (llvm::Triple::Darwin); } - - // If we reach this point we have a valid cpu type, but no cpu subtype. - // Search for the first matching cpu type and use the corresponding cpu - // subtype. This setting should typically be the _ALL variant and should - // appear first in the list for each cpu type in the g_mach_arch_defs - // structure. - for (i=0; iname, "unknown", "unknown"); + m_byte_order = core_def->default_byte_order; + } + else + { + if (update_triple) + m_triple = llvm::Triple(); + m_byte_order = eByteOrderInvalid; } - return eByteOrderInvalid; } -//---------------------------------------------------------------------- -// Equal operator -//---------------------------------------------------------------------- +//===----------------------------------------------------------------------===// +// Operators. + bool lldb_private::operator== (const ArchSpec& lhs, const ArchSpec& rhs) { - uint32_t lhs_cpu = lhs.GetCPUType(); - uint32_t rhs_cpu = rhs.GetCPUType(); + const ArchSpec::Core lhs_core = lhs.GetCore (); + const ArchSpec::Core rhs_core = rhs.GetCore (); + + if (lhs_core == rhs_core) + return true; - if (lhs_cpu == CPU_ANY || rhs_cpu == CPU_ANY) + if (lhs_core == ArchSpec::kCore_any || rhs_core == ArchSpec::kCore_any) return true; - else if (lhs_cpu == rhs_cpu) + if (lhs_core == ArchSpec::kCore_arm_any) + { + if ((rhs_core >= ArchSpec::kCore_arm_first && rhs_core <= ArchSpec::kCore_arm_last) || (rhs_core == ArchSpec::kCore_arm_any)) + return true; + } + else if (rhs_core == ArchSpec::kCore_arm_any) + { + if ((lhs_core >= ArchSpec::kCore_arm_first && lhs_core <= ArchSpec::kCore_arm_last) || (lhs_core == ArchSpec::kCore_arm_any)) + return true; + } + else if (lhs_core == ArchSpec::kCore_x86_32_any) + { + if ((rhs_core >= ArchSpec::kCore_x86_32_first && rhs_core <= ArchSpec::kCore_x86_32_last) || (rhs_core == ArchSpec::kCore_x86_32_any)) + return true; + } + else if (rhs_core == ArchSpec::kCore_x86_32_any) { - uint32_t lhs_subtype = lhs.GetCPUSubtype(); - uint32_t rhs_subtype = rhs.GetCPUSubtype(); - if (lhs_subtype == CPU_ANY || rhs_subtype == CPU_ANY) + if ((lhs_core >= ArchSpec::kCore_x86_32_first && lhs_core <= ArchSpec::kCore_x86_32_last) || (lhs_core == ArchSpec::kCore_x86_32_any)) + return true; + } + else if (lhs_core == ArchSpec::kCore_ppc_any) + { + if ((rhs_core >= ArchSpec::kCore_ppc_first && rhs_core <= ArchSpec::kCore_ppc_last) || (rhs_core == ArchSpec::kCore_ppc_any)) + return true; + } + else if (rhs_core == ArchSpec::kCore_ppc_any) + { + if ((lhs_core >= ArchSpec::kCore_ppc_first && lhs_core <= ArchSpec::kCore_ppc_last) || (lhs_core == ArchSpec::kCore_ppc_any)) + return true; + } + else if (lhs_core == ArchSpec::kCore_ppc64_any) + { + if ((rhs_core >= ArchSpec::kCore_ppc64_first && rhs_core <= ArchSpec::kCore_ppc64_last) || (rhs_core == ArchSpec::kCore_ppc64_any)) + return true; + } + else if (rhs_core == ArchSpec::kCore_ppc64_any) + { + if ((lhs_core >= ArchSpec::kCore_ppc64_first && lhs_core <= ArchSpec::kCore_ppc64_last) || (lhs_core == ArchSpec::kCore_ppc64_any)) return true; - return lhs_subtype == rhs_subtype; } return false; } - -//---------------------------------------------------------------------- -// Not Equal operator -//---------------------------------------------------------------------- bool lldb_private::operator!= (const ArchSpec& lhs, const ArchSpec& rhs) { return !(lhs == rhs); } -//---------------------------------------------------------------------- -// Less than operator -//---------------------------------------------------------------------- bool lldb_private::operator<(const ArchSpec& lhs, const ArchSpec& rhs) { - uint32_t lhs_cpu = lhs.GetCPUType(); - uint32_t rhs_cpu = rhs.GetCPUType(); - - if (lhs_cpu == rhs_cpu) - return lhs.GetCPUSubtype() < rhs.GetCPUSubtype(); - - return lhs_cpu < rhs_cpu; + const ArchSpec::Core lhs_core = lhs.GetCore (); + const ArchSpec::Core rhs_core = rhs.GetCore (); + return lhs_core < rhs_core; } - Modified: lldb/trunk/source/Core/Debugger.cpp URL: http://llvm.org/viewvc/llvm-project/lldb/trunk/source/Core/Debugger.cpp?rev=126278&r1=126277&r2=126278&view=diff ============================================================================== --- lldb/trunk/source/Core/Debugger.cpp (original) +++ lldb/trunk/source/Core/Debugger.cpp Tue Feb 22 18:35:02 2011 @@ -877,7 +877,7 @@ ArchSpec arch (target->GetArchitecture ()); if (arch.IsValid()) { - s.PutCString (arch.AsCString()); + s.PutCString (arch.GetArchitectureName()); var_success = true; } } Modified: lldb/trunk/source/Core/Disassembler.cpp URL: http://llvm.org/viewvc/llvm-project/lldb/trunk/source/Core/Disassembler.cpp?rev=126278&r1=126277&r2=126278&view=diff ============================================================================== --- lldb/trunk/source/Core/Disassembler.cpp (original) +++ lldb/trunk/source/Core/Disassembler.cpp Tue Feb 22 18:35:02 2011 @@ -38,7 +38,7 @@ { Timer scoped_timer (__PRETTY_FUNCTION__, "Disassembler::FindPlugin (arch = %s)", - arch.AsCString()); + arch.GetArchitectureName()); std::auto_ptr disassembler_ap; DisassemblerCreateInstance create_callback; Modified: lldb/trunk/source/Core/Log.cpp URL: http://llvm.org/viewvc/llvm-project/lldb/trunk/source/Core/Log.cpp?rev=126278&r1=126277&r2=126278&view=diff ============================================================================== --- lldb/trunk/source/Core/Log.cpp (original) +++ lldb/trunk/source/Core/Log.cpp Tue Feb 22 18:35:02 2011 @@ -87,13 +87,10 @@ { static uint32_t g_sequence_id = 0; StreamString header; - static Mutex g_LogThreadedMutex(Mutex::eMutexTypeRecursive); - - Mutex::Locker locker; - - // Lock the threaded logging mutex if we are doing thread safe logging - if (m_options.Test (LLDB_LOG_OPTION_THREADSAFE)) - locker.Reset(g_LogThreadedMutex.GetMutex()); + // Enabling the thread safe logging actually deadlocks right now. + // Need to fix this at some point. +// static Mutex g_LogThreadedMutex(Mutex::eMutexTypeRecursive); +// Mutex::Locker locker (g_LogThreadedMutex); // Add a sequence ID if requested if (m_options.Test (LLDB_LOG_OPTION_PREPEND_SEQUENCE)) Modified: lldb/trunk/source/Core/Module.cpp URL: http://llvm.org/viewvc/llvm-project/lldb/trunk/source/Core/Module.cpp?rev=126278&r1=126277&r2=126278&view=diff ============================================================================== --- lldb/trunk/source/Core/Module.cpp (original) +++ lldb/trunk/source/Core/Module.cpp Tue Feb 22 18:35:02 2011 @@ -42,7 +42,7 @@ if (log) log->Printf ("%p Module::Module((%s) '%s/%s%s%s%s')", this, - m_arch.AsCString(), + m_arch.GetArchitectureName(), m_file.GetDirectory().AsCString(""), m_file.GetFilename().AsCString(""), m_object_name.IsEmpty() ? "" : "(", @@ -56,7 +56,7 @@ if (log) log->Printf ("%p Module::~Module((%s) '%s/%s%s%s%s')", this, - m_arch.AsCString(), + m_arch.GetArchitectureName(), m_file.GetDirectory().AsCString(""), m_file.GetFilename().AsCString(""), m_object_name.IsEmpty() ? "" : "(", @@ -474,7 +474,7 @@ Mutex::Locker locker (m_mutex); if (m_arch.IsValid()) - s->Printf("(%s) ", m_arch.AsCString()); + s->Printf("(%s) ", m_arch.GetArchitectureName()); char path[PATH_MAX]; if (m_file.GetPath(path, sizeof(path))) @@ -648,17 +648,11 @@ bool Module::SetArchitecture (const ArchSpec &new_arch) { - if (m_arch == new_arch) - return true; - else if (!m_arch.IsValid()) + if (!m_arch.IsValid()) { m_arch = new_arch; return true; - } - else - { - return false; - } - + } + return m_arch == new_arch; } Modified: lldb/trunk/source/Core/ModuleList.cpp URL: http://llvm.org/viewvc/llvm-project/lldb/trunk/source/Core/ModuleList.cpp?rev=126278&r1=126277&r2=126278&view=diff ============================================================================== --- lldb/trunk/source/Core/ModuleList.cpp (original) +++ lldb/trunk/source/Core/ModuleList.cpp Tue Feb 22 18:35:02 2011 @@ -404,7 +404,7 @@ prefix_cstr ? prefix_cstr : "", (uint32_t)std::distance (begin, pos), uuid_cstr, - module->GetArchitecture().AsCString(), + module->GetArchitecture().GetArchitectureName(), module_file_spec.GetDirectory().GetCString(), module_file_spec.GetFilename().GetCString()); } @@ -521,7 +521,7 @@ const FileSpec &module_file_spec = module_ptr->GetFileSpec(); fprintf (stderr, "warning: module not in shared module list: %s (%s) \"%s/%s\"\n", uuid_cstr, - module_ptr->GetArchitecture().AsCString(), + module_ptr->GetArchitecture().GetArchitectureName(), module_file_spec.GetDirectory().GetCString(), module_file_spec.GetFilename().GetCString()); } @@ -650,9 +650,9 @@ if (arch.IsValid()) { if (uuid_cstr[0]) - error.SetErrorStringWithFormat("'%s' does not contain the %s architecture and UUID %s.\n", path, arch.AsCString(), uuid_cstr[0]); + error.SetErrorStringWithFormat("'%s' does not contain the %s architecture and UUID %s.\n", path, arch.GetArchitectureName(), uuid_cstr[0]); else - error.SetErrorStringWithFormat("'%s' does not contain the %s architecture.\n", path, arch.AsCString()); + error.SetErrorStringWithFormat("'%s' does not contain the %s architecture.\n", path, arch.GetArchitectureName()); } } else @@ -707,7 +707,7 @@ if (file_spec) { if (arch.IsValid()) - error.SetErrorStringWithFormat("Unable to open %s architecture in '%s'.\n", arch.AsCString(), path); + error.SetErrorStringWithFormat("Unable to open %s architecture in '%s'.\n", arch.GetArchitectureName(), path); else error.SetErrorStringWithFormat("Unable to open '%s'.\n", path); } @@ -721,7 +721,7 @@ if (uuid_cstr[0]) error.SetErrorStringWithFormat("Cannot locate a module for UUID '%s'.\n", uuid_cstr[0]); else - error.SetErrorStringWithFormat("Cannot locate a module.\n", path, arch.AsCString()); + error.SetErrorStringWithFormat("Cannot locate a module.\n", path, arch.GetArchitectureName()); } } } Modified: lldb/trunk/source/Expression/ClangExpressionParser.cpp URL: http://llvm.org/viewvc/llvm-project/lldb/trunk/source/Expression/ClangExpressionParser.cpp?rev=126278&r1=126277&r2=126278&view=diff ============================================================================== --- lldb/trunk/source/Expression/ClangExpressionParser.cpp (original) +++ lldb/trunk/source/Expression/ClangExpressionParser.cpp Tue Feb 22 18:35:02 2011 @@ -714,7 +714,7 @@ if (disassembler == NULL) { ret.SetErrorToGenericError(); - ret.SetErrorStringWithFormat("Unable to find disassembler plug-in for %s architecture.", arch.AsCString()); + ret.SetErrorStringWithFormat("Unable to find disassembler plug-in for %s architecture.", arch.GetArchitectureName()); return ret; } Modified: lldb/trunk/source/Host/common/Host.cpp URL: http://llvm.org/viewvc/llvm-project/lldb/trunk/source/Host/common/Host.cpp?rev=126278&r1=126277&r2=126278&view=diff ============================================================================== --- lldb/trunk/source/Host/common/Host.cpp (original) +++ lldb/trunk/source/Host/common/Host.cpp Tue Feb 22 18:35:02 2011 @@ -268,20 +268,20 @@ if (cputype & CPU_ARCH_ABI64) { // We have a 64 bit kernel on a 64 bit system - g_host_arch_32.SetMachOArch (~(CPU_ARCH_MASK) & cputype, cpusubtype); - g_host_arch_64.SetMachOArch (cputype, cpusubtype); + g_host_arch_32.SetArchitecture (lldb::eArchTypeMachO, ~(CPU_ARCH_MASK) & cputype, cpusubtype); + g_host_arch_64.SetArchitecture (lldb::eArchTypeMachO, cputype, cpusubtype); } else { // We have a 32 bit kernel on a 64 bit system - g_host_arch_32.SetMachOArch (cputype, cpusubtype); + g_host_arch_32.SetArchitecture (lldb::eArchTypeMachO, cputype, cpusubtype); cputype |= CPU_ARCH_ABI64; - g_host_arch_64.SetMachOArch (cputype, cpusubtype); + g_host_arch_64.SetArchitecture (lldb::eArchTypeMachO, cputype, cpusubtype); } } else { - g_host_arch_32.SetMachOArch (cputype, cpusubtype); + g_host_arch_32.SetArchitecture (lldb::eArchTypeMachO, cputype, cpusubtype); g_host_arch_64.Clear(); } } @@ -293,23 +293,23 @@ { #if defined (__x86_64__) - g_host_arch_64.SetArch ("x86_64"); + g_host_arch_64.SetTriple ("x86_64"); #elif defined (__i386__) - g_host_arch_32.SetArch ("i386"); + g_host_arch_32.SetTriple ("i386"); #elif defined (__arm__) - g_host_arch_32.SetArch ("arm"); + g_host_arch_32.SetTriple ("arm"); #elif defined (__ppc64__) - g_host_arch_64.SetArch ("ppc64"); + g_host_arch_64.SetTriple ("ppc64"); #elif defined (__powerpc__) || defined (__ppc__) - g_host_arch_32.SetArch ("ppc"); + g_host_arch_32.SetTriple ("ppc"); #else @@ -377,7 +377,7 @@ { StreamString triple; triple.Printf("%s-%s-%s", - GetArchitecture().AsCString(), + GetArchitecture().GetArchitectureName(), GetVendorString().AsCString(), GetOSString().AsCString()); @@ -1093,9 +1093,9 @@ if (error == 0) return return_spec; if (bsd_info.pbi_flags & PROC_FLAG_LP64) - return_spec.SetArch(LLDB_ARCH_DEFAULT_64BIT); + return_spec.SetTriple (LLDB_ARCH_DEFAULT_64BIT); else - return_spec.SetArch(LLDB_ARCH_DEFAULT_32BIT); + return_spec.SetTriple (LLDB_ARCH_DEFAULT_32BIT); #endif return return_spec; Modified: lldb/trunk/source/Host/macosx/Host.mm URL: http://llvm.org/viewvc/llvm-project/lldb/trunk/source/Host/macosx/Host.mm?rev=126278&r1=126277&r2=126278&view=diff ============================================================================== --- lldb/trunk/source/Host/macosx/Host.mm (original) +++ lldb/trunk/source/Host/macosx/Host.mm Tue Feb 22 18:35:02 2011 @@ -279,7 +279,7 @@ if (arch_spec && arch_spec->IsValid()) { - command_file.Printf("--arch=%s ", arch_spec->AsCString()); + command_file.Printf("--arch=%s ", arch_spec->GetArchitectureName()); } if (disable_aslr) @@ -441,12 +441,12 @@ darwin_debug_file_spec.GetPath(launcher_path, sizeof(launcher_path)); if (arch_spec) - command.Printf("arch -arch %s ", arch_spec->AsCString()); + command.Printf("arch -arch %s ", arch_spec->GetArchitectureName()); command.Printf("'%s' --unix-socket=%s", launcher_path, unix_socket_name.c_str()); if (arch_spec && arch_spec->IsValid()) - command.Printf(" --arch=%s", arch_spec->AsCString()); + command.Printf(" --arch=%s", arch_spec->GetArchitectureName()); if (working_dir) command.Printf(" --working-dir '%s'", working_dir); Modified: lldb/trunk/source/Host/macosx/Symbols.cpp URL: http://llvm.org/viewvc/llvm-project/lldb/trunk/source/Host/macosx/Symbols.cpp?rev=126278&r1=126277&r2=126278&view=diff ============================================================================== --- lldb/trunk/source/Host/macosx/Symbols.cpp (original) +++ lldb/trunk/source/Host/macosx/Symbols.cpp Tue Feb 22 18:35:02 2011 @@ -433,7 +433,7 @@ Timer scoped_timer (__PRETTY_FUNCTION__, "LocateExecutableObjectFile (file = %s, arch = %s, uuid = %p)", exec_fspec ? exec_fspec->GetFilename().AsCString ("") : "", - arch ? arch->AsCString() : "", + arch ? arch->GetArchitectureName() : "", uuid); FileSpec objfile_fspec; @@ -450,7 +450,7 @@ Timer scoped_timer (__PRETTY_FUNCTION__, "LocateExecutableSymbolFile (file = %s, arch = %s, uuid = %p)", exec_fspec ? exec_fspec->GetFilename().AsCString ("") : "", - arch ? arch->AsCString() : "", + arch ? arch->GetArchitectureName() : "", uuid); FileSpec symbol_fspec; Modified: lldb/trunk/source/Plugins/Disassembler/llvm/DisassemblerLLVM.cpp URL: http://llvm.org/viewvc/llvm-project/lldb/trunk/source/Plugins/Disassembler/llvm/DisassemblerLLVM.cpp?rev=126278&r1=126277&r2=126278&view=diff ============================================================================== --- lldb/trunk/source/Plugins/Disassembler/llvm/DisassemblerLLVM.cpp (original) +++ lldb/trunk/source/Plugins/Disassembler/llvm/DisassemblerLLVM.cpp Tue Feb 22 18:35:02 2011 @@ -345,16 +345,12 @@ static inline EDAssemblySyntax_t SyntaxForArchSpec (const ArchSpec &arch) { - switch (arch.GetGenericCPUType()) + switch (arch.GetMachine ()) { - case ArchSpec::eCPU_i386: - case ArchSpec::eCPU_x86_64: + case llvm::Triple::x86: + case llvm::Triple::x86_64: return kEDAssemblySyntaxX86ATT; - case ArchSpec::eCPU_arm: - case ArchSpec::eCPU_ppc: - case ArchSpec::eCPU_ppc64: - case ArchSpec::eCPU_sparc: default: break; } Modified: lldb/trunk/source/Plugins/Instruction/ARM/EmulateInstructionARM.cpp URL: http://llvm.org/viewvc/llvm-project/lldb/trunk/source/Plugins/Instruction/ARM/EmulateInstructionARM.cpp?rev=126278&r1=126277&r2=126278&view=diff ============================================================================== --- lldb/trunk/source/Plugins/Instruction/ARM/EmulateInstructionARM.cpp (original) +++ lldb/trunk/source/Plugins/Instruction/ARM/EmulateInstructionARM.cpp Tue Feb 22 18:35:02 2011 @@ -6814,7 +6814,7 @@ EmulateInstructionARM::SetArchitecture (const ArchSpec &arch) { m_arm_isa = 0; - const char *arch_cstr = arch.AsCString (); + const char *arch_cstr = arch.GetArchitectureName (); if (arch_cstr) { if (0 == ::strcasecmp(arch_cstr, "armv4t")) m_arm_isa = ARMv4T; Modified: lldb/trunk/source/Plugins/ObjectContainer/BSD-Archive/ObjectContainerBSDArchive.cpp URL: http://llvm.org/viewvc/llvm-project/lldb/trunk/source/Plugins/ObjectContainer/BSD-Archive/ObjectContainerBSDArchive.cpp?rev=126278&r1=126277&r2=126278&view=diff ============================================================================== --- lldb/trunk/source/Plugins/ObjectContainer/BSD-Archive/ObjectContainerBSDArchive.cpp (original) +++ lldb/trunk/source/Plugins/ObjectContainer/BSD-Archive/ObjectContainerBSDArchive.cpp Tue Feb 22 18:35:02 2011 @@ -360,7 +360,7 @@ { s->Indent(); GetArchitectureAtIndex(i, arch); - s->Printf("arch[%u] = %s\n", arch.AsCString()); + s->Printf("arch[%u] = %s\n", arch.GetArchitectureName()); } for (i=0; iIndent(); GetArchitectureAtIndex(i, arch); - s->Printf("arch[%u] = %s\n", arch.AsCString()); + s->Printf("arch[%u] = %s\n", arch.GetArchitectureName()); } for (i=0; iGetArchitecture(); Modified: lldb/trunk/source/Plugins/ObjectFile/ELF/ObjectFileELF.cpp URL: http://llvm.org/viewvc/llvm-project/lldb/trunk/source/Plugins/ObjectFile/ELF/ObjectFileELF.cpp?rev=126278&r1=126277&r2=126278&view=diff ============================================================================== --- lldb/trunk/source/Plugins/ObjectFile/ELF/ObjectFileELF.cpp (original) +++ lldb/trunk/source/Plugins/ObjectFile/ELF/ObjectFileELF.cpp Tue Feb 22 18:35:02 2011 @@ -19,6 +19,7 @@ #include "lldb/Core/PluginManager.h" #include "lldb/Core/Section.h" #include "lldb/Core/Stream.h" +#include "lldb/Host/Host.h" #define CASE_AND_STREAM(s, def, width) \ case def: s->Printf("%-*s", width, #def); break; @@ -1045,28 +1046,9 @@ bool ObjectFileELF::GetArchitecture (ArchSpec &arch) { - switch (m_header.e_machine) - { - default: - assert(false && "Unexpected machine type."); - break; - case EM_SPARC: arch.GetTriple().setArchName("sparc"); break; - case EM_386: arch.GetTriple().setArchName("i386"); break; - case EM_68K: arch.GetTriple().setArchName("68k"); break; - case EM_88K: arch.GetTriple().setArchName("88k"); break; - case EM_860: arch.GetTriple().setArchName("i860"); break; - case EM_MIPS: arch.GetTriple().setArchName("mips"); break; - case EM_PPC: arch.GetTriple().setArchName("powerpc"); break; - case EM_PPC64: arch.GetTriple().setArchName("powerpc64"); break; - case EM_ARM: arch.GetTriple().setArchName("arm"); break; - case EM_X86_64: arch.GetTriple().setArchName("x86_64"); break; - } - // TODO: determine if there is a vendor in the ELF? Default to "linux" for now - arch.GetTriple().setOSName ("linux"); - // TODO: determine if there is an OS in the ELF? Default to "gnu" for now - arch.GetTriple().setVendorName("gnu"); - - arch.SetElfArch(m_header.e_machine, m_header.e_flags); + arch.SetArchitecture (lldb::eArchTypeELF, m_header.e_machine, m_header.e_flags); + arch.GetTriple().setOSName (Host::GetOSString().GetCString()); + arch.GetTriple().setVendorName(Host::GetVendorString().GetCString()); return true; } Modified: lldb/trunk/source/Plugins/ObjectFile/Mach-O/ObjectFileMachO.cpp URL: http://llvm.org/viewvc/llvm-project/lldb/trunk/source/Plugins/ObjectFile/Mach-O/ObjectFileMachO.cpp?rev=126278&r1=126277&r2=126278&view=diff ============================================================================== --- lldb/trunk/source/Plugins/ObjectFile/Mach-O/ObjectFileMachO.cpp (original) +++ lldb/trunk/source/Plugins/ObjectFile/Mach-O/ObjectFileMachO.cpp Tue Feb 22 18:35:02 2011 @@ -1351,7 +1351,7 @@ ArchSpec header_arch(eArchTypeMachO, m_header.cputype, m_header.cpusubtype); - *s << ", file = '" << m_file << "', arch = " << header_arch.AsCString() << "\n"; + *s << ", file = '" << m_file << "', arch = " << header_arch.GetArchitectureName() << "\n"; if (m_sections_ap.get()) m_sections_ap->Dump(s, NULL, true, UINT32_MAX); @@ -1439,7 +1439,7 @@ ObjectFileMachO::GetArchitecture (ArchSpec &arch) { lldb_private::Mutex::Locker locker(m_mutex); - arch.SetMachOArch(m_header.cputype, m_header.cpusubtype); + arch.SetArchitecture (lldb::eArchTypeMachO, m_header.cputype, m_header.cpusubtype); return true; } Modified: lldb/trunk/source/Plugins/Process/MacOSX-User/source/MacOSX/MachThreadContext_i386.cpp URL: http://llvm.org/viewvc/llvm-project/lldb/trunk/source/Plugins/Process/MacOSX-User/source/MacOSX/MachThreadContext_i386.cpp?rev=126278&r1=126277&r2=126278&view=diff ============================================================================== --- lldb/trunk/source/Plugins/Process/MacOSX-User/source/MacOSX/MachThreadContext_i386.cpp (original) +++ lldb/trunk/source/Plugins/Process/MacOSX-User/source/MacOSX/MachThreadContext_i386.cpp Tue Feb 22 18:35:02 2011 @@ -42,7 +42,11 @@ void MachThreadContext_i386::Initialize() { - ArchSpec arch_spec("i386"); + llvm::Triple triple; + triple.setArch (llvm::Triple::x86); + triple.setVendor (llvm::Triple::Apple); + triple.setOS (llvm::Triple::Darwin); + ArchSpec arch_spec (triple); ProcessMacOSX::AddArchCreateCallback(arch_spec, MachThreadContext_i386::Create); } Modified: lldb/trunk/source/Plugins/Process/MacOSX-User/source/MacOSX/MachThreadContext_x86_64.cpp URL: http://llvm.org/viewvc/llvm-project/lldb/trunk/source/Plugins/Process/MacOSX-User/source/MacOSX/MachThreadContext_x86_64.cpp?rev=126278&r1=126277&r2=126278&view=diff ============================================================================== --- lldb/trunk/source/Plugins/Process/MacOSX-User/source/MacOSX/MachThreadContext_x86_64.cpp (original) +++ lldb/trunk/source/Plugins/Process/MacOSX-User/source/MacOSX/MachThreadContext_x86_64.cpp Tue Feb 22 18:35:02 2011 @@ -11,6 +11,8 @@ #include +#include "llvm/ADT/Triple.h" + #include "lldb/Symbol/Function.h" #include "lldb/Symbol/Symbol.h" @@ -41,7 +43,11 @@ void MachThreadContext_x86_64::Initialize() { - ArchSpec arch_spec("x86_64"); + llvm::Triple triple; + triple.setArch (llvm::Triple::x86_64); + triple.setVendor (llvm::Triple::Apple); + triple.setOS (llvm::Triple::Darwin); + ArchSpec arch_spec (triple); ProcessMacOSX::AddArchCreateCallback(arch_spec, MachThreadContext_x86_64::Create); } Modified: lldb/trunk/source/Plugins/Process/MacOSX-User/source/ProcessMacOSX.cpp URL: http://llvm.org/viewvc/llvm-project/lldb/trunk/source/Plugins/Process/MacOSX-User/source/ProcessMacOSX.cpp?rev=126278&r1=126277&r2=126278&view=diff ============================================================================== --- lldb/trunk/source/Plugins/Process/MacOSX-User/source/ProcessMacOSX.cpp (original) +++ lldb/trunk/source/Plugins/Process/MacOSX-User/source/ProcessMacOSX.cpp Tue Feb 22 18:35:02 2011 @@ -337,7 +337,9 @@ // Set our user ID to an invalid process ID. SetID (LLDB_INVALID_PROCESS_ID); error.SetErrorToGenericError (); - error.SetErrorStringWithFormat("Failed to get object file from '%s' for arch %s.\n", module->GetFileSpec().GetFilename().AsCString(), module->GetArchitecture().AsCString()); + error.SetErrorStringWithFormat("Failed to get object file from '%s' for arch %s.\n", + module->GetFileSpec().GetFilename().AsCString(), + module->GetArchitecture().GetArchitectureName()); } // Return the process ID we have @@ -498,16 +500,16 @@ static const uint8_t g_ppc_breakpoint_opcode[] = { 0x7F, 0xC0, 0x00, 0x08 }; static const uint8_t g_i386_breakpoint_opcode[] = { 0xCC }; - ArchSpec::CPU arch_cpu = m_arch_spec.GetGenericCPUType(); - switch (arch_cpu) + llvm::Triple::ArchType machine = m_arch_spec.GetMachine(); + switch (machine) { - case ArchSpec::eCPU_i386: - case ArchSpec::eCPU_x86_64: + case llvm::Triple::x86: + case llvm::Triple::x86_64: trap_opcode = g_i386_breakpoint_opcode; trap_opcode_size = sizeof(g_i386_breakpoint_opcode); break; - case ArchSpec::eCPU_arm: + case llvm::Triple::arm: // TODO: fill this in for ARM. We need to dig up the symbol for // the address in the breakpoint locaiton and figure out if it is // an ARM or Thumb breakpoint. @@ -515,8 +517,8 @@ trap_opcode_size = sizeof(g_arm_breakpoint_opcode); break; - case ArchSpec::eCPU_ppc: - case ArchSpec::eCPU_ppc64: + case llvm::Triple::ppc: + case llvm::Triple::ppc64: trap_opcode = g_ppc_breakpoint_opcode; trap_opcode_size = sizeof(g_ppc_breakpoint_opcode); break; @@ -1672,19 +1674,16 @@ // We don't need to do this for ARM, and we really shouldn't now that we // have multiple CPU subtypes and no posix_spawnattr call that allows us // to set which CPU subtype to launch... - if (arch_spec.GetType() == eArchTypeMachO) + cpu_type_t cpu = arch_spec.GetMachOCPUType(); + if (cpu != 0 && cpu != UINT32_MAX && cpu != LLDB_INVALID_CPUTYPE) { - cpu_type_t cpu = arch_spec.GetCPUType(); - if (cpu != 0 && cpu != UINT32_MAX && cpu != LLDB_INVALID_CPUTYPE) - { - size_t ocount = 0; - err.SetError( ::posix_spawnattr_setbinpref_np (&attr, 1, &cpu, &ocount), eErrorTypePOSIX); - if (err.Fail() || log) - err.PutToLog(log.get(), "::posix_spawnattr_setbinpref_np ( &attr, 1, cpu_type = 0x%8.8x, count => %zu )", cpu, ocount); + size_t ocount = 0; + err.SetError( ::posix_spawnattr_setbinpref_np (&attr, 1, &cpu, &ocount), eErrorTypePOSIX); + if (err.Fail() || log) + err.PutToLog(log.get(), "::posix_spawnattr_setbinpref_np ( &attr, 1, cpu_type = 0x%8.8x, count => %zu )", cpu, ocount); - if (err.Fail() != 0 || ocount != 1) - return LLDB_INVALID_PROCESS_ID; - } + if (err.Fail() != 0 || ocount != 1) + return LLDB_INVALID_PROCESS_ID; } #endif Modified: lldb/trunk/source/Plugins/Process/Utility/ArchDefaultUnwindPlan-x86.cpp URL: http://llvm.org/viewvc/llvm-project/lldb/trunk/source/Plugins/Process/Utility/ArchDefaultUnwindPlan-x86.cpp?rev=126278&r1=126277&r2=126278&view=diff ============================================================================== --- lldb/trunk/source/Plugins/Process/Utility/ArchDefaultUnwindPlan-x86.cpp (original) +++ lldb/trunk/source/Plugins/Process/Utility/ArchDefaultUnwindPlan-x86.cpp Tue Feb 22 18:35:02 2011 @@ -18,7 +18,7 @@ lldb_private::ArchDefaultUnwindPlan * ArchDefaultUnwindPlan_x86_64::CreateInstance (const lldb_private::ArchSpec &arch) { - if (arch.GetGenericCPUType () == ArchSpec::eCPU_x86_64) + if (arch.GetMachine () == llvm::Triple::x86_64) return new ArchDefaultUnwindPlan_x86_64 (); return NULL; } @@ -126,7 +126,7 @@ lldb_private::ArchDefaultUnwindPlan * ArchDefaultUnwindPlan_i386::CreateInstance (const lldb_private::ArchSpec &arch) { - if (arch.GetGenericCPUType () == ArchSpec::eCPU_i386) + if (arch.GetMachine () == llvm::Triple::x86) return new ArchDefaultUnwindPlan_i386 (); return NULL; } Modified: lldb/trunk/source/Plugins/Process/Utility/ArchVolatileRegs-x86.cpp URL: http://llvm.org/viewvc/llvm-project/lldb/trunk/source/Plugins/Process/Utility/ArchVolatileRegs-x86.cpp?rev=126278&r1=126277&r2=126278&view=diff ============================================================================== --- lldb/trunk/source/Plugins/Process/Utility/ArchVolatileRegs-x86.cpp (original) +++ lldb/trunk/source/Plugins/Process/Utility/ArchVolatileRegs-x86.cpp Tue Feb 22 18:35:02 2011 @@ -34,22 +34,20 @@ lldb_private::ArchVolatileRegs * ArchVolatileRegs_x86::CreateInstance (const lldb_private::ArchSpec &arch) { - uint32_t cpu = arch.GetCPUType (); - if (cpu != llvm::MachO::CPUTypeX86_64 && cpu != llvm::MachO::CPUTypeI386) - return NULL; - - return new ArchVolatileRegs_x86 (cpu); + llvm::Triple::ArchType cpu = arch.GetMachine (); + if (cpu == llvm::Triple::x86 || cpu == llvm::Triple::x86_64) + return new ArchVolatileRegs_x86 (cpu); + return NULL; } -ArchVolatileRegs_x86::ArchVolatileRegs_x86(int cpu) : - lldb_private::ArchVolatileRegs(), - m_cpu(cpu), - m_non_volatile_regs() +ArchVolatileRegs_x86::ArchVolatileRegs_x86(llvm::Triple::ArchType cpu) : + lldb_private::ArchVolatileRegs(), + m_cpu(cpu), + m_non_volatile_regs() { } void - ArchVolatileRegs_x86::initialize_regset(Thread& thread) { if (m_non_volatile_regs.size() > 0) @@ -78,13 +76,14 @@ const char **names; int namecount; - if (m_cpu == llvm::MachO::CPUTypeX86_64) + if (m_cpu == llvm::Triple::x86_64) { names = x86_64_regnames; namecount = sizeof (x86_64_regnames) / sizeof (char *); } else { + assert (m_cpu == llvm::Triple::x86); names = i386_regnames; namecount = sizeof (i386_regnames) / sizeof (char *); } Modified: lldb/trunk/source/Plugins/Process/Utility/ArchVolatileRegs-x86.h URL: http://llvm.org/viewvc/llvm-project/lldb/trunk/source/Plugins/Process/Utility/ArchVolatileRegs-x86.h?rev=126278&r1=126277&r2=126278&view=diff ============================================================================== --- lldb/trunk/source/Plugins/Process/Utility/ArchVolatileRegs-x86.h (original) +++ lldb/trunk/source/Plugins/Process/Utility/ArchVolatileRegs-x86.h Tue Feb 22 18:35:02 2011 @@ -11,6 +11,7 @@ #define liblldb_ArchVolatileRegs_x86_h_ #include "lldb/lldb-private.h" +#include "lldb/Core/ArchSpec.h" #include "lldb/Utility/ArchVolatileRegs.h" #include @@ -62,11 +63,11 @@ EnablePluginLogging (lldb_private::Stream *strm, lldb_private::Args &command); private: - ArchVolatileRegs_x86(int cpu); // Call CreateInstance instead. + ArchVolatileRegs_x86(llvm::Triple::ArchType cpu); // Call CreateInstance instead. void initialize_regset(lldb_private::Thread& thread); - int m_cpu; + llvm::Triple::ArchType m_cpu; std::set m_non_volatile_regs; }; Modified: lldb/trunk/source/Plugins/Process/Utility/StopInfoMachException.cpp URL: http://llvm.org/viewvc/llvm-project/lldb/trunk/source/Plugins/Process/Utility/StopInfoMachException.cpp?rev=126278&r1=126277&r2=126278&view=diff ============================================================================== --- lldb/trunk/source/Plugins/Process/Utility/StopInfoMachException.cpp (original) +++ lldb/trunk/source/Plugins/Process/Utility/StopInfoMachException.cpp Tue Feb 22 18:35:02 2011 @@ -30,7 +30,7 @@ { if (m_description.empty() && m_value != 0) { - ArchSpec::CPU cpu = m_thread.GetProcess().GetTarget().GetArchitecture().GetGenericCPUType(); + const llvm::Triple::ArchType cpu = m_thread.GetProcess().GetTarget().GetArchitecture().GetMachine(); const char *exc_desc = NULL; const char *code_label = "code"; @@ -44,7 +44,7 @@ subcode_label = "address"; switch (cpu) { - case ArchSpec::eCPU_arm: + case llvm::Triple::arm: switch (m_exc_code) { case 0x101: code_desc = "EXC_ARM_DA_ALIGN"; break; @@ -52,8 +52,8 @@ } break; - case ArchSpec::eCPU_ppc: - case ArchSpec::eCPU_ppc64: + case llvm::Triple::ppc: + case llvm::Triple::ppc64: switch (m_exc_code) { case 0x101: code_desc = "EXC_PPC_VM_PROT_READ"; break; @@ -71,14 +71,14 @@ exc_desc = "EXC_BAD_INSTRUCTION"; switch (cpu) { - case ArchSpec::eCPU_i386: - case ArchSpec::eCPU_x86_64: + case llvm::Triple::x86: + case llvm::Triple::x86_64: if (m_exc_code == 1) code_desc = "EXC_I386_INVOP"; break; - case ArchSpec::eCPU_ppc: - case ArchSpec::eCPU_ppc64: + case llvm::Triple::ppc: + case llvm::Triple::ppc64: switch (m_exc_code) { case 1: code_desc = "EXC_PPC_INVALID_SYSCALL"; break; @@ -90,7 +90,7 @@ } break; - case ArchSpec::eCPU_arm: + case llvm::Triple::arm: if (m_exc_code == 1) code_desc = "EXC_ARM_UNDEFINED"; break; @@ -104,8 +104,8 @@ exc_desc = "EXC_ARITHMETIC"; switch (cpu) { - case ArchSpec::eCPU_i386: - case ArchSpec::eCPU_x86_64: + case llvm::Triple::x86: + case llvm::Triple::x86_64: switch (m_exc_code) { case 1: code_desc = "EXC_I386_DIV"; break; @@ -119,8 +119,8 @@ } break; - case ArchSpec::eCPU_ppc: - case ArchSpec::eCPU_ppc64: + case llvm::Triple::ppc: + case llvm::Triple::ppc64: switch (m_exc_code) { case 1: code_desc = "EXC_PPC_OVERFLOW"; break; @@ -157,8 +157,8 @@ exc_desc = "EXC_BREAKPOINT"; switch (cpu) { - case ArchSpec::eCPU_i386: - case ArchSpec::eCPU_x86_64: + case llvm::Triple::x86: + case llvm::Triple::x86_64: switch (m_exc_code) { case 1: subcode_desc = "EXC_I386_SGL"; break; @@ -166,15 +166,15 @@ } break; - case ArchSpec::eCPU_ppc: - case ArchSpec::eCPU_ppc64: + case llvm::Triple::ppc: + case llvm::Triple::ppc64: switch (m_exc_code) { case 1: subcode_desc = "EXC_PPC_BREAKPOINT"; break; } break; - case ArchSpec::eCPU_arm: + case llvm::Triple::arm: switch (m_exc_code) { case 1: subcode_desc = "EXC_ARM_BREAKPOINT"; break; @@ -248,7 +248,7 @@ { if (exc_type != 0) { - ArchSpec::CPU cpu = thread.GetProcess().GetTarget().GetArchitecture().GetGenericCPUType(); + const llvm::Triple::ArchType cpu = thread.GetProcess().GetTarget().GetArchitecture().GetMachine(); switch (exc_type) { @@ -258,8 +258,8 @@ case 2: // EXC_BAD_INSTRUCTION switch (cpu) { - case ArchSpec::eCPU_ppc: - case ArchSpec::eCPU_ppc64: + case llvm::Triple::ppc: + case llvm::Triple::ppc64: switch (exc_code) { case 1: // EXC_PPC_INVALID_SYSCALL @@ -293,8 +293,8 @@ bool is_software_breakpoint = false; switch (cpu) { - case ArchSpec::eCPU_i386: - case ArchSpec::eCPU_x86_64: + case llvm::Triple::x86: + case llvm::Triple::x86_64: if (exc_code == 1) // EXC_I386_SGL { return StopInfo::CreateStopReasonToTrace(thread); @@ -305,12 +305,12 @@ } break; - case ArchSpec::eCPU_ppc: - case ArchSpec::eCPU_ppc64: + case llvm::Triple::ppc: + case llvm::Triple::ppc64: is_software_breakpoint = exc_code == 1; // EXC_PPC_BREAKPOINT break; - case ArchSpec::eCPU_arm: + case llvm::Triple::arm: is_software_breakpoint = exc_code == 1; // EXC_ARM_BREAKPOINT break; Modified: lldb/trunk/source/Plugins/Process/Utility/UnwindAssemblyProfiler-x86.cpp URL: http://llvm.org/viewvc/llvm-project/lldb/trunk/source/Plugins/Process/Utility/UnwindAssemblyProfiler-x86.cpp?rev=126278&r1=126277&r2=126278&view=diff ============================================================================== --- lldb/trunk/source/Plugins/Process/Utility/UnwindAssemblyProfiler-x86.cpp (original) +++ lldb/trunk/source/Plugins/Process/Utility/UnwindAssemblyProfiler-x86.cpp Tue Feb 22 18:35:02 2011 @@ -847,11 +847,12 @@ UnwindAssemblyProfiler * UnwindAssemblyProfiler_x86::CreateInstance (const ArchSpec &arch) { - ArchSpec::CPU cpu = arch.GetGenericCPUType (); - if (cpu != ArchSpec::eCPU_x86_64 && cpu != ArchSpec::eCPU_i386) - return NULL; - - return new UnwindAssemblyProfiler_x86 (cpu == ArchSpec::eCPU_x86_64 ? k_x86_64 : k_i386); + const llvm::Triple::ArchType cpu = arch.GetMachine (); + if (cpu == llvm::Triple::x86) + return new UnwindAssemblyProfiler_x86 (k_i386); + else if (cpu == llvm::Triple::x86_64) + return new UnwindAssemblyProfiler_x86 (k_x86_64); + return NULL; } Modified: lldb/trunk/source/Plugins/Process/Utility/UnwindMacOSXFrameBackchain.cpp URL: http://llvm.org/viewvc/llvm-project/lldb/trunk/source/Plugins/Process/Utility/UnwindMacOSXFrameBackchain.cpp?rev=126278&r1=126277&r2=126278&view=diff ============================================================================== --- lldb/trunk/source/Plugins/Process/Utility/UnwindMacOSXFrameBackchain.cpp (original) +++ lldb/trunk/source/Plugins/Process/Utility/UnwindMacOSXFrameBackchain.cpp Tue Feb 22 18:35:02 2011 @@ -32,12 +32,12 @@ { if (m_cursors.empty()) { - const ArchSpec target_arch (m_thread.GetProcess().GetTarget().GetArchitecture ()); + const ArchSpec& target_arch = m_thread.GetProcess().GetTarget().GetArchitecture (); // Frame zero should always be supplied by the thread... StackFrameSP frame_sp (m_thread.GetStackFrameAtIndex (0)); - if (target_arch == ArchSpec("x86_64")) + if (target_arch.GetMachine() == llvm::Triple::x86_64) GetStackFrameData_x86_64 (frame_sp.get()); - else if (target_arch == ArchSpec("i386")) + else if (target_arch.GetMachine() == llvm::Triple::x86) GetStackFrameData_i386 (frame_sp.get()); } Modified: lldb/trunk/source/Plugins/Process/gdb-remote/GDBRemoteCommunication.cpp URL: http://llvm.org/viewvc/llvm-project/lldb/trunk/source/Plugins/Process/gdb-remote/GDBRemoteCommunication.cpp?rev=126278&r1=126277&r2=126278&view=diff ============================================================================== --- lldb/trunk/source/Plugins/Process/gdb-remote/GDBRemoteCommunication.cpp (original) +++ lldb/trunk/source/Plugins/Process/gdb-remote/GDBRemoteCommunication.cpp Tue Feb 22 18:35:02 2011 @@ -1001,7 +1001,7 @@ } if (cpu != LLDB_INVALID_CPUTYPE) - m_arch.SetMachOArch (cpu, sub); + m_arch.SetArchitecture (lldb::eArchTypeMachO, cpu, sub); } } return m_supports_qHostInfo == eLazyBoolYes; Modified: lldb/trunk/source/Plugins/Process/gdb-remote/ProcessGDBRemote.cpp URL: http://llvm.org/viewvc/llvm-project/lldb/trunk/source/Plugins/Process/gdb-remote/ProcessGDBRemote.cpp?rev=126278&r1=126277&r2=126278&view=diff ============================================================================== --- lldb/trunk/source/Plugins/Process/gdb-remote/ProcessGDBRemote.cpp (original) +++ lldb/trunk/source/Plugins/Process/gdb-remote/ProcessGDBRemote.cpp Tue Feb 22 18:35:02 2011 @@ -328,8 +328,7 @@ // We didn't get anything. See if we are debugging ARM and fill with // a hard coded register set until we can get an updated debugserver // down on the devices. - ArchSpec arm_arch ("arm"); - if (GetTarget().GetArchitecture() == arm_arch) + if (GetTarget().GetArchitecture().GetMachine() == llvm::Triple::arm) m_register_info.HardcodeARMRegisters(); } m_register_info.Finalize (); @@ -553,7 +552,9 @@ { // Set our user ID to an invalid process ID. SetID(LLDB_INVALID_PROCESS_ID); - error.SetErrorStringWithFormat("Failed to get object file from '%s' for arch %s.\n", module->GetFileSpec().GetFilename().AsCString(), module->GetArchitecture().AsCString()); + error.SetErrorStringWithFormat("Failed to get object file from '%s' for arch %s.\n", + module->GetFileSpec().GetFilename().AsCString(), + module->GetArchitecture().GetArchitectureName()); } return error; @@ -642,8 +643,8 @@ // it has, so we really need to take the remote host architecture as our // defacto architecture in this case. - if (gdb_remote_arch == ArchSpec ("arm") && - vendor && ::strcmp(vendor, "apple") == 0) + if (gdb_remote_arch.GetMachine() == llvm::Triple::arm && + gdb_remote_arch.GetTriple().getVendor() == llvm::Triple::Apple) { GetTarget().SetArchitecture (gdb_remote_arch); target_arch = gdb_remote_arch; @@ -1044,16 +1045,16 @@ static const uint8_t g_ppc_breakpoint_opcode[] = { 0x7F, 0xC0, 0x00, 0x08 }; static const uint8_t g_i386_breakpoint_opcode[] = { 0xCC }; - ArchSpec::CPU arch_cpu = GetTarget().GetArchitecture().GetGenericCPUType(); - switch (arch_cpu) + const llvm::Triple::ArchType machine = GetTarget().GetArchitecture().GetMachine(); + switch (machine) { - case ArchSpec::eCPU_i386: - case ArchSpec::eCPU_x86_64: + case llvm::Triple::x86: + case llvm::Triple::x86_64: trap_opcode = g_i386_breakpoint_opcode; trap_opcode_size = sizeof(g_i386_breakpoint_opcode); break; - case ArchSpec::eCPU_arm: + case llvm::Triple::arm: // TODO: fill this in for ARM. We need to dig up the symbol for // the address in the breakpoint locaiton and figure out if it is // an ARM or Thumb breakpoint. @@ -1061,8 +1062,8 @@ trap_opcode_size = sizeof(g_arm_breakpoint_opcode); break; - case ArchSpec::eCPU_ppc: - case ArchSpec::eCPU_ppc64: + case llvm::Triple::ppc: + case llvm::Triple::ppc64: trap_opcode = g_ppc_breakpoint_opcode; trap_opcode_size = sizeof(g_ppc_breakpoint_opcode); break; @@ -1955,31 +1956,33 @@ Error local_err; // Errors that don't affect the spawning. if (log) - log->Printf ("%s ( path='%s', argv=%p, envp=%p, arch=%s )", __FUNCTION__, debugserver_path, inferior_argv, inferior_envp, inferior_arch.AsCString()); + log->Printf ("%s ( path='%s', argv=%p, envp=%p, arch=%s )", + __FUNCTION__, + debugserver_path, + inferior_argv, + inferior_envp, + inferior_arch.GetArchitectureName()); error.SetError( ::posix_spawnattr_init (&attr), eErrorTypePOSIX); if (error.Fail() || log) error.PutToLog(log.get(), "::posix_spawnattr_init ( &attr )"); if (error.Fail()) - return error;; + return error; #if !defined (__arm__) // We don't need to do this for ARM, and we really shouldn't now // that we have multiple CPU subtypes and no posix_spawnattr call // that allows us to set which CPU subtype to launch... - if (inferior_arch.GetType() == eArchTypeMachO) + cpu_type_t cpu = inferior_arch.GetMachOCPUType(); + if (cpu != 0 && cpu != UINT32_MAX && cpu != LLDB_INVALID_CPUTYPE) { - cpu_type_t cpu = inferior_arch.GetCPUType(); - if (cpu != 0 && cpu != UINT32_MAX && cpu != LLDB_INVALID_CPUTYPE) - { - size_t ocount = 0; - error.SetError( ::posix_spawnattr_setbinpref_np (&attr, 1, &cpu, &ocount), eErrorTypePOSIX); - if (error.Fail() || log) - error.PutToLog(log.get(), "::posix_spawnattr_setbinpref_np ( &attr, 1, cpu_type = 0x%8.8x, count => %zu )", cpu, ocount); - - if (error.Fail() != 0 || ocount != 1) - return error; - } + size_t ocount = 0; + error.SetError( ::posix_spawnattr_setbinpref_np (&attr, 1, &cpu, &ocount), eErrorTypePOSIX); + if (error.Fail() || log) + error.PutToLog(log.get(), "::posix_spawnattr_setbinpref_np ( &attr, 1, cpu_type = 0x%8.8x, count => %zu )", cpu, ocount); + + if (error.Fail() != 0 || ocount != 1) + return error; } #endif Modified: lldb/trunk/source/Plugins/Process/gdb-remote/ThreadGDBRemote.cpp URL: http://llvm.org/viewvc/llvm-project/lldb/trunk/source/Plugins/Process/gdb-remote/ThreadGDBRemote.cpp?rev=126278&r1=126277&r2=126278&view=diff ============================================================================== --- lldb/trunk/source/Plugins/Process/gdb-remote/ThreadGDBRemote.cpp (original) +++ lldb/trunk/source/Plugins/Process/gdb-remote/ThreadGDBRemote.cpp Tue Feb 22 18:35:02 2011 @@ -142,7 +142,8 @@ if (m_unwinder_ap.get() == NULL) { const ArchSpec target_arch (GetProcess().GetTarget().GetArchitecture ()); - if (target_arch == ArchSpec("x86_64") || target_arch == ArchSpec("i386")) + const llvm::Triple::ArchType machine = target_arch.GetMachine(); + if (machine == llvm::Triple::x86_64 || machine == llvm::Triple::x86) { m_unwinder_ap.reset (new UnwindLLDB (*this)); } Modified: lldb/trunk/source/Symbol/SymbolContext.cpp URL: http://llvm.org/viewvc/llvm-project/lldb/trunk/source/Symbol/SymbolContext.cpp?rev=126278&r1=126277&r2=126278&view=diff ============================================================================== --- lldb/trunk/source/Symbol/SymbolContext.cpp (original) +++ lldb/trunk/source/Symbol/SymbolContext.cpp Tue Feb 22 18:35:02 2011 @@ -182,7 +182,7 @@ module_sp->GetFileSpec().Dump(s); *s << '"'; if (module_sp->GetArchitecture().IsValid()) - s->Printf (", arch = \"%s\"", module_sp->GetArchitecture().AsCString()); + s->Printf (", arch = \"%s\"", module_sp->GetArchitecture().GetArchitectureName()); s->EOL(); } Modified: lldb/trunk/source/Target/Target.cpp URL: http://llvm.org/viewvc/llvm-project/lldb/trunk/source/Target/Target.cpp?rev=126278&r1=126277&r2=126278&view=diff ============================================================================== --- lldb/trunk/source/Target/Target.cpp (original) +++ lldb/trunk/source/Target/Target.cpp Tue Feb 22 18:35:02 2011 @@ -801,28 +801,20 @@ ArchSpec Target::GetDefaultArchitecture () { - lldb::UserSettingsControllerSP &settings_controller = GetSettingsController(); - lldb::SettableVariableType var_type; - Error err; - StringList result = settings_controller->GetVariable ("target.default-arch", var_type, "[]", err); - - const char *default_name = ""; - if (result.GetSize() == 1 && err.Success()) - default_name = result.GetStringAtIndex (0); - - ArchSpec default_arch (default_name); - return default_arch; + lldb::UserSettingsControllerSP settings_controller_sp (GetSettingsController()); + + if (settings_controller_sp) + return static_cast(settings_controller_sp.get())->GetArchitecture (); + return ArchSpec(); } void -Target::SetDefaultArchitecture (ArchSpec new_arch) +Target::SetDefaultArchitecture (const ArchSpec& arch) { - if (new_arch.IsValid()) - GetSettingsController ()->SetVariable ("target.default-arch", - new_arch.AsCString(), - lldb::eVarSetOperationAssign, - false, - "[]"); + lldb::UserSettingsControllerSP settings_controller_sp (GetSettingsController()); + + if (settings_controller_sp) + static_cast(settings_controller_sp.get())->GetArchitecture () = arch; } Target * @@ -854,7 +846,7 @@ { sstr.Printf ("%s_%s", module_sp->GetFileSpec().GetFilename().AsCString(), - module_sp->GetArchitecture().AsCString()); + module_sp->GetArchitecture().GetArchitectureName()); GetSettingsController()->RenameInstanceSettings (GetInstanceName().AsCString(), sstr.GetData()); } @@ -1053,11 +1045,9 @@ { if (var_name == GetSettingNameForDefaultArch()) { - ArchSpec tmp_spec (value); - if (tmp_spec.IsValid()) - m_default_architecture = tmp_spec; - else - err.SetErrorStringWithFormat ("'%s' is not a valid architecture.", value); + m_default_architecture.SetTriple (value); + if (!m_default_architecture.IsValid()) + err.SetErrorStringWithFormat ("'%s' is not a valid architecture or triple.", value); } return true; } @@ -1072,7 +1062,7 @@ { // If the arch is invalid (the default), don't show a string for it if (m_default_architecture.IsValid()) - value.AppendString (m_default_architecture.AsCString()); + value.AppendString (m_default_architecture.GetArchitectureName()); return true; } else Modified: lldb/trunk/source/Target/TargetList.cpp URL: http://llvm.org/viewvc/llvm-project/lldb/trunk/source/Target/TargetList.cpp?rev=126278&r1=126277&r2=126278&view=diff ============================================================================== --- lldb/trunk/source/Target/TargetList.cpp (original) +++ lldb/trunk/source/Target/TargetList.cpp Tue Feb 22 18:35:02 2011 @@ -58,7 +58,7 @@ "TargetList::CreateTarget (file = '%s/%s', arch = '%s', uuid = %p)", file.GetDirectory().AsCString(), file.GetFilename().AsCString(), - arch.AsCString(), + arch.GetArchitectureName(), uuid_ptr); Error error; @@ -96,7 +96,7 @@ file.GetDirectory().AsCString(), file.GetDirectory() ? "/" : "", file.GetFilename().AsCString(), - arch.AsCString()); + arch.GetArchitectureName()); } else { Modified: lldb/trunk/test/dotest.py URL: http://llvm.org/viewvc/llvm-project/lldb/trunk/test/dotest.py?rev=126278&r1=126277&r2=126278&view=diff ============================================================================== --- lldb/trunk/test/dotest.py (original) +++ lldb/trunk/test/dotest.py Tue Feb 22 18:35:02 2011 @@ -629,7 +629,7 @@ else: lldb_log_option = "event process expr state api" ci.HandleCommand( - "log enable -T -n -f " + os.environ["LLDB_LOG"] + " lldb " + lldb_log_option, + "log enable -n -f " + os.environ["LLDB_LOG"] + " lldb " + lldb_log_option, res) if not res.Succeeded(): raise Exception('log enable failed (check LLDB_LOG env variable.') @@ -641,7 +641,7 @@ else: gdb_remote_log_option = "packets process" ci.HandleCommand( - "log enable -T -n -f " + os.environ["GDB_REMOTE_LOG"] + " process.gdb-remote " + "log enable -n -f " + os.environ["GDB_REMOTE_LOG"] + " process.gdb-remote " + gdb_remote_log_option, res) if not res.Succeeded(): From johnny.chen at apple.com Tue Feb 22 19:01:21 2011 From: johnny.chen at apple.com (Johnny Chen) Date: Wed, 23 Feb 2011 01:01:21 -0000 Subject: [Lldb-commits] [lldb] r126283 - in /lldb/trunk/source/Plugins/Instruction/ARM: EmulateInstructionARM.cpp EmulateInstructionARM.h Message-ID: <20110223010122.10EBF2A6C12C@llvm.org> Author: johnny Date: Tue Feb 22 19:01:21 2011 New Revision: 126283 URL: http://llvm.org/viewvc/llvm-project?rev=126283&view=rev Log: Add emulation methods for "SBC (immediate)" and "SBC (register)" operations. Modified: lldb/trunk/source/Plugins/Instruction/ARM/EmulateInstructionARM.cpp lldb/trunk/source/Plugins/Instruction/ARM/EmulateInstructionARM.h Modified: lldb/trunk/source/Plugins/Instruction/ARM/EmulateInstructionARM.cpp URL: http://llvm.org/viewvc/llvm-project/lldb/trunk/source/Plugins/Instruction/ARM/EmulateInstructionARM.cpp?rev=126283&r1=126282&r2=126283&view=diff ============================================================================== --- lldb/trunk/source/Plugins/Instruction/ARM/EmulateInstructionARM.cpp (original) +++ lldb/trunk/source/Plugins/Instruction/ARM/EmulateInstructionARM.cpp Tue Feb 22 19:01:21 2011 @@ -6165,6 +6165,163 @@ return true; } +// Subtract with Carry (immediate) subtracts an immediate value and the value of +// NOT (Carry flag) from a register value, and writes the result to the destination register. +// It can optionally update the condition flags based on the result. +bool +EmulateInstructionARM::EmulateSBCImm (ARMEncoding encoding) +{ +#if 0 + // ARM pseudo code... + if ConditionPassed() then + EncodingSpecificOperations(); + (result, carry, overflow) = AddWithCarry(R[n], NOT(imm32), APSR.C); + if d == 15 then // Can only occur for ARM encoding + ALUWritePC(result); // setflags is always FALSE here + else + R[d] = result; + if setflags then + APSR.N = result<31>; + APSR.Z = IsZeroBit(result); + APSR.C = carry; + APSR.V = overflow; +#endif + + bool success = false; + const uint32_t opcode = OpcodeAsUnsigned (&success); + if (!success) + return false; + + uint32_t Rd; // the destination register + uint32_t Rn; // the first operand + bool setflags; + uint32_t imm32; // the immediate value to be added to the value obtained from Rn + switch (encoding) { + case eEncodingT1: + Rd = Bits32(opcode, 11, 8); + Rn = Bits32(opcode, 19, 16); + setflags = BitIsSet(opcode, 20); + imm32 = ThumbExpandImm(opcode); // imm32 = ThumbExpandImm(i:imm3:imm8) + if (BadReg(Rd) || BadReg(Rn)) + return false; + break; + case eEncodingA1: + Rd = Bits32(opcode, 15, 12); + Rn = Bits32(opcode, 19, 16); + setflags = BitIsSet(opcode, 20); + imm32 = ARMExpandImm(opcode); // imm32 = ARMExpandImm(imm12) + // if Rd == '1111' && S == '1' then SEE SUBS PC, LR and related instructions; + // TODO: Emulate SUBS PC, LR and related instructions. + if (Rd == 15 && setflags) + return false; + break; + default: + return false; + } + // Read the register value from the operand register Rn. + uint32_t reg_val = ReadCoreReg(Rn, &success); + if (!success) + return false; + + AddWithCarryResult res = AddWithCarry(reg_val, ~imm32, APSR_C); + + EmulateInstruction::Context context; + context.type = EmulateInstruction::eContextImmediate; + context.SetNoArgs (); + + if (!WriteCoreRegOptionalFlags(context, res.result, Rd, setflags, res.carry_out, res.overflow)) + return false; + + return true; +} + +// Subtract with Carry (register) subtracts an optionally-shifted register value and the value of +// NOT (Carry flag) from a register value, and writes the result to the destination register. +// It can optionally update the condition flags based on the result. +bool +EmulateInstructionARM::EmulateSBCReg (ARMEncoding encoding) +{ +#if 0 + // ARM pseudo code... + if ConditionPassed() then + EncodingSpecificOperations(); + shifted = Shift(R[m], shift_t, shift_n, APSR.C); + (result, carry, overflow) = AddWithCarry(R[n], NOT(shifted), APSR.C); + if d == 15 then // Can only occur for ARM encoding + ALUWritePC(result); // setflags is always FALSE here + else + R[d] = result; + if setflags then + APSR.N = result<31>; + APSR.Z = IsZeroBit(result); + APSR.C = carry; + APSR.V = overflow; +#endif + + bool success = false; + const uint32_t opcode = OpcodeAsUnsigned (&success); + if (!success) + return false; + + uint32_t Rd; // the destination register + uint32_t Rn; // the first operand + uint32_t Rm; // the second operand + bool setflags; + ARM_ShifterType shift_t; + uint32_t shift_n; // the shift applied to the value read from Rm + switch (encoding) { + case eEncodingT1: + Rd = Rn = Bits32(opcode, 2, 0); + Rm = Bits32(opcode, 5, 3); + setflags = !InITBlock(); + shift_t = SRType_LSL; + shift_n = 0; + break; + case eEncodingT2: + Rd = Bits32(opcode, 11, 8); + Rn = Bits32(opcode, 19, 16); + Rm = Bits32(opcode, 3, 0); + setflags = BitIsSet(opcode, 20); + shift_n = DecodeImmShiftThumb(opcode, shift_t); + if (BadReg(Rd) || BadReg(Rn) || BadReg(Rm)) + return false; + break; + case eEncodingA1: + Rd = Bits32(opcode, 15, 12); + Rn = Bits32(opcode, 19, 16); + Rm = Bits32(opcode, 3, 0); + setflags = BitIsSet(opcode, 20); + shift_n = DecodeImmShiftARM(opcode, shift_t); + // if Rd == '1111' && S == '1' then SEE SUBS PC, LR and related instructions; + // TODO: Emulate SUBS PC, LR and related instructions. + if (Rd == 15 && setflags) + return false; + break; + default: + return false; + } + // Read the register value from register Rn. + uint32_t val1 = ReadCoreReg(Rn, &success); + if (!success) + return false; + + // Read the register value from register Rm. + uint32_t val2 = ReadCoreReg(Rm, &success); + if (!success) + return false; + + uint32_t shifted = Shift(val2, shift_t, shift_n, APSR_C); + AddWithCarryResult res = AddWithCarry(val1, ~shifted, APSR_C); + + EmulateInstruction::Context context; + context.type = EmulateInstruction::eContextImmediate; + context.SetNoArgs(); + if (!WriteCoreRegOptionalFlags(context, res.result, Rd, setflags, res.carry_out, res.overflow)) + return false; + + return true; +} + // Test Equivalence (immediate) performs a bitwise exclusive OR operation on a register value and an // immediate value. It updates the condition flags based on the result, and discards the result. bool @@ -6517,6 +6674,10 @@ { 0x0fe00000, 0x02e00000, ARMvAll, eEncodingA1, eSize32, &EmulateInstructionARM::EmulateRSCImm, "rsc{s} , , #"}, // rsc (register) { 0x0fe00010, 0x00e00000, ARMvAll, eEncodingA1, eSize32, &EmulateInstructionARM::EmulateRSCReg, "rsc{s} , , {,}"}, + // sbc (immediate) + { 0x0fe00000, 0x02c00000, ARMvAll, eEncodingA1, eSize32, &EmulateInstructionARM::EmulateSBCImm, "sbc{s} , , #"}, + // sbc (register) + { 0x0fe00010, 0x00c00000, ARMvAll, eEncodingA1, eSize32, &EmulateInstructionARM::EmulateSBCReg, "sbc{s} , , {,}"}, // teq (immediate) { 0x0ff0f000, 0x03300000, ARMvAll, eEncodingA1, eSize32, &EmulateInstructionARM::EmulateTEQImm, "teq , #const"}, // teq (register) @@ -6703,6 +6864,11 @@ { 0xfbe08000, 0xf1c00000, ARMV6T2_ABOVE, eEncodingT2, eSize32, &EmulateInstructionARM::EmulateRSBImm, "rsb{s}.w , , #"}, // rsb (register) { 0xffe08000, 0xea400000, ARMV6T2_ABOVE, eEncodingT1, eSize32, &EmulateInstructionARM::EmulateRSBReg, "rsb{s}.w , , {,}"}, + // sbc (immediate) + { 0xfbe08000, 0xf1600000, ARMV6T2_ABOVE, eEncodingT1, eSize32, &EmulateInstructionARM::EmulateSBCImm, "sbc{s} , , #"}, + // sbc (register) + { 0xffffffc0, 0x00004180, ARMvAll, eEncodingT1, eSize16, &EmulateInstructionARM::EmulateSBCReg, "sbcs|sbc , "}, + { 0xffe08000, 0xeb600000, ARMV6T2_ABOVE, eEncodingT2, eSize32, &EmulateInstructionARM::EmulateSBCReg, "sbc{s}.w , , {,}"}, // teq (immediate) { 0xfbf08f00, 0xf0900f00, ARMV6T2_ABOVE, eEncodingT1, eSize32, &EmulateInstructionARM::EmulateTEQImm, "teq , #"}, // teq (register) Modified: lldb/trunk/source/Plugins/Instruction/ARM/EmulateInstructionARM.h URL: http://llvm.org/viewvc/llvm-project/lldb/trunk/source/Plugins/Instruction/ARM/EmulateInstructionARM.h?rev=126283&r1=126282&r2=126283&view=diff ============================================================================== --- lldb/trunk/source/Plugins/Instruction/ARM/EmulateInstructionARM.h (original) +++ lldb/trunk/source/Plugins/Instruction/ARM/EmulateInstructionARM.h Tue Feb 22 19:01:21 2011 @@ -669,13 +669,13 @@ bool EmulateRSCReg (ARMEncoding encoding); - // A8.6.150 SBC (immediate) - Encoding A1 + // A8.6.150 SBC (immediate) bool - EmulateSBCImmediate (ARMEncoding encoding); + EmulateSBCImm (ARMEncoding encoding); - // A8.6.151 SBC (register) - Encoding T1, A1 + // A8.6.151 SBC (register) bool - EmulateSBCRegister (ARMEncoding encoding); + EmulateSBCReg (ARMEncoding encoding); // A8.6.210 SUB (immediate, Thumb) - Encoding T1, T2 bool From johnny.chen at apple.com Tue Feb 22 19:55:07 2011 From: johnny.chen at apple.com (Johnny Chen) Date: Wed, 23 Feb 2011 01:55:07 -0000 Subject: [Lldb-commits] [lldb] r126293 - in /lldb/trunk/source/Plugins/Instruction/ARM: EmulateInstructionARM.cpp EmulateInstructionARM.h Message-ID: <20110223015507.E0BC12A6C12C@llvm.org> Author: johnny Date: Tue Feb 22 19:55:07 2011 New Revision: 126293 URL: http://llvm.org/viewvc/llvm-project?rev=126293&view=rev Log: Modify EmulateSUBSPImm() to handle the cases with generic Rd value instead of Rd == 13. Add opcode entries for the generic "sub (sp minus immediate)" operations. Modified: lldb/trunk/source/Plugins/Instruction/ARM/EmulateInstructionARM.cpp lldb/trunk/source/Plugins/Instruction/ARM/EmulateInstructionARM.h Modified: lldb/trunk/source/Plugins/Instruction/ARM/EmulateInstructionARM.cpp URL: http://llvm.org/viewvc/llvm-project/lldb/trunk/source/Plugins/Instruction/ARM/EmulateInstructionARM.cpp?rev=126293&r1=126292&r2=126293&view=diff ============================================================================== --- lldb/trunk/source/Plugins/Instruction/ARM/EmulateInstructionARM.cpp (original) +++ lldb/trunk/source/Plugins/Instruction/ARM/EmulateInstructionARM.cpp Tue Feb 22 19:55:07 2011 @@ -1407,7 +1407,10 @@ return true; } -// A sub operation to adjust the SP -- allocate space for local storage. +// This instruction subtracts an immediate value from the SP value, and writes +// the result to the destination register. +// +// If Rd == 13 => A sub operation to adjust the SP -- allocate space for local storage. bool EmulateInstructionARM::EmulateSUBSPImm (ARMEncoding encoding) { @@ -1439,31 +1442,53 @@ const addr_t sp = ReadCoreReg (SP_REG, &success); if (!success) return false; + + uint32_t Rd; + bool setflags; uint32_t imm32; switch (encoding) { case eEncodingT1: + Rd = 13; + setflags = false; imm32 = ThumbImmScaled(opcode); // imm32 = ZeroExtend(imm7:'00', 32) break; case eEncodingT2: + Rd = Bits32(opcode, 11, 8); + setflags = BitIsSet(opcode, 20); imm32 = ThumbExpandImm(opcode); // imm32 = ThumbExpandImm(i:imm3:imm8) + if (Rd == 15 && setflags) + return EmulateCMPImm(eEncodingT2); + if (Rd == 15 && !setflags) + return false; break; case eEncodingT3: + Rd = Bits32(opcode, 11, 8); + setflags = false; imm32 = ThumbImm12(opcode); // imm32 = ZeroExtend(i:imm3:imm8, 32) break; case eEncodingA1: + Rd = Bits32(opcode, 15, 12); + setflags = BitIsSet(opcode, 20); imm32 = ARMExpandImm(opcode); // imm32 = ARMExpandImm(imm12) break; default: return false; } - addr_t sp_offset = imm32; - addr_t addr = sp - sp_offset; // the adjusted stack pointer value - + AddWithCarryResult res = AddWithCarry(sp, ~imm32, 1); + EmulateInstruction::Context context; - context.type = EmulateInstruction::eContextAdjustStackPointer; - context.SetImmediateSigned (-sp_offset); - - if (!WriteRegisterUnsigned (context, eRegisterKindGeneric, LLDB_REGNUM_GENERIC_SP, addr)) + if (Rd == 13) + { + context.type = EmulateInstruction::eContextAdjustStackPointer; + context.SetImmediateSigned (-imm32); // the stack pointer offset + } + else + { + context.type = EmulateInstruction::eContextImmediate; + context.SetNoArgs (); + } + + if (!WriteCoreRegOptionalFlags(context, res.result, Rd, setflags, res.carry_out, res.overflow)) return false; } return true; @@ -6678,6 +6703,8 @@ { 0x0fe00000, 0x02c00000, ARMvAll, eEncodingA1, eSize32, &EmulateInstructionARM::EmulateSBCImm, "sbc{s} , , #"}, // sbc (register) { 0x0fe00010, 0x00c00000, ARMvAll, eEncodingA1, eSize32, &EmulateInstructionARM::EmulateSBCReg, "sbc{s} , , {,}"}, + // sub (sp minus immediate) + { 0x0fef0000, 0x024d0000, ARMvAll, eEncodingA1, eSize32, &EmulateInstructionARM::EmulateSUBSPImm, "sub{s} , sp, #"}, // teq (immediate) { 0x0ff0f000, 0x03300000, ARMvAll, eEncodingA1, eSize32, &EmulateInstructionARM::EmulateTEQImm, "teq , #const"}, // teq (register) @@ -6781,7 +6808,7 @@ // adjust the stack pointer { 0xffffff87, 0x00004485, ARMvAll, eEncodingT2, eSize16, &EmulateInstructionARM::EmulateADDSPRm, "add sp, "}, - { 0xffffff80, 0x0000b080, ARMvAll, eEncodingT1, eSize16, &EmulateInstructionARM::EmulateSUBSPImm, "add sp, sp, #imm"}, + { 0xffffff80, 0x0000b080, ARMvAll, eEncodingT1, eSize16, &EmulateInstructionARM::EmulateSUBSPImm, "sub sp, sp, #imm"}, { 0xfbef8f00, 0xf1ad0d00, ARMV6T2_ABOVE, eEncodingT2, eSize32, &EmulateInstructionARM::EmulateSUBSPImm, "sub.w sp, sp, #"}, { 0xfbff8f00, 0xf2ad0d00, ARMV6T2_ABOVE, eEncodingT3, eSize32, &EmulateInstructionARM::EmulateSUBSPImm, "subw sp, sp, #imm12"}, @@ -6869,6 +6896,9 @@ // sbc (register) { 0xffffffc0, 0x00004180, ARMvAll, eEncodingT1, eSize16, &EmulateInstructionARM::EmulateSBCReg, "sbcs|sbc , "}, { 0xffe08000, 0xeb600000, ARMV6T2_ABOVE, eEncodingT2, eSize32, &EmulateInstructionARM::EmulateSBCReg, "sbc{s}.w , , {,}"}, + // sub (sp minus immediate) + { 0xfbef8000, 0xf1ad0000, ARMV6T2_ABOVE, eEncodingT2, eSize32, &EmulateInstructionARM::EmulateSUBSPImm, "sub{s}.w , sp, #"}, + { 0xfbff8000, 0xf2ad0000, ARMV6T2_ABOVE, eEncodingT3, eSize32, &EmulateInstructionARM::EmulateSUBSPImm, "subw , sp, #imm12"}, // teq (immediate) { 0xfbf08f00, 0xf0900f00, ARMV6T2_ABOVE, eEncodingT1, eSize32, &EmulateInstructionARM::EmulateTEQImm, "teq , #"}, // teq (register) Modified: lldb/trunk/source/Plugins/Instruction/ARM/EmulateInstructionARM.h URL: http://llvm.org/viewvc/llvm-project/lldb/trunk/source/Plugins/Instruction/ARM/EmulateInstructionARM.h?rev=126293&r1=126292&r2=126293&view=diff ============================================================================== --- lldb/trunk/source/Plugins/Instruction/ARM/EmulateInstructionARM.h (original) +++ lldb/trunk/source/Plugins/Instruction/ARM/EmulateInstructionARM.h Tue Feb 22 19:55:07 2011 @@ -677,18 +677,14 @@ bool EmulateSBCReg (ARMEncoding encoding); - // A8.6.210 SUB (immediate, Thumb) - Encoding T1, T2 + // A8.6.211 SUB (immediate, Thumb) - Encoding T1, T2 bool EmulateSUBImmediateThumb (ARMEncoding encoding); - // A8.6.211 SUB (immediate, ARM) - Encoding A1 + // A8.6.212 SUB (immediate, ARM) - Encoding A1 bool EmulateSUBImmediateARM (ARMEncoding encoding); - // A8.6.214 SUB (SP minus immediate) - Encoding T1, A1 - bool - EmulateSUBSpImmediate (ARMEncoding encoding); - // A8.6.222 SXTB - Encoding T1 bool EmulateSXTB (ARMEncoding encoding); From wilsons at start.ca Wed Feb 23 15:16:18 2011 From: wilsons at start.ca (Stephen Wilson) Date: Wed, 23 Feb 2011 16:16:18 -0500 Subject: [Lldb-commits] [PATCH 0/4] Linux updates to support the new ArchSpec. Message-ID: <1298495782-17446-1-git-send-email-wilsons@start.ca> This patch series is fairly simple. It touches mostly linux specific code to support the new ArchSpec implementation. Patch 1 is the main item that needs review as it changes ArchSpec::SetTriple and may impact the Darwin builds. -- steve From wilsons at start.ca Wed Feb 23 15:16:19 2011 From: wilsons at start.ca (Stephen Wilson) Date: Wed, 23 Feb 2011 16:16:19 -0500 Subject: [Lldb-commits] [PATCH 1/4] ArchSpec: Do not set default to host settings when setting a triple. In-Reply-To: <1298495782-17446-1-git-send-email-wilsons@start.ca> References: <1298495782-17446-1-git-send-email-wilsons@start.ca> Message-ID: <1298495782-17446-2-git-send-email-wilsons@start.ca> The major issue this patch solves is that ArchSpec::SetTriple no longer depends on the implementation of Host::GetArchitecture. On linux, HostGetArchitecture calls ArchSpec::SetTriple, thus blowing the stack. A second smaller point is that SetTriple now does what its name suggests. Clients that need "default to the Host triple" semantics can implement such logic if needed. --- source/Core/ArchSpec.cpp | 9 --------- 1 files changed, 0 insertions(+), 9 deletions(-) diff --git a/source/Core/ArchSpec.cpp b/source/Core/ArchSpec.cpp index a5493b3..9592aa9 100644 --- a/source/Core/ArchSpec.cpp +++ b/source/Core/ArchSpec.cpp @@ -406,15 +406,6 @@ ArchSpec::SetTriple (const llvm::Triple &triple) { m_core = core_def->core; m_byte_order = core_def->default_byte_order; - - // If the vendor, OS or environment aren't specified, default to the system? - const ArchSpec &host_arch_ref = Host::GetArchitecture (Host::eSystemDefaultArchitecture); - if (m_triple.getVendor() == llvm::Triple::UnknownVendor) - m_triple.setVendor(host_arch_ref.GetTriple().getVendor()); - if (m_triple.getOS() == llvm::Triple::UnknownOS) - m_triple.setOS(host_arch_ref.GetTriple().getOS()); - if (m_triple.getEnvironment() == llvm::Triple::UnknownEnvironment) - m_triple.setEnvironment(host_arch_ref.GetTriple().getEnvironment()); } else { -- 1.7.3.5 From wilsons at start.ca Wed Feb 23 15:16:20 2011 From: wilsons at start.ca (Stephen Wilson) Date: Wed, 23 Feb 2011 16:16:20 -0500 Subject: [Lldb-commits] [PATCH 2/4] Host: linux: Use llvm::sys::getHostTriple for the default host ArchSpec. In-Reply-To: <1298495782-17446-1-git-send-email-wilsons@start.ca> References: <1298495782-17446-1-git-send-email-wilsons@start.ca> Message-ID: <1298495782-17446-3-git-send-email-wilsons@start.ca> Previously we were using a set of preprocessor defines and returning an ArchSpec without any OS/Vendor information. This fixes an issue with plugin resolution on Linux where a valid OS component is needed. --- source/Host/common/Host.cpp | 47 +++++++++++++++++++++---------------------- 1 files changed, 23 insertions(+), 24 deletions(-) diff --git a/source/Host/common/Host.cpp b/source/Host/common/Host.cpp index 98e5b95..1f48b20 100644 --- a/source/Host/common/Host.cpp +++ b/source/Host/common/Host.cpp @@ -18,6 +18,8 @@ #include "lldb/Host/Endian.h" #include "lldb/Host/Mutex.h" +#include "llvm/Support/Host.h" + #include #include @@ -288,34 +290,31 @@ Host::GetArchitecture (SystemDefaultArchitecture arch_kind) } #else // #if defined (__APPLE__) - + if (g_supports_32 == false && g_supports_64 == false) { -#if defined (__x86_64__) - - g_host_arch_64.SetTriple ("x86_64"); - -#elif defined (__i386__) - - g_host_arch_32.SetTriple ("i386"); - -#elif defined (__arm__) - - g_host_arch_32.SetTriple ("arm"); - -#elif defined (__ppc64__) + llvm::Triple triple(llvm::sys::getHostTriple()); - g_host_arch_64.SetTriple ("ppc64"); + g_host_arch_32.Clear(); + g_host_arch_64.Clear(); -#elif defined (__powerpc__) || defined (__ppc__) - - g_host_arch_32.SetTriple ("ppc"); - -#else - -#error undefined architecture, define your architecture here - -#endif + switch (triple.getArch()) + { + default: + g_host_arch_32.SetTriple(triple); + g_supports_32 = true; + break; + + case llvm::Triple::alpha: + case llvm::Triple::x86_64: + case llvm::Triple::sparcv9: + case llvm::Triple::ppc64: + case llvm::Triple::systemz: + case llvm::Triple::cellspu: + g_host_arch_64.SetTriple(triple); + g_supports_64 = true; + break; + } g_supports_32 = g_host_arch_32.IsValid(); g_supports_64 = g_host_arch_64.IsValid(); -- 1.7.3.5 From wilsons at start.ca Wed Feb 23 15:16:21 2011 From: wilsons at start.ca (Stephen Wilson) Date: Wed, 23 Feb 2011 16:16:21 -0500 Subject: [Lldb-commits] [PATCH 3/4] linux: Remove a local ObjectFileELF version of GetArchitecture. In-Reply-To: <1298495782-17446-1-git-send-email-wilsons@start.ca> References: <1298495782-17446-1-git-send-email-wilsons@start.ca> Message-ID: <1298495782-17446-4-git-send-email-wilsons@start.ca> Also fix a bug where we were not lazily parsing the ELF header and thus returning an ArchSpec with invalid cpu type components. Initialize the cpu subtype as LLDB_INVALID_CPUTYPE for compatibility with the new ArchSpec implementation. --- source/Plugins/ObjectFile/ELF/ObjectFileELF.cpp | 18 +++++++----------- source/Plugins/ObjectFile/ELF/ObjectFileELF.h | 3 --- 2 files changed, 7 insertions(+), 14 deletions(-) diff --git a/source/Plugins/ObjectFile/ELF/ObjectFileELF.cpp b/source/Plugins/ObjectFile/ELF/ObjectFileELF.cpp index 445518d..c381a3b 100644 --- a/source/Plugins/ObjectFile/ELF/ObjectFileELF.cpp +++ b/source/Plugins/ObjectFile/ELF/ObjectFileELF.cpp @@ -74,8 +74,9 @@ ObjectFileELF::CreateInstance(Module *module, { std::auto_ptr objfile_ap( new ObjectFileELF(module, data_sp, file, offset, length)); - ArchSpec spec = objfile_ap->GetArchitecture(); - if (spec.IsValid() && objfile_ap->SetModulesArchitecture(spec)) + ArchSpec spec; + if (objfile_ap->GetArchitecture(spec) && + objfile_ap->SetModulesArchitecture(spec)) return objfile_ap.release(); } } @@ -83,14 +84,6 @@ ObjectFileELF::CreateInstance(Module *module, return NULL; } -ArchSpec -ObjectFileELF::GetArchitecture() -{ - if (!ParseHeader()) - return ArchSpec(); - - return ArchSpec(eArchTypeELF, m_header.e_machine, m_header.e_flags); -} //------------------------------------------------------------------ // PluginInterface protocol @@ -1046,7 +1039,10 @@ ObjectFileELF::DumpDependentModules(lldb_private::Stream *s) bool ObjectFileELF::GetArchitecture (ArchSpec &arch) { - arch.SetArchitecture (lldb::eArchTypeELF, m_header.e_machine, m_header.e_flags); + if (!ParseHeader()) + return false; + + arch.SetArchitecture (lldb::eArchTypeELF, m_header.e_machine, LLDB_INVALID_CPUTYPE); arch.GetTriple().setOSName (Host::GetOSString().GetCString()); arch.GetTriple().setVendorName(Host::GetVendorString().GetCString()); return true; diff --git a/source/Plugins/ObjectFile/ELF/ObjectFileELF.h b/source/Plugins/ObjectFile/ELF/ObjectFileELF.h index ad97165..5de0a8a 100644 --- a/source/Plugins/ObjectFile/ELF/ObjectFileELF.h +++ b/source/Plugins/ObjectFile/ELF/ObjectFileELF.h @@ -116,9 +116,6 @@ public: virtual lldb_private::Address GetImageInfoAddress(); - lldb_private::ArchSpec - GetArchitecture(); - private: ObjectFileELF(lldb_private::Module* module, lldb::DataBufferSP& dataSP, -- 1.7.3.5 From wilsons at start.ca Wed Feb 23 15:16:22 2011 From: wilsons at start.ca (Stephen Wilson) Date: Wed, 23 Feb 2011 16:16:22 -0500 Subject: [Lldb-commits] [PATCH 4/4] linux: Use ArchSpec::GetCore and the ArchSpec::Core enums. In-Reply-To: <1298495782-17446-1-git-send-email-wilsons@start.ca> References: <1298495782-17446-1-git-send-email-wilsons@start.ca> Message-ID: <1298495782-17446-5-git-send-email-wilsons@start.ca> --- source/Plugins/Process/Linux/LinuxThread.cpp | 4 ++-- source/Plugins/Process/Linux/ProcessLinux.cpp | 6 +++--- 2 files changed, 5 insertions(+), 5 deletions(-) diff --git a/source/Plugins/Process/Linux/LinuxThread.cpp b/source/Plugins/Process/Linux/LinuxThread.cpp index 5c278d4..397d31b 100644 --- a/source/Plugins/Process/Linux/LinuxThread.cpp +++ b/source/Plugins/Process/Linux/LinuxThread.cpp @@ -65,13 +65,13 @@ LinuxThread::GetRegisterContext() { ArchSpec arch = process.GetTarget().GetArchitecture(); - switch (arch.GetGenericCPUType()) + switch (arch.GetCore()) { default: assert(false && "CPU type not supported!"); break; - case ArchSpec::eCPU_x86_64: + case ArchSpec::eCore_x86_64_x86_64: m_reg_context_sp.reset(new RegisterContextLinux_x86_64(*this, 0)); break; } diff --git a/source/Plugins/Process/Linux/ProcessLinux.cpp b/source/Plugins/Process/Linux/ProcessLinux.cpp index 9939fe7..f62a303 100644 --- a/source/Plugins/Process/Linux/ProcessLinux.cpp +++ b/source/Plugins/Process/Linux/ProcessLinux.cpp @@ -353,14 +353,14 @@ ProcessLinux::GetSoftwareBreakpointTrapOpcode(BreakpointSite* bp_site) const uint8_t *opcode = NULL; size_t opcode_size = 0; - switch (arch.GetGenericCPUType()) + switch (arch.GetCore()) { default: assert(false && "CPU type not supported!"); break; - case ArchSpec::eCPU_i386: - case ArchSpec::eCPU_x86_64: + case ArchSpec::eCore_x86_32_i386: + case ArchSpec::eCore_x86_64_x86_64: opcode = g_i386_opcode; opcode_size = sizeof(g_i386_opcode); break; -- 1.7.3.5 From johnny.chen at apple.com Wed Feb 23 15:24:25 2011 From: johnny.chen at apple.com (Johnny Chen) Date: Wed, 23 Feb 2011 21:24:25 -0000 Subject: [Lldb-commits] [lldb] r126335 - in /lldb/trunk/source/Plugins: Instruction/ARM/EmulateInstructionARM.cpp Instruction/ARM/EmulateInstructionARM.h Process/Utility/ARMUtils.h Message-ID: <20110223212425.EBE852A6C12C@llvm.org> Author: johnny Date: Wed Feb 23 15:24:25 2011 New Revision: 126335 URL: http://llvm.org/viewvc/llvm-project?rev=126335&view=rev Log: Add emulation for "ADR" operations. Add a ThumbImm8Scaled() convenience function and rename the original ThumbImmScaled() function to ThumbImm7Scaled(). Modified: lldb/trunk/source/Plugins/Instruction/ARM/EmulateInstructionARM.cpp lldb/trunk/source/Plugins/Instruction/ARM/EmulateInstructionARM.h lldb/trunk/source/Plugins/Process/Utility/ARMUtils.h Modified: lldb/trunk/source/Plugins/Instruction/ARM/EmulateInstructionARM.cpp URL: http://llvm.org/viewvc/llvm-project/lldb/trunk/source/Plugins/Instruction/ARM/EmulateInstructionARM.cpp?rev=126335&r1=126334&r2=126335&view=diff ============================================================================== --- lldb/trunk/source/Plugins/Instruction/ARM/EmulateInstructionARM.cpp (original) +++ lldb/trunk/source/Plugins/Instruction/ARM/EmulateInstructionARM.cpp Wed Feb 23 15:24:25 2011 @@ -1000,7 +1000,7 @@ uint32_t imm32; // the immediate operand switch (encoding) { case eEncodingT2: - imm32 = ThumbImmScaled(opcode); // imm32 = ZeroExtend(imm7:'00', 32) + imm32 = ThumbImm7Scaled(opcode); // imm32 = ZeroExtend(imm7:'00', 32) break; default: return false; @@ -1450,7 +1450,7 @@ case eEncodingT1: Rd = 13; setflags = false; - imm32 = ThumbImmScaled(opcode); // imm32 = ZeroExtend(imm7:'00', 32) + imm32 = ThumbImm7Scaled(opcode); // imm32 = ZeroExtend(imm7:'00', 32) break; case eEncodingT2: Rd = Bits32(opcode, 11, 8); @@ -4664,6 +4664,73 @@ return true; } +// This instruction adds an immediate value to the PC value to form a PC-relative address, +// and writes the result to the destination register. +bool +EmulateInstructionARM::EmulateADR (ARMEncoding encoding) +{ +#if 0 + // ARM pseudo code... + if ConditionPassed() then + EncodingSpecificOperations(); + result = if add then (Align(PC,4) + imm32) else (Align(PC,4) - imm32); + if d == 15 then // Can only occur for ARM encodings + ALUWritePC(result); + else + R[d] = result; +#endif + + bool success = false; + const uint32_t opcode = OpcodeAsUnsigned (&success); + if (!success) + return false; + + if (ConditionPassed()) + { + uint32_t Rd; + uint32_t imm32; // the immediate value to be added/subtracted to/from the PC + bool add; + switch (encoding) + { + case eEncodingT1: + Rd = Bits32(opcode, 10, 8); + imm32 = ThumbImm8Scaled(opcode); // imm32 = ZeroExtend(imm8:'00', 32) + break; + case eEncodingT2: + case eEncodingT3: + Rd = Bits32(opcode, 11, 8); + imm32 = ThumbImm12(opcode); // imm32 = ZeroExtend(i:imm3:imm8, 32) + add = (Bits32(opcode, 24, 21) == 0); // 0b0000 => ADD; 0b0101 => SUB + if (BadReg(Rd)) + return false; + break; + case eEncodingA1: + case eEncodingA2: + Rd = Bits32(opcode, 15, 12); + imm32 = ARMExpandImm(opcode); // imm32 = ARMExpandImm(imm12) + add = (Bits32(opcode, 24, 21) == 0x4); // 0b0100 => ADD; 0b0010 => SUB + break; + default: + return false; + } + + // Read the PC value. + uint32_t pc = ReadCoreReg(PC_REG, &success); + if (!success) + return false; + + uint32_t result = (add ? Align(pc, 4) + imm32 : Align(pc, 4) - imm32); + + EmulateInstruction::Context context; + context.type = EmulateInstruction::eContextImmediate; + context.SetNoArgs (); + + if (!WriteCoreReg(context, result, Rd)) + return false; + } + return true; +} + // This instruction performs a bitwise AND of a register value and an immediate value, and writes the result // to the destination register. It can optionally update the condition flags based on the result. bool @@ -6679,6 +6746,9 @@ { 0x0fe00000, 0x02800000, ARMvAll, eEncodingA1, eSize32, &EmulateInstructionARM::EmulateADDImmARM, "add{s} , , #const"}, // add (register) { 0x0fe00010, 0x00800000, ARMvAll, eEncodingA1, eSize32, &EmulateInstructionARM::EmulateADDReg, "add{s} , , {,}"}, + // adr + { 0x0fff0000, 0x028f0000, ARMvAll, eEncodingA1, eSize32, &EmulateInstructionARM::EmulateADR, "add , PC, #"}, + { 0x0fff0000, 0x024f0000, ARMvAll, eEncodingA2, eSize32, &EmulateInstructionARM::EmulateADR, "sub , PC, #"}, // and (immediate) { 0x0fe00000, 0x02000000, ARMvAll, eEncodingA1, eSize32, &EmulateInstructionARM::EmulateANDImm, "and{s} , , #const"}, // and (register) @@ -6871,6 +6941,10 @@ { 0xfffffe00, 0x00001800, ARMvAll, eEncodingT1, eSize16, &EmulateInstructionARM::EmulateADDReg, "adds|add , , "}, // Make sure "add sp, " comes before this instruction, so there's no ambiguity decoding the two. { 0xffffff00, 0x00004400, ARMvAll, eEncodingT2, eSize16, &EmulateInstructionARM::EmulateADDReg, "add , "}, + // adr + { 0xfffff800, 0x0000a000, ARMvAll, eEncodingT1, eSize16, &EmulateInstructionARM::EmulateADR, "add , PC, #"}, + { 0xfbff8000, 0xf2af0000, ARMV6T2_ABOVE, eEncodingT2, eSize32, &EmulateInstructionARM::EmulateADR, "sub , PC, #"}, + { 0xfbff8000, 0xf20f0000, ARMV6T2_ABOVE, eEncodingT3, eSize32, &EmulateInstructionARM::EmulateADR, "add , PC, #"}, // and (immediate) { 0xfbe08000, 0xf0000000, ARMV6T2_ABOVE, eEncodingT1, eSize32, &EmulateInstructionARM::EmulateANDImm, "and{s} , , #"}, // and (register) @@ -7397,7 +7471,22 @@ } else { - if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_r0 + Rd, result)) + uint32_t reg_kind, reg_num; + switch (Rd) + { + case SP_REG: + reg_kind = eRegisterKindGeneric; + reg_num = LLDB_REGNUM_GENERIC_SP; + break; + case LR_REG: + reg_kind = eRegisterKindGeneric; + reg_num = LLDB_REGNUM_GENERIC_RA; + break; + default: + reg_kind = eRegisterKindDWARF; + reg_num = dwarf_r0 + Rd; + } + if (!WriteRegisterUnsigned (context, reg_kind, reg_num, result)) return false; if (setflags) return WriteFlags (context, result, carry, overflow); Modified: lldb/trunk/source/Plugins/Instruction/ARM/EmulateInstructionARM.h URL: http://llvm.org/viewvc/llvm-project/lldb/trunk/source/Plugins/Instruction/ARM/EmulateInstructionARM.h?rev=126335&r1=126334&r2=126335&view=diff ============================================================================== --- lldb/trunk/source/Plugins/Instruction/ARM/EmulateInstructionARM.h (original) +++ lldb/trunk/source/Plugins/Instruction/ARM/EmulateInstructionARM.h Wed Feb 23 15:24:25 2011 @@ -207,6 +207,15 @@ const uint32_t carry = ~0u, const uint32_t overflow = ~0u); + bool + WriteCoreReg (Context &context, + const uint32_t result, + const uint32_t Rd) + { + // Don't set the flags. + return WriteCoreRegOptionalFlags(context, result, Rd, false); + } + // See A8.6.35 CMP (immediate) Operation. // Default arguments are specified for carry and overflow parameters, which means // not to update the respective flags. @@ -679,11 +688,11 @@ // A8.6.211 SUB (immediate, Thumb) - Encoding T1, T2 bool - EmulateSUBImmediateThumb (ARMEncoding encoding); + EmulateSUBImmThumb (ARMEncoding encoding); // A8.6.212 SUB (immediate, ARM) - Encoding A1 bool - EmulateSUBImmediateARM (ARMEncoding encoding); + EmulateSUBImmARM (ARMEncoding encoding); // A8.6.222 SXTB - Encoding T1 bool Modified: lldb/trunk/source/Plugins/Process/Utility/ARMUtils.h URL: http://llvm.org/viewvc/llvm-project/lldb/trunk/source/Plugins/Process/Utility/ARMUtils.h?rev=126335&r1=126334&r2=126335&view=diff ============================================================================== --- lldb/trunk/source/Plugins/Process/Utility/ARMUtils.h (original) +++ lldb/trunk/source/Plugins/Process/Utility/ARMUtils.h Wed Feb 23 15:24:25 2011 @@ -314,12 +314,19 @@ } // imm32 = ZeroExtend(imm7:'00', 32) -static inline uint32_t ThumbImmScaled(uint32_t opcode) +static inline uint32_t ThumbImm7Scaled(uint32_t opcode) { const uint32_t imm7 = bits(opcode, 6, 0); return imm7 * 4; } +// imm32 = ZeroExtend(imm8:'00', 32) +static inline uint32_t ThumbImm8Scaled(uint32_t opcode) +{ + const uint32_t imm8 = bits(opcode, 7, 0); + return imm8 * 4; +} + // This function performs the check for the register numbers 13 and 15 that are // not permitted for many Thumb register specifiers. static inline bool BadReg(uint32_t n) { return n == 13 || n == 15; } From johnny.chen at apple.com Wed Feb 23 17:47:56 2011 From: johnny.chen at apple.com (Johnny Chen) Date: Wed, 23 Feb 2011 23:47:56 -0000 Subject: [Lldb-commits] [lldb] r126343 - in /lldb/trunk/source/Plugins/Instruction/ARM: EmulateInstructionARM.cpp EmulateInstructionARM.h Message-ID: <20110223234756.BF7AE2A6C12C@llvm.org> Author: johnny Date: Wed Feb 23 17:47:56 2011 New Revision: 126343 URL: http://llvm.org/viewvc/llvm-project?rev=126343&view=rev Log: Add emulation methods for "SUB (immediate, Thumb)" and "SUB (immediate, ARM)" operations. Modified: lldb/trunk/source/Plugins/Instruction/ARM/EmulateInstructionARM.cpp lldb/trunk/source/Plugins/Instruction/ARM/EmulateInstructionARM.h Modified: lldb/trunk/source/Plugins/Instruction/ARM/EmulateInstructionARM.cpp URL: http://llvm.org/viewvc/llvm-project/lldb/trunk/source/Plugins/Instruction/ARM/EmulateInstructionARM.cpp?rev=126343&r1=126342&r2=126343&view=diff ============================================================================== --- lldb/trunk/source/Plugins/Instruction/ARM/EmulateInstructionARM.cpp (original) +++ lldb/trunk/source/Plugins/Instruction/ARM/EmulateInstructionARM.cpp Wed Feb 23 17:47:56 2011 @@ -1420,7 +1420,7 @@ { EncodingSpecificOperations(); (result, carry, overflow) = AddWithCarry(SP, NOT(imm32), ???1???); - if d == 15 then // Can only occur for ARM encoding + if d == 15 then // Can only occur for ARM encoding ALUWritePC(result); // setflags is always FALSE here else R[d] = result; @@ -1465,11 +1465,17 @@ Rd = Bits32(opcode, 11, 8); setflags = false; imm32 = ThumbImm12(opcode); // imm32 = ZeroExtend(i:imm3:imm8, 32) + if (Rd == 15) + return false; break; case eEncodingA1: Rd = Bits32(opcode, 15, 12); setflags = BitIsSet(opcode, 20); imm32 = ARMExpandImm(opcode); // imm32 = ARMExpandImm(imm12) + // if Rd == '1111' && S == '1' then SEE SUBS PC, LR and related instructions; + // TODO: Emulate SUBS PC, LR and related instructions. + if (Rd == 15 && setflags) + return false; break; default: return false; @@ -6267,7 +6273,7 @@ // ARM pseudo code... if ConditionPassed() then EncodingSpecificOperations(); - (result, carry, overflow) = AddWithCarry(R[n], NOT(imm32), APSR.C); + (result, carry, overflow) = AddWithCarry(R[n], NOT(imm32), APSR.C); if d == 15 then // Can only occur for ARM encoding ALUWritePC(result); // setflags is always FALSE here else @@ -6414,6 +6420,170 @@ return true; } +// This instruction subtracts an immediate value from a register value, and writes the result +// to the destination register. It can optionally update the condition flags based on the result. +bool +EmulateInstructionARM::EmulateSUBImmThumb (ARMEncoding encoding) +{ +#if 0 + // ARM pseudo code... + if ConditionPassed() then + EncodingSpecificOperations(); + (result, carry, overflow) = AddWithCarry(R[n], NOT(imm32), '1'); + R[d] = result; + if setflags then + APSR.N = result<31>; + APSR.Z = IsZeroBit(result); + APSR.C = carry; + APSR.V = overflow; +#endif + + bool success = false; + const uint32_t opcode = OpcodeAsUnsigned (&success); + if (!success) + return false; + + uint32_t Rd; // the destination register + uint32_t Rn; // the first operand + bool setflags; + uint32_t imm32; // the immediate value to be subtracted from the value obtained from Rn + switch (encoding) { + case eEncodingT1: + Rd = Bits32(opcode, 2, 0); + Rn = Bits32(opcode, 5, 3); + setflags = !InITBlock(); + imm32 = Bits32(opcode, 8, 6); // imm32 = ZeroExtend(imm3, 32) + break; + case eEncodingT2: + Rd = Rn = Bits32(opcode, 10, 8); + setflags = !InITBlock(); + imm32 = Bits32(opcode, 7, 0); // imm32 = ZeroExtend(imm8, 32) + break; + case eEncodingT3: + Rd = Bits32(opcode, 11, 8); + Rn = Bits32(opcode, 19, 16); + setflags = BitIsSet(opcode, 20); + imm32 = ThumbExpandImm(opcode); // imm32 = ThumbExpandImm(i:imm3:imm8) + + // if Rd == '1111' && S == '1' then SEE CMP (immediate); + if (Rd == 15 && setflags) + return EmulateCMPImm(eEncodingT2); + + // if Rn == ???1101??? then SEE SUB (SP minus immediate); + if (Rn == 13) + return EmulateSUBSPImm(eEncodingT2); + + // if d == 13 || (d == 15 && S == '0') || n == 15 then UNPREDICTABLE; + if (Rd == 13 || (Rd == 15 && !setflags) || Rn == 15) + return false; + break; + case eEncodingT4: + Rd = Bits32(opcode, 11, 8); + Rn = Bits32(opcode, 19, 16); + setflags = BitIsSet(opcode, 20); + imm32 = ThumbImm12(opcode); // imm32 = ZeroExtend(i:imm3:imm8, 32) + + // if Rn == '1111' then SEE ADR; + if (Rn == 15) + return EmulateADR(eEncodingT2); + + // if Rn == '1101' then SEE SUB (SP minus immediate); + if (Rn == 13) + return EmulateSUBSPImm(eEncodingT3); + + if (BadReg(Rd)) + return false; + break; + default: + return false; + } + // Read the register value from the operand register Rn. + uint32_t reg_val = ReadCoreReg(Rn, &success); + if (!success) + return false; + + AddWithCarryResult res = AddWithCarry(reg_val, ~imm32, 1); + + EmulateInstruction::Context context; + context.type = EmulateInstruction::eContextImmediate; + context.SetNoArgs (); + + if (!WriteCoreRegOptionalFlags(context, res.result, Rd, setflags, res.carry_out, res.overflow)) + return false; + + return true; +} + +// This instruction subtracts an immediate value from a register value, and writes the result +// to the destination register. It can optionally update the condition flags based on the result. +bool +EmulateInstructionARM::EmulateSUBImmARM (ARMEncoding encoding) +{ +#if 0 + // ARM pseudo code... + if ConditionPassed() then + EncodingSpecificOperations(); + (result, carry, overflow) = AddWithCarry(R[n], NOT(imm32), '1'); + if d == 15 then + ALUWritePC(result); // setflags is always FALSE here + else + R[d] = result; + if setflags then + APSR.N = result<31>; + APSR.Z = IsZeroBit(result); + APSR.C = carry; + APSR.V = overflow; +#endif + + bool success = false; + const uint32_t opcode = OpcodeAsUnsigned (&success); + if (!success) + return false; + + uint32_t Rd; // the destination register + uint32_t Rn; // the first operand + bool setflags; + uint32_t imm32; // the immediate value to be subtracted from the value obtained from Rn + switch (encoding) { + case eEncodingA1: + Rd = Bits32(opcode, 15, 12); + Rn = Bits32(opcode, 19, 16); + setflags = BitIsSet(opcode, 20); + imm32 = ARMExpandImm(opcode); // imm32 = ARMExpandImm(imm12) + + // if Rn == ???1111??? && S == ???0??? then SEE ADR; + if (Rn == 15 && !setflags) + return EmulateADR(eEncodingA2); + + // if Rn == ???1101??? then SEE SUB (SP minus immediate); + if (Rn == 13) + return EmulateSUBSPImm(eEncodingA1); + + // if Rd == '1111' && S == '1' then SEE SUBS PC, LR and related instructions; + // TODO: Emulate SUBS PC, LR and related instructions. + if (Rd == 15 && setflags) + return false; + break; + default: + return false; + } + // Read the register value from the operand register Rn. + uint32_t reg_val = ReadCoreReg(Rn, &success); + if (!success) + return false; + + AddWithCarryResult res = AddWithCarry(reg_val, ~imm32, 1); + + EmulateInstruction::Context context; + context.type = EmulateInstruction::eContextImmediate; + context.SetNoArgs (); + + if (!WriteCoreRegOptionalFlags(context, res.result, Rd, setflags, res.carry_out, res.overflow)) + return false; + + return true; +} + // Test Equivalence (immediate) performs a bitwise exclusive OR operation on a register value and an // immediate value. It updates the condition flags based on the result, and discards the result. bool @@ -6773,6 +6943,8 @@ { 0x0fe00000, 0x02c00000, ARMvAll, eEncodingA1, eSize32, &EmulateInstructionARM::EmulateSBCImm, "sbc{s} , , #"}, // sbc (register) { 0x0fe00010, 0x00c00000, ARMvAll, eEncodingA1, eSize32, &EmulateInstructionARM::EmulateSBCReg, "sbc{s} , , {,}"}, + // sub (immediate, ARM) + { 0x0fe00000, 0x02400000, ARMvAll, eEncodingA1, eSize32, &EmulateInstructionARM::EmulateSUBImmARM, "sub{s} , , #"}, // sub (sp minus immediate) { 0x0fef0000, 0x024d0000, ARMvAll, eEncodingA1, eSize32, &EmulateInstructionARM::EmulateSUBSPImm, "sub{s} , sp, #"}, // teq (immediate) @@ -6970,6 +7142,11 @@ // sbc (register) { 0xffffffc0, 0x00004180, ARMvAll, eEncodingT1, eSize16, &EmulateInstructionARM::EmulateSBCReg, "sbcs|sbc , "}, { 0xffe08000, 0xeb600000, ARMV6T2_ABOVE, eEncodingT2, eSize32, &EmulateInstructionARM::EmulateSBCReg, "sbc{s}.w , , {,}"}, + // sub (immediate, Thumb) + { 0xfffffe00, 0x00001e00, ARMvAll, eEncodingT1, eSize16, &EmulateInstructionARM::EmulateSUBImmThumb, "subs|sub , #imm3"}, + { 0xfffff800, 0x00003800, ARMvAll, eEncodingT2, eSize16, &EmulateInstructionARM::EmulateSUBImmThumb, "subs|sub , #imm8"}, + { 0xfbe08000, 0xf1a00000, ARMV6T2_ABOVE, eEncodingT3, eSize32, &EmulateInstructionARM::EmulateSUBImmThumb, "sub{s}.w , , #"}, + { 0xfbf08000, 0xf2a00000, ARMV6T2_ABOVE, eEncodingT4, eSize32, &EmulateInstructionARM::EmulateSUBImmThumb, "subw , , #imm12"}, // sub (sp minus immediate) { 0xfbef8000, 0xf1ad0000, ARMV6T2_ABOVE, eEncodingT2, eSize32, &EmulateInstructionARM::EmulateSUBSPImm, "sub{s}.w , sp, #"}, { 0xfbff8000, 0xf2ad0000, ARMV6T2_ABOVE, eEncodingT3, eSize32, &EmulateInstructionARM::EmulateSUBSPImm, "subw , sp, #imm12"}, Modified: lldb/trunk/source/Plugins/Instruction/ARM/EmulateInstructionARM.h URL: http://llvm.org/viewvc/llvm-project/lldb/trunk/source/Plugins/Instruction/ARM/EmulateInstructionARM.h?rev=126343&r1=126342&r2=126343&view=diff ============================================================================== --- lldb/trunk/source/Plugins/Instruction/ARM/EmulateInstructionARM.h (original) +++ lldb/trunk/source/Plugins/Instruction/ARM/EmulateInstructionARM.h Wed Feb 23 17:47:56 2011 @@ -686,11 +686,11 @@ bool EmulateSBCReg (ARMEncoding encoding); - // A8.6.211 SUB (immediate, Thumb) - Encoding T1, T2 + // A8.6.211 SUB (immediate, Thumb) bool EmulateSUBImmThumb (ARMEncoding encoding); - // A8.6.212 SUB (immediate, ARM) - Encoding A1 + // A8.6.212 SUB (immediate, ARM) bool EmulateSUBImmARM (ARMEncoding encoding); From gclayton at apple.com Wed Feb 23 17:55:33 2011 From: gclayton at apple.com (Greg Clayton) Date: Wed, 23 Feb 2011 15:55:33 -0800 Subject: [Lldb-commits] [PATCH 1/4] ArchSpec: Do not set default to host settings when setting a triple. In-Reply-To: <1298495782-17446-2-git-send-email-wilsons@start.ca> References: <1298495782-17446-1-git-send-email-wilsons@start.ca> <1298495782-17446-2-git-send-email-wilsons@start.ca> Message-ID: <44EC619F-DD25-443D-AF34-AA9CF0551D63@apple.com> I still think we need to make the m_triple have the host's vendor and host's OS. Can we modify this patch to use the string versions from host? Something like: if (m_triple.getVendor() == llvm::Triple::UnknownVendor) m_triple.setVendor(llvm::StringRef (Host::GetVendorString().GetCString())); if (m_triple.getOS() == llvm::Triple::UnknownOS) m_triple.setOS(llvm::StringRef (Host::GetOSString().GetCString())); On Feb 23, 2011, at 1:16 PM, Stephen Wilson wrote: > The major issue this patch solves is that ArchSpec::SetTriple no longer depends > on the implementation of Host::GetArchitecture. On linux, HostGetArchitecture > calls ArchSpec::SetTriple, thus blowing the stack. > > A second smaller point is that SetTriple now does what its name suggests. > Clients that need "default to the Host triple" semantics can implement such > logic if needed. > --- > source/Core/ArchSpec.cpp | 9 --------- > 1 files changed, 0 insertions(+), 9 deletions(-) > > diff --git a/source/Core/ArchSpec.cpp b/source/Core/ArchSpec.cpp > index a5493b3..9592aa9 100644 > --- a/source/Core/ArchSpec.cpp > +++ b/source/Core/ArchSpec.cpp > @@ -406,15 +406,6 @@ ArchSpec::SetTriple (const llvm::Triple &triple) > { > m_core = core_def->core; > m_byte_order = core_def->default_byte_order; > - > - // If the vendor, OS or environment aren't specified, default to the system? > - const ArchSpec &host_arch_ref = Host::GetArchitecture (Host::eSystemDefaultArchitecture); > - if (m_triple.getVendor() == llvm::Triple::UnknownVendor) > - m_triple.setVendor(host_arch_ref.GetTriple().getVendor()); > - if (m_triple.getOS() == llvm::Triple::UnknownOS) > - m_triple.setOS(host_arch_ref.GetTriple().getOS()); > - if (m_triple.getEnvironment() == llvm::Triple::UnknownEnvironment) > - m_triple.setEnvironment(host_arch_ref.GetTriple().getEnvironment()); > } > else > { > -- > 1.7.3.5 > > _______________________________________________ > lldb-commits mailing list > lldb-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/lldb-commits From gclayton at apple.com Wed Feb 23 17:57:09 2011 From: gclayton at apple.com (Greg Clayton) Date: Wed, 23 Feb 2011 15:57:09 -0800 Subject: [Lldb-commits] [PATCH 2/4] Host: linux: Use llvm::sys::getHostTriple for the default host ArchSpec. In-Reply-To: <1298495782-17446-3-git-send-email-wilsons@start.ca> References: <1298495782-17446-1-git-send-email-wilsons@start.ca> <1298495782-17446-3-git-send-email-wilsons@start.ca> Message-ID: <217928C1-CB9C-4330-885B-F18477576E85@apple.com> Looks good. On Feb 23, 2011, at 1:16 PM, Stephen Wilson wrote: > Previously we were using a set of preprocessor defines and returning an ArchSpec > without any OS/Vendor information. This fixes an issue with plugin resolution > on Linux where a valid OS component is needed. > --- > source/Host/common/Host.cpp | 47 +++++++++++++++++++++---------------------- > 1 files changed, 23 insertions(+), 24 deletions(-) > > diff --git a/source/Host/common/Host.cpp b/source/Host/common/Host.cpp > index 98e5b95..1f48b20 100644 > --- a/source/Host/common/Host.cpp > +++ b/source/Host/common/Host.cpp > @@ -18,6 +18,8 @@ > #include "lldb/Host/Endian.h" > #include "lldb/Host/Mutex.h" > > +#include "llvm/Support/Host.h" > + > #include > #include > > @@ -288,34 +290,31 @@ Host::GetArchitecture (SystemDefaultArchitecture arch_kind) > } > > #else // #if defined (__APPLE__) > - > + > if (g_supports_32 == false && g_supports_64 == false) > { > -#if defined (__x86_64__) > - > - g_host_arch_64.SetTriple ("x86_64"); > - > -#elif defined (__i386__) > - > - g_host_arch_32.SetTriple ("i386"); > - > -#elif defined (__arm__) > - > - g_host_arch_32.SetTriple ("arm"); > - > -#elif defined (__ppc64__) > + llvm::Triple triple(llvm::sys::getHostTriple()); > > - g_host_arch_64.SetTriple ("ppc64"); > + g_host_arch_32.Clear(); > + g_host_arch_64.Clear(); > > -#elif defined (__powerpc__) || defined (__ppc__) > - > - g_host_arch_32.SetTriple ("ppc"); > - > -#else > - > -#error undefined architecture, define your architecture here > - > -#endif > + switch (triple.getArch()) > + { > + default: > + g_host_arch_32.SetTriple(triple); > + g_supports_32 = true; > + break; > + > + case llvm::Triple::alpha: > + case llvm::Triple::x86_64: > + case llvm::Triple::sparcv9: > + case llvm::Triple::ppc64: > + case llvm::Triple::systemz: > + case llvm::Triple::cellspu: > + g_host_arch_64.SetTriple(triple); > + g_supports_64 = true; > + break; > + } > > g_supports_32 = g_host_arch_32.IsValid(); > g_supports_64 = g_host_arch_64.IsValid(); > -- > 1.7.3.5 > > _______________________________________________ > lldb-commits mailing list > lldb-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/lldb-commits From gclayton at apple.com Wed Feb 23 17:58:20 2011 From: gclayton at apple.com (Greg Clayton) Date: Wed, 23 Feb 2011 15:58:20 -0800 Subject: [Lldb-commits] [PATCH 3/4] linux: Remove a local ObjectFileELF version of GetArchitecture. In-Reply-To: <1298495782-17446-4-git-send-email-wilsons@start.ca> References: <1298495782-17446-1-git-send-email-wilsons@start.ca> <1298495782-17446-4-git-send-email-wilsons@start.ca> Message-ID: <075B2D2B-D6F2-44CF-9ADF-3DB9C8191449@apple.com> Looks good. On Feb 23, 2011, at 1:16 PM, Stephen Wilson wrote: > Also fix a bug where we were not lazily parsing the ELF header and thus > returning an ArchSpec with invalid cpu type components. Initialize the cpu > subtype as LLDB_INVALID_CPUTYPE for compatibility with the new ArchSpec > implementation. > --- > source/Plugins/ObjectFile/ELF/ObjectFileELF.cpp | 18 +++++++----------- > source/Plugins/ObjectFile/ELF/ObjectFileELF.h | 3 --- > 2 files changed, 7 insertions(+), 14 deletions(-) > > diff --git a/source/Plugins/ObjectFile/ELF/ObjectFileELF.cpp b/source/Plugins/ObjectFile/ELF/ObjectFileELF.cpp > index 445518d..c381a3b 100644 > --- a/source/Plugins/ObjectFile/ELF/ObjectFileELF.cpp > +++ b/source/Plugins/ObjectFile/ELF/ObjectFileELF.cpp > @@ -74,8 +74,9 @@ ObjectFileELF::CreateInstance(Module *module, > { > std::auto_ptr objfile_ap( > new ObjectFileELF(module, data_sp, file, offset, length)); > - ArchSpec spec = objfile_ap->GetArchitecture(); > - if (spec.IsValid() && objfile_ap->SetModulesArchitecture(spec)) > + ArchSpec spec; > + if (objfile_ap->GetArchitecture(spec) && > + objfile_ap->SetModulesArchitecture(spec)) > return objfile_ap.release(); > } > } > @@ -83,14 +84,6 @@ ObjectFileELF::CreateInstance(Module *module, > return NULL; > } > > -ArchSpec > -ObjectFileELF::GetArchitecture() > -{ > - if (!ParseHeader()) > - return ArchSpec(); > - > - return ArchSpec(eArchTypeELF, m_header.e_machine, m_header.e_flags); > -} > > //------------------------------------------------------------------ > // PluginInterface protocol > @@ -1046,7 +1039,10 @@ ObjectFileELF::DumpDependentModules(lldb_private::Stream *s) > bool > ObjectFileELF::GetArchitecture (ArchSpec &arch) > { > - arch.SetArchitecture (lldb::eArchTypeELF, m_header.e_machine, m_header.e_flags); > + if (!ParseHeader()) > + return false; > + > + arch.SetArchitecture (lldb::eArchTypeELF, m_header.e_machine, LLDB_INVALID_CPUTYPE); > arch.GetTriple().setOSName (Host::GetOSString().GetCString()); > arch.GetTriple().setVendorName(Host::GetVendorString().GetCString()); > return true; > diff --git a/source/Plugins/ObjectFile/ELF/ObjectFileELF.h b/source/Plugins/ObjectFile/ELF/ObjectFileELF.h > index ad97165..5de0a8a 100644 > --- a/source/Plugins/ObjectFile/ELF/ObjectFileELF.h > +++ b/source/Plugins/ObjectFile/ELF/ObjectFileELF.h > @@ -116,9 +116,6 @@ public: > virtual lldb_private::Address > GetImageInfoAddress(); > > - lldb_private::ArchSpec > - GetArchitecture(); > - > private: > ObjectFileELF(lldb_private::Module* module, > lldb::DataBufferSP& dataSP, > -- > 1.7.3.5 > > _______________________________________________ > lldb-commits mailing list > lldb-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/lldb-commits From gclayton at apple.com Wed Feb 23 17:58:30 2011 From: gclayton at apple.com (Greg Clayton) Date: Wed, 23 Feb 2011 15:58:30 -0800 Subject: [Lldb-commits] [PATCH 4/4] linux: Use ArchSpec::GetCore and the ArchSpec::Core enums. In-Reply-To: <1298495782-17446-5-git-send-email-wilsons@start.ca> References: <1298495782-17446-1-git-send-email-wilsons@start.ca> <1298495782-17446-5-git-send-email-wilsons@start.ca> Message-ID: <104268BB-AA88-46B0-BA36-B0935A8D343E@apple.com> Looks good. On Feb 23, 2011, at 1:16 PM, Stephen Wilson wrote: > --- > source/Plugins/Process/Linux/LinuxThread.cpp | 4 ++-- > source/Plugins/Process/Linux/ProcessLinux.cpp | 6 +++--- > 2 files changed, 5 insertions(+), 5 deletions(-) > > diff --git a/source/Plugins/Process/Linux/LinuxThread.cpp b/source/Plugins/Process/Linux/LinuxThread.cpp > index 5c278d4..397d31b 100644 > --- a/source/Plugins/Process/Linux/LinuxThread.cpp > +++ b/source/Plugins/Process/Linux/LinuxThread.cpp > @@ -65,13 +65,13 @@ LinuxThread::GetRegisterContext() > { > ArchSpec arch = process.GetTarget().GetArchitecture(); > > - switch (arch.GetGenericCPUType()) > + switch (arch.GetCore()) > { > default: > assert(false && "CPU type not supported!"); > break; > > - case ArchSpec::eCPU_x86_64: > + case ArchSpec::eCore_x86_64_x86_64: > m_reg_context_sp.reset(new RegisterContextLinux_x86_64(*this, 0)); > break; > } > diff --git a/source/Plugins/Process/Linux/ProcessLinux.cpp b/source/Plugins/Process/Linux/ProcessLinux.cpp > index 9939fe7..f62a303 100644 > --- a/source/Plugins/Process/Linux/ProcessLinux.cpp > +++ b/source/Plugins/Process/Linux/ProcessLinux.cpp > @@ -353,14 +353,14 @@ ProcessLinux::GetSoftwareBreakpointTrapOpcode(BreakpointSite* bp_site) > const uint8_t *opcode = NULL; > size_t opcode_size = 0; > > - switch (arch.GetGenericCPUType()) > + switch (arch.GetCore()) > { > default: > assert(false && "CPU type not supported!"); > break; > > - case ArchSpec::eCPU_i386: > - case ArchSpec::eCPU_x86_64: > + case ArchSpec::eCore_x86_32_i386: > + case ArchSpec::eCore_x86_64_x86_64: > opcode = g_i386_opcode; > opcode_size = sizeof(g_i386_opcode); > break; > -- > 1.7.3.5 > > _______________________________________________ > lldb-commits mailing list > lldb-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/lldb-commits From gclayton at apple.com Wed Feb 23 17:59:37 2011 From: gclayton at apple.com (Greg Clayton) Date: Wed, 23 Feb 2011 15:59:37 -0800 Subject: [Lldb-commits] [PATCH 1/4] ArchSpec: Do not set default to host settings when setting a triple. In-Reply-To: <44EC619F-DD25-443D-AF34-AA9CF0551D63@apple.com> References: <1298495782-17446-1-git-send-email-wilsons@start.ca> <1298495782-17446-2-git-send-email-wilsons@start.ca> <44EC619F-DD25-443D-AF34-AA9CF0551D63@apple.com> Message-ID: <4C2C3942-D5E1-4BC7-A504-EDEBB411EB83@apple.com> Or use the llvm::sys::getHostTriple() like you did in path 2/4... On Feb 23, 2011, at 3:55 PM, Greg Clayton wrote: > I still think we need to make the m_triple have the host's vendor and host's OS. > > Can we modify this patch to use the string versions from host? Something like: > > if (m_triple.getVendor() == llvm::Triple::UnknownVendor) > m_triple.setVendor(llvm::StringRef (Host::GetVendorString().GetCString())); > if (m_triple.getOS() == llvm::Triple::UnknownOS) > m_triple.setOS(llvm::StringRef (Host::GetOSString().GetCString())); > > > On Feb 23, 2011, at 1:16 PM, Stephen Wilson wrote: > >> The major issue this patch solves is that ArchSpec::SetTriple no longer depends >> on the implementation of Host::GetArchitecture. On linux, HostGetArchitecture >> calls ArchSpec::SetTriple, thus blowing the stack. >> >> A second smaller point is that SetTriple now does what its name suggests. >> Clients that need "default to the Host triple" semantics can implement such >> logic if needed. >> --- >> source/Core/ArchSpec.cpp | 9 --------- >> 1 files changed, 0 insertions(+), 9 deletions(-) >> >> diff --git a/source/Core/ArchSpec.cpp b/source/Core/ArchSpec.cpp >> index a5493b3..9592aa9 100644 >> --- a/source/Core/ArchSpec.cpp >> +++ b/source/Core/ArchSpec.cpp >> @@ -406,15 +406,6 @@ ArchSpec::SetTriple (const llvm::Triple &triple) >> { >> m_core = core_def->core; >> m_byte_order = core_def->default_byte_order; >> - >> - // If the vendor, OS or environment aren't specified, default to the system? >> - const ArchSpec &host_arch_ref = Host::GetArchitecture (Host::eSystemDefaultArchitecture); >> - if (m_triple.getVendor() == llvm::Triple::UnknownVendor) >> - m_triple.setVendor(host_arch_ref.GetTriple().getVendor()); >> - if (m_triple.getOS() == llvm::Triple::UnknownOS) >> - m_triple.setOS(host_arch_ref.GetTriple().getOS()); >> - if (m_triple.getEnvironment() == llvm::Triple::UnknownEnvironment) >> - m_triple.setEnvironment(host_arch_ref.GetTriple().getEnvironment()); >> } >> else >> { >> -- >> 1.7.3.5 >> >> _______________________________________________ >> lldb-commits mailing list >> lldb-commits at cs.uiuc.edu >> http://lists.cs.uiuc.edu/mailman/listinfo/lldb-commits > > > _______________________________________________ > lldb-commits mailing list > lldb-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/lldb-commits From wilsons at start.ca Wed Feb 23 18:48:19 2011 From: wilsons at start.ca (Stephen Wilson) Date: Wed, 23 Feb 2011 19:48:19 -0500 Subject: [Lldb-commits] [PATCH 1/4] ArchSpec: Do not set default to host settings when setting a triple. In-Reply-To: <4C2C3942-D5E1-4BC7-A504-EDEBB411EB83@apple.com> References: <1298495782-17446-1-git-send-email-wilsons@start.ca> <1298495782-17446-2-git-send-email-wilsons@start.ca> <44EC619F-DD25-443D-AF34-AA9CF0551D63@apple.com> <4C2C3942-D5E1-4BC7-A504-EDEBB411EB83@apple.com> Message-ID: <20110224004818.GA18314@fibrous.localdomain> On Wed, Feb 23, 2011 at 03:59:37PM -0800, Greg Clayton wrote: > Or use the llvm::sys::getHostTriple() like you did in path 2/4... OK. How about the following patch. Instead of filling in unknown fields selectively this version updates the missing vendor/OS/environment fields iff all of them are undefined. This should help in the situations where, for example, you are debugging an embedded linux board remotely on darwin. Otherwise a call to SetTriple("armv5l-unknown-linux") would come out as "armv5l-apple-linux". diff --git a/include/lldb/Core/ArchSpec.h b/include/lldb/Core/ArchSpec.h index a479f47..69fff9f 100644 --- a/include/lldb/Core/ArchSpec.h +++ b/include/lldb/Core/ArchSpec.h @@ -294,11 +294,12 @@ public: //------------------------------------------------------------------ /// Architecture tripple setter. /// - /// Configures this ArchSpec according to the given triple. At a - /// minimum, the given triple must describe a valid operating - /// system. If archetecture or environment components are present - /// they too will be used to further resolve the CPU type and - /// subtype, endian characteristics, etc. + /// Configures this ArchSpec according to the given triple. If the + /// triple has unknown components in all of the vendor, OS, and + /// the optional environment field (i.e. "i386-unknown-unknown") + /// then default values are taken from the host. Architecture and + /// environment components are used to further resolve the CPU type + /// and subtype, endian characteristics, etc. /// /// @return A triple describing this ArchSpec. //------------------------------------------------------------------ diff --git a/source/Core/ArchSpec.cpp b/source/Core/ArchSpec.cpp index a5493b3..3d59d28 100644 --- a/source/Core/ArchSpec.cpp +++ b/source/Core/ArchSpec.cpp @@ -14,6 +14,7 @@ #include #include "llvm/Support/ELF.h" +#include "llvm/Support/Host.h" #include "llvm/Support/MachO.h" #include "lldb/Host/Endian.h" #include "lldb/Host/Host.h" @@ -407,14 +408,16 @@ ArchSpec::SetTriple (const llvm::Triple &triple) m_core = core_def->core; m_byte_order = core_def->default_byte_order; - // If the vendor, OS or environment aren't specified, default to the system? - const ArchSpec &host_arch_ref = Host::GetArchitecture (Host::eSystemDefaultArchitecture); - if (m_triple.getVendor() == llvm::Triple::UnknownVendor) - m_triple.setVendor(host_arch_ref.GetTriple().getVendor()); - if (m_triple.getOS() == llvm::Triple::UnknownOS) - m_triple.setOS(host_arch_ref.GetTriple().getOS()); - if (m_triple.getEnvironment() == llvm::Triple::UnknownEnvironment) - m_triple.setEnvironment(host_arch_ref.GetTriple().getEnvironment()); + if (m_triple.getVendor() == llvm::Triple::UnknownVendor && + m_triple.getOS() == llvm::Triple::UnknownOS && + m_triple.getEnvironment() == llvm::Triple::UnknownEnvironment) + { + llvm::Triple host_triple(llvm::sys::getHostTriple()); + + m_triple.setVendor(host_triple.getVendor()); + m_triple.setOS(host_triple.getOS()); + m_triple.setEnvironment(host_triple.getEnvironment()); + } } else { From johnny.chen at apple.com Wed Feb 23 19:15:18 2011 From: johnny.chen at apple.com (Johnny Chen) Date: Thu, 24 Feb 2011 01:15:18 -0000 Subject: [Lldb-commits] [lldb] r126355 - in /lldb/trunk/source/Plugins/Instruction/ARM: EmulateInstructionARM.cpp EmulateInstructionARM.h Message-ID: <20110224011518.2F0942A6C12C@llvm.org> Author: johnny Date: Wed Feb 23 19:15:17 2011 New Revision: 126355 URL: http://llvm.org/viewvc/llvm-project?rev=126355&view=rev Log: Add emulation methods for Bitwise Bit Clear (immediate and register) operations. Modified: lldb/trunk/source/Plugins/Instruction/ARM/EmulateInstructionARM.cpp lldb/trunk/source/Plugins/Instruction/ARM/EmulateInstructionARM.h Modified: lldb/trunk/source/Plugins/Instruction/ARM/EmulateInstructionARM.cpp URL: http://llvm.org/viewvc/llvm-project/lldb/trunk/source/Plugins/Instruction/ARM/EmulateInstructionARM.cpp?rev=126355&r1=126354&r2=126355&view=diff ============================================================================== --- lldb/trunk/source/Plugins/Instruction/ARM/EmulateInstructionARM.cpp (original) +++ lldb/trunk/source/Plugins/Instruction/ARM/EmulateInstructionARM.cpp Wed Feb 23 19:15:17 2011 @@ -4905,6 +4905,171 @@ return true; } +// Bitwise Bit Clear (immediate) performs a bitwise AND of a register value and the complement of an +// immediate value, and writes the result to the destination register. It can optionally update the +// condition flags based on the result. +bool +EmulateInstructionARM::EmulateBICImm (ARMEncoding encoding) +{ +#if 0 + // ARM pseudo code... + if ConditionPassed() then + EncodingSpecificOperations(); + result = R[n] AND NOT(imm32); + if d == 15 then // Can only occur for ARM encoding + ALUWritePC(result); // setflags is always FALSE here + else + R[d] = result; + if setflags then + APSR.N = result<31>; + APSR.Z = IsZeroBit(result); + APSR.C = carry; + // APSR.V unchanged +#endif + + bool success = false; + const uint32_t opcode = OpcodeAsUnsigned (&success); + if (!success) + return false; + + if (ConditionPassed()) + { + uint32_t Rd, Rn; + uint32_t imm32; // the immediate value to be bitwise inverted and ANDed to the value obtained from Rn + bool setflags; + uint32_t carry; // the carry bit after ARM/Thumb Expand operation + switch (encoding) + { + case eEncodingT1: + Rd = Bits32(opcode, 11, 8); + Rn = Bits32(opcode, 19, 16); + setflags = BitIsSet(opcode, 20); + imm32 = ThumbExpandImm_C(opcode, APSR_C, carry); // (imm32, carry) = ThumbExpandImm(i:imm3:imm8, APSR.C) + if (BadReg(Rd) || BadReg(Rn)) + return false; + break; + case eEncodingA1: + Rd = Bits32(opcode, 15, 12); + Rn = Bits32(opcode, 19, 16); + setflags = BitIsSet(opcode, 20); + imm32 = ARMExpandImm_C(opcode, APSR_C, carry); // (imm32, carry) = ARMExpandImm(imm12, APSR.C) + // if Rd == ???1111??? && S == ???1??? then SEE SUBS PC, LR and related instructions; + // TODO: Emulate SUBS PC, LR and related instructions. + if (Rd == 15 && setflags) + return false; + break; + default: + return false; + } + + // Read the first operand. + uint32_t val1 = ReadCoreReg(Rn, &success); + if (!success) + return false; + + uint32_t result = val1 & ~imm32; + + EmulateInstruction::Context context; + context.type = EmulateInstruction::eContextImmediate; + context.SetNoArgs (); + + if (!WriteCoreRegOptionalFlags(context, result, Rd, setflags, carry)) + return false; + } + return true; +} + +// Bitwise Bit Clear (register) performs a bitwise AND of a register value and the complement of an +// optionally-shifted register value, and writes the result to the destination register. +// It can optionally update the condition flags based on the result. +bool +EmulateInstructionARM::EmulateBICReg (ARMEncoding encoding) +{ +#if 0 + // ARM pseudo code... + if ConditionPassed() then + EncodingSpecificOperations(); + (shifted, carry) = Shift_C(R[m], shift_t, shift_n, APSR.C); + result = R[n] AND NOT(shifted); + if d == 15 then // Can only occur for ARM encoding + ALUWritePC(result); // setflags is always FALSE here + else + R[d] = result; + if setflags then + APSR.N = result<31>; + APSR.Z = IsZeroBit(result); + APSR.C = carry; + // APSR.V unchanged +#endif + + bool success = false; + const uint32_t opcode = OpcodeAsUnsigned (&success); + if (!success) + return false; + + if (ConditionPassed()) + { + uint32_t Rd, Rn, Rm; + ARM_ShifterType shift_t; + uint32_t shift_n; // the shift applied to the value read from Rm + bool setflags; + uint32_t carry; + switch (encoding) + { + case eEncodingT1: + Rd = Rn = Bits32(opcode, 2, 0); + Rm = Bits32(opcode, 5, 3); + setflags = !InITBlock(); + shift_t = SRType_LSL; + shift_n = 0; + break; + case eEncodingT2: + Rd = Bits32(opcode, 11, 8); + Rn = Bits32(opcode, 19, 16); + Rm = Bits32(opcode, 3, 0); + setflags = BitIsSet(opcode, 20); + shift_n = DecodeImmShiftThumb(opcode, shift_t); + if (BadReg(Rd) || BadReg(Rn) || BadReg(Rm)) + return false; + break; + case eEncodingA1: + Rd = Bits32(opcode, 15, 12); + Rn = Bits32(opcode, 19, 16); + Rm = Bits32(opcode, 3, 0); + setflags = BitIsSet(opcode, 20); + shift_n = DecodeImmShiftARM(opcode, shift_t); + // if Rd == ???1111??? && S == ???1??? then SEE SUBS PC, LR and related instructions; + // TODO: Emulate SUBS PC, LR and related instructions. + if (Rd == 15 && setflags) + return false; + break; + default: + return false; + } + + // Read the first operand. + uint32_t val1 = ReadCoreReg(Rn, &success); + if (!success) + return false; + + // Read the second operand. + uint32_t val2 = ReadCoreReg(Rm, &success); + if (!success) + return false; + + uint32_t shifted = Shift_C(val2, shift_t, shift_n, APSR_C, carry); + uint32_t result = val1 & ~shifted; + + EmulateInstruction::Context context; + context.type = EmulateInstruction::eContextImmediate; + context.SetNoArgs (); + + if (!WriteCoreRegOptionalFlags(context, result, Rd, setflags, carry)) + return false; + } + return true; +} + // LDR (immediate, ARM) calculates an address from a base register value and an immediate offset, loads a word // from memory, and writes it to a register. It can use offset, post-indexed, or pre-indexed addressing. bool @@ -6923,6 +7088,10 @@ { 0x0fe00000, 0x02000000, ARMvAll, eEncodingA1, eSize32, &EmulateInstructionARM::EmulateANDImm, "and{s} , , #const"}, // and (register) { 0x0fe00010, 0x00000000, ARMvAll, eEncodingA1, eSize32, &EmulateInstructionARM::EmulateANDReg, "and{s} , , {,}"}, + // bic (immediate) + { 0x0fe00000, 0x03c00000, ARMvAll, eEncodingA1, eSize32, &EmulateInstructionARM::EmulateBICImm, "bic{s} , , #const"}, + // bic (register) + { 0x0fe00010, 0x01c00000, ARMvAll, eEncodingA1, eSize32, &EmulateInstructionARM::EmulateBICReg, "bic{s} , , {,}"}, // eor (immediate) { 0x0fe00000, 0x02200000, ARMvAll, eEncodingA1, eSize32, &EmulateInstructionARM::EmulateEORImm, "eor{s} , , #const"}, // eor (register) @@ -7122,6 +7291,11 @@ // and (register) { 0xffffffc0, 0x00004000, ARMvAll, eEncodingT1, eSize16, &EmulateInstructionARM::EmulateANDReg, "ands|and , "}, { 0xffe08000, 0xea000000, ARMV6T2_ABOVE, eEncodingT2, eSize32, &EmulateInstructionARM::EmulateANDReg, "and{s}.w , , {,}"}, + // bic (immediate) + { 0xfbe08000, 0xf0200000, ARMV6T2_ABOVE, eEncodingT1, eSize32, &EmulateInstructionARM::EmulateBICImm, "bic{s} , , #"}, + // bic (register) + { 0xffffffc0, 0x00004380, ARMvAll, eEncodingT1, eSize16, &EmulateInstructionARM::EmulateBICReg, "bics|bic , "}, + { 0xffe08000, 0xea200000, ARMV6T2_ABOVE, eEncodingT2, eSize32, &EmulateInstructionARM::EmulateBICReg, "bic{s}.w , , {,}"}, // eor (immediate) { 0xfbe08000, 0xf0800000, ARMV6T2_ABOVE, eEncodingT1, eSize32, &EmulateInstructionARM::EmulateEORImm, "eor{s} , , #"}, // eor (register) Modified: lldb/trunk/source/Plugins/Instruction/ARM/EmulateInstructionARM.h URL: http://llvm.org/viewvc/llvm-project/lldb/trunk/source/Plugins/Instruction/ARM/EmulateInstructionARM.h?rev=126355&r1=126354&r2=126355&view=diff ============================================================================== --- lldb/trunk/source/Plugins/Instruction/ARM/EmulateInstructionARM.h (original) +++ lldb/trunk/source/Plugins/Instruction/ARM/EmulateInstructionARM.h Wed Feb 23 19:15:17 2011 @@ -546,13 +546,13 @@ bool EmulateANDReg (ARMEncoding encoding); - // A8.6.19 BIC (immediate) - Encoding A1 + // A8.6.19 BIC (immediate) bool - EmulateBICImmediate (ARMEncoding encoding); + EmulateBICImm (ARMEncoding encoding); - // A8.6.20 BIC (register) - Encoding T1, A1 + // A8.6.20 BIC (register) bool - EmulateBICRegister (ARMEncoding encoding); + EmulateBICReg (ARMEncoding encoding); // A8.6.26 BXJ bool From gclayton at apple.com Thu Feb 24 11:28:00 2011 From: gclayton at apple.com (Greg Clayton) Date: Thu, 24 Feb 2011 09:28:00 -0800 Subject: [Lldb-commits] [PATCH 1/4] ArchSpec: Do not set default to host settings when setting a triple. In-Reply-To: <20110224004818.GA18314@fibrous.localdomain> References: <1298495782-17446-1-git-send-email-wilsons@start.ca> <1298495782-17446-2-git-send-email-wilsons@start.ca> <44EC619F-DD25-443D-AF34-AA9CF0551D63@apple.com> <4C2C3942-D5E1-4BC7-A504-EDEBB411EB83@apple.com> <20110224004818.GA18314@fibrous.localdomain> Message-ID: <2B83B8A0-EBF4-42B5-9F5B-F99C3830952F@apple.com> I like it. Make it so. On Feb 23, 2011, at 4:48 PM, Stephen Wilson wrote: > > > On Wed, Feb 23, 2011 at 03:59:37PM -0800, Greg Clayton wrote: >> Or use the llvm::sys::getHostTriple() like you did in path 2/4... > > OK. How about the following patch. Instead of filling in unknown > fields selectively this version updates the missing > vendor/OS/environment fields iff all of them are undefined. > > This should help in the situations where, for example, you are > debugging an embedded linux board remotely on darwin. Otherwise a call to > SetTriple("armv5l-unknown-linux") would come out as "armv5l-apple-linux". > > > diff --git a/include/lldb/Core/ArchSpec.h b/include/lldb/Core/ArchSpec.h > index a479f47..69fff9f 100644 > --- a/include/lldb/Core/ArchSpec.h > +++ b/include/lldb/Core/ArchSpec.h > @@ -294,11 +294,12 @@ public: > //------------------------------------------------------------------ > /// Architecture tripple setter. > /// > - /// Configures this ArchSpec according to the given triple. At a > - /// minimum, the given triple must describe a valid operating > - /// system. If archetecture or environment components are present > - /// they too will be used to further resolve the CPU type and > - /// subtype, endian characteristics, etc. > + /// Configures this ArchSpec according to the given triple. If the > + /// triple has unknown components in all of the vendor, OS, and > + /// the optional environment field (i.e. "i386-unknown-unknown") > + /// then default values are taken from the host. Architecture and > + /// environment components are used to further resolve the CPU type > + /// and subtype, endian characteristics, etc. > /// > /// @return A triple describing this ArchSpec. > //------------------------------------------------------------------ > diff --git a/source/Core/ArchSpec.cpp b/source/Core/ArchSpec.cpp > index a5493b3..3d59d28 100644 > --- a/source/Core/ArchSpec.cpp > +++ b/source/Core/ArchSpec.cpp > @@ -14,6 +14,7 @@ > #include > > #include "llvm/Support/ELF.h" > +#include "llvm/Support/Host.h" > #include "llvm/Support/MachO.h" > #include "lldb/Host/Endian.h" > #include "lldb/Host/Host.h" > @@ -407,14 +408,16 @@ ArchSpec::SetTriple (const llvm::Triple &triple) > m_core = core_def->core; > m_byte_order = core_def->default_byte_order; > > - // If the vendor, OS or environment aren't specified, default to the system? > - const ArchSpec &host_arch_ref = Host::GetArchitecture (Host::eSystemDefaultArchitecture); > - if (m_triple.getVendor() == llvm::Triple::UnknownVendor) > - m_triple.setVendor(host_arch_ref.GetTriple().getVendor()); > - if (m_triple.getOS() == llvm::Triple::UnknownOS) > - m_triple.setOS(host_arch_ref.GetTriple().getOS()); > - if (m_triple.getEnvironment() == llvm::Triple::UnknownEnvironment) > - m_triple.setEnvironment(host_arch_ref.GetTriple().getEnvironment()); > + if (m_triple.getVendor() == llvm::Triple::UnknownVendor && > + m_triple.getOS() == llvm::Triple::UnknownOS && > + m_triple.getEnvironment() == llvm::Triple::UnknownEnvironment) > + { > + llvm::Triple host_triple(llvm::sys::getHostTriple()); > + > + m_triple.setVendor(host_triple.getVendor()); > + m_triple.setOS(host_triple.getOS()); > + m_triple.setEnvironment(host_triple.getEnvironment()); > + } > } > else > { From wilsons at start.ca Thu Feb 24 13:13:58 2011 From: wilsons at start.ca (Stephen Wilson) Date: Thu, 24 Feb 2011 19:13:58 -0000 Subject: [Lldb-commits] [lldb] r126403 - in /lldb/trunk: include/lldb/Core/ArchSpec.h source/Core/ArchSpec.cpp Message-ID: <20110224191358.5B81F2A6C12C@llvm.org> Author: wilsons Date: Thu Feb 24 13:13:58 2011 New Revision: 126403 URL: http://llvm.org/viewvc/llvm-project?rev=126403&view=rev Log: ArchSpec: Do not depend on Host::GetArchitecture. The major issue this patch solves is that ArchSpec::SetTriple no longer depends on the implementation of Host::GetArchitecture. On linux, Host::GetArchitecture calls ArchSpec::SetTriple, thus blowing the stack. A second smaller point is that SetTriple now defaults to Host defined components iff all OS, vendor and environment fields are not set. Modified: lldb/trunk/include/lldb/Core/ArchSpec.h lldb/trunk/source/Core/ArchSpec.cpp Modified: lldb/trunk/include/lldb/Core/ArchSpec.h URL: http://llvm.org/viewvc/llvm-project/lldb/trunk/include/lldb/Core/ArchSpec.h?rev=126403&r1=126402&r2=126403&view=diff ============================================================================== --- lldb/trunk/include/lldb/Core/ArchSpec.h (original) +++ lldb/trunk/include/lldb/Core/ArchSpec.h Thu Feb 24 13:13:58 2011 @@ -294,11 +294,12 @@ //------------------------------------------------------------------ /// Architecture tripple setter. /// - /// Configures this ArchSpec according to the given triple. At a - /// minimum, the given triple must describe a valid operating - /// system. If archetecture or environment components are present - /// they too will be used to further resolve the CPU type and - /// subtype, endian characteristics, etc. + /// Configures this ArchSpec according to the given triple. If the + /// triple has unknown components in all of the vendor, OS, and + /// the optional environment field (i.e. "i386-unknown-unknown") + /// then default values are taken from the host. Architecture and + /// environment components are used to further resolve the CPU type + /// and subtype, endian characteristics, etc. /// /// @return A triple describing this ArchSpec. //------------------------------------------------------------------ Modified: lldb/trunk/source/Core/ArchSpec.cpp URL: http://llvm.org/viewvc/llvm-project/lldb/trunk/source/Core/ArchSpec.cpp?rev=126403&r1=126402&r2=126403&view=diff ============================================================================== --- lldb/trunk/source/Core/ArchSpec.cpp (original) +++ lldb/trunk/source/Core/ArchSpec.cpp Thu Feb 24 13:13:58 2011 @@ -14,6 +14,7 @@ #include #include "llvm/Support/ELF.h" +#include "llvm/Support/Host.h" #include "llvm/Support/MachO.h" #include "lldb/Host/Endian.h" #include "lldb/Host/Host.h" @@ -407,14 +408,16 @@ m_core = core_def->core; m_byte_order = core_def->default_byte_order; - // If the vendor, OS or environment aren't specified, default to the system? - const ArchSpec &host_arch_ref = Host::GetArchitecture (Host::eSystemDefaultArchitecture); - if (m_triple.getVendor() == llvm::Triple::UnknownVendor) - m_triple.setVendor(host_arch_ref.GetTriple().getVendor()); - if (m_triple.getOS() == llvm::Triple::UnknownOS) - m_triple.setOS(host_arch_ref.GetTriple().getOS()); - if (m_triple.getEnvironment() == llvm::Triple::UnknownEnvironment) - m_triple.setEnvironment(host_arch_ref.GetTriple().getEnvironment()); + if (m_triple.getVendor() == llvm::Triple::UnknownVendor && + m_triple.getOS() == llvm::Triple::UnknownOS && + m_triple.getEnvironment() == llvm::Triple::UnknownEnvironment) + { + llvm::Triple host_triple(llvm::sys::getHostTriple()); + + m_triple.setVendor(host_triple.getVendor()); + m_triple.setOS(host_triple.getOS()); + m_triple.setEnvironment(host_triple.getEnvironment()); + } } else { From wilsons at start.ca Thu Feb 24 13:15:09 2011 From: wilsons at start.ca (Stephen Wilson) Date: Thu, 24 Feb 2011 19:15:09 -0000 Subject: [Lldb-commits] [lldb] r126404 - /lldb/trunk/source/Host/common/Host.cpp Message-ID: <20110224191509.4E2962A6C12C@llvm.org> Author: wilsons Date: Thu Feb 24 13:15:09 2011 New Revision: 126404 URL: http://llvm.org/viewvc/llvm-project?rev=126404&view=rev Log: Host: linux: Use llvm::sys::getHostTriple for the default host ArchSpec. Previously we were using a set of preprocessor defines and returning an ArchSpec without any OS/Vendor information. This fixes an issue with plugin resolution on Linux where a valid OS component is needed. Modified: lldb/trunk/source/Host/common/Host.cpp Modified: lldb/trunk/source/Host/common/Host.cpp URL: http://llvm.org/viewvc/llvm-project/lldb/trunk/source/Host/common/Host.cpp?rev=126404&r1=126403&r2=126404&view=diff ============================================================================== --- lldb/trunk/source/Host/common/Host.cpp (original) +++ lldb/trunk/source/Host/common/Host.cpp Thu Feb 24 13:15:09 2011 @@ -18,6 +18,8 @@ #include "lldb/Host/Endian.h" #include "lldb/Host/Mutex.h" +#include "llvm/Support/Host.h" + #include #include @@ -288,34 +290,31 @@ } #else // #if defined (__APPLE__) - + if (g_supports_32 == false && g_supports_64 == false) { -#if defined (__x86_64__) - - g_host_arch_64.SetTriple ("x86_64"); - -#elif defined (__i386__) - - g_host_arch_32.SetTriple ("i386"); - -#elif defined (__arm__) - - g_host_arch_32.SetTriple ("arm"); - -#elif defined (__ppc64__) + llvm::Triple triple(llvm::sys::getHostTriple()); - g_host_arch_64.SetTriple ("ppc64"); + g_host_arch_32.Clear(); + g_host_arch_64.Clear(); -#elif defined (__powerpc__) || defined (__ppc__) - - g_host_arch_32.SetTriple ("ppc"); - -#else - -#error undefined architecture, define your architecture here - -#endif + switch (triple.getArch()) + { + default: + g_host_arch_32.SetTriple(triple); + g_supports_32 = true; + break; + + case llvm::Triple::alpha: + case llvm::Triple::x86_64: + case llvm::Triple::sparcv9: + case llvm::Triple::ppc64: + case llvm::Triple::systemz: + case llvm::Triple::cellspu: + g_host_arch_64.SetTriple(triple); + g_supports_64 = true; + break; + } g_supports_32 = g_host_arch_32.IsValid(); g_supports_64 = g_host_arch_64.IsValid(); From wilsons at start.ca Thu Feb 24 13:16:15 2011 From: wilsons at start.ca (Stephen Wilson) Date: Thu, 24 Feb 2011 19:16:15 -0000 Subject: [Lldb-commits] [lldb] r126405 - in /lldb/trunk/source/Plugins/ObjectFile/ELF: ObjectFileELF.cpp ObjectFileELF.h Message-ID: <20110224191615.EBC2C2A6C12C@llvm.org> Author: wilsons Date: Thu Feb 24 13:16:15 2011 New Revision: 126405 URL: http://llvm.org/viewvc/llvm-project?rev=126405&view=rev Log: linux: Remove a local ObjectFileELF version of GetArchitecture. Also fix a bug where we were not lazily parsing the ELF header and thus returning an ArchSpec with invalid cpu type components. Initialize the cpu subtype as LLDB_INVALID_CPUTYPE for compatibility with the new ArchSpec implementation. Modified: lldb/trunk/source/Plugins/ObjectFile/ELF/ObjectFileELF.cpp lldb/trunk/source/Plugins/ObjectFile/ELF/ObjectFileELF.h Modified: lldb/trunk/source/Plugins/ObjectFile/ELF/ObjectFileELF.cpp URL: http://llvm.org/viewvc/llvm-project/lldb/trunk/source/Plugins/ObjectFile/ELF/ObjectFileELF.cpp?rev=126405&r1=126404&r2=126405&view=diff ============================================================================== --- lldb/trunk/source/Plugins/ObjectFile/ELF/ObjectFileELF.cpp (original) +++ lldb/trunk/source/Plugins/ObjectFile/ELF/ObjectFileELF.cpp Thu Feb 24 13:16:15 2011 @@ -74,8 +74,9 @@ { std::auto_ptr objfile_ap( new ObjectFileELF(module, data_sp, file, offset, length)); - ArchSpec spec = objfile_ap->GetArchitecture(); - if (spec.IsValid() && objfile_ap->SetModulesArchitecture(spec)) + ArchSpec spec; + if (objfile_ap->GetArchitecture(spec) && + objfile_ap->SetModulesArchitecture(spec)) return objfile_ap.release(); } } @@ -83,14 +84,6 @@ return NULL; } -ArchSpec -ObjectFileELF::GetArchitecture() -{ - if (!ParseHeader()) - return ArchSpec(); - - return ArchSpec(eArchTypeELF, m_header.e_machine, m_header.e_flags); -} //------------------------------------------------------------------ // PluginInterface protocol @@ -1046,7 +1039,10 @@ bool ObjectFileELF::GetArchitecture (ArchSpec &arch) { - arch.SetArchitecture (lldb::eArchTypeELF, m_header.e_machine, m_header.e_flags); + if (!ParseHeader()) + return false; + + arch.SetArchitecture (lldb::eArchTypeELF, m_header.e_machine, LLDB_INVALID_CPUTYPE); arch.GetTriple().setOSName (Host::GetOSString().GetCString()); arch.GetTriple().setVendorName(Host::GetVendorString().GetCString()); return true; Modified: lldb/trunk/source/Plugins/ObjectFile/ELF/ObjectFileELF.h URL: http://llvm.org/viewvc/llvm-project/lldb/trunk/source/Plugins/ObjectFile/ELF/ObjectFileELF.h?rev=126405&r1=126404&r2=126405&view=diff ============================================================================== --- lldb/trunk/source/Plugins/ObjectFile/ELF/ObjectFileELF.h (original) +++ lldb/trunk/source/Plugins/ObjectFile/ELF/ObjectFileELF.h Thu Feb 24 13:16:15 2011 @@ -116,9 +116,6 @@ virtual lldb_private::Address GetImageInfoAddress(); - lldb_private::ArchSpec - GetArchitecture(); - private: ObjectFileELF(lldb_private::Module* module, lldb::DataBufferSP& dataSP, From wilsons at start.ca Thu Feb 24 13:17:09 2011 From: wilsons at start.ca (Stephen Wilson) Date: Thu, 24 Feb 2011 19:17:09 -0000 Subject: [Lldb-commits] [lldb] r126406 - in /lldb/trunk/source/Plugins/Process/Linux: LinuxThread.cpp ProcessLinux.cpp Message-ID: <20110224191709.C60EB2A6C12C@llvm.org> Author: wilsons Date: Thu Feb 24 13:17:09 2011 New Revision: 126406 URL: http://llvm.org/viewvc/llvm-project?rev=126406&view=rev Log: linux: Use ArchSpec::GetCore and the ArchSpec::Core enums. Modified: lldb/trunk/source/Plugins/Process/Linux/LinuxThread.cpp lldb/trunk/source/Plugins/Process/Linux/ProcessLinux.cpp Modified: lldb/trunk/source/Plugins/Process/Linux/LinuxThread.cpp URL: http://llvm.org/viewvc/llvm-project/lldb/trunk/source/Plugins/Process/Linux/LinuxThread.cpp?rev=126406&r1=126405&r2=126406&view=diff ============================================================================== --- lldb/trunk/source/Plugins/Process/Linux/LinuxThread.cpp (original) +++ lldb/trunk/source/Plugins/Process/Linux/LinuxThread.cpp Thu Feb 24 13:17:09 2011 @@ -65,13 +65,13 @@ { ArchSpec arch = process.GetTarget().GetArchitecture(); - switch (arch.GetGenericCPUType()) + switch (arch.GetCore()) { default: assert(false && "CPU type not supported!"); break; - case ArchSpec::eCPU_x86_64: + case ArchSpec::eCore_x86_64_x86_64: m_reg_context_sp.reset(new RegisterContextLinux_x86_64(*this, 0)); break; } Modified: lldb/trunk/source/Plugins/Process/Linux/ProcessLinux.cpp URL: http://llvm.org/viewvc/llvm-project/lldb/trunk/source/Plugins/Process/Linux/ProcessLinux.cpp?rev=126406&r1=126405&r2=126406&view=diff ============================================================================== --- lldb/trunk/source/Plugins/Process/Linux/ProcessLinux.cpp (original) +++ lldb/trunk/source/Plugins/Process/Linux/ProcessLinux.cpp Thu Feb 24 13:17:09 2011 @@ -353,14 +353,14 @@ const uint8_t *opcode = NULL; size_t opcode_size = 0; - switch (arch.GetGenericCPUType()) + switch (arch.GetCore()) { default: assert(false && "CPU type not supported!"); break; - case ArchSpec::eCPU_i386: - case ArchSpec::eCPU_x86_64: + case ArchSpec::eCore_x86_32_i386: + case ArchSpec::eCore_x86_64_x86_64: opcode = g_i386_opcode; opcode_size = sizeof(g_i386_opcode); break; From johnny.chen at apple.com Thu Feb 24 15:01:20 2011 From: johnny.chen at apple.com (Johnny Chen) Date: Thu, 24 Feb 2011 21:01:20 -0000 Subject: [Lldb-commits] [lldb] r126423 - in /lldb/trunk/source/Plugins/Instruction/ARM: EmulateInstructionARM.cpp EmulateInstructionARM.h Message-ID: <20110224210120.F052C2A6C12C@llvm.org> Author: johnny Date: Thu Feb 24 15:01:20 2011 New Revision: 126423 URL: http://llvm.org/viewvc/llvm-project?rev=126423&view=rev Log: Add emulation for BXJ (Branch and Exchange Jazelle), assuming that the attempt to switch to Jazelle state fails, thus treating BXJ as a BX operation. Modified: lldb/trunk/source/Plugins/Instruction/ARM/EmulateInstructionARM.cpp lldb/trunk/source/Plugins/Instruction/ARM/EmulateInstructionARM.h Modified: lldb/trunk/source/Plugins/Instruction/ARM/EmulateInstructionARM.cpp URL: http://llvm.org/viewvc/llvm-project/lldb/trunk/source/Plugins/Instruction/ARM/EmulateInstructionARM.cpp?rev=126423&r1=126422&r2=126423&view=diff ============================================================================== --- lldb/trunk/source/Plugins/Instruction/ARM/EmulateInstructionARM.cpp (original) +++ lldb/trunk/source/Plugins/Instruction/ARM/EmulateInstructionARM.cpp Thu Feb 24 15:01:20 2011 @@ -129,6 +129,7 @@ #define ARMV4T_ABOVE (ARMv4T|ARMv5T|ARMv5TE|ARMv5TEJ|ARMv6|ARMv6K|ARMv6T2|ARMv7|ARMv8) #define ARMV5_ABOVE (ARMv5T|ARMv5TE|ARMv5TEJ|ARMv6|ARMv6K|ARMv6T2|ARMv7|ARMv8) +#define ARMV5J_ABOVE (ARMv5TEJ|ARMv6|ARMv6K|ARMv6T2|ARMv7|ARMv8) #define ARMV6T2_ABOVE (ARMv6T2|ARMv7|ARMv8) //---------------------------------------------------------------------- @@ -1247,7 +1248,6 @@ } // Branch and Exchange causes a branch to an address and instruction set specified by a register. -// BX bool EmulateInstructionARM::EmulateBXRm (ARMEncoding encoding) { @@ -1295,6 +1295,68 @@ return true; } +// Branch and Exchange Jazelle attempts to change to Jazelle state. If the attempt fails, it branches to an +// address and instruction set specified by a register as though it were a BX instruction. +// +// TODO: Emulate Jazelle architecture? +// We currently assume that switching to Jazelle state fails, thus treating BXJ as a BX operation. +bool +EmulateInstructionARM::EmulateBXJRm (ARMEncoding encoding) +{ +#if 0 + // ARM pseudo code... + if (ConditionPassed()) + { + EncodingSpecificOperations(); + if JMCR.JE == ???0??? || CurrentInstrSet() == InstrSet_ThumbEE then + BXWritePC(R[m]); + else + if JazelleAcceptsExecution() then + SwitchToJazelleExecution(); + else + SUBARCHITECTURE_DEFINED handler call; + } +#endif + + bool success = false; + const uint32_t opcode = OpcodeAsUnsigned (&success); + if (!success) + return false; + + if (ConditionPassed()) + { + EmulateInstruction::Context context; + context.type = EmulateInstruction::eContextAbsoluteBranchRegister; + uint32_t Rm; // the register with the target address + switch (encoding) { + case eEncodingT1: + Rm = Bits32(opcode, 19, 16); + if (BadReg(Rm)) + return false; + if (InITBlock() && !LastInITBlock()) + return false; + break; + case eEncodingA1: + Rm = Bits32(opcode, 3, 0); + if (Rm == 15) + return false; + break; + default: + return false; + } + addr_t target = ReadCoreReg (Rm, &success); + if (!success) + return false; + + Register dwarf_reg; + dwarf_reg.SetRegister (eRegisterKindDWARF, dwarf_r0 + Rm); + context.SetRegister (dwarf_reg); + if (!BXWritePC(context, target)) + return false; + } + return true; +} + // Set r7 to point to some ip offset. // SUB (immediate) bool @@ -7069,6 +7131,8 @@ { 0x0ffffff0, 0x012fff30, ARMV5_ABOVE, eEncodingA1, eSize32, &EmulateInstructionARM::EmulateBLXRm, "blx "}, // for example, "bx lr" { 0x0ffffff0, 0x012fff10, ARMvAll, eEncodingA1, eSize32, &EmulateInstructionARM::EmulateBXRm, "bx "}, + // bxj + { 0x0ffffff0, 0x012fff20, ARMvAll, eEncodingA1, eSize32, &EmulateInstructionARM::EmulateBXJRm, "bxj "}, //---------------------------------------------------------------------- // Data-processing instructions @@ -7263,6 +7327,8 @@ { 0xffffff87, 0x00004780, ARMV5_ABOVE, eEncodingT1, eSize16, &EmulateInstructionARM::EmulateBLXRm, "blx "}, // for example, "bx lr" { 0xffffff87, 0x00004700, ARMvAll, eEncodingA1, eSize32, &EmulateInstructionARM::EmulateBXRm, "bx "}, + // bxj + { 0xfff0ffff, 0xf3c08f00, ARMV5J_ABOVE, eEncodingT1, eSize32, &EmulateInstructionARM::EmulateBXJRm, "bxj "}, // compare and branch { 0xfffff500, 0x0000b100, ARMV6T2_ABOVE, eEncodingT1, eSize16, &EmulateInstructionARM::EmulateCB, "cb{n}z ,