From ctice at apple.com Mon Mar 28 11:10:45 2011 From: ctice at apple.com (Caroline Tice) Date: Mon, 28 Mar 2011 16:10:45 -0000 Subject: [Lldb-commits] [lldb] r128409 - /lldb/trunk/source/Plugins/Instruction/ARM/EmulateInstructionARM.cpp Message-ID: <20110328161045.80FFE2A6C12C@llvm.org> Author: ctice Date: Mon Mar 28 11:10:45 2011 New Revision: 128409 URL: http://llvm.org/viewvc/llvm-project?rev=128409&view=rev Log: Fix single quote characters throughout the ARM emulation stuff. Fix bugs in various ARM istruction emulation functions: EmulateVPUSH - Fix context. - Fix bug calculating register numbers. EmulateVPOP - Fix context. - Fix bug calculating register numbers. EmulateShiftIMM - Fix bug in assert statement. EmulateLDMDA - Fix context. EmulateLDMDB - Fix context. EmulateLDMIB - Fix context. EmulateSTM - Fix bug calculating lowest_set_bit. EmulateSTMDA - Fix context. - Fix bug calculating lowest_set_bit. EmulateSTMDB - Fix context. - Fix bug calculating lowest_set_bit. EmulateSTMIB - FIx context EmulateLDRSBImmed - Fix test to match correction in corrected manual Modified: lldb/trunk/source/Plugins/Instruction/ARM/EmulateInstructionARM.cpp Modified: lldb/trunk/source/Plugins/Instruction/ARM/EmulateInstructionARM.cpp URL: http://llvm.org/viewvc/llvm-project/lldb/trunk/source/Plugins/Instruction/ARM/EmulateInstructionARM.cpp?rev=128409&r1=128408&r2=128409&view=diff ============================================================================== --- lldb/trunk/source/Plugins/Instruction/ARM/EmulateInstructionARM.cpp (original) +++ lldb/trunk/source/Plugins/Instruction/ARM/EmulateInstructionARM.cpp Mon Mar 28 11:10:45 2011 @@ -202,7 +202,7 @@ for (i = 0 to 14) { - if (registers == ???1???) + if (registers == '1') { if i == 13 && i != LowestSetBit(registers) // Only possible for encoding A1 MemA[address,4] = bits(32) UNKNOWN; @@ -212,7 +212,7 @@ } } - if (registers<15> == ???1???) // Only possible for encoding A1 or A2 + if (registers<15> == '1') // Only possible for encoding A1 or A2 MemA[address,4] = PCStoreValue(); SP = SP - 4*BitCount(registers); @@ -326,15 +326,15 @@ EncodingSpecificOperations(); NullCheckIfThumbEE(13); address = SP; for i = 0 to 14 - if registers == ???1??? then + if registers == '1' then R[i} = if UnalignedAllowed then MemU[address,4] else MemA[address,4]; address = address + 4; - if registers<15> == ???1??? then + if registers<15> == '1' then if UnalignedAllowed then LoadWritePC(MemU[address,4]); else LoadWritePC(MemA[address,4]); - if registers<13> == ???0??? then SP = SP + 4*BitCount(registers); - if registers<13> == ???1??? then SP = bits(32) UNKNOWN; + if registers<13> == '0' then SP = SP + 4*BitCount(registers); + if registers<13> == '1' then SP = bits(32) UNKNOWN; } #endif @@ -383,7 +383,7 @@ // which amounts to popping one reg from the full descending stacks. // if BitCount(register_list) < 2 then SEE LDM / LDMIA / LDMFD; - // if registers<13> == ???1??? && ArchVersion() >= 7 then UNPREDICTABLE; + // if registers<13> == '1' && ArchVersion() >= 7 then UNPREDICTABLE; if (BitIsSet(opcode, 13) && ArchVersion() >= ARMv7) return false; break; @@ -454,7 +454,7 @@ if (ConditionPassed()) { EncodingSpecificOperations(); - (result, carry, overflow) = AddWithCarry(SP, imm32, ???0???); + (result, carry, overflow) = AddWithCarry(SP, imm32, '0'); if d == 15 then ALUWritePC(result); // setflags is always FALSE here else @@ -772,7 +772,7 @@ break; case eEncodingA1: - // d = UInt(Rd); n = UInt(Rn); m = UInt(Rm); setflags = (S == ???1???); + // d = UInt(Rd); n = UInt(Rn); m = UInt(Rm); setflags = (S == '1'); d = Bits32 (opcode, 19, 16); n = Bits32 (opcode, 3, 0); m = Bits32 (opcode, 11, 8); @@ -994,8 +994,8 @@ address = if add then (base + imm32) else (base - imm32); data = MemU[address,4]; if t == 15 then - if address<1:0> == ???00??? then LoadWritePC(data); else UNPREDICTABLE; - elsif UnalignedSupport() || address<1:0> = ???00??? then + if address<1:0> == '00' then LoadWritePC(data); else UNPREDICTABLE; + elsif UnalignedSupport() || address<1:0> = '00' then R[t] = data; else // Can only apply before ARMv7 if CurrentInstrSet() == InstrSet_ARM then @@ -1086,7 +1086,7 @@ if (ConditionPassed()) { EncodingSpecificOperations(); - (result, carry, overflow) = AddWithCarry(SP, imm32, ???0???); + (result, carry, overflow) = AddWithCarry(SP, imm32, '0'); if d == 15 then // Can only occur for ARM encoding ALUWritePC(result); // setflags is always FALSE here else @@ -1112,7 +1112,7 @@ switch (encoding) { case eEncodingT1: - // d = UInt(Rd); setflags = FALSE; imm32 = ZeroExtend(imm8:???00???, 32); + // d = UInt(Rd); setflags = FALSE; imm32 = ZeroExtend(imm8:'00', 32); d = Bits32 (opcode, 10, 8); setflags = false; imm32 = (Bits32 (opcode, 7, 0) << 2); @@ -1120,7 +1120,7 @@ break; case eEncodingT2: - // d = 13; setflags = FALSE; imm32 = ZeroExtend(imm7:???00???, 32); + // d = 13; setflags = FALSE; imm32 = ZeroExtend(imm7:'00', 32); d = 13; setflags = false; imm32 = ThumbImm7Scaled(opcode); // imm32 = ZeroExtend(imm7:'00', 32) @@ -1162,7 +1162,7 @@ { EncodingSpecificOperations(); shifted = Shift(R[m], shift_t, shift_n, APSR.C); - (result, carry, overflow) = AddWithCarry(SP, shifted, ???0???); + (result, carry, overflow) = AddWithCarry(SP, shifted, '0'); if d == 15 then ALUWritePC(result); // setflags is always FALSE here else @@ -1320,7 +1320,7 @@ LR = next_instr_addr; else next_instr_addr = PC - 2; - LR = next_instr_addr<31:1> : ???1???; + LR = next_instr_addr<31:1> : '1'; BXWritePC(target); } #endif @@ -1427,7 +1427,7 @@ if (ConditionPassed()) { EncodingSpecificOperations(); - if JMCR.JE == ???0??? || CurrentInstrSet() == InstrSet_ThumbEE then + if JMCR.JE == '0' || CurrentInstrSet() == InstrSet_ThumbEE then BXWritePC(R[m]); else if JazelleAcceptsExecution() then @@ -1482,7 +1482,7 @@ if (ConditionPassed()) { EncodingSpecificOperations(); - (result, carry, overflow) = AddWithCarry(SP, NOT(imm32), ???1???); + (result, carry, overflow) = AddWithCarry(SP, NOT(imm32), '1'); if d == 15 then // Can only occur for ARM encoding ALUWritePC(result); // setflags is always FALSE here else @@ -1534,7 +1534,7 @@ if (ConditionPassed()) { EncodingSpecificOperations(); - (result, carry, overflow) = AddWithCarry(SP, NOT(imm32), ???1???); + (result, carry, overflow) = AddWithCarry(SP, NOT(imm32), '1'); if d == 15 then // Can only occur for ARM encoding ALUWritePC(result); // setflags is always FALSE here else @@ -1588,7 +1588,7 @@ if (ConditionPassed()) { EncodingSpecificOperations(); - (result, carry, overflow) = AddWithCarry(SP, NOT(imm32), ???1???); + (result, carry, overflow) = AddWithCarry(SP, NOT(imm32), '1'); if d == 15 then // Can only occur for ARM encoding ALUWritePC(result); // setflags is always FALSE here else @@ -1834,10 +1834,12 @@ context.type = EmulateInstruction::eContextPushRegisterOnStack; Register dwarf_reg; dwarf_reg.SetRegister (eRegisterKindDWARF, 0); - for (i=d; i; @@ -2259,9 +2263,9 @@ break; case eEncodingT3: - // if Rd == ???1111??? && S == ???1??? then SEE CMN (immediate); - // if Rn == ???1101??? then SEE ADD (SP plus immediate); - // d = UInt(Rd); n = UInt(Rn); setflags = (S == ???1???); imm32 = ThumbExpandImm(i:imm3:imm8); + // if Rd == '1111' && S == '1' then SEE CMN (immediate); + // if Rn == '1101' then SEE ADD (SP plus immediate); + // d = UInt(Rd); n = UInt(Rn); setflags = (S == '1'); imm32 = ThumbExpandImm(i:imm3:imm8); d = Bits32 (opcode, 11, 8); n = Bits32 (opcode, 19, 16); setflags = BitIsSet (opcode, 20); @@ -2275,8 +2279,8 @@ case eEncodingT4: { - // if Rn == ???1111??? then SEE ADR; - // if Rn == ???1101??? then SEE ADD (SP plus immediate); + // if Rn == '1111' then SEE ADR; + // if Rn == '1101' then SEE ADD (SP plus immediate); // d = UInt(Rd); n = UInt(Rn); setflags = FALSE; imm32 = ZeroExtend(i:imm3:imm8, 32); d = Bits32 (opcode, 11, 8); n = Bits32 (opcode, 19, 16); @@ -2300,7 +2304,7 @@ if (!success) return false; - //(result, carry, overflow) = AddWithCarry(R[n], imm32, ???0???); + //(result, carry, overflow) = AddWithCarry(R[n], imm32, '0'); AddWithCarryResult res = AddWithCarry (Rn, imm32, 0); Register reg_n; @@ -2937,7 +2941,11 @@ bool EmulateInstructionARM::EmulateShiftImm (const uint32_t opcode, const ARMEncoding encoding, ARM_ShifterType shift_type) { - assert(shift_type == SRType_ASR || shift_type == SRType_LSL || shift_type == SRType_LSR); + assert(shift_type == SRType_ASR + || shift_type == SRType_LSL + || shift_type == SRType_LSR + || shift_type == SRType_ROR + || shift_type == SRType_RRX); bool success = false; @@ -3115,7 +3123,7 @@ switch (encoding) { case eEncodingT1: - // n = UInt(Rn); registers = ???00000000???:register_list; wback = (registers == ???0???); + // n = UInt(Rn); registers = '00000000':register_list; wback = (registers == '0'); n = Bits32 (opcode, 10, 8); registers = Bits32 (opcode, 7, 0); registers = registers & 0x00ff; // Make sure the top 8 bits are zeros. @@ -3125,24 +3133,24 @@ return false; break; case eEncodingT2: - // if W == ???1??? && Rn == ???1101??? then SEE POP; - // n = UInt(Rn); registers = P:M:???0???:register_list; wback = (W == ???1???); + // if W == '1' && Rn == '1101' then SEE POP; + // n = UInt(Rn); registers = P:M:'0':register_list; wback = (W == '1'); n = Bits32 (opcode, 19, 16); registers = Bits32 (opcode, 15, 0); registers = registers & 0xdfff; // Make sure bit 13 is zero. wback = BitIsSet (opcode, 21); - // if n == 15 || BitCount(registers) < 2 || (P == ???1??? && M == ???1???) then UNPREDICTABLE; + // if n == 15 || BitCount(registers) < 2 || (P == '1' && M == '1') then UNPREDICTABLE; if ((n == 15) || (BitCount (registers) < 2) || (BitIsSet (opcode, 14) && BitIsSet (opcode, 15))) return false; - // if registers<15> == ???1??? && InITBlock() && !LastInITBlock() then UNPREDICTABLE; + // if registers<15> == '1' && InITBlock() && !LastInITBlock() then UNPREDICTABLE; if (BitIsSet (registers, 15) && InITBlock() && !LastInITBlock()) return false; - // if wback && registers == ???1??? then UNPREDICTABLE; + // if wback && registers == '1' then UNPREDICTABLE; if (wback && BitIsSet (registers, n)) return false; @@ -3222,9 +3230,9 @@ return true; } -// LDMDA loads multiple registers from consecutive memory locations using an address from a base registers. -// The consecutive memorty locations end at this address and the address just below the lowest of those locations -// can optionally be written back tot he base registers. +// LDMDA loads multiple registers from consecutive memory locations using an address from a base register. +// The consecutive memory locations end at this address and the address just below the lowest of those locations +// can optionally be written back to the base register. bool EmulateInstructionARM::EmulateLDMDA (const uint32_t opcode, const ARMEncoding encoding) { @@ -3235,14 +3243,14 @@ address = R[n] - 4*BitCount(registers) + 4; for i = 0 to 14 - if registers == ???1??? then + if registers == '1' then R[i] = MemA[address,4]; address = address + 4; - if registers<15> == ???1??? then + if registers<15> == '1' then LoadWritePC(MemA[address,4]); - if wback && registers == ???0??? then R[n] = R[n] - 4*BitCount(registers); - if wback && registers == ???1??? then R[n] = bits(32) UNKNOWN; + if wback && registers == '0' then R[n] = R[n] - 4*BitCount(registers); + if wback && registers == '1' then R[n] = bits(32) UNKNOWN; #endif bool success = false; @@ -3258,7 +3266,7 @@ switch (encoding) { case eEncodingA1: - // n = UInt(Rn); registers = register_list; wback = (W == ???1???); + // n = UInt(Rn); registers = register_list; wback = (W == '1'); n = Bits32 (opcode, 19, 16); registers = Bits32 (opcode, 15, 0); wback = BitIsSet (opcode, 21); @@ -3275,12 +3283,12 @@ // address = R[n] - 4*BitCount(registers) + 4; int32_t offset = 0; - addr_t address = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_r0 + n, 0, &success); + addr_t Rn = ReadCoreReg (n, &success); if (!success) return false; - address = address - (addr_byte_size * BitCount (registers)) + addr_byte_size; + addr_t address = Rn - (addr_byte_size * BitCount (registers)) + addr_byte_size; EmulateInstruction::Context context; context.type = EmulateInstruction::eContextRegisterPlusOffset; @@ -3291,11 +3299,11 @@ // for i = 0 to 14 for (int i = 0; i < 14; ++i) { - // if registers == ???1??? then + // if registers == '1' then if (BitIsSet (registers, i)) { // R[i] = MemA[address,4]; address = address + 4; - context.SetRegisterPlusOffset (dwarf_reg, offset); + context.SetRegisterPlusOffset (dwarf_reg, Rn - (address + offset)); uint32_t data = MemARead (context, address + offset, addr_byte_size, 0, &success); if (!success) return false; @@ -3305,7 +3313,7 @@ } } - // if registers<15> == ???1??? then + // if registers<15> == '1' then // LoadWritePC(MemA[address,4]); if (BitIsSet (registers, 15)) { @@ -3318,22 +3326,21 @@ return false; } - // if wback && registers == ???0??? then R[n] = R[n] - 4*BitCount(registers); + // if wback && registers == '0' then R[n] = R[n] - 4*BitCount(registers); if (wback && BitIsClear (registers, n)) { - addr_t addr = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_r0 + n, 0, &success); if (!success) return false; offset = (addr_byte_size * BitCount (registers)) * -1; context.type = EmulateInstruction::eContextAdjustBaseRegister; context.SetImmediateSigned (offset); - addr = addr + offset; + addr_t addr = Rn + offset; if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_r0 + n, addr)) return false; } - // if wback && registers == ???1??? then R[n] = bits(32) UNKNOWN; + // if wback && registers == '1' then R[n] = bits(32) UNKNOWN; if (wback && BitIsSet (registers, n)) return WriteBits32Unknown (n); } @@ -3353,13 +3360,13 @@ address = R[n] - 4*BitCount(registers); for i = 0 to 14 - if registers == ???1??? then + if registers == '1' then R[i] = MemA[address,4]; address = address + 4; - if registers<15> == ???1??? then + if registers<15> == '1' then LoadWritePC(MemA[address,4]); - if wback && registers == ???0??? then R[n] = R[n] - 4*BitCount(registers); - if wback && registers == ???1??? then R[n] = bits(32) UNKNOWN; // Only possible for encoding A1 + if wback && registers == '0' then R[n] = R[n] - 4*BitCount(registers); + if wback && registers == '1' then R[n] = bits(32) UNKNOWN; // Only possible for encoding A1 #endif bool success = false; @@ -3373,30 +3380,30 @@ switch (encoding) { case eEncodingT1: - // n = UInt(Rn); registers = P:M:???0???:register_list; wback = (W == ???1???); + // n = UInt(Rn); registers = P:M:'0':register_list; wback = (W == '1'); n = Bits32 (opcode, 19, 16); registers = Bits32 (opcode, 15, 0); registers = registers & 0xdfff; // Make sure bit 13 is a zero. wback = BitIsSet (opcode, 21); - // if n == 15 || BitCount(registers) < 2 || (P == ???1??? && M == ???1???) then UNPREDICTABLE; + // if n == 15 || BitCount(registers) < 2 || (P == '1' && M == '1') then UNPREDICTABLE; if ((n == 15) || (BitCount (registers) < 2) || (BitIsSet (opcode, 14) && BitIsSet (opcode, 15))) return false; - // if registers<15> == ???1??? && InITBlock() && !LastInITBlock() then UNPREDICTABLE; + // if registers<15> == '1' && InITBlock() && !LastInITBlock() then UNPREDICTABLE; if (BitIsSet (registers, 15) && InITBlock() && !LastInITBlock()) return false; - // if wback && registers == ???1??? then UNPREDICTABLE; + // if wback && registers == '1' then UNPREDICTABLE; if (wback && BitIsSet (registers, n)) return false; break; case eEncodingA1: - // n = UInt(Rn); registers = register_list; wback = (W == ???1???); + // n = UInt(Rn); registers = register_list; wback = (W == '1'); n = Bits32 (opcode, 19, 16); registers = Bits32 (opcode, 15, 0); wback = BitIsSet (opcode, 21); @@ -3414,24 +3421,24 @@ // address = R[n] - 4*BitCount(registers); int32_t offset = 0; - addr_t address = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_r0 + n, 0, &success); + addr_t Rn = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_r0 + n, 0, &success); if (!success) return false; - address = address - (addr_byte_size * BitCount (registers)); + addr_t address = Rn - (addr_byte_size * BitCount (registers)); EmulateInstruction::Context context; context.type = EmulateInstruction::eContextRegisterPlusOffset; Register dwarf_reg; dwarf_reg.SetRegister (eRegisterKindDWARF, dwarf_r0 + n); - context.SetRegisterPlusOffset (dwarf_reg, offset); + context.SetRegisterPlusOffset (dwarf_reg, Rn - address); for (int i = 0; i < 14; ++i) { if (BitIsSet (registers, i)) { // R[i] = MemA[address,4]; address = address + 4; - context.SetRegisterPlusOffset (dwarf_reg, offset); + context.SetRegisterPlusOffset (dwarf_reg, Rn - (address + offset)); uint32_t data = MemARead (context, address + offset, addr_byte_size, 0, &success); if (!success) return false; @@ -3443,7 +3450,7 @@ } } - // if registers<15> == ???1??? then + // if registers<15> == '1' then // LoadWritePC(MemA[address,4]); if (BitIsSet (registers, 15)) { @@ -3456,22 +3463,21 @@ return false; } - // if wback && registers == ???0??? then R[n] = R[n] - 4*BitCount(registers); + // if wback && registers == '0' then R[n] = R[n] - 4*BitCount(registers); if (wback && BitIsClear (registers, n)) { - addr_t addr = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_r0 + n, 0, &success); if (!success) return false; offset = (addr_byte_size * BitCount (registers)) * -1; context.type = EmulateInstruction::eContextAdjustBaseRegister; context.SetImmediateSigned (offset); - addr = addr + offset; + addr_t addr = Rn + offset; if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_r0 + n, addr)) return false; } - // if wback && registers == ???1??? then R[n] = bits(32) UNKNOWN; // Only possible for encoding A1 + // if wback && registers == '1' then R[n] = bits(32) UNKNOWN; // Only possible for encoding A1 if (wback && BitIsSet (registers, n)) return WriteBits32Unknown (n); } @@ -3490,13 +3496,13 @@ address = R[n] + 4; for i = 0 to 14 - if registers == ???1??? then + if registers == '1' then R[i] = MemA[address,4]; address = address + 4; - if registers<15> == ???1??? then + if registers<15> == '1' then LoadWritePC(MemA[address,4]); - if wback && registers == ???0??? then R[n] = R[n] + 4*BitCount(registers); - if wback && registers == ???1??? then R[n] = bits(32) UNKNOWN; + if wback && registers == '0' then R[n] = R[n] + 4*BitCount(registers); + if wback && registers == '1' then R[n] = bits(32) UNKNOWN; #endif bool success = false; @@ -3510,7 +3516,7 @@ switch (encoding) { case eEncodingA1: - // n = UInt(Rn); registers = register_list; wback = (W == ???1???); + // n = UInt(Rn); registers = register_list; wback = (W == '1'); n = Bits32 (opcode, 19, 16); registers = Bits32 (opcode, 15, 0); wback = BitIsSet (opcode, 21); @@ -3526,12 +3532,12 @@ // address = R[n] + 4; int32_t offset = 0; - addr_t address = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_r0 + n, 0, &success); + addr_t Rn = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_r0 + n, 0, &success); if (!success) return false; - address = address + addr_byte_size; + addr_t address = Rn + addr_byte_size; EmulateInstruction::Context context; context.type = EmulateInstruction::eContextRegisterPlusOffset; @@ -3545,7 +3551,7 @@ { // R[i] = MemA[address,4]; address = address + 4; - context.SetRegisterPlusOffset (dwarf_reg, offset); + context.SetRegisterPlusOffset (dwarf_reg, offset + addr_byte_size); uint32_t data = MemARead (context, address + offset, addr_byte_size, 0, &success); if (!success) return false; @@ -3557,7 +3563,7 @@ } } - // if registers<15> == ???1??? then + // if registers<15> == '1' then // LoadWritePC(MemA[address,4]); if (BitIsSet (registers, 15)) { @@ -3570,22 +3576,21 @@ return false; } - // if wback && registers == ???0??? then R[n] = R[n] + 4*BitCount(registers); + // if wback && registers == '0' then R[n] = R[n] + 4*BitCount(registers); if (wback && BitIsClear (registers, n)) { - addr_t addr = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_r0 + n, 0, &success); if (!success) return false; offset = addr_byte_size * BitCount (registers); context.type = EmulateInstruction::eContextAdjustBaseRegister; context.SetImmediateSigned (offset); - addr = addr + offset; + addr_t addr = Rn + offset; if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_r0 + n, addr)) return false; } - // if wback && registers == ???1??? then R[n] = bits(32) UNKNOWN; // Only possible for encoding A1 + // if wback && registers == '1' then R[n] = bits(32) UNKNOWN; // Only possible for encoding A1 if (wback && BitIsSet (registers, n)) return WriteBits32Unknown (n); } @@ -3639,7 +3644,7 @@ break; case eEncodingT2: - // t = UInt(Rt); n = 13; imm32 = ZeroExtend(imm8:???00???, 32); + // t = UInt(Rt); n = 13; imm32 = ZeroExtend(imm8:'00', 32); Rt = Bits32 (opcode, 10, 8); Rn = 13; imm32 = Bits32 (opcode, 7, 0) << 2; @@ -3652,7 +3657,7 @@ break; case eEncodingT3: - // if Rn == ???1111??? then SEE LDR (literal); + // if Rn == '1111' then SEE LDR (literal); // t = UInt(Rt); n = UInt(Rn); imm32 = ZeroExtend(imm12, 32); Rt = Bits32 (opcode, 15, 12); Rn = Bits32 (opcode, 19, 16); @@ -3670,10 +3675,10 @@ break; case eEncodingT4: - // if Rn == ???1111??? then SEE LDR (literal); - // if P == ???1??? && U == ???1??? && W == ???0??? then SEE LDRT; - // if Rn == ???1101??? && P == ???0??? && U == ???1??? && W == ???1??? && imm8 == ???00000100??? then SEE POP; - // if P == ???0??? && W == ???0??? then UNDEFINED; + // if Rn == '1111' then SEE LDR (literal); + // if P == '1' && U == '1' && W == '0' then SEE LDRT; + // if Rn == '1101' && P == '0' && U == '1' && W == '1' && imm8 == '00000100' then SEE POP; + // if P == '0' && W == '0' then UNDEFINED; if (BitIsClear (opcode, 10) && BitIsClear (opcode, 8)) return false; @@ -3682,7 +3687,7 @@ Rn = Bits32 (opcode, 19, 16); imm32 = Bits32 (opcode, 7, 0); - // index = (P == ???1???); add = (U == ???1???); wback = (W == ???1???); + // index = (P == '1'); add = (U == '1'); wback = (W == '1'); index = BitIsSet (opcode, 10); add = BitIsSet (opcode, 9); wback = BitIsSet (opcode, 8); @@ -3761,14 +3766,14 @@ address = R[n]; for i = 0 to 14 - if registers == ???1??? then + if registers == '1' then if i == n && wback && i != LowestSetBit(registers) then MemA[address,4] = bits(32) UNKNOWN; // Only possible for encodings T1 and A1 else MemA[address,4] = R[i]; address = address + 4; - if registers<15> == ???1??? then // Only possible for encoding A1 + if registers<15> == '1' then // Only possible for encoding A1 MemA[address,4] = PCStoreValue(); if wback then R[n] = R[n] + 4*BitCount(registers); #endif @@ -3786,7 +3791,7 @@ switch (encoding) { case eEncodingT1: - // n = UInt(Rn); registers = ???00000000???:register_list; wback = TRUE; + // n = UInt(Rn); registers = '00000000':register_list; wback = TRUE; n = Bits32 (opcode, 10, 8); registers = Bits32 (opcode, 7, 0); registers = registers & 0x00ff; // Make sure the top 8 bits are zeros. @@ -3799,7 +3804,7 @@ break; case eEncodingT2: - // n = UInt(Rn); registers = ???0???:M:???0???:register_list; wback = (W == ???1???); + // n = UInt(Rn); registers = '0':M:'0':register_list; wback = (W == '1'); n = Bits32 (opcode, 19, 16); registers = Bits32 (opcode, 15, 0); registers = registers & 0x5fff; // Make sure bits 15 & 13 are zeros. @@ -3809,14 +3814,14 @@ if ((n == 15) || (BitCount (registers) < 2)) return false; - // if wback && registers == ???1??? then UNPREDICTABLE; + // if wback && registers == '1' then UNPREDICTABLE; if (wback && BitIsSet (registers, n)) return false; break; case eEncodingA1: - // n = UInt(Rn); registers = register_list; wback = (W == ???1???); + // n = UInt(Rn); registers = register_list; wback = (W == '1'); n = Bits32 (opcode, 19, 16); registers = Bits32 (opcode, 15, 0); wback = BitIsSet (opcode, 21); @@ -3843,10 +3848,10 @@ base_reg.SetRegister (eRegisterKindDWARF, dwarf_r0 + n); // for i = 0 to 14 + int lowest_set_bit = 14; for (int i = 0; i < 14; ++i) { - int lowest_set_bit = 14; - // if registers == ???1??? then + // if registers == '1' then if (BitIsSet (registers, i)) { if (i < lowest_set_bit) @@ -3874,7 +3879,7 @@ } } - // if registers<15> == ???1??? then // Only possible for encoding A1 + // if registers<15> == '1' then // Only possible for encoding A1 // MemA[address,4] = PCStoreValue(); if (BitIsSet (registers, 15)) { @@ -3915,14 +3920,14 @@ address = R[n] - 4*BitCount(registers) + 4; for i = 0 to 14 - if registers == ???1??? then + if registers == '1' then if i == n && wback && i != LowestSetBit(registers) then MemA[address,4] = bits(32) UNKNOWN; else MemA[address,4] = R[i]; address = address + 4; - if registers<15> == ???1??? then + if registers<15> == '1' then MemA[address,4] = PCStoreValue(); if wback then R[n] = R[n] - 4*BitCount(registers); @@ -3941,7 +3946,7 @@ switch (encoding) { case eEncodingA1: - // n = UInt(Rn); registers = register_list; wback = (W == ???1???); + // n = UInt(Rn); registers = register_list; wback = (W == '1'); n = Bits32 (opcode, 19, 16); registers = Bits32 (opcode, 15, 0); wback = BitIsSet (opcode, 21); @@ -3956,11 +3961,11 @@ // address = R[n] - 4*BitCount(registers) + 4; int32_t offset = 0; - addr_t address = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_r0 + n, 0, &success); + addr_t Rn = ReadCoreReg (n, &success); if (!success) return false; - address = address - (addr_byte_size * BitCount (registers)) + 4; + addr_t address = Rn - (addr_byte_size * BitCount (registers)) + 4; EmulateInstruction::Context context; context.type = EmulateInstruction::eContextRegisterStore; @@ -3968,10 +3973,10 @@ base_reg.SetRegister (eRegisterKindDWARF, dwarf_r0 + n); // for i = 0 to 14 + int lowest_bit_set = 14; for (int i = 0; i < 14; ++i) { - int lowest_bit_set = 14; - // if registers == ???1??? then + // if registers == '1' then if (BitIsSet (registers, i)) { if (i < lowest_bit_set) @@ -3989,7 +3994,7 @@ Register data_reg; data_reg.SetRegister (eRegisterKindDWARF, dwarf_r0 + i); - context.SetRegisterToRegisterPlusOffset (data_reg, base_reg, offset); + context.SetRegisterToRegisterPlusOffset (data_reg, base_reg, Rn - (address + offset)); if (!MemAWrite (context, address + offset, data, addr_byte_size)) return false; } @@ -3999,7 +4004,7 @@ } } - // if registers<15> == ???1??? then + // if registers<15> == '1' then // MemA[address,4] = PCStoreValue(); if (BitIsSet (registers, 15)) { @@ -4020,7 +4025,7 @@ offset = (addr_byte_size * BitCount (registers)) * -1; context.type = EmulateInstruction::eContextAdjustBaseRegister; context.SetImmediateSigned (offset); - addr_t data = address + offset; + addr_t data = Rn + offset; if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_r0 + n, data)) return false; } @@ -4040,14 +4045,14 @@ address = R[n] - 4*BitCount(registers); for i = 0 to 14 - if registers == ???1??? then + if registers == '1' then if i == n && wback && i != LowestSetBit(registers) then MemA[address,4] = bits(32) UNKNOWN; // Only possible for encoding A1 else MemA[address,4] = R[i]; address = address + 4; - if registers<15> == ???1??? then // Only possible for encoding A1 + if registers<15> == '1' then // Only possible for encoding A1 MemA[address,4] = PCStoreValue(); if wback then R[n] = R[n] - 4*BitCount(registers); @@ -4067,12 +4072,12 @@ switch (encoding) { case eEncodingT1: - // if W == ???1??? && Rn == ???1101??? then SEE PUSH; + // if W == '1' && Rn == '1101' then SEE PUSH; if ((BitIsSet (opcode, 21)) && (Bits32 (opcode, 19, 16) == 13)) { // See PUSH } - // n = UInt(Rn); registers = ???0???:M:???0???:register_list; wback = (W == ???1???); + // n = UInt(Rn); registers = '0':M:'0':register_list; wback = (W == '1'); n = Bits32 (opcode, 19, 16); registers = Bits32 (opcode, 15, 0); registers = registers & 0x5fff; // Make sure bits 15 & 13 are zeros. @@ -4080,18 +4085,18 @@ // if n == 15 || BitCount(registers) < 2 then UNPREDICTABLE; if ((n == 15) || BitCount (registers) < 2) return false; - // if wback && registers == ???1??? then UNPREDICTABLE; + // if wback && registers == '1' then UNPREDICTABLE; if (wback && BitIsSet (registers, n)) return false; break; case eEncodingA1: - // if W == ???1??? && Rn == ???1101??? && BitCount(register_list) >= 2 then SEE PUSH; + // if W == '1' && Rn == '1101??? && BitCount(register_list) >= 2 then SEE PUSH; if (BitIsSet (opcode, 21) && (Bits32 (opcode, 19, 16) == 13) && BitCount (Bits32 (opcode, 15, 0)) >= 2) { // See Push } - // n = UInt(Rn); registers = register_list; wback = (W == ???1???); + // n = UInt(Rn); registers = register_list; wback = (W == '1'); n = Bits32 (opcode, 19, 16); registers = Bits32 (opcode, 15, 0); wback = BitIsSet (opcode, 21); @@ -4107,11 +4112,11 @@ // address = R[n] - 4*BitCount(registers); int32_t offset = 0; - addr_t address = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_r0 + n, 0, &success); + addr_t Rn = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_r0 + n, 0, &success); if (!success) return false; - address = address - (addr_byte_size * BitCount (registers)); + addr_t address = Rn - (addr_byte_size * BitCount (registers)); EmulateInstruction::Context context; context.type = EmulateInstruction::eContextRegisterStore; @@ -4119,10 +4124,10 @@ base_reg.SetRegister (eRegisterKindDWARF, dwarf_r0 + n); // for i = 0 to 14 + uint32_t lowest_set_bit = 14; for (int i = 0; i < 14; ++i) { - uint32_t lowest_set_bit = 14; - // if registers == ???1??? then + // if registers == '1' then if (BitIsSet (registers, i)) { if (i < lowest_set_bit) @@ -4140,7 +4145,7 @@ Register data_reg; data_reg.SetRegister (eRegisterKindDWARF, dwarf_r0 + i); - context.SetRegisterToRegisterPlusOffset (data_reg, base_reg, offset); + context.SetRegisterToRegisterPlusOffset (data_reg, base_reg, Rn - (address + offset)); if (!MemAWrite (context, address + offset, data, addr_byte_size)) return false; } @@ -4150,7 +4155,7 @@ } } - // if registers<15> == ???1??? then // Only possible for encoding A1 + // if registers<15> == '1' then // Only possible for encoding A1 // MemA[address,4] = PCStoreValue(); if (BitIsSet (registers, 15)) { @@ -4171,7 +4176,7 @@ offset = (addr_byte_size * BitCount (registers)) * -1; context.type = EmulateInstruction::eContextAdjustBaseRegister; context.SetImmediateSigned (offset); - addr_t data = address + offset; + addr_t data = Rn + offset; if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_r0 + n, data)) return false; } @@ -4191,14 +4196,14 @@ address = R[n] + 4; for i = 0 to 14 - if registers == ???1??? then + if registers == '1' then if i == n && wback && i != LowestSetBit(registers) then MemA[address,4] = bits(32) UNKNOWN; else MemA[address,4] = R[i]; address = address + 4; - if registers<15> == ???1??? then + if registers<15> == '1' then MemA[address,4] = PCStoreValue(); if wback then R[n] = R[n] + 4*BitCount(registers); @@ -4217,7 +4222,7 @@ switch (encoding) { case eEncodingA1: - // n = UInt(Rn); registers = register_list; wback = (W == ???1???); + // n = UInt(Rn); registers = register_list; wback = (W == '1'); n = Bits32 (opcode, 19, 16); registers = Bits32 (opcode, 15, 0); wback = BitIsSet (opcode, 21); @@ -4232,11 +4237,11 @@ // address = R[n] + 4; int32_t offset = 0; - addr_t address = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_r0 + n, 0, &success); + addr_t Rn = ReadCoreReg (n, &success); if (!success) return false; - address = address + addr_byte_size; + addr_t address = Rn + addr_byte_size; EmulateInstruction::Context context; context.type = EmulateInstruction::eContextRegisterStore; @@ -4247,7 +4252,7 @@ // for i = 0 to 14 for (int i = 0; i < 14; ++i) { - // if registers == ???1??? then + // if registers == '1' then if (BitIsSet (registers, i)) { if (i < lowest_set_bit) @@ -4266,7 +4271,7 @@ Register data_reg; data_reg.SetRegister (eRegisterKindDWARF, dwarf_r0 + i); - context.SetRegisterToRegisterPlusOffset (data_reg, base_reg, offset); + context.SetRegisterToRegisterPlusOffset (data_reg, base_reg, offset + addr_byte_size); if (!MemAWrite (context, address + offset, data, addr_byte_size)) return false; } @@ -4276,7 +4281,7 @@ } } - // if registers<15> == ???1??? then + // if registers<15> == '1' then // MemA[address,4] = PCStoreValue(); if (BitIsSet (registers, 15)) { @@ -4297,7 +4302,7 @@ offset = addr_byte_size * BitCount (registers); context.type = EmulateInstruction::eContextAdjustBaseRegister; context.SetImmediateSigned (offset); - addr_t data = address + offset; + addr_t data = Rn + offset; if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_r0 + n, data)) return false; } @@ -4315,7 +4320,7 @@ EncodingSpecificOperations(); NullCheckIfThumbEE(n); offset_addr = if add then (R[n] + imm32) else (R[n] - imm32); address = if index then offset_addr else R[n]; - if UnalignedSupport() || address<1:0> == ???00??? then + if UnalignedSupport() || address<1:0> == '00' then MemU[address,4] = R[t]; else // Can only occur before ARMv7 MemU[address,4] = bits(32) UNKNOWN; @@ -4338,7 +4343,7 @@ switch (encoding) { case eEncodingT1: - // t = UInt(Rt); n = UInt(Rn); imm32 = ZeroExtend(imm5:???00???, 32); + // t = UInt(Rt); n = UInt(Rn); imm32 = ZeroExtend(imm5:'00', 32); t = Bits32 (opcode, 2, 0); n = Bits32 (opcode, 5, 3); imm32 = Bits32 (opcode, 10, 6) << 2; @@ -4350,7 +4355,7 @@ break; case eEncodingT2: - // t = UInt(Rt); n = 13; imm32 = ZeroExtend(imm8:???00???, 32); + // t = UInt(Rt); n = 13; imm32 = ZeroExtend(imm8:'00', 32); t = Bits32 (opcode, 10, 8); n = 13; imm32 = Bits32 (opcode, 7, 0) << 2; @@ -4362,7 +4367,7 @@ break; case eEncodingT3: - // if Rn == ???1111??? then UNDEFINED; + // if Rn == '1111' then UNDEFINED; if (Bits32 (opcode, 19, 16) == 15) return false; @@ -4382,9 +4387,9 @@ break; case eEncodingT4: - // if P == ???1??? && U == ???1??? && W == ???0??? then SEE STRT; - // if Rn == ???1101??? && P == ???1??? && U == ???0??? && W == ???1??? && imm8 == ???00000100??? then SEE PUSH; - // if Rn == ???1111??? || (P == ???0??? && W == ???0???) then UNDEFINED; + // if P == '1' && U == '1' && W == '0' then SEE STRT; + // if Rn == '1101' && P == '1' && U == '0' && W == '1' && imm8 == '00000100' then SEE PUSH; + // if Rn == '1111' || (P == '0' && W == '0') then UNDEFINED; if ((Bits32 (opcode, 19, 16) == 15) || (BitIsClear (opcode, 10) && BitIsClear (opcode, 8))) return false; @@ -4394,7 +4399,7 @@ n = Bits32 (opcode, 19, 16); imm32 = Bits32 (opcode, 7, 0); - // index = (P == ???1???); add = (U == ???1???); wback = (W == ???1???); + // index = (P == '1'); add = (U == '1'); wback = (W == '1'); index = BitIsSet (opcode, 10); add = BitIsSet (opcode, 9); wback = BitIsSet (opcode, 8); @@ -4432,7 +4437,7 @@ Register base_reg; base_reg.SetRegister (eRegisterKindDWARF, dwarf_r0 + n); - // if UnalignedSupport() || address<1:0> == ???00??? then + // if UnalignedSupport() || address<1:0> == '00' then if (UnalignedSupport () || (BitIsClear (address, 1) && BitIsClear (address, 0))) { // MemU[address,4] = R[t]; @@ -4480,7 +4485,7 @@ data = PCStoreValue(); else data = R[t]; - if UnalignedSupport() || address<1:0> == ???00??? || CurrentInstrSet() == InstrSet_ARM then + if UnalignedSupport() || address<1:0> == '00' || CurrentInstrSet() == InstrSet_ARM then MemU[address,4] = data; else // Can only occur before ARMv7 MemU[address,4] = bits(32) UNKNOWN; @@ -4523,7 +4528,7 @@ break; case eEncodingT2: - // if Rn == ???1111??? then UNDEFINED; + // if Rn == '1111' then UNDEFINED; if (Bits32 (opcode, 19, 16) == 15) return false; @@ -4548,13 +4553,13 @@ case eEncodingA1: { - // if P == ???0??? && W == ???1??? then SEE STRT; + // if P == '0' && W == '1' then SEE STRT; // t = UInt(Rt); n = UInt(Rn); m = UInt(Rm); t = Bits32 (opcode, 15, 12); n = Bits32 (opcode, 19, 16); m = Bits32 (opcode, 3, 0); - // index = (P == ???1???); add = (U == ???1???); wback = (P == ???0???) || (W == ???1???); + // index = (P == '1'); add = (U == '1'); wback = (P == '0') || (W == '1'); index = BitIsSet (opcode, 24); add = BitIsSet (opcode, 23); wback = (BitIsClear (opcode, 24) || BitIsSet (opcode, 21)); @@ -4620,7 +4625,7 @@ EmulateInstruction::Context context; context.type = eContextRegisterStore; - // if UnalignedSupport() || address<1:0> == ???00??? || CurrentInstrSet() == InstrSet_ARM then + // if UnalignedSupport() || address<1:0> == '00' || CurrentInstrSet() == InstrSet_ARM then if (UnalignedSupport () || (BitIsClear (address, 1) && BitIsClear (address, 0)) || CurrentInstrSet() == eModeARM) @@ -4694,7 +4699,7 @@ break; case eEncodingT2: - // if Rn == ???1111??? then UNDEFINED; + // if Rn == '1111' then UNDEFINED; if (Bits32 (opcode, 19, 16) == 15) return false; @@ -4714,8 +4719,8 @@ break; case eEncodingT3: - // if P == ???1??? && U == ???1??? && W == ???0??? then SEE STRBT; - // if Rn == ???1111??? || (P == ???0??? && W == ???0???) then UNDEFINED; + // if P == '1' && U == '1' && W == '0' then SEE STRBT; + // if Rn == '1111' || (P == '0' && W == '0') then UNDEFINED; if (Bits32 (opcode, 19, 16) == 15) return false; @@ -4724,7 +4729,7 @@ n = Bits32 (opcode, 19, 16); imm32 = Bits32 (opcode, 7, 0); - // index = (P == ???1???); add = (U == ???1???); wback = (W == ???1???); + // index = (P == '1'); add = (U == '1'); wback = (W == '1'); index = BitIsSet (opcode, 10); add = BitIsSet (opcode, 9); wback = BitIsSet (opcode, 8); @@ -4801,7 +4806,7 @@ offset = Shift(R[m], shift_t, shift_n, APSR.C); offset_addr = if add then (R[n] + offset) else (R[n] - offset); address = if index then offset_addr else R[n]; - if UnalignedSupport() || address<0> == ???0??? then + if UnalignedSupport() || address<0> == '0' then MemU[address,2] = R[t]<15:0>; else // Can only occur before ARMv7 MemU[address,2] = bits(16) UNKNOWN; @@ -4843,7 +4848,7 @@ break; case eEncodingT2: - // if Rn == ???1111??? then UNDEFINED; + // if Rn == '1111' then UNDEFINED; // t = UInt(Rt); n = UInt(Rn); m = UInt(Rm); t = Bits32 (opcode, 15, 12); n = Bits32 (opcode, 19, 16); @@ -4867,13 +4872,13 @@ break; case eEncodingA1: - // if P == ???0??? && W == ???1??? then SEE STRHT; + // if P == '0' && W == '1' then SEE STRHT; // t = UInt(Rt); n = UInt(Rn); m = UInt(Rm); t = Bits32 (opcode, 15, 12); n = Bits32 (opcode, 19, 16); m = Bits32 (opcode, 3, 0); - // index = (P == ???1???); add = (U == ???1???); wback = (P == ???0???) || (W == ???1???); + // index = (P == '1'); add = (U == '1'); wback = (P == '0') || (W == '1'); index = BitIsSet (opcode, 24); add = BitIsSet (opcode, 23); wback = (BitIsClear (opcode, 24) || BitIsSet (opcode, 21)); @@ -4928,7 +4933,7 @@ Register offset_reg; offset_reg.SetRegister (eRegisterKindDWARF, dwarf_r0 + m); - // if UnalignedSupport() || address<0> == ???0??? then + // if UnalignedSupport() || address<0> == '0' then if (UnalignedSupport() || BitIsClear (address, 0)) { // MemU[address,2] = R[t]<15:0>; @@ -5393,7 +5398,7 @@ Rn = Bits32(opcode, 19, 16); setflags = BitIsSet(opcode, 20); imm32 = ARMExpandImm_C(opcode, APSR_C, carry); // (imm32, carry) = ARMExpandImm(imm12, APSR.C) - // if Rd == ???1111??? && S == ???1??? then SEE SUBS PC, LR and related instructions; + // if Rd == '1111' && S == '1' then SEE SUBS PC, LR and related instructions; // TODO: Emulate SUBS PC, LR and related instructions. if (Rd == 15 && setflags) return false; @@ -5475,7 +5480,7 @@ Rm = Bits32(opcode, 3, 0); setflags = BitIsSet(opcode, 20); shift_n = DecodeImmShiftARM(opcode, shift_t); - // if Rd == ???1111??? && S == ???1??? then SEE SUBS PC, LR and related instructions; + // if Rd == '1111' && S == '1' then SEE SUBS PC, LR and related instructions; // TODO: Emulate SUBS PC, LR and related instructions. if (Rd == 15 && setflags) return false; @@ -5520,8 +5525,8 @@ data = MemU[address,4]; if wback then R[n] = offset_addr; if t == 15 then - if address<1:0> == ???00??? then LoadWritePC(data); else UNPREDICTABLE; - elsif UnalignedSupport() || address<1:0> = ???00??? then + if address<1:0> == '00' then LoadWritePC(data); else UNPREDICTABLE; + elsif UnalignedSupport() || address<1:0> = '00' then R[t] = data; else // Can only apply before ARMv7 R[t] = ROR(data, 8*UInt(address<1:0>)); @@ -5543,18 +5548,18 @@ switch (encoding) { case eEncodingA1: - // if Rn == ???1111??? then SEE LDR (literal); - // if P == ???0??? && W == ???1??? then SEE LDRT; - // if Rn == ???1101??? && P == ???0??? && U == ???1??? && W == ???0??? && imm12 == ???000000000100??? then SEE POP; + // if Rn == '1111' then SEE LDR (literal); + // if P == '0' && W == '1' then SEE LDRT; + // if Rn == '1101' && P == '0' && U == '1' && W == '0' && imm12 == '000000000100' then SEE POP; // t == UInt(Rt); n = UInt(Rn); imm32 = ZeroExtend(imm12, 32); t = Bits32 (opcode, 15, 12); n = Bits32 (opcode, 19, 16); imm32 = Bits32 (opcode, 11, 0); - // index = (P == ???1???); add = (U == ???1???); wback = (P == ???0???) || (W == ???1???); - index = BitIsSet (opcode, 24); - add = BitIsSet (opcode, 23); - wback = (BitIsClear (opcode, 24) || BitIsSet (opcode, 21)); + // index = (P == '1'); add = (U == '1'); wback = (P == '0') || (W == '1'); + index = BitIsSet (opcode, 24); + add = BitIsSet (opcode, 23); + wback = (BitIsClear (opcode, 24) || BitIsSet (opcode, 21)); // if wback && n == t then UNPREDICTABLE; if (wback && (n == t)) @@ -5609,7 +5614,7 @@ // if t == 15 then if (t == 15) { - // if address<1:0> == ???00??? then LoadWritePC(data); else UNPREDICTABLE; + // if address<1:0> == '00' then LoadWritePC(data); else UNPREDICTABLE; if (BitIsClear (address, 1) && BitIsClear (address, 0)) { // LoadWritePC (data); @@ -5620,7 +5625,7 @@ else return false; } - // elsif UnalignedSupport() || address<1:0> = ???00??? then + // elsif UnalignedSupport() || address<1:0> = '00' then else if (UnalignedSupport() || (BitIsClear (address, 1) && BitIsClear (address, 0))) { // R[t] = data; @@ -5658,8 +5663,8 @@ data = MemU[address,4]; if wback then R[n] = offset_addr; if t == 15 then - if address<1:0> == ???00??? then LoadWritePC(data); else UNPREDICTABLE; - elsif UnalignedSupport() || address<1:0> = ???00??? then + if address<1:0> == '00' then LoadWritePC(data); else UNPREDICTABLE; + elsif UnalignedSupport() || address<1:0> = '00' then R[t] = data; else // Can only apply before ARMv7 if CurrentInstrSet() == InstrSet_ARM then @@ -5704,7 +5709,7 @@ break; case eEncodingT2: - // if Rn == ???1111??? then SEE LDR (literal); + // if Rn == '1111' then SEE LDR (literal); // t = UInt(Rt); n = UInt(Rn); m = UInt(Rm); t = Bits32 (opcode, 15, 12); n = Bits32 (opcode, 19, 16); @@ -5731,13 +5736,13 @@ case eEncodingA1: { - // if P == ???0??? && W == ???1??? then SEE LDRT; + // if P == '0' && W == '1' then SEE LDRT; // t = UInt(Rt); n = UInt(Rn); m = UInt(Rm); t = Bits32 (opcode, 15, 12); n = Bits32 (opcode, 19, 16); m = Bits32 (opcode, 3, 0); - // index = (P == ???1???); add = (U == ???1???); wback = (P == ???0???) || (W == ???1???); + // index = (P == '1'); add = (U == '1'); wback = (P == '0') || (W == '1'); index = BitIsSet (opcode, 24); add = BitIsSet (opcode, 23); wback = (BitIsClear (opcode, 24) || BitIsSet (opcode, 21)); @@ -5812,7 +5817,7 @@ // if t == 15 then if (t == 15) { - // if address<1:0> == ???00??? then LoadWritePC(data); else UNPREDICTABLE; + // if address<1:0> == '00' then LoadWritePC(data); else UNPREDICTABLE; if (BitIsClear (address, 1) && BitIsClear (address, 0)) { context.type = eContextRegisterLoad; @@ -5822,7 +5827,7 @@ else return false; } - // elsif UnalignedSupport() || address<1:0> = ???00??? then + // elsif UnalignedSupport() || address<1:0> = '00' then else if (UnalignedSupport () || (BitIsClear (address, 1) && BitIsClear (address, 0))) { // R[t] = data; @@ -5894,8 +5899,8 @@ break; case eEncodingT2: - // if Rt == ???1111??? then SEE PLD; - // if Rn == ???1111??? then SEE LDRB (literal); + // if Rt == '1111' then SEE PLD; + // if Rn == '1111' then SEE LDRB (literal); // t = UInt(Rt); n = UInt(Rn); imm32 = ZeroExtend(imm12, 32); t = Bits32 (opcode, 15, 12); n = Bits32 (opcode, 19, 16); @@ -5913,10 +5918,10 @@ break; case eEncodingT3: - // if Rt == ???1111??? && P == ???1??? && U == ???0??? && W == ???0??? then SEE PLD; - // if Rn == ???1111??? then SEE LDRB (literal); - // if P == ???1??? && U == ???1??? && W == ???0??? then SEE LDRBT; - // if P == ???0??? && W == ???0??? then UNDEFINED; + // if Rt == '1111' && P == '1' && U == '0' && W == '0' then SEE PLD; + // if Rn == '1111' then SEE LDRB (literal); + // if P == '1' && U == '1' && W == '0' then SEE LDRBT; + // if P == '0' && W == '0' then UNDEFINED; if (BitIsClear (opcode, 10) && BitIsClear (opcode, 8)) return false; @@ -5925,7 +5930,7 @@ n = Bits32 (opcode, 19, 16); imm32 = Bits32 (opcode, 7, 0); - // index = (P == ???1???); add = (U == ???1???); wback = (W == ???1???); + // index = (P == '1'); add = (U == '1'); wback = (W == '1'); index = BitIsSet (opcode, 10); add = BitIsSet (opcode, 9); wback = BitIsSet (opcode, 8); @@ -6011,8 +6016,8 @@ switch (encoding) { case eEncodingT1: - // if Rt == ???1111??? then SEE PLD; - // t = UInt(Rt); imm32 = ZeroExtend(imm12, 32); add = (U == ???1???); + // if Rt == '1111' then SEE PLD; + // t = UInt(Rt); imm32 = ZeroExtend(imm12, 32); add = (U == '1'); t = Bits32 (opcode, 15, 12); imm32 = Bits32 (opcode, 11, 0); add = BitIsSet (opcode, 23); @@ -6024,7 +6029,7 @@ break; case eEncodingA1: - // t == UInt(Rt); imm32 = ZeroExtend(imm12, 32); add = (U == ???1???); + // t == UInt(Rt); imm32 = ZeroExtend(imm12, 32); add = (U == '1'); t = Bits32 (opcode, 15, 12); imm32 = Bits32 (opcode, 11, 0); add = BitIsSet (opcode, 23); @@ -6116,8 +6121,8 @@ break; case eEncodingT2: - // if Rt == ???1111??? then SEE PLD; - // if Rn == ???1111??? then SEE LDRB (literal); + // if Rt == '1111' then SEE PLD; + // if Rn == '1111' then SEE LDRB (literal); // t = UInt(Rt); n = UInt(Rn); m = UInt(Rm); t = Bits32 (opcode, 15, 12); n = Bits32 (opcode, 19, 16); @@ -6139,13 +6144,13 @@ case eEncodingA1: { - // if P == ???0??? && W == ???1??? then SEE LDRBT; + // if P == '0' && W == '1' then SEE LDRBT; // t = UInt(Rt); n = UInt(Rn); m = UInt(Rm); t = Bits32 (opcode, 15, 12); n = Bits32 (opcode, 19, 16); m = Bits32 (opcode, 3, 0); - // index = (P == ???1???); add = (U == ???1???); wback = (P == ???0???) || (W == ???1???); + // index = (P == '1'); add = (U == '1'); wback = (P == '0') || (W == '1'); index = BitIsSet (opcode, 24); add = BitIsSet (opcode, 23); wback = (BitIsClear (opcode, 24) || BitIsSet (opcode, 21)); @@ -6235,7 +6240,7 @@ address = if index then offset_addr else R[n]; data = MemU[address,2]; if wback then R[n] = offset_addr; - if UnalignedSupport() || address<0> = ???0??? then + if UnalignedSupport() || address<0> = '0' then R[t] = ZeroExtend(data, 32); else // Can only apply before ARMv7 R[t] = bits(32) UNKNOWN; @@ -6257,7 +6262,7 @@ switch (encoding) { case eEncodingT1: - // t = UInt(Rt); n = UInt(Rn); imm32 = ZeroExtend(imm5:???0???, 32); + // t = UInt(Rt); n = UInt(Rn); imm32 = ZeroExtend(imm5:'0', 32); t = Bits32 (opcode, 2, 0); n = Bits32 (opcode, 5, 3); imm32 = Bits32 (opcode, 10, 6) << 1; @@ -6270,8 +6275,8 @@ break; case eEncodingT2: - // if Rt == ???1111??? then SEE "Unallocated memory hints"; - // if Rn == ???1111??? then SEE LDRH (literal); + // if Rt == '1111' then SEE "Unallocated memory hints"; + // if Rn == '1111' then SEE LDRH (literal); // t = UInt(Rt); n = UInt(Rn); imm32 = ZeroExtend(imm12, 32); t = Bits32 (opcode, 15, 12); n = Bits32 (opcode, 19, 16); @@ -6288,10 +6293,10 @@ break; case eEncodingT3: - // if Rn == ???1111??? then SEE LDRH (literal); - // if Rt == ???1111??? && P == ???1??? && U == ???0??? && W == ???0??? then SEE "Unallocated memory hints"; - // if P == ???1??? && U == ???1??? && W == ???0??? then SEE LDRHT; - // if P == ???0??? && W == ???0??? then UNDEFINED; + // if Rn == '1111' then SEE LDRH (literal); + // if Rt == '1111' && P == '1' && U == '0' && W == '0' then SEE "Unallocated memory hints"; + // if P == '1' && U == '1' && W == '0' then SEE LDRHT; + // if P == '0' && W == '0' then UNDEFINED; if (BitIsClear (opcode, 10) && BitIsClear (opcode, 8)) return false; @@ -6300,7 +6305,7 @@ n = Bits32 (opcode, 19, 16); imm32 = Bits32 (opcode, 7, 0); - // index = (P == ???1???); add = (U == ???1???); wback = (W == ???1???); + // index = (P == '1'); add = (U == '1'); wback = (W == '1'); index = BitIsSet (opcode, 10); add = BitIsSet (opcode, 9); wback = BitIsSet (opcode, 8); @@ -6354,7 +6359,7 @@ return false; } - // if UnalignedSupport() || address<0> = ???0??? then + // if UnalignedSupport() || address<0> = '0' then if (UnalignedSupport () || BitIsClear (address, 0)) { // R[t] = ZeroExtend(data, 32); @@ -6383,7 +6388,7 @@ base = Align(PC,4); address = if add then (base + imm32) else (base - imm32); data = MemU[address,2]; - if UnalignedSupport() || address<0> = ???0??? then + if UnalignedSupport() || address<0> = '0' then R[t] = ZeroExtend(data, 32); else // Can only apply before ARMv7 R[t] = bits(32) UNKNOWN; @@ -6401,8 +6406,8 @@ switch (encoding) { case eEncodingT1: - // if Rt == ???1111??? then SEE "Unallocated memory hints"; - // t = UInt(Rt); imm32 = ZeroExtend(imm12, 32); add = (U == ???1???); + // if Rt == '1111' then SEE "Unallocated memory hints"; + // t = UInt(Rt); imm32 = ZeroExtend(imm12, 32); add = (U == '1'); t = Bits32 (opcode, 15, 12); imm32 = Bits32 (opcode, 11, 0); add = BitIsSet (opcode, 23); @@ -6418,7 +6423,7 @@ uint32_t imm4H = Bits32 (opcode, 11, 8); uint32_t imm4L = Bits32 (opcode, 3, 0); - // t == UInt(Rt); imm32 = ZeroExtend(imm4H:imm4L, 32); add = (U == ???1???); + // t == UInt(Rt); imm32 = ZeroExtend(imm4H:imm4L, 32); add = (U == '1'); t = Bits32 (opcode, 15, 12); imm32 = (imm4H << 4) | imm4L; add = BitIsSet (opcode, 23); @@ -6460,7 +6465,7 @@ return false; - // if UnalignedSupport() || address<0> = ???0??? then + // if UnalignedSupport() || address<0> = '0' then if (UnalignedSupport () || BitIsClear (address, 0)) { // R[t] = ZeroExtend(data, 32); @@ -6493,7 +6498,7 @@ address = if index then offset_addr else R[n]; data = MemU[address,2]; if wback then R[n] = offset_addr; - if UnalignedSupport() || address<0> = ???0??? then + if UnalignedSupport() || address<0> = '0' then R[t] = ZeroExtend(data, 32); else // Can only apply before ARMv7 R[t] = bits(32) UNKNOWN; @@ -6534,8 +6539,8 @@ break; case eEncodingT2: - // if Rn == ???1111??? then SEE LDRH (literal); - // if Rt == ???1111??? then SEE "Unallocated memory hints"; + // if Rn == '1111' then SEE LDRH (literal); + // if Rt == '1111' then SEE "Unallocated memory hints"; // t = UInt(Rt); n = UInt(Rn); m = UInt(Rm); t = Bits32 (opcode, 15, 12); n = Bits32 (opcode, 19, 16); @@ -6556,13 +6561,13 @@ break; case eEncodingA1: - // if P == ???0??? && W == ???1??? then SEE LDRHT; + // if P == '0' && W == '1' then SEE LDRHT; // t = UInt(Rt); n = UInt(Rn); m = UInt(Rm); t = Bits32 (opcode, 15, 12); n = Bits32 (opcode, 19, 16); m = Bits32 (opcode, 3, 0); - // index = (P == ???1???); add = (U == ???1???); wback = (P == ???0???) || (W == ???1???); + // index = (P == '1'); add = (U == '1'); wback = (P == '0') || (W == '1'); index = BitIsSet (opcode, 24); add = BitIsSet (opcode, 23); wback = (BitIsClear (opcode, 24) || BitIsSet (opcode, 21)); @@ -6634,7 +6639,7 @@ return false; } - // if UnalignedSupport() || address<0> = ???0??? then + // if UnalignedSupport() || address<0> = '0' then if (UnalignedSupport() || BitIsClear (address, 0)) { // R[t] = ZeroExtend(data, 32); @@ -6682,8 +6687,8 @@ switch (encoding) { case eEncodingT1: - // if Rt == ???1111??? then SEE PLI; - // if Rn == ???1111??? then SEE LDRSB (literal); + // if Rt == '1111' then SEE PLI; + // if Rn == '1111' then SEE LDRSB (literal); // t = UInt(Rt); n = UInt(Rn); imm32 = ZeroExtend(imm12, 32); t = Bits32 (opcode, 15, 12); n = Bits32 (opcode, 19, 16); @@ -6701,10 +6706,10 @@ break; case eEncodingT2: - // if Rt == ???1111??? && P == ???1??? && U == ???0??? && W == ???0??? then SEE PLI; - // if Rn == ???1111??? then SEE LDRSB (literal); - // if P == ???1??? && U == ???1??? && W == ???0??? then SEE LDRSBT; - // if P == ???0??? && W == ???0??? then UNDEFINED; + // if Rt == '1111' && P == '1' && U == '0' && W == '0' then SEE PLI; + // if Rn == '1111' then SEE LDRSB (literal); + // if P == '1' && U == '1' && W == '0' then SEE LDRSBT; + // if P == '0' && W == '0' then UNDEFINED; if (BitIsClear (opcode, 10) && BitIsClear (opcode, 8)) return false; @@ -6713,21 +6718,23 @@ n = Bits32 (opcode, 19, 16); imm32 = Bits32 (opcode, 7, 0); - // index = (P == ???1???); add = (U == ???1???); wback = (W == ???1???); + // index = (P == '1'); add = (U == '1'); wback = (W == '1'); index = BitIsSet (opcode, 10); add = BitIsSet (opcode, 9); wback = BitIsSet (opcode, 8); // if BadReg(t) || (wback && n == t) then UNPREDICTABLE; - if (BadReg (t) || (wback && (n == t))) + if (((t == 13) || ((t == 15) + && (BitIsClear (opcode, 10) || BitIsSet (opcode, 9) || BitIsSet (opcode, 8)))) + || (wback && (n == t))) return false; break; case eEncodingA1: { - // if Rn == ???1111??? then SEE LDRSB (literal); - // if P == ???0??? && W == ???1??? then SEE LDRSBT; + // if Rn == '1111' then SEE LDRSB (literal); + // if P == '0' && W == '1' then SEE LDRSBT; // t == UInt(Rt); n = UInt(Rn); imm32 = ZeroExtend(imm4H:imm4L, 32); t = Bits32 (opcode, 15, 12); n = Bits32 (opcode, 19, 16); @@ -6736,7 +6743,7 @@ uint32_t imm4L = Bits32 (opcode, 3, 0); imm32 = (imm4H << 4) | imm4L; - // index = (P == ???1???); add = (U == ???1???); wback = (P == ???0???) || (W == ???1???); + // index = (P == '1'); add = (U == '1'); wback = (P == '0') || (W == '1'); index = BitIsSet (opcode, 24); add = BitIsSet (opcode, 23); wback = (BitIsClear (opcode, 24) || BitIsSet (opcode, 21)); @@ -6752,7 +6759,7 @@ return false; } - uint64_t Rn = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_r0 + n, 0, &success); + uint64_t Rn = ReadCoreReg (n, &success); if (!success) return false; @@ -6825,8 +6832,8 @@ switch (encoding) { case eEncodingT1: - // if Rt == ???1111??? then SEE PLI; - // t = UInt(Rt); imm32 = ZeroExtend(imm12, 32); add = (U == ???1???); + // if Rt == '1111' then SEE PLI; + // t = UInt(Rt); imm32 = ZeroExtend(imm12, 32); add = (U == '1'); t = Bits32 (opcode, 15, 12); imm32 = Bits32 (opcode, 11, 0); add = BitIsSet (opcode, 23); @@ -6839,7 +6846,7 @@ case eEncodingA1: { - // t == UInt(Rt); imm32 = ZeroExtend(imm4H:imm4L, 32); add = (U == ???1???); + // t == UInt(Rt); imm32 = ZeroExtend(imm4H:imm4L, 32); add = (U == '1'); t = Bits32 (opcode, 15, 12); uint32_t imm4H = Bits32 (opcode, 11, 8); uint32_t imm4L = Bits32 (opcode, 3, 0); @@ -6939,8 +6946,8 @@ break; case eEncodingT2: - // if Rt == ???1111??? then SEE PLI; - // if Rn == ???1111??? then SEE LDRSB (literal); + // if Rt == '1111' then SEE PLI; + // if Rn == '1111' then SEE LDRSB (literal); // t = UInt(Rt); n = UInt(Rn); m = UInt(Rm); t = Bits32 (opcode, 15, 12); n = Bits32 (opcode, 19, 16); @@ -6961,13 +6968,13 @@ break; case eEncodingA1: - // if P == ???0??? && W == ???1??? then SEE LDRSBT; + // if P == '0' && W == '1' then SEE LDRSBT; // t = UInt(Rt); n = UInt(Rn); m = UInt(Rm); t = Bits32 (opcode, 15, 12); n = Bits32 (opcode, 19, 16); m = Bits32 (opcode, 3, 0); - // index = (P == ???1???); add = (U == ???1???); wback = (P == ???0???) || (W == ???1???); + // index = (P == '1'); add = (U == '1'); wback = (P == '0') || (W == '1'); index = BitIsSet (opcode, 24); add = BitIsSet (opcode, 23); wback = BitIsClear (opcode, 24) || BitIsSet (opcode, 21); @@ -7058,7 +7065,7 @@ address = if index then offset_addr else R[n]; data = MemU[address,2]; if wback then R[n] = offset_addr; - if UnalignedSupport() || address<0> = ???0??? then + if UnalignedSupport() || address<0> = '0' then R[t] = SignExtend(data, 32); else // Can only apply before ARMv7 R[t] = bits(32) UNKNOWN; @@ -7079,8 +7086,8 @@ switch (encoding) { case eEncodingT1: - // if Rn == ???1111??? then SEE LDRSH (literal); - // if Rt == ???1111??? then SEE "Unallocated memory hints"; + // if Rn == '1111' then SEE LDRSH (literal); + // if Rt == '1111' then SEE "Unallocated memory hints"; // t = UInt(Rt); n = UInt(Rn); imm32 = ZeroExtend(imm12, 32); t = Bits32 (opcode, 15, 12); n = Bits32 (opcode, 19, 16); @@ -7098,10 +7105,10 @@ break; case eEncodingT2: - // if Rn == ???1111??? then SEE LDRSH (literal); - // if Rt == ???1111??? && P == ???1??? && U == ???0??? && W == ???0??? then SEE "Unallocated memory hints"; - // if P == ???1??? && U == ???1??? && W == ???0??? then SEE LDRSHT; - // if P == ???0??? && W == ???0??? then UNDEFINED; + // if Rn == '1111' then SEE LDRSH (literal); + // if Rt == '1111' && P == '1' && U == '0' && W == '0' then SEE "Unallocated memory hints"; + // if P == '1' && U == '1' && W == '0' then SEE LDRSHT; + // if P == '0' && W == '0' then UNDEFINED; if (BitIsClear (opcode, 10) && BitIsClear (opcode, 8)) return false; @@ -7110,7 +7117,7 @@ n = Bits32 (opcode, 19, 16); imm32 = Bits32 (opcode, 7, 0); - // index = (P == ???1???); add = (U == ???1???); wback = (W == ???1???); + // index = (P == '1'); add = (U == '1'); wback = (W == '1'); index = BitIsSet (opcode, 10); add = BitIsSet (opcode, 9); wback = BitIsSet (opcode, 8); @@ -7123,8 +7130,8 @@ case eEncodingA1: { - // if Rn == ???1111??? then SEE LDRSH (literal); - // if P == ???0??? && W == ???1??? then SEE LDRSHT; + // if Rn == '1111' then SEE LDRSH (literal); + // if P == '0' && W == '1' then SEE LDRSHT; // t == UInt(Rt); n = UInt(Rn); imm32 = ZeroExtend(imm4H:imm4L, 32); t = Bits32 (opcode, 15, 12); n = Bits32 (opcode, 19, 16); @@ -7132,7 +7139,7 @@ uint32_t imm4L = Bits32 (opcode, 3, 0); imm32 = (imm4H << 4) | imm4L; - // index = (P == ???1???); add = (U == ???1???); wback = (P == ???0???) || (W == ???1???); + // index = (P == '1'); add = (U == '1'); wback = (P == '0') || (W == '1'); index = BitIsSet (opcode, 24); add = BitIsSet (opcode, 23); wback = BitIsClear (opcode, 24) || BitIsSet (opcode, 21); @@ -7187,7 +7194,7 @@ return false; } - // if UnalignedSupport() || address<0> = ???0??? then + // if UnalignedSupport() || address<0> = '0' then if (UnalignedSupport() || BitIsClear (address, 0)) { // R[t] = SignExtend(data, 32); @@ -7217,7 +7224,7 @@ base = Align(PC,4); address = if add then (base + imm32) else (base - imm32); data = MemU[address,2]; - if UnalignedSupport() || address<0> = ???0??? then + if UnalignedSupport() || address<0> = '0' then R[t] = SignExtend(data, 32); else // Can only apply before ARMv7 R[t] = bits(32) UNKNOWN; @@ -7235,8 +7242,8 @@ switch (encoding) { case eEncodingT1: - // if Rt == ???1111??? then SEE "Unallocated memory hints"; - // t = UInt(Rt); imm32 = ZeroExtend(imm12, 32); add = (U == ???1???); + // if Rt == '1111' then SEE "Unallocated memory hints"; + // t = UInt(Rt); imm32 = ZeroExtend(imm12, 32); add = (U == '1'); t = Bits32 (opcode, 15, 12); imm32 = Bits32 (opcode, 11, 0); add = BitIsSet (opcode, 23); @@ -7249,7 +7256,7 @@ case eEncodingA1: { - // t == UInt(Rt); imm32 = ZeroExtend(imm4H:imm4L, 32); add = (U == ???1???); + // t == UInt(Rt); imm32 = ZeroExtend(imm4H:imm4L, 32); add = (U == '1'); t = Bits32 (opcode, 15, 12); uint32_t imm4H = Bits32 (opcode, 11, 8); uint32_t imm4L = Bits32 (opcode, 3, 0); @@ -7292,7 +7299,7 @@ if (!success) return false; - // if UnalignedSupport() || address<0> = ???0??? then + // if UnalignedSupport() || address<0> = '0' then if (UnalignedSupport() || BitIsClear (address, 0)) { // R[t] = SignExtend(data, 32); @@ -7323,7 +7330,7 @@ address = if index then offset_addr else R[n]; data = MemU[address,2]; if wback then R[n] = offset_addr; - if UnalignedSupport() || address<0> = ???0??? then + if UnalignedSupport() || address<0> = '0' then R[t] = SignExtend(data, 32); else // Can only apply before ARMv7 R[t] = bits(32) UNKNOWN; @@ -7364,8 +7371,8 @@ break; case eEncodingT2: - // if Rn == ???1111??? then SEE LDRSH (literal); - // if Rt == ???1111??? then SEE "Unallocated memory hints"; + // if Rn == '1111' then SEE LDRSH (literal); + // if Rt == '1111' then SEE "Unallocated memory hints"; // t = UInt(Rt); n = UInt(Rn); m = UInt(Rm); t = Bits32 (opcode, 15, 12); n = Bits32 (opcode, 19, 16); @@ -7387,13 +7394,13 @@ break; case eEncodingA1: - // if P == ???0??? && W == ???1??? then SEE LDRSHT; + // if P == '0' && W == '1' then SEE LDRSHT; // t = UInt(Rt); n = UInt(Rn); m = UInt(Rm); t = Bits32 (opcode, 15, 12); n = Bits32 (opcode, 19, 16); m = Bits32 (opcode, 3, 0); - // index = (P == ???1???); add = (U == ???1???); wback = (P == ???0???) || (W == ???1???); + // index = (P == '1'); add = (U == '1'); wback = (P == '0') || (W == '1'); index = BitIsSet (opcode, 24); add = BitIsSet (opcode, 23); wback = BitIsClear (opcode, 24) || BitIsSet (opcode, 21); @@ -7466,7 +7473,7 @@ return false; } - // if UnalignedSupport() || address<0> = ???0??? then + // if UnalignedSupport() || address<0> = '0' then if (UnalignedSupport() || BitIsClear (address, 0)) { // R[t] = SignExtend(data, 32); @@ -7518,7 +7525,7 @@ break; case eEncodingT2: - // d = UInt(Rd); m = UInt(Rm); rotation = UInt(rotate:???000???); + // d = UInt(Rd); m = UInt(Rm); rotation = UInt(rotate:'000'); d = Bits32 (opcode, 11, 8); m = Bits32 (opcode, 3, 0); rotation = Bits32 (opcode, 5, 4) << 3; @@ -7530,7 +7537,7 @@ break; case eEncodingA1: - // d = UInt(Rd); m = UInt(Rm); rotation = UInt(rotate:???000???); + // d = UInt(Rd); m = UInt(Rm); rotation = UInt(rotate:'000'); d = Bits32 (opcode, 15, 12); m = Bits32 (opcode, 3, 0); rotation = Bits32 (opcode, 11, 10) << 3; @@ -7600,7 +7607,7 @@ break; case eEncodingT2: - // d = UInt(Rd); m = UInt(Rm); rotation = UInt(rotate:???000???); + // d = UInt(Rd); m = UInt(Rm); rotation = UInt(rotate:'000'); d = Bits32 (opcode, 11, 8); m = Bits32 (opcode, 3, 0); rotation = Bits32 (opcode, 5, 4) << 3; @@ -7612,7 +7619,7 @@ break; case eEncodingA1: - // d = UInt(Rd); m = UInt(Rm); rotation = UInt(rotate:???000???); + // d = UInt(Rd); m = UInt(Rm); rotation = UInt(rotate:'000'); d = Bits32 (opcode, 15, 12); m = Bits32 (opcode, 3, 0); rotation = Bits32 (opcode, 11, 10) << 3; @@ -7682,7 +7689,7 @@ break; case eEncodingT2: - // d = UInt(Rd); m = UInt(Rm); rotation = UInt(rotate:???000???); + // d = UInt(Rd); m = UInt(Rm); rotation = UInt(rotate:'000'); d = Bits32 (opcode, 11, 8); m = Bits32 (opcode, 3, 0); rotation = Bits32 (opcode, 5, 4) << 3; @@ -7694,7 +7701,7 @@ break; case eEncodingA1: - // d = UInt(Rd); m = UInt(Rm); rotation = UInt(rotate:???000???); + // d = UInt(Rd); m = UInt(Rm); rotation = UInt(rotate:'000'); d = Bits32 (opcode, 15, 12); m = Bits32 (opcode, 3, 0); rotation = Bits32 (opcode, 11, 10) << 3; @@ -7761,7 +7768,7 @@ break; case eEncodingT2: - // d = UInt(Rd); m = UInt(Rm); rotation = UInt(rotate:???000???); + // d = UInt(Rd); m = UInt(Rm); rotation = UInt(rotate:'000'); d = Bits32 (opcode, 11, 8); m = Bits32 (opcode, 3, 0); rotation = Bits32 (opcode, 5, 4) << 3; @@ -7773,7 +7780,7 @@ break; case eEncodingA1: - // d = UInt(Rd); m = UInt(Rm); rotation = UInt(rotate:???000???); + // d = UInt(Rd); m = UInt(Rm); rotation = UInt(rotate:'000'); d = Bits32 (opcode, 15, 12); m = Bits32 (opcode, 3, 0); rotation = Bits32 (opcode, 11, 10) << 3; @@ -7822,7 +7829,7 @@ else address = if increment then R[n] else R[n]-8; if wordhigher then address = address+4; - CPSRWriteByInstr(MemA[address+4,4], ???1111???, TRUE); + CPSRWriteByInstr(MemA[address+4,4], '1111', TRUE); BranchWritePC(MemA[address,4]); if wback then R[n] = if increment then R[n]+8 else R[n]-8; #endif @@ -7840,7 +7847,7 @@ switch (encoding) { case eEncodingT1: - // n = UInt(Rn); wback = (W == ???1???); increment = FALSE; wordhigher = FALSE; + // n = UInt(Rn); wback = (W == '1'); increment = FALSE; wordhigher = FALSE; n = Bits32 (opcode, 19, 16); wback = BitIsSet (opcode, 21); increment = false; @@ -7857,7 +7864,7 @@ break; case eEncodingT2: - // n = UInt(Rn); wback = (W == ???1???); increment = TRUE; wordhigher = FALSE; + // n = UInt(Rn); wback = (W == '1'); increment = TRUE; wordhigher = FALSE; n = Bits32 (opcode, 19, 16); wback = BitIsSet (opcode, 21); increment = true; @@ -7877,7 +7884,7 @@ // n = UInt(Rn); n = Bits32 (opcode, 19, 16); - // wback = (W == ???1???); inc = (U == ???1???); wordhigher = (P == U); + // wback = (W == '1'); inc = (U == '1'); wordhigher = (P == U); wback = BitIsSet (opcode, 21); increment = BitIsSet (opcode, 23); wordhigher = (Bit32 (opcode, 24) == Bit32 (opcode, 23)); @@ -7913,7 +7920,7 @@ if (wordhigher) address = address + 4; - // CPSRWriteByInstr(MemA[address+4,4], ???1111???, TRUE); + // CPSRWriteByInstr(MemA[address+4,4], '1111', TRUE); Register base_reg; base_reg.SetRegister (eRegisterKindDWARF, dwarf_r0 + n); @@ -8158,7 +8165,7 @@ Rn = Bits32(opcode, 19, 16); setflags = BitIsSet(opcode, 20); imm32 = ThumbExpandImm_C(opcode, APSR_C, carry); // (imm32, carry) = ThumbExpandImm(i:imm3:imm8, APSR.C) - // if Rn == ???1111??? then SEE MOV (immediate); + // if Rn == '1111' then SEE MOV (immediate); if (Rn == 15) return EmulateMOVRdImm (opcode, eEncodingT2); if (BadReg(Rd) || Rn == 13) @@ -8757,7 +8764,7 @@ if (Rd == 15 && setflags) return EmulateCMPImm (opcode, eEncodingT2); - // if Rn == ???1101??? then SEE SUB (SP minus immediate); + // if Rn == '1101' then SEE SUB (SP minus immediate); if (Rn == 13) return EmulateSUBSPImm (opcode, eEncodingT2); @@ -8836,11 +8843,11 @@ setflags = BitIsSet(opcode, 20); imm32 = ARMExpandImm(opcode); // imm32 = ARMExpandImm(imm12) - // if Rn == ???1111??? && S == ???0??? then SEE ADR; + // if Rn == '1111' && S == '0' then SEE ADR; if (Rn == 15 && !setflags) return EmulateADR (opcode, eEncodingA2); - // if Rn == ???1101??? then SEE SUB (SP minus immediate); + // if Rn == '1101' then SEE SUB (SP minus immediate); if (Rn == 13) return EmulateSUBSPImm (opcode, eEncodingA1); From johnny.chen at apple.com Mon Mar 28 17:40:32 2011 From: johnny.chen at apple.com (Johnny Chen) Date: Mon, 28 Mar 2011 22:40:32 -0000 Subject: [Lldb-commits] [lldb] r128428 - in /lldb/trunk/utils/test: README-lldb-disasm lldb-disasm.py Message-ID: <20110328224032.EDF2F2A6C12C@llvm.org> Author: johnny Date: Mon Mar 28 17:40:32 2011 New Revision: 128428 URL: http://llvm.org/viewvc/llvm-project?rev=128428&view=rev Log: Add an initial version of lldb-disasm.py script whose purpose is to iterate through all the symbols for an executable image and to issue the lldb 'disassemble' command on each symbol. The initial version just dumps the symbol table. Added: lldb/trunk/utils/test/README-lldb-disasm lldb/trunk/utils/test/lldb-disasm.py (with props) Added: lldb/trunk/utils/test/README-lldb-disasm URL: http://llvm.org/viewvc/llvm-project/lldb/trunk/utils/test/README-lldb-disasm?rev=128428&view=auto ============================================================================== --- lldb/trunk/utils/test/README-lldb-disasm (added) +++ lldb/trunk/utils/test/README-lldb-disasm Mon Mar 28 17:40:32 2011 @@ -0,0 +1,94 @@ +This README describes a sample invocation of lldb-disasm.py whose purpose is to test +the lldb 'disassemble' command. + +This is for the initial checkin of lldb-disasm.py which only reads an executable image and +dumps the symbol table from the imgae and its dependent libraries. The output was cut off +since it is too large. + +da0603a-dhcp191:9131529 johnny$ /Volumes/data/lldb/svn/trunk/utils/test/lldb-disasm.py -C 'platform create remote-ios' -e /Developer/Platforms/iPhoneOS.platform/Developer/SDKs/iPhoneOS4.3.sdk/usr/lib/libSystem.B.dylib +lldb commands: ['platform create remote-ios'] +lldb options: None +executable: /Developer/Platforms/iPhoneOS.platform/Developer/SDKs/iPhoneOS4.3.sdk/usr/lib/libSystem.B.dylib +sys.path: ['/Volumes/data/lldb/svn/trunk/utils/test', '/Volumes/data/lldb/svn/trunk/build/Debug/LLDB.framework/Resources/Python', '/System/Library/Frameworks/Python.framework/Versions/2.6/lib/python26.zip', '/System/Library/Frameworks/Python.framework/Versions/2.6/lib/python2.6', '/System/Library/Frameworks/Python.framework/Versions/2.6/lib/python2.6/plat-darwin', '/System/Library/Frameworks/Python.framework/Versions/2.6/lib/python2.6/plat-mac', '/System/Library/Frameworks/Python.framework/Versions/2.6/lib/python2.6/plat-mac/lib-scriptpackages', '/System/Library/Frameworks/Python.framework/Versions/2.6/Extras/lib/python', '/System/Library/Frameworks/Python.framework/Versions/2.6/lib/python2.6/lib-tk', '/System/Library/Frameworks/Python.framework/Versions/2.6/lib/python2.6/lib-old', '/System/Library/Frameworks/Python.framework/Versions/2.6/lib/python2.6/lib-dynload', '/Library/Python/2.6/site-packages', '/AppleInternal/Library/Python/2.6/site-packages', '/System/Library/Frame works/Python.framework/Versions/2.6/Extras/lib/python/PyObjC', '/System/Library/Frameworks/Python.framework/Versions/2.6/Extras/lib/python/wx-2.8-mac-unicode', '/Volumes/data/lldb/svn/trunk/utils/test/../../test/pexpect-2.4', '/Volumes/data/lldb/svn/trunk/test'] +/Volumes/data/lldb/svn/trunk/test/lldbutil.py:80: SyntaxWarning: import * only allowed at module level + def int_to_bytearray(val, bytesize): +/Volumes/data/lldb/svn/trunk/test/lldbutil.py:105: SyntaxWarning: import * only allowed at module level + def bytearray_to_int(bytes, bytesize): +run command: platform create remote-ios +output: Platform: remote-ios +Not connected to a remote platform. +SDKROOT: "/Developer/Platforms/iPhoneOS.platform/DeviceSupport/4.3 (8F190)" + +run command: file /Developer/Platforms/iPhoneOS.platform/Developer/SDKs/iPhoneOS4.3.sdk/usr/lib/libSystem.B.dylib +output: Current executable set to '/Developer/Platforms/iPhoneOS.platform/Developer/SDKs/iPhoneOS4.3.sdk/usr/lib/libSystem.B.dylib' (armv7). + +run command: image dump symtab +output: Dumping symbol table for 18 modules. +Symtab, file = /Developer/Platforms/iPhoneOS.platform/Developer/SDKs/iPhoneOS4.3.sdk/usr/lib/libSystem.B.dylib, num_symbols = 851: + Debug symbol + |Synthetic symbol + ||Externally Visible + ||| +Index UserID DSX Type File Address/Value Load Address Size Flags Name +------- ------ --- ------------ ------------------ ------------------ ------------------ ---------- ---------------------------------- +[ 0] 0 Code 0x0000000000001420 0x0000000000000000 0x000e0008 libSystem_initializer +[ 1] 1 Code 0x00000000000014c4 0x0000000000000000 0x001e0008 __keymgr_initializer +[ 2] 2 Code 0x00000000000014fc 0x0000000000000000 0x000e0008 dwarf2_unwind_dyld_add_image_hook +[ 3] 3 Code 0x0000000000001564 0x0000000000000000 0x000e0008 get_or_create_key_element +[ 4] 4 Code 0x0000000000001684 0x0000000000000000 0x000e0008 unlock_node +[ 5] 5 Code 0x0000000000001930 0x0000000000000000 0x000e0000 RsqrtTable +[ 6] 6 Code 0x0000000000001c30 0x0000000000000000 0x000e0000 acosf_crossover +[ 7] 7 Code 0x0000000000001c34 0x0000000000000000 0x000e0000 acosf_mid_poly +[ 8] 8 Code 0x0000000000001c48 0x0000000000000000 0x000e0000 Pi2_Q30 +[ 9] 9 Code 0x0000000000001c4c 0x0000000000000000 0x000e0000 Pi_Q30 +[ 10] 10 Code 0x0000000000001c78 0x0000000000000000 0x000e0000 acosf_approx +[ 11] 11 Code 0x0000000000001cec 0x0000000000000000 0x000e0000 acosf_pos_tail_poly +[ 12] 12 Code 0x0000000000001d00 0x0000000000000000 0x000e0000 acosf_tail +[ 13] 13 Code 0x0000000000001dfc 0x0000000000000000 0x000e0000 acosf_normalize +[ 14] 14 Code 0x0000000000001e10 0x0000000000000000 0x000e0000 acosf_round +[ 15] 15 Code 0x0000000000001e28 0x0000000000000000 0x000e0000 acosf_encode +[ 16] 16 Code 0x0000000000001e30 0x0000000000000000 0x000e0000 acosf_done +[ 17] 17 Code 0x0000000000001e38 0x0000000000000000 0x000e0000 acosf_special +[ 18] 18 Code 0x0000000000001e68 0x0000000000000000 0x000e0000 acosf_small +[ 19] 19 Code 0x0000000000001e9c 0x0000000000000000 0x000e0000 acosf_very_small +[ 20] 20 Code 0x0000000000001eb8 0x0000000000000000 0x000e0000 Pif +[ 21] 21 Code 0x000000000000220c 0x0000000000000000 0x000e0000 RsqrtTable +[ 22] 22 Code 0x000000000000250c 0x0000000000000000 0x000e0000 asinf_crossover +[ 23] 23 Code 0x0000000000002510 0x0000000000000000 0x000e0000 asinf_mid_poly +[ 24] 24 Code 0x0000000000002524 0x0000000000000000 0x000e0000 Pi2_Q30 +[ 25] 25 Code 0x0000000000002550 0x0000000000000000 0x000e0000 asinf_approx +[ 26] 26 Code 0x00000000000025e4 0x0000000000000000 0x000e0000 asinf_tail_poly +[ 27] 27 Code 0x0000000000002600 0x0000000000000000 0x000e0000 asinf_tail +[ 28] 28 Code 0x00000000000026e0 0x0000000000000000 0x000e0000 asinf_normalize +[ 29] 29 Code 0x00000000000026f4 0x0000000000000000 0x000e0000 asinf_round +[ 30] 30 Code 0x000000000000270c 0x0000000000000000 0x000e0000 asinf_encode +[ 31] 31 Code 0x0000000000002718 0x0000000000000000 0x000e0000 asinf_done +[ 32] 32 Code 0x0000000000002720 0x0000000000000000 0x000e0000 asinf_special +[ 33] 33 Code 0x0000000000002754 0x0000000000000000 0x000e0000 asinf_small +[ 34] 34 Code 0x0000000000002784 0x0000000000000000 0x000e0000 Pi2f +[ 35] 35 Code 0x0000000000005774 0x0000000000000000 0x000e0008 rem_pio2 +[ 36] 36 Code 0x00000000000076c4 0x0000000000000000 0x000e0008 __kernel_rem_pio2 +[ 37] 37 Code 0x0000000000008c90 0x0000000000000000 0x000e0008 __kernel_tan +[ 38] 38 Code 0x0000000000008ef0 0x0000000000000000 0x000e0008 lgammaApprox +[ 39] 39 Code 0x000000000000b3d4 0x0000000000000000 0x000e0000 powf_not_special +[ 40] 40 Code 0x000000000000b3dc 0x0000000000000000 0x000e0000 powf_ylgx +[ 41] 41 Code 0x000000000000b438 0x0000000000000000 0x000e0000 powf_done +[ 42] 42 Code 0x000000000000b43c 0x0000000000000000 0x000e0000 powf_special_y +[ 43] 43 Code 0x000000000000b4a8 0x0000000000000000 0x000e0000 powf_special_x +[ 44] 44 Code 0x000000000000b4cc 0x0000000000000000 0x000e0000 powf_mzero_minf +[ 45] 45 Code 0x000000000000b54c 0x0000000000000000 0x000e0000 powf_y_odd +[ 46] 46 Code 0x000000000000b57c 0x0000000000000000 0x000e0000 powf_y_nonint +[ 47] 47 Code 0x000000000000b588 0x0000000000000000 0x000e0000 powf_y_even +[ 48] 48 Code 0x000000000000b7a8 0x0000000000000000 0x000e0000 powf_log2_reduction +[ 49] 49 Code 0x000000000000b7a8 0x0000000000000000 0x000e0000 powf_log2 +[ 50] 50 Code 0x000000000000b814 0x0000000000000000 0x000e0000 powf_log2_approx +[ 51] 51 Code 0x000000000000b88c 0x0000000000000000 0x000e0000 powf_log2_synthesis +[ 52] 52 Code 0x000000000000b960 0x0000000000000000 0x000e0000 powf_log2_exactPowerOfTwo +[ 53] 53 Code 0x000000000000b980 0x0000000000000000 0x000e0000 powf_log2_near1 +[ 54] 54 Code 0x000000000000b9ec 0x0000000000000000 0x000e0000 powf_log2_synthesis_near1 +[ 55] 55 Code 0x000000000000ba04 0x0000000000000000 0x000e0000 Q32_minimax +[ 56] 56 Code 0x000000000000ba10 0x0000000000000000 0x000e0000 iexp2_lut +[ 57] 57 Code 0x000000000000ba94 0x0000000000000000 0x000e0000 powf_exp2 +[ 58] 58 Code 0x000000000000bb18 0x0000000000000000 0x000e0000 powf_exp2_exact_int +[ 59] 59 Code 0x000000000000bb24 0x0000000000000000 0x000e0000 powf_exp2_big +[ 60] 60 Code 0x000000000000bb74 0x0000000000000000 0x000e0000 powf_exp2_overflow Added: lldb/trunk/utils/test/lldb-disasm.py URL: http://llvm.org/viewvc/llvm-project/lldb/trunk/utils/test/lldb-disasm.py?rev=128428&view=auto ============================================================================== --- lldb/trunk/utils/test/lldb-disasm.py (added) +++ lldb/trunk/utils/test/lldb-disasm.py Mon Mar 28 17:40:32 2011 @@ -0,0 +1,151 @@ +#!/usr/bin/env python + +""" +Run lldb to disassemble all the available functions for an executable image. + +""" + +import os +import sys +from optparse import OptionParser + +def setupSysPath(): + """ + Add LLDB.framework/Resources/Python to the search paths for modules. + """ + # Get the directory containing the current script. + scriptPath = sys.path[0] + if not scriptPath.endswith(os.path.join('utils', 'test')): + print "This script expects to reside in lldb's utils/test directory." + sys.exit(-1) + + # This is our base name component. + base = os.path.abspath(os.path.join(scriptPath, os.pardir, os.pardir)) + + # This is for the goodies in the test directory under base. + sys.path.append(os.path.join(base,'test')) + + # These are for xcode build directories. + xcode3_build_dir = ['build'] + xcode4_build_dir = ['build', 'lldb', 'Build', 'Products'] + dbg = ['Debug'] + rel = ['Release'] + bai = ['BuildAndIntegration'] + python_resource_dir = ['LLDB.framework', 'Resources', 'Python'] + + dbgPath = os.path.join(base, *(xcode3_build_dir + dbg + python_resource_dir)) + dbgPath2 = os.path.join(base, *(xcode4_build_dir + dbg + python_resource_dir)) + relPath = os.path.join(base, *(xcode3_build_dir + rel + python_resource_dir)) + relPath2 = os.path.join(base, *(xcode4_build_dir + rel + python_resource_dir)) + baiPath = os.path.join(base, *(xcode3_build_dir + bai + python_resource_dir)) + baiPath2 = os.path.join(base, *(xcode4_build_dir + bai + python_resource_dir)) + + lldbPath = None + if os.path.isfile(os.path.join(dbgPath, 'lldb.py')): + lldbPath = dbgPath + elif os.path.isfile(os.path.join(dbgPath2, 'lldb.py')): + lldbPath = dbgPath2 + elif os.path.isfile(os.path.join(relPath, 'lldb.py')): + lldbPath = relPath + elif os.path.isfile(os.path.join(relPath2, 'lldb.py')): + lldbPath = relPath2 + elif os.path.isfile(os.path.join(baiPath, 'lldb.py')): + lldbPath = baiPath + elif os.path.isfile(os.path.join(baiPath2, 'lldb.py')): + lldbPath = baiPath2 + + if not lldbPath: + print 'This script requires lldb.py to be in either ' + dbgPath + ',', + print relPath + ', or ' + baiPath + sys.exit(-1) + + # This is to locate the lldb.py module. Insert it right after sys.path[0]. + sys.path[1:1] = [lldbPath] + print "sys.path:", sys.path + + +def run_command(ci, cmd, res): + print "run command:", cmd + ci.HandleCommand(cmd, res) + if res.Succeeded(): + print "output:", res.GetOutput() + else: + print "run command failed!" + print "error:", res.GetError() + +def do_lldb_disassembly(lldb_commands, lldb_options, exe): + import lldb, lldbutil, atexit + + # Create the debugger instance now. + dbg = lldb.SBDebugger.Create() + if not dbg.IsValid(): + raise Exception('Invalid debugger instance') + + # Register an exit callback. + atexit.register(lambda: lldb.SBDebugger.Terminate()) + + # We want our debugger to be synchronous. + dbg.SetAsync(False) + + # Get the command interpreter from the debugger. + ci = dbg.GetCommandInterpreter() + if not ci: + raise Exception('Could not get the command interpreter') + + # And the associated result object. + res = lldb.SBCommandReturnObject() + + # See if there any extra command(s) to execute before we issue the file command. + for cmd in lldb_commands: + run_command(ci, cmd, res) + + # Now issue the file command. + run_command(ci, 'file %s' % exe, res) + + # Send the 'image dump symtab' command. + run_command(ci, 'image dump symtab', res) + +def main(): + # This is to set up the Python path to include the pexpect-2.4 dir. + # Remember to update this when/if things change. + scriptPath = sys.path[0] + sys.path.append(os.path.join(scriptPath, os.pardir, os.pardir, 'test', 'pexpect-2.4')) + + parser = OptionParser(usage="""\ +Run lldb to disassemble all the available functions for an executable image. + +Usage: %prog [options] +""") + parser.add_option('-C', '--lldb-command', + type='string', action='append', metavar='COMMAND', + default=[], dest='lldb_commands', + help='Command(s) lldb executes after starting up (can be empty)') + parser.add_option('-O', '--lldb-options', + type='string', action='store', + dest='lldb_options', + help="""The options passed to 'lldb' command if specified.""") + parser.add_option('-e', '--executable', + type='string', action='store', + dest='executable', + help="""The executable to do disassembly on.""") + + opts, args = parser.parse_args() + + lldb_commands = opts.lldb_commands + lldb_options = opts.lldb_options + + if not opts.executable: + parser.print_help() + sys.exit(1) + executable = opts.executable + + # We have parsed the options. + print "lldb commands:", lldb_commands + print "lldb options:", lldb_options + print "executable:", executable + + setupSysPath() + do_lldb_disassembly(lldb_commands, lldb_options, executable) + +if __name__ == '__main__': + main() Propchange: lldb/trunk/utils/test/lldb-disasm.py ------------------------------------------------------------------------------ svn:executable = * From johnny.chen at apple.com Mon Mar 28 17:48:25 2011 From: johnny.chen at apple.com (Johnny Chen) Date: Mon, 28 Mar 2011 22:48:25 -0000 Subject: [Lldb-commits] [lldb] r128429 - /lldb/trunk/utils/test/lldb-disasm.py Message-ID: <20110328224825.D3D062A6C12C@llvm.org> Author: johnny Date: Mon Mar 28 17:48:25 2011 New Revision: 128429 URL: http://llvm.org/viewvc/llvm-project?rev=128429&view=rev Log: Doc string change. Modified: lldb/trunk/utils/test/lldb-disasm.py Modified: lldb/trunk/utils/test/lldb-disasm.py URL: http://llvm.org/viewvc/llvm-project/lldb/trunk/utils/test/lldb-disasm.py?rev=128429&r1=128428&r2=128429&view=diff ============================================================================== --- lldb/trunk/utils/test/lldb-disasm.py (original) +++ lldb/trunk/utils/test/lldb-disasm.py Mon Mar 28 17:48:25 2011 @@ -11,7 +11,7 @@ def setupSysPath(): """ - Add LLDB.framework/Resources/Python to the search paths for modules. + Add LLDB.framework/Resources/Python and the test dir to the sys.path. """ # Get the directory containing the current script. scriptPath = sys.path[0] From johnny.chen at apple.com Mon Mar 28 20:07:00 2011 From: johnny.chen at apple.com (Johnny Chen) Date: Tue, 29 Mar 2011 01:07:00 -0000 Subject: [Lldb-commits] [lldb] r128442 - /lldb/trunk/utils/test/lldb-disasm.py Message-ID: <20110329010700.F06D92A6C12C@llvm.org> Author: johnny Date: Mon Mar 28 20:07:00 2011 New Revision: 128442 URL: http://llvm.org/viewvc/llvm-project?rev=128442&view=rev Log: Add the ability to invoke lldb's disassemble command on the symbols digested from the 'image dump symtab' command. The number of symbols to disassemble can be specified by the '-n Num' option, or unlimited if not specified. Modified: lldb/trunk/utils/test/lldb-disasm.py Modified: lldb/trunk/utils/test/lldb-disasm.py URL: http://llvm.org/viewvc/llvm-project/lldb/trunk/utils/test/lldb-disasm.py?rev=128442&r1=128441&r2=128442&view=diff ============================================================================== --- lldb/trunk/utils/test/lldb-disasm.py (original) +++ lldb/trunk/utils/test/lldb-disasm.py Mon Mar 28 20:07:00 2011 @@ -64,17 +64,20 @@ print "sys.path:", sys.path -def run_command(ci, cmd, res): - print "run command:", cmd +def run_command(ci, cmd, res, echoInput=True, echoOutput=True): + if echoInput: + print "run command:", cmd ci.HandleCommand(cmd, res) if res.Succeeded(): - print "output:", res.GetOutput() + if echoOutput: + print "run_command output:", res.GetOutput() else: - print "run command failed!" - print "error:", res.GetError() + if echoOutput: + print "run command failed!" + print "run_command error:", res.GetError() -def do_lldb_disassembly(lldb_commands, lldb_options, exe): - import lldb, lldbutil, atexit +def do_lldb_disassembly(lldb_commands, exe, disassemble_options, num_symbols): + import lldb, lldbutil, atexit, re # Create the debugger instance now. dbg = lldb.SBDebugger.Create() @@ -103,7 +106,50 @@ run_command(ci, 'file %s' % exe, res) # Send the 'image dump symtab' command. - run_command(ci, 'image dump symtab', res) + run_command(ci, 'image dump symtab', res, echoOutput=False) + + if not res.Succeeded(): + print "Symbol table dump failed!" + sys.exit(-2) + + # Do disassembly on the symbols. + # The following line from the 'image dump symtab' gives us a hint as to the + # starting char position of the symbol name. + # Index UserID DSX Type File Address/Value Load Address Size Flags Name + # ------- ------ --- ------------ ------------------ ------------------ ------------------ ---------- ---------------------------------- + # [ 0] 0 Code 0x0000000000000820 0x0000000000000000 0x000e0008 sandbox_init_internal + symtab_dump = res.GetOutput() + symbol_pos = -1 + code_type_pos = -1 + code_type_end = -1 + + # Heuristics: the first 50 lines should give us the answer for symbol_pos and code_type_pos. + for line in symtab_dump.splitlines()[:50]: + print "line:", line + if re.match("^Index.*Name$", line): + symbol_pos = line.rfind('Name') + #print "symbol_pos:", symbol_pos + code_type_pos = line.find('Type') + code_type_end = code_type_pos + 4 + #print "code_type_pos:", code_type_pos + break + + # Disassembly time. + limited = True if num_symbols != -1 else False + if limited: + count = 0 + for line in symtab_dump.splitlines(): + if line[code_type_pos:code_type_end] == 'Code': + symbol = line[symbol_pos:] + #print "symbol:", symbol + cmd = "disassemble %s '%s'" % (disassemble_options, symbol) + run_command(ci, cmd, res) + if limited: + count = count + 1 + print "number of symbols disassembled:", count + if count >= num_symbols: + break + def main(): # This is to set up the Python path to include the pexpect-2.4 dir. @@ -120,32 +166,43 @@ type='string', action='append', metavar='COMMAND', default=[], dest='lldb_commands', help='Command(s) lldb executes after starting up (can be empty)') - parser.add_option('-O', '--lldb-options', - type='string', action='store', - dest='lldb_options', - help="""The options passed to 'lldb' command if specified.""") parser.add_option('-e', '--executable', type='string', action='store', dest='executable', - help="""The executable to do disassembly on.""") + help="""Mandatory: the executable to do disassembly on.""") + parser.add_option('-o', '--options', + type='string', action='store', + dest='disassemble_options', + help="""Mandatory: the options passed to lldb's 'disassemble' command.""") + parser.add_option('-n', '--num-symbols', + type='int', action='store', + dest='num_symbols', + help="""The number of symbols to disassemble, if specified.""") opts, args = parser.parse_args() lldb_commands = opts.lldb_commands - lldb_options = opts.lldb_options - if not opts.executable: + if not opts.executable or not opts.disassemble_options: parser.print_help() sys.exit(1) + executable = opts.executable + disassemble_options = opts.disassemble_options + + if opts.num_symbols: + num_symbols = opts.num_symbols + else: + num_symbols = -1 # We have parsed the options. print "lldb commands:", lldb_commands - print "lldb options:", lldb_options print "executable:", executable + print "disassemble options:", disassemble_options + print "num of symbols to disassemble:", num_symbols setupSysPath() - do_lldb_disassembly(lldb_commands, lldb_options, executable) + do_lldb_disassembly(lldb_commands, executable, disassemble_options, num_symbols) if __name__ == '__main__': main() From ctice at apple.com Tue Mar 29 14:53:44 2011 From: ctice at apple.com (Caroline Tice) Date: Tue, 29 Mar 2011 19:53:44 -0000 Subject: [Lldb-commits] [lldb] r128479 - /lldb/trunk/source/Plugins/Instruction/ARM/EmulateInstructionARM.cpp Message-ID: <20110329195344.7E2052A6C12C@llvm.org> Author: ctice Date: Tue Mar 29 14:53:44 2011 New Revision: 128479 URL: http://llvm.org/viewvc/llvm-project?rev=128479&view=rev Log: Add missing encodings for EmulateMOVRdImm (MOV register) function. Modified: lldb/trunk/source/Plugins/Instruction/ARM/EmulateInstructionARM.cpp Modified: lldb/trunk/source/Plugins/Instruction/ARM/EmulateInstructionARM.cpp URL: http://llvm.org/viewvc/llvm-project/lldb/trunk/source/Plugins/Instruction/ARM/EmulateInstructionARM.cpp?rev=128479&r1=128478&r2=128479&view=diff ============================================================================== --- lldb/trunk/source/Plugins/Instruction/ARM/EmulateInstructionARM.cpp (original) +++ lldb/trunk/source/Plugins/Instruction/ARM/EmulateInstructionARM.cpp Tue Mar 29 14:53:44 2011 @@ -681,21 +681,66 @@ uint32_t carry; // the carry bit after ThumbExpandImm_C or ARMExpandImm_C. bool setflags; switch (encoding) { - case eEncodingT1: - Rd = Bits32(opcode, 10, 8); - setflags = !InITBlock(); - imm32 = Bits32(opcode, 7, 0); // imm32 = ZeroExtend(imm8, 32) - carry = APSR_C; - break; - case eEncodingT2: - Rd = Bits32(opcode, 11, 8); - setflags = BitIsSet(opcode, 20); - imm32 = ThumbExpandImm_C(opcode, APSR_C, carry); - if (BadReg(Rd)) + case eEncodingT1: + Rd = Bits32(opcode, 10, 8); + setflags = !InITBlock(); + imm32 = Bits32(opcode, 7, 0); // imm32 = ZeroExtend(imm8, 32) + carry = APSR_C; + + break; + + case eEncodingT2: + Rd = Bits32(opcode, 11, 8); + setflags = BitIsSet(opcode, 20); + imm32 = ThumbExpandImm_C(opcode, APSR_C, carry); + if (BadReg(Rd)) + return false; + + break; + + case eEncodingT3: + { + // d = UInt(Rd); setflags = FALSE; imm32 = ZeroExtend(imm4:i:imm3:imm8, 32); + Rd = Bits32 (opcode, 11, 8); + setflags = false; + uint32_t imm4 = Bits32 (opcode, 19, 16); + uint32_t imm3 = Bits32 (opcode, 14, 12); + uint32_t i = Bit32 (opcode, 26); + uint32_t imm8 = Bits32 (opcode, 7, 0); + imm32 = (imm4 << 12) | (i << 11) | (imm3 << 8) | imm8; + + // if BadReg(d) then UNPREDICTABLE; + if (BadReg (Rd)) + return false; + } + break; + + case eEncodingA1: + // if Rd == ???1111??? && S == ???1??? then SEE SUBS PC, LR and related instructions; + // d = UInt(Rd); setflags = (S == ???1???); (imm32, carry) = ARMExpandImm_C(imm12, APSR.C); + Rd = Bits32 (opcode, 15, 12); + setflags = BitIsSet (opcode, 20); + imm32 = ARMExpandImm_C (opcode, APSR_C, carry); + + break; + + case eEncodingA2: + { + // d = UInt(Rd); setflags = FALSE; imm32 = ZeroExtend(imm4:imm12, 32); + Rd = Bits32 (opcode, 15, 12); + setflags = false; + uint32_t imm4 = Bits32 (opcode, 19, 16); + uint32_t imm12 = Bits32 (opcode, 11, 0); + imm32 = (imm4 << 12) | imm12; + + // if d == 15 then UNPREDICTABLE; + if (Rd == 15) + return false; + } + break; + + default: return false; - break; - default: - return false; } uint32_t result = imm32; @@ -9242,7 +9287,9 @@ // tst (register) { 0x0ff0f010, 0x01100000, ARMvAll, eEncodingA1, eSize32, &EmulateInstructionARM::EmulateTSTReg, "tst , {,}"}, - + // mov (immediate) + { 0x0fef0000, 0x03a00000, ARMvAll, eEncodingA1, eSize32, &EmulateInstructionARM::EmulateMOVRdImm, "mov{s} , #"}, + { 0x0ff00000, 0x03000000, ARMV6T2_ABOVE, eEncodingA2, eSize32, &EmulateInstructionARM::EmulateMOVRdImm, "movw , #" }, // mov (register) { 0x0fef0ff0, 0x01a00000, ARMvAll, eEncodingA1, eSize32, &EmulateInstructionARM::EmulateMOVRdRm, "mov{s} , "}, // mvn (immediate) @@ -9490,6 +9537,7 @@ // move immediate { 0xfffff800, 0x00002000, ARMvAll, eEncodingT1, eSize16, &EmulateInstructionARM::EmulateMOVRdImm, "movs|mov , #imm8"}, { 0xfbef8000, 0xf04f0000, ARMV6T2_ABOVE, eEncodingT2, eSize32, &EmulateInstructionARM::EmulateMOVRdImm, "mov{s}.w , #"}, + { 0xfbf08000, 0xf2400000, ARMV6T2_ABOVE, eEncodingT3, eSize32, &EmulateInstructionARM::EmulateMOVRdImm, "movw ,#"}, // mvn (immediate) { 0xfbef8000, 0xf06f0000, ARMV6T2_ABOVE, eEncodingT1, eSize32, &EmulateInstructionARM::EmulateMVNImm, "mvn{s} , #"}, // mvn (register) From ctice at apple.com Tue Mar 29 16:24:06 2011 From: ctice at apple.com (Caroline Tice) Date: Tue, 29 Mar 2011 21:24:06 -0000 Subject: [Lldb-commits] [lldb] r128491 - in /lldb/trunk: include/lldb/Core/EmulateInstruction.h source/Plugins/Instruction/ARM/EmulateInstructionARM.cpp source/Plugins/Instruction/ARM/EmulateInstructionARM.h Message-ID: <20110329212406.829AE2A6C12C@llvm.org> Author: ctice Date: Tue Mar 29 16:24:06 2011 New Revision: 128491 URL: http://llvm.org/viewvc/llvm-project?rev=128491&view=rev Log: Add subtraction context. Add code to emulate SUB (SP minus register) ARM instruction. Add stubs for other ARM emulation functions that need to be written. Modified: lldb/trunk/include/lldb/Core/EmulateInstruction.h lldb/trunk/source/Plugins/Instruction/ARM/EmulateInstructionARM.cpp lldb/trunk/source/Plugins/Instruction/ARM/EmulateInstructionARM.h Modified: lldb/trunk/include/lldb/Core/EmulateInstruction.h URL: http://llvm.org/viewvc/llvm-project/lldb/trunk/include/lldb/Core/EmulateInstruction.h?rev=128491&r1=128490&r2=128491&view=diff ============================================================================== --- lldb/trunk/include/lldb/Core/EmulateInstruction.h (original) +++ lldb/trunk/include/lldb/Core/EmulateInstruction.h Tue Mar 29 16:24:06 2011 @@ -139,6 +139,8 @@ eContextMultiplication, eContextAddition, + + eContextSubtraction, eContextReturnFromException }; Modified: lldb/trunk/source/Plugins/Instruction/ARM/EmulateInstructionARM.cpp URL: http://llvm.org/viewvc/llvm-project/lldb/trunk/source/Plugins/Instruction/ARM/EmulateInstructionARM.cpp?rev=128491&r1=128490&r2=128491&view=diff ============================================================================== --- lldb/trunk/source/Plugins/Instruction/ARM/EmulateInstructionARM.cpp (original) +++ lldb/trunk/source/Plugins/Instruction/ARM/EmulateInstructionARM.cpp Tue Mar 29 16:24:06 2011 @@ -9171,6 +9171,689 @@ } return true; } + +// A8.6.216 SUB (SP minus register) +bool +EmulateInstructionARM::EmulateSUBSPReg (const uint32_t opcode, const ARMEncoding encoding) +{ +#if 0 + if ConditionPassed() then + EncodingSpecificOperations(); + shifted = Shift(R[m], shift_t, shift_n, APSR.C); + (result, carry, overflow) = AddWithCarry(SP, NOT(shifted), ???1???); + if d == 15 then // Can only occur for ARM encoding + ALUWritePC(result); // setflags is always FALSE here + else + R[d] = result; + if setflags then + APSR.N = result<31>; + APSR.Z = IsZeroBit(result); + APSR.C = carry; + APSR.V = overflow; +#endif + + bool success = false; + + if (ConditionPassed(opcode)) + { + uint32_t d; + uint32_t m; + bool setflags; + ARM_ShifterType shift_t; + uint32_t shift_n; + + switch (encoding) + { + case eEncodingT1: + // d = UInt(Rd); m = UInt(Rm); setflags = (S == ???1???); + d = Bits32 (opcode, 11, 8); + m = Bits32 (opcode, 3, 0); + setflags = BitIsSet (opcode, 20); + + // (shift_t, shift_n) = DecodeImmShift(type, imm3:imm2); + shift_n = DecodeImmShiftThumb (opcode, shift_t); + + // if d == 13 && (shift_t != SRType_LSL || shift_n > 3) then UNPREDICTABLE; + if ((d == 13) && ((shift_t != SRType_LSL) || (shift_n > 3))) + return false; + + // if d == 15 || BadReg(m) then UNPREDICTABLE; + if ((d == 15) || BadReg (m)) + return false; + break; + + case eEncodingA1: + // if Rd == ???1111??? && S == ???1??? then SEE SUBS PC, LR and related instructions; + // d = UInt(Rd); m = UInt(Rm); setflags = (S == ???1???); + d = Bits32 (opcode, 15, 12); + m = Bits32 (opcode, 3, 0); + setflags = BitIsSet (opcode, 20); + + // (shift_t, shift_n) = DecodeImmShift(type, imm5); + shift_n = DecodeImmShiftARM (opcode, shift_t); + break; + + default: + return false; + } + + // shifted = Shift(R[m], shift_t, shift_n, APSR.C); + uint32_t Rm = ReadCoreReg (m, &success); + if (!success) + return false; + + uint32_t shifted = Shift (Rm, shift_t, shift_n, APSR_C); + + // (result, carry, overflow) = AddWithCarry(SP, NOT(shifted), ???1???); + uint32_t sp_val = ReadCoreReg (SP_REG, &success); + if (!success) + return false; + + AddWithCarryResult res = AddWithCarry (sp_val, ~shifted, 1); + + EmulateInstruction::Context context; + context.type = eContextSubtraction; + Register sp_reg; + sp_reg.SetRegister (eRegisterKindDWARF, dwarf_sp); + Register dwarf_reg; + dwarf_reg.SetRegister (eRegisterKindDWARF, dwarf_r0 + m); + context.SetRegisterRegisterOperands (sp_reg, dwarf_reg); + + uint32_t regnum = dwarf_r0 + d; + + if (!WriteCoreRegOptionalFlags(context, res.result, regnum, setflags, res.carry_out, res.overflow)) + return false; + } + return true; +} + + +// A8.6.7 ADD (register-shifted register) +bool +EmulateInstructionARM::EmulateAddRegShift (const uint32_t opcode, const ARMEncoding encoding) +{ +#if 0 +#endif + + //bool success = false; + + if (ConditionPassed(opcode)) + { + switch (encoding) + { + } + } + return true; +} + +// A8.6.213 SUB (register) +bool +EmulateInstructionARM::EmulateSUBReg (const uint32_t opcode, const ARMEncoding encoding) +{ +#if 0 +#endif + + //bool success = false; + + if (ConditionPassed(opcode)) + { + switch (encoding) + { + } + } + return true; +} + +// A8.6.202 STREX +bool +EmulateInstructionARM::EmulateSTREX (const uint32_t opcode, const ARMEncoding encoding) +{ +#if 0 +#endif + + //bool success = false; + + if (ConditionPassed(opcode)) + { + switch (encoding) + { + } + } + return true; +} + +// A8.6.197 STRB (immediate, ARM) +bool +EmulateInstructionARM::EmulateSTRBImmARM (const uint32_t opcode, const ARMEncoding encoding) +{ +#if 0 +#endif + + //bool success = false; + + if (ConditionPassed(opcode)) + { + switch (encoding) + { + } + } + return true; +} + +// A8.6.194 STR (immediate, ARM) +bool +EmulateInstructionARM::EmulateSTRImmARM (const uint32_t opcode, const ARMEncoding encoding) +{ +#if 0 +#endif + + //bool success = false; + + if (ConditionPassed(opcode)) + { + switch (encoding) + { + } + } + return true; +} + +// A8.6.74 LDRH (immediate, ARM) +bool +EmulateInstructionARM::EmulateLDRHImmediateARM (const uint32_t opcode, const ARMEncoding encoding) +{ +#if 0 +#endif + + //bool success = false; + + if (ConditionPassed(opcode)) + { + switch (encoding) + { + } + } + return true; +} + +// A8.6.69 LDREX +bool +EmulateInstructionARM::EmulateLDREX (const uint32_t opcode, const ARMEncoding encoding) +{ +#if 0 +#endif + + //bool success = false; + + if (ConditionPassed(opcode)) + { + switch (encoding) + { + } + } + return true; +} + +// A8.6.62 LDRB (immediate, ARM) +bool +EmulateInstructionARM::EmulateLDRBImmediateARM (const uint32_t opcode, const ARMEncoding encoding) +{ +#if 0 +#endif + + //bool success = false; + + if (ConditionPassed(opcode)) + { + switch (encoding) + { + } + } + return true; +} + +// A8.6.59 LDR (literal) +bool +EmulateInstructionARM::EmulateLDRLiteral (const uint32_t opcode, const ARMEncoding encoding) +{ +#if 0 +#endif + + //bool success = false; + + if (ConditionPassed(opcode)) + { + switch (encoding) + { + } + } + return true; +} + + + +// A8.6.65 LDRBT +bool +EmulateInstructionARM::EmulateLDRBT (const uint32_t opcode, const ARMEncoding encoding) +{ +#if 0 +#endif + + //bool success = false; + + if (ConditionPassed(opcode)) + { + switch (encoding) + { + } + } + return true; +} + + +// A8.6.66 LDRD (immediate) +bool +EmulateInstructionARM::EmulateLDRDImmediate (const uint32_t opcode, const ARMEncoding encoding) +{ +#if 0 +#endif + + //bool success = false; + + if (ConditionPassed(opcode)) + { + switch (encoding) + { + } + } + return true; +} + + +// A8.6.67 LDRD (literal) +bool +EmulateInstructionARM::EmulateLDRDLiteral (const uint32_t opcode, const ARMEncoding encoding) +{ +#if 0 +#endif + + //bool success = false; + + if (ConditionPassed(opcode)) + { + switch (encoding) + { + } + } + return true; +} + + +// A8.6.68 LDRD (register) +bool +EmulateInstructionARM::EmulateLDRDRegister (const uint32_t opcode, const ARMEncoding encoding) +{ +#if 0 +#endif + + //bool success = false; + + if (ConditionPassed(opcode)) + { + switch (encoding) + { + } + } + return true; +} + + +// A8.6.70 LDREXB +bool +EmulateInstructionARM::EmulateLDREXB (const uint32_t opcode, const ARMEncoding encoding) +{ +#if 0 +#endif + + //bool success = false; + + if (ConditionPassed(opcode)) + { + switch (encoding) + { + } + } + return true; +} + + +// A8.6.71 LDREXD +bool +EmulateInstructionARM::EmulateLDREXD (const uint32_t opcode, const ARMEncoding encoding) +{ +#if 0 +#endif + + //bool success = false; + + if (ConditionPassed(opcode)) + { + switch (encoding) + { + } + } + return true; +} + + +// A8.6.72 LDREXH +bool +EmulateInstructionARM::EmulateLDREXH (const uint32_t opcode, const ARMEncoding encoding) +{ +#if 0 +#endif + + //bool success = false; + + if (ConditionPassed(opcode)) + { + switch (encoding) + { + } + } + return true; +} + + + +// A8.6.77 LDRHT +bool +EmulateInstructionARM::EmulateLDRHT (const uint32_t opcode, const ARMEncoding encoding) +{ +#if 0 +#endif + + //bool success = false; + + if (ConditionPassed(opcode)) + { + switch (encoding) + { + } + } + return true; +} + + +// A8.6.81 LDRSBT +bool +EmulateInstructionARM::EmulateLDRSBT (const uint32_t opcode, const ARMEncoding encoding) +{ +#if 0 +#endif + + //bool success = false; + + if (ConditionPassed(opcode)) + { + switch (encoding) + { + } + } + return true; +} + + +// A8.6.85 LDRSHT +bool +EmulateInstructionARM::EmulateLDRSHT (const uint32_t opcode, const ARMEncoding encoding) +{ +#if 0 +#endif + + //bool success = false; + + if (ConditionPassed(opcode)) + { + switch (encoding) + { + } + } + return true; +} + + +// A8.6.86 LDRT +bool +EmulateInstructionARM::EmulateLDRT (const uint32_t opcode, const ARMEncoding encoding) +{ +#if 0 +#endif + + //bool success = false; + + if (ConditionPassed(opcode)) + { + switch (encoding) + { + } + } + return true; +} + + + +// A8.6.198 STRB (register) +bool +EmulateInstructionARM::EmulateSTRBReg (const uint32_t opcode, const ARMEncoding encoding) +{ +#if 0 +#endif + + //bool success = false; + + if (ConditionPassed(opcode)) + { + switch (encoding) + { + } + } + return true; +} + + +// A8.6.199 STRBT +bool +EmulateInstructionARM::EmulateSTRBT (const uint32_t opcode, const ARMEncoding encoding) +{ +#if 0 +#endif + + //bool success = false; + + if (ConditionPassed(opcode)) + { + switch (encoding) + { + } + } + return true; +} + + +// A8.6.200 STRD (immediate) +bool +EmulateInstructionARM::EmulateSTRDImm (const uint32_t opcode, const ARMEncoding encoding) +{ +#if 0 +#endif + + //bool success = false; + + if (ConditionPassed(opcode)) + { + switch (encoding) + { + } + } + return true; +} + + +// A8.6.201 STRD (register) +bool +EmulateInstructionARM::EmulateSTRDReg (const uint32_t opcode, const ARMEncoding encoding) +{ +#if 0 +#endif + + //bool success = false; + + if (ConditionPassed(opcode)) + { + switch (encoding) + { + } + } + return true; +} + + +// A8.6.203 STREXB +bool +EmulateInstructionARM::EmulateSTREXB (const uint32_t opcode, const ARMEncoding encoding) +{ +#if 0 +#endif + + //bool success = false; + + if (ConditionPassed(opcode)) + { + switch (encoding) + { + } + } + return true; +} + + +// A8.6.204 STREXD +bool +EmulateInstructionARM::EmulateSTREXD (const uint32_t opcode, const ARMEncoding encoding) +{ +#if 0 +#endif + + //bool success = false; + + if (ConditionPassed(opcode)) + { + switch (encoding) + { + } + } + return true; +} + + +// A8.6.205 STREXH +bool +EmulateInstructionARM::EmulateSTREXH (const uint32_t opcode, const ARMEncoding encoding) +{ +#if 0 +#endif + + //bool success = false; + + if (ConditionPassed(opcode)) + { + switch (encoding) + { + } + } + return true; +} + + +// A8.6.206 STRH (immediate, Thumb) +bool +EmulateInstructionARM::EmulateSTRHImmThumb (const uint32_t opcode, const ARMEncoding encoding) +{ +#if 0 +#endif + + //bool success = false; + + if (ConditionPassed(opcode)) + { + switch (encoding) + { + } + } + return true; +} + + +// A8.6.207 STRH (immediate, ARM) +bool +EmulateInstructionARM::EmulateSTRHImmARM (const uint32_t opcode, const ARMEncoding encoding) +{ +#if 0 +#endif + + //bool success = false; + + if (ConditionPassed(opcode)) + { + switch (encoding) + { + } + } + return true; +} + + + +// A8.6.209 STRHT +bool +EmulateInstructionARM::EmulateSTRHT (const uint32_t opcode, const ARMEncoding encoding) +{ +#if 0 +#endif + + //bool success = false; + + if (ConditionPassed(opcode)) + { + switch (encoding) + { + } + } + return true; +} + + +// A8.6.210 STRT +bool +EmulateInstructionARM::EmulateSTRT (const uint32_t opcode, const ARMEncoding encoding) +{ +#if 0 +#endif + + // bool success = false; + + if (ConditionPassed(opcode)) + { + switch (encoding) + { + } + } + return true; +} + + + EmulateInstructionARM::ARMOpcode* EmulateInstructionARM::GetARMOpcodeForInstruction (const uint32_t opcode) @@ -9196,6 +9879,7 @@ // adjust the stack pointer { 0x0ffff000, 0x024dd000, ARMvAll, eEncodingA1, eSize32, &EmulateInstructionARM::EmulateSUBSPImm, "sub sp, sp, #"}, + { 0x0fef0010, 0x004d0000, ARMvAll, eEncodingA1, eSize32, &EmulateInstructionARM::EmulateSUBSPReg, "sub{s} , sp, {,}" }, // push one register // if Rn == '1101' && imm12 == '000000000100' then SEE PUSH; @@ -9407,6 +10091,7 @@ { 0xffffff80, 0x0000b080, ARMvAll, eEncodingT1, eSize16, &EmulateInstructionARM::EmulateSUBSPImm, "sub sp, sp, #imm"}, { 0xfbef8f00, 0xf1ad0d00, ARMV6T2_ABOVE, eEncodingT2, eSize32, &EmulateInstructionARM::EmulateSUBSPImm, "sub.w sp, sp, #"}, { 0xfbff8f00, 0xf2ad0d00, ARMV6T2_ABOVE, eEncodingT3, eSize32, &EmulateInstructionARM::EmulateSUBSPImm, "subw sp, sp, #imm12"}, + { 0xffef8000, 0xebad0000, ARMV6T2_ABOVE, eEncodingT1, eSize32, &EmulateInstructionARM::EmulateSUBSPReg, "sub{s} , sp, {,}" }, // vector push consecutive extension register(s) { 0xffbf0f00, 0xed2d0b00, ARMV6T2_ABOVE, eEncodingT1, eSize32, &EmulateInstructionARM::EmulateVPUSH, "vpush.64 "}, Modified: lldb/trunk/source/Plugins/Instruction/ARM/EmulateInstructionARM.h URL: http://llvm.org/viewvc/llvm-project/lldb/trunk/source/Plugins/Instruction/ARM/EmulateInstructionARM.h?rev=128491&r1=128490&r2=128491&view=diff ============================================================================== --- lldb/trunk/source/Plugins/Instruction/ARM/EmulateInstructionARM.h (original) +++ lldb/trunk/source/Plugins/Instruction/ARM/EmulateInstructionARM.h Tue Mar 29 16:24:06 2011 @@ -371,6 +371,10 @@ // A8.6.215 SUB (SP minus immediate) bool EmulateSUBSPImm (const uint32_t opcode, const ARMEncoding encoding); + + // A8.6.216 SUB (SP minus register) + bool + EmulateSUBSPReg (const uint32_t opcode, const ARMEncoding encoding); // A8.6.194 STR (immediate, ARM) -- Rn == sp bool @@ -415,6 +419,10 @@ // A8.6.6 ADD (register) bool EmulateADDReg (const uint32_t opcode, const ARMEncoding encoding); + + // A8.6.7 ADD (register-shifted register) + bool + EmulateAddRegShift (const uint32_t opcode, const ARMEncoding encoding); // A8.6.97 MOV (register) bool @@ -476,6 +484,8 @@ bool EmulateShiftReg (const uint32_t opcode, const ARMEncoding encoding, ARM_ShifterType shift_type); + // LOAD FUNCTIONS + // A8.6.53 LDM/LDMIA/LDMFD bool EmulateLDM (const uint32_t opcode, const ARMEncoding encoding); @@ -496,37 +506,212 @@ bool EmulateLDRRtRnImm (const uint32_t opcode, const ARMEncoding encoding); - // A8.6.188 STM/STMIA/STMEA + // A8.6.58 LDR (immediate, ARM) - Encoding A1 + bool + EmulateLDRImmediateARM (const uint32_t opcode, const ARMEncoding encoding); + + // A8.6.59 LDR (literal) + bool + EmulateLDRLiteral (const uint32_t, const ARMEncoding encoding); + + // A8.6.60 LDR (register) - Encoding T1, T2, A1 + bool + EmulateLDRRegister (const uint32_t opcode, const ARMEncoding encoding); + + // A8.6.61 LDRB (immediate, Thumb) - Encoding T1, T2, T3 + bool + EmulateLDRBImmediate (const uint32_t opcode, const ARMEncoding encoding); + + // A8.6.62 LDRB (immediate, ARM) + bool + EmulateLDRBImmediateARM (const uint32_t opcode, const ARMEncoding encoding); + + // A8.6.63 LDRB (literal) - Encoding T1, A1 + bool + EmulateLDRBLiteral (const uint32_t opcode, const ARMEncoding encoding); + + // A8.6.64 LDRB (register) - Encoding T1, T2, A1 + bool + EmulateLDRBRegister (const uint32_t opcode, const ARMEncoding encoding); + + // A8.6.65 LDRBT + bool + EmulateLDRBT (const uint32_t opcode, const ARMEncoding encoding); + + // A8.6.66 LDRD (immediate) + bool + EmulateLDRDImmediate (const uint32_t opcode, const ARMEncoding encoding); + + // A8.6.67 + bool + EmulateLDRDLiteral (const uint32_t opcode, const ARMEncoding encoding); + + // A8.6.68 LDRD (register) + bool + EmulateLDRDRegister (const uint32_t opcode, const ARMEncoding encoding); + + // A8.6.69 LDREX + bool + EmulateLDREX (const uint32_t opcode, const ARMEncoding encoding); + + // A8.6.70 LDREXB + bool + EmulateLDREXB (const uint32_t opcode, const ARMEncoding encoding); + + // A8.6.71 LDREXD + bool + EmulateLDREXD (const uint32_t opcode, const ARMEncoding encoding); + + // A8.6.72 LDREXH + bool + EmulateLDREXH (const uint32_t opcode, const ARMEncoding encoding); + + // A8.6.73 LDRH (immediate, Thumb) - Encoding T1, T2, T3 + bool + EmulateLDRHImmediate (const uint32_t opcode, const ARMEncoding encoding); + + // A8.6.74 LDRS (immediate, ARM) + bool + EmulateLDRHImmediateARM (const uint32_t opcode, const ARMEncoding encoding); + + // A8.6.75 LDRH (literal) - Encoding T1, A1 + bool + EmulateLDRHLiteral (const uint32_t opcode, const ARMEncoding encoding); + + // A8.6.76 LDRH (register) - Encoding T1, T2, A1 + bool + EmulateLDRHRegister (const uint32_t opcode, const ARMEncoding encoding); + + // A8.6.77 LDRHT + bool + EmulateLDRHT (const uint32_t opcode, const ARMEncoding encoding); + + // A8.6.78 LDRSB (immediate) - Encoding T1, T2, A1 + bool + EmulateLDRSBImmediate (const uint32_t opcode, const ARMEncoding encoding); + + // A8.6.79 LDRSB (literal) - Encoding T1, A1 + bool + EmulateLDRSBLiteral (const uint32_t opcode, const ARMEncoding encoding); + + // A8.6.80 LDRSB (register) - Encoding T1, T2, A1 + bool + EmulateLDRSBRegister (const uint32_t opcode, const ARMEncoding encoding); + + // A8.6.81 LDRSBT + bool + EmulateLDRSBT (const uint32_t opcode, const ARMEncoding encoding); + + // A8.6.82 LDRSH (immediate) - Encoding T1, T2, A1 + bool + EmulateLDRSHImmediate (const uint32_t opcode, const ARMEncoding encoding); + + // A8.6.83 LDRSH (literal) - Encoding T1, A1 + bool + EmulateLDRSHLiteral (const uint32_t opcode, const ARMEncoding encoding); + + // A8.6.84 LDRSH (register) - Encoding T1, T2, A1 + bool + EmulateLDRSHRegister (const uint32_t opcode, const ARMEncoding encoding); + + // A8.6.85 LDRSHT + bool + EmulateLDRSHT (const uint32_t opcode, const ARMEncoding encoding); + + // A8.6.86 + bool + EmulateLDRT (const uint32_t opcode, const ARMEncoding encoding); + + + // STORE FUNCTIONS + + // A8.6.189 STM/STMIA/STMEA bool EmulateSTM (const uint32_t opcode, const ARMEncoding encoding); - // A8.6.189 STMDA/STMED + // A8.6.190 STMDA/STMED bool EmulateSTMDA (const uint32_t opcode, const ARMEncoding encoding); - // A8.6.190 STMDB/STMFD + // A8.6.191 STMDB/STMFD bool EmulateSTMDB (const uint32_t opcode, const ARMEncoding encoding); - // A8.6.191 STMIB/STMFA + // A8.6.192 STMIB/STMFA bool EmulateSTMIB (const uint32_t opcode, const ARMEncoding encoding); - // A8.6.192 STR (immediate, Thumb) + // A8.6.193 STR (immediate, Thumb) bool EmulateSTRThumb(const uint32_t opcode, const ARMEncoding encoding); + + // A8.6.194 STR (immediate, ARM) + bool + EmulateSTRImmARM (const uint32_t opcode, const ARMEncoding encoding); - // A8.6.194 STR (register) + // A8.6.195 STR (register) bool EmulateSTRRegister (const uint32_t opcode, const ARMEncoding encoding); - // A8.6.195 STRB (immediate, Thumb) + // A8.6.196 STRB (immediate, Thumb) bool EmulateSTRBThumb (const uint32_t opcode, const ARMEncoding encoding); - - // A8.6.207 STRH (register) + + // A8.6.197 STRB (immediate, ARM) + bool + EmulateSTRBImmARM (const uint32_t opcode, const ARMEncoding encoding); + + // A8.6.198 STRB (register) + bool + EmulateSTRBReg (const uint32_t opcode, const ARMEncoding encoding); + + // A8.6.199 STRBT + bool + EmulateSTRBT (const uint32_t opcode, const ARMEncoding encoding); + + // A8.6.200 STRD (immediate) + bool + EmulateSTRDImm (const uint32_t opcode, const ARMEncoding encoding); + + // A8.6.201 STRD (register) + bool + EmulateSTRDReg (const uint32_t opcode, const ARMEncoding encoding); + + // A8.6.202 STREX + bool + EmulateSTREX (const uint32_t opcode, const ARMEncoding encoding); + + // A8.6.203 STREXB + bool + EmulateSTREXB (const uint32_t opcode, const ARMEncoding encoding); + + // A8.6.204 STREXD + bool + EmulateSTREXD (const uint32_t opcode, const ARMEncoding encoding); + + // A8.6.205 STREXH + bool + EmulateSTREXH (const uint32_t opcode, const ARMEncoding encoding); + + // A8.6.206 STRH (immediate, Thumb) + bool + EmulateSTRHImmThumb (const uint32_t opcode, const ARMEncoding encoding); + + // A8.6.207 STRH (immediate, ARM) + bool + EmulateSTRHImmARM (const uint32_t opcode, const ARMEncoding encoding); + + // A8.6.208 STRH (register) bool EmulateSTRHRegister (const uint32_t opcode, const ARMEncoding encoding); + + // A8.6.209 STRHT + bool + EmulateSTRHT (const uint32_t opcode, const ARMEncoding encoding); + + // A8.6.210 STRT + bool + EmulateSTRT (const uint32_t opcode, const ARMEncoding encoding); // A8.6.1 ADC (immediate) bool @@ -576,62 +761,6 @@ bool EmulateEORReg (const uint32_t opcode, const ARMEncoding encoding); - // A8.6.58 LDR (immediate, ARM) - Encoding A1 - bool - EmulateLDRImmediateARM (const uint32_t opcode, const ARMEncoding encoding); - - // A8.6.60 LDR (register) - Encoding T1, T2, A1 - bool - EmulateLDRRegister (const uint32_t opcode, const ARMEncoding encoding); - - // A8.6.61 LDRB (immediate, Thumb) - Encoding T1, T2 - bool - EmulateLDRBImmediate (const uint32_t opcode, const ARMEncoding encoding); - - // A8.6.63 LDRB (literal) - Encoding T1 - bool - EmulateLDRBLiteral (const uint32_t opcode, const ARMEncoding encoding); - - // A8.6.64 LDRB (register) - Encoding T1 - bool - EmulateLDRBRegister (const uint32_t opcode, const ARMEncoding encoding); - - // A8.6.73 LDRH (immediate, Thumb) - Encoding T1, T2 - bool - EmulateLDRHImmediate (const uint32_t opcode, const ARMEncoding encoding); - - // A8.6.75 LDRH (literal) - Encoding T1 - bool - EmulateLDRHLiteral (const uint32_t opcode, const ARMEncoding encoding); - - // A8.6.76 LDRH (register) - Encoding T1, T2 - bool - EmulateLDRHRegister (const uint32_t opcode, const ARMEncoding encoding); - - // A8.6.78 LDRSB (immediate) - Encoding T1 - bool - EmulateLDRSBImmediate (const uint32_t opcode, const ARMEncoding encoding); - - // A8.6.79 LDRSB (literal) - Encoding T1 - bool - EmulateLDRSBLiteral (const uint32_t opcode, const ARMEncoding encoding); - - // A8.6.80 LDRSB (register) - Encoding T1, T2 - bool - EmulateLDRSBRegister (const uint32_t opcode, const ARMEncoding encoding); - - // A8.6.82 LDRSH (immediate) - Encoding T1 - bool - EmulateLDRSHImmediate (const uint32_t opcode, const ARMEncoding encoding); - - // A8.6.83 LDRSH (literal) - Encoding T1 - bool - EmulateLDRSHLiteral (const uint32_t opcode, const ARMEncoding encoding); - - // A8.6.84 LDRSH (register) - Encoding T1, T2 - bool - EmulateLDRSHRegister (const uint32_t opcode, const ARMEncoding encoding); - // A8.6.105 MUL bool EmulateMUL (const uint32_t opcode, const ARMEncoding encoding); @@ -695,6 +824,14 @@ // A8.6.212 SUB (immediate, ARM) bool EmulateSUBImmARM (const uint32_t opcode, const ARMEncoding encoding); + + // A8.6.213 SUB (register) + bool + EmulateSUBReg (const uint32_t opcode, const ARMEncoding encoding); + + // A8.6.214 SUB (register-shifted register) + bool + EmulateSUBRegShift (const uint32_t opcode, const ARMEncoding encoding); // A8.6.222 SXTB - Encoding T1 bool From jingham at apple.com Tue Mar 29 16:45:47 2011 From: jingham at apple.com (Jim Ingham) Date: Tue, 29 Mar 2011 21:45:47 -0000 Subject: [Lldb-commits] [lldb] r128493 - /lldb/trunk/source/Plugins/Process/gdb-remote/ProcessGDBRemote.cpp Message-ID: <20110329214547.378902A6C12C@llvm.org> Author: jingham Date: Tue Mar 29 16:45:47 2011 New Revision: 128493 URL: http://llvm.org/viewvc/llvm-project?rev=128493&view=rev Log: Can't just call "rand" to get a random port, 'cause then you'll get the same sequence in two lldb's. This makes running lldb on lldb not work very well. Modified: lldb/trunk/source/Plugins/Process/gdb-remote/ProcessGDBRemote.cpp Modified: lldb/trunk/source/Plugins/Process/gdb-remote/ProcessGDBRemote.cpp URL: http://llvm.org/viewvc/llvm-project/lldb/trunk/source/Plugins/Process/gdb-remote/ProcessGDBRemote.cpp?rev=128493&r1=128492&r2=128493&view=diff ============================================================================== --- lldb/trunk/source/Plugins/Process/gdb-remote/ProcessGDBRemote.cpp (original) +++ lldb/trunk/source/Plugins/Process/gdb-remote/ProcessGDBRemote.cpp Tue Mar 29 16:45:47 2011 @@ -54,9 +54,16 @@ using namespace lldb; using namespace lldb_private; +static bool rand_initialized = false; + static inline uint16_t get_random_port () { + if (!rand_initialized) + { + rand_initialized = true; + sranddev(); + } return (rand() % (UINT16_MAX - 1000u)) + 1000u; } From ctice at apple.com Tue Mar 29 18:03:16 2011 From: ctice at apple.com (Caroline Tice) Date: Tue, 29 Mar 2011 23:03:16 -0000 Subject: [Lldb-commits] [lldb] r128500 - in /lldb/trunk/source/Plugins/Instruction/ARM: EmulateInstructionARM.cpp EmulateInstructionARM.h Message-ID: <20110329230316.EDF372A6C12C@llvm.org> Author: ctice Date: Tue Mar 29 18:03:16 2011 New Revision: 128500 URL: http://llvm.org/viewvc/llvm-project?rev=128500&view=rev Log: Fill in code in EmulateADDRegShift, to emulate the ADD (register-shifted register) ARM instruction. Modified: lldb/trunk/source/Plugins/Instruction/ARM/EmulateInstructionARM.cpp lldb/trunk/source/Plugins/Instruction/ARM/EmulateInstructionARM.h Modified: lldb/trunk/source/Plugins/Instruction/ARM/EmulateInstructionARM.cpp URL: http://llvm.org/viewvc/llvm-project/lldb/trunk/source/Plugins/Instruction/ARM/EmulateInstructionARM.cpp?rev=128500&r1=128499&r2=128500&view=diff ============================================================================== --- lldb/trunk/source/Plugins/Instruction/ARM/EmulateInstructionARM.cpp (original) +++ lldb/trunk/source/Plugins/Instruction/ARM/EmulateInstructionARM.cpp Tue Mar 29 18:03:16 2011 @@ -9270,18 +9270,96 @@ // A8.6.7 ADD (register-shifted register) bool -EmulateInstructionARM::EmulateAddRegShift (const uint32_t opcode, const ARMEncoding encoding) +EmulateInstructionARM::EmulateADDRegShift (const uint32_t opcode, const ARMEncoding encoding) { #if 0 + if ConditionPassed() then + EncodingSpecificOperations(); + shift_n = UInt(R[s]<7:0>); + shifted = Shift(R[m], shift_t, shift_n, APSR.C); + (result, carry, overflow) = AddWithCarry(R[n], shifted, ???0???); + R[d] = result; + if setflags then + APSR.N = result<31>; + APSR.Z = IsZeroBit(result); + APSR.C = carry; + APSR.V = overflow; #endif - //bool success = false; + bool success = false; if (ConditionPassed(opcode)) { + uint32_t d; + uint32_t n; + uint32_t m; + uint32_t s; + bool setflags; + ARM_ShifterType shift_t; + switch (encoding) { - } + case eEncodingA1: + // d = UInt(Rd); n = UInt(Rn); m = UInt(Rm); s = UInt(Rs); + d = Bits32 (opcode, 15, 12); + n = Bits32 (opcode, 19, 16); + m = Bits32 (opcode, 3, 0); + s = Bits32 (opcode, 11, 8); + + // setflags = (S == ???1???); shift_t = DecodeRegShift(type); + setflags = BitIsSet (opcode, 20); + shift_t = DecodeRegShift (Bits32 (opcode, 6, 5)); + + // if d == 15 || n == 15 || m == 15 || s == 15 then UNPREDICTABLE; + if ((d == 15) || (m == 15) || (m == 15) || (s == 15)) + return false; + break; + + default: + return false; + } + + // shift_n = UInt(R[s]<7:0>); + uint32_t Rs = ReadCoreReg (s, &success); + if (!success) + return false; + + uint32_t shift_n = Bits32 (Rs, 7, 0); + + // shifted = Shift(R[m], shift_t, shift_n, APSR.C); + uint32_t Rm = ReadCoreReg (m, &success); + if (!success) + return false; + + uint32_t shifted = Shift (Rm, shift_t, shift_n, APSR_C); + + // (result, carry, overflow) = AddWithCarry(R[n], shifted, ???0???); + uint32_t Rn = ReadCoreReg (n, &success); + if (!success) + return false; + + AddWithCarryResult res = AddWithCarry (Rn, shifted, 0); + + // R[d] = result; + EmulateInstruction::Context context; + context.type = eContextAddition; + Register reg_n; + reg_n.SetRegister (eRegisterKindDWARF, n); + Register reg_m; + reg_m.SetRegister (eRegisterKindDWARF, m); + + context.SetRegisterRegisterOperands (reg_n, reg_m); + + if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_r0 + d, res.result)) + return false; + + // if setflags then + // APSR.N = result<31>; + // APSR.Z = IsZeroBit(result); + // APSR.C = carry; + // APSR.V = overflow; + if (setflags) + return WriteFlags (context, res.result, res.carry_out, res.overflow); } return true; } @@ -9927,6 +10005,8 @@ { 0x0fe00000, 0x02800000, ARMvAll, eEncodingA1, eSize32, &EmulateInstructionARM::EmulateADDImmARM, "add{s} , , #const"}, // add (register) { 0x0fe00010, 0x00800000, ARMvAll, eEncodingA1, eSize32, &EmulateInstructionARM::EmulateADDReg, "add{s} , , {,}"}, + // add (register-shifted register) + { 0x0fe00090, 0x00800010, ARMvAll, eEncodingA1, eSize32, &EmulateInstructionARM::EmulateADDRegShift, "add{s} , m, , "}, // adr { 0x0fff0000, 0x028f0000, ARMvAll, eEncodingA1, eSize32, &EmulateInstructionARM::EmulateADR, "add , PC, #"}, { 0x0fff0000, 0x024f0000, ARMvAll, eEncodingA2, eSize32, &EmulateInstructionARM::EmulateADR, "sub , PC, #"}, Modified: lldb/trunk/source/Plugins/Instruction/ARM/EmulateInstructionARM.h URL: http://llvm.org/viewvc/llvm-project/lldb/trunk/source/Plugins/Instruction/ARM/EmulateInstructionARM.h?rev=128500&r1=128499&r2=128500&view=diff ============================================================================== --- lldb/trunk/source/Plugins/Instruction/ARM/EmulateInstructionARM.h (original) +++ lldb/trunk/source/Plugins/Instruction/ARM/EmulateInstructionARM.h Tue Mar 29 18:03:16 2011 @@ -422,7 +422,7 @@ // A8.6.7 ADD (register-shifted register) bool - EmulateAddRegShift (const uint32_t opcode, const ARMEncoding encoding); + EmulateADDRegShift (const uint32_t opcode, const ARMEncoding encoding); // A8.6.97 MOV (register) bool From wilsons at start.ca Tue Mar 29 18:20:06 2011 From: wilsons at start.ca (Stephen Wilson) Date: Tue, 29 Mar 2011 19:20:06 -0400 Subject: [Lldb-commits] [lldb] r128493 - /lldb/trunk/source/Plugins/Process/gdb-remote/ProcessGDBRemote.cpp In-Reply-To: <20110329214547.378902A6C12C@llvm.org> References: <20110329214547.378902A6C12C@llvm.org> Message-ID: <20110329232005.GA20927@fibrous.localdomain> Hi Jim. On Tue, Mar 29, 2011 at 09:45:47PM -0000, Jim Ingham wrote: > get_random_port () > { > + if (!rand_initialized) > + { > + rand_initialized = true; > + sranddev(); > + } > return (rand() % (UINT16_MAX - 1000u)) + 1000u; > } > Would something like the following address the issue (applied atop your patch)? IIRC sranddev() is mostly a BSD'ism, whereas the following should be OK in any standard C environment. diff --git a/source/Plugins/Process/gdb-remote/ProcessGDBRemote.cpp b/source/Plugins/Process/gdb-remote/ProcessGDBRemote.cpp index b434853..987f246 100644 --- a/source/Plugins/Process/gdb-remote/ProcessGDBRemote.cpp +++ b/source/Plugins/Process/gdb-remote/ProcessGDBRemote.cpp @@ -13,6 +13,7 @@ #include #include #include +#include // C++ Includes #include @@ -61,8 +62,10 @@ get_random_port () { if (!rand_initialized) { + time_t seed = time(NULL); + rand_initialized = true; - sranddev(); + srand(seed); } return (rand() % (UINT16_MAX - 1000u)) + 1000u; } From jingham at apple.com Tue Mar 29 18:22:29 2011 From: jingham at apple.com (Jim Ingham) Date: Tue, 29 Mar 2011 23:22:29 -0000 Subject: [Lldb-commits] [lldb] r128505 - /lldb/trunk/test/abbreviation_tests/TestAbbreviations.py Message-ID: <20110329232229.3C6232A6C12C@llvm.org> Author: jingham Date: Tue Mar 29 18:22:29 2011 New Revision: 128505 URL: http://llvm.org/viewvc/llvm-project?rev=128505&view=rev Log: Can't count on the particular number of modules loaded into a basic C executable. Modified: lldb/trunk/test/abbreviation_tests/TestAbbreviations.py Modified: lldb/trunk/test/abbreviation_tests/TestAbbreviations.py URL: http://llvm.org/viewvc/llvm-project/lldb/trunk/test/abbreviation_tests/TestAbbreviations.py?rev=128505&r1=128504&r2=128505&view=diff ============================================================================== --- lldb/trunk/test/abbreviation_tests/TestAbbreviations.py (original) +++ lldb/trunk/test/abbreviation_tests/TestAbbreviations.py Tue Mar 29 18:22:29 2011 @@ -131,13 +131,13 @@ patterns = ["Line table for .*main.cpp in `a.out"]) self.expect("i d se", - startstr = "Dumping sections for 5 modules.") + patterns = ["Dumping sections for [0-9]+ modules."]) self.expect("i d symf", - startstr = "Dumping debug symbols for 5 modules.") + patterns = ["Dumping debug symbols for [0-9]+ modules."]) self.expect("i d symt", - startstr = "Dumping symbol table for 5 modules.") + patterns = ["Dumping symbol table for [0-9]+ modules."]) self.expect("i li", substrs = [ 'a.out', From jingham at apple.com Tue Mar 29 18:34:15 2011 From: jingham at apple.com (Jim Ingham) Date: Tue, 29 Mar 2011 16:34:15 -0700 Subject: [Lldb-commits] [lldb] r128493 - /lldb/trunk/source/Plugins/Process/gdb-remote/ProcessGDBRemote.cpp In-Reply-To: <20110329232005.GA20927@fibrous.localdomain> References: <20110329214547.378902A6C12C@llvm.org> <20110329232005.GA20927@fibrous.localdomain> Message-ID: <5497A5FC-D41E-4E68-B94B-C66120E2C349@apple.com> I looked at what claimed to be Linux man pages online, and they claimed to have sranddev, but seeding from time would also be fine, if you want to apply that feel free. Cryptographic grade random numbers aren't required here, but two lldb's running at the same time shouldn't be trying to use the same port, which is what happens when you try to run lldb on lldb... BTW, at some point we'll fix this more properly by having lldb open the port, and telling the debugserver it launches to connect back to that. That way we can avoid these collisions. But for now anything like this will work. Thanks, Jim On Mar 29, 2011, at 4:20 PM, Stephen Wilson wrote: > Hi Jim. > > On Tue, Mar 29, 2011 at 09:45:47PM -0000, Jim Ingham wrote: >> get_random_port () >> { >> + if (!rand_initialized) >> + { >> + rand_initialized = true; >> + sranddev(); >> + } >> return (rand() % (UINT16_MAX - 1000u)) + 1000u; >> } >> > > Would something like the following address the issue (applied atop your patch)? > IIRC sranddev() is mostly a BSD'ism, whereas the following should be OK > in any standard C environment. > > > > diff --git a/source/Plugins/Process/gdb-remote/ProcessGDBRemote.cpp b/source/Plugins/Process/gdb-remote/ProcessGDBRemote.cpp > index b434853..987f246 100644 > --- a/source/Plugins/Process/gdb-remote/ProcessGDBRemote.cpp > +++ b/source/Plugins/Process/gdb-remote/ProcessGDBRemote.cpp > @@ -13,6 +13,7 @@ > #include > #include > #include > +#include > > // C++ Includes > #include > @@ -61,8 +62,10 @@ get_random_port () > { > if (!rand_initialized) > { > + time_t seed = time(NULL); > + > rand_initialized = true; > - sranddev(); > + srand(seed); > } > return (rand() % (UINT16_MAX - 1000u)) + 1000u; > } > > From ctice at apple.com Tue Mar 29 18:44:21 2011 From: ctice at apple.com (Caroline Tice) Date: Tue, 29 Mar 2011 23:44:21 -0000 Subject: [Lldb-commits] [lldb] r128508 - /lldb/trunk/source/Plugins/Instruction/ARM/EmulateInstructionARM.cpp Message-ID: <20110329234421.225102A6C12C@llvm.org> Author: ctice Date: Tue Mar 29 18:44:20 2011 New Revision: 128508 URL: http://llvm.org/viewvc/llvm-project?rev=128508&view=rev Log: Fill in code in EmulateSUBReg to emulate the SUB (register) ARM instruction. Modified: lldb/trunk/source/Plugins/Instruction/ARM/EmulateInstructionARM.cpp Modified: lldb/trunk/source/Plugins/Instruction/ARM/EmulateInstructionARM.cpp URL: http://llvm.org/viewvc/llvm-project/lldb/trunk/source/Plugins/Instruction/ARM/EmulateInstructionARM.cpp?rev=128508&r1=128507&r2=128508&view=diff ============================================================================== --- lldb/trunk/source/Plugins/Instruction/ARM/EmulateInstructionARM.cpp (original) +++ lldb/trunk/source/Plugins/Instruction/ARM/EmulateInstructionARM.cpp Tue Mar 29 18:44:20 2011 @@ -9369,19 +9369,123 @@ EmulateInstructionARM::EmulateSUBReg (const uint32_t opcode, const ARMEncoding encoding) { #if 0 + if ConditionPassed() then + EncodingSpecificOperations(); + shifted = Shift(R[m], shift_t, shift_n, APSR.C); + (result, carry, overflow) = AddWithCarry(R[n], NOT(shifted), ???1???); + if d == 15 then // Can only occur for ARM encoding + ALUWritePC(result); // setflags is always FALSE here + else + R[d] = result; + if setflags then + APSR.N = result<31>; + APSR.Z = IsZeroBit(result); + APSR.C = carry; + APSR.V = overflow; #endif - //bool success = false; + bool success = false; if (ConditionPassed(opcode)) { + uint32_t d; + uint32_t n; + uint32_t m; + bool setflags; + ARM_ShifterType shift_t; + uint32_t shift_n; + switch (encoding) { - } + case eEncodingT1: + // d = UInt(Rd); n = UInt(Rn); m = UInt(Rm); setflags = !InITBlock(); + d = Bits32 (opcode, 2, 0); + n = Bits32 (opcode, 5, 3); + m = Bits32 (opcode, 8, 6); + setflags = !InITBlock(); + + // (shift_t, shift_n) = (SRType_LSL, 0); + shift_t = SRType_LSL; + shift_n = 0; + + break; + + case eEncodingT2: + // if Rd == ???1111??? && S == ???1??? then SEE CMP (register); + // if Rn == ???1101??? then SEE SUB (SP minus register); + // d = UInt(Rd); n = UInt(Rn); m = UInt(Rm); setflags = (S == ???1???); + d = Bits32 (opcode, 11, 8); + n = Bits32 (opcode, 19, 16); + m = Bits32 (opcode, 3, 0); + setflags = BitIsSet (opcode, 20); + + // (shift_t, shift_n) = DecodeImmShift(type, imm3:imm2); + shift_n = DecodeImmShiftThumb (opcode, shift_t); + + // if d == 13 || (d == 15 && S == '0') || n == 15 || BadReg(m) then UNPREDICTABLE; + if ((d == 13) || ((d == 15) && BitIsClear (opcode, 20)) || (n == 15) || BadReg (m)) + return false; + + break; + + case eEncodingA1: + // if Rd == ???1111??? && S == ???1??? then SEE SUBS PC, LR and related instructions; + // if Rn == ???1101??? then SEE SUB (SP minus register); + // d = UInt(Rd); n = UInt(Rn); m = UInt(Rm); setflags = (S == ???1???); + d = Bits32 (opcode, 15, 12); + n = Bits32 (opcode, 19, 16); + m = Bits32 (opcode, 3, 0); + setflags = BitIsSet (opcode, 20); + + // (shift_t, shift_n) = DecodeImmShift(type, imm5); + shift_n = DecodeImmShiftARM (opcode, shift_t); + + break; + + default: + return false; + } + + // shifted = Shift(R[m], shift_t, shift_n, APSR.C); + uint32_t Rm = ReadCoreReg (m, &success); + if (!success) + return false; + + uint32_t shifted = Shift (Rm, shift_t, shift_n, APSR_C); + + // (result, carry, overflow) = AddWithCarry(R[n], NOT(shifted), ???1???); + uint32_t Rn = ReadCoreReg (n, &success); + if (!success) + return false; + + AddWithCarryResult res = AddWithCarry (Rn, ~shifted, 1); + + // if d == 15 then // Can only occur for ARM encoding + // ALUWritePC(result); // setflags is always FALSE here + // else + // R[d] = result; + // if setflags then + // APSR.N = result<31>; + // APSR.Z = IsZeroBit(result); + // APSR.C = carry; + // APSR.V = overflow; + + EmulateInstruction::Context context; + context.type = eContextSubtraction; + Register reg_n; + reg_n.SetRegister (eRegisterKindDWARF, n); + Register reg_m; + reg_m.SetRegister (eRegisterKindDWARF, m); + context.SetRegisterRegisterOperands (reg_n, reg_m); + + uint32_t dest_reg_num = dwarf_r0 + d; + + if (!WriteCoreRegOptionalFlags (context, res.result, dest_reg_num, setflags, res.carry_out, res.overflow)) + return false; } return true; } - + // A8.6.202 STREX bool EmulateInstructionARM::EmulateSTREX (const uint32_t opcode, const ARMEncoding encoding) @@ -10042,6 +10146,8 @@ { 0x0fe00000, 0x02400000, ARMvAll, eEncodingA1, eSize32, &EmulateInstructionARM::EmulateSUBImmARM, "sub{s} , , #"}, // sub (sp minus immediate) { 0x0fef0000, 0x024d0000, ARMvAll, eEncodingA1, eSize32, &EmulateInstructionARM::EmulateSUBSPImm, "sub{s} , sp, #"}, + // sub (register) + { 0x0fe00010, 0x00400000, ARMvAll, eEncodingA1, eSize32, &EmulateInstructionARM::EmulateSUBReg, "sub{s} , , {,}"}, // teq (immediate) { 0x0ff0f000, 0x03300000, ARMvAll, eEncodingA1, eSize32, &EmulateInstructionARM::EmulateTEQImm, "teq , #const"}, // teq (register) @@ -10282,6 +10388,9 @@ // sub (sp minus immediate) { 0xfbef8000, 0xf1ad0000, ARMV6T2_ABOVE, eEncodingT2, eSize32, &EmulateInstructionARM::EmulateSUBSPImm, "sub{s}.w , sp, #"}, { 0xfbff8000, 0xf2ad0000, ARMV6T2_ABOVE, eEncodingT3, eSize32, &EmulateInstructionARM::EmulateSUBSPImm, "subw , sp, #imm12"}, + // sub (register) + { 0xfffffe00, 0x00001a00, ARMV4T_ABOVE, eEncodingT1, eSize16, &EmulateInstructionARM::EmulateSUBReg, "subs|sub , , "}, + { 0xffe08000, 0xeba00000, ARMV6T2_ABOVE, eEncodingT2, eSize32, &EmulateInstructionARM::EmulateSUBReg, "sub{s}.w , , {,}"}, // teq (immediate) { 0xfbf08f00, 0xf0900f00, ARMV6T2_ABOVE, eEncodingT1, eSize32, &EmulateInstructionARM::EmulateTEQImm, "teq , #"}, // teq (register) From wilsons at start.ca Tue Mar 29 19:12:40 2011 From: wilsons at start.ca (Stephen Wilson) Date: Wed, 30 Mar 2011 00:12:40 -0000 Subject: [Lldb-commits] [lldb] r128514 - /lldb/trunk/source/Plugins/Process/gdb-remote/ProcessGDBRemote.cpp Message-ID: <20110330001240.7427A2A6C12C@llvm.org> Author: wilsons Date: Tue Mar 29 19:12:40 2011 New Revision: 128514 URL: http://llvm.org/viewvc/llvm-project?rev=128514&view=rev Log: Unfortunately, sranddev() is not available on all platforms so seed using the current time instead. Modified: lldb/trunk/source/Plugins/Process/gdb-remote/ProcessGDBRemote.cpp Modified: lldb/trunk/source/Plugins/Process/gdb-remote/ProcessGDBRemote.cpp URL: http://llvm.org/viewvc/llvm-project/lldb/trunk/source/Plugins/Process/gdb-remote/ProcessGDBRemote.cpp?rev=128514&r1=128513&r2=128514&view=diff ============================================================================== --- lldb/trunk/source/Plugins/Process/gdb-remote/ProcessGDBRemote.cpp (original) +++ lldb/trunk/source/Plugins/Process/gdb-remote/ProcessGDBRemote.cpp Tue Mar 29 19:12:40 2011 @@ -13,6 +13,7 @@ #include #include #include +#include // C++ Includes #include @@ -61,8 +62,10 @@ { if (!rand_initialized) { + time_t seed = time(NULL); + rand_initialized = true; - sranddev(); + srand(seed); } return (rand() % (UINT16_MAX - 1000u)) + 1000u; } From wilsons at start.ca Tue Mar 29 19:26:21 2011 From: wilsons at start.ca (Stephen Wilson) Date: Tue, 29 Mar 2011 20:26:21 -0400 Subject: [Lldb-commits] [PATCH] give subclasses access to UnixSignals::m_signals In-Reply-To: <20110328003824.GA30603@fibrous.localdomain> References: <20110328003824.GA30603@fibrous.localdomain> Message-ID: <20110330002621.GA21373@fibrous.localdomain> Any chance I could get a quick thumbs up on the following patch? I know this is a rater trivial change and I should probably just go ahead and commit it. My main concern was if there are any short-term plans to move the default darwin-specific implementation elsewhere -- thus potentially making this change redundant. On Sun, Mar 27, 2011 at 08:38:24PM -0400, Stephen Wilson wrote: > > Allow subclasses of UnixSignals to access m_signals by marking the > member protected instead of private. This enables a subclass to provide > a default signal set as appropriate on construction. > > > > diff --git a/include/lldb/Target/UnixSignals.h b/include/lldb/Target/UnixSignals.h > index 3e13438..f47a90b 100644 > --- a/include/lldb/Target/UnixSignals.h > +++ b/include/lldb/Target/UnixSignals.h > @@ -133,10 +133,6 @@ protected: > void > Reset (); > > -private: > - //------------------------------------------------------------------ > - // For UnixSignals only > - //------------------------------------------------------------------ > typedef std::map collection; > > collection m_signals; > > > _______________________________________________ > lldb-commits mailing list > lldb-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/lldb-commits -- steve From gclayton at apple.com Tue Mar 29 20:02:38 2011 From: gclayton at apple.com (Greg Clayton) Date: Wed, 30 Mar 2011 01:02:38 -0000 Subject: [Lldb-commits] [lldb] r128518 - in /lldb/trunk/www: lldb-gdb.html sidebar.incl style.css tutorial.html Message-ID: <20110330010238.365AD2A6C12C@llvm.org> Author: gclayton Date: Tue Mar 29 20:02:37 2011 New Revision: 128518 URL: http://llvm.org/viewvc/llvm-project?rev=128518&view=rev Log: Updated the web site with a getting started with LLDB and also some resources to help GDB users figure out the equivalent commands in LLDB. Added: lldb/trunk/www/lldb-gdb.html (with props) lldb/trunk/www/tutorial.html (with props) Modified: lldb/trunk/www/sidebar.incl lldb/trunk/www/style.css Added: lldb/trunk/www/lldb-gdb.html URL: http://llvm.org/viewvc/llvm-project/lldb/trunk/www/lldb-gdb.html?rev=128518&view=auto ============================================================================== --- lldb/trunk/www/lldb-gdb.html (added) +++ lldb/trunk/www/lldb-gdb.html Tue Mar 29 20:02:37 2011 @@ -0,0 +1,448 @@ + + + + + +LLDB Goals + + + +
+ The LLDB Debugger +
+ +
+
+ +
+
+

LLDB to GDB Command Map

+
+ +

Below is a table of LLDB commands with the GDB counterparts. + The built in GDB compatability aliases in GDB are also + listed.

+
+
+ +

Execution Commands

+
+ +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
LLDBGDB
Launch a process no arguments.
+ (lldb) process launch
+ (lldb) run
+ (lldb) r + 		+ (gdb) run
+ (gdb) r +
Launch a process with arguments <args>.
+ (lldb) process launch -- <args>
+ (lldb) run -- <args>
+ (lldb) r <args> + 		+ (gdb) run <args>
+ (gdb) r <args> +
Launch a process with arguments in new terminal window (Mac OS X only).
+ (lldb) process launch --tty -- <args>
+ (lldb) process launch -t -- <args>
+ 		+
Launch a process with arguments in existing terminal /dev/ttys006 (Mac OS X only).
+ (lldb) process launch --tty=/dev/ttys006 -- <args>
+ (lldb) process launch -t/dev/ttys006 -- <args>
+ 		+
Attach to a process with process ID 123.
+ (lldb) process attach --pid 123
+ (lldb) attach -p 123 + 		+ (gdb) attach 123 +
Attach to a process named "a.out".
+ (lldb) process attach --name a.out
+ (lldb) process attach -n a.out + 		+ (gdb) attach a.out +
Wait for a process named "a.out" to launch and attach.
+ (lldb) process attach --name a.out --waitfor
+ (lldb) process attach -n a.out -w + 		+ (gdb) attach -waitfor a.out +
Do a source level single step in the currently selected thread.
+ (lldb) thread step-in
+ (lldb) step
+ (lldb) s + 		+ (gdb) step
+ (gdb) s +
Do a source level single step over in the currently selected thread.
+ (lldb) thread step-over
+ (lldb) next
+ (lldb) n
+ 		+ (gdb) next
+ (gdb) n +
Do an instruction level single step in the currently selected thread.
+ (lldb) thread step-inst
+ (lldb) si
+ 		+ (gdb) stepi
+ (gdb) si +
Do an instruction level single step over in the currently selected thread.
+ (lldb) thread step-inst-over
+ 		+ (gdb) nexti
+ (gdb) ni +
Step out of the currently selected frame.
+ (lldb) thread step-out
+ (lldb) finish
+ 		+ (gdb) finish
+
+

+

+
+ +

Breakpoint Commands

+
+ +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
LLDBGDB
Set a breakpoint at all functions named main.
+ (lldb) breakpoint set --name main
+ (lldb) breakpoint set -n main
+ (lldb) b main + 		+ (lldb) break main +
Set a breakpoint in file test.c at line 12.
+ (lldb) breakpoint set --file test.c --line 12
+ (lldb) breakpoint set -f test.c -l 12
+ (lldb) b test.c:12 + 		+ (lldb) break test.c:12 +
Set a breakpoint at all C++ methods whose basename is main.
+ (lldb) breakpoint set --method main
+ (lldb) breakpoint set -M main
+ 		+ (lldb) break main
+ (Hope that there are no C funtions named main). +
Set a breakpoint at all Objective C methods whose selector is count.
+ (lldb) breakpoint set --selector count
+ (lldb) breakpoint set -S count
+ 		+ (lldb) break count
+ (Hope that there are no C or C++ funtions named count). +
+

+

+
+ +

Examining Thread State

+
+ +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +\ + + + + + + + + + + + + + + + + + +
LLDBGDB
Show the arguments and local variables for the current frame.
+ (lldb) frame variable
+ 		+ (gdb) info args
+ and
+ (gdb) info locals
+
Show the stack backtrace for the current thread.
+ (lldb) thread backtrace
+ (lldb) bt
+ 		+ (gdb) bt
+
Show the stack backtraces for all threads.
+ (lldb) thread backtrace all
+ (lldb) bt all + 		+ (gdb) thread apply all bt +
Show all thread registers.
+ (lldb) register read + + (gdb) info all-registers +
Show the values for the thread registers name "rax", "rsp" and "rbp".
+ (lldb) register read rax rsp rbp + + (gdb) info all-registers rax rsp rbp +
Read memory from address 0xbffff3c0 and show 4 hex uint32_t values.
+ (lldb) memory read --size 4 --format x --count 4 0xbffff3c0
+ (lldb) x --size 4 --format x --count 4 0xbffff3c0 + 		+ (gdb) x/4xw 0xbffff3c0 +
Disassemble the current function for the current frame.
+ (lldb) disassemble --frame
+ (lldb) disassemble -f + 		+ (gdb) disassemble +
Disassemble any functions named main.
+ (lldb) disassemble --name main
+ (lldb) disassemble -n main + 		+ (gdb) disassemble main +
Disassemble an address range.
+ (lldb) disassemble --start-address 0x00001eb8 --end-address 0x00001ec3
+ 		+ (gdb) disassemble 0x00001eb8 0x00001ec3 +
Show mixed source and disassembly for the current function for the current frame.
+ (lldb) disassemble --frame --mixed
+ (lldb) disassemble -f -m + 		+ n/a +
Disassemble the current function for the current frame and show the opcode bytes.
+ (lldb) disassemble --frame --bytes
+ (lldb) disassemble -f -b + 		+ n/a +
Disassemble the current source line for the current frame.
+ (lldb) disassemble --line
+ (lldb) disassemble -l + 		+ n/a +
+

+

+
+ +

Executable and Shared Library Query Commands

+
+ +

+ + + + + + + + + + + + + + + + + + + + + + + + + + +
LLDBGDB
List the main executable and all dependent shared libraries.
+ (lldb) image list
+ 		+ (gdb) info shared
+
Lookup information for a raw address in the executable or any shared libraries.
+ (lldb) image lookup --address 0x1ec4
+ (lldb) image lookup -a 0x1ec4
+ 		+ (gdb) info symbol 0x1ec4
+
Dump all sections from the main executable and any shared libraries.
+ (lldb) image dump sections
+ 		+ (gdb) maintenance info sections
+
+

+

+
+ +

+ + +

+
+
+
+ + Propchange: lldb/trunk/www/lldb-gdb.html ------------------------------------------------------------------------------ svn:executable = * Modified: lldb/trunk/www/sidebar.incl URL: http://llvm.org/viewvc/llvm-project/lldb/trunk/www/sidebar.incl?rev=128518&r1=128517&r2=128518&view=diff ============================================================================== --- lldb/trunk/www/sidebar.incl (original) +++ lldb/trunk/www/sidebar.incl Tue Mar 29 20:02:37 2011 @@ -7,6 +7,8 @@
  • Goals
  • Features
  • Status
    • +
  • Tutorial
    • +
  • LLDB and GDB
    • Modified: lldb/trunk/www/style.css URL: http://llvm.org/viewvc/llvm-project/lldb/trunk/www/style.css?rev=128518&r1=128517&r2=128518&view=diff ============================================================================== --- lldb/trunk/www/style.css (original) +++ lldb/trunk/www/style.css Tue Mar 29 20:02:37 2011 @@ -72,23 +72,88 @@ color: black; } -.urbangreymenu ul li a:hover{ /*hover state CSS*/ +.urbangreymenu ul li a:hover { /*hover state CSS*/ color: black; background: #bbbbbb; } +.samplecode { + background-repeat:repeat-x; + border:1px solid #d1c7ac; + width: 230px; + color:#333333; + padding:3px; + margin-right:4px; + margin-bottom:8px; + font-family:tahoma, arial, sans-serif; +} + +table.stats { + text-align: center; + font-family: Verdana, Geneva, Arial, Helvetica, sans-serif ; + font-weight: normal; + font-size: 11px; + color: #fff; + background-color: #666; + border: 0px; + border-collapse: collapse; + border-spacing: 0px; +} + +td.blank { + background-color: white; + background: white; + color: white; +} + +td.content { + background-color: #CCC; + color: #000; + padding: 4px; + text-align: left; + border: 1px #fff solid; + height: 40px; + vertical-align: top; +} + +td.header { + background-color: #bbb; + color: #000; + padding: 4px; + text-align: left; + border: 1px #fff solid; + vertical-align: top; +} + +table.stats { + color: #000; + padding: 4px; + text-align: left; + border: 1px #fff solid; +} + + +table.stats td.hed { + background: #606060; + color: white; + padding: 4px; + text-align: left; + border-bottom: 2px #fff solid; + font-size: 12px; + font-weight: bold; +} -.post{ -width: 640px; /*width of menu*/ +.post { + width: 640px; /*width of menu*/ } -.postheader{ -font: bold 13px Verdana; -color: white; -background: #606060; -margin-bottom: 0; /*bottom spacing between header and rest of content*/ -text-transform: uppercase; -padding: 7px 0 7px 7px; +.postheader { + font: bold 13px Verdana; + color: white; + background: #606060; + margin-bottom: 0; /*bottom spacing between header and rest of content*/ + text-transform: uppercase; + padding: 7px 0 7px 7px; } .postcontent{ Added: lldb/trunk/www/tutorial.html URL: http://llvm.org/viewvc/llvm-project/lldb/trunk/www/tutorial.html?rev=128518&view=auto ============================================================================== --- lldb/trunk/www/tutorial.html (added) +++ lldb/trunk/www/tutorial.html Tue Mar 29 20:02:37 2011 @@ -0,0 +1,558 @@ + + + + + +LLDB Goals + + + +
    + The LLDB Debugger +
    + +
    +
    + +
    +
    +

    Getting Started

    +
    + +

    Here's a short precis of how to run lldb if you are familiar with the gdb command set. + We will first start with some details on lldb command structure to help orient you.

    + +
    +
    + +
    +

    Command Structure

    +
    + +

    Unlike gdb's command set, which is rather free-form, we tried to make + the lldb command syntax fairly structured. The commands are all of the + form:

    + + + <noun> <verb< [-options [option-value]] [argument [argument...]] + + +

    The command line parsing is done before command execution, so it is + uniform across all the commands. The command syntax is very simple, + basically arguments, options and option values are all white-space + separated. If you need to put a backslash or double-quote character + in an argument you back-slash it in the argument. That makes the + command syntax more regular, but it also means you may have to + quote some arguments in lldb that you wouldn't in gdb.

    + +

    Options can be placed anywhere on the command line, but if the arguments + begin with a "-" then you have to tell lldb that you're done with options + for the current command by adding an option termination: "--" + So for instance if you want to launch a process and give the "process launch" command + the "--stop-at-entry" option, yet you want the + process you are about to launch to be launched with the arguments + "-program_arg value", you would type:

    + + + (lldb) process launch --stop-at-entry -- -program_arg value + + +

    We also tried to reduce the number of special purpose argument + parsers, which sometimes forces the user to be a little more explicit + about stating their intentions. The first instance you'll note of + this is the breakpoint command. In gdb, to set a breakpoint, you + might enter one of:

    + + + (gdb) break foo.c:12 +
    (gdb) break foo +     + +

    if foo is a function. As time went on, the parser that tells foo.c:12 + from foo from foo.c::foo (which means the function foo in the file + foo.c) got more and more complex and bizarre, and especially in C++ + there are times where there's really no way to specify the function + you want to break on. The lldb commands are more verbose but also more precise + and allow for intellegent auto completion. + +

    To set the same file and line breakpoint in LLDB you can enter either of:

    + + + (lldb) breakpoint set --file foo.c --line 12 +
    (lldb) breakpoint set -f foo.c -l 12 +     + +

    To set a breakpoint on a function named foo in LLDB you can enter either of:

    + + + (lldb) breakpoint set --name foo +
    (lldb) breakpoint set -n foo +     + +

    Setting breakpoints by name is event more specialized in LLDB as you can specify + that you want to set a breakpoint at a function by method name. To set a breakpoint + on all C++ methods named foo you can entier either of:

    + + + (lldb) breakpoint set --method foo +
    (lldb) breakpoint set -M foo +     + +

    To set a breakpoint Objective C selectors named alignLeftEdges: you can entier either of:

    + + + (lldb) breakpoint set --selector alignLeftEdges: +
    (lldb) breakpoint set -S alignLeftEdges: +     + +

    You can limit any breakpoints to a specific executable image by using + the "--shlib <path>" ("-s <path>" for short):

    + + + (lldb) breakpoint set --shlib foo.dylib --name foo +
    (lldb) breakpoint set -s foo.dylib -n foo +     + +

    Suggestions on more interesting primitives of this sort are also very welcome.

    + +

    Just like gdb, the lldb command interpreter does a shortest unique + string match on command names, so the following two commands will + both execute the same command:

    + + + (lldb) breakpoint set -n "-[SKTGraphicView alignLeftEdges:]" +
    (lldb) b s -n "-[SKTGraphicView alignLeftEdges:]" +     + +

    lldb also supports command completion for source file names, symbol + names, file names, etc. Completion is initiated by a hitting a TAB. + Individual options in a command can have different completers, so for + instance the "--file <path>" option in "breakpoint" completes to source files, the + "--shlib <path>" option to currently loaded shared libraries, etc. We can even do + things like if you specify "--shlib <path>", and are completing on "--file <path>", we will only + list source files in the shared library specified by "--shlib <path>".

    + +

    The individual commands are pretty extensively documented, using + the help command. And there is an apropos command that will + search the help for a particular word and dump a summary help string + for each matching command.

    + +

    Finally, there is a mechanism to construct aliases for commonly used + commands. So for instance if you get annoyed typing:

    + + + (lldb) breakpoint set --file foo.c --line 12 + + +

    you can do:

    + + + (lldb) command alias bfl breakpoint set -f %1 -l %2 +
    (lldb) bfl foo.c 12 +     + +

    We have added a few aliases for commonly used commands (e.g. "step", + "next" and "continue") but we haven't tried to be exhaustive because + in our experience it is more convenient to make the basic commands + unique down to a letter or two, and then learn these sequences than + fill the namespace with lots of aliases, and then have to type them + all the way out.

    + +

    However, users are free to customize lldb's command set however they + like, and since lldb reads the file ~/.lldbinit at startup, you can + store all your aliases there and they will be generally available to + you. Your aliases are also documented in the help command so you can + remind yourself of what you've set up.

    + +

    lldb also has a built-in Python interpreter, which is accessible by + the "script" command. All the functionality of the debugger is + available as classes in the Python interpreter, so the more complex + commands that in gdb you would introduce with the "define" command can + be done by writing Python functions using the lldb-Python library, + then loading the scripts into your running session and accessing them + with the "script" command.

    + +
    +
    + + +
    +

    Loading a program into lldb

    +
    + +

    First we need to set the program to debug. As with gdb, you + can start lldb and specify the file you wish to debug on the command line:

    + + + $ lldb /Projects/Sketch/build/Debug/Sketch.app +
    Current executable set to '/Projects/Sketch/build/Debug/Sketch.app' (x86_64). +     + +

    or you can specify it after the fact with the "file" command:

    + + + $ lldb +
    (lldb) file /Projects/Sketch/build/Debug/Sketch.app +
    Current executable set to '/Projects/Sketch/build/Debug/Sketch.app' (x86_64). +     +

    +

    +
    + +
    +

    Setting breakpoints

    +
    + +

    We've discussed how to set breakpoints above. You can use help breakpoint set + to see all the options for breakpoint setting. For instance, we might do:

    + + + (lldb) breakpoint set --selector alignLeftEdges: +
    Breakpoint created: 1: name = 'alignLeftEdges:', locations = 1, resolved = 1 +     + +

    You can find out about the breakpoints you've set with:

    + + 
    (lldb) breakpoint list
+Current breakpoints:
+1: name = 'alignLeftEdges:', locations = 1, resolved = 1
+  1.1: where = Sketch`-[SKTGraphicView alignLeftEdges:] + 33 at /Projects/Sketch/SKTGraphicView.m:1405, address = 0x0000000100010d5b, resolved, hit count = 0 
+
    + +

    Note that each logical breakpoint can have multiple locations. + The logical breakpoint has an integer id, and it's locations have an + id within their parent breakpoint (the two are joined by a ".", + e.g. 1.1 in the example above.)

    + +

    Also the breakpoints remain live so that if another shared library + were to be loaded that had another implementation of the + "alignLeftEdges:" selector, the new location would be added to + breakpoint 1 (e.g. a "1.2" breakpoint would be set on the newly loaded + selector).

    + +

    The other piece of information in the breakpoint listing is whether the + breakpoint location was resolved or not. A location gets resolved when + the file address it corresponds to gets loaded into the program you are + debugging. For instance if you set a breakpoint in a shared library that + then gets unloaded, that breakpoint location will remain, but it will no + longer be resolved.

    + +

    One other thing to note for gdb users is that lldb acts like gdb with:

    + + + (gdb) set breakpoint pending on + + +

    That is, lldb should always make a breakpoint from your specification, even + if it couldn't find any locations that match the specification. You can tell + whether the expression was resolved or not by checking the locations field + in "breakpoint list", and we report the breakpoint as "pending" when you + set it so you can tell you've made a typo more easily, if that was indeed + the reason no locations were found:

    + + + (lldb) breakpoint set --file foo.c --line 12 +
    Breakpoint created: 2: file ='foo.c', line = 12, locations = 0 (pending) +
    WARNING: Unable to resolve breakpoint to any actual locations. +     + +

    You can delete, disable, set conditions and ignore counts either on all the + locations generated by your logical breakpoint, or on particular locations + your specification resolved to. For instance if we wanted to add a command + to print a backtrace when we hit this breakpoint we could do:

    + + + (lldb) breakpoint command add --commands 1.1 +
    Enter your debugger command(s). Type 'DONE' to end. +
    > bt +
    > DONE +     + +

    The "--command" option specifies that the breakpoint command is a set of lldb + commmand interpreter commands. Use "--script" if you want to implement your + breakpoint command using the Python script instead.

    + +
    +
    + +
    +

    Starting or attaching to your Program

    +
    + +

    To launch a program in lldb we use the "process launch" command or + one of its built in aliases:

    + + + (lldb) process launch +
    (lldb) run +
    (lldb) r +     + +

    You can also attach to a process by process ID or process name. + When attaching to a process by name, lldb also supports the "--waitfor" option which waits for the + next process that has that name to show up, and attaches to it

    + + + (lldb) process attach --pid 123 +
    (lldb) process attach --name Sketch +
    (lldb) process attach --name Sketch --waitfor +     + +

    After you launch or attach to a process, your process might stop + somewhere:

    + + (lldb) process attach -p 12345 +
    Process 46915 Attaching +
    Process 46915 Stopped +
    1 of 3 threads stopped with reasons: +
    * thread #1: tid = 0x2c03, 0x00007fff85cac76a, where = libSystem.B.dylib`__getdirentries64 + 10, stop reason = signal = SIGSTOP, queue = com.apple.main-thread +     + + +

    Note the line that says "1 of 3 threads stopped with reasons:" and the + lines that follow it. In a multi-threaded environment it is very + common for more than one thread to hit your breakpoint(s) before the + kernel actually returns control to the debugger. In that case, you + will see all the threads that stopped for some interesting reason + listed in the stop message.

    + +
    +
    + +
    +

    Controlling your Program

    +
    + + +

    After launching, we can continue until we hit our breakpoint. The primitive + commands for process control all exist under the "thread" command:

    + + + (lldb) thread continue +
    Resuming thread 0x2c03 in process 46915 +
    Resuming process 46915 +
    (lldb) +     + +

    At present you can only operate on one thread at a time, but the + design will ultimately support saying "step over the function in + Thread 1, and step into the function in Thread 2, and continue Thread + 3" etc. When we eventually support keeping some threads running while + others are stopped this will be particularly important. For + convenience, however, all the stepping commands have easy aliases. + So "thread continue" is just "c", etc.

    + +

    The other program stepping commands are pretty much the same as in gdb. + You've got:

    + + 
    (lldb) thread step-in    // The same as gdb's "step" or "s" 
+(lldb) thread step-over  // The same as gdb's "next" or "n"
+(lldb) thread step-out   // The same as gdb's "finish" or "f"
+
    + +

    By default, lldb does defined aliases to all common gdb process control + commands ("s", "step", "n", "next", "finish"). + If we have missed any, please add them to your ~/.lldbinit file + using the "command alias" command. + +

    lldb also supported the step by instruction versions:

    + 
    (lldb) thread step-inst       // The same as gdb's "stepi" / "si"
+(lldb) thread step-over-inst  // The same as gdb's "nexti" / "ni"
+
    + +

    Finally, lldb has a run until line or frame exit stepping mode:

    + + + (lldb) thread until 100 + + +

    This command will run the thread in the current frame till it reaches line 100 in + this frame or stops if it leaves the current frame. This is a pretty + close equivalent to gdb's "until" command.

    + +

    A process, by default, will shared the lldb terminal with the inferior + process. When in this mode, much like when debugging with gdb, when + the process is running anything you type will go to the STDIN of the + inferior process. To interrupt your inferior program, type CTRL+C.

    + +

    If you attach to a process, or launch a process with the "--no-stdin + option, the command interpreter is always available to enter commands. This + might be a little disconcerting to gdb users when always have an (lldb) + prompt. This allows you to set a breakpoint, etc without having to explicitly interrupt + the program you are debugging:

    + + + (lldb) process continue +
    (lldb) breakpoint set --name stop_here +     + +

    There are many commands that won't work while running, and the command + interpreter should do a good job of letting you know when this is the + case. If you find any instances where the command interpreter isn't + doing its job, please file a bug. This way of operation will set us + up for a future debugging mode called thread centric debugging. + This mode will allow us to run all threads and only stop the threads + that are at breakpoints or have exceptions or signals.

    + +

    There command commands that currently work while running include + interrupting the process to halt execution ("process interrupt"), + getting the process status ("process status"), + breakpoint setting and clearing (" breakpoint [set|clear|enable|disable|list] ..."), + and memory reading and writing (" memory [read|write] ..."). +

    + +
    +
    + +
    +

    Examining Thread State

    +
    + +

    Once you've stopped, lldb will choose a current thread, usually the + one that stopped "for a reason", and a current frame in that thread. + Many the commands for inspecting state work on this current + thread/frame.

    + +

    To inspect the current state of your process, you can start with the + threads:

    + + 
    (lldb) thread list
+Process 46915 state is Stopped
+* thread #1: tid = 0x2c03, 0x00007fff85cac76a, where = libSystem.B.dylib`__getdirentries64 + 10, stop reason = signal = SIGSTOP, queue = com.apple.main-thread
+  thread #2: tid = 0x2e03, 0x00007fff85cbb08a, where = libSystem.B.dylib`kevent + 10, queue = com.apple.libdispatch-manager
+  thread #3: tid = 0x2f03, 0x00007fff85cbbeaa, where = libSystem.B.dylib`__workq_kernreturn + 10
+
    + +

    The * indicates that Thread 1 is the current thread. To get a + backtrace for that thread, do:

    + + 
    (lldb) thread backtrace
+thread #1: tid = 0x2c03, stop reason = breakpoint 1.1, queue = com.apple.main-thread
+ frame #0: 0x0000000100010d5b, where = Sketch`-[SKTGraphicView alignLeftEdges:] + 33 at /Projects/Sketch/SKTGraphicView.m:1405
+ frame #1: 0x00007fff8602d152, where = AppKit`-[NSApplication sendAction:to:from:] + 95
+ frame #2: 0x00007fff860516be, where = AppKit`-[NSMenuItem _corePerformAction] + 365
+ frame #3: 0x00007fff86051428, where = AppKit`-[NSCarbonMenuImpl performActionWithHighlightingForItemAtIndex:] + 121
+ frame #4: 0x00007fff860370c1, where = AppKit`-[NSMenu performKeyEquivalent:] + 272
+ frame #5: 0x00007fff86035e69, where = AppKit`-[NSApplication _handleKeyEquivalent:] + 559
+ frame #6: 0x00007fff85f06aa1, where = AppKit`-[NSApplication sendEvent:] + 3630
+ frame #7: 0x00007fff85e9d922, where = AppKit`-[NSApplication run] + 474
+ frame #8: 0x00007fff85e965f8, where = AppKit`NSApplicationMain + 364
+ frame #9: 0x0000000100015ae3, where = Sketch`main + 33 at /Projects/Sketch/SKTMain.m:11
+ frame #10: 0x0000000100000f20, where = Sketch`start + 52
+
    + +

    You can also provide a list of threads to backtrace, or the keyword + "all" to see all threads:

    + + + (lldb) thread backtrace all + +

    +

    +
    + +
    +

    Examining Stack Frame State

    +
    + + +

    The most convenient way to inspect a frame's arguments and local variables is to use the "frame variable" command:

    + + + (lldb) frame variable +
    self = (SKTGraphicView *) 0x0000000100208b40 +
    _cmd = (struct objc_selector *) 0x000000010001bae1 +
    sender = (id) 0x00000001001264e0 +
    selection = (NSArray *) 0x00000001001264e0 +
    i = (NSUInteger) 0x00000001001264e0 +
    c = (NSUInteger) 0x00000001001253b0 +     + +

    As you see above, if you don't specify any variable names, all arguments + and locals will be shown. If give "frame variable" some arguments, + they should be the name of locals or paths to children of the variables:

    + + + (lldb) frame variable self +
    (SKTGraphicView *) self = 0x0000000100208b40 +
    (lldb) frame variable self.isa +
    (struct objc_class *) self.isa = 0x0000000100023730 +     + +

    The "frame variable" command is not a full expression + parser but it does support a few simple operations like &, *, ->, [] (no overloaded + operators). The array brackets can be used on pointers to treat pointers + as arrays:

    + + + (lldb) frame variable *self +
    (SKTGraphicView *) self = 0x0000000100208b40 +
    (NSView) NSView = { +
    (NSResponder) NSResponder = { +
    ... +
    +
    (lldb) frame variable &self +
    (SKTGraphicView **) &self = 0x0000000100304ab +
    +
    (lldb) frame variable argv[0] +
    (char const *) argv[0] = 0x00007fff5fbffaf8 "/Projects/Sketch/build/Debug/Sketch.app/Contents/MacOS/Sketch" +     + +

    The frame variable command will also perform "object printing" operations on + variables (currently we only support NSPrintForDebugger) with:

    + + + (lldb) frame variable -o self + (SKTGraphicView *) self = 0x0000000100208b40 <SKTGraphicView: 0x100208b40> + + +

    You can select another frame to view with by selecting a frame with the "frame select"

    + + + (lldb) frame select 9 + frame #9: 0x0000000100015ae3, where = Sketch`function1 + 33 at /Projects/Sketch/SKTFunctions.m:11 + + +

    If you need to view more complex data or change program data, you can + use the general "expression" command. It takes an expression and + evaluates it in the scope of the currently selected frame. For instance:

    + + + (lldb) expr self +
    $0 = (SKTGraphicView *) 0x0000000100135430 +
    (lldb) expr self = 0x00 +
    $1 = (SKTGraphicView *) 0x0000000000000000 +
    (lldb) frame var self +
    (SKTGraphicView *) self = 0x0000000000000000 +     + +

    You can also call functions:

    + + + (lldb) expr (int) printf ("I have a pointer 0x%llx.\n", self) +
    $2 = (int) 22 +
    I have a pointer 0x0. +     + +

    One thing to note from this example is that lldb commands can be defined to + take "raw" input. "expression" is one of these. So in the expression command, + you don't have to quote your whole expression, nor backslash protect quotes, + etc...

    + +

    Finally, the results of the expressions are stored in persistent variables + (of the form $[0-9]+) that you can use in further expressions, like:

    + + + (lldb) expr self = $0 +
    $4 = (SKTGraphicView *) 0x0000000100135430 +     +

    +

    +
    + +
    +
    +
    +
    + + Propchange: lldb/trunk/www/tutorial.html ------------------------------------------------------------------------------ svn:executable = * From jingham at apple.com Tue Mar 29 20:55:23 2011 From: jingham at apple.com (Jim Ingham) Date: Wed, 30 Mar 2011 01:55:23 -0000 Subject: [Lldb-commits] [lldb] r128523 - /lldb/trunk/examples/python/disasm.py Message-ID: <20110330015523.BD0282A6C12C@llvm.org> Author: jingham Date: Tue Mar 29 20:55:23 2011 New Revision: 128523 URL: http://llvm.org/viewvc/llvm-project?rev=128523&view=rev Log: The example had gotten stale, so I made it work again, and for fun printed out the frame registers as well. Modified: lldb/trunk/examples/python/disasm.py Modified: lldb/trunk/examples/python/disasm.py URL: http://llvm.org/viewvc/llvm-project/lldb/trunk/examples/python/disasm.py?rev=128523&r1=128522&r2=128523&view=diff ============================================================================== --- lldb/trunk/examples/python/disasm.py (original) +++ lldb/trunk/examples/python/disasm.py Tue Mar 29 20:55:23 2011 @@ -31,13 +31,14 @@ if target.IsValid(): # If the target is valid set a breakpoint at main - main_bp = target.BreakpointCreateByName ("main", sys.argv[1]); + main_bp = target.BreakpointCreateByName ("main", target.GetExecutable().GetFilename()); print main_bp # Launch the process. Since we specified synchronous mode, we won't return # from this function until we hit the breakpoint at main - process = target.LaunchProcess ([''], [''], "/dev/stdout", 0, False) + error = lldb.SBError() + process = target.Launch (debugger.GetListener(), None, None, os.ctermid(), os.ctermid(), os.ctermid(), None, 0, False, error) # Make sure the launch went ok if process.IsValid(): @@ -72,6 +73,19 @@ # Now get all instructions for this symbol and print them insts = symbol.GetInstructions(target) disassemble_instructions (insts) + + print "Frame registers:" + registerList = frame.GetRegisters() + numRegisterSets = registerList.GetSize() + for i in range (0, numRegisterSets): + value = registerList.GetValueAtIndex(i) + print value + numChildren = value.GetNumChildren() + if numChildren > 0: + for j in range (0, numChildren): + child = value.GetChildAtIndex(j) + print "Name: ", child.GetName(), " Value: ", child.GetValue(frame) + print "Hit the breakpoint at main, continue and wait for program to exit..." # Now continue to the program exit process.Continue() From gclayton at apple.com Wed Mar 30 00:17:42 2011 From: gclayton at apple.com (Greg Clayton) Date: Tue, 29 Mar 2011 22:17:42 -0700 Subject: [Lldb-commits] [PATCH] give subclasses access to UnixSignals::m_signals In-Reply-To: <20110330002621.GA21373@fibrous.localdomain> References: <20110328003824.GA30603@fibrous.localdomain> <20110330002621.GA21373@fibrous.localdomain> Message-ID: Don't you want "protected:" so the subclasses can edit it? On Mar 29, 2011, at 5:26 PM, Stephen Wilson wrote: > > Any chance I could get a quick thumbs up on the following patch? > > I know this is a rater trivial change and I should probably just go > ahead and commit it. My main concern was if there are any short-term > plans to move the default darwin-specific implementation elsewhere -- > thus potentially making this change redundant. > > > On Sun, Mar 27, 2011 at 08:38:24PM -0400, Stephen Wilson wrote: >> >> Allow subclasses of UnixSignals to access m_signals by marking the >> member protected instead of private. This enables a subclass to provide >> a default signal set as appropriate on construction. >> >> >> >> diff --git a/include/lldb/Target/UnixSignals.h b/include/lldb/Target/UnixSignals.h >> index 3e13438..f47a90b 100644 >> --- a/include/lldb/Target/UnixSignals.h >> +++ b/include/lldb/Target/UnixSignals.h >> @@ -133,10 +133,6 @@ protected: >> void >> Reset (); >> >> -private: >> - //------------------------------------------------------------------ >> - // For UnixSignals only >> - //------------------------------------------------------------------ >> typedef std::map collection; >> >> collection m_signals; >> >> >> _______________________________________________ >> lldb-commits mailing list >> lldb-commits at cs.uiuc.edu >> http://lists.cs.uiuc.edu/mailman/listinfo/lldb-commits > > -- > steve > From ctice at apple.com Wed Mar 30 00:15:46 2011 From: ctice at apple.com (Caroline Tice) Date: Wed, 30 Mar 2011 05:15:46 -0000 Subject: [Lldb-commits] [lldb] r128525 - /lldb/trunk/source/Plugins/Instruction/ARM/EmulateInstructionARM.cpp Message-ID: <20110330051547.14F9E2A6C12C@llvm.org> Author: ctice Date: Wed Mar 30 00:15:46 2011 New Revision: 128525 URL: http://llvm.org/viewvc/llvm-project?rev=128525&view=rev Log: Fill in EmulateSTREX to emulate the STREX ARM instruction. Modified: lldb/trunk/source/Plugins/Instruction/ARM/EmulateInstructionARM.cpp Modified: lldb/trunk/source/Plugins/Instruction/ARM/EmulateInstructionARM.cpp URL: http://llvm.org/viewvc/llvm-project/lldb/trunk/source/Plugins/Instruction/ARM/EmulateInstructionARM.cpp?rev=128525&r1=128524&r2=128525&view=diff ============================================================================== --- lldb/trunk/source/Plugins/Instruction/ARM/EmulateInstructionARM.cpp (original) +++ lldb/trunk/source/Plugins/Instruction/ARM/EmulateInstructionARM.cpp Wed Mar 30 00:15:46 2011 @@ -9487,18 +9487,109 @@ } // A8.6.202 STREX +// Store Register Exclusive calculates an address from a base register value and an immediate offset, and stores a +// word from a register to memory if the executing processor has exclusive access to the memory addressed. bool EmulateInstructionARM::EmulateSTREX (const uint32_t opcode, const ARMEncoding encoding) { #if 0 + if ConditionPassed() then + EncodingSpecificOperations(); NullCheckIfThumbEE(n); + address = R[n] + imm32; + if ExclusiveMonitorsPass(address,4) then + MemA[address,4] = R[t]; + R[d] = 0; + else + R[d] = 1; #endif - //bool success = false; + bool success = false; if (ConditionPassed(opcode)) { + uint32_t d; + uint32_t t; + uint32_t n; + uint32_t imm32; + const uint32_t addr_byte_size = GetAddressByteSize(); + switch (encoding) { + case eEncodingT1: + // d = UInt(Rd); t = UInt(Rt); n = UInt(Rn); imm32 = ZeroExtend(imm8:???00???, 32); + d = Bits32 (opcode, 11, 8); + t = Bits32 (opcode, 15, 12); + n = Bits32 (opcode, 19, 16); + imm32 = Bits32 (opcode, 7, 0) << 2; + + // if BadReg(d) || BadReg(t) || n == 15 then UNPREDICTABLE; + if (BadReg (d) || BadReg (t) || (n == 15)) + return false; + + // if d == n || d == t then UNPREDICTABLE; + if ((d == n) || (d == t)) + return false; + + break; + + case eEncodingA1: + // d = UInt(Rd); t = UInt(Rt); n = UInt(Rn); imm32 = Zeros(32); // Zero offset + d = Bits32 (opcode, 15, 12); + t = Bits32 (opcode, 3, 0); + n = Bits32 (opcode, 19, 16); + imm32 = 0; + + // if d == 15 || t == 15 || n == 15 then UNPREDICTABLE; + if ((d == 15) || (t == 15) || (n == 15)) + return false; + + // if d == n || d == t then UNPREDICTABLE; + if ((d == n) || (d == t)) + return false; + + break; + + default: + return false; + } + + // address = R[n] + imm32; + uint32_t Rn = ReadCoreReg (n, &success); + if (!success) + return false; + + addr_t address = Rn + imm32; + + Register base_reg; + base_reg.SetRegister (eRegisterKindDWARF, dwarf_r0 + n); + Register data_reg; + data_reg.SetRegister (eRegisterKindDWARF, dwarf_r0 + t); + EmulateInstruction::Context context; + context.type = eContextRegisterStore; + context.SetRegisterToRegisterPlusOffset (data_reg, base_reg, imm32); + + // if ExclusiveMonitorsPass(address,4) then + // if (ExclusiveMonitorsPass (address, addr_byte_size)) -- For now, for the sake of emulation, we will say this + // always return true. + if (true) + { + // MemA[address,4] = R[t]; + uint32_t Rt = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_r0 + t, 0, &success); + if (!success) + return false; + + if (!MemAWrite (context, address, Rt, addr_byte_size)) + return false; + + // R[d] = 0; + if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_r0 + t, 0)) + return false; + } + else + { + // R[d] = 1; + if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_r0 + t, 1)) + return false; } } return true; @@ -10224,6 +10315,7 @@ { 0x0fd00000, 0x09800000, ARMvAll, eEncodingA1, eSize32, &EmulateInstructionARM::EmulateSTMIB, "stmib {!} " }, { 0x0e500010, 0x06000000, ARMvAll, eEncodingA1, eSize32, &EmulateInstructionARM::EmulateSTRRegister, "str [ +/- {}]{!}" }, { 0x0e5000f0, 0x000000b0, ARMvAll, eEncodingA1, eSize32, &EmulateInstructionARM::EmulateSTRHRegister, "strh ,[,+/-[{!}" }, + { 0x0ff00ff0, 0x01800f90, ARMV6_ABOVE, eEncodingA1, eSize32, &EmulateInstructionARM::EmulateSTREX, "strex , , []"}, //---------------------------------------------------------------------- // Other instructions @@ -10513,6 +10605,7 @@ { 0xfff00800, 0xf8000800, ARMV6T2_ABOVE, eEncodingT3, eSize32, &EmulateInstructionARM::EmulateSTRBThumb, "strb ,[, #+/-]{!}" }, { 0xfffffe00, 0x00005200, ARMV4T_ABOVE, eEncodingT1, eSize16, &EmulateInstructionARM::EmulateSTRHRegister, "strh ,[,]" }, { 0xfff00fc0, 0xf8200000, ARMV6T2_ABOVE, eEncodingT2, eSize32, &EmulateInstructionARM::EmulateSTRHRegister, "strh.w ,[,{,LSL #}]" }, + { 0xfff00000, 0xe8400000, ARMV6T2_ABOVE, eEncodingT1, eSize32, &EmulateInstructionARM::EmulateSTREX, "strex , , [}]" }, //---------------------------------------------------------------------- // Other instructions From wilsons at start.ca Wed Mar 30 00:32:59 2011 From: wilsons at start.ca (Stephen Wilson) Date: Wed, 30 Mar 2011 01:32:59 -0400 Subject: [Lldb-commits] [PATCH] give subclasses access to UnixSignals::m_signals In-Reply-To: References: <20110328003824.GA30603@fibrous.localdomain> <20110330002621.GA21373@fibrous.localdomain> Message-ID: <20110330053258.GA7462@fibrous.localdomain> On Tue, Mar 29, 2011 at 10:17:42PM -0700, Greg Clayton wrote: > Don't you want "protected:" so the subclasses can edit it? > There is not enough context to show it in the patch, but there is a "protected:" earlier on in the class declaration. > On Mar 29, 2011, at 5:26 PM, Stephen Wilson wrote: > > > > > Any chance I could get a quick thumbs up on the following patch? > > > > I know this is a rater trivial change and I should probably just go > > ahead and commit it. My main concern was if there are any short-term > > plans to move the default darwin-specific implementation elsewhere -- > > thus potentially making this change redundant. > > > > > > On Sun, Mar 27, 2011 at 08:38:24PM -0400, Stephen Wilson wrote: > >> > >> Allow subclasses of UnixSignals to access m_signals by marking the > >> member protected instead of private. This enables a subclass to provide > >> a default signal set as appropriate on construction. > >> > >> > >> > >> diff --git a/include/lldb/Target/UnixSignals.h b/include/lldb/Target/UnixSignals.h > >> index 3e13438..f47a90b 100644 > >> --- a/include/lldb/Target/UnixSignals.h > >> +++ b/include/lldb/Target/UnixSignals.h > >> @@ -133,10 +133,6 @@ protected: > >> void > >> Reset (); > >> > >> -private: > >> - //------------------------------------------------------------------ > >> - // For UnixSignals only > >> - //------------------------------------------------------------------ > >> typedef std::map collection; > >> > >> collection m_signals; > >> > >> > >> _______________________________________________ > >> lldb-commits mailing list > >> lldb-commits at cs.uiuc.edu > >> http://lists.cs.uiuc.edu/mailman/listinfo/lldb-commits > > > > -- > > steve > > -- steve From ctice at apple.com Wed Mar 30 00:40:56 2011 From: ctice at apple.com (Caroline Tice) Date: Wed, 30 Mar 2011 05:40:56 -0000 Subject: [Lldb-commits] [lldb] r128527 - /lldb/trunk/source/Plugins/Instruction/ARM/EmulateInstructionARM.cpp Message-ID: <20110330054056.A6E2D2A6C12C@llvm.org> Author: ctice Date: Wed Mar 30 00:40:56 2011 New Revision: 128527 URL: http://llvm.org/viewvc/llvm-project?rev=128527&view=rev Log: Fill in EmulateSTRBImmARM to emulate the STRB (immediate, ARM) instruction. Modified: lldb/trunk/source/Plugins/Instruction/ARM/EmulateInstructionARM.cpp Modified: lldb/trunk/source/Plugins/Instruction/ARM/EmulateInstructionARM.cpp URL: http://llvm.org/viewvc/llvm-project/lldb/trunk/source/Plugins/Instruction/ARM/EmulateInstructionARM.cpp?rev=128527&r1=128526&r2=128527&view=diff ============================================================================== --- lldb/trunk/source/Plugins/Instruction/ARM/EmulateInstructionARM.cpp (original) +++ lldb/trunk/source/Plugins/Instruction/ARM/EmulateInstructionARM.cpp Wed Mar 30 00:40:56 2011 @@ -9259,9 +9259,7 @@ dwarf_reg.SetRegister (eRegisterKindDWARF, dwarf_r0 + m); context.SetRegisterRegisterOperands (sp_reg, dwarf_reg); - uint32_t regnum = dwarf_r0 + d; - - if (!WriteCoreRegOptionalFlags(context, res.result, regnum, setflags, res.carry_out, res.overflow)) + if (!WriteCoreRegOptionalFlags(context, res.result, dwarf_r0 + d, setflags, res.carry_out, res.overflow)) return false; } return true; @@ -9478,9 +9476,7 @@ reg_m.SetRegister (eRegisterKindDWARF, m); context.SetRegisterRegisterOperands (reg_n, reg_m); - uint32_t dest_reg_num = dwarf_r0 + d; - - if (!WriteCoreRegOptionalFlags (context, res.result, dest_reg_num, setflags, res.carry_out, res.overflow)) + if (!WriteCoreRegOptionalFlags (context, res.result, dwarf_r0 + d, setflags, res.carry_out, res.overflow)) return false; } return true; @@ -9600,14 +9596,92 @@ EmulateInstructionARM::EmulateSTRBImmARM (const uint32_t opcode, const ARMEncoding encoding) { #if 0 + if ConditionPassed() then + EncodingSpecificOperations(); + offset_addr = if add then (R[n] + imm32) else (R[n] - imm32); + address = if index then offset_addr else R[n]; + MemU[address,1] = R[t]<7:0>; + if wback then R[n] = offset_addr; #endif - //bool success = false; + bool success = false; if (ConditionPassed(opcode)) { + uint32_t t; + uint32_t n; + uint32_t imm32; + bool index; + bool add; + bool wback; + switch (encoding) { + case eEncodingA1: + // if P == ???0??? && W == ???1??? then SEE STRBT; + // t = UInt(Rt); n = UInt(Rn); imm32 = ZeroExtend(imm12, 32); + t = Bits32 (opcode, 15, 12); + n = Bits32 (opcode, 19, 16); + imm32 = Bits32 (opcode, 11, 0); + + // index = (P == ???1???); add = (U == ???1???); wback = (P == ???0???) || (W == ???1???); + index = BitIsSet (opcode, 24); + add = BitIsSet (opcode, 23); + wback = BitIsClear (opcode, 24) || BitIsSet (opcode, 21); + + // if t == 15 then UNPREDICTABLE; + if (t == 15) + return false; + + // if wback && (n == 15 || n == t) then UNPREDICTABLE; + if (wback && ((n == 15) || (n == t))) + return false; + + break; + + default: + return false; + } + + // offset_addr = if add then (R[n] + imm32) else (R[n] - imm32); + uint32_t Rn = ReadCoreReg (n, &success); + if (!success) + return false; + + addr_t offset_addr; + if (add) + offset_addr = Rn + imm32; + else + offset_addr = Rn - imm32; + + // address = if index then offset_addr else R[n]; + addr_t address; + if (index) + address = offset_addr; + else + address = Rn; + + // MemU[address,1] = R[t]<7:0>; + uint32_t Rt = ReadCoreReg (t, &success); + if (!success) + return false; + + Register base_reg; + base_reg.SetRegister (eRegisterKindDWARF, n); + Register data_reg; + data_reg.SetRegister (eRegisterKindDWARF, t); + EmulateInstruction::Context context; + context.type = eContextRegisterStore; + context.SetRegisterToRegisterPlusOffset (data_reg, base_reg, address - Rn); + + if (!MemUWrite (context, address, Bits32 (Rt, 7, 0), 1)) + return false; + + // if wback then R[n] = offset_addr; + if (wback) + { + if (WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_r0 + n, offset_addr)) + return false; } } return true; @@ -10316,6 +10390,7 @@ { 0x0e500010, 0x06000000, ARMvAll, eEncodingA1, eSize32, &EmulateInstructionARM::EmulateSTRRegister, "str [ +/- {}]{!}" }, { 0x0e5000f0, 0x000000b0, ARMvAll, eEncodingA1, eSize32, &EmulateInstructionARM::EmulateSTRHRegister, "strh ,[,+/-[{!}" }, { 0x0ff00ff0, 0x01800f90, ARMV6_ABOVE, eEncodingA1, eSize32, &EmulateInstructionARM::EmulateSTREX, "strex , , []"}, + { 0x0e500000, 0x04400000, ARMvAll, eEncodingA1, eSize32, &EmulateInstructionARM::EmulateSTRBImmARM, "strb ,[,#+/-]!"}, //---------------------------------------------------------------------- // Other instructions @@ -10570,7 +10645,7 @@ { 0xfff00800, 0xf8100800, ARMV6T2_ABOVE, eEncodingT3, eSize32, &EmulateInstructionARM::EmulateLDRBImmediate, "ldrb ,[>Rn>, #+/-]{!}" }, { 0xff7f0000, 0xf81f0000, ARMV6T2_ABOVE, eEncodingT1, eSize32, &EmulateInstructionARM::EmulateLDRBLiteral, "ldrb ,[...]" }, { 0xfffffe00, 0x00005c00, ARMV6T2_ABOVE, eEncodingT1, eSize16, &EmulateInstructionARM::EmulateLDRBRegister, "ldrb ,[,]" }, - { 0xfff00fc0, 0xf8100000, ARMV6T2_ABOVE, eEncodingT2, eSize32,&EmulateInstructionARM::EmulateLDRBRegister, "ldrb.w ,[,{,LSL #imm2>}]" }, + { 0xfff00fc0, 0xf8100000, ARMV6T2_ABOVE, eEncodingT2, eSize32,&EmulateInstructionARM::EmulateLDRBRegister, "ldrb.w ,[,{,LSL #imm2>}]" }, { 0xfffff800, 0x00008800, ARMV4T_ABOVE, eEncodingT1, eSize16, &EmulateInstructionARM::EmulateLDRHImmediate, "ldrh , [{,#}]" }, { 0xfff00000, 0xf8b00000, ARMV6T2_ABOVE, eEncodingT2, eSize32, &EmulateInstructionARM::EmulateLDRHImmediate, "ldrh.w ,[{,#}]" }, { 0xfff00800, 0xf8300800, ARMV6T2_ABOVE, eEncodingT3, eSize32, &EmulateInstructionARM::EmulateLDRHImmediate, "ldrh ,[,#+/-]{!}" }, From ctice at apple.com Wed Mar 30 01:03:24 2011 From: ctice at apple.com (Caroline Tice) Date: Wed, 30 Mar 2011 06:03:24 -0000 Subject: [Lldb-commits] [lldb] r128528 - /lldb/trunk/source/Plugins/Instruction/ARM/EmulateInstructionARM.cpp Message-ID: <20110330060324.C20972A6C12C@llvm.org> Author: ctice Date: Wed Mar 30 01:03:24 2011 New Revision: 128528 URL: http://llvm.org/viewvc/llvm-project?rev=128528&view=rev Log: Fill in EmulateSTRImmARM to emulate the STR (immediate,ARM) instruction. Modified: lldb/trunk/source/Plugins/Instruction/ARM/EmulateInstructionARM.cpp Modified: lldb/trunk/source/Plugins/Instruction/ARM/EmulateInstructionARM.cpp URL: http://llvm.org/viewvc/llvm-project/lldb/trunk/source/Plugins/Instruction/ARM/EmulateInstructionARM.cpp?rev=128528&r1=128527&r2=128528&view=diff ============================================================================== --- lldb/trunk/source/Plugins/Instruction/ARM/EmulateInstructionARM.cpp (original) +++ lldb/trunk/source/Plugins/Instruction/ARM/EmulateInstructionARM.cpp Wed Mar 30 01:03:24 2011 @@ -9692,14 +9692,106 @@ EmulateInstructionARM::EmulateSTRImmARM (const uint32_t opcode, const ARMEncoding encoding) { #if 0 + if ConditionPassed() then + EncodingSpecificOperations(); + offset_addr = if add then (R[n] + imm32) else (R[n] - imm32); + address = if index then offset_addr else R[n]; + MemU[address,4] = if t == 15 then PCStoreValue() else R[t]; + if wback then R[n] = offset_addr; #endif - //bool success = false; + bool success = false; if (ConditionPassed(opcode)) { + uint32_t t; + uint32_t n; + uint32_t imm32; + bool index; + bool add; + bool wback; + + const uint32_t addr_byte_size = GetAddressByteSize(); + switch (encoding) { + case eEncodingA1: + // if P == ???0??? && W == ???1??? then SEE STRT; + // if Rn == ???1101??? && P == ???1??? && U == ???0??? && W == ???1??? && imm12 == ???000000000100??? then SEE PUSH; + // t = UInt(Rt); n = UInt(Rn); imm32 = ZeroExtend(imm12, 32); + t = Bits32 (opcode, 15, 12); + n = Bits32 (opcode, 19, 16); + imm32 = Bits32 (opcode, 11, 0); + + // index = (P == ???1???); add = (U == ???1???); wback = (P == ???0???) || (W == ???1???); + index = BitIsSet (opcode, 24); + add = BitIsSet (opcode, 23); + wback = BitIsClear (opcode, 24) || BitIsSet (opcode, 21); + + // if wback && (n == 15 || n == t) then UNPREDICTABLE; + if (wback && ((n == 15) || (n == t))) + return false; + + break; + + default: + return false; + } + + // offset_addr = if add then (R[n] + imm32) else (R[n] - imm32); + uint32_t Rn = ReadCoreReg (n, &success); + if (!success) + return false; + + addr_t offset_addr; + if (add) + offset_addr = Rn + imm32; + else + offset_addr = Rn - imm32; + + // address = if index then offset_addr else R[n]; + addr_t address; + if (index) + address = offset_addr; + else + address = Rn; + + Register base_reg; + base_reg.SetRegister (eRegisterKindDWARF, n); + Register data_reg; + data_reg.SetRegister (eRegisterKindDWARF, t); + EmulateInstruction::Context context; + context.type = eContextRegisterStore; + context.SetRegisterToRegisterPlusOffset (data_reg, base_reg, address - Rn); + + // MemU[address,4] = if t == 15 then PCStoreValue() else R[t]; + uint32_t Rt = ReadCoreReg (t, &success); + if (!success) + return false; + + if (t == 15) + { + uint32_t pc_value = ReadCoreReg (SP_REG, &success); + if (!success) + return false; + + if (!MemUWrite (context, address, pc_value, addr_byte_size)) + return false; + } + else + { + if (!MemUWrite (context, address, Rt, addr_byte_size)) + return false; + } + + // if wback then R[n] = offset_addr; + if (wback) + { + context.type = eContextAdjustBaseRegister; + context.SetImmediate (offset_addr); + + if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_r0 + n, offset_addr)) + return false; } } return true; @@ -10391,6 +10483,7 @@ { 0x0e5000f0, 0x000000b0, ARMvAll, eEncodingA1, eSize32, &EmulateInstructionARM::EmulateSTRHRegister, "strh ,[,+/-[{!}" }, { 0x0ff00ff0, 0x01800f90, ARMV6_ABOVE, eEncodingA1, eSize32, &EmulateInstructionARM::EmulateSTREX, "strex , , []"}, { 0x0e500000, 0x04400000, ARMvAll, eEncodingA1, eSize32, &EmulateInstructionARM::EmulateSTRBImmARM, "strb ,[,#+/-]!"}, + { 0x0e500000, 0x04000000, ARMvAll, eEncodingA1, eSize32, &EmulateInstructionARM::EmulateSTRImmARM, "str ,[,#+/-]!"}, //---------------------------------------------------------------------- // Other instructions From gclayton at apple.com Wed Mar 30 02:02:54 2011 From: gclayton at apple.com (Greg Clayton) Date: Wed, 30 Mar 2011 00:02:54 -0700 Subject: [Lldb-commits] [PATCH] give subclasses access to UnixSignals::m_signals In-Reply-To: <20110330053258.GA7462@fibrous.localdomain> References: <20110328003824.GA30603@fibrous.localdomain> <20110330002621.GA21373@fibrous.localdomain> <20110330053258.GA7462@fibrous.localdomain> Message-ID: Yikes, that was a minus sign on the diff to _remove_ the private... Looks good. Commit when desired! On Mar 29, 2011, at 10:32 PM, Stephen Wilson wrote: > On Tue, Mar 29, 2011 at 10:17:42PM -0700, Greg Clayton wrote: >> Don't you want "protected:" so the subclasses can edit it? >> > > There is not enough context to show it in the patch, but there is a > "protected:" earlier on in the class declaration. > > >> On Mar 29, 2011, at 5:26 PM, Stephen Wilson wrote: >> >>> >>> Any chance I could get a quick thumbs up on the following patch? >>> >>> I know this is a rater trivial change and I should probably just go >>> ahead and commit it. My main concern was if there are any short-term >>> plans to move the default darwin-specific implementation elsewhere -- >>> thus potentially making this change redundant. >>> >>> >>> On Sun, Mar 27, 2011 at 08:38:24PM -0400, Stephen Wilson wrote: >>>> >>>> Allow subclasses of UnixSignals to access m_signals by marking the >>>> member protected instead of private. This enables a subclass to provide >>>> a default signal set as appropriate on construction. >>>> >>>> >>>> >>>> diff --git a/include/lldb/Target/UnixSignals.h b/include/lldb/Target/UnixSignals.h >>>> index 3e13438..f47a90b 100644 >>>> --- a/include/lldb/Target/UnixSignals.h >>>> +++ b/include/lldb/Target/UnixSignals.h >>>> @@ -133,10 +133,6 @@ protected: >>>> void >>>> Reset (); >>>> >>>> -private: >>>> - //------------------------------------------------------------------ >>>> - // For UnixSignals only >>>> - //------------------------------------------------------------------ >>>> typedef std::map collection; >>>> >>>> collection m_signals; >>>> >>>> >>>> _______________________________________________ >>>> lldb-commits mailing list >>>> lldb-commits at cs.uiuc.edu >>>> http://lists.cs.uiuc.edu/mailman/listinfo/lldb-commits >>> >>> -- >>> steve >>> > > -- > steve > From wilsons at start.ca Wed Mar 30 10:33:24 2011 From: wilsons at start.ca (Stephen Wilson) Date: Wed, 30 Mar 2011 15:33:24 -0000 Subject: [Lldb-commits] [lldb] r128544 - /lldb/trunk/include/lldb/Target/UnixSignals.h Message-ID: <20110330153324.736DA2A6C12C@llvm.org> Author: wilsons Date: Wed Mar 30 10:33:24 2011 New Revision: 128544 URL: http://llvm.org/viewvc/llvm-project?rev=128544&view=rev Log: give subclasses access to UnixSignals::m_signals Allow subclasses of UnixSignals to access m_signals by marking the member protected instead of private. This enables a subclass to provide a default signal set as appropriate on construction. Modified: lldb/trunk/include/lldb/Target/UnixSignals.h Modified: lldb/trunk/include/lldb/Target/UnixSignals.h URL: http://llvm.org/viewvc/llvm-project/lldb/trunk/include/lldb/Target/UnixSignals.h?rev=128544&r1=128543&r2=128544&view=diff ============================================================================== --- lldb/trunk/include/lldb/Target/UnixSignals.h (original) +++ lldb/trunk/include/lldb/Target/UnixSignals.h Wed Mar 30 10:33:24 2011 @@ -133,10 +133,6 @@ void Reset (); -private: - //------------------------------------------------------------------ - // For UnixSignals only - //------------------------------------------------------------------ typedef std::map collection; collection m_signals; From wilsons at start.ca Wed Mar 30 10:55:53 2011 From: wilsons at start.ca (Stephen Wilson) Date: Wed, 30 Mar 2011 15:55:53 -0000 Subject: [Lldb-commits] [lldb] r128547 - in /lldb/trunk/source/Plugins/Process/Linux: LinuxSignals.cpp LinuxSignals.h LinuxStopInfo.cpp LinuxStopInfo.h LinuxThread.cpp LinuxThread.h ProcessLinux.cpp ProcessLinux.h ProcessMessage.cpp ProcessMessage.h ProcessMonitor.cpp ProcessMonitor.h Message-ID: <20110330155553.3C5272A6C12C@llvm.org> Author: wilsons Date: Wed Mar 30 10:55:52 2011 New Revision: 128547 URL: http://llvm.org/viewvc/llvm-project?rev=128547&view=rev Log: linux: initial support for 'real' signal handling This patch upgrades the Linux process plugin to handle a larger range of signal events. For example, we can detect when the inferior has "crashed" and why, interrupt a running process, deliver an arbitrary signal, and so on. Added: lldb/trunk/source/Plugins/Process/Linux/LinuxSignals.cpp lldb/trunk/source/Plugins/Process/Linux/LinuxSignals.h lldb/trunk/source/Plugins/Process/Linux/LinuxStopInfo.cpp lldb/trunk/source/Plugins/Process/Linux/LinuxStopInfo.h lldb/trunk/source/Plugins/Process/Linux/ProcessMessage.cpp Modified: lldb/trunk/source/Plugins/Process/Linux/LinuxThread.cpp lldb/trunk/source/Plugins/Process/Linux/LinuxThread.h lldb/trunk/source/Plugins/Process/Linux/ProcessLinux.cpp lldb/trunk/source/Plugins/Process/Linux/ProcessLinux.h lldb/trunk/source/Plugins/Process/Linux/ProcessMessage.h lldb/trunk/source/Plugins/Process/Linux/ProcessMonitor.cpp lldb/trunk/source/Plugins/Process/Linux/ProcessMonitor.h Added: lldb/trunk/source/Plugins/Process/Linux/LinuxSignals.cpp URL: http://llvm.org/viewvc/llvm-project/lldb/trunk/source/Plugins/Process/Linux/LinuxSignals.cpp?rev=128547&view=auto ============================================================================== --- lldb/trunk/source/Plugins/Process/Linux/LinuxSignals.cpp (added) +++ lldb/trunk/source/Plugins/Process/Linux/LinuxSignals.cpp Wed Mar 30 10:55:52 2011 @@ -0,0 +1,67 @@ +//===-- LinuxSignals.cpp ----------------------------------------*- C++ -*-===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// + +// C Includes +#include + +// C++ Includes +// Other libraries and framework includes +// Project includes +#include "LinuxSignals.h" + +LinuxSignals::LinuxSignals() + : UnixSignals() +{ + Reset(); +} + +void +LinuxSignals::Reset() +{ + m_signals.clear(); + +#define ADDSIGNAL(S, SUPPRESS, STOP, NOTIFY, DESCRIPTION) \ + AddSignal(SIG ## S, "SIG" #S, #S, SUPPRESS, STOP, NOTIFY, DESCRIPTION) + + ADDSIGNAL(HUP, false, true, true, "hangup"); + ADDSIGNAL(INT, true, true, true, "interrupt"); + ADDSIGNAL(QUIT, false, true, true, "quit"); + ADDSIGNAL(ILL, false, true, true, "illegal instruction"); + ADDSIGNAL(TRAP, true, true, true, "trace trap (not reset when caught)"); + ADDSIGNAL(ABRT, false, true, true, "abort"); + ADDSIGNAL(IOT, false, true, true, "abort"); + ADDSIGNAL(BUS, false, true, true, "bus error"); + ADDSIGNAL(FPE, false, true, true, "floating point exception"); + ADDSIGNAL(KILL, false, true, true, "kill"); + ADDSIGNAL(USR1, false, true, true, "user defined signal 1"); + ADDSIGNAL(SEGV, false, true, true, "segmentation violation"); + ADDSIGNAL(USR2, false, true, true, "user defined signal 2"); + ADDSIGNAL(PIPE, false, true, true, "write to pipe with reading end closed"); + ADDSIGNAL(ALRM, false, false, true, "alarm"); + ADDSIGNAL(TERM, false, true, true, "termination requested"); + ADDSIGNAL(STKFLT, false, true, true, "stack fault"); + ADDSIGNAL(CHLD, false, false, true, "child process exit"); + ADDSIGNAL(CONT, false, true, true, "process continue"); + ADDSIGNAL(STOP, false, true, true, "process stop"); + ADDSIGNAL(TSTP, false, true, true, "tty stop"); + ADDSIGNAL(TTIN, false, true, true, "background tty read"); + ADDSIGNAL(TTOU, false, true, true, "background tty write"); + ADDSIGNAL(URG, false, true, true, "urgent data on socket"); + ADDSIGNAL(XCPU, false, true, true, "CPU resource exceeded"); + ADDSIGNAL(XFSZ, false, true, true, "file size limit exceeded"); + ADDSIGNAL(VTALRM, false, true, true, "virtual alarm"); + ADDSIGNAL(PROF, false, true, true, "profiling alarm"); + ADDSIGNAL(WINCH, false, true, true, "window size change"); + ADDSIGNAL(POLL, false, true, true, "pollable event"); + ADDSIGNAL(IO, false, true, true, "input/output ready"); + ADDSIGNAL(PWR, false, true, true, "power failure"); + ADDSIGNAL(SYS, false, true, true, "invalid system call"); + +#undef ADDSIGNAL +} Added: lldb/trunk/source/Plugins/Process/Linux/LinuxSignals.h URL: http://llvm.org/viewvc/llvm-project/lldb/trunk/source/Plugins/Process/Linux/LinuxSignals.h?rev=128547&view=auto ============================================================================== --- lldb/trunk/source/Plugins/Process/Linux/LinuxSignals.h (added) +++ lldb/trunk/source/Plugins/Process/Linux/LinuxSignals.h Wed Mar 30 10:55:52 2011 @@ -0,0 +1,31 @@ +//===-- LinuxSignals.h ------------------------------------------*- C++ -*-===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// + +#ifndef liblldb_LinuxSignals_H_ +#define liblldb_LinuxSignals_H_ + +// C Includes +// C++ Includes +// Other libraries and framework includes +// Project includes +#include "lldb/Target/UnixSignals.h" + +/// Linux specific set of Unix signals. +class LinuxSignals + : public lldb_private::UnixSignals +{ +public: + LinuxSignals(); + +private: + void + Reset(); +}; + +#endif Added: lldb/trunk/source/Plugins/Process/Linux/LinuxStopInfo.cpp URL: http://llvm.org/viewvc/llvm-project/lldb/trunk/source/Plugins/Process/Linux/LinuxStopInfo.cpp?rev=128547&view=auto ============================================================================== --- lldb/trunk/source/Plugins/Process/Linux/LinuxStopInfo.cpp (added) +++ lldb/trunk/source/Plugins/Process/Linux/LinuxStopInfo.cpp Wed Mar 30 10:55:52 2011 @@ -0,0 +1,60 @@ +//===-- LinuxStopInfo.cpp ---------------------------------------*- C++ -*-===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// + +#include "LinuxStopInfo.h" + +using namespace lldb; +using namespace lldb_private; + + +//===----------------------------------------------------------------------===// +// LinuxLimboStopInfo + +LinuxLimboStopInfo::~LinuxLimboStopInfo() { } + +lldb::StopReason +LinuxLimboStopInfo::GetStopReason() const +{ + return lldb::eStopReasonTrace; +} + +const char * +LinuxLimboStopInfo::GetDescription() +{ + return "thread exiting"; +} + +bool +LinuxLimboStopInfo::ShouldStop(Event *event_ptr) +{ + return true; +} + +bool +LinuxLimboStopInfo::ShouldNotify(Event *event_ptr) +{ + return true; +} + +//===----------------------------------------------------------------------===// +// LinuxCrashStopInfo + +LinuxCrashStopInfo::~LinuxCrashStopInfo() { } + +lldb::StopReason +LinuxCrashStopInfo::GetStopReason() const +{ + return lldb::eStopReasonException; +} + +const char * +LinuxCrashStopInfo::GetDescription() +{ + return ProcessMessage::GetCrashReasonString(m_crash_reason); +} Added: lldb/trunk/source/Plugins/Process/Linux/LinuxStopInfo.h URL: http://llvm.org/viewvc/llvm-project/lldb/trunk/source/Plugins/Process/Linux/LinuxStopInfo.h?rev=128547&view=auto ============================================================================== --- lldb/trunk/source/Plugins/Process/Linux/LinuxStopInfo.h (added) +++ lldb/trunk/source/Plugins/Process/Linux/LinuxStopInfo.h Wed Mar 30 10:55:52 2011 @@ -0,0 +1,92 @@ +//===-- LinuxStopInfo.h -----------------------------------------*- C++ -*-===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// + +#ifndef liblldb_LinuxStopInfo_H_ +#define liblldb_LinuxStopInfo_H_ + +// C Includes +// C++ Includes +// Other libraries and framework includes +// Project includes +#include "lldb/Target/StopInfo.h" + +#include "LinuxThread.h" +#include "ProcessMessage.h" + +//===----------------------------------------------------------------------===// +/// @class LinuxStopInfo +/// @brief Simple base class for all Linux-specific StopInfo objects. +/// +class LinuxStopInfo + : public lldb_private::StopInfo +{ +public: + LinuxStopInfo(lldb_private::Thread &thread, uint32_t status) + : StopInfo(thread, status) + { } +}; + +//===----------------------------------------------------------------------===// +/// @class LinuxLimboStopInfo +/// @brief Represents the stop state of a process ready to exit. +/// +class LinuxLimboStopInfo + : public LinuxStopInfo +{ +public: + LinuxLimboStopInfo(LinuxThread &thread) + : LinuxStopInfo(thread, 0) + { } + + ~LinuxLimboStopInfo(); + + lldb::StopReason + GetStopReason() const; + + const char * + GetDescription(); + + bool + ShouldStop(lldb_private::Event *event_ptr); + + bool + ShouldNotify(lldb_private::Event *event_ptr); +}; + + +//===----------------------------------------------------------------------===// +/// @class LinuxCrashStopInfo +/// @brief Represents the stop state of process that is ready to crash. +/// +class LinuxCrashStopInfo + : public LinuxStopInfo +{ +public: + LinuxCrashStopInfo(LinuxThread &thread, uint32_t status, + ProcessMessage::CrashReason reason) + : LinuxStopInfo(thread, status), + m_crash_reason(reason) + { } + + ~LinuxCrashStopInfo(); + + lldb::StopReason + GetStopReason() const; + + const char * + GetDescription(); + + ProcessMessage::CrashReason + GetCrashReason() const; + +private: + ProcessMessage::CrashReason m_crash_reason; +}; + +#endif Modified: lldb/trunk/source/Plugins/Process/Linux/LinuxThread.cpp URL: http://llvm.org/viewvc/llvm-project/lldb/trunk/source/Plugins/Process/Linux/LinuxThread.cpp?rev=128547&r1=128546&r2=128547&view=diff ============================================================================== --- lldb/trunk/source/Plugins/Process/Linux/LinuxThread.cpp (original) +++ lldb/trunk/source/Plugins/Process/Linux/LinuxThread.cpp Wed Mar 30 10:55:52 2011 @@ -12,11 +12,13 @@ // C++ Includes // Other libraries and framework includes +// Project includes #include "lldb/Host/Host.h" #include "lldb/Target/Process.h" #include "lldb/Target/StopInfo.h" #include "lldb/Target/Target.h" +#include "LinuxStopInfo.h" #include "LinuxThread.h" #include "ProcessLinux.h" #include "ProcessMonitor.h" @@ -26,11 +28,10 @@ using namespace lldb_private; + LinuxThread::LinuxThread(Process &process, lldb::tid_t tid) : Thread(process, tid), - m_frame_ap(0), - m_stop_info_id(0), - m_note(eNone) + m_frame_ap(0) { } @@ -49,7 +50,6 @@ void LinuxThread::RefreshStateAfterStop() { - RefreshPrivateStopReason(); } const char * @@ -117,10 +117,6 @@ lldb::StopInfoSP LinuxThread::GetPrivateStopReason() { - const uint32_t process_stop_id = GetProcess().GetStopID(); - - if (m_stop_info_id != process_stop_id || !m_stop_info || !m_stop_info->IsValid()) - RefreshPrivateStopReason(); return m_stop_info; } @@ -152,34 +148,64 @@ ProcessMonitor &monitor = GetMonitor(); bool status; - switch (GetResumeState()) + switch (resume_state) { default: assert(false && "Unexpected state for resume!"); status = false; break; - case lldb::eStateSuspended: - // FIXME: Implement process suspension. - status = false; - case lldb::eStateRunning: SetState(resume_state); - status = monitor.Resume(GetID()); + status = monitor.Resume(GetID(), GetResumeSignal()); break; case lldb::eStateStepping: SetState(resume_state); - status = monitor.SingleStep(GetID()); + status = monitor.SingleStep(GetID(), GetResumeSignal()); break; } - m_note = eNone; return status; } void -LinuxThread::BreakNotify() +LinuxThread::Notify(const ProcessMessage &message) +{ + switch (message.GetKind()) + { + default: + assert(false && "Unexpected message kind!"); + break; + + case ProcessMessage::eLimboMessage: + LimboNotify(message); + break; + + case ProcessMessage::eSignalMessage: + SignalNotify(message); + break; + + case ProcessMessage::eSignalDeliveredMessage: + SignalDeliveredNotify(message); + break; + + case ProcessMessage::eTraceMessage: + TraceNotify(message); + break; + + case ProcessMessage::eBreakpointMessage: + BreakNotify(message); + break; + + case ProcessMessage::eCrashMessage: + CrashNotify(message); + break; + } +} + +void +LinuxThread::BreakNotify(const ProcessMessage &message) { bool status; @@ -190,47 +216,53 @@ // corresponding to our current PC. lldb::addr_t pc = GetRegisterContext()->GetPC(); lldb::BreakpointSiteSP bp_site(GetProcess().GetBreakpointSiteList().FindByAddress(pc)); + lldb::break_id_t bp_id = bp_site->GetID(); assert(bp_site && bp_site->ValidForThisThread(this)); - m_note = eBreak; + m_breakpoint = bp_site; + m_stop_info = StopInfo::CreateStopReasonWithBreakpointSiteID(*this, bp_id); } void -LinuxThread::TraceNotify() +LinuxThread::TraceNotify(const ProcessMessage &message) { - m_note = eTrace; + m_stop_info = StopInfo::CreateStopReasonToTrace(*this); } void -LinuxThread::ExitNotify() +LinuxThread::LimboNotify(const ProcessMessage &message) { - m_note = eExit; + m_stop_info = lldb::StopInfoSP(new LinuxLimboStopInfo(*this)); } void -LinuxThread::RefreshPrivateStopReason() +LinuxThread::SignalNotify(const ProcessMessage &message) { - m_stop_info_id = GetProcess().GetStopID(); + int signo = message.GetSignal(); - switch (m_note) { + m_stop_info = StopInfo::CreateStopReasonWithSignal(*this, signo); + SetResumeSignal(signo); +} - default: - case eNone: - m_stop_info.reset(); - break; +void +LinuxThread::SignalDeliveredNotify(const ProcessMessage &message) +{ + int signo = message.GetSignal(); - case eBreak: - m_stop_info = StopInfo::CreateStopReasonWithBreakpointSiteID( - *this, m_breakpoint->GetID()); - break; + // Just treat debugger generated signal events like breakpoints for now. + m_stop_info = StopInfo::CreateStopReasonToTrace(*this); + SetResumeSignal(signo); +} - case eTrace: - m_stop_info = StopInfo::CreateStopReasonToTrace(*this); - break; +void +LinuxThread::CrashNotify(const ProcessMessage &message) +{ + int signo = message.GetSignal(); - case eExit: - m_stop_info = StopInfo::CreateStopReasonWithSignal(*this, SIGCHLD); - break; - } + assert(message.GetKind() == ProcessMessage::eCrashMessage); + + m_stop_info = lldb::StopInfoSP(new LinuxCrashStopInfo( + *this, signo, message.GetCrashReason())); + SetResumeSignal(signo); } Modified: lldb/trunk/source/Plugins/Process/Linux/LinuxThread.h URL: http://llvm.org/viewvc/llvm-project/lldb/trunk/source/Plugins/Process/Linux/LinuxThread.h?rev=128547&r1=128546&r2=128547&view=diff ============================================================================== --- lldb/trunk/source/Plugins/Process/Linux/LinuxThread.h (original) +++ lldb/trunk/source/Plugins/Process/Linux/LinuxThread.h Wed Mar 30 10:55:52 2011 @@ -17,6 +17,7 @@ // Other libraries and framework includes #include "lldb/Target/Thread.h" +class ProcessMessage; class ProcessMonitor; class RegisterContextLinux; @@ -51,9 +52,7 @@ // bool Resume(); - void BreakNotify(); - void TraceNotify(); - void ExitNotify(); + void Notify(const ProcessMessage &message); protected: virtual bool @@ -63,7 +62,6 @@ RestoreSaveFrameZero(const RegisterCheckpoint &checkpoint); private: - RegisterContextLinux * GetRegisterContextLinux () { @@ -77,26 +75,18 @@ lldb::BreakpointSiteSP m_breakpoint; lldb::StopInfoSP m_stop_info; - // Cached process stop id. Used to ensure we do not recalculate stop - // information/state needlessly. - uint32_t m_stop_info_id; - - enum Notification { - eNone, - eBreak, - eTrace, - eExit - }; - - Notification m_note; - - ProcessMonitor &GetMonitor(); + ProcessMonitor & + GetMonitor(); lldb::StopInfoSP GetPrivateStopReason(); - void - RefreshPrivateStopReason(); + void BreakNotify(const ProcessMessage &message); + void TraceNotify(const ProcessMessage &message); + void LimboNotify(const ProcessMessage &message); + void SignalNotify(const ProcessMessage &message); + void SignalDeliveredNotify(const ProcessMessage &message); + void CrashNotify(const ProcessMessage &message); lldb_private::Unwind * GetUnwinder(); Modified: lldb/trunk/source/Plugins/Process/Linux/ProcessLinux.cpp URL: http://llvm.org/viewvc/llvm-project/lldb/trunk/source/Plugins/Process/Linux/ProcessLinux.cpp?rev=128547&r1=128546&r2=128547&view=diff ============================================================================== --- lldb/trunk/source/Plugins/Process/Linux/ProcessLinux.cpp (original) +++ lldb/trunk/source/Plugins/Process/Linux/ProcessLinux.cpp Wed Mar 30 10:55:52 2011 @@ -72,7 +72,9 @@ ProcessLinux::ProcessLinux(Target& target, Listener &listener) : Process(target, listener), m_monitor(NULL), - m_module(NULL) + m_module(NULL), + m_in_limbo(false), + m_exit_now(false) { // FIXME: Putting this code in the ctor and saving the byte order in a // member variable is a hack to avoid const qual issues in GetByteOrder. @@ -147,11 +149,20 @@ Error ProcessLinux::DoResume() { - assert(GetPrivateState() == eStateStopped && "Bad state for DoResume!"); + StateType state = GetPrivateState(); - // Set our state to running. This ensures inferior threads do not post a - // state change first. - SetPrivateState(eStateRunning); + assert(state == eStateStopped || state == eStateCrashed); + + // We are about to resume a thread that will cause the process to exit so + // set our exit status now. Do not change our state if the inferior + // crashed. + if (state == eStateStopped) + { + if (m_in_limbo) + SetExitStatus(m_exit_status, NULL); + else + SetPrivateState(eStateRunning); + } bool did_resume = false; uint32_t thread_count = m_thread_list.GetSize(false); @@ -182,7 +193,23 @@ Error ProcessLinux::DoHalt(bool &caused_stop) { - return Error(1, eErrorTypeGeneric); + Error error; + + if (IsStopped()) + { + caused_stop = false; + } + else if (kill(GetID(), SIGSTOP)) + { + caused_stop = false; + error.SetErrorToErrno(); + } + else + { + caused_stop = true; + } + + return error; } Error @@ -194,7 +221,12 @@ Error ProcessLinux::DoSignal(int signal) { - return Error(1, eErrorTypeGeneric); + Error error; + + if (kill(GetID(), signal)) + error.SetErrorToErrno(); + + return error; } Error @@ -204,42 +236,19 @@ if (!HasExited()) { - // Shut down the private state thread as we will synchronize with events - // ourselves. Discard all current thread plans. - PausePrivateStateThread(); - GetThreadList().DiscardThreadPlans(); - - // Bringing the inferior into limbo will be caught by our monitor - // thread, in turn updating the process state. - if (!m_monitor->BringProcessIntoLimbo()) + // Drive the exit event to completion (do not keep the inferior in + // limbo). + m_exit_now = true; + + if (kill(m_monitor->GetPID(), SIGKILL) && error.Success()) { - error.SetErrorToGenericError(); - error.SetErrorString("Process termination failed."); + error.SetErrorToErrno(); return error; } - // Wait for the event to arrive. This is guaranteed to be an exit event. - StateType state; - EventSP event; - do { - TimeValue timeout_time; - timeout_time = TimeValue::Now(); - timeout_time.OffsetWithSeconds(2); - state = WaitForStateChangedEventsPrivate(&timeout_time, event); - } while (state != eStateExited && state != eStateInvalid); - - // Check if we timed out waiting for the exit event to arrive. - if (state == eStateInvalid) - error.SetErrorString("ProcessLinux::DoDestroy timed out."); - - // Restart standard event handling and send the process the final kill, - // driving it out of limbo. - ResumePrivateStateThread(); + SetPrivateState(eStateExited); } - if (kill(m_monitor->GetPID(), SIGKILL) && error.Success()) - error.SetErrorToErrno(); - return error; } @@ -251,18 +260,41 @@ switch (message.GetKind()) { default: - SetPrivateState(eStateStopped); + assert(false && "Unexpected process message!"); break; case ProcessMessage::eInvalidMessage: return; + case ProcessMessage::eLimboMessage: + m_in_limbo = true; + m_exit_status = message.GetExitStatus(); + if (m_exit_now) + { + SetPrivateState(eStateExited); + m_monitor->Detach(); + } + else + SetPrivateState(eStateStopped); + break; + case ProcessMessage::eExitMessage: - SetExitStatus(message.GetExitStatus(), NULL); + m_exit_status = message.GetExitStatus(); + SetExitStatus(m_exit_status, NULL); + break; + + case ProcessMessage::eTraceMessage: + case ProcessMessage::eBreakpointMessage: + SetPrivateState(eStateStopped); break; case ProcessMessage::eSignalMessage: - SetExitStatus(-1, NULL); + case ProcessMessage::eSignalDeliveredMessage: + SetPrivateState(eStateStopped); + break; + + case ProcessMessage::eCrashMessage: + SetPrivateState(eStateCrashed); break; } @@ -278,30 +310,12 @@ ProcessMessage &message = m_message_queue.front(); - // Resolve the thread this message corresponds to. + // Resolve the thread this message corresponds to and pass it along. lldb::tid_t tid = message.GetTID(); LinuxThread *thread = static_cast( GetThreadList().FindThreadByID(tid, false).get()); - switch (message.GetKind()) - { - default: - assert(false && "Unexpected message kind!"); - break; - - case ProcessMessage::eExitMessage: - case ProcessMessage::eSignalMessage: - thread->ExitNotify(); - break; - - case ProcessMessage::eTraceMessage: - thread->TraceNotify(); - break; - - case ProcessMessage::eBreakpointMessage: - thread->BreakNotify(); - break; - } + thread->Notify(message); m_message_queue.pop(); } @@ -432,6 +446,11 @@ return GetSTDOUT(buf, len, error); } +UnixSignals & +ProcessLinux::GetUnixSignals() +{ + return m_linux_signals; +} //------------------------------------------------------------------------------ // ProcessInterface protocol. @@ -482,8 +501,6 @@ default: break; - case eStateUnloaded: - case eStateCrashed: case eStateDetached: case eStateExited: return true; @@ -491,3 +508,20 @@ return false; } + +bool +ProcessLinux::IsStopped() +{ + switch (GetPrivateState()) + { + default: + break; + + case eStateStopped: + case eStateCrashed: + case eStateSuspended: + return true; + } + + return false; +} Modified: lldb/trunk/source/Plugins/Process/Linux/ProcessLinux.h URL: http://llvm.org/viewvc/llvm-project/lldb/trunk/source/Plugins/Process/Linux/ProcessLinux.h?rev=128547&r1=128546&r2=128547&view=diff ============================================================================== --- lldb/trunk/source/Plugins/Process/Linux/ProcessLinux.h (original) +++ lldb/trunk/source/Plugins/Process/Linux/ProcessLinux.h Wed Mar 30 10:55:52 2011 @@ -17,6 +17,7 @@ // Other libraries and framework includes #include "lldb/Target/Process.h" +#include "LinuxSignals.h" #include "ProcessMessage.h" class ProcessMonitor; @@ -178,6 +179,9 @@ ProcessMonitor &GetMonitor() { return *m_monitor; } + lldb_private::UnixSignals & + GetUnixSignals(); + private: /// Target byte order. lldb::ByteOrder m_byte_order; @@ -192,6 +196,19 @@ lldb_private::Mutex m_message_mutex; std::queue m_message_queue; + /// True when the process has entered a state of "limbo". + /// + /// This flag qualifies eStateStopped. It lets us know that when we + /// continue from this state the process will exit. Also, when true, + /// Process::m_exit_status is set. + bool m_in_limbo; + + /// Drive any exit events to completion. + bool m_exit_now; + + /// Linux-specific signal set. + LinuxSignals m_linux_signals; + /// Updates the loaded sections provided by the executable. /// /// FIXME: It would probably be better to delegate this task to the @@ -200,6 +217,9 @@ /// Returns true if the process has exited. bool HasExited(); + + /// Returns true if the process is stopped. + bool IsStopped(); }; #endif // liblldb_MacOSXProcess_H_ Added: lldb/trunk/source/Plugins/Process/Linux/ProcessMessage.cpp URL: http://llvm.org/viewvc/llvm-project/lldb/trunk/source/Plugins/Process/Linux/ProcessMessage.cpp?rev=128547&view=auto ============================================================================== --- lldb/trunk/source/Plugins/Process/Linux/ProcessMessage.cpp (added) +++ lldb/trunk/source/Plugins/Process/Linux/ProcessMessage.cpp Wed Mar 30 10:55:52 2011 @@ -0,0 +1,91 @@ +//===-- ProcessMessage.cpp --------------------------------------*- C++ -*-===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// + +#include "ProcessMessage.h" + +using namespace lldb_private; + +const char * +ProcessMessage::GetCrashReasonString(CrashReason reason) +{ + const char *str = NULL; + + switch (reason) + { + default: + assert(false && "invalid CrashReason"); + break; + + case eInvalidAddress: + str = "invalid address"; + break; + case ePrivilegedAddress: + str = "address access protected"; + break; + case eIllegalOpcode: + str = "illegal instruction"; + break; + case eIllegalOperand: + str = "illegal instruction operand"; + break; + case eIllegalAddressingMode: + str = "illegal addressing mode"; + break; + case eIllegalTrap: + str = "illegal trap"; + break; + case ePrivilegedOpcode: + str = "privileged instruction"; + break; + case ePrivilegedRegister: + str = "privileged register"; + break; + case eCoprocessorError: + str = "coprocessor error"; + break; + case eInternalStackError: + str = "internal stack error"; + break; + case eIllegalAlignment: + str = "illegal alignment"; + break; + case eIllegalAddress: + str = "illegal address"; + break; + case eHardwareError: + str = "hardware error"; + break; + case eIntegerDivideByZero: + str = "integer divide by zero"; + break; + case eIntegerOverflow: + str = "integer overflow"; + break; + case eFloatDivideByZero: + str = "floating point divide by zero"; + break; + case eFloatOverflow: + str = "floating point overflow"; + break; + case eFloatUnderflow: + str = "floating point underflow"; + break; + case eFloatInexactResult: + str = "inexact floating point result"; + break; + case eFloatInvalidOperation: + str = "invalid floating point operation"; + break; + case eFloatSubscriptRange: + str = "invalid floating point subscript range"; + break; + } + + return str; +} Modified: lldb/trunk/source/Plugins/Process/Linux/ProcessMessage.h URL: http://llvm.org/viewvc/llvm-project/lldb/trunk/source/Plugins/Process/Linux/ProcessMessage.h?rev=128547&r1=128546&r2=128547&view=diff ============================================================================== --- lldb/trunk/source/Plugins/Process/Linux/ProcessMessage.h (original) +++ lldb/trunk/source/Plugins/Process/Linux/ProcessMessage.h Wed Mar 30 10:55:52 2011 @@ -26,63 +26,134 @@ eExitMessage, eLimboMessage, eSignalMessage, + eSignalDeliveredMessage, eTraceMessage, - eBreakpointMessage + eBreakpointMessage, + eCrashMessage + }; + + enum CrashReason + { + eInvalidCrashReason, + + // SIGSEGV crash reasons. + eInvalidAddress, + ePrivilegedAddress, + + // SIGILL crash reasons. + eIllegalOpcode, + eIllegalOperand, + eIllegalAddressingMode, + eIllegalTrap, + ePrivilegedOpcode, + ePrivilegedRegister, + eCoprocessorError, + eInternalStackError, + + // SIGBUS crash reasons, + eIllegalAlignment, + eIllegalAddress, + eHardwareError, + + // SIGFPE crash reasons, + eIntegerDivideByZero, + eIntegerOverflow, + eFloatDivideByZero, + eFloatOverflow, + eFloatUnderflow, + eFloatInexactResult, + eFloatInvalidOperation, + eFloatSubscriptRange }; ProcessMessage() - : m_kind(eInvalidMessage), - m_tid(LLDB_INVALID_PROCESS_ID), - m_data(0) { } + : m_tid(LLDB_INVALID_PROCESS_ID), + m_kind(eInvalidMessage), + m_crash_reason(eInvalidCrashReason), + m_status(0), + m_addr(0) { } Kind GetKind() const { return m_kind; } lldb::tid_t GetTID() const { return m_tid; } - static ProcessMessage Exit(lldb::tid_t tid, int status) { - return ProcessMessage(tid, eExitMessage, status); - } - + /// Indicates that the thread @p tid is about to exit with status @p status. static ProcessMessage Limbo(lldb::tid_t tid, int status) { return ProcessMessage(tid, eLimboMessage, status); } + /// Indicates that the thread @p tid had the signal @p signum delivered. static ProcessMessage Signal(lldb::tid_t tid, int signum) { return ProcessMessage(tid, eSignalMessage, signum); } + /// Indicates that a signal @p signum generated by the debugging process was + /// delivered to the thread @p tid. + static ProcessMessage SignalDelivered(lldb::tid_t tid, int signum) { + return ProcessMessage(tid, eSignalDeliveredMessage, signum); + } + + /// Indicates that the thread @p tid encountered a trace point. static ProcessMessage Trace(lldb::tid_t tid) { return ProcessMessage(tid, eTraceMessage); } + /// Indicates that the thread @p tid encountered a break point. static ProcessMessage Break(lldb::tid_t tid) { return ProcessMessage(tid, eBreakpointMessage); } + /// Indicates that the thread @p tid crashed. + static ProcessMessage Crash(lldb::pid_t pid, CrashReason reason, + int signo, lldb::addr_t fault_addr) { + ProcessMessage message(pid, eCrashMessage, signo, fault_addr); + message.m_crash_reason = reason; + return message; + } + int GetExitStatus() const { assert(GetKind() == eExitMessage || GetKind() == eLimboMessage); - return m_data; + return m_status; } int GetSignal() const { - assert(GetKind() == eSignalMessage); - return m_data; + assert(GetKind() == eSignalMessage || GetKind() == eCrashMessage || + GetKind() == eSignalDeliveredMessage); + return m_status; } int GetStopStatus() const { assert(GetKind() == eSignalMessage); - return m_data; + return m_status; + } + + CrashReason GetCrashReason() const { + assert(GetKind() == eCrashMessage); + return m_crash_reason; } + lldb::addr_t GetFaultAddress() const { + assert(GetKind() == eCrashMessage); + return m_addr; + } + + static const char * + GetCrashReasonString(CrashReason reason); + private: - ProcessMessage(lldb::tid_t tid, Kind kind, int data = 0) - : m_kind(kind), - m_tid(tid), - m_data(data) { } + ProcessMessage(lldb::tid_t tid, Kind kind, + int status = 0, lldb::addr_t addr = 0) + : m_tid(tid), + m_kind(kind), + m_crash_reason(eInvalidCrashReason), + m_status(status), + m_addr(addr) { } - Kind m_kind; lldb::tid_t m_tid; - int m_data; + Kind m_kind : 8; + CrashReason m_crash_reason : 8; + int m_status; + lldb::addr_t m_addr; }; #endif // #ifndef liblldb_ProcessMessage_H_ Modified: lldb/trunk/source/Plugins/Process/Linux/ProcessMonitor.cpp URL: http://llvm.org/viewvc/llvm-project/lldb/trunk/source/Plugins/Process/Linux/ProcessMonitor.cpp?rev=128547&r1=128546&r2=128547&view=diff ============================================================================== --- lldb/trunk/source/Plugins/Process/Linux/ProcessMonitor.cpp (original) +++ lldb/trunk/source/Plugins/Process/Linux/ProcessMonitor.cpp Wed Mar 30 10:55:52 2011 @@ -338,20 +338,26 @@ class ResumeOperation : public Operation { public: - ResumeOperation(lldb::tid_t tid, bool &result) : - m_tid(tid), m_result(result) { } + ResumeOperation(lldb::tid_t tid, uint32_t signo, bool &result) : + m_tid(tid), m_signo(signo), m_result(result) { } void Execute(ProcessMonitor *monitor); private: lldb::tid_t m_tid; + uint32_t m_signo; bool &m_result; }; void ResumeOperation::Execute(ProcessMonitor *monitor) { - if (ptrace(PTRACE_CONT, m_tid, NULL, NULL)) + int data = 0; + + if (m_signo != LLDB_INVALID_SIGNAL_NUMBER) + data = m_signo; + + if (ptrace(PTRACE_CONT, m_tid, NULL, data)) m_result = false; else m_result = true; @@ -363,20 +369,26 @@ class SingleStepOperation : public Operation { public: - SingleStepOperation(lldb::tid_t tid, bool &result) - : m_tid(tid), m_result(result) { } + SingleStepOperation(lldb::tid_t tid, uint32_t signo, bool &result) + : m_tid(tid), m_signo(signo), m_result(result) { } void Execute(ProcessMonitor *monitor); private: lldb::tid_t m_tid; + uint32_t m_signo; bool &m_result; }; void SingleStepOperation::Execute(ProcessMonitor *monitor) { - if (ptrace(PTRACE_SINGLESTEP, m_tid, NULL, NULL)) + int data = 0; + + if (m_signo != LLDB_INVALID_SIGNAL_NUMBER) + data = m_signo; + + if (ptrace(PTRACE_SINGLESTEP, m_tid, NULL, data)) m_result = false; else m_result = true; @@ -457,32 +469,6 @@ m_result = false; else m_result = true; - -#if 0 - // First, stop the inferior process. - if (kill(pid, SIGSTOP)) - { - m_result = false; - return; - } - - // Clear any ptrace options. When PTRACE_O_TRACEEXIT is set, a plain - // PTRACE_KILL (or any termination signal) will not truely terminate the - // inferior process. Instead, the process is left in a state of "limbo" - // allowing us to interrogate its state. However in this case we really do - // want the process gone. - if (ptrace(PTRACE_SETOPTIONS, pid, NULL, 0UL)) - { - m_result = false; - return; - } - - // Kill it. - if (ptrace(PTRACE_KILL, pid, NULL, NULL)) - m_result = false; - else - m_result = true; -#endif } ProcessMonitor::LaunchArgs::LaunchArgs(ProcessMonitor *monitor, @@ -586,12 +572,7 @@ ProcessMonitor::~ProcessMonitor() { - StopMonitoringChildProcess(); - StopOperationThread(); - - close(m_terminal_fd); - close(m_client_fd); - close(m_server_fd); + StopMonitor(); } //------------------------------------------------------------------------------ @@ -768,50 +749,39 @@ ProcessMessage message; ProcessMonitor *monitor = static_cast(callback_baton); ProcessLinux *process = monitor->m_process; + bool stop_monitoring; + siginfo_t info; - switch (signal) - { - case 0: - // No signal. The child has exited normally. - message = ProcessMessage::Exit(pid, status); - break; - - case SIGTRAP: - // Specially handle SIGTRAP and form the appropriate message. - message = MonitorSIGTRAP(monitor, pid); - break; + if (!monitor->GetSignalInfo(pid, &info)) + stop_monitoring = true; // pid is gone. Bail. + else { + switch (info.si_signo) + { + case SIGTRAP: + message = MonitorSIGTRAP(monitor, &info, pid); + break; + + default: + message = MonitorSignal(monitor, &info, pid); + break; + } - default: - // For all other signals simply notify the process instance. Note that - // the process exit status is set when the signal resulted in - // termination. - // - // FIXME: We need a specialized message to inform the process instance - // about "crashes". - if (status) - message = ProcessMessage::Exit(pid, status); - else - message = ProcessMessage::Signal(pid, signal); + process->SendMessage(message); + stop_monitoring = message.GetKind() == ProcessMessage::eExitMessage; } - process->SendMessage(message); - bool stop_monitoring = message.GetKind() == ProcessMessage::eExitMessage; return stop_monitoring; } ProcessMessage -ProcessMonitor::MonitorSIGTRAP(ProcessMonitor *monitor, lldb::pid_t pid) +ProcessMonitor::MonitorSIGTRAP(ProcessMonitor *monitor, + const struct siginfo *info, lldb::pid_t pid) { - siginfo_t info; ProcessMessage message; - bool status; - - status = monitor->GetSignalInfo(pid, &info); - assert(status && "GetSignalInfo failed!"); - assert(info.si_signo == SIGTRAP && "Unexpected child signal!"); + assert(info->si_signo == SIGTRAP && "Unexpected child signal!"); - switch (info.si_code) + switch (info->si_code) { default: assert(false && "Unexpected SIGTRAP code!"); @@ -825,7 +795,7 @@ unsigned long data = 0; if (!monitor->GetEventMessage(pid, &data)) data = -1; - message = ProcessMessage::Exit(pid, (data >> 8)); + message = ProcessMessage::Limbo(pid, (data >> 8)); break; } @@ -843,6 +813,193 @@ return message; } +ProcessMessage +ProcessMonitor::MonitorSignal(ProcessMonitor *monitor, + const struct siginfo *info, lldb::pid_t pid) +{ + ProcessMessage message; + int signo = info->si_signo; + + // POSIX says that process behaviour is undefined after it ignores a SIGFPE, + // SIGILL, SIGSEGV, or SIGBUS *unless* that signal was generated by a + // kill(2) or raise(3). Similarly for tgkill(2) on Linux. + // + // IOW, user generated signals never generate what we consider to be a + // "crash". + // + // Similarly, ACK signals generated by this monitor. + if (info->si_code == SI_TKILL || info->si_code == SI_USER) + { + if (info->si_pid == getpid()) + return ProcessMessage::SignalDelivered(pid, signo); + else + return ProcessMessage::Signal(pid, signo); + } + + if (signo == SIGSEGV) { + lldb::addr_t fault_addr = reinterpret_cast(info->si_addr); + ProcessMessage::CrashReason reason = GetCrashReasonForSIGSEGV(info); + return ProcessMessage::Crash(pid, reason, signo, fault_addr); + } + + if (signo == SIGILL) { + lldb::addr_t fault_addr = reinterpret_cast(info->si_addr); + ProcessMessage::CrashReason reason = GetCrashReasonForSIGILL(info); + return ProcessMessage::Crash(pid, reason, signo, fault_addr); + } + + if (signo == SIGFPE) { + lldb::addr_t fault_addr = reinterpret_cast(info->si_addr); + ProcessMessage::CrashReason reason = GetCrashReasonForSIGFPE(info); + return ProcessMessage::Crash(pid, reason, signo, fault_addr); + } + + if (signo == SIGBUS) { + lldb::addr_t fault_addr = reinterpret_cast(info->si_addr); + ProcessMessage::CrashReason reason = GetCrashReasonForSIGBUS(info); + return ProcessMessage::Crash(pid, reason, signo, fault_addr); + } + + // Everything else is "normal" and does not require any special action on + // our part. + return ProcessMessage::Signal(pid, signo); +} + +ProcessMessage::CrashReason +ProcessMonitor::GetCrashReasonForSIGSEGV(const struct siginfo *info) +{ + ProcessMessage::CrashReason reason; + assert(info->si_signo == SIGSEGV); + + reason = ProcessMessage::eInvalidCrashReason; + + switch (info->si_code) + { + default: + assert(false && "unexpected si_code for SIGSEGV"); + break; + case SEGV_MAPERR: + reason = ProcessMessage::eInvalidAddress; + break; + case SEGV_ACCERR: + reason = ProcessMessage::ePrivilegedAddress; + break; + } + + return reason; +} + +ProcessMessage::CrashReason +ProcessMonitor::GetCrashReasonForSIGILL(const struct siginfo *info) +{ + ProcessMessage::CrashReason reason; + assert(info->si_signo == SIGILL); + + reason = ProcessMessage::eInvalidCrashReason; + + switch (info->si_code) + { + default: + assert(false && "unexpected si_code for SIGILL"); + break; + case ILL_ILLOPC: + reason = ProcessMessage::eIllegalOpcode; + break; + case ILL_ILLOPN: + reason = ProcessMessage::eIllegalOperand; + break; + case ILL_ILLADR: + reason = ProcessMessage::eIllegalAddressingMode; + break; + case ILL_ILLTRP: + reason = ProcessMessage::eIllegalTrap; + break; + case ILL_PRVOPC: + reason = ProcessMessage::ePrivilegedOpcode; + break; + case ILL_PRVREG: + reason = ProcessMessage::ePrivilegedRegister; + break; + case ILL_COPROC: + reason = ProcessMessage::eCoprocessorError; + break; + case ILL_BADSTK: + reason = ProcessMessage::eInternalStackError; + break; + } + + return reason; +} + +ProcessMessage::CrashReason +ProcessMonitor::GetCrashReasonForSIGFPE(const struct siginfo *info) +{ + ProcessMessage::CrashReason reason; + assert(info->si_signo == SIGFPE); + + reason = ProcessMessage::eInvalidCrashReason; + + switch (info->si_code) + { + default: + assert(false && "unexpected si_code for SIGFPE"); + break; + case FPE_INTDIV: + reason = ProcessMessage::eIntegerDivideByZero; + break; + case FPE_INTOVF: + reason = ProcessMessage::eIntegerOverflow; + break; + case FPE_FLTDIV: + reason = ProcessMessage::eFloatDivideByZero; + break; + case FPE_FLTOVF: + reason = ProcessMessage::eFloatOverflow; + break; + case FPE_FLTUND: + reason = ProcessMessage::eFloatUnderflow; + break; + case FPE_FLTRES: + reason = ProcessMessage::eFloatInexactResult; + break; + case FPE_FLTINV: + reason = ProcessMessage::eFloatInvalidOperation; + break; + case FPE_FLTSUB: + reason = ProcessMessage::eFloatSubscriptRange; + break; + } + + return reason; +} + +ProcessMessage::CrashReason +ProcessMonitor::GetCrashReasonForSIGBUS(const struct siginfo *info) +{ + ProcessMessage::CrashReason reason; + assert(info->si_signo == SIGBUS); + + reason = ProcessMessage::eInvalidCrashReason; + + switch (info->si_code) + { + default: + assert(false && "unexpected si_code for SIGBUS"); + break; + case BUS_ADRALN: + reason = ProcessMessage::eIllegalAlignment; + break; + case BUS_ADRERR: + reason = ProcessMessage::eIllegalAddress; + break; + case BUS_OBJERR: + reason = ProcessMessage::eHardwareError; + break; + } + + return reason; +} + void ProcessMonitor::ServeOperation(LaunchArgs *args) { @@ -976,19 +1133,19 @@ } bool -ProcessMonitor::Resume(lldb::tid_t tid) +ProcessMonitor::Resume(lldb::tid_t tid, uint32_t signo) { bool result; - ResumeOperation op(tid, result); + ResumeOperation op(tid, signo, result); DoOperation(&op); return result; } bool -ProcessMonitor::SingleStep(lldb::tid_t tid) +ProcessMonitor::SingleStep(lldb::tid_t tid, uint32_t signo) { bool result; - SingleStepOperation op(tid, result); + SingleStepOperation op(tid, signo, result); DoOperation(&op); return result; } @@ -1021,6 +1178,16 @@ } bool +ProcessMonitor::Detach() +{ + bool result; + KillOperation op(result); + DoOperation(&op); + StopMonitor(); + return result; +} + +bool ProcessMonitor::DupDescriptor(const char *path, int fd, int flags) { int target_fd = open(path, flags); @@ -1043,3 +1210,23 @@ m_monitor_thread = LLDB_INVALID_HOST_THREAD; } } + +void +ProcessMonitor::StopMonitor() +{ + StopMonitoringChildProcess(); + StopOperationThread(); + CloseFD(m_terminal_fd); + CloseFD(m_client_fd); + CloseFD(m_server_fd); +} + +void +ProcessMonitor::CloseFD(int &fd) +{ + if (fd != -1) + { + close(fd); + fd = -1; + } +} Modified: lldb/trunk/source/Plugins/Process/Linux/ProcessMonitor.h URL: http://llvm.org/viewvc/llvm-project/lldb/trunk/source/Plugins/Process/Linux/ProcessMonitor.h?rev=128547&r1=128546&r2=128547&view=diff ============================================================================== --- lldb/trunk/source/Plugins/Process/Linux/ProcessMonitor.h (original) +++ lldb/trunk/source/Plugins/Process/Linux/ProcessMonitor.h Wed Mar 30 10:55:52 2011 @@ -12,6 +12,7 @@ // C Includes #include +#include // C++ Includes // Other libraries and framework includes @@ -127,13 +128,15 @@ bool GetEventMessage(lldb::tid_t tid, unsigned long *message); - /// Resumes the given thread. + /// Resumes the given thread. If @p signo is anything but + /// LLDB_INVALID_SIGNAL_NUMBER, deliver that signal to the thread. bool - Resume(lldb::tid_t tid); + Resume(lldb::tid_t tid, uint32_t signo); - /// Single steps the given thread. + /// Single steps the given thread. If @p signo is anything but + /// LLDB_INVALID_SIGNAL_NUMBER, deliver that signal to the thread. bool - SingleStep(lldb::tid_t tid); + SingleStep(lldb::tid_t tid, uint32_t signo); /// Sends the inferior process a PTRACE_KILL signal. The inferior will /// still exists and can be interrogated. Once resumed it will exit as @@ -141,6 +144,10 @@ bool BringProcessIntoLimbo(); + bool + Detach(); + + private: ProcessLinux *m_process; @@ -207,13 +214,37 @@ lldb::pid_t pid, int signal, int status); static ProcessMessage - MonitorSIGTRAP(ProcessMonitor *monitor, lldb::pid_t pid); + MonitorSIGTRAP(ProcessMonitor *monitor, + const struct siginfo *info, lldb::pid_t pid); + + static ProcessMessage + MonitorSignal(ProcessMonitor *monitor, + const struct siginfo *info, lldb::pid_t pid); + + static ProcessMessage::CrashReason + GetCrashReasonForSIGSEGV(const struct siginfo *info); + + static ProcessMessage::CrashReason + GetCrashReasonForSIGILL(const struct siginfo *info); + + static ProcessMessage::CrashReason + GetCrashReasonForSIGFPE(const struct siginfo *info); + + static ProcessMessage::CrashReason + GetCrashReasonForSIGBUS(const struct siginfo *info); void DoOperation(Operation *op); /// Stops the child monitor thread. - void StopMonitoringChildProcess(); + void + StopMonitoringChildProcess(); + + void + StopMonitor(); + + void + CloseFD(int &fd); }; #endif // #ifndef liblldb_ProcessMonitor_H_ From wilsons at start.ca Wed Mar 30 10:59:12 2011 From: wilsons at start.ca (Stephen Wilson) Date: Wed, 30 Mar 2011 15:59:12 -0000 Subject: [Lldb-commits] [lldb] r128548 - in /lldb/trunk/source/Plugins/ObjectFile/ELF: ELFHeader.cpp ELFHeader.h Message-ID: <20110330155912.500DB2A6C12C@llvm.org> Author: wilsons Date: Wed Mar 30 10:59:12 2011 New Revision: 128548 URL: http://llvm.org/viewvc/llvm-project?rev=128548&view=rev Log: elf: add support for ELF relocation entries Modified: lldb/trunk/source/Plugins/ObjectFile/ELF/ELFHeader.cpp lldb/trunk/source/Plugins/ObjectFile/ELF/ELFHeader.h Modified: lldb/trunk/source/Plugins/ObjectFile/ELF/ELFHeader.cpp URL: http://llvm.org/viewvc/llvm-project/lldb/trunk/source/Plugins/ObjectFile/ELF/ELFHeader.cpp?rev=128548&r1=128547&r2=128548&view=diff ============================================================================== --- lldb/trunk/source/Plugins/ObjectFile/ELF/ELFHeader.cpp (original) +++ lldb/trunk/source/Plugins/ObjectFile/ELF/ELFHeader.cpp Wed Mar 30 10:59:12 2011 @@ -153,6 +153,33 @@ return address_size; } +unsigned +ELFHeader::GetRelocationJumpSlotType() const +{ + unsigned slot = 0; + + switch (e_machine) + { + default: + assert(false && "architecture not supported"); + break; + case EM_386: + case EM_486: + slot = R_386_JUMP_SLOT; + break; + case EM_X86_64: + slot = R_X86_64_JUMP_SLOT; + break; + case EM_ARM: + slot = R_ARM_JUMP_SLOT; + break; + case EM_MBLAZE: + slot = R_MICROBLAZE_JUMP_SLOT; + } + + return slot; +} + //------------------------------------------------------------------------------ // ELFSectionHeader @@ -293,10 +320,54 @@ } bool -ELFDynamic::Parse(const lldb_private::DataExtractor &data, uint32_t *offset) +ELFDynamic::Parse(const lldb_private::DataExtractor &data, uint32_t *offset) { const unsigned byte_size = data.GetAddressByteSize(); return GetMaxS64(data, offset, &d_tag, byte_size, 2); } +//------------------------------------------------------------------------------ +// ELFRel + +ELFRel::ELFRel() +{ + memset(this, 0, sizeof(ELFRel)); +} + +bool +ELFRel::Parse(const lldb_private::DataExtractor &data, uint32_t *offset) +{ + const unsigned byte_size = data.GetAddressByteSize(); + + // Read r_offset and r_info. + if (GetMaxU64(data, offset, &r_offset, byte_size, 2) == false) + return false; + + return true; +} + +//------------------------------------------------------------------------------ +// ELFRela + +ELFRela::ELFRela() +{ + memset(this, 0, sizeof(ELFRela)); +} + +bool +ELFRela::Parse(const lldb_private::DataExtractor &data, uint32_t *offset) +{ + const unsigned byte_size = data.GetAddressByteSize(); + + // Read r_offset and r_info. + if (GetMaxU64(data, offset, &r_offset, byte_size, 2) == false) + return false; + + // Read r_addend; + if (GetMaxS64(data, offset, &r_addend, byte_size) == false) + return false; + + return true; +} + Modified: lldb/trunk/source/Plugins/ObjectFile/ELF/ELFHeader.h URL: http://llvm.org/viewvc/llvm-project/lldb/trunk/source/Plugins/ObjectFile/ELF/ELFHeader.h?rev=128548&r1=128547&r2=128548&view=diff ============================================================================== --- lldb/trunk/source/Plugins/ObjectFile/ELF/ELFHeader.h (original) +++ lldb/trunk/source/Plugins/ObjectFile/ELF/ELFHeader.h Wed Mar 30 10:59:12 2011 @@ -102,6 +102,11 @@ GetByteOrder() const; //-------------------------------------------------------------------------- + /// The jump slot relocation type of this ELF. + unsigned + GetRelocationJumpSlotType() const; + + //-------------------------------------------------------------------------- /// Parse an ELFSectionHeader entry starting at position \p offset and /// update the data extractor with the address size and byte order /// attributes as defined by the header. @@ -290,6 +295,123 @@ Parse(const lldb_private::DataExtractor &data, uint32_t *offset); }; +//------------------------------------------------------------------------------ +/// @class ELFRel +/// @brief Represents a relocation entry with an implicit addend. +struct ELFRel +{ + elf_addr r_offset; ///< Address of reference. + elf_xword r_info; ///< symbol index and type of relocation. + + ELFRel(); + + /// Parse an ELFRel entry from the given DataExtractor starting at position + /// \p offset. The address size of the DataExtractor determines if a 32 or + /// 64 bit object is to be parsed. + /// + /// @param[in] data + /// The DataExtractor to read from. The address size of the extractor + /// determines if a 32 or 64 bit object should be read. + /// + /// @param[in,out] offset + /// Pointer to an offset in the data. On return the offset will be + /// advanced by the number of bytes read. + /// + /// @return + /// True if the ELFRel entry was successfully read and false otherwise. + bool + Parse(const lldb_private::DataExtractor &data, uint32_t *offset); + + /// Returns the type when the given entry represents a 32-bit relocation. + static unsigned + RelocType32(const ELFRel &rel) + { + return rel.r_info & 0x0ff; + } + + /// Returns the type when the given entry represents a 64-bit relocation. + static unsigned + RelocType64(const ELFRel &rel) + { + return rel.r_info & 0xffffffff; + } + + /// Returns the symbol index when the given entry represents a 32-bit + /// reloction. + static unsigned + RelocSymbol32(const ELFRel &rel) + { + return rel.r_info >> 8; + } + + /// Returns the symbol index when the given entry represents a 64-bit + /// reloction. + static unsigned + RelocSymbol64(const ELFRel &rel) + { + return rel.r_info >> 32; + } +}; + +//------------------------------------------------------------------------------ +/// @class ELFRela +/// @brief Represents a relocation entry with an explicit addend. +struct ELFRela +{ + elf_addr r_offset; ///< Address of reference. + elf_xword r_info; ///< Symbol index and type of relocation. + elf_sxword r_addend; ///< Constant part of expression. + + ELFRela(); + + /// Parse an ELFRela entry from the given DataExtractor starting at position + /// \p offset. The address size of the DataExtractor determines if a 32 or + /// 64 bit object is to be parsed. + /// + /// @param[in] data + /// The DataExtractor to read from. The address size of the extractor + /// determines if a 32 or 64 bit object should be read. + /// + /// @param[in,out] offset + /// Pointer to an offset in the data. On return the offset will be + /// advanced by the number of bytes read. + /// + /// @return + /// True if the ELFRela entry was successfully read and false otherwise. + bool + Parse(const lldb_private::DataExtractor &data, uint32_t *offset); + + /// Returns the type when the given entry represents a 32-bit relocation. + static unsigned + RelocType32(const ELFRela &rela) + { + return rela.r_info & 0x0ff; + } + + /// Returns the type when the given entry represents a 64-bit relocation. + static unsigned + RelocType64(const ELFRela &rela) + { + return rela.r_info & 0xffffffff; + } + + /// Returns the symbol index when the given entry represents a 32-bit + /// reloction. + static unsigned + RelocSymbol32(const ELFRela &rela) + { + return rela.r_info >> 8; + } + + /// Returns the symbol index when the given entry represents a 64-bit + /// reloction. + static unsigned + RelocSymbol64(const ELFRela &rela) + { + return rela.r_info >> 32; + } +}; + } // End namespace elf. #endif // #ifndef liblldb_ELFHeader_h_ From ctice at apple.com Wed Mar 30 11:05:24 2011 From: ctice at apple.com (Caroline Tice) Date: Wed, 30 Mar 2011 16:05:24 -0000 Subject: [Lldb-commits] [lldb] r128549 - /lldb/trunk/source/Plugins/Instruction/ARM/EmulateInstructionARM.cpp Message-ID: <20110330160524.1E76D2A6C12C@llvm.org> Author: ctice Date: Wed Mar 30 11:05:23 2011 New Revision: 128549 URL: http://llvm.org/viewvc/llvm-project?rev=128549&view=rev Log: Fix typo in previous check-in. Modified: lldb/trunk/source/Plugins/Instruction/ARM/EmulateInstructionARM.cpp Modified: lldb/trunk/source/Plugins/Instruction/ARM/EmulateInstructionARM.cpp URL: http://llvm.org/viewvc/llvm-project/lldb/trunk/source/Plugins/Instruction/ARM/EmulateInstructionARM.cpp?rev=128549&r1=128548&r2=128549&view=diff ============================================================================== --- lldb/trunk/source/Plugins/Instruction/ARM/EmulateInstructionARM.cpp (original) +++ lldb/trunk/source/Plugins/Instruction/ARM/EmulateInstructionARM.cpp Wed Mar 30 11:05:23 2011 @@ -9771,7 +9771,7 @@ if (t == 15) { - uint32_t pc_value = ReadCoreReg (SP_REG, &success); + uint32_t pc_value = ReadCoreReg (PC_REG, &success); if (!success) return false; From wilsons at start.ca Wed Mar 30 11:07:05 2011 From: wilsons at start.ca (Stephen Wilson) Date: Wed, 30 Mar 2011 16:07:05 -0000 Subject: [Lldb-commits] [lldb] r128550 - in /lldb/trunk/source/Plugins/ObjectFile/ELF: ObjectFileELF.cpp ObjectFileELF.h Message-ID: <20110330160705.913982A6C12C@llvm.org> Author: wilsons Date: Wed Mar 30 11:07:05 2011 New Revision: 128550 URL: http://llvm.org/viewvc/llvm-project?rev=128550&view=rev Log: elf: synthesize symbols for PLT entries When populating symbol tables ObjectFileELF now generates a set of synthetic trampoline symbols. These new symbols correspond to entries in the program linkage table and have a (possibly mangled) name identifying the corresponding symbol in some DSO. These symbols will be used by the DynamicLoader loader plugin on Linux to provide thread plans when execution flows from one DSO to another. Modified: lldb/trunk/source/Plugins/ObjectFile/ELF/ObjectFileELF.cpp lldb/trunk/source/Plugins/ObjectFile/ELF/ObjectFileELF.h Modified: lldb/trunk/source/Plugins/ObjectFile/ELF/ObjectFileELF.cpp URL: http://llvm.org/viewvc/llvm-project/lldb/trunk/source/Plugins/ObjectFile/ELF/ObjectFileELF.cpp?rev=128550&r1=128549&r2=128550&view=diff ============================================================================== --- lldb/trunk/source/Plugins/ObjectFile/ELF/ObjectFileELF.cpp (original) +++ lldb/trunk/source/Plugins/ObjectFile/ELF/ObjectFileELF.cpp Wed Mar 30 11:07:05 2011 @@ -23,6 +23,8 @@ #include "lldb/Symbol/SymbolContext.h" #include "lldb/Host/Host.h" +#include "llvm/ADT/PointerUnion.h" + #define CASE_AND_STREAM(s, def, width) \ case def: s->Printf("%-*s", width, #def); break; @@ -31,6 +33,113 @@ using namespace elf; using namespace llvm::ELF; +namespace { +//===----------------------------------------------------------------------===// +/// @class ELFRelocation +/// @brief Generic wrapper for ELFRel and ELFRela. +/// +/// This helper class allows us to parse both ELFRel and ELFRela relocation +/// entries in a generic manner. +class ELFRelocation +{ +public: + + /// Constructs an ELFRelocation entry with a personality as given by @p + /// type. + /// + /// @param type Either DT_REL or DT_RELA. Any other value is invalid. + ELFRelocation(unsigned type); + + ~ELFRelocation(); + + bool + Parse(const lldb_private::DataExtractor &data, uint32_t *offset); + + static unsigned + RelocType32(const ELFRelocation &rel); + + static unsigned + RelocType64(const ELFRelocation &rel); + + static unsigned + RelocSymbol32(const ELFRelocation &rel); + + static unsigned + RelocSymbol64(const ELFRelocation &rel); + +private: + typedef llvm::PointerUnion RelocUnion; + + RelocUnion reloc; +}; + +ELFRelocation::ELFRelocation(unsigned type) +{ + if (type == DT_REL) + reloc = new ELFRel(); + else if (type == DT_RELA) + reloc = new ELFRela(); + else { + assert(false && "unexpected relocation type"); + reloc = static_cast(NULL); + } +} + +ELFRelocation::~ELFRelocation() +{ + if (reloc.is()) + delete reloc.get(); + else + delete reloc.get(); +} + +bool +ELFRelocation::Parse(const lldb_private::DataExtractor &data, uint32_t *offset) +{ + if (reloc.is()) + return reloc.get()->Parse(data, offset); + else + return reloc.get()->Parse(data, offset); +} + +unsigned +ELFRelocation::RelocType32(const ELFRelocation &rel) +{ + if (rel.reloc.is()) + return ELFRel::RelocType32(*rel.reloc.get()); + else + return ELFRela::RelocType32(*rel.reloc.get()); +} + +unsigned +ELFRelocation::RelocType64(const ELFRelocation &rel) +{ + if (rel.reloc.is()) + return ELFRel::RelocType64(*rel.reloc.get()); + else + return ELFRela::RelocType64(*rel.reloc.get()); +} + +unsigned +ELFRelocation::RelocSymbol32(const ELFRelocation &rel) +{ + if (rel.reloc.is()) + return ELFRel::RelocSymbol32(*rel.reloc.get()); + else + return ELFRela::RelocSymbol32(*rel.reloc.get()); +} + +unsigned +ELFRelocation::RelocSymbol64(const ELFRelocation &rel) +{ + if (rel.reloc.is()) + return ELFRel::RelocSymbol64(*rel.reloc.get()); + else + return ELFRela::RelocSymbol64(*rel.reloc.get()); +} + +} // end anonymous namespace + //------------------------------------------------------------------ // Static methods. //------------------------------------------------------------------ @@ -195,54 +304,54 @@ return num_specs; } -Address -ObjectFileELF::GetImageInfoAddress() +user_id_t +ObjectFileELF::GetSectionIndexByType(unsigned type) { if (!ParseSectionHeaders()) - return Address(); + return 0; - user_id_t dynsym_id = 0; for (SectionHeaderCollIter sh_pos = m_section_headers.begin(); sh_pos != m_section_headers.end(); ++sh_pos) { - if (sh_pos->sh_type == SHT_DYNAMIC) - { - dynsym_id = SectionIndex(sh_pos); - break; - } + if (sh_pos->sh_type == type) + return SectionIndex(sh_pos); } - if (!dynsym_id) + return 0; +} + +Address +ObjectFileELF::GetImageInfoAddress() +{ + if (!ParseDynamicSymbols()) return Address(); SectionList *section_list = GetSectionList(); if (!section_list) return Address(); - // Resolve the dynamic table entries. + user_id_t dynsym_id = GetSectionIndexByType(SHT_DYNAMIC); + if (!dynsym_id) + return Address(); + + const ELFSectionHeader *dynsym_hdr = GetSectionHeaderByIndex(dynsym_id); + if (!dynsym_hdr) + return Address(); + Section *dynsym = section_list->FindSectionByID(dynsym_id).get(); if (!dynsym) return Address(); - - DataExtractor dynsym_data; - if (dynsym->ReadSectionDataFromObjectFile(this, dynsym_data)) + + for (size_t i = 0; i < m_dynamic_symbols.size(); ++i) { - ELFDynamic symbol; - const unsigned section_size = dynsym_data.GetByteSize(); - unsigned offset = 0; - unsigned cursor = 0; + ELFDynamic &symbol = m_dynamic_symbols[i]; - // Look for a DT_DEBUG entry. - while (cursor < section_size) + if (symbol.d_tag == DT_DEBUG) { - offset = cursor; - if (!symbol.Parse(dynsym_data, &cursor)) - break; - - if (symbol.d_tag != DT_DEBUG) - continue; - - return Address(dynsym, offset + sizeof(symbol.d_tag)); + // Compute the offset as the number of previous entries plus the + // size of d_tag. + addr_t offset = i * dynsym_hdr->sh_entsize + GetAddressByteSize(); + return Address(dynsym, offset); } } @@ -476,6 +585,18 @@ return 0; } +const elf::ELFSectionHeader * +ObjectFileELF::GetSectionHeaderByIndex(lldb::user_id_t id) +{ + if (!ParseSectionHeaders() || !id) + return NULL; + + if (--id < m_section_headers.size()) + return &m_section_headers[id]; + + return NULL; +} + SectionList * ObjectFileELF::GetSectionList() { @@ -548,16 +669,18 @@ return m_sections_ap.get(); } -static void -ParseSymbols(Symtab *symtab, SectionList *section_list, - const ELFSectionHeader &symtab_shdr, +static unsigned +ParseSymbols(Symtab *symtab, + user_id_t start_id, + SectionList *section_list, + const ELFSectionHeader *symtab_shdr, const DataExtractor &symtab_data, const DataExtractor &strtab_data) { ELFSymbol symbol; uint32_t offset = 0; - const unsigned numSymbols = - symtab_data.GetByteSize() / symtab_shdr.sh_entsize; + const unsigned num_symbols = + symtab_data.GetByteSize() / symtab_shdr->sh_entsize; static ConstString text_section_name(".text"); static ConstString init_section_name(".init"); @@ -571,7 +694,8 @@ static ConstString data2_section_name(".data1"); static ConstString bss_section_name(".bss"); - for (unsigned i = 0; i < numSymbols; ++i) + unsigned i; + for (i = 0; i < num_symbols; ++i) { if (symbol.Parse(symtab_data, &offset) == false) break; @@ -658,7 +782,7 @@ uint32_t flags = symbol.st_other << 8 | symbol.st_info; Symbol dc_symbol( - i, // ID is the original symbol table index. + i + start_id, // ID is the original symbol table index. symbol_name, // Symbol name. false, // Is the symbol name mangled? symbol_type, // Type of this symbol @@ -672,26 +796,29 @@ flags); // Symbol flags. symtab->AddSymbol(dc_symbol); } + + return i; } -void -ObjectFileELF::ParseSymbolTable(Symtab *symbol_table, - const ELFSectionHeader &symtab_hdr, +unsigned +ObjectFileELF::ParseSymbolTable(Symtab *symbol_table, user_id_t start_id, + const ELFSectionHeader *symtab_hdr, user_id_t symtab_id) { - assert(symtab_hdr.sh_type == SHT_SYMTAB || - symtab_hdr.sh_type == SHT_DYNSYM); + assert(symtab_hdr->sh_type == SHT_SYMTAB || + symtab_hdr->sh_type == SHT_DYNSYM); // Parse in the section list if needed. SectionList *section_list = GetSectionList(); if (!section_list) - return; + return 0; // Section ID's are ones based. - user_id_t strtab_id = symtab_hdr.sh_link + 1; + user_id_t strtab_id = symtab_hdr->sh_link + 1; Section *symtab = section_list->FindSectionByID(symtab_id).get(); Section *strtab = section_list->FindSectionByID(strtab_id).get(); + unsigned num_symbols = 0; if (symtab && strtab) { DataExtractor symtab_data; @@ -699,10 +826,244 @@ if (symtab->ReadSectionDataFromObjectFile(this, symtab_data) && strtab->ReadSectionDataFromObjectFile(this, strtab_data)) { - ParseSymbols(symbol_table, section_list, symtab_hdr, - symtab_data, strtab_data); + num_symbols = ParseSymbols(symbol_table, start_id, + section_list, symtab_hdr, + symtab_data, strtab_data); } } + + return num_symbols; +} + +size_t +ObjectFileELF::ParseDynamicSymbols() +{ + if (m_dynamic_symbols.size()) + return m_dynamic_symbols.size(); + + user_id_t dyn_id = GetSectionIndexByType(SHT_DYNAMIC); + if (!dyn_id) + return NULL; + + SectionList *section_list = GetSectionList(); + if (!section_list) + return NULL; + + Section *dynsym = section_list->FindSectionByID(dyn_id).get(); + if (!dynsym) + return NULL; + + ELFDynamic symbol; + DataExtractor dynsym_data; + if (dynsym->ReadSectionDataFromObjectFile(this, dynsym_data)) + { + + const unsigned section_size = dynsym_data.GetByteSize(); + unsigned offset = 0; + unsigned cursor = 0; + + while (cursor < section_size) + { + offset = cursor; + if (!symbol.Parse(dynsym_data, &cursor)) + break; + + m_dynamic_symbols.push_back(symbol); + } + } + + return m_dynamic_symbols.size(); +} + +const ELFDynamic * +ObjectFileELF::FindDynamicSymbol(unsigned tag) +{ + if (!ParseDynamicSymbols()) + return NULL; + + SectionList *section_list = GetSectionList(); + if (!section_list) + return 0; + + DynamicSymbolCollIter I = m_dynamic_symbols.begin(); + DynamicSymbolCollIter E = m_dynamic_symbols.end(); + for ( ; I != E; ++I) + { + ELFDynamic *symbol = &*I; + + if (symbol->d_tag == tag) + return symbol; + } + + return NULL; +} + +Section * +ObjectFileELF::PLTSection() +{ + const ELFDynamic *symbol = FindDynamicSymbol(DT_JMPREL); + SectionList *section_list = GetSectionList(); + + if (symbol && section_list) + { + addr_t addr = symbol->d_ptr; + return section_list->FindSectionContainingFileAddress(addr).get(); + } + + return NULL; +} + +unsigned +ObjectFileELF::PLTRelocationType() +{ + const ELFDynamic *symbol = FindDynamicSymbol(DT_PLTREL); + + if (symbol) + return symbol->d_val; + + return 0; +} + +static unsigned +ParsePLTRelocations(Symtab *symbol_table, + user_id_t start_id, + unsigned rel_type, + const ELFHeader *hdr, + const ELFSectionHeader *rel_hdr, + const ELFSectionHeader *plt_hdr, + const ELFSectionHeader *sym_hdr, + Section *plt_section, + DataExtractor &rel_data, + DataExtractor &symtab_data, + DataExtractor &strtab_data) +{ + ELFRelocation rel(rel_type); + ELFSymbol symbol; + uint32_t offset = 0; + const unsigned plt_entsize = plt_hdr->sh_entsize; + const unsigned num_relocations = rel_hdr->sh_size / rel_hdr->sh_entsize; + + typedef unsigned (*reloc_info_fn)(const ELFRelocation &rel); + reloc_info_fn reloc_type; + reloc_info_fn reloc_symbol; + + if (hdr->Is32Bit() == 4) + { + reloc_type = ELFRelocation::RelocType32; + reloc_symbol = ELFRelocation::RelocSymbol32; + } + else + { + reloc_type = ELFRelocation::RelocType64; + reloc_symbol = ELFRelocation::RelocSymbol64; + } + + unsigned slot_type = hdr->GetRelocationJumpSlotType(); + unsigned i; + for (i = 0; i < num_relocations; ++i) + { + if (rel.Parse(rel_data, &offset) == false) + break; + + if (reloc_type(rel) != slot_type) + continue; + + unsigned symbol_offset = reloc_symbol(rel) * sym_hdr->sh_entsize; + uint64_t plt_index = (i + 1) * plt_entsize; + + if (!symbol.Parse(symtab_data, &symbol_offset)) + break; + + const char *symbol_name = strtab_data.PeekCStr(symbol.st_name); + + Symbol jump_symbol( + i + start_id, // Symbol table index + symbol_name, // symbol name. + false, // is the symbol name mangled? + eSymbolTypeTrampoline, // Type of this symbol + false, // Is this globally visible? + false, // Is this symbol debug info? + true, // Is this symbol a trampoline? + true, // Is this symbol artificial? + plt_section, // Section in which this symbol is defined or null. + plt_index, // Offset in section or symbol value. + plt_entsize, // Size in bytes of this symbol. + 0); // Symbol flags. + + symbol_table->AddSymbol(jump_symbol); + } + + return i; +} + +unsigned +ObjectFileELF::ParseTrampolineSymbols(Symtab *symbol_table, + user_id_t start_id, + const ELFSectionHeader *rel_hdr, + user_id_t rel_id) +{ + assert(rel_hdr->sh_type == SHT_RELA || rel_hdr->sh_type == SHT_REL); + + // The link field points to the asscoiated symbol table. The info field + // points to the section holding the plt. + user_id_t symtab_id = rel_hdr->sh_link; + user_id_t plt_id = rel_hdr->sh_info; + + if (!symtab_id || !plt_id) + return 0; + + // Section ID's are ones based; + symtab_id++; + plt_id++; + + const ELFSectionHeader *plt_hdr = GetSectionHeaderByIndex(plt_id); + if (!plt_hdr) + return 0; + + const ELFSectionHeader *sym_hdr = GetSectionHeaderByIndex(symtab_id); + if (!sym_hdr) + return 0; + + SectionList *section_list = GetSectionList(); + if (!section_list) + return 0; + + Section *rel_section = section_list->FindSectionByID(rel_id).get(); + if (!rel_section) + return 0; + + Section *plt_section = section_list->FindSectionByID(plt_id).get(); + if (!plt_section) + return 0; + + Section *symtab = section_list->FindSectionByID(symtab_id).get(); + if (!symtab) + return 0; + + Section *strtab = section_list->FindSectionByID(sym_hdr->sh_link + 1).get(); + if (!strtab) + return 0; + + DataExtractor rel_data; + if (!rel_section->ReadSectionDataFromObjectFile(this, rel_data)) + return 0; + + DataExtractor symtab_data; + if (!symtab->ReadSectionDataFromObjectFile(this, symtab_data)) + return 0; + + DataExtractor strtab_data; + if (!strtab->ReadSectionDataFromObjectFile(this, strtab_data)) + return 0; + + unsigned rel_type = PLTRelocationType(); + if (!rel_type) + return 0; + + return ParsePLTRelocations(symbol_table, start_id, rel_type, + &m_header, rel_hdr, plt_hdr, sym_hdr, + plt_section, + rel_data, symtab_data, strtab_data); } Symtab * @@ -714,22 +1075,35 @@ Symtab *symbol_table = new Symtab(this); m_symtab_ap.reset(symbol_table); - Mutex::Locker locker (symbol_table->GetMutex ()); + Mutex::Locker locker(symbol_table->GetMutex()); if (!(ParseSectionHeaders() && GetSectionHeaderStringTable())) return symbol_table; // Locate and parse all linker symbol tables. + uint64_t symbol_id = 0; for (SectionHeaderCollIter I = m_section_headers.begin(); I != m_section_headers.end(); ++I) { if (I->sh_type == SHT_SYMTAB) { - const ELFSectionHeader &symtab_section = *I; + const ELFSectionHeader &symtab_header = *I; user_id_t section_id = SectionIndex(I); - ParseSymbolTable (symbol_table, symtab_section, section_id); + symbol_id += ParseSymbolTable(symbol_table, symbol_id, + &symtab_header, section_id); } } + + // Synthesize trampoline symbols to help navigate the PLT. + Section *reloc_section = PLTSection(); + if (reloc_section) + { + user_id_t reloc_id = reloc_section->GetID(); + const ELFSectionHeader *reloc_header = GetSectionHeaderByIndex(reloc_id); + assert(reloc_header); + + ParseTrampolineSymbols(symbol_table, symbol_id, reloc_header, reloc_id); + } return symbol_table; } Modified: lldb/trunk/source/Plugins/ObjectFile/ELF/ObjectFileELF.h URL: http://llvm.org/viewvc/llvm-project/lldb/trunk/source/Plugins/ObjectFile/ELF/ObjectFileELF.h?rev=128550&r1=128549&r2=128550&view=diff ============================================================================== --- lldb/trunk/source/Plugins/ObjectFile/ELF/ObjectFileELF.h (original) +++ lldb/trunk/source/Plugins/ObjectFile/ELF/ObjectFileELF.h Wed Mar 30 11:07:05 2011 @@ -120,6 +120,10 @@ typedef SectionHeaderColl::iterator SectionHeaderCollIter; typedef SectionHeaderColl::const_iterator SectionHeaderCollConstIter; + typedef std::vector DynamicSymbolColl; + typedef DynamicSymbolColl::iterator DynamicSymbolCollIter; + typedef DynamicSymbolColl::const_iterator DynamicSymbolCollConstIter; + /// Version of this reader common to all plugins based on this class. static const uint32_t m_plugin_version = 1; @@ -132,6 +136,9 @@ /// Collection of section headers. SectionHeaderColl m_section_headers; + /// Collection of symbols from the dynamic table. + DynamicSymbolColl m_dynamic_symbols; + /// List of sections present in this ELF object file. mutable std::auto_ptr m_sections_ap; @@ -147,7 +154,7 @@ /// Cached value of the entry point for this module. lldb_private::Address m_entry_point_address; - + /// Returns a 1 based index of the given section header. unsigned SectionIndex(const SectionHeaderCollIter &I); @@ -175,13 +182,29 @@ size_t ParseDependentModules(); + /// Parses the dynamic symbol table and populates m_dynamic_symbols. The + /// vector retains the order as found in the object file. Returns the + /// number of dynamic symbols parsed. + size_t + ParseDynamicSymbols(); + /// Populates m_symtab_ap will all non-dynamic linker symbols. This method /// will parse the symbols only once. Returns the number of symbols parsed. - void + unsigned ParseSymbolTable(lldb_private::Symtab *symbol_table, - const elf::ELFSectionHeader &symtab_section, + lldb::user_id_t start_id, + const elf::ELFSectionHeader *symtab_section, lldb::user_id_t symtab_id); + /// Scans the relocation entries and adds a set of artificial symbols to the + /// given symbol table for each PLT slot. Returns the number of symbols + /// added. + unsigned + ParseTrampolineSymbols(lldb_private::Symtab *symbol_table, + lldb::user_id_t start_id, + const elf::ELFSectionHeader *rela_hdr, + lldb::user_id_t section_id); + /// Loads the section name string table into m_shstr_data. Returns the /// number of bytes constituting the table. size_t @@ -194,6 +217,14 @@ lldb::user_id_t GetSectionIndexByName(const char *name); + // Returns the ID of the first section that has the given type. + lldb::user_id_t + GetSectionIndexByType(unsigned type); + + /// Returns the section header with the given id or NULL. + const elf::ELFSectionHeader * + GetSectionHeaderByIndex(lldb::user_id_t id); + /// @name ELF header dump routines //@{ static void @@ -246,6 +277,14 @@ void DumpDependentModules(lldb_private::Stream *s); + const elf::ELFDynamic * + FindDynamicSymbol(unsigned tag); + + lldb_private::Section * + PLTSection(); + + unsigned + PLTRelocationType(); }; #endif // #ifndef liblldb_ObjectFileELF_h_ From wilsons at start.ca Wed Mar 30 11:11:36 2011 From: wilsons at start.ca (Stephen Wilson) Date: Wed, 30 Mar 2011 16:11:36 -0000 Subject: [Lldb-commits] [lldb] r128552 - /lldb/trunk/source/Plugins/DynamicLoader/Linux-DYLD/DynamicLoaderLinuxDYLD.cpp Message-ID: <20110330161136.AE8342A6C12C@llvm.org> Author: wilsons Date: Wed Mar 30 11:11:36 2011 New Revision: 128552 URL: http://llvm.org/viewvc/llvm-project?rev=128552&view=rev Log: linux: create thread plans for stepping thru PLT entries Using the new synthetic symbols generated by ObjectFileELF, have the Linux dynamic loader plugin generate a thread plan that will take us thru a PLT entry to the corresponding target function. Modified: lldb/trunk/source/Plugins/DynamicLoader/Linux-DYLD/DynamicLoaderLinuxDYLD.cpp Modified: lldb/trunk/source/Plugins/DynamicLoader/Linux-DYLD/DynamicLoaderLinuxDYLD.cpp URL: http://llvm.org/viewvc/llvm-project/lldb/trunk/source/Plugins/DynamicLoader/Linux-DYLD/DynamicLoaderLinuxDYLD.cpp?rev=128552&r1=128551&r2=128552&view=diff ============================================================================== --- lldb/trunk/source/Plugins/DynamicLoader/Linux-DYLD/DynamicLoaderLinuxDYLD.cpp (original) +++ lldb/trunk/source/Plugins/DynamicLoader/Linux-DYLD/DynamicLoaderLinuxDYLD.cpp Wed Mar 30 11:11:36 2011 @@ -9,13 +9,13 @@ // C Includes // C++ Includes -#include - // Other libraries and framework includes #include "lldb/Core/PluginManager.h" #include "lldb/Core/Log.h" #include "lldb/Target/Process.h" #include "lldb/Target/Target.h" +#include "lldb/Target/Thread.h" +#include "lldb/Target/ThreadPlanRunToAddress.h" #include "AuxVector.h" #include "DynamicLoaderLinuxDYLD.h" @@ -287,14 +287,55 @@ } ThreadPlanSP -DynamicLoaderLinuxDYLD::GetStepThroughTrampolinePlan(Thread &thread, bool stop_others) +DynamicLoaderLinuxDYLD::GetStepThroughTrampolinePlan(Thread &thread, bool stop) { LogSP log(GetLogIfAnyCategoriesSet(LIBLLDB_LOG_DYNAMIC_LOADER)); ThreadPlanSP thread_plan_sp; - if (log) - log->PutCString("DynamicLoaderLinuxDYLD: " - "GetStepThroughTrampolinePlan not implemented\n"); + StackFrame *frame = thread.GetStackFrameAtIndex(0).get(); + const SymbolContext &context = frame->GetSymbolContext(eSymbolContextSymbol); + Symbol *sym = context.symbol; + + if (sym == NULL || !sym->IsTrampoline()) + return thread_plan_sp; + + const ConstString &sym_name = sym->GetMangled().GetName(Mangled::ePreferMangled); + if (!sym_name) + return thread_plan_sp; + + SymbolContextList target_symbols; + Target &target = thread.GetProcess().GetTarget(); + ModuleList &images = target.GetImages(); + + images.FindSymbolsWithNameAndType(sym_name, eSymbolTypeCode, target_symbols); + size_t num_targets = target_symbols.GetSize(); + if (!num_targets) + return thread_plan_sp; + + typedef std::vector AddressVector; + AddressVector addrs; + for (size_t i = 0; i < num_targets; ++i) + { + SymbolContext context; + AddressRange range; + if (target_symbols.GetContextAtIndex(i, context)) + { + context.GetAddressRange(eSymbolContextEverything, range); + lldb::addr_t addr = range.GetBaseAddress().GetLoadAddress(&target); + if (addr != LLDB_INVALID_ADDRESS) + addrs.push_back(addr); + } + } + + if (addrs.size() > 0) + { + AddressVector::iterator start = addrs.begin(); + AddressVector::iterator end = addrs.end(); + + std::sort(start, end); + addrs.erase(std::unique(start, end), end); + thread_plan_sp.reset(new ThreadPlanRunToAddress(thread, addrs, stop)); + } return thread_plan_sp; } From gclayton at apple.com Wed Mar 30 11:51:56 2011 From: gclayton at apple.com (Greg Clayton) Date: Wed, 30 Mar 2011 09:51:56 -0700 Subject: [Lldb-commits] [lldb] r128547 - in /lldb/trunk/source/Plugins/Process/Linux: LinuxSignals.cpp LinuxSignals.h LinuxStopInfo.cpp LinuxStopInfo.h LinuxThread.cpp LinuxThread.h ProcessLinux.cpp ProcessLinux.h ProcessMessage.cpp ProcessMessage.h ProcessMonitor.cpp ProcessMonitor.h In-Reply-To: <20110330155553.3C5272A6C12C@llvm.org> References: <20110330155553.3C5272A6C12C@llvm.org> Message-ID: <65CDF3CD-4212-424E-9689-A455D3801D5C@apple.com> Well done! I am glad to see this works well for Linux. One question: are all of the signals you added actually signals? It looked like it from what I can tell. One of the hacks we did in GDB for mach exceptions was to make up new fake signal numbers because the debugger wanted to deal with signals. One thing I just want to make sure happens in LLDB is that we never have to make up anything. For mach exceptions, we have a StopInfo subclass that is not part of the built in StopInfo stuff: StopInfoMachException. This class takes care of doing all of the special mach things that no other platform really cares about. So if there are things that aren't signals in your recent checkin, you might consider making a StopInfoLinux to take care of any special things that aren't signal related. Greg Clayton On Mar 30, 2011, at 8:55 AM, Stephen Wilson wrote: > Author: wilsons > Date: Wed Mar 30 10:55:52 2011 > New Revision: 128547 > > URL: http://llvm.org/viewvc/llvm-project?rev=128547&view=rev > Log: > > linux: initial support for 'real' signal handling > > This patch upgrades the Linux process plugin to handle a larger range of signal > events. For example, we can detect when the inferior has "crashed" and why, > interrupt a running process, deliver an arbitrary signal, and so on. > > > Added: > lldb/trunk/source/Plugins/Process/Linux/LinuxSignals.cpp > lldb/trunk/source/Plugins/Process/Linux/LinuxSignals.h > lldb/trunk/source/Plugins/Process/Linux/LinuxStopInfo.cpp > lldb/trunk/source/Plugins/Process/Linux/LinuxStopInfo.h > lldb/trunk/source/Plugins/Process/Linux/ProcessMessage.cpp > Modified: > lldb/trunk/source/Plugins/Process/Linux/LinuxThread.cpp > lldb/trunk/source/Plugins/Process/Linux/LinuxThread.h > lldb/trunk/source/Plugins/Process/Linux/ProcessLinux.cpp > lldb/trunk/source/Plugins/Process/Linux/ProcessLinux.h > lldb/trunk/source/Plugins/Process/Linux/ProcessMessage.h > lldb/trunk/source/Plugins/Process/Linux/ProcessMonitor.cpp > lldb/trunk/source/Plugins/Process/Linux/ProcessMonitor.h From ctice at apple.com Wed Mar 30 12:11:45 2011 From: ctice at apple.com (Caroline Tice) Date: Wed, 30 Mar 2011 17:11:45 -0000 Subject: [Lldb-commits] [lldb] r128556 - /lldb/trunk/source/Plugins/Instruction/ARM/EmulateInstructionARM.cpp Message-ID: <20110330171145.A95EA2A6C12C@llvm.org> Author: ctice Date: Wed Mar 30 12:11:45 2011 New Revision: 128556 URL: http://llvm.org/viewvc/llvm-project?rev=128556&view=rev Log: Fill in EmulateLDRLImmediate to emulate the LDRD (immediate) ARM instruction. Modified: lldb/trunk/source/Plugins/Instruction/ARM/EmulateInstructionARM.cpp Modified: lldb/trunk/source/Plugins/Instruction/ARM/EmulateInstructionARM.cpp URL: http://llvm.org/viewvc/llvm-project/lldb/trunk/source/Plugins/Instruction/ARM/EmulateInstructionARM.cpp?rev=128556&r1=128555&r2=128556&view=diff ============================================================================== --- lldb/trunk/source/Plugins/Instruction/ARM/EmulateInstructionARM.cpp (original) +++ lldb/trunk/source/Plugins/Instruction/ARM/EmulateInstructionARM.cpp Wed Mar 30 12:11:45 2011 @@ -129,6 +129,7 @@ #define ARMV4T_ABOVE (ARMv4T|ARMv5T|ARMv5TE|ARMv5TEJ|ARMv6|ARMv6K|ARMv6T2|ARMv7|ARMv8) #define ARMV5_ABOVE (ARMv5T|ARMv5TE|ARMv5TEJ|ARMv6|ARMv6K|ARMv6T2|ARMv7|ARMv8) +#define ARMV5TE_ABOVE (ARMv5TE|ARMv5TEJ|ARMv6|ARMv6K|ARMv6T2|ARMv7|ARMv8) #define ARMV5J_ABOVE (ARMv5TEJ|ARMv6|ARMv6K|ARMv6T2|ARMv7|ARMv8) #define ARMV6_ABOVE (ARMv6|ARMv6K|ARMv6T2|ARMv7|ARMv8) #define ARMV6T2_ABOVE (ARMv6T2|ARMv7|ARMv8) @@ -9342,9 +9343,9 @@ EmulateInstruction::Context context; context.type = eContextAddition; Register reg_n; - reg_n.SetRegister (eRegisterKindDWARF, n); + reg_n.SetRegister (eRegisterKindDWARF, dwarf_r0 +n); Register reg_m; - reg_m.SetRegister (eRegisterKindDWARF, m); + reg_m.SetRegister (eRegisterKindDWARF, dwarf_r0 + m); context.SetRegisterRegisterOperands (reg_n, reg_m); @@ -9471,9 +9472,9 @@ EmulateInstruction::Context context; context.type = eContextSubtraction; Register reg_n; - reg_n.SetRegister (eRegisterKindDWARF, n); + reg_n.SetRegister (eRegisterKindDWARF, dwarf_r0 + n); Register reg_m; - reg_m.SetRegister (eRegisterKindDWARF, m); + reg_m.SetRegister (eRegisterKindDWARF, dwarf_r0 + m); context.SetRegisterRegisterOperands (reg_n, reg_m); if (!WriteCoreRegOptionalFlags (context, res.result, dwarf_r0 + d, setflags, res.carry_out, res.overflow)) @@ -9667,9 +9668,9 @@ return false; Register base_reg; - base_reg.SetRegister (eRegisterKindDWARF, n); + base_reg.SetRegister (eRegisterKindDWARF, dwarf_r0 + n); Register data_reg; - data_reg.SetRegister (eRegisterKindDWARF, t); + data_reg.SetRegister (eRegisterKindDWARF, dwarf_r0 + t); EmulateInstruction::Context context; context.type = eContextRegisterStore; context.SetRegisterToRegisterPlusOffset (data_reg, base_reg, address - Rn); @@ -9757,9 +9758,9 @@ address = Rn; Register base_reg; - base_reg.SetRegister (eRegisterKindDWARF, n); + base_reg.SetRegister (eRegisterKindDWARF, dwarf_r0 + n); Register data_reg; - data_reg.SetRegister (eRegisterKindDWARF, t); + data_reg.SetRegister (eRegisterKindDWARF, dwarf_r0 + t); EmulateInstruction::Context context; context.type = eContextRegisterStore; context.SetRegisterToRegisterPlusOffset (data_reg, base_reg, address - Rn); @@ -9891,18 +9892,143 @@ // A8.6.66 LDRD (immediate) +// Load Register Dual (immediate) calculates an address from a base register value and an immediate offset, loads two +// words from memory, and writes them to two registers. It can use offset, post-indexed, or pre-indexed addressing. bool EmulateInstructionARM::EmulateLDRDImmediate (const uint32_t opcode, const ARMEncoding encoding) { #if 0 + if ConditionPassed() then + EncodingSpecificOperations(); NullCheckIfThumbEE(n); + offset_addr = if add then (R[n] + imm32) else (R[n] - imm32); + address = if index then offset_addr else R[n]; + R[t] = MemA[address,4]; + R[t2] = MemA[address+4,4]; + if wback then R[n] = offset_addr; #endif - //bool success = false; + bool success = false; if (ConditionPassed(opcode)) { + uint32_t t; + uint32_t t2; + uint32_t n; + uint32_t imm32; + bool index; + bool add; + bool wback; + switch (encoding) { + case eEncodingT1: + //if P == ???0??? && W == ???0??? then SEE ???Related encodings???; + //if Rn == ???1111??? then SEE LDRD (literal); + //t = UInt(Rt); t2 = UInt(Rt2); n = UInt(Rn); imm32 = ZeroExtend(imm8:???00???, 32); + t = Bits32 (opcode, 15, 12); + t2 = Bits32 (opcode, 11, 8); + n = Bits32 (opcode, 19, 16); + imm32 = Bits32 (opcode, 7, 0) << 2; + + //index = (P == ???1???); add = (U == ???1???); wback = (W == ???1???); + index = BitIsSet (opcode, 24); + add = BitIsSet (opcode, 23); + wback = BitIsSet (opcode, 21); + + //if wback && (n == t || n == t2) then UNPREDICTABLE; + if (wback && ((n == t) || (n == t2))) + return false; + + //if BadReg(t) || BadReg(t2) || t == t2 then UNPREDICTABLE; + if (BadReg (t) || BadReg (t2) || (t == t2)) + return false; + + break; + + case eEncodingA1: + //if Rn == ???1111??? then SEE LDRD (literal); + //if Rt<0> == ???1??? then UNPREDICTABLE; + //t = UInt(Rt); t2 = t+1; n = UInt(Rn); imm32 = ZeroExtend(imm4H:imm4L, 32); + t = Bits32 (opcode, 15, 12); + t2 = t + 1; + n = Bits32 (opcode, 19, 16); + imm32 = (Bits32 (opcode, 11, 8) << 4) | Bits32 (opcode, 3, 0); + + //index = (P == ???1???); add = (U == ???1???); wback = (P == ???0???) || (W == ???1???); + index = BitIsSet (opcode, 24); + add = BitIsSet (opcode, 23); + wback = BitIsClear (opcode, 24) || BitIsSet (opcode, 21); + + //if P == ???0??? && W == ???1??? then UNPREDICTABLE; + if (BitIsClear (opcode, 24) && BitIsSet (opcode, 21)) + return false; + + //if wback && (n == t || n == t2) then UNPREDICTABLE; + if (wback && ((n == t) || (n == t2))) + return false; + + //if t2 == 15 then UNPREDICTABLE; + if (t2 == 15) + return false; + + break; + + default: + return false; + } + + //offset_addr = if add then (R[n] + imm32) else (R[n] - imm32); + uint32_t Rn = ReadCoreReg (n, &success); + if (!success) + return false; + + addr_t offset_addr; + if (add) + offset_addr = Rn + imm32; + else + offset_addr = Rn - imm32; + + //address = if index then offset_addr else R[n]; + addr_t address; + if (index) + address = offset_addr; + else + address = Rn; + + //R[t] = MemA[address,4]; + Register base_reg; + base_reg.SetRegister (eRegisterKindDWARF, dwarf_r0 + n); + + EmulateInstruction::Context context; + context.type = eContextRegisterLoad; + context.SetRegisterPlusOffset (base_reg, address - Rn); + + const uint32_t addr_byte_size = GetAddressByteSize(); + uint32_t data = MemARead (context, address, addr_byte_size, 0, &success); + if (!success) + return false; + + if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_r0 + t, data)) + return false; + + //R[t2] = MemA[address+4,4]; + + context.SetRegisterPlusOffset (base_reg, (address + 4) - Rn); + data = MemARead (context, address + 4, addr_byte_size, 0, &success); + if (!success) + return false; + + if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_r0 + t2, data)) + return false; + + //if wback then R[n] = offset_addr; + if (wback) + { + context.type = eContextAdjustBaseRegister; + context.SetAddress (offset_addr); + + if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_r0 + n, offset_addr)) + return false; } } return true; @@ -10471,6 +10597,7 @@ { 0x0e5000f0, 0x005000f0, ARMvAll, eEncodingA1, eSize32, &EmulateInstructionARM::EmulateLDRSHImmediate, "ldrsh ,[{,#+/-}]"}, { 0x0e5f00f0, 0x005f00f0, ARMvAll, eEncodingA1, eSize32, &EmulateInstructionARM::EmulateLDRSHLiteral, "ldrsh ,