From lattner at cs.uiuc.edu Mon Nov 11 13:38:01 2002 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Mon Nov 11 13:38:01 2002 Subject: [llvm-commits] CVS: llvm/lib/Target/X86/InstSelectSimple.cpp X86InstrInfo.def Message-ID: <200211111937.NAA29265@psmith.cs.uiuc.edu> Changes in directory llvm/lib/Target/X86: InstSelectSimple.cpp updated: 1.22 -> 1.23 X86InstrInfo.def updated: 1.13 -> 1.14 --- Log message: InstSelectSimple.cpp: (visitReturnInst) Add return instructions with return values. X86InstrInfo.def: add LEAVE instruction. --- Diffs of the changes: Index: llvm/lib/Target/X86/InstSelectSimple.cpp diff -u llvm/lib/Target/X86/InstSelectSimple.cpp:1.22 llvm/lib/Target/X86/InstSelectSimple.cpp:1.23 --- llvm/lib/Target/X86/InstSelectSimple.cpp:1.22 Thu Nov 7 11:59:21 2002 +++ llvm/lib/Target/X86/InstSelectSimple.cpp Mon Nov 11 13:37:09 2002 @@ -326,15 +326,70 @@ /// ret long, ulong : Move value into EAX/EDX (?) and return /// ret float/double : ? Top of FP stack? XMM0? /// -void ISel::visitReturnInst(ReturnInst &I) { - if (I.getNumOperands() != 0) { // Not 'ret void'? - // Move result into a hard register... then emit a ret - visitInstruction(I); // abort - } - - // Emit a simple 'ret' instruction... appending it to the end of the basic - // block - BuildMI(BB, X86::RET, 0); +void +ISel::visitReturnInst (ReturnInst & I) +{ + if (I.getNumOperands () == 1) + { + unsigned val = getReg (I.getOperand (0)); + unsigned operandSize = + I.getOperand (0)->getType ()->getPrimitiveSize (); + bool isFP = I.getOperand (0)->getType ()->isFloatingPoint (); + if (isFP) + { + // ret float/double: top of FP stack + // FLD + switch (operandSize) + { + case 4: + BuildMI (BB, X86::FLDr4, 1, X86::NoReg).addReg (val); + break; + case 8: + BuildMI (BB, X86::FLDr8, 1, X86::NoReg).addReg (val); + break; + default: + visitInstruction (I); + break; + } + } + else + { + switch (operandSize) + { + case 1: + // ret sbyte, ubyte: Extend value into EAX and return + // MOV AL, + // CBW + BuildMI (BB, X86::MOVrr8, 1, X86::AL).addReg (val); + BuildMI (BB, X86::CBW, 0); + break; + case 2: + // ret short, ushort: Extend value into EAX and return + // MOV AX, + // CWDE + BuildMI (BB, X86::MOVrr16, 1, X86::AX).addReg (val); + BuildMI (BB, X86::CWDE, 0); + break; + case 4: + // ret int, uint, ptr: Move value into EAX and return + // MOV EAX, + BuildMI (BB, X86::MOVrr32, 1, X86::EAX).addReg (val); + break; + case 8: + // ret long: use EAX(least significant 32 bits)/EDX (most + // significant 32)...uh, I think so Brain, but how do i call + // up the two parts of the value from inside this mouse + // cage? *zort* + default: + // abort + visitInstruction (I); + break; + } + } + } + // Emit a 'leave' and a 'ret' + BuildMI (BB, X86::LEAVE, 0); + BuildMI (BB, X86::RET, 0); } /// visitBranchInst - Handle conditional and unconditional branches here. Note Index: llvm/lib/Target/X86/X86InstrInfo.def diff -u llvm/lib/Target/X86/X86InstrInfo.def:1.13 llvm/lib/Target/X86/X86InstrInfo.def:1.14 --- llvm/lib/Target/X86/X86InstrInfo.def:1.13 Thu Nov 7 11:59:21 2002 +++ llvm/lib/Target/X86/X86InstrInfo.def Mon Nov 11 13:37:09 2002 @@ -44,6 +44,7 @@ I(MOVir8 , "movb", 0, 0) // R8 = imm8 B0+ rb I(MOVir16 , "movw", 0, 0) // R16 = imm16 B8+ rw I(MOVir32 , "movl", 0, 0) // R32 = imm32 B8+ rd +I(LEAVE , "leave", 0, 0) // leave C9 // Arithmetic instructions I(ADDrr8 , "addb", 0, 0) // R8 += R8 00/r From lattner at cs.uiuc.edu Mon Nov 11 14:49:01 2002 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Mon Nov 11 14:49:01 2002 Subject: [llvm-commits] CVS: llvm/www/docs/DSGraphStatus.html Message-ID: <200211112048.OAA21146@tank.cs.uiuc.edu> Changes in directory llvm/www/docs: DSGraphStatus.html updated: 1.10 -> 1.11 --- Log message: More numbers --- Diffs of the changes: Index: llvm/www/docs/DSGraphStatus.html diff -u llvm/www/docs/DSGraphStatus.html:1.10 llvm/www/docs/DSGraphStatus.html:1.11 --- llvm/www/docs/DSGraphStatus.html:1.10 Sun Nov 10 01:31:38 2002 +++ llvm/www/docs/DSGraphStatus.html Mon Nov 11 14:48:45 2002 @@ -13,6 +13,125 @@ previous value.

+

Nov 11, 2002:

+ +This is the first successful run of all of the benchmarks! This is still +compiled in debug mode, still has lots of tweaks and minor improvements that +could be made, lots of optimizations even, but they will have to wait for a +bit.

+ +Also note that we now include time taken the parse the bytecode file into LLVM +IR, and the space used by the LLVM IR.

+ +

+Name:                     Anlyz: LocTime: BUTime:  TDTime:  TotTime: BCTime:      LocSize: BUSize:  TDSize:  TotSize: BCSize:    NumFold  NumNodes   main   __main GlobGr
+255.vortex.lib             24.44 0.5896   2.7741   11.5906  16.5760  2.3257   |   1381816  1338688  14822760 17543264 11691568 |    7288  7321+3135  166+11 0+0    0+0    
+254.gap.lib                19.51 0.8708   4.6071   3.5835   10.6354  2.9075   |   2024600  3155592  2323136  7503328  16555920 |    6934  24027+3950 44+9   0+0    0+0    
+300.twolf.lib               3.38 0.2753   0.2930   0.5233   1.5807   0.9966   |   466248   392352   398296   1256896  6936800  |    765   4129+784   91+53  0+0    0+0    
+197.parser.lib              1.89 0.1478   0.3243   0.2178   0.8755   0.6667   |   408560   224928   213736   966696   4451256  |    1350  2259+711   14+6   0+0    0+0    
+burg.llvm.lib               1.23 0.1039   0.1877   0.1779   0.5589   0.4972   |   530224   471200   183504   1184928  3039960  |    790   2239+575   42+7   0+0    0+0    
+164.gzip.llvm.lib           0.71 0.0408   0.0578   0.0332   0.1965   0.4323   |   201664   128768   70864    498912   1870880  |    24    971+87     8+2    0+0    0+0    
+optimizer-eval.llvm.lib     0.51 0.0166   0.0480   0.2086   0.3041   0.1716   |   81584    78352    60304    238616   620296   |    *     309+41     72+27  0+0    0+0    
+256.bzip2.lib               0.33 0.0240   0.0383   0.0114   0.1214   0.1565   |   139536   84224    39704    335680   1370784  |    *     563+37     8+2    0+0    0+0    
+181.mcf.lib                 0.22 0.0184   0.0286   0.0287   0.0959   0.0874   |   111384   145792   43360    317776   589808   |    156   393+51     23+10  0+0    0+0    
+sim.llvm.lib                0.20 0.0136   0.0137   0.0130   0.0792   0.0848   |   55376    81000    21960    253344   721520   |    *     261+36     39+22  0+0    0+0    
+voronoi.llvm.lib            0.17 0.0135   0.0262   0.0289   0.0833   0.0553   |   79696    87968    27128    208568   419920   |    18    299+77     15+8   0+0    0+0    
+bh.llvm.lib                 0.16 0.0116   0.0164   0.0118   0.0590   0.0665   |   55864    71416    27432    219376   473840   |    61    194+35     6+2    0+0    0+0    
+sgefa.llvm.lib              0.15 0.0089   0.0222   0.0246   0.0720   0.0530   |   85904    82240    67064    260872   364520   |    *     130+24     24+14  0+0    0+0    
+health.llvm.lib             0.10 0.0050   0.0096   0.0055   0.0275   0.0450   |   29880    27920    7608     73008    199064   |    71    79+29      10+4   0+0    0+0    
+tsp.llvm.lib                0.08 0.0049   0.0072   0.0027   0.0224   0.0350   |   25704    14472    4872     52216    176600   |    21    42+15      7+4    0+0    0+0    
+power.llvm.lib              0.08 0.0041   0.0067   0.0037   0.0222   0.0361   |   28512    17760    7848     61960    214128   |    *     81+18      11+2   0+0    0+0    
+em3d.llvm.lib               0.08 0.0060   0.0113   0.0055   0.0312   0.0315   |   24280    32960    12536    86576    224616   |    13    172+25     12+4   0+0    0+0    
+perimeter.llvm.lib          0.07 0.0031   0.0069   0.0020   0.0196   0.0261   |   14936    14112    3928     45592    155208   |    *     35+15      7+4    0+0    0+0    
+mst.llvm.lib                0.07 0.0039   0.0067   0.0037   0.0216   0.0285   |   27408    16752    7040     66048    178328   |    10    97+15      12+3   0+0    0+0    
+lists.llvm.lib              0.07 0.0043   0.0128   0.0072   0.0299   0.0276   |   24544    16912    14440    68008    141480   |    30    67+26      3+1    0+0    0+0    
+hash.llvm.lib               0.06 0.0030   0.0051   0.0054   0.0202   0.0186   |   17936    24808    8216     64232    153552   |    *     117+17     14+6   0+0    0+0    
+methcall.llvm.lib           0.05 0.0017   0.0047   0.0029   0.0142   0.0174   |   10984    9856     9144     44000    87328    |    30    43+12      14+8   0+0    0+0    
+objinst.llvm.lib            0.04 0.0019   0.0042   0.0033   0.0147   0.0114   |   11072    15328    10536    50496    87064    |    34    45+14      16+10  0+0    0+0    
+matrix.llvm.lib             0.04 0.0012   0.0021   0.0016   0.0094   0.0164   |   8720     8784     3048     36600    68048    |    *     38+9       12+8   0+0    0+0    
+llubenchmark.llvm.lib       0.04 0.0021   0.0027   0.0014   0.0130   0.0117   |   4728     9368     2608     33440    122712   |    *     31+7       15+5   0+0    0+0    
+bisort.llvm.lib             0.04 0.0029   0.0056   0.0019   0.0160   0.0125   |   13608    11744    3712     45984    126584   |    *     35+13      7+4    0+0    0+0    
+ary3.llvm.lib               0.04 0.0012   0.0020   0.0011   0.0088   0.0138   |   8648     19856    2976     43080    73064    |    6     44+5       12+3   0+0    0+0    
+ackermann.llvm.lib          0.04 0.0007   0.0017   0.0004   0.0058   0.0226   |   1744     5728     1200     22056    46448    |    *     13+2       3+1    0+0    0+0    
+treeadd.llvm.lib            0.03 0.0014   0.0029   0.0009   0.0090   0.0077   |   3856     7384     2200     29784    72064    |    *     25+7       6+3    0+0    0+0    
+sumarraymalloc.llvm.lib     0.03 0.0009   0.0017   0.0009   0.0069   0.0100   |   7040     2672     2048     25872    54352    |    *     23+5       7+4    0+0    0+0    
+sieve.llvm.lib              0.03 0.0007   0.0012   0.0005   0.0060   0.0138   |   2176     6176     1632     23432    216840   |    *     22+2       12+1   0+0    0+0    
+random.llvm.lib             0.03 0.0008   0.0018   0.0004   0.0060   0.0137   |   2056     5720     1320     22080    45264    |    *     15+2       3+1    0+0    0+0    
+matrixTranspose.llvm.lib    0.03 0.0005   0.0010   0.0003   0.0033   0.0151   |   4248     1144     736      8520     68104    |    *     8+1        5+1    0+0    0+0    
+hello.llvm.lib              0.03 0.0004   0.0018   0.0001   0.0064   0.0105   |   752      2952     472      6512     12264    |    *     2+0        0+0    0+0    0+0    
+heapsort.llvm.lib           0.03 0.0009   0.0020   0.0007   0.0074   0.0080   |   7448     7224     1992     28032    62704    |    *     26+3       7+2    0+0    0+0    
+sumarray2d.llvm.lib         0.02 0.0005   0.0009   0.0002   0.0033   0.0030   |   4208     856      3656     10904    21968    |    *     10+1       7+1    0+0    0+0    
+printargs.llvm.lib          0.02 0.0004   0.0014   0.0002   0.0033   0.0061   |   1240     1048     696      5128     19160    |    *     6+1        4+1    0+0    0+0    
+pi.llvm.lib                 0.02 0.0007   0.0019   0.0004   0.0050   0.0037   |   5392     1560     1392     8344     36032    |    *     17+2       13+2   0+0    0+0    
+indvars.llvm.lib            0.02 0.0011   0.0010   0.0003   0.0043   0.0035   |   1744     4088     1024     9696     31336    |    *     13+1       8+1    0+0    0+0    
+fib2.llvm.lib               0.02 0.0008   0.0015   0.0007   0.0061   0.0050   |   2416     10376    1648     30088    43792    |    *     21+5       8+3    0+0    0+0    
+sumarray.llvm.lib           0.01 0.0003   0.0009   0.0002   0.0027   0.0022   |   904      3192     624      4720     15152    |    *     6+1        4+1    0+0    0+0    
+

+ + + +

+

Nov 10, 2002:

+ +This data set has the prototype Tarjan SCC code in to help with cases that were +causing exponential behavior. This gets Gap working, but Vortex is still either +infinite looping or really slow. I'm almost certain there are a couple of bugs +still remaining in the implementation, so these should be regarded as +preliminary numbers.

+ +Here is some trivia for you: Vortex contains a SCC with 38 nodes, and another +with 19. Gap contains SCCs of size 2, 2, 20, 6, 2.

+ +Also note that the bytecode file for GAP is 3x the size of the bytecode file for +twolf.

+ +

+Name:                     Anlyz: LocTime: BUTime:  TDTime:  TotTime: BCTime:      LocSize: BUSize:  TDSize:  TotSize: BCSize:    NumFold  NumNodes   main   __main GlobGr
+255.vortex.lib              7.56 *        *        *        *        *        |   *        *        *        *        *        |    *     *          *      *      *      
+254.gap.lib                22.53 0.8908   7.0430   3.2424   12.8506  3.1879   |   2024600  5229888  3882656  11137144 16555920 |    6959  42275+3949 59+9   0+0    0+0    
+300.twolf.lib               3.92 0.3259   0.3470   0.8163   2.0253   1.0287   |   466248   405936   456456   1328640  6936800  |    821   4119+784   90+53  0+0    0+0    
+197.parser.lib              2.23 0.1939   0.4020   0.2499   1.0864   0.7768   |   408560   229568   220672   978272   4451256  |    1362  2272+704   16+6   0+0    0+0    
+burg.llvm.lib               1.28 0.1085   0.1942   0.1954   0.5911   0.5072   |   530224   477440   290376   1298040  3039960  |    796   2248+575   39+7   0+0    0+0    
+164.gzip.llvm.lib           0.67 0.0392   0.0506   0.0326   0.1873   0.4044   |   201664   130312   72000    501592   1870880  |    24    988+87     12+2   0+0    0+0    
+optimizer-eval.llvm.lib     0.43 0.0172   0.0570   0.2122   0.3200   0.0725   |   81584    78640    60384    238984   620296   |    *     299+41     62+27  0+0    0+0    
+256.bzip2.lib               0.34 0.0250   0.0374   0.0117   0.1242   0.1508   |   139536   84856    40208    336816   1370784  |    *     569+37     12+2   0+0    0+0    
+181.mcf.lib                 0.23 0.0304   0.0296   0.0438   0.1255   0.0685   |   111384   145928   38568    313120   589808   |    161   384+51     27+10  0+0    0+0    
+sim.llvm.lib                0.22 0.0138   0.0162   0.0146   0.0850   0.0891   |   55376    81680    21784    253848   721520   |    *     259+36     37+22  0+0    0+0    
+voronoi.llvm.lib            0.20 0.0140   0.0311   0.0293   0.0962   0.0547   |   79696    85176    27272    205920   419920   |    18    294+76     17+8   0+0    0+0    
+sgefa.llvm.lib              0.17 0.0088   0.0250   0.0223   0.0730   0.0615   |   85904    82240    67064    260872   364520   |    *     130+24     24+14  0+0    0+0    
+bh.llvm.lib                 0.15 0.0120   0.0173   0.0126   0.0614   0.0548   |   55864    71416    27432    219376   473840   |    61    194+35     6+2    0+0    0+0    
+em3d.llvm.lib               0.09 0.0066   0.0111   0.0088   0.0350   0.0284   |   24280    32960    12536    86576    224616   |    13    172+25     12+4   0+0    0+0    
+health.llvm.lib             0.08 0.0052   0.0098   0.0062   0.0287   0.0330   |   29880    27920    7608     73008    199064   |    71    79+29      10+4   0+0    0+0    
+mst.llvm.lib                0.07 0.0048   0.0068   0.0056   0.0266   0.0218   |   27408    16752    7040     66048    178328   |    10    97+15      12+3   0+0    0+0    
+tsp.llvm.lib                0.06 0.0049   0.0069   0.0026   0.0222   0.0212   |   25704    14472    4872     52216    176600   |    21    42+15      7+4    0+0    0+0    
+power.llvm.lib              0.06 0.0042   0.0065   0.0036   0.0217   0.0214   |   28512    17760    7848     61960    214128   |    *     81+18      11+2   0+0    0+0    
+lists.llvm.lib              0.06 0.0042   0.0113   0.0071   0.0293   0.0146   |   24544    16912    14440    68008    141480   |    30    67+26      3+1    0+0    0+0    
+perimeter.llvm.lib          0.05 0.0030   0.0058   0.0020   0.0186   0.0161   |   14936    14112    3928     45592    155208   |    *     35+15      7+4    0+0    0+0    
+methcall.llvm.lib           0.05 0.0017   0.0042   0.0028   0.0137   0.0099   |   10984    9856     9144     44000    87328    |    30    43+12      14+8   0+0    0+0    
+hash.llvm.lib               0.05 0.0031   0.0050   0.0039   0.0187   0.0163   |   17936    24808    8216     64232    153552   |    *     117+17     14+6   0+0    0+0    
+bisort.llvm.lib             0.05 0.0048   0.0053   0.0018   0.0188   0.0125   |   13608    11744    3712     45984    126584   |    *     35+13      7+4    0+0    0+0    
+objinst.llvm.lib            0.04 0.0018   0.0044   0.0032   0.0163   0.0103   |   11072    15328    10536    50496    87064    |    34    45+14      16+10  0+0    0+0    
+llubenchmark.llvm.lib       0.04 0.0021   0.0022   0.0014   0.0125   0.0124   |   4728     9520     2624     33608    122712   |    *     31+7       15+5   0+0    0+0    
+treeadd.llvm.lib            0.03 0.0015   0.0024   0.0009   0.0085   0.0077   |   3856     7384     2200     29784    72064    |    *     25+7       6+3    0+0    0+0    
+sumarraymalloc.llvm.lib     0.03 0.0009   0.0035   0.0009   0.0088   0.0058   |   7040     2672     2048     25872    54352    |    *     23+5       7+4    0+0    0+0    
+sieve.llvm.lib              0.03 0.0007   0.0011   0.0005   0.0060   0.0144   |   2176     6176     1632     23432    216840   |    *     22+2       12+1   0+0    0+0    
+random.llvm.lib             0.03 0.0008   0.0016   0.0004   0.0063   0.0050   |   2056     5720     1320     22080    45264    |    *     15+2       3+1    0+0    0+0    
+matrix.llvm.lib             0.03 0.0012   0.0021   0.0014   0.0093   0.0081   |   8720     8784     3048     36600    68048    |    *     38+9       12+8   0+0    0+0    
+heapsort.llvm.lib           0.03 0.0010   0.0018   0.0006   0.0084   0.0064   |   7448     7224     1992     28032    62704    |    *     26+3       7+2    0+0    0+0    
+fib2.llvm.lib               0.03 0.0008   0.0016   0.0007   0.0063   0.0048   |   2416     10376    1648     30088    43792    |    *     21+5       8+3    0+0    0+0    
+ary3.llvm.lib               0.03 0.0012   0.0019   0.0011   0.0086   0.0073   |   8648     19856    2976     43080    73064    |    6     44+5       12+3   0+0    0+0    
+sumarray2d.llvm.lib         0.02 0.0004   0.0008   0.0003   0.0031   0.0029   |   4208     856      3656     10904    21968    |    *     10+1       7+1    0+0    0+0    
+printargs.llvm.lib          0.02 0.0005   0.0012   0.0002   0.0031   0.0024   |   1240     1048     696      5128     19160    |    *     6+1        4+1    0+0    0+0    
+pi.llvm.lib                 0.02 0.0007   0.0015   0.0004   0.0050   0.0035   |   5392     1560     1392     8344     36032    |    *     17+2       13+2   0+0    0+0    
+matrixTranspose.llvm.lib    0.02 0.0006   0.0011   0.0003   0.0036   0.0051   |   4248     1144     736      8520     68104    |    *     8+1        5+1    0+0    0+0    
+indvars.llvm.lib            0.02 0.0005   0.0009   0.0003   0.0035   0.0037   |   1744     4088     1024     9696     31336    |    *     13+1       8+1    0+0    0+0    
+ackermann.llvm.lib          0.02 0.0008   0.0014   0.0004   0.0056   0.0060   |   1744     5728     1200     22056    46448    |    *     13+2       3+1    0+0    0+0    
+sumarray.llvm.lib           0.01 0.0014   0.0008   0.0002   0.0036   0.0021   |   904      3192     624      4720     15152    |    *     6+1        4+1    0+0    0+0    
+hello.llvm.lib              0.01 0.0004   0.0015   0.0001   0.0028   0.0019   |   752      2952     472      6512     12264    |    *     2+0        0+0    0+0    0+0    
+

+ + +

Nov 9, 2002 #2:

This has the first part of the globals graph implemented, this simply deletes @@ -470,7 +589,7 @@
Chris Lattner
-Last modified: Sun Nov 10 01:26:16 CST 2002 +Last modified: Mon Nov 11 14:48:26 CST 2002 From lattner at cs.uiuc.edu Mon Nov 11 15:35:01 2002 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Mon Nov 11 15:35:01 2002 Subject: [llvm-commits] CVS: llvm/include/llvm/Analysis/DataStructure.h Message-ID: <200211112134.PAA08627@apoc.cs.uiuc.edu> Changes in directory llvm/include/llvm/Analysis: DataStructure.h updated: 1.57 -> 1.58 --- Log message: Almost complete rewrite of BU closure code --- Diffs of the changes: Index: llvm/include/llvm/Analysis/DataStructure.h diff -u llvm/include/llvm/Analysis/DataStructure.h:1.57 llvm/include/llvm/Analysis/DataStructure.h:1.58 --- llvm/include/llvm/Analysis/DataStructure.h:1.57 Sun Nov 10 17:47:02 2002 +++ llvm/include/llvm/Analysis/DataStructure.h Mon Nov 11 15:34:34 2002 @@ -102,10 +102,24 @@ AU.addRequired(); } private: - DSGraph &calculateGraph(Function &F, unsigned Indent); + DSGraph &calculateGraph(Function &F); + DSGraph &calculateSCCGraph(Function &F, + std::set &InlinedSCCFunctions); + void calculateReachableGraphs(Function *F); + + + DSGraph &getOrCreateGraph(Function *F); + + unsigned calculateGraphs(Function *F, std::vector &Stack, + unsigned &NextID, + std::map &ValMap); + + + /* bool ResolveFunctionCalls(DSGraph &G, unsigned &FirstResolvableCall, std::map &InProcess, unsigned Indent); + */ }; From lattner at cs.uiuc.edu Mon Nov 11 15:36:01 2002 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Mon Nov 11 15:36:01 2002 Subject: [llvm-commits] CVS: llvm/lib/Analysis/DataStructure/BottomUpClosure.cpp Message-ID: <200211112135.PAA08643@apoc.cs.uiuc.edu> Changes in directory llvm/lib/Analysis/DataStructure: BottomUpClosure.cpp updated: 1.42 -> 1.43 --- Log message: Complete rewrite of BU code to use Tarjan's SCC finding algorithm to drive the algorithm instead of hand coded depth first iteration --- Diffs of the changes: Index: llvm/lib/Analysis/DataStructure/BottomUpClosure.cpp diff -u llvm/lib/Analysis/DataStructure/BottomUpClosure.cpp:1.42 llvm/lib/Analysis/DataStructure/BottomUpClosure.cpp:1.43 --- llvm/lib/Analysis/DataStructure/BottomUpClosure.cpp:1.42 Sun Nov 10 18:01:34 2002 +++ llvm/lib/Analysis/DataStructure/BottomUpClosure.cpp Mon Nov 11 15:35:13 2002 @@ -18,19 +18,230 @@ using namespace DS; +// isCompleteNode - Return true if we know all of the targets of this node, and +// if the call sites are not external. +// +static inline bool isCompleteNode(DSNode *N) { + if (N->NodeType & DSNode::Incomplete) return false; + const std::vector &Callees = N->getGlobals(); + for (unsigned i = 0, e = Callees.size(); i != e; ++i) + if (Callees[i]->isExternal()) { + GlobalValue &FI = cast(*Callees[i]); + if (FI.getName() != "printf" && FI.getName() != "sscanf" && + FI.getName() != "fprintf" && FI.getName() != "open" && + FI.getName() != "sprintf" && FI.getName() != "fputs") + return false; // External function found... + } + return true; // otherwise ok +} + +struct CallSiteIterator { + // FCs are the edges out of the current node are the call site targets... + std::vector *FCs; + unsigned CallSite; + unsigned CallSiteEntry; + + CallSiteIterator(std::vector &CS) : FCs(&CS) { + CallSite = 0; CallSiteEntry = 0; + advanceToNextValid(); + } + + // End iterator ctor... + CallSiteIterator(std::vector &CS, bool) : FCs(&CS) { + CallSite = FCs->size(); CallSiteEntry = 0; + } + + void advanceToNextValid() { + while (CallSite < FCs->size()) { + if (DSNode *CalleeNode = (*FCs)[CallSite].getCallee().getNode()) { + if (CallSiteEntry || isCompleteNode(CalleeNode)) { + const std::vector &Callees = CalleeNode->getGlobals(); + + if (CallSiteEntry < Callees.size()) + return; + } + CallSiteEntry = 0; + ++CallSite; + } + } + } +public: + static CallSiteIterator begin(DSGraph &G) { return G.getAuxFunctionCalls(); } + static CallSiteIterator end(DSGraph &G) { + return CallSiteIterator(G.getAuxFunctionCalls(), true); + } + static CallSiteIterator begin(std::vector &CSs) { return CSs; } + static CallSiteIterator end(std::vector &CSs) { + return CallSiteIterator(CSs, true); + } + bool operator==(const CallSiteIterator &CSI) const { + return CallSite == CSI.CallSite && CallSiteEntry == CSI.CallSiteEntry; + } + bool operator!=(const CallSiteIterator &CSI) const { return !operator==(CSI);} + + unsigned getCallSiteIdx() const { return CallSite; } + DSCallSite &getCallSite() const { return (*FCs)[CallSite]; } + + Function* operator*() const { + DSNode *Node = (*FCs)[CallSite].getCallee().getNode(); + return cast(Node->getGlobals()[CallSiteEntry]); + } + + CallSiteIterator& operator++() { // Preincrement + ++CallSiteEntry; + advanceToNextValid(); + return *this; + } + CallSiteIterator operator++(int) { // Postincrement + CallSiteIterator tmp = *this; ++*this; return tmp; + } +}; + + + // run - Calculate the bottom up data structure graphs for each function in the // program. // bool BUDataStructures::run(Module &M) { GlobalsGraph = new DSGraph(); - // Simply calculate the graphs for each function... + Function *MainFunc = M.getMainFunction(); + if (MainFunc) + calculateReachableGraphs(MainFunc); + + // Calculate the graphs for any functions that are unreachable from main... for (Module::iterator I = M.begin(), E = M.end(); I != E; ++I) - if (!I->isExternal()) - calculateGraph(*I, 0); + if (!I->isExternal() && DSInfo.find(I) == DSInfo.end()) { + if (MainFunc) + std::cerr << "*** Function unreachable from main: " + << I->getName() << "\n"; + calculateReachableGraphs(I); // Calculate all graphs... + } return false; } +void BUDataStructures::calculateReachableGraphs(Function *F) { + std::vector Stack; + std::map ValMap; + unsigned NextID = 1; + calculateGraphs(F, Stack, NextID, ValMap); +} + +DSGraph &BUDataStructures::getOrCreateGraph(Function *F) { + // Has the graph already been created? + DSGraph *&Graph = DSInfo[F]; + if (Graph) return *Graph; + + // Copy the local version into DSInfo... + Graph = new DSGraph(getAnalysis().getDSGraph(*F)); + + Graph->setGlobalsGraph(GlobalsGraph); + Graph->setPrintAuxCalls(); + + // Start with a copy of the original call sites... + Graph->getAuxFunctionCalls() = Graph->getFunctionCalls(); + return *Graph; +} + +unsigned BUDataStructures::calculateGraphs(Function *F, + std::vector &Stack, + unsigned &NextID, + std::map &ValMap) { + assert(ValMap.find(F) == ValMap.end() && "Shouldn't revisit functions!"); + unsigned Min = NextID++, MyID = Min; + ValMap[F] = Min; + Stack.push_back(F); + + if (F->isExternal()) { // sprintf, fprintf, sscanf, etc... + // No callees! + Stack.pop_back(); + ValMap[F] = ~0; + return Min; + } + + DSGraph &Graph = getOrCreateGraph(F); + + // The edges out of the current node are the call site targets... + for (CallSiteIterator I = CallSiteIterator::begin(Graph), + E = CallSiteIterator::end(Graph); I != E; ++I) { + Function *Callee = *I; + unsigned M; + // Have we visited the destination function yet? + std::map::iterator It = ValMap.find(Callee); + if (It == ValMap.end()) // No, visit it now. + M = calculateGraphs(Callee, Stack, NextID, ValMap); + else // Yes, get it's number. + M = It->second; + if (M < Min) Min = M; + } + + assert(ValMap[F] == MyID && "SCC construction assumption wrong!"); + if (Min != MyID) + return Min; // This is part of a larger SCC! + + // If this is a new SCC, process it now. + if (Stack.back() == F) { // Special case the single "SCC" case here. + DEBUG(std::cerr << "Visiting single node SCC #: " << MyID << " fn: " + << F->getName() << "\n"); + Stack.pop_back(); + DSGraph &G = calculateGraph(*F); + + // Should we revisit the graph? + if (CallSiteIterator::begin(G) != CallSiteIterator::end(G)) { + ValMap.erase(F); + return calculateGraphs(F, Stack, NextID, ValMap); + } else { + ValMap[F] = ~0U; + } + return MyID; + + } else { + // SCCFunctions - Keep track of the functions in the current SCC + // + std::set SCCFunctions; + + Function *NF; + std::vector::iterator FirstInSCC = Stack.end(); + do { + NF = *--FirstInSCC; + ValMap[NF] = ~0U; + SCCFunctions.insert(NF); + } while (NF != F); + + std::cerr << "Identified SCC #: " << MyID << " of size: " + << (Stack.end()-FirstInSCC) << "\n"; + + std::vector::iterator I = Stack.end(); + do { + --I; + /*DEBUG*/(std::cerr << " Fn #" << (Stack.end()-I) << "/" + << (Stack.end()-FirstInSCC) << " in SCC: " + << (*I)->getName()); + DSGraph &G = getDSGraph(**I); + std::cerr << " [" << G.getGraphSize() << "+" + << G.getAuxFunctionCalls().size() << "] " << std::flush; + + // Inline all graphs into the last (highest numbered) node in the SCC + calculateSCCGraph(**I, SCCFunctions); + + std::cerr << "after [" << G.getGraphSize() << "+" + << G.getAuxFunctionCalls().size() << "]\n"; + } while (I != FirstInSCC); + + + std::cerr << "DONE with SCC #: " << MyID << "\n"; + + // We never have to revisit "SCC" processed functions... + + // Drop the stuff we don't need from the end of the stack + Stack.erase(FirstInSCC, Stack.end()); + return MyID; + } + + return MyID; // == Min +} + + // releaseMemory - If the pass pipeline is done with this pass, we can release // our memory... here... // @@ -46,294 +257,169 @@ GlobalsGraph = 0; } +DSGraph &BUDataStructures::calculateGraph(Function &F) { + DSGraph &Graph = getDSGraph(F); + DEBUG(std::cerr << " [BU] Calculating graph for: " << F.getName() << "\n"); + + // Move our call site list into TempFCs so that inline call sites go into the + // new call site list and doesn't invalidate our iterators! + std::vector TempFCs; + std::vector &AuxCallsList = Graph.getAuxFunctionCalls(); + TempFCs.swap(AuxCallsList); + + // Loop over all of the resolvable call sites + unsigned LastCallSiteIdx = ~0U; + for (CallSiteIterator I = CallSiteIterator::begin(TempFCs), + E = CallSiteIterator::end(TempFCs); I != E; ++I) { + // If we skipped over any call sites, they must be unresolvable, copy them + // to the real call site list. + LastCallSiteIdx++; + for (; LastCallSiteIdx < I.getCallSiteIdx(); ++LastCallSiteIdx) + AuxCallsList.push_back(TempFCs[LastCallSiteIdx]); + LastCallSiteIdx = I.getCallSiteIdx(); + + // Resolve the current call... + Function *Callee = *I; + DSCallSite &CS = I.getCallSite(); + + if (Callee->isExternal()) { + // Ignore this case, simple varargs functions we cannot stub out! + } else if (Callee == &F) { + // Self recursion... simply link up the formal arguments with the + // actual arguments... + DEBUG(std::cerr << " Self Inlining: " << F.getName() << "\n"); + + // Handle self recursion by resolving the arguments and return value + Graph.mergeInGraph(CS, Graph, 0); -// Return true if a graph was inlined -// Can not modify the part of the AuxCallList < FirstResolvableCall. -// -bool BUDataStructures::ResolveFunctionCalls(DSGraph &G, - unsigned &FirstResolvableCall, - std::map &InProcess, - unsigned Indent) { - std::vector &FCs = G.getAuxFunctionCalls(); - bool Changed = false; - - // Loop while there are call sites that we can resolve! - while (FirstResolvableCall != FCs.size()) { - DSCallSite Call = FCs[FirstResolvableCall]; - - // If the function list is incomplete... - if (Call.getCallee().getNode()->NodeType & DSNode::Incomplete) { - // If incomplete, we cannot resolve it, so leave it at the beginning of - // the call list with the other unresolvable calls... - ++FirstResolvableCall; } else { - // Start inlining all of the functions we can... some may not be - // inlinable if they are external... + // Get the data structure graph for the called function. // - const std::vector &Callees = - Call.getCallee().getNode()->getGlobals(); - - bool hasExternalTarget = false; + DSGraph &GI = getDSGraph(*Callee); // Graph to inline - // Loop over the functions, inlining whatever we can... - for (unsigned c = 0, e = Callees.size(); c != e; ++c) { - // Must be a function type, so this cast should succeed unless something - // really wierd is happening. - Function &FI = cast(*Callees[c]); - - if (FI.getName() == "printf" || FI.getName() == "sscanf" || - FI.getName() == "fprintf" || FI.getName() == "open" || - FI.getName() == "sprintf" || FI.getName() == "fputs") { - // Ignore - } else if (FI.isExternal()) { - // If the function is external, then we cannot resolve this call site! - hasExternalTarget = true; - break; - } else { - std::map::iterator I = - InProcess.lower_bound(&FI); - - if (I != InProcess.end() && I->first == &FI) { // Recursion detected? - // Merge two call sites to eliminate recursion... - Call.mergeWith(I->second); - - DEBUG(std::cerr << std::string(Indent*2, ' ') - << "* Recursion detected for function " << FI.getName()<<"\n"); - } else { - DEBUG(std::cerr << std::string(Indent*2, ' ') - << "Inlining: " << FI.getName() << "\n"); - - // Get the data structure graph for the called function, closing it - // if possible... - // - DSGraph &GI = calculateGraph(FI, Indent+1); // Graph to inline - - DEBUG(std::cerr << std::string(Indent*2, ' ') - << "Got graph for: " << FI.getName() << "[" - << GI.getGraphSize() << "+" - << GI.getAuxFunctionCalls().size() << "] " - << " in: " << G.getFunction().getName() << "[" - << G.getGraphSize() << "+" - << G.getAuxFunctionCalls().size() << "]\n"); - - // Keep track of how many call sites are added by the inlining... - unsigned NumCalls = FCs.size(); - - // Resolve the arguments and return value - G.mergeInGraph(Call, GI, DSGraph::StripAllocaBit | - DSGraph::DontCloneCallNodes); - - // Added a call site? - if (FCs.size() != NumCalls) { - // Otherwise we need to inline the graph. Temporarily add the - // current function to the InProcess map to be able to handle - // recursion successfully. - // - I = InProcess.insert(I, std::make_pair(&FI, Call)); - - // ResolveFunctionCalls - Resolve the function calls that just got - // inlined... - // - Changed |= ResolveFunctionCalls(G, NumCalls, InProcess, Indent+1); - - // Now that we are done processing the inlined graph, remove our - // cycle detector record... - // - //InProcess.erase(I); - } - } - } - } - - if (hasExternalTarget) { - // If we cannot resolve this call site... - ++FirstResolvableCall; - } else { - Changed = true; - FCs.erase(FCs.begin()+FirstResolvableCall); - } + DEBUG(std::cerr << " Inlining graph for " << Callee->getName() + << " in: " << F.getName() << "[" << GI.getGraphSize() << "+" + << GI.getAuxFunctionCalls().size() << "]\n"); + + // Handle self recursion by resolving the arguments and return value + Graph.mergeInGraph(CS, GI, DSGraph::StripAllocaBit | + DSGraph::DontCloneCallNodes); } } - return Changed; -} - -DSGraph &BUDataStructures::calculateGraph(Function &F, unsigned Indent) { - // Make sure this graph has not already been calculated, or that we don't get - // into an infinite loop with mutually recursive functions. - // - DSGraph *&GraphPtr = DSInfo[&F]; - if (GraphPtr) return *GraphPtr; - - // Copy the local version into DSInfo... - GraphPtr = new DSGraph(getAnalysis().getDSGraph(F)); - DSGraph &Graph = *GraphPtr; + // Make sure to catch any leftover unresolvable calls... + for (++LastCallSiteIdx; LastCallSiteIdx < TempFCs.size(); ++LastCallSiteIdx) + AuxCallsList.push_back(TempFCs[LastCallSiteIdx]); + + TempFCs.clear(); + + // Recompute the Incomplete markers. If there are any function calls left + // now that are complete, we must loop! + Graph.maskIncompleteMarkers(); + Graph.markIncompleteNodes(); + Graph.removeDeadNodes(); - Graph.setGlobalsGraph(GlobalsGraph); - Graph.setPrintAuxCalls(); + DEBUG(std::cerr << " [BU] Done inlining: " << F.getName() << " [" + << Graph.getGraphSize() << "+" << Graph.getAuxFunctionCalls().size() + << "]\n"); - // Start resolving calls... - std::vector &FCs = Graph.getAuxFunctionCalls(); + //Graph.writeGraphToFile(std::cerr, "bu_" + F.getName()); - // Start with a copy of the original call sites... - FCs = Graph.getFunctionCalls(); + return Graph; +} - DEBUG(std::cerr << std::string(Indent*2, ' ') - << "[BU] Calculating graph for: " << F.getName() << "\n"); - bool Changed; - while (1) { - unsigned FirstResolvableCall = 0; - std::map InProcess; - - // Insert a call site for self to handle self recursion... - std::vector Args; - Args.reserve(F.asize()); - for (Function::aiterator I = F.abegin(), E = F.aend(); I != E; ++I) - if (isPointerType(I->getType())) - Args.push_back(Graph.getNodeForValue(I)); - - InProcess.insert(std::make_pair(&F, - DSCallSite(*(CallInst*)0, Graph.getRetNode(),(DSNode*)0,Args))); - - Changed = ResolveFunctionCalls(Graph, FirstResolvableCall, InProcess, - Indent); - - if (Changed) { - Graph.maskIncompleteMarkers(); - Graph.markIncompleteNodes(); - Graph.removeDeadNodes(); - break; - } else { - break; +DSGraph &BUDataStructures::calculateSCCGraph(Function &F, + std::set &InlinedSCCFunctions) { + DSGraph &Graph = getDSGraph(F); + DEBUG(std::cerr << " [BU] Calculating SCC graph for: " << F.getName()<<"\n"); + + std::vector UnresolvableCalls; + std::map SCCCallSiteMap; + std::vector &AuxCallsList = Graph.getAuxFunctionCalls(); + + while (1) { // Loop until we run out of resolvable call sites! + // Move our call site list into TempFCs so that inline call sites go into + // the new call site list and doesn't invalidate our iterators! + std::vector TempFCs; + TempFCs.swap(AuxCallsList); + + // Loop over all of the resolvable call sites + unsigned LastCallSiteIdx = ~0U; + CallSiteIterator I = CallSiteIterator::begin(TempFCs), + E = CallSiteIterator::end(TempFCs); + if (I == E) { + TempFCs.swap(AuxCallsList); + break; // Done when no resolvable call sites exist } - } -#if 0 - bool Inlined; - do { - Inlined = false; - - for (unsigned i = 0; i != FCs.size(); ++i) { - // Copy the call, because inlining graphs may invalidate the FCs vector. - DSCallSite Call = FCs[i]; - - // If the function list is complete... - if ((Call.getCallee().getNode()->NodeType & DSNode::Incomplete)==0) { - // Start inlining all of the functions we can... some may not be - // inlinable if they are external... + for (; I != E; ++I) { + // If we skipped over any call sites, they must be unresolvable, copy them + // to the unresolvable site list. + LastCallSiteIdx++; + for (; LastCallSiteIdx < I.getCallSiteIdx(); ++LastCallSiteIdx) + UnresolvableCalls.push_back(TempFCs[LastCallSiteIdx]); + LastCallSiteIdx = I.getCallSiteIdx(); + + // Resolve the current call... + Function *Callee = *I; + DSCallSite &CS = I.getCallSite(); + + if (Callee->isExternal()) { + // Ignore this case, simple varargs functions we cannot stub out! + } else if (Callee == &F) { + // Self recursion... simply link up the formal arguments with the + // actual arguments... + DEBUG(std::cerr << " Self Inlining: " << F.getName() << "\n"); + + // Handle self recursion by resolving the arguments and return value + Graph.mergeInGraph(CS, Graph, 0); + } else if (SCCCallSiteMap.count(Callee)) { + // We have already seen a call site in the SCC for this function, just + // merge the two call sites together and we are done. + SCCCallSiteMap.find(Callee)->second.mergeWith(CS); + } else { + // Get the data structure graph for the called function. // - std::vector Callees = - Call.getCallee().getNode()->getGlobals(); - - unsigned OldNumCalls = FCs.size(); - - // Loop over the functions, inlining whatever we can... - for (unsigned c = 0; c != Callees.size(); ++c) { - // Must be a function type, so this cast MUST succeed. - Function &FI = cast(*Callees[c]); - - if (&FI == &F) { - // Self recursion... simply link up the formal arguments with the - // actual arguments... - DEBUG(std::cerr << std::string(Indent*2, ' ') - << "[BU] Self Inlining: " << F.getName() << "\n"); - - // Handle self recursion by resolving the arguments and return value - Graph.mergeInGraph(Call, Graph, DSGraph::StripAllocaBit); - - // Erase the entry in the callees vector - Callees.erase(Callees.begin()+c--); - - } else if (!FI.isExternal()) { - DEBUG(std::cerr << std::string(Indent*2, ' ') - << "[BU] In " << F.getName() << " inlining: " - << FI.getName() << "\n"); - - // Get the data structure graph for the called function, closing it - // if possible (which is only impossible in the case of mutual - // recursion... - // - DSGraph &GI = calculateGraph(FI, Indent+1); // Graph to inline - - DEBUG(std::cerr << std::string(Indent*2, ' ') - << "[BU] Got graph for " << FI.getName() - << " in: " << F.getName() << "[" << GI.getGraphSize() << "+" - << GI.getAuxFunctionCalls().size() << "]\n"); - - // Handle self recursion by resolving the arguments and return value - Graph.mergeInGraph(Call, GI, DSGraph::StripAllocaBit | - DSGraph::DontCloneCallNodes); - - // Erase the entry in the Callees vector - Callees.erase(Callees.begin()+c--); - - } else if (FI.getName() == "printf" || FI.getName() == "sscanf" || - FI.getName() == "fprintf" || FI.getName() == "open" || - FI.getName() == "sprintf" || FI.getName() == "fputs") { - // FIXME: These special cases (eg printf) should go away when we can - // define functions that take a variable number of arguments. - - // FIXME: at the very least, this should update mod/ref info - // Erase the entry in the globals vector - Callees.erase(Callees.begin()+c--); - } - } - - if (Callees.empty()) { // Inlined all of the function calls? - // Erase the call if it is resolvable... - FCs.erase(FCs.begin()+i--); // Don't skip a the next call... - Inlined = true; - } else if (Callees.size() != - Call.getCallee().getNode()->getGlobals().size()) { - // Was able to inline SOME, but not all of the functions. Construct a - // new global node here. - // - assert(0 && "Unimpl!"); - Inlined = true; - } - + DSGraph &GI = getDSGraph(*Callee); // Graph to inline + + DEBUG(std::cerr << " Inlining graph for " << Callee->getName() + << " in: " << F.getName() << "[" << GI.getGraphSize() << "+" + << GI.getAuxFunctionCalls().size() << "]\n"); + + // Handle self recursion by resolving the arguments and return value + Graph.mergeInGraph(CS, GI, DSGraph::StripAllocaBit | + DSGraph::DontCloneCallNodes); -#if 0 - // If we just inlined a function that had call nodes, chances are that - // the call nodes are redundant with ones we already have. Eliminate - // those call nodes now. - // - if (FCs.size() >= OldNumCalls) - Graph.removeTriviallyDeadNodes(); -#endif + if (InlinedSCCFunctions.count(Callee)) + SCCCallSiteMap.insert(std::make_pair(Callee, CS)); } + } + + // Make sure to catch any leftover unresolvable calls... + for (++LastCallSiteIdx; LastCallSiteIdx < TempFCs.size(); ++LastCallSiteIdx) + UnresolvableCalls.push_back(TempFCs[LastCallSiteIdx]); + } - if (FCs.size() > 200) { - std::cerr << "Aborted inlining fn: '" << F.getName() << "'!" - << std::endl; - Graph.maskIncompleteMarkers(); - Graph.markIncompleteNodes(); - Graph.removeDeadNodes(); - Graph.writeGraphToFile(std::cerr, "crap."+F.getName()); - exit(1); - return Graph; - } + // Reset the SCCCallSiteMap... + SCCCallSiteMap.clear(); - } + AuxCallsList.insert(AuxCallsList.end(), UnresolvableCalls.begin(), + UnresolvableCalls.end()); + UnresolvableCalls.clear(); - // Recompute the Incomplete markers. If there are any function calls left - // now that are complete, we must loop! - if (Inlined) { - Graph.maskIncompleteMarkers(); - Graph.markIncompleteNodes(); - Graph.removeDeadNodes(); - } - - } while (Inlined && !FCs.empty()); -#endif - DEBUG(std::cerr << std::string(Indent*2, ' ') - << "[BU] Done inlining: " << F.getName() << " [" + // Recompute the Incomplete markers. If there are any function calls left + // now that are complete, we must loop! + Graph.maskIncompleteMarkers(); + Graph.markIncompleteNodes(); + Graph.removeDeadNodes(); + + DEBUG(std::cerr << " [BU] Done inlining: " << F.getName() << " [" << Graph.getGraphSize() << "+" << Graph.getAuxFunctionCalls().size() << "]\n"); - Graph.writeGraphToFile(std::cerr, "bu_" + F.getName()); + //Graph.writeGraphToFile(std::cerr, "bu_" + F.getName()); return Graph; } From lattner at cs.uiuc.edu Mon Nov 11 15:36:02 2002 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Mon Nov 11 15:36:02 2002 Subject: [llvm-commits] CVS: llvm/lib/Analysis/DataStructure/DataStructure.cpp Message-ID: <200211112135.PAA08654@apoc.cs.uiuc.edu> Changes in directory llvm/lib/Analysis/DataStructure: DataStructure.cpp updated: 1.65 -> 1.66 --- Log message: Elimiante calls to a node with nothing in it. --- Diffs of the changes: Index: llvm/lib/Analysis/DataStructure/DataStructure.cpp diff -u llvm/lib/Analysis/DataStructure/DataStructure.cpp:1.65 llvm/lib/Analysis/DataStructure/DataStructure.cpp:1.66 --- llvm/lib/Analysis/DataStructure/DataStructure.cpp:1.65 Sun Nov 10 21:36:55 2002 +++ llvm/lib/Analysis/DataStructure/DataStructure.cpp Mon Nov 11 15:35:38 2002 @@ -808,45 +808,54 @@ DSNode *LastCalleeNode = 0; unsigned NumDuplicateCalls = 0; bool LastCalleeContainsExternalFunction = false; - for (unsigned i = 0, e = Calls.size(); i != e; ++i) { + for (unsigned i = 0; i != Calls.size(); ++i) { DSCallSite &CS = Calls[i]; - // If the return value or any arguments point to a void node with no - // information at all in it, and the call node is the only node to point - // to it, remove the edge to the node (killing the node). - // - killIfUselessEdge(CS.getRetVal()); - for (unsigned a = 0, e = CS.getNumPtrArgs(); a != e; ++a) - killIfUselessEdge(CS.getPtrArg(a)); - - // If this call site calls the same function as the last call site, and if - // the function pointer contains an external function, this node will never - // be resolved. Merge the arguments of the call node because no information - // will be lost. - // - if (CS.getCallee().getNode() == LastCalleeNode) { - ++NumDuplicateCalls; - if (NumDuplicateCalls == 1) { - LastCalleeContainsExternalFunction = - nodeContainsExternalFunction(LastCalleeNode); - } - - if (LastCalleeContainsExternalFunction || - // This should be more than enough context sensitivity! - // FIXME: Evaluate how many times this is tripped! - NumDuplicateCalls > 20) { - DSCallSite &OCS = Calls[i-1]; - OCS.mergeWith(CS); - - // The node will now be eliminated as a duplicate! - if (CS.getNumPtrArgs() < OCS.getNumPtrArgs()) - CS = OCS; - else if (CS.getNumPtrArgs() > OCS.getNumPtrArgs()) - OCS = CS; - } + // If the Callee is a useless edge, this must be an unreachable call site, + // eliminate it. + killIfUselessEdge(CS.getCallee()); + if (CS.getCallee().getNode() == 0) { + CS.swap(Calls.back()); + Calls.pop_back(); + --i; } else { - LastCalleeNode = CS.getCallee().getNode(); - NumDuplicateCalls = 0; + // If the return value or any arguments point to a void node with no + // information at all in it, and the call node is the only node to point + // to it, remove the edge to the node (killing the node). + // + killIfUselessEdge(CS.getRetVal()); + for (unsigned a = 0, e = CS.getNumPtrArgs(); a != e; ++a) + killIfUselessEdge(CS.getPtrArg(a)); + + // If this call site calls the same function as the last call site, and if + // the function pointer contains an external function, this node will + // never be resolved. Merge the arguments of the call node because no + // information will be lost. + // + if (CS.getCallee().getNode() == LastCalleeNode) { + ++NumDuplicateCalls; + if (NumDuplicateCalls == 1) { + LastCalleeContainsExternalFunction = + nodeContainsExternalFunction(LastCalleeNode); + } + + if (LastCalleeContainsExternalFunction || + // This should be more than enough context sensitivity! + // FIXME: Evaluate how many times this is tripped! + NumDuplicateCalls > 20) { + DSCallSite &OCS = Calls[i-1]; + OCS.mergeWith(CS); + + // The node will now be eliminated as a duplicate! + if (CS.getNumPtrArgs() < OCS.getNumPtrArgs()) + CS = OCS; + else if (CS.getNumPtrArgs() > OCS.getNumPtrArgs()) + OCS = CS; + } + } else { + LastCalleeNode = CS.getCallee().getNode(); + NumDuplicateCalls = 0; + } } } From lattner at cs.uiuc.edu Mon Nov 11 15:37:00 2002 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Mon Nov 11 15:37:00 2002 Subject: [llvm-commits] CVS: llvm/lib/Analysis/DataStructure/TopDownClosure.cpp Message-ID: <200211112136.PAA08665@apoc.cs.uiuc.edu> Changes in directory llvm/lib/Analysis/DataStructure: TopDownClosure.cpp updated: 1.29 -> 1.30 --- Log message: Handle a mismatch between # function args and call site args --- Diffs of the changes: Index: llvm/lib/Analysis/DataStructure/TopDownClosure.cpp diff -u llvm/lib/Analysis/DataStructure/TopDownClosure.cpp:1.29 llvm/lib/Analysis/DataStructure/TopDownClosure.cpp:1.30 --- llvm/lib/Analysis/DataStructure/TopDownClosure.cpp:1.29 Sat Nov 9 16:06:59 2002 +++ llvm/lib/Analysis/DataStructure/TopDownClosure.cpp Mon Nov 11 15:36:05 2002 @@ -160,7 +160,8 @@ // Resolve all of the arguments... Function::aiterator AI = Callee->abegin(); - for (unsigned i = 0, e = NewCS.getNumPtrArgs(); i != e; ++i, ++AI) { + for (unsigned i = 0, e = NewCS.getNumPtrArgs(); + i != e && AI != Callee->aend(); ++i, ++AI) { // Advance the argument iterator to the first pointer argument... while (!DS::isPointerType(AI->getType())) { ++AI; From lattner at cs.uiuc.edu Mon Nov 11 16:25:01 2002 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Mon Nov 11 16:25:01 2002 Subject: [llvm-commits] CVS: llvm/lib/Analysis/IPA/IPModRef.cpp Message-ID: <200211112224.QAA09252@apoc.cs.uiuc.edu> Changes in directory llvm/lib/Analysis/IPA: IPModRef.cpp updated: 1.9 -> 1.10 --- Log message: Fix bug --- Diffs of the changes: Index: llvm/lib/Analysis/IPA/IPModRef.cpp diff -u llvm/lib/Analysis/IPA/IPModRef.cpp:1.9 llvm/lib/Analysis/IPA/IPModRef.cpp:1.10 --- llvm/lib/Analysis/IPA/IPModRef.cpp:1.9 Fri Nov 8 16:17:01 2002 +++ llvm/lib/Analysis/IPA/IPModRef.cpp Mon Nov 11 16:23:56 2002 @@ -158,9 +158,8 @@ return 0; } - // Remove trivial dead nodes... don't aggressively prune graph though... the - // graph is short lived anyway. - Result->removeTriviallyDeadNodes(false); + // Remove dead nodes... + Result->removeDeadNodes(); // Step #4: Return the clone + the mapping (by ref) return Result; From lattner at cs.uiuc.edu Tue Nov 12 00:54:01 2002 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Tue Nov 12 00:54:01 2002 Subject: [llvm-commits] CVS: llvm/www/docs/DSGraphStatus.html Message-ID: <200211120653.AAA25267@tank.cs.uiuc.edu> Changes in directory llvm/www/docs: DSGraphStatus.html updated: 1.11 -> 1.12 --- Log message: Add new numbers --- Diffs of the changes: Index: llvm/www/docs/DSGraphStatus.html diff -u llvm/www/docs/DSGraphStatus.html:1.11 llvm/www/docs/DSGraphStatus.html:1.12 --- llvm/www/docs/DSGraphStatus.html:1.11 Mon Nov 11 14:48:45 2002 +++ llvm/www/docs/DSGraphStatus.html Tue Nov 12 00:53:43 2002 @@ -13,6 +13,63 @@ previous value.

+

Nov 11, 2002 #2:

+ +This is the result after fixing some major bugs. The globals list was supposed +to be kept sorted, but there was one minor, tiny, little, bug that caused it to +get screwed up sometimes. This caused vortex to explode, fixing it gets things +back in control where you'd expect. Viola.

+ +This also includes a merging bug that caused some things to be merged and some +other things to happen when they shouldn't, which accounts for folding +reductions.

+ +

+Name:                     Anlyz: LocTime: BUTime:  TDTime:  TotTime: BCTime:      LocSize: BUSize:  TDSize:  TotSize: BCSize:    NumFold  NumNodes   main   __main GlobGr
+254.gap.lib                17.65 0.8186   4.5919   2.3718   9.2483   2.8978   |   2024984  2984936  2025480  7035400  16554904 |    6853  24032+3950 44+9   0+0    0+0    
+255.vortex.lib             15.02 0.5766   2.4586   3.5717   7.6692   2.2728   |   1381056  1340216  2461232  5182504  11689312 |    7127  7302+2815  166+11 0+0    0+0    
+300.twolf.lib               3.23 0.2747   0.2856   0.5057   1.5129   0.9846   |   466528   391512   396552   1254592  6936728  |    749   4128+784   90+53  0+0    0+0    
+197.parser.lib              1.84 0.1528   0.3458   0.2180   0.8983   0.6469   |   408392   225312   212688   965648   4447944  |    1357  2257+707   14+6   0+0    0+0    
+burg.llvm.lib               1.20 0.1017   0.1867   0.1765   0.5525   0.4912   |   530600   473296   185792   1189688  3040208  |    756   2273+576   45+7   0+0    0+0    
+164.gzip.llvm.lib           0.71 0.0392   0.0649   0.0330   0.2008   0.4263   |   145952   184776   70872    499912   1876248  |    24    971+87     8+2    0+0    0+0    
+optimizer-eval.llvm.lib     0.42 0.0163   0.0446   0.2063   0.2953   0.0798   |   101184   79456    61760    242400   624688   |    *     309+41     72+27  0+0    0+0    
+256.bzip2.lib               0.34 0.0238   0.0491   0.0112   0.1311   0.1543   |   139504   83400    39712    335144   1373216  |    *     563+37     8+2    0+0    0+0    
+181.mcf.lib                 0.20 0.0174   0.0267   0.0272   0.0906   0.0744   |   115448   146520   43680    322864   589440   |    166   388+51     22+10  0+0    0+0    
+sim.llvm.lib                0.19 0.0135   0.0136   0.0130   0.0776   0.0794   |   81632    51496    21872    226584   734152   |    *     260+35     39+22  0+0    0+0    
+voronoi.llvm.lib            0.17 0.0137   0.0267   0.0286   0.0829   0.0561   |   79824    84152    27112    204904   420568   |    18    299+77     15+8   0+0    0+0    
+bh.llvm.lib                 0.16 0.0116   0.0161   0.0111   0.0591   0.0675   |   75000    51080    27760    217632   470720   |    61    194+35     6+2    0+0    0+0    
+sgefa.llvm.lib              0.14 0.0086   0.0201   0.0208   0.0656   0.0517   |   85688    100456   67024    277864   368680   |    *     130+24     24+14  0+0    0+0    
+sumarray2d.llvm.lib         0.11 0.0005   0.0009   0.0002   0.0033   0.0922   |   1568     3584     848      8264     23288    |    *     10+1       7+1    0+0    0+0    
+health.llvm.lib             0.09 0.0050   0.0082   0.0073   0.0280   0.0419   |   30632    31432    12704    89592    199888   |    18    97+31      12+4   0+0    0+0    
+em3d.llvm.lib               0.09 0.0058   0.0110   0.0059   0.0304   0.0395   |   33040    36256    13008    90632    227520   |    1     178+28     12+4   0+0    0+0    
+power.llvm.lib              0.08 0.0042   0.0067   0.0040   0.0222   0.0365   |   27776    17688    18144    71424    213760   |    *     81+18      11+2   0+0    0+0    
+mst.llvm.lib                0.08 0.0039   0.0072   0.0037   0.0218   0.0306   |   18624    25576    7040     65808    178832   |    10    97+15      12+3   0+0    0+0    
+lists.llvm.lib              0.08 0.0043   0.0137   0.0072   0.0306   0.0283   |   24552    16920    14440    68024    141480   |    30    67+26      3+1    0+0    0+0    
+tsp.llvm.lib                0.07 0.0048   0.0066   0.0027   0.0217   0.0327   |   18232    14336    4920     51888    180744   |    21    43+15      8+4    0+0    0+0    
+perimeter.llvm.lib          0.06 0.0031   0.0066   0.0024   0.0194   0.0260   |   15016    14192    3936     45912    156352   |    *     35+15      7+4    0+0    0+0    
+bisort.llvm.lib             0.06 0.0029   0.0056   0.0018   0.0230   0.0229   |   13288    11408    3712     39448    127360   |    *     35+13      7+4    0+0    0+0    
+objinst.llvm.lib            0.05 0.0019   0.0048   0.0031   0.0153   0.0174   |   11280    15784    4112     45296    89856    |    34    45+14      16+10  0+0    0+0    
+methcall.llvm.lib           0.05 0.0017   0.0043   0.0028   0.0135   0.0187   |   11008    9880     3928     38624    87976    |    30    43+12      14+8   0+0    0+0    
+heapsort.llvm.lib           0.05 0.0009   0.0020   0.0007   0.0074   0.0306   |   2856     6968     2008     26976    63160    |    *     26+3       7+2    0+0    0+0    
+hash.llvm.lib               0.05 0.0030   0.0052   0.0040   0.0184   0.0173   |   25728    16608    8208     63576    151680   |    *     117+17     14+6   0+0    0+0    
+sumarraymalloc.llvm.lib     0.04 0.0009   0.0015   0.0009   0.0067   0.0156   |   7040     2672     2048     25872    54352    |    *     23+5       7+4    0+0    0+0    
+random.llvm.lib             0.04 0.0009   0.0018   0.0004   0.0060   0.0223   |   2056     5720     1320     22080    45264    |    *     15+2       3+1    0+0    0+0    
+llubenchmark.llvm.lib       0.04 0.0022   0.0028   0.0015   0.0130   0.0118   |   11072    11760    2624     36480    124344   |    *     31+7       15+5   0+0    0+0    
+ackermann.llvm.lib          0.04 0.0007   0.0015   0.0004   0.0055   0.0230   |   1744     5728     1200     22056    46448    |    *     13+2       3+1    0+0    0+0    
+treeadd.llvm.lib            0.03 0.0015   0.0029   0.0009   0.0090   0.0076   |   3856     7384     2200     29784    72064    |    *     25+7       6+3    0+0    0+0    
+sieve.llvm.lib              0.03 0.0007   0.0013   0.0005   0.0060   0.0140   |   2176     6176     1632     23432    216840   |    *     22+2       12+1   0+0    0+0    
+printargs.llvm.lib          0.03 0.0005   0.0015   0.0002   0.0034   0.0077   |   1240     1048     696      5128     19160    |    *     6+1        4+1    0+0    0+0    
+matrixTranspose.llvm.lib    0.03 0.0005   0.0010   0.0003   0.0032   0.0167   |   4272     1144     736      8560     68448    |    *     8+1        5+1    0+0    0+0    
+matrix.llvm.lib             0.03 0.0013   0.0022   0.0014   0.0092   0.0100   |   8808     8872     3072     33144    69112    |    *     38+9       12+8   0+0    0+0    
+hello.llvm.lib              0.03 0.0004   0.0014   0.0001   0.0067   0.0123   |   752      2952     472      6512     14160    |    *     2+0        0+0    0+0    0+0    
+fib2.llvm.lib               0.03 0.0008   0.0015   0.0007   0.0061   0.0135   |   7960     6288     1640     28408    42256    |    *     21+5       8+3    0+0    0+0    
+ary3.llvm.lib               0.03 0.0012   0.0020   0.0011   0.0086   0.0084   |   10240    13104    10888    45832    73064    |    6     44+5       12+3   0+0    0+0    
+sumarray.llvm.lib           0.02 0.0003   0.0009   0.0002   0.0028   0.0114   |   904      3192     624      4720     15152    |    *     6+1        4+1    0+0    0+0    
+pi.llvm.lib                 0.02 0.0008   0.0020   0.0004   0.0050   0.0037   |   5392     1560     1392     8344     36032    |    *     17+2       13+2   0+0    0+0    
+indvars.llvm.lib            0.02 0.0005   0.0009   0.0003   0.0035   0.0035   |   4744     1072     4208     12544    31336    |    *     13+1       8+1    0+0    0+0    
+

+ +

Nov 11, 2002:

This is the first successful run of all of the benchmarks! This is still @@ -589,7 +646,7 @@
Chris Lattner
-Last modified: Mon Nov 11 14:48:26 CST 2002 +Last modified: Tue Nov 12 00:49:40 CST 2002 From lattner at cs.uiuc.edu Tue Nov 12 01:21:01 2002 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Tue Nov 12 01:21:01 2002 Subject: [llvm-commits] CVS: llvm/lib/Analysis/DataStructure/DataStructure.cpp Message-ID: <200211120720.BAA15116@apoc.cs.uiuc.edu> Changes in directory llvm/lib/Analysis/DataStructure: DataStructure.cpp updated: 1.66 -> 1.67 --- Log message: Fix two bugs: * The globals vector was getting broken and unsorted, this caused vortex to get badly pessimized * Node offset handling was being handled really poorly, and in particular we were not merging types with offsets right. This causes several graphs to be non-merged. --- Diffs of the changes: Index: llvm/lib/Analysis/DataStructure/DataStructure.cpp diff -u llvm/lib/Analysis/DataStructure/DataStructure.cpp:1.66 llvm/lib/Analysis/DataStructure/DataStructure.cpp:1.67 --- llvm/lib/Analysis/DataStructure/DataStructure.cpp:1.66 Mon Nov 11 15:35:38 2002 +++ llvm/lib/Analysis/DataStructure/DataStructure.cpp Tue Nov 12 01:20:45 2002 @@ -341,9 +341,9 @@ T Tmp = Dest[0]; // Save value in temporary... Dest = Src; // Copy over list... typename vector::iterator I = - std::lower_bound(Dest.begin(), Dest.end(),Tmp); - if (I == Dest.end() || *I != Src[0]) // If not already contained... - Dest.insert(I, Src[0]); + std::lower_bound(Dest.begin(), Dest.end(), Tmp); + if (I == Dest.end() || *I != Tmp) // If not already contained... + Dest.insert(I, Tmp); } else { // Make a copy to the side of Dest... @@ -387,9 +387,28 @@ return; } + // If both nodes are not at offset 0, make sure that we are merging the node + // at an later offset into the node with the zero offset. + // + if (Offset < NH.getOffset()) { + N->mergeWith(DSNodeHandle(this, Offset), NH.getOffset()); + return; + } else if (Offset == NH.getOffset() && getSize() < N->getSize()) { + // If the offsets are the same, merge the smaller node into the bigger node + N->mergeWith(DSNodeHandle(this, Offset), NH.getOffset()); + return; + } + + // Now we know that Offset >= NH.Offset, so convert it so our "Offset" (with + // respect to NH.Offset) is now zero. NOffset is the distance from the base + // of our object that N starts from. + // + unsigned NOffset = Offset-NH.getOffset(); + unsigned NSize = N->getSize(); + // Merge the type entries of the two nodes together... if (N->Ty.Ty != Type::VoidTy) { - mergeTypeInfo(N->Ty.Ty, Offset); + mergeTypeInfo(N->Ty.Ty, NOffset); // mergeTypeInfo can cause collapsing, which can cause this node to become // dead. @@ -404,44 +423,25 @@ if (!N->isNodeCompletelyFolded()) { N->foldNodeCompletely(); if (hasNoReferrers()) return; + NSize = N->getSize(); } } else if (N->isNodeCompletelyFolded()) { foldNodeCompletely(); - Offset = 0; if (hasNoReferrers()) return; + Offset = 0; + NOffset = NH.getOffset(); + NSize = N->getSize(); } N = NH.getNode(); - assert((NodeType & DSNode::DEAD) == 0); - if (this == N || N == 0) return; assert((NodeType & DSNode::DEAD) == 0); - // If both nodes are not at offset 0, make sure that we are merging the node - // at an later offset into the node with the zero offset. - // - if (Offset > NH.getOffset()) { - N->mergeWith(DSNodeHandle(this, Offset), NH.getOffset()); - return; - } else if (Offset == NH.getOffset() && getSize() < N->getSize()) { - // If the offsets are the same, merge the smaller node into the bigger node - N->mergeWith(DSNodeHandle(this, Offset), NH.getOffset()); - return; - } - #if 0 std::cerr << "\n\nMerging:\n"; N->print(std::cerr, 0); std::cerr << " and:\n"; print(std::cerr, 0); #endif - - // Now we know that Offset <= NH.Offset, so convert it so our "Offset" (with - // respect to NH.Offset) is now zero. - // - unsigned NOffset = NH.getOffset()-Offset; - unsigned NSize = N->getSize(); - - assert((NodeType & DSNode::DEAD) == 0); // Remove all edges pointing at N, causing them to point to 'this' instead. // Make sure to adjust their offset, not just the node pointer. From lattner at cs.uiuc.edu Tue Nov 12 09:58:01 2002 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Tue Nov 12 09:58:01 2002 Subject: [llvm-commits] CVS: llvm/include/llvm/Analysis/DataStructure.h Message-ID: <200211121557.JAA16816@apoc.cs.uiuc.edu> Changes in directory llvm/include/llvm/Analysis: DataStructure.h updated: 1.58 -> 1.59 --- Log message: Remove dead method, add new method --- Diffs of the changes: Index: llvm/include/llvm/Analysis/DataStructure.h diff -u llvm/include/llvm/Analysis/DataStructure.h:1.58 llvm/include/llvm/Analysis/DataStructure.h:1.59 --- llvm/include/llvm/Analysis/DataStructure.h:1.58 Mon Nov 11 15:34:34 2002 +++ llvm/include/llvm/Analysis/DataStructure.h Tue Nov 12 09:57:28 2002 @@ -103,6 +103,15 @@ } private: DSGraph &calculateGraph(Function &F); + + // inlineNonSCCGraphs - This method is almost like the other two calculate + // graph methods. This one is used to inline function graphs (from functions + // outside of the SCC) into functions in the SCC. It is not supposed to touch + // functions IN the SCC at all. + // + DSGraph &BUDataStructures::inlineNonSCCGraphs(Function &F, + std::set &SCCFunctions); + DSGraph &calculateSCCGraph(Function &F, std::set &InlinedSCCFunctions); void calculateReachableGraphs(Function *F); @@ -113,13 +122,6 @@ unsigned calculateGraphs(Function *F, std::vector &Stack, unsigned &NextID, std::map &ValMap); - - - /* - bool ResolveFunctionCalls(DSGraph &G, unsigned &FirstResolvableCall, - std::map &InProcess, - unsigned Indent); - */ }; From lattner at cs.uiuc.edu Tue Nov 12 09:59:00 2002 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Tue Nov 12 09:59:00 2002 Subject: [llvm-commits] CVS: llvm/lib/Analysis/DataStructure/BottomUpClosure.cpp Message-ID: <200211121558.JAA16827@apoc.cs.uiuc.edu> Changes in directory llvm/lib/Analysis/DataStructure: BottomUpClosure.cpp updated: 1.43 -> 1.44 --- Log message: Inline graphs from outside the SCC into the SCC before SCC resolution starts --- Diffs of the changes: Index: llvm/lib/Analysis/DataStructure/BottomUpClosure.cpp diff -u llvm/lib/Analysis/DataStructure/BottomUpClosure.cpp:1.43 llvm/lib/Analysis/DataStructure/BottomUpClosure.cpp:1.44 --- llvm/lib/Analysis/DataStructure/BottomUpClosure.cpp:1.43 Mon Nov 11 15:35:13 2002 +++ llvm/lib/Analysis/DataStructure/BottomUpClosure.cpp Tue Nov 12 09:58:08 2002 @@ -214,18 +214,43 @@ std::vector::iterator I = Stack.end(); do { --I; +#ifndef NDEBUG /*DEBUG*/(std::cerr << " Fn #" << (Stack.end()-I) << "/" << (Stack.end()-FirstInSCC) << " in SCC: " << (*I)->getName()); DSGraph &G = getDSGraph(**I); std::cerr << " [" << G.getGraphSize() << "+" - << G.getAuxFunctionCalls().size() << "] " << std::flush; + << G.getAuxFunctionCalls().size() << "] "; +#endif - // Inline all graphs into the last (highest numbered) node in the SCC + // Eliminate all call sites in the SCC that are not to functions that are + // in the SCC. + inlineNonSCCGraphs(**I, SCCFunctions); + +#ifndef NDEBUG + std::cerr << "after Non-SCC's [" << G.getGraphSize() << "+" + << G.getAuxFunctionCalls().size() << "]\n"; +#endif + } while (I != FirstInSCC); + + I = Stack.end(); + do { + --I; +#ifndef NDEBUG + /*DEBUG*/(std::cerr << " Fn #" << (Stack.end()-I) << "/" + << (Stack.end()-FirstInSCC) << " in SCC: " + << (*I)->getName()); + DSGraph &G = getDSGraph(**I); + std::cerr << " [" << G.getGraphSize() << "+" + << G.getAuxFunctionCalls().size() << "] "; +#endif + // Inline all graphs into the SCC nodes... calculateSCCGraph(**I, SCCFunctions); +#ifndef NDEBUG std::cerr << "after [" << G.getGraphSize() << "+" << G.getAuxFunctionCalls().size() << "]\n"; +#endif } while (I != FirstInSCC); @@ -329,8 +354,83 @@ } +// inlineNonSCCGraphs - This method is almost like the other two calculate graph +// methods. This one is used to inline function graphs (from functions outside +// of the SCC) into functions in the SCC. It is not supposed to touch functions +// IN the SCC at all. +// +DSGraph &BUDataStructures::inlineNonSCCGraphs(Function &F, + std::set &SCCFunctions){ + DSGraph &Graph = getDSGraph(F); + DEBUG(std::cerr << " [BU] Inlining Non-SCC graphs for: " + << F.getName() << "\n"); + + // Move our call site list into TempFCs so that inline call sites go into the + // new call site list and doesn't invalidate our iterators! + std::vector TempFCs; + std::vector &AuxCallsList = Graph.getAuxFunctionCalls(); + TempFCs.swap(AuxCallsList); + + // Loop over all of the resolvable call sites + unsigned LastCallSiteIdx = ~0U; + for (CallSiteIterator I = CallSiteIterator::begin(TempFCs), + E = CallSiteIterator::end(TempFCs); I != E; ++I) { + // If we skipped over any call sites, they must be unresolvable, copy them + // to the real call site list. + LastCallSiteIdx++; + for (; LastCallSiteIdx < I.getCallSiteIdx(); ++LastCallSiteIdx) + AuxCallsList.push_back(TempFCs[LastCallSiteIdx]); + LastCallSiteIdx = I.getCallSiteIdx(); + + // Resolve the current call... + Function *Callee = *I; + DSCallSite &CS = I.getCallSite(); + + if (Callee->isExternal()) { + // Ignore this case, simple varargs functions we cannot stub out! + } else if (SCCFunctions.count(Callee)) { + // Calling a function in the SCC, ignore it for now! + DEBUG(std::cerr << " SCC CallSite for: " << Callee->getName() << "\n"); + AuxCallsList.push_back(CS); + } else { + // Get the data structure graph for the called function. + // + DSGraph &GI = getDSGraph(*Callee); // Graph to inline + + DEBUG(std::cerr << " Inlining graph for " << Callee->getName() + << " in: " << F.getName() << "[" << GI.getGraphSize() << "+" + << GI.getAuxFunctionCalls().size() << "]\n"); + + // Handle self recursion by resolving the arguments and return value + Graph.mergeInGraph(CS, GI, DSGraph::StripAllocaBit | + DSGraph::DontCloneCallNodes); + } + } + + // Make sure to catch any leftover unresolvable calls... + for (++LastCallSiteIdx; LastCallSiteIdx < TempFCs.size(); ++LastCallSiteIdx) + AuxCallsList.push_back(TempFCs[LastCallSiteIdx]); + + TempFCs.clear(); + + // Recompute the Incomplete markers. If there are any function calls left + // now that are complete, we must loop! + Graph.maskIncompleteMarkers(); + Graph.markIncompleteNodes(); + Graph.removeDeadNodes(); + + DEBUG(std::cerr << " [BU] Done Non-SCC inlining: " << F.getName() << " [" + << Graph.getGraphSize() << "+" << Graph.getAuxFunctionCalls().size() + << "]\n"); + + //Graph.writeGraphToFile(std::cerr, "bu_" + F.getName()); + + return Graph; +} + + DSGraph &BUDataStructures::calculateSCCGraph(Function &F, - std::set &InlinedSCCFunctions) { + std::set &SCCFunctions){ DSGraph &Graph = getDSGraph(F); DEBUG(std::cerr << " [BU] Calculating SCC graph for: " << F.getName()<<"\n"); @@ -391,7 +491,7 @@ Graph.mergeInGraph(CS, GI, DSGraph::StripAllocaBit | DSGraph::DontCloneCallNodes); - if (InlinedSCCFunctions.count(Callee)) + if (SCCFunctions.count(Callee)) SCCCallSiteMap.insert(std::make_pair(Callee, CS)); } } From lattner at cs.uiuc.edu Tue Nov 12 10:08:03 2002 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Tue Nov 12 10:08:03 2002 Subject: [llvm-commits] CVS: llvm/www/docs/DSGraphStatus.html Message-ID: <200211121607.KAA27484@tank.cs.uiuc.edu> Changes in directory llvm/www/docs: DSGraphStatus.html updated: 1.12 -> 1.13 --- Log message: Add new numbers --- Diffs of the changes: Index: llvm/www/docs/DSGraphStatus.html diff -u llvm/www/docs/DSGraphStatus.html:1.12 llvm/www/docs/DSGraphStatus.html:1.13 --- llvm/www/docs/DSGraphStatus.html:1.12 Tue Nov 12 00:53:43 2002 +++ llvm/www/docs/DSGraphStatus.html Tue Nov 12 10:06:51 2002 @@ -9,16 +9,78 @@ were taking too long (time listed show how long I waited).

Fields that appear in bold have changes from the last entry on the page. -Floating point entries are only highlighted if they double or half their -previous value.

+Floating point entries are only highlighted if they change significantly from +their previous value.

+ +

+

Nov 12, 2002:

+ +This +small change is important to programs with large SCC's. It basically makes +sure to inline calls to non-scc functions before we inline any intra-scc +calls. The problem is that inlining an SCC call could add more call +sites that would slow things down.

+ +Note that the total time underestimates the improvement. Take a look at the +change on BU time/total time to get an accurate accessment. I had some of the +graph IO printing code commented out in the last run, which affected Analyze +time, but not total time.

+ +

+Name:                     Anlyz: LocTime: BUTime:  TDTime:  TotTime: BCTime:      LocSize: BUSize:  TDSize:  TotSize: BCSize:    NumFold  NumNodes   main   __main GlobGr
+254.gap.lib                17.69 0.8298   4.1158   2.4087   8.9138   2.9912   |   2024984  2840288  2024560  6889832  16554904 |    5985  24035+3950 44+9   0+0    0+0    
+255.vortex.lib             14.99 0.5988   1.8871   3.6557   7.3284   2.4054   |   1381056  1259144  1997120  4637320  11689312 |    5853  7328+2841  166+11 0+0    0+0    
+300.twolf.lib               3.34 0.2774   0.2827   0.5115   1.5475   1.0153   |   466528   391512   396552   1254592  6936728  |    749   4128+784   90+53  0+0    0+0    
+197.parser.lib              1.85 0.1485   0.3190   0.2156   0.8689   0.6872   |   408392   225184   212552   965384   4447944  |    1343  2257+707   14+6   0+0    0+0    
+burg.llvm.lib               1.22 0.1027   0.1926   0.1739   0.5598   0.4947   |   530600   474592   185792   1190984  3040208  |    758   2273+576   45+7   0+0    0+0    
+164.gzip.llvm.lib           0.74 0.0398   0.0559   0.0350   0.1957   0.4561   |   145952   184776   70872    499912   1876248  |    24    971+87     8+2    0+0    0+0    
+optimizer-eval.llvm.lib     0.43 0.0183   0.0485   0.2054   0.3047   0.0839   |   101184   79456    61760    242400   624688   |    *     309+41     72+27  0+0    0+0    
+256.bzip2.lib               0.34 0.0241   0.0404   0.0113   0.1250   0.1624   |   139504   83400    39712    335144   1373216  |    *     563+37     8+2    0+0    0+0    
+181.mcf.lib                 0.23 0.0216   0.0279   0.0301   0.1126   0.0795   |   115448   146520   43680    322864   589440   |    166   388+51     22+10  0+0    0+0    
+sim.llvm.lib                0.20 0.0137   0.0138   0.0131   0.0800   0.0876   |   81632    51496    21872    226584   734152   |    *     260+35     39+22  0+0    0+0    
+voronoi.llvm.lib            0.17 0.0139   0.0246   0.0282   0.0811   0.0591   |   79824    84152    27112    204904   420568   |    18    299+77     15+8   0+0    0+0    
+sgefa.llvm.lib              0.16 0.0090   0.0195   0.0201   0.0848   0.0542   |   85688    100456   67024    277864   368680   |    *     130+24     24+14  0+0    0+0    
+bh.llvm.lib                 0.16 0.0121   0.0164   0.0115   0.0581   0.0682   |   75000    51080    27760    217632   470720   |    61    194+35     6+2    0+0    0+0    
+power.llvm.lib              0.13 0.0044   0.0122   0.0037   0.0282   0.0484   |   27776    17688    18144    71424    213760   |    *     81+18      11+2   0+0    0+0    
+em3d.llvm.lib               0.11 0.0060   0.0110   0.0059   0.0308   0.0561   |   33040    36256    13008    90632    227520   |    1     178+28     12+4   0+0    0+0    
+health.llvm.lib             0.10 0.0052   0.0203   0.0073   0.0406   0.0421   |   30632    31432    12704    89592    199888   |    18    97+31      12+4   0+0    0+0    
+tsp.llvm.lib                0.07 0.0051   0.0063   0.0027   0.0217   0.0332   |   18232    14336    4920     51888    180744   |    21    43+15      8+4    0+0    0+0    
+mst.llvm.lib                0.07 0.0040   0.0065   0.0037   0.0215   0.0296   |   18624    25576    7040     65808    178832   |    10    97+15      12+3   0+0    0+0    
+lists.llvm.lib              0.07 0.0043   0.0131   0.0071   0.0299   0.0269   |   24552    16920    14440    68024    141480   |    30    67+26      3+1    0+0    0+0    
+fib2.llvm.lib               0.07 0.0053   0.0217   0.0008   0.0313   0.0076   |   7960     6288     1640     28408    42256    |    *     21+5       8+3    0+0    0+0    
+perimeter.llvm.lib          0.06 0.0031   0.0064   0.0021   0.0190   0.0275   |   15016    14192    3936     45912    156352   |    *     35+15      7+4    0+0    0+0    
+hash.llvm.lib               0.06 0.0031   0.0050   0.0052   0.0200   0.0211   |   25728    16608    8208     63576    151680   |    *     117+17     14+6   0+0    0+0    
+bisort.llvm.lib             0.06 0.0030   0.0055   0.0019   0.0318   0.0126   |   13288    11408    3712     39448    127360   |    *     35+13      7+4    0+0    0+0    
+sumarraymalloc.llvm.lib     0.04 0.0009   0.0014   0.0009   0.0075   0.0240   |   7040     2672     2048     25872    54352    |    *     23+5       7+4    0+0    0+0    
+objinst.llvm.lib            0.04 0.0019   0.0050   0.0032   0.0154   0.0100   |   11280    15784    4112     45296    89856    |    34    45+14      16+10  0+0    0+0    
+methcall.llvm.lib           0.04 0.0018   0.0047   0.0031   0.0145   0.0122   |   11008    9880     3928     38624    87976    |    30    43+12      14+8   0+0    0+0    
+matrix.llvm.lib             0.04 0.0013   0.0021   0.0014   0.0106   0.0198   |   8808     8872     3072     33144    69112    |    *     38+9       12+8   0+0    0+0    
+llubenchmark.llvm.lib       0.04 0.0024   0.0026   0.0015   0.0142   0.0118   |   11072    11760    2624     36480    124344   |    *     31+7       15+5   0+0    0+0    
+heapsort.llvm.lib           0.04 0.0009   0.0019   0.0007   0.0073   0.0137   |   2856     6968     2008     26976    63160    |    *     26+3       7+2    0+0    0+0    
+ary3.llvm.lib               0.04 0.0013   0.0020   0.0011   0.0090   0.0134   |   10240    13104    10888    45832    73064    |    6     44+5       12+3   0+0    0+0    
+ackermann.llvm.lib          0.04 0.0007   0.0015   0.0004   0.0066   0.0262   |   1744     5728     1200     22056    46448    |    *     13+2       3+1    0+0    0+0    
+treeadd.llvm.lib            0.03 0.0015   0.0028   0.0010   0.0090   0.0084   |   3856     7384     2200     29784    72064    |    *     25+7       6+3    0+0    0+0    
+sieve.llvm.lib              0.03 0.0008   0.0012   0.0006   0.0061   0.0162   |   2176     6176     1632     23432    216840   |    *     22+2       12+1   0+0    0+0    
+random.llvm.lib             0.03 0.0008   0.0017   0.0004   0.0059   0.0133   |   2056     5720     1320     22080    45264    |    *     15+2       3+1    0+0    0+0    
+matrixTranspose.llvm.lib    0.03 0.0005   0.0010   0.0003   0.0032   0.0129   |   4272     1144     736      8560     68448    |    *     8+1        5+1    0+0    0+0    
+hello.llvm.lib              0.03 0.0004   0.0015   0.0001   0.0066   0.0107   |   752      2952     472      6512     14160    |    *     2+0        0+0    0+0    0+0    
+sumarray2d.llvm.lib         0.02 0.0005   0.0009   0.0002   0.0034   0.0055   |   1568     3584     848      8264     23288    |    *     10+1       7+1    0+0    0+0    
+printargs.llvm.lib          0.02 0.0004   0.0013   0.0002   0.0032   0.0058   |   1240     1048     696      5128     19160    |    *     6+1        4+1    0+0    0+0    
+pi.llvm.lib                 0.02 0.0008   0.0021   0.0005   0.0052   0.0036   |   5392     1560     1392     8344     36032    |    *     17+2       13+2   0+0    0+0    
+indvars.llvm.lib            0.02 0.0006   0.0010   0.0003   0.0037   0.0036   |   4744     1072     4208     12544    31336    |    *     13+1       8+1    0+0    0+0    
+sumarray.llvm.lib           0.01 0.0004   0.0008   0.0002   0.0026   0.0029   |   904      3192     624      4720     15152    |    *     6+1        4+1    0+0    0+0    
+

Nov 11, 2002 #2:

-This is the result after fixing some major bugs. The globals list was supposed -to be kept sorted, but there was one minor, tiny, little, bug that caused it to -get screwed up sometimes. This caused vortex to explode, fixing it gets things -back in control where you'd expect. Viola.

+This is the result after fixing +some major bugs. The globals list was supposed to be kept sorted, but there +was one minor, tiny, little, bug that caused it to get screwed up sometimes. +This caused vortex to explode, fixing it gets things back in control where you'd +expect. Viola.

This also includes a merging bug that caused some things to be merged and some other things to happen when they shouldn't, which accounts for folding @@ -646,7 +708,7 @@

Chris Lattner
-Last modified: Tue Nov 12 00:49:40 CST 2002 +Last modified: Tue Nov 12 10:06:27 CST 2002 From brukman at neo.cs.uiuc.edu Tue Nov 12 20:39:01 2002 From: brukman at neo.cs.uiuc.edu (Misha Brukman) Date: Tue Nov 12 20:39:01 2002 Subject: [llvm-commits] CVS: llvm/lib/Reoptimizer/BinInterface/sparc9.h Message-ID: <200211130240.gAD2eAW04168@neo.cs.uiuc.edu> Changes in directory llvm/lib/Reoptimizer/BinInterface: sparc9.h updated: 1.3 -> 1.4 --- Log message: Manually converted the binary constants to hex, this way we don't need to have a preprocessor for it (is that some Windows thing?). The original binary codes are left in comments, digits grouped in fours to easily check if I went wrong somewhere. Feel free to triple check as I only double-checked it. :) --- Diffs of the changes: Index: llvm/lib/Reoptimizer/BinInterface/sparc9.h diff -u llvm/lib/Reoptimizer/BinInterface/sparc9.h:1.3 llvm/lib/Reoptimizer/BinInterface/sparc9.h:1.4 --- llvm/lib/Reoptimizer/BinInterface/sparc9.h:1.3 Fri Nov 8 04:38:13 2002 +++ llvm/lib/Reoptimizer/BinInterface/sparc9.h Tue Nov 12 20:40:00 2002 @@ -1,22 +1,22 @@ -//***************************************************************************** +//===-----------------------------------------------------------*- C++ -*--===// // -// Portable SPARC v9 Machine Code Definition Header +// Portable SPARC v9 Machine Code Definition Header // // // 2002 Cameron Buschardt -//***************************************************************************** +//===----------------------------------------------------------------------===// //********************************* -// Bitfield manipulation Macros +// Bitfield manipulation Macros //********************************* #define FLD_UPPER(FLD_DEF) (1 ? FLD_DEF) #define FLD_LOWER(FLD_DEF) (0 ? FLD_DEF) -#define MASKBELOW(V) ((1 << V) | ((1 << V) - 1)) //masks off everything ABOVE +#define MASKBELOW(V) ((1 << V) | ((1 << V) - 1)) //masks off everything ABOVE #define RD_FLD(x, FLD) ((x & MASKBELOW(FLD_UPPER(FLD))) >> FLD_LOWER(FLD)) #define MK_FLD(FLD, val) ((val << FLD_LOWER(FLD)) & MASKBELOW(FLD_UPPER(FLD))) //********************************** -// Portable sign extend macros +// Portable sign extend macros //********************************** #define SIGN_EXTEND13(x) (x & 0x1000 ? -(-x & 0x1FFF): x) #define SIGN_EXTEND(x, bits) (x & (1 << (bits-1)) ? -(-x & ((1 << bits)-1)):x) @@ -24,46 +24,46 @@ //********************************** // Instruction bitfield definitions //********************************** -#define INSTR_OP 31:30 -#define INSTR_A 29:29 -#define INSTR_FCN 29:25 -#define INSTR_DISP30 29:0 -#define INSTR_COND_H 28:25 -#define INSTR_RCOND_H 27:25 -#define INSTR_CC1_H 26:26 -#define INSTR_CC0_H 25:25 -#define INSTR_OP2 24:22 -#define INSTR_OP3 24:19 -#define INSTR_CC1_L 21:21 -#define INSTR_D16HI 21:20 -#define INSTR_D16LO 13:0 -#define INSTR_IMM22 21:0 -#define INSTR_DISP22 21:0 -#define INSTR_CC0_L 20:20 -#define INSTR_P 19:19 -#define INSTR_CC2 18:18 -#define INSTR_DISP19 18:0 -#define INSTR_IMPLDEP 18:0 -#define INSTR_COND_L 17:14 -#define INSTR_I 13:13 -#define INSTR_OPFCC 13:11 -#define INSTR_OPF 13:5 -#define INSTR_X 12:12 -#define INSTR_RCOND_L 12:10 -#define INSTR_IMMASI 12:5 -#define INSTR_SIMM13 12:0 -#define INSTR_OPFLOW_B 10:5 -#define INSTR_OPFLOW_S 9:5 -#define INSTR_SIMM10 9:0 -#define INSTR_CMASK 6:4 -#define INSTR_SWTRAP 6:0 -#define INSTR_SHCNT64 5:0 -#define INSTR_SHCNT32 4:0 -#define INSTR_MMASK 3:0 - -#define INSTR_RS1 18:14 -#define INSTR_RS2 4:0 -#define INSTR_RD 29:25 +#define INSTR_OP 31:30 +#define INSTR_A 29:29 +#define INSTR_FCN 29:25 +#define INSTR_DISP30 29:0 +#define INSTR_COND_H 28:25 +#define INSTR_RCOND_H 27:25 +#define INSTR_CC1_H 26:26 +#define INSTR_CC0_H 25:25 +#define INSTR_OP2 24:22 +#define INSTR_OP3 24:19 +#define INSTR_CC1_L 21:21 +#define INSTR_D16HI 21:20 +#define INSTR_D16LO 13:0 +#define INSTR_IMM22 21:0 +#define INSTR_DISP22 21:0 +#define INSTR_CC0_L 20:20 +#define INSTR_P 19:19 +#define INSTR_CC2 18:18 +#define INSTR_DISP19 18:0 +#define INSTR_IMPLDEP 18:0 +#define INSTR_COND_L 17:14 +#define INSTR_I 13:13 +#define INSTR_OPFCC 13:11 +#define INSTR_OPF 13:5 +#define INSTR_X 12:12 +#define INSTR_RCOND_L 12:10 +#define INSTR_IMMASI 12:5 +#define INSTR_SIMM13 12:0 +#define INSTR_OPFLOW_B 10:5 +#define INSTR_OPFLOW_S 9:5 +#define INSTR_SIMM10 9:0 +#define INSTR_CMASK 6:4 +#define INSTR_SWTRAP 6:0 +#define INSTR_SHCNT64 5:0 +#define INSTR_SHCNT32 4:0 +#define INSTR_MMASK 3:0 + +#define INSTR_RS1 18:14 +#define INSTR_RS2 4:0 +#define INSTR_RD 29:25 #define RD_D16(i) ((RD_FLD(i, INSTR_D16HI) << 14) | RD_FLD(i, INSTR_D16LO)) @@ -72,96 +72,99 @@ //********************************** // Op-code classification //********************************** -#define OP_CALL 0b01 -#define OP_BRANCH 0b00 -#define OP_2 0b10 -#define OP_3 0b11 +#define OP_BRANCH 0x0 // 0b00 +#define OP_CALL 0x1 // 0b01 +#define OP_2 0x2 // 0b10 +#define OP_3 0x3 // 0b11 //********************************** // Branch Class Instructions //********************************** -#define OP2_ILLTRAP 0b000 //OP=OP_BRANCH -#define OP2_NOP 0b100 //BRANCH -#define OP2_SETHI 0b100 //BRANCH - uhh? duplicate? DOH =p -#define OP2_BICC 0b010 -#define OP2_BPR 0b011 -#define OP2_FB 0b110 -#define OP2_FBP 0b101 +#define OP2_ILLTRAP 0x0 // 0b000 //OP=OP_BRANCH +#define OP2_BICC 0x2 // 0b010 +#define OP2_BPR 0x3 // 0b011 +#define OP2_NOP 0x4 // 0b100 //BRANCH +#define OP2_SETHI 0x4 // 0b100 //BRANCH - uhh? duplicate? DOH =p +#define OP2_FBP 0x5 // 0b101 +#define OP2_FB 0x6 // 0b110 //********************************** // Register Condition Codes //********************************** -#define RCOND_RZ 0b001 -#define RCOND_RLEZ 0b010 -#define RCOND_RNZ 0b101 -#define RCOND_RGZ 0b110 -#define RCOND_RGEZ 0b111 +#define RCOND_RZ 0x1 // 0b001 +#define RCOND_RLEZ 0x2 // 0b010 +#define RCOND_RNZ 0x5 // 0b101 +#define RCOND_RGZ 0x6 // 0b110 +#define RCOND_RGEZ 0x7 // 0b111 //********************************** // FPU Branch Conditions //********************************** -#define COND_FBN 0b0000 -#define COND_FBNE 0b0001 -#define COND_FBLG 0b0010 -#define COND_FBUL 0b0011 -#define COND_FBL 0b0100 -#define COND_FBUG 0b0101 -#define COND_FBG 0b0110 -#define COND_FBU 0b0111 -#define COND_FBA 0b1000 -#define COND_FBE 0b1001 -#define COND_FBUE 0b1010 -#define COND_FBGE 0b1011 -#define COND_FBUGE 0b1100 -#define COND_FBLE 0b1101 -#define COND_FBULE 0b1110 -#define COND_FBO 0b1111 +#define COND_FBN 0x0 // 0b0000 +#define COND_FBNE 0x1 // 0b0001 +#define COND_FBLG 0x2 // 0b0010 +#define COND_FBUL 0x3 // 0b0011 +#define COND_FBL 0x4 // 0b0100 +#define COND_FBUG 0x5 // 0b0101 +#define COND_FBG 0x6 // 0b0110 +#define COND_FBU 0x7 // 0b0111 +#define COND_FBA 0x8 // 0b1000 +#define COND_FBE 0x9 // 0b1001 +#define COND_FBUE 0xa // 0b1010 +#define COND_FBGE 0xb // 0b1011 +#define COND_FBUGE 0xc // 0b1100 +#define COND_FBLE 0xd // 0b1101 +#define COND_FBULE 0xe // 0b1110 +#define COND_FBO 0xf // 0b1111 //********************************** // Integer Branch Conditions //********************************** -#define COND_BN 0b0000 -#define COND_BE 0b0001 -#define COND_BLE 0b0010 -#define COND_BL 0b0011 -#define COND_BLEU 0b0100 -#define COND_BCS 0b0101 -#define COND_BNEG 0b0110 -#define COND_BVS 0b0111 -#define COND_BA 0b1000 -#define COND_BNE 0b1001 -#define COND_BG 0b1010 -#define COND_BGE 0b1011 -#define COND_BGU 0b1100 -#define COND_BCC 0b1101 -#define COND_BPOS 0b1110 -#define COND_BVC 0b1111 +#define COND_BN 0x0 // 0b0000 +#define COND_BE 0x1 // 0b0001 +#define COND_BLE 0x2 // 0b0010 +#define COND_BL 0x3 // 0b0011 +#define COND_BLEU 0x4 // 0b0100 +#define COND_BCS 0x5 // 0b0101 +#define COND_BNEG 0x6 // 0b0110 +#define COND_BVS 0x7 // 0b0111 +#define COND_BA 0x8 // 0b1000 +#define COND_BNE 0x9 // 0b1001 +#define COND_BG 0xa // 0b1010 +#define COND_BGE 0xb // 0b1011 +#define COND_BGU 0xc // 0b1100 +#define COND_BCC 0xd // 0b1101 +#define COND_BPOS 0xe // 0b1110 +#define COND_BVC 0xf // 0b1111 //********************************** // Name Lookup tables // index is Condition code //********************************** -static char * fcond_names[] = {"FBN","FBNE","FBLG","FBUL","FBL","FBUG","FBG","FBU","FBA","FBE", - "FBUE","FBGE","FBUGE","FBLE","FBULE","FBO"}; +static char * fcond_names[] = + { "FBN", "FBNE", "FBLG", "FBUL", "FBL", "FBUG", "FBG", "FBU", + "FBA", "FBE", "FBUE", "FBGE", "FBUGE", "FBLE", "FBULE","FBO" }; + +static char * icond_names[] = + { "BN", "BE", "BLE", "BL", "BLEU", "BCS", "BNEG", "BVS", + "BA", "BNE", "BG", "BGE", "BGU", "BCC", "BPOS", "BVC"}; -static char * icond_names[] = {"BN","BE","BLE","BL","BLEU","BCS","BNEG","BVS","BA","BNE","BG","BGE", - "BGU","BCC","BPOS","BVC"}; - -static char * rcond_names[] = {"r000", "RZ", "RLEZ", "r011", "r100", "RNZ", "RGZ", "RGEZ"}; +static char * rcond_names[] = + { "r000", "RZ", "RLEZ", "r011", "r100", "RNZ", "RGZ", "RGEZ" }; //********************************** // Flag register encoding //********************************** -#define FLAG_FCC0 0b000 -#define FLAG_FCC1 0b001 -#define FLAG_FCC2 0b010 -#define FLAG_FCC3 0b011 -#define FLAG_ICC 0b100 -#define FLAG_XCC 0b110 +#define FLAG_FCC0 0x0 // 0b000 +#define FLAG_FCC1 0x1 // 0b001 +#define FLAG_FCC2 0x2 // 0b010 +#define FLAG_FCC3 0x3 // 0b011 +#define FLAG_ICC 0x4 // 0b100 +#define FLAG_XCC 0x6 // 0b110 //********************************** // OP_2 class instructions @@ -169,143 +172,145 @@ // present members: // RD, OP3, RS1 // if I=0 -// RS2 +// RS2 // else -// SIMM13 +// SIMM13 //********************************** -#define OP3_ADD 0b000000 -#define OP3_ADDC 0b001000 -#define OP3_AND 0b000001 -#define OP3_OR 0b000010 -#define OP3_XOR 0b000011 -#define OP3_SUB 0b000100 -#define OP3_ANDN 0b000101 -#define OP3_ORN 0b000110 -#define OP3_XNOR 0b000111 -#define OP3_SUBC 0b001100 -#define OP3_ADDcc 0b010000 -#define OP3_ADDCcc 0b011000 -#define OP3_ANDcc 0b010001 -#define OP3_ORcc 0b010010 -#define OP3_XORcc 0b010011 -#define OP3_SUBcc 0b010100 -#define OP3_ANDNcc 0b010101 -#define OP3_ORNcc 0b010110 -#define OP3_XNORcc 0b010111 -#define OP3_SUBCcc 0b011100 -#define OP3_MULX 0b001001 -#define OP3_SDIVX 0b101101 -#define OP3_UDIVX 0b001101 +#define OP3_ADD 0x0 // 0b00 0000 +#define OP3_ADDC 0x8 // 0b00 1000 +#define OP3_AND 0x1 // 0b00 0001 +#define OP3_OR 0x2 // 0b00 0010 +#define OP3_XOR 0x3 // 0b00 0011 +#define OP3_SUB 0x4 // 0b00 0100 +#define OP3_ANDN 0x5 // 0b00 0101 +#define OP3_ORN 0x6 // 0b00 0110 +#define OP3_XNOR 0x7 // 0b00 0111 +#define OP3_SUBC 0xc // 0b00 1100 +#define OP3_ADDcc 0x10 // 0b01 0000 +#define OP3_ADDCcc 0x18 // 0b01 1000 +#define OP3_ANDcc 0x11 // 0b01 0001 +#define OP3_ORcc 0x12 // 0b01 0010 +#define OP3_XORcc 0x13 // 0b01 0011 +#define OP3_SUBcc 0x14 // 0b01 0100 +#define OP3_ANDNcc 0x15 // 0b01 0101 +#define OP3_ORNcc 0x16 // 0b01 0110 +#define OP3_XNORcc 0x17 // 0b01 0111 +#define OP3_SUBCcc 0x1c // 0b01 1100 +#define OP3_MULX 0x9 // 0b00 1001 +#define OP3_SDIVX 0x2d // 0b10 1101 +#define OP3_UDIVX 0xd // 0b00 1101 //Op3 members -#define OP3_CASA 0b111100 -#define OP3_CASXA 0b111110 +#define OP3_CASA 0x3c // 0b11 1100 +#define OP3_CASXA 0x3e // 0b11 1110 //Instructions below generated with: //OP=OP_2: RD, OP_3 RS1: {I=0 -> X & RS2 ,I=1 -> {X=0 -> SHCNT32 X=1->SHCNT64 }} -#define OP3_SLL 0b100101 -#define OP3_SRL 0b100110 -#define OP3_SRA 0b100111 +#define OP3_SLL 0x25 // 0b10 0101 +#define OP3_SRL 0x26 // 0b10 0110 +#define OP3_SRA 0x27 // 0b10 0111 // class OP_3 -#define OP3_STFA 0b110100 -#define OP3_STDFA 0b110111 -#define OP3_STQFA 0b110110 +#define OP3_STFA 0x34 // 0b11 0100 +#define OP3_STDFA 0x37 // 0b11 0111 +#define OP3_STQFA 0x36 // 0b11 0110 //Instructions below generated with: //OP=OP_2: FCN -#define OP3_DONERETRY 0b111110 -#define FCN_DONE 0 -#define FCN_RETRY 1 +#define OP3_DONERETRY 0x3e // 0b11 1110 +#define FCN_DONE 0 +#define FCN_RETRY 1 //These masks are valid for the instructions below -#define OPF_MASK_ONs 0b0001 //these are valid for 'n' field -#define OPF_MASK_ONd 0b0010 -#define OPF_MASK_ONq 0b0011 -#define OPF_MASK_TOs 0b0100 //these are valid for 't' field -#define OPF_MASK_TOd 0b1000 -#define OPF_MASK_TOq 0b1100 +#define OPF_MASK_ONs 0x1 // 0b0001 //these are valid for 'n' field +#define OPF_MASK_ONd 0x2 // 0b0010 +#define OPF_MASK_ONq 0x3 // 0b0011 +#define OPF_MASK_TOs 0x4 // 0b0100 //these are valid for 't' field +#define OPF_MASK_TOd 0x8 // 0b1000 +#define OPF_MASK_TOq 0xc // 0b1100 -#define OPF_MASK_ON 0b0011 -#define OPF_MASK_TO 0b1100 +#define OPF_MASK_ON 0x3 // 0b0011 +#define OPF_MASK_TO 0xc // 0b1100 //Instructions below generated with //OP=OP_2: CC1_H, CC0_H, RS1, OPF, RS2 -#define OP3_FCMP 0b110101 -#define OPF_FCMPn 0b001010000 -#define OPF_FCMPEn 0b001010100 +#define OP3_FCMP 0x35 // 0b 11 0101 +#define OPF_FCMPn 0x50 // 0b0 0101 0000 +#define OPF_FCMPEn 0x54 // 0b0 0101 0100 //Instructions below generated with //OP=OP_2: RD, OP3 RS1, OPF, RS2 -#define OP3_FPU 0b110100 -#define OPF_FADDn 0b001000000 -#define OPF_FSUBn 0b001000100 -#define OPF_FMOVn 0b000000000 -#define OPF_FNEGn 0b000000100 -#define OPF_FABSn 0b000001000 -#define OPF_FMULn 0b001001000 -#define OPF_FDIVn 0b001001100 -#define OPF_FSQRTn 0b000101000 -#define OPF_FsTOx 0b010000001 -#define OPF_FsTOi 0b011010001 -#define OPF_FsTOd 0b011001001 -#define OPF_FsTOq 0b011001101 -#define OPF_FdTOx 0b010000010 -#define OPF_FdTOi 0b011010010 -#define OPF_FdTOs 0b011000110 -#define OPF_FdTOq 0b011001110 -#define OPF_FqTOx 0b010000011 -#define OPF_FqTOi 0b011010011 -#define OPF_FqTOs 0b011000111 -#define OPF_FqTOd 0b011001011 -#define OPF_FxTOt 0b010000000 -#define OPF_FiTOt 0b011000000 -#define OPF_FsMULd 0b001101001 -#define OPF_FdMULq 0b001101110 - - -#define OP3_FLUSH 0b111011 //OP=OP_2 RS1 {I=0 -> rs2, I=1->simm13} -#define OP3_FLUSHW 0b101011 //OP=OP_2 I = 0 -#define OP3_JMPL 0b111000 //OP=OP_2 RD, RS1 {I=0-> RS2, I=1->SIMM13} -#define OP3_LDFA 0b110000 //OP=OP_3 RD, Rs1, {I=0->IMM_ASI, RS2 I=1->SIMM13} -#define OP3_LDDFA 0b110011 //OP=OP_3 RD, Rs1, {I=0->IMM_ASI, RS2 I=1->SIMM13} -#define OP3_LDQFA 0b110010 //OP=OP_3 RD, Rs1, {I=0->IMM_ASI, RS2 I=1->SIMM13} - -#define OP3_LDSTUB 0b001101 //OP=OP_3 RD, Rs1 {I=0->RS2, I=1->SIMM13} -#define OP3_STB 0b000101 -#define OP3_STH 0b000110 -#define OP3_STW 0b000100 -#define OP3_STX 0b000111 -#define OP3_LDSB 0b001001 -#define OP3_LDSH 0b001010 -#define OP3_LDSW 0b001000 -#define OP3_LDUB 0b000001 -#define OP3_LDUH 0b000010 -#define OP3_LDUW 0b000000 -#define OP3_LDX 0b001011 - - - -#define OP3_LDSTUBA 0b011101 //OP=OP_3 RD, RS1 {I=0->RS2, IMM_ASI, I=1->SIMM13} - -#define OP3_MEMBAR 0b101000 //OP=OP_2 CMASK, MMASK //WTF?!?! some bits get set +#define OP3_FPU 0x34 // 0b 11 0100 +#define OPF_FADDn 0x40 // 0b0 0100 0000 +#define OPF_FSUBn 0x44 // 0b0 0100 0100 +#define OPF_FMOVn 0x0 // 0b0 0000 0000 +#define OPF_FNEGn 0x4 // 0b0 0000 0100 +#define OPF_FABSn 0x8 // 0b0 0000 1000 +#define OPF_FMULn 0x48 // 0b0 0100 1000 +#define OPF_FDIVn 0x4c // 0b0 0100 1100 +#define OPF_FSQRTn 0x28 // 0b0 0010 1000 +#define OPF_FsTOx 0x81 // 0b0 1000 0001 +#define OPF_FsTOi 0xd1 // 0b0 1101 0001 +#define OPF_FsTOd 0xc9 // 0b0 1100 1001 +#define OPF_FsTOq 0xcd // 0b0 1100 1101 +#define OPF_FdTOx 0x82 // 0b0 1000 0010 +#define OPF_FdTOi 0xd2 // 0b0 1101 0010 +#define OPF_FdTOs 0xc6 // 0b0 1100 0110 +#define OPF_FdTOq 0xce // 0b0 1100 1110 +#define OPF_FqTOx 0x83 // 0b0 1000 0011 +#define OPF_FqTOi 0xd3 // 0b0 1101 0011 +#define OPF_FqTOs 0xc7 // 0b0 1100 0111 +#define OPF_FqTOd 0xcb // 0b0 1100 1011 +#define OPF_FxTOt 0x80 // 0b0 1000 0000 +#define OPF_FiTOt 0xc0 // 0b0 1100 0000 +#define OPF_FsMULd 0x69 // 0b0 0110 1001 +#define OPF_FdMULq 0x6e // 0b0 0110 1110 + + +#define OP3_FLUSH 0x3b // 0b11 1011 //OP=OP_2 RS1 {I=0 -> rs2, I=1->simm13} +#define OP3_FLUSHW 0x2b // 0b10 1011 //OP=OP_2 I = 0 +#define OP3_JMPL 0x38 // 0b11 1000 //OP=OP_2 RD, RS1 {I=0-> RS2, I=1->SIMM13} +//OP=OP_3 RD, Rs1, {I=0->IMM_ASI, RS2 I=1->SIMM13} +#define OP3_LDFA 0x30 // 0b11 0000 +//OP=OP_3 RD, Rs1, {I=0->IMM_ASI, RS2 I=1->SIMM13} +#define OP3_LDDFA 0x33 // 0b11 0011 +//OP=OP_3 RD, Rs1, {I=0->IMM_ASI, RS2 I=1->SIMM13} +#define OP3_LDQFA 0x32 // 0b11 0010 + +#define OP3_LDSTUB 0xd // 0b00 1101 //OP=OP_3 RD, Rs1 {I=0->RS2, I=1->SIMM13} +#define OP3_STB 0x5 // 0b00 0101 +#define OP3_STH 0x6 // 0b00 0110 +#define OP3_STW 0x4 // 0b00 0100 +#define OP3_STX 0x7 // 0b00 0111 +#define OP3_LDSB 0x9 // 0b00 1001 +#define OP3_LDSH 0xa // 0b00 1010 +#define OP3_LDSW 0x8 // 0b00 1000 +#define OP3_LDUB 0x1 // 0b00 0001 +#define OP3_LDUH 0x2 // 0b00 0010 +#define OP3_LDUW 0x0 // 0b00 0000 +#define OP3_LDX 0xb // 0b00 1011 + + +//OP=OP_3 RD, RS1 {I=0->RS2, IMM_ASI, I=1->SIMM13} +#define OP3_LDSTUBA 0x1d // 0b01 1101 +//OP=OP_2 CMASK, MMASK //WTF?!?! some bits get set +#define OP3_MEMBAR 0x28 // 0b10 1000 //These two instructions are FUNKY as hell -#define OP3_FMOVcc 0b110101 //OP=OP_2 RD, COND, OPF_CC, OPF_LOW, RS2 -#define OP3_MOVcc 0b101100 // - +#define OP3_FMOVcc 0x35 // 0b11 0101 //OP=OP_2 RD, COND, OPF_CC, OPF_LOW, RS2 +#define OP3_MOVcc 0x2c // 0b10 1100 // -#define OP3_POPC 0b101110 -#define OP3_PREFETCH 0b101101 -#define OP3_PREFETCHA 0b111101 -#define OP3_RETURN 0b111001 -#define OP3_SAVE 0b111100 -#define OP3_RESTORE 0b111101 - -#define OP3_SAVDRESTD 0b110001 -#define FCN_SAVED 0 -#define FCN_RESTORED 1 -#define OP3_TRAP 0b111010 //integer trap +#define OP3_POPC 0x2e // 0b10 1110 +#define OP3_PREFETCH 0x2d // 0b10 1101 +#define OP3_PREFETCHA 0x3d // 0b11 1101 +#define OP3_RETURN 0x39 // 0b11 1001 +#define OP3_SAVE 0x3c // 0b11 1100 +#define OP3_RESTORE 0x3d // 0b11 1101 + +#define OP3_SAVDRESTD 0x31 // 0b11 0001 +#define FCN_SAVED 0 +#define FCN_RESTORED 1 +#define OP3_TRAP 0x3a // 0b11 1010 //integer trap From brukman at neo.cs.uiuc.edu Tue Nov 12 20:39:03 2002 From: brukman at neo.cs.uiuc.edu (Misha Brukman) Date: Tue Nov 12 20:39:03 2002 Subject: [llvm-commits] CVS: llvm/lib/Reoptimizer/BinInterface/sparc.cpp Message-ID: <200211130240.gAD2eH004174@neo.cs.uiuc.edu> Changes in directory llvm/lib/Reoptimizer/BinInterface: sparc.cpp updated: 1.2 -> 1.3 --- Log message: * Fixed code layout to not go past 80 chars per line * Removed Windows end-of-line ^M and converted tabs to spaces * Include sparc9.h not sparc9.hp, since I manually preprocessed it * Changed comments at the top to match the rest of LLVM standard --- Diffs of the changes: Index: llvm/lib/Reoptimizer/BinInterface/sparc.cpp diff -u llvm/lib/Reoptimizer/BinInterface/sparc.cpp:1.2 llvm/lib/Reoptimizer/BinInterface/sparc.cpp:1.3 --- llvm/lib/Reoptimizer/BinInterface/sparc.cpp:1.2 Fri Aug 9 14:35:15 2002 +++ llvm/lib/Reoptimizer/BinInterface/sparc.cpp Tue Nov 12 20:38:36 2002 @@ -1,892 +1,1108 @@ +//===-----------------------------------------------------------*- C++ -*--===// +// +// SPARC Disassembler Library +// +// For debugging purposes only: +// +// * some deprecated instructions not supported +// +// This was an insane amount of.. inocous small crud to +// implement. +// Multimedia instructions NOT supported //===----------------------------------------------------------------------===// -// -// SPARC Disassembler Library -// -// For debugging purposes only: -// -// * some deprecated instructions not supported -// -// This was an insane amount of.. inocous small crud to -// implement. -// Multimedia instrctions NOT supported -//===----------------------------------------------------------------------===// - + +#include +#include #include "sparc9.h" -#include -#include - - -void sparc_printbr(unsigned instr) -{ - // look at the OP2 field - if (RD_FLD(instr,INSTR_OP2)==OP2_ILLTRAP) - printf("ILLTRAP .. "); - else if (RD_FLD(instr, INSTR_OP2)==OP2_NOP) - printf("NOP ... "); - else if (RD_FLD(instr, INSTR_OP2)==OP2_SETHI) - printf("SETHI ... "); - else if (RD_FLD(instr, INSTR_OP2)==OP2_BICC) - { - printf("%s (Dep) disp:%08X",icond_names[RD_FLD(instr, INSTR_COND_H)], RD_FLD(instr,INSTR_DISP22)); - } - else if (RD_FLD(instr, INSTR_OP2)==OP2_BPR) - { - //A, RCOND_H, D16HI, P, RS1, D16LO - printf("P%s r%d " , rcond_names[RD_FLD(instr, INSTR_RCOND_H)], RD_FLD(instr, INSTR_RS1)); - } - else{ - printf("Unknown:OP=0b00 OP2 = 0x%04X", RD_FLD(instr, INSTR_OP2)); - } -} - -void sparc_printalu(char * basename , unsigned instr) -{ - // OP=OP_2 : RD, OP3, RS1: {I=0 -> RS2 I=1->SIMM13} - if (RD_FLD(instr, INSTR_I)==0) - printf("%s r%d <- r%d ,r%d",basename, RD_FLD(instr, INSTR_RD),RD_FLD(instr, INSTR_RS1), RD_FLD(instr, INSTR_RS2)); - else - printf("%s r%d <- r%d ,%d",basename, RD_FLD(instr, INSTR_RD),RD_FLD(instr, INSTR_RS1), SIGN_EXTEND13(RD_FLD(instr, INSTR_SIMM13))); -} - -void sparc_printshf(char * basename, unsigned instr) -{ - //OP=OP_2: RD, OP_3 RS1: {I=0 -> X & RS2 ,I=1 -> {X=0 -> SHCNT32 X=1->SHCNT64 }} - if (RD_FLD(instr, INSTR_I)==0) - printf("%s%d r%d <- r%d, by r%d ",(RD_FLD(instr, INSTR_X)==0 ? 32 : 64), basename, RD_FLD(instr, INSTR_RD), RD_FLD(instr, INSTR_RS1), RD_FLD(instr, INSTR_RS2)); - else - printf("%s%d r%d <- r%d, by 0x%04X ", basename,(RD_FLD(instr, INSTR_X)==0 ? 32 : 64), RD_FLD(instr, INSTR_RD), RD_FLD(instr, INSTR_RS1), (RD_FLD(instr, INSTR_X)==0 ? RD_FLD(instr, INSTR_SHCNT32) : RD_FLD(instr, INSTR_SHCNT64)) ); - -} - - -/////////////////////////////////// -// Floating point instructions // -// * complete // -/////////////////////////////////// -void sparc_printfpu(unsigned instr) -{ - //OP=OP_2: RD, OP3 RS1, OPF, RS2 - bool rs1 = true; - switch(CC_FLD(RD_FLD(instr, INSTR_OPF), OPF_TYPE_ON)) - { - case OPF_FADDn: - rs1 = true; - printf("FADD%s ", opf_type_name[RD_FLD(instr,OPF_TYPE_ON)]); - break; - case OPF_FSUBn: - rs1 = true; - printf("FSUB%s ", opf_type_name[RD_FLD(instr,OPF_TYPE_ON)]); - break; - case OPF_FMOVn: //RS1 not valid - rs1 = false; - printf("FMOV%s ", opf_type_name[RD_FLD(instr,OPF_TYPE_ON)]); - break; - case OPF_FNEGn: //RS1 not valid - rs1 = false; - printf("FNEG%s ", opf_type_name[RD_FLD(instr,OPF_TYPE_ON)]); - break; - case OPF_FABSn: //RS1 not valid - rs1 = false; - printf("FABS%s ", opf_type_name[RD_FLD(instr,OPF_TYPE_ON)]); - break; - case OPF_FMULn: - rs1 = true; - printf("FMUL%s ", opf_type_name[RD_FLD(instr,OPF_TYPE_ON)]); - break; - case OPF_FDIVn: - rs1 = true; - printf("FDIV%s ", opf_type_name[RD_FLD(instr,OPF_TYPE_ON)]); - break; - case OPF_FSQRTn: - rs1 = true; - printf("FSQRT%s ", opf_type_name[RD_FLD(instr,OPF_TYPE_ON)]); - break; - } - switch (CC_FLD(RD_FLD(instr, INSTR_OPF),OPF_TYPE_TO)) - { - case OPF_FxTOt: // RS1 not valid - rs1 = false; - printf("FxTO%s ", opf_type_name[RD_FLD(instr,OPF_TYPE_TO)]); - break; - case OPF_FiTOt: // RS1 not valid - rs1 = false; - printf("FxTO%s ", opf_type_name[RD_FLD(instr,OPF_TYPE_TO)]); - break; - } - - switch(RD_FLD(instr, INSTR_OPF)) - { - case OPF_FsMULd: - rs1 = true; - printf("FsMULd "); - break; - case OPF_FdMULq: - rs1 = true; - printf("FdMULq "); - break; - case OPF_FsTOx: // RS1 not valid - rs1 = false; - printf("FsTOx "); - break; - case OPF_FsTOi: // RS1 not valid - rs1 = false; - printf("FsTOi "); - break; - case OPF_FsTOd: // RS1 not valid - rs1 = false; - printf("FsTOd "); - break; - case OPF_FsTOq: // RS1 not valid - rs1 = false; - printf("FsTOq "); - break; - case OPF_FdTOx: // RS1 not valid - rs1 = false; - printf("FdTOx "); - break; - case OPF_FdTOi: // RS1 not valid - rs1 = false; - printf("FdTOi "); - break; - case OPF_FdTOs: // RS1 not valid - rs1 = false; - printf("FdTOs "); - break; - case OPF_FdTOq: // RS1 not valid - rs1 = false; - printf("FdTOq "); - break; - case OPF_FqTOx: // RS1 not valid - rs1 = false; - printf("FqTOx "); - break; - case OPF_FqTOi: // RS1 not valid - rs1 = false; - printf("FqTOi "); - break; - case OPF_FqTOs: // RS1 not valid - rs1 = false; - printf("FqTOs "); - break; - case OPF_FqTOd: // RS1 not valid - rs1 = false; - printf("FqTOd "); - break; - } - //OP=OP_2: RD, OP3 RS1, OPF, RS2 - if (rs1) - printf("rd=r%d rs1=r%d rs2=r%d ", RD_FLD(instr, INSTR_RD),RD_FLD(instr, INSTR_RS1), RD_FLD(instr, INSTR_RS2)); - else - printf("rd=r%d rs2=r%d", RD_FLD(instr, INSTR_RD), RD_FLD(instr, INSTR_RS2)); -} - -void sparc_print2(unsigned instr) -{ - switch(RD_FLD(instr, INSTR_OP3)) - { - case OP3_ADD: - sparc_printalu("ADD", instr); - return; - - case OP3_ADDcc: - sparc_printalu("ADDcc", instr); - return; - - case OP3_ADDC: - sparc_printalu("ADDC", instr); - return; - - case OP3_ADDCcc: - sparc_printalu("ADDCcc", instr); - return; - - case OP3_AND: - sparc_printalu("AND", instr); - return; - - case OP3_ANDcc: - sparc_printalu("ANDcc", instr); - return; - - case OP3_OR: - sparc_printalu("OR", instr); - return; - - case OP3_ORcc: - sparc_printalu("ORcc", instr); - return; - - case OP3_XOR: - sparc_printalu("XOR", instr); - return; - - case OP3_XORcc: - sparc_printalu("XORcc", instr); - return; - - case OP3_SUB: - sparc_printalu("SUB", instr); - return; - - case OP3_SUBcc: - sparc_printalu("SUBcc", instr); - return; - - case OP3_ANDN: - sparc_printalu("ANDN", instr); - return; - - case OP3_ANDNcc: - sparc_printalu("ANDNcc", instr); - return; - - case OP3_ORN: - sparc_printalu("ORN", instr); - return; - - case OP3_ORNcc: - sparc_printalu("ORNcc", instr); - return; - - case OP3_XNOR: - sparc_printalu("XNOR", instr); - return; - - case OP3_XNORcc: - sparc_printalu("XNORcc", instr); - return; - - case OP3_SUBC: - sparc_printalu("SUBC", instr); - return; - - case OP3_SUBCcc: - sparc_printalu("SUBCcc", instr); - return; - - case OP3_MULX: - sparc_printalu("MULX", instr); - return; - - case OP3_SDIVX: - sparc_printalu("SDIVX", instr); - return; - - case OP3_UDIVX: - sparc_printalu("UDIVX", instr); - return; - - case OP3_SLL: - sparc_printshf("SLL",instr); - return; - case OP3_SRL: - sparc_printshf("SRL",instr); - return; - case OP3_SRA: - sparc_printshf("SRA",instr); - return; - - case OP3_DONERETRY: - { - if (RD_FLD(instr, INSTR_FCN)==FCN_DONE) - printf("DONE"); - else if (RD_FLD(instr, INSTR_FCN)==FCN_RETRY) - printf("RETRY"); - return; - } - - case OP3_FCMP: //OP=OP_2: CC1_H, CC0_H, RS1, OPF, RS2 - { - unsigned fop_n = CC_FLD(RD_FLD(instr, INSTR_OPF),OPF_TYPE_ON); - if (fop_n==OPF_FCMPn) - printf("FCMP "); - else if (fop_n==OPF_FCMPEn) - printf("FCMPE "); - - //which floating point condition register - unsigned fcc = (RD_FLD(instr, INSTR_CC1_H) << 1) | - RD_FLD(instr, INSTR_CC0_H); - - printf (" fcc=%d rs1=r%d rs2=r%d", fcc, RD_FLD(instr, INSTR_RS1), RD_FLD(instr, INSTR_RS2)); - - return; - } - - case OP3_FPU: - sparc_printfpu(instr); - return; - - case OP3_FLUSH: //OP=OP_2 RS1 {I=0 -> rs2, I=1->simm13} - if (RD_FLD(instr, INSTR_I)==0) - printf("FLUSH rs1=r%d rs2=r%d", RD_FLD(instr, INSTR_RS1), RD_FLD(instr, INSTR_RS2)); - else - printf("FLUSH rs1=r%d simm13=%d", RD_FLD(instr, INSTR_RS1), SIGN_EXTEND13(RD_FLD(instr, INSTR_SIMM13))); - return; - case OP3_FLUSHW: //OP=OP_2 I = 0 - printf("FLUSHW"); - return; - case OP3_JMPL: //OP=OP_2 RD, RS1 {I=0-> RS2, I=1->SIMM13} - if (RD_FLD(instr, INSTR_I)==0) - printf("JMPL link:r%d, to: r%d+r%d", RD_FLD(instr, INSTR_RD),RD_FLD(instr, INSTR_RS1),RD_FLD(instr, INSTR_RS2) ); - else - printf("JMPL link:r%d, to: r%d+%d", RD_FLD(instr, INSTR_RD),RD_FLD(instr, INSTR_RS1),SIGN_EXTEND13(RD_FLD(instr, INSTR_SIMM13)) ); - return; - - case OP3_POPC: //OP=OP_2, RD, RS1=0, {I=0->RS2, I=1->SIMM13} - if (RD_FLD(instr, INSTR_I)==0) - printf("POPC rs1=r%d rs2=r%d", RD_FLD(instr, INSTR_RS1), RD_FLD(instr, INSTR_RS2)); - else - printf("POPC rs1=r%d simm13=%d", RD_FLD(instr, INSTR_RS1),SIGN_EXTEND13(RD_FLD(instr, INSTR_SIMM13))); - return; - - case OP3_MEMBAR: //OP=OP_2 FCN = 0 RS1=0b01111 CMASK MMASK - printf("MEMBAR cmask=0x%X mmask=0x%X", RD_FLD(instr, INSTR_CMASK), RD_FLD(instr, INSTR_MMASK)); - return; - - case OP3_Tcc: //integer trap COND_HI RS1, CC1/CC0 {I=0->RS2, I=1->SW_TRAP_#} - if (RD_FLD(instr, INSTR_I)==0) - printf("T%s Xcc?=%d rs1=r%d rs2=r%d", icond_names[RD_FLD(instr, INSTR_COND_H)], - RD_FLD(instr, INSTR_CC1), - RD_FLD(instr, INSTR_RS1), - RD_FLD(instr, INSTR_RS2)); - else - printf("T%s Xcc?=%d rs1=r%d trap#=%d", icond_names[RD_FLD(instr, INSTR_COND_H)], - RD_FLD(instr, INSTR_CC1), - RD_FLD(instr, INSTR_RS1), - RD_FLD(instr, INSTR_SWTRAP)); - - // guess what? a REALLY twisted special case.. - // FMOVcc and FRMOVcc share the same opcode.. you have to test if OPF_LOW_S makes - // sense.. if so, it is a RMOVcc.. else FMOVcc.. - case OP3_FMOVcc: //OP=OP_2 RD, COND, bit18=0, OPF_CC, OPF_LOW_B, RS2 - //case OP3_FRMOVcc: //OP=OP_2 RD, RS1, bit13=0, RCOND,OPF_LOW_S, RS2 - { - unsigned opflows = RD_FLD(instr, INSTR_OPF_LOW_S); - unsigned opflowb = RD_FLD(instr, INSTR_OPF_LOW_B); - if (opflows == OPF_FRMOVS || opflows == OPF_FRMOVD || opflows == OPF_FRMOVQ) - { - // Oh.. its a FRMOVcc - char * basename; - if (opflows == OPF_FRMOVS) - basename = "FRMOVS"; - else if (opflows == OPF_FRMOVD) - basename = "FRMOVD"; - else if (opflows == OPF_FRMOVQ) - basename = "FRMOVQ"; - - printf("%s%s rd=r%d rs1=r%d rs2=r%d", basename, rcond_names[RD_FLD(instr, INSTR_ECOND)], - RD_FLD(instr, INSTR_RD), - RD_FLD(instr, INSTR_RS1), - RD_FLD(instr, INSTR_RS2)); - - } - else - { - char * basename; - - if (opflowb == OPF_FMOVS) - basename = "FMOVS"; - else if (opflowb == OPF_FMOVD) - basename = "FMOVD"; - else if (opflowb == OPF_FMOVQ) - basename = "FMOVQ"; - else - basename = "FMOV?"; - - // Must be a FMOVcc - printf("%s%s rd=r%d rs2=r%d %s", basename, fcond_names[RD_FLD(instr, INSTR_COND_H)], - RD_FLD(instr, INSTR_RD), - RD_FLD(instr, INSTR_RS2), - cc_names[RD_FLD(instr, INSTR_OPFCC)]); - - } - return; - } - case OP3_MOVcc: //OP=OP_2, Rd, OP3, CC2-CC1-CC0, COND, {I=0->RS2, I=1->SIMM13} - { - unsigned ccc = (RD_FLD(instr, INSTR_CC2) << 2) | - (RD_FLD(instr, INSTR_CC1_H) << 1) | - RD_FLD(instr, INSTR_CC0_H); - - if (RD_FLD(instr, INSTR_I) == 0) - printf("MOV%s rd=r%d rs2=r%d %s", icond_names[RD_FLD(instr, INSTR_COND)], - RD_FLD(instr, INSTR_RD), - RD_FLD(instr, INSTR_RS2), - cc_names[ccc]); - else - printf("MOV%s rd=r%d simm13=%d %s", icond_names[RD_FLD(instr, INSTR_COND)], - RD_FLD(instr, INSTR_RD), - SIGN_EXTEND13(RD_FLD(instr, INSTR_SIMM13)), - cc_names[ccc]); - return; - - - } - case OP3_RMOVcc: //OP=OP_2, Rd, RS1,RCOND, {I=0->RS2 -> I=1->SIMM10} - { - if (RD_FLD(instr, INSTR_I) == 0) - printf("RMOV%s rd=r%d rs1=r%d rs2=r%d", rcond_names[RD_FLD(instr, INSTR_RCOND)], - RD_FLD(instr, INSTR_RS1), - RD_FLD(instr, INSTR_RS2)); - else - printf("RMOV%s rd=r%d rs1=r%d simm10=%d", rcond_names[RD_FLD(instr, INSTR_RCOND)], - RD_FLD(instr, INSTR_RS1), - SIGN_EXTEND(RD_FLD(instr, INSTR_SIMM10),10)); - return; - } - - case OP3_RETURN: - if (RD_FLD(instr, INSTR_I) == 0) - printf("RETURN r%d + r%d", RD_FLD(instr, INSTR_RS1), RD_FLD(instr, INSTR_RS2)); - else - printf("RETURN r%d + %d", RD_FLD(instr, INSTR_RS1), SIGN_EXTEND13(RD_FLD(instr, INSTR_SIMM13))); - return; - - case OP3_SAVE: - if (RD_FLD(instr, INSTR_I) == 0) - printf("SAVE r%d , r%d, r%d", RD_FLD(instr, INSTR_RS1), RD_FLD(instr, INSTR_RS2), RD_FLD(instr, INSTR_RD)); - else - printf("SAVE r%d , %d, r%d", RD_FLD(instr, INSTR_RS1), SIGN_EXTEND13(RD_FLD(instr, INSTR_SIMM13)), RD_FLD(instr, INSTR_RD)); - return; - - case OP3_RESTORE: - if (RD_FLD(instr, INSTR_I) == 0) - printf("RESTORE r%d , r%d, r%d", RD_FLD(instr, INSTR_RS1), RD_FLD(instr, INSTR_RS2), RD_FLD(instr, INSTR_RD)); - else - printf("RESTORE r%d , %d, r%d", RD_FLD(instr, INSTR_RS1), SIGN_EXTEND13(RD_FLD(instr, INSTR_SIMM13)), RD_FLD(instr, INSTR_RD)); - return; - - - } - - printf("Unknown:OP=0b10 OP3 = 0x%04X", RD_FLD(instr, INSTR_OP3)); -} - - -// -// Decodes OP_3 = 3 family instructions -// * complete -// * instructions need pseudo-code translation =p -// * STQFA for example has special register packing -// that need decoded - -void sparc_print3(unsigned instr) -{ - switch(RD_FLD(instr, INSTR_OP3)) - { - case OP3_LDFA: //OP=OP_3 RD, Rs1, {I=0->IMM_ASI, RS2 I=1->SIMM13} - { - if (RD_FLD(instr, INSTR_I)==0) - printf("LDFA rd=r%d rs1=r%d rs2=r%d immasi=0x%04X", RD_FLD(instr, INSTR_RD), RD_FLD(instr, INSTR_RS1),RD_FLD(instr, INSTR_RS2), RD_FLD(instr, INSTR_IMMASI)); - else - printf("LDFA rd=r%d rs1=r%d simm13=%d", RD_FLD(instr, INSTR_RD), RD_FLD(instr, INSTR_RS1),SIGN_EXTEND13(RD_FLD(instr, INSTR_SIMM13))); - return; - } - case OP3_LDDFA: //OP=OP_3 RD, Rs1, {I=0->IMM_ASI, RS2 I=1->SIMM13} - { - if (RD_FLD(instr, INSTR_I)==0) - printf("LDDFA rd=r%d rs1=r%d rs2=r%d immasi=0x%04X", RD_FLD(instr, INSTR_RD), RD_FLD(instr, INSTR_RS1),RD_FLD(instr, INSTR_RS2), RD_FLD(instr, INSTR_IMMASI)); - else - printf("LDDFA rd=r%d rs1=r%d simm13=%d", RD_FLD(instr, INSTR_RD), RD_FLD(instr, INSTR_RS1),SIGN_EXTEND13(RD_FLD(instr, INSTR_SIMM13))); - return; - } - case OP3_LDQFA: //OP=OP_3 RD, Rs1, {I=0->IMM_ASI, RS2 I=1->SIMM13} - { - if (RD_FLD(instr, INSTR_I)==0) - printf("LDQFA rd=r%d rs1=r%d rs2=r%d immasi=0x%04X", RD_FLD(instr, INSTR_RD), RD_FLD(instr, INSTR_RS1),RD_FLD(instr, INSTR_RS2), RD_FLD(instr, INSTR_IMMASI)); - else - printf("LDQFA rd=r%d rs1=r%d simm13=%d", RD_FLD(instr, INSTR_RD), RD_FLD(instr, INSTR_RS1),SIGN_EXTEND13(RD_FLD(instr, INSTR_SIMM13))); - return; - } - case OP3_LDF: //OP=OP_3 RD, RS1, {I=0->RS2, I=1->SIMM13} RD = 0->31 - { - if (RD_FLD(instr, INSTR_I)==0) - printf("LDF rd=r%d rs1=r%d rs2=r%d", RD_FLD(instr, INSTR_RD), RD_FLD(instr, INSTR_RS1),RD_FLD(instr, INSTR_RS2)); - else - printf("LDF rd=r%d rs1=r%d simm13=%d", RD_FLD(instr, INSTR_RD), RD_FLD(instr, INSTR_RS1),SIGN_EXTEND13(RD_FLD(instr, INSTR_SIMM13))); - return; - } - case OP3_LDDF: //OP=OP_3 RD, RS1, {I=0->RS2, I=1->SIMM13} RD ? spec? 5.1.4.1 - { - if (RD_FLD(instr, INSTR_I)==0) - printf("LDDF rd=r%d rs1=r%d rs2=r%d", RD_FLD(instr, INSTR_RD), RD_FLD(instr, INSTR_RS1),RD_FLD(instr, INSTR_RS2)); - else - printf("LDDF rd=r%d rs1=r%d simm13=%d", RD_FLD(instr, INSTR_RD), RD_FLD(instr, INSTR_RS1),SIGN_EXTEND13(RD_FLD(instr, INSTR_SIMM13))); - return; - } - case OP3_LDQF: //OP=OP_3 RD, RS1, {I=0->RS2, I=1->SIMM13} RD ? spec? - { - if (RD_FLD(instr, INSTR_I)==0) - printf("LDQF rd=r%d rs1=r%d rs2=r%d", RD_FLD(instr, INSTR_RD), RD_FLD(instr, INSTR_RS1),RD_FLD(instr, INSTR_RS2)); - else - printf("LDQF rd=r%d rs1=r%d simm13=%d", RD_FLD(instr, INSTR_RD), RD_FLD(instr, INSTR_RS1),SIGN_EXTEND13(RD_FLD(instr, INSTR_SIMM13))); - return; - } - // **SPECIAL case these 2 instructions have same OP3 field.. RD field determines which ** - case OP3_LDFSR: //OP=OP_3 RD, RS1, {I=0->RS2, I=1->SIMM13} RD = 0 - //case OP3_LDXFSR: //OP=OP_3 RD, RS1, {I=0->RS2, I=1->SIMM13} RD = 1 - { - if (RD_FLD(instr, INSTR_RD)==0) - printf("LDFSR "); - else if (RD_FLD(instr, INSTR_RD)==1) - printf("LDXFSR "); - - if (RD_FLD(instr, INSTR_I)==0) - printf("rs1=r%d rs2=r%d", RD_FLD(instr, INSTR_RS1),RD_FLD(instr, INSTR_RS2)); - else - printf("rs1=r%d simm13=%d", RD_FLD(instr, INSTR_RS1),SIGN_EXTEND13(RD_FLD(instr, INSTR_SIMM13))); - - return; - } - - case OP3_LDSTUBA: //OP=OP_3 RD, RS1 {I=0->RS2, IMM_ASI, I=1->SIMM13} - { - if (RD_FLD(instr, INSTR_I)==0) - printf("LDSTUBA rd=r%d rs1=r%d rs2=r%d", RD_FLD(instr, INSTR_RD), RD_FLD(instr, INSTR_RS1),RD_FLD(instr, INSTR_RS2)); - else - printf("LDSTUBA rd=r%d rs1=r%d simm13=%d", RD_FLD(instr, INSTR_RD), RD_FLD(instr, INSTR_RS1),SIGN_EXTEND13(RD_FLD(instr, INSTR_SIMM13))); - return; - } - case OP3_LDSTUB: //OP=OP_3 RD, Rs1 {I=0->RS2, I=1->SIMM13} - { - if (RD_FLD(instr, INSTR_I)==0) - printf("LDSTUB rd=r%d rs1=r%d rs2=r%d", RD_FLD(instr, INSTR_RD), RD_FLD(instr, INSTR_RS1),RD_FLD(instr, INSTR_RS2)); - else - printf("LDSTUB rd=r%d rs1=r%d simm13=%d", RD_FLD(instr, INSTR_RD), RD_FLD(instr, INSTR_RS1),SIGN_EXTEND13(RD_FLD(instr, INSTR_SIMM13))); - return; - } - case OP3_STB: //OP=OP_3 RD RS1 {I=0->RS2, I=1->SIMM13} - { - if (RD_FLD(instr, INSTR_I)==0) - printf("STB rd=r%d rs1=r%d rs2=r%d", RD_FLD(instr, INSTR_RD), RD_FLD(instr, INSTR_RS1),RD_FLD(instr, INSTR_RS2)); - else - printf("STB rd=r%d rs1=r%d simm13=%d", RD_FLD(instr, INSTR_RD), RD_FLD(instr, INSTR_RS1),SIGN_EXTEND13(RD_FLD(instr, INSTR_SIMM13))); - return; - } - case OP3_STBA: //OP=OP_3 RD RS1 {I=0->RS2 IMM_ASI, I=1->SIMM13} - { - if (RD_FLD(instr, INSTR_I)==0) - printf("STBA rd=r%d rs1=r%d rs2=r%d immasi=0x%04X", RD_FLD(instr, INSTR_RD), RD_FLD(instr, INSTR_RS1),RD_FLD(instr, INSTR_RS2), RD_FLD(instr, INSTR_IMMASI)); - else - printf("STBA rd=r%d rs1=r%d simm13=%d", RD_FLD(instr, INSTR_RD), RD_FLD(instr, INSTR_RS1),SIGN_EXTEND13(RD_FLD(instr, INSTR_SIMM13))); - return; - } - case OP3_STH: //OP=OP_3 RD RS1 {I=0->RS2, I=1->SIMM13} - { - if (RD_FLD(instr, INSTR_I)==0) - printf("STH rd=r%d rs1=r%d rs2=r%d", RD_FLD(instr, INSTR_RD), RD_FLD(instr, INSTR_RS1),RD_FLD(instr, INSTR_RS2)); - else - printf("STH rd=r%d rs1=r%d simm13=%d", RD_FLD(instr, INSTR_RD), RD_FLD(instr, INSTR_RS1),SIGN_EXTEND13(RD_FLD(instr, INSTR_SIMM13))); - return; - } - case OP3_STHA: //OP=OP_3 RD RS1 {I=0->RS2 IMM_ASI, I=1->SIMM13} - { - if (RD_FLD(instr, INSTR_I)==0) - printf("STHA rd=r%d rs1=r%d rs2=r%d immasi=0x%04X", RD_FLD(instr, INSTR_RD), RD_FLD(instr, INSTR_RS1),RD_FLD(instr, INSTR_RS2), RD_FLD(instr, INSTR_IMMASI)); - else - printf("STHA rd=r%d rs1=r%d simm13=%d", RD_FLD(instr, INSTR_RD), RD_FLD(instr, INSTR_RS1),SIGN_EXTEND13(RD_FLD(instr, INSTR_SIMM13))); - return; - } - case OP3_STW: //OP=OP_3 RD RS1 {I=0->RS2, I=1->SIMM13} - { - if (RD_FLD(instr, INSTR_I)==0) - printf("STW rd=r%d rs1=r%d rs2=r%d", RD_FLD(instr, INSTR_RD), RD_FLD(instr, INSTR_RS1),RD_FLD(instr, INSTR_RS2)); - else - printf("STW rd=r%d rs1=r%d simm13=%d", RD_FLD(instr, INSTR_RD), RD_FLD(instr, INSTR_RS1),SIGN_EXTEND13(RD_FLD(instr, INSTR_SIMM13))); - return; - } - case OP3_STWA: //OP=OP_3 RD RS1 {I=0->RS2 IMM_ASI, I=1->SIMM13} - { - if (RD_FLD(instr, INSTR_I)==0) - printf("STWA rd=r%d rs1=r%d rs2=r%d immasi=0x%04X", RD_FLD(instr, INSTR_RD), RD_FLD(instr, INSTR_RS1),RD_FLD(instr, INSTR_RS2), RD_FLD(instr, INSTR_IMMASI)); - else - printf("STWA rd=r%d rs1=r%d simm13=%d", RD_FLD(instr, INSTR_RD), RD_FLD(instr, INSTR_RS1),SIGN_EXTEND13(RD_FLD(instr, INSTR_SIMM13))); - return; - } - case OP3_STX: //OP=OP_3 RD RS1 {I=0->RS2, I=1->SIMM13} - { - if (RD_FLD(instr, INSTR_I)==0) - printf("STX rd=r%d rs1=r%d rs2=r%d", RD_FLD(instr, INSTR_RD), RD_FLD(instr, INSTR_RS1),RD_FLD(instr, INSTR_RS2)); - else - printf("STX rd=r%d rs1=r%d simm13=%d", RD_FLD(instr, INSTR_RD), RD_FLD(instr, INSTR_RS1),SIGN_EXTEND13(RD_FLD(instr, INSTR_SIMM13))); - return; - } - case OP3_STXA: //OP=OP_3 RD RS1 {I=0->RS2 IMM_ASI, I=1->SIMM13} - { - if (RD_FLD(instr, INSTR_I)==0) - printf("STXA rd=r%d rs1=r%d rs2=r%d immasi=0x%04X", RD_FLD(instr, INSTR_RD), RD_FLD(instr, INSTR_RS1),RD_FLD(instr, INSTR_RS2), RD_FLD(instr, INSTR_IMMASI)); - else - printf("STXA rd=r%d rs1=r%d simm13=%d", RD_FLD(instr, INSTR_RD), RD_FLD(instr, INSTR_RS1),SIGN_EXTEND13(RD_FLD(instr, INSTR_SIMM13))); - return; - } - case OP3_STF: //OP=OP_3 RD RS1 {I=0->RS2, I=1->SIMM13} - { - if (RD_FLD(instr, INSTR_I)==0) - printf("STF rd=r%d rs1=r%d rs2=r%d", RD_FLD(instr, INSTR_RD), RD_FLD(instr, INSTR_RS1),RD_FLD(instr, INSTR_RS2)); - else - printf("STF rd=r%d rs1=r%d simm13=%d", RD_FLD(instr, INSTR_RD), RD_FLD(instr, INSTR_RS1),SIGN_EXTEND13(RD_FLD(instr, INSTR_SIMM13))); - return; - } - case OP3_STFA: //OP=OP_3 RD RS1 {I=0->RS2 IMM_ASI, I=1->SIMM13} - { - if (RD_FLD(instr, INSTR_I)==0) - printf("STFA rd=r%d rs1=r%d rs2=r%d immasi=0x%04X", RD_FLD(instr, INSTR_RD), RD_FLD(instr, INSTR_RS1),RD_FLD(instr, INSTR_RS2), RD_FLD(instr, INSTR_IMMASI)); - else - printf("STFA rd=r%d rs1=r%d simm13=%d", RD_FLD(instr, INSTR_RD), RD_FLD(instr, INSTR_RS1),SIGN_EXTEND13(RD_FLD(instr, INSTR_SIMM13))); - return; - } - case OP3_STDF: //OP=OP_3 RD RS1 {I=0->RS2, I=1->SIMM13} - { - if (RD_FLD(instr, INSTR_I)==0) - printf("STDF rd=r%d rs1=r%d rs2=r%d", RD_FLD(instr, INSTR_RD), RD_FLD(instr, INSTR_RS1),RD_FLD(instr, INSTR_RS2)); - else - printf("STDF rd=r%d rs1=r%d simm13=%d", RD_FLD(instr, INSTR_RD), RD_FLD(instr, INSTR_RS1),SIGN_EXTEND13(RD_FLD(instr, INSTR_SIMM13))); - return; - } - case OP3_STDFA: //OP=OP_3 RD RS1 {I=0->RS2 IMM_ASI, I=1->SIMM13} - { - if (RD_FLD(instr, INSTR_I)==0) - printf("STDFA rd=r%d rs1=r%d rs2=r%d immasi=0x%04X", RD_FLD(instr, INSTR_RD), RD_FLD(instr, INSTR_RS1),RD_FLD(instr, INSTR_RS2), RD_FLD(instr, INSTR_IMMASI)); - else - printf("STDFA rd=r%d rs1=r%d simm13=%d", RD_FLD(instr, INSTR_RD), RD_FLD(instr, INSTR_RS1),SIGN_EXTEND13(RD_FLD(instr, INSTR_SIMM13))); - return; - } - case OP3_STQF: //OP=OP_3 RD RS1 {I=0->RS2, I=1->SIMM13} - { - if (RD_FLD(instr, INSTR_I)==0) - printf("STQF rd=r%d rs1=r%d rs2=r%d", RD_FLD(instr, INSTR_RD), RD_FLD(instr, INSTR_RS1),RD_FLD(instr, INSTR_RS2)); - else - printf("STQF rd=r%d rs1=r%d simm13=%d", RD_FLD(instr, INSTR_RD), RD_FLD(instr, INSTR_RS1),SIGN_EXTEND13(RD_FLD(instr, INSTR_SIMM13))); - return; - } - case OP3_STQFA: //OP=OP_3 RD RS1 {I=0->RS2 IMM_ASI, I=1->SIMM13} - { - if (RD_FLD(instr, INSTR_I)==0) - printf("STQFA rd=r%d rs1=r%d rs2=r%d immasi=0x%04X", RD_FLD(instr, INSTR_RD), RD_FLD(instr, INSTR_RS1),RD_FLD(instr, INSTR_RS2), RD_FLD(instr, INSTR_IMMASI)); - else - printf("STQFA rd=r%d rs1=r%d simm13=%d", RD_FLD(instr, INSTR_RD), RD_FLD(instr, INSTR_RS1),SIGN_EXTEND13(RD_FLD(instr, INSTR_SIMM13))); - return; - } - - // ** SPECIAL CASE ** These 2 opcodes have same OP3 field.. RD determines - case OP3_STFSR: //OP=OP_3 RD=0 RS1 {I=0->RS2, I=1->SIMM13} - //case OP3_STXFSR: //OP=OP_3 RD=1 RS1 {I=0->RS2, I=1->SIMM13} - { - if (RD_FLD(instr, INSTR_RD)==0) - printf("STFSR "); - else if (RD_FLD(instr, INSTR_RD)==1) - printf("STXFSR "); - - if (RD_FLD(instr, INSTR_I)==0) - printf("rs1=r%d rs2=r%d", RD_FLD(instr, INSTR_RS1),RD_FLD(instr, INSTR_RS2)); - else - printf("rs1=r%d simm13=%d", RD_FLD(instr, INSTR_RS1),SIGN_EXTEND13(RD_FLD(instr, INSTR_SIMM13))); - - return; - } - - case OP3_LDSB: //OP=OP_3,RD RS1, {I=0->RS2, I=1->SIMM13} - { - if (RD_FLD(instr, INSTR_I)==0) - printf("LDSB rd=r%d rs1=r%d rs2=r%d", RD_FLD(instr, INSTR_RD), RD_FLD(instr, INSTR_RS1),RD_FLD(instr, INSTR_RS2)); - else - printf("LDSB rd=r%d rs1=r%d simm13=%d", RD_FLD(instr, INSTR_RD), RD_FLD(instr, INSTR_RS1),SIGN_EXTEND13(RD_FLD(instr, INSTR_SIMM13))); - return; - } - case OP3_LDSH: //OP=OP_3,RD RS1, {I=0->RS2, I=1->SIMM13} - { - if (RD_FLD(instr, INSTR_I)==0) - printf("LDSH rd=r%d rs1=r%d rs2=r%d", RD_FLD(instr, INSTR_RD), RD_FLD(instr, INSTR_RS1),RD_FLD(instr, INSTR_RS2)); - else - printf("LDSH rd=r%d rs1=r%d simm13=%d", RD_FLD(instr, INSTR_RD), RD_FLD(instr, INSTR_RS1),SIGN_EXTEND13(RD_FLD(instr, INSTR_SIMM13))); - return; - } - case OP3_LDSW: //OP=OP_3,RD RS1, {I=0->RS2, I=1->SIMM13} - { - if (RD_FLD(instr, INSTR_I)==0) - printf("LDSW rd=r%d rs1=r%d rs2=r%d", RD_FLD(instr, INSTR_RD), RD_FLD(instr, INSTR_RS1),RD_FLD(instr, INSTR_RS2)); - else - printf("LDSW rd=r%d rs1=r%d simm13=%d", RD_FLD(instr, INSTR_RD), RD_FLD(instr, INSTR_RS1),SIGN_EXTEND13(RD_FLD(instr, INSTR_SIMM13))); - return; - } - case OP3_LDUB: //OP=OP_3,RD RS1, {I=0->RS2, I=1->SIMM13} - { - if (RD_FLD(instr, INSTR_I)==0) - printf("LDUB rd=r%d rs1=r%d rs2=r%d", RD_FLD(instr, INSTR_RD), RD_FLD(instr, INSTR_RS1),RD_FLD(instr, INSTR_RS2)); - else - printf("LDUB rd=r%d rs1=r%d simm13=%d", RD_FLD(instr, INSTR_RD), RD_FLD(instr, INSTR_RS1),SIGN_EXTEND13(RD_FLD(instr, INSTR_SIMM13))); - return; - } - case OP3_LDUH: //OP=OP_3,RD RS1, {I=0->RS2, I=1->SIMM13} - { - if (RD_FLD(instr, INSTR_I)==0) - printf("LDUH rd=r%d rs1=r%d rs2=r%d", RD_FLD(instr, INSTR_RD), RD_FLD(instr, INSTR_RS1),RD_FLD(instr, INSTR_RS2)); - else - printf("LDUH rd=r%d rs1=r%d simm13=%d", RD_FLD(instr, INSTR_RD), RD_FLD(instr, INSTR_RS1),SIGN_EXTEND13(RD_FLD(instr, INSTR_SIMM13))); - return; - } - case OP3_LDUW: //OP=OP_3,RD RS1, {I=0->RS2, I=1->SIMM13} - { - if (RD_FLD(instr, INSTR_I)==0) - printf("LDUW rd=r%d rs1=r%d rs2=r%d", RD_FLD(instr, INSTR_RD), RD_FLD(instr, INSTR_RS1),RD_FLD(instr, INSTR_RS2)); - else - printf("LDUW rd=r%d rs1=r%d simm13=%d", RD_FLD(instr, INSTR_RD), RD_FLD(instr, INSTR_RS1),SIGN_EXTEND13(RD_FLD(instr, INSTR_SIMM13))); - return; - } - case OP3_LDX: //OP=OP_3,RD RS1, {I=0->RS2, I=1->SIMM13} - { - if (RD_FLD(instr, INSTR_I)==0) - printf("LDX rd=r%d rs1=r%d rs2=r%d", RD_FLD(instr, INSTR_RD), RD_FLD(instr, INSTR_RS1),RD_FLD(instr, INSTR_RS2)); - else - printf("LDX rd=r%d rs1=r%d simm13=%d", RD_FLD(instr, INSTR_RD), RD_FLD(instr, INSTR_RS1),SIGN_EXTEND13(RD_FLD(instr, INSTR_SIMM13))); - return; - } - case OP3_LDSBA: //OP=OP_3,RD RS1, {I=0->RS2,IMM_ASI, I=1->SIMM13} - { - if (RD_FLD(instr, INSTR_I)==0) - printf("LDSBA rd=r%d rs1=r%d rs2=r%d immasi=0x%04X", RD_FLD(instr, INSTR_RD), RD_FLD(instr, INSTR_RS1),RD_FLD(instr, INSTR_RS2), RD_FLD(instr, INSTR_IMMASI)); - else - printf("LDSBA rd=r%d rs1=r%d simm13=%d", RD_FLD(instr, INSTR_RD), RD_FLD(instr, INSTR_RS1),SIGN_EXTEND13(RD_FLD(instr, INSTR_SIMM13))); - return; - } - case OP3_LDSHA: //OP=OP_3, RS1, {I=0->RS2,IMM_ASI, I=1->SIMM13} - { - if (RD_FLD(instr, INSTR_I)==0) - printf("LDSHA rd=r%d rs1=r%d rs2=r%d immasi=0x%04X", RD_FLD(instr, INSTR_RD), RD_FLD(instr, INSTR_RS1),RD_FLD(instr, INSTR_RS2), RD_FLD(instr, INSTR_IMMASI)); - else - printf("LDSHA rd=r%d rs1=r%d simm13=%d", RD_FLD(instr, INSTR_RD), RD_FLD(instr, INSTR_RS1),SIGN_EXTEND13(RD_FLD(instr, INSTR_SIMM13))); - return; - } - case OP3_LDSWA: //OP=OP_3, RS1, {I=0->RS2,IMM_ASI, I=1->SIMM13} - { - if (RD_FLD(instr, INSTR_I)==0) - printf("LDSWA rd=r%d rs1=r%d rs2=r%d immasi=0x%04X", RD_FLD(instr, INSTR_RD), RD_FLD(instr, INSTR_RS1),RD_FLD(instr, INSTR_RS2), RD_FLD(instr, INSTR_IMMASI)); - else - printf("LDSWA rd=r%d rs1=r%d simm13=%d", RD_FLD(instr, INSTR_RD), RD_FLD(instr, INSTR_RS1),SIGN_EXTEND13(RD_FLD(instr, INSTR_SIMM13))); - return; - } - case OP3_LDUBA: //OP=OP_3, RS1, {I=0->RS2,IMM_ASI, I=1->SIMM13} - { - if (RD_FLD(instr, INSTR_I)==0) - printf("LDUBA rd=r%d rs1=r%d rs2=r%d immasi=0x%04X", RD_FLD(instr, INSTR_RD), RD_FLD(instr, INSTR_RS1),RD_FLD(instr, INSTR_RS2), RD_FLD(instr, INSTR_IMMASI)); - else - printf("LDUBA rd=r%d rs1=r%d simm13=%d", RD_FLD(instr, INSTR_RD), RD_FLD(instr, INSTR_RS1),SIGN_EXTEND13(RD_FLD(instr, INSTR_SIMM13))); - return; - } - case OP3_LDUHA: //OP=OP_3, RS1, {I=0->RS2,IMM_ASI, I=1->SIMM13} - { - if (RD_FLD(instr, INSTR_I)==0) - printf("LDUHA rd=r%d rs1=r%d rs2=r%d immasi=0x%04X", RD_FLD(instr, INSTR_RD), RD_FLD(instr, INSTR_RS1),RD_FLD(instr, INSTR_RS2), RD_FLD(instr, INSTR_IMMASI)); - else - printf("LDUHA rd=r%d rs1=r%d simm13=%d", RD_FLD(instr, INSTR_RD), RD_FLD(instr, INSTR_RS1),SIGN_EXTEND13(RD_FLD(instr, INSTR_SIMM13))); - return; - } - case OP3_LDUWA: //OP=OP_3, RS1, {I=0->RS2,IMM_ASI, I=1->SIMM13} - { - if (RD_FLD(instr, INSTR_I)==0) - printf("LDUWA rd=r%d rs1=r%d rs2=r%d immasi=0x%04X", RD_FLD(instr, INSTR_RD), RD_FLD(instr, INSTR_RS1),RD_FLD(instr, INSTR_RS2), RD_FLD(instr, INSTR_IMMASI)); - else - printf("LDUWA rd=r%d rs1=r%d simm13=%d", RD_FLD(instr, INSTR_RD), RD_FLD(instr, INSTR_RS1),SIGN_EXTEND13(RD_FLD(instr, INSTR_SIMM13))); - return; - } - case OP3_LDXA: //OP=OP_3, RS1, {I=0->RS2,IMM_ASI, I=1->SIMM13} - { - if (RD_FLD(instr, INSTR_I)==0) - printf("LDXA rd=r%d rs1=r%d rs2=r%d immasi=0x%04X", RD_FLD(instr, INSTR_RD), RD_FLD(instr, INSTR_RS1),RD_FLD(instr, INSTR_RS2), RD_FLD(instr, INSTR_IMMASI)); - else - printf("LDXA rd=r%d rs1=r%d simm13=%d", RD_FLD(instr, INSTR_RD), RD_FLD(instr, INSTR_RS1),SIGN_EXTEND13(RD_FLD(instr, INSTR_SIMM13))); - return; - } - case OP3_LDDA: //OP=OP_3, RS1, {I=0->RS2,IMM_ASI, I=1->SIMM13} - { - if (RD_FLD(instr, INSTR_I)==0) - printf("LDDA rd=r%d rs1=r%d rs2=r%d immasi=0x%04X", RD_FLD(instr, INSTR_RD), RD_FLD(instr, INSTR_RS1),RD_FLD(instr, INSTR_RS2), RD_FLD(instr, INSTR_IMMASI)); - else - printf("LDDA rd=r%d rs1=r%d simm13=%d", RD_FLD(instr, INSTR_RD), RD_FLD(instr, INSTR_RS1),SIGN_EXTEND13(RD_FLD(instr, INSTR_SIMM13))); - return; - } - case OP3_PREFETCH: //OP=OP_3 FCN, RS1 {I=0->RS2, I=1->SIMM13} - { - if (RD_FLD(instr, INSTR_I)==0) - printf("PREFETCH rd=r%d rs1=r%d rs2=r%d", RD_FLD(instr, INSTR_RD), RD_FLD(instr, INSTR_RS1),RD_FLD(instr, INSTR_RS2)); - else - printf("PREFETCH rd=r%d rs1=r%d simm13=%d", RD_FLD(instr, INSTR_RD), RD_FLD(instr, INSTR_RS1),SIGN_EXTEND13(RD_FLD(instr, INSTR_SIMM13))); - return; - } - case OP3_PREFETCHA: //OP=OP_3 FCN, RS1 {I=0->RS2+IMM_ASI, I=1->SIMM13} - { - if (RD_FLD(instr, INSTR_I)==0) - printf("PREFETCHA rd=r%d rs1=r%d rs2=r%d immasi=0x%04X", RD_FLD(instr, INSTR_RD), RD_FLD(instr, INSTR_RS1),RD_FLD(instr, INSTR_RS2), RD_FLD(instr, INSTR_IMMASI)); - else - printf("PREFETCHA rd=r%d rs1=r%d simm13=%d", RD_FLD(instr, INSTR_RD), RD_FLD(instr, INSTR_RS1),SIGN_EXTEND13(RD_FLD(instr, INSTR_SIMM13))); - return; - } - case OP3_CASA: //OP=OP_3 RD RS1 RS2{I=0->IMM_ASI, I=1->*} - { - printf("CASA rs1=r%d rs2=r%d rd=r%d", RD_FLD(instr, INSTR_RS1), RD_FLD(instr, INSTR_RS1), RD_FLD(instr, INSTR_RD)); - if (RD_FLD(instr, INSTR_I)==0) - printf("imm=0x%04X", RD_FLD(instr, INSTR_IMMASI)); - return; - } - case OP3_CASXA: //OP=OP_3 RD RS1 RS2{I=0->IMM_ASI, I=1->*} - { - printf("CASXA rs1=r%d rs2=r%d rd=r%d", RD_FLD(instr, INSTR_RS1), RD_FLD(instr, INSTR_RS1), RD_FLD(instr, INSTR_RD)); - if (RD_FLD(instr, INSTR_I)==0) - printf("imm=0x%04X", RD_FLD(instr, INSTR_IMMASI)); - return; - } - } - - printf("Unknown OP_3: OP3 = %08X", RD_FLD(instr, INSTR_OP3)); -} - -#define FLIP_ENDIAN(x) (((x & 255) << 24) | (((x >> 8) & 255) << 16) | (((x >> 16) & 255) << 8) | ((x >> 24) & 255)) - -void sparc_print(unsigned instr) -{ - printf("%08X: ", instr); - if (RD_FLD(instr,INSTR_OP)==OP_CALL) - printf("CALL disp:+%08X", instr & 0x3FFFFFFF); - else if (RD_FLD(instr,INSTR_OP)==OP_BRANCH) - sparc_printbr(instr); - else if (RD_FLD(instr,INSTR_OP)==OP_2) - sparc_print2(instr); - else if (RD_FLD(instr,INSTR_OP)==OP_3) - sparc_print3(instr); - printf("\n"); -} - - -void main() -{ -sparc_print(0x9DE3BF88); -sparc_print(0xF027A044); -sparc_print(0xF227A048); -sparc_print(0xD007A044); -sparc_print(0xD027BFEC); -sparc_print(0xD007BFEC); -sparc_print(0x933A2001); -sparc_print(0xD227BFEC); -sparc_print(0xD007BFEC); -sparc_print(0x932A2001); -sparc_print(0xD227BFEC); -sparc_print(0xD007BFEC); -sparc_print(0x80A22000); -sparc_print(0x02800005); -sparc_print(0x01000000); -sparc_print(0xD007BFEC); -sparc_print(0x92022001); -sparc_print(0xD227BFEC); -sparc_print(0xD007BFEC); -sparc_print(0x9202200A); -sparc_print(0xD227BFEC); -sparc_print(0xD007BFEC); -sparc_print(0x94100008); -sparc_print(0x932AA002); -sparc_print(0x92024008); -sparc_print(0x912A6001); -sparc_print(0xD027BFEC); -sparc_print(0xD007A044); -sparc_print(0xD207BFEC); - getchar(); -} + +void sparc_printbr(unsigned instr) +{ + // look at the OP2 field + if (RD_FLD(instr,INSTR_OP2)==OP2_ILLTRAP) { + printf("ILLTRAP .. "); + } else if (RD_FLD(instr, INSTR_OP2)==OP2_NOP) { + printf("NOP ... "); + } else if (RD_FLD(instr, INSTR_OP2)==OP2_SETHI) { + printf("SETHI ... "); + } else if (RD_FLD(instr, INSTR_OP2)==OP2_BICC) { + printf("%s (Dep) disp:%08X", icond_names[RD_FLD(instr, INSTR_COND_H)], + RD_FLD(instr,INSTR_DISP22)); + } else if (RD_FLD(instr, INSTR_OP2)==OP2_BPR) { + //A, RCOND_H, D16HI, P, RS1, D16LO + printf("P%s r%d " , rcond_names[RD_FLD(instr, INSTR_RCOND_H)], + RD_FLD(instr, INSTR_RS1)); + } else { + printf("Unknown:OP=0b00 OP2 = 0x%04X", RD_FLD(instr, INSTR_OP2)); + } +} + +void sparc_printalu(char * basename , unsigned instr) +{ + // OP=OP_2 : RD, OP3, RS1: {I=0 -> RS2 I=1->SIMM13} + if (RD_FLD(instr, INSTR_I)==0) { + printf("%s r%d <- r%d ,r%d",basename, RD_FLD(instr, INSTR_RD), + RD_FLD(instr, INSTR_RS1), RD_FLD(instr, INSTR_RS2)); + } else { + printf("%s r%d <- r%d ,%d",basename, RD_FLD(instr, INSTR_RD), + RD_FLD(instr, INSTR_RS1), + SIGN_EXTEND13(RD_FLD(instr, INSTR_SIMM13))); + } +} + +void sparc_printshf(char * basename, unsigned instr) +{ + // OP=OP_2: RD, OP_3 RS1: + // {I=0 -> X & RS2 ,I=1 -> {X=0 -> SHCNT32 X=1->SHCNT64 }} + if (RD_FLD(instr, INSTR_I)==0) { + printf("%s%d r%d <- r%d, by r%d ", (RD_FLD(instr, INSTR_X)==0 ? 32 : 64), + basename, RD_FLD(instr, INSTR_RD), RD_FLD(instr, INSTR_RS1), + RD_FLD(instr, INSTR_RS2)); + } else { + printf("%s%d r%d <- r%d, by 0x%04X ", basename, + (RD_FLD(instr, INSTR_X)==0 ? 32 : 64), + RD_FLD(instr, INSTR_RD), RD_FLD(instr, INSTR_RS1), + (RD_FLD(instr, INSTR_X)==0 ? RD_FLD(instr, INSTR_SHCNT32) + : RD_FLD(instr, INSTR_SHCNT64)) ); + } +} + + +/////////////////////////////////// +// Floating point instructions // +// * complete // +/////////////////////////////////// +void sparc_printfpu(unsigned instr) +{ + //OP=OP_2: RD, OP3 RS1, OPF, RS2 + bool rs1 = true; + switch(CC_FLD(RD_FLD(instr, INSTR_OPF), OPF_TYPE_ON)) + { + case OPF_FADDn: + rs1 = true; + printf("FADD%s ", opf_type_name[RD_FLD(instr,OPF_TYPE_ON)]); + break; + case OPF_FSUBn: + rs1 = true; + printf("FSUB%s ", opf_type_name[RD_FLD(instr,OPF_TYPE_ON)]); + break; + case OPF_FMOVn: //RS1 not valid + rs1 = false; + printf("FMOV%s ", opf_type_name[RD_FLD(instr,OPF_TYPE_ON)]); + break; + case OPF_FNEGn: //RS1 not valid + rs1 = false; + printf("FNEG%s ", opf_type_name[RD_FLD(instr,OPF_TYPE_ON)]); + break; + case OPF_FABSn: //RS1 not valid + rs1 = false; + printf("FABS%s ", opf_type_name[RD_FLD(instr,OPF_TYPE_ON)]); + break; + case OPF_FMULn: + rs1 = true; + printf("FMUL%s ", opf_type_name[RD_FLD(instr,OPF_TYPE_ON)]); + break; + case OPF_FDIVn: + rs1 = true; + printf("FDIV%s ", opf_type_name[RD_FLD(instr,OPF_TYPE_ON)]); + break; + case OPF_FSQRTn: + rs1 = true; + printf("FSQRT%s ", opf_type_name[RD_FLD(instr,OPF_TYPE_ON)]); + break; + } + switch (CC_FLD(RD_FLD(instr, INSTR_OPF),OPF_TYPE_TO)) + { + case OPF_FxTOt: // RS1 not valid + rs1 = false; + printf("FxTO%s ", opf_type_name[RD_FLD(instr,OPF_TYPE_TO)]); + break; + case OPF_FiTOt: // RS1 not valid + rs1 = false; + printf("FxTO%s ", opf_type_name[RD_FLD(instr,OPF_TYPE_TO)]); + break; + } + + switch(RD_FLD(instr, INSTR_OPF)) + { + case OPF_FsMULd: + rs1 = true; + printf("FsMULd "); + break; + case OPF_FdMULq: + rs1 = true; + printf("FdMULq "); + break; + case OPF_FsTOx: // RS1 not valid + rs1 = false; + printf("FsTOx "); + break; + case OPF_FsTOi: // RS1 not valid + rs1 = false; + printf("FsTOi "); + break; + case OPF_FsTOd: // RS1 not valid + rs1 = false; + printf("FsTOd "); + break; + case OPF_FsTOq: // RS1 not valid + rs1 = false; + printf("FsTOq "); + break; + case OPF_FdTOx: // RS1 not valid + rs1 = false; + printf("FdTOx "); + break; + case OPF_FdTOi: // RS1 not valid + rs1 = false; + printf("FdTOi "); + break; + case OPF_FdTOs: // RS1 not valid + rs1 = false; + printf("FdTOs "); + break; + case OPF_FdTOq: // RS1 not valid + rs1 = false; + printf("FdTOq "); + break; + case OPF_FqTOx: // RS1 not valid + rs1 = false; + printf("FqTOx "); + break; + case OPF_FqTOi: // RS1 not valid + rs1 = false; + printf("FqTOi "); + break; + case OPF_FqTOs: // RS1 not valid + rs1 = false; + printf("FqTOs "); + break; + case OPF_FqTOd: // RS1 not valid + rs1 = false; + printf("FqTOd "); + break; + } + //OP=OP_2: RD, OP3 RS1, OPF, RS2 + if (rs1) { + printf("rd=r%d rs1=r%d rs2=r%d ", RD_FLD(instr, INSTR_RD), + RD_FLD(instr, INSTR_RS1), RD_FLD(instr, INSTR_RS2)); + } else { + printf("rd=r%d rs2=r%d", RD_FLD(instr, INSTR_RD), RD_FLD(instr, INSTR_RS2)); + } +} + +void sparc_print2(unsigned instr) +{ + switch(RD_FLD(instr, INSTR_OP3)) + { + case OP3_ADD: + sparc_printalu("ADD", instr); + return; + + case OP3_ADDcc: + sparc_printalu("ADDcc", instr); + return; + + case OP3_ADDC: + sparc_printalu("ADDC", instr); + return; + + case OP3_ADDCcc: + sparc_printalu("ADDCcc", instr); + return; + + case OP3_AND: + sparc_printalu("AND", instr); + return; + + case OP3_ANDcc: + sparc_printalu("ANDcc", instr); + return; + + case OP3_OR: + sparc_printalu("OR", instr); + return; + + case OP3_ORcc: + sparc_printalu("ORcc", instr); + return; + + case OP3_XOR: + sparc_printalu("XOR", instr); + return; + + case OP3_XORcc: + sparc_printalu("XORcc", instr); + return; + + case OP3_SUB: + sparc_printalu("SUB", instr); + return; + + case OP3_SUBcc: + sparc_printalu("SUBcc", instr); + return; + + case OP3_ANDN: + sparc_printalu("ANDN", instr); + return; + + case OP3_ANDNcc: + sparc_printalu("ANDNcc", instr); + return; + + case OP3_ORN: + sparc_printalu("ORN", instr); + return; + + case OP3_ORNcc: + sparc_printalu("ORNcc", instr); + return; + + case OP3_XNOR: + sparc_printalu("XNOR", instr); + return; + + case OP3_XNORcc: + sparc_printalu("XNORcc", instr); + return; + + case OP3_SUBC: + sparc_printalu("SUBC", instr); + return; + + case OP3_SUBCcc: + sparc_printalu("SUBCcc", instr); + return; + + case OP3_MULX: + sparc_printalu("MULX", instr); + return; + + case OP3_SDIVX: + sparc_printalu("SDIVX", instr); + return; + + case OP3_UDIVX: + sparc_printalu("UDIVX", instr); + return; + + case OP3_SLL: + sparc_printshf("SLL",instr); + return; + case OP3_SRL: + sparc_printshf("SRL",instr); + return; + case OP3_SRA: + sparc_printshf("SRA",instr); + return; + + case OP3_DONERETRY: + { + if (RD_FLD(instr, INSTR_FCN)==FCN_DONE) + printf("DONE"); + else if (RD_FLD(instr, INSTR_FCN)==FCN_RETRY) + printf("RETRY"); + return; + } + + case OP3_FCMP: //OP=OP_2: CC1_H, CC0_H, RS1, OPF, RS2 + { + unsigned fop_n = CC_FLD(RD_FLD(instr, INSTR_OPF),OPF_TYPE_ON); + if (fop_n==OPF_FCMPn) + printf("FCMP "); + else if (fop_n==OPF_FCMPEn) + printf("FCMPE "); + + //which floating point condition register + unsigned fcc = (RD_FLD(instr, INSTR_CC1_H) << 1) | + RD_FLD(instr, INSTR_CC0_H); + + printf (" fcc=%d rs1=r%d rs2=r%d", fcc, RD_FLD(instr, INSTR_RS1), + RD_FLD(instr, INSTR_RS2)); + + return; + } + + case OP3_FPU: + sparc_printfpu(instr); + return; + + case OP3_FLUSH: //OP=OP_2 RS1 {I=0 -> rs2, I=1->simm13} + if (RD_FLD(instr, INSTR_I)==0) { + printf("FLUSH rs1=r%d rs2=r%d", RD_FLD(instr, INSTR_RS1), + RD_FLD(instr, INSTR_RS2)); + } else { + printf("FLUSH rs1=r%d simm13=%d", RD_FLD(instr, INSTR_RS1), + SIGN_EXTEND13(RD_FLD(instr, INSTR_SIMM13))); + } + return; + case OP3_FLUSHW: //OP=OP_2 I = 0 + printf("FLUSHW"); + return; + case OP3_JMPL: //OP=OP_2 RD, RS1 {I=0-> RS2, I=1->SIMM13} + if (RD_FLD(instr, INSTR_I)==0) { + printf("JMPL link:r%d, to: r%d+r%d", RD_FLD(instr, INSTR_RD), + RD_FLD(instr, INSTR_RS1),RD_FLD(instr, INSTR_RS2) ); + } else { + printf("JMPL link:r%d, to: r%d+%d", RD_FLD(instr, INSTR_RD), + RD_FLD(instr, INSTR_RS1), + SIGN_EXTEND13(RD_FLD(instr, INSTR_SIMM13)) ); + } + return; + case OP3_POPC: //OP=OP_2, RD, RS1=0, {I=0->RS2, I=1->SIMM13} + if (RD_FLD(instr, INSTR_I)==0) { + printf("POPC rs1=r%d rs2=r%d", RD_FLD(instr, INSTR_RS1), + RD_FLD(instr, INSTR_RS2)); + } else { + printf("POPC rs1=r%d simm13=%d", RD_FLD(instr, INSTR_RS1), + SIGN_EXTEND13(RD_FLD(instr, INSTR_SIMM13))); + } + return; + case OP3_MEMBAR: //OP=OP_2 FCN = 0 RS1=0b01111 CMASK MMASK + printf("MEMBAR cmask=0x%X mmask=0x%X", RD_FLD(instr, INSTR_CMASK), + RD_FLD(instr, INSTR_MMASK)); + return; + case OP3_Tcc: //integer trap COND_HI RS1, CC1/CC0 {I=0->RS2, I=1->SW_TRAP_#} + if (RD_FLD(instr, INSTR_I)==0) { + printf("T%s Xcc?=%d rs1=r%d rs2=r%d", + icond_names[RD_FLD(instr, INSTR_COND_H)], + RD_FLD(instr, INSTR_CC1), + RD_FLD(instr, INSTR_RS1), + RD_FLD(instr, INSTR_RS2)); + } else { + printf("T%s Xcc?=%d rs1=r%d trap#=%d", + icond_names[RD_FLD(instr, INSTR_COND_H)], + RD_FLD(instr, INSTR_CC1), + RD_FLD(instr, INSTR_RS1), + RD_FLD(instr, INSTR_SWTRAP)); + } + // guess what? a REALLY twisted special case.. + // FMOVcc and FRMOVcc share the same opcode.. + // you have to test if OPF_LOW_S makes sense.. + // if so, it is a RMOVcc.. else FMOVcc.. + case OP3_FMOVcc: //OP=OP_2 RD, COND, bit18=0, OPF_CC, OPF_LOW_B, RS2 + //case OP3_FRMOVcc: //OP=OP_2 RD, RS1, bit13=0, RCOND,OPF_LOW_S, RS2 + { + unsigned opflows = RD_FLD(instr, INSTR_OPF_LOW_S); + unsigned opflowb = RD_FLD(instr, INSTR_OPF_LOW_B); + if (opflows == OPF_FRMOVS || opflows == OPF_FRMOVD || + opflows == OPF_FRMOVQ) + { + // Oh.. its a FRMOVcc + char * basename; + if (opflows == OPF_FRMOVS) + basename = "FRMOVS"; + else if (opflows == OPF_FRMOVD) + basename = "FRMOVD"; + else if (opflows == OPF_FRMOVQ) + basename = "FRMOVQ"; + + printf("%s%s rd=r%d rs1=r%d rs2=r%d", basename, + rcond_names[RD_FLD(instr, INSTR_ECOND)], + RD_FLD(instr, INSTR_RD), + RD_FLD(instr, INSTR_RS1), + RD_FLD(instr, INSTR_RS2)); + + } else { + char *basename; + if (opflowb == OPF_FMOVS) + basename = "FMOVS"; + else if (opflowb == OPF_FMOVD) + basename = "FMOVD"; + else if (opflowb == OPF_FMOVQ) + basename = "FMOVQ"; + else + basename = "FMOV?"; + + // Must be a FMOVcc + printf("%s%s rd=r%d rs2=r%d %s", basename, + fcond_names[RD_FLD(instr, INSTR_COND_H)], + RD_FLD(instr, INSTR_RD), + RD_FLD(instr, INSTR_RS2), + cc_names[RD_FLD(instr, INSTR_OPFCC)]); + } + return; + } + case OP3_MOVcc: //OP=OP_2, Rd, OP3, CC2-CC1-CC0, COND, {I=0->RS2, I=1->SIMM13} + { + unsigned ccc = (RD_FLD(instr, INSTR_CC2) << 2) | + (RD_FLD(instr, INSTR_CC1_H) << 1) | + RD_FLD(instr, INSTR_CC0_H); + + if (RD_FLD(instr, INSTR_I) == 0) { + printf("MOV%s rd=r%d rs2=r%d %s", + icond_names[RD_FLD(instr, INSTR_COND)], + RD_FLD(instr, INSTR_RD), + RD_FLD(instr, INSTR_RS2), + cc_names[ccc]); + } else { + printf("MOV%s rd=r%d simm13=%d %s", + icond_names[RD_FLD(instr, INSTR_COND)], + RD_FLD(instr, INSTR_RD), + SIGN_EXTEND13(RD_FLD(instr, INSTR_SIMM13)), + cc_names[ccc]); + } + return; + } + case OP3_RMOVcc: //OP=OP_2, Rd, RS1,RCOND, {I=0->RS2 -> I=1->SIMM10} + { + if (RD_FLD(instr, INSTR_I) == 0) { + printf("RMOV%s rd=r%d rs1=r%d rs2=r%d", + rcond_names[RD_FLD(instr, INSTR_RCOND)], + RD_FLD(instr, INSTR_RS1), + RD_FLD(instr, INSTR_RS2)); + } else { + printf("RMOV%s rd=r%d rs1=r%d simm10=%d", + rcond_names[RD_FLD(instr, INSTR_RCOND)], + RD_FLD(instr, INSTR_RS1), + SIGN_EXTEND(RD_FLD(instr, INSTR_SIMM10),10)); + } + return; + } + + case OP3_RETURN: + if (RD_FLD(instr, INSTR_I) == 0) { + printf("RETURN r%d + r%d", RD_FLD(instr, INSTR_RS1), + RD_FLD(instr, INSTR_RS2)); + } else { + printf("RETURN r%d + %d", RD_FLD(instr, INSTR_RS1), + SIGN_EXTEND13(RD_FLD(instr, INSTR_SIMM13))); + } + return; + case OP3_SAVE: + if (RD_FLD(instr, INSTR_I) == 0) { + printf("SAVE r%d , r%d, r%d", RD_FLD(instr, INSTR_RS1), + RD_FLD(instr, INSTR_RS2), RD_FLD(instr, INSTR_RD)); + } else { + printf("SAVE r%d , %d, r%d", RD_FLD(instr, INSTR_RS1), + SIGN_EXTEND13(RD_FLD(instr, INSTR_SIMM13)), + RD_FLD(instr, INSTR_RD)); + } + return; + case OP3_RESTORE: + if (RD_FLD(instr, INSTR_I) == 0) { + printf("RESTORE r%d , r%d, r%d", RD_FLD(instr, INSTR_RS1), + RD_FLD(instr, INSTR_RS2), RD_FLD(instr, INSTR_RD)); + } else { + printf("RESTORE r%d , %d, r%d", RD_FLD(instr, INSTR_RS1), + SIGN_EXTEND13(RD_FLD(instr, INSTR_SIMM13)), + RD_FLD(instr, INSTR_RD)); + } + return; + } + + printf("Unknown:OP=0b10 OP3 = 0x%04X", RD_FLD(instr, INSTR_OP3)); +} + + +// +// Decodes OP_3 = 3 family instructions +// * complete +// * instructions need pseudo-code translation =p +// * STQFA for example has special register packing +// that need decoded + +void sparc_print3(unsigned instr) +{ + switch(RD_FLD(instr, INSTR_OP3)) + { + case OP3_LDFA: //OP=OP_3 RD, Rs1, {I=0->IMM_ASI, RS2 I=1->SIMM13} + { + if (RD_FLD(instr, INSTR_I)==0) { + printf("LDFA rd=r%d rs1=r%d rs2=r%d immasi=0x%04X", + RD_FLD(instr, INSTR_RD), RD_FLD(instr, INSTR_RS1), + RD_FLD(instr, INSTR_RS2), RD_FLD(instr, INSTR_IMMASI)); + } else { + printf("LDFA rd=r%d rs1=r%d simm13=%d", RD_FLD(instr, INSTR_RD), + RD_FLD(instr, INSTR_RS1), + SIGN_EXTEND13(RD_FLD(instr, INSTR_SIMM13))); + } + return; + } + case OP3_LDDFA: //OP=OP_3 RD, Rs1, {I=0->IMM_ASI, RS2 I=1->SIMM13} + { + if (RD_FLD(instr, INSTR_I)==0) { + printf("LDDFA rd=r%d rs1=r%d rs2=r%d immasi=0x%04X", + RD_FLD(instr, INSTR_RD), RD_FLD(instr, INSTR_RS1), + RD_FLD(instr, INSTR_RS2), RD_FLD(instr, INSTR_IMMASI)); + } else { + printf("LDDFA rd=r%d rs1=r%d simm13=%d", RD_FLD(instr, INSTR_RD), + RD_FLD(instr, INSTR_RS1), + SIGN_EXTEND13(RD_FLD(instr, INSTR_SIMM13))); + } + return; + } + case OP3_LDQFA: //OP=OP_3 RD, Rs1, {I=0->IMM_ASI, RS2 I=1->SIMM13} + { + if (RD_FLD(instr, INSTR_I)==0) { + printf("LDQFA rd=r%d rs1=r%d rs2=r%d immasi=0x%04X", + RD_FLD(instr, INSTR_RD), RD_FLD(instr, INSTR_RS1), + RD_FLD(instr, INSTR_RS2), RD_FLD(instr, INSTR_IMMASI)); + } else { + printf("LDQFA rd=r%d rs1=r%d simm13=%d", RD_FLD(instr, INSTR_RD), + RD_FLD(instr, INSTR_RS1), + SIGN_EXTEND13(RD_FLD(instr, INSTR_SIMM13))); + return; + } + case OP3_LDF: //OP=OP_3 RD, RS1, {I=0->RS2, I=1->SIMM13} RD = 0->31 + { + if (RD_FLD(instr, INSTR_I)==0) { + printf("LDF rd=r%d rs1=r%d rs2=r%d", RD_FLD(instr, INSTR_RD), + RD_FLD(instr, INSTR_RS1),RD_FLD(instr, INSTR_RS2)); + } else { + printf("LDF rd=r%d rs1=r%d simm13=%d", RD_FLD(instr, INSTR_RD), + RD_FLD(instr, INSTR_RS1), + SIGN_EXTEND13(RD_FLD(instr, INSTR_SIMM13))); + } + return; + } + case OP3_LDDF: //OP=OP_3 RD, RS1, {I=0->RS2, I=1->SIMM13} RD ? spec? 5.1.4.1 + { + if (RD_FLD(instr, INSTR_I)==0) { + printf("LDDF rd=r%d rs1=r%d rs2=r%d", RD_FLD(instr, INSTR_RD), + RD_FLD(instr, INSTR_RS1),RD_FLD(instr, INSTR_RS2)); + } else { + printf("LDDF rd=r%d rs1=r%d simm13=%d", RD_FLD(instr, INSTR_RD), + RD_FLD(instr, INSTR_RS1), + SIGN_EXTEND13(RD_FLD(instr, INSTR_SIMM13))); + } + return; + } + case OP3_LDQF: //OP=OP_3 RD, RS1, {I=0->RS2, I=1->SIMM13} RD ? spec? + { + if (RD_FLD(instr, INSTR_I)==0) { + printf("LDQF rd=r%d rs1=r%d rs2=r%d", RD_FLD(instr, INSTR_RD), + RD_FLD(instr, INSTR_RS1),RD_FLD(instr, INSTR_RS2)); + } else { + printf("LDQF rd=r%d rs1=r%d simm13=%d", RD_FLD(instr, INSTR_RD), + RD_FLD(instr, INSTR_RS1), + SIGN_EXTEND13(RD_FLD(instr, INSTR_SIMM13))); + } + return; + } + // **SPECIAL case these 2 instructions have same OP3 field + // RD field determines which ** + case OP3_LDFSR: //OP=OP_3 RD, RS1, {I=0->RS2, I=1->SIMM13} RD = 0 + //case OP3_LDXFSR: //OP=OP_3 RD, RS1, {I=0->RS2, I=1->SIMM13} RD = 1 + { + if (RD_FLD(instr, INSTR_RD)==0) + printf("LDFSR "); + else if (RD_FLD(instr, INSTR_RD)==1) + printf("LDXFSR "); + + if (RD_FLD(instr, INSTR_I)==0) { + printf("rs1=r%d rs2=r%d", RD_FLD(instr, INSTR_RS1), + RD_FLD(instr, INSTR_RS2)); + } else { + printf("rs1=r%d simm13=%d", RD_FLD(instr, INSTR_RS1), + SIGN_EXTEND13(RD_FLD(instr, INSTR_SIMM13))); + } + return; + } + + case OP3_LDSTUBA: //OP=OP_3 RD, RS1 {I=0->RS2, IMM_ASI, I=1->SIMM13} + { + if (RD_FLD(instr, INSTR_I)==0) { + printf("LDSTUBA rd=r%d rs1=r%d rs2=r%d", RD_FLD(instr, INSTR_RD), + RD_FLD(instr, INSTR_RS1),RD_FLD(instr, INSTR_RS2)); + } else { + printf("LDSTUBA rd=r%d rs1=r%d simm13=%d", RD_FLD(instr, INSTR_RD), + RD_FLD(instr, INSTR_RS1), + SIGN_EXTEND13(RD_FLD(instr, INSTR_SIMM13))); + } + return; + } + case OP3_LDSTUB: //OP=OP_3 RD, Rs1 {I=0->RS2, I=1->SIMM13} + { + if (RD_FLD(instr, INSTR_I)==0) { + printf("LDSTUB rd=r%d rs1=r%d rs2=r%d", RD_FLD(instr, INSTR_RD), + RD_FLD(instr, INSTR_RS1),RD_FLD(instr, INSTR_RS2)); + } else { + printf("LDSTUB rd=r%d rs1=r%d simm13=%d", RD_FLD(instr, INSTR_RD), + RD_FLD(instr, INSTR_RS1), + SIGN_EXTEND13(RD_FLD(instr, INSTR_SIMM13))); + } + return; + } + case OP3_STB: //OP=OP_3 RD RS1 {I=0->RS2, I=1->SIMM13} + { + if (RD_FLD(instr, INSTR_I)==0) { + printf("STB rd=r%d rs1=r%d rs2=r%d", RD_FLD(instr, INSTR_RD), + RD_FLD(instr, INSTR_RS1),RD_FLD(instr, INSTR_RS2)); + } else { + printf("STB rd=r%d rs1=r%d simm13=%d", RD_FLD(instr, INSTR_RD), + RD_FLD(instr, INSTR_RS1), + SIGN_EXTEND13(RD_FLD(instr, INSTR_SIMM13))); + } + return; + } + case OP3_STBA: //OP=OP_3 RD RS1 {I=0->RS2 IMM_ASI, I=1->SIMM13} + { + if (RD_FLD(instr, INSTR_I)==0) { + printf("STBA rd=r%d rs1=r%d rs2=r%d immasi=0x%04X", + RD_FLD(instr, INSTR_RD), RD_FLD(instr, INSTR_RS1), + RD_FLD(instr, INSTR_RS2), RD_FLD(instr, INSTR_IMMASI)); + } else { + printf("STBA rd=r%d rs1=r%d simm13=%d", RD_FLD(instr, INSTR_RD), + RD_FLD(instr, INSTR_RS1), + SIGN_EXTEND13(RD_FLD(instr, INSTR_SIMM13))); + } + return; + } + case OP3_STH: //OP=OP_3 RD RS1 {I=0->RS2, I=1->SIMM13} + { + if (RD_FLD(instr, INSTR_I)==0) { + printf("STH rd=r%d rs1=r%d rs2=r%d", RD_FLD(instr, INSTR_RD), + RD_FLD(instr, INSTR_RS1),RD_FLD(instr, INSTR_RS2)); + } else { + printf("STH rd=r%d rs1=r%d simm13=%d", RD_FLD(instr, INSTR_RD), + RD_FLD(instr, INSTR_RS1), + SIGN_EXTEND13(RD_FLD(instr, INSTR_SIMM13))); + } + return; + } + case OP3_STHA: //OP=OP_3 RD RS1 {I=0->RS2 IMM_ASI, I=1->SIMM13} + { + if (RD_FLD(instr, INSTR_I)==0) { + printf("STHA rd=r%d rs1=r%d rs2=r%d immasi=0x%04X", + RD_FLD(instr, INSTR_RD), RD_FLD(instr, INSTR_RS1), + RD_FLD(instr, INSTR_RS2), RD_FLD(instr, INSTR_IMMASI)); + } else { + printf("STHA rd=r%d rs1=r%d simm13=%d", RD_FLD(instr, INSTR_RD), + RD_FLD(instr, INSTR_RS1), + SIGN_EXTEND13(RD_FLD(instr, INSTR_SIMM13))); + } + return; + } + case OP3_STW: //OP=OP_3 RD RS1 {I=0->RS2, I=1->SIMM13} + { + if (RD_FLD(instr, INSTR_I)==0) { + printf("STW rd=r%d rs1=r%d rs2=r%d", RD_FLD(instr, INSTR_RD), + RD_FLD(instr, INSTR_RS1), RD_FLD(instr, INSTR_RS2)); + } else { + printf("STW rd=r%d rs1=r%d simm13=%d", RD_FLD(instr, INSTR_RD), + RD_FLD(instr, INSTR_RS1), + SIGN_EXTEND13(RD_FLD(instr, INSTR_SIMM13))); + } + return; + } + case OP3_STWA: //OP=OP_3 RD RS1 {I=0->RS2 IMM_ASI, I=1->SIMM13} + { + if (RD_FLD(instr, INSTR_I)==0) { + printf("STWA rd=r%d rs1=r%d rs2=r%d immasi=0x%04X", + RD_FLD(instr, INSTR_RD), RD_FLD(instr, INSTR_RS1), + RD_FLD(instr, INSTR_RS2), RD_FLD(instr, INSTR_IMMASI)); + } else { + printf("STWA rd=r%d rs1=r%d simm13=%d", RD_FLD(instr, INSTR_RD), + RD_FLD(instr, INSTR_RS1), + SIGN_EXTEND13(RD_FLD(instr, INSTR_SIMM13))); + } + return; + } + case OP3_STX: //OP=OP_3 RD RS1 {I=0->RS2, I=1->SIMM13} + { + if (RD_FLD(instr, INSTR_I)==0) { + printf("STX rd=r%d rs1=r%d rs2=r%d", RD_FLD(instr, INSTR_RD), + RD_FLD(instr, INSTR_RS1),RD_FLD(instr, INSTR_RS2)); + } else { + printf("STX rd=r%d rs1=r%d simm13=%d", RD_FLD(instr, INSTR_RD), + RD_FLD(instr, INSTR_RS1), + SIGN_EXTEND13(RD_FLD(instr, INSTR_SIMM13))); + } + return; + } + case OP3_STXA: //OP=OP_3 RD RS1 {I=0->RS2 IMM_ASI, I=1->SIMM13} + { + if (RD_FLD(instr, INSTR_I)==0) { + printf("STXA rd=r%d rs1=r%d rs2=r%d immasi=0x%04X", + RD_FLD(instr, INSTR_RD), RD_FLD(instr, INSTR_RS1), + RD_FLD(instr, INSTR_RS2), RD_FLD(instr, INSTR_IMMASI)); + } else { + printf("STXA rd=r%d rs1=r%d simm13=%d", RD_FLD(instr, INSTR_RD), + RD_FLD(instr, INSTR_RS1), + SIGN_EXTEND13(RD_FLD(instr, INSTR_SIMM13))); + } + return; + } + case OP3_STF: //OP=OP_3 RD RS1 {I=0->RS2, I=1->SIMM13} + { + if (RD_FLD(instr, INSTR_I)==0) { + printf("STF rd=r%d rs1=r%d rs2=r%d", RD_FLD(instr, INSTR_RD), + RD_FLD(instr, INSTR_RS1),RD_FLD(instr, INSTR_RS2)); + } else { + printf("STF rd=r%d rs1=r%d simm13=%d", RD_FLD(instr, INSTR_RD), + RD_FLD(instr, INSTR_RS1), + SIGN_EXTEND13(RD_FLD(instr, INSTR_SIMM13))); + } + return; + } + case OP3_STFA: //OP=OP_3 RD RS1 {I=0->RS2 IMM_ASI, I=1->SIMM13} + { + if (RD_FLD(instr, INSTR_I)==0) { + printf("STFA rd=r%d rs1=r%d rs2=r%d immasi=0x%04X", + RD_FLD(instr, INSTR_RD), RD_FLD(instr, INSTR_RS1), + RD_FLD(instr, INSTR_RS2), RD_FLD(instr, INSTR_IMMASI)); + } else { + printf("STFA rd=r%d rs1=r%d simm13=%d", RD_FLD(instr, INSTR_RD), + RD_FLD(instr, INSTR_RS1), + SIGN_EXTEND13(RD_FLD(instr, INSTR_SIMM13))); + } + return; + } + case OP3_STDF: //OP=OP_3 RD RS1 {I=0->RS2, I=1->SIMM13} + { + if (RD_FLD(instr, INSTR_I)==0) { + printf("STDF rd=r%d rs1=r%d rs2=r%d", RD_FLD(instr, INSTR_RD), + RD_FLD(instr, INSTR_RS1),RD_FLD(instr, INSTR_RS2)); + } else { + printf("STDF rd=r%d rs1=r%d simm13=%d", RD_FLD(instr, INSTR_RD), + RD_FLD(instr, INSTR_RS1), + SIGN_EXTEND13(RD_FLD(instr, INSTR_SIMM13))); + } + return; + } + case OP3_STDFA: //OP=OP_3 RD RS1 {I=0->RS2 IMM_ASI, I=1->SIMM13} + { + if (RD_FLD(instr, INSTR_I)==0) { + printf("STDFA rd=r%d rs1=r%d rs2=r%d immasi=0x%04X", + RD_FLD(instr, INSTR_RD), RD_FLD(instr, INSTR_RS1), + RD_FLD(instr, INSTR_RS2), RD_FLD(instr, INSTR_IMMASI)); + } else { + printf("STDFA rd=r%d rs1=r%d simm13=%d", RD_FLD(instr, INSTR_RD), + RD_FLD(instr, INSTR_RS1), + SIGN_EXTEND13(RD_FLD(instr, INSTR_SIMM13))); + } + return; + } + case OP3_STQF: //OP=OP_3 RD RS1 {I=0->RS2, I=1->SIMM13} + { + if (RD_FLD(instr, INSTR_I)==0) { + printf("STQF rd=r%d rs1=r%d rs2=r%d", RD_FLD(instr, INSTR_RD), + RD_FLD(instr, INSTR_RS1),RD_FLD(instr, INSTR_RS2)); + } else { + printf("STQF rd=r%d rs1=r%d simm13=%d", RD_FLD(instr, INSTR_RD), + RD_FLD(instr, INSTR_RS1), + SIGN_EXTEND13(RD_FLD(instr, INSTR_SIMM13))); + } + return; + } + case OP3_STQFA: //OP=OP_3 RD RS1 {I=0->RS2 IMM_ASI, I=1->SIMM13} + { + if (RD_FLD(instr, INSTR_I)==0) { + printf("STQFA rd=r%d rs1=r%d rs2=r%d immasi=0x%04X", + RD_FLD(instr, INSTR_RD), RD_FLD(instr, INSTR_RS1), + RD_FLD(instr, INSTR_RS2), RD_FLD(instr, INSTR_IMMASI)); + } else { + printf("STQFA rd=r%d rs1=r%d simm13=%d", RD_FLD(instr, INSTR_RD), + RD_FLD(instr, INSTR_RS1), + SIGN_EXTEND13(RD_FLD(instr, INSTR_SIMM13))); + } + return; + } + + // ** SPECIAL CASE ** These 2 opcodes have same OP3 field.. RD determines + case OP3_STFSR: //OP=OP_3 RD=0 RS1 {I=0->RS2, I=1->SIMM13} + //case OP3_STXFSR: //OP=OP_3 RD=1 RS1 {I=0->RS2, I=1->SIMM13} + { + if (RD_FLD(instr, INSTR_RD)==0) + printf("STFSR "); + else if (RD_FLD(instr, INSTR_RD)==1) + printf("STXFSR "); + + if (RD_FLD(instr, INSTR_I)==0) { + printf("rs1=r%d rs2=r%d", RD_FLD(instr, INSTR_RS1), + RD_FLD(instr, INSTR_RS2)); + } else { + printf("rs1=r%d simm13=%d", RD_FLD(instr, INSTR_RS1), + SIGN_EXTEND13(RD_FLD(instr, INSTR_SIMM13))); + + return; + } + + case OP3_LDSB: //OP=OP_3,RD RS1, {I=0->RS2, I=1->SIMM13} + { + if (RD_FLD(instr, INSTR_I)==0) { + printf("LDSB rd=r%d rs1=r%d rs2=r%d", RD_FLD(instr, INSTR_RD), + RD_FLD(instr, INSTR_RS1),RD_FLD(instr, INSTR_RS2)); + } else { + printf("LDSB rd=r%d rs1=r%d simm13=%d", RD_FLD(instr, INSTR_RD), + RD_FLD(instr, INSTR_RS1), + SIGN_EXTEND13(RD_FLD(instr, INSTR_SIMM13))); + } + return; + } + case OP3_LDSH: //OP=OP_3,RD RS1, {I=0->RS2, I=1->SIMM13} + { + if (RD_FLD(instr, INSTR_I)==0) { + printf("LDSH rd=r%d rs1=r%d rs2=r%d", RD_FLD(instr, INSTR_RD), + RD_FLD(instr, INSTR_RS1),RD_FLD(instr, INSTR_RS2)); + } else { + printf("LDSH rd=r%d rs1=r%d simm13=%d", RD_FLD(instr, INSTR_RD), + RD_FLD(instr, INSTR_RS1), + SIGN_EXTEND13(RD_FLD(instr, INSTR_SIMM13))); + } + return; + } + case OP3_LDSW: //OP=OP_3,RD RS1, {I=0->RS2, I=1->SIMM13} + { + if (RD_FLD(instr, INSTR_I)==0) { + printf("LDSW rd=r%d rs1=r%d rs2=r%d", RD_FLD(instr, INSTR_RD), + RD_FLD(instr, INSTR_RS1),RD_FLD(instr, INSTR_RS2)); + } else { + printf("LDSW rd=r%d rs1=r%d simm13=%d", RD_FLD(instr, INSTR_RD), + RD_FLD(instr, INSTR_RS1), + SIGN_EXTEND13(RD_FLD(instr, INSTR_SIMM13))); + } + return; + } + case OP3_LDUB: //OP=OP_3,RD RS1, {I=0->RS2, I=1->SIMM13} + { + if (RD_FLD(instr, INSTR_I)==0) { + printf("LDUB rd=r%d rs1=r%d rs2=r%d", RD_FLD(instr, INSTR_RD), + RD_FLD(instr, INSTR_RS1),RD_FLD(instr, INSTR_RS2)); + } else { + printf("LDUB rd=r%d rs1=r%d simm13=%d", RD_FLD(instr, INSTR_RD), + RD_FLD(instr, INSTR_RS1), + SIGN_EXTEND13(RD_FLD(instr, INSTR_SIMM13))); + } + return; + } + case OP3_LDUH: //OP=OP_3,RD RS1, {I=0->RS2, I=1->SIMM13} + { + if (RD_FLD(instr, INSTR_I)==0) { + printf("LDUH rd=r%d rs1=r%d rs2=r%d", RD_FLD(instr, INSTR_RD), + RD_FLD(instr, INSTR_RS1),RD_FLD(instr, INSTR_RS2)); + } else { + printf("LDUH rd=r%d rs1=r%d simm13=%d", RD_FLD(instr, INSTR_RD), + RD_FLD(instr, INSTR_RS1), + SIGN_EXTEND13(RD_FLD(instr, INSTR_SIMM13))); + } + return; + } + case OP3_LDUW: //OP=OP_3,RD RS1, {I=0->RS2, I=1->SIMM13} + { + if (RD_FLD(instr, INSTR_I)==0) { + printf("LDUW rd=r%d rs1=r%d rs2=r%d", RD_FLD(instr, INSTR_RD), + RD_FLD(instr, INSTR_RS1),RD_FLD(instr, INSTR_RS2)); + } else { + printf("LDUW rd=r%d rs1=r%d simm13=%d", RD_FLD(instr, INSTR_RD), + RD_FLD(instr, INSTR_RS1), + SIGN_EXTEND13(RD_FLD(instr, INSTR_SIMM13))); + } + return; + } + case OP3_LDX: //OP=OP_3,RD RS1, {I=0->RS2, I=1->SIMM13} + { + if (RD_FLD(instr, INSTR_I)==0) + printf("LDX rd=r%d rs1=r%d rs2=r%d", RD_FLD(instr, INSTR_RD), + RD_FLD(instr, INSTR_RS1),RD_FLD(instr, INSTR_RS2)); + } else { + printf("LDX rd=r%d rs1=r%d simm13=%d", RD_FLD(instr, INSTR_RD), + RD_FLD(instr, INSTR_RS1), + SIGN_EXTEND13(RD_FLD(instr, INSTR_SIMM13))); + } + return; + } + case OP3_LDSBA: //OP=OP_3,RD RS1, {I=0->RS2,IMM_ASI, I=1->SIMM13} + { + if (RD_FLD(instr, INSTR_I)==0) { + printf("LDSBA rd=r%d rs1=r%d rs2=r%d immasi=0x%04X", + RD_FLD(instr, INSTR_RD), RD_FLD(instr, INSTR_RS1), + RD_FLD(instr, INSTR_RS2), RD_FLD(instr, INSTR_IMMASI)); + } else { + printf("LDSBA rd=r%d rs1=r%d simm13=%d", RD_FLD(instr, INSTR_RD), + RD_FLD(instr, INSTR_RS1), + SIGN_EXTEND13(RD_FLD(instr, INSTR_SIMM13))); + } + return; + } + case OP3_LDSHA: //OP=OP_3, RS1, {I=0->RS2,IMM_ASI, I=1->SIMM13} + { + if (RD_FLD(instr, INSTR_I)==0) { + printf("LDSHA rd=r%d rs1=r%d rs2=r%d immasi=0x%04X", + RD_FLD(instr, INSTR_RD), RD_FLD(instr, INSTR_RS1), + RD_FLD(instr, INSTR_RS2), RD_FLD(instr, INSTR_IMMASI)); + } else { + printf("LDSHA rd=r%d rs1=r%d simm13=%d", RD_FLD(instr, INSTR_RD), + RD_FLD(instr, INSTR_RS1), + SIGN_EXTEND13(RD_FLD(instr, INSTR_SIMM13))); + } + return; + } + case OP3_LDSWA: //OP=OP_3, RS1, {I=0->RS2,IMM_ASI, I=1->SIMM13} + { + if (RD_FLD(instr, INSTR_I)==0) { + printf("LDSWA rd=r%d rs1=r%d rs2=r%d immasi=0x%04X", + RD_FLD(instr, INSTR_RD), RD_FLD(instr, INSTR_RS1), + RD_FLD(instr, INSTR_RS2), RD_FLD(instr, INSTR_IMMASI)); + } else { + printf("LDSWA rd=r%d rs1=r%d simm13=%d", RD_FLD(instr, INSTR_RD), + RD_FLD(instr, INSTR_RS1), + SIGN_EXTEND13(RD_FLD(instr, INSTR_SIMM13))); + } + return; + } + case OP3_LDUBA: //OP=OP_3, RS1, {I=0->RS2,IMM_ASI, I=1->SIMM13} + { + if (RD_FLD(instr, INSTR_I)==0) { + printf("LDUBA rd=r%d rs1=r%d rs2=r%d immasi=0x%04X", + RD_FLD(instr, INSTR_RD), RD_FLD(instr, INSTR_RS1), + RD_FLD(instr, INSTR_RS2), RD_FLD(instr, INSTR_IMMASI)); + } else { + printf("LDUBA rd=r%d rs1=r%d simm13=%d", RD_FLD(instr, INSTR_RD), + RD_FLD(instr, INSTR_RS1), + SIGN_EXTEND13(RD_FLD(instr, INSTR_SIMM13))); + } + return; + } + case OP3_LDUHA: //OP=OP_3, RS1, {I=0->RS2,IMM_ASI, I=1->SIMM13} + { + if (RD_FLD(instr, INSTR_I)==0) { + printf("LDUHA rd=r%d rs1=r%d rs2=r%d immasi=0x%04X", + RD_FLD(instr, INSTR_RD), RD_FLD(instr, INSTR_RS1), + RD_FLD(instr, INSTR_RS2), RD_FLD(instr, INSTR_IMMASI)); + } else { + printf("LDUHA rd=r%d rs1=r%d simm13=%d", RD_FLD(instr, INSTR_RD), + RD_FLD(instr, INSTR_RS1), + SIGN_EXTEND13(RD_FLD(instr, INSTR_SIMM13))); + } + return; + } + case OP3_LDUWA: //OP=OP_3, RS1, {I=0->RS2,IMM_ASI, I=1->SIMM13} + { + if (RD_FLD(instr, INSTR_I)==0) { + printf("LDUWA rd=r%d rs1=r%d rs2=r%d immasi=0x%04X", + RD_FLD(instr, INSTR_RD), RD_FLD(instr, INSTR_RS1), + RD_FLD(instr, INSTR_RS2), RD_FLD(instr, INSTR_IMMASI)); + } else { + printf("LDUWA rd=r%d rs1=r%d simm13=%d", RD_FLD(instr, INSTR_RD), + RD_FLD(instr, INSTR_RS1), + SIGN_EXTEND13(RD_FLD(instr, INSTR_SIMM13))); + } + return; + } + case OP3_LDXA: //OP=OP_3, RS1, {I=0->RS2,IMM_ASI, I=1->SIMM13} + { + if (RD_FLD(instr, INSTR_I)==0) { + printf("LDXA rd=r%d rs1=r%d rs2=r%d immasi=0x%04X", + RD_FLD(instr, INSTR_RD), RD_FLD(instr, INSTR_RS1), + RD_FLD(instr, INSTR_RS2), RD_FLD(instr, INSTR_IMMASI)); + } else { + printf("LDXA rd=r%d rs1=r%d simm13=%d", RD_FLD(instr, INSTR_RD), + RD_FLD(instr, INSTR_RS1), + SIGN_EXTEND13(RD_FLD(instr, INSTR_SIMM13))); + } + return; + } + case OP3_LDDA: //OP=OP_3, RS1, {I=0->RS2,IMM_ASI, I=1->SIMM13} + { + if (RD_FLD(instr, INSTR_I)==0) { + printf("LDDA rd=r%d rs1=r%d rs2=r%d immasi=0x%04X", + RD_FLD(instr, INSTR_RD), RD_FLD(instr, INSTR_RS1), + RD_FLD(instr, INSTR_RS2), RD_FLD(instr, INSTR_IMMASI)); + } else { + printf("LDDA rd=r%d rs1=r%d simm13=%d", RD_FLD(instr, INSTR_RD), + RD_FLD(instr, INSTR_RS1), + SIGN_EXTEND13(RD_FLD(instr, INSTR_SIMM13))); + } + return; + } + case OP3_PREFETCH: //OP=OP_3 FCN, RS1 {I=0->RS2, I=1->SIMM13} + { + if (RD_FLD(instr, INSTR_I)==0) { + printf("PREFETCH rd=r%d rs1=r%d rs2=r%d", RD_FLD(instr, INSTR_RD), + RD_FLD(instr, INSTR_RS1),RD_FLD(instr, INSTR_RS2)); + } else { + printf("PREFETCH rd=r%d rs1=r%d simm13=%d", RD_FLD(instr, INSTR_RD), + RD_FLD(instr, INSTR_RS1), + SIGN_EXTEND13(RD_FLD(instr, INSTR_SIMM13))); + } + return; + } + case OP3_PREFETCHA: //OP=OP_3 FCN, RS1 {I=0->RS2+IMM_ASI, I=1->SIMM13} + { + if (RD_FLD(instr, INSTR_I)==0) { + printf("PREFETCHA rd=r%d rs1=r%d rs2=r%d immasi=0x%04X", + RD_FLD(instr, INSTR_RD), RD_FLD(instr, INSTR_RS1), + RD_FLD(instr, INSTR_RS2), RD_FLD(instr, INSTR_IMMASI)); + } else { + printf("PREFETCHA rd=r%d rs1=r%d simm13=%d", RD_FLD(instr, INSTR_RD), + RD_FLD(instr, INSTR_RS1), + SIGN_EXTEND13(RD_FLD(instr, INSTR_SIMM13))); + return; + } + case OP3_CASA: //OP=OP_3 RD RS1 RS2{I=0->IMM_ASI, I=1->*} + { + printf("CASA rs1=r%d rs2=r%d rd=r%d", RD_FLD(instr, INSTR_RS1), + RD_FLD(instr, INSTR_RS1), RD_FLD(instr, INSTR_RD)); + if (RD_FLD(instr, INSTR_I)==0) + printf("imm=0x%04X", RD_FLD(instr, INSTR_IMMASI)); + return; + } + case OP3_CASXA: //OP=OP_3 RD RS1 RS2{I=0->IMM_ASI, I=1->*} + { + printf("CASXA rs1=r%d rs2=r%d rd=r%d", RD_FLD(instr, INSTR_RS1), + RD_FLD(instr, INSTR_RS1), RD_FLD(instr, INSTR_RD)); + if (RD_FLD(instr, INSTR_I)==0) + printf("imm=0x%04X", RD_FLD(instr, INSTR_IMMASI)); + return; + } + } + + printf("Unknown OP_3: OP3 = %08X", RD_FLD(instr, INSTR_OP3)); +} + +#define FLIP_ENDIAN(x) (((x & 255) << 24) \ + | (((x >> 8) & 255) << 16) \ + | (((x >> 16) & 255) << 8) \ + | ((x >> 24) & 255)) + + +void sparc_print(unsigned instr) +{ + printf("%08X: ", instr); + if (RD_FLD(instr,INSTR_OP)==OP_CALL) + printf("CALL disp:+%08X", instr & 0x3FFFFFFF); + else if (RD_FLD(instr,INSTR_OP)==OP_BRANCH) + sparc_printbr(instr); + else if (RD_FLD(instr,INSTR_OP)==OP_2) + sparc_print2(instr); + else if (RD_FLD(instr,INSTR_OP)==OP_3) + sparc_print3(instr); + printf("\n"); +} + + +void main() +{ + sparc_print(0x9DE3BF88); + sparc_print(0xF027A044); + sparc_print(0xF227A048); + sparc_print(0xD007A044); + sparc_print(0xD027BFEC); + sparc_print(0xD007BFEC); + sparc_print(0x933A2001); + sparc_print(0xD227BFEC); + sparc_print(0xD007BFEC); + sparc_print(0x932A2001); + sparc_print(0xD227BFEC); + sparc_print(0xD007BFEC); + sparc_print(0x80A22000); + sparc_print(0x02800005); + sparc_print(0x01000000); + sparc_print(0xD007BFEC); + sparc_print(0x92022001); + sparc_print(0xD227BFEC); + sparc_print(0xD007BFEC); + sparc_print(0x9202200A); + sparc_print(0xD227BFEC); + sparc_print(0xD007BFEC); + sparc_print(0x94100008); + sparc_print(0x932AA002); + sparc_print(0x92024008); + sparc_print(0x912A6001); + sparc_print(0xD027BFEC); + sparc_print(0xD007A044); + sparc_print(0xD207BFEC); + getchar(); +} From brukman at neo.cs.uiuc.edu Tue Nov 12 20:40:01 2002 From: brukman at neo.cs.uiuc.edu (Misha Brukman) Date: Tue Nov 12 20:40:01 2002 Subject: [llvm-commits] CVS: llvm/lib/Reoptimizer/BinInterface/machine.h Message-ID: <200211130241.gAD2fEk04189@neo.cs.uiuc.edu> Changes in directory llvm/lib/Reoptimizer/BinInterface: machine.h updated: 1.1 -> 1.2 --- Log message: Wrap code at 80 chars per line, and line it up so it's readable. --- Diffs of the changes: Index: llvm/lib/Reoptimizer/BinInterface/machine.h diff -u llvm/lib/Reoptimizer/BinInterface/machine.h:1.1 llvm/lib/Reoptimizer/BinInterface/machine.h:1.2 --- llvm/lib/Reoptimizer/BinInterface/machine.h:1.1 Fri Nov 8 04:38:13 2002 +++ llvm/lib/Reoptimizer/BinInterface/machine.h Tue Nov 12 20:41:04 2002 @@ -1,15 +1,17 @@ -//***************************************************************************** -// Machine Definition File -// -// -// 2002 Cameron Buschardt -//***************************************************************************** - -#ifndef __MACHINE_H__ -#define __MACHINE_H__ - -#define MACHINE_CACHELINE 16 -#define FLIP_ENDIAN32(x) (((x & 255) << 24) | (((x >> 8) & 255) << 16) | (((x >> 16) & 255) << 8) | ((x >> 24) & 255)) - - -#endif \ No newline at end of file +//***************************************************************************** +// Machine Definition File +// +// +// 2002 Cameron Buschardt +//***************************************************************************** + +#ifndef __MACHINE_H__ +#define __MACHINE_H__ + +#define MACHINE_CACHELINE 16 +#define FLIP_ENDIAN32(x) (((x & 255) << 24) \ + | (((x >> 8) & 255) << 16) \ + | (((x >> 16) & 255) << 8) \ + | ((x >> 24) & 255)) + +#endif From brukman at neo.cs.uiuc.edu Tue Nov 12 20:43:00 2002 From: brukman at neo.cs.uiuc.edu (Misha Brukman) Date: Tue Nov 12 20:43:00 2002 Subject: [llvm-commits] CVS: llvm/lib/Reoptimizer/BinInterface/analyze.cpp analyze.h Message-ID: <200211130244.gAD2iw904212@neo.cs.uiuc.edu> Changes in directory llvm/lib/Reoptimizer/BinInterface: analyze.cpp updated: 1.1 -> 1.2 analyze.h updated: 1.1 -> 1.2 --- Log message: * Tabs to spaces * Got rid of ^M (Windows EOL) * #include sparc9.h not .hp * Wrap code at 80 chars per line * Fixed comments at top of file --- Diffs of the changes: Index: llvm/lib/Reoptimizer/BinInterface/analyze.cpp diff -u llvm/lib/Reoptimizer/BinInterface/analyze.cpp:1.1 llvm/lib/Reoptimizer/BinInterface/analyze.cpp:1.2 --- llvm/lib/Reoptimizer/BinInterface/analyze.cpp:1.1 Fri Nov 8 04:38:12 2002 +++ llvm/lib/Reoptimizer/BinInterface/analyze.cpp Tue Nov 12 20:44:48 2002 @@ -1,4 +1,4 @@ -//***************************************************************************** +//===-----------------------------------------------------------*- C++ -*--===// // SPARC Instruction Analyzer // // Implementation of Analysis API @@ -6,195 +6,194 @@ // * Need to add support for register conditional branches // // 2002 Cameron Buschardt -//***************************************************************************** +//===----------------------------------------------------------------------===// #include #include - -#include "sparc9.hp" // include the preprocessed header -#include "analyze.h" #include +#include "sparc9.h" +#include "analyze.h" unsigned sparc_analyzebr(unsigned instr) { - // look at the OP2 field - if (RD_FLD(instr, INSTR_OP2)==OP2_SETHI) - { - if (RD_FLD(instr, INSTR_RD) == 0) - return 0; // This is the special encoding for NOP - else - return IF_RD; - } - else if (RD_FLD(instr, INSTR_OP2)==OP2_BICC) - { - return IF_RCC | IF_BR; - } - else if (RD_FLD(instr, INSTR_OP2)==OP2_BPR) - return IF_RCC; - else{ - printf("Unknown:OP=0b00 OP2 = 0x%04X\n", RD_FLD(instr, INSTR_OP2)); - assert(0); - return 0; - } + // look at the OP2 field + if (RD_FLD(instr, INSTR_OP2)==OP2_SETHI) + { + if (RD_FLD(instr, INSTR_RD) == 0) + return 0; // This is the special encoding for NOP + else + return IF_RD; + } + else if (RD_FLD(instr, INSTR_OP2)==OP2_BICC) + { + return IF_RCC | IF_BR; + } + else if (RD_FLD(instr, INSTR_OP2)==OP2_BPR) + return IF_RCC; + else{ + printf("Unknown:OP=0b00 OP2 = 0x%04X\n", RD_FLD(instr, INSTR_OP2)); + assert(0); + return 0; + } } unsigned sparc_analyze_c2(unsigned instr) { - switch(RD_FLD(instr, INSTR_OP3)) - { - case OP3_DONERETRY: - return 0; - - case OP3_FCMP: - case OP3_FPU: - assert(0); - return 0; - - case OP3_FLUSHW: //OP=OP_2 I = 0 - return 0; - - case OP3_FLUSH: //OP=OP_2 RS1 {I=0 -> IF_RS2, I=1->simm13} - if (RD_FLD(instr, INSTR_I) == 0) - return IF_RS1 | IF_RS2; - else - return IF_RS1; - - case OP3_JMPL: //OP=OP_2 RD, IF_RS1 {I=0-> IF_RS2, I=1->SIMM13} - case OP3_ADD: - case OP3_AND: - case OP3_OR: - case OP3_XOR: - case OP3_SUB: - case OP3_ANDN: - case OP3_ORN: - case OP3_XNOR: - case OP3_MULX: - case OP3_SDIVX: - case OP3_UDIVX: - case OP3_SLL: - case OP3_SRL: - case OP3_SRA: - case OP3_SAVE: - case OP3_RETURN: - case OP3_RESTORE: - if (RD_FLD(instr, INSTR_I) == 0) - return IF_RD | IF_RS1 | IF_RS2; - else - return IF_RD | IF_RS1; - - case OP3_ADDC: - case OP3_SUBC: - if (RD_FLD(instr, INSTR_I) == 0) - return IF_RD| IF_RS1 | IF_RS2 | IF_RCC; - else - return IF_RD| IF_RS1 | IF_RCC; - - - - case OP3_XNORcc: - case OP3_ANDNcc: - case OP3_ANDcc: - case OP3_ADDcc: - case OP3_ORcc: - case OP3_ORNcc: - case OP3_SUBcc: - case OP3_XORcc: - if (RD_FLD(instr, INSTR_I) == 0) - return IF_RD | IF_RS1 | IF_RS2 | IF_WCC; - else - return IF_RD | IF_RS1 | IF_WCC; - - case OP3_ADDCcc: - case OP3_SUBCcc: - if (RD_FLD(instr, INSTR_I) == 0) - return IF_RD | IF_RS1 | IF_RS2 | IF_WCC | IF_RCC; - else - return IF_RD | IF_RS1 | IF_WCC | IF_RCC; - - default: - printf("Unknown:OP=0b10 OP3 = 0x%04X\n", RD_FLD(instr, INSTR_OP3)); - assert(0); - - } + switch(RD_FLD(instr, INSTR_OP3)) + { + case OP3_DONERETRY: + return 0; + + case OP3_FCMP: + case OP3_FPU: + assert(0); + return 0; + + case OP3_FLUSHW: //OP=OP_2 I = 0 + return 0; + + case OP3_FLUSH: //OP=OP_2 RS1 {I=0 -> IF_RS2, I=1->simm13} + if (RD_FLD(instr, INSTR_I) == 0) + return IF_RS1 | IF_RS2; + else + return IF_RS1; + + case OP3_JMPL: //OP=OP_2 RD, IF_RS1 {I=0-> IF_RS2, I=1->SIMM13} + case OP3_ADD: + case OP3_AND: + case OP3_OR: + case OP3_XOR: + case OP3_SUB: + case OP3_ANDN: + case OP3_ORN: + case OP3_XNOR: + case OP3_MULX: + case OP3_SDIVX: + case OP3_UDIVX: + case OP3_SLL: + case OP3_SRL: + case OP3_SRA: + case OP3_SAVE: + case OP3_RETURN: + case OP3_RESTORE: + if (RD_FLD(instr, INSTR_I) == 0) + return IF_RD | IF_RS1 | IF_RS2; + else + return IF_RD | IF_RS1; + + case OP3_ADDC: + case OP3_SUBC: + if (RD_FLD(instr, INSTR_I) == 0) + return IF_RD| IF_RS1 | IF_RS2 | IF_RCC; + else + return IF_RD| IF_RS1 | IF_RCC; + + + + case OP3_XNORcc: + case OP3_ANDNcc: + case OP3_ANDcc: + case OP3_ADDcc: + case OP3_ORcc: + case OP3_ORNcc: + case OP3_SUBcc: + case OP3_XORcc: + if (RD_FLD(instr, INSTR_I) == 0) + return IF_RD | IF_RS1 | IF_RS2 | IF_WCC; + else + return IF_RD | IF_RS1 | IF_WCC; + + case OP3_ADDCcc: + case OP3_SUBCcc: + if (RD_FLD(instr, INSTR_I) == 0) + return IF_RD | IF_RS1 | IF_RS2 | IF_WCC | IF_RCC; + else + return IF_RD | IF_RS1 | IF_WCC | IF_RCC; + + default: + printf("Unknown:OP=0b10 OP3 = 0x%04X\n", RD_FLD(instr, INSTR_OP3)); + assert(0); + + } } unsigned sparc_analyze3(unsigned instr) { - switch(RD_FLD(instr, INSTR_OP3)) - { - //OP=OP_3 RD, IF_RS1 {I=0->IF_RS2, I=1->SIMM13} - case OP3_STB: - case OP3_STH: - case OP3_STW: - case OP3_STX: - case OP3_LDSB: - case OP3_LDSH: - case OP3_LDSW: - case OP3_LDUB: - case OP3_LDUH: - case OP3_LDUW: - case OP3_LDX: - case OP3_LDSTUB: - case OP3_STFA: - case OP3_STDFA: - case OP3_STQFA: - if (RD_FLD(instr, INSTR_I) == 0) - return IF_RD | IF_RS1 | IF_RS2; - else - return IF_RD | IF_RS1; - - case OP3_CASXA: - case OP3_CASA: - return IF_RD | IF_RS1 | IF_RS2; - - case OP3_PREFETCHA: - case OP3_PREFETCH: - if (RD_FLD(instr, INSTR_I) == 0) - return IF_RS1 | IF_RS2; - else - return IF_RS1; - - default: - printf("Unknown OP_3: OP3 = %08X\n", RD_FLD(instr, INSTR_OP3)); - assert(0); - } + switch(RD_FLD(instr, INSTR_OP3)) + { + //OP=OP_3 RD, IF_RS1 {I=0->IF_RS2, I=1->SIMM13} + case OP3_STB: + case OP3_STH: + case OP3_STW: + case OP3_STX: + case OP3_LDSB: + case OP3_LDSH: + case OP3_LDSW: + case OP3_LDUB: + case OP3_LDUH: + case OP3_LDUW: + case OP3_LDX: + case OP3_LDSTUB: + case OP3_STFA: + case OP3_STDFA: + case OP3_STQFA: + if (RD_FLD(instr, INSTR_I) == 0) + return IF_RD | IF_RS1 | IF_RS2; + else + return IF_RD | IF_RS1; + + case OP3_CASXA: + case OP3_CASA: + return IF_RD | IF_RS1 | IF_RS2; + + case OP3_PREFETCHA: + case OP3_PREFETCH: + if (RD_FLD(instr, INSTR_I) == 0) + return IF_RS1 | IF_RS2; + else + return IF_RS1; + + default: + printf("Unknown OP_3: OP3 = %08X\n", RD_FLD(instr, INSTR_OP3)); + assert(0); + } } unsigned sparc_analyze(unsigned instr) { - if (RD_FLD(instr,INSTR_OP)==OP_2) - return sparc_analyze_c2(instr); - else if (RD_FLD(instr,INSTR_OP)==OP_3) - return sparc_analyze3(instr); - else if (RD_FLD(instr,INSTR_OP)==OP_BRANCH) - return sparc_analyzebr(instr); - else - return 0; + if (RD_FLD(instr,INSTR_OP)==OP_2) + return sparc_analyze_c2(instr); + else if (RD_FLD(instr,INSTR_OP)==OP_3) + return sparc_analyze3(instr); + else if (RD_FLD(instr,INSTR_OP)==OP_BRANCH) + return sparc_analyzebr(instr); + else + return 0; } unsigned sparc_getwrites(unsigned mask, unsigned instr) { - if (mask & IF_RD) - return (1 << RD_FLD(instr, INSTR_RD)); - else - return 0; + if (mask & IF_RD) + return (1 << RD_FLD(instr, INSTR_RD)); + else + return 0; } unsigned sparc_getreads (unsigned mask, unsigned instr) { - unsigned m = 0; - - if (mask & IF_RS1) - m |= (1 << RD_FLD(instr, INSTR_RS1)); + unsigned m = 0; + + if (mask & IF_RS1) + m |= (1 << RD_FLD(instr, INSTR_RS1)); - if (mask & IF_RS2) - m |= (1 << RD_FLD(instr, INSTR_RS2)); + if (mask & IF_RS2) + m |= (1 << RD_FLD(instr, INSTR_RS2)); - return m; + return m; } -unsigned sparc_getcc (unsigned mask, unsigned instr) // bit 0 -> CC READ , bit 1 -> CC write +// bit 0 -> CC READ , bit 1 -> CC write +unsigned sparc_getcc (unsigned mask, unsigned instr) { - return (mask & (IF_WCC | IF_RCC)); + return (mask & (IF_WCC | IF_RCC)); } - Index: llvm/lib/Reoptimizer/BinInterface/analyze.h diff -u llvm/lib/Reoptimizer/BinInterface/analyze.h:1.1 llvm/lib/Reoptimizer/BinInterface/analyze.h:1.2 --- llvm/lib/Reoptimizer/BinInterface/analyze.h:1.1 Fri Nov 8 04:38:12 2002 +++ llvm/lib/Reoptimizer/BinInterface/analyze.h Tue Nov 12 20:44:48 2002 @@ -1,28 +1,29 @@ -//***************************************************************************** +//===-----------------------------------------------------------*- C++ -*--===// // SPARC Instruction Analyzer // // Definitions of Analysis API // // 2002 Cameron Buschardt -//***************************************************************************** - -#ifndef __ANALYZE__ -#define __ANALYZE__ - -#define IF_RS1 1 // READ from RS1 -#define IF_RS2 2 // READ from RS2 -#define IF_RD 4 // WRITE to RC -#define IF_BR 8 // BRANCH -#define IF_WCC 16 // write to condition code -#define IF_RCC 32 // read from condition code -#define IF_USR 64 // first user IF instr - -// parse instruction -unsigned sparc_analyze(unsigned instr); - -// use these command to expand the information return by analyze +//===----------------------------------------------------------------------===// + +#ifndef __ANALYZE__ +#define __ANALYZE__ + +#define IF_RS1 1 // READ from RS1 +#define IF_RS2 2 // READ from RS2 +#define IF_RD 4 // WRITE to RC +#define IF_BR 8 // BRANCH +#define IF_WCC 16 // write to condition code +#define IF_RCC 32 // read from condition code +#define IF_USR 64 // first user IF instr + +// parse instruction +unsigned sparc_analyze(unsigned instr); + +// use these command to expand the information return by analyze unsigned sparc_getwrites(unsigned mask, unsigned instr); unsigned sparc_getreads (unsigned mask, unsigned instr); -unsigned sparc_getcc (unsigned mask, unsigned instr); // returns a bitmask containing RCC or WCC - -#endif \ No newline at end of file +// returns a bitmask containing RCC or WCC +unsigned sparc_getcc (unsigned mask, unsigned instr); + +#endif From brukman at neo.cs.uiuc.edu Tue Nov 12 20:46:01 2002 From: brukman at neo.cs.uiuc.edu (Misha Brukman) Date: Tue Nov 12 20:46:01 2002 Subject: [llvm-commits] CVS: llvm/lib/Reoptimizer/BinInterface/sparcdis.cpp binproc.cpp Message-ID: <200211130247.gAD2lOO04233@neo.cs.uiuc.edu> Changes in directory llvm/lib/Reoptimizer/BinInterface: sparcdis.cpp updated: 1.1 -> 1.2 binproc.cpp updated: 1.2 -> 1.3 --- Log message: Tabs to spaces, fixed code layout, comment header at top of file. --- Diffs of the changes: Index: llvm/lib/Reoptimizer/BinInterface/sparcdis.cpp diff -u llvm/lib/Reoptimizer/BinInterface/sparcdis.cpp:1.1 llvm/lib/Reoptimizer/BinInterface/sparcdis.cpp:1.2 --- llvm/lib/Reoptimizer/BinInterface/sparcdis.cpp:1.1 Fri Nov 8 04:38:14 2002 +++ llvm/lib/Reoptimizer/BinInterface/sparcdis.cpp Tue Nov 12 20:47:14 2002 @@ -1,452 +1,481 @@ -//***************************************************************************** +//===-----------------------------------------------------------*- C++ -*--===// // SPARC Disassembler // // // // 2002 Cameron Buschardt -//***************************************************************************** +//===----------------------------------------------------------------------===// #include #include -#include "sparc9.hp" // include the preprocessed header +#include "sparc9.h" void sparc_printbr(unsigned instr) { - // look at the OP2 field - if (RD_FLD(instr,INSTR_OP2)==OP2_ILLTRAP) - printf("ILLTRAP .. "); - else if (RD_FLD(instr, INSTR_OP2)==OP2_SETHI) - { - if (RD_FLD(instr, INSTR_RD) == 0) - printf("NOP"); - else - printf("SETHI %%hi(%08X), r%d", RD_FLD(instr, INSTR_IMM22) << 10, RD_FLD(instr, INSTR_RD)); - } - else if (RD_FLD(instr, INSTR_OP2)==OP2_BICC) - { - printf("%s disp:%08X",icond_names[RD_FLD(instr, INSTR_COND_H)], SIGN_EXTEND(RD_FLD(instr,INSTR_DISP22),22)); - } - else if (RD_FLD(instr, INSTR_OP2)==OP2_BPR) - { - //A, RCOND_H, D16HI, P, RS1, D16LO - printf("P%s%s%s r%d, %06X " , rcond_names[RD_FLD(instr, INSTR_RCOND_H)], - RD_FLD(instr, INSTR_A) ? ",a" : "", - RD_FLD(instr, INSTR_P) ? ",pt" : ",pn", - RD_FLD(instr, INSTR_RS1), - RD_D16(instr) - ); - } - else if (RD_FLD(instr, INSTR_OP2)==OP2_FB) - { - // cond, A, disp22 - printf("%s%s %08X", fcond_names[RD_FLD(instr, INSTR_COND_H)], - RD_FLD(instr, INSTR_A) ? ",a" : "", - RD_FLD(instr, INSTR_DISP22)); - } - else if (RD_FLD(instr, INSTR_OP2)==OP2_FBP) - { - // - } - else{ - printf("Unknown:OP=0b00 OP2 = 0x%04X", RD_FLD(instr, INSTR_OP2)); - } + // look at the OP2 field + if (RD_FLD(instr,INSTR_OP2)==OP2_ILLTRAP) { + printf("ILLTRAP .. "); + } else if (RD_FLD(instr, INSTR_OP2)==OP2_SETHI) { + if (RD_FLD(instr, INSTR_RD) == 0) + printf("NOP"); + else + printf("SETHI %%hi(%08X), r%d", + RD_FLD(instr, INSTR_IMM22) << 10, RD_FLD(instr, INSTR_RD)); + } else if (RD_FLD(instr, INSTR_OP2) == OP2_BICC) { + printf("%s disp:%08X",icond_names[RD_FLD(instr, INSTR_COND_H)], + SIGN_EXTEND(RD_FLD(instr,INSTR_DISP22),22)); + } else if (RD_FLD(instr, INSTR_OP2)==OP2_BPR) { + //A, RCOND_H, D16HI, P, RS1, D16LO + printf("P%s%s%s r%d, %06X " , rcond_names[RD_FLD(instr, INSTR_RCOND_H)], + RD_FLD(instr, INSTR_A) ? ",a" : "", + RD_FLD(instr, INSTR_P) ? ",pt" : ",pn", + RD_FLD(instr, INSTR_RS1), + RD_D16(instr) + ); + } else if (RD_FLD(instr, INSTR_OP2)==OP2_FB) { + // cond, A, disp22 + printf("%s%s %08X", fcond_names[RD_FLD(instr, INSTR_COND_H)], + RD_FLD(instr, INSTR_A) ? ",a" : "", + RD_FLD(instr, INSTR_DISP22)); + } else if (RD_FLD(instr, INSTR_OP2)==OP2_FBP) { + // + } else{ + printf("Unknown:OP=0b00 OP2 = 0x%04X", RD_FLD(instr, INSTR_OP2)); + } } void sparc_printalu(char * basename , unsigned instr) { - // OP=OP_2 : RD, OP3, RS1: {I=0 -> RS2 I=1->SIMM13} - if (RD_FLD(instr, INSTR_I)==0) - printf("%s r%d <- r%d ,r%d",basename, RD_FLD(instr, INSTR_RD),RD_FLD(instr, INSTR_RS1), RD_FLD(instr, INSTR_RS2)); - else - printf("%s r%d <- r%d ,%d",basename, RD_FLD(instr, INSTR_RD),RD_FLD(instr, INSTR_RS1), SIGN_EXTEND13(RD_FLD(instr, INSTR_SIMM13))); + // OP=OP_2 : RD, OP3, RS1: {I=0 -> RS2 I=1->SIMM13} + if (RD_FLD(instr, INSTR_I)==0) { + printf("%s r%d <- r%d ,r%d",basename, RD_FLD(instr, INSTR_RD), + RD_FLD(instr, INSTR_RS1), RD_FLD(instr, INSTR_RS2)); + } else { + printf("%s r%d <- r%d ,%d",basename, RD_FLD(instr, INSTR_RD), + RD_FLD(instr, INSTR_RS1), + SIGN_EXTEND13(RD_FLD(instr, INSTR_SIMM13))); + } } void sparc_printshf(char * basename, unsigned instr) { - //OP=OP_2: RD, OP_3 RS1: {I=0 -> X & RS2 ,I=1 -> {X=0 -> SHCNT32 X=1->SHCNT64 }} - if (RD_FLD(instr, INSTR_I)==0) - printf("%s%d r%d <- r%d, by r%d ",(RD_FLD(instr, INSTR_X)==0 ? 32 : 64), basename, RD_FLD(instr, INSTR_RD), RD_FLD(instr, INSTR_RS1), RD_FLD(instr, INSTR_RS2)); - else - printf("%s%d r%d <- r%d, by 0x%04X ", basename,(RD_FLD(instr, INSTR_X)==0 ? 32 : 64), RD_FLD(instr, INSTR_RD), RD_FLD(instr, INSTR_RS1), (RD_FLD(instr, INSTR_X)==0 ? RD_FLD(instr, INSTR_SHCNT32) : RD_FLD(instr, INSTR_SHCNT64)) ); - + // OP=OP_2: RD, OP_3 RS1: + // {I=0 -> X & RS2 ,I=1 -> {X=0 -> SHCNT32 X=1->SHCNT64 }} + if (RD_FLD(instr, INSTR_I)==0) { + printf("%s%d r%d <- r%d, by r%d ", (RD_FLD(instr, INSTR_X)==0 ? 32 : 64), + basename, RD_FLD(instr, INSTR_RD), RD_FLD(instr, INSTR_RS1), + RD_FLD(instr, INSTR_RS2)); + } else { + printf("%s%d r%d <- r%d, by 0x%04X ", basename, + (RD_FLD(instr, INSTR_X)==0 ? 32 : 64), + RD_FLD(instr, INSTR_RD), RD_FLD(instr, INSTR_RS1), + (RD_FLD(instr, INSTR_X)==0 ? RD_FLD(instr, INSTR_SHCNT32) + : RD_FLD(instr, INSTR_SHCNT64)) ); + } } // Op2 class instructions void sparc_printfpu(unsigned instr) { - switch(RD_FLD(instr, INSTR_OPF) &~ OPF_MASK_ON) - { - case OPF_FADDn: - printf("FADDn"); - return; - case OPF_FSUBn: - printf("FSUBn"); - return; - case OPF_FMOVn: - printf("FMOVn"); - return; - case OPF_FNEGn: - printf("FNEGn"); - return; - case OPF_FABSn: - printf("FABSn"); - return; - case OPF_FMULn: - printf("FMULn"); - return; - case OPF_FDIVn: - printf("FDIVn"); - return; - case OPF_FSQRTn: - printf("FSQRTn"); - return; - } - switch (RD_FLD(instr, INSTR_OPF) &~OPF_MASK_TO) - { - case OPF_FxTOt: - printf("FxTOt"); - return; - case OPF_FiTOt: - printf("FiTOt"); - return; - } - - switch(RD_FLD(instr, INSTR_OPF)) - { - case OPF_FsTOx: - printf("OPF_FsTOx"); - return; - case OPF_FsTOi: - printf("OPF_FsTOi"); - return; - case OPF_FsTOd: - printf("OPF_FsTOd"); - return; - case OPF_FsTOq: - printf("OPF_FsTOq"); - return; - case OPF_FdTOx: - printf("OPF_FdTOx"); - return; - case OPF_FdTOi: - printf("OPF_FdTOi"); - return; - case OPF_FqTOx: - printf("OPF_FqTOx"); - return; - case OPF_FdTOs: - printf("OPF_FdTOs"); - return; - case OPF_FdTOq: - printf("OPF_FdTOq"); - return; - case OPF_FqTOi: - printf("OPF_FqTOi"); - return; - case OPF_FqTOs: - printf("OPF_FqTOs"); - return; - case OPF_FqTOd: - printf("OPF_FqTOd"); - return; - case OPF_FsMULd: - printf("OPF_FsMULd"); - return; - case OPF_FdMULq: - printf("OPF_FdMULq"); - return; - } + switch(RD_FLD(instr, INSTR_OPF) &~ OPF_MASK_ON) + { + case OPF_FADDn: + printf("FADDn"); + return; + case OPF_FSUBn: + printf("FSUBn"); + return; + case OPF_FMOVn: + printf("FMOVn"); + return; + case OPF_FNEGn: + printf("FNEGn"); + return; + case OPF_FABSn: + printf("FABSn"); + return; + case OPF_FMULn: + printf("FMULn"); + return; + case OPF_FDIVn: + printf("FDIVn"); + return; + case OPF_FSQRTn: + printf("FSQRTn"); + return; + } + switch (RD_FLD(instr, INSTR_OPF) &~OPF_MASK_TO) + { + case OPF_FxTOt: + printf("FxTOt"); + return; + case OPF_FiTOt: + printf("FiTOt"); + return; + } + + switch(RD_FLD(instr, INSTR_OPF)) + { + case OPF_FsTOx: + printf("OPF_FsTOx"); + return; + case OPF_FsTOi: + printf("OPF_FsTOi"); + return; + case OPF_FsTOd: + printf("OPF_FsTOd"); + return; + case OPF_FsTOq: + printf("OPF_FsTOq"); + return; + case OPF_FdTOx: + printf("OPF_FdTOx"); + return; + case OPF_FdTOi: + printf("OPF_FdTOi"); + return; + case OPF_FqTOx: + printf("OPF_FqTOx"); + return; + case OPF_FdTOs: + printf("OPF_FdTOs"); + return; + case OPF_FdTOq: + printf("OPF_FdTOq"); + return; + case OPF_FqTOi: + printf("OPF_FqTOi"); + return; + case OPF_FqTOs: + printf("OPF_FqTOs"); + return; + case OPF_FqTOd: + printf("OPF_FqTOd"); + return; + case OPF_FsMULd: + printf("OPF_FsMULd"); + return; + case OPF_FdMULq: + printf("OPF_FdMULq"); + return; + } } void sparc_print2(unsigned instr) { - switch(RD_FLD(instr, INSTR_OP3)) - { - case OP3_ADD: - sparc_printalu("ADD", instr); - return; - - case OP3_ADDcc: - sparc_printalu("ADDcc", instr); - return; - - case OP3_ADDC: - sparc_printalu("ADDC", instr); - return; - - case OP3_ADDCcc: - sparc_printalu("ADDCcc", instr); - return; - - case OP3_AND: - sparc_printalu("AND", instr); - return; - - case OP3_ANDcc: - sparc_printalu("ANDcc", instr); - return; - - case OP3_OR: - sparc_printalu("OR", instr); - return; - - case OP3_ORcc: - sparc_printalu("ORcc", instr); - return; - - case OP3_XOR: - sparc_printalu("XOR", instr); - return; - - case OP3_XORcc: - sparc_printalu("XORcc", instr); - return; - - case OP3_SUB: - sparc_printalu("SUB", instr); - return; - - case OP3_SUBcc: - sparc_printalu("SUBcc", instr); - return; - - case OP3_ANDN: - sparc_printalu("ANDN", instr); - return; - - case OP3_ANDNcc: - sparc_printalu("ANDNcc", instr); - return; - - case OP3_ORN: - sparc_printalu("ORN", instr); - return; - - case OP3_ORNcc: - sparc_printalu("ORNcc", instr); - return; - - case OP3_XNOR: - sparc_printalu("XNOR", instr); - return; - - case OP3_XNORcc: - sparc_printalu("XNORcc", instr); - return; - - case OP3_SUBC: - sparc_printalu("SUBC", instr); - return; - - case OP3_SUBCcc: - sparc_printalu("SUBCcc", instr); - return; - - case OP3_MULX: - sparc_printalu("MULX", instr); - return; - - case OP3_SDIVX: - sparc_printalu("SDIVX", instr); - return; - - case OP3_UDIVX: - sparc_printalu("UDIVX", instr); - return; - - case OP3_SLL: - sparc_printshf("SLL",instr); - return; - case OP3_SRL: - sparc_printshf("SRL",instr); - return; - case OP3_SRA: - sparc_printshf("SRA",instr); - return; - - case OP3_DONERETRY: - { - if (RD_FLD(instr, INSTR_FCN)==FCN_DONE) - printf("DONE"); - else if (RD_FLD(instr, INSTR_FCN)==FCN_RETRY) - printf("RETRY"); - else - printf("DOH!"); - return; - } - - case OP3_FCMP: - { - unsigned fop_n =RD_FLD(instr, INSTR_OPF) &~ OPF_MASK_ON; - if (fop_n==OPF_FCMPn) - printf("FCMP"); - else if (fop_n==OPF_FCMPEn) - printf("FCMPE"); - else - printf("DOH!"); - return; - } - - case OP3_FPU: - sparc_printfpu(instr); - return; - - case OP3_FLUSH: //OP=OP_2 RS1 {I=0 -> rs2, I=1->simm13} - printf("OP3_FLUSH"); - return; - case OP3_FLUSHW: //OP=OP_2 I = 0 - printf("OP3_FLUSHW"); - return; - case OP3_JMPL: //OP=OP_2 RD, RS1 {I=0-> RS2, I=1->SIMM13} - if (RD_FLD(instr, INSTR_I)==0) - printf("JMPL link:r%d, to: r%d+r%d", RD_FLD(instr, INSTR_RD),RD_FLD(instr, INSTR_RS1),RD_FLD(instr, INSTR_RS2) ); - else - printf("JMPL link:r%d, to: r%d+%d", RD_FLD(instr, INSTR_RD),RD_FLD(instr, INSTR_RS1),SIGN_EXTEND13(RD_FLD(instr, INSTR_SIMM13)) ); - return; - - case OP3_POPC: - printf("POPC ????"); - return; - - case OP3_RETURN: - if (RD_FLD(instr, INSTR_I) == 0) - printf("RETURN r%d + r%d", RD_FLD(instr, INSTR_RS1), RD_FLD(instr, INSTR_RS2)); - else - printf("RETURN r%d + %d", RD_FLD(instr, INSTR_RS1), SIGN_EXTEND13(RD_FLD(instr, INSTR_SIMM13))); - return; - - case OP3_SAVE: - if (RD_FLD(instr, INSTR_I) == 0) - printf("save r%d , r%d, r%d", RD_FLD(instr, INSTR_RS1), RD_FLD(instr, INSTR_RS2), RD_FLD(instr, INSTR_RD)); - else - printf("save r%d , %d, r%d", RD_FLD(instr, INSTR_RS1), SIGN_EXTEND13(RD_FLD(instr, INSTR_SIMM13)), RD_FLD(instr, INSTR_RD)); - return; - - case OP3_RESTORE: - if (RD_FLD(instr, INSTR_I) == 0) - printf("RESTORE r%d , r%d, r%d", RD_FLD(instr, INSTR_RS1), RD_FLD(instr, INSTR_RS2), RD_FLD(instr, INSTR_RD)); - else - printf("RESTORE r%d , %d, r%d", RD_FLD(instr, INSTR_RS1), SIGN_EXTEND13(RD_FLD(instr, INSTR_SIMM13)), RD_FLD(instr, INSTR_RD)); - return; + switch(RD_FLD(instr, INSTR_OP3)) + { + case OP3_ADD: + sparc_printalu("ADD", instr); + return; + + case OP3_ADDcc: + sparc_printalu("ADDcc", instr); + return; + + case OP3_ADDC: + sparc_printalu("ADDC", instr); + return; + + case OP3_ADDCcc: + sparc_printalu("ADDCcc", instr); + return; + + case OP3_AND: + sparc_printalu("AND", instr); + return; + + case OP3_ANDcc: + sparc_printalu("ANDcc", instr); + return; + + case OP3_OR: + sparc_printalu("OR", instr); + return; + + case OP3_ORcc: + sparc_printalu("ORcc", instr); + return; + + case OP3_XOR: + sparc_printalu("XOR", instr); + return; + + case OP3_XORcc: + sparc_printalu("XORcc", instr); + return; + + case OP3_SUB: + sparc_printalu("SUB", instr); + return; + + case OP3_SUBcc: + sparc_printalu("SUBcc", instr); + return; + + case OP3_ANDN: + sparc_printalu("ANDN", instr); + return; + + case OP3_ANDNcc: + sparc_printalu("ANDNcc", instr); + return; + + case OP3_ORN: + sparc_printalu("ORN", instr); + return; + + case OP3_ORNcc: + sparc_printalu("ORNcc", instr); + return; + + case OP3_XNOR: + sparc_printalu("XNOR", instr); + return; + + case OP3_XNORcc: + sparc_printalu("XNORcc", instr); + return; + + case OP3_SUBC: + sparc_printalu("SUBC", instr); + return; + + case OP3_SUBCcc: + sparc_printalu("SUBCcc", instr); + return; + + case OP3_MULX: + sparc_printalu("MULX", instr); + return; + + case OP3_SDIVX: + sparc_printalu("SDIVX", instr); + return; + + case OP3_UDIVX: + sparc_printalu("UDIVX", instr); + return; + + case OP3_SLL: + sparc_printshf("SLL",instr); + return; + case OP3_SRL: + sparc_printshf("SRL",instr); + return; + case OP3_SRA: + sparc_printshf("SRA",instr); + return; + + case OP3_DONERETRY: + { + if (RD_FLD(instr, INSTR_FCN)==FCN_DONE) + printf("DONE"); + else if (RD_FLD(instr, INSTR_FCN)==FCN_RETRY) + printf("RETRY"); + else + printf("DOH!"); + return; + } + + case OP3_FCMP: + { + unsigned fop_n =RD_FLD(instr, INSTR_OPF) &~ OPF_MASK_ON; + if (fop_n==OPF_FCMPn) + printf("FCMP"); + else if (fop_n==OPF_FCMPEn) + printf("FCMPE"); + else + printf("DOH!"); + return; + } + + case OP3_FPU: + sparc_printfpu(instr); + return; + + case OP3_FLUSH: //OP=OP_2 RS1 {I=0 -> rs2, I=1->simm13} + printf("OP3_FLUSH"); + return; + case OP3_FLUSHW: //OP=OP_2 I = 0 + printf("OP3_FLUSHW"); + return; + case OP3_JMPL: //OP=OP_2 RD, RS1 {I=0-> RS2, I=1->SIMM13} + if (RD_FLD(instr, INSTR_I)==0) + printf("JMPL link:r%d, to: r%d+r%d", RD_FLD(instr, INSTR_RD), + RD_FLD(instr, INSTR_RS1),RD_FLD(instr, INSTR_RS2) ); + else + printf("JMPL link:r%d, to: r%d+%d", RD_FLD(instr, INSTR_RD), + RD_FLD(instr, INSTR_RS1), + SIGN_EXTEND13(RD_FLD(instr, INSTR_SIMM13)) ); + return; + + case OP3_POPC: + printf("POPC ????"); + return; + + case OP3_RETURN: + if (RD_FLD(instr, INSTR_I) == 0) + printf("RETURN r%d + r%d", RD_FLD(instr, INSTR_RS1), + RD_FLD(instr, INSTR_RS2)); + else + printf("RETURN r%d + %d", RD_FLD(instr, INSTR_RS1), + SIGN_EXTEND13(RD_FLD(instr, INSTR_SIMM13))); + return; + + case OP3_SAVE: + if (RD_FLD(instr, INSTR_I) == 0) + printf("save r%d , r%d, r%d", RD_FLD(instr, INSTR_RS1), + RD_FLD(instr, INSTR_RS2), RD_FLD(instr, INSTR_RD)); + else + printf("save r%d , %d, r%d", RD_FLD(instr, INSTR_RS1), + SIGN_EXTEND13(RD_FLD(instr, INSTR_SIMM13)), + RD_FLD(instr, INSTR_RD)); + return; + + case OP3_RESTORE: + if (RD_FLD(instr, INSTR_I) == 0) + printf("RESTORE r%d , r%d, r%d", RD_FLD(instr, INSTR_RS1), + RD_FLD(instr, INSTR_RS2), RD_FLD(instr, INSTR_RD)); + else + printf("RESTORE r%d , %d, r%d", RD_FLD(instr, INSTR_RS1), + SIGN_EXTEND13(RD_FLD(instr, INSTR_SIMM13)), + RD_FLD(instr, INSTR_RD)); + return; - } + } - printf("Unknown:OP=0b10 OP3 = 0x%04X", RD_FLD(instr, INSTR_OP3)); + printf("Unknown:OP=0b10 OP3 = 0x%04X", RD_FLD(instr, INSTR_OP3)); } void sparc_printldst(char * basename, unsigned instr) -{ - if (RD_FLD(instr, INSTR_I)==0) - printf("%s r%d <- r%d , r%d", basename,RD_FLD(instr, INSTR_RD), RD_FLD(instr, INSTR_RS1), RD_FLD(instr, INSTR_RS2)); - else - printf("%s r%d <- r%d , %d",basename, RD_FLD(instr, INSTR_RD), RD_FLD(instr, INSTR_RS1), SIGN_EXTEND13(RD_FLD(instr, INSTR_SIMM13))); +{ + if (RD_FLD(instr, INSTR_I)==0) + printf("%s r%d <- r%d , r%d", basename, RD_FLD(instr, INSTR_RD), + RD_FLD(instr, INSTR_RS1), RD_FLD(instr, INSTR_RS2)); + else + printf("%s r%d <- r%d , %d",basename, RD_FLD(instr, INSTR_RD), + RD_FLD(instr, INSTR_RS1), + SIGN_EXTEND13(RD_FLD(instr, INSTR_SIMM13))); } void sparc_print3(unsigned instr) { -//#define OP3_LDFA 0b110000 //OP=OP_3 RD, Rs1, {I=0->IMM_ASI, RS2 I=1->SIMM13} -//#define OP3_LDDFA 0b110011 //OP=OP_3 RD, Rs1, {I=0->IMM_ASI, RS2 I=1->SIMM13} -//#define OP3_LDQFA 0b110010 //OP=OP_3 RD, Rs1, {I=0->IMM_ASI, RS2 I=1->SIMM13} -//#define OP3_LDSTUB 0b001101 //OP=OP_3 RD, Rs1 {I=0->RS2, I=1->SIMM13} -//#define OP3_LDSTUBA 0b011101 //OP=OP_3 RD, RS1 {I=0->RS2, IMM_ASI, I=1->SIMM13} - switch(RD_FLD(instr, INSTR_OP3)) - { - //OP=OP_3 RD, Rs1 {I=0->RS2, I=1->SIMM13} - case OP3_LDSTUB: - sparc_printldst("LDSTUB", instr); - return; - - case OP3_STB: - sparc_printldst("STB", instr); - return; - - case OP3_STH: - sparc_printldst("STH", instr); - return; - - case OP3_STW: - sparc_printldst("STW", instr); - return; - - case OP3_STX: - sparc_printldst("STX", instr); - return; - - case OP3_LDSB: - sparc_printldst("LDSB", instr); - return; - - case OP3_LDSH: - sparc_printldst("LDSH", instr); - return; - - case OP3_LDSW: - sparc_printldst("LDSW", instr); - return; - - case OP3_LDUB: - sparc_printldst("LDUB", instr); - return; - - case OP3_LDUH: - sparc_printldst("LDUH", instr); - return; - - case OP3_LDUW: - sparc_printldst("LDUW", instr); - return; - - case OP3_LDX: - sparc_printldst("LDX", instr); - return; - - case OP3_CASA: - if (RD_FLD(instr, INSTR_I)==0) - printf("CASA [r%d] %%%d, r%d, r%d", RD_FLD(instr, INSTR_RS1),RD_FLD(instr, INSTR_IMMASI), RD_FLD(instr, INSTR_RS2), RD_FLD(instr, INSTR_RD)); - else - printf("CASA [r%d] , r%d, r%d", RD_FLD(instr, INSTR_RS1), RD_FLD(instr, INSTR_RS2), RD_FLD(instr, INSTR_RD)); - - sparc_printalu("CASA", instr); - - return; - - case OP3_CASXA: - sparc_printalu("CASXA", instr); - return; - case OP3_STFA: - sparc_printalu("STFA",instr); - return; - case OP3_STDFA: - sparc_printalu("STDFA",instr); - return; - case OP3_STQFA: - sparc_printalu("STQFA",instr); - return; - - case OP3_PREFETCH: - printf("PREFETCH ??? "); - return; - - case OP3_PREFETCHA: - printf("PREFETCHA ??? "); - return; - } + //#define OP3_LDFA 0b110000 + //OP=OP_3 RD, Rs1, {I=0->IMM_ASI, RS2 I=1->SIMM13} + + //#define OP3_LDDFA 0b110011 + //OP=OP_3 RD, Rs1, {I=0->IMM_ASI, RS2 I=1->SIMM13} + + //#define OP3_LDQFA 0b110010 + //OP=OP_3 RD, Rs1, {I=0->IMM_ASI, RS2 I=1->SIMM13} + + //#define OP3_LDSTUB 0b001101 + //OP=OP_3 RD, Rs1 {I=0->RS2, I=1->SIMM13} + + //#define OP3_LDSTUBA 0b011101 + //OP=OP_3 RD, RS1 {I=0->RS2, IMM_ASI, I=1->SIMM13} + + switch(RD_FLD(instr, INSTR_OP3)) + { + //OP=OP_3 RD, Rs1 {I=0->RS2, I=1->SIMM13} + case OP3_LDSTUB: + sparc_printldst("LDSTUB", instr); + return; + + case OP3_STB: + sparc_printldst("STB", instr); + return; + + case OP3_STH: + sparc_printldst("STH", instr); + return; + + case OP3_STW: + sparc_printldst("STW", instr); + return; + + case OP3_STX: + sparc_printldst("STX", instr); + return; + + case OP3_LDSB: + sparc_printldst("LDSB", instr); + return; + + case OP3_LDSH: + sparc_printldst("LDSH", instr); + return; + + case OP3_LDSW: + sparc_printldst("LDSW", instr); + return; + + case OP3_LDUB: + sparc_printldst("LDUB", instr); + return; + + case OP3_LDUH: + sparc_printldst("LDUH", instr); + return; + + case OP3_LDUW: + sparc_printldst("LDUW", instr); + return; + + case OP3_LDX: + sparc_printldst("LDX", instr); + return; + + case OP3_CASA: + if (RD_FLD(instr, INSTR_I)==0) + printf("CASA [r%d] %%%d, r%d, r%d", RD_FLD(instr, INSTR_RS1), + RD_FLD(instr, INSTR_IMMASI), RD_FLD(instr, INSTR_RS2), + RD_FLD(instr, INSTR_RD)); + else + printf("CASA [r%d] , r%d, r%d", RD_FLD(instr, INSTR_RS1), + RD_FLD(instr, INSTR_RS2), RD_FLD(instr, INSTR_RD)); + + sparc_printalu("CASA", instr); + + return; + + case OP3_CASXA: + sparc_printalu("CASXA", instr); + return; + case OP3_STFA: + sparc_printalu("STFA",instr); + return; + case OP3_STDFA: + sparc_printalu("STDFA",instr); + return; + case OP3_STQFA: + sparc_printalu("STQFA",instr); + return; + + case OP3_PREFETCH: + printf("PREFETCH ??? "); + return; + + case OP3_PREFETCHA: + printf("PREFETCHA ??? "); + return; + } - printf("Unknown OP_3: OP3 = %08X", RD_FLD(instr, INSTR_OP3)); + printf("Unknown OP_3: OP3 = %08X", RD_FLD(instr, INSTR_OP3)); } void sparc_print(unsigned instr) { - printf("(%08X) ", instr); - if (RD_FLD(instr,INSTR_OP)==OP_CALL) - printf("CALL disp:+%08X", instr & 0x3FFFFFFF); - else if (RD_FLD(instr,INSTR_OP)==OP_BRANCH) - sparc_printbr(instr); - else if (RD_FLD(instr,INSTR_OP)==OP_2) - sparc_print2(instr); - else if (RD_FLD(instr,INSTR_OP)==OP_3) - sparc_print3(instr); + printf("(%08X) ", instr); + if (RD_FLD(instr,INSTR_OP)==OP_CALL) + printf("CALL disp:+%08X", instr & 0x3FFFFFFF); + else if (RD_FLD(instr,INSTR_OP)==OP_BRANCH) + sparc_printbr(instr); + else if (RD_FLD(instr,INSTR_OP)==OP_2) + sparc_print2(instr); + else if (RD_FLD(instr,INSTR_OP)==OP_3) + sparc_print3(instr); } - Index: llvm/lib/Reoptimizer/BinInterface/binproc.cpp diff -u llvm/lib/Reoptimizer/BinInterface/binproc.cpp:1.2 llvm/lib/Reoptimizer/BinInterface/binproc.cpp:1.3 --- llvm/lib/Reoptimizer/BinInterface/binproc.cpp:1.2 Fri Nov 8 04:38:13 2002 +++ llvm/lib/Reoptimizer/BinInterface/binproc.cpp Tue Nov 12 20:47:14 2002 @@ -1,113 +1,117 @@ +//===-----------------------------------------------------------*- C++ -*--===// +// +//===----------------------------------------------------------------------===// + #include #include -char * LoadFile(const char * fname) +char* LoadFile(const char * fname) { - unsigned size; - char * buffer; - FILE * file = fopen(fname, "rb"); - if (!file) - return NULL; - - fseek(file, 0, SEEK_END); - size = ftell(file); - fseek(file, 0, SEEK_SET); - - - buffer = new char[size + 1]; - fread(buffer, 1, size, file); - buffer[size] = 0; + unsigned size; + char * buffer; + FILE * file = fopen(fname, "rb"); + if (!file) + return NULL; + + fseek(file, 0, SEEK_END); + size = ftell(file); + fseek(file, 0, SEEK_SET); + + + buffer = new char[size + 1]; + fread(buffer, 1, size, file); + buffer[size] = 0; - fclose(file); - return buffer; + fclose(file); + return buffer; } #define IS_TOK(x) ((x >= '0' && x <= '9') || \ - (x >= 'A' && x <= 'Z') || \ - (x >= 'a' && x <= 'z') || \ - (x == '_')) + (x >= 'A' && x <= 'Z') || \ + (x >= 'a' && x <= 'z') || \ + (x == '_')) void process_token (char * begin, char * end, FILE * file) { - unsigned u = 0; - char * i = begin; + unsigned u = 0; + char * i = begin; - if (i==end || *i++ != '0') - goto not_binary; + if (i==end || *i++ != '0') + goto not_binary; - if (i== end || *i++ != 'b') - goto not_binary; + if (i== end || *i++ != 'b') + goto not_binary; - while (i!=end && (*i == '0' || *i == '1')) - { - u = (u << 1) | (*i - '0'); - i++; - } - - fprintf(file, "0x%08X", u); - return; - -not_binary: - //just output the thing, it wasn't it - while (begin!=end) - fputc(*begin++, file); + while (i!=end && (*i == '0' || *i == '1')) + { + u = (u << 1) | (*i - '0'); + i++; + } + + fprintf(file, "0x%08X", u); + return; + + not_binary: + //just output the thing, it wasn't it + while (begin!=end) + fputc(*begin++, file); } void process(char * buffer, FILE * file) { - while (*buffer) - { - if (IS_TOK(*buffer)) - { - char * begin = buffer; - char * end = buffer; - - while (IS_TOK(*end)) - end++; - - process_token(begin, end, file); - buffer = end; - } - else - fputc(*buffer++, file); - } + while (*buffer) + { + if (IS_TOK(*buffer)) + { + char * begin = buffer; + char * end = buffer; + + while (IS_TOK(*end)) + end++; + + process_token(begin, end, file); + buffer = end; + } + else + fputc(*buffer++, file); + } } int main(int argc, char ** argv) { - FILE * file = NULL; - char * buffer = NULL; - if (argc!=3) - { - printf("Usage: \n" - " binproc [infile] [outfile]\n"); - goto failure; - } - buffer = LoadFile(argv[1]); - - if (!buffer) - { - printf("Failed to open input file\n"); - goto failure; - } - - file = fopen(argv[2],"wb"); - if (!file) - { - printf("Failed to open output file\n"); - goto failure; - } - fprintf(file, "#line 1 \"%s\"\n", argv[1]); - process(buffer, file); - - delete buffer; - fclose(file); - - return 0; - -failure: - if (file) - fclose(file); - if (buffer) - delete buffer; - return 1; + FILE * file = NULL; + char * buffer = NULL; + if (argc!=3) + { + printf("Usage: \n" + " binproc [infile] [outfile]\n"); + goto failure; + } + buffer = LoadFile(argv[1]); + + if (!buffer) + { + printf("Failed to open input file\n"); + goto failure; + } + + file = fopen(argv[2],"wb"); + if (!file) + { + printf("Failed to open output file\n"); + goto failure; + } + fprintf(file, "#line 1 \"%s\"\n", argv[1]); + process(buffer, file); + + delete buffer; + fclose(file); + + return 0; + + failure: + if (file) + fclose(file); + if (buffer) + delete buffer; + return 1; } From lattner at cs.uiuc.edu Wed Nov 13 00:55:02 2002 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Wed Nov 13 00:55:02 2002 Subject: [llvm-commits] CVS: llvm/test/Regression/Transforms/LevelRaise/2002-11-13-PointerFunction.ll Message-ID: <200211130654.AAA27814@apoc.cs.uiuc.edu> Changes in directory llvm/test/Regression/Transforms/LevelRaise: 2002-11-13-PointerFunction.ll added (r1.1) --- Log message: New testcase --- Diffs of the changes: From lattner at cs.uiuc.edu Wed Nov 13 00:55:06 2002 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Wed Nov 13 00:55:06 2002 Subject: [llvm-commits] CVS: llvm/lib/Transforms/ExprTypeConvert.cpp Message-ID: <200211130654.AAA27823@apoc.cs.uiuc.edu> Changes in directory llvm/lib/Transforms: ExprTypeConvert.cpp updated: 1.65 -> 1.66 --- Log message: Fix bug: 2002-11-13-PointerFunction.ll This should fix codegen on vortex to work much better --- Diffs of the changes: Index: llvm/lib/Transforms/ExprTypeConvert.cpp diff -u llvm/lib/Transforms/ExprTypeConvert.cpp:1.65 llvm/lib/Transforms/ExprTypeConvert.cpp:1.66 --- llvm/lib/Transforms/ExprTypeConvert.cpp:1.65 Sun Nov 3 23:50:42 2002 +++ llvm/lib/Transforms/ExprTypeConvert.cpp Wed Nov 13 00:54:20 2002 @@ -285,6 +285,24 @@ return false; // No match, maybe next time. } + case Instruction::Call: { + if (isa(I->getOperand(0))) + return false; // Don't even try to change direct calls. + + // If this is a function pointer, we can convert the return type if we can + // convert the source function pointer. + // + const PointerType *PT = cast(I->getOperand(0)->getType()); + const FunctionType *FT = cast(PT->getElementType()); + std::vector ArgTys(FT->getParamTypes().begin(), + FT->getParamTypes().end()); + const FunctionType *NewTy = + FunctionType::get(Ty, ArgTys, FT->isVarArg()); + if (!ExpressionConvertableToType(I->getOperand(0), + PointerType::get(NewTy), CTMap)) + return false; + break; + } default: return false; } @@ -477,9 +495,30 @@ assert(Res && "Didn't find match!"); - break; // No match, maybe next time. + break; } + case Instruction::Call: { + assert(!isa(I->getOperand(0))); + + // If this is a function pointer, we can convert the return type if we can + // convert the source function pointer. + // + const PointerType *PT = cast(I->getOperand(0)->getType()); + const FunctionType *FT = cast(PT->getElementType()); + std::vector ArgTys(FT->getParamTypes().begin(), + FT->getParamTypes().end()); + const FunctionType *NewTy = + FunctionType::get(Ty, ArgTys, FT->isVarArg()); + const PointerType *NewPTy = PointerType::get(NewTy); + + Res = new CallInst(Constant::getNullValue(NewPTy), + std::vector(I->op_begin()+1, I->op_end()), + Name); + VMC.ExprMap[I] = Res; + Res->setOperand(0, ConvertExpressionToType(I->getOperand(0), NewPTy, VMC)); + break; + } default: assert(0 && "Expression convertable, but don't know how to convert?"); return 0; From vadve at cs.uiuc.edu Wed Nov 13 09:42:01 2002 From: vadve at cs.uiuc.edu (Vikram Adve) Date: Wed Nov 13 09:42:01 2002 Subject: [llvm-commits] CVS: llvm/lib/Analysis/DataStructure/DataStructureStats.cpp Message-ID: <200211131541.JAA06741@psmith.cs.uiuc.edu> Changes in directory llvm/lib/Analysis/DataStructure: DataStructureStats.cpp added (r1.1) --- Log message: Pass to compute various statisics related to DSGraphs. For now, this just computes the #indirect call sites and the avg. #callees per indirect call site (actually it prints both totals and the average is their ratio). --- Diffs of the changes: From dhurjati at cs.uiuc.edu Wed Nov 13 12:23:01 2002 From: dhurjati at cs.uiuc.edu (Dinakar Dhurjati) Date: Wed Nov 13 12:23:01 2002 Subject: [llvm-commits] CVS: llvm/lib/Analysis/InstCount.cpp Message-ID: <200211131822.MAA14881@choi.cs.uiuc.edu> Changes in directory llvm/lib/Analysis: InstCount.cpp added (r1.1) --- Log message: Gives the count for various instructions. --- Diffs of the changes: From brukman at neo.cs.uiuc.edu Wed Nov 13 14:16:01 2002 From: brukman at neo.cs.uiuc.edu (Misha Brukman) Date: Wed Nov 13 14:16:01 2002 Subject: [llvm-commits] CVS: llvm/lib/Reoptimizer/BinInterface/BinInterface.cpp BinInterface.h bitmath.h test1.cpp sparcdis.cpp sparcdis.h Message-ID: <200211132018.gADKI3G05252@neo.cs.uiuc.edu> Changes in directory llvm/lib/Reoptimizer/BinInterface: BinInterface.cpp updated: 1.1 -> 1.2 BinInterface.h updated: 1.1 -> 1.2 bitmath.h updated: 1.1 -> 1.2 test1.cpp updated: 1.1 -> 1.2 sparcdis.cpp updated: 1.2 -> 1.3 sparcdis.h updated: 1.1 -> 1.2 --- Log message: * Fixed comment headers * Re-aligned, wrapped code * Changed Windows end-of-line to Unix style * Stopped including sparc9.hp in favor of sparc9.h --- Diffs of the changes: Index: llvm/lib/Reoptimizer/BinInterface/BinInterface.cpp diff -u llvm/lib/Reoptimizer/BinInterface/BinInterface.cpp:1.1 llvm/lib/Reoptimizer/BinInterface/BinInterface.cpp:1.2 --- llvm/lib/Reoptimizer/BinInterface/BinInterface.cpp:1.1 Fri Nov 8 04:38:13 2002 +++ llvm/lib/Reoptimizer/BinInterface/BinInterface.cpp Wed Nov 13 14:17:52 2002 @@ -8,14 +8,14 @@ #include #include +#include #include "salloc.h" #include "fvector.h" #include "analyze.h" #include "BinInterface.h" #include "machine.h" #include "sparcdis.h" -#include "sparc9.hp" -#include +#include "sparc9.h" // 512kb initial size #define BIN_INIT_HEAP_SIZE 0x80000 @@ -23,141 +23,141 @@ void BinInterface::process_branch(const insertion & i, unsigned ** brdest, int scns) { - unsigned cid = i.idstart; - unsigned *ibegin = i.begin; - unsigned *iend = i.end; - unsigned tail = sections[i.section]; + unsigned cid = i.idstart; + unsigned *ibegin = i.begin; + unsigned *iend = i.end; + unsigned tail = sections[i.section]; - while(ibegin!=iend) - { - // look at the instruction - unsigned flags = sparc_analyze(*ibegin); - unsigned * instr; + while(ibegin!=iend) + { + // look at the instruction + unsigned flags = sparc_analyze(*ibegin); + unsigned * instr; - if (flags & IF_BR) - { + if (flags & IF_BR) + { - int fwd = SIGN_EXTEND(RD_FLD(*ibegin,INSTR_DISP22),22); - unsigned * dest = ibegin + fwd; + int fwd = SIGN_EXTEND(RD_FLD(*ibegin,INSTR_DISP22),22); + unsigned * dest = ibegin + fwd; - // create a branch instruction - instr = (unsigned *)alloca.alloc(SIZE_BRANCH * sizeof(unsigned)); - instr[I_FLAGS] = flags; - - instr[I_BRDEST] = 0; - // scan for branch destination - for (int l = 0; lphi.src_prolog, instr->phi.src_trace); - printf("PHI NODE\n"); - u = next(u); - continue; - } + if (instr[I_FLAGS] & IF_PHI) + { + //printf(" PHI{prolog=%02d, trace=%02d}\n", instr->phi.src_prolog, instr->phi.src_trace); + printf("PHI NODE\n"); + u = next(u); + continue; + } - if (instr[I_FLAGS] & IF_BR) - { - //if (instr[I_FLAGS] & INTERNAL_BR) - printf("{%02d} ", instr[I_BRDEST]); - //else - // printf(" "); - printf(" "); - } - else - { - if (instr[I_FLAGS] & IF_RS1) - printf("A=%02d ", instr[I_GENRS1]); - else - printf(" "); + if (instr[I_FLAGS] & IF_BR) + { + //if (instr[I_FLAGS] & INTERNAL_BR) + printf("{%02d} ", instr[I_BRDEST]); + //else + // printf(" "); + printf(" "); + } + else + { + if (instr[I_FLAGS] & IF_RS1) + printf("A=%02d ", instr[I_GENRS1]); + else + printf(" "); - if (instr[I_FLAGS] & IF_RS2) - printf("B=%02d ", instr[I_GENRS2]); - else - printf(" "); - } - sparc_print(instr[I_INSTR]); + if (instr[I_FLAGS] & IF_RS2) + printf("B=%02d ", instr[I_GENRS2]); + else + printf(" "); + } + sparc_print(instr[I_INSTR]); - printf("\n"); + printf("\n"); - u = next(u); - } + u = next(u); + } } void BinInterface::print() { - for (int p = 0; p< sections.size(); p++) - { - printf("Section %d\n",p); - print(p); - } + for (int p = 0; p< sections.size(); p++) + { + printf("Section %d\n",p); + print(p); + } } @@ -165,23 +165,23 @@ unsigned BinInterface::newepilog() { - unsigned v = sections.size(); - push_section(); - return v; + unsigned v = sections.size(); + push_section(); + return v; } void BinInterface::insert_instr(unsigned instr_id, unsigned * instr) { - unsigned a = instr_id; - unsigned c = itable[a][I_NEXT]; + unsigned a = instr_id; + unsigned c = itable[a][I_NEXT]; - itable[a][I_NEXT] = instr[I_SELF]; - instr[I_PREV] = a; + itable[a][I_NEXT] = instr[I_SELF]; + instr[I_PREV] = a; - instr[I_NEXT] = c; - itable[c][I_PREV] = instr[I_SELF]; + instr[I_NEXT] = c; + itable[c][I_PREV] = instr[I_SELF]; } // @@ -191,48 +191,48 @@ // AFTER INSTR AFTER->NEXT void BinInterface::push_section() { - // create header node - unsigned * instr = (unsigned *)alloca.alloc(SIZE_HEADER * sizeof(unsigned)); - instr[I_NEXT] = itable.size(); - instr[I_PREV] = itable.size(); - instr[I_FLAGS] = 0; - instr[I_SELF] = itable.size(); + // create header node + unsigned * instr = (unsigned *)alloca.alloc(SIZE_HEADER * sizeof(unsigned)); + instr[I_NEXT] = itable.size(); + instr[I_PREV] = itable.size(); + instr[I_FLAGS] = 0; + instr[I_SELF] = itable.size(); - sections.push_back(itable.size()); - itable.push_back(instr); + sections.push_back(itable.size()); + itable.push_back(instr); } unsigned BinInterface::insert(unsigned section, unsigned *ibegin, unsigned * iend) { - insertion i; - i.begin = ibegin; - i.end = iend; - i.section = section; - i.idstart = itable.size(); + insertion i; + i.begin = ibegin; + i.end = iend; + i.section = section; + i.idstart = itable.size(); - itable.inc(iend - ibegin); - queue.push_back(i); + itable.inc(iend - ibegin); + queue.push_back(i); - return i.idstart; + return i.idstart; } BinInterface::BinInterface(unsigned instr_count) - : alloca(BIN_INIT_HEAP_SIZE + instr_count * 16) , itable(&alloca), sections(&alloca), - queue(&alloca) + : alloca(BIN_INIT_HEAP_SIZE + instr_count * 16) , itable(&alloca), sections(&alloca), + queue(&alloca) { - // create prolog and trace link nodes - push_section(); - push_section(); + // create prolog and trace link nodes + push_section(); + push_section(); } void BinInterface::clear() { - itable.clear(); - sections.clear(); - queue.clear(); - alloca.clear(); - // create prolog and trace link nodes - push_section(); - push_section(); + itable.clear(); + sections.clear(); + queue.clear(); + alloca.clear(); + // create prolog and trace link nodes + push_section(); + push_section(); } Index: llvm/lib/Reoptimizer/BinInterface/BinInterface.h diff -u llvm/lib/Reoptimizer/BinInterface/BinInterface.h:1.1 llvm/lib/Reoptimizer/BinInterface/BinInterface.h:1.2 --- llvm/lib/Reoptimizer/BinInterface/BinInterface.h:1.1 Fri Nov 8 04:38:13 2002 +++ llvm/lib/Reoptimizer/BinInterface/BinInterface.h Wed Nov 13 14:17:52 2002 @@ -55,77 +55,77 @@ class BinInterface { -private: + private: - StackAllocator alloca; // primary stack allocator - fvector itable; // maps an unsigned ID - // to an instruction + StackAllocator alloca; // primary stack allocator + fvector itable; // maps an unsigned ID + // to an instruction - fvector sections; + fvector sections; - // make SURE instr has already has its SELF index - // assigned! - void insert_instr(unsigned instr_id, unsigned * instr); - void push_section(); + // make SURE instr has already has its SELF index + // assigned! + void insert_instr(unsigned instr_id, unsigned * instr); + void push_section(); - // insertions are delayed to facilitate branch analysis + // insertions are delayed to facilitate branch analysis - struct insertion - { - unsigned * begin; - unsigned * end; - unsigned section; - unsigned idstart; - }; + struct insertion + { + unsigned * begin; + unsigned * end; + unsigned section; + unsigned idstart; + }; - void process_branch(const insertion & i, unsigned ** brdest, int scns); + void process_branch(const insertion & i, unsigned ** brdest, int scns); - fvector queue; + fvector queue; -public: + public: - const static unsigned SECTION_PROLOG =0; - const static unsigned SECTION_TRACE =1; + const static unsigned SECTION_PROLOG =0; + const static unsigned SECTION_TRACE =1; - // create a new section and get back ID - unsigned newepilog(); + // create a new section and get back ID + unsigned newepilog(); - // switch to section (for insertion) - unsigned insert(unsigned section, unsigned *ibegin, unsigned * iend); - - unsigned begin(unsigned sectionid) { return (itable[sections[sectionid]])[I_NEXT]; } - unsigned end (unsigned sectionid) { return sections[sectionid]; } - - // iterator over instructions - unsigned next(unsigned t) { return (itable[t])[I_NEXT]; } - unsigned prev(unsigned t) { return (itable[t])[I_PREV]; } - - void remove(unsigned); - void move(unsigned first, unsigned last, unsigned after_this); - void swap(unsigned a, unsigned b); - unsigned getopcode(unsigned); - unsigned getrs1(unsigned); - unsigned getrs2(unsigned); - unsigned getcc0(unsigned); + // switch to section (for insertion) + unsigned insert(unsigned section, unsigned *ibegin, unsigned * iend); + + unsigned begin(unsigned sectionid) { return (itable[sections[sectionid]])[I_NEXT]; } + unsigned end (unsigned sectionid) { return sections[sectionid]; } + + // iterator over instructions + unsigned next(unsigned t) { return (itable[t])[I_NEXT]; } + unsigned prev(unsigned t) { return (itable[t])[I_PREV]; } + + void remove(unsigned); + void move(unsigned first, unsigned last, unsigned after_this); + void swap(unsigned a, unsigned b); + unsigned getopcode(unsigned); + unsigned getrs1(unsigned); + unsigned getrs2(unsigned); + unsigned getcc0(unsigned); - // use 'move' to place these instructions into the stream - unsigned newbranch(unsigned op, unsigned dest); - unsigned newalu (unsigned op, unsigned rs1, unsigned rs2); - unsigned newalucc (unsigned op, unsigned rs1, unsigned rs2, unsigned cc0); - - void reduce(); - void select(); - unsigned predict(); - void emit(unsigned char * out); - void print(); - void print(unsigned scn); + // use 'move' to place these instructions into the stream + unsigned newbranch(unsigned op, unsigned dest); + unsigned newalu (unsigned op, unsigned rs1, unsigned rs2); + unsigned newalucc (unsigned op, unsigned rs1, unsigned rs2, unsigned cc0); + + void reduce(); + void select(); + unsigned predict(); + void emit(unsigned char * out); + void print(); + void print(unsigned scn); - void clear(); + void clear(); - BinInterface(unsigned instr_count); + BinInterface(unsigned instr_count); }; -#endif \ No newline at end of file +#endif Index: llvm/lib/Reoptimizer/BinInterface/bitmath.h diff -u llvm/lib/Reoptimizer/BinInterface/bitmath.h:1.1 llvm/lib/Reoptimizer/BinInterface/bitmath.h:1.2 --- llvm/lib/Reoptimizer/BinInterface/bitmath.h:1.1 Fri Nov 8 04:38:13 2002 +++ llvm/lib/Reoptimizer/BinInterface/bitmath.h Wed Nov 13 14:17:52 2002 @@ -1,97 +1,94 @@ -//***************************************************************************** -// -// High Performance Bit Utility Functions +//===-----------------------------------------------------------*- C++ -*--===// +// High Performance Bit Utility Functions // // // 2002 Cameron Buschardt -//***************************************************************************** +//===----------------------------------------------------------------------===// + +#ifndef __BITMATH_H__ +#define __BITMATH_H__ + +#define IS_POWER_2(x) !(x & (x-1)) +#define LOWEST_BIT(x) x & ~(x & (x-1)) +#define UPPER_BITS(x) (x & (x-1)) + +// Good if expected number of bits set < 4 +inline static int countbits_sparse(unsigned m) //VALIDATED +{ + int c = 0; + while (m) + { + c++; + m = UPPER_BITS(m); + } + return c; +} + +// base 2 sum of digits +inline static int countbits_dense(unsigned w) //VALIDATED +{ + w = (0x55555555 & w) + (0x55555555 & (w >> 1)); + w = (0x33333333 & w) + (0x33333333 & (w >> 2)); + w = (w + (w>>4)) & 0x0f0f0f0f; + w = w + (w>>16); + w = w + (w>>8); + return w&0xFF; +} + +inline static bool ismod3(unsigned w) //VALIDATED +{ + w = (w >> 16) + (w&0xFFFF); + w = (w >> 8) + (w&0xFF); + w = (w >> 4) + (w&0xF); + w = (w >> 2) + (w&0x3); + return (0xB6DB6DB6 >> w) & 1; +} + + +inline static int mod3(unsigned w) //VALIDATED +{ + w = (w >> 16) + (w&0xFFFF); + w = (w >> 8) + (w&0xFF); + w = (w >> 4) + (w&0xF); + w = (w >> 2) + (w&0x3); + //use lookuptable + return (0x24924924 >> (w<<1)) & 3; +} + + +inline static int parity(unsigned w) //VALIDATED +{ + w = w >> 16; + w = w >> 8; + w = w >> 4; + w = w >> 2; + w = w >> 1; + return w & 1; +} + + +inline static int log2(unsigned w) //VALIDATED +{ + int n = 0; + + if (w >> 16) + { + w >>= 16; + n+=16; + } + if (w >> 8) + { + w >>= 8; + n+=8; + } + if (w >> 4) + { + w >>= 4; + n+=4; + } + + w <<= 1; + return ((0xFFFFAA50 >> w) & 3)+n; +} -#ifndef __BITMATH_H__ -#define __BITMATH_H__ - -#define IS_POWER_2(x) !(x & (x-1)) -#define LOWEST_BIT(x) x & ~(x & (x-1)) -#define UPPER_BITS(x) (x & (x-1)) - -// Good if expected number of bits set < 4 -static int __forceinline countbits_sparse(unsigned m) //VALIDATED -{ - int c = 0; - while (m) - { - c++; - m = UPPER_BITS(m); - } - return c; -} - -// base 2 sum of digits -static int __forceinline countbits_dense(unsigned w) //VALIDATED -{ - w = (0x55555555 & w) + (0x55555555 & (w >> 1)); - w = (0x33333333 & w) + (0x33333333 & (w >> 2)); - w = (w + (w>>4)) & 0x0f0f0f0f; - w = w + (w>>16); - w = w + (w>>8); - return w&0xFF; -} - -static bool __forceinline ismod3(unsigned w) //VALIDATED -{ - w = (w >> 16) + (w&0xFFFF); - w = (w >> 8) + (w&0xFF); - w = (w >> 4) + (w&0xF); - w = (w >> 2) + (w&0x3); - return (0xB6DB6DB6 >> w) & 1; -} - - -static int __forceinline mod3(unsigned w) //VALIDATED -{ - w = (w >> 16) + (w&0xFFFF); - w = (w >> 8) + (w&0xFF); - w = (w >> 4) + (w&0xF); - w = (w >> 2) + (w&0x3); - //use lookuptable - return (0x24924924 >> (w<<1)) & 3; -} - - -static int __forceinline parity(unsigned w) //VALIDATED -{ - w = w >> 16; - w = w >> 8; - w = w >> 4; - w = w >> 2; - w = w >> 1; - return w & 1; -} - - -static int __forceinline log2(unsigned w) //VALIDATED -{ - int n = 0; - - if (w >> 16) - { - w >>= 16; - n+=16; - } - if (w >> 8) - { - w >>= 8; - n+=8; - } - if (w >> 4) - { - w >>= 4; - n+=4; - } - - w <<= 1; - return ((0xFFFFAA50 >> w) & 3)+n; -} - - - -#endif \ No newline at end of file +#endif Index: llvm/lib/Reoptimizer/BinInterface/test1.cpp diff -u llvm/lib/Reoptimizer/BinInterface/test1.cpp:1.1 llvm/lib/Reoptimizer/BinInterface/test1.cpp:1.2 --- llvm/lib/Reoptimizer/BinInterface/test1.cpp:1.1 Fri Nov 8 04:38:14 2002 +++ llvm/lib/Reoptimizer/BinInterface/test1.cpp Wed Nov 13 14:17:52 2002 @@ -1,69 +1,57 @@ #include #include -#include "sparc9.hp" +#include +#include +#include +#include "sparc9.h" #include "analyze.h" #include "sparcdis.h" -#include - -#include -#include -using std::vector; - +#include "BinInterface.h" +using std::vector; // cache line is 2^4 bytes #define MSA_CACHE_LINE 4 - -#include "BinInterface.h" - - //********************************* // Fast Vector Class //********************************* - - - - - - unsigned ex1[] = {0x853A2001, 0x92120009, 0x8528A00C, 0x900A0002, 0x81C3E008}; - - unsigned ex1_prolog[] = {0x86100008}; unsigned ex1_trace[] = {0x8400FFFF, 0x8688C002, 0x12BFFFFE, 0x92026001}; unsigned ex1_epilog[] = {0x81C3E008}; #define arrsize(x) (sizeof(x) / sizeof(*x)) - void main() { - BinInterface bin(1024); + BinInterface bin(1024); - unsigned __int64 s,e,f; - QueryPerformanceCounter((LARGE_INTEGER *)&s); + unsigned __int64 s,e,f; + QueryPerformanceCounter((LARGE_INTEGER *)&s); - for (int l = 0; l<1024;l++) - { - bin.clear(); - unsigned epilog = bin.newepilog(); - bin.insert(BinInterface::SECTION_PROLOG,ex1_prolog, ex1_prolog + arrsize(ex1_prolog)); - bin.insert(BinInterface::SECTION_TRACE,ex1_trace, ex1_trace + arrsize(ex1_trace)); - bin.insert(epilog,ex1_epilog, ex1_epilog + arrsize(ex1_epilog)); - bin.reduce(); - } - QueryPerformanceCounter((LARGE_INTEGER *)&e); - QueryPerformanceFrequency((LARGE_INTEGER *)&f); - - e-=s; - e*=1000000000; - e/=f; - - double nsi = e; - nsi/=1024; - printf("Executed in %gns per iteration.\n", nsi); - - bin.print(); - getchar(); -} + for (int l = 0; l<1024;l++) + { + bin.clear(); + unsigned epilog = bin.newepilog(); + bin.insert(BinInterface::SECTION_PROLOG, ex1_prolog, + ex1_prolog + arrsize(ex1_prolog)); + bin.insert(BinInterface::SECTION_TRACE, ex1_trace, + ex1_trace + arrsize(ex1_trace)); + bin.insert(epilog,ex1_epilog, ex1_epilog + arrsize(ex1_epilog)); + bin.reduce(); + } + QueryPerformanceCounter((LARGE_INTEGER *)&e); + QueryPerformanceFrequency((LARGE_INTEGER *)&f); + + e-=s; + e*=1000000000; + e/=f; + + double nsi = e; + nsi/=1024; + printf("Executed in %gns per iteration.\n", nsi); + + bin.print(); + getchar(); +} Index: llvm/lib/Reoptimizer/BinInterface/sparcdis.cpp diff -u llvm/lib/Reoptimizer/BinInterface/sparcdis.cpp:1.2 llvm/lib/Reoptimizer/BinInterface/sparcdis.cpp:1.3 --- llvm/lib/Reoptimizer/BinInterface/sparcdis.cpp:1.2 Tue Nov 12 20:47:14 2002 +++ llvm/lib/Reoptimizer/BinInterface/sparcdis.cpp Wed Nov 13 14:17:52 2002 @@ -1,14 +1,12 @@ //===-----------------------------------------------------------*- C++ -*--===// // SPARC Disassembler // -// // // 2002 Cameron Buschardt //===----------------------------------------------------------------------===// #include #include - #include "sparc9.h" void sparc_printbr(unsigned instr) Index: llvm/lib/Reoptimizer/BinInterface/sparcdis.h diff -u llvm/lib/Reoptimizer/BinInterface/sparcdis.h:1.1 llvm/lib/Reoptimizer/BinInterface/sparcdis.h:1.2 --- llvm/lib/Reoptimizer/BinInterface/sparcdis.h:1.1 Fri Nov 8 04:38:14 2002 +++ llvm/lib/Reoptimizer/BinInterface/sparcdis.h Wed Nov 13 14:17:52 2002 @@ -1,2 +1 @@ -void sparc_print(unsigned instr); - +void sparc_print(unsigned instr); From lattner at cs.uiuc.edu Thu Nov 14 16:33:01 2002 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Thu Nov 14 16:33:01 2002 Subject: [llvm-commits] CVS: llvm/lib/Target/X86/InstSelectSimple.cpp Printer.cpp X86InstrInfo.def X86RegisterInfo.def Message-ID: <200211142232.QAA12380@psmith.cs.uiuc.edu> Changes in directory llvm/lib/Target/X86: InstSelectSimple.cpp updated: 1.23 -> 1.24 Printer.cpp updated: 1.3 -> 1.4 X86InstrInfo.def updated: 1.14 -> 1.15 X86RegisterInfo.def updated: 1.2 -> 1.3 --- Log message: include/llvm/CodeGen/MachineInstrBuilder.h: Add addClobber() inline convenience method. Fix typo in comment. lib/Target/X86/InstSelectSimple.cpp: Explicitly specify some implicit uses. Use MOVZX/MOVSX instead of MOV instructions with sign extend instructions. Take out LEAVE instructions. 32-bit IDIV and DIV use CDQ, not CWQ (CWQ is a typo). Fix typo in comment and remove some FIXME comments. lib/Target/X86/Printer.cpp: Include X86InstrInfo.h and llvm/Function.h. Add some simple code to Printer::runOnFunction to iterate over MachineBasicBlocks and call X86InstrInfo::print(). lib/Target/X86/X86InstrInfo.def: Make some more instructions with implicit defs "Void". Add more sign/zero extending "move" insns (movsx, movzx). lib/Target/X86/X86RegisterInfo.def: Add EFLAGS as a register. --- Diffs of the changes: Index: llvm/lib/Target/X86/InstSelectSimple.cpp diff -u llvm/lib/Target/X86/InstSelectSimple.cpp:1.23 llvm/lib/Target/X86/InstSelectSimple.cpp:1.24 --- llvm/lib/Target/X86/InstSelectSimple.cpp:1.23 Mon Nov 11 13:37:09 2002 +++ llvm/lib/Target/X86/InstSelectSimple.cpp Thu Nov 14 16:32:30 2002 @@ -211,33 +211,30 @@ break; } // (Non-trapping) compare and pop twice. - // FIXME: Result of comparison -> condition codes, not a register. BuildMI (BB, X86::FUCOMPP, 0); // Move fp status word (concodes) to ax. BuildMI (BB, X86::FNSTSWr8, 1, X86::AX); // Load real concodes from ax. - // FIXME: Once again, flags are not modeled. - BuildMI (BB, X86::SAHF, 0); + BuildMI (BB, X86::SAHF, 1, X86::EFLAGS).addReg(X86::AH); } else { // integer comparison // Emit: cmp , (do the comparison). We can // compare 8-bit with 8-bit, 16-bit with 16-bit, 32-bit with // 32-bit. - // FIXME: Result of comparison -> condition codes, not a register. switch (comparisonWidth) { case 1: BuildMI (BB, X86::CMPrr8, 2, - X86::NoReg).addReg (reg1).addReg (reg2); + X86::EFLAGS).addReg (reg1).addReg (reg2); break; case 2: BuildMI (BB, X86::CMPrr16, 2, - X86::NoReg).addReg (reg1).addReg (reg2); + X86::EFLAGS).addReg (reg1).addReg (reg2); break; case 4: BuildMI (BB, X86::CMPrr32, 2, - X86::NoReg).addReg (reg1).addReg (reg2); + X86::EFLAGS).addReg (reg1).addReg (reg2); break; case 8: default: @@ -297,15 +294,11 @@ case 1: BuildMI (BB, X86::MOVrr8, 1, resultReg).addReg (X86::AL); break; - // FIXME: What to do about implicit destination registers? - // E.g., you don't specify it, but CBW is more like AX = CBW(AL). case 2: - BuildMI (BB, X86::CBW, 0, X86::AX); - BuildMI (BB, X86::MOVrr16, 1, resultReg).addReg (X86::AX); + BuildMI (BB, X86::MOVZXr16r8, 1, resultReg).addReg (X86::AL); break; case 4: - BuildMI (BB, X86::CWDE, 0, X86::EAX); - BuildMI (BB, X86::MOVrr32, 1, resultReg).addReg (X86::EAX); + BuildMI (BB, X86::MOVZXr32r8, 1, resultReg).addReg (X86::AL); break; case 8: default: @@ -331,6 +324,7 @@ { if (I.getNumOperands () == 1) { + bool unsignedReturnValue = I.getOperand(0)->getType()->isUnsigned(); unsigned val = getReg (I.getOperand (0)); unsigned operandSize = I.getOperand (0)->getType ()->getPrimitiveSize (); @@ -358,21 +352,22 @@ { case 1: // ret sbyte, ubyte: Extend value into EAX and return - // MOV AL, - // CBW - BuildMI (BB, X86::MOVrr8, 1, X86::AL).addReg (val); - BuildMI (BB, X86::CBW, 0); + if (unsignedReturnValue) { + BuildMI (BB, X86::MOVZXr32r8, 1, X86::EAX).addReg (val); + } else { + BuildMI (BB, X86::MOVSXr32r8, 1, X86::EAX).addReg (val); + } break; case 2: // ret short, ushort: Extend value into EAX and return - // MOV AX, - // CWDE - BuildMI (BB, X86::MOVrr16, 1, X86::AX).addReg (val); - BuildMI (BB, X86::CWDE, 0); + if (unsignedReturnValue) { + BuildMI (BB, X86::MOVZXr32r16, 1, X86::EAX).addReg (val); + } else { + BuildMI (BB, X86::MOVSXr32r16, 1, X86::EAX).addReg (val); + } break; case 4: // ret int, uint, ptr: Move value into EAX and return - // MOV EAX, BuildMI (BB, X86::MOVrr32, 1, X86::EAX).addReg (val); break; case 8: @@ -387,8 +382,7 @@ } } } - // Emit a 'leave' and a 'ret' - BuildMI (BB, X86::LEAVE, 0); + // Emit a 'ret' -- the 'leave' will be added by the reg allocator, I guess? BuildMI (BB, X86::RET, 0); } @@ -473,7 +467,7 @@ static const unsigned Regs[] ={ X86::AL , X86::AX , X86::EAX }; static const unsigned MovOpcode[]={ X86::MOVrr8, X86::MOVrr16, X86::MOVrr32 }; - static const unsigned ExtOpcode[]={ X86::CBW , X86::CWD , X86::CWQ }; + static const unsigned ExtOpcode[]={ X86::CBW , X86::CWD , X86::CDQ }; static const unsigned ClrOpcode[]={ X86::XORrr8, X86::XORrr16, X86::XORrr32 }; static const unsigned ExtRegs[] ={ X86::AH , X86::DX , X86::EDX }; @@ -502,7 +496,7 @@ // Figure out which register we want to pick the result out of... unsigned DestReg = (I.getOpcode() == Instruction::Div) ? Reg : ExtReg; - // Emit the appropriate multiple instruction... + // Emit the appropriate divide or remainder instruction... // FIXME: We need to mark that this modified AH, DX, or EDX also!! BuildMI(BB,DivOpcode[isSigned][Class], 2, DestReg).addReg(Reg).addReg(Op1Reg); Index: llvm/lib/Target/X86/Printer.cpp diff -u llvm/lib/Target/X86/Printer.cpp:1.3 llvm/lib/Target/X86/Printer.cpp:1.4 --- llvm/lib/Target/X86/Printer.cpp:1.3 Tue Oct 29 16:37:54 2002 +++ llvm/lib/Target/X86/Printer.cpp Thu Nov 14 16:32:30 2002 @@ -6,7 +6,10 @@ //===----------------------------------------------------------------------===// #include "X86.h" +#include "X86InstrInfo.h" #include "llvm/Pass.h" +#include "llvm/Function.h" +#include "llvm/Target/TargetMachine.h" #include "llvm/CodeGen/MachineFunction.h" #include @@ -21,17 +24,40 @@ }; } -bool Printer::runOnFunction(Function &F) { - MachineFunction &MF = MachineFunction::get(&F); - O << "x86 printing not implemented yet!\n"; - - // This should use the X86InstructionInfo::print method to print assembly - // for each instruction +/// runOnFunction - This uses the X86InstructionInfo::print method +/// to print assembly for each instruction. +bool Printer::runOnFunction (Function & F) +{ + static unsigned bbnumber = 0; + MachineFunction & MF = MachineFunction::get (&F); + const MachineInstrInfo & MII = TM.getInstrInfo (); + const X86InstrInfo & x86ii = dynamic_cast (MII); + + O << "# x86 printing not implemented yet!\n"; + + // Print out labels for the function. + O << "\t.globl\t" << F.getName () << "\n"; + O << "\t.type\t" << F.getName () << ", @function\n"; + O << F.getName () << ":\n"; + + // Print out code for the function. + for (MachineFunction::const_iterator bb_i = MF.begin (), bb_e = MF.end (); + bb_i != bb_e; ++bb_i) + { + // Print a label for the basic block. + O << ".BB" << bbnumber++ << ":\n"; + for (MachineBasicBlock::const_iterator i_i = bb_i->begin (), i_e = + bb_i->end (); i_i != i_e; ++i_i) + { + // Print the assembly for the instruction. + O << "\t"; + x86ii.print (*i_i, O); + } + } + + // We didn't modify anything. return false; } - - - /// createX86CodePrinterPass - Print out the specified machine code function to /// the specified stream. This function should work regardless of whether or Index: llvm/lib/Target/X86/X86InstrInfo.def diff -u llvm/lib/Target/X86/X86InstrInfo.def:1.14 llvm/lib/Target/X86/X86InstrInfo.def:1.15 --- llvm/lib/Target/X86/X86InstrInfo.def:1.14 Mon Nov 11 13:37:09 2002 +++ llvm/lib/Target/X86/X86InstrInfo.def Thu Nov 14 16:32:30 2002 @@ -99,14 +99,14 @@ I(SARir32 , "sarl", 0, 0) // R32 >>= imm8 C1/7 ib // Floating point loads -I(FLDr4 , "flds", 0, 0) // push float D9/0 -I(FLDr8 , "fldl ", 0, 0) // push double DD/0 +I(FLDr4 , "flds", 0, X86II::Void) // push float D9/0 +I(FLDr8 , "fldl ", 0, X86II::Void) // push double DD/0 // Floating point compares -I(FUCOMPP , "fucompp", 0, 0) // compare+pop2x DA E9 +I(FUCOMPP , "fucompp", 0, X86II::Void) // compare+pop2x DA E9 // Floating point flag ops -I(FNSTSWr8 , "fnstsw", 0, 0) // AX = fp flags DF E0 +I(FNSTSWr8 , "fnstsw", 0, X86II::Void) // AX = fp flags DF E0 // Condition code ops, incl. set if equal/not equal/... I(SAHF , "sahf", 0, 0) // flags = AH 9E @@ -126,11 +126,16 @@ I(CMPrr16 , "cmpw", 0, 0) // compare R16,R16 39/r I(CMPrr32 , "cmpl", 0, 0) // compare R32,R32 39/r -// Sign extenders -I(CBW , "cbw", 0, 0) // AH = signext(AL) 98 -I(CWD , "cwd", 0, 0) // DX = signext(AX) 99 -I(CWQ , "cwq", 0, 0) // EDX= signext(EAX) 99 -I(CWDE , "cwde", 0, 0) // EAX = extend AX 98 +// Sign extenders (first 3 are good for DIV/IDIV; the others are more general) +I(CBW , "cbw", 0, 0) // AX = signext(AL) 98 +I(CWD , "cwd", 0, 0) // DX:AX = signext(AX) 99 +I(CDQ , "cdq", 0, 0) // EDX:EAX = signext(EAX) 99 +I(MOVSXr16r8 , "movsx", 0, 0) // R32 = signext(R8) 0F BE /r +I(MOVSXr32r8 , "movsx", 0, 0) // R32 = signext(R8) 0F BE /r +I(MOVSXr32r16 , "movsx", 0, 0) // R32 = signext(R16) 0F BF /r +I(MOVZXr16r8 , "movzx", 0, 0) // R32 = zeroext(R8) 0F B6 /r +I(MOVZXr32r8 , "movzx", 0, 0) // R32 = zeroext(R8) 0F B6 /r +I(MOVZXr32r16 , "movzx", 0, 0) // R32 = zeroext(R16) 0F B7 /r // At this point, I is dead, so undefine the macro #undef I Index: llvm/lib/Target/X86/X86RegisterInfo.def diff -u llvm/lib/Target/X86/X86RegisterInfo.def:1.2 llvm/lib/Target/X86/X86RegisterInfo.def:1.3 --- llvm/lib/Target/X86/X86RegisterInfo.def:1.2 Mon Oct 28 14:01:52 2002 +++ llvm/lib/Target/X86/X86RegisterInfo.def Thu Nov 14 16:32:30 2002 @@ -64,5 +64,10 @@ // Flags, Segment registers, etc... +// This is a slimy hack to make it possible to say that flags are clobbered... +// Ideally we'd model instructions based on which particular flag(s) they +// could clobber. +R(EFLAGS, "eflags", MRF::INT8, 0) + // We are now done with the R macro #undef R From lattner at cs.uiuc.edu Thu Nov 14 16:33:05 2002 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Thu Nov 14 16:33:05 2002 Subject: [llvm-commits] CVS: llvm/include/llvm/CodeGen/MachineInstrBuilder.h Message-ID: <200211142232.QAA12373@psmith.cs.uiuc.edu> Changes in directory llvm/include/llvm/CodeGen: MachineInstrBuilder.h updated: 1.4 -> 1.5 --- Log message: include/llvm/CodeGen/MachineInstrBuilder.h: Add addClobber() inline convenience method. Fix typo in comment. lib/Target/X86/InstSelectSimple.cpp: Explicitly specify some implicit uses. Use MOVZX/MOVSX instead of MOV instructions with sign extend instructions. Take out LEAVE instructions. 32-bit IDIV and DIV use CDQ, not CWQ (CWQ is a typo). Fix typo in comment and remove some FIXME comments. lib/Target/X86/Printer.cpp: Include X86InstrInfo.h and llvm/Function.h. Add some simple code to Printer::runOnFunction to iterate over MachineBasicBlocks and call X86InstrInfo::print(). lib/Target/X86/X86InstrInfo.def: Make some more instructions with implicit defs "Void". Add more sign/zero extending "move" insns (movsx, movzx). lib/Target/X86/X86RegisterInfo.def: Add EFLAGS as a register. --- Diffs of the changes: Index: llvm/include/llvm/CodeGen/MachineInstrBuilder.h diff -u llvm/include/llvm/CodeGen/MachineInstrBuilder.h:1.4 llvm/include/llvm/CodeGen/MachineInstrBuilder.h:1.5 --- llvm/include/llvm/CodeGen/MachineInstrBuilder.h:1.4 Tue Oct 29 19:48:41 2002 +++ llvm/include/llvm/CodeGen/MachineInstrBuilder.h Thu Nov 14 16:32:30 2002 @@ -34,10 +34,19 @@ return *this; } - /// addReg - Add an LLVM value that is to be used as a register...x + /// addReg - Add an LLVM value that is to be used as a register... /// MachineInstrBuilder &addReg(Value *V, bool isDef = false, bool isDNU = false){ MI->addRegOperand(V, isDef, isDNU); + return *this; + } + + /// addClobber - Assert that this MI is going to clobber a specific + /// register. Useful for instructions that always clobber certain hard regs. + /// (Same as addReg(RegNo, true) but shorter and more obvious). + /// + MachineInstrBuilder &addClobber(int RegNo) { + MI->addRegOperand(RegNo, true); return *this; } From lattner at cs.uiuc.edu Fri Nov 15 12:05:00 2002 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Fri Nov 15 12:05:00 2002 Subject: [llvm-commits] CVS: llvm/include/Support/TarjanSCCIterator.h Message-ID: <200211151804.MAA12364@apoc.cs.uiuc.edu> Changes in directory llvm/include/Support: TarjanSCCIterator.h updated: 1.2 -> 1.3 --- Log message: Fix warning --- Diffs of the changes: Index: llvm/include/Support/TarjanSCCIterator.h diff -u llvm/include/Support/TarjanSCCIterator.h:1.2 llvm/include/Support/TarjanSCCIterator.h:1.3 --- llvm/include/Support/TarjanSCCIterator.h:1.2 Sun Nov 10 17:46:31 2002 +++ llvm/include/Support/TarjanSCCIterator.h Fri Nov 15 12:04:16 2002 @@ -56,8 +56,6 @@ // reverse topological order of the SCC DAG. //-------------------------------------------------------------------------- -const unsigned long MAXLONG = (1 << (8 * sizeof(unsigned long) - 1)); - namespace { Statistic<> NumSCCs("NumSCCs", "Number of Strongly Connected Components"); Statistic<> MaxSCCSize("MaxSCCSize", "Size of largest Strongly Connected Component"); @@ -152,7 +150,7 @@ do { CurrentSCC.push_back(SCCNodeStack.top()); SCCNodeStack.pop(); - nodeVisitNumbers[CurrentSCC.back()] = MAXLONG; + nodeVisitNumbers[CurrentSCC.back()] = ~0UL; } while (CurrentSCC.back() != visitingN); ++NumSCCs; From hldnbrnd at cs.uiuc.edu Fri Nov 15 15:19:01 2002 From: hldnbrnd at cs.uiuc.edu (Nicholas Hildenbrandt) Date: Fri Nov 15 15:19:01 2002 Subject: [llvm-commits] CVS: llvm/www/docs/TestStatus.html Message-ID: <200211152118.PAA22917@tank.cs.uiuc.edu> Changes in directory llvm/www/docs: TestStatus.html updated: 1.15 -> 1.16 --- Log message: Updates --- Diffs of the changes: Index: llvm/www/docs/TestStatus.html diff -u llvm/www/docs/TestStatus.html:1.15 llvm/www/docs/TestStatus.html:1.16 --- llvm/www/docs/TestStatus.html:1.15 Thu Nov 7 16:57:41 2002 +++ llvm/www/docs/TestStatus.html Fri Nov 15 15:18:22 2002 @@ -3,7 +3,7 @@

Test Results

-
last updated: 11/07/2002
+
last updated: 11/15/2002
tests current: 11/07/2002

SingleSource

@@ -73,8 +73,8 @@ - - + + From lattner at cs.uiuc.edu Sun Nov 17 14:08:01 2002 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Sun Nov 17 14:08:01 2002 Subject: [llvm-commits] CVS: llvm/lib/Target/X86/InstSelectSimple.cpp Message-ID: <200211172007.OAA10418@apoc.cs.uiuc.edu> Changes in directory llvm/lib/Target/X86: InstSelectSimple.cpp updated: 1.24 -> 1.25 --- Log message: Switch visitRet to use getClass() --- Diffs of the changes: Index: llvm/lib/Target/X86/InstSelectSimple.cpp diff -u llvm/lib/Target/X86/InstSelectSimple.cpp:1.24 llvm/lib/Target/X86/InstSelectSimple.cpp:1.25 --- llvm/lib/Target/X86/InstSelectSimple.cpp:1.24 Thu Nov 14 16:32:30 2002 +++ llvm/lib/Target/X86/InstSelectSimple.cpp Sun Nov 17 14:07:45 2002 @@ -17,7 +17,6 @@ #include "llvm/CodeGen/MachineFunction.h" #include "llvm/CodeGen/MachineInstrBuilder.h" #include "llvm/Support/InstVisitor.h" -#include namespace { struct ISel : public FunctionPass, InstVisitor { @@ -113,26 +112,33 @@ }; } +/// TypeClass - Used by the X86 backend to group LLVM types by their basic X86 +/// Representation. +/// +enum TypeClass { + cByte, cShort, cInt, cLong, cFloat, cDouble +}; + /// getClass - Turn a primitive type into a "class" number which is based on the /// size of the type, and whether or not it is floating point. /// -static inline unsigned getClass(const Type *Ty) { +static inline TypeClass getClass(const Type *Ty) { switch (Ty->getPrimitiveID()) { case Type::SByteTyID: - case Type::UByteTyID: return 0; // Byte operands are class #0 + case Type::UByteTyID: return cByte; // Byte operands are class #0 case Type::ShortTyID: - case Type::UShortTyID: return 1; // Short operands are class #1 + case Type::UShortTyID: return cShort; // Short operands are class #1 case Type::IntTyID: case Type::UIntTyID: - case Type::PointerTyID: return 2; // Int's and pointers are class #2 + case Type::PointerTyID: return cInt; // Int's and pointers are class #2 case Type::LongTyID: - case Type::ULongTyID: return 3; // Longs are class #3 - case Type::FloatTyID: return 4; // Float is class #4 - case Type::DoubleTyID: return 5; // Doubles are class #5 + case Type::ULongTyID: return cLong; // Longs are class #3 + case Type::FloatTyID: return cFloat; // Float is class #4 + case Type::DoubleTyID: return cDouble; // Doubles are class #5 default: assert(0 && "Invalid type to getClass!"); - return 0; // not reached + return cByte; // not reached } } @@ -319,71 +325,58 @@ /// ret long, ulong : Move value into EAX/EDX (?) and return /// ret float/double : ? Top of FP stack? XMM0? /// -void -ISel::visitReturnInst (ReturnInst & I) -{ - if (I.getNumOperands () == 1) - { - bool unsignedReturnValue = I.getOperand(0)->getType()->isUnsigned(); - unsigned val = getReg (I.getOperand (0)); - unsigned operandSize = - I.getOperand (0)->getType ()->getPrimitiveSize (); - bool isFP = I.getOperand (0)->getType ()->isFloatingPoint (); - if (isFP) - { - // ret float/double: top of FP stack - // FLD - switch (operandSize) - { - case 4: - BuildMI (BB, X86::FLDr4, 1, X86::NoReg).addReg (val); - break; - case 8: - BuildMI (BB, X86::FLDr8, 1, X86::NoReg).addReg (val); - break; - default: - visitInstruction (I); - break; - } - } - else - { - switch (operandSize) - { - case 1: - // ret sbyte, ubyte: Extend value into EAX and return - if (unsignedReturnValue) { - BuildMI (BB, X86::MOVZXr32r8, 1, X86::EAX).addReg (val); - } else { - BuildMI (BB, X86::MOVSXr32r8, 1, X86::EAX).addReg (val); - } - break; - case 2: - // ret short, ushort: Extend value into EAX and return - if (unsignedReturnValue) { - BuildMI (BB, X86::MOVZXr32r16, 1, X86::EAX).addReg (val); - } else { - BuildMI (BB, X86::MOVSXr32r16, 1, X86::EAX).addReg (val); - } - break; - case 4: - // ret int, uint, ptr: Move value into EAX and return - BuildMI (BB, X86::MOVrr32, 1, X86::EAX).addReg (val); - break; - case 8: - // ret long: use EAX(least significant 32 bits)/EDX (most - // significant 32)...uh, I think so Brain, but how do i call - // up the two parts of the value from inside this mouse - // cage? *zort* - default: - // abort - visitInstruction (I); - break; - } - } +void ISel::visitReturnInst (ReturnInst & I) { + if (I.getNumOperands() == 0) { + // Emit a 'ret' instruction + BuildMI(BB, X86::RET, 0); + return; + } + + unsigned val = getReg(I.getOperand(0)); + unsigned Class = getClass(I.getType()); + bool isUnsigned = I.getOperand(0)->getType()->isUnsigned(); + switch (Class) { + case cByte: + // ret sbyte, ubyte: Extend value into EAX and return + if (isUnsigned) { + BuildMI (BB, X86::MOVZXr32r8, 1, X86::EAX).addReg (val); + } else { + BuildMI (BB, X86::MOVSXr32r8, 1, X86::EAX).addReg (val); + } + break; + case cShort: + // ret short, ushort: Extend value into EAX and return + if (unsignedReturnValue) { + BuildMI (BB, X86::MOVZXr32r16, 1, X86::EAX).addReg (val); + } else { + BuildMI (BB, X86::MOVSXr32r16, 1, X86::EAX).addReg (val); } - // Emit a 'ret' -- the 'leave' will be added by the reg allocator, I guess? - BuildMI (BB, X86::RET, 0); + break; + case cInt: + // ret int, uint, ptr: Move value into EAX and return + // MOV EAX, + BuildMI(BB, X86::MOVrr32, 1, X86::EAX).addReg(val); + break; + + // ret float/double: top of FP stack + // FLD + case cFloat: // Floats + BuildMI(BB, X86::FLDr4, 1).addReg(val); + break; + case cDouble: // Doubles + BuildMI(BB, X86::FLDr8, 1).addReg(val); + break; + case cLong: + // ret long: use EAX(least significant 32 bits)/EDX (most + // significant 32)...uh, I think so Brain, but how do i call + // up the two parts of the value from inside this mouse + // cage? *zort* + default: + visitInstruction(I); + } + + // Emit a 'ret' instruction + BuildMI(BB, X86::RET, 0); } /// visitBranchInst - Handle conditional and unconditional branches here. Note From lattner at cs.uiuc.edu Sun Nov 17 14:34:00 2002 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Sun Nov 17 14:34:00 2002 Subject: [llvm-commits] CVS: llvm/lib/Target/X86/README.txt Message-ID: <200211172033.OAA14419@apoc.cs.uiuc.edu> Changes in directory llvm/lib/Target/X86: README.txt updated: 1.2 -> 1.3 --- Log message: Add information about memory index representation --- Diffs of the changes: Index: llvm/lib/Target/X86/README.txt diff -u llvm/lib/Target/X86/README.txt:1.2 llvm/lib/Target/X86/README.txt:1.3 --- llvm/lib/Target/X86/README.txt:1.2 Wed Oct 30 00:04:46 2002 +++ llvm/lib/Target/X86/README.txt Sun Nov 17 14:33:26 2002 @@ -128,8 +128,33 @@ bunch of really trivial testcases that we should build up to supporting. +=================================================== +IV. Strange Things, or, Things That Should Be Known +=================================================== + +Representing memory in MachineInstrs +------------------------------------ + +The x86 has a very, uhm, flexible, way of accessing memory. It is capable of +addressing memory addresses of the following form directly in integer +instructions (which use ModR/M addressing): + + Base+[1,2,4,8]*IndexReg+Disp32 + +Wow, that's crazy. In order to represent this, LLVM tracks no less that 4 +operands for each memory operand of this form. This means that the "load" form +of 'mov' has the following "Operands" in this order: + +Index: 0 | 1 2 3 4 +Meaning: DestReg, | BaseReg, Scale, IndexReg, Displacement +OperandTy: VirtReg, | VirtReg, UnsImm, VirtReg, SignExtImm + +Stores and all other instructions treat the four memory operands in the same +way, in the same order. + + ========================== -IV. TODO / Future Projects +V. TODO / Future Projects ========================== There are a large number of things remaining to do. Here is a partial list: From lattner at cs.uiuc.edu Sun Nov 17 14:34:03 2002 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Sun Nov 17 14:34:03 2002 Subject: [llvm-commits] CVS: llvm/lib/Target/X86/X86InstrInfo.def Message-ID: <200211172033.OAA14424@apoc.cs.uiuc.edu> Changes in directory llvm/lib/Target/X86: X86InstrInfo.def updated: 1.15 -> 1.16 --- Log message: Add load/store instructions --- Diffs of the changes: Index: llvm/lib/Target/X86/X86InstrInfo.def diff -u llvm/lib/Target/X86/X86InstrInfo.def:1.15 llvm/lib/Target/X86/X86InstrInfo.def:1.16 --- llvm/lib/Target/X86/X86InstrInfo.def:1.15 Thu Nov 14 16:32:30 2002 +++ llvm/lib/Target/X86/X86InstrInfo.def Sun Nov 17 14:33:12 2002 @@ -37,6 +37,9 @@ I(RET , "ret", M_RET_FLAG, X86II::Void) // ret CB I(JMP , "jmp", M_BRANCH_FLAG, X86II::Void) // jmp foo EB|E9 cb|w +// Misc instructions +I(LEAVE , "leave", 0, 0) // leave C9 + // Move instructions I(MOVrr8 , "movb", 0, 0) // R8 = R8 88/r I(MOVrr16 , "movw", 0, 0) // R16 = R16 89/r @@ -44,7 +47,12 @@ I(MOVir8 , "movb", 0, 0) // R8 = imm8 B0+ rb I(MOVir16 , "movw", 0, 0) // R16 = imm16 B8+ rw I(MOVir32 , "movl", 0, 0) // R32 = imm32 B8+ rd -I(LEAVE , "leave", 0, 0) // leave C9 +I(MOVmr8 , "movb", 0, 0) // R8 = [mem] 8A/r +I(MOVmr16 , "movw", 0, 0) // R16 = [mem] 8B/r +I(MOVmr32 , "movl", 0, 0) // R32 = [mem] 8B/r +I(MOVrm8 , "movb", 0, 0) // [mem] = R8 88/r +I(MOVrm16 , "movw", 0, 0) // [mem] = R16 89/r +I(MOVrm32 , "movl", 0, 0) // [mem] = R32 89/r // Arithmetic instructions I(ADDrr8 , "addb", 0, 0) // R8 += R8 00/r From lattner at cs.uiuc.edu Sun Nov 17 15:03:01 2002 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Sun Nov 17 15:03:01 2002 Subject: [llvm-commits] CVS: llvm/include/llvm/CodeGen/MachineInstrBuilder.h Message-ID: <200211172102.PAA15194@apoc.cs.uiuc.edu> Changes in directory llvm/include/llvm/CodeGen: MachineInstrBuilder.h updated: 1.5 -> 1.6 --- Log message: Return const refefrences to enable default construction --- Diffs of the changes: Index: llvm/include/llvm/CodeGen/MachineInstrBuilder.h diff -u llvm/include/llvm/CodeGen/MachineInstrBuilder.h:1.5 llvm/include/llvm/CodeGen/MachineInstrBuilder.h:1.6 --- llvm/include/llvm/CodeGen/MachineInstrBuilder.h:1.5 Thu Nov 14 16:32:30 2002 +++ llvm/include/llvm/CodeGen/MachineInstrBuilder.h Sun Nov 17 15:02:42 2002 @@ -29,14 +29,15 @@ /// addReg - Add a new virtual register operand... /// - MachineInstrBuilder &addReg(int RegNo, bool isDef = false) { + const MachineInstrBuilder &addReg(int RegNo, bool isDef = false) const { MI->addRegOperand(RegNo, isDef); return *this; } /// addReg - Add an LLVM value that is to be used as a register... /// - MachineInstrBuilder &addReg(Value *V, bool isDef = false, bool isDNU = false){ + const MachineInstrBuilder &addReg(Value *V, bool isDef = false, + bool isDNU = false) const { MI->addRegOperand(V, isDef, isDNU); return *this; } @@ -45,7 +46,7 @@ /// register. Useful for instructions that always clobber certain hard regs. /// (Same as addReg(RegNo, true) but shorter and more obvious). /// - MachineInstrBuilder &addClobber(int RegNo) { + const MachineInstrBuilder &addClobber(int RegNo) const { MI->addRegOperand(RegNo, true); return *this; } @@ -53,28 +54,28 @@ /// addPCDisp - Add an LLVM value to be treated as a PC relative /// displacement... /// - MachineInstrBuilder &addPCDisp(Value *V) { + const MachineInstrBuilder &addPCDisp(Value *V) const { MI->addPCDispOperand(V); return *this; } /// addMReg - Add a machine register operand... /// - MachineInstrBuilder &addMReg(int Reg, bool isDef=false) { + const MachineInstrBuilder &addMReg(int Reg, bool isDef = false) const { MI->addMachineRegOperand(Reg, isDef); return *this; } /// addSImm - Add a new sign extended immediate operand... /// - MachineInstrBuilder &addSImm(int64_t val) { + const MachineInstrBuilder &addSImm(int64_t val) const { MI->addSignExtImmOperand(val); return *this; } /// addZImm - Add a new zero extended immediate operand... /// - MachineInstrBuilder &addZImm(int64_t Val) { + const MachineInstrBuilder &addZImm(int64_t Val) const { MI->addZeroExtImmOperand(Val); return *this; } From lattner at cs.uiuc.edu Sun Nov 17 15:04:01 2002 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Sun Nov 17 15:04:01 2002 Subject: [llvm-commits] CVS: llvm/lib/Target/X86/X86InstrBuilder.h Message-ID: <200211172103.PAA15205@apoc.cs.uiuc.edu> Changes in directory llvm/lib/Target/X86: X86InstrBuilder.h added (r1.1) --- Log message: Add functions to buld X86 specific constructs --- Diffs of the changes: From lattner at cs.uiuc.edu Sun Nov 17 15:07:02 2002 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Sun Nov 17 15:07:02 2002 Subject: [llvm-commits] CVS: llvm/test/Regression/Jello/test-loadstore.ll Message-ID: <200211172106.PAA15332@apoc.cs.uiuc.edu> Changes in directory llvm/test/Regression/Jello: test-loadstore.ll added (r1.1) --- Log message: New testcase for loads and stores --- Diffs of the changes: From lattner at cs.uiuc.edu Sun Nov 17 15:13:01 2002 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Sun Nov 17 15:13:01 2002 Subject: [llvm-commits] CVS: llvm/lib/Target/X86/InstSelectSimple.cpp Message-ID: <200211172112.PAA15438@apoc.cs.uiuc.edu> Changes in directory llvm/lib/Target/X86: InstSelectSimple.cpp updated: 1.25 -> 1.26 --- Log message: Fix a few typos, implement load/store --- Diffs of the changes: Index: llvm/lib/Target/X86/InstSelectSimple.cpp diff -u llvm/lib/Target/X86/InstSelectSimple.cpp:1.25 llvm/lib/Target/X86/InstSelectSimple.cpp:1.26 --- llvm/lib/Target/X86/InstSelectSimple.cpp:1.25 Sun Nov 17 14:07:45 2002 +++ llvm/lib/Target/X86/InstSelectSimple.cpp Sun Nov 17 15:11:55 2002 @@ -6,16 +6,17 @@ #include "X86.h" #include "X86InstrInfo.h" +#include "X86InstrBuilder.h" #include "llvm/Function.h" #include "llvm/iTerminators.h" #include "llvm/iOperators.h" #include "llvm/iOther.h" #include "llvm/iPHINode.h" +#include "llvm/iMemory.h" #include "llvm/Type.h" #include "llvm/Constants.h" #include "llvm/Pass.h" #include "llvm/CodeGen/MachineFunction.h" -#include "llvm/CodeGen/MachineInstrBuilder.h" #include "llvm/Support/InstVisitor.h" namespace { @@ -74,10 +75,14 @@ void visitXor(BinaryOperator &B) { visitSimpleBinary(B, 4); } // Binary comparison operators + void visitSetCondInst(SetCondInst &I); + + // Memory Instructions + void visitLoadInst(LoadInst &I); + void visitStoreInst(StoreInst &I); // Other operators void visitShiftInst(ShiftInst &I); - void visitSetCondInst(SetCondInst &I); void visitPHINode(PHINode &I); void visitInstruction(Instruction &I) { @@ -325,7 +330,7 @@ /// ret long, ulong : Move value into EAX/EDX (?) and return /// ret float/double : ? Top of FP stack? XMM0? /// -void ISel::visitReturnInst (ReturnInst & I) { +void ISel::visitReturnInst (ReturnInst &I) { if (I.getNumOperands() == 0) { // Emit a 'ret' instruction BuildMI(BB, X86::RET, 0); @@ -333,24 +338,22 @@ } unsigned val = getReg(I.getOperand(0)); - unsigned Class = getClass(I.getType()); + unsigned Class = getClass(I.getOperand(0)->getType()); bool isUnsigned = I.getOperand(0)->getType()->isUnsigned(); switch (Class) { case cByte: // ret sbyte, ubyte: Extend value into EAX and return - if (isUnsigned) { + if (isUnsigned) BuildMI (BB, X86::MOVZXr32r8, 1, X86::EAX).addReg (val); - } else { + else BuildMI (BB, X86::MOVSXr32r8, 1, X86::EAX).addReg (val); - } break; case cShort: // ret short, ushort: Extend value into EAX and return - if (unsignedReturnValue) { + if (isUnsigned) BuildMI (BB, X86::MOVZXr32r16, 1, X86::EAX).addReg (val); - } else { + else BuildMI (BB, X86::MOVSXr32r16, 1, X86::EAX).addReg (val); - } break; case cInt: // ret int, uint, ptr: Move value into EAX and return @@ -434,7 +437,7 @@ static const unsigned MovOpcode[]={ X86::MOVrr8, X86::MOVrr16, X86::MOVrr32 }; unsigned Reg = Regs[Class]; - unsigned Op0Reg = getReg(I.getOperand(1)); + unsigned Op0Reg = getReg(I.getOperand(0)); unsigned Op1Reg = getReg(I.getOperand(1)); // Put the first operand into one of the A registers... @@ -472,7 +475,7 @@ bool isSigned = I.getType()->isSigned(); unsigned Reg = Regs[Class]; unsigned ExtReg = ExtRegs[Class]; - unsigned Op0Reg = getReg(I.getOperand(1)); + unsigned Op0Reg = getReg(I.getOperand(0)); unsigned Op1Reg = getReg(I.getOperand(1)); // Put the first operand into one of the A registers... @@ -557,6 +560,36 @@ BuildMI(BB, OpTab[OperandClass], 2, DestReg).addReg(Op0r).addReg(X86::CL); } } + +/// visitLoadInst - Implement LLVM load instructions in terms of the x86 'mov' +/// instruction. +/// +void ISel::visitLoadInst(LoadInst &I) { + unsigned Class = getClass(I.getType()); + if (Class > 2) // FIXME: Handle longs and others... + visitInstruction(I); + + static const unsigned Opcode[] = { X86::MOVmr8, X86::MOVmr16, X86::MOVmr32 }; + + unsigned AddressReg = getReg(I.getOperand(0)); + addDirectMem(BuildMI(BB, Opcode[Class], 4, getReg(I)), AddressReg); +} + +/// visitStoreInst - Implement LLVM store instructions in terms of the x86 'mov' +/// instruction. +/// +void ISel::visitStoreInst(StoreInst &I) { + unsigned Class = getClass(I.getOperand(0)->getType()); + if (Class > 2) // FIXME: Handle longs and others... + visitInstruction(I); + + static const unsigned Opcode[] = { X86::MOVrm8, X86::MOVrm16, X86::MOVrm32 }; + + unsigned ValReg = getReg(I.getOperand(0)); + unsigned AddressReg = getReg(I.getOperand(1)); + addDirectMem(BuildMI(BB, Opcode[Class], 1+4), AddressReg).addReg(ValReg); +} + /// visitPHINode - Turn an LLVM PHI node into an X86 PHI node... /// From lattner at cs.uiuc.edu Sun Nov 17 15:57:01 2002 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Sun Nov 17 15:57:01 2002 Subject: [llvm-commits] CVS: llvm/include/llvm/CodeGen/MachineInstr.h MachineInstrBuilder.h Message-ID: <200211172156.PAA17251@apoc.cs.uiuc.edu> Changes in directory llvm/include/llvm/CodeGen: MachineInstr.h updated: 1.84 -> 1.85 MachineInstrBuilder.h updated: 1.6 -> 1.7 --- Log message: Convert to use an enum to access def/use/use&def information. These make reading code much easier than just seeing "true, false" especially when default parameters default one but not both arguments. --- Diffs of the changes: Index: llvm/include/llvm/CodeGen/MachineInstr.h diff -u llvm/include/llvm/CodeGen/MachineInstr.h:1.84 llvm/include/llvm/CodeGen/MachineInstr.h:1.85 --- llvm/include/llvm/CodeGen/MachineInstr.h:1.84 Wed Oct 30 14:38:16 2002 +++ llvm/include/llvm/CodeGen/MachineInstr.h Sun Nov 17 15:56:10 2002 @@ -20,6 +20,20 @@ typedef int MachineOpCode; +/// MOTy - MachineOperandType - This namespace contains an enum that describes +/// how the machine operand is used by the instruction: is it read, defined, or +/// both? Note that the MachineInstr/Operator class currently uses bool +/// arguments to represent this information instead of an enum. Eventually this +/// should change over to use this _easier to read_ representation instead. +/// +namespace MOTy { + enum UseType { + Use, /// This machine operand is only read by the instruction + Def, /// This machine operand is only written by the instruction + UseAndDef /// This machine operand is read AND written + }; +} + //--------------------------------------------------------------------------- // class MachineOperand // @@ -102,18 +116,26 @@ flags(0), regNum(-1) {} - MachineOperand(int Reg, MachineOperandType OpTy, bool isDef = false) + MachineOperand(int Reg, MachineOperandType OpTy, MOTy::UseType UseTy) : immedVal(0), opType(OpTy), - flags(isDef ? DEFFLAG : 0), - regNum(Reg) {} - - MachineOperand(Value *V, MachineOperandType OpTy, - bool isDef = false, bool isDNU = false) - : value(V), - opType(OpTy), - regNum(-1) { - flags = (isDef ? DEFFLAG : 0) | (isDNU ? DEFUSEFLAG : 0); + regNum(Reg) { + switch (UseTy) { + case MOTy::Use: flags = 0; break; + case MOTy::Def: flags = DEFFLAG; break; + case MOTy::UseAndDef: flags = DEFUSEFLAG; break; + default: assert(0 && "Invalid value for UseTy!"); + } + } + + MachineOperand(Value *V, MachineOperandType OpTy, MOTy::UseType UseTy) + : value(V), opType(OpTy), regNum(-1) { + switch (UseTy) { + case MOTy::Use: flags = 0; break; + case MOTy::Def: flags = DEFFLAG; break; + case MOTy::UseAndDef: flags = DEFUSEFLAG; break; + default: assert(0 && "Invalid value for UseTy!"); + } } public: @@ -367,7 +389,14 @@ assert(!OperandsComplete() && "Trying to add an operand to a machine instr that is already done!"); operands.push_back(MachineOperand(V, MachineOperand::MO_VirtualRegister, - isDef, isDefAndUse)); + !isDef ? MOTy::Use : (isDefAndUse ? MOTy::UseAndDef : MOTy::Def))); + } + + void addRegOperand(Value *V, MOTy::UseType UTy = MOTy::Use) { + assert(!OperandsComplete() && + "Trying to add an operand to a machine instr that is already done!"); + operands.push_back(MachineOperand(V, MachineOperand::MO_VirtualRegister, + UTy)); } /// addRegOperand - Add a symbolic virtual register reference... @@ -376,7 +405,7 @@ assert(!OperandsComplete() && "Trying to add an operand to a machine instr that is already done!"); operands.push_back(MachineOperand(reg, MachineOperand::MO_VirtualRegister, - isDef)); + isDef ? MOTy::Def : MOTy::Use)); } /// addPCDispOperand - Add a PC relative displacement operand to the MI @@ -384,7 +413,8 @@ void addPCDispOperand(Value *V) { assert(!OperandsComplete() && "Trying to add an operand to a machine instr that is already done!"); - operands.push_back(MachineOperand(V, MachineOperand::MO_PCRelativeDisp)); + operands.push_back(MachineOperand(V, MachineOperand::MO_PCRelativeDisp, + MOTy::Use)); } /// addMachineRegOperand - Add a virtual register operand to this MachineInstr @@ -393,7 +423,7 @@ assert(!OperandsComplete() && "Trying to add an operand to a machine instr that is already done!"); operands.push_back(MachineOperand(reg, MachineOperand::MO_MachineRegister, - isDef)); + isDef ? MOTy::Def : MOTy::Use)); insertUsedReg(reg); } Index: llvm/include/llvm/CodeGen/MachineInstrBuilder.h diff -u llvm/include/llvm/CodeGen/MachineInstrBuilder.h:1.6 llvm/include/llvm/CodeGen/MachineInstrBuilder.h:1.7 --- llvm/include/llvm/CodeGen/MachineInstrBuilder.h:1.6 Sun Nov 17 15:02:42 2002 +++ llvm/include/llvm/CodeGen/MachineInstrBuilder.h Sun Nov 17 15:56:10 2002 @@ -18,7 +18,7 @@ #include "llvm/CodeGen/MachineInstr.h" -struct MachineInstrBuilder { +struct MachineInstrBuilder { MachineInstr *MI; MachineInstrBuilder(MachineInstr *mi) : MI(mi) {} @@ -29,16 +29,17 @@ /// addReg - Add a new virtual register operand... /// - const MachineInstrBuilder &addReg(int RegNo, bool isDef = false) const { - MI->addRegOperand(RegNo, isDef); + const MachineInstrBuilder &addReg(int RegNo, + MOTy::UseType Ty = MOTy::Use) const { + MI->addRegOperand(RegNo, Ty); return *this; } /// addReg - Add an LLVM value that is to be used as a register... /// - const MachineInstrBuilder &addReg(Value *V, bool isDef = false, - bool isDNU = false) const { - MI->addRegOperand(V, isDef, isDNU); + const MachineInstrBuilder &addReg(Value *V, + MOTy::UseType Ty = MOTy::Use) const { + MI->addRegOperand(V, Ty); return *this; } @@ -61,8 +62,9 @@ /// addMReg - Add a machine register operand... /// - const MachineInstrBuilder &addMReg(int Reg, bool isDef = false) const { - MI->addMachineRegOperand(Reg, isDef); + const MachineInstrBuilder &addMReg(int Reg, + MOTy::UseType Ty = MOTy::Use) const { + MI->addMachineRegOperand(Reg, Ty); return *this; } @@ -106,7 +108,7 @@ unsigned NumOperands, unsigned DestReg) { return MachineInstrBuilder(new MachineInstr(BB, Opcode, NumOperands+1)).addReg(DestReg, - true); + MOTy::Def); } #endif From lattner at cs.uiuc.edu Sun Nov 17 15:57:05 2002 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Sun Nov 17 15:57:05 2002 Subject: [llvm-commits] CVS: llvm/lib/Target/X86/InstSelectSimple.cpp Message-ID: <200211172156.PAA17262@apoc.cs.uiuc.edu> Changes in directory llvm/lib/Target/X86: InstSelectSimple.cpp updated: 1.26 -> 1.27 --- Log message: Fix Mul/Div clobbers --- Diffs of the changes: Index: llvm/lib/Target/X86/InstSelectSimple.cpp diff -u llvm/lib/Target/X86/InstSelectSimple.cpp:1.26 llvm/lib/Target/X86/InstSelectSimple.cpp:1.27 --- llvm/lib/Target/X86/InstSelectSimple.cpp:1.26 Sun Nov 17 15:11:55 2002 +++ llvm/lib/Target/X86/InstSelectSimple.cpp Sun Nov 17 15:56:38 2002 @@ -19,6 +19,8 @@ #include "llvm/CodeGen/MachineFunction.h" #include "llvm/Support/InstVisitor.h" +using namespace MOTy; // Get Use, Def, UseAndDef + namespace { struct ISel : public FunctionPass, InstVisitor { TargetMachine &TM; @@ -147,6 +149,7 @@ } } + /// copyConstantToRegister - Output the instructions required to put the /// specified constant into the specified register. /// @@ -173,6 +176,7 @@ } } + /// SetCC instructions - Here we just emit boilerplate code to set a byte-sized /// register, then move it to wherever the result should be. /// We handle FP setcc instructions by pushing them, doing a @@ -327,8 +331,8 @@ /// ret short, ushort: Extend value into EAX and return /// ret int, uint : Move value into EAX and return /// ret pointer : Move value into EAX and return -/// ret long, ulong : Move value into EAX/EDX (?) and return -/// ret float/double : ? Top of FP stack? XMM0? +/// ret long, ulong : Move value into EAX/EDX and return +/// ret float/double : Top of FP stack /// void ISel::visitReturnInst (ReturnInst &I) { if (I.getNumOperands() == 0) { @@ -382,6 +386,7 @@ BuildMI(BB, X86::RET, 0); } + /// visitBranchInst - Handle conditional and unconditional branches here. Note /// that since code layout is frozen at this point, that if we are trying to /// jump to a block that is the immediate successor of the current block, we can @@ -433,24 +438,27 @@ visitInstruction(I); static const unsigned Regs[] ={ X86::AL , X86::AX , X86::EAX }; + static const unsigned Clobbers[] ={ X86::AH , X86::DX , X86::EDX }; static const unsigned MulOpcode[]={ X86::MULrr8, X86::MULrr16, X86::MULrr32 }; static const unsigned MovOpcode[]={ X86::MOVrr8, X86::MOVrr16, X86::MOVrr32 }; - unsigned Reg = Regs[Class]; - unsigned Op0Reg = getReg(I.getOperand(0)); - unsigned Op1Reg = getReg(I.getOperand(1)); + unsigned Reg = Regs[Class]; + unsigned Clobber = Clobbers[Class]; + unsigned Op0Reg = getReg(I.getOperand(0)); + unsigned Op1Reg = getReg(I.getOperand(1)); // Put the first operand into one of the A registers... BuildMI(BB, MovOpcode[Class], 1, Reg).addReg(Op0Reg); - // Emit the appropriate multiple instruction... - // FIXME: We need to mark that this modified AH, DX, or EDX also!! - BuildMI(BB, MulOpcode[Class], 2, Reg).addReg(Reg).addReg(Op1Reg); + // Emit the appropriate multiply instruction... + BuildMI(BB, MulOpcode[Class], 4) + .addReg(Reg, UseAndDef).addReg(Op1Reg).addClobber(Clobber); // Put the result into the destination register... BuildMI(BB, MovOpcode[Class], 1, getReg(I)).addReg(Reg); } + /// visitDivRem - Handle division and remainder instructions... these /// instruction both require the same instructions to be generated, they just /// select the result from a different register. Note that both of these @@ -489,17 +497,18 @@ BuildMI(BB, ClrOpcode[Class], 2, ExtReg).addReg(ExtReg).addReg(ExtReg); } + // Emit the appropriate divide or remainder instruction... + BuildMI(BB, DivOpcode[isSigned][Class], 2) + .addReg(Reg, UseAndDef).addReg(ExtReg, UseAndDef).addReg(Op1Reg); + // Figure out which register we want to pick the result out of... unsigned DestReg = (I.getOpcode() == Instruction::Div) ? Reg : ExtReg; - // Emit the appropriate divide or remainder instruction... - // FIXME: We need to mark that this modified AH, DX, or EDX also!! - BuildMI(BB,DivOpcode[isSigned][Class], 2, DestReg).addReg(Reg).addReg(Op1Reg); - // Put the result into the destination register... BuildMI(BB, MovOpcode[Class], 1, getReg(I)).addReg(DestReg); } + /// Shift instructions: 'shl', 'sar', 'shr' - Some special cases here /// for constant immediate shift values, and for constant immediate /// shift values equal to 1. Even the general case is sort of special, @@ -561,6 +570,7 @@ } } + /// visitLoadInst - Implement LLVM load instructions in terms of the x86 'mov' /// instruction. /// @@ -574,6 +584,7 @@ unsigned AddressReg = getReg(I.getOperand(0)); addDirectMem(BuildMI(BB, Opcode[Class], 4, getReg(I)), AddressReg); } + /// visitStoreInst - Implement LLVM store instructions in terms of the x86 'mov' /// instruction. From lattner at cs.uiuc.edu Sun Nov 17 16:15:01 2002 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Sun Nov 17 16:15:01 2002 Subject: [llvm-commits] CVS: llvm/lib/CodeGen/MachineInstr.cpp Message-ID: <200211172214.QAA18029@apoc.cs.uiuc.edu> Changes in directory llvm/lib/CodeGen: MachineInstr.cpp updated: 1.63 -> 1.64 --- Log message: Remove only uses of markDef/markDefAndUse methods --- Diffs of the changes: Index: llvm/lib/CodeGen/MachineInstr.cpp diff -u llvm/lib/CodeGen/MachineInstr.cpp:1.63 llvm/lib/CodeGen/MachineInstr.cpp:1.64 --- llvm/lib/CodeGen/MachineInstr.cpp:1.63 Tue Oct 29 20:02:37 2002 +++ llvm/lib/CodeGen/MachineInstr.cpp Sun Nov 17 16:14:08 2002 @@ -98,12 +98,13 @@ operands[i].opType = opType; operands[i].value = V; operands[i].regNum = -1; - operands[i].flags = 0; - if (isdef || TargetInstrDescriptors[opCode].resultPos == (int) i) - operands[i].markDef(); if (isDefAndUse) - operands[i].markDefAndUse(); + operands[i].flags = MachineOperand::DEFUSEFLAG; + else if (isdef || TargetInstrDescriptors[opCode].resultPos == (int) i) + operands[i].flags = MachineOperand::DEFFLAG; + else + operands[i].flags = 0; } void @@ -131,10 +132,12 @@ operands[i].opType = MachineOperand::MO_MachineRegister; operands[i].value = NULL; operands[i].regNum = regNum; - operands[i].flags = 0; if (isdef || TargetInstrDescriptors[opCode].resultPos == (int) i) - operands[i].markDef(); + operands[i].flags = MachineOperand::DEFFLAG; + else + operands[i].flags = 0; + insertUsedReg(regNum); } From lattner at cs.uiuc.edu Sun Nov 17 16:15:05 2002 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Sun Nov 17 16:15:05 2002 Subject: [llvm-commits] CVS: llvm/include/llvm/CodeGen/MachineInstr.h Message-ID: <200211172214.QAA18040@apoc.cs.uiuc.edu> Changes in directory llvm/include/llvm/CodeGen: MachineInstr.h updated: 1.85 -> 1.86 --- Log message: Remove unused methods --- Diffs of the changes: Index: llvm/include/llvm/CodeGen/MachineInstr.h diff -u llvm/include/llvm/CodeGen/MachineInstr.h:1.85 llvm/include/llvm/CodeGen/MachineInstr.h:1.86 --- llvm/include/llvm/CodeGen/MachineInstr.h:1.85 Sun Nov 17 15:56:10 2002 +++ llvm/include/llvm/CodeGen/MachineInstr.h Sun Nov 17 16:14:22 2002 @@ -197,8 +197,6 @@ // Construction methods needed for fine-grain control. // These must be accessed via coresponding methods in MachineInstr. - void markDef() { flags |= DEFFLAG; } - void markDefAndUse() { flags |= DEFUSEFLAG; } void markHi32() { flags |= HIFLAG32; } void markLo32() { flags |= LOFLAG32; } void markHi64() { flags |= HIFLAG64; } From lattner at cs.uiuc.edu Sun Nov 17 16:16:00 2002 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Sun Nov 17 16:16:00 2002 Subject: [llvm-commits] CVS: llvm/lib/Analysis/InstCount.cpp Message-ID: <200211172215.QAA18055@apoc.cs.uiuc.edu> Changes in directory llvm/lib/Analysis: InstCount.cpp updated: 1.1 -> 1.2 --- Log message: Count CallInsts correctly, remove unneccesary initializers S: ---------------------------------------------------------------------- --- Diffs of the changes: Index: llvm/lib/Analysis/InstCount.cpp diff -u llvm/lib/Analysis/InstCount.cpp:1.1 llvm/lib/Analysis/InstCount.cpp:1.2 --- llvm/lib/Analysis/InstCount.cpp:1.1 Wed Nov 13 12:22:13 2002 +++ llvm/lib/Analysis/InstCount.cpp Sun Nov 17 16:15:40 2002 @@ -74,7 +74,7 @@ inline void visitBranchInst(BranchInst &I) { NumBranchInst++; } inline void visitPHINode(PHINode &I) { NumPHINode++; } inline void visitCastInst (CastInst &I) { NumCastInst++; } - inline void visitCallInst (CallInst &I) { NumCastInst++; } + inline void visitCallInst (CallInst &I) { NumCallInst++; } inline void visitMallocInst(MallocInst &I) { NumMallocInst++; } inline void visitAllocaInst(AllocaInst &I) { NumAllocaInst++; } inline void visitFreeInst (FreeInst &I) { NumFreeInst++; } @@ -95,8 +95,8 @@ } }; - RegisterOpt X("instcount", - "Counts the various types of Instructions"); + RegisterAnalysis X("instcount", + "Counts the various types of Instructions"); } @@ -108,40 +108,6 @@ // function. // bool InstCount::run(Module &M) { - /* Initialization */ - NumReturnInst = 0; - NumBranchInst = 0; - NumPHINode = 0; - NumCastInst = 0; - NumCallInst = 0; - NumMallocInst = 0; - NumAllocaInst = 0; - NumFreeInst = 0; - NumLoadInst = 0; - NumStoreInst = 0; - NumGetElementPtrInst = 0; - NumSwitchInst = 0; - NumInvokeInst = 0; - NumBinaryOperator = 0; - NumShiftInst = 0; - NumShlInst = 0; - NumShrInst = 0; - NumAddInst = 0; - NumSubInst = 0; - NumMulInst = 0; - NumDivInst = 0; - NumRemInst = 0; - NumAndInst = 0; - NumOrInst = 0; - NumXorInst = 0; - NumSetCondInst = 0; - NumSetEQInst = 0; - NumSetNEInst = 0; - NumSetLEInst = 0; - NumSetGEInst = 0; - NumSetLTInst = 0; - NumSetGTInst = 0; - for (Module::iterator mI = M.begin(), mE = M.end(); mI != mE; ++mI) for (inst_iterator I = inst_begin(*mI), E = inst_end(*mI); I != E; ++I) visit(*I); From lattner at cs.uiuc.edu Sun Nov 17 16:17:01 2002 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Sun Nov 17 16:17:01 2002 Subject: [llvm-commits] CVS: llvm/lib/Analysis/DataStructure/BottomUpClosure.cpp Message-ID: <200211172216.QAA18073@apoc.cs.uiuc.edu> Changes in directory llvm/lib/Analysis/DataStructure: BottomUpClosure.cpp updated: 1.44 -> 1.45 --- Log message: Add MaxSCC statistics --- Diffs of the changes: Index: llvm/lib/Analysis/DataStructure/BottomUpClosure.cpp diff -u llvm/lib/Analysis/DataStructure/BottomUpClosure.cpp:1.44 llvm/lib/Analysis/DataStructure/BottomUpClosure.cpp:1.45 --- llvm/lib/Analysis/DataStructure/BottomUpClosure.cpp:1.44 Tue Nov 12 09:58:08 2002 +++ llvm/lib/Analysis/DataStructure/BottomUpClosure.cpp Sun Nov 17 16:16:28 2002 @@ -13,8 +13,12 @@ #include "Support/Statistic.h" using std::map; -static RegisterAnalysis -X("budatastructure", "Bottom-up Data Structure Analysis Closure"); +namespace { + Statistic<> MaxSCC("budatastructure", "Maximum SCC Size in Call Graph"); + + RegisterAnalysis + X("budatastructure", "Bottom-up Data Structure Analysis Closure"); +} using namespace DS; @@ -112,9 +116,11 @@ // Calculate the graphs for any functions that are unreachable from main... for (Module::iterator I = M.begin(), E = M.end(); I != E; ++I) if (!I->isExternal() && DSInfo.find(I) == DSInfo.end()) { +#ifndef NDEBUG if (MainFunc) std::cerr << "*** Function unreachable from main: " << I->getName() << "\n"; +#endif calculateReachableGraphs(I); // Calculate all graphs... } return false; @@ -186,6 +192,8 @@ Stack.pop_back(); DSGraph &G = calculateGraph(*F); + if (MaxSCC < 1) MaxSCC = 1; + // Should we revisit the graph? if (CallSiteIterator::begin(G) != CallSiteIterator::end(G)) { ValMap.erase(F); @@ -211,6 +219,10 @@ std::cerr << "Identified SCC #: " << MyID << " of size: " << (Stack.end()-FirstInSCC) << "\n"; + // Compute the Max SCC Size... + if (MaxSCC < unsigned(Stack.end()-FirstInSCC)) + MaxSCC = Stack.end()-FirstInSCC; + std::vector::iterator I = Stack.end(); do { --I; @@ -325,10 +337,20 @@ DEBUG(std::cerr << " Inlining graph for " << Callee->getName() << " in: " << F.getName() << "[" << GI.getGraphSize() << "+" << GI.getAuxFunctionCalls().size() << "]\n"); + +#if 0 + Graph.writeGraphToFile(std::cerr, "bu_" + F.getName() + "_before_" + + Callee->getName()); +#endif // Handle self recursion by resolving the arguments and return value Graph.mergeInGraph(CS, GI, DSGraph::StripAllocaBit | DSGraph::DontCloneCallNodes); + +#if 0 + Graph.writeGraphToFile(std::cerr, "bu_" + F.getName() + "_after_" + + Callee->getName()); +#endif } } @@ -400,7 +422,7 @@ DEBUG(std::cerr << " Inlining graph for " << Callee->getName() << " in: " << F.getName() << "[" << GI.getGraphSize() << "+" << GI.getAuxFunctionCalls().size() << "]\n"); - + // Handle self recursion by resolving the arguments and return value Graph.mergeInGraph(CS, GI, DSGraph::StripAllocaBit | DSGraph::DontCloneCallNodes); @@ -423,8 +445,6 @@ << Graph.getGraphSize() << "+" << Graph.getAuxFunctionCalls().size() << "]\n"); - //Graph.writeGraphToFile(std::cerr, "bu_" + F.getName()); - return Graph; } @@ -518,7 +538,6 @@ DEBUG(std::cerr << " [BU] Done inlining: " << F.getName() << " [" << Graph.getGraphSize() << "+" << Graph.getAuxFunctionCalls().size() << "]\n"); - //Graph.writeGraphToFile(std::cerr, "bu_" + F.getName()); return Graph; From lattner at cs.uiuc.edu Sun Nov 17 16:18:01 2002 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Sun Nov 17 16:18:01 2002 Subject: [llvm-commits] CVS: llvm/lib/Analysis/DataStructure/DataStructureStats.cpp Message-ID: <200211172217.QAA18084@apoc.cs.uiuc.edu> Changes in directory llvm/lib/Analysis/DataStructure: DataStructureStats.cpp updated: 1.1 -> 1.2 --- Log message: Add hack to only consider indirect calls indirect if they do more than cast their source function --- Diffs of the changes: Index: llvm/lib/Analysis/DataStructure/DataStructureStats.cpp diff -u llvm/lib/Analysis/DataStructure/DataStructureStats.cpp:1.1 llvm/lib/Analysis/DataStructure/DataStructureStats.cpp:1.2 --- llvm/lib/Analysis/DataStructure/DataStructureStats.cpp:1.1 Wed Nov 13 09:41:00 2002 +++ llvm/lib/Analysis/DataStructure/DataStructureStats.cpp Sun Nov 17 16:17:12 2002 @@ -11,7 +11,7 @@ #include namespace { - Statistic TotalNumCallees("totalcallees", + Statistic<> TotalNumCallees("totalcallees", "Total number of callee functions at all indirect call sites"); Statistic<> NumIndirectCalls("numindirect", "Total number of indirect call sites in the program"); @@ -39,6 +39,14 @@ static RegisterAnalysis Z("dsstats", "DS Graph Statistics"); } +static bool isIndirectCallee(Value *V) { + if (isa(V)) return false; + + if (CastInst *CI = dyn_cast(V)) + return isIndirectCallee(CI->getOperand(0)); + return true; +} + void DSGraphStats::countCallees(const Function& F, const DSGraph& tdGraph) @@ -47,7 +55,7 @@ const std::vector& callSites = tdGraph.getFunctionCalls(); for (unsigned i=0, N = callSites.size(); i < N; ++i) - if (callSites[i].getCallInst().getCalledFunction() == NULL) + if (isIndirectCallee(callSites[i].getCallInst().getCalledValue())) { // This is an indirect function call std::vector Callees = callSites[i].getCallee().getNode()->getGlobals(); @@ -66,10 +74,10 @@ TotalNumCallees += totalNumCallees; NumIndirectCalls += numIndirectCalls; - std::cout << " In function " << F.getName() << " : " - << (double) (numIndirectCalls == 0? 0.0 - : (totalNumCallees / (double) numIndirectCalls)) - << " avg. callees per indirect call\n"; + if (numIndirectCalls) + std::cout << " In function " << F.getName() << ": " + << (totalNumCallees / (double) numIndirectCalls) + << " average callees per indirect call\n"; } From lattner at cs.uiuc.edu Sun Nov 17 16:19:01 2002 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Sun Nov 17 16:19:01 2002 Subject: [llvm-commits] CVS: llvm/test/DSGraphs/htmlcoldiff.pl Message-ID: <200211172218.QAA18107@apoc.cs.uiuc.edu> Changes in directory llvm/test/DSGraphs: htmlcoldiff.pl updated: 1.2 -> 1.3 --- Log message: Reduce threshold to print change --- Diffs of the changes: Index: llvm/test/DSGraphs/htmlcoldiff.pl diff -u llvm/test/DSGraphs/htmlcoldiff.pl:1.2 llvm/test/DSGraphs/htmlcoldiff.pl:1.3 --- llvm/test/DSGraphs/htmlcoldiff.pl:1.2 Sun Nov 10 01:31:02 2002 +++ llvm/test/DSGraphs/htmlcoldiff.pl Sun Nov 17 16:18:46 2002 @@ -48,7 +48,7 @@ $Field != 0) { # Handle floating point numbers special # They are only highlighted if they change by 20% or more... my $Change = $FieldComp/$Field; - $Hilight = 1 if ($Change > 2 || $Change < 0.5); + $Hilight = 1 if ($Change > 1.3333 || $Change < 0.666); } elsif ($Field ne $FieldComp) { $Hilight = 1; From lattner at cs.uiuc.edu Sun Nov 17 16:19:05 2002 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Sun Nov 17 16:19:05 2002 Subject: [llvm-commits] CVS: llvm/test/DSGraphs/Makefile.DSGraphs Message-ID: <200211172218.QAA18112@apoc.cs.uiuc.edu> Changes in directory llvm/test/DSGraphs: Makefile.DSGraphs updated: 1.9 -> 1.10 --- Log message: minor tweak --- Diffs of the changes: Index: llvm/test/DSGraphs/Makefile.DSGraphs diff -u llvm/test/DSGraphs/Makefile.DSGraphs:1.9 llvm/test/DSGraphs/Makefile.DSGraphs:1.10 --- llvm/test/DSGraphs/Makefile.DSGraphs:1.9 Fri Nov 8 15:29:01 2002 +++ llvm/test/DSGraphs/Makefile.DSGraphs Sun Nov 17 16:18:17 2002 @@ -1,4 +1,4 @@ -## $Id: Makefile.DSGraphs,v 1.9 2002/11/08 21:29:01 lattner Exp $ +## $Id: Makefile.DSGraphs,v 1.10 2002/11/17 22:18:17 lattner Exp $ ##---------------------------------------------------------------------------- ## Common makefile rules for testing DSGraph analysis. ## @@ -45,10 +45,10 @@ ANALYZE_OPTS = -stats -time-passes -only-print-main-ds report.out.txt: $(LIB_LINKED) $(LANALYZE) - @echo "---------------------------------------------------------------" - @echo ">>> ========= " $< - @echo "---------------------------------------------------------------" - -time -p $(LANALYZE) -$(PASS)datastructure $(ANALYZE_OPTS) $< > $@ 2>&1 + -time -p $(LANALYZE) -$(PASS)datastructure $(ANALYZE_OPTS) -dsstats -instcount $< > $@ 2>&1 recursive_reports: report.out.txt - cat report.out.txt \ No newline at end of file + @echo "---------------------------------------------------------------" + @echo ">>> ========= " $(LIB_LINKED) + @echo "---------------------------------------------------------------" + cat report.out.txt From lattner at cs.uiuc.edu Sun Nov 17 16:20:01 2002 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Sun Nov 17 16:20:01 2002 Subject: [llvm-commits] CVS: llvm/test/DSGraphs/generate_report.pl Message-ID: <200211172219.QAA18129@apoc.cs.uiuc.edu> Changes in directory llvm/test/DSGraphs: generate_report.pl updated: 1.8 -> 1.9 --- Log message: lots o changes --- Diffs of the changes: Index: llvm/test/DSGraphs/generate_report.pl diff -u llvm/test/DSGraphs/generate_report.pl:1.8 llvm/test/DSGraphs/generate_report.pl:1.9 --- llvm/test/DSGraphs/generate_report.pl:1.8 Sun Nov 10 01:31:18 2002 +++ llvm/test/DSGraphs/generate_report.pl Sun Nov 17 16:18:29 2002 @@ -36,23 +36,23 @@ # Output the headers for the report.... -printf("%-25s ", "Name:"); +printf("%-20s ", "Name:"); if ($SHOW_TIMES) { - printf("%6s %-8s %-8s %-8s %-8s %-8s ", - "Anlyz:", "LocTime:", "BUTime:", "TDTime:", "TotTime:", "BCTime:"); + printf("%6s %-6s %-6s %-6s %-8s %-8s ", + "Anlyz:", "LocTm:", "BUTim:", "TDTim:", "TimeSum:", "BCTime:"); } -printf("%-8s %-8s %-8s %-8s %-8s " . "%-8s %-10s %-6s %-6s %-6s\n", - "LocSize:", "BUSize:", "TDSize:", "TotSize:", "BCSize:", - "NumFold", "NumNodes", "main", "__main", "GlobGr"); +printf("%-8s %-8s %-8s %-8s %-8s ", + "LocSize:", "BUSize:", "TDSize:", "BUTDSz:", "BCSize:"); +printf("%-8s %-10s %-6s %-6s %-6s " . "| %-5s %-5s %-5s %-5s %-5s %-5s" . + " | %7s %9s %5s\n", + "NumFold", "NumNodes", "MaxSz", "GlobGr", "MaxSCC", + "Loads", "Store", "Calls", "Allca", "Mallc", "Sum", + "num/ind", "indcallee", "ratio"); foreach $Record (@Records) { # Print BM name - printField('([-a-zA-Z0-9.]+)\.bc', $Record, -25); - - if ($SHOW_TIMES) { # Print total elapsed time... - printField('real\s+([ms0-9.]+)', $Record, 6); - } + printField('([-a-zA-Z0-9.]+)\.lib\.bc', $Record, -20); if ($Record =~ m/Assertion/) { # If an assertion failure occured, print it out. @@ -60,31 +60,48 @@ } else { if ($SHOW_TIMES) { # Print Times - printField('([0-9.]+) \([^)]+\)[ ]*[0-9]+ Local', $Record, -8); - printField('([0-9.]+) \([^)]+\)[ ]*[0-9]+ Bottom-up', $Record, -8); - printField('([0-9.]+) \([^)]+\)[ ]*[0-9]+ Top-down', $Record, -8); - printField('([0-9.]+) \([^)]+\)[ ]*[0-9]+ TOTAL', $Record, -8); + my $B = printField('([0-9.]+) \([^)]+\)[ 0-9]+Bottom', $Record, -6); + my $L = printField('([0-9.]+) \([^)]+\)[ 0-9]+Local' , $Record, -6); + printField('([0-9.]+) \([^)]+\)[ 0-9]+Bottom', $Record, -6); + my $T = printField('([0-9.]+) \([^)]+\)[ 0-9]+Top' , $Record, -6); + printf("%-8s ", $L+$B+$T); printField('([0-9.]+) \([^)]+\)[ ]*[0-9]+ Bytecode', $Record, -8); print "| "; } # Print Sizes printField("([0-9]+) Local", $Record, -8); - printField("([0-9]+) Bottom-up", $Record, -8); - printField("([0-9]+) Top-down", $Record, -8); - printField("([0-9]+) TOTAL", $Record, -8); + my $B = printField("([0-9]+) Bottom-up", $Record, -8); + my $T = printField("([0-9]+) Top-down", $Record, -8); + printf("%-8s ", $B+$T); printField("([0-9]+) Bytecode", $Record, -8); print "| "; - printField("([0-9]+).*completely folded", $Record, -5); + printField("([0-9]+).*Number of folded nodes ", $Record, -5); printField("Graphs contain \\[([0-9+]+)\\] nodes total", $Record, -10); - printField("\\.main\\.dot'... \\[([0-9+]+)\\]", $Record, -6); - printField("\\.__main\\.dot'... \\[([0-9+]+)\\]", $Record, -6); + printField("([0-9]+).*Maximum graph size", $Record, -6); printField("\\.GlobalsGraph\\.dot'... \\[([0-9+]+)\\]", $Record, -6); + printField("([0-9]+).*Maximum SCC Size in Call Graph", $Record, -6); + + print "| "; + my $I = printField("([0-9]+).*Number of LoadInsts", $Record, -5); + $I += printField("([0-9]+).*Number of StoreInsts", $Record, -5); + $I += printField("([0-9]+).*Number of CallInsts", $Record, -5); + $I += printField("([0-9]+).*Number of AllocaInsts", $Record, -5); + $I += printField("([0-9]+).*Number of MallocInsts", $Record, -5); + printf("%-5s ", $I); + + print "| "; + my $NI = printField("([0-9]+).*number of indirect call sites", $Record, -7); + my $NC = printField("([0-9]+).*number of callee functions at", $Record, -9); + if ($NI != 0) { + printf("%-5s ", $NC/$NI); + } else { + printf("%-5s ", "n/a"); + } + } print "\n"; - #print "#####\n"; - #print $Record; } sub printField { @@ -93,7 +110,9 @@ $Record =~ m/$Regex/; if (!defined($1)) { printf("%${FieldWidth}s ", "*"); + return "0"; } else { printf("%${FieldWidth}s ", $1); } + return $1; } From lattner at cs.uiuc.edu Sun Nov 17 16:20:05 2002 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Sun Nov 17 16:20:05 2002 Subject: [llvm-commits] CVS: llvm/www/docs/DSGraphStatus.html Message-ID: <200211172219.QAA18142@apoc.cs.uiuc.edu> Changes in directory llvm/www/docs: DSGraphStatus.html updated: 1.13 -> 1.14 --- Log message: Add more numbers --- Diffs of the changes: Index: llvm/www/docs/DSGraphStatus.html diff -u llvm/www/docs/DSGraphStatus.html:1.13 llvm/www/docs/DSGraphStatus.html:1.14 --- llvm/www/docs/DSGraphStatus.html:1.13 Tue Nov 12 10:06:51 2002 +++ llvm/www/docs/DSGraphStatus.html Sun Nov 17 16:19:10 2002 @@ -13,6 +13,175 @@ their previous value.

+

Nov 14, 2002:

+ +Some fine tuning happened here. The DSNode object was shrunk by a little bit, +lowering memory consumption. The type merging code now ignores access to +structure fields when checking compatibility, reducing node collapses and +increasing memory consumption in some cases. This table also includes data for +the number of indirect call sites, and the number of indirect call targets. The +final column is the average number of call targets per indirect call site.

+ +

+Name:                Anlyz: LocTm: BUTim: TDTim: TimeSum: BCTime:      LocSize: BUSize:  TDSize:  BUTDSz:  BCSize:    NumFold  NumNodes   MaxSz  GlobGr MaxSCC | Loads Store Calls Allca Mallc Sum   | num/ind indcallee ratio
+254.gap              0.6627 0.1810 0.6627 0.4697 1.3134   0.6080   |   2024800  2822584  2018424  4841008  16585864 |    2076  24032+3948 268    0+0    20     | 18420 3888  5805  87    3     28203 | 11      11        1     
+255.vortex           0.3589 0.1648 0.3589 0.6751 1.1988   0.4810   |   1381200  1259752  2001576  3261328  11694840 |    1038  7343+2842  166    0+0    38     | 13901 6136  6829  1420  2     28288 | 6       95        15.8333
+300.twolf            0.0690 0.0663 0.0690 0.1151 0.2504   0.2424   |   466600   392384   400272   792656   7054760  |    95    4144+784   215    0+0    1      | 11246 2911  1865  114   3     16139 | 269     269       1     
+197.parser           0.0481 0.0305 0.0481 0.0479 0.1265   0.1291   |   281184   225008   212296   437304   4409632  |    338   2257+707   97     0+0    3      | 2611  908   1651  25    2     5197  | 2       4         2     
+burg.llvm            0.0265 0.0218 0.0265 0.0389 0.0872   0.1565   |   536960   477848   188472   666320   2997272  |    213   2309+575   98     0+0    2      | 2265  363   1128  44    4     3804  | 8       24        3     
+ptrdist-bc           0.0107 0.0079 0.0107 0.0116 0.0302   0.0354   |   198640   269032   91248    360280   1332992  |    62    680+199    42     0+0    1      | 764   411   425   21    25    1646  | 3       3         1     
+ptrdist-yacr2        0.0100 0.0073 0.0100 0.0078 0.0251   0.0212   |   176112   193048   72296    265344   982896   |    *     1036+90    53     0+0    1      | 872   174   289   16    27    1378  | *       *         n/a   
+164.gzip.llvm        0.0062 0.0094 0.0062 0.0070 0.0226   0.1029   |   201568   129000   70880    199880   1873760  |    8     971+87     67     0+0    1      | 1014  622   351   19    3     2009  | 9       9         1     
+optimizer-eval.llvm  0.0060 0.0034 0.0060 0.0344 0.0438   0.0145   |   100008   78968    61784    140752   626688   |    *     309+41     72     0+0    1      | 278   405   108   32    *     823   | 2       174       87    
+181.mcf              0.0050 0.0040 0.0050 0.0055 0.0145   0.0195   |   130984   120848   43208    164056   579064   |    46    376+52     83     0+0    1      | 362   225   81    8     2     678   | *       *         n/a   
+voronoi.llvm         0.0037 0.0028 0.0037 0.0054 0.0119   0.0098   |   63768    82584    48808    131392   413304   |    3     307+77     58     0+0    1      | 399   171   121   44    4     739   | *       *         n/a   
+256.bzip2            0.0030 0.0060 0.0030 0.0025 0.0115   0.0907   |   138536   83624    39760    123384   1363416  |    *     563+37     59     0+0    1      | 698   307   287   18    10    1320  | 2       2         1     
+sgefa.llvm           0.0028 0.0019 0.0028 0.0029 0.0076   0.0080   |   85680    81992    67056    149048   372736   |    *     130+24     36     0+0    1      | 159   65    77    5     5     311   | 1       1         1     
+sim.llvm             0.0022 0.0032 0.0022 0.0026 0.008    0.0193   |   54952    81152    21976    103128   737584   |    *     261+36     60     0+0    1      | 687   305   75    2     21    1090  | *       *         n/a   
+bh.llvm              0.0021 0.0025 0.0021 0.0019 0.0065   0.0113   |   75656    51520    27768    79288    470680   |    38    194+35     23     0+0    1      | 266   189   151   36    3     645   | 2       2         1     
+ptrdist-ft           0.0019 0.0020 0.0019 0.0021 0.006    0.0115   |   46336    58552    15464    74016    502704   |    *     192+42     19     0+0    1      | 147   80    96    1     5     329   | 6       6         1     
+ptrdist-ks           0.0017 0.0028 0.0017 0.0017 0.0062   0.0089   |   48792    44664    31304    75968    381528   |    *     215+30     36     0+0    1      | 155   87    88    2     6     338   | *       *         n/a   
+ptrdist-anagram      0.0014 0.0017 0.0014 0.0012 0.0043   0.0079   |   43400    41992    14864    56856    409312   |    5     196+28     20     0+0    1      | 105   77    60    5     3     250   | 3       3         1     
+em3d.llvm            0.0013 0.0012 0.0013 0.0010 0.0035   0.0056   |   24256    43304    13024    56328    223952   |    1     178+28     21     0+0    1      | 114   41    71    *     12    238   | 3       8         2.66666
+health.llvm          0.0012 0.0010 0.0012 0.0013 0.0035   0.0070   |   32064    31992    12720    44712    202312   |    3     97+31      13     0+0    1      | 85    72    47    5     3     212   | *       *         n/a   
+lists.llvm           0.0010 0.0008 0.0010 0.0015 0.0033   0.0033   |   24968    22808    6640     29448    139832   |    *     67+26      28     0+0    1      | 40    31    53    *     3     127   | *       *         n/a   
+mst.llvm             0.0008 0.0008 0.0008 0.0007 0.0023   0.0044   |   18944    15584    16680    32264    183080   |    4     97+15      13     0+0    1      | 55    36    42    5     5     143   | 2       2         1     
+hash.llvm            0.0008 0.0006 0.0008 0.0008 0.0022   0.0035   |   17504    26464    8208     34672    150160   |    *     117+17     19     0+0    1      | 35    25    25    1     4     90    | *       *         n/a   
+tsp.llvm             0.0007 0.0009 0.0007 0.0005 0.0021   0.0042   |   18416    15024    5408     20432    183312   |    *     42+15      7      0+0    1      | 54    61    64    *     1     180   | *       *         n/a   
+power.llvm           0.0007 0.0008 0.0007 0.0007 0.0022   0.0050   |   19704    18880    18120    37000    212104   |    *     81+18      11     0+0    1      | 141   86    46    11    4     288   | *       *         n/a   
+perimeter.llvm       0.0007 0.0006 0.0007 0.0004 0.0017   0.0035   |   14944    13072    3936     17008    155240   |    *     35+15      7      0+0    1      | 30    25    49    *     1     105   | *       *         n/a   
+bisort.llvm          0.0005 0.0006 0.0005 0.0003 0.0014   0.0032   |   13480    11608    3704     15312    124416   |    *     35+13      7      0+0    1      | 37    24    40    *     1     102   | *       *         n/a   
+objinst.llvm         0.0004 0.0004 0.0004 0.0005 0.0013   0.0028   |   11360    11008    12288    23296    86552    |    7     53+14      19     0+0    1      | 18    11    19    *     2     50    | *       *         n/a   
+methcall.llvm        0.0004 0.0004 0.0004 0.0006 0.0014   0.0026   |   10280    9816     9128     18944    86632    |    17    45+12      15     0+0    1      | 18    11    16    *     2     47    | 1       3         3     
+treeadd.llvm         0.0003 0.0003 0.0003 0.0002 0.0008   0.0019   |   8712     7568     2216     9784     70776    |    *     25+7       7      0+0    1      | 15    6     18    *     1     40    | *       *         n/a   
+matrix.llvm          0.0003 0.0003 0.0003 0.0003 0.0009   0.0019   |   3840     15744    3064     18808    69184    |    *     38+9       12     0+0    1      | 21    4     11    *     2     38    | *       *         n/a   
+llubenchmark.llvm    0.0003 0.0005 0.0003 0.0003 0.0011   0.0028   |   11016    9448     2616     12064    123384   |    *     31+7       15     0+0    1      | 29    9     26    *     2     66    | *       *         n/a   
+ary3.llvm            0.0003 0.0003 0.0003 0.0002 0.0008   0.0018   |   8832     12584    3008     15592    71432    |    4     44+5       17     0+0    1      | 10    14    7     *     1     32    | *       *         n/a   
+sumarraymalloc.llvm  0.0002 0.0005 0.0002 0.0002 0.0009   0.0016   |   7032     2680     2064     4744     54544    |    *     23+5       7      0+0    1      | 8     2     8     *     1     19    | *       *         n/a   
+sieve.llvm           0.0002 0.0002 0.0002 0.0006 0.001    0.0032   |   5704     1944     1616     3560     216328   |    *     22+2       12     0+0    1      | 7     3     4     *     *     14    | *       *         n/a   
+random.llvm          0.0002 0.0002 0.0002 0.0001 0.0005   0.0014   |   2056     7176     1312     8488     46680    |    *     15+2       7      0+0    1      | 8     2     6     *     *     16    | *       *         n/a   
+heapsort.llvm        0.0002 0.0003 0.0002 0.0001 0.0006   0.0016   |   2856     6976     1992     8968     63368    |    *     26+3       7      0+0    1      | 14    7     6     *     1     28    | *       *         n/a   
+fib2.llvm            0.0002 0.0002 0.0002 0.0001 0.0005   0.0014   |   5744     6168     1632     7800     42448    |    *     21+5       8      0+0    1      | 6     1     7     *     *     14    | *       *         n/a   
+ackermann.llvm       0.0002 0.0002 0.0002 0.0001 0.0005   0.0013   |   1744     1536     1192     2728     47528    |    *     13+2       7      0+0    1      | 6     1     6     *     *     13    | *       *         n/a   
+sumarray.llvm        0.0001 0.0001 0.0001 0.0000 0.0002   0.0007   |   912      624      632      1256     15112    |    *     6+1        4      0+0    1      | 1     3     2     *     1     7     | *       *         n/a   
+sumarray2d.llvm      0.0001 0.0001 0.0001 0.0001 0.0003   0.0009   |   1576     3656     848      4504     22544    |    *     10+1       7      0+0    1      | 1     2     3     1     *     7     | *       *         n/a   
+printargs.llvm       0.0001 0.0001 0.0001 0.0001 0.0003   0.0007   |   3712     1048     704      1752     19104    |    *     6+1        4      0+0    1      | 4     *     5     *     *     9     | *       *         n/a   
+pi.llvm              0.0001 0.0002 0.0001 0.0001 0.0004   0.0011   |   2368     4720     4736     9456     35208    |    *     17+2       13     0+0    1      | 7     3     7     2     *     19    | *       *         n/a   
+matrixTranspose.llvm 0.0001 0.0002 0.0001 0.0001 0.0004   0.0013   |   1392     4128     736      4864     69720    |    *     8+1        5      0+0    1      | 6     5     4     *     *     15    | *       *         n/a   
+indvars.llvm         0.0001 0.0002 0.0001 0.0001 0.0004   0.0010   |   4752     1072     1024     2096     31536    |    *     13+1       8      0+0    1      | 2     6     3     1     *     12    | *       *         n/a   
+hello.llvm           0.0000 0.0001 0.0000 0.0000 0.0001   0.0006   |   752      472      472      944      14112    |    *     2+0        2      0+0    1      | 3     *     4     *     *     7     | *       *         n/a   
+

+ +

+

Nov 13, 2002:

+ +New numbers, same as last time, just some extra columns on the end:

+ +This data set also includes new data for the ptrdist benchmark.

+ +

+Name:                Anlyz: LocTime: BUTime:  TDTime:  TimeSum: BCTime:      LocSize: BUSize:  TDSize:  BUTDSz:  BCSize:    NumFold  NumNodes   MaxSz  GlobGr MaxSCC | Loads Store Calls Allca Mallc Sum  
+254.gap                4.39 0.1773   0.6581   0.4703   1.3057   0.6054   |   2024952  2823064  2018920  4841984  16585864 |    2080  24032+3948 268    0+0    20     | 18420 3888  5805  87    3     28203 
+255.vortex             4.03 0.1154   0.3172   0.6416   1.0742   0.4523   |   1381344  1261232  1997512  3258744  11694840 |    1043  7331+2844  166    0+0    38     | 13901 6136  6829  1420  2     28288 
+300.twolf              0.80 0.0557   0.0593   0.1062   0.2212   0.2191   |   466544   391432   394760   786192   7054760  |    115   4127+784   215    0+0    1      | 11246 2911  1865  114   3     16139 
+197.parser             0.44 0.0302   0.0403   0.0442   0.1147   0.1204   |   280960   224800   212168   436968   4409632  |    338   2255+706   97     0+0    3      | 2611  908   1651  25    2     5197  
+burg.llvm              0.33 0.0208   0.0268   0.0356   0.0832   0.1293   |   536552   478856   185880   664736   2997272  |    205   2273+576   98     0+0    2      | 2265  363   1128  44    4     3804  
+164.gzip.llvm          0.20 0.0093   0.0062   0.0073   0.0228   0.0999   |   201568   129000   70880    199880   1873760  |    8     971+87     67     0+0    1      | 1014  622   351   19    3     2009  
+ptrdist-bc             0.12 0.0080   0.0111   0.0132   0.0323   0.0304   |   198640   269032   91232    360264   1332992  |    62    680+199    42     0+0    1      | 764   411   425   21    25    1646  
+256.bzip2              0.11 0.0057   0.0028   0.0024   0.0109   0.0462   |   138536   83624    39760    123384   1363416  |    *     563+37     59     0+0    1      | 698   307   287   18    10    1320  
+optimizer-eval.llvm    0.10 0.0033   0.0064   0.0304   0.0401   0.0133   |   100008   78968    61784    140752   626688   |    *     309+41     72     0+0    1      | 278   405   108   32    *     823   
+ptrdist-yacr2          0.09 0.0075   0.0097   0.0084   0.0256   0.0211   |   176112   193048   72296    265344   982896   |    *     1036+90    53     0+0    1      | 872   174   289   16    27    1378  
+181.mcf                0.09 0.0081   0.0051   0.0054   0.0186   0.0216   |   130816   121096   43648    164744   579064   |    44    388+51     83     0+0    1      | 362   225   81    8     2     678   
+sgefa.llvm             0.08 0.0019   0.0026   0.0029   0.0074   0.0081   |   85680    81992    67056    149048   372736   |    *     130+24     36     0+0    1      | 159   65    77    5     5     311   
+voronoi.llvm           0.06 0.0028   0.0037   0.0053   0.0118   0.0097   |   63768    82416    51856    134272   413304   |    11    299+77     58     0+0    1      | 399   171   121   44    4     739   
+sim.llvm               0.06 0.0032   0.0022   0.0025   0.0079   0.0162   |   54952    81152    21976    103128   737584   |    *     261+36     60     0+0    1      | 687   305   75    2     21    1090  
+bh.llvm                0.06 0.0025   0.0021   0.0023   0.0069   0.0116   |   75656    51520    27768    79288    470680   |    38    194+35     23     0+0    1      | 266   189   151   36    3     645   
+ptrdist-ft             0.05 0.0020   0.0019   0.0021   0.006    0.0113   |   46336    58552    15464    74016    502704   |    *     192+42     19     0+0    1      | 147   80    96    1     5     329   
+em3d.llvm              0.05 0.0012   0.0012   0.0011   0.0035   0.0056   |   24256    43304    13024    56328    223952   |    1     178+28     21     0+0    1      | 114   41    71    *     12    238   
+ptrdist-ks             0.04 0.0023   0.0016   0.0017   0.0056   0.0081   |   48792    44664    31304    75968    381528   |    *     215+30     36     0+0    1      | 155   87    88    2     6     338   
+ptrdist-anagram        0.04 0.0016   0.0014   0.0025   0.0055   0.0079   |   43400    41992    14864    56856    409312   |    5     196+28     20     0+0    1      | 105   77    60    5     3     250   
+mst.llvm               0.04 0.0008   0.0007   0.0007   0.0022   0.0044   |   18944    15584    16680    32264    183080   |    4     97+15      13     0+0    1      | 55    36    42    5     5     143   
+health.llvm            0.04 0.0010   0.0012   0.0017   0.0039   0.0070   |   32064    31992    12720    44712    202312   |    3     97+31      13     0+0    1      | 85    72    47    5     3     212   
+tsp.llvm               0.03 0.0009   0.0006   0.0005   0.002    0.0041   |   18416    14504    4872     19376    183312   |    9     42+15      7      0+0    1      | 54    61    64    *     1     180   
+treeadd.llvm           0.03 0.0003   0.0003   0.0002   0.0008   0.0019   |   8712     7568     2216     9784     70776    |    *     25+7       7      0+0    1      | 15    6     18    *     1     40    
+sieve.llvm             0.03 0.0002   0.0002   0.0001   0.0005   0.0032   |   5704     1944     1616     3560     216328   |    *     22+2       12     0+0    1      | 7     3     4     *     *     14    
+power.llvm             0.03 0.0008   0.0007   0.0007   0.0022   0.0049   |   19704    18880    18120    37000    212104   |    *     81+18      11     0+0    1      | 141   86    46    11    4     288   
+pi.llvm                0.03 0.0002   0.0001   0.0001   0.0004   0.0010   |   2368     4720     4736     9456     35208    |    *     17+2       13     0+0    1      | 7     3     7     2     *     19    
+perimeter.llvm         0.03 0.0006   0.0007   0.0004   0.0017   0.0035   |   14944    13072    3936     17008    155240   |    *     35+15      7      0+0    1      | 30    25    49    *     1     105   
+objinst.llvm           0.03 0.0005   0.0005   0.0006   0.0016   0.0025   |   11360    16328    4112     20440    86552    |    19    45+14      16     0+0    1      | 18    11    19    *     2     50    
+methcall.llvm          0.03 0.0004   0.0004   0.0006   0.0014   0.0026   |   10280    9752     9040     18792    86632    |    19    43+12      14     0+0    1      | 18    11    16    *     2     47    
+matrixTranspose.llvm   0.03 0.0002   0.0001   0.0002   0.0005   0.0013   |   1392     4128     736      4864     69720    |    *     8+1        5      0+0    1      | 6     5     4     *     *     15    
+matrix.llvm            0.03 0.0003   0.0003   0.0003   0.0009   0.0019   |   3840     15744    3064     18808    69184    |    *     38+9       12     0+0    1      | 21    4     11    *     2     38    
+llubenchmark.llvm      0.03 0.0005   0.0003   0.0003   0.0011   0.0028   |   11016    9448     2616     12064    123384   |    *     31+7       15     0+0    1      | 29    9     26    *     2     66    
+lists.llvm             0.03 0.0008   0.0010   0.0014   0.0032   0.0033   |   24968    22552    6128     28680    139832   |    15    67+26      28     0+0    1      | 40    31    53    *     3     127   
+hash.llvm              0.03 0.0006   0.0008   0.0008   0.0022   0.0035   |   17504    26464    8208     34672    150160   |    *     117+17     19     0+0    1      | 35    25    25    1     4     90    
+bisort.llvm            0.03 0.0006   0.0005   0.0003   0.0014   0.0029   |   13480    11608    3704     15312    124416   |    *     35+13      7      0+0    1      | 37    24    40    *     1     102   
+ary3.llvm              0.03 0.0003   0.0003   0.0002   0.0008   0.0018   |   8832     12584    3008     15592    71432    |    4     44+5       17     0+0    1      | 10    14    7     *     1     32    
+sumarraymalloc.llvm    0.02 0.0002   0.0002   0.0002   0.0006   0.0015   |   7032     2680     2064     4744     54544    |    *     23+5       7      0+0    1      | 8     2     8     *     1     19    
+sumarray.llvm          0.02 0.0001   0.0001   0.0000   0.0002   0.0007   |   912      624      632      1256     15112    |    *     6+1        4      0+0    1      | 1     3     2     *     1     7     
+sumarray2d.llvm        0.02 0.0001   0.0001   0.0001   0.0003   0.0009   |   1576     3656     848      4504     22544    |    *     10+1       7      0+0    1      | 1     2     3     1     *     7     
+random.llvm            0.02 0.0002   0.0002   0.0001   0.0005   0.0014   |   2056     7176     1312     8488     46680    |    *     15+2       7      0+0    1      | 8     2     6     *     *     16    
+printargs.llvm         0.02 0.0001   0.0001   0.0000   0.0002   0.0008   |   3712     1048     704      1752     19104    |    *     6+1        4      0+0    1      | 4     *     5     *     *     9     
+indvars.llvm           0.02 0.0002   0.0001   0.0001   0.0004   0.0010   |   4752     1072     1024     2096     31536    |    *     13+1       8      0+0    1      | 2     6     3     1     *     12    
+heapsort.llvm          0.02 0.0002   0.0002   0.0001   0.0005   0.0017   |   2856     6976     1992     8968     63368    |    *     26+3       7      0+0    1      | 14    7     6     *     1     28    
+fib2.llvm              0.02 0.0002   0.0002   0.0001   0.0005   0.0013   |   5744     6168     1632     7800     42448    |    *     21+5       8      0+0    1      | 6     1     7     *     *     14    
+ackermann.llvm         0.02 0.0002   0.0002   0.0001   0.0005   0.0017   |   1744     1536     1192     2728     47528    |    *     13+2       7      0+0    1      | 6     1     6     *     *     13    
+hello.llvm             0.01 0.0001   0.0001   0.0000   0.0002   0.0006   |   752      472      472      944      14112    |    *     2+0        2      0+0    1      | 3     *     4     *     *     7     
+

+ +

+

Nov 12, 2002 #2:

+ +This build is the same as before, except now this is +compiled in release mode (optimizations enabled, assertions off).

+ +

+Name:                     Anlyz: LocTime: BUTime:  TDTime:  TotTime: BCTime:      LocSize: BUSize:  TDSize:  TotSize: BCSize:    NumFold  NumNodes   main   __main GlobGr
+254.gap.lib                 3.43 0.1783   0.6490   0.4676   1.7957   0.5938   |   2024904  2816256  2016824  6857984  16561248 |    5973  24033+3949 44+9   0+0    0+0    
+255.vortex.lib              3.01 0.1177   0.3156   0.6452   1.5678   0.4652   |   1381488  1260088  2000864  4642440  11691072 |    5851  7324+2837  166+11 0+0    0+0    
+300.twolf.lib               0.72 0.0547   0.0591   0.1054   0.3435   0.2076   |   466544   391448   394984   1252976  6950016  |    768   4127+784   90+53  0+0    0+0    
+197.parser.lib              0.38 0.0301   0.0400   0.0448   0.1712   0.1206   |   407728   224960   212368   964008   4442008  |    1332  2256+707   14+6   0+0    0+0    
+burg.llvm.lib               0.31 0.0207   0.0264   0.0359   0.1114   0.1493   |   535720   477752   185808   1265384  2998392  |    754   2273+576   45+7   0+0    0+0    
+164.gzip.llvm.lib           0.17 0.0089   0.0062   0.0070   0.0400   0.0977   |   201336   128072   135240   561056   1860784  |    24    971+87     8+2    0+0    0+0    
+optimizer-eval.llvm.lib     0.08 0.0033   0.0063   0.0311   0.0528   0.0131   |   101272   79216    61760    242248   624880   |    *     309+41     72+27  0+0    0+0    
+256.bzip2.lib               0.08 0.0056   0.0028   0.0024   0.0242   0.0342   |   139696   84264    39688    335984   1371144  |    *     563+37     8+2    0+0    0+0    
+181.mcf.lib                 0.07 0.0038   0.0049   0.0055   0.0345   0.0155   |   109872   142976   43664    313504   585632   |    167   388+51     22+10  0+0    0+0    
+sim.llvm.lib                0.05 0.0031   0.0023   0.0026   0.0187   0.0159   |   55880    51128    21864    225776   728104   |    *     260+35     39+22  0+0    0+0    
+voronoi.llvm.lib            0.04 0.0028   0.0037   0.0054   0.0165   0.0098   |   79696    83000    27112    203160   412912   |    18    299+77     15+8   0+0    0+0    
+hash.llvm.lib               0.04 0.0006   0.0008   0.0008   0.0045   0.0038   |   25568    23384    8184     70024    150480   |    *     117+17     14+6   0+0    0+0    
+bh.llvm.lib                 0.04 0.0025   0.0021   0.0019   0.0118   0.0114   |   75208    51032    27800    202752   482440   |    64    194+35     6+2    0+0    0+0    
+sgefa.llvm.lib              0.03 0.0019   0.0026   0.0028   0.0124   0.0085   |   85856    82224    67032    260752   375800   |    *     130+24     24+14  0+0    0+0    
+health.llvm.lib             0.03 0.0010   0.0012   0.0013   0.0077   0.0072   |   30416    30184    12704    80824    197952   |    18    97+31      12+4   0+0    0+0    
+tsp.llvm.lib                0.02 0.0009   0.0006   0.0005   0.0044   0.0044   |   18416    14448    4880     52472    183104   |    22    42+15      7+4    0+0    0+0    
+power.llvm.lib              0.02 0.0008   0.0007   0.0007   0.0049   0.0065   |   19592    27536    7848     63072    218032   |    *     81+18      11+2   0+0    0+0    
+perimeter.llvm.lib          0.02 0.0006   0.0006   0.0004   0.0039   0.0035   |   15200    14104    3944     46320    158680   |    *     35+15      7+4    0+0    0+0    
+objinst.llvm.lib            0.02 0.0004   0.0004   0.0006   0.0038   0.0026   |   11368    15280    4112     45376    90432    |    32    45+14      16+10  0+0    0+0    
+mst.llvm.lib                0.02 0.0008   0.0008   0.0007   0.0047   0.0046   |   18952    16568    7024     58032    183080   |    10    97+15      12+3   0+0    0+0    
+methcall.llvm.lib           0.02 0.0004   0.0004   0.0005   0.0035   0.0026   |   10944    11088    3928     39584    87008    |    30    43+12      14+8   0+0    0+0    
+llubenchmark.llvm.lib       0.02 0.0005   0.0003   0.0003   0.0037   0.0030   |   11008    9448     2600     33976    123336   |    *     31+7       15+5   0+0    0+0    
+lists.llvm.lib              0.02 0.0010   0.0010   0.0014   0.0054   0.0036   |   25352    15608    14344    67520    139752   |    29    67+26      3+1    0+0    0+0    
+em3d.llvm.lib               0.02 0.0011   0.0013   0.0011   0.0063   0.0055   |   24320    32736    12984    86912    224936   |    1     178+28     12+4   0+0    0+0    
+bisort.llvm.lib             0.02 0.0006   0.0005   0.0003   0.0033   0.0030   |   13520    11672    3704     45912    125120   |    *     35+13      7+4    0+0    0+0    
+treeadd.llvm.lib            0.01 0.0003   0.0003   0.0002   0.0023   0.0019   |   8064     7512     2200     29880    70776    |    *     25+7       6+3    0+0    0+0    
+sumarraymalloc.llvm.lib     0.01 0.0002   0.0002   0.0002   0.0020   0.0015   |   2712     7000     2048     25576    54608    |    *     23+5       7+4    0+0    0+0    
+sumarray.llvm.lib           0.01 0.0001   0.0001   0.0001   0.0011   0.0007   |   904      3192     624      4720     15112    |    *     6+1        4+1    0+0    0+0    
+sumarray2d.llvm.lib         0.01 0.0002   0.0001   0.0001   0.0013   0.0009   |   1568     3536     848      8176     22504    |    *     10+1       7+1    0+0    0+0    
+sieve.llvm.lib              0.01 0.0002   0.0002   0.0001   0.0020   0.0033   |   2152     6144     1616     23240    216328   |    *     22+2       12+1   0+0    0+0    
+random.llvm.lib             0.01 0.0002   0.0002   0.0001   0.0017   0.0014   |   7616     1632     1320     23104    46680    |    *     15+2       3+1    0+0    0+0    
+printargs.llvm.lib          0.01 0.0001   0.0001   0.0001   0.0011   0.0008   |   1248     1048     704      5144     19104    |    *     6+1        4+1    0+0    0+0    
+pi.llvm.lib                 0.01 0.0002   0.0001   0.0001   0.0016   0.0011   |   5392     3800     4728     13920    35880    |    *     17+2       13+2   0+0    0+0    
+matrixTranspose.llvm.lib    0.01 0.0002   0.0001   0.0001   0.0012   0.0013   |   5800     1144     736      7680     69712    |    *     8+1        5+1    0+0    0+0    
+matrix.llvm.lib             0.01 0.0003   0.0003   0.0003   0.0028   0.0018   |   10088    8616     10672    40912    68728    |    *     38+9       12+8   0+0    0+0    
+indvars.llvm.lib            0.01 0.0002   0.0001   0.0001   0.0014   0.0010   |   4760     1080     1016     9392     31536    |    *     13+1       8+1    0+0    0+0    
+hello.llvm.lib              0.01 0.0001   0.0001   0.0000   0.0009   0.0007   |   752      2952     472      6512     12216    |    *     2+0        0+0    0+0    0+0    
+heapsort.llvm.lib           0.01 0.0002   0.0002   0.0001   0.0021   0.0017   |   2856     6968     2008     26672    63368    |    *     26+3       7+2    0+0    0+0    
+fib2.llvm.lib               0.01 0.0002   0.0002   0.0001   0.0019   0.0013   |   5696     6136     1640     26200    41992    |    *     21+5       8+3    0+0    0+0    
+ary3.llvm.lib               0.01 0.0003   0.0004   0.0002   0.0026   0.0018   |   10264    21184    3008     45968    72576    |    6     44+5       12+3   0+0    0+0    
+ackermann.llvm.lib          0.01 0.0002   0.0002   0.0001   0.0016   0.0014   |   1752     5736     1200     24944    46728    |    *     13+2       3+1    0+0    0+0    
+

+ + +

Nov 12, 2002:

Chris Lattner -Last modified: Tue Nov 12 10:06:27 CST 2002 +Last modified: Thu Nov 14 20:00:50 CST 2002 From lattner at cs.uiuc.edu Sun Nov 17 16:34:01 2002 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Sun Nov 17 16:34:01 2002 Subject: [llvm-commits] CVS: llvm/lib/Target/X86/InstSelectSimple.cpp Message-ID: <200211172233.QAA19545@apoc.cs.uiuc.edu> Changes in directory llvm/lib/Target/X86: InstSelectSimple.cpp updated: 1.27 -> 1.28 --- Log message: Fix minor detail --- Diffs of the changes: Index: llvm/lib/Target/X86/InstSelectSimple.cpp diff -u llvm/lib/Target/X86/InstSelectSimple.cpp:1.27 llvm/lib/Target/X86/InstSelectSimple.cpp:1.28 --- llvm/lib/Target/X86/InstSelectSimple.cpp:1.27 Sun Nov 17 15:56:38 2002 +++ llvm/lib/Target/X86/InstSelectSimple.cpp Sun Nov 17 16:33:26 2002 @@ -451,7 +451,7 @@ BuildMI(BB, MovOpcode[Class], 1, Reg).addReg(Op0Reg); // Emit the appropriate multiply instruction... - BuildMI(BB, MulOpcode[Class], 4) + BuildMI(BB, MulOpcode[Class], 3) .addReg(Reg, UseAndDef).addReg(Op1Reg).addClobber(Clobber); // Put the result into the destination register... From lattner at cs.uiuc.edu Sun Nov 17 16:35:01 2002 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Sun Nov 17 16:35:01 2002 Subject: [llvm-commits] CVS: llvm/include/llvm/CodeGen/MachineInstr.h Message-ID: <200211172234.QAA19556@apoc.cs.uiuc.edu> Changes in directory llvm/include/llvm/CodeGen: MachineInstr.h updated: 1.86 -> 1.87 --- Log message: Finish enumating code --- Diffs of the changes: Index: llvm/include/llvm/CodeGen/MachineInstr.h diff -u llvm/include/llvm/CodeGen/MachineInstr.h:1.86 llvm/include/llvm/CodeGen/MachineInstr.h:1.87 --- llvm/include/llvm/CodeGen/MachineInstr.h:1.86 Sun Nov 17 16:14:22 2002 +++ llvm/include/llvm/CodeGen/MachineInstr.h Sun Nov 17 16:33:54 2002 @@ -383,7 +383,7 @@ /// addRegOperand - Add a MO_VirtualRegister operand to the end of the /// operands list... /// - void addRegOperand(Value *V, bool isDef=false, bool isDefAndUse=false) { + void addRegOperand(Value *V, bool isDef, bool isDefAndUse=false) { assert(!OperandsComplete() && "Trying to add an operand to a machine instr that is already done!"); operands.push_back(MachineOperand(V, MachineOperand::MO_VirtualRegister, @@ -399,13 +399,22 @@ /// addRegOperand - Add a symbolic virtual register reference... /// - void addRegOperand(int reg, bool isDef = false) { + void addRegOperand(int reg, bool isDef) { assert(!OperandsComplete() && "Trying to add an operand to a machine instr that is already done!"); operands.push_back(MachineOperand(reg, MachineOperand::MO_VirtualRegister, isDef ? MOTy::Def : MOTy::Use)); } + /// addRegOperand - Add a symbolic virtual register reference... + /// + void addRegOperand(int reg, MOTy::UseType UTy = MOTy::Use) { + assert(!OperandsComplete() && + "Trying to add an operand to a machine instr that is already done!"); + operands.push_back(MachineOperand(reg, MachineOperand::MO_VirtualRegister, + UTy)); + } + /// addPCDispOperand - Add a PC relative displacement operand to the MI /// void addPCDispOperand(Value *V) { @@ -417,11 +426,21 @@ /// addMachineRegOperand - Add a virtual register operand to this MachineInstr /// - void addMachineRegOperand(int reg, bool isDef=false) { + void addMachineRegOperand(int reg, bool isDef) { assert(!OperandsComplete() && "Trying to add an operand to a machine instr that is already done!"); operands.push_back(MachineOperand(reg, MachineOperand::MO_MachineRegister, isDef ? MOTy::Def : MOTy::Use)); + insertUsedReg(reg); + } + + /// addMachineRegOperand - Add a virtual register operand to this MachineInstr + /// + void addMachineRegOperand(int reg, MOTy::UseType UTy = MOTy::Use) { + assert(!OperandsComplete() && + "Trying to add an operand to a machine instr that is already done!"); + operands.push_back(MachineOperand(reg, MachineOperand::MO_MachineRegister, + UTy)); insertUsedReg(reg); } From lattner at cs.uiuc.edu Sun Nov 17 16:54:00 2002 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Sun Nov 17 16:54:00 2002 Subject: [llvm-commits] CVS: llvm/lib/Target/MachineInstrInfo.cpp Message-ID: <200211172253.QAA20436@apoc.cs.uiuc.edu> Changes in directory llvm/lib/Target: MachineInstrInfo.cpp updated: 1.3 -> 1.4 --- Log message: Add default implementation of printing interface --- Diffs of the changes: Index: llvm/lib/Target/MachineInstrInfo.cpp diff -u llvm/lib/Target/MachineInstrInfo.cpp:1.3 llvm/lib/Target/MachineInstrInfo.cpp:1.4 --- llvm/lib/Target/MachineInstrInfo.cpp:1.3 Tue Oct 29 11:37:48 2002 +++ llvm/lib/Target/MachineInstrInfo.cpp Sun Nov 17 16:53:03 2002 @@ -1,11 +1,10 @@ -//===-- TargetMachine.cpp - General Target Information ---------------------==// +//===-- MachineInstrInfo.cpp - Target Instruction Information -------------===// // -// This file describes the general parts of a Target machine. -// This file also implements MachineInstrInfo and MachineCacheInfo. // //===----------------------------------------------------------------------===// #include "llvm/Target/MachineInstrInfo.h" +#include "llvm/CodeGen/MachineInstr.h" #include "llvm/Constant.h" #include "llvm/DerivedTypes.h" @@ -34,6 +33,9 @@ TargetInstrDescriptors = NULL; // reset global variable } +void MachineInstrInfo::print(const MachineInstr *MI, std::ostream &O) const { + O << *MI; +} bool MachineInstrInfo::constantFitsInImmedField(MachineOpCode opCode, int64_t intValue) const { From lattner at cs.uiuc.edu Sun Nov 17 16:54:04 2002 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Sun Nov 17 16:54:04 2002 Subject: [llvm-commits] CVS: llvm/lib/Target/X86/Printer.cpp X86InstrInfo.cpp X86InstrInfo.h Message-ID: <200211172253.QAA20448@apoc.cs.uiuc.edu> Changes in directory llvm/lib/Target/X86: Printer.cpp updated: 1.4 -> 1.5 X86InstrInfo.cpp updated: 1.5 -> 1.6 X86InstrInfo.h updated: 1.6 -> 1.7 --- Log message: Reorganize printing interface a bit --- Diffs of the changes: Index: llvm/lib/Target/X86/Printer.cpp diff -u llvm/lib/Target/X86/Printer.cpp:1.4 llvm/lib/Target/X86/Printer.cpp:1.5 --- llvm/lib/Target/X86/Printer.cpp:1.4 Thu Nov 14 16:32:30 2002 +++ llvm/lib/Target/X86/Printer.cpp Sun Nov 17 16:53:13 2002 @@ -11,7 +11,7 @@ #include "llvm/Function.h" #include "llvm/Target/TargetMachine.h" #include "llvm/CodeGen/MachineFunction.h" -#include +#include "llvm/CodeGen/MachineInstr.h" namespace { struct Printer : public FunctionPass { @@ -24,6 +24,15 @@ }; } +/// createX86CodePrinterPass - Print out the specified machine code function to +/// the specified stream. This function should work regardless of whether or +/// not the function is in SSA form or not. +/// +Pass *createX86CodePrinterPass(TargetMachine &TM, std::ostream &O) { + return new Printer(TM, O); +} + + /// runOnFunction - This uses the X86InstructionInfo::print method /// to print assembly for each instruction. bool Printer::runOnFunction (Function & F) @@ -31,9 +40,8 @@ static unsigned bbnumber = 0; MachineFunction & MF = MachineFunction::get (&F); const MachineInstrInfo & MII = TM.getInstrInfo (); - const X86InstrInfo & x86ii = dynamic_cast (MII); - O << "# x86 printing not implemented yet!\n"; + O << "# x86 printing only sorta implemented so far!\n"; // Print out labels for the function. O << "\t.globl\t" << F.getName () << "\n"; @@ -51,7 +59,7 @@ { // Print the assembly for the instruction. O << "\t"; - x86ii.print (*i_i, O); + MII.print(*i_i, O); } } @@ -59,10 +67,9 @@ return false; } -/// createX86CodePrinterPass - Print out the specified machine code function to -/// the specified stream. This function should work regardless of whether or -/// not the function is in SSA form or not. -/// -Pass *createX86CodePrinterPass(TargetMachine &TM, std::ostream &O) { - return new Printer(TM, O); + +// print - Print out an x86 instruction in intel syntax +void X86InstrInfo::print(const MachineInstr *MI, std::ostream &O) const { + // FIXME: This sucks. + O << getName(MI->getOpCode()) << "\n"; } Index: llvm/lib/Target/X86/X86InstrInfo.cpp diff -u llvm/lib/Target/X86/X86InstrInfo.cpp:1.5 llvm/lib/Target/X86/X86InstrInfo.cpp:1.6 --- llvm/lib/Target/X86/X86InstrInfo.cpp:1.5 Tue Oct 29 19:15:31 2002 +++ llvm/lib/Target/X86/X86InstrInfo.cpp Sun Nov 17 16:53:13 2002 @@ -25,9 +25,3 @@ } -// print - Print out an x86 instruction in GAS syntax -void X86InstrInfo::print(const MachineInstr *MI, std::ostream &O) const { - // FIXME: This sucks. - O << getName(MI->getOpCode()) << "\n"; -} - Index: llvm/lib/Target/X86/X86InstrInfo.h diff -u llvm/lib/Target/X86/X86InstrInfo.h:1.6 llvm/lib/Target/X86/X86InstrInfo.h:1.7 --- llvm/lib/Target/X86/X86InstrInfo.h:1.6 Tue Oct 29 19:09:34 2002 +++ llvm/lib/Target/X86/X86InstrInfo.h Sun Nov 17 16:53:13 2002 @@ -30,7 +30,7 @@ /// virtual const MRegisterInfo &getRegisterInfo() const { return RI; } - /// print - Print out an x86 instruction in GAS syntax + /// print - Print out an x86 instruction in intel syntax /// virtual void print(const MachineInstr *MI, std::ostream &O) const; From lattner at cs.uiuc.edu Sun Nov 17 16:56:01 2002 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Sun Nov 17 16:56:01 2002 Subject: [llvm-commits] CVS: llvm/include/llvm/Target/MachineInstrInfo.h Message-ID: <200211172255.QAA20465@apoc.cs.uiuc.edu> Changes in directory llvm/include/llvm/Target: MachineInstrInfo.h updated: 1.33 -> 1.34 --- Log message: Add machine independant printer interface --- Diffs of the changes: Index: llvm/include/llvm/Target/MachineInstrInfo.h diff -u llvm/include/llvm/Target/MachineInstrInfo.h:1.33 llvm/include/llvm/Target/MachineInstrInfo.h:1.34 --- llvm/include/llvm/Target/MachineInstrInfo.h:1.33 Tue Oct 29 19:06:53 2002 +++ llvm/include/llvm/Target/MachineInstrInfo.h Sun Nov 17 16:54:55 2002 @@ -94,6 +94,12 @@ return desc[opCode]; } + /// print - Print out the specified machine instruction in the appropriate + /// target specific assembly language. If this method is not overridden, the + /// default implementation uses the crummy machine independant printer. + /// + virtual void print(const MachineInstr *MI, std::ostream &O) const; + const char *getName(MachineOpCode opCode) const { return get(opCode).Name; } From lattner at cs.uiuc.edu Sun Nov 17 16:58:01 2002 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Sun Nov 17 16:58:01 2002 Subject: [llvm-commits] CVS: llvm/lib/Target/Sparc/EmitAssembly.cpp Message-ID: <200211172257.QAA20487@apoc.cs.uiuc.edu> Changes in directory llvm/lib/Target/Sparc: EmitAssembly.cpp updated: 1.71 -> 1.72 --- Log message: Fix misleading indentation --- Diffs of the changes: Index: llvm/lib/Target/Sparc/EmitAssembly.cpp diff -u llvm/lib/Target/Sparc/EmitAssembly.cpp:1.71 llvm/lib/Target/Sparc/EmitAssembly.cpp:1.72 --- llvm/lib/Target/Sparc/EmitAssembly.cpp:1.71 Tue Nov 5 18:34:26 2002 +++ llvm/lib/Target/Sparc/EmitAssembly.cpp Sun Nov 17 16:57:23 2002 @@ -457,9 +457,8 @@ if (NeedComma) toAsm << ", "; // Handle comma outputing NeedComma = true; N = printOperands(MI, OpNum); - } - else - N = 1; + } else + N = 1; toAsm << "\n"; } From lattner at cs.uiuc.edu Sun Nov 17 17:04:01 2002 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Sun Nov 17 17:04:01 2002 Subject: [llvm-commits] CVS: llvm/lib/Target/X86/X86RegisterInfo.def Message-ID: <200211172303.RAA20512@apoc.cs.uiuc.edu> Changes in directory llvm/lib/Target/X86: X86RegisterInfo.def updated: 1.3 -> 1.4 --- Log message: Rename registers to follow the intel style of all caps --- Diffs of the changes: Index: llvm/lib/Target/X86/X86RegisterInfo.def diff -u llvm/lib/Target/X86/X86RegisterInfo.def:1.3 llvm/lib/Target/X86/X86RegisterInfo.def:1.4 --- llvm/lib/Target/X86/X86RegisterInfo.def:1.3 Thu Nov 14 16:32:30 2002 +++ llvm/lib/Target/X86/X86RegisterInfo.def Sun Nov 17 17:03:46 2002 @@ -26,48 +26,50 @@ // is used as the destination register for instructions that do not produce a // value. Some frontends may use this as an operand register to mean special // things, for example, the Sparc backend uses R#0 to mean %g0 which always -// PRODUCES the value 0. The X86 backend does not use this value as an operand -// register. +// PRODUCES the value 0. +// +// The X86 backend uses this value as an operand register only in memory +// references where it means that there is no base or index register. // R(NoReg, "none", 0, 0) // 32 bit registers, ordered as the processor does... -R(EAX, "eax", MRF::INT32, 0) -R(ECX, "ecx", MRF::INT32, 0) -R(EDX, "edx", MRF::INT32, 0) -R(EBX, "ebx", MRF::INT32, 0) -R(ESP, "esp", MRF::INT32, 0) -R(EBP, "ebp", MRF::INT32, 0) -R(ESI, "esi", MRF::INT32, 0) -R(EDI, "edi", MRF::INT32, 0) +R(EAX, "EAX", MRF::INT32, 0) +R(ECX, "ECX", MRF::INT32, 0) +R(EDX, "EDX", MRF::INT32, 0) +R(EBX, "EBX", MRF::INT32, 0) +R(ESP, "ESP", MRF::INT32, 0) +R(EBP, "EBP", MRF::INT32, 0) +R(ESI, "ESI", MRF::INT32, 0) +R(EDI, "EDI", MRF::INT32, 0) // 16 bit registers, aliased with the corresponding 32 bit registers above -R(AX, "ax", MRF::INT16, 0) -R(CX, "cx", MRF::INT16, 0) -R(DX, "dx", MRF::INT16, 0) -R(BX, "bx", MRF::INT16, 0) -R(SP, "sp", MRF::INT16, 0) -R(BP, "bp", MRF::INT16, 0) -R(SI, "si", MRF::INT16, 0) -R(DI, "di", MRF::INT16, 0) +R(AX, "AX", MRF::INT16, 0) +R(CX, "CX", MRF::INT16, 0) +R(DX, "Dx", MRF::INT16, 0) +R(BX, "BX", MRF::INT16, 0) +R(SP, "SP", MRF::INT16, 0) +R(BP, "BP", MRF::INT16, 0) +R(SI, "SI", MRF::INT16, 0) +R(DI, "DI", MRF::INT16, 0) // 8 bit registers aliased with registers above as well -R(AL, "al", MRF::INT8, 0) -R(CL, "cl", MRF::INT8, 0) -R(DL, "dl", MRF::INT8, 0) -R(BL, "bl", MRF::INT8, 0) -R(AH, "ah", MRF::INT8, 0) -R(CH, "ch", MRF::INT8, 0) -R(DH, "dh", MRF::INT8, 0) -R(BH, "bh", MRF::INT8, 0) +R(AL, "AL", MRF::INT8, 0) +R(CL, "CL", MRF::INT8, 0) +R(DL, "DL", MRF::INT8, 0) +R(BL, "BL", MRF::INT8, 0) +R(AH, "AH", MRF::INT8, 0) +R(CH, "CH", MRF::INT8, 0) +R(DH, "DH", MRF::INT8, 0) +R(BH, "BH", MRF::INT8, 0) // Flags, Segment registers, etc... // This is a slimy hack to make it possible to say that flags are clobbered... // Ideally we'd model instructions based on which particular flag(s) they // could clobber. -R(EFLAGS, "eflags", MRF::INT8, 0) +R(EFLAGS, "EFLAGS", MRF::INT16, 0) // We are now done with the R macro #undef R From lattner at cs.uiuc.edu Sun Nov 17 17:06:01 2002 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Sun Nov 17 17:06:01 2002 Subject: [llvm-commits] CVS: llvm/lib/Target/X86/X86RegisterInfo.def Message-ID: <200211172305.RAA20577@apoc.cs.uiuc.edu> Changes in directory llvm/lib/Target/X86: X86RegisterInfo.def updated: 1.4 -> 1.5 --- Log message: Wow, I'm incapable of the simplest things today... --- Diffs of the changes: Index: llvm/lib/Target/X86/X86RegisterInfo.def diff -u llvm/lib/Target/X86/X86RegisterInfo.def:1.4 llvm/lib/Target/X86/X86RegisterInfo.def:1.5 --- llvm/lib/Target/X86/X86RegisterInfo.def:1.4 Sun Nov 17 17:03:46 2002 +++ llvm/lib/Target/X86/X86RegisterInfo.def Sun Nov 17 17:05:21 2002 @@ -47,7 +47,7 @@ // 16 bit registers, aliased with the corresponding 32 bit registers above R(AX, "AX", MRF::INT16, 0) R(CX, "CX", MRF::INT16, 0) -R(DX, "Dx", MRF::INT16, 0) +R(DX, "DX", MRF::INT16, 0) R(BX, "BX", MRF::INT16, 0) R(SP, "SP", MRF::INT16, 0) R(BP, "BP", MRF::INT16, 0) From lattner at cs.uiuc.edu Sun Nov 17 17:11:01 2002 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Sun Nov 17 17:11:01 2002 Subject: [llvm-commits] CVS: llvm/include/llvm/Analysis/CallGraph.h Message-ID: <200211172310.RAA21165@apoc.cs.uiuc.edu> Changes in directory llvm/include/llvm/Analysis: CallGraph.h updated: 1.24 -> 1.25 --- Log message: Omit the indirect node when printing call graphs --- Diffs of the changes: Index: llvm/include/llvm/Analysis/CallGraph.h diff -u llvm/include/llvm/Analysis/CallGraph.h:1.24 llvm/include/llvm/Analysis/CallGraph.h:1.25 --- llvm/include/llvm/Analysis/CallGraph.h:1.24 Sun Nov 3 20:53:39 2002 +++ llvm/include/llvm/Analysis/CallGraph.h Sun Nov 17 17:10:27 2002 @@ -253,7 +253,9 @@ // nodes_iterator/begin/end - Allow iteration over all nodes in the graph typedef mapped_iterator nodes_iterator; static nodes_iterator nodes_begin(CallGraph *CG) { - return map_iterator(CG->begin(), DerefFun(CGdereference)); + CallGraph::iterator I = CG->begin(); + ++I; + return map_iterator(I, DerefFun(CGdereference)); } static nodes_iterator nodes_end (CallGraph *CG) { return map_iterator(CG->end(), DerefFun(CGdereference)); From lattner at cs.uiuc.edu Sun Nov 17 17:21:01 2002 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Sun Nov 17 17:21:01 2002 Subject: [llvm-commits] CVS: llvm/lib/Target/X86/Printer.cpp X86InstrInfo.h Message-ID: <200211172320.RAA22423@apoc.cs.uiuc.edu> Changes in directory llvm/lib/Target/X86: Printer.cpp updated: 1.5 -> 1.6 X86InstrInfo.h updated: 1.7 -> 1.8 --- Log message: Arrange to have a TargetMachine available in X86InstrInfo::print --- Diffs of the changes: Index: llvm/lib/Target/X86/Printer.cpp diff -u llvm/lib/Target/X86/Printer.cpp:1.5 llvm/lib/Target/X86/Printer.cpp:1.6 --- llvm/lib/Target/X86/Printer.cpp:1.5 Sun Nov 17 16:53:13 2002 +++ llvm/lib/Target/X86/Printer.cpp Sun Nov 17 17:20:37 2002 @@ -41,7 +41,7 @@ MachineFunction & MF = MachineFunction::get (&F); const MachineInstrInfo & MII = TM.getInstrInfo (); - O << "# x86 printing only sorta implemented so far!\n"; + O << "; x86 printing only sorta implemented so far!\n"; // Print out labels for the function. O << "\t.globl\t" << F.getName () << "\n"; @@ -59,7 +59,7 @@ { // Print the assembly for the instruction. O << "\t"; - MII.print(*i_i, O); + MII.print(*i_i, O, TM); } } @@ -69,7 +69,8 @@ // print - Print out an x86 instruction in intel syntax -void X86InstrInfo::print(const MachineInstr *MI, std::ostream &O) const { +void X86InstrInfo::print(const MachineInstr *MI, std::ostream &O, + const TargetMachine &TM) const { // FIXME: This sucks. O << getName(MI->getOpCode()) << "\n"; } Index: llvm/lib/Target/X86/X86InstrInfo.h diff -u llvm/lib/Target/X86/X86InstrInfo.h:1.7 llvm/lib/Target/X86/X86InstrInfo.h:1.8 --- llvm/lib/Target/X86/X86InstrInfo.h:1.7 Sun Nov 17 16:53:13 2002 +++ llvm/lib/Target/X86/X86InstrInfo.h Sun Nov 17 17:20:37 2002 @@ -32,7 +32,8 @@ /// print - Print out an x86 instruction in intel syntax /// - virtual void print(const MachineInstr *MI, std::ostream &O) const; + virtual void print(const MachineInstr *MI, std::ostream &O, + const TargetMachine &TM) const; //===--------------------------------------------------------------------===// From lattner at cs.uiuc.edu Sun Nov 17 17:22:01 2002 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Sun Nov 17 17:22:01 2002 Subject: [llvm-commits] CVS: llvm/include/llvm/CodeGen/MachineInstr.h Message-ID: <200211172321.RAA22443@apoc.cs.uiuc.edu> Changes in directory llvm/include/llvm/CodeGen: MachineInstr.h updated: 1.87 -> 1.88 --- Log message: Print is const! --- Diffs of the changes: Index: llvm/include/llvm/CodeGen/MachineInstr.h diff -u llvm/include/llvm/CodeGen/MachineInstr.h:1.87 llvm/include/llvm/CodeGen/MachineInstr.h:1.88 --- llvm/include/llvm/CodeGen/MachineInstr.h:1.87 Sun Nov 17 16:33:54 2002 +++ llvm/include/llvm/CodeGen/MachineInstr.h Sun Nov 17 17:21:26 2002 @@ -347,7 +347,7 @@ // // Debugging support // - void print(std::ostream &OS, const TargetMachine &TM); + void print(std::ostream &OS, const TargetMachine &TM) const; void dump() const; friend std::ostream& operator<<(std::ostream& os, const MachineInstr& minstr); From lattner at cs.uiuc.edu Sun Nov 17 17:22:04 2002 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Sun Nov 17 17:22:04 2002 Subject: [llvm-commits] CVS: llvm/include/llvm/Target/MachineInstrInfo.h Message-ID: <200211172321.RAA22453@apoc.cs.uiuc.edu> Changes in directory llvm/include/llvm/Target: MachineInstrInfo.h updated: 1.34 -> 1.35 --- Log message: Make sure that print gets a targetmachine CVS: ---------------------------------------------------------------------- --- Diffs of the changes: Index: llvm/include/llvm/Target/MachineInstrInfo.h diff -u llvm/include/llvm/Target/MachineInstrInfo.h:1.34 llvm/include/llvm/Target/MachineInstrInfo.h:1.35 --- llvm/include/llvm/Target/MachineInstrInfo.h:1.34 Sun Nov 17 16:54:55 2002 +++ llvm/include/llvm/Target/MachineInstrInfo.h Sun Nov 17 17:21:45 2002 @@ -98,7 +98,8 @@ /// target specific assembly language. If this method is not overridden, the /// default implementation uses the crummy machine independant printer. /// - virtual void print(const MachineInstr *MI, std::ostream &O) const; + virtual void print(const MachineInstr *MI, std::ostream &O, + const TargetMachine &TM) const; const char *getName(MachineOpCode opCode) const { return get(opCode).Name; From lattner at cs.uiuc.edu Sun Nov 17 17:23:01 2002 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Sun Nov 17 17:23:01 2002 Subject: [llvm-commits] CVS: llvm/lib/Target/MachineInstrInfo.cpp Message-ID: <200211172322.RAA22469@apoc.cs.uiuc.edu> Changes in directory llvm/lib/Target: MachineInstrInfo.cpp updated: 1.4 -> 1.5 --- Log message: Pass on a targetmachine --- Diffs of the changes: Index: llvm/lib/Target/MachineInstrInfo.cpp diff -u llvm/lib/Target/MachineInstrInfo.cpp:1.4 llvm/lib/Target/MachineInstrInfo.cpp:1.5 --- llvm/lib/Target/MachineInstrInfo.cpp:1.4 Sun Nov 17 16:53:03 2002 +++ llvm/lib/Target/MachineInstrInfo.cpp Sun Nov 17 17:22:03 2002 @@ -33,8 +33,9 @@ TargetInstrDescriptors = NULL; // reset global variable } -void MachineInstrInfo::print(const MachineInstr *MI, std::ostream &O) const { - O << *MI; +void MachineInstrInfo::print(const MachineInstr *MI, std::ostream &O, + const TargetMachine &TM) const { + MI->print(O, TM); } bool MachineInstrInfo::constantFitsInImmedField(MachineOpCode opCode, From lattner at cs.uiuc.edu Sun Nov 17 17:23:05 2002 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Sun Nov 17 17:23:05 2002 Subject: [llvm-commits] CVS: llvm/lib/CodeGen/MachineInstr.cpp Message-ID: <200211172322.RAA22476@apoc.cs.uiuc.edu> Changes in directory llvm/lib/CodeGen: MachineInstr.cpp updated: 1.64 -> 1.65 --- Log message: Print is const! --- Diffs of the changes: Index: llvm/lib/CodeGen/MachineInstr.cpp diff -u llvm/lib/CodeGen/MachineInstr.cpp:1.64 llvm/lib/CodeGen/MachineInstr.cpp:1.65 --- llvm/lib/CodeGen/MachineInstr.cpp:1.64 Sun Nov 17 16:14:08 2002 +++ llvm/lib/CodeGen/MachineInstr.cpp Sun Nov 17 17:22:13 2002 @@ -268,7 +268,7 @@ OS << ")"; } -void MachineInstr::print(std::ostream &OS, const TargetMachine &TM) { +void MachineInstr::print(std::ostream &OS, const TargetMachine &TM) const { unsigned StartOp = 0; // Specialize printing if op#0 is definition From lattner at cs.uiuc.edu Sun Nov 17 19:35:00 2002 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Sun Nov 17 19:35:00 2002 Subject: [llvm-commits] CVS: llvm/lib/Target/X86/X86InstrInfo.def Message-ID: <200211180134.TAA22853@apoc.cs.uiuc.edu> Changes in directory llvm/lib/Target/X86: X86InstrInfo.def updated: 1.16 -> 1.17 --- Log message: Set the void flag on instructions that should get it --- Diffs of the changes: Index: llvm/lib/Target/X86/X86InstrInfo.def diff -u llvm/lib/Target/X86/X86InstrInfo.def:1.16 llvm/lib/Target/X86/X86InstrInfo.def:1.17 --- llvm/lib/Target/X86/X86InstrInfo.def:1.16 Sun Nov 17 14:33:12 2002 +++ llvm/lib/Target/X86/X86InstrInfo.def Sun Nov 17 19:34:36 2002 @@ -27,10 +27,10 @@ // defined in X86InstrInfo.h in the X86II namespace. // -// The first instruction must always be the PHI instruction: (FIXME, not yet) +// The first instruction must always be the PHI instruction: I(PHI , "phi", 0, 0) -// The second instruction must always be the noop instruction: (FIXME, not yet) +// The second instruction must always be the noop instruction: I(NOOP , "nop", 0, X86II::Void) // nop 90 // Flow control instructions @@ -50,9 +50,9 @@ I(MOVmr8 , "movb", 0, 0) // R8 = [mem] 8A/r I(MOVmr16 , "movw", 0, 0) // R16 = [mem] 8B/r I(MOVmr32 , "movl", 0, 0) // R32 = [mem] 8B/r -I(MOVrm8 , "movb", 0, 0) // [mem] = R8 88/r -I(MOVrm16 , "movw", 0, 0) // [mem] = R16 89/r -I(MOVrm32 , "movl", 0, 0) // [mem] = R32 89/r +I(MOVrm8 , "movb", 0, X86II::Void) // [mem] = R8 88/r +I(MOVrm16 , "movw", 0, X86II::Void) // [mem] = R16 89/r +I(MOVrm32 , "movl", 0, X86II::Void) // [mem] = R32 89/r // Arithmetic instructions I(ADDrr8 , "addb", 0, 0) // R8 += R8 00/r @@ -66,14 +66,14 @@ I(MULrr32 , "mull", 0, 0) // ED:EA= EA*R32 F7/4 // unsigned division/remainder -I(DIVrr8 , "divb", 0, 0) // AX/r8= AL&AH F6/6 -I(DIVrr16 , "divw", 0, 0) // DA/r16=AX&DX F7/6 -I(DIVrr32 , "divl", 0, 0) // DA/r32=EAX&DX F7/6 +I(DIVrr8 , "divb", 0, X86II::Void) // AX/r8= AL&AH F6/6 +I(DIVrr16 , "divw", 0, X86II::Void) // DA/r16=AX&DX F7/6 +I(DIVrr32 , "divl", 0, X86II::Void) // DA/r32=EAX&DX F7/6 // signed division/remainder -I(IDIVrr8 , "idivb", 0, 0) // AX/r8= AL&AH F6/6 -I(IDIVrr16 , "idivw", 0, 0) // DA/r16=AX&DX F7/6 -I(IDIVrr32 , "idivl", 0, 0) // DA/r32=EAX&DX F7/6 +I(IDIVrr8 , "idivb", 0, X86II::Void) // AX/r8= AL&AH F6/6 +I(IDIVrr16 , "idivw", 0, X86II::Void) // DA/r16=AX&DX F7/6 +I(IDIVrr32 , "idivl", 0, X86II::Void) // DA/r32=EAX&DX F7/6 // Logical operators I(ANDrr8 , "andb", 0, 0) // R8 &= R8 20/r From lattner at cs.uiuc.edu Sun Nov 17 19:38:00 2002 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Sun Nov 17 19:38:00 2002 Subject: [llvm-commits] CVS: llvm/lib/Target/X86/X86InstrInfo.def Message-ID: <200211180137.TAA22875@apoc.cs.uiuc.edu> Changes in directory llvm/lib/Target/X86: X86InstrInfo.def updated: 1.17 -> 1.18 --- Log message: Add more void flags --- Diffs of the changes: Index: llvm/lib/Target/X86/X86InstrInfo.def diff -u llvm/lib/Target/X86/X86InstrInfo.def:1.17 llvm/lib/Target/X86/X86InstrInfo.def:1.18 --- llvm/lib/Target/X86/X86InstrInfo.def:1.17 Sun Nov 17 19:34:36 2002 +++ llvm/lib/Target/X86/X86InstrInfo.def Sun Nov 17 19:37:48 2002 @@ -61,9 +61,9 @@ I(SUBrr8 , "subb", 0, 0) // R8 -= R8 2A/r I(SUBrr16 , "subw", 0, 0) // R16 -= R16 2B/r I(SUBrr32 , "subl", 0, 0) // R32 -= R32 2B/r -I(MULrr8 , "mulb", 0, 0) // AX = AL*R8 F6/4 -I(MULrr16 , "mulw", 0, 0) // DX:AX= AX*R16 F7/4 -I(MULrr32 , "mull", 0, 0) // ED:EA= EA*R32 F7/4 +I(MULrr8 , "mulb", 0, X86II::Void) // AX = AL*R8 F6/4 +I(MULrr16 , "mulw", 0, X86II::Void) // DX:AX= AX*R16 F7/4 +I(MULrr32 , "mull", 0, X86II::Void) // ED:EA= EA*R32 F7/4 // unsigned division/remainder I(DIVrr8 , "divb", 0, X86II::Void) // AX/r8= AL&AH F6/6 From lattner at cs.uiuc.edu Sun Nov 17 20:00:01 2002 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Sun Nov 17 20:00:01 2002 Subject: [llvm-commits] CVS: llvm/lib/Target/X86/X86InstrInfo.def X86InstrInfo.h Message-ID: <200211180159.TAA22914@apoc.cs.uiuc.edu> Changes in directory llvm/lib/Target/X86: X86InstrInfo.def updated: 1.18 -> 1.19 X86InstrInfo.h updated: 1.8 -> 1.9 --- Log message: Add instruction annotation about whether it has a 0x0F opcode prefix --- Diffs of the changes: Index: llvm/lib/Target/X86/X86InstrInfo.def diff -u llvm/lib/Target/X86/X86InstrInfo.def:1.18 llvm/lib/Target/X86/X86InstrInfo.def:1.19 --- llvm/lib/Target/X86/X86InstrInfo.def:1.18 Sun Nov 17 19:37:48 2002 +++ llvm/lib/Target/X86/X86InstrInfo.def Sun Nov 17 19:59:28 2002 @@ -118,16 +118,16 @@ // Condition code ops, incl. set if equal/not equal/... I(SAHF , "sahf", 0, 0) // flags = AH 9E -I(SETA , "seta", 0, 0) // R8 = > unsign 0F 97 -I(SETAE , "setae", 0, 0) // R8 = >=unsign 0F 93 -I(SETB , "setb", 0, 0) // R8 = < unsign 0F 92 -I(SETBE , "setbe", 0, 0) // R8 = <=unsign 0F 96 -I(SETE , "sete", 0, 0) // R8 = == 0F 94 -I(SETG , "setg", 0, 0) // R8 = > signed 0F 9F -I(SETGE , "setge", 0, 0) // R8 = >=signed 0F 9D -I(SETL , "setl", 0, 0) // R8 = < signed 0F 9C -I(SETLE , "setle", 0, 0) // R8 = <=signed 0F 9E -I(SETNE , "setne", 0, 0) // R8 = != 0F 95 +I(SETA , "seta", 0, X86II::TB) // R8 = > unsign 0F 97 +I(SETAE , "setae", 0, X86II::TB) // R8 = >=unsign 0F 93 +I(SETB , "setb", 0, X86II::TB) // R8 = < unsign 0F 92 +I(SETBE , "setbe", 0, X86II::TB) // R8 = <=unsign 0F 96 +I(SETE , "sete", 0, X86II::TB) // R8 = == 0F 94 +I(SETG , "setg", 0, X86II::TB) // R8 = > signed 0F 9F +I(SETGE , "setge", 0, X86II::TB) // R8 = >=signed 0F 9D +I(SETL , "setl", 0, X86II::TB) // R8 = < signed 0F 9C +I(SETLE , "setle", 0, X86II::TB) // R8 = <=signed 0F 9E +I(SETNE , "setne", 0, X86II::TB) // R8 = != 0F 95 // Integer comparisons I(CMPrr8 , "cmpb", 0, 0) // compare R8,R8 38/r @@ -138,12 +138,12 @@ I(CBW , "cbw", 0, 0) // AX = signext(AL) 98 I(CWD , "cwd", 0, 0) // DX:AX = signext(AX) 99 I(CDQ , "cdq", 0, 0) // EDX:EAX = signext(EAX) 99 -I(MOVSXr16r8 , "movsx", 0, 0) // R32 = signext(R8) 0F BE /r -I(MOVSXr32r8 , "movsx", 0, 0) // R32 = signext(R8) 0F BE /r -I(MOVSXr32r16 , "movsx", 0, 0) // R32 = signext(R16) 0F BF /r -I(MOVZXr16r8 , "movzx", 0, 0) // R32 = zeroext(R8) 0F B6 /r -I(MOVZXr32r8 , "movzx", 0, 0) // R32 = zeroext(R8) 0F B6 /r -I(MOVZXr32r16 , "movzx", 0, 0) // R32 = zeroext(R16) 0F B7 /r +I(MOVSXr16r8 , "movsx", 0, X86II::TB) // R32 = signext(R8) 0F BE /r +I(MOVSXr32r8 , "movsx", 0, X86II::TB) // R32 = signext(R8) 0F BE /r +I(MOVSXr32r16 , "movsx", 0, X86II::TB) // R32 = signext(R16) 0F BF /r +I(MOVZXr16r8 , "movzx", 0, X86II::TB) // R32 = zeroext(R8) 0F B6 /r +I(MOVZXr32r8 , "movzx", 0, X86II::TB) // R32 = zeroext(R8) 0F B6 /r +I(MOVZXr32r16 , "movzx", 0, X86II::TB) // R32 = zeroext(R16) 0F B7 /r // At this point, I is dead, so undefine the macro #undef I Index: llvm/lib/Target/X86/X86InstrInfo.h diff -u llvm/lib/Target/X86/X86InstrInfo.h:1.8 llvm/lib/Target/X86/X86InstrInfo.h:1.9 --- llvm/lib/Target/X86/X86InstrInfo.h:1.8 Sun Nov 17 17:20:37 2002 +++ llvm/lib/Target/X86/X86InstrInfo.h Sun Nov 17 19:59:28 2002 @@ -15,7 +15,14 @@ /// namespace X86II { enum { - Void = 1 << 0, // Set if this instruction produces no value + /// Void - Set if this instruction produces no value + Void = 1 << 0, + + // TB - TwoByte - Set if this instruction has a two byte opcode, which + // starts with a 0x0F byte before the real opcode. + TB = 1 << 1, + + }; } From lattner at cs.uiuc.edu Sun Nov 17 23:38:01 2002 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Sun Nov 17 23:38:01 2002 Subject: [llvm-commits] CVS: llvm/lib/Target/X86/X86.h X86InstrInfo.cpp X86InstrInfo.def X86InstrInfo.h Message-ID: <200211180537.XAA27480@apoc.cs.uiuc.edu> Changes in directory llvm/lib/Target/X86: X86.h updated: 1.5 -> 1.6 X86InstrInfo.cpp updated: 1.6 -> 1.7 X86InstrInfo.def updated: 1.19 -> 1.20 X86InstrInfo.h updated: 1.9 -> 1.10 --- Log message: Start to add more information to instr.def --- Diffs of the changes: Index: llvm/lib/Target/X86/X86.h diff -u llvm/lib/Target/X86/X86.h:1.5 llvm/lib/Target/X86/X86.h:1.6 --- llvm/lib/Target/X86/X86.h:1.5 Tue Oct 29 16:37:54 2002 +++ llvm/lib/Target/X86/X86.h Sun Nov 17 23:37:11 2002 @@ -52,7 +52,7 @@ // This defines a large number of symbolic names for X86 instruction opcodes. enum Opcode { -#define I(ENUM, NAME, FLAGS, TSFLAGS) ENUM, +#define I(ENUM, NAME, BASEOPCODE, FLAGS, TSFLAGS) ENUM, #include "X86InstrInfo.def" }; } Index: llvm/lib/Target/X86/X86InstrInfo.cpp diff -u llvm/lib/Target/X86/X86InstrInfo.cpp:1.6 llvm/lib/Target/X86/X86InstrInfo.cpp:1.7 --- llvm/lib/Target/X86/X86InstrInfo.cpp:1.6 Sun Nov 17 16:53:13 2002 +++ llvm/lib/Target/X86/X86InstrInfo.cpp Sun Nov 17 23:37:11 2002 @@ -12,7 +12,7 @@ // descriptors // static const MachineInstrDescriptor X86Insts[] = { -#define I(ENUM, NAME, FLAGS, TSFLAGS) \ +#define I(ENUM, NAME, BASEOPCODE, FLAGS, TSFLAGS) \ { NAME, \ -1, /* Always vararg */ \ ((TSFLAGS) & X86II::Void) ? -1 : 0, /* Result is in 0 */ \ Index: llvm/lib/Target/X86/X86InstrInfo.def diff -u llvm/lib/Target/X86/X86InstrInfo.def:1.19 llvm/lib/Target/X86/X86InstrInfo.def:1.20 --- llvm/lib/Target/X86/X86InstrInfo.def:1.19 Sun Nov 17 19:59:28 2002 +++ llvm/lib/Target/X86/X86InstrInfo.def Sun Nov 17 23:37:11 2002 @@ -20,130 +20,131 @@ // Arguments to be passed into the I macro // #1: Enum name - This ends up being the opcode symbol in the X86 namespace // #2: Opcode name, as used by the gnu assembler -// #3: Instruction Flags - This should be a field or'd together that contains +// #3: The base opcode for the instruction +// #4: Instruction Flags - This should be a field or'd together that contains // constants from the MachineInstrInfo.h file. -// #4: Target Specific Flags - Another bitfield containing X86 specific flags +// #5: Target Specific Flags - Another bitfield containing X86 specific flags // that we are interested in for each instruction. These should be flags // defined in X86InstrInfo.h in the X86II namespace. // // The first instruction must always be the PHI instruction: -I(PHI , "phi", 0, 0) +I(PHI , "phi", 0, 0, 0) // The second instruction must always be the noop instruction: -I(NOOP , "nop", 0, X86II::Void) // nop 90 +I(NOOP , "nop", 0x90, 0, X86II::RawFrm | X86II::Void) // nop // Flow control instructions -I(RET , "ret", M_RET_FLAG, X86II::Void) // ret CB -I(JMP , "jmp", M_BRANCH_FLAG, X86II::Void) // jmp foo EB|E9 cb|w +I(RET , "ret", 0xCB, M_RET_FLAG, X86II::RawFrm | X86II::Void) // ret +I(JMP , "jmp", 0x00, M_BRANCH_FLAG, X86II::Void) // jmp foo EB|E9 cb|w // Misc instructions -I(LEAVE , "leave", 0, 0) // leave C9 +I(LEAVE , "leave", 0xC9, 0, X86II::RawFrm) // leave // Move instructions -I(MOVrr8 , "movb", 0, 0) // R8 = R8 88/r -I(MOVrr16 , "movw", 0, 0) // R16 = R16 89/r -I(MOVrr32 , "movl", 0, 0) // R32 = R32 89/r -I(MOVir8 , "movb", 0, 0) // R8 = imm8 B0+ rb -I(MOVir16 , "movw", 0, 0) // R16 = imm16 B8+ rw -I(MOVir32 , "movl", 0, 0) // R32 = imm32 B8+ rd -I(MOVmr8 , "movb", 0, 0) // R8 = [mem] 8A/r -I(MOVmr16 , "movw", 0, 0) // R16 = [mem] 8B/r -I(MOVmr32 , "movl", 0, 0) // R32 = [mem] 8B/r -I(MOVrm8 , "movb", 0, X86II::Void) // [mem] = R8 88/r -I(MOVrm16 , "movw", 0, X86II::Void) // [mem] = R16 89/r -I(MOVrm32 , "movl", 0, X86II::Void) // [mem] = R32 89/r +I(MOVrr8 , "movb", 0x88, 0, X86II::MRMDestReg) // R8 = R8 88/r +I(MOVrr16 , "movw", 0x89, 0, X86II::MRMDestReg) // R16 = R16 89/r +I(MOVrr32 , "movl", 0x89, 0, X86II::MRMDestReg) // R32 = R32 89/r +I(MOVir8 , "movb", 0xB0, 0, X86II::AddRegFrm) // R8 = imm8 B0+ rb +I(MOVir16 , "movw", 0xB8, 0, X86II::AddRegFrm) // R16 = imm16 B8+ rw +I(MOVir32 , "movl", 0xB8, 0, X86II::AddRegFrm) // R32 = imm32 B8+ rd +I(MOVmr8 , "movb", 0x8A, 0, X86II::MRMSrcMem) // R8 = [mem] 8A/r +I(MOVmr16 , "movw", 0x8B, 0, X86II::MRMSrcMem) // R16 = [mem] 8B/r +I(MOVmr32 , "movl", 0x8B, 0, X86II::MRMSrcMem) // R32 = [mem] 8B/r +I(MOVrm8 , "movb", 0x88, 0, X86II::MRMDestMem | X86II::Void) // [mem] = R8 88/r +I(MOVrm16 , "movw", 0x89, 0, X86II::MRMDestMem | X86II::Void) // [mem] = R16 89/r +I(MOVrm32 , "movl", 0x89, 0, X86II::MRMDestMem | X86II::Void) // [mem] = R32 89/r // Arithmetic instructions -I(ADDrr8 , "addb", 0, 0) // R8 += R8 00/r -I(ADDrr16 , "addw", 0, 0) // R16 += R16 01/r -I(ADDrr32 , "addl", 0, 0) // R32 += R32 01/r -I(SUBrr8 , "subb", 0, 0) // R8 -= R8 2A/r -I(SUBrr16 , "subw", 0, 0) // R16 -= R16 2B/r -I(SUBrr32 , "subl", 0, 0) // R32 -= R32 2B/r -I(MULrr8 , "mulb", 0, X86II::Void) // AX = AL*R8 F6/4 -I(MULrr16 , "mulw", 0, X86II::Void) // DX:AX= AX*R16 F7/4 -I(MULrr32 , "mull", 0, X86II::Void) // ED:EA= EA*R32 F7/4 +I(ADDrr8 , "addb", 0x00, 0, X86II::MRMDestReg) // R8 += R8 00/r +I(ADDrr16 , "addw", 0x01, 0, X86II::MRMDestReg) // R16 += R16 01/r +I(ADDrr32 , "addl", 0x01, 0, X86II::MRMDestReg) // R32 += R32 01/r +I(SUBrr8 , "subb", 0x2A, 0, X86II::MRMDestReg) // R8 -= R8 2A/r +I(SUBrr16 , "subw", 0x2B, 0, X86II::MRMDestReg) // R16 -= R16 2B/r +I(SUBrr32 , "subl", 0x2B, 0, X86II::MRMDestReg) // R32 -= R32 2B/r +I(MULrr8 , "mulb", 0xF6, 0, X86II::Void) // AX = AL*R8 F6/4 +I(MULrr16 , "mulw", 0xF7, 0, X86II::Void) // DX:AX= AX*R16 F7/4 +I(MULrr32 , "mull", 0xF7, 0, X86II::Void) // ED:EA= EA*R32 F7/4 // unsigned division/remainder -I(DIVrr8 , "divb", 0, X86II::Void) // AX/r8= AL&AH F6/6 -I(DIVrr16 , "divw", 0, X86II::Void) // DA/r16=AX&DX F7/6 -I(DIVrr32 , "divl", 0, X86II::Void) // DA/r32=EAX&DX F7/6 +I(DIVrr8 , "divb", 0xF6, 0, X86II::Void) // AX/r8= AL&AH F6/6 +I(DIVrr16 , "divw", 0xF7, 0, X86II::Void) // DA/r16=AX&DX F7/6 +I(DIVrr32 , "divl", 0xF7, 0, X86II::Void) // DA/r32=EAX&DX F7/6 // signed division/remainder -I(IDIVrr8 , "idivb", 0, X86II::Void) // AX/r8= AL&AH F6/6 -I(IDIVrr16 , "idivw", 0, X86II::Void) // DA/r16=AX&DX F7/6 -I(IDIVrr32 , "idivl", 0, X86II::Void) // DA/r32=EAX&DX F7/6 +I(IDIVrr8 , "idivb", 0xF6, 0, X86II::Void) // AX/r8= AL&AH F6/6 +I(IDIVrr16 , "idivw", 0xF7, 0, X86II::Void) // DA/r16=AX&DX F7/6 +I(IDIVrr32 , "idivl", 0xF7, 0, X86II::Void) // DA/r32=EAX&DX F7/6 // Logical operators -I(ANDrr8 , "andb", 0, 0) // R8 &= R8 20/r -I(ANDrr16 , "andw", 0, 0) // R16 &= R16 21/r -I(ANDrr32 , "andl", 0, 0) // R32 &= R32 21/r -I(ORrr8 , "orb", 0, 0) // R8 |= R8 08/r -I(ORrr16 , "orw", 0, 0) // R16 |= R16 09/r -I(ORrr32 , "orl", 0, 0) // R32 |= R32 09/r -I(XORrr8 , "xorb", 0, 0) // R8 ^= R8 30/r -I(XORrr16 , "xorw", 0, 0) // R16 ^= R16 31/r -I(XORrr32 , "xorl", 0, 0) // R32 ^= R32 31/r +I(ANDrr8 , "andb", 0x20, 0, X86II::MRMDestReg) // R8 &= R8 20/r +I(ANDrr16 , "andw", 0x21, 0, X86II::MRMDestReg) // R16 &= R16 21/r +I(ANDrr32 , "andl", 0x21, 0, X86II::MRMDestReg) // R32 &= R32 21/r +I(ORrr8 , "orb", 0x08, 0, X86II::MRMDestReg) // R8 |= R8 08/r +I(ORrr16 , "orw", 0x09, 0, X86II::MRMDestReg) // R16 |= R16 09/r +I(ORrr32 , "orl", 0x09, 0, X86II::MRMDestReg) // R32 |= R32 09/r +I(XORrr8 , "xorb", 0x30, 0, X86II::MRMDestReg) // R8 ^= R8 30/r +I(XORrr16 , "xorw", 0x31, 0, X86II::MRMDestReg) // R16 ^= R16 31/r +I(XORrr32 , "xorl", 0x31, 0, X86II::MRMDestReg) // R32 ^= R32 31/r // Shift instructions -I(SHLrr8 , "shlb", 0, 0) // R8 <<= cl D2/4 -I(SHLir8 , "shlb", 0, 0) // R8 <<= imm8 C0/4 ib -I(SHLrr16 , "shlw", 0, 0) // R16 <<= cl D3/4 -I(SHLir16 , "shlw", 0, 0) // R16 <<= imm8 C1/4 ib -I(SHLrr32 , "shll", 0, 0) // R32 <<= cl D3/4 -I(SHLir32 , "shll", 0, 0) // R32 <<= imm8 C1/4 ib -I(SHRrr8 , "shrb", 0, 0) // R8 >>>= cl D2/5 -I(SHRir8 , "shrb", 0, 0) // R8 >>>= imm8 C0/5 ib -I(SHRrr16 , "shrw", 0, 0) // R16 >>>= cl D3/5 -I(SHRir16 , "shrw", 0, 0) // R16 >>>= imm8 C1/5 ib -I(SHRrr32 , "shrl", 0, 0) // R32 >>>= cl D3/5 -I(SHRir32 , "shrl", 0, 0) // R32 >>>= imm8 C1/5 ib -I(SARrr8 , "sarb", 0, 0) // R8 >>= cl D2/7 -I(SARir8 , "sarb", 0, 0) // R8 >>= imm8 C0/7 ib -I(SARrr16 , "sarw", 0, 0) // R16 >>= cl D3/7 -I(SARir16 , "sarw", 0, 0) // R16 >>= imm8 C1/7 ib -I(SARrr32 , "sarl", 0, 0) // R32 >>= cl D3/7 -I(SARir32 , "sarl", 0, 0) // R32 >>= imm8 C1/7 ib +I(SHLrr8 , "shlb", 0xD2, 0, 0) // R8 <<= cl D2/4 +I(SHLrr16 , "shlw", 0xD3, 0, 0) // R16 <<= cl D3/4 +I(SHLrr32 , "shll", 0xD3, 0, 0) // R32 <<= cl D3/4 +I(SHLir8 , "shlb", 0xC0, 0, 0) // R8 <<= imm8 C0/4 ib +I(SHLir16 , "shlw", 0xC1, 0, 0) // R16 <<= imm8 C1/4 ib +I(SHLir32 , "shll", 0xC1, 0, 0) // R32 <<= imm8 C1/4 ib +I(SHRrr8 , "shrb", 0xD2, 0, 0) // R8 >>>= cl D2/5 +I(SHRrr16 , "shrw", 0xD3, 0, 0) // R16 >>>= cl D3/5 +I(SHRrr32 , "shrl", 0xD3, 0, 0) // R32 >>>= cl D3/5 +I(SHRir8 , "shrb", 0xC0, 0, 0) // R8 >>>= imm8 C0/5 ib +I(SHRir16 , "shrw", 0xC1, 0, 0) // R16 >>>= imm8 C1/5 ib +I(SHRir32 , "shrl", 0xC1, 0, 0) // R32 >>>= imm8 C1/5 ib +I(SARrr8 , "sarb", 0xD2, 0, 0) // R8 >>= cl D2/7 +I(SARrr16 , "sarw", 0xD3, 0, 0) // R16 >>= cl D3/7 +I(SARrr32 , "sarl", 0xD3, 0, 0) // R32 >>= cl D3/7 +I(SARir8 , "sarb", 0xC0, 0, 0) // R8 >>= imm8 C0/7 ib +I(SARir16 , "sarw", 0xC1, 0, 0) // R16 >>= imm8 C1/7 ib +I(SARir32 , "sarl", 0xC1, 0, 0) // R32 >>= imm8 C1/7 ib // Floating point loads -I(FLDr4 , "flds", 0, X86II::Void) // push float D9/0 -I(FLDr8 , "fldl ", 0, X86II::Void) // push double DD/0 +I(FLDr4 , "flds", 0xD9, 0, X86II::Void) // push float D9/0 +I(FLDr8 , "fldl ", 0xDD, 0, X86II::Void) // push double DD/0 // Floating point compares -I(FUCOMPP , "fucompp", 0, X86II::Void) // compare+pop2x DA E9 +I(FUCOMPP , "fucompp", 0xDA, 0, X86II::Void) // compare+pop2x DA E9 // Floating point flag ops -I(FNSTSWr8 , "fnstsw", 0, X86II::Void) // AX = fp flags DF E0 +I(FNSTSWr8 , "fnstsw", 0xDF, 0, X86II::Void) // AX = fp flags DF E0 // Condition code ops, incl. set if equal/not equal/... -I(SAHF , "sahf", 0, 0) // flags = AH 9E -I(SETA , "seta", 0, X86II::TB) // R8 = > unsign 0F 97 -I(SETAE , "setae", 0, X86II::TB) // R8 = >=unsign 0F 93 -I(SETB , "setb", 0, X86II::TB) // R8 = < unsign 0F 92 -I(SETBE , "setbe", 0, X86II::TB) // R8 = <=unsign 0F 96 -I(SETE , "sete", 0, X86II::TB) // R8 = == 0F 94 -I(SETG , "setg", 0, X86II::TB) // R8 = > signed 0F 9F -I(SETGE , "setge", 0, X86II::TB) // R8 = >=signed 0F 9D -I(SETL , "setl", 0, X86II::TB) // R8 = < signed 0F 9C -I(SETLE , "setle", 0, X86II::TB) // R8 = <=signed 0F 9E -I(SETNE , "setne", 0, X86II::TB) // R8 = != 0F 95 +I(SAHF , "sahf", 0x9E, 0, 0) // flags = AH 9E +I(SETA , "seta", 0x97, 0, X86II::TB) // R8 = > unsign 0F 97 +I(SETAE , "setae", 0x93, 0, X86II::TB) // R8 = >=unsign 0F 93 +I(SETB , "setb", 0x92, 0, X86II::TB) // R8 = < unsign 0F 92 +I(SETBE , "setbe", 0x96, 0, X86II::TB) // R8 = <=unsign 0F 96 +I(SETE , "sete", 0x94, 0, X86II::TB) // R8 = == 0F 94 +I(SETG , "setg", 0x9F, 0, X86II::TB) // R8 = > signed 0F 9F +I(SETGE , "setge", 0x9D, 0, X86II::TB) // R8 = >=signed 0F 9D +I(SETL , "setl", 0x9C, 0, X86II::TB) // R8 = < signed 0F 9C +I(SETLE , "setle", 0x9E, 0, X86II::TB) // R8 = <=signed 0F 9E +I(SETNE , "setne", 0x95, 0, X86II::TB) // R8 = != 0F 95 // Integer comparisons -I(CMPrr8 , "cmpb", 0, 0) // compare R8,R8 38/r -I(CMPrr16 , "cmpw", 0, 0) // compare R16,R16 39/r -I(CMPrr32 , "cmpl", 0, 0) // compare R32,R32 39/r +I(CMPrr8 , "cmpb", 0x38, 0, X86II::MRMDestReg) // compare R8,R8 38/r +I(CMPrr16 , "cmpw", 0x39, 0, X86II::MRMDestReg) // compare R16,R16 39/r +I(CMPrr32 , "cmpl", 0x39, 0, X86II::MRMDestReg) // compare R32,R32 39/r // Sign extenders (first 3 are good for DIV/IDIV; the others are more general) -I(CBW , "cbw", 0, 0) // AX = signext(AL) 98 -I(CWD , "cwd", 0, 0) // DX:AX = signext(AX) 99 -I(CDQ , "cdq", 0, 0) // EDX:EAX = signext(EAX) 99 -I(MOVSXr16r8 , "movsx", 0, X86II::TB) // R32 = signext(R8) 0F BE /r -I(MOVSXr32r8 , "movsx", 0, X86II::TB) // R32 = signext(R8) 0F BE /r -I(MOVSXr32r16 , "movsx", 0, X86II::TB) // R32 = signext(R16) 0F BF /r -I(MOVZXr16r8 , "movzx", 0, X86II::TB) // R32 = zeroext(R8) 0F B6 /r -I(MOVZXr32r8 , "movzx", 0, X86II::TB) // R32 = zeroext(R8) 0F B6 /r -I(MOVZXr32r16 , "movzx", 0, X86II::TB) // R32 = zeroext(R16) 0F B7 /r +I(CBW , "cbw", 0x98, 0, X86II::RawFrm) // AX = signext(AL) +I(CWD , "cwd", 0x99, 0, X86II::RawFrm) // DX:AX = signext(AX) +I(CDQ , "cdq", 0x99, 0, X86II::RawFrm) // EDX:EAX = signext(EAX) +I(MOVSXr16r8 , "movsx", 0xBE, 0, X86II::MRMSrcReg | X86II::TB) // R32 = signext(R8) 0F BE /r +I(MOVSXr32r8 , "movsx", 0xBE, 0, X86II::MRMSrcReg | X86II::TB) // R32 = signext(R8) 0F BE /r +I(MOVSXr32r16 , "movsx", 0xBF, 0, X86II::MRMSrcReg | X86II::TB) // R32 = signext(R16) 0F BF /r +I(MOVZXr16r8 , "movzx", 0xB6, 0, X86II::MRMSrcReg | X86II::TB) // R32 = zeroext(R8) 0F B6 /r +I(MOVZXr32r8 , "movzx", 0xB6, 0, X86II::MRMSrcReg | X86II::TB) // R32 = zeroext(R8) 0F B6 /r +I(MOVZXr32r16 , "movzx", 0xB7, 0, X86II::MRMSrcReg | X86II::TB) // R32 = zeroext(R16) 0F B7 /r // At this point, I is dead, so undefine the macro #undef I Index: llvm/lib/Target/X86/X86InstrInfo.h diff -u llvm/lib/Target/X86/X86InstrInfo.h:1.9 llvm/lib/Target/X86/X86InstrInfo.h:1.10 --- llvm/lib/Target/X86/X86InstrInfo.h:1.9 Sun Nov 17 19:59:28 2002 +++ llvm/lib/Target/X86/X86InstrInfo.h Sun Nov 17 23:37:11 2002 @@ -15,14 +15,55 @@ /// namespace X86II { enum { + //===------------------------------------------------------------------===// + // Instruction types. These are the standard/most common forms for X86 + // instructions. + // + + /// Other - An instruction gets this form if it doesn't fit any of the + /// catagories below. + OtherFrm = 0, + + /// Raw - This form is for instructions that don't have any operands, so + /// they are just a fixed opcode value, like 'leave'. + RawFrm = 1, + + /// AddRegFrm - This form is used for instructions like 'push r32' that have + /// their one register operand added to their opcode. + AddRegFrm = 2, + + /// MRMDestReg - This form is used for instructions that use the Mod/RM byte + /// to specify a destination, which in this case is a register. + /// + MRMDestReg = 3, + + /// MRMDestMem - This form is used for instructions that use the Mod/RM byte + /// to specify a destination, which in this case is memory. + /// + MRMDestMem = 4, + + /// MRMSrcReg - This form is used for instructions that use the Mod/RM byte + /// to specify a source, which in this case is a register. + /// + MRMSrcReg = 5, + + /// MRMSrcMem - This form is used for instructions that use the Mod/RM byte + /// to specify a source, which in this case is memory. + /// + MRMSrcMem = 6, + + /// TODO: Mod/RM that uses a fixed opcode extension, like /0 + + + //===------------------------------------------------------------------===// + // Actual flags... + /// Void - Set if this instruction produces no value - Void = 1 << 0, + Void = 1 << 3, // TB - TwoByte - Set if this instruction has a two byte opcode, which // starts with a 0x0F byte before the real opcode. - TB = 1 << 1, - - + TB = 1 << 4, }; }
OptimizerEvalXXOIt is a timing test, so not matching is expected.
sgefaXXOBoth native and CBE seg fault
simXXO
Ptrdist-bcOOOBytecode fails to be generated
Ptrdist-ftOOOBytecode fails to be generated
Ptrdist-bcOXOBytecode fails to be generated in our test framework
Ptrdist-ftOXOBytecode fails to be generated in our test framework
Ptrdist-ksXXX
Ptrdist-yacr2XXONative seg faults, not 64 friendly