From lattner at cs.uiuc.edu Mon Dec 23 17:45:01 2002 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Mon Dec 23 17:45:01 2002 Subject: [llvm-commits] CVS: llvm/lib/CodeGen/RegAllocSimple.cpp Message-ID: <200212232344.RAA00791@apoc.cs.uiuc.edu> Changes in directory llvm/lib/CodeGen: RegAllocSimple.cpp updated: 1.32 -> 1.33 --- Log message: Fix compilation on GCC 2.96 --- Diffs of the changes: Index: llvm/lib/CodeGen/RegAllocSimple.cpp diff -u llvm/lib/CodeGen/RegAllocSimple.cpp:1.32 llvm/lib/CodeGen/RegAllocSimple.cpp:1.33 --- llvm/lib/CodeGen/RegAllocSimple.cpp:1.32 Tue Dec 17 19:11:14 2002 +++ llvm/lib/CodeGen/RegAllocSimple.cpp Mon Dec 23 17:44:04 2002 @@ -346,7 +346,7 @@ /// void RegAllocSimple::EmitEpilogue(MachineBasicBlock &MBB) { // Insert instructions before the return. - MachineBasicBlock::iterator I = --MBB.end(); + MachineBasicBlock::iterator I = MBB.end()-1; const unsigned *CSRegs = RegInfo->getCalleeSaveRegs(); for (unsigned i = 0; CSRegs[i]; ++i) { From lattner at cs.uiuc.edu Mon Dec 23 17:47:01 2002 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Mon Dec 23 17:47:01 2002 Subject: [llvm-commits] CVS: llvm/lib/Target/X86/MachineCodeEmitter.cpp Printer.cpp Message-ID: <200212232346.RAA00809@apoc.cs.uiuc.edu> Changes in directory llvm/lib/Target/X86: MachineCodeEmitter.cpp updated: 1.14 -> 1.15 Printer.cpp updated: 1.29 -> 1.30 --- Log message: Add support for the bswap instruction --- Diffs of the changes: Index: llvm/lib/Target/X86/MachineCodeEmitter.cpp diff -u llvm/lib/Target/X86/MachineCodeEmitter.cpp:1.14 llvm/lib/Target/X86/MachineCodeEmitter.cpp:1.15 --- llvm/lib/Target/X86/MachineCodeEmitter.cpp:1.14 Thu Dec 19 22:12:48 2002 +++ llvm/lib/Target/X86/MachineCodeEmitter.cpp Mon Dec 23 17:46:00 2002 @@ -238,7 +238,8 @@ break; case X86II::AddRegFrm: MCE.emitByte(BaseOpcode + getX86RegNum(MI.getOperand(0).getReg())); - if (MI.getNumOperands() == 2) { + if (MI.getNumOperands() == 2 && (MI.getOperand(1).isImmediate() || + MI.getOperand(1).getVRegValueOrNull())) { unsigned Size = sizeOfPtr(Desc); if (Value *V = MI.getOperand(1).getVRegValueOrNull()) { assert(Size == 4 && "Don't know how to emit non-pointer values!"); Index: llvm/lib/Target/X86/Printer.cpp diff -u llvm/lib/Target/X86/Printer.cpp:1.29 llvm/lib/Target/X86/Printer.cpp:1.30 --- llvm/lib/Target/X86/Printer.cpp:1.29 Sun Dec 15 15:13:40 2002 +++ llvm/lib/Target/X86/Printer.cpp Mon Dec 23 17:46:00 2002 @@ -196,20 +196,22 @@ // or it takes a register and an immediate of the same size as the register // (move immediate f.e.). Note that this immediate value might be stored as // an LLVM value, to represent, for example, loading the address of a global - // into a register. + // into a register. The initial register might be duplicated if this is a + // M_2_ADDR_REG instruction // assert(MI->getOperand(0).isRegister() && (MI->getNumOperands() == 1 || (MI->getNumOperands() == 2 && (MI->getOperand(1).getVRegValueOrNull() || - MI->getOperand(1).isImmediate()))) && + MI->getOperand(1).isImmediate() || + MI->getOperand(1).isRegister()))) && "Illegal form for AddRegFrm instruction!"); unsigned Reg = MI->getOperand(0).getReg(); O << getName(MI->getOpCode()) << " "; printOp(O, MI->getOperand(0), RI); - if (MI->getNumOperands() == 2) { + if (MI->getNumOperands() == 2 && !MI->getOperand(1).isRegister()) { O << ", "; printOp(O, MI->getOperand(1), RI); } From lattner at cs.uiuc.edu Mon Dec 23 17:47:02 2002 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Mon Dec 23 17:47:02 2002 Subject: [llvm-commits] CVS: llvm/lib/Target/X86/X86InstrInfo.def Message-ID: <200212232346.RAA00820@apoc.cs.uiuc.edu> Changes in directory llvm/lib/Target/X86: X86InstrInfo.def updated: 1.44 -> 1.45 --- Log message: Add definition for the bswap instruction *** FIX: the encoding of the SUB instruction --- Diffs of the changes: Index: llvm/lib/Target/X86/X86InstrInfo.def diff -u llvm/lib/Target/X86/X86InstrInfo.def:1.44 llvm/lib/Target/X86/X86InstrInfo.def:1.45 --- llvm/lib/Target/X86/X86InstrInfo.def:1.44 Thu Dec 19 22:13:11 2002 +++ llvm/lib/Target/X86/X86InstrInfo.def Mon Dec 23 17:46:31 2002 @@ -73,6 +73,10 @@ // Misc instructions I(LEAVE , "leave", 0xC9, 0, X86II::RawFrm, O_EBP, O_EBP) // leave +I(BSWAPr32 , "bswap", 0xC8, M_2_ADDR_FLAG, X86II::AddRegFrm | X86II::TB | + X86II::Arg32, NoIR, NoIR) // R32 = bswap R32 +I(BSWAPr16 , "bswap", 0xC8, M_2_ADDR_FLAG, X86II::AddRegFrm | X86II::TB | + X86II::OpSize | X86II::Arg16, NoIR, NoIR) // R16 = bswap R16 // Move instructions I(MOVrr8 , "movb", 0x88, 0, X86II::MRMDestReg, NoIR, NoIR) // R8 = R8 @@ -100,9 +104,9 @@ I(ADDrr16 , "addw", 0x01, M_2_ADDR_FLAG, X86II::MRMDestReg | X86II::OpSize, NoIR, NoIR) // R16 += R16 I(ADDrr32 , "addl", 0x01, M_2_ADDR_FLAG, X86II::MRMDestReg, NoIR, NoIR) // R32 += R32 I(ADDri32 , "add", 0x81, M_2_ADDR_FLAG, X86II::MRMS0r | X86II::Arg32, NoIR, NoIR) // R32 += imm32 -I(SUBrr8 , "subb", 0x2A, M_2_ADDR_FLAG, X86II::MRMDestReg, NoIR, NoIR) // R8 -= R8 -I(SUBrr16 , "subw", 0x2B, M_2_ADDR_FLAG, X86II::MRMDestReg | X86II::OpSize, NoIR, NoIR) // R16 -= R16 -I(SUBrr32 , "subl", 0x2B, M_2_ADDR_FLAG, X86II::MRMDestReg, NoIR, NoIR) // R32 -= R32 +I(SUBrr8 , "subb", 0x28, M_2_ADDR_FLAG, X86II::MRMDestReg, NoIR, NoIR) // R8 -= R8 +I(SUBrr16 , "subw", 0x29, M_2_ADDR_FLAG, X86II::MRMDestReg | X86II::OpSize, NoIR, NoIR) // R16 -= R16 +I(SUBrr32 , "subl", 0x29, M_2_ADDR_FLAG, X86II::MRMDestReg, NoIR, NoIR) // R32 -= R32 I(SUBri32 , "sub", 0x81, M_2_ADDR_FLAG, X86II::MRMS5r | X86II::Arg32, NoIR, NoIR) // R32 -= imm32 I(MULrr8 , "mulb", 0xF6, 0, X86II::MRMS4r | X86II::Void, O_AL, O_AX) // AX = AL*R8 I(MULrr16 , "mulw", 0xF7, 0, X86II::MRMS4r | X86II::Void | // DX:AX= AX*R16 From lattner at cs.uiuc.edu Mon Dec 23 17:48:01 2002 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Mon Dec 23 17:48:01 2002 Subject: [llvm-commits] CVS: llvm/lib/Target/X86/X86RegisterInfo.cpp Message-ID: <200212232347.RAA00836@apoc.cs.uiuc.edu> Changes in directory llvm/lib/Target/X86: X86RegisterInfo.cpp updated: 1.23 -> 1.24 --- Log message: Fix compilation on gcc 2.96 --- Diffs of the changes: Index: llvm/lib/Target/X86/X86RegisterInfo.cpp diff -u llvm/lib/Target/X86/X86RegisterInfo.cpp:1.23 llvm/lib/Target/X86/X86RegisterInfo.cpp:1.24 --- llvm/lib/Target/X86/X86RegisterInfo.cpp:1.23 Thu Dec 19 22:13:28 2002 +++ llvm/lib/Target/X86/X86RegisterInfo.cpp Mon Dec 23 17:46:55 2002 @@ -33,7 +33,7 @@ static const unsigned Opcode[] = { X86::MOVrm8, X86::MOVrm16, X86::MOVrm32 }; MachineInstr *MI = addRegOffset(BuildMI(Opcode[getIdx(dataSize)], 5), DestReg, ImmOffset).addReg(SrcReg); - return ++MBB.insert(MBBI, MI); + return MBB.insert(MBBI, MI)+1; } MachineBasicBlock::iterator @@ -46,7 +46,7 @@ static const unsigned Opcode[] = { X86::MOVmr8, X86::MOVmr16, X86::MOVmr32 }; MachineInstr *MI = addRegOffset(BuildMI(Opcode[getIdx(dataSize)], 4, DestReg), SrcReg, ImmOffset); - return ++MBB.insert(MBBI, MI); + return MBB.insert(MBBI, MI)+1; } MachineBasicBlock::iterator @@ -57,7 +57,7 @@ { static const unsigned Opcode[] = { X86::MOVrr8, X86::MOVrr16, X86::MOVrr32 }; MachineInstr *MI = BuildMI(Opcode[getIdx(dataSize)],1,DestReg).addReg(SrcReg); - return ++MBB.insert(MBBI, MI); + return MBB.insert(MBBI, MI)+1; } MachineBasicBlock::iterator @@ -68,7 +68,7 @@ { static const unsigned Opcode[] = { X86::MOVir8, X86::MOVir16, X86::MOVir32 }; MachineInstr *MI = BuildMI(Opcode[getIdx(dataSize)], 1, DestReg).addReg(Imm); - return ++MBB.insert(MBBI, MI); + return MBB.insert(MBBI, MI)+1; } @@ -103,24 +103,24 @@ // PUSH ebp MachineInstr *MI = BuildMI(X86::PUSHr32, 1).addReg(X86::EBP); - MBBI = ++MBB.insert(MBBI, MI); + MBBI = MBB.insert(MBBI, MI)+1; // MOV ebp, esp MI = BuildMI(X86::MOVrr32, 1, X86::EBP).addReg(X86::ESP); - MBBI = ++MBB.insert(MBBI, MI); + MBBI = MBB.insert(MBBI, MI)+1; // adjust stack pointer: ESP -= numbytes MI = BuildMI(X86::SUBri32, 2, X86::ESP).addReg(X86::ESP).addZImm(NumBytes); - MBBI = ++MBB.insert(MBBI, MI); + MBBI = 1+MBB.insert(MBBI, MI); } void X86RegisterInfo::emitEpilogue(MachineBasicBlock &MBB, unsigned numBytes) const { - MachineBasicBlock::iterator MBBI = --MBB.end(); + MachineBasicBlock::iterator MBBI = MBB.end()-1; assert((*MBBI)->getOpcode() == X86::RET && "Can only insert epilog into returning blocks"); // insert LEAVE: mov ESP, EBP; pop EBP - MBBI = ++MBB.insert(MBBI, BuildMI(X86::MOVrr32, 1,X86::ESP).addReg(X86::EBP)); - MBBI = ++MBB.insert(MBBI, BuildMI(X86::POPr32, 1).addReg(X86::EBP)); + MBBI = 1+MBB.insert(MBBI, BuildMI(X86::MOVrr32, 1,X86::ESP).addReg(X86::EBP)); + MBBI = 1+MBB.insert(MBBI, BuildMI(X86::POPr32, 1).addReg(X86::EBP)); } From lattner at cs.uiuc.edu Mon Dec 23 17:48:01 2002 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Mon Dec 23 17:48:01 2002 Subject: [llvm-commits] CVS: llvm/test/Makefile.tests Message-ID: <200212232347.RAA00847@apoc.cs.uiuc.edu> Changes in directory llvm/test: Makefile.tests updated: 1.50 -> 1.51 --- Log message: Jello is going away --- Diffs of the changes: Index: llvm/test/Makefile.tests diff -u llvm/test/Makefile.tests:1.50 llvm/test/Makefile.tests:1.51 --- llvm/test/Makefile.tests:1.50 Tue Nov 19 15:57:18 2002 +++ llvm/test/Makefile.tests Mon Dec 23 17:47:20 2002 @@ -43,7 +43,6 @@ LOPT = $(TOOLS)/opt LLINK = $(TOOLS)/link LANALYZE = $(TOOLS)/analyze -LJELLO = $(TOOLS)/jello LBUGPOINT= $(TOOLS)/bugpoint LCCFLAGS += -O2 -Wall From lattner at cs.uiuc.edu Mon Dec 23 17:48:02 2002 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Mon Dec 23 17:48:02 2002 Subject: [llvm-commits] CVS: llvm/test/Regression/BugPoint/Makefile Message-ID: <200212232347.RAA00860@apoc.cs.uiuc.edu> Changes in directory llvm/test/Regression/BugPoint: Makefile updated: 1.1 -> 1.2 --- Log message: Remove temp files --- Diffs of the changes: Index: llvm/test/Regression/BugPoint/Makefile diff -u llvm/test/Regression/BugPoint/Makefile:1.1 llvm/test/Regression/BugPoint/Makefile:1.2 --- llvm/test/Regression/BugPoint/Makefile:1.1 Wed Nov 20 16:30:01 2002 +++ llvm/test/Regression/BugPoint/Makefile Mon Dec 23 17:47:39 2002 @@ -12,6 +12,8 @@ Output/%.ll.out: %.ll Output/.dir $(LAS) $(LBUGPOINT) -$(TESTRUNR) $< + -# Remove temporary files generated... + @rm -f bugpoint-$<-* clean:: rm -f *.bc From lattner at cs.uiuc.edu Mon Dec 23 17:51:01 2002 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Mon Dec 23 17:51:01 2002 Subject: [llvm-commits] CVS: llvm/tools/bugpoint/BugDriver.cpp BugDriver.h CrashDebugger.cpp Makefile OptimizerDriver.cpp Message-ID: <200212232350.RAA00886@apoc.cs.uiuc.edu> Changes in directory llvm/tools/bugpoint: BugDriver.cpp updated: 1.1 -> 1.2 BugDriver.h updated: 1.1 -> 1.2 CrashDebugger.cpp updated: 1.1 -> 1.2 Makefile updated: 1.1 -> 1.2 OptimizerDriver.cpp updated: 1.1 -> 1.2 --- Log message: Implement the start of the miscompilation detection stuff --- Diffs of the changes: Index: llvm/tools/bugpoint/BugDriver.cpp diff -u llvm/tools/bugpoint/BugDriver.cpp:1.1 llvm/tools/bugpoint/BugDriver.cpp:1.2 --- llvm/tools/bugpoint/BugDriver.cpp:1.1 Wed Nov 20 16:28:10 2002 +++ llvm/tools/bugpoint/BugDriver.cpp Mon Dec 23 17:49:59 2002 @@ -82,19 +82,3 @@ else return debugMiscompilation(); } - - -/// debugMiscompilation - This method is used when the passes selected are not -/// crashing, but the generated output is semantically different from the -/// input. -/// -bool BugDriver::debugMiscompilation() { - std::cout << "*** Debugging miscompilation!\n"; - std::cerr << "Sorry, bugpoint cannot debug a miscompilation yet!\n"; - - // If no reference output was specified, run the program without optimizations - // to get a reference output. - // - - return true; -} Index: llvm/tools/bugpoint/BugDriver.h diff -u llvm/tools/bugpoint/BugDriver.h:1.1 llvm/tools/bugpoint/BugDriver.h:1.2 --- llvm/tools/bugpoint/BugDriver.h:1.1 Wed Nov 20 16:28:10 2002 +++ llvm/tools/bugpoint/BugDriver.h Mon Dec 23 17:49:59 2002 @@ -14,13 +14,18 @@ class PassInfo; class Module; class Function; +class AbstractInterpreter; class BugDriver { const std::string ToolName; // Name of bugpoint Module *Program; // The raw program, linked together std::vector PassesToRun; + AbstractInterpreter *Interpreter; // How to run the program public: - BugDriver(const char *toolname) : ToolName(toolname), Program(0) {} + BugDriver(const char *toolname) + : ToolName(toolname), Program(0), Interpreter(0) {} + + const std::string &getToolName() const { return ToolName; } // Set up methods... these methods are used to copy information about the // command line arguments into instance variables of BugDriver. @@ -51,20 +56,25 @@ /// input. bool debugMiscompilation(); + /// debugPassMiscompilation - This method is called when the specified pass + /// miscompiles Program as input. It tries to reduce the testcase to + /// something that smaller that still miscompiles the program. + /// ReferenceOutput contains the filename of the file containing the output we + /// are to match. + /// + bool debugPassMiscompilation(const PassInfo *ThePass, + const std::string &ReferenceOutput); + private: /// ParseInputFile - Given a bytecode or assembly input filename, parse and /// return it, or return null if not possible. /// Module *ParseInputFile(const std::string &InputFilename) const; - /// removeFile - Delete the specified file - /// - void removeFile(const std::string &Filename) const; - /// writeProgramToFile - This writes the current "Program" to the named /// bytecode file. If an error occurs, true is returned. /// - bool writeProgramToFile(const std::string &Filename) const; + bool writeProgramToFile(const std::string &Filename, Module *M = 0) const; /// EmitProgressBytecode - This function is used to output the current Program @@ -78,10 +88,11 @@ /// otherwise return false. If DeleteOutput is set to true, the bytecode is /// deleted on success, and the filename string is undefined. This prints to /// cout a single line message indicating whether compilation was successful - /// or failed. + /// or failed, unless Quiet is set. /// bool runPasses(const std::vector &PassesToRun, - std::string &OutputFilename, bool DeleteOutput = false) const; + std::string &OutputFilename, bool DeleteOutput = false, + bool Quiet = false) const; /// runPasses - Just like the method above, but this just returns true or /// false indicating whether or not the optimizer crashed on the specified @@ -94,6 +105,7 @@ } /// runPass - Run only the specified pass on the program. + /// bool runPass(const PassInfo *P, bool DeleteOutput = true) const { return runPasses(std::vector(1, P), DeleteOutput); } @@ -102,8 +114,27 @@ /// (non-external) function from the current program, slim down the module, /// and then return it. This does not modify Program at all, it modifies a /// copy, which it returns. + /// Module *extractFunctionFromModule(Function *F) const; + /// initializeExecutionEnvironment - This method is used to set up the + /// environment for executing LLVM programs. + /// + bool initializeExecutionEnvironment(); + + /// executeProgram - This method runs "Program", capturing the output of the + /// program to a file, returning the filename of the file. A recommended + /// filename may be optionally specified. + /// + std::string executeProgram(std::string RequestedOutputFilename = "", + std::string Bytecode = ""); + + /// diffProgram - This method executes the specified module and diffs the + /// output against the file specified by ReferenceOutputFile. If the output + /// is different, true is returned. + /// + bool diffProgram(const std::string &ReferenceOutputFile, + const std::string &BytecodeFile = ""); }; #endif Index: llvm/tools/bugpoint/CrashDebugger.cpp diff -u llvm/tools/bugpoint/CrashDebugger.cpp:1.1 llvm/tools/bugpoint/CrashDebugger.cpp:1.2 --- llvm/tools/bugpoint/CrashDebugger.cpp:1.1 Wed Nov 20 16:28:10 2002 +++ llvm/tools/bugpoint/CrashDebugger.cpp Mon Dec 23 17:49:59 2002 @@ -5,6 +5,7 @@ //===----------------------------------------------------------------------===// #include "BugDriver.h" +#include "SystemUtils.h" #include "llvm/Module.h" #include "llvm/Bytecode/Writer.h" #include "llvm/Pass.h" @@ -44,8 +45,7 @@ << "': " << CrashingPass->getPassName() << "\n"; // Compile the program with just the passes that don't crash. - if (LastToPass != 0) { - // Don't bother doing this if the first pass crashes... + if (LastToPass != 0) { // Don't bother doing this if the first pass crashes... std::vector P(PassesToRun.begin(), PassesToRun.begin()+LastToPass); std::string Filename; @@ -87,7 +87,7 @@ if (CountFunctions(Program) > 1) { // Attempt to reduce the input program down to a single function that still - // crashes. + // crashes. Do this by removing everything except for that one function... // std::cout << "\n*** Attempting to reduce the testcase to one function\n"; @@ -116,5 +116,16 @@ } } + if (CountFunctions(Program) > 1) { + std::cout << "\n*** Couldn't reduce testcase to one function.\n" + << " Attempting to remove individual functions.\n"; + std::cout << "XXX Individual function removal unimplemented!\n"; + } + + // Now that we have deleted the functions that are unneccesary for the + // program, try to remove instructions and basic blocks that are not neccesary + // to cause the crash. + // + return false; } Index: llvm/tools/bugpoint/Makefile diff -u llvm/tools/bugpoint/Makefile:1.1 llvm/tools/bugpoint/Makefile:1.2 --- llvm/tools/bugpoint/Makefile:1.1 Wed Nov 20 16:28:10 2002 +++ llvm/tools/bugpoint/Makefile Mon Dec 23 17:49:59 2002 @@ -2,10 +2,10 @@ TOOLNAME = bugpoint -OPTLIBS = instrument profpaths scalaropts ipo -ANALIBS = datastructure ipa target.a analysis +#OPTLIBS = instrument profpaths +ANALIBS = datastructure ipa target.a -USEDLIBS = ipo scalaropts $(ANALIBS) \ +USEDLIBS = ipo scalaropts analysis $(OPTLIBS) $(ANALIBS) \ transformutils asmparser bcreader bcwriter vmcore support TOOLLINKOPTS = -ldl Index: llvm/tools/bugpoint/OptimizerDriver.cpp diff -u llvm/tools/bugpoint/OptimizerDriver.cpp:1.1 llvm/tools/bugpoint/OptimizerDriver.cpp:1.2 --- llvm/tools/bugpoint/OptimizerDriver.cpp:1.1 Wed Nov 20 16:28:10 2002 +++ llvm/tools/bugpoint/OptimizerDriver.cpp Mon Dec 23 17:49:59 2002 @@ -9,6 +9,7 @@ //===----------------------------------------------------------------------===// #include "BugDriver.h" +#include "SystemUtils.h" #include "llvm/PassManager.h" #include "llvm/Analysis/Verifier.h" #include "llvm/Bytecode/WriteBytecodePass.h" @@ -18,20 +19,14 @@ #include #include -/// removeFile - Delete the specified file -/// -void BugDriver::removeFile(const std::string &Filename) const { - unlink(Filename.c_str()); -} - /// writeProgramToFile - This writes the current "Program" to the named bytecode /// file. If an error occurs, true is returned. /// -bool BugDriver::writeProgramToFile(const std::string &Filename) const { +bool BugDriver::writeProgramToFile(const std::string &Filename, + Module *M) const { std::ofstream Out(Filename.c_str()); if (!Out.good()) return true; - - WriteBytecodeToFile(Program, Out); + WriteBytecodeToFile(M ? M : Program, Out); return false; } @@ -50,7 +45,7 @@ return; } - std::cout << "Emitted bytecode to 'bugpoint-" << Filename << ".bc'\n"; + std::cout << "Emitted bytecode to '" << Filename << "'\n"; std::cout << "\n*** You can reproduce the problem with: "; unsigned PassType = Pass->getPassType(); @@ -101,23 +96,11 @@ /// failed. /// bool BugDriver::runPasses(const std::vector &Passes, - std::string &OutputFilename, bool DeleteOutput) const{ + std::string &OutputFilename, bool DeleteOutput, + bool Quiet) const{ std::cout << std::flush; + OutputFilename = getUniqueFilename("bugpoint-output.bc"); - // Agree on a temporary file name to use.... - char FNBuffer[] = "bugpoint-output.bc-XXXXXX"; - int TempFD; - if ((TempFD = mkstemp(FNBuffer)) == -1) { - std::cerr << ToolName << ": ERROR: Cannot create temporary" - << " file in the current directory!\n"; - exit(1); - } - OutputFilename = FNBuffer; - - // We don't need to hold the temp file descriptor... we will trust that noone - // will overwrite/delete the file while we are working on it... - close(TempFD); - pid_t child_pid; switch (child_pid = fork()) { case -1: // Error occurred @@ -143,7 +126,7 @@ if (DeleteOutput) removeFile(OutputFilename); - std::cout << (Status ? "Crashed!\n" : "Success!\n"); + if (!Quiet) std::cout << (Status ? "Crashed!\n" : "Success!\n"); // Was the child successful? return Status != 0; From lattner at cs.uiuc.edu Mon Dec 23 17:51:02 2002 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Mon Dec 23 17:51:02 2002 Subject: [llvm-commits] CVS: llvm/tools/bugpoint/ExecutionDriver.cpp Miscompilation.cpp SystemUtils.cpp SystemUtils.h Message-ID: <200212232350.RAA00898@apoc.cs.uiuc.edu> Changes in directory llvm/tools/bugpoint: ExecutionDriver.cpp added (r1.1) Miscompilation.cpp added (r1.1) SystemUtils.cpp added (r1.1) SystemUtils.h added (r1.1) --- Log message: New files for miscompilation detection --- Diffs of the changes: From lattner at cs.uiuc.edu Mon Dec 23 17:51:02 2002 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Mon Dec 23 17:51:02 2002 Subject: [llvm-commits] CVS: llvm/test/Regression/BugPoint/misopt-basictest.ll Message-ID: <200212232350.RAA00913@apoc.cs.uiuc.edu> Changes in directory llvm/test/Regression/BugPoint: misopt-basictest.ll added (r1.1) --- Log message: New testcase --- Diffs of the changes: From lattner at cs.uiuc.edu Mon Dec 23 17:52:01 2002 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Mon Dec 23 17:52:01 2002 Subject: [llvm-commits] CVS: llvm/test/Regression/Jello/2002-12-23-LocalRAProblem.llx 2002-12-23-SubProblem.llx Message-ID: <200212232351.RAA00938@apoc.cs.uiuc.edu> Changes in directory llvm/test/Regression/Jello: 2002-12-23-LocalRAProblem.llx added (r1.1) 2002-12-23-SubProblem.llx added (r1.1) --- Log message: Testcases for bugfixes --- Diffs of the changes: From lattner at cs.uiuc.edu Mon Dec 23 17:52:02 2002 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Mon Dec 23 17:52:02 2002 Subject: [llvm-commits] CVS: llvm/test/Regression/Jello/Makefile Message-ID: <200212232351.RAA00955@apoc.cs.uiuc.edu> Changes in directory llvm/test/Regression/Jello: Makefile updated: 1.3 -> 1.4 --- Log message: Jello is now part of LLI --- Diffs of the changes: Index: llvm/test/Regression/Jello/Makefile diff -u llvm/test/Regression/Jello/Makefile:1.3 llvm/test/Regression/Jello/Makefile:1.4 --- llvm/test/Regression/Jello/Makefile:1.3 Thu Dec 19 22:14:19 2002 +++ llvm/test/Regression/Jello/Makefile Mon Dec 23 17:51:19 2002 @@ -1,6 +1,6 @@ # test/Regression/Jello/Makefile # -# This directory contains regression tests for the LLVM jello program. +# This directory contains regression tests for the LLVM x86 JIT # LEVEL = ../../.. include $(LEVEL)/test/Makefile.tests @@ -10,9 +10,9 @@ all:: $(addprefix Output/, $(TESTS:%.ll=%.out)) -Output/%.out: Output/%.bc $(LJELLO) +Output/%.out: Output/%.bc $(LLI) @echo "======== Running $< ===================" - $(VERB) jello -stats $< > $@ 2>&1 || \ + $(VERB) $(LLI) -force-interpreter=false -stats $< > $@ 2>&1 || \ ( cat $@; rm -f $@; $(FAILURE) $@ ) From lattner at cs.uiuc.edu Mon Dec 23 17:56:01 2002 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Mon Dec 23 17:56:01 2002 Subject: [llvm-commits] CVS: llvm/tools/jello/jello.cpp Message-ID: <200212232355.RAA02518@apoc.cs.uiuc.edu> Changes in directory llvm/tools/jello: jello.cpp updated: 1.9 -> 1.10 --- Log message: X86 target machine is now parameterizable --- Diffs of the changes: Index: llvm/tools/jello/jello.cpp diff -u llvm/tools/jello/jello.cpp:1.9 llvm/tools/jello/jello.cpp:1.10 --- llvm/tools/jello/jello.cpp:1.9 Fri Dec 13 10:48:57 2002 +++ llvm/tools/jello/jello.cpp Mon Dec 23 17:55:01 2002 @@ -11,6 +11,7 @@ #include "llvm/Target/TargetMachineImpls.h" #include "Support/CommandLine.h" #include "VM.h" +#include namespace { cl::opt @@ -32,7 +33,8 @@ // Allocate a target... in the future this will be controllable on the // command line. - std::auto_ptr Target(allocateX86TargetMachine()); + std::auto_ptr Target( + allocateX86TargetMachine(TM::PtrSize64 | TM::BigEndian)); assert(Target.get() && "Could not allocate target machine!"); // Parse the input bytecode file... From lattner at cs.uiuc.edu Mon Dec 23 17:57:01 2002 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Mon Dec 23 17:57:01 2002 Subject: [llvm-commits] CVS: llvm/tools/lli/Interpreter/ Message-ID: <200212232356.RAA03047@apoc.cs.uiuc.edu> Changes in directory llvm/tools/lli/Interpreter: --- Log message: Directory /home/vadve/vadve/Research/DynOpt/CVSRepository/llvm/tools/lli/Interpreter added to the repository --- Diffs of the changes: From lattner at cs.uiuc.edu Mon Dec 23 18:00:01 2002 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Mon Dec 23 18:00:01 2002 Subject: [llvm-commits] CVS: llvm/tools/lli/JIT/ Message-ID: <200212232359.RAA04660@apoc.cs.uiuc.edu> Changes in directory llvm/tools/lli/JIT: --- Log message: Directory /home/vadve/vadve/Research/DynOpt/CVSRepository/llvm/tools/lli/JIT added to the repository --- Diffs of the changes: From lattner at cs.uiuc.edu Mon Dec 23 18:00:02 2002 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Mon Dec 23 18:00:02 2002 Subject: [llvm-commits] CVS: llvm/tools/lli/Makefile lli.cpp Message-ID: <200212232359.RAA04704@apoc.cs.uiuc.edu> Changes in directory llvm/tools/lli: Makefile updated: 1.18 -> 1.19 lli.cpp updated: 1.13 -> 1.14 --- Log message: Substantial changes to refactor LLI to incorporate both the Jello JIT and the traditional LLI interpreter --- Diffs of the changes: Index: llvm/tools/lli/Makefile diff -u llvm/tools/lli/Makefile:1.18 llvm/tools/lli/Makefile:1.19 --- llvm/tools/lli/Makefile:1.18 Mon Nov 4 14:50:56 2002 +++ llvm/tools/lli/Makefile Mon Dec 23 17:59:32 2002 @@ -1,6 +1,10 @@ LEVEL = ../.. TOOLNAME = lli -USEDLIBS = bcreader vmcore analysis.a support.a target.a transforms.a +PARALLEL_DIRS = Interpreter JIT + +JITLIBS = lli-jit codegen x86 scalaropts.a +USEDLIBS = lli-interpreter $(JITLIBS) bcreader vmcore analysis.a support.a target.a +#transforms.a # Have gcc tell the linker to export symbols from the program so that # dynamically loaded modules can be linked against them. Index: llvm/tools/lli/lli.cpp diff -u llvm/tools/lli/lli.cpp:1.13 llvm/tools/lli/lli.cpp:1.14 --- llvm/tools/lli/lli.cpp:1.13 Sat Dec 7 23:51:08 2002 +++ llvm/tools/lli/lli.cpp Mon Dec 23 17:59:32 2002 @@ -1,85 +1,101 @@ -//===----------------------------------------------------------------------===// -// LLVM INTERPRETER/DEBUGGER/PROFILER UTILITY +//===- lli.cpp - LLVM Interpreter / Dynamic compiler ----------------------===// // -// This utility is an interactive frontend to almost all other LLVM -// functionality. It may be used as an interpreter to run code, a debugger to -// find problems, or a profiler to analyze execution frequencies. +// This utility provides a way to execute LLVM bytecode without static +// compilation. This consists of a very simple and slow (but portable) +// interpreter, along with capability for system specific dynamic compilers. At +// runtime, the fastest (stable) execution engine is selected to run the +// program. This means the JIT compiler for the current platform if it's +// available. // //===----------------------------------------------------------------------===// -#include "Interpreter.h" +#include "ExecutionEngine.h" #include "Support/CommandLine.h" +#include "llvm/Bytecode/Reader.h" +#include "llvm/Module.h" +#include "llvm/Target/TargetMachineImpls.h" -static cl::opt -InputFile(cl::desc(""), cl::Positional, cl::init("-")); - -static cl::list -InputArgv(cl::ConsumeAfter, cl::desc("...")); +namespace { + cl::opt + InputFile(cl::desc(""), cl::Positional, cl::init("-")); -static cl::opt -MainFunction ("f", cl::desc("Function to execute"), cl::init("main"), - cl::value_desc("function name")); + cl::list + InputArgv(cl::ConsumeAfter, cl::desc("...")); -static cl::opt -DebugMode("d", cl::desc("Start program in debugger")); + cl::opt + MainFunction ("f", cl::desc("Function to execute"), cl::init("main"), + cl::value_desc("function name")); -static cl::opt -TraceMode("trace", cl::desc("Enable Tracing")); + cl::opt DebugMode("d", cl::desc("Start program in debugger")); -static cl::opt -ProfileMode("profile", cl::desc("Enable Profiling [unimp]")); + cl::opt TraceMode("trace", cl::desc("Enable Tracing")); + cl::opt ForceInterpreter("force-interpreter", + cl::desc("Force interpretation: disable JIT"), + cl::init(true)); +} //===----------------------------------------------------------------------===// -// Interpreter ctor - Initialize stuff +// ExecutionEngine Class Implementation // -Interpreter::Interpreter() : ExitCode(0), Profile(ProfileMode), - Trace(TraceMode), CurFrame(-1) { - CurMod = 0; - loadModule(InputFile); - - // Initialize the "backend" - initializeExecutionEngine(); - initializeExternalMethods(); + +ExecutionEngine::~ExecutionEngine() { + delete &CurMod; } //===----------------------------------------------------------------------===// // main Driver function // int main(int argc, char** argv) { - cl::ParseCommandLineOptions(argc, argv, " llvm interpreter\n"); + cl::ParseCommandLineOptions(argc, argv, + " llvm interpreter & dynamic compiler\n"); - // Add the module name to the start of the argv vector... - // - InputArgv.insert(InputArgv.begin(), InputFile); - - // Create the interpreter... - Interpreter I; + // Load the bytecode... + string ErrorMsg; + Module *M = ParseBytecodeFile(InputFile, &ErrorMsg); + if (M == 0) { + cout << "Error parsing '" << InputFile << "': " + << ErrorMsg << "\n"; + exit(1); + } - // Handle alternate names of the program. If started as llp, enable profiling - // if started as ldb, enable debugging... - // - if (argv[0] == "ldb") // TODO: Obviously incorrect, but you get the idea - DebugMode = true; - else if (argv[0] == "llp") - ProfileMode = true; - - // If running with the profiler, enable it now... - if (ProfileMode) I.enableProfiling(); - if (TraceMode) I.enableTracing(); - - // Start interpreter into the main function... - // - if (!I.callMainMethod(MainFunction, InputArgv) && !DebugMode) { - // If not in debug mode and if the call succeeded, run the code now... - I.run(); +#if 0 + // Link in the runtime library for LLI... + string RuntimeLib = getCurrentExecutablePath(); + if (!RuntimeLib.empty()) RuntimeLib += "/"; + RuntimeLib += "RuntimeLib.bc"; + + if (Module *SupportLib = ParseBytecodeFile(RuntimeLib, &ErrorMsg)) { + if (LinkModules(M, SupportLib, &ErrorMsg)) + std::cerr << "Error Linking runtime library into current module: " + << ErrorMsg << "\n"; + } else { + std::cerr << "Error loading runtime library '"+RuntimeLib+"': " + << ErrorMsg << "\n"; } +#endif + + // FIXME: This should look at the PointerSize and endianness of the bytecode + // file to determine the endianness and pointer size of target machine to use. + unsigned Config = TM::PtrSize64 | TM::BigEndian; + + ExecutionEngine *EE = 0; + + // If there is nothing that is forcing us to use the interpreter, make a JIT. + if (!ForceInterpreter && !DebugMode && !TraceMode) + EE = ExecutionEngine::createJIT(M, Config); + + // If we can't make a JIT, make an interpreter instead. + if (EE == 0) + EE = ExecutionEngine::createInterpreter(M, Config, DebugMode, TraceMode); + + // Add the module name to the start of the argv vector... + InputArgv.insert(InputArgv.begin(), InputFile); - // If debug mode, allow the user to interact... also, if the user pressed - // ctrl-c or execution hit an error, enter the event loop... - if (DebugMode || I.isStopped()) - I.handleUserInput(); + // Run the main function! + int ExitCode = EE->run(MainFunction, InputArgv); - // Return the status code of the program executed... - return I.getExitCode(); + // Now that we are done executing the program, shut down the execution engine + delete EE; + return ExitCode; } From lattner at cs.uiuc.edu Mon Dec 23 18:00:03 2002 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Mon Dec 23 18:00:03 2002 Subject: [llvm-commits] CVS: llvm/tools/lli/Interpreter/Execution.cpp ExecutionAnnotations.h ExternalFunctions.cpp Interpreter.h Support.cpp UserInput.cpp Message-ID: <200212232359.RAA04723@apoc.cs.uiuc.edu> Changes in directory llvm/tools/lli/Interpreter: Execution.cpp updated: 1.73 -> 1.74 ExecutionAnnotations.h updated: 1.8 -> 1.9 ExternalFunctions.cpp updated: 1.40 -> 1.41 Interpreter.h updated: 1.24 -> 1.25 Support.cpp updated: 1.5 -> 1.6 UserInput.cpp updated: 1.23 -> 1.24 --- Log message: Substantial changes to refactor LLI to incorporate both the Jello JIT and the traditional LLI interpreter --- Diffs of the changes: Index: llvm/tools/lli/Interpreter/Execution.cpp diff -u llvm/tools/lli/Interpreter/Execution.cpp:1.73 llvm/tools/lli/Interpreter/Execution.cpp:1.74 --- llvm/tools/lli/Interpreter/Execution.cpp:1.73 Sun Dec 8 00:01:34 2002 +++ llvm/tools/lli/Interpreter/Execution.cpp Mon Dec 23 17:59:41 2002 @@ -6,6 +6,8 @@ #include "Interpreter.h" #include "ExecutionAnnotations.h" +#include "llvm/GlobalVariable.h" +#include "llvm/Function.h" #include "llvm/iPHINode.h" #include "llvm/iOther.h" #include "llvm/iTerminators.h" @@ -13,7 +15,6 @@ #include "llvm/DerivedTypes.h" #include "llvm/Constants.h" #include "llvm/Assembly/Writer.h" -#include "llvm/Target/TargetData.h" #include "Support/CommandLine.h" #include "Support/Statistic.h" #include // For fmod @@ -23,11 +24,14 @@ using std::cout; using std::cerr; +Interpreter *TheEE = 0; + namespace { Statistic<> NumDynamicInsts("lli", "Number of dynamic instructions executed"); cl::opt - QuietMode("quiet", cl::desc("Do not emit any non-program output")); + QuietMode("quiet", cl::desc("Do not emit any non-program output"), + cl::init(true)); cl::alias QuietModeA("q", cl::desc("Alias for -quiet"), cl::aliasopt(QuietMode)); @@ -43,10 +47,8 @@ // Create a TargetData structure to handle memory addressing and size/alignment // computations // -TargetData TD("lli Interpreter"); CachedWriter CW; // Object to accelerate printing of LLVM - #ifdef PROFILE_STRUCTURE_FIELDS static cl::opt ProfileStructureFields("profilestructfields", @@ -87,48 +89,12 @@ return SN->SlotNum; } -#define GET_CONST_VAL(TY, CLASS) \ - case Type::TY##TyID: Result.TY##Val = cast(C)->getValue(); break - // Operations used by constant expr implementations... static GenericValue executeCastOperation(Value *Src, const Type *DestTy, ExecutionContext &SF); -static GenericValue executeGEPOperation(Value *Src, User::op_iterator IdxBegin, - User::op_iterator IdxEnd, - ExecutionContext &SF); static GenericValue executeAddInst(GenericValue Src1, GenericValue Src2, const Type *Ty, ExecutionContext &SF); -static GenericValue getConstantValue(const Constant *C) { - GenericValue Result; - switch (C->getType()->getPrimitiveID()) { - GET_CONST_VAL(Bool , ConstantBool); - GET_CONST_VAL(UByte , ConstantUInt); - GET_CONST_VAL(SByte , ConstantSInt); - GET_CONST_VAL(UShort , ConstantUInt); - GET_CONST_VAL(Short , ConstantSInt); - GET_CONST_VAL(UInt , ConstantUInt); - GET_CONST_VAL(Int , ConstantSInt); - GET_CONST_VAL(ULong , ConstantUInt); - GET_CONST_VAL(Long , ConstantSInt); - GET_CONST_VAL(Float , ConstantFP); - GET_CONST_VAL(Double , ConstantFP); - case Type::PointerTyID: - if (isa(C)) { - Result.PointerVal = 0; - } else if (const ConstantPointerRef *CPR = dyn_cast(C)){ - GlobalAddress *Address = - (GlobalAddress*)CPR->getValue()->getOrCreateAnnotation(GlobalAddressAID); - Result.PointerVal = (PointerTy)Address->Ptr; - } else { - assert(0 && "Unknown constant pointer type!"); - } - break; - default: - cout << "ERROR: Constant unimp for type: " << C->getType() << "\n"; - } - return Result; -} static GenericValue getOperandValue(Value *V, ExecutionContext &SF) { if (ConstantExpr *CE = dyn_cast(V)) { @@ -136,8 +102,8 @@ case Instruction::Cast: return executeCastOperation(CE->getOperand(0), CE->getType(), SF); case Instruction::GetElementPtr: - return executeGEPOperation(CE->getOperand(0), CE->op_begin()+1, - CE->op_end(), SF); + return TheEE->executeGEPOperation(CE->getOperand(0), CE->op_begin()+1, + CE->op_end(), SF); case Instruction::Add: return executeAddInst(getOperandValue(CE->getOperand(0), SF), getOperandValue(CE->getOperand(1), SF), @@ -148,13 +114,9 @@ { GenericValue V; return V; } } } else if (Constant *CPV = dyn_cast(V)) { - return getConstantValue(CPV); + return TheEE->getConstantValue(CPV); } else if (GlobalValue *GV = dyn_cast(V)) { - GlobalAddress *Address = - (GlobalAddress*)GV->getOrCreateAnnotation(GlobalAddressAID); - GenericValue Result; - Result.PointerVal = (PointerTy)(GenericValue*)Address->Ptr; - return Result; + return PTOGV(TheEE->getPointerToGlobal(GV)); } else { unsigned TyP = V->getType()->getUniqueID(); // TypePlane for value unsigned OpSlot = getOperandSlot(V); @@ -201,85 +163,12 @@ //===----------------------------------------------------------------------===// void Interpreter::initializeExecutionEngine() { + TheEE = this; AnnotationManager::registerAnnotationFactory(MethodInfoAID, &MethodInfo::Create); - AnnotationManager::registerAnnotationFactory(GlobalAddressAID, - &GlobalAddress::Create); initializeSignalHandlers(); } -static void StoreValueToMemory(GenericValue Val, GenericValue *Ptr, - const Type *Ty); - -// InitializeMemory - Recursive function to apply a Constant value into the -// specified memory location... -// -static void InitializeMemory(const Constant *Init, char *Addr) { - - if (Init->getType()->isFirstClassType()) { - GenericValue Val = getConstantValue(Init); - StoreValueToMemory(Val, (GenericValue*)Addr, Init->getType()); - return; - } - - switch (Init->getType()->getPrimitiveID()) { - case Type::ArrayTyID: { - const ConstantArray *CPA = cast(Init); - const vector &Val = CPA->getValues(); - unsigned ElementSize = - TD.getTypeSize(cast(CPA->getType())->getElementType()); - for (unsigned i = 0; i < Val.size(); ++i) - InitializeMemory(cast(Val[i].get()), Addr+i*ElementSize); - return; - } - - case Type::StructTyID: { - const ConstantStruct *CPS = cast(Init); - const StructLayout *SL=TD.getStructLayout(cast(CPS->getType())); - const vector &Val = CPS->getValues(); - for (unsigned i = 0; i < Val.size(); ++i) - InitializeMemory(cast(Val[i].get()), - Addr+SL->MemberOffsets[i]); - return; - } - - default: - CW << "Bad Type: " << Init->getType() << "\n"; - assert(0 && "Unknown constant type to initialize memory with!"); - } -} - -Annotation *GlobalAddress::Create(AnnotationID AID, const Annotable *O, void *){ - assert(AID == GlobalAddressAID); - - // This annotation will only be created on GlobalValue objects... - GlobalValue *GVal = cast((Value*)O); - - if (isa(GVal)) { - // The GlobalAddress object for a function is just a pointer to function - // itself. Don't delete it when the annotation is gone though! - return new GlobalAddress(GVal, false); - } - - // Handle the case of a global variable... - assert(isa(GVal) && - "Global value found that isn't a function or global variable!"); - GlobalVariable *GV = cast(GVal); - - // First off, we must allocate space for the global variable to point at... - const Type *Ty = GV->getType()->getElementType(); // Type to be allocated - - // Allocate enough memory to hold the type... - void *Addr = calloc(1, TD.getTypeSize(Ty)); - assert(Addr != 0 && "Null pointer returned by malloc!"); - - // Initialize the memory if there is an initializer... - if (GV->hasInitializer()) - InitializeMemory(GV->getInitializer(), (char*)Addr); - - return new GlobalAddress(Addr, true); // Simply invoke the ctor -} - //===----------------------------------------------------------------------===// // Binary Instruction Implementations //===----------------------------------------------------------------------===// @@ -760,8 +649,7 @@ // FIXME: Don't use CALLOC, use a tainted malloc. void *Memory = calloc(NumElements, TD.getTypeSize(Ty)); - GenericValue Result; - Result.PointerVal = (PointerTy)Memory; + GenericValue Result = PTOGV(Memory); assert(Result.PointerVal != 0 && "Null pointer returned by malloc!"); SetValue(&I, Result, SF); @@ -773,15 +661,15 @@ assert(isa(I.getOperand(0)->getType()) && "Freeing nonptr?"); GenericValue Value = getOperandValue(I.getOperand(0), SF); // TODO: Check to make sure memory is allocated - free((void*)Value.PointerVal); // Free memory + free(GVTOP(Value)); // Free memory } // getElementOffset - The workhorse for getelementptr. // -static GenericValue executeGEPOperation(Value *Ptr, User::op_iterator I, - User::op_iterator E, - ExecutionContext &SF) { +GenericValue Interpreter::executeGEPOperation(Value *Ptr, User::op_iterator I, + User::op_iterator E, + ExecutionContext &SF) { assert(isa(Ptr->getType()) && "Cannot getElementOffset of a nonpointer type!"); @@ -834,13 +722,13 @@ } static void executeGEPInst(GetElementPtrInst &I, ExecutionContext &SF) { - SetValue(&I, executeGEPOperation(I.getPointerOperand(), + SetValue(&I, TheEE->executeGEPOperation(I.getPointerOperand(), I.idx_begin(), I.idx_end(), SF), SF); } -static void executeLoadInst(LoadInst &I, ExecutionContext &SF) { +void Interpreter::executeLoadInst(LoadInst &I, ExecutionContext &SF) { GenericValue SRC = getOperandValue(I.getPointerOperand(), SF); - GenericValue *Ptr = (GenericValue*)SRC.PointerVal; + GenericValue *Ptr = (GenericValue*)GVTOP(SRC); GenericValue Result; if (TD.isLittleEndian()) { @@ -910,102 +798,14 @@ SetValue(&I, Result, SF); } -static void StoreValueToMemory(GenericValue Val, GenericValue *Ptr, - const Type *Ty) { - if (TD.isLittleEndian()) { - switch (Ty->getPrimitiveID()) { - case Type::BoolTyID: - case Type::UByteTyID: - case Type::SByteTyID: Ptr->Untyped[0] = Val.UByteVal; break; - case Type::UShortTyID: - case Type::ShortTyID: Ptr->Untyped[0] = Val.UShortVal & 255; - Ptr->Untyped[1] = (Val.UShortVal >> 8) & 255; - break; - case Type::FloatTyID: - case Type::UIntTyID: - case Type::IntTyID: Ptr->Untyped[0] = Val.UIntVal & 255; - Ptr->Untyped[1] = (Val.UIntVal >> 8) & 255; - Ptr->Untyped[2] = (Val.UIntVal >> 16) & 255; - Ptr->Untyped[3] = (Val.UIntVal >> 24) & 255; - break; - case Type::DoubleTyID: - case Type::ULongTyID: - case Type::LongTyID: - case Type::PointerTyID: Ptr->Untyped[0] = Val.ULongVal & 255; - Ptr->Untyped[1] = (Val.ULongVal >> 8) & 255; - Ptr->Untyped[2] = (Val.ULongVal >> 16) & 255; - Ptr->Untyped[3] = (Val.ULongVal >> 24) & 255; - Ptr->Untyped[4] = (Val.ULongVal >> 32) & 255; - Ptr->Untyped[5] = (Val.ULongVal >> 40) & 255; - Ptr->Untyped[6] = (Val.ULongVal >> 48) & 255; - Ptr->Untyped[7] = (Val.ULongVal >> 56) & 255; - break; - default: - cout << "Cannot store value of type " << Ty << "!\n"; - } - } else { - switch (Ty->getPrimitiveID()) { - case Type::BoolTyID: - case Type::UByteTyID: - case Type::SByteTyID: Ptr->Untyped[0] = Val.UByteVal; break; - case Type::UShortTyID: - case Type::ShortTyID: Ptr->Untyped[1] = Val.UShortVal & 255; - Ptr->Untyped[0] = (Val.UShortVal >> 8) & 255; - break; - case Type::FloatTyID: - case Type::UIntTyID: - case Type::IntTyID: Ptr->Untyped[3] = Val.UIntVal & 255; - Ptr->Untyped[2] = (Val.UIntVal >> 8) & 255; - Ptr->Untyped[1] = (Val.UIntVal >> 16) & 255; - Ptr->Untyped[0] = (Val.UIntVal >> 24) & 255; - break; - case Type::DoubleTyID: - case Type::ULongTyID: - case Type::LongTyID: - case Type::PointerTyID: Ptr->Untyped[7] = Val.ULongVal & 255; - Ptr->Untyped[6] = (Val.ULongVal >> 8) & 255; - Ptr->Untyped[5] = (Val.ULongVal >> 16) & 255; - Ptr->Untyped[4] = (Val.ULongVal >> 24) & 255; - Ptr->Untyped[3] = (Val.ULongVal >> 32) & 255; - Ptr->Untyped[2] = (Val.ULongVal >> 40) & 255; - Ptr->Untyped[1] = (Val.ULongVal >> 48) & 255; - Ptr->Untyped[0] = (Val.ULongVal >> 56) & 255; - break; - default: - cout << "Cannot store value of type " << Ty << "!\n"; - } - } -} - -static void executeStoreInst(StoreInst &I, ExecutionContext &SF) { +void Interpreter::executeStoreInst(StoreInst &I, ExecutionContext &SF) { GenericValue Val = getOperandValue(I.getOperand(0), SF); GenericValue SRC = getOperandValue(I.getPointerOperand(), SF); - StoreValueToMemory(Val, (GenericValue *)SRC.PointerVal, + StoreValueToMemory(Val, (GenericValue *)GVTOP(SRC), I.getOperand(0)->getType()); } -GenericValue Interpreter::CreateArgv(const std::vector &InputArgv){ - // Pointers are 64 bits... - PointerTy *Result = new PointerTy[InputArgv.size()+1]; // 64 bit assumption - - for (unsigned i = 0; i < InputArgv.size(); ++i) { - unsigned Size = InputArgv[i].size()+1; - char *Dest = new char[Size]; - copy(InputArgv[i].begin(), InputArgv[i].end(), Dest); - Dest[Size-1] = 0; - - GenericValue GV; GV.PointerVal = (PointerTy)Dest; - // Endian safe: Result[i] = (PointerTy)Dest; - StoreValueToMemory(GV, (GenericValue*)(Result+i), - Type::LongTy); // 64 bit assumption - } - - Result[InputArgv.size()] = 0; - GenericValue GV; GV.PointerVal = (PointerTy)Result; - return GV; -} - //===----------------------------------------------------------------------===// // Miscellaneous Instruction Implementations @@ -1022,7 +822,7 @@ // and treat it as a function pointer. GenericValue SRC = getOperandValue(I.getCalledValue(), SF); - callMethod((Function*)SRC.PointerVal, ArgVals); + callMethod((Function*)GVTOP(SRC), ArgVals); } static void executePHINode(PHINode &I, ExecutionContext &SF) { @@ -1433,7 +1233,7 @@ case Type::ULongTyID: cout << (unsigned long)V.ULongVal; break; case Type::FloatTyID: cout << V.FloatVal; break; case Type::DoubleTyID: cout << V.DoubleVal; break; - case Type::PointerTyID:cout << (void*)V.PointerVal; break; + case Type::PointerTyID:cout << (void*)GVTOP(V); break; default: cout << "- Don't know how to print value of this type!"; break; Index: llvm/tools/lli/Interpreter/ExecutionAnnotations.h diff -u llvm/tools/lli/Interpreter/ExecutionAnnotations.h:1.8 llvm/tools/lli/Interpreter/ExecutionAnnotations.h:1.9 --- llvm/tools/lli/Interpreter/ExecutionAnnotations.h:1.8 Tue Apr 9 14:40:40 2002 +++ llvm/tools/lli/Interpreter/ExecutionAnnotations.h Mon Dec 23 17:59:41 2002 @@ -90,32 +90,4 @@ // Just use an Annotation directly, Breakpoint is currently just a marker -//===----------------------------------------------------------------------===// -// Support for the GlobalAddress annotation -//===----------------------------------------------------------------------===// - -// This annotation (attached only to GlobalValue objects) is used to hold the -// address of the chunk of memory that represents a global value. For -// Functions, this pointer is the Function object pointer that represents it. -// For global variables, this is the dynamically allocated (and potentially -// initialized) chunk of memory for the global. This annotation is created on -// demand. -// -static AnnotationID GlobalAddressAID( - AnnotationManager::getID("Interpreter::GlobalAddress")); - -struct GlobalAddress : public Annotation { - void *Ptr; // The pointer itself - bool Delete; // Should I delete them memory on destruction? - - GlobalAddress(void *ptr, bool d) : Annotation(GlobalAddressAID), Ptr(ptr), - Delete(d) {} - ~GlobalAddress() { if (Delete) free(Ptr); } - - // Create - Factory function to allow GlobalAddress annotations to be - // created on demand. - // - static Annotation *Create(AnnotationID AID, const Annotable *O, void *); -}; - #endif Index: llvm/tools/lli/Interpreter/ExternalFunctions.cpp diff -u llvm/tools/lli/Interpreter/ExternalFunctions.cpp:1.40 llvm/tools/lli/Interpreter/ExternalFunctions.cpp:1.41 --- llvm/tools/lli/Interpreter/ExternalFunctions.cpp:1.40 Thu Dec 19 22:18:13 2002 +++ llvm/tools/lli/Interpreter/ExternalFunctions.cpp Mon Dec 23 17:59:41 2002 @@ -12,6 +12,7 @@ #include "Interpreter.h" #include "ExecutionAnnotations.h" +#include "llvm/Module.h" #include "llvm/DerivedTypes.h" #include "llvm/SymbolTable.h" #include "llvm/Target/TargetData.h" @@ -23,8 +24,6 @@ using std::vector; using std::cout; -extern TargetData TD; - typedef GenericValue (*ExFunc)(FunctionType *, const vector &); static std::map Functions; static std::map FuncNames; @@ -440,8 +439,8 @@ static PointerTy IOBBase = 0; static unsigned FILESize; - if (LastMod != TheInterpreter->getModule()) { // Module change or initialize? - Module *M = LastMod = TheInterpreter->getModule(); + if (LastMod != &TheInterpreter->getModule()) { // Module change or initialize? + Module *M = LastMod = &TheInterpreter->getModule(); // Check to see if the currently loaded module contains an __iob symbol... GlobalVariable *IOB = 0; @@ -456,6 +455,7 @@ if (IOB) break; } +#if 0 /// FIXME! __iob support for LLI // If we found an __iob symbol now, find out what the actual address it's // held in is... if (IOB) { @@ -472,6 +472,7 @@ else FILESize = 16*8; // Default size } +#endif } // Check to see if this is a reference to __iob... Index: llvm/tools/lli/Interpreter/Interpreter.h diff -u llvm/tools/lli/Interpreter/Interpreter.h:1.24 llvm/tools/lli/Interpreter/Interpreter.h:1.25 --- llvm/tools/lli/Interpreter/Interpreter.h:1.24 Thu Nov 7 13:29:31 2002 +++ llvm/tools/lli/Interpreter/Interpreter.h Mon Dec 23 17:59:41 2002 @@ -10,36 +10,23 @@ // Uncomment this line to enable profiling of structure field accesses. //#define PROFILE_STRUCTURE_FIELDS 1 -#include "llvm/Module.h" +#include "../ExecutionEngine.h" #include "Support/DataTypes.h" #include "llvm/Assembly/CachedWriter.h" +#include "llvm/Target/TargetData.h" +#include "llvm/BasicBlock.h" +#include "../GenericValue.h" -extern CachedWriter CW; // Object to accellerate printing of LLVM +extern CachedWriter CW; // Object to accelerate printing of LLVM struct MethodInfo; // Defined in ExecutionAnnotations.h class CallInst; class ReturnInst; class BranchInst; +class LoadInst; +class StoreInst; class AllocationInst; -typedef uint64_t PointerTy; - -union GenericValue { - bool BoolVal; - unsigned char UByteVal; - signed char SByteVal; - unsigned short UShortVal; - signed short ShortVal; - unsigned int UIntVal; - signed int IntVal; - uint64_t ULongVal; - int64_t LongVal; - double DoubleVal; - float FloatVal; - PointerTy PointerVal; - unsigned char Untyped[8]; -}; - // AllocaHolder - Object to track all of the blocks of memory allocated by // alloca. When the function returns, this object is poped off the execution // stack, which causes the dtor to be run, which frees all the alloca'd memory. @@ -90,25 +77,31 @@ // Interpreter - This class represents the entirety of the interpreter. // -class Interpreter { - Module *CurMod; // The current Module being executed (0 if none) +class Interpreter : public ExecutionEngine { int ExitCode; // The exit code to be returned by the lli util + bool Debug; // Debug mode enabled? bool Profile; // Profiling enabled? bool Trace; // Tracing enabled? int CurFrame; // The current stack frame being inspected + TargetData TD; // The runtime stack of executing code. The top of the stack is the current // function record. std::vector ECStack; public: - Interpreter(); - inline ~Interpreter() { CW.setModule(0); delete CurMod; } + Interpreter(Module *M, unsigned Config, bool DebugMode, bool TraceMode); + inline ~Interpreter() { CW.setModule(0); } // getExitCode - return the code that should be the exit code for the lli // utility. inline int getExitCode() const { return ExitCode; } - inline Module *getModule() const { return CurMod; } + + /// run - Start execution with the specified function and arguments. + /// + virtual int run(const std::string &FnName, + const std::vector &Args); + // enableProfiling() - Turn profiling on, clear stats? void enableProfiling() { Profile = true; } @@ -117,8 +110,6 @@ void handleUserInput(); // User Interation Methods... - void loadModule(const std::string &Filename); - bool flushModule(); bool callMethod(const std::string &Name); // return true on failure void setBreakpoint(const std::string &Name); void infoValue(const std::string &Name); @@ -128,7 +119,6 @@ bool callMainMethod(const std::string &MainName, const std::vector &InputFilename); - GenericValue CreateArgv(const std::vector &InputArgv); void list(); // Do the 'list' command void printStackTrace(); // Do the 'backtrace' command @@ -161,7 +151,17 @@ // inline bool isStopped() const { return !ECStack.empty(); } + //FIXME: private: +public: + GenericValue executeGEPOperation(Value *Ptr, User::op_iterator I, + User::op_iterator E, ExecutionContext &SF); + void executeLoadInst(LoadInst &I, ExecutionContext &SF); + void executeStoreInst(StoreInst &I, ExecutionContext &SF); + + private: // Helper functions + void *getPointerToFunction(const Function *F) { return (void*)F; } + // getCurrentExecutablePath() - Return the directory that the lli executable // lives in. // Index: llvm/tools/lli/Interpreter/Support.cpp diff -u llvm/tools/lli/Interpreter/Support.cpp:1.5 llvm/tools/lli/Interpreter/Support.cpp:1.6 --- llvm/tools/lli/Interpreter/Support.cpp:1.5 Wed Nov 20 12:35:26 2002 +++ llvm/tools/lli/Interpreter/Support.cpp Mon Dec 23 17:59:41 2002 @@ -7,6 +7,7 @@ #include "Interpreter.h" #include "llvm/SymbolTable.h" #include "llvm/Assembly/Writer.h" +#include "llvm/Module.h" #include using std::cout; @@ -38,7 +39,7 @@ Function *CurMeth = getCurrentMethod(); if (CurMeth) ::LookupMatchingNames(Name, CurMeth->getSymbolTable(), Results); - if (CurMod ) ::LookupMatchingNames(Name, CurMod ->getSymbolTable(), Results); + ::LookupMatchingNames(Name, getModule().getSymbolTable(), Results); return Results; } Index: llvm/tools/lli/Interpreter/UserInput.cpp diff -u llvm/tools/lli/Interpreter/UserInput.cpp:1.23 llvm/tools/lli/Interpreter/UserInput.cpp:1.24 --- llvm/tools/lli/Interpreter/UserInput.cpp:1.23 Thu Nov 7 13:29:31 2002 +++ llvm/tools/lli/Interpreter/UserInput.cpp Mon Dec 23 17:59:41 2002 @@ -7,6 +7,7 @@ #include "Interpreter.h" #include "llvm/Bytecode/Reader.h" #include "llvm/DerivedTypes.h" +#include "llvm/Function.h" #include "llvm/Transforms/Utils/Linker.h" #include using std::string; @@ -18,8 +19,8 @@ Print, Info, List, StackTrace, Up, Down, // Inspection Next, Step, Run, Finish, Call, // Control flow changes Break, Watch, // Debugging - Load, Flush, - TraceOpt, ProfileOpt // Toggle features + Flush, + TraceOpt, // Toggle features }; // CommandTable - Build a lookup table for the commands available to the user... @@ -53,11 +54,9 @@ { "break" , Break }, { "b", Break }, { "watch" , Watch }, - { "load" , Load }, { "flush" , Flush }, { "trace" , TraceOpt }, - { "profile" , ProfileOpt }, }; static CommandTableElement *CommandTableEnd = CommandTable+sizeof(CommandTable)/sizeof(CommandTable[0]); @@ -90,11 +89,6 @@ switch (E->CID) { case Quit: UserQuit = true; break; - case Load: - cin >> Command; - loadModule(Command); - break; - case Flush: flushModule(); break; case Print: cin >> Command; print(Command); @@ -132,11 +126,6 @@ cout << "Tracing " << (Trace ? "enabled\n" : "disabled\n"); break; - case ProfileOpt: - Profile = !Profile; - cout << "Profiling " << (Trace ? "enabled\n" : "disabled\n"); - break; - default: cout << "Command '" << Command << "' unimplemented!\n"; break; @@ -146,61 +135,6 @@ } //===----------------------------------------------------------------------===// -// loadModule - Load a new module to execute... -// -void Interpreter::loadModule(const string &Filename) { - string ErrorMsg; - if (CurMod && !flushModule()) return; // Kill current execution - - CurMod = ParseBytecodeFile(Filename, &ErrorMsg); - if (CurMod == 0) { - cout << "Error parsing '" << Filename << "': No module loaded: " - << ErrorMsg << "\n"; - return; - } - CW.setModule(CurMod); // Update Writer - -#if 0 - string RuntimeLib = getCurrentExecutablePath(); - if (!RuntimeLib.empty()) RuntimeLib += "/"; - RuntimeLib += "RuntimeLib.bc"; - - if (Module *SupportLib = ParseBytecodeFile(RuntimeLib, &ErrorMsg)) { - if (LinkModules(CurMod, SupportLib, &ErrorMsg)) - std::cerr << "Error Linking runtime library into current module: " - << ErrorMsg << "\n"; - } else { - std::cerr << "Error loading runtime library '"+RuntimeLib+"': " - << ErrorMsg << "\n"; - } -#endif -} - - -//===----------------------------------------------------------------------===// -// flushModule - Return true if the current program has been unloaded. -// -bool Interpreter::flushModule() { - if (CurMod == 0) { - cout << "Error flushing: No module loaded!\n"; - return false; - } - - if (!ECStack.empty()) { - // TODO: if use is not sure, return false - cout << "Killing current execution!\n"; - ECStack.clear(); - CurFrame = -1; - } - - CW.setModule(0); - delete CurMod; - CurMod = 0; - ExitCode = 0; - return true; -} - -//===----------------------------------------------------------------------===// // setBreakpoint - Enable a breakpoint at the specified location // void Interpreter::setBreakpoint(const string &Name) { @@ -272,7 +206,7 @@ return true; } - Args.push_back(CreateArgv(InputArgv)); + Args.push_back(PTOGV(CreateArgv(InputArgv))); } // fallthrough case 1: From lattner at cs.uiuc.edu Mon Dec 23 18:02:00 2002 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Mon Dec 23 18:02:00 2002 Subject: [llvm-commits] CVS: llvm/tools/lli/ExecutionEngine.cpp ExecutionEngine.h GenericValue.h Message-ID: <200212240001.SAA04954@apoc.cs.uiuc.edu> Changes in directory llvm/tools/lli: ExecutionEngine.cpp added (r1.1) ExecutionEngine.h added (r1.1) GenericValue.h added (r1.1) --- Log message: Initial checkin of new LLI with JIT compiler --- Diffs of the changes: From lattner at cs.uiuc.edu Mon Dec 23 18:02:02 2002 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Mon Dec 23 18:02:02 2002 Subject: [llvm-commits] CVS: llvm/tools/lli/Interpreter/Interpreter.cpp Makefile Message-ID: <200212240001.SAA04960@apoc.cs.uiuc.edu> Changes in directory llvm/tools/lli/Interpreter: Interpreter.cpp added (r1.1) Makefile added (r1.1) --- Log message: Initial checkin of new LLI with JIT compiler --- Diffs of the changes: From lattner at cs.uiuc.edu Mon Dec 23 18:02:03 2002 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Mon Dec 23 18:02:03 2002 Subject: [llvm-commits] CVS: llvm/tools/lli/JIT/Callback.cpp Emitter.cpp GlobalVars.cpp JIT.cpp Makefile VM.cpp Message-ID: <200212240001.SAA04965@apoc.cs.uiuc.edu> Changes in directory llvm/tools/lli/JIT: Callback.cpp added (r1.1) Emitter.cpp added (r1.1) GlobalVars.cpp added (r1.1) JIT.cpp added (r1.1) Makefile added (r1.1) VM.cpp added (r1.1) --- Log message: Initial checkin of new LLI with JIT compiler --- Diffs of the changes: From lattner at cs.uiuc.edu Mon Dec 23 18:02:04 2002 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Mon Dec 23 18:02:04 2002 Subject: [llvm-commits] CVS: llvm/tools/lli/JIT/VM.h Message-ID: <200212240001.SAA04978@apoc.cs.uiuc.edu> Changes in directory llvm/tools/lli/JIT: VM.h added (r1.1) --- Log message: Initial checkin --- Diffs of the changes: From lattner at cs.uiuc.edu Mon Dec 23 18:03:01 2002 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Mon Dec 23 18:03:01 2002 Subject: [llvm-commits] CVS: llvm/include/llvm/Target/TargetMachine.h TargetMachineImpls.h Message-ID: <200212240002.SAA05151@apoc.cs.uiuc.edu> Changes in directory llvm/include/llvm/Target: TargetMachine.h updated: 1.24 -> 1.25 TargetMachineImpls.h updated: 1.2 -> 1.3 --- Log message: Allow the target machines to specify endianness and pointer size --- Diffs of the changes: Index: llvm/include/llvm/Target/TargetMachine.h diff -u llvm/include/llvm/Target/TargetMachine.h:1.24 llvm/include/llvm/Target/TargetMachine.h:1.25 --- llvm/include/llvm/Target/TargetMachine.h:1.24 Tue Dec 3 23:20:12 2002 +++ llvm/include/llvm/Target/TargetMachine.h Mon Dec 23 18:02:17 2002 @@ -39,13 +39,14 @@ protected: TargetMachine(const std::string &name, // Can only create subclasses... + bool LittleEndian = false, unsigned char SubWordSize = 1, unsigned char IntRegSize = 8, unsigned char PtrSize = 8, unsigned char PtrAl = 8, unsigned char DoubleAl = 8, unsigned char FloatAl = 4, unsigned char LongAl = 8, unsigned char IntAl = 4, unsigned char ShortAl = 2, unsigned char ByteAl = 1) - : Name(name), DataLayout(name, SubWordSize, IntRegSize, PtrSize, PtrAl, - DoubleAl, FloatAl, LongAl, + : Name(name), DataLayout(name, LittleEndian, SubWordSize, IntRegSize, + PtrSize, PtrAl, DoubleAl, FloatAl, LongAl, IntAl, ShortAl, ByteAl) {} public: virtual ~TargetMachine() {} Index: llvm/include/llvm/Target/TargetMachineImpls.h diff -u llvm/include/llvm/Target/TargetMachineImpls.h:1.2 llvm/include/llvm/Target/TargetMachineImpls.h:1.3 --- llvm/include/llvm/Target/TargetMachineImpls.h:1.2 Tue Oct 29 14:51:29 2002 +++ llvm/include/llvm/Target/TargetMachineImpls.h Mon Dec 23 18:02:17 2002 @@ -8,6 +8,18 @@ #ifndef LLVM_TARGET_TARGETMACHINEIMPLS_H #define LLVM_TARGET_TARGETMACHINEIMPLS_H +namespace TM { + enum { + PtrSizeMask = 1, + PtrSize32 = 0, + PtrSize64 = 1, + + EndianMask = 2, + LittleEndian = 0, + BigEndian = 2, + }; +} + class TargetMachine; // allocateSparcTargetMachine - Allocate and return a subclass of TargetMachine @@ -16,8 +28,11 @@ TargetMachine *allocateSparcTargetMachine(); // allocateX86TargetMachine - Allocate and return a subclass of TargetMachine -// that implements the X86 backend. +// that implements the X86 backend. The X86 target machine can run in +// "emulation" mode, where it is capable of emulating machines of larger pointer +// size and different endianness if desired. // -TargetMachine *allocateX86TargetMachine(); +TargetMachine *allocateX86TargetMachine(unsigned Configuration = + TM::PtrSize32|TM::LittleEndian); #endif From lattner at cs.uiuc.edu Mon Dec 23 18:03:02 2002 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Mon Dec 23 18:03:02 2002 Subject: [llvm-commits] CVS: llvm/lib/Target/Sparc/Sparc.cpp Message-ID: <200212240002.SAA05162@apoc.cs.uiuc.edu> Changes in directory llvm/lib/Target/Sparc: Sparc.cpp updated: 1.57 -> 1.58 --- Log message: Sparc is not little endian --- Diffs of the changes: Index: llvm/lib/Target/Sparc/Sparc.cpp diff -u llvm/lib/Target/Sparc/Sparc.cpp:1.57 llvm/lib/Target/Sparc/Sparc.cpp:1.58 --- llvm/lib/Target/Sparc/Sparc.cpp:1.57 Mon Dec 2 23:41:54 2002 +++ llvm/lib/Target/Sparc/Sparc.cpp Mon Dec 23 18:02:38 2002 @@ -127,7 +127,7 @@ //--------------------------------------------------------------------------- UltraSparc::UltraSparc() - : TargetMachine("UltraSparc-Native", 4), + : TargetMachine("UltraSparc-Native", false, 4), schedInfo(*this), regInfo(*this), frameInfo(*this), From lattner at cs.uiuc.edu Mon Dec 23 18:04:01 2002 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Mon Dec 23 18:04:01 2002 Subject: [llvm-commits] CVS: llvm/lib/Target/X86/InstSelectSimple.cpp Message-ID: <200212240003.SAA05173@apoc.cs.uiuc.edu> Changes in directory llvm/lib/Target/X86: InstSelectSimple.cpp updated: 1.76 -> 1.77 --- Log message: Changes to compile with GCC 2.96 Changes to support configurable pointer size and endianness --- Diffs of the changes: Index: llvm/lib/Target/X86/InstSelectSimple.cpp diff -u llvm/lib/Target/X86/InstSelectSimple.cpp:1.76 llvm/lib/Target/X86/InstSelectSimple.cpp:1.77 --- llvm/lib/Target/X86/InstSelectSimple.cpp:1.76 Tue Dec 17 19:44:31 2002 +++ llvm/lib/Target/X86/InstSelectSimple.cpp Mon Dec 23 18:03:11 2002 @@ -37,7 +37,7 @@ unsigned DestReg) { assert(I >= MBB->begin() && I <= MBB->end() && "Bad iterator!"); MachineInstr *MI = new MachineInstr(Opcode, NumOperands+1, true, true); - I = ++MBB->insert(I, MI); + I = MBB->insert(I, MI)+1; return MachineInstrBuilder(MI).addReg(DestReg, MOTy::Def); } @@ -49,7 +49,7 @@ unsigned NumOperands) { assert(I > MBB->begin() && I <= MBB->end() && "Bad iterator!"); MachineInstr *MI = new MachineInstr(Opcode, NumOperands, true, true); - I = ++MBB->insert(I, MI); + I = MBB->insert(I, MI)+1; return MachineInstrBuilder(MI); } @@ -816,17 +816,43 @@ /// visitLoadInst - Implement LLVM load instructions in terms of the x86 'mov' -/// instruction. +/// instruction. The load and store instructions are the only place where we +/// need to worry about the memory layout of the target machine. /// void ISel::visitLoadInst(LoadInst &I) { + bool isLittleEndian = TM.getTargetData().isLittleEndian(); + bool hasLongPointers = TM.getTargetData().getPointerSize() == 8; + unsigned Class = getClass(I.getType()); if (Class > 2) // FIXME: Handle longs and others... visitInstruction(I); static const unsigned Opcode[] = { X86::MOVmr8, X86::MOVmr16, X86::MOVmr32 }; + unsigned SrcAddrReg = getReg(I.getOperand(0)); + + // We need to adjust the input pointer if we are emulating a big-endian + // long-pointer target. On these systems, the pointer that we are interested + // in is in the upper part of the eight byte memory image of the pointer. It + // also happens to be byte-swapped, but this will be handled later. + // + if (!isLittleEndian && hasLongPointers && isa(I.getType())) { + unsigned R = makeAnotherReg(Type::UIntTy); + BuildMI(BB, X86::ADDri32, 2, R).addReg(SrcAddrReg).addZImm(4); + SrcAddrReg = R; + } + unsigned DestReg = getReg(I); + unsigned IReg = DestReg; + if (!isLittleEndian) { // If big endian we need an intermediate stage + IReg = makeAnotherReg(I.getType()); + std::swap(IReg, DestReg); + } + addDirectMem(BuildMI(BB, Opcode[Class], 4, DestReg), SrcAddrReg); - unsigned AddressReg = getReg(I.getOperand(0)); - addDirectMem(BuildMI(BB, Opcode[Class], 4, getReg(I)), AddressReg); + if (!isLittleEndian) { + // Emit the byte swap instruction... + static const unsigned BSWAPOpcode[] = { X86::MOVrr8, X86::BSWAPr16, X86::BSWAPr32 }; + BuildMI(BB, BSWAPOpcode[Class], 1, IReg).addReg(DestReg); + } } @@ -834,6 +860,8 @@ /// instruction. /// void ISel::visitStoreInst(StoreInst &I) { + bool isLittleEndian = TM.getTargetData().isLittleEndian(); + bool hasLongPointers = TM.getTargetData().getPointerSize() == 8; unsigned Class = getClass(I.getOperand(0)->getType()); if (Class > 2) // FIXME: Handle longs and others... visitInstruction(I); @@ -842,6 +870,21 @@ unsigned ValReg = getReg(I.getOperand(0)); unsigned AddressReg = getReg(I.getOperand(1)); + + if (!isLittleEndian && hasLongPointers && isa(I.getOperand(0)->getType())) { + unsigned R = makeAnotherReg(Type::UIntTy); + BuildMI(BB, X86::ADDri32, 2, R).addReg(AddressReg).addZImm(4); + AddressReg = R; + } + + if (!isLittleEndian && Class) { + // Emit the byte swap instruction... + static const unsigned BSWAPOpcode[] = { X86::MOVrr8, X86::BSWAPr16, X86::BSWAPr32 }; + unsigned R = makeAnotherReg(I.getOperand(0)->getType()); + BuildMI(BB, BSWAPOpcode[Class], 1, R).addReg(ValReg); + ValReg = R; + } + addDirectMem(BuildMI(BB, Opcode[Class], 1+4), AddressReg).addReg(ValReg); } @@ -983,7 +1026,7 @@ // be constant, we can get its value and use it to find the // right byte offset from the StructLayout class's list of // structure member offsets. - unsigned idxValue = CUI->getValue (); + unsigned idxValue = CUI->getValue(); unsigned memberOffset = TD.getStructLayout (StTy)->MemberOffsets[idxValue]; // Emit an ADD to add memberOffset to the basePtr. From lattner at cs.uiuc.edu Mon Dec 23 18:05:01 2002 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Mon Dec 23 18:05:01 2002 Subject: [llvm-commits] CVS: llvm/lib/Target/X86/X86TargetMachine.cpp X86TargetMachine.h Message-ID: <200212240004.SAA05188@apoc.cs.uiuc.edu> Changes in directory llvm/lib/Target/X86: X86TargetMachine.cpp updated: 1.8 -> 1.9 X86TargetMachine.h updated: 1.4 -> 1.5 --- Log message: Changes to allow for a configurable target machine that allows big endian and/or long pointer operation --- Diffs of the changes: Index: llvm/lib/Target/X86/X86TargetMachine.cpp diff -u llvm/lib/Target/X86/X86TargetMachine.cpp:1.8 llvm/lib/Target/X86/X86TargetMachine.cpp:1.9 --- llvm/lib/Target/X86/X86TargetMachine.cpp:1.8 Mon Dec 16 20:51:15 2002 +++ llvm/lib/Target/X86/X86TargetMachine.cpp Mon Dec 23 18:04:01 2002 @@ -5,11 +5,11 @@ //===----------------------------------------------------------------------===// #include "X86TargetMachine.h" +#include "X86.h" #include "llvm/Transforms/Scalar.h" #include "llvm/Target/TargetMachineImpls.h" #include "llvm/CodeGen/MachineFunction.h" #include "llvm/PassManager.h" -#include "X86.h" #include "Support/CommandLine.h" #include "Support/Statistic.h" #include @@ -17,17 +17,26 @@ namespace { cl::opt NoLocalRA("no-local-ra", cl::desc("Use Simple RA instead of Local RegAlloc")); + cl::opt PrintCode("print-machineinstrs", + cl::desc("Print generated machine code")); } // allocateX86TargetMachine - Allocate and return a subclass of TargetMachine // that implements the X86 backend. // -TargetMachine *allocateX86TargetMachine() { return new X86TargetMachine(); } +TargetMachine *allocateX86TargetMachine(unsigned Configuration) { + return new X86TargetMachine(Configuration); +} /// X86TargetMachine ctor - Create an ILP32 architecture model /// -X86TargetMachine::X86TargetMachine() : TargetMachine("X86", 1, 4, 4, 4) { +X86TargetMachine::X86TargetMachine(unsigned Config) + : TargetMachine("X86", + (Config & TM::EndianMask) == TM::LittleEndian, + 1, 4, + (Config & TM::PtrSizeMask) == TM::PtrSize64 ? 8 : 4, + (Config & TM::PtrSizeMask) == TM::PtrSize64 ? 8 : 4) { } @@ -46,7 +55,8 @@ // TODO: optional optimizations go here // Print the instruction selected machine code... - DEBUG(PM.add(createMachineFunctionPrinterPass())); + if (PrintCode) + PM.add(createMachineFunctionPrinterPass()); // Perform register allocation to convert to a concrete x86 representation if (NoLocalRA) @@ -58,7 +68,8 @@ // PM.add(createMachineFunctionPrinterPass()); // Print the register-allocated code - DEBUG(PM.add(createX86CodePrinterPass(*this, std::cerr))); + if (PrintCode) + PM.add(createX86CodePrinterPass(*this, std::cerr)); return false; // success! } Index: llvm/lib/Target/X86/X86TargetMachine.h diff -u llvm/lib/Target/X86/X86TargetMachine.h:1.4 llvm/lib/Target/X86/X86TargetMachine.h:1.5 --- llvm/lib/Target/X86/X86TargetMachine.h:1.4 Mon Dec 2 15:50:41 2002 +++ llvm/lib/Target/X86/X86TargetMachine.h Mon Dec 23 18:04:01 2002 @@ -13,7 +13,7 @@ class X86TargetMachine : public TargetMachine { X86InstrInfo instrInfo; public: - X86TargetMachine(); + X86TargetMachine(unsigned Configuration); virtual const X86InstrInfo &getInstrInfo() const { return instrInfo; } virtual const MachineSchedInfo &getSchedInfo() const { abort(); } From lattner at cs.uiuc.edu Mon Dec 23 18:06:01 2002 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Mon Dec 23 18:06:01 2002 Subject: [llvm-commits] CVS: llvm/lib/CodeGen/RegAllocLocal.cpp Message-ID: <200212240005.SAA05202@apoc.cs.uiuc.edu> Changes in directory llvm/lib/CodeGen: RegAllocLocal.cpp updated: 1.6 -> 1.7 --- Log message: Substantial fixes to live range handling, fixing several problems, getting strtol to not miscompile, and fixing bug: 2002-12-23-LocalRAProblem.llx --- Diffs of the changes: Index: llvm/lib/CodeGen/RegAllocLocal.cpp diff -u llvm/lib/CodeGen/RegAllocLocal.cpp:1.6 llvm/lib/CodeGen/RegAllocLocal.cpp:1.7 --- llvm/lib/CodeGen/RegAllocLocal.cpp:1.6 Wed Dec 18 02:14:26 2002 +++ llvm/lib/CodeGen/RegAllocLocal.cpp Mon Dec 23 18:04:55 2002 @@ -61,16 +61,17 @@ void MarkPhysRegRecentlyUsed(unsigned Reg) { assert(!PhysRegsUseOrder.empty() && "No registers used!"); - if (PhysRegsUseOrder.back() != Reg) { - for (unsigned i = PhysRegsUseOrder.size(); i != 0; --i) - if (areRegsEqual(Reg, PhysRegsUseOrder[i-1])) { // remove from middle - unsigned RegMatch = PhysRegsUseOrder[i-1]; - PhysRegsUseOrder.erase(PhysRegsUseOrder.begin()+i-1); - PhysRegsUseOrder.push_back(RegMatch); // Add it to the end of the list - if (RegMatch == Reg) - return; // Found an exact match, exit early - } - } + if (PhysRegsUseOrder.back() == Reg) return; // Already most recently used + + for (unsigned i = PhysRegsUseOrder.size(); i != 0; --i) + if (areRegsEqual(Reg, PhysRegsUseOrder[i-1])) { + unsigned RegMatch = PhysRegsUseOrder[i-1]; // remove from middle + PhysRegsUseOrder.erase(PhysRegsUseOrder.begin()+i-1); + // Add it to the end of the list + PhysRegsUseOrder.push_back(RegMatch); + if (RegMatch == Reg) + return; // Found an exact match, exit early + } } public: @@ -160,11 +161,11 @@ void spillPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator &I, unsigned PhysReg) { std::map::iterator PI = PhysRegsUsed.find(PhysReg); - if (PI != PhysRegsUsed.end()) { // Only spill it if it's used! + if (PI != PhysRegsUsed.end()) { // Only spill it if it's used! spillVirtReg(MBB, I, PI->second, PhysReg); } else if (const unsigned *AliasSet = RegInfo.getAliasSet(PhysReg)) { - // If the selected register aliases any other registers, we must make sure - // that one of the aliases isn't alive... + // If the selected register aliases any other registers, we must make + // sure that one of the aliases isn't alive... for (unsigned i = 0; AliasSet[i]; ++i) { PI = PhysRegsUsed.find(AliasSet[i]); if (PI != PhysRegsUsed.end()) // Spill aliased register... @@ -503,12 +504,15 @@ // Loop over all of the operands of the instruction, spilling registers that // are defined, and marking explicit destinations in the PhysRegsUsed map. + + // FIXME: We don't need to spill a register if this is the last use of the + // value! for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) if (MI->getOperand(i).opIsDef() && MI->getOperand(i).isPhysicalRegister()) { unsigned Reg = MI->getOperand(i).getAllocatedRegNum(); spillPhysReg(MBB, I, Reg); - PhysRegsUsed[Reg] = 0; // It's free now, and it's reserved + PhysRegsUsed[Reg] = 0; // It is free and reserved now PhysRegsUseOrder.push_back(Reg); } @@ -520,11 +524,14 @@ // We don't want to spill implicit definitions if they were explicitly // chosen. For this reason, check to see now if the register we are // to spill has a vreg of 0. - if (PhysRegsUsed.count(Reg) && PhysRegsUsed[Reg] != 0) { + if (PhysRegsUsed.count(Reg) && PhysRegsUsed[Reg] != 0) spillPhysReg(MBB, I, Reg); - PhysRegsUsed[Reg] = 0; // It's free now, and it's reserved - PhysRegsUseOrder.push_back(Reg); - } + else if (PhysRegsUsed.count(Reg)) { + // Remove the entry from PhysRegsUseOrder to avoid having two entries! + removePhysReg(Reg); + } + PhysRegsUseOrder.push_back(Reg); + PhysRegsUsed[Reg] = 0; // It is free and reserved now } // Loop over the implicit uses, making sure that they are at the head of the @@ -534,8 +541,8 @@ MarkPhysRegRecentlyUsed(ImplicitUses[i]); // Loop over all of the operands again, getting the used operands into - // registers. This has the potiential to spill incoming values because we - // are out of registers. + // registers. This has the potiential to spill incoming values if we are + // out of registers. // for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) if (MI->getOperand(i).opIsUse() && @@ -576,16 +583,17 @@ } if (!DisableKill) { - // If this instruction is the last user of anything in registers, kill the - // value, freeing the register being used, so it doesn't need to be spilled - // to memory at the end of the block. + // If this instruction is the last user of anything in registers, kill the + // value, freeing the register being used, so it doesn't need to be + // spilled to memory at the end of the block. std::multimap::iterator LUOI = LastUserOf.lower_bound(MI); - for (; LUOI != LastUserOf.end() && LUOI->first == MI; ++MI) {// entry found? - unsigned VirtReg = LUOI->second; + for (; LUOI != LastUserOf.end() && LUOI->first == MI; ++MI) { + unsigned VirtReg = LUOI->second; // entry found? unsigned PhysReg = Virt2PhysRegMap[VirtReg]; if (PhysReg) { - DEBUG(std::cout << "V: " << VirtReg << " P: " << PhysReg << " Last use of: " << *MI); + DEBUG(std::cout << "V: " << VirtReg << " P: " << PhysReg + << " Last use of: " << *MI); removePhysReg(PhysReg); } Virt2PhysRegMap.erase(VirtReg); @@ -646,7 +654,7 @@ /// void RA::EmitEpilogue(MachineBasicBlock &MBB) { // Insert instructions before the return. - MachineBasicBlock::iterator I = --MBB.end(); + MachineBasicBlock::iterator I = MBB.end()-1; const unsigned *CSRegs = RegInfo.getCalleeSaveRegs(); for (unsigned i = 0; CSRegs[i]; ++i) { From lattner at cs.uiuc.edu Mon Dec 23 18:15:00 2002 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Mon Dec 23 18:15:00 2002 Subject: [llvm-commits] CVS: llvm/tools/jello/Callback.cpp Emitter.cpp GlobalVars.cpp Makefile VM.cpp VM.h jello.cpp Message-ID: <200212240014.SAA05274@apoc.cs.uiuc.edu> Changes in directory llvm/tools/jello: Callback.cpp (r1.3) removed Emitter.cpp (r1.6) removed GlobalVars.cpp (r1.4) removed Makefile (r1.3) removed VM.cpp (r1.6) removed VM.h (r1.5) removed jello.cpp (r1.10) removed --- Log message: Jello is now part of LLI --- Diffs of the changes: From lattner at cs.uiuc.edu Mon Dec 23 18:40:00 2002 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Mon Dec 23 18:40:00 2002 Subject: [llvm-commits] CVS: llvm/tools/lli/ExecutionEngine.cpp lli.cpp Message-ID: <200212240039.SAA06479@apoc.cs.uiuc.edu> Changes in directory llvm/tools/lli: ExecutionEngine.cpp updated: 1.1 -> 1.2 lli.cpp updated: 1.14 -> 1.15 --- Log message: Fixes to compile with GCC 3.2 --- Diffs of the changes: Index: llvm/tools/lli/ExecutionEngine.cpp diff -u llvm/tools/lli/ExecutionEngine.cpp:1.1 llvm/tools/lli/ExecutionEngine.cpp:1.2 --- llvm/tools/lli/ExecutionEngine.cpp:1.1 Mon Dec 23 18:01:01 2002 +++ llvm/tools/lli/ExecutionEngine.cpp Mon Dec 23 18:39:16 2002 @@ -56,7 +56,7 @@ } break; default: - cout << "ERROR: Constant unimp for type: " << C->getType() << "\n"; + std::cout << "ERROR: Constant unimp for type: " << C->getType() << "\n"; } return Result; } @@ -92,7 +92,7 @@ Ptr->Untyped[7] = (Val.ULongVal >> 56) & 255; break; default: - cout << "Cannot store value of type " << Ty << "!\n"; + std::cout << "Cannot store value of type " << Ty << "!\n"; } } else { switch (Ty->getPrimitiveID()) { @@ -123,7 +123,7 @@ Ptr->Untyped[0] = (Val.ULongVal >> 56) & 255; break; default: - cout << "Cannot store value of type " << Ty << "!\n"; + std::cout << "Cannot store value of type " << Ty << "!\n"; } } } @@ -141,7 +141,7 @@ switch (Init->getType()->getPrimitiveID()) { case Type::ArrayTyID: { const ConstantArray *CPA = cast(Init); - const vector &Val = CPA->getValues(); + const std::vector &Val = CPA->getValues(); unsigned ElementSize = getTargetData().getTypeSize(cast(CPA->getType())->getElementType()); for (unsigned i = 0; i < Val.size(); ++i) @@ -153,7 +153,7 @@ const ConstantStruct *CPS = cast(Init); const StructLayout *SL = getTargetData().getStructLayout(cast(CPS->getType())); - const vector &Val = CPS->getValues(); + const std::vector &Val = CPS->getValues(); for (unsigned i = 0; i < Val.size(); ++i) InitializeMemory(cast(Val[i].get()), (char*)Addr+SL->MemberOffsets[i]); Index: llvm/tools/lli/lli.cpp diff -u llvm/tools/lli/lli.cpp:1.14 llvm/tools/lli/lli.cpp:1.15 --- llvm/tools/lli/lli.cpp:1.14 Mon Dec 23 17:59:32 2002 +++ llvm/tools/lli/lli.cpp Mon Dec 23 18:39:16 2002 @@ -51,17 +51,17 @@ " llvm interpreter & dynamic compiler\n"); // Load the bytecode... - string ErrorMsg; + std::string ErrorMsg; Module *M = ParseBytecodeFile(InputFile, &ErrorMsg); if (M == 0) { - cout << "Error parsing '" << InputFile << "': " - << ErrorMsg << "\n"; + std::cout << "Error parsing '" << InputFile << "': " + << ErrorMsg << "\n"; exit(1); } #if 0 // Link in the runtime library for LLI... - string RuntimeLib = getCurrentExecutablePath(); + std::string RuntimeLib = getCurrentExecutablePath(); if (!RuntimeLib.empty()) RuntimeLib += "/"; RuntimeLib += "RuntimeLib.bc"; From lattner at cs.uiuc.edu Mon Dec 23 18:45:01 2002 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Mon Dec 23 18:45:01 2002 Subject: [llvm-commits] CVS: llvm/tools/Makefile Message-ID: <200212240044.SAA18332@apoc.cs.uiuc.edu> Changes in directory llvm/tools: Makefile updated: 1.17 -> 1.18 --- Log message: Don't try to buidl jello --- Diffs of the changes: Index: llvm/tools/Makefile diff -u llvm/tools/Makefile:1.17 llvm/tools/Makefile:1.18 --- llvm/tools/Makefile:1.17 Thu Dec 5 21:53:40 2002 +++ llvm/tools/Makefile Mon Dec 23 18:44:26 2002 @@ -3,12 +3,12 @@ include $(LEVEL)/Makefile.common -ifeq ($(ARCH),x86) +#ifeq ($(ARCH),x86) # Only build jello when we are on X86 -all :: jello/.makeall -install :: jello/.makeinstall -clean :: jello/.makeclean -endif +#all :: jello/.makeall +#install :: jello/.makeinstall +#clean :: jello/.makeclean +#endif From lattner at cs.uiuc.edu Mon Dec 23 18:45:03 2002 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Mon Dec 23 18:45:03 2002 Subject: [llvm-commits] CVS: llvm/tools/bugpoint/ExecutionDriver.cpp SystemUtils.cpp Message-ID: <200212240044.SAA18341@apoc.cs.uiuc.edu> Changes in directory llvm/tools/bugpoint: ExecutionDriver.cpp updated: 1.1 -> 1.2 SystemUtils.cpp updated: 1.1 -> 1.2 --- Log message: Fix compilation on GCC 3.2 --- Diffs of the changes: Index: llvm/tools/bugpoint/ExecutionDriver.cpp diff -u llvm/tools/bugpoint/ExecutionDriver.cpp:1.1 llvm/tools/bugpoint/ExecutionDriver.cpp:1.2 --- llvm/tools/bugpoint/ExecutionDriver.cpp:1.1 Mon Dec 23 17:50:16 2002 +++ llvm/tools/bugpoint/ExecutionDriver.cpp Mon Dec 23 18:44:34 2002 @@ -18,6 +18,7 @@ #include "SystemUtils.h" #include "Support/CommandLine.h" #include +#include namespace { // OutputType - Allow the user to specify the way code should be run, to test Index: llvm/tools/bugpoint/SystemUtils.cpp diff -u llvm/tools/bugpoint/SystemUtils.cpp:1.1 llvm/tools/bugpoint/SystemUtils.cpp:1.2 --- llvm/tools/bugpoint/SystemUtils.cpp:1.1 Mon Dec 23 17:50:16 2002 +++ llvm/tools/bugpoint/SystemUtils.cpp Mon Dec 23 18:44:34 2002 @@ -8,6 +8,7 @@ #include "SystemUtils.h" #include #include +#include #include #include #include From lattner at cs.uiuc.edu Tue Dec 24 23:01:00 2002 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Tue Dec 24 23:01:00 2002 Subject: [llvm-commits] CVS: llvm/include/llvm/CodeGen/MachineFunction.h Message-ID: <200212250500.XAA27029@apoc.cs.uiuc.edu> Changes in directory llvm/include/llvm/CodeGen: MachineFunction.h updated: 1.21 -> 1.22 --- Log message: Remove dependency on SSARegMap.h --- Diffs of the changes: Index: llvm/include/llvm/CodeGen/MachineFunction.h diff -u llvm/include/llvm/CodeGen/MachineFunction.h:1.21 llvm/include/llvm/CodeGen/MachineFunction.h:1.22 --- llvm/include/llvm/CodeGen/MachineFunction.h:1.21 Fri Nov 22 16:32:15 2002 +++ llvm/include/llvm/CodeGen/MachineFunction.h Tue Dec 24 23:00:16 2002 @@ -10,7 +10,6 @@ #define LLVM_CODEGEN_MACHINEFUNCTION_H #include "llvm/CodeGen/MachineBasicBlock.h" -#include "llvm/CodeGen/SSARegMap.h" #include "llvm/Annotation.h" #include "Support/HashExtras.h" #include "Support/hash_set" @@ -22,6 +21,7 @@ class Type; class TargetMachine; class Pass; +class SSARegMap; Pass *createMachineCodeConstructionPass(TargetMachine &Target); Pass *createMachineCodeDestructionPass(); @@ -34,6 +34,9 @@ // List of machine basic blocks in function iplist BasicBlocks; + // Keeping track of mapping from SSA values to registers + SSARegMap *SSARegMapping; + // FIXME: State should be held elsewhere... hash_set constantsForConstPool; hash_map offsets; @@ -48,11 +51,9 @@ bool spillsAreaFrozen; bool automaticVarsAreaFrozen; - // Keeping track of mapping from SSA values to registers - SSARegMap *SSARegMapping; - public: MachineFunction(const Function *Fn, const TargetMachine& target); + ~MachineFunction(); /// getFunction - Return the LLVM function that this machine code represents /// @@ -71,11 +72,6 @@ /// void dump() const; - /// CalculateArgSize - Call this method to fill in the maxOptionalArgsSize & - /// staticStackSize fields... - /// - void CalculateArgSize(); - // The next three methods are used to construct, destruct, and retrieve the // MachineFunction object for the given method. // @@ -90,18 +86,6 @@ static void destruct(const Function *F); static MachineFunction& get(const Function *F); - // Getting and storing SSARegMap information - const TargetRegisterClass* getRegClass(unsigned Reg) { - return SSARegMapping->getRegClass(Reg); - } - void addRegMap(unsigned Reg, const TargetRegisterClass *RegClass) { - SSARegMapping->addRegMap(Reg, RegClass); - } - void clearSSARegMap() { - delete SSARegMapping; - SSARegMapping = NULL; - } - // Provide accessors for the MachineBasicBlock list... typedef iplist BasicBlockListType; typedef BasicBlockListType::iterator iterator; @@ -134,11 +118,24 @@ MachineBasicBlock & back() { return BasicBlocks.back(); } //===--------------------------------------------------------------------===// + // SSARegMap Interface... Keep track of information about each SSA virtual + // register, such as which register class it belongs to. // - // FIXME: Most of the following state should be moved out to passes that use - // it, instead of being put here. + + SSARegMap *getSSARegMap() const { return SSARegMapping; } + void clearSSARegMap(); + + + //===--------------------------------------------------------------------===// + // + // FIXME: Most of the following state should be moved into another class! // + /// CalculateArgSize - Call this method to fill in the maxOptionalArgsSize & + /// staticStackSize fields... + /// + void CalculateArgSize(); + // // Accessors for global information about generated code for a method. // @@ -181,8 +178,6 @@ void freezeAutomaticVarsArea () { automaticVarsAreaFrozen=true; } int getOffset (const Value* val) const; - - // int getOffsetFromFP (const Value* val) const; private: inline void incrementAutomaticVarsSize(int incr) { From lattner at cs.uiuc.edu Tue Dec 24 23:01:03 2002 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Tue Dec 24 23:01:03 2002 Subject: [llvm-commits] CVS: llvm/include/llvm/CodeGen/MachineInstr.h Message-ID: <200212250500.XAA27182@apoc.cs.uiuc.edu> Changes in directory llvm/include/llvm/CodeGen: MachineInstr.h updated: 1.92 -> 1.93 --- Log message: (null) --- Diffs of the changes: Index: llvm/include/llvm/CodeGen/MachineInstr.h diff -u llvm/include/llvm/CodeGen/MachineInstr.h:1.92 llvm/include/llvm/CodeGen/MachineInstr.h:1.93 --- llvm/include/llvm/CodeGen/MachineInstr.h:1.92 Sun Dec 15 16:05:02 2002 +++ llvm/include/llvm/CodeGen/MachineInstr.h Tue Dec 24 23:00:49 2002 @@ -80,6 +80,7 @@ MO_UnextendedImmed, MO_PCRelativeDisp, MO_MachineBasicBlock, // MachineBasicBlock reference + MO_FrameIndex, // Abstract Stack Frame Index }; private: @@ -182,28 +183,27 @@ bool isImmediate() const { return opType == MO_SignExtendedImmed || opType == MO_UnextendedImmed; } + bool isFrameIndex() const { return opType == MO_FrameIndex; } - inline Value* getVRegValue () const { + Value* getVRegValue() const { assert(opType == MO_VirtualRegister || opType == MO_CCRegister || - opType == MO_PCRelativeDisp); + isPCRelativeDisp()); return value; } - inline Value* getVRegValueOrNull() const { + Value* getVRegValueOrNull() const { return (opType == MO_VirtualRegister || opType == MO_CCRegister || - opType == MO_PCRelativeDisp)? value : NULL; + isPCRelativeDisp()) ? value : NULL; } - inline int getMachineRegNum() const { + int getMachineRegNum() const { assert(opType == MO_MachineRegister); return regNum; } - inline int64_t getImmedValue () const { - assert(isImmediate()); - return immedVal; - } + int64_t getImmedValue() const { assert(isImmediate()); return immedVal; } MachineBasicBlock *getMachineBasicBlock() const { assert(isMachineBasicBlock() && "Can't get MBB in non-MBB operand!"); return MBB; } + unsigned getFrameIndex() const { assert(isFrameIndex()); return immedVal; } bool opIsUse () const { return (flags & USEDEFMASK) == 0; } bool opIsDef () const { return flags & DEFFLAG; } @@ -214,20 +214,20 @@ bool opLoBits64 () const { return flags & LOFLAG64; } // used to check if a machine register has been allocated to this operand - inline bool hasAllocatedReg() const { + bool hasAllocatedReg() const { return (regNum >= 0 && (opType == MO_VirtualRegister || opType == MO_CCRegister || opType == MO_MachineRegister)); } // used to get the reg number if when one is allocated - inline int getAllocatedRegNum() const { + int getAllocatedRegNum() const { assert(opType == MO_VirtualRegister || opType == MO_CCRegister || opType == MO_MachineRegister); return regNum; } - inline unsigned getReg() const { + unsigned getReg() const { assert(hasAllocatedReg() && "Cannot call MachineOperand::getReg()!"); return regNum; } @@ -509,6 +509,14 @@ assert(!OperandsComplete() && "Trying to add an operand to a machine instr that is already done!"); operands.push_back(MachineOperand(MBB)); + } + + /// addFrameIndexOperand - Add an abstract frame index to the instruction + /// + void addFrameIndexOperand(unsigned Idx) { + assert(!OperandsComplete() && + "Trying to add an operand to a machine instr that is already done!"); + operands.push_back(MachineOperand(Idx, MachineOperand::MO_FrameIndex)); } unsigned substituteValue(const Value* oldVal, Value* newVal, From lattner at cs.uiuc.edu Tue Dec 24 23:02:01 2002 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Tue Dec 24 23:02:01 2002 Subject: [llvm-commits] CVS: llvm/include/llvm/CodeGen/MachineInstrBuilder.h Message-ID: <200212250501.XAA27289@apoc.cs.uiuc.edu> Changes in directory llvm/include/llvm/CodeGen: MachineInstrBuilder.h updated: 1.9 -> 1.10 --- Log message: Add abstract frame index capability --- Diffs of the changes: Index: llvm/include/llvm/CodeGen/MachineInstrBuilder.h diff -u llvm/include/llvm/CodeGen/MachineInstrBuilder.h:1.9 llvm/include/llvm/CodeGen/MachineInstrBuilder.h:1.10 --- llvm/include/llvm/CodeGen/MachineInstrBuilder.h:1.9 Sun Dec 15 02:01:02 2002 +++ llvm/include/llvm/CodeGen/MachineInstrBuilder.h Tue Dec 24 23:01:18 2002 @@ -48,7 +48,7 @@ /// (Same as addReg(RegNo, true) but shorter and more obvious). /// const MachineInstrBuilder &addClobber(int RegNo) const { - MI->addRegOperand(RegNo, true); + MI->addRegOperand(RegNo, MOTy::Def); return *this; } @@ -84,6 +84,11 @@ const MachineInstrBuilder &addMBB(MachineBasicBlock *MBB) const { MI->addMachineBasicBlockOperand(MBB); + return *this; + } + + const MachineInstrBuilder &addFrameIndex(unsigned Idx) const { + MI->addFrameIndexOperand(Idx); return *this; } }; From lattner at cs.uiuc.edu Tue Dec 24 23:02:03 2002 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Tue Dec 24 23:02:03 2002 Subject: [llvm-commits] CVS: llvm/include/llvm/CodeGen/SSARegMap.h Message-ID: <200212250501.XAA27395@apoc.cs.uiuc.edu> Changes in directory llvm/include/llvm/CodeGen: SSARegMap.h updated: 1.1 -> 1.2 --- Log message: Remove default ctor --- Diffs of the changes: Index: llvm/include/llvm/CodeGen/SSARegMap.h diff -u llvm/include/llvm/CodeGen/SSARegMap.h:1.1 llvm/include/llvm/CodeGen/SSARegMap.h:1.2 --- llvm/include/llvm/CodeGen/SSARegMap.h:1.1 Tue Nov 19 18:53:10 2002 +++ llvm/include/llvm/CodeGen/SSARegMap.h Tue Dec 24 23:01:05 2002 @@ -22,8 +22,6 @@ } public: - SSARegMap() {} - const TargetRegisterClass* getRegClass(unsigned Reg) { unsigned actualReg = rescale(Reg); assert(actualReg < RegClassMap.size() && "Register out of bounds"); From lattner at cs.uiuc.edu Tue Dec 24 23:03:01 2002 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Tue Dec 24 23:03:01 2002 Subject: [llvm-commits] CVS: llvm/include/llvm/Target/MRegisterInfo.h Message-ID: <200212250502.XAA27671@apoc.cs.uiuc.edu> Changes in directory llvm/include/llvm/Target: MRegisterInfo.h updated: 1.13 -> 1.14 --- Log message: Simplify spill interface methods --- Diffs of the changes: Index: llvm/include/llvm/Target/MRegisterInfo.h diff -u llvm/include/llvm/Target/MRegisterInfo.h:1.13 llvm/include/llvm/Target/MRegisterInfo.h:1.14 --- llvm/include/llvm/Target/MRegisterInfo.h:1.13 Mon Dec 16 22:20:39 2002 +++ llvm/include/llvm/Target/MRegisterInfo.h Tue Dec 24 23:02:00 2002 @@ -168,27 +168,27 @@ virtual void emitPrologue(MachineFunction &MF, unsigned Bytes) const = 0; virtual void emitEpilogue(MachineBasicBlock &MBB, unsigned Bytes) const = 0; - virtual MachineBasicBlock::iterator - storeReg2RegOffset(MachineBasicBlock &MBB, - MachineBasicBlock::iterator MBBI, - unsigned SrcReg, unsigned DestReg, - unsigned ImmOffset, unsigned dataSize) const = 0; + virtual void storeReg2RegOffset(MachineBasicBlock &MBB, + MachineBasicBlock::iterator &MBBI, + unsigned SrcReg, unsigned DestReg, + unsigned ImmOffset, + const TargetRegisterClass *RC) const = 0; - virtual MachineBasicBlock::iterator - loadRegOffset2Reg(MachineBasicBlock &MBB, - MachineBasicBlock::iterator MBBI, - unsigned DestReg, unsigned SrcReg, - unsigned ImmOffset, unsigned dataSize) const = 0; + virtual void loadRegOffset2Reg(MachineBasicBlock &MBB, + MachineBasicBlock::iterator &MBBI, + unsigned DestReg, unsigned SrcReg, + unsigned ImmOffset, + const TargetRegisterClass *RC) const = 0; - virtual MachineBasicBlock::iterator - moveReg2Reg(MachineBasicBlock &MBB, - MachineBasicBlock::iterator MBBI, - unsigned DestReg, unsigned SrcReg, unsigned dataSize) const = 0; + virtual void moveReg2Reg(MachineBasicBlock &MBB, + MachineBasicBlock::iterator &MBBI, + unsigned DestReg, unsigned SrcReg, + const TargetRegisterClass *RC) const = 0; - virtual MachineBasicBlock::iterator - moveImm2Reg(MachineBasicBlock &MBB, - MachineBasicBlock::iterator MBBI, - unsigned DestReg, unsigned Imm, unsigned dataSize) const = 0; + virtual void moveImm2Reg(MachineBasicBlock &MBB, + MachineBasicBlock::iterator &MBBI, + unsigned DestReg, unsigned Imm, + const TargetRegisterClass *RC) const = 0; }; #endif From lattner at cs.uiuc.edu Tue Dec 24 23:03:02 2002 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Tue Dec 24 23:03:02 2002 Subject: [llvm-commits] CVS: llvm/include/llvm/Target/MachineInstrInfo.h Message-ID: <200212250502.XAA27751@apoc.cs.uiuc.edu> Changes in directory llvm/include/llvm/Target: MachineInstrInfo.h updated: 1.38 -> 1.39 --- Log message: Add comment --- Diffs of the changes: Index: llvm/include/llvm/Target/MachineInstrInfo.h diff -u llvm/include/llvm/Target/MachineInstrInfo.h:1.38 llvm/include/llvm/Target/MachineInstrInfo.h:1.39 --- llvm/include/llvm/Target/MachineInstrInfo.h:1.38 Sun Dec 15 16:16:08 2002 +++ llvm/include/llvm/Target/MachineInstrInfo.h Tue Dec 24 23:01:46 2002 @@ -53,7 +53,7 @@ const unsigned M_PREFETCH_FLAG = 1 << 11; const unsigned M_STORE_FLAG = 1 << 12; const unsigned M_DUMMY_PHI_FLAG = 1 << 13; -const unsigned M_PSEUDO_FLAG = 1 << 14; +const unsigned M_PSEUDO_FLAG = 1 << 14; // Pseudo instruction // 3-addr instructions which really work like 2-addr ones, eg. X86 add/sub const unsigned M_2_ADDR_FLAG = 1 << 15; From lattner at cs.uiuc.edu Tue Dec 24 23:04:01 2002 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Tue Dec 24 23:04:01 2002 Subject: [llvm-commits] CVS: llvm/lib/CodeGen/MachineFunction.cpp Message-ID: <200212250503.XAA28119@apoc.cs.uiuc.edu> Changes in directory llvm/lib/CodeGen: MachineFunction.cpp updated: 1.31 -> 1.32 --- Log message: Remove dependency on SSARegMap.h by MachineFunction.h --- Diffs of the changes: Index: llvm/lib/CodeGen/MachineFunction.cpp diff -u llvm/lib/CodeGen/MachineFunction.cpp:1.31 llvm/lib/CodeGen/MachineFunction.cpp:1.32 --- llvm/lib/CodeGen/MachineFunction.cpp:1.31 Sun Dec 15 14:35:25 2002 +++ llvm/lib/CodeGen/MachineFunction.cpp Tue Dec 24 23:03:22 2002 @@ -6,9 +6,10 @@ // //===----------------------------------------------------------------------===// -#include "llvm/CodeGen/MachineInstr.h" // For debug output #include "llvm/CodeGen/MachineFunction.h" +#include "llvm/CodeGen/MachineInstr.h" #include "llvm/CodeGen/MachineCodeForInstruction.h" +#include "llvm/CodeGen/SSARegMap.h" #include "llvm/Target/TargetMachine.h" #include "llvm/Target/MachineFrameInfo.h" #include "llvm/Target/MachineCacheInfo.h" @@ -95,14 +96,18 @@ MachineFunction::MachineFunction(const Function *F, const TargetMachine& target) - : Annotation(MF_AID), - Fn(F), Target(target), staticStackSize(0), - automaticVarsSize(0), regSpillsSize(0), - maxOptionalArgsSize(0), maxOptionalNumArgs(0), - currentTmpValuesSize(0), maxTmpValuesSize(0), compiledAsLeaf(false), - spillsAreaFrozen(false), automaticVarsAreaFrozen(false) -{ + : Annotation(MF_AID), Fn(F), Target(target) { SSARegMapping = new SSARegMap(); + + // FIXME: move state into another class + staticStackSize = automaticVarsSize = regSpillsSize = 0; + maxOptionalArgsSize = maxOptionalNumArgs = currentTmpValuesSize = 0; + maxTmpValuesSize = 0; + compiledAsLeaf = spillsAreaFrozen = automaticVarsAreaFrozen = false; +} + +MachineFunction::~MachineFunction() { + delete SSARegMapping; } void MachineFunction::dump() const { print(std::cerr); } @@ -152,6 +157,12 @@ assert(mc && "Call construct() method first to allocate the object"); return *mc; } + +void MachineFunction::clearSSARegMap() { + delete SSARegMapping; + SSARegMapping = 0; +} + static unsigned ComputeMaxOptionalArgsSize(const TargetMachine& target, const Function *F, From lattner at cs.uiuc.edu Tue Dec 24 23:05:01 2002 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Tue Dec 24 23:05:01 2002 Subject: [llvm-commits] CVS: llvm/lib/CodeGen/RegAllocSimple.cpp Message-ID: <200212250504.XAA28144@apoc.cs.uiuc.edu> Changes in directory llvm/lib/CodeGen: RegAllocSimple.cpp updated: 1.33 -> 1.34 --- Log message: Adjustments to work with the simpler spill interface --- Diffs of the changes: Index: llvm/lib/CodeGen/RegAllocSimple.cpp diff -u llvm/lib/CodeGen/RegAllocSimple.cpp:1.33 llvm/lib/CodeGen/RegAllocSimple.cpp:1.34 --- llvm/lib/CodeGen/RegAllocSimple.cpp:1.33 Mon Dec 23 17:44:04 2002 +++ llvm/lib/CodeGen/RegAllocSimple.cpp Tue Dec 24 23:04:20 2002 @@ -6,6 +6,7 @@ #include "llvm/CodeGen/MachineFunction.h" #include "llvm/CodeGen/MachineInstr.h" +#include "llvm/CodeGen/SSARegMap.h" #include "llvm/Target/MachineInstrInfo.h" #include "llvm/Target/TargetMachine.h" #include "Support/Statistic.h" @@ -145,11 +146,11 @@ } unsigned RegAllocSimple::getFreeReg(unsigned virtualReg) { - const TargetRegisterClass* regClass = MF->getRegClass(virtualReg); + const TargetRegisterClass* RC = MF->getSSARegMap()->getRegClass(virtualReg); - unsigned regIdx = RegClassIdx[regClass]++; - assert(regIdx < regClass->getNumRegs() && "Not enough registers!"); - unsigned physReg = regClass->getRegister(regIdx); + unsigned regIdx = RegClassIdx[RC]++; + assert(regIdx < RC->getNumRegs() && "Not enough registers!"); + unsigned physReg = RC->getRegister(regIdx); if (RegsUsed.find(physReg) == RegsUsed.end()) return physReg; @@ -160,14 +161,14 @@ unsigned RegAllocSimple::reloadVirtReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator &I, unsigned VirtReg) { - const TargetRegisterClass* regClass = MF->getRegClass(VirtReg); - unsigned stackOffset = getStackSpaceFor(VirtReg, regClass); + const TargetRegisterClass* RC = MF->getSSARegMap()->getRegClass(VirtReg); + unsigned stackOffset = getStackSpaceFor(VirtReg, RC); unsigned PhysReg = getFreeReg(VirtReg); // Add move instruction(s) ++NumReloaded; - I = RegInfo->loadRegOffset2Reg(MBB, I, PhysReg, RegInfo->getFramePointer(), - -stackOffset, regClass->getDataSize()); + RegInfo->loadRegOffset2Reg(MBB, I, PhysReg, RegInfo->getFramePointer(), + -stackOffset, RC); return PhysReg; } @@ -175,13 +176,13 @@ MachineBasicBlock::iterator &I, unsigned VirtReg, unsigned PhysReg) { - const TargetRegisterClass* regClass = MF->getRegClass(VirtReg); - unsigned stackOffset = getStackSpaceFor(VirtReg, regClass); + const TargetRegisterClass* RC = MF->getSSARegMap()->getRegClass(VirtReg); + unsigned stackOffset = getStackSpaceFor(VirtReg, RC); // Add move instruction(s) ++NumSpilled; - I = RegInfo->storeReg2RegOffset(MBB, I, PhysReg, RegInfo->getFramePointer(), - -stackOffset, regClass->getDataSize()); + RegInfo->storeReg2RegOffset(MBB, I, PhysReg, RegInfo->getFramePointer(), + -stackOffset, RC); } @@ -234,20 +235,21 @@ // move back to the first branch instruction so new instructions // are inserted right in front of it and not in front of a non-branch + // if (!MII.isBranch(opMI->getOpcode())) ++opI; - unsigned dataSize = MF->getRegClass(virtualReg)->getDataSize(); + const TargetRegisterClass *RC = + MF->getSSARegMap()->getRegClass(virtualReg); // Retrieve the constant value from this op, move it to target // register of the phi if (opVal.isImmediate()) { - opI = RegInfo->moveImm2Reg(opBlock, opI, virtualReg, - (unsigned) opVal.getImmedValue(), - dataSize); + RegInfo->moveImm2Reg(opBlock, opI, virtualReg, + (unsigned) opVal.getImmedValue(), RC); } else { - opI = RegInfo->moveReg2Reg(opBlock, opI, virtualReg, - opVal.getAllocatedRegNum(), dataSize); + RegInfo->moveReg2Reg(opBlock, opI, virtualReg, + opVal.getAllocatedRegNum(), RC); } } } @@ -331,8 +333,8 @@ unsigned Offset = getStackSpaceFor(CSRegs[i], RegClass); // Insert the spill to the stack frame... - I = RegInfo->storeReg2RegOffset(MBB, I,CSRegs[i],RegInfo->getFramePointer(), - -Offset, RegClass->getDataSize()); + RegInfo->storeReg2RegOffset(MBB, I,CSRegs[i],RegInfo->getFramePointer(), + -Offset, RegClass); ++NumSpilled; } @@ -353,8 +355,8 @@ const TargetRegisterClass *RegClass = RegInfo->getRegClass(CSRegs[i]); unsigned Offset = getStackSpaceFor(CSRegs[i], RegClass); - I = RegInfo->loadRegOffset2Reg(MBB, I, CSRegs[i],RegInfo->getFramePointer(), - -Offset, RegClass->getDataSize()); + RegInfo->loadRegOffset2Reg(MBB, I, CSRegs[i],RegInfo->getFramePointer(), + -Offset, RegClass); --I; // Insert in reverse order ++NumReloaded; } From lattner at cs.uiuc.edu Tue Dec 24 23:06:01 2002 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Tue Dec 24 23:06:01 2002 Subject: [llvm-commits] CVS: llvm/lib/CodeGen/RegAllocLocal.cpp Message-ID: <200212250505.XAA28181@apoc.cs.uiuc.edu> Changes in directory llvm/lib/CodeGen: RegAllocLocal.cpp updated: 1.7 -> 1.8 --- Log message: Adjust to simpler spill interface Only spill and reload caller saved registers that are actually modified. --- Diffs of the changes: Index: llvm/lib/CodeGen/RegAllocLocal.cpp diff -u llvm/lib/CodeGen/RegAllocLocal.cpp:1.7 llvm/lib/CodeGen/RegAllocLocal.cpp:1.8 --- llvm/lib/CodeGen/RegAllocLocal.cpp:1.7 Mon Dec 23 18:04:55 2002 +++ llvm/lib/CodeGen/RegAllocLocal.cpp Tue Dec 24 23:05:46 2002 @@ -7,11 +7,13 @@ #include "llvm/CodeGen/MachineFunction.h" #include "llvm/CodeGen/MachineInstr.h" +#include "llvm/CodeGen/SSARegMap.h" #include "llvm/Target/MachineInstrInfo.h" #include "llvm/Target/TargetMachine.h" #include "Support/Statistic.h" #include "Support/CommandLine.h" #include +#include namespace { Statistic<> NumSpilled ("ra-local", "Number of registers spilled"); @@ -25,6 +27,14 @@ const MRegisterInfo &RegInfo; const MachineInstrInfo &MIInfo; unsigned NumBytesAllocated; + + // PhysRegsModified - Keep track of which physical registers are actually + // modified by the function we are code generating. This set allows us to + // only spill caller-saved registers that we actually change. + // + // FIXME: this would be much nicer & faster as a bitset. + // + std::set PhysRegsModified; // Maps SSA Regs => offsets on the stack where these values are stored std::map VirtReg2OffsetMap; @@ -111,11 +121,12 @@ /// EmitPrologue/EmitEpilogue - Use the register info object to add a - /// prologue/epilogue to the function and save/restore any callee saved - /// registers we are responsible for. + /// prologue/epilogue to the function and save/restore the callee saved + /// registers specified by the CSRegs list. /// - void EmitPrologue(); - void EmitEpilogue(MachineBasicBlock &MBB); + void EmitPrologue(const std::vector &CSRegs); + void EmitEpilogue(MachineBasicBlock &MBB, + const std::vector &CSRegs); /// areRegsEqual - This method returns true if the specified registers are /// related to each other. To do this, it checks to see if they are equal @@ -251,12 +262,13 @@ unsigned VirtReg, unsigned PhysReg) { // If this is just a marker register, we don't need to spill it. if (VirtReg != 0) { - const TargetRegisterClass *RegClass = MF->getRegClass(VirtReg); + const TargetRegisterClass *RegClass = + MF->getSSARegMap()->getRegClass(VirtReg); unsigned stackOffset = getStackSpaceFor(VirtReg, RegClass); // Add move instruction(s) - I = RegInfo.storeReg2RegOffset(MBB, I, PhysReg, RegInfo.getFramePointer(), - -stackOffset, RegClass->getDataSize()); + RegInfo.storeReg2RegOffset(MBB, I, PhysReg, RegInfo.getFramePointer(), + -stackOffset, RegClass); ++NumSpilled; // Update statistics Virt2PhysRegMap.erase(VirtReg); // VirtReg no longer available } @@ -289,7 +301,8 @@ /// unsigned RA::getFreeReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator &I, unsigned VirtReg) { - const TargetRegisterClass *RegClass = MF->getRegClass(VirtReg); + const TargetRegisterClass *RegClass = + MF->getSSARegMap()->getRegClass(VirtReg); unsigned PhysReg = 0; // First check to see if we have a free register of the requested type... @@ -377,12 +390,12 @@ unsigned PhysReg = getFreeReg(MBB, I, VirtReg); - const TargetRegisterClass *RegClass = MF->getRegClass(VirtReg); - unsigned StackOffset = getStackSpaceFor(VirtReg, RegClass); + const TargetRegisterClass *RC = MF->getSSARegMap()->getRegClass(VirtReg); + unsigned StackOffset = getStackSpaceFor(VirtReg, RC); // Add move instruction(s) - I = RegInfo.loadRegOffset2Reg(MBB, I, PhysReg, RegInfo.getFramePointer(), - -StackOffset, RegClass->getDataSize()); + RegInfo.loadRegOffset2Reg(MBB, I, PhysReg, RegInfo.getFramePointer(), + -StackOffset, RC); ++NumReloaded; // Update statistics return PhysReg; } @@ -474,17 +487,17 @@ if (!MII.isBranch(opMI->getOpcode())) ++opI; - unsigned dataSize = MF->getRegClass(virtualReg)->getDataSize(); + const TargetRegisterClass *RC = + MF->getSSARegMap()->getRegClass(virtualReg); // Retrieve the constant value from this op, move it to target // register of the phi if (opVal.isImmediate()) { - opI = RegInfo.moveImm2Reg(opBlock, opI, virtualReg, - (unsigned) opVal.getImmedValue(), - dataSize); + RegInfo.moveImm2Reg(opBlock, opI, virtualReg, + (unsigned) opVal.getImmedValue(), RC); } else { - opI = RegInfo.moveReg2Reg(opBlock, opI, virtualReg, - opVal.getAllocatedRegNum(), dataSize); + RegInfo.moveReg2Reg(opBlock, opI, virtualReg, + opVal.getAllocatedRegNum(), RC); } } } @@ -514,6 +527,7 @@ spillPhysReg(MBB, I, Reg); PhysRegsUsed[Reg] = 0; // It is free and reserved now PhysRegsUseOrder.push_back(Reg); + PhysRegsModified.insert(Reg); // Register is modified by current Fn } // Loop over the implicit defs, spilling them, as above. @@ -531,7 +545,8 @@ removePhysReg(Reg); } PhysRegsUseOrder.push_back(Reg); - PhysRegsUsed[Reg] = 0; // It is free and reserved now + PhysRegsUsed[Reg] = 0; // It is free and reserved now + PhysRegsModified.insert(Reg); // Register is modified by current Fn } // Loop over the implicit uses, making sure that they are at the head of the @@ -550,6 +565,7 @@ unsigned VirtSrcReg = MI->getOperand(i).getAllocatedRegNum(); unsigned PhysSrcReg = reloadVirtReg(MBB, I, VirtSrcReg); MI->SetMachineOperandReg(i, PhysSrcReg); // Assign the input register + PhysRegsModified.insert(PhysSrcReg); // Register is modified } // Okay, we have allocated all of the source operands and spilled any values @@ -579,6 +595,7 @@ } else { DestPhysReg = getFreeReg(MBB, I, DestVirtReg); } + PhysRegsModified.insert(DestPhysReg); // Register is modified MI->SetMachineOperandReg(i, DestPhysReg); // Assign the output register } @@ -625,23 +642,18 @@ /// EmitPrologue - Use the register info object to add a prologue to the /// function and save any callee saved registers we are responsible for. /// -void RA::EmitPrologue() { - // Get a list of the callee saved registers, so that we can save them on entry - // to the function. - // - +void RA::EmitPrologue(const std::vector &CSRegs) { MachineBasicBlock &MBB = MF->front(); // Prolog goes in entry BB MachineBasicBlock::iterator I = MBB.begin(); - const unsigned *CSRegs = RegInfo.getCalleeSaveRegs(); - for (unsigned i = 0; CSRegs[i]; ++i) { + for (unsigned i = 0, e = CSRegs.size(); i != e; ++i) { const TargetRegisterClass *RegClass = RegInfo.getRegClass(CSRegs[i]); unsigned Offset = getStackSpaceFor(CSRegs[i], RegClass); // Insert the spill to the stack frame... ++NumSpilled; - I = RegInfo.storeReg2RegOffset(MBB, I, CSRegs[i], RegInfo.getFramePointer(), - -Offset, RegClass->getDataSize()); + RegInfo.storeReg2RegOffset(MBB, I, CSRegs[i], RegInfo.getFramePointer(), + -Offset, RegClass); } // Add prologue to the function... @@ -652,17 +664,17 @@ /// EmitEpilogue - Use the register info object to add a epilogue to the /// function and restore any callee saved registers we are responsible for. /// -void RA::EmitEpilogue(MachineBasicBlock &MBB) { +void RA::EmitEpilogue(MachineBasicBlock &MBB, + const std::vector &CSRegs) { // Insert instructions before the return. MachineBasicBlock::iterator I = MBB.end()-1; - const unsigned *CSRegs = RegInfo.getCalleeSaveRegs(); - for (unsigned i = 0; CSRegs[i]; ++i) { + for (unsigned i = 0, e = CSRegs.size(); i != e; ++i) { const TargetRegisterClass *RegClass = RegInfo.getRegClass(CSRegs[i]); unsigned Offset = getStackSpaceFor(CSRegs[i], RegClass); ++NumReloaded; - I = RegInfo.loadRegOffset2Reg(MBB, I, CSRegs[i], RegInfo.getFramePointer(), - -Offset, RegClass->getDataSize()); + RegInfo.loadRegOffset2Reg(MBB, I, CSRegs[i], RegInfo.getFramePointer(), + -Offset, RegClass); --I; // Insert in reverse order } @@ -706,9 +718,25 @@ MBB != MBBe; ++MBB) AllocateBasicBlock(*MBB); + // Figure out which callee saved registers are modified by the current + // function, thus needing to be saved and restored in the prolog/epilog. + // + const unsigned *CSRegs = RegInfo.getCalleeSaveRegs(); + std::vector RegsToSave; + for (unsigned i = 0; CSRegs[i]; ++i) { + unsigned Reg = CSRegs[i]; + if (PhysRegsModified.count(Reg)) // If modified register... + RegsToSave.push_back(Reg); + else if (const unsigned *AliasSet = RegInfo.getAliasSet(Reg)) + for (unsigned j = 0; AliasSet[j]; ++j) // Check alias registers too... + if (PhysRegsModified.count(AliasSet[j])) { + RegsToSave.push_back(Reg); + break; + } + } // Emit a prologue for the function... - EmitPrologue(); + EmitPrologue(RegsToSave); const MachineInstrInfo &MII = TM.getInstrInfo(); @@ -717,9 +745,10 @@ MBB != MBBe; ++MBB) { // If last instruction is a return instruction, add an epilogue if (MII.isReturn(MBB->back()->getOpcode())) - EmitEpilogue(*MBB); + EmitEpilogue(*MBB, RegsToSave); } + PhysRegsModified.clear(); LastUserOf.clear(); cleanupAfterFunction(); return true; From lattner at cs.uiuc.edu Tue Dec 24 23:07:00 2002 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Tue Dec 24 23:07:00 2002 Subject: [llvm-commits] CVS: llvm/lib/Target/X86/X86TargetMachine.cpp Message-ID: <200212250506.XAA28221@apoc.cs.uiuc.edu> Changes in directory llvm/lib/Target/X86: X86TargetMachine.cpp updated: 1.9 -> 1.10 --- Log message: Free machine code --- Diffs of the changes: Index: llvm/lib/Target/X86/X86TargetMachine.cpp diff -u llvm/lib/Target/X86/X86TargetMachine.cpp:1.9 llvm/lib/Target/X86/X86TargetMachine.cpp:1.10 --- llvm/lib/Target/X86/X86TargetMachine.cpp:1.9 Mon Dec 23 18:04:01 2002 +++ llvm/lib/Target/X86/X86TargetMachine.cpp Tue Dec 24 23:06:21 2002 @@ -64,12 +64,10 @@ else PM.add(createLocalRegisterAllocator(*this)); - // Print the instruction selected machine code... - // PM.add(createMachineFunctionPrinterPass()); - - // Print the register-allocated code - if (PrintCode) + if (PrintCode) // Print the register-allocated code PM.add(createX86CodePrinterPass(*this, std::cerr)); + + PM.add(createMachineCodeDestructionPass()); return false; // success! } From lattner at cs.uiuc.edu Tue Dec 24 23:07:02 2002 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Tue Dec 24 23:07:02 2002 Subject: [llvm-commits] CVS: llvm/lib/Target/X86/X86RegisterInfo.h Message-ID: <200212250506.XAA28305@apoc.cs.uiuc.edu> Changes in directory llvm/lib/Target/X86: X86RegisterInfo.h updated: 1.11 -> 1.12 --- Log message: Adjustments to match new simpler spill interface --- Diffs of the changes: Index: llvm/lib/Target/X86/X86RegisterInfo.h diff -u llvm/lib/Target/X86/X86RegisterInfo.h:1.11 llvm/lib/Target/X86/X86RegisterInfo.h:1.12 --- llvm/lib/Target/X86/X86RegisterInfo.h:1.11 Mon Dec 16 22:19:17 2002 +++ llvm/lib/Target/X86/X86RegisterInfo.h Tue Dec 24 23:06:43 2002 @@ -14,27 +14,23 @@ struct X86RegisterInfo : public MRegisterInfo { X86RegisterInfo(); - MachineBasicBlock::iterator - storeReg2RegOffset(MachineBasicBlock &MBB, - MachineBasicBlock::iterator MBBI, - unsigned DestReg, unsigned SrcReg, - unsigned ImmOffset, unsigned dataSize) const; + void storeReg2RegOffset(MachineBasicBlock &MBB, + MachineBasicBlock::iterator &MBBI, + unsigned SrcReg, unsigned DestReg, unsigned ImmOffset, + const TargetRegisterClass *RC) const; - MachineBasicBlock::iterator - loadRegOffset2Reg(MachineBasicBlock &MBB, - MachineBasicBlock::iterator MBBI, - unsigned DestReg, unsigned SrcReg, - unsigned ImmOffset, unsigned dataSize) const; + void loadRegOffset2Reg(MachineBasicBlock &MBB, + MachineBasicBlock::iterator &MBBI, + unsigned DestReg, unsigned SrcReg, unsigned ImmOffset, + const TargetRegisterClass *RC) const; - MachineBasicBlock::iterator - moveReg2Reg(MachineBasicBlock &MBB, - MachineBasicBlock::iterator MBBI, - unsigned DestReg, unsigned SrcReg, unsigned dataSize) const; + void moveReg2Reg(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI, + unsigned DestReg, unsigned SrcReg, + const TargetRegisterClass *RC) const; - MachineBasicBlock::iterator - moveImm2Reg(MachineBasicBlock &MBB, - MachineBasicBlock::iterator MBBI, - unsigned DestReg, unsigned Imm, unsigned dataSize) const; + void moveImm2Reg(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI, + unsigned DestReg, unsigned Imm, + const TargetRegisterClass *RC) const; unsigned getFramePointer() const; unsigned getStackPointer() const; From lattner at cs.uiuc.edu Tue Dec 24 23:08:01 2002 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Tue Dec 24 23:08:01 2002 Subject: [llvm-commits] CVS: llvm/lib/Target/X86/X86RegisterInfo.cpp Message-ID: <200212250507.XAA28446@apoc.cs.uiuc.edu> Changes in directory llvm/lib/Target/X86: X86RegisterInfo.cpp updated: 1.24 -> 1.25 --- Log message: New simpler spill interface --- Diffs of the changes: Index: llvm/lib/Target/X86/X86RegisterInfo.cpp diff -u llvm/lib/Target/X86/X86RegisterInfo.cpp:1.24 llvm/lib/Target/X86/X86RegisterInfo.cpp:1.25 --- llvm/lib/Target/X86/X86RegisterInfo.cpp:1.24 Mon Dec 23 17:46:55 2002 +++ llvm/lib/Target/X86/X86RegisterInfo.cpp Tue Dec 24 23:07:09 2002 @@ -12,63 +12,59 @@ #include "llvm/CodeGen/MachineInstrBuilder.h" #include "llvm/CodeGen/MachineFunction.h" -unsigned getIdx(unsigned dataSize) { - switch (dataSize) { +static unsigned getIdx(const TargetRegisterClass *RC) { + switch (RC->getDataSize()) { default: assert(0 && "Invalid data size!"); - case 1: return 0; - case 2: return 1; - case 4: return 2; - // FIXME: longs handled as ints - case 8: return 2; + case 1: return 0; + case 2: return 1; + case 4: return 2; + case 10: return 3; } } -MachineBasicBlock::iterator -X86RegisterInfo::storeReg2RegOffset(MachineBasicBlock &MBB, - MachineBasicBlock::iterator MBBI, - unsigned SrcReg, unsigned DestReg, - unsigned ImmOffset, unsigned dataSize) - const -{ - static const unsigned Opcode[] = { X86::MOVrm8, X86::MOVrm16, X86::MOVrm32 }; - MachineInstr *MI = addRegOffset(BuildMI(Opcode[getIdx(dataSize)], 5), +void X86RegisterInfo::storeReg2RegOffset(MachineBasicBlock &MBB, + MachineBasicBlock::iterator &MBBI, + unsigned SrcReg, unsigned DestReg, + unsigned ImmOffset, + const TargetRegisterClass *RC) const { + static const unsigned Opcode[] = + { X86::MOVrm8, X86::MOVrm16, X86::MOVrm32, X86::FSTPr80 }; + MachineInstr *MI = addRegOffset(BuildMI(Opcode[getIdx(RC)], 5), DestReg, ImmOffset).addReg(SrcReg); - return MBB.insert(MBBI, MI)+1; + MBBI = MBB.insert(MBBI, MI)+1; } -MachineBasicBlock::iterator -X86RegisterInfo::loadRegOffset2Reg(MachineBasicBlock &MBB, - MachineBasicBlock::iterator MBBI, - unsigned DestReg, unsigned SrcReg, - unsigned ImmOffset, unsigned dataSize) - const -{ - static const unsigned Opcode[] = { X86::MOVmr8, X86::MOVmr16, X86::MOVmr32 }; - MachineInstr *MI = addRegOffset(BuildMI(Opcode[getIdx(dataSize)], 4, DestReg), +void X86RegisterInfo::loadRegOffset2Reg(MachineBasicBlock &MBB, + MachineBasicBlock::iterator &MBBI, + unsigned DestReg, unsigned SrcReg, + unsigned ImmOffset, + const TargetRegisterClass *RC) const { + static const unsigned Opcode[] = + { X86::MOVmr8, X86::MOVmr16, X86::MOVmr32, X86::FLDr80 }; + MachineInstr *MI = addRegOffset(BuildMI(Opcode[getIdx(RC)], 4, DestReg), SrcReg, ImmOffset); - return MBB.insert(MBBI, MI)+1; + MBBI = MBB.insert(MBBI, MI)+1; } -MachineBasicBlock::iterator -X86RegisterInfo::moveReg2Reg(MachineBasicBlock &MBB, - MachineBasicBlock::iterator MBBI, - unsigned DestReg, unsigned SrcReg, - unsigned dataSize) const -{ - static const unsigned Opcode[] = { X86::MOVrr8, X86::MOVrr16, X86::MOVrr32 }; - MachineInstr *MI = BuildMI(Opcode[getIdx(dataSize)],1,DestReg).addReg(SrcReg); - return MBB.insert(MBBI, MI)+1; -} - -MachineBasicBlock::iterator -X86RegisterInfo::moveImm2Reg(MachineBasicBlock &MBB, - MachineBasicBlock::iterator MBBI, - unsigned DestReg, unsigned Imm, unsigned dataSize) - const -{ - static const unsigned Opcode[] = { X86::MOVir8, X86::MOVir16, X86::MOVir32 }; - MachineInstr *MI = BuildMI(Opcode[getIdx(dataSize)], 1, DestReg).addReg(Imm); - return MBB.insert(MBBI, MI)+1; +void X86RegisterInfo::moveReg2Reg(MachineBasicBlock &MBB, + MachineBasicBlock::iterator &MBBI, + unsigned DestReg, unsigned SrcReg, + const TargetRegisterClass *RC) const { + static const unsigned Opcode[] = + { X86::MOVrr8, X86::MOVrr16, X86::MOVrr32, X86::FpMOV }; + MachineInstr *MI = BuildMI(Opcode[getIdx(RC)],1,DestReg).addReg(SrcReg); + MBBI = MBB.insert(MBBI, MI)+1; +} + +void X86RegisterInfo::moveImm2Reg(MachineBasicBlock &MBB, + MachineBasicBlock::iterator &MBBI, + unsigned DestReg, unsigned Imm, + const TargetRegisterClass *RC) const { + static const unsigned Opcode[] = + { X86::MOVir8, X86::MOVir16, X86::MOVir32, 0 }; + MachineInstr *MI = BuildMI(Opcode[getIdx(RC)], 1, DestReg).addReg(Imm); + assert(MI->getOpcode() != 0 && "Cannot move FP imm to reg yet!"); + MBBI = MBB.insert(MBBI, MI)+1; } @@ -81,15 +77,13 @@ } const unsigned* X86RegisterInfo::getCalleeSaveRegs() const { - static const unsigned CalleeSaveRegs[] = { X86::ESI, X86::EDI, X86::EBX, - MRegisterInfo::NoRegister }; + static const unsigned CalleeSaveRegs[] = { X86::ESI, X86::EDI, X86::EBX, 0 }; return CalleeSaveRegs; } const unsigned* X86RegisterInfo::getCallerSaveRegs() const { - static const unsigned CallerSaveRegs[] = { X86::EAX, X86::ECX, X86::EDX, - MRegisterInfo::NoRegister }; + static const unsigned CallerSaveRegs[] = { X86::EAX, X86::ECX, X86::EDX, 0 }; return CallerSaveRegs; } From lattner at cs.uiuc.edu Tue Dec 24 23:09:00 2002 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Tue Dec 24 23:09:00 2002 Subject: [llvm-commits] CVS: llvm/lib/Target/X86/X86RegisterClasses.cpp X86RegisterInfo.def Message-ID: <200212250508.XAA28566@apoc.cs.uiuc.edu> Changes in directory llvm/lib/Target/X86: X86RegisterClasses.cpp updated: 1.8 -> 1.9 X86RegisterInfo.def updated: 1.10 -> 1.11 --- Log message: Initial support for FP registers --- Diffs of the changes: Index: llvm/lib/Target/X86/X86RegisterClasses.cpp diff -u llvm/lib/Target/X86/X86RegisterClasses.cpp:1.8 llvm/lib/Target/X86/X86RegisterClasses.cpp:1.9 --- llvm/lib/Target/X86/X86RegisterClasses.cpp:1.8 Mon Dec 16 22:19:17 2002 +++ llvm/lib/Target/X86/X86RegisterClasses.cpp Tue Dec 24 23:08:03 2002 @@ -9,6 +9,9 @@ #include "llvm/Type.h" #include "X86.h" +//===----------------------------------------------------------------------===// +// 8 Bit Integer Registers +// namespace { const unsigned ByteRegClassRegs[] = { #define R8(ENUM, NAME, FLAGS, TSFLAGS, ALIAS_SET) X86::ENUM, @@ -18,8 +21,8 @@ TargetRegisterClass X86ByteRegisterClassInstance(1, ByteRegClassRegs, ByteRegClassRegs+sizeof(ByteRegClassRegs)/sizeof(ByteRegClassRegs[0])); -// -// +//===----------------------------------------------------------------------===// +// 16 Bit Integer Registers // const unsigned ShortRegClassRegs[] = { #define R16(ENUM, NAME, FLAGS, TSFLAGS, ALIAS_SET) X86::ENUM, @@ -29,10 +32,9 @@ TargetRegisterClass X86ShortRegisterClassInstance(2, ShortRegClassRegs, ShortRegClassRegs+sizeof(ShortRegClassRegs)/sizeof(ShortRegClassRegs[0])); +//===----------------------------------------------------------------------===// +// 32 Bit Integer Registers // -// -// - const unsigned IntRegClassRegs[] = { #define R32(ENUM, NAME, FLAGS, TSFLAGS, ALIAS_SET) X86::ENUM, #include "X86RegisterInfo.def" @@ -41,10 +43,25 @@ TargetRegisterClass X86IntRegisterClassInstance(4, IntRegClassRegs, IntRegClassRegs+sizeof(IntRegClassRegs)/sizeof(IntRegClassRegs[0])); +//===----------------------------------------------------------------------===// +// Pseudo Floating Point Registers +// + const unsigned PFPRegClassRegs[] = { +#define PFP(ENUM, NAME, FLAGS, TSFLAGS, ALIAS_SET) X86::ENUM, +#include "X86RegisterInfo.def" + }; + + TargetRegisterClass X86FPRegisterClassInstance(10, PFPRegClassRegs, + PFPRegClassRegs+sizeof(PFPRegClassRegs)/sizeof(PFPRegClassRegs[0])); + +//===----------------------------------------------------------------------===// +// Register class array... +// const TargetRegisterClass * const X86RegClasses[] = { &X86ByteRegisterClassInstance, &X86ShortRegisterClassInstance, - &X86IntRegisterClassInstance + &X86IntRegisterClassInstance, + &X86FPRegisterClassInstance, }; } @@ -72,26 +89,23 @@ -const TargetRegisterClass* X86RegisterInfo::getRegClassForType(const Type* Ty) - const { +const TargetRegisterClass* +X86RegisterInfo::getRegClassForType(const Type* Ty) const { switch (Ty->getPrimitiveID()) { + default: assert(0 && "Invalid type to getClass!"); case Type::BoolTyID: case Type::SByteTyID: case Type::UByteTyID: return &X86ByteRegisterClassInstance; case Type::ShortTyID: case Type::UShortTyID: return &X86ShortRegisterClassInstance; - case Type::LongTyID: // None of these are handled yet! - case Type::ULongTyID: // FIXME: Treat these like ints, this is bogus! + case Type::LongTyID: // FIXME: Longs are not handled yet! + case Type::ULongTyID: // FIXME: Treat these like ints, this is bogus! case Type::IntTyID: case Type::UIntTyID: case Type::PointerTyID: return &X86IntRegisterClassInstance; case Type::FloatTyID: - case Type::DoubleTyID: - - default: - assert(0 && "Invalid type to getClass!"); - return 0; // not reached + case Type::DoubleTyID: return &X86FPRegisterClassInstance; } } Index: llvm/lib/Target/X86/X86RegisterInfo.def diff -u llvm/lib/Target/X86/X86RegisterInfo.def:1.10 llvm/lib/Target/X86/X86RegisterInfo.def:1.11 --- llvm/lib/Target/X86/X86RegisterInfo.def:1.10 Mon Dec 16 13:31:48 2002 +++ llvm/lib/Target/X86/X86RegisterInfo.def Tue Dec 24 23:08:03 2002 @@ -27,6 +27,18 @@ R(ENUM, NAME, FLAGS, TSFLAGS, ALIAS_SET) #endif +// Pseudo Floating Point registers +#ifndef PFP +#define PFP(ENUM, NAME, FLAGS, TSFLAGS, ALIAS_SET) \ + R(ENUM, NAME, FLAGS, TSFLAGS, ALIAS_SET) +#endif + +// Floating Point Stack registers +#ifndef FPS +#define FPS(ENUM, NAME, FLAGS, TSFLAGS, ALIAS_SET) \ + R(ENUM, NAME, FLAGS, TSFLAGS, ALIAS_SET) +#endif + // Arguments passed into the R macros // #1: Enum Name - This ends up being a symbol in the X86 namespace // #2: Register name - The name of the register as used by the gnu assembler @@ -69,14 +81,33 @@ R16( DI, "DI" , MRF::INT16, 0, A_DI) // 8 bit registers aliased with registers above as well - R8 ( AL, "AL" , MRF::INT8 , 0, A_AL) - R8 ( CL, "CL" , MRF::INT8 , 0, A_CL) - R8 ( DL, "DL" , MRF::INT8 , 0, A_DL) - R8 ( BL, "BL" , MRF::INT8 , 0, A_BL) - R8 ( AH, "AH" , MRF::INT8 , 0, A_AH) - R8 ( CH, "CH" , MRF::INT8 , 0, A_CH) - R8 ( DH, "DH" , MRF::INT8 , 0, A_DH) - R8 ( BH, "BH" , MRF::INT8 , 0, A_BH) +R8 ( AL, "AL" , MRF::INT8 , 0, A_AL) +R8 ( CL, "CL" , MRF::INT8 , 0, A_CL) +R8 ( DL, "DL" , MRF::INT8 , 0, A_DL) +R8 ( BL, "BL" , MRF::INT8 , 0, A_BL) +R8 ( AH, "AH" , MRF::INT8 , 0, A_AH) +R8 ( CH, "CH" , MRF::INT8 , 0, A_CH) +R8 ( DH, "DH" , MRF::INT8 , 0, A_DH) +R8 ( BH, "BH" , MRF::INT8 , 0, A_BH) + +// Pseudo Floating Point Registers +PFP(FP0, "fp0", MRF::FP80 , 0, 0 /*noalias*/) +PFP(FP1, "fp1", MRF::FP80 , 0, 0 /*noalias*/) +PFP(FP2, "fp2", MRF::FP80 , 0, 0 /*noalias*/) +PFP(FP3, "fp3", MRF::FP80 , 0, 0 /*noalias*/) +PFP(FP4, "fp4", MRF::FP80 , 0, 0 /*noalias*/) +PFP(FP5, "fp5", MRF::FP80 , 0, 0 /*noalias*/) +PFP(FP6, "fp6", MRF::FP80 , 0, 0 /*noalias*/) + +// Floating point stack registers +FPS(ST0, "ST(0)", MRF::FP80, 0, 0) +FPS(ST1, "ST(1)", MRF::FP80, 0, 0) +FPS(ST2, "ST(2)", MRF::FP80, 0, 0) +FPS(ST3, "ST(3)", MRF::FP80, 0, 0) +FPS(ST4, "ST(4)", MRF::FP80, 0, 0) +FPS(ST5, "ST(5)", MRF::FP80, 0, 0) +FPS(ST6, "ST(6)", MRF::FP80, 0, 0) +FPS(ST7, "ST(7)", MRF::FP80, 0, 0) // Flags, Segment registers, etc... @@ -126,3 +157,5 @@ #undef R8 #undef R16 #undef R32 +#undef PFP +#undef FPS From lattner at cs.uiuc.edu Tue Dec 24 23:10:01 2002 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Tue Dec 24 23:10:01 2002 Subject: [llvm-commits] CVS: llvm/lib/Target/X86/Printer.cpp Message-ID: <200212250509.XAA28857@apoc.cs.uiuc.edu> Changes in directory llvm/lib/Target/X86: Printer.cpp updated: 1.30 -> 1.31 --- Log message: Add printer support for Pseudo instructions --- Diffs of the changes: Index: llvm/lib/Target/X86/Printer.cpp diff -u llvm/lib/Target/X86/Printer.cpp:1.30 llvm/lib/Target/X86/Printer.cpp:1.31 --- llvm/lib/Target/X86/Printer.cpp:1.30 Mon Dec 23 17:46:00 2002 +++ llvm/lib/Target/X86/Printer.cpp Tue Dec 24 23:09:01 2002 @@ -111,13 +111,13 @@ static const std::string sizePtr (const MachineInstrDescriptor &Desc) { switch (Desc.TSFlags & X86II::ArgMask) { + default: assert(0 && "Unknown arg size!"); case X86II::Arg8: return "BYTE PTR"; case X86II::Arg16: return "WORD PTR"; case X86II::Arg32: return "DWORD PTR"; - case X86II::Arg64: return "QWORD PTR"; - case X86II::Arg80: return "XWORD PTR"; - case X86II::Arg128: return "128BIT PTR"; // dunno what the real one is - default: return " PTR"; // crack being smoked + case X86II::ArgF32: return "DWORD PTR"; + case X86II::ArgF64: return "QWORD PTR"; + case X86II::ArgF80: return "XWORD PTR"; } } @@ -157,23 +157,38 @@ unsigned Opcode = MI->getOpcode(); const MachineInstrDescriptor &Desc = get(Opcode); - if (Opcode == X86::PHI) { - printOp(O, MI->getOperand(0), RI); - O << " = phi "; - for (unsigned i = 1, e = MI->getNumOperands(); i != e; i+=2) { - if (i != 1) O << ", "; - O << "["; - printOp(O, MI->getOperand(i), RI); - O << ", "; - printOp(O, MI->getOperand(i+1), RI); - O << "]"; + switch (Desc.TSFlags & X86II::FormMask) { + case X86II::Pseudo: + if (Opcode == X86::PHI) { + printOp(O, MI->getOperand(0), RI); + O << " = phi "; + for (unsigned i = 1, e = MI->getNumOperands(); i != e; i+=2) { + if (i != 1) O << ", "; + O << "["; + printOp(O, MI->getOperand(i), RI); + O << ", "; + printOp(O, MI->getOperand(i+1), RI); + O << "]"; + } + } else { + unsigned i = 0; + if (MI->getNumOperands() && MI->getOperand(0).opIsDef()) { + printOp(O, MI->getOperand(0), RI); + O << " = "; + ++i; + } + O << getName(MI->getOpcode()); + + for (unsigned e = MI->getNumOperands(); i != e; ++i) { + O << " "; + if (MI->getOperand(i).opIsDef()) O << "*"; + printOp(O, MI->getOperand(i), RI); + if (MI->getOperand(i).opIsDef()) O << "*"; + } } O << "\n"; return; - } - - switch (Desc.TSFlags & X86II::FormMask) { case X86II::RawFrm: // The accepted forms of Raw instructions are: // 1. nop - No operand required @@ -182,7 +197,7 @@ assert(MI->getNumOperands() == 0 || (MI->getNumOperands() == 1 && MI->getOperand(0).isPCRelativeDisp())&& "Illegal raw instruction!"); - O << getName(MI->getOpCode()) << " "; + O << getName(MI->getOpcode()) << " "; if (MI->getNumOperands() == 1) { printOp(O, MI->getOperand(0), RI); From lattner at cs.uiuc.edu Tue Dec 24 23:10:03 2002 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Tue Dec 24 23:10:03 2002 Subject: [llvm-commits] CVS: llvm/lib/Target/X86/MachineCodeEmitter.cpp Message-ID: <200212250509.XAA28869@apoc.cs.uiuc.edu> Changes in directory llvm/lib/Target/X86: MachineCodeEmitter.cpp updated: 1.15 -> 1.16 --- Log message: Add support for FP prefixes --- Diffs of the changes: Index: llvm/lib/Target/X86/MachineCodeEmitter.cpp diff -u llvm/lib/Target/X86/MachineCodeEmitter.cpp:1.15 llvm/lib/Target/X86/MachineCodeEmitter.cpp:1.16 --- llvm/lib/Target/X86/MachineCodeEmitter.cpp:1.15 Mon Dec 23 17:46:00 2002 +++ llvm/lib/Target/X86/MachineCodeEmitter.cpp Tue Dec 24 23:09:21 2002 @@ -209,9 +209,9 @@ case X86II::Arg8: return 1; case X86II::Arg16: return 2; case X86II::Arg32: return 4; - case X86II::Arg64: return 8; - case X86II::Arg80: return 10; - case X86II::Arg128: return 16; + case X86II::ArgF32: return 4; + case X86II::ArgF64: return 8; + case X86II::ArgF80: return 10; default: assert(0 && "Memory size not set!"); return 0; } @@ -224,10 +224,25 @@ // Emit instruction prefixes if neccesary if (Desc.TSFlags & X86II::OpSize) MCE.emitByte(0x66);// Operand size... - if (Desc.TSFlags & X86II::TB) MCE.emitByte(0x0F);// Two-byte opcode prefix + + switch (Desc.TSFlags & X86II::Op0Mask) { + case X86II::TB: + MCE.emitByte(0x0F); // Two-byte opcode prefix + break; + case X86II::D8: case X86II::D9: case X86II::DA: case X86II::DB: + case X86II::DC: case X86II::DD: case X86II::DE: case X86II::DF: + MCE.emitByte(0xD8 + (Desc.TSFlags & X86II::Op0Mask)-X86II::D8); + break; // Two-byte opcode prefix + + default: break; // No prefix! + } unsigned char BaseOpcode = II.getBaseOpcodeFor(Opcode); switch (Desc.TSFlags & X86II::FormMask) { + default: assert(0 && "Unknown FormMask value!"); + case X86II::Pseudo: + std::cerr << "X86 Machine Code Emitter: Not emitting: " << MI; + break; case X86II::RawFrm: MCE.emitByte(BaseOpcode); From lattner at cs.uiuc.edu Tue Dec 24 23:11:01 2002 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Tue Dec 24 23:11:01 2002 Subject: [llvm-commits] CVS: llvm/lib/Target/X86/X86InstrInfo.h Message-ID: <200212250510.XAA28885@apoc.cs.uiuc.edu> Changes in directory llvm/lib/Target/X86: X86InstrInfo.h updated: 1.17 -> 1.18 --- Log message: Add FP instr prefix byte support Add Pseudo instr class --- Diffs of the changes: Index: llvm/lib/Target/X86/X86InstrInfo.h diff -u llvm/lib/Target/X86/X86InstrInfo.h:1.17 llvm/lib/Target/X86/X86InstrInfo.h:1.18 --- llvm/lib/Target/X86/X86InstrInfo.h:1.17 Thu Dec 12 21:51:55 2002 +++ llvm/lib/Target/X86/X86InstrInfo.h Tue Dec 24 23:09:59 2002 @@ -20,33 +20,38 @@ // instructions. // + // PseudoFrm - This represents an instruction that is a pseudo instruction + // or one that has not been implemented yet. It is illegal to code generate + // it, but tolerated for intermediate implementation stages. + Pseudo = 0, + /// Raw - This form is for instructions that don't have any operands, so /// they are just a fixed opcode value, like 'leave'. - RawFrm = 0, + RawFrm = 1, /// AddRegFrm - This form is used for instructions like 'push r32' that have /// their one register operand added to their opcode. - AddRegFrm = 1, + AddRegFrm = 2, /// MRMDestReg - This form is used for instructions that use the Mod/RM byte /// to specify a destination, which in this case is a register. /// - MRMDestReg = 2, + MRMDestReg = 3, /// MRMDestMem - This form is used for instructions that use the Mod/RM byte /// to specify a destination, which in this case is memory. /// - MRMDestMem = 3, + MRMDestMem = 4, /// MRMSrcReg - This form is used for instructions that use the Mod/RM byte /// to specify a source, which in this case is a register. /// - MRMSrcReg = 4, + MRMSrcReg = 5, /// MRMSrcMem - This form is used for instructions that use the Mod/RM byte /// to specify a source, which in this case is memory. /// - MRMSrcMem = 5, + MRMSrcMem = 6, /// MRMS[0-7][rm] - These forms are used to represent instructions that use /// a Mod/RM byte, and use the middle field to hold extended opcode @@ -69,28 +74,38 @@ /// Void - Set if this instruction produces no value Void = 1 << 5, - // TB - TwoByte - Set if this instruction has a two byte opcode, which - // starts with a 0x0F byte before the real opcode. - TB = 1 << 6, - - // FIXME: There are several more two byte opcode escapes: D8-DF - // Handle this. - // OpSize - Set if this instruction requires an operand size prefix (0x66), // which most often indicates that the instruction operates on 16 bit data // instead of 32 bit data. - OpSize = 1 << 7, + OpSize = 1 << 6, + + // Op0Mask - There are several prefix bytes that are used to form two byte + // opcodes. These are currently 0x0F, and 0xD8-0xDF. This mask is used to + // obtain the setting of this field. If no bits in this field is set, there + // is no prefix byte for obtaining a multibyte opcode. + // + Op0Mask = 0xF << 7, + + // TB - TwoByte - Set if this instruction has a two byte opcode, which + // starts with a 0x0F byte before the real opcode. + TB = 1 << 7, + + // D8-DF - These escape opcodes are used by the floating point unit. These + // values must remain sequential. + D8 = 2 << 7, D9 = 3 << 7, DA = 4 << 7, DB = 5 << 7, + DC = 6 << 7, DD = 7 << 7, DE = 8 << 7, DF = 9 << 7, + + // This three-bit field describes the size of a memory operand. Zero is + // unused so that we can tell if we forgot to set a value. + Arg8 = 1 << 11, + Arg16 = 2 << 11, + Arg32 = 3 << 11, + ArgF32 = 4 << 11, + ArgF64 = 5 << 11, + ArgF80 = 6 << 11, + ArgMask = 7 << 11, - // This three-bit field describes the size of a memory operand. - // I'm just being paranoid not using the zero value; there's - // probably no reason you couldn't use it. - Arg8 = 0x1 << 8, - Arg16 = 0x2 << 8, - Arg32 = 0x3 << 8, - Arg64 = 0x4 << 8, - Arg80 = 0x5 << 8, - Arg128 = 0x6 << 8, - ArgMask = 0x7 << 8, + // Bits 14 -> 31 are unused }; } From lattner at cs.uiuc.edu Tue Dec 24 23:12:01 2002 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Tue Dec 24 23:12:01 2002 Subject: [llvm-commits] CVS: llvm/lib/Target/X86/X86InstrInfo.def Message-ID: <200212250511.XAA28908@apoc.cs.uiuc.edu> Changes in directory llvm/lib/Target/X86: X86InstrInfo.def updated: 1.45 -> 1.46 --- Log message: * Use new pseudo instr form for instructions * Mark CALLpcrel as a RawFrm instruction as required * Eliminate invalid BSWAP16 instruction * Add xchg instructions * Add initial support for FP instructions --- Diffs of the changes: Index: llvm/lib/Target/X86/X86InstrInfo.def diff -u llvm/lib/Target/X86/X86InstrInfo.def:1.45 llvm/lib/Target/X86/X86InstrInfo.def:1.46 --- llvm/lib/Target/X86/X86InstrInfo.def:1.45 Mon Dec 23 17:46:31 2002 +++ llvm/lib/Target/X86/X86InstrInfo.def Tue Dec 24 23:11:46 2002 @@ -53,7 +53,7 @@ // // The first instruction must always be the PHI instruction: -I(PHI , "phi", 0, 0, 0, NoIR, NoIR) +I(PHI , "phi", 0, 0, X86II::Pseudo , NoIR, NoIR) // The second instruction must always be the noop instruction: I(NOOP , "nop", 0x90, 0, X86II::RawFrm | X86II::Void, NoIR, NoIR) // nop @@ -65,7 +65,7 @@ NoIR) // jne foo I(JE , "je", 0x84, M_BRANCH_FLAG, X86II::RawFrm | X86II::TB | X86II::Void, NoIR, NoIR) // je foo -I(CALLpcrel32 , "call", 0xE8, M_BRANCH_FLAG, X86II::Void, NoIR, C_CLOBBER) // call pc+42 +I(CALLpcrel32 , "call", 0xE8, M_BRANCH_FLAG, X86II::Void | X86II::RawFrm, NoIR, C_CLOBBER) // call pc+42 I(CALLr32 , "call", 0xFF, M_BRANCH_FLAG, X86II::Void | X86II::MRMS2r | X86II::Arg32, NoIR, C_CLOBBER) // call [r32] I(CALLm32 , "call", 0xFF, M_BRANCH_FLAG, X86II::Void | X86II::MRMS2m | X86II::Arg32, @@ -75,8 +75,9 @@ I(LEAVE , "leave", 0xC9, 0, X86II::RawFrm, O_EBP, O_EBP) // leave I(BSWAPr32 , "bswap", 0xC8, M_2_ADDR_FLAG, X86II::AddRegFrm | X86II::TB | X86II::Arg32, NoIR, NoIR) // R32 = bswap R32 -I(BSWAPr16 , "bswap", 0xC8, M_2_ADDR_FLAG, X86II::AddRegFrm | X86II::TB | - X86II::OpSize | X86II::Arg16, NoIR, NoIR) // R16 = bswap R16 +I(XCHGrr8 , "xchg" , 0x86, 0, X86II::MRMDestReg | X86II::Arg8, NoIR, NoIR) // xchg(R8, R8) +I(XCHGrr16 , "xchg" , 0x87, 0, X86II::MRMDestReg | X86II::Arg16 | X86II::OpSize, NoIR, NoIR) // xchg(R16, R16) +I(XCHGrr32 , "xchg" , 0x87, 0, X86II::MRMDestReg | X86II::Arg32, NoIR, NoIR) // xchg(R32, R32) // Move instructions I(MOVrr8 , "movb", 0x88, 0, X86II::MRMDestReg, NoIR, NoIR) // R8 = R8 @@ -158,16 +159,6 @@ I(SARir16 , "sarw", 0xC1, M_2_ADDR_FLAG, X86II::MRMS7r | X86II::Arg8 | X86II::OpSize, NoIR, NoIR) // R16 >>= imm8 I(SARir32 , "sarl", 0xC1, M_2_ADDR_FLAG, X86II::MRMS7r | X86II::Arg8, NoIR, NoIR) // R32 >>= imm8 -// Floating point loads -I(FLDr32 , "flds", 0xD9, 0, X86II::MRMS0m, NoIR, NoIR) // push float -I(FLDr64 , "fldl", 0xDD, 0, X86II::MRMS0m, NoIR, NoIR) // push double - -// Floating point compares -I(FUCOMPP , "fucompp", 0xDA, 0, X86II::Void, NoIR, NoIR) // compare+pop2x - -// Floating point flag ops -I(FNSTSWr8 , "fnstsw", 0xDF, 0, X86II::Void, NoIR, O_AX) // AX = fp flags - // Condition code ops, incl. set if equal/not equal/... I(SAHF , "sahf", 0x9E, 0, X86II::RawFrm, O_AH, NoIR) // flags = AH I(SETBr , "setb", 0x92, 0, X86II::TB | X86II::MRMS0r, NoIR, NoIR) // R8 = < unsign @@ -199,6 +190,44 @@ X86II::OpSize, NoIR, NoIR) I(MOVZXr32r8 , "movzx", 0xB6, 0, X86II::MRMSrcReg | X86II::TB, NoIR, NoIR) // R32 = zeroext(R8) I(MOVZXr32r16 , "movzx", 0xB7, 0, X86II::MRMSrcReg | X86II::TB, NoIR, NoIR) // R32 = zeroext(R16) + + +//===----------------------------------------------------------------------===// +// Floating point support +//===----------------------------------------------------------------------===// + +// FIXME: These need to indicate mod/ref sets for FP regs... & FP 'TOP' +// FIXME: Remove Pseudo encodings from some insts + +// Floating point loads & stores... PREFIX ARGTYPE ENCODING REF MOD +I(FLDr32 , "flds" , 0xD9, 0, X86II::ArgF32 | X86II::Pseudo, NoIR, NoIR) // load float MRMS0m +I(FLDr64 , "fldl" , 0xDD, 0, X86II::ArgF64 | X86II::Pseudo, NoIR, NoIR) // load double MRMS0m +I(FLDr80 , "fldx" , 0xDB, 0, X86II::ArgF80 | X86II::Pseudo, NoIR, NoIR) // store extended MRMS5m +I(FSTr32 , "fsts" , 0xD9, 0, X86II::ArgF32 | X86II::Pseudo, NoIR, NoIR) // store float MRMS2m +I(FSTr64 , "fstl" , 0xDD, 0, X86II::ArgF64 | X86II::Pseudo, NoIR, NoIR) // store double MRMS2m +I(FSTPr80 , "fstpx", 0xDB, 0, X86II::ArgF80 | X86II::Pseudo, NoIR, NoIR) // store extended MRMS7m + + +// Floating point constant loads... +I(FLD0 , "fld0" , 0xEE, 0, X86II::D9 | X86II::ArgF80 | X86II::Pseudo, NoIR, NoIR) // load +0.0 RawFrm +I(FLD1 , "fld1" , 0xE8, 0, X86II::D9 | X86II::ArgF80 | X86II::Pseudo, NoIR, NoIR) // load +1.0 RawFrm + +// Floating point pseudo instructions... +I(FpMOV , "FMOV" , 0, M_PSEUDO_FLAG, X86II::ArgF80 | X86II::Pseudo, NoIR, NoIR) // f1 = fmov f2 +I(FpADD , "FADD" , 0, M_PSEUDO_FLAG, X86II::ArgF80 | X86II::Pseudo, NoIR, NoIR) // f1 = fadd f2, f3 +I(FpSUB , "FSUB" , 0, M_PSEUDO_FLAG, X86II::ArgF80 | X86II::Pseudo, NoIR, NoIR) // f1 = fsub f2, f3 +I(FpMUL , "FMUL" , 0, M_PSEUDO_FLAG, X86II::ArgF80 | X86II::Pseudo, NoIR, NoIR) // f1 = fmul f2, f3 +I(FpDIV , "FDIV" , 0, M_PSEUDO_FLAG, X86II::ArgF80 | X86II::Pseudo, NoIR, NoIR) // f1 = fdiv f2, f3 +I(FpREM , "FREM" , 0, M_PSEUDO_FLAG, X86II::ArgF80 | X86II::Pseudo, NoIR, NoIR) // f1 = frem f2, f3 + + +// Floating point compares +//I(FUCOMPP , "fucompp", 0xDA, 0, X86II::Void, NoIR, NoIR) // compare+pop2x + +// Floating point flag ops +//I(FNSTSWr8 , "fnstsw", 0xDF, 0, X86II::Void, NoIR, O_AX) // AX = fp flags + + // At this point, I is dead, so undefine the macro #undef I From lattner at cs.uiuc.edu Tue Dec 24 23:15:01 2002 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Tue Dec 24 23:15:01 2002 Subject: [llvm-commits] CVS: llvm/lib/Target/X86/InstSelectSimple.cpp Message-ID: <200212250514.XAA28927@apoc.cs.uiuc.edu> Changes in directory llvm/lib/Target/X86: InstSelectSimple.cpp updated: 1.77 -> 1.78 --- Log message: * Simplify Value classes * Add initial support for FP constants * Add initial FP support for several instructions --- Diffs of the changes: Index: llvm/lib/Target/X86/InstSelectSimple.cpp diff -u llvm/lib/Target/X86/InstSelectSimple.cpp:1.77 llvm/lib/Target/X86/InstSelectSimple.cpp:1.78 --- llvm/lib/Target/X86/InstSelectSimple.cpp:1.77 Mon Dec 23 18:03:11 2002 +++ llvm/lib/Target/X86/InstSelectSimple.cpp Tue Dec 24 23:13:53 2002 @@ -19,14 +19,12 @@ #include "llvm/Pass.h" #include "llvm/CodeGen/MachineFunction.h" #include "llvm/CodeGen/MachineInstrBuilder.h" +#include "llvm/CodeGen/SSARegMap.h" #include "llvm/Target/TargetMachine.h" #include "llvm/Support/InstVisitor.h" #include "llvm/Target/MRegisterInfo.h" #include -using namespace MOTy; // Get Use, Def, UseAndDef - - /// BMI - A special BuildMI variant that takes an iterator to insert the /// instruction at as well as a basic block. /// this is the version for when you have a destination register in mind. @@ -207,7 +205,9 @@ /// we haven't yet used. unsigned makeAnotherReg(const Type *Ty) { // Add the mapping of regnumber => reg class to MachineFunction - F->addRegMap(CurReg, TM.getRegisterInfo()->getRegClassForType(Ty)); + const TargetRegisterClass *RC = + TM.getRegisterInfo()->getRegClassForType(Ty); + F->getSSARegMap()->addRegMap(CurReg, RC); return CurReg++; } @@ -250,7 +250,7 @@ /// Representation. /// enum TypeClass { - cByte, cShort, cInt, cLong, cFloat, cDouble + cByte, cShort, cInt, cFP, cLong }; /// getClass - Turn a primitive type into a "class" number which is based on the @@ -266,12 +266,11 @@ case Type::UIntTyID: case Type::PointerTyID: return cInt; // Int's and pointers are class #2 + case Type::FloatTyID: + case Type::DoubleTyID: return cFP; // Floating Point is #3 case Type::LongTyID: case Type::ULongTyID: //return cLong; // Longs are class #3 return cInt; // FIXME: LONGS ARE TREATED AS INTS! - - case Type::FloatTyID: return cFloat; // Float is class #4 - case Type::DoubleTyID: return cDouble; // Doubles are class #5 default: assert(0 && "Invalid type to getClass!"); return cByte; // not reached @@ -299,12 +298,12 @@ } std::cerr << "Offending expr: " << C << "\n"; - assert (0 && "Constant expressions not yet handled!\n"); + assert(0 && "Constant expressions not yet handled!\n"); } if (C->getType()->isIntegral()) { unsigned Class = getClassB(C->getType()); - assert(Class != 3 && "Type not handled yet!"); + assert(Class <= cInt && "Type not handled yet!"); static const unsigned IntegralOpcodeTab[] = { X86::MOVir8, X86::MOVir16, X86::MOVir32 @@ -319,6 +318,17 @@ ConstantUInt *CUI = cast(C); BMI(MBB, IP, IntegralOpcodeTab[Class], 1, R).addZImm(CUI->getValue()); } + } else if (ConstantFP *CFP = dyn_cast(C)) { + double Value = CFP->getValue(); + if (Value == +0.0) + BMI(MBB, IP, X86::FLD0, 0, R); + else if (Value == +1.0) + BMI(MBB, IP, X86::FLD1, 0, R); + else { + std::cerr << "Cannot load constant '" << Value << "'!\n"; + assert(0); + } + } else if (isa(C)) { // Copy zero (null pointer) to the register. BMI(MBB, IP, X86::MOVir32, 1, R).addZImm(0); @@ -396,22 +406,25 @@ BuildMI (BB, X86::CMPrr32, 2).addReg (reg1).addReg (reg2); break; +#if 0 // Push the variables on the stack with fldl opcodes. // FIXME: assuming var1, var2 are in memory, if not, spill to // stack first - case cFloat: // Floats + case cFP: // Floats BuildMI (BB, X86::FLDr32, 1).addReg (reg1); BuildMI (BB, X86::FLDr32, 1).addReg (reg2); break; - case cDouble: // Doubles + case cFP (doubles): // Doubles BuildMI (BB, X86::FLDr64, 1).addReg (reg1); BuildMI (BB, X86::FLDr64, 1).addReg (reg2); break; +#endif case cLong: default: visitInstruction(I); } +#if 0 if (CompTy->isFloatingPoint()) { // (Non-trapping) compare and pop twice. BuildMI (BB, X86::FUCOMPP, 0); @@ -420,6 +433,7 @@ // Load real concodes from ax. BuildMI (BB, X86::SAHF, 1).addReg(X86::AH); } +#endif // Emit setOp instruction (extract concode; clobbers ax), // using the following mapping: @@ -442,35 +456,31 @@ /// promote32 - Emit instructions to turn a narrow operand into a 32-bit-wide /// operand, in the specified target register. -void -ISel::promote32 (unsigned targetReg, Value *v) -{ - unsigned vReg = getReg (v); - unsigned Class = getClass (v->getType ()); - bool isUnsigned = v->getType ()->isUnsigned (); - assert (((Class == cByte) || (Class == cShort) || (Class == cInt)) - && "Unpromotable operand class in promote32"); - switch (Class) - { - case cByte: - // Extend value into target register (8->32) - if (isUnsigned) - BuildMI (BB, X86::MOVZXr32r8, 1, targetReg).addReg (vReg); - else - BuildMI (BB, X86::MOVSXr32r8, 1, targetReg).addReg (vReg); - break; - case cShort: - // Extend value into target register (16->32) - if (isUnsigned) - BuildMI (BB, X86::MOVZXr32r16, 1, targetReg).addReg (vReg); - else - BuildMI (BB, X86::MOVSXr32r16, 1, targetReg).addReg (vReg); - break; - case cInt: - // Move value into target register (32->32) - BuildMI (BB, X86::MOVrr32, 1, targetReg).addReg (vReg); - break; - } +void ISel::promote32 (unsigned targetReg, Value *v) { + unsigned vReg = getReg(v); + bool isUnsigned = v->getType()->isUnsigned(); + switch (getClass(v->getType())) { + case cByte: + // Extend value into target register (8->32) + if (isUnsigned) + BuildMI(BB, X86::MOVZXr32r8, 1, targetReg).addReg(vReg); + else + BuildMI(BB, X86::MOVSXr32r8, 1, targetReg).addReg(vReg); + break; + case cShort: + // Extend value into target register (16->32) + if (isUnsigned) + BuildMI(BB, X86::MOVZXr32r16, 1, targetReg).addReg(vReg); + else + BuildMI(BB, X86::MOVSXr32r16, 1, targetReg).addReg(vReg); + break; + case cInt: + // Move value into target register (32->32) + BuildMI(BB, X86::MOVrr32, 1, targetReg).addReg(vReg); + break; + default: + assert(0 && "Unpromotable operand class in promote32"); + } } /// 'ret' instruction - Here we are interested in meeting the x86 ABI. As such, @@ -484,43 +494,30 @@ /// ret long, ulong : Move value into EAX/EDX and return /// ret float/double : Top of FP stack /// -void -ISel::visitReturnInst (ReturnInst &I) -{ - if (I.getNumOperands () == 0) - { - // Emit a 'ret' instruction - BuildMI (BB, X86::RET, 0); - return; - } - Value *rv = I.getOperand (0); - unsigned Class = getClass (rv->getType ()); - switch (Class) - { - // integral return values: extend or move into EAX and return. - case cByte: - case cShort: - case cInt: - promote32 (X86::EAX, rv); - break; - // ret float/double: top of FP stack - // FLD - case cFloat: // Floats - BuildMI (BB, X86::FLDr32, 1).addReg (getReg (rv)); - break; - case cDouble: // Doubles - BuildMI (BB, X86::FLDr64, 1).addReg (getReg (rv)); - break; - case cLong: - // ret long: use EAX(least significant 32 bits)/EDX (most - // significant 32)...uh, I think so Brain, but how do i call - // up the two parts of the value from inside this mouse - // cage? *zort* - default: - visitInstruction (I); - } +void ISel::visitReturnInst (ReturnInst &I) { + if (I.getNumOperands() == 0) { + BuildMI(BB, X86::RET, 0); // Just emit a 'ret' instruction + return; + } + + Value *RetVal = I.getOperand(0); + switch (getClass(RetVal->getType())) { + case cByte: // integral return values: extend or move into EAX and return + case cShort: + case cInt: + promote32(X86::EAX, RetVal); + break; + case cFP: // Floats & Doubles: Return in ST(0) + BuildMI(BB, X86::FpMOV, 1, X86::ST0).addReg(getReg(RetVal)); + break; + case cLong: + // ret long: use EAX(least significant 32 bits)/EDX (most + // significant 32)... + default: + visitInstruction (I); + } // Emit a 'ret' instruction - BuildMI (BB, X86::RET, 0); + BuildMI(BB, X86::RET, 0); } /// visitBranchInst - Handle conditional and unconditional branches here. Note @@ -528,63 +525,52 @@ /// jump to a block that is the immediate successor of the current block, we can /// just make a fall-through. (but we don't currently). /// -void -ISel::visitBranchInst (BranchInst & BI) -{ - if (BI.isConditional ()) - { - BasicBlock *ifTrue = BI.getSuccessor (0); - BasicBlock *ifFalse = BI.getSuccessor (1); // this is really unobvious - - // simplest thing I can think of: compare condition with zero, - // followed by jump-if-equal to ifFalse, and jump-if-nonequal to - // ifTrue - unsigned int condReg = getReg (BI.getCondition ()); - BuildMI (BB, X86::CMPri8, 2).addReg (condReg).addZImm (0); - BuildMI (BB, X86::JNE, 1).addPCDisp (BI.getSuccessor (0)); - BuildMI (BB, X86::JE, 1).addPCDisp (BI.getSuccessor (1)); - } - else // unconditional branch - { - BuildMI (BB, X86::JMP, 1).addPCDisp (BI.getSuccessor (0)); - } +void ISel::visitBranchInst(BranchInst &BI) { + if (BI.isConditional()) { + BasicBlock *ifTrue = BI.getSuccessor(0); + BasicBlock *ifFalse = BI.getSuccessor(1); + + // Compare condition with zero, followed by jump-if-equal to ifFalse, and + // jump-if-nonequal to ifTrue + unsigned int condReg = getReg(BI.getCondition()); + BuildMI(BB, X86::CMPri8, 2).addReg(condReg).addZImm(0); + BuildMI(BB, X86::JNE, 1).addPCDisp(BI.getSuccessor(0)); + BuildMI(BB, X86::JE, 1).addPCDisp(BI.getSuccessor(1)); + } else { // unconditional branch + BuildMI(BB, X86::JMP, 1).addPCDisp(BI.getSuccessor(0)); + } } /// visitCallInst - Push args on stack and do a procedure call instruction. -void -ISel::visitCallInst (CallInst & CI) -{ +void ISel::visitCallInst(CallInst &CI) { // keep a counter of how many bytes we pushed on the stack unsigned bytesPushed = 0; // Push the arguments on the stack in reverse order, as specified by // the ABI. - for (unsigned i = CI.getNumOperands()-1; i >= 1; --i) - { - Value *v = CI.getOperand (i); - switch (getClass (v->getType ())) - { - case cByte: - case cShort: - // Promote V to 32 bits wide, and move the result into EAX, - // then push EAX. - promote32 (X86::EAX, v); - BuildMI (BB, X86::PUSHr32, 1).addReg (X86::EAX); - bytesPushed += 4; - break; - case cInt: - case cFloat: { - unsigned Reg = getReg(v); - BuildMI (BB, X86::PUSHr32, 1).addReg(Reg); - bytesPushed += 4; - break; - } - default: - // FIXME: long/ulong/double args not handled. - visitInstruction (CI); - break; - } + for (unsigned i = CI.getNumOperands()-1; i >= 1; --i) { + Value *v = CI.getOperand(i); + switch (getClass(v->getType())) { + case cByte: + case cShort: + // Promote V to 32 bits wide, and move the result into EAX, + // then push EAX. + promote32 (X86::EAX, v); + BuildMI(BB, X86::PUSHr32, 1).addReg(X86::EAX); + bytesPushed += 4; + break; + case cInt: { + unsigned Reg = getReg(v); + BuildMI(BB, X86::PUSHr32, 1).addReg(Reg); + bytesPushed += 4; + break; + } + default: + // FIXME: long/ulong/float/double args not handled. + visitInstruction(CI); + break; } + } if (Function *F = CI.getCalledFunction()) { // Emit a CALL instruction with PC-relative displacement. @@ -596,13 +582,13 @@ // Adjust the stack by `bytesPushed' amount if non-zero if (bytesPushed > 0) - BuildMI (BB, X86::ADDri32,2,X86::ESP).addReg(X86::ESP).addZImm(bytesPushed); + BuildMI(BB, X86::ADDri32,2, X86::ESP).addReg(X86::ESP).addZImm(bytesPushed); // If there is a return value, scavenge the result from the location the call // leaves it in... // if (CI.getType() != Type::VoidTy) { - unsigned resultTypeClass = getClass (CI.getType ()); + unsigned resultTypeClass = getClass(CI.getType()); switch (resultTypeClass) { case cByte: case cShort: @@ -613,19 +599,12 @@ X86::MOVrr8, X86::MOVrr16, X86::MOVrr32 }; static const unsigned AReg[] = { X86::AL, X86::AX, X86::EAX }; - BuildMI (BB, regRegMove[resultTypeClass], 1, - getReg (CI)).addReg (AReg[resultTypeClass]); + BuildMI(BB, regRegMove[resultTypeClass], 1, getReg(CI)) + .addReg(AReg[resultTypeClass]); break; } - case cFloat: - // Floating-point return values live in %st(0) (i.e., the top of - // the FP stack.) The general way to approach this is to do a - // FSTP to save the top of the FP stack on the real stack, then - // do a MOV to load the top of the real stack into the target - // register. - visitInstruction (CI); // FIXME: add the right args for the calls below - // BuildMI (BB, X86::FSTPm32, 0); - // BuildMI (BB, X86::MOVmr32, 0); + case cFP: // Floating-point return values live in %ST(0) + BuildMI(BB, X86::FpMOV, 1, getReg(CI)).addReg(X86::ST0); break; default: std::cerr << "Cannot get return value for call of type '" @@ -644,13 +623,13 @@ visitInstruction(B); unsigned Class = getClass(B.getType()); - if (Class > 2) // FIXME: Handle longs + if (Class > cFP) // FIXME: Handle longs visitInstruction(B); static const unsigned OpcodeTab[][4] = { // Arithmetic operators - { X86::ADDrr8, X86::ADDrr16, X86::ADDrr32, 0 }, // ADD - { X86::SUBrr8, X86::SUBrr16, X86::SUBrr32, 0 }, // SUB + { X86::ADDrr8, X86::ADDrr16, X86::ADDrr32, X86::FpADD }, // ADD + { X86::SUBrr8, X86::SUBrr16, X86::SUBrr32, X86::FpSUB }, // SUB // Bitwise operators { X86::ANDrr8, X86::ANDrr16, X86::ANDrr32, 0 }, // AND @@ -659,6 +638,7 @@ }; unsigned Opcode = OpcodeTab[OperatorClass][Class]; + assert(Opcode && "Floating point arguments to logical inst?"); unsigned Op0r = getReg(B.getOperand(0)); unsigned Op1r = getReg(B.getOperand(1)); BuildMI(BB, Opcode, 2, getReg(B)).addReg(Op0r).addReg(Op1r); @@ -670,11 +650,19 @@ void ISel::doMultiply(MachineBasicBlock *MBB, MachineBasicBlock::iterator &MBBI, unsigned destReg, const Type *resultType, unsigned op0Reg, unsigned op1Reg) { - unsigned Class = getClass (resultType); - - // FIXME: - assert (Class <= 2 && "Someday, we will learn how to multiply" - "longs and floating-point numbers. This is not that day."); + unsigned Class = getClass(resultType); + switch (Class) { + case cFP: // Floating point multiply + BuildMI(BB, X86::FpMUL, 2, destReg).addReg(op0Reg).addReg(op1Reg); + return; + default: + case cLong: + assert(0 && "doMultiply not implemented for this class yet!"); + case cByte: + case cShort: + case cInt: // Small integerals, handled below... + break; + } static const unsigned Regs[] ={ X86::AL , X86::AX , X86::EAX }; static const unsigned MulOpcode[]={ X86::MULrr8, X86::MULrr16, X86::MULrr32 }; @@ -710,9 +698,26 @@ /// instructions work differently for signed and unsigned operands. /// void ISel::visitDivRem(BinaryOperator &I) { - unsigned Class = getClass(I.getType()); - if (Class > 2) // FIXME: Handle longs - visitInstruction(I); + unsigned Class = getClass(I.getType()); + unsigned Op0Reg = getReg(I.getOperand(0)); + unsigned Op1Reg = getReg(I.getOperand(1)); + unsigned ResultReg = getReg(I); + + switch (Class) { + case cFP: // Floating point multiply + if (I.getOpcode() == Instruction::Div) + BuildMI(BB, X86::FpDIV, 2, ResultReg).addReg(Op0Reg).addReg(Op1Reg); + else + BuildMI(BB, X86::FpREM, 2, ResultReg).addReg(Op0Reg).addReg(Op1Reg); + return; + default: + case cLong: + assert(0 && "div/rem not implemented for this class yet!"); + case cByte: + case cShort: + case cInt: // Small integerals, handled below... + break; + } static const unsigned Regs[] ={ X86::AL , X86::AX , X86::EAX }; static const unsigned MovOpcode[]={ X86::MOVrr8, X86::MOVrr16, X86::MOVrr32 }; @@ -728,8 +733,6 @@ bool isSigned = I.getType()->isSigned(); unsigned Reg = Regs[Class]; unsigned ExtReg = ExtRegs[Class]; - unsigned Op0Reg = getReg(I.getOperand(0)); - unsigned Op1Reg = getReg(I.getOperand(1)); // Put the first operand into one of the A registers... BuildMI(BB, MovOpcode[Class], 1, Reg).addReg(Op0Reg); @@ -749,7 +752,7 @@ unsigned DestReg = (I.getOpcode() == Instruction::Div) ? Reg : ExtReg; // Put the result into the destination register... - BuildMI(BB, MovOpcode[Class], 1, getReg(I)).addReg(DestReg); + BuildMI(BB, MovOpcode[Class], 1, ResultReg).addReg(DestReg); } @@ -765,7 +768,7 @@ bool isOperandSigned = I.getType()->isUnsigned(); unsigned OperandClass = getClass(I.getType()); - if (OperandClass > 2) + if (OperandClass > cInt) visitInstruction(I); // Can't handle longs yet! if (ConstantUInt *CUI = dyn_cast (I.getOperand (1))) @@ -822,13 +825,22 @@ void ISel::visitLoadInst(LoadInst &I) { bool isLittleEndian = TM.getTargetData().isLittleEndian(); bool hasLongPointers = TM.getTargetData().getPointerSize() == 8; + unsigned SrcAddrReg = getReg(I.getOperand(0)); + unsigned DestReg = getReg(I); unsigned Class = getClass(I.getType()); - if (Class > 2) // FIXME: Handle longs and others... - visitInstruction(I); - - static const unsigned Opcode[] = { X86::MOVmr8, X86::MOVmr16, X86::MOVmr32 }; - unsigned SrcAddrReg = getReg(I.getOperand(0)); + switch (Class) { + default: visitInstruction(I); // FIXME: Handle longs... + case cFP: { + // FIXME: Handle endian swapping for FP values. + unsigned Opcode = I.getType() == Type::FloatTy ? X86::FLDr32 : X86::FLDr64; + addDirectMem(BuildMI(BB, Opcode, 4, DestReg), SrcAddrReg); + return; + } + case cInt: // Integers of various sizes handled below + case cShort: + case cByte: break; + } // We need to adjust the input pointer if we are emulating a big-endian // long-pointer target. On these systems, the pointer that we are interested @@ -840,18 +852,40 @@ BuildMI(BB, X86::ADDri32, 2, R).addReg(SrcAddrReg).addZImm(4); SrcAddrReg = R; } - unsigned DestReg = getReg(I); + unsigned IReg = DestReg; if (!isLittleEndian) { // If big endian we need an intermediate stage IReg = makeAnotherReg(I.getType()); std::swap(IReg, DestReg); } + + static const unsigned Opcode[] = { X86::MOVmr8, X86::MOVmr16, X86::MOVmr32 }; addDirectMem(BuildMI(BB, Opcode[Class], 4, DestReg), SrcAddrReg); if (!isLittleEndian) { // Emit the byte swap instruction... - static const unsigned BSWAPOpcode[] = { X86::MOVrr8, X86::BSWAPr16, X86::BSWAPr32 }; - BuildMI(BB, BSWAPOpcode[Class], 1, IReg).addReg(DestReg); + switch (Class) { + case cByte: + // No byteswap neccesary for 8 bit value... + BuildMI(BB, X86::MOVrr8, 1, IReg).addReg(DestReg); + break; + case cInt: + // Use the 32 bit bswap instruction to do a 32 bit swap... + BuildMI(BB, X86::BSWAPr32, 1, IReg).addReg(DestReg); + break; + + case cShort: + // For 16 bit we have to use an xchg instruction, because there is no + // 16-bit bswap. XCHG is neccesarily not in SSA form, so we force things + // into AX to do the xchg. + // + BuildMI(BB, X86::MOVrr16, 1, X86::AX).addReg(DestReg); + BuildMI(BB, X86::XCHGrr8, 2).addReg(X86::AL, MOTy::UseAndDef) + .addReg(X86::AH, MOTy::UseAndDef); + BuildMI(BB, X86::MOVrr16, 1, DestReg).addReg(X86::AX); + break; + default: assert(0 && "Class not handled yet!"); + } } } @@ -862,29 +896,55 @@ void ISel::visitStoreInst(StoreInst &I) { bool isLittleEndian = TM.getTargetData().isLittleEndian(); bool hasLongPointers = TM.getTargetData().getPointerSize() == 8; - unsigned Class = getClass(I.getOperand(0)->getType()); - if (Class > 2) // FIXME: Handle longs and others... - visitInstruction(I); - - static const unsigned Opcode[] = { X86::MOVrm8, X86::MOVrm16, X86::MOVrm32 }; - unsigned ValReg = getReg(I.getOperand(0)); unsigned AddressReg = getReg(I.getOperand(1)); - if (!isLittleEndian && hasLongPointers && isa(I.getOperand(0)->getType())) { + unsigned Class = getClass(I.getOperand(0)->getType()); + switch (Class) { + default: visitInstruction(I); // FIXME: Handle longs... + case cFP: { + // FIXME: Handle endian swapping for FP values. + unsigned Opcode = I.getOperand(0)->getType() == Type::FloatTy ? + X86::FSTr32 : X86::FSTr64; + addDirectMem(BuildMI(BB, Opcode, 1+4), AddressReg).addReg(ValReg); + return; + } + case cInt: // Integers of various sizes handled below + case cShort: + case cByte: break; + } + + if (!isLittleEndian && hasLongPointers && + isa(I.getOperand(0)->getType())) { unsigned R = makeAnotherReg(Type::UIntTy); BuildMI(BB, X86::ADDri32, 2, R).addReg(AddressReg).addZImm(4); AddressReg = R; } - if (!isLittleEndian && Class) { - // Emit the byte swap instruction... - static const unsigned BSWAPOpcode[] = { X86::MOVrr8, X86::BSWAPr16, X86::BSWAPr32 }; - unsigned R = makeAnotherReg(I.getOperand(0)->getType()); - BuildMI(BB, BSWAPOpcode[Class], 1, R).addReg(ValReg); - ValReg = R; + if (!isLittleEndian && Class != cByte) { + // Emit a byte swap instruction... + switch (Class) { + case cInt: { + unsigned R = makeAnotherReg(I.getOperand(0)->getType()); + BuildMI(BB, X86::BSWAPr32, 1, R).addReg(ValReg); + ValReg = R; + break; + } + case cShort: + // For 16 bit we have to use an xchg instruction, because there is no + // 16-bit bswap. XCHG is neccesarily not in SSA form, so we force things + // into AX to do the xchg. + // + BuildMI(BB, X86::MOVrr16, 1, X86::AX).addReg(ValReg); + BuildMI(BB, X86::XCHGrr8, 2).addReg(X86::AL, MOTy::UseAndDef) + .addReg(X86::AH, MOTy::UseAndDef); + ValReg = X86::AX; + break; + default: assert(0 && "Unknown class!"); + } } + static const unsigned Opcode[] = { X86::MOVrm8, X86::MOVrm16, X86::MOVrm32 }; addDirectMem(BuildMI(BB, Opcode[Class], 1+4), AddressReg).addReg(ValReg); } @@ -927,20 +987,20 @@ // 2) Implement casts between values of the same type class (as determined // by getClass) by using a register-to-register move. - unsigned srcClass = getClassB (sourceType); - unsigned targClass = getClass (targetType); + unsigned srcClass = getClassB(sourceType); + unsigned targClass = getClass(targetType); static const unsigned regRegMove[] = { X86::MOVrr8, X86::MOVrr16, X86::MOVrr32 }; - if ((srcClass < cLong) && (targClass < cLong) && (srcClass == targClass)) - { - BuildMI (BB, regRegMove[srcClass], 1, destReg).addReg (operandReg); - return; - } + + if (srcClass <= cInt && targClass <= cInt && srcClass == targClass) { + BuildMI(BB, regRegMove[srcClass], 1, destReg).addReg(operandReg); + return; + } // 3) Handle cast of SMALLER int to LARGER int using a move with sign // extension or zero extension, depending on whether the source type // was signed. - if ((srcClass < cLong) && (targClass < cLong) && (srcClass < targClass)) + if ((srcClass <= cInt) && (targClass <= cInt) && (srcClass < targClass)) { static const unsigned ops[] = { X86::MOVSXr16r8, X86::MOVSXr32r8, X86::MOVSXr32r16, @@ -953,7 +1013,7 @@ } // 4) Handle cast of LARGER int to SMALLER int using a move to EAX // followed by a move out of AX or AL. - if ((srcClass < cLong) && (targClass < cLong) && (srcClass > targClass)) + if ((srcClass <= cInt) && (targClass <= cInt) && (srcClass > targClass)) { static const unsigned AReg[] = { X86::AL, X86::AX, X86::EAX }; BuildMI (BB, regRegMove[srcClass], 1, From lattner at cs.uiuc.edu Tue Dec 24 23:15:03 2002 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Tue Dec 24 23:15:03 2002 Subject: [llvm-commits] CVS: llvm/test/Regression/Jello/test-fp.ll Message-ID: <200212250514.XAA28937@apoc.cs.uiuc.edu> Changes in directory llvm/test/Regression/Jello: test-fp.ll added (r1.1) --- Log message: Initial fp test --- Diffs of the changes: From lattner at cs.uiuc.edu Sat Dec 28 14:01:01 2002 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Sat Dec 28 14:01:01 2002 Subject: [llvm-commits] CVS: llvm/tools/llc/llc.cpp Message-ID: <200212282000.OAA07240@apoc.cs.uiuc.edu> Changes in directory llvm/tools/llc: llc.cpp updated: 1.63 -> 1.64 --- Log message: Eliminate direct access to TargetData structure --- Diffs of the changes: Index: llvm/tools/llc/llc.cpp diff -u llvm/tools/llc/llc.cpp:1.63 llvm/tools/llc/llc.cpp:1.64 --- llvm/tools/llc/llc.cpp:1.63 Tue Oct 29 15:48:33 2002 +++ llvm/tools/llc/llc.cpp Sat Dec 28 14:00:00 2002 @@ -201,7 +201,7 @@ if (Opt->getNormalCtor()) Passes.add(Opt->getNormalCtor()()); else if (Opt->getDataCtor()) - Passes.add(Opt->getDataCtor()(Target.DataLayout)); + Passes.add(Opt->getDataCtor()(Target.getTargetData())); else if (Opt->getTargetCtor()) Passes.add(Opt->getTargetCtor()(Target)); else From lattner at cs.uiuc.edu Sat Dec 28 14:01:05 2002 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Sat Dec 28 14:01:05 2002 Subject: [llvm-commits] CVS: llvm/tools/lli/ExecutionEngine.cpp Message-ID: <200212282000.OAA07250@apoc.cs.uiuc.edu> Changes in directory llvm/tools/lli: ExecutionEngine.cpp updated: 1.2 -> 1.3 --- Log message: Add diagnostic output --- Diffs of the changes: Index: llvm/tools/lli/ExecutionEngine.cpp diff -u llvm/tools/lli/ExecutionEngine.cpp:1.2 llvm/tools/lli/ExecutionEngine.cpp:1.3 --- llvm/tools/lli/ExecutionEngine.cpp:1.2 Mon Dec 23 18:39:16 2002 +++ llvm/tools/lli/ExecutionEngine.cpp Sat Dec 28 14:00:15 2002 @@ -213,6 +213,7 @@ DEBUG(std::cerr << "Global '" << I->getName() << "' -> " << (void*)GlobalAddress[I] << "\n"); } else { + std::cerr << "Global: " << I->getName() << "\n"; assert(0 && "References to external globals not handled yet!"); } From lattner at cs.uiuc.edu Sat Dec 28 14:01:07 2002 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Sat Dec 28 14:01:07 2002 Subject: [llvm-commits] CVS: llvm/test/Regression/Jello/test-fp.ll Message-ID: <200212282000.OAA07269@apoc.cs.uiuc.edu> Changes in directory llvm/test/Regression/Jello: test-fp.ll updated: 1.1 -> 1.2 --- Log message: Test argument passing --- Diffs of the changes: Index: llvm/test/Regression/Jello/test-fp.ll diff -u llvm/test/Regression/Jello/test-fp.ll:1.1 llvm/test/Regression/Jello/test-fp.ll:1.2 --- llvm/test/Regression/Jello/test-fp.ll:1.1 Tue Dec 24 23:14:29 2002 +++ llvm/test/Regression/Jello/test-fp.ll Sat Dec 28 14:00:47 2002 @@ -1,17 +1,18 @@ -double %test(double* %DP) { +double %test(double* %DP, double %Arg) { %D = load double* %DP %V = add double %D, 1.0 %W = sub double %V, %V %X = mul double %W, %W %Y = div double %X, %X %Z = rem double %Y, %Y - store double %Z, double* %DP + %Q = add double %Z, %Arg + store double %Q, double* %DP ret double %Z } int %main() { %X = alloca double - call double %test(double* %X) + call double %test(double* %X, double 1.0) ret int 0 } From lattner at cs.uiuc.edu Sat Dec 28 14:02:01 2002 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Sat Dec 28 14:02:01 2002 Subject: [llvm-commits] CVS: llvm/test/Regression/Jello/test-loadstore.ll Message-ID: <200212282001.OAA07281@apoc.cs.uiuc.edu> Changes in directory llvm/test/Regression/Jello: test-loadstore.ll updated: 1.3 -> 1.4 --- Log message: Add a variable sized alloca to test --- Diffs of the changes: Index: llvm/test/Regression/Jello/test-loadstore.ll diff -u llvm/test/Regression/Jello/test-loadstore.ll:1.3 llvm/test/Regression/Jello/test-loadstore.ll:1.4 --- llvm/test/Regression/Jello/test-loadstore.ll:1.3 Fri Dec 13 03:28:50 2002 +++ llvm/test/Regression/Jello/test-loadstore.ll Sat Dec 28 14:00:33 2002 @@ -11,10 +11,19 @@ ret void } +uint %varalloca(uint %Size) { + %X = alloca uint, uint %Size ;; Variable sized alloca + store uint %Size, uint* %X + %Y = load uint* %X + ret uint %Y +} + int %main() { %A = alloca sbyte %B = alloca short %C = alloca int call void %test(sbyte* %A, short* %B, int* %C) + call uint %varalloca(uint 7) + ret int 0 } From lattner at cs.uiuc.edu Sat Dec 28 14:02:03 2002 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Sat Dec 28 14:02:03 2002 Subject: [llvm-commits] CVS: llvm/test/Regression/Jello/Makefile Message-ID: <200212282001.OAA07295@apoc.cs.uiuc.edu> Changes in directory llvm/test/Regression/Jello: Makefile updated: 1.4 -> 1.5 --- Log message: Add capability to turn on the -no-fp-elim option --- Diffs of the changes: Index: llvm/test/Regression/Jello/Makefile diff -u llvm/test/Regression/Jello/Makefile:1.4 llvm/test/Regression/Jello/Makefile:1.5 --- llvm/test/Regression/Jello/Makefile:1.4 Mon Dec 23 17:51:19 2002 +++ llvm/test/Regression/Jello/Makefile Sat Dec 28 14:01:23 2002 @@ -10,9 +10,15 @@ all:: $(addprefix Output/, $(TESTS:%.ll=%.out)) +LLI_FLAGS = -force-interpreter=false + +ifdef DISABLE_FP_ELIM +LLI_FLAGS += -no-fp-elim +endif + Output/%.out: Output/%.bc $(LLI) @echo "======== Running $< ===================" - $(VERB) $(LLI) -force-interpreter=false -stats $< > $@ 2>&1 || \ + $(VERB) $(LLI) $(LLI_FLAGS) -stats $< > $@ 2>&1 || \ ( cat $@; rm -f $@; $(FAILURE) $@ ) From lattner at cs.uiuc.edu Sat Dec 28 14:02:06 2002 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Sat Dec 28 14:02:06 2002 Subject: [llvm-commits] CVS: llvm/test/Regression/Jello/test-call.ll Message-ID: <200212282001.OAA07302@apoc.cs.uiuc.edu> Changes in directory llvm/test/Regression/Jello: test-call.ll updated: 1.4 -> 1.5 --- Log message: Add another simple call --- Diffs of the changes: Index: llvm/test/Regression/Jello/test-call.ll diff -u llvm/test/Regression/Jello/test-call.ll:1.4 llvm/test/Regression/Jello/test-call.ll:1.5 --- llvm/test/Regression/Jello/test-call.ll:1.4 Fri Dec 13 08:15:20 2002 +++ llvm/test/Regression/Jello/test-call.ll Sat Dec 28 14:01:07 2002 @@ -1,9 +1,14 @@ declare void %exit(int) +int %test(sbyte %C, short %S) { + %X = cast short %S to int + ret int %X +} void %FP(void(int) * %F) { - call void %F(int 0) + %X = call int %test(sbyte 123, short 1024) + call void %F(int %X) ret void } From lattner at cs.uiuc.edu Sat Dec 28 14:04:00 2002 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Sat Dec 28 14:04:00 2002 Subject: [llvm-commits] CVS: llvm/include/llvm/CodeGen/MachineFunctionPass.h Message-ID: <200212282003.OAA07349@apoc.cs.uiuc.edu> Changes in directory llvm/include/llvm/CodeGen: MachineFunctionPass.h added (r1.1) --- Log message: Initial check in of MachineFunctionPass.h --- Diffs of the changes: From lattner at cs.uiuc.edu Sat Dec 28 14:05:01 2002 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Sat Dec 28 14:05:01 2002 Subject: [llvm-commits] CVS: llvm/include/llvm/CodeGen/MachineFunction.h Message-ID: <200212282004.OAA07360@apoc.cs.uiuc.edu> Changes in directory llvm/include/llvm/CodeGen: MachineFunction.h updated: 1.22 -> 1.23 --- Log message: * Pull a bunch of frame and constant pool state out into a new MachineFunctionInfo class * Add a new FunctionFrameInfo object --- Diffs of the changes: Index: llvm/include/llvm/CodeGen/MachineFunction.h diff -u llvm/include/llvm/CodeGen/MachineFunction.h:1.22 llvm/include/llvm/CodeGen/MachineFunction.h:1.23 --- llvm/include/llvm/CodeGen/MachineFunction.h:1.22 Tue Dec 24 23:00:16 2002 +++ llvm/include/llvm/CodeGen/MachineFunction.h Sat Dec 28 14:04:31 2002 @@ -1,8 +1,10 @@ //===-- llvm/CodeGen/MachineFunction.h --------------------------*- C++ -*-===// // -// Collect native machine code information for a method. This allows -// target-specific information about the generated code to be stored with each -// method. +// Collect native machine code for a function. This class contains a list of +// MachineBasicBlock instances that make up the current compiled function. +// +// This class also contains pointers to various classes which hold +// target-specific information about the generated code. // //===----------------------------------------------------------------------===// @@ -11,17 +13,14 @@ #include "llvm/CodeGen/MachineBasicBlock.h" #include "llvm/Annotation.h" -#include "Support/HashExtras.h" -#include "Support/hash_set" #include "Support/ilist" -class Value; class Function; -class Constant; -class Type; class TargetMachine; class Pass; class SSARegMap; +class MachineFunctionInfo; +class FunctionFrameInfo; Pass *createMachineCodeConstructionPass(TargetMachine &Target); Pass *createMachineCodeDestructionPass(); @@ -37,19 +36,11 @@ // Keeping track of mapping from SSA values to registers SSARegMap *SSARegMapping; - // FIXME: State should be held elsewhere... - hash_set constantsForConstPool; - hash_map offsets; - unsigned staticStackSize; - unsigned automaticVarsSize; - unsigned regSpillsSize; - unsigned maxOptionalArgsSize; - unsigned maxOptionalNumArgs; - unsigned currentTmpValuesSize; - unsigned maxTmpValuesSize; - bool compiledAsLeaf; - bool spillsAreaFrozen; - bool automaticVarsAreaFrozen; + // Used to keep track of frame and constant area information for sparc be + MachineFunctionInfo *MFInfo; + + // Keep track of objects allocated on the stack. + FunctionFrameInfo *FrameInfo; public: MachineFunction(const Function *Fn, const TargetMachine& target); @@ -63,6 +54,24 @@ /// const TargetMachine &getTarget() const { return Target; } + /// SSARegMap Interface... Keep track of information about each SSA virtual + /// register, such as which register class it belongs to. + /// + SSARegMap *getSSARegMap() const { return SSARegMapping; } + void clearSSARegMap(); + + /// getFrameInfo - Return the frame info object for the current function. + /// This object contains information about objects allocated on the stack + /// frame of the current function in an abstract way. + /// + FunctionFrameInfo *getFrameInfo() const { return FrameInfo; } + + /// MachineFunctionInfo - Keep track of various per-function pieces of + /// information for the sparc backend. + /// + MachineFunctionInfo *getInfo() const { return MFInfo; } + + /// print - Print out the MachineFunction in a format suitable for debugging /// to the specified stream. /// @@ -116,91 +125,6 @@ MachineBasicBlock &front() { return BasicBlocks.front(); } const MachineBasicBlock & back() const { return BasicBlocks.back(); } MachineBasicBlock & back() { return BasicBlocks.back(); } - - //===--------------------------------------------------------------------===// - // SSARegMap Interface... Keep track of information about each SSA virtual - // register, such as which register class it belongs to. - // - - SSARegMap *getSSARegMap() const { return SSARegMapping; } - void clearSSARegMap(); - - - //===--------------------------------------------------------------------===// - // - // FIXME: Most of the following state should be moved into another class! - // - - /// CalculateArgSize - Call this method to fill in the maxOptionalArgsSize & - /// staticStackSize fields... - /// - void CalculateArgSize(); - - // - // Accessors for global information about generated code for a method. - // - inline bool isCompiledAsLeafMethod() const { return compiledAsLeaf; } - inline unsigned getStaticStackSize() const { return staticStackSize; } - inline unsigned getAutomaticVarsSize() const { return automaticVarsSize; } - inline unsigned getRegSpillsSize() const { return regSpillsSize; } - inline unsigned getMaxOptionalArgsSize() const { return maxOptionalArgsSize;} - inline unsigned getMaxOptionalNumArgs() const { return maxOptionalNumArgs;} - inline const hash_set& - getConstantPoolValues() const {return constantsForConstPool;} - - // - // Modifiers used during code generation - // - void initializeFrameLayout (const TargetMachine& target); - - void addToConstantPool (const Constant* constVal) - { constantsForConstPool.insert(constVal); } - - inline void markAsLeafMethod() { compiledAsLeaf = true; } - - int computeOffsetforLocalVar (const TargetMachine& target, - const Value* local, - unsigned int& getPaddedSize, - unsigned int sizeToUse = 0); - int allocateLocalVar (const TargetMachine& target, - const Value* local, - unsigned int sizeToUse = 0); - - int allocateSpilledValue (const TargetMachine& target, - const Type* type); - - int pushTempValue (const TargetMachine& target, - unsigned int size); - - void popAllTempValues (const TargetMachine& target); - - void freezeSpillsArea () { spillsAreaFrozen = true; } - void freezeAutomaticVarsArea () { automaticVarsAreaFrozen=true; } - - int getOffset (const Value* val) const; - -private: - inline void incrementAutomaticVarsSize(int incr) { - automaticVarsSize+= incr; - staticStackSize += incr; - } - inline void incrementRegSpillsSize(int incr) { - regSpillsSize+= incr; - staticStackSize += incr; - } - inline void incrementTmpAreaSize(int incr) { - currentTmpValuesSize += incr; - if (maxTmpValuesSize < currentTmpValuesSize) - { - staticStackSize += currentTmpValuesSize - maxTmpValuesSize; - maxTmpValuesSize = currentTmpValuesSize; - } - } - inline void resetTmpAreaSize() { - currentTmpValuesSize = 0; - } - int allocateOptionalArg (const TargetMachine& target, - const Type* type); }; #endif From lattner at cs.uiuc.edu Sat Dec 28 14:06:01 2002 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Sat Dec 28 14:06:01 2002 Subject: [llvm-commits] CVS: llvm/include/llvm/CodeGen/MachineInstr.h Message-ID: <200212282005.OAA07371@apoc.cs.uiuc.edu> Changes in directory llvm/include/llvm/CodeGen: MachineInstr.h updated: 1.93 -> 1.94 --- Log message: * Frame indices are signed * Cluster modification methods together --- Diffs of the changes: Index: llvm/include/llvm/CodeGen/MachineInstr.h diff -u llvm/include/llvm/CodeGen/MachineInstr.h:1.93 llvm/include/llvm/CodeGen/MachineInstr.h:1.94 --- llvm/include/llvm/CodeGen/MachineInstr.h:1.93 Tue Dec 24 23:00:49 2002 +++ llvm/include/llvm/CodeGen/MachineInstr.h Sat Dec 28 14:05:44 2002 @@ -203,7 +203,7 @@ assert(isMachineBasicBlock() && "Can't get MBB in non-MBB operand!"); return MBB; } - unsigned getFrameIndex() const { assert(isFrameIndex()); return immedVal; } + int getFrameIndex() const { assert(isFrameIndex()); return immedVal; } bool opIsUse () const { return (flags & USEDEFMASK) == 0; } bool opIsDef () const { return flags & DEFFLAG; } @@ -313,12 +313,6 @@ MachineInstr(MachineBasicBlock *MBB, MachineOpCode Opcode, unsigned numOps); - /// replace - Support to rewrite a machine instruction in place: for now, - /// simply replace() and then set new operands with Set.*Operand methods - /// below. - /// - void replace(MachineOpCode Opcode, unsigned numOperands); - // The opcode. // const MachineOpCode getOpcode() const { return opCode; } @@ -338,10 +332,12 @@ return operands[i]; } + // FIXME: ELIMINATE MachineOperand::MachineOperandType getOperandType(unsigned i) const { return getOperand(i).getType(); } + // FIXME: ELIMINATE: Misleading name: Definition not defined. bool operandIsDefined(unsigned i) const { return getOperand(i).opIsDef(); } @@ -401,21 +397,6 @@ typedef ValOpIterator const_val_op_iterator; typedef ValOpIterator< MachineInstr*, Value*> val_op_iterator; - // Access to set the operands when building the machine instruction - // - void SetMachineOperandVal (unsigned i, - MachineOperand::MachineOperandType operandType, - Value* V, - bool isDef=false, - bool isDefAndUse=false); - - void SetMachineOperandConst (unsigned i, - MachineOperand::MachineOperandType operandType, - int64_t intValue); - - void SetMachineOperandReg (unsigned i, - int regNum, - bool isDef=false); //===--------------------------------------------------------------------===// // Accessors to add operands when building up machine instructions @@ -518,6 +499,35 @@ "Trying to add an operand to a machine instr that is already done!"); operands.push_back(MachineOperand(Idx, MachineOperand::MO_FrameIndex)); } + + + //===--------------------------------------------------------------------===// + // Accessors used to modify instructions in place. + // + // FIXME: Move this stuff to MachineOperand itself! + + /// replace - Support to rewrite a machine instruction in place: for now, + /// simply replace() and then set new operands with Set.*Operand methods + /// below. + /// + void replace(MachineOpCode Opcode, unsigned numOperands); + + // Access to set the operands when building the machine instruction + // + void SetMachineOperandVal (unsigned i, + MachineOperand::MachineOperandType operandType, + Value* V, + bool isDef=false, + bool isDefAndUse=false); + + void SetMachineOperandConst (unsigned i, + MachineOperand::MachineOperandType operandType, + int64_t intValue); + + void SetMachineOperandReg (unsigned i, + int regNum, + bool isDef=false); + unsigned substituteValue(const Value* oldVal, Value* newVal, bool defsOnly = true); From lattner at cs.uiuc.edu Sat Dec 28 14:08:01 2002 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Sat Dec 28 14:08:01 2002 Subject: [llvm-commits] CVS: llvm/include/llvm/CodeGen/MachineFunctionInfo.h Message-ID: <200212282007.OAA07390@apoc.cs.uiuc.edu> Changes in directory llvm/include/llvm/CodeGen: MachineFunctionInfo.h added (r1.1) --- Log message: State for frame and constant pool information pulled out of MachineFunction --- Diffs of the changes: From lattner at cs.uiuc.edu Sat Dec 28 14:08:05 2002 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Sat Dec 28 14:08:05 2002 Subject: [llvm-commits] CVS: llvm/include/llvm/CodeGen/FunctionFrameInfo.h Message-ID: <200212282007.OAA07397@apoc.cs.uiuc.edu> Changes in directory llvm/include/llvm/CodeGen: FunctionFrameInfo.h added (r1.1) --- Log message: Descriptor object used to manage abstract frame references --- Diffs of the changes: From lattner at cs.uiuc.edu Sat Dec 28 14:11:01 2002 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Sat Dec 28 14:11:01 2002 Subject: [llvm-commits] CVS: llvm/include/llvm/Target/MRegisterInfo.h Message-ID: <200212282010.OAA07414@apoc.cs.uiuc.edu> Changes in directory llvm/include/llvm/Target: MRegisterInfo.h updated: 1.14 -> 1.15 --- Log message: * Keep track of register alignment as well as register size * Add comments * Add a new allocation_order iterator for register classes which targets may use to control the register order and available registers based on properties of the function being compiled. * Remove access to FP and SP registers * Add new callframe setup opcode support * Eliminate moveImm2Reg method * Revamp frame offset handling and prolog/epilog code generation --- Diffs of the changes: Index: llvm/include/llvm/Target/MRegisterInfo.h diff -u llvm/include/llvm/Target/MRegisterInfo.h:1.14 llvm/include/llvm/Target/MRegisterInfo.h:1.15 --- llvm/include/llvm/Target/MRegisterInfo.h:1.14 Tue Dec 24 23:02:00 2002 +++ llvm/include/llvm/Target/MRegisterInfo.h Sat Dec 28 14:10:23 2002 @@ -52,23 +52,55 @@ typedef const unsigned* const_iterator; private: - const unsigned RegSize; // Size of register in bytes + const unsigned RegSize, Alignment; // Size & Alignment of register in bytes const iterator RegsBegin, RegsEnd; public: - TargetRegisterClass(unsigned RS, iterator RB, iterator RE) - : RegSize(RS), RegsBegin(RB), RegsEnd(RE) {} + TargetRegisterClass(unsigned RS, unsigned Al, iterator RB, iterator RE) + : RegSize(RS), Alignment(Al), RegsBegin(RB), RegsEnd(RE) {} virtual ~TargetRegisterClass() {} // Allow subclasses + // begin/end - Return all of the registers in this class. iterator begin() const { return RegsBegin; } iterator end() const { return RegsEnd; } + // getNumRegs - Return the number of registers in this class unsigned getNumRegs() const { return RegsEnd-RegsBegin; } + + // getRegister - Return the specified register in the class unsigned getRegister(unsigned i) const { assert(i < getNumRegs() && "Register number out of range!"); return RegsBegin[i]; } - unsigned getDataSize() const { return RegSize; } + /// allocation_order_begin/end - These methods define a range of registers + /// which specify the registers in this class that are valid to register + /// allocate, and the preferred order to allocate them in. For example, + /// callee saved registers should be at the end of the list, because it is + /// cheaper to allocate caller saved registers. + /// + /// These methods take a MachineFunction argument, which can be used to tune + /// the allocatable registers based on the characteristics of the function. + /// One simple example is that the frame pointer register can be used if + /// frame-pointer-elimination is performed. + /// + /// By default, these methods return all registers in the class. + /// + virtual iterator allocation_order_begin(MachineFunction &MF) const { + return begin(); + } + virtual iterator allocation_order_end(MachineFunction &MF) const { + return end(); + } + + + + /// getSize - Return the size of the register in bytes, which is also the size + /// of a stack slot allocated to hold a spilled copy of this register. + unsigned getSize() const { return RegSize; } + + /// getAlignment - Return the minimum required alignment for a register of + /// this class. + unsigned getAlignment() const { return Alignment; } }; @@ -87,9 +119,11 @@ regclass_iterator RegClassBegin, RegClassEnd; // List of regclasses const TargetRegisterClass **PhysRegClasses; // Reg class for each register + int CallFrameSetupOpcode, CallFrameDestroyOpcode; protected: MRegisterInfo(const MRegisterDesc *D, unsigned NR, - regclass_iterator RegClassBegin, regclass_iterator RegClassEnd); + regclass_iterator RegClassBegin, regclass_iterator RegClassEnd, + int CallFrameSetupOpcode = -1, int CallFrameDestroyOpcode = -1); virtual ~MRegisterInfo(); public: @@ -139,11 +173,7 @@ return get(RegNo).AliasSet; } - virtual unsigned getFramePointer() const = 0; - virtual unsigned getStackPointer() const = 0; - virtual const unsigned* getCalleeSaveRegs() const = 0; - virtual const unsigned* getCallerSaveRegs() const = 0; //===--------------------------------------------------------------------===// @@ -161,34 +191,74 @@ //===--------------------------------------------------------------------===// - // Interfaces used primarily by the register allocator to move data around - // between registers, immediates and memory. + // Interfaces used by the register allocator and stack frame manipulation + // passes to move data around between registers, immediates and memory. // - virtual void emitPrologue(MachineFunction &MF, unsigned Bytes) const = 0; - virtual void emitEpilogue(MachineBasicBlock &MBB, unsigned Bytes) const = 0; + virtual void storeRegToStackSlot(MachineBasicBlock &MBB, + MachineBasicBlock::iterator &MBBI, + unsigned SrcReg, int FrameIndex, + const TargetRegisterClass *RC) const = 0; + + virtual void loadRegFromStackSlot(MachineBasicBlock &MBB, + MachineBasicBlock::iterator &MBBI, + unsigned DestReg, int FrameIndex, + const TargetRegisterClass *RC) const = 0; + + virtual void copyRegToReg(MachineBasicBlock &MBB, + MachineBasicBlock::iterator &MBBI, + unsigned DestReg, unsigned SrcReg, + const TargetRegisterClass *RC) const = 0; + + + /// getCallFrameSetup/DestroyOpcode - These methods return the opcode of the + /// frame setup/destroy instructions if they exist (-1 otherwise). Some + /// targets use pseudo instructions in order to abstract away the difference + /// between operating with a frame pointer and operating without, through the + /// use of these two instructions. + /// + int getCallFrameSetupOpcode() const { return CallFrameSetupOpcode; } + int getCallFrameDestroyOpcode() const { return CallFrameDestroyOpcode; } + + + /// eliminateCallFramePseudoInstr - This method is called during prolog/epilog + /// code insertion to eliminate call frame setup and destroy pseudo + /// instructions (but only if the Target is using them). It is responsible + /// for eliminating these instructions, replacing them with concrete + /// instructions. This method need only be implemented if using call frame + /// setup/destroy pseudo instructions. + /// + virtual void eliminateCallFramePseudoInstr(MachineFunction &MF, + MachineBasicBlock &MBB, + MachineBasicBlock::iterator &I) const { + assert(getCallFrameSetupOpcode()== -1 && getCallFrameDestroyOpcode()== -1 && + "eliminateCallFramePseudoInstr must be implemented if using" + " call frame setup/destroy pseudo instructions!"); + assert(0 && "Call Frame Pseudo Instructions do not exist on this target!"); + } + + /// processFunctionBeforeFrameFinalized - This method is called immediately + /// before the specified functions frame layout (MF.getFrameInfo()) is + /// finalized. Once the frame is finalized, MO_FrameIndex operands are + /// replaced with direct constants. This method is optional. + /// + virtual void processFunctionBeforeFrameFinalized(MachineFunction &MF) const {} + + /// eliminateFrameIndex - This method must be overriden to eliminate abstract + /// frame indices from instructions which may use them. The instruction + /// referenced by the iterator contains an MO_FrameIndex operand which must be + /// eliminated by this method. This method may modify or replace the + /// specified instruction, as long as it keeps the iterator pointing the the + /// finished product. + /// + virtual void eliminateFrameIndex(MachineFunction &MF, + MachineBasicBlock::iterator &II) const = 0; - virtual void storeReg2RegOffset(MachineBasicBlock &MBB, - MachineBasicBlock::iterator &MBBI, - unsigned SrcReg, unsigned DestReg, - unsigned ImmOffset, - const TargetRegisterClass *RC) const = 0; - - virtual void loadRegOffset2Reg(MachineBasicBlock &MBB, - MachineBasicBlock::iterator &MBBI, - unsigned DestReg, unsigned SrcReg, - unsigned ImmOffset, - const TargetRegisterClass *RC) const = 0; - - virtual void moveReg2Reg(MachineBasicBlock &MBB, - MachineBasicBlock::iterator &MBBI, - unsigned DestReg, unsigned SrcReg, - const TargetRegisterClass *RC) const = 0; - - virtual void moveImm2Reg(MachineBasicBlock &MBB, - MachineBasicBlock::iterator &MBBI, - unsigned DestReg, unsigned Imm, - const TargetRegisterClass *RC) const = 0; + /// emitProlog/emitEpilog - These methods insert prolog and epilog code into + /// the function. + virtual void emitPrologue(MachineFunction &MF) const = 0; + virtual void emitEpilogue(MachineFunction &MF, + MachineBasicBlock &MBB) const = 0; }; #endif From lattner at cs.uiuc.edu Sat Dec 28 14:13:01 2002 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Sat Dec 28 14:13:01 2002 Subject: [llvm-commits] CVS: llvm/include/llvm/Target/MachineFrameInfo.h Message-ID: <200212282012.OAA08834@apoc.cs.uiuc.edu> Changes in directory llvm/include/llvm/Target: MachineFrameInfo.h updated: 1.6 -> 1.7 --- Log message: Expose some very simple information about the frame, rather than in-depth target specific information. Rename MachineFrameInfo to TargetFrameInfo --- Diffs of the changes: Index: llvm/include/llvm/Target/MachineFrameInfo.h diff -u llvm/include/llvm/Target/MachineFrameInfo.h:1.6 llvm/include/llvm/Target/MachineFrameInfo.h:1.7 --- llvm/include/llvm/Target/MachineFrameInfo.h:1.6 Sun Oct 27 18:26:17 2002 +++ llvm/include/llvm/Target/MachineFrameInfo.h Sat Dec 28 14:12:10 2002 @@ -1,76 +1,95 @@ -//===-- llvm/CodeGen/MachineFrameInfo.h -------------------------*- C++ -*-===// +//===-- llvm/Target/TargetFrameInfo.h ---------------------------*- C++ -*-===// // -// Interface to layout of stack frame on target machine. +// Interface to describe the layout of a stack frame on the target machine. // //===----------------------------------------------------------------------===// -#ifndef LLVM_CODEGEN_FRAMEINFO_H -#define LLVM_CODEGEN_FRAMEINFO_H - -#include "Support/NonCopyable.h" -#include +#ifndef LLVM_TARGET_TARGETFRAMEINFO_H +#define LLVM_TARGET_TARGETFRAMEINFO_H class MachineFunction; -class TargetMachine; -struct MachineFrameInfo : public NonCopyableV { - const TargetMachine ⌖ - +struct TargetFrameInfo { + enum StackDirection { + StackGrowsUp, // Adding to the stack increases the stack address + StackGrowsDown // Adding to the stack decreases the stack address + }; +private: + StackDirection StackDir; + unsigned StackAlignment; + int LocalAreaOffset; public: - MachineFrameInfo(const TargetMachine& tgt) : target(tgt) {} - - // These methods provide constant parameters of the frame layout. - // - virtual int getStackFrameSizeAlignment () const = 0; - virtual int getMinStackFrameSize () const = 0; - virtual int getNumFixedOutgoingArgs () const = 0; - virtual int getSizeOfEachArgOnStack () const = 0; - virtual bool argsOnStackHaveFixedSize () const = 0; + TargetFrameInfo(StackDirection D, unsigned StackAl, int LAO) + : StackDir(D), StackAlignment(StackAl), LocalAreaOffset(LAO) {} + + // These methods return information that describes the abstract stack layout + // of the target machine. + + /// getStackGrowthDirection - Return the direction the stack grows + /// + StackDirection getStackGrowthDirection() const { return StackDir; } + + /// getStackAlignment - This method returns the number of bytes that the stack + /// pointer must be aligned to. Typically, this is the largest alignment for + /// any data object in the target. + /// + unsigned getStackAlignment() const { return StackAlignment; } + + /// getOffsetOfLocalArea - This method returns the offset of the local area + /// from the stack pointer on entrance to a function. + /// + int getOffsetOfLocalArea() const { return LocalAreaOffset; } + + //===--------------------------------------------------------------------===// + // These methods provide details of the stack frame used by Sparc, thus they + // are Sparc specific. + //===--------------------------------------------------------------------===// + + virtual int getStackFrameSizeAlignment () const { abort(); } + virtual int getMinStackFrameSize () const { abort(); } + virtual int getNumFixedOutgoingArgs () const { abort(); } + virtual int getSizeOfEachArgOnStack () const { abort(); } + virtual bool argsOnStackHaveFixedSize () const { abort(); } // This method adjusts a stack offset to meet alignment rules of target. - // - virtual int adjustAlignment (int unalignedOffset, - bool growUp, - unsigned int align) const { - return unalignedOffset + (growUp? +1:-1)*(unalignedOffset % align); - } - - // These methods compute offsets using the frame contents for a - // particular method. The frame contents are obtained from the - // MachineCodeInfoForMethod object for the given method. - // The first few methods have default machine-independent implementations. - // The rest must be implemented by the machine-specific subclass. + virtual int adjustAlignment(int unalignedOffset, bool growUp, + unsigned align) const { abort(); } + + // These methods compute offsets using the frame contents for a particular + // function. The frame contents are obtained from the MachineFunction object + // for the given function. The rest must be implemented by the + // machine-specific subclass. // virtual int getIncomingArgOffset (MachineFunction& mcInfo, - unsigned argNum) const; + unsigned argNum)const{abort();} virtual int getOutgoingArgOffset (MachineFunction& mcInfo, - unsigned argNum) const; + unsigned argNum)const{abort();} virtual int getFirstIncomingArgOffset (MachineFunction& mcInfo, - bool& growUp) const=0; + bool& growUp) const { abort();} virtual int getFirstOutgoingArgOffset (MachineFunction& mcInfo, - bool& growUp) const=0; + bool& growUp) const {abort();} virtual int getFirstOptionalOutgoingArgOffset (MachineFunction&, - bool& growUp) const=0; + bool& growUp) const {abort();} virtual int getFirstAutomaticVarOffset (MachineFunction& mcInfo, - bool& growUp) const=0; + bool& growUp) const {abort();} virtual int getRegSpillAreaOffset (MachineFunction& mcInfo, - bool& growUp) const=0; + bool& growUp) const {abort();} virtual int getTmpAreaOffset (MachineFunction& mcInfo, - bool& growUp) const=0; + bool& growUp) const {abort();} virtual int getDynamicAreaOffset (MachineFunction& mcInfo, - bool& growUp) const=0; + bool& growUp) const {abort();} // // These methods specify the base register used for each stack area // (generally FP or SP) // - virtual int getIncomingArgBaseRegNum() const=0; - virtual int getOutgoingArgBaseRegNum() const=0; - virtual int getOptionalOutgoingArgBaseRegNum() const=0; - virtual int getAutomaticVarBaseRegNum() const=0; - virtual int getRegSpillAreaBaseRegNum() const=0; - virtual int getDynamicAreaBaseRegNum() const=0; + virtual int getIncomingArgBaseRegNum() const { abort(); } + virtual int getOutgoingArgBaseRegNum() const { abort(); } + virtual int getOptionalOutgoingArgBaseRegNum() const { abort(); } + virtual int getAutomaticVarBaseRegNum() const { abort(); } + virtual int getRegSpillAreaBaseRegNum() const { abort(); } + virtual int getDynamicAreaBaseRegNum() const { abort(); } }; #endif From lattner at cs.uiuc.edu Sat Dec 28 14:14:00 2002 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Sat Dec 28 14:14:00 2002 Subject: [llvm-commits] CVS: llvm/include/llvm/Target/MachineInstrInfo.h Message-ID: <200212282013.OAA08851@apoc.cs.uiuc.edu> Changes in directory llvm/include/llvm/Target: MachineInstrInfo.h updated: 1.39 -> 1.40 --- Log message: Sparc specific methods default to abort rather than being pure virtual --- Diffs of the changes: Index: llvm/include/llvm/Target/MachineInstrInfo.h diff -u llvm/include/llvm/Target/MachineInstrInfo.h:1.39 llvm/include/llvm/Target/MachineInstrInfo.h:1.40 --- llvm/include/llvm/Target/MachineInstrInfo.h:1.39 Tue Dec 24 23:01:46 2002 +++ llvm/include/llvm/Target/MachineInstrInfo.h Sat Dec 28 14:12:54 2002 @@ -267,12 +267,15 @@ //------------------------------------------------------------------------- // Code generation support for creating individual machine instructions + // + // WARNING: These methods are Sparc specific + // //------------------------------------------------------------------------- // Get certain common op codes for the current target. this and all the // Create* methods below should be moved to a machine code generation class // - virtual MachineOpCode getNOPOpCode() const = 0; + virtual MachineOpCode getNOPOpCode() const { abort(); } // Create an instruction sequence to put the constant `val' into // the virtual register `dest'. `val' may be a Constant or a @@ -287,7 +290,9 @@ Value* val, Instruction* dest, std::vector& mvec, - MachineCodeForInstruction& mcfi) const=0; + MachineCodeForInstruction& mcfi) const { + abort(); + } // Create an instruction sequence to copy an integer value `val' // to a floating point value `dest' by copying to memory and back. @@ -296,12 +301,14 @@ // Any temp. registers (TmpInstruction) created are recorded in mcfi. // Any stack space required is allocated via mcff. // - virtual void CreateCodeToCopyIntToFloat(const TargetMachine& target, - Function* F, - Value* val, - Instruction* dest, - std::vector& mvec, - MachineCodeForInstruction& mcfi)const=0; + virtual void CreateCodeToCopyIntToFloat(const TargetMachine& target, + Function* F, + Value* val, + Instruction* dest, + std::vector& mvec, + MachineCodeForInstruction& MI) const { + abort(); + } // Similarly, create an instruction sequence to copy an FP value // `val' to an integer value `dest' by copying to memory and back. @@ -309,12 +316,14 @@ // Any temp. registers (TmpInstruction) created are recorded in mcfi. // Any stack space required is allocated via mcff. // - virtual void CreateCodeToCopyFloatToInt(const TargetMachine& target, - Function* F, - Value* val, - Instruction* dest, - std::vector& mvec, - MachineCodeForInstruction& mcfi)const=0; + virtual void CreateCodeToCopyFloatToInt(const TargetMachine& target, + Function* F, + Value* val, + Instruction* dest, + std::vector& mvec, + MachineCodeForInstruction& MI) const { + abort(); + } // Create instruction(s) to copy src to dest, for arbitrary types // The generated instructions are returned in `mvec'. @@ -322,11 +331,13 @@ // Any stack space required is allocated via mcff. // virtual void CreateCopyInstructionsByType(const TargetMachine& target, - Function* F, - Value* src, - Instruction* dest, - std::vector& mvec, - MachineCodeForInstruction& mcfi)const=0; + Function* F, + Value* src, + Instruction* dest, + std::vector& mvec, + MachineCodeForInstruction& MI) const { + abort(); + } // Create instruction sequence to produce a sign-extended register value // from an arbitrary sized value (sized in bits, not bytes). @@ -340,7 +351,9 @@ Value* destVal, unsigned numLowBits, std::vector& mvec, - MachineCodeForInstruction& mcfi) const=0; + MachineCodeForInstruction& MI) const { + abort(); + } // Create instruction sequence to produce a zero-extended register value // from an arbitrary sized value (sized in bits, not bytes). @@ -354,7 +367,9 @@ Value* destVal, unsigned srcSizeInBits, std::vector& mvec, - MachineCodeForInstruction& mcfi) const=0; + MachineCodeForInstruction& mcfi) const { + abort(); + } }; #endif From lattner at cs.uiuc.edu Sat Dec 28 14:14:03 2002 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Sat Dec 28 14:14:03 2002 Subject: [llvm-commits] CVS: llvm/include/llvm/Target/TargetMachine.h Message-ID: <200212282013.OAA08919@apoc.cs.uiuc.edu> Changes in directory llvm/include/llvm/Target: TargetMachine.h updated: 1.25 -> 1.26 --- Log message: * doxygenize comment * rename MachineFrameInfo to TargetFrameInfo --- Diffs of the changes: Index: llvm/include/llvm/Target/TargetMachine.h diff -u llvm/include/llvm/Target/TargetMachine.h:1.25 llvm/include/llvm/Target/TargetMachine.h:1.26 --- llvm/include/llvm/Target/TargetMachine.h:1.25 Mon Dec 23 18:02:17 2002 +++ llvm/include/llvm/Target/TargetMachine.h Sat Dec 28 14:13:29 2002 @@ -14,7 +14,7 @@ class MachineInstrDescriptor; class MachineSchedInfo; class MachineRegInfo; -class MachineFrameInfo; +class TargetFrameInfo; class MachineCacheInfo; class MachineOptInfo; class MachineCodeEmitter; @@ -22,19 +22,14 @@ class PassManager; class Pass; -//--------------------------------------------------------------------------- -// class TargetMachine -// -// Purpose: -// Primary interface to the complete machine description for the -// target machine. All target-specific information should be -// accessible through this interface. -// -//--------------------------------------------------------------------------- - +//===----------------------------------------------------------------------===// +/// +/// TargetMachine - Primary interface to the complete machine description for +/// the target machine. All target-specific information should be accessible +/// through this interface. +/// class TargetMachine : public NonCopyableV { const std::string Name; -public: const TargetData DataLayout; // Calculates type size & alignment protected: @@ -53,7 +48,6 @@ const std::string &getName() const { return Name; } - // // Interfaces to the major aspects of target machine information: // -- Instruction opcode and operand information // -- Pipelines and scheduling information @@ -65,14 +59,14 @@ virtual const MachineInstrInfo& getInstrInfo() const = 0; virtual const MachineSchedInfo& getSchedInfo() const = 0; virtual const MachineRegInfo& getRegInfo() const = 0; - virtual const MachineFrameInfo& getFrameInfo() const = 0; + virtual const TargetFrameInfo& getFrameInfo() const = 0; virtual const MachineCacheInfo& getCacheInfo() const = 0; virtual const MachineOptInfo& getOptInfo() const = 0; const TargetData &getTargetData() const { return DataLayout; } /// getRegisterInfo - If register information is available, return it. If - /// not, return null. This is kept separate from RegInfo until RegInfo gets - /// straightened out. + /// not, return null. This is kept separate from RegInfo until RegInfo has + /// details of graph coloring register allocation removed from it. /// virtual const MRegisterInfo* getRegisterInfo() const { return 0; } From lattner at cs.uiuc.edu Sat Dec 28 14:17:00 2002 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Sat Dec 28 14:17:00 2002 Subject: [llvm-commits] CVS: llvm/lib/Target/Sparc/EmitAssembly.cpp Message-ID: <200212282016.OAA09951@apoc.cs.uiuc.edu> Changes in directory llvm/lib/Target/Sparc: EmitAssembly.cpp updated: 1.72 -> 1.73 --- Log message: * Don't access TargetData directly * Changes because frame info is not in MachineFunction directly anymore --- Diffs of the changes: Index: llvm/lib/Target/Sparc/EmitAssembly.cpp diff -u llvm/lib/Target/Sparc/EmitAssembly.cpp:1.72 llvm/lib/Target/Sparc/EmitAssembly.cpp:1.73 --- llvm/lib/Target/Sparc/EmitAssembly.cpp:1.72 Sun Nov 17 16:57:23 2002 +++ llvm/lib/Target/Sparc/EmitAssembly.cpp Sat Dec 28 14:15:01 2002 @@ -14,6 +14,7 @@ #include "SparcInternals.h" #include "llvm/CodeGen/MachineInstr.h" #include "llvm/CodeGen/MachineFunction.h" +#include "llvm/CodeGen/MachineFunctionInfo.h" #include "llvm/Constants.h" #include "llvm/DerivedTypes.h" #include "llvm/Module.h" @@ -193,17 +194,17 @@ { // generate a symbolic expression for the byte address const Value* ptrVal = CE->getOperand(0); std::vector idxVec(CE->op_begin()+1, CE->op_end()); + const TargetData &TD = target.getTargetData(); S += "(" + valToExprString(ptrVal, target) + ") + (" - + utostr(target.DataLayout.getIndexedOffset(ptrVal->getType(),idxVec)) - + ")"; + + utostr(TD.getIndexedOffset(ptrVal->getType(),idxVec)) + ")"; break; } case Instruction::Cast: // Support only non-converting casts for now, i.e., a no-op. // This assertion is not a complete check. - assert(target.DataLayout.getTypeSize(CE->getType()) == - target.DataLayout.getTypeSize(CE->getOperand(0)->getType())); + assert(target.getTargetData().getTypeSize(CE->getType()) == + target.getTargetData().getTypeSize(CE->getOperand(0)->getType())); S += "(" + valToExprString(CE->getOperand(0), target) + ")"; break; @@ -489,7 +490,7 @@ // Output code for all of the basic blocks in the function... MachineFunction &MF = MachineFunction::get(&F); - for (MachineFunction::const_iterator I = MF.begin(), E = MF.end(); I != E; ++I) + for (MachineFunction::const_iterator I = MF.begin(), E = MF.end(); I != E;++I) emitBasicBlock(*I); // Output a .size directive so the debugger knows the extents of the function @@ -803,7 +804,7 @@ else if (const ConstantStruct *CVS = dyn_cast(CV)) { // Print the fields in successive locations. Pad to align if needed! const StructLayout *cvsLayout = - Target.DataLayout.getStructLayout(CVS->getType()); + Target.getTargetData().getStructLayout(CVS->getType()); const std::vector& constValues = CVS->getValues(); unsigned sizeSoFar = 0; for (unsigned i=0, N = constValues.size(); i < N; i++) @@ -811,7 +812,8 @@ const Constant* field = cast(constValues[i].get()); // Check if padding is needed and insert one or more 0s. - unsigned fieldSize = Target.DataLayout.getTypeSize(field->getType()); + unsigned fieldSize = + Target.getTargetData().getTypeSize(field->getType()); int padSize = ((i == N-1? cvsLayout->StructSize : cvsLayout->MemberOffsets[i+1]) - cvsLayout->MemberOffsets[i]) - fieldSize; @@ -864,7 +866,7 @@ for (Module::const_iterator I = M.begin(), E = M.end(); I != E; ++I) if (!I->isExternal()) { const hash_set &pool = - MachineFunction::get(I).getConstantPoolValues(); + MachineFunction::get(I).getInfo()->getConstantPoolValues(); MC.insert(pool.begin(), pool.end()); } } From lattner at cs.uiuc.edu Sat Dec 28 14:18:01 2002 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Sat Dec 28 14:18:01 2002 Subject: [llvm-commits] CVS: llvm/lib/Target/Sparc/PrologEpilogCodeInserter.cpp Message-ID: <200212282017.OAA10517@apoc.cs.uiuc.edu> Changes in directory llvm/lib/Target/Sparc: PrologEpilogCodeInserter.cpp updated: 1.19 -> 1.20 --- Log message: * Changes to be a MachineFunctionPass * Frame information is now stuck in MachineFunctionInfo instead of directly in MachineFunction. * Don't require a TM as an argument to the ctor --- Diffs of the changes: Index: llvm/lib/Target/Sparc/PrologEpilogCodeInserter.cpp diff -u llvm/lib/Target/Sparc/PrologEpilogCodeInserter.cpp:1.19 llvm/lib/Target/Sparc/PrologEpilogCodeInserter.cpp:1.20 --- llvm/lib/Target/Sparc/PrologEpilogCodeInserter.cpp:1.19 Mon Oct 28 15:43:57 2002 +++ llvm/lib/Target/Sparc/PrologEpilogCodeInserter.cpp Sat Dec 28 14:16:08 2002 @@ -11,7 +11,8 @@ #include "SparcInternals.h" #include "SparcRegClassInfo.h" -#include "llvm/CodeGen/MachineFunction.h" +#include "llvm/CodeGen/MachineFunctionPass.h" +#include "llvm/CodeGen/MachineFunctionInfo.h" #include "llvm/CodeGen/MachineCodeForInstruction.h" #include "llvm/CodeGen/MachineInstrBuilder.h" #include "llvm/CodeGen/InstrSelectionSupport.h" @@ -19,48 +20,38 @@ #include "llvm/Function.h" namespace { - class InsertPrologEpilogCode : public FunctionPass { - TargetMachine &Target; - public: - InsertPrologEpilogCode(TargetMachine &T) : Target(T) {} - + struct InsertPrologEpilogCode : public MachineFunctionPass { const char *getPassName() const { return "Sparc Prolog/Epilog Inserter"; } - bool runOnFunction(Function &F) { - MachineFunction &mcodeInfo = MachineFunction::get(&F); - if (!mcodeInfo.isCompiledAsLeafMethod()) { + bool runOnMachineFunction(MachineFunction &F) { + if (!F.getInfo()->isCompiledAsLeafMethod()) { InsertPrologCode(F); InsertEpilogCode(F); } return false; } - void InsertPrologCode(Function &F); - void InsertEpilogCode(Function &F); + void InsertPrologCode(MachineFunction &F); + void InsertEpilogCode(MachineFunction &F); }; } // End anonymous namespace //------------------------------------------------------------------------ -// External Function: GetInstructionsForProlog -// External Function: GetInstructionsForEpilog -// -// Purpose: // Create prolog and epilog code for procedure entry and exit //------------------------------------------------------------------------ -void InsertPrologEpilogCode::InsertPrologCode(Function &F) +void InsertPrologEpilogCode::InsertPrologCode(MachineFunction &MF) { std::vector mvec; - MachineInstr* M; - const MachineFrameInfo& frameInfo = Target.getFrameInfo(); + const TargetMachine &TM = MF.getTarget(); + const TargetFrameInfo& frameInfo = TM.getFrameInfo(); // The second operand is the stack size. If it does not fit in the // immediate field, we have to use a free register to hold the size. // See the comments below for the choice of this register. // - MachineFunction& mcInfo = MachineFunction::get(&F); - unsigned staticStackSize = mcInfo.getStaticStackSize(); + unsigned staticStackSize = MF.getInfo()->getStaticStackSize(); if (staticStackSize < (unsigned) frameInfo.getMinStackFrameSize()) staticStackSize = (unsigned) frameInfo.getMinStackFrameSize(); @@ -70,50 +61,50 @@ staticStackSize += frameInfo.getStackFrameSizeAlignment() - padsz; int32_t C = - (int) staticStackSize; - int SP = Target.getRegInfo().getStackPointer(); - if (Target.getInstrInfo().constantFitsInImmedField(SAVE, staticStackSize)) { - M = BuildMI(SAVE, 3).addMReg(SP).addSImm(C).addMReg(SP); - mvec.push_back(M); + int SP = TM.getRegInfo().getStackPointer(); + if (TM.getInstrInfo().constantFitsInImmedField(SAVE, staticStackSize)) { + mvec.push_back(BuildMI(SAVE, 3).addMReg(SP).addSImm(C).addMReg(SP)); } else { - // We have to put the stack size value into a register before SAVE. - // Use register %g1 since it is volatile across calls. Note that the - // local (%l) and in (%i) registers cannot be used before the SAVE! - // Do this by creating a code sequence equivalent to: - // SETSW -(stackSize), %g1 - int uregNum = Target.getRegInfo().getUnifiedRegNum( - Target.getRegInfo().getRegClassIDOfType(Type::IntTy), - SparcIntRegClass::g1); - - M = BuildMI(SETHI, 2).addSImm(C).addMReg(uregNum); - M->setOperandHi32(0); - mvec.push_back(M); - - M = BuildMI(OR, 3).addMReg(uregNum).addSImm(C).addMReg(uregNum); - M->setOperandLo32(1); - mvec.push_back(M); - - M = BuildMI(SRA, 3).addMReg(uregNum).addZImm(0).addMReg(uregNum); - mvec.push_back(M); - - // Now generate the SAVE using the value in register %g1 - M = BuildMI(SAVE, 3).addMReg(SP).addMReg(uregNum).addMReg(SP); - mvec.push_back(M); - } + // We have to put the stack size value into a register before SAVE. + // Use register %g1 since it is volatile across calls. Note that the + // local (%l) and in (%i) registers cannot be used before the SAVE! + // Do this by creating a code sequence equivalent to: + // SETSW -(stackSize), %g1 + int uregNum = TM.getRegInfo().getUnifiedRegNum( + TM.getRegInfo().getRegClassIDOfType(Type::IntTy), + SparcIntRegClass::g1); - MachineBasicBlock& bbMvec = mcInfo.front(); - bbMvec.insert(bbMvec.begin(), mvec.begin(), mvec.end()); + MachineInstr* M = BuildMI(SETHI, 2).addSImm(C).addMReg(uregNum); + M->setOperandHi32(0); + mvec.push_back(M); + + M = BuildMI(OR, 3).addMReg(uregNum).addSImm(C).addMReg(uregNum); + M->setOperandLo32(1); + mvec.push_back(M); + + M = BuildMI(SRA, 3).addMReg(uregNum).addZImm(0).addMReg(uregNum); + mvec.push_back(M); + + // Now generate the SAVE using the value in register %g1 + M = BuildMI(SAVE, 3).addMReg(SP).addMReg(uregNum).addMReg(SP); + mvec.push_back(M); + } + + MF.front().insert(MF.front().begin(), mvec.begin(), mvec.end()); } -void InsertPrologEpilogCode::InsertEpilogCode(Function &F) +void InsertPrologEpilogCode::InsertEpilogCode(MachineFunction &MF) { - MachineFunction &MF = MachineFunction::get(&F); + const TargetMachine &TM = MF.getTarget(); + const MachineInstrInfo &MII = TM.getInstrInfo(); + for (MachineFunction::iterator I = MF.begin(), E = MF.end(); I != E; ++I) { MachineBasicBlock &MBB = *I; BasicBlock &BB = *I->getBasicBlock(); Instruction *TermInst = (Instruction*)BB.getTerminator(); if (TermInst->getOpcode() == Instruction::Ret) { - int ZR = Target.getRegInfo().getZeroRegNum(); + int ZR = TM.getRegInfo().getZeroRegNum(); MachineInstr *Restore = BuildMI(RESTORE, 3).addMReg(ZR).addSImm(0).addMReg(ZR); @@ -121,7 +112,6 @@ MachineCodeForInstruction::get(TermInst); // Remove the NOPs in the delay slots of the return instruction - const MachineInstrInfo &mii = Target.getInstrInfo(); unsigned numNOPs = 0; while (termMvec.back()->getOpCode() == NOP) { @@ -134,7 +124,7 @@ // Check that we found the right number of NOPs and have the right // number of instructions to replace them. - unsigned ndelays = mii.getNumDelaySlots(termMvec.back()->getOpCode()); + unsigned ndelays = MII.getNumDelaySlots(termMvec.back()->getOpCode()); assert(numNOPs == ndelays && "Missing NOPs in delay slots?"); assert(ndelays == 1 && "Cannot use epilog code for delay slots?"); @@ -145,5 +135,5 @@ } Pass* UltraSparc::getPrologEpilogInsertionPass() { - return new InsertPrologEpilogCode(*this); + return new InsertPrologEpilogCode(); } From lattner at cs.uiuc.edu Sat Dec 28 14:19:01 2002 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Sat Dec 28 14:19:01 2002 Subject: [llvm-commits] CVS: llvm/lib/Target/Sparc/Sparc.cpp Message-ID: <200212282018.OAA10714@apoc.cs.uiuc.edu> Changes in directory llvm/lib/Target/Sparc: Sparc.cpp updated: 1.58 -> 1.59 --- Log message: * Frame & const pool info is no longer directly in MachineFunction --- Diffs of the changes: Index: llvm/lib/Target/Sparc/Sparc.cpp diff -u llvm/lib/Target/Sparc/Sparc.cpp:1.58 llvm/lib/Target/Sparc/Sparc.cpp:1.59 --- llvm/lib/Target/Sparc/Sparc.cpp:1.58 Mon Dec 23 18:02:38 2002 +++ llvm/lib/Target/Sparc/Sparc.cpp Sat Dec 28 14:17:43 2002 @@ -11,6 +11,7 @@ #include "llvm/PassManager.h" #include "llvm/Transforms/Scalar.h" #include "llvm/CodeGen/MachineFunction.h" +#include "llvm/CodeGen/MachineFunctionInfo.h" #include "llvm/CodeGen/PreSelection.h" #include "llvm/CodeGen/StackSlots.h" #include "llvm/CodeGen/PeepholeOpts.h" @@ -59,7 +60,6 @@ //--------------------------------------------------------------------------- // class UltraSparcFrameInfo // -// Purpose: // Interface to stack frame layout info for the UltraSPARC. // Starting offsets for each area of the stack frame are aligned at // a multiple of getStackFrameSizeAlignment(). @@ -77,10 +77,11 @@ UltraSparcFrameInfo::getRegSpillAreaOffset(MachineFunction& mcInfo, bool& pos) const { - mcInfo.freezeAutomaticVarsArea(); // ensure no more auto vars are added + // ensure no more auto vars are added + mcInfo.getInfo()->freezeAutomaticVarsArea(); pos = false; // static stack area grows downwards - unsigned int autoVarsSize = mcInfo.getAutomaticVarsSize(); + unsigned autoVarsSize = mcInfo.getInfo()->getAutomaticVarsSize(); return StaticAreaOffsetFromFP - autoVarsSize; } @@ -88,12 +89,13 @@ UltraSparcFrameInfo::getTmpAreaOffset(MachineFunction& mcInfo, bool& pos) const { - mcInfo.freezeAutomaticVarsArea(); // ensure no more auto vars are added - mcInfo.freezeSpillsArea(); // ensure no more spill slots are added + MachineFunctionInfo *MFI = mcInfo.getInfo(); + MFI->freezeAutomaticVarsArea(); // ensure no more auto vars are added + MFI->freezeSpillsArea(); // ensure no more spill slots are added pos = false; // static stack area grows downwards - unsigned int autoVarsSize = mcInfo.getAutomaticVarsSize(); - unsigned int spillAreaSize = mcInfo.getRegSpillsSize(); + unsigned autoVarsSize = MFI->getAutomaticVarsSize(); + unsigned spillAreaSize = MFI->getRegSpillsSize(); int offset = autoVarsSize + spillAreaSize; return StaticAreaOffsetFromFP - offset; } @@ -107,7 +109,7 @@ // during calls and traps, so they are shifted downwards on each // dynamic-size alloca. pos = false; - unsigned int optArgsSize = mcInfo.getMaxOptionalArgsSize(); + unsigned optArgsSize = mcInfo.getInfo()->getMaxOptionalArgsSize(); if (int extra = optArgsSize % getStackFrameSizeAlignment()) optArgsSize += (getStackFrameSizeAlignment() - extra); int offset = optArgsSize + FirstOptionalOutgoingArgOffsetFromSP; From lattner at cs.uiuc.edu Sat Dec 28 14:21:00 2002 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Sat Dec 28 14:21:00 2002 Subject: [llvm-commits] CVS: llvm/lib/Target/Sparc/SparcInstrSelection.cpp Message-ID: <200212282020.OAA10967@apoc.cs.uiuc.edu> Changes in directory llvm/lib/Target/Sparc: SparcInstrSelection.cpp updated: 1.80 -> 1.81 --- Log message: * TargetData is no longer directly accessable from TM * s/unsigned int/unsigned/ --- Diffs of the changes: Index: llvm/lib/Target/Sparc/SparcInstrSelection.cpp diff -u llvm/lib/Target/Sparc/SparcInstrSelection.cpp:1.80 llvm/lib/Target/Sparc/SparcInstrSelection.cpp:1.81 --- llvm/lib/Target/Sparc/SparcInstrSelection.cpp:1.80 Tue Oct 29 13:37:31 2002 +++ llvm/lib/Target/Sparc/SparcInstrSelection.cpp Sat Dec 28 14:19:44 2002 @@ -13,6 +13,7 @@ #include "llvm/CodeGen/InstrForest.h" #include "llvm/CodeGen/InstrSelection.h" #include "llvm/CodeGen/MachineFunction.h" +#include "llvm/CodeGen/MachineFunctionInfo.h" #include "llvm/CodeGen/MachineCodeForInstruction.h" #include "llvm/DerivedTypes.h" #include "llvm/iTerminators.h" @@ -315,7 +316,7 @@ // // Since fdtoi converts to signed integers, any FP value V between MAXINT+1 // and MAXUNSIGNED (i.e., 2^31 <= V <= 2^32-1) would be converted incorrectly -// *only* when converting to an unsigned int. (Unsigned byte, short or long +// *only* when converting to an unsigned. (Unsigned byte, short or long // don't have this problem.) // For unsigned int, we therefore have to generate the code sequence: // @@ -324,7 +325,7 @@ // result = result + (unsigned) MAXINT; // } // else -// result = (unsigned int) V; +// result = (unsigned) V; // static void CreateCodeToConvertFloatToInt(const TargetMachine& target, @@ -338,7 +339,7 @@ // depends on the type of FP register to use: single-prec for a 32-bit // int or smaller; double-prec for a 64-bit int. // - size_t destSize = target.DataLayout.getTypeSize(destI->getType()); + size_t destSize = target.getTargetData().getTypeSize(destI->getType()); const Type* destTypeToUse = (destSize > 4)? Type::DoubleTy : Type::FloatTy; TmpInstruction* destForCast = new TmpInstruction(destTypeToUse, opVal); mcfi.addTemp(destForCast); @@ -522,7 +523,7 @@ MachineOpCode shiftOpCode, Value* argVal1, Value* optArgVal2, /* Use optArgVal2 if not NULL */ - unsigned int optShiftNum, /* else use optShiftNum */ + unsigned optShiftNum, /* else use optShiftNum */ Instruction* destVal, vector& mvec, MachineCodeForInstruction& mcfi) @@ -536,9 +537,9 @@ // of dest, so we need to put the result of the SLL into a temporary. // Value* shiftDest = destVal; - unsigned opSize = target.DataLayout.getTypeSize(argVal1->getType()); + unsigned opSize = target.getTargetData().getTypeSize(argVal1->getType()); if ((shiftOpCode == SLL || shiftOpCode == SLLX) - && opSize < target.DataLayout.getIntegerRegize()) + && opSize < target.getTargetData().getIntegerRegize()) { // put SLL result into a temporary shiftDest = new TmpInstruction(argVal1, optArgVal2, "sllTmp"); mcfi.addTemp(shiftDest); @@ -563,15 +564,15 @@ // create a cheaper instruction. // This returns the approximate cost of the instructions generated, // which is used to pick the cheapest when both operands are constant. -static inline unsigned int +static inline unsigned CreateMulConstInstruction(const TargetMachine &target, Function* F, Value* lval, Value* rval, Instruction* destVal, vector& mvec, MachineCodeForInstruction& mcfi) { /* Use max. multiply cost, viz., cost of MULX */ - unsigned int cost = target.getInstrInfo().minLatency(MULX); - unsigned int firstNewInstr = mvec.size(); + unsigned cost = target.getInstrInfo().minLatency(MULX); + unsigned firstNewInstr = mvec.size(); Value* constOp = rval; if (! isa(constOp)) @@ -612,7 +613,7 @@ } else if (isPowerOf2(C, pow)) { - unsigned int opSize = target.DataLayout.getTypeSize(resultType); + unsigned opSize = target.getTargetData().getTypeSize(resultType); MachineOpCode opCode = (opSize <= 32)? SLL : SLLX; CreateShiftInstructions(target, F, opCode, lval, NULL, pow, destVal, mvec, mcfi); @@ -644,7 +645,7 @@ if (firstNewInstr < mvec.size()) { cost = 0; - for (unsigned int i=firstNewInstr; i < mvec.size(); ++i) + for (unsigned i=firstNewInstr; i < mvec.size(); ++i) cost += target.getInstrInfo().minLatency(mvec[i]->getOpCode()); } @@ -687,7 +688,7 @@ MachineCodeForInstruction& mcfi, MachineOpCode forceMulOp = INVALID_MACHINE_OPCODE) { - unsigned int L = mvec.size(); + unsigned L = mvec.size(); CreateCheapestMulConstInstruction(target,F, lval, rval, destVal, mvec, mcfi); if (mvec.size() == L) { // no instructions were added so create MUL reg, reg, reg. @@ -829,7 +830,7 @@ static void CreateCodeForVariableSizeAlloca(const TargetMachine& target, Instruction* result, - unsigned int tsize, + unsigned tsize, Value* numElementsVal, vector& getMvec) { @@ -895,7 +896,8 @@ // Instruction 3: add %sp, frameSizeBelowDynamicArea -> result M = new MachineInstr(ADD); M->SetMachineOperandReg(0, target.getRegInfo().getStackPointer()); - M->SetMachineOperandVal(1, MachineOperand::MO_VirtualRegister, dynamicAreaOffset); + M->SetMachineOperandVal(1, MachineOperand::MO_VirtualRegister, + dynamicAreaOffset); M->SetMachineOperandVal(2, MachineOperand::MO_VirtualRegister, result); getMvec.push_back(M); } @@ -904,8 +906,8 @@ static void CreateCodeForFixedSizeAlloca(const TargetMachine& target, Instruction* result, - unsigned int tsize, - unsigned int numElements, + unsigned tsize, + unsigned numElements, vector& getMvec) { assert(tsize > 0 && "Illegal (zero) type size for alloca"); @@ -918,20 +920,19 @@ // load/stores (check LDX because all load/stores have the same-size immediate // field). If not, put the variable in the dynamically sized area of the // frame. - unsigned int paddedSizeIgnored; - int offsetFromFP = mcInfo.computeOffsetforLocalVar(target, result, + unsigned paddedSizeIgnored; + int offsetFromFP = mcInfo.getInfo()->computeOffsetforLocalVar(result, paddedSizeIgnored, tsize * numElements); - if (! target.getInstrInfo().constantFitsInImmedField(LDX, offsetFromFP)) - { - CreateCodeForVariableSizeAlloca(target, result, tsize, - ConstantSInt::get(Type::IntTy,numElements), - getMvec); - return; - } + if (! target.getInstrInfo().constantFitsInImmedField(LDX, offsetFromFP)) { + CreateCodeForVariableSizeAlloca(target, result, tsize, + ConstantSInt::get(Type::IntTy,numElements), + getMvec); + return; + } // else offset fits in immediate field so go ahead and allocate it. - offsetFromFP = mcInfo.allocateLocalVar(target, result, tsize * numElements); + offsetFromFP = mcInfo.getInfo()->allocateLocalVar(result, tsize *numElements); // Create a temporary Value to hold the constant offset. // This is needed because it may not fit in the immediate field. @@ -995,7 +996,7 @@ { // Compute the offset value using the index vector. Create a // virtual reg. for it since it may not fit in the immed field. - uint64_t offset = target.DataLayout.getIndexedOffset(ptrType,idxVec); + uint64_t offset = target.getTargetData().getIndexedOffset(ptrType,idxVec); valueForRegOffset = ConstantSInt::get(Type::LongTy, offset); } else @@ -1025,7 +1026,7 @@ : ptrType); const Type* eltType = cast(vecType)->getElementType(); ConstantUInt* eltSizeVal = ConstantUInt::get(Type::ULongTy, - target.DataLayout.getTypeSize(eltType)); + target.getTargetData().getTypeSize(eltType)); // CreateMulInstruction() folds constants intelligently enough. CreateMulInstruction(target, memInst->getParent()->getParent(), @@ -1222,9 +1223,9 @@ bool maskUnsignedResult = false; int nextRule; int forwardOperandNum = -1; - unsigned int allocaSize = 0; + unsigned allocaSize = 0; MachineInstr* M, *M2; - unsigned int L; + unsigned L; mvec.clear(); @@ -1498,8 +1499,8 @@ const Type* opType = opVal->getType(); if (opType->isIntegral() || isa(opType)) { - unsigned opSize = target.DataLayout.getTypeSize(opType); - unsigned destSize = target.DataLayout.getTypeSize(destI->getType()); + unsigned opSize = target.getTargetData().getTypeSize(opType); + unsigned destSize = target.getTargetData().getTypeSize(destI->getType()); if (opSize >= destSize) { // Operand is same size as or larger than dest: // zero- or sign-extend, according to the signeddness of @@ -1592,7 +1593,7 @@ // double-prec for a 64-bit int. // uint64_t srcSize = - target.DataLayout.getTypeSize(leftVal->getType()); + target.getTargetData().getTypeSize(leftVal->getType()); Type* tmpTypeToUse = (srcSize <= 4)? Type::FloatTy : Type::DoubleTy; srcForCast = new TmpInstruction(tmpTypeToUse, dest); @@ -1703,7 +1704,8 @@ case 36: // reg: Div(reg, reg) maskUnsignedResult = true; - mvec.push_back(new MachineInstr(ChooseDivInstruction(target, subtreeRoot))); + mvec.push_back(new MachineInstr(ChooseDivInstruction(target, + subtreeRoot))); Set3OperandsFromInstr(mvec.back(), subtreeRoot, target); break; @@ -1947,8 +1949,8 @@ { // add %fp, offsetFromFP -> result AllocationInst* instr = cast(subtreeRoot->getInstruction()); - unsigned int tsize = - target.DataLayout.getTypeSize(instr->getAllocatedType()); + unsigned tsize = + target.getTargetData().getTypeSize(instr->getAllocatedType()); assert(tsize != 0); CreateCodeForFixedSizeAlloca(target, instr, tsize, 1, mvec); break; @@ -1963,14 +1965,14 @@ const Type* eltType = instr->getAllocatedType(); // If #elements is constant, use simpler code for fixed-size allocas - int tsize = (int) target.DataLayout.getTypeSize(eltType); + int tsize = (int) target.getTargetData().getTypeSize(eltType); Value* numElementsVal = NULL; bool isArray = instr->isArrayAllocation(); if (!isArray || isa(numElementsVal = instr->getArraySize())) { // total size is constant: generate code for fixed-size alloca - unsigned int numElements = isArray? + unsigned numElements = isArray? cast(numElementsVal)->getValue() : 1; CreateCodeForFixedSizeAlloca(target, instr, tsize, numElements, mvec); @@ -2157,7 +2159,7 @@ Instruction* dest = subtreeRoot->getInstruction(); if (dest->getType()->isUnsigned()) { - unsigned destSize = target.DataLayout.getTypeSize(dest->getType()); + unsigned destSize=target.getTargetData().getTypeSize(dest->getType()); if (destSize <= 4) { // Mask high bits. Use a TmpInstruction to represent the // intermediate result before masking. Since those instructions @@ -2173,7 +2175,7 @@ M = Create3OperandInstr_UImmed(SRL, tmpI, 8*(4-destSize), dest); mvec.push_back(M); } - else if (destSize < target.DataLayout.getIntegerRegize()) + else if (destSize < target.getTargetData().getIntegerRegize()) assert(0 && "Unsupported type size: 32 < size < 64 bits"); } } From lattner at cs.uiuc.edu Sat Dec 28 14:22:00 2002 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Sat Dec 28 14:22:00 2002 Subject: [llvm-commits] CVS: llvm/lib/Target/Sparc/SparcInstrInfo.cpp Message-ID: <200212282021.OAA11001@apoc.cs.uiuc.edu> Changes in directory llvm/lib/Target/Sparc: SparcInstrInfo.cpp updated: 1.32 -> 1.33 --- Log message: * TargetData is no longer directly accessable from TargetMachine * Constpool & frame info is no longer directly in MachineFunction --- Diffs of the changes: Index: llvm/lib/Target/Sparc/SparcInstrInfo.cpp diff -u llvm/lib/Target/Sparc/SparcInstrInfo.cpp:1.32 llvm/lib/Target/Sparc/SparcInstrInfo.cpp:1.33 --- llvm/lib/Target/Sparc/SparcInstrInfo.cpp:1.32 Tue Oct 29 09:45:20 2002 +++ llvm/lib/Target/Sparc/SparcInstrInfo.cpp Sat Dec 28 14:18:21 2002 @@ -7,6 +7,7 @@ #include "llvm/CodeGen/InstrSelection.h" #include "llvm/CodeGen/InstrSelectionSupport.h" #include "llvm/CodeGen/MachineFunction.h" +#include "llvm/CodeGen/MachineFunctionInfo.h" #include "llvm/CodeGen/MachineCodeForInstruction.h" #include "llvm/Function.h" #include "llvm/Constants.h" @@ -396,8 +397,8 @@ else if (valType->isIntegral()) { bool isValidConstant; - unsigned opSize = target.DataLayout.getTypeSize(val->getType()); - unsigned destSize = target.DataLayout.getTypeSize(dest->getType()); + unsigned opSize = target.getTargetData().getTypeSize(val->getType()); + unsigned destSize = target.getTargetData().getTypeSize(dest->getType()); if (! dest->getType()->isSigned()) { @@ -406,7 +407,7 @@ if (opSize > destSize || (val->getType()->isSigned() - && destSize < target.DataLayout.getIntegerRegize())) + && destSize < target.getTargetData().getIntegerRegize())) { // operand is larger than dest, // OR both are equal but smaller than the full register size // AND operand is signed, so it may have extra sign bits: @@ -461,7 +462,7 @@ mvec.push_back(MI); // Make sure constant is emitted to constant pool in assembly code. - MachineFunction::get(F).addToConstantPool(cast(val)); + MachineFunction::get(F).getInfo()->addToConstantPool(cast(val)); } } @@ -487,10 +488,10 @@ && "Dest type must be float/double"); // Get a stack slot to use for the copy - int offset = MachineFunction::get(F).allocateLocalVar(target, val); + int offset = MachineFunction::get(F).getInfo()->allocateLocalVar(val); // Get the size of the source value being copied. - size_t srcSize = target.DataLayout.getTypeSize(val->getType()); + size_t srcSize = target.getTargetData().getTypeSize(val->getType()); // Store instruction stores `val' to [%fp+offset]. // The store and load opCodes are based on the size of the source value. @@ -499,7 +500,7 @@ // Note that the store instruction is the same for signed and unsigned ints. const Type* storeType = (srcSize <= 4)? Type::IntTy : Type::LongTy; Value* storeVal = val; - if (srcSize < target.DataLayout.getTypeSize(Type::FloatTy)) + if (srcSize < target.getTargetData().getTypeSize(Type::FloatTy)) { // sign- or zero-extend respectively storeVal = new TmpInstruction(storeType, val); if (val->getType()->isSigned()) @@ -549,7 +550,7 @@ assert((destTy->isIntegral() || isa(destTy)) && "Dest type must be integer, bool or pointer"); - int offset = MachineFunction::get(F).allocateLocalVar(target, val); + int offset = MachineFunction::get(F).getInfo()->allocateLocalVar(val); // Store instruction stores `val' to [%fp+offset]. // The store opCode is based only the source value being copied. From lattner at cs.uiuc.edu Sat Dec 28 14:22:04 2002 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Sat Dec 28 14:22:04 2002 Subject: [llvm-commits] CVS: llvm/lib/Target/Sparc/SparcInternals.h Message-ID: <200212282021.OAA11007@apoc.cs.uiuc.edu> Changes in directory llvm/lib/Target/Sparc: SparcInternals.h updated: 1.73 -> 1.74 --- Log message: * Rename MachineFrameInfo to TargetFrameInfo * Move some sparc specific code here from Target files --- Diffs of the changes: Index: llvm/lib/Target/Sparc/SparcInternals.h diff -u llvm/lib/Target/Sparc/SparcInternals.h:1.73 llvm/lib/Target/Sparc/SparcInternals.h:1.74 --- llvm/lib/Target/Sparc/SparcInternals.h:1.73 Tue Oct 29 16:01:44 2002 +++ llvm/lib/Target/Sparc/SparcInternals.h Sat Dec 28 14:20:24 2002 @@ -528,9 +528,11 @@ // a multiple of getStackFrameSizeAlignment(). //--------------------------------------------------------------------------- -class UltraSparcFrameInfo: public MachineFrameInfo { +class UltraSparcFrameInfo: public TargetFrameInfo { + const TargetMachine ⌖ public: - UltraSparcFrameInfo(const TargetMachine &tgt) : MachineFrameInfo(tgt) {} + UltraSparcFrameInfo(const TargetMachine &TM) + : TargetFrameInfo(StackGrowsDown, StackFrameSizeAlignment, 0), target(TM) {} public: // These methods provide constant parameters of the frame layout. @@ -603,6 +605,28 @@ virtual int getDynamicAreaBaseRegNum() const { return (int) target.getRegInfo().getStackPointer(); } + + virtual int getIncomingArgOffset(MachineFunction& mcInfo, + unsigned argNum) const { + assert(argsOnStackHaveFixedSize()); + + unsigned relativeOffset = argNum * getSizeOfEachArgOnStack(); + bool growUp; // do args grow up or down + int firstArg = getFirstIncomingArgOffset(mcInfo, growUp); + return growUp ? firstArg + relativeOffset : firstArg - relativeOffset; + } + + virtual int getOutgoingArgOffset(MachineFunction& mcInfo, + unsigned argNum) const { + assert(argsOnStackHaveFixedSize()); + //assert(((int) argNum - this->getNumFixedOutgoingArgs()) + // <= (int) mcInfo.getInfo()->getMaxOptionalNumArgs()); + + unsigned relativeOffset = argNum * getSizeOfEachArgOnStack(); + bool growUp; // do args grow up or down + int firstArg = getFirstOutgoingArgOffset(mcInfo, growUp); + return growUp ? firstArg + relativeOffset : firstArg - relativeOffset; + } private: /*---------------------------------------------------------------------- @@ -612,7 +636,7 @@ by us. The rest conform to the Sparc V9 ABI. All stack addresses are offset by OFFSET = 0x7ff (2047). - Alignment assumpteions and other invariants: + Alignment assumptions and other invariants: (1) %sp+OFFSET and %fp+OFFSET are always aligned on 16-byte boundary (2) Variables in automatic, spill, temporary, or dynamic regions are aligned according to their size as in all memory accesses. @@ -714,7 +738,7 @@ virtual const MachineInstrInfo &getInstrInfo() const { return instrInfo; } virtual const MachineSchedInfo &getSchedInfo() const { return schedInfo; } virtual const MachineRegInfo &getRegInfo() const { return regInfo; } - virtual const MachineFrameInfo &getFrameInfo() const { return frameInfo; } + virtual const TargetFrameInfo &getFrameInfo() const { return frameInfo; } virtual const MachineCacheInfo &getCacheInfo() const { return cacheInfo; } virtual const MachineOptInfo &getOptInfo() const { return optInfo; } From lattner at cs.uiuc.edu Sat Dec 28 14:22:07 2002 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Sat Dec 28 14:22:07 2002 Subject: [llvm-commits] CVS: llvm/lib/Target/Sparc/SparcRegInfo.cpp Message-ID: <200212282021.OAA11031@apoc.cs.uiuc.edu> Changes in directory llvm/lib/Target/Sparc: SparcRegInfo.cpp updated: 1.81 -> 1.82 --- Log message: * Rename machineFrameInfo to targetFrameInfo * Constant pool and frame info is no longer directly in MachineFunction --- Diffs of the changes: Index: llvm/lib/Target/Sparc/SparcRegInfo.cpp diff -u llvm/lib/Target/Sparc/SparcRegInfo.cpp:1.81 llvm/lib/Target/Sparc/SparcRegInfo.cpp:1.82 --- llvm/lib/Target/Sparc/SparcRegInfo.cpp:1.81 Tue Oct 29 14:47:46 2002 +++ llvm/lib/Target/Sparc/SparcRegInfo.cpp Sat Dec 28 14:21:29 2002 @@ -8,6 +8,7 @@ #include "SparcInternals.h" #include "SparcRegClassInfo.h" #include "llvm/CodeGen/MachineFunction.h" +#include "llvm/CodeGen/MachineFunctionInfo.h" #include "llvm/CodeGen/PhyRegAlloc.h" #include "llvm/CodeGen/InstrSelection.h" #include "llvm/CodeGen/InstrSelectionSupport.h" @@ -19,7 +20,6 @@ #include "llvm/iOther.h" #include "llvm/Function.h" #include "llvm/DerivedTypes.h" -#include #include using std::cerr; using std::vector; @@ -476,7 +476,7 @@ regClassIDOfArgReg == IntRegClassID && "This should only be an Int register for an FP argument"); - int TmpOff = MachineFunction::get(Meth).pushTempValue(target, + int TmpOff = MachineFunction::get(Meth).getInfo()->pushTempValue( getSpilledRegSize(regType)); cpReg2MemMI(FirstAI->InstrnsBefore, UniArgReg, getFramePointer(), TmpOff, IntRegType); @@ -493,7 +493,7 @@ // Now the arg is coming on stack. Since the LR recieved a register, // we just have to load the arg on stack into that register // - const MachineFrameInfo& frameInfo = target.getFrameInfo(); + const TargetFrameInfo& frameInfo = target.getFrameInfo(); int offsetFromFP = frameInfo.getIncomingArgOffset(MachineFunction::get(Meth), argNo); @@ -541,7 +541,7 @@ // since this method is called before any other method that makes // uses of the stack pos of the LR (e.g., updateMachineInstr) - const MachineFrameInfo& frameInfo = target.getFrameInfo(); + const TargetFrameInfo& frameInfo = target.getFrameInfo(); int offsetFromFP = frameInfo.getIncomingArgOffset(MachineFunction::get(Meth), argNo); @@ -651,7 +651,7 @@ AddedInstrns *CallAI, PhyRegAlloc &PRA, LiveRange* LR, unsigned regType, unsigned RegClassID, - int UniArgRegOrNone, unsigned int argNo, + int UniArgRegOrNone, unsigned argNo, std::vector& AddedInstrnsBefore) const { @@ -681,7 +681,7 @@ } else { // Copy UniLRReg to the stack to pass the arg on stack. - const MachineFrameInfo& frameInfo = target.getFrameInfo(); + const TargetFrameInfo& frameInfo = target.getFrameInfo(); int argOffset = frameInfo.getOutgoingArgOffset(PRA.MF, argNo); cpReg2MemMI(CallAI->InstrnsBefore, UniLRReg, getStackPointer(), argOffset, regType); @@ -704,9 +704,9 @@ // Use TmpOff to save TReg, since that may have a live value. // int TReg = PRA.getUniRegNotUsedByThisInst( LR->getRegClass(), CallMI ); - int TmpOff = PRA.MF.pushTempValue(target, - getSpilledRegSize(getRegType(LR))); - const MachineFrameInfo& frameInfo = target.getFrameInfo(); + int TmpOff = PRA.MF.getInfo()-> + pushTempValue(getSpilledRegSize(getRegType(LR))); + const TargetFrameInfo& frameInfo = target.getFrameInfo(); int argOffset = frameInfo.getOutgoingArgOffset(PRA.MF, argNo); MachineInstr *Ad1, *Ad2, *Ad3, *Ad4; @@ -1411,8 +1411,8 @@ // and add them to InstrnsBefore and InstrnsAfter of the // call instruction // - int StackOff = PRA.MF.pushTempValue(target, - getSpilledRegSize(RegType)); + int StackOff = + PRA.MF.getInfo()->pushTempValue(getSpilledRegSize(RegType)); vector AdIBef, AdIAft; @@ -1661,8 +1661,8 @@ if (DebugPrint && DEBUG_RA) { cerr << "\nAdded instructions were reordered to:\n"; - for(unsigned int i=0; i < OrdVec.size(); i++) - cerr << *(OrdVec[i]); + for(unsigned i=0; i < OrdVec.size(); i++) + cerr << *OrdVec[i]; } } @@ -1711,16 +1711,15 @@ int RegType = getRegType(UReg); MachineInstr *AdIBef, *AdIAft; - const int StackOff = PRA.MF.pushTempValue(target, - getSpilledRegSize(RegType)); + int StackOff = + PRA.MF.getInfo()->pushTempValue(getSpilledRegSize(RegType)); // Save the UReg (%ox) on stack before it's destroyed vector mvec; cpReg2MemMI(mvec, UReg, getFramePointer(), StackOff, RegType); - for (vector::iterator MI=mvec.begin(); MI != mvec.end(); ++MI) { - OrdIt = OrdVec.insert(OrdIt, *MI); - ++OrdIt; // OrdIt must still point to current instr we processed - } + for (vector::iterator MI=mvec.begin(); + MI != mvec.end(); ++MI) + OrdIt = 1+OrdVec.insert(OrdIt, *MI); // Load directly into DReg (%oy) MachineOperand& DOp= From lattner at cs.uiuc.edu Sat Dec 28 14:26:01 2002 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Sat Dec 28 14:26:01 2002 Subject: [llvm-commits] CVS: llvm/lib/Target/X86/InstSelectSimple.cpp Message-ID: <200212282025.OAA11372@apoc.cs.uiuc.edu> Changes in directory llvm/lib/Target/X86: InstSelectSimple.cpp updated: 1.78 -> 1.79 --- Log message: * Use the new Abstract Frame Manager to handle incoming arguments and fixed size allocas * Revamp call emission to work with new frame manager --- Diffs of the changes: Index: llvm/lib/Target/X86/InstSelectSimple.cpp diff -u llvm/lib/Target/X86/InstSelectSimple.cpp:1.78 llvm/lib/Target/X86/InstSelectSimple.cpp:1.79 --- llvm/lib/Target/X86/InstSelectSimple.cpp:1.78 Tue Dec 24 23:13:53 2002 +++ llvm/lib/Target/X86/InstSelectSimple.cpp Sat Dec 28 14:24:02 2002 @@ -20,6 +20,7 @@ #include "llvm/CodeGen/MachineFunction.h" #include "llvm/CodeGen/MachineInstrBuilder.h" #include "llvm/CodeGen/SSARegMap.h" +#include "llvm/CodeGen/FunctionFrameInfo.h" #include "llvm/Target/TargetMachine.h" #include "llvm/Support/InstVisitor.h" #include "llvm/Target/MRegisterInfo.h" @@ -73,29 +74,12 @@ bool runOnFunction(Function &Fn) { F = &MachineFunction::construct(&Fn, TM); + // Create all of the machine basic blocks for the function... for (Function::iterator I = Fn.begin(), E = Fn.end(); I != E; ++I) F->getBasicBlockList().push_back(MBBMap[I] = new MachineBasicBlock(I)); - // Emit instructions to load the arguments... The function's arguments - // look like this: - // - // [EBP] -- copy of old EBP - // [EBP + 4] -- return address - // [EBP + 8] -- first argument (leftmost lexically) - // - // So we want to start with counter = 2. - // BB = &F->front(); - unsigned ArgOffset = 8; - for (Function::aiterator I = Fn.abegin(), E = Fn.aend(); I != E; - ++I, ArgOffset += 4) { - unsigned Reg = getReg(*I); - - // Load it out of the stack frame at EBP + 4*argPos. - - // FIXME: This should load the argument of the appropriate size!! - addRegOffset(BuildMI(BB, X86::MOVmr32, 4, Reg), X86::EBP, ArgOffset); - } + LoadArgumentsToVirtualRegs(Fn); // Instruction select everything except PHI nodes visit(Fn); @@ -123,6 +107,10 @@ BB = MBBMap[&LLVM_BB]; } + /// LoadArgumentsToVirtualRegs - Load all of the arguments to this function + /// from the stack into virtual registers. + /// + void LoadArgumentsToVirtualRegs(Function &F); /// SelectPHINodes - Insert machine code to generate phis. This is tricky /// because we have to generate our sources into the source basic blocks, @@ -170,9 +158,12 @@ void visitLoadInst(LoadInst &I); void visitStoreInst(StoreInst &I); void visitGetElementPtrInst(GetElementPtrInst &I); - void visitMallocInst(MallocInst &I); - void visitFreeInst(FreeInst &I); void visitAllocaInst(AllocaInst &I); + + // We assume that by this point, malloc instructions have been + // lowered to calls, and dlsym will magically find malloc for us. + void visitMallocInst(MallocInst &I) { visitInstruction (I); } + void visitFreeInst(FreeInst &I) { visitInstruction(I); } // Other operators void visitShiftInst(ShiftInst &I); @@ -341,6 +332,59 @@ } } +/// LoadArgumentsToVirtualRegs - Load all of the arguments to this function from +/// the stack into virtual registers. +/// +void ISel::LoadArgumentsToVirtualRegs(Function &Fn) { + // Emit instructions to load the arguments... On entry to a function on the + // X86, the stack frame looks like this: + // + // [ESP] -- return address + // [ESP + 4] -- first argument (leftmost lexically) if four bytes in size + // [ESP + 8] -- second argument, if four bytes in size + // ... + // + unsigned ArgOffset = 0; + FunctionFrameInfo *FFI = F->getFrameInfo(); + + for (Function::aiterator I = Fn.abegin(), E = Fn.aend(); I != E; ++I) { + unsigned Reg = getReg(*I); + + ArgOffset += 4; // Each argument takes at least 4 bytes on the stack... + int FI; // Frame object index + + switch (getClassB(I->getType())) { + case cByte: + FI = FFI->CreateFixedObject(1, ArgOffset); + addFrameReference(BuildMI(BB, X86::MOVmr8, 4, Reg), FI); + break; + case cShort: + FI = FFI->CreateFixedObject(2, ArgOffset); + addFrameReference(BuildMI(BB, X86::MOVmr16, 4, Reg), FI); + break; + case cInt: + FI = FFI->CreateFixedObject(4, ArgOffset); + addFrameReference(BuildMI(BB, X86::MOVmr32, 4, Reg), FI); + break; + case cFP: + unsigned Opcode; + if (I->getType() == Type::FloatTy) { + Opcode = X86::FLDr32; + FI = FFI->CreateFixedObject(4, ArgOffset); + } else { + Opcode = X86::FLDr64; + ArgOffset += 4; // doubles require 4 additional bytes + FI = FFI->CreateFixedObject(8, ArgOffset); + } + addFrameReference(BuildMI(BB, Opcode, 4, Reg), FI); + break; + default: + assert(0 && "Unhandled argument type!"); + } + } +} + + /// SelectPHINodes - Insert machine code to generate phis. This is tricky /// because we have to generate our sources into the source basic blocks, not /// the current one. @@ -366,7 +410,8 @@ // available in a virtual register, insert the computation code into // PredMBB // - + // FIXME: This should insert the code into the BOTTOM of the block, not + // the top of the block. This just makes for huge live ranges... MachineBasicBlock::iterator PI = PredMBB->begin(); while ((*PI)->getOpcode() == X86::PHI) ++PI; @@ -532,7 +577,7 @@ // Compare condition with zero, followed by jump-if-equal to ifFalse, and // jump-if-nonequal to ifTrue - unsigned int condReg = getReg(BI.getCondition()); + unsigned condReg = getReg(BI.getCondition()); BuildMI(BB, X86::CMPri8, 2).addReg(condReg).addZImm(0); BuildMI(BB, X86::JNE, 1).addPCDisp(BI.getSuccessor(0)); BuildMI(BB, X86::JE, 1).addPCDisp(BI.getSuccessor(1)); @@ -543,32 +588,64 @@ /// visitCallInst - Push args on stack and do a procedure call instruction. void ISel::visitCallInst(CallInst &CI) { - // keep a counter of how many bytes we pushed on the stack - unsigned bytesPushed = 0; + // Count how many bytes are to be pushed on the stack... + unsigned NumBytes = 0; - // Push the arguments on the stack in reverse order, as specified by - // the ABI. - for (unsigned i = CI.getNumOperands()-1; i >= 1; --i) { - Value *v = CI.getOperand(i); - switch (getClass(v->getType())) { - case cByte: - case cShort: - // Promote V to 32 bits wide, and move the result into EAX, - // then push EAX. - promote32 (X86::EAX, v); - BuildMI(BB, X86::PUSHr32, 1).addReg(X86::EAX); - bytesPushed += 4; - break; - case cInt: { - unsigned Reg = getReg(v); - BuildMI(BB, X86::PUSHr32, 1).addReg(Reg); - bytesPushed += 4; - break; - } - default: - // FIXME: long/ulong/float/double args not handled. - visitInstruction(CI); - break; + if (CI.getNumOperands() > 1) { + for (unsigned i = 1, e = CI.getNumOperands(); i != e; ++i) + switch (getClass(CI.getOperand(i)->getType())) { + case cByte: case cShort: case cInt: + NumBytes += 4; + break; + case cLong: + NumBytes += 8; + break; + case cFP: + NumBytes += CI.getOperand(i)->getType() == Type::FloatTy ? 4 : 8; + break; + default: assert(0 && "Unknown class!"); + } + + // Adjust the stack pointer for the new arguments... + BuildMI(BB, X86::ADJCALLSTACKDOWN, 1).addZImm(NumBytes); + + // Arguments go on the stack in reverse order, as specified by the ABI. + unsigned ArgOffset = 0; + for (unsigned i = 1, e = CI.getNumOperands(); i != e; ++i) { + Value *Arg = CI.getOperand(i); + switch (getClass(Arg->getType())) { + case cByte: + case cShort: { + // Promote arg to 32 bits wide into a temporary register... + unsigned R = makeAnotherReg(Type::UIntTy); + promote32(R, Arg); + addRegOffset(BuildMI(BB, X86::MOVrm32, 5), + X86::ESP, ArgOffset).addReg(R); + break; + } + case cInt: + addRegOffset(BuildMI(BB, X86::MOVrm32, 5), + X86::ESP, ArgOffset).addReg(getReg(Arg)); + break; + + case cFP: + if (Arg->getType() == Type::FloatTy) { + addRegOffset(BuildMI(BB, X86::FSTr32, 5), + X86::ESP, ArgOffset).addReg(getReg(Arg)); + } else { + assert(Arg->getType() == Type::DoubleTy && "Unknown FP type!"); + ArgOffset += 4; + addRegOffset(BuildMI(BB, X86::FSTr32, 5), + X86::ESP, ArgOffset).addReg(getReg(Arg)); + } + break; + + default: + // FIXME: long/ulong/float/double args not handled. + visitInstruction(CI); + break; + } + ArgOffset += 4; } } @@ -580,9 +657,7 @@ BuildMI(BB, X86::CALLr32, 1).addReg(Reg); } - // Adjust the stack by `bytesPushed' amount if non-zero - if (bytesPushed > 0) - BuildMI(BB, X86::ADDri32,2, X86::ESP).addReg(X86::ESP).addZImm(bytesPushed); + BuildMI(BB, X86::ADJCALLSTACKUP, 1).addZImm(NumBytes); // If there is a return value, scavenge the result from the location the call // leaves it in... @@ -771,7 +846,7 @@ if (OperandClass > cInt) visitInstruction(I); // Can't handle longs yet! - if (ConstantUInt *CUI = dyn_cast (I.getOperand (1))) + if (ConstantUInt *CUI = dyn_cast (I.getOperand (1))) { // The shift amount is constant, guaranteed to be a ubyte. Get its value. assert(CUI->getType() == Type::UByteTy && "Shift amount not a ubyte?"); @@ -956,9 +1031,9 @@ { const Type *targetType = CI.getType (); Value *operand = CI.getOperand (0); - unsigned int operandReg = getReg (operand); + unsigned operandReg = getReg (operand); const Type *sourceType = operand->getType (); - unsigned int destReg = getReg (CI); + unsigned destReg = getReg (CI); // // Currently we handle: // @@ -1075,11 +1150,11 @@ oe = IdxEnd; oi != oe; ++oi) { Value *idx = *oi; unsigned nextBasePtrReg = makeAnotherReg(Type::UIntTy); - if (const StructType *StTy = dyn_cast (Ty)) { + if (const StructType *StTy = dyn_cast(Ty)) { // It's a struct access. idx is the index into the structure, // which names the field. This index must have ubyte type. - const ConstantUInt *CUI = cast (idx); - assert (CUI->getType () == Type::UByteTy + const ConstantUInt *CUI = cast(idx); + assert(CUI->getType() == Type::UByteTy && "Funny-looking structure index in GEP"); // Use the TargetData structure to pick out what the layout of // the structure is in memory. Since the structure index must @@ -1088,14 +1163,14 @@ // structure member offsets. unsigned idxValue = CUI->getValue(); unsigned memberOffset = - TD.getStructLayout (StTy)->MemberOffsets[idxValue]; + TD.getStructLayout(StTy)->MemberOffsets[idxValue]; // Emit an ADD to add memberOffset to the basePtr. BMI(MBB, IP, X86::ADDri32, 2, - nextBasePtrReg).addReg (basePtrReg).addZImm (memberOffset); + nextBasePtrReg).addReg(basePtrReg).addZImm(memberOffset); // The next type is the member of the structure selected by the // index. - Ty = StTy->getElementTypes ()[idxValue]; - } else if (const SequentialType *SqTy = cast (Ty)) { + Ty = StTy->getElementTypes()[idxValue]; + } else if (const SequentialType *SqTy = cast(Ty)) { // It's an array or pointer access: [ArraySize x ElementType]. // idx is the index into the array. Unlike with structure @@ -1103,7 +1178,7 @@ // time. assert(idx->getType() == Type::LongTy && "Bad GEP array index!"); - // We want to add basePtrReg to (idxReg * sizeof ElementType). First, we + // We want to add basePtrReg to(idxReg * sizeof ElementType). First, we // must find the size of the pointed-to type (Not coincidentally, the next // type is the type of the elements in the array). Ty = SqTy->getElementType(); @@ -1143,7 +1218,7 @@ } // Emit an ADD to add OffsetReg to the basePtr. BMI(MBB, IP, X86::ADDrr32, 2, - nextBasePtrReg).addReg (basePtrReg).addReg (OffsetReg); + nextBasePtrReg).addReg(basePtrReg).addReg(OffsetReg); } } // Now that we are here, further indices refer to subtypes of this @@ -1154,51 +1229,62 @@ // basePtrReg. Move it to the register where we were expected to // put the answer. A 32-bit move should do it, because we are in // ILP32 land. - BMI(MBB, IP, X86::MOVrr32, 1, TargetReg).addReg (basePtrReg); -} - - -/// visitMallocInst - I know that personally, whenever I want to remember -/// something, I have to clear off some space in my brain. -void -ISel::visitMallocInst (MallocInst &I) -{ - // We assume that by this point, malloc instructions have been - // lowered to calls, and dlsym will magically find malloc for us. - // So we do not want to see malloc instructions here. - visitInstruction (I); + BMI(MBB, IP, X86::MOVrr32, 1, TargetReg).addReg(basePtrReg); } -/// visitFreeInst - same story as MallocInst -void -ISel::visitFreeInst (FreeInst &I) -{ - // We assume that by this point, free instructions have been - // lowered to calls, and dlsym will magically find free for us. - // So we do not want to see free instructions here. - visitInstruction (I); -} +/// visitAllocaInst - If this is a fixed size alloca, allocate space from the +/// frame manager, otherwise do it the hard way. +/// +void ISel::visitAllocaInst(AllocaInst &I) { + // Find the data size of the alloca inst's getAllocatedType. + const Type *Ty = I.getAllocatedType(); + unsigned TySize = TM.getTargetData().getTypeSize(Ty); + // If this is a fixed size alloca in the entry block for the function, + // statically stack allocate the space. + // + if (ConstantUInt *CUI = dyn_cast(I.getArraySize())) { + if (I.getParent() == I.getParent()->getParent()->begin()) { + TySize *= CUI->getValue(); // Get total allocated size... + unsigned Alignment = TM.getTargetData().getTypeAlignment(Ty); + + // Create a new stack object using the frame manager... + int FrameIdx = F->getFrameInfo()->CreateStackObject(TySize, Alignment); + addFrameReference(BuildMI(BB, X86::LEAr32, 5, getReg(I)), FrameIdx); + return; + } + } + + // Create a register to hold the temporary result of multiplying the type size + // constant by the variable amount. + unsigned TotalSizeReg = makeAnotherReg(Type::UIntTy); + unsigned SrcReg1 = getReg(I.getArraySize()); + unsigned SizeReg = makeAnotherReg(Type::UIntTy); + BuildMI(BB, X86::MOVir32, 1, SizeReg).addZImm(TySize); + + // TotalSizeReg = mul , + MachineBasicBlock::iterator MBBI = BB->end(); + doMultiply(BB, MBBI, TotalSizeReg, Type::UIntTy, SrcReg1, SizeReg); -/// visitAllocaInst - I want some stack space. Come on, man, I said I -/// want some freakin' stack space. -void -ISel::visitAllocaInst (AllocaInst &I) -{ - // Find the data size of the alloca inst's getAllocatedType. - const Type *allocatedType = I.getAllocatedType (); - const TargetData &TD = TM.DataLayout; - unsigned allocatedTypeSize = TD.getTypeSize (allocatedType); - // Keep stack 32-bit aligned. - unsigned int allocatedTypeWords = allocatedTypeSize / 4; - if (allocatedTypeSize % 4 != 0) { allocatedTypeWords++; } + // AddedSize = add , 15 + unsigned AddedSizeReg = makeAnotherReg(Type::UIntTy); + BuildMI(BB, X86::ADDri32, 2, AddedSizeReg).addReg(TotalSizeReg).addZImm(15); + + // AlignedSize = and , ~15 + unsigned AlignedSize = makeAnotherReg(Type::UIntTy); + BuildMI(BB, X86::ANDri32, 2, AlignedSize).addReg(AddedSizeReg).addZImm(~15); + // Subtract size from stack pointer, thereby allocating some space. - BuildMI(BB, X86::SUBri32, 2, - X86::ESP).addReg(X86::ESP).addZImm(allocatedTypeWords * 4); + BuildMI(BB, X86::SUBri32, 2, X86::ESP).addReg(X86::ESP).addZImm(AlignedSize); + // Put a pointer to the space into the result register, by copying // the stack pointer. - BuildMI (BB, X86::MOVrr32, 1, getReg (I)).addReg (X86::ESP); + BuildMI(BB, X86::MOVrr32, 1, getReg(I)).addReg(X86::ESP); + + // Inform the Frame Information that we have just allocated a variable sized + // object. + F->getFrameInfo()->CreateVariableSizedObject(); } From lattner at cs.uiuc.edu Sat Dec 28 14:27:01 2002 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Sat Dec 28 14:27:01 2002 Subject: [llvm-commits] CVS: llvm/lib/Target/X86/Printer.cpp Message-ID: <200212282026.OAA11383@apoc.cs.uiuc.edu> Changes in directory llvm/lib/Target/X86: Printer.cpp updated: 1.31 -> 1.32 --- Log message: * Convert to a MachineFunctionPass * Don't take a TM as a ctor parameter * Print [X - Y] instead of [X + -Y] when possible --- Diffs of the changes: Index: llvm/lib/Target/X86/Printer.cpp diff -u llvm/lib/Target/X86/Printer.cpp:1.31 llvm/lib/Target/X86/Printer.cpp:1.32 --- llvm/lib/Target/X86/Printer.cpp:1.31 Tue Dec 24 23:09:01 2002 +++ llvm/lib/Target/X86/Printer.cpp Sat Dec 28 14:25:38 2002 @@ -7,25 +7,23 @@ #include "X86.h" #include "X86InstrInfo.h" -#include "llvm/Pass.h" #include "llvm/Function.h" #include "llvm/Target/TargetMachine.h" -#include "llvm/CodeGen/MachineFunction.h" +#include "llvm/CodeGen/MachineFunctionPass.h" #include "llvm/CodeGen/MachineInstr.h" #include "Support/Statistic.h" namespace { - struct Printer : public FunctionPass { - TargetMachine &TM; + struct Printer : public MachineFunctionPass { std::ostream &O; - Printer(TargetMachine &tm, std::ostream &o) : TM(tm), O(o) {} + Printer(std::ostream &o) : O(o) {} virtual const char *getPassName() const { return "X86 Assembly Printer"; } - bool runOnFunction(Function &F); + bool runOnMachineFunction(MachineFunction &F); }; } @@ -33,38 +31,35 @@ /// the specified stream. This function should work regardless of whether or /// not the function is in SSA form or not. /// -Pass *createX86CodePrinterPass(TargetMachine &TM, std::ostream &O) { - return new Printer(TM, O); +Pass *createX86CodePrinterPass(std::ostream &O) { + return new Printer(O); } /// runOnFunction - This uses the X86InstructionInfo::print method /// to print assembly for each instruction. -bool Printer::runOnFunction (Function & F) -{ - static unsigned bbnumber = 0; - MachineFunction & MF = MachineFunction::get (&F); - const MachineInstrInfo & MII = TM.getInstrInfo (); +bool Printer::runOnMachineFunction(MachineFunction &MF) { + static unsigned BBNumber = 0; + const TargetMachine &TM = MF.getTarget(); + const MachineInstrInfo &MII = TM.getInstrInfo(); // Print out labels for the function. - O << "\t.globl\t" << F.getName () << "\n"; - O << "\t.type\t" << F.getName () << ", @function\n"; - O << F.getName () << ":\n"; + O << "\t.globl\t" << MF.getFunction()->getName() << "\n"; + O << "\t.type\t" << MF.getFunction()->getName() << ", @function\n"; + O << MF.getFunction()->getName() << ":\n"; // Print out code for the function. - for (MachineFunction::const_iterator bb_i = MF.begin (), bb_e = MF.end (); - bb_i != bb_e; ++bb_i) - { - // Print a label for the basic block. - O << ".BB" << bbnumber++ << ":\n"; - for (MachineBasicBlock::const_iterator i_i = bb_i->begin (), i_e = - bb_i->end (); i_i != i_e; ++i_i) - { - // Print the assembly for the instruction. - O << "\t"; - MII.print(*i_i, O, TM); - } + for (MachineFunction::const_iterator I = MF.begin(), E = MF.end(); + I != E; ++I) { + // Print a label for the basic block. + O << ".BB" << BBNumber++ << ":\n"; + for (MachineBasicBlock::const_iterator II = I->begin(), E = I->end(); + II != E; ++II) { + // Print the assembly for the instruction. + O << "\t"; + MII.print(*II, O, TM); } + } // We didn't modify anything. return false; @@ -109,7 +104,7 @@ } } -static const std::string sizePtr (const MachineInstrDescriptor &Desc) { +static const std::string sizePtr(const MachineInstrDescriptor &Desc) { switch (Desc.TSFlags & X86II::ArgMask) { default: assert(0 && "Unknown arg size!"); case X86II::Arg8: return "BYTE PTR"; @@ -125,9 +120,9 @@ unsigned Op, const MRegisterInfo &RI) { assert(isMem(MI, Op) && "Invalid memory reference!"); const MachineOperand &BaseReg = MI->getOperand(Op); - const MachineOperand &Scale = MI->getOperand(Op+1); + int ScaleVal = MI->getOperand(Op+1).getImmedValue(); const MachineOperand &IndexReg = MI->getOperand(Op+2); - const MachineOperand &Disp = MI->getOperand(Op+3); + int DispVal = MI->getOperand(Op+3).getImmedValue(); O << "["; bool NeedPlus = false; @@ -138,15 +133,21 @@ if (IndexReg.getReg()) { if (NeedPlus) O << " + "; - if (Scale.getImmedValue() != 1) - O << Scale.getImmedValue() << "*"; + if (ScaleVal != 1) + O << ScaleVal << "*"; printOp(O, IndexReg, RI); NeedPlus = true; } - if (Disp.getImmedValue()) { - if (NeedPlus) O << " + "; - printOp(O, Disp, RI); + if (DispVal) { + if (NeedPlus) + if (DispVal > 0) + O << " + "; + else { + O << " - "; + DispVal = -DispVal; + } + O << DispVal; } O << "]"; } From lattner at cs.uiuc.edu Sat Dec 28 14:27:05 2002 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Sat Dec 28 14:27:05 2002 Subject: [llvm-commits] CVS: llvm/lib/Target/X86/MachineCodeEmitter.cpp Message-ID: <200212282026.OAA11394@apoc.cs.uiuc.edu> Changes in directory llvm/lib/Target/X86: MachineCodeEmitter.cpp updated: 1.16 -> 1.17 --- Log message: * Convert to a MachineFunctionPass * ctor doesn't take TM argument * handle direct ESP references correctly! --- Diffs of the changes: Index: llvm/lib/Target/X86/MachineCodeEmitter.cpp diff -u llvm/lib/Target/X86/MachineCodeEmitter.cpp:1.16 llvm/lib/Target/X86/MachineCodeEmitter.cpp:1.17 --- llvm/lib/Target/X86/MachineCodeEmitter.cpp:1.16 Tue Dec 24 23:09:21 2002 +++ llvm/lib/Target/X86/MachineCodeEmitter.cpp Sat Dec 28 14:24:48 2002 @@ -9,21 +9,19 @@ #include "X86.h" #include "llvm/PassManager.h" #include "llvm/CodeGen/MachineCodeEmitter.h" -#include "llvm/CodeGen/MachineFunction.h" +#include "llvm/CodeGen/MachineFunctionPass.h" #include "llvm/CodeGen/MachineInstr.h" #include "llvm/Value.h" namespace { - class Emitter : public FunctionPass { - X86TargetMachine &TM; - const X86InstrInfo &II; + class Emitter : public MachineFunctionPass { + const X86InstrInfo *II; MachineCodeEmitter &MCE; public: - Emitter(X86TargetMachine &tm, MachineCodeEmitter &mce) - : TM(tm), II(TM.getInstrInfo()), MCE(mce) {} + Emitter(MachineCodeEmitter &mce) : II(0), MCE(mce) {} - bool runOnFunction(Function &F); + bool runOnMachineFunction(MachineFunction &MF); virtual const char *getPassName() const { return "X86 Machine Code Emitter"; @@ -52,12 +50,12 @@ /// bool X86TargetMachine::addPassesToEmitMachineCode(PassManager &PM, MachineCodeEmitter &MCE) { - PM.add(new Emitter(*this, MCE)); + PM.add(new Emitter(MCE)); return false; } -bool Emitter::runOnFunction(Function &F) { - MachineFunction &MF = MachineFunction::get(&F); +bool Emitter::runOnMachineFunction(MachineFunction &MF) { + II = &((X86TargetMachine&)MF.getTarget()).getInstrInfo(); MCE.startFunction(MF); for (MachineFunction::iterator I = MF.begin(), E = MF.end(); I != E; ++I) @@ -190,7 +188,11 @@ emitSIBByte(SS, getX86RegNum(IndexReg.getReg()), 5); } else { unsigned BaseRegNo = getX86RegNum(BaseReg.getReg()); - unsigned IndexRegNo = getX86RegNum(IndexReg.getReg()); + unsigned IndexRegNo; + if (IndexReg.getReg()) + IndexRegNo = getX86RegNum(IndexReg.getReg()); + else + IndexRegNo = 4; // For example [ESP+1*+4] emitSIBByte(SS, IndexRegNo, BaseRegNo); } @@ -220,7 +222,7 @@ void Emitter::emitInstruction(MachineInstr &MI) { unsigned Opcode = MI.getOpcode(); - const MachineInstrDescriptor &Desc = II.get(Opcode); + const MachineInstrDescriptor &Desc = II->get(Opcode); // Emit instruction prefixes if neccesary if (Desc.TSFlags & X86II::OpSize) MCE.emitByte(0x66);// Operand size... @@ -237,7 +239,7 @@ default: break; // No prefix! } - unsigned char BaseOpcode = II.getBaseOpcodeFor(Opcode); + unsigned char BaseOpcode = II->getBaseOpcodeFor(Opcode); switch (Desc.TSFlags & X86II::FormMask) { default: assert(0 && "Unknown FormMask value!"); case X86II::Pseudo: From lattner at cs.uiuc.edu Sat Dec 28 14:30:01 2002 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Sat Dec 28 14:30:01 2002 Subject: [llvm-commits] CVS: llvm/lib/Target/X86/X86InstrInfo.h Message-ID: <200212282029.OAA11413@apoc.cs.uiuc.edu> Changes in directory llvm/lib/Target/X86: X86InstrInfo.h updated: 1.18 -> 1.19 --- Log message: * Remove implementations of previously pure virtual functions that are not any longer. --- Diffs of the changes: Index: llvm/lib/Target/X86/X86InstrInfo.h diff -u llvm/lib/Target/X86/X86InstrInfo.h:1.18 llvm/lib/Target/X86/X86InstrInfo.h:1.19 --- llvm/lib/Target/X86/X86InstrInfo.h:1.18 Tue Dec 24 23:09:59 2002 +++ llvm/lib/Target/X86/X86InstrInfo.h Sat Dec 28 14:29:41 2002 @@ -129,55 +129,6 @@ // specified opcode number. // unsigned char getBaseOpcodeFor(unsigned Opcode) const; - - - - //===--------------------------------------------------------------------===// - // - // These are stubs for pure virtual methods that should be factored out of - // MachineInstrInfo. We never call them, we don't want them, but we need - // stubs so that we can instatiate our class. - // - MachineOpCode getNOPOpCode() const { abort(); } - void CreateCodeToLoadConst(const TargetMachine& target, Function* F, - Value *V, Instruction *I, - std::vector& mvec, - MachineCodeForInstruction& mcfi) const { abort(); } - void CreateCodeToCopyIntToFloat(const TargetMachine& target, - Function* F, Value* val, Instruction* dest, - std::vector& mvec, - MachineCodeForInstruction& mcfi) const { - abort(); - } - void CreateCodeToCopyFloatToInt(const TargetMachine& target, Function* F, - Value* val, Instruction* dest, - std::vector& mvec, - MachineCodeForInstruction& mcfi)const { - abort(); - } - void CreateCopyInstructionsByType(const TargetMachine& target, - Function* F, Value* src, - Instruction* dest, - std::vector& mvec, - MachineCodeForInstruction& mcfi)const { - abort(); - } - - void CreateSignExtensionInstructions(const TargetMachine& target, - Function* F, Value* srcVal, - Value* destVal, unsigned numLowBits, - std::vector& mvec, - MachineCodeForInstruction& mcfi) const { - abort(); - } - - void CreateZeroExtensionInstructions(const TargetMachine& target, - Function* F, Value* srcVal, - Value* destVal, unsigned srcSizeInBits, - std::vector& mvec, - MachineCodeForInstruction& mcfi) const { - abort(); - } }; From lattner at cs.uiuc.edu Sat Dec 28 14:30:04 2002 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Sat Dec 28 14:30:04 2002 Subject: [llvm-commits] CVS: llvm/lib/Target/X86/X86InstrInfo.def Message-ID: <200212282029.OAA11419@apoc.cs.uiuc.edu> Changes in directory llvm/lib/Target/X86: X86InstrInfo.def updated: 1.46 -> 1.47 --- Log message: * Minor reformatting * Remove some size suffixes [bwl] * Add new ADJCALLSTACKDOWN & ADJCALLSTACKUP pseudo instrs * Call instructions are M_CALL not M_BRANCH! * Disable push and pop instructions * Add new ANDri32 instr --- Diffs of the changes: Index: llvm/lib/Target/X86/X86InstrInfo.def diff -u llvm/lib/Target/X86/X86InstrInfo.def:1.46 llvm/lib/Target/X86/X86InstrInfo.def:1.47 --- llvm/lib/Target/X86/X86InstrInfo.def:1.46 Tue Dec 24 23:11:46 2002 +++ llvm/lib/Target/X86/X86InstrInfo.def Sat Dec 28 14:29:14 2002 @@ -56,88 +56,103 @@ I(PHI , "phi", 0, 0, X86II::Pseudo , NoIR, NoIR) // The second instruction must always be the noop instruction: -I(NOOP , "nop", 0x90, 0, X86II::RawFrm | X86II::Void, NoIR, NoIR) // nop +I(NOOP , "nop", 0x90, 0, X86II::RawFrm | X86II::Void, NoIR, NoIR) // nop + +// This "instruction" is really an annotation which indicates that a specified +// amount of stack space is needed for an outgoing function call. This +// instruction is found before any of the stores to the argument slots, which +// use direct ESP references. If the frame pointer is eliminated, this +// instruction turns into a noop, but if the frame pointer is retained, this +// turns into a 'sub ESP, '. +// +I(ADJCALLSTACKDOWN, "adjcallstackdown", 0, 0, X86II::Pseudo, NoIR, NoIR) + +// This instruction is used to mark readjustment of the stack after a function +// call. If the frame pointer is retained, this becomes a 'add ESP, ' +// instruction after the call. +I(ADJCALLSTACKUP , "adjcallstackup" , 0, 0, X86II::Pseudo, NoIR, NoIR) // Flow control instructions -I(RET , "ret", 0xC3, M_RET_FLAG, X86II::RawFrm | X86II::Void, NoIR, NoIR) // ret -I(JMP , "jmp", 0xE9, M_BRANCH_FLAG, X86II::RawFrm | X86II::Void, NoIR, NoIR) // jmp foo -I(JNE , "jne", 0x85, M_BRANCH_FLAG, X86II::RawFrm | X86II::TB | X86II::Void, NoIR, - NoIR) // jne foo -I(JE , "je", 0x84, M_BRANCH_FLAG, X86II::RawFrm | X86II::TB | X86II::Void, NoIR, - NoIR) // je foo -I(CALLpcrel32 , "call", 0xE8, M_BRANCH_FLAG, X86II::Void | X86II::RawFrm, NoIR, C_CLOBBER) // call pc+42 -I(CALLr32 , "call", 0xFF, M_BRANCH_FLAG, X86II::Void | X86II::MRMS2r | X86II::Arg32, - NoIR, C_CLOBBER) // call [r32] -I(CALLm32 , "call", 0xFF, M_BRANCH_FLAG, X86II::Void | X86II::MRMS2m | X86II::Arg32, - NoIR, C_CLOBBER) // call [m32] +I(RET , "ret", 0xC3, M_RET_FLAG, X86II::RawFrm | X86II::Void, NoIR, NoIR) // ret +I(JMP , "jmp", 0xE9, M_BRANCH_FLAG, X86II::RawFrm | X86II::Void, NoIR, NoIR) // jmp foo +I(JNE , "jne", 0x85, M_BRANCH_FLAG, X86II::RawFrm | X86II::TB | X86II::Void, NoIR, NoIR) // jne foo +I(JE , "je", 0x84, M_BRANCH_FLAG, X86II::RawFrm | X86II::TB | X86II::Void, NoIR, NoIR) // je foo +I(CALLpcrel32 , "call", 0xE8, M_CALL_FLAG, X86II::Void | X86II::RawFrm, NoIR, C_CLOBBER) // call pc+42 +I(CALLr32 , "call", 0xFF, M_CALL_FLAG, X86II::Void | X86II::MRMS2r | X86II::Arg32, + NoIR, C_CLOBBER) // call [r32] +I(CALLm32 , "call", 0xFF, M_CALL_FLAG, X86II::Void | X86II::MRMS2m | X86II::Arg32, + NoIR, C_CLOBBER) // call [m32] // Misc instructions -I(LEAVE , "leave", 0xC9, 0, X86II::RawFrm, O_EBP, O_EBP) // leave -I(BSWAPr32 , "bswap", 0xC8, M_2_ADDR_FLAG, X86II::AddRegFrm | X86II::TB | - X86II::Arg32, NoIR, NoIR) // R32 = bswap R32 -I(XCHGrr8 , "xchg" , 0x86, 0, X86II::MRMDestReg | X86II::Arg8, NoIR, NoIR) // xchg(R8, R8) +I(LEAVE , "leave", 0xC9, 0, X86II::RawFrm , O_EBP, O_EBP) // leave +I(BSWAPr32 , "bswap", 0xC8, M_2_ADDR_FLAG, X86II::AddRegFrm | X86II::Arg32 | X86II::TB , NoIR, NoIR) // R32 = bswap R32 +I(XCHGrr8 , "xchg" , 0x86, 0, X86II::MRMDestReg | X86II::Arg8 , NoIR, NoIR) // xchg(R8, R8) I(XCHGrr16 , "xchg" , 0x87, 0, X86II::MRMDestReg | X86II::Arg16 | X86II::OpSize, NoIR, NoIR) // xchg(R16, R16) -I(XCHGrr32 , "xchg" , 0x87, 0, X86II::MRMDestReg | X86II::Arg32, NoIR, NoIR) // xchg(R32, R32) +I(XCHGrr32 , "xchg" , 0x87, 0, X86II::MRMDestReg | X86II::Arg32 , NoIR, NoIR) // xchg(R32, R32) +I(LEAr16 , "lea" , 0x8D, 0, X86II::MRMSrcMem | X86II::Arg16 | X86II::OpSize, NoIR, NoIR) // R16 = lea [mem] +I(LEAr32 , "lea" , 0x8D, 0, X86II::MRMSrcMem | X86II::Arg32 , NoIR, NoIR) // R32 = lea [mem] + // Move instructions -I(MOVrr8 , "movb", 0x88, 0, X86II::MRMDestReg, NoIR, NoIR) // R8 = R8 -I(MOVrr16 , "movw", 0x89, 0, X86II::MRMDestReg | X86II::OpSize, NoIR, NoIR) // R16 = R16 -I(MOVrr32 , "movl", 0x89, 0, X86II::MRMDestReg, NoIR, NoIR) // R32 = R32 -I(MOVir8 , "movb", 0xB0, 0, X86II::AddRegFrm | X86II::Arg8, NoIR, NoIR) // R8 = imm8 -I(MOVir16 , "movw", 0xB8, 0, X86II::AddRegFrm | X86II::Arg16 | X86II::OpSize, NoIR, NoIR) // R16 = imm16 -I(MOVir32 , "movl", 0xB8, 0, X86II::AddRegFrm | X86II::Arg32, NoIR, NoIR) // R32 = imm32 -I(MOVmr8 , "movb", 0x8A, 0, X86II::MRMSrcMem | X86II::Arg8, NoIR, NoIR) // R8 = [mem] -I(MOVmr16 , "movw", 0x8B, 0, X86II::MRMSrcMem | X86II::OpSize | - X86II::Arg16, NoIR, NoIR) // R16 = [mem] -I(MOVmr32 , "movl", 0x8B, 0, X86II::MRMSrcMem | X86II::Arg32, NoIR, NoIR)// R32 = [mem] -I(MOVrm8 , "movb", 0x88, 0, X86II::MRMDestMem | X86II::Void | - X86II::Arg8, NoIR, NoIR) // [mem] = R8 -I(MOVrm16 , "movw", 0x89, 0, X86II::MRMDestMem | X86II::Void | - X86II::OpSize | X86II::Arg16, NoIR, NoIR) // [mem] = R16 -I(MOVrm32 , "movl", 0x89, 0, X86II::MRMDestMem | X86II::Void | - X86II::Arg32, NoIR, NoIR) // [mem] = R32 +I(MOVrr8 , "mov", 0x88, 0, X86II::MRMDestReg, NoIR, NoIR) // R8 = R8 +I(MOVrr16 , "mov", 0x89, 0, X86II::MRMDestReg | X86II::OpSize, NoIR, NoIR) // R16 = R16 +I(MOVrr32 , "mov", 0x89, 0, X86II::MRMDestReg, NoIR, NoIR) // R32 = R32 +I(MOVir8 , "mov", 0xB0, 0, X86II::AddRegFrm | X86II::Arg8, NoIR, NoIR) // R8 = imm8 +I(MOVir16 , "mov", 0xB8, 0, X86II::AddRegFrm | X86II::Arg16 | X86II::OpSize, NoIR, NoIR) // R16 = imm16 +I(MOVir32 , "mov", 0xB8, 0, X86II::AddRegFrm | X86II::Arg32, NoIR, NoIR) // R32 = imm32 +I(MOVmr8 , "mov", 0x8A, 0, X86II::MRMSrcMem | X86II::Arg8, NoIR, NoIR) // R8 = [mem] +I(MOVmr16 , "mov", 0x8B, 0, X86II::MRMSrcMem | X86II::OpSize | + X86II::Arg16, NoIR, NoIR) // R16 = [mem] +I(MOVmr32 , "mov", 0x8B, 0, X86II::MRMSrcMem | X86II::Arg32, NoIR, NoIR)// R32 = [mem] +I(MOVrm8 , "mov", 0x88, 0, X86II::MRMDestMem | X86II::Void | + X86II::Arg8, NoIR, NoIR) // [mem] = R8 +I(MOVrm16 , "mov", 0x89, 0, X86II::MRMDestMem | X86II::Void | + X86II::OpSize | X86II::Arg16, NoIR, NoIR) // [mem] = R16 +I(MOVrm32 , "mov", 0x89, 0, X86II::MRMDestMem | X86II::Void | + X86II::Arg32, NoIR, NoIR) // [mem] = R32 -I(PUSHr32 , "pushl", 0x50, 0, X86II::AddRegFrm | X86II::Void, NoIR, NoIR) -I(POPr32 , "popl", 0x58, 0, X86II::AddRegFrm, NoIR, NoIR) + //I(PUSHr32 , "pushl", 0x50, 0, X86II::AddRegFrm | X86II::Void, NoIR, NoIR) + //I(POPr32 , "popl", 0x58, 0, X86II::AddRegFrm, NoIR, NoIR) // Arithmetic instructions -I(ADDrr8 , "addb", 0x00, M_2_ADDR_FLAG, X86II::MRMDestReg, NoIR, NoIR) // R8 += R8 -I(ADDrr16 , "addw", 0x01, M_2_ADDR_FLAG, X86II::MRMDestReg | X86II::OpSize, NoIR, NoIR) // R16 += R16 -I(ADDrr32 , "addl", 0x01, M_2_ADDR_FLAG, X86II::MRMDestReg, NoIR, NoIR) // R32 += R32 -I(ADDri32 , "add", 0x81, M_2_ADDR_FLAG, X86II::MRMS0r | X86II::Arg32, NoIR, NoIR) // R32 += imm32 -I(SUBrr8 , "subb", 0x28, M_2_ADDR_FLAG, X86II::MRMDestReg, NoIR, NoIR) // R8 -= R8 -I(SUBrr16 , "subw", 0x29, M_2_ADDR_FLAG, X86II::MRMDestReg | X86II::OpSize, NoIR, NoIR) // R16 -= R16 -I(SUBrr32 , "subl", 0x29, M_2_ADDR_FLAG, X86II::MRMDestReg, NoIR, NoIR) // R32 -= R32 -I(SUBri32 , "sub", 0x81, M_2_ADDR_FLAG, X86II::MRMS5r | X86II::Arg32, NoIR, NoIR) // R32 -= imm32 -I(MULrr8 , "mulb", 0xF6, 0, X86II::MRMS4r | X86II::Void, O_AL, O_AX) // AX = AL*R8 -I(MULrr16 , "mulw", 0xF7, 0, X86II::MRMS4r | X86II::Void | // DX:AX= AX*R16 +I(ADDrr8 , "add", 0x00, M_2_ADDR_FLAG, X86II::MRMDestReg, NoIR, NoIR) // R8 += R8 +I(ADDrr16 , "add", 0x01, M_2_ADDR_FLAG, X86II::MRMDestReg | X86II::OpSize, NoIR, NoIR) // R16 += R16 +I(ADDrr32 , "add", 0x01, M_2_ADDR_FLAG, X86II::MRMDestReg, NoIR, NoIR) // R32 += R32 +I(ADDri32 , "add", 0x81, M_2_ADDR_FLAG, X86II::MRMS0r | X86II::Arg32, NoIR, NoIR) // R32 += imm32 +I(SUBrr8 , "sub", 0x28, M_2_ADDR_FLAG, X86II::MRMDestReg, NoIR, NoIR) // R8 -= R8 +I(SUBrr16 , "sub", 0x29, M_2_ADDR_FLAG, X86II::MRMDestReg | X86II::OpSize, NoIR, NoIR) // R16 -= R16 +I(SUBrr32 , "sub", 0x29, M_2_ADDR_FLAG, X86II::MRMDestReg, NoIR, NoIR) // R32 -= R32 +I(SUBri32 , "sub", 0x81, M_2_ADDR_FLAG, X86II::MRMS5r | X86II::Arg32, NoIR, NoIR) // R32 -= imm32 +I(MULrr8 , "mul", 0xF6, 0, X86II::MRMS4r | X86II::Void, O_AL, O_AX) // AX = AL*R8 +I(MULrr16 , "mul", 0xF7, 0, X86II::MRMS4r | X86II::Void | // DX:AX= AX*R16 X86II::OpSize, O_AX, T_AXDX) -I(MULrr32 , "mull", 0xF7, 0, X86II::MRMS4r | X86II::Void, O_EAX, T_EAXEDX) // ED:EA= EA*R32 +I(MULrr32 , "mul", 0xF7, 0, X86II::MRMS4r | X86II::Void, O_EAX, T_EAXEDX) // ED:EA= EA*R32 // unsigned division/remainder -I(DIVrr8 , "divb", 0xF6, 0, X86II::MRMS6r | X86II::Void, O_AX, O_AX) // AX/r8= AL&AH -I(DIVrr16 , "divw", 0xF7, 0, X86II::MRMS6r | X86II::Void | // ED:EA/r16=AX&DX +I(DIVrr8 , "div", 0xF6, 0, X86II::MRMS6r | X86II::Void, O_AX, O_AX) // AX/r8= AL&AH +I(DIVrr16 , "div", 0xF7, 0, X86II::MRMS6r | X86II::Void | // ED:EA/r16=AX&DX X86II::OpSize, T_AXDX, T_AXDX) -I(DIVrr32 , "divl", 0xF7, 0, X86II::MRMS6r | X86II::Void, T_EAXEDX, +I(DIVrr32 , "div", 0xF7, 0, X86II::MRMS6r | X86II::Void, T_EAXEDX, T_EAXEDX) // ED:EA/r32=EA&ED // signed division/remainder -I(IDIVrr8 , "idivb", 0xF6, 0, X86II::MRMS7r | X86II::Void, O_AX, O_AX) // AX/r8= AL&AH -I(IDIVrr16 , "idivw", 0xF7, 0, X86II::MRMS7r | X86II::Void | // DA/r16=AX&DX +I(IDIVrr8 , "idiv", 0xF6, 0, X86II::MRMS7r | X86II::Void, O_AX, O_AX) // AX/r8= AL&AH +I(IDIVrr16 , "idiv", 0xF7, 0, X86II::MRMS7r | X86II::Void | // DA/r16=AX&DX X86II::OpSize, T_AXDX, T_AXDX) -I(IDIVrr32 , "idivl", 0xF7, 0, X86II::MRMS7r | X86II::Void, T_EAXEDX, +I(IDIVrr32 , "idiv", 0xF7, 0, X86II::MRMS7r | X86II::Void, T_EAXEDX, T_EAXEDX) // DA/r32=EAX&DX // Logical operators -I(ANDrr8 , "andb", 0x20, M_2_ADDR_FLAG, X86II::MRMDestReg, NoIR, NoIR) // R8 &= R8 -I(ANDrr16 , "andw", 0x21, M_2_ADDR_FLAG, X86II::MRMDestReg | X86II::OpSize, NoIR, NoIR) // R16 &= R16 -I(ANDrr32 , "andl", 0x21, M_2_ADDR_FLAG, X86II::MRMDestReg, NoIR, NoIR) // R32 &= R32 -I(ORrr8 , "orb", 0x08, M_2_ADDR_FLAG, X86II::MRMDestReg, NoIR, NoIR) // R8 |= R8 -I(ORrr16 , "orw", 0x09, M_2_ADDR_FLAG, X86II::MRMDestReg | X86II::OpSize, NoIR, NoIR) // R16 |= R16 -I(ORrr32 , "orl", 0x09, M_2_ADDR_FLAG, X86II::MRMDestReg, NoIR, NoIR) // R32 |= R32 -I(XORrr8 , "xorb", 0x30, M_2_ADDR_FLAG, X86II::MRMDestReg, NoIR, NoIR) // R8 ^= R8 -I(XORrr16 , "xorw", 0x31, M_2_ADDR_FLAG, X86II::MRMDestReg | X86II::OpSize, NoIR, NoIR) // R16 ^= R16 -I(XORrr32 , "xorl", 0x31, M_2_ADDR_FLAG, X86II::MRMDestReg, NoIR, NoIR) // R32 ^= R32 +I(ANDrr8 , "and", 0x20, M_2_ADDR_FLAG, X86II::MRMDestReg, NoIR, NoIR) // R8 &= R8 +I(ANDrr16 , "and", 0x21, M_2_ADDR_FLAG, X86II::MRMDestReg | X86II::OpSize, NoIR, NoIR) // R16 &= R16 +I(ANDrr32 , "and", 0x21, M_2_ADDR_FLAG, X86II::MRMDestReg, NoIR, NoIR) // R32 &= R32 +I(ANDri32 , "and", 0x81, M_2_ADDR_FLAG, X86II::MRMS4r | X86II::Arg32, NoIR, NoIR) // R32 &= imm32 +I(ORrr8 , "or", 0x08, M_2_ADDR_FLAG, X86II::MRMDestReg, NoIR, NoIR) // R8 |= R8 +I(ORrr16 , "or", 0x09, M_2_ADDR_FLAG, X86II::MRMDestReg | X86II::OpSize, NoIR, NoIR) // R16 |= R16 +I(ORrr32 , "or", 0x09, M_2_ADDR_FLAG, X86II::MRMDestReg, NoIR, NoIR) // R32 |= R32 +I(XORrr8 , "xor", 0x30, M_2_ADDR_FLAG, X86II::MRMDestReg, NoIR, NoIR) // R8 ^= R8 +I(XORrr16 , "xor", 0x31, M_2_ADDR_FLAG, X86II::MRMDestReg | X86II::OpSize, NoIR, NoIR) // R16 ^= R16 +I(XORrr32 , "xor", 0x31, M_2_ADDR_FLAG, X86II::MRMDestReg, NoIR, NoIR) // R32 ^= R32 // Shift instructions I(SHLrr8 , "shlb", 0xD2, M_2_ADDR_FLAG, X86II::MRMS4r, O_CL, NoIR) // R8 <<= cl @@ -176,7 +191,7 @@ I(CMPrr8 , "cmpb", 0x38, 0, X86II::MRMDestReg, NoIR, NoIR) // compare R8,R8 I(CMPrr16 , "cmpw", 0x39, 0, X86II::MRMDestReg | X86II::OpSize, NoIR, NoIR) // compare R16,R16 I(CMPrr32 , "cmpl", 0x39, 0, X86II::MRMDestReg, NoIR, NoIR) // compare R32,R32 -I(CMPri8 , "cmp", 0x80, 0, X86II::MRMS7r | X86II::Arg8, NoIR, NoIR) // compare R8, imm8 +I(CMPri8 , "cmp", 0x80, 0, X86II::MRMS7r | X86II::Arg8, NoIR, NoIR) // compare R8, imm8 // Sign extenders (first 3 are good for DIV/IDIV; the others are more general) I(CBW , "cbw", 0x98, 0, X86II::RawFrm | X86II::OpSize, O_AL, O_AH) // AX = signext(AL) From lattner at cs.uiuc.edu Sat Dec 28 14:30:08 2002 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Sat Dec 28 14:30:08 2002 Subject: [llvm-commits] CVS: llvm/lib/Target/X86/X86.h Message-ID: <200212282029.OAA11424@apoc.cs.uiuc.edu> Changes in directory llvm/lib/Target/X86: X86.h updated: 1.10 -> 1.11 --- Log message: * Most pass ctor functions don't take TM arguments anymore * New createPrologEpilogCodeInserter() function --- Diffs of the changes: Index: llvm/lib/Target/X86/X86.h diff -u llvm/lib/Target/X86/X86.h:1.10 llvm/lib/Target/X86/X86.h:1.11 --- llvm/lib/Target/X86/X86.h:1.10 Mon Dec 16 10:14:51 2002 +++ llvm/lib/Target/X86/X86.h Sat Dec 28 14:26:16 2002 @@ -20,24 +20,29 @@ /// Pass *createSimpleX86InstructionSelector(TargetMachine &TM); -/// createSimpleRegisterAllocation - This function converts the specified -/// machine code function from SSA form to use explicit registers by spilling -/// every register. Wow, great policy huh? +/// createSimpleRegisterAllocation - This function returns a pass that converts +/// the specified machine code function from SSA form to use explicit registers +/// by spilling every register. Wow, great policy huh? /// -Pass *createSimpleRegisterAllocator(TargetMachine &TM); -Pass *createLocalRegisterAllocator(TargetMachine &TM); +Pass *createSimpleRegisterAllocator(); +Pass *createLocalRegisterAllocator(); + +/// createPrologEpilogCodeInserter - This function returns a pass that inserts +/// prolog and epilog code, and eliminates abstract frame references. +/// +Pass *createPrologEpilogCodeInserter(); /// createX86CodePrinterPass - Print out the specified machine code function to /// the specified stream. This function should work regardless of whether or /// not the function is in SSA form or not. /// -Pass *createX86CodePrinterPass(TargetMachine &TM, std::ostream &O); +Pass *createX86CodePrinterPass(std::ostream &O); /// X86EmitCodeToMemory - This function converts a register allocated function /// into raw machine code in a dynamically allocated chunk of memory. A pointer /// to the start of the function is returned. /// -Pass *createEmitX86CodeToMemory(TargetMachine &TM); +Pass *createEmitX86CodeToMemory(); // Put symbolic names in a namespace to avoid causing these to clash with all // kinds of other things... From lattner at cs.uiuc.edu Sat Dec 28 14:31:01 2002 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Sat Dec 28 14:31:01 2002 Subject: [llvm-commits] CVS: llvm/lib/Target/X86/X86RegisterClasses.cpp Message-ID: <200212282030.OAA11440@apoc.cs.uiuc.edu> Changes in directory llvm/lib/Target/X86: X86RegisterClasses.cpp (r1.9) removed --- Log message: Contents merged with X86RegisterInfo.cpp --- Diffs of the changes: From lattner at cs.uiuc.edu Sat Dec 28 14:34:00 2002 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Sat Dec 28 14:34:00 2002 Subject: [llvm-commits] CVS: llvm/lib/Target/X86/X86RegisterInfo.h Message-ID: <200212282033.OAA11469@apoc.cs.uiuc.edu> Changes in directory llvm/lib/Target/X86: X86RegisterInfo.h updated: 1.12 -> 1.13 --- Log message: Changes to match new MRegisterInfo api --- Diffs of the changes: Index: llvm/lib/Target/X86/X86RegisterInfo.h diff -u llvm/lib/Target/X86/X86RegisterInfo.h:1.12 llvm/lib/Target/X86/X86RegisterInfo.h:1.13 --- llvm/lib/Target/X86/X86RegisterInfo.h:1.12 Tue Dec 24 23:06:43 2002 +++ llvm/lib/Target/X86/X86RegisterInfo.h Sat Dec 28 14:32:54 2002 @@ -1,4 +1,4 @@ -//===- X86RegisterInfo.h - X86 Register Information Impl ----------*-C++-*-===// +//===- X86RegisterInfo.h - X86 Register Information Impl --------*- C++ -*-===// // // This file contains the X86 implementation of the MRegisterInfo class. // @@ -14,38 +14,39 @@ struct X86RegisterInfo : public MRegisterInfo { X86RegisterInfo(); - void storeReg2RegOffset(MachineBasicBlock &MBB, - MachineBasicBlock::iterator &MBBI, - unsigned SrcReg, unsigned DestReg, unsigned ImmOffset, - const TargetRegisterClass *RC) const; - - void loadRegOffset2Reg(MachineBasicBlock &MBB, - MachineBasicBlock::iterator &MBBI, - unsigned DestReg, unsigned SrcReg, unsigned ImmOffset, - const TargetRegisterClass *RC) const; + const unsigned* getCalleeSaveRegs() const; - void moveReg2Reg(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI, - unsigned DestReg, unsigned SrcReg, - const TargetRegisterClass *RC) const; + /// Returns register class appropriate for input SSA register + /// + const TargetRegisterClass *getClassForReg(unsigned Reg) const; + const TargetRegisterClass* getRegClassForType(const Type* Ty) const; - void moveImm2Reg(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI, - unsigned DestReg, unsigned Imm, + /// Code Generation virtual methods... + void storeRegToStackSlot(MachineBasicBlock &MBB, + MachineBasicBlock::iterator &MBBI, + unsigned SrcReg, int FrameIndex, + const TargetRegisterClass *RC) const; + + void loadRegFromStackSlot(MachineBasicBlock &MBB, + MachineBasicBlock::iterator &MBBI, + unsigned DestReg, int FrameIndex, + const TargetRegisterClass *RC) const; + + void copyRegToReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI, + unsigned DestReg, unsigned SrcReg, const TargetRegisterClass *RC) const; - unsigned getFramePointer() const; - unsigned getStackPointer() const; + void eliminateCallFramePseudoInstr(MachineFunction &MF, + MachineBasicBlock &MBB, + MachineBasicBlock::iterator &I) const; - const unsigned* getCalleeSaveRegs() const; - const unsigned* getCallerSaveRegs() const; + void eliminateFrameIndex(MachineFunction &MF, + MachineBasicBlock::iterator &II) const; - void emitPrologue(MachineFunction &MF, unsigned numBytes) const; - void emitEpilogue(MachineBasicBlock &MBB, unsigned numBytes) const; + void processFunctionBeforeFrameFinalized(MachineFunction &MF) const; - /// Returns register class appropriate for input SSA register - /// - const TargetRegisterClass *getClassForReg(unsigned Reg) const; - - const TargetRegisterClass* getRegClassForType(const Type* Ty) const; + void emitPrologue(MachineFunction &MF) const; + void emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const; }; #endif From lattner at cs.uiuc.edu Sat Dec 28 14:35:01 2002 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Sat Dec 28 14:35:01 2002 Subject: [llvm-commits] CVS: llvm/lib/Target/X86/X86InstrBuilder.h Message-ID: <200212282034.OAA11492@apoc.cs.uiuc.edu> Changes in directory llvm/lib/Target/X86: X86InstrBuilder.h updated: 1.3 -> 1.4 --- Log message: New addFrameReference function --- Diffs of the changes: Index: llvm/lib/Target/X86/X86InstrBuilder.h diff -u llvm/lib/Target/X86/X86InstrBuilder.h:1.3 llvm/lib/Target/X86/X86InstrBuilder.h:1.4 --- llvm/lib/Target/X86/X86InstrBuilder.h:1.3 Fri Dec 13 03:28:50 2002 +++ llvm/lib/Target/X86/X86InstrBuilder.h Sat Dec 28 14:26:58 2002 @@ -20,8 +20,9 @@ #include "llvm/CodeGen/MachineInstrBuilder.h" /// addDirectMem - This function is used to add a direct memory reference to the -/// current instruction -- that is, a dereference of an address in a register, with -/// no scale, index or displacement. An example is: DWORD PTR [EAX]. +/// current instruction -- that is, a dereference of an address in a register, +/// with no scale, index or displacement. An example is: DWORD PTR [EAX]. +/// inline const MachineInstrBuilder &addDirectMem(const MachineInstrBuilder &MIB, unsigned Reg) { // Because memory references are always represented with four @@ -30,12 +31,23 @@ } -/// addRegOffset - This function is used to add a memory reference of -/// the form [Reg + Offset], i.e., one with no scale or index, but -/// with a displacement. An example is: DWORD PTR [EAX + 4]. +/// addRegOffset - This function is used to add a memory reference of the form +/// [Reg + Offset], i.e., one with no scale or index, but with a +/// displacement. An example is: DWORD PTR [EAX + 4]. +/// inline const MachineInstrBuilder &addRegOffset(const MachineInstrBuilder &MIB, - unsigned Reg, unsigned Offset) { + unsigned Reg, int Offset) { return MIB.addReg(Reg).addZImm(1).addMReg(0).addSImm(Offset); +} + +/// addFrameReference - This function is used to add a reference to the base of +/// an abstract object on the stack frame of the current function. This +/// reference has base register and a FrameIndex offset until it is +/// resolved. +/// +inline const MachineInstrBuilder & +addFrameReference(const MachineInstrBuilder &MIB, int FI) { + return MIB.addReg(0).addZImm(1).addMReg(0).addFrameIndex(FI); } #endif From lattner at cs.uiuc.edu Sat Dec 28 14:35:04 2002 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Sat Dec 28 14:35:04 2002 Subject: [llvm-commits] CVS: llvm/lib/Target/X86/X86TargetMachine.h Message-ID: <200212282034.OAA11485@apoc.cs.uiuc.edu> Changes in directory llvm/lib/Target/X86: X86TargetMachine.h updated: 1.5 -> 1.6 --- Log message: Implement the TargetFrameInfo interface --- Diffs of the changes: Index: llvm/lib/Target/X86/X86TargetMachine.h diff -u llvm/lib/Target/X86/X86TargetMachine.h:1.5 llvm/lib/Target/X86/X86TargetMachine.h:1.6 --- llvm/lib/Target/X86/X86TargetMachine.h:1.5 Mon Dec 23 18:04:01 2002 +++ llvm/lib/Target/X86/X86TargetMachine.h Sat Dec 28 14:33:52 2002 @@ -9,21 +9,24 @@ #include "llvm/Target/TargetMachine.h" #include "X86InstrInfo.h" +#include "llvm/Target/MachineFrameInfo.h" class X86TargetMachine : public TargetMachine { - X86InstrInfo instrInfo; + X86InstrInfo InstrInfo; + TargetFrameInfo FrameInfo; public: X86TargetMachine(unsigned Configuration); - virtual const X86InstrInfo &getInstrInfo() const { return instrInfo; } + virtual const X86InstrInfo &getInstrInfo() const { return InstrInfo; } + virtual const TargetFrameInfo &getFrameInfo() const { return FrameInfo; } + virtual const MRegisterInfo *getRegisterInfo() const { + return &InstrInfo.getRegisterInfo(); + } + virtual const MachineSchedInfo &getSchedInfo() const { abort(); } virtual const MachineRegInfo &getRegInfo() const { abort(); } - virtual const MachineFrameInfo &getFrameInfo() const { abort(); } virtual const MachineCacheInfo &getCacheInfo() const { abort(); } virtual const MachineOptInfo &getOptInfo() const { abort(); } - virtual const MRegisterInfo *getRegisterInfo() const { - return &instrInfo.getRegisterInfo(); - } /// addPassesToJITCompile - Add passes to the specified pass manager to /// implement a fast dynamic compiler for this target. Return true if this is From lattner at cs.uiuc.edu Sat Dec 28 14:35:08 2002 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Sat Dec 28 14:35:08 2002 Subject: [llvm-commits] CVS: llvm/lib/Target/X86/X86RegisterInfo.cpp Message-ID: <200212282034.OAA11497@apoc.cs.uiuc.edu> Changes in directory llvm/lib/Target/X86: X86RegisterInfo.cpp updated: 1.25 -> 1.26 --- Log message: *** Implement frame pointer elimination on X86! * Include contents of X86RegisterClasses.cpp into here * Adjustments to register api to work with new frame manager * Eliminate moveImm2Reg, getFramePointer, and getStackPointer * Cleanup and simplify prolog/epilog code generation * Prolog/epilog are MUCH more efficient now. --- Diffs of the changes: Index: llvm/lib/Target/X86/X86RegisterInfo.cpp diff -u llvm/lib/Target/X86/X86RegisterInfo.cpp:1.25 llvm/lib/Target/X86/X86RegisterInfo.cpp:1.26 --- llvm/lib/Target/X86/X86RegisterInfo.cpp:1.25 Tue Dec 24 23:07:09 2002 +++ llvm/lib/Target/X86/X86RegisterInfo.cpp Sat Dec 28 14:32:28 2002 @@ -1,6 +1,7 @@ //===- X86RegisterInfo.cpp - X86 Register Information -----------*- C++ -*-===// // -// This file contains the X86 implementation of the MRegisterInfo class. +// This file contains the X86 implementation of the MRegisterInfo class. This +// file is responsible for the frame pointer elimination optimization on X86. // //===----------------------------------------------------------------------===// @@ -11,9 +12,17 @@ #include "llvm/Type.h" #include "llvm/CodeGen/MachineInstrBuilder.h" #include "llvm/CodeGen/MachineFunction.h" +#include "llvm/CodeGen/FunctionFrameInfo.h" +#include "Support/CommandLine.h" + +namespace { + cl::opt + NoFPElim("no-fp-elim", + cl::desc("Disable frame pointer elimination optimization")); +} static unsigned getIdx(const TargetRegisterClass *RC) { - switch (RC->getDataSize()) { + switch (RC->getSize()) { default: assert(0 && "Invalid data size!"); case 1: return 0; case 2: return 1; @@ -22,99 +31,321 @@ } } -void X86RegisterInfo::storeReg2RegOffset(MachineBasicBlock &MBB, - MachineBasicBlock::iterator &MBBI, - unsigned SrcReg, unsigned DestReg, - unsigned ImmOffset, - const TargetRegisterClass *RC) const { +void X86RegisterInfo::storeRegToStackSlot(MachineBasicBlock &MBB, + MachineBasicBlock::iterator &MBBI, + unsigned SrcReg, int FrameIdx, + const TargetRegisterClass *RC) const { static const unsigned Opcode[] = { X86::MOVrm8, X86::MOVrm16, X86::MOVrm32, X86::FSTPr80 }; - MachineInstr *MI = addRegOffset(BuildMI(Opcode[getIdx(RC)], 5), - DestReg, ImmOffset).addReg(SrcReg); + MachineInstr *MI = addFrameReference(BuildMI(Opcode[getIdx(RC)], 5), + FrameIdx).addReg(SrcReg); MBBI = MBB.insert(MBBI, MI)+1; } -void X86RegisterInfo::loadRegOffset2Reg(MachineBasicBlock &MBB, - MachineBasicBlock::iterator &MBBI, - unsigned DestReg, unsigned SrcReg, - unsigned ImmOffset, - const TargetRegisterClass *RC) const { +void X86RegisterInfo::loadRegFromStackSlot(MachineBasicBlock &MBB, + MachineBasicBlock::iterator &MBBI, + unsigned DestReg, int FrameIdx, + const TargetRegisterClass *RC) const{ static const unsigned Opcode[] = { X86::MOVmr8, X86::MOVmr16, X86::MOVmr32, X86::FLDr80 }; - MachineInstr *MI = addRegOffset(BuildMI(Opcode[getIdx(RC)], 4, DestReg), - SrcReg, ImmOffset); + MachineInstr *MI = addFrameReference(BuildMI(Opcode[getIdx(RC)], 4, DestReg), + FrameIdx); MBBI = MBB.insert(MBBI, MI)+1; } -void X86RegisterInfo::moveReg2Reg(MachineBasicBlock &MBB, - MachineBasicBlock::iterator &MBBI, - unsigned DestReg, unsigned SrcReg, - const TargetRegisterClass *RC) const { +void X86RegisterInfo::copyRegToReg(MachineBasicBlock &MBB, + MachineBasicBlock::iterator &MBBI, + unsigned DestReg, unsigned SrcReg, + const TargetRegisterClass *RC) const { static const unsigned Opcode[] = { X86::MOVrr8, X86::MOVrr16, X86::MOVrr32, X86::FpMOV }; MachineInstr *MI = BuildMI(Opcode[getIdx(RC)],1,DestReg).addReg(SrcReg); MBBI = MBB.insert(MBBI, MI)+1; } -void X86RegisterInfo::moveImm2Reg(MachineBasicBlock &MBB, - MachineBasicBlock::iterator &MBBI, - unsigned DestReg, unsigned Imm, - const TargetRegisterClass *RC) const { - static const unsigned Opcode[] = - { X86::MOVir8, X86::MOVir16, X86::MOVir32, 0 }; - MachineInstr *MI = BuildMI(Opcode[getIdx(RC)], 1, DestReg).addReg(Imm); - assert(MI->getOpcode() != 0 && "Cannot move FP imm to reg yet!"); - MBBI = MBB.insert(MBBI, MI)+1; +const unsigned* X86RegisterInfo::getCalleeSaveRegs() const { + static const unsigned CalleeSaveRegs[] = { + X86::ESI, X86::EDI, X86::EBX, X86::EBP, 0 + }; + return CalleeSaveRegs; } -unsigned X86RegisterInfo::getFramePointer() const { - return X86::EBP; +//===----------------------------------------------------------------------===// +// Stack Frame Processing methods +//===----------------------------------------------------------------------===// + +// hasFP - Return true if the specified function should have a dedicated frame +// pointer register. This is true if the function has variable sized allocas or +// if frame pointer elimination is disabled. +// +static bool hasFP(MachineFunction &MF) { + return NoFPElim || MF.getFrameInfo()->hasVarSizedObjects(); } -unsigned X86RegisterInfo::getStackPointer() const { - return X86::ESP; +// hasSPAdjust - Return true if this function has ESP adjustment instructions in +// the prolog and epilog which allocate local stack space. This is neccesary +// because we elide these instructions if there are no function calls in the +// current function (ie, this is a leaf function). In this case, we can refer +// beyond the stack pointer because we know that nothing will trample on that +// part of the stack. +// +static bool hasSPAdjust(MachineFunction &MF) { + assert(!hasFP(MF) && "Can only eliminate SP adjustment if no frame-pointer!"); + return MF.getFrameInfo()->hasCalls(); } -const unsigned* X86RegisterInfo::getCalleeSaveRegs() const { - static const unsigned CalleeSaveRegs[] = { X86::ESI, X86::EDI, X86::EBX, 0 }; - return CalleeSaveRegs; +void X86RegisterInfo::eliminateCallFramePseudoInstr(MachineFunction &MF, + MachineBasicBlock &MBB, + MachineBasicBlock::iterator &I) const { + MachineInstr *New = 0, *Old = *I;; + if (hasFP(MF)) { + // If we have a frame pointer, turn the adjcallstackup instruction into a + // 'sub ESP, ' and the adjcallstackdown instruction into 'add ESP, + // ' + unsigned Amount = Old->getOperand(0).getImmedValue(); + if (Amount != 0) { + if (Old->getOpcode() == X86::ADJCALLSTACKDOWN) { + New=BuildMI(X86::SUBri32, 2, X86::ESP).addReg(X86::ESP).addZImm(Amount); + } else { + assert(Old->getOpcode() == X86::ADJCALLSTACKUP); + New=BuildMI(X86::ADDri32, 2, X86::ESP).addReg(X86::ESP).addZImm(Amount); + } + } + } + + if (New) + *I = New; // Replace the pseudo instruction with a new instruction... + else + I = MBB.erase(I);// Just delete the pseudo instruction... + delete Old; } +void X86RegisterInfo::eliminateFrameIndex(MachineFunction &MF, + MachineBasicBlock::iterator &II) const { + unsigned i = 3; + MachineInstr &MI = **II; + while (!MI.getOperand(i).isFrameIndex()) { + ++i; + assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!"); + } -const unsigned* X86RegisterInfo::getCallerSaveRegs() const { - static const unsigned CallerSaveRegs[] = { X86::EAX, X86::ECX, X86::EDX, 0 }; - return CallerSaveRegs; + // This must be part of a four operand memory reference. Replace the + // FrameIndex with the offset and the base register with EBP. + MI.SetMachineOperandReg(i-3, hasFP(MF) ? X86::EBP : X86::ESP); + + // Now replace the frame index itself with the offset from EBP. + int FrameIndex = MI.getOperand(i).getFrameIndex(); + int Offset = MF.getFrameInfo()->getObjectOffset(FrameIndex); + + if (!hasFP(MF) && hasSPAdjust(MF)) { + const FunctionFrameInfo *FFI = MF.getFrameInfo(); + Offset += FFI->getStackSize() + FFI->getMaxCallFrameSize(); + } + + MI.SetMachineOperandConst(i, MachineOperand::MO_SignExtendedImmed, Offset); +} + +void X86RegisterInfo::processFunctionBeforeFrameFinalized(MachineFunction &MF) + const { + if (hasFP(MF)) { + // Create a frame entry for the EBP register that must be saved. + int FrameIdx = MF.getFrameInfo()->CreateStackObject(4, 4); + assert(FrameIdx == MF.getFrameInfo()->getObjectIndexEnd()-1 && + "Slot for EBP register must be last in order to be found!"); + } } -void X86RegisterInfo::emitPrologue(MachineFunction &MF, - unsigned NumBytes) const { +void X86RegisterInfo::emitPrologue(MachineFunction &MF) const { MachineBasicBlock &MBB = MF.front(); // Prolog goes in entry BB MachineBasicBlock::iterator MBBI = MBB.begin(); + const FunctionFrameInfo *FFI = MF.getFrameInfo(); + MachineInstr *MI; - // Round stack allocation up to a nice alignment to keep the stack aligned - NumBytes = (NumBytes + 3) & ~3; - - // PUSH ebp - MachineInstr *MI = BuildMI(X86::PUSHr32, 1).addReg(X86::EBP); - MBBI = MBB.insert(MBBI, MI)+1; - - // MOV ebp, esp - MI = BuildMI(X86::MOVrr32, 1, X86::EBP).addReg(X86::ESP); - MBBI = MBB.insert(MBBI, MI)+1; + // Get the number of bytes to allocate from the FrameInfo + unsigned NumBytes = FFI->getStackSize(); + if (hasFP(MF)) { + // Get the offset of the stack slot for the EBP register... which is + // guaranteed to be the last slot by processFunctionBeforeFrameFinalized. + int EBPOffset = FFI->getObjectOffset(FFI->getObjectIndexEnd()-1); + + MI = addRegOffset(BuildMI(X86::MOVrm32, 5), // mov [ESP-], EBP + X86::ESP, EBPOffset).addReg(X86::EBP); + MBBI = MBB.insert(MBBI, MI)+1; + + MI = BuildMI(X86::MOVrr32, 2, X86::EBP).addReg(X86::ESP); + MBBI = MBB.insert(MBBI, MI)+1; + } else { + // If we don't have a frame pointer, and the function contains no call sites + // (it's a leaf function), we don't have to emit ANY stack adjustment + // instructions at all, we can just refer to the area beyond the stack + // pointer. This can be important for small functions. + // + if (!hasSPAdjust(MF)) return; + + // When we have no frame pointer, we reserve argument space for call sites + // in the function immediately on entry to the current function. This + // eliminates the need for add/sub ESP brackets around call sites. + // + NumBytes += FFI->getMaxCallFrameSize(); + } - // adjust stack pointer: ESP -= numbytes - MI = BuildMI(X86::SUBri32, 2, X86::ESP).addReg(X86::ESP).addZImm(NumBytes); - MBBI = 1+MBB.insert(MBBI, MI); + if (NumBytes) { + // adjust stack pointer: ESP -= numbytes + MI = BuildMI(X86::SUBri32, 2, X86::ESP).addReg(X86::ESP).addZImm(NumBytes); + MBBI = 1+MBB.insert(MBBI, MI); + } } -void X86RegisterInfo::emitEpilogue(MachineBasicBlock &MBB, - unsigned numBytes) const { +void X86RegisterInfo::emitEpilogue(MachineFunction &MF, + MachineBasicBlock &MBB) const { + const FunctionFrameInfo *FFI = MF.getFrameInfo(); MachineBasicBlock::iterator MBBI = MBB.end()-1; + MachineInstr *MI; assert((*MBBI)->getOpcode() == X86::RET && "Can only insert epilog into returning blocks"); - // insert LEAVE: mov ESP, EBP; pop EBP - MBBI = 1+MBB.insert(MBBI, BuildMI(X86::MOVrr32, 1,X86::ESP).addReg(X86::EBP)); - MBBI = 1+MBB.insert(MBBI, BuildMI(X86::POPr32, 1).addReg(X86::EBP)); + if (hasFP(MF)) { + // Get the offset of the stack slot for the EBP register... which is + // guaranteed to be the last slot by processFunctionBeforeFrameFinalized. + int EBPOffset = FFI->getObjectOffset(FFI->getObjectIndexEnd()-1); + + // mov ESP, EBP + MI = BuildMI(X86::MOVrr32, 1,X86::ESP).addReg(X86::EBP); + MBBI = 1+MBB.insert(MBBI, MI); + + // mov EBP, [ESP-] + MI = addRegOffset(BuildMI(X86::MOVmr32, 5, X86::EBP), X86::ESP, EBPOffset); + MBBI = 1+MBB.insert(MBBI, MI); + } else { + if (!hasSPAdjust(MF)) return; + + // Get the number of bytes allocated from the FrameInfo... + unsigned NumBytes = FFI->getStackSize(); + NumBytes += FFI->getMaxCallFrameSize(); + + if (NumBytes) { // adjust stack pointer back: ESP += numbytes + MI =BuildMI(X86::ADDri32, 2, X86::ESP).addReg(X86::ESP).addZImm(NumBytes); + MBBI = 1+MBB.insert(MBBI, MI); + } + } +} + + +//===----------------------------------------------------------------------===// +// Register Class Implementation Code +//===----------------------------------------------------------------------===// + +//===----------------------------------------------------------------------===// +// 8 Bit Integer Registers +// +namespace { + const unsigned ByteRegClassRegs[] = { + X86::AL, X86::CL, X86::DL, X86::BL, X86::AH, X86::CH, X86::DH, X86::BH, + }; + + TargetRegisterClass X86ByteRegisterClassInstance(1, 1, ByteRegClassRegs, + ByteRegClassRegs+sizeof(ByteRegClassRegs)/sizeof(ByteRegClassRegs[0])); + +//===----------------------------------------------------------------------===// +// 16 Bit Integer Registers +// + const unsigned ShortRegClassRegs[] = { + X86::AX, X86::CX, X86::DX, X86::BX, X86::SI, X86::DI, X86::BP, X86::SP + }; + + struct R16CL : public TargetRegisterClass { + R16CL():TargetRegisterClass(2, 2, ShortRegClassRegs, ShortRegClassRegs+8) {} + iterator allocation_order_end(MachineFunction &MF) const { + if (hasFP(MF)) // Does the function dedicate EBP to being a frame ptr? + return end()-2; // Don't allocate SP or BP + else + return end()-1; // Don't allocate SP + } + } X86ShortRegisterClassInstance; + +//===----------------------------------------------------------------------===// +// 32 Bit Integer Registers +// + const unsigned IntRegClassRegs[] = { + X86::EAX, X86::ECX, X86::EDX, X86::EBX, + X86::ESI, X86::EDI, X86::EBP, X86::ESP + }; + + struct R32CL : public TargetRegisterClass { + R32CL() : TargetRegisterClass(4, 4, IntRegClassRegs, IntRegClassRegs+8) {} + iterator allocation_order_end(MachineFunction &MF) const { + if (hasFP(MF)) // Does the function dedicate EBP to being a frame ptr? + return end()-2; // Don't allocate ESP or EBP + else + return end()-1; // Don't allocate ESP + } + } X86IntRegisterClassInstance; + +//===----------------------------------------------------------------------===// +// Pseudo Floating Point Registers +// + const unsigned PFPRegClassRegs[] = { +#define PFP(ENUM, NAME, FLAGS, TSFLAGS, ALIAS_SET) X86::ENUM, +#include "X86RegisterInfo.def" + }; + + TargetRegisterClass X86FPRegisterClassInstance(10, 4, PFPRegClassRegs, + PFPRegClassRegs+sizeof(PFPRegClassRegs)/sizeof(PFPRegClassRegs[0])); + +//===----------------------------------------------------------------------===// +// Register class array... +// + const TargetRegisterClass * const X86RegClasses[] = { + &X86ByteRegisterClassInstance, + &X86ShortRegisterClassInstance, + &X86IntRegisterClassInstance, + &X86FPRegisterClassInstance, + }; +} + + +// Create static lists to contain register alias sets... +#define ALIASLIST(NAME, ...) \ + static const unsigned NAME[] = { __VA_ARGS__ }; +#include "X86RegisterInfo.def" + + +// X86Regs - Turn the X86RegisterInfo.def file into a bunch of register +// descriptors +// +static const MRegisterDesc X86Regs[] = { +#define R(ENUM, NAME, FLAGS, TSFLAGS, ALIAS_SET) \ + { NAME, ALIAS_SET, FLAGS, TSFLAGS }, +#include "X86RegisterInfo.def" +}; + +X86RegisterInfo::X86RegisterInfo() + : MRegisterInfo(X86Regs, sizeof(X86Regs)/sizeof(X86Regs[0]), + X86RegClasses, + X86RegClasses+sizeof(X86RegClasses)/sizeof(X86RegClasses[0]), + X86::ADJCALLSTACKDOWN, X86::ADJCALLSTACKUP) { +} + + + +const TargetRegisterClass* +X86RegisterInfo::getRegClassForType(const Type* Ty) const { + switch (Ty->getPrimitiveID()) { + default: assert(0 && "Invalid type to getClass!"); + case Type::BoolTyID: + case Type::SByteTyID: + case Type::UByteTyID: return &X86ByteRegisterClassInstance; + case Type::ShortTyID: + case Type::UShortTyID: return &X86ShortRegisterClassInstance; + case Type::LongTyID: // FIXME: Longs are not handled yet! + case Type::ULongTyID: // FIXME: Treat these like ints, this is bogus! + + case Type::IntTyID: + case Type::UIntTyID: + case Type::PointerTyID: return &X86IntRegisterClassInstance; + + case Type::FloatTyID: + case Type::DoubleTyID: return &X86FPRegisterClassInstance; + } } From lattner at cs.uiuc.edu Sat Dec 28 14:35:12 2002 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Sat Dec 28 14:35:12 2002 Subject: [llvm-commits] CVS: llvm/lib/Target/X86/X86TargetMachine.cpp Message-ID: <200212282034.OAA11502@apoc.cs.uiuc.edu> Changes in directory llvm/lib/Target/X86: X86TargetMachine.cpp updated: 1.10 -> 1.11 --- Log message: * Initialize new FrameInfo member * most pass ctors no longer take TM arguments * New prolog/epilog insertion pass --- Diffs of the changes: Index: llvm/lib/Target/X86/X86TargetMachine.cpp diff -u llvm/lib/Target/X86/X86TargetMachine.cpp:1.10 llvm/lib/Target/X86/X86TargetMachine.cpp:1.11 --- llvm/lib/Target/X86/X86TargetMachine.cpp:1.10 Tue Dec 24 23:06:21 2002 +++ llvm/lib/Target/X86/X86TargetMachine.cpp Sat Dec 28 14:33:32 2002 @@ -36,7 +36,8 @@ (Config & TM::EndianMask) == TM::LittleEndian, 1, 4, (Config & TM::PtrSizeMask) == TM::PtrSize64 ? 8 : 4, - (Config & TM::PtrSizeMask) == TM::PtrSize64 ? 8 : 4) { + (Config & TM::PtrSizeMask) == TM::PtrSize64 ? 8 : 4), + FrameInfo(TargetFrameInfo::StackGrowsDown, 1/*16*/, 0) { } @@ -60,12 +61,18 @@ // Perform register allocation to convert to a concrete x86 representation if (NoLocalRA) - PM.add(createSimpleRegisterAllocator(*this)); + PM.add(createSimpleRegisterAllocator()); else - PM.add(createLocalRegisterAllocator(*this)); + PM.add(createLocalRegisterAllocator()); + + if (PrintCode) + PM.add(createMachineFunctionPrinterPass()); + + // Insert prolog/epilog code. Eliminate abstract frame index references... + PM.add(createPrologEpilogCodeInserter()); if (PrintCode) // Print the register-allocated code - PM.add(createX86CodePrinterPass(*this, std::cerr)); + PM.add(createX86CodePrinterPass(std::cerr)); PM.add(createMachineCodeDestructionPass()); From lattner at cs.uiuc.edu Sat Dec 28 14:35:16 2002 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Sat Dec 28 14:35:16 2002 Subject: [llvm-commits] CVS: llvm/lib/Target/MachineFrameInfo.cpp Message-ID: <200212282034.OAA11523@apoc.cs.uiuc.edu> Changes in directory llvm/lib/Target: MachineFrameInfo.cpp (r1.3) removed --- Log message: Eliminate unneccesary file --- Diffs of the changes: From lattner at cs.uiuc.edu Sat Dec 28 14:35:20 2002 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Sat Dec 28 14:35:20 2002 Subject: [llvm-commits] CVS: llvm/lib/Target/MRegisterInfo.cpp Message-ID: <200212282034.OAA11528@apoc.cs.uiuc.edu> Changes in directory llvm/lib/Target: MRegisterInfo.cpp updated: 1.1 -> 1.2 --- Log message: Capture more information in ctor --- Diffs of the changes: Index: llvm/lib/Target/MRegisterInfo.cpp diff -u llvm/lib/Target/MRegisterInfo.cpp:1.1 llvm/lib/Target/MRegisterInfo.cpp:1.2 --- llvm/lib/Target/MRegisterInfo.cpp:1.1 Mon Dec 16 22:03:08 2002 +++ llvm/lib/Target/MRegisterInfo.cpp Sat Dec 28 14:34:18 2002 @@ -7,7 +7,8 @@ #include "llvm/Target/MRegisterInfo.h" MRegisterInfo::MRegisterInfo(const MRegisterDesc *D, unsigned NR, - regclass_iterator RCB, regclass_iterator RCE) + regclass_iterator RCB, regclass_iterator RCE, + int CFSO, int CFDO) : Desc(D), NumRegs(NR), RegClassBegin(RCB), RegClassEnd(RCE) { assert(NumRegs < FirstVirtualRegister && "Target has too many physical registers!"); @@ -24,6 +25,9 @@ "Register in more than one class?"); PhysRegClasses[(*I)->getRegister(i)] = *I; } + + CallFrameSetupOpcode = CFSO; + CallFrameDestroyOpcode = CFDO; } From lattner at cs.uiuc.edu Sat Dec 28 14:36:01 2002 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Sat Dec 28 14:36:01 2002 Subject: [llvm-commits] CVS: llvm/lib/CodeGen/RegAlloc/PhyRegAlloc.cpp Message-ID: <200212282035.OAA11544@apoc.cs.uiuc.edu> Changes in directory llvm/lib/CodeGen/RegAlloc: PhyRegAlloc.cpp updated: 1.87 -> 1.88 --- Log message: Frame info moved out of MachineFunction into a seperate object --- Diffs of the changes: Index: llvm/lib/CodeGen/RegAlloc/PhyRegAlloc.cpp diff -u llvm/lib/CodeGen/RegAlloc/PhyRegAlloc.cpp:1.87 llvm/lib/CodeGen/RegAlloc/PhyRegAlloc.cpp:1.88 --- llvm/lib/CodeGen/RegAlloc/PhyRegAlloc.cpp:1.87 Tue Oct 29 11:35:37 2002 +++ llvm/lib/CodeGen/RegAlloc/PhyRegAlloc.cpp Sat Dec 28 14:35:34 2002 @@ -11,6 +11,7 @@ #include "llvm/CodeGen/MachineInstr.h" #include "llvm/CodeGen/MachineInstrAnnot.h" #include "llvm/CodeGen/MachineFunction.h" +#include "llvm/CodeGen/MachineFunctionInfo.h" #include "llvm/Analysis/LiveVar/FunctionLiveVarInfo.h" #include "llvm/Analysis/LoopInfo.h" #include "llvm/Target/TargetMachine.h" @@ -508,7 +509,7 @@ continue; // Reset tmp stack positions so they can be reused for each machine instr. - MF.popAllTempValues(TM); + MF.getInfo()->popAllTempValues(); // Now insert speical instructions (if necessary) for call/return // instructions. @@ -658,7 +659,7 @@ RegClass *RC = LR->getRegClass(); const ValueSet &LVSetBef = LVI->getLiveVarSetBeforeMInst(MInst, BB); - MF.pushTempValue(TM, MRI.getSpilledRegSize(RegType) ); + MF.getInfo()->pushTempValue(MRI.getSpilledRegSize(RegType) ); vector MIBef, MIAft; vector AdIMid; @@ -749,7 +750,7 @@ // we couldn't find an unused register. Generate code to free up a reg by // saving it on stack and restoring after the instruction - int TmpOff = MF.pushTempValue(TM, MRI.getSpilledRegSize(RegType) ); + int TmpOff = MF.getInfo()->pushTempValue(MRI.getSpilledRegSize(RegType)); RegU = getUniRegNotUsedByThisInst(RC, MInst); @@ -1093,7 +1094,7 @@ if (HMI->first && HMI->second) { LiveRange *L = HMI->second; // get the LiveRange if (!L->hasColor()) { // NOTE: ** allocating the size of long Type ** - int stackOffset = MF.allocateSpilledValue(TM, Type::LongTy); + int stackOffset = MF.getInfo()->allocateSpilledValue(Type::LongTy); L->setSpillOffFromFP(stackOffset); if (DEBUG_RA) cerr << " LR# " << L->getUserIGNode()->getIndex() @@ -1159,12 +1160,12 @@ for (unsigned rc=0; rc < NumOfRegClasses ; rc++) RegClassList[rc]->colorAllRegs(); - // Atter grpah coloring, if some LRs did not receive a color (i.e, spilled) + // Atter graph coloring, if some LRs did not receive a color (i.e, spilled) // a poistion for such spilled LRs // allocateStackSpace4SpilledLRs(); - MF.popAllTempValues(TM); // TODO **Check + MF.getInfo()->popAllTempValues(); // TODO **Check // color incoming args - if the correct color was not received // insert code to copy to the correct register From lattner at cs.uiuc.edu Sat Dec 28 14:41:00 2002 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Sat Dec 28 14:41:00 2002 Subject: [llvm-commits] CVS: llvm/lib/CodeGen/MachineInstr.cpp Message-ID: <200212282040.OAA11569@apoc.cs.uiuc.edu> Changes in directory llvm/lib/CodeGen: MachineInstr.cpp updated: 1.66 -> 1.67 --- Log message: * Add printing support for FrameIndex operands --- Diffs of the changes: Index: llvm/lib/CodeGen/MachineInstr.cpp diff -u llvm/lib/CodeGen/MachineInstr.cpp:1.66 llvm/lib/CodeGen/MachineInstr.cpp:1.67 --- llvm/lib/CodeGen/MachineInstr.cpp:1.66 Sun Dec 15 14:35:25 2002 +++ llvm/lib/CodeGen/MachineInstr.cpp Sat Dec 28 14:37:37 2002 @@ -265,7 +265,9 @@ << ((Value*)MO.getMachineBasicBlock()->getBasicBlock())->getName() << "," << (void*)MO.getMachineBasicBlock()->getBasicBlock() << ">"; break; - + case MachineOperand::MO_FrameIndex: + OS << ""; + break; default: assert(0 && "Unrecognized operand type"); } @@ -341,61 +343,64 @@ return os << "\n"; } -std::ostream &operator<<(std::ostream &os, const MachineOperand &MO) +std::ostream &operator<<(std::ostream &OS, const MachineOperand &MO) { if (MO.opHiBits32()) - os << "%lm("; + OS << "%lm("; else if (MO.opLoBits32()) - os << "%lo("; + OS << "%lo("; else if (MO.opHiBits64()) - os << "%hh("; + OS << "%hh("; else if (MO.opLoBits64()) - os << "%hm("; + OS << "%hm("; switch (MO.getType()) { case MachineOperand::MO_VirtualRegister: - os << "%reg"; - OutputValue(os, MO.getVRegValue()); + OS << "%reg"; + OutputValue(OS, MO.getVRegValue()); if (MO.hasAllocatedReg()) { - os << "=="; - OutputReg(os, MO.getAllocatedRegNum()); + OS << "=="; + OutputReg(OS, MO.getAllocatedRegNum()); } break; case MachineOperand::MO_CCRegister: - os << "%ccreg"; - OutputValue(os, MO.getVRegValue()); + OS << "%ccreg"; + OutputValue(OS, MO.getVRegValue()); if (MO.hasAllocatedReg()) { - os << "=="; - OutputReg(os, MO.getAllocatedRegNum()); + OS << "=="; + OutputReg(OS, MO.getAllocatedRegNum()); } break; case MachineOperand::MO_MachineRegister: - OutputReg(os, MO.getMachineRegNum()); + OutputReg(OS, MO.getMachineRegNum()); break; case MachineOperand::MO_SignExtendedImmed: - os << (long)MO.getImmedValue(); + OS << (long)MO.getImmedValue(); break; case MachineOperand::MO_UnextendedImmed: - os << (long)MO.getImmedValue(); + OS << (long)MO.getImmedValue(); break; case MachineOperand::MO_PCRelativeDisp: { const Value* opVal = MO.getVRegValue(); bool isLabel = isa(opVal) || isa(opVal); - os << "%disp(" << (isLabel? "label " : "addr-of-val "); + OS << "%disp(" << (isLabel? "label " : "addr-of-val "); if (opVal->hasName()) - os << opVal->getName(); + OS << opVal->getName(); else - os << (const void*) opVal; - os << ")"; + OS << (const void*) opVal; + OS << ")"; break; } case MachineOperand::MO_MachineBasicBlock: - os << "bb<" + OS << "bb<" << ((Value*)MO.getMachineBasicBlock()->getBasicBlock())->getName() << "," << (void*)MO.getMachineBasicBlock()->getBasicBlock() << ">"; break; + case MachineOperand::MO_FrameIndex: + OS << ""; + break; default: assert(0 && "Unrecognized operand type"); break; @@ -404,7 +409,7 @@ if (MO.flags & (MachineOperand::HIFLAG32 | MachineOperand::LOFLAG32 | MachineOperand::HIFLAG64 | MachineOperand::LOFLAG64)) - os << ")"; + OS << ")"; - return os; + return OS; } From lattner at cs.uiuc.edu Sat Dec 28 14:43:01 2002 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Sat Dec 28 14:43:01 2002 Subject: [llvm-commits] CVS: llvm/lib/CodeGen/RegAllocLocal.cpp Message-ID: <200212282042.OAA11588@apoc.cs.uiuc.edu> Changes in directory llvm/lib/CodeGen: RegAllocLocal.cpp updated: 1.8 -> 1.9 --- Log message: * Convert to be a MachineFunctionPass instance * Use new FunctionFrameInfo object to manage stack slots instead of doing it directly * Adjust to new MRegisterInfo API * Don't take a TM as a ctor argument * Don't keep track of which callee saved registers are modified * Don't emit prolog/epilog code or spill/restore code for callee saved regs * Use new allocation_order_begin/end iterators to simplify dramatically the logic for picking registers to allocate * Machine PHI nodes can no longer contain constant arguments --- Diffs of the changes: Index: llvm/lib/CodeGen/RegAllocLocal.cpp diff -u llvm/lib/CodeGen/RegAllocLocal.cpp:1.8 llvm/lib/CodeGen/RegAllocLocal.cpp:1.9 --- llvm/lib/CodeGen/RegAllocLocal.cpp:1.8 Tue Dec 24 23:05:46 2002 +++ llvm/lib/CodeGen/RegAllocLocal.cpp Sat Dec 28 14:40:43 2002 @@ -5,9 +5,10 @@ // //===----------------------------------------------------------------------===// -#include "llvm/CodeGen/MachineFunction.h" +#include "llvm/CodeGen/MachineFunctionPass.h" #include "llvm/CodeGen/MachineInstr.h" #include "llvm/CodeGen/SSARegMap.h" +#include "llvm/CodeGen/FunctionFrameInfo.h" #include "llvm/Target/MachineInstrInfo.h" #include "llvm/Target/TargetMachine.h" #include "Support/Statistic.h" @@ -21,23 +22,14 @@ cl::opt DisableKill("no-kill", cl::Hidden, cl::desc("Disable register kill in local-ra")); - class RA : public FunctionPass { - TargetMachine &TM; + class RA : public MachineFunctionPass { + const TargetMachine *TM; MachineFunction *MF; - const MRegisterInfo &RegInfo; - const MachineInstrInfo &MIInfo; - unsigned NumBytesAllocated; - - // PhysRegsModified - Keep track of which physical registers are actually - // modified by the function we are code generating. This set allows us to - // only spill caller-saved registers that we actually change. - // - // FIXME: this would be much nicer & faster as a bitset. - // - std::set PhysRegsModified; - - // Maps SSA Regs => offsets on the stack where these values are stored - std::map VirtReg2OffsetMap; + const MRegisterInfo *RegInfo; + + // StackSlotForVirtReg - Maps SSA Regs => frame index where these values are + // spilled + std::map StackSlotForVirtReg; // Virt2PhysRegMap - This map contains entries for each virtual register // that is currently available in a physical register. @@ -85,16 +77,6 @@ } public: - - RA(TargetMachine &tm) - : TM(tm), RegInfo(*tm.getRegisterInfo()), MIInfo(tm.getInstrInfo()) { - cleanupAfterFunction(); - } - - bool runOnFunction(Function &Fn) { - return runOnMachineFunction(MachineFunction::get(&Fn)); - } - virtual const char *getPassName() const { return "Local Register Allocator"; } @@ -120,42 +102,21 @@ std::map &LastUseOfVReg) const; - /// EmitPrologue/EmitEpilogue - Use the register info object to add a - /// prologue/epilogue to the function and save/restore the callee saved - /// registers specified by the CSRegs list. - /// - void EmitPrologue(const std::vector &CSRegs); - void EmitEpilogue(MachineBasicBlock &MBB, - const std::vector &CSRegs); - /// areRegsEqual - This method returns true if the specified registers are /// related to each other. To do this, it checks to see if they are equal /// or if the first register is in the alias set of the second register. /// bool areRegsEqual(unsigned R1, unsigned R2) const { if (R1 == R2) return true; - if (const unsigned *AliasSet = RegInfo.getAliasSet(R2)) + if (const unsigned *AliasSet = RegInfo->getAliasSet(R2)) for (unsigned i = 0; AliasSet[i]; ++i) if (AliasSet[i] == R1) return true; return false; } - /// isAllocatableRegister - A register may be used by the program if it's - /// not the stack or frame pointer. - bool isAllocatableRegister(unsigned R) const { - unsigned FP = RegInfo.getFramePointer(), SP = RegInfo.getStackPointer(); - return !areRegsEqual(FP, R) && !areRegsEqual(SP, R); - } - - /// getStackSpaceFor - This returns the offset of the specified virtual + /// getStackSpaceFor - This returns the frame index of the specified virtual /// register on the stack, allocating space if neccesary. - unsigned getStackSpaceFor(unsigned VirtReg, - const TargetRegisterClass *regClass); - - void cleanupAfterFunction() { - VirtReg2OffsetMap.clear(); - NumBytesAllocated = 4; // FIXME: This is X86 specific - } + int getStackSpaceFor(unsigned VirtReg, const TargetRegisterClass *RC); void removePhysReg(unsigned PhysReg); @@ -174,7 +135,7 @@ std::map::iterator PI = PhysRegsUsed.find(PhysReg); if (PI != PhysRegsUsed.end()) { // Only spill it if it's used! spillVirtReg(MBB, I, PI->second, PhysReg); - } else if (const unsigned *AliasSet = RegInfo.getAliasSet(PhysReg)) { + } else if (const unsigned *AliasSet = RegInfo->getAliasSet(PhysReg)) { // If the selected register aliases any other registers, we must make // sure that one of the aliases isn't alive... for (unsigned i = 0; AliasSet[i]; ++i) { @@ -215,29 +176,22 @@ /// getStackSpaceFor - This allocates space for the specified virtual /// register to be held on the stack. -unsigned RA::getStackSpaceFor(unsigned VirtReg, - const TargetRegisterClass *RegClass) { +int RA::getStackSpaceFor(unsigned VirtReg, + const TargetRegisterClass *RC) { // Find the location VirtReg would belong... - std::map::iterator I = - VirtReg2OffsetMap.lower_bound(VirtReg); + std::map::iterator I = + StackSlotForVirtReg.lower_bound(VirtReg); - if (I != VirtReg2OffsetMap.end() && I->first == VirtReg) + if (I != StackSlotForVirtReg.end() && I->first == VirtReg) return I->second; // Already has space allocated? - unsigned RegSize = RegClass->getDataSize(); + // Allocate a new stack object for this spill location... + int FrameIdx = + MF->getFrameInfo()->CreateStackObject(RC->getSize(), RC->getAlignment()); - // Align NumBytesAllocated. We should be using TargetData alignment stuff - // to determine this, but we don't know the LLVM type associated with the - // virtual register. Instead, just align to a multiple of the size for now. - NumBytesAllocated += RegSize-1; - NumBytesAllocated = NumBytesAllocated/RegSize*RegSize; - // Assign the slot... - VirtReg2OffsetMap.insert(I, std::make_pair(VirtReg, NumBytesAllocated)); - - // Reserve the space! - NumBytesAllocated += RegSize; - return NumBytesAllocated-RegSize; + StackSlotForVirtReg.insert(I, std::make_pair(VirtReg, FrameIdx)); + return FrameIdx; } @@ -264,11 +218,10 @@ if (VirtReg != 0) { const TargetRegisterClass *RegClass = MF->getSSARegMap()->getRegClass(VirtReg); - unsigned stackOffset = getStackSpaceFor(VirtReg, RegClass); + int FrameIndex = getStackSpaceFor(VirtReg, RegClass); // Add move instruction(s) - RegInfo.storeReg2RegOffset(MBB, I, PhysReg, RegInfo.getFramePointer(), - -stackOffset, RegClass); + RegInfo->storeRegToStackSlot(MBB, I, PhysReg, FrameIndex, RegClass); ++NumSpilled; // Update statistics Virt2PhysRegMap.erase(VirtReg); // VirtReg no longer available } @@ -286,7 +239,7 @@ // If the selected register aliases any other allocated registers, it is // not free! - if (const unsigned *AliasSet = RegInfo.getAliasSet(PhysReg)) + if (const unsigned *AliasSet = RegInfo->getAliasSet(PhysReg)) for (unsigned i = 0; AliasSet[i]; ++i) if (PhysRegsUsed.count(AliasSet[i])) // Aliased register in use? return false; // Can't use this reg then. @@ -301,20 +254,22 @@ /// unsigned RA::getFreeReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator &I, unsigned VirtReg) { - const TargetRegisterClass *RegClass = - MF->getSSARegMap()->getRegClass(VirtReg); - unsigned PhysReg = 0; + const TargetRegisterClass *RC = MF->getSSARegMap()->getRegClass(VirtReg); + + // Get iterators defining the range of registers that are valid to allocate in + // this class, which also specifies the preferred allocation order. + TargetRegisterClass::iterator RI = RC->allocation_order_begin(*MF); + TargetRegisterClass::iterator RE = RC->allocation_order_end(*MF); // First check to see if we have a free register of the requested type... - for (TargetRegisterClass::iterator It = RegClass->begin(),E = RegClass->end(); - It != E; ++It) { - unsigned R = *It; + unsigned PhysReg = 0; + for (; RI != RE; ++RI) { + unsigned R = *RI; if (isPhysRegAvailable(R)) { // Is reg unused? - if (isAllocatableRegister(R)) { // And is not a frame register? - // Found an unused register! - PhysReg = R; - break; - } + // Found an unused register! + PhysReg = R; + assert(PhysReg != 0 && "Cannot use register!"); + break; } } @@ -331,25 +286,21 @@ unsigned R = PhysRegsUseOrder[i]; // If the current register is compatible, use it. - if (isAllocatableRegister(R)) { - if (RegInfo.getRegClass(R) == RegClass) { - PhysReg = R; - break; - } else { - // If one of the registers aliased to the current register is - // compatible, use it. - if (const unsigned *AliasSet = RegInfo.getAliasSet(R)) - for (unsigned a = 0; AliasSet[a]; ++a) - if (RegInfo.getRegClass(AliasSet[a]) == RegClass) { - PhysReg = AliasSet[a]; // Take an aliased register - break; - } - } + if (RegInfo->getRegClass(R) == RC) { + PhysReg = R; + break; + } else { + // If one of the registers aliased to the current register is + // compatible, use it. + if (const unsigned *AliasSet = RegInfo->getAliasSet(R)) + for (unsigned a = 0; AliasSet[a]; ++a) + if (RegInfo->getRegClass(AliasSet[a]) == RC) { + PhysReg = AliasSet[a]; // Take an aliased register + break; + } } } - assert(isAllocatableRegister(PhysReg) && "Register is not allocatable!"); - assert(PhysReg && "Physical register not assigned!?!?"); // At this point PhysRegsUseOrder[i] is the least recently used register of @@ -391,11 +342,10 @@ unsigned PhysReg = getFreeReg(MBB, I, VirtReg); const TargetRegisterClass *RC = MF->getSSARegMap()->getRegClass(VirtReg); - unsigned StackOffset = getStackSpaceFor(VirtReg, RC); + int FrameIndex = getStackSpaceFor(VirtReg, RC); // Add move instruction(s) - RegInfo.loadRegOffset2Reg(MBB, I, PhysReg, RegInfo.getFramePointer(), - -StackOffset, RC); + RegInfo->loadRegFromStackSlot(MBB, I, PhysReg, FrameIndex, RC); ++NumReloaded; // Update statistics return PhysReg; } @@ -440,7 +390,7 @@ /// predecessor basic blocks. /// void RA::EliminatePHINodes(MachineBasicBlock &MBB) { - const MachineInstrInfo &MII = TM.getInstrInfo(); + const MachineInstrInfo &MII = TM->getInstrInfo(); while (MBB.front()->getOpcode() == MachineInstrInfo::PHI) { MachineInstr *MI = MBB.front(); @@ -490,15 +440,9 @@ const TargetRegisterClass *RC = MF->getSSARegMap()->getRegClass(virtualReg); - // Retrieve the constant value from this op, move it to target - // register of the phi - if (opVal.isImmediate()) { - RegInfo.moveImm2Reg(opBlock, opI, virtualReg, - (unsigned) opVal.getImmedValue(), RC); - } else { - RegInfo.moveReg2Reg(opBlock, opI, virtualReg, - opVal.getAllocatedRegNum(), RC); - } + assert(opVal.isVirtualRegister() && + "Machine PHI Operands must all be virtual registers!"); + RegInfo->copyRegToReg(opBlock, opI, virtualReg, opVal.getReg(), RC); } } @@ -513,7 +457,7 @@ MachineBasicBlock::iterator I = MBB.begin(); for (; I != MBB.end(); ++I) { MachineInstr *MI = *I; - const MachineInstrDescriptor &MID = MIInfo.get(MI->getOpcode()); + const MachineInstrDescriptor &MID = TM->getInstrInfo().get(MI->getOpcode()); // Loop over all of the operands of the instruction, spilling registers that // are defined, and marking explicit destinations in the PhysRegsUsed map. @@ -527,7 +471,6 @@ spillPhysReg(MBB, I, Reg); PhysRegsUsed[Reg] = 0; // It is free and reserved now PhysRegsUseOrder.push_back(Reg); - PhysRegsModified.insert(Reg); // Register is modified by current Fn } // Loop over the implicit defs, spilling them, as above. @@ -546,7 +489,6 @@ } PhysRegsUseOrder.push_back(Reg); PhysRegsUsed[Reg] = 0; // It is free and reserved now - PhysRegsModified.insert(Reg); // Register is modified by current Fn } // Loop over the implicit uses, making sure that they are at the head of the @@ -565,7 +507,6 @@ unsigned VirtSrcReg = MI->getOperand(i).getAllocatedRegNum(); unsigned PhysSrcReg = reloadVirtReg(MBB, I, VirtSrcReg); MI->SetMachineOperandReg(i, PhysSrcReg); // Assign the input register - PhysRegsModified.insert(PhysSrcReg); // Register is modified } // Okay, we have allocated all of the source operands and spilled any values @@ -579,7 +520,7 @@ unsigned DestVirtReg = MI->getOperand(i).getAllocatedRegNum(); unsigned DestPhysReg; - if (TM.getInstrInfo().isTwoAddrInstr(MI->getOpcode()) && i == 0) { + if (TM->getInstrInfo().isTwoAddrInstr(MI->getOpcode()) && i == 0) { // must be same register number as the first operand // This maps a = b + c into b += c, and saves b into a's spot assert(MI->getOperand(1).isRegister() && @@ -595,7 +536,6 @@ } else { DestPhysReg = getFreeReg(MBB, I, DestVirtReg); } - PhysRegsModified.insert(DestPhysReg); // Register is modified MI->SetMachineOperandReg(i, DestPhysReg); // Assign the output register } @@ -619,7 +559,7 @@ } // Rewind the iterator to point to the first flow control instruction... - const MachineInstrInfo &MII = TM.getInstrInfo(); + const MachineInstrInfo &MII = TM->getInstrInfo(); I = MBB.end(); do { --I; @@ -639,54 +579,13 @@ } -/// EmitPrologue - Use the register info object to add a prologue to the -/// function and save any callee saved registers we are responsible for. -/// -void RA::EmitPrologue(const std::vector &CSRegs) { - MachineBasicBlock &MBB = MF->front(); // Prolog goes in entry BB - MachineBasicBlock::iterator I = MBB.begin(); - - for (unsigned i = 0, e = CSRegs.size(); i != e; ++i) { - const TargetRegisterClass *RegClass = RegInfo.getRegClass(CSRegs[i]); - unsigned Offset = getStackSpaceFor(CSRegs[i], RegClass); - - // Insert the spill to the stack frame... - ++NumSpilled; - RegInfo.storeReg2RegOffset(MBB, I, CSRegs[i], RegInfo.getFramePointer(), - -Offset, RegClass); - } - - // Add prologue to the function... - RegInfo.emitPrologue(*MF, NumBytesAllocated); -} - - -/// EmitEpilogue - Use the register info object to add a epilogue to the -/// function and restore any callee saved registers we are responsible for. -/// -void RA::EmitEpilogue(MachineBasicBlock &MBB, - const std::vector &CSRegs) { - // Insert instructions before the return. - MachineBasicBlock::iterator I = MBB.end()-1; - - for (unsigned i = 0, e = CSRegs.size(); i != e; ++i) { - const TargetRegisterClass *RegClass = RegInfo.getRegClass(CSRegs[i]); - unsigned Offset = getStackSpaceFor(CSRegs[i], RegClass); - ++NumReloaded; - RegInfo.loadRegOffset2Reg(MBB, I, CSRegs[i], RegInfo.getFramePointer(), - -Offset, RegClass); - --I; // Insert in reverse order - } - - RegInfo.emitEpilogue(MBB, NumBytesAllocated); -} - - /// runOnMachineFunction - Register allocate the whole function /// bool RA::runOnMachineFunction(MachineFunction &Fn) { DEBUG(std::cerr << "Machine Function " << "\n"); MF = &Fn; + TM = &Fn.getTarget(); + RegInfo = TM->getRegisterInfo(); // First pass: eliminate PHI instructions by inserting copies into predecessor // blocks, and calculate a simple approximation of killing uses for virtual @@ -718,42 +617,11 @@ MBB != MBBe; ++MBB) AllocateBasicBlock(*MBB); - // Figure out which callee saved registers are modified by the current - // function, thus needing to be saved and restored in the prolog/epilog. - // - const unsigned *CSRegs = RegInfo.getCalleeSaveRegs(); - std::vector RegsToSave; - for (unsigned i = 0; CSRegs[i]; ++i) { - unsigned Reg = CSRegs[i]; - if (PhysRegsModified.count(Reg)) // If modified register... - RegsToSave.push_back(Reg); - else if (const unsigned *AliasSet = RegInfo.getAliasSet(Reg)) - for (unsigned j = 0; AliasSet[j]; ++j) // Check alias registers too... - if (PhysRegsModified.count(AliasSet[j])) { - RegsToSave.push_back(Reg); - break; - } - } - - // Emit a prologue for the function... - EmitPrologue(RegsToSave); - - const MachineInstrInfo &MII = TM.getInstrInfo(); - - // Add epilogue to restore the callee-save registers in each exiting block - for (MachineFunction::iterator MBB = Fn.begin(), MBBe = Fn.end(); - MBB != MBBe; ++MBB) { - // If last instruction is a return instruction, add an epilogue - if (MII.isReturn(MBB->back()->getOpcode())) - EmitEpilogue(*MBB, RegsToSave); - } - - PhysRegsModified.clear(); LastUserOf.clear(); - cleanupAfterFunction(); + StackSlotForVirtReg.clear(); return true; } -Pass *createLocalRegisterAllocator(TargetMachine &TM) { - return new RA(TM); +Pass *createLocalRegisterAllocator() { + return new RA(); } From lattner at cs.uiuc.edu Sat Dec 28 14:43:05 2002 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Sat Dec 28 14:43:05 2002 Subject: [llvm-commits] CVS: llvm/lib/CodeGen/RegAllocSimple.cpp Message-ID: <200212282042.OAA11595@apoc.cs.uiuc.edu> Changes in directory llvm/lib/CodeGen: RegAllocSimple.cpp updated: 1.34 -> 1.35 --- Log message: * Convert to be a MachineFunctionPass instance * Use new FunctionFrameInfo object to manage stack slots instead of doing it directly * Adjust to new MRegisterInfo API * Don't take a TM as a ctor argument * Don't keep track of which callee saved registers are modified * Don't emit prolog/epilog code or spill/restore code for callee saved regs * Use new allocation_order_begin/end iterators to simplify dramatically the logic for picking registers to allocate * Machine PHI nodes can no longer contain constant arguments * Use a bitvector to keep track of registers used instead of a set * Fix problem where explicitly referenced registers would be added to regsused set and never removed --- Diffs of the changes: Index: llvm/lib/CodeGen/RegAllocSimple.cpp diff -u llvm/lib/CodeGen/RegAllocSimple.cpp:1.34 llvm/lib/CodeGen/RegAllocSimple.cpp:1.35 --- llvm/lib/CodeGen/RegAllocSimple.cpp:1.34 Tue Dec 24 23:04:20 2002 +++ llvm/lib/CodeGen/RegAllocSimple.cpp Sat Dec 28 14:42:14 2002 @@ -1,33 +1,37 @@ //===-- RegAllocSimple.cpp - A simple generic register allocator ----------===// // -// This file implements a simple register allocator. *Very* simple. +// This file implements a simple register allocator. *Very* simple: It immediate +// spills every value right after it is computed, and it reloads all used +// operands from the spill area to temporary registers before each instruction. +// It does not keep values in registers across instructions. // //===----------------------------------------------------------------------===// -#include "llvm/CodeGen/MachineFunction.h" +#include "llvm/CodeGen/MachineFunctionPass.h" #include "llvm/CodeGen/MachineInstr.h" #include "llvm/CodeGen/SSARegMap.h" +#include "llvm/CodeGen/FunctionFrameInfo.h" #include "llvm/Target/MachineInstrInfo.h" #include "llvm/Target/TargetMachine.h" #include "Support/Statistic.h" #include -#include namespace { Statistic<> NumSpilled ("ra-simple", "Number of registers spilled"); Statistic<> NumReloaded("ra-simple", "Number of registers reloaded"); - class RegAllocSimple : public FunctionPass { - TargetMachine &TM; + class RegAllocSimple : public MachineFunctionPass { MachineFunction *MF; + const TargetMachine *TM; const MRegisterInfo *RegInfo; - unsigned NumBytesAllocated; - // Maps SSA Regs => offsets on the stack where these values are stored - std::map VirtReg2OffsetMap; - - // RegsUsed - Keep track of what registers are currently in use. - std::set RegsUsed; + // StackSlotForVirtReg - Maps SSA Regs => frame index on the stack where + // these values are spilled + std::map StackSlotForVirtReg; + + // RegsUsed - Keep track of what registers are currently in use. This is a + // bitset. + std::vector RegsUsed; // RegClassIdx - Maps RegClass => which index we can take a register // from. Since this is a simple register allocator, when we need a register @@ -35,27 +39,14 @@ std::map RegClassIdx; public: - - RegAllocSimple(TargetMachine &tm) - : TM(tm), RegInfo(tm.getRegisterInfo()) { - RegsUsed.insert(RegInfo->getFramePointer()); - RegsUsed.insert(RegInfo->getStackPointer()); - - cleanupAfterFunction(); - } - - bool runOnFunction(Function &Fn) { - return runOnMachineFunction(MachineFunction::get(&Fn)); - } - virtual const char *getPassName() const { return "Simple Register Allocator"; } - private: /// runOnMachineFunction - Register allocate the whole function bool runOnMachineFunction(MachineFunction &Fn); + private: /// AllocateBasicBlock - Register allocate the specified basic block. void AllocateBasicBlock(MachineBasicBlock &MBB); @@ -63,18 +54,9 @@ /// in predecessor basic blocks. void EliminatePHINodes(MachineBasicBlock &MBB); - /// EmitPrologue/EmitEpilogue - Use the register info object to add a - /// prologue/epilogue to the function and save/restore any callee saved - /// registers we are responsible for. - /// - void EmitPrologue(); - void EmitEpilogue(MachineBasicBlock &MBB); - - /// getStackSpaceFor - This returns the offset of the specified virtual /// register on the stack, allocating space if neccesary. - unsigned getStackSpaceFor(unsigned VirtReg, - const TargetRegisterClass *regClass); + int getStackSpaceFor(unsigned VirtReg, const TargetRegisterClass *RC); /// Given a virtual register, return a compatible physical register that is /// currently unused. @@ -83,30 +65,6 @@ /// unsigned getFreeReg(unsigned virtualReg); - /// Returns all `borrowed' registers back to the free pool - void clearAllRegs() { - RegClassIdx.clear(); - } - - /// Invalidates any references, real or implicit, to physical registers - /// - void invalidatePhysRegs(const MachineInstr *MI) { - unsigned Opcode = MI->getOpcode(); - const MachineInstrDescriptor &Desc = TM.getInstrInfo().get(Opcode); - if (const unsigned *regs = Desc.ImplicitUses) - while (*regs) - RegsUsed.insert(*regs++); - - if (const unsigned *regs = Desc.ImplicitDefs) - while (*regs) - RegsUsed.insert(*regs++); - } - - void cleanupAfterFunction() { - VirtReg2OffsetMap.clear(); - NumBytesAllocated = 4; // FIXME: This is X86 specific - } - /// Moves value from memory into that register unsigned reloadVirtReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator &I, unsigned VirtReg); @@ -120,69 +78,62 @@ /// getStackSpaceFor - This allocates space for the specified virtual /// register to be held on the stack. -unsigned RegAllocSimple::getStackSpaceFor(unsigned VirtReg, - const TargetRegisterClass *regClass) { +int RegAllocSimple::getStackSpaceFor(unsigned VirtReg, + const TargetRegisterClass *RC) { // Find the location VirtReg would belong... - std::map::iterator I = - VirtReg2OffsetMap.lower_bound(VirtReg); + std::map::iterator I = + StackSlotForVirtReg.lower_bound(VirtReg); - if (I != VirtReg2OffsetMap.end() && I->first == VirtReg) + if (I != StackSlotForVirtReg.end() && I->first == VirtReg) return I->second; // Already has space allocated? - unsigned RegSize = regClass->getDataSize(); - - // Align NumBytesAllocated. We should be using TargetData alignment stuff - // to determine this, but we don't know the LLVM type associated with the - // virtual register. Instead, just align to a multiple of the size for now. - NumBytesAllocated += RegSize-1; - NumBytesAllocated = NumBytesAllocated/RegSize*RegSize; + // Allocate a new stack object for this spill location... + int FrameIdx = + MF->getFrameInfo()->CreateStackObject(RC->getSize(), RC->getAlignment()); // Assign the slot... - VirtReg2OffsetMap.insert(I, std::make_pair(VirtReg, NumBytesAllocated)); - - // Reserve the space! - NumBytesAllocated += RegSize; - return NumBytesAllocated-RegSize; + StackSlotForVirtReg.insert(I, std::make_pair(VirtReg, FrameIdx)); + + return FrameIdx; } unsigned RegAllocSimple::getFreeReg(unsigned virtualReg) { const TargetRegisterClass* RC = MF->getSSARegMap()->getRegClass(virtualReg); - - unsigned regIdx = RegClassIdx[RC]++; - assert(regIdx < RC->getNumRegs() && "Not enough registers!"); - unsigned physReg = RC->getRegister(regIdx); - - if (RegsUsed.find(physReg) == RegsUsed.end()) - return physReg; - else - return getFreeReg(virtualReg); + TargetRegisterClass::iterator RI = RC->allocation_order_begin(*MF); + TargetRegisterClass::iterator RE = RC->allocation_order_end(*MF); + + while (1) { + unsigned regIdx = RegClassIdx[RC]++; + assert(RI+regIdx != RE && "Not enough registers!"); + unsigned PhysReg = *(RI+regIdx); + + if (!RegsUsed[PhysReg]) + return PhysReg; + } } unsigned RegAllocSimple::reloadVirtReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator &I, unsigned VirtReg) { const TargetRegisterClass* RC = MF->getSSARegMap()->getRegClass(VirtReg); - unsigned stackOffset = getStackSpaceFor(VirtReg, RC); + int FrameIdx = getStackSpaceFor(VirtReg, RC); unsigned PhysReg = getFreeReg(VirtReg); // Add move instruction(s) ++NumReloaded; - RegInfo->loadRegOffset2Reg(MBB, I, PhysReg, RegInfo->getFramePointer(), - -stackOffset, RC); + RegInfo->loadRegFromStackSlot(MBB, I, PhysReg, FrameIdx, RC); return PhysReg; } void RegAllocSimple::spillVirtReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator &I, - unsigned VirtReg, unsigned PhysReg) -{ + unsigned VirtReg, unsigned PhysReg) { const TargetRegisterClass* RC = MF->getSSARegMap()->getRegClass(VirtReg); - unsigned stackOffset = getStackSpaceFor(VirtReg, RC); + int FrameIdx = getStackSpaceFor(VirtReg, RC); // Add move instruction(s) ++NumSpilled; - RegInfo->storeReg2RegOffset(MBB, I, PhysReg, RegInfo->getFramePointer(), - -stackOffset, RC); + RegInfo->storeRegToStackSlot(MBB, I, PhysReg, FrameIdx, RC); } @@ -190,7 +141,7 @@ /// predecessor basic blocks. /// void RegAllocSimple::EliminatePHINodes(MachineBasicBlock &MBB) { - const MachineInstrInfo &MII = TM.getInstrInfo(); + const MachineInstrInfo &MII = TM->getInstrInfo(); while (MBB.front()->getOpcode() == MachineInstrInfo::PHI) { MachineInstr *MI = MBB.front(); @@ -242,15 +193,9 @@ const TargetRegisterClass *RC = MF->getSSARegMap()->getRegClass(virtualReg); - // Retrieve the constant value from this op, move it to target - // register of the phi - if (opVal.isImmediate()) { - RegInfo->moveImm2Reg(opBlock, opI, virtualReg, - (unsigned) opVal.getImmedValue(), RC); - } else { - RegInfo->moveReg2Reg(opBlock, opI, virtualReg, - opVal.getAllocatedRegNum(), RC); - } + assert(opVal.isVirtualRegister() && + "Machine PHI Operands must all be virtual registers!"); + RegInfo->copyRegToReg(opBlock, opI, virtualReg, opVal.getReg(), RC); } } @@ -267,10 +212,20 @@ std::map Virt2PhysRegMap; MachineInstr *MI = *I; + + RegsUsed.resize(MRegisterInfo::FirstVirtualRegister); // a preliminary pass that will invalidate any registers that // are used by the instruction (including implicit uses) - invalidatePhysRegs(MI); + unsigned Opcode = MI->getOpcode(); + const MachineInstrDescriptor &Desc = TM->getInstrInfo().get(Opcode); + if (const unsigned *Regs = Desc.ImplicitUses) + while (*Regs) + RegsUsed[*Regs++] = true; + + if (const unsigned *Regs = Desc.ImplicitDefs) + while (*Regs) + RegsUsed[*Regs++] = true; // Loop over uses, move from memory into registers for (int i = MI->getNumOperands() - 1; i >= 0; --i) { @@ -280,14 +235,14 @@ unsigned virtualReg = (unsigned) op.getAllocatedRegNum(); DEBUG(std::cerr << "op: " << op << "\n"); DEBUG(std::cerr << "\t inst[" << i << "]: "; - MI->print(std::cerr, TM)); + MI->print(std::cerr, *TM)); // make sure the same virtual register maps to the same physical // register in any given instruction unsigned physReg = Virt2PhysRegMap[virtualReg]; if (physReg == 0) { if (op.opIsDef()) { - if (TM.getInstrInfo().isTwoAddrInstr(MI->getOpcode()) && i == 0) { + if (TM->getInstrInfo().isTwoAddrInstr(MI->getOpcode()) && i == 0) { // must be same register number as the first operand // This maps a = b + c into b += c, and saves b into a's spot assert(MI->getOperand(1).isRegister() && @@ -312,56 +267,9 @@ ", phys: " << op.getAllocatedRegNum() << "\n"); } } - clearAllRegs(); - } -} - - -/// EmitPrologue - Use the register info object to add a prologue to the -/// function and save any callee saved registers we are responsible for. -/// -void RegAllocSimple::EmitPrologue() { - // Get a list of the callee saved registers, so that we can save them on entry - // to the function. - // - MachineBasicBlock &MBB = MF->front(); // Prolog goes in entry BB - MachineBasicBlock::iterator I = MBB.begin(); - - const unsigned *CSRegs = RegInfo->getCalleeSaveRegs(); - for (unsigned i = 0; CSRegs[i]; ++i) { - const TargetRegisterClass *RegClass = RegInfo->getRegClass(CSRegs[i]); - unsigned Offset = getStackSpaceFor(CSRegs[i], RegClass); - - // Insert the spill to the stack frame... - RegInfo->storeReg2RegOffset(MBB, I,CSRegs[i],RegInfo->getFramePointer(), - -Offset, RegClass); - ++NumSpilled; + RegClassIdx.clear(); + RegsUsed.clear(); } - - // Add prologue to the function... - RegInfo->emitPrologue(*MF, NumBytesAllocated); -} - - -/// EmitEpilogue - Use the register info object to add a epilogue to the -/// function and restore any callee saved registers we are responsible for. -/// -void RegAllocSimple::EmitEpilogue(MachineBasicBlock &MBB) { - // Insert instructions before the return. - MachineBasicBlock::iterator I = MBB.end()-1; - - const unsigned *CSRegs = RegInfo->getCalleeSaveRegs(); - for (unsigned i = 0; CSRegs[i]; ++i) { - const TargetRegisterClass *RegClass = RegInfo->getRegClass(CSRegs[i]); - unsigned Offset = getStackSpaceFor(CSRegs[i], RegClass); - - RegInfo->loadRegOffset2Reg(MBB, I, CSRegs[i],RegInfo->getFramePointer(), - -Offset, RegClass); - --I; // Insert in reverse order - ++NumReloaded; - } - - RegInfo->emitEpilogue(MBB, NumBytesAllocated); } @@ -370,6 +278,8 @@ bool RegAllocSimple::runOnMachineFunction(MachineFunction &Fn) { DEBUG(std::cerr << "Machine Function " << "\n"); MF = &Fn; + TM = &MF->getTarget(); + RegInfo = TM->getRegisterInfo(); // First pass: eliminate PHI instructions by inserting copies into predecessor // blocks. @@ -382,27 +292,10 @@ MBB != MBBe; ++MBB) AllocateBasicBlock(*MBB); - // Round stack allocation up to a nice alignment to keep the stack aligned - // FIXME: This is X86 specific! Move to frame manager - NumBytesAllocated = (NumBytesAllocated + 3) & ~3; - - // Emit a prologue for the function... - EmitPrologue(); - - const MachineInstrInfo &MII = TM.getInstrInfo(); - - // Add epilogue to restore the callee-save registers in each exiting block - for (MachineFunction::iterator MBB = Fn.begin(), MBBe = Fn.end(); - MBB != MBBe; ++MBB) { - // If last instruction is a return instruction, add an epilogue - if (MII.isReturn(MBB->back()->getOpcode())) - EmitEpilogue(*MBB); - } - - cleanupAfterFunction(); + StackSlotForVirtReg.clear(); return true; } -Pass *createSimpleRegisterAllocator(TargetMachine &TM) { - return new RegAllocSimple(TM); +Pass *createSimpleRegisterAllocator() { + return new RegAllocSimple(); } From lattner at cs.uiuc.edu Sat Dec 28 14:43:09 2002 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Sat Dec 28 14:43:09 2002 Subject: [llvm-commits] CVS: llvm/lib/CodeGen/MachineFunction.cpp Message-ID: <200212282042.OAA11600@apoc.cs.uiuc.edu> Changes in directory llvm/lib/CodeGen: MachineFunction.cpp updated: 1.32 -> 1.33 --- Log message: * A bunch of functionality and data was removed from MachineFunction and put into a new MachineFunctionInfo class * Implement new FunctionFrameInfo class --- Diffs of the changes: Index: llvm/lib/CodeGen/MachineFunction.cpp diff -u llvm/lib/CodeGen/MachineFunction.cpp:1.32 llvm/lib/CodeGen/MachineFunction.cpp:1.33 --- llvm/lib/CodeGen/MachineFunction.cpp:1.32 Tue Dec 24 23:03:22 2002 +++ llvm/lib/CodeGen/MachineFunction.cpp Sat Dec 28 14:37:16 2002 @@ -10,6 +10,8 @@ #include "llvm/CodeGen/MachineInstr.h" #include "llvm/CodeGen/MachineCodeForInstruction.h" #include "llvm/CodeGen/SSARegMap.h" +#include "llvm/CodeGen/MachineFunctionInfo.h" +#include "llvm/CodeGen/FunctionFrameInfo.h" #include "llvm/Target/TargetMachine.h" #include "llvm/Target/MachineFrameInfo.h" #include "llvm/Target/MachineCacheInfo.h" @@ -39,7 +41,7 @@ } bool runOnFunction(Function &F) { - MachineFunction::construct(&F, Target).CalculateArgSize(); + MachineFunction::construct(&F, Target).getInfo()->CalculateArgSize(); return false; } }; @@ -95,25 +97,27 @@ //===---------------------------------------------------------------------===// MachineFunction::MachineFunction(const Function *F, - const TargetMachine& target) - : Annotation(MF_AID), Fn(F), Target(target) { + const TargetMachine &TM) + : Annotation(MF_AID), Fn(F), Target(TM) { SSARegMapping = new SSARegMap(); - - // FIXME: move state into another class - staticStackSize = automaticVarsSize = regSpillsSize = 0; - maxOptionalArgsSize = maxOptionalNumArgs = currentTmpValuesSize = 0; - maxTmpValuesSize = 0; - compiledAsLeaf = spillsAreaFrozen = automaticVarsAreaFrozen = false; + MFInfo = new MachineFunctionInfo(*this); + FrameInfo = new FunctionFrameInfo(); } MachineFunction::~MachineFunction() { delete SSARegMapping; + delete MFInfo; + delete FrameInfo; } void MachineFunction::dump() const { print(std::cerr); } void MachineFunction::print(std::ostream &OS) const { - OS << "\n" << *(Value*)Fn->getReturnType() << " \"" << Fn->getName()<< "\"\n"; + OS << "\n" << *(Value*)Fn->getFunctionType() << " \"" << Fn->getName() + << "\"\n"; + + // Print Frame Information + getFrameInfo()->print(OS); for (const_iterator BB = begin(); BB != end(); ++BB) { BasicBlock *LBB = BB->getBasicBlock(); @@ -163,12 +167,48 @@ SSARegMapping = 0; } +//===----------------------------------------------------------------------===// +// FunctionFrameInfo implementation +//===----------------------------------------------------------------------===// + +void FunctionFrameInfo::print(std::ostream &OS) const { + for (unsigned i = 0, e = Objects.size(); i != e; ++i) { + const StackObject &SO = Objects[i]; + OS << " is "; + if (SO.Size == 0) + OS << "variable sized"; + else + OS << SO.Size << " byte" << (SO.Size != 1 ? "s" : " "); + + if (i < NumFixedObjects) + OS << " fixed"; + if (i < NumFixedObjects || SO.SPOffset != -1) { + OS << " at location [SP"; + if (SO.SPOffset > 0) + OS << "+" << SO.SPOffset; + else if (SO.SPOffset < 0) + OS << SO.SPOffset; + OS << "]"; + } + OS << "\n"; + } + + if (HasVarSizedObjects) + OS << " Stack frame contains variable sized objects\n"; +} + +void FunctionFrameInfo::dump() const { print(std::cerr); } + + +//===----------------------------------------------------------------------===// +// MachineFunctionInfo implementation +//===----------------------------------------------------------------------===// static unsigned ComputeMaxOptionalArgsSize(const TargetMachine& target, const Function *F, unsigned &maxOptionalNumArgs) { - const MachineFrameInfo& frameInfo = target.getFrameInfo(); + const TargetFrameInfo &frameInfo = target.getFrameInfo(); unsigned maxSize = 0; @@ -181,7 +221,7 @@ if (numExtra <= 0) continue; - unsigned int sizeForThisCall; + unsigned sizeForThisCall; if (frameInfo.argsOnStackHaveFixedSize()) { int argSize = frameInfo.getSizeOfEachArgOnStack(); @@ -194,7 +234,7 @@ "compute MaxOptionalArgsSize"); sizeForThisCall = 0; for (unsigned i = 0; i < numOperands; ++i) - sizeForThisCall += target.DataLayout.getTypeSize(callInst-> + sizeForThisCall += target.getTargetData().getTypeSize(callInst-> getOperand(i)->getType()); } @@ -217,52 +257,51 @@ // but they are unrelated. This one does not align at more than a // double-word boundary whereas that one might. // -inline unsigned int -SizeToAlignment(unsigned int size, const TargetMachine& target) +inline unsigned +SizeToAlignment(unsigned size, const TargetMachine& target) { unsigned short cacheLineSize = target.getCacheInfo().getCacheLineSize(1); if (size > (unsigned) cacheLineSize / 2) return cacheLineSize; else for (unsigned sz=1; /*no condition*/; sz *= 2) - if (sz >= size || sz >= target.DataLayout.getDoubleAlignment()) + if (sz >= size || sz >= target.getTargetData().getDoubleAlignment()) return sz; } -void MachineFunction::CalculateArgSize() { - maxOptionalArgsSize = ComputeMaxOptionalArgsSize(Target, Fn, +void MachineFunctionInfo::CalculateArgSize() { + maxOptionalArgsSize = ComputeMaxOptionalArgsSize(MF.getTarget(), + MF.getFunction(), maxOptionalNumArgs); staticStackSize = maxOptionalArgsSize - + Target.getFrameInfo().getMinStackFrameSize(); + + MF.getTarget().getFrameInfo().getMinStackFrameSize(); } int -MachineFunction::computeOffsetforLocalVar(const TargetMachine& target, - const Value* val, - unsigned int& getPaddedSize, - unsigned int sizeToUse) +MachineFunctionInfo::computeOffsetforLocalVar(const Value* val, + unsigned &getPaddedSize, + unsigned sizeToUse) { if (sizeToUse == 0) - sizeToUse = target.findOptimalStorageSize(val->getType()); - unsigned int align = SizeToAlignment(sizeToUse, target); + sizeToUse = MF.getTarget().findOptimalStorageSize(val->getType()); + unsigned align = SizeToAlignment(sizeToUse, MF.getTarget()); bool growUp; - int firstOffset = target.getFrameInfo().getFirstAutomaticVarOffset(*this, - growUp); + int firstOffset = MF.getTarget().getFrameInfo().getFirstAutomaticVarOffset(MF, + growUp); int offset = growUp? firstOffset + getAutomaticVarsSize() : firstOffset - (getAutomaticVarsSize() + sizeToUse); - int aligned = target.getFrameInfo().adjustAlignment(offset, growUp, align); + int aligned = MF.getTarget().getFrameInfo().adjustAlignment(offset, growUp, align); getPaddedSize = sizeToUse + abs(aligned - offset); return aligned; } int -MachineFunction::allocateLocalVar(const TargetMachine& target, - const Value* val, - unsigned int sizeToUse) +MachineFunctionInfo::allocateLocalVar(const Value* val, + unsigned sizeToUse) { assert(! automaticVarsAreaFrozen && "Size of auto vars area has been used to compute an offset so " @@ -273,8 +312,8 @@ int offset = getOffset(val); if (offset == INVALID_FRAME_OFFSET) { - unsigned int getPaddedSize; - offset = computeOffsetforLocalVar(target, val, getPaddedSize, sizeToUse); + unsigned getPaddedSize; + offset = computeOffsetforLocalVar(val, getPaddedSize, sizeToUse); offsets[val] = offset; incrementAutomaticVarsSize(getPaddedSize); } @@ -282,23 +321,22 @@ } int -MachineFunction::allocateSpilledValue(const TargetMachine& target, - const Type* type) +MachineFunctionInfo::allocateSpilledValue(const Type* type) { assert(! spillsAreaFrozen && "Size of reg spills area has been used to compute an offset so " "no more register spill slots should be allocated!"); - unsigned int size = target.DataLayout.getTypeSize(type); - unsigned char align = target.DataLayout.getTypeAlignment(type); + unsigned size = MF.getTarget().getTargetData().getTypeSize(type); + unsigned char align = MF.getTarget().getTargetData().getTypeAlignment(type); bool growUp; - int firstOffset = target.getFrameInfo().getRegSpillAreaOffset(*this, growUp); + int firstOffset = MF.getTarget().getFrameInfo().getRegSpillAreaOffset(MF, growUp); int offset = growUp? firstOffset + getRegSpillsSize() : firstOffset - (getRegSpillsSize() + size); - int aligned = target.getFrameInfo().adjustAlignment(offset, growUp, align); + int aligned = MF.getTarget().getFrameInfo().adjustAlignment(offset, growUp, align); size += abs(aligned - offset); // include alignment padding in size incrementRegSpillsSize(size); // update size of reg. spills area @@ -307,18 +345,18 @@ } int -MachineFunction::pushTempValue(const TargetMachine& target, - unsigned int size) +MachineFunctionInfo::pushTempValue(unsigned size) { - unsigned int align = SizeToAlignment(size, target); + unsigned align = SizeToAlignment(size, MF.getTarget()); bool growUp; - int firstOffset = target.getFrameInfo().getTmpAreaOffset(*this, growUp); + int firstOffset = MF.getTarget().getFrameInfo().getTmpAreaOffset(MF, growUp); int offset = growUp? firstOffset + currentTmpValuesSize : firstOffset - (currentTmpValuesSize + size); - int aligned = target.getFrameInfo().adjustAlignment(offset, growUp, align); + int aligned = MF.getTarget().getFrameInfo().adjustAlignment(offset, growUp, + align); size += abs(aligned - offset); // include alignment padding in size incrementTmpAreaSize(size); // update "current" size of tmp area @@ -326,14 +364,12 @@ return aligned; } -void -MachineFunction::popAllTempValues(const TargetMachine& target) -{ +void MachineFunctionInfo::popAllTempValues() { resetTmpAreaSize(); // clear tmp area to reuse } int -MachineFunction::getOffset(const Value* val) const +MachineFunctionInfo::getOffset(const Value* val) const { hash_map::const_iterator pair = offsets.find(val); return (pair == offsets.end()) ? INVALID_FRAME_OFFSET : pair->second; From lattner at cs.uiuc.edu Sat Dec 28 14:44:00 2002 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Sat Dec 28 14:44:00 2002 Subject: [llvm-commits] CVS: llvm/lib/CodeGen/PrologEpilogInserter.cpp Message-ID: <200212282043.OAA11623@apoc.cs.uiuc.edu> Changes in directory llvm/lib/CodeGen: PrologEpilogInserter.cpp added (r1.1) --- Log message: Initial checkin of Prolog/Epilog code inserter, which is an important part of the abstract frame representation --- Diffs of the changes: From lattner at cs.uiuc.edu Sat Dec 28 14:44:05 2002 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Sat Dec 28 14:44:05 2002 Subject: [llvm-commits] CVS: llvm/lib/CodeGen/Mapping/StackSlots.cpp Message-ID: <200212282043.OAA11614@apoc.cs.uiuc.edu> Changes in directory llvm/lib/CodeGen/Mapping: StackSlots.cpp updated: 1.3 -> 1.4 --- Log message: Put class in anonymous namespace --- Diffs of the changes: Index: llvm/lib/CodeGen/Mapping/StackSlots.cpp diff -u llvm/lib/CodeGen/Mapping/StackSlots.cpp:1.3 llvm/lib/CodeGen/Mapping/StackSlots.cpp:1.4 --- llvm/lib/CodeGen/Mapping/StackSlots.cpp:1.3 Sun Oct 27 18:27:45 2002 +++ llvm/lib/CodeGen/Mapping/StackSlots.cpp Sat Dec 28 14:42:56 2002 @@ -14,30 +14,32 @@ #include "llvm/DerivedTypes.h" #include "llvm/Pass.h" #include "llvm/CodeGen/MachineFunction.h" +#include "llvm/CodeGen/MachineFunctionInfo.h" -class StackSlots : public FunctionPass { - const TargetMachine &Target; -public: - StackSlots (const TargetMachine &T) : Target(T) {} - - const char *getPassName() const { - return "Stack Slot Insertion for profiling code"; - } - - virtual void getAnalysisUsage(AnalysisUsage &AU) const { - AU.setPreservesCFG(); - } - - bool runOnFunction(Function &F) { - const Type *PtrInt = PointerType::get(Type::IntTy); - unsigned Size = Target.DataLayout.getTypeSize(PtrInt); - - MachineFunction &mcInfo = MachineFunction::get(&F); - Value *V = Constant::getNullValue(Type::IntTy); - mcInfo.allocateLocalVar(Target, V, 2*Size); - return true; - } -}; +namespace { + class StackSlots : public FunctionPass { + const TargetMachine &Target; + public: + StackSlots(const TargetMachine &T) : Target(T) {} + + const char *getPassName() const { + return "Stack Slot Insertion for profiling code"; + } + + virtual void getAnalysisUsage(AnalysisUsage &AU) const { + AU.setPreservesCFG(); + } + + bool runOnFunction(Function &F) { + const Type *PtrInt = PointerType::get(Type::IntTy); + unsigned Size = Target.getTargetData().getTypeSize(PtrInt); + + Value *V = Constant::getNullValue(Type::IntTy); + MachineFunction::get(&F).getInfo()->allocateLocalVar(V, 2*Size); + return true; + } + }; +} Pass *createStackSlotsPass(const TargetMachine &Target) { return new StackSlots(Target); From lattner at cs.uiuc.edu Sat Dec 28 15:01:01 2002 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Sat Dec 28 15:01:01 2002 Subject: [llvm-commits] CVS: llvm/lib/CodeGen/MachineFunction.cpp PrologEpilogInserter.cpp Message-ID: <200212282100.PAA13665@apoc.cs.uiuc.edu> Changes in directory llvm/lib/CodeGen: MachineFunction.cpp updated: 1.33 -> 1.34 PrologEpilogInserter.cpp updated: 1.1 -> 1.2 --- Log message: Rename MachineFrameInfo to TargetFrameInfo.h --- Diffs of the changes: Index: llvm/lib/CodeGen/MachineFunction.cpp diff -u llvm/lib/CodeGen/MachineFunction.cpp:1.33 llvm/lib/CodeGen/MachineFunction.cpp:1.34 --- llvm/lib/CodeGen/MachineFunction.cpp:1.33 Sat Dec 28 14:37:16 2002 +++ llvm/lib/CodeGen/MachineFunction.cpp Sat Dec 28 15:00:17 2002 @@ -13,7 +13,7 @@ #include "llvm/CodeGen/MachineFunctionInfo.h" #include "llvm/CodeGen/FunctionFrameInfo.h" #include "llvm/Target/TargetMachine.h" -#include "llvm/Target/MachineFrameInfo.h" +#include "llvm/Target/TargetFrameInfo.h" #include "llvm/Target/MachineCacheInfo.h" #include "llvm/Function.h" #include "llvm/iOther.h" Index: llvm/lib/CodeGen/PrologEpilogInserter.cpp diff -u llvm/lib/CodeGen/PrologEpilogInserter.cpp:1.1 llvm/lib/CodeGen/PrologEpilogInserter.cpp:1.2 --- llvm/lib/CodeGen/PrologEpilogInserter.cpp:1.1 Sat Dec 28 14:43:30 2002 +++ llvm/lib/CodeGen/PrologEpilogInserter.cpp Sat Dec 28 15:00:17 2002 @@ -15,7 +15,7 @@ #include "llvm/CodeGen/FunctionFrameInfo.h" #include "llvm/Target/TargetMachine.h" #include "llvm/Target/MRegisterInfo.h" -#include "llvm/Target/MachineFrameInfo.h" +#include "llvm/Target/TargetFrameInfo.h" #include "llvm/Target/MachineInstrInfo.h" namespace { From lattner at cs.uiuc.edu Sat Dec 28 15:01:06 2002 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Sat Dec 28 15:01:06 2002 Subject: [llvm-commits] CVS: llvm/lib/CodeGen/RegAlloc/PhyRegAlloc.cpp Message-ID: <200212282100.PAA13672@apoc.cs.uiuc.edu> Changes in directory llvm/lib/CodeGen/RegAlloc: PhyRegAlloc.cpp updated: 1.88 -> 1.89 --- Log message: Rename MachineFrameInfo to TargetFrameInfo.h --- Diffs of the changes: Index: llvm/lib/CodeGen/RegAlloc/PhyRegAlloc.cpp diff -u llvm/lib/CodeGen/RegAlloc/PhyRegAlloc.cpp:1.88 llvm/lib/CodeGen/RegAlloc/PhyRegAlloc.cpp:1.89 --- llvm/lib/CodeGen/RegAlloc/PhyRegAlloc.cpp:1.88 Sat Dec 28 14:35:34 2002 +++ llvm/lib/CodeGen/RegAlloc/PhyRegAlloc.cpp Sat Dec 28 15:00:19 2002 @@ -15,7 +15,7 @@ #include "llvm/Analysis/LiveVar/FunctionLiveVarInfo.h" #include "llvm/Analysis/LoopInfo.h" #include "llvm/Target/TargetMachine.h" -#include "llvm/Target/MachineFrameInfo.h" +#include "llvm/Target/TargetFrameInfo.h" #include "llvm/Target/MachineInstrInfo.h" #include "llvm/Function.h" #include "llvm/Type.h" From lattner at cs.uiuc.edu Sat Dec 28 15:01:10 2002 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Sat Dec 28 15:01:10 2002 Subject: [llvm-commits] CVS: llvm/lib/Target/Sparc/SparcInternals.h Message-ID: <200212282100.PAA13679@apoc.cs.uiuc.edu> Changes in directory llvm/lib/Target/Sparc: SparcInternals.h updated: 1.74 -> 1.75 --- Log message: Rename MachineFrameInfo to TargetFrameInfo.h --- Diffs of the changes: Index: llvm/lib/Target/Sparc/SparcInternals.h diff -u llvm/lib/Target/Sparc/SparcInternals.h:1.74 llvm/lib/Target/Sparc/SparcInternals.h:1.75 --- llvm/lib/Target/Sparc/SparcInternals.h:1.74 Sat Dec 28 14:20:24 2002 +++ llvm/lib/Target/Sparc/SparcInternals.h Sat Dec 28 15:00:21 2002 @@ -10,7 +10,7 @@ #include "llvm/Target/TargetMachine.h" #include "llvm/Target/MachineSchedInfo.h" -#include "llvm/Target/MachineFrameInfo.h" +#include "llvm/Target/TargetFrameInfo.h" #include "llvm/Target/MachineCacheInfo.h" #include "llvm/Target/MachineRegInfo.h" #include "llvm/Target/MachineOptInfo.h" From lattner at cs.uiuc.edu Sat Dec 28 15:01:15 2002 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Sat Dec 28 15:01:15 2002 Subject: [llvm-commits] CVS: llvm/lib/Target/X86/X86TargetMachine.h Message-ID: <200212282100.PAA13758@apoc.cs.uiuc.edu> Changes in directory llvm/lib/Target/X86: X86TargetMachine.h updated: 1.6 -> 1.7 --- Log message: Rename MachineFrameInfo to TargetFrameInfo.h --- Diffs of the changes: Index: llvm/lib/Target/X86/X86TargetMachine.h diff -u llvm/lib/Target/X86/X86TargetMachine.h:1.6 llvm/lib/Target/X86/X86TargetMachine.h:1.7 --- llvm/lib/Target/X86/X86TargetMachine.h:1.6 Sat Dec 28 14:33:52 2002 +++ llvm/lib/Target/X86/X86TargetMachine.h Sat Dec 28 15:00:25 2002 @@ -8,8 +8,8 @@ #define X86TARGETMACHINE_H #include "llvm/Target/TargetMachine.h" +#include "llvm/Target/TargetFrameInfo.h" #include "X86InstrInfo.h" -#include "llvm/Target/MachineFrameInfo.h" class X86TargetMachine : public TargetMachine { X86InstrInfo InstrInfo; From lattner at cs.uiuc.edu Sat Dec 28 15:09:02 2002 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Sat Dec 28 15:09:02 2002 Subject: [llvm-commits] CVS: llvm/include/llvm/CodeGen/MachineFrameInfo.h MachineFunction.h Message-ID: <200212282108.PAA15115@apoc.cs.uiuc.edu> Changes in directory llvm/include/llvm/CodeGen: MachineFrameInfo.h updated: 1.1 -> 1.2 MachineFunction.h updated: 1.23 -> 1.24 --- Log message: Rename FunctionFrameInfo to MachineFrameInfo --- Diffs of the changes: Index: llvm/include/llvm/CodeGen/MachineFrameInfo.h diff -u llvm/include/llvm/CodeGen/MachineFrameInfo.h:1.1 llvm/include/llvm/CodeGen/MachineFrameInfo.h:1.2 --- llvm/include/llvm/CodeGen/MachineFrameInfo.h:1.1 Sat Dec 28 14:07:47 2002 +++ llvm/include/llvm/CodeGen/MachineFrameInfo.h Sat Dec 28 15:08:25 2002 @@ -1,6 +1,6 @@ -//===-- CodeGen/FunctionFrameInfo.h - Abstract Stack Frame Rep --*- C++ -*-===// +//===-- CodeGen/MachineFrameInfo.h - Abstract Stack Frame Rep. --*- C++ -*-===// // -// The FunctionFrameInfo class represents an abstract stack frame until +// The MachineFrameInfo class represents an abstract stack frame until // prolog/epilog code is inserted. This class is key to allowing stack frame // representation optimizations, such as frame pointer elimination. It also // allows more mundane (but still important) optimizations, such as reordering @@ -31,7 +31,7 @@ #ifndef LLVM_CODEGEN_FUNCTIONFRAMEINFO_H #define LLVM_CODEGEN_FUNCTIONFRAMEINFO_H -class FunctionFrameInfo { +class MachineFrameInfo { // StackObject - Represent a single object allocated on the stack. struct StackObject { @@ -83,7 +83,7 @@ /// unsigned MaxCallFrameSize; public: - FunctionFrameInfo() { + MachineFrameInfo() { NumFixedObjects = StackSize = 0; HasVarSizedObjects = false; HasCalls = false; @@ -181,7 +181,7 @@ return Objects.size()-NumFixedObjects-1; } - /// CreateVariableSizedObject - Notify the FunctionFrameInfo object that a + /// CreateVariableSizedObject - Notify the MachineFrameInfo object that a /// variable sized object has been created. This must be created whenever a /// variable sized object is created, whether or not the index returned is /// actually used. Index: llvm/include/llvm/CodeGen/MachineFunction.h diff -u llvm/include/llvm/CodeGen/MachineFunction.h:1.23 llvm/include/llvm/CodeGen/MachineFunction.h:1.24 --- llvm/include/llvm/CodeGen/MachineFunction.h:1.23 Sat Dec 28 14:04:31 2002 +++ llvm/include/llvm/CodeGen/MachineFunction.h Sat Dec 28 15:08:25 2002 @@ -20,7 +20,7 @@ class Pass; class SSARegMap; class MachineFunctionInfo; -class FunctionFrameInfo; +class MachineFrameInfo; Pass *createMachineCodeConstructionPass(TargetMachine &Target); Pass *createMachineCodeDestructionPass(); @@ -40,7 +40,7 @@ MachineFunctionInfo *MFInfo; // Keep track of objects allocated on the stack. - FunctionFrameInfo *FrameInfo; + MachineFrameInfo *FrameInfo; public: MachineFunction(const Function *Fn, const TargetMachine& target); @@ -64,7 +64,7 @@ /// This object contains information about objects allocated on the stack /// frame of the current function in an abstract way. /// - FunctionFrameInfo *getFrameInfo() const { return FrameInfo; } + MachineFrameInfo *getFrameInfo() const { return FrameInfo; } /// MachineFunctionInfo - Keep track of various per-function pieces of /// information for the sparc backend. From lattner at cs.uiuc.edu Sat Dec 28 15:09:07 2002 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Sat Dec 28 15:09:07 2002 Subject: [llvm-commits] CVS: llvm/lib/CodeGen/MachineFunction.cpp PrologEpilogInserter.cpp RegAllocLocal.cpp RegAllocSimple.cpp Message-ID: <200212282108.PAA15128@apoc.cs.uiuc.edu> Changes in directory llvm/lib/CodeGen: MachineFunction.cpp updated: 1.34 -> 1.35 PrologEpilogInserter.cpp updated: 1.2 -> 1.3 RegAllocLocal.cpp updated: 1.9 -> 1.10 RegAllocSimple.cpp updated: 1.35 -> 1.36 --- Log message: Rename FunctionFrameInfo to MachineFrameInfo --- Diffs of the changes: Index: llvm/lib/CodeGen/MachineFunction.cpp diff -u llvm/lib/CodeGen/MachineFunction.cpp:1.34 llvm/lib/CodeGen/MachineFunction.cpp:1.35 --- llvm/lib/CodeGen/MachineFunction.cpp:1.34 Sat Dec 28 15:00:17 2002 +++ llvm/lib/CodeGen/MachineFunction.cpp Sat Dec 28 15:08:26 2002 @@ -11,7 +11,7 @@ #include "llvm/CodeGen/MachineCodeForInstruction.h" #include "llvm/CodeGen/SSARegMap.h" #include "llvm/CodeGen/MachineFunctionInfo.h" -#include "llvm/CodeGen/FunctionFrameInfo.h" +#include "llvm/CodeGen/MachineFrameInfo.h" #include "llvm/Target/TargetMachine.h" #include "llvm/Target/TargetFrameInfo.h" #include "llvm/Target/MachineCacheInfo.h" @@ -101,7 +101,7 @@ : Annotation(MF_AID), Fn(F), Target(TM) { SSARegMapping = new SSARegMap(); MFInfo = new MachineFunctionInfo(*this); - FrameInfo = new FunctionFrameInfo(); + FrameInfo = new MachineFrameInfo(); } MachineFunction::~MachineFunction() { @@ -168,10 +168,10 @@ } //===----------------------------------------------------------------------===// -// FunctionFrameInfo implementation +// MachineFrameInfo implementation //===----------------------------------------------------------------------===// -void FunctionFrameInfo::print(std::ostream &OS) const { +void MachineFrameInfo::print(std::ostream &OS) const { for (unsigned i = 0, e = Objects.size(); i != e; ++i) { const StackObject &SO = Objects[i]; OS << " is "; @@ -197,7 +197,7 @@ OS << " Stack frame contains variable sized objects\n"; } -void FunctionFrameInfo::dump() const { print(std::cerr); } +void MachineFrameInfo::dump() const { print(std::cerr); } //===----------------------------------------------------------------------===// Index: llvm/lib/CodeGen/PrologEpilogInserter.cpp diff -u llvm/lib/CodeGen/PrologEpilogInserter.cpp:1.2 llvm/lib/CodeGen/PrologEpilogInserter.cpp:1.3 --- llvm/lib/CodeGen/PrologEpilogInserter.cpp:1.2 Sat Dec 28 15:00:17 2002 +++ llvm/lib/CodeGen/PrologEpilogInserter.cpp Sat Dec 28 15:08:26 2002 @@ -12,7 +12,7 @@ #include "llvm/Pass.h" #include "llvm/CodeGen/MachineFunction.h" #include "llvm/CodeGen/MachineInstr.h" -#include "llvm/CodeGen/FunctionFrameInfo.h" +#include "llvm/CodeGen/MachineFrameInfo.h" #include "llvm/Target/TargetMachine.h" #include "llvm/Target/MRegisterInfo.h" #include "llvm/Target/TargetFrameInfo.h" @@ -114,7 +114,7 @@ ++I; } - FunctionFrameInfo *FFI = Fn.getFrameInfo(); + MachineFrameInfo *FFI = Fn.getFrameInfo(); FFI->setHasCalls(HasCalls); FFI->setMaxCallFrameSize(MaxCallFrameSize); @@ -185,7 +185,7 @@ assert(StackGrowsDown && "Only tested on stack down growing targets!"); // Loop over all of the stack objects, assigning sequential addresses... - FunctionFrameInfo *FFI = Fn.getFrameInfo(); + MachineFrameInfo *FFI = Fn.getFrameInfo(); // Start at the beginning of the local area... int Offset = -TFI.getOffsetOfLocalArea(); Index: llvm/lib/CodeGen/RegAllocLocal.cpp diff -u llvm/lib/CodeGen/RegAllocLocal.cpp:1.9 llvm/lib/CodeGen/RegAllocLocal.cpp:1.10 --- llvm/lib/CodeGen/RegAllocLocal.cpp:1.9 Sat Dec 28 14:40:43 2002 +++ llvm/lib/CodeGen/RegAllocLocal.cpp Sat Dec 28 15:08:26 2002 @@ -8,7 +8,7 @@ #include "llvm/CodeGen/MachineFunctionPass.h" #include "llvm/CodeGen/MachineInstr.h" #include "llvm/CodeGen/SSARegMap.h" -#include "llvm/CodeGen/FunctionFrameInfo.h" +#include "llvm/CodeGen/MachineFrameInfo.h" #include "llvm/Target/MachineInstrInfo.h" #include "llvm/Target/TargetMachine.h" #include "Support/Statistic.h" Index: llvm/lib/CodeGen/RegAllocSimple.cpp diff -u llvm/lib/CodeGen/RegAllocSimple.cpp:1.35 llvm/lib/CodeGen/RegAllocSimple.cpp:1.36 --- llvm/lib/CodeGen/RegAllocSimple.cpp:1.35 Sat Dec 28 14:42:14 2002 +++ llvm/lib/CodeGen/RegAllocSimple.cpp Sat Dec 28 15:08:26 2002 @@ -10,7 +10,7 @@ #include "llvm/CodeGen/MachineFunctionPass.h" #include "llvm/CodeGen/MachineInstr.h" #include "llvm/CodeGen/SSARegMap.h" -#include "llvm/CodeGen/FunctionFrameInfo.h" +#include "llvm/CodeGen/MachineFrameInfo.h" #include "llvm/Target/MachineInstrInfo.h" #include "llvm/Target/TargetMachine.h" #include "Support/Statistic.h" From lattner at cs.uiuc.edu Sat Dec 28 15:09:13 2002 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Sat Dec 28 15:09:13 2002 Subject: [llvm-commits] CVS: llvm/lib/Target/X86/InstSelectSimple.cpp X86RegisterInfo.cpp Message-ID: <200212282108.PAA15137@apoc.cs.uiuc.edu> Changes in directory llvm/lib/Target/X86: InstSelectSimple.cpp updated: 1.79 -> 1.80 X86RegisterInfo.cpp updated: 1.26 -> 1.27 --- Log message: Rename FunctionFrameInfo to MachineFrameInfo --- Diffs of the changes: Index: llvm/lib/Target/X86/InstSelectSimple.cpp diff -u llvm/lib/Target/X86/InstSelectSimple.cpp:1.79 llvm/lib/Target/X86/InstSelectSimple.cpp:1.80 --- llvm/lib/Target/X86/InstSelectSimple.cpp:1.79 Sat Dec 28 14:24:02 2002 +++ llvm/lib/Target/X86/InstSelectSimple.cpp Sat Dec 28 15:08:27 2002 @@ -20,7 +20,7 @@ #include "llvm/CodeGen/MachineFunction.h" #include "llvm/CodeGen/MachineInstrBuilder.h" #include "llvm/CodeGen/SSARegMap.h" -#include "llvm/CodeGen/FunctionFrameInfo.h" +#include "llvm/CodeGen/MachineFrameInfo.h" #include "llvm/Target/TargetMachine.h" #include "llvm/Support/InstVisitor.h" #include "llvm/Target/MRegisterInfo.h" @@ -345,7 +345,7 @@ // ... // unsigned ArgOffset = 0; - FunctionFrameInfo *FFI = F->getFrameInfo(); + MachineFrameInfo *MFI = F->getFrameInfo(); for (Function::aiterator I = Fn.abegin(), E = Fn.aend(); I != E; ++I) { unsigned Reg = getReg(*I); @@ -355,26 +355,26 @@ switch (getClassB(I->getType())) { case cByte: - FI = FFI->CreateFixedObject(1, ArgOffset); + FI = MFI->CreateFixedObject(1, ArgOffset); addFrameReference(BuildMI(BB, X86::MOVmr8, 4, Reg), FI); break; case cShort: - FI = FFI->CreateFixedObject(2, ArgOffset); + FI = MFI->CreateFixedObject(2, ArgOffset); addFrameReference(BuildMI(BB, X86::MOVmr16, 4, Reg), FI); break; case cInt: - FI = FFI->CreateFixedObject(4, ArgOffset); + FI = MFI->CreateFixedObject(4, ArgOffset); addFrameReference(BuildMI(BB, X86::MOVmr32, 4, Reg), FI); break; case cFP: unsigned Opcode; if (I->getType() == Type::FloatTy) { Opcode = X86::FLDr32; - FI = FFI->CreateFixedObject(4, ArgOffset); + FI = MFI->CreateFixedObject(4, ArgOffset); } else { Opcode = X86::FLDr64; ArgOffset += 4; // doubles require 4 additional bytes - FI = FFI->CreateFixedObject(8, ArgOffset); + FI = MFI->CreateFixedObject(8, ArgOffset); } addFrameReference(BuildMI(BB, Opcode, 4, Reg), FI); break; Index: llvm/lib/Target/X86/X86RegisterInfo.cpp diff -u llvm/lib/Target/X86/X86RegisterInfo.cpp:1.26 llvm/lib/Target/X86/X86RegisterInfo.cpp:1.27 --- llvm/lib/Target/X86/X86RegisterInfo.cpp:1.26 Sat Dec 28 14:32:28 2002 +++ llvm/lib/Target/X86/X86RegisterInfo.cpp Sat Dec 28 15:08:28 2002 @@ -12,7 +12,7 @@ #include "llvm/Type.h" #include "llvm/CodeGen/MachineInstrBuilder.h" #include "llvm/CodeGen/MachineFunction.h" -#include "llvm/CodeGen/FunctionFrameInfo.h" +#include "llvm/CodeGen/MachineFrameInfo.h" #include "Support/CommandLine.h" namespace { @@ -139,8 +139,8 @@ int Offset = MF.getFrameInfo()->getObjectOffset(FrameIndex); if (!hasFP(MF) && hasSPAdjust(MF)) { - const FunctionFrameInfo *FFI = MF.getFrameInfo(); - Offset += FFI->getStackSize() + FFI->getMaxCallFrameSize(); + const MachineFrameInfo *MFI = MF.getFrameInfo(); + Offset += MFI->getStackSize() + MFI->getMaxCallFrameSize(); } MI.SetMachineOperandConst(i, MachineOperand::MO_SignExtendedImmed, Offset); @@ -159,15 +159,15 @@ void X86RegisterInfo::emitPrologue(MachineFunction &MF) const { MachineBasicBlock &MBB = MF.front(); // Prolog goes in entry BB MachineBasicBlock::iterator MBBI = MBB.begin(); - const FunctionFrameInfo *FFI = MF.getFrameInfo(); + const MachineFrameInfo *MFI = MF.getFrameInfo(); MachineInstr *MI; // Get the number of bytes to allocate from the FrameInfo - unsigned NumBytes = FFI->getStackSize(); + unsigned NumBytes = MFI->getStackSize(); if (hasFP(MF)) { // Get the offset of the stack slot for the EBP register... which is // guaranteed to be the last slot by processFunctionBeforeFrameFinalized. - int EBPOffset = FFI->getObjectOffset(FFI->getObjectIndexEnd()-1); + int EBPOffset = MFI->getObjectOffset(MFI->getObjectIndexEnd()-1); MI = addRegOffset(BuildMI(X86::MOVrm32, 5), // mov [ESP-], EBP X86::ESP, EBPOffset).addReg(X86::EBP); @@ -187,7 +187,7 @@ // in the function immediately on entry to the current function. This // eliminates the need for add/sub ESP brackets around call sites. // - NumBytes += FFI->getMaxCallFrameSize(); + NumBytes += MFI->getMaxCallFrameSize(); } if (NumBytes) { @@ -199,7 +199,7 @@ void X86RegisterInfo::emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const { - const FunctionFrameInfo *FFI = MF.getFrameInfo(); + const MachineFrameInfo *MFI = MF.getFrameInfo(); MachineBasicBlock::iterator MBBI = MBB.end()-1; MachineInstr *MI; assert((*MBBI)->getOpcode() == X86::RET && @@ -208,7 +208,7 @@ if (hasFP(MF)) { // Get the offset of the stack slot for the EBP register... which is // guaranteed to be the last slot by processFunctionBeforeFrameFinalized. - int EBPOffset = FFI->getObjectOffset(FFI->getObjectIndexEnd()-1); + int EBPOffset = MFI->getObjectOffset(MFI->getObjectIndexEnd()-1); // mov ESP, EBP MI = BuildMI(X86::MOVrr32, 1,X86::ESP).addReg(X86::EBP); @@ -221,8 +221,8 @@ if (!hasSPAdjust(MF)) return; // Get the number of bytes allocated from the FrameInfo... - unsigned NumBytes = FFI->getStackSize(); - NumBytes += FFI->getMaxCallFrameSize(); + unsigned NumBytes = MFI->getStackSize(); + NumBytes += MFI->getMaxCallFrameSize(); if (NumBytes) { // adjust stack pointer back: ESP += numbytes MI =BuildMI(X86::ADDri32, 2, X86::ESP).addReg(X86::ESP).addZImm(NumBytes); From lattner at cs.uiuc.edu Sat Dec 28 20:51:01 2002 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Sat Dec 28 20:51:01 2002 Subject: [llvm-commits] CVS: llvm/lib/CodeGen/MachineFunction.cpp Message-ID: <200212290250.UAA17740@apoc.cs.uiuc.edu> Changes in directory llvm/lib/CodeGen: MachineFunction.cpp updated: 1.35 -> 1.36 --- Log message: Rename MachineOptInfo to TargetoptInfo Rename MachineCacheInfo to TargetCacheInfo --- Diffs of the changes: Index: llvm/lib/CodeGen/MachineFunction.cpp diff -u llvm/lib/CodeGen/MachineFunction.cpp:1.35 llvm/lib/CodeGen/MachineFunction.cpp:1.36 --- llvm/lib/CodeGen/MachineFunction.cpp:1.35 Sat Dec 28 15:08:26 2002 +++ llvm/lib/CodeGen/MachineFunction.cpp Sat Dec 28 20:50:27 2002 @@ -14,7 +14,7 @@ #include "llvm/CodeGen/MachineFrameInfo.h" #include "llvm/Target/TargetMachine.h" #include "llvm/Target/TargetFrameInfo.h" -#include "llvm/Target/MachineCacheInfo.h" +#include "llvm/Target/TargetCacheInfo.h" #include "llvm/Function.h" #include "llvm/iOther.h" #include "llvm/Pass.h" From lattner at cs.uiuc.edu Sat Dec 28 20:51:06 2002 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Sat Dec 28 20:51:06 2002 Subject: [llvm-commits] CVS: llvm/lib/CodeGen/PostOpts/PeepholeOpts.cpp Message-ID: <200212290250.UAA17747@apoc.cs.uiuc.edu> Changes in directory llvm/lib/CodeGen/PostOpts: PeepholeOpts.cpp updated: 1.4 -> 1.5 --- Log message: Rename MachineOptInfo to TargetoptInfo Rename MachineCacheInfo to TargetCacheInfo --- Diffs of the changes: Index: llvm/lib/CodeGen/PostOpts/PeepholeOpts.cpp diff -u llvm/lib/CodeGen/PostOpts/PeepholeOpts.cpp:1.4 llvm/lib/CodeGen/PostOpts/PeepholeOpts.cpp:1.5 --- llvm/lib/CodeGen/PostOpts/PeepholeOpts.cpp:1.4 Mon Oct 28 14:00:31 2002 +++ llvm/lib/CodeGen/PostOpts/PeepholeOpts.cpp Sat Dec 28 20:50:29 2002 @@ -10,7 +10,7 @@ #include "llvm/CodeGen/MachineInstr.h" #include "llvm/Target/TargetMachine.h" #include "llvm/Target/MachineInstrInfo.h" -#include "llvm/Target/MachineOptInfo.h" +#include "llvm/Target/TargetOptInfo.h" #include "llvm/BasicBlock.h" #include "llvm/Pass.h" From lattner at cs.uiuc.edu Sat Dec 28 20:51:10 2002 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Sat Dec 28 20:51:10 2002 Subject: [llvm-commits] CVS: llvm/lib/Target/TargetMachine.cpp Message-ID: <200212290250.UAA17754@apoc.cs.uiuc.edu> Changes in directory llvm/lib/Target: TargetMachine.cpp updated: 1.16 -> 1.17 --- Log message: Rename MachineOptInfo to TargetoptInfo Rename MachineCacheInfo to TargetCacheInfo --- Diffs of the changes: Index: llvm/lib/Target/TargetMachine.cpp diff -u llvm/lib/Target/TargetMachine.cpp:1.16 llvm/lib/Target/TargetMachine.cpp:1.17 --- llvm/lib/Target/TargetMachine.cpp:1.16 Tue Oct 29 15:47:50 2002 +++ llvm/lib/Target/TargetMachine.cpp Sat Dec 28 20:50:31 2002 @@ -1,12 +1,12 @@ //===-- TargetMachine.cpp - General Target Information ---------------------==// // // This file describes the general parts of a Target machine. -// This file also implements MachineCacheInfo. +// This file also implements TargetCacheInfo. // //===----------------------------------------------------------------------===// #include "llvm/Target/TargetMachine.h" -#include "llvm/Target/MachineCacheInfo.h" +#include "llvm/Target/TargetCacheInfo.h" #include "llvm/Type.h" //--------------------------------------------------------------------------- @@ -36,13 +36,13 @@ //--------------------------------------------------------------------------- -// class MachineCacheInfo +// class TargetCacheInfo // // Purpose: // Describes properties of the target cache architecture. //--------------------------------------------------------------------------- -void MachineCacheInfo::Initialize() { +void TargetCacheInfo::Initialize() { numLevels = 2; cacheLineSizes.push_back(16); cacheLineSizes.push_back(32); cacheSizes.push_back(1 << 15); cacheSizes.push_back(1 << 20); From lattner at cs.uiuc.edu Sat Dec 28 20:51:15 2002 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Sat Dec 28 20:51:15 2002 Subject: [llvm-commits] CVS: llvm/lib/Target/Sparc/SparcInternals.h Message-ID: <200212290250.UAA17761@apoc.cs.uiuc.edu> Changes in directory llvm/lib/Target/Sparc: SparcInternals.h updated: 1.75 -> 1.76 --- Log message: Rename MachineOptInfo to TargetoptInfo Rename MachineCacheInfo to TargetCacheInfo --- Diffs of the changes: Index: llvm/lib/Target/Sparc/SparcInternals.h diff -u llvm/lib/Target/Sparc/SparcInternals.h:1.75 llvm/lib/Target/Sparc/SparcInternals.h:1.76 --- llvm/lib/Target/Sparc/SparcInternals.h:1.75 Sat Dec 28 15:00:21 2002 +++ llvm/lib/Target/Sparc/SparcInternals.h Sat Dec 28 20:50:33 2002 @@ -11,9 +11,9 @@ #include "llvm/Target/TargetMachine.h" #include "llvm/Target/MachineSchedInfo.h" #include "llvm/Target/TargetFrameInfo.h" -#include "llvm/Target/MachineCacheInfo.h" +#include "llvm/Target/TargetCacheInfo.h" #include "llvm/Target/MachineRegInfo.h" -#include "llvm/Target/MachineOptInfo.h" +#include "llvm/Target/TargetOptInfo.h" #include "llvm/Type.h" #include @@ -694,9 +694,8 @@ // Just use defaults for now. //--------------------------------------------------------------------------- -class UltraSparcCacheInfo: public MachineCacheInfo { -public: - UltraSparcCacheInfo(const TargetMachine &T) : MachineCacheInfo(T) {} +struct UltraSparcCacheInfo: public TargetCacheInfo { + UltraSparcCacheInfo(const TargetMachine &T) : TargetCacheInfo(T) {} }; @@ -707,9 +706,8 @@ // Interface to machine-level optimization routines for the UltraSPARC. //--------------------------------------------------------------------------- -class UltraSparcOptInfo: public MachineOptInfo { -public: - UltraSparcOptInfo(const TargetMachine &T) : MachineOptInfo(T) {} +struct UltraSparcOptInfo: public TargetOptInfo { + UltraSparcOptInfo(const TargetMachine &T) : TargetOptInfo(T) {} virtual bool IsUselessCopy (const MachineInstr* MI) const; }; @@ -739,8 +737,8 @@ virtual const MachineSchedInfo &getSchedInfo() const { return schedInfo; } virtual const MachineRegInfo &getRegInfo() const { return regInfo; } virtual const TargetFrameInfo &getFrameInfo() const { return frameInfo; } - virtual const MachineCacheInfo &getCacheInfo() const { return cacheInfo; } - virtual const MachineOptInfo &getOptInfo() const { return optInfo; } + virtual const TargetCacheInfo &getCacheInfo() const { return cacheInfo; } + virtual const TargetOptInfo &getOptInfo() const { return optInfo; } virtual bool addPassesToEmitAssembly(PassManager &PM, std::ostream &Out); From lattner at cs.uiuc.edu Sat Dec 28 20:51:20 2002 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Sat Dec 28 20:51:20 2002 Subject: [llvm-commits] CVS: llvm/lib/Target/X86/X86TargetMachine.h Message-ID: <200212290250.UAA17768@apoc.cs.uiuc.edu> Changes in directory llvm/lib/Target/X86: X86TargetMachine.h updated: 1.7 -> 1.8 --- Log message: Rename MachineOptInfo to TargetoptInfo Rename MachineCacheInfo to TargetCacheInfo --- Diffs of the changes: Index: llvm/lib/Target/X86/X86TargetMachine.h diff -u llvm/lib/Target/X86/X86TargetMachine.h:1.7 llvm/lib/Target/X86/X86TargetMachine.h:1.8 --- llvm/lib/Target/X86/X86TargetMachine.h:1.7 Sat Dec 28 15:00:25 2002 +++ llvm/lib/Target/X86/X86TargetMachine.h Sat Dec 28 20:50:35 2002 @@ -25,8 +25,8 @@ virtual const MachineSchedInfo &getSchedInfo() const { abort(); } virtual const MachineRegInfo &getRegInfo() const { abort(); } - virtual const MachineCacheInfo &getCacheInfo() const { abort(); } - virtual const MachineOptInfo &getOptInfo() const { abort(); } + virtual const TargetCacheInfo &getCacheInfo() const { abort(); } + virtual const TargetOptInfo &getOptInfo() const { abort(); } /// addPassesToJITCompile - Add passes to the specified pass manager to /// implement a fast dynamic compiler for this target. Return true if this is From lattner at cs.uiuc.edu Sat Dec 28 20:52:01 2002 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Sat Dec 28 20:52:01 2002 Subject: [llvm-commits] CVS: llvm/include/llvm/Target/TargetCacheInfo.h TargetMachine.h TargetOptInfo.h Message-ID: <200212290251.UAA17794@apoc.cs.uiuc.edu> Changes in directory llvm/include/llvm/Target: TargetCacheInfo.h updated: 1.6 -> 1.7 TargetMachine.h updated: 1.26 -> 1.27 TargetOptInfo.h updated: 1.1 -> 1.2 --- Log message: Rename MachineOptInfo to TargetoptInfo Rename MachineCacheInfo to TargetCacheInfo --- Diffs of the changes: Index: llvm/include/llvm/Target/TargetCacheInfo.h diff -u llvm/include/llvm/Target/TargetCacheInfo.h:1.6 llvm/include/llvm/Target/TargetCacheInfo.h:1.7 --- llvm/include/llvm/Target/TargetCacheInfo.h:1.6 Mon Oct 28 17:53:32 2002 +++ llvm/include/llvm/Target/TargetCacheInfo.h Sat Dec 28 20:50:25 2002 @@ -1,16 +1,16 @@ -//===-- llvm/Target/MachineCacheInfo.h --------------------------*- C++ -*-===// +//===-- llvm/Target/TargetCacheInfo.h ---------------------------*- C++ -*-===// // // Describes properties of the target cache architecture. // //===----------------------------------------------------------------------===// -#ifndef LLVM_TARGET_MACHINECACHEINFO_H -#define LLVM_TARGET_MACHINECACHEINFO_H +#ifndef LLVM_TARGET_TARGETCACHEINFO_H +#define LLVM_TARGET_TARGETCACHEINFO_H #include "Support/DataTypes.h" class TargetMachine; -struct MachineCacheInfo : public NonCopyableV { +struct TargetCacheInfo : public NonCopyableV { const TargetMachine ⌖ protected: unsigned int numLevels; @@ -19,7 +19,7 @@ std::vector cacheAssoc; public: - MachineCacheInfo(const TargetMachine& tgt) : target(tgt) { + TargetCacheInfo(const TargetMachine& tgt) : target(tgt) { Initialize(); } Index: llvm/include/llvm/Target/TargetMachine.h diff -u llvm/include/llvm/Target/TargetMachine.h:1.26 llvm/include/llvm/Target/TargetMachine.h:1.27 --- llvm/include/llvm/Target/TargetMachine.h:1.26 Sat Dec 28 14:13:29 2002 +++ llvm/include/llvm/Target/TargetMachine.h Sat Dec 28 20:50:25 2002 @@ -15,8 +15,8 @@ class MachineSchedInfo; class MachineRegInfo; class TargetFrameInfo; -class MachineCacheInfo; -class MachineOptInfo; +class TargetCacheInfo; +class TargetOptInfo; class MachineCodeEmitter; class MRegisterInfo; class PassManager; @@ -60,8 +60,8 @@ virtual const MachineSchedInfo& getSchedInfo() const = 0; virtual const MachineRegInfo& getRegInfo() const = 0; virtual const TargetFrameInfo& getFrameInfo() const = 0; - virtual const MachineCacheInfo& getCacheInfo() const = 0; - virtual const MachineOptInfo& getOptInfo() const = 0; + virtual const TargetCacheInfo& getCacheInfo() const = 0; + virtual const TargetOptInfo& getOptInfo() const = 0; const TargetData &getTargetData() const { return DataLayout; } /// getRegisterInfo - If register information is available, return it. If Index: llvm/include/llvm/Target/TargetOptInfo.h diff -u llvm/include/llvm/Target/TargetOptInfo.h:1.1 llvm/include/llvm/Target/TargetOptInfo.h:1.2 --- llvm/include/llvm/Target/TargetOptInfo.h:1.1 Thu Sep 19 19:49:21 2002 +++ llvm/include/llvm/Target/TargetOptInfo.h Sat Dec 28 20:50:25 2002 @@ -1,20 +1,19 @@ -//===-- llvm/Target/MachineOptInfo.h -----------------------------*- C++ -*-==// +//===-- llvm/Target/TargetOptInfo.h ------------------------------*- C++ -*-==// // -// Describes properties of the target cache architecture. // //===----------------------------------------------------------------------===// -#ifndef LLVM_TARGET_MACHINEOPTINFO_H -#define LLVM_TARGET_MACHINEOPTINFO_H +#ifndef LLVM_TARGET_TARGETOPTINFO_H +#define LLVM_TARGET_TARGETOPTINFO_H #include "Support/DataTypes.h" class TargetMachine; -struct MachineOptInfo : public NonCopyableV { +struct TargetOptInfo : public NonCopyableV { const TargetMachine ⌖ public: - MachineOptInfo(const TargetMachine& tgt): target(tgt) { } + TargetOptInfo(const TargetMachine& tgt): target(tgt) { } virtual bool IsUselessCopy (const MachineInstr* MI) const = 0; }; From lattner at cs.uiuc.edu Sat Dec 28 21:14:01 2002 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Sat Dec 28 21:14:01 2002 Subject: [llvm-commits] CVS: llvm/lib/CodeGen/InstrSched/InstrScheduling.cpp SchedGraph.cpp SchedPriorities.h Message-ID: <200212290313.VAA19516@apoc.cs.uiuc.edu> Changes in directory llvm/lib/CodeGen/InstrSched: InstrScheduling.cpp updated: 1.48 -> 1.49 SchedGraph.cpp updated: 1.39 -> 1.40 SchedPriorities.h updated: 1.22 -> 1.23 --- Log message: More renamings of Target/Machine*Info to Target/Target*Info --- Diffs of the changes: Index: llvm/lib/CodeGen/InstrSched/InstrScheduling.cpp diff -u llvm/lib/CodeGen/InstrSched/InstrScheduling.cpp:1.48 llvm/lib/CodeGen/InstrSched/InstrScheduling.cpp:1.49 --- llvm/lib/CodeGen/InstrSched/InstrScheduling.cpp:1.48 Mon Oct 28 12:50:08 2002 +++ llvm/lib/CodeGen/InstrSched/InstrScheduling.cpp Sat Dec 28 21:12:55 2002 @@ -340,8 +340,8 @@ class SchedulingManager: public NonCopyable { public: // publicly accessible data members - const unsigned int nslots; - const MachineSchedInfo& schedInfo; + const unsigned nslots; + const TargetSchedInfo& schedInfo; SchedPriorities& schedPrio; InstrSchedule isched; Index: llvm/lib/CodeGen/InstrSched/SchedGraph.cpp diff -u llvm/lib/CodeGen/InstrSched/SchedGraph.cpp:1.39 llvm/lib/CodeGen/InstrSched/SchedGraph.cpp:1.40 --- llvm/lib/CodeGen/InstrSched/SchedGraph.cpp:1.39 Mon Oct 28 12:50:08 2002 +++ llvm/lib/CodeGen/InstrSched/SchedGraph.cpp Sat Dec 28 21:12:55 2002 @@ -10,7 +10,7 @@ #include "llvm/CodeGen/InstrSelection.h" #include "llvm/CodeGen/MachineCodeForInstruction.h" #include "llvm/CodeGen/MachineFunction.h" -#include "llvm/Target/MachineRegInfo.h" +#include "llvm/Target/TargetRegInfo.h" #include "llvm/Target/TargetMachine.h" #include "llvm/Target/MachineInstrInfo.h" #include "llvm/Function.h" Index: llvm/lib/CodeGen/InstrSched/SchedPriorities.h diff -u llvm/lib/CodeGen/InstrSched/SchedPriorities.h:1.22 llvm/lib/CodeGen/InstrSched/SchedPriorities.h:1.23 --- llvm/lib/CodeGen/InstrSched/SchedPriorities.h:1.22 Sat Nov 2 16:07:51 2002 +++ llvm/lib/CodeGen/InstrSched/SchedPriorities.h Sat Dec 28 21:12:55 2002 @@ -15,7 +15,7 @@ #include "SchedGraph.h" #include "llvm/CodeGen/InstrScheduling.h" -#include "llvm/Target/MachineSchedInfo.h" +#include "llvm/Target/TargetSchedInfo.h" #include "Support/hash_set" #include From lattner at cs.uiuc.edu Sat Dec 28 21:14:06 2002 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Sat Dec 28 21:14:06 2002 Subject: [llvm-commits] CVS: llvm/lib/CodeGen/InstrSelection/InstrSelection.cpp InstrSelectionSupport.cpp Message-ID: <200212290313.VAA19525@apoc.cs.uiuc.edu> Changes in directory llvm/lib/CodeGen/InstrSelection: InstrSelection.cpp updated: 1.54 -> 1.55 InstrSelectionSupport.cpp updated: 1.40 -> 1.41 --- Log message: More renamings of Target/Machine*Info to Target/Target*Info --- Diffs of the changes: Index: llvm/lib/CodeGen/InstrSelection/InstrSelection.cpp diff -u llvm/lib/CodeGen/InstrSelection/InstrSelection.cpp:1.54 llvm/lib/CodeGen/InstrSelection/InstrSelection.cpp:1.55 --- llvm/lib/CodeGen/InstrSelection/InstrSelection.cpp:1.54 Fri Nov 8 18:49:16 2002 +++ llvm/lib/CodeGen/InstrSelection/InstrSelection.cpp Sat Dec 28 21:12:57 2002 @@ -12,7 +12,7 @@ #include "llvm/CodeGen/InstrForest.h" #include "llvm/CodeGen/MachineCodeForInstruction.h" #include "llvm/CodeGen/MachineFunction.h" -#include "llvm/Target/MachineRegInfo.h" +#include "llvm/Target/TargetRegInfo.h" #include "llvm/Target/TargetMachine.h" #include "llvm/Function.h" #include "llvm/iPHINode.h" Index: llvm/lib/CodeGen/InstrSelection/InstrSelectionSupport.cpp diff -u llvm/lib/CodeGen/InstrSelection/InstrSelectionSupport.cpp:1.40 llvm/lib/CodeGen/InstrSelection/InstrSelectionSupport.cpp:1.41 --- llvm/lib/CodeGen/InstrSelection/InstrSelectionSupport.cpp:1.40 Tue Oct 29 11:25:41 2002 +++ llvm/lib/CodeGen/InstrSelection/InstrSelectionSupport.cpp Sat Dec 28 21:12:57 2002 @@ -13,7 +13,7 @@ #include "llvm/CodeGen/MachineFunction.h" #include "llvm/CodeGen/InstrForest.h" #include "llvm/Target/TargetMachine.h" -#include "llvm/Target/MachineRegInfo.h" +#include "llvm/Target/TargetRegInfo.h" #include "llvm/Target/MachineInstrInfo.h" #include "llvm/Constants.h" #include "llvm/Function.h" From lattner at cs.uiuc.edu Sat Dec 28 21:14:10 2002 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Sat Dec 28 21:14:10 2002 Subject: [llvm-commits] CVS: llvm/lib/CodeGen/RegAlloc/RegClass.cpp Message-ID: <200212290313.VAA19532@apoc.cs.uiuc.edu> Changes in directory llvm/lib/CodeGen/RegAlloc: RegClass.cpp updated: 1.19 -> 1.20 --- Log message: More renamings of Target/Machine*Info to Target/Target*Info --- Diffs of the changes: Index: llvm/lib/CodeGen/RegAlloc/RegClass.cpp diff -u llvm/lib/CodeGen/RegAlloc/RegClass.cpp:1.19 llvm/lib/CodeGen/RegAlloc/RegClass.cpp:1.20 --- llvm/lib/CodeGen/RegAlloc/RegClass.cpp:1.19 Tue Oct 29 10:51:05 2002 +++ llvm/lib/CodeGen/RegAlloc/RegClass.cpp Sat Dec 28 21:12:58 2002 @@ -14,7 +14,7 @@ // createInterferenceGraph() above. //---------------------------------------------------------------------------- RegClass::RegClass(const Function *M, - const MachineRegClassInfo *Mrc, + const TargetRegClassInfo *Mrc, const ReservedColorListType *RCL) : Meth(M), MRC(Mrc), RegClassID( Mrc->getRegClassID() ), IG(this), IGNodeStack(), ReservedColorList(RCL) { From lattner at cs.uiuc.edu Sat Dec 28 21:14:15 2002 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Sat Dec 28 21:14:15 2002 Subject: [llvm-commits] CVS: llvm/lib/Target/MachineSchedInfo.cpp Message-ID: <200212290313.VAA19539@apoc.cs.uiuc.edu> Changes in directory llvm/lib/Target: MachineSchedInfo.cpp updated: 1.8 -> 1.9 --- Log message: More renamings of Target/Machine*Info to Target/Target*Info --- Diffs of the changes: Index: llvm/lib/Target/MachineSchedInfo.cpp diff -u llvm/lib/Target/MachineSchedInfo.cpp:1.8 llvm/lib/Target/MachineSchedInfo.cpp:1.9 --- llvm/lib/Target/MachineSchedInfo.cpp:1.8 Tue Oct 29 11:37:48 2002 +++ llvm/lib/Target/MachineSchedInfo.cpp Sat Dec 28 21:13:00 2002 @@ -5,7 +5,7 @@ // //===----------------------------------------------------------------------===// -#include "llvm/Target/MachineSchedInfo.h" +#include "llvm/Target/TargetSchedInfo.h" #include "llvm/Target/TargetMachine.h" resourceId_t MachineResource::nextId = 0; @@ -69,17 +69,17 @@ //--------------------------------------------------------------------------- -// class MachineSchedInfo +// class TargetSchedInfo // Interface to machine description for instruction scheduling //--------------------------------------------------------------------------- -MachineSchedInfo::MachineSchedInfo(const TargetMachine& tgt, - int NumSchedClasses, - const InstrClassRUsage* ClassRUsages, - const InstrRUsageDelta* UsageDeltas, - const InstrIssueDelta* IssueDeltas, - unsigned int NumUsageDeltas, - unsigned int NumIssueDeltas) +TargetSchedInfo::TargetSchedInfo(const TargetMachine& tgt, + int NumSchedClasses, + const InstrClassRUsage* ClassRUsages, + const InstrRUsageDelta* UsageDeltas, + const InstrIssueDelta* IssueDeltas, + unsigned NumUsageDeltas, + unsigned NumIssueDeltas) : target(tgt), numSchedClasses(NumSchedClasses), mii(& tgt.getInstrInfo()), classRUsages(ClassRUsages), usageDeltas(UsageDeltas), @@ -88,7 +88,7 @@ {} void -MachineSchedInfo::initializeResources() +TargetSchedInfo::initializeResources() { assert(MAX_NUM_SLOTS >= (int)getMaxNumIssueTotal() && "Insufficient slots for static data! Increase MAX_NUM_SLOTS"); @@ -111,7 +111,7 @@ void -MachineSchedInfo::computeInstrResources(const std::vector& +TargetSchedInfo::computeInstrResources(const std::vector& instrRUForClasses) { int numOpCodes = mii->getNumRealOpCodes(); @@ -141,7 +141,7 @@ void -MachineSchedInfo::computeIssueGaps(const std::vector& +TargetSchedInfo::computeIssueGaps(const std::vector& instrRUForClasses) { int numOpCodes = mii->getNumRealOpCodes(); From lattner at cs.uiuc.edu Sat Dec 28 21:14:20 2002 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Sat Dec 28 21:14:20 2002 Subject: [llvm-commits] CVS: llvm/lib/Target/Sparc/SparcInternals.h SparcOptInfo.cpp SparcRegClassInfo.h SparcRegInfo.cpp UltraSparcSchedInfo.cpp Message-ID: <200212290313.VAA19554@apoc.cs.uiuc.edu> Changes in directory llvm/lib/Target/Sparc: SparcInternals.h updated: 1.76 -> 1.77 SparcOptInfo.cpp updated: 1.4 -> 1.5 SparcRegClassInfo.h updated: 1.14 -> 1.15 SparcRegInfo.cpp updated: 1.82 -> 1.83 UltraSparcSchedInfo.cpp updated: 1.2 -> 1.3 --- Log message: More renamings of Target/Machine*Info to Target/Target*Info --- Diffs of the changes: Index: llvm/lib/Target/Sparc/SparcInternals.h diff -u llvm/lib/Target/Sparc/SparcInternals.h:1.76 llvm/lib/Target/Sparc/SparcInternals.h:1.77 --- llvm/lib/Target/Sparc/SparcInternals.h:1.76 Sat Dec 28 20:50:33 2002 +++ llvm/lib/Target/Sparc/SparcInternals.h Sat Dec 28 21:13:02 2002 @@ -9,10 +9,10 @@ #define SPARC_INTERNALS_H #include "llvm/Target/TargetMachine.h" -#include "llvm/Target/MachineSchedInfo.h" +#include "llvm/Target/TargetSchedInfo.h" #include "llvm/Target/TargetFrameInfo.h" #include "llvm/Target/TargetCacheInfo.h" -#include "llvm/Target/MachineRegInfo.h" +#include "llvm/Target/TargetRegInfo.h" #include "llvm/Target/TargetOptInfo.h" #include "llvm/Type.h" #include @@ -211,11 +211,11 @@ //---------------------------------------------------------------------------- // class UltraSparcRegInfo // -// This class implements the virtual class MachineRegInfo for Sparc. +// This class implements the virtual class TargetRegInfo for Sparc. // //---------------------------------------------------------------------------- -class UltraSparcRegInfo : public MachineRegInfo { +class UltraSparcRegInfo : public TargetRegInfo { // The actual register classes in the Sparc // enum RegClassIDs { @@ -511,7 +511,7 @@ //--------------------------------------------------------------------------- -class UltraSparcSchedInfo: public MachineSchedInfo { +class UltraSparcSchedInfo: public TargetSchedInfo { public: UltraSparcSchedInfo(const TargetMachine &tgt); protected: @@ -734,8 +734,8 @@ UltraSparc(); virtual const MachineInstrInfo &getInstrInfo() const { return instrInfo; } - virtual const MachineSchedInfo &getSchedInfo() const { return schedInfo; } - virtual const MachineRegInfo &getRegInfo() const { return regInfo; } + virtual const TargetSchedInfo &getSchedInfo() const { return schedInfo; } + virtual const TargetRegInfo &getRegInfo() const { return regInfo; } virtual const TargetFrameInfo &getFrameInfo() const { return frameInfo; } virtual const TargetCacheInfo &getCacheInfo() const { return cacheInfo; } virtual const TargetOptInfo &getOptInfo() const { return optInfo; } Index: llvm/lib/Target/Sparc/SparcOptInfo.cpp diff -u llvm/lib/Target/Sparc/SparcOptInfo.cpp:1.4 llvm/lib/Target/Sparc/SparcOptInfo.cpp:1.5 --- llvm/lib/Target/Sparc/SparcOptInfo.cpp:1.4 Sun Oct 27 22:45:29 2002 +++ llvm/lib/Target/Sparc/SparcOptInfo.cpp Sat Dec 28 21:13:02 2002 @@ -5,7 +5,7 @@ //===----------------------------------------------------------------------===// #include "SparcInternals.h" -#include "llvm/Target/MachineRegInfo.h" +#include "llvm/Target/TargetRegInfo.h" #include "llvm/CodeGen/MachineInstr.h" #include Index: llvm/lib/Target/Sparc/SparcRegClassInfo.h diff -u llvm/lib/Target/Sparc/SparcRegClassInfo.h:1.14 llvm/lib/Target/Sparc/SparcRegClassInfo.h:1.15 --- llvm/lib/Target/Sparc/SparcRegClassInfo.h:1.14 Mon Aug 12 16:25:04 2002 +++ llvm/lib/Target/Sparc/SparcRegClassInfo.h Sat Dec 28 21:13:02 2002 @@ -7,7 +7,7 @@ #ifndef SPARC_REG_CLASS_INFO_H #define SPARC_REG_CLASS_INFO_H -#include "llvm/Target/MachineRegInfo.h" +#include "llvm/Target/TargetRegInfo.h" #include "llvm/CodeGen/IGNode.h" //----------------------------------------------------------------------------- @@ -15,9 +15,9 @@ //----------------------------------------------------------------------------- -struct SparcIntRegClass : public MachineRegClassInfo { +struct SparcIntRegClass : public TargetRegClassInfo { SparcIntRegClass(unsigned ID) - : MachineRegClassInfo(ID, NumOfAvailRegs, NumOfAllRegs) { } + : TargetRegClassInfo(ID, NumOfAvailRegs, NumOfAllRegs) { } void colorIGNode(IGNode *Node, std::vector &IsColorUsedArr) const; @@ -73,12 +73,12 @@ // Float Register Class //----------------------------------------------------------------------------- -class SparcFloatRegClass : public MachineRegClassInfo { +class SparcFloatRegClass : public TargetRegClassInfo { int findFloatColor(const LiveRange *LR, unsigned Start, unsigned End, std::vector &IsColorUsedArr) const; public: SparcFloatRegClass(unsigned ID) - : MachineRegClassInfo(ID, NumOfAvailRegs, NumOfAllRegs) {} + : TargetRegClassInfo(ID, NumOfAvailRegs, NumOfAllRegs) {} void colorIGNode(IGNode *Node, std::vector &IsColorUsedArr) const; @@ -119,9 +119,9 @@ // allocated for two names. //----------------------------------------------------------------------------- -struct SparcIntCCRegClass : public MachineRegClassInfo { +struct SparcIntCCRegClass : public TargetRegClassInfo { SparcIntCCRegClass(unsigned ID) - : MachineRegClassInfo(ID, 1, 2) { } + : TargetRegClassInfo(ID, 1, 2) { } void colorIGNode(IGNode *Node, std::vector &IsColorUsedArr) const { if (IsColorUsedArr[0]) @@ -149,9 +149,9 @@ // Only 4 Float CC registers are available //----------------------------------------------------------------------------- -struct SparcFloatCCRegClass : public MachineRegClassInfo { +struct SparcFloatCCRegClass : public TargetRegClassInfo { SparcFloatCCRegClass(unsigned ID) - : MachineRegClassInfo(ID, 4, 4) { } + : TargetRegClassInfo(ID, 4, 4) { } void colorIGNode(IGNode *Node, std::vector &IsColorUsedArr) const { for(unsigned c = 0; c != 4; ++c) Index: llvm/lib/Target/Sparc/SparcRegInfo.cpp diff -u llvm/lib/Target/Sparc/SparcRegInfo.cpp:1.82 llvm/lib/Target/Sparc/SparcRegInfo.cpp:1.83 --- llvm/lib/Target/Sparc/SparcRegInfo.cpp:1.82 Sat Dec 28 14:21:29 2002 +++ llvm/lib/Target/Sparc/SparcRegInfo.cpp Sat Dec 28 21:13:02 2002 @@ -25,7 +25,7 @@ using std::vector; UltraSparcRegInfo::UltraSparcRegInfo(const UltraSparc &tgt) - : MachineRegInfo(tgt), NumOfIntArgRegs(6), + : TargetRegInfo(tgt), NumOfIntArgRegs(6), NumOfFloatArgRegs(32), InvalidRegNum(1000) { MachineRegClassArr.push_back(new SparcIntRegClass(IntRegClassID)); Index: llvm/lib/Target/Sparc/UltraSparcSchedInfo.cpp diff -u llvm/lib/Target/Sparc/UltraSparcSchedInfo.cpp:1.2 llvm/lib/Target/Sparc/UltraSparcSchedInfo.cpp:1.3 --- llvm/lib/Target/Sparc/UltraSparcSchedInfo.cpp:1.2 Wed Aug 21 21:58:57 2002 +++ llvm/lib/Target/Sparc/UltraSparcSchedInfo.cpp Sat Dec 28 21:13:02 2002 @@ -700,12 +700,12 @@ // Purpose: // Scheduling information for the UltraSPARC. // Primarily just initializes machine-dependent parameters in -// class MachineSchedInfo. +// class TargetSchedInfo. //--------------------------------------------------------------------------- /*ctor*/ UltraSparcSchedInfo::UltraSparcSchedInfo(const TargetMachine& tgt) - : MachineSchedInfo(tgt, + : TargetSchedInfo(tgt, (unsigned int) SPARC_NUM_SCHED_CLASSES, SparcRUsageDesc, SparcInstrUsageDeltas, @@ -733,8 +733,8 @@ void UltraSparcSchedInfo::initializeResources() { - // Compute MachineSchedInfo::instrRUsages and MachineSchedInfo::issueGaps - MachineSchedInfo::initializeResources(); + // Compute TargetSchedInfo::instrRUsages and TargetSchedInfo::issueGaps + TargetSchedInfo::initializeResources(); // Machine-dependent fixups go here. None for now. } From lattner at cs.uiuc.edu Sat Dec 28 21:14:25 2002 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Sat Dec 28 21:14:25 2002 Subject: [llvm-commits] CVS: llvm/lib/Target/X86/X86TargetMachine.h Message-ID: <200212290313.VAA19562@apoc.cs.uiuc.edu> Changes in directory llvm/lib/Target/X86: X86TargetMachine.h updated: 1.8 -> 1.9 --- Log message: More renamings of Target/Machine*Info to Target/Target*Info --- Diffs of the changes: Index: llvm/lib/Target/X86/X86TargetMachine.h diff -u llvm/lib/Target/X86/X86TargetMachine.h:1.8 llvm/lib/Target/X86/X86TargetMachine.h:1.9 --- llvm/lib/Target/X86/X86TargetMachine.h:1.8 Sat Dec 28 20:50:35 2002 +++ llvm/lib/Target/X86/X86TargetMachine.h Sat Dec 28 21:13:05 2002 @@ -23,8 +23,8 @@ return &InstrInfo.getRegisterInfo(); } - virtual const MachineSchedInfo &getSchedInfo() const { abort(); } - virtual const MachineRegInfo &getRegInfo() const { abort(); } + virtual const TargetSchedInfo &getSchedInfo() const { abort(); } + virtual const TargetRegInfo &getRegInfo() const { abort(); } virtual const TargetCacheInfo &getCacheInfo() const { abort(); } virtual const TargetOptInfo &getOptInfo() const { abort(); } From lattner at cs.uiuc.edu Sat Dec 28 21:14:30 2002 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Sat Dec 28 21:14:30 2002 Subject: [llvm-commits] CVS: llvm/include/llvm/CodeGen/LiveRangeInfo.h PhyRegAlloc.h RegClass.h Message-ID: <200212290313.VAA19573@apoc.cs.uiuc.edu> Changes in directory llvm/include/llvm/CodeGen: LiveRangeInfo.h updated: 1.14 -> 1.15 PhyRegAlloc.h updated: 1.39 -> 1.40 RegClass.h updated: 1.14 -> 1.15 --- Log message: More renamings of Target/Machine*Info to Target/Target*Info --- Diffs of the changes: Index: llvm/include/llvm/CodeGen/LiveRangeInfo.h diff -u llvm/include/llvm/CodeGen/LiveRangeInfo.h:1.14 llvm/include/llvm/CodeGen/LiveRangeInfo.h:1.15 --- llvm/include/llvm/CodeGen/LiveRangeInfo.h:1.14 Tue Oct 29 11:03:19 2002 +++ llvm/include/llvm/CodeGen/LiveRangeInfo.h Sat Dec 28 21:12:52 2002 @@ -25,7 +25,7 @@ class LiveRange; class MachineInstr; class RegClass; -class MachineRegInfo; +class TargetRegInfo; class TargetMachine; class Value; class Function; @@ -50,7 +50,7 @@ std::vector & RegClassList;// vector containing register classess - const MachineRegInfo& MRI; // machine reg info + const TargetRegInfo& MRI; // machine reg info std::vector CallRetInstrList; // a list of all call/ret instrs Index: llvm/include/llvm/CodeGen/PhyRegAlloc.h diff -u llvm/include/llvm/CodeGen/PhyRegAlloc.h:1.39 llvm/include/llvm/CodeGen/PhyRegAlloc.h:1.40 --- llvm/include/llvm/CodeGen/PhyRegAlloc.h:1.39 Tue Oct 29 11:08:05 2002 +++ llvm/include/llvm/CodeGen/PhyRegAlloc.h Sat Dec 28 21:12:52 2002 @@ -7,9 +7,9 @@ ===== * RegisterClasses: Each RegClass accepts a - MachineRegClass which contains machine specific info about that register + TargetRegClass which contains machine specific info about that register class. The code in the RegClass is machine independent and they use - access functions in the MachineRegClass object passed into it to get + access functions in the TargetRegClass object passed into it to get machine specific info. * Machine dependent work: All parts of the register coloring algorithm @@ -24,7 +24,7 @@ #include class MachineFunction; -class MachineRegInfo; +class TargetRegInfo; class FunctionLiveVarInfo; class MachineInstr; class LoopInfo; @@ -57,7 +57,7 @@ FunctionLiveVarInfo *const LVI; // LV information for this method // (already computed for BBs) LiveRangeInfo LRI; // LR info (will be computed) - const MachineRegInfo &MRI; // Machine Register information + const TargetRegInfo &MRI; // Machine Register information const unsigned NumOfRegClasses; // recorded here for efficiency Index: llvm/include/llvm/CodeGen/RegClass.h diff -u llvm/include/llvm/CodeGen/RegClass.h:1.14 llvm/include/llvm/CodeGen/RegClass.h:1.15 --- llvm/include/llvm/CodeGen/RegClass.h:1.14 Tue Oct 29 10:50:33 2002 +++ llvm/include/llvm/CodeGen/RegClass.h Sat Dec 28 21:12:52 2002 @@ -9,9 +9,9 @@ #define REG_CLASS_H #include "llvm/CodeGen/InterferenceGraph.h" -#include "llvm/Target/MachineRegInfo.h" +#include "llvm/Target/TargetRegInfo.h" #include -class MachineRegClassInfo; +class TargetRegClassInfo; typedef std::vector ReservedColorListType; @@ -24,7 +24,7 @@ // This is the class that contains all data structures and common algos // for coloring a particular register class (e.g., int class, fp class). // This class is hardware independent. This class accepts a hardware -// dependent description of machine registers (MachineRegInfo class) to +// dependent description of machine registers (TargetRegInfo class) to // get hardware specific info and to color an individual IG node. // // This class contains the InterferenceGraph (IG). @@ -35,7 +35,7 @@ //----------------------------------------------------------------------------- class RegClass { const Function *const Meth; // Function we are working on - const MachineRegClassInfo *const MRC; // corresponding MRC + const TargetRegClassInfo *const MRC; // corresponding MRC const unsigned RegClassID; // my int ID InterferenceGraph IG; // Interference graph - constructed by @@ -69,7 +69,7 @@ public: RegClass(const Function *M, - const MachineRegClassInfo *MRC, + const TargetRegClassInfo *MRC, const ReservedColorListType *RCL = 0); inline void createInterferenceGraph() { IG.createGraph(); } From lattner at cs.uiuc.edu Sat Dec 28 21:14:35 2002 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Sat Dec 28 21:14:35 2002 Subject: [llvm-commits] CVS: llvm/include/llvm/Target/TargetMachine.h TargetRegInfo.h TargetSchedInfo.h Message-ID: <200212290313.VAA19582@apoc.cs.uiuc.edu> Changes in directory llvm/include/llvm/Target: TargetMachine.h updated: 1.27 -> 1.28 TargetRegInfo.h updated: 1.29 -> 1.30 TargetSchedInfo.h updated: 1.12 -> 1.13 --- Log message: More renamings of Target/Machine*Info to Target/Target*Info --- Diffs of the changes: Index: llvm/include/llvm/Target/TargetMachine.h diff -u llvm/include/llvm/Target/TargetMachine.h:1.27 llvm/include/llvm/Target/TargetMachine.h:1.28 --- llvm/include/llvm/Target/TargetMachine.h:1.27 Sat Dec 28 20:50:25 2002 +++ llvm/include/llvm/Target/TargetMachine.h Sat Dec 28 21:12:54 2002 @@ -12,8 +12,8 @@ class MachineInstrInfo; class MachineInstrDescriptor; -class MachineSchedInfo; -class MachineRegInfo; +class TargetSchedInfo; +class TargetRegInfo; class TargetFrameInfo; class TargetCacheInfo; class TargetOptInfo; @@ -57,8 +57,8 @@ // -- Machine-level optimization information (peephole only) // virtual const MachineInstrInfo& getInstrInfo() const = 0; - virtual const MachineSchedInfo& getSchedInfo() const = 0; - virtual const MachineRegInfo& getRegInfo() const = 0; + virtual const TargetSchedInfo& getSchedInfo() const = 0; + virtual const TargetRegInfo& getRegInfo() const = 0; virtual const TargetFrameInfo& getFrameInfo() const = 0; virtual const TargetCacheInfo& getCacheInfo() const = 0; virtual const TargetOptInfo& getOptInfo() const = 0; Index: llvm/include/llvm/Target/TargetRegInfo.h diff -u llvm/include/llvm/Target/TargetRegInfo.h:1.29 llvm/include/llvm/Target/TargetRegInfo.h:1.30 --- llvm/include/llvm/Target/TargetRegInfo.h:1.29 Sun Oct 27 20:27:07 2002 +++ llvm/include/llvm/Target/TargetRegInfo.h Sat Dec 28 21:12:54 2002 @@ -1,12 +1,12 @@ -//===-- llvm/Target/RegInfo.h - Target Register Information ------*- C++ -*-==// +//===-- llvm/Target/TargetRegInfo.h - Target Register Info -------*- C++ -*-==// // // This file is used to describe the register system of a target to the // register allocator. // //===----------------------------------------------------------------------===// -#ifndef LLVM_TARGET_MACHINEREGINFO_H -#define LLVM_TARGET_MACHINEREGINFO_H +#ifndef LLVM_TARGET_TARGETREGINFO_H +#define LLVM_TARGET_TARGETREGINFO_H #include "Support/NonCopyable.h" #include "Support/hash_map" @@ -24,17 +24,11 @@ class PhyRegAlloc; class BasicBlock; -//----------------------------------------------------------------------------- -// class MachineRegClassInfo -// -// Purpose: -// Interface to description of machine register class (e.g., int reg class -// float reg class etc) -// -//-------------------------------------------------------------------------- - - -class MachineRegClassInfo { +///---------------------------------------------------------------------------- +/// Interface to description of machine register class (e.g., int reg class +/// float reg class etc) +/// +class TargetRegClassInfo { protected: const unsigned RegClassID; // integer ID of a reg class const unsigned NumOfAvailRegs; // # of avail for coloring -without SP etc. @@ -51,31 +45,26 @@ std::vector &IsColorUsedArr) const = 0; virtual bool isRegVolatile(int Reg) const = 0; - MachineRegClassInfo(unsigned ID, unsigned NVR, unsigned NAR) + TargetRegClassInfo(unsigned ID, unsigned NVR, unsigned NAR) : RegClassID(ID), NumOfAvailRegs(NVR), NumOfAllRegs(NAR) {} }; //--------------------------------------------------------------------------- -// class MachineRegInfo -// -// Purpose: -// Interface to register info of target machine -// -//-------------------------------------------------------------------------- - -class MachineRegInfo : public NonCopyableV { +/// TargetRegInfo - Interface to register info of target machine +/// +class TargetRegInfo : public NonCopyableV { protected: // A vector of all machine register classes // - std::vector MachineRegClassArr; + std::vector MachineRegClassArr; public: const TargetMachine ⌖ - MachineRegInfo(const TargetMachine& tgt) : target(tgt) { } - ~MachineRegInfo() { + TargetRegInfo(const TargetMachine& tgt) : target(tgt) { } + ~TargetRegInfo() { for (unsigned i = 0, e = MachineRegClassArr.size(); i != e; ++i) delete MachineRegClassArr[i]; } @@ -96,7 +85,7 @@ return MachineRegClassArr.size(); } - const MachineRegClassInfo *getMachineRegClass(unsigned i) const { + const TargetRegClassInfo *getMachineRegClass(unsigned i) const { return MachineRegClassArr[i]; } @@ -136,7 +125,7 @@ // The following methods are used to generate "copy" machine instructions - // for an architecture. Currently they are used in MachineRegClass + // for an architecture. Currently they are used in TargetRegClass // interface. However, they can be moved to MachineInstrInfo interface if // necessary. // Index: llvm/include/llvm/Target/TargetSchedInfo.h diff -u llvm/include/llvm/Target/TargetSchedInfo.h:1.12 llvm/include/llvm/Target/TargetSchedInfo.h:1.13 --- llvm/include/llvm/Target/TargetSchedInfo.h:1.12 Mon Oct 28 17:54:23 2002 +++ llvm/include/llvm/Target/TargetSchedInfo.h Sat Dec 28 21:12:54 2002 @@ -1,11 +1,11 @@ -//===- Target/MachineSchedInfo.h - Target Instruction Sched Info -*- C++ -*-==// +//===- Target/TargetSchedInfo.h - Target Instruction Sched Info --*- C++ -*-==// // // This file describes the target machine to the instruction scheduler. // //===----------------------------------------------------------------------===// -#ifndef LLVM_TARGET_MACHINESCHEDINFO_H -#define LLVM_TARGET_MACHINESCHEDINFO_H +#ifndef LLVM_TARGET_TARGETSCHEDINFO_H +#define LLVM_TARGET_TARGETSCHEDINFO_H #include "llvm/Target/MachineInstrInfo.h" #include "Support/hash_map" @@ -164,19 +164,15 @@ feasibleSlots.resize(maxNumSlots); } - friend class MachineSchedInfo; // give access to these functions + friend class TargetSchedInfo; // give access to these functions }; //--------------------------------------------------------------------------- -// class MachineSchedInfo -// -// Purpose: -// Common interface to machine information for instruction scheduling -//--------------------------------------------------------------------------- - -class MachineSchedInfo { -public: +/// TargetSchedInfo - Common interface to machine information for +/// instruction scheduling +/// +struct TargetSchedInfo { const TargetMachine& target; unsigned maxNumIssueTotal; @@ -203,17 +199,17 @@ } private: - MachineSchedInfo(const MachineSchedInfo &); // DO NOT IMPLEMENT - void operator=(const MachineSchedInfo &); // DO NOT IMPLEMENT + TargetSchedInfo(const TargetSchedInfo &); // DO NOT IMPLEMENT + void operator=(const TargetSchedInfo &); // DO NOT IMPLEMENT public: - /*ctor*/ MachineSchedInfo (const TargetMachine& tgt, + /*ctor*/ TargetSchedInfo (const TargetMachine& tgt, int _numSchedClasses, const InstrClassRUsage* _classRUsages, const InstrRUsageDelta* _usageDeltas, const InstrIssueDelta* _issueDeltas, unsigned _numUsageDeltas, unsigned _numIssueDeltas); - /*dtor*/ virtual ~MachineSchedInfo () {} + /*dtor*/ virtual ~TargetSchedInfo() {} inline const MachineInstrInfo& getInstrInfo() const { return *mii;