From lattner at cs.uiuc.edu  Mon Jun  2 00:22:02 2003
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Mon Jun  2 00:22:02 2003
Subject: [llvm-commits] CVS: llvm/lib/Target/TargetData.cpp
Message-ID: <200306020521.AAA25866@apoc.cs.uiuc.edu>


Changes in directory llvm/lib/Target:

TargetData.cpp updated: 1.32 -> 1.33

---
Log message:

Minor cleanups


---
Diffs of the changes:

Index: llvm/lib/Target/TargetData.cpp
diff -u llvm/lib/Target/TargetData.cpp:1.32 llvm/lib/Target/TargetData.cpp:1.33
--- llvm/lib/Target/TargetData.cpp:1.32	Wed May 21 13:08:44 2003
+++ llvm/lib/Target/TargetData.cpp	Mon Jun  2 00:21:06 2003
@@ -195,10 +195,10 @@
       // Get the array index and the size of each array element.
       // Both must be known constants, or the index shd be 0; else this fails.
       int64_t arrayIdx = cast<ConstantSInt>(Idx[CurIDX])->getValue();
-      Result += arrayIdx == 0? 0
-                : (uint64_t) (arrayIdx * (int64_t) getTypeSize(Ty)); 
+      Result += arrayIdx * (int64_t)getTypeSize(Ty);
 
-    } else if (const StructType *STy = dyn_cast<const StructType>(Ty)) {
+    } else {
+      const StructType *STy = cast<StructType>(Ty);
       assert(Idx[CurIDX]->getType() == Type::UByteTy && "Illegal struct idx");
       unsigned FieldNo = cast<ConstantUInt>(Idx[CurIDX])->getValue();
 
@@ -211,9 +211,6 @@
 
       // Update Ty to refer to current element
       Ty = STy->getElementTypes()[FieldNo];
-    } else {
-      assert(0 && "Indexing type that is not struct or array?");
-      return 0;                         // Load directly through ptr
     }
   }
 




From brukman at cs.uiuc.edu  Mon Jun  2 00:25:01 2003
From: brukman at cs.uiuc.edu (Misha Brukman)
Date: Mon Jun  2 00:25:01 2003
Subject: [llvm-commits] CVS: llvm/lib/Target/Sparc/SparcV9CodeEmitter.cpp
Message-ID: <200306020524.AAA09273@zion.cs.uiuc.edu>


Changes in directory llvm/lib/Target/Sparc:

SparcV9CodeEmitter.cpp updated: 1.8 -> 1.9

---
Log message:

Clean up after merging in SparcEmitter.cpp; branches and return work again.


---
Diffs of the changes:

Index: llvm/lib/Target/Sparc/SparcV9CodeEmitter.cpp
diff -u llvm/lib/Target/Sparc/SparcV9CodeEmitter.cpp:1.8 llvm/lib/Target/Sparc/SparcV9CodeEmitter.cpp:1.9
--- llvm/lib/Target/Sparc/SparcV9CodeEmitter.cpp:1.8	Sun Jun  1 23:12:39 2003
+++ llvm/lib/Target/Sparc/SparcV9CodeEmitter.cpp	Mon Jun  2 00:24:46 2003
@@ -184,7 +184,27 @@
   int64_t rv = 0; // Return value; defaults to 0 for unhandled cases
                   // or things that get fixed up later by the JIT.
 
-  if (MO.isPhysicalRegister()) {
+  if (MO.isVirtualRegister()) {
+    std::cerr << "ERROR: virtual register found in machine code.\n";
+    abort();
+  } else if (MO.isPCRelativeDisp()) {
+    Value *V = MO.getVRegValue();
+    if (BasicBlock *BB = dyn_cast<BasicBlock>(V)) {
+      std::cerr << "Saving reference to BB (VReg)\n";
+      unsigned* CurrPC = (unsigned*)(intptr_t)MCE->getCurrentPCValue();
+      BBRefs.push_back(std::make_pair(BB, std::make_pair(CurrPC, &MI)));
+    } else if (Constant *C = dyn_cast<Constant>(V)) {
+      if (ConstantMap.find(C) != ConstantMap.end())
+        rv = (int64_t)(intptr_t)ConstantMap[C];
+      else {
+        std::cerr << "ERROR: constant not in map:" << MO << "\n";
+        abort();
+      }
+    } else {
+      std::cerr << "ERROR: PC relative disp unhandled:" << MO << "\n";
+      abort();
+    }
+  } else if (MO.isPhysicalRegister()) {
     // This is necessary because the Sparc doesn't actually lay out registers
     // in the real fashion -- it skips those that it chooses not to allocate,
     // i.e. those that are the SP, etc.
@@ -198,25 +218,33 @@
     rv = realReg;
   } else if (MO.isImmediate()) {
     rv = MO.getImmedValue();
-  } else if (MO.isPCRelativeDisp()) { // this is not always a call!! (fp const)
-    std::cerr << "Saving reference to func (call - PCRelDisp)\n";
+  } else if (MO.isGlobalAddress()) {
     rv = (int64_t)
       (intptr_t)getGlobalAddress(cast<GlobalValue>(MO.getVRegValue()),
-                                 MI,true);
+                                 MI, MO.isPCRelative());
   } else if (MO.isMachineBasicBlock()) {
+    // Duplicate code of the above case for VirtualRegister, BasicBlock... 
+    // It should really hit this case, but Sparc backend uses VRegs instead
     std::cerr << "Saving reference to MBB\n";
-    BBRefs.push_back(std::make_pair(MO.getMachineBasicBlock()->getBasicBlock(),
-            std::make_pair((unsigned*)(intptr_t)MCE->getCurrentPCValue(),&MI)));
+    BasicBlock *BB = MO.getMachineBasicBlock()->getBasicBlock();
+    unsigned* CurrPC = (unsigned*)(intptr_t)MCE->getCurrentPCValue();
+    BBRefs.push_back(std::make_pair(BB, std::make_pair(CurrPC, &MI)));
+  } else if (MO.isExternalSymbol()) {
+    // Sparc backend doesn't generate this (yet...)
+    std::cerr << "ERROR: External symbol unhandled: " << MO << "\n";
+    abort();
   } else if (MO.isFrameIndex()) {
+    // Sparc backend doesn't generate this (yet...)
+    int FrameIndex = MO.getFrameIndex();
     std::cerr << "ERROR: Frame index unhandled.\n";
+    abort();
   } else if (MO.isConstantPoolIndex()) {
+    // Sparc backend doesn't generate this (yet...)
     std::cerr << "ERROR: Constant Pool index unhandled.\n";
-  } else if (MO.isGlobalAddress()) {
-    std::cerr << "ERROR: Global addr unhandled.\n";
-  } else if (MO.isExternalSymbol()) {
-    std::cerr << "ERROR: External symbol unhandled.\n";
+    abort();
   } else {
     std::cerr << "ERROR: Unknown type of MachineOperand: " << MO << "\n";
+    abort();
   }
 
   // Finally, deal with the various bitfield-extracting functions that
@@ -357,7 +385,8 @@
         TheJITResolver->addFunctionReference(MCE->getCurrentPCValue(),
                                              cast<Function>(V));
         // Delayed resolution...
-        return (void*)TheJITResolver->getLazyResolver(cast<Function>(V));
+        return 
+          (void*)(intptr_t)TheJITResolver->getLazyResolver(cast<Function>(V));
 
       } else if (Constant *C = ConstantPointerRef::get(V)) {
         if (ConstantMap.find(C) != ConstantMap.end()) {




From lattner at cs.uiuc.edu  Mon Jun  2 00:43:01 2003
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Mon Jun  2 00:43:01 2003
Subject: [llvm-commits] CVS: llvm/test/Regression/Transforms/BasicAA/2003-06-01-AliasCrash.ll
Message-ID: <200306020542.AAA26312@apoc.cs.uiuc.edu>


Changes in directory llvm/test/Regression/Transforms/BasicAA:

2003-06-01-AliasCrash.ll updated: 1.1 -> 1.2

---
Log message:

No need to print out bytecode :)


---
Diffs of the changes:

Index: llvm/test/Regression/Transforms/BasicAA/2003-06-01-AliasCrash.ll
diff -u llvm/test/Regression/Transforms/BasicAA/2003-06-01-AliasCrash.ll:1.1 llvm/test/Regression/Transforms/BasicAA/2003-06-01-AliasCrash.ll:1.2
--- llvm/test/Regression/Transforms/BasicAA/2003-06-01-AliasCrash.ll:1.1	Sun Jun  1 23:58:23 2003
+++ llvm/test/Regression/Transforms/BasicAA/2003-06-01-AliasCrash.ll	Mon Jun  2 00:42:16 2003
@@ -1,4 +1,4 @@
-; RUN: as < %s | opt -basicaa -aa-eval
+; RUN: as < %s | opt -basicaa -aa-eval -disable-output
 
 int %MTConcat([3 x int]* %a.1) {
 	%tmp.961 = getelementptr [3 x int]* %a.1, long 0, long 4




From lattner at cs.uiuc.edu  Mon Jun  2 00:43:03 2003
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Mon Jun  2 00:43:03 2003
Subject: [llvm-commits] CVS: llvm/lib/Analysis/BasicAliasAnalysis.cpp
Message-ID: <200306020542.AAA26353@apoc.cs.uiuc.edu>


Changes in directory llvm/lib/Analysis:

BasicAliasAnalysis.cpp updated: 1.9 -> 1.10

---
Log message:

Be more robust in the face of undefined behavior.
Fixes bug: BasicAA/2003-06-01-AliasCrash.ll


---
Diffs of the changes:

Index: llvm/lib/Analysis/BasicAliasAnalysis.cpp
diff -u llvm/lib/Analysis/BasicAliasAnalysis.cpp:1.9 llvm/lib/Analysis/BasicAliasAnalysis.cpp:1.10
--- llvm/lib/Analysis/BasicAliasAnalysis.cpp:1.9	Wed May 21 15:23:26 2003
+++ llvm/lib/Analysis/BasicAliasAnalysis.cpp	Mon Jun  2 00:42:39 2003
@@ -182,6 +182,22 @@
   return MayAlias;
 }
 
+static Value *CheckArrayIndicesForOverflow(const Type *PtrTy,
+                                           const std::vector<Value*> &Indices,
+                                           const ConstantInt *Idx) {
+  if (const ConstantSInt *IdxS = dyn_cast<ConstantSInt>(Idx)) {
+    if (IdxS->getValue() < 0)   // Underflow on the array subscript?
+      return Constant::getNullValue(Type::LongTy);
+    else {                       // Check for overflow
+      const ArrayType *ATy =
+        cast<ArrayType>(GetElementPtrInst::getIndexedType(PtrTy, Indices,true));
+      if (IdxS->getValue() >= (int64_t)ATy->getNumElements())
+        return ConstantSInt::get(Type::LongTy, ATy->getNumElements()-1);
+    }
+  }
+  return (Value*)Idx;  // Everything is acceptable.
+}
+
 // CheckGEPInstructions - Check two GEP instructions of compatible types and
 // equal number of arguments.  This checks to see if the index expressions
 // preclude the pointers from aliasing...
@@ -214,7 +230,7 @@
   //
   unsigned SizeMax = std::max(G1S, G2S);
   if (SizeMax == ~0U) return MayAlias; // Avoid frivolous work...
-      
+
   // Scan for the first operand that is constant and unequal in the
   // two getelemenptrs...
   unsigned FirstConstantOper = UnequalOper;
@@ -262,16 +278,20 @@
   const Type *GEPPointerTy = GEP1->getOperand(0)->getType();
   
   // Loop over the rest of the operands...
-  for (unsigned i = FirstConstantOper+1; i!=NumGEPOperands; ++i){
+  for (unsigned i = FirstConstantOper+1; i != NumGEPOperands; ++i) {
     const Value *Op1 = GEP1->getOperand(i);
     const Value *Op2 = GEP2->getOperand(i);
     if (Op1 == Op2) {   // If they are equal, use a zero index...
       Indices1.push_back(Constant::getNullValue(Op1->getType()));
       Indices2.push_back(Indices1.back());
     } else {
-      if (isa<Constant>(Op1))
+      if (const ConstantInt *Op1C = dyn_cast<ConstantInt>(Op1)) {
+        // If this is an array index, make sure the array element is in range...
+        if (i != 1)   // The pointer index can be "out of range"
+          Op1 = CheckArrayIndicesForOverflow(GEPPointerTy, Indices1, Op1C);
+
         Indices1.push_back((Value*)Op1);
-      else {
+      } else {
         // GEP1 is known to produce a value less than GEP2.  To be
         // conservatively correct, we must assume the largest possible constant
         // is used in this position.  This cannot be the initial index to the
@@ -287,8 +307,13 @@
                                              ElTy->getNumElements()-1));
       }
       
-      if (isa<Constant>(Op2))
+      if (const ConstantInt *Op1C = dyn_cast<ConstantInt>(Op2)) {
+        // If this is an array index, make sure the array element is in range...
+        if (i != 1)   // The pointer index can be "out of range"
+          Op1 = CheckArrayIndicesForOverflow(GEPPointerTy, Indices2, Op1C);
+
         Indices2.push_back((Value*)Op2);
+      }
       else // Conservatively assume the minimum value for this index
         Indices2.push_back(Constant::getNullValue(Op2->getType()));
     }




From lattner at cs.uiuc.edu  Mon Jun  2 00:49:01 2003
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Mon Jun  2 00:49:01 2003
Subject: [llvm-commits] CVS: llvm/test/Programs/External/SPEC/CINT2000/255.vortex/Makefile
Message-ID: <200306020548.AAA26466@apoc.cs.uiuc.edu>


Changes in directory llvm/test/Programs/External/SPEC/CINT2000/255.vortex:

Makefile updated: 1.1 -> 1.2

---
Log message:

Configure run parameters


---
Diffs of the changes:

Index: llvm/test/Programs/External/SPEC/CINT2000/255.vortex/Makefile
diff -u llvm/test/Programs/External/SPEC/CINT2000/255.vortex/Makefile:1.1 llvm/test/Programs/External/SPEC/CINT2000/255.vortex/Makefile:1.2
--- llvm/test/Programs/External/SPEC/CINT2000/255.vortex/Makefile:1.1	Thu May 22 12:29:23 2003
+++ llvm/test/Programs/External/SPEC/CINT2000/255.vortex/Makefile	Mon Jun  2 00:48:35 2003
@@ -1,4 +1,4 @@
 LEVEL = ../../../../../..
-#RUN_OPTIONS     = `cat $(REF_IN_DIR)control`
+RUN_OPTIONS     = lendian.raw
 #STDOUT_FILENAME := input.random.out
 include ../../Makefile.spec




From lattner at cs.uiuc.edu  Mon Jun  2 00:50:01 2003
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Mon Jun  2 00:50:01 2003
Subject: [llvm-commits] CVS: llvm/test/Makefile.tests
Message-ID: <200306020549.AAA26496@apoc.cs.uiuc.edu>


Changes in directory llvm/test:

Makefile.tests updated: 1.58 -> 1.59

---
Log message:

Add support for C++ tests


---
Diffs of the changes:

Index: llvm/test/Makefile.tests
diff -u llvm/test/Makefile.tests:1.58 llvm/test/Makefile.tests:1.59
--- llvm/test/Makefile.tests:1.58	Sat May 17 17:33:18 2003
+++ llvm/test/Makefile.tests	Mon Jun  2 00:49:09 2003
@@ -87,6 +87,10 @@
 Output/%.ll: $(SourceDir)%.cpp $(LCC1XX) Output/.dir $(INCLUDES)
 	$(LCXX) $(CPPFLAGS) $(LCXXFLAGS) -S $< -o $@
 
+# Compile from X.cc to Output/X.ll
+Output/%.ll: $(SourceDir)%.cc $(LCC1XX) Output/.dir $(INCLUDES)
+	$(LCXX) $(CPPFLAGS) $(LCXXFLAGS) -S $< -o $@
+
 # LLVM Assemble from Output/X.ll to Output/X.bc.  Output/X.ll must have come
 # from GCC output, so use GCCAS.
 #




From lattner at cs.uiuc.edu  Mon Jun  2 00:50:03 2003
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Mon Jun  2 00:50:03 2003
Subject: [llvm-commits] CVS: llvm/test/Programs/External/SPEC/Makefile.spec
Message-ID: <200306020549.AAA26519@apoc.cs.uiuc.edu>


Changes in directory llvm/test/Programs/External/SPEC:

Makefile.spec updated: 1.7 -> 1.8

---
Log message:

Add support for C++ tests



---
Diffs of the changes:

Index: llvm/test/Programs/External/SPEC/Makefile.spec
diff -u llvm/test/Programs/External/SPEC/Makefile.spec:1.7 llvm/test/Programs/External/SPEC/Makefile.spec:1.8
--- llvm/test/Programs/External/SPEC/Makefile.spec:1.7	Sat May 31 18:16:52 2003
+++ llvm/test/Programs/External/SPEC/Makefile.spec	Mon Jun  2 00:49:10 2003
@@ -31,7 +31,7 @@
 SPEC_BENCH_DIR := $(SPEC_ROOT)/$(SPEC_SUBDIR)
 
 PROG := $(BENCH_NAME)
-Source := $(wildcard $(SPEC_BENCH_DIR)/src/*.c)
+Source := $(wildcard $(SPEC_BENCH_DIR)/src/*.c $(SPEC_BENCH_DIR)/src/*.cc) \
 
 # Disable the default Output/%.out-* targets...
 PROGRAMS_HAVE_CUSTOM_RUN_RULES := 1




From lattner at cs.uiuc.edu  Mon Jun  2 00:50:05 2003
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Mon Jun  2 00:50:05 2003
Subject: [llvm-commits] CVS: llvm/test/Programs/MultiSource/Makefile.multisrc
Message-ID: <200306020549.AAA26537@apoc.cs.uiuc.edu>


Changes in directory llvm/test/Programs/MultiSource:

Makefile.multisrc updated: 1.30 -> 1.31

---
Log message:

Add support for C++ tests


---
Diffs of the changes:

Index: llvm/test/Programs/MultiSource/Makefile.multisrc
diff -u llvm/test/Programs/MultiSource/Makefile.multisrc:1.30 llvm/test/Programs/MultiSource/Makefile.multisrc:1.31
--- llvm/test/Programs/MultiSource/Makefile.multisrc:1.30	Sat May 31 17:24:41 2003
+++ llvm/test/Programs/MultiSource/Makefile.multisrc	Mon Jun  2 00:49:11 2003
@@ -37,6 +37,9 @@
 Output/%.o: $(SourceDir)%.cpp Output/.dir
 	$(CC) $(CPPFLAGS) $(CXXFLAGS) -c $< -o $@
 
+Output/%.o: $(SourceDir)%.cc Output/.dir
+	$(CC) $(CPPFLAGS) $(CXXFLAGS) -c $< -o $@
+
 bugpoint-gccas: Output/$(PROG).bugpoint-gccas
 bugpoint-gccld: Output/$(PROG).bugpoint-gccld
 




From lattner at cs.uiuc.edu  Mon Jun  2 12:09:30 2003
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Mon Jun  2 12:09:30 2003
Subject: [llvm-commits] CVS: llvm/test/Regression/Linker/2003-06-02-TypeResolveProblem.ll
Message-ID: <200306021707.MAA11157@apoc.cs.uiuc.edu>


Changes in directory llvm/test/Regression/Linker:

2003-06-02-TypeResolveProblem.ll added (r1.1)

---
Log message:

New testcase identified by Joel


---
Diffs of the changes:

Index: llvm/test/Regression/Linker/2003-06-02-TypeResolveProblem.ll
diff -c /dev/null llvm/test/Regression/Linker/2003-06-02-TypeResolveProblem.ll:1.1
*** /dev/null	Mon Jun  2 12:07:52 2003
--- llvm/test/Regression/Linker/2003-06-02-TypeResolveProblem.ll	Mon Jun  2 12:07:42 2003
***************
*** 0 ****
--- 1,7 ----
+ ; RUN: echo "%T = type opaque" | as > Output/%s.2.bc
+ ; RUN: as < %s > Output/%s.1.bc
+ ; RUN: link Output/%s.[12].bc
+ 
+ %T = type opaque
+ %a = constant { %T* }  { %T* null }
+ 




From lattner at cs.uiuc.edu  Mon Jun  2 12:26:01 2003
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Mon Jun  2 12:26:01 2003
Subject: [llvm-commits] CVS: llvm/lib/VMCore/Constants.cpp
Message-ID: <200306021725.MAA11509@apoc.cs.uiuc.edu>


Changes in directory llvm/lib/VMCore:

Constants.cpp updated: 1.42 -> 1.43

---
Log message:

Fix bug: Linker/2003-06-02-TypeResolveProblem.ll


---
Diffs of the changes:

Index: llvm/lib/VMCore/Constants.cpp
diff -u llvm/lib/VMCore/Constants.cpp:1.42 llvm/lib/VMCore/Constants.cpp:1.43
--- llvm/lib/VMCore/Constants.cpp:1.42	Sun May 25 11:15:32 2003
+++ llvm/lib/VMCore/Constants.cpp	Mon Jun  2 12:25:46 2003
@@ -556,6 +556,7 @@
 void ConstantArray::refineAbstractType(const DerivedType *OldTy,
                                        const Type *NewTy) {
   Value::refineAbstractType(OldTy, NewTy);
+  if (OldTy == NewTy) return;
 
   // Make everyone now use a constant of the new type...
   std::vector<Constant*> C;
@@ -625,6 +626,7 @@
 void ConstantStruct::refineAbstractType(const DerivedType *OldTy,
                                         const Type *NewTy) {
   Value::refineAbstractType(OldTy, NewTy);
+  if (OldTy == NewTy) return;
 
   // Make everyone now use a constant of the new type...
   std::vector<Constant*> C;
@@ -666,6 +668,7 @@
 void ConstantPointerNull::refineAbstractType(const DerivedType *OldTy,
                                              const Type *NewTy) {
   Value::refineAbstractType(OldTy, NewTy);
+  if (OldTy == NewTy) return;
 
   // Make everyone now use a constant of the new type...
   if (NewTy != OldTy) {
@@ -798,6 +801,7 @@
 void ConstantExpr::refineAbstractType(const DerivedType *OldTy,
                                       const Type *NewTy) {
   Value::refineAbstractType(OldTy, NewTy);
+  if (OldTy == NewTy) return;
 
   // FIXME: These need to use a lower-level implementation method, because the
   // ::get methods intuit the type of the result based on the types of the




From lattner at cs.uiuc.edu  Mon Jun  2 12:32:01 2003
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Mon Jun  2 12:32:01 2003
Subject: [llvm-commits] CVS: llvm/test/Regression/Linker/2003-06-02-TypeResolveProblem2.ll
Message-ID: <200306021731.MAA11586@apoc.cs.uiuc.edu>


Changes in directory llvm/test/Regression/Linker:

2003-06-02-TypeResolveProblem2.ll added (r1.1)

---
Log message:

Second testcase identified by Joel


---
Diffs of the changes:

Index: llvm/test/Regression/Linker/2003-06-02-TypeResolveProblem2.ll
diff -c /dev/null llvm/test/Regression/Linker/2003-06-02-TypeResolveProblem2.ll:1.1
*** /dev/null	Mon Jun  2 12:31:34 2003
--- llvm/test/Regression/Linker/2003-06-02-TypeResolveProblem2.ll	Mon Jun  2 12:31:24 2003
***************
*** 0 ****
--- 1,8 ----
+ ; RUN: echo "%T = type int" | as > Output/%s.1.bc
+ ; RUN: as < %s > Output/%s.2.bc
+ ; RUN: link Output/%s.[12].bc
+ 
+ %T = type opaque
+ 
+ %X = constant {%T*} {%T* null }
+ 




From lattner at cs.uiuc.edu  Mon Jun  2 12:43:01 2003
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Mon Jun  2 12:43:01 2003
Subject: [llvm-commits] CVS: llvm/lib/VMCore/Constants.cpp
Message-ID: <200306021742.MAA11687@apoc.cs.uiuc.edu>


Changes in directory llvm/lib/VMCore:

Constants.cpp updated: 1.43 -> 1.44

---
Log message:

* Make assertion message useful
* Kill dead conditional


---
Diffs of the changes:

Index: llvm/lib/VMCore/Constants.cpp
diff -u llvm/lib/VMCore/Constants.cpp:1.43 llvm/lib/VMCore/Constants.cpp:1.44
--- llvm/lib/VMCore/Constants.cpp:1.43	Mon Jun  2 12:25:46 2003
+++ llvm/lib/VMCore/Constants.cpp	Mon Jun  2 12:42:47 2003
@@ -225,7 +225,8 @@
          "Invalid initializer vector for constant structure");
   Operands.reserve(V.size());
   for (unsigned i = 0, e = V.size(); i != e; ++i) {
-    assert(V[i]->getType() == ETypes[i]);
+    assert(V[i]->getType() == ETypes[i] &&
+           "Initializer for struct element doesn't match struct element type!");
     Operands.push_back(Use(V[i], this));
   }
 }
@@ -671,12 +672,10 @@
   if (OldTy == NewTy) return;
 
   // Make everyone now use a constant of the new type...
-  if (NewTy != OldTy) {
-    replaceAllUsesWith(ConstantPointerNull::get(cast<PointerType>(NewTy)));
+  replaceAllUsesWith(ConstantPointerNull::get(cast<PointerType>(NewTy)));
     
-    // This constant is now dead, destroy it.
-    destroyConstant();
-  }
+  // This constant is now dead, destroy it.
+  destroyConstant();
 }
 
 




From gshi1 at cs.uiuc.edu  Mon Jun  2 12:50:01 2003
From: gshi1 at cs.uiuc.edu (Guochun Shi)
Date: Mon Jun  2 12:50:01 2003
Subject: [llvm-commits] CVS: llvm/lib/CodeGen/ModuloScheduling/ModuloSchedGraph.cpp ModuloSchedGraph.h ModuloScheduling.h
Message-ID: <200306021749.MAA02432@psmith.cs.uiuc.edu>


Changes in directory llvm/lib/CodeGen/ModuloScheduling:

ModuloSchedGraph.cpp updated: 1.5 -> 1.6
ModuloSchedGraph.h updated: 1.5 -> 1.6
ModuloScheduling.h updated: 1.5 -> 1.6

---
Log message:

compiled with the new SchedGraphCommon


---
Diffs of the changes:

Index: llvm/lib/CodeGen/ModuloScheduling/ModuloSchedGraph.cpp
diff -u llvm/lib/CodeGen/ModuloScheduling/ModuloSchedGraph.cpp:1.5 llvm/lib/CodeGen/ModuloScheduling/ModuloSchedGraph.cpp:1.6
--- llvm/lib/CodeGen/ModuloScheduling/ModuloSchedGraph.cpp:1.5	Tue Apr 22 18:00:08 2003
+++ llvm/lib/CodeGen/ModuloScheduling/ModuloSchedGraph.cpp	Mon Jun  2 12:48:56 2003
@@ -50,12 +50,12 @@
 
 // class Modulo SchedGraphNode
 
-ModuloSchedGraphNode::ModuloSchedGraphNode(unsigned int _nodeId,
-                                           const BasicBlock * _bb,
-                                           const Instruction * _inst,
+ModuloSchedGraphNode::ModuloSchedGraphNode(unsigned int in_nodeId,
+                                           const BasicBlock * in_bb,
+                                           const Instruction * in_inst,
                                            int indexInBB,
                                            const TargetMachine & target)
-:SchedGraphNodeCommon(_nodeId, _bb, indexInBB), inst(_inst)
+:SchedGraphNodeCommon(in_nodeId, indexInBB), inst(in_inst)
 {
   if (inst) {
     //FIXME: find the latency 
@@ -298,8 +298,7 @@
   //only if the last instruction in the basicblock is branch instruction and 
   //there is at least an option to branch itself
 
-  assert(bbVec.size() == 1 && "only 1 basicblock in a graph");
-  const BasicBlock *bb = bbVec[0];
+  assert(this->bb&& "the basicblock is not empty");
   const Instruction *inst = &(bb->back());
   if (BranchInst::classof(inst))
     for (unsigned i = 0; i < ((BranchInst *) inst)->getNumSuccessors();
@@ -308,7 +307,7 @@
       if (sb == bb)
         return true;
     }
-
+  
   return false;
 
 }
@@ -674,7 +673,6 @@
   oNodes.clear();
 
   std::vector < ModuloSchedGraphNode * >set;
-  const BasicBlock *bb = bbVec[0];
   unsigned numNodes = bb->size();
 
   // first order all the sets
@@ -873,9 +871,8 @@
 
 void ModuloSchedGraph::buildGraph(const TargetMachine & target)
 {
-  const BasicBlock *bb = bbVec[0];
 
-  assert(bbVec.size() == 1 && "only handling a single basic block here");
+  assert(this->bb && "The basicBlock is NULL?");
 
   // Use this data structure to note all machine operands that compute
   // ordinary LLVM values.  These must be computed defs (i.e., instructions). 
@@ -1277,10 +1274,9 @@
 void ModuloSchedGraph::dump() const
 {
   DEBUG(std::cerr << " ModuloSchedGraph for basic Blocks:");
-  for (unsigned i = 0, N = bbVec.size(); i < N; i++) {
-    DEBUG(std::cerr << (bbVec[i]->hasName()? bbVec[i]->getName() : "block")
-          << " (" << bbVec[i] << ")" << ((i == N - 1) ? "" : ", "));
-  }
+
+  DEBUG(std::cerr << (bb->hasName()? bb->getName() : "block")
+	<< " (" << bb << ")" <<  "");
 
   DEBUG(std::cerr << "\n\n    Actual Root nodes : ");
   for (unsigned i = 0, N = graphRoot->outEdges.size(); i < N; i++)
@@ -1290,7 +1286,7 @@
   DEBUG(std::cerr << "\n    Graph Nodes:\n");
   //for (const_iterator I=begin(); I != end(); ++I)
   //DEBUG(std::cerr << "\n" << *I->second;
-  unsigned numNodes = bbVec[0]->size();
+  unsigned numNodes = bb->size();
   for (unsigned i = 2; i < numNodes + 2; i++) {
     ModuloSchedGraphNode *node = getNode(i);
     DEBUG(std::cerr << "\n" << *node);
@@ -1301,7 +1297,7 @@
 
 void ModuloSchedGraph::dumpNodeProperty() const
 {
-  const BasicBlock *bb = bbVec[0];
+
   unsigned numNodes = bb->size();
   for (unsigned i = 2; i < numNodes + 2; i++) {
     ModuloSchedGraphNode *node = getNode(i);
@@ -1317,8 +1313,11 @@
 void ModuloSchedGraphSet::buildGraphsForMethod(const Function *F,
                                                const TargetMachine &target)
 {
-  for (Function::const_iterator BI = F->begin(); BI != F->end(); ++BI)
-    addGraph(new ModuloSchedGraph(BI, target));
+  for (Function::const_iterator BI = F->begin(); BI != F->end(); ++BI){
+    const BasicBlock* local_bb;
+    local_bb=BI;
+    addGraph(new ModuloSchedGraph((BasicBlock*)local_bb, target));
+  }
 }
 
 std::ostream& operator<<(std::ostream &os,


Index: llvm/lib/CodeGen/ModuloScheduling/ModuloSchedGraph.h
diff -u llvm/lib/CodeGen/ModuloScheduling/ModuloSchedGraph.h:1.5 llvm/lib/CodeGen/ModuloScheduling/ModuloSchedGraph.h:1.6
--- llvm/lib/CodeGen/ModuloScheduling/ModuloSchedGraph.h:1.5	Tue Apr 22 18:00:08 2003
+++ llvm/lib/CodeGen/ModuloScheduling/ModuloSchedGraph.h	Mon Jun  2 12:48:56 2003
@@ -56,6 +56,7 @@
   const unsigned getInstOpcode() const {
     return inst->getOpcode();
   }
+
   //return whether the node is NULL
   bool isNullNode() const {
     return (inst == NULL);
@@ -138,6 +139,9 @@
   protected hash_map<const Instruction*,ModuloSchedGraphNode*> {
 
 private:
+
+  BasicBlock* bb;
+  
   //iteration Interval
   int MII;
 
@@ -153,14 +157,14 @@
   typedef std::vector<ModuloSchedGraphNode*> NodeVec;
 
   //the function to compute properties
-  void computeNodeASAP(const BasicBlock *bb);
-  void computeNodeALAP(const BasicBlock *bb);
-  void computeNodeMov(const BasicBlock *bb);
-  void computeNodeDepth(const BasicBlock *bb);
-  void computeNodeHeight(const BasicBlock *bb);
+  void computeNodeASAP(const BasicBlock * in_bb);
+  void computeNodeALAP(const BasicBlock * in_bb);
+  void computeNodeMov(const BasicBlock *  in_bb);
+  void computeNodeDepth(const BasicBlock * in_bb);
+  void computeNodeHeight(const BasicBlock * in_bb);
 
   //the function to compute node property
-  void computeNodeProperty(const BasicBlock *bb);
+  void computeNodeProperty(const BasicBlock * in_bb);
 
   //the function to sort nodes
   void orderNodes();
@@ -220,6 +224,13 @@
   const TargetMachine & getTarget() {
     return target;
   }
+
+  //get the basic block
+  BasicBlock* getBasicBlock() const {
+    return bb;
+  }
+
+
   //get the iteration interval
   const int getMII() {
     return MII;
@@ -265,8 +276,9 @@
   friend class ModuloSchedGraphSet;     //give access to ctor
 
 public:
-  ModuloSchedGraph(const BasicBlock *bb, const TargetMachine &_target)
-    :SchedGraphCommon(bb), target(_target)
+  ModuloSchedGraph(BasicBlock * in_bb, 
+		   const TargetMachine & in_target)
+    :SchedGraphCommon(), bb(in_bb),target(in_target)
   {
     buildGraph(target);
   }


Index: llvm/lib/CodeGen/ModuloScheduling/ModuloScheduling.h
diff -u llvm/lib/CodeGen/ModuloScheduling/ModuloScheduling.h:1.5 llvm/lib/CodeGen/ModuloScheduling/ModuloScheduling.h:1.6
--- llvm/lib/CodeGen/ModuloScheduling/ModuloScheduling.h:1.5	Thu May 29 19:17:09 2003
+++ llvm/lib/CodeGen/ModuloScheduling/ModuloScheduling.h	Mon Jun  2 12:48:56 2003
@@ -65,7 +65,7 @@
     graph(_graph), target(graph.getTarget()), oNodes(graph.getONodes())
   {
     II = graph.getMII();
-    bb = (BasicBlock *) graph.getBasicBlocks()[0];
+    bb = graph.getBasicBlock();
     instrScheduling();
   };
 




From brukman at cs.uiuc.edu  Mon Jun  2 14:09:01 2003
From: brukman at cs.uiuc.edu (Misha Brukman)
Date: Mon Jun  2 14:09:01 2003
Subject: [llvm-commits] CVS: llvm/lib/Target/Sparc/SparcV9.td
Message-ID: <200306021908.OAA14021@zion.cs.uiuc.edu>


Changes in directory llvm/lib/Target/Sparc:

SparcV9.td updated: 1.7 -> 1.8

---
Log message:

* Added casts to/from floating-point to integers.
* Changed // comments to #ifdef 0 to maintain syntax highlighting.


---
Diffs of the changes:

Index: llvm/lib/Target/Sparc/SparcV9.td
diff -u llvm/lib/Target/Sparc/SparcV9.td:1.7 llvm/lib/Target/Sparc/SparcV9.td:1.8
--- llvm/lib/Target/Sparc/SparcV9.td:1.7	Sat May 31 01:24:29 2003
+++ llvm/lib/Target/Sparc/SparcV9.td	Mon Jun  2 14:08:37 2003
@@ -75,24 +75,27 @@
 }
 
 // Section A.5: p167
-//set op2 = 0b101 in {
-  //def FBPA     : F2_3<0b1000, "fbpa">;              // Branch always
-  //def FBPN     : F2_3<0b0000, "fbpn">;              // Branch never
-  //def FBPU     : F2_3<0b0111, "fbpu">;              // Branch on unordered
-  //def FBPG     : F2_3<0b0110, "fbpg">;              // Branch >
-  //def FBPUG    : F2_3<0b0101, "fbpug">;             // Branch on unordered or >
-  //def FBPL     : F2_3<0b0100, "fbpl">;              // Branch <
-  //def FBPUL    : F2_3<0b0011, "fbpul">;             // Branch on unordered or <
-  //def FBPLG    : F2_3<0b0010, "fbplg">;             // Branch < or >
-  //def FBPNE    : F2_3<0b0001, "fbpne">;             // Branch !=
-  //def FBPE     : F2_3<0b1001, "fbpe">;              // Branch ==
-  //def FBPUE    : F2_3<0b1010, "fbpue">;             // Branch on unordered or ==
-  //def FBPGE    : F2_3<0b1011, "fbpge">;             // Branch > or ==
-  //def FBPUGE   : F2_3<0b1100, "fbpuge">;            // Branch unord or > or ==
-  //def FBPLE    : F2_3<0b1101, "fbple">;             // Branch < or ==
-  //def FBPULE   : F2_3<0b1110, "fbpule">;            // Branch unord or < or ==
-  //def FBPO     : F2_3<0b1111, "fbpo">;              // Branch on ordered
-//}
+// Not used in the Sparc backend
+#if 0
+set op2 = 0b101 in {
+  def FBPA     : F2_3<0b1000, "fbpa">;              // Branch always
+  def FBPN     : F2_3<0b0000, "fbpn">;              // Branch never
+  def FBPU     : F2_3<0b0111, "fbpu">;              // Branch on unordered
+  def FBPG     : F2_3<0b0110, "fbpg">;              // Branch >
+  def FBPUG    : F2_3<0b0101, "fbpug">;             // Branch on unordered or >
+  def FBPL     : F2_3<0b0100, "fbpl">;              // Branch <
+  def FBPUL    : F2_3<0b0011, "fbpul">;             // Branch on unordered or <
+  def FBPLG    : F2_3<0b0010, "fbplg">;             // Branch < or >
+  def FBPNE    : F2_3<0b0001, "fbpne">;             // Branch !=
+  def FBPE     : F2_3<0b1001, "fbpe">;              // Branch ==
+  def FBPUE    : F2_3<0b1010, "fbpue">;             // Branch on unordered or ==
+  def FBPGE    : F2_3<0b1011, "fbpge">;             // Branch > or ==
+  def FBPUGE   : F2_3<0b1100, "fbpuge">;            // Branch unord or > or ==
+  def FBPLE    : F2_3<0b1101, "fbple">;             // Branch < or ==
+  def FBPULE   : F2_3<0b1110, "fbpule">;            // Branch unord or < or ==
+  def FBPO     : F2_3<0b1111, "fbpo">;              // Branch on ordered
+}
+#endif
 
 // Section A.6: Branch on Integer condition codes (Bicc) - p146
 set isDeprecated = 1 in {
@@ -117,26 +120,29 @@
 }
 
 // Section A.7: Branch on integer condition codes with prediction - p148
-//set op2 = 0b001 in {
-//  def BPA     : F2_3<0b1000, "bpa">;              // Branch always
-//  def BPN     : F2_3<0b0000, "bpn">;              // Branch never
-//  def BPNE    : F2_3<0b1001, "bpne">;             // Branch !=
-//  def BPE     : F2_3<0b0001, "bpe">;              // Branch ==
-//  def BPG     : F2_3<0b1010, "bpg">;              // Branch >
-//  def BPLE    : F2_3<0b0010, "bple">;             // Branch <=
-//  def BPGE    : F2_3<0b1011, "bpge">;             // Branch >=
-//  def BPL     : F2_3<0b0011, "bpl">;              // Branch <
-//  def BPGU    : F2_3<0b1100, "bpgu">;             // Branch unsigned >
-//  def BPLEU   : F2_3<0b0100, "bpleu">;            // Branch unsigned <=
-//  def BPCC    : F2_3<0b1101, "bpcc">;             // Branch unsigned >=
-//  def BPCS    : F2_3<0b0101, "bpcs">;             // Branch unsigned <=
-//  def BPPOS   : F2_3<0b1110, "bppos">;            // Branch on positive
-//  def BPNEG   : F2_3<0b0110, "bpneg">;            // Branch on negative
-//  def BPVC    : F2_3<0b1111, "bpvc">;             // Branch on overflow clear
-//  def BPVS    : F2_3<0b0111, "bpvs">;             // Branch on overflow set
-//}
+// Not used in the Sparc backend
+#if 0
+set op2 = 0b001 in {
+  def BPA     : F2_3<0b1000, "bpa">;              // Branch always
+  def BPN     : F2_3<0b0000, "bpn">;              // Branch never
+  def BPNE    : F2_3<0b1001, "bpne">;             // Branch !=
+  def BPE     : F2_3<0b0001, "bpe">;              // Branch ==
+  def BPG     : F2_3<0b1010, "bpg">;              // Branch >
+  def BPLE    : F2_3<0b0010, "bple">;             // Branch <=
+  def BPGE    : F2_3<0b1011, "bpge">;             // Branch >=
+  def BPL     : F2_3<0b0011, "bpl">;              // Branch <
+  def BPGU    : F2_3<0b1100, "bpgu">;             // Branch unsigned >
+  def BPLEU   : F2_3<0b0100, "bpleu">;            // Branch unsigned <=
+  def BPCC    : F2_3<0b1101, "bpcc">;             // Branch unsigned >=
+  def BPCS    : F2_3<0b0101, "bpcs">;             // Branch unsigned <=
+  def BPPOS   : F2_3<0b1110, "bppos">;            // Branch on positive
+  def BPNEG   : F2_3<0b0110, "bpneg">;            // Branch on negative
+  def BPVC    : F2_3<0b1111, "bpvc">;             // Branch on overflow clear
+  def BPVS    : F2_3<0b0111, "bpvs">;             // Branch on overflow set
+}
+#endif
 
-// Section A.8: p175 - CALL - the only Format #1 instruction
+// Section A.8: CALL - p151, the only Format #1 instruction
 def CALL : InstV9 {
   bits<30> disp;
   set op = 1;
@@ -151,22 +157,27 @@
 
 // Section A.10: Divide (64-bit / 32-bit) - p178
 // Not used in the Sparc backend
-//set isDeprecated = 1 in {
-  //def UDIVr   : F3_1<2, 0b001110, "udiv">;        // udiv r, r, r
-  //def UDIVi   : F3_2<2, 0b001110, "udiv">;        // udiv r, r, i
-  //def SDIVr   : F3_1<2, 0b001111, "sdiv">;        // sdiv r, r, r
-  //def SDIVi   : F3_2<2, 0b001111, "sdiv">;        // sdiv r, r, i
-  //def UDIVCCr : F3_1<2, 0b011110, "udivcc">;      // udivcc r, r, r
-  //def UDIVCCi : F3_2<2, 0b011110, "udivcc">;      // udivcc r, r, i
-  //def SDIVCCr : F3_1<2, 0b011111, "sdivcc">;      // sdivcc r, r, r
-  //def SDIVCCi : F3_2<2, 0b011111, "sdivcc">;      // sdivcc r, r, i
-//}
+#if 0
+set isDeprecated = 1 in {
+  def UDIVr   : F3_1<2, 0b001110, "udiv">;        // udiv r, r, r
+  def UDIVi   : F3_2<2, 0b001110, "udiv">;        // udiv r, r, i
+  def SDIVr   : F3_1<2, 0b001111, "sdiv">;        // sdiv r, r, r
+  def SDIVi   : F3_2<2, 0b001111, "sdiv">;        // sdiv r, r, i
+  def UDIVCCr : F3_1<2, 0b011110, "udivcc">;      // udivcc r, r, r
+  def UDIVCCi : F3_2<2, 0b011110, "udivcc">;      // udivcc r, r, i
+  def SDIVCCr : F3_1<2, 0b011111, "sdivcc">;      // sdivcc r, r, r
+  def SDIVCCi : F3_2<2, 0b011111, "sdivcc">;      // sdivcc r, r, i
+}
+#endif
 
 // Section A.11: DONE and RETRY - p181
-//set isPrivileged = 1 in {
-  //def DONE    : F3_18<0, "done">;                 // done
-  //def RETRY   : F3_18<1, "retry">;                // retry
-//}
+// Not used in the Sparc backend
+#if 0
+set isPrivileged = 1 in {
+  def DONE    : F3_18<0, "done">;                 // done
+  def RETRY   : F3_18<1, "retry">;                // retry
+}
+#endif
 
 // Section A.12: Floating-Point Add and Subtract - p182
 def FADDS : F3_16<2, 0b110100, 0x41, "fadds">;    // fadds f, f, f
@@ -176,6 +187,41 @@
 def FSUBD : F3_16<2, 0b110100, 0x46, "fsubd">;    // fsubd f, f, f
 def FSUBQ : F3_16<2, 0b110100, 0x47, "fsubq">;    // fsubq f, f, f
 
+// Section A.13: Floating-point compare - p159
+// FIXME: FCMPS, FCMPD, FCMPQ !!!
+#if 0
+def FSTOX : F3_14<2, 0b110100, 0b011001001, "fstod">;   // fstod rs2, rd
+def FDTOX : F3_14<2, 0b110100, 0b011001101, "fstoq">;   // fstoq rs2, rd
+def FQTOX : F3_14<2, 0b110100, 0b011000110, "fstos">;   // fstos rs2, rd
+def FSTOI : F3_14<2, 0b110100, 0b011001110, "fdtoq">;   // fdtoq rs2, rd
+def FDTOI : F3_14<2, 0b110100, 0b011000111, "fqtos">;   // fqtos rs2, rd
+def FQTOI : F3_14<2, 0b110100, 0b011001011, "fqtod">;   // fqtod rs2, rd
+#endif
+
+// Section A.14: Convert floating-point to integer - p161
+def FSTOX : F3_14<2, 0b110100, 0b010000001, "fstox">;   // fstox rs2, rd
+def FDTOX : F3_14<2, 0b110100, 0b010000010, "fstox">;   // fstox rs2, rd
+def FQTOX : F3_14<2, 0b110100, 0b010000011, "fstox">;   // fstox rs2, rd
+def FSTOI : F3_14<2, 0b110100, 0b011010001, "fstoi">;   // fstoi rs2, rd
+def FDTOI : F3_14<2, 0b110100, 0b011010010, "fdtoi">;   // fdtoi rs2, rd
+def FQTOI : F3_14<2, 0b110100, 0b011010011, "fqtoi">;   // fqtoi rs2, rd
+
+// Section A.15: Convert between floating-point formats - p162
+def FSTOD : F3_14<2, 0b110100, 0b011001001, "fstod">;   // fstod rs2, rd
+def FSTOQ : F3_14<2, 0b110100, 0b011001101, "fstoq">;   // fstoq rs2, rd
+def FDTOS : F3_14<2, 0b110100, 0b011000110, "fstos">;   // fstos rs2, rd
+def FDTOQ : F3_14<2, 0b110100, 0b011001110, "fdtoq">;   // fdtoq rs2, rd
+def FQTOS : F3_14<2, 0b110100, 0b011000111, "fqtos">;   // fqtos rs2, rd
+def FQTOD : F3_14<2, 0b110100, 0b011001011, "fqtod">;   // fqtod rs2, rd
+
+// Section A.16: Convert integer to floating-point - p163
+def FXTOS : F3_14<2, 0b110100, 0b010000100, "fxtos">;   // fxtos rs2, rd
+def FXTOD : F3_14<2, 0b110100, 0b010001000, "fxtod">;   // fxtod rs2, rd
+def FXTOQ : F3_14<2, 0b110100, 0b010001100, "fxtoq">;   // fxtoq rs2, rd
+def FITOS : F3_14<2, 0b110100, 0b011000100, "fitos">;   // fitos rs2, rd
+def FITOD : F3_14<2, 0b110100, 0b011001000, "fitod">;   // fitod rs2, rd
+def FITOQ : F3_14<2, 0b110100, 0b011001100, "fitoq">;   // fitoq rs2, rd
+
 // Section A.17: Floating-Point Move - p164
 def FMOVS : F3_14<2, 0b110100, 0b000000001, "fmovs">;   // fmovs r, r
 def FMOVD : F3_14<2, 0b110100, 0b000000010, "fmovs">;   // fmovd r, r
@@ -218,9 +264,6 @@
 def JMPLRETr  : F3_1<2, 0b111000, "jmpl">;              // jmpl [r+r], r
 def JMPLRETi  : F3_2<2, 0b111000, "jmpl">;              // jmpl [r+i], r
 
-// FIXME: FCMPS, FCMPD, FCMPQ !!!
-// FIXME: FMULS, FMULD, FMULQ, ...
-
 // Section A.25: Load Floating-Point - p173
 def LDFr  : F3_1<3, 0b100000, "ld">;             // ld [r+r], r
 def LDFi  : F3_2<3, 0b100000, "ld">;             // ld [r+i], r
@@ -256,10 +299,12 @@
 // LDD should no longer be used, LDX should be used instead
 def LDXr : F3_1<3, 0b001011, "ldx">;              // ldx [r+r], r
 def LDXi : F3_2<3, 0b001011, "ldx">;              // ldx [r+i], r
-//set isDeprecated = 1 in {
-//  def LDDr : F3_1<3, 0b000011, "ldd">;            // ldd [r+r], r
-//  def LDDi : F3_2<3, 0b000011, "ldd">;            // ldd [r+i], r
-//}
+#if 0
+set isDeprecated = 1 in {
+  def LDDr : F3_1<3, 0b000011, "ldd">;            // ldd [r+r], r
+  def LDDi : F3_2<3, 0b000011, "ldd">;            // ldd [r+i], r
+}
+#endif
 
 // Section A.31: Logical operations
 def ANDr    : F3_1<2, 0b000001, "and">;          // and r, r, r
@@ -289,6 +334,9 @@
 def XNORccr : F3_1<2, 0b010111, "xnorcc">;       // xnorcc r, r, r
 def XNORcci : F3_2<2, 0b010111, "xnorcc">;       // xnorcc r, r, i
 
+// Section A.32: Memory Barrier - p186
+// Not currently used in the Sparc backend
+
 #if 0
 // Section A.33: Move Floating-Point Register on Condition (FMOVcc)
 // For integer condition codes
@@ -331,8 +379,44 @@
 // FIXME: Section A.34: Move F-P Register on Integer Register (FMOVr)
 
 
-// FIXME: Section A.35: Move Integer Register on Condition (MOVcc)
+// Section A.35: Move Integer Register on Condition (MOVcc) - p194
+// For integer condition codes
+#if 0
+def MOVA    :
+def MOVN    :
+def MOVNE   :
+def MOVE    :
+def MOVG    :
+def MOVLE   :
+def MOVGE   :
+def MOVL    :
+def MOVGU   :
+def MOVLEU  :
+def MOVCC   :
+def MOVCS   :
+def MOVPOS  :
+def MOVNEG  :
+def MOVVC   :
+def MOVVS   :
 
+// For floating-point condition codes
+def MOVFA   :
+def MOVFN   :
+def MOVFU   :
+def MOVFG   :
+def MOVFUG  :
+def MOVFL   :
+def MOVFUL  :
+def MOVFLG  :
+def MOVFNE  :
+def MOVFE   :
+def MOVFUE  :
+def MOVFGE  :
+def MOVFUGE :
+def MOVFLE  :
+def MOVFULE :
+def MOVFO   :
+#endif
 
 // FIXME: Section A.36: Move Integer Register on Register Condition (MOVR)
 
@@ -346,19 +430,21 @@
 def UDIVXi : F3_2<2, 0b001101, "udivx">;       // mulx  r, i, r
 
 // Section A.38: Multiply (32-bit) - p200
-// Not used in the Sparc backend?
-//set Inst{13} = 0 in {
-//  def UMULr   : F3_1<2, 0b001010, "umul">;        // umul   r, r, r
-//  def SMULr   : F3_1<2, 0b001011, "smul">;        // smul   r, r, r
-//  def UMULCCr : F3_1<2, 0b011010, "umulcc">;      // mulcc  r, r, r
-//  def SMULCCr : F3_1<2, 0b011011, "smulcc">;      // smulcc r, r, r
-//}
-//set Inst{13} = 1 in {
-//  def UMULi   : F3_1<2, 0b001010, "umul">;        // umul   r, i, r
-//  def SMULi   : F3_1<2, 0b001011, "smul">;        // smul   r, i, r
-//  def UMULCCi : F3_1<2, 0b011010, "umulcc">;      // umulcc r, i, r
-//  def SMULCCi : F3_1<2, 0b011011, "smulcc">;      // smulcc r, i, r
-//}
+// Not used in the Sparc backend
+#if 0
+set Inst{13} = 0 in {
+  def UMULr   : F3_1<2, 0b001010, "umul">;        // umul   r, r, r
+  def SMULr   : F3_1<2, 0b001011, "smul">;        // smul   r, r, r
+  def UMULCCr : F3_1<2, 0b011010, "umulcc">;      // mulcc  r, r, r
+  def SMULCCr : F3_1<2, 0b011011, "smulcc">;      // smulcc r, r, r
+}
+set Inst{13} = 1 in {
+  def UMULi   : F3_1<2, 0b001010, "umul">;        // umul   r, i, r
+  def SMULi   : F3_1<2, 0b001011, "smul">;        // smul   r, i, r
+  def UMULCCi : F3_1<2, 0b011010, "umulcc">;      // umulcc r, i, r
+  def SMULCCi : F3_1<2, 0b011011, "smulcc">;      // smulcc r, i, r
+}
+#endif
 
 // Section A.39: FIXME
 
@@ -403,15 +489,19 @@
 }
 
 // Section A.49: Shift - p221
-// uses 5 least significant bits of rs2
-//set x = 0 in {
-//  def SLLr5  : F3_11<2, 0b100101, "sll">;                // sll r, r, r
-//  def SRLr5  : F3_11<2, 0b100110, "srl">;                // srl r, r, r
-//  def SRAr5  : F3_11<2, 0b100111, "sra">;                // sra r, r, r
-//  def SLLXr5 : F3_11<2, 0b100101, "sllx">;               // sllx r, r, r
-//  def SRLXr5 : F3_11<2, 0b100110, "srlx">;               // srlx r, r, r
-//  def SRAXr5 : F3_11<2, 0b100111, "srax">;               // srax r, r, r
-//}
+// Not currently used in the Sparc backend
+#if 0
+ uses 5 least significant bits of rs2
+set x = 0 in {
+  def SLLr5  : F3_11<2, 0b100101, "sll">;                // sll r, r, r
+  def SRLr5  : F3_11<2, 0b100110, "srl">;                // srl r, r, r
+  def SRAr5  : F3_11<2, 0b100111, "sra">;                // sra r, r, r
+  def SLLXr5 : F3_11<2, 0b100101, "sllx">;               // sllx r, r, r
+  def SRLXr5 : F3_11<2, 0b100110, "srlx">;               // srlx r, r, r
+  def SRAXr5 : F3_11<2, 0b100111, "srax">;               // srax r, r, r
+}
+#endif
+
 // uses 6 least significant bits of rs2
 set x = 1 in {
   def SLLr6  : F3_11<2, 0b100101, "sll">;                // sll r, r, r
@@ -422,12 +512,15 @@
   def SRAXr6 : F3_11<2, 0b100111, "srax">;               // srax r, r, r
 }
 
-//def SLLi5  : F3_12<2, 0b100101, "sll">;                // sll r, shcnt32, r
-//def SRLi5  : F3_12<2, 0b100110, "srl">;                // srl r, shcnt32, r
-//def SRAi5  : F3_12<2, 0b100111, "sra">;                // sra r, shcnt32, r
-//def SLLXi5 : F3_12<2, 0b100101, "sllx">;               // sllx r, shcnt32, r
-//def SRLXi5 : F3_12<2, 0b100110, "srlx">;               // srlx r, shcnt32, r
-//def SRAXi5 : F3_12<2, 0b100111, "srax">;               // srax r, shcnt32, r
+// Not currently used in the Sparc backend
+#if 0
+def SLLi5  : F3_12<2, 0b100101, "sll">;                // sll r, shcnt32, r
+def SRLi5  : F3_12<2, 0b100110, "srl">;                // srl r, shcnt32, r
+def SRAi5  : F3_12<2, 0b100111, "sra">;                // sra r, shcnt32, r
+def SLLXi5 : F3_12<2, 0b100101, "sllx">;               // sllx r, shcnt32, r
+def SRLXi5 : F3_12<2, 0b100110, "srlx">;               // srlx r, shcnt32, r
+def SRAXi5 : F3_12<2, 0b100111, "srax">;               // srax r, shcnt32, r
+#endif
 
 def SLLi6  : F3_13<2, 0b100101, "sll">;                  // sll r, shcnt64, r
 def SRLi6  : F3_13<2, 0b100110, "srl">;                  // srl r, shcnt64, r
@@ -445,9 +538,13 @@
 def STFi  : F3_2<3, 0b100100, "st">;                      // st r, [r+i]
 def STDFr : F3_1<3, 0b100111, "std">;                     // std r, [r+r]
 def STDFi : F3_2<3, 0b100111, "std">;                     // std r, [r+i]
+
 // Not currently used in the Sparc backend
-//def STQFr : F3_1<3, 0b100110, "stq">;                     // stq r, [r+r]
-//def STQFi : F3_2<3, 0b100110, "stq">;                     // stq r, [r+i]
+#if 0
+def STQFr : F3_1<3, 0b100110, "stq">;                     // stq r, [r+r]
+def STQFi : F3_2<3, 0b100110, "stq">;                     // stq r, [r+i]
+#endif
+
 set isDeprecated = 1 in {
   def STFSRr : F3_1<3, 0b100101, "st">;                   // st r, [r+r]
   def STFSRi : F3_2<3, 0b100101, "st">;                   // st r, [r+i]




From brukman at cs.uiuc.edu  Mon Jun  2 15:51:29 2003
From: brukman at cs.uiuc.edu (Misha Brukman)
Date: Mon Jun  2 15:51:29 2003
Subject: [llvm-commits] CVS: llvm/lib/CodeGen/MachineCodeEmitter.cpp
Message-ID: <200306022049.PAA15356@zion.cs.uiuc.edu>


Changes in directory llvm/lib/CodeGen:

MachineCodeEmitter.cpp updated: 1.10 -> 1.11

---
Log message:

Removed a useless ofstream.


---
Diffs of the changes:

Index: llvm/lib/CodeGen/MachineCodeEmitter.cpp
diff -u llvm/lib/CodeGen/MachineCodeEmitter.cpp:1.10 llvm/lib/CodeGen/MachineCodeEmitter.cpp:1.11
--- llvm/lib/CodeGen/MachineCodeEmitter.cpp:1.10	Sun Jun  1 23:10:41 2003
+++ llvm/lib/CodeGen/MachineCodeEmitter.cpp	Mon Jun  2 15:49:09 2003
@@ -60,27 +60,21 @@
 
 namespace {
   class FilePrinterEmitter : public MachineCodeEmitter {
-    std::ofstream f, actual;
+    std::ofstream actual;
     std::ostream &o;
     MachineCodeEmitter &MCE;
     unsigned counter;
-    bool mustClose;
     unsigned values[4];
     
   public:
     FilePrinterEmitter(MachineCodeEmitter &M, std::ostream &os)
-      : f("lli.out"), o(os), MCE(M), counter(0), mustClose(false) {
-      if (!f.good()) {
-        std::cerr << "Cannot open 'lli.out' for writing\n";
-        abort();
-      }
+      : o(os), MCE(M), counter(0) {
       openActual();
     }
     
     ~FilePrinterEmitter() { 
       o << "\n";
       actual.close();
-      if (mustClose) f.close();
     }
 
     void openActual() {




From brukman at cs.uiuc.edu  Mon Jun  2 15:56:01 2003
From: brukman at cs.uiuc.edu (Misha Brukman)
Date: Mon Jun  2 15:56:01 2003
Subject: [llvm-commits] CVS: llvm/lib/Target/Sparc/SparcInstr.def SparcInstrSelection.cpp SparcV9.td SparcV9_F4.td
Message-ID: <200306022055.PAA15397@zion.cs.uiuc.edu>


Changes in directory llvm/lib/Target/Sparc:

SparcInstr.def updated: 1.17 -> 1.18
SparcInstrSelection.cpp updated: 1.99 -> 1.100
SparcV9.td updated: 1.8 -> 1.9
SparcV9_F4.td updated: 1.1 -> 1.2

---
Log message:

SparcInstr.def: added 'r' and 'i' versions of MOV(F)cc instructions

SparcInstrSelection.cpp: 
* Fixed opcodes to return correct 'i' version since the two functions are each
  only used in one place.
* Changed name of function to have an 'i' in the name to signify that they each
  return an immediate form of the opcode.
* Added a warning if either of the functions is ever used in a context which
  requires a register-version opcode.

SparcV9_F4.td: fixed class F4_3, added F4_4 and notes that F4_{1,2} need fixing
SparcV9.td: added the MOV(F)cc instructions


---
Diffs of the changes:

Index: llvm/lib/Target/Sparc/SparcInstr.def
diff -u llvm/lib/Target/Sparc/SparcInstr.def:1.17 llvm/lib/Target/Sparc/SparcInstr.def:1.18
--- llvm/lib/Target/Sparc/SparcInstr.def:1.17	Fri May 30 14:14:01 2003
+++ llvm/lib/Target/Sparc/SparcInstr.def	Mon Jun  2 15:55:14 2003
@@ -244,44 +244,76 @@
 
 // Conditional move on integer condition code.
 // The first argument specifies the ICC register: %icc or %xcc
-I(MOVA  , "mova",	3,  2, B12, true , 0, 2,  SPARC_SINGLE,  M_CC_FLAG | M_INT_FLAG)
-I(MOVN  , "movn",	3,  2, B12, true , 0, 2,  SPARC_SINGLE,  M_CC_FLAG | M_INT_FLAG)
-I(MOVNE , "movne",	3,  2, B12, true , 0, 2,  SPARC_SINGLE,  M_CC_FLAG | M_INT_FLAG)
-I(MOVE  , "move",	3,  2, B12, true , 0, 2,  SPARC_SINGLE,  M_CC_FLAG | M_INT_FLAG)
-I(MOVG  , "movg",	3,  2, B12, true , 0, 2,  SPARC_SINGLE,  M_CC_FLAG | M_INT_FLAG)
-I(MOVLE , "movle",	3,  2, B12, true , 0, 2,  SPARC_SINGLE,  M_CC_FLAG | M_INT_FLAG)
-I(MOVGE , "movge",	3,  2, B12, true , 0, 2,  SPARC_SINGLE,  M_CC_FLAG | M_INT_FLAG)
-I(MOVL  , "movl",	3,  2, B12, true , 0, 2,  SPARC_SINGLE,  M_CC_FLAG | M_INT_FLAG)
-I(MOVGU , "movgu",	3,  2, B12, true , 0, 2,  SPARC_SINGLE,  M_CC_FLAG | M_INT_FLAG)
-I(MOVLEU, "movleu",	3,  2, B12, true , 0, 2,  SPARC_SINGLE,  M_CC_FLAG | M_INT_FLAG)
-I(MOVCC , "movcc",	3,  2, B12, true , 0, 2,  SPARC_SINGLE,  M_CC_FLAG | M_INT_FLAG)
-I(MOVCS , "movcs",	3,  2, B12, true , 0, 2,  SPARC_SINGLE,  M_CC_FLAG | M_INT_FLAG)
-I(MOVPOS, "movpos",	3,  2, B12, true , 0, 2,  SPARC_SINGLE,  M_CC_FLAG | M_INT_FLAG)
-I(MOVNEG, "movneg",	3,  2, B12, true , 0, 2,  SPARC_SINGLE,  M_CC_FLAG | M_INT_FLAG)
-I(MOVVC , "movvc",	3,  2, B12, true , 0, 2,  SPARC_SINGLE,  M_CC_FLAG | M_INT_FLAG)
-I(MOVVS , "movvs",	3,  2, B12, true , 0, 2,  SPARC_SINGLE,  M_CC_FLAG | M_INT_FLAG)
+I(MOVAr  , "mova",	3,  2, B12, true , 0, 2,  SPARC_SINGLE,  M_CC_FLAG | M_INT_FLAG)
+I(MOVAi  , "mova",	3,  2, B12, true , 0, 2,  SPARC_SINGLE,  M_CC_FLAG | M_INT_FLAG)
+I(MOVNr  , "movn",	3,  2, B12, true , 0, 2,  SPARC_SINGLE,  M_CC_FLAG | M_INT_FLAG)
+I(MOVNi  , "movn",	3,  2, B12, true , 0, 2,  SPARC_SINGLE,  M_CC_FLAG | M_INT_FLAG)
+I(MOVNEr , "movne",	3,  2, B12, true , 0, 2,  SPARC_SINGLE,  M_CC_FLAG | M_INT_FLAG)
+I(MOVNEi , "movne",	3,  2, B12, true , 0, 2,  SPARC_SINGLE,  M_CC_FLAG | M_INT_FLAG)
+I(MOVEr  , "move",	3,  2, B12, true , 0, 2,  SPARC_SINGLE,  M_CC_FLAG | M_INT_FLAG)
+I(MOVEi  , "move",	3,  2, B12, true , 0, 2,  SPARC_SINGLE,  M_CC_FLAG | M_INT_FLAG)
+I(MOVGr  , "movg",	3,  2, B12, true , 0, 2,  SPARC_SINGLE,  M_CC_FLAG | M_INT_FLAG)
+I(MOVGi  , "movg",	3,  2, B12, true , 0, 2,  SPARC_SINGLE,  M_CC_FLAG | M_INT_FLAG)
+I(MOVLEr , "movle",	3,  2, B12, true , 0, 2,  SPARC_SINGLE,  M_CC_FLAG | M_INT_FLAG)
+I(MOVLEi , "movle",	3,  2, B12, true , 0, 2,  SPARC_SINGLE,  M_CC_FLAG | M_INT_FLAG)
+I(MOVGEr , "movge",	3,  2, B12, true , 0, 2,  SPARC_SINGLE,  M_CC_FLAG | M_INT_FLAG)
+I(MOVGEi , "movge",	3,  2, B12, true , 0, 2,  SPARC_SINGLE,  M_CC_FLAG | M_INT_FLAG)
+I(MOVLr  , "movl",	3,  2, B12, true , 0, 2,  SPARC_SINGLE,  M_CC_FLAG | M_INT_FLAG)
+I(MOVLi  , "movl",	3,  2, B12, true , 0, 2,  SPARC_SINGLE,  M_CC_FLAG | M_INT_FLAG)
+I(MOVGUr , "movgu",	3,  2, B12, true , 0, 2,  SPARC_SINGLE,  M_CC_FLAG | M_INT_FLAG)
+I(MOVGUi , "movgu",	3,  2, B12, true , 0, 2,  SPARC_SINGLE,  M_CC_FLAG | M_INT_FLAG)
+I(MOVLEUr, "movleu",	3,  2, B12, true , 0, 2,  SPARC_SINGLE,  M_CC_FLAG | M_INT_FLAG)
+I(MOVLEUi, "movleu",	3,  2, B12, true , 0, 2,  SPARC_SINGLE,  M_CC_FLAG | M_INT_FLAG)
+I(MOVCCr , "movcc",	3,  2, B12, true , 0, 2,  SPARC_SINGLE,  M_CC_FLAG | M_INT_FLAG)
+I(MOVCCi , "movcc",	3,  2, B12, true , 0, 2,  SPARC_SINGLE,  M_CC_FLAG | M_INT_FLAG)
+I(MOVCSr , "movcs",	3,  2, B12, true , 0, 2,  SPARC_SINGLE,  M_CC_FLAG | M_INT_FLAG)
+I(MOVCSi , "movcs",	3,  2, B12, true , 0, 2,  SPARC_SINGLE,  M_CC_FLAG | M_INT_FLAG)
+I(MOVPOSr, "movpos",	3,  2, B12, true , 0, 2,  SPARC_SINGLE,  M_CC_FLAG | M_INT_FLAG)
+I(MOVPOSi, "movpos",	3,  2, B12, true , 0, 2,  SPARC_SINGLE,  M_CC_FLAG | M_INT_FLAG)
+I(MOVNEGr, "movneg",	3,  2, B12, true , 0, 2,  SPARC_SINGLE,  M_CC_FLAG | M_INT_FLAG)
+I(MOVNEGi, "movneg",	3,  2, B12, true , 0, 2,  SPARC_SINGLE,  M_CC_FLAG | M_INT_FLAG)
+I(MOVVCr , "movvc",	3,  2, B12, true , 0, 2,  SPARC_SINGLE,  M_CC_FLAG | M_INT_FLAG)
+I(MOVVCi , "movvc",	3,  2, B12, true , 0, 2,  SPARC_SINGLE,  M_CC_FLAG | M_INT_FLAG)
+I(MOVVSr , "movvs",	3,  2, B12, true , 0, 2,  SPARC_SINGLE,  M_CC_FLAG | M_INT_FLAG)
+I(MOVVSi , "movvs",	3,  2, B12, true , 0, 2,  SPARC_SINGLE,  M_CC_FLAG | M_INT_FLAG)
 
 // Conditional move (of integer register) on floating point condition code.
 // The first argument is the FCCn register (0 <= n <= 3).
 // Note that the enum name above is not the same as the assembly mnemonic
 // because some of the assembly mnemonics are the same as the move on
 // integer CC (e.g., MOVG), and we cannot have the same enum entry twice.
-I(MOVFA  , "mova",	3,  2, B12, true , 0, 2,  SPARC_SINGLE,  M_CC_FLAG | M_INT_FLAG)
-I(MOVFN  , "movn",	3,  2, B12, true , 0, 2,  SPARC_SINGLE,  M_CC_FLAG | M_INT_FLAG)
-I(MOVFU  , "movu",	3,  2, B12, true , 0, 2,  SPARC_SINGLE,  M_CC_FLAG | M_INT_FLAG)
-I(MOVFG  , "movg",	3,  2, B12, true , 0, 2,  SPARC_SINGLE,  M_CC_FLAG | M_INT_FLAG)
-I(MOVFUG , "movug",	3,  2, B12, true , 0, 2,  SPARC_SINGLE,  M_CC_FLAG | M_INT_FLAG)
-I(MOVFL  , "movl",	3,  2, B12, true , 0, 2,  SPARC_SINGLE,  M_CC_FLAG | M_INT_FLAG)
-I(MOVFUL , "movul",	3,  2, B12, true , 0, 2,  SPARC_SINGLE,  M_CC_FLAG | M_INT_FLAG)
-I(MOVFLG , "movlg",	3,  2, B12, true , 0, 2,  SPARC_SINGLE,  M_CC_FLAG | M_INT_FLAG)
-I(MOVFNE , "movne",	3,  2, B12, true , 0, 2,  SPARC_SINGLE,  M_CC_FLAG | M_INT_FLAG)
-I(MOVFE  , "move",	3,  2, B12, true , 0, 2,  SPARC_SINGLE,  M_CC_FLAG | M_INT_FLAG)
-I(MOVFUE , "movue",	3,  2, B12, true , 0, 2,  SPARC_SINGLE,  M_CC_FLAG | M_INT_FLAG)
-I(MOVFGE , "movge",	3,  2, B12, true , 0, 2,  SPARC_SINGLE,  M_CC_FLAG | M_INT_FLAG)
-I(MOVFUGE, "movuge",	3,  2, B12, true , 0, 2,  SPARC_SINGLE,  M_CC_FLAG | M_INT_FLAG)
-I(MOVFLE , "movle",	3,  2, B12, true , 0, 2,  SPARC_SINGLE,  M_CC_FLAG | M_INT_FLAG)
-I(MOVFULE, "movule",	3,  2, B12, true , 0, 2,  SPARC_SINGLE,  M_CC_FLAG | M_INT_FLAG)
-I(MOVFO  , "movo",	3,  2, B12, true , 0, 2,  SPARC_SINGLE,  M_CC_FLAG | M_INT_FLAG)
+I(MOVFAr  , "mova",	3,  2, B12, true , 0, 2,  SPARC_SINGLE,  M_CC_FLAG | M_INT_FLAG)
+I(MOVFAi  , "mova",	3,  2, B12, true , 0, 2,  SPARC_SINGLE,  M_CC_FLAG | M_INT_FLAG)
+I(MOVFNr  , "movn",	3,  2, B12, true , 0, 2,  SPARC_SINGLE,  M_CC_FLAG | M_INT_FLAG)
+I(MOVFNi  , "movn",	3,  2, B12, true , 0, 2,  SPARC_SINGLE,  M_CC_FLAG | M_INT_FLAG)
+I(MOVFUr  , "movu",	3,  2, B12, true , 0, 2,  SPARC_SINGLE,  M_CC_FLAG | M_INT_FLAG)
+I(MOVFUi  , "movu",	3,  2, B12, true , 0, 2,  SPARC_SINGLE,  M_CC_FLAG | M_INT_FLAG)
+I(MOVFGr  , "movg",	3,  2, B12, true , 0, 2,  SPARC_SINGLE,  M_CC_FLAG | M_INT_FLAG)
+I(MOVFGi  , "movg",	3,  2, B12, true , 0, 2,  SPARC_SINGLE,  M_CC_FLAG | M_INT_FLAG)
+I(MOVFUGr , "movug",	3,  2, B12, true , 0, 2,  SPARC_SINGLE,  M_CC_FLAG | M_INT_FLAG)
+I(MOVFUGi , "movug",	3,  2, B12, true , 0, 2,  SPARC_SINGLE,  M_CC_FLAG | M_INT_FLAG)
+I(MOVFLr  , "movl",	3,  2, B12, true , 0, 2,  SPARC_SINGLE,  M_CC_FLAG | M_INT_FLAG)
+I(MOVFLi  , "movl",	3,  2, B12, true , 0, 2,  SPARC_SINGLE,  M_CC_FLAG | M_INT_FLAG)
+I(MOVFULr , "movul",	3,  2, B12, true , 0, 2,  SPARC_SINGLE,  M_CC_FLAG | M_INT_FLAG)
+I(MOVFULi , "movul",	3,  2, B12, true , 0, 2,  SPARC_SINGLE,  M_CC_FLAG | M_INT_FLAG)
+I(MOVFLGr , "movlg",	3,  2, B12, true , 0, 2,  SPARC_SINGLE,  M_CC_FLAG | M_INT_FLAG)
+I(MOVFLGi , "movlg",	3,  2, B12, true , 0, 2,  SPARC_SINGLE,  M_CC_FLAG | M_INT_FLAG)
+I(MOVFNEr , "movne",	3,  2, B12, true , 0, 2,  SPARC_SINGLE,  M_CC_FLAG | M_INT_FLAG)
+I(MOVFNEi , "movne",	3,  2, B12, true , 0, 2,  SPARC_SINGLE,  M_CC_FLAG | M_INT_FLAG)
+I(MOVFEr  , "move",	3,  2, B12, true , 0, 2,  SPARC_SINGLE,  M_CC_FLAG | M_INT_FLAG)
+I(MOVFEi  , "move",	3,  2, B12, true , 0, 2,  SPARC_SINGLE,  M_CC_FLAG | M_INT_FLAG)
+I(MOVFUEr , "movue",	3,  2, B12, true , 0, 2,  SPARC_SINGLE,  M_CC_FLAG | M_INT_FLAG)
+I(MOVFUEi , "movue",	3,  2, B12, true , 0, 2,  SPARC_SINGLE,  M_CC_FLAG | M_INT_FLAG)
+I(MOVFGEr , "movge",	3,  2, B12, true , 0, 2,  SPARC_SINGLE,  M_CC_FLAG | M_INT_FLAG)
+I(MOVFGEi , "movge",	3,  2, B12, true , 0, 2,  SPARC_SINGLE,  M_CC_FLAG | M_INT_FLAG)
+I(MOVFUGEr, "movuge",	3,  2, B12, true , 0, 2,  SPARC_SINGLE,  M_CC_FLAG | M_INT_FLAG)
+I(MOVFUGEi, "movuge",	3,  2, B12, true , 0, 2,  SPARC_SINGLE,  M_CC_FLAG | M_INT_FLAG)
+I(MOVFLEr , "movle",	3,  2, B12, true , 0, 2,  SPARC_SINGLE,  M_CC_FLAG | M_INT_FLAG)
+I(MOVFLEi , "movle",	3,  2, B12, true , 0, 2,  SPARC_SINGLE,  M_CC_FLAG | M_INT_FLAG)
+I(MOVFULEr, "movule",	3,  2, B12, true , 0, 2,  SPARC_SINGLE,  M_CC_FLAG | M_INT_FLAG)
+I(MOVFULEi, "movule",	3,  2, B12, true , 0, 2,  SPARC_SINGLE,  M_CC_FLAG | M_INT_FLAG)
+I(MOVFOr  , "movo",	3,  2, B12, true , 0, 2,  SPARC_SINGLE,  M_CC_FLAG | M_INT_FLAG)
+I(MOVFOi  , "movo",	3,  2, B12, true , 0, 2,  SPARC_SINGLE,  M_CC_FLAG | M_INT_FLAG)
 
 // Conditional move of floating point register on each of the above:
 // i.   on integer comparison with zero.


Index: llvm/lib/Target/Sparc/SparcInstrSelection.cpp
diff -u llvm/lib/Target/Sparc/SparcInstrSelection.cpp:1.99 llvm/lib/Target/Sparc/SparcInstrSelection.cpp:1.100
--- llvm/lib/Target/Sparc/SparcInstrSelection.cpp:1.99	Sat May 31 02:30:29 2003
+++ llvm/lib/Target/Sparc/SparcInstrSelection.cpp	Mon Jun  2 15:55:14 2003
@@ -402,19 +402,26 @@
 }
 
 
+// WARNING: since this function has only one caller, it always returns
+// the opcode that expects an immediate and a register. If this function
+// is ever used in cases where an opcode that takes two registers is required,
+// then modify this function and use convertOpcodeFromRegToImm() where required.
+//
+// It will be necessary to expand convertOpcodeFromRegToImm() to handle the
+// new cases of opcodes.
 static inline MachineOpCode 
-ChooseMovFpccInstruction(const InstructionNode* instrNode)
+ChooseMovFpcciInstruction(const InstructionNode* instrNode)
 {
   MachineOpCode opCode = V9::INVALID_OPCODE;
   
   switch(instrNode->getInstruction()->getOpcode())
   {
-  case Instruction::SetEQ: opCode = V9::MOVFE;  break;
-  case Instruction::SetNE: opCode = V9::MOVFNE; break;
-  case Instruction::SetLE: opCode = V9::MOVFLE; break;
-  case Instruction::SetGE: opCode = V9::MOVFGE; break;
-  case Instruction::SetLT: opCode = V9::MOVFL;  break;
-  case Instruction::SetGT: opCode = V9::MOVFG;  break;
+  case Instruction::SetEQ: opCode = V9::MOVFEi;  break;
+  case Instruction::SetNE: opCode = V9::MOVFNEi; break;
+  case Instruction::SetLE: opCode = V9::MOVFLEi; break;
+  case Instruction::SetGE: opCode = V9::MOVFGEi; break;
+  case Instruction::SetLT: opCode = V9::MOVFLi;  break;
+  case Instruction::SetGT: opCode = V9::MOVFGi;  break;
   default:
     assert(0 && "Unrecognized VM instruction!");
     break; 
@@ -432,19 +439,26 @@
 //                      (i.e., we want to test inverse of a condition)
 // (The latter two cases do not seem to arise because SetNE needs nothing.)
 // 
+// WARNING: since this function has only one caller, it always returns
+// the opcode that expects an immediate and a register. If this function
+// is ever used in cases where an opcode that takes two registers is required,
+// then modify this function and use convertOpcodeFromRegToImm() where required.
+//
+// It will be necessary to expand convertOpcodeFromRegToImm() to handle the
+// new cases of opcodes.
 static MachineOpCode
-ChooseMovpccAfterSub(const InstructionNode* instrNode)
+ChooseMovpcciAfterSub(const InstructionNode* instrNode)
 {
   MachineOpCode opCode = V9::INVALID_OPCODE;
   
   switch(instrNode->getInstruction()->getOpcode())
   {
-  case Instruction::SetEQ: opCode = V9::MOVE;  break;
-  case Instruction::SetLE: opCode = V9::MOVLE; break;
-  case Instruction::SetGE: opCode = V9::MOVGE; break;
-  case Instruction::SetLT: opCode = V9::MOVL;  break;
-  case Instruction::SetGT: opCode = V9::MOVG;  break;
-  case Instruction::SetNE: opCode = V9::MOVNE; break;
+  case Instruction::SetEQ: opCode = V9::MOVEi;  break;
+  case Instruction::SetLE: opCode = V9::MOVLEi; break;
+  case Instruction::SetGE: opCode = V9::MOVGEi; break;
+  case Instruction::SetLT: opCode = V9::MOVLi;  break;
+  case Instruction::SetGT: opCode = V9::MOVGi;  break;
+  case Instruction::SetNE: opCode = V9::MOVNEi; break;
   default: assert(0 && "Unrecognized VM instr!"); break; 
   }
   
@@ -2049,8 +2063,8 @@
         
         if (computeBoolVal) {
           MachineOpCode movOpCode = (isFPCompare
-                                     ? ChooseMovFpccInstruction(subtreeRoot)
-                                     : ChooseMovpccAfterSub(subtreeRoot));
+                                     ? ChooseMovFpcciInstruction(subtreeRoot)
+                                     : ChooseMovpcciAfterSub(subtreeRoot));
 
           // Unconditionally set register to 0
           M = BuildMI(V9::SETHI, 2).addZImm(0).addRegDef(setCCInstr);


Index: llvm/lib/Target/Sparc/SparcV9.td
diff -u llvm/lib/Target/Sparc/SparcV9.td:1.8 llvm/lib/Target/Sparc/SparcV9.td:1.9
--- llvm/lib/Target/Sparc/SparcV9.td:1.8	Mon Jun  2 14:08:37 2003
+++ llvm/lib/Target/Sparc/SparcV9.td	Mon Jun  2 15:55:14 2003
@@ -381,42 +381,72 @@
 
 // Section A.35: Move Integer Register on Condition (MOVcc) - p194
 // For integer condition codes
-#if 0
-def MOVA    :
-def MOVN    :
-def MOVNE   :
-def MOVE    :
-def MOVG    :
-def MOVLE   :
-def MOVGE   :
-def MOVL    :
-def MOVGU   :
-def MOVLEU  :
-def MOVCC   :
-def MOVCS   :
-def MOVPOS  :
-def MOVNEG  :
-def MOVVC   :
-def MOVVS   :
+def MOVAr    : F4_3<2, 0b101100, 0b1000, "mova">;      // mova i/xcc, rs2, rd
+def MOVAi    : F4_4<2, 0b101100, 0b1000, "mova">;      // mova i/xcc, rs2, rd
+def MOVNr    : F4_3<2, 0b101100, 0b0000, "movn">;      // mova i/xcc, rs2, rd
+def MOVNi    : F4_4<2, 0b101100, 0b0000, "movn">;      // mova i/xcc, rs2, rd
+def MOVNEr   : F4_3<2, 0b101100, 0b1001, "movne">;     // mova i/xcc, rs2, rd
+def MOVNEi   : F4_4<2, 0b101100, 0b1001, "movne">;     // mova i/xcc, rs2, rd
+def MOVEr    : F4_3<2, 0b101100, 0b0001, "move">;      // mova i/xcc, rs2, rd
+def MOVEi    : F4_4<2, 0b101100, 0b0001, "move">;      // mova i/xcc, rs2, rd
+def MOVGr    : F4_3<2, 0b101100, 0b1010, "movg">;      // mova i/xcc, rs2, rd
+def MOVGi    : F4_4<2, 0b101100, 0b1010, "movg">;      // mova i/xcc, rs2, rd
+def MOVLEr   : F4_3<2, 0b101100, 0b0010, "movle">;     // mova i/xcc, rs2, rd
+def MOVLEi   : F4_4<2, 0b101100, 0b0010, "movle">;     // mova i/xcc, rs2, rd
+def MOVGEr   : F4_3<2, 0b101100, 0b1011, "movge">;     // mova i/xcc, rs2, rd
+def MOVGEi   : F4_4<2, 0b101100, 0b1011, "movge">;     // mova i/xcc, rs2, rd
+def MOVLr    : F4_3<2, 0b101100, 0b0011, "movl">;      // mova i/xcc, rs2, rd
+def MOVLi    : F4_4<2, 0b101100, 0b0011, "movl">;      // mova i/xcc, rs2, rd
+def MOVGUr   : F4_3<2, 0b101100, 0b1100, "movgu">;     // mova i/xcc, rs2, rd
+def MOVGUi   : F4_4<2, 0b101100, 0b1100, "movgu">;     // mova i/xcc, rs2, rd
+def MOVLEUr  : F4_3<2, 0b101100, 0b0100, "movleu">;    // mova i/xcc, rs2, rd
+def MOVLEUi  : F4_4<2, 0b101100, 0b0100, "movleu">;    // mova i/xcc, rs2, rd
+def MOVCCr   : F4_3<2, 0b101100, 0b1101, "movcc">;     // mova i/xcc, rs2, rd
+def MOVCCi   : F4_4<2, 0b101100, 0b1101, "movcc">;     // mova i/xcc, rs2, rd
+def MOVCSr   : F4_3<2, 0b101100, 0b0101, "movcs">;     // mova i/xcc, rs2, rd
+def MOVCSi   : F4_4<2, 0b101100, 0b0101, "movcs">;     // mova i/xcc, rs2, rd
+def MOVPOSr  : F4_3<2, 0b101100, 0b1110, "movpos">;    // mova i/xcc, rs2, rd
+def MOVPOSi  : F4_4<2, 0b101100, 0b1110, "movpos">;    // mova i/xcc, rs2, rd
+def MOVNEGr  : F4_3<2, 0b101100, 0b0110, "movneg">;    // mova i/xcc, rs2, rd
+def MOVNEGi  : F4_4<2, 0b101100, 0b0110, "movneg">;    // mova i/xcc, rs2, rd
+def MOVVCr   : F4_3<2, 0b101100, 0b1111, "movvc">;     // mova i/xcc, rs2, rd
+def MOVVCi   : F4_4<2, 0b101100, 0b1111, "movvc">;     // mova i/xcc, rs2, rd
+def MOVVSr   : F4_3<2, 0b101100, 0b0111, "movvs">;     // mova i/xcc, rs2, rd
+def MOVVSi   : F4_4<2, 0b101100, 0b0111, "movvs">;     // mova i/xcc, rs2, rd
 
 // For floating-point condition codes
-def MOVFA   :
-def MOVFN   :
-def MOVFU   :
-def MOVFG   :
-def MOVFUG  :
-def MOVFL   :
-def MOVFUL  :
-def MOVFLG  :
-def MOVFNE  :
-def MOVFE   :
-def MOVFUE  :
-def MOVFGE  :
-def MOVFUGE :
-def MOVFLE  :
-def MOVFULE :
-def MOVFO   :
-#endif
+def MOVFAr   : F4_3<2, 0b101100, 0b1000, "movfa">;     // mova i/xcc, rs2, rd
+def MOVFAi   : F4_4<2, 0b101100, 0b1000, "movfa">;     // mova i/xcc, rs2, rd
+def MOVFNr   : F4_3<2, 0b101100, 0b0000, "movfn">;     // mova i/xcc, rs2, rd
+def MOVFNi   : F4_4<2, 0b101100, 0b0000, "movfn">;     // mova i/xcc, rs2, rd
+def MOVFUr   : F4_3<2, 0b101100, 0b0111, "movfu">;     // mova i/xcc, rs2, rd
+def MOVFUi   : F4_4<2, 0b101100, 0b0111, "movfu">;     // mova i/xcc, rs2, rd
+def MOVFGr   : F4_3<2, 0b101100, 0b0110, "movfg">;     // mova i/xcc, rs2, rd
+def MOVFGi   : F4_4<2, 0b101100, 0b0110, "movfg">;     // mova i/xcc, rs2, rd
+def MOVFUGr  : F4_3<2, 0b101100, 0b0101, "movfug">;    // mova i/xcc, rs2, rd
+def MOVFUGi  : F4_4<2, 0b101100, 0b0101, "movfug">;    // mova i/xcc, rs2, rd
+def MOVFLr   : F4_3<2, 0b101100, 0b0100, "movfl">;     // mova i/xcc, rs2, rd
+def MOVFLi   : F4_4<2, 0b101100, 0b0100, "movfl">;     // mova i/xcc, rs2, rd
+def MOVFULr  : F4_3<2, 0b101100, 0b0011, "movful">;    // mova i/xcc, rs2, rd
+def MOVFULi  : F4_4<2, 0b101100, 0b0011, "movful">;    // mova i/xcc, rs2, rd
+def MOVFLGr  : F4_3<2, 0b101100, 0b0010, "movflg">;    // mova i/xcc, rs2, rd
+def MOVFLGi  : F4_4<2, 0b101100, 0b0010, "movflg">;    // mova i/xcc, rs2, rd
+def MOVFNEr  : F4_3<2, 0b101100, 0b0001, "movfne">;    // mova i/xcc, rs2, rd
+def MOVFNEi  : F4_4<2, 0b101100, 0b0001, "movfne">;    // mova i/xcc, rs2, rd
+def MOVFEr   : F4_3<2, 0b101100, 0b1001, "movfe">;     // mova i/xcc, rs2, rd
+def MOVFEi   : F4_4<2, 0b101100, 0b1001, "movfe">;     // mova i/xcc, rs2, rd
+def MOVFUEr  : F4_3<2, 0b101100, 0b1010, "movfue">;    // mova i/xcc, rs2, rd
+def MOVFUEi  : F4_4<2, 0b101100, 0b1010, "movfue">;    // mova i/xcc, rs2, rd
+def MOVFGEr  : F4_3<2, 0b101100, 0b1011, "movfge">;    // mova i/xcc, rs2, rd
+def MOVFGEi  : F4_4<2, 0b101100, 0b1011, "movfge">;    // mova i/xcc, rs2, rd
+def MOVFUGEr : F4_3<2, 0b101100, 0b1100, "movfuge">;   // mova i/xcc, rs2, rd
+def MOVFUGEi : F4_4<2, 0b101100, 0b1100, "movfuge">;   // mova i/xcc, rs2, rd
+def MOVFLEr  : F4_3<2, 0b101100, 0b1101, "movfle">;    // mova i/xcc, rs2, rd
+def MOVFLEi  : F4_4<2, 0b101100, 0b1101, "movfle">;    // mova i/xcc, rs2, rd
+def MOVFULEr : F4_3<2, 0b101100, 0b1110, "movfule">;   // mova i/xcc, rs2, rd
+def MOVFULEi : F4_4<2, 0b101100, 0b1110, "movfule">;   // mova i/xcc, rs2, rd
+def MOVFOr   : F4_3<2, 0b101100, 0b1111, "movfo">;     // mova i/xcc, rs2, rd
+def MOVFOi   : F4_4<2, 0b101100, 0b1111, "movfo">;     // mova i/xcc, rs2, rd
 
 // FIXME: Section A.36: Move Integer Register on Register Condition (MOVR)
 


Index: llvm/lib/Target/Sparc/SparcV9_F4.td
diff -u llvm/lib/Target/Sparc/SparcV9_F4.td:1.1 llvm/lib/Target/Sparc/SparcV9_F4.td:1.2
--- llvm/lib/Target/Sparc/SparcV9_F4.td:1.1	Wed May 28 22:31:43 2003
+++ llvm/lib/Target/Sparc/SparcV9_F4.td	Mon Jun  2 15:55:14 2003
@@ -53,8 +53,23 @@
   set Inst{4-0} = rs2;
 }
 
+// F4_cc - Common class of instructions that have a cond field
+class F4_cond : F4 {
+  bits<4> cond;
+  set Inst{17-14} = cond;
+}
+
+// F4_cc - Common class of instructions that have cc register as first operand
+class F4_condcc : F4_cond {
+  bits<3> cc;
+  set Inst{18} = cc{2};
+  set Inst{12} = cc{1};
+  set Inst{11} = cc{0};
+}
+
 // Actual F4 instruction classes
 
+// FIXME: order of operands is incorrect!!
 class F4_1<bits<2> opVal, bits<6> op3Val, string name> : F4_rdrs1rs2 {
   bits<2> cc;
 
@@ -66,6 +81,7 @@
   //set Inst{10-5} = dontcare;
 }
 
+// FIXME: order of operands is incorrect!!
 class F4_2<bits<2> opVal, bits<6> op3Val, string name> : F4_rdsimm11rs1 {
   bits<2> cc;
 
@@ -76,15 +92,31 @@
   set Inst{12-11} = cc;
 }
 
-class F4_3<bits<2> opVal, bits<6> op3Val, string name> : F3_rd {
+class F4_3<bits<2> opVal, bits<6> op3Val, bits<4> condVal,
+           string name> : F4_condcc {
   bits<5> rs2;
-  bits<2> cc;
 
   set op = opVal;
   set op3 = op3Val;
+  set cond = condVal;
   set Name = name;
   set Inst{13} = 0; // i bit
-  set Inst{12-11} = cc;
   //set Inst{10-5} = dontcare;
   set Inst{4-0} = rs2;
 }
+
+class F4_4<bits<2> opVal, bits<6> op3Val, bits<4> condVal,
+           string name> : F4_condcc {
+  bits<11> sim11;
+  bits<5>  rd;
+
+  set op = opVal;
+  set op3 = op3Val;
+  set cond = condVal;
+  set Name = name;
+  set Inst{13} = 1; // i bit
+  set Inst{10-0} = sim11;
+}  
+  
+
+// FIXME: F4 classes 4




From brukman at cs.uiuc.edu  Mon Jun  2 16:18:01 2003
From: brukman at cs.uiuc.edu (Misha Brukman)
Date: Mon Jun  2 16:18:01 2003
Subject: [llvm-commits] CVS: llvm/lib/Target/Sparc/SparcInstr.def SparcV9.td SparcV9_F3.td
Message-ID: <200306022117.QAA15590@zion.cs.uiuc.edu>


Changes in directory llvm/lib/Target/Sparc:

SparcInstr.def updated: 1.18 -> 1.19
SparcV9.td updated: 1.9 -> 1.10
SparcV9_F3.td updated: 1.5 -> 1.6

---
Log message:

Added MOVR (move int reg on register condition), aka comparison with zero.
None of these instructions are actually used in the Sparc backend, so no changes
were required in the instruction selector.


---
Diffs of the changes:

Index: llvm/lib/Target/Sparc/SparcInstr.def
diff -u llvm/lib/Target/Sparc/SparcInstr.def:1.18 llvm/lib/Target/Sparc/SparcInstr.def:1.19
--- llvm/lib/Target/Sparc/SparcInstr.def:1.18	Mon Jun  2 15:55:14 2003
+++ llvm/lib/Target/Sparc/SparcInstr.def	Mon Jun  2 16:16:54 2003
@@ -235,12 +235,18 @@
 I(FBO  , "fbo",		2, -1, B18, true , 1, 2,  SPARC_CTI,  M_CC_FLAG | M_BRANCH_FLAG)
 
 // Conditional move on integer comparison with zero.
-I(MOVRZ  , "movrz",	3,  2, B12, true , 0, 2,  SPARC_SINGLE,  M_CONDL_FLAG | M_INT_FLAG)
-I(MOVRLEZ, "movrlez",	3,  2, B12, true , 0, 2,  SPARC_SINGLE,  M_CONDL_FLAG | M_INT_FLAG)
-I(MOVRLZ , "movrlz",	3,  2, B12, true , 0, 2,  SPARC_SINGLE,  M_CONDL_FLAG | M_INT_FLAG)
-I(MOVRNZ , "movrnz",	3,  2, B12, true , 0, 2,  SPARC_SINGLE,  M_CONDL_FLAG | M_INT_FLAG)
-I(MOVRGZ , "movrgz",	3,  2, B12, true , 0, 2,  SPARC_SINGLE,  M_CONDL_FLAG | M_INT_FLAG)
-I(MOVRGEZ, "movrgez",	3,  2, B12, true , 0, 2,  SPARC_SINGLE,  M_CONDL_FLAG | M_INT_FLAG)
+I(MOVRZr  , "movrz",	3,  2, B12, true , 0, 2,  SPARC_SINGLE,  M_CONDL_FLAG | M_INT_FLAG)
+I(MOVRZi  , "movrz",	3,  2, B12, true , 0, 2,  SPARC_SINGLE,  M_CONDL_FLAG | M_INT_FLAG)
+I(MOVRLEZr, "movrlez",	3,  2, B12, true , 0, 2,  SPARC_SINGLE,  M_CONDL_FLAG | M_INT_FLAG)
+I(MOVRLEZi, "movrlez",	3,  2, B12, true , 0, 2,  SPARC_SINGLE,  M_CONDL_FLAG | M_INT_FLAG)
+I(MOVRLZr , "movrlz",	3,  2, B12, true , 0, 2,  SPARC_SINGLE,  M_CONDL_FLAG | M_INT_FLAG)
+I(MOVRLZi , "movrlz",	3,  2, B12, true , 0, 2,  SPARC_SINGLE,  M_CONDL_FLAG | M_INT_FLAG)
+I(MOVRNZr , "movrnz",	3,  2, B12, true , 0, 2,  SPARC_SINGLE,  M_CONDL_FLAG | M_INT_FLAG)
+I(MOVRNZi , "movrnz",	3,  2, B12, true , 0, 2,  SPARC_SINGLE,  M_CONDL_FLAG | M_INT_FLAG)
+I(MOVRGZr , "movrgz",	3,  2, B12, true , 0, 2,  SPARC_SINGLE,  M_CONDL_FLAG | M_INT_FLAG)
+I(MOVRGZi , "movrgz",	3,  2, B12, true , 0, 2,  SPARC_SINGLE,  M_CONDL_FLAG | M_INT_FLAG)
+I(MOVRGEZr, "movrgez",	3,  2, B12, true , 0, 2,  SPARC_SINGLE,  M_CONDL_FLAG | M_INT_FLAG)
+I(MOVRGEZi, "movrgez",	3,  2, B12, true , 0, 2,  SPARC_SINGLE,  M_CONDL_FLAG | M_INT_FLAG)
 
 // Conditional move on integer condition code.
 // The first argument specifies the ICC register: %icc or %xcc


Index: llvm/lib/Target/Sparc/SparcV9.td
diff -u llvm/lib/Target/Sparc/SparcV9.td:1.9 llvm/lib/Target/Sparc/SparcV9.td:1.10
--- llvm/lib/Target/Sparc/SparcV9.td:1.9	Mon Jun  2 15:55:14 2003
+++ llvm/lib/Target/Sparc/SparcV9.td	Mon Jun  2 16:16:54 2003
@@ -448,8 +448,19 @@
 def MOVFOr   : F4_3<2, 0b101100, 0b1111, "movfo">;     // mova i/xcc, rs2, rd
 def MOVFOi   : F4_4<2, 0b101100, 0b1111, "movfo">;     // mova i/xcc, rs2, rd
 
-// FIXME: Section A.36: Move Integer Register on Register Condition (MOVR)
-
+// Section A.36: Move Integer Register on Register Condition (MOVR)
+def MOVRZr   : F3_5<2, 0b101111, 0b001, "movrz">;      // movrz rs1, rs2, rd
+def MOVRZi   : F3_6<2, 0b101111, 0b001, "movrz">;      // movrz rs1, imm, rd
+def MOVRLEZr : F3_5<2, 0b101111, 0b010, "movrlez">;    // movrz rs1, rs2, rd
+def MOVRLEZi : F3_6<2, 0b101111, 0b010, "movrlez">;    // movrz rs1, imm, rd
+def MOVRLZr  : F3_5<2, 0b101111, 0b011, "movrlz">;     // movrz rs1, rs2, rd
+def MOVRLZi  : F3_6<2, 0b101111, 0b011, "movrlz">;     // movrz rs1, imm, rd
+def MOVRNZr  : F3_5<2, 0b101111, 0b101, "movrnz">;     // movrz rs1, rs2, rd
+def MOVRNZi  : F3_6<2, 0b101111, 0b101, "movrnz">;     // movrz rs1, imm, rd
+def MOVRGZr  : F3_5<2, 0b101111, 0b110, "movrgz">;     // movrz rs1, rs2, rd
+def MOVRGZi  : F3_6<2, 0b101111, 0b110, "movrgz">;     // movrz rs1, imm, rd
+def MOVRGEZr : F3_5<2, 0b101111, 0b111, "movrgez">;    // movrz rs1, rs2, rd
+def MOVRGEZi : F3_6<2, 0b101111, 0b111, "movrgez">;    // movrz rs1, imm, rd
 
 // Section A.37: Multiply and Divide (64-bit) - p199
 def MULXr  : F3_1<2, 0b001001, "mulx">;        // mulx  r, r, r


Index: llvm/lib/Target/Sparc/SparcV9_F3.td
diff -u llvm/lib/Target/Sparc/SparcV9_F3.td:1.5 llvm/lib/Target/Sparc/SparcV9_F3.td:1.6
--- llvm/lib/Target/Sparc/SparcV9_F3.td:1.5	Sat May 31 01:25:19 2003
+++ llvm/lib/Target/Sparc/SparcV9_F3.td	Mon Jun  2 16:16:54 2003
@@ -142,6 +142,29 @@
   set Inst{12-0} = simm;
 }
 
+class F3_5<bits<2> opVal, bits<6> op3Val, bits<3> rcondVal,
+           string name> : F3_rs1rs2rd {
+  set op  = opVal;
+  set op3 = op3Val;
+  set Name = name;
+  set Inst{13} = 0;           // i field = 0
+  set Inst{12-10} = rcondVal; // rcond field
+}
+
+class F3_6<bits<2> opVal, bits<6> op3Val, bits<3> rcondVal,
+           string name> : F3_rs1 {
+  bits<10> simm10;
+  bits<5>  rd;
+
+  set op  = opVal;
+  set op3 = op3Val;
+  set Name = name;
+  set Inst{13} = 1;           // i field = 1
+  set Inst{12-10} = rcondVal; // rcond field
+}
+
+//FIXME: classes 7-10 not defined!!
+
 class F3_11<bits<2> opVal, bits<6> op3Val, string name> : F3_rdrs1rs2 {
   bit x;
   set op = opVal;




From lattner at cs.uiuc.edu  Mon Jun  2 17:06:02 2003
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Mon Jun  2 17:06:02 2003
Subject: [llvm-commits] CVS: llvm/lib/CodeGen/InstrSched/SchedGraph.h
Message-ID: <200306022205.RAA13916@apoc.cs.uiuc.edu>


Changes in directory llvm/lib/CodeGen/InstrSched:

SchedGraph.h updated: 1.26 -> 1.27

---
Log message:

Add #include


---
Diffs of the changes:

Index: llvm/lib/CodeGen/InstrSched/SchedGraph.h
diff -u llvm/lib/CodeGen/InstrSched/SchedGraph.h:1.26 llvm/lib/CodeGen/InstrSched/SchedGraph.h:1.27
--- llvm/lib/CodeGen/InstrSched/SchedGraph.h:1.26	Sat May 31 02:37:05 2003
+++ llvm/lib/CodeGen/InstrSched/SchedGraph.h	Mon Jun  2 17:05:13 2003
@@ -17,6 +17,7 @@
 #include "llvm/CodeGen/MachineInstr.h"
 #include "Support/HashExtras.h"
 #include "Support/GraphTraits.h"
+#include "Support/NonCopyable.h"
 
 class Value;
 class Instruction;




From lattner at cs.uiuc.edu  Mon Jun  2 17:08:00 2003
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Mon Jun  2 17:08:00 2003
Subject: [llvm-commits] CVS: llvm/include/llvm/CodeGen/MachineInstr.h
Message-ID: <200306022207.RAA14270@apoc.cs.uiuc.edu>


Changes in directory llvm/include/llvm/CodeGen:

MachineInstr.h updated: 1.100 -> 1.101

---
Log message:

Remove NonCopyable base class to clean up doxygen output


---
Diffs of the changes:

Index: llvm/include/llvm/CodeGen/MachineInstr.h
diff -u llvm/include/llvm/CodeGen/MachineInstr.h:1.100 llvm/include/llvm/CodeGen/MachineInstr.h:1.101
--- llvm/include/llvm/CodeGen/MachineInstr.h:1.100	Sat May 31 02:43:01 2003
+++ llvm/include/llvm/CodeGen/MachineInstr.h	Mon Jun  2 17:07:37 2003
@@ -11,7 +11,6 @@
 
 #include "llvm/Target/MRegisterInfo.h"
 #include "Support/Annotation.h"
-#include "Support/NonCopyable.h"
 #include "Support/iterator"
 #include <set>
 class Value;
@@ -341,8 +340,7 @@
 //      a CALL (if any), and return value of a RETURN.
 //---------------------------------------------------------------------------
 
-class MachineInstr: public NonCopyable {      // Disable copy operations
-
+class MachineInstr {
   MachineOpCode    opCode;              // the opcode
   unsigned         opCodeFlags;         // flags modifying instrn behavior
   std::vector<MachineOperand> operands; // the operands
@@ -355,6 +353,8 @@
   // OperandComplete - Return true if it's illegal to add a new operand
   bool OperandsComplete() const;
 
+  MachineInstr(const MachineInstr &);  // DO NOT IMPLEMENT
+  void operator=(const MachineInstr&); // DO NOT IMPLEMENT
 public:
   MachineInstr(MachineOpCode Opcode, unsigned numOperands);
 




From lattner at cs.uiuc.edu  Mon Jun  2 17:46:02 2003
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Mon Jun  2 17:46:02 2003
Subject: [llvm-commits] CVS: llvm/lib/CodeGen/InstrSched/SchedGraph.h SchedPriorities.h
Message-ID: <200306022245.RAA15616@apoc.cs.uiuc.edu>


Changes in directory llvm/lib/CodeGen/InstrSched:

SchedGraph.h updated: 1.27 -> 1.28
SchedPriorities.h updated: 1.23 -> 1.24

---
Log message:

Remove usage of noncopyable classes to clean up doxygen output.

In particular these classes are the last that link the noncopyable classes
with the hash_map, vector, and list classes.



---
Diffs of the changes:

Index: llvm/lib/CodeGen/InstrSched/SchedGraph.h
diff -u llvm/lib/CodeGen/InstrSched/SchedGraph.h:1.27 llvm/lib/CodeGen/InstrSched/SchedGraph.h:1.28
--- llvm/lib/CodeGen/InstrSched/SchedGraph.h:1.27	Mon Jun  2 17:05:13 2003
+++ llvm/lib/CodeGen/InstrSched/SchedGraph.h	Mon Jun  2 17:45:07 2003
@@ -17,7 +17,6 @@
 #include "llvm/CodeGen/MachineInstr.h"
 #include "Support/HashExtras.h"
 #include "Support/GraphTraits.h"
-#include "Support/NonCopyable.h"
 
 class Value;
 class Instruction;
@@ -46,7 +45,9 @@
 
 //*********************** Public Class Declarations ************************/
 
-class SchedGraphEdge: public NonCopyable {
+class SchedGraphEdge {
+  SchedGraphEdge(const SchedGraphEdge &);  // DO NOT IMPLEMENT
+  void operator=(const SchedGraphEdge &);  // DO NOT IMPLEMENT
 public:
   enum SchedGraphEdgeDepType {
     CtrlDep, MemoryDep, ValueDep, MachineRegister, MachineResource
@@ -55,7 +56,7 @@
     TrueDep = 0x1, AntiDep=0x2, OutputDep=0x4, NonDataDep=0x8
   };
   
-protected:
+private:
   SchedGraphNode*	src;
   SchedGraphNode*	sink;
   SchedGraphEdgeDepType depType;
@@ -132,7 +133,7 @@
 
 
 
-class SchedGraphNode: public NonCopyable {
+class SchedGraphNode {
   unsigned nodeId;
   MachineBasicBlock *MBB;
   const MachineInstr* minstr;
@@ -140,7 +141,9 @@
   std::vector<SchedGraphEdge*> outEdges;
   int origIndexInBB;            // original position of machine instr in BB
   int latency;
-  
+
+  SchedGraphNode(const SchedGraphNode &);  // DO NOT IMPLEMENT
+  void operator=(const SchedGraphNode &);  // DO NOT IMPLEMENT
 public:
   typedef std::vector<SchedGraphEdge*>::      iterator	       iterator;
   typedef std::vector<SchedGraphEdge*>::const_iterator         const_iterator;
@@ -203,15 +206,14 @@
 
 
 
-class SchedGraph :
-  public NonCopyable,
-  private hash_map<const MachineInstr*, SchedGraphNode*>
-{
+class SchedGraph : private hash_map<const MachineInstr*, SchedGraphNode*> {
   MachineBasicBlock &MBB;               // basic blocks for this graph
   SchedGraphNode* graphRoot;		// the root and leaf are not inserted
   SchedGraphNode* graphLeaf;		//  in the hash_map (see getNumNodes())
   
   typedef hash_map<const MachineInstr*, SchedGraphNode*> map_base;
+  SchedGraph(const SchedGraph &);       // DO NOT IMPLEMENT
+  void operator=(const SchedGraph &);   // DO NOT IMPLEMENT
 public:
   using map_base::iterator;
   using map_base::const_iterator;
@@ -327,29 +329,27 @@
 };
 
 
-class SchedGraphSet :  
-  public NonCopyable,
-  private std::vector<SchedGraph*>
-{
+class SchedGraphSet : private std::vector<SchedGraph*> {
 private:
   const Function* method;
-  
+
+  SchedGraphSet(const SchedGraphSet&);    // DO NOT IMPLEMENT
+  void operator=(const SchedGraphSet&);   // DO NOT IMPLEMENT
 public:
   typedef std::vector<SchedGraph*> baseVector;
   using baseVector::iterator;
   using baseVector::const_iterator;
   
 public:
-  /*ctor*/	SchedGraphSet		(const Function * function,
-					 const TargetMachine& target);
-  /*dtor*/	~SchedGraphSet		();
+  SchedGraphSet(const Function *F, const TargetMachine &TM);
+  ~SchedGraphSet();
   
   // Iterators
   using baseVector::begin;
   using baseVector::end;
   
   // Debugging support
-  void		dump	() const;
+  void dump() const;
   
 private:
   inline void	addGraph(SchedGraph* graph) {
@@ -358,8 +358,7 @@
   }
   
   // Graph builder
-  void		buildGraphsForMethod	(const Function *F,
-					 const TargetMachine& target);
+  void buildGraphsForMethod(const Function *F, const TargetMachine &TM);
 };
 
 


Index: llvm/lib/CodeGen/InstrSched/SchedPriorities.h
diff -u llvm/lib/CodeGen/InstrSched/SchedPriorities.h:1.23 llvm/lib/CodeGen/InstrSched/SchedPriorities.h:1.24
--- llvm/lib/CodeGen/InstrSched/SchedPriorities.h:1.23	Sat Dec 28 21:12:55 2002
+++ llvm/lib/CodeGen/InstrSched/SchedPriorities.h	Mon Jun  2 17:45:07 2003
@@ -63,7 +63,9 @@
   return np1->delay < np2->delay;
 }
 
-class NodeHeap: public std::list<NodeDelayPair*>, public NonCopyable {
+class NodeHeap : public std::list<NodeDelayPair*> {
+  NodeHeap(const NodeHeap&);          // DO NOT IMPLEMENT
+  void operator=(const NodeHeap&);    // DO NOT IMPLEMENT
 public:
   typedef std::list<NodeDelayPair*>::iterator iterator;
   typedef std::list<NodeDelayPair*>::const_iterator const_iterator;
@@ -115,7 +117,9 @@
 };
 
 
-class SchedPriorities: public NonCopyable {
+class SchedPriorities {
+  SchedPriorities(const SchedPriorities&); // DO NOT IMPLEMENT
+  void operator=(const SchedPriorities &); // DO NOT IMPLEMENT
 public:
   SchedPriorities(const Function *F, const SchedGraph *G,
                   FunctionLiveVarInfo &LVI);




From lattner at cs.uiuc.edu  Mon Jun  2 17:58:02 2003
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Mon Jun  2 17:58:02 2003
Subject: [llvm-commits] CVS: llvm/lib/CodeGen/Mapping/FInfo.cpp
Message-ID: <200306022257.RAA23811@apoc.cs.uiuc.edu>


Changes in directory llvm/lib/CodeGen/Mapping:

FInfo.cpp updated: 1.1 -> 1.2

---
Log message:

Minor cleanups.
This pass should be moved to lib/Target/Sparc since it's sparc specific
It also needs a file comment.



---
Diffs of the changes:

Index: llvm/lib/CodeGen/Mapping/FInfo.cpp
diff -u llvm/lib/CodeGen/Mapping/FInfo.cpp:1.1 llvm/lib/CodeGen/Mapping/FInfo.cpp:1.2
--- llvm/lib/CodeGen/Mapping/FInfo.cpp:1.1	Tue Aug 27 17:47:09 2002
+++ llvm/lib/CodeGen/Mapping/FInfo.cpp	Mon Jun  2 17:57:41 2003
@@ -2,19 +2,17 @@
 #include "llvm/Pass.h"
 #include "llvm/Module.h"
 
-
 namespace {
   class FunctionInfo : public Pass {
     std::ostream &Out;
   public:
     FunctionInfo(std::ostream &out) : Out(out){}
-    const char* getPassName() const{return "Sparc FunctionInfo";}
+    const char* getPassName() const{ return "Sparc FunctionInfo"; }
     bool run(Module &M);
   private:
-    void FunctionInfo::writePrologue(const char *area,
-					const char *label);
-    void FunctionInfo::writeEpilogue(const char *area,
-					const char *label);
+    void writePrologue(const char *area, const char *label);
+    void writeEpilogue(const char *area, const char *label);
+                       
   };
 }
 




From brukman at cs.uiuc.edu  Mon Jun  2 18:28:02 2003
From: brukman at cs.uiuc.edu (Misha Brukman)
Date: Mon Jun  2 18:28:02 2003
Subject: [llvm-commits] CVS: llvm/lib/CodeGen/Mapping/FInfo.cpp
Message-ID: <200306022327.SAA15825@zion.cs.uiuc.edu>


Changes in directory llvm/lib/CodeGen/Mapping:

FInfo.cpp (r1.2) removed

---
Log message:

Moved FInfo.cpp to lib/Target/Sparc as it is Sparc-specific.


---
Diffs of the changes:



From brukman at cs.uiuc.edu  Mon Jun  2 19:08:00 2003
From: brukman at cs.uiuc.edu (Misha Brukman)
Date: Mon Jun  2 19:08:00 2003
Subject: [llvm-commits] CVS: llvm/utils/TableGen/CodeEmitterGen.cpp
Message-ID: <200306030007.TAA19556@zion.cs.uiuc.edu>


Changes in directory llvm/utils/TableGen:

CodeEmitterGen.cpp updated: 1.5 -> 1.6

---
Log message:

Stop ignoring the `cc' field, we actually use it now (e.g. conditional move)


---
Diffs of the changes:

Index: llvm/utils/TableGen/CodeEmitterGen.cpp
diff -u llvm/utils/TableGen/CodeEmitterGen.cpp:1.5 llvm/utils/TableGen/CodeEmitterGen.cpp:1.6
--- llvm/utils/TableGen/CodeEmitterGen.cpp:1.5	Fri May 30 15:32:01 2003
+++ llvm/utils/TableGen/CodeEmitterGen.cpp	Mon Jun  2 19:07:17 2003
@@ -105,8 +105,7 @@
           }
         } 
       } else {
-        if (Vals[f].getName() == "annul" || Vals[f].getName() == "cc" ||
-            Vals[f].getName() == "predict")
+        if (Vals[f].getName() == "annul" || Vals[f].getName() == "predict")
           --Offset;
       }
     }




From brukman at cs.uiuc.edu  Mon Jun  2 19:57:01 2003
From: brukman at cs.uiuc.edu (Misha Brukman)
Date: Mon Jun  2 19:57:01 2003
Subject: [llvm-commits] CVS: llvm/utils/vim/llvm.vim
Message-ID: <200306030056.TAA20285@zion.cs.uiuc.edu>


Changes in directory llvm/utils/vim:

llvm.vim updated: 1.4 -> 1.5

---
Log message:

* Added the `to' keyword, as in `cast <type> <data> to <type>'.
* Gave the file a maintainer.
* Cleaned up the layout somewhat.


---
Diffs of the changes:

Index: llvm/utils/vim/llvm.vim
diff -u llvm/utils/vim/llvm.vim:1.4 llvm/utils/vim/llvm.vim:1.5
--- llvm/utils/vim/llvm.vim:1.4	Wed May  7 21:41:11 2003
+++ llvm/utils/vim/llvm.vim	Mon Jun  2 19:56:09 2003
@@ -1,7 +1,7 @@
 " Vim syntax file
-" Language:	llvm
-" Maintainer:	?
-" Updated:	2003-04-22
+" Language:   llvm
+" Maintainer: The LLVM team, http://llvm.cs.uiuc.edu/
+" Updated:    2003-06-02
 
 if version < 600
   syntax clear
@@ -20,7 +20,7 @@
 syn keyword llvmStatement and or xor
 syn keyword llvmStatement setne seteq setlt setgt setle setge
 
-syn keyword llvmStatement phi call cast shl shr va_arg
+syn keyword llvmStatement phi call cast to shl shr va_arg
 syn keyword llvmStatement ret br switch invoke
 syn keyword llvmStatement malloc alloca free load store getelementptr
 
@@ -32,12 +32,12 @@
 syn keyword llvmStatement big little
 
 "syn match llvmFunction /%[a-zA-Z\$._\-][a-zA-Z\$._\-0-9]*/
-syn match llvmNumber /\<\d\+\>/
-syn match llvmNumber /\<\d\+\.\d*\>/
+syn match  llvmNumber /\<\d\+\>/
+syn match  llvmNumber /\<\d\+\.\d*\>/
 
-syn match llvmComment /;.*$/
+syn match  llvmComment /;.*$/
 syn region llvmString start=/"/ skip=/\\"/ end=/"/
-syn match llvmLabel /[\-a-zA-Z\$._0-9]*:/
+syn match  llvmLabel /[\-a-zA-Z\$._0-9]*:/
 
 
 if version >= 508 || !exists("did_c_syn_inits")




From brukman at cs.uiuc.edu  Mon Jun  2 19:58:01 2003
From: brukman at cs.uiuc.edu (Misha Brukman)
Date: Mon Jun  2 19:58:01 2003
Subject: [llvm-commits] CVS: llvm/utils/emacs/llvm-mode.el
Message-ID: <200306030057.TAA20309@zion.cs.uiuc.edu>


Changes in directory llvm/utils/emacs:

llvm-mode.el updated: 1.4 -> 1.5

---
Log message:

Added the `to' keyword as in `cast <type> <data> to <type>'.
Cleaned up the header of the file (comments/description/etc).


---
Diffs of the changes:

Index: llvm/utils/emacs/llvm-mode.el
diff -u llvm/utils/emacs/llvm-mode.el:1.4 llvm/utils/emacs/llvm-mode.el:1.5
--- llvm/utils/emacs/llvm-mode.el:1.4	Wed May  7 21:41:08 2003
+++ llvm/utils/emacs/llvm-mode.el	Mon Jun  2 19:57:41 2003
@@ -1,9 +1,6 @@
-;; Author: Misha Brukman <brukman at cs.uiuc.edu>
-;; Description:
-;;         Major mode for the LLVM assembler language.
-;; Updated:
-;;         Apr 22, 2003
-;; Code:
+;; Author:      Misha Brukman <brukman at cs.uiuc.edu>
+;; Description: Major mode for the LLVM assembler language.
+;; Updated:     2003-06-02
 
 ;; Create mode-specific tables.
 (defvar llvm-mode-syntax-table nil
@@ -34,7 +31,7 @@
    ;; Arithmetic and Logical Operators
    '("add\\|sub\\|mul\\|div\\|rem\\|and\\|or\\|xor\\|set\\(ne\\|eq\\|lt\\|gt\\|le\\|ge\\)" . font-lock-keyword-face)
    ;; Special instructions
-   '("phi\\|call\\|cast\\|shl\\|shr\\|va_arg" . font-lock-keyword-face)
+   '("phi\\|call\\|cast\\|to\\|shl\\|shr\\|va_arg" . font-lock-keyword-face)
    ;; Control instructions
    '("ret\\|br\\|switch\\|invoke" . font-lock-keyword-face)
    ;; Memory operators




From brukman at cs.uiuc.edu  Mon Jun  2 20:00:01 2003
From: brukman at cs.uiuc.edu (Misha Brukman)
Date: Mon Jun  2 20:00:01 2003
Subject: [llvm-commits] CVS: llvm/utils/emacs/llvm-mode.el
Message-ID: <200306030059.TAA20332@zion.cs.uiuc.edu>


Changes in directory llvm/utils/emacs:

llvm-mode.el updated: 1.5 -> 1.6

---
Log message:

Removing personal name from source code.


---
Diffs of the changes:

Index: llvm/utils/emacs/llvm-mode.el
diff -u llvm/utils/emacs/llvm-mode.el:1.5 llvm/utils/emacs/llvm-mode.el:1.6
--- llvm/utils/emacs/llvm-mode.el:1.5	Mon Jun  2 19:57:41 2003
+++ llvm/utils/emacs/llvm-mode.el	Mon Jun  2 19:59:24 2003
@@ -1,4 +1,4 @@
-;; Author:      Misha Brukman <brukman at cs.uiuc.edu>
+;; Maintainer:  The LLVM team, http://llvm.cs.uiuc.edu/
 ;; Description: Major mode for the LLVM assembler language.
 ;; Updated:     2003-06-02
 




From brukman at cs.uiuc.edu  Mon Jun  2 20:05:01 2003
From: brukman at cs.uiuc.edu (Misha Brukman)
Date: Mon Jun  2 20:05:01 2003
Subject: [llvm-commits] CVS: llvm/lib/Target/Sparc/SparcV9_F2.td
Message-ID: <200306030104.UAA20371@zion.cs.uiuc.edu>


Changes in directory llvm/lib/Target/Sparc:

SparcV9_F2.td updated: 1.1 -> 1.2

---
Log message:

The rd field goes after the immediate field in format 2.1 instructions.


---
Diffs of the changes:

Index: llvm/lib/Target/Sparc/SparcV9_F2.td
diff -u llvm/lib/Target/Sparc/SparcV9_F2.td:1.1 llvm/lib/Target/Sparc/SparcV9_F2.td:1.2
--- llvm/lib/Target/Sparc/SparcV9_F2.td:1.1	Wed May 28 22:31:43 2003
+++ llvm/lib/Target/Sparc/SparcV9_F2.td	Mon Jun  2 20:04:04 2003
@@ -13,8 +13,8 @@
 
 // Format 2.1 instructions
 class F2_1<string name> : F2 {
-  bits<5> rd;
   bits<22> imm;
+  bits<5> rd;
 
   set Name = name;
   set Inst{29-25} = rd;
@@ -48,7 +48,6 @@
 }
 
 class F2_4<bits<3> rcond, string name> : F2_br { // Format 2.4 instructions
-  // Variables exposed by the instruction...
   bit        predict;
   bits<5>    rs1;
   bits<16>   disp;




From brukman at cs.uiuc.edu  Mon Jun  2 20:13:02 2003
From: brukman at cs.uiuc.edu (Misha Brukman)
Date: Mon Jun  2 20:13:02 2003
Subject: [llvm-commits] CVS: llvm/lib/Target/Sparc/SparcV9_F3.td
Message-ID: <200306030112.UAA20668@zion.cs.uiuc.edu>


Changes in directory llvm/lib/Target/Sparc:

SparcV9_F3.td updated: 1.6 -> 1.7

---
Log message:

* Removed unused classes: the rd field is always mentioned as the last reg.
* Added new classes which start building from rs1, adding rs2, and then rd.
* Fixed order of operands in classes 3.11, 3.12, 3.16, and 3.17 .
* Fixed comments to reflect Real Life (tm).
* Removed "don't care" commented out assignments and dead classes (#if 0).


---
Diffs of the changes:

Index: llvm/lib/Target/Sparc/SparcV9_F3.td
diff -u llvm/lib/Target/Sparc/SparcV9_F3.td:1.6 llvm/lib/Target/Sparc/SparcV9_F3.td:1.7
--- llvm/lib/Target/Sparc/SparcV9_F3.td:1.6	Mon Jun  2 16:16:54 2003
+++ llvm/lib/Target/Sparc/SparcV9_F3.td	Mon Jun  2 20:11:58 2003
@@ -14,45 +14,15 @@
   set Inst{24-19} = op3;
 }
 
-class F3_rd : F3 {
-  bits<5> rd;
-  set Inst{29-25} = rd;
-}
-
-class F3_rdsimm13 : F3_rd {
-  bits<13> simm13;
-  set Inst{12-0} = simm13;
-}
-
-class F3_rdsimm13rs1 : F3_rdsimm13 {
-  bits<5> rs1;
-  set Inst{18-14} = rs1;
-}
-
-// F3_rdrs1 - Common superclass of instructions that use rd & rs1
-class F3_rdrs1 : F3_rd {
-  bits<5> rs1;
-  set Inst{18-14} = rs1;
-}
-
-// F3_rs1rdrs2 - Common superclass of instructions with rd, rs1, & rs2 fields
-class F3_rdrs1rs2 : F3_rdrs1 {
-  bits<5> rs2;
-  set Inst{4-0} = rs2;
-}
-
-// F3_rs1 - Common class of instructions that do not have an rd field,
-// but start at rs1
+// F3_rs1 - Common class of instructions that have an rs1 field
 class F3_rs1 : F3 {
   bits<5> rs1;
-  //set Inst{29-25} = dontcare;
   set Inst{18-14} = rs1;
 }
 
 // F3_rs1rs2 - Common class of instructions that only have rs1 and rs2 fields
 class F3_rs1rs2 : F3_rs1 {
   bits<5> rs2;
-  //set Inst{12-5} = dontcare;
   set Inst{4-0} = rs2;
 }
 
@@ -74,6 +44,12 @@
   set Inst{29-25} = rd;
 }
 
+// F3_rs1rd - Common class of instructions that have an rs1 and rd fields
+class F3_rs1rd : F3_rs1 {
+  bits<5> rd;
+  set Inst{29-25} = rd;
+}
+
 // F3_rs2 - Common class of instructions that don't use an rs1
 class F3_rs2 : F3 {
   bits<5> rs2;
@@ -86,6 +62,12 @@
   set Inst{29-25} = rd;
 }
 
+// F3_rd - Common class of instructions that only have an rd field
+class F3_rd : F3 {
+  bits<5> rd;
+  set Inst{29-25} = rd;
+}
+
 
 // Specific F3 classes...
 //
@@ -105,26 +87,6 @@
   set Inst{13} = 1;   // i field = 1
 }
 
-#if 0
-// The ordering is actually incorrect in these: in the assemble syntax,
-// rd appears last!
-class F3_1a<bits<2> opVal, bits<6> op3val, string name> : F3_rdrs1rs2 {
-  set op  = opVal;
-  set op3 = op3val;
-  set Name = name;
-  set Inst{13} = 0;   // i field = 0
-  //set Inst{12-5} = dontcare;
-}
-
-class F3_2a<bits<2> opVal, bits<6> op3val, string name> : F3_rdsimm13rs1 {
-  set op  = opVal;
-  set op3 = op3val;
-  set Name = name;
-  set Inst{13} = 1;   // i field = 1
-}
-#endif
-
-
 class F3_3<bits<2> opVal, bits<6> op3val, string name> : F3_rs1rs2 {
   set op   = opVal;
   set op3  = op3val;
@@ -165,7 +127,7 @@
 
 //FIXME: classes 7-10 not defined!!
 
-class F3_11<bits<2> opVal, bits<6> op3Val, string name> : F3_rdrs1rs2 {
+class F3_11<bits<2> opVal, bits<6> op3Val, string name> : F3_rs1rs2rd {
   bit x;
   set op = opVal;
   set op3 = op3Val;
@@ -175,14 +137,14 @@
   //set Inst{11-5} = dontcare;
 }
 
-class F3_12<bits<2> opVal, bits<6> op3Val, string name> : F3_rd {
+class F3_12<bits<2> opVal, bits<6> op3Val, string name> : F3_rs1 {
   bits<5> shcnt;
-  bits<5> rs1;
+  bits<5> rd;
 
   set op  = opVal;
   set op3 = op3Val;
   set Name = name;
-  set Inst{18-14} = rs1;
+  set Inst{29-25} = rd;
   set Inst{13} = 1; // i field = 1
   set Inst{12} = 0; // x field = 0
   //set Inst{11-5} = dontcare;
@@ -213,14 +175,14 @@
 }
   
 class F3_16<bits<2> opVal,  bits<6> op3Val,
-            bits<9> opfval, string name> : F3_rdrs1rs2 {
+            bits<9> opfval, string name> : F3_rs1rs2rd {
   set op  = opVal;
   set op3 = op3Val;
   set Name = name;
   set Inst{13-5} = opfval;
 }
 
-class F3_17<bits<2> opVal, bits<6> op3Val, string name> : F3_rdrs1 {
+class F3_17<bits<2> opVal, bits<6> op3Val, string name> : F3_rs1rd {
   set op = opVal;
   set op3 = op3Val;
   set Name = name;




From brukman at cs.uiuc.edu  Mon Jun  2 20:15:01 2003
From: brukman at cs.uiuc.edu (Misha Brukman)
Date: Mon Jun  2 20:15:01 2003
Subject: [llvm-commits] CVS: llvm/lib/Target/Sparc/SparcV9_F4.td
Message-ID: <200306030114.UAA20695@zion.cs.uiuc.edu>


Changes in directory llvm/lib/Target/Sparc:

SparcV9_F4.td updated: 1.2 -> 1.3

---
Log message:

* Removed unused classes (rd field is always mentioned last); fixed comments.
* Added instruction classes which start building from rs1, then rs2, and rd.
* Fixed order of operands in classes 4.1 and 4.2; added 4.6 .


---
Diffs of the changes:

Index: llvm/lib/Target/Sparc/SparcV9_F4.td
diff -u llvm/lib/Target/Sparc/SparcV9_F4.td:1.2 llvm/lib/Target/Sparc/SparcV9_F4.td:1.3
--- llvm/lib/Target/Sparc/SparcV9_F4.td:1.2	Mon Jun  2 15:55:14 2003
+++ llvm/lib/Target/Sparc/SparcV9_F4.td	Mon Jun  2 20:13:53 2003
@@ -11,48 +11,35 @@
   set Inst{24-19} = op3;
 }
 
-class F4_rd : F4 {
-  bits<5> rd;
-  set Inst{29-25} = rd;
-}
-
-class F4_rdsimm11 : F4_rd {
-  bits<11> simm11;
-  set Inst{10-0} = simm11;
-}
-
-class F4_rdsimm11rs1 : F4_rdsimm11 {
-  bits<5> rs1;
-  set Inst{18-14} = rs1;
-}
-
-// F4_rdrs1 - Common superclass of instructions that use rd & rs1
-class F4_rdrs1 : F4_rd {
-  bits<5> rs1;
-  set Inst{18-14} = rs1;
-}
-
-// F4_rs1rdrs2 - Common superclass of instructions with rd, rs1, & rs2 fields
-class F4_rdrs1rs2 : F4_rdrs1 {
-  bits<5> rs2;
-  set Inst{4-0} = rs2;
-}
-
-// F4_rs1 - Common class of instructions that do not have an rd field,
-// but start at rs1
+// F4_rs1 - Common class of instructions that use an rs1 field
 class F4_rs1 : F4 {
   bits<5> rs1;
   //set Inst{29-25} = dontcare;
   set Inst{18-14} = rs1;
 }
 
-// F4_rs1rs2 - Common class of instructions that only have rs1 and rs2 fields
+// F4_rs1rs2 - Common class of instructions that have rs1 and rs2 fields
 class F4_rs1rs2 : F4_rs1 {
   bits<5> rs2;
   //set Inst{12-5} = dontcare;
   set Inst{4-0} = rs2;
 }
 
+// F4_rs1rs2rd - Common class of instructions that have 3 register operands
+class F4_rs1rs2rd : F4_rs1rs2 {
+  bits<5> rd;
+  set Inst{29-25} = rd;
+}
+
+// F4_rs1rs2rd - Common class of instructions that have 2 reg and 1 imm operand
+class F4_rs1simm11rd : F4_rs1 {
+  bits<11> simm11;
+  bits<5>  rd;
+
+  set Inst{10-0}  = simm11;
+  set Inst{29-25} = rd;
+}
+
 // F4_cc - Common class of instructions that have a cond field
 class F4_cond : F4 {
   bits<4> cond;
@@ -68,9 +55,8 @@
 }
 
 // Actual F4 instruction classes
-
-// FIXME: order of operands is incorrect!!
-class F4_1<bits<2> opVal, bits<6> op3Val, string name> : F4_rdrs1rs2 {
+//
+class F4_1<bits<2> opVal, bits<6> op3Val, string name> : F4_rs1rs2rd {
   bits<2> cc;
 
   set op = opVal;
@@ -81,8 +67,7 @@
   //set Inst{10-5} = dontcare;
 }
 
-// FIXME: order of operands is incorrect!!
-class F4_2<bits<2> opVal, bits<6> op3Val, string name> : F4_rdsimm11rs1 {
+class F4_2<bits<2> opVal, bits<6> op3Val, string name> : F4_rs1simm11rd {
   bits<2> cc;
 
   set op = opVal;
@@ -110,13 +95,24 @@
   bits<11> sim11;
   bits<5>  rd;
 
-  set op = opVal;
-  set op3 = op3Val;
+  set op   = opVal;
+  set op3  = op3Val;
   set cond = condVal;
   set Name = name;
   set Inst{13} = 1; // i bit
   set Inst{10-0} = sim11;
 }  
   
+// FIXME: class F4_5
+
+class F4_6<bits<2> opVal, bits<6> op3Val, bits<3> rcondVal,
+           bits<5> opf_lowVal, string name> : F4_rs1rs2rd {
+  set op  = opVal;
+  set op3 = op3Val;
+  set Name = name;
+  set Inst{13} = 0;
+  set Inst{12-10} = rcondVal;
+  set Inst{9-5} = opf_lowVal;
+}
 
-// FIXME: F4 classes 4
+// FIXME: F4 classes 7-9




From brukman at cs.uiuc.edu  Mon Jun  2 20:17:01 2003
From: brukman at cs.uiuc.edu (Misha Brukman)
Date: Mon Jun  2 20:17:01 2003
Subject: [llvm-commits] CVS: llvm/lib/Target/Sparc/SparcV9.td
Message-ID: <200306030116.UAA20744@zion.cs.uiuc.edu>


Changes in directory llvm/lib/Target/Sparc:

SparcV9.td updated: 1.10 -> 1.11

---
Log message:

* Added section A.34: Move FP register on int reg condition (FMOVr)
* Labeled sections that are not currently used in the Sparc backend as not
  requiring completion at this time.


---
Diffs of the changes:

Index: llvm/lib/Target/Sparc/SparcV9.td
diff -u llvm/lib/Target/Sparc/SparcV9.td:1.10 llvm/lib/Target/Sparc/SparcV9.td:1.11
--- llvm/lib/Target/Sparc/SparcV9.td:1.10	Mon Jun  2 16:16:54 2003
+++ llvm/lib/Target/Sparc/SparcV9.td	Mon Jun  2 20:16:27 2003
@@ -252,10 +252,10 @@
 // FIXME: A.21: Flush Register Windows - p169
 
 // A.22: Illegal instruction Trap - p170
-// Not used
+// Not currently used
 
 // A.23: Implementation-Dependent Instructions - p171
-// Not used
+// Not currently used
 
 // Section A.24: Jump and Link - p172
 // Mimicking the Sparc's instr def...
@@ -337,8 +337,8 @@
 // Section A.32: Memory Barrier - p186
 // Not currently used in the Sparc backend
 
-#if 0
 // Section A.33: Move Floating-Point Register on Condition (FMOVcc)
+#if 0
 // For integer condition codes
 def FMOVA   : F4_7<2, 0b110101, 0b1000, "fmova">;        // fmova r, r
 def FMOVN   : F4_7<2, 0b110101, 0b0000, "fmovn">;        // fmovn r, r
@@ -376,7 +376,27 @@
 def FMOVFO   : F4_7<2, 0b110101, 0b1111, "fmovfo">;      // fmovfo r, r
 #endif
 
-// FIXME: Section A.34: Move F-P Register on Integer Register (FMOVr)
+// Section A.34: Move FP Register on Integer Register condition (FMOVr) - p192
+def FMOVRSZ   : F4_6<2, 0b110101, 0b001, 0b00101, "fmovrsz">;  //fmovsrz r,r,rd
+def FMOVRSLEZ : F4_6<2, 0b110101, 0b010, 0b00101, "fmovrslez">;//fmovsrz r,r,rd
+def FMOVRSLZ  : F4_6<2, 0b110101, 0b011, 0b00101, "fmovrslz">; //fmovsrz r,r,rd
+def FMOVRSNZ  : F4_6<2, 0b110101, 0b101, 0b00101, "fmovrsne">; //fmovsrz r,r,rd
+def FMOVRSGZ  : F4_6<2, 0b110101, 0b110, 0b00101, "fmovrsgz">; //fmovsrz r,r,rd
+def FMOVRSGEZ : F4_6<2, 0b110101, 0b111, 0b00101, "fmovrsgez">;//fmovsrz r,r,rd
+
+def FMOVRDZ   : F4_6<2, 0b110101, 0b001, 0b00110, "fmovrdz">;  //fmovsrz r,r,rd
+def FMOVRDLEZ : F4_6<2, 0b110101, 0b010, 0b00110, "fmovrdlez">;//fmovsrz r,r,rd
+def FMOVRDLZ  : F4_6<2, 0b110101, 0b011, 0b00110, "fmovrdlz">; //fmovsrz r,r,rd
+def FMOVRDNZ  : F4_6<2, 0b110101, 0b101, 0b00110, "fmovrdne">; //fmovsrz r,r,rd
+def FMOVRDGZ  : F4_6<2, 0b110101, 0b110, 0b00110, "fmovrdgz">; //fmovsrz r,r,rd
+def FMOVRDGEZ : F4_6<2, 0b110101, 0b111, 0b00110, "fmovrdgez">;//fmovsrz r,r,rd
+
+def FMOVRQZ   : F4_6<2, 0b110101, 0b001, 0b00111, "fmovrqz">;  //fmovsrz r,r,rd
+def FMOVRQLEZ : F4_6<2, 0b110101, 0b010, 0b00111, "fmovrqlez">;//fmovsrz r,r,rd
+def FMOVRQLZ  : F4_6<2, 0b110101, 0b011, 0b00111, "fmovrqlz">; //fmovsrz r,r,rd
+def FMOVRQNZ  : F4_6<2, 0b110101, 0b101, 0b00111, "fmovrqne">; //fmovsrz r,r,rd
+def FMOVRQGZ  : F4_6<2, 0b110101, 0b110, 0b00111, "fmovrqgz">; //fmovsrz r,r,rd
+def FMOVRQGEZ : F4_6<2, 0b110101, 0b111, 0b00111, "fmovrqgez">;//fmovsrz r,r,rd
 
 
 // Section A.35: Move Integer Register on Condition (MOVcc) - p194
@@ -487,7 +507,8 @@
 }
 #endif
 
-// Section A.39: FIXME
+// Section A.39: Multiply Step - p202
+// Not currently used in the Sparc backend
 
 // Section A.40: No operation - p204
 // NOP is really a pseudo-instruction (special case of SETHI)
@@ -499,9 +520,14 @@
   }
 }
 
-// Section A.41: FIXME
-// Section A.42: FIXME
-// Section A.43: FIXME
+// Section A.41: Population Count - p205
+// Not currently used in the Sparc backend
+
+// Section A.42: Prefetch Data - p206
+// Not currently used in the Sparc backend
+
+// Section A.43: Read Privileged Register - p211
+// Not currently used in the Sparc backend
 
 // Section A.44: Read State Register
 // The only instr from this section currently used is RDCCR
@@ -570,9 +596,11 @@
 def SRLXi6 : F3_13<2, 0b100110, "srlx">;                 // srlx r, shcnt64, r
 def SRAXi6 : F3_13<2, 0b100111, "srax">;                 // srax r, shcnt64, r
 
-// Section A.50: FIXME
+// Section A.50: Sofware-Initiated Reset - p223
+// Not currently used in the Sparc backend
 
-// Section A.51: FIXME
+// Section A.51: Store Barrier - p224
+// Not currently used in the Sparc backend
 
 // Section A.52: Store Floating-point -p225
 def STFr  : F3_1<3, 0b100100, "st">;                      // st r, [r+r]
@@ -593,7 +621,8 @@
 def STXFSRr : F3_1<3, 0b100101, "stq">;                   // stx r, [r+r]
 def STXFSRi : F3_2<3, 0b100101, "stq">;                   // stx r, [r+i]
 
-// Section A.53: FIXME
+// Section A.53: Store Floating-Point into Alternate Space - p227
+// Not currently used in the Sparc backend
 
 // Section A.54: Store Integer - p229
 def STBr : F3_1<3, 0b000101, "stb">;                     // stb r, [r+r]
@@ -605,8 +634,8 @@
 def STXr : F3_1<3, 0b001110, "stb">;                     // stb r, [r+r]
 def STXi : F3_2<3, 0b001110, "stb">;                     // stb r, [r+i]
 
-// Floating point store...
-// Section A.55: FIXME
+// Section A.55: Store Integer into Alternate Space - p231
+// Not currently used in the Sparc backend
 
 // Section A.56: Subtract - p233
 def SUBr    : F3_1<2, 0b000100, "sub">;                   // sub r, r, r




From brukman at cs.uiuc.edu  Mon Jun  2 22:19:01 2003
From: brukman at cs.uiuc.edu (Misha Brukman)
Date: Mon Jun  2 22:19:01 2003
Subject: [llvm-commits] CVS: llvm/lib/CodeGen/InstrSelection/InstrSelectionSupport.cpp
Message-ID: <200306030318.WAA23591@zion.cs.uiuc.edu>


Changes in directory llvm/lib/CodeGen/InstrSelection:

InstrSelectionSupport.cpp updated: 1.48 -> 1.49

---
Log message:

Moved code to modify the opcode from 'reg' to 'imm' form to a more logical place.


---
Diffs of the changes:

Index: llvm/lib/CodeGen/InstrSelection/InstrSelectionSupport.cpp
diff -u llvm/lib/CodeGen/InstrSelection/InstrSelectionSupport.cpp:1.48 llvm/lib/CodeGen/InstrSelection/InstrSelectionSupport.cpp:1.49
--- llvm/lib/CodeGen/InstrSelection/InstrSelectionSupport.cpp:1.48	Sat May 31 02:38:37 2003
+++ llvm/lib/CodeGen/InstrSelection/InstrSelectionSupport.cpp	Mon Jun  2 22:18:20 2003
@@ -186,12 +186,6 @@
                                       immedValue);
             if (opType == MachineOperand::MO_VirtualRegister)
               constantThatMustBeLoaded = true;
-            else {
-              // The optype has changed from being a register to an immediate
-              // This means we need to change the opcode, e.g. ADDr -> ADDi
-              unsigned newOpcode = convertOpcodeFromRegToImm(opCode);
-              minstr->setOpcode(newOpcode);
-            }
           }
         }
       else
@@ -219,21 +213,18 @@
                 ? (Value*)ConstantSInt::get(Type::LongTy, immedValue)
                 : (Value*)ConstantUInt::get(Type::ULongTy,(uint64_t)immedValue);
             }
-          else 
-            {
-              // The optype has changed from being a register to an immediate
-              // This means we need to change the opcode, e.g. ADDr -> ADDi
-              unsigned newOpcode = convertOpcodeFromRegToImm(opCode);
-              minstr->setOpcode(newOpcode);
-            }
         }
 
       if (opType == MachineOperand::MO_MachineRegister)
         minstr->SetMachineOperandReg(op, machineRegNum);
       else if (opType == MachineOperand::MO_SignExtendedImmed ||
-               opType == MachineOperand::MO_UnextendedImmed)
+               opType == MachineOperand::MO_UnextendedImmed) {
         minstr->SetMachineOperandConst(op, opType, immedValue);
-      else if (constantThatMustBeLoaded ||
+        // The optype has changed from being a register to an immediate
+        // This means we need to change the opcode, e.g. ADDr -> ADDi
+        unsigned newOpcode = convertOpcodeFromRegToImm(opCode);
+        minstr->setOpcode(newOpcode);
+      } else if (constantThatMustBeLoaded ||
                (opValue && isa<GlobalValue>(opValue)))
         { // opValue is a constant that must be explicitly loaded into a reg
           assert(opValue);




From brukman at cs.uiuc.edu  Mon Jun  2 22:21:00 2003
From: brukman at cs.uiuc.edu (Misha Brukman)
Date: Mon Jun  2 22:21:00 2003
Subject: [llvm-commits] CVS: llvm/lib/Target/Sparc/SparcV9_F3.td SparcV9.td
Message-ID: <200306030320.WAA23622@zion.cs.uiuc.edu>


Changes in directory llvm/lib/Target/Sparc:

SparcV9_F3.td updated: 1.7 -> 1.8
SparcV9.td updated: 1.11 -> 1.12

---
Log message:

Store instructions are different from other Format 3.1/3.2 instructions in that
they prefer the destination register to be last. Thus, two new classes were made
for them that accomodate for having this layout of operands (F3_1rd, F3_2rd).


---
Diffs of the changes:

Index: llvm/lib/Target/Sparc/SparcV9_F3.td
diff -u llvm/lib/Target/Sparc/SparcV9_F3.td:1.7 llvm/lib/Target/Sparc/SparcV9_F3.td:1.8
--- llvm/lib/Target/Sparc/SparcV9_F3.td:1.7	Mon Jun  2 20:11:58 2003
+++ llvm/lib/Target/Sparc/SparcV9_F3.td	Mon Jun  2 22:20:14 2003
@@ -62,12 +62,31 @@
   set Inst{29-25} = rd;
 }
 
-// F3_rd - Common class of instructions that only have an rd field
+// F3_rd - Common class of instructions that have an rd field
 class F3_rd : F3 {
   bits<5> rd;
   set Inst{29-25} = rd;
 }
 
+// F3_rdrs1 - Common class of instructions that have rd and rs1 fields
+class F3_rdrs1 : F3_rd {
+  bits<5> rs1;
+  set Inst{18-14} = rs1;
+}
+
+// F3_rdrs1simm13 - Common class of instructions that have rd, rs1, and simm13
+class F3_rdrs1simm13 : F3_rd {
+  bits<13> simm13;
+  set Inst{12-0} = simm13;
+}
+
+
+// F3_rdrs1rs2 - Common class of instructions that have rd, rs1, and rs2 fields
+class F3_rdrs1rs2 : F3_rs1 {
+  bits<5> rs2;
+  set Inst{4-0} = rs2;
+}
+
 
 // Specific F3 classes...
 //
@@ -80,7 +99,24 @@
   //set Inst{12-5} = dontcare;
 }
 
+// The store instructions seem to like to see rd first, then rs1 and rs2
+class F3_1rd<bits<2> opVal, bits<6> op3val, string name> : F3_rdrs1rs2 {
+  set op  = opVal;
+  set op3 = op3val;
+  set Name = name;
+  set Inst{13} = 0;   // i field = 0
+  //set Inst{12-5} = dontcare;
+}
+
 class F3_2<bits<2> opVal, bits<6> op3val, string name> : F3_rs1simm13rd {
+  set op  = opVal;
+  set op3 = op3val;
+  set Name = name;
+  set Inst{13} = 1;   // i field = 1
+}
+
+// The store instructions seem to like to see rd first, then rs1 and imm
+class F3_2rd<bits<2> opVal, bits<6> op3val, string name> : F3_rdrs1simm13 {
   set op  = opVal;
   set op3 = op3val;
   set Name = name;


Index: llvm/lib/Target/Sparc/SparcV9.td
diff -u llvm/lib/Target/Sparc/SparcV9.td:1.11 llvm/lib/Target/Sparc/SparcV9.td:1.12
--- llvm/lib/Target/Sparc/SparcV9.td:1.11	Mon Jun  2 20:16:27 2003
+++ llvm/lib/Target/Sparc/SparcV9.td	Mon Jun  2 22:20:14 2003
@@ -603,15 +603,15 @@
 // Not currently used in the Sparc backend
 
 // Section A.52: Store Floating-point -p225
-def STFr  : F3_1<3, 0b100100, "st">;                      // st r, [r+r]
-def STFi  : F3_2<3, 0b100100, "st">;                      // st r, [r+i]
-def STDFr : F3_1<3, 0b100111, "std">;                     // std r, [r+r]
-def STDFi : F3_2<3, 0b100111, "std">;                     // std r, [r+i]
+def STFr  : F3_1rd<3, 0b100100, "st">;                      // st r, [r+r]
+def STFi  : F3_2rd<3, 0b100100, "st">;                      // st r, [r+i]
+def STDFr : F3_1rd<3, 0b100111, "std">;                     // std r, [r+r]
+def STDFi : F3_2rd<3, 0b100111, "std">;                     // std r, [r+i]
 
 // Not currently used in the Sparc backend
 #if 0
-def STQFr : F3_1<3, 0b100110, "stq">;                     // stq r, [r+r]
-def STQFi : F3_2<3, 0b100110, "stq">;                     // stq r, [r+i]
+def STQFr : F3_1rd<3, 0b100110, "stq">;                     // stq r, [r+r]
+def STQFi : F3_2rd<3, 0b100110, "stq">;                     // stq r, [r+i]
 #endif
 
 set isDeprecated = 1 in {




From brukman at cs.uiuc.edu  Mon Jun  2 22:22:00 2003
From: brukman at cs.uiuc.edu (Misha Brukman)
Date: Mon Jun  2 22:22:00 2003
Subject: [llvm-commits] CVS: llvm/lib/Target/Sparc/SparcInstrInfo.cpp
Message-ID: <200306030321.WAA23635@zion.cs.uiuc.edu>


Changes in directory llvm/lib/Target/Sparc:

SparcInstrInfo.cpp updated: 1.45 -> 1.46

---
Log message:

Convert load/store opcodes from register to immediate forms, if necessary.


---
Diffs of the changes:

Index: llvm/lib/Target/Sparc/SparcInstrInfo.cpp
diff -u llvm/lib/Target/Sparc/SparcInstrInfo.cpp:1.45 llvm/lib/Target/Sparc/SparcInstrInfo.cpp:1.46
--- llvm/lib/Target/Sparc/SparcInstrInfo.cpp:1.45	Sat May 31 02:30:29 2003
+++ llvm/lib/Target/Sparc/SparcInstrInfo.cpp	Mon Jun  2 22:20:57 2003
@@ -478,6 +478,7 @@
     // Generate the load instruction
     int64_t zeroOffset = 0;           // to avoid ambiguity with (Value*) 0
     unsigned Opcode = ChooseLoadInstruction(val->getType());
+    Opcode = convertOpcodeFromRegToImm(Opcode);
     mvec.push_back(BuildMI(Opcode, 3).addReg(addrReg).
                    addSImm(zeroOffset).addRegDef(dest));
       
@@ -532,7 +533,9 @@
   }
 
   unsigned FPReg = target.getRegInfo().getFramePointer();
-  mvec.push_back(BuildMI(ChooseStoreInstruction(storeType), 3)
+  unsigned StoreOpcode = ChooseStoreInstruction(storeType);
+  StoreOpcode = convertOpcodeFromRegToImm(StoreOpcode);
+  mvec.push_back(BuildMI(StoreOpcode, 3)
                  .addReg(storeVal).addMReg(FPReg).addSImm(offset));
 
   // Load instruction loads [%fp+offset] to `dest'.
@@ -541,7 +544,9 @@
   // On SparcV9: float for int or smaller, double for long.
   // 
   const Type* loadType = (srcSize <= 4)? Type::FloatTy : Type::DoubleTy;
-  mvec.push_back(BuildMI(ChooseLoadInstruction(loadType), 3)
+  unsigned LoadOpcode = ChooseLoadInstruction(loadType);
+  LoadOpcode = convertOpcodeFromRegToImm(LoadOpcode);
+  mvec.push_back(BuildMI(LoadOpcode, 3)
                  .addMReg(FPReg).addSImm(offset).addRegDef(dest));
 }
 
@@ -577,7 +582,9 @@
   // Store instruction stores `val' to [%fp+offset].
   // The store opCode is based only the source value being copied.
   // 
-  mvec.push_back(BuildMI(ChooseStoreInstruction(opTy), 3)
+  unsigned StoreOpcode = ChooseStoreInstruction(opTy);
+  StoreOpcode = convertOpcodeFromRegToImm(StoreOpcode);  
+  mvec.push_back(BuildMI(StoreOpcode, 3)
                  .addReg(val).addMReg(FPReg).addSImm(offset));
 
   // Load instruction loads [%fp+offset] to `dest'.
@@ -588,7 +595,9 @@
   // ensure correct sign-extension for UByte, UShort or UInt:
   // 
   const Type* loadTy = (opTy == Type::FloatTy)? Type::IntTy : Type::LongTy;
-  mvec.push_back(BuildMI(ChooseLoadInstruction(loadTy), 3).addMReg(FPReg)
+  unsigned LoadOpcode = ChooseLoadInstruction(loadTy);
+  LoadOpcode = convertOpcodeFromRegToImm(LoadOpcode);
+  mvec.push_back(BuildMI(LoadOpcode, 3).addMReg(FPReg)
                  .addSImm(offset).addRegDef(dest));
 }
 




From brukman at cs.uiuc.edu  Mon Jun  2 22:23:00 2003
From: brukman at cs.uiuc.edu (Misha Brukman)
Date: Mon Jun  2 22:23:00 2003
Subject: [llvm-commits] CVS: llvm/lib/Target/Sparc/SparcInstrSelection.cpp
Message-ID: <200306030322.WAA23649@zion.cs.uiuc.edu>


Changes in directory llvm/lib/Target/Sparc:

SparcInstrSelection.cpp updated: 1.100 -> 1.101

---
Log message:

* Convert load/store opcodes from register to immediate forms.
* Stop code from wrapping to the next line.


---
Diffs of the changes:

Index: llvm/lib/Target/Sparc/SparcInstrSelection.cpp
diff -u llvm/lib/Target/Sparc/SparcInstrSelection.cpp:1.100 llvm/lib/Target/Sparc/SparcInstrSelection.cpp:1.101
--- llvm/lib/Target/Sparc/SparcInstrSelection.cpp:1.100	Mon Jun  2 15:55:14 2003
+++ llvm/lib/Target/Sparc/SparcInstrSelection.cpp	Mon Jun  2 22:21:58 2003
@@ -2228,15 +2228,16 @@
               // float-to-int instructions to pass the value as an int.
               // To check if it is in teh first $K$, get the register
               // number for the arg #i.
-              int copyRegNum = regInfo.regNumForIntArg(false, false,
-                                                       argNo, regClassIDOfArgReg);
+              int copyRegNum = regInfo.regNumForIntArg(false, false, argNo,
+                                                       regClassIDOfArgReg);
               if (copyRegNum != regInfo.getInvalidRegNum()) {
                 // Create a virtual register to represent copyReg. Mark
                 // this vreg as being an implicit operand of the call MI
                 const Type* loadTy = (argType == Type::FloatTy
                                       ? Type::IntTy : Type::LongTy);
-                TmpInstruction* argVReg= new TmpInstruction(mcfi,loadTy,
-                                                            argVal, NULL, "argRegCopy");
+                TmpInstruction* argVReg = new TmpInstruction(mcfi, loadTy,
+                                                             argVal, NULL,
+                                                             "argRegCopy");
                 callMI->addImplicitRef(argVReg);
                         
                 // Get a temp stack location to use to copy
@@ -2251,22 +2252,23 @@
                 int tmpOffset = MF.getInfo()->allocateLocalVar(argVReg);
                     
                 // Generate the store from FP reg to stack
-                M = BuildMI(ChooseStoreInstruction(argType), 3)
+                unsigned StoreOpcode = ChooseStoreInstruction(argType);
+                M = BuildMI(convertOpcodeFromRegToImm(StoreOpcode), 3)
                   .addReg(argVal).addMReg(regInfo.getFramePointer())
                   .addSImm(tmpOffset);
                 mvec.push_back(M);
                         
                 // Generate the load from stack to int arg reg
-                M = BuildMI(ChooseLoadInstruction(loadTy), 3)
+                unsigned LoadOpcode = ChooseLoadInstruction(loadTy);
+                M = BuildMI(convertOpcodeFromRegToImm(LoadOpcode), 3)
                   .addMReg(regInfo.getFramePointer()).addSImm(tmpOffset)
                   .addReg(argVReg, MOTy::Def);
 
                 // Mark operand with register it should be assigned
                 // both for copy and for the callMI
                 M->SetRegForOperand(M->getNumOperands()-1, copyRegNum);
-                callMI->SetRegForImplicitRef(
-                                             callMI->getNumImplicitRefs()-1, copyRegNum);
-
+                callMI->SetRegForImplicitRef(callMI->getNumImplicitRefs()-1,
+                                             copyRegNum);
                 mvec.push_back(M);
 
                 // Add info about the argument to the CallArgsDescriptor




From brukman at cs.uiuc.edu  Mon Jun  2 22:24:01 2003
From: brukman at cs.uiuc.edu (Misha Brukman)
Date: Mon Jun  2 22:24:01 2003
Subject: [llvm-commits] CVS: llvm/lib/Target/Sparc/SparcInstrSelectionSupport.h
Message-ID: <200306030323.WAA23667@zion.cs.uiuc.edu>


Changes in directory llvm/lib/Target/Sparc:

SparcInstrSelectionSupport.h updated: 1.8 -> 1.9

---
Log message:

Added opcode conversion for conditional move of integers.


---
Diffs of the changes:

Index: llvm/lib/Target/Sparc/SparcInstrSelectionSupport.h
diff -u llvm/lib/Target/Sparc/SparcInstrSelectionSupport.h:1.8 llvm/lib/Target/Sparc/SparcInstrSelectionSupport.h:1.9
--- llvm/lib/Target/Sparc/SparcInstrSelectionSupport.h:1.8	Fri May 30 15:11:56 2003
+++ llvm/lib/Target/Sparc/SparcInstrSelectionSupport.h	Mon Jun  2 22:23:35 2003
@@ -117,6 +117,51 @@
   case V9::SRLXr6:  return V9::SRLXi6;
   case V9::SRAXr6:  return V9::SRAXi6;
 
+    /* Conditional move on int comparison with zero */
+  case V9::MOVRZr:   return V9::MOVRZi;
+  case V9::MOVRLEZr: return V9::MOVRLEZi;
+  case V9::MOVRLZr:  return V9::MOVRLZi;
+  case V9::MOVRNZr:  return V9::MOVRNZi;
+  case V9::MOVRGZr:  return V9::MOVRGZi;
+  case V9::MOVRGEZr: return V9::MOVRGEZi;
+
+
+    /* Conditional move on int condition code */
+  case V9::MOVAr:   return V9::MOVAi;
+  case V9::MOVNr:   return V9::MOVNi;
+  case V9::MOVNEr:  return V9::MOVNEi;
+  case V9::MOVEr:   return V9::MOVEi;
+  case V9::MOVGr:   return V9::MOVGi;
+  case V9::MOVLEr:  return V9::MOVLEi;
+  case V9::MOVGEr:  return V9::MOVGEi;
+  case V9::MOVLr:   return V9::MOVLi;
+  case V9::MOVGUr:  return V9::MOVGUi;
+  case V9::MOVLEUr: return V9::MOVLEUi;
+  case V9::MOVCCr:  return V9::MOVCCi;
+  case V9::MOVCSr:  return V9::MOVCSi;
+  case V9::MOVPOSr: return V9::MOVPOSi;
+  case V9::MOVNEGr: return V9::MOVNEGi;
+  case V9::MOVVCr:  return V9::MOVVCi;
+  case V9::MOVVSr:  return V9::MOVVSi;
+
+    /* Conditional move of int reg on fp condition code */
+  case V9::MOVFAr:   return V9::MOVFAi;
+  case V9::MOVFNr:   return V9::MOVFNi;
+  case V9::MOVFUr:   return V9::MOVFUi;
+  case V9::MOVFGr:   return V9::MOVFGi;
+  case V9::MOVFUGr:  return V9::MOVFUGi;
+  case V9::MOVFLr:   return V9::MOVFLi;
+  case V9::MOVFULr:  return V9::MOVFULi;
+  case V9::MOVFLGr:  return V9::MOVFLGi;
+  case V9::MOVFNEr:  return V9::MOVFNEi;
+  case V9::MOVFEr:   return V9::MOVFEi;
+  case V9::MOVFUEr:  return V9::MOVFUEi;
+  case V9::MOVFGEr:  return V9::MOVFGEi;
+  case V9::MOVFUGEr: return V9::MOVFUGEi;
+  case V9::MOVFLEr:  return V9::MOVFLEi;
+  case V9::MOVFULEr: return V9::MOVFULEi;
+  case V9::MOVFOr:   return V9::MOVFOi;
+
     /* load */
   case V9::LDSBr:   return V9::LDSBi;
   case V9::LDSHr:   return V9::LDSHi;
@@ -152,6 +197,11 @@
 
   default:
     // It's already in correct format
+    // Or, it's just not handled yet, but an assert() would break LLC
+#if 0
+    std::cerr << "Unhandled opcode in convertOpcodeFromRegToImm(): " << Opcode 
+              << "\n";
+#endif
     return Opcode;
   }
 }




From brukman at cs.uiuc.edu  Mon Jun  2 22:25:01 2003
From: brukman at cs.uiuc.edu (Misha Brukman)
Date: Mon Jun  2 22:25:01 2003
Subject: [llvm-commits] CVS: llvm/lib/Target/Sparc/SparcV9CodeEmitter.cpp
Message-ID: <200306030324.WAA23694@zion.cs.uiuc.edu>


Changes in directory llvm/lib/Target/Sparc:

SparcV9CodeEmitter.cpp updated: 1.9 -> 1.10

---
Log message:

Constants are laid out in memory in PC-relative form.


---
Diffs of the changes:

Index: llvm/lib/Target/Sparc/SparcV9CodeEmitter.cpp
diff -u llvm/lib/Target/Sparc/SparcV9CodeEmitter.cpp:1.9 llvm/lib/Target/Sparc/SparcV9CodeEmitter.cpp:1.10
--- llvm/lib/Target/Sparc/SparcV9CodeEmitter.cpp:1.9	Mon Jun  2 00:24:46 2003
+++ llvm/lib/Target/Sparc/SparcV9CodeEmitter.cpp	Mon Jun  2 22:24:12 2003
@@ -195,7 +195,7 @@
       BBRefs.push_back(std::make_pair(BB, std::make_pair(CurrPC, &MI)));
     } else if (Constant *C = dyn_cast<Constant>(V)) {
       if (ConstantMap.find(C) != ConstantMap.end())
-        rv = (int64_t)(intptr_t)ConstantMap[C];
+        rv = (int64_t)(intptr_t)ConstantMap[C] - MCE->getCurrentPCValue();
       else {
         std::cerr << "ERROR: constant not in map:" << MO << "\n";
         abort();




From gaeke at cs.uiuc.edu  Mon Jun  2 22:42:01 2003
From: gaeke at cs.uiuc.edu (Brian Gaeke)
Date: Mon Jun  2 22:42:01 2003
Subject: [llvm-commits] CVS: llvm/lib/Target/Sparc/FInfo.cpp
Message-ID: <200306030341.WAA16101@neo.cs.uiuc.edu>


Changes in directory llvm/lib/Target/Sparc:

FInfo.cpp updated: 1.2 -> 1.3

---
Log message:

Add file comment.



---
Diffs of the changes:

Index: llvm/lib/Target/Sparc/FInfo.cpp
diff -u llvm/lib/Target/Sparc/FInfo.cpp:1.2 llvm/lib/Target/Sparc/FInfo.cpp:1.3
--- llvm/lib/Target/Sparc/FInfo.cpp:1.2	Mon Jun  2 17:57:41 2003
+++ llvm/lib/Target/Sparc/FInfo.cpp	Mon Jun  2 22:41:07 2003
@@ -1,3 +1,16 @@
+//===-- FInfo.cpp --------------------------------------------*- C++ -*-===//// 
+// 
+// This file contains a pass, FunctionInfo, used by LLC's SPARC back-end
+// which writes out two tables used by the Reoptimizer.  These tables,
+// named FunctionBB and FunctionLI, map Function numbers to the BBMIMap and
+// LMIMap tables output by the getMappingInfoForFunction (MappingInfo.cpp)
+// pass, respectively.
+// 
+// An LLVM Function's Function number is the index within a Module* where a
+// particular Function* can be found.
+//
+//===----------------------------------------------------------------------===//
+
 #include "llvm/Reoptimizer/Mapping/FInfo.h"
 #include "llvm/Pass.h"
 #include "llvm/Module.h"




From lattner at cs.uiuc.edu  Mon Jun  2 23:41:02 2003
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Mon Jun  2 23:41:02 2003
Subject: [llvm-commits] CVS: llvm/www/docs/CommandLine.html
Message-ID: <200306030440.XAA01461@tank.cs.uiuc.edu>


Changes in directory llvm/www/docs:

CommandLine.html updated: 1.8 -> 1.9

---
Log message:

Fix minor bug


---
Diffs of the changes:

Index: llvm/www/docs/CommandLine.html
diff -u llvm/www/docs/CommandLine.html:1.8 llvm/www/docs/CommandLine.html:1.9
--- llvm/www/docs/CommandLine.html:1.8	Thu May 22 15:36:06 2003
+++ llvm/www/docs/CommandLine.html	Mon Jun  2 23:40:06 2003
@@ -541,7 +541,7 @@
 };
 
 // Enable Debug Options to be specified on the command line
-<a href="#cl::opt">cl::opt</a><DebugLev> DebugLevel("<i>debug_level</i>", <a href="#cl::desc">cl::desc</a>("<i>Set the debugging level:</i>"),
+<a href="#cl::opt">cl::opt</a>&lt;DebugLev&gt; DebugLevel("<i>debug_level</i>", <a href="#cl::desc">cl::desc</a>("<i>Set the debugging level:</i>"),
   <a href="#cl::values">cl::values</a>(
     clEnumValN(nodebuginfo, "none", "<i>disable debug information</i>"),
      clEnumVal(quick,               "<i>enable quick debug information</i>"),
@@ -1495,7 +1495,7 @@
 <address><a href="mailto:sabre at nondot.org">Chris Lattner</a></address>
 <!-- Created: Tue Jan 23 15:19:28 CST 2001 -->
 <!-- hhmts start -->
-Last modified: Thu May 22 15:35:19 CDT 2003
+Last modified: Mon Jun  2 23:39:44 CDT 2003
 <!-- hhmts end -->
 </font>
 </body></html>




From lattner at cs.uiuc.edu  Mon Jun  2 23:57:01 2003
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Mon Jun  2 23:57:01 2003
Subject: [llvm-commits] CVS: llvm/utils/TableGen/TableGen.cpp
Message-ID: <200306030456.XAA26906@apoc.cs.uiuc.edu>


Changes in directory llvm/utils/TableGen:

TableGen.cpp updated: 1.4 -> 1.5

---
Log message:

Make tablegen use more structured command line options



---
Diffs of the changes:

Index: llvm/utils/TableGen/TableGen.cpp
diff -u llvm/utils/TableGen/TableGen.cpp:1.4 llvm/utils/TableGen/TableGen.cpp:1.5
--- llvm/utils/TableGen/TableGen.cpp:1.4	Fri May 23 19:17:12 2003
+++ llvm/utils/TableGen/TableGen.cpp	Mon Jun  2 23:56:29 2003
@@ -3,9 +3,30 @@
 #include "CodeEmitterGen.h"
 #include <algorithm>
 
-static cl::opt<std::string> Class("class", cl::desc("Print Enum list for this class"));
-static cl::opt<bool>        Parse("parse");
-static cl::opt<bool>        GenEmitter("gen-emitter");
+enum ActionType {
+  PrintRecords,
+  GenEmitter,
+  PrintEnums,
+  Parse,
+};
+
+namespace {
+  cl::opt<ActionType>
+  Action(cl::desc("Action to perform:"),
+         cl::values(clEnumValN(PrintRecords, "print-records",
+                               "Print all records to stdout"),
+                    clEnumValN(GenEmitter, "gen-emitter",
+                               "Generate machine code emitter"),
+                    clEnumValN(PrintEnums, "print-enums",
+                               "Print enum values for a class"),
+                    clEnumValN(Parse, "parse",
+                               "Interpret machine code (testing only)"),
+                    0));
+
+  cl::opt<std::string>
+  Class("class", cl::desc("Print Enum list for this class"));
+}
+
 
 void ParseFile();
 
@@ -353,20 +374,15 @@
   cl::ParseCommandLineOptions(argc, argv);
   ParseFile();
 
-  if (Parse) {
-    ParseMachineCode();
-    return 0;
-  }
-
-  if (GenEmitter) {
-    CodeEmitterGen CEG(Records);
-    CEG.createEmitter(std::cout);
-    return 0;
-  }
-
-  if (Class == "") {
+  switch (Action) {
+  case Parse: ParseMachineCode(); break;
+  case GenEmitter:
+    CodeEmitterGen(Records).createEmitter(std::cout);
+    break;
+  case PrintRecords:
     std::cout << Records;           // No argument, dump all contents
-  } else {
+    break;
+  case PrintEnums:
     Record *R = Records.getClass(Class);
     if (R == 0) {
       std::cerr << "Cannot find class '" << Class << "'!\n";
@@ -381,6 +397,7 @@
       }
     }
     std::cout << "\n";
+    break;
   }
   return 0;
 }




From lattner at cs.uiuc.edu  Tue Jun  3 00:05:01 2003
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Tue Jun  3 00:05:01 2003
Subject: [llvm-commits] CVS: llvm/utils/TableGen/TableGen.cpp
Message-ID: <200306030504.AAA27051@apoc.cs.uiuc.edu>


Changes in directory llvm/utils/TableGen:

TableGen.cpp updated: 1.5 -> 1.6

---
Log message:

Add -o support for TableGen

I figure that misha has done a lot of things on my todo list, the least I
can do is reciprocate a bit.  :)


---
Diffs of the changes:

Index: llvm/utils/TableGen/TableGen.cpp
diff -u llvm/utils/TableGen/TableGen.cpp:1.5 llvm/utils/TableGen/TableGen.cpp:1.6
--- llvm/utils/TableGen/TableGen.cpp:1.5	Mon Jun  2 23:56:29 2003
+++ llvm/utils/TableGen/TableGen.cpp	Tue Jun  3 00:04:42 2003
@@ -1,7 +1,9 @@
 #include "Record.h"
 #include "Support/CommandLine.h"
+#include "Support/Signals.h"
 #include "CodeEmitterGen.h"
 #include <algorithm>
+#include <fstream>
 
 enum ActionType {
   PrintRecords,
@@ -25,6 +27,10 @@
 
   cl::opt<std::string>
   Class("class", cl::desc("Print Enum list for this class"));
+
+ cl::opt<std::string>
+ OutputFilename("o", cl::desc("Output filename"), cl::value_desc("filename"),
+                cl::init("-"));
 }
 
 
@@ -374,13 +380,26 @@
   cl::ParseCommandLineOptions(argc, argv);
   ParseFile();
 
+  std::ostream *Out = &std::cout;
+  if (OutputFilename != "-") {
+    Out = new std::ofstream(OutputFilename.c_str());
+
+    if (!Out->good()) {
+      std::cerr << argv[0] << ": error opening " << OutputFilename << "!\n";
+      return 1;
+    }
+
+    // Make sure the file gets removed if *gasp* tablegen crashes...
+    RemoveFileOnSignal(OutputFilename);
+  }
+
   switch (Action) {
   case Parse: ParseMachineCode(); break;
   case GenEmitter:
-    CodeEmitterGen(Records).createEmitter(std::cout);
+    CodeEmitterGen(Records).createEmitter(*Out);
     break;
   case PrintRecords:
-    std::cout << Records;           // No argument, dump all contents
+    *Out << Records;           // No argument, dump all contents
     break;
   case PrintEnums:
     Record *R = Records.getClass(Class);
@@ -393,11 +412,13 @@
     for (std::map<std::string, Record*>::const_iterator I = Defs.begin(),
 	   E = Defs.end(); I != E; ++I) {
       if (I->second->isSubClassOf(R)) {
-	std::cout << I->first << ", ";
+	*Out << I->first << ", ";
       }
     }
-    std::cout << "\n";
+    *Out << "\n";
     break;
   }
+
+  if (Out != &std::cout) delete Out;
   return 0;
 }




From lattner at cs.uiuc.edu  Tue Jun  3 00:07:01 2003
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Tue Jun  3 00:07:01 2003
Subject: [llvm-commits] CVS: llvm/lib/Target/Sparc/Makefile
Message-ID: <200306030506.AAA27115@apoc.cs.uiuc.edu>


Changes in directory llvm/lib/Target/Sparc:

Makefile updated: 1.21 -> 1.22

---
Log message:

Use the new -o tablegen option


---
Diffs of the changes:

Index: llvm/lib/Target/Sparc/Makefile
diff -u llvm/lib/Target/Sparc/Makefile:1.21 llvm/lib/Target/Sparc/Makefile:1.22
--- llvm/lib/Target/Sparc/Makefile:1.21	Sat May 31 23:52:51 2003
+++ llvm/lib/Target/Sparc/Makefile	Tue Jun  3 00:06:33 2003
@@ -34,12 +34,9 @@
 
 SparcV9CodeEmitter.cpp: SparcV9CodeEmitter.inc
 
-TEMP_EMITTER_INC = _temp_emitter.inc
-
 SparcV9CodeEmitter.inc: SparcV9.td SparcV9_F2.td SparcV9_F3.td SparcV9_F4.td SparcV9_Reg.td $(TBLGEN)
 	@echo "TableGen-erating $@"
-	cpp -P SparcV9.td | $(TBLGEN) -gen-emitter > $(TEMP_EMITTER_INC) 
-	mv -f $(TEMP_EMITTER_INC) SparcV9CodeEmitter.inc
+	cpp -P SparcV9.td | $(TBLGEN) -gen-emitter -o $@
 
 clean::
 	rm -f SparcV9CodeEmitter.inc




From lattner at cs.uiuc.edu  Tue Jun  3 00:08:01 2003
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Tue Jun  3 00:08:01 2003
Subject: [llvm-commits] CVS: llvm/utils/TableGen/TableGen.cpp
Message-ID: <200306030507.AAA27152@apoc.cs.uiuc.edu>


Changes in directory llvm/utils/TableGen:

TableGen.cpp updated: 1.6 -> 1.7

---
Log message:

Spiff up options a bit


---
Diffs of the changes:

Index: llvm/utils/TableGen/TableGen.cpp
diff -u llvm/utils/TableGen/TableGen.cpp:1.6 llvm/utils/TableGen/TableGen.cpp:1.7
--- llvm/utils/TableGen/TableGen.cpp:1.6	Tue Jun  3 00:04:42 2003
+++ llvm/utils/TableGen/TableGen.cpp	Tue Jun  3 00:07:28 2003
@@ -16,7 +16,7 @@
   cl::opt<ActionType>
   Action(cl::desc("Action to perform:"),
          cl::values(clEnumValN(PrintRecords, "print-records",
-                               "Print all records to stdout"),
+                               "Print all records to stdout (default)"),
                     clEnumValN(GenEmitter, "gen-emitter",
                                "Generate machine code emitter"),
                     clEnumValN(PrintEnums, "print-enums",
@@ -26,7 +26,8 @@
                     0));
 
   cl::opt<std::string>
-  Class("class", cl::desc("Print Enum list for this class"));
+  Class("class", cl::desc("Print Enum list for this class"),
+        cl::value_desc("class name"));
 
  cl::opt<std::string>
  OutputFilename("o", cl::desc("Output filename"), cl::value_desc("filename"),




From gaeke at cs.uiuc.edu  Tue Jun  3 02:57:01 2003
From: gaeke at cs.uiuc.edu (Brian Gaeke)
Date: Tue Jun  3 02:57:01 2003
Subject: [llvm-commits] CVS: llvm/lib/CodeGen/Mapping/MappingInfo.cpp
Message-ID: <200306030756.CAA16889@neo.cs.uiuc.edu>


Changes in directory llvm/lib/CodeGen/Mapping:

MappingInfo.cpp updated: 1.4 -> 1.5

---
Log message:

I documented this file, in an attempt to understand it, with a view toward
rewriting it.  I also vacuumed out all the commented-out code and
inaccurate comments, etc.

(We need to put the mapping information in a data structure so that we can
pass it out to the JIT, instead of automagically converting it to .byte
directives.)


---
Diffs of the changes:

Index: llvm/lib/CodeGen/Mapping/MappingInfo.cpp
diff -u llvm/lib/CodeGen/Mapping/MappingInfo.cpp:1.4 llvm/lib/CodeGen/Mapping/MappingInfo.cpp:1.5
--- llvm/lib/CodeGen/Mapping/MappingInfo.cpp:1.4	Mon Oct 28 14:00:25 2002
+++ llvm/lib/CodeGen/Mapping/MappingInfo.cpp	Tue Jun  3 02:56:05 2003
@@ -1,8 +1,16 @@
 //===- MappingInfo.cpp - create LLVM info and output to .s file ---------===//
 //
-// Create Map from LLVM BB and Instructions and Machine Instructions
-// and output the information as .byte directives to the .s file
-// Currently Sparc specific but will be extended for others later
+// This file contains a FunctionPass called getMappingInfoForFunction,
+// which creates two maps: one between LLVM Instructions and MachineInstrs,
+// and another between MachineBasicBlocks and MachineInstrs (the "BB TO
+// MI MAP").
+//
+// As a side effect, it outputs this information as .byte directives to
+// the assembly file. The output is designed to survive the SPARC assembler,
+// in order that the Reoptimizer may read it in from memory later when the
+// binary is loaded. Therefore, it may contain some hidden SPARC-architecture
+// dependencies. Currently this question is purely theoretical as the
+// Reoptimizer works only on the SPARC.
 //
 //===--------------------------------------------------------------------===//
 
@@ -15,10 +23,6 @@
 #include <map>
 using std::vector;
 
-
-// MappingInfo - This method collects mapping info 
-// for the mapping from LLVM to machine code.
-//
 namespace {
   class getMappingInfoForFunction : public FunctionPass { 
     std::ostream &Out;
@@ -46,24 +50,22 @@
   };
 }
 
-
-//pass definition
+/// MappingInfoForFunction -- Static factory method: returns a new
+/// getMappingInfoForFunction Pass object.
 Pass *MappingInfoForFunction(std::ostream &out){
   return (new getMappingInfoForFunction(out));
 }
 
-//function definitions :
-//create and output maps to the .s file
+/// runOnFunction -- Builds up the maps for the given function and then
+/// writes them out as assembly code to the current output stream Out.
+/// This is an entry point to the pass, called by the PassManager.
 bool getMappingInfoForFunction::runOnFunction(Function &FI) {
-  
-  
-  //first create reference maps
-  //createFunctionKey(M);
+  // First we build up the maps.
   create_BB_to_MInumber_Key(FI);
   create_MI_to_number_Key(FI);
-  unsigned FunctionNo = Fkey[&(FI)];
+  unsigned FunctionNo = Fkey[&FI];
 
-  //now print out the maps
+  // Now, print out the maps.
   writePrologue("BB TO MI MAP", "BBMIMap", FunctionNo);
   writeBBToMImap(FI);
   writeEpilogue("BB TO MI MAP", "BBMIMap", FunctionNo);  
@@ -95,7 +97,8 @@
       << FunctionNo << "\n\n\n\n";
 }
 
-//write out information as .byte directives
+/// writeNumber -- Write out the number X as a sequence of .byte
+/// directives to the current output stream Out.
 unsigned getMappingInfoForFunction::writeNumber(unsigned X) {
   unsigned i=0;
   do {
@@ -108,20 +111,31 @@
   return i;
 }
 
-//Assign a number to each Function 
+/// doInitialization -- Assign a number to each Function, as follows:
+/// Functions are numbered starting at 0 at the begin() of each Module.
+/// Functions which are External (and thus have 0 basic blocks) are not
+/// inserted into the maps, and are not assigned a number.  The side-effect
+/// of this method is to fill in Fkey to contain the mapping from Functions
+/// to numbers. (This method is called automatically by the PassManager.)
 bool getMappingInfoForFunction::doInitialization(Module &M) {
   unsigned i = 0;
-  for (Module::iterator FI = M.begin(), FE = M.end();
-       FI != FE; ++FI){
-    //dont count F with 0 BBs
-    if(FI->isExternal()) continue;
+  for (Module::iterator FI = M.begin(), FE = M.end(); FI != FE; ++FI) {
+    if (FI->isExternal()) continue;
     Fkey[FI] = i;
     ++i;
   }
   return false;
 }
-     
-//Assign a Number to each BB
+
+/// create_BB_to_MInumber_Key -- Assign a number to each MachineBasicBlock
+/// in the given Function, as follows: Numbering starts at zero in each
+/// Function. MachineBasicBlocks are numbered from begin() to end()
+/// in the Function's corresponding MachineFunction. Each successive
+/// MachineBasicBlock increments the numbering by the number of instructions
+/// it contains. The side-effect of this method is to fill in the instance
+/// variable BBkey with the mapping of MachineBasicBlocks to numbers. BBkey
+/// is keyed on MachineInstrs, so each MachineBasicBlock is represented
+/// therein by its first MachineInstr.
 void getMappingInfoForFunction::create_BB_to_MInumber_Key(Function &FI) {
   unsigned i = 0;
   MachineFunction &MF = MachineFunction::get(&FI);
@@ -133,7 +147,13 @@
   }
 }
 
-//Assign a number to each MI wrt beginning of the BB
+/// create_MI_to_number_Key -- Assign a number to each MachineInstr
+/// in the given Function with respect to its enclosing MachineBasicBlock, as
+/// follows: Numberings start at 0 in each MachineBasicBlock. MachineInstrs
+/// are numbered from begin() to end() in their MachineBasicBlock. Each
+/// MachineInstr is numbered, then the numbering is incremented by 1. The
+/// side-effect of this method is to fill in the instance variable MIkey
+/// with the mapping from MachineInstrs to numbers.
 void getMappingInfoForFunction::create_MI_to_number_Key(Function &FI) {
   MachineFunction &MF = MachineFunction::get(&FI);
   for (MachineFunction::iterator BI=MF.begin(), BE=MF.end(); BI != BE; ++BI) {
@@ -146,8 +166,13 @@
   }
 }
 
-//BBtoMImap: contains F#, BB#, 
-//              MI#[wrt beginning of F], #MI in BB
+/// writeBBToMImap -- Output the BB TO MI MAP for the given function as
+/// assembly code to the current output stream. The BB TO MI MAP consists
+/// of a three-element tuple for each MachineBasicBlock in a function:
+/// first, the index of the MachineBasicBlock in the function; second,
+/// the number of the MachineBasicBlock in the function as computed by
+/// create_BB_to_MInumber_Key; and third, the number of MachineInstrs in
+/// the MachineBasicBlock.
 void getMappingInfoForFunction::writeBBToMImap(Function &FI){
   unsigned bb = 0;
   MachineFunction &MF = MachineFunction::get(&FI);  
@@ -155,47 +180,39 @@
        BI != BE; ++BI, ++bb) {
     MachineBasicBlock &miBB = *BI;
     writeNumber(bb);
-    //Out << " BB: "<<(void *)BI<<"\n";
-    //for(int i=0; i<miBB.size(); ++i)
-    //Out<<*miBB[i]<<"\n";
-    writeNumber( BBkey[ miBB[0] ]);
+    writeNumber(BBkey[miBB[0]]);
     writeNumber(miBB.size());
   }
 }
 
-//LLVMtoMImap: contains F#, BB#, LLVM#, 
-//                           MIs[wrt to beginning of BB] 
+/// writeLLVMToMImap -- Output the LLVM I TO MI MAP for the given function
+/// as assembly code to the current output stream. The LLVM I TO MI MAP
+/// consists of a set of information for each BasicBlock in a Function,
+/// ordered from begin() to end(). The information for a BasicBlock consists
+/// of 1) its (0-based) index in the Function, 2) the number of LLVM
+/// Instructions it contains, and 3) information for each Instruction, in
+/// sequence from the begin() to the end() of the BasicBlock. The information
+/// for an Instruction consists of 1) its (0-based) index in the BasicBlock,
+/// 2) the number of MachineInstrs that correspond to that Instruction
+/// (as reported by MachineCodeForInstruction), and 3) the MachineInstr
+/// number calculated by create_MI_to_number_Key, for each of the
+/// MachineInstrs that correspond to that Instruction.
 void getMappingInfoForFunction::writeLLVMToMImap(Function &FI) {
 
-  unsigned bb =0;
-  for (Function::iterator BI = FI.begin(),  BE = FI.end(); 
+  unsigned bb = 0;
+  for (Function::iterator BI = FI.begin(), BE = FI.end(); 
        BI != BE; ++BI, ++bb) {
     unsigned li = 0;
     writeNumber(bb);
-    //std::cerr<<"BasicBlockNumber= "<<bb<<"\n";
-
-    //Out << "BB: "<<(void *)BI<<"\n";
     writeNumber(BI->size());
-    //std::cerr<<"BasicBlockSize  = "<<BI->size()<<"\n";
-
-    for (BasicBlock::iterator II = BI->begin(), 
-	   IE = BI->end(); II != IE; ++II, ++li) {
-    //Out << "I: "<<*II<<"\n";
-      MachineCodeForInstruction& miI = 
-	MachineCodeForInstruction::get(II);
-      
-      //do for each corr. MI
+    for (BasicBlock::iterator II = BI->begin(), IE = BI->end(); II != IE;
+         ++II, ++li) {
+      MachineCodeForInstruction& miI = MachineCodeForInstruction::get(II);
       writeNumber(li);
-      //std::cerr<<"InstructionNumber= "<<li<<"\n";
-
       writeNumber(miI.size());
-      //std::cerr<<"InstructionSize  = "<<miI.size()<<"\n";
-   
       for (MachineCodeForInstruction::iterator miII = miI.begin(), 
-	     miIE = miI.end(); miII != miIE; ++miII){
-	//Out << "MI: "<<**miII<<"\n";
-	writeNumber(MIkey[*miII]);
-        //std::cerr<<"MachineInstruction= "<<MIkey[*miII]<<"\n";
+           miIE = miI.end(); miII != miIE; ++miII) {
+	     writeNumber(MIkey[*miII]);
       }
     }
   } 




From lattner at cs.uiuc.edu  Tue Jun  3 10:29:01 2003
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Tue Jun  3 10:29:01 2003
Subject: [llvm-commits] CVS: llvm/include/llvm/Target/TargetCacheInfo.h TargetMachine.h TargetOptInfo.h TargetRegInfo.h
Message-ID: <200306031528.KAA10127@apoc.cs.uiuc.edu>


Changes in directory llvm/include/llvm/Target:

TargetCacheInfo.h updated: 1.7 -> 1.8
TargetMachine.h updated: 1.30 -> 1.31
TargetOptInfo.h updated: 1.2 -> 1.3
TargetRegInfo.h updated: 1.36 -> 1.37

---
Log message:

Remove noncopyableV base classes, as they were confusing the doxygen documentation,
making it harder to read.


---
Diffs of the changes:

Index: llvm/include/llvm/Target/TargetCacheInfo.h
diff -u llvm/include/llvm/Target/TargetCacheInfo.h:1.7 llvm/include/llvm/Target/TargetCacheInfo.h:1.8
--- llvm/include/llvm/Target/TargetCacheInfo.h:1.7	Sat Dec 28 20:50:25 2002
+++ llvm/include/llvm/Target/TargetCacheInfo.h	Tue Jun  3 10:28:40 2003
@@ -10,8 +10,10 @@
 #include "Support/DataTypes.h"
 class TargetMachine;
 
-struct TargetCacheInfo : public NonCopyableV {
+struct TargetCacheInfo {
   const TargetMachine &target;
+  TargetCacheInfo(const TargetCacheInfo&); // DO NOT IMPLEMENT
+  void operator=(const TargetCacheInfo&);  // DO NOT IMPLEMENT
 protected:
   unsigned int           numLevels;
   std::vector<unsigned short> cacheLineSizes;
@@ -22,6 +24,7 @@
   TargetCacheInfo(const TargetMachine& tgt) : target(tgt) {
     Initialize();
   }
+  virtual ~TargetCacheInfo() {}
   
   // Default parameters are:
   //    NumLevels    = 2


Index: llvm/include/llvm/Target/TargetMachine.h
diff -u llvm/include/llvm/Target/TargetMachine.h:1.30 llvm/include/llvm/Target/TargetMachine.h:1.31
--- llvm/include/llvm/Target/TargetMachine.h:1.30	Sat Apr 26 15:10:54 2003
+++ llvm/include/llvm/Target/TargetMachine.h	Tue Jun  3 10:28:40 2003
@@ -28,10 +28,12 @@
 /// the target machine.  All target-specific information should be accessible
 /// through this interface.
 /// 
-class TargetMachine : public NonCopyableV {
+class TargetMachine {
   const std::string Name;
-  const TargetData DataLayout;		// Calculates type size & alignment
+  const TargetData DataLayout;		 // Calculates type size & alignment
   
+  TargetMachine(const TargetMachine&);   // DO NOT IMPLEMENT
+  void operator=(const TargetMachine&);  // DO NOT IMPLEMENT
 protected:
   TargetMachine(const std::string &name, // Can only create subclasses...
 		bool LittleEndian = false,


Index: llvm/include/llvm/Target/TargetOptInfo.h
diff -u llvm/include/llvm/Target/TargetOptInfo.h:1.2 llvm/include/llvm/Target/TargetOptInfo.h:1.3
--- llvm/include/llvm/Target/TargetOptInfo.h:1.2	Sat Dec 28 20:50:25 2002
+++ llvm/include/llvm/Target/TargetOptInfo.h	Tue Jun  3 10:28:40 2003
@@ -1,21 +1,24 @@
 //===-- llvm/Target/TargetOptInfo.h ------------------------------*- C++ -*-==//
 //
+//  FIXME: ADD A COMMENT DESCRIBING THIS FILE!
 //
 //===----------------------------------------------------------------------===//
 
 #ifndef LLVM_TARGET_TARGETOPTINFO_H
 #define LLVM_TARGET_TARGETOPTINFO_H
 
-#include "Support/DataTypes.h"
+class MachineInstr;
 class TargetMachine;
 
-struct TargetOptInfo : public NonCopyableV {
+struct TargetOptInfo {
   const TargetMachine &target;
   
+  TargetOptInfo(const TargetOptInfo &);   // DO NOT IMPLEMENT
+  void operator=(const TargetOptInfo &);  // DO NOT IMPLEMENT
 public:
-  TargetOptInfo(const TargetMachine& tgt): target(tgt) { }
+  TargetOptInfo(const TargetMachine &TM) : target(TM) { }
 
-  virtual bool IsUselessCopy    (const MachineInstr* MI) const = 0;
+  virtual bool IsUselessCopy(const MachineInstr* MI) const = 0;
 };
 
 #endif


Index: llvm/include/llvm/Target/TargetRegInfo.h
diff -u llvm/include/llvm/Target/TargetRegInfo.h:1.36 llvm/include/llvm/Target/TargetRegInfo.h:1.37
--- llvm/include/llvm/Target/TargetRegInfo.h:1.36	Sat May 31 02:44:07 2003
+++ llvm/include/llvm/Target/TargetRegInfo.h	Tue Jun  3 10:28:40 2003
@@ -8,7 +8,6 @@
 #ifndef LLVM_TARGET_TARGETREGINFO_H
 #define LLVM_TARGET_TARGETREGINFO_H
 
-#include "Support/NonCopyable.h"
 #include "Support/hash_map"
 #include <string>
 
@@ -56,7 +55,9 @@
 //---------------------------------------------------------------------------
 /// TargetRegInfo - Interface to register info of target machine
 ///
-class TargetRegInfo : public NonCopyableV {
+class TargetRegInfo {
+  TargetRegInfo(const TargetRegInfo &);  // DO NOT IMPLEMENT
+  void operator=(const TargetRegInfo &); // DO NOT IMPLEMENT
 protected:
   // A vector of all machine register classes
   //
@@ -71,7 +72,7 @@
   static int getInvalidRegNum() { return -1; }
 
   TargetRegInfo(const TargetMachine& tgt) : target(tgt) { }
-  ~TargetRegInfo() {
+  virtual ~TargetRegInfo() {
     for (unsigned i = 0, e = MachineRegClassArr.size(); i != e; ++i)
       delete MachineRegClassArr[i];
   }




From lattner at cs.uiuc.edu  Tue Jun  3 10:30:02 2003
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Tue Jun  3 10:30:02 2003
Subject: [llvm-commits] CVS: llvm/include/llvm/CodeGen/InstrForest.h
Message-ID: <200306031529.KAA10139@apoc.cs.uiuc.edu>


Changes in directory llvm/include/llvm/CodeGen:

InstrForest.h updated: 1.24 -> 1.25

---
Log message:

Remove noncopyable base class as it was making the doxygen docs harder to read


---
Diffs of the changes:

Index: llvm/include/llvm/CodeGen/InstrForest.h
diff -u llvm/include/llvm/CodeGen/InstrForest.h:1.24 llvm/include/llvm/CodeGen/InstrForest.h:1.25
--- llvm/include/llvm/CodeGen/InstrForest.h:1.24	Sat Aug 24 16:02:42 2002
+++ llvm/include/llvm/CodeGen/InstrForest.h	Tue Jun  3 10:29:12 2003
@@ -20,7 +20,6 @@
 #define LLVM_CODEGEN_INSTRFOREST_H
 
 #include "llvm/Instruction.h"
-#include "Support/NonCopyable.h"
 #include "Support/HashExtras.h"
 
 class Constant;
@@ -106,7 +105,9 @@
 // instruction selection via BURG.
 //------------------------------------------------------------------------ 
 
-class InstrTreeNode : public NonCopyableV {
+class InstrTreeNode {
+  InstrTreeNode(const InstrTreeNode &);   // DO NOT IMPLEMENT
+  void operator=(const InstrTreeNode &);  // DO NOT IMPLEMENT
 public:
   enum InstrTreeNodeType { NTInstructionNode,
 			   NTVRegListNode,




From lattner at cs.uiuc.edu  Tue Jun  3 10:31:01 2003
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Tue Jun  3 10:31:01 2003
Subject: [llvm-commits] CVS: llvm/include/llvm/Intrinsics.h
Message-ID: <200306031530.KAA10188@apoc.cs.uiuc.edu>


Changes in directory llvm/include/llvm:

Intrinsics.h updated: 1.2 -> 1.3

---
Log message:

Add comment for doxygen for namespace


---
Diffs of the changes:

Index: llvm/include/llvm/Intrinsics.h
diff -u llvm/include/llvm/Intrinsics.h:1.2 llvm/include/llvm/Intrinsics.h:1.3
--- llvm/include/llvm/Intrinsics.h:1.2	Sat May 17 17:26:26 2003
+++ llvm/include/llvm/Intrinsics.h	Tue Jun  3 10:30:13 2003
@@ -9,6 +9,10 @@
 #ifndef LLVM_INTRINSICS_H
 #define LLVM_INTRINSICS_H
 
+/// LLVMIntrinsic Namespace - This namespace contains an enum with a value for
+/// every intrinsic/builtin function known by LLVM.  These enum values are
+/// returned by Function::getIntrinsicID().
+///
 namespace LLVMIntrinsic {
   enum ID {
     not_intrinsic = 0,   // Must be zero




From lattner at cs.uiuc.edu  Tue Jun  3 10:31:06 2003
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Tue Jun  3 10:31:06 2003
Subject: [llvm-commits] CVS: llvm/include/llvm/Analysis/DependenceGraph.h
Message-ID: <200306031530.KAA10220@apoc.cs.uiuc.edu>


Changes in directory llvm/include/llvm/Analysis:

DependenceGraph.h updated: 1.2 -> 1.3

---
Log message:

Minor cleanups:
  * LLVM #include should use "", not <>
  * Fix line wrapping
  * Remove noncopyable base class to improve doxygen output


---
Diffs of the changes:

Index: llvm/include/llvm/Analysis/DependenceGraph.h
diff -u llvm/include/llvm/Analysis/DependenceGraph.h:1.2 llvm/include/llvm/Analysis/DependenceGraph.h:1.3
--- llvm/include/llvm/Analysis/DependenceGraph.h:1.2	Wed Dec 11 23:31:26 2002
+++ llvm/include/llvm/Analysis/DependenceGraph.h	Tue Jun  3 10:30:01 2003
@@ -11,15 +11,14 @@
 // of the dependence.  This saves space and is important because dep. graphs
 // can grow quickly.  It works just fine because the standard idiom is to
 // start with a known node and enumerate the dependences to or from that node.
+//
 //===----------------------------------------------------------------------===//
 
 
 #ifndef LLVM_ANALYSIS_DEPENDENCEGRAPH_H
 #define LLVM_ANALYSIS_DEPENDENCEGRAPH_H
 
-
-#include <Support/NonCopyable.h>
-#include <Support/hash_map>
+#include "Support/hash_map"
 #include <iosfwd>
 #include <vector>
 #include <utility>
@@ -44,12 +43,6 @@
   IncomingFlag       = 0x10         // is this an incoming or outgoing dep?
 };
 
-#undef SUPPORTING_LOOP_DEPENDENCES
-#ifdef SUPPORTING_LOOP_DEPENDENCES
-typedef int   DependenceDistance;       // negative means unknown distance
-typedef short DependenceLevel;          // 0 means global level outside loops
-#endif
-
 
 //----------------------------------------------------------------------------
 // class Dependence:
@@ -62,9 +55,7 @@
   unsigned char  depType;
 
 public:
-  /*ctor*/      Dependence      (DepGraphNode* toOrFromN,
-                                 DependenceType type,
-                                 bool isIncoming)
+  Dependence(DepGraphNode* toOrFromN, DependenceType type, bool isIncoming)
     : toOrFromNode(toOrFromN),
       depType(type | (isIncoming? IncomingFlag : 0x0)) { }
 
@@ -72,7 +63,7 @@
     : toOrFromNode(D.toOrFromNode),
       depType(D.depType) { }
 
-  bool operator==(const Dependence& D) {
+  bool operator==(const Dependence& D) const {
     return toOrFromNode == D.toOrFromNode && depType == D.depType;
   }
 
@@ -111,8 +102,8 @@
 #ifdef SUPPORTING_LOOP_DEPENDENCES
 struct LoopDependence: public Dependence {
   DependenceDirection dir;
-  DependenceDistance  distance;
-  DependenceLevel     level;
+  int                 distance;
+  short               level;
   LoopInfo*           enclosingLoop;
 };
 #endif
@@ -166,7 +157,10 @@
 // for the node.
 //----------------------------------------------------------------------------
 
-class DependenceGraph: public NonCopyable {
+class DependenceGraph {
+  DependenceGraph(const DependenceGraph&); // DO NOT IMPLEMENT
+  void operator=(const DependenceGraph&);  // DO NOT IMPLEMENT
+
   typedef hash_map<Instruction*, DepGraphNode*> DepNodeMapType;
   typedef DepNodeMapType::      iterator       map_iterator;
   typedef DepNodeMapType::const_iterator const_map_iterator;
@@ -204,17 +198,33 @@
       ->getNodeInternal(const_cast<Instruction&>(inst));
   }
 
-        iterator inDepBegin (      DepGraphNode& T)       { return T.inDeps.begin(); }
-  const_iterator inDepBegin (const DepGraphNode& T) const { return T.inDeps.begin(); }
+  iterator inDepBegin(DepGraphNode& T) {
+    return T.inDeps.begin();
+  }
+  const_iterator inDepBegin (const DepGraphNode& T) const {
+    return T.inDeps.begin();
+  }
 
-        iterator inDepEnd   (      DepGraphNode& T)       { return T.inDeps.end(); }
-  const_iterator inDepEnd   (const DepGraphNode& T) const { return T.inDeps.end(); }
+  iterator inDepEnd(DepGraphNode& T) {
+    return T.inDeps.end();
+  }
+  const_iterator inDepEnd(const DepGraphNode& T) const {
+    return T.inDeps.end();
+  }
 
-        iterator outDepBegin(      DepGraphNode& F)       { return F.outDeps.begin();}
-  const_iterator outDepBegin(const DepGraphNode& F) const { return F.outDeps.begin();}
+  iterator outDepBegin(DepGraphNode& F) {
+    return F.outDeps.begin();
+  }
+  const_iterator outDepBegin(const DepGraphNode& F) const {
+    return F.outDeps.begin();
+  }
 
-        iterator outDepEnd  (      DepGraphNode& F)       { return F.outDeps.end(); }
-  const_iterator outDepEnd  (const DepGraphNode& F) const { return F.outDeps.end(); }
+  iterator outDepEnd(DepGraphNode& F) {
+    return F.outDeps.end();
+  }
+  const_iterator outDepEnd(const DepGraphNode& F) const {
+    return F.outDeps.end();
+  }
 
   /// Debugging support methods
   /// 
@@ -239,8 +249,8 @@
                          Instruction&  toI,
                          DependenceType      depType,
                          DependenceDirection dir,
-                         DependenceDistance  distance,
-                         DependenceLevel     level,
+                         int                 distance,
+                         short               level,
                          LoopInfo*           enclosingLoop);
 #endif // SUPPORTING_LOOP_DEPENDENCES
 };




From lattner at cs.uiuc.edu  Tue Jun  3 10:32:01 2003
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Tue Jun  3 10:32:01 2003
Subject: [llvm-commits] CVS: llvm/include/Support/CommandLine.h
Message-ID: <200306031531.KAA10296@apoc.cs.uiuc.edu>


Changes in directory llvm/include/Support:

CommandLine.h updated: 1.10 -> 1.11

---
Log message:

Add doxygen comment for namespace


---
Diffs of the changes:

Index: llvm/include/Support/CommandLine.h
diff -u llvm/include/Support/CommandLine.h:1.10 llvm/include/Support/CommandLine.h:1.11
--- llvm/include/Support/CommandLine.h:1.10	Thu May 22 15:25:57 2003
+++ llvm/include/Support/CommandLine.h	Tue Jun  3 10:30:37 2003
@@ -19,7 +19,10 @@
 #include <cstdarg>
 #include "boost/type_traits/object_traits.hpp"
 
-namespace cl {   // Short namespace to make usage concise
+/// cl Namespace - This namespace contains all of the command line option
+/// processing machinery.  It is intentionally a short name to make qualified
+/// usage concise.
+namespace cl {
 
 //===----------------------------------------------------------------------===//
 // ParseCommandLineOptions - Command line option processing entry point.




From lattner at cs.uiuc.edu  Tue Jun  3 10:32:06 2003
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Tue Jun  3 10:32:06 2003
Subject: [llvm-commits] CVS: llvm/lib/Target/X86/X86.h X86CodeEmitter.cpp
Message-ID: <200306031531.KAA10316@apoc.cs.uiuc.edu>


Changes in directory llvm/lib/Target/X86:

X86.h updated: 1.12 -> 1.13
X86CodeEmitter.cpp updated: 1.25 -> 1.26

---
Log message:

Add namespace comments for doxygen


---
Diffs of the changes:

Index: llvm/lib/Target/X86/X86.h
diff -u llvm/lib/Target/X86/X86.h:1.12 llvm/lib/Target/X86/X86.h:1.13
--- llvm/lib/Target/X86/X86.h:1.12	Sun Jan 12 18:45:29 2003
+++ llvm/lib/Target/X86/X86.h	Tue Jun  3 10:31:23 2003
@@ -41,9 +41,9 @@
 ///
 Pass *createEmitX86CodeToMemory();
 
-// Put symbolic names in a namespace to avoid causing these to clash with all
-// kinds of other things...
-//
+/// X86 namespace - This namespace contains all of the register and opcode enums
+/// used by the X86 backend.
+///
 namespace X86 {
   // Defines a large number of symbolic names for X86 registers.  This defines a
   // mapping from register name to register number.


Index: llvm/lib/Target/X86/X86CodeEmitter.cpp
diff -u llvm/lib/Target/X86/X86CodeEmitter.cpp:1.25 llvm/lib/Target/X86/X86CodeEmitter.cpp:1.26
--- llvm/lib/Target/X86/X86CodeEmitter.cpp:1.25	Sun Jun  1 23:13:58 2003
+++ llvm/lib/Target/X86/X86CodeEmitter.cpp	Tue Jun  3 10:31:23 2003
@@ -264,8 +264,9 @@
 
 
 
-
-namespace N86 {  // Native X86 Register numbers...
+/// N86 namespace - Native X86 Register numbers... used by X86 backend.
+///
+namespace N86 {
   enum {
     EAX = 0, ECX = 1, EDX = 2, EBX = 3, ESP = 4, EBP = 5, ESI = 6, EDI = 7
   };




From lattner at cs.uiuc.edu  Tue Jun  3 10:32:09 2003
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Tue Jun  3 10:32:09 2003
Subject: [llvm-commits] CVS: llvm/include/Support/NonCopyable.h
Message-ID: <200306031531.KAA10241@apoc.cs.uiuc.edu>


Changes in directory llvm/include/Support:

NonCopyable.h updated: 1.1 -> 1.2

---
Log message:

There are now no uses of NonCopyableV


---
Diffs of the changes:

Index: llvm/include/Support/NonCopyable.h
diff -u llvm/include/Support/NonCopyable.h:1.1 llvm/include/Support/NonCopyable.h:1.2
--- llvm/include/Support/NonCopyable.h:1.1	Mon Nov 26 18:02:45 2001
+++ llvm/include/Support/NonCopyable.h	Tue Jun  3 10:30:48 2003
@@ -23,15 +23,4 @@
   inline ~NonCopyable() {}
 };
 
-class NonCopyableV {
-  // Disable the copy constructor and the assignment operator
-  // by making them both private:
-  // 
-  NonCopyableV(const NonCopyableV &);            // DO NOT IMPLEMENT
-  NonCopyableV &operator=(const NonCopyableV &); // DO NOT IMPLEMENT
-protected:
-  inline NonCopyableV() {}
-  virtual ~NonCopyableV() {}
-};
-
 #endif




From lattner at cs.uiuc.edu  Tue Jun  3 10:42:01 2003
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Tue Jun  3 10:42:01 2003
Subject: [llvm-commits] CVS: llvm/include/llvm/CodeGen/MachineInstrBuilder.h
Message-ID: <200306031541.KAA17129@apoc.cs.uiuc.edu>


Changes in directory llvm/include/llvm/CodeGen:

MachineInstrBuilder.h updated: 1.13 -> 1.14

---
Log message:

Remove use of enum


---
Diffs of the changes:

Index: llvm/include/llvm/CodeGen/MachineInstrBuilder.h
diff -u llvm/include/llvm/CodeGen/MachineInstrBuilder.h:1.13 llvm/include/llvm/CodeGen/MachineInstrBuilder.h:1.14
--- llvm/include/llvm/CodeGen/MachineInstrBuilder.h:1.13	Wed Jan 15 13:22:23 2003
+++ llvm/include/llvm/CodeGen/MachineInstrBuilder.h	Tue Jun  3 10:41:45 2003
@@ -120,7 +120,7 @@
 /// itself.  NumOperands is the number of operands to the machine instruction to
 /// allow for memory efficient representation of machine instructions.
 ///
-inline MachineInstrBuilder BuildMI(MachineOpCode Opcode, unsigned NumOperands) {
+inline MachineInstrBuilder BuildMI(int Opcode, unsigned NumOperands) {
   return MachineInstrBuilder(new MachineInstr(Opcode, NumOperands, true, true));
 }
 
@@ -128,7 +128,7 @@
 /// destination virtual register.  NumOperands is the number of additional add*
 /// calls that are expected, it does not include the destination register.
 ///
-inline MachineInstrBuilder BuildMI(MachineOpCode Opcode, unsigned NumOperands,
+inline MachineInstrBuilder BuildMI(int Opcode, unsigned NumOperands,
                                    unsigned DestReg) {
   return MachineInstrBuilder(new MachineInstr(Opcode, NumOperands+1,
                                    true, true)).addReg(DestReg, MOTy::Def);
@@ -138,7 +138,7 @@
 /// BuildMI - This version of the builder inserts the built MachineInstr into
 /// the specified MachineBasicBlock.
 ///
-inline MachineInstrBuilder BuildMI(MachineBasicBlock *BB, MachineOpCode Opcode,
+inline MachineInstrBuilder BuildMI(MachineBasicBlock *BB, int Opcode,
                                    unsigned NumOperands) {
   return MachineInstrBuilder(new MachineInstr(BB, Opcode, NumOperands));
 }
@@ -148,7 +148,7 @@
 /// destination virtual register.  NumOperands is the number of additional add*
 /// calls that are expected, it does not include the destination register.
 ///
-inline MachineInstrBuilder BuildMI(MachineBasicBlock *BB, MachineOpCode Opcode,
+inline MachineInstrBuilder BuildMI(MachineBasicBlock *BB, int Opcode,
                                    unsigned NumOperands, unsigned DestReg) {
   return MachineInstrBuilder(new MachineInstr(BB, Opcode,
                                               NumOperands+1)).addReg(DestReg,




From lattner at cs.uiuc.edu  Tue Jun  3 10:43:02 2003
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Tue Jun  3 10:43:02 2003
Subject: [llvm-commits] CVS: llvm/lib/Target/X86/InstSelectSimple.cpp
Message-ID: <200306031542.KAA17316@apoc.cs.uiuc.edu>


Changes in directory llvm/lib/Target/X86:

InstSelectSimple.cpp updated: 1.103 -> 1.104

---
Log message:

Remove usage of typedef


---
Diffs of the changes:

Index: llvm/lib/Target/X86/InstSelectSimple.cpp
diff -u llvm/lib/Target/X86/InstSelectSimple.cpp:1.103 llvm/lib/Target/X86/InstSelectSimple.cpp:1.104
--- llvm/lib/Target/X86/InstSelectSimple.cpp:1.103	Sat May 31 22:38:24 2003
+++ llvm/lib/Target/X86/InstSelectSimple.cpp	Tue Jun  3 10:41:58 2003
@@ -27,8 +27,7 @@
 /// have a destination register in mind.
 inline static MachineInstrBuilder BMI(MachineBasicBlock *MBB,
                                       MachineBasicBlock::iterator &I,
-                                      MachineOpCode Opcode,
-                                      unsigned NumOperands,
+                                      int Opcode, unsigned NumOperands,
                                       unsigned DestReg) {
   assert(I >= MBB->begin() && I <= MBB->end() && "Bad iterator!");
   MachineInstr *MI = new MachineInstr(Opcode, NumOperands+1, true, true);
@@ -40,8 +39,7 @@
 /// instruction at as well as a basic block.
 inline static MachineInstrBuilder BMI(MachineBasicBlock *MBB,
                                       MachineBasicBlock::iterator &I,
-                                      MachineOpCode Opcode,
-                                      unsigned NumOperands) {
+                                      int Opcode, unsigned NumOperands) {
   assert(I >= MBB->begin() && I <= MBB->end() && "Bad iterator!");
   MachineInstr *MI = new MachineInstr(Opcode, NumOperands, true, true);
   I = MBB->insert(I, MI)+1;




From lattner at cs.uiuc.edu  Tue Jun  3 10:44:01 2003
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Tue Jun  3 10:44:01 2003
Subject: [llvm-commits] CVS: llvm/include/llvm/CodeGen/MachineInstr.h
Message-ID: <200306031543.KAA18290@apoc.cs.uiuc.edu>


Changes in directory llvm/include/llvm/CodeGen:

MachineInstr.h updated: 1.101 -> 1.102

---
Log message:

Minor cleanups:
  * Document the MOTy namespace correctly for doxygen
  * Eliminate usage of the MachineOpCode typedef, which should eventually
    be eliminated entirely.


---
Diffs of the changes:

Index: llvm/include/llvm/CodeGen/MachineInstr.h
diff -u llvm/include/llvm/CodeGen/MachineInstr.h:1.101 llvm/include/llvm/CodeGen/MachineInstr.h:1.102
--- llvm/include/llvm/CodeGen/MachineInstr.h:1.101	Mon Jun  2 17:07:37 2003
+++ llvm/include/llvm/CodeGen/MachineInstr.h	Tue Jun  3 10:42:53 2003
@@ -21,27 +21,24 @@
 
 typedef int MachineOpCode;
 
-///---------------------------------------------------------------------------
+//===----------------------------------------------------------------------===//
 /// Special flags on instructions that modify the opcode.
 /// These flags are unused for now, but having them enforces that some
 /// changes will be needed if they are used.
-///---------------------------------------------------------------------------
-
+///
 enum MachineOpCodeFlags {
   AnnulFlag,         /// 1 if annul bit is set on a branch
   PredTakenFlag,     /// 1 if branch should be predicted taken
   PredNotTakenFlag   /// 1 if branch should be predicted not taken
 };
 
-///---------------------------------------------------------------------------
+//===----------------------------------------------------------------------===//
 /// MOTy - MachineOperandType - This namespace contains an enum that describes
 /// how the machine operand is used by the instruction: is it read, defined, or
 /// both?  Note that the MachineInstr/Operator class currently uses bool
 /// arguments to represent this information instead of an enum.  Eventually this
 /// should change over to use this _easier to read_ representation instead.
 ///
-///---------------------------------------------------------------------------
-
 namespace MOTy {
   enum UseType {
     Use,             /// This machine operand is only read by the instruction
@@ -50,7 +47,7 @@
   };
 }
 
-//---------------------------------------------------------------------------
+//===----------------------------------------------------------------------===//
 // class MachineOperand 
 // 
 // Purpose:
@@ -83,7 +80,7 @@
 //   -	Ptr will also be of virtual register type MO_VirtualReg.
 //	Again, the field Value* value identifies the value.
 // 
-//---------------------------------------------------------------------------
+//===----------------------------------------------------------------------===//
 
 struct MachineOperand {
   enum MachineOperandType {
@@ -322,7 +319,7 @@
 };
 
 
-//---------------------------------------------------------------------------
+//===----------------------------------------------------------------------===//
 // class MachineInstr 
 // 
 // Purpose:
@@ -338,10 +335,10 @@
 //  (2) "Implicit operands" are values implicitly used or defined by the
 //      machine instruction, such as arguments to a CALL, return value of
 //      a CALL (if any), and return value of a RETURN.
-//---------------------------------------------------------------------------
+//===----------------------------------------------------------------------===//
 
 class MachineInstr {
-  MachineOpCode    opCode;              // the opcode
+  int              opCode;              // the opcode
   unsigned         opCodeFlags;         // flags modifying instrn behavior
   std::vector<MachineOperand> operands; // the operands
   unsigned numImplicitRefs;             // number of implicit operands
@@ -356,26 +353,26 @@
   MachineInstr(const MachineInstr &);  // DO NOT IMPLEMENT
   void operator=(const MachineInstr&); // DO NOT IMPLEMENT
 public:
-  MachineInstr(MachineOpCode Opcode, unsigned numOperands);
+  MachineInstr(int Opcode, unsigned numOperands);
 
   /// MachineInstr ctor - This constructor only does a _reserve_ of the
   /// operands, not a resize for them.  It is expected that if you use this that
   /// you call add* methods below to fill up the operands, instead of the Set
   /// methods.  Eventually, the "resizing" ctors will be phased out.
   ///
-  MachineInstr(MachineOpCode Opcode, unsigned numOperands, bool XX, bool YY);
+  MachineInstr(int Opcode, unsigned numOperands, bool XX, bool YY);
 
   /// MachineInstr ctor - Work exactly the same as the ctor above, except that
   /// the MachineInstr is created and added to the end of the specified basic
   /// block.
   ///
-  MachineInstr(MachineBasicBlock *MBB, MachineOpCode Opcode, unsigned numOps);
+  MachineInstr(MachineBasicBlock *MBB, int Opcode, unsigned numOps);
   
 
   // The opcode.
   // 
-  const MachineOpCode getOpcode() const { return opCode; }
-  const MachineOpCode getOpCode() const { return opCode; }
+  const int getOpcode() const { return opCode; }
+  const int getOpCode() const { return opCode; }
 
   // Opcode flags.
   // 
@@ -428,10 +425,17 @@
     return getImplicitOp(i).getVRegValue();
   }
 
-  inline void addImplicitRef    (Value* V,
-                                 bool isDef=false,bool isDefAndUse=false);
-  inline void setImplicitRef    (unsigned i, Value* V,
-                                 bool isDef=false, bool isDefAndUse=false);
+  void addImplicitRef(Value* V, bool isDef = false, bool isDefAndUse = false) {
+    ++numImplicitRefs;
+    addRegOperand(V, isDef, isDefAndUse);
+  }
+  void setImplicitRef(unsigned i, Value* V, bool isDef=false,
+                      bool isDefAndUse=false) {
+    assert(i < getNumImplicitRefs() && "setImplicitRef() out of range!");
+    SetMachineOperandVal(i + getNumOperands(),
+                         MachineOperand::MO_VirtualRegister,
+                         V, isDef, isDefAndUse);
+  }
 
   //
   // Information about registers used in this instruction.
@@ -608,7 +612,7 @@
   /// simply replace() and then set new operands with Set.*Operand methods
   /// below.
   /// 
-  void replace(MachineOpCode Opcode, unsigned numOperands);
+  void replace(int Opcode, unsigned numOperands);
 
   /// setOpcode - Replace the opcode of the current instruction with a new one.
   ///
@@ -721,38 +725,11 @@
 };
 
 
-// Define here to enable inlining of the functions used.
-// 
-void MachineInstr::addImplicitRef(Value* V,
-                                  bool isDef,
-                                  bool isDefAndUse)
-{
-  ++numImplicitRefs;
-  addRegOperand(V, isDef, isDefAndUse);
-}
-
-void MachineInstr::setImplicitRef(unsigned i,
-                                  Value* V,
-                                  bool isDef,
-                                  bool isDefAndUse)
-{
-  assert(i < getNumImplicitRefs() && "setImplicitRef() out of range!");
-  SetMachineOperandVal(i + getNumOperands(),
-                       MachineOperand::MO_VirtualRegister,
-                       V, isDef, isDefAndUse);
-}
-
-
-//---------------------------------------------------------------------------
+//===----------------------------------------------------------------------===//
 // Debugging Support
-//---------------------------------------------------------------------------
-
-std::ostream& operator<<        (std::ostream& os,
-                                 const MachineInstr& minstr);
 
-std::ostream& operator<<        (std::ostream& os,
-                                 const MachineOperand& mop);
-					 
-void PrintMachineInstructions   (const Function *F);
+std::ostream& operator<<(std::ostream &OS, const MachineInstr &MI);
+std::ostream& operator<<(std::ostream &OS, const MachineOperand &MO);
+void PrintMachineInstructions(const Function *F);
 
 #endif




From vadve at cs.uiuc.edu  Tue Jun  3 13:58:02 2003
From: vadve at cs.uiuc.edu (Vikram Adve)
Date: Tue Jun  3 13:58:02 2003
Subject: [llvm-commits] CVS: llvm/test/Makefile.tests
Message-ID: <200306031857.NAA06529@psmith.cs.uiuc.edu>


Changes in directory llvm/test:

Makefile.tests updated: 1.59 -> 1.60

---
Log message:

Improved how tracing can be used: 
-- added new targets %.trace-out-llc and %.trace-out-cbe
-- either TRACE=yes or TRACEM=yes is still needed and chooses how to trace


---
Diffs of the changes:

Index: llvm/test/Makefile.tests
diff -u llvm/test/Makefile.tests:1.59 llvm/test/Makefile.tests:1.60
--- llvm/test/Makefile.tests:1.59	Mon Jun  2 00:49:09 2003
+++ llvm/test/Makefile.tests	Tue Jun  3 13:56:53 2003
@@ -63,15 +63,21 @@
 NATGCC  = /usr/dcs/software/supported/bin/gcc
 CP	= /bin/cp -f
 
+## If TRACE or TRACEM is "yes", set the appropriate llc flag (-trace or -tracem)
+## mark that tracing on, and set the TRACELIBS variable.
 ifeq ($(TRACE), yes)
-    LLCFLAGS += -trace basicblock
-    LLCLIBS := -L$(LEVEL)/test/Libraries/Output -linstr64
+    LLCFLAGS += -trace
+    DOTRACING = yes
 else
     ifeq ($(TRACEM), yes)
-	LLCFLAGS += -trace function
-	LLCLIBS := -L$(LEVEL)/test/Libraries/Output -linstr64
+	LLCFLAGS += -tracem
+	DOTRACING = yes
     endif
 endif
+ifeq ($(DOTRACING), yes)
+    TRACELIBS := -L$(LEVEL)/test/Libraries/Output -linstr64
+endif
+
 
 LLCLIBS := $(LLCLIBS) -lm
 




From vadve at cs.uiuc.edu  Tue Jun  3 13:58:07 2003
From: vadve at cs.uiuc.edu (Vikram Adve)
Date: Tue Jun  3 13:58:07 2003
Subject: [llvm-commits] CVS: llvm/test/Programs/Makefile.programs
Message-ID: <200306031857.NAA06536@psmith.cs.uiuc.edu>


Changes in directory llvm/test/Programs:

Makefile.programs updated: 1.53 -> 1.54

---
Log message:

Improved how tracing can be used: 
-- added new targets %.trace-out-llc and %.trace-out-cbe
-- either TRACE=yes or TRACEM=yes is still needed and chooses how to trace


---
Diffs of the changes:

Index: llvm/test/Programs/Makefile.programs
diff -u llvm/test/Programs/Makefile.programs:1.53 llvm/test/Programs/Makefile.programs:1.54
--- llvm/test/Programs/Makefile.programs:1.53	Sun Jun  1 21:01:59 2003
+++ llvm/test/Programs/Makefile.programs	Tue Jun  3 13:56:57 2003
@@ -89,6 +89,8 @@
 # Generated code for llc (which does not require the target platform)
 LLCCODEGEN := $(addsuffix .llc.s,   $(PREFIXED_PROGRAMS_TO_TEST))
 CBECODEGEN := $(addsuffix .cbe.c,   $(PREFIXED_PROGRAMS_TO_TEST))
+LLCTRACECODEGEN := $(addsuffix .trace.llc.s, $(PREFIXED_PROGRAMS_TO_TEST))
+CBETRACECODEGEN := $(addsuffix .trace.cbe.c, $(PREFIXED_PROGRAMS_TO_TEST))
 
 # Output produced by programs run
 GCCOUTPUT := $(addsuffix .ll,       $(addprefix Output/,$basename $(Source)))
@@ -112,6 +114,7 @@
 .PRECIOUS: Output/%.diff-lli Output/%.diff-jit
 .PRECIOUS: Output/%.diff-llc Output/%.diff-cbe
 
+
 # Regardless of what other options are specified, build the program's bytecode
 # representation.
 all:: $(BYTECODE)
@@ -122,13 +125,23 @@
 endif
 
 ifndef DISABLE_LLC
+ifeq ($(DOTRACING), yes)
+all:: $(LLCTRACECODEGEN)
+DISABLE_LLC_DIFFS = 1
+else
 all:: $(LLCCODEGEN)
+endif
 else
 DISABLE_LLC_DIFFS = 1
 endif
 
 ifndef DISABLE_CBE
+ifeq ($(DOTRACING), yes)
+all:: $(CBETRACECODEGEN)
+DISABLE_CBE_DIFFS = 1
+else
 all:: $(CBECODEGEN)
+endif
 else
 DISABLE_CBE_DIFFS = 1
 endif
@@ -200,6 +213,14 @@
 Output/%.cbe: Output/%.cbe.c
 	-$(CC) -o $@ $< $(LDFLAGS) $(CFLAGS)
 
+$(PROGRAMS_TO_TEST:%=Output/%.trace.cbe.c): \
+Output/%.trace.cbe.c: Output/%.llvm.trace.bc $(LDIS)
+	-$(LDIS) -c < $< > $@
+
+$(PROGRAMS_TO_TEST:%=Output/%.trace.cbe): \
+Output/%.trace.cbe: Output/%.trace.cbe.c
+	-$(CC) -o $@ $< $(LDFLAGS) $(CFLAGS) $(TRACELIBS)
+
 #
 # Compile a linked program to machine code with LLC.
 #
@@ -207,12 +228,20 @@
 Output/%.llc.s: Output/%.llvm.bc $(LLC)
 	-$(LLC) $(LLCFLAGS) -f $< -o $@
 
+$(PROGRAMS_TO_TEST:%=Output/%.trace.llc.s): \
+Output/%.trace.llc.s: Output/%.llvm.bc $(LLC)
+	-$(LLC) $(LLCFLAGS) -f $< -o $@
+
 # Assemble (and link) an LLVM-linked program using the system assembler...
 #
 $(PROGRAMS_TO_TEST:%=Output/%.llc): \
 Output/%.llc: Output/%.llc.s
 	-$(CC) $(CFLAGS) $< $(LLCLIBS) -o $@
 
+$(PROGRAMS_TO_TEST:%=Output/%.trace.llc): \
+Output/%.trace.llc: Output/%.trace.llc.s
+	-$(CC) $(CFLAGS) $< $(LLCLIBS) $(TRACELIBS) -o $@
+
 
 #
 # Rules to execute the program
@@ -248,6 +277,14 @@
 
 $(PROGRAMS_TO_TEST:%=Output/%.out-cbe): \
 Output/%.out-cbe: Output/%.cbe
+	-$(RUNSAFELY) $(STDIN_FILENAME) $@ $< $(RUN_OPTIONS)
+
+$(PROGRAMS_TO_TEST:%=Output/%.trace-out-llc): \
+Output/%.trace-out-llc: Output/%.trace.llc
+	-$(RUNSAFELY) $(STDIN_FILENAME) $@ $< $(RUN_OPTIONS)
+
+$(PROGRAMS_TO_TEST:%=Output/%.trace-out-cbe): \
+Output/%.trace-out-cbe: Output/%.trace.cbe
 	-$(RUNSAFELY) $(STDIN_FILENAME) $@ $< $(RUN_OPTIONS)
 endif
 




From vadve at cs.uiuc.edu  Tue Jun  3 14:00:01 2003
From: vadve at cs.uiuc.edu (Vikram Adve)
Date: Tue Jun  3 14:00:01 2003
Subject: [llvm-commits] CVS: llvm/test/Programs/SingleSource/UnitTests/2003-05-26-Shorts.c
Message-ID: <200306031859.NAA06557@psmith.cs.uiuc.edu>


Changes in directory llvm/test/Programs/SingleSource/UnitTests:

2003-05-26-Shorts.c updated: 1.2 -> 1.3

---
Log message:

Pull out constant to prevent constant folding.


---
Diffs of the changes:

Index: llvm/test/Programs/SingleSource/UnitTests/2003-05-26-Shorts.c
diff -u llvm/test/Programs/SingleSource/UnitTests/2003-05-26-Shorts.c:1.2 llvm/test/Programs/SingleSource/UnitTests/2003-05-26-Shorts.c:1.3
--- llvm/test/Programs/SingleSource/UnitTests/2003-05-26-Shorts.c:1.2	Fri May 30 00:14:24 2003
+++ llvm/test/Programs/SingleSource/UnitTests/2003-05-26-Shorts.c	Tue Jun  3 13:59:34 2003
@@ -9,10 +9,16 @@
  */
 #include <stdio.h>
 
+/* Move the value here to prevent constant folding */
+unsigned long long getL()
+{
+  return 0xafafafafc5c5b8a3ull;
+}
+
 int
 main(int argc, char** argv)
 {
-  unsigned long long  UL = 0xafafafafc5c5b8a3ULL;
+  unsigned long long  UL = getL();                   /* 0xafafafafc5c5b8a3 */
            long long   L = (long long) UL;
 
   unsigned int   ui = (unsigned int) UL;        /* 0xc5c5b8a3 =  3318069411 */




From vadve at cs.uiuc.edu  Tue Jun  3 14:02:02 2003
From: vadve at cs.uiuc.edu (Vikram Adve)
Date: Tue Jun  3 14:02:02 2003
Subject: [llvm-commits] CVS: llvm/test/Programs/MultiSource/Fhourstones/Makefile
Message-ID: <200306031901.OAA06585@psmith.cs.uiuc.edu>


Changes in directory llvm/test/Programs/MultiSource/Fhourstones:

Makefile updated: 1.4 -> 1.5

---
Log message:

Increase time limit for SPARC!


---
Diffs of the changes:

Index: llvm/test/Programs/MultiSource/Fhourstones/Makefile
diff -u llvm/test/Programs/MultiSource/Fhourstones/Makefile:1.4 llvm/test/Programs/MultiSource/Fhourstones/Makefile:1.5
--- llvm/test/Programs/MultiSource/Fhourstones/Makefile:1.4	Sun Jun  1 21:02:02 2003
+++ llvm/test/Programs/MultiSource/Fhourstones/Makefile	Tue Jun  3 14:01:11 2003
@@ -6,4 +6,6 @@
 # Specify which file provides the contents of stdin for the test run 
 STDIN_FILENAME = input
 
+RUNTIMELIMIT = 300
+
 include	../Makefile.multisrc




From vadve at cs.uiuc.edu  Tue Jun  3 14:02:05 2003
From: vadve at cs.uiuc.edu (Vikram Adve)
Date: Tue Jun  3 14:02:05 2003
Subject: [llvm-commits] CVS: llvm/test/Programs/MultiSource/McCat-08-main/Makefile
Message-ID: <200306031901.OAA06592@psmith.cs.uiuc.edu>


Changes in directory llvm/test/Programs/MultiSource/McCat-08-main:

Makefile updated: 1.1 -> 1.2

---
Log message:

Increase time limit for SPARC!


---
Diffs of the changes:

Index: llvm/test/Programs/MultiSource/McCat-08-main/Makefile
diff -u llvm/test/Programs/MultiSource/McCat-08-main/Makefile:1.1 llvm/test/Programs/MultiSource/McCat-08-main/Makefile:1.2
--- llvm/test/Programs/MultiSource/McCat-08-main/Makefile:1.1	Mon May 12 13:26:43 2003
+++ llvm/test/Programs/MultiSource/McCat-08-main/Makefile	Tue Jun  3 14:01:12 2003
@@ -1,6 +1,7 @@
 LEVEL = ../../../..
 PROG = main
 LDFLAGS = -lm
+RUNTIMELIMIT = 300
 
 include ../Makefile.multisrc
 




From vadve at cs.uiuc.edu  Tue Jun  3 14:08:06 2003
From: vadve at cs.uiuc.edu (Vikram Adve)
Date: Tue Jun  3 14:08:06 2003
Subject: [llvm-commits] CVS: llvm/test/Programs/MultiSource/Fhourstones/trans.c
Message-ID: <200306031907.OAA06608@psmith.cs.uiuc.edu>


Changes in directory llvm/test/Programs/MultiSource/Fhourstones:

trans.c updated: 1.1 -> 1.2

---
Log message:

Add stdlib.h to prevent error on Sparc.


---
Diffs of the changes:

Index: llvm/test/Programs/MultiSource/Fhourstones/trans.c
diff -u llvm/test/Programs/MultiSource/Fhourstones/trans.c:1.1 llvm/test/Programs/MultiSource/Fhourstones/trans.c:1.2
--- llvm/test/Programs/MultiSource/Fhourstones/trans.c:1.1	Wed Oct  2 14:30:25 2002
+++ llvm/test/Programs/MultiSource/Fhourstones/trans.c	Tue Jun  3 14:07:23 2003
@@ -1,3 +1,4 @@
+#include "stdlib.h"
 #include "types.h"
 #include "c4.h"
 




From gaeke at cs.uiuc.edu  Tue Jun  3 14:31:01 2003
From: gaeke at cs.uiuc.edu (Brian Gaeke)
Date: Tue Jun  3 14:31:01 2003
Subject: [llvm-commits] CVS: llvm/lib/CodeGen/Mapping/MappingInfo.cpp
Message-ID: <200306031930.OAA18143@neo.cs.uiuc.edu>


Changes in directory llvm/lib/CodeGen/Mapping:

MappingInfo.cpp updated: 1.5 -> 1.6

---
Log message:

Make the write*map methods more self-contained. Document some more.


---
Diffs of the changes:

Index: llvm/lib/CodeGen/Mapping/MappingInfo.cpp
diff -u llvm/lib/CodeGen/Mapping/MappingInfo.cpp:1.5 llvm/lib/CodeGen/Mapping/MappingInfo.cpp:1.6
--- llvm/lib/CodeGen/Mapping/MappingInfo.cpp:1.5	Tue Jun  3 02:56:05 2003
+++ llvm/lib/CodeGen/Mapping/MappingInfo.cpp	Tue Jun  3 14:30:15 2003
@@ -34,71 +34,79 @@
     std::map<const Function*, unsigned> Fkey; //key of F to num
     std::map<const MachineInstr*, unsigned> BBkey; //key BB to num
     std::map<const MachineInstr*, unsigned> MIkey; //key MI to num
-    
+    void writePrologue(const std::string &comment,
+                       const std::string &symbolPrefix, unsigned num);
+    void writeEpilogue(const std::string &symbolPrefix, unsigned num);
+
     bool doInitialization(Module &M);
     void create_BB_to_MInumber_Key(Function &FI);    
     void create_MI_to_number_Key(Function &FI);
-    void writeBBToMImap(Function &FI);
-    void writeLLVMToMImap(Function &FI);
-    void getMappingInfoForFunction::writePrologue(const char * area,    
-						  const char *label,
-						  unsigned FunctionNo);
-    void getMappingInfoForFunction::writeEpilogue(const char *area, 
-						  const char *label,
-						  unsigned FunctionNo);
+    void writeBBToMImap(Function &FI, unsigned num);
+    void writeLLVMToMImap(Function &FI, unsigned num);
     unsigned writeNumber(unsigned X);
   };
 }
 
 /// MappingInfoForFunction -- Static factory method: returns a new
-/// getMappingInfoForFunction Pass object.
+/// getMappingInfoForFunction Pass object, which uses OUT as its
+/// output stream for assembly output. 
 Pass *MappingInfoForFunction(std::ostream &out){
   return (new getMappingInfoForFunction(out));
 }
 
-/// runOnFunction -- Builds up the maps for the given function and then
-/// writes them out as assembly code to the current output stream Out.
+/// runOnFunction -- Builds up the maps for the given function FI and then
+/// writes them out as assembly code to the current output stream OUT.
 /// This is an entry point to the pass, called by the PassManager.
 bool getMappingInfoForFunction::runOnFunction(Function &FI) {
-  // First we build up the maps.
+  // First we build temporary tables used to write out the maps.
   create_BB_to_MInumber_Key(FI);
   create_MI_to_number_Key(FI);
-  unsigned FunctionNo = Fkey[&FI];
+  unsigned num = Fkey[&FI]; // Function number for the current function.
+
+  // Now, write out the maps.
+  writeBBToMImap(FI, num);
+  writeLLVMToMImap(FI, num);
 
-  // Now, print out the maps.
-  writePrologue("BB TO MI MAP", "BBMIMap", FunctionNo);
-  writeBBToMImap(FI);
-  writeEpilogue("BB TO MI MAP", "BBMIMap", FunctionNo);  
-  
-  writePrologue("LLVM I TO MI MAP", "LMIMap", FunctionNo);
-  writeLLVMToMImap(FI);
-  writeEpilogue("LLVM I TO MI MAP", "LMIMap", FunctionNo); 
   return false; 
 }  
 
-void getMappingInfoForFunction::writePrologue(const char *area,
-					      const char *label, 
-					      unsigned FunctionNo){
-  Out << "!" << area << "\n";   
+/// writePrologue -- Output a COMMENT describing the map, then output a
+/// global symbol to start the map named by concatenating SYMBOLPREFIX
+/// and NUM, then output a word containing the length of the map, to the
+/// current output stream Out. This also switches the current section to
+/// .rodata in the assembly output.
+void getMappingInfoForFunction::writePrologue(const std::string &comment,
+                                              const std::string &symbolPrefix,
+                                              unsigned num) {
+  // Comment:
+  Out << "!" << comment << "\n";   
+  // Switch sections:
   Out << "\t.section \".rodata\"\n\t.align 8\n";  
-  Out << "\t.global " << label << FunctionNo << "\n";    
-  Out << "\t.type " << label << FunctionNo << ",#object\n"; 
-  Out << label << FunctionNo << ":\n"; 
-  Out << "\t.word .end_" << label << FunctionNo << "-"
-      << label << FunctionNo << "\n";
-}
-
-void getMappingInfoForFunction::writeEpilogue(const char *area,
-					      const char *label,
-					      unsigned FunctionNo){
-  Out << ".end_" << label << FunctionNo << ":\n";    
-  Out << "\t.size " << label << FunctionNo << ", .end_" 
-      << label << FunctionNo << "-" << label 
-      << FunctionNo << "\n\n\n\n";
+  // Global symbol naming the map:
+  Out << "\t.global " << symbolPrefix << num << "\n";    
+  Out << "\t.type " << symbolPrefix << num << ",#object\n"; 
+  Out << symbolPrefix << num << ":\n"; 
+  // Length word:
+  Out << "\t.word .end_" << symbolPrefix << num << "-"
+      << symbolPrefix << num << "\n";
+}
+
+/// writeEpilogue -- Outputs a local symbol to end the map named by
+/// concatenating SYMBOLPREFIX and NUM, followed by a .size directive that
+/// gives the size of the map, to the current output stream Out.
+void getMappingInfoForFunction::writeEpilogue(const std::string &symbolPrefix,
+                                              unsigned num) {
+  // Local symbol ending the map:
+  Out << ".end_" << symbolPrefix << num << ":\n";    
+  // Size directive:
+  Out << "\t.size " << symbolPrefix << num << ", .end_" 
+      << symbolPrefix << num << "-" << symbolPrefix 
+      << num << "\n\n\n\n";
 }
 
 /// writeNumber -- Write out the number X as a sequence of .byte
-/// directives to the current output stream Out.
+/// directives to the current output stream Out. This method performs a
+/// run-length encoding of the unsigned integers X that are output.
 unsigned getMappingInfoForFunction::writeNumber(unsigned X) {
   unsigned i=0;
   do {
@@ -173,8 +181,11 @@
 /// the number of the MachineBasicBlock in the function as computed by
 /// create_BB_to_MInumber_Key; and third, the number of MachineInstrs in
 /// the MachineBasicBlock.
-void getMappingInfoForFunction::writeBBToMImap(Function &FI){
+void getMappingInfoForFunction::writeBBToMImap(Function &FI, unsigned num){
   unsigned bb = 0;
+  const std::string MapComment = "BB TO MI MAP";
+  const std::string MapSymbolPrefix = "BBMIMap";
+  writePrologue(MapComment, MapSymbolPrefix, num);
   MachineFunction &MF = MachineFunction::get(&FI);  
   for (MachineFunction::iterator BI = MF.begin(), BE = MF.end();
        BI != BE; ++BI, ++bb) {
@@ -183,6 +194,7 @@
     writeNumber(BBkey[miBB[0]]);
     writeNumber(miBB.size());
   }
+  writeEpilogue(MapSymbolPrefix, num);  
 }
 
 /// writeLLVMToMImap -- Output the LLVM I TO MI MAP for the given function
@@ -197,9 +209,11 @@
 /// (as reported by MachineCodeForInstruction), and 3) the MachineInstr
 /// number calculated by create_MI_to_number_Key, for each of the
 /// MachineInstrs that correspond to that Instruction.
-void getMappingInfoForFunction::writeLLVMToMImap(Function &FI) {
-
+void getMappingInfoForFunction::writeLLVMToMImap(Function &FI, unsigned num) {
   unsigned bb = 0;
+  const std::string MapComment = "LLVM I TO MI MAP";
+  const std::string MapSymbolPrefix = "LMIMap";
+  writePrologue(MapComment, MapSymbolPrefix, num);
   for (Function::iterator BI = FI.begin(), BE = FI.end(); 
        BI != BE; ++BI, ++bb) {
     unsigned li = 0;
@@ -216,4 +230,5 @@
       }
     }
   } 
+  writeEpilogue(MapSymbolPrefix, num); 
 }




From brukman at cs.uiuc.edu  Tue Jun  3 15:01:01 2003
From: brukman at cs.uiuc.edu (Misha Brukman)
Date: Tue Jun  3 15:01:01 2003
Subject: [llvm-commits] CVS: llvm/lib/CodeGen/MachineCodeEmitter.cpp
Message-ID: <200306032000.PAA29837@zion.cs.uiuc.edu>


Changes in directory llvm/lib/CodeGen:

MachineCodeEmitter.cpp updated: 1.11 -> 1.12

---
Log message:

Pass through the emitConstantPool() call to the real emitter.


---
Diffs of the changes:

Index: llvm/lib/CodeGen/MachineCodeEmitter.cpp
diff -u llvm/lib/CodeGen/MachineCodeEmitter.cpp:1.11 llvm/lib/CodeGen/MachineCodeEmitter.cpp:1.12
--- llvm/lib/CodeGen/MachineCodeEmitter.cpp:1.11	Mon Jun  2 15:49:09 2003
+++ llvm/lib/CodeGen/MachineCodeEmitter.cpp	Tue Jun  3 15:00:49 2003
@@ -93,6 +93,10 @@
       MCE.finishFunction(F);
     }
 
+    void emitConstantPool(MachineConstantPool *MCP) {
+      MCE.emitConstantPool(MCP);
+    }
+
     void startFunctionStub(const Function &F, unsigned StubSize) {
       MCE.startFunctionStub(F, StubSize);
     }




From lattner at cs.uiuc.edu  Tue Jun  3 20:25:01 2003
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Tue Jun  3 20:25:01 2003
Subject: [llvm-commits] CVS: llvm/lib/CodeGen/PreOpts/PreSelection.cpp
Message-ID: <200306040124.UAA24297@apoc.cs.uiuc.edu>


Changes in directory llvm/lib/CodeGen/PreOpts:

PreSelection.cpp updated: 1.11 -> 1.12

---
Log message:

Avoid generating a getelementptr instruction of a function


---
Diffs of the changes:

Index: llvm/lib/CodeGen/PreOpts/PreSelection.cpp
diff -u llvm/lib/CodeGen/PreOpts/PreSelection.cpp:1.11 llvm/lib/CodeGen/PreOpts/PreSelection.cpp:1.12
--- llvm/lib/CodeGen/PreOpts/PreSelection.cpp:1.11	Sat May 31 02:34:57 2003
+++ llvm/lib/CodeGen/PreOpts/PreSelection.cpp	Tue Jun  3 20:24:40 2003
@@ -177,7 +177,7 @@
   if (isa<ConstantPointerRef>(ptr))
     ptr = cast<ConstantPointerRef>(ptr)->getValue();
 
-  return (isa<GlobalValue>(ptr))
+  return (isa<GlobalVariable>(ptr))
     ? new GetElementPtrInst(ptr,
                     std::vector<Value*>(1, ConstantSInt::get(Type::LongTy, 0U)),
                     "addrOfGlobal", &insertBefore)




From brukman at cs.uiuc.edu  Tue Jun  3 20:58:01 2003
From: brukman at cs.uiuc.edu (Misha Brukman)
Date: Tue Jun  3 20:58:01 2003
Subject: [llvm-commits] CVS: llvm/tools/lli/JIT/Intercept.cpp
Message-ID: <200306040157.UAA03629@zion.cs.uiuc.edu>


Changes in directory llvm/tools/lli/JIT:

Intercept.cpp updated: 1.3 -> 1.4

---
Log message:

Sparc's dlsym() requires the special operand RTLD_SELF to find a symbol in the
currently-running process.


---
Diffs of the changes:

Index: llvm/tools/lli/JIT/Intercept.cpp
diff -u llvm/tools/lli/JIT/Intercept.cpp:1.3 llvm/tools/lli/JIT/Intercept.cpp:1.4
--- llvm/tools/lli/JIT/Intercept.cpp:1.3	Wed May 14 08:53:40 2003
+++ llvm/tools/lli/JIT/Intercept.cpp	Tue Jun  3 20:57:22 2003
@@ -54,7 +54,11 @@
   if (Name == "atexit") return (void*)&jit_atexit;
 
   // If it's an external function, look it up in the process image...
+#if defined(i386) || defined(__i386__) || defined(__x86__)
   void *Ptr = dlsym(0, Name.c_str());
+#elif defined(sparc) || defined(__sparc__) || defined(__sparcv9)
+  void *Ptr = dlsym(RTLD_SELF, Name.c_str());
+#endif
   if (Ptr == 0) {
     std::cerr << "WARNING: Cannot resolve fn '" << Name
 	      << "' using a dummy noop function instead!\n";




From vadve at cs.uiuc.edu  Tue Jun  3 21:11:01 2003
From: vadve at cs.uiuc.edu (Vikram Adve)
Date: Tue Jun  3 21:11:01 2003
Subject: [llvm-commits] CVS: llvm/lib/Target/TargetData.cpp
Message-ID: <200306040210.VAA09150@psmith.cs.uiuc.edu>


Changes in directory llvm/lib/Target:

TargetData.cpp updated: 1.33 -> 1.34

---
Log message:

Undo one of those last fixes -- it was incorrect.


---
Diffs of the changes:

Index: llvm/lib/Target/TargetData.cpp
diff -u llvm/lib/Target/TargetData.cpp:1.33 llvm/lib/Target/TargetData.cpp:1.34
--- llvm/lib/Target/TargetData.cpp:1.33	Mon Jun  2 00:21:06 2003
+++ llvm/lib/Target/TargetData.cpp	Tue Jun  3 21:10:37 2003
@@ -193,10 +193,12 @@
       Ty = cast<SequentialType>(Ty)->getElementType();
 
       // Get the array index and the size of each array element.
-      // Both must be known constants, or the index shd be 0; else this fails.
+      // The size must be a known value, except if arrayIdx is 0.
+      // In particular, don't try to get the type size if the arrayIdx is 0:
+      // 0 index into an unsized type is legal and should be allowed.
       int64_t arrayIdx = cast<ConstantSInt>(Idx[CurIDX])->getValue();
-      Result += arrayIdx * (int64_t)getTypeSize(Ty);
-
+      Result += arrayIdx == 0? 0
+                             : arrayIdx * (int64_t)getTypeSize(Ty);
     } else {
       const StructType *STy = cast<StructType>(Ty);
       assert(Idx[CurIDX]->getType() == Type::UByteTy && "Illegal struct idx");




From brukman at cs.uiuc.edu  Tue Jun  3 21:27:01 2003
From: brukman at cs.uiuc.edu (Misha Brukman)
Date: Tue Jun  3 21:27:01 2003
Subject: [llvm-commits] CVS: llvm/lib/Target/Sparc/SparcV9.td SparcV9_F3.td
Message-ID: <200306040226.VAA03738@zion.cs.uiuc.edu>


Changes in directory llvm/lib/Target/Sparc:

SparcV9.td updated: 1.12 -> 1.13
SparcV9_F3.td updated: 1.8 -> 1.9

---
Log message:

Added instruction format class 3.15 and floating-point compare instructions.


---
Diffs of the changes:

Index: llvm/lib/Target/Sparc/SparcV9.td
diff -u llvm/lib/Target/Sparc/SparcV9.td:1.12 llvm/lib/Target/Sparc/SparcV9.td:1.13
--- llvm/lib/Target/Sparc/SparcV9.td:1.12	Mon Jun  2 22:20:14 2003
+++ llvm/lib/Target/Sparc/SparcV9.td	Tue Jun  3 21:26:14 2003
@@ -188,15 +188,12 @@
 def FSUBQ : F3_16<2, 0b110100, 0x47, "fsubq">;    // fsubq f, f, f
 
 // Section A.13: Floating-point compare - p159
-// FIXME: FCMPS, FCMPD, FCMPQ !!!
-#if 0
-def FSTOX : F3_14<2, 0b110100, 0b011001001, "fstod">;   // fstod rs2, rd
-def FDTOX : F3_14<2, 0b110100, 0b011001101, "fstoq">;   // fstoq rs2, rd
-def FQTOX : F3_14<2, 0b110100, 0b011000110, "fstos">;   // fstos rs2, rd
-def FSTOI : F3_14<2, 0b110100, 0b011001110, "fdtoq">;   // fdtoq rs2, rd
-def FDTOI : F3_14<2, 0b110100, 0b011000111, "fqtos">;   // fqtos rs2, rd
-def FQTOI : F3_14<2, 0b110100, 0b011001011, "fqtod">;   // fqtod rs2, rd
-#endif
+def FCMPS  : F3_15<2, 0b110101, 0b010100001, "fcmps">;   // fcmps  %fcc, r1, r2
+def FCMPD  : F3_15<2, 0b110101, 0b010100010, "fcmpd">;   // fcmpd  %fcc, r1, r2
+def FCMPQ  : F3_15<2, 0b110101, 0b010100011, "fcmpq">;   // fcmpq  %fcc, r1, r2
+def FCMPES : F3_15<2, 0b110101, 0b010100101, "fcmpes">;  // fcmpes %fcc, r1, r2
+def FCMPED : F3_15<2, 0b110101, 0b010100110, "fcmped">;  // fcmped %fcc, r1, r2
+def FCMPEQ : F3_15<2, 0b110101, 0b010100111, "fcmpeq">;  // fcmpeq %fcc, r1, r2
 
 // Section A.14: Convert floating-point to integer - p161
 def FSTOX : F3_14<2, 0b110100, 0b010000001, "fstox">;   // fstox rs2, rd


Index: llvm/lib/Target/Sparc/SparcV9_F3.td
diff -u llvm/lib/Target/Sparc/SparcV9_F3.td:1.8 llvm/lib/Target/Sparc/SparcV9_F3.td:1.9
--- llvm/lib/Target/Sparc/SparcV9_F3.td:1.8	Mon Jun  2 22:20:14 2003
+++ llvm/lib/Target/Sparc/SparcV9_F3.td	Tue Jun  3 21:26:14 2003
@@ -202,12 +202,26 @@
 }
 
 class F3_14<bits<2> opVal, bits<6> op3Val,
-            bits<9> opfval, string name> : F3_rs2rd {
+            bits<9> opfVal, string name> : F3_rs2rd {
   set op  = opVal;
   set op3 = op3Val;
   set Name = name;
   //set Inst{18-14} = dontcare;
-  set Inst{13-5} = opfval;
+  set Inst{13-5} = opfVal;
+}
+
+class F3_15<bits<2> opVal, bits<6> op3Val,
+            bits<9> opfVal, string name> : F3 {
+  bits<2> cc;
+  bits<5> rs1;
+  bits<5> rs2;
+
+  set op  = opVal;
+  set op3 = op3Val;
+  set Inst{26-25} = cc;
+  set Inst{18-14} = rs1;
+  set Inst{13-5}  = opfVal;
+  set Inst{4-0}   = rs2;
 }
   
 class F3_16<bits<2> opVal,  bits<6> op3Val,




From lattner at cs.uiuc.edu  Tue Jun  3 21:36:01 2003
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Tue Jun  3 21:36:01 2003
Subject: [llvm-commits] CVS: llvm/lib/Target/TargetData.cpp
Message-ID: <200306040235.VAA24486@apoc.cs.uiuc.edu>


Changes in directory llvm/lib/Target:

TargetData.cpp updated: 1.34 -> 1.35

---
Log message:

No really, you _cannot use_ getelementptr on an unsized type: that makes 
no sense.


---
Diffs of the changes:

Index: llvm/lib/Target/TargetData.cpp
diff -u llvm/lib/Target/TargetData.cpp:1.34 llvm/lib/Target/TargetData.cpp:1.35
--- llvm/lib/Target/TargetData.cpp:1.34	Tue Jun  3 21:10:37 2003
+++ llvm/lib/Target/TargetData.cpp	Tue Jun  3 21:35:35 2003
@@ -193,12 +193,8 @@
       Ty = cast<SequentialType>(Ty)->getElementType();
 
       // Get the array index and the size of each array element.
-      // The size must be a known value, except if arrayIdx is 0.
-      // In particular, don't try to get the type size if the arrayIdx is 0:
-      // 0 index into an unsized type is legal and should be allowed.
       int64_t arrayIdx = cast<ConstantSInt>(Idx[CurIDX])->getValue();
-      Result += arrayIdx == 0? 0
-                             : arrayIdx * (int64_t)getTypeSize(Ty);
+      Result += arrayIdx * (int64_t)getTypeSize(Ty);
     } else {
       const StructType *STy = cast<StructType>(Ty);
       assert(Idx[CurIDX]->getType() == Type::UByteTy && "Illegal struct idx");




From vadve at cs.uiuc.edu  Tue Jun  3 21:40:00 2003
From: vadve at cs.uiuc.edu (Vikram Adve)
Date: Tue Jun  3 21:40:00 2003
Subject: [llvm-commits] CVS: llvm/test/Programs/DiffOutput.sh
Message-ID: <200306040239.VAA02251@trinity.cs.uiuc.edu>


Changes in directory llvm/test/Programs:

DiffOutput.sh updated: 1.9 -> 1.10

---
Log message:

Really don't use something that doesn't work on the Sparcs.


---
Diffs of the changes:

Index: llvm/test/Programs/DiffOutput.sh
diff -u llvm/test/Programs/DiffOutput.sh:1.9 llvm/test/Programs/DiffOutput.sh:1.10
--- llvm/test/Programs/DiffOutput.sh:1.9	Sat May 31 20:49:13 2003
+++ llvm/test/Programs/DiffOutput.sh	Tue Jun  3 21:39:26 2003
@@ -20,7 +20,7 @@
 fi
 
 # Diff the two files.
-$DIFF -u Output/$2.out-nat Output/$2.out-$1 > $DIFFOUTPUT || (
+$DIFF -C 2 Output/$2.out-nat Output/$2.out-$1 > $DIFFOUTPUT || (
   # They are different!
   echo "******************** TEST '$2' FAILED! ********************"
   echo "Execution Context Diff:"




From brukman at cs.uiuc.edu  Tue Jun  3 21:59:01 2003
From: brukman at cs.uiuc.edu (Misha Brukman)
Date: Tue Jun  3 21:59:01 2003
Subject: [llvm-commits] CVS: llvm/lib/Target/Sparc/SparcV9.td
Message-ID: <200306040258.VAA04371@zion.cs.uiuc.edu>


Changes in directory llvm/lib/Target/Sparc:

SparcV9.td updated: 1.13 -> 1.14

---
Log message:

Comment out opcodes currently unused in the Sparc backend.


---
Diffs of the changes:

Index: llvm/lib/Target/Sparc/SparcV9.td
diff -u llvm/lib/Target/Sparc/SparcV9.td:1.13 llvm/lib/Target/Sparc/SparcV9.td:1.14
--- llvm/lib/Target/Sparc/SparcV9.td:1.13	Tue Jun  3 21:26:14 2003
+++ llvm/lib/Target/Sparc/SparcV9.td	Tue Jun  3 21:57:55 2003
@@ -191,9 +191,12 @@
 def FCMPS  : F3_15<2, 0b110101, 0b010100001, "fcmps">;   // fcmps  %fcc, r1, r2
 def FCMPD  : F3_15<2, 0b110101, 0b010100010, "fcmpd">;   // fcmpd  %fcc, r1, r2
 def FCMPQ  : F3_15<2, 0b110101, 0b010100011, "fcmpq">;   // fcmpq  %fcc, r1, r2
+// Currently unused in the Sparc backend
+#if 0
 def FCMPES : F3_15<2, 0b110101, 0b010100101, "fcmpes">;  // fcmpes %fcc, r1, r2
 def FCMPED : F3_15<2, 0b110101, 0b010100110, "fcmped">;  // fcmped %fcc, r1, r2
 def FCMPEQ : F3_15<2, 0b110101, 0b010100111, "fcmpeq">;  // fcmpeq %fcc, r1, r2
+#endif
 
 // Section A.14: Convert floating-point to integer - p161
 def FSTOX : F3_14<2, 0b110100, 0b010000001, "fstox">;   // fstox rs2, rd




From lattner at cs.uiuc.edu  Tue Jun  3 23:38:01 2003
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Tue Jun  3 23:38:01 2003
Subject: [llvm-commits] CVS: llvm/test/Regression/Transforms/InstCombine/or.ll
Message-ID: <200306040437.XAA27036@apoc.cs.uiuc.edu>


Changes in directory llvm/test/Regression/Transforms/InstCombine:

or.ll updated: 1.12 -> 1.13

---
Log message:

Add new test for inverting branches


---
Diffs of the changes:

Index: llvm/test/Regression/Transforms/InstCombine/or.ll
diff -u llvm/test/Regression/Transforms/InstCombine/or.ll:1.12 llvm/test/Regression/Transforms/InstCombine/or.ll:1.13
--- llvm/test/Regression/Transforms/InstCombine/or.ll:1.12	Mon Mar 10 18:10:59 2003
+++ llvm/test/Regression/Transforms/InstCombine/or.ll	Tue Jun  3 23:37:46 2003
@@ -105,3 +105,13 @@
 	%E = or ubyte %C, %D
 	ret ubyte %E
 }
+
+ubyte %test18(bool %c) {
+	%d = xor bool %c, true    ; invert the condition
+	br bool %d, label %True, label %False
+True:
+	ret ubyte 1
+False:
+	ret ubyte 3
+}
+




From lattner at cs.uiuc.edu  Tue Jun  3 23:47:01 2003
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Tue Jun  3 23:47:01 2003
Subject: [llvm-commits] CVS: llvm/lib/Transforms/Scalar/InstructionCombining.cpp
Message-ID: <200306040446.XAA27096@apoc.cs.uiuc.edu>


Changes in directory llvm/lib/Transforms/Scalar:

InstructionCombining.cpp updated: 1.86 -> 1.87

---
Log message:

Implement combination of boolean not with branch


---
Diffs of the changes:

Index: llvm/lib/Transforms/Scalar/InstructionCombining.cpp
diff -u llvm/lib/Transforms/Scalar/InstructionCombining.cpp:1.86 llvm/lib/Transforms/Scalar/InstructionCombining.cpp:1.87
--- llvm/lib/Transforms/Scalar/InstructionCombining.cpp:1.86	Sat May 31 22:35:25 2003
+++ llvm/lib/Transforms/Scalar/InstructionCombining.cpp	Tue Jun  3 23:46:00 2003
@@ -76,6 +76,7 @@
     Instruction *visitPHINode(PHINode &PN);
     Instruction *visitGetElementPtrInst(GetElementPtrInst &GEP);
     Instruction *visitAllocationInst(AllocationInst &AI);
+    Instruction *visitBranchInst(BranchInst &BI);
 
     // visitInstruction - Specify what to return for unhandled instructions...
     Instruction *visitInstruction(Instruction &I) { return 0; }
@@ -1061,6 +1062,19 @@
   return 0;
 }
 
+Instruction *InstCombiner::visitBranchInst(BranchInst &BI) {
+  // Change br (not X), label True, label False to: br X, label False, True
+  if (BI.isConditional() && BinaryOperator::isNot(BI.getCondition())) {
+    BasicBlock *TrueDest = BI.getSuccessor(0);
+    BasicBlock *FalseDest = BI.getSuccessor(1);
+    // Swap Destinations and condition...
+    BI.setCondition(BinaryOperator::getNotArgument(cast<BinaryOperator>(BI.getCondition())));
+    BI.setSuccessor(0, FalseDest);
+    BI.setSuccessor(1, TrueDest);
+    return &BI;
+  }
+  return 0;
+}
 
 
 void InstCombiner::removeFromWorkList(Instruction *I) {




From lattner at cs.uiuc.edu  Tue Jun  3 23:48:01 2003
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Tue Jun  3 23:48:01 2003
Subject: [llvm-commits] CVS: llvm/test/Regression/Transforms/InstCombine/set.ll
Message-ID: <200306040447.XAA27112@apoc.cs.uiuc.edu>


Changes in directory llvm/test/Regression/Transforms/InstCombine:

set.ll updated: 1.6 -> 1.7

---
Log message:

Modernize testcase


---
Diffs of the changes:

Index: llvm/test/Regression/Transforms/InstCombine/set.ll
diff -u llvm/test/Regression/Transforms/InstCombine/set.ll:1.6 llvm/test/Regression/Transforms/InstCombine/set.ll:1.7
--- llvm/test/Regression/Transforms/InstCombine/set.ll:1.6	Sat May 31 22:34:53 2003
+++ llvm/test/Regression/Transforms/InstCombine/set.ll	Tue Jun  3 23:47:40 2003
@@ -8,46 +8,46 @@
 
 %X = uninitialized global int
 
-bool "test1"(int %A) {
+bool %test1(int %A) {
 	%B = seteq int %A, %A
 	%C = seteq int* %X, null   ; Never true
 	%D = and bool %B, %C
 	ret bool %D
 }
 
-bool "test2"(int %A) {
+bool %test2(int %A) {
 	%B = setne int %A, %A
 	%C = setne int* %X, null   ; Never false
 	%D = or bool %B, %C
 	ret bool %D
 }
 
-bool "test3"(int %A) {
+bool %test3(int %A) {
 	%B = setlt int %A, %A
 	ret bool %B
 }
 
-bool "test4"(int %A) {
+bool %test4(int %A) {
 	%B = setgt int %A, %A
 	ret bool %B
 }
 
-bool "test5"(int %A) {
+bool %test5(int %A) {
 	%B = setle int %A, %A
 	ret bool %B
 }
 
-bool "test6"(int %A) {
+bool %test6(int %A) {
 	%B = setge int %A, %A
 	ret bool %B
 }
 
-bool "test7"(uint %A) {
+bool %test7(uint %A) {
 	%B = setge uint %A, 0  ; true
 	ret bool %B
 }
 
-bool "test8"(uint %A) {
+bool %test8(uint %A) {
 	%B = setlt uint %A, 0  ; false
 	ret bool %B
 }




From brukman at cs.uiuc.edu  Tue Jun  3 23:49:00 2003
From: brukman at cs.uiuc.edu (Misha Brukman)
Date: Tue Jun  3 23:49:00 2003
Subject: [llvm-commits] CVS: llvm/lib/Target/Sparc/SparcV9_F4.td SparcV9.td
Message-ID: <200306040448.XAA06181@zion.cs.uiuc.edu>


Changes in directory llvm/lib/Target/Sparc:

SparcV9_F4.td updated: 1.3 -> 1.4
SparcV9.td updated: 1.14 -> 1.15

---
Log message:

Added the 4.7 instruction class and all the FMOVcc instructions in them.


---
Diffs of the changes:

Index: llvm/lib/Target/Sparc/SparcV9_F4.td
diff -u llvm/lib/Target/Sparc/SparcV9_F4.td:1.3 llvm/lib/Target/Sparc/SparcV9_F4.td:1.4
--- llvm/lib/Target/Sparc/SparcV9_F4.td:1.3	Mon Jun  2 20:13:53 2003
+++ llvm/lib/Target/Sparc/SparcV9_F4.td	Tue Jun  3 23:48:31 2003
@@ -115,4 +115,21 @@
   set Inst{9-5} = opf_lowVal;
 }
 
-// FIXME: F4 classes 7-9
+class F4_7<bits<2> opVal, bits<6> op3Val, bits<4> condVal,
+           bits<6> opf_lowVal, string name> : F4_cond {
+  bits<3> cc;
+  bits<5> rs2;
+  bits<5> rd;
+
+  set op   = opVal;
+  set op3  = op3Val;
+  set cond = condVal;
+  set Name = name;
+  set Inst{29-25} = rd;
+  set Inst{18}    = 0;
+  set Inst{13-11} = cc;
+  set Inst{10-5}  = opf_lowVal;
+  set Inst{4-0}   = rs2;
+}
+
+// FIXME: F4 classes 8-9


Index: llvm/lib/Target/Sparc/SparcV9.td
diff -u llvm/lib/Target/Sparc/SparcV9.td:1.14 llvm/lib/Target/Sparc/SparcV9.td:1.15
--- llvm/lib/Target/Sparc/SparcV9.td:1.14	Tue Jun  3 21:57:55 2003
+++ llvm/lib/Target/Sparc/SparcV9.td	Tue Jun  3 23:48:31 2003
@@ -248,8 +248,11 @@
 def FSQRTD : F3_14<2, 0b110100, 0b000101010, "fsqrts">;  // fsqrts r, r
 def FSQRTQ : F3_14<2, 0b110100, 0b000101011, "fsqrts">;  // fsqrts r, r
 
-// FIXME: A.20: Flush Instruction Memory - p167
-// FIXME: A.21: Flush Register Windows - p169
+// A.20: Flush Instruction Memory - p167
+// Not currently used
+
+// A.21: Flush Register Windows - p169
+// Not currently used
 
 // A.22: Illegal instruction Trap - p170
 // Not currently used
@@ -338,43 +341,116 @@
 // Not currently used in the Sparc backend
 
 // Section A.33: Move Floating-Point Register on Condition (FMOVcc)
-#if 0
+// ======================= Single Floating Point ======================
 // For integer condition codes
-def FMOVA   : F4_7<2, 0b110101, 0b1000, "fmova">;        // fmova r, r
-def FMOVN   : F4_7<2, 0b110101, 0b0000, "fmovn">;        // fmovn r, r
-def FMOVNE  : F4_7<2, 0b110101, 0b1001, "fmovne">;       // fmovne r, r
-def FMOVE   : F4_7<2, 0b110101, 0b0000, "fmove">;        // fmove r, r
-def FMOVG   : F4_7<2, 0b110101, 0b1010, "fmovg">;        // fmovg r, r
-def FMOVLE  : F4_7<2, 0b110101, 0b0000, "fmovle">;       // fmovle r, r
-def FMOVGE  : F4_7<2, 0b110101, 0b1011, "fmovge">;       // fmovge r, r
-def FMOVL   : F4_7<2, 0b110101, 0b0011, "fmovl">;        // fmovl r, r
-def FMOVGU  : F4_7<2, 0b110101, 0b1100, "fmovgu">;       // fmovgu r, r
-def FMOVLEU : F4_7<2, 0b110101, 0b0100, "fmovleu">;      // fmovleu r, r
-def FMOVCC  : F4_7<2, 0b110101, 0b1101, "fmovcc">;       // fmovcc r, r
-def FMOVCS  : F4_7<2, 0b110101, 0b0101, "fmovcs">;       // fmovcs r, r
-def FMOVPOS : F4_7<2, 0b110101, 0b1110, "fmovpos">;      // fmovpos r, r
-def FMOVNEG : F4_7<2, 0b110101, 0b0110, "fmovneg">;      // fmovneg r, r
-def FMOVVC  : F4_7<2, 0b110101, 0b1111, "fmovvc">;       // fmovvc r, r
-def FMOVVS  : F4_7<2, 0b110101, 0b0111, "fmovvs">;       // fmovvs r, r
+def FMOVSA   : F4_7<2, 0b110101, 0b1000, 0b000001, "fmovsa">;   // fmovsa   cc, r, r
+def FMOVSN   : F4_7<2, 0b110101, 0b0000, 0b000001, "fmovsn">;   // fmovsn   cc, r, r
+def FMOVSNE  : F4_7<2, 0b110101, 0b1001, 0b000001, "fmovsne">;  // fmovsne  cc, r, r
+def FMOVSE   : F4_7<2, 0b110101, 0b0000, 0b000001, "fmovse">;   // fmovse   cc, r, r
+def FMOVSG   : F4_7<2, 0b110101, 0b1010, 0b000001, "fmovsg">;   // fmovsg   cc, r, r
+def FMOVSLE  : F4_7<2, 0b110101, 0b0000, 0b000001, "fmovsle">;  // fmovsle  cc, r, r
+def FMOVSGE  : F4_7<2, 0b110101, 0b1011, 0b000001, "fmovsge">;  // fmovsge  cc, r, r
+def FMOVSL   : F4_7<2, 0b110101, 0b0011, 0b000001, "fmovsl">;   // fmovsl   cc, r, r
+def FMOVSGU  : F4_7<2, 0b110101, 0b1100, 0b000001, "fmovsgu">;  // fmovsgu  cc, r, r
+def FMOVSLEU : F4_7<2, 0b110101, 0b0100, 0b000001, "fmovsleu">; // fmovsleu cc, r, r
+def FMOVSCC  : F4_7<2, 0b110101, 0b1101, 0b000001, "fmovscc">;  // fmovscc  cc, r, r
+def FMOVSCS  : F4_7<2, 0b110101, 0b0101, 0b000001, "fmovscs">;  // fmovscs  cc, r, r
+def FMOVSPOS : F4_7<2, 0b110101, 0b1110, 0b000001, "fmovspos">; // fmovspos cc, r, r
+def FMOVSNEG : F4_7<2, 0b110101, 0b0110, 0b000001, "fmovsneg">; // fmovsneg cc, r, r
+def FMOVSVC  : F4_7<2, 0b110101, 0b1111, 0b000001, "fmovsvc">;  // fmovsvc  cc, r, r
+def FMOVSVS  : F4_7<2, 0b110101, 0b0111, 0b000001, "fmovsvs">;  // fmovsvs  cc, r, r
 
 // For floating-point condition codes
-def FMOVFA   : F4_7<2, 0b110101, 0b0100, "fmovfa">;      // fmovfa r, r
-def FMOVFN   : F4_7<2, 0b110101, 0b0000, "fmovfn">;      // fmovfa r, r
-def FMOVFU   : F4_7<2, 0b110101, 0b0111, "fmovfu">;      // fmovfu r, r
-def FMOVFG   : F4_7<2, 0b110101, 0b0110, "fmovfg">;      // fmovfg r, r
-def FMOVFUG  : F4_7<2, 0b110101, 0b0101, "fmovfug">;     // fmovfug r, r
-def FMOVFL   : F4_7<2, 0b110101, 0b0100, "fmovfl">;      // fmovfl r, r
-def FMOVFUL  : F4_7<2, 0b110101, 0b0011, "fmovful">;     // fmovful r, r
-def FMOVFLG  : F4_7<2, 0b110101, 0b0010, "fmovflg">;     // fmovflg r, r
-def FMOVFNE  : F4_7<2, 0b110101, 0b0001, "fmovfne">;     // fmovfne r, r
-def FMOVFE   : F4_7<2, 0b110101, 0b1001, "fmovfe">;      // fmovfe r, r
-def FMOVFUE  : F4_7<2, 0b110101, 0b1010, "fmovfue">;     // fmovfue r, r
-def FMOVGE   : F4_7<2, 0b110101, 0b1011, "fmovge">;      // fmovge r, r
-def FMOVFUGE : F4_7<2, 0b110101, 0b1100, "fmovfuge">;    // fmovfuge r, r
-def FMOVFLE  : F4_7<2, 0b110101, 0b1101, "fmovfle">;     // fmovfle r, r
-def FMOVFULE : F4_7<2, 0b110101, 0b1110, "fmovfule">;    // fmovfule r, r
-def FMOVFO   : F4_7<2, 0b110101, 0b1111, "fmovfo">;      // fmovfo r, r
-#endif
+def FMOVSFA   : F4_7<2, 0b110101, 0b0100, 0b000001, "fmovsfa">;  // fmovsfa   cc,r,r
+def FMOVSFN   : F4_7<2, 0b110101, 0b0000, 0b000001, "fmovsfn">;  // fmovsfa   cc,r,r
+def FMOVSFU   : F4_7<2, 0b110101, 0b0111, 0b000001, "fmovsfu">;  // fmovsfu   cc,r,r
+def FMOVSFG   : F4_7<2, 0b110101, 0b0110, 0b000001, "fmovsfg">;  // fmovsfg   cc,r,r
+def FMOVSFUG  : F4_7<2, 0b110101, 0b0101, 0b000001, "fmovsfug">; // fmovsfug  cc,r,r
+def FMOVSFL   : F4_7<2, 0b110101, 0b0100, 0b000001, "fmovsfl">;  // fmovsfl   cc,r,r
+def FMOVSFUL  : F4_7<2, 0b110101, 0b0011, 0b000001, "fmovsful">; // fmovsful  cc,r,r
+def FMOVSFLG  : F4_7<2, 0b110101, 0b0010, 0b000001, "fmovsflg">; // fmovsflg  cc,r,r
+def FMOVSFNE  : F4_7<2, 0b110101, 0b0001, 0b000001, "fmovsfne">; // fmovsfne  cc,r,r
+def FMOVSFE   : F4_7<2, 0b110101, 0b1001, 0b000001, "fmovsfe">;  // fmovsfe   cc,r,r
+def FMOVSFUE  : F4_7<2, 0b110101, 0b1010, 0b000001, "fmovsfue">; // fmovsfue  cc,r,r
+def FMOVSFGE  : F4_7<2, 0b110101, 0b1011, 0b000001, "fmovsge">;  // fmovsge   cc,r,r
+def FMOVSFUGE : F4_7<2, 0b110101, 0b1100, 0b000001, "fmovsfuge">;// fmovsfuge cc,r,r
+def FMOVSFLE  : F4_7<2, 0b110101, 0b1101, 0b000001, "fmovsfle">; // fmovsfle  cc,r,r
+def FMOVSFULE : F4_7<2, 0b110101, 0b1110, 0b000001, "fmovsfule">;// fmovsfule cc,r,r
+def FMOVSFO   : F4_7<2, 0b110101, 0b1111, 0b000001, "fmovsfo">;  // fmovsfo   cc,r,r
+
+// ======================= Double Floating Point ======================
+// For integer condition codes
+def FMOVDA   : F4_7<2, 0b110101, 0b1000, 0b000010, "fmovda">;   // fmovda   cc, r, r
+def FMOVDN   : F4_7<2, 0b110101, 0b0000, 0b000010, "fmovdn">;   // fmovdn   cc, r, r
+def FMOVDNE  : F4_7<2, 0b110101, 0b1001, 0b000010, "fmovdne">;  // fmovdne  cc, r, r
+def FMOVDE   : F4_7<2, 0b110101, 0b0000, 0b000010, "fmovde">;   // fmovde   cc, r, r
+def FMOVDG   : F4_7<2, 0b110101, 0b1010, 0b000010, "fmovdg">;   // fmovdg   cc, r, r
+def FMOVDLE  : F4_7<2, 0b110101, 0b0000, 0b000010, "fmovdle">;  // fmovdle  cc, r, r
+def FMOVDGE  : F4_7<2, 0b110101, 0b1011, 0b000010, "fmovdge">;  // fmovdge  cc, r, r
+def FMOVDL   : F4_7<2, 0b110101, 0b0011, 0b000010, "fmovdl">;   // fmovdl   cc, r, r
+def FMOVDGU  : F4_7<2, 0b110101, 0b1100, 0b000010, "fmovdgu">;  // fmovdgu  cc, r, r
+def FMOVDLEU : F4_7<2, 0b110101, 0b0100, 0b000010, "fmovdleu">; // fmovdleu cc, r, r
+def FMOVDCC  : F4_7<2, 0b110101, 0b1101, 0b000010, "fmovdcc">;  // fmovdcc  cc, r, r
+def FMOVDCS  : F4_7<2, 0b110101, 0b0101, 0b000010, "fmovdcs">;  // fmovdcs  cc, r, r
+def FMOVDPOS : F4_7<2, 0b110101, 0b1110, 0b000010, "fmovdpos">; // fmovdpos cc, r, r
+def FMOVDNEG : F4_7<2, 0b110101, 0b0110, 0b000010, "fmovdneg">; // fmovdneg cc, r, r
+def FMOVDVC  : F4_7<2, 0b110101, 0b1111, 0b000010, "fmovdvc">;  // fmovdvc  cc, r, r
+def FMOVDVS  : F4_7<2, 0b110101, 0b0111, 0b000010, "fmovdvs">;  // fmovdvs  cc, r, r
+
+// For floating-point condition codes
+def FMOVDFA   : F4_7<2, 0b110101, 0b0100, 0b000010, "fmovdfa">;  // fmovdfa   cc,r,r
+def FMOVDFN   : F4_7<2, 0b110101, 0b0000, 0b000010, "fmovdfn">;  // fmovdfa   cc,r,r
+def FMOVDFU   : F4_7<2, 0b110101, 0b0111, 0b000010, "fmovdfu">;  // fmovdfu   cc,r,r
+def FMOVDFG   : F4_7<2, 0b110101, 0b0110, 0b000010, "fmovdfg">;  // fmovdfg   cc,r,r
+def FMOVDFUG  : F4_7<2, 0b110101, 0b0101, 0b000010, "fmovdfug">; // fmovdfug  cc,r,r
+def FMOVDFL   : F4_7<2, 0b110101, 0b0100, 0b000010, "fmovdfl">;  // fmovdfl   cc,r,r
+def FMOVDFUL  : F4_7<2, 0b110101, 0b0011, 0b000010, "fmovdful">; // fmovdful  cc,r,r
+def FMOVDFLG  : F4_7<2, 0b110101, 0b0010, 0b000010, "fmovdflg">; // fmovdflg  cc,r,r
+def FMOVDFNE  : F4_7<2, 0b110101, 0b0001, 0b000010, "fmovdfne">; // fmovdfne  cc,r,r
+def FMOVDFE   : F4_7<2, 0b110101, 0b1001, 0b000010, "fmovdfe">;  // fmovdfe   cc,r,r
+def FMOVDFUE  : F4_7<2, 0b110101, 0b1010, 0b000010, "fmovdfue">; // fmovdfue  cc,r,r
+def FMOVDFGE  : F4_7<2, 0b110101, 0b1011, 0b000010, "fmovdge">;  // fmovdge   cc,r,r
+def FMOVDFUGE : F4_7<2, 0b110101, 0b1100, 0b000010, "fmovdfuge">;// fmovdfuge cc,r,r
+def FMOVDFLE  : F4_7<2, 0b110101, 0b1101, 0b000010, "fmovdfle">; // fmovdfle  cc,r,r
+def FMOVDFULE : F4_7<2, 0b110101, 0b1110, 0b000010, "fmovdfule">;// fmovdfule cc,r,r
+def FMOVDFO   : F4_7<2, 0b110101, 0b1111, 0b000010, "fmovdfo">;  // fmovdfo   cc,r,r
+
+// ======================= Quad Floating Point ======================
+// For integer condition codes
+def FMOVQA   : F4_7<2, 0b110101, 0b1000, 0b000011, "fmovqa">;   // fmovqa   cc, r, r
+def FMOVQN   : F4_7<2, 0b110101, 0b0000, 0b000011, "fmovqn">;   // fmovqn   cc, r, r
+def FMOVQNE  : F4_7<2, 0b110101, 0b1001, 0b000011, "fmovqne">;  // fmovqne  cc, r, r
+def FMOVQE   : F4_7<2, 0b110101, 0b0000, 0b000011, "fmovqe">;   // fmovqe   cc, r, r
+def FMOVQG   : F4_7<2, 0b110101, 0b1010, 0b000011, "fmovqg">;   // fmovqg   cc, r, r
+def FMOVQLE  : F4_7<2, 0b110101, 0b0000, 0b000011, "fmovqle">;  // fmovqle  cc, r, r
+def FMOVQGE  : F4_7<2, 0b110101, 0b1011, 0b000011, "fmovqge">;  // fmovqge  cc, r, r
+def FMOVQL   : F4_7<2, 0b110101, 0b0011, 0b000011, "fmovql">;   // fmovql   cc, r, r
+def FMOVQGU  : F4_7<2, 0b110101, 0b1100, 0b000011, "fmovqgu">;  // fmovqgu  cc, r, r
+def FMOVQLEU : F4_7<2, 0b110101, 0b0100, 0b000011, "fmovqleu">; // fmovqleu cc, r, r
+def FMOVQCC  : F4_7<2, 0b110101, 0b1101, 0b000011, "fmovqcc">;  // fmovqcc  cc, r, r
+def FMOVQCS  : F4_7<2, 0b110101, 0b0101, 0b000011, "fmovqcs">;  // fmovqcs  cc, r, r
+def FMOVQPOS : F4_7<2, 0b110101, 0b1110, 0b000011, "fmovqpos">; // fmovqpos cc, r, r
+def FMOVQNEG : F4_7<2, 0b110101, 0b0110, 0b000011, "fmovqneg">; // fmovqneg cc, r, r
+def FMOVQVC  : F4_7<2, 0b110101, 0b1111, 0b000011, "fmovqvc">;  // fmovqvc  cc, r, r
+def FMOVQVS  : F4_7<2, 0b110101, 0b0111, 0b000011, "fmovqvs">;  // fmovqvs  cc, r, r
+
+// For floating-point condition codes
+def FMOVQFA   : F4_7<2, 0b110101, 0b0100, 0b000011, "fmovqfa">;  // fmovqfa   cc,r,r
+def FMOVQFN   : F4_7<2, 0b110101, 0b0000, 0b000011, "fmovqfn">;  // fmovqfa   cc,r,r
+def FMOVQFU   : F4_7<2, 0b110101, 0b0111, 0b000011, "fmovqfu">;  // fmovqfu   cc,r,r
+def FMOVQFG   : F4_7<2, 0b110101, 0b0110, 0b000011, "fmovqfg">;  // fmovqfg   cc,r,r
+def FMOVQFUG  : F4_7<2, 0b110101, 0b0101, 0b000011, "fmovqfug">; // fmovqfug  cc,r,r
+def FMOVQFL   : F4_7<2, 0b110101, 0b0100, 0b000011, "fmovqfl">;  // fmovqfl   cc,r,r
+def FMOVQFUL  : F4_7<2, 0b110101, 0b0011, 0b000011, "fmovqful">; // fmovqful  cc,r,r
+def FMOVQFLG  : F4_7<2, 0b110101, 0b0010, 0b000011, "fmovqflg">; // fmovqflg  cc,r,r
+def FMOVQFNE  : F4_7<2, 0b110101, 0b0001, 0b000011, "fmovqfne">; // fmovqfne  cc,r,r
+def FMOVQFE   : F4_7<2, 0b110101, 0b1001, 0b000011, "fmovqfe">;  // fmovqfe   cc,r,r
+def FMOVQFUE  : F4_7<2, 0b110101, 0b1010, 0b000011, "fmovqfue">; // fmovqfue  cc,r,r
+def FMOVQFGE  : F4_7<2, 0b110101, 0b1011, 0b000011, "fmovqge">;  // fmovqge   cc,r,r
+def FMOVQFUGE : F4_7<2, 0b110101, 0b1100, 0b000011, "fmovqfuge">;// fmovqfuge cc,r,r
+def FMOVQFLE  : F4_7<2, 0b110101, 0b1101, 0b000011, "fmovqfle">; // fmovqfle  cc,r,r
+def FMOVQFULE : F4_7<2, 0b110101, 0b1110, 0b000011, "fmovqfule">;// fmovqfule cc,r,r
+def FMOVQFO   : F4_7<2, 0b110101, 0b1111, 0b000011, "fmovqfo">;  // fmovqfo   cc,r,r
 
 // Section A.34: Move FP Register on Integer Register condition (FMOVr) - p192
 def FMOVRSZ   : F4_6<2, 0b110101, 0b001, 0b00101, "fmovrsz">;  //fmovsrz r,r,rd




From brukman at cs.uiuc.edu  Tue Jun  3 23:55:01 2003
From: brukman at cs.uiuc.edu (Misha Brukman)
Date: Tue Jun  3 23:55:01 2003
Subject: [llvm-commits] CVS: llvm/lib/CodeGen/InstrSelection/InstrSelectionSupport.cpp
Message-ID: <200306040454.XAA06449@zion.cs.uiuc.edu>


Changes in directory llvm/lib/CodeGen/InstrSelection:

InstrSelectionSupport.cpp updated: 1.49 -> 1.50

---
Log message:

I have finally seen the light. The code to change the opcode must live higher in
the loop, and in both cases. In the first case, it is a VReg that is a constant
so it may be actually converted to a constant. In the second case, it is already
a constant, but then if it doesn't change its type (e.g. to become a register
and have the value loaded from memory if it is too large to live in its
instruction field), we must change the opcode BEFORE the 'continue', otherwise
we miss the opportunity.


---
Diffs of the changes:

Index: llvm/lib/CodeGen/InstrSelection/InstrSelectionSupport.cpp
diff -u llvm/lib/CodeGen/InstrSelection/InstrSelectionSupport.cpp:1.49 llvm/lib/CodeGen/InstrSelection/InstrSelectionSupport.cpp:1.50
--- llvm/lib/CodeGen/InstrSelection/InstrSelectionSupport.cpp:1.49	Mon Jun  2 22:18:20 2003
+++ llvm/lib/CodeGen/InstrSelection/InstrSelectionSupport.cpp	Tue Jun  3 23:54:06 2003
@@ -186,6 +186,12 @@
                                       immedValue);
             if (opType == MachineOperand::MO_VirtualRegister)
               constantThatMustBeLoaded = true;
+            else {
+              // The optype has changed from being a register to an immediate
+              // This means we need to change the opcode, e.g. ADDr -> ADDi
+              unsigned newOpcode = convertOpcodeFromRegToImm(opCode);
+              minstr->setOpcode(newOpcode);
+            }
           }
         }
       else
@@ -203,6 +209,13 @@
                                     opCode, target, (immedPos == (int)op), 
                                     machineRegNum, immedValue);
 
+          if (opType == MachineOperand::MO_SignExtendedImmed) {
+            // The optype is an immediate value
+            // This means we need to change the opcode, e.g. ADDr -> ADDi
+            unsigned newOpcode = convertOpcodeFromRegToImm(opCode);
+            minstr->setOpcode(newOpcode);
+          }
+
           if (opType == mop.getType()) 
             continue;           // no change: this is the most common case
 
@@ -220,10 +233,6 @@
       else if (opType == MachineOperand::MO_SignExtendedImmed ||
                opType == MachineOperand::MO_UnextendedImmed) {
         minstr->SetMachineOperandConst(op, opType, immedValue);
-        // The optype has changed from being a register to an immediate
-        // This means we need to change the opcode, e.g. ADDr -> ADDi
-        unsigned newOpcode = convertOpcodeFromRegToImm(opCode);
-        minstr->setOpcode(newOpcode);
       } else if (constantThatMustBeLoaded ||
                (opValue && isa<GlobalValue>(opValue)))
         { // opValue is a constant that must be explicitly loaded into a reg




From lattner at cs.uiuc.edu  Wed Jun  4 00:09:03 2003
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Wed Jun  4 00:09:03 2003
Subject: [llvm-commits] CVS: llvm/include/llvm/iTerminators.h
Message-ID: <200306040508.AAA27857@apoc.cs.uiuc.edu>


Changes in directory llvm/include/llvm:

iTerminators.h updated: 1.25 -> 1.26

---
Log message:

Add new setCondition member


---
Diffs of the changes:

Index: llvm/include/llvm/iTerminators.h
diff -u llvm/include/llvm/iTerminators.h:1.25 llvm/include/llvm/iTerminators.h:1.26
--- llvm/include/llvm/iTerminators.h:1.25	Mon Feb 24 14:48:28 2003
+++ llvm/include/llvm/iTerminators.h	Wed Jun  4 00:08:31 2003
@@ -78,11 +78,13 @@
   inline bool isUnconditional() const { return Operands.size() == 1; }
   inline bool isConditional()   const { return Operands.size() == 3; }
 
-  inline const Value *getCondition() const {
-    return isUnconditional() ? 0 : Operands[2].get();
+  inline Value *getCondition() const {
+    return isUnconditional() ? 0 : (Value*)Operands[2].get();
   }
-  Value *getCondition() {
-    return isUnconditional() ? 0 : Operands[2].get();
+
+  void setCondition(Value *V) {
+    assert(isConditional() && "Cannot set condition of unconditional branch!");
+    setOperand(2, V);
   }
 
   // setUnconditionalDest - Change the current branch to an unconditional branch




From lattner at cs.uiuc.edu  Wed Jun  4 00:11:00 2003
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Wed Jun  4 00:11:00 2003
Subject: [llvm-commits] CVS: llvm/lib/Transforms/Scalar/InstructionCombining.cpp
Message-ID: <200306040510.AAA27872@apoc.cs.uiuc.edu>


Changes in directory llvm/lib/Transforms/Scalar:

InstructionCombining.cpp updated: 1.87 -> 1.88

---
Log message:

Clean up previous code.
Add new combination to turn seteq X, 0 -> not(cast X to bool)


---
Diffs of the changes:

Index: llvm/lib/Transforms/Scalar/InstructionCombining.cpp
diff -u llvm/lib/Transforms/Scalar/InstructionCombining.cpp:1.87 llvm/lib/Transforms/Scalar/InstructionCombining.cpp:1.88
--- llvm/lib/Transforms/Scalar/InstructionCombining.cpp:1.87	Tue Jun  3 23:46:00 2003
+++ llvm/lib/Transforms/Scalar/InstructionCombining.cpp	Wed Jun  4 00:10:11 2003
@@ -683,8 +683,16 @@
   // integers at the end of their ranges...
   //
   if (ConstantInt *CI = dyn_cast<ConstantInt>(Op1)) {
-    if (CI->isNullValue() && I.getOpcode() == Instruction::SetNE)
-      return new CastInst(Op0, Type::BoolTy, I.getName());
+    if (CI->isNullValue()) {
+      if (I.getOpcode() == Instruction::SetNE)
+        return new CastInst(Op0, Type::BoolTy, I.getName());
+      else if (I.getOpcode() == Instruction::SetEQ) {
+        // seteq X, 0 -> not (cast X to bool)
+        Instruction *Val = new CastInst(Op0, Type::BoolTy, I.getName()+".not");
+        InsertNewInstBefore(Val, I);
+        return BinaryOperator::createNot(Val, I.getName());
+      }
+    }
 
     // Check to see if we are comparing against the minimum or maximum value...
     if (CI->isMinValue()) {
@@ -1064,15 +1072,16 @@
 
 Instruction *InstCombiner::visitBranchInst(BranchInst &BI) {
   // Change br (not X), label True, label False to: br X, label False, True
-  if (BI.isConditional() && BinaryOperator::isNot(BI.getCondition())) {
-    BasicBlock *TrueDest = BI.getSuccessor(0);
-    BasicBlock *FalseDest = BI.getSuccessor(1);
-    // Swap Destinations and condition...
-    BI.setCondition(BinaryOperator::getNotArgument(cast<BinaryOperator>(BI.getCondition())));
-    BI.setSuccessor(0, FalseDest);
-    BI.setSuccessor(1, TrueDest);
-    return &BI;
-  }
+  if (BI.isConditional())
+    if (Value *V = dyn_castNotVal(BI.getCondition())) {
+      BasicBlock *TrueDest = BI.getSuccessor(0);
+      BasicBlock *FalseDest = BI.getSuccessor(1);
+      // Swap Destinations and condition...
+      BI.setCondition(V);
+      BI.setSuccessor(0, FalseDest);
+      BI.setSuccessor(1, TrueDest);
+      return &BI;
+    }
   return 0;
 }
 




From kowshik at cs.uiuc.edu  Wed Jun  4 03:01:01 2003
From: kowshik at cs.uiuc.edu (Sumant Kowshik)
Date: Wed Jun  4 03:01:01 2003
Subject: [llvm-commits] CVS: llvm/include/Support/EquivalenceClasses.h
Message-ID: <200306040800.DAA28165@apoc.cs.uiuc.edu>


Changes in directory llvm/include/Support:

EquivalenceClasses.h updated: 1.1 -> 1.2

---
Log message:

Made changes suggested by Chris; Renamed 'union' function to unionSetsWith

---
Diffs of the changes:

Index: llvm/include/Support/EquivalenceClasses.h
diff -u llvm/include/Support/EquivalenceClasses.h:1.1 llvm/include/Support/EquivalenceClasses.h:1.2
--- llvm/include/Support/EquivalenceClasses.h:1.1	Thu May 29 17:44:25 2003
+++ llvm/include/Support/EquivalenceClasses.h	Wed Jun  4 03:00:05 2003
@@ -12,23 +12,19 @@
 #define LLVM_SUPPORT_EQUIVALENCE_CLASSES_H
 
 #include <map>
-#include <set>
 #include <vector>
-using std::map;
-using std::set;
-using std::vector;
 
 template <class ElemTy>
 class EquivalenceClasses {
   // Maps each element to the element that is the leader of its 
   // equivalence class.
-  map<ElemTy, ElemTy> Elem2ECLeaderMap;
+  std::map<ElemTy, ElemTy> Elem2ECLeaderMap;
   
   // Make Element2 the leader of the union of classes Element1 and Element2
   // Element1 and Element2 are presumed to be leaders of their respective
   // equivalence classes.
   void attach(ElemTy Element1, ElemTy Element2) {
-    for (typename map<ElemTy, ElemTy>::iterator ElemI = 
+    for (typename std::map<ElemTy, ElemTy>::iterator ElemI = 
 	   Elem2ECLeaderMap.begin(), ElemE = Elem2ECLeaderMap.end(); 
 	 ElemI != ElemE; ++ElemI) {
       if (ElemI->second == Element1)
@@ -53,7 +49,7 @@
   /// Attach the set with Element1 to the set with Element2 adding Element1 and
   /// Element2 to the set of equivalence classes if they are not there already.
   /// Implication: Make Element1 the element in the smaller set.
-  void unionElements(ElemTy Element1, ElemTy Element2) {
+  void unionSetsWith(ElemTy Element1, ElemTy Element2) {
     // If either Element1 or Element2 does not already exist, include it
     if (Elem2ECLeaderMap.find(Element1) == Elem2ECLeaderMap.end())
       Elem2ECLeaderMap[Element1] = Element1;
@@ -65,15 +61,15 @@
   
   // Returns a vector containing all the elements in the equivalent class
   // including Element1
-  vector<ElemTy> getEqClass(ElemTy Element1) {
-    vector<ElemTy> EqClass;
+  std::vector<ElemTy> getEqClass(ElemTy Element1) {
+    std::vector<ElemTy> EqClass;
     
     if (Elem2ECLeaderMap.find(EqClass) == Elem2ECLeaderMap.end())
       return EqClass;
     
     ElemTy classLeader = Elem2ECLeaderMap[Element1];
 
-    for (typename map<ElemTy, ElemTy>::iterator ElemI = 
+    for (typename std::map<ElemTy, ElemTy>::iterator ElemI = 
 	   Elem2ECLeaderMap.begin(), ElemE = Elem2ECLeaderMap.end(); 
 	 ElemI != ElemE; ++ElemI) {
       if (ElemI->second == classLeader)
@@ -84,7 +80,7 @@
     
   }
 
-  map<ElemTy, ElemTy> getLeaderMap() {
+  std::map<ElemTy, ElemTy>& getLeaderMap() {
     return Elem2ECLeaderMap ;
   }
   




From kowshik at cs.uiuc.edu  Wed Jun  4 03:02:00 2003
From: kowshik at cs.uiuc.edu (Sumant Kowshik)
Date: Wed Jun  4 03:02:00 2003
Subject: [llvm-commits] CVS: llvm/include/llvm/Transforms/PoolAllocate.h
Message-ID: <200306040801.DAA28178@apoc.cs.uiuc.edu>


Changes in directory llvm/include/llvm/Transforms:

PoolAllocate.h updated: 1.2 -> 1.3

---
Log message:

Made changes suggested by Chris

---
Diffs of the changes:

Index: llvm/include/llvm/Transforms/PoolAllocate.h
diff -u llvm/include/llvm/Transforms/PoolAllocate.h:1.2 llvm/include/llvm/Transforms/PoolAllocate.h:1.3
--- llvm/include/llvm/Transforms/PoolAllocate.h:1.2	Thu May 29 17:43:46 2003
+++ llvm/include/llvm/Transforms/PoolAllocate.h	Wed Jun  4 03:01:13 2003
@@ -90,14 +90,14 @@
   EquivalenceClasses<Function *> FuncECs;
 
   // Map from an Indirect CallInst to the set of Functions that it can point to
-  map<CallInst *, vector<Function *> > CallInstTargets;
+  std::multimap<CallInst *, Function *> CallInstTargets;
 
   // This maps an equivalence class to the last pool argument number for that 
   // class. This is used because the pool arguments for all functions within
   // an equivalence class is passed to all the functions in that class.
   // If an equivalence class does not require pool arguments, it is not
   // on this map.
-  map<Function *, int> EqClass2LastPoolArg;
+  std::map<Function *, int> EqClass2LastPoolArg;
 
  public:
   bool run(Module &M);




From kowshik at cs.uiuc.edu  Wed Jun  4 03:05:01 2003
From: kowshik at cs.uiuc.edu (Sumant Kowshik)
Date: Wed Jun  4 03:05:01 2003
Subject: [llvm-commits] CVS: llvm/lib/Transforms/IPO/PoolAllocate.cpp
Message-ID: <200306040804.DAA28218@apoc.cs.uiuc.edu>


Changes in directory llvm/lib/Transforms/IPO:

PoolAllocate.cpp updated: 1.6 -> 1.7

---
Log message:

Made changes suggested by Chris

---
Diffs of the changes:

Index: llvm/lib/Transforms/IPO/PoolAllocate.cpp
diff -u llvm/lib/Transforms/IPO/PoolAllocate.cpp:1.6 llvm/lib/Transforms/IPO/PoolAllocate.cpp:1.7
--- llvm/lib/Transforms/IPO/PoolAllocate.cpp:1.6	Thu May 29 17:42:44 2003
+++ llvm/lib/Transforms/IPO/PoolAllocate.cpp	Wed Jun  4 03:03:57 2003
@@ -17,16 +17,25 @@
 #include "llvm/Support/InstVisitor.h"
 #include "Support/Statistic.h"
 #include "Support/VectorExtras.h"
-
+using std::vector;
+using std::map;
+using std::multimap;
 using namespace PA;
 
 namespace {
   const Type *VoidPtrTy = PointerType::get(Type::SByteTy);
-  // The type to allocate for a pool descriptor: { sbyte*, uint }
-  const Type *PoolDescType =
-    StructType::get(make_vector<const Type*>(VoidPtrTy, Type::UIntTy, 0));
-  const PointerType *PoolDescPtr = PointerType::get(PoolDescType);
 
+  // The type to allocate for a pool descriptor: { sbyte*, uint, uint }
+  // void *Data (the data)
+  // unsigned NodeSize  (size of an allocated node)
+  // unsigned FreeablePool (are slabs in the pool freeable upon calls to 
+  //                        poolfree?)
+  const Type *PoolDescType = 
+  StructType::get(make_vector<const Type*>(VoidPtrTy, Type::UIntTy, 
+					   Type::UIntTy, 0));
+  
+  const PointerType *PoolDescPtr = PointerType::get(PoolDescType);
+  
   RegisterOpt<PoolAllocate>
   X("poolalloc", "Pool allocate disjoint data structures");
 }
@@ -40,7 +49,7 @@
 // Prints out the functions mapped to the leader of the equivalence class they
 // belong to.
 void PoolAllocate::printFuncECs() {
-  map<Function*, Function*> leaderMap = FuncECs.getLeaderMap();
+  map<Function*, Function*> &leaderMap = FuncECs.getLeaderMap();
   std::cerr << "Indirect Function Map \n";
   for (map<Function*, Function*>::iterator LI = leaderMap.begin(),
 	 LE = leaderMap.end(); LI != LE; ++LI) {
@@ -73,23 +82,28 @@
 	   CSE = callSites.end(); CSI != CSE ; ++CSI) {
       if (CSI->isIndirectCall()) {
 	DSNode *DSN = CSI->getCalleeNode();
+	if (DSN->NodeType == DSNode::Incomplete) 
+	  std::cerr << "Incomplete node " << CSI->getCallInst();
 	// assert(DSN->NodeType == DSNode::GlobalNode);
-	std::vector<GlobalValue*> Callees = DSN->getGlobals();
+	std::vector<GlobalValue*> &Callees = DSN->getGlobals();
 	if (Callees.size() > 0) {
 	  Function *firstCalledF = dyn_cast<Function>(*Callees.begin());
 	  FuncECs.addElement(firstCalledF);
-	  CallInstTargets[&CSI->getCallInst()].push_back(firstCalledF);
+	  CallInstTargets.insert(std::pair<CallInst*,Function*>
+				 (&CSI->getCallInst(),
+				  firstCalledF));
 	  if (Callees.size() > 1) {
 	    for (std::vector<GlobalValue*>::iterator CalleesI = 
 		   ++Callees.begin(), CalleesE = Callees.end(); 
 		 CalleesI != CalleesE; ++CalleesI) {
 	      Function *calledF = dyn_cast<Function>(*CalleesI);
-	      FuncECs.unionElements(firstCalledF, calledF);
-	      CallInstTargets[&CSI->getCallInst()].push_back(calledF);
+	      FuncECs.unionSetsWith(firstCalledF, calledF);
+	      CallInstTargets.insert(std::pair<CallInst*,Function*>
+				     (&CSI->getCallInst(), calledF));
 	    }
 	  }
 	} else {
-	  std::cerr << "Callee has no targets\n";
+	  std::cerr << "No targets " << CSI->getCallInst();
 	}
       }
     }
@@ -97,7 +111,6 @@
   
   // Print the equivalence classes
   DEBUG(printFuncECs());
-  
 }
 
 bool PoolAllocate::run(Module &M) {
@@ -523,7 +536,7 @@
 
     Function* getFuncClass(Value *V);
 
-    Value* retCloneIfNotFP(Value *V);
+    Value* retCloneIfFunc(Value *V);
   };
 }
 
@@ -534,13 +547,8 @@
 
 // Returns true if V is a function pointer
 bool FuncTransform::isFuncPtr(Value *V) {
-  if (V->getType()->getPrimitiveID() == Type::PointerTyID) {
-    const PointerType *PTy = dyn_cast<PointerType>(V->getType());
-    
-    if (PTy->getElementType()->getPrimitiveID() == Type::FunctionTyID)
-      return true;
-  }
-
+  if (const PointerType *PTy = dyn_cast<PointerType>(V->getType()))
+     return isa<FunctionType>(PTy->getElementType());
   return false;
 }
 
@@ -569,7 +577,7 @@
   if (!DSN) {
     return 0;
   }
-  std::vector<GlobalValue*> Callees = DSN->getGlobals();
+  std::vector<GlobalValue*> &Callees = DSN->getGlobals();
   if (Callees.size() > 0) {
     Function *calledF = dyn_cast<Function>(*Callees.begin());
     assert(PAInfo.FuncECs.findClass(calledF) && "should exist in some eq. class");
@@ -580,40 +588,36 @@
   return 0;
 }
 
-// Returns the clone if  V is not a function pointer 
-Value* FuncTransform::retCloneIfNotFP(Value *V) {
-  if (isFuncPtr(V))
-    if (isa<Function>(V))
-      if (getFuncClass(V)) {
-	Function *fixedFunc = dyn_cast<Function>(V);
-	return PAInfo.getFuncInfo(*fixedFunc)->Clone;
-      }
+// Returns the clone if  V is a static function (not a pointer) and belongs 
+// to an equivalence class i.e. is pool allocated
+Value* FuncTransform::retCloneIfFunc(Value *V) {
+  if (Function *fixedFunc = dyn_cast<Function>(V))
+    if (getFuncClass(V))
+      return PAInfo.getFuncInfo(*fixedFunc)->Clone;
   
   return 0;
 }
 
 void FuncTransform::visitReturnInst (ReturnInst &I) {
   if (I.getNumOperands())
-    if (Value *clonedFunc = retCloneIfNotFP(I.getOperand(0))) {
+    if (Value *clonedFunc = retCloneIfFunc(I.getOperand(0))) {
       // Cast the clone of I.getOperand(0) to the non-pool-allocated type
       CastInst *CastI = new CastInst(clonedFunc, I.getOperand(0)->getType(), 
-				     "", &I);
+				     "tmp", &I);
       // Insert return instruction that returns the casted value
       new ReturnInst(CastI, &I);
 
       // Remove original return instruction
-      I.setName("");
       I.getParent()->getInstList().erase(&I);
     }
 }
 
 void FuncTransform::visitStoreInst (StoreInst &I) {
   // Check if a constant function is being stored
-  if (Value *clonedFunc = retCloneIfNotFP(I.getOperand(0))) {
-    CastInst *CastI = new CastInst(clonedFunc, I.getOperand(0)->getType(), "", 
-				   &I);
+  if (Value *clonedFunc = retCloneIfFunc(I.getOperand(0))) {
+    CastInst *CastI = new CastInst(clonedFunc, I.getOperand(0)->getType(), 
+				   "tmp", &I);
     new StoreInst(CastI, I.getOperand(1), &I);
-    I.setName("");
     I.getParent()->getInstList().erase(&I);
   }
 }
@@ -626,11 +630,11 @@
   if (isFuncPtr(&I)) {
     PHINode *V = new PHINode(I.getType(), I.getName(), &I);
     for (unsigned i = 0 ; i < I.getNumIncomingValues(); ++i) {
-      if (Value *clonedFunc = retCloneIfNotFP(I.getIncomingValue(i))) {
+      if (Value *clonedFunc = retCloneIfFunc(I.getIncomingValue(i))) {
 	// Insert CastInst at the end of  I.getIncomingBlock(i)
 	BasicBlock::iterator BBI = --I.getIncomingBlock(i)->end();
 	// BBI now points to the terminator instruction of the basic block.
-	CastInst *CastI = new CastInst(clonedFunc, I.getType(), "", BBI);
+	CastInst *CastI = new CastInst(clonedFunc, I.getType(), "tmp", BBI);
 	V->addIncoming(CastI, I.getIncomingBlock(i));
       } else {
 	V->addIncoming(I.getIncomingValue(i), I.getIncomingBlock(i));
@@ -638,7 +642,6 @@
       
     }
     I.replaceAllUsesWith(V);
-    I.setName("");
     I.getParent()->getInstList().erase(&I);
   }
 }
@@ -739,8 +742,7 @@
       if (isa<Function>(CastI->getOperand(0)) && 
 	  CastI->getOperand(0)->getType() == CastI->getType())
 	CF = dyn_cast<Function>(CastI->getOperand(0));
-    } else if (isa<ConstantExpr>(CI.getOperand(0))) {
-      ConstantExpr *CE = dyn_cast<ConstantExpr>(CI.getOperand(0));
+    } else if (ConstantExpr *CE = dyn_cast<ConstantExpr>(CI.getOperand(0))) {
       if (CE->getOpcode() == Instruction::Cast) {
 	if (isa<ConstantPointerRef>(CE->getOperand(0)))
 	  return;
@@ -760,24 +762,25 @@
     std::map<unsigned, Value*> PoolArgs;
     Function *FuncClass;
     
-    for (vector<Function *>::iterator TFI = PAInfo.CallInstTargets[&CI].begin(),
-	   TFE = PAInfo.CallInstTargets[&CI].end(); TFI != TFE; ++TFI) {
-      if (TFI == PAInfo.CallInstTargets[&CI].begin()) {
-	FuncClass = PAInfo.FuncECs.findClass(*TFI);
+    std::pair<multimap<CallInst*, Function*>::iterator, multimap<CallInst*, Function*>::iterator> Targets = PAInfo.CallInstTargets.equal_range(&CI);
+    for (multimap<CallInst*, Function*>::iterator TFI = Targets.first,
+	   TFE = Targets.second; TFI != TFE; ++TFI) {
+      if (TFI == Targets.first) {
+	FuncClass = PAInfo.FuncECs.findClass(TFI->second);
 	// Nothing to transform if there are no pool arguments in this
 	// equivalence class of functions.
 	if (!PAInfo.EqClass2LastPoolArg.count(FuncClass))
 	  return;
       }
       
-      FuncInfo *CFI = PAInfo.getFuncInfo(**TFI);
+      FuncInfo *CFI = PAInfo.getFuncInfo(*TFI->second);
 
       if (!CFI->ArgNodes.size()) continue;  // Nothing to transform...
       
-      DSGraph &CG = PAInfo.getBUDataStructures().getDSGraph(**TFI);  
+      DSGraph &CG = PAInfo.getBUDataStructures().getDSGraph(*TFI->second);  
       std::map<DSNode*, DSNode*> NodeMapping;
       
-      Function::aiterator AI = (*TFI)->abegin(), AE = (*TFI)->aend();
+      Function::aiterator AI = TFI->second->abegin(), AE = TFI->second->aend();
       unsigned OpNum = 1;
       for ( ; AI != AE; ++AI, ++OpNum) {
 	if (!isa<Constant>(CI.getOperand(OpNum)))
@@ -832,15 +835,16 @@
     
     Value *NewCall;
     if (Args.size() > CI.getNumOperands() - 1) {
+      // If there are any pool arguments
       CastInst *CastI = 
 	new CastInst(CI.getOperand(0), 
-		     PAInfo.getFuncInfo(*FuncClass)->Clone->getType(), "", &CI);
+		     PAInfo.getFuncInfo(*FuncClass)->Clone->getType(), "tmp", 
+		     &CI);
       NewCall = new CallInst(CastI, Args, Name, &CI);
     } else {
       NewCall = new CallInst(CI.getOperand(0), Args, Name, &CI);
     }
 
-    CI.setName("");
     CI.replaceAllUsesWith(NewCall);
     DEBUG(std::cerr << "  Result Call: " << *NewCall);
   }
@@ -914,7 +918,7 @@
     // Add the rest of the arguments...
     Args.insert(Args.end(), CI.op_begin()+1, CI.op_end());
     
-    std::string Name = CI.getName(); CI.setName("");
+    std::string Name = CI.getName(); 
     Value *NewCall = new CallInst(CFI->Clone, Args, Name, &CI);
     CI.replaceAllUsesWith(NewCall);
     DEBUG(std::cerr << "  Result Call: " << *NewCall);




From ashukla at cs.uiuc.edu  Wed Jun  4 04:41:01 2003
From: ashukla at cs.uiuc.edu (Anand Shukla)
Date: Wed Jun  4 04:41:01 2003
Subject: [llvm-commits] CVS: llvm/lib/Reoptimizer/BinInterface/emit.cpp
Message-ID: <200306040940.EAA13332@morpheus.cs.uiuc.edu>


Changes in directory llvm/lib/Reoptimizer/BinInterface:

emit.cpp updated: 1.4 -> 1.5

---
Log message:

Fixed some bugs with register pressure and spills, and added some more ALU instruction constructors

---
Diffs of the changes:

Index: llvm/lib/Reoptimizer/BinInterface/emit.cpp
diff -u llvm/lib/Reoptimizer/BinInterface/emit.cpp:1.4 llvm/lib/Reoptimizer/BinInterface/emit.cpp:1.5
--- llvm/lib/Reoptimizer/BinInterface/emit.cpp:1.4	Sat May 31 17:07:45 2003
+++ llvm/lib/Reoptimizer/BinInterface/emit.cpp	Wed Jun  4 04:40:43 2003
@@ -231,7 +231,9 @@
   // and allocate space for them in the prolog (and save)
   // Do not touch reg 0
   unsigned save_regs = regs.touched_regs & ~ regs.liveout_regs & ~1;
-  
+  if(regs.spillreg)
+    save_regs |= (1<<regs.spillreg);
+
   unsigned save_area = stack_size;
 
   //add to the stack size, the regs being saved in prolog




From ashukla at cs.uiuc.edu  Wed Jun  4 04:41:06 2003
From: ashukla at cs.uiuc.edu (Anand Shukla)
Date: Wed Jun  4 04:41:06 2003
Subject: [llvm-commits] CVS: llvm/lib/Reoptimizer/BinInterface/select.cpp
Message-ID: <200306040940.EAA13346@morpheus.cs.uiuc.edu>


Changes in directory llvm/lib/Reoptimizer/BinInterface:

select.cpp updated: 1.5 -> 1.6

---
Log message:

Fixed some bugs with register pressure and spills, and added some more ALU instruction constructors

---
Diffs of the changes:

Index: llvm/lib/Reoptimizer/BinInterface/select.cpp
diff -u llvm/lib/Reoptimizer/BinInterface/select.cpp:1.5 llvm/lib/Reoptimizer/BinInterface/select.cpp:1.6
--- llvm/lib/Reoptimizer/BinInterface/select.cpp:1.5	Sat May 31 21:36:20 2003
+++ llvm/lib/Reoptimizer/BinInterface/select.cpp	Wed Jun  4 04:40:48 2003
@@ -26,6 +26,8 @@
 //
 //*****************************************************************************
 
+#define FOR_DEBUG
+
 void BinInterface::select(regalloc & regs)
 {
    regs.touched_regs = 0;    // mask containing all the touched registers
@@ -264,36 +266,43 @@
 	 
 	 //if this is last use, free up the machine reg
 	 if (vregs[vid].lastuse == i && vregs[vid].mreg != 0){
-	   freeregs.freereg(vregs[vid].mreg);
 	   
-	   if (VREG_ISREG(vregs[vid].mreg))
+	   //freeregs.freereg(vregs[vid].mreg);
+	   
+	   if (VREG_ISREG(vregs[vid].mreg)){
+	     freeregs.freereg(vregs[vid].mreg);
 	     hwregs[vregs[vid].mreg] = 0;
+	   }
 	 }
        }
        
        if (flags & IF_R_RS2){
 	 int vid = ssa_to_vreg[instr->alu.genrs2];
 	 if (vregs[vid].lastuse == i && vregs[vid].mreg != 0){
-	   freeregs.freereg(vregs[vid].mreg);
-	   if (VREG_ISREG(vregs[vid].mreg))
+	   //freeregs.freereg(vregs[vid].mreg);
+	   if (VREG_ISREG(vregs[vid].mreg)){
+	     freeregs.freereg(vregs[vid].mreg);
 	     hwregs[vregs[vid].mreg] = 0;
+	   }
 	 }
        }
 
        if (flags & IF_R_RD){
 	 int vid = ssa_to_vreg[instr->alu.genrd];
 	 if (vregs[vid].lastuse == i && vregs[vid].mreg != 0){
-	   freeregs.freereg(vregs[vid].mreg);
-	   if (VREG_ISREG(vregs[vid].mreg))
+	   //freeregs.freereg(vregs[vid].mreg);
+	   if (VREG_ISREG(vregs[vid].mreg)){
+	     freeregs.freereg(vregs[vid].mreg);
 	     hwregs[vregs[vid].mreg] = 0;
+	   }
 	 }
        }
        
        if ((flags & IF_W_RD) || ((flags & IF_RS1_RS2_DEFINED) && 
 				 !(flags & IF_BR))){
-	 assert((!(flags & IF_RS1_RS2_DEFINED) || 
-		 (flags & IF_RS1_RS2_DEFINED) && !(flags & IF_LIVEOUT)) && 
-		"liveout for new instructions not implemented");
+	 // assert((!(flags & IF_RS1_RS2_DEFINED) || 
+	 // (flags & IF_RS1_RS2_DEFINED) && !(flags & IF_LIVEOUT)) && 
+	 //"liveout for new instructions not implemented");
 	 
 	 bool skipIteration = false;
 	 //make sure this instruction is not in pinned
@@ -378,8 +387,6 @@
 	   hwregs[dreg]   = id;
 	   vregs[id].mreg = dreg;
 	 }
-	 
-	 vregs[id].mreg = dreg;
        }
      }
    }




From ashukla at cs.uiuc.edu  Wed Jun  4 04:42:01 2003
From: ashukla at cs.uiuc.edu (Anand Shukla)
Date: Wed Jun  4 04:42:01 2003
Subject: [llvm-commits] CVS: llvm/lib/Reoptimizer/BinInterface/construct.cpp
Message-ID: <200306040941.EAA13361@morpheus.cs.uiuc.edu>


Changes in directory llvm/lib/Reoptimizer/BinInterface:

construct.cpp updated: 1.4 -> 1.5

---
Log message:

Fixed some bugs with register pressure and spills, and added some more ALU instruction constructors

---
Diffs of the changes:

Index: llvm/lib/Reoptimizer/BinInterface/construct.cpp
diff -u llvm/lib/Reoptimizer/BinInterface/construct.cpp:1.4 llvm/lib/Reoptimizer/BinInterface/construct.cpp:1.5
--- llvm/lib/Reoptimizer/BinInterface/construct.cpp:1.4	Sat May 31 17:07:40 2003
+++ llvm/lib/Reoptimizer/BinInterface/construct.cpp	Wed Jun  4 04:40:38 2003
@@ -395,12 +395,15 @@
   for (int v=0;v<32;v++)
     map[v] = 0;
   
-  create_exits_liveouts(regmaps);
-  
   // Update gen fields for instructions (can't be done
   // in last pass due to insertion of PHI's)
   process_markgen(SECTION_PROLOG, map);
   process_markgen(SECTION_TRACE , map);
+
+  //for each PHI, insert a new SSA instruction
+  process_phis();
+
+  create_exits_liveouts(regmaps);
   
   // For each epilog
   for (unsigned int s=SECTION_TRACE+1;s<sections.size();s++){
@@ -418,6 +421,7 @@
 	continue;
       
       instruction * instr = itable[ssaid];
+      /*
       if (instr->flags & IF_PHI){
 	// if any of the PHI parameters are marked live out,
 	// the phi node itself becomes liveout.
@@ -433,9 +437,50 @@
 	// this one is liveout.  Let's do the insertion
 	shuffles->push_back(shufflepair(i,ssaid));
       }
+      */
+      
+      shuffles->push_back(shufflepair(i,ssaid));
     }
     // place the shuffler node
     allocnodeshuffles(s, shuffles);
   }
 }
 
+void BinInterface::process_phis(){
+  for (unsigned int i = begin(SECTION_TRACE); i!=end(SECTION_TRACE); ){
+    instruction *instr = itable[i];
+    
+    if(instr->flags & IF_PHI){
+      vector<unsigned> *vec = new vector<unsigned>();
+      for (unsigned int s = 0; s< instr->phi.params->size(); s++){
+	unsigned int j = (*instr->phi.params)[s];
+	instruction *phiArgInstr = itable[j];
+	if(phiArgInstr->flags & IF_NODELIVEIN){
+	  vec->push_back(j);
+	  continue;
+	}
+	
+	assert(phiArgInstr->flags & IF_W_RD && 
+	       "Phi instr must write into a reg");
+
+	//create a new move instruction, and insert it AFTER j
+	unsigned int movInstr = MK_MOV_R_R(instr->instr, 0);
+	unsigned int newCid = newaluOnlyRs2(movInstr, j);
+	itable[newCid]->flags |= IF_W_RD; //it writes into a destination
+	move(newCid, j);
+	
+	//if(itable[j]->flags & IF_LIVEOUT){
+	//itable[newCid]->flags |= IF_LIVEOUT;
+	//itable[j]->flags &= ~(IF_LIVEOUT);
+	//}
+
+	vec->push_back(newCid);
+      }
+      
+      delete instr->phi.params;
+      instr->phi.params = vec;
+    }
+
+    i = instr->next;
+  }
+}




From ashukla at cs.uiuc.edu  Wed Jun  4 04:42:05 2003
From: ashukla at cs.uiuc.edu (Anand Shukla)
Date: Wed Jun  4 04:42:05 2003
Subject: [llvm-commits] CVS: llvm/lib/Reoptimizer/BinInterface/sparcbin.cpp
Message-ID: <200306040941.EAA13354@morpheus.cs.uiuc.edu>


Changes in directory llvm/lib/Reoptimizer/BinInterface:

sparcbin.cpp updated: 1.6 -> 1.7

---
Log message:

Fixed some bugs with register pressure and spills, and added some more ALU instruction constructors

---
Diffs of the changes:

Index: llvm/lib/Reoptimizer/BinInterface/sparcbin.cpp
diff -u llvm/lib/Reoptimizer/BinInterface/sparcbin.cpp:1.6 llvm/lib/Reoptimizer/BinInterface/sparcbin.cpp:1.7
--- llvm/lib/Reoptimizer/BinInterface/sparcbin.cpp:1.6	Sat May 31 21:36:26 2003
+++ llvm/lib/Reoptimizer/BinInterface/sparcbin.cpp	Wed Jun  4 04:40:54 2003
@@ -182,14 +182,14 @@
     // Add instruction into linked list for given section
     insert_instr(tail, instr);
     tail = cid;
-#ifdef FOR_DEBUG
+    //#ifdef FOR_DEBUG
     printf("cid :%u\t", cid);
     if(instr->isFloatingPoint)
       printf("FP\n");
     else
       sparc_print(instr->instr);
     printf("\n");
-#endif    
+    //#endif    
 
     cid++;
     ibegin++;
@@ -595,6 +595,37 @@
   
   return cid;
 }
+
+unsigned BinInterface::newaluOnlyRs2(unsigned op, unsigned rs2){
+  instruction *instr = new instruction();
+  //do not set the flags IF_R_RSx, and instead assign SSA values to 
+  //rs1 and rs2 right here
+  instr->flags = (IF_ALUOP | IF_RS1_RS2_DEFINED | IF_R_RS2);
+  instr-> alu.genrs2 = rs2;
+  
+  instr->instr = op;
+  unsigned cid = itable.size();
+  instr->self = cid;
+  itable.push_back(instr);
+  
+  return cid;
+}
+
+unsigned BinInterface::newaluOnlyRs1(unsigned op, unsigned rs1){
+  instruction *instr = new instruction();
+  //do not set the flags IF_R_RSx, and instead assign SSA values to 
+  //rs1 and rs2 right here
+  instr->flags = (IF_ALUOP | IF_RS1_RS2_DEFINED | IF_R_RS1);
+  instr-> alu.genrs1 = rs1;
+  
+  instr->instr = op;
+  unsigned cid = itable.size();
+  instr->self = cid;
+  itable.push_back(instr);
+  
+  return cid;
+}
+
 
 //Create a NOP
 unsigned BinInterface::newnop(){




From ashukla at cs.uiuc.edu  Wed Jun  4 04:43:01 2003
From: ashukla at cs.uiuc.edu (Anand Shukla)
Date: Wed Jun  4 04:43:01 2003
Subject: [llvm-commits] CVS: llvm/include/llvm/Reoptimizer/BinInterface/sparcbin.h
Message-ID: <200306040942.EAA13387@morpheus.cs.uiuc.edu>


Changes in directory llvm/include/llvm/Reoptimizer/BinInterface:

sparcbin.h updated: 1.1 -> 1.2

---
Log message:

Fixed some bugs with register pressure and spills, and added some more ALU instruction constructors

---
Diffs of the changes:

Index: llvm/include/llvm/Reoptimizer/BinInterface/sparcbin.h
diff -u llvm/include/llvm/Reoptimizer/BinInterface/sparcbin.h:1.1 llvm/include/llvm/Reoptimizer/BinInterface/sparcbin.h:1.2
--- llvm/include/llvm/Reoptimizer/BinInterface/sparcbin.h:1.1	Sat May 31 17:18:40 2003
+++ llvm/include/llvm/Reoptimizer/BinInterface/sparcbin.h	Wed Jun  4 04:42:22 2003
@@ -116,6 +116,8 @@
       unsigned          emit_gen(unsigned char * out, const regalloc & regs);
 
 
+      void process_phis();
+     
    public:
 
 
@@ -225,7 +227,9 @@
 
       // General operation generation
       unsigned newalu  (unsigned op, unsigned rs1, unsigned rs2);
-      unsigned newalucc(unsigned op, unsigned rs1, unsigned rs2, unsigned cc0);
+      unsigned newaluOnlyRs2(unsigned op, unsigned rs2);
+      unsigned newaluOnlyRs1(unsigned op, unsigned rs1);
+      //unsigned newalucc(unsigned op, unsigned rs1, unsigned rs2, unsigned cc0);
 
       //new NOP
       unsigned newnop();




From ashukla at cs.uiuc.edu  Wed Jun  4 04:43:05 2003
From: ashukla at cs.uiuc.edu (Anand Shukla)
Date: Wed Jun  4 04:43:05 2003
Subject: [llvm-commits] CVS: llvm/include/llvm/Reoptimizer/BinInterface/sparcpriv.h
Message-ID: <200306040942.EAA13374@morpheus.cs.uiuc.edu>


Changes in directory llvm/include/llvm/Reoptimizer/BinInterface:

sparcpriv.h updated: 1.2 -> 1.3

---
Log message:

Fixed some bugs with register pressure and spills, and added some more ALU instruction constructors

---
Diffs of the changes:

Index: llvm/include/llvm/Reoptimizer/BinInterface/sparcpriv.h
diff -u llvm/include/llvm/Reoptimizer/BinInterface/sparcpriv.h:1.2 llvm/include/llvm/Reoptimizer/BinInterface/sparcpriv.h:1.3
--- llvm/include/llvm/Reoptimizer/BinInterface/sparcpriv.h:1.2	Sat May 31 21:32:10 2003
+++ llvm/include/llvm/Reoptimizer/BinInterface/sparcpriv.h	Wed Jun  4 04:41:52 2003
@@ -32,8 +32,7 @@
 #define RM_IGNORE ((1 << R_SP) | 1 | (1 << R_BP))
 
 // allocate all regs except R0(G0), O6(R14)(SP), I6(FP), g1-g7
-#define R_ALLOCREGS   (0xFFFFFFFF & ~ RM_IGNORE)//  & ~(0xff))       
-
+#define R_ALLOCREGS   (0xFFFFFFFF & ~ RM_IGNORE  & ~(0xff))       
 
 // Max of 62 epilogs (64 sections in all)
 #define MAX_SECTIONS 64




From vadve at cs.uiuc.edu  Wed Jun  4 09:26:01 2003
From: vadve at cs.uiuc.edu (Vikram Adve)
Date: Wed Jun  4 09:26:01 2003
Subject: [llvm-commits] CVS: llvm/test/Makefile.tests
Message-ID: <200306041425.JAA10749@psmith.cs.uiuc.edu>


Changes in directory llvm/test:

Makefile.tests updated: 1.60 -> 1.61

---
Log message:

Modify tracing rules to use opt -trace[m] instead of llc -trace[m].


---
Diffs of the changes:

Index: llvm/test/Makefile.tests
diff -u llvm/test/Makefile.tests:1.60 llvm/test/Makefile.tests:1.61
--- llvm/test/Makefile.tests:1.60	Tue Jun  3 13:56:53 2003
+++ llvm/test/Makefile.tests	Wed Jun  4 09:24:50 2003
@@ -65,12 +65,13 @@
 
 ## If TRACE or TRACEM is "yes", set the appropriate llc flag (-trace or -tracem)
 ## mark that tracing on, and set the TRACELIBS variable.
+TRACEFLAGS = 
 ifeq ($(TRACE), yes)
-    LLCFLAGS += -trace
+    TRACEFLAGS += -trace
     DOTRACING = yes
 else
     ifeq ($(TRACEM), yes)
-	LLCFLAGS += -tracem
+	TRACEFLAGS += -tracem
 	DOTRACING = yes
     endif
 endif




From vadve at cs.uiuc.edu  Wed Jun  4 09:26:06 2003
From: vadve at cs.uiuc.edu (Vikram Adve)
Date: Wed Jun  4 09:26:06 2003
Subject: [llvm-commits] CVS: llvm/test/Programs/Makefile.programs
Message-ID: <200306041425.JAA10756@psmith.cs.uiuc.edu>


Changes in directory llvm/test/Programs:

Makefile.programs updated: 1.54 -> 1.55

---
Log message:

Modify tracing rules to use opt -trace[m] instead of llc -trace[m].


---
Diffs of the changes:

Index: llvm/test/Programs/Makefile.programs
diff -u llvm/test/Programs/Makefile.programs:1.54 llvm/test/Programs/Makefile.programs:1.55
--- llvm/test/Programs/Makefile.programs:1.54	Tue Jun  3 13:56:57 2003
+++ llvm/test/Programs/Makefile.programs	Wed Jun  4 09:24:52 2003
@@ -182,6 +182,13 @@
 Output/%.llvm: Output/%.linked.bc
 	$(LGCCLD) $(STATS) $< -lgcc -lc $(LIBS) crtend.o -o Output/$*.llvm
 
+# Rule to get the tracing version of the llvm.bc file for tracing:
+ifeq ($(DOTRACING), yes)
+$(PROGRAMS_TO_TEST:%=Output/%.llvm.trace.bc): \
+Output/%.llvm.trace.bc: Output/%.llvm.bc
+	$(LOPT) $(TRACEFLAGS) $< -o $@
+endif
+
 # Targets to get the pass arguments that gccas and gccld are using...
 Output/gccas-pass-args: $(LGCCAS)
 	$(LGCCAS) /dev/null -o /dev/null -debug-pass=Arguments > $@.1 2>&1
@@ -229,7 +236,7 @@
 	-$(LLC) $(LLCFLAGS) -f $< -o $@
 
 $(PROGRAMS_TO_TEST:%=Output/%.trace.llc.s): \
-Output/%.trace.llc.s: Output/%.llvm.bc $(LLC)
+Output/%.trace.llc.s: Output/%.llvm.trace.bc $(LLC)
 	-$(LLC) $(LLCFLAGS) -f $< -o $@
 
 # Assemble (and link) an LLVM-linked program using the system assembler...




From vadve at cs.uiuc.edu  Wed Jun  4 09:26:10 2003
From: vadve at cs.uiuc.edu (Vikram Adve)
Date: Wed Jun  4 09:26:10 2003
Subject: [llvm-commits] CVS: llvm/test/Programs/External/SPEC/Makefile.spec
Message-ID: <200306041425.JAA10765@psmith.cs.uiuc.edu>


Changes in directory llvm/test/Programs/External/SPEC:

Makefile.spec updated: 1.8 -> 1.9

---
Log message:

Add tracing targets to Makefile.spec.


---
Diffs of the changes:

Index: llvm/test/Programs/External/SPEC/Makefile.spec
diff -u llvm/test/Programs/External/SPEC/Makefile.spec:1.8 llvm/test/Programs/External/SPEC/Makefile.spec:1.9
--- llvm/test/Programs/External/SPEC/Makefile.spec:1.8	Mon Jun  2 00:49:10 2003
+++ llvm/test/Programs/External/SPEC/Makefile.spec	Wed Jun  4 09:24:58 2003
@@ -91,3 +91,17 @@
              ../../$(RUNSAFELY) $(STDIN_FILENAME) $(STDOUT_FILENAME) \
                   ../../$< $(RUN_OPTIONS)
 	-(cd Output/cbe-$(RUN_TYPE); cat $(LOCAL_OUTPUTS)) > $@
+
+$(PROGRAMS_TO_TEST:%=Output/%.trace-out-llc): \
+Output/%.trace-out-llc: Output/%.trace.llc
+	$(SPEC_SANDBOX) llc-$(RUN_TYPE) $@ $(REF_IN_DIR) \
+             ../../$(RUNSAFELY) $(STDIN_FILENAME) $(STDOUT_FILENAME) \
+                  ../../$< $(RUN_OPTIONS)
+	-(cd Output/llc-$(RUN_TYPE); cat $(LOCAL_OUTPUTS)) > $@
+
+$(PROGRAMS_TO_TEST:%=Output/%.trace-out-cbe): \
+Output/%.trace-out-cbe: Output/%.trace.cbe
+	$(SPEC_SANDBOX) cbe-$(RUN_TYPE) $@ $(REF_IN_DIR) \
+             ../../$(RUNSAFELY) $(STDIN_FILENAME) $(STDOUT_FILENAME) \
+                  ../../$< $(RUN_OPTIONS)
+	-(cd Output/cbe-$(RUN_TYPE); cat $(LOCAL_OUTPUTS)) > $@




From gaeke at cs.uiuc.edu  Wed Jun  4 13:18:01 2003
From: gaeke at cs.uiuc.edu (Brian Gaeke)
Date: Wed Jun  4 13:18:01 2003
Subject: [llvm-commits] CVS: llvm/lib/CodeGen/Mapping/MappingInfo.cpp
Message-ID: <200306041817.NAA19963@neo.cs.uiuc.edu>


Changes in directory llvm/lib/CodeGen/Mapping:

MappingInfo.cpp updated: 1.6 -> 1.7

---
Log message:

Make writeNumber() void. Get ready to decouple it from .byte directive output.


---
Diffs of the changes:

Index: llvm/lib/CodeGen/Mapping/MappingInfo.cpp
diff -u llvm/lib/CodeGen/Mapping/MappingInfo.cpp:1.6 llvm/lib/CodeGen/Mapping/MappingInfo.cpp:1.7
--- llvm/lib/CodeGen/Mapping/MappingInfo.cpp:1.6	Tue Jun  3 14:30:15 2003
+++ llvm/lib/CodeGen/Mapping/MappingInfo.cpp	Wed Jun  4 13:17:22 2003
@@ -43,7 +43,7 @@
     void create_MI_to_number_Key(Function &FI);
     void writeBBToMImap(Function &FI, unsigned num);
     void writeLLVMToMImap(Function &FI, unsigned num);
-    unsigned writeNumber(unsigned X);
+    void writeNumber(unsigned X);
   };
 }
 
@@ -104,19 +104,24 @@
       << num << "\n\n\n\n";
 }
 
+/// outByte -- NOT DONE YET.
+void outByte (unsigned char b) {
+  Out << "\t.byte " << tmp << "\n";
+}
+
+
 /// writeNumber -- Write out the number X as a sequence of .byte
 /// directives to the current output stream Out. This method performs a
 /// run-length encoding of the unsigned integers X that are output.
-unsigned getMappingInfoForFunction::writeNumber(unsigned X) {
+void getMappingInfoForFunction::writeNumber(unsigned X) {
   unsigned i=0;
   do {
     unsigned tmp = X & 127;
     X >>= 7;
     if (X) tmp |= 128;
-    Out << "\t.byte " << tmp << "\n";
+    outByte (tmp);
     ++i;
   } while(X);
-  return i;
 }
 
 /// doInitialization -- Assign a number to each Function, as follows:




From brukman at cs.uiuc.edu  Wed Jun  4 14:46:00 2003
From: brukman at cs.uiuc.edu (Misha Brukman)
Date: Wed Jun  4 14:46:00 2003
Subject: [llvm-commits] CVS: llvm/tools/lli/JIT/Emitter.cpp
Message-ID: <200306041945.OAA14000@zion.cs.uiuc.edu>


Changes in directory llvm/tools/lli/JIT:

Emitter.cpp updated: 1.10 -> 1.11

---
Log message:

* Institute a hack for the Sparc call to mmap() to get our generated code to be
  laid out closer to the VM so that calls to library functions (e.g. puts()) and
  callback (e.g.  JITResolver::CompilationCallback) fit into 30 bits of the call
  instruction.
* Abort if architecture is not yet supported (not X86 or Sparc) because it
  likely requires a different set of parameters to mmap() .
* Stop using hard-coded values for page size; use sysconf(_SC_PAGESIZE) instead.


---
Diffs of the changes:

Index: llvm/tools/lli/JIT/Emitter.cpp
diff -u llvm/tools/lli/JIT/Emitter.cpp:1.10 llvm/tools/lli/JIT/Emitter.cpp:1.11
--- llvm/tools/lli/JIT/Emitter.cpp:1.10	Sun Jun  1 22:23:16 2003
+++ llvm/tools/lli/JIT/Emitter.cpp	Wed Jun  4 14:45:25 2003
@@ -67,20 +67,25 @@
 // FIXME: This should be rewritten to support a real memory manager for
 // executable memory pages!
 static void *getMemory(unsigned NumPages) {
+  void *pa;
+  if (NumPages == 0) return 0;
+  static const long pageSize = sysconf(_SC_PAGESIZE);
+
 #if defined(i386) || defined(__i386__) || defined(__x86__)
-  static const int fd = 0;
+  pa = mmap(0, pageSize*NumPages, PROT_READ|PROT_WRITE|PROT_EXEC,
+            MAP_PRIVATE|MAP_ANONYMOUS, 0, 0);  /* fd = 0  */
 #elif defined(sparc) || defined(__sparc__) || defined(__sparcv9)
-  static const int fd = -1;
+  static unsigned long Counter = 0;
+  pa = mmap((void*)(0x140000000UL+Counter), pageSize*NumPages,
+            PROT_READ|PROT_WRITE|PROT_EXEC,
+            MAP_PRIVATE|MAP_ANON|MAP_FIXED, -1, 0); /* fd = -1 */
+  Counter += pageSize*NumPages;
+  std::cerr << "getMemory() returning " << pa << "\n";
 #else
-  // This is an unsupported architecture.
-  static const int fd = 0;
+  std::cerr << "This architecture is not supported by the JIT\n";
+  abort();
 #endif
 
-  void *pa;
-  if (NumPages == 0) return 0;
-  static const long pageSize = sysconf (_SC_PAGESIZE);
-  pa = mmap(0, pageSize*NumPages, PROT_READ|PROT_WRITE|PROT_EXEC,
-            MAP_PRIVATE|MAP_ANONYMOUS, fd, 0);
   if (pa == MAP_FAILED) {
     perror("mmap");
     abort();
@@ -118,9 +123,10 @@
 }
 
 void Emitter::startFunctionStub(const Function &F, unsigned StubSize) {
+  static const long pageSize = sysconf(_SC_PAGESIZE);
   SavedCurBlock = CurBlock;  SavedCurByte = CurByte;
   // FIXME: this is a huge waste of memory.
-  CurBlock = (unsigned char *)getMemory((StubSize+4095)/4096);
+  CurBlock = (unsigned char *)getMemory((StubSize+pageSize-1)/pageSize);
   CurByte = CurBlock;  // Start writing at the beginning of the fn.
 }
 




From lattner at cs.uiuc.edu  Wed Jun  4 14:47:01 2003
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Wed Jun  4 14:47:01 2003
Subject: [llvm-commits] CVS: llvm/LICENSE.TXT
Message-ID: <200306041946.OAA03564@apoc.cs.uiuc.edu>


Changes in directory llvm:

LICENSE.TXT added (r1.1)

---
Log message:

Add prerelease license to cvs


---
Diffs of the changes:

Index: llvm/LICENSE.TXT
diff -c /dev/null llvm/LICENSE.TXT:1.1
*** /dev/null	Wed Jun  4 14:46:46 2003
--- llvm/LICENSE.TXT	Wed Jun  4 14:46:36 2003
***************
*** 0 ****
--- 1,19 ----
+ LLVM pre-release license:
+ 
+ This is a pre-release distribution of the LLVM software and is provided for
+ evaluation only.  This version of the LLVM software or modifications thereof
+ should not be distributed to third parties for any purpose.  Any third parties
+ interested in it can request a copy directly by sending e-mail to
+ llvmdev at cs.uiuc.edu.  As this is an evaluation release, we would appreciate any
+ and all feedback, ideas, and reports of bugs that you encounter.  These can be
+ submitted through the llvmbugs at cs.uiuc.edu or llvmdev at cs.uiuc.edu mailing lists
+ as appropriate.  We thank you for your interest in LLVM and look forward to any
+ comments or feedback you may have.
+ 
+ THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL THE
+ CONTRIBUTORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS WITH THE
+ SOFTWARE.




From brukman at cs.uiuc.edu  Wed Jun  4 15:02:00 2003
From: brukman at cs.uiuc.edu (Misha Brukman)
Date: Wed Jun  4 15:02:00 2003
Subject: [llvm-commits] CVS: llvm/lib/Target/Sparc/SparcV9CodeEmitter.cpp SparcV9CodeEmitter.h
Message-ID: <200306042001.PAA14084@zion.cs.uiuc.edu>


Changes in directory llvm/lib/Target/Sparc:

SparcV9CodeEmitter.cpp updated: 1.10 -> 1.11
SparcV9CodeEmitter.h updated: 1.5 -> 1.6

---
Log message:

* Instead of re-inventing the MachineConstantPool emitter that's already given
  in Emitter.cpp, just convert the Sparc version of the constant pool into
  what's already supported and inter-operate.
* Implemented a first pass at lazy function resolution in the JITResolver. That
  required adding a SparcV9CodeEmitter pointer to simplify generating
  bit-patterns of the instructions.
* SparcV9CodeEmitter now creates and destroys static TheJITResolver, which makes
  sense because the SparcV9CodeEmitter is the only user of TheJITResolver, and
  lives for the entire duration of the JIT (via PassManager which lives in VM).
* Changed all return values in the JITResolver to uint64_t because of the 64-bit
  Sparc architecture.
* Added a new version of getting the value of a GlobalValue in the
  SparcV9CodeEmitter, which now works for already-generated functions (JITted or
  library functions).
* Removed little-used and unused functions, cleaning up the internal view of the
  SparcV9CodeEmitter.


---
Diffs of the changes:

Index: llvm/lib/Target/Sparc/SparcV9CodeEmitter.cpp
diff -u llvm/lib/Target/Sparc/SparcV9CodeEmitter.cpp:1.10 llvm/lib/Target/Sparc/SparcV9CodeEmitter.cpp:1.11
--- llvm/lib/Target/Sparc/SparcV9CodeEmitter.cpp:1.10	Mon Jun  2 22:24:12 2003
+++ llvm/lib/Target/Sparc/SparcV9CodeEmitter.cpp	Wed Jun  4 15:01:13 2003
@@ -8,6 +8,7 @@
 #include "llvm/GlobalVariable.h"
 #include "llvm/PassManager.h"
 #include "llvm/CodeGen/MachineCodeEmitter.h"
+#include "llvm/CodeGen/MachineConstantPool.h"
 #include "llvm/CodeGen/MachineFunctionInfo.h"
 #include "llvm/CodeGen/MachineFunctionPass.h"
 #include "llvm/CodeGen/MachineInstr.h"
@@ -22,31 +23,41 @@
   //PM.add(new SparcV9CodeEmitter(MCE));
   //MachineCodeEmitter *M = MachineCodeEmitter::createDebugMachineCodeEmitter();
   MachineCodeEmitter *M = MachineCodeEmitter::createFilePrinterEmitter(MCE);
-  PM.add(new SparcV9CodeEmitter(this, *M));
+  PM.add(new SparcV9CodeEmitter(*this, *M));
   PM.add(createMachineCodeDestructionPass()); // Free stuff no longer needed
   return false;
 }
 
 namespace {
   class JITResolver {
+    SparcV9CodeEmitter &SparcV9;
     MachineCodeEmitter &MCE;
 
     // LazyCodeGenMap - Keep track of call sites for functions that are to be
     // lazily resolved.
-    std::map<unsigned, Function*> LazyCodeGenMap;
+    std::map<uint64_t, Function*> LazyCodeGenMap;
 
     // LazyResolverMap - Keep track of the lazy resolver created for a
     // particular function so that we can reuse them if necessary.
-    std::map<Function*, unsigned> LazyResolverMap;
+    std::map<Function*, uint64_t> LazyResolverMap;
   public:
-    JITResolver(MachineCodeEmitter &mce) : MCE(mce) {}
-    unsigned getLazyResolver(Function *F);
-    unsigned addFunctionReference(unsigned Address, Function *F);
-    
+    JITResolver(SparcV9CodeEmitter &V9,
+                MachineCodeEmitter &mce) : SparcV9(V9), MCE(mce) {}
+    uint64_t getLazyResolver(Function *F);
+    uint64_t addFunctionReference(uint64_t Address, Function *F);
+
+    // Utility functions for accessing data from static callback
+    uint64_t getCurrentPCValue() {
+      return MCE.getCurrentPCValue();
+    }
+    unsigned getBinaryCodeForInstr(MachineInstr &MI) {
+      return SparcV9.getBinaryCodeForInstr(MI);
+    }
+
   private:
-    unsigned emitStubForFunction(Function *F);
+    uint64_t emitStubForFunction(Function *F);
     static void CompilationCallback();
-    unsigned resolveFunctionReference(unsigned RetAddr);
+    uint64_t resolveFunctionReference(uint64_t RetAddr);
   };
 
   JITResolver *TheJITResolver;
@@ -57,26 +68,26 @@
 /// address.  Instead, we emit a call to the CompilationCallback method, and
 /// keep track of where we are.
 ///
-unsigned JITResolver::addFunctionReference(unsigned Address, Function *F) {
+uint64_t JITResolver::addFunctionReference(uint64_t Address, Function *F) {
   LazyCodeGenMap[Address] = F;  
   return (intptr_t)&JITResolver::CompilationCallback;
 }
 
-unsigned JITResolver::resolveFunctionReference(unsigned RetAddr) {
-  std::map<unsigned, Function*>::iterator I = LazyCodeGenMap.find(RetAddr);
+uint64_t JITResolver::resolveFunctionReference(uint64_t RetAddr) {
+  std::map<uint64_t, Function*>::iterator I = LazyCodeGenMap.find(RetAddr);
   assert(I != LazyCodeGenMap.end() && "Not in map!");
   Function *F = I->second;
   LazyCodeGenMap.erase(I);
   return MCE.forceCompilationOf(F);
 }
 
-unsigned JITResolver::getLazyResolver(Function *F) {
-  std::map<Function*, unsigned>::iterator I = LazyResolverMap.lower_bound(F);
+uint64_t JITResolver::getLazyResolver(Function *F) {
+  std::map<Function*, uint64_t>::iterator I = LazyResolverMap.lower_bound(F);
   if (I != LazyResolverMap.end() && I->first == F) return I->second;
   
 //std::cerr << "Getting lazy resolver for : " << ((Value*)F)->getName() << "\n";
 
-  unsigned Stub = emitStubForFunction(F);
+  uint64_t Stub = emitStubForFunction(F);
   LazyResolverMap.insert(I, std::make_pair(F, Stub));
   return Stub;
 }
@@ -85,26 +96,23 @@
   uint64_t *StackPtr = (uint64_t*)__builtin_frame_address(0);
   uint64_t RetAddr = (uint64_t)(intptr_t)__builtin_return_address(0);
 
-#if 0  
   std::cerr << "In callback! Addr=0x" << std::hex << RetAddr
-            << " SP=0x" << (unsigned)StackPtr << std::dec
-            << ": Resolving call to function: "
-            << TheVM->getFunctionReferencedName((void*)RetAddr) << "\n";
-#endif
-
-  std::cerr << "Sparc's JIT Resolver not implemented!\n";
-  abort();
+            << " SP=0x" << (uint64_t)(intptr_t)StackPtr << std::dec << "\n";
 
-#if 0
-  unsigned NewVal = TheJITResolver->resolveFunctionReference((void*)RetAddr);
+  int64_t NewVal = (int64_t)TheJITResolver->resolveFunctionReference(RetAddr);
 
   // Rewrite the call target... so that we don't fault every time we execute
   // the call.
-  *(unsigned*)RetAddr = NewVal;
+  int64_t RealCallTarget = (int64_t)
+    ((NewVal - TheJITResolver->getCurrentPCValue()) >> 4);
+  MachineInstr *MI = BuildMI(V9::CALL, 1);
+  MI->addSignExtImmOperand(RealCallTarget);
+  // FIXME: this could be in the wrong byte order!!
+  *((unsigned*)(intptr_t)RetAddr) = TheJITResolver->getBinaryCodeForInstr(*MI);
+  delete MI;
   
   // Change the return address to reexecute the call instruction...
   StackPtr[1] -= 4;
-#endif
 }
 
 /// emitStubForFunction - This method is used by the JIT when it needs to emit
@@ -113,28 +121,52 @@
 /// function compiler, which will eventually get fixed to call the function
 /// directly.
 ///
-unsigned JITResolver::emitStubForFunction(Function *F) {
+uint64_t JITResolver::emitStubForFunction(Function *F) {
 #if 0
   MCE.startFunctionStub(*F, 6);
   MCE.emitByte(0xE8);   // Call with 32 bit pc-rel destination...
 
-  unsigned Address = addFunctionReference(MCE.getCurrentPCValue(), F);
+  uint64_t Address = addFunctionReference(MCE.getCurrentPCValue(), F);
   MCE.emitWord(Address-MCE.getCurrentPCValue()-4);
 
   MCE.emitByte(0xCD);   // Interrupt - Just a marker identifying the stub!
   return (intptr_t)MCE.finishFunctionStub(*F);
 #endif
-  std::cerr << "Sparc's JITResolver::emitStubForFunction() not implemented!\n";
-  abort();
+  MCE.startFunctionStub(*F, 6);
+
+  int64_t CurrPC = MCE.getCurrentPCValue();
+  int64_t Addr = (int64_t)addFunctionReference(CurrPC, F);
+  int64_t CallTarget = (Addr-CurrPC) >> 2;
+  MachineInstr *Call = BuildMI(V9::CALL, 1);
+  Call->addSignExtImmOperand(CallTarget);
+  SparcV9.emitWord(SparcV9.getBinaryCodeForInstr(*Call));
+  delete Call;
+  
+  MachineInstr *Nop = BuildMI(V9::NOP, 0);
+  SparcV9.emitWord(SparcV9.getBinaryCodeForInstr(*Nop));
+  delete Nop;
+
+  SparcV9.emitWord(0xDEADBEEF); // marker so that we know it's really a stub
+  return (intptr_t)MCE.finishFunctionStub(*F);
+}
+
+
+SparcV9CodeEmitter::SparcV9CodeEmitter(TargetMachine &tm,
+                                       MachineCodeEmitter &M): TM(tm), MCE(M)
+{
+  TheJITResolver = new JITResolver(*this, M);
 }
 
+SparcV9CodeEmitter::~SparcV9CodeEmitter() {
+  delete TheJITResolver;
+}
 
-void SparcV9CodeEmitter::emitConstant(unsigned Val, unsigned Size) {
+void SparcV9CodeEmitter::emitWord(unsigned Val) {
   // Output the constant in big endian byte order...
   unsigned byteVal;
-  for (int i = Size-1; i >= 0; --i) {
+  for (int i = 3; i >= 0; --i) {
     byteVal = Val >> 8*i;
-    MCE->emitByte(byteVal & 255);
+    MCE.emitByte(byteVal & 255);
   }
 }
 
@@ -188,18 +220,60 @@
     std::cerr << "ERROR: virtual register found in machine code.\n";
     abort();
   } else if (MO.isPCRelativeDisp()) {
+    std::cerr << "PCRelativeDisp: ";
     Value *V = MO.getVRegValue();
     if (BasicBlock *BB = dyn_cast<BasicBlock>(V)) {
       std::cerr << "Saving reference to BB (VReg)\n";
-      unsigned* CurrPC = (unsigned*)(intptr_t)MCE->getCurrentPCValue();
+      unsigned* CurrPC = (unsigned*)(intptr_t)MCE.getCurrentPCValue();
       BBRefs.push_back(std::make_pair(BB, std::make_pair(CurrPC, &MI)));
-    } else if (Constant *C = dyn_cast<Constant>(V)) {
-      if (ConstantMap.find(C) != ConstantMap.end())
-        rv = (int64_t)(intptr_t)ConstantMap[C] - MCE->getCurrentPCValue();
-      else {
+    } else if (const Constant *C = dyn_cast<Constant>(V)) {
+      if (ConstantMap.find(C) != ConstantMap.end()) {
+        rv = (int64_t)MCE.getConstantPoolEntryAddress(ConstantMap[C]);
+        std::cerr << "const: 0x" << std::hex << rv
+                  << "\n" << std::dec;
+      } else {
         std::cerr << "ERROR: constant not in map:" << MO << "\n";
         abort();
       }
+    } else if (GlobalValue *GV = dyn_cast<GlobalValue>(V)) {
+      // same as MO.isGlobalAddress()
+      std::cerr << "GlobalValue: ";
+      // external function calls, etc.?
+      if (Function *F = dyn_cast<Function>(GV)) {
+        std::cerr << "Function: ";
+        if (F->isExternal()) {
+          // Sparc backend broken: this MO should be `ExternalSymbol'
+          rv = (int64_t)MCE.getGlobalValueAddress(F->getName());
+        } else {
+          rv = (int64_t)MCE.getGlobalValueAddress(F);
+        }
+        if (rv == 0) {
+          std::cerr << "not yet generated\n";
+          // Function has not yet been code generated!
+          TheJITResolver->addFunctionReference(MCE.getCurrentPCValue(), F);
+          // Delayed resolution...
+          rv = TheJITResolver->getLazyResolver(F);
+        } else {
+          std::cerr << "already generated: 0x" << std::hex << rv << "\n" 
+                    << std::dec;
+        }
+      } else {
+        std::cerr << "not a function: " << *GV << "\n";
+        abort();
+      }
+      // The real target of the call is Addr = PC + (rv * 4)
+      // So undo that: give the instruction (Addr - PC) / 4
+      if (MI.getOpcode() == V9::CALL) {
+        int64_t CurrPC = MCE.getCurrentPCValue();
+        std::cerr << "rv addr: 0x" << std::hex << rv << "\n";
+        std::cerr << "curr PC: 0x" << CurrPC << "\n";
+        rv = (rv - CurrPC) >> 2;
+        if (rv >= (1<<29) || rv <= -(1<<29)) {
+          std::cerr << "addr out of bounds for the 30-bit call: " << rv << "\n";
+          abort();
+        }
+        std::cerr << "returning addr: 0x" << rv << "\n" << std::dec;
+      }
     } else {
       std::cerr << "ERROR: PC relative disp unhandled:" << MO << "\n";
       abort();
@@ -209,16 +283,18 @@
     // in the real fashion -- it skips those that it chooses not to allocate,
     // i.e. those that are the SP, etc.
     unsigned fakeReg = MO.getReg(), realReg, regClass, regType;
-    regType = TM->getRegInfo().getRegType(fakeReg);
+    regType = TM.getRegInfo().getRegType(fakeReg);
     // At least map fakeReg into its class
-    fakeReg = TM->getRegInfo().getClassRegNum(fakeReg, regClass);
+    fakeReg = TM.getRegInfo().getClassRegNum(fakeReg, regClass);
     // Find the real register number for use in an instruction
     realReg = getRealRegNum(fakeReg, regClass);
     std::cerr << "Reg[" << std::dec << fakeReg << "] = " << realReg << "\n";
     rv = realReg;
   } else if (MO.isImmediate()) {
     rv = MO.getImmedValue();
+    std::cerr << "immed: " << rv << "\n";
   } else if (MO.isGlobalAddress()) {
+    std::cerr << "GlobalAddress: not PC-relative\n";
     rv = (int64_t)
       (intptr_t)getGlobalAddress(cast<GlobalValue>(MO.getVRegValue()),
                                  MI, MO.isPCRelative());
@@ -227,7 +303,7 @@
     // It should really hit this case, but Sparc backend uses VRegs instead
     std::cerr << "Saving reference to MBB\n";
     BasicBlock *BB = MO.getMachineBasicBlock()->getBasicBlock();
-    unsigned* CurrPC = (unsigned*)(intptr_t)MCE->getCurrentPCValue();
+    unsigned* CurrPC = (unsigned*)(intptr_t)MCE.getCurrentPCValue();
     BBRefs.push_back(std::make_pair(BB, std::make_pair(CurrPC, &MI)));
   } else if (MO.isExternalSymbol()) {
     // Sparc backend doesn't generate this (yet...)
@@ -269,45 +345,30 @@
   return (Val & 1);
 }
 
-void* SparcV9CodeEmitter::convertAddress(intptr_t Addr, bool isPCRelative) {
-  if (isPCRelative) {
-    return (void*)(Addr - (intptr_t)MCE->getCurrentPCValue());
-  } else {
-    return (void*)Addr;
-  }
-}
-
-
-
 bool SparcV9CodeEmitter::runOnMachineFunction(MachineFunction &MF) {
+  MCE.startFunction(MF);
   std::cerr << "Starting function " << MF.getFunction()->getName()
             << ", address: " << "0x" << std::hex 
-            << (long)MCE->getCurrentPCValue() << "\n";
-
-  MCE->startFunction(MF);
-
-  // FIXME: the Sparc backend does not use the ConstantPool!!
-  //MCE->emitConstantPool(MF.getConstantPool());
+            << (long)MCE.getCurrentPCValue() << "\n";
 
-  // Instead, the Sparc backend has its own constant pool implementation:
+  // The Sparc backend does not use MachineConstantPool;
+  // instead, it has its own constant pool implementation.
+  // We create a new MachineConstantPool here to be compatible with the emitter.
+  MachineConstantPool MCP;
   const hash_set<const Constant*> &pool = MF.getInfo()->getConstantPoolValues();
   for (hash_set<const Constant*>::const_iterator I = pool.begin(),
          E = pool.end();  I != E; ++I)
   {
-    const Constant *C = *I;
-    // For now we just allocate some memory on the heap, this can be
-    // dramatically improved.
-    const Type *Ty = ((Value*)C)->getType();
-    void *Addr = malloc(TM->getTargetData().getTypeSize(Ty));
-    //FIXME
-    //TheVM.InitializeMemory(C, Addr);
-    std::cerr << "Adding ConstantMap[" << C << "]=" << std::dec << Addr << "\n";
-    ConstantMap[C] = Addr;
+    Constant *C = (Constant*)*I;
+    unsigned idx = MCP.getConstantPoolIndex(C);
+    std::cerr << "Mapping constant 0x" << (intptr_t)C << " to " << idx << "\n";
+    ConstantMap[C] = idx;
   }  
+  MCE.emitConstantPool(&MCP);
 
   for (MachineFunction::iterator I = MF.begin(), E = MF.end(); I != E; ++I)
     emitBasicBlock(*I);
-  MCE->finishFunction(MF);
+  MCE.finishFunction(MF);
 
   std::cerr << "Finishing function " << MF.getFunction()->getName() << "\n";
   ConstantMap.clear();
@@ -360,13 +421,9 @@
 
 void SparcV9CodeEmitter::emitBasicBlock(MachineBasicBlock &MBB) {
   currBB = MBB.getBasicBlock();
-  BBLocations[currBB] = MCE->getCurrentPCValue();
+  BBLocations[currBB] = MCE.getCurrentPCValue();
   for (MachineBasicBlock::iterator I = MBB.begin(), E = MBB.end(); I != E; ++I)
-    emitInstruction(**I);
-}
-
-void SparcV9CodeEmitter::emitInstruction(MachineInstr &MI) {
-  emitConstant(getBinaryCodeForInstr(MI), 4);
+    emitWord(getBinaryCodeForInstr(**I));
 }
 
 void* SparcV9CodeEmitter::getGlobalAddress(GlobalValue *V, MachineInstr &MI,
@@ -374,15 +431,15 @@
 {
   if (isPCRelative) { // must be a call, this is a major hack!
     // Try looking up the function to see if it is already compiled!
-    if (void *Addr = (void*)(intptr_t)MCE->getGlobalValueAddress(V)) {
-      intptr_t CurByte = MCE->getCurrentPCValue();
+    if (void *Addr = (void*)(intptr_t)MCE.getGlobalValueAddress(V)) {
+      intptr_t CurByte = MCE.getCurrentPCValue();
       // The real target of the call is Addr = PC + (target * 4)
       // CurByte is the PC, Addr we just received
       return (void*) (((long)Addr - (long)CurByte) >> 2);
     } else {
       if (Function *F = dyn_cast<Function>(V)) {
         // Function has not yet been code generated!
-        TheJITResolver->addFunctionReference(MCE->getCurrentPCValue(),
+        TheJITResolver->addFunctionReference(MCE.getCurrentPCValue(),
                                              cast<Function>(V));
         // Delayed resolution...
         return 
@@ -390,36 +447,20 @@
 
       } else if (Constant *C = ConstantPointerRef::get(V)) {
         if (ConstantMap.find(C) != ConstantMap.end()) {
-          return ConstantMap[C];
+          return (void*)
+            (intptr_t)MCE.getConstantPoolEntryAddress(ConstantMap[C]);
         } else {
           std::cerr << "Constant: 0x" << std::hex << &*C << std::dec
                     << ", " << *V << " not found in ConstantMap!\n";
           abort();
         }
-
-#if 0
-      } else if (const GlobalVariable *G = dyn_cast<GlobalVariable>(V)) {
-        if (G->isConstant()) {
-          const Constant* C = G->getInitializer();
-          if (ConstantMap.find(C) != ConstantMap.end()) {
-            return ConstantMap[C];
-          } else {
-            std::cerr << "Constant: " << *G << " not found in ConstantMap!\n";
-            abort();
-          }
-        } else {
-          std::cerr << "Variable: " << *G << " address not found!\n";
-          abort();          
-        }
-#endif
       } else {
         std::cerr << "Unhandled global: " << *V << "\n";
         abort();
       }
     }
   } else {
-    return convertAddress((intptr_t)MCE->getGlobalValueAddress(V),
-                          isPCRelative);
+    return (void*)(intptr_t)MCE.getGlobalValueAddress(V);
   }
 }
 


Index: llvm/lib/Target/Sparc/SparcV9CodeEmitter.h
diff -u llvm/lib/Target/Sparc/SparcV9CodeEmitter.h:1.5 llvm/lib/Target/Sparc/SparcV9CodeEmitter.h:1.6
--- llvm/lib/Target/Sparc/SparcV9CodeEmitter.h:1.5	Sun Jun  1 23:12:39 2003
+++ llvm/lib/Target/Sparc/SparcV9CodeEmitter.h	Wed Jun  4 15:01:13 2003
@@ -16,8 +16,8 @@
 class MachineOperand;
 
 class SparcV9CodeEmitter : public MachineFunctionPass {
-  MachineCodeEmitter *MCE;
-  TargetMachine *TM;
+  TargetMachine &TM;
+  MachineCodeEmitter &MCE;
   BasicBlock *currBB;
 
   // Tracks which instruction references which BasicBlock
@@ -25,16 +25,17 @@
                         std::pair<unsigned*,MachineInstr*> > > BBRefs;
   // Tracks where each BasicBlock starts
   std::map<BasicBlock*, long> BBLocations;
+
   // Tracks locations of Constants which are laid out in memory (e.g. FP)
-  std::map<const Constant*, void*> ConstantMap;
+  // But we also need to map Constants to ConstantPool indices
+  std::map<const Constant*, unsigned> ConstantMap;
 
 public:
-  SparcV9CodeEmitter(TargetMachine *tm, MachineCodeEmitter &M) { 
-    MCE = &M;
-    TM = tm;
-  }
+  SparcV9CodeEmitter(TargetMachine &T, MachineCodeEmitter &M);
+  ~SparcV9CodeEmitter();
 
   bool runOnMachineFunction(MachineFunction &F);
+  void emitWord(unsigned Val);
     
   /// Function generated by the CodeEmitterGenerator using TableGen
   ///
@@ -43,16 +44,9 @@
 private:    
   int64_t getMachineOpValue(MachineInstr &MI, MachineOperand &MO);
   unsigned getValueBit(int64_t Val, unsigned bit);
-
-  void emitConstant(unsigned Val, unsigned Size);
-
   void emitBasicBlock(MachineBasicBlock &MBB);
-  void emitInstruction(MachineInstr &MI);
-    
-  void* convertAddress(intptr_t Addr, bool isPCRelative);
   void* getGlobalAddress(GlobalValue *V, MachineInstr &MI,
                          bool isPCRelative);
-
 };
 
 #endif




From lattner at cs.uiuc.edu  Wed Jun  4 15:09:03 2003
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Wed Jun  4 15:09:03 2003
Subject: [llvm-commits] CVS: llvm/lib/Transforms/Instrumentation/EmitFunctions.cpp
Message-ID: <200306042008.PAA03719@apoc.cs.uiuc.edu>


Changes in directory llvm/lib/Transforms/Instrumentation:

EmitFunctions.cpp updated: 1.8 -> 1.9

---
Log message:

Make this work with counter > 127


---
Diffs of the changes:

Index: llvm/lib/Transforms/Instrumentation/EmitFunctions.cpp
diff -u llvm/lib/Transforms/Instrumentation/EmitFunctions.cpp:1.8 llvm/lib/Transforms/Instrumentation/EmitFunctions.cpp:1.9
--- llvm/lib/Transforms/Instrumentation/EmitFunctions.cpp:1.8	Sat May 31 21:40:49 2003
+++ llvm/lib/Transforms/Instrumentation/EmitFunctions.cpp	Wed Jun  4 15:08:47 2003
@@ -37,7 +37,7 @@
                                           cstruct, "llvmFunctionTable");
   M.getGlobalList().push_back(gb);
 
-  ConstantInt *cnst = ConstantInt::get(Type::IntTy, counter); 
+  ConstantInt *cnst = ConstantSInt::get(Type::IntTy, counter); 
   GlobalVariable *fnCount = new GlobalVariable(Type::IntTy, true, 
 					       GlobalValue::ExternalLinkage, 
 					       cnst, "llvmFunctionCount");




From tbrethou at cs.uiuc.edu  Wed Jun  4 15:38:01 2003
From: tbrethou at cs.uiuc.edu (Tanya Brethour)
Date: Wed Jun  4 15:38:01 2003
Subject: [llvm-commits] CVS: llvm/lib/Reoptimizer/SSAPRE/Trigger.cpp
Message-ID: <200306042037.PAA14307@tank.cs.uiuc.edu>


Changes in directory llvm/lib/Reoptimizer/SSAPRE:

Trigger.cpp (r1.1) removed

---
Log message:

Since Anand reorganized things, Trigger.cpp is not longer needed. Optimizations should be called from
within RuntimeOptimizations.cpp. I am also sick of having to remove this each time I do a cvs update. 


---
Diffs of the changes:



From tbrethou at cs.uiuc.edu  Wed Jun  4 15:55:01 2003
From: tbrethou at cs.uiuc.edu (Tanya Brethour)
Date: Wed Jun  4 15:55:01 2003
Subject: [llvm-commits] CVS: llvm/lib/CodeGen/Mapping/MappingInfo.cpp
Message-ID: <200306042054.PAA15400@tank.cs.uiuc.edu>


Changes in directory llvm/lib/CodeGen/Mapping:

MappingInfo.cpp updated: 1.7 -> 1.8

---
Log message:

Had to comment out a line in outByte() to get it to compile because Out and tmp were
undeclared. I was not sure what Brian wanted, so I will let him fix this. But now it compiles.


---
Diffs of the changes:

Index: llvm/lib/CodeGen/Mapping/MappingInfo.cpp
diff -u llvm/lib/CodeGen/Mapping/MappingInfo.cpp:1.7 llvm/lib/CodeGen/Mapping/MappingInfo.cpp:1.8
--- llvm/lib/CodeGen/Mapping/MappingInfo.cpp:1.7	Wed Jun  4 13:17:22 2003
+++ llvm/lib/CodeGen/Mapping/MappingInfo.cpp	Wed Jun  4 15:53:46 2003
@@ -106,7 +106,7 @@
 
 /// outByte -- NOT DONE YET.
 void outByte (unsigned char b) {
-  Out << "\t.byte " << tmp << "\n";
+  //Out << "\t.byte " << tmp << "\n";
 }
 
 




From lattner at cs.uiuc.edu  Wed Jun  4 16:02:01 2003
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Wed Jun  4 16:02:01 2003
Subject: [llvm-commits] CVS: llvm/lib/CodeGen/Mapping/MappingInfo.cpp
Message-ID: <200306042101.QAA03916@apoc.cs.uiuc.edu>


Changes in directory llvm/lib/CodeGen/Mapping:

MappingInfo.cpp updated: 1.8 -> 1.9

---
Log message:

Revert brians patch to get mapping info working again
sorry dude


---
Diffs of the changes:

Index: llvm/lib/CodeGen/Mapping/MappingInfo.cpp
diff -u llvm/lib/CodeGen/Mapping/MappingInfo.cpp:1.8 llvm/lib/CodeGen/Mapping/MappingInfo.cpp:1.9
--- llvm/lib/CodeGen/Mapping/MappingInfo.cpp:1.8	Wed Jun  4 15:53:46 2003
+++ llvm/lib/CodeGen/Mapping/MappingInfo.cpp	Wed Jun  4 16:01:12 2003
@@ -43,7 +43,7 @@
     void create_MI_to_number_Key(Function &FI);
     void writeBBToMImap(Function &FI, unsigned num);
     void writeLLVMToMImap(Function &FI, unsigned num);
-    void writeNumber(unsigned X);
+    unsigned writeNumber(unsigned X);
   };
 }
 
@@ -104,24 +104,19 @@
       << num << "\n\n\n\n";
 }
 
-/// outByte -- NOT DONE YET.
-void outByte (unsigned char b) {
-  //Out << "\t.byte " << tmp << "\n";
-}
-
-
 /// writeNumber -- Write out the number X as a sequence of .byte
 /// directives to the current output stream Out. This method performs a
 /// run-length encoding of the unsigned integers X that are output.
-void getMappingInfoForFunction::writeNumber(unsigned X) {
+unsigned getMappingInfoForFunction::writeNumber(unsigned X) {
   unsigned i=0;
   do {
     unsigned tmp = X & 127;
     X >>= 7;
     if (X) tmp |= 128;
-    outByte (tmp);
+    Out << "\t.byte " << tmp << "\n";
     ++i;
   } while(X);
+  return i;
 }
 
 /// doInitialization -- Assign a number to each Function, as follows:




From gaeke at uiuc.edu  Wed Jun  4 16:19:01 2003
From: gaeke at uiuc.edu (Brian R. Gaeke)
Date: Wed Jun  4 16:19:01 2003
Subject: [llvm-commits] CVS: llvm/lib/CodeGen/Mapping/MappingInfo.cpp (fwd)
In-Reply-To: <Pine.LNX.4.44.0306041602020.24510-100000@nondot.org>
References: <Pine.LNX.4.44.0306041602020.24510-100000@nondot.org>
Message-ID: <20030604211850.GA64656@prisoner.dgate.ORG>

Sorry about that.  I didn't realize the NOT DONE YET version slipped in there.
I'll be checking in a new version after my SPARC build finishes.

-Brian

> From: Tanya Brethour <tbrethou at cs.uiuc.edu>
> 
> Changes in directory llvm/lib/CodeGen/Mapping:
> MappingInfo.cpp updated: 1.7 -> 1.8
> 
> ---
> Log message:
> 
> Had to comment out a line in outByte() to get it to compile because Out and tmp were
> undeclared. I was not sure what Brian wanted, so I will let him fix this. But now it compiles.

-- 
gaeke at uiuc.edu


From gaeke at cs.uiuc.edu  Wed Jun  4 17:03:01 2003
From: gaeke at cs.uiuc.edu (Brian Gaeke)
Date: Wed Jun  4 17:03:01 2003
Subject: [llvm-commits] CVS: llvm/include/llvm/Reoptimizer/Mapping/MappingInfo.h
Message-ID: <200306042202.RAA17760@morpheus.cs.uiuc.edu>


Changes in directory llvm/include/llvm/Reoptimizer/Mapping:

MappingInfo.h updated: 1.1 -> 1.2

---
Log message:

Add file comment. Include <vector> and <string>.  Update include guards
to reflect file's current location.  Add definition of class
MappingInfo.


---
Diffs of the changes:

Index: llvm/include/llvm/Reoptimizer/Mapping/MappingInfo.h
diff -u llvm/include/llvm/Reoptimizer/Mapping/MappingInfo.h:1.1 llvm/include/llvm/Reoptimizer/Mapping/MappingInfo.h:1.2
--- llvm/include/llvm/Reoptimizer/Mapping/MappingInfo.h:1.1	Mon Jul 22 17:09:35 2002
+++ llvm/include/llvm/Reoptimizer/Mapping/MappingInfo.h	Wed Jun  4 17:02:47 2003
@@ -1,11 +1,38 @@
-#ifndef LLVM_CODEGEN_MAPPINGINFO_H
-#define LLVM_CODEGEN_MAPPINGINFO_H
+//===- llvm/Reoptimizer/Mapping/MappingInfo.h ------------------*- C++ -*--=////
+//
+// Data structures to support the Reoptimizer's Instruction-to-MachineInstr
+// mapping information gatherer.
+//
+//===----------------------------------------------------------------------===//
+
+#ifndef LLVM_REOPTIMIZER_MAPPING_MAPPINGINFO_H
+#define LLVM_REOPTIMIZER_MAPPING_MAPPINGINFO_H
 
 #include <iosfwd>
+#include <vector>
+#include <string>
 class Pass;
 
-Pass *MappingInfoForFunction(std::ostream &out);
-
-#endif
+Pass *getMappingInfoCollector(std::ostream &out);
 
+class MappingInfo {
+  class byteVector : public std::vector <unsigned char> {
+  public:
+	void dumpAssembly (std::ostream &Out);
+  };
+  std::string comment;
+  std::string symbolPrefix;
+  unsigned functionNumber;
+  byteVector bytes;
+public:
+  void outByte (unsigned char b) { bytes.push_back (b); }
+  MappingInfo (std::string _comment, std::string _symbolPrefix,
+	           unsigned _functionNumber) : comment(_comment),
+        	   symbolPrefix(_symbolPrefix), functionNumber(_functionNumber) { }
+  void dumpAssembly (std::ostream &Out);
+  unsigned char *getBytes (unsigned int &length) {
+	length = bytes.size(); return &bytes[0];
+  }
+};
 
+#endif




From gaeke at cs.uiuc.edu  Wed Jun  4 17:08:04 2003
From: gaeke at cs.uiuc.edu (Brian Gaeke)
Date: Wed Jun  4 17:08:04 2003
Subject: [llvm-commits] CVS: llvm/lib/CodeGen/Mapping/MappingInfo.cpp
Message-ID: <200306042207.RAA17791@morpheus.cs.uiuc.edu>


Changes in directory llvm/lib/CodeGen/Mapping:

MappingInfo.cpp updated: 1.9 -> 1.10

---
Log message:

lib/CodeGen/Mapping/MappingInfo.cpp:
 Update file comment to contain a bunch of the overview mapping-info
  documentation previously buried within the file.
 Remove some unnecessary include/using stmts.
 Rename pass to MappingInfoCollector.
 Rewrite a lot of it so it doesn't use global instance variables and so
  it outputs into MappingInfo objects and then dumps those out, instead of going
  straight to an assembly file.
 Change name of factory to getMappingInfoCollector.
 Fold prologue & epilogue writers into MappingInfo methods.

lib/Target/Sparc/FInfo.cpp:
 Correct file comment to reflect above change

lib/Target/Sparc/Sparc.cpp:
 Change name of factory to getMappingInfoCollector.


---
Diffs of the changes:

Index: llvm/lib/CodeGen/Mapping/MappingInfo.cpp
diff -u llvm/lib/CodeGen/Mapping/MappingInfo.cpp:1.9 llvm/lib/CodeGen/Mapping/MappingInfo.cpp:1.10
--- llvm/lib/CodeGen/Mapping/MappingInfo.cpp:1.9	Wed Jun  4 16:01:12 2003
+++ llvm/lib/CodeGen/Mapping/MappingInfo.cpp	Wed Jun  4 17:07:10 2003
@@ -1,9 +1,9 @@
 //===- MappingInfo.cpp - create LLVM info and output to .s file ---------===//
 //
-// This file contains a FunctionPass called getMappingInfoForFunction,
-// which creates two maps: one between LLVM Instructions and MachineInstrs,
-// and another between MachineBasicBlocks and MachineInstrs (the "BB TO
-// MI MAP").
+// This file contains a FunctionPass called MappingInfo,
+// which creates two maps: one between LLVM Instructions and MachineInstrs
+// (the "LLVM I TO MI MAP"), and another between MachineBasicBlocks and
+// MachineInstrs (the "BB TO MI MAP").
 //
 // As a side effect, it outputs this information as .byte directives to
 // the assembly file. The output is designed to survive the SPARC assembler,
@@ -12,6 +12,27 @@
 // dependencies. Currently this question is purely theoretical as the
 // Reoptimizer works only on the SPARC.
 //
+// The LLVM I TO MI MAP consists of a set of information for each
+// BasicBlock in a Function, ordered from begin() to end(). The information
+// for a BasicBlock consists of
+//  1) its (0-based) index in the Function,
+//  2) the number of LLVM Instructions it contains, and
+//  3) information for each Instruction, in sequence from the begin()
+//     to the end() of the BasicBlock. The information for an Instruction
+//     consists of
+//     1) its (0-based) index in the BasicBlock,
+//     2) the number of MachineInstrs that correspond to that Instruction
+//        (as reported by MachineCodeForInstruction), and
+//     3) the MachineInstr number calculated by create_MI_to_number_Key,
+//        for each of the MachineInstrs that correspond to that Instruction.
+//
+// The BB TO MI MAP consists of a three-element tuple for each
+// MachineBasicBlock in a function, ordered from begin() to end() of
+// its MachineFunction: first, the index of the MachineBasicBlock in the
+// function; second, the number of the MachineBasicBlock in the function
+// as computed by create_BB_to_MInumber_Key; and third, the number of
+// MachineInstrs in the MachineBasicBlock.
+//
 //===--------------------------------------------------------------------===//
 
 #include "llvm/Reoptimizer/Mapping/MappingInfo.h"
@@ -20,103 +41,69 @@
 #include "llvm/CodeGen/MachineInstr.h"
 #include "llvm/CodeGen/MachineFunction.h"
 #include "llvm/CodeGen/MachineCodeForInstruction.h"
-#include <map>
-using std::vector;
 
 namespace {
-  class getMappingInfoForFunction : public FunctionPass { 
+  class MappingInfoCollector : public FunctionPass { 
     std::ostream &Out;
   public:
-    getMappingInfoForFunction(std::ostream &out) : Out(out){}
-    const char* getPassName() const{return "Sparc MappingInformation";}
+    MappingInfoCollector(std::ostream &out) : Out(out){}
+    const char *getPassName () const { return "Instr. Mapping Info Collector"; }
     bool runOnFunction(Function &FI);
+    typedef std::map<const MachineInstr*, unsigned> InstructionKey;
   private:
-    std::map<const Function*, unsigned> Fkey; //key of F to num
-    std::map<const MachineInstr*, unsigned> BBkey; //key BB to num
-    std::map<const MachineInstr*, unsigned> MIkey; //key MI to num
-    void writePrologue(const std::string &comment,
-                       const std::string &symbolPrefix, unsigned num);
-    void writeEpilogue(const std::string &symbolPrefix, unsigned num);
-
+    MappingInfo *currentOutputMap;
+    std::map<Function *, unsigned> Fkey; // Function # for all functions.
     bool doInitialization(Module &M);
-    void create_BB_to_MInumber_Key(Function &FI);    
-    void create_MI_to_number_Key(Function &FI);
-    void writeBBToMImap(Function &FI, unsigned num);
-    void writeLLVMToMImap(Function &FI, unsigned num);
-    unsigned writeNumber(unsigned X);
+    void create_BB_to_MInumber_Key(Function &FI, InstructionKey &key);
+    void create_MI_to_number_Key(Function &FI, InstructionKey &key);
+    void buildBBMIMap (Function &FI, MappingInfo &Map);
+    void buildLMIMap (Function &FI, MappingInfo &Map);
+    void writeNumber(unsigned X);
+    void selectOutputMap (MappingInfo &m) { currentOutputMap = &m; }
+    void outByte (unsigned char b) { currentOutputMap->outByte (b); }
   };
 }
 
-/// MappingInfoForFunction -- Static factory method: returns a new
-/// getMappingInfoForFunction Pass object, which uses OUT as its
+/// getMappingInfoCollector -- Static factory method: returns a new
+/// MappingInfoCollector Pass object, which uses OUT as its
 /// output stream for assembly output. 
-Pass *MappingInfoForFunction(std::ostream &out){
-  return (new getMappingInfoForFunction(out));
+Pass *getMappingInfoCollector(std::ostream &out){
+  return (new MappingInfoCollector(out));
 }
 
 /// runOnFunction -- Builds up the maps for the given function FI and then
 /// writes them out as assembly code to the current output stream OUT.
 /// This is an entry point to the pass, called by the PassManager.
-bool getMappingInfoForFunction::runOnFunction(Function &FI) {
-  // First we build temporary tables used to write out the maps.
-  create_BB_to_MInumber_Key(FI);
-  create_MI_to_number_Key(FI);
+bool MappingInfoCollector::runOnFunction(Function &FI) {
   unsigned num = Fkey[&FI]; // Function number for the current function.
 
+  // Create objects to hold the maps.
+  MappingInfo LMIMap ("LLVM I TO MI MAP", "LMIMap", num);
+  MappingInfo BBMIMap ("BB TO MI MAP", "BBMIMap", num);
+
+  // Now, build the maps.
+  buildLMIMap (FI, LMIMap);
+  buildBBMIMap (FI, BBMIMap);
+
   // Now, write out the maps.
-  writeBBToMImap(FI, num);
-  writeLLVMToMImap(FI, num);
+  LMIMap.dumpAssembly (Out);
+  BBMIMap.dumpAssembly (Out);
 
   return false; 
 }  
 
-/// writePrologue -- Output a COMMENT describing the map, then output a
-/// global symbol to start the map named by concatenating SYMBOLPREFIX
-/// and NUM, then output a word containing the length of the map, to the
-/// current output stream Out. This also switches the current section to
-/// .rodata in the assembly output.
-void getMappingInfoForFunction::writePrologue(const std::string &comment,
-                                              const std::string &symbolPrefix,
-                                              unsigned num) {
-  // Comment:
-  Out << "!" << comment << "\n";   
-  // Switch sections:
-  Out << "\t.section \".rodata\"\n\t.align 8\n";  
-  // Global symbol naming the map:
-  Out << "\t.global " << symbolPrefix << num << "\n";    
-  Out << "\t.type " << symbolPrefix << num << ",#object\n"; 
-  Out << symbolPrefix << num << ":\n"; 
-  // Length word:
-  Out << "\t.word .end_" << symbolPrefix << num << "-"
-      << symbolPrefix << num << "\n";
-}
-
-/// writeEpilogue -- Outputs a local symbol to end the map named by
-/// concatenating SYMBOLPREFIX and NUM, followed by a .size directive that
-/// gives the size of the map, to the current output stream Out.
-void getMappingInfoForFunction::writeEpilogue(const std::string &symbolPrefix,
-                                              unsigned num) {
-  // Local symbol ending the map:
-  Out << ".end_" << symbolPrefix << num << ":\n";    
-  // Size directive:
-  Out << "\t.size " << symbolPrefix << num << ", .end_" 
-      << symbolPrefix << num << "-" << symbolPrefix 
-      << num << "\n\n\n\n";
-}
-
 /// writeNumber -- Write out the number X as a sequence of .byte
 /// directives to the current output stream Out. This method performs a
 /// run-length encoding of the unsigned integers X that are output.
-unsigned getMappingInfoForFunction::writeNumber(unsigned X) {
+void MappingInfoCollector::writeNumber(unsigned X) {
   unsigned i=0;
   do {
     unsigned tmp = X & 127;
     X >>= 7;
     if (X) tmp |= 128;
-    Out << "\t.byte " << tmp << "\n";
+    outByte (tmp);
     ++i;
   } while(X);
-  return i;
 }
 
 /// doInitialization -- Assign a number to each Function, as follows:
@@ -125,14 +112,14 @@
 /// inserted into the maps, and are not assigned a number.  The side-effect
 /// of this method is to fill in Fkey to contain the mapping from Functions
 /// to numbers. (This method is called automatically by the PassManager.)
-bool getMappingInfoForFunction::doInitialization(Module &M) {
+bool MappingInfoCollector::doInitialization(Module &M) {
   unsigned i = 0;
   for (Module::iterator FI = M.begin(), FE = M.end(); FI != FE; ++FI) {
     if (FI->isExternal()) continue;
     Fkey[FI] = i;
     ++i;
   }
-  return false;
+  return false; // Success.
 }
 
 /// create_BB_to_MInumber_Key -- Assign a number to each MachineBasicBlock
@@ -140,17 +127,18 @@
 /// Function. MachineBasicBlocks are numbered from begin() to end()
 /// in the Function's corresponding MachineFunction. Each successive
 /// MachineBasicBlock increments the numbering by the number of instructions
-/// it contains. The side-effect of this method is to fill in the instance
-/// variable BBkey with the mapping of MachineBasicBlocks to numbers. BBkey
+/// it contains. The side-effect of this method is to fill in the paramete
+/// KEY with the mapping of MachineBasicBlocks to numbers. KEY
 /// is keyed on MachineInstrs, so each MachineBasicBlock is represented
 /// therein by its first MachineInstr.
-void getMappingInfoForFunction::create_BB_to_MInumber_Key(Function &FI) {
+void MappingInfoCollector::create_BB_to_MInumber_Key(Function &FI,
+                                                     InstructionKey &key) {
   unsigned i = 0;
   MachineFunction &MF = MachineFunction::get(&FI);
   for (MachineFunction::iterator BI = MF.begin(), BE = MF.end();
        BI != BE; ++BI) {
     MachineBasicBlock &miBB = *BI;
-    BBkey[miBB[0]] = i;
+    key[miBB[0]] = i;
     i = i+(miBB.size());
   }
 }
@@ -160,32 +148,31 @@
 /// follows: Numberings start at 0 in each MachineBasicBlock. MachineInstrs
 /// are numbered from begin() to end() in their MachineBasicBlock. Each
 /// MachineInstr is numbered, then the numbering is incremented by 1. The
-/// side-effect of this method is to fill in the instance variable MIkey
+/// side-effect of this method is to fill in the parameter KEY
 /// with the mapping from MachineInstrs to numbers.
-void getMappingInfoForFunction::create_MI_to_number_Key(Function &FI) {
+void MappingInfoCollector::create_MI_to_number_Key(Function &FI,
+                                                   InstructionKey &key) {
   MachineFunction &MF = MachineFunction::get(&FI);
   for (MachineFunction::iterator BI=MF.begin(), BE=MF.end(); BI != BE; ++BI) {
     MachineBasicBlock &miBB = *BI;
     unsigned j = 0;
-    for(MachineBasicBlock::iterator miI=miBB.begin(), miE=miBB.end();
-	miI!=miE; ++miI, ++j) {
-      MIkey[*miI]=j;
+    for(MachineBasicBlock::iterator miI = miBB.begin(), miE = miBB.end();
+        miI != miE; ++miI, ++j) {
+      key[*miI] = j;
     }
   }
 }
 
-/// writeBBToMImap -- Output the BB TO MI MAP for the given function as
-/// assembly code to the current output stream. The BB TO MI MAP consists
-/// of a three-element tuple for each MachineBasicBlock in a function:
-/// first, the index of the MachineBasicBlock in the function; second,
-/// the number of the MachineBasicBlock in the function as computed by
-/// create_BB_to_MInumber_Key; and third, the number of MachineInstrs in
-/// the MachineBasicBlock.
-void getMappingInfoForFunction::writeBBToMImap(Function &FI, unsigned num){
+/// buildBBMIMap -- Build the BB TO MI MAP for the function FI,
+/// and save it into the parameter MAP.
+void MappingInfoCollector::buildBBMIMap(Function &FI, MappingInfo &Map) {
   unsigned bb = 0;
-  const std::string MapComment = "BB TO MI MAP";
-  const std::string MapSymbolPrefix = "BBMIMap";
-  writePrologue(MapComment, MapSymbolPrefix, num);
+
+  // First build temporary table used to write out the map.
+  InstructionKey BBkey;
+  create_BB_to_MInumber_Key(FI, BBkey);
+
+  selectOutputMap (Map);
   MachineFunction &MF = MachineFunction::get(&FI);  
   for (MachineFunction::iterator BI = MF.begin(), BE = MF.end();
        BI != BE; ++BI, ++bb) {
@@ -194,26 +181,17 @@
     writeNumber(BBkey[miBB[0]]);
     writeNumber(miBB.size());
   }
-  writeEpilogue(MapSymbolPrefix, num);  
 }
 
-/// writeLLVMToMImap -- Output the LLVM I TO MI MAP for the given function
-/// as assembly code to the current output stream. The LLVM I TO MI MAP
-/// consists of a set of information for each BasicBlock in a Function,
-/// ordered from begin() to end(). The information for a BasicBlock consists
-/// of 1) its (0-based) index in the Function, 2) the number of LLVM
-/// Instructions it contains, and 3) information for each Instruction, in
-/// sequence from the begin() to the end() of the BasicBlock. The information
-/// for an Instruction consists of 1) its (0-based) index in the BasicBlock,
-/// 2) the number of MachineInstrs that correspond to that Instruction
-/// (as reported by MachineCodeForInstruction), and 3) the MachineInstr
-/// number calculated by create_MI_to_number_Key, for each of the
-/// MachineInstrs that correspond to that Instruction.
-void getMappingInfoForFunction::writeLLVMToMImap(Function &FI, unsigned num) {
+/// buildLMIMap -- Build the LLVM I TO MI MAP for the function FI,
+/// and save it into the parameter MAP.
+void MappingInfoCollector::buildLMIMap(Function &FI, MappingInfo &Map) {
   unsigned bb = 0;
-  const std::string MapComment = "LLVM I TO MI MAP";
-  const std::string MapSymbolPrefix = "LMIMap";
-  writePrologue(MapComment, MapSymbolPrefix, num);
+  // First build temporary table used to write out the map.
+  InstructionKey MIkey;
+  create_MI_to_number_Key(FI, MIkey);
+
+  selectOutputMap (Map);
   for (Function::iterator BI = FI.begin(), BE = FI.end(); 
        BI != BE; ++BI, ++bb) {
     unsigned li = 0;
@@ -230,5 +208,35 @@
       }
     }
   } 
-  writeEpilogue(MapSymbolPrefix, num); 
+}
+
+void MappingInfo::byteVector::dumpAssembly (std::ostream &Out) {
+  for (iterator i = begin (), e = end (); i != e; ++i)
+	Out << ".byte " << (int)*i << "\n";
+}
+
+void MappingInfo::dumpAssembly (std::ostream &Out) {
+  // Prologue:
+  // Output a comment describing the map.
+  Out << "!" << comment << "\n";   
+  // Switch the current section to .rodata in the assembly output:
+  Out << "\t.section \".rodata\"\n\t.align 8\n";  
+  // Output a global symbol naming the map:
+  Out << "\t.global " << symbolPrefix << functionNumber << "\n";    
+  Out << "\t.type " << symbolPrefix << functionNumber << ",#object\n"; 
+  Out << symbolPrefix << functionNumber << ":\n"; 
+  // Output a word containing the length of the map:
+  Out << "\t.word .end_" << symbolPrefix << functionNumber << "-"
+      << symbolPrefix << functionNumber << "\n";
+
+  // Output the map data itself:
+  bytes.dumpAssembly (Out);
+
+  // Epilogue:
+  // Output a local symbol marking the end of the map:
+  Out << ".end_" << symbolPrefix << functionNumber << ":\n";    
+  // Output size directive giving the size of the map:
+  Out << "\t.size " << symbolPrefix << functionNumber << ", .end_" 
+      << symbolPrefix << functionNumber << "-" << symbolPrefix 
+      << functionNumber << "\n\n";
 }




From gaeke at cs.uiuc.edu  Wed Jun  4 17:08:12 2003
From: gaeke at cs.uiuc.edu (Brian Gaeke)
Date: Wed Jun  4 17:08:12 2003
Subject: [llvm-commits] CVS: llvm/lib/Target/Sparc/FInfo.cpp Sparc.cpp
Message-ID: <200306042207.RAA17802@morpheus.cs.uiuc.edu>


Changes in directory llvm/lib/Target/Sparc:

FInfo.cpp updated: 1.3 -> 1.4
Sparc.cpp updated: 1.65 -> 1.66

---
Log message:

lib/CodeGen/Mapping/MappingInfo.cpp:
 Update file comment to contain a bunch of the overview mapping-info
  documentation previously buried within the file.
 Remove some unnecessary include/using stmts.
 Rename pass to MappingInfoCollector.
 Rewrite a lot of it so it doesn't use global instance variables and so
  it outputs into MappingInfo objects and then dumps those out, instead of going
  straight to an assembly file.
 Change name of factory to getMappingInfoCollector.
 Fold prologue & epilogue writers into MappingInfo methods.

lib/Target/Sparc/FInfo.cpp:
 Correct file comment to reflect above change

lib/Target/Sparc/Sparc.cpp:
 Change name of factory to getMappingInfoCollector.


---
Diffs of the changes:

Index: llvm/lib/Target/Sparc/FInfo.cpp
diff -u llvm/lib/Target/Sparc/FInfo.cpp:1.3 llvm/lib/Target/Sparc/FInfo.cpp:1.4
--- llvm/lib/Target/Sparc/FInfo.cpp:1.3	Mon Jun  2 22:41:07 2003
+++ llvm/lib/Target/Sparc/FInfo.cpp	Wed Jun  4 17:07:12 2003
@@ -3,8 +3,7 @@
 // This file contains a pass, FunctionInfo, used by LLC's SPARC back-end
 // which writes out two tables used by the Reoptimizer.  These tables,
 // named FunctionBB and FunctionLI, map Function numbers to the BBMIMap and
-// LMIMap tables output by the getMappingInfoForFunction (MappingInfo.cpp)
-// pass, respectively.
+// LMIMap tables output by the MappingInfo pass, respectively.
 // 
 // An LLVM Function's Function number is the index within a Module* where a
 // particular Function* can be found.


Index: llvm/lib/Target/Sparc/Sparc.cpp
diff -u llvm/lib/Target/Sparc/Sparc.cpp:1.65 llvm/lib/Target/Sparc/Sparc.cpp:1.66
--- llvm/lib/Target/Sparc/Sparc.cpp:1.65	Fri May 30 23:23:04 2003
+++ llvm/lib/Target/Sparc/Sparc.cpp	Wed Jun  4 17:07:12 2003
@@ -174,7 +174,7 @@
   if (!DisablePeephole)
     PM.add(createPeepholeOptsPass(*this));
 
-  PM.add(MappingInfoForFunction(Out));  
+  PM.add(getMappingInfoCollector(Out));  
 
   // Output assembly language to the .s file.  Assembly emission is split into
   // two parts: Function output and Global value output.  This is because




From brukman at cs.uiuc.edu  Wed Jun  4 19:40:01 2003
From: brukman at cs.uiuc.edu (Misha Brukman)
Date: Wed Jun  4 19:40:01 2003
Subject: [llvm-commits] CVS: llvm/lib/Target/Sparc/SparcV9_F3.td
Message-ID: <200306050039.TAA17424@zion.cs.uiuc.edu>


Changes in directory llvm/lib/Target/Sparc:

SparcV9_F3.td updated: 1.9 -> 1.10

---
Log message:

F3_2rd instructions were missing an 'rd' field.


---
Diffs of the changes:

Index: llvm/lib/Target/Sparc/SparcV9_F3.td
diff -u llvm/lib/Target/Sparc/SparcV9_F3.td:1.9 llvm/lib/Target/Sparc/SparcV9_F3.td:1.10
--- llvm/lib/Target/Sparc/SparcV9_F3.td:1.9	Tue Jun  3 21:26:14 2003
+++ llvm/lib/Target/Sparc/SparcV9_F3.td	Wed Jun  4 19:39:45 2003
@@ -75,14 +75,13 @@
 }
 
 // F3_rdrs1simm13 - Common class of instructions that have rd, rs1, and simm13
-class F3_rdrs1simm13 : F3_rd {
+class F3_rdrs1simm13 : F3_rdrs1 {
   bits<13> simm13;
   set Inst{12-0} = simm13;
 }
 
-
 // F3_rdrs1rs2 - Common class of instructions that have rd, rs1, and rs2 fields
-class F3_rdrs1rs2 : F3_rs1 {
+class F3_rdrs1rs2 : F3_rdrs1 {
   bits<5> rs2;
   set Inst{4-0} = rs2;
 }




From brukman at cs.uiuc.edu  Wed Jun  4 20:07:01 2003
From: brukman at cs.uiuc.edu (Misha Brukman)
Date: Wed Jun  4 20:07:01 2003
Subject: [llvm-commits] CVS: llvm/lib/Target/Sparc/SparcV9.td
Message-ID: <200306050106.UAA18315@zion.cs.uiuc.edu>


Changes in directory llvm/lib/Target/Sparc:

SparcV9.td updated: 1.15 -> 1.16

---
Log message:

All store instructions really want 'rd' in the first field.

Special cases: STFSRx and STXFSRx - they operate on predefined rd=0 or rd=1, and
expect %fsr as the parameter in assembly. They are disabled (since not used)
until an encoding, both for code generation and output, is chosen.


---
Diffs of the changes:

Index: llvm/lib/Target/Sparc/SparcV9.td
diff -u llvm/lib/Target/Sparc/SparcV9.td:1.15 llvm/lib/Target/Sparc/SparcV9.td:1.16
--- llvm/lib/Target/Sparc/SparcV9.td:1.15	Tue Jun  3 23:48:31 2003
+++ llvm/lib/Target/Sparc/SparcV9.td	Wed Jun  4 20:06:10 2003
@@ -678,7 +678,8 @@
 // Section A.51: Store Barrier - p224
 // Not currently used in the Sparc backend
 
-// Section A.52: Store Floating-point -p225
+// Section A.52: Store Floating-point - p225
+// Store instructions all want their rd register first
 def STFr  : F3_1rd<3, 0b100100, "st">;                      // st r, [r+r]
 def STFi  : F3_2rd<3, 0b100100, "st">;                      // st r, [r+i]
 def STDFr : F3_1rd<3, 0b100111, "std">;                     // std r, [r+r]
@@ -690,25 +691,31 @@
 def STQFi : F3_2rd<3, 0b100110, "stq">;                     // stq r, [r+i]
 #endif
 
+// FIXME: An encoding needs to be chosen here, because STFSRx expect rd=0,
+// while STXFSRx expect rd=1, but assembly syntax dictates %fsr as first arg.
+// These are being disabled because they aren't used in the Sparc backend.
+#if 0
 set isDeprecated = 1 in {
-  def STFSRr : F3_1<3, 0b100101, "st">;                   // st r, [r+r]
-  def STFSRi : F3_2<3, 0b100101, "st">;                   // st r, [r+i]
+  def STFSRr : F3_1<3, 0b100101, "st">;                   // st  %fsr, [r+r]
+  def STFSRi : F3_2<3, 0b100101, "st">;                   // st  %fsr, [r+i]
 }
-def STXFSRr : F3_1<3, 0b100101, "stq">;                   // stx r, [r+r]
-def STXFSRi : F3_2<3, 0b100101, "stq">;                   // stx r, [r+i]
+def STXFSRr : F3_1<3, 0b100101, "stx">;                   // stx %fsr, [r+r]
+def STXFSRi : F3_2<3, 0b100101, "stx">;                   // stx %fsr, [r+i]
+#endif
 
 // Section A.53: Store Floating-Point into Alternate Space - p227
 // Not currently used in the Sparc backend
 
 // Section A.54: Store Integer - p229
-def STBr : F3_1<3, 0b000101, "stb">;                     // stb r, [r+r]
-def STBi : F3_2<3, 0b000101, "stb">;                     // stb r, [r+i]
-def STHr : F3_1<3, 0b000110, "stb">;                     // stb r, [r+r]
-def STHi : F3_2<3, 0b000110, "stb">;                     // stb r, [r+i]
-def STWr : F3_1<3, 0b000100, "stb">;                     // stb r, [r+r]
-def STWi : F3_2<3, 0b000100, "stb">;                     // stb r, [r+i]
-def STXr : F3_1<3, 0b001110, "stb">;                     // stb r, [r+r]
-def STXi : F3_2<3, 0b001110, "stb">;                     // stb r, [r+i]
+// Store instructions all want their rd register first
+def STBr : F3_1rd<3, 0b000101, "stb">;                     // stb r, [r+r]
+def STBi : F3_2rd<3, 0b000101, "stb">;                     // stb r, [r+i]
+def STHr : F3_1rd<3, 0b000110, "sth">;                     // stb r, [r+r]
+def STHi : F3_2rd<3, 0b000110, "sth">;                     // stb r, [r+i]
+def STWr : F3_1rd<3, 0b000100, "stw">;                     // stb r, [r+r]
+def STWi : F3_2rd<3, 0b000100, "stw">;                     // stb r, [r+i]
+def STXr : F3_1rd<3, 0b001110, "stx">;                     // stb r, [r+r]
+def STXi : F3_2rd<3, 0b001110, "stx">;                     // stb r, [r+i]
 
 // Section A.55: Store Integer into Alternate Space - p231
 // Not currently used in the Sparc backend




From lattner at cs.uiuc.edu  Wed Jun  4 23:49:00 2003
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Wed Jun  4 23:49:00 2003
Subject: [llvm-commits] CVS: llvm/lib/Transforms/Instrumentation/TraceValues.cpp
Message-ID: <200306050448.XAA05624@apoc.cs.uiuc.edu>


Changes in directory llvm/lib/Transforms/Instrumentation:

TraceValues.cpp updated: 1.56 -> 1.57

---
Log message:

Use a constant expr GEP instead of an actual instruction


---
Diffs of the changes:

Index: llvm/lib/Transforms/Instrumentation/TraceValues.cpp
diff -u llvm/lib/Transforms/Instrumentation/TraceValues.cpp:1.56 llvm/lib/Transforms/Instrumentation/TraceValues.cpp:1.57
--- llvm/lib/Transforms/Instrumentation/TraceValues.cpp:1.56	Wed Apr 23 11:37:40 2003
+++ llvm/lib/Transforms/Instrumentation/TraceValues.cpp	Wed Jun  4 23:48:18 2003
@@ -231,10 +231,8 @@
   GlobalVariable *fmtVal = getStringRef(Mod, Message+getPrintfCodeFor(V)+"\n");
 
   // Turn the format string into an sbyte *
-  Instruction *GEP = 
-    new GetElementPtrInst(fmtVal,
-                          vector<Value*>(2,ConstantSInt::get(Type::LongTy, 0)),
-                          "trstrp", InsertBefore);
+  Constant *GEP =ConstantExpr::getGetElementPtr(ConstantPointerRef::get(fmtVal),
+                     vector<Constant*>(2,Constant::getNullValue(Type::LongTy)));
   
   // Insert a call to the hash function if this is a pointer value
   if (V && isa<PointerType>(V->getType()) && !DisablePtrHashing) {




From lattner at cs.uiuc.edu  Thu Jun  5 00:39:02 2003
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Thu Jun  5 00:39:02 2003
Subject: [llvm-commits] CVS: llvm/test/Regression/Jello/2003-06-04-bzip2-bug.ll
Message-ID: <200306050538.AAA06609@apoc.cs.uiuc.edu>


Changes in directory llvm/test/Regression/Jello:

2003-06-04-bzip2-bug.ll added (r1.1)

---
Log message:

New testcase for PHI handling


---
Diffs of the changes:

Index: llvm/test/Regression/Jello/2003-06-04-bzip2-bug.ll
diff -c /dev/null llvm/test/Regression/Jello/2003-06-04-bzip2-bug.ll:1.1
*** /dev/null	Thu Jun  5 00:38:40 2003
--- llvm/test/Regression/Jello/2003-06-04-bzip2-bug.ll	Thu Jun  5 00:38:30 2003
***************
*** 0 ****
--- 1,19 ----
+ ; Testcase distilled from 256.bzip2.
+ 
+ target endian = little
+ target pointersize = 32
+ 
+ int %main() {
+ entry:
+ 	br label %loopentry.0
+ 
+ loopentry.0:
+ 	%h.0 = phi int [ %tmp.2, %loopentry.0 ], [ -1, %entry ]
+ 	%tmp.2 = add int %h.0, 1
+ 	%tmp.4 = setne int %tmp.2, 0
+ 	br bool %tmp.4, label %loopentry.0, label %loopentry.1
+ 
+ loopentry.1:
+ 	%h.1 = phi int [ %tmp.2, %loopentry.0 ]
+ 	ret int %h.1
+ }




From ashukla at cs.uiuc.edu  Thu Jun  5 01:03:01 2003
From: ashukla at cs.uiuc.edu (Anand Shukla)
Date: Thu Jun  5 01:03:01 2003
Subject: [llvm-commits] CVS: llvm/lib/Transforms/Instrumentation/ProfilePaths/EdgeCode.cpp
Message-ID: <200306050602.BAA16744@niobe.cs.uiuc.edu>


Changes in directory llvm/lib/Transforms/Instrumentation/ProfilePaths:

EdgeCode.cpp updated: 1.20 -> 1.21

---
Log message:

Fixed a bug so initialization code is always inserted in main

---
Diffs of the changes:

Index: llvm/lib/Transforms/Instrumentation/ProfilePaths/EdgeCode.cpp
diff -u llvm/lib/Transforms/Instrumentation/ProfilePaths/EdgeCode.cpp:1.20 llvm/lib/Transforms/Instrumentation/ProfilePaths/EdgeCode.cpp:1.21
--- llvm/lib/Transforms/Instrumentation/ProfilePaths/EdgeCode.cpp:1.20	Wed Apr 23 11:37:41 2003
+++ llvm/lib/Transforms/Instrumentation/ProfilePaths/EdgeCode.cpp	Thu Jun  5 01:02:27 2003
@@ -293,7 +293,7 @@
 //iniArgs.push_back(ConstantSInt::get(Type::IntTy, k));
 //new CallInst(inCountMth, iniArgs, "", here);
   
-
+/*
   if(front->getParent()->getName() == "main"){
     //intialize threshold
     vector<const Type*> initialize_args;
@@ -309,6 +309,7 @@
   
     new CallInst(initialMeth, trargs, "", here);
   }
+*/
 }
 
 




From ashukla at cs.uiuc.edu  Thu Jun  5 01:03:08 2003
From: ashukla at cs.uiuc.edu (Anand Shukla)
Date: Thu Jun  5 01:03:08 2003
Subject: [llvm-commits] CVS: llvm/lib/Transforms/Instrumentation/ProfilePaths/ProfilePaths.cpp
Message-ID: <200306050602.BAA16759@niobe.cs.uiuc.edu>


Changes in directory llvm/lib/Transforms/Instrumentation/ProfilePaths:

ProfilePaths.cpp updated: 1.27 -> 1.28

---
Log message:

Fixed a bug so initialization code is always inserted in main

---
Diffs of the changes:

Index: llvm/lib/Transforms/Instrumentation/ProfilePaths/ProfilePaths.cpp
diff -u llvm/lib/Transforms/Instrumentation/ProfilePaths/ProfilePaths.cpp:1.27 llvm/lib/Transforms/Instrumentation/ProfilePaths/ProfilePaths.cpp:1.28
--- llvm/lib/Transforms/Instrumentation/ProfilePaths/ProfilePaths.cpp:1.27	Wed Apr 23 11:37:41 2003
+++ llvm/lib/Transforms/Instrumentation/ProfilePaths/ProfilePaths.cpp	Thu Jun  5 01:02:46 2003
@@ -29,10 +29,12 @@
 #include "llvm/Constants.h"
 #include "llvm/DerivedTypes.h"
 #include "llvm/iMemory.h"
+#include "llvm/iOperators.h"
+#include "llvm/iOther.h"
 #include "llvm/Module.h"
 #include "Graph.h"
 #include <fstream>
-
+#include <stdio.h>
 using std::vector;
 
 struct ProfilePaths : public FunctionPass {
@@ -61,7 +63,7 @@
 bool ProfilePaths::runOnFunction(Function &F){
 
   static int mn = -1;
-
+  static int CountCounter = 1;
   if(F.isExternal()) {
     return false;
   }
@@ -157,6 +159,38 @@
 
   //if(numPaths<=1) return false;
 
+  static GlobalVariable *threshold = NULL;
+  static bool insertedThreshold = false;
+
+  if(!insertedThreshold){
+    threshold = new GlobalVariable(Type::IntTy, false,
+                                   GlobalValue::ExternalLinkage, 0,
+                                   "reopt_threshold");
+
+    F.getParent()->getGlobalList().push_back(threshold);
+    insertedThreshold = true;
+  }
+
+  assert(threshold && "GlobalVariable threshold not defined!");
+
+
+  if(fr->getParent()->getName() == "main"){
+    //intialize threshold
+    vector<const Type*> initialize_args;
+    initialize_args.push_back(PointerType::get(Type::IntTy));
+    
+    const FunctionType *Fty = FunctionType::get(Type::VoidTy, initialize_args,
+                                                false);
+    Function *initialMeth = fr->getParent()->getParent()->getOrInsertFunction("reoptimizerInitialize", Fty);
+    assert(initialMeth && "Initialize method could not be inserted!");
+    
+    vector<Value *> trargs;
+    trargs.push_back(threshold);
+  
+    new CallInst(initialMeth, trargs, "", fr->begin());
+  }
+
+
   if(numPaths<=1 || numPaths >5000) return false;
   
 #ifdef DEBUG_PATH_PROFILES  
@@ -185,24 +219,15 @@
 
   const ArrayType *ATy = ArrayType::get(Type::IntTy, numPaths);
   Constant *initializer =  ConstantArray::get(ATy, arrayInitialize);
+  char tempChar[20];
+  sprintf(tempChar, "Count%d", CountCounter);
+  CountCounter++;
+  std::string countStr = tempChar;
   GlobalVariable *countVar = new GlobalVariable(ATy, false,
                                                 GlobalValue::InternalLinkage, 
-                                                initializer, "Count",
+                                                initializer, countStr,
                                                 F.getParent());
-  static GlobalVariable *threshold = NULL;
-  static bool insertedThreshold = false;
-
-  if(!insertedThreshold){
-    threshold = new GlobalVariable(Type::IntTy, false,
-                                   GlobalValue::ExternalLinkage, 0,
-                                   "reopt_threshold");
-
-    F.getParent()->getGlobalList().push_back(threshold);
-    insertedThreshold = true;
-  }
-
-  assert(threshold && "GlobalVariable threshold not defined!");
-
+  
   // insert initialization code in first (entry) BB
   // this includes initializing r and count
   insertInTopBB(&F.getEntryNode(),numPaths, rVar, threshold);




From ashukla at cs.uiuc.edu  Thu Jun  5 01:05:01 2003
From: ashukla at cs.uiuc.edu (Anand Shukla)
Date: Thu Jun  5 01:05:01 2003
Subject: [llvm-commits] CVS: llvm/lib/Reoptimizer/Trigger/Trigger.cpp
Message-ID: <200306050604.BAA16783@niobe.cs.uiuc.edu>


Changes in directory llvm/lib/Reoptimizer/Trigger:

Trigger.cpp updated: 1.17 -> 1.18

---
Log message:

Put in check so that it avoids forming traces with calls

---
Diffs of the changes:

Index: llvm/lib/Reoptimizer/Trigger/Trigger.cpp
diff -u llvm/lib/Reoptimizer/Trigger/Trigger.cpp:1.17 llvm/lib/Reoptimizer/Trigger/Trigger.cpp:1.18
--- llvm/lib/Reoptimizer/Trigger/Trigger.cpp:1.17	Sat May 31 21:35:01 2003
+++ llvm/lib/Reoptimizer/Trigger/Trigger.cpp	Thu Jun  5 01:04:35 2003
@@ -77,11 +77,20 @@
   std::vector<BasicBlock *> vBB; //trace of BBs
   getBBtrace(vBB, pn, funcList[mn]);//, instToErase);
 
+#ifdef FOR_DEBUG
+  printTrace(vBB, pn);
+#endif
+
   if(!isWellFormedLoop(vBB, funcList[mn])){
     cnt[pn] = -99999999;
     return;
   }
-   
+  
+  if(hasCall(vBB)){
+    cnt[pn] = -99999999;
+    return;
+  }
+
   std::pair<uint64_t, uint64_t> firstBBLimits = 
     getBasicBlockInfo(*(vBB.begin()));
 
@@ -94,12 +103,12 @@
     cnt[pn] = -9999999;
     return;
   }
-  /*
+  
   if(isThrashing(tr, startAddr)){
     cnt[pn] = -9999999;
     return;
   }
-  */
+  
   
   cnt[pn] = -9999999;
 
@@ -151,9 +160,9 @@
 
     uint64_t bbStart = bbInst.first;
     uint64_t bbEnd = bbInst.second;
-#ifdef FOR_DEBUG
+    //#ifdef FOR_DEBUG
     std::cerr<<"Start: "<<bbStart<<"\t End: "<<bbEnd<<"\n";
-#endif
+    //#endif
     //get the instructions until which to insert
     uint64_t startBB = bbStart;
 
@@ -234,10 +243,12 @@
                    && "Incorrect trace");
 
             //later change this to BA
-            cidToTop = cid + instIndex-1;
+            //cidToTop = cid + instIndex;//-1;
             unsigned int dscid = bin.insert(SECTION_TRACE, 
 					    (uint *)(intptr_t)(addr+4), 
 					    (uint *)(intptr_t)(addr+8));
+	    cidToTop = dscid;
+
 	    if(unrollCount == 1 && !bbToCid[*VBI]){
 	      bbToCid[*VBI] = dscid;
 	      bbToSec[*VBI] = secId;
@@ -268,8 +279,11 @@
 	      if(flags_br & IF_R_RS1){
 		unsigned int flags_ds = sparc_analyze(ds);
 		if(flags_ds & IF_W_RD){
-		  assert(((RD_FLD(ds, INSTR_RD)) !=(RD_FLD(br, INSTR_RS1)))
-			 && "Can not move delay slot above branch!");
+		   if((RD_FLD(ds, INSTR_RD)) == (RD_FLD(br, INSTR_RS1))){
+		    return;
+		   }
+		   //assert(((RD_FLD(ds, INSTR_RD)) !=(RD_FLD(br, INSTR_RS1)))
+		   // && "Can not move delay slot above branch!");
 		}
 	      }
 	      
@@ -307,8 +321,11 @@
 	      if(flags_br & IF_R_RS1){
 		unsigned int flags_ds = sparc_analyze(ds);
 		if(flags_ds & IF_W_RD){
-		  assert(((RD_FLD(ds, INSTR_RD)) !=(RD_FLD(br, INSTR_RS1)))
-			 && "Can not move delay slot above branch!");
+		  if((RD_FLD(ds, INSTR_RD)) == (RD_FLD(br, INSTR_RS1))){
+		    return;
+		  }
+		  //assert(((RD_FLD(ds, INSTR_RD)) !=(RD_FLD(br, INSTR_RS1)))
+		  // && "Can not move delay slot above branch!");
 		}
 	      }
 
@@ -343,10 +360,13 @@
                    getBasicBlockInfo(BI->getSuccessor(1)).first == startAddr 
                    && "Incorrect trace");
             
-            cidToTop = cid + instIndex-1;
+            //cidToTop = cid + instIndex-1;
             unsigned int dscid = bin.insert(SECTION_TRACE, 
 					    (uint *)(intptr_t)(addr+4), 
 					    (uint *)(intptr_t)(addr+8));
+	    
+	    cidToTop = dscid;
+
 	    if(unrollCount == 1 && !bbToCid[*VBI]){
 	      bbToCid[*VBI] = dscid;
 	      bbToSec[*VBI] = secId;
@@ -434,9 +454,9 @@
 
   //std::cerr<<"Cid to to "<<cidToTop<<"\n";
   unsigned nop = bin.newnop();
-  bin.move(nop, cidToTop);
-  bin.move(newBr, nop);
-
+  bin.move(newBr, cidToTop);
+  bin.move(nop, newBr);
+  
   bin.reduce();
 
   //mark instructions as pinned
@@ -460,13 +480,13 @@
 
   optimizationPasses(funcList[mn], vBB, ltrace, bin, secId, cidOffset);
 
-#ifdef FOR_DEBUG
+  //#ifdef FOR_DEBUG
   for(unsigned int i = 0; i < 2+(secId-2)*UNROLL_FACTOR; i++){
     std::cerr<<"------------SECTION "<<i<<"\n";
     bin.print(i);
   }
   std::cerr<<"-------------------------\n";
-#endif
+  //#endif
 
   uint64_t addrToOutput;
   
@@ -476,7 +496,7 @@
   bin.emit((unsigned char *)(intptr_t)addrToOutput);
 
   doFlush(addrToOutput-4, addrToOutput+bin.predict()/4);
-#ifdef FOR_DEBUG
+  //#ifdef FOR_DEBUG
   std::cerr<<"-----------\n";
-#endif
+  //#endif
 }




From ashukla at cs.uiuc.edu  Thu Jun  5 01:05:09 2003
From: ashukla at cs.uiuc.edu (Anand Shukla)
Date: Thu Jun  5 01:05:09 2003
Subject: [llvm-commits] CVS: llvm/lib/Reoptimizer/Trigger/TriggerAuxillary.cpp
Message-ID: <200306050604.BAA16795@niobe.cs.uiuc.edu>


Changes in directory llvm/lib/Reoptimizer/Trigger:

TriggerAuxillary.cpp updated: 1.4 -> 1.5

---
Log message:

Put in check so that it avoids forming traces with calls

---
Diffs of the changes:

Index: llvm/lib/Reoptimizer/Trigger/TriggerAuxillary.cpp
diff -u llvm/lib/Reoptimizer/Trigger/TriggerAuxillary.cpp:1.4 llvm/lib/Reoptimizer/Trigger/TriggerAuxillary.cpp:1.5
--- llvm/lib/Reoptimizer/Trigger/TriggerAuxillary.cpp:1.4	Sat May 31 21:35:06 2003
+++ llvm/lib/Reoptimizer/Trigger/TriggerAuxillary.cpp	Thu Jun  5 01:04:42 2003
@@ -21,6 +21,7 @@
 #include "llvm/iOther.h"
 #include "llvm/iPHINode.h"
 #include "llvm/iMemory.h"
+#include "llvm/iOperators.h"
 #include "llvm/Support/CFG.h"
 #include "TriggerAuxillary.h"
 #include <iostream>
@@ -608,4 +609,20 @@
     }
   }
   return true;
+}
+
+bool hasCall(vector<BasicBlock *> &vBB){
+  for(vector<BasicBlock *>::iterator VBI = vBB.begin(), VBE = vBB.end(); 
+      VBI != VBE; ++VBI){
+    for(BasicBlock::iterator BI = (*VBI)->begin(), BE = (*VBI)->end(); 
+	BI != BE; ++BI){
+      //std::cerr<<"Looking at:\n";
+      //std::cerr<<*BI;
+      if(CallInst *ci = dyn_cast<CallInst>(&*BI)){
+	//std::cerr<<"Found\n";
+	return true;
+      }
+    }
+  }
+  return false;
 }




From ashukla at cs.uiuc.edu  Thu Jun  5 01:05:14 2003
From: ashukla at cs.uiuc.edu (Anand Shukla)
Date: Thu Jun  5 01:05:14 2003
Subject: [llvm-commits] CVS: llvm/lib/Reoptimizer/Trigger/TriggerAuxillary.h
Message-ID: <200306050604.BAA16802@niobe.cs.uiuc.edu>


Changes in directory llvm/lib/Reoptimizer/Trigger:

TriggerAuxillary.h updated: 1.2 -> 1.3

---
Log message:

Put in check so that it avoids forming traces with calls

---
Diffs of the changes:

Index: llvm/lib/Reoptimizer/Trigger/TriggerAuxillary.h
diff -u llvm/lib/Reoptimizer/Trigger/TriggerAuxillary.h:1.2 llvm/lib/Reoptimizer/Trigger/TriggerAuxillary.h:1.3
--- llvm/lib/Reoptimizer/Trigger/TriggerAuxillary.h:1.2	Sat May 31 21:35:09 2003
+++ llvm/lib/Reoptimizer/Trigger/TriggerAuxillary.h	Thu Jun  5 01:04:47 2003
@@ -75,4 +75,6 @@
 
 bool isWellFormedLoop(vector<BasicBlock *> &vBB, Function *f);
 
+bool hasCall(vector<BasicBlock *> &vBB);
+
 #endif




From ashukla at cs.uiuc.edu  Thu Jun  5 01:07:01 2003
From: ashukla at cs.uiuc.edu (Anand Shukla)
Date: Thu Jun  5 01:07:01 2003
Subject: [llvm-commits] CVS: llvm/lib/Reoptimizer/BinInterface/analyze.cpp sparcdis.cpp
Message-ID: <200306050606.BAA16819@niobe.cs.uiuc.edu>


Changes in directory llvm/lib/Reoptimizer/BinInterface:

analyze.cpp updated: 1.9 -> 1.10
sparcdis.cpp updated: 1.11 -> 1.12

---
Log message:

Added check for FP BRanch and FPCMP

---
Diffs of the changes:

Index: llvm/lib/Reoptimizer/BinInterface/analyze.cpp
diff -u llvm/lib/Reoptimizer/BinInterface/analyze.cpp:1.9 llvm/lib/Reoptimizer/BinInterface/analyze.cpp:1.10
--- llvm/lib/Reoptimizer/BinInterface/analyze.cpp:1.9	Sat May 31 17:07:33 2003
+++ llvm/lib/Reoptimizer/BinInterface/analyze.cpp	Thu Jun  5 01:06:03 2003
@@ -76,6 +76,11 @@
       return false;
     }
   }
+  if(RD_FLD(instr,INSTR_OP)==OP_2){
+    if(RD_FLD(instr, INSTR_OP3) == OP3_FCMP)
+      return true;
+  }
+  
   return false;
 }
 


Index: llvm/lib/Reoptimizer/BinInterface/sparcdis.cpp
diff -u llvm/lib/Reoptimizer/BinInterface/sparcdis.cpp:1.11 llvm/lib/Reoptimizer/BinInterface/sparcdis.cpp:1.12
--- llvm/lib/Reoptimizer/BinInterface/sparcdis.cpp:1.11	Sat May 31 17:08:16 2003
+++ llvm/lib/Reoptimizer/BinInterface/sparcdis.cpp	Thu Jun  5 01:06:03 2003
@@ -62,11 +62,13 @@
          sparc_printop_rrd(instr, labelrd);
       }
    }
-   else if (RD_FLD(instr, INSTR_OP2)==OP2_BICC)
-   {
-      printf("b%s disp:%08X",icond_names[RD_FLD(instr, INSTR_COND_H)], SIGN_EXTEND(RD_FLD(instr,INSTR_DISP22),22));
+   else if (RD_FLD(instr, INSTR_OP2)==OP2_BICC || RD_FLD(instr, INSTR_OP2)==OP2_FB)
+     {
+       printf("b%s disp:%08X",icond_names[RD_FLD(instr, INSTR_COND_H)], 
+	      SIGN_EXTEND(RD_FLD(instr,INSTR_DISP22),22));
    }
-   else if (RD_FLD(instr, INSTR_OP2)==OP2_BPICC)
+   else if (RD_FLD(instr, INSTR_OP2)==OP2_BPICC || 
+	    RD_FLD(instr, INSTR_OP2)==OP2_FBP)
    {
       printf("b%s",icond_names[RD_FLD(instr, INSTR_COND_H)]);
    }




From lattner at cs.uiuc.edu  Thu Jun  5 11:59:02 2003
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Thu Jun  5 11:59:02 2003
Subject: [llvm-commits] CVS: llvm/test/Regression/Jello/2003-06-05-PHIBug.ll
Message-ID: <200306051658.LAA14414@apoc.cs.uiuc.edu>


Changes in directory llvm/test/Regression/Jello:

2003-06-05-PHIBug.ll added (r1.1)

---
Log message:

New testcase, the JIT currently handles this right, I just don't want to
reintroduce a bug that didn't have a testcase.


---
Diffs of the changes:

Index: llvm/test/Regression/Jello/2003-06-05-PHIBug.ll
diff -c /dev/null llvm/test/Regression/Jello/2003-06-05-PHIBug.ll:1.1
*** /dev/null	Thu Jun  5 11:58:05 2003
--- llvm/test/Regression/Jello/2003-06-05-PHIBug.ll	Thu Jun  5 11:57:55 2003
***************
*** 0 ****
--- 1,16 ----
+ ; Testcase distilled from 256.bzip2.
+ 
+ target endian = little
+ target pointersize = 32
+ 
+ int %main() {
+ entry:
+ 	%X = add int 1, -1
+ 	br label %Next
+ 
+ Next:
+ 	%A = phi int [ %X, %entry ]
+ 	%B = phi int [ %X, %entry ]
+ 	%C = phi int [ %X, %entry ]
+ 	ret int %C
+ }




From lattner at cs.uiuc.edu  Thu Jun  5 12:16:01 2003
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Thu Jun  5 12:16:01 2003
Subject: [llvm-commits] CVS: llvm/lib/CodeGen/PHIElimination.cpp
Message-ID: <200306051715.MAA15385@apoc.cs.uiuc.edu>


Changes in directory llvm/lib/CodeGen:

PHIElimination.cpp updated: 1.9 -> 1.10

---
Log message:

Fix bug: Jello/2003-06-04-bzip2-bug.ll


---
Diffs of the changes:

Index: llvm/lib/CodeGen/PHIElimination.cpp
diff -u llvm/lib/CodeGen/PHIElimination.cpp:1.9 llvm/lib/CodeGen/PHIElimination.cpp:1.10
--- llvm/lib/CodeGen/PHIElimination.cpp:1.9	Mon May 26 19:05:17 2003
+++ llvm/lib/CodeGen/PHIElimination.cpp	Thu Jun  5 12:15:04 2003
@@ -193,14 +193,16 @@
           //
           LiveVariables::VarInfo &InRegVI = LV->getVarInfo(SrcReg);
 
-          // Loop over all of the successors of the basic block, checking to
-          // see if the value is either live in the block, or if it is killed
-          // in the block.
+          // Loop over all of the successors of the basic block, checking to see
+          // if the value is either live in the block, or if it is killed in the
+          // block.  Also check to see if this register is in use by another PHI
+          // node which has not yet been eliminated.  If so, it will be killed
+          // at an appropriate point later.
           //
           bool ValueIsLive = false;
           BasicBlock *BB = opBlock.getBasicBlock();
           for (succ_iterator SI = succ_begin(BB), E = succ_end(BB);
-               SI != E; ++SI) {
+               SI != E && !ValueIsLive; ++SI) {
             const std::pair<MachineBasicBlock*, unsigned> &
               SuccInfo = LV->getBasicBlockInfo(*SI);
             
@@ -219,32 +221,28 @@
                 ValueIsLive = true;
                 break;
               }
+
+            // Is it used by any PHI instructions in this block?
+            if (ValueIsLive) break;
+
+            // Loop over all of the PHIs in this successor, checking to see if
+            // the register is being used...
+            for (MachineBasicBlock::iterator BBI = MBB->begin(), E=MBB->end();
+                 BBI != E && (*BBI)->getOpcode() == TargetInstrInfo::PHI;
+                 ++BBI)
+              for (unsigned i = 1, e = (*BBI)->getNumOperands(); i < e; i += 2)
+                if ((*BBI)->getOperand(i).getReg() == SrcReg) {
+                  ValueIsLive = true;
+                  break;
+                }
           }
           
           // Okay, if we now know that the value is not live out of the block,
           // we can add a kill marker to the copy we inserted saying that it
           // kills the incoming value!
           //
-          if (!ValueIsLive) {
-            // One more complication to worry about.  There may actually be
-            // multiple PHI nodes using this value on this branch.  If we aren't
-            // careful, the first PHI node will end up killing the value, not
-            // letting it get the to the copy for the final PHI node in the
-            // block.  Therefore we have to check to see if there is already a
-            // kill in this block, and if so, extend the lifetime to our new
-            // copy.
-            //
-            for (unsigned i = 0, e = InRegVI.Kills.size(); i != e; ++i)
-              if (InRegVI.Kills[i].first == &opBlock) {
-                std::pair<LiveVariables::killed_iterator,
-                          LiveVariables::killed_iterator> Range
-                  = LV->killed_range(InRegVI.Kills[i].second);
-                LV->removeVirtualRegistersKilled(Range.first, Range.second);
-                break;
-              }
-
+          if (!ValueIsLive)
             LV->addVirtualRegisterKilled(SrcReg, &opBlock, *(I-1));
-          }
         }
       }
     }




From lattner at cs.uiuc.edu  Thu Jun  5 13:30:02 2003
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Thu Jun  5 13:30:02 2003
Subject: [llvm-commits] CVS: llvm/lib/Target/X86/InstSelectSimple.cpp
Message-ID: <200306051829.NAA19027@apoc.cs.uiuc.edu>


Changes in directory llvm/lib/Target/X86:

InstSelectSimple.cpp updated: 1.104 -> 1.105

---
Log message:

Special case simple binary operator X op C

  This avoid generating a register to hold C, which in turn speeds up the
  register allocator by a lot: ~9% on 164.gzip and ~17% on 256.bzip2.  This
  also speeds up other passes.  This also speeds up execution of the program 
  marginally, and makes the asm much easier to read. :)


---
Diffs of the changes:

Index: llvm/lib/Target/X86/InstSelectSimple.cpp
diff -u llvm/lib/Target/X86/InstSelectSimple.cpp:1.104 llvm/lib/Target/X86/InstSelectSimple.cpp:1.105
--- llvm/lib/Target/X86/InstSelectSimple.cpp:1.104	Tue Jun  3 10:41:58 2003
+++ llvm/lib/Target/X86/InstSelectSimple.cpp	Thu Jun  5 13:28:55 2003
@@ -983,36 +983,64 @@
                                      Value *Op0, Value *Op1,
                                      unsigned OperatorClass,unsigned TargetReg){
   unsigned Class = getClassB(Op0->getType());
+  if (!isa<ConstantInt>(Op1) || Class == cLong) {
+    static const unsigned OpcodeTab[][4] = {
+      // Arithmetic operators
+      { X86::ADDrr8, X86::ADDrr16, X86::ADDrr32, X86::FpADD },  // ADD
+      { X86::SUBrr8, X86::SUBrr16, X86::SUBrr32, X86::FpSUB },  // SUB
+      
+      // Bitwise operators
+      { X86::ANDrr8, X86::ANDrr16, X86::ANDrr32, 0 },  // AND
+      { X86:: ORrr8, X86:: ORrr16, X86:: ORrr32, 0 },  // OR
+      { X86::XORrr8, X86::XORrr16, X86::XORrr32, 0 },  // XOR
+    };
+    
+    bool isLong = false;
+    if (Class == cLong) {
+      isLong = true;
+      Class = cInt;          // Bottom 32 bits are handled just like ints
+    }
+    
+    unsigned Opcode = OpcodeTab[OperatorClass][Class];
+    assert(Opcode && "Floating point arguments to logical inst?");
+    unsigned Op0r = getReg(Op0, BB, IP);
+    unsigned Op1r = getReg(Op1, BB, IP);
+    BMI(BB, IP, Opcode, 2, TargetReg).addReg(Op0r).addReg(Op1r);
+    
+    if (isLong) {        // Handle the upper 32 bits of long values...
+      static const unsigned TopTab[] = {
+        X86::ADCrr32, X86::SBBrr32, X86::ANDrr32, X86::ORrr32, X86::XORrr32
+      };
+      BMI(BB, IP, TopTab[OperatorClass], 2,
+          TargetReg+1).addReg(Op0r+1).addReg(Op1r+1);
+    }
+  } else {
+    // Special case: op Reg, <const>
+    ConstantInt *Op1C = cast<ConstantInt>(Op1);
 
-  static const unsigned OpcodeTab[][4] = {
-    // Arithmetic operators
-    { X86::ADDrr8, X86::ADDrr16, X86::ADDrr32, X86::FpADD },  // ADD
-    { X86::SUBrr8, X86::SUBrr16, X86::SUBrr32, X86::FpSUB },  // SUB
-
-    // Bitwise operators
-    { X86::ANDrr8, X86::ANDrr16, X86::ANDrr32, 0 },  // AND
-    { X86:: ORrr8, X86:: ORrr16, X86:: ORrr32, 0 },  // OR
-    { X86::XORrr8, X86::XORrr16, X86::XORrr32, 0 },  // XOR
-  };
+    static const unsigned OpcodeTab[][3] = {
+      // Arithmetic operators
+      { X86::ADDri8, X86::ADDri16, X86::ADDri32 },  // ADD
+      { X86::SUBri8, X86::SUBri16, X86::SUBri32 },  // SUB
+      
+      // Bitwise operators
+      { X86::ANDri8, X86::ANDri16, X86::ANDri32 },  // AND
+      { X86:: ORri8, X86:: ORri16, X86:: ORri32 },  // OR
+      { X86::XORri8, X86::XORri16, X86::XORri32 },  // XOR
+    };
 
-  bool isLong = false;
-  if (Class == cLong) {
-    isLong = true;
-    Class = cInt;          // Bottom 32 bits are handled just like ints
-  }
-  
-  unsigned Opcode = OpcodeTab[OperatorClass][Class];
-  assert(Opcode && "Floating point arguments to logical inst?");
-  unsigned Op0r = getReg(Op0, BB, IP);
-  unsigned Op1r = getReg(Op1, BB, IP);
-  BMI(BB, IP, Opcode, 2, TargetReg).addReg(Op0r).addReg(Op1r);
+    assert(Class < 3 && "General code handles 64-bit integer types!");
+    unsigned Opcode = OpcodeTab[OperatorClass][Class];
+    unsigned Op0r = getReg(Op0, BB, IP);
+    uint64_t Op1v;
+    if (ConstantSInt *CSI = dyn_cast<ConstantSInt>(Op1C))
+      Op1v = CSI->getValue();
+    else
+      Op1v = cast<ConstantUInt>(Op1C)->getValue();
 
-  if (isLong) {        // Handle the upper 32 bits of long values...
-    static const unsigned TopTab[] = {
-      X86::ADCrr32, X86::SBBrr32, X86::ANDrr32, X86::ORrr32, X86::XORrr32
-    };
-    BMI(BB, IP, TopTab[OperatorClass], 2,
-        TargetReg+1).addReg(Op0r+1).addReg(Op1r+1);
+    // Mask off any upper bits of the constant, if there are any...
+    Op1v &= (1ULL << (8 << Class)) - 1;
+    BMI(BB, IP, Opcode, 2, TargetReg).addReg(Op0r).addZImm(Op1v);
   }
 }
 




From lattner at cs.uiuc.edu  Thu Jun  5 13:30:07 2003
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Thu Jun  5 13:30:07 2003
Subject: [llvm-commits] CVS: llvm/lib/Target/X86/X86InstrInfo.def
Message-ID: <200306051829.NAA19032@apoc.cs.uiuc.edu>


Changes in directory llvm/lib/Target/X86:

X86InstrInfo.def updated: 1.55 -> 1.56

---
Log message:

Add instructions for (add|sub|and|or|xor)ri(8|16|32)


---
Diffs of the changes:

Index: llvm/lib/Target/X86/X86InstrInfo.def
diff -u llvm/lib/Target/X86/X86InstrInfo.def:1.55 llvm/lib/Target/X86/X86InstrInfo.def:1.56
--- llvm/lib/Target/X86/X86InstrInfo.def:1.55	Sat May 31 22:37:46 2003
+++ llvm/lib/Target/X86/X86InstrInfo.def	Thu Jun  5 13:25:08 2003
@@ -142,15 +142,25 @@
 // Arithmetic instructions
 I(ADDrr8      , "add",  0x00, M_2_ADDR_FLAG, X86II::MRMDestReg, NoIR, NoIR)                 // R8  += R8
 I(ADDrr16     , "add",  0x01, M_2_ADDR_FLAG, X86II::MRMDestReg | X86II::OpSize, NoIR, NoIR) // R16 += R16
-I(ADDrr32     , "add",  0x01, M_2_ADDR_FLAG, X86II::MRMDestReg, NoIR, NoIR)                 // R32 += R32
-I(ADDri32     , "add",  0x81, M_2_ADDR_FLAG, X86II::MRMS0r | X86II::Arg32, NoIR, NoIR)      // R32 += imm32
+I(ADDrr32     , "add",  0x01, M_2_ADDR_FLAG, X86II::MRMDestReg | X86II::Arg32, NoIR, NoIR)  // R32 += R32
+
+I(ADDri8      , "add",  0x80, M_2_ADDR_FLAG, X86II::MRMS0r     | X86II::Arg8, NoIR, NoIR)  // R8  += imm8
+I(ADDri16     , "add",  0x81, M_2_ADDR_FLAG, X86II::MRMS0r     | X86II::OpSize | X86II::Arg16, NoIR, NoIR) // R16 += imm16
+I(ADDri32     , "add",  0x81, M_2_ADDR_FLAG, X86II::MRMS0r     | X86II::Arg32, NoIR, NoIR)  // R32 += imm32
+
 I(ADCrr32     , "adc",  0x11, M_2_ADDR_FLAG, X86II::MRMDestReg | X86II::Arg32, NoIR, NoIR)  // R32 += R32 + Carry
 
 I(SUBrr8      , "sub",  0x28, M_2_ADDR_FLAG, X86II::MRMDestReg, NoIR, NoIR)                 // R8  -= R8
 I(SUBrr16     , "sub",  0x29, M_2_ADDR_FLAG, X86II::MRMDestReg | X86II::OpSize, NoIR, NoIR) // R16 -= R16
 I(SUBrr32     , "sub",  0x29, M_2_ADDR_FLAG, X86II::MRMDestReg, NoIR, NoIR)                 // R32 -= R32
+
+I(SUBri8      , "sub",  0x80, M_2_ADDR_FLAG, X86II::MRMS5r | X86II::Arg8 , NoIR, NoIR)      // R8  -= imm8
+I(SUBri16     , "sub",  0x81, M_2_ADDR_FLAG, X86II::MRMS5r | X86II::OpSize | X86II::Arg16, NoIR, NoIR)  // R16 -= imm16
 I(SUBri32     , "sub",  0x81, M_2_ADDR_FLAG, X86II::MRMS5r | X86II::Arg32, NoIR, NoIR)      // R32 -= imm32
+
 I(SBBrr32     , "sbb",  0x19, M_2_ADDR_FLAG, X86II::MRMDestReg | X86II::Arg32, NoIR, NoIR)  // R32 -= R32 + Carry
+
+
 I(MULr8       , "mul",  0xF6,             0, X86II::MRMS4r | X86II::Void, O_AL, O_AX)       // AX   = AL*R8
 I(MULr16      , "mul",  0xF7,             0, X86II::MRMS4r | X86II::Void |                  // DX:AX= AX*R16
                                               X86II::OpSize, O_AX, T_AXDX)
@@ -174,13 +184,24 @@
 I(ANDrr8      , "and",   0x20, M_2_ADDR_FLAG, X86II::MRMDestReg, NoIR, NoIR)                 // R8  &= R8
 I(ANDrr16     , "and",   0x21, M_2_ADDR_FLAG, X86II::MRMDestReg | X86II::OpSize, NoIR, NoIR) // R16 &= R16
 I(ANDrr32     , "and",   0x21, M_2_ADDR_FLAG, X86II::MRMDestReg, NoIR, NoIR)                 // R32 &= R32
+I(ANDri8      , "and",   0x80, M_2_ADDR_FLAG, X86II::MRMS4r     | X86II::Arg8 , NoIR, NoIR)  // R8  &= imm8
+I(ANDri16     , "and",   0x81, M_2_ADDR_FLAG, X86II::MRMS4r     | X86II::Arg16 | X86II::OpSize, NoIR, NoIR)  // R16 &= imm16
 I(ANDri32     , "and",   0x81, M_2_ADDR_FLAG, X86II::MRMS4r     | X86II::Arg32, NoIR, NoIR)  // R32 &= imm32
+
+
 I(ORrr8       , "or",    0x08, M_2_ADDR_FLAG, X86II::MRMDestReg, NoIR, NoIR)                 // R8  |= R8
 I(ORrr16      , "or",    0x09, M_2_ADDR_FLAG, X86II::MRMDestReg | X86II::OpSize, NoIR, NoIR) // R16 |= R16
 I(ORrr32      , "or",    0x09, M_2_ADDR_FLAG, X86II::MRMDestReg, NoIR, NoIR)                 // R32 |= R32
+I(ORri8       , "or",    0x80, M_2_ADDR_FLAG, X86II::MRMS1r     | X86II::Arg8 , NoIR, NoIR)  // R8  |= imm8
+I(ORri16      , "or",    0x81, M_2_ADDR_FLAG, X86II::MRMS1r     | X86II::Arg16 | X86II::OpSize, NoIR, NoIR)  // R16 |= imm16
+I(ORri32      , "or",    0x81, M_2_ADDR_FLAG, X86II::MRMS1r     | X86II::Arg32, NoIR, NoIR)  // R32 |= imm32
+
 I(XORrr8      , "xor",   0x30, M_2_ADDR_FLAG, X86II::MRMDestReg, NoIR, NoIR)                 // R8  ^= R8
 I(XORrr16     , "xor",   0x31, M_2_ADDR_FLAG, X86II::MRMDestReg | X86II::OpSize, NoIR, NoIR) // R16 ^= R16
 I(XORrr32     , "xor",   0x31, M_2_ADDR_FLAG, X86II::MRMDestReg, NoIR, NoIR)                 // R32 ^= R32
+I(XORri8      , "xor",   0x80, M_2_ADDR_FLAG, X86II::MRMS6r     | X86II::Arg8 , NoIR, NoIR)  // R8  ^= imm8
+I(XORri16     , "xor",   0x81, M_2_ADDR_FLAG, X86II::MRMS6r     | X86II::Arg16 | X86II::OpSize, NoIR, NoIR)  // R16 ^= imm16
+I(XORri32     , "xor",   0x81, M_2_ADDR_FLAG, X86II::MRMS6r     | X86II::Arg32, NoIR, NoIR)  // R32 ^= imm32
 
 // test instructions are just like and, except they don't generate a result (but
 // they do set flags).




From lattner at cs.uiuc.edu  Thu Jun  5 14:31:02 2003
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Thu Jun  5 14:31:02 2003
Subject: [llvm-commits] CVS: llvm/lib/Target/X86/InstSelectSimple.cpp X86InstrInfo.def
Message-ID: <200306051930.OAA20195@apoc.cs.uiuc.edu>


Changes in directory llvm/lib/Target/X86:

InstSelectSimple.cpp updated: 1.105 -> 1.106
X86InstrInfo.def updated: 1.56 -> 1.57

---
Log message:

Implement generation of cmp R, C to not use an extra register


---
Diffs of the changes:

Index: llvm/lib/Target/X86/InstSelectSimple.cpp
diff -u llvm/lib/Target/X86/InstSelectSimple.cpp:1.105 llvm/lib/Target/X86/InstSelectSimple.cpp:1.106
--- llvm/lib/Target/X86/InstSelectSimple.cpp:1.105	Thu Jun  5 13:28:55 2003
+++ llvm/lib/Target/X86/InstSelectSimple.cpp	Thu Jun  5 14:30:30 2003
@@ -579,26 +579,47 @@
   // The arguments are already supposed to be of the same type.
   const Type *CompTy = Op0->getType();
   bool isSigned = CompTy->isSigned();
-  unsigned reg1 = getReg(Op0);
-  unsigned reg2 = getReg(Op1);
-
   unsigned Class = getClassB(CompTy);
+  unsigned Op0r = getReg(Op0);
+
+  // Special case handling of: cmp R, i
+  if (Class == cByte || Class == cShort || Class == cInt)
+    if (ConstantInt *CI = dyn_cast<ConstantInt>(Op1)) {
+      uint64_t Op1v;
+      if (ConstantSInt *CSI = dyn_cast<ConstantSInt>(CI))
+        Op1v = CSI->getValue();
+      else
+        Op1v = cast<ConstantUInt>(CI)->getValue();
+      // Mask off any upper bits of the constant, if there are any...
+      Op1v &= (1ULL << (8 << Class)) - 1;
+
+      switch (Class) {
+      case cByte:  BuildMI(BB, X86::CMPri8, 2).addReg(Op0r).addZImm(Op1v);break;
+      case cShort: BuildMI(BB, X86::CMPri16,2).addReg(Op0r).addZImm(Op1v);break;
+      case cInt:   BuildMI(BB, X86::CMPri32,2).addReg(Op0r).addZImm(Op1v);break;
+      default:
+        assert(0 && "Invalid class!");
+      }
+      return isSigned;
+    }
+
+  unsigned Op1r = getReg(Op1);
   switch (Class) {
   default: assert(0 && "Unknown type class!");
     // Emit: cmp <var1>, <var2> (do the comparison).  We can
     // compare 8-bit with 8-bit, 16-bit with 16-bit, 32-bit with
     // 32-bit.
   case cByte:
-    BuildMI(BB, X86::CMPrr8, 2).addReg(reg1).addReg(reg2);
+    BuildMI(BB, X86::CMPrr8, 2).addReg(Op0r).addReg(Op1r);
     break;
   case cShort:
-    BuildMI(BB, X86::CMPrr16, 2).addReg(reg1).addReg(reg2);
+    BuildMI(BB, X86::CMPrr16, 2).addReg(Op0r).addReg(Op1r);
     break;
   case cInt:
-    BuildMI(BB, X86::CMPrr32, 2).addReg(reg1).addReg(reg2);
+    BuildMI(BB, X86::CMPrr32, 2).addReg(Op0r).addReg(Op1r);
     break;
   case cFP:
-    BuildMI(BB, X86::FpUCOM, 2).addReg(reg1).addReg(reg2);
+    BuildMI(BB, X86::FpUCOM, 2).addReg(Op0r).addReg(Op1r);
     BuildMI(BB, X86::FNSTSWr8, 0);
     BuildMI(BB, X86::SAHF, 1);
     isSigned = false;   // Compare with unsigned operators
@@ -609,8 +630,8 @@
       unsigned LoTmp = makeAnotherReg(Type::IntTy);
       unsigned HiTmp = makeAnotherReg(Type::IntTy);
       unsigned FinalTmp = makeAnotherReg(Type::IntTy);
-      BuildMI(BB, X86::XORrr32, 2, LoTmp).addReg(reg1).addReg(reg2);
-      BuildMI(BB, X86::XORrr32, 2, HiTmp).addReg(reg1+1).addReg(reg2+1);
+      BuildMI(BB, X86::XORrr32, 2, LoTmp).addReg(Op0r).addReg(Op1r);
+      BuildMI(BB, X86::XORrr32, 2, HiTmp).addReg(Op0r+1).addReg(Op1r+1);
       BuildMI(BB, X86::ORrr32,  2, FinalTmp).addReg(LoTmp).addReg(HiTmp);
       break;  // Allow the sete or setne to be generated from flags set by OR
     } else {
@@ -627,9 +648,9 @@
       // classes!  Until then, hardcode registers so that we can deal with their
       // aliases (because we don't have conditional byte moves).
       //
-      BuildMI(BB, X86::CMPrr32, 2).addReg(reg1).addReg(reg2);
+      BuildMI(BB, X86::CMPrr32, 2).addReg(Op0r).addReg(Op1r);
       BuildMI(BB, SetCCOpcodeTab[0][OpNum], 0, X86::AL);
-      BuildMI(BB, X86::CMPrr32, 2).addReg(reg1+1).addReg(reg2+1);
+      BuildMI(BB, X86::CMPrr32, 2).addReg(Op0r+1).addReg(Op1r+1);
       BuildMI(BB, SetCCOpcodeTab[isSigned][OpNum], 0, X86::BL);
       BuildMI(BB, X86::CMOVErr16, 2, X86::BX).addReg(X86::BX).addReg(X86::AX);
       // NOTE: visitSetCondInst knows that the value is dumped into the BL


Index: llvm/lib/Target/X86/X86InstrInfo.def
diff -u llvm/lib/Target/X86/X86InstrInfo.def:1.56 llvm/lib/Target/X86/X86InstrInfo.def:1.57
--- llvm/lib/Target/X86/X86InstrInfo.def:1.56	Thu Jun  5 13:25:08 2003
+++ llvm/lib/Target/X86/X86InstrInfo.def	Thu Jun  5 14:30:30 2003
@@ -263,7 +263,9 @@
 I(CMPrr8      , "cmpb",  0x38,             0, X86II::Void | X86II::MRMDestReg                , NoIR, NoIR) // compare R8,R8
 I(CMPrr16     , "cmpw",  0x39,             0, X86II::Void | X86II::MRMDestReg | X86II::OpSize, NoIR, NoIR) // compare R16,R16
 I(CMPrr32     , "cmpl",  0x39,             0, X86II::Void | X86II::MRMDestReg                , NoIR, NoIR) // compare R32,R32
-I(CMPri8      , "cmp",   0x80,             0, X86II::Void | X86II::MRMS7r     | X86II::Arg8  , NoIR, NoIR) // compare R8, imm8
+I(CMPri8      , "cmpb",  0x80,             0, X86II::Void | X86II::MRMS7r     | X86II::Arg8  , NoIR, NoIR) // compare R8, imm8
+I(CMPri16     , "cmpw",  0x81,             0, X86II::Void | X86II::MRMS7r     | X86II::Arg16 | X86II::OpSize, NoIR, NoIR) // compare R8, imm8
+I(CMPri32     , "cmpl",  0x81,             0, X86II::Void | X86II::MRMS7r     | X86II::Arg32 , NoIR, NoIR) // compare R8, imm8
 
 // Sign extenders (first 3 are good for DIV/IDIV; the others are more general)
 I(CBW         , "cbw",   0x98,             0, X86II::Void | X86II::RawFrm | X86II::OpSize, O_AL, O_AH)     // AX = signext(AL)




From lattner at cs.uiuc.edu  Thu Jun  5 15:12:01 2003
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Thu Jun  5 15:12:01 2003
Subject: [llvm-commits] CVS: llvm/test/Regression/Transforms/InstCombine/set.ll
Message-ID: <200306052011.PAA20464@apoc.cs.uiuc.edu>


Changes in directory llvm/test/Regression/Transforms/InstCombine:

set.ll updated: 1.7 -> 1.8

---
Log message:

Test seteq AND setne


---
Diffs of the changes:

Index: llvm/test/Regression/Transforms/InstCombine/set.ll
diff -u llvm/test/Regression/Transforms/InstCombine/set.ll:1.7 llvm/test/Regression/Transforms/InstCombine/set.ll:1.8
--- llvm/test/Regression/Transforms/InstCombine/set.ll:1.7	Tue Jun  3 23:47:40 2003
+++ llvm/test/Regression/Transforms/InstCombine/set.ll	Thu Jun  5 15:11:19 2003
@@ -81,9 +81,9 @@
 ; These instructions can be turned into cast-to-bool
 bool %test15(sbyte %A, short %A, int %A, long %A) {
 	%B1 = setne sbyte %A, 0
-	%B2 = setne short %A, 0
+	%B2 = seteq short %A, 0
 	%B3 = setne int %A, 0
-	%B4 = setne long %A, 0
+	%B4 = seteq long %A, 0
 	%C1 = or bool %B1, %B2
 	%C2 = or bool %B3, %B4
 	%D = or bool %C1, %C2




From lattner at cs.uiuc.edu  Thu Jun  5 15:13:01 2003
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Thu Jun  5 15:13:01 2003
Subject: [llvm-commits] CVS: llvm/test/Regression/Transforms/InstCombine/2003-06-05-BranchInvertInfLoop.ll
Message-ID: <200306052012.PAA20480@apoc.cs.uiuc.edu>


Changes in directory llvm/test/Regression/Transforms/InstCombine:

2003-06-05-BranchInvertInfLoop.ll added (r1.1)

---
Log message:

New testcase


---
Diffs of the changes:

Index: llvm/test/Regression/Transforms/InstCombine/2003-06-05-BranchInvertInfLoop.ll
diff -c /dev/null llvm/test/Regression/Transforms/InstCombine/2003-06-05-BranchInvertInfLoop.ll:1.1
*** /dev/null	Thu Jun  5 15:12:42 2003
--- llvm/test/Regression/Transforms/InstCombine/2003-06-05-BranchInvertInfLoop.ll	Thu Jun  5 15:12:32 2003
***************
*** 0 ****
--- 1,14 ----
+ ; This testcase causes an infinite loop in the instruction combiner,
+ ; because it things that the constant value is a not expression... and 
+ ; constantly inverts the branch back and forth.
+ ;
+ ; RUN: as < %s | opt -instcombine -disable-output
+ 
+ ubyte %test19(bool %c) {
+         br bool true, label %True, label %False
+ True:
+         ret ubyte 1
+ False:
+         ret ubyte 3
+ }
+ 




From lattner at cs.uiuc.edu  Thu Jun  5 15:14:02 2003
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Thu Jun  5 15:14:02 2003
Subject: [llvm-commits] CVS: llvm/lib/Transforms/Scalar/InstructionCombining.cpp
Message-ID: <200306052013.PAA20491@apoc.cs.uiuc.edu>


Changes in directory llvm/lib/Transforms/Scalar:

InstructionCombining.cpp updated: 1.88 -> 1.89

---
Log message:

Fix bug: InstCombine/2003-06-05-BranchInvertInfLoop.ll


---
Diffs of the changes:

Index: llvm/lib/Transforms/Scalar/InstructionCombining.cpp
diff -u llvm/lib/Transforms/Scalar/InstructionCombining.cpp:1.88 llvm/lib/Transforms/Scalar/InstructionCombining.cpp:1.89
--- llvm/lib/Transforms/Scalar/InstructionCombining.cpp:1.88	Wed Jun  4 00:10:11 2003
+++ llvm/lib/Transforms/Scalar/InstructionCombining.cpp	Thu Jun  5 15:12:51 2003
@@ -1072,7 +1072,7 @@
 
 Instruction *InstCombiner::visitBranchInst(BranchInst &BI) {
   // Change br (not X), label True, label False to: br X, label False, True
-  if (BI.isConditional())
+  if (BI.isConditional() && !isa<Constant>(BI.getCondition()))
     if (Value *V = dyn_castNotVal(BI.getCondition())) {
       BasicBlock *TrueDest = BI.getSuccessor(0);
       BasicBlock *FalseDest = BI.getSuccessor(1);




From lattner at cs.uiuc.edu  Thu Jun  5 15:49:02 2003
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Thu Jun  5 15:49:02 2003
Subject: [llvm-commits] CVS: llvm/lib/Reoptimizer/Trigger/Trigger.cpp
Message-ID: <200306052048.PAA03284@apoc.cs.uiuc.edu>


Changes in directory llvm/lib/Reoptimizer/Trigger:

Trigger.cpp updated: 1.18 -> 1.19

---
Log message:

Fix warning


---
Diffs of the changes:

Index: llvm/lib/Reoptimizer/Trigger/Trigger.cpp
diff -u llvm/lib/Reoptimizer/Trigger/Trigger.cpp:1.18 llvm/lib/Reoptimizer/Trigger/Trigger.cpp:1.19
--- llvm/lib/Reoptimizer/Trigger/Trigger.cpp:1.18	Thu Jun  5 01:04:35 2003
+++ llvm/lib/Reoptimizer/Trigger/Trigger.cpp	Thu Jun  5 15:47:52 2003
@@ -119,7 +119,7 @@
   map<unsigned int, uint64_t> toFixCid; //cid, original PC
   
   //cid of BA to top
-  unsigned cidToTop;
+  unsigned cidToTop = 0;
 
   
   //map of BB to starting cid




From lattner at cs.uiuc.edu  Thu Jun  5 15:52:01 2003
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Thu Jun  5 15:52:01 2003
Subject: [llvm-commits] CVS: llvm/tools/llc/llc.cpp
Message-ID: <200306052051.PAA03493@apoc.cs.uiuc.edu>


Changes in directory llvm/tools/llc:

llc.cpp updated: 1.72 -> 1.73

---
Log message:

Remove duplicate pass


---
Diffs of the changes:

Index: llvm/tools/llc/llc.cpp
diff -u llvm/tools/llc/llc.cpp:1.72 llvm/tools/llc/llc.cpp:1.73
--- llvm/tools/llc/llc.cpp:1.72	Tue May 27 16:23:02 2003
+++ llvm/tools/llc/llc.cpp	Thu Jun  5 15:51:10 2003
@@ -118,10 +118,6 @@
                 << Opt->getPassName() << "\n";
   }
 
-  // Decompose multi-dimensional refs into a sequence of 1D refs
-  // FIXME: This is sparc specific!
-  Passes.add(createDecomposeMultiDimRefsPass());
-
   // Replace malloc and free instructions with library calls.
   // Do this after tracing until lli implements these lib calls.
   // For now, it will emulate malloc and free internally.




From brukman at cs.uiuc.edu  Thu Jun  5 15:52:06 2003
From: brukman at cs.uiuc.edu (Misha Brukman)
Date: Thu Jun  5 15:52:06 2003
Subject: [llvm-commits] CVS: llvm/lib/Target/Sparc/SparcV9.td
Message-ID: <200306052051.PAA25125@zion.cs.uiuc.edu>


Changes in directory llvm/lib/Target/Sparc:

SparcV9.td updated: 1.16 -> 1.17

---
Log message:

* The textual output of (non-)predicted FP branches is the same.
* Stop mapping FBcc instructions to deprecated opcodes, map to FBPcc instead.
* Fixed opf in FCMPxy instructions.


---
Diffs of the changes:

Index: llvm/lib/Target/Sparc/SparcV9.td
diff -u llvm/lib/Target/Sparc/SparcV9.td:1.16 llvm/lib/Target/Sparc/SparcV9.td:1.17
--- llvm/lib/Target/Sparc/SparcV9.td:1.16	Wed Jun  4 20:06:10 2003
+++ llvm/lib/Target/Sparc/SparcV9.td	Thu Jun  5 15:51:37 2003
@@ -52,7 +52,9 @@
   def BRGEZ   : F2_4<0b111, "brgez">;               // Branch on rs1 >= 0
 }
 
-// Section A.4: p164
+// Section A.4: Branch on Floating-Point Condition Codes (FBfcc) p140
+// The following deprecated instructions don't seem to play nice on Sparc
+#if 0
 set isDeprecated = 1 in {
   set op2 = 0b110 in {
     def FBA     : F2_2<0b1000, "fba">;              // Branch always
@@ -73,27 +75,51 @@
     def FBO     : F2_2<0b1111, "fbo">;              // Branch on ordered
   }
 }
+#endif
+
+// These instructions are hacked to really represent A.5 instructions,
+// but with cc hardcoded to be %fcc0. Hence, they behave like FBPfcc instrs.
+set op2 = 0b101 in {
+  set cc = 0b00 in {
+    def FBA     : F2_3<0b1000, "fba">;              // Branch always
+    def FBN     : F2_3<0b0000, "fbn">;              // Branch never
+    def FBU     : F2_3<0b0111, "fbu">;              // Branch on unordered
+    def FBG     : F2_3<0b0110, "fbg">;              // Branch >
+    def FBUG    : F2_3<0b0101, "fbug">;             // Branch on unordered or >
+    def FBL     : F2_3<0b0100, "fbl">;              // Branch <
+    def FBUL    : F2_3<0b0011, "fbul">;             // Branch on unordered or <
+    def FBLG    : F2_3<0b0010, "fblg">;             // Branch < or >
+    def FBNE    : F2_3<0b0001, "fbne">;             // Branch !=
+    def FBE     : F2_3<0b1001, "fbe">;              // Branch ==
+    def FBUE    : F2_3<0b1010, "fbue">;             // Branch on unordered or ==
+    def FBGE    : F2_3<0b1011, "fbge">;             // Branch > or ==
+    def FBUGE   : F2_3<0b1100, "fbuge">;            // Branch unord or > or ==
+    def FBLE    : F2_3<0b1101, "fble">;             // Branch < or ==
+    def FBULE   : F2_3<0b1110, "fbule">;            // Branch unord or < or ==
+    def FBO     : F2_3<0b1111, "fbo">;              // Branch on ordered
+  }
+}
 
-// Section A.5: p167
+// Section A.5: Branch on FP condition codes with prediction - p143
 // Not used in the Sparc backend
 #if 0
 set op2 = 0b101 in {
-  def FBPA     : F2_3<0b1000, "fbpa">;              // Branch always
-  def FBPN     : F2_3<0b0000, "fbpn">;              // Branch never
-  def FBPU     : F2_3<0b0111, "fbpu">;              // Branch on unordered
-  def FBPG     : F2_3<0b0110, "fbpg">;              // Branch >
-  def FBPUG    : F2_3<0b0101, "fbpug">;             // Branch on unordered or >
-  def FBPL     : F2_3<0b0100, "fbpl">;              // Branch <
-  def FBPUL    : F2_3<0b0011, "fbpul">;             // Branch on unordered or <
-  def FBPLG    : F2_3<0b0010, "fbplg">;             // Branch < or >
-  def FBPNE    : F2_3<0b0001, "fbpne">;             // Branch !=
-  def FBPE     : F2_3<0b1001, "fbpe">;              // Branch ==
-  def FBPUE    : F2_3<0b1010, "fbpue">;             // Branch on unordered or ==
-  def FBPGE    : F2_3<0b1011, "fbpge">;             // Branch > or ==
-  def FBPUGE   : F2_3<0b1100, "fbpuge">;            // Branch unord or > or ==
-  def FBPLE    : F2_3<0b1101, "fbple">;             // Branch < or ==
-  def FBPULE   : F2_3<0b1110, "fbpule">;            // Branch unord or < or ==
-  def FBPO     : F2_3<0b1111, "fbpo">;              // Branch on ordered
+  def FBPA     : F2_3<0b1000, "fba">;              // Branch always
+  def FBPN     : F2_3<0b0000, "fbn">;              // Branch never
+  def FBPU     : F2_3<0b0111, "fbu">;              // Branch on unordered
+  def FBPG     : F2_3<0b0110, "fbg">;              // Branch >
+  def FBPUG    : F2_3<0b0101, "fbug">;             // Branch on unordered or >
+  def FBPL     : F2_3<0b0100, "fbl">;              // Branch <
+  def FBPUL    : F2_3<0b0011, "fbul">;             // Branch on unordered or <
+  def FBPLG    : F2_3<0b0010, "fblg">;             // Branch < or >
+  def FBPNE    : F2_3<0b0001, "fbne">;             // Branch !=
+  def FBPE     : F2_3<0b1001, "fbe">;              // Branch ==
+  def FBPUE    : F2_3<0b1010, "fbue">;             // Branch on unordered or ==
+  def FBPGE    : F2_3<0b1011, "fbge">;             // Branch > or ==
+  def FBPUGE   : F2_3<0b1100, "fbuge">;            // Branch unord or > or ==
+  def FBPLE    : F2_3<0b1101, "fble">;             // Branch < or ==
+  def FBPULE   : F2_3<0b1110, "fbule">;            // Branch unord or < or ==
+  def FBPO     : F2_3<0b1111, "fbo">;              // Branch on ordered
 }
 #endif
 
@@ -188,14 +214,14 @@
 def FSUBQ : F3_16<2, 0b110100, 0x47, "fsubq">;    // fsubq f, f, f
 
 // Section A.13: Floating-point compare - p159
-def FCMPS  : F3_15<2, 0b110101, 0b010100001, "fcmps">;   // fcmps  %fcc, r1, r2
-def FCMPD  : F3_15<2, 0b110101, 0b010100010, "fcmpd">;   // fcmpd  %fcc, r1, r2
-def FCMPQ  : F3_15<2, 0b110101, 0b010100011, "fcmpq">;   // fcmpq  %fcc, r1, r2
+def FCMPS  : F3_15<2, 0b110101, 0b001010001, "fcmps">;   // fcmps  %fcc, r1, r2
+def FCMPD  : F3_15<2, 0b110101, 0b001010010, "fcmpd">;   // fcmpd  %fcc, r1, r2
+def FCMPQ  : F3_15<2, 0b110101, 0b001010011, "fcmpq">;   // fcmpq  %fcc, r1, r2
 // Currently unused in the Sparc backend
 #if 0
-def FCMPES : F3_15<2, 0b110101, 0b010100101, "fcmpes">;  // fcmpes %fcc, r1, r2
-def FCMPED : F3_15<2, 0b110101, 0b010100110, "fcmped">;  // fcmped %fcc, r1, r2
-def FCMPEQ : F3_15<2, 0b110101, 0b010100111, "fcmpeq">;  // fcmpeq %fcc, r1, r2
+def FCMPES : F3_15<2, 0b110101, 0b001010101, "fcmpes">;  // fcmpes %fcc, r1, r2
+def FCMPED : F3_15<2, 0b110101, 0b001010110, "fcmped">;  // fcmped %fcc, r1, r2
+def FCMPEQ : F3_15<2, 0b110101, 0b001010111, "fcmpeq">;  // fcmpeq %fcc, r1, r2
 #endif
 
 // Section A.14: Convert floating-point to integer - p161




From brukman at cs.uiuc.edu  Thu Jun  5 15:53:01 2003
From: brukman at cs.uiuc.edu (Misha Brukman)
Date: Thu Jun  5 15:53:01 2003
Subject: [llvm-commits] CVS: llvm/lib/Target/Sparc/SparcV9CodeEmitter.cpp SparcV9CodeEmitter.h
Message-ID: <200306052052.PAA25149@zion.cs.uiuc.edu>


Changes in directory llvm/lib/Target/Sparc:

SparcV9CodeEmitter.cpp updated: 1.11 -> 1.12
SparcV9CodeEmitter.h updated: 1.6 -> 1.7

---
Log message:

Added lazy function resolution to the JIT.


---
Diffs of the changes:

Index: llvm/lib/Target/Sparc/SparcV9CodeEmitter.cpp
diff -u llvm/lib/Target/Sparc/SparcV9CodeEmitter.cpp:1.11 llvm/lib/Target/Sparc/SparcV9CodeEmitter.cpp:1.12
--- llvm/lib/Target/Sparc/SparcV9CodeEmitter.cpp:1.11	Wed Jun  4 15:01:13 2003
+++ llvm/lib/Target/Sparc/SparcV9CodeEmitter.cpp	Thu Jun  5 15:52:06 2003
@@ -54,10 +54,13 @@
       return SparcV9.getBinaryCodeForInstr(MI);
     }
 
+    inline uint64_t insertFarJumpAtAddr(int64_t Value, uint64_t Addr);
+
   private:
     uint64_t emitStubForFunction(Function *F);
     static void CompilationCallback();
     uint64_t resolveFunctionReference(uint64_t RetAddr);
+
   };
 
   JITResolver *TheJITResolver;
@@ -92,27 +95,175 @@
   return Stub;
 }
 
-void JITResolver::CompilationCallback() {
-  uint64_t *StackPtr = (uint64_t*)__builtin_frame_address(0);
-  uint64_t RetAddr = (uint64_t)(intptr_t)__builtin_return_address(0);
+uint64_t JITResolver::insertFarJumpAtAddr(int64_t Target, uint64_t Addr) {
+
+  static const unsigned i1 = SparcIntRegClass::i1, i2 = SparcIntRegClass::i2,
+    i7 = SparcIntRegClass::i7,
+    o6 = SparcIntRegClass::o6, g0 = SparcIntRegClass::g0;
+
+  // 
+  // Save %i1, %i2 to the stack so we can form a 64-bit constant in %i2
+  // 
+
+  // stx %i1, [%sp + 2119]       ;; save %i1 to the stack, used as temp
+  MachineInstr *STX = BuildMI(V9::STXi, 3).addReg(i1).addReg(o6).addSImm(2119);
+  *((unsigned*)(intptr_t)Addr) = getBinaryCodeForInstr(*STX);
+  delete STX;
+  Addr += 4;
+
+  // stx %i2, [%sp + 2127]       ;; save %i2 to the stack
+  STX = BuildMI(V9::STXi, 3).addReg(i2).addReg(o6).addSImm(2127);
+  *((unsigned*)(intptr_t)Addr) = getBinaryCodeForInstr(*STX);
+  delete STX;
+  Addr += 4;
+
+  //
+  // Get address to branch into %i2, using %i1 as a temporary
+  //
+
+  // sethi %uhi(Target), %i1   ;; get upper 22 bits of Target into %i1
+  MachineInstr *SH = BuildMI(V9::SETHI, 2).addSImm(Target >> 42).addReg(i1);
+  *((unsigned*)(intptr_t)Addr) = getBinaryCodeForInstr(*SH);
+  delete SH;
+  Addr += 4;
+
+  // or %i1, %ulo(Target), %i1 ;; get 10 lower bits of upper word into %1
+  MachineInstr *OR = BuildMI(V9::ORi, 3)
+    .addReg(i1).addSImm((Target >> 32) & 0x03ff).addReg(i1);
+  *((unsigned*)(intptr_t)Addr) = getBinaryCodeForInstr(*OR);
+  delete OR;
+  Addr += 4;
+
+  // sllx %i1, 32, %i1            ;; shift those 10 bits to the upper word
+  MachineInstr *SL = BuildMI(V9::SLLXi6, 3).addReg(i1).addSImm(32).addReg(i1);
+  *((unsigned*)(intptr_t)Addr) = getBinaryCodeForInstr(*SL);
+  delete SL;
+  Addr += 4;
+
+  // sethi %hi(Target), %i2    ;; extract bits 10-31 into the dest reg
+  SH = BuildMI(V9::SETHI, 2).addSImm((Target >> 10) & 0x03fffff).addReg(i2);
+  *((unsigned*)(intptr_t)Addr) = getBinaryCodeForInstr(*SH);
+  delete SH;
+  Addr += 4;
+
+  // or %i1, %i2, %i2             ;; get upper word (in %i1) into %i2
+  OR = BuildMI(V9::ORr, 3).addReg(i1).addReg(i2).addReg(i2);
+  *((unsigned*)(intptr_t)Addr) = getBinaryCodeForInstr(*OR);
+  delete OR;
+  Addr += 4;
+
+  // or %i2, %lo(Target), %i2  ;; get lowest 10 bits of Target into %i2
+  OR = BuildMI(V9::ORi, 3).addReg(i2).addSImm(Target & 0x03ff).addReg(i2);
+  *((unsigned*)(intptr_t)Addr) = getBinaryCodeForInstr(*OR);
+  delete OR;
+  Addr += 4;
+
+  // ldx [%sp + 2119], %i1       ;; restore %i1 -> 2119 = BIAS(2047) + 72
+  MachineInstr *LDX = BuildMI(V9::LDXi, 3).addReg(o6).addSImm(2119).addReg(i1);
+  *((unsigned*)(intptr_t)Addr) = getBinaryCodeForInstr(*LDX);
+  delete LDX;
+  Addr += 4;
+
+  // jmpl %i2, %g0, %g0          ;; indirect branch on %i2
+  MachineInstr *J = BuildMI(V9::JMPLRETr, 3).addReg(i2).addReg(g0).addReg(g0);
+  *((unsigned*)(intptr_t)Addr) = getBinaryCodeForInstr(*J);
+  delete J;
+  Addr += 4;
+
+  // ldx [%sp + 2127], %i2       ;; restore %i2 -> 2127 = BIAS(2047) + 80
+  LDX = BuildMI(V9::LDXi, 3).addReg(o6).addSImm(2127).addReg(i2);
+  *((unsigned*)(intptr_t)Addr) = getBinaryCodeForInstr(*LDX);
+  delete LDX;
+  Addr += 4;
 
-  std::cerr << "In callback! Addr=0x" << std::hex << RetAddr
-            << " SP=0x" << (uint64_t)(intptr_t)StackPtr << std::dec << "\n";
+  return Addr;
+}
 
-  int64_t NewVal = (int64_t)TheJITResolver->resolveFunctionReference(RetAddr);
+void JITResolver::CompilationCallback() {
+  uint64_t CameFrom = (uint64_t)(intptr_t)__builtin_return_address(0);
+  int64_t Target = (int64_t)TheJITResolver->resolveFunctionReference(CameFrom);
+  std::cerr << "In callback! Addr=0x" << std::hex << CameFrom << "\n";
 
   // Rewrite the call target... so that we don't fault every time we execute
   // the call.
+#if 0
   int64_t RealCallTarget = (int64_t)
     ((NewVal - TheJITResolver->getCurrentPCValue()) >> 4);
-  MachineInstr *MI = BuildMI(V9::CALL, 1);
-  MI->addSignExtImmOperand(RealCallTarget);
-  // FIXME: this could be in the wrong byte order!!
-  *((unsigned*)(intptr_t)RetAddr) = TheJITResolver->getBinaryCodeForInstr(*MI);
+  if (RealCallTarget >= (1<<22) || RealCallTarget <= -(1<<22)) {
+    std::cerr << "Address out of bounds for 22bit BA: " << RealCallTarget<<"\n";
+    abort();
+  }
+#endif
+
+  //uint64_t CurrPC    = TheJITResolver->getCurrentPCValue();
+  // we will insert 9 instructions before we do the actual jump
+  //int64_t NewTarget  = (NewVal - 9*4 - InstAddr) >> 2;
+
+  static const unsigned i1 = SparcIntRegClass::i1, i2 = SparcIntRegClass::i2,
+    i7 = SparcIntRegClass::i7, o6 = SparcIntRegClass::o6,
+    o7 = SparcIntRegClass::o7, g0 = SparcIntRegClass::g0;
+
+  // Subtract 4 to overwrite the 'save' that's there now
+  uint64_t InstAddr = CameFrom-4;
+
+  InstAddr = TheJITResolver->insertFarJumpAtAddr(Target, InstAddr);
+
+  // CODE SHOULD NEVER GO PAST THIS LOAD!! The real function should return to
+  // the original caller, not here!!
+
+  // FIXME: add call 0 to make sure?!?
+
+  // =============== THE REAL STUB ENDS HERE =========================
+
+  // What follows below is one-time restore code, because this callback may be
+  // changing registers in unpredictible ways. However, since it is executed
+  // only once per function (after the function is resolved, the callback is no
+  // longer in the path), this has to be done only once.
+  //
+  // Thus, it is after the regular stub code. The call back returns to THIS
+  // point, but every other call to the target function will execute the code
+  // above. Hence, this code is one-time use.
+
+  uint64_t OneTimeRestore = InstAddr;
+
+  // restore %g0, 0, %g0
+  //MachineInstr *R = BuildMI(V9::RESTOREi, 3).addMReg(g0).addSImm(0)
+  //                                          .addMReg(g0, MOTy::Def);
+  //*((unsigned*)(intptr_t)InstAddr)=TheJITResolver->getBinaryCodeForInstr(*R);
+  //delete R;
+
+  // FIXME: BuildMI() above crashes. Encode the instruction directly.
+  // restore %g0, 0, %g0
+  *((unsigned*)(intptr_t)InstAddr) = 0x81e82000U;
+  InstAddr += 4;  
+
+  InstAddr = TheJITResolver->insertFarJumpAtAddr(Target, InstAddr);
+
+  // FIXME: if the target function is close enough to fit into the 19bit disp of
+  // BA, we should use this version, as its much cheaper to generate.
+  /*
+  MachineInstr *MI = BuildMI(V9::BA, 1).addSImm(RealCallTarget);
+  *((unsigned*)(intptr_t)InstAddr) = TheJITResolver->getBinaryCodeForInstr(*MI);
   delete MI;
-  
+  InstAddr += 4;
+
+  // Add another NOP
+  MachineInstr *Nop = BuildMI(V9::NOP, 0);
+  *((unsigned*)(intptr_t)InstAddr)=TheJITResolver->getBinaryCodeForInstr(*Nop);
+  delete Nop;
+  InstAddr += 4;
+
+  MachineInstr *BA = BuildMI(V9::BA, 1).addSImm(RealCallTarget-2);
+  *((unsigned*)(intptr_t)InstAddr) = TheJITResolver->getBinaryCodeForInstr(*BA);
+  delete BA;
+  */
+
   // Change the return address to reexecute the call instruction...
-  StackPtr[1] -= 4;
+  // The return address is really %o7, but will disappear after this function
+  // returns, and the register windows are rotated away.
+#if defined(sparc) || defined(__sparc__) || defined(__sparcv9)
+  __asm__ __volatile__ ("or %%g0, %0, %%i7" : : "r" (OneTimeRestore-8));
+#endif
 }
 
 /// emitStubForFunction - This method is used by the JIT when it needs to emit
@@ -122,26 +273,31 @@
 /// directly.
 ///
 uint64_t JITResolver::emitStubForFunction(Function *F) {
-#if 0
   MCE.startFunctionStub(*F, 6);
-  MCE.emitByte(0xE8);   // Call with 32 bit pc-rel destination...
 
-  uint64_t Address = addFunctionReference(MCE.getCurrentPCValue(), F);
-  MCE.emitWord(Address-MCE.getCurrentPCValue()-4);
+  std::cerr << "Emitting stub at addr: 0x" 
+            << std::hex << MCE.getCurrentPCValue() << "\n";
 
-  MCE.emitByte(0xCD);   // Interrupt - Just a marker identifying the stub!
-  return (intptr_t)MCE.finishFunctionStub(*F);
-#endif
-  MCE.startFunctionStub(*F, 6);
+  unsigned o6 = SparcIntRegClass::o6;
+  // save %sp, -192, %sp
+  MachineInstr *SV = BuildMI(V9::SAVEi, 3).addReg(o6).addSImm(-192).addReg(o6);
+  SparcV9.emitWord(SparcV9.getBinaryCodeForInstr(*SV));
+  delete SV;
 
   int64_t CurrPC = MCE.getCurrentPCValue();
   int64_t Addr = (int64_t)addFunctionReference(CurrPC, F);
+
   int64_t CallTarget = (Addr-CurrPC) >> 2;
-  MachineInstr *Call = BuildMI(V9::CALL, 1);
-  Call->addSignExtImmOperand(CallTarget);
+  if (CallTarget >= (1 << 30) || CallTarget <= -(1 << 30)) {
+    std::cerr << "Call target beyond 30 bit limit of CALL: " <<CallTarget<<"\n";
+    abort();
+  }
+  // call CallTarget              ;; invoke the callback
+  MachineInstr *Call = BuildMI(V9::CALL, 1).addSImm(CallTarget);
   SparcV9.emitWord(SparcV9.getBinaryCodeForInstr(*Call));
   delete Call;
   
+  // nop                          ;; call delay slot
   MachineInstr *Nop = BuildMI(V9::NOP, 0);
   SparcV9.emitWord(SparcV9.getBinaryCodeForInstr(*Nop));
   delete Nop;
@@ -170,7 +326,25 @@
   }
 }
 
-unsigned getRealRegNum(unsigned fakeReg, unsigned regClass) {
+bool SparcV9CodeEmitter::isFPInstr(MachineInstr &MI) {
+  for (unsigned i = 0, e = MI.getNumOperands(); i < e; ++i) {
+    const MachineOperand &MO = MI.getOperand(i);
+    if (MO.isPhysicalRegister()) {
+      unsigned fakeReg = MO.getReg(), realReg, regClass, regType;
+      regType = TM.getRegInfo().getRegType(fakeReg);
+      // At least map fakeReg into its class
+      fakeReg = TM.getRegInfo().getClassRegNum(fakeReg, regClass);
+      if (regClass == UltraSparcRegInfo::FPSingleRegType ||
+          regClass == UltraSparcRegInfo::FPDoubleRegType)
+        return true;
+    }
+  }
+  return false;
+}
+
+unsigned 
+SparcV9CodeEmitter::getRealRegNum(unsigned fakeReg, unsigned regClass,
+                                  MachineInstr &MI) {
   switch (regClass) {
   case UltraSparcRegInfo::IntRegType: {
     // Sparc manual, p31
@@ -199,11 +373,23 @@
     return fakeReg;
   }
   case UltraSparcRegInfo::FloatCCRegType: {
+    /* These are laid out %fcc0 - %fcc3 => 0 - 3, so are correct */
     return fakeReg;
 
   }
   case UltraSparcRegInfo::IntCCRegType: {
-    return fakeReg;
+    static const unsigned FPInstrIntCCReg[]  = { 6 /* xcc */, 4  /* icc */ };
+    static const unsigned IntInstrIntCCReg[] = { 2 /* xcc */, 0  /* icc */ };
+    
+    if (isFPInstr(MI)) {
+      assert(fakeReg < sizeof(FPInstrIntCCReg)/sizeof(FPInstrIntCCReg[0])
+             && "Int CC register out of bounds for FPInstr IntCCReg map");      
+      return FPInstrIntCCReg[fakeReg];
+    } else {
+      assert(fakeReg < sizeof(IntInstrIntCCReg)/sizeof(IntInstrIntCCReg[0])
+             && "Int CC register out of bounds for IntInstr IntCCReg map");
+      return IntInstrIntCCReg[fakeReg];
+    }
   }
   default:
     assert(0 && "Invalid unified register number in getRegType");
@@ -278,7 +464,9 @@
       std::cerr << "ERROR: PC relative disp unhandled:" << MO << "\n";
       abort();
     }
-  } else if (MO.isPhysicalRegister()) {
+  } else if (MO.isPhysicalRegister() ||
+             MO.getType() == MachineOperand::MO_CCRegister)
+  {
     // This is necessary because the Sparc doesn't actually lay out registers
     // in the real fashion -- it skips those that it chooses not to allocate,
     // i.e. those that are the SP, etc.
@@ -287,7 +475,7 @@
     // At least map fakeReg into its class
     fakeReg = TM.getRegInfo().getClassRegNum(fakeReg, regClass);
     // Find the real register number for use in an instruction
-    realReg = getRealRegNum(fakeReg, regClass);
+    realReg = getRealRegNum(fakeReg, regClass, MI);
     std::cerr << "Reg[" << std::dec << fakeReg << "] = " << realReg << "\n";
     rv = realReg;
   } else if (MO.isImmediate()) {
@@ -327,13 +515,13 @@
   // are used in SPARC assembly. (Some of these make no sense in combination
   // with some of the above; we'll trust that the instruction selector
   // will not produce nonsense, and not check for valid combinations here.)
-  if (MO.opLoBits32()) {          // %lo(val)
+  if (MO.opLoBits32()) {          // %lo(val) == %lo() in Sparc ABI doc
     return rv & 0x03ff;
-  } else if (MO.opHiBits32()) {   // %lm(val)
+  } else if (MO.opHiBits32()) {   // %lm(val) == %hi() in Sparc ABI doc
     return (rv >> 10) & 0x03fffff;
-  } else if (MO.opLoBits64()) {   // %hm(val)
+  } else if (MO.opLoBits64()) {   // %hm(val) == %ulo() in Sparc ABI doc
     return (rv >> 32) & 0x03ff;
-  } else if (MO.opHiBits64()) {   // %hh(val)
+  } else if (MO.opHiBits64()) {   // %hh(val) == %uhi() in Sparc ABI doc
     return rv >> 42;
   } else {                        // (unadorned) val
     return rv;


Index: llvm/lib/Target/Sparc/SparcV9CodeEmitter.h
diff -u llvm/lib/Target/Sparc/SparcV9CodeEmitter.h:1.6 llvm/lib/Target/Sparc/SparcV9CodeEmitter.h:1.7
--- llvm/lib/Target/Sparc/SparcV9CodeEmitter.h:1.6	Wed Jun  4 15:01:13 2003
+++ llvm/lib/Target/Sparc/SparcV9CodeEmitter.h	Thu Jun  5 15:52:06 2003
@@ -47,6 +47,10 @@
   void emitBasicBlock(MachineBasicBlock &MBB);
   void* getGlobalAddress(GlobalValue *V, MachineInstr &MI,
                          bool isPCRelative);
+  bool isFPInstr(MachineInstr &MI);
+  unsigned getRealRegNum(unsigned fakeReg, unsigned regClass,
+                         MachineInstr &MI);
+
 };
 
 #endif




From lattner at cs.uiuc.edu  Thu Jun  5 16:02:02 2003
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Thu Jun  5 16:02:02 2003
Subject: [llvm-commits] CVS: llvm/lib/VMCore/Verifier.cpp
Message-ID: <200306052101.QAA03965@apoc.cs.uiuc.edu>


Changes in directory llvm/lib/VMCore:

Verifier.cpp updated: 1.50 -> 1.51

---
Log message:

Fix (bogus) possibly uninitialized warning


---
Diffs of the changes:

Index: llvm/lib/VMCore/Verifier.cpp
diff -u llvm/lib/VMCore/Verifier.cpp:1.50 llvm/lib/VMCore/Verifier.cpp:1.51
--- llvm/lib/VMCore/Verifier.cpp:1.50	Sat May 17 17:26:33 2003
+++ llvm/lib/VMCore/Verifier.cpp	Thu Jun  5 16:01:26 2003
@@ -508,7 +508,7 @@
   Function *IF = CI.getCalledFunction();
   const FunctionType *FT = IF->getFunctionType();
   Assert1(IF->isExternal(), "Intrinsic functions should never be defined!", IF);
-  unsigned NumArgs;
+  unsigned NumArgs = 0;
 
   switch (ID) {
   case LLVMIntrinsic::va_start:




From lattner at cs.uiuc.edu  Thu Jun  5 16:03:01 2003
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Thu Jun  5 16:03:01 2003
Subject: [llvm-commits] CVS: llvm/lib/Reoptimizer/TraceCache/TraceCache.cpp
Message-ID: <200306052102.QAA04038@apoc.cs.uiuc.edu>


Changes in directory llvm/lib/Reoptimizer/TraceCache:

TraceCache.cpp updated: 1.12 -> 1.13

---
Log message:

Fix warning


---
Diffs of the changes:

Index: llvm/lib/Reoptimizer/TraceCache/TraceCache.cpp
diff -u llvm/lib/Reoptimizer/TraceCache/TraceCache.cpp:1.12 llvm/lib/Reoptimizer/TraceCache/TraceCache.cpp:1.13
--- llvm/lib/Reoptimizer/TraceCache/TraceCache.cpp:1.12	Sat May 31 21:33:08 2003
+++ llvm/lib/Reoptimizer/TraceCache/TraceCache.cpp	Thu Jun  5 16:02:07 2003
@@ -589,5 +589,5 @@
     if(RMI->first < brAddr)
       return RMI->first;
 
-  assert(0);
+  abort();
 }	




From vadve at cs.uiuc.edu  Thu Jun  5 16:14:01 2003
From: vadve at cs.uiuc.edu (Vikram Adve)
Date: Thu Jun  5 16:14:01 2003
Subject: [llvm-commits] CVS: llvm/lib/CodeGen/PreOpts/PreSelection.cpp
Message-ID: <200306052113.QAA19481@psmith.cs.uiuc.edu>


Changes in directory llvm/lib/CodeGen/PreOpts:

PreSelection.cpp updated: 1.12 -> 1.13

---
Log message:

Minor tuning -- avoid a non-inlinable function call on every operand.
Also, reorder a couple of functions for inlining.


---
Diffs of the changes:

Index: llvm/lib/CodeGen/PreOpts/PreSelection.cpp
diff -u llvm/lib/CodeGen/PreOpts/PreSelection.cpp:1.12 llvm/lib/CodeGen/PreOpts/PreSelection.cpp:1.13
--- llvm/lib/CodeGen/PreOpts/PreSelection.cpp:1.12	Tue Jun  3 20:24:40 2003
+++ llvm/lib/CodeGen/PreOpts/PreSelection.cpp	Thu Jun  5 16:12:56 2003
@@ -115,6 +115,7 @@
   class PreSelection : public BasicBlockPass, public InstVisitor<PreSelection>
   {
     const TargetMachine &target;
+    const TargetInstrInfo &instrInfo;
     Function* function;
 
     GlobalVariable* getGlobalForConstant(Constant* CV) {
@@ -123,7 +124,8 @@
     }
 
   public:
-    PreSelection (const TargetMachine &T): target(T), function(NULL) {}
+    PreSelection (const TargetMachine &T):
+      target(T), instrInfo(T.getInstrInfo()), function(NULL) {}
 
     // runOnBasicBlock - apply this pass to each BB
     bool runOnBasicBlock(BasicBlock &BB) {
@@ -237,6 +239,75 @@
 //------------------------------------------------------------------------------
 // Instruction visitor methods to perform instruction-specific operations
 //------------------------------------------------------------------------------
+inline void
+PreSelection::visitOneOperand(Instruction &I, Value* Op, unsigned opNum,
+                              Instruction& insertBefore)
+{
+  if (GetElementPtrInst* gep = getGlobalAddr(Op, insertBefore)) {
+    I.setOperand(opNum, gep);           // replace global operand
+    return;
+  }
+
+  Constant* CV  = dyn_cast<Constant>(Op);
+  if (CV == NULL)
+    return;
+
+  if (ConstantExpr* CE = dyn_cast<ConstantExpr>(CV))
+    { // load-time constant: factor it out so we optimize as best we can
+      Instruction* computeConst = DecomposeConstantExpr(CE, insertBefore);
+      I.setOperand(opNum, computeConst); // replace expr operand with result
+    }
+  else if (instrInfo.ConstantTypeMustBeLoaded(CV))
+    { // load address of constant into a register, then load the constant
+      GetElementPtrInst* gep = getGlobalAddr(getGlobalForConstant(CV),
+                                             insertBefore);
+      LoadInst* ldI = new LoadInst(gep, "loadConst", &insertBefore);
+      I.setOperand(opNum, ldI);        // replace operand with copy in v.reg.
+    }
+  else if (instrInfo.ConstantMayNotFitInImmedField(CV, &I))
+    { // put the constant into a virtual register using a cast
+      CastInst* castI = new CastInst(CV, CV->getType(), "copyConst",
+                                     &insertBefore);
+      I.setOperand(opNum, castI);      // replace operand with copy in v.reg.
+    }
+}
+
+// visitOperands() transforms individual operands of all instructions:
+// -- Load "large" int constants into a virtual register.  What is large
+//    depends on the type of instruction and on the target architecture.
+// -- For any constants that cannot be put in an immediate field,
+//    load address into virtual register first, and then load the constant.
+// 
+// firstOp and lastOp can be used to skip leading and trailing operands.
+// If lastOp is 0, it defaults to #operands or #incoming Phi values.
+//  
+inline void
+PreSelection::visitOperands(Instruction &I, int firstOp, int lastOp)
+{
+  // For any instruction other than PHI, copies go just before the instr.
+  // For a PHI, operand copies must be before the terminator of the
+  // appropriate predecessor basic block.  Remaining logic is simple
+  // so just handle PHIs and other instructions separately.
+  // 
+  if (PHINode* phi = dyn_cast<PHINode>(&I))
+    {
+      if (lastOp == 0)
+        lastOp = phi->getNumIncomingValues();
+      for (unsigned i=firstOp, N=lastOp; i < N; ++i)
+        this->visitOneOperand(I, phi->getIncomingValue(i),
+                              phi->getOperandNumForIncomingValue(i),
+                              * phi->getIncomingBlock(i)->getTerminator());
+    }
+  else
+    {
+      if (lastOp == 0)
+        lastOp = I.getNumOperands();
+      for (unsigned i=firstOp, N=lastOp; i < N; ++i)
+        this->visitOneOperand(I, I.getOperand(i), i, I);
+    }
+}
+
+
 
 // Common work for *all* instructions.  This needs to be called explicitly
 // by other visit<InstructionType> functions.
@@ -326,75 +397,6 @@
 {
   // Tell visitOperands to ignore the function name if this is a direct call.
   visitOperands(I, (/*firstOp=*/ I.getCalledFunction()? 1 : 0));
-}
-
-
-// visitOperands() transforms individual operands of all instructions:
-// -- Load "large" int constants into a virtual register.  What is large
-//    depends on the type of instruction and on the target architecture.
-// -- For any constants that cannot be put in an immediate field,
-//    load address into virtual register first, and then load the constant.
-// 
-// firstOp and lastOp can be used to skip leading and trailing operands.
-// If lastOp is 0, it defaults to #operands or #incoming Phi values.
-//  
-void
-PreSelection::visitOperands(Instruction &I, int firstOp, int lastOp)
-{
-  // For any instruction other than PHI, copies go just before the instr.
-  // For a PHI, operand copies must be before the terminator of the
-  // appropriate predecessor basic block.  Remaining logic is simple
-  // so just handle PHIs and other instructions separately.
-  // 
-  if (PHINode* phi = dyn_cast<PHINode>(&I))
-    {
-      if (lastOp == 0)
-        lastOp = phi->getNumIncomingValues();
-      for (unsigned i=firstOp, N=lastOp; i < N; ++i)
-        this->visitOneOperand(I, phi->getIncomingValue(i),
-                              phi->getOperandNumForIncomingValue(i),
-                              * phi->getIncomingBlock(i)->getTerminator());
-    }
-  else
-    {
-      if (lastOp == 0)
-        lastOp = I.getNumOperands();
-      for (unsigned i=firstOp, N=lastOp; i < N; ++i)
-        this->visitOneOperand(I, I.getOperand(i), i, I);
-    }
-}
-
-void
-PreSelection::visitOneOperand(Instruction &I, Value* Op, unsigned opNum,
-                              Instruction& insertBefore)
-{
-  if (GetElementPtrInst* gep = getGlobalAddr(Op, insertBefore)) {
-    I.setOperand(opNum, gep);           // replace global operand
-    return;
-  }
-
-  Constant* CV  = dyn_cast<Constant>(Op);
-  if (CV == NULL)
-    return;
-
-  if (ConstantExpr* CE = dyn_cast<ConstantExpr>(CV))
-    { // load-time constant: factor it out so we optimize as best we can
-      Instruction* computeConst = DecomposeConstantExpr(CE, insertBefore);
-      I.setOperand(opNum, computeConst); // replace expr operand with result
-    }
-  else if (target.getInstrInfo().ConstantTypeMustBeLoaded(CV))
-    { // load address of constant into a register, then load the constant
-      GetElementPtrInst* gep = getGlobalAddr(getGlobalForConstant(CV),
-                                             insertBefore);
-      LoadInst* ldI = new LoadInst(gep, "loadConst", &insertBefore);
-      I.setOperand(opNum, ldI);        // replace operand with copy in v.reg.
-    }
-  else if (target.getInstrInfo().ConstantMayNotFitInImmedField(CV, &I))
-    { // put the constant into a virtual register using a cast
-      CastInst* castI = new CastInst(CV, CV->getType(), "copyConst",
-                                     &insertBefore);
-      I.setOperand(opNum, castI);      // replace operand with copy in v.reg.
-    }
 }
 
 




From brukman at cs.uiuc.edu  Thu Jun  5 18:16:01 2003
From: brukman at cs.uiuc.edu (Misha Brukman)
Date: Thu Jun  5 18:16:01 2003
Subject: [llvm-commits] CVS: llvm/utils/TableGen/CodeEmitterGen.cpp
Message-ID: <200306052315.SAA26024@zion.cs.uiuc.edu>


Changes in directory llvm/utils/TableGen:

CodeEmitterGen.cpp updated: 1.6 -> 1.7

---
Log message:

* Stop ignoring cc registers, since we actually use them in branches.
* Added comment as to why we are still ignoring predict and annul bits.


---
Diffs of the changes:

Index: llvm/utils/TableGen/CodeEmitterGen.cpp
diff -u llvm/utils/TableGen/CodeEmitterGen.cpp:1.6 llvm/utils/TableGen/CodeEmitterGen.cpp:1.7
--- llvm/utils/TableGen/CodeEmitterGen.cpp:1.6	Mon Jun  2 19:07:17 2003
+++ llvm/utils/TableGen/CodeEmitterGen.cpp	Thu Jun  5 18:15:25 2003
@@ -63,8 +63,8 @@
     for (unsigned i = 0, e = Vals.size(); i != e; ++i) {
       if (Vals[i].getName() != "Inst" && 
           !Vals[i].getValue()->isComplete() &&
+          /* ignore annul and predict bits since no one sets them yet */
           Vals[i].getName() != "annul" && 
-          Vals[i].getName() != "cc" &&
           Vals[i].getName() != "predict")
       {
         o << "      // op" << op << ": " << Vals[i].getName() << "\n"
@@ -105,6 +105,7 @@
           }
         } 
       } else {
+        // ignore annul and predict bits since no one sets them yet
         if (Vals[f].getName() == "annul" || Vals[f].getName() == "predict")
           --Offset;
       }




From brukman at cs.uiuc.edu  Thu Jun  5 18:31:00 2003
From: brukman at cs.uiuc.edu (Misha Brukman)
Date: Thu Jun  5 18:31:00 2003
Subject: [llvm-commits] CVS: llvm/lib/Target/Sparc/SparcV9.td
Message-ID: <200306052330.SAA27478@zion.cs.uiuc.edu>


Changes in directory llvm/lib/Target/Sparc:

SparcV9.td updated: 1.17 -> 1.18

---
Log message:

Do not preset the cc register, the instructions actually use it.


---
Diffs of the changes:

Index: llvm/lib/Target/Sparc/SparcV9.td
diff -u llvm/lib/Target/Sparc/SparcV9.td:1.17 llvm/lib/Target/Sparc/SparcV9.td:1.18
--- llvm/lib/Target/Sparc/SparcV9.td:1.17	Thu Jun  5 15:51:37 2003
+++ llvm/lib/Target/Sparc/SparcV9.td	Thu Jun  5 18:30:27 2003
@@ -77,27 +77,24 @@
 }
 #endif
 
-// These instructions are hacked to really represent A.5 instructions,
-// but with cc hardcoded to be %fcc0. Hence, they behave like FBPfcc instrs.
+// We now make these same opcodes represent the FBPfcc instructions
 set op2 = 0b101 in {
-  set cc = 0b00 in {
-    def FBA     : F2_3<0b1000, "fba">;              // Branch always
-    def FBN     : F2_3<0b0000, "fbn">;              // Branch never
-    def FBU     : F2_3<0b0111, "fbu">;              // Branch on unordered
-    def FBG     : F2_3<0b0110, "fbg">;              // Branch >
-    def FBUG    : F2_3<0b0101, "fbug">;             // Branch on unordered or >
-    def FBL     : F2_3<0b0100, "fbl">;              // Branch <
-    def FBUL    : F2_3<0b0011, "fbul">;             // Branch on unordered or <
-    def FBLG    : F2_3<0b0010, "fblg">;             // Branch < or >
-    def FBNE    : F2_3<0b0001, "fbne">;             // Branch !=
-    def FBE     : F2_3<0b1001, "fbe">;              // Branch ==
-    def FBUE    : F2_3<0b1010, "fbue">;             // Branch on unordered or ==
-    def FBGE    : F2_3<0b1011, "fbge">;             // Branch > or ==
-    def FBUGE   : F2_3<0b1100, "fbuge">;            // Branch unord or > or ==
-    def FBLE    : F2_3<0b1101, "fble">;             // Branch < or ==
-    def FBULE   : F2_3<0b1110, "fbule">;            // Branch unord or < or ==
-    def FBO     : F2_3<0b1111, "fbo">;              // Branch on ordered
-  }
+  def FBA     : F2_3<0b1000, "fba">;              // Branch always
+  def FBN     : F2_3<0b0000, "fbn">;              // Branch never
+  def FBU     : F2_3<0b0111, "fbu">;              // Branch on unordered
+  def FBG     : F2_3<0b0110, "fbg">;              // Branch >
+  def FBUG    : F2_3<0b0101, "fbug">;             // Branch on unordered or >
+  def FBL     : F2_3<0b0100, "fbl">;              // Branch <
+  def FBUL    : F2_3<0b0011, "fbul">;             // Branch on unordered or <
+  def FBLG    : F2_3<0b0010, "fblg">;             // Branch < or >
+  def FBNE    : F2_3<0b0001, "fbne">;             // Branch !=
+  def FBE     : F2_3<0b1001, "fbe">;              // Branch ==
+  def FBUE    : F2_3<0b1010, "fbue">;             // Branch on unordered or ==
+  def FBGE    : F2_3<0b1011, "fbge">;             // Branch > or ==
+  def FBUGE   : F2_3<0b1100, "fbuge">;            // Branch unord or > or ==
+  def FBLE    : F2_3<0b1101, "fble">;             // Branch < or ==
+  def FBULE   : F2_3<0b1110, "fbule">;            // Branch unord or < or ==
+  def FBO     : F2_3<0b1111, "fbo">;              // Branch on ordered
 }
 
 // Section A.5: Branch on FP condition codes with prediction - p143




From brukman at cs.uiuc.edu  Thu Jun  5 18:34:00 2003
From: brukman at cs.uiuc.edu (Misha Brukman)
Date: Thu Jun  5 18:34:00 2003
Subject: [llvm-commits] CVS: llvm/lib/Target/Sparc/SparcV9_F2.td
Message-ID: <200306052333.SAA27513@zion.cs.uiuc.edu>


Changes in directory llvm/lib/Target/Sparc:

SparcV9_F2.td updated: 1.2 -> 1.3

---
Log message:

Moved predict and annul fields to the end of each individual instruction
class, because they are currently unused.


---
Diffs of the changes:

Index: llvm/lib/Target/Sparc/SparcV9_F2.td
diff -u llvm/lib/Target/Sparc/SparcV9_F2.td:1.2 llvm/lib/Target/Sparc/SparcV9_F2.td:1.3
--- llvm/lib/Target/Sparc/SparcV9_F2.td:1.2	Mon Jun  2 20:04:04 2003
+++ llvm/lib/Target/Sparc/SparcV9_F2.td	Thu Jun  5 18:33:15 2003
@@ -7,40 +7,42 @@
 //
 class F2 : InstV9 {                   // Format 2 instructions
   bits<3> op2;
-  set op = 0;    // Op = 0
+  set op          = 0;    // Op = 0
   set Inst{24-22} = op2;
 }
 
 // Format 2.1 instructions
 class F2_1<string name> : F2 {
   bits<22> imm;
-  bits<5> rd;
+  bits<5>  rd;
 
-  set Name = name;
+  set Name        = name;
   set Inst{29-25} = rd;
   set Inst{21-0}  = imm;
 }
 
 class F2_br : F2 {                    // Format 2 Branch instruction
-  bit annul;  // All branches have an annul bit
-  set Inst{29} = annul;
   set isBranch    = 1;      // All instances are branch instructions
 }
 
 class F2_2<bits<4> cond, string name> : F2_br { // Format 2.2 instructions
   bits<22> disp;
+  bit      annul;
 
   set Name        = name;
+  set Inst{29}    = annul;
   set Inst{28-25} = cond;
   set Inst{21-0}  = disp;
 }
 
 class F2_3<bits<4> cond, string name> : F2_br { // Format 2.3 instructions
-  bits<2> cc;
+  bits<2>  cc;
   bits<19> disp;
-  bit predict;
+  bit      predict;
+  bit      annul;
 
   set Name        = name;
+  set Inst{29}    = annul;
   set Inst{28-25} = cond;
   set Inst{21-20} = cc;
   set Inst{19}    = predict;
@@ -48,14 +50,15 @@
 }
 
 class F2_4<bits<3> rcond, string name> : F2_br { // Format 2.4 instructions
-  bit        predict;
-  bits<5>    rs1;
-  bits<16>   disp;
+  bits<5>  rs1;
+  bits<16> disp;
+  bit      predict;
+  bit      annul;
 
-  set Name = name;
+  set Name        = name;
+  set Inst{29}    = annul;
   set Inst{28}    = 0;
   set Inst{27-25} = rcond;
-  //  Inst{24-22} = op2 field
   set Inst{21-20} = disp{15-14};
   set Inst{19}    = predict;
   set Inst{18-14} = rs1;




From brukman at cs.uiuc.edu  Thu Jun  5 18:36:01 2003
From: brukman at cs.uiuc.edu (Misha Brukman)
Date: Thu Jun  5 18:36:01 2003
Subject: [llvm-commits] CVS: llvm/lib/Target/Sparc/SparcV9_F3.td
Message-ID: <200306052335.SAA27537@zion.cs.uiuc.edu>


Changes in directory llvm/lib/Target/Sparc:

SparcV9_F3.td updated: 1.10 -> 1.11

---
Log message:

Added missing directive to store the instruction name.


---
Diffs of the changes:

Index: llvm/lib/Target/Sparc/SparcV9_F3.td
diff -u llvm/lib/Target/Sparc/SparcV9_F3.td:1.10 llvm/lib/Target/Sparc/SparcV9_F3.td:1.11
--- llvm/lib/Target/Sparc/SparcV9_F3.td:1.10	Wed Jun  4 19:39:45 2003
+++ llvm/lib/Target/Sparc/SparcV9_F3.td	Thu Jun  5 18:35:11 2003
@@ -217,6 +217,7 @@
 
   set op  = opVal;
   set op3 = op3Val;
+  set Name = name;
   set Inst{26-25} = cc;
   set Inst{18-14} = rs1;
   set Inst{13-5}  = opfVal;




From brukman at cs.uiuc.edu  Thu Jun  5 18:52:01 2003
From: brukman at cs.uiuc.edu (Misha Brukman)
Date: Thu Jun  5 18:52:01 2003
Subject: [llvm-commits] CVS: llvm/lib/Target/Sparc/SparcV9CodeEmitter.cpp
Message-ID: <200306052351.SAA28278@zion.cs.uiuc.edu>


Changes in directory llvm/lib/Target/Sparc:

SparcV9CodeEmitter.cpp updated: 1.12 -> 1.13

---
Log message:

Fixed confusion between register classes and register types.
Now %fcc registers are recognized correctly.


---
Diffs of the changes:

Index: llvm/lib/Target/Sparc/SparcV9CodeEmitter.cpp
diff -u llvm/lib/Target/Sparc/SparcV9CodeEmitter.cpp:1.12 llvm/lib/Target/Sparc/SparcV9CodeEmitter.cpp:1.13
--- llvm/lib/Target/Sparc/SparcV9CodeEmitter.cpp:1.12	Thu Jun  5 15:52:06 2003
+++ llvm/lib/Target/Sparc/SparcV9CodeEmitter.cpp	Thu Jun  5 18:51:10 2003
@@ -475,8 +475,10 @@
     // At least map fakeReg into its class
     fakeReg = TM.getRegInfo().getClassRegNum(fakeReg, regClass);
     // Find the real register number for use in an instruction
-    realReg = getRealRegNum(fakeReg, regClass, MI);
-    std::cerr << "Reg[" << std::dec << fakeReg << "] = " << realReg << "\n";
+    /////realReg = getRealRegNum(fakeReg, regClass, MI);
+    realReg = getRealRegNum(fakeReg, regType, MI);
+    std::cerr << MO << ": Reg[" << std::dec << fakeReg << "] = "
+              << realReg << "\n";
     rv = realReg;
   } else if (MO.isImmediate()) {
     rv = MO.getImmedValue();




From brukman at cs.uiuc.edu  Thu Jun  5 19:02:01 2003
From: brukman at cs.uiuc.edu (Misha Brukman)
Date: Thu Jun  5 19:02:01 2003
Subject: [llvm-commits] CVS: llvm/tools/lli/JIT/Emitter.cpp
Message-ID: <200306060001.TAA28336@zion.cs.uiuc.edu>


Changes in directory llvm/tools/lli/JIT:

Emitter.cpp updated: 1.11 -> 1.12

---
Log message:

Removed debug print statement.


---
Diffs of the changes:

Index: llvm/tools/lli/JIT/Emitter.cpp
diff -u llvm/tools/lli/JIT/Emitter.cpp:1.11 llvm/tools/lli/JIT/Emitter.cpp:1.12
--- llvm/tools/lli/JIT/Emitter.cpp:1.11	Wed Jun  4 14:45:25 2003
+++ llvm/tools/lli/JIT/Emitter.cpp	Thu Jun  5 19:00:54 2003
@@ -80,7 +80,6 @@
             PROT_READ|PROT_WRITE|PROT_EXEC,
             MAP_PRIVATE|MAP_ANON|MAP_FIXED, -1, 0); /* fd = -1 */
   Counter += pageSize*NumPages;
-  std::cerr << "getMemory() returning " << pa << "\n";
 #else
   std::cerr << "This architecture is not supported by the JIT\n";
   abort();




From brukman at cs.uiuc.edu  Thu Jun  5 19:27:01 2003
From: brukman at cs.uiuc.edu (Misha Brukman)
Date: Thu Jun  5 19:27:01 2003
Subject: [llvm-commits] CVS: llvm/lib/Target/Sparc/SparcV9CodeEmitter.cpp
Message-ID: <200306060026.TAA28942@zion.cs.uiuc.edu>


Changes in directory llvm/lib/Target/Sparc:

SparcV9CodeEmitter.cpp updated: 1.13 -> 1.14

---
Log message:

Put all debug print statements under the DEBUG() guard to make output clean so
that tests can automatically diff the output.


---
Diffs of the changes:

Index: llvm/lib/Target/Sparc/SparcV9CodeEmitter.cpp
diff -u llvm/lib/Target/Sparc/SparcV9CodeEmitter.cpp:1.13 llvm/lib/Target/Sparc/SparcV9CodeEmitter.cpp:1.14
--- llvm/lib/Target/Sparc/SparcV9CodeEmitter.cpp:1.13	Thu Jun  5 18:51:10 2003
+++ llvm/lib/Target/Sparc/SparcV9CodeEmitter.cpp	Thu Jun  5 19:26:11 2003
@@ -14,15 +14,15 @@
 #include "llvm/CodeGen/MachineInstr.h"
 #include "llvm/Target/TargetMachine.h"
 #include "llvm/Target/TargetData.h"
+#include "Support/Statistic.h"
 #include "Support/hash_set"
 #include "SparcInternals.h"
 #include "SparcV9CodeEmitter.h"
 
 bool UltraSparc::addPassesToEmitMachineCode(PassManager &PM,
                                             MachineCodeEmitter &MCE) {
-  //PM.add(new SparcV9CodeEmitter(MCE));
-  //MachineCodeEmitter *M = MachineCodeEmitter::createDebugMachineCodeEmitter();
-  MachineCodeEmitter *M = MachineCodeEmitter::createFilePrinterEmitter(MCE);
+  MachineCodeEmitter *M = &MCE;
+  DEBUG(MachineCodeEmitter::createFilePrinterEmitter(MCE));
   PM.add(new SparcV9CodeEmitter(*this, *M));
   PM.add(createMachineCodeDestructionPass()); // Free stuff no longer needed
   return false;
@@ -182,7 +182,7 @@
 void JITResolver::CompilationCallback() {
   uint64_t CameFrom = (uint64_t)(intptr_t)__builtin_return_address(0);
   int64_t Target = (int64_t)TheJITResolver->resolveFunctionReference(CameFrom);
-  std::cerr << "In callback! Addr=0x" << std::hex << CameFrom << "\n";
+  DEBUG(std::cerr << "In callback! Addr=0x" << std::hex << CameFrom << "\n");
 
   // Rewrite the call target... so that we don't fault every time we execute
   // the call.
@@ -275,8 +275,8 @@
 uint64_t JITResolver::emitStubForFunction(Function *F) {
   MCE.startFunctionStub(*F, 6);
 
-  std::cerr << "Emitting stub at addr: 0x" 
-            << std::hex << MCE.getCurrentPCValue() << "\n";
+  DEBUG(std::cerr << "Emitting stub at addr: 0x" 
+                  << std::hex << MCE.getCurrentPCValue() << "\n");
 
   unsigned o6 = SparcIntRegClass::o6;
   // save %sp, -192, %sp
@@ -289,7 +289,8 @@
 
   int64_t CallTarget = (Addr-CurrPC) >> 2;
   if (CallTarget >= (1 << 30) || CallTarget <= -(1 << 30)) {
-    std::cerr << "Call target beyond 30 bit limit of CALL: " <<CallTarget<<"\n";
+    std::cerr << "Call target beyond 30 bit limit of CALL: " 
+              << CallTarget << "\n";
     abort();
   }
   // call CallTarget              ;; invoke the callback
@@ -403,30 +404,29 @@
                   // or things that get fixed up later by the JIT.
 
   if (MO.isVirtualRegister()) {
-    std::cerr << "ERROR: virtual register found in machine code.\n";
+    DEBUG(std::cerr << "ERROR: virtual register found in machine code.\n");
     abort();
   } else if (MO.isPCRelativeDisp()) {
-    std::cerr << "PCRelativeDisp: ";
+    DEBUG(std::cerr << "PCRelativeDisp: ");
     Value *V = MO.getVRegValue();
     if (BasicBlock *BB = dyn_cast<BasicBlock>(V)) {
-      std::cerr << "Saving reference to BB (VReg)\n";
+      DEBUG(std::cerr << "Saving reference to BB (VReg)\n");
       unsigned* CurrPC = (unsigned*)(intptr_t)MCE.getCurrentPCValue();
       BBRefs.push_back(std::make_pair(BB, std::make_pair(CurrPC, &MI)));
     } else if (const Constant *C = dyn_cast<Constant>(V)) {
       if (ConstantMap.find(C) != ConstantMap.end()) {
         rv = (int64_t)MCE.getConstantPoolEntryAddress(ConstantMap[C]);
-        std::cerr << "const: 0x" << std::hex << rv
-                  << "\n" << std::dec;
+        DEBUG(std::cerr << "const: 0x" << std::hex << rv << "\n");
       } else {
-        std::cerr << "ERROR: constant not in map:" << MO << "\n";
+        DEBUG(std::cerr << "ERROR: constant not in map:" << MO << "\n");
         abort();
       }
     } else if (GlobalValue *GV = dyn_cast<GlobalValue>(V)) {
       // same as MO.isGlobalAddress()
-      std::cerr << "GlobalValue: ";
+      DEBUG(std::cerr << "GlobalValue: ");
       // external function calls, etc.?
       if (Function *F = dyn_cast<Function>(GV)) {
-        std::cerr << "Function: ";
+        DEBUG(std::cerr << "Function: ");
         if (F->isExternal()) {
           // Sparc backend broken: this MO should be `ExternalSymbol'
           rv = (int64_t)MCE.getGlobalValueAddress(F->getName());
@@ -434,31 +434,30 @@
           rv = (int64_t)MCE.getGlobalValueAddress(F);
         }
         if (rv == 0) {
-          std::cerr << "not yet generated\n";
+          DEBUG(std::cerr << "not yet generated\n");
           // Function has not yet been code generated!
           TheJITResolver->addFunctionReference(MCE.getCurrentPCValue(), F);
           // Delayed resolution...
           rv = TheJITResolver->getLazyResolver(F);
         } else {
-          std::cerr << "already generated: 0x" << std::hex << rv << "\n" 
-                    << std::dec;
+          DEBUG(std::cerr << "already generated: 0x" << std::hex << rv << "\n");
         }
       } else {
-        std::cerr << "not a function: " << *GV << "\n";
+        DEBUG(std::cerr << "not a function: " << *GV << "\n");
         abort();
       }
       // The real target of the call is Addr = PC + (rv * 4)
       // So undo that: give the instruction (Addr - PC) / 4
       if (MI.getOpcode() == V9::CALL) {
         int64_t CurrPC = MCE.getCurrentPCValue();
-        std::cerr << "rv addr: 0x" << std::hex << rv << "\n";
-        std::cerr << "curr PC: 0x" << CurrPC << "\n";
+        DEBUG(std::cerr << "rv addr: 0x" << std::hex << rv << "\n"
+                        << "curr PC: 0x" << CurrPC << "\n");
         rv = (rv - CurrPC) >> 2;
         if (rv >= (1<<29) || rv <= -(1<<29)) {
           std::cerr << "addr out of bounds for the 30-bit call: " << rv << "\n";
           abort();
         }
-        std::cerr << "returning addr: 0x" << rv << "\n" << std::dec;
+        DEBUG(std::cerr << "returning addr: 0x" << rv << "\n");
       }
     } else {
       std::cerr << "ERROR: PC relative disp unhandled:" << MO << "\n";
@@ -477,21 +476,21 @@
     // Find the real register number for use in an instruction
     /////realReg = getRealRegNum(fakeReg, regClass, MI);
     realReg = getRealRegNum(fakeReg, regType, MI);
-    std::cerr << MO << ": Reg[" << std::dec << fakeReg << "] = "
-              << realReg << "\n";
+    DEBUG(std::cerr << MO << ": Reg[" << std::dec << fakeReg << "] = "
+                    << realReg << "\n");
     rv = realReg;
   } else if (MO.isImmediate()) {
     rv = MO.getImmedValue();
-    std::cerr << "immed: " << rv << "\n";
+    DEBUG(std::cerr << "immed: " << rv << "\n");
   } else if (MO.isGlobalAddress()) {
-    std::cerr << "GlobalAddress: not PC-relative\n";
+    DEBUG(std::cerr << "GlobalAddress: not PC-relative\n");
     rv = (int64_t)
       (intptr_t)getGlobalAddress(cast<GlobalValue>(MO.getVRegValue()),
                                  MI, MO.isPCRelative());
   } else if (MO.isMachineBasicBlock()) {
     // Duplicate code of the above case for VirtualRegister, BasicBlock... 
     // It should really hit this case, but Sparc backend uses VRegs instead
-    std::cerr << "Saving reference to MBB\n";
+    DEBUG(std::cerr << "Saving reference to MBB\n");
     BasicBlock *BB = MO.getMachineBasicBlock()->getBasicBlock();
     unsigned* CurrPC = (unsigned*)(intptr_t)MCE.getCurrentPCValue();
     BBRefs.push_back(std::make_pair(BB, std::make_pair(CurrPC, &MI)));
@@ -537,9 +536,9 @@
 
 bool SparcV9CodeEmitter::runOnMachineFunction(MachineFunction &MF) {
   MCE.startFunction(MF);
-  std::cerr << "Starting function " << MF.getFunction()->getName()
+  DEBUG(std::cerr << "Starting function " << MF.getFunction()->getName()
             << ", address: " << "0x" << std::hex 
-            << (long)MCE.getCurrentPCValue() << "\n";
+            << (long)MCE.getCurrentPCValue() << "\n");
 
   // The Sparc backend does not use MachineConstantPool;
   // instead, it has its own constant pool implementation.
@@ -551,7 +550,8 @@
   {
     Constant *C = (Constant*)*I;
     unsigned idx = MCP.getConstantPoolIndex(C);
-    std::cerr << "Mapping constant 0x" << (intptr_t)C << " to " << idx << "\n";
+    DEBUG(std::cerr << "Mapping constant 0x" << (intptr_t)C << " to " 
+                    << idx << "\n");
     ConstantMap[C] = idx;
   }  
   MCE.emitConstantPool(&MCP);
@@ -560,14 +560,15 @@
     emitBasicBlock(*I);
   MCE.finishFunction(MF);
 
-  std::cerr << "Finishing function " << MF.getFunction()->getName() << "\n";
+  DEBUG(std::cerr << "Finishing function " << MF.getFunction()->getName() 
+                  << "\n");
   ConstantMap.clear();
   for (unsigned i = 0, e = BBRefs.size(); i != e; ++i) {
     long Location = BBLocations[BBRefs[i].first];
     unsigned *Ref = BBRefs[i].second.first;
     MachineInstr *MI = BBRefs[i].second.second;
-    std::cerr << "Fixup @" << std::hex << Ref << " to " << Location
-              << " in instr: " << std::dec << *MI << "\n";
+    DEBUG(std::cerr << "Fixup @" << std::hex << Ref << " to " << Location
+                    << " in instr: " << std::dec << *MI << "\n");
   }
 
   // Resolve branches to BasicBlocks for the entire function
@@ -575,7 +576,7 @@
     long Location = BBLocations[BBRefs[i].first];
     unsigned *Ref = BBRefs[i].second.first;
     MachineInstr *MI = BBRefs[i].second.second;
-    std::cerr << "attempting to resolve BB: " << i << "\n";
+    DEBUG(std::cerr << "attempting to resolve BB: " << i << "\n");
     for (unsigned ii = 0, ee = MI->getNumOperands(); ii != ee; ++ii) {
       MachineOperand &op = MI->getOperand(ii);
       if (op.isPCRelativeDisp()) {
@@ -596,7 +597,7 @@
         else if (hiBits32) { MI->setOperandHi32(ii); }
         else if (loBits64) { MI->setOperandLo64(ii); }
         else if (hiBits64) { MI->setOperandHi64(ii); }
-        std::cerr << "Rewrote BB ref: ";
+        DEBUG(std::cerr << "Rewrote BB ref: ");
         unsigned fixedInstr = SparcV9CodeEmitter::getBinaryCodeForInstr(*MI);
         *Ref = fixedInstr;
         break;




From brukman at cs.uiuc.edu  Thu Jun  5 19:28:02 2003
From: brukman at cs.uiuc.edu (Misha Brukman)
Date: Thu Jun  5 19:28:02 2003
Subject: [llvm-commits] CVS: llvm/utils/TableGen/CodeEmitterGen.cpp
Message-ID: <200306060027.TAA28963@zion.cs.uiuc.edu>


Changes in directory llvm/utils/TableGen:

CodeEmitterGen.cpp updated: 1.7 -> 1.8

---
Log message:

All debug print statements are now output with the DEBUG() guard to make
output clean so that tests can automatically diff the output.


---
Diffs of the changes:

Index: llvm/utils/TableGen/CodeEmitterGen.cpp
diff -u llvm/utils/TableGen/CodeEmitterGen.cpp:1.7 llvm/utils/TableGen/CodeEmitterGen.cpp:1.8
--- llvm/utils/TableGen/CodeEmitterGen.cpp:1.7	Thu Jun  5 18:15:25 2003
+++ llvm/utils/TableGen/CodeEmitterGen.cpp	Thu Jun  5 19:27:02 2003
@@ -21,14 +21,14 @@
   o << "unsigned " << ClassName
     << "getBinaryCodeForInstr(MachineInstr &MI) {\n"
     << "  unsigned Value = 0;\n"
-    << "  std::cerr << MI;\n"
+    << "  DEBUG(std::cerr << MI);\n"
     << "  switch (MI.getOpcode()) {\n";
   for (std::vector<Record*>::iterator I = Insts.begin(), E = Insts.end();
        I != E; ++I)
   {
     Record *R = *I;
     o << "    case " << Namespace << R->getName() << ": {\n"
-      << "      std::cerr << \"Emitting " << R->getName() << "\\n\";\n";
+      << "      DEBUG(std::cerr << \"Emitting " << R->getName() << "\\n\");\n";
 
     const RecordVal *InstVal = R->getValue("Inst");
     Init *InitVal = InstVal->getValue();
@@ -115,7 +115,7 @@
       << "    }\n";
   }
   o << "  default:\n"
-    << "    std::cerr << \"Not supported instr: \" << MI << \"\\n\";\n"
+    << "    DEBUG(std::cerr << \"Not supported instr: \" << MI << \"\\n\");\n"
     << "    abort();\n"
     << "  }\n"
     << "  return Value;\n"




From brukman at cs.uiuc.edu  Thu Jun  5 22:35:01 2003
From: brukman at cs.uiuc.edu (Misha Brukman)
Date: Thu Jun  5 22:35:01 2003
Subject: [llvm-commits] CVS: llvm/lib/Target/Sparc/SparcV9.td
Message-ID: <200306060334.WAA30683@zion.cs.uiuc.edu>


Changes in directory llvm/lib/Target/Sparc:

SparcV9.td updated: 1.18 -> 1.19

---
Log message:

The SUB*i instructions belong to a different class than their SUB*r brethren.


---
Diffs of the changes:

Index: llvm/lib/Target/Sparc/SparcV9.td
diff -u llvm/lib/Target/Sparc/SparcV9.td:1.18 llvm/lib/Target/Sparc/SparcV9.td:1.19
--- llvm/lib/Target/Sparc/SparcV9.td:1.18	Thu Jun  5 18:30:27 2003
+++ llvm/lib/Target/Sparc/SparcV9.td	Thu Jun  5 22:34:47 2003
@@ -745,12 +745,12 @@
 
 // Section A.56: Subtract - p233
 def SUBr    : F3_1<2, 0b000100, "sub">;                   // sub r, r, r
-def SUBi    : F3_1<2, 0b000100, "sub">;                   // sub r, i, r
+def SUBi    : F3_2<2, 0b000100, "sub">;                   // sub r, i, r
 def SUBccr  : F3_1<2, 0b010100, "subcc">;                 // subcc r, r, r
-def SUBcci  : F3_1<2, 0b010100, "subcc">;                 // subcc r, i, r
+def SUBcci  : F3_2<2, 0b010100, "subcc">;                 // subcc r, i, r
 def SUBCr   : F3_1<2, 0b001100, "subc">;                  // subc r, r, r
-def SUBCi   : F3_1<2, 0b001100, "subc">;                  // subc r, i, r
+def SUBCi   : F3_2<2, 0b001100, "subc">;                  // subc r, i, r
 def SUBCccr : F3_1<2, 0b011100, "subccc">;                // subccc r, r, r
-def SUBCcci : F3_1<2, 0b011100, "subccc">;                // subccc r, i, r
+def SUBCcci : F3_2<2, 0b011100, "subccc">;                // subccc r, i, r
 
 // FIXME: More...?




From brukman at cs.uiuc.edu  Thu Jun  5 22:36:01 2003
From: brukman at cs.uiuc.edu (Misha Brukman)
Date: Thu Jun  5 22:36:01 2003
Subject: [llvm-commits] CVS: llvm/lib/Target/Sparc/SparcV9CodeEmitter.cpp
Message-ID: <200306060335.WAA30696@zion.cs.uiuc.edu>


Changes in directory llvm/lib/Target/Sparc:

SparcV9CodeEmitter.cpp updated: 1.14 -> 1.15

---
Log message:

* If a global is not a function, just ask the MachineCodeEmitter for the addr
* Do not block a print statement with a DEBUG() guard if we're going to abort()


---
Diffs of the changes:

Index: llvm/lib/Target/Sparc/SparcV9CodeEmitter.cpp
diff -u llvm/lib/Target/Sparc/SparcV9CodeEmitter.cpp:1.14 llvm/lib/Target/Sparc/SparcV9CodeEmitter.cpp:1.15
--- llvm/lib/Target/Sparc/SparcV9CodeEmitter.cpp:1.14	Thu Jun  5 19:26:11 2003
+++ llvm/lib/Target/Sparc/SparcV9CodeEmitter.cpp	Thu Jun  5 22:35:37 2003
@@ -404,7 +404,7 @@
                   // or things that get fixed up later by the JIT.
 
   if (MO.isVirtualRegister()) {
-    DEBUG(std::cerr << "ERROR: virtual register found in machine code.\n");
+    std::cerr << "ERROR: virtual register found in machine code.\n";
     abort();
   } else if (MO.isPCRelativeDisp()) {
     DEBUG(std::cerr << "PCRelativeDisp: ");
@@ -418,7 +418,7 @@
         rv = (int64_t)MCE.getConstantPoolEntryAddress(ConstantMap[C]);
         DEBUG(std::cerr << "const: 0x" << std::hex << rv << "\n");
       } else {
-        DEBUG(std::cerr << "ERROR: constant not in map:" << MO << "\n");
+        std::cerr << "ERROR: constant not in map:" << MO << "\n";
         abort();
       }
     } else if (GlobalValue *GV = dyn_cast<GlobalValue>(V)) {
@@ -444,7 +444,7 @@
         }
       } else {
         DEBUG(std::cerr << "not a function: " << *GV << "\n");
-        abort();
+        rv = (int64_t)MCE.getGlobalValueAddress(GV);
       }
       // The real target of the call is Addr = PC + (rv * 4)
       // So undo that: give the instruction (Addr - PC) / 4




From lattner at cs.uiuc.edu  Thu Jun  5 23:01:01 2003
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Thu Jun  5 23:01:01 2003
Subject: [llvm-commits] CVS: llvm/lib/Target/X86/X86CodeEmitter.cpp
Message-ID: <200306060400.XAA13963@apoc.cs.uiuc.edu>


Changes in directory llvm/lib/Target/X86:

X86CodeEmitter.cpp updated: 1.26 -> 1.27

---
Log message:

Add statistic for # machine instrs emitted
Add GROSS HACK to get CompilationCallback to work when compiled in release mode


---
Diffs of the changes:

Index: llvm/lib/Target/X86/X86CodeEmitter.cpp
diff -u llvm/lib/Target/X86/X86CodeEmitter.cpp:1.26 llvm/lib/Target/X86/X86CodeEmitter.cpp:1.27
--- llvm/lib/Target/X86/X86CodeEmitter.cpp:1.26	Tue Jun  3 10:31:23 2003
+++ llvm/lib/Target/X86/X86CodeEmitter.cpp	Thu Jun  5 23:00:05 2003
@@ -12,8 +12,12 @@
 #include "llvm/CodeGen/MachineFunctionPass.h"
 #include "llvm/CodeGen/MachineInstr.h"
 #include "llvm/Value.h"
+#include "Support/Statistic.h"
 
 namespace {
+  Statistic<>
+  NumEmitted("x86-emitter", "Number of machine instructions emitted");
+
   class JITResolver {
     MachineCodeEmitter &MCE;
 
@@ -71,11 +75,17 @@
 void JITResolver::CompilationCallback() {
   unsigned *StackPtr = (unsigned*)__builtin_frame_address(0);
   unsigned RetAddr = (unsigned)(intptr_t)__builtin_return_address(0);
-
   assert(StackPtr[1] == RetAddr &&
          "Could not find return address on the stack!");
   bool isStub = ((unsigned char*)RetAddr)[0] == 0xCD;  // Interrupt marker?
 
+  // FIXME FIXME FIXME FIXME: __builtin_frame_address doesn't work if frame
+  // pointer elimination has been performed.  Having a variable sized alloca
+  // disables frame pointer elimination currently, even if it's dead.  This is a
+  // gross hack.
+  alloca(10+isStub);
+  // FIXME FIXME FIXME FIXME
+
   // The call instruction should have pushed the return value onto the stack...
   RetAddr -= 4;  // Backtrack to the reference itself...
 
@@ -429,6 +439,8 @@
 }
 
 void Emitter::emitInstruction(MachineInstr &MI) {
+  NumEmitted++;  // Keep track of the # of mi's emitted
+
   unsigned Opcode = MI.getOpcode();
   const TargetInstrDescriptor &Desc = II->get(Opcode);
 




From brukman at cs.uiuc.edu  Thu Jun  5 23:42:00 2003
From: brukman at cs.uiuc.edu (Misha Brukman)
Date: Thu Jun  5 23:42:00 2003
Subject: [llvm-commits] CVS: llvm/lib/Target/Sparc/SparcV9CodeEmitter.cpp
Message-ID: <200306060441.XAA32022@zion.cs.uiuc.edu>


Changes in directory llvm/lib/Target/Sparc:

SparcV9CodeEmitter.cpp updated: 1.15 -> 1.16

---
Log message:

Fixed a bunch of test cases in test/Regression/Jello which could not get the
address of a floating-point (allocated via ConstantPool) correctly.


---
Diffs of the changes:

Index: llvm/lib/Target/Sparc/SparcV9CodeEmitter.cpp
diff -u llvm/lib/Target/Sparc/SparcV9CodeEmitter.cpp:1.15 llvm/lib/Target/Sparc/SparcV9CodeEmitter.cpp:1.16
--- llvm/lib/Target/Sparc/SparcV9CodeEmitter.cpp:1.15	Thu Jun  5 22:35:37 2003
+++ llvm/lib/Target/Sparc/SparcV9CodeEmitter.cpp	Thu Jun  5 23:41:22 2003
@@ -22,7 +22,7 @@
 bool UltraSparc::addPassesToEmitMachineCode(PassManager &PM,
                                             MachineCodeEmitter &MCE) {
   MachineCodeEmitter *M = &MCE;
-  DEBUG(MachineCodeEmitter::createFilePrinterEmitter(MCE));
+  DEBUG(M = MachineCodeEmitter::createFilePrinterEmitter(MCE));
   PM.add(new SparcV9CodeEmitter(*this, *M));
   PM.add(createMachineCodeDestructionPass()); // Free stuff no longer needed
   return false;
@@ -443,8 +443,19 @@
           DEBUG(std::cerr << "already generated: 0x" << std::hex << rv << "\n");
         }
       } else {
-        DEBUG(std::cerr << "not a function: " << *GV << "\n");
         rv = (int64_t)MCE.getGlobalValueAddress(GV);
+        if (rv == 0) {
+          if (Constant *C = ConstantPointerRef::get(GV)) {
+            if (ConstantMap.find(C) != ConstantMap.end()) {
+              rv = MCE.getConstantPoolEntryAddress(ConstantMap[C]);
+            } else {
+              std::cerr << "Constant: 0x" << std::hex << &*C << std::dec
+                        << ", " << *V << " not found in ConstantMap!\n";
+              abort();
+            }
+          }
+        }
+        DEBUG(std::cerr << "Global addr: " << rv << "\n");
       }
       // The real target of the call is Addr = PC + (rv * 4)
       // So undo that: give the instruction (Addr - PC) / 4




From brukman at cs.uiuc.edu  Fri Jun  6 01:51:01 2003
From: brukman at cs.uiuc.edu (Misha Brukman)
Date: Fri Jun  6 01:51:01 2003
Subject: [llvm-commits] CVS: llvm/test/Regression/Jello/2003-01-04-ArgumentBug.ll
Message-ID: <200306060650.BAA05160@zion.cs.uiuc.edu>


Changes in directory llvm/test/Regression/Jello:

2003-01-04-ArgumentBug.ll updated: 1.1 -> 1.2

---
Log message:

Simplify test case: remove declaration of __main() and call to it.


---
Diffs of the changes:

Index: llvm/test/Regression/Jello/2003-01-04-ArgumentBug.ll
diff -u llvm/test/Regression/Jello/2003-01-04-ArgumentBug.ll:1.1 llvm/test/Regression/Jello/2003-01-04-ArgumentBug.ll:1.2
--- llvm/test/Regression/Jello/2003-01-04-ArgumentBug.ll:1.1	Sun Jan 12 19:03:16 2003
+++ llvm/test/Regression/Jello/2003-01-04-ArgumentBug.ll	Fri Jun  6 01:50:43 2003
@@ -1,18 +1,13 @@
 
 implementation   ; Functions:
 
-declare void %__main()
-
 int %foo(int %X, int %Y, double %A) {
-bb0:		; No predecessors!
 	%cond212 = setne double %A, 1.000000e+00		; <bool> [#uses=1]
 	%cast110 = cast bool %cond212 to int		; <int> [#uses=1]
 	ret int %cast110
 }
 
 int %main() {
-bb0:		; No predecessors!
-	call void %__main( )
 	%reg212 = call int %foo( int 0, int 1, double 1.000000e+00 )		; <int> [#uses=1]
 	ret int %reg212
 }




From brukman at cs.uiuc.edu  Fri Jun  6 01:53:01 2003
From: brukman at cs.uiuc.edu (Misha Brukman)
Date: Fri Jun  6 01:53:01 2003
Subject: [llvm-commits] CVS: llvm/tools/lli/JIT/Emitter.cpp
Message-ID: <200306060652.BAA05185@zion.cs.uiuc.edu>


Changes in directory llvm/tools/lli/JIT:

Emitter.cpp updated: 1.12 -> 1.13

---
Log message:

Output function address as hex.


---
Diffs of the changes:

Index: llvm/tools/lli/JIT/Emitter.cpp
diff -u llvm/tools/lli/JIT/Emitter.cpp:1.12 llvm/tools/lli/JIT/Emitter.cpp:1.13
--- llvm/tools/lli/JIT/Emitter.cpp:1.12	Thu Jun  5 19:00:54 2003
+++ llvm/tools/lli/JIT/Emitter.cpp	Fri Jun  6 01:52:35 2003
@@ -103,9 +103,8 @@
   ConstantPoolAddresses.clear();
   NumBytes += CurByte-CurBlock;
 
-  DEBUG(std::cerr << "Finished CodeGen of [0x" << std::hex
-                  << (unsigned)(intptr_t)CurBlock
-                  << std::dec << "] Function: " << F.getFunction()->getName()
+  DEBUG(std::cerr << "Finished CodeGen of [0x" << (void*)CurBlock
+                  << "] Function: " << F.getFunction()->getName()
                   << ": " << CurByte-CurBlock << " bytes of text\n");
 }
 




From brukman at cs.uiuc.edu  Fri Jun  6 02:01:01 2003
From: brukman at cs.uiuc.edu (Misha Brukman)
Date: Fri Jun  6 02:01:01 2003
Subject: [llvm-commits] CVS: llvm/tools/lli/JIT/JIT.cpp
Message-ID: <200306060700.CAA05203@zion.cs.uiuc.edu>


Changes in directory llvm/tools/lli/JIT:

JIT.cpp updated: 1.6 -> 1.7

---
Log message:

::: HACK ALERT ::: HACK ALERT ::: HACK ALERT ::: HACK ALERT ::: HACK ALERT :::

The JIT is designed to code-generate a function at-a-time. That means that any
pass can only make local changes to its function. Period.

Because the Sparc PreSelection pass claims to be a BasicBlock pass while adding
globals to the Module, it cannot be run with the other passes, because by this
time, the globals have been output already by the JIT, and the addresses of any
globals appearing AFTER this point are not recognized.

However, the PreSelection pass is a requirement for correctness in the Sparc
codegen path, so it MUST be run.

::: HACK ALERT ::: HACK ALERT ::: HACK ALERT ::: HACK ALERT ::: HACK ALERT :::


---
Diffs of the changes:

Index: llvm/tools/lli/JIT/JIT.cpp
diff -u llvm/tools/lli/JIT/JIT.cpp:1.6 llvm/tools/lli/JIT/JIT.cpp:1.7
--- llvm/tools/lli/JIT/JIT.cpp:1.6	Sun Jun  1 22:23:16 2003
+++ llvm/tools/lli/JIT/JIT.cpp	Fri Jun  6 01:59:55 2003
@@ -11,6 +11,9 @@
 #include "llvm/Module.h"
 #include "Support/CommandLine.h"
 
+// FIXME: REMOVE THIS
+#include "llvm/PassManager.h"
+
 namespace {
   cl::opt<std::string>
   Arch("march", cl::desc("Architecture: `x86' or `sparc'"), cl::Prefix,
@@ -27,7 +30,6 @@
 
 }
 
-
 /// createJIT - Create an return a new JIT compiler if there is one available
 /// for the current target.  Otherwise it returns null.
 ///
@@ -65,6 +67,17 @@
   MCE = createEmitter(*this);
 
   setupPassManager();
+
+  // THIS GOES BEYOND UGLY HACKS
+  if (TM.getName() == "UltraSparc-Native") {
+    extern Pass *createPreSelectionPass(TargetMachine &TM);
+    PassManager PM;
+    // Specialize LLVM code for this target machine and then
+    // run basic dataflow optimizations on LLVM code.
+    PM.add(createPreSelectionPass(TM));
+    PM.run(*M);
+  }
+
   emitGlobals();
 }
 




From lattner at cs.uiuc.edu  Fri Jun  6 02:11:02 2003
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Fri Jun  6 02:11:02 2003
Subject: [llvm-commits] CVS: llvm/lib/CWriter/Writer.cpp
Message-ID: <200306060710.CAA27330@apoc.cs.uiuc.edu>


Changes in directory llvm/lib/CWriter:

Writer.cpp updated: 1.91 -> 1.92

---
Log message:

Don't output explicit initializers for globals that are zero initialized


---
Diffs of the changes:

Index: llvm/lib/CWriter/Writer.cpp
diff -u llvm/lib/CWriter/Writer.cpp:1.91 llvm/lib/CWriter/Writer.cpp:1.92
--- llvm/lib/CWriter/Writer.cpp:1.91	Sun Jun  1 22:10:53 2003
+++ llvm/lib/CWriter/Writer.cpp	Fri Jun  6 02:10:24 2003
@@ -73,7 +73,6 @@
     void printModule(Module *M);
     void printSymbolTable(const SymbolTable &ST);
     void printContainedStructs(const Type *Ty, std::set<const StructType *> &);
-    void printGlobal(const GlobalVariable *GV);
     void printFunctionSignature(const Function *F, bool Prototype);
 
     void printFunction(Function *);
@@ -619,9 +618,10 @@
         if (I->hasInternalLinkage())
           Out << "static ";
         printType(Out, I->getType()->getElementType(), getValueName(I));
-      
-        Out << " = " ;
-        writeOperand(I->getInitializer());
+        if (!I->getInitializer()->isNullValue()) {
+          Out << " = " ;
+          writeOperand(I->getInitializer());
+        }
         Out << ";\n";
       }
   }




From brukman at cs.uiuc.edu  Fri Jun  6 02:12:02 2003
From: brukman at cs.uiuc.edu (Misha Brukman)
Date: Fri Jun  6 02:12:02 2003
Subject: [llvm-commits] CVS: llvm/lib/Target/Sparc/Sparc.cpp
Message-ID: <200306060711.CAA05256@zion.cs.uiuc.edu>


Changes in directory llvm/lib/Target/Sparc:

Sparc.cpp updated: 1.66 -> 1.67

---
Log message:

* Removed PreSelection pass because that is now done in the JIT
* Removed instruction scheduling as it is too slow to run in a JIT environment
* Removed other passes because they aren't necessary and can slow JIT down


---
Diffs of the changes:

Index: llvm/lib/Target/Sparc/Sparc.cpp
diff -u llvm/lib/Target/Sparc/Sparc.cpp:1.66 llvm/lib/Target/Sparc/Sparc.cpp:1.67
--- llvm/lib/Target/Sparc/Sparc.cpp:1.66	Wed Jun  4 17:07:12 2003
+++ llvm/lib/Target/Sparc/Sparc.cpp	Fri Jun  6 02:11:16 2003
@@ -198,34 +198,24 @@
 // generation for the UltraSparc.
 //
 bool UltraSparc::addPassesToJITCompile(PassManager &PM) {
+  const TargetData &TD = getTargetData();
+
+  PM.add(new TargetData("lli", TD.isLittleEndian(), TD.getPointerSize(),
+                        TD.getPointerAlignment(), TD.getDoubleAlignment()));
+
+  // Replace malloc and free instructions with library calls.
+  // Do this after tracing until lli implements these lib calls.
+  // For now, it will emulate malloc and free internally.
+  PM.add(createLowerAllocationsPass());
+
   // FIXME: implement the switch instruction in the instruction selector.
   PM.add(createLowerSwitchPass());
 
   // Construct and initialize the MachineFunction object for this fn.
   PM.add(createMachineCodeConstructionPass(*this));
 
-  //Insert empty stackslots in the stack frame of each function
-  //so %fp+offset-8 and %fp+offset-16 are empty slots now!
-  PM.add(createStackSlotsPass(*this));
-
-  // Specialize LLVM code for this target machine and then
-  // run basic dataflow optimizations on LLVM code.
-#if 0
-  if (!DisablePreSelect) {
-    PM.add(createPreSelectionPass(*this));
-    PM.add(createReassociatePass());
-    PM.add(createLICMPass());
-    PM.add(createGCSEPass());
-  }
-#endif
-
   PM.add(createInstructionSelectionPass(*this));
 
-#if 0
-  if (!DisableSched)
-    PM.add(createInstructionSchedulingWithSSAPass(*this));
-#endif
-
   // new pass: convert Value* in MachineOperand to an unsigned register
   // this brings it in line with what the X86 JIT's RegisterAllocator expects
   //PM.add(createAddRegNumToValuesPass());
@@ -233,10 +223,8 @@
   PM.add(getRegisterAllocator(*this));
   PM.add(getPrologEpilogInsertionPass());
 
-#if 0
   if (!DisablePeephole)
     PM.add(createPeepholeOptsPass(*this));
-#endif
 
   return false; // success!
 }




From brukman at cs.uiuc.edu  Fri Jun  6 02:59:00 2003
From: brukman at cs.uiuc.edu (Michael Brukman)
Date: Fri Jun  6 02:59:00 2003
Subject: [llvm-commits] CVS: llvm/test/Regression/Jello/test-branch.ll
Message-ID: <200306060758.CAA22166@trinity.cs.uiuc.edu>


Changes in directory llvm/test/Regression/Jello:

test-branch.ll updated: 1.4 -> 1.5

---
Log message:

Return 'int 0' instead of void so that the test can be considered to pass.


---
Diffs of the changes:

Index: llvm/test/Regression/Jello/test-branch.ll
diff -u llvm/test/Regression/Jello/test-branch.ll:1.4 llvm/test/Regression/Jello/test-branch.ll:1.5
--- llvm/test/Regression/Jello/test-branch.ll:1.4	Thu Dec 12 23:28:50 2002
+++ llvm/test/Regression/Jello/test-branch.ll	Fri Jun  6 02:58:29 2003
@@ -1,9 +1,9 @@
 ; test unconditional branch
-void %main() {
+int %main() {
 	br label %Test
 Test:
 	%X = seteq int 0, 4
 	br bool %X, label %Test, label %Label
 Label:
-	ret void
+	ret int 0
 }




From brukman at cs.uiuc.edu  Fri Jun  6 03:01:01 2003
From: brukman at cs.uiuc.edu (Michael Brukman)
Date: Fri Jun  6 03:01:01 2003
Subject: [llvm-commits] CVS: llvm/test/Regression/Jello/test-setcond-fp.ll
Message-ID: <200306060800.DAA22249@trinity.cs.uiuc.edu>


Changes in directory llvm/test/Regression/Jello:

test-setcond-fp.ll updated: 1.1 -> 1.2

---
Log message:

Return 'int 0' instead of 'void' so that the test can be seen as successful.


---
Diffs of the changes:

Index: llvm/test/Regression/Jello/test-setcond-fp.ll
diff -u llvm/test/Regression/Jello/test-setcond-fp.ll:1.1 llvm/test/Regression/Jello/test-setcond-fp.ll:1.2
--- llvm/test/Regression/Jello/test-setcond-fp.ll:1.1	Thu Nov  7 11:59:21 2002
+++ llvm/test/Regression/Jello/test-setcond-fp.ll	Fri Jun  6 03:00:40 2003
@@ -1,5 +1,5 @@
 
-void %main() {
+int %main() {
 	%double1 = add double 0.0, 0.0
 	%double2 = add double 0.0, 0.0
 	%float1 = add float 0.0, 0.0
@@ -16,5 +16,5 @@
 	%test58 = setle double %double1, %double2
 	%test59 = setlt double %double1, %double2
 	%test60 = setne double %double1, %double2
-	ret void
+	ret int 0
 }




From brukman at cs.uiuc.edu  Fri Jun  6 04:53:01 2003
From: brukman at cs.uiuc.edu (Misha Brukman)
Date: Fri Jun  6 04:53:01 2003
Subject: [llvm-commits] CVS: llvm/lib/Target/Sparc/PrologEpilogCodeInserter.cpp SparcInstr.def SparcInstrInfo.cpp SparcInstrSelection.cpp SparcInstrSelectionSupport.h SparcRegInfo.cpp SparcV9.td
Message-ID: <200306060952.EAA07420@zion.cs.uiuc.edu>


Changes in directory llvm/lib/Target/Sparc:

PrologEpilogCodeInserter.cpp updated: 1.26 -> 1.27
SparcInstr.def updated: 1.19 -> 1.20
SparcInstrInfo.cpp updated: 1.46 -> 1.47
SparcInstrSelection.cpp updated: 1.101 -> 1.102
SparcInstrSelectionSupport.h updated: 1.9 -> 1.10
SparcRegInfo.cpp updated: 1.97 -> 1.98
SparcV9.td updated: 1.19 -> 1.20

---
Log message:

* Changed Bcc instructions to behave like BPcc instructions
* BPA and BPN do not take a %cc register as a parameter
* SLL/SRL/SRA{r,i}5 are there for a reason - they are ONLY 32-bit instructions
* Likewise, SLL/SRL/SRAX{r,i}6 are only 64-bit
* Added WRCCR{r,i} opcodes


---
Diffs of the changes:

Index: llvm/lib/Target/Sparc/PrologEpilogCodeInserter.cpp
diff -u llvm/lib/Target/Sparc/PrologEpilogCodeInserter.cpp:1.26 llvm/lib/Target/Sparc/PrologEpilogCodeInserter.cpp:1.27
--- llvm/lib/Target/Sparc/PrologEpilogCodeInserter.cpp:1.26	Tue May 27 17:35:03 2003
+++ llvm/lib/Target/Sparc/PrologEpilogCodeInserter.cpp	Fri Jun  6 04:52:23 2003
@@ -86,7 +86,7 @@
     M->setOperandLo32(1);
     mvec.push_back(M);
     
-    M = BuildMI(V9::SRAi6, 3).addMReg(uregNum).addZImm(0)
+    M = BuildMI(V9::SRAi5, 3).addMReg(uregNum).addZImm(0)
       .addMReg(uregNum, MOTy::Def);
     mvec.push_back(M);
     


Index: llvm/lib/Target/Sparc/SparcInstr.def
diff -u llvm/lib/Target/Sparc/SparcInstr.def:1.19 llvm/lib/Target/Sparc/SparcInstr.def:1.20
--- llvm/lib/Target/Sparc/SparcInstr.def:1.19	Mon Jun  2 16:16:54 2003
+++ llvm/lib/Target/Sparc/SparcInstr.def	Fri Jun  6 04:52:23 2003
@@ -135,12 +135,12 @@
 I(XNORcci, "xnorcc",	4,  2, B12, true , 0, 1, SPARC_IEU1,  M_INT_FLAG | M_LOGICAL_FLAG)
 
 // Shift operations
-I(SLLr6 , "sll",  	3,  2,  B5, true , 0, 1, SPARC_IEU0,  M_INT_FLAG | M_LOGICAL_FLAG)
-I(SLLi6 , "sll",  	3,  2,  B5, true , 0, 1, SPARC_IEU0,  M_INT_FLAG | M_LOGICAL_FLAG)
-I(SRLr6 , "srl",  	3,  2,  B5, true , 0, 1, SPARC_IEU0,  M_INT_FLAG | M_LOGICAL_FLAG)
-I(SRLi6 , "srl",  	3,  2,  B5, true , 0, 1, SPARC_IEU0,  M_INT_FLAG | M_LOGICAL_FLAG)
-I(SRAr6 , "sra",  	3,  2,  B5, true , 0, 1, SPARC_IEU0,  M_INT_FLAG | M_ARITH_FLAG)
-I(SRAi6 , "sra",  	3,  2,  B5, true , 0, 1, SPARC_IEU0,  M_INT_FLAG | M_ARITH_FLAG)
+I(SLLr5 , "sll",  	3,  2,  B5, true , 0, 1, SPARC_IEU0,  M_INT_FLAG | M_LOGICAL_FLAG)
+I(SLLi5 , "sll",  	3,  2,  B5, true , 0, 1, SPARC_IEU0,  M_INT_FLAG | M_LOGICAL_FLAG)
+I(SRLr5 , "srl",  	3,  2,  B5, true , 0, 1, SPARC_IEU0,  M_INT_FLAG | M_LOGICAL_FLAG)
+I(SRLi5 , "srl",  	3,  2,  B5, true , 0, 1, SPARC_IEU0,  M_INT_FLAG | M_LOGICAL_FLAG)
+I(SRAr5 , "sra",  	3,  2,  B5, true , 0, 1, SPARC_IEU0,  M_INT_FLAG | M_ARITH_FLAG)
+I(SRAi5 , "sra",  	3,  2,  B5, true , 0, 1, SPARC_IEU0,  M_INT_FLAG | M_ARITH_FLAG)
 I(SLLXr6, "sllx", 	3,  2,  B6, true , 0, 1, SPARC_IEU0,  M_INT_FLAG | M_LOGICAL_FLAG)
 I(SLLXi6, "sllx", 	3,  2,  B6, true , 0, 1, SPARC_IEU0,  M_INT_FLAG | M_LOGICAL_FLAG)
 I(SRLXr6, "srlx", 	3,  2,  B6, true , 0, 1, SPARC_IEU0,  M_INT_FLAG | M_LOGICAL_FLAG)
@@ -526,7 +526,8 @@
 
 // Read and Write CCR register from/to an int reg
 I(RDCCR,  "rd",         2,   2, 0, false,  0,  1,  SPARC_SINGLE,  M_INT_FLAG | M_CC_FLAG)
-I(WRCCR,  "wr",         2,   2, 0, false,  0,  1,  SPARC_SINGLE,  M_INT_FLAG | M_CC_FLAG)
+I(WRCCRr,  "wr",         2,   2, 0, false,  0,  1,  SPARC_SINGLE,  M_INT_FLAG | M_CC_FLAG)
+I(WRCCRi,  "wr",         2,   2, 0, false,  0,  1,  SPARC_SINGLE,  M_INT_FLAG | M_CC_FLAG)
 
 // Synthetic phi operation for near-SSA form of machine code
 // Number of operands is variable, indicated by -1.  Result is the first op.


Index: llvm/lib/Target/Sparc/SparcInstrInfo.cpp
diff -u llvm/lib/Target/Sparc/SparcInstrInfo.cpp:1.46 llvm/lib/Target/Sparc/SparcInstrInfo.cpp:1.47
--- llvm/lib/Target/Sparc/SparcInstrInfo.cpp:1.46	Mon Jun  2 22:20:57 2003
+++ llvm/lib/Target/Sparc/SparcInstrInfo.cpp	Fri Jun  6 04:52:23 2003
@@ -145,7 +145,7 @@
   // Sign-extend to the high 32 bits if needed.
   // NOTE: The value C = 0x80000000 is bad: -C == C and so -C is < MAXSIMM
   if (C < 0 && (C == -C || -C > (int32_t) MAXSIMM))
-    mvec.push_back(BuildMI(V9::SRAi6, 3).addReg(dest).addZImm(0).addRegDef(dest));
+    mvec.push_back(BuildMI(V9::SRAi5,3).addReg(dest).addZImm(0).addRegDef(dest));
 }
 
 
@@ -692,7 +692,7 @@
     srcVal = tmpI;
   }
 
-  mvec.push_back(BuildMI(signExtend? V9::SRAi6 : V9::SRLi6, 3)
+  mvec.push_back(BuildMI(signExtend? V9::SRAi5 : V9::SRLi5, 3)
                  .addReg(srcVal).addZImm(32-numLowBits).addRegDef(destVal));
 }
 


Index: llvm/lib/Target/Sparc/SparcInstrSelection.cpp
diff -u llvm/lib/Target/Sparc/SparcInstrSelection.cpp:1.101 llvm/lib/Target/Sparc/SparcInstrSelection.cpp:1.102
--- llvm/lib/Target/Sparc/SparcInstrSelection.cpp:1.101	Mon Jun  2 22:21:58 2003
+++ llvm/lib/Target/Sparc/SparcInstrSelection.cpp	Fri Jun  6 04:52:23 2003
@@ -747,7 +747,7 @@
   Value* shiftDest = destVal;
   unsigned opSize = target.getTargetData().getTypeSize(argVal1->getType());
 
-  if ((shiftOpCode == V9::SLLr6 || shiftOpCode == V9::SLLXr6) && opSize < 8) {
+  if ((shiftOpCode == V9::SLLr5 || shiftOpCode == V9::SLLXr6) && opSize < 8) {
     // put SLL result into a temporary
     shiftDest = new TmpInstruction(mcfi, argVal1, optArgVal2, "sllTmp");
   }
@@ -815,7 +815,7 @@
         mvec.push_back(M);
       } else if (isPowerOf2(C, pow)) {
         unsigned opSize = target.getTargetData().getTypeSize(resultType);
-        MachineOpCode opCode = (opSize <= 32)? V9::SLLr6 : V9::SLLXr6;
+        MachineOpCode opCode = (opSize <= 32)? V9::SLLr5 : V9::SLLXr6;
         CreateShiftInstructions(target, F, opCode, lval, NULL, pow,
                                 destVal, mvec, mcfi);
       }
@@ -979,7 +979,7 @@
 
           // Create the SRL or SRLX instruction to get the sign bit
           mvec.push_back(BuildMI((resultType==Type::LongTy) ?
-                                 V9::SRLXi6 : V9::SRLi6, 3)
+                                 V9::SRLXi6 : V9::SRLi5, 3)
                          .addReg(LHS)
                          .addSImm((resultType==Type::LongTy)? 63 : 31)
                          .addRegDef(srlTmp));
@@ -990,11 +990,11 @@
 
           // Get the shift operand and "right-shift" opcode to do the divide
           shiftOperand = addTmp;
-          opCode = (resultType==Type::LongTy) ? V9::SRAXi6 : V9::SRAi6;
+          opCode = (resultType==Type::LongTy) ? V9::SRAXi6 : V9::SRAi5;
         } else {
           // Get the shift operand and "right-shift" opcode to do the divide
           shiftOperand = LHS;
-          opCode = (resultType==Type::LongTy) ? V9::SRLXi6 : V9::SRLi6;
+          opCode = (resultType==Type::LongTy) ? V9::SRLXi6 : V9::SRLi5;
         }
 
         // Now do the actual shift!
@@ -2419,7 +2419,7 @@
                "Shl unsupported for other types");
         
         CreateShiftInstructions(target, shlInstr->getParent()->getParent(),
-                                (opType == Type::LongTy)? V9::SLLXr6:V9::SLLr6,
+                                (opType == Type::LongTy)? V9::SLLXr6:V9::SLLr5,
                                 argVal1, argVal2, 0, shlInstr, mvec,
                                 MachineCodeForInstruction::get(shlInstr));
         break;
@@ -2431,8 +2431,8 @@
         assert((opType->isInteger() || isa<PointerType>(opType)) &&
                "Shr unsupported for other types");
         Add3OperandInstr(opType->isSigned()
-                         ? (opType == Type::LongTy ? V9::SRAXr6 : V9::SRAr6)
-                         : (opType == Type::LongTy ? V9::SRLXr6 : V9::SRLr6),
+                         ? (opType == Type::LongTy ? V9::SRAXr6 : V9::SRAr5)
+                         : (opType == Type::LongTy ? V9::SRLXr6 : V9::SRLr5),
                          subtreeRoot, mvec);
         break;
       }
@@ -2503,7 +2503,7 @@
         for (unsigned i=0, N=mvec.size(); i < N; ++i)
           mvec[i]->substituteValue(dest, tmpI);
 
-        M = BuildMI(V9::SRLi6, 3).addReg(tmpI).addZImm(8*(4-destSize))
+        M = BuildMI(V9::SRLi5, 3).addReg(tmpI).addZImm(8*(4-destSize))
           .addReg(dest, MOTy::Def);
         mvec.push_back(M);
       } else if (destSize < 8) {


Index: llvm/lib/Target/Sparc/SparcInstrSelectionSupport.h
diff -u llvm/lib/Target/Sparc/SparcInstrSelectionSupport.h:1.9 llvm/lib/Target/Sparc/SparcInstrSelectionSupport.h:1.10
--- llvm/lib/Target/Sparc/SparcInstrSelectionSupport.h:1.9	Mon Jun  2 22:23:35 2003
+++ llvm/lib/Target/Sparc/SparcInstrSelectionSupport.h	Fri Jun  6 04:52:23 2003
@@ -110,9 +110,9 @@
   case V9::XNORccr: return V9::XNORcci;
 
     /* shift */
-  case V9::SLLr6:   return V9::SLLi6;
-  case V9::SRLr6:   return V9::SRLi6;
-  case V9::SRAr6:   return V9::SRAi6;
+  case V9::SLLr5:   return V9::SLLi5;
+  case V9::SRLr5:   return V9::SRLi5;
+  case V9::SRAr5:   return V9::SRAi5;
   case V9::SLLXr6:  return V9::SLLXi6;
   case V9::SRLXr6:  return V9::SRLXi6;
   case V9::SRAXr6:  return V9::SRAXi6;


Index: llvm/lib/Target/Sparc/SparcRegInfo.cpp
diff -u llvm/lib/Target/Sparc/SparcRegInfo.cpp:1.97 llvm/lib/Target/Sparc/SparcRegInfo.cpp:1.98
--- llvm/lib/Target/Sparc/SparcRegInfo.cpp:1.97	Sat May 31 21:48:23 2003
+++ llvm/lib/Target/Sparc/SparcRegInfo.cpp	Fri Jun  6 04:52:23 2003
@@ -1068,7 +1068,8 @@
                                unsigned SrcReg,
                                unsigned DestReg,
                                int RegType) const {
-  assert( ((int)SrcReg != getInvalidRegNum()) && ((int)DestReg != getInvalidRegNum()) &&
+  assert( ((int)SrcReg != getInvalidRegNum()) && 
+          ((int)DestReg != getInvalidRegNum()) &&
 	  "Invalid Register");
   
   MachineInstr * MI = NULL;
@@ -1085,7 +1086,8 @@
       // Use DestReg+1 to get the name "%ccr" instead of "%xcc" for WRCCR
       assert(getRegType(SrcReg) == IntRegType
              && "Can only copy CC reg to/from integer reg");
-      MI = BuildMI(V9::WRCCR, 2).addMReg(SrcReg).addMReg(DestReg+1, MOTy::Def);
+      MI = BuildMI(V9::WRCCRr, 2).addMReg(SrcReg)
+        .addMReg(SparcIntRegClass::g0).addMReg(DestReg+1, MOTy::Def);
     }
     break;
     
@@ -1212,7 +1214,8 @@
     cpMem2RegMI(mvec, SrcPtrReg, Offset, scratchReg, IntRegType);
     
     // Use DestReg+1 to get the name "%ccr" instead of "%xcc" for WRCCR
-    MI = BuildMI(V9::WRCCR, 2).addMReg(scratchReg).addMReg(DestReg+1,MOTy::Def);
+    MI = BuildMI(V9::WRCCRr, 2).addMReg(scratchReg)
+      .addMReg(SparcIntRegClass::g0).addMReg(DestReg+1,MOTy::Def);
     break;
     
   case FloatCCRegType: {


Index: llvm/lib/Target/Sparc/SparcV9.td
diff -u llvm/lib/Target/Sparc/SparcV9.td:1.19 llvm/lib/Target/Sparc/SparcV9.td:1.20
--- llvm/lib/Target/Sparc/SparcV9.td:1.19	Thu Jun  5 22:34:47 2003
+++ llvm/lib/Target/Sparc/SparcV9.td	Fri Jun  6 04:52:23 2003
@@ -121,6 +121,7 @@
 #endif
 
 // Section A.6: Branch on Integer condition codes (Bicc) - p146
+#if 0 // instead of using deprecated version, use the predicted version below
 set isDeprecated = 1 in {
   set op2 = 0b010 in {
     def BA     : F2_2<0b1000, "ba">;              // Branch always
@@ -141,6 +142,29 @@
     def BVS    : F2_2<0b0111, "bvs">;             // Branch on overflow set
   }
 }
+#endif
+
+// Using the format of A.7 instructions...
+set op2 = 0b001 in {
+  set cc = 0 in {   // BA and BN don't read condition codes
+    def BA   : F2_3<0b1000, "ba">;              // Branch always
+    def BN   : F2_3<0b0000, "bn">;              // Branch never
+  }
+  def BNE    : F2_3<0b1001, "bne">;             // Branch !=
+  def BE     : F2_3<0b0001, "be">;              // Branch ==
+  def BG     : F2_3<0b1010, "bg">;              // Branch >
+  def BLE    : F2_3<0b0010, "ble">;             // Branch <=
+  def BGE    : F2_3<0b1011, "bge">;             // Branch >=
+  def BL     : F2_3<0b0011, "bl">;              // Branch <
+  def BGU    : F2_3<0b1100, "bgu">;             // Branch unsigned >
+  def BLEU   : F2_3<0b0100, "bleu">;            // Branch unsigned <=
+  def BCC    : F2_3<0b1101, "bcc">;             // Branch unsigned >=
+  def BCS    : F2_3<0b0101, "bcs">;             // Branch unsigned <=
+  def BPOS   : F2_3<0b1110, "bpos">;            // Branch on positive
+  def BNEG   : F2_3<0b0110, "bneg">;            // Branch on negative
+  def BVC    : F2_3<0b1111, "bvc">;             // Branch on overflow clear
+  def BVS    : F2_3<0b0111, "bvs">;             // Branch on overflow set
+}
 
 // Section A.7: Branch on integer condition codes with prediction - p148
 // Not used in the Sparc backend
@@ -669,28 +693,20 @@
 #endif
 
 // uses 6 least significant bits of rs2
+set x = 0 in { 
+  def SLLr5  : F3_11<2, 0b100101, "sll">;                // sll r, r, r
+  def SRLr5  : F3_11<2, 0b100110, "srl">;                // srl r, r, r
+  def SRAr5  : F3_11<2, 0b100111, "sra">;                // sra r, r, r
+}
 set x = 1 in {
-  def SLLr6  : F3_11<2, 0b100101, "sll">;                // sll r, r, r
-  def SRLr6  : F3_11<2, 0b100110, "srl">;                // srl r, r, r
-  def SRAr6  : F3_11<2, 0b100111, "sra">;                // sra r, r, r
   def SLLXr6 : F3_11<2, 0b100101, "sllx">;               // sllx r, r, r
   def SRLXr6 : F3_11<2, 0b100110, "srlx">;               // srlx r, r, r
   def SRAXr6 : F3_11<2, 0b100111, "srax">;               // srax r, r, r
 }
 
-// Not currently used in the Sparc backend
-#if 0
 def SLLi5  : F3_12<2, 0b100101, "sll">;                // sll r, shcnt32, r
 def SRLi5  : F3_12<2, 0b100110, "srl">;                // srl r, shcnt32, r
 def SRAi5  : F3_12<2, 0b100111, "sra">;                // sra r, shcnt32, r
-def SLLXi5 : F3_12<2, 0b100101, "sllx">;               // sllx r, shcnt32, r
-def SRLXi5 : F3_12<2, 0b100110, "srlx">;               // srlx r, shcnt32, r
-def SRAXi5 : F3_12<2, 0b100111, "srax">;               // srax r, shcnt32, r
-#endif
-
-def SLLi6  : F3_13<2, 0b100101, "sll">;                  // sll r, shcnt64, r
-def SRLi6  : F3_13<2, 0b100110, "srl">;                  // srl r, shcnt64, r
-def SRAi6  : F3_13<2, 0b100111, "sra">;                  // sra r, shcnt64, r
 def SLLXi6 : F3_13<2, 0b100101, "sllx">;                 // sllx r, shcnt64, r
 def SRLXi6 : F3_13<2, 0b100110, "srlx">;                 // srlx r, shcnt64, r
 def SRAXi6 : F3_13<2, 0b100111, "srax">;                 // srax r, shcnt64, r
@@ -754,3 +770,9 @@
 def SUBCcci : F3_2<2, 0b011100, "subccc">;                // subccc r, i, r
 
 // FIXME: More...?
+
+// Section A.63: Write State Register - p244
+set rd = 2 in {
+  def WRCCRr : F3_1<2, 0b110000, "wr">;                 // wr r, r, %y/ccr/etc
+  def WRCCRi : F3_2<2, 0b110000, "wr">;                 // wr r, i, %y/ccr/etc
+}




From brukman at cs.uiuc.edu  Fri Jun  6 04:54:00 2003
From: brukman at cs.uiuc.edu (Misha Brukman)
Date: Fri Jun  6 04:54:00 2003
Subject: [llvm-commits] CVS: llvm/lib/Target/Sparc/UltraSparcSchedInfo.cpp
Message-ID: <200306060953.EAA07435@zion.cs.uiuc.edu>


Changes in directory llvm/lib/Target/Sparc:

UltraSparcSchedInfo.cpp updated: 1.5 -> 1.6

---
Log message:

Added 'r' and 'i' versions to WRCCR.


---
Diffs of the changes:

Index: llvm/lib/Target/Sparc/UltraSparcSchedInfo.cpp
diff -u llvm/lib/Target/Sparc/UltraSparcSchedInfo.cpp:1.5 llvm/lib/Target/Sparc/UltraSparcSchedInfo.cpp:1.6
--- llvm/lib/Target/Sparc/UltraSparcSchedInfo.cpp:1.5	Tue May 27 17:33:39 2003
+++ llvm/lib/Target/Sparc/UltraSparcSchedInfo.cpp	Fri Jun  6 04:52:58 2003
@@ -484,7 +484,8 @@
   { V9::UDIVXi,		true,	true,	68 },
 //{ V9::SDIVcc,		true,	true,	36 },
 //{ V9::UDIVcc,		true,	true,	37 },
-  { V9::WRCCR,		true,	true,	4 },
+  { V9::WRCCRr,		true,	true,	4 },
+  { V9::WRCCRi,		true,	true,	4 },
 //{ V9::WRPR,		true,	true,	4 },
 //{ V9::RDCCR,		true,	true,	0 }, // no bubbles after, but see below
 //{ V9::RDPR,		true,	true,	0 },




From brukman at cs.uiuc.edu  Fri Jun  6 04:54:06 2003
From: brukman at cs.uiuc.edu (Misha Brukman)
Date: Fri Jun  6 04:54:06 2003
Subject: [llvm-commits] CVS: llvm/lib/Target/Sparc/SparcV9CodeEmitter.cpp
Message-ID: <200306060953.EAA07459@zion.cs.uiuc.edu>


Changes in directory llvm/lib/Target/Sparc:

SparcV9CodeEmitter.cpp updated: 1.16 -> 1.17

---
Log message:

Print address out as hex.


---
Diffs of the changes:

Index: llvm/lib/Target/Sparc/SparcV9CodeEmitter.cpp
diff -u llvm/lib/Target/Sparc/SparcV9CodeEmitter.cpp:1.16 llvm/lib/Target/Sparc/SparcV9CodeEmitter.cpp:1.17
--- llvm/lib/Target/Sparc/SparcV9CodeEmitter.cpp:1.16	Thu Jun  5 23:41:22 2003
+++ llvm/lib/Target/Sparc/SparcV9CodeEmitter.cpp	Fri Jun  6 04:53:28 2003
@@ -449,7 +449,7 @@
             if (ConstantMap.find(C) != ConstantMap.end()) {
               rv = MCE.getConstantPoolEntryAddress(ConstantMap[C]);
             } else {
-              std::cerr << "Constant: 0x" << std::hex << &*C << std::dec
+              std::cerr << "Constant: 0x" << std::hex << (intptr_t)C
                         << ", " << *V << " not found in ConstantMap!\n";
               abort();
             }




From dhurjati at cs.uiuc.edu  Fri Jun  6 13:06:01 2003
From: dhurjati at cs.uiuc.edu (Dinakar Dhurjati)
Date: Fri Jun  6 13:06:01 2003
Subject: [llvm-commits] CVS: llvm/www/safecode/
Message-ID: <200306061805.NAA15226@tank.cs.uiuc.edu>


Changes in directory llvm/www/safecode:


---
Log message:

Directory /home/vadve/vadve/Research/DynOpt/CVSRepository/llvm/www/safecode added to the repository


---
Diffs of the changes:



From dhurjati at cs.uiuc.edu  Fri Jun  6 13:08:01 2003
From: dhurjati at cs.uiuc.edu (Dinakar Dhurjati)
Date: Fri Jun  6 13:08:01 2003
Subject: [llvm-commits] CVS: llvm/www/safecode/index.html
Message-ID: <200306061807.NAA15306@tank.cs.uiuc.edu>


Changes in directory llvm/www/safecode:

index.html added (r1.1)

---
Log message:

Added safecode project to the llvm webpage


---
Diffs of the changes:

Index: llvm/www/safecode/index.html
diff -c /dev/null llvm/www/safecode/index.html:1.1
*** /dev/null	Fri Jun  6 13:07:51 2003
--- llvm/www/safecode/index.html	Fri Jun  6 13:07:40 2003
***************
*** 0 ****
--- 1,25 ----
+ <!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+ <html><head><title>SAFE Code</title></head>
+ <body bgcolor=white>
+ <center><font size=+3 face=Verdana><b>SAFE Code</b></font></center>
+ <hr size=0>
+ 
+ Static Analysis for safe Execution of Code 
+ 
+ Publications :
+ 
+ <ul>
+   <li> Dinakar Dhurjati, Sumant Kowshik, Vikram Adve and Chris Lattner :
+ <a href="http://llvm.cs.uiuc.edu/pubs/2003-05-05-LCTES03-CodeSafety.html" >
+       Memory Safety without Runtime Checks or Garbage Collection for
+        Embedded Systems </a>, LCTES 2003.
+   <li> Sumant Kowshik, Dinakar Dhurjati, Vikram Adve : <a href="http://llvm.cs.uiuc.edu/pubs/2002-08-08-CASES02-ControlC.html" >Ensuring Code
+        Safety without Runtime Checks for Real Time Control Systems </a>, CASES
+        2002.
+ 
+ </ul>      
+ 
+ <hr>
+ <address><a href="mailto:sabre at nondot.org">Chris Lattner</a></address>
+ </body>
+ </html>




From dhurjati at cs.uiuc.edu  Fri Jun  6 13:23:01 2003
From: dhurjati at cs.uiuc.edu (Dinakar Dhurjati)
Date: Fri Jun  6 13:23:01 2003
Subject: [llvm-commits] CVS: llvm/www/safecode/index.html
Message-ID: <200306061822.NAA15547@tank.cs.uiuc.edu>


Changes in directory llvm/www/safecode:

index.html updated: 1.1 -> 1.2

---
Log message:

Modified the email address to dhurjati at cs.uiuc.edu


---
Diffs of the changes:

Index: llvm/www/safecode/index.html
diff -u llvm/www/safecode/index.html:1.1 llvm/www/safecode/index.html:1.2
--- llvm/www/safecode/index.html:1.1	Fri Jun  6 13:07:40 2003
+++ llvm/www/safecode/index.html	Fri Jun  6 13:22:38 2003
@@ -4,9 +4,9 @@
 <center><font size=+3 face=Verdana><b>SAFE Code</b></font></center>
 <hr size=0>
 
-Static Analysis for safe Execution of Code 
+<H2>Static Analysis for safe Execution of Code <br>
 
-Publications :
+Publications : <bf>
 
 <ul>
   <li> Dinakar Dhurjati, Sumant Kowshik, Vikram Adve and Chris Lattner :
@@ -20,6 +20,6 @@
 </ul>      
 
 <hr>
-<address><a href="mailto:sabre at nondot.org">Chris Lattner</a></address>
+<address><a href="mailto:dhurjati at cs.uiuc.edu">Dinakar Dhurjati</a></address>
 </body>
 </html>




From lattner at cs.uiuc.edu  Fri Jun  6 13:26:01 2003
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Fri Jun  6 13:26:01 2003
Subject: [llvm-commits] CVS: llvm/lib/Target/X86/X86CodeEmitter.cpp
Message-ID: <200306061825.NAA19902@apoc.cs.uiuc.edu>


Changes in directory llvm/lib/Target/X86:

X86CodeEmitter.cpp updated: 1.27 -> 1.28

---
Log message:

Fix warnings on Sparc


---
Diffs of the changes:

Index: llvm/lib/Target/X86/X86CodeEmitter.cpp
diff -u llvm/lib/Target/X86/X86CodeEmitter.cpp:1.27 llvm/lib/Target/X86/X86CodeEmitter.cpp:1.28
--- llvm/lib/Target/X86/X86CodeEmitter.cpp:1.27	Thu Jun  5 23:00:05 2003
+++ llvm/lib/Target/X86/X86CodeEmitter.cpp	Fri Jun  6 13:25:33 2003
@@ -13,6 +13,7 @@
 #include "llvm/CodeGen/MachineInstr.h"
 #include "llvm/Value.h"
 #include "Support/Statistic.h"
+#include <alloca.h>
 
 namespace {
   Statistic<>
@@ -77,7 +78,9 @@
   unsigned RetAddr = (unsigned)(intptr_t)__builtin_return_address(0);
   assert(StackPtr[1] == RetAddr &&
          "Could not find return address on the stack!");
-  bool isStub = ((unsigned char*)RetAddr)[0] == 0xCD;  // Interrupt marker?
+
+  // It's a stub if there is an interrupt marker after the call...
+  bool isStub = ((unsigned char*)(intptr_t)RetAddr)[0] == 0xCD;
 
   // FIXME FIXME FIXME FIXME: __builtin_frame_address doesn't work if frame
   // pointer elimination has been performed.  Having a variable sized alloca
@@ -97,20 +100,20 @@
 #endif
 
   // Sanity check to make sure this really is a call instruction...
-  assert(((unsigned char*)RetAddr)[-1] == 0xE8 && "Not a call instr!");
+  assert(((unsigned char*)(intptr_t)RetAddr)[-1] == 0xE8 &&"Not a call instr!");
   
   unsigned NewVal = TheJITResolver->resolveFunctionReference(RetAddr);
 
   // Rewrite the call target... so that we don't fault every time we execute
   // the call.
-  *(unsigned*)RetAddr = NewVal-RetAddr-4;    
+  *(unsigned*)(intptr_t)RetAddr = NewVal-RetAddr-4;    
 
   if (isStub) {
     // If this is a stub, rewrite the call into an unconditional branch
     // instruction so that two return addresses are not pushed onto the stack
     // when the requested function finally gets called.  This also makes the
     // 0xCD byte (interrupt) dead, so the marker doesn't effect anything.
-    ((unsigned char*)RetAddr)[-1] = 0xE9;
+    ((unsigned char*)(intptr_t)RetAddr)[-1] = 0xE9;
   }
 
   // Change the return address to reexecute the call instruction...
@@ -195,7 +198,7 @@
   for (unsigned i = 0, e = BBRefs.size(); i != e; ++i) {
     unsigned Location = BasicBlockAddrs[BBRefs[i].first];
     unsigned Ref = BBRefs[i].second;
-    *(unsigned*)Ref = Location-Ref-4;
+    *(unsigned*)(intptr_t)Ref = Location-Ref-4;
   }
   BBRefs.clear();
   BasicBlockAddrs.clear();




From dhurjati at cs.uiuc.edu  Fri Jun  6 13:30:00 2003
From: dhurjati at cs.uiuc.edu (Dinakar Dhurjati)
Date: Fri Jun  6 13:30:00 2003
Subject: [llvm-commits] CVS: llvm/www/www-index.html
Message-ID: <200306061829.NAA15686@tank.cs.uiuc.edu>


Changes in directory llvm/www:

www-index.html updated: 1.38 -> 1.39

---
Log message:

Added link to safecode


---
Diffs of the changes:

Index: llvm/www/www-index.html
diff -u llvm/www/www-index.html:1.38 llvm/www/www-index.html:1.39
--- llvm/www/www-index.html:1.38	Wed May 21 17:23:00 2003
+++ llvm/www/www-index.html	Fri Jun  6 13:29:01 2003
@@ -440,8 +440,9 @@
                         Optimizing native code during
                         execution, using LLVM-to-native-code
                         mapping information. </li>
-                    <li><em><strong>Code safety for embedded
-                        systems</strong>:</em> Language and
+                    <li><em><strong><a href="safecode/"> SAFECode </a>
+			project 
+			</strong>:</em> Language and
                         compiler support for ensuring memory
                         safety of embedded code through static
                         analysis.</li>




From dhurjati at cs.uiuc.edu  Fri Jun  6 13:37:01 2003
From: dhurjati at cs.uiuc.edu (Dinakar Dhurjati)
Date: Fri Jun  6 13:37:01 2003
Subject: [llvm-commits] CVS: llvm/www/safecode/index.html
Message-ID: <200306061836.NAA15789@tank.cs.uiuc.edu>


Changes in directory llvm/www/safecode:

index.html updated: 1.2 -> 1.3

---
Log message:

Added some description


---
Diffs of the changes:

Index: llvm/www/safecode/index.html
diff -u llvm/www/safecode/index.html:1.2 llvm/www/safecode/index.html:1.3
--- llvm/www/safecode/index.html:1.2	Fri Jun  6 13:22:38 2003
+++ llvm/www/safecode/index.html	Fri Jun  6 13:36:08 2003
@@ -4,9 +4,13 @@
 <center><font size=+3 face=Verdana><b>SAFE Code</b></font></center>
 <hr size=0>
 
-<H2>Static Analysis for safe Execution of Code <br>
+<H2>Static Analysis For safe Execution of Code </H2><br>
 
-Publications : <bf>
+To enable program safety without runtime checks and garbage collection, through 100% or near-100% static enforcement of program safety properties.  SAFECode defines a code representation with minimal semantic restrictions designed to enable static enforcement of safety, using aggressive compiler techniques developed in this project.<br><br><br>
+
+
+
+<h3> Publications : </H3> <bf>
 
 <ul>
   <li> Dinakar Dhurjati, Sumant Kowshik, Vikram Adve and Chris Lattner :




From dhurjati at cs.uiuc.edu  Fri Jun  6 15:10:01 2003
From: dhurjati at cs.uiuc.edu (Dinakar Dhurjati)
Date: Fri Jun  6 15:10:01 2003
Subject: [llvm-commits] CVS: llvm/www/safecode/index.html
Message-ID: <200306062009.PAA17012@tank.cs.uiuc.edu>


Changes in directory llvm/www/safecode:

index.html updated: 1.3 -> 1.4

---
Log message:


---
Diffs of the changes:

Index: llvm/www/safecode/index.html
diff -u llvm/www/safecode/index.html:1.3 llvm/www/safecode/index.html:1.4
--- llvm/www/safecode/index.html:1.3	Fri Jun  6 13:36:08 2003
+++ llvm/www/safecode/index.html	Fri Jun  6 15:00:04 2003
@@ -1,7 +1,7 @@
 <!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
 <html><head><title>SAFE Code</title></head>
 <body bgcolor=white>
-<center><font size=+3 face=Verdana><b>SAFE Code</b></font></center>
+<center><font size=+3 face=Verdana><b>SAFECode</b></font></center>
 <hr size=0>
 
 <H2>Static Analysis For safe Execution of Code </H2><br>




From lattner at cs.uiuc.edu  Fri Jun  6 16:10:05 2003
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Fri Jun  6 16:10:05 2003
Subject: [llvm-commits] CVS: llvm/lib/Support/Timer.cpp
Message-ID: <200306062109.QAA24414@apoc.cs.uiuc.edu>


Changes in directory llvm/lib/Support:

Timer.cpp updated: 1.16 -> 1.17

---
Log message:

Fix problem with perror


---
Diffs of the changes:

Index: llvm/lib/Support/Timer.cpp
diff -u llvm/lib/Support/Timer.cpp:1.16 llvm/lib/Support/Timer.cpp:1.17
--- llvm/lib/Support/Timer.cpp:1.16	Fri May  9 15:05:44 2003
+++ llvm/lib/Support/Timer.cpp	Fri Jun  6 16:09:29 2003
@@ -11,6 +11,7 @@
 #include <sys/unistd.h>
 #include <unistd.h>
 #include <malloc.h>
+#include <stdio.h>
 #include <iostream>
 #include <algorithm>
 #include <functional>




From tbrethou at cs.uiuc.edu  Fri Jun  6 16:22:01 2003
From: tbrethou at cs.uiuc.edu (Tanya Brethour)
Date: Fri Jun  6 16:22:01 2003
Subject: [llvm-commits] CVS: llvm/lib/Reoptimizer/SSAPRE/RuntimeLICM.cpp
Message-ID: <200306062121.QAA17778@tank.cs.uiuc.edu>


Changes in directory llvm/lib/Reoptimizer/SSAPRE:

RuntimeLICM.cpp added (r1.1)

---
Log message:

Simple runtime LICM on traces.


---
Diffs of the changes:

Index: llvm/lib/Reoptimizer/SSAPRE/RuntimeLICM.cpp
diff -c /dev/null llvm/lib/Reoptimizer/SSAPRE/RuntimeLICM.cpp:1.1
*** /dev/null	Fri Jun  6 16:21:13 2003
--- llvm/lib/Reoptimizer/SSAPRE/RuntimeLICM.cpp	Fri Jun  6 16:21:03 2003
***************
*** 0 ****
--- 1,70 ----
+ //===-- RuntimeLICM.cpp - Runtime LICM on traces ----------------------------=//
+ //
+ //  Implements the loop invariant code motion optmization for traces.
+ //  Only moves LI instructions to the prologe if all operands are not
+ //  defined in the trace.
+ //
+ //===----------------------------------------------------------------------===//
+ 
+ #include "llvm/BasicBlock.h"
+ #include "llvm/Instruction.h"
+ #include "llvm/iMemory.h"
+ #include "llvm/iPHINode.h"
+ #include "llvm/Reoptimizer/BinInterface/LLVMTrace.h"
+ 
+ #include <iostream>
+ #include <vector>
+ #include <set>
+ 
+ using std::vector;
+ using std::set;
+ 
+ void RuntimeLICM(vector<BasicBlock *> &trace, LLVMTrace &ltrace) {
+   
+   //Put the trace in a set for faster searching
+   std::set<BasicBlock*> traceSet(trace.begin(), trace.end());
+   
+   //Keep track of the number of LI expressions we find
+   unsigned numLIC = 0;
+   
+   //loop over all the basic blocks in my trace
+   for(vector<BasicBlock *>::iterator T = trace.begin(), End = trace.end(); 
+       T != End; ++T) {
+     
+     //loop over all the instructions in the basic block
+     BasicBlock *BB = (*T);
+     for(BasicBlock::iterator i = BB->begin(), e = BB->end(); i != e; ++i) {
+ 
+       //Keep track of instructions status. Assume invariant until proven
+       //otherwise
+       bool isLoopInvariant = true;
+ 	
+       //Check if its a load, a phi, a terminator, or if it can write to mem
+       //If any of these are true, we can not move it
+       if (!isa<LoadInst>(*i) && !i->mayWriteToMemory() && 
+ 	  !i->isTerminator() && !isa<PHINode>(*i)) {
+ 	
+ 	//loop over the operands and see where they are defined
+ 	//if all operands are defined out of the trace, its loop invariant
+ 	for(User::op_iterator z = i->op_begin(), ze = i->op_end(); 
+ 	    z != ze; ++z) {
+ 	  Value *V = *z;
+ 	  if(Instruction* def = dyn_cast<Instruction>(V)) {
+ 	    BasicBlock *parent = def->getParent();
+ 	    if(traceSet.count(parent))
+ 	      isLoopInvariant = false;
+ 	  }
+ 	}
+ 
+ 	if(isLoopInvariant) {
+ 	  std::cerr << "Loop Invariant Instruction: " << i << "\n";
+ 	  //move to header block
+ 	  ltrace.moveInstrToSec(&(*i), 0);
+ 	  ++numLIC;
+ 	}
+       }
+     }
+   }
+   
+   std::cerr << "Number Loop Invariant: " << numLIC << "\n";
+ }




From tbrethou at cs.uiuc.edu  Fri Jun  6 16:22:07 2003
From: tbrethou at cs.uiuc.edu (Tanya Brethour)
Date: Fri Jun  6 16:22:07 2003
Subject: [llvm-commits] CVS: llvm/include/llvm/Reoptimizer/Transforms/
Message-ID: <200306062121.QAA17793@tank.cs.uiuc.edu>


Changes in directory llvm/include/llvm/Reoptimizer/Transforms:


---
Log message:

Directory /home/vadve/vadve/Research/DynOpt/CVSRepository/llvm/include/llvm/Reoptimizer/Transforms added to the repository


---
Diffs of the changes:



From tbrethou at cs.uiuc.edu  Fri Jun  6 16:23:01 2003
From: tbrethou at cs.uiuc.edu (Tanya Brethour)
Date: Fri Jun  6 16:23:01 2003
Subject: [llvm-commits] CVS: llvm/include/llvm/Reoptimizer/Transforms/RuntimeLICM.h
Message-ID: <200306062122.QAA17823@tank.cs.uiuc.edu>


Changes in directory llvm/include/llvm/Reoptimizer/Transforms:

RuntimeLICM.h added (r1.1)

---
Log message:

Header file for my runtime LICM on traces.


---
Diffs of the changes:

Index: llvm/include/llvm/Reoptimizer/Transforms/RuntimeLICM.h
diff -c /dev/null llvm/include/llvm/Reoptimizer/Transforms/RuntimeLICM.h:1.1
*** /dev/null	Fri Jun  6 16:22:04 2003
--- llvm/include/llvm/Reoptimizer/Transforms/RuntimeLICM.h	Fri Jun  6 16:21:54 2003
***************
*** 0 ****
--- 1,14 ----
+ //===-- RuntimeLICM.cpp - Runtime LICM on traces ----------------------------=//
+ //
+ //  This transformation does trace invariant code motion.
+ //  Only moves LI instructions to the prologe if all operands are not
+ //  defined in the trace.
+ //
+ //===----------------------------------------------------------------------===//
+ 
+ #ifndef LLVM_REOPTIMIZER_TRANSFORMS_RUNTIMELICM
+ #define LLVM_REOPTIMIZER_TRANSFORMS_RUNTIMELICM
+ 
+ void RuntimeLICM(vector<BasicBlock *> &t, LLVMTrace &ltrace);
+ 
+ #endif




From dhurjati at cs.uiuc.edu  Fri Jun  6 16:38:01 2003
From: dhurjati at cs.uiuc.edu (Dinakar Dhurjati)
Date: Fri Jun  6 16:38:01 2003
Subject: [llvm-commits] CVS: llvm/www/safecode/index.html
Message-ID: <200306062137.QAA29842@apoc.cs.uiuc.edu>


Changes in directory llvm/www/safecode:

index.html updated: 1.4 -> 1.5

---
Log message:

Added funding/project members/Links etc.


---
Diffs of the changes:

Index: llvm/www/safecode/index.html
diff -u llvm/www/safecode/index.html:1.4 llvm/www/safecode/index.html:1.5
--- llvm/www/safecode/index.html:1.4	Fri Jun  6 15:00:04 2003
+++ llvm/www/safecode/index.html	Fri Jun  6 16:37:05 2003
@@ -8,22 +8,53 @@
 
 To enable program safety without runtime checks and garbage collection, through 100% or near-100% static enforcement of program safety properties.  SAFECode defines a code representation with minimal semantic restrictions designed to enable static enforcement of safety, using aggressive compiler techniques developed in this project.<br><br><br>
 
+<H3> Project Members : </H3>
 
+<H4>Faculty : </H4>
+<ul>
+<li><a href="http://www.cs.uiuc.edu/~vadve" > Vikram Adve </a> <br>
+</ul>
+<H4>Graduate Students : </H4> 
+<ul>
+<li><a href="http://llvm.cs.uiuc.edu/~dhurjati" > Dinakar Dhurjati </a> <br>
+<li><a href="mailto:kowshik at cs.uiuc.edu" > Sumant Kowshik </a> <br>
+<li><a href="http://www.nondot.org/~sabre" > Chris Lattner </a> <br><br>
+</ul>
+
+<br>
 
-<h3> Publications : </H3> <bf>
+<H3> Publications : </H3> 
 
 <ul>
-  <li> Dinakar Dhurjati, Sumant Kowshik, Vikram Adve and Chris Lattner :
-<a href="http://llvm.cs.uiuc.edu/pubs/2003-05-05-LCTES03-CodeSafety.html" >
-      Memory Safety without Runtime Checks or Garbage Collection for
-       Embedded Systems </a>, LCTES 2003.
-  <li> Sumant Kowshik, Dinakar Dhurjati, Vikram Adve : <a href="http://llvm.cs.uiuc.edu/pubs/2002-08-08-CASES02-ControlC.html" >Ensuring Code
-       Safety without Runtime Checks for Real Time Control Systems </a>, CASES
+  <li> <a
+      href="http://llvm.cs.uiuc.edu/pubs/2003-05-05-LCTES03-CodeSafety.html" >  Memory Safety without Runtime Checks or Garbage Collection for
+       Embedded Systems </a>, Dinakar Dhurjati, Sumant Kowshik, Vikram
+      Adve and Chris Lattner. LCTES 2003.
+  <li> 
+      <a href="http://llvm.cs.uiuc.edu/pubs/2002-08-08-CASES02-ControlC.html" >Ensuring Code
+       Safety without Runtime Checks for Real Time Control Systems
+      </a>, Sumant Kowshik, Dinakar Dhurjati, Vikram Adve : CASES
        2002.
 
 </ul>      
 
-<hr>
+<H3> Download : </H3>
+
+Not in public domain for now. Check this page later.
+
+<H3> Funding : </H3> <bf>
+This project is sponsored
+by the NSF Embedded Systems program under award CCR-02-09202
+and in part by an NSF CAREER award, EIA-0093426 and ONR, 
+N0004-02-0102.
+
+<H3> Links : </H3>
+<ul>
+<li>      <a href="http://llvm.cs.uiuc.edu" > LLVM <br>
+</ul>  
+
+
+  <hr>
 <address><a href="mailto:dhurjati at cs.uiuc.edu">Dinakar Dhurjati</a></address>
 </body>
 </html>




From dhurjati at cs.uiuc.edu  Fri Jun  6 16:40:02 2003
From: dhurjati at cs.uiuc.edu (Dinakar Dhurjati)
Date: Fri Jun  6 16:40:02 2003
Subject: [llvm-commits] CVS: llvm/www/safecode/index.html
Message-ID: <200306062139.QAA17964@tank.cs.uiuc.edu>


Changes in directory llvm/www/safecode:

index.html updated: 1.5 -> 1.6

---
Log message:

Added link to LLVM 


---
Diffs of the changes:

Index: llvm/www/safecode/index.html
diff -u llvm/www/safecode/index.html:1.5 llvm/www/safecode/index.html:1.6
--- llvm/www/safecode/index.html:1.5	Fri Jun  6 16:37:05 2003
+++ llvm/www/safecode/index.html	Fri Jun  6 16:39:30 2003
@@ -20,7 +20,7 @@
 <li><a href="mailto:kowshik at cs.uiuc.edu" > Sumant Kowshik </a> <br>
 <li><a href="http://www.nondot.org/~sabre" > Chris Lattner </a> <br><br>
 </ul>
-
+ 
 <br>
 
 <H3> Publications : </H3> 




From lattner at cs.uiuc.edu  Fri Jun  6 17:14:00 2003
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Fri Jun  6 17:14:00 2003
Subject: [llvm-commits] CVS: llvm/lib/Support/Timer.cpp
Message-ID: <200306062213.RAA29963@apoc.cs.uiuc.edu>


Changes in directory llvm/lib/Support:

Timer.cpp updated: 1.17 -> 1.18

---
Log message:

Fix compilation problem with some versions of G++


---
Diffs of the changes:

Index: llvm/lib/Support/Timer.cpp
diff -u llvm/lib/Support/Timer.cpp:1.17 llvm/lib/Support/Timer.cpp:1.18
--- llvm/lib/Support/Timer.cpp:1.17	Fri Jun  6 16:09:29 2003
+++ llvm/lib/Support/Timer.cpp	Fri Jun  6 17:13:01 2003
@@ -235,7 +235,7 @@
     return &std::cout;
 
   std::ostream *Result = new std::ofstream(LibSupportInfoOutputFilename.c_str(),
-                                           std::ios_base::app);
+                                           std::ios::app);
   if (!Result->good()) {
     std::cerr << "Error opening info-output-file '"
               << LibSupportInfoOutputFilename << " for appending!\n";




From lattner at cs.uiuc.edu  Fri Jun  6 18:07:01 2003
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Fri Jun  6 18:07:01 2003
Subject: [llvm-commits] CVS: llvm/utils/TableGen/CodeEmitterGen.cpp CodeEmitterGen.h
Message-ID: <200306062306.SAA07197@apoc.cs.uiuc.edu>


Changes in directory llvm/utils/TableGen:

CodeEmitterGen.cpp updated: 1.8 -> 1.9
CodeEmitterGen.h updated: 1.1 -> 1.2

---
Log message:

Old versions of GCC doesn't have <ostream> :(


---
Diffs of the changes:

Index: llvm/utils/TableGen/CodeEmitterGen.cpp
diff -u llvm/utils/TableGen/CodeEmitterGen.cpp:1.8 llvm/utils/TableGen/CodeEmitterGen.cpp:1.9
--- llvm/utils/TableGen/CodeEmitterGen.cpp:1.8	Thu Jun  5 19:27:02 2003
+++ llvm/utils/TableGen/CodeEmitterGen.cpp	Fri Jun  6 18:06:20 2003
@@ -1,6 +1,5 @@
 #include "Record.h"
 #include "CodeEmitterGen.h"
-#include <ostream>
 
 void CodeEmitterGen::createEmitter(std::ostream &o) {
   std::vector<Record*> Insts;


Index: llvm/utils/TableGen/CodeEmitterGen.h
diff -u llvm/utils/TableGen/CodeEmitterGen.h:1.1 llvm/utils/TableGen/CodeEmitterGen.h:1.2
--- llvm/utils/TableGen/CodeEmitterGen.h:1.1	Fri May 23 19:15:53 2003
+++ llvm/utils/TableGen/CodeEmitterGen.h	Fri Jun  6 18:06:20 2003
@@ -7,7 +7,7 @@
 #define CODEMITTERGEN_H
 
 #include "Record.h"
-#include <ostream>
+#include <iostream>
 
 struct CodeEmitterGen {
   RecordKeeper &Records;




From brukman at cs.uiuc.edu  Fri Jun  6 21:35:01 2003
From: brukman at cs.uiuc.edu (Misha Brukman)
Date: Fri Jun  6 21:35:01 2003
Subject: [llvm-commits] CVS: llvm/lib/CodeGen/InstrSelection/InstrSelectionSupport.cpp
Message-ID: <200306070234.VAA09519@zion.cs.uiuc.edu>


Changes in directory llvm/lib/CodeGen/InstrSelection:

InstrSelectionSupport.cpp updated: 1.50 -> 1.51

---
Log message:

Do not hastily change the Opcode from 'r' to 'i' type if we're not actually
SETTING the operand to be an immediate or have verified that one of the operands
is really a SignExtended or Unextended immediate value already, which warrants
an 'i' opcode.


---
Diffs of the changes:

Index: llvm/lib/CodeGen/InstrSelection/InstrSelectionSupport.cpp
diff -u llvm/lib/CodeGen/InstrSelection/InstrSelectionSupport.cpp:1.50 llvm/lib/CodeGen/InstrSelection/InstrSelectionSupport.cpp:1.51
--- llvm/lib/CodeGen/InstrSelection/InstrSelectionSupport.cpp:1.50	Tue Jun  3 23:54:06 2003
+++ llvm/lib/CodeGen/InstrSelection/InstrSelectionSupport.cpp	Fri Jun  6 21:34:43 2003
@@ -186,12 +186,6 @@
                                       immedValue);
             if (opType == MachineOperand::MO_VirtualRegister)
               constantThatMustBeLoaded = true;
-            else {
-              // The optype has changed from being a register to an immediate
-              // This means we need to change the opcode, e.g. ADDr -> ADDi
-              unsigned newOpcode = convertOpcodeFromRegToImm(opCode);
-              minstr->setOpcode(newOpcode);
-            }
           }
         }
       else
@@ -209,7 +203,8 @@
                                     opCode, target, (immedPos == (int)op), 
                                     machineRegNum, immedValue);
 
-          if (opType == MachineOperand::MO_SignExtendedImmed) {
+          if (opType == MachineOperand::MO_SignExtendedImmed ||
+              opType == MachineOperand::MO_UnextendedImmed) {
             // The optype is an immediate value
             // This means we need to change the opcode, e.g. ADDr -> ADDi
             unsigned newOpcode = convertOpcodeFromRegToImm(opCode);
@@ -233,6 +228,10 @@
       else if (opType == MachineOperand::MO_SignExtendedImmed ||
                opType == MachineOperand::MO_UnextendedImmed) {
         minstr->SetMachineOperandConst(op, opType, immedValue);
+        // The optype is or has become an immediate
+        // This means we need to change the opcode, e.g. ADDr -> ADDi
+        unsigned newOpcode = convertOpcodeFromRegToImm(opCode);
+        minstr->setOpcode(newOpcode);
       } else if (constantThatMustBeLoaded ||
                (opValue && isa<GlobalValue>(opValue)))
         { // opValue is a constant that must be explicitly loaded into a reg




From brukman at cs.uiuc.edu  Fri Jun  6 21:49:01 2003
From: brukman at cs.uiuc.edu (Misha Brukman)
Date: Fri Jun  6 21:49:01 2003
Subject: [llvm-commits] CVS: llvm/test/Programs/SingleSource/UnitTests/2002-10-09-ArrayResolution.c
Message-ID: <200306070248.VAA09579@zion.cs.uiuc.edu>


Changes in directory llvm/test/Programs/SingleSource/UnitTests:

2002-10-09-ArrayResolution.c updated: 1.1 -> 1.2

---
Log message:

* If we're using printf(), might as well #include <stdio.h>
* 50000 doesn't make much sense for the size of the array, since the point is
  that the upper bound of the loop equals the size of the array (shouldn't it be
  sizeof(array)+1?) The real problem is running 'dis' on a bytecode file with a
  an array of size 50000 and finding it statically initialized with 50000 const
  zeros written out. That grinds the editor to a halt on a slow machine, since
  that's all on the same line. Instead, why not use something manageable, that's
  also a power of 2, say 2**5?


---
Diffs of the changes:

Index: llvm/test/Programs/SingleSource/UnitTests/2002-10-09-ArrayResolution.c
diff -u llvm/test/Programs/SingleSource/UnitTests/2002-10-09-ArrayResolution.c:1.1 llvm/test/Programs/SingleSource/UnitTests/2002-10-09-ArrayResolution.c:1.2
--- llvm/test/Programs/SingleSource/UnitTests/2002-10-09-ArrayResolution.c:1.1	Wed Oct  9 11:48:12 2002
+++ llvm/test/Programs/SingleSource/UnitTests/2002-10-09-ArrayResolution.c	Fri Jun  6 21:48:43 2003
@@ -1,10 +1,13 @@
+#include <stdio.h>
+#define NUM 32
+
 int Array[];
-int Array[50000];
+int Array[NUM];
 int Foo;            /* If writing to the wrong "Array", this will get clobbered */
 
 int main() { 
   unsigned i;
-  for (i = 0; i != 50000; ++i)
+  for (i = 0; i != NUM; ++i)
     Array[i] = 5;
 
   printf("%d\n", Foo);




From lattner at cs.uiuc.edu  Fri Jun  6 23:06:02 2003
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Fri Jun  6 23:06:02 2003
Subject: [llvm-commits] CVS: llvm/test/Programs/MultiSource/Olden-perimeter/main.c
Message-ID: <200306070405.XAA14096@apoc.cs.uiuc.edu>


Changes in directory llvm/test/Programs/MultiSource/Olden-perimeter:

main.c updated: 1.2 -> 1.3

---
Log message:

Allow cranking up the size of the input size a lot


---
Diffs of the changes:

Index: llvm/test/Programs/MultiSource/Olden-perimeter/main.c
diff -u llvm/test/Programs/MultiSource/Olden-perimeter/main.c:1.2 llvm/test/Programs/MultiSource/Olden-perimeter/main.c:1.3
--- llvm/test/Programs/MultiSource/Olden-perimeter/main.c:1.2	Sat Nov  3 00:04:37 2001
+++ llvm/test/Programs/MultiSource/Olden-perimeter/main.c	Fri Jun  6 23:04:59 2003
@@ -210,7 +210,7 @@
   tree=MakeTree(2048,0,0,0,__NumNodes-1,NULL,southeast,level);
 #else
   chatting("Perimeter with %d levels on %d processors\n",level,NumNodes);
-  tree=MakeTree(2048,0,0,0,NumNodes-1,NULL,southeast,level);
+  tree=MakeTree(2048*1024,0,0,0,NumNodes-1,NULL,southeast,level);
 #endif
 
 #ifdef DEBUG




From lattner at cs.uiuc.edu  Fri Jun  6 23:17:00 2003
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Fri Jun  6 23:17:00 2003
Subject: [llvm-commits] CVS: llvm/test/Programs/MultiSource/Olden-power/power.h
Message-ID: <200306070416.XAA14272@apoc.cs.uiuc.edu>


Changes in directory llvm/test/Programs/MultiSource/Olden-power:

power.h updated: 1.3 -> 1.4

---
Log message:

New increased execution time settings


---
Diffs of the changes:

Index: llvm/test/Programs/MultiSource/Olden-power/power.h
diff -u llvm/test/Programs/MultiSource/Olden-power/power.h:1.3 llvm/test/Programs/MultiSource/Olden-power/power.h:1.4
--- llvm/test/Programs/MultiSource/Olden-power/power.h:1.3	Mon May 20 16:52:22 2002
+++ llvm/test/Programs/MultiSource/Olden-power/power.h	Fri Jun  6 23:16:02 2003
@@ -29,10 +29,17 @@
 #define BRANCHES_PER_LATERAL 2
 #define LEAVES_PER_BRANCH 4
 #else
+#if 0  /* DEFAULT SETTINGS */
 #define NUM_FEEDERS 10
 #define LATERALS_PER_FEEDER 20
 #define BRANCHES_PER_LATERAL 5
 #define LEAVES_PER_BRANCH 10
+#else  /* SCALED UP SETTINGS */
+#define NUM_FEEDERS 11
+#define LATERALS_PER_FEEDER 21
+#define BRANCHES_PER_LATERAL 6
+#define LEAVES_PER_BRANCH 12
+#endif
 #endif
 
 #define F_EPSILON 0.000001




From lattner at cs.uiuc.edu  Fri Jun  6 23:39:00 2003
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Fri Jun  6 23:39:00 2003
Subject: [llvm-commits] CVS: llvm/test/Programs/MultiSource/Ptrdist-bc/primes.b
Message-ID: <200306070438.XAA16755@apoc.cs.uiuc.edu>


Changes in directory llvm/test/Programs/MultiSource/Ptrdist-bc:

primes.b updated: 1.1 -> 1.2

---
Log message:

Increase problem size


---
Diffs of the changes:

Index: llvm/test/Programs/MultiSource/Ptrdist-bc/primes.b
diff -u llvm/test/Programs/MultiSource/Ptrdist-bc/primes.b:1.1 llvm/test/Programs/MultiSource/Ptrdist-bc/primes.b:1.2
--- llvm/test/Programs/MultiSource/Ptrdist-bc/primes.b:1.1	Fri Feb 14 13:14:11 2003
+++ llvm/test/Programs/MultiSource/Ptrdist-bc/primes.b	Fri Jun  6 23:37:58 2003
@@ -1,7 +1,7 @@
 
 /* An example that finds all primes between 2 and limit. */
 
-    limit = 500;
+    limit = 1500000;
 
     /* auto prime[], num, p, root, i */
 




From lattner at cs.uiuc.edu  Fri Jun  6 23:39:07 2003
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Fri Jun  6 23:39:07 2003
Subject: [llvm-commits] CVS: llvm/test/Programs/MultiSource/Ptrdist-ft/Makefile
Message-ID: <200306070438.XAA16776@apoc.cs.uiuc.edu>


Changes in directory llvm/test/Programs/MultiSource/Ptrdist-ft:

Makefile updated: 1.2 -> 1.3

---
Log message:

Increase problem size


---
Diffs of the changes:

Index: llvm/test/Programs/MultiSource/Ptrdist-ft/Makefile
diff -u llvm/test/Programs/MultiSource/Ptrdist-ft/Makefile:1.2 llvm/test/Programs/MultiSource/Ptrdist-ft/Makefile:1.3
--- llvm/test/Programs/MultiSource/Ptrdist-ft/Makefile:1.2	Sun May 11 17:25:30 2003
+++ llvm/test/Programs/MultiSource/Ptrdist-ft/Makefile	Fri Jun  6 23:38:47 2003
@@ -1,5 +1,5 @@
 LEVEL = ../../../..
 PROG=ft
-RUN_OPTIONS += 500 1000
+RUN_OPTIONS +=  1500 100000
 
 include ../Makefile.multisrc




From lattner at cs.uiuc.edu  Sat Jun  7 15:31:01 2003
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Sat Jun  7 15:31:01 2003
Subject: [llvm-commits] CVS: llvm/lib/Transforms/IPO/PoolAllocate.cpp
Message-ID: <200306072030.PAA30731@apoc.cs.uiuc.edu>


Changes in directory llvm/lib/Transforms/IPO:

PoolAllocate.cpp updated: 1.7 -> 1.8

---
Log message:

Fix compilation problem on GCC 2.9x


---
Diffs of the changes:

Index: llvm/lib/Transforms/IPO/PoolAllocate.cpp
diff -u llvm/lib/Transforms/IPO/PoolAllocate.cpp:1.7 llvm/lib/Transforms/IPO/PoolAllocate.cpp:1.8
--- llvm/lib/Transforms/IPO/PoolAllocate.cpp:1.7	Wed Jun  4 03:03:57 2003
+++ llvm/lib/Transforms/IPO/PoolAllocate.cpp	Sat Jun  7 15:29:58 2003
@@ -94,7 +94,7 @@
 				  firstCalledF));
 	  if (Callees.size() > 1) {
 	    for (std::vector<GlobalValue*>::iterator CalleesI = 
-		   ++Callees.begin(), CalleesE = Callees.end(); 
+		   Callees.begin()+1, CalleesE = Callees.end(); 
 		 CalleesI != CalleesE; ++CalleesI) {
 	      Function *calledF = dyn_cast<Function>(*CalleesI);
 	      FuncECs.unionSetsWith(firstCalledF, calledF);




From lattner at cs.uiuc.edu  Sat Jun  7 16:45:01 2003
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Sat Jun  7 16:45:01 2003
Subject: [llvm-commits] CVS: llvm/test/Regression/Transforms/LevelRaise/2003-06-07-EmptyArrayTest.ll
Message-ID: <200306072144.QAA31802@apoc.cs.uiuc.edu>


Changes in directory llvm/test/Regression/Transforms/LevelRaise:

2003-06-07-EmptyArrayTest.ll added (r1.1)

---
Log message:

New testcase


---
Diffs of the changes:

Index: llvm/test/Regression/Transforms/LevelRaise/2003-06-07-EmptyArrayTest.ll
diff -c /dev/null llvm/test/Regression/Transforms/LevelRaise/2003-06-07-EmptyArrayTest.ll:1.1
*** /dev/null	Sat Jun  7 16:44:06 2003
--- llvm/test/Regression/Transforms/LevelRaise/2003-06-07-EmptyArrayTest.ll	Sat Jun  7 16:43:56 2003
***************
*** 0 ****
--- 1,10 ----
+ ; RUN: as < %s | opt -raise -disable-output
+ 
+ %T = type { [0 x ubyte] }
+ 
+ void %test(%T* %tmp.22) {
+ 	%tmp.23 = getelementptr %T* %tmp.22, long 0, ubyte 0
+ 	%tmp.24 = cast [0 x ubyte]* %tmp.23 to sbyte**
+ 	%tmp.25 = load sbyte** %tmp.24
+ 	ret void
+ }




From lattner at cs.uiuc.edu  Sat Jun  7 16:46:01 2003
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Sat Jun  7 16:46:01 2003
Subject: [llvm-commits] CVS: llvm/lib/Transforms/TransformInternals.cpp
Message-ID: <200306072145.QAA32090@apoc.cs.uiuc.edu>


Changes in directory llvm/lib/Transforms:

TransformInternals.cpp updated: 1.34 -> 1.35

---
Log message:

Fix bug: LevelRaise/2003-06-07-EmptyArrayTest.ll


---
Diffs of the changes:

Index: llvm/lib/Transforms/TransformInternals.cpp
diff -u llvm/lib/Transforms/TransformInternals.cpp:1.34 llvm/lib/Transforms/TransformInternals.cpp:1.35
--- llvm/lib/Transforms/TransformInternals.cpp:1.34	Tue May 20 13:45:33 2003
+++ llvm/lib/Transforms/TransformInternals.cpp	Sat Jun  7 16:45:42 2003
@@ -56,7 +56,8 @@
     ThisOffset = Offset;
     NextType = getStructOffsetStep(STy, ThisOffset, Indices, TD);
   } else if (const ArrayType *ATy = dyn_cast<ArrayType>(Ty)) {
-    assert(Offset < TD.getTypeSize(ATy) && "Offset not in composite!");
+    assert(Offset == 0 || Offset < TD.getTypeSize(ATy) &&
+           "Offset not in composite!");
 
     NextType = ATy->getElementType();
     unsigned ChildSize = TD.getTypeSize(NextType);




From lattner at cs.uiuc.edu  Sun Jun  8 01:45:02 2003
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Sun Jun  8 01:45:02 2003
Subject: [llvm-commits] CVS: llvm/tools/lli/JIT/Emitter.cpp
Message-ID: <200306080644.BAA00420@apoc.cs.uiuc.edu>


Changes in directory llvm/tools/lli/JIT:

Emitter.cpp updated: 1.13 -> 1.14

---
Log message:

Add #include for older GCC's


---
Diffs of the changes:

Index: llvm/tools/lli/JIT/Emitter.cpp
diff -u llvm/tools/lli/JIT/Emitter.cpp:1.13 llvm/tools/lli/JIT/Emitter.cpp:1.14
--- llvm/tools/lli/JIT/Emitter.cpp:1.13	Fri Jun  6 01:52:35 2003
+++ llvm/tools/lli/JIT/Emitter.cpp	Sun Jun  8 01:43:57 2003
@@ -12,6 +12,7 @@
 #include "llvm/Target/TargetData.h"
 #include "llvm/Function.h"
 #include "Support/Statistic.h"
+#include <stdio.h>
 
 static VM *TheVM = 0;
 




From lattner at cs.uiuc.edu  Sun Jun  8 10:34:02 2003
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Sun Jun  8 10:34:02 2003
Subject: [llvm-commits] CVS: llvm/www/docs/GettingStarted.html
Message-ID: <200306081533.KAA26432@tank.cs.uiuc.edu>


Changes in directory llvm/www/docs:

GettingStarted.html updated: 1.11 -> 1.12

---
Log message:

Fix bug in environment setting


---
Diffs of the changes:

Index: llvm/www/docs/GettingStarted.html
diff -u llvm/www/docs/GettingStarted.html:1.11 llvm/www/docs/GettingStarted.html:1.12
--- llvm/www/docs/GettingStarted.html:1.11	Sun May 25 19:17:49 2003
+++ llvm/www/docs/GettingStarted.html	Sun Jun  8 10:33:25 2003
@@ -185,7 +185,7 @@
        alias llvmgcc <i>LLVMGCCDIR</i><tt>/bin/llvm-gcc</tt>
 
        # Make the LLVM tools easy to use...
-       setenv PATH <i>LLVM_OBJ_DIR</i>/tools/Debug:${PATH}
+       setenv PATH <i>LLVM_OBJ_DIR</i>/llvm/tools/Debug:${PATH}
     </pre>
     The <tt>llvmgcc</tt> alias is useful because the C compiler is not
     included in the CVS tree you just checked out.
@@ -471,7 +471,7 @@
 
 	    <!-- Created: Mon Jul  1 02:29:02 CDT 2002 -->
 	    <!-- hhmts start -->
-Last modified: Sun May 11 16:49:46 CDT 2003
+Last modified: Tue Jun  3 22:06:43 CDT 2003
 <!-- hhmts end -->
   </body>
 </html>




From gshi1 at cs.uiuc.edu  Sun Jun  8 15:41:01 2003
From: gshi1 at cs.uiuc.edu (Guochun Shi)
Date: Sun Jun  8 15:41:01 2003
Subject: [llvm-commits] CVS: llvm/lib/CodeGen/ModuloScheduling/ModuloSchedGraph.cpp ModuloScheduling.cpp ModuloScheduling.h
Message-ID: <200306082040.PAA14093@psmith.cs.uiuc.edu>


Changes in directory llvm/lib/CodeGen/ModuloScheduling:

ModuloSchedGraph.cpp updated: 1.6 -> 1.7
ModuloScheduling.cpp updated: 1.5 -> 1.6
ModuloScheduling.h updated: 1.6 -> 1.7

---
Log message:

 change DEBUG  to DEBUG_PRINT


---
Diffs of the changes:

Index: llvm/lib/CodeGen/ModuloScheduling/ModuloSchedGraph.cpp
diff -u llvm/lib/CodeGen/ModuloScheduling/ModuloSchedGraph.cpp:1.6 llvm/lib/CodeGen/ModuloScheduling/ModuloSchedGraph.cpp:1.7
--- llvm/lib/CodeGen/ModuloScheduling/ModuloSchedGraph.cpp:1.6	Mon Jun  2 12:48:56 2003
+++ llvm/lib/CodeGen/ModuloScheduling/ModuloSchedGraph.cpp	Sun Jun  8 15:40:47 2003
@@ -19,9 +19,7 @@
 #include <algorithm>
 #include <ostream>
 #include <vector>
-// FIXME: Should be using #include <cmath>
 #include <math.h>
-//#include <swig.h>
 
 #define UNIDELAY 1
 
@@ -605,21 +603,21 @@
 
 void ModuloSchedGraph::dumpCircuits()
 {
-  DEBUG(std::cerr << "dumping circuits for graph:\n");
+  DEBUG_PRINT(std::cerr << "dumping circuits for graph:\n");
   int j = -1;
   while (circuits[++j][0] != 0) {
     int k = -1;
     while (circuits[j][++k] != 0)
-      DEBUG(std::cerr << circuits[j][k] << "\t");
-    DEBUG(std::cerr << "\n");
+      DEBUG_PRINT(std::cerr << circuits[j][k] << "\t");
+    DEBUG_PRINT(std::cerr << "\n");
   }
 }
 
 void ModuloSchedGraph::dumpSet(std::vector < ModuloSchedGraphNode * >set)
 {
   for (unsigned i = 0; i < set.size(); i++)
-    DEBUG(std::cerr << set[i]->getNodeId() << "\t");
-  DEBUG(std::cerr << "\n");
+    DEBUG_PRINT(std::cerr << set[i]->getNodeId() << "\t");
+  DEBUG_PRINT(std::cerr << "\n");
 }
 
 std::vector<ModuloSchedGraphNode*>
@@ -708,7 +706,7 @@
   int backEdgeSrc;
   int backEdgeSink;
   if (ModuloScheduling::printScheduleProcess())
-    DEBUG(std::cerr << "building the first set" << "\n");
+    DEBUG_PRINT(std::cerr << "building the first set" << "\n");
   int setSeq = -1;
   int k = -1;
   setSeq++;
@@ -719,7 +717,7 @@
     backEdgeSink = circuits[setSeq][0];
   }
   if (ModuloScheduling::printScheduleProcess()) {
-    DEBUG(std::cerr << "the first set is:");
+    DEBUG_PRINT(std::cerr << "the first set is:");
     dumpSet(set);
   }
   // implement the ordering algorithm
@@ -753,7 +751,7 @@
     while (!R.empty()) {
       if (order == top_down) {
         if (ModuloScheduling::printScheduleProcess())
-          DEBUG(std::cerr << "in top_down round\n");
+          DEBUG_PRINT(std::cerr << "in top_down round\n");
         while (!R.empty()) {
           int maxHeight = -1;
           NodeVec::iterator chosenI;
@@ -797,7 +795,7 @@
         R = vectorConj(predSet(oNodes), set);
       } else {
         if (ModuloScheduling::printScheduleProcess())
-          DEBUG(std::cerr << "in bottom up round\n");
+          DEBUG_PRINT(std::cerr << "in bottom up round\n");
         while (!R.empty()) {
           int maxDepth = -1;
           NodeVec::iterator chosenI;
@@ -824,8 +822,8 @@
       }
     }
     if (ModuloScheduling::printScheduleProcess()) {
-      DEBUG(std::cerr << "order finished\n");
-      DEBUG(std::cerr << "dumping the ordered nodes:\n");
+      DEBUG_PRINT(std::cerr << "order finished\n");
+      DEBUG_PRINT(std::cerr << "dumping the ordered nodes:\n");
       dumpSet(oNodes);
       dumpCircuits();
     }
@@ -833,7 +831,7 @@
     //FIXME: the nodes between onodes and this circuit should also be include in
     //this set
     if (ModuloScheduling::printScheduleProcess())
-      DEBUG(std::cerr << "building the next set\n");
+      DEBUG_PRINT(std::cerr << "building the next set\n");
     set.clear();
     int k = -1;
     setSeq++;
@@ -847,7 +845,7 @@
       //no circuits any more
       //collect all other nodes
       if (ModuloScheduling::printScheduleProcess())
-        DEBUG(std::cerr << "no circuits any more, collect the rest nodes\n");
+        DEBUG_PRINT(std::cerr << "no circuits any more, collect the rest nodes\n");
       for (unsigned i = 2; i < numNodes + 2; i++) {
         bool inset = false;
         for (unsigned j = 0; j < oNodes.size(); j++)
@@ -860,7 +858,7 @@
       }
     }
     if (ModuloScheduling::printScheduleProcess()) {
-      DEBUG(std::cerr << "next set is:\n");
+      DEBUG_PRINT(std::cerr << "next set is:\n");
       dumpSet(set);
     }
   }                             //while(!set.empty())
@@ -917,7 +915,7 @@
     this->dump(bb);
 
   if (!isLoop(bb)) {
-    DEBUG(std::cerr << " dumping non-loop BB:\n");
+    DEBUG_PRINT(std::cerr << " dumping non-loop BB:\n");
     dump(bb);
   }
   if (isLoop(bb)) {
@@ -932,10 +930,10 @@
 
     int ResII = this->computeResII(bb);
     if (ModuloScheduling::printScheduleProcess())
-      DEBUG(std::cerr << "ResII is " << ResII << "\n");
+      DEBUG_PRINT(std::cerr << "ResII is " << ResII << "\n");
     int RecII = this->computeRecII(bb);
     if (ModuloScheduling::printScheduleProcess())
-      DEBUG(std::cerr << "RecII is " << RecII << "\n");
+      DEBUG_PRINT(std::cerr << "RecII is " << RecII << "\n");
 
     this->MII = std::max(ResII, RecII);
 
@@ -995,19 +993,19 @@
 
   while (currentNode != NULL) {
     unsigned currentNodeId = currentNode->getNodeId();
-    // DEBUG(std::cerr<<"current node is "<<currentNodeId<<"\n");
+    // DEBUG_PRINT(std::cerr<<"current node is "<<currentNodeId<<"\n");
 
     ModuloSchedGraphNode *nextNode = NULL;
     for (ModuloSchedGraphNode::const_iterator I =
          currentNode->beginOutEdges(), E = currentNode->endOutEdges();
          I != E; I++) {
-      //DEBUG(std::cerr <<" searching in outgoint edges of node
+      //DEBUG_PRINT(std::cerr <<" searching in outgoint edges of node
       //"<<currentNodeId<<"\n";
       unsigned nodeId = ((SchedGraphEdge *) * I)->getSink()->getNodeId();
       bool inpath = false, instack = false;
       int k;
 
-      //DEBUG(std::cerr<<"nodeId is "<<nodeId<<"\n");
+      //DEBUG_PRINT(std::cerr<<"nodeId is "<<nodeId<<"\n");
 
       k = -1;
       while (path[++k] != 0)
@@ -1031,7 +1029,7 @@
     }
 
     if (nextNode != NULL) {
-      //DEBUG(std::cerr<<"find the next Node "<<nextNode->getNodeId()<<"\n");
+      //DEBUG_PRINT(std::cerr<<"find the next Node "<<nextNode->getNodeId()<<"\n");
 
       int j = 0;
       while (stack[i][j] != 0)
@@ -1042,7 +1040,7 @@
       path[i] = nextNode->getNodeId();
       currentNode = nextNode;
     } else {
-      //DEBUG(std::cerr<<"no expansion any more"<<"\n");
+      //DEBUG_PRINT(std::cerr<<"no expansion any more"<<"\n");
       //confirmCircuit();
       for (ModuloSchedGraphNode::const_iterator I =
            currentNode->beginOutEdges(), E = currentNode->endOutEdges();
@@ -1069,15 +1067,15 @@
     if (i == 0) {
 
       if (ModuloScheduling::printScheduleProcess())
-        DEBUG(std::cerr << "circuits found are:\n");
+        DEBUG_PRINT(std::cerr << "circuits found are:\n");
       int j = -1;
       while (circuits[++j][0] != 0) {
         int k = -1;
         while (circuits[j][++k] != 0)
           if (ModuloScheduling::printScheduleProcess())
-            DEBUG(std::cerr << circuits[j][k] << "\t");
+            DEBUG_PRINT(std::cerr << circuits[j][k] << "\t");
         if (ModuloScheduling::printScheduleProcess())
-          DEBUG(std::cerr << "\n");
+          DEBUG_PRINT(std::cerr << "\n");
 
         //for this circuit, compute the sum of all edge delay
         int sumDelay = 0;
@@ -1107,7 +1105,7 @@
         //       this is correct for SSA form only
         //      
         if (ModuloScheduling::printScheduleProcess())
-          DEBUG(std::cerr << "The total Delay in the circuit is " << sumDelay
+          DEBUG_PRINT(std::cerr << "The total Delay in the circuit is " << sumDelay
                 << "\n");
 
         RecII = RecII > sumDelay ? RecII : sumDelay;
@@ -1124,7 +1122,7 @@
 void ModuloSchedGraph::addResourceUsage(std::vector<std::pair<int,int> > &ruVec,
                                         int rid)
 {
-  //DEBUG(std::cerr<<"\nadding a resouce , current resouceUsage vector size is
+  //DEBUG_PRINT(std::cerr<<"\nadding a resouce , current resouceUsage vector size is
   //"<<ruVec.size()<<"\n";
   bool alreadyExists = false;
   for (unsigned i = 0; i < ruVec.size(); i++) {
@@ -1136,7 +1134,7 @@
   }
   if (!alreadyExists)
     ruVec.push_back(std::make_pair(rid, 1));
-  //DEBUG(std::cerr<<"current resouceUsage vector size is "<<ruVec.size()<<"\n";
+  //DEBUG_PRINT(std::cerr<<"current resouceUsage vector size is "<<ruVec.size()<<"\n";
 
 }
 void ModuloSchedGraph::dumpResourceUsage(std::vector<std::pair<int,int> > &ru)
@@ -1144,18 +1142,18 @@
   TargetSchedInfo & msi = (TargetSchedInfo &) target.getSchedInfo();
 
   std::vector<std::pair<int,int> > resourceNumVector = msi.resourceNumVector;
-  DEBUG(std::cerr << "resourceID\t" << "resourceNum\n");
+  DEBUG_PRINT(std::cerr << "resourceID\t" << "resourceNum\n");
   for (unsigned i = 0; i < resourceNumVector.size(); i++)
-    DEBUG(std::cerr << resourceNumVector[i].
+    DEBUG_PRINT(std::cerr << resourceNumVector[i].
         first << "\t" << resourceNumVector[i].second << "\n");
 
-  DEBUG(std::cerr << " maxNumIssueTotal(issue slot in one cycle) = " << msi.
+  DEBUG_PRINT(std::cerr << " maxNumIssueTotal(issue slot in one cycle) = " << msi.
         maxNumIssueTotal << "\n");
-  DEBUG(std::cerr << "resourceID\t resourceUsage\t ResourceNum\n");
+  DEBUG_PRINT(std::cerr << "resourceID\t resourceUsage\t ResourceNum\n");
   for (unsigned i = 0; i < ru.size(); i++) {
-    DEBUG(std::cerr << ru[i].first << "\t" << ru[i].second);
+    DEBUG_PRINT(std::cerr << ru[i].first << "\t" << ru[i].second);
     const unsigned resNum = msi.getCPUResourceNum(ru[i].first);
-    DEBUG(std::cerr << "\t" << resNum << "\n");
+    DEBUG_PRINT(std::cerr << "\t" << resNum << "\n");
   }
 }
 
@@ -1175,14 +1173,14 @@
   for (BasicBlock::const_iterator I = bb->begin(), E = bb->end(); I != E;
        I++) {
     if (ModuloScheduling::printScheduleProcess()) {
-      DEBUG(std::cerr << "machine instruction for llvm instruction( node " <<
+      DEBUG_PRINT(std::cerr << "machine instruction for llvm instruction( node " <<
             getGraphNodeForInst(I)->getNodeId() << ")\n");
-      DEBUG(std::cerr << "\t" << *I);
+      DEBUG_PRINT(std::cerr << "\t" << *I);
     }
     MachineCodeForInstruction & tempMvec =
         MachineCodeForInstruction::get(I);
     if (ModuloScheduling::printScheduleProcess())
-      DEBUG(std::cerr << "size =" << tempMvec.size() << "\n");
+      DEBUG_PRINT(std::cerr << "size =" << tempMvec.size() << "\n");
     for (unsigned i = 0; i < tempMvec.size(); i++) {
       MachineInstr *minstr = tempMvec[i];
 
@@ -1195,20 +1193,20 @@
       std::vector<std::vector<resourceId_t> > resources=rUsage.resourcesByCycle;
       assert(totCycles == resources.size());
       if (ModuloScheduling::printScheduleProcess())
-        DEBUG(std::cerr << "resources Usage for this Instr(totCycles="
+        DEBUG_PRINT(std::cerr << "resources Usage for this Instr(totCycles="
               << totCycles << ",mindLatency="
               << mii.minLatency(minstr->getOpCode()) << "): " << *minstr
               << "\n");
       for (unsigned j = 0; j < resources.size(); j++) {
         if (ModuloScheduling::printScheduleProcess())
-          DEBUG(std::cerr << "cycle " << j << ": ");
+          DEBUG_PRINT(std::cerr << "cycle " << j << ": ");
         for (unsigned k = 0; k < resources[j].size(); k++) {
           if (ModuloScheduling::printScheduleProcess())
-            DEBUG(std::cerr << "\t" << resources[j][k]);
+            DEBUG_PRINT(std::cerr << "\t" << resources[j][k]);
           addResourceUsage(resourceUsage, resources[j][k]);
         }
         if (ModuloScheduling::printScheduleProcess())
-          DEBUG(std::cerr << "\n");
+          DEBUG_PRINT(std::cerr << "\n");
       }
     }
   }
@@ -1248,19 +1246,19 @@
 
 void ModuloSchedGraphSet::dump() const
 {
-  DEBUG(std::cerr << " ====== ModuloSched graphs for function `" << 
+  DEBUG_PRINT(std::cerr << " ====== ModuloSched graphs for function `" << 
         method->getName() << "' =========\n\n");
   for (const_iterator I = begin(); I != end(); ++I)
     (*I)->dump();
 
-  DEBUG(std::cerr << "\n=========End graphs for function `" << method->getName()
+  DEBUG_PRINT(std::cerr << "\n=========End graphs for function `" << method->getName()
         << "' ==========\n\n");
 }
 
 void ModuloSchedGraph::dump(const BasicBlock * bb)
 {
-  DEBUG(std::cerr << "dumping basic block:");
-  DEBUG(std::cerr << (bb->hasName()? bb->getName() : "block")
+  DEBUG_PRINT(std::cerr << "dumping basic block:");
+  DEBUG_PRINT(std::cerr << (bb->hasName()? bb->getName() : "block")
         << " (" << bb << ")" << "\n");
 }
 
@@ -1273,26 +1271,26 @@
 
 void ModuloSchedGraph::dump() const
 {
-  DEBUG(std::cerr << " ModuloSchedGraph for basic Blocks:");
+  DEBUG_PRINT(std::cerr << " ModuloSchedGraph for basic Blocks:");
 
-  DEBUG(std::cerr << (bb->hasName()? bb->getName() : "block")
+  DEBUG_PRINT(std::cerr << (bb->hasName()? bb->getName() : "block")
 	<< " (" << bb << ")" <<  "");
 
-  DEBUG(std::cerr << "\n\n    Actual Root nodes : ");
+  DEBUG_PRINT(std::cerr << "\n\n    Actual Root nodes : ");
   for (unsigned i = 0, N = graphRoot->outEdges.size(); i < N; i++)
-    DEBUG(std::cerr << graphRoot->outEdges[i]->getSink()->getNodeId()
+    DEBUG_PRINT(std::cerr << graphRoot->outEdges[i]->getSink()->getNodeId()
           << ((i == N - 1) ? "" : ", "));
 
-  DEBUG(std::cerr << "\n    Graph Nodes:\n");
+  DEBUG_PRINT(std::cerr << "\n    Graph Nodes:\n");
   //for (const_iterator I=begin(); I != end(); ++I)
-  //DEBUG(std::cerr << "\n" << *I->second;
+  //DEBUG_PRINT(std::cerr << "\n" << *I->second;
   unsigned numNodes = bb->size();
   for (unsigned i = 2; i < numNodes + 2; i++) {
     ModuloSchedGraphNode *node = getNode(i);
-    DEBUG(std::cerr << "\n" << *node);
+    DEBUG_PRINT(std::cerr << "\n" << *node);
   }
 
-  DEBUG(std::cerr << "\n");
+  DEBUG_PRINT(std::cerr << "\n");
 }
 
 void ModuloSchedGraph::dumpNodeProperty() const
@@ -1301,12 +1299,12 @@
   unsigned numNodes = bb->size();
   for (unsigned i = 2; i < numNodes + 2; i++) {
     ModuloSchedGraphNode *node = getNode(i);
-    DEBUG(std::cerr << "NodeId " << node->getNodeId() << "\t");
-    DEBUG(std::cerr << "ASAP " << node->getASAP() << "\t");
-    DEBUG(std::cerr << "ALAP " << node->getALAP() << "\t");
-    DEBUG(std::cerr << "mov " << node->getMov() << "\t");
-    DEBUG(std::cerr << "depth " << node->getDepth() << "\t");
-    DEBUG(std::cerr << "height " << node->getHeight() << "\t\n");
+    DEBUG_PRINT(std::cerr << "NodeId " << node->getNodeId() << "\t");
+    DEBUG_PRINT(std::cerr << "ASAP " << node->getASAP() << "\t");
+    DEBUG_PRINT(std::cerr << "ALAP " << node->getALAP() << "\t");
+    DEBUG_PRINT(std::cerr << "mov " << node->getMov() << "\t");
+    DEBUG_PRINT(std::cerr << "depth " << node->getDepth() << "\t");
+    DEBUG_PRINT(std::cerr << "height " << node->getHeight() << "\t\n");
   }
 }
 


Index: llvm/lib/CodeGen/ModuloScheduling/ModuloScheduling.cpp
diff -u llvm/lib/CodeGen/ModuloScheduling/ModuloScheduling.cpp:1.5 llvm/lib/CodeGen/ModuloScheduling/ModuloScheduling.cpp:1.6
--- llvm/lib/CodeGen/ModuloScheduling/ModuloScheduling.cpp:1.5	Thu May 29 19:17:09 2003
+++ llvm/lib/CodeGen/ModuloScheduling/ModuloScheduling.cpp	Sun Jun  8 15:40:47 2003
@@ -25,7 +25,8 @@
 #include <algorithm>
 #include <fstream>
 #include <iostream>
-//#include <swig.h>
+
+using std::endl;
 
 //************************************************************
 // printing Debug information
@@ -53,8 +54,11 @@
 //
 void ModuloScheduling::instrScheduling()
 {
+
+  printf(" instrScheduling \n");
+
   if (ModuloScheduling::printScheduleProcess())
-    DEBUG(std::cerr << "************ computing modulo schedule ***********\n");
+    DEBUG_PRINT(std::cerr << "************ computing modulo schedule ***********\n");
 
   const TargetSchedInfo & msi = target.getSchedInfo();
 
@@ -73,7 +77,7 @@
     if (!success) {
       II++;
       if (ModuloScheduling::printScheduleProcess())
-        DEBUG(std::cerr << "increase II  to " << II << "\n");
+        DEBUG_PRINT(std::cerr << "increase II  to " << II << "\n");
     }
   }
 
@@ -89,7 +93,7 @@
 
   //print the original BasicBlock if necessary
   if (ModuloScheduling::printSchedule()) {
-    DEBUG(std::cerr << "dumping the orginal block\n");
+    DEBUG_PRINT(std::cerr << "dumping the orginal block\n");
     graph.dump(bb);
   }
   //construction of prologue, kernel and epilogue
@@ -108,11 +112,11 @@
 
   //print the BasicBlocks if necessary
   if (ModuloScheduling::printSchedule()) {
-    DEBUG(std::cerr << "dumping the prologue block:\n");
+    DEBUG_PRINT(std::cerr << "dumping the prologue block:\n");
     graph.dump(prologue);
-    DEBUG(std::cerr << "dumping the kernel block\n");
+    DEBUG_PRINT(std::cerr << "dumping the kernel block\n");
     graph.dump(kernel);
-    DEBUG(std::cerr << "dumping the epilogue block\n");
+    DEBUG_PRINT(std::cerr << "dumping the epilogue block\n");
     graph.dump(epilogue);
   }
 }
@@ -124,8 +128,8 @@
   unsigned numIssueSlots = msi.maxNumIssueTotal;
   // clear nodeScheduled from the last round
   if (ModuloScheduling::printScheduleProcess()) {
-    DEBUG(std::cerr << "***** new round  with II= " << II << " ***********\n");
-    DEBUG(std::cerr <<
+    DEBUG_PRINT(std::cerr << "***** new round  with II= " << II << " ***********\n");
+    DEBUG_PRINT(std::cerr <<
         " ************clear the vector nodeScheduled*************\n");
   }
   nodeScheduled.clear();
@@ -156,7 +160,7 @@
 {
 
   if (ModuloScheduling::printScheduleProcess())
-    DEBUG(std::cerr << "start to compute schedule\n");
+    DEBUG_PRINT(std::cerr << "start to compute schedule\n");
 
   // Loop over the ordered nodes
   for (NodeVec::const_iterator I = oNodes.begin(); I != oNodes.end(); ++I) {
@@ -253,7 +257,7 @@
     }
     //try to schedule this node based on the startTime and endTime
     if (ModuloScheduling::printScheduleProcess())
-      DEBUG(std::cerr << "scheduling the node " << (*I)->getNodeId() << "\n");
+      DEBUG_PRINT(std::cerr << "scheduling the node " << (*I)->getNodeId() << "\n");
 
     bool success =
         this->ScheduleNode(node, startTime, endTime, nodeScheduled);
@@ -622,16 +626,16 @@
   unsigned int numIssueSlots = msi.maxNumIssueTotal;
 
   if (ModuloScheduling::printScheduleProcess())
-    DEBUG(std::cerr << "startTime= " << start << " endTime= " << end << "\n");
+    DEBUG_PRINT(std::cerr << "startTime= " << start << " endTime= " << end << "\n");
   bool isScheduled = false;
   for (unsigned i = start; i <= end; i++) {
     if (ModuloScheduling::printScheduleProcess())
-      DEBUG(std::cerr << " now try cycle " << i << ":" << "\n");
+      DEBUG_PRINT(std::cerr << " now try cycle " << i << ":" << "\n");
     for (unsigned j = 0; j < numIssueSlots; j++) {
       unsigned int core_i = i % II;
       unsigned int core_j = j;
       if (ModuloScheduling::printScheduleProcess())
-        DEBUG(std::cerr << "\t Trying slot " << j << "...........");
+        DEBUG_PRINT(std::cerr << "\t Trying slot " << j << "...........");
       //check the resouce table, make sure there is no resource conflicts
       const Instruction *instr = node->getInst();
       MachineCodeForInstruction & tempMvec =
@@ -671,8 +675,8 @@
       }
       if (!resourceConflict && !coreSchedule[core_i][core_j]) {
         if (ModuloScheduling::printScheduleProcess()) {
-          DEBUG(std::cerr << " OK!" << "\n");
-          DEBUG(std::cerr << "Node " << node->getNodeId() << " scheduled.\n");
+          DEBUG_PRINT(std::cerr << " OK!" << "\n");
+          DEBUG_PRINT(std::cerr << "Node " << node->getNodeId() << " scheduled.\n");
         }
         //schedule[i][j]=node;
         while (schedule.size() <= i) {
@@ -710,10 +714,10 @@
         break;
       } else if (coreSchedule[core_i][core_j]) {
         if (ModuloScheduling::printScheduleProcess())
-          DEBUG(std::cerr << " Slot not available\n");
+          DEBUG_PRINT(std::cerr << " Slot not available\n");
       } else {
         if (ModuloScheduling::printScheduleProcess())
-          DEBUG(std::cerr << " Resource conflicts\n");
+          DEBUG_PRINT(std::cerr << " Resource conflicts\n");
       }
     }
     if (isScheduled)
@@ -798,12 +802,12 @@
 
 void ModuloScheduling::dumpResourceUsageTable()
 {
-  DEBUG(std::cerr << "dumping resource usage table\n");
+  DEBUG_PRINT(std::cerr << "dumping resource usage table\n");
   for (unsigned i = 0; i < resourceTable.size(); i++) {
     for (unsigned j = 0; j < resourceTable[i].size(); j++)
-      DEBUG(std::cerr << resourceTable[i][j].first 
+      DEBUG_PRINT(std::cerr << resourceTable[i][j].first 
             << ":" << resourceTable[i][j].second << " ");
-    DEBUG(std::cerr << "\n");
+    DEBUG_PRINT(std::cerr << "\n");
   }
 
 }
@@ -819,16 +823,16 @@
   const TargetSchedInfo & msi = target.getSchedInfo();
   unsigned numIssueSlots = msi.maxNumIssueTotal;
   for (unsigned i = 0; i < numIssueSlots; i++)
-    DEBUG(std::cerr << "\t#");
-  DEBUG(std::cerr << "\n");
+    DEBUG_PRINT(std::cerr << "\t#");
+  DEBUG_PRINT(std::cerr << "\n");
   for (unsigned i = 0; i < thisSchedule.size(); i++) {
-    DEBUG(std::cerr << "cycle" << i << ": ");
+    DEBUG_PRINT(std::cerr << "cycle" << i << ": ");
     for (unsigned j = 0; j < thisSchedule[i].size(); j++)
       if (thisSchedule[i][j] != NULL)
-        DEBUG(std::cerr << thisSchedule[i][j]->getNodeId() << "\t");
+        DEBUG_PRINT(std::cerr << thisSchedule[i][j]->getNodeId() << "\t");
       else
-        DEBUG(std::cerr << "\t");
-    DEBUG(std::cerr << "\n");
+        DEBUG_PRINT(std::cerr << "\t");
+    DEBUG_PRINT(std::cerr << "\n");
   }
 }
 
@@ -842,34 +846,34 @@
 
 void ModuloScheduling::dumpScheduling()
 {
-  DEBUG(std::cerr << "dump schedule:" << "\n");
+  DEBUG_PRINT(std::cerr << "dump schedule:" << "\n");
   const TargetSchedInfo & msi = target.getSchedInfo();
   unsigned numIssueSlots = msi.maxNumIssueTotal;
   for (unsigned i = 0; i < numIssueSlots; i++)
-    DEBUG(std::cerr << "\t#");
-  DEBUG(std::cerr << "\n");
+    DEBUG_PRINT(std::cerr << "\t#");
+  DEBUG_PRINT(std::cerr << "\n");
   for (unsigned i = 0; i < schedule.size(); i++) {
-    DEBUG(std::cerr << "cycle" << i << ": ");
+    DEBUG_PRINT(std::cerr << "cycle" << i << ": ");
     for (unsigned j = 0; j < schedule[i].size(); j++)
       if (schedule[i][j] != NULL)
-        DEBUG(std::cerr << schedule[i][j]->getNodeId() << "\t");
+        DEBUG_PRINT(std::cerr << schedule[i][j]->getNodeId() << "\t");
       else
-        DEBUG(std::cerr << "\t");
-    DEBUG(std::cerr << "\n");
+        DEBUG_PRINT(std::cerr << "\t");
+    DEBUG_PRINT(std::cerr << "\n");
   }
 
-  DEBUG(std::cerr << "dump coreSchedule:" << "\n");
+  DEBUG_PRINT(std::cerr << "dump coreSchedule:" << "\n");
   for (unsigned i = 0; i < numIssueSlots; i++)
-    DEBUG(std::cerr << "\t#");
-  DEBUG(std::cerr << "\n");
+    DEBUG_PRINT(std::cerr << "\t#");
+  DEBUG_PRINT(std::cerr << "\n");
   for (unsigned i = 0; i < coreSchedule.size(); i++) {
-    DEBUG(std::cerr << "cycle" << i << ": ");
+    DEBUG_PRINT(std::cerr << "cycle" << i << ": ");
     for (unsigned j = 0; j < coreSchedule[i].size(); j++)
       if (coreSchedule[i][j] != NULL)
-        DEBUG(std::cerr << coreSchedule[i][j]->getNodeId() << "\t");
+        DEBUG_PRINT(std::cerr << coreSchedule[i][j]->getNodeId() << "\t");
       else
-        DEBUG(std::cerr << "\t");
-    DEBUG(std::cerr << "\n");
+        DEBUG_PRINT(std::cerr << "\t");
+    DEBUG_PRINT(std::cerr << "\n");
   }
 }
 


Index: llvm/lib/CodeGen/ModuloScheduling/ModuloScheduling.h
diff -u llvm/lib/CodeGen/ModuloScheduling/ModuloScheduling.h:1.6 llvm/lib/CodeGen/ModuloScheduling/ModuloScheduling.h:1.7
--- llvm/lib/CodeGen/ModuloScheduling/ModuloScheduling.h:1.6	Mon Jun  2 12:48:56 2003
+++ llvm/lib/CodeGen/ModuloScheduling/ModuloScheduling.h	Sun Jun  8 15:40:47 2003
@@ -13,6 +13,8 @@
 #include <iostream>
 #include <vector>
 
+#define DEBUG_PRINT(x) x
+
 // for debug information selecton
 enum ModuloSchedDebugLevel_t { 
   ModuloSchedDebugLevel_NoDebugInfo,




From gshi1 at cs.uiuc.edu  Sun Jun  8 18:17:01 2003
From: gshi1 at cs.uiuc.edu (Guochun Shi)
Date: Sun Jun  8 18:17:01 2003
Subject: [llvm-commits] CVS: llvm/lib/CodeGen/ModuloScheduling/ModuloSchedGraph.cpp ModuloSchedGraph.h ModuloScheduling.cpp ModuloScheduling.h
Message-ID: <200306082316.SAA14296@psmith.cs.uiuc.edu>


Changes in directory llvm/lib/CodeGen/ModuloScheduling:

ModuloSchedGraph.cpp updated: 1.7 -> 1.8
ModuloSchedGraph.h updated: 1.6 -> 1.7
ModuloScheduling.cpp updated: 1.6 -> 1.7
ModuloScheduling.h updated: 1.7 -> 1.8

---
Log message:

delete useless functions
add comment


---
Diffs of the changes:

Index: llvm/lib/CodeGen/ModuloScheduling/ModuloSchedGraph.cpp
diff -u llvm/lib/CodeGen/ModuloScheduling/ModuloSchedGraph.cpp:1.7 llvm/lib/CodeGen/ModuloScheduling/ModuloSchedGraph.cpp:1.8
--- llvm/lib/CodeGen/ModuloScheduling/ModuloSchedGraph.cpp:1.7	Sun Jun  8 15:40:47 2003
+++ llvm/lib/CodeGen/ModuloScheduling/ModuloSchedGraph.cpp	Sun Jun  8 18:16:07 2003
@@ -21,83 +21,42 @@
 #include <vector>
 #include <math.h>
 
+
 #define UNIDELAY 1
 
-//*********************** Internal Data Structures *************************/
+using std::cerr;
+using std::endl;
+using std::vector;
 
-// The following two types need to be classes, not typedefs, so we can use
-// opaque declarations in SchedGraph.h
-// 
-struct RefVec:public std::vector<std::pair<ModuloSchedGraphNode*,int> > {
-  typedef std::vector<std::pair<ModuloSchedGraphNode*,
-                                int> >::iterator iterator;
-  typedef std::vector<std::pair<ModuloSchedGraphNode*,
-                                int> >::const_iterator const_iterator;
-};
 
-struct RegToRefVecMap:public hash_map<int,RefVec> {
-  typedef hash_map<int,RefVec>::iterator iterator;
-  typedef hash_map<int,RefVec>::const_iterator const_iterator;
-};
+/***********member functions for ModuloSchedGraphNode*********/
 
-struct ValueToDefVecMap:public hash_map<const Instruction*,RefVec> {
-  typedef hash_map<const Instruction*, RefVec>::iterator iterator;
-  typedef hash_map<const Instruction*,
-                        RefVec>::const_iterator const_iterator;
-};
-
-// class Modulo SchedGraphNode
 
 ModuloSchedGraphNode::ModuloSchedGraphNode(unsigned int in_nodeId,
                                            const BasicBlock * in_bb,
                                            const Instruction * in_inst,
                                            int indexInBB,
                                            const TargetMachine & target)
-:SchedGraphNodeCommon(in_nodeId, indexInBB), inst(in_inst)
-{
+  :SchedGraphNodeCommon(in_nodeId, indexInBB), inst(in_inst){
+  
   if (inst) {
     //FIXME: find the latency 
-    //currently setthe latency to zero
+    //currently set the latency to zero
     latency = 0;
   }
 }
 
-//class ModuloScheGraph
 
-void ModuloSchedGraph::addDummyEdges()
-{
-  assert(graphRoot->outEdges.size() == 0);
+/***********member functions for ModuloSchedGraph*********/
 
-  for (const_iterator I = begin(); I != end(); ++I) {
-    ModuloSchedGraphNode *node = (ModuloSchedGraphNode *) ((*I).second);
-    assert(node != graphRoot && node != graphLeaf);
-    if (node->beginInEdges() == node->endInEdges())
-      (void) new SchedGraphEdge(graphRoot, node, SchedGraphEdge::CtrlDep,
-                                SchedGraphEdge::NonDataDep, 0);
-    if (node->beginOutEdges() == node->endOutEdges())
-      (void) new SchedGraphEdge(node, graphLeaf, SchedGraphEdge::CtrlDep,
-                                SchedGraphEdge::NonDataDep, 0);
-  }
-}
-
-bool isDefinition(const Instruction *I)
-{
-  //if(TerminatorInst::classof(I)||FreeInst::classof(I) || StoreInst::classof(I) || CallInst::classof(I))
-  if (!I->hasName())
-    return false;
-  else
-    return true;
-}
-
-void ModuloSchedGraph::addDefUseEdges(const BasicBlock *bb)
-{
+void 
+ModuloSchedGraph::addDefUseEdges(const BasicBlock *bb){
+  
   //collect def instructions, store them in vector
-  //  const TargetInstrInfo& mii = target.getInstrInfo();
   const TargetInstrInfo & mii = target.getInstrInfo();
-
-  typedef std::vector < ModuloSchedGraphNode * >DefVec;
-  DefVec defVec;
-
+  vector < ModuloSchedGraphNode * > defVec;
+  
+  
   //find those def instructions
   for (BasicBlock::const_iterator I = bb->begin(), E = bb->end(); I != E; ++I) {
     if (I->getType() != Type::VoidTy) {
@@ -115,38 +74,40 @@
       Instruction *inst = (Instruction *) (*I);
       ModuloSchedGraphNode *node = NULL;
 
-      for (BasicBlock::const_iterator I = bb->begin(), E = bb->end();
-           I != E; ++I)
-        if ((const Instruction *) I == inst) {
+      for (BasicBlock::const_iterator ins = bb->begin(), E = bb->end();
+           ins != E; ++ins)
+        if ((const Instruction *) ins == inst) {
           node = (*this)[inst];
           break;
         }
 
-      assert(inst != NULL && " Use not an Instruction ?");
 
-      if (node == NULL)         //inst is not an instruction in this block
-      {
+      if (node == NULL){
+	
+	//inst is not an instruction in this block
+	//do nothing
+
       } else {
         // Add a flow edge from the def instruction to the ref instruction
-
+	// This is a true dependence, so the delay is equal to the 
+	//delay of the preceding node.
+	
+        int delay = 0;
+	
         // self loop will not happen in SSA form
         assert(defVec[i] != node && "same node?");
 
-        // This is a true dependence, so the delay is equal to the delay of the
-        // pred node.
-        int delay = 0;
         MachineCodeForInstruction & tempMvec =
             MachineCodeForInstruction::get(value);
         for (unsigned j = 0; j < tempMvec.size(); j++) {
           MachineInstr *temp = tempMvec[j];
-          //delay +=mii.minLatency(temp->getOpCode());
           delay = std::max(delay, mii.minLatency(temp->getOpCode()));
         }
 
         SchedGraphEdge *trueEdge =
-            new SchedGraphEdge(defVec[i], node, value,
+	  new SchedGraphEdge(defVec[i], node, value,
                                SchedGraphEdge::TrueDep, delay);
-
+	
         // if the ref instruction is before the def instrution
         // then the def instruction must be a phi instruction 
         // add an anti-dependence edge to from the ref instruction to the def
@@ -163,11 +124,14 @@
   }
 }
 
-void ModuloSchedGraph::addCDEdges(const BasicBlock * bb) {
+void 
+ModuloSchedGraph::addCDEdges(const BasicBlock * bb) {
+
   // find the last instruction in the basic block
   // see if it is an branch instruction. 
-  // If yes, then add an edge from each node expcept the last node to the last
-  // node
+  // If yes, then add an edge from each node expcept the last node 
+  //to the last node
+
   const Instruction *inst = &(bb->back());
   ModuloSchedGraphNode *lastNode = (*this)[inst];
   if (TerminatorInst::classof(inst))
@@ -179,7 +143,7 @@
         (void) new SchedGraphEdge(node, lastNode, SchedGraphEdge::CtrlDep,
                                   SchedGraphEdge::NonDataDep, 0);
       }
-
+      
     }
 }
 
@@ -206,30 +170,46 @@
 // Use latency 1 just to ensure that memory operations are ordered;
 // latency does not otherwise matter (true dependences enforce that).
 // 
-void ModuloSchedGraph::addMemEdges(const BasicBlock * bb) {
-
-  std::vector<ModuloSchedGraphNode*> memNodeVec;
+void 
+ModuloSchedGraph::addMemEdges(const BasicBlock * bb) {
 
+  vector<ModuloSchedGraphNode*> memNodeVec;
+  
   //construct the memNodeVec
-  for (BasicBlock::const_iterator I = bb->begin(), E = bb->end(); I != E; ++I) {
+  for (BasicBlock::const_iterator I = bb->begin(), 
+	 E = bb->end(); I != E; ++I) {
+
     if (LoadInst::classof(I) || StoreInst::classof(I)
         || CallInst::classof(I)) {
+
       ModuloSchedGraphNode *node = (*this)[(const Instruction *) I];
       memNodeVec.push_back(node);
+      
     }
   }
 
-  // Instructions in memNodeVec are in execution order within the basic block,
-  // so simply look at all pairs <memNodeVec[i], memNodeVec[j: j > i]>.
-  // 
+  // Instructions in memNodeVec are in execution order within the 
+  // basic block, so simply look at all pairs 
+  // <memNodeVec[i], memNodeVec[j: j > i]>.
+
   for (unsigned im = 0, NM = memNodeVec.size(); im < NM; im++) {
-    const Instruction *fromInst = memNodeVec[im]->getInst();
-    int fromType = CallInst::classof(fromInst) ? SG_CALL_REF
-        : LoadInst::classof(fromInst) ? SG_LOAD_REF : SG_STORE_REF;
+    
+    const Instruction *fromInst,*toInst;
+    int toType, fromType;
+    
+    //get the first mem instruction and instruction type
+    fromInst = memNodeVec[im]->getInst();
+    fromType = CallInst::classof(fromInst) ? SG_CALL_REF
+      : LoadInst::classof(fromInst) ? SG_LOAD_REF : SG_STORE_REF;
+    
     for (unsigned jm = im + 1; jm < NM; jm++) {
-      const Instruction *toInst = memNodeVec[jm]->getInst();
-      int toType = CallInst::classof(toInst) ? SG_CALL_REF
+      
+      //get the second mem instruction and instruction type
+      toInst = memNodeVec[jm]->getInst();
+      toType = CallInst::classof(toInst) ? SG_CALL_REF
           : LoadInst::classof(toInst) ? SG_LOAD_REF : SG_STORE_REF;
+      
+      //add two edges if not both of them are LOAD instructions
       if (fromType != SG_LOAD_REF || toType != SG_LOAD_REF) {
         (void) new SchedGraphEdge(memNodeVec[im], memNodeVec[jm],
                                   SchedGraphEdge::MemoryDep,
@@ -239,8 +219,10 @@
             new SchedGraphEdge(memNodeVec[jm], memNodeVec[im],
                                SchedGraphEdge::MemoryDep,
                                SG_DepOrderArray[toType][fromType], 1);
-        edge->setIteDiff(1);
 
+	//set the iteration difference for this edge to 1.
+        edge->setIteDiff(1);
+	
       }
     }
   }
@@ -248,36 +230,32 @@
 
 
 
-void ModuloSchedGraph::buildNodesforBB(const TargetMachine &target,
-                                       const BasicBlock *bb,
-                                    std::vector<ModuloSchedGraphNode*> &memNode,
-                                       RegToRefVecMap &regToRefVecMap,
-                                       ValueToDefVecMap &valueToDefVecMap)
-{
-  //const TargetInstrInfo& mii=target.getInstrInfo();
-
-  //Build graph nodes for each LLVM instruction and gather def/use info.
-  //Do both together in a single pass over all machine instructions.
-
+void 
+ModuloSchedGraph::buildNodesforBB(const TargetMachine &target,
+				  const BasicBlock *bb){
+  
   int i = 0;
-  for (BasicBlock::const_iterator I = bb->begin(), E = bb->end(); I != E; 
-       ++I) {
-    ModuloSchedGraphNode *node =
-        new ModuloSchedGraphNode(getNumNodes(), bb, I, i, target);
+  ModuloSchedGraphNode *node;
+
+  for (BasicBlock::const_iterator I = bb->begin(), E = bb->end(); 
+       I != E; ++I) {
+    
+    node=new ModuloSchedGraphNode(getNumNodes(), bb, I, i, target);
+    
     i++;
-    this->noteModuloSchedGraphNodeForInst(I, node);
+    
+    this->addHash(I, node);
   }
 
-  //this function finds some info about instruction in basic block for later use
-  //findDefUseInfoAtInstr(target, node,
-  //memNode,regToRefVecMap,valueToDefVecMap);
 }
 
 
-bool ModuloSchedGraph::isLoop(const BasicBlock *bb) {
+bool 
+ModuloSchedGraph::isLoop(const BasicBlock *bb) {
+  
   //only if the last instruction in the basicblock is branch instruction and 
   //there is at least an option to branch itself
-
+  
   const Instruction *inst = &(bb->back());
   if (BranchInst::classof(inst)) {
     for (unsigned i = 0; i < ((BranchInst *) inst)->getNumSuccessors();
@@ -292,24 +270,6 @@
 
 }
 
-bool ModuloSchedGraph::isLoop() {
-  //only if the last instruction in the basicblock is branch instruction and 
-  //there is at least an option to branch itself
-
-  assert(this->bb&& "the basicblock is not empty");
-  const Instruction *inst = &(bb->back());
-  if (BranchInst::classof(inst))
-    for (unsigned i = 0; i < ((BranchInst *) inst)->getNumSuccessors();
-         i++) {
-      BasicBlock *sb = ((BranchInst *) inst)->getSuccessor(i);
-      if (sb == bb)
-        return true;
-    }
-  
-  return false;
-
-}
-
 void ModuloSchedGraph::computeNodeASAP(const BasicBlock *bb) {
 
   //FIXME: now assume the only backward edges come from the edges from other
@@ -872,27 +832,6 @@
 
   assert(this->bb && "The basicBlock is NULL?");
 
-  // Use this data structure to note all machine operands that compute
-  // ordinary LLVM values.  These must be computed defs (i.e., instructions). 
-  // Note that there may be multiple machine instructions that define
-  // each Value.
-  ValueToDefVecMap valueToDefVecMap;
-
-  // Use this data structure to note all memory instructions.
-  // We use this to add memory dependence edges without a second full walk.
-  // 
-  // vector<const Instruction*> memVec;
-  std::vector<ModuloSchedGraphNode*> memNodeVec;
-
-  // Use this data structure to note any uses or definitions of
-  // machine registers so we can add edges for those later without
-  // extra passes over the nodes.
-  // The vector holds an ordered list of references to the machine reg,
-  // ordered according to control-flow order.  This only works for a
-  // single basic block, hence the assertion.  Each reference is identified
-  // by the pair: <node, operand-number>.
-  // 
-  RegToRefVecMap regToRefVecMap;
 
   // Make a dummy root node.  We'll add edges to the real roots later.
   graphRoot = new ModuloSchedGraphNode(0, NULL, NULL, -1, target);
@@ -913,21 +852,21 @@
 
   if (ModuloScheduling::printScheduleProcess())
     this->dump(bb);
-
-  if (!isLoop(bb)) {
-    DEBUG_PRINT(std::cerr << " dumping non-loop BB:\n");
-    dump(bb);
-  }
+  
   if (isLoop(bb)) {
-    buildNodesforBB(target, bb, memNodeVec, regToRefVecMap,
-                    valueToDefVecMap);
 
+    DEBUG_PRINT(cerr << "building nodes for this BasicBlock\n");
+    buildNodesforBB(target, bb);
+    
+    DEBUG_PRINT(cerr << "adding def-use edge to this basic block\n");
     this->addDefUseEdges(bb);
-    this->addCDEdges(bb);
-    this->addMemEdges(bb);
 
-    //this->dump();
+    DEBUG_PRINT(cerr << "adding CD edges to this basic block\n");
+    this->addCDEdges(bb);
 
+    DEBUG_PRINT(cerr << "adding memory edges to this basicblock\n");
+    this->addMemEdges(bb);
+    
     int ResII = this->computeResII(bb);
     if (ModuloScheduling::printScheduleProcess())
       DEBUG_PRINT(std::cerr << "ResII is " << ResII << "\n");
@@ -942,11 +881,12 @@
       this->dumpNodeProperty();
 
     this->orderNodes();
-
+    
     if (ModuloScheduling::printScheduleProcess())
       this->dump();
-    //this->instrScheduling();
 
+    //this->instrScheduling();
+    
     //this->dumpScheduling();
   }
 }
@@ -1229,31 +1169,8 @@
   return ResII;
 }
 
-ModuloSchedGraphSet::ModuloSchedGraphSet(const Function *function,
-                                         const TargetMachine &target)
-:  method(function)
-{
-  buildGraphsForMethod(method, target);
-}
 
 
-ModuloSchedGraphSet::~ModuloSchedGraphSet()
-{
-  //delete all the graphs
-  for (iterator I = begin(), E = end(); I != E; ++I)
-    delete *I;
-}
-
-void ModuloSchedGraphSet::dump() const
-{
-  DEBUG_PRINT(std::cerr << " ====== ModuloSched graphs for function `" << 
-        method->getName() << "' =========\n\n");
-  for (const_iterator I = begin(); I != end(); ++I)
-    (*I)->dump();
-
-  DEBUG_PRINT(std::cerr << "\n=========End graphs for function `" << method->getName()
-        << "' ==========\n\n");
-}
 
 void ModuloSchedGraph::dump(const BasicBlock * bb)
 {
@@ -1308,15 +1225,68 @@
   }
 }
 
-void ModuloSchedGraphSet::buildGraphsForMethod(const Function *F,
-                                               const TargetMachine &target)
-{
+
+
+
+/************member functions for ModuloSchedGraphSet**************/
+
+ModuloSchedGraphSet::ModuloSchedGraphSet(const Function *function,
+                                         const TargetMachine &target)
+:  method(function){
+  
+  buildGraphsForMethod(method, target);
+
+}
+
+
+ModuloSchedGraphSet::~ModuloSchedGraphSet(){
+  
+  //delete all the graphs
+  for (iterator I = begin(), E = end(); I != E; ++I)
+    delete *I;
+}
+
+
+
+void 
+ModuloSchedGraphSet::buildGraphsForMethod(const Function *F,
+					  const TargetMachine &target){
+  
   for (Function::const_iterator BI = F->begin(); BI != F->end(); ++BI){
     const BasicBlock* local_bb;
+    
     local_bb=BI;
     addGraph(new ModuloSchedGraph((BasicBlock*)local_bb, target));
   }
+  
+}
+
+void 
+ModuloSchedGraphSet::dump() const{
+  
+  DEBUG_PRINT(std::cerr << " ====== ModuloSched graphs for function `" << 
+	      method->getName() << "' =========\n\n");
+  for (const_iterator I = begin(); I != end(); ++I)
+    (*I)->dump();
+  
+  DEBUG_PRINT(std::cerr << "\n=========End graphs for function `" << method->getName()
+	      << "' ==========\n\n");
+}
+
+
+
+
+/********************misc functions***************************/
+
+
+static void 
+dumpBasicBlock(const BasicBlock * bb){
+  
+  DEBUG_PRINT(std::cerr << "dumping basic block:");
+  DEBUG_PRINT(std::cerr << (bb->hasName()? bb->getName() : "block")
+	      << " (" << bb << ")" << "\n");
 }
+
 
 std::ostream& operator<<(std::ostream &os,
                          const ModuloSchedGraphNode &node)


Index: llvm/lib/CodeGen/ModuloScheduling/ModuloSchedGraph.h
diff -u llvm/lib/CodeGen/ModuloScheduling/ModuloSchedGraph.h:1.6 llvm/lib/CodeGen/ModuloScheduling/ModuloSchedGraph.h:1.7
--- llvm/lib/CodeGen/ModuloScheduling/ModuloSchedGraph.h:1.6	Mon Jun  2 12:48:56 2003
+++ llvm/lib/CodeGen/ModuloScheduling/ModuloSchedGraph.h	Sun Jun  8 18:16:07 2003
@@ -250,9 +250,6 @@
   //return wether the BasicBlock 'bb' contains a loop
   bool isLoop(const BasicBlock *bb);
 
-  //return this basibBlock contains a loop
-  bool isLoop();
-
   //return the node for the input instruction
   ModuloSchedGraphNode *getGraphNodeForInst(const Instruction *inst) const {
     const_iterator onePair = this->find(inst);
@@ -293,11 +290,12 @@
   using map_base::begin;
   using map_base::end;
 
-  void noteModuloSchedGraphNodeForInst(const Instruction *inst,
-                                       ModuloSchedGraphNode *node)
-  {
+  void addHash(const Instruction *inst,
+	       ModuloSchedGraphNode *node){
+    
     assert((*this)[inst] == NULL);
     (*this)[inst] = node;
+    
   }
 
   // Graph builder
@@ -308,10 +306,7 @@
 
   // Build nodes for BasicBlock
   void buildNodesforBB(const TargetMachine &target,
-                       const BasicBlock *bb,
-                       NodeVec &memNode,
-                       RegToRefVecMap &regToRefVecMap,
-                       ValueToDefVecMap &valueToDefVecMap);
+                       const BasicBlock *bb);
 
   //find definitiona and use information for all nodes
   void findDefUseInfoAtInstr(const TargetMachine &target,
@@ -328,9 +323,6 @@
 
   //add memory dependence dges
   void addMemEdges(const BasicBlock *bb);
-
-  //add dummy edges
-  void addDummyEdges();
 
   //computer source restrictoin II
   int computeResII(const BasicBlock *bb);


Index: llvm/lib/CodeGen/ModuloScheduling/ModuloScheduling.cpp
diff -u llvm/lib/CodeGen/ModuloScheduling/ModuloScheduling.cpp:1.6 llvm/lib/CodeGen/ModuloScheduling/ModuloScheduling.cpp:1.7
--- llvm/lib/CodeGen/ModuloScheduling/ModuloScheduling.cpp:1.6	Sun Jun  8 15:40:47 2003
+++ llvm/lib/CodeGen/ModuloScheduling/ModuloScheduling.cpp	Sun Jun  8 18:16:07 2003
@@ -97,28 +97,34 @@
     graph.dump(bb);
   }
   //construction of prologue, kernel and epilogue
+  
+  /*
   BasicBlock *kernel = bb->splitBasicBlock(bb->begin());
   BasicBlock *prologue = bb;
   BasicBlock *epilogue = kernel->splitBasicBlock(kernel->begin());
+  */
 
   // Construct prologue
-  constructPrologue(prologue);
+  /*constructPrologue(prologue);*/
 
   // Construct kernel
-  constructKernel(prologue, kernel, epilogue);
+  
+  /*constructKernel(prologue, kernel, epilogue);*/
 
   // Construct epilogue
-  constructEpilogue(epilogue, succ_bb);
 
+  /*constructEpilogue(epilogue, succ_bb);*/
+  
   //print the BasicBlocks if necessary
-  if (ModuloScheduling::printSchedule()) {
-    DEBUG_PRINT(std::cerr << "dumping the prologue block:\n");
-    graph.dump(prologue);
-    DEBUG_PRINT(std::cerr << "dumping the kernel block\n");
-    graph.dump(kernel);
-    DEBUG_PRINT(std::cerr << "dumping the epilogue block\n");
-    graph.dump(epilogue);
-  }
+//    if (0){
+//      DEBUG_PRINT(std::cerr << "dumping the prologue block:\n");
+//      graph.dump(prologue);
+//      DEBUG_PRINT(std::cerr << "dumping the kernel block\n");
+//      graph.dump(kernel);
+//      DEBUG_PRINT(std::cerr << "dumping the epilogue block\n");
+//      graph.dump(epilogue);
+//    }
+
 }
 
 // Clear memory from the last round and initialize if necessary
@@ -526,7 +532,7 @@
         Instruction *ist = (Instruction *) coreSchedule[i][j]->getInst();
         ist->getParent()->getInstList().erase(ist);
       }
-  //**************************************************************//
+
 
 
   //finally, insert an unconditional branch instruction at the end
@@ -900,23 +906,29 @@
     }
 
     // getAnalysisUsage - We use LiveVarInfo...
-        virtual void getAnalysisUsage(AnalysisUsage &AU) const {
+    virtual void getAnalysisUsage(AnalysisUsage &AU) const {
       //AU.addRequired(FunctionLiveVarInfo::ID);
-    } bool runOnFunction(Function & F);
+    }
+    
+    bool runOnFunction(Function & F);
   };
 }                               // end anonymous namespace
 
 
 bool ModuloSchedulingPass::runOnFunction(Function &F)
 {
+
   ModuloSchedGraphSet *graphSet = new ModuloSchedGraphSet(&F, target);
-  ModuloSchedulingSet ModuloSchedulingSet(*graphSet);
 
+  //ModuloSchedulingSet ModuloSchedulingSet(*graphSet);
+  
+  printf("runOnFunction  in ModuloSchedulingPass returns\n");
   return false;
 }
 
 
 Pass *createModuloSchedulingPass(const TargetMachine & tgt)
 {
+  printf("creating modulo scheduling \n");
   return new ModuloSchedulingPass(tgt);
 }


Index: llvm/lib/CodeGen/ModuloScheduling/ModuloScheduling.h
diff -u llvm/lib/CodeGen/ModuloScheduling/ModuloScheduling.h:1.7 llvm/lib/CodeGen/ModuloScheduling/ModuloScheduling.h:1.8
--- llvm/lib/CodeGen/ModuloScheduling/ModuloScheduling.h:1.7	Sun Jun  8 15:40:47 2003
+++ llvm/lib/CodeGen/ModuloScheduling/ModuloScheduling.h	Sun Jun  8 18:16:07 2003
@@ -79,15 +79,15 @@
   printSchedule() { 
 
     //return ModuloScheduling::DebugLevel >= DebugLevel_PrintSchedule; 
-    return false;
-
+    return true;
 
+    
   }
   static bool 
   printScheduleProcess() {
   
     //return DebugLevel >= DebugLevel_PrintScheduleProcess;
-    return false;
+    return true;
 
 
   }
@@ -180,7 +180,7 @@
   ModuloSchedulingSet(ModuloSchedGraphSet _graphSet): graphSet(_graphSet) {
     for (unsigned i = 0; i < graphSet.size(); i++) {
       ModuloSchedGraph & graph = *(graphSet[i]);
-      if (graph.isLoop())
+      if (graph.isLoop(graph.getBasicBlock()))
         ModuloScheduling ModuloScheduling(graph);
     }
   };