From lattner at cs.uiuc.edu Mon Jul 26 00:04:36 2004 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Mon, 26 Jul 2004 00:04:36 -0500 Subject: [llvm-commits] CVS: llvm/test/Regression/CodeGen/CBackend/2004-02-26-FPNotPrintableConstants.llx Message-ID: <200407260504.AAA32151@apoc.cs.uiuc.edu> Changes in directory llvm/test/Regression/CodeGen/CBackend: 2004-02-26-FPNotPrintableConstants.llx updated: 1.2 -> 1.3 --- Log message: Update test --- Diffs of the changes: (+2 -2) Index: llvm/test/Regression/CodeGen/CBackend/2004-02-26-FPNotPrintableConstants.llx diff -u llvm/test/Regression/CodeGen/CBackend/2004-02-26-FPNotPrintableConstants.llx:1.2 llvm/test/Regression/CodeGen/CBackend/2004-02-26-FPNotPrintableConstants.llx:1.3 --- llvm/test/Regression/CodeGen/CBackend/2004-02-26-FPNotPrintableConstants.llx:1.2 Thu Feb 26 16:56:13 2004 +++ llvm/test/Regression/CodeGen/CBackend/2004-02-26-FPNotPrintableConstants.llx Mon Jul 26 00:04:25 2004 @@ -1,7 +1,7 @@ -; This is a non-normal FP value: it's a nan. +; This is a non-normal FP value ; RUN: llvm-as < %s | llc -march=c | grep FPConstant | grep static float %func () { - ret float 0xFF20000000000000 + ret float 0xFFF0000000000000 ; -inf } From lattner at cs.uiuc.edu Mon Jul 26 00:50:19 2004 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Mon, 26 Jul 2004 00:50:19 -0500 Subject: [llvm-commits] CVS: llvm/include/llvm/Analysis/AliasSetTracker.h Message-ID: <200407260550.AAA32741@apoc.cs.uiuc.edu> Changes in directory llvm/include/llvm/Analysis: AliasSetTracker.h updated: 1.17 -> 1.18 --- Log message: New methods --- Diffs of the changes: (+2 -0) Index: llvm/include/llvm/Analysis/AliasSetTracker.h diff -u llvm/include/llvm/Analysis/AliasSetTracker.h:1.17 llvm/include/llvm/Analysis/AliasSetTracker.h:1.18 --- llvm/include/llvm/Analysis/AliasSetTracker.h:1.17 Sun Jul 25 02:57:21 2004 +++ llvm/include/llvm/Analysis/AliasSetTracker.h Mon Jul 26 00:50:09 2004 @@ -262,6 +262,7 @@ /// These methods return true if inserting the instruction resulted in the /// addition of a new alias set (i.e., the pointer did not alias anything). /// + bool add(Value *Ptr, unsigned Size); // Add a location bool add(LoadInst *LI); bool add(StoreInst *SI); bool add(FreeInst *FI); @@ -275,6 +276,7 @@ /// remove methods - These methods are used to remove all entries that might /// be aliased by the specified instruction. These methods return true if any /// alias sets were eliminated. + bool remove(Value *Ptr, unsigned Size); // Remove a location bool remove(LoadInst *LI); bool remove(StoreInst *SI); bool remove(FreeInst *FI); From lattner at cs.uiuc.edu Mon Jul 26 00:50:33 2004 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Mon, 26 Jul 2004 00:50:33 -0500 Subject: [llvm-commits] CVS: llvm/lib/Analysis/AliasSetTracker.cpp Message-ID: <200407260550.AAA32752@apoc.cs.uiuc.edu> Changes in directory llvm/lib/Analysis: AliasSetTracker.cpp updated: 1.22 -> 1.23 --- Log message: Add some new methods --- Diffs of the changes: (+13 -0) Index: llvm/lib/Analysis/AliasSetTracker.cpp diff -u llvm/lib/Analysis/AliasSetTracker.cpp:1.22 llvm/lib/Analysis/AliasSetTracker.cpp:1.23 --- llvm/lib/Analysis/AliasSetTracker.cpp:1.22 Sun Jul 25 13:32:01 2004 +++ llvm/lib/Analysis/AliasSetTracker.cpp Mon Jul 26 00:50:23 2004 @@ -215,6 +215,13 @@ } } +bool AliasSetTracker::add(Value *Ptr, unsigned Size) { + bool NewPtr; + addPointer(Ptr, Size, AliasSet::NoModRef, NewPtr); + return NewPtr; +} + + bool AliasSetTracker::add(LoadInst *LI) { bool NewPtr; AliasSet &AS = addPointer(LI->getOperand(0), @@ -319,6 +326,12 @@ } while (!SetDead); } +bool AliasSetTracker::remove(Value *Ptr, unsigned Size) { + AliasSet *AS = findAliasSetForPointer(Ptr, Size); + if (!AS) return false; + remove(*AS); + return true; +} bool AliasSetTracker::remove(LoadInst *LI) { unsigned Size = AA.getTargetData().getTypeSize(LI->getType()); From lattner at cs.uiuc.edu Mon Jul 26 01:11:53 2004 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Mon, 26 Jul 2004 01:11:53 -0500 Subject: [llvm-commits] CVS: llvm/test/Regression/Transforms/DeadStoreElimination/alloca.llx Message-ID: <200407260611.BAA01187@apoc.cs.uiuc.edu> Changes in directory llvm/test/Regression/Transforms/DeadStoreElimination: alloca.llx added (r1.1) --- Log message: New testcase --- Diffs of the changes: (+8 -0) Index: llvm/test/Regression/Transforms/DeadStoreElimination/alloca.llx diff -c /dev/null llvm/test/Regression/Transforms/DeadStoreElimination/alloca.llx:1.1 *** /dev/null Mon Jul 26 01:11:53 2004 --- llvm/test/Regression/Transforms/DeadStoreElimination/alloca.llx Mon Jul 26 01:11:42 2004 *************** *** 0 **** --- 1,8 ---- + ; RUN: llvm-as < %s | opt -dse | llvm-dis | not grep DEAD + + void %test(int* %Q) { + %P = alloca int + %DEAD = load int* %Q + store int %DEAD, int* %P ;; Alloca goes out of scope, dead store. + ret void + } From lattner at cs.uiuc.edu Mon Jul 26 01:14:21 2004 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Mon, 26 Jul 2004 01:14:21 -0500 Subject: [llvm-commits] CVS: llvm/lib/Transforms/Scalar/DeadStoreElimination.cpp Message-ID: <200407260614.BAA01205@apoc.cs.uiuc.edu> Changes in directory llvm/lib/Transforms/Scalar: DeadStoreElimination.cpp updated: 1.4 -> 1.5 --- Log message: Implement DeadStoreElim/alloca.llx by observing that allocas are dead at the end of the function (either return or unwind) --- Diffs of the changes: (+4 -1) Index: llvm/lib/Transforms/Scalar/DeadStoreElimination.cpp diff -u llvm/lib/Transforms/Scalar/DeadStoreElimination.cpp:1.4 llvm/lib/Transforms/Scalar/DeadStoreElimination.cpp:1.5 --- llvm/lib/Transforms/Scalar/DeadStoreElimination.cpp:1.4 Sun Jul 25 06:09:56 2004 +++ llvm/lib/Transforms/Scalar/DeadStoreElimination.cpp Mon Jul 26 01:14:11 2004 @@ -66,7 +66,10 @@ // If this block ends in a return, unwind, and eventually tailcall/barrier, // then all allocas are dead at its end. if (BB.getTerminator()->getNumSuccessors() == 0) { - + BasicBlock *Entry = BB.getParent()->begin(); + for (BasicBlock::iterator I = Entry->begin(), E = Entry->end(); I != E; ++I) + if (AllocaInst *AI = dyn_cast(I)) + KillLocs.add(AI, ~0); } // PotentiallyDeadInsts - Deleting dead stores from the program can make other From llvm at cs.uiuc.edu Mon Jul 26 10:04:23 2004 From: llvm at cs.uiuc.edu (LLVM) Date: Mon, 26 Jul 2004 10:04:23 -0500 Subject: [llvm-commits] CVS: llvm/test/Regression/CodeGen/CBackend/2004-02-26-FPNotPrintableConstants.llx Message-ID: <200407261504.KAA24755@zion.cs.uiuc.edu> Changes in directory llvm/test/Regression/CodeGen/CBackend: 2004-02-26-FPNotPrintableConstants.llx updated: 1.3 -> 1.4 --- Log message: Added another test case for double FP constants as well. --- Diffs of the changes: (+3 -0) Index: llvm/test/Regression/CodeGen/CBackend/2004-02-26-FPNotPrintableConstants.llx diff -u llvm/test/Regression/CodeGen/CBackend/2004-02-26-FPNotPrintableConstants.llx:1.3 llvm/test/Regression/CodeGen/CBackend/2004-02-26-FPNotPrintableConstants.llx:1.4 --- llvm/test/Regression/CodeGen/CBackend/2004-02-26-FPNotPrintableConstants.llx:1.3 Mon Jul 26 00:04:25 2004 +++ llvm/test/Regression/CodeGen/CBackend/2004-02-26-FPNotPrintableConstants.llx Mon Jul 26 10:04:13 2004 @@ -5,3 +5,6 @@ ret float 0xFFF0000000000000 ; -inf } +double %func2() { + ret double 0xFF20000000000000 ; -inf +} From brukman at cs.uiuc.edu Mon Jul 26 13:43:21 2004 From: brukman at cs.uiuc.edu (Misha Brukman) Date: Mon, 26 Jul 2004 13:43:21 -0500 Subject: [llvm-commits] CVS: llvm/lib/Target/X86/FloatingPoint.cpp InstSelectPattern.cpp InstSelectSimple.cpp PeepholeOptimizer.cpp Printer.cpp Message-ID: <200407261843.NAA26939@zion.cs.uiuc.edu> Changes in directory llvm/lib/Target/X86: FloatingPoint.cpp (r1.38) removed InstSelectPattern.cpp (r1.8) removed InstSelectSimple.cpp (r1.275) removed PeepholeOptimizer.cpp (r1.33) removed Printer.cpp (r1.104) removed --- Log message: Renamed files to have the `X86' prefix for uniqueness purposes. All CVS history was renamed, the *,v were copied over. No worries. --- Diffs of the changes: (+0 -0) From brukman at cs.uiuc.edu Mon Jul 26 13:45:59 2004 From: brukman at cs.uiuc.edu (Misha Brukman) Date: Mon, 26 Jul 2004 13:45:59 -0500 Subject: [llvm-commits] CVS: llvm/lib/Target/X86/X86AsmPrinter.cpp X86FloatingPoint.cpp X86ISelPattern.cpp X86ISelSimple.cpp X86PeepholeOpt.cpp Message-ID: <200407261845.NAA28255@zion.cs.uiuc.edu> Changes in directory llvm/lib/Target/X86: X86AsmPrinter.cpp updated: 1.104 -> 1.105 X86FloatingPoint.cpp updated: 1.38 -> 1.39 X86ISelPattern.cpp updated: 1.8 -> 1.9 X86ISelSimple.cpp updated: 1.275 -> 1.276 X86PeepholeOpt.cpp updated: 1.33 -> 1.34 --- Log message: Fix file header as it has been renamed. --- Diffs of the changes: (+5 -5) Index: llvm/lib/Target/X86/X86AsmPrinter.cpp diff -u llvm/lib/Target/X86/X86AsmPrinter.cpp:1.104 llvm/lib/Target/X86/X86AsmPrinter.cpp:1.105 --- llvm/lib/Target/X86/X86AsmPrinter.cpp:1.104 Sat Jul 17 19:33:38 2004 +++ llvm/lib/Target/X86/X86AsmPrinter.cpp Mon Jul 26 13:45:48 2004 @@ -1,4 +1,4 @@ -//===-- X86/Printer.cpp - Convert X86 LLVM code to Intel assembly ---------===// +//===-- X86AsmPrinter.cpp - Convert X86 LLVM code to Intel assembly -------===// // // The LLVM Compiler Infrastructure // Index: llvm/lib/Target/X86/X86FloatingPoint.cpp diff -u llvm/lib/Target/X86/X86FloatingPoint.cpp:1.38 llvm/lib/Target/X86/X86FloatingPoint.cpp:1.39 --- llvm/lib/Target/X86/X86FloatingPoint.cpp:1.38 Thu Jun 24 19:13:11 2004 +++ llvm/lib/Target/X86/X86FloatingPoint.cpp Mon Jul 26 13:45:48 2004 @@ -1,4 +1,4 @@ -//===-- FloatingPoint.cpp - Floating point Reg -> Stack converter ---------===// +//===-- X86FloatingPoint.cpp - Floating point Reg -> Stack converter ------===// // // The LLVM Compiler Infrastructure // Index: llvm/lib/Target/X86/X86ISelPattern.cpp diff -u llvm/lib/Target/X86/X86ISelPattern.cpp:1.8 llvm/lib/Target/X86/X86ISelPattern.cpp:1.9 --- llvm/lib/Target/X86/X86ISelPattern.cpp:1.8 Sun Jul 4 07:19:56 2004 +++ llvm/lib/Target/X86/X86ISelPattern.cpp Mon Jul 26 13:45:48 2004 @@ -1,4 +1,4 @@ -//===-- InstSelectPattern.cpp - A pattern matching inst selector for X86 --===// +//===-- X86ISelPattern.cpp - A pattern matching inst selector for X86 -----===// // // The LLVM Compiler Infrastructure // Index: llvm/lib/Target/X86/X86ISelSimple.cpp diff -u llvm/lib/Target/X86/X86ISelSimple.cpp:1.275 llvm/lib/Target/X86/X86ISelSimple.cpp:1.276 --- llvm/lib/Target/X86/X86ISelSimple.cpp:1.275 Wed Jul 21 16:28:26 2004 +++ llvm/lib/Target/X86/X86ISelSimple.cpp Mon Jul 26 13:45:48 2004 @@ -1,4 +1,4 @@ -//===-- InstSelectSimple.cpp - A simple instruction selector for x86 ------===// +//===-- X86ISelSimple.cpp - A simple instruction selector for x86 ---------===// // // The LLVM Compiler Infrastructure // Index: llvm/lib/Target/X86/X86PeepholeOpt.cpp diff -u llvm/lib/Target/X86/X86PeepholeOpt.cpp:1.33 llvm/lib/Target/X86/X86PeepholeOpt.cpp:1.34 --- llvm/lib/Target/X86/X86PeepholeOpt.cpp:1.33 Wed Jun 2 00:55:25 2004 +++ llvm/lib/Target/X86/X86PeepholeOpt.cpp Mon Jul 26 13:45:48 2004 @@ -1,4 +1,4 @@ -//===-- PeepholeOptimizer.cpp - X86 Peephole Optimizer --------------------===// +//===-- X86PeepholeOpt.cpp - X86 Peephole Optimizer -----------------------===// // // The LLVM Compiler Infrastructure // From brukman at cs.uiuc.edu Mon Jul 26 13:49:08 2004 From: brukman at cs.uiuc.edu (Misha Brukman) Date: Mon, 26 Jul 2004 13:49:08 -0500 Subject: [llvm-commits] CVS: llvm/lib/Target/X86/X86AsmPrinter.cpp Message-ID: <200407261849.NAA28291@zion.cs.uiuc.edu> Changes in directory llvm/lib/Target/X86: X86AsmPrinter.cpp updated: 1.105 -> 1.106 --- Log message: Fix indentation: should be 2 spaces. --- Diffs of the changes: (+25 -25) Index: llvm/lib/Target/X86/X86AsmPrinter.cpp diff -u llvm/lib/Target/X86/X86AsmPrinter.cpp:1.105 llvm/lib/Target/X86/X86AsmPrinter.cpp:1.106 --- llvm/lib/Target/X86/X86AsmPrinter.cpp:1.105 Mon Jul 26 13:45:48 2004 +++ llvm/lib/Target/X86/X86AsmPrinter.cpp Mon Jul 26 13:48:58 2004 @@ -41,34 +41,34 @@ cl::desc("Emit X86 assembly code suitable for consumption by cygwin")); struct GasBugWorkaroundEmitter : public MachineCodeEmitter { - GasBugWorkaroundEmitter(std::ostream& o) - : O(o), OldFlags(O.flags()), firstByte(true) { - O << std::hex; - } + GasBugWorkaroundEmitter(std::ostream& o) + : O(o), OldFlags(O.flags()), firstByte(true) { + O << std::hex; + } - ~GasBugWorkaroundEmitter() { - O.flags(OldFlags); - O << "\t# "; - } + ~GasBugWorkaroundEmitter() { + O.flags(OldFlags); + O << "\t# "; + } - virtual void emitByte(unsigned char B) { - if (!firstByte) O << "\n\t"; - firstByte = false; - O << ".byte 0x" << (unsigned) B; - } + virtual void emitByte(unsigned char B) { + if (!firstByte) O << "\n\t"; + firstByte = false; + O << ".byte 0x" << (unsigned) B; + } - // These should never be called - virtual void emitWord(unsigned W) { assert(0); } - virtual uint64_t getGlobalValueAddress(GlobalValue *V) { abort(); } - virtual uint64_t getGlobalValueAddress(const std::string &Name) { abort(); } - virtual uint64_t getConstantPoolEntryAddress(unsigned Index) { abort(); } - virtual uint64_t getCurrentPCValue() { abort(); } - virtual uint64_t forceCompilationOf(Function *F) { abort(); } + // These should never be called + virtual void emitWord(unsigned W) { assert(0); } + virtual uint64_t getGlobalValueAddress(GlobalValue *V) { abort(); } + virtual uint64_t getGlobalValueAddress(const std::string &Name) { abort(); } + virtual uint64_t getConstantPoolEntryAddress(unsigned Index) { abort(); } + virtual uint64_t getCurrentPCValue() { abort(); } + virtual uint64_t forceCompilationOf(Function *F) { abort(); } private: - std::ostream& O; - std::ios::fmtflags OldFlags; - bool firstByte; + std::ostream& O; + std::ios::fmtflags OldFlags; + bool firstByte; }; struct Printer : public MachineFunctionPass { @@ -920,8 +920,8 @@ MI->getOpcode() == X86::FLD80m || MI->getOpcode() == X86::FILD64m || MI->getOpcode() == X86::FISTP64m) { - GasBugWorkaroundEmitter gwe(O); - X86::emitInstruction(gwe, (X86InstrInfo&)*TM.getInstrInfo(), *MI); + GasBugWorkaroundEmitter gwe(O); + X86::emitInstruction(gwe, (X86InstrInfo&)*TM.getInstrInfo(), *MI); } O << TII.getName(MI->getOpcode()) << " "; From lattner at cs.uiuc.edu Mon Jul 26 16:17:06 2004 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Mon, 26 Jul 2004 16:17:06 -0500 Subject: [llvm-commits] CVS: llvm/docs/TableGenFundamentals.html Message-ID: <200407262117.QAA03327@apoc.cs.uiuc.edu> Changes in directory llvm/docs: TableGenFundamentals.html updated: 1.8 -> 1.9 --- Log message: Remove dead section --- Diffs of the changes: (+2 -18) Index: llvm/docs/TableGenFundamentals.html diff -u llvm/docs/TableGenFundamentals.html:1.8 llvm/docs/TableGenFundamentals.html:1.9 --- llvm/docs/TableGenFundamentals.html:1.8 Thu Jun 3 18:41:48 2004 +++ llvm/docs/TableGenFundamentals.html Mon Jul 26 16:16:55 2004 @@ -41,10 +41,6 @@
  1. todo
-
  • The LLVM code generator -
      -
    1. todo
      2. -
    • @@ -68,7 +64,7 @@

    The core part of TableGen parses a file, instantiates the declarations, and hands the result off to a domain-specific "TableGen backend" for processing. The current major user -of TableGen is the LLVM code generator.

    +of TableGen is the LLVM code generator.

    Note that if you work on TableGen much, and use emacs or vim, that you can find an emacs "TableGen mode" and a vim language file in @@ -551,18 +547,6 @@ -

    The LLVM code generator -
    - - -
    -

    This is just a temporary, convenient, place to put stuff about the code -generator before it gets its own document. This should describe all of the -tablegen backends used by the code generator and the classes/definitions they -expect.

    -
    - -
    @@ -573,7 +557,7 @@ Chris Lattner
    LLVM Compiler Infrastructure
    - Last modified: $Date: 2004/06/03 23:41:48 $ + Last modified: $Date: 2004/07/26 21:16:55 $
    From llvm at cs.uiuc.edu Mon Jul 26 17:52:55 2004 From: llvm at cs.uiuc.edu (LLVM) Date: Mon, 26 Jul 2004 17:52:55 -0500 Subject: [llvm-commits] CVS: llvm/utils/llvmdo Message-ID: <200407262252.RAA04428@zion.cs.uiuc.edu> Changes in directory llvm/utils: llvmdo added (r1.1) --- Log message: A utility to run an arbitrary program on each of the LLVM source files. This is like llvmgrep but instead of running grep, it runs the command given by the first argument. For example, to find the top ten files with the most lines in llvm, you could: utils/llvmdo wc -l | sort -nb | tail Or, to find any source files with the wrong permissions, you could: utils/llvmdo ls -l | grep -v rw-r--r-- Hopefully, you get the idea. --- Diffs of the changes: (+31 -0) Index: llvm/utils/llvmdo diff -c /dev/null llvm/utils/llvmdo:1.1 *** /dev/null Mon Jul 26 17:52:54 2004 --- llvm/utils/llvmdo Mon Jul 26 17:52:44 2004 *************** *** 0 **** --- 1,31 ---- + #!/bin/sh + # This is useful because it prints out all of the source files. Useful for + # greps. + PROGRAM=`which $1` + if [ ! -x "$PROGRAM" ]; then + echo "Can't execute $1" + exit 1 + fi + shift; + ARGS="$*" + TOPDIR=`pwd | sed -e 's#(.*/llvm).*#$1#'` + if test -d "$TOPDIR" ; then + cd $TOPDIR + echo $TOPDIR + find docs include lib tools utils projects -type f \ + \( -path '*/doxygen/*' -o -path '*/Burg/*' \) -prune -o \ + -name '*.[cdhyl]*' \ + \! -name '*~' \ + \! -name '#*' \ + \! -name '*.ll' \ + \! -name '*.d' \ + \! -name '*.dir' \ + \! -name 'Sparc.burm.c' \ + \! -name 'llvmAsmParser.cpp' \ + \! -name 'llvmAsmParser.h' \ + \! -name 'FileParser.cpp' \ + \! -name 'FileParser.h' \ + -exec $PROGRAM $ARGS {} \; + else + echo "Can't find LLVM top directory in $TOPDIR" + fi From lattner at cs.uiuc.edu Mon Jul 26 18:21:44 2004 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Mon, 26 Jul 2004 18:21:44 -0500 Subject: [llvm-commits] CVS: llvm/utils/TableGen/FileParser.y Record.cpp Record.h Message-ID: <200407262321.SAA10512@apoc.cs.uiuc.edu> Changes in directory llvm/utils/TableGen: FileParser.y updated: 1.29 -> 1.30 Record.cpp updated: 1.32 -> 1.33 Record.h updated: 1.39 -> 1.40 --- Log message: Add initial support for list slices. This currently allows you to do stuff like this: def B { list X = [10, 20, 30, 4, 1, 1231, 20] [2-4,2,2,0-6]; } ... which isn't particularly useful, but more is to come. --- Diffs of the changes: (+65 -16) Index: llvm/utils/TableGen/FileParser.y diff -u llvm/utils/TableGen/FileParser.y:1.29 llvm/utils/TableGen/FileParser.y:1.30 --- llvm/utils/TableGen/FileParser.y:1.29 Sat Feb 28 11:41:48 2004 +++ llvm/utils/TableGen/FileParser.y Mon Jul 26 18:21:34 2004 @@ -300,6 +300,14 @@ } $$ = new DagInit(D, *$3); delete $2; delete $3; + } | Value '[' BitList ']' { + std::reverse($3->begin(), $3->end()); + $$ = $1->convertInitListSlice(*$3); + if ($$ == 0) { + err() << "Invalid list slice for value '" << *$1 << "'!\n"; + exit(1); + } + delete $3; }; OptVarName : /* empty */ { @@ -330,41 +338,61 @@ $$ = new std::vector(); $$->push_back($1); } | INTVAL '-' INTVAL { - if ($1 < $3 || $1 < 0 || $3 < 0) { - err() << "Invalid bit range: " << $1 << "-" << $3 << "!\n"; + if ($1 < 0 || $3 < 0) { + err() << "Invalid range: " << $1 << "-" << $3 << "!\n"; exit(1); } $$ = new std::vector(); - for (int i = $1; i >= $3; --i) - $$->push_back(i); + if ($1 < $3) { + for (int i = $1; i <= $3; ++i) + $$->push_back(i); + } else { + for (int i = $1; i >= $3; --i) + $$->push_back(i); + } } | INTVAL INTVAL { $2 = -$2; - if ($1 < $2 || $1 < 0 || $2 < 0) { - err() << "Invalid bit range: " << $1 << "-" << $2 << "!\n"; + if ($1 < 0 || $2 < 0) { + err() << "Invalid range: " << $1 << "-" << $2 << "!\n"; exit(1); } $$ = new std::vector(); - for (int i = $1; i >= $2; --i) - $$->push_back(i); + if ($1 < $2) { + for (int i = $1; i <= $2; ++i) + $$->push_back(i); + } else { + for (int i = $1; i >= $2; --i) + $$->push_back(i); + } } | RBitList ',' INTVAL { ($$=$1)->push_back($3); } | RBitList ',' INTVAL '-' INTVAL { - if ($3 < $5 || $3 < 0 || $5 < 0) { - err() << "Invalid bit range: " << $3 << "-" << $5 << "!\n"; + if ($3 < 0 || $5 < 0) { + err() << "Invalid range: " << $3 << "-" << $5 << "!\n"; exit(1); } $$ = $1; - for (int i = $3; i >= $5; --i) - $$->push_back(i); + if ($3 < $5) { + for (int i = $3; i <= $5; ++i) + $$->push_back(i); + } else { + for (int i = $3; i >= $5; --i) + $$->push_back(i); + } } | RBitList ',' INTVAL INTVAL { $4 = -$4; - if ($3 < $4 || $3 < 0 || $4 < 0) { - err() << "Invalid bit range: " << $3 << "-" << $4 << "!\n"; + if ($3 < 0 || $4 < 0) { + err() << "Invalid range: " << $3 << "-" << $4 << "!\n"; exit(1); } $$ = $1; - for (int i = $3; i >= $4; --i) - $$->push_back(i); + if ($3 < $4) { + for (int i = $3; i <= $4; ++i) + $$->push_back(i); + } else { + for (int i = $3; i >= $4; --i) + $$->push_back(i); + } }; BitList : RBitList { $$ = $1; std::reverse($1->begin(), $1->end()); }; Index: llvm/utils/TableGen/Record.cpp diff -u llvm/utils/TableGen/Record.cpp:1.32 llvm/utils/TableGen/Record.cpp:1.33 --- llvm/utils/TableGen/Record.cpp:1.32 Mon Jun 21 13:01:47 2004 +++ llvm/utils/TableGen/Record.cpp Mon Jul 26 18:21:34 2004 @@ -310,6 +310,16 @@ return BI; } +Init *ListInit::convertInitListSlice(const std::vector &Elements) { + std::vector Vals; + for (unsigned i = 0, e = Elements.size(); i != e; ++i) { + if (Elements[i] >= getSize()) + return 0; + Vals.push_back(getElement(Elements[i])); + } + return new ListInit(Vals); +} + void ListInit::print(std::ostream &OS) const { OS << "["; for (unsigned i = 0, e = Values.size(); i != e; ++i) { Index: llvm/utils/TableGen/Record.h diff -u llvm/utils/TableGen/Record.h:1.39 llvm/utils/TableGen/Record.h:1.40 --- llvm/utils/TableGen/Record.h:1.39 Thu Apr 15 10:30:15 2004 +++ llvm/utils/TableGen/Record.h Mon Jul 26 18:21:34 2004 @@ -304,6 +304,15 @@ return 0; } + /// convertInitListSlice - This method is used to implement the list slice + /// selection operator. Given an initializer, it selects the specified list + /// elements, returning them as a new init of list type. If it is not legal + /// to take a slice of this, return null. + /// + virtual Init *convertInitListSlice(const std::vector &Elements) { + return 0; + } + /// getFieldType - This method is used to implement the FieldInit class. /// Implementors of this method should return the type of the named field if /// they are of record type. @@ -466,6 +475,8 @@ return Values[i]; } + Init *convertInitListSlice(const std::vector &Elements); + virtual Init *convertInitializerTo(RecTy *Ty) { return Ty->convertValue(this); } From lattner at cs.uiuc.edu Mon Jul 26 20:01:07 2004 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Mon, 26 Jul 2004 20:01:07 -0500 Subject: [llvm-commits] CVS: llvm/test/Regression/TableGen/ListSlices.td Message-ID: <200407270101.UAA23345@apoc.cs.uiuc.edu> Changes in directory llvm/test/Regression/TableGen: ListSlices.td added (r1.1) --- Log message: New testcase for list slicing --- Diffs of the changes: (+18 -0) Index: llvm/test/Regression/TableGen/ListSlices.td diff -c /dev/null llvm/test/Regression/TableGen/ListSlices.td:1.1 *** /dev/null Mon Jul 26 20:01:06 2004 --- llvm/test/Regression/TableGen/ListSlices.td Mon Jul 26 20:00:56 2004 *************** *** 0 **** --- 1,18 ---- + // RUN: tblgen %s + + def A { + list B = [10, 20, 30, 4, 1, 1231, 20]; + } + + def B { + list X = [10, 20, 30, 4, 1, 1231, 20] [2-4,2,2,0-6]; + + list Y = X[4,5]; + int Z = X[4]; + + list C = A.B[1-4]; + + list> AA = [X, Y]; + + int BB = AA[0][1]; + } From lattner at cs.uiuc.edu Mon Jul 26 20:01:31 2004 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Mon, 26 Jul 2004 20:01:31 -0500 Subject: [llvm-commits] CVS: llvm/utils/TableGen/Record.cpp Record.h Message-ID: <200407270101.UAA23358@apoc.cs.uiuc.edu> Changes in directory llvm/utils/TableGen: Record.cpp updated: 1.33 -> 1.34 Record.h updated: 1.40 -> 1.41 --- Log message: Implement test/Regression/TableGen/ListSlices.td --- Diffs of the changes: (+142 -29) Index: llvm/utils/TableGen/Record.cpp diff -u llvm/utils/TableGen/Record.cpp:1.33 llvm/utils/TableGen/Record.cpp:1.34 --- llvm/utils/TableGen/Record.cpp:1.33 Mon Jul 26 18:21:34 2004 +++ llvm/utils/TableGen/Record.cpp Mon Jul 26 20:01:21 2004 @@ -320,6 +320,28 @@ return new ListInit(Vals); } +Init *ListInit::resolveReferences(Record &R) { + std::vector Resolved; + Resolved.reserve(getSize()); + bool Changed = false; + + for (unsigned i = 0, e = getSize(); i != e; ++i) { + Init *E; + Init *CurElt = getElement(i); + + do { + E = CurElt; + CurElt = CurElt->resolveReferences(R); + Changed |= E != CurElt; + } while (E != CurElt); + Resolved.push_back(E); + } + + if (Changed) + return new ListInit(Resolved); + return this; +} + void ListInit::print(std::ostream &OS) const { OS << "["; for (unsigned i = 0, e = Values.size(); i != e; ++i) { @@ -329,7 +351,7 @@ OS << "]"; } -Init *VarInit::convertInitializerBitRange(const std::vector &Bits) { +Init *TypedInit::convertInitializerBitRange(const std::vector &Bits) { BitsRecTy *T = dynamic_cast(getType()); if (T == 0) return 0; // Cannot subscript a non-bits variable... unsigned NumBits = T->getNumBits(); @@ -345,9 +367,24 @@ return BI; } +Init *TypedInit::convertInitListSlice(const std::vector &Elements) { + ListRecTy *T = dynamic_cast(getType()); + if (T == 0) return 0; // Cannot subscript a non-list variable... + + if (Elements.size() == 1) + return new VarListElementInit(this, Elements[0]); + + std::vector ListInits; + ListInits.reserve(Elements.size()); + for (unsigned i = 0, e = Elements.size(); i != e; ++i) + ListInits.push_back(new VarListElementInit(this, Elements[i])); + return new ListInit(ListInits); +} + + Init *VarInit::resolveBitReference(Record &R, unsigned Bit) { if (R.isTemplateArg(getName())) - return this; + return 0; RecordVal *RV = R.getValue(getName()); assert(RV && "Reference to a non-existant variable?"); @@ -359,9 +396,27 @@ if (!dynamic_cast(B)) // If the bit is not set... return B; // Replace the VarBitInit with it. - return this; + return 0; +} + +Init *VarInit::resolveListElementReference(Record &R, unsigned Elt) { + if (R.isTemplateArg(getName())) + return 0; + + RecordVal *RV = R.getValue(getName()); + assert(RV && "Reference to a non-existant variable?"); + ListInit *LI = dynamic_cast(RV->getValue()); + assert(LI && "Invalid list element!"); + + if (Elt >= LI->getSize()) + return 0; // Out of range reference. + Init *E = LI->getElement(Elt); + if (!dynamic_cast(E)) // If the element is set + return E; // Replace the VarListElementInit with it. + return 0; } + RecTy *VarInit::getFieldType(const std::string &FieldName) const { if (RecordRecTy *RTy = dynamic_cast(getType())) if (const RecordVal *RV = RTy->getRecord()->getValue(FieldName)) @@ -396,12 +451,29 @@ Init *VarBitInit::resolveReferences(Record &R) { - Init *I = getVariable()->resolveBitReference(R, getBitNum()); - if (I != getVariable()) + if (Init *I = getVariable()->resolveBitReference(R, getBitNum())) return I; return this; } +Init *VarListElementInit::resolveReferences(Record &R) { + if (Init *I = getVariable()->resolveListElementReference(R, getElementNum())) + return I; + return this; +} + +Init *VarListElementInit::resolveBitReference(Record &R, unsigned Bit) { + // FIXME: This should be implemented, to support references like: + // bit B = AA[0]{1}; + return 0; +} + +Init *VarListElementInit::resolveListElementReference(Record &R, unsigned Elt) { + // FIXME: This should be implemented, to support references like: + // int B = AA[0][1]; + return 0; +} + RecTy *DefInit::getFieldType(const std::string &FieldName) const { if (const RecordVal *RV = Def->getValue(FieldName)) return RV->getType(); @@ -417,25 +489,8 @@ OS << Def->getName(); } -Init *FieldInit::convertInitializerBitRange(const std::vector &Bits) { - BitsRecTy *T = dynamic_cast(getType()); - if (T == 0) return 0; // Cannot subscript a non-bits field... - unsigned NumBits = T->getNumBits(); - - BitsInit *BI = new BitsInit(Bits.size()); - for (unsigned i = 0, e = Bits.size(); i != e; ++i) { - if (Bits[i] >= NumBits) { - delete BI; - return 0; - } - BI->setBit(i, new VarBitInit(this, Bits[i])); - } - return BI; -} - Init *FieldInit::resolveBitReference(Record &R, unsigned Bit) { - Init *BitsVal = Rec->getFieldInit(R, FieldName); - if (BitsVal) + if (Init *BitsVal = Rec->getFieldInit(R, FieldName)) if (BitsInit *BI = dynamic_cast(BitsVal)) { assert(Bit < BI->getNumBits() && "Bit reference out of range!"); Init *B = BI->getBit(Bit); @@ -443,7 +498,19 @@ if (dynamic_cast(B)) // If the bit is set... return B; // Replace the VarBitInit with it. } - return this; + return 0; +} + +Init *FieldInit::resolveListElementReference(Record &R, unsigned Elt) { + if (Init *ListVal = Rec->getFieldInit(R, FieldName)) + if (ListInit *LI = dynamic_cast(ListVal)) { + if (Elt >= LI->getSize()) return 0; + Init *E = LI->getElement(Elt); + + if (!dynamic_cast(E)) // If the bit is set... + return E; // Replace the VarListElementInit with it. + } + return 0; } Init *FieldInit::resolveReferences(Record &R) { Index: llvm/utils/TableGen/Record.h diff -u llvm/utils/TableGen/Record.h:1.40 llvm/utils/TableGen/Record.h:1.41 --- llvm/utils/TableGen/Record.h:1.40 Mon Jul 26 18:21:34 2004 +++ llvm/utils/TableGen/Record.h Mon Jul 26 20:01:21 2004 @@ -48,6 +48,7 @@ class VarInit; class FieldInit; class VarBitInit; +class VarListElementInit; // Other classes... class Record; @@ -481,6 +482,13 @@ return Ty->convertValue(this); } + /// resolveReferences - This method is used by classes that refer to other + /// variables which may not be defined at the time they expression is formed. + /// If a value is set for the variable later, this method will be called on + /// users of the value to allow the value to propagate out. + /// + virtual Init *resolveReferences(Record &R); + virtual void print(std::ostream &OS) const; }; @@ -495,11 +503,19 @@ RecTy *getType() const { return Ty; } + virtual Init *convertInitializerBitRange(const std::vector &Bits); + virtual Init *convertInitListSlice(const std::vector &Elements); + /// resolveBitReference - This method is used to implement /// VarBitInit::resolveReferences. If the bit is able to be resolved, we - /// simply return the resolved value, otherwise we return this. + /// simply return the resolved value, otherwise we return null. /// virtual Init *resolveBitReference(Record &R, unsigned Bit) = 0; + + /// resolveListElementReference - This method is used to implement + /// VarListElementInit::resolveReferences. If the list element is resolvable + /// now, we return the resolved value, otherwise we return null. + virtual Init *resolveListElementReference(Record &R, unsigned Elt) = 0; }; /// VarInit - 'Opcode' - Represent a reference to an entire variable object. @@ -515,9 +531,8 @@ const std::string &getName() const { return VarName; } - virtual Init *convertInitializerBitRange(const std::vector &Bits); - virtual Init *resolveBitReference(Record &R, unsigned Bit); + virtual Init *resolveListElementReference(Record &R, unsigned Elt); virtual RecTy *getFieldType(const std::string &FieldName) const; virtual Init *getFieldInit(Record &R, const std::string &FieldName) const; @@ -558,6 +573,38 @@ virtual Init *resolveReferences(Record &R); }; +/// VarListElementInit - List[4] - Represent access to one element of a var or +/// field. +class VarListElementInit : public TypedInit { + TypedInit *TI; + unsigned Element; +public: + VarListElementInit(TypedInit *T, unsigned E) + : TypedInit(dynamic_cast(T->getType())->getElementType()), + TI(T), Element(E) { + assert(T->getType() && dynamic_cast(T->getType()) && + "Illegal VarBitInit expression!"); + } + + virtual Init *convertInitializerTo(RecTy *Ty) { + return Ty->convertValue(this); + } + + TypedInit *getVariable() const { return TI; } + unsigned getElementNum() const { return Element; } + + virtual Init *resolveBitReference(Record &R, unsigned Bit); + + /// resolveListElementReference - This method is used to implement + /// VarListElementInit::resolveReferences. If the list element is resolvable + /// now, we return the resolved value, otherwise we return null. + virtual Init *resolveListElementReference(Record &R, unsigned Elt); + + virtual void print(std::ostream &OS) const { + TI->print(OS); OS << "[" << Element << "]"; + } + virtual Init *resolveReferences(Record &R); +}; /// DefInit - AL - Represent a reference to a 'def' in the description /// @@ -596,9 +643,8 @@ return Ty->convertValue(this); } - virtual Init *convertInitializerBitRange(const std::vector &Bits); - virtual Init *resolveBitReference(Record &R, unsigned Bit); + virtual Init *resolveListElementReference(Record &R, unsigned Elt); virtual Init *resolveReferences(Record &R); From lattner at cs.uiuc.edu Mon Jul 26 20:59:53 2004 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Mon, 26 Jul 2004 20:59:53 -0500 Subject: [llvm-commits] CVS: llvm/lib/Analysis/BasicAliasAnalysis.cpp Message-ID: <200407270159.UAA23577@apoc.cs.uiuc.edu> Changes in directory llvm/lib/Analysis: BasicAliasAnalysis.cpp updated: 1.47 -> 1.48 --- Log message: This was implemented back in march --- Diffs of the changes: (+0 -7) Index: llvm/lib/Analysis/BasicAliasAnalysis.cpp diff -u llvm/lib/Analysis/BasicAliasAnalysis.cpp:1.47 llvm/lib/Analysis/BasicAliasAnalysis.cpp:1.48 --- llvm/lib/Analysis/BasicAliasAnalysis.cpp:1.47 Tue Jul 20 22:56:54 2004 +++ llvm/lib/Analysis/BasicAliasAnalysis.cpp Mon Jul 26 20:59:42 2004 @@ -11,13 +11,6 @@ // that simply implements a few identities (two different globals cannot alias, // etc), but otherwise does no analysis. // -// FIXME: This could be extended for a very simple form of mod/ref information. -// If a pointer is locally allocated (either malloc or alloca) and never passed -// into a call or stored to memory, then we know that calls will not mod/ref the -// memory. This can be important for tailcallelim, and can support CSE of loads -// and dead store elimination across calls. This is particularly important for -// stack allocated arrays. -// //===----------------------------------------------------------------------===// #include "llvm/Analysis/AliasAnalysis.h" From lattner at cs.uiuc.edu Mon Jul 26 21:14:06 2004 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Mon, 26 Jul 2004 21:14:06 -0500 Subject: [llvm-commits] CVS: llvm/lib/Analysis/BasicAliasAnalysis.cpp Message-ID: <200407270214.VAA26066@apoc.cs.uiuc.edu> Changes in directory llvm/lib/Analysis: BasicAliasAnalysis.cpp updated: 1.48 -> 1.49 --- Log message: basic-aa can actually provide simple mod/ref info --- Diffs of the changes: (+3 -3) Index: llvm/lib/Analysis/BasicAliasAnalysis.cpp diff -u llvm/lib/Analysis/BasicAliasAnalysis.cpp:1.48 llvm/lib/Analysis/BasicAliasAnalysis.cpp:1.49 --- llvm/lib/Analysis/BasicAliasAnalysis.cpp:1.48 Mon Jul 26 20:59:42 2004 +++ llvm/lib/Analysis/BasicAliasAnalysis.cpp Mon Jul 26 21:13:55 2004 @@ -83,9 +83,9 @@ ModRefResult getModRefInfo(CallSite CS, Value *P, unsigned Size); - /// hasNoModRefInfoForCalls - We have no way to test one call against - /// another, unless they are pure or const. - virtual bool hasNoModRefInfoForCalls() const { return true; } + /// hasNoModRefInfoForCalls - We can provide mod/ref information against + /// non-escaping allocations. + virtual bool hasNoModRefInfoForCalls() const { return false; } /// pointsToConstantMemory - Chase pointers until we find a (constant /// global) or not. From lattner at cs.uiuc.edu Mon Jul 26 21:19:02 2004 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Mon, 26 Jul 2004 21:19:02 -0500 Subject: [llvm-commits] CVS: llvm/lib/Analysis/BasicAliasAnalysis.cpp Message-ID: <200407270219.VAA27108@apoc.cs.uiuc.edu> Changes in directory llvm/lib/Analysis: BasicAliasAnalysis.cpp updated: 1.49 -> 1.50 --- Log message: Make basicaa a bit more aggressive --- Diffs of the changes: (+4 -0) Index: llvm/lib/Analysis/BasicAliasAnalysis.cpp diff -u llvm/lib/Analysis/BasicAliasAnalysis.cpp:1.49 llvm/lib/Analysis/BasicAliasAnalysis.cpp:1.50 --- llvm/lib/Analysis/BasicAliasAnalysis.cpp:1.49 Mon Jul 26 21:13:55 2004 +++ llvm/lib/Analysis/BasicAliasAnalysis.cpp Mon Jul 26 21:18:52 2004 @@ -196,6 +196,10 @@ return true; if (AddressMightEscape(I)) return true; break; + case Instruction::Ret: + // If returned, the address will escape to calling functions, but no + // callees could modify it. + break; default: return true; } From lattner at cs.uiuc.edu Mon Jul 26 21:19:37 2004 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Mon, 26 Jul 2004 21:19:37 -0500 Subject: [llvm-commits] CVS: llvm/test/Regression/Transforms/DeadStoreElimination/context-sensitive.llx Message-ID: <200407270219.VAA27132@apoc.cs.uiuc.edu> Changes in directory llvm/test/Regression/Transforms/DeadStoreElimination: context-sensitive.llx added (r1.1) --- Log message: New testcase. DSE should delete all of the DEAD instructions. --- Diffs of the changes: (+15 -0) Index: llvm/test/Regression/Transforms/DeadStoreElimination/context-sensitive.llx diff -c /dev/null llvm/test/Regression/Transforms/DeadStoreElimination/context-sensitive.llx:1.1 *** /dev/null Mon Jul 26 21:19:37 2004 --- llvm/test/Regression/Transforms/DeadStoreElimination/context-sensitive.llx Mon Jul 26 21:19:27 2004 *************** *** 0 **** --- 1,15 ---- + ; RUN: llvm-as < %s | opt -dse | llvm-dis | not grep DEAD + + declare void %ext() + + int* %caller() { + %P = malloc int + %DEAD = load int* %P + %DEAD2 = add int %DEAD, 1 + store int %DEAD2, int* %P ;; dead store + + call void %ext() ; Can not clobber *P + + store int 0, int* %P + ret int* %P + } From lattner at cs.uiuc.edu Mon Jul 26 21:20:36 2004 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Mon, 26 Jul 2004 21:20:36 -0500 Subject: [llvm-commits] CVS: llvm/lib/Analysis/AliasSetTracker.cpp Message-ID: <200407270220.VAA27144@apoc.cs.uiuc.edu> Changes in directory llvm/lib/Analysis: AliasSetTracker.cpp updated: 1.23 -> 1.24 --- Log message: Use context-sensitive alias analysis to avoid pessimization in clients of AliasSetTracker (dse and licm). This implements DeadStoreElimination/context-sensitive.llx --- Diffs of the changes: (+23 -5) Index: llvm/lib/Analysis/AliasSetTracker.cpp diff -u llvm/lib/Analysis/AliasSetTracker.cpp:1.23 llvm/lib/Analysis/AliasSetTracker.cpp:1.24 --- llvm/lib/Analysis/AliasSetTracker.cpp:1.23 Mon Jul 26 00:50:23 2004 +++ llvm/lib/Analysis/AliasSetTracker.cpp Mon Jul 26 21:20:26 2004 @@ -138,20 +138,38 @@ return true; // Check the call sites list and invoke list... - if (!CallSites.empty()) - // FIXME: this is pessimistic! - return true; + if (!CallSites.empty()) { + if (AA.hasNoModRefInfoForCalls()) + return true; + + for (unsigned i = 0, e = CallSites.size(); i != e; ++i) + if (AA.getModRefInfo(CallSites[i], const_cast(Ptr), Size) + != AliasAnalysis::NoModRef) + return true; + } return false; } bool AliasSet::aliasesCallSite(CallSite CS, AliasAnalysis &AA) const { - // FIXME: Use mod/ref information to prune this better! if (Function *F = CS.getCalledFunction()) if (AA.doesNotAccessMemory(F)) return false; - return true; + if (AA.hasNoModRefInfoForCalls()) + return true; + + for (unsigned i = 0, e = CallSites.size(); i != e; ++i) + if (AA.getModRefInfo(CallSites[i], CS) != AliasAnalysis::NoModRef || + AA.getModRefInfo(CS, CallSites[i]) != AliasAnalysis::NoModRef) + return true; + + for (iterator I = begin(), E = end(); I != E; ++I) + if (AA.getModRefInfo(CS, I.getPointer(), I.getSize()) != + AliasAnalysis::NoModRef) + return true; + + return false; } From lattner at cs.uiuc.edu Mon Jul 26 21:34:59 2004 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Mon, 26 Jul 2004 21:34:59 -0500 Subject: [llvm-commits] CVS: llvm/lib/Bytecode/Reader/Reader.cpp Message-ID: <200407270234.VAA27335@apoc.cs.uiuc.edu> Changes in directory llvm/lib/Bytecode/Reader: Reader.cpp updated: 1.119 -> 1.120 --- Log message: Simplify code and silence warning --- Diffs of the changes: (+4 -6) Index: llvm/lib/Bytecode/Reader/Reader.cpp diff -u llvm/lib/Bytecode/Reader/Reader.cpp:1.119 llvm/lib/Bytecode/Reader/Reader.cpp:1.120 --- llvm/lib/Bytecode/Reader/Reader.cpp:1.119 Sun Jul 25 18:15:44 2004 +++ llvm/lib/Bytecode/Reader/Reader.cpp Mon Jul 26 21:34:49 2004 @@ -1401,16 +1401,14 @@ // Check to see if we have already read this global variable... Value *Val = getValue(TypeID, Slot, false); - GlobalValue *GV; if (Val) { - if (!(GV = dyn_cast(Val))) - error("GlobalValue not in ValueTable!"); + GlobalValue *GV = dyn_cast(Val); + if (!GV) error("GlobalValue not in ValueTable!"); + if (Handler) Handler->handleConstantPointer(PT, Slot, GV); + return GV; } else { error("Forward references are not allowed here."); } - - if (Handler) Handler->handleConstantPointer(PT, Slot, GV ); - return GV; } default: From lattner at cs.uiuc.edu Mon Jul 26 22:04:40 2004 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Mon, 26 Jul 2004 22:04:40 -0500 Subject: [llvm-commits] CVS: llvm/include/llvm/Target/MRegisterInfo.h Message-ID: <200407270304.WAA27708@apoc.cs.uiuc.edu> Changes in directory llvm/include/llvm/Target: MRegisterInfo.h updated: 1.43 -> 1.44 --- Log message: Fix out of date comment --- Diffs of the changes: (+1 -2) Index: llvm/include/llvm/Target/MRegisterInfo.h diff -u llvm/include/llvm/Target/MRegisterInfo.h:1.43 llvm/include/llvm/Target/MRegisterInfo.h:1.44 --- llvm/include/llvm/Target/MRegisterInfo.h:1.43 Fri Jun 11 11:50:21 2004 +++ llvm/include/llvm/Target/MRegisterInfo.h Mon Jul 26 22:04:30 2004 @@ -280,8 +280,7 @@ /// instructions (but only if the Target is using them). It is responsible /// for eliminating these instructions, replacing them with concrete /// instructions. This method need only be implemented if using call frame - /// setup/destroy pseudo instructions. The return value is the number of - /// instructions added to (negative if removed from) the basic block. + /// setup/destroy pseudo instructions. /// virtual void eliminateCallFramePseudoInstr(MachineFunction &MF, From lattner at cs.uiuc.edu Mon Jul 26 23:01:04 2004 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Mon, 26 Jul 2004 23:01:04 -0500 Subject: [llvm-commits] CVS: llvm/include/llvm/Target/TargetSchedInfo.h Message-ID: <200407270401.XAA31466@apoc.cs.uiuc.edu> Changes in directory llvm/include/llvm/Target: TargetSchedInfo.h updated: 1.27 -> 1.28 --- Log message: Add a note --- Diffs of the changes: (+2 -0) Index: llvm/include/llvm/Target/TargetSchedInfo.h diff -u llvm/include/llvm/Target/TargetSchedInfo.h:1.27 llvm/include/llvm/Target/TargetSchedInfo.h:1.28 --- llvm/include/llvm/Target/TargetSchedInfo.h:1.27 Sat May 8 11:13:26 2004 +++ llvm/include/llvm/Target/TargetSchedInfo.h Mon Jul 26 23:00:54 2004 @@ -9,6 +9,8 @@ // // This file describes the target machine to the instruction scheduler. // +// NOTE: This file is currently sparc V9 specific. +// //===----------------------------------------------------------------------===// #ifndef LLVM_TARGET_TARGETSCHEDINFO_H From lattner at cs.uiuc.edu Tue Jul 27 01:25:29 2004 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Tue, 27 Jul 2004 01:25:29 -0500 Subject: [llvm-commits] CVS: llvm/test/Regression/Analysis/GlobalsModRef/ Message-ID: <200407270625.BAA00585@apoc.cs.uiuc.edu> Changes in directory llvm/test/Regression/Analysis/GlobalsModRef: --- Log message: Directory /home/vadve/shared/PublicCVS/llvm/test/Regression/Analysis/GlobalsModRef added to the repository --- Diffs of the changes: (+0 -0) From lattner at cs.uiuc.edu Tue Jul 27 01:26:18 2004 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Tue, 27 Jul 2004 01:26:18 -0500 Subject: [llvm-commits] CVS: llvm/test/Regression/Analysis/GlobalsModRef/aliastest.ll modreftest.ll Message-ID: <200407270626.BAA00626@apoc.cs.uiuc.edu> Changes in directory llvm/test/Regression/Analysis/GlobalsModRef: aliastest.ll added (r1.1) modreftest.ll added (r1.1) --- Log message: Have some testcases --- Diffs of the changes: (+22 -0) Index: llvm/test/Regression/Analysis/GlobalsModRef/aliastest.ll diff -c /dev/null llvm/test/Regression/Analysis/GlobalsModRef/aliastest.ll:1.1 *** /dev/null Tue Jul 27 01:26:18 2004 --- llvm/test/Regression/Analysis/GlobalsModRef/aliastest.ll Tue Jul 27 01:26:08 2004 *************** *** 0 **** --- 1,9 ---- + ; RUN: llvm-as < %s | opt -globalsmodref-aa -load-vn -gcse | llvm-dis | not grep load + %X = internal global int 4 + + int %test(int *%P) { + store int 7, int* %P + store int 12, int* %X ;; cannot alias P, X's addr isn't taken + %V = load int* %P + ret int %V + } Index: llvm/test/Regression/Analysis/GlobalsModRef/modreftest.ll diff -c /dev/null llvm/test/Regression/Analysis/GlobalsModRef/modreftest.ll:1.1 *** /dev/null Tue Jul 27 01:26:18 2004 --- llvm/test/Regression/Analysis/GlobalsModRef/modreftest.ll Tue Jul 27 01:26:08 2004 *************** *** 0 **** --- 1,13 ---- + ; RUN: llvm-as < %s | opt -globalsmodref-aa -load-vn -gcse | llvm-dis | not grep load + %X = internal global int 4 + + int %test(int *%P) { + store int 12, int* %X + call void %doesnotmodX() + %V = load int* %X + ret int %V + } + + void %doesnotmodX() { + ret void + } From lattner at cs.uiuc.edu Tue Jul 27 01:35:21 2004 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Tue, 27 Jul 2004 01:35:21 -0500 Subject: [llvm-commits] CVS: llvm/test/Regression/Analysis/GlobalsModRef/purecse.ll Message-ID: <200407270635.BAA01406@apoc.cs.uiuc.edu> Changes in directory llvm/test/Regression/Analysis/GlobalsModRef: purecse.ll added (r1.1) --- Log message: new testcase --- Diffs of the changes: (+15 -0) Index: llvm/test/Regression/Analysis/GlobalsModRef/purecse.ll diff -c /dev/null llvm/test/Regression/Analysis/GlobalsModRef/purecse.ll:1.1 *** /dev/null Tue Jul 27 01:35:21 2004 --- llvm/test/Regression/Analysis/GlobalsModRef/purecse.ll Tue Jul 27 01:35:11 2004 *************** *** 0 **** --- 1,15 ---- + ; Test that pure functions are cse'd away + + ; RUN: llvm-as < %s | opt -globalsmodref-aa -load-vn -gcse -instcombine -adce| llvm-dis | not grep call + + int %pure(int %X) { + %Y = add int %X, 1 + ret int %Y + } + + int %test(int %X) { + %A = call int %pure(int %X) + %B = call int %pure(int %X) + %C = sub int %A, %B + ret int %C + } From lattner at cs.uiuc.edu Tue Jul 27 01:40:48 2004 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Tue, 27 Jul 2004 01:40:48 -0500 Subject: [llvm-commits] CVS: llvm/lib/Analysis/IPA/GlobalsModRef.cpp Message-ID: <200407270640.BAA01541@apoc.cs.uiuc.edu> Changes in directory llvm/lib/Analysis/IPA: GlobalsModRef.cpp updated: 1.2 -> 1.3 --- Log message: Complete rewrite of this pass to be faster, use less memory, be easier to understand, and more accurate to boot! This implements GlobalModRef/purecse.ll over the previous impl. --- Diffs of the changes: (+148 -97) Index: llvm/lib/Analysis/IPA/GlobalsModRef.cpp diff -u llvm/lib/Analysis/IPA/GlobalsModRef.cpp:1.2 llvm/lib/Analysis/IPA/GlobalsModRef.cpp:1.3 --- llvm/lib/Analysis/IPA/GlobalsModRef.cpp:1.2 Sat Jul 17 19:18:30 2004 +++ llvm/lib/Analysis/IPA/GlobalsModRef.cpp Tue Jul 27 01:40:37 2004 @@ -8,12 +8,13 @@ //===----------------------------------------------------------------------===// // // This simple pass provides alias and mod/ref information for global values -// that do not have their address taken. For this simple (but very common) -// case, we can provide pretty accurate and useful information. +// that do not have their address taken, and keeps track of whether functions +// read or write memory (are "pure"). For this simple (but very common) case, +// we can provide pretty accurate and useful information. // //===----------------------------------------------------------------------===// -#define DEBUG_TYPE "globalsmodref" +#define DEBUG_TYPE "globalsmodref-aa" #include "llvm/Analysis/Passes.h" #include "llvm/Module.h" #include "llvm/Pass.h" @@ -21,6 +22,8 @@ #include "llvm/Constants.h" #include "llvm/Analysis/AliasAnalysis.h" #include "llvm/Analysis/CallGraph.h" +#include "llvm/Support/InstIterator.h" +#include "Support/CommandLine.h" #include "Support/Debug.h" #include "Support/Statistic.h" #include "Support/SCCIterator.h" @@ -34,22 +37,44 @@ Statistic<> NumNonAddrTakenFunctions("globalsmodref-aa", "Number of functions without address taken"); + Statistic<> + NumNoMemFunctions("globalsmodref-aa", + "Number of functions that do not access memory"); + Statistic<> + NumReadMemFunctions("globalsmodref-aa", + "Number of functions that only read memory"); + /// FunctionRecord - One instance of this structure is stored for every + /// function in the program. Later, the entries for these functions are + /// removed if the function is found to call an external function (in which + /// case we know nothing about it. + struct FunctionRecord { + /// GlobalInfo - Maintain mod/ref info for all of the globals without + /// addresses taken that are read or written (transitively) by this + /// function. + std::map GlobalInfo; + + unsigned getInfoForGlobal(GlobalValue *GV) const { + std::map::const_iterator I = GlobalInfo.find(GV); + if (I != GlobalInfo.end()) + return I->second; + return 0; + } + + /// FunctionEffect - Capture whether or not this function reads or writes to + /// ANY memory. If not, we can do a lot of aggressive analysis on it. + unsigned FunctionEffect; + }; + + /// GlobalsModRef - The actual analysis pass. class GlobalsModRef : public Pass, public AliasAnalysis { - /// ModRefFns - One instance of this record is kept for each global without - /// its address taken. - struct ModRefFns { - /// RefFns/ModFns - Sets of functions that and write globals. - std::set RefFns, ModFns; - }; - - /// NonAddressTakenGlobals - A map of globals that do not have their - /// addresses taken to their record. - std::map NonAddressTakenGlobals; + /// NonAddressTakenGlobals - The globals that do not have their addresses + /// taken. + std::set NonAddressTakenGlobals; /// FunctionInfo - For each function, keep track of what globals are /// modified or read. - std::map, unsigned> FunctionInfo; + std::map FunctionInfo; public: bool run(Module &M) { @@ -73,12 +98,37 @@ ModRefResult getModRefInfo(CallSite CS, Value *P, unsigned Size); bool hasNoModRefInfoForCalls() const { return false; } + bool doesNotAccessMemory(Function *F) { + if (FunctionRecord *FR = getFunctionInfo(F)) + if (FR->FunctionEffect == 0) + return true; + return AliasAnalysis::doesNotAccessMemory(F); + } + bool onlyReadsMemory(Function *F) { + if (FunctionRecord *FR = getFunctionInfo(F)) + if ((FR->FunctionEffect & Mod) == 0) + return true; + return AliasAnalysis::onlyReadsMemory(F); + } + + virtual void deleteValue(Value *V); virtual void copyValue(Value *From, Value *To); private: + /// getFunctionInfo - Return the function info for the function, or null if + /// the function calls an external function (in which case we don't have + /// anything useful to say about it). + FunctionRecord *getFunctionInfo(Function *F) { + std::map::iterator I = FunctionInfo.find(F); + if (I != FunctionInfo.end()) + return &I->second; + return 0; + } + void AnalyzeGlobals(Module &M); void AnalyzeCallGraph(CallGraph &CG, Module &M); + void AnalyzeSCC(std::vector &SCC); bool AnalyzeUsesOfGlobal(Value *V, std::vector &Readers, std::vector &Writers); }; @@ -100,25 +150,24 @@ for (Module::iterator I = M.begin(), E = M.end(); I != E; ++I) if (I->hasInternalLinkage()) { if (!AnalyzeUsesOfGlobal(I, Readers, Writers)) { - // Remember that we are tracking this global, and the mod/ref fns - ModRefFns &E = NonAddressTakenGlobals[I]; - E.RefFns.insert(Readers.begin(), Readers.end()); - E.ModFns.insert(Writers.begin(), Writers.end()); + // Remember that we are tracking this global. + NonAddressTakenGlobals.insert(I); ++NumNonAddrTakenFunctions; } Readers.clear(); Writers.clear(); } for (Module::giterator I = M.gbegin(), E = M.gend(); I != E; ++I) - // FIXME: it is kinda dumb to track aliasing properties for constant - // globals, it will never be particularly useful anyways, 'cause they can - // never be modified (and the optimizer knows this already)! if (I->hasInternalLinkage()) { if (!AnalyzeUsesOfGlobal(I, Readers, Writers)) { // Remember that we are tracking this global, and the mod/ref fns - ModRefFns &E = NonAddressTakenGlobals[I]; - E.RefFns.insert(Readers.begin(), Readers.end()); - E.ModFns.insert(Writers.begin(), Writers.end()); + NonAddressTakenGlobals.insert(I); + for (unsigned i = 0, e = Readers.size(); i != e; ++i) + FunctionInfo[Readers[i]].GlobalInfo[I] |= Ref; + + if (!I->isConstant()) // No need to keep track of writers to constants + for (unsigned i = 0, e = Writers.size(); i != e; ++i) + FunctionInfo[Writers[i]].GlobalInfo[I] |= Mod; ++NumNonAddrTakenGlobalVars; } Readers.clear(); Writers.clear(); @@ -132,7 +181,7 @@ bool GlobalsModRef::AnalyzeUsesOfGlobal(Value *V, std::vector &Readers, std::vector &Writers) { - //if (!isa(V->getType())) return true; + if (!isa(V->getType())) return true; for (Value::use_iterator UI = V->use_begin(), E = V->use_end(); UI != E; ++UI) if (LoadInst *LI = dyn_cast(*UI)) { @@ -175,67 +224,82 @@ /// AnalyzeCallGraph - At this point, we know the functions where globals are /// immediately stored to and read from. Propagate this information up the call -/// graph to all callers. +/// graph to all callers and compute the mod/ref info for all memory for each +/// function. void GlobalsModRef::AnalyzeCallGraph(CallGraph &CG, Module &M) { - if (NonAddressTakenGlobals.empty()) return; // Don't bother, nothing to do. - - // Invert the NonAddressTakenGlobals map into the FunctionInfo map. - for (std::map::iterator I = - NonAddressTakenGlobals.begin(), E = NonAddressTakenGlobals.end(); - I != E; ++I) { - GlobalValue *GV = I->first; - ModRefFns &MRInfo = I->second; - for (std::set::iterator I = MRInfo.RefFns.begin(), - E = MRInfo.RefFns.begin(); I != E; ++I) - FunctionInfo[std::make_pair(*I, GV)] |= Ref; - MRInfo.RefFns.clear(); - for (std::set::iterator I = MRInfo.ModFns.begin(), - E = MRInfo.ModFns.begin(); I != E; ++I) - FunctionInfo[std::make_pair(*I, GV)] |= Mod; - MRInfo.ModFns.clear(); - } + DEBUG(std::cerr << "GlobalsModRef: Analyze Call Graph\n"); // We do a bottom-up SCC traversal of the call graph. In other words, we // visit all callees before callers (leaf-first). - for (scc_iterator I = scc_begin(&CG), E = scc_end(&CG); - I != E; ++I) { - std::map ModRefProperties; - const std::vector &SCC = *I; + for (scc_iterator I = scc_begin(&CG), E = scc_end(&CG); I!=E; ++I) + // Do not call AnalyzeSCC on the external function node. + if ((*I).size() != 1 || (*I)[0]->getFunction()) + AnalyzeSCC(*I); +} + +void GlobalsModRef::AnalyzeSCC(std::vector &SCC) { + assert(!SCC.empty() && "SCC with no functions?"); + FunctionRecord &FR = FunctionInfo[SCC[0]->getFunction()]; + + bool CallsExternal = false; + unsigned FunctionEffect = 0; + + // Collect the mod/ref properties due to called functions. We only compute + // one mod-ref set + for (unsigned i = 0, e = SCC.size(); i != e && !CallsExternal; ++i) + for (CallGraphNode::iterator CI = SCC[i]->begin(), E = SCC[i]->end(); + CI != E; ++CI) + if (Function *Callee = (*CI)->getFunction()) { + if (FunctionRecord *CalleeFR = getFunctionInfo(Callee)) { + // Propagate function effect up. + FunctionEffect |= CalleeFR->FunctionEffect; + + // Incorporate callee's effects on globals into our info. + for (std::map::iterator GI = + CalleeFR->GlobalInfo.begin(), E = CalleeFR->GlobalInfo.end(); + GI != E; ++GI) + FR.GlobalInfo[GI->first] |= GI->second; - // Collect the mod/ref properties due to called functions. - for (unsigned i = 0, e = SCC.size(); i != e; ++i) - for (CallGraphNode::iterator CI = SCC[i]->begin(), E = SCC[i]->end(); - CI != E; ++CI) { - if (Function *Callee = (*CI)->getFunction()) { - // Otherwise, combine the callee properties into our accumulated set. - std::map, unsigned>::iterator - CI = FunctionInfo.lower_bound(std::make_pair(Callee, - (GlobalValue*)0)); - for (;CI != FunctionInfo.end() && CI->first.first == Callee; ++CI) - ModRefProperties[CI->first.second] |= CI->second; } else { - // For now assume that external functions could mod/ref anything, - // since they could call into an escaping function that mod/refs an - // internal. FIXME: We need better tracking! - for (std::map::iterator GI = - NonAddressTakenGlobals.begin(), - E = NonAddressTakenGlobals.end(); GI != E; ++GI) - ModRefProperties[GI->first] = ModRef; - goto Out; + CallsExternal = true; + break; } + } else { + CallsExternal = true; + break; } - Out: - // Set all functions in the CFG to have these properties. FIXME: it would - // be better to use union find to only store these properties once, - // PARTICULARLY if it's the universal set. + + // If this SCC calls an external function, we can't say anything about it, so + // remove all SCC functions from the FunctionInfo map. + if (CallsExternal) { for (unsigned i = 0, e = SCC.size(); i != e; ++i) - if (Function *F = SCC[i]->getFunction()) { - for (std::map::iterator I = - ModRefProperties.begin(), E = ModRefProperties.end(); - I != E; ++I) - FunctionInfo[std::make_pair(F, I->first)] = I->second; - } + FunctionInfo.erase(SCC[i]->getFunction()); + return; + } + + // Otherwise, unless we already know that this function mod/refs memory, scan + // the function bodies to see if there are any explicit loads or stores. + if (FunctionEffect != ModRef) { + for (unsigned i = 0, e = SCC.size(); i != e && FunctionEffect != ModRef;++i) + for (inst_iterator II = inst_begin(SCC[i]->getFunction()), + E = inst_end(SCC[i]->getFunction()); + II != E && FunctionEffect != ModRef; ++II) + if (isa(*II)) + FunctionEffect |= Ref; + else if (isa(*II)) + FunctionEffect |= Mod; } + + if ((FunctionEffect & Mod) == 0) + ++NumReadMemFunctions; + if (FunctionEffect == 0) + ++NumNoMemFunctions; + FR.FunctionEffect = FunctionEffect; + + // Finally, now that we know the full effect on this SCC, clone the + // information to each function in the SCC. + for (unsigned i = 1, e = SCC.size(); i != e; ++i) + FunctionInfo[SCC[i]->getFunction()] = FR; } @@ -244,7 +308,7 @@ /// the specified value points to. If the value points to, or is derived from, /// a global object, return it. static const GlobalValue *getUnderlyingObject(const Value *V) { - //if (!isa(V->getType())) return 0; + if (!isa(V->getType())) return 0; // If we are at some type of object... return it. if (const GlobalValue *GV = dyn_cast(V)) return GV; @@ -286,15 +350,13 @@ unsigned Known = ModRef; // If we are asking for mod/ref info of a direct call with a pointer to a - // global, return information if we have it. + // global we are tracking, return information if we have it. if (GlobalValue *GV = const_cast(getUnderlyingObject(P))) if (GV->hasInternalLinkage()) - if (Function *F = CS.getCalledFunction()) { - std::map, unsigned>::iterator - it = FunctionInfo.find(std::make_pair(F, GV)); - if (it != FunctionInfo.end()) - Known = it->second; - } + if (Function *F = CS.getCalledFunction()) + if (NonAddressTakenGlobals.count(GV)) + if (FunctionRecord *FR = getFunctionInfo(F)) + Known = FR->getInfoForGlobal(GV); if (Known == NoModRef) return NoModRef; // No need to query other mod/ref analyses @@ -306,20 +368,9 @@ // Methods to update the analysis as a result of the client transformation. // void GlobalsModRef::deleteValue(Value *V) { - if (GlobalValue *GV = dyn_cast(V)) { - std::map::iterator I = - NonAddressTakenGlobals.find(GV); - if (I != NonAddressTakenGlobals.end()) - NonAddressTakenGlobals.erase(I); - } + if (GlobalValue *GV = dyn_cast(V)) + NonAddressTakenGlobals.erase(GV); } void GlobalsModRef::copyValue(Value *From, Value *To) { - if (GlobalValue *FromGV = dyn_cast(From)) - if (GlobalValue *ToGV = dyn_cast(To)) { - std::map::iterator I = - NonAddressTakenGlobals.find(FromGV); - if (I != NonAddressTakenGlobals.end()) - NonAddressTakenGlobals[ToGV] = I->second; - } } From lattner at cs.uiuc.edu Tue Jul 27 02:22:31 2004 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Tue, 27 Jul 2004 02:22:31 -0500 Subject: [llvm-commits] CVS: llvm/lib/Analysis/AliasSetTracker.cpp Message-ID: <200407270722.CAA04599@apoc.cs.uiuc.edu> Changes in directory llvm/lib/Analysis: AliasSetTracker.cpp updated: 1.24 -> 1.25 --- Log message: Remove a bogus assertion --- Diffs of the changes: (+0 -3) Index: llvm/lib/Analysis/AliasSetTracker.cpp diff -u llvm/lib/Analysis/AliasSetTracker.cpp:1.24 llvm/lib/Analysis/AliasSetTracker.cpp:1.25 --- llvm/lib/Analysis/AliasSetTracker.cpp:1.24 Mon Jul 26 21:20:26 2004 +++ llvm/lib/Analysis/AliasSetTracker.cpp Tue Jul 27 02:22:21 2004 @@ -41,9 +41,6 @@ AS.CallSites.clear(); } - // FIXME: If AS's refcount is zero, nuke it now... - assert(RefCount != 0); - AS.Forward = this; // Forward across AS now... addRef(); // AS is now pointing to us... From lattner at cs.uiuc.edu Tue Jul 27 02:30:13 2004 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Tue, 27 Jul 2004 02:30:13 -0500 Subject: [llvm-commits] CVS: llvm/lib/VMCore/iMemory.cpp Message-ID: <200407270730.CAA06450@apoc.cs.uiuc.edu> Changes in directory llvm/lib/VMCore: iMemory.cpp updated: 1.42 -> 1.43 --- Log message: alloca void makes no sense --- Diffs of the changes: (+1 -0) Index: llvm/lib/VMCore/iMemory.cpp diff -u llvm/lib/VMCore/iMemory.cpp:1.42 llvm/lib/VMCore/iMemory.cpp:1.43 --- llvm/lib/VMCore/iMemory.cpp:1.42 Wed Jul 14 13:14:33 2004 +++ llvm/lib/VMCore/iMemory.cpp Tue Jul 27 02:30:02 2004 @@ -17,6 +17,7 @@ using namespace llvm; void AllocationInst::init(const Type *Ty, Value *ArraySize, unsigned iTy) { + assert(Ty != Type::VoidTy && "Cannot allocate void elements!"); // ArraySize defaults to 1. if (!ArraySize) ArraySize = ConstantUInt::get(Type::UIntTy, 1); From lattner at cs.uiuc.edu Tue Jul 27 02:38:42 2004 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Tue, 27 Jul 2004 02:38:42 -0500 Subject: [llvm-commits] CVS: llvm/lib/Transforms/Scalar/LICM.cpp Message-ID: <200407270738.CAA08129@apoc.cs.uiuc.edu> Changes in directory llvm/lib/Transforms/Scalar: LICM.cpp updated: 1.63 -> 1.64 --- Log message: Fix hoisting of void typed values, e.g. calls --- Diffs of the changes: (+13 -7) Index: llvm/lib/Transforms/Scalar/LICM.cpp diff -u llvm/lib/Transforms/Scalar/LICM.cpp:1.63 llvm/lib/Transforms/Scalar/LICM.cpp:1.64 --- llvm/lib/Transforms/Scalar/LICM.cpp:1.63 Sat Jun 19 15:23:35 2004 +++ llvm/lib/Transforms/Scalar/LICM.cpp Tue Jul 27 02:38:32 2004 @@ -462,9 +462,12 @@ // the value into a stack object to get it to do this. // Firstly, we create a stack object to hold the value... - AllocaInst *AI = new AllocaInst(I.getType(), 0, I.getName(), - I.getParent()->getParent()->front().begin()); + AllocaInst *AI = 0; + if (I.getType() != Type::VoidTy) + AI = new AllocaInst(I.getType(), 0, I.getName(), + I.getParent()->getParent()->front().begin()); + // Secondly, insert load instructions for each use of the instruction // outside of the loop. while (!I.use_empty()) { @@ -522,12 +525,13 @@ New = &I; } else { New = I.clone(); - New->setName(I.getName()+".le"); + if (!I.getName().empty()) + New->setName(I.getName()+".le"); ExitBlock->getInstList().insert(InsertPt, New); } // Now that we have inserted the instruction, store it into the alloca - new StoreInst(New, AI, InsertPt); + if (AI) new StoreInst(New, AI, InsertPt); } } } @@ -539,9 +543,11 @@ } // Finally, promote the fine value to SSA form. - std::vector Allocas; - Allocas.push_back(AI); - PromoteMemToReg(Allocas, *DT, *DF, AA->getTargetData()); + if (AI) { + std::vector Allocas; + Allocas.push_back(AI); + PromoteMemToReg(Allocas, *DT, *DF, AA->getTargetData()); + } } } From lattner at cs.uiuc.edu Tue Jul 27 02:46:37 2004 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Tue, 27 Jul 2004 02:46:37 -0500 Subject: [llvm-commits] CVS: llvm/lib/Analysis/IPA/GlobalsModRef.cpp Message-ID: <200407270746.CAA09044@apoc.cs.uiuc.edu> Changes in directory llvm/lib/Analysis/IPA: GlobalsModRef.cpp updated: 1.3 -> 1.4 --- Log message: Fix conservative assumption, which was quite broken. Also, notice that functions known to not access memory (like sin/cos) don't access memory! :) --- Diffs of the changes: (+22 -2) Index: llvm/lib/Analysis/IPA/GlobalsModRef.cpp diff -u llvm/lib/Analysis/IPA/GlobalsModRef.cpp:1.3 llvm/lib/Analysis/IPA/GlobalsModRef.cpp:1.4 --- llvm/lib/Analysis/IPA/GlobalsModRef.cpp:1.3 Tue Jul 27 01:40:37 2004 +++ llvm/lib/Analysis/IPA/GlobalsModRef.cpp Tue Jul 27 02:46:26 2004 @@ -64,6 +64,8 @@ /// FunctionEffect - Capture whether or not this function reads or writes to /// ANY memory. If not, we can do a lot of aggressive analysis on it. unsigned FunctionEffect; + + FunctionRecord() : FunctionEffect(0) {} }; /// GlobalsModRef - The actual analysis pass. @@ -232,9 +234,27 @@ // We do a bottom-up SCC traversal of the call graph. In other words, we // visit all callees before callers (leaf-first). for (scc_iterator I = scc_begin(&CG), E = scc_end(&CG); I!=E; ++I) - // Do not call AnalyzeSCC on the external function node. - if ((*I).size() != 1 || (*I)[0]->getFunction()) + if ((*I).size() != 1) { AnalyzeSCC(*I); + } else if (Function *F = (*I)[0]->getFunction()) { + if (!F->isExternal()) { + // Nonexternal function. + AnalyzeSCC(*I); + } else { + // Otherwise external function. Handle intrinsics and other special + // cases here. + if (getAnalysis().doesNotAccessMemory(F)) + // If it does not access memory, process the function, causing us to + // realize it doesn't do anything (the body is empty). + AnalyzeSCC(*I); + else { + // Otherwise, don't process it. This will cause us to conservatively + // assume the worst. + } + } + } else { + // Do not process the external node, assume the worst. + } } void GlobalsModRef::AnalyzeSCC(std::vector &SCC) { From lattner at cs.uiuc.edu Tue Jul 27 02:49:50 2004 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Tue, 27 Jul 2004 02:49:50 -0500 Subject: [llvm-commits] CVS: llvm/docs/TableGenFundamentals.html Message-ID: <200407270749.CAA09423@apoc.cs.uiuc.edu> Changes in directory llvm/docs: TableGenFundamentals.html updated: 1.9 -> 1.10 --- Log message: Document new syntax --- Diffs of the changes: (+3 -1) Index: llvm/docs/TableGenFundamentals.html diff -u llvm/docs/TableGenFundamentals.html:1.9 llvm/docs/TableGenFundamentals.html:1.10 --- llvm/docs/TableGenFundamentals.html:1.9 Mon Jul 26 16:16:55 2004 +++ llvm/docs/TableGenFundamentals.html Tue Jul 27 02:49:39 2004 @@ -309,6 +309,8 @@
  • value{17} - Access to one or more bits of a value.
  • DEF - Reference to a record definition.
  • X.Y - Reference to the subfield of a value.
    • +
  • list[4-7,17,2-3] - A slice of the 'list' list, including elements + 4,5,6,7,17,2, and 3 from it. Elements may be included multiple times.
  • (DEF a, b) - A dag value. The first element is required to be a record definition, the remaining elements in the list may be arbitrary other values, @@ -557,7 +559,7 @@ Chris Lattner
    LLVM Compiler Infrastructure
    - Last modified: $Date: 2004/07/26 21:16:55 $ + Last modified: $Date: 2004/07/27 07:49:39 $ From lattner at cs.uiuc.edu Tue Jul 27 02:50:17 2004 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Tue, 27 Jul 2004 02:50:17 -0500 Subject: [llvm-commits] CVS: llvm/docs/AliasAnalysis.html Message-ID: <200407270750.CAA09451@apoc.cs.uiuc.edu> Changes in directory llvm/docs: AliasAnalysis.html updated: 1.22 -> 1.23 --- Log message: New functionality --- Diffs of the changes: (+6 -4) Index: llvm/docs/AliasAnalysis.html diff -u llvm/docs/AliasAnalysis.html:1.22 llvm/docs/AliasAnalysis.html:1.23 --- llvm/docs/AliasAnalysis.html:1.22 Thu Jul 1 10:33:24 2004 +++ llvm/docs/AliasAnalysis.html Tue Jul 27 02:50:07 2004 @@ -699,9 +699,11 @@

    This pass implements a simple context-sensitive mod/ref and alias analysis -for internal global variables that don't "have their address taken". If a -global does not have its address taken, the pass knows that no pointers alias -the global. +for internal global variables that don't "have their address taken". If a +global does not have its address taken, the pass knows that no pointers alias +the global. This pass also keeps track of functions that it knows never access +memory or never read memory. This allows certain optimizations (e.g. GCSE) to +eliminate call instructions entirely.

    The real power of this pass is that it provides context-sensitive mod/ref @@ -938,7 +940,7 @@ Chris Lattner
    LLVM Compiler Infrastructure
    - Last modified: $Date: 2004/07/01 15:33:24 $ + Last modified: $Date: 2004/07/27 07:50:07 $ From lattner at cs.uiuc.edu Tue Jul 27 03:03:28 2004 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Tue, 27 Jul 2004 03:03:28 -0500 Subject: [llvm-commits] CVS: llvm/lib/Analysis/IPA/GlobalsModRef.cpp Message-ID: <200407270803.DAA10488@apoc.cs.uiuc.edu> Changes in directory llvm/lib/Analysis/IPA: GlobalsModRef.cpp updated: 1.4 -> 1.5 --- Log message: nuke pointless -debug output --- Diffs of the changes: (+0 -4) Index: llvm/lib/Analysis/IPA/GlobalsModRef.cpp diff -u llvm/lib/Analysis/IPA/GlobalsModRef.cpp:1.4 llvm/lib/Analysis/IPA/GlobalsModRef.cpp:1.5 --- llvm/lib/Analysis/IPA/GlobalsModRef.cpp:1.4 Tue Jul 27 02:46:26 2004 +++ llvm/lib/Analysis/IPA/GlobalsModRef.cpp Tue Jul 27 03:03:18 2004 @@ -14,7 +14,6 @@ // //===----------------------------------------------------------------------===// -#define DEBUG_TYPE "globalsmodref-aa" #include "llvm/Analysis/Passes.h" #include "llvm/Module.h" #include "llvm/Pass.h" @@ -24,7 +23,6 @@ #include "llvm/Analysis/CallGraph.h" #include "llvm/Support/InstIterator.h" #include "Support/CommandLine.h" -#include "Support/Debug.h" #include "Support/Statistic.h" #include "Support/SCCIterator.h" #include @@ -229,8 +227,6 @@ /// graph to all callers and compute the mod/ref info for all memory for each /// function. void GlobalsModRef::AnalyzeCallGraph(CallGraph &CG, Module &M) { - DEBUG(std::cerr << "GlobalsModRef: Analyze Call Graph\n"); - // We do a bottom-up SCC traversal of the call graph. In other words, we // visit all callees before callers (leaf-first). for (scc_iterator I = scc_begin(&CG), E = scc_end(&CG); I!=E; ++I) From lattner at cs.uiuc.edu Tue Jul 27 03:13:25 2004 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Tue, 27 Jul 2004 03:13:25 -0500 Subject: [llvm-commits] CVS: llvm/tools/gccld/GenerateCode.cpp Message-ID: <200407270813.DAA11103@apoc.cs.uiuc.edu> Changes in directory llvm/tools/gccld: GenerateCode.cpp updated: 1.29 -> 1.30 --- Log message: Run DSE at link-time, and turn on an IP alias analysis by default in gccld! The -disable-globalsmodref is temporary and will be removed eventually. --- Diffs of the changes: (+7 -1) Index: llvm/tools/gccld/GenerateCode.cpp diff -u llvm/tools/gccld/GenerateCode.cpp:1.29 llvm/tools/gccld/GenerateCode.cpp:1.30 --- llvm/tools/gccld/GenerateCode.cpp:1.29 Wed Jun 23 12:32:09 2004 +++ llvm/tools/gccld/GenerateCode.cpp Tue Jul 27 03:13:15 2004 @@ -17,6 +17,7 @@ #include "llvm/Module.h" #include "llvm/PassManager.h" #include "llvm/Analysis/LoadValueNumbering.h" +#include "llvm/Analysis/Passes.h" #include "llvm/Analysis/Verifier.h" #include "llvm/Bytecode/WriteBytecodePass.h" #include "llvm/Target/TargetData.h" @@ -37,6 +38,9 @@ cl::opt DisableOptimizations("disable-opt", cl::desc("Do not run any optimization passes")); + cl::opt + DisableGlobalsModRef("disable-globalsmodref", cl::Hidden, + cl::desc("Turn on the more aggressive alias analysis")); } /// CopyEnv - This function takes an array of environment variables and makes a @@ -196,11 +200,13 @@ addPass(Passes, createScalarReplAggregatesPass()); // Break up allocas // Run a few AA driven optimizations here and now, to cleanup the code. - // Eventually we should put an IP AA in place here. + if (!DisableGlobalsModRef) + addPass(Passes, createGlobalsModRefPass()); // IP alias analysis addPass(Passes, createLICMPass()); // Hoist loop invariants addPass(Passes, createLoadValueNumberingPass()); // GVN for load instrs addPass(Passes, createGCSEPass()); // Remove common subexprs + addPass(Passes, createDeadStoreEliminationPass()); // Nuke dead stores // Cleanup and simplify the code after the scalar optimizations. addPass(Passes, createInstructionCombiningPass()); From lattner at cs.uiuc.edu Tue Jul 27 03:29:16 2004 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Tue, 27 Jul 2004 03:29:16 -0500 Subject: [llvm-commits] CVS: llvm/utils/NightlyTest.pl Message-ID: <200407270829.DAA11296@apoc.cs.uiuc.edu> Changes in directory llvm/utils: NightlyTest.pl updated: 1.60 -> 1.61 --- Log message: Ugh, the upgrade of zion brought in GCC 3.3.2, our arch nemesis. --- Diffs of the changes: (+2 -0) Index: llvm/utils/NightlyTest.pl diff -u llvm/utils/NightlyTest.pl:1.60 llvm/utils/NightlyTest.pl:1.61 --- llvm/utils/NightlyTest.pl:1.60 Fri Jun 25 02:25:28 2004 +++ llvm/utils/NightlyTest.pl Tue Jul 27 03:29:06 2004 @@ -32,6 +32,7 @@ # on busy servers. # -gnuplotscript Next argument specifies gnuplot script to use # -templatefile Next argument specifies template file to use +# -gccpath Path to gcc/g++ used to build LLVM # # CVSROOT is the CVS repository from which the tree will be checked out, # specified either in the full :method:user at host:/dir syntax, or @@ -269,6 +270,7 @@ if (/^-nice$/) { $NICE = "nice "; next; } if (/^-gnuplotscript$/) { $PlotScriptFilename = $ARGV[0]; shift; next; } if (/^-templatefile$/) { $Template = $ARGV[0]; shift; next; } + if (/^-gccpath/) { $CONFIGUREARGS=" CC=$ARGV[0]/gcc CXX=$ARGV[0]/g++"; shift; next; } if (/^-noexternals$/) { $NOEXTERNALS = 1; next; } print "Unknown option: $_ : ignoring!\n"; From gaeke at cs.uiuc.edu Tue Jul 27 12:43:31 2004 From: gaeke at cs.uiuc.edu (Brian Gaeke) Date: Tue, 27 Jul 2004 12:43:31 -0500 (CDT) Subject: [llvm-commits] CVS: llvm/lib/Analysis/LoadValueNumbering.cpp Message-ID: <200407271743.MAA10040@seraph.cs.uiuc.edu> Changes in directory llvm/lib/Analysis: LoadValueNumbering.cpp updated: 1.19 -> 1.20 --- Log message: Make the create...() functions for some of these passes return a FunctionPass *. --- Diffs of the changes: (+1 -1) Index: llvm/lib/Analysis/LoadValueNumbering.cpp diff -u llvm/lib/Analysis/LoadValueNumbering.cpp:1.19 llvm/lib/Analysis/LoadValueNumbering.cpp:1.20 --- llvm/lib/Analysis/LoadValueNumbering.cpp:1.19 Sun May 23 16:13:24 2004 +++ llvm/lib/Analysis/LoadValueNumbering.cpp Tue Jul 27 12:43:21 2004 @@ -87,7 +87,7 @@ RegisterAnalysisGroup Y; } -Pass *llvm::createLoadValueNumberingPass() { return new LoadVN(); } +FunctionPass *llvm::createLoadValueNumberingPass() { return new LoadVN(); } /// getAnalysisUsage - Does not modify anything. It uses Value Numbering and From gaeke at cs.uiuc.edu Tue Jul 27 12:43:31 2004 From: gaeke at cs.uiuc.edu (Brian Gaeke) Date: Tue, 27 Jul 2004 12:43:31 -0500 (CDT) Subject: [llvm-commits] CVS: llvm/include/llvm/Analysis/LoadValueNumbering.h Message-ID: <200407271743.MAA10033@seraph.cs.uiuc.edu> Changes in directory llvm/include/llvm/Analysis: LoadValueNumbering.h updated: 1.3 -> 1.4 --- Log message: Make the create...() functions for some of these passes return a FunctionPass *. --- Diffs of the changes: (+2 -2) Index: llvm/include/llvm/Analysis/LoadValueNumbering.h diff -u llvm/include/llvm/Analysis/LoadValueNumbering.h:1.3 llvm/include/llvm/Analysis/LoadValueNumbering.h:1.4 --- llvm/include/llvm/Analysis/LoadValueNumbering.h:1.3 Tue Nov 11 16:41:31 2003 +++ llvm/include/llvm/Analysis/LoadValueNumbering.h Tue Jul 27 12:43:20 2004 @@ -23,12 +23,12 @@ namespace llvm { -class Pass; +class FunctionPass; /// createLoadValueNumberingPass - Create and return a new pass that implements /// the ValueNumbering interface. /// -Pass *createLoadValueNumberingPass(); +FunctionPass *createLoadValueNumberingPass(); } // End llvm namespace From gaeke at cs.uiuc.edu Tue Jul 27 12:43:31 2004 From: gaeke at cs.uiuc.edu (Brian Gaeke) Date: Tue, 27 Jul 2004 12:43:31 -0500 (CDT) Subject: [llvm-commits] CVS: llvm/include/llvm/Transforms/Scalar.h Message-ID: <200407271743.MAA10047@seraph.cs.uiuc.edu> Changes in directory llvm/include/llvm/Transforms: Scalar.h updated: 1.42 -> 1.43 --- Log message: Make the create...() functions for some of these passes return a FunctionPass *. --- Diffs of the changes: (+2 -2) Index: llvm/include/llvm/Transforms/Scalar.h diff -u llvm/include/llvm/Transforms/Scalar.h:1.42 llvm/include/llvm/Transforms/Scalar.h:1.43 --- llvm/include/llvm/Transforms/Scalar.h:1.42 Thu Jul 22 03:07:30 2004 +++ llvm/include/llvm/Transforms/Scalar.h Tue Jul 27 12:43:21 2004 @@ -61,7 +61,7 @@ // their other instructions become dead, to eliminate chains of dead // computations. // -Pass *createDeadCodeEliminationPass(); +FunctionPass *createDeadCodeEliminationPass(); //===----------------------------------------------------------------------===// // @@ -132,7 +132,7 @@ // into: // %Z = add int 2, %X // -Pass *createInstructionCombiningPass(); +FunctionPass *createInstructionCombiningPass(); //===----------------------------------------------------------------------===// From gaeke at cs.uiuc.edu Tue Jul 27 12:43:32 2004 From: gaeke at cs.uiuc.edu (Brian Gaeke) Date: Tue, 27 Jul 2004 12:43:32 -0500 (CDT) Subject: [llvm-commits] CVS: llvm/lib/Transforms/Scalar/DCE.cpp InstructionCombining.cpp Message-ID: <200407271743.MAA10056@seraph.cs.uiuc.edu> Changes in directory llvm/lib/Transforms/Scalar: DCE.cpp updated: 1.53 -> 1.54 InstructionCombining.cpp updated: 1.231 -> 1.232 --- Log message: Make the create...() functions for some of these passes return a FunctionPass *. --- Diffs of the changes: (+2 -2) Index: llvm/lib/Transforms/Scalar/DCE.cpp diff -u llvm/lib/Transforms/Scalar/DCE.cpp:1.53 llvm/lib/Transforms/Scalar/DCE.cpp:1.54 --- llvm/lib/Transforms/Scalar/DCE.cpp:1.53 Tue Apr 27 10:12:23 2004 +++ llvm/lib/Transforms/Scalar/DCE.cpp Tue Jul 27 12:43:21 2004 @@ -123,7 +123,7 @@ return true; } -Pass *llvm::createDeadCodeEliminationPass() { +FunctionPass *llvm::createDeadCodeEliminationPass() { return new DCE(); } Index: llvm/lib/Transforms/Scalar/InstructionCombining.cpp diff -u llvm/lib/Transforms/Scalar/InstructionCombining.cpp:1.231 llvm/lib/Transforms/Scalar/InstructionCombining.cpp:1.232 --- llvm/lib/Transforms/Scalar/InstructionCombining.cpp:1.231 Wed Jul 21 15:14:10 2004 +++ llvm/lib/Transforms/Scalar/InstructionCombining.cpp Tue Jul 27 12:43:21 2004 @@ -3210,7 +3210,7 @@ return Changed; } -Pass *llvm::createInstructionCombiningPass() { +FunctionPass *llvm::createInstructionCombiningPass() { return new InstCombiner(); } From gaeke at cs.uiuc.edu Tue Jul 27 12:43:32 2004 From: gaeke at cs.uiuc.edu (Brian Gaeke) Date: Tue, 27 Jul 2004 12:43:32 -0500 (CDT) Subject: [llvm-commits] CVS: llvm/include/llvm/Target/TargetInstrInfo.h Message-ID: <200407271743.MAA10063@seraph.cs.uiuc.edu> Changes in directory llvm/include/llvm/Target: TargetInstrInfo.h updated: 1.57 -> 1.58 --- Log message: As it happens, none of these TargetInstrInfo methods which are only used in the SparcV9 backend really have anything to do with TargetInstrInfo, so we're converting them into regular old global functions and moving their declarations to SparcV9InstrSelectionSupport.h. (They're mostly used as helper functions for SparcV9InstrSelection.) --- Diffs of the changes: (+0 -122) Index: llvm/include/llvm/Target/TargetInstrInfo.h diff -u llvm/include/llvm/Target/TargetInstrInfo.h:1.57 llvm/include/llvm/Target/TargetInstrInfo.h:1.58 --- llvm/include/llvm/Target/TargetInstrInfo.h:1.57 Sun Feb 29 00:30:35 2004 +++ llvm/include/llvm/Target/TargetInstrInfo.h Tue Jul 27 12:43:22 2004 @@ -252,128 +252,6 @@ /// sense for primitive types. /// virtual bool ConstantTypeMustBeLoaded(const Constant* CV) const; - - // Test if this constant may not fit in the immediate field of the - // machine instructions (probably) generated for this instruction. - // - virtual bool ConstantMayNotFitInImmedField(const Constant* CV, - const Instruction* I) const { - return true; // safe but very conservative - } - - // Get certain common op codes for the current target. this and all the - // Create* methods below should be moved to a machine code generation class - // - virtual MachineOpCode getNOPOpCode() const { abort(); } - - // Get the value of an integral constant in the form that must - // be put into the machine register. The specified constant is interpreted - // as (i.e., converted if necessary to) the specified destination type. The - // result is always returned as an uint64_t, since the representation of - // int64_t and uint64_t are identical. The argument can be any known const. - // - // isValidConstant is set to true if a valid constant was found. - // - virtual uint64_t ConvertConstantToIntType(const TargetMachine &target, - const Value *V, - const Type *destType, - bool &isValidConstant) const { - abort(); - } - - // Create an instruction sequence to put the constant `val' into - // the virtual register `dest'. `val' may be a Constant or a - // GlobalValue, viz., the constant address of a global variable or function. - // The generated instructions are returned in `mvec'. - // Any temp. registers (TmpInstruction) created are recorded in mcfi. - // Symbolic constants or constants that must be accessed from memory - // are added to the constant pool via MachineFunction::get(F). - // - virtual void CreateCodeToLoadConst(const TargetMachine& target, - Function* F, - Value* val, - Instruction* dest, - std::vector& mvec, - MachineCodeForInstruction& mcfi) const { - abort(); - } - - // Create an instruction sequence to copy an integer value `val' - // to a floating point value `dest' by copying to memory and back. - // val must be an integral type. dest must be a Float or Double. - // The generated instructions are returned in `mvec'. - // Any temp. registers (TmpInstruction) created are recorded in mcfi. - // Any stack space required is allocated via mcff. - // - virtual void CreateCodeToCopyIntToFloat(const TargetMachine& target, - Function* F, - Value* val, - Instruction* dest, - std::vector& mvec, - MachineCodeForInstruction& MI) const { - abort(); - } - - // Similarly, create an instruction sequence to copy an FP value - // `val' to an integer value `dest' by copying to memory and back. - // The generated instructions are returned in `mvec'. - // Any temp. registers (TmpInstruction) created are recorded in mcfi. - // Any stack space required is allocated via mcff. - // - virtual void CreateCodeToCopyFloatToInt(const TargetMachine& target, - Function* F, - Value* val, - Instruction* dest, - std::vector& mvec, - MachineCodeForInstruction& MI) const { - abort(); - } - - // Create instruction(s) to copy src to dest, for arbitrary types - // The generated instructions are returned in `mvec'. - // Any temp. registers (TmpInstruction) created are recorded in mcfi. - // Any stack space required is allocated via mcff. - // - virtual void CreateCopyInstructionsByType(const TargetMachine& target, - Function* F, - Value* src, - Instruction* dest, - std::vector& mvec, - MachineCodeForInstruction& MI) const { - abort(); - } - - // Create instruction sequence to produce a sign-extended register value - // from an arbitrary sized value (sized in bits, not bytes). - // The generated instructions are appended to `mvec'. - // Any temp. registers (TmpInstruction) created are recorded in mcfi. - // Any stack space required is allocated via mcff. - // - virtual void CreateSignExtensionInstructions(const TargetMachine& target, - Function* F, - Value* srcVal, - Value* destVal, - unsigned numLowBits, - std::vector& mvec, - MachineCodeForInstruction& MI) const { - abort(); - } - - // Create instruction sequence to produce a zero-extended register value - // from an arbitrary sized value (sized in bits, not bytes). - // The generated instructions are appended to `mvec'. - // Any temp. registers (TmpInstruction) created are recorded in mcfi. - // Any stack space required is allocated via mcff. - // - virtual void CreateZeroExtensionInstructions(const TargetMachine& target, - Function* F, - Value* srcVal, - Value* destVal, - unsigned srcSizeInBits, - std::vector& mvec, - MachineCodeForInstruction& mcfi) const { - abort(); - } }; } // End llvm namespace From gaeke at cs.uiuc.edu Tue Jul 27 12:43:32 2004 From: gaeke at cs.uiuc.edu (Brian Gaeke) Date: Tue, 27 Jul 2004 12:43:32 -0500 (CDT) Subject: [llvm-commits] CVS: llvm/lib/Target/SparcV9/SparcV9InstrInfo.h SparcV9InstrSelectionSupport.h Message-ID: <200407271743.MAA10072@seraph.cs.uiuc.edu> Changes in directory llvm/lib/Target/SparcV9: SparcV9InstrInfo.h updated: 1.7 -> 1.8 SparcV9InstrSelectionSupport.h updated: 1.18 -> 1.19 --- Log message: As it happens, none of these TargetInstrInfo methods which are only used in the SparcV9 backend really have anything to do with TargetInstrInfo, so we're converting them into regular old global functions and moving their declarations to SparcV9InstrSelectionSupport.h. (They're mostly used as helper functions for SparcV9InstrSelection.) --- Diffs of the changes: (+90 -104) Index: llvm/lib/Target/SparcV9/SparcV9InstrInfo.h diff -u llvm/lib/Target/SparcV9/SparcV9InstrInfo.h:1.7 llvm/lib/Target/SparcV9/SparcV9InstrInfo.h:1.8 --- llvm/lib/Target/SparcV9/SparcV9InstrInfo.h:1.7 Sun May 30 03:29:16 2004 +++ llvm/lib/Target/SparcV9/SparcV9InstrInfo.h Tue Jul 27 12:43:22 2004 @@ -68,110 +68,6 @@ // 2 other groups, including NOPs if necessary). return (opCode == V9::FCMPS || opCode == V9::FCMPD || opCode == V9::FCMPQ); } - - //------------------------------------------------------------------------- - // Queries about representation of LLVM quantities (e.g., constants) - //------------------------------------------------------------------------- - - virtual bool ConstantMayNotFitInImmedField(const Constant* CV, - const Instruction* I) const; - - //------------------------------------------------------------------------- - // Code generation support for creating individual machine instructions - //------------------------------------------------------------------------- - - // Get certain common op codes for the current target. This and all the - // Create* methods below should be moved to a machine code generation class - // - virtual MachineOpCode getNOPOpCode() const { return V9::NOP; } - - // Get the value of an integral constant in the form that must - // be put into the machine register. The specified constant is interpreted - // as (i.e., converted if necessary to) the specified destination type. The - // result is always returned as an uint64_t, since the representation of - // int64_t and uint64_t are identical. The argument can be any known const. - // - // isValidConstant is set to true if a valid constant was found. - // - virtual uint64_t ConvertConstantToIntType(const TargetMachine &target, - const Value *V, - const Type *destType, - bool &isValidConstant) const; - - // Create an instruction sequence to put the constant `val' into - // the virtual register `dest'. `val' may be a Constant or a - // GlobalValue, viz., the constant address of a global variable or function. - // The generated instructions are returned in `mvec'. - // Any temp. registers (TmpInstruction) created are recorded in mcfi. - // - virtual void CreateCodeToLoadConst(const TargetMachine& target, - Function* F, - Value* val, - Instruction* dest, - std::vector& mvec, - MachineCodeForInstruction& mcfi) const; - - // Create an instruction sequence to copy an integer value `val' - // to a floating point value `dest' by copying to memory and back. - // val must be an integral type. dest must be a Float or Double. - // The generated instructions are returned in `mvec'. - // Any temp. registers (TmpInstruction) created are recorded in mcfi. - // - virtual void CreateCodeToCopyIntToFloat(const TargetMachine& target, - Function* F, - Value* val, - Instruction* dest, - std::vector& mvec, - MachineCodeForInstruction& mcfi) const; - - // Similarly, create an instruction sequence to copy an FP value - // `val' to an integer value `dest' by copying to memory and back. - // The generated instructions are returned in `mvec'. - // Any temp. registers (TmpInstruction) created are recorded in mcfi. - // - virtual void CreateCodeToCopyFloatToInt(const TargetMachine& target, - Function* F, - Value* val, - Instruction* dest, - std::vector& mvec, - MachineCodeForInstruction& mcfi) const; - - // Create instruction(s) to copy src to dest, for arbitrary types - // The generated instructions are returned in `mvec'. - // Any temp. registers (TmpInstruction) created are recorded in mcfi. - // - virtual void CreateCopyInstructionsByType(const TargetMachine& target, - Function* F, - Value* src, - Instruction* dest, - std::vector& mvec, - MachineCodeForInstruction& mcfi) const; - - // Create instruction sequence to produce a sign-extended register value - // from an arbitrary sized value (sized in bits, not bytes). - // The generated instructions are appended to `mvec'. - // Any temp. registers (TmpInstruction) created are recorded in mcfi. - // - virtual void CreateSignExtensionInstructions(const TargetMachine& target, - Function* F, - Value* srcVal, - Value* destVal, - unsigned int numLowBits, - std::vector& mvec, - MachineCodeForInstruction& mcfi) const; - - // Create instruction sequence to produce a zero-extended register value - // from an arbitrary sized value (sized in bits, not bytes). - // The generated instructions are appended to `mvec'. - // Any temp. registers (TmpInstruction) created are recorded in mcfi. - // - virtual void CreateZeroExtensionInstructions(const TargetMachine& target, - Function* F, - Value* srcVal, - Value* destVal, - unsigned int numLowBits, - std::vector& mvec, - MachineCodeForInstruction& mcfi) const; }; } // End llvm namespace Index: llvm/lib/Target/SparcV9/SparcV9InstrSelectionSupport.h diff -u llvm/lib/Target/SparcV9/SparcV9InstrSelectionSupport.h:1.18 llvm/lib/Target/SparcV9/SparcV9InstrSelectionSupport.h:1.19 --- llvm/lib/Target/SparcV9/SparcV9InstrSelectionSupport.h:1.18 Thu Jul 1 23:57:35 2004 +++ llvm/lib/Target/SparcV9/SparcV9InstrSelectionSupport.h Tue Jul 27 12:43:22 2004 @@ -226,6 +226,96 @@ const TargetMachine& targetMachine, bool canUseImmed, unsigned& getMachineRegNum, int64_t& getImmedValue); +/// ConvertConstantToIntType - Get the value of an integral constant in the +/// form that must be put into the machine register. The specified constant is +/// interpreted as (i.e., converted if necessary to) the specified destination +/// type. The result is always returned as an uint64_t, since the +/// representation of int64_t and uint64_t are identical. The argument can be +/// any known const. isValidConstant is set to true if a valid constant was +/// found. +/// +uint64_t ConvertConstantToIntType (const TargetMachine &target, + const Value *V, const Type *destType, bool &isValidConstant); + +/// ConstantMayNotFitInImmedField - Test if this constant may not fit in the +/// immediate field of the machine instructions (probably) generated for this +/// instruction. +/// +bool ConstantMayNotFitInImmedField (const Constant *CV, const Instruction *I); + +/// CreateCodeToLoadConst - Create an instruction sequence to put the +/// constant `val' into the virtual register `dest'. `val' may be a Constant +/// or a GlobalValue, viz., the constant address of a global variable or +/// function. The generated instructions are returned in `mvec'. Any temp. +/// registers (TmpInstruction) created are recorded in mcfi. +/// +void CreateCodeToLoadConst (const TargetMachine &target, Function *F, + Value *val, Instruction *dest, std::vector &mvec, + MachineCodeForInstruction &mcfi); + +/// CreateSignExtensionInstructions - Create instruction sequence to produce a +/// sign-extended register value from an arbitrary sized value (sized in bits, +/// not bytes). The generated instructions are appended to `mvec'. Any temp. +/// registers (TmpInstruction) created are recorded in mcfi. +/// +void CreateSignExtensionInstructions (const TargetMachine &target, + Function *F, Value *srcVal, Value *destVal, unsigned int numLowBits, + std::vector &mvec, MachineCodeForInstruction &mcfi); + +/// CreateZeroExtensionInstructions - Create instruction sequence to produce a +/// zero-extended register value from an arbitrary sized value (sized in bits, +/// not bytes). The generated instructions are appended to `mvec'. Any temp. +/// registers (TmpInstruction) created are recorded in mcfi. +/// +void CreateZeroExtensionInstructions (const TargetMachine &target, + Function *F, Value *srcVal, Value *destVal, unsigned int numLowBits, + std::vector &mvec, MachineCodeForInstruction &mcfi); + +/// CreateCodeToCopyIntToFloat - Create an instruction sequence to copy an +/// integer value `val' to a floating point value `dest' by copying to memory +/// and back. val must be an integral type. dest must be a Float or Double. +/// The generated instructions are returned in `mvec'. Any temp. registers +/// (TmpInstruction) created are recorded in mcfi. +/// +void CreateCodeToCopyIntToFloat (const TargetMachine &target, + Function *F, Value *val, Instruction *dest, std::vector &mvec, + MachineCodeForInstruction &mcfi); + +/// CreateCodeToCopyFloatToInt - Create an instruction sequence to copy an FP +/// value `val' to an integer value `dest' by copying to memory and back. The +/// generated instructions are returned in `mvec'. Any temp. registers +/// (TmpInstruction) created are recorded in mcfi. +/// +void CreateCodeToCopyFloatToInt (const TargetMachine &target, Function *F, + Value *val, Instruction *dest, std::vector &mvec, + MachineCodeForInstruction &mcfi); + +/// CreateCopyInstructionsByType - Create instruction(s) to copy src to dest, +/// for arbitrary types The generated instructions are returned in `mvec'. Any +/// temp. registers (TmpInstruction) created are recorded in mcfi. +/// +void CreateCopyInstructionsByType (const TargetMachine &target, + Function *F, Value *src, Instruction *dest, std::vector &mvec, + MachineCodeForInstruction &mcfi); + +/// CreateSignExtensionInstructions - Create instruction sequence to produce a +/// sign-extended register value from an arbitrary sized value (sized in bits, +/// not bytes). The generated instructions are appended to `mvec'. Any temp. +/// registers (TmpInstruction) created are recorded in mcfi. +/// +void CreateSignExtensionInstructions (const TargetMachine &target, + Function *F, Value *srcVal, Value *destVal, unsigned int numLowBits, + std::vector &mvec, MachineCodeForInstruction &mcfi); + +/// CreateZeroExtensionInstructions - Create instruction sequence to produce a +/// zero-extended register value from an arbitrary sized value (sized in bits, +/// not bytes). The generated instructions are appended to `mvec'. Any temp. +/// registers (TmpInstruction) created are recorded in mcfi. +/// +void CreateZeroExtensionInstructions (const TargetMachine &target, + Function *F, Value *srcVal, Value *destVal, unsigned int numLowBits, + std::vector &mvec, MachineCodeForInstruction &mcfi); + } // End llvm namespace #endif From gaeke at cs.uiuc.edu Tue Jul 27 12:43:34 2004 From: gaeke at cs.uiuc.edu (Brian Gaeke) Date: Tue, 27 Jul 2004 12:43:34 -0500 (CDT) Subject: [llvm-commits] CVS: llvm/lib/Target/SparcV9/SparcV9PeepholeOpts.cpp Message-ID: <200407271743.MAA10097@seraph.cs.uiuc.edu> Changes in directory llvm/lib/Target/SparcV9: SparcV9PeepholeOpts.cpp updated: 1.24 -> 1.25 --- Log message: TargetInstrInfo::getNOPOpCode() has been replaced by a reference to V9::NOP. --- Diffs of the changes: (+1 -1) Index: llvm/lib/Target/SparcV9/SparcV9PeepholeOpts.cpp diff -u llvm/lib/Target/SparcV9/SparcV9PeepholeOpts.cpp:1.24 llvm/lib/Target/SparcV9/SparcV9PeepholeOpts.cpp:1.25 --- llvm/lib/Target/SparcV9/SparcV9PeepholeOpts.cpp:1.24 Wed Jun 2 00:54:43 2004 +++ llvm/lib/Target/SparcV9/SparcV9PeepholeOpts.cpp Tue Jul 27 12:43:24 2004 @@ -39,7 +39,7 @@ // to update the I-I maps. // assert(ndelay == 1 && "Not yet handling multiple-delay-slot targets"); - BBI->replace(mii.getNOPOpCode(), 0); + BBI->replace(V9::NOP, 0); return; } } From gaeke at cs.uiuc.edu Tue Jul 27 12:43:33 2004 From: gaeke at cs.uiuc.edu (Brian Gaeke) Date: Tue, 27 Jul 2004 12:43:33 -0500 (CDT) Subject: [llvm-commits] CVS: llvm/lib/Target/SparcV9/SparcV9InstrInfo.cpp SparcV9InstrSelection.cpp SparcV9PreSelection.cpp Message-ID: <200407271743.MAA10085@seraph.cs.uiuc.edu> Changes in directory llvm/lib/Target/SparcV9: SparcV9InstrInfo.cpp updated: 1.69 -> 1.70 SparcV9InstrSelection.cpp updated: 1.144 -> 1.145 SparcV9PreSelection.cpp updated: 1.36 -> 1.37 --- Log message: Convert many of the virtual TargetInstrInfo methods used as helper functions in SparcV9InstrSelection and SparcV9PreSelection into regular old global functions. As it happens, none of them really have anything to do with TargetInstrInfo. --- Diffs of the changes: (+46 -54) Index: llvm/lib/Target/SparcV9/SparcV9InstrInfo.cpp diff -u llvm/lib/Target/SparcV9/SparcV9InstrInfo.cpp:1.69 llvm/lib/Target/SparcV9/SparcV9InstrInfo.cpp:1.70 --- llvm/lib/Target/SparcV9/SparcV9InstrInfo.cpp:1.69 Mon Jul 19 08:25:02 2004 +++ llvm/lib/Target/SparcV9/SparcV9InstrInfo.cpp Tue Jul 27 12:43:23 2004 @@ -45,10 +45,10 @@ //--------------------------------------------------------------------------- uint64_t -SparcV9InstrInfo::ConvertConstantToIntType(const TargetMachine &target, +ConvertConstantToIntType(const TargetMachine &target, const Value *V, const Type *destType, - bool &isValidConstant) const + bool &isValidConstant) { isValidConstant = false; uint64_t C = 0; @@ -426,10 +426,7 @@ InitializeMaxConstantsTable(); } -bool -SparcV9InstrInfo::ConstantMayNotFitInImmedField(const Constant* CV, - const Instruction* I) const -{ +bool ConstantMayNotFitInImmedField(const Constant* CV, const Instruction* I) { if (I->getOpcode() >= MaxConstantsTable.size()) // user-defined op (or bug!) return true; @@ -457,12 +454,12 @@ // Any stack space required is allocated via MachineFunction. // void -SparcV9InstrInfo::CreateCodeToLoadConst(const TargetMachine& target, +CreateCodeToLoadConst(const TargetMachine& target, Function* F, Value* val, Instruction* dest, std::vector& mvec, - MachineCodeForInstruction& mcfi) const + MachineCodeForInstruction& mcfi) { assert(isa(val) && "I only know about constant values and global addresses"); @@ -541,7 +538,6 @@ } } - // Create an instruction sequence to copy an integer register `val' // to a floating point register `dest' by copying to memory and back. // val must be an integral type. dest must be a Float or Double. @@ -550,12 +546,12 @@ // Any stack space required is allocated via MachineFunction. // void -SparcV9InstrInfo::CreateCodeToCopyIntToFloat(const TargetMachine& target, +CreateCodeToCopyIntToFloat(const TargetMachine& target, Function* F, Value* val, Instruction* dest, std::vector& mvec, - MachineCodeForInstruction& mcfi) const + MachineCodeForInstruction& mcfi) { assert((val->getType()->isIntegral() || isa(val->getType())) && "Source type must be integral (integer or bool) or pointer"); @@ -611,12 +607,12 @@ // Temporary stack space required is allocated via MachineFunction. // void -SparcV9InstrInfo::CreateCodeToCopyFloatToInt(const TargetMachine& target, +CreateCodeToCopyFloatToInt(const TargetMachine& target, Function* F, Value* val, Instruction* dest, std::vector& mvec, - MachineCodeForInstruction& mcfi) const + MachineCodeForInstruction& mcfi) { const Type* opTy = val->getType(); const Type* destTy = dest->getType(); @@ -662,12 +658,12 @@ // Any stack space required is allocated via MachineFunction. // void -SparcV9InstrInfo::CreateCopyInstructionsByType(const TargetMachine& target, +CreateCopyInstructionsByType(const TargetMachine& target, Function *F, Value* src, Instruction* dest, std::vector& mvec, - MachineCodeForInstruction& mcfi) const + MachineCodeForInstruction& mcfi) { bool loadConstantToReg = false; @@ -697,8 +693,7 @@ if (loadConstantToReg) { // `src' is constant and cannot fit in immed field for the ADD // Insert instructions to "load" the constant into a register - target.getInstrInfo()->CreateCodeToLoadConst(target, F, src, dest, - mvec, mcfi); + CreateCodeToLoadConst(target, F, src, dest, mvec, mcfi); } else { // Create a reg-to-reg copy instruction for the given type: // -- For FP values, create a FMOVS or FMOVD instruction @@ -756,14 +751,14 @@ // Any stack space required is allocated via MachineFunction. // void -SparcV9InstrInfo::CreateSignExtensionInstructions( +CreateSignExtensionInstructions( const TargetMachine& target, Function* F, Value* srcVal, Value* destVal, unsigned int numLowBits, std::vector& mvec, - MachineCodeForInstruction& mcfi) const + MachineCodeForInstruction& mcfi) { CreateBitExtensionInstructions(/*signExtend*/ true, target, F, srcVal, destVal, numLowBits, mvec, mcfi); @@ -778,14 +773,14 @@ // Any stack space required is allocated via MachineFunction. // void -SparcV9InstrInfo::CreateZeroExtensionInstructions( +CreateZeroExtensionInstructions( const TargetMachine& target, Function* F, Value* srcVal, Value* destVal, unsigned int numLowBits, std::vector& mvec, - MachineCodeForInstruction& mcfi) const + MachineCodeForInstruction& mcfi) { CreateBitExtensionInstructions(/*signExtend*/ false, target, F, srcVal, destVal, numLowBits, mvec, mcfi); Index: llvm/lib/Target/SparcV9/SparcV9InstrSelection.cpp diff -u llvm/lib/Target/SparcV9/SparcV9InstrSelection.cpp:1.144 llvm/lib/Target/SparcV9/SparcV9InstrSelection.cpp:1.145 --- llvm/lib/Target/SparcV9/SparcV9InstrSelection.cpp:1.144 Thu Jun 17 13:17:08 2004 +++ llvm/lib/Target/SparcV9/SparcV9InstrSelection.cpp Tue Jul 27 12:43:23 2004 @@ -592,14 +592,13 @@ castDestType)); // Create the fpreg-to-intreg copy code - target.getInstrInfo()->CreateCodeToCopyFloatToInt(target, F, destForCast, - fpToIntCopyDest, mvec, mcfi); + CreateCodeToCopyFloatToInt(target, F, destForCast, fpToIntCopyDest, mvec, + mcfi); // Create the uint64_t to uint32_t conversion, if needed if (destI->getType() == Type::UIntTy) - target.getInstrInfo()-> - CreateZeroExtensionInstructions(target, F, fpToIntCopyDest, destI, - /*numLowBits*/ 32, mvec, mcfi); + CreateZeroExtensionInstructions(target, F, fpToIntCopyDest, destI, + /*numLowBits*/ 32, mvec, mcfi); } @@ -793,9 +792,8 @@ if (shiftDest != destVal) { // extend the sign-bit of the result into all upper bits of dest assert(8*opSize <= 32 && "Unexpected type size > 4 and < IntRegSize?"); - target.getInstrInfo()-> - CreateSignExtensionInstructions(target, F, shiftDest, destVal, - 8*opSize, mvec, mcfi); + CreateSignExtensionInstructions(target, F, shiftDest, destVal, 8*opSize, + mvec, mcfi); } } @@ -826,8 +824,9 @@ if (resultType->isInteger() || isa(resultType)) { bool isValidConst; - int64_t C = (int64_t) target.getInstrInfo()->ConvertConstantToIntType(target, - constOp, constOp->getType(), isValidConst); + int64_t C = (int64_t) ConvertConstantToIntType(target, constOp, + constOp->getType(), + isValidConst); if (isValidConst) { unsigned pow; bool needNeg = false; @@ -897,7 +896,7 @@ Constant* P = ConstantExpr::get(Instruction::Mul, cast(lval), cast(rval)); - target.getInstrInfo()->CreateCodeToLoadConst(target,F,P,destVal,mvec,mcfi); + CreateCodeToLoadConst (target, F, P, destVal, mvec, mcfi); } else if (isa(rval)) // rval is constant, but not lval CreateMulConstInstruction(target, F, lval, rval, destVal, mvec, mcfi); @@ -980,8 +979,9 @@ if (resultType->isInteger()) { unsigned pow; bool isValidConst; - int64_t C = (int64_t) target.getInstrInfo()->ConvertConstantToIntType(target, - constOp, constOp->getType(), isValidConst); + int64_t C = (int64_t) ConvertConstantToIntType(target, constOp, + constOp->getType(), + isValidConst); if (isValidConst) { bool needNeg = false; if (C < 0) { @@ -1089,7 +1089,7 @@ // compile time if the total size is a known constant. if (isa(numElementsVal)) { bool isValid; - int64_t numElem = (int64_t) target.getInstrInfo()-> + int64_t numElem = (int64_t) ConvertConstantToIntType(target, numElementsVal, numElementsVal->getType(), isValid); assert(isValid && "Unexpectedly large array dimension in alloca!"); @@ -1567,7 +1567,7 @@ retValToUse = new TmpInstruction(mcfi, retVal); // sign-extend retVal and put the result in the temporary reg. - target.getInstrInfo()->CreateSignExtensionInstructions + CreateSignExtensionInstructions (target, returnInstr->getParent()->getParent(), retVal, retValToUse, 8*retSize, mvec, mcfi); } @@ -1637,7 +1637,7 @@ if ((constVal->getType()->isInteger() || isa(constVal->getType())) - && target.getInstrInfo()->ConvertConstantToIntType(target, + && ConvertConstantToIntType(target, constVal, constVal->getType(), isValidConst) == 0 && isValidConst) { @@ -1889,15 +1889,15 @@ ? new TmpInstruction(mcfi, destType, opVal) : destI); - target.getInstrInfo()->CreateSignExtensionInstructions + CreateSignExtensionInstructions (target, currentFunc,opVal,signExtDest,extSourceInBits,mvec,mcfi); if (signAndZeroExtend) - target.getInstrInfo()->CreateZeroExtensionInstructions + CreateZeroExtensionInstructions (target, currentFunc, signExtDest, destI, 8*destSize, mvec, mcfi); } else if (zeroExtendOnly) { - target.getInstrInfo()->CreateZeroExtensionInstructions + CreateZeroExtensionInstructions (target, currentFunc, opVal, destI, extSourceInBits, mvec, mcfi); } else @@ -1955,7 +1955,7 @@ MachineCodeForInstruction::get(dest); srcForCast = new TmpInstruction(destMCFI, tmpTypeToUse, dest); - target.getInstrInfo()->CreateCodeToCopyIntToFloat(target, + CreateCodeToCopyIntToFloat(target, dest->getParent()->getParent(), leftVal, cast(srcForCast), mvec, destMCFI); @@ -2067,13 +2067,11 @@ MachineCodeForInstruction& mcfi=MachineCodeForInstruction::get(divI); divOp1ToUse = new TmpInstruction(mcfi, divOp1); divOp2ToUse = new TmpInstruction(mcfi, divOp2); - target.getInstrInfo()-> - CreateSignExtensionInstructions(target, + CreateSignExtensionInstructions(target, divI->getParent()->getParent(), divOp1, divOp1ToUse, 8*opSize, mvec, mcfi); - target.getInstrInfo()-> - CreateSignExtensionInstructions(target, + CreateSignExtensionInstructions(target, divI->getParent()->getParent(), divOp2, divOp2ToUse, 8*opSize, mvec, mcfi); @@ -2109,8 +2107,7 @@ unsigned opSize=target.getTargetData().getTypeSize(divOp2->getType()); if (opSize < 8) { divOpToUse = new TmpInstruction(mcfi, divOp2); - target.getInstrInfo()-> - CreateSignExtensionInstructions(target, + CreateSignExtensionInstructions(target, remI->getParent()->getParent(), divOp2, divOpToUse, 8*opSize, mvec, mcfi); @@ -2251,7 +2248,7 @@ if ((constVal->getType()->isInteger() || isa(constVal->getType())) - && target.getInstrInfo()->ConvertConstantToIntType(target, + && ConvertConstantToIntType(target, constVal, constVal->getType(), isValidConst) == 0 && isValidConst) { @@ -2328,10 +2325,10 @@ rightOpToUse = new TmpInstruction(mcfi, rightVal); // sign-extend each operand and put the result in the temporary reg. - target.getInstrInfo()->CreateSignExtensionInstructions + CreateSignExtensionInstructions (target, setCCInstr->getParent()->getParent(), leftVal, leftOpToUse, 8*opSize, mvec, mcfi); - target.getInstrInfo()->CreateSignExtensionInstructions + CreateSignExtensionInstructions (target, setCCInstr->getParent()->getParent(), rightVal, rightOpToUse, 8*opSize, mvec, mcfi); } @@ -2506,7 +2503,7 @@ TmpInstruction* argExtend = new TmpInstruction(mcfi, argVal); // sign-extend argVal and put the result in the temporary reg. - target.getInstrInfo()->CreateSignExtensionInstructions + CreateSignExtensionInstructions (target, currentFunc, argVal, argExtend, 8*argSize, mvec, mcfi); @@ -2826,8 +2823,7 @@ else { std::vector minstrVec; Instruction* instr = subtreeRoot->getInstruction(); - target.getInstrInfo()-> - CreateCopyInstructionsByType(target, + CreateCopyInstructionsByType(target, instr->getParent()->getParent(), instr->getOperand(forwardOperandNum), instr, minstrVec, Index: llvm/lib/Target/SparcV9/SparcV9PreSelection.cpp diff -u llvm/lib/Target/SparcV9/SparcV9PreSelection.cpp:1.36 llvm/lib/Target/SparcV9/SparcV9PreSelection.cpp:1.37 --- llvm/lib/Target/SparcV9/SparcV9PreSelection.cpp:1.36 Sat Jul 17 19:38:32 2004 +++ llvm/lib/Target/SparcV9/SparcV9PreSelection.cpp Tue Jul 27 12:43:23 2004 @@ -16,6 +16,7 @@ //===----------------------------------------------------------------------===// #include "SparcV9Internals.h" +#include "SparcV9InstrSelectionSupport.h" #include "llvm/Constants.h" #include "llvm/DerivedTypes.h" #include "llvm/iMemory.h" @@ -180,7 +181,7 @@ // load address of constant into a register, then load the constant // this is now done during instruction selection // the constant will live in the MachineConstantPool later on - } else if (instrInfo.ConstantMayNotFitInImmedField(CV, &I)) { + } else if (ConstantMayNotFitInImmedField(CV, &I)) { // put the constant into a virtual register using a cast CastInst* castI = new CastInst(CV, CV->getType(), "copyConst", &insertBefore); From gaeke at cs.uiuc.edu Tue Jul 27 12:43:34 2004 From: gaeke at cs.uiuc.edu (Brian Gaeke) Date: Tue, 27 Jul 2004 12:43:34 -0500 (CDT) Subject: [llvm-commits] CVS: llvm/lib/Target/SparcV9/InstrSelection/InstrSelectionSupport.cpp Message-ID: <200407271743.MAA10090@seraph.cs.uiuc.edu> Changes in directory llvm/lib/Target/SparcV9/InstrSelection: InstrSelectionSupport.cpp updated: 1.69 -> 1.70 --- Log message: Convert many of the virtual TargetInstrInfo methods used as helper functions in SparcV9InstrSelection and SparcV9PreSelection into regular old global functions. As it happens, none of them really have anything to do with TargetInstrInfo. --- Diffs of the changes: (+2 -4) Index: llvm/lib/Target/SparcV9/InstrSelection/InstrSelectionSupport.cpp diff -u llvm/lib/Target/SparcV9/InstrSelection/InstrSelectionSupport.cpp:1.69 llvm/lib/Target/SparcV9/InstrSelection/InstrSelectionSupport.cpp:1.70 --- llvm/lib/Target/SparcV9/InstrSelection/InstrSelectionSupport.cpp:1.69 Sat Jul 17 19:38:32 2004 +++ llvm/lib/Target/SparcV9/InstrSelection/InstrSelectionSupport.cpp Tue Jul 27 12:43:23 2004 @@ -41,8 +41,7 @@ MachineCodeForInstruction &mcfi = MachineCodeForInstruction::get(vmInstr); TmpInstruction* tmpReg = new TmpInstruction(mcfi, opValue); - target.getInstrInfo()->CreateCodeToLoadConst(target, F, opValue, tmpReg, - loadConstVec, mcfi); + CreateCodeToLoadConst(target, F, opValue, tmpReg, loadConstVec, mcfi); // Record the mapping from the tmp VM instruction to machine instruction. // Do this for all machine instructions that were not mapped to any @@ -96,8 +95,7 @@ // TargetInstrInfo::ConvertConstantToIntType() does the right conversions: bool isValidConstant; uint64_t valueToUse = - target.getInstrInfo()->ConvertConstantToIntType(target, val, val->getType(), - isValidConstant); + ConvertConstantToIntType(target, val, val->getType(), isValidConstant); if (! isValidConstant) return MachineOperand::MO_VirtualRegister; From gaeke at cs.uiuc.edu Tue Jul 27 12:43:34 2004 From: gaeke at cs.uiuc.edu (Brian Gaeke) Date: Tue, 27 Jul 2004 12:43:34 -0500 (CDT) Subject: [llvm-commits] CVS: llvm/lib/Target/SparcV9/RegAlloc/PhyRegAlloc.cpp Message-ID: <200407271743.MAA10104@seraph.cs.uiuc.edu> Changes in directory llvm/lib/Target/SparcV9/RegAlloc: PhyRegAlloc.cpp updated: 1.154 -> 1.155 --- Log message: TargetInstrInfo::getNOPOpCode() has been replaced by a reference to V9::NOP. --- Diffs of the changes: (+2 -1) Index: llvm/lib/Target/SparcV9/RegAlloc/PhyRegAlloc.cpp diff -u llvm/lib/Target/SparcV9/RegAlloc/PhyRegAlloc.cpp:1.154 llvm/lib/Target/SparcV9/RegAlloc/PhyRegAlloc.cpp:1.155 --- llvm/lib/Target/SparcV9/RegAlloc/PhyRegAlloc.cpp:1.154 Sat Jul 17 19:36:44 2004 +++ llvm/lib/Target/SparcV9/RegAlloc/PhyRegAlloc.cpp Tue Jul 27 12:43:24 2004 @@ -26,6 +26,7 @@ #include "RegAllocCommon.h" #include "RegClass.h" #include "../LiveVar/FunctionLiveVarInfo.h" +#include "../SparcV9InstrInfo.h" #include "llvm/Constants.h" #include "llvm/DerivedTypes.h" #include "llvm/iPHINode.h" @@ -550,7 +551,7 @@ // instruction out of the delay slot). On cond2 we need // to insert a nop in place of the moved instruction if (cond2) { - MBB.insert(MII, BuildMI(TM.getInstrInfo()->getNOPOpCode(),1)); + MBB.insert(MII, BuildMI(V9::NOP, 1)); } } else { From gaeke at cs.uiuc.edu Tue Jul 27 13:35:16 2004 From: gaeke at cs.uiuc.edu (Brian Gaeke) Date: Tue, 27 Jul 2004 13:35:16 -0500 (CDT) Subject: [llvm-commits] CVS: reopt/lib/LightWtProfiling/UnpackTraceFunction.cpp Message-ID: <200407271835.NAA10185@seraph.cs.uiuc.edu> Changes in directory reopt/lib/LightWtProfiling: UnpackTraceFunction.cpp updated: 1.103 -> 1.104 --- Log message: Save call-clobbered registers at trace boundaries if we see a call on the trace. Save g-registers around calls. --- Diffs of the changes: (+68 -5) Index: reopt/lib/LightWtProfiling/UnpackTraceFunction.cpp diff -u reopt/lib/LightWtProfiling/UnpackTraceFunction.cpp:1.103 reopt/lib/LightWtProfiling/UnpackTraceFunction.cpp:1.104 --- reopt/lib/LightWtProfiling/UnpackTraceFunction.cpp:1.103 Fri Jul 23 00:00:03 2004 +++ reopt/lib/LightWtProfiling/UnpackTraceFunction.cpp Tue Jul 27 13:35:05 2004 @@ -29,6 +29,7 @@ #include "../../../../lib/Target/SparcV9/RegAlloc/AllocInfo.h" #include "../../../../lib/Target/SparcV9/SparcV9RegInfo.h" #include "../../../../lib/Target/SparcV9/SparcV9TargetMachine.h" +#include "../../../../lib/Target/SparcV9/SparcV9InstrSelectionSupport.h" namespace llvm { @@ -83,8 +84,63 @@ fi != fe; ++fi) for (MachineBasicBlock::iterator bi = fi->begin (), be = fi->end (); bi != be; ++bi) { - if (bi->getOpcode () == V9::CALL) - RegsToSave.insert (SparcV9::o7); // save return-address register + if (bi->getOpcode () == V9::CALL) { + RegsToSave.insert (SparcV9::o0); + RegsToSave.insert (SparcV9::o1); + RegsToSave.insert (SparcV9::o2); + RegsToSave.insert (SparcV9::o3); + RegsToSave.insert (SparcV9::o4); + RegsToSave.insert (SparcV9::o5); + RegsToSave.insert (SparcV9::o7); + RegsToSave.insert (SparcV9::f0); + RegsToSave.insert (SparcV9::f1); + RegsToSave.insert (SparcV9::f2); + RegsToSave.insert (SparcV9::f3); + RegsToSave.insert (SparcV9::f4); + RegsToSave.insert (SparcV9::f5); + RegsToSave.insert (SparcV9::f6); + RegsToSave.insert (SparcV9::f7); + RegsToSave.insert (SparcV9::f8); + RegsToSave.insert (SparcV9::f9); + RegsToSave.insert (SparcV9::f10); + RegsToSave.insert (SparcV9::f11); + RegsToSave.insert (SparcV9::f12); + RegsToSave.insert (SparcV9::f13); + RegsToSave.insert (SparcV9::f14); + RegsToSave.insert (SparcV9::f15); + RegsToSave.insert (SparcV9::f16); + RegsToSave.insert (SparcV9::f17); + RegsToSave.insert (SparcV9::f18); + RegsToSave.insert (SparcV9::f19); + RegsToSave.insert (SparcV9::f20); + RegsToSave.insert (SparcV9::f21); + RegsToSave.insert (SparcV9::f22); + RegsToSave.insert (SparcV9::f23); + RegsToSave.insert (SparcV9::f24); + RegsToSave.insert (SparcV9::f25); + RegsToSave.insert (SparcV9::f26); + RegsToSave.insert (SparcV9::f27); + RegsToSave.insert (SparcV9::f28); + RegsToSave.insert (SparcV9::f29); + RegsToSave.insert (SparcV9::f30); + RegsToSave.insert (SparcV9::f31); + RegsToSave.insert (SparcV9::f32); + RegsToSave.insert (SparcV9::f34); + RegsToSave.insert (SparcV9::f36); + RegsToSave.insert (SparcV9::f38); + RegsToSave.insert (SparcV9::f40); + RegsToSave.insert (SparcV9::f42); + RegsToSave.insert (SparcV9::f44); + RegsToSave.insert (SparcV9::f46); + RegsToSave.insert (SparcV9::f48); + RegsToSave.insert (SparcV9::f50); + RegsToSave.insert (SparcV9::f52); + RegsToSave.insert (SparcV9::f54); + RegsToSave.insert (SparcV9::f56); + RegsToSave.insert (SparcV9::f58); + RegsToSave.insert (SparcV9::f60); + RegsToSave.insert (SparcV9::f62); + } for (unsigned oi = 0, oe = bi->getNumOperands (); oi != oe; ++oi) { const MachineOperand &MO = bi->getOperand (oi); if (MO.isDef ()) { @@ -307,11 +363,10 @@ UnpackTraceFunction::copyConstantToRegister (MachineFunction &MF, Constant *C, unsigned Reg, unsigned SpareReg, std::vector &mvec){ - const TargetInstrInfo &TII = *TM->getInstrInfo (); TmpInstruction *tmp = new TmpInstruction (C); MachineCodeForInstruction throwaway; - TII.CreateCodeToLoadConst (*TM, const_cast (MF.getFunction ()), - C, tmp, mvec, throwaway); + CreateCodeToLoadConst (*TM, const_cast (MF.getFunction ()), + C, tmp, mvec, throwaway); DEBUG (for (std::vector::iterator i = mvec.begin (), e = mvec.end (); i != e; ++i) @@ -615,6 +670,10 @@ // Let fp = g1. mvec.push_back (BuildMI (V9::ORr, 3).addMReg (TraceFP).addZImm (0) .addMReg (MatrixFP, MachineOperand::Def)); + unsigned R; + R = SparcV9::g2; TRI.cpReg2MemMI (mvec, R, sp, stackOffsetForReg (R), TRI.getRegType (R), g2); + R = SparcV9::g3; TRI.cpReg2MemMI (mvec, R, sp, stackOffsetForReg (R), TRI.getRegType (R), g2); + R = SparcV9::g4; TRI.cpReg2MemMI (mvec, R, sp, stackOffsetForReg (R), TRI.getRegType (R), g2); // Insert all the instrs into the MBB after the call instruction. for (std::vector::iterator ei = mvec.begin (), ee = mvec.end (); ei != ee; ++ei) { @@ -629,6 +688,9 @@ TRI.getRegType (MatrixFP), g2); TRI.cpMem2RegMI (mvec, sp, stackOffsetForReg (TraceFP), TraceFP, TRI.getRegType (TraceFP), g2); + R = SparcV9::g2; TRI.cpMem2RegMI (mvec, sp, stackOffsetForReg (R), R, TRI.getRegType (R), g2); + R = SparcV9::g3; TRI.cpMem2RegMI (mvec, sp, stackOffsetForReg (R), R, TRI.getRegType (R), g2); + R = SparcV9::g4; TRI.cpMem2RegMI (mvec, sp, stackOffsetForReg (R), R, TRI.getRegType (R), g2); // Insert all the instrs into the MBB after the call instruction. for (std::vector::iterator ei = mvec.begin (), ee = mvec.end (); ei != ee; ++ei) { @@ -674,6 +736,7 @@ DEBUG(std::cerr << "UnpackTraceFunction: Stack sizes: static = " << StaticStackSize << ", total = " << TotalStackSize << "\n"); + bool Changed = false; for (MachineFunction::iterator I = MF.begin (), E = MF.end (); I != E; ++I) Changed |= runOnMachineBasicBlock (*I); From lattner at cs.uiuc.edu Tue Jul 27 13:41:59 2004 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Tue, 27 Jul 2004 13:41:59 -0500 Subject: [llvm-commits] CVS: llvm/utils/NightlyTest.pl Message-ID: <200407271841.NAA02691@apoc.cs.uiuc.edu> Changes in directory llvm/utils: NightlyTest.pl updated: 1.61 -> 1.62 --- Log message: Fix the nightly tester to default to using gnuplot in /usr/bin --- Diffs of the changes: (+1 -1) Index: llvm/utils/NightlyTest.pl diff -u llvm/utils/NightlyTest.pl:1.61 llvm/utils/NightlyTest.pl:1.62 --- llvm/utils/NightlyTest.pl:1.61 Tue Jul 27 03:29:06 2004 +++ llvm/utils/NightlyTest.pl Tue Jul 27 13:41:49 2004 @@ -751,7 +751,7 @@ # # Rebuild the graphs now... # -$GNUPLOT = "/usr/dcs/software/supported/bin/gnuplot"; +$GNUPLOT = "/usr/bin/gnuplot"; $GNUPLOT = "gnuplot" if ! -x $GNUPLOT; system ("$GNUPLOT", $PlotScriptFilename); From gaeke at cs.uiuc.edu Tue Jul 27 13:47:31 2004 From: gaeke at cs.uiuc.edu (Brian Gaeke) Date: Tue, 27 Jul 2004 13:47:31 -0500 (CDT) Subject: [llvm-commits] CVS: reopt/include/reopt/UnpackTraceFunction.h Message-ID: <200407271847.NAA10664@seraph.cs.uiuc.edu> Changes in directory reopt/include/reopt: UnpackTraceFunction.h updated: 1.14 -> 1.15 --- Log message: Get rid of some unused flags. --- Diffs of the changes: (+0 -6) Index: reopt/include/reopt/UnpackTraceFunction.h diff -u reopt/include/reopt/UnpackTraceFunction.h:1.14 reopt/include/reopt/UnpackTraceFunction.h:1.15 --- reopt/include/reopt/UnpackTraceFunction.h:1.14 Fri Jul 23 00:00:01 2004 +++ reopt/include/reopt/UnpackTraceFunction.h Tue Jul 27 13:47:21 2004 @@ -46,12 +46,6 @@ std::map > AllocStates; - /// True IFF, in the current MachineFunction, register %fp contains - /// the traceFn's frame pointer (as opposed to matrixFn's.) - /// Only used in assertions. - bool fpIsTraceFP; - bool g3IsMatrixFP; - unsigned getStaticStackSize (MachineFunction &MF); unsigned stackOffsetForReg (const unsigned R) const; void findRegsToSave (MachineFunction &MF); From gaeke at cs.uiuc.edu Tue Jul 27 13:47:33 2004 From: gaeke at cs.uiuc.edu (Brian Gaeke) Date: Tue, 27 Jul 2004 13:47:33 -0500 (CDT) Subject: [llvm-commits] CVS: reopt/test/run-tests Message-ID: <200407271847.NAA10678@seraph.cs.uiuc.edu> Changes in directory reopt/test: run-tests updated: 1.15 -> 1.16 --- Log message: Endless test-case roulette --- Diffs of the changes: (+3 -3) Index: reopt/test/run-tests diff -u reopt/test/run-tests:1.15 reopt/test/run-tests:1.16 --- reopt/test/run-tests:1.15 Fri Jul 23 00:00:05 2004 +++ reopt/test/run-tests Tue Jul 27 13:47:23 2004 @@ -70,8 +70,8 @@ shootout) SUBDIR=SingleSource/Benchmarks/Shootout ;; stanford) SUBDIR=SingleSource/Benchmarks/Stanford ;; olden) SUBDIR=MultiSource/Benchmarks/Olden ;; - em3d) SUBDIR=MultiSource/Benchmarks/Olden/em3d ;; - bh) SUBDIR=MultiSource/Benchmarks/Olden/bh ;; + power) SUBDIR=MultiSource/Benchmarks/Olden/power ;; + tsp) SUBDIR=MultiSource/Benchmarks/Olden/tsp ;; mcf) SUBDIR=External/SPEC/CINT2000/181.mcf; spectest=1 ;; art) SUBDIR=External/SPEC/CFP2000/179.art; spectest=1;; @@ -100,7 +100,7 @@ reoptllcbinary=$1 grep STDIN_FILENAME Makefile grep RUN_OPTIONS Makefile - prog_args=`grep RUN_OPTIONS Makefile | cut -d= -f2-` + prog_args=`grep RUN_OPTIONS Makefile | cut -d= -f2- | head -1` gdbcmd="exec gdb --args $reoptllcbinary $prog_args" echo "running '$gdbcmd' in $fullsubdirpath" eval $gdbcmd From gaeke at cs.uiuc.edu Tue Jul 27 13:47:32 2004 From: gaeke at cs.uiuc.edu (Brian Gaeke) Date: Tue, 27 Jul 2004 13:47:32 -0500 (CDT) Subject: [llvm-commits] CVS: reopt/lib/TraceJIT/TraceJITOpts.cpp Message-ID: <200407271847.NAA10671@seraph.cs.uiuc.edu> Changes in directory reopt/lib/TraceJIT: TraceJITOpts.cpp updated: 1.2 -> 1.3 --- Log message: Switch passes. Instcombine+dce doesn't do much here. --- Diffs of the changes: (+1 -2) Index: reopt/lib/TraceJIT/TraceJITOpts.cpp diff -u reopt/lib/TraceJIT/TraceJITOpts.cpp:1.2 reopt/lib/TraceJIT/TraceJITOpts.cpp:1.3 --- reopt/lib/TraceJIT/TraceJITOpts.cpp:1.2 Wed Jul 21 15:18:45 2004 +++ reopt/lib/TraceJIT/TraceJITOpts.cpp Tue Jul 27 13:47:22 2004 @@ -23,8 +23,7 @@ void TraceJIT::addOptimizationPasses (FunctionPassManager &PM) { if (RunOptimizationPasses) { - PM.add(createInstructionCombiningPass()); - PM.add(createDeadCodeEliminationPass()); + PM.add(createLICMPass()); } } From gaeke at cs.uiuc.edu Tue Jul 27 14:37:48 2004 From: gaeke at cs.uiuc.edu (Brian Gaeke) Date: Tue, 27 Jul 2004 14:37:48 -0500 (CDT) Subject: [llvm-commits] CVS: llvm/lib/Target/SparcV9/SparcV9CodeEmitter.cpp Message-ID: <200407271937.OAA14279@seraph.cs.uiuc.edu> Changes in directory llvm/lib/Target/SparcV9: SparcV9CodeEmitter.cpp updated: 1.67 -> 1.68 --- Log message: Get rid of the (apparently non-working) filePrinterEmitter which is added in debug mode. Its only effect seems to be the creation of an empty file... --- Diffs of the changes: (+1 -3) Index: llvm/lib/Target/SparcV9/SparcV9CodeEmitter.cpp diff -u llvm/lib/Target/SparcV9/SparcV9CodeEmitter.cpp:1.67 llvm/lib/Target/SparcV9/SparcV9CodeEmitter.cpp:1.68 --- llvm/lib/Target/SparcV9/SparcV9CodeEmitter.cpp:1.67 Mon Jul 19 02:52:35 2004 +++ llvm/lib/Target/SparcV9/SparcV9CodeEmitter.cpp Tue Jul 27 14:37:37 2004 @@ -50,9 +50,7 @@ bool SparcV9TargetMachine::addPassesToEmitMachineCode(FunctionPassManager &PM, MachineCodeEmitter &MCE) { - MachineCodeEmitter *M = &MCE; - DEBUG(M = MachineCodeEmitter::createFilePrinterEmitter(MCE)); - PM.add(new SparcV9CodeEmitter(*this, *M)); + PM.add(new SparcV9CodeEmitter(*this, MCE)); PM.add(createSparcV9MachineCodeDestructionPass()); //Free stuff no longer needed return false; } From bocchino at cs.uiuc.edu Tue Jul 27 15:50:12 2004 From: bocchino at cs.uiuc.edu (Robert Bocchino) Date: Tue, 27 Jul 2004 15:50:12 -0500 Subject: [llvm-commits] CVS: llvm/test/Regression/Transforms/InstCombine/2004-07-27-ConstantExprMul.ll Message-ID: <200407272050.PAA25949@cypher.cs.uiuc.edu> Changes in directory llvm/test/Regression/Transforms/InstCombine: 2004-07-27-ConstantExprMul.ll added (r1.1) --- Log message: --- Diffs of the changes: (+8 -0) Index: llvm/test/Regression/Transforms/InstCombine/2004-07-27-ConstantExprMul.ll diff -c /dev/null llvm/test/Regression/Transforms/InstCombine/2004-07-27-ConstantExprMul.ll:1.1 *** /dev/null Tue Jul 27 15:50:12 2004 --- llvm/test/Regression/Transforms/InstCombine/2004-07-27-ConstantExprMul.ll Tue Jul 27 15:50:02 2004 *************** *** 0 **** --- 1,8 ---- + ; RUN: llvm-as < %s | opt -instcombine -disable-output + + %p = weak global int 0 + + int %test(int %x) { + %y = mul int %x, cast (int* %p to int) + ret int %y + } From bocchino at cs.uiuc.edu Tue Jul 27 16:02:32 2004 From: bocchino at cs.uiuc.edu (Robert Bocchino) Date: Tue, 27 Jul 2004 16:02:32 -0500 Subject: [llvm-commits] CVS: llvm/lib/Transforms/Scalar/InstructionCombining.cpp Message-ID: <200407272102.QAA26058@cypher.cs.uiuc.edu> Changes in directory llvm/lib/Transforms/Scalar: InstructionCombining.cpp updated: 1.232 -> 1.233 --- Log message: This change fixed a bug in the function visitMul. The prior version assumed that a constant on the RHS of a multiplication was either an IntConstant or an FPConstant. It checked for an IntConstant and then, if it did not find one, did a hard cast to an FPConstant. That code would crash if the RHS were a ConstantExpr that was neither an IntConstant nor an FPConstant. This version replaces the hard cast with a dyn_cast. It performs the same way for IntConstants and FPConstants but does nothing, instead of crashing, for constant expressions. The regression test for this change is 2004-07-27-ConstantExprMul.ll. --- Diffs of the changes: (+3 -3) Index: llvm/lib/Transforms/Scalar/InstructionCombining.cpp diff -u llvm/lib/Transforms/Scalar/InstructionCombining.cpp:1.232 llvm/lib/Transforms/Scalar/InstructionCombining.cpp:1.233 --- llvm/lib/Transforms/Scalar/InstructionCombining.cpp:1.232 Tue Jul 27 12:43:21 2004 +++ llvm/lib/Transforms/Scalar/InstructionCombining.cpp Tue Jul 27 16:02:21 2004 @@ -509,8 +509,9 @@ } // X + X --> X << 1 - if (I.getType()->isInteger()) + if (I.getType()->isInteger()) { if (Instruction *Result = AssociativeOpt(I, AddRHS(RHS))) return Result; + } // -A + B --> B - A if (Value *V = dyn_castNegVal(LHS)) @@ -745,8 +746,7 @@ if (uint64_t C = Log2(Val)) // Replace X*(2^C) with X << C return new ShiftInst(Instruction::Shl, Op0, ConstantUInt::get(Type::UByteTy, C)); - } else { - ConstantFP *Op1F = cast(Op1); + } else if (ConstantFP *Op1F = dyn_cast(Op1)) { if (Op1F->isNullValue()) return ReplaceInstUsesWith(I, Op1); From gaeke at cs.uiuc.edu Tue Jul 27 16:11:30 2004 From: gaeke at cs.uiuc.edu (Brian Gaeke) Date: Tue, 27 Jul 2004 16:11:30 -0500 (CDT) Subject: [llvm-commits] CVS: llvm/lib/Target/SparcV9/SparcV9PreSelection.cpp Message-ID: <200407272111.QAA07487@kain.cs.uiuc.edu> Changes in directory llvm/lib/Target/SparcV9: SparcV9PreSelection.cpp updated: 1.37 -> 1.38 --- Log message: This was the only user of TargetInstrInfo::ConstantTypeMustBeLoaded(). --- Diffs of the changes: (+5 -1) Index: llvm/lib/Target/SparcV9/SparcV9PreSelection.cpp diff -u llvm/lib/Target/SparcV9/SparcV9PreSelection.cpp:1.37 llvm/lib/Target/SparcV9/SparcV9PreSelection.cpp:1.38 --- llvm/lib/Target/SparcV9/SparcV9PreSelection.cpp:1.37 Tue Jul 27 12:43:23 2004 +++ llvm/lib/Target/SparcV9/SparcV9PreSelection.cpp Tue Jul 27 16:11:20 2004 @@ -154,6 +154,10 @@ } } +static inline bool ConstantTypeMustBeLoaded(const Type* CVT) { + assert(CVT->isPrimitiveType() || isa(CVT)); + return !(CVT->isIntegral() || isa(CVT)); +} //------------------------------------------------------------------------------ // Instruction visitor methods to perform instruction-specific operations @@ -177,7 +181,7 @@ // load-time constant: factor it out so we optimize as best we can Instruction* computeConst = DecomposeConstantExpr(CE, insertBefore); I.setOperand(opNum, computeConst); // replace expr operand with result - } else if (instrInfo.ConstantTypeMustBeLoaded(CV)) { + } else if (ConstantTypeMustBeLoaded(CV->getType())) { // load address of constant into a register, then load the constant // this is now done during instruction selection // the constant will live in the MachineConstantPool later on From bocchino at cs.uiuc.edu Tue Jul 27 16:06:44 2004 From: bocchino at cs.uiuc.edu (Robert Bocchino) Date: Tue, 27 Jul 2004 16:06:44 -0500 Subject: [llvm-commits] CVS: llvm/test/Regression/Transforms/InstCombine/2004-07-27-ConstantExprMul.ll Message-ID: <200407272106.QAA26158@cypher.cs.uiuc.edu> Changes in directory llvm/test/Regression/Transforms/InstCombine: 2004-07-27-ConstantExprMul.ll updated: 1.1 -> 1.2 --- Log message: This is the regression test for the change to InstructionCombining.cpp that I made today. It illustrates that the old version of the code would crash if the RHS of a multiplication were a ConstantExpr that could not be resolved into a ConstantInt or ConstantFP. --- Diffs of the changes: (+0 -0) From gaeke at cs.uiuc.edu Tue Jul 27 16:43:48 2004 From: gaeke at cs.uiuc.edu (Brian Gaeke) Date: Tue, 27 Jul 2004 16:43:48 -0500 (CDT) Subject: [llvm-commits] CVS: llvm/lib/Target/TargetInstrInfo.cpp Message-ID: <200407272143.QAA17704@kain.cs.uiuc.edu> Changes in directory llvm/lib/Target: TargetInstrInfo.cpp updated: 1.12 -> 1.13 --- Log message: ConstantTypeMustBeLoaded has been incorporated into SparcV9PreSelection, its only user. --- Diffs of the changes: (+0 -5) Index: llvm/lib/Target/TargetInstrInfo.cpp diff -u llvm/lib/Target/TargetInstrInfo.cpp:1.12 llvm/lib/Target/TargetInstrInfo.cpp:1.13 --- llvm/lib/Target/TargetInstrInfo.cpp:1.12 Sun Feb 29 00:31:32 2004 +++ llvm/lib/Target/TargetInstrInfo.cpp Tue Jul 27 16:43:38 2004 @@ -56,9 +56,4 @@ return false; } -bool TargetInstrInfo::ConstantTypeMustBeLoaded(const Constant* CV) const { - assert(CV->getType()->isPrimitiveType() || isa(CV->getType())); - return !(CV->getType()->isIntegral() || isa(CV->getType())); -} - } // End llvm namespace From gaeke at cs.uiuc.edu Tue Jul 27 16:43:48 2004 From: gaeke at cs.uiuc.edu (Brian Gaeke) Date: Tue, 27 Jul 2004 16:43:48 -0500 (CDT) Subject: [llvm-commits] CVS: llvm/include/llvm/Target/TargetInstrInfo.h Message-ID: <200407272143.QAA17697@kain.cs.uiuc.edu> Changes in directory llvm/include/llvm/Target: TargetInstrInfo.h updated: 1.58 -> 1.59 --- Log message: ConstantTypeMustBeLoaded has been incorporated into SparcV9PreSelection, its only user. --- Diffs of the changes: (+0 -11) Index: llvm/include/llvm/Target/TargetInstrInfo.h diff -u llvm/include/llvm/Target/TargetInstrInfo.h:1.58 llvm/include/llvm/Target/TargetInstrInfo.h:1.59 --- llvm/include/llvm/Target/TargetInstrInfo.h:1.58 Tue Jul 27 12:43:22 2004 +++ llvm/include/llvm/Target/TargetInstrInfo.h Tue Jul 27 16:43:37 2004 @@ -241,17 +241,6 @@ isSignExtended = get(opCode).immedIsSignExtended; return get(opCode).maxImmedConst; } - - //------------------------------------------------------------------------- - // Queries about representation of LLVM quantities (e.g., constants) - //------------------------------------------------------------------------- - - /// ConstantTypeMustBeLoaded - Test if this type of constant must be loaded - /// from memory into a register, i.e., cannot be set bitwise in register and - /// cannot use immediate fields of instructions. Note that this only makes - /// sense for primitive types. - /// - virtual bool ConstantTypeMustBeLoaded(const Constant* CV) const; }; } // End llvm namespace From lattner at cs.uiuc.edu Tue Jul 27 21:36:35 2004 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Tue, 27 Jul 2004 21:36:35 -0500 Subject: [llvm-commits] CVS: poolalloc/lib/PoolAllocate/TransformFunctionBody.cpp Message-ID: <200407280236.VAA24276@apoc.cs.uiuc.edu> Changes in directory poolalloc/lib/PoolAllocate: TransformFunctionBody.cpp updated: 1.26 -> 1.27 --- Log message: Remove CPR --- Diffs of the changes: (+2 -7) Index: poolalloc/lib/PoolAllocate/TransformFunctionBody.cpp diff -u poolalloc/lib/PoolAllocate/TransformFunctionBody.cpp:1.26 poolalloc/lib/PoolAllocate/TransformFunctionBody.cpp:1.27 --- poolalloc/lib/PoolAllocate/TransformFunctionBody.cpp:1.26 Wed Jul 7 01:22:54 2004 +++ poolalloc/lib/PoolAllocate/TransformFunctionBody.cpp Tue Jul 27 21:36:25 2004 @@ -113,9 +113,6 @@ // Returns the clone if V is a static function (not a pointer) and belongs // to an equivalence class i.e. is pool allocated Function* FuncTransform::retCloneIfFunc(Value *V) { - if (ConstantPointerRef *CPR = dyn_cast(V)) - V = CPR->getValue(); - if (Function *F = dyn_cast(V)) if (FuncInfo *FI = PAInfo.getFuncInfo(*F)) return FI->Clone; @@ -313,9 +310,7 @@ CF = dyn_cast(CastI->getOperand(0)); } else if (ConstantExpr *CE = dyn_cast(CV)) { if (CE->getOpcode() == Instruction::Cast) - if (ConstantPointerRef *CPR - = dyn_cast(CE->getOperand(0))) - CF = dyn_cast(CPR->getValue()); + CF = dyn_cast(CE->getOperand(0)); } } @@ -516,7 +511,7 @@ void FuncTransform::visitInstruction(Instruction &I) { for (unsigned i = 0, e = I.getNumOperands(); i != e; ++i) if (Function *clonedFunc = retCloneIfFunc(I.getOperand(i))) { - Constant *CF = ConstantPointerRef::get(clonedFunc); + Constant *CF = clonedFunc; I.setOperand(i, ConstantExpr::getCast(CF, I.getOperand(i)->getType())); } } From alkis at cs.uiuc.edu Wed Jul 28 05:09:07 2004 From: alkis at cs.uiuc.edu (Alkis Evlogimenos) Date: Wed, 28 Jul 2004 05:09:07 -0500 Subject: [llvm-commits] CVS: llvm-java/test/Makefile.test Message-ID: <200407281009.FAA05534@zion.cs.uiuc.edu> Changes in directory llvm-java/test: Makefile.test updated: 1.11 -> 1.12 --- Log message: Create some make output. --- Diffs of the changes: (+3 -0) Index: llvm-java/test/Makefile.test diff -u llvm-java/test/Makefile.test:1.11 llvm-java/test/Makefile.test:1.12 --- llvm-java/test/Makefile.test:1.11 Sat Jul 24 15:05:42 2004 +++ llvm-java/test/Makefile.test Wed Jul 28 05:08:57 2004 @@ -21,14 +21,17 @@ #rule to link in runtime to raw bytecode %.linked.bc: %.raw.bc $(LEVEL)/runtime/runtime.bc + @$(ECHO) Linking $< with the Java runtime $(LLVMTOOLCURRENT)/llvm-link$(EXEEXT) $^ -o $@ # rule to make assembly from bytecode %.dis-ll: %.bc + @$(ECHO) Disassembling $< $(LDIS) < $< > $@ # rule to compile java source Output/%.class: %.java Output/.dir + @$(ECHO) Compiling $< $(JAVAC) -d Output $< # rule to run a .class file with the jvm From alkis at cs.uiuc.edu Wed Jul 28 05:09:07 2004 From: alkis at cs.uiuc.edu (Alkis Evlogimenos) Date: Wed, 28 Jul 2004 05:09:07 -0500 Subject: [llvm-commits] CVS: llvm-java/Makefile.rules Message-ID: <200407281009.FAA05536@zion.cs.uiuc.edu> Changes in directory llvm-java: Makefile.rules updated: 1.10 -> 1.11 --- Log message: Create some make output. --- Diffs of the changes: (+1 -0) Index: llvm-java/Makefile.rules diff -u llvm-java/Makefile.rules:1.10 llvm-java/Makefile.rules:1.11 --- llvm-java/Makefile.rules:1.10 Sat Jul 24 11:36:57 2004 +++ llvm-java/Makefile.rules Wed Jul 28 05:08:57 2004 @@ -12,4 +12,5 @@ # rule to make bytecode from assembly %.bc: %.ll + @$(ECHO) Assembling $< to bytecode $(LLVMAS) < $< > $@ From alkis at cs.uiuc.edu Wed Jul 28 05:09:40 2004 From: alkis at cs.uiuc.edu (Alkis Evlogimenos) Date: Wed, 28 Jul 2004 05:09:40 -0500 Subject: [llvm-commits] CVS: llvm-java/runtime/Makefile Message-ID: <200407281009.FAA05577@zion.cs.uiuc.edu> Changes in directory llvm-java/runtime: Makefile updated: 1.1 -> 1.2 --- Log message: Add clean target. --- Diffs of the changes: (+4 -0) Index: llvm-java/runtime/Makefile diff -u llvm-java/runtime/Makefile:1.1 llvm-java/runtime/Makefile:1.2 --- llvm-java/runtime/Makefile:1.1 Thu Jul 15 06:28:44 2004 +++ llvm-java/runtime/Makefile Wed Jul 28 05:09:30 2004 @@ -11,3 +11,7 @@ include $(LEVEL)/Makefile.common all:: runtime.bc + +clean:: + rm -f *.bc + From alkis at cs.uiuc.edu Wed Jul 28 05:10:38 2004 From: alkis at cs.uiuc.edu (Alkis Evlogimenos) Date: Wed, 28 Jul 2004 05:10:38 -0500 Subject: [llvm-commits] CVS: llvm-java/lib/Compiler/Compiler.cpp Message-ID: <200407281010.FAA05624@zion.cs.uiuc.edu> Changes in directory llvm-java/lib/Compiler: Compiler.cpp updated: 1.70 -> 1.71 --- Log message: Untabify, cleanup whitespace and properly indent code. --- Diffs of the changes: (+5 -5) Index: llvm-java/lib/Compiler/Compiler.cpp diff -u llvm-java/lib/Compiler/Compiler.cpp:1.70 llvm-java/lib/Compiler/Compiler.cpp:1.71 --- llvm-java/lib/Compiler/Compiler.cpp:1.70 Sun Jul 25 05:37:29 2004 +++ llvm-java/lib/Compiler/Compiler.cpp Wed Jul 28 05:10:27 2004 @@ -221,7 +221,7 @@ return FunctionType::get(getTypeHelper(descr, ++i), params, false); } - // FIXME: Throw something + // FIXME: Throw something default: return NULL; } } @@ -232,7 +232,7 @@ ClassFile* cf = ClassFile::getClassFile(className); OpaqueType* newType = OpaqueType::get(); it = c2ciMap_.insert(it, std::make_pair(className, - ClassInfo(newType))); + ClassInfo(newType))); std::vector elements; if (ConstantClass* super = cf->getSuperClass()) elements.push_back @@ -440,7 +440,7 @@ // insert an opaque type for java.lang.Object. This is // defined in runtime.ll c2ciMap_.insert(std::make_pair("java/lang/Object", - ClassInfo(OpaqueType::get()))); + ClassInfo(OpaqueType::get()))); module.addTypeName("java/lang/Object", getClassInfo("java/lang/Object").type); @@ -746,7 +746,7 @@ c = new CallInst(module_->getOrInsertFunction ("llvm.isunordered", Type::BoolTy, v1->getType(), v2->getType(), 0), - v1, v2, TMP, getBBAt(bcI)); + v1, v2, TMP, getBBAt(bcI)); r = new SelectInst(c, ConstantSInt::get(Type::IntTy, valueIfUnordered), r, TMP, getBBAt(bcI)); @@ -808,7 +808,7 @@ void do_putstatic(unsigned bcI, unsigned index) { Value* v = opStack_.top(); opStack_.pop(); - new StoreInst(v, getStaticField(index), getBBAt(bcI)); + new StoreInst(v, getStaticField(index), getBBAt(bcI)); } void do_getfield(unsigned bcI, unsigned index) { From gaeke at cs.uiuc.edu Wed Jul 28 13:00:53 2004 From: gaeke at cs.uiuc.edu (Brian Gaeke) Date: Wed, 28 Jul 2004 13:00:53 -0500 (CDT) Subject: [llvm-commits] CVS: reopt/lib/LightWtProfiling/UnpackTraceFunction.cpp Message-ID: <200407281800.NAA29982@seraph.cs.uiuc.edu> Changes in directory reopt/lib/LightWtProfiling: UnpackTraceFunction.cpp updated: 1.104 -> 1.105 --- Log message: Tighten up the sequence that saves registers when we see a call instr. Don't save g registers around calls. --- Diffs of the changes: (+22 -64) Index: reopt/lib/LightWtProfiling/UnpackTraceFunction.cpp diff -u reopt/lib/LightWtProfiling/UnpackTraceFunction.cpp:1.104 reopt/lib/LightWtProfiling/UnpackTraceFunction.cpp:1.105 --- reopt/lib/LightWtProfiling/UnpackTraceFunction.cpp:1.104 Tue Jul 27 13:35:05 2004 +++ reopt/lib/LightWtProfiling/UnpackTraceFunction.cpp Wed Jul 28 13:00:42 2004 @@ -78,69 +78,14 @@ /// void UnpackTraceFunction::findRegsToSave (MachineFunction &MF) { const SparcV9RegInfo &TRI = *TM->getRegInfo (); - bool intCCRegSeen = false, floatCCRegSeen = false; + bool intCCRegSeen = false, floatCCRegSeen = false, callSeen = false; RegsToSave.clear (); for (MachineFunction::iterator fi = MF.begin (), fe = MF.end (); fi != fe; ++fi) for (MachineBasicBlock::iterator bi = fi->begin (), be = fi->end (); bi != be; ++bi) { - if (bi->getOpcode () == V9::CALL) { - RegsToSave.insert (SparcV9::o0); - RegsToSave.insert (SparcV9::o1); - RegsToSave.insert (SparcV9::o2); - RegsToSave.insert (SparcV9::o3); - RegsToSave.insert (SparcV9::o4); - RegsToSave.insert (SparcV9::o5); - RegsToSave.insert (SparcV9::o7); - RegsToSave.insert (SparcV9::f0); - RegsToSave.insert (SparcV9::f1); - RegsToSave.insert (SparcV9::f2); - RegsToSave.insert (SparcV9::f3); - RegsToSave.insert (SparcV9::f4); - RegsToSave.insert (SparcV9::f5); - RegsToSave.insert (SparcV9::f6); - RegsToSave.insert (SparcV9::f7); - RegsToSave.insert (SparcV9::f8); - RegsToSave.insert (SparcV9::f9); - RegsToSave.insert (SparcV9::f10); - RegsToSave.insert (SparcV9::f11); - RegsToSave.insert (SparcV9::f12); - RegsToSave.insert (SparcV9::f13); - RegsToSave.insert (SparcV9::f14); - RegsToSave.insert (SparcV9::f15); - RegsToSave.insert (SparcV9::f16); - RegsToSave.insert (SparcV9::f17); - RegsToSave.insert (SparcV9::f18); - RegsToSave.insert (SparcV9::f19); - RegsToSave.insert (SparcV9::f20); - RegsToSave.insert (SparcV9::f21); - RegsToSave.insert (SparcV9::f22); - RegsToSave.insert (SparcV9::f23); - RegsToSave.insert (SparcV9::f24); - RegsToSave.insert (SparcV9::f25); - RegsToSave.insert (SparcV9::f26); - RegsToSave.insert (SparcV9::f27); - RegsToSave.insert (SparcV9::f28); - RegsToSave.insert (SparcV9::f29); - RegsToSave.insert (SparcV9::f30); - RegsToSave.insert (SparcV9::f31); - RegsToSave.insert (SparcV9::f32); - RegsToSave.insert (SparcV9::f34); - RegsToSave.insert (SparcV9::f36); - RegsToSave.insert (SparcV9::f38); - RegsToSave.insert (SparcV9::f40); - RegsToSave.insert (SparcV9::f42); - RegsToSave.insert (SparcV9::f44); - RegsToSave.insert (SparcV9::f46); - RegsToSave.insert (SparcV9::f48); - RegsToSave.insert (SparcV9::f50); - RegsToSave.insert (SparcV9::f52); - RegsToSave.insert (SparcV9::f54); - RegsToSave.insert (SparcV9::f56); - RegsToSave.insert (SparcV9::f58); - RegsToSave.insert (SparcV9::f60); - RegsToSave.insert (SparcV9::f62); - } + if (bi->getOpcode () == V9::CALL) + callSeen = true; for (unsigned oi = 0, oe = bi->getNumOperands (); oi != oe; ++oi) { const MachineOperand &MO = bi->getOperand (oi); if (MO.isDef ()) { @@ -157,6 +102,25 @@ } } } + + if (callSeen) { + static const unsigned CallerSavedRegs[] = { SparcV9::o0, SparcV9::o1, + SparcV9::o2, SparcV9::o3, SparcV9::o4, SparcV9::o5, SparcV9::o7, + SparcV9::g2, SparcV9::g3, SparcV9::g4, SparcV9::g5, + SparcV9::f0, SparcV9::f1, SparcV9::f2, SparcV9::f3, SparcV9::f4, + SparcV9::f5, SparcV9::f6, SparcV9::f7, SparcV9::f8, SparcV9::f9, + SparcV9::f10, SparcV9::f11, SparcV9::f12, SparcV9::f13, SparcV9::f14, + SparcV9::f15, SparcV9::f16, SparcV9::f17, SparcV9::f18, SparcV9::f19, + SparcV9::f20, SparcV9::f21, SparcV9::f22, SparcV9::f23, SparcV9::f24, + SparcV9::f25, SparcV9::f26, SparcV9::f27, SparcV9::f28, SparcV9::f29, + SparcV9::f30, SparcV9::f31, SparcV9::f32, SparcV9::f34, SparcV9::f36, + SparcV9::f38, SparcV9::f40, SparcV9::f42, SparcV9::f44, SparcV9::f46, + SparcV9::f48, SparcV9::f50, SparcV9::f52, SparcV9::f54, SparcV9::f56, + SparcV9::f58, SparcV9::f60, SparcV9::f62 }; + RegsToSave.insert (CallerSavedRegs, CallerSavedRegs + + sizeof (CallerSavedRegs) / sizeof (CallerSavedRegs[0])); + } + RegsToSave.insert (MatrixFP); // Deal with some sparc lunacy: If any of the floatcc regs are used, then we @@ -671,9 +635,6 @@ mvec.push_back (BuildMI (V9::ORr, 3).addMReg (TraceFP).addZImm (0) .addMReg (MatrixFP, MachineOperand::Def)); unsigned R; - R = SparcV9::g2; TRI.cpReg2MemMI (mvec, R, sp, stackOffsetForReg (R), TRI.getRegType (R), g2); - R = SparcV9::g3; TRI.cpReg2MemMI (mvec, R, sp, stackOffsetForReg (R), TRI.getRegType (R), g2); - R = SparcV9::g4; TRI.cpReg2MemMI (mvec, R, sp, stackOffsetForReg (R), TRI.getRegType (R), g2); // Insert all the instrs into the MBB after the call instruction. for (std::vector::iterator ei = mvec.begin (), ee = mvec.end (); ei != ee; ++ei) { @@ -688,9 +649,6 @@ TRI.getRegType (MatrixFP), g2); TRI.cpMem2RegMI (mvec, sp, stackOffsetForReg (TraceFP), TraceFP, TRI.getRegType (TraceFP), g2); - R = SparcV9::g2; TRI.cpMem2RegMI (mvec, sp, stackOffsetForReg (R), R, TRI.getRegType (R), g2); - R = SparcV9::g3; TRI.cpMem2RegMI (mvec, sp, stackOffsetForReg (R), R, TRI.getRegType (R), g2); - R = SparcV9::g4; TRI.cpMem2RegMI (mvec, sp, stackOffsetForReg (R), R, TRI.getRegType (R), g2); // Insert all the instrs into the MBB after the call instruction. for (std::vector::iterator ei = mvec.begin (), ee = mvec.end (); ei != ee; ++ei) { From gaeke at cs.uiuc.edu Wed Jul 28 14:24:58 2004 From: gaeke at cs.uiuc.edu (Brian Gaeke) Date: Wed, 28 Jul 2004 14:24:58 -0500 (CDT) Subject: [llvm-commits] CVS: llvm/lib/CodeGen/InstrSched/InstrScheduling.cpp Message-ID: <200407281924.OAA12191@kain.cs.uiuc.edu> Changes in directory llvm/lib/CodeGen/InstrSched: InstrScheduling.cpp updated: 1.73 -> 1.74 --- Log message: TargetInstrInfo::hasOperandInterlock() is always true, because it is never overridden by any target. --- Diffs of the changes: (+1 -10) Index: llvm/lib/CodeGen/InstrSched/InstrScheduling.cpp diff -u llvm/lib/CodeGen/InstrSched/InstrScheduling.cpp:1.73 llvm/lib/CodeGen/InstrSched/InstrScheduling.cpp:1.74 --- llvm/lib/CodeGen/InstrSched/InstrScheduling.cpp:1.73 Thu Jul 15 19:04:54 2004 +++ llvm/lib/CodeGen/InstrSched/InstrScheduling.cpp Wed Jul 28 14:24:48 2004 @@ -1045,11 +1045,6 @@ && (*EI)->getDepType() == SchedGraphEdge::CtrlDep) return false; - // for now, don't put an instruction that does not have operand - // interlocks in the delay slot of a branch - if (! S.getInstrInfo().hasOperandInterlock(node->getOpcode())) - return false; - // Finally, if the instruction precedes the branch, we make sure the // instruction can be reordered relative to the branch. We simply check // if the instr. has only 1 outgoing edge, viz., a CD edge to the branch. @@ -1326,11 +1321,7 @@ const SchedGraphNode* dnode = delayNodeVec[i]; if ( ! S.isScheduled(dnode) && S.schedInfo.instrCanUseSlot(dnode->getOpcode(), nextSlot) - && instrIsFeasible(S, dnode->getOpcode())) - { - assert(S.getInstrInfo().hasOperandInterlock(dnode->getOpcode()) - && "Instructions without interlocks not yet supported " - "when filling branch delay slots"); + && instrIsFeasible(S, dnode->getOpcode())) { S.scheduleInstr(dnode, nextSlot, nextTime); break; } From gaeke at cs.uiuc.edu Wed Jul 28 14:24:58 2004 From: gaeke at cs.uiuc.edu (Brian Gaeke) Date: Wed, 28 Jul 2004 14:24:58 -0500 (CDT) Subject: [llvm-commits] CVS: llvm/include/llvm/Target/TargetInstrInfo.h Message-ID: <200407281924.OAA12184@kain.cs.uiuc.edu> Changes in directory llvm/include/llvm/Target: TargetInstrInfo.h updated: 1.59 -> 1.60 --- Log message: TargetInstrInfo::hasOperandInterlock() is always true, because it is never overridden by any target. --- Diffs of the changes: (+2 -9) Index: llvm/include/llvm/Target/TargetInstrInfo.h diff -u llvm/include/llvm/Target/TargetInstrInfo.h:1.59 llvm/include/llvm/Target/TargetInstrInfo.h:1.60 --- llvm/include/llvm/Target/TargetInstrInfo.h:1.59 Tue Jul 27 16:43:37 2004 +++ llvm/include/llvm/Target/TargetInstrInfo.h Wed Jul 28 14:24:48 2004 @@ -194,18 +194,11 @@ bool isDummyPhiInstr(MachineOpCode opCode) const { return get(opCode).Flags & M_DUMMY_PHI_FLAG; } - // Check if an instruction can be issued before its operands are ready, - // or if a subsequent instruction that uses its result can be issued - // before the results are ready. - // Default to true since most instructions on many architectures allow this. - // - virtual bool hasOperandInterlock(MachineOpCode opCode) const { - return true; - } + virtual bool hasResultInterlock(MachineOpCode opCode) const { return true; } - + // // Latencies for individual instructions and instruction pairs // From brukman at cs.uiuc.edu Wed Jul 28 17:09:39 2004 From: brukman at cs.uiuc.edu (Misha Brukman) Date: Wed, 28 Jul 2004 17:09:39 -0500 Subject: [llvm-commits] CVS: llvm/docs/TableGenFundamentals.html Message-ID: <200407282209.RAA10658@zion.cs.uiuc.edu> Changes in directory llvm/docs: TableGenFundamentals.html updated: 1.10 -> 1.11 --- Log message: Put around verbatim code elements. --- Diffs of the changes: (+18 -19) Index: llvm/docs/TableGenFundamentals.html diff -u llvm/docs/TableGenFundamentals.html:1.10 llvm/docs/TableGenFundamentals.html:1.11 --- llvm/docs/TableGenFundamentals.html:1.10 Tue Jul 27 02:49:39 2004 +++ llvm/docs/TableGenFundamentals.html Wed Jul 28 17:09:29 2004 @@ -296,26 +296,25 @@ supported include:

      -
    • ? - Uninitialized field.
      • -
    • 0b1001011 - Binary integer value.
      • -
    • 07654321 - Octal integer value (indicated by a leading 0).
      • -
    • 7 - Decimal integer value.
      • -
    • 0x7F - Hexadecimal integer value.
      • -
    • "foo" - String value.
      • -
    • [{ .... }] - Code fragment.
      • -
    • [ X, Y, Z ] - List value.
      • -
    • { a, b, c } - Initializer for a "bits<3>" value.
      • -
    • value - Value reference.
      • -
    • value{17} - Access to one or more bits of a value.
      • -
    • DEF - Reference to a record definition.
      • -
    • X.Y - Reference to the subfield of a value.
      • +
    • ? - uninitialized field
      • +
    • 0b1001011 - binary integer value
      • +
    • 07654321 - octal integer value (indicated by a leading 0)
      • +
    • 7 - decimal integer value
      • +
    • 0x7F - hexadecimal integer value
      • +
    • "foo" - string value
      • +
    • [{ ... }] - code fragment
      • +
    • [ X, Y, Z ] - list value.
      • +
    • { a, b, c } - initializer for a "bits<3>" value
      • +
    • value - value reference
      • +
    • value{17} - access to one bit of a value
      • +
    • value{15-17} - access to multiple bits of a value
      • +
    • DEF - reference to a record definition
      • +
    • X.Y - reference to the subfield of a value
    • list[4-7,17,2-3] - A slice of the 'list' list, including elements 4,5,6,7,17,2, and 3 from it. Elements may be included multiple times.
      • - -
    • (DEF a, b) - A dag value. The first element is required to be a record -definition, the remaining elements in the list may be arbitrary other values, -including nested 'dag' values.
      • - +
    • (DEF a, b) - a dag value. The first element is required to be a +record definition, the remaining elements in the list may be arbitrary other +values, including nested `dag' values.

    Note that all of the values have rules specifying how they convert to values @@ -559,7 +558,7 @@ Chris Lattner
    LLVM Compiler Infrastructure
    - Last modified: $Date: 2004/07/27 07:49:39 $ + Last modified: $Date: 2004/07/28 22:09:29 $ From brukman at cs.uiuc.edu Wed Jul 28 17:18:43 2004 From: brukman at cs.uiuc.edu (Misha Brukman) Date: Wed, 28 Jul 2004 17:18:43 -0500 Subject: [llvm-commits] CVS: llvm/docs/AliasAnalysis.html Message-ID: <200407282218.RAA10830@zion.cs.uiuc.edu> Changes in directory llvm/docs: AliasAnalysis.html updated: 1.23 -> 1.24 --- Log message: * Use the doc_code class for code listings to make it stand out from text * Wrap text in soft, comfortable

    s and

    s * Wrap lines at 80 cols --- Diffs of the changes: (+65 -56) Index: llvm/docs/AliasAnalysis.html diff -u llvm/docs/AliasAnalysis.html:1.23 llvm/docs/AliasAnalysis.html:1.24 --- llvm/docs/AliasAnalysis.html:1.23 Tue Jul 27 02:50:07 2004 +++ llvm/docs/AliasAnalysis.html Wed Jul 28 17:18:33 2004 @@ -134,16 +134,18 @@ important for correct Alias Analyses. For example, consider this (silly, but possible) C code:

    +
    -  int i;
-  char C[2];
-  char A[10]; 
-  /* ... */
-  for (i = 0; i != 10; ++i) {
-    C[0] = A[i];          /* One byte store */
-    C[1] = A[9-i];        /* One byte store */
-  }
+int i;
+char C[2];
+char A[10]; 
+/* ... */
+for (i = 0; i != 10; ++i) {
+  C[0] = A[i];          /* One byte store */
+  C[1] = A[9-i];        /* One byte store */
+}
    +

    In this case, the basicaa pass will disambiguate the stores to C[0] and C[1] because they are accesses to two distinct @@ -151,16 +153,18 @@ LICM pass can use store motion to remove the stores from the loop. In constrast, the following code:

    +
    -  int i;
-  char C[2];
-  char A[10]; 
-  /* ... */
-  for (i = 0; i != 10; ++i) {
-    ((short*)C)[0] = A[i];  /* Two byte store! */
-    C[1] = A[9-i];          /* One byte store */
-  }
+int i;
+char C[2];
+char A[10]; 
+/* ... */
+for (i = 0; i != 10; ++i) {
+  ((short*)C)[0] = A[i];  /* Two byte store! */
+  C[1] = A[9-i];          /* One byte store */
+}
    +

    In this case, the two stores to C do alias each other, because the access to the &C[0] element is a two byte access. If size information wasn't @@ -361,25 +365,29 @@ declaring any pass dependencies your pass has. Thus you should have something like this:

    +
    -    void getAnalysisUsage(AnalysisUsage &AU) const {
-      AliasAnalysis::getAnalysisUsage(AU);
-      // declare your dependencies here.
-    }
+void getAnalysisUsage(AnalysisUsage &AU) const {
+  AliasAnalysis::getAnalysisUsage(AU);
+  // declare your dependencies here.
+}
    +

    Additionally, your must invoke the InitializeAliasAnalysis method from your analysis run method (run for a Pass, runOnFunction for a FunctionPass, or InitializePass for an ImmutablePass). For example (as part of a Pass):

    +
    -    bool run(Module &M) {
-      InitializeAliasAnalysis(this);
-      // Perform analysis here...
-      return false;
-    }
+bool run(Module &M) {
+  InitializeAliasAnalysis(this);
+  // Perform analysis here...
+  return false;
+}
    +
    @@ -419,17 +427,19 @@ paths that return a conservative MayAlias or Mod/Ref result, simply return whatever the superclass computes. For example:

    +
    -  AliasAnalysis::AliasResult alias(const Value *V1, unsigned V1Size,
-                                   const Value *V2, unsigned V2Size) {
-    if (...)
-      return NoAlias;
-    ...
-
-    // Couldn't determine a must or no-alias result.
-    return AliasAnalysis::alias(V1, V1Size, V2, V2Size);
-  }
+AliasAnalysis::AliasResult alias(const Value *V1, unsigned V1Size,
+                                 const Value *V2, unsigned V2Size) {
+  if (...)
+    return NoAlias;
+  ...
+
+  // Couldn't determine a must or no-alias result.
+  return AliasAnalysis::alias(V1, V1Size, V2, V2Size);
+}
    +

    In addition to analysis queries, you must make sure to unconditionally pass LLVM update notification methods to the superclass as @@ -473,7 +483,6 @@ any entries for the specified value, if they exist.

    -
    The copyValue method
    @@ -485,7 +494,6 @@ new value has exactly the same properties as the value being copied. -
    The replaceWithNewValue method
    @@ -549,8 +557,8 @@

    Many transformations need information about alias sets that are active in some scope, rather than information about pairwise aliasing. The AliasSetTracker class is used -to efficiently build these Alias Sets from the pairwise alias analysis +href="/doxygen/classllvm_1_1AliasSetTracker.html">AliasSetTracker class +is used to efficiently build these Alias Sets from the pairwise alias analysis information provided by the AliasAnalysis interface.

    First you initialize the AliasSetTracker by using the "add" methods @@ -602,7 +610,6 @@ -

    Using the AliasAnalysis interface directly @@ -662,7 +669,6 @@
    -
    The -basicaa pass @@ -845,8 +851,8 @@
    -

    -The -load-vn pass uses alias analysis to "value + +

    The -load-vn pass uses alias analysis to "value number" loads and pointers values, which is used by the GCSE pass to eliminate instructions. The -load-vn pass relies on alias information and must-alias information. This combination of passes can make the following @@ -864,18 +870,19 @@

    - - -
    - Clients for debugging and evaluation of implementations + Clients for debugging and evaluation of + implementations
    -These passes are useful for evaluating the various alias analysis +
    + +

    These passes are useful for evaluating the various alias analysis implementations. You can use them with commands like 'opt -anders-aa -ds-aa --aa-eval foo.bc -disable-output -stats'. +-aa-eval foo.bc -disable-output -stats'.

    +
    @@ -900,17 +907,19 @@

    The -count-aa pass is useful to see how many queries a particular -pass is making and what responses are returned by the alias analysis. An -example usage is:

    +pass is making and what responses are returned by the alias analysis. As an +example,

    +
    -  $ opt -basicaa -count-aa -ds-aa -count-aa -licm
+% opt -basicaa -count-aa -ds-aa -count-aa -licm
    +
    -

    Which will print out how many queries (and what responses are returned) by -the -licm pass (of the -ds-aa pass) and how many queries are -made of the -basicaa pass by the -ds-aa pass. This can be -useful when debugging a transformation or an alias analysis implementation.

    +

    will print out how many queries (and what responses are returned) by the +-licm pass (of the -ds-aa pass) and how many queries are made +of the -basicaa pass by the -ds-aa pass. This can be useful +when debugging a transformation or an alias analysis implementation.

    @@ -940,7 +949,7 @@ Chris Lattner
    LLVM Compiler Infrastructure
    - Last modified: $Date: 2004/07/27 07:50:07 $ + Last modified: $Date: 2004/07/28 22:18:33 $ From brukman at cs.uiuc.edu Wed Jul 28 17:32:04 2004 From: brukman at cs.uiuc.edu (Misha Brukman) Date: Wed, 28 Jul 2004 17:32:04 -0500 Subject: [llvm-commits] CVS: llvm/docs/CodingStandards.html Message-ID: <200407282232.RAA11059@zion.cs.uiuc.edu> Changes in directory llvm/docs: CodingStandards.html updated: 1.18 -> 1.19 --- Log message: * Wrap code listings in
    * Wrap keywords in * Wrap lines at 80 cols --- Diffs of the changes: (+50 -39) Index: llvm/docs/CodingStandards.html diff -u llvm/docs/CodingStandards.html:1.18 llvm/docs/CodingStandards.html:1.19 --- llvm/docs/CodingStandards.html:1.18 Mon Jun 21 23:24:55 2004 +++ llvm/docs/CodingStandards.html Wed Jul 28 17:31:54 2004 @@ -122,6 +122,7 @@ file header format. The standard format for the LLVM source tree looks like this:

    +
     //===-- llvm/Instruction.h - Instruction class definition -------*- C++ -*-===//
 // 
@@ -136,8 +137,8 @@
 // base class for all of the VM instructions.
 //
 //===----------------------------------------------------------------------===//
-
    +

    A few things to note about this particular format: The "-*- C++ -*-" string on the first line is there to tell Emacs that the source file @@ -211,21 +212,22 @@

    Immediately after the header file comment (and include guards if working on a header file), the minimal list of #includes required by the file should -be listed. We prefer these #includes to be listed in this order:

    +href="#hl_dontinclude">minimal list of #includes required by the +file should be listed. We prefer these #includes to be listed in this +order:

    1. Main Module header
    2. Local/Private Headers
      3. -
    3. llvm/*
      4. -
    4. llvm/Analysis/*
      5. -
    5. llvm/Assembly/*
      6. -
    6. llvm/Bytecode/*
      7. -
    7. llvm/CodeGen/*
      8. +
    8. llvm/*
      9. +
    9. llvm/Analysis/*
      10. +
    10. llvm/Assembly/*
      11. +
    11. llvm/Bytecode/*
      12. +
    12. llvm/CodeGen/*
    13. ...
      14. -
    14. Support/*
      15. -
    15. Config/*
      16. -
    16. System #includes
      17. +
    17. Support/*
      18. +
    18. Config/*
      19. +
    19. System #includes

    ... and each catagory should be sorted by name.

    @@ -315,22 +317,26 @@ syntax of the code slightly. For example, an warning that annoys me occurs when I write code like this:

    +
    -  if (V = getValue()) {
-    ..
-  }
+if (V = getValue()) {
+  ...
+}
    +

    gcc will warn me that I probably want to use the == operator, and that I probably mistyped it. In most cases, I haven't, and I really don't want the spurious errors. To fix this particular problem, I rewrite the code like this:

    +
    -  if ((V = getValue())) {
-    ..
-  }
+if ((V = getValue())) {
+  ...
+}
    +

    ...which shuts gcc up. Any gcc warning that annoys you can be fixed by massaging the code appropriately.

    @@ -477,26 +483,30 @@ helps the poor debugging make sense of why an assertion is being made and enforced, and hopefully what to do about it. Here is one complete example:

    +
    -  inline Value *getOperand(unsigned i) { 
-    assert(i < Operands.size() && "getOperand() out of range!");
-    return Operands[i]; 
-  }
+inline Value *getOperand(unsigned i) { 
+  assert(i < Operands.size() && "getOperand() out of range!");
+  return Operands[i]; 
+}
    +

    Here are some examples:

    +
    -  assert(Ty->isPointerType() && "Can't allocate a non pointer type!");
+assert(Ty->isPointerType() && "Can't allocate a non pointer type!");
 
-  assert((Opcode == Shl || Opcode == Shr) && "ShiftInst Opcode invalid!");
+assert((Opcode == Shl || Opcode == Shr) && "ShiftInst Opcode invalid!");
 
-  assert(idx < getNumSuccessors() && "Successor # out of range!");
+assert(idx < getNumSuccessors() && "Successor # out of range!");
 
-  assert(V1.getType() == V2.getType() && "Constant types must be identical!");
+assert(V1.getType() == V2.getType() && "Constant types must be identical!");
 
-  assert(isa<PHINode>(Succ->front()) && "Only works on PHId BBs!");
+assert(isa<PHINode>(Succ->front()) && "Only works on PHId BBs!");
    +

    You get the idea...

    @@ -510,9 +520,9 @@
    -

    Hard fast rule: Preincrement (++X) may be no slower than postincrement (X++) -and could very well be a lot faster than it. Use preincrementation whenever -possible.

    +

    Hard fast rule: Preincrement (++X) may be no slower than +postincrement (X++) and could very well be a lot faster than it. Use +preincrementation whenever possible.

    The semantics of postincrement include making a copy of the value being incremented, returning it, and then preincrementing the "work value". For @@ -523,7 +533,6 @@

    -
    Avoid std::endl @@ -535,13 +544,15 @@ to the output stream specified. In addition to doing this, however, it also flushes the output stream. In other words, these are equivalent:

    +
    -  std::cout << std::endl;
-  std::cout << "\n" << std::flush;
+std::cout << std::endl;
+std::cout << '\n' << std::flush;
    +

    Most of the time, you probably have no reason to flush the output stream, so -it's better to use a literal "\n".

    +it's better to use a literal '\n'.

    @@ -552,11 +563,11 @@
    -

    C++ is a powerful language. With a firm grasp on its capabilities, you can make -write effective, consise, readable and maintainable code all at the same time. -By staying consistent, you reduce the amount of special cases that need to be -remembered. Reducing the total number of lines of code you write is a good way -to avoid documentation, and avoid giving bugs a place to hide.

    +

    C++ is a powerful language. With a firm grasp on its capabilities, you can +make write effective, consise, readable and maintainable code all at the same +time. By staying consistent, you reduce the amount of special cases that need +to be remembered. Reducing the total number of lines of code you write is a +good way to avoid documentation, and avoid giving bugs a place to hide.

    For these reasons, come to know and love the contents of your local <algorithm> header file. Know about <functional> and what it can do @@ -605,7 +616,7 @@ Chris Lattner
    LLVM Compiler Infrastructure
    - Last modified: $Date: 2004/06/22 04:24:55 $ + Last modified: $Date: 2004/07/28 22:31:54 $ From brukman at cs.uiuc.edu Wed Jul 28 17:38:07 2004 From: brukman at cs.uiuc.edu (Misha Brukman) Date: Wed, 28 Jul 2004 17:38:07 -0500 Subject: [llvm-commits] CVS: llvm/docs/CodingStandards.html Message-ID: <200407282238.RAA11279@zion.cs.uiuc.edu> Changes in directory llvm/docs: CodingStandards.html updated: 1.19 -> 1.20 --- Log message: Fix grammar, eliminate double parenthesized sentence fragment. --- Diffs of the changes: (+6 -5) Index: llvm/docs/CodingStandards.html diff -u llvm/docs/CodingStandards.html:1.19 llvm/docs/CodingStandards.html:1.20 --- llvm/docs/CodingStandards.html:1.19 Wed Jul 28 17:31:54 2004 +++ llvm/docs/CodingStandards.html Wed Jul 28 17:37:57 2004 @@ -142,10 +142,11 @@

    A few things to note about this particular format: The "-*- C++ -*-" string on the first line is there to tell Emacs that the source file -is a C++ file, not a C file (Emacs assumes .h files are C files by default [Note -that tag this is not necessary in .cpp files]). The name of the file is also on -the first line, along with a very short description of the purpose of the file. -This is important when printing out code and flipping though lots of pages.

    +is a C++ file, not a C file (Emacs assumes .h files are C files by default). +Note that this tag is not necessary in .cpp files. The name of the file is also +on the first line, along with a very short description of the purpose of the +file. This is important when printing out code and flipping though lots of +pages.

    The next section in the file is a concise note that defines the license that the file is released under. This makes it perfectly clear what terms the source @@ -616,7 +617,7 @@ Chris Lattner
    LLVM Compiler Infrastructure
    - Last modified: $Date: 2004/07/28 22:31:54 $ + Last modified: $Date: 2004/07/28 22:37:57 $ From llvm at cs.uiuc.edu Wed Jul 28 19:13:14 2004 From: llvm at cs.uiuc.edu (LLVM) Date: Wed, 28 Jul 2004 19:13:14 -0500 Subject: [llvm-commits] CVS: llvm/docs/BytecodeFormat.html Message-ID: <200407290013.TAA12128@zion.cs.uiuc.edu> Changes in directory llvm/docs: BytecodeFormat.html updated: 1.19 -> 1.20 --- Log message: Updates to reflect most recent changes to bytecode file format: * Dependent libraries & target triple * Short block headers * 24-bit type slot ids. --- Diffs of the changes: (+1306 -967) Index: llvm/docs/BytecodeFormat.html diff -u llvm/docs/BytecodeFormat.html:1.19 llvm/docs/BytecodeFormat.html:1.20 --- llvm/docs/BytecodeFormat.html:1.19 Wed Jul 7 10:02:54 2004 +++ llvm/docs/BytecodeFormat.html Wed Jul 28 19:13:04 2004 @@ -1,5 +1,4 @@ - + LLVM Bytecode File Format @@ -13,7 +12,7 @@ -

    LLVM Bytecode File Format
    +
    LLVM Bytecode File Format
    1. Abstract
    2. Concepts @@ -53,385 +52,518 @@

      Written by Reid Spencer

    -
    Abstract
    -

    This document describes the LLVM bytecode file format. It specifies the - binary encoding rules of the bytecode file format so that equivalent systems - can encode bytecode files correctly. The LLVM bytecode representation is - used to store the intermediate representation on disk in compacted form.

    -

    The LLVM bytecode format may change in the future, but LLVM will always be - backwards compatible with older formats. This document will only describe - the most current version of the bytecode format. See - Version Differences for the details on how the - current version is different from previous versions.

    -

    +

    This document describes the LLVM bytecode file format. It specifies +the binary encoding rules of the bytecode file format so that +equivalent systems can encode bytecode files correctly. The LLVM +bytecode representation is used to store the intermediate +representation on disk in compacted form.

    +

    The LLVM bytecode format may change in the future, but LLVM will +always be backwards compatible with older formats. This document will +only describe the most current version of the bytecode format. See Version Differences for the details on how +the current version is different from previous versions.

    -
    Concepts
    -

    This section describes the general concepts of the bytecode file format - without getting into specific layout details. It is recommended that you read - this section thoroughly before interpreting the detailed descriptions.

    +

    This section describes the general concepts of the bytecode file +format without getting into specific layout details. It is recommended +that you read this section thoroughly before interpreting the detailed +descriptions.

    -
    Blocks
    -

    LLVM bytecode files consist simply of a sequence of blocks of bytes using - a binary encoding Each block begins with an header of two unsigned integers. - The first value identifies the type of block and the second value provides - the size of the block in bytes. The block identifier is used because it is - possible for entire blocks to be omitted from the file if they are empty. - The block identifier helps the reader determine which kind of block is next - in the file. Note that blocks can be nested within other blocks.

    -

    All blocks are variable length, and the block header specifies the size - of the block. All blocks begin on a byte index that is aligned to an even - 32-bit boundary. That is, the first block is 32-bit aligned because it - starts at offset 0. Each block is padded with zero fill bytes to ensure that - the next block also starts on a 32-bit boundary.

    +

    LLVM bytecode files consist simply of a sequence of blocks of bytes +using a binary encoding Each block begins with an header of two +unsigned integers. The first value identifies the type of block and the +second value provides the size of the block in bytes. The block +identifier is used because it is possible for entire blocks to be +omitted from the file if they are empty. The block identifier helps the +reader determine which kind of block is next in the file. Note that +blocks can be nested within other blocks.

    +

    All blocks are variable length, and the block header specifies the +size of the block. All blocks begin on a byte index that is aligned to +an even 32-bit boundary. That is, the first block is 32-bit aligned +because it starts at offset 0. Each block is padded with zero fill +bytes to ensure that the next block also starts on a 32-bit boundary.

    -
    Lists
    -

    LLVM Bytecode blocks often contain lists of things of a similar type. For - example, a function contains a list of instructions and a function type - contains a list of argument types. There are two basic types of lists: - length lists (llist), and null terminated lists - (zlist), as described below in the - Encoding Primitives.

    +

    LLVM Bytecode blocks often contain lists of things of a similar +type. For example, a function contains a list of instructions and a +function type contains a list of argument types. There are two basic +types of lists: length lists (llist), and null +terminated lists (zlist), as described below in +the Encoding Primitives.

    -
    Fields
    -

    Fields are units of information that LLVM knows how to write atomically. -Most fields have a uniform length or some kind of length indication built into -their encoding. For example, a constant string (array of bytes) is -written simply as the length followed by the characters. Although this is -similar to a list, constant strings are treated atomically and are thus -fields.

    +

    Fields are units of information that LLVM knows how to write atomically. Most +fields have a uniform length or some kind of length indication built into their +encoding. For example, a constant string (array of bytes) is written simply as +the length followed by the characters. Although this is similar to a list, +constant strings are treated atomically and are thus fields.

    Fields use a condensed bit format specific to the type of information they must contain. As few bits as possible are written for each field. The -sections that follow will provide the details on how these fields are +sections that follow will provide the details on how these fields are written and how the bits are to be interpreted.

    -
    Alignment
    -

    To support cross-platform differences, the bytecode file is aligned on - certain boundaries. This means that a small amount of padding (at most 3 - bytes) will be added to ensure that the next entry is aligned to a 32-bit - boundary.

    -
    - - -
    Variable Bit-Rate Encoding
    -
    -

    Most of the values written to LLVM bytecode files are small integers. To -minimize the number of bytes written for these quantities, an encoding -scheme similar to UTF-8 is used to write integer data. The scheme is known as -variable bit rate (vbr) encoding. In this encoding, the high bit of each -byte is used to indicate if more bytes follow. If (byte & 0x80) is non-zero -in any given byte, it means there is another byte immediately following that -also contributes to the value. For the final byte (byte & 0x80) is false -(the high bit is not set). In each byte only the low seven bits contribute to -the value. Consequently 32-bit quantities can take from one to five -bytes to encode. In general, smaller quantities will encode in fewer bytes, -as follows:

    - - - - - - - - - - - - - - - - -
    Byte #Significant BitsMaximum Value
    10-6127
    27-1316,383
    314-202,097,151
    421-27268,435,455
    528-3434,359,738,367
    635-414,398,046,511,103
    742-48562,949,953,421,311
    849-5572,057,594,037,927,935
    956-629,223,372,036,854,775,807
    1063-691,180,591,620,717,411,303,423
    -

    Note that in practice, the tenth byte could only encode bit 63 -since the maximum quantity to use this encoding is a 64-bit integer.

    - -

    Signed VBR values are encoded with the standard vbr encoding, but -with the sign bit as the low order bit instead of the high order bit. This -allows small negative quantities to be encoded efficiently. For example, -3 -is encoded as "((3 << 1) | 1)" and 3 is encoded as "(3 << 1) | -0)", emitted with the standard vbr encoding above.

    +

    To support cross-platform differences, the bytecode file is aligned +on certain boundaries. This means that a small amount of padding (at +most 3 bytes) will be added to ensure that the next entry is aligned to +a 32-bit boundary.

    +
    + +
    Variable Bit-Rate Encoding +
    +
    +

    Most of the values written to LLVM bytecode files are small integers. To +minimize the number of bytes written for these quantities, an encoding scheme +similar to UTF-8 is used to write integer data. The scheme is known as +variable bit rate (vbr) encoding. In this encoding, the high bit of +each byte is used to indicate if more bytes follow. If (byte & +0x80) is non-zero in any given byte, it means there is another byte +immediately following that also contributes to the value. For the final +byte (byte & 0x80) is false (the high bit is not set). In each byte +only the low seven bits contribute to the value. Consequently 32-bit +quantities can take from one to five bytes to encode. In +general, smaller quantities will encode in fewer bytes, as follows:

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    Byte #Significant BitsMaximum Value
    10-6127
    27-1316,383
    314-202,097,151
    421-27268,435,455
    528-3434,359,738,367
    635-414,398,046,511,103
    742-48562,949,953,421,311
    849-5572,057,594,037,927,935
    956-629,223,372,036,854,775,807
    1063-691,180,591,620,717,411,303,423
    +

    Note that in practice, the tenth byte could only encode bit 63 since +the maximum quantity to use this encoding is a 64-bit integer.

    +

    Signed VBR values are encoded with the standard vbr +encoding, but with the sign bit as the low order bit instead of the +high order bit. This allows small negative quantities to be encoded +efficiently. For example, -3 +is encoded as "((3 << 1) | 1)" and 3 is encoded as "(3 << +1) | 0)", emitted with the standard vbr encoding above.

    -
    Encoding Primitives
    -

    Each field in the bytecode format is encoded into the file using a small - set of primitive formats. The table below defines the encoding rules for the - various primitives used and gives them each a type name. The type names used - in the descriptions of blocks and fields in the Detailed - Layoutnext section. Any type name with the suffix _vbr indicates - a quantity that is encoded using variable bit rate encoding as described - above.

    - - - - - - - - +
    TypeRule
    unsignedA 32-bit unsigned integer that always occupies four +

    Each field in the bytecode format is encoded into the file using a +small set of primitive formats. The table below defines the encoding +rules for the various primitives used and gives them each a type name. +The type names used in the descriptions of blocks and fields in the Detailed Layoutnext section. Any type name with +the suffix _vbr indicates a quantity that is encoded using +variable bit rate encoding as described above.

    + + + + + + + + + - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    TypeRule
    unsignedA 32-bit unsigned integer that always occupies four consecutive bytes. The unsigned integer is encoded using LSB first ordering. That is bits 20 through 27 are in the byte with the lowest file offset (little endian).
    uint32_vbrA 32-bit unsigned integer that occupies from one to five - bytes using variable bit rate encoding.
    uint64_vbrA 64-bit unsigned integer that occupies from one to ten - bytes using variable bit rate encoding.
    int64_vbrA 64-bit signed integer that occupies from one to ten - bytes using the signed variable bit rate encoding.
    charA single unsigned character encoded into one byte
    bit(n-m)A set of bit within some larger integer field. The - values of n and m specify the inclusive range - of bits that define the subfield. The value for m may be - omitted if its the same as n.
    stringA uint32_vbr indicating the type of the constant string - which also includes its length, immediately followed by the characters of - the string. There is no terminating null byte in the string.
    dataAn arbitrarily long segment of data to which no - interpretation is implied. This is used for float, double, and constant - initializers.
    llist(x)A length list of x. This means the list is encoded as - an uint32_vbr providing the length of the list, - followed by a sequence of that many "x" items. This implies that the reader - should iterate the number of times provided by the length.
    zlist(x)A zero-terminated list of x. This means the list is encoded - as a sequence of an indeterminate number of "x" items, followed by an - uint32_vbr terminating value. This implies that none - of the "x" items can have a zero value (or else the list terminates).
    blockA block of data that is logically related. A block - begins with an unsigned that provides the block - identifier (constant value) and an unsigned that - provides the length of the block. Blocks may compose other blocks. -
    uint24_vbrA 24-bit unsigned + integer that occupies from one to four bytes using variable bit rate + encoding.
    uint32_vbrA 32-bit unsigned integer that occupies from +one to five bytes using variable bit rate encoding.
    uint64_vbrA 64-bit unsigned integer that occupies from +one to ten bytes using variable bit rate encoding.
    int64_vbrA 64-bit signed integer that occupies from +one to ten bytes using the signed variable bit rate encoding.
    charA single unsigned character encoded into one +byte
    bit(n-m)A set of bit within some larger integer +field. The values of n and m specify the +inclusive range of bits that define the subfield. The value for m +may be omitted if its the same as n.
    floatA floating +point value encoded as a 32-bit IEEE value written in little-endian +form.
    +
    doubleA floating +point value encoded as a64-bit IEEE value written in little-endian form
    stringA uint32_vbr indicating the type of the +constant string which also includes its length, immediately followed by +the characters of the string. There is no terminating null byte in the +string.
    dataAn arbitrarily long segment of data to which +no interpretation is implied. This is used for constant initializers.
    +
    llist(x)A length list of x. This means the list is +encoded as an uint32_vbr providing the +length of the list, followed by a sequence of that many "x" items. This +implies that the reader should iterate the number of times provided by +the length.
    zlist(x)A zero-terminated list of x. This means the +list is encoded as a sequence of an indeterminate number of "x" items, +followed by an uint32_vbr terminating value. +This implies that none of the "x" items can have a zero value (or else +the list terminates).
    blockA block of data that is logically related. A +block is an unsigned 32-bit integer that encodes the type of the block +in the low 5 bits and the size of the block in the high 27 bits. The +length does not include the block header or any alignment bytes at the +end of the block. Blocks may compose other blocks.
    -
    Field Notation
    -

    In the detailed block and field descriptions that follow, a regex like - notation is used to describe optional and repeated fields. A very limited - subset of regex is used to describe these, as given in the following table: -

    - +

    In the detailed block and field descriptions that follow, a regex +like notation is used to describe optional and repeated fields. A very +limited subset of regex is used to describe these, as given in the +following table:

    +
    + - + + - - + + + - - + + + - - + + + - + + - + -
    Character Meaning
    ?The question mark indicates 0 or 1 occurrences of - the thing preceding it.
    The question mark indicates 0 or 1 +occurrences of the thing preceding it.
    *The asterisk indicates 0 or more occurrences of the - thing preceding it.
    The asterisk indicates 0 or more occurrences +of the thing preceding it.
    +The plus sign indicates 1 or more occurrences of the - thing preceding it.
    The plus sign indicates 1 or more occurrences +of the thing preceding it.
    () Parentheses are used for grouping.
    ,The comma separates sequential fields.The comma separates sequential fields.
    -

    So, for example, consider the following specifications:

    -
    -
      -
    1. string?
      2. -
    2. (uint32_vbr,uin32_vbr)+
      3. -
    3. (unsigned?,uint32_vbr)*
      4. -
    4. (llist(unsigned))?
      5. -
    -
    -

    with the following interpretations:

    -
      -
    1. An optional string. Matches either nothing or a single string
      2. -
    2. One or more pairs of uint32_vbr.
      3. -
    3. Zero or more occurrences of either an unsigned followed by a uint32_vbr - or just a uint32_vbr.
      4. -
    4. An optional length list of unsigned values.
      5. -
    +
    +

    So, for example, consider the following specifications:

    +
    +
      +
    1. string?
      2. +
    2. (uint32_vbr,uin32_vbr)+
      3. +
    3. (unsigned?,uint32_vbr)*
      4. +
    4. (llist(unsigned))?
      5. +
    +
    +

    with the following interpretations:

    +
      +
    1. An optional string. Matches either nothing or a single string
      2. +
    2. One or more pairs of uint32_vbr.
      3. +
    3. Zero or more occurrences of either an unsigned followed by a +uint32_vbr or just a uint32_vbr.
      4. +
    4. An optional length list of unsigned values.
      5. +
    -
    Slots
    -

    The bytecode format uses the notion of a "slot" to reference Types and -Values. Since the bytecode file is a direct representation of LLVM's -intermediate representation, there is a need to represent pointers in the file. -Slots are used for this purpose. For example, if one has the following assembly: +

    The bytecode format uses the notion of a "slot" to reference Types +and Values. Since the bytecode file is a direct representation of +LLVM's intermediate representation, there is a need to represent pointers in +the file. Slots are used for this purpose. For example, if one has the following +assembly:

    -
    - %MyType = type { int, sbyte }
    - %MyVar = external global %MyType +
    %MyType = type { int, sbyte }
    +%MyVar = external global %MyType
    -

    there are two definitions. The definition of %MyVar uses -%MyType. In the C++ IR this linkage between %MyVar and -%MyType is -explicit through the use of C++ pointers. In bytecode, however, there's no -ability to store memory addresses. Instead, we compute and write out slot -numbers for every Type and Value written to the file.

    +

    there are two definitions. The definition of %MyVar uses %MyType. +In the C++ IR this linkage between %MyVar and %MyType +is explicit through the use of C++ pointers. In bytecode, however, there's no +ability to store memory addresses. Instead, we compute and write out +slot numbers for every Type and Value written to the file.

    A slot number is simply an unsigned 32-bit integer encoded in the variable bit rate scheme (see encoding). This ensures that low slot numbers are encoded in one byte. Through various bits of magic LLVM attempts to always keep the slot numbers low. The first attempt is to associate -slot numbers with their "type plane". That is, Values of the same type are -written to the bytecode file in a list (sequentially). Their order in that list -determines their slot number. This means that slot #1 doesn't mean anything -unless you also specify for which type you want slot #1. Types are handled -specially and are always written to the file first (in the -Global Type Pool) and -in such a way that both forward and backward references of the types can often be -resolved with a single pass through the type pool.

    -

    Slot numbers are also kept small by rearranging their order. Because of the -structure of LLVM, certain values are much more likely to be used frequently -in the body of a function. For this reason, a compaction table is provided in -the body of a function if its use would make the function body smaller. -Suppose you have a function body that uses just the types "int*" and "{double}" -but uses them thousands of time. Its worthwhile to ensure that the slot number -for these types are low so they can be encoded in a single byte (via vbr). -This is exactly what the compaction table does.

    +slot numbers with their "type plane". That is, Values of the same type +are written to the bytecode file in a list (sequentially). Their order in +that list determines their slot number. This means that slot #1 doesn't mean +anything unless you also specify for which type you want slot #1. Types are +handled specially and are always written to the file first (in the Global Type Pool) and in such a way that both forward +and backward references of the types can often be resolved with a single pass +through the type pool.

    +

    Slot numbers are also kept small by rearranging their order. Because +of the structure of LLVM, certain values are much more likely to be used +frequently in the body of a function. For this reason, a compaction table is +provided in the body of a function if its use would make the function body +smaller. Suppose you have a function body that uses just the types "int*" and +"{double}" but uses them thousands of time. Its worthwhile to ensure that the +slot number for these types are low so they can be encoded in a single byte +(via vbr). This is exactly what the compaction table does.

    -
    General Structure
    -

    This section provides the general structure of the LLVM bytecode file - format. The bytecode file format requires blocks to be in a certain order and - nested in a particular way so that an LLVM module can be constructed - efficiently from the contents of the file. This ordering defines a general - structure for bytecode files as shown below. The table below shows the order - in which all block types may appear. Please note that some of the blocks are - optional and some may be repeated. The structure is fairly loose because - optional blocks, if empty, are completely omitted from the file.

    - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - +

    This section provides the general structure of the LLVM bytecode +file format. The bytecode file format requires blocks to be in a +certain order and nested in a particular way so that an LLVM module can +be constructed efficiently from the contents of the file. This ordering +defines a general structure for bytecode files as shown below. The +table below shows the order in which all block types may appear. Please +note that some of the blocks are optional and some may be repeated. The +structure is fairly loose because optional blocks, if empty, are +completely omitted from the file.

    +
    IDParentOptional?Repeated?LevelBlock TypeDescription
    N/AFileNoNo0SignatureThis contains the file signature (magic number) - that identifies the file as LLVM bytecode.
    0x01FileNoNo0ModuleThis is the top level block in a bytecode file. It - contains all the other blocks. -
    0x15ModuleNoNo1   Global Type PoolThis block contains all the global (module) level - types.
    0x14ModuleNoNo1   Module Globals InfoThis block contains the type, constness, and linkage - for each of the global variables in the module. It also contains the - type of the functions and the constant initializers.
    0x12ModuleYesNo1   Module Constant PoolThis block contains all the global constants - except function arguments, global values and constant strings.
    0x11ModuleYesYes1   Function Definitions*One function block is written for each function in - the module. The function block contains the instructions, compaction - table, type constant pool, and symbol table for the function.
    0x12FunctionYesNo2      Function Constant PoolAny constants (including types) used solely - within the function are emitted here in the function constant pool. -
    0x33FunctionYesNo2      Compaction TableThis table reduces bytecode size by providing a - funtion-local mapping of type and value slot numbers to their - global slot numbers
    0x32FunctionNoNo2      Instruction ListThis block contains all the instructions of the - function. The basic blocks are inferred by terminating instructions. -
    0x13FunctionYesNo2      Function Symbol TableThis symbol table provides the names for the - function specific values used (basic block labels mostly).
    0x13ModuleYesNo1   Module Symbol TableThis symbol table provides the names for the various - entries in the file that are not function specific (global vars, and - functions mostly).
    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    IDParentOptional?Repeated?LevelBlock TypeDescription
    N/AFileNoNo0SignatureThis contains the file signature (magic +number) that identifies the file as LLVM bytecode.
    0x01FileNoNo0ModuleThis is the top level block in a bytecode +file. It contains all the other blocks.
    0x06ModuleNoNo1   Global Type PoolThis block contains all the global (module) +level types.
    0x05ModuleNoNo1   Module Globals InfoThis block contains the type, constness, and +linkage for each of the global variables in the module. It also +contains the type of the functions and the constant initializers.
    0x03ModuleYesNo1   Module Constant PoolThis block contains all the global constants +except function arguments, global values and constant strings.
    0x02ModuleYesYes1   Function Definitions*One function block is written for each +function in the module. The function block contains the instructions, +compaction table, type constant pool, and symbol table for the function.
    0x03FunctionYesNo2      Function Constant PoolAny constants (including types) used solely +within the function are emitted here in the function constant pool.
    0x08FunctionYesNo2      Compaction TableThis table reduces bytecode size by providing +a funtion-local mapping of type and value slot numbers to their global +slot numbers
    0x07FunctionNoNo2      Instruction ListThis block contains all the instructions of +the function. The basic blocks are inferred by terminating +instructions.
    0x04FunctionYesNo2      Function Symbol TableThis symbol table provides the names for the +function specific values used (basic block labels mostly).
    0x04ModuleYesNo1   Module Symbol TableThis symbol table provides the names for the +various entries in the file that are not function specific (global +vars, and functions mostly).
    -

    Use the links in the table for details about the contents of each of the block types.

    +

    Use the links in the table for details about the contents of each of +the block types.

    -
    Block Definitions
    -

    This section provides the detailed layout of the individual block types - in the LLVM bytecode file format.

    +

    This section provides the detailed layout of the individual block +types in the LLVM bytecode file format.

    -
    Signature Block
    @@ -440,26 +572,32 @@ bytecode file. This block is always four bytes in length and differs from the other blocks because there is no identifier and no block length at the start of the block. Essentially, this block is just the "magic number" for the file. +

    - - - - - - - - - - - - - - - - + + + + + + + + + + + + + + + + + + + + + +
    TypeField Description
    charConstant "l" (0x6C)
    charConstant "l" (0x6C)
    charConstant "v" (0x76)
    charConstant "m" (0x6D)
    TypeField Description
    charConstant "l" (0x6C)
    charConstant "l" (0x6C)
    charConstant "v" (0x76)
    charConstant "m" (0x6D)
    -
    Module Block
    @@ -469,106 +607,125 @@ information. Everything else is contained in other blocks, described in other sections.

    - - - - - - - - - - - - - - - - - - - - - - - - - - - - + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    TypeField Description
    unsignedModule Identifier (0x01)
    unsignedSize of the module block in bytes
    uint32_vbrFormat Information
    blockGlobal Type Pool
    blockModule Globals Info
    blockModule Constant Pool
    block*Function Definitions
    blockModule Symbol Table
    TypeField Description
    block
    +     		Module Block Identifier (0x01) and Size
    +
    uint32_vbrFormat Information
    blockGlobal Type Pool
    blockModule Globals Info
    blockModule Constant Pool
    block*Function Definitions
    blockModule Symbol Table
    -
    Format Information
    -

    The format information field is encoded into a - uint32_vbr as shown in the following table.

    +

    The format information field is encoded into a uint32_vbr +as shown in the following table.

    - - - - - - - - - - - - - - - - - - - + + + + + + + + + + + + + + + + + + + + + + + + + +
    TypeDescription
    bit(0)Target is big endian?
    bit(1)On target pointers are 64-bit?
    bit(2)Target has no endianess?
    bit(3)Target has no pointer size?
    bit(4-31)Bytecode format version
    TypeDescription
    bit(0)Target is big endian?
    bit(1)On target pointers are 64-bit?
    bit(2)Target has no endianess?
    bit(3)Target has no pointer size?
    bit(4-31)Bytecode format version

    Of particular note, the bytecode format number is simply a 28-bit monotonically increase integer that identifies the version of the bytecode -format (which is not directly related to the LLVM release number). The -bytecode versions defined so far are (note that this document only describes -the latest version, 1.3):

    +format (which is not directly related to the LLVM release number). The +bytecode versions defined so far are (note that this document only +describes the latest version, 1.3):

      -
    • #0: LLVM 1.0 & 1.1
      • -
    • #1: LLVM 1.2
      • -
    • #2: LLVM 1.3
      • +
    • #0: LLVM 1.0 & 1.1
      • +
    • #1: LLVM 1.2
      • +
    • #2: LLVM 1.2.5 (not released)
      • +
    • #3: LLVM 1.3
      +
    -

    Note that we plan to eventually expand the target description capabilities -of bytecode files to target triples. +

    Note that we plan to eventually expand the target description +capabilities +of bytecode files to target +triples.

    -
    Global Type Pool

    The global type pool consists of type definitions. Their order of appearance -in the file determines their slot number (0 based). Slot numbers are used to -replace pointers in the intermediate representation. Each slot number uniquely -identifies one entry in a type plane (a collection of values of the same type). -Since all values have types and are associated with the order in which the type -pool is written, the global type pool must be written as the first -block of a module. If it is not, attempts to read the file will fail because -both forward and backward type resolution will not be possible.

    -

    The type pool is simply a list of type definitions, as shown in the table -below.

    - - - - - - - - - - - - - - +in the file determines their slot number (0 based). Slot numbers are +used to replace pointers in the intermediate representation. Each slot number +uniquely identifies one entry in a type plane (a collection of values of the +same type). Since all values have types and are associated with the order in +which the type pool is written, the global type pool must be written +as the first block of a module. If it is not, attempts to read the file will +fail because both forward and backward type resolution will not be possible.

    +

    The type pool is simply a list of type definitions, as shown in the +table below.

    +
    TypeField Description
    unsignedType Pool Identifier (0x15)
    unsignedSize in bytes of the type pool block.
    llist(type)A length list of type definitions.
    + + + + + + + + + + + + + +
    TypeField Description
    blockType Pool Identifier (0x06) + Size
    +
    llist(type)A length list of type definitions.
    @@ -577,722 +734,904 @@

    Types in the type pool are defined using a different format for each kind of type, as given in the following sections.

    Primitive Types

    -

    The primitive types encompass the basic integer and floating point types

    +

    The primitive types encompass the basic integer and floating point +types

    - - - - - - - + + + + + + + + + +
    TypeDescription
    uint32_vbrType ID for the primitive types (values 1 to 11) - 1
    TypeDescription
    uint24_vbrType ID for the primitive types (values 1 to +11) 1
    Notes:
      -
    1. The values for the Type IDs for the primitive types are provided by the - definition of the llvm::Type::TypeID enumeration in - include/llvm/Type.h. The enumeration gives the following - mapping:
        -
      1. bool
        2. -
      2. ubyte
        3. -
      3. sbyte
        4. -
      4. ushort
        5. -
      5. short
        6. -
      6. uint
        7. -
      7. int
        8. -
      8. ulong
        9. -
      9. long
        10. -
      10. float
        11. -
      11. double
        12. -
      2. +
    2. The values for the Type IDs for the primitive types are provided +by the definition of the llvm::Type::TypeID enumeration +in include/llvm/Type.h. The enumeration gives the +following mapping: +
        +
      1. bool
        2. +
      2. ubyte
        3. +
      3. sbyte
        4. +
      4. ushort
        5. +
      5. short
        6. +
      6. uint
        7. +
      7. int
        8. +
      8. ulong
        9. +
      9. long
        10. +
      10. float
        11. +
      11. double
        12. +
      +

    Function Types

    - - - - - - - - - - - + + + + + + + + + + + + + + + - - - - + + + + + +
    TypeDescription
    uint32_vbrType ID for function types (13)
    uint32_vbrSlot number of function's return type.
    llist(uint32_vbr)
    TypeDescription
    uint24_vbrType ID for function types (13)
    uint24_vbrSlot number of function's return type.
    llist(uint24_vbr) Slot number of each argument's type.
    uint32_vbr?Value 0 if this is a varargs function, missing otherwise.
    uint32_vbr?Value 0 if this is a varargs function, +missing otherwise.

    Structure Types

    - - - - - - - - - - + + + + + + + + + + + + + +
    TypeDescription
    uint32_vbrType ID for structure types (14)
    zlist(uint32_vbr)Slot number of each of the element's fields.
    TypeDescription
    uint24_vbrType ID for structure types (14)
    zlist(uint24_vbr)Slot number of each of the element's fields.

    Array Types

    - - - - - - - - - - - - - + + + + + + + + + + + + + + + + + +
    TypeDescription
    uint32_vbrType ID for Array Types (15)
    uint32_vbrSlot number of array's element type.
    uint32_vbrThe number of elements in the array.
    TypeDescription
    uint24_vbrType ID for Array Types (15)
    uint24_vbrSlot number of array's element type.
    uint32_vbrThe number of elements in the array.

    Pointer Types

    - - - - - - - - - - + + + + + + + + + + + + + +
    TypeDescription
    uint32_vbrType ID For Pointer Types (16)
    uint32_vbrSlot number of pointer's element type.
    TypeDescription
    uint24_vbrType ID For Pointer Types (16)
    uint24_vbrSlot number of pointer's element type.

    Opaque Types

    - - - - - - - + + + + + + + + + +
    TypeDescription
    uint32_vbrType ID For Opaque Types (17)
    TypeDescription
    uint24_vbrType ID For Opaque Types (17)
    -
    Module Global Info
    -
    -

    The module global info block contains the definitions of all global - variables including their initializers and the declaration of all - functions. The format is shown in the table below:

    - +
    Module Global Info +
    +
    +

    The module global info block contains the definitions of all global +variables including their initializers and the declaration of +all functions. The format is shown in the table below:

    +
    + - - - - - - - + + + + + + - - - - + -
    Type Field Description
    unsignedModule global info identifier (0x14)
    unsignedSize in bytes of the module global info block.
    blockModule global info identifier (0x05) + size
    +
    zlist(globalvar)A zero terminated list of global var definitions - occuring in the module.
    zlist(uint32_vbr)A zero terminated list of function types occuring in - the module.A zero terminated list of global var +definitions occuring in the module.
    + + zlist(uint24_vbr) + A zero terminated list of function types +occuring in the module. + + + llist(string)
    + + A length list +of strings that specify the names of the libraries that this module +depends upon.
    + + + + string
    + + The target +triple for the module (blank means no target triple specified, i.e. a +platform independent module).
    + + + +
    -
    Global Variable Field
    -

    Global variables are written using an uint32_vbr - that encodes information about the global variable and a list of the constant - initializers for the global var, if any.

    -

    The table below provides the bit layout of the first - uint32_vbr that describes the global variable.

    - - - - - - - - - - - - - - - - -
    TypeDescription
    bit(0)Is constant?
    bit(1)Has initializer? Note that this bit determines whether - the constant initializer field (described below) follows. -
    bit(2-4)Linkage type: 0=External, 1=Weak, 2=Appending, - 3=Internal, 4=LinkOnce
    bit(5-31)Slot number of type for the global variable.
    -

    The table below provides the format of the constant initializers for the - global variable field, if it has one.

    - +

    Global variables are written using an uint32_vbr +that encodes information about the global variable and a list of the +constant initializers for the global var, if any.

    +

    The table below provides the bit layout of the first uint32_vbr that describes the global variable.

    +
    + + + + + + + + + + + + + + + + + + + + + + +
    TypeDescription
    bit(0)Is constant?
    bit(1)Has initializer? Note that this bit +determines whether the constant initializer field (described below) +follows.
    bit(2-4)Linkage type: 0=External, 1=Weak, +2=Appending, 3=Internal, 4=LinkOnce
    bit(5-31)Slot number of type for the global variable.
    +

    The table below provides the format of the constant initializers for +the global variable field, if it has one.

    + + - + + - + -
    Type Description
    (zlist(uint32_vbr))? - An optional zero-terminated list of slot numbers of - the global variable's constant initializer.An optional zero-terminated list of slot +numbers of the global variable's constant initializer.
    + +
    -
    Constant Pool
    -

    A constant pool defines as set of constant values. There are actually two - types of constant pool blocks: one for modules and one for functions. For - modules, the block begins with the constant strings encountered anywhere in - the module. For functions, the block begins with types only encountered in - the function. In both cases the header is identical. The tables that follow, - show the header, module constant pool preamble, function constant pool - preamble, and the part common to both function and module constant pools.

    -

    Common Block Header

    - +

    A constant pool defines as set of constant values. There are +actually two types of constant pool blocks: one for modules and one for +functions. For modules, the block begins with the constant strings +encountered anywhere in the module. For functions, the block begins +with types only encountered in the function. In both cases the header +is identical. The tables that follow, show the header, module constant +pool preamble, function constant pool preamble, and the part common to +both function and module constant pools.

    +

    Common Block Header

    +
    + - - - - - - -
    Type Field Description
    unsignedConstant pool identifier (0x12)
    unsignedSize in bytes of the constant pool block.
    -

    Module Constant Pool Preamble (constant strings)

    - + + + + + +
    blockConstant pool identifier (0x03) + size
    +
    +

    Module Constant Pool Preamble (constant strings)

    + + - + + - + + - - - - + -
    Type Field Description
    uint32_vbr The number of constant strings that follow.
    uint32_vbrZero. This identifies the following "plane" as - containing the constant strings. This is needed to identify it - uniquely from other constant planes that follow. -
    uint32_vbr+Slot number of the constant string's type. Note - that the constant string's type implicitly defines the length of - the string. - Zero. This identifies the following "plane" +as containing the constant strings. This is needed to identify it +uniquely from other constant planes that follow.
    -

    Function Constant Pool Preamble (function types)

    -

    The structure of the types for functions is identical to the - Global Type Pool. Please refer to that section - for the details. -

    Common Part (other constants)

    - + + + + + +
    uint24_vbr+Slot number of the constant string's type. +Note that the constant string's type implicitly defines the length of +the string.
    +

    Function Constant Pool Preamble (function types)

    +

    The structure of the types for functions is identical to the Global Type Pool. Please refer to that section +for the details.

    +

    Common Part (other constants)

    + + - + + - - + + + - + + -
    Type Field Description
    uint32_vbr Number of entries in this type plane.
    uint32_vbr
    uint24_vbr Type slot number of this plane.
    constant+ The definition of a constant (see below).
    + +
    Constant Field
    -

    Constants come in many shapes and flavors. The sections that followe define - the format for each of them. All constants start with a - uint32_vbr encoded integer that provides the number - of operands for the constant. For primitive, structure, and array constants, - this will always be zero since those types of constants have no operands. - In this case, we have the following field definitions:

    -
      -
    • Bool. This is written as an uint32_vbr - of value 1U or 0U.
      • -
    • Signed Integers (sbyte,short,int,long). These are written as - an int64_vbr with the corresponding value.
      • -
    • Unsigned Integers (ubyte,ushort,uint,ulong). These are written - as an uint64_vbr with the corresponding value. -
      • -
    • Floating Point. Both the float and double types are written - literally in binary format.
      • -
    • Arrays. Arrays are written simply as a list of - uint32_vbr encoded slot numbers to the constant - element values.
      • -
    • Structures. Structures are written simply as a list of - uint32_vbr encoded slot numbers to the constant - field values of the structure.
      • -
    -

    When the number of operands to the constant is non-zero, we have a - constant expression and its field format is provided in the table below.

    - +

    Constants come in many shapes and flavors. The sections that followe +define the format for each of them. All constants start with a uint32_vbr encoded integer that provides the +number of operands for the constant. For primitive, structure, and +array constants, this will always be zero since those types of +constants have no operands. In this case, we have the following field +definitions:

    +
      +
    • Bool. This is written as an uint32_vbr +of value 1U or 0U.
      • +
    • Signed Integers (sbyte,short,int,long). These are written +as an int64_vbr with the corresponding value.
      • +
    • Unsigned Integers (ubyte,ushort,uint,ulong). These are +written as an uint64_vbr with the +corresponding value.
      • +
    • Floating Point. Both the float and double types are +written literally in binary format.
      • +
    • Arrays. Arrays are written simply as a list of uint32_vbr encoded slot numbers to the constant +element values.
      • +
    • Structures. Structures are written simply as a list of uint32_vbr encoded slot numbers to the constant +field values of the structure.
      • +
    +

    When the number of operands to the constant is non-zero, we have a +constant expression and its field format is provided in the table below.

    +
    + - - - - + + - - + + + - + + + + + -
    Type Field Description
    uint32_vbrOp code of the instruction for the constant - expression.
    uint32_vbrThe slot number of the constant value for an - operand.1
    Op code of the instruction for the constant +expression.
    uint32_vbrThe slot number for the type of the constant value - for an operand.1The slot number of the constant value for an +operand.1
    uint24_vbrThe slot number for the type of the constant +value for an operand.1
    - Notes:
      -
    1. Both these fields are repeatable but only in pairs.
      2. -
    + + +Notes: +
      +
    1. Both these fields are repeatable but only in pairs.
      2. +
    Function Definition
    -

    Function definitions contain the linkage, constant pool or compaction - table, instruction list, and symbol table for a function. The following table - shows the structure of a function definition.

    - +

    Function definitions contain the linkage, constant pool or +compaction table, instruction list, and symbol table for a function. +The following table shows the structure of a function definition.

    +
    + - - - - - - - + + + + + + - - - - - - - - - - - + + + + + + + - - -
    Type Field Description
    unsignedFunction definition block identifier (0x11)
    unsignedSize in bytes of the function definition block.
    block
    +     		Function definition block identifier (0x02) + +size
    +
    uint32_vbrThe linkage type of the function: 0=External, 1=Weak, - 2=Appending, 3=Internal, 4=LinkOnce1
    blockThe constant pool block - for this function.2
    blockThe compaction table - block for the function.2
    blockThe instruction list - for the function.
    The linkage type of the function: 0=External, +1=Weak, 2=Appending, 3=Internal, 4=LinkOnce1
    blockThe constant pool +block for this function.2
    blockThe function's symbol table - containing only those symbols pertinent to the function (mostly - block labels).
    - Notes:
      -
    1. Note that if the linkage type is "External" then none of the other - fields will be present as the function is defined elsewhere.
      2. -
    2. Note that only one of the constant pool or compaction table will be - written. Compaction tables are only written if they will actually save - bytecode space. If not, then a regular constant pool is written.
      3. -
    -
    - -
    Compaction Table
    -
    -

    Compaction tables are part of a function definition. They are merely a - device for reducing the size of bytecode files. The size of a bytecode - file is dependent on the value of the slot numbers used because - larger values use more bytes in the variable bit rate encoding scheme. - Furthermore, the compressed instruction format reserves only six bits for - the type of the instruction. In large modules, declaring hundreds or thousands - of types, the values of the slot numbers can be quite large. However, - functions may use only a small fraction of the global types. In such cases - a compaction table is created that maps the global type and value slot - numbers to smaller values used by a function. Functions will contain either - a function-specific constant pool or a compaction table but not - both. Compaction tables have the format shown in the table below.

    - + + + + + + + + + + + +
    The compaction +table block for the function.2
    blockThe instruction +list for the function.
    blockThe function's symbol +table containing only those symbols pertinent to the function +(mostly block labels).
    +Notes: +
      +
    1. Note that if the linkage type is "External" then none of the +other fields will be present as the function is defined elsewhere.
      2. +
    2. Note that only one of the constant pool or compaction table will +be written. Compaction tables are only written if they will actually +save bytecode space. If not, then a regular constant pool is written.
      3. +
    +
    + +
    Compaction Table +
    +
    +

    Compaction tables are part of a function definition. They are merely +a device for reducing the size of bytecode files. The size of a +bytecode file is dependent on the value of the slot numbers +used because larger values use more bytes in the variable bit rate +encoding scheme. Furthermore, the compressed instruction format +reserves only six bits for the type of the instruction. In large +modules, declaring hundreds or thousands of types, the values of the +slot numbers can be quite large. However, functions may use only a +small fraction of the global types. In such cases a compaction table is +created that maps the global type and value slot numbers to smaller +values used by a function. Functions will contain either a +function-specific constant pool or a compaction table but not +both. Compaction tables have the format shown in the table below.

    + + - + + - - - - + + + + + + - - + + + - + -
    Type Field Description
    uint32_vbr The number of types that follow
    uint32_vbr+The slot number in the global type plane of the - type that will be referenced in the function with the index of - this entry in the compaction table.
    uint24_vbr+The slot number in the global type plane of +the type that will be referenced in the function with the index of this +entry in the compaction table.
    type_lenAn encoding of the type and number of values that - follow. This field's encoding varies depending on the size of - the type plane. See Type and Length for - further details.
    An encoding of the type and number of values +that follow. This field's encoding varies depending on the size of the +type plane. See Type and Length for further +details.
    uint32_vbr+The slot number in the globals of the value that - will be referenced in the function with the index of this entry in - the compaction tableThe slot number in the globals of the value +that will be referenced in the function with the index of this entry in +the compaction table
    + +
    -
    Type and Length
    -

    The type and length of a compaction table type plane is encoded differently - depending on the length of the plane. For planes of length 1 or 2, the length - is encoded into bits 0 and 1 of a uint32_vbr and the - type is encoded into bits 2-31. Because type numbers are often small, this - often saves an extra byte per plane. If the length of the plane is greater - than 2 then the encoding uses a uint32_vbr for each - of the length and type, in that order.

    -
    - - -
    Instruction List
    -
    -

    The instructions in a function are written as a simple list. Basic blocks - are inferred by the terminating instruction types. The format of the block - is given in the following table.

    - +

    The type and length of a compaction table type plane is encoded +differently depending on the length of the plane. For planes of length +1 or 2, the length is encoded into bits 0 and 1 of a uint32_vbr and the type is encoded into bits +2-31. Because type numbers are often small, this often saves an extra +byte per plane. If the length of the plane is greater than 2 then the +encoding uses a uint32_vbr for each of the +length and type, in that order.

    + + +
    Instruction List +
    +
    +

    The instructions in a function are written as a simple list. Basic +blocks are inferred by the terminating instruction types. The format of +the block is given in the following table.

    +
    + - - - - - - - + + + + + + - + -
    Type Field Description
    unsignedInstruction list identifier (0x33).
    unsignedSize in bytes of the instruction list.
    block
    +     		Instruction list identifier (0x07) + size
    +
    instruction+An instruction. Instructions have a variety of formats. - See Instructions for details.An instruction. Instructions have a variety +of formats. See Instructions for details.
    + +
    -
    Instructions
    -

    For brevity, instructions are written in one of four formats, depending on - the number of operands to the instruction. Each instruction begins with a - uint32_vbr that encodes the type of the instruction - as well as other things. The tables that follow describe the format of this - first word of each instruction.

    -

    Instruction Format 0

    -

    This format is used for a few instructions that can't easily be optimized - because they have large numbers of operands (e.g. PHI Node or getelementptr). - Each of the opcode, type, and operand fields is as successive fields.

    - +

    For brevity, instructions are written in one of four formats, +depending on the number of operands to the instruction. Each +instruction begins with a uint32_vbr that +encodes the type of the instruction as well as other things. The tables +that follow describe the format of this first word of each instruction.

    +

    Instruction Format 0

    +

    This format is used for a few instructions that can't easily be +optimized because they have large numbers of operands (e.g. PHI Node or +getelementptr). Each of the opcode, type, and operand fields is as +successive fields.

    +
    + - - - - + + - - + + + + + + + - + + - + -
    Type Field Description
    uint32_vbrSpecifies the opcode of the instruction. Note that for - compatibility with the other instruction formats, the opcode is shifted - left by 2 bits. Bits 0 and 1 must have value zero for this format.
    uint32_vbrProvides the slot number of the result type of the - instruction
    Specifies the opcode of the instruction. Note +that for compatibility with the other instruction formats, the opcode +is shifted left by 2 bits. Bits 0 and 1 must have value zero for this +format.
    uint24_vbrProvides the slot number of the result type +of the instruction
    uint32_vbr The number of operands that follow.
    uint32_vbr+The slot number of the value(s) for the operand(s). - 1The slot number of the value(s) for the +operand(s). 1
    - Notes:
      -
    1. Note that if the instruction is a getelementptr and the type of the - operand is a sequential type (array or pointer) then the slot number is - shifted up two bits and the low order bits will encode the type of index - used, as follows: 0=uint, 1=int, 2=ulong, 3=long.
      2. -
    -

    Instruction Format 1

    -

    This format encodes the opcode, type and a single operand into a single - uint32_vbr as follows:

    - + +
    +Notes: +
      +
    1. Note that if the instruction is a getelementptr and the type of +the operand is a sequential type (array or pointer) then the slot +number is shifted up two bits and the low order bits will encode the +type of index used, as follows: 0=uint, 1=int, 2=ulong, 3=long.
      2. +
    +

    Instruction Format 1

    +

    This format encodes the opcode, type and a single operand into a +single uint32_vbr as follows:

    + + - - - - - - - - - - - - - - -
    Bits Type Field Description
    0-1constant "1"These two bits must be the value 1 which identifies - this as an instruction of format 1.
    2-7opcodeSpecifies the opcode of the instruction. Note that - the maximum opcode value is 63.
    8-19unsignedSpecifies the slot number of the type for this - instruction. Maximum slot number is 212-1=4095.
    20-31unsignedSpecifies the slot number of the value for the - first operand. Maximum slot number is 212-1=4095. Note - that the value 212-1 denotes zero operands.
    -

    Instruction Format 2

    -

    This format encodes the opcode, type and two operands into a single - uint32_vbr as follows:

    - + + + + + + + + + + + + + + + + + + + + + + +
    0-1constant "1"These two bits must be the value 1 which +identifies this as an instruction of format 1.
    2-7opcodeSpecifies the opcode of the instruction. Note +that the maximum opcode value is 63.
    8-19unsignedSpecifies the slot number of the type for +this instruction. Maximum slot number is 212-1=4095.
    20-31unsignedSpecifies the slot number of the value for +the first operand. Maximum slot number is 212-1=4095. Note +that the value 212-1 denotes zero operands.
    +

    Instruction Format 2

    +

    This format encodes the opcode, type and two operands into a single uint32_vbr as follows:

    + + - - - - - - - - - - - - - - - - - -
    Bits Type Field Description
    0-1constant "2"These two bits must be the value 2 which identifies - this as an instruction of format 2.
    2-7opcodeSpecifies the opcode of the instruction. Note that - the maximum opcode value is 63.
    8-15unsignedSpecifies the slot number of the type for this - instruction. Maximum slot number is 28-1=255.
    16-23unsignedSpecifies the slot number of the value for the - first operand. Maximum slot number is 28-1=255.
    24-31unsignedSpecifies the slot number of the value for the - second operand. Maximum slot number is 28-1=255.
    -

    Instruction Format 3

    -

    This format encodes the opcode, type and three operands into a single - uint32_vbr as follows:

    - + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    0-1constant "2"These two bits must be the value 2 which +identifies this as an instruction of format 2.
    2-7opcodeSpecifies the opcode of the instruction. Note +that the maximum opcode value is 63.
    8-15unsignedSpecifies the slot number of the type for +this instruction. Maximum slot number is 28-1=255.
    16-23unsignedSpecifies the slot number of the value for +the first operand. Maximum slot number is 28-1=255.
    24-31unsignedSpecifies the slot number of the value for +the second operand. Maximum slot number is 28-1=255.
    +

    Instruction Format 3

    +

    This format encodes the opcode, type and three operands into a +single uint32_vbr as follows:

    + + - - - - - - - - - - - - - - - - - - - -
    Bits Type Field Description
    0-1constant "3"These two bits must be the value 3 which identifies - this as an instruction of format 3.
    2-7opcodeSpecifies the opcode of the instruction. Note that - the maximum opcode value is 63.
    8-13unsignedSpecifies the slot number of the type for this - instruction. Maximum slot number is 26-1=63.
    14-19unsignedSpecifies the slot number of the value for the - first operand. Maximum slot number is 26-1=63.
    20-25unsignedSpecifies the slot number of the value for the - second operand. Maximum slot number is 26-1=63.
    26-31unsignedSpecifies the slot number of the value for the - third operand. Maximum slot number is 26-1=63.
    + + 0-1 + constant "3" + These two bits must be the value 3 which +identifies this as an instruction of format 3. + + + 2-7 + opcode + Specifies the opcode of the instruction. Note +that the maximum opcode value is 63. + + + 8-13 + unsigned + Specifies the slot number of the type for +this instruction. Maximum slot number is 26-1=63. + + + 14-19 + unsigned + Specifies the slot number of the value for +the first operand. Maximum slot number is 26-1=63. + + + 20-25 + unsigned + Specifies the slot number of the value for +the second operand. Maximum slot number is 26-1=63. + + + 26-31 + unsigned + Specifies the slot number of the value for +the third operand. Maximum slot number is 26-1=63. + + +
    -
    Symbol Table

    A symbol table can be put out in conjunction with a module or a function. A symbol table is a list of type planes. Each type plane starts with the number -of entries in the plane and the type plane's slot number (so the type can be -looked up in the global type pool). For each entry in a type plane, the slot -number of the value and the name associated with that value are written. The -format is given in the table below.

    - - - - - - - - - - - - - - - - - - - - -
    TypeField Description
    unsignedSymbol Table Identifier (0x13)
    unsignedSize in bytes of the symbol table block.
    uint32_vbrNumber of entries in type plane
    symtab_entry*Provides the slot number of the type and its name.
    symtab_plane*A type plane containing value slot number and name - for all values of the same type.
    -
    - - -
    Symbol Table Plane -
    -
    -

    A symbol table plane provides the symbol table entries for all values of - a common type. The encoding is given in the following table:

    - - - - - - - - - - - - - - -
    TypeField Description
    uint32_vbrNumber of entries in this plane.
    uint32_vbrSlot number of type for this plane.
    symtab_entry+The symbol table entries for this plane.
    -
    - - -
    Symbol Table Entry -
    -
    -

    A symbol table entry provides the assocation between a type or value's - slot number and the name given to that type or value. The format is given - in the following table:

    - - - - - - - - - - - - - - +of entries in the plane and the type plane's slot number (so the type +can be looked up in the global type pool). For each entry in a type +plane, the slot number of the value and the name associated with that +value are written. The format is given in the table below.

    +
    TypeField Description
    uint32_vbrSlot number of the type or value being given a name. -
    uint32_vbrLength of the character array that follows.
    char+The characters of the name.
    + + + + + + + + + + + + + + + + + + + + + + +
    TypeField Description
    block
    +     		Symbol Table Identifier (0x04)
    uint32_vbrNumber of entries in type plane
    symtab_entry*Provides the slot number of the type and its +name.
    symtab_plane*A type plane containing value slot number and +name for all values of the same type.
    +
    + +
    Symbol Table +Plane +
    +
    +

    A symbol table plane provides the symbol table entries for all +values of a common type. The encoding is given in the following table:

    + + + + + + + + + + + + + + + + + + + +
    TypeField Description
    uint32_vbrNumber of entries in this plane.
    uint32_vbrSlot number of type for this plane.
    symtab_entry+The symbol table entries for this plane.
    +
    + +
    Symbol Table +Entry +
    +
    +

    A symbol table entry provides the assocation between a type or +value's slot number and the name given to that type or value. The +format is given in the following table:

    + + + + + + + + + + + + + + + + + + +
    TypeField Description
    uint24_vbrSlot number of the type or value being given +a name.
    uint32_vbrLength of the character array that follows.
    char+The characters of the name.
    - -
    Version Differences
    +
    Version Differences +
    -

    This section describes the differences in the Bytecode Format across LLVM -versions. The versions are listed in reverse order because it assumes the -current version is as documented in the previous sections. Each section here +

    This section describes the differences in the Bytecode Format across +LLVM +versions. The versions are listed in reverse order because it assumes +the current version is as documented in the previous sections. Each +section here describes the differences between that version and the one that follows.

    - -
    -Version 1.2 Differences From 1.3
    +
    Version 1.2 Differences +From 1.3
    Type Derives From Value
    -

    In version 1.2, the Type class in the LLVM IR derives from the Value class. - This is not the case in version 1.3. Consequently, in version 1.2 the notion - of a "Type Type" was used to write out values that were Types. The types - always occuped plane 12 (corresponding to the TypeTyID) of any type planed - set of values. In 1.3 this representation is not convenient because the - TypeTyID (12) is not present and its value is now used for LabelTyID. - Consequently, the data structures written that involve types do so by writing - all the types first and then each of the value planes according to those - types. In version 1.2, the types would have been written intermingled with - the values.

    -
    - - -
    Restricted getelementptr Types
    -
    -

    In version 1.2, the getelementptr instruction required a ubyte type index - for accessing a structure field and a long type index for accessing an array - element. Consequently, it was only possible to access structures of 255 or - fewer elements. Starting in version 1.3, this restriction was lifted. - Structures must now be indexed with uint constants. Arrays may now be - indexed with int, uint, long, or ulong typed values. - The consequence of this was that the bytecode format had to - change in order to accommodate the larger range of structure indices.

    +

    In version 1.2, the Type class in the LLVM IR derives from the Value +class. This is not the case in version 1.3. Consequently, in version +1.2 the notion of a "Type Type" was used to write out values that were +Types. The types always occuped plane 12 (corresponding to the +TypeTyID) of any type planed set of values. In 1.3 this representation +is not convenient because the TypeTyID (12) is not present and its +value is now used for LabelTyID. Consequently, the data structures +written that involve types do so by writing all the types first and +then each of the value planes according to those types. In version 1.2, +the types would have been written intermingled with the values.

    +
    + +
    Restricted getelementptr Types
    +
    +

    In version 1.2, the getelementptr instruction required a ubyte type +index for accessing a structure field and a long type index for +accessing an array element. Consequently, it was only possible to +access structures of 255 or fewer elements. Starting in version 1.3, +this restriction was lifted. Structures must now be indexed with uint +constants. Arrays may now be indexed with int, uint, long, or ulong +typed values. The consequence of this was that the bytecode format had +to change in order to accommodate the larger range of structure indices.

    +
    + +
    Short Block Headers
    +
    +

    In version 1.2, block headers were always 8 bytes being comprised of +both an unsigned integer type and an unsigned integer size. For very +small modules, these block headers turn out to be a large fraction of +the total bytecode file size. In an attempt to make these small files +smaller, the type and size information was encoded into a single +unsigned integer (4 bytes) comprised of 5 bits for the block type +(maximum 31 block types) and 27 bits for the block size (max +~134MBytes). These limits seemed sufficient for any blocks or sizes +forseen in the future. Note that the module block, which encloses all +the other blocks is still written as 8 bytes since bytecode files +larger than 134MBytes might be possible.

    +
    + +
    Dependent Libraries and Target Triples
    +
    +

    In version 1.2, the bytecode format does not store module's target +triple or dependent. These fields have been added to the end of the module global info block. The purpose of these +fields is to allow a front end compiler to specifiy that the generated +module is specific to a particular target triple (operating +system/manufacturer/processor) which makes it non-portable; and to +allow front end compilers to specify the list of libraries that the +module depends on for successful linking.

    +
    + +
    Types Restricted to 24-bits
    +
    +

    In version 1.2, type slot identifiers were written as 32-bit VBR +quantities. In 1.3 this has been reduced to 24-bits in order to ensure +that it is not possible to overflow the type field of a global variable +definition. 24-bits for type slot numbers is deemed sufficient for any +practical use of LLVM.

    - -
    -Version 1.1 Differences From 1.2
    + +
    Version 1.1 Differences +From 1.2
    Explicit Primitive Zeros
    -

    In version 1.1, the zero value for primitives was explicitly encoded into - the bytecode format. Since these zero values are constant values in the - LLVM IR and never change, there is no reason to explicitly encode them. This - explicit encoding was removed in version 1.2.

    +

    In version 1.1, the zero value for primitives was explicitly encoded +into the bytecode format. Since these zero values are constant values +in the LLVM IR and never change, there is no reason to explicitly +encode them. This explicit encoding was removed in version 1.2.

    -
    Inconsistent Module Global Info
    -

    In version 1.1, the Module Global Info block was not aligned causing the - next block to be read in on an unaligned boundary. This problem was corrected - in version 1.2.

    +

    In version 1.1, the Module Global Info block was not aligned causing +the next block to be read in on an unaligned boundary. This problem was +corrected in version 1.2.
    +
    +

    - -
    -Version 1.0 Differences From 1.1
    +
    Version 1.0 Differences +From 1.1

    None. Version 1.0 and 1.1 bytecode formats are identical.

    -
    -
    - Valid CSS! - Valid HTML 4.01! - - Reid Spencer and - Chris Lattner
    - The LLVM Compiler Infrastructure
    - Last modified: $Date: 2004/07/07 15:02:54 $ +
    Valid CSS! +Valid HTML 4.01! +Reid Spencer and Chris Lattner
    +The LLVM Compiler Infrastructure
    +Last modified: $Date: 2004/07/29 00:13:04 $
    - - + + From lattner at cs.uiuc.edu Wed Jul 28 20:33:15 2004 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Wed, 28 Jul 2004 20:33:15 -0500 Subject: [llvm-commits] CVS: llvm/test/Regression/Transforms/BasicAA/2004-07-28-MustAliasbug.llx Message-ID: <200407290133.UAA29733@apoc.cs.uiuc.edu> Changes in directory llvm/test/Regression/Transforms/BasicAA: 2004-07-28-MustAliasbug.llx added (r1.1) --- Log message: Due to a bug in BasicAA, DSE is incorrectly deleting the first store in this testcase, causing the miscompilation of MallocBench/gs. --- Diffs of the changes: (+10 -0) Index: llvm/test/Regression/Transforms/BasicAA/2004-07-28-MustAliasbug.llx diff -c /dev/null llvm/test/Regression/Transforms/BasicAA/2004-07-28-MustAliasbug.llx:1.1 *** /dev/null Wed Jul 28 20:33:15 2004 --- llvm/test/Regression/Transforms/BasicAA/2004-07-28-MustAliasbug.llx Wed Jul 28 20:33:05 2004 *************** *** 0 **** --- 1,10 ---- + ; RUN: llvm-as < %s | opt -dse | llvm-dis | grep 'store int 0' + + void %test({int,int }* %P) { + %Q = getelementptr {int,int}* %P, int 1 + %X = getelementptr {int,int}* %Q, int 0, uint 1 + %Y = getelementptr {int,int}* %Q, int 1, uint 1 + store int 0, int* %X + store int 1, int* %Y + ret void + } From lattner at cs.uiuc.edu Wed Jul 28 20:34:20 2004 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Wed, 28 Jul 2004 20:34:20 -0500 Subject: [llvm-commits] CVS: llvm/test/Regression/Transforms/BasicAA/2003-02-26-AccessSizeTest.ll 2003-03-04-GEPCrash.ll 2003-04-22-GEPProblem.ll 2003-04-25-GEPCrash.ll 2003-05-21-GEP-Problem.ll 2003-06-01-AliasCrash.ll 2003-07-03-BasicAACrash.ll 2003-09-19-LocalArgument.ll 2003-11-04-SimpleCases.ll 2003-12-11-ConstExprGEP.ll 2004-01-29-InvariantMemory.llx 2004-07-28-MustAliasbug.llx featuretest.ll gcsetest.ll licmtest.ll Message-ID: <200407290134.UAA29757@apoc.cs.uiuc.edu> Changes in directory llvm/test/Regression/Transforms/BasicAA: 2003-02-26-AccessSizeTest.ll (r1.2) removed 2003-03-04-GEPCrash.ll (r1.2) removed 2003-04-22-GEPProblem.ll (r1.2) removed 2003-04-25-GEPCrash.ll (r1.2) removed 2003-05-21-GEP-Problem.ll (r1.3) removed 2003-06-01-AliasCrash.ll (r1.3) removed 2003-07-03-BasicAACrash.ll (r1.2) removed 2003-09-19-LocalArgument.ll (r1.1) removed 2003-11-04-SimpleCases.ll (r1.1) removed 2003-12-11-ConstExprGEP.ll (r1.2) removed 2004-01-29-InvariantMemory.llx (r1.1) removed 2004-07-28-MustAliasbug.llx (r1.1) removed featuretest.ll (r1.9) removed gcsetest.ll (r1.6) removed licmtest.ll (r1.8) removed --- Log message: Move Transforms/BasicAA to Analysis/BasicAA --- Diffs of the changes: (+0 -0) From gaeke at cs.uiuc.edu Wed Jul 28 23:15:46 2004 From: gaeke at cs.uiuc.edu (Brian Gaeke) Date: Wed, 28 Jul 2004 23:15:46 -0500 (CDT) Subject: [llvm-commits] CVS: llvm/lib/Target/SparcV9/SparcV9RegClassInfo.cpp Message-ID: <200407290415.XAA14131@seraph.cs.uiuc.edu> Changes in directory llvm/lib/Target/SparcV9: SparcV9RegClassInfo.cpp updated: 1.37 -> 1.38 --- Log message: Remove mustSaveAcrossCalls flag, which isn't ever read, and its mutator, markForSaveAcrossCalls. --- Diffs of the changes: (+0 -2) Index: llvm/lib/Target/SparcV9/SparcV9RegClassInfo.cpp diff -u llvm/lib/Target/SparcV9/SparcV9RegClassInfo.cpp:1.37 llvm/lib/Target/SparcV9/SparcV9RegClassInfo.cpp:1.38 --- llvm/lib/Target/SparcV9/SparcV9RegClassInfo.cpp:1.37 Sun Jul 4 07:19:56 2004 +++ llvm/lib/Target/SparcV9/SparcV9RegClassInfo.cpp Wed Jul 28 23:15:36 2004 @@ -113,7 +113,6 @@ // get the live range corresponding to live var // since LR span across calls, must save across calls // - LR->markForSaveAcrossCalls(); if (DEBUG_RA) std::cerr << "\n Colored after SECOND search with col " << c; } @@ -306,7 +305,6 @@ if (ColorFound >= 0) { LR->setColor(ColorFound); // first color found in preferred order - LR->markForSaveAcrossCalls(); } else { // we are here because no color could be found LR->markForSpill(); // no color found - must spill From gaeke at cs.uiuc.edu Wed Jul 28 23:15:46 2004 From: gaeke at cs.uiuc.edu (Brian Gaeke) Date: Wed, 28 Jul 2004 23:15:46 -0500 (CDT) Subject: [llvm-commits] CVS: llvm/lib/Target/SparcV9/RegAlloc/LiveRange.h Message-ID: <200407290415.XAA14138@seraph.cs.uiuc.edu> Changes in directory llvm/lib/Target/SparcV9/RegAlloc: LiveRange.h updated: 1.25 -> 1.26 --- Log message: Remove mustSaveAcrossCalls flag, which isn't ever read, and its mutator, markForSaveAcrossCalls. --- Diffs of the changes: (+1 -8) Index: llvm/lib/Target/SparcV9/RegAlloc/LiveRange.h diff -u llvm/lib/Target/SparcV9/RegAlloc/LiveRange.h:1.25 llvm/lib/Target/SparcV9/RegAlloc/LiveRange.h:1.26 --- llvm/lib/Target/SparcV9/RegAlloc/LiveRange.h:1.25 Tue Nov 11 16:41:33 2003 +++ llvm/lib/Target/SparcV9/RegAlloc/LiveRange.h Wed Jul 28 23:15:36 2004 @@ -40,11 +40,6 @@ int Color; // color assigned to this live range bool mustSpill; // whether this LR must be spilt - /// mustSaveAcrossCalls - whether this LR must be saved accross calls - /// ***TODO REMOVE this - /// - bool mustSaveAcrossCalls; - /// SuggestedColor - if this LR has a suggested color, can it be /// really alloated? A suggested color cannot be allocated when the /// suggested color is volatile and when there are call @@ -77,7 +72,7 @@ public: LiveRange() { Color = SuggestedColor = -1; // not yet colored - mustSpill = mustSaveAcrossCalls = false; + mustSpill = false; MyRegClass = 0; UserIGNode = 0; doesSpanAcrossCalls = false; @@ -133,8 +128,6 @@ return SpilledStackOffsetFromFP; } - inline void markForSaveAcrossCalls() { mustSaveAcrossCalls = true; } - inline void setUserIGNode(IGNode *IGN) { assert(!UserIGNode); UserIGNode = IGN; } From gaeke at cs.uiuc.edu Wed Jul 28 23:22:40 2004 From: gaeke at cs.uiuc.edu (Brian Gaeke) Date: Wed, 28 Jul 2004 23:22:40 -0500 (CDT) Subject: [llvm-commits] CVS: llvm/include/Support/SetVector.h Message-ID: <200407290422.XAA14171@seraph.cs.uiuc.edu> Changes in directory llvm/include/Support: SetVector.h updated: 1.4 -> 1.5 --- Log message: Fix typo in comment. --- Diffs of the changes: (+1 -1) Index: llvm/include/Support/SetVector.h diff -u llvm/include/Support/SetVector.h:1.4 llvm/include/Support/SetVector.h:1.5 --- llvm/include/Support/SetVector.h:1.4 Sun Jul 25 06:07:02 2004 +++ llvm/include/Support/SetVector.h Wed Jul 28 23:22:30 2004 @@ -26,7 +26,7 @@ /// This class provides a way to keep a set of things that also has the /// property of a deterministic iteration order. The order of iteration is the /// order of insertion. -/// @breif A vector that has set insertion semantics. +/// @brief A vector that has set insertion semantics. template class SetVector { public: From gaeke at cs.uiuc.edu Wed Jul 28 23:25:54 2004 From: gaeke at cs.uiuc.edu (Brian Gaeke) Date: Wed, 28 Jul 2004 23:25:54 -0500 (CDT) Subject: [llvm-commits] CVS: llvm/lib/Target/SparcV9/RegAlloc/LiveRange.h Message-ID: <200407290425.XAA14192@seraph.cs.uiuc.edu> Changes in directory llvm/lib/Target/SparcV9/RegAlloc: LiveRange.h updated: 1.26 -> 1.27 --- Log message: Fix a few typoes and grammaroes in comments. --- Diffs of the changes: (+5 -5) Index: llvm/lib/Target/SparcV9/RegAlloc/LiveRange.h diff -u llvm/lib/Target/SparcV9/RegAlloc/LiveRange.h:1.26 llvm/lib/Target/SparcV9/RegAlloc/LiveRange.h:1.27 --- llvm/lib/Target/SparcV9/RegAlloc/LiveRange.h:1.26 Wed Jul 28 23:15:36 2004 +++ llvm/lib/Target/SparcV9/RegAlloc/LiveRange.h Wed Jul 28 23:25:43 2004 @@ -40,8 +40,8 @@ int Color; // color assigned to this live range bool mustSpill; // whether this LR must be spilt - /// SuggestedColor - if this LR has a suggested color, can it be - /// really alloated? A suggested color cannot be allocated when the + /// SuggestedColor - if this LR has a suggested color, can it + /// really be allocated? A suggested color cannot be allocated when the /// suggested color is volatile and when there are call /// interferences. /// @@ -60,12 +60,12 @@ /// int SpilledStackOffsetFromFP; - /// HasSpillOffset 0 Whether this live range has a spill offset + /// HasSpillOffset - True iff this live range has a spill offset. /// bool HasSpillOffset; - /// The spill cost of this live range. Calculated using loop depth of - /// each reference to each Value in the live range + /// SpillCost - The spill cost of this live range. Calculated using loop depth + /// of each reference to each Value in the live range. /// unsigned SpillCost; From gaeke at cs.uiuc.edu Thu Jul 29 01:43:17 2004 From: gaeke at cs.uiuc.edu (Brian Gaeke) Date: Thu, 29 Jul 2004 01:43:17 -0500 (CDT) Subject: [llvm-commits] CVS: llvm/lib/Target/SparcV9/RegAlloc/LiveRange.h Message-ID: <200407290643.BAA02105@seraph.cs.uiuc.edu> Changes in directory llvm/lib/Target/SparcV9/RegAlloc: LiveRange.h updated: 1.27 -> 1.28 --- Log message: Don't derive from ValueSet to implement class LiveRange; instead, use a SetVector data member. Add << operator for LiveRanges (a dumb one, for now.) --- Diffs of the changes: (+25 -8) Index: llvm/lib/Target/SparcV9/RegAlloc/LiveRange.h diff -u llvm/lib/Target/SparcV9/RegAlloc/LiveRange.h:1.27 llvm/lib/Target/SparcV9/RegAlloc/LiveRange.h:1.28 --- llvm/lib/Target/SparcV9/RegAlloc/LiveRange.h:1.27 Wed Jul 28 23:25:43 2004 +++ llvm/lib/Target/SparcV9/RegAlloc/LiveRange.h Thu Jul 29 01:43:06 2004 @@ -7,11 +7,8 @@ // //===----------------------------------------------------------------------===// // -// Implements a live range using a ValueSet. A LiveRange is a simple set -// of Values. -// -// Since the Value pointed by a use is the same as of its def, it is sufficient -// to keep only defs in a LiveRange. +// Implements a live range using a SetVector of Value *s. We keep only +// defs in a LiveRange. // //===----------------------------------------------------------------------===// @@ -19,15 +16,23 @@ #define LIVERANGE_H #include "llvm/Value.h" -#include "llvm/CodeGen/ValueSet.h" +#include "Support/SetVector.h" +#include namespace llvm { class RegClass; class IGNode; -class LiveRange : public ValueSet { - RegClass *MyRegClass; // register class (e.g., int, FP) for this LR +class LiveRange { +public: + typedef SetVector ValueContainerType; + typedef ValueContainerType::iterator iterator; + typedef ValueContainerType::const_iterator const_iterator; + +private: + ValueContainerType MyValues; // Values in this LiveRange + RegClass *MyRegClass; // register class (e.g., int, FP) for this LR /// doesSpanAcrossCalls - Does this live range span across calls? /// This information is used by graph coloring algo to avoid allocating @@ -70,6 +75,13 @@ unsigned SpillCost; public: + iterator begin() { return MyValues.begin(); } + const_iterator begin() const { return MyValues.begin(); } + iterator end() { return MyValues.end(); } + const_iterator end() const { return MyValues.end(); } + bool insert(const Value *&X) { return MyValues.insert (X); } + void insert(iterator b, iterator e) { MyValues.insert (b, e); } + LiveRange() { Color = SuggestedColor = -1; // not yet colored mustSpill = false; @@ -172,6 +184,11 @@ } }; +static inline std::ostream &operator << (std::ostream &os, const LiveRange &lr) { + os << "LiveRange@" << (void *)(&lr); + return os; +}; + } // End llvm namespace #endif From gaeke at cs.uiuc.edu Thu Jul 29 01:43:18 2004 From: gaeke at cs.uiuc.edu (Brian Gaeke) Date: Thu, 29 Jul 2004 01:43:18 -0500 (CDT) Subject: [llvm-commits] CVS: llvm/lib/Target/SparcV9/RegAlloc/LiveRangeInfo.cpp Message-ID: <200407290643.BAA02112@seraph.cs.uiuc.edu> Changes in directory llvm/lib/Target/SparcV9/RegAlloc: LiveRangeInfo.cpp updated: 1.54 -> 1.55 --- Log message: Get rid of calls to void llvm::printSet(const ValueSet &). Use LiveRange's iterator types and operations instead of ValueSet's. --- Diffs of the changes: (+3 -5) Index: llvm/lib/Target/SparcV9/RegAlloc/LiveRangeInfo.cpp diff -u llvm/lib/Target/SparcV9/RegAlloc/LiveRangeInfo.cpp:1.54 llvm/lib/Target/SparcV9/RegAlloc/LiveRangeInfo.cpp:1.55 --- llvm/lib/Target/SparcV9/RegAlloc/LiveRangeInfo.cpp:1.54 Sun Jul 4 07:19:56 2004 +++ llvm/lib/Target/SparcV9/RegAlloc/LiveRangeInfo.cpp Thu Jul 29 01:43:08 2004 @@ -65,11 +65,9 @@ assert(! (L1->hasColor() && L2->hasColor()) || L1->getColor() == L2->getColor()); - set_union(*L1, *L2); // add elements of L2 to L1 - - for(ValueSet::iterator L2It = L2->begin(); L2It != L2->end(); ++L2It) { - //assert(( L1->getTypeID() == L2->getTypeID()) && "Merge:Different types"); + L2->insert (L1->begin(), L1->end()); // add elements of L2 to L1 + for(LiveRange::iterator L2It = L2->begin(); L2It != L2->end(); ++L2It) { L1->insert(*L2It); // add the var in L2 to L1 LiveRangeMap[*L2It] = L1; // now the elements in L2 should map //to L1 @@ -408,7 +406,7 @@ std::cerr << "LR# " << igNode->getIndex(); else std::cerr << "LR# " << ""; - std::cerr << "\t:Values = "; printSet(*HMI->second); std::cerr << "\n"; + std::cerr << "\t:Values = " << *HMI->second << "\n"; } } } From gaeke at cs.uiuc.edu Thu Jul 29 01:43:18 2004 From: gaeke at cs.uiuc.edu (Brian Gaeke) Date: Thu, 29 Jul 2004 01:43:18 -0500 (CDT) Subject: [llvm-commits] CVS: llvm/lib/Target/SparcV9/SparcV9RegClassInfo.cpp Message-ID: <200407290643.BAA02119@seraph.cs.uiuc.edu> Changes in directory llvm/lib/Target/SparcV9: SparcV9RegClassInfo.cpp updated: 1.38 -> 1.39 --- Log message: Get rid of calls to void llvm::printSet(const ValueSet &). Use LiveRange's iterator types and operations instead of ValueSet's. --- Diffs of the changes: (+8 -9) Index: llvm/lib/Target/SparcV9/SparcV9RegClassInfo.cpp diff -u llvm/lib/Target/SparcV9/SparcV9RegClassInfo.cpp:1.38 llvm/lib/Target/SparcV9/SparcV9RegClassInfo.cpp:1.39 --- llvm/lib/Target/SparcV9/SparcV9RegClassInfo.cpp:1.38 Wed Jul 28 23:15:36 2004 +++ llvm/lib/Target/SparcV9/SparcV9RegClassInfo.cpp Thu Jul 29 01:43:08 2004 @@ -41,10 +41,9 @@ { LiveRange *LR = Node->getParentLR(); - if (DEBUG_RA) { - std::cerr << "\nColoring LR [CallInt=" << LR->isCallInterference() <<"]:"; - printSet(*LR); - } + if (DEBUG_RA) + std::cerr << "\nColoring LR [CallInt=" << LR->isCallInterference() <<"]:" + << *LR << "\n"; if (LR->hasSuggestedColor()) { unsigned SugCol = LR->getSuggestedColor(); @@ -61,8 +60,8 @@ std::cerr << "\n Couldn't alloc Sug col - LR volatile & calls interf"; } } else if (DEBUG_RA) { // can't allocate the suggested col - std::cerr << "\n Could NOT allocate the suggested color (already used) "; - printSet(*LR); std::cerr << "\n"; + std::cerr << "\n Could NOT allocate the suggested color (already used) " + << *LR << "\n"; } } @@ -162,7 +161,7 @@ #ifndef NDEBUG // Let's just make sure values of two different types have not been // coalesced into this LR. - for (ValueSet::const_iterator I=ccLR->begin(), E=ccLR->end(); I!=E; ++I) { + for (LiveRange::const_iterator I=ccLR->begin(), E=ccLR->end(); I!=E; ++I) { const Type* ccType = (*I)->getType(); assert((ccReg == xcc && (isa(ccType) || ccType == Type::LongTy)) || @@ -251,8 +250,8 @@ LR->setColor( LR->getSuggestedColor() ); return; } else if (DEBUG_RA) { // can't allocate the suggested col - std::cerr << " Could NOT allocate the suggested color for LR "; - printSet(*LR); std::cerr << "\n"; + std::cerr << " Could NOT allocate the suggested color for LR " << *LR + << "\n"; } } From gaeke at cs.uiuc.edu Thu Jul 29 01:43:19 2004 From: gaeke at cs.uiuc.edu (Brian Gaeke) Date: Thu, 29 Jul 2004 01:43:19 -0500 (CDT) Subject: [llvm-commits] CVS: llvm/lib/Target/SparcV9/RegAlloc/PhyRegAlloc.cpp InterferenceGraph.cpp Message-ID: <200407290643.BAA02128@seraph.cs.uiuc.edu> Changes in directory llvm/lib/Target/SparcV9/RegAlloc: PhyRegAlloc.cpp updated: 1.155 -> 1.156 InterferenceGraph.cpp updated: 1.20 -> 1.21 --- Log message: Get rid of calls to void llvm::printSet(const ValueSet &). --- Diffs of the changes: (+10 -21) Index: llvm/lib/Target/SparcV9/RegAlloc/PhyRegAlloc.cpp diff -u llvm/lib/Target/SparcV9/RegAlloc/PhyRegAlloc.cpp:1.155 llvm/lib/Target/SparcV9/RegAlloc/PhyRegAlloc.cpp:1.156 --- llvm/lib/Target/SparcV9/RegAlloc/PhyRegAlloc.cpp:1.155 Tue Jul 27 12:43:24 2004 +++ llvm/lib/Target/SparcV9/RegAlloc/PhyRegAlloc.cpp Thu Jul 29 01:43:09 2004 @@ -175,22 +175,17 @@ LIt != LEnd; ++LIt) { // get the live range corresponding to live var - LiveRange *const LR = LRI->getLiveRangeForValue(*LIt ); + LiveRange *const LR = LRI->getLiveRangeForValue(*LIt); // LR can be null if it is a const since a const // doesn't have a dominating def - see Assumptions above - if (LR ) { - if (DEBUG_RA >= RA_DEBUG_Interference) { - std::cerr << "\n\tLR after Call: "; - printSet(*LR); - } + if (LR) { + if (DEBUG_RA >= RA_DEBUG_Interference) + std::cerr << "\n\tLR after Call: " << *LR << "\n"; LR->setCallInterference(); - if (DEBUG_RA >= RA_DEBUG_Interference) { - std::cerr << "\n ++After adding call interference for LR: " ; - printSet(*LR); - } + if (DEBUG_RA >= RA_DEBUG_Interference) + std::cerr << "\n ++After adding call interference for LR: " << *LR << "\n"; } - } // Now find the LR of the return value of the call Index: llvm/lib/Target/SparcV9/RegAlloc/InterferenceGraph.cpp diff -u llvm/lib/Target/SparcV9/RegAlloc/InterferenceGraph.cpp:1.20 llvm/lib/Target/SparcV9/RegAlloc/InterferenceGraph.cpp:1.21 --- llvm/lib/Target/SparcV9/RegAlloc/InterferenceGraph.cpp:1.20 Sun Jul 4 07:19:56 2004 +++ llvm/lib/Target/SparcV9/RegAlloc/InterferenceGraph.cpp Thu Jul 29 01:43:09 2004 @@ -157,9 +157,7 @@ assertIGNode(this, SrcNode); if( DEBUG_RA >= RA_DEBUG_Interference) { - std::cerr << "Merging LRs: \""; printSet(*LR1); - std::cerr << "\" and \""; printSet(*LR2); - std::cerr << "\"\n"; + std::cerr << "Merging LRs: \"" << *LR1 << "\" and \"" << *LR2 << "\"\n"; } unsigned SrcDegree = SrcNode->getNumOfNeighbors(); @@ -240,13 +238,9 @@ void InterferenceGraph::printIGNodeList() const { for(unsigned i=0; i < IGNodeList.size() ; ++i) { const IGNode *const Node = IGNodeList[i]; - - if (Node) { - std::cerr << " [" << Node->getIndex() << "] "; - printSet(*Node->getParentLR()); - //int Deg = Node->getCurDegree(); - std::cerr << "\t <# of Neighs: " << Node->getNumOfNeighbors() << ">\n"; - } + if (Node) + std::cerr << " [" << Node->getIndex() << "] " << *Node->getParentLR() + << "\t <# of Neighbors: " << Node->getNumOfNeighbors() << ">\n"; } } From gaeke at cs.uiuc.edu Thu Jul 29 01:43:20 2004 From: gaeke at cs.uiuc.edu (Brian Gaeke) Date: Thu, 29 Jul 2004 01:43:20 -0500 (CDT) Subject: [llvm-commits] CVS: llvm/lib/Target/SparcV9/RegAlloc/LiveRangeInfo.h Message-ID: <200407290643.BAA02135@seraph.cs.uiuc.edu> Changes in directory llvm/lib/Target/SparcV9/RegAlloc: LiveRangeInfo.h updated: 1.24 -> 1.25 --- Log message: Get rid of a few dead method declarations. --- Diffs of the changes: (+0 -7) Index: llvm/lib/Target/SparcV9/RegAlloc/LiveRangeInfo.h diff -u llvm/lib/Target/SparcV9/RegAlloc/LiveRangeInfo.h:1.24 llvm/lib/Target/SparcV9/RegAlloc/LiveRangeInfo.h:1.25 --- llvm/lib/Target/SparcV9/RegAlloc/LiveRangeInfo.h:1.24 Wed Jun 2 21:45:09 2004 +++ llvm/lib/Target/SparcV9/RegAlloc/LiveRangeInfo.h Thu Jul 29 01:43:10 2004 @@ -63,7 +63,6 @@ std::vector CallRetInstrList; // a list of all call/ret instrs - //------------ Private methods (see LiveRangeInfo.cpp for description)------- LiveRange* createNewLiveRange (const Value* Def, @@ -75,13 +74,7 @@ void unionAndUpdateLRs (LiveRange *L1, LiveRange *L2); - void addInterference (const Instruction *Inst, - const ValueSet *LVSet); - void suggestRegs4CallRets (); - - const Function *getMethod () const { return Meth; } - public: LiveRangeInfo(const Function *F, From lattner at cs.uiuc.edu Thu Jul 29 02:56:49 2004 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Thu, 29 Jul 2004 02:56:49 -0500 Subject: [llvm-commits] CVS: llvm/lib/Analysis/BasicAliasAnalysis.cpp Message-ID: <200407290756.CAA32567@apoc.cs.uiuc.edu> Changes in directory llvm/lib/Analysis: BasicAliasAnalysis.cpp updated: 1.50 -> 1.51 --- Log message: Fix test/Regression/Analysis/BasicAA/2004-07-28-MustAliasbug.llx This also fixes the miscompilation of MallocBench/gs with dead store elimination enabled. --- Diffs of the changes: (+9 -5) Index: llvm/lib/Analysis/BasicAliasAnalysis.cpp diff -u llvm/lib/Analysis/BasicAliasAnalysis.cpp:1.50 llvm/lib/Analysis/BasicAliasAnalysis.cpp:1.51 --- llvm/lib/Analysis/BasicAliasAnalysis.cpp:1.50 Mon Jul 26 21:18:52 2004 +++ llvm/lib/Analysis/BasicAliasAnalysis.cpp Thu Jul 29 02:56:39 2004 @@ -322,11 +322,15 @@ BasePtr1 = GetGEPOperands(V1, GEP1Ops); BasePtr2 = GetGEPOperands(V2, GEP2Ops); - AliasResult GAlias = - CheckGEPInstructions(BasePtr1->getType(), GEP1Ops, V1Size, - BasePtr2->getType(), GEP2Ops, V2Size); - if (GAlias != MayAlias) - return GAlias; + // If GetGEPOperands were able to fold to the same must-aliased pointer, + // do the comparison. + if (BasePtr1 == BasePtr2) { + AliasResult GAlias = + CheckGEPInstructions(BasePtr1->getType(), GEP1Ops, V1Size, + BasePtr2->getType(), GEP2Ops, V2Size); + if (GAlias != MayAlias) + return GAlias; + } } } From alkis at cs.uiuc.edu Thu Jul 29 07:17:44 2004 From: alkis at cs.uiuc.edu (Alkis Evlogimenos) Date: Thu, 29 Jul 2004 07:17:44 -0500 Subject: [llvm-commits] CVS: llvm/lib/Transforms/Utils/UnifyFunctionExitNodes.cpp Message-ID: <200407291217.HAA32515@zion.cs.uiuc.edu> Changes in directory llvm/lib/Transforms/Utils: UnifyFunctionExitNodes.cpp updated: 1.30 -> 1.31 --- Log message: Merge i*.h headers into Instructions.h as part of bug403: http://llvm.cs.uiuc.edu/PR403 . --- Diffs of the changes: (+1 -2) Index: llvm/lib/Transforms/Utils/UnifyFunctionExitNodes.cpp diff -u llvm/lib/Transforms/Utils/UnifyFunctionExitNodes.cpp:1.30 llvm/lib/Transforms/Utils/UnifyFunctionExitNodes.cpp:1.31 --- llvm/lib/Transforms/Utils/UnifyFunctionExitNodes.cpp:1.30 Wed May 26 16:38:14 2004 +++ llvm/lib/Transforms/Utils/UnifyFunctionExitNodes.cpp Thu Jul 29 07:17:33 2004 @@ -18,8 +18,7 @@ #include "llvm/Transforms/Scalar.h" #include "llvm/BasicBlock.h" #include "llvm/Function.h" -#include "llvm/iTerminators.h" -#include "llvm/iPHINode.h" +#include "llvm/Instructions.h" #include "llvm/Type.h" using namespace llvm; From alkis at cs.uiuc.edu Thu Jul 29 07:17:44 2004 From: alkis at cs.uiuc.edu (Alkis Evlogimenos) Date: Thu, 29 Jul 2004 07:17:44 -0500 Subject: [llvm-commits] CVS: llvm/lib/VMCore/iSwitch.cpp iOperators.cpp iMemory.cpp iCall.cpp iBranch.cpp Message-ID: <200407291217.HAA32516@zion.cs.uiuc.edu> Changes in directory llvm/lib/VMCore: iSwitch.cpp updated: 1.13 -> 1.14 iOperators.cpp updated: 1.29 -> 1.30 iMemory.cpp updated: 1.43 -> 1.44 iCall.cpp updated: 1.27 -> 1.28 iBranch.cpp updated: 1.14 -> 1.15 --- Log message: Merge i*.h headers into Instructions.h as part of bug403: http://llvm.cs.uiuc.edu/PR403 . --- Diffs of the changes: (+5 -6) Index: llvm/lib/VMCore/iSwitch.cpp diff -u llvm/lib/VMCore/iSwitch.cpp:1.13 llvm/lib/VMCore/iSwitch.cpp:1.14 --- llvm/lib/VMCore/iSwitch.cpp:1.13 Wed May 26 17:07:18 2004 +++ llvm/lib/VMCore/iSwitch.cpp Thu Jul 29 07:17:33 2004 @@ -11,7 +11,7 @@ // //===----------------------------------------------------------------------===// -#include "llvm/iTerminators.h" +#include "llvm/Instructions.h" #include "llvm/BasicBlock.h" using namespace llvm; Index: llvm/lib/VMCore/iOperators.cpp diff -u llvm/lib/VMCore/iOperators.cpp:1.29 llvm/lib/VMCore/iOperators.cpp:1.30 --- llvm/lib/VMCore/iOperators.cpp:1.29 Sun Jun 27 13:38:48 2004 +++ llvm/lib/VMCore/iOperators.cpp Thu Jul 29 07:17:33 2004 @@ -11,7 +11,7 @@ // //===----------------------------------------------------------------------===// -#include "llvm/iOperators.h" +#include "llvm/Instructions.h" #include "llvm/Type.h" #include "llvm/Constants.h" #include "llvm/BasicBlock.h" Index: llvm/lib/VMCore/iMemory.cpp diff -u llvm/lib/VMCore/iMemory.cpp:1.43 llvm/lib/VMCore/iMemory.cpp:1.44 --- llvm/lib/VMCore/iMemory.cpp:1.43 Tue Jul 27 02:30:02 2004 +++ llvm/lib/VMCore/iMemory.cpp Thu Jul 29 07:17:33 2004 @@ -11,7 +11,7 @@ // //===----------------------------------------------------------------------===// -#include "llvm/iMemory.h" +#include "llvm/Instructions.h" #include "llvm/Constants.h" #include "llvm/DerivedTypes.h" using namespace llvm; Index: llvm/lib/VMCore/iCall.cpp diff -u llvm/lib/VMCore/iCall.cpp:1.27 llvm/lib/VMCore/iCall.cpp:1.28 --- llvm/lib/VMCore/iCall.cpp:1.27 Sat Jul 17 19:03:48 2004 +++ llvm/lib/VMCore/iCall.cpp Thu Jul 29 07:17:33 2004 @@ -11,8 +11,7 @@ // //===----------------------------------------------------------------------===// -#include "llvm/iOther.h" -#include "llvm/iTerminators.h" +#include "llvm/Instructions.h" #include "llvm/Constants.h" #include "llvm/DerivedTypes.h" #include "llvm/Function.h" Index: llvm/lib/VMCore/iBranch.cpp diff -u llvm/lib/VMCore/iBranch.cpp:1.14 llvm/lib/VMCore/iBranch.cpp:1.15 --- llvm/lib/VMCore/iBranch.cpp:1.14 Wed May 26 17:07:18 2004 +++ llvm/lib/VMCore/iBranch.cpp Thu Jul 29 07:17:33 2004 @@ -12,7 +12,7 @@ // //===----------------------------------------------------------------------===// -#include "llvm/iTerminators.h" +#include "llvm/Instructions.h" #include "llvm/BasicBlock.h" #include "llvm/Type.h" using namespace llvm; From alkis at cs.uiuc.edu Thu Jul 29 07:17:44 2004 From: alkis at cs.uiuc.edu (Alkis Evlogimenos) Date: Thu, 29 Jul 2004 07:17:44 -0500 Subject: [llvm-commits] CVS: llvm/lib/Transforms/TransformInternals.cpp LevelRaise.cpp ExprTypeConvert.cpp Message-ID: <200407291217.HAA32529@zion.cs.uiuc.edu> Changes in directory llvm/lib/Transforms: TransformInternals.cpp updated: 1.45 -> 1.46 LevelRaise.cpp updated: 1.99 -> 1.100 ExprTypeConvert.cpp updated: 1.95 -> 1.96 --- Log message: Merge i*.h headers into Instructions.h as part of bug403: http://llvm.cs.uiuc.edu/PR403 . --- Diffs of the changes: (+3 -6) Index: llvm/lib/Transforms/TransformInternals.cpp diff -u llvm/lib/Transforms/TransformInternals.cpp:1.45 llvm/lib/Transforms/TransformInternals.cpp:1.46 --- llvm/lib/Transforms/TransformInternals.cpp:1.45 Sun Apr 4 20:28:59 2004 +++ llvm/lib/Transforms/TransformInternals.cpp Thu Jul 29 07:17:33 2004 @@ -16,7 +16,7 @@ #include "llvm/Type.h" #include "llvm/Analysis/Expressions.h" #include "llvm/Function.h" -#include "llvm/iOther.h" +#include "llvm/Instructions.h" using namespace llvm; static const Type *getStructOffsetStep(const StructType *STy, uint64_t &Offset, Index: llvm/lib/Transforms/LevelRaise.cpp diff -u llvm/lib/Transforms/LevelRaise.cpp:1.99 llvm/lib/Transforms/LevelRaise.cpp:1.100 --- llvm/lib/Transforms/LevelRaise.cpp:1.99 Sat Jul 17 19:19:45 2004 +++ llvm/lib/Transforms/LevelRaise.cpp Thu Jul 29 07:17:33 2004 @@ -16,8 +16,7 @@ #include "llvm/Transforms/Scalar.h" #include "llvm/Transforms/Utils/Local.h" #include "TransformInternals.h" -#include "llvm/iOther.h" -#include "llvm/iMemory.h" +#include "llvm/Instructions.h" #include "llvm/Pass.h" #include "llvm/Transforms/Utils/BasicBlockUtils.h" #include "Support/CommandLine.h" Index: llvm/lib/Transforms/ExprTypeConvert.cpp diff -u llvm/lib/Transforms/ExprTypeConvert.cpp:1.95 llvm/lib/Transforms/ExprTypeConvert.cpp:1.96 --- llvm/lib/Transforms/ExprTypeConvert.cpp:1.95 Wed Jul 21 15:50:33 2004 +++ llvm/lib/Transforms/ExprTypeConvert.cpp Thu Jul 29 07:17:34 2004 @@ -15,9 +15,7 @@ #include "TransformInternals.h" #include "llvm/Constants.h" -#include "llvm/iOther.h" -#include "llvm/iPHINode.h" -#include "llvm/iMemory.h" +#include "llvm/Instructions.h" #include "llvm/Analysis/Expressions.h" #include "Support/STLExtras.h" #include "Support/Debug.h" From alkis at cs.uiuc.edu Thu Jul 29 07:17:44 2004 From: alkis at cs.uiuc.edu (Alkis Evlogimenos) Date: Thu, 29 Jul 2004 07:17:44 -0500 Subject: [llvm-commits] CVS: llvm/include/llvm/Instructions.h iTerminators.h iPHINode.h iOther.h iOperators.h iMemory.h Message-ID: <200407291217.HAA32559@zion.cs.uiuc.edu> Changes in directory llvm/include/llvm: Instructions.h updated: 1.2 -> 1.3 iTerminators.h (r1.45) removed iPHINode.h (r1.19) removed iOther.h (r1.47) removed iOperators.h (r1.16) removed iMemory.h (r1.48) removed --- Log message: Merge i*.h headers into Instructions.h as part of bug403: http://llvm.cs.uiuc.edu/PR403 . --- Diffs of the changes: (+1176 -5) Index: llvm/include/llvm/Instructions.h diff -u llvm/include/llvm/Instructions.h:1.2 llvm/include/llvm/Instructions.h:1.3 --- llvm/include/llvm/Instructions.h:1.2 Mon Oct 20 15:19:14 2003 +++ llvm/include/llvm/Instructions.h Thu Jul 29 07:17:34 2004 @@ -16,10 +16,1181 @@ #ifndef LLVM_INSTRUCTIONS_H #define LLVM_INSTRUCTIONS_H -#include "llvm/iTerminators.h" // Terminator instructions -#include "llvm/iPHINode.h" // The PHI node instruction -#include "llvm/iOperators.h" // Binary operator instructions -#include "llvm/iMemory.h" // Memory related instructions -#include "llvm/iOther.h" // Everything else +#include "llvm/Instruction.h" +#include "llvm/InstrTypes.h" + +namespace llvm { + +struct BasicBlock; +class PointerType; + +//===----------------------------------------------------------------------===// +// AllocationInst Class +//===----------------------------------------------------------------------===// + +/// AllocationInst - This class is the common base class of MallocInst and +/// AllocaInst. +/// +class AllocationInst : public Instruction { +protected: + void init(const Type *Ty, Value *ArraySize, unsigned iTy); + AllocationInst(const Type *Ty, Value *ArraySize, unsigned iTy, + const std::string &Name = "", Instruction *InsertBefore = 0); + AllocationInst(const Type *Ty, Value *ArraySize, unsigned iTy, + const std::string &Name, BasicBlock *InsertAtEnd); + +public: + + /// isArrayAllocation - Return true if there is an allocation size parameter + /// to the allocation instruction that is not 1. + /// + bool isArrayAllocation() const; + + /// getArraySize - Get the number of element allocated, for a simple + /// allocation of a single element, this will return a constant 1 value. + /// + inline const Value *getArraySize() const { return Operands[0]; } + inline Value *getArraySize() { return Operands[0]; } + + /// getType - Overload to return most specific pointer type + /// + inline const PointerType *getType() const { + return reinterpret_cast(Instruction::getType()); + } + + /// getAllocatedType - Return the type that is being allocated by the + /// instruction. + /// + const Type *getAllocatedType() const; + + virtual Instruction *clone() const = 0; + + // Methods for support type inquiry through isa, cast, and dyn_cast: + static inline bool classof(const AllocationInst *) { return true; } + static inline bool classof(const Instruction *I) { + return I->getOpcode() == Instruction::Alloca || + I->getOpcode() == Instruction::Malloc; + } + static inline bool classof(const Value *V) { + return isa(V) && classof(cast(V)); + } +}; + + +//===----------------------------------------------------------------------===// +// MallocInst Class +//===----------------------------------------------------------------------===// + +/// MallocInst - an instruction to allocated memory on the heap +/// +class MallocInst : public AllocationInst { + MallocInst(const MallocInst &MI); +public: + explicit MallocInst(const Type *Ty, Value *ArraySize = 0, + const std::string &Name = "", + Instruction *InsertBefore = 0) + : AllocationInst(Ty, ArraySize, Malloc, Name, InsertBefore) {} + MallocInst(const Type *Ty, Value *ArraySize, const std::string &Name, + BasicBlock *InsertAtEnd) + : AllocationInst(Ty, ArraySize, Malloc, Name, InsertAtEnd) {} + + virtual Instruction *clone() const { + return new MallocInst(*this); + } + + // Methods for support type inquiry through isa, cast, and dyn_cast: + static inline bool classof(const MallocInst *) { return true; } + static inline bool classof(const Instruction *I) { + return (I->getOpcode() == Instruction::Malloc); + } + static inline bool classof(const Value *V) { + return isa(V) && classof(cast(V)); + } +}; + + +//===----------------------------------------------------------------------===// +// AllocaInst Class +//===----------------------------------------------------------------------===// + +/// AllocaInst - an instruction to allocate memory on the stack +/// +class AllocaInst : public AllocationInst { + AllocaInst(const AllocaInst &); +public: + explicit AllocaInst(const Type *Ty, Value *ArraySize = 0, + const std::string &Name = "", + Instruction *InsertBefore = 0) + : AllocationInst(Ty, ArraySize, Alloca, Name, InsertBefore) {} + AllocaInst(const Type *Ty, Value *ArraySize, const std::string &Name, + BasicBlock *InsertAtEnd) + : AllocationInst(Ty, ArraySize, Alloca, Name, InsertAtEnd) {} + + virtual Instruction *clone() const { + return new AllocaInst(*this); + } + + // Methods for support type inquiry through isa, cast, and dyn_cast: + static inline bool classof(const AllocaInst *) { return true; } + static inline bool classof(const Instruction *I) { + return (I->getOpcode() == Instruction::Alloca); + } + static inline bool classof(const Value *V) { + return isa(V) && classof(cast(V)); + } +}; + + +//===----------------------------------------------------------------------===// +// FreeInst Class +//===----------------------------------------------------------------------===// + +/// FreeInst - an instruction to deallocate memory +/// +class FreeInst : public Instruction { + void init(Value *Ptr); + +public: + explicit FreeInst(Value *Ptr, Instruction *InsertBefore = 0); + FreeInst(Value *Ptr, BasicBlock *InsertAfter); + + virtual Instruction *clone() const { return new FreeInst(Operands[0]); } + + virtual bool mayWriteToMemory() const { return true; } + + // Methods for support type inquiry through isa, cast, and dyn_cast: + static inline bool classof(const FreeInst *) { return true; } + static inline bool classof(const Instruction *I) { + return (I->getOpcode() == Instruction::Free); + } + static inline bool classof(const Value *V) { + return isa(V) && classof(cast(V)); + } +}; + + +//===----------------------------------------------------------------------===// +// LoadInst Class +//===----------------------------------------------------------------------===// + +/// LoadInst - an instruction for reading from memory +/// +class LoadInst : public Instruction { + LoadInst(const LoadInst &LI) : Instruction(LI.getType(), Load) { + Volatile = LI.isVolatile(); + init(LI.Operands[0]); + } + bool Volatile; // True if this is a volatile load + void init(Value *Ptr); +public: + LoadInst(Value *Ptr, const std::string &Name, Instruction *InsertBefore); + LoadInst(Value *Ptr, const std::string &Name, BasicBlock *InsertAtEnd); + LoadInst(Value *Ptr, const std::string &Name = "", bool isVolatile = false, + Instruction *InsertBefore = 0); + LoadInst(Value *Ptr, const std::string &Name, bool isVolatile, + BasicBlock *InsertAtEnd); + + /// isVolatile - Return true if this is a load from a volatile memory + /// location. + /// + bool isVolatile() const { return Volatile; } + + /// setVolatile - Specify whether this is a volatile load or not. + /// + void setVolatile(bool V) { Volatile = V; } + + virtual Instruction *clone() const { return new LoadInst(*this); } + + virtual bool mayWriteToMemory() const { return isVolatile(); } + + Value *getPointerOperand() { return getOperand(0); } + const Value *getPointerOperand() const { return getOperand(0); } + static unsigned getPointerOperandIndex() { return 0U; } + + // Methods for support type inquiry through isa, cast, and dyn_cast: + static inline bool classof(const LoadInst *) { return true; } + static inline bool classof(const Instruction *I) { + return I->getOpcode() == Instruction::Load; + } + static inline bool classof(const Value *V) { + return isa(V) && classof(cast(V)); + } +}; + + +//===----------------------------------------------------------------------===// +// StoreInst Class +//===----------------------------------------------------------------------===// + +/// StoreInst - an instruction for storing to memory +/// +class StoreInst : public Instruction { + StoreInst(const StoreInst &SI) : Instruction(SI.getType(), Store) { + Volatile = SI.isVolatile(); + init(SI.Operands[0], SI.Operands[1]); + } + bool Volatile; // True if this is a volatile store + void init(Value *Val, Value *Ptr); +public: + StoreInst(Value *Val, Value *Ptr, Instruction *InsertBefore); + StoreInst(Value *Val, Value *Ptr, BasicBlock *InsertAtEnd); + StoreInst(Value *Val, Value *Ptr, bool isVolatile = false, + Instruction *InsertBefore = 0); + StoreInst(Value *Val, Value *Ptr, bool isVolatile, BasicBlock *InsertAtEnd); + + + /// isVolatile - Return true if this is a load from a volatile memory + /// location. + /// + bool isVolatile() const { return Volatile; } + + /// setVolatile - Specify whether this is a volatile load or not. + /// + void setVolatile(bool V) { Volatile = V; } + + virtual Instruction *clone() const { return new StoreInst(*this); } + + virtual bool mayWriteToMemory() const { return true; } + + Value *getPointerOperand() { return getOperand(1); } + const Value *getPointerOperand() const { return getOperand(1); } + static unsigned getPointerOperandIndex() { return 1U; } + + // Methods for support type inquiry through isa, cast, and dyn_cast: + static inline bool classof(const StoreInst *) { return true; } + static inline bool classof(const Instruction *I) { + return I->getOpcode() == Instruction::Store; + } + static inline bool classof(const Value *V) { + return isa(V) && classof(cast(V)); + } +}; + + +//===----------------------------------------------------------------------===// +// GetElementPtrInst Class +//===----------------------------------------------------------------------===// + +/// GetElementPtrInst - an instruction for type-safe pointer arithmetic to +/// access elements of arrays and structs +/// +class GetElementPtrInst : public Instruction { + GetElementPtrInst(const GetElementPtrInst &EPI) + : Instruction((static_cast(&EPI)->getType()), + GetElementPtr) { + Operands.reserve(EPI.Operands.size()); + for (unsigned i = 0, E = EPI.Operands.size(); i != E; ++i) + Operands.push_back(Use(EPI.Operands[i], this)); + } + void init(Value *Ptr, const std::vector &Idx); + void init(Value *Ptr, Value *Idx0, Value *Idx1); +public: + /// Constructors - Create a getelementptr instruction with a base pointer an + /// list of indices. The first ctor can optionally insert before an existing + /// instruction, the second appends the new instruction to the specified + /// BasicBlock. + GetElementPtrInst(Value *Ptr, const std::vector &Idx, + const std::string &Name = "", Instruction *InsertBefore =0); + GetElementPtrInst(Value *Ptr, const std::vector &Idx, + const std::string &Name, BasicBlock *InsertAtEnd); + + /// Constructors - These two constructors are convenience methods because two + /// index getelementptr instructions are so common. + GetElementPtrInst(Value *Ptr, Value *Idx0, Value *Idx1, + const std::string &Name = "", Instruction *InsertBefore =0); + GetElementPtrInst(Value *Ptr, Value *Idx0, Value *Idx1, + const std::string &Name, BasicBlock *InsertAtEnd); + + virtual Instruction *clone() const { return new GetElementPtrInst(*this); } + + // getType - Overload to return most specific pointer type... + inline const PointerType *getType() const { + return reinterpret_cast(Instruction::getType()); + } + + /// getIndexedType - Returns the type of the element that would be loaded with + /// a load instruction with the specified parameters. + /// + /// A null type is returned if the indices are invalid for the specified + /// pointer type. + /// + static const Type *getIndexedType(const Type *Ptr, + const std::vector &Indices, + bool AllowStructLeaf = false); + static const Type *getIndexedType(const Type *Ptr, Value *Idx0, Value *Idx1, + bool AllowStructLeaf = false); + + inline op_iterator idx_begin() { return op_begin()+1; } + inline const_op_iterator idx_begin() const { return op_begin()+1; } + inline op_iterator idx_end() { return op_end(); } + inline const_op_iterator idx_end() const { return op_end(); } + + Value *getPointerOperand() { + return getOperand(0); + } + const Value *getPointerOperand() const { + return getOperand(0); + } + static unsigned getPointerOperandIndex() { + return 0U; // get index for modifying correct operand + } + + inline unsigned getNumIndices() const { // Note: always non-negative + return getNumOperands() - 1; + } + + inline bool hasIndices() const { + return getNumOperands() > 1; + } + + // Methods for support type inquiry through isa, cast, and dyn_cast: + static inline bool classof(const GetElementPtrInst *) { return true; } + static inline bool classof(const Instruction *I) { + return (I->getOpcode() == Instruction::GetElementPtr); + } + static inline bool classof(const Value *V) { + return isa(V) && classof(cast(V)); + } +}; + +//===----------------------------------------------------------------------===// +// SetCondInst Class +//===----------------------------------------------------------------------===// + +/// SetCondInst class - Represent a setCC operator, where CC is eq, ne, lt, gt, +/// le, or ge. +/// +class SetCondInst : public BinaryOperator { + BinaryOps OpType; +public: + SetCondInst(BinaryOps Opcode, Value *LHS, Value *RHS, + const std::string &Name = "", Instruction *InsertBefore = 0); + SetCondInst(BinaryOps Opcode, Value *LHS, Value *RHS, + const std::string &Name, BasicBlock *InsertAtEnd); + + /// getInverseCondition - Return the inverse of the current condition opcode. + /// For example seteq -> setne, setgt -> setle, setlt -> setge, etc... + /// + BinaryOps getInverseCondition() const { + return getInverseCondition(getOpcode()); + } + + /// getInverseCondition - Static version that you can use without an + /// instruction available. + /// + static BinaryOps getInverseCondition(BinaryOps Opcode); + + /// getSwappedCondition - Return the condition opcode that would be the result + /// of exchanging the two operands of the setcc instruction without changing + /// the result produced. Thus, seteq->seteq, setle->setge, setlt->setgt, etc. + /// + BinaryOps getSwappedCondition() const { + return getSwappedCondition(getOpcode()); + } + + /// getSwappedCondition - Static version that you can use without an + /// instruction available. + /// + static BinaryOps getSwappedCondition(BinaryOps Opcode); + + + // Methods for support type inquiry through isa, cast, and dyn_cast: + static inline bool classof(const SetCondInst *) { return true; } + static inline bool classof(const Instruction *I) { + return I->getOpcode() == SetEQ || I->getOpcode() == SetNE || + I->getOpcode() == SetLE || I->getOpcode() == SetGE || + I->getOpcode() == SetLT || I->getOpcode() == SetGT; + } + static inline bool classof(const Value *V) { + return isa(V) && classof(cast(V)); + } +}; + +//===----------------------------------------------------------------------===// +// CastInst Class +//===----------------------------------------------------------------------===// + +/// CastInst - This class represents a cast from Operand[0] to the type of +/// the instruction (i->getType()). +/// +class CastInst : public Instruction { + CastInst(const CastInst &CI) : Instruction(CI.getType(), Cast) { + Operands.reserve(1); + Operands.push_back(Use(CI.Operands[0], this)); + } + void init(Value *S) { + Operands.reserve(1); + Operands.push_back(Use(S, this)); + } +public: + CastInst(Value *S, const Type *Ty, const std::string &Name = "", + Instruction *InsertBefore = 0) + : Instruction(Ty, Cast, Name, InsertBefore) { + init(S); + } + CastInst(Value *S, const Type *Ty, const std::string &Name, + BasicBlock *InsertAtEnd) + : Instruction(Ty, Cast, Name, InsertAtEnd) { + init(S); + } + + virtual Instruction *clone() const { return new CastInst(*this); } + + // Methods for support type inquiry through isa, cast, and dyn_cast: + static inline bool classof(const CastInst *) { return true; } + static inline bool classof(const Instruction *I) { + return I->getOpcode() == Cast; + } + static inline bool classof(const Value *V) { + return isa(V) && classof(cast(V)); + } +}; + + +//===----------------------------------------------------------------------===// +// CallInst Class +//===----------------------------------------------------------------------===// + +/// CallInst - This class represents a function call, abstracting a target +/// machine's calling convention. +/// +class CallInst : public Instruction { + CallInst(const CallInst &CI); + void init(Value *Func, const std::vector &Params); + void init(Value *Func, Value *Actual1, Value *Actual2); + void init(Value *Func, Value *Actual); + void init(Value *Func); + +public: + CallInst(Value *F, const std::vector &Par, + const std::string &Name = "", Instruction *InsertBefore = 0); + CallInst(Value *F, const std::vector &Par, + const std::string &Name, BasicBlock *InsertAtEnd); + + // Alternate CallInst ctors w/ two actuals, w/ one actual and no + // actuals, respectively. + CallInst(Value *F, Value *Actual1, Value *Actual2, + const std::string& Name = "", Instruction *InsertBefore = 0); + CallInst(Value *F, Value *Actual1, Value *Actual2, + const std::string& Name, BasicBlock *InsertAtEnd); + CallInst(Value *F, Value *Actual, const std::string& Name = "", + Instruction *InsertBefore = 0); + CallInst(Value *F, Value *Actual, const std::string& Name, + BasicBlock *InsertAtEnd); + explicit CallInst(Value *F, const std::string &Name = "", + Instruction *InsertBefore = 0); + explicit CallInst(Value *F, const std::string &Name, + BasicBlock *InsertAtEnd); + + virtual Instruction *clone() const { return new CallInst(*this); } + bool mayWriteToMemory() const { return true; } + + // FIXME: These methods should be inline once we eliminate + // ConstantPointerRefs! + const Function *getCalledFunction() const; + Function *getCalledFunction(); + + // getCalledValue - Get a pointer to a method that is invoked by this inst. + inline const Value *getCalledValue() const { return Operands[0]; } + inline Value *getCalledValue() { return Operands[0]; } + + // Methods for support type inquiry through isa, cast, and dyn_cast: + static inline bool classof(const CallInst *) { return true; } + static inline bool classof(const Instruction *I) { + return I->getOpcode() == Instruction::Call; + } + static inline bool classof(const Value *V) { + return isa(V) && classof(cast(V)); + } +}; + + +//===----------------------------------------------------------------------===// +// ShiftInst Class +//===----------------------------------------------------------------------===// + +/// ShiftInst - This class represents left and right shift instructions. +/// +class ShiftInst : public Instruction { + ShiftInst(const ShiftInst &SI) : Instruction(SI.getType(), SI.getOpcode()) { + Operands.reserve(2); + Operands.push_back(Use(SI.Operands[0], this)); + Operands.push_back(Use(SI.Operands[1], this)); + } + void init(OtherOps Opcode, Value *S, Value *SA) { + assert((Opcode == Shl || Opcode == Shr) && "ShiftInst Opcode invalid!"); + Operands.reserve(2); + Operands.push_back(Use(S, this)); + Operands.push_back(Use(SA, this)); + } + +public: + ShiftInst(OtherOps Opcode, Value *S, Value *SA, const std::string &Name = "", + Instruction *InsertBefore = 0) + : Instruction(S->getType(), Opcode, Name, InsertBefore) { + init(Opcode, S, SA); + } + ShiftInst(OtherOps Opcode, Value *S, Value *SA, const std::string &Name, + BasicBlock *InsertAtEnd) + : Instruction(S->getType(), Opcode, Name, InsertAtEnd) { + init(Opcode, S, SA); + } + + OtherOps getOpcode() const { + return static_cast(Instruction::getOpcode()); + } + + virtual Instruction *clone() const { return new ShiftInst(*this); } + + // Methods for support type inquiry through isa, cast, and dyn_cast: + static inline bool classof(const ShiftInst *) { return true; } + static inline bool classof(const Instruction *I) { + return (I->getOpcode() == Instruction::Shr) | + (I->getOpcode() == Instruction::Shl); + } + static inline bool classof(const Value *V) { + return isa(V) && classof(cast(V)); + } +}; + +//===----------------------------------------------------------------------===// +// SelectInst Class +//===----------------------------------------------------------------------===// + +/// SelectInst - This class represents the LLVM 'select' instruction. +/// +class SelectInst : public Instruction { + SelectInst(const SelectInst &SI) : Instruction(SI.getType(), SI.getOpcode()) { + Operands.reserve(3); + Operands.push_back(Use(SI.Operands[0], this)); + Operands.push_back(Use(SI.Operands[1], this)); + Operands.push_back(Use(SI.Operands[2], this)); + } + void init(Value *C, Value *S1, Value *S2) { + Operands.reserve(3); + Operands.push_back(Use(C, this)); + Operands.push_back(Use(S1, this)); + Operands.push_back(Use(S2, this)); + } + +public: + SelectInst(Value *C, Value *S1, Value *S2, const std::string &Name = "", + Instruction *InsertBefore = 0) + : Instruction(S1->getType(), Instruction::Select, Name, InsertBefore) { + init(C, S1, S2); + } + SelectInst(Value *C, Value *S1, Value *S2, const std::string &Name, + BasicBlock *InsertAtEnd) + : Instruction(S1->getType(), Instruction::Select, Name, InsertAtEnd) { + init(C, S1, S2); + } + + Value *getCondition() const { return Operands[0]; } + Value *getTrueValue() const { return Operands[1]; } + Value *getFalseValue() const { return Operands[2]; } + + OtherOps getOpcode() const { + return static_cast(Instruction::getOpcode()); + } + + virtual Instruction *clone() const { return new SelectInst(*this); } + + // Methods for support type inquiry through isa, cast, and dyn_cast: + static inline bool classof(const SelectInst *) { return true; } + static inline bool classof(const Instruction *I) { + return I->getOpcode() == Instruction::Select; + } + static inline bool classof(const Value *V) { + return isa(V) && classof(cast(V)); + } +}; + + +//===----------------------------------------------------------------------===// +// VANextInst Class +//===----------------------------------------------------------------------===// + +/// VANextInst - This class represents the va_next llvm instruction, which +/// advances a vararg list passed an argument of the specified type, returning +/// the resultant list. +/// +class VANextInst : public Instruction { + PATypeHolder ArgTy; + void init(Value *List) { + Operands.reserve(1); + Operands.push_back(Use(List, this)); + } + VANextInst(const VANextInst &VAN) + : Instruction(VAN.getType(), VANext), ArgTy(VAN.getArgType()) { + init(VAN.Operands[0]); + } + +public: + VANextInst(Value *List, const Type *Ty, const std::string &Name = "", + Instruction *InsertBefore = 0) + : Instruction(List->getType(), VANext, Name, InsertBefore), ArgTy(Ty) { + init(List); + } + VANextInst(Value *List, const Type *Ty, const std::string &Name, + BasicBlock *InsertAtEnd) + : Instruction(List->getType(), VANext, Name, InsertAtEnd), ArgTy(Ty) { + init(List); + } + + const Type *getArgType() const { return ArgTy; } + + virtual Instruction *clone() const { return new VANextInst(*this); } + + // Methods for support type inquiry through isa, cast, and dyn_cast: + static inline bool classof(const VANextInst *) { return true; } + static inline bool classof(const Instruction *I) { + return I->getOpcode() == VANext; + } + static inline bool classof(const Value *V) { + return isa(V) && classof(cast(V)); + } +}; + + +//===----------------------------------------------------------------------===// +// VAArgInst Class +//===----------------------------------------------------------------------===// + +/// VAArgInst - This class represents the va_arg llvm instruction, which returns +/// an argument of the specified type given a va_list. +/// +class VAArgInst : public Instruction { + void init(Value* List) { + Operands.reserve(1); + Operands.push_back(Use(List, this)); + } + VAArgInst(const VAArgInst &VAA) + : Instruction(VAA.getType(), VAArg) { + init(VAA.Operands[0]); + } +public: + VAArgInst(Value *List, const Type *Ty, const std::string &Name = "", + Instruction *InsertBefore = 0) + : Instruction(Ty, VAArg, Name, InsertBefore) { + init(List); + } + VAArgInst(Value *List, const Type *Ty, const std::string &Name, + BasicBlock *InsertAtEnd) + : Instruction(Ty, VAArg, Name, InsertAtEnd) { + init(List); + } + + virtual Instruction *clone() const { return new VAArgInst(*this); } + + // Methods for support type inquiry through isa, cast, and dyn_cast: + static inline bool classof(const VAArgInst *) { return true; } + static inline bool classof(const Instruction *I) { + return I->getOpcode() == VAArg; + } + static inline bool classof(const Value *V) { + return isa(V) && classof(cast(V)); + } +}; + +//===----------------------------------------------------------------------===// +// PHINode Class +//===----------------------------------------------------------------------===// + +// PHINode - The PHINode class is used to represent the magical mystical PHI +// node, that can not exist in nature, but can be synthesized in a computer +// scientist's overactive imagination. +// +class PHINode : public Instruction { + PHINode(const PHINode &PN); +public: + PHINode(const Type *Ty, const std::string &Name = "", + Instruction *InsertBefore = 0) + : Instruction(Ty, Instruction::PHI, Name, InsertBefore) { + } + + PHINode(const Type *Ty, const std::string &Name, BasicBlock *InsertAtEnd) + : Instruction(Ty, Instruction::PHI, Name, InsertAtEnd) { + } + + virtual Instruction *clone() const { return new PHINode(*this); } + + /// getNumIncomingValues - Return the number of incoming edges + /// + unsigned getNumIncomingValues() const { return Operands.size()/2; } + + /// getIncomingValue - Return incoming value #x + /// + Value *getIncomingValue(unsigned i) const { + assert(i*2 < Operands.size() && "Invalid value number!"); + return Operands[i*2]; + } + void setIncomingValue(unsigned i, Value *V) { + assert(i*2 < Operands.size() && "Invalid value number!"); + Operands[i*2] = V; + } + inline unsigned getOperandNumForIncomingValue(unsigned i) { + return i*2; + } + + /// getIncomingBlock - Return incoming basic block #x + /// + BasicBlock *getIncomingBlock(unsigned i) const { + assert(i*2+1 < Operands.size() && "Invalid value number!"); + return reinterpret_cast(Operands[i*2+1].get()); + } + void setIncomingBlock(unsigned i, BasicBlock *BB) { + assert(i*2+1 < Operands.size() && "Invalid value number!"); + Operands[i*2+1] = reinterpret_cast(BB); + } + unsigned getOperandNumForIncomingBlock(unsigned i) { + return i*2+1; + } + + /// addIncoming - Add an incoming value to the end of the PHI list + /// + void addIncoming(Value *V, BasicBlock *BB) { + assert(getType() == V->getType() && + "All operands to PHI node must be the same type as the PHI node!"); + Operands.push_back(Use(V, this)); + Operands.push_back(Use(reinterpret_cast(BB), this)); + } + + /// removeIncomingValue - Remove an incoming value. This is useful if a + /// predecessor basic block is deleted. The value removed is returned. + /// + /// If the last incoming value for a PHI node is removed (and DeletePHIIfEmpty + /// is true), the PHI node is destroyed and any uses of it are replaced with + /// dummy values. The only time there should be zero incoming values to a PHI + /// node is when the block is dead, so this strategy is sound. + /// + Value *removeIncomingValue(unsigned Idx, bool DeletePHIIfEmpty = true); + + Value *removeIncomingValue(const BasicBlock *BB, bool DeletePHIIfEmpty =true){ + int Idx = getBasicBlockIndex(BB); + assert(Idx >= 0 && "Invalid basic block argument to remove!"); + return removeIncomingValue(Idx, DeletePHIIfEmpty); + } + + /// getBasicBlockIndex - Return the first index of the specified basic + /// block in the value list for this PHI. Returns -1 if no instance. + /// + int getBasicBlockIndex(const BasicBlock *BB) const { + for (unsigned i = 0; i < Operands.size()/2; ++i) + if (getIncomingBlock(i) == BB) return i; + return -1; + } + + Value *getIncomingValueForBlock(const BasicBlock *BB) const { + return getIncomingValue(getBasicBlockIndex(BB)); + } + + /// Methods for support type inquiry through isa, cast, and dyn_cast: + static inline bool classof(const PHINode *) { return true; } + static inline bool classof(const Instruction *I) { + return I->getOpcode() == Instruction::PHI; + } + static inline bool classof(const Value *V) { + return isa(V) && classof(cast(V)); + } +}; + +//===----------------------------------------------------------------------===// +// ReturnInst Class +//===----------------------------------------------------------------------===// + +//===--------------------------------------------------------------------------- +/// ReturnInst - Return a value (possibly void), from a function. Execution +/// does not continue in this function any longer. +/// +class ReturnInst : public TerminatorInst { + ReturnInst(const ReturnInst &RI) : TerminatorInst(Instruction::Ret) { + if (RI.Operands.size()) { + assert(RI.Operands.size() == 1 && "Return insn can only have 1 operand!"); + Operands.reserve(1); + Operands.push_back(Use(RI.Operands[0], this)); + } + } + + void init(Value *RetVal) { + if (RetVal) { + assert(!isa(RetVal) && + "Cannot return basic block. Probably using the incorrect ctor"); + Operands.reserve(1); + Operands.push_back(Use(RetVal, this)); + } + } + +public: + // ReturnInst constructors: + // ReturnInst() - 'ret void' instruction + // ReturnInst(Value* X) - 'ret X' instruction + // ReturnInst( null, Inst *) - 'ret void' instruction, insert before I + // ReturnInst(Value* X, Inst *I) - 'ret X' instruction, insert before I + // ReturnInst( null, BB *B) - 'ret void' instruction, insert @ end of BB + // ReturnInst(Value* X, BB *B) - 'ret X' instruction, insert @ end of BB + ReturnInst(Value *RetVal = 0, Instruction *InsertBefore = 0) + : TerminatorInst(Instruction::Ret, InsertBefore) { + init(RetVal); + } + ReturnInst(Value *RetVal, BasicBlock *InsertAtEnd) + : TerminatorInst(Instruction::Ret, InsertAtEnd) { + init(RetVal); + } + ReturnInst(BasicBlock *InsertAtEnd) + : TerminatorInst(Instruction::Ret, InsertAtEnd) { + } + + virtual Instruction *clone() const { return new ReturnInst(*this); } + + inline const Value *getReturnValue() const { + return Operands.size() ? Operands[0].get() : 0; + } + inline Value *getReturnValue() { + return Operands.size() ? Operands[0].get() : 0; + } + + virtual const BasicBlock *getSuccessor(unsigned idx) const { + assert(0 && "ReturnInst has no successors!"); + abort(); + return 0; + } + virtual void setSuccessor(unsigned idx, BasicBlock *NewSucc); + virtual unsigned getNumSuccessors() const { return 0; } + + // Methods for support type inquiry through isa, cast, and dyn_cast: + static inline bool classof(const ReturnInst *) { return true; } + static inline bool classof(const Instruction *I) { + return (I->getOpcode() == Instruction::Ret); + } + static inline bool classof(const Value *V) { + return isa(V) && classof(cast(V)); + } +}; + +//===----------------------------------------------------------------------===// +// BranchInst Class +//===----------------------------------------------------------------------===// + +//===--------------------------------------------------------------------------- +/// BranchInst - Conditional or Unconditional Branch instruction. +/// +class BranchInst : public TerminatorInst { + BranchInst(const BranchInst &BI); + void init(BasicBlock *IfTrue); + void init(BasicBlock *True, BasicBlock *False, Value *Cond); +public: + // BranchInst constructors (where {B, T, F} are blocks, and C is a condition): + // BranchInst(BB *B) - 'br B' + // BranchInst(BB* T, BB *F, Value *C) - 'br C, T, F' + // BranchInst(BB* B, Inst *I) - 'br B' insert before I + // BranchInst(BB* T, BB *F, Value *C, Inst *I) - 'br C, T, F', insert before I + // BranchInst(BB* B, BB *I) - 'br B' insert at end + // BranchInst(BB* T, BB *F, Value *C, BB *I) - 'br C, T, F', insert at end + BranchInst(BasicBlock *IfTrue, Instruction *InsertBefore = 0) + : TerminatorInst(Instruction::Br, InsertBefore) { + init(IfTrue); + } + BranchInst(BasicBlock *IfTrue, BasicBlock *IfFalse, Value *Cond, + Instruction *InsertBefore = 0) + : TerminatorInst(Instruction::Br, InsertBefore) { + init(IfTrue, IfFalse, Cond); + } + + BranchInst(BasicBlock *IfTrue, BasicBlock *InsertAtEnd) + : TerminatorInst(Instruction::Br, InsertAtEnd) { + init(IfTrue); + } + + BranchInst(BasicBlock *IfTrue, BasicBlock *IfFalse, Value *Cond, + BasicBlock *InsertAtEnd) + : TerminatorInst(Instruction::Br, InsertAtEnd) { + init(IfTrue, IfFalse, Cond); + } + + virtual Instruction *clone() const { return new BranchInst(*this); } + + inline bool isUnconditional() const { return Operands.size() == 1; } + inline bool isConditional() const { return Operands.size() == 3; } + + inline Value *getCondition() const { + assert(isConditional() && "Cannot get condition of an uncond branch!"); + return Operands[2].get(); + } + + void setCondition(Value *V) { + assert(isConditional() && "Cannot set condition of unconditional branch!"); + setOperand(2, V); + } + + // setUnconditionalDest - Change the current branch to an unconditional branch + // targeting the specified block. + // + void setUnconditionalDest(BasicBlock *Dest) { + if (isConditional()) Operands.erase(Operands.begin()+1, Operands.end()); + Operands[0] = reinterpret_cast(Dest); + } + + virtual const BasicBlock *getSuccessor(unsigned i) const { + assert(i < getNumSuccessors() && "Successor # out of range for Branch!"); + return (i == 0) ? cast(Operands[0].get()) : + cast(Operands[1].get()); + } + inline BasicBlock *getSuccessor(unsigned idx) { + const BranchInst *BI = this; + return const_cast(BI->getSuccessor(idx)); + } + + virtual void setSuccessor(unsigned idx, BasicBlock *NewSucc) { + assert(idx < getNumSuccessors() && "Successor # out of range for Branch!"); + Operands[idx] = reinterpret_cast(NewSucc); + } + + virtual unsigned getNumSuccessors() const { return 1+isConditional(); } + + // Methods for support type inquiry through isa, cast, and dyn_cast: + static inline bool classof(const BranchInst *) { return true; } + static inline bool classof(const Instruction *I) { + return (I->getOpcode() == Instruction::Br); + } + static inline bool classof(const Value *V) { + return isa(V) && classof(cast(V)); + } +}; + +//===----------------------------------------------------------------------===// +// SwitchInst Class +//===----------------------------------------------------------------------===// + +//===--------------------------------------------------------------------------- +/// SwitchInst - Multiway switch +/// +class SwitchInst : public TerminatorInst { + // Operand[0] = Value to switch on + // Operand[1] = Default basic block destination + // Operand[2n ] = Value to match + // Operand[2n+1] = BasicBlock to go to on match + SwitchInst(const SwitchInst &RI); + void init(Value *Value, BasicBlock *Default); + +public: + SwitchInst(Value *Value, BasicBlock *Default, Instruction *InsertBefore = 0) + : TerminatorInst(Instruction::Switch, InsertBefore) { + init(Value, Default); + } + SwitchInst(Value *Value, BasicBlock *Default, BasicBlock *InsertAtEnd) + : TerminatorInst(Instruction::Switch, InsertAtEnd) { + init(Value, Default); + } + + virtual Instruction *clone() const { return new SwitchInst(*this); } + + // Accessor Methods for Switch stmt + // + inline const Value *getCondition() const { return Operands[0]; } + inline Value *getCondition() { return Operands[0]; } + inline const BasicBlock *getDefaultDest() const { + return cast(Operands[1].get()); + } + inline BasicBlock *getDefaultDest() { + return cast(Operands[1].get()); + } + + /// getNumCases - return the number of 'cases' in this switch instruction. + /// Note that case #0 is always the default case. + unsigned getNumCases() const { + return Operands.size()/2; + } + + /// getCaseValue - Return the specified case value. Note that case #0, the + /// default destination, does not have a case value. + Constant *getCaseValue(unsigned i) { + assert(i && i < getNumCases() && "Illegal case value to get!"); + return getSuccessorValue(i); + } + + /// getCaseValue - Return the specified case value. Note that case #0, the + /// default destination, does not have a case value. + const Constant *getCaseValue(unsigned i) const { + assert(i && i < getNumCases() && "Illegal case value to get!"); + return getSuccessorValue(i); + } + + /// findCaseValue - Search all of the case values for the specified constant. + /// If it is explicitly handled, return the case number of it, otherwise + /// return 0 to indicate that it is handled by the default handler. + unsigned findCaseValue(const Constant *C) const { + for (unsigned i = 1, e = getNumCases(); i != e; ++i) + if (getCaseValue(i) == C) + return i; + return 0; + } + + /// addCase - Add an entry to the switch instruction... + /// + void addCase(Constant *OnVal, BasicBlock *Dest); + + /// removeCase - This method removes the specified successor from the switch + /// instruction. Note that this cannot be used to remove the default + /// destination (successor #0). + /// + void removeCase(unsigned idx); + + virtual const BasicBlock *getSuccessor(unsigned idx) const { + assert(idx < getNumSuccessors() &&"Successor idx out of range for switch!"); + return cast(Operands[idx*2+1].get()); + } + inline BasicBlock *getSuccessor(unsigned idx) { + assert(idx < getNumSuccessors() &&"Successor idx out of range for switch!"); + return cast(Operands[idx*2+1].get()); + } + + virtual void setSuccessor(unsigned idx, BasicBlock *NewSucc) { + assert(idx < getNumSuccessors() && "Successor # out of range for switch!"); + Operands[idx*2+1] = reinterpret_cast(NewSucc); + } + + // getSuccessorValue - Return the value associated with the specified + // successor. + inline const Constant *getSuccessorValue(unsigned idx) const { + assert(idx < getNumSuccessors() && "Successor # out of range!"); + return cast(Operands[idx*2].get()); + } + inline Constant *getSuccessorValue(unsigned idx) { + assert(idx < getNumSuccessors() && "Successor # out of range!"); + return cast(Operands[idx*2].get()); + } + virtual unsigned getNumSuccessors() const { return Operands.size()/2; } + + // Methods for support type inquiry through isa, cast, and dyn_cast: + static inline bool classof(const SwitchInst *) { return true; } + static inline bool classof(const Instruction *I) { + return (I->getOpcode() == Instruction::Switch); + } + static inline bool classof(const Value *V) { + return isa(V) && classof(cast(V)); + } +}; + +//===----------------------------------------------------------------------===// +// InvokeInst Class +//===----------------------------------------------------------------------===// + +//===--------------------------------------------------------------------------- +/// InvokeInst - Invoke instruction +/// +class InvokeInst : public TerminatorInst { + InvokeInst(const InvokeInst &BI); + void init(Value *Fn, BasicBlock *IfNormal, BasicBlock *IfException, + const std::vector &Params); +public: + InvokeInst(Value *Fn, BasicBlock *IfNormal, BasicBlock *IfException, + const std::vector &Params, const std::string &Name = "", + Instruction *InsertBefore = 0); + InvokeInst(Value *Fn, BasicBlock *IfNormal, BasicBlock *IfException, + const std::vector &Params, const std::string &Name, + BasicBlock *InsertAtEnd); + + virtual Instruction *clone() const { return new InvokeInst(*this); } + + bool mayWriteToMemory() const { return true; } + + /// getCalledFunction - Return the function called, or null if this is an + /// indirect function invocation... + /// + /// FIXME: These should be inlined once we get rid of ConstantPointerRefs! + /// + const Function *getCalledFunction() const; + Function *getCalledFunction(); + + // getCalledValue - Get a pointer to a function that is invoked by this inst. + inline const Value *getCalledValue() const { return Operands[0]; } + inline Value *getCalledValue() { return Operands[0]; } + + // get*Dest - Return the destination basic blocks... + inline const BasicBlock *getNormalDest() const { + return cast(Operands[1].get()); + } + inline BasicBlock *getNormalDest() { + return cast(Operands[1].get()); + } + inline const BasicBlock *getUnwindDest() const { + return cast(Operands[2].get()); + } + inline BasicBlock *getUnwindDest() { + return cast(Operands[2].get()); + } + + inline void setNormalDest(BasicBlock *B){ + Operands[1] = reinterpret_cast(B); + } + + inline void setUnwindDest(BasicBlock *B){ + Operands[2] = reinterpret_cast(B); + } + + virtual const BasicBlock *getSuccessor(unsigned i) const { + assert(i < 2 && "Successor # out of range for invoke!"); + return i == 0 ? getNormalDest() : getUnwindDest(); + } + inline BasicBlock *getSuccessor(unsigned i) { + assert(i < 2 && "Successor # out of range for invoke!"); + return i == 0 ? getNormalDest() : getUnwindDest(); + } + + virtual void setSuccessor(unsigned idx, BasicBlock *NewSucc) { + assert(idx < 2 && "Successor # out of range for invoke!"); + Operands[idx+1] = reinterpret_cast(NewSucc); + } + + virtual unsigned getNumSuccessors() const { return 2; } + + // Methods for support type inquiry through isa, cast, and dyn_cast: + static inline bool classof(const InvokeInst *) { return true; } + static inline bool classof(const Instruction *I) { + return (I->getOpcode() == Instruction::Invoke); + } + static inline bool classof(const Value *V) { + return isa(V) && classof(cast(V)); + } +}; + + +//===----------------------------------------------------------------------===// +// UnwindInst Class +//===----------------------------------------------------------------------===// + +//===--------------------------------------------------------------------------- +/// UnwindInst - Immediately exit the current function, unwinding the stack +/// until an invoke instruction is found. +/// +struct UnwindInst : public TerminatorInst { + UnwindInst(Instruction *InsertBefore = 0) + : TerminatorInst(Instruction::Unwind, InsertBefore) { + } + UnwindInst(BasicBlock *InsertAtEnd) + : TerminatorInst(Instruction::Unwind, InsertAtEnd) { + } + + virtual Instruction *clone() const { return new UnwindInst(); } + + virtual const BasicBlock *getSuccessor(unsigned idx) const { + assert(0 && "UnwindInst has no successors!"); + abort(); + return 0; + } + virtual void setSuccessor(unsigned idx, BasicBlock *NewSucc); + virtual unsigned getNumSuccessors() const { return 0; } + + // Methods for support type inquiry through isa, cast, and dyn_cast: + static inline bool classof(const UnwindInst *) { return true; } + static inline bool classof(const Instruction *I) { + return I->getOpcode() == Instruction::Unwind; + } + static inline bool classof(const Value *V) { + return isa(V) && classof(cast(V)); + } +}; + +} // End llvm namespace #endif From alkis at cs.uiuc.edu Thu Jul 29 07:17:44 2004 From: alkis at cs.uiuc.edu (Alkis Evlogimenos) Date: Thu, 29 Jul 2004 07:17:44 -0500 Subject: [llvm-commits] CVS: llvm/lib/AsmParser/llvmAsmParser.y ParserInternals.h Message-ID: <200407291217.HAA32545@zion.cs.uiuc.edu> Changes in directory llvm/lib/AsmParser: llvmAsmParser.y updated: 1.195 -> 1.196 ParserInternals.h updated: 1.36 -> 1.37 --- Log message: Merge i*.h headers into Instructions.h as part of bug403: http://llvm.cs.uiuc.edu/PR403 . --- Diffs of the changes: (+4 -7) Index: llvm/lib/AsmParser/llvmAsmParser.y diff -u llvm/lib/AsmParser/llvmAsmParser.y:1.195 llvm/lib/AsmParser/llvmAsmParser.y:1.196 --- llvm/lib/AsmParser/llvmAsmParser.y:1.195 Sun Jul 25 20:40:20 2004 +++ llvm/lib/AsmParser/llvmAsmParser.y Thu Jul 29 07:17:34 2004 @@ -13,12 +13,9 @@ %{ #include "ParserInternals.h" -#include "llvm/SymbolTable.h" +#include "llvm/Instructions.h" #include "llvm/Module.h" -#include "llvm/iTerminators.h" -#include "llvm/iMemory.h" -#include "llvm/iOperators.h" -#include "llvm/iPHINode.h" +#include "llvm/SymbolTable.h" #include "llvm/Support/GetElementPtrTypeIterator.h" #include "Support/STLExtras.h" #include Index: llvm/lib/AsmParser/ParserInternals.h diff -u llvm/lib/AsmParser/ParserInternals.h:1.36 llvm/lib/AsmParser/ParserInternals.h:1.37 --- llvm/lib/AsmParser/ParserInternals.h:1.36 Tue Jul 13 03:28:21 2004 +++ llvm/lib/AsmParser/ParserInternals.h Thu Jul 29 07:17:34 2004 @@ -16,9 +16,9 @@ #define PARSER_INTERNALS_H #include "llvm/Constants.h" -#include "llvm/iOther.h" -#include "llvm/Function.h" #include "llvm/DerivedTypes.h" +#include "llvm/Function.h" +#include "llvm/Instructions.h" #include "llvm/Assembly/Parser.h" #include "Support/StringExtras.h" From alkis at cs.uiuc.edu Thu Jul 29 07:17:44 2004 From: alkis at cs.uiuc.edu (Alkis Evlogimenos) Date: Thu, 29 Jul 2004 07:17:44 -0500 Subject: [llvm-commits] CVS: llvm/lib/Bytecode/Writer/SlotCalculator.cpp Message-ID: <200407291217.HAA32534@zion.cs.uiuc.edu> Changes in directory llvm/lib/Bytecode/Writer: SlotCalculator.cpp updated: 1.60 -> 1.61 --- Log message: Merge i*.h headers into Instructions.h as part of bug403: http://llvm.cs.uiuc.edu/PR403 . --- Diffs of the changes: (+1 -1) Index: llvm/lib/Bytecode/Writer/SlotCalculator.cpp diff -u llvm/lib/Bytecode/Writer/SlotCalculator.cpp:1.60 llvm/lib/Bytecode/Writer/SlotCalculator.cpp:1.61 --- llvm/lib/Bytecode/Writer/SlotCalculator.cpp:1.60 Sat Jul 17 19:17:10 2004 +++ llvm/lib/Bytecode/Writer/SlotCalculator.cpp Thu Jul 29 07:17:34 2004 @@ -17,8 +17,8 @@ #include "SlotCalculator.h" #include "llvm/Constants.h" #include "llvm/DerivedTypes.h" -#include "llvm/iOther.h" #include "llvm/Function.h" +#include "llvm/Instructions.h" #include "llvm/Module.h" #include "llvm/SymbolTable.h" #include "llvm/Type.h" From alkis at cs.uiuc.edu Thu Jul 29 07:17:44 2004 From: alkis at cs.uiuc.edu (Alkis Evlogimenos) Date: Thu, 29 Jul 2004 07:17:44 -0500 Subject: [llvm-commits] CVS: llvm/lib/Analysis/BasicAliasAnalysis.cpp Message-ID: <200407291217.HAA32552@zion.cs.uiuc.edu> Changes in directory llvm/lib/Analysis: BasicAliasAnalysis.cpp updated: 1.51 -> 1.52 --- Log message: Merge i*.h headers into Instructions.h as part of bug403: http://llvm.cs.uiuc.edu/PR403 . --- Diffs of the changes: (+1 -2) Index: llvm/lib/Analysis/BasicAliasAnalysis.cpp diff -u llvm/lib/Analysis/BasicAliasAnalysis.cpp:1.51 llvm/lib/Analysis/BasicAliasAnalysis.cpp:1.52 --- llvm/lib/Analysis/BasicAliasAnalysis.cpp:1.51 Thu Jul 29 02:56:39 2004 +++ llvm/lib/Analysis/BasicAliasAnalysis.cpp Thu Jul 29 07:17:34 2004 @@ -18,8 +18,7 @@ #include "llvm/DerivedTypes.h" #include "llvm/Function.h" #include "llvm/GlobalVariable.h" -#include "llvm/iOther.h" -#include "llvm/iMemory.h" +#include "llvm/Instructions.h" #include "llvm/Pass.h" #include "llvm/Target/TargetData.h" #include "llvm/Support/GetElementPtrTypeIterator.h" From alkis at cs.uiuc.edu Thu Jul 29 07:33:36 2004 From: alkis at cs.uiuc.edu (Alkis Evlogimenos) Date: Thu, 29 Jul 2004 07:33:36 -0500 Subject: [llvm-commits] CVS: llvm/lib/VMCore/Instructions.cpp iSwitch.cpp iOperators.cpp iMemory.cpp iCall.cpp iBranch.cpp Message-ID: <200407291233.HAA32689@zion.cs.uiuc.edu> Changes in directory llvm/lib/VMCore: Instructions.cpp added (r1.1) iSwitch.cpp (r1.14) removed iOperators.cpp (r1.30) removed iMemory.cpp (r1.44) removed iCall.cpp (r1.28) removed iBranch.cpp (r1.15) removed --- Log message: Merge i*.cpp definitions into Instructions.cpp as part of bug403: http://llvm.cs.uiuc.edu/PR403 . --- Diffs of the changes: (+802 -0) Index: llvm/lib/VMCore/Instructions.cpp diff -c /dev/null llvm/lib/VMCore/Instructions.cpp:1.1 *** /dev/null Thu Jul 29 07:33:36 2004 --- llvm/lib/VMCore/Instructions.cpp Thu Jul 29 07:33:25 2004 *************** *** 0 **** --- 1,802 ---- + //===-- Instructions.cpp - Implement the LLVM instructions ----------------===// + // + // The LLVM Compiler Infrastructure + // + // This file was developed by the LLVM research group and is distributed under + // the University of Illinois Open Source License. See LICENSE.TXT for details. + // + //===----------------------------------------------------------------------===// + // + // This file implements the LLVM instructions... + // + //===----------------------------------------------------------------------===// + + #include "llvm/BasicBlock.h" + #include "llvm/Constants.h" + #include "llvm/DerivedTypes.h" + #include "llvm/Function.h" + #include "llvm/Instructions.h" + #include "llvm/Support/CallSite.h" + using namespace llvm; + + //===----------------------------------------------------------------------===// + // CallInst Implementation + //===----------------------------------------------------------------------===// + + void CallInst::init(Value *Func, const std::vector &Params) + { + Operands.reserve(1+Params.size()); + Operands.push_back(Use(Func, this)); + + const FunctionType *FTy = + cast(cast(Func->getType())->getElementType()); + + assert((Params.size() == FTy->getNumParams() || + (FTy->isVarArg() && Params.size() > FTy->getNumParams())) && + "Calling a function with bad signature"); + for (unsigned i = 0; i != Params.size(); i++) + Operands.push_back(Use(Params[i], this)); + } + + void CallInst::init(Value *Func, Value *Actual1, Value *Actual2) + { + Operands.reserve(3); + Operands.push_back(Use(Func, this)); + + const FunctionType *MTy = + cast(cast(Func->getType())->getElementType()); + + assert((MTy->getNumParams() == 2 || + (MTy->isVarArg() && MTy->getNumParams() == 0)) && + "Calling a function with bad signature"); + Operands.push_back(Use(Actual1, this)); + Operands.push_back(Use(Actual2, this)); + } + + void CallInst::init(Value *Func, Value *Actual) + { + Operands.reserve(2); + Operands.push_back(Use(Func, this)); + + const FunctionType *MTy = + cast(cast(Func->getType())->getElementType()); + + assert((MTy->getNumParams() == 1 || + (MTy->isVarArg() && MTy->getNumParams() == 0)) && + "Calling a function with bad signature"); + Operands.push_back(Use(Actual, this)); + } + + void CallInst::init(Value *Func) + { + Operands.reserve(1); + Operands.push_back(Use(Func, this)); + + const FunctionType *MTy = + cast(cast(Func->getType())->getElementType()); + + assert(MTy->getNumParams() == 0 && "Calling a function with bad signature"); + } + + CallInst::CallInst(Value *Func, const std::vector &Params, + const std::string &Name, Instruction *InsertBefore) + : Instruction(cast(cast(Func->getType()) + ->getElementType())->getReturnType(), + Instruction::Call, Name, InsertBefore) { + init(Func, Params); + } + + CallInst::CallInst(Value *Func, const std::vector &Params, + const std::string &Name, BasicBlock *InsertAtEnd) + : Instruction(cast(cast(Func->getType()) + ->getElementType())->getReturnType(), + Instruction::Call, Name, InsertAtEnd) { + init(Func, Params); + } + + CallInst::CallInst(Value *Func, Value *Actual1, Value *Actual2, + const std::string &Name, Instruction *InsertBefore) + : Instruction(cast(cast(Func->getType()) + ->getElementType())->getReturnType(), + Instruction::Call, Name, InsertBefore) { + init(Func, Actual1, Actual2); + } + + CallInst::CallInst(Value *Func, Value *Actual1, Value *Actual2, + const std::string &Name, BasicBlock *InsertAtEnd) + : Instruction(cast(cast(Func->getType()) + ->getElementType())->getReturnType(), + Instruction::Call, Name, InsertAtEnd) { + init(Func, Actual1, Actual2); + } + + CallInst::CallInst(Value *Func, Value* Actual, const std::string &Name, + Instruction *InsertBefore) + : Instruction(cast(cast(Func->getType()) + ->getElementType())->getReturnType(), + Instruction::Call, Name, InsertBefore) { + init(Func, Actual); + } + + CallInst::CallInst(Value *Func, Value* Actual, const std::string &Name, + BasicBlock *InsertAtEnd) + : Instruction(cast(cast(Func->getType()) + ->getElementType())->getReturnType(), + Instruction::Call, Name, InsertAtEnd) { + init(Func, Actual); + } + + CallInst::CallInst(Value *Func, const std::string &Name, + Instruction *InsertBefore) + : Instruction(cast(cast(Func->getType()) + ->getElementType())->getReturnType(), + Instruction::Call, Name, InsertBefore) { + init(Func); + } + + CallInst::CallInst(Value *Func, const std::string &Name, + BasicBlock *InsertAtEnd) + : Instruction(cast(cast(Func->getType()) + ->getElementType())->getReturnType(), + Instruction::Call, Name, InsertAtEnd) { + init(Func); + } + + CallInst::CallInst(const CallInst &CI) + : Instruction(CI.getType(), Instruction::Call) { + Operands.reserve(CI.Operands.size()); + for (unsigned i = 0; i < CI.Operands.size(); ++i) + Operands.push_back(Use(CI.Operands[i], this)); + } + + const Function *CallInst::getCalledFunction() const { + if (const Function *F = dyn_cast(Operands[0])) + return F; + return 0; + } + Function *CallInst::getCalledFunction() { + if (Function *F = dyn_cast(Operands[0])) + return F; + return 0; + } + + + //===----------------------------------------------------------------------===// + // InvokeInst Implementation + //===----------------------------------------------------------------------===// + + void InvokeInst::init(Value *Fn, BasicBlock *IfNormal, BasicBlock *IfException, + const std::vector &Params) + { + Operands.reserve(3+Params.size()); + Operands.push_back(Use(Fn, this)); + Operands.push_back(Use((Value*)IfNormal, this)); + Operands.push_back(Use((Value*)IfException, this)); + const FunctionType *MTy = + cast(cast(Fn->getType())->getElementType()); + + assert((Params.size() == MTy->getNumParams()) || + (MTy->isVarArg() && Params.size() > MTy->getNumParams()) && + "Calling a function with bad signature"); + + for (unsigned i = 0; i < Params.size(); i++) + Operands.push_back(Use(Params[i], this)); + } + + InvokeInst::InvokeInst(Value *Fn, BasicBlock *IfNormal, + BasicBlock *IfException, + const std::vector &Params, + const std::string &Name, Instruction *InsertBefore) + : TerminatorInst(cast(cast(Fn->getType()) + ->getElementType())->getReturnType(), + Instruction::Invoke, Name, InsertBefore) { + init(Fn, IfNormal, IfException, Params); + } + + InvokeInst::InvokeInst(Value *Fn, BasicBlock *IfNormal, + BasicBlock *IfException, + const std::vector &Params, + const std::string &Name, BasicBlock *InsertAtEnd) + : TerminatorInst(cast(cast(Fn->getType()) + ->getElementType())->getReturnType(), + Instruction::Invoke, Name, InsertAtEnd) { + init(Fn, IfNormal, IfException, Params); + } + + InvokeInst::InvokeInst(const InvokeInst &CI) + : TerminatorInst(CI.getType(), Instruction::Invoke) { + Operands.reserve(CI.Operands.size()); + for (unsigned i = 0; i < CI.Operands.size(); ++i) + Operands.push_back(Use(CI.Operands[i], this)); + } + + const Function *InvokeInst::getCalledFunction() const { + if (const Function *F = dyn_cast(Operands[0])) + return F; + return 0; + } + Function *InvokeInst::getCalledFunction() { + if (Function *F = dyn_cast(Operands[0])) + return F; + return 0; + } + + // FIXME: Is this supposed to be here? + Function *CallSite::getCalledFunction() const { + Value *Callee = getCalledValue(); + if (Function *F = dyn_cast(Callee)) + return F; + return 0; + } + + //===----------------------------------------------------------------------===// + // ReturnInst Implementation + //===----------------------------------------------------------------------===// + + // Out-of-line ReturnInst method, put here so the C++ compiler can choose to + // emit the vtable for the class in this translation unit. + void ReturnInst::setSuccessor(unsigned idx, BasicBlock *NewSucc) { + assert(0 && "ReturnInst has no successors!"); + } + + //===----------------------------------------------------------------------===// + // UnwindInst Implementation + //===----------------------------------------------------------------------===// + + // Likewise for UnwindInst + void UnwindInst::setSuccessor(unsigned idx, BasicBlock *NewSucc) { + assert(0 && "UnwindInst has no successors!"); + } + + //===----------------------------------------------------------------------===// + // BranchInst Implementation + //===----------------------------------------------------------------------===// + + void BranchInst::init(BasicBlock *IfTrue) + { + assert(IfTrue != 0 && "Branch destination may not be null!"); + Operands.reserve(1); + Operands.push_back(Use(IfTrue, this)); + } + + void BranchInst::init(BasicBlock *IfTrue, BasicBlock *IfFalse, Value *Cond) + { + assert(IfTrue && IfFalse && Cond && + "Branch destinations and condition may not be null!"); + assert(Cond && Cond->getType() == Type::BoolTy && + "May only branch on boolean predicates!"); + Operands.reserve(3); + Operands.push_back(Use(IfTrue, this)); + Operands.push_back(Use(IfFalse, this)); + Operands.push_back(Use(Cond, this)); + } + + BranchInst::BranchInst(const BranchInst &BI) : TerminatorInst(Instruction::Br) { + Operands.reserve(BI.Operands.size()); + Operands.push_back(Use(BI.Operands[0], this)); + if (BI.Operands.size() != 1) { + assert(BI.Operands.size() == 3 && "BR can have 1 or 3 operands!"); + Operands.push_back(Use(BI.Operands[1], this)); + Operands.push_back(Use(BI.Operands[2], this)); + } + } + + //===----------------------------------------------------------------------===// + // AllocationInst Implementation + //===----------------------------------------------------------------------===// + + void AllocationInst::init(const Type *Ty, Value *ArraySize, unsigned iTy) { + assert(Ty != Type::VoidTy && "Cannot allocate void elements!"); + // ArraySize defaults to 1. + if (!ArraySize) ArraySize = ConstantUInt::get(Type::UIntTy, 1); + + Operands.reserve(1); + assert(ArraySize->getType() == Type::UIntTy && + "Malloc/Allocation array size != UIntTy!"); + + Operands.push_back(Use(ArraySize, this)); + } + + AllocationInst::AllocationInst(const Type *Ty, Value *ArraySize, unsigned iTy, + const std::string &Name, + Instruction *InsertBefore) + : Instruction(PointerType::get(Ty), iTy, Name, InsertBefore) { + init(Ty, ArraySize, iTy); + } + + AllocationInst::AllocationInst(const Type *Ty, Value *ArraySize, unsigned iTy, + const std::string &Name, + BasicBlock *InsertAtEnd) + : Instruction(PointerType::get(Ty), iTy, Name, InsertAtEnd) { + init(Ty, ArraySize, iTy); + } + + bool AllocationInst::isArrayAllocation() const { + return getOperand(0) != ConstantUInt::get(Type::UIntTy, 1); + } + + const Type *AllocationInst::getAllocatedType() const { + return getType()->getElementType(); + } + + AllocaInst::AllocaInst(const AllocaInst &AI) + : AllocationInst(AI.getType()->getElementType(), (Value*)AI.getOperand(0), + Instruction::Alloca) { + } + + MallocInst::MallocInst(const MallocInst &MI) + : AllocationInst(MI.getType()->getElementType(), (Value*)MI.getOperand(0), + Instruction::Malloc) { + } + + //===----------------------------------------------------------------------===// + // FreeInst Implementation + //===----------------------------------------------------------------------===// + + void FreeInst::init(Value *Ptr) + { + assert(Ptr && isa(Ptr->getType()) && "Can't free nonpointer!"); + Operands.reserve(1); + Operands.push_back(Use(Ptr, this)); + } + + FreeInst::FreeInst(Value *Ptr, Instruction *InsertBefore) + : Instruction(Type::VoidTy, Free, "", InsertBefore) { + init(Ptr); + } + + FreeInst::FreeInst(Value *Ptr, BasicBlock *InsertAtEnd) + : Instruction(Type::VoidTy, Free, "", InsertAtEnd) { + init(Ptr); + } + + + //===----------------------------------------------------------------------===// + // LoadInst Implementation + //===----------------------------------------------------------------------===// + + void LoadInst::init(Value *Ptr) { + assert(Ptr && isa(Ptr->getType()) && + "Ptr must have pointer type."); + Operands.reserve(1); + Operands.push_back(Use(Ptr, this)); + } + + LoadInst::LoadInst(Value *Ptr, const std::string &Name, Instruction *InsertBef) + : Instruction(cast(Ptr->getType())->getElementType(), + Load, Name, InsertBef), Volatile(false) { + init(Ptr); + } + + LoadInst::LoadInst(Value *Ptr, const std::string &Name, BasicBlock *InsertAE) + : Instruction(cast(Ptr->getType())->getElementType(), + Load, Name, InsertAE), Volatile(false) { + init(Ptr); + } + + LoadInst::LoadInst(Value *Ptr, const std::string &Name, bool isVolatile, + Instruction *InsertBef) + : Instruction(cast(Ptr->getType())->getElementType(), + Load, Name, InsertBef), Volatile(isVolatile) { + init(Ptr); + } + + LoadInst::LoadInst(Value *Ptr, const std::string &Name, bool isVolatile, + BasicBlock *InsertAE) + : Instruction(cast(Ptr->getType())->getElementType(), + Load, Name, InsertAE), Volatile(isVolatile) { + init(Ptr); + } + + + //===----------------------------------------------------------------------===// + // StoreInst Implementation + //===----------------------------------------------------------------------===// + + StoreInst::StoreInst(Value *Val, Value *Ptr, Instruction *InsertBefore) + : Instruction(Type::VoidTy, Store, "", InsertBefore), Volatile(false) { + init(Val, Ptr); + } + + StoreInst::StoreInst(Value *Val, Value *Ptr, BasicBlock *InsertAtEnd) + : Instruction(Type::VoidTy, Store, "", InsertAtEnd), Volatile(false) { + init(Val, Ptr); + } + + StoreInst::StoreInst(Value *Val, Value *Ptr, bool isVolatile, + Instruction *InsertBefore) + : Instruction(Type::VoidTy, Store, "", InsertBefore), Volatile(isVolatile) { + init(Val, Ptr); + } + + StoreInst::StoreInst(Value *Val, Value *Ptr, bool isVolatile, + BasicBlock *InsertAtEnd) + : Instruction(Type::VoidTy, Store, "", InsertAtEnd), Volatile(isVolatile) { + init(Val, Ptr); + } + + void StoreInst::init(Value *Val, Value *Ptr) { + assert(isa(Ptr->getType()) && + Val->getType() == cast(Ptr->getType())->getElementType() + && "Ptr must have pointer type."); + + Operands.reserve(2); + Operands.push_back(Use(Val, this)); + Operands.push_back(Use(Ptr, this)); + } + + //===----------------------------------------------------------------------===// + // GetElementPtrInst Implementation + //===----------------------------------------------------------------------===// + + // checkType - Simple wrapper function to give a better assertion failure + // message on bad indexes for a gep instruction. + // + static inline const Type *checkType(const Type *Ty) { + assert(Ty && "Invalid indices for type!"); + return Ty; + } + + void GetElementPtrInst::init(Value *Ptr, const std::vector &Idx) + { + Operands.reserve(1+Idx.size()); + Operands.push_back(Use(Ptr, this)); + + for (unsigned i = 0, E = Idx.size(); i != E; ++i) + Operands.push_back(Use(Idx[i], this)); + } + + void GetElementPtrInst::init(Value *Ptr, Value *Idx0, Value *Idx1) { + Operands.reserve(3); + Operands.push_back(Use(Ptr, this)); + Operands.push_back(Use(Idx0, this)); + Operands.push_back(Use(Idx1, this)); + } + + GetElementPtrInst::GetElementPtrInst(Value *Ptr, const std::vector &Idx, + const std::string &Name, Instruction *InBe) + : Instruction(PointerType::get(checkType(getIndexedType(Ptr->getType(), + Idx, true))), + GetElementPtr, Name, InBe) { + init(Ptr, Idx); + } + + GetElementPtrInst::GetElementPtrInst(Value *Ptr, const std::vector &Idx, + const std::string &Name, BasicBlock *IAE) + : Instruction(PointerType::get(checkType(getIndexedType(Ptr->getType(), + Idx, true))), + GetElementPtr, Name, IAE) { + init(Ptr, Idx); + } + + GetElementPtrInst::GetElementPtrInst(Value *Ptr, Value *Idx0, Value *Idx1, + const std::string &Name, Instruction *InBe) + : Instruction(PointerType::get(checkType(getIndexedType(Ptr->getType(), + Idx0, Idx1, true))), + GetElementPtr, Name, InBe) { + init(Ptr, Idx0, Idx1); + } + + GetElementPtrInst::GetElementPtrInst(Value *Ptr, Value *Idx0, Value *Idx1, + const std::string &Name, BasicBlock *IAE) + : Instruction(PointerType::get(checkType(getIndexedType(Ptr->getType(), + Idx0, Idx1, true))), + GetElementPtr, Name, IAE) { + init(Ptr, Idx0, Idx1); + } + + // getIndexedType - Returns the type of the element that would be loaded with + // a load instruction with the specified parameters. + // + // A null type is returned if the indices are invalid for the specified + // pointer type. + // + const Type* GetElementPtrInst::getIndexedType(const Type *Ptr, + const std::vector &Idx, + bool AllowCompositeLeaf) { + if (!isa(Ptr)) return 0; // Type isn't a pointer type! + + // Handle the special case of the empty set index set... + if (Idx.empty()) + if (AllowCompositeLeaf || + cast(Ptr)->getElementType()->isFirstClassType()) + return cast(Ptr)->getElementType(); + else + return 0; + + unsigned CurIdx = 0; + while (const CompositeType *CT = dyn_cast(Ptr)) { + if (Idx.size() == CurIdx) { + if (AllowCompositeLeaf || CT->isFirstClassType()) return Ptr; + return 0; // Can't load a whole structure or array!?!? + } + + Value *Index = Idx[CurIdx++]; + if (isa(CT) && CurIdx != 1) + return 0; // Can only index into pointer types at the first index! + if (!CT->indexValid(Index)) return 0; + Ptr = CT->getTypeAtIndex(Index); + + // If the new type forwards to another type, then it is in the middle + // of being refined to another type (and hence, may have dropped all + // references to what it was using before). So, use the new forwarded + // type. + if (const Type * Ty = Ptr->getForwardedType()) { + Ptr = Ty; + } + } + return CurIdx == Idx.size() ? Ptr : 0; + } + + const Type* GetElementPtrInst::getIndexedType(const Type *Ptr, + Value *Idx0, Value *Idx1, + bool AllowCompositeLeaf) { + const PointerType *PTy = dyn_cast(Ptr); + if (!PTy) return 0; // Type isn't a pointer type! + + // Check the pointer index. + if (!PTy->indexValid(Idx0)) return 0; + + const CompositeType *CT = dyn_cast(PTy->getElementType()); + if (!CT || !CT->indexValid(Idx1)) return 0; + + const Type *ElTy = CT->getTypeAtIndex(Idx1); + if (AllowCompositeLeaf || ElTy->isFirstClassType()) + return ElTy; + return 0; + } + + //===----------------------------------------------------------------------===// + // BinaryOperator Class + //===----------------------------------------------------------------------===// + + void BinaryOperator::init(BinaryOps iType, Value *S1, Value *S2) + { + Operands.reserve(2); + Operands.push_back(Use(S1, this)); + Operands.push_back(Use(S2, this)); + assert(S1 && S2 && S1->getType() == S2->getType()); + + #ifndef NDEBUG + switch (iType) { + case Add: case Sub: + case Mul: case Div: + case Rem: + assert(getType() == S1->getType() && + "Arithmetic operation should return same type as operands!"); + assert((getType()->isInteger() || getType()->isFloatingPoint()) && + "Tried to create an arithmetic operation on a non-arithmetic type!"); + break; + case And: case Or: + case Xor: + assert(getType() == S1->getType() && + "Logical operation should return same type as operands!"); + assert(getType()->isIntegral() && + "Tried to create an logical operation on a non-integral type!"); + break; + case SetLT: case SetGT: case SetLE: + case SetGE: case SetEQ: case SetNE: + assert(getType() == Type::BoolTy && "Setcc must return bool!"); + default: + break; + } + #endif + } + + BinaryOperator *BinaryOperator::create(BinaryOps Op, Value *S1, Value *S2, + const std::string &Name, + Instruction *InsertBefore) { + assert(S1->getType() == S2->getType() && + "Cannot create binary operator with two operands of differing type!"); + switch (Op) { + // Binary comparison operators... + case SetLT: case SetGT: case SetLE: + case SetGE: case SetEQ: case SetNE: + return new SetCondInst(Op, S1, S2, Name, InsertBefore); + + default: + return new BinaryOperator(Op, S1, S2, S1->getType(), Name, InsertBefore); + } + } + + BinaryOperator *BinaryOperator::create(BinaryOps Op, Value *S1, Value *S2, + const std::string &Name, + BasicBlock *InsertAtEnd) { + BinaryOperator *Res = create(Op, S1, S2, Name); + InsertAtEnd->getInstList().push_back(Res); + return Res; + } + + BinaryOperator *BinaryOperator::createNeg(Value *Op, const std::string &Name, + Instruction *InsertBefore) { + if (!Op->getType()->isFloatingPoint()) + return new BinaryOperator(Instruction::Sub, + Constant::getNullValue(Op->getType()), Op, + Op->getType(), Name, InsertBefore); + else + return new BinaryOperator(Instruction::Sub, + ConstantFP::get(Op->getType(), -0.0), Op, + Op->getType(), Name, InsertBefore); + } + + BinaryOperator *BinaryOperator::createNeg(Value *Op, const std::string &Name, + BasicBlock *InsertAtEnd) { + if (!Op->getType()->isFloatingPoint()) + return new BinaryOperator(Instruction::Sub, + Constant::getNullValue(Op->getType()), Op, + Op->getType(), Name, InsertAtEnd); + else + return new BinaryOperator(Instruction::Sub, + ConstantFP::get(Op->getType(), -0.0), Op, + Op->getType(), Name, InsertAtEnd); + } + + BinaryOperator *BinaryOperator::createNot(Value *Op, const std::string &Name, + Instruction *InsertBefore) { + return new BinaryOperator(Instruction::Xor, Op, + ConstantIntegral::getAllOnesValue(Op->getType()), + Op->getType(), Name, InsertBefore); + } + + BinaryOperator *BinaryOperator::createNot(Value *Op, const std::string &Name, + BasicBlock *InsertAtEnd) { + return new BinaryOperator(Instruction::Xor, Op, + ConstantIntegral::getAllOnesValue(Op->getType()), + Op->getType(), Name, InsertAtEnd); + } + + + // isConstantAllOnes - Helper function for several functions below + static inline bool isConstantAllOnes(const Value *V) { + return isa(V) &&cast(V)->isAllOnesValue(); + } + + bool BinaryOperator::isNeg(const Value *V) { + if (const BinaryOperator *Bop = dyn_cast(V)) + if (Bop->getOpcode() == Instruction::Sub) + if (!V->getType()->isFloatingPoint()) + return Bop->getOperand(0) == Constant::getNullValue(Bop->getType()); + else + return Bop->getOperand(0) == ConstantFP::get(Bop->getType(), -0.0); + return false; + } + + bool BinaryOperator::isNot(const Value *V) { + if (const BinaryOperator *Bop = dyn_cast(V)) + return (Bop->getOpcode() == Instruction::Xor && + (isConstantAllOnes(Bop->getOperand(1)) || + isConstantAllOnes(Bop->getOperand(0)))); + return false; + } + + Value *BinaryOperator::getNegArgument(BinaryOperator *Bop) { + assert(isNeg(Bop) && "getNegArgument from non-'neg' instruction!"); + return Bop->getOperand(1); + } + + const Value *BinaryOperator::getNegArgument(const BinaryOperator *Bop) { + return getNegArgument((BinaryOperator*)Bop); + } + + Value *BinaryOperator::getNotArgument(BinaryOperator *Bop) { + assert(isNot(Bop) && "getNotArgument on non-'not' instruction!"); + Value *Op0 = Bop->getOperand(0); + Value *Op1 = Bop->getOperand(1); + if (isConstantAllOnes(Op0)) return Op1; + + assert(isConstantAllOnes(Op1)); + return Op0; + } + + const Value *BinaryOperator::getNotArgument(const BinaryOperator *Bop) { + return getNotArgument((BinaryOperator*)Bop); + } + + + // swapOperands - Exchange the two operands to this instruction. This + // instruction is safe to use on any binary instruction and does not + // modify the semantics of the instruction. If the instruction is + // order dependent (SetLT f.e.) the opcode is changed. + // + bool BinaryOperator::swapOperands() { + if (isCommutative()) + ; // If the instruction is commutative, it is safe to swap the operands + else if (SetCondInst *SCI = dyn_cast(this)) + /// FIXME: SetCC instructions shouldn't all have different opcodes. + setOpcode(SCI->getSwappedCondition()); + else + return true; // Can't commute operands + + std::swap(Operands[0], Operands[1]); + return false; + } + + + //===----------------------------------------------------------------------===// + // SetCondInst Class + //===----------------------------------------------------------------------===// + + SetCondInst::SetCondInst(BinaryOps Opcode, Value *S1, Value *S2, + const std::string &Name, Instruction *InsertBefore) + : BinaryOperator(Opcode, S1, S2, Type::BoolTy, Name, InsertBefore) { + + // Make sure it's a valid type... getInverseCondition will assert out if not. + assert(getInverseCondition(Opcode)); + } + + SetCondInst::SetCondInst(BinaryOps Opcode, Value *S1, Value *S2, + const std::string &Name, BasicBlock *InsertAtEnd) + : BinaryOperator(Opcode, S1, S2, Type::BoolTy, Name, InsertAtEnd) { + + // Make sure it's a valid type... getInverseCondition will assert out if not. + assert(getInverseCondition(Opcode)); + } + + // getInverseCondition - Return the inverse of the current condition opcode. + // For example seteq -> setne, setgt -> setle, setlt -> setge, etc... + // + Instruction::BinaryOps SetCondInst::getInverseCondition(BinaryOps Opcode) { + switch (Opcode) { + default: + assert(0 && "Unknown setcc opcode!"); + case SetEQ: return SetNE; + case SetNE: return SetEQ; + case SetGT: return SetLE; + case SetLT: return SetGE; + case SetGE: return SetLT; + case SetLE: return SetGT; + } + } + + // getSwappedCondition - Return the condition opcode that would be the result + // of exchanging the two operands of the setcc instruction without changing + // the result produced. Thus, seteq->seteq, setle->setge, setlt->setgt, etc. + // + Instruction::BinaryOps SetCondInst::getSwappedCondition(BinaryOps Opcode) { + switch (Opcode) { + default: assert(0 && "Unknown setcc instruction!"); + case SetEQ: case SetNE: return Opcode; + case SetGT: return SetLT; + case SetLT: return SetGT; + case SetGE: return SetLE; + case SetLE: return SetGE; + } + } + + //===----------------------------------------------------------------------===// + // SwitchInst Implementation + //===----------------------------------------------------------------------===// + + void SwitchInst::init(Value *Value, BasicBlock *Default) + { + assert(Value && Default); + Operands.push_back(Use(Value, this)); + Operands.push_back(Use(Default, this)); + } + + SwitchInst::SwitchInst(const SwitchInst &SI) + : TerminatorInst(Instruction::Switch) { + Operands.reserve(SI.Operands.size()); + + for (unsigned i = 0, E = SI.Operands.size(); i != E; i+=2) { + Operands.push_back(Use(SI.Operands[i], this)); + Operands.push_back(Use(SI.Operands[i+1], this)); + } + } + + /// addCase - Add an entry to the switch instruction... + /// + void SwitchInst::addCase(Constant *OnVal, BasicBlock *Dest) { + Operands.push_back(Use((Value*)OnVal, this)); + Operands.push_back(Use((Value*)Dest, this)); + } + + /// removeCase - This method removes the specified successor from the switch + /// instruction. Note that this cannot be used to remove the default + /// destination (successor #0). + /// + void SwitchInst::removeCase(unsigned idx) { + assert(idx != 0 && "Cannot remove the default case!"); + assert(idx*2 < Operands.size() && "Successor index out of range!!!"); + Operands.erase(Operands.begin()+idx*2, Operands.begin()+(idx+1)*2); + } From brukman at cs.uiuc.edu Thu Jul 29 11:54:03 2004 From: brukman at cs.uiuc.edu (Misha Brukman) Date: Thu, 29 Jul 2004 11:54:03 -0500 Subject: [llvm-commits] CVS: llvm/lib/VMCore/AsmWriter.cpp BasicBlock.cpp Function.cpp Message-ID: <200407291654.LAA03954@zion.cs.uiuc.edu> Changes in directory llvm/lib/VMCore: AsmWriter.cpp updated: 1.152 -> 1.153 BasicBlock.cpp updated: 1.47 -> 1.48 Function.cpp updated: 1.76 -> 1.77 --- Log message: Fix #includes of i*.h files => Instructions.h as per PR403: http://llvm.cs.uiuc.edu/PR403 --- Diffs of the changes: (+4 -8) Index: llvm/lib/VMCore/AsmWriter.cpp diff -u llvm/lib/VMCore/AsmWriter.cpp:1.152 llvm/lib/VMCore/AsmWriter.cpp:1.153 --- llvm/lib/VMCore/AsmWriter.cpp:1.152 Sun Jul 25 16:44:54 2004 +++ llvm/lib/VMCore/AsmWriter.cpp Thu Jul 29 11:53:53 2004 @@ -21,10 +21,7 @@ #include "llvm/Constants.h" #include "llvm/DerivedTypes.h" #include "llvm/Instruction.h" -#include "llvm/iMemory.h" -#include "llvm/iTerminators.h" -#include "llvm/iPHINode.h" -#include "llvm/iOther.h" +#include "llvm/Instructions.h" #include "llvm/Module.h" #include "llvm/SymbolTable.h" #include "llvm/Assembly/Writer.h" Index: llvm/lib/VMCore/BasicBlock.cpp diff -u llvm/lib/VMCore/BasicBlock.cpp:1.47 llvm/lib/VMCore/BasicBlock.cpp:1.48 --- llvm/lib/VMCore/BasicBlock.cpp:1.47 Tue Jul 6 12:44:17 2004 +++ llvm/lib/VMCore/BasicBlock.cpp Thu Jul 29 11:53:53 2004 @@ -12,11 +12,10 @@ //===----------------------------------------------------------------------===// #include "llvm/BasicBlock.h" -#include "llvm/iTerminators.h" +#include "llvm/Constant.h" +#include "llvm/Instructions.h" #include "llvm/Type.h" #include "llvm/Support/CFG.h" -#include "llvm/Constant.h" -#include "llvm/iPHINode.h" #include "llvm/SymbolTable.h" #include "Support/LeakDetector.h" #include "SymbolTableListTraitsImpl.h" Index: llvm/lib/VMCore/Function.cpp diff -u llvm/lib/VMCore/Function.cpp:1.76 llvm/lib/VMCore/Function.cpp:1.77 --- llvm/lib/VMCore/Function.cpp:1.76 Sat Jul 17 18:50:19 2004 +++ llvm/lib/VMCore/Function.cpp Thu Jul 29 11:53:53 2004 @@ -15,7 +15,7 @@ #include "llvm/Module.h" #include "llvm/Constant.h" #include "llvm/DerivedTypes.h" -#include "llvm/iOther.h" +#include "llvm/Instructions.h" #include "llvm/Intrinsics.h" #include "Support/LeakDetector.h" #include "SymbolTableListTraitsImpl.h" From brukman at cs.uiuc.edu Thu Jul 29 12:03:42 2004 From: brukman at cs.uiuc.edu (Misha Brukman) Date: Thu, 29 Jul 2004 12:03:42 -0500 Subject: [llvm-commits] CVS: llvm/lib/Analysis/DataStructure/DataStructureStats.cpp IPModRef.cpp MemoryDepAnalysis.cpp Message-ID: <200407291703.MAA10348@zion.cs.uiuc.edu> Changes in directory llvm/lib/Analysis/DataStructure: DataStructureStats.cpp updated: 1.12 -> 1.13 IPModRef.cpp updated: 1.24 -> 1.25 MemoryDepAnalysis.cpp updated: 1.16 -> 1.17 --- Log message: Fix #includes of i*.h => Instructions.h as per PR403: http://llvm.cs.uiuc.edu/PR403 . --- Diffs of the changes: (+4 -8) Index: llvm/lib/Analysis/DataStructure/DataStructureStats.cpp diff -u llvm/lib/Analysis/DataStructure/DataStructureStats.cpp:1.12 llvm/lib/Analysis/DataStructure/DataStructureStats.cpp:1.13 --- llvm/lib/Analysis/DataStructure/DataStructureStats.cpp:1.12 Sat Jul 17 19:18:30 2004 +++ llvm/lib/Analysis/DataStructure/DataStructureStats.cpp Thu Jul 29 12:03:32 2004 @@ -14,8 +14,7 @@ #include "llvm/Analysis/DataStructure/DataStructure.h" #include "llvm/Analysis/DataStructure/DSGraph.h" #include "llvm/Function.h" -#include "llvm/iOther.h" -#include "llvm/iMemory.h" +#include "llvm/Instructions.h" #include "llvm/Pass.h" #include "llvm/Support/InstVisitor.h" #include "Support/Statistic.h" Index: llvm/lib/Analysis/DataStructure/IPModRef.cpp diff -u llvm/lib/Analysis/DataStructure/IPModRef.cpp:1.24 llvm/lib/Analysis/DataStructure/IPModRef.cpp:1.25 --- llvm/lib/Analysis/DataStructure/IPModRef.cpp:1.24 Wed Jul 14 21:26:49 2004 +++ llvm/lib/Analysis/DataStructure/IPModRef.cpp Thu Jul 29 12:03:32 2004 @@ -15,9 +15,7 @@ #include "llvm/Analysis/DataStructure/DataStructure.h" #include "llvm/Analysis/DataStructure/DSGraph.h" #include "llvm/Module.h" -#include "llvm/Function.h" -#include "llvm/iMemory.h" -#include "llvm/iOther.h" +#include "llvm/Instructions.h" #include "Support/Statistic.h" #include "Support/STLExtras.h" #include "Support/StringExtras.h" Index: llvm/lib/Analysis/DataStructure/MemoryDepAnalysis.cpp diff -u llvm/lib/Analysis/DataStructure/MemoryDepAnalysis.cpp:1.16 llvm/lib/Analysis/DataStructure/MemoryDepAnalysis.cpp:1.17 --- llvm/lib/Analysis/DataStructure/MemoryDepAnalysis.cpp:1.16 Wed Jul 7 01:32:21 2004 +++ llvm/lib/Analysis/DataStructure/MemoryDepAnalysis.cpp Thu Jul 29 12:03:32 2004 @@ -18,10 +18,9 @@ //===----------------------------------------------------------------------===// #include "MemoryDepAnalysis.h" -#include "llvm/Module.h" -#include "llvm/iMemory.h" -#include "llvm/iOther.h" #include "IPModRef.h" +#include "llvm/Instructions.h" +#include "llvm/Module.h" #include "llvm/Analysis/DataStructure/DataStructure.h" #include "llvm/Analysis/DataStructure/DSGraph.h" #include "llvm/Support/InstVisitor.h" From brukman at cs.uiuc.edu Thu Jul 29 12:05:23 2004 From: brukman at cs.uiuc.edu (Misha Brukman) Date: Thu, 29 Jul 2004 12:05:23 -0500 Subject: [llvm-commits] CVS: llvm/lib/Transforms/Scalar/LowerConstantExprs.cpp LowerSwitch.cpp PRE.cpp PiNodeInsertion.cpp Reassociate.cpp ScalarReplAggregates.cpp TailDuplication.cpp Message-ID: <200407291705.MAA11437@zion.cs.uiuc.edu> Changes in directory llvm/lib/Transforms/Scalar: LowerConstantExprs.cpp updated: 1.2 -> 1.3 LowerSwitch.cpp updated: 1.12 -> 1.13 PRE.cpp updated: 1.9 -> 1.10 PiNodeInsertion.cpp updated: 1.15 -> 1.16 Reassociate.cpp updated: 1.32 -> 1.33 ScalarReplAggregates.cpp updated: 1.23 -> 1.24 TailDuplication.cpp updated: 1.20 -> 1.21 --- Log message: Fix #includes of i*.h => Instructions.h as per PR403: http://llvm.cs.uiuc.edu/PR403 . --- Diffs of the changes: (+7 -15) Index: llvm/lib/Transforms/Scalar/LowerConstantExprs.cpp diff -u llvm/lib/Transforms/Scalar/LowerConstantExprs.cpp:1.2 llvm/lib/Transforms/Scalar/LowerConstantExprs.cpp:1.3 --- llvm/lib/Transforms/Scalar/LowerConstantExprs.cpp:1.2 Sun Jul 4 07:19:56 2004 +++ llvm/lib/Transforms/Scalar/LowerConstantExprs.cpp Thu Jul 29 12:05:13 2004 @@ -17,9 +17,7 @@ #include "llvm/Pass.h" #include "llvm/Function.h" #include "llvm/Constants.h" -#include "llvm/iMemory.h" -#include "llvm/iPHINode.h" -#include "llvm/iOther.h" +#include "llvm/Instructions.h" #include "llvm/Support/InstIterator.h" #include #include Index: llvm/lib/Transforms/Scalar/LowerSwitch.cpp diff -u llvm/lib/Transforms/Scalar/LowerSwitch.cpp:1.12 llvm/lib/Transforms/Scalar/LowerSwitch.cpp:1.13 --- llvm/lib/Transforms/Scalar/LowerSwitch.cpp:1.12 Sat Mar 13 22:14:31 2004 +++ llvm/lib/Transforms/Scalar/LowerSwitch.cpp Thu Jul 29 12:05:13 2004 @@ -16,9 +16,7 @@ #include "llvm/Transforms/Scalar.h" #include "llvm/Constants.h" #include "llvm/Function.h" -#include "llvm/iTerminators.h" -#include "llvm/iOperators.h" -#include "llvm/iPHINode.h" +#include "llvm/Instructions.h" #include "llvm/Pass.h" #include "Support/Debug.h" #include "Support/Statistic.h" Index: llvm/lib/Transforms/Scalar/PRE.cpp diff -u llvm/lib/Transforms/Scalar/PRE.cpp:1.9 llvm/lib/Transforms/Scalar/PRE.cpp:1.10 --- llvm/lib/Transforms/Scalar/PRE.cpp:1.9 Wed Jul 14 20:50:47 2004 +++ llvm/lib/Transforms/Scalar/PRE.cpp Thu Jul 29 12:05:13 2004 @@ -23,8 +23,7 @@ #include "llvm/Pass.h" #include "llvm/Function.h" #include "llvm/Type.h" -#include "llvm/iPHINode.h" -#include "llvm/iMemory.h" +#include "llvm/Instructions.h" #include "llvm/Support/CFG.h" #include "llvm/Analysis/Dominators.h" #include "llvm/Analysis/PostDominators.h" Index: llvm/lib/Transforms/Scalar/PiNodeInsertion.cpp diff -u llvm/lib/Transforms/Scalar/PiNodeInsertion.cpp:1.15 llvm/lib/Transforms/Scalar/PiNodeInsertion.cpp:1.16 --- llvm/lib/Transforms/Scalar/PiNodeInsertion.cpp:1.15 Fri Jan 9 00:02:20 2004 +++ llvm/lib/Transforms/Scalar/PiNodeInsertion.cpp Thu Jul 29 12:05:13 2004 @@ -36,9 +36,7 @@ #include "llvm/Analysis/Dominators.h" #include "llvm/Pass.h" #include "llvm/Function.h" -#include "llvm/iTerminators.h" -#include "llvm/iOperators.h" -#include "llvm/iPHINode.h" +#include "llvm/Instructions.h" #include "llvm/Support/CFG.h" #include "Support/Statistic.h" using namespace llvm; Index: llvm/lib/Transforms/Scalar/Reassociate.cpp diff -u llvm/lib/Transforms/Scalar/Reassociate.cpp:1.32 llvm/lib/Transforms/Scalar/Reassociate.cpp:1.33 --- llvm/lib/Transforms/Scalar/Reassociate.cpp:1.32 Wed Jul 14 20:50:47 2004 +++ llvm/lib/Transforms/Scalar/Reassociate.cpp Thu Jul 29 12:05:13 2004 @@ -25,7 +25,7 @@ #include "llvm/Transforms/Scalar.h" #include "llvm/Function.h" -#include "llvm/iOperators.h" +#include "llvm/Instructions.h" #include "llvm/Type.h" #include "llvm/Pass.h" #include "llvm/Constant.h" Index: llvm/lib/Transforms/Scalar/ScalarReplAggregates.cpp diff -u llvm/lib/Transforms/Scalar/ScalarReplAggregates.cpp:1.23 llvm/lib/Transforms/Scalar/ScalarReplAggregates.cpp:1.24 --- llvm/lib/Transforms/Scalar/ScalarReplAggregates.cpp:1.23 Wed Jul 14 20:50:47 2004 +++ llvm/lib/Transforms/Scalar/ScalarReplAggregates.cpp Thu Jul 29 12:05:13 2004 @@ -24,7 +24,7 @@ #include "llvm/DerivedTypes.h" #include "llvm/Function.h" #include "llvm/Pass.h" -#include "llvm/iMemory.h" +#include "llvm/Instructions.h" #include "llvm/Analysis/Dominators.h" #include "llvm/Support/GetElementPtrTypeIterator.h" #include "llvm/Target/TargetData.h" Index: llvm/lib/Transforms/Scalar/TailDuplication.cpp diff -u llvm/lib/Transforms/Scalar/TailDuplication.cpp:1.20 llvm/lib/Transforms/Scalar/TailDuplication.cpp:1.21 --- llvm/lib/Transforms/Scalar/TailDuplication.cpp:1.20 Tue May 25 03:51:36 2004 +++ llvm/lib/Transforms/Scalar/TailDuplication.cpp Thu Jul 29 12:05:13 2004 @@ -21,8 +21,7 @@ #include "llvm/Transforms/Scalar.h" #include "llvm/Constant.h" #include "llvm/Function.h" -#include "llvm/iPHINode.h" -#include "llvm/iTerminators.h" +#include "llvm/Instructions.h" #include "llvm/Pass.h" #include "llvm/Type.h" #include "llvm/Support/CFG.h" From lattner at cs.uiuc.edu Thu Jul 29 12:06:55 2004 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Thu, 29 Jul 2004 12:06:55 -0500 Subject: [llvm-commits] CVS: llvm/lib/CodeGen/InstrSched/SchedGraph.cpp Message-ID: <200407291706.MAA05304@apoc.cs.uiuc.edu> Changes in directory llvm/lib/CodeGen/InstrSched: SchedGraph.cpp updated: 1.63 -> 1.64 --- Log message: Fix #includes of i*.h => Instructions.h as per PR403: http://llvm.cs.uiuc.edu/PR403 : http://llvm.cs.uiuc.edu/PR403: http://llvm.cs.uiuc.edu/PR403 . --- Diffs of the changes: (+1 -1) Index: llvm/lib/CodeGen/InstrSched/SchedGraph.cpp diff -u llvm/lib/CodeGen/InstrSched/SchedGraph.cpp:1.63 llvm/lib/CodeGen/InstrSched/SchedGraph.cpp:1.64 --- llvm/lib/CodeGen/InstrSched/SchedGraph.cpp:1.63 Wed Jul 14 21:40:04 2004 +++ llvm/lib/CodeGen/InstrSched/SchedGraph.cpp Thu Jul 29 12:06:44 2004 @@ -15,7 +15,7 @@ #include "SchedGraph.h" #include "llvm/Function.h" -#include "llvm/iOther.h" +#include "llvm/Instructions.h" #include "llvm/CodeGen/MachineCodeForInstruction.h" #include "llvm/CodeGen/MachineFunction.h" #include "llvm/Target/TargetInstrInfo.h" From lattner at cs.uiuc.edu Thu Jul 29 12:11:45 2004 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Thu, 29 Jul 2004 12:11:45 -0500 Subject: [llvm-commits] CVS: llvm/lib/Target/SparcV9/SparcV9InstrInfo.cpp SparcV9PreSelection.cpp SparcV9RegInfo.cpp Message-ID: <200407291711.MAA11624@apoc.cs.uiuc.edu> Changes in directory llvm/lib/Target/SparcV9: SparcV9InstrInfo.cpp updated: 1.70 -> 1.71 SparcV9PreSelection.cpp updated: 1.38 -> 1.39 SparcV9RegInfo.cpp updated: 1.131 -> 1.132 --- Log message: Fix #includes of i*.h => Instructions.h as per PR403: http://llvm.cs.uiuc.edu/PR403 : http://llvm.cs.uiuc.edu/PR403: http://llvm.cs.uiuc.edu/PR403 . --- Diffs of the changes: (+3 -6) Index: llvm/lib/Target/SparcV9/SparcV9InstrInfo.cpp diff -u llvm/lib/Target/SparcV9/SparcV9InstrInfo.cpp:1.70 llvm/lib/Target/SparcV9/SparcV9InstrInfo.cpp:1.71 --- llvm/lib/Target/SparcV9/SparcV9InstrInfo.cpp:1.70 Tue Jul 27 12:43:23 2004 +++ llvm/lib/Target/SparcV9/SparcV9InstrInfo.cpp Thu Jul 29 12:11:35 2004 @@ -16,7 +16,7 @@ #include "llvm/Constants.h" #include "llvm/DerivedTypes.h" #include "llvm/Function.h" -#include "llvm/iTerminators.h" +#include "llvm/Instructions.h" #include "llvm/CodeGen/InstrSelection.h" #include "llvm/CodeGen/MachineConstantPool.h" #include "llvm/CodeGen/MachineFunction.h" Index: llvm/lib/Target/SparcV9/SparcV9PreSelection.cpp diff -u llvm/lib/Target/SparcV9/SparcV9PreSelection.cpp:1.38 llvm/lib/Target/SparcV9/SparcV9PreSelection.cpp:1.39 --- llvm/lib/Target/SparcV9/SparcV9PreSelection.cpp:1.38 Tue Jul 27 16:11:20 2004 +++ llvm/lib/Target/SparcV9/SparcV9PreSelection.cpp Thu Jul 29 12:11:35 2004 @@ -19,9 +19,7 @@ #include "SparcV9InstrSelectionSupport.h" #include "llvm/Constants.h" #include "llvm/DerivedTypes.h" -#include "llvm/iMemory.h" -#include "llvm/iPHINode.h" -#include "llvm/iOther.h" +#include "llvm/Instructions.h" #include "llvm/Module.h" #include "llvm/Pass.h" #include "llvm/Support/InstVisitor.h" Index: llvm/lib/Target/SparcV9/SparcV9RegInfo.cpp diff -u llvm/lib/Target/SparcV9/SparcV9RegInfo.cpp:1.131 llvm/lib/Target/SparcV9/SparcV9RegInfo.cpp:1.132 --- llvm/lib/Target/SparcV9/SparcV9RegInfo.cpp:1.131 Sun Jul 4 07:19:56 2004 +++ llvm/lib/Target/SparcV9/SparcV9RegInfo.cpp Thu Jul 29 12:11:35 2004 @@ -22,8 +22,7 @@ #include "RegAlloc/LiveRange.h" #include "llvm/DerivedTypes.h" #include "llvm/Function.h" -#include "llvm/iTerminators.h" -#include "llvm/iOther.h" +#include "llvm/Instructions.h" #include "SparcV9Internals.h" #include "SparcV9RegClassInfo.h" #include "SparcV9RegInfo.h" From lattner at cs.uiuc.edu Thu Jul 29 12:11:47 2004 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Thu, 29 Jul 2004 12:11:47 -0500 Subject: [llvm-commits] CVS: llvm/lib/Target/SparcV9/InstrSelection/InstrForest.cpp InstrSelection.cpp Message-ID: <200407291711.MAA11849@apoc.cs.uiuc.edu> Changes in directory llvm/lib/Target/SparcV9/InstrSelection: InstrForest.cpp updated: 1.56 -> 1.57 InstrSelection.cpp updated: 1.83 -> 1.84 --- Log message: Fix #includes of i*.h => Instructions.h as per PR403: http://llvm.cs.uiuc.edu/PR403 : http://llvm.cs.uiuc.edu/PR403: http://llvm.cs.uiuc.edu/PR403 . --- Diffs of the changes: (+2 -4) Index: llvm/lib/Target/SparcV9/InstrSelection/InstrForest.cpp diff -u llvm/lib/Target/SparcV9/InstrSelection/InstrForest.cpp:1.56 llvm/lib/Target/SparcV9/InstrSelection/InstrForest.cpp:1.57 --- llvm/lib/Target/SparcV9/InstrSelection/InstrForest.cpp:1.56 Sat Jul 17 19:38:32 2004 +++ llvm/lib/Target/SparcV9/InstrSelection/InstrForest.cpp Thu Jul 29 12:11:37 2004 @@ -21,8 +21,7 @@ #include "llvm/Constant.h" #include "llvm/Function.h" -#include "llvm/iTerminators.h" -#include "llvm/iMemory.h" +#include "llvm/Instructions.h" #include "llvm/Type.h" #include "llvm/CodeGen/InstrForest.h" #include "llvm/CodeGen/MachineInstr.h" Index: llvm/lib/Target/SparcV9/InstrSelection/InstrSelection.cpp diff -u llvm/lib/Target/SparcV9/InstrSelection/InstrSelection.cpp:1.83 llvm/lib/Target/SparcV9/InstrSelection/InstrSelection.cpp:1.84 --- llvm/lib/Target/SparcV9/InstrSelection/InstrSelection.cpp:1.83 Thu Jul 15 19:06:26 2004 +++ llvm/lib/Target/SparcV9/InstrSelection/InstrSelection.cpp Thu Jul 29 12:11:37 2004 @@ -16,8 +16,7 @@ #include "llvm/CodeGen/InstrSelection.h" #include "llvm/Function.h" -#include "llvm/iPHINode.h" -#include "llvm/iOther.h" +#include "llvm/Instructions.h" #include "llvm/Pass.h" #include "llvm/CodeGen/InstrForest.h" #include "llvm/CodeGen/IntrinsicLowering.h" From lattner at cs.uiuc.edu Thu Jul 29 12:11:47 2004 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Thu, 29 Jul 2004 12:11:47 -0500 Subject: [llvm-commits] CVS: llvm/lib/Target/SparcV9/RegAlloc/PhyRegAlloc.cpp Message-ID: <200407291711.MAA11856@apoc.cs.uiuc.edu> Changes in directory llvm/lib/Target/SparcV9/RegAlloc: PhyRegAlloc.cpp updated: 1.156 -> 1.157 --- Log message: Fix #includes of i*.h => Instructions.h as per PR403: http://llvm.cs.uiuc.edu/PR403 : http://llvm.cs.uiuc.edu/PR403: http://llvm.cs.uiuc.edu/PR403 . --- Diffs of the changes: (+1 -2) Index: llvm/lib/Target/SparcV9/RegAlloc/PhyRegAlloc.cpp diff -u llvm/lib/Target/SparcV9/RegAlloc/PhyRegAlloc.cpp:1.156 llvm/lib/Target/SparcV9/RegAlloc/PhyRegAlloc.cpp:1.157 --- llvm/lib/Target/SparcV9/RegAlloc/PhyRegAlloc.cpp:1.156 Thu Jul 29 01:43:09 2004 +++ llvm/lib/Target/SparcV9/RegAlloc/PhyRegAlloc.cpp Thu Jul 29 12:11:37 2004 @@ -29,8 +29,7 @@ #include "../SparcV9InstrInfo.h" #include "llvm/Constants.h" #include "llvm/DerivedTypes.h" -#include "llvm/iPHINode.h" -#include "llvm/iOther.h" +#include "llvm/Instructions.h" #include "llvm/Module.h" #include "llvm/Type.h" #include "llvm/Analysis/LoopInfo.h" From brukman at cs.uiuc.edu Thu Jul 29 12:14:27 2004 From: brukman at cs.uiuc.edu (Misha Brukman) Date: Thu, 29 Jul 2004 12:14:27 -0500 Subject: [llvm-commits] CVS: llvm/lib/Analysis/IPA/CallGraph.cpp Message-ID: <200407291714.MAA15022@zion.cs.uiuc.edu> Changes in directory llvm/lib/Analysis/IPA: CallGraph.cpp updated: 1.38 -> 1.39 --- Log message: Fix #includes of i*.h => Instructions.h as per PR403: http://llvm.cs.uiuc.edu/PR403 . --- Diffs of the changes: (+1 -2) Index: llvm/lib/Analysis/IPA/CallGraph.cpp diff -u llvm/lib/Analysis/IPA/CallGraph.cpp:1.38 llvm/lib/Analysis/IPA/CallGraph.cpp:1.39 --- llvm/lib/Analysis/IPA/CallGraph.cpp:1.38 Sat Jul 17 19:18:30 2004 +++ llvm/lib/Analysis/IPA/CallGraph.cpp Thu Jul 29 12:14:17 2004 @@ -14,8 +14,7 @@ #include "llvm/Analysis/CallGraph.h" #include "llvm/Constants.h" // Remove when ConstantPointerRefs are gone #include "llvm/Module.h" -#include "llvm/iOther.h" -#include "llvm/iTerminators.h" +#include "llvm/Instructions.h" #include "llvm/Support/CallSite.h" #include "Support/STLExtras.h" using namespace llvm; From brukman at cs.uiuc.edu Thu Jul 29 12:14:46 2004 From: brukman at cs.uiuc.edu (Misha Brukman) Date: Thu, 29 Jul 2004 12:14:46 -0500 Subject: [llvm-commits] CVS: llvm/lib/Analysis/DataStructure/DataStructure.cpp Message-ID: <200407291714.MAA15037@zion.cs.uiuc.edu> Changes in directory llvm/lib/Analysis/DataStructure: DataStructure.cpp updated: 1.178 -> 1.179 --- Log message: Fix #includes of i*.h => Instructions.h as per PR403: http://llvm.cs.uiuc.edu/PR403 . --- Diffs of the changes: (+1 -1) Index: llvm/lib/Analysis/DataStructure/DataStructure.cpp diff -u llvm/lib/Analysis/DataStructure/DataStructure.cpp:1.178 llvm/lib/Analysis/DataStructure/DataStructure.cpp:1.179 --- llvm/lib/Analysis/DataStructure/DataStructure.cpp:1.178 Thu Jul 8 02:25:51 2004 +++ llvm/lib/Analysis/DataStructure/DataStructure.cpp Thu Jul 29 12:14:36 2004 @@ -14,7 +14,7 @@ #include "llvm/Analysis/DataStructure/DSGraphTraits.h" #include "llvm/Function.h" #include "llvm/GlobalVariable.h" -#include "llvm/iOther.h" +#include "llvm/Instructions.h" #include "llvm/DerivedTypes.h" #include "llvm/Target/TargetData.h" #include "llvm/Assembly/Writer.h" From brukman at cs.uiuc.edu Thu Jul 29 12:15:04 2004 From: brukman at cs.uiuc.edu (Misha Brukman) Date: Thu, 29 Jul 2004 12:15:04 -0500 Subject: [llvm-commits] CVS: llvm/lib/Analysis/AliasAnalysis.cpp AliasAnalysisEvaluator.cpp AliasSetTracker.cpp CFGPrinter.cpp LoadValueNumbering.cpp PostDominators.cpp Message-ID: <200407291715.MAA15063@zion.cs.uiuc.edu> Changes in directory llvm/lib/Analysis: AliasAnalysis.cpp updated: 1.19 -> 1.20 AliasAnalysisEvaluator.cpp updated: 1.17 -> 1.18 AliasSetTracker.cpp updated: 1.25 -> 1.26 CFGPrinter.cpp updated: 1.8 -> 1.9 LoadValueNumbering.cpp updated: 1.20 -> 1.21 PostDominators.cpp updated: 1.46 -> 1.47 --- Log message: Fix #includes of i*.h => Instructions.h as per PR403: http://llvm.cs.uiuc.edu/PR403 . --- Diffs of the changes: (+6 -10) Index: llvm/lib/Analysis/AliasAnalysis.cpp diff -u llvm/lib/Analysis/AliasAnalysis.cpp:1.19 llvm/lib/Analysis/AliasAnalysis.cpp:1.20 --- llvm/lib/Analysis/AliasAnalysis.cpp:1.19 Sun Jul 4 07:19:55 2004 +++ llvm/lib/Analysis/AliasAnalysis.cpp Thu Jul 29 12:14:54 2004 @@ -26,7 +26,7 @@ #include "llvm/Analysis/AliasAnalysis.h" #include "llvm/BasicBlock.h" -#include "llvm/iMemory.h" +#include "llvm/Instructions.h" #include "llvm/Target/TargetData.h" #include using namespace llvm; Index: llvm/lib/Analysis/AliasAnalysisEvaluator.cpp diff -u llvm/lib/Analysis/AliasAnalysisEvaluator.cpp:1.17 llvm/lib/Analysis/AliasAnalysisEvaluator.cpp:1.18 --- llvm/lib/Analysis/AliasAnalysisEvaluator.cpp:1.17 Sat Jul 17 02:40:34 2004 +++ llvm/lib/Analysis/AliasAnalysisEvaluator.cpp Thu Jul 29 12:14:54 2004 @@ -18,8 +18,7 @@ //===----------------------------------------------------------------------===// #include "llvm/Function.h" -#include "llvm/iOther.h" -#include "llvm/iTerminators.h" +#include "llvm/Instructions.h" #include "llvm/Pass.h" #include "llvm/DerivedTypes.h" #include "llvm/Analysis/AliasAnalysis.h" Index: llvm/lib/Analysis/AliasSetTracker.cpp diff -u llvm/lib/Analysis/AliasSetTracker.cpp:1.25 llvm/lib/Analysis/AliasSetTracker.cpp:1.26 --- llvm/lib/Analysis/AliasSetTracker.cpp:1.25 Tue Jul 27 02:22:21 2004 +++ llvm/lib/Analysis/AliasSetTracker.cpp Thu Jul 29 12:14:54 2004 @@ -13,9 +13,7 @@ #include "llvm/Analysis/AliasSetTracker.h" #include "llvm/Analysis/AliasAnalysis.h" -#include "llvm/iMemory.h" -#include "llvm/iOther.h" -#include "llvm/iTerminators.h" +#include "llvm/Instructions.h" #include "llvm/Pass.h" #include "llvm/Target/TargetData.h" #include "llvm/Assembly/Writer.h" Index: llvm/lib/Analysis/CFGPrinter.cpp diff -u llvm/lib/Analysis/CFGPrinter.cpp:1.8 llvm/lib/Analysis/CFGPrinter.cpp:1.9 --- llvm/lib/Analysis/CFGPrinter.cpp:1.8 Wed May 5 01:10:06 2004 +++ llvm/lib/Analysis/CFGPrinter.cpp Thu Jul 29 12:14:54 2004 @@ -18,7 +18,7 @@ //===----------------------------------------------------------------------===// #include "llvm/Function.h" -#include "llvm/iTerminators.h" +#include "llvm/Instructions.h" #include "llvm/Pass.h" #include "llvm/Analysis/CFGPrinter.h" #include "llvm/Assembly/Writer.h" Index: llvm/lib/Analysis/LoadValueNumbering.cpp diff -u llvm/lib/Analysis/LoadValueNumbering.cpp:1.20 llvm/lib/Analysis/LoadValueNumbering.cpp:1.21 --- llvm/lib/Analysis/LoadValueNumbering.cpp:1.20 Tue Jul 27 12:43:21 2004 +++ llvm/lib/Analysis/LoadValueNumbering.cpp Thu Jul 29 12:14:54 2004 @@ -24,8 +24,7 @@ #include "llvm/Analysis/LoadValueNumbering.h" #include "llvm/Constant.h" #include "llvm/Function.h" -#include "llvm/iMemory.h" -#include "llvm/iOther.h" +#include "llvm/Instructions.h" #include "llvm/Pass.h" #include "llvm/Type.h" #include "llvm/Analysis/ValueNumbering.h" Index: llvm/lib/Analysis/PostDominators.cpp diff -u llvm/lib/Analysis/PostDominators.cpp:1.46 llvm/lib/Analysis/PostDominators.cpp:1.47 --- llvm/lib/Analysis/PostDominators.cpp:1.46 Sat Dec 6 18:35:42 2003 +++ llvm/lib/Analysis/PostDominators.cpp Thu Jul 29 12:14:54 2004 @@ -12,7 +12,7 @@ //===----------------------------------------------------------------------===// #include "llvm/Analysis/PostDominators.h" -#include "llvm/iTerminators.h" +#include "llvm/Instructions.h" #include "llvm/Support/CFG.h" #include "Support/DepthFirstIterator.h" #include "Support/SetOperations.h" From lattner at cs.uiuc.edu Thu Jul 29 12:15:48 2004 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Thu, 29 Jul 2004 12:15:48 -0500 Subject: [llvm-commits] CVS: llvm/lib/Debugger/ProgramInfo.cpp UnixLocalInferiorProcess.cpp Message-ID: <200407291715.MAA16217@apoc.cs.uiuc.edu> Changes in directory llvm/lib/Debugger: ProgramInfo.cpp updated: 1.4 -> 1.5 UnixLocalInferiorProcess.cpp updated: 1.4 -> 1.5 --- Log message: Header moved --- Diffs of the changes: (+2 -2) Index: llvm/lib/Debugger/ProgramInfo.cpp diff -u llvm/lib/Debugger/ProgramInfo.cpp:1.4 llvm/lib/Debugger/ProgramInfo.cpp:1.5 --- llvm/lib/Debugger/ProgramInfo.cpp:1.4 Sat Jul 17 19:42:12 2004 +++ llvm/lib/Debugger/ProgramInfo.cpp Thu Jul 29 12:15:38 2004 @@ -16,7 +16,7 @@ #include "llvm/Constants.h" #include "llvm/DerivedTypes.h" #include "llvm/Intrinsics.h" -#include "llvm/iOther.h" +#include "llvm/Instructions.h" #include "llvm/Module.h" #include "llvm/Debugger/SourceFile.h" #include "llvm/Debugger/SourceLanguage.h" Index: llvm/lib/Debugger/UnixLocalInferiorProcess.cpp diff -u llvm/lib/Debugger/UnixLocalInferiorProcess.cpp:1.4 llvm/lib/Debugger/UnixLocalInferiorProcess.cpp:1.5 --- llvm/lib/Debugger/UnixLocalInferiorProcess.cpp:1.4 Sun Jun 20 02:48:54 2004 +++ llvm/lib/Debugger/UnixLocalInferiorProcess.cpp Thu Jul 29 12:15:38 2004 @@ -25,10 +25,10 @@ #include "llvm/Debugger/InferiorProcess.h" #include "llvm/Constant.h" +#include "llvm/Instructions.h" #include "llvm/Module.h" #include "llvm/ModuleProvider.h" #include "llvm/Type.h" -#include "llvm/iOther.h" #include "llvm/CodeGen/IntrinsicLowering.h" #include "llvm/ExecutionEngine/GenericValue.h" #include "llvm/ExecutionEngine/ExecutionEngine.h" From brukman at cs.uiuc.edu Thu Jul 29 12:16:51 2004 From: brukman at cs.uiuc.edu (Misha Brukman) Date: Thu, 29 Jul 2004 12:16:51 -0500 Subject: [llvm-commits] CVS: llvm/tools/bugpoint/CrashDebugger.cpp TestPasses.cpp Message-ID: <200407291716.MAA15104@zion.cs.uiuc.edu> Changes in directory llvm/tools/bugpoint: CrashDebugger.cpp updated: 1.36 -> 1.37 TestPasses.cpp updated: 1.7 -> 1.8 --- Log message: Fix #includes of i*.h => Instructions.h as per PR403: http://llvm.cs.uiuc.edu/PR403 . --- Diffs of the changes: (+2 -2) Index: llvm/tools/bugpoint/CrashDebugger.cpp diff -u llvm/tools/bugpoint/CrashDebugger.cpp:1.36 llvm/tools/bugpoint/CrashDebugger.cpp:1.37 --- llvm/tools/bugpoint/CrashDebugger.cpp:1.36 Thu Jul 22 20:30:49 2004 +++ llvm/tools/bugpoint/CrashDebugger.cpp Thu Jul 29 12:16:41 2004 @@ -14,7 +14,7 @@ #include "BugDriver.h" #include "ListReducer.h" #include "llvm/Constant.h" -#include "llvm/iTerminators.h" +#include "llvm/Instructions.h" #include "llvm/Module.h" #include "llvm/Pass.h" #include "llvm/PassManager.h" Index: llvm/tools/bugpoint/TestPasses.cpp diff -u llvm/tools/bugpoint/TestPasses.cpp:1.7 llvm/tools/bugpoint/TestPasses.cpp:1.8 --- llvm/tools/bugpoint/TestPasses.cpp:1.7 Wed Mar 17 11:29:08 2004 +++ llvm/tools/bugpoint/TestPasses.cpp Thu Jul 29 12:16:41 2004 @@ -14,7 +14,7 @@ #include "llvm/BasicBlock.h" #include "llvm/Constant.h" -#include "llvm/iOther.h" +#include "llvm/Instructions.h" #include "llvm/Pass.h" #include "llvm/Support/InstVisitor.h" From brukman at cs.uiuc.edu Thu Jul 29 12:17:56 2004 From: brukman at cs.uiuc.edu (Misha Brukman) Date: Thu, 29 Jul 2004 12:17:56 -0500 Subject: [llvm-commits] CVS: llvm/projects/Stacker/lib/compiler/StackerCompiler.cpp StackerParser.y Message-ID: <200407291717.MAA15128@zion.cs.uiuc.edu> Changes in directory llvm/projects/Stacker/lib/compiler: StackerCompiler.cpp updated: 1.6 -> 1.7 StackerParser.y updated: 1.5 -> 1.6 --- Log message: Fix #includes of i*.h => Instructions.h as per PR403: http://llvm.cs.uiuc.edu/PR403 . --- Diffs of the changes: (+2 -8) Index: llvm/projects/Stacker/lib/compiler/StackerCompiler.cpp diff -u llvm/projects/Stacker/lib/compiler/StackerCompiler.cpp:1.6 llvm/projects/Stacker/lib/compiler/StackerCompiler.cpp:1.7 --- llvm/projects/Stacker/lib/compiler/StackerCompiler.cpp:1.6 Sun May 9 18:20:19 2004 +++ llvm/projects/Stacker/lib/compiler/StackerCompiler.cpp Thu Jul 29 12:17:46 2004 @@ -17,10 +17,7 @@ //===----------------------------------------------------------------------===// #include -#include -#include -#include -#include +#include #include #include "StackerCompiler.h" #include "StackerParser.h" Index: llvm/projects/Stacker/lib/compiler/StackerParser.y diff -u llvm/projects/Stacker/lib/compiler/StackerParser.y:1.5 llvm/projects/Stacker/lib/compiler/StackerParser.y:1.6 --- llvm/projects/Stacker/lib/compiler/StackerParser.y:1.5 Sun May 9 18:20:19 2004 +++ llvm/projects/Stacker/lib/compiler/StackerParser.y Thu Jul 29 12:17:46 2004 @@ -15,10 +15,7 @@ #include "StackerCompiler.h" #include "llvm/SymbolTable.h" #include "llvm/Module.h" -#include "llvm/iTerminators.h" -#include "llvm/iMemory.h" -#include "llvm/iOperators.h" -#include "llvm/iPHINode.h" +#include "llvm/Instructions.h" #include "Support/STLExtras.h" #include "Support/DepthFirstIterator.h" #include From brukman at cs.uiuc.edu Thu Jul 29 12:20:32 2004 From: brukman at cs.uiuc.edu (Misha Brukman) Date: Thu, 29 Jul 2004 12:20:32 -0500 Subject: [llvm-commits] CVS: llvm/lib/VMCore/Constants.cpp InstrTypes.cpp Linker.cpp Message-ID: <200407291720.MAA15188@zion.cs.uiuc.edu> Changes in directory llvm/lib/VMCore: Constants.cpp updated: 1.96 -> 1.97 InstrTypes.cpp updated: 1.25 -> 1.26 Linker.cpp updated: 1.74 -> 1.75 --- Log message: Fix #includes of i*.h => Instructions.h as per PR403: http://llvm.cs.uiuc.edu/PR403 . --- Diffs of the changes: (+3 -4) Index: llvm/lib/VMCore/Constants.cpp diff -u llvm/lib/VMCore/Constants.cpp:1.96 llvm/lib/VMCore/Constants.cpp:1.97 --- llvm/lib/VMCore/Constants.cpp:1.96 Sun Jul 18 19:59:10 2004 +++ llvm/lib/VMCore/Constants.cpp Thu Jul 29 12:20:21 2004 @@ -15,7 +15,7 @@ #include "ConstantFolding.h" #include "llvm/DerivedTypes.h" #include "llvm/GlobalValue.h" -#include "llvm/iMemory.h" +#include "llvm/Instructions.h" #include "llvm/SymbolTable.h" #include "llvm/Module.h" #include "Support/StringExtras.h" Index: llvm/lib/VMCore/InstrTypes.cpp diff -u llvm/lib/VMCore/InstrTypes.cpp:1.25 llvm/lib/VMCore/InstrTypes.cpp:1.26 --- llvm/lib/VMCore/InstrTypes.cpp:1.25 Wed May 26 16:41:09 2004 +++ llvm/lib/VMCore/InstrTypes.cpp Thu Jul 29 12:20:21 2004 @@ -11,8 +11,7 @@ // //===----------------------------------------------------------------------===// -#include "llvm/iOther.h" -#include "llvm/iPHINode.h" +#include "llvm/Instructions.h" #include "llvm/Function.h" #include "llvm/SymbolTable.h" #include "llvm/Constant.h" Index: llvm/lib/VMCore/Linker.cpp diff -u llvm/lib/VMCore/Linker.cpp:1.74 llvm/lib/VMCore/Linker.cpp:1.75 --- llvm/lib/VMCore/Linker.cpp:1.74 Sat Jul 17 18:50:57 2004 +++ llvm/lib/VMCore/Linker.cpp Thu Jul 29 12:20:21 2004 @@ -21,7 +21,7 @@ #include "llvm/DerivedTypes.h" #include "llvm/Module.h" #include "llvm/SymbolTable.h" -#include "llvm/iOther.h" +#include "llvm/Instructions.h" #include "llvm/Assembly/Writer.h" #include From brukman at cs.uiuc.edu Thu Jul 29 12:21:04 2004 From: brukman at cs.uiuc.edu (Misha Brukman) Date: Thu, 29 Jul 2004 12:21:04 -0500 Subject: [llvm-commits] CVS: llvm/lib/CodeGen/IntrinsicLowering.cpp MachineFunction.cpp MachineInstrAnnot.cpp Message-ID: <200407291721.MAA15213@zion.cs.uiuc.edu> Changes in directory llvm/lib/CodeGen: IntrinsicLowering.cpp updated: 1.20 -> 1.21 MachineFunction.cpp updated: 1.64 -> 1.65 MachineInstrAnnot.cpp updated: 1.12 -> 1.13 --- Log message: Fix #includes of i*.h => Instructions.h as per PR403: http://llvm.cs.uiuc.edu/PR403 . --- Diffs of the changes: (+3 -3) Index: llvm/lib/CodeGen/IntrinsicLowering.cpp diff -u llvm/lib/CodeGen/IntrinsicLowering.cpp:1.20 llvm/lib/CodeGen/IntrinsicLowering.cpp:1.21 --- llvm/lib/CodeGen/IntrinsicLowering.cpp:1.20 Sun Jul 4 07:19:55 2004 +++ llvm/lib/CodeGen/IntrinsicLowering.cpp Thu Jul 29 12:20:54 2004 @@ -15,7 +15,7 @@ #include "llvm/Constants.h" #include "llvm/DerivedTypes.h" #include "llvm/Module.h" -#include "llvm/iOther.h" +#include "llvm/Instructions.h" #include using namespace llvm; Index: llvm/lib/CodeGen/MachineFunction.cpp diff -u llvm/lib/CodeGen/MachineFunction.cpp:1.64 llvm/lib/CodeGen/MachineFunction.cpp:1.65 --- llvm/lib/CodeGen/MachineFunction.cpp:1.64 Wed Jul 7 19:47:58 2004 +++ llvm/lib/CodeGen/MachineFunction.cpp Thu Jul 29 12:20:54 2004 @@ -23,7 +23,7 @@ #include "llvm/Target/TargetMachine.h" #include "llvm/Target/TargetFrameInfo.h" #include "llvm/Function.h" -#include "llvm/iOther.h" +#include "llvm/Instructions.h" #include "llvm/Type.h" #include "Support/LeakDetector.h" #include "Support/GraphWriter.h" Index: llvm/lib/CodeGen/MachineInstrAnnot.cpp diff -u llvm/lib/CodeGen/MachineInstrAnnot.cpp:1.12 llvm/lib/CodeGen/MachineInstrAnnot.cpp:1.13 --- llvm/lib/CodeGen/MachineInstrAnnot.cpp:1.12 Sun Feb 29 13:12:51 2004 +++ llvm/lib/CodeGen/MachineInstrAnnot.cpp Thu Jul 29 12:20:54 2004 @@ -15,7 +15,7 @@ #include "../Target/SparcV9/MachineInstrAnnot.h" #include "llvm/CodeGen/InstrSelection.h" #include "llvm/CodeGen/MachineCodeForInstruction.h" -#include "llvm/iOther.h" +#include "llvm/Instructions.h" #include "llvm/Type.h" using namespace llvm; From brukman at cs.uiuc.edu Thu Jul 29 12:22:08 2004 From: brukman at cs.uiuc.edu (Misha Brukman) Date: Thu, 29 Jul 2004 12:22:08 -0500 Subject: [llvm-commits] CVS: llvm/lib/Transforms/Utils/BasicBlockUtils.cpp BreakCriticalEdges.cpp CloneTrace.cpp PromoteMemoryToRegister.cpp Message-ID: <200407291722.MAA15244@zion.cs.uiuc.edu> Changes in directory llvm/lib/Transforms/Utils: BasicBlockUtils.cpp updated: 1.10 -> 1.11 BreakCriticalEdges.cpp updated: 1.19 -> 1.20 CloneTrace.cpp updated: 1.7 -> 1.8 PromoteMemoryToRegister.cpp updated: 1.64 -> 1.65 --- Log message: Fix #includes of i*.h => Instructions.h as per PR403: http://llvm.cs.uiuc.edu/PR403 . --- Diffs of the changes: (+4 -6) Index: llvm/lib/Transforms/Utils/BasicBlockUtils.cpp diff -u llvm/lib/Transforms/Utils/BasicBlockUtils.cpp:1.10 llvm/lib/Transforms/Utils/BasicBlockUtils.cpp:1.11 --- llvm/lib/Transforms/Utils/BasicBlockUtils.cpp:1.10 Fri Jan 9 00:12:10 2004 +++ llvm/lib/Transforms/Utils/BasicBlockUtils.cpp Thu Jul 29 12:21:57 2004 @@ -14,7 +14,7 @@ #include "llvm/Transforms/Utils/BasicBlockUtils.h" #include "llvm/Function.h" -#include "llvm/iTerminators.h" +#include "llvm/Instructions.h" #include "llvm/Constant.h" #include "llvm/Type.h" #include Index: llvm/lib/Transforms/Utils/BreakCriticalEdges.cpp diff -u llvm/lib/Transforms/Utils/BreakCriticalEdges.cpp:1.19 llvm/lib/Transforms/Utils/BreakCriticalEdges.cpp:1.20 --- llvm/lib/Transforms/Utils/BreakCriticalEdges.cpp:1.19 Sun Feb 29 16:24:41 2004 +++ llvm/lib/Transforms/Utils/BreakCriticalEdges.cpp Thu Jul 29 12:21:57 2004 @@ -20,7 +20,7 @@ #include "llvm/Transforms/Utils/BasicBlockUtils.h" #include "llvm/Analysis/Dominators.h" #include "llvm/Function.h" -#include "llvm/iTerminators.h" +#include "llvm/Instructions.h" #include "llvm/iPHINode.h" #include "llvm/Support/CFG.h" #include "Support/Statistic.h" Index: llvm/lib/Transforms/Utils/CloneTrace.cpp diff -u llvm/lib/Transforms/Utils/CloneTrace.cpp:1.7 llvm/lib/Transforms/Utils/CloneTrace.cpp:1.8 --- llvm/lib/Transforms/Utils/CloneTrace.cpp:1.7 Wed May 19 04:08:14 2004 +++ llvm/lib/Transforms/Utils/CloneTrace.cpp Thu Jul 29 12:21:57 2004 @@ -17,7 +17,7 @@ #include "llvm/Analysis/Trace.h" #include "llvm/Transforms/Utils/Cloning.h" -#include "llvm/iPHINode.h" +#include "llvm/Instructions.h" #include "llvm/Function.h" #include "ValueMapper.h" using namespace llvm; Index: llvm/lib/Transforms/Utils/PromoteMemoryToRegister.cpp diff -u llvm/lib/Transforms/Utils/PromoteMemoryToRegister.cpp:1.64 llvm/lib/Transforms/Utils/PromoteMemoryToRegister.cpp:1.65 --- llvm/lib/Transforms/Utils/PromoteMemoryToRegister.cpp:1.64 Sat Jun 19 03:42:40 2004 +++ llvm/lib/Transforms/Utils/PromoteMemoryToRegister.cpp Thu Jul 29 12:21:57 2004 @@ -18,9 +18,7 @@ #include "llvm/Transforms/Utils/PromoteMemToReg.h" #include "llvm/Analysis/Dominators.h" -#include "llvm/iMemory.h" -#include "llvm/iPHINode.h" -#include "llvm/iOther.h" +#include "llvm/Instructions.h" #include "llvm/Function.h" #include "llvm/Constant.h" #include "llvm/Support/CFG.h" From lattner at cs.uiuc.edu Thu Jul 29 12:23:10 2004 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Thu, 29 Jul 2004 12:23:10 -0500 Subject: [llvm-commits] CVS: llvm/lib/CodeGen/UnreachableBlockElim.cpp Message-ID: <200407291723.MAA24455@apoc.cs.uiuc.edu> Changes in directory llvm/lib/CodeGen: UnreachableBlockElim.cpp updated: 1.2 -> 1.3 --- Log message: Fix #includes of i*.h => Instructions.h as per PR403: http://llvm.cs.uiuc.edu/PR403 : http://llvm.cs.uiuc.edu/PR403: http://llvm.cs.uiuc.edu/PR403 . --- Diffs of the changes: (+1 -1) Index: llvm/lib/CodeGen/UnreachableBlockElim.cpp diff -u llvm/lib/CodeGen/UnreachableBlockElim.cpp:1.2 llvm/lib/CodeGen/UnreachableBlockElim.cpp:1.3 --- llvm/lib/CodeGen/UnreachableBlockElim.cpp:1.2 Tue Jul 6 01:36:11 2004 +++ llvm/lib/CodeGen/UnreachableBlockElim.cpp Thu Jul 29 12:23:00 2004 @@ -21,8 +21,8 @@ //===----------------------------------------------------------------------===// #include "llvm/CodeGen/Passes.h" -#include "llvm/iPHINode.h" #include "llvm/Constant.h" +#include "llvm/Instructions.h" #include "llvm/Function.h" #include "llvm/Pass.h" #include "llvm/Support/CFG.h" From brukman at cs.uiuc.edu Thu Jul 29 12:23:35 2004 From: brukman at cs.uiuc.edu (Misha Brukman) Date: Thu, 29 Jul 2004 12:23:35 -0500 Subject: [llvm-commits] CVS: llvm/lib/Transforms/Scalar/DecomposeMultiDimRefs.cpp LoopSimplify.cpp LowerAllocations.cpp Mem2Reg.cpp Message-ID: <200407291723.MAA15278@zion.cs.uiuc.edu> Changes in directory llvm/lib/Transforms/Scalar: DecomposeMultiDimRefs.cpp updated: 1.34 -> 1.35 LoopSimplify.cpp updated: 1.47 -> 1.48 LowerAllocations.cpp updated: 1.47 -> 1.48 Mem2Reg.cpp updated: 1.9 -> 1.10 --- Log message: Fix #includes of i*.h => Instructions.h as per PR403: http://llvm.cs.uiuc.edu/PR403 . --- Diffs of the changes: (+4 -7) Index: llvm/lib/Transforms/Scalar/DecomposeMultiDimRefs.cpp diff -u llvm/lib/Transforms/Scalar/DecomposeMultiDimRefs.cpp:1.34 llvm/lib/Transforms/Scalar/DecomposeMultiDimRefs.cpp:1.35 --- llvm/lib/Transforms/Scalar/DecomposeMultiDimRefs.cpp:1.34 Tue Jul 6 14:24:47 2004 +++ llvm/lib/Transforms/Scalar/DecomposeMultiDimRefs.cpp Thu Jul 29 12:23:24 2004 @@ -19,8 +19,7 @@ #include "llvm/DerivedTypes.h" #include "llvm/Constants.h" #include "llvm/Constant.h" -#include "llvm/iMemory.h" -#include "llvm/iOther.h" +#include "llvm/Instructions.h" #include "llvm/BasicBlock.h" #include "llvm/Pass.h" #include "Support/Statistic.h" Index: llvm/lib/Transforms/Scalar/LoopSimplify.cpp diff -u llvm/lib/Transforms/Scalar/LoopSimplify.cpp:1.47 llvm/lib/Transforms/Scalar/LoopSimplify.cpp:1.48 --- llvm/lib/Transforms/Scalar/LoopSimplify.cpp:1.47 Thu Jul 15 03:20:22 2004 +++ llvm/lib/Transforms/Scalar/LoopSimplify.cpp Thu Jul 29 12:23:25 2004 @@ -34,8 +34,7 @@ #include "llvm/Transforms/Scalar.h" #include "llvm/Constant.h" -#include "llvm/iTerminators.h" -#include "llvm/iPHINode.h" +#include "llvm/Instructions.h" #include "llvm/Function.h" #include "llvm/Type.h" #include "llvm/Analysis/Dominators.h" Index: llvm/lib/Transforms/Scalar/LowerAllocations.cpp diff -u llvm/lib/Transforms/Scalar/LowerAllocations.cpp:1.47 llvm/lib/Transforms/Scalar/LowerAllocations.cpp:1.48 --- llvm/lib/Transforms/Scalar/LowerAllocations.cpp:1.47 Wed Jul 14 20:08:08 2004 +++ llvm/lib/Transforms/Scalar/LowerAllocations.cpp Thu Jul 29 12:23:25 2004 @@ -15,8 +15,7 @@ #include "llvm/Transforms/Scalar.h" #include "llvm/Module.h" #include "llvm/DerivedTypes.h" -#include "llvm/iMemory.h" -#include "llvm/iOther.h" +#include "llvm/Instructions.h" #include "llvm/Constants.h" #include "llvm/Pass.h" #include "Support/Statistic.h" Index: llvm/lib/Transforms/Scalar/Mem2Reg.cpp diff -u llvm/lib/Transforms/Scalar/Mem2Reg.cpp:1.9 llvm/lib/Transforms/Scalar/Mem2Reg.cpp:1.10 --- llvm/lib/Transforms/Scalar/Mem2Reg.cpp:1.9 Fri Jan 9 00:02:20 2004 +++ llvm/lib/Transforms/Scalar/Mem2Reg.cpp Thu Jul 29 12:23:25 2004 @@ -15,7 +15,7 @@ #include "llvm/Transforms/Scalar.h" #include "llvm/Transforms/Utils/PromoteMemToReg.h" #include "llvm/Analysis/Dominators.h" -#include "llvm/iMemory.h" +#include "llvm/Instructions.h" #include "llvm/Function.h" #include "llvm/Target/TargetData.h" #include "Support/Statistic.h" From brukman at cs.uiuc.edu Thu Jul 29 12:24:30 2004 From: brukman at cs.uiuc.edu (Misha Brukman) Date: Thu, 29 Jul 2004 12:24:30 -0500 Subject: [llvm-commits] CVS: llvm/lib/Transforms/Utils/BreakCriticalEdges.cpp CloneFunction.cpp Message-ID: <200407291724.MAA15303@zion.cs.uiuc.edu> Changes in directory llvm/lib/Transforms/Utils: BreakCriticalEdges.cpp updated: 1.20 -> 1.21 CloneFunction.cpp updated: 1.22 -> 1.23 --- Log message: Fix #includes of i*.h => Instructions.h as per PR403: http://llvm.cs.uiuc.edu/PR403 . --- Diffs of the changes: (+1 -2) Index: llvm/lib/Transforms/Utils/BreakCriticalEdges.cpp diff -u llvm/lib/Transforms/Utils/BreakCriticalEdges.cpp:1.20 llvm/lib/Transforms/Utils/BreakCriticalEdges.cpp:1.21 --- llvm/lib/Transforms/Utils/BreakCriticalEdges.cpp:1.20 Thu Jul 29 12:21:57 2004 +++ llvm/lib/Transforms/Utils/BreakCriticalEdges.cpp Thu Jul 29 12:24:20 2004 @@ -21,7 +21,6 @@ #include "llvm/Analysis/Dominators.h" #include "llvm/Function.h" #include "llvm/Instructions.h" -#include "llvm/iPHINode.h" #include "llvm/Support/CFG.h" #include "Support/Statistic.h" using namespace llvm; Index: llvm/lib/Transforms/Utils/CloneFunction.cpp diff -u llvm/lib/Transforms/Utils/CloneFunction.cpp:1.22 llvm/lib/Transforms/Utils/CloneFunction.cpp:1.23 --- llvm/lib/Transforms/Utils/CloneFunction.cpp:1.22 Wed May 19 04:08:11 2004 +++ llvm/lib/Transforms/Utils/CloneFunction.cpp Thu Jul 29 12:24:20 2004 @@ -14,7 +14,7 @@ //===----------------------------------------------------------------------===// #include "llvm/Transforms/Utils/Cloning.h" -#include "llvm/iTerminators.h" +#include "llvm/Instructions.h" #include "llvm/DerivedTypes.h" #include "llvm/Function.h" #include "ValueMapper.h" From brukman at cs.uiuc.edu Thu Jul 29 12:25:31 2004 From: brukman at cs.uiuc.edu (Misha Brukman) Date: Thu, 29 Jul 2004 12:25:31 -0500 Subject: [llvm-commits] CVS: llvm/lib/Transforms/Instrumentation/TraceValues.cpp Message-ID: <200407291725.MAA15335@zion.cs.uiuc.edu> Changes in directory llvm/lib/Transforms/Instrumentation: TraceValues.cpp updated: 1.67 -> 1.68 --- Log message: Fix #includes of i*.h => Instructions.h as per PR403: http://llvm.cs.uiuc.edu/PR403 . --- Diffs of the changes: (+1 -3) Index: llvm/lib/Transforms/Instrumentation/TraceValues.cpp diff -u llvm/lib/Transforms/Instrumentation/TraceValues.cpp:1.67 llvm/lib/Transforms/Instrumentation/TraceValues.cpp:1.68 --- llvm/lib/Transforms/Instrumentation/TraceValues.cpp:1.67 Sat Jul 17 19:21:14 2004 +++ llvm/lib/Transforms/Instrumentation/TraceValues.cpp Thu Jul 29 12:25:20 2004 @@ -15,9 +15,7 @@ #include "llvm/Transforms/Instrumentation.h" #include "llvm/Constants.h" #include "llvm/DerivedTypes.h" -#include "llvm/iMemory.h" -#include "llvm/iTerminators.h" -#include "llvm/iOther.h" +#include "llvm/Instructions.h" #include "llvm/Module.h" #include "llvm/Pass.h" #include "llvm/Assembly/Writer.h" From brukman at cs.uiuc.edu Thu Jul 29 12:25:34 2004 From: brukman at cs.uiuc.edu (Misha Brukman) Date: Thu, 29 Jul 2004 12:25:34 -0500 Subject: [llvm-commits] CVS: llvm/lib/Transforms/Instrumentation/ProfilePaths/EdgeCode.cpp Graph.cpp InstLoops.cpp Message-ID: <200407291725.MAA15346@zion.cs.uiuc.edu> Changes in directory llvm/lib/Transforms/Instrumentation/ProfilePaths: EdgeCode.cpp updated: 1.27 -> 1.28 Graph.cpp updated: 1.16 -> 1.17 InstLoops.cpp updated: 1.15 -> 1.16 --- Log message: Fix #includes of i*.h => Instructions.h as per PR403: http://llvm.cs.uiuc.edu/PR403 . --- Diffs of the changes: (+4 -10) Index: llvm/lib/Transforms/Instrumentation/ProfilePaths/EdgeCode.cpp diff -u llvm/lib/Transforms/Instrumentation/ProfilePaths/EdgeCode.cpp:1.27 llvm/lib/Transforms/Instrumentation/ProfilePaths/EdgeCode.cpp:1.28 --- llvm/lib/Transforms/Instrumentation/ProfilePaths/EdgeCode.cpp:1.27 Thu Nov 20 12:25:21 2003 +++ llvm/lib/Transforms/Instrumentation/ProfilePaths/EdgeCode.cpp Thu Jul 29 12:25:24 2004 @@ -17,11 +17,7 @@ #include "Graph.h" #include "llvm/Constants.h" #include "llvm/DerivedTypes.h" -#include "llvm/iMemory.h" -#include "llvm/iTerminators.h" -#include "llvm/iOther.h" -#include "llvm/iOperators.h" -#include "llvm/iPHINode.h" +#include "llvm/Instructions.h" #include "llvm/Module.h" #define INSERT_LOAD_COUNT Index: llvm/lib/Transforms/Instrumentation/ProfilePaths/Graph.cpp diff -u llvm/lib/Transforms/Instrumentation/ProfilePaths/Graph.cpp:1.16 llvm/lib/Transforms/Instrumentation/ProfilePaths/Graph.cpp:1.17 --- llvm/lib/Transforms/Instrumentation/ProfilePaths/Graph.cpp:1.16 Wed Jul 21 15:50:33 2004 +++ llvm/lib/Transforms/Instrumentation/ProfilePaths/Graph.cpp Thu Jul 29 12:25:24 2004 @@ -13,7 +13,7 @@ //===----------------------------------------------------------------------===// #include "Graph.h" -#include "llvm/iTerminators.h" +#include "llvm/Instructions.h" #include "Support/Debug.h" #include Index: llvm/lib/Transforms/Instrumentation/ProfilePaths/InstLoops.cpp diff -u llvm/lib/Transforms/Instrumentation/ProfilePaths/InstLoops.cpp:1.15 llvm/lib/Transforms/Instrumentation/ProfilePaths/InstLoops.cpp:1.16 --- llvm/lib/Transforms/Instrumentation/ProfilePaths/InstLoops.cpp:1.15 Wed Jul 21 15:50:33 2004 +++ llvm/lib/Transforms/Instrumentation/ProfilePaths/InstLoops.cpp Thu Jul 29 12:25:24 2004 @@ -16,12 +16,10 @@ #include "llvm/Analysis/Dominators.h" #include "llvm/Support/CFG.h" -#include "llvm/iOther.h" -#include "llvm/Type.h" -#include "llvm/iTerminators.h" -#include "llvm/iPHINode.h" +#include "llvm/Instructions.h" #include "llvm/Module.h" #include "llvm/Pass.h" +#include "llvm/Type.h" #include "Support/Debug.h" #include "../ProfilingUtils.h" From brukman at cs.uiuc.edu Thu Jul 29 12:27:03 2004 From: brukman at cs.uiuc.edu (Misha Brukman) Date: Thu, 29 Jul 2004 12:27:03 -0500 Subject: [llvm-commits] CVS: llvm/lib/Transforms/Instrumentation/ProfilePaths/CombineBranch.cpp GraphAuxiliary.cpp ProfilePaths.cpp RetracePath.cpp Message-ID: <200407291727.MAA15391@zion.cs.uiuc.edu> Changes in directory llvm/lib/Transforms/Instrumentation/ProfilePaths: CombineBranch.cpp updated: 1.10 -> 1.11 GraphAuxiliary.cpp updated: 1.23 -> 1.24 ProfilePaths.cpp updated: 1.38 -> 1.39 RetracePath.cpp updated: 1.9 -> 1.10 --- Log message: Fix #includes of i*.h => Instructions.h as per PR403: http://llvm.cs.uiuc.edu/PR403 . --- Diffs of the changes: (+4 -8) Index: llvm/lib/Transforms/Instrumentation/ProfilePaths/CombineBranch.cpp diff -u llvm/lib/Transforms/Instrumentation/ProfilePaths/CombineBranch.cpp:1.10 llvm/lib/Transforms/Instrumentation/ProfilePaths/CombineBranch.cpp:1.11 --- llvm/lib/Transforms/Instrumentation/ProfilePaths/CombineBranch.cpp:1.10 Thu Jun 3 00:03:02 2004 +++ llvm/lib/Transforms/Instrumentation/ProfilePaths/CombineBranch.cpp Thu Jul 29 12:26:53 2004 @@ -14,8 +14,7 @@ //===----------------------------------------------------------------------===// #include "llvm/Support/CFG.h" -#include "llvm/iTerminators.h" -#include "llvm/iPHINode.h" +#include "llvm/Instructions.h" #include "llvm/Function.h" #include "llvm/Pass.h" Index: llvm/lib/Transforms/Instrumentation/ProfilePaths/GraphAuxiliary.cpp diff -u llvm/lib/Transforms/Instrumentation/ProfilePaths/GraphAuxiliary.cpp:1.23 llvm/lib/Transforms/Instrumentation/ProfilePaths/GraphAuxiliary.cpp:1.24 --- llvm/lib/Transforms/Instrumentation/ProfilePaths/GraphAuxiliary.cpp:1.23 Wed Jul 21 15:50:33 2004 +++ llvm/lib/Transforms/Instrumentation/ProfilePaths/GraphAuxiliary.cpp Thu Jul 29 12:26:53 2004 @@ -14,7 +14,7 @@ #include "llvm/Pass.h" #include "llvm/Module.h" -#include "llvm/iTerminators.h" +#include "llvm/Instructions.h" #include "Support/Debug.h" #include #include "Graph.h" Index: llvm/lib/Transforms/Instrumentation/ProfilePaths/ProfilePaths.cpp diff -u llvm/lib/Transforms/Instrumentation/ProfilePaths/ProfilePaths.cpp:1.38 llvm/lib/Transforms/Instrumentation/ProfilePaths/ProfilePaths.cpp:1.39 --- llvm/lib/Transforms/Instrumentation/ProfilePaths/ProfilePaths.cpp:1.38 Tue Nov 11 16:41:33 2003 +++ llvm/lib/Transforms/Instrumentation/ProfilePaths/ProfilePaths.cpp Thu Jul 29 12:26:53 2004 @@ -35,9 +35,7 @@ #include "llvm/Support/CFG.h" #include "llvm/Constants.h" #include "llvm/DerivedTypes.h" -#include "llvm/iMemory.h" -#include "llvm/iOperators.h" -#include "llvm/iOther.h" +#include "llvm/Instructions.h" #include "llvm/Module.h" #include "Graph.h" #include Index: llvm/lib/Transforms/Instrumentation/ProfilePaths/RetracePath.cpp diff -u llvm/lib/Transforms/Instrumentation/ProfilePaths/RetracePath.cpp:1.9 llvm/lib/Transforms/Instrumentation/ProfilePaths/RetracePath.cpp:1.10 --- llvm/lib/Transforms/Instrumentation/ProfilePaths/RetracePath.cpp:1.9 Sun Jul 4 07:19:56 2004 +++ llvm/lib/Transforms/Instrumentation/ProfilePaths/RetracePath.cpp Thu Jul 29 12:26:53 2004 @@ -12,8 +12,7 @@ //===----------------------------------------------------------------------===// #include "llvm/Module.h" -#include "llvm/iTerminators.h" -#include "llvm/iOther.h" +#include "llvm/Instructions.h" #include "llvm/Support/CFG.h" #include "Graph.h" #include From brukman at cs.uiuc.edu Thu Jul 29 12:27:16 2004 From: brukman at cs.uiuc.edu (Misha Brukman) Date: Thu, 29 Jul 2004 12:27:16 -0500 Subject: [llvm-commits] CVS: llvm/lib/Transforms/Instrumentation/TraceBasicBlocks.cpp Message-ID: <200407291727.MAA15404@zion.cs.uiuc.edu> Changes in directory llvm/lib/Transforms/Instrumentation: TraceBasicBlocks.cpp updated: 1.6 -> 1.7 --- Log message: Fix #includes of i*.h => Instructions.h as per PR403: http://llvm.cs.uiuc.edu/PR403 . --- Diffs of the changes: (+1 -3) Index: llvm/lib/Transforms/Instrumentation/TraceBasicBlocks.cpp diff -u llvm/lib/Transforms/Instrumentation/TraceBasicBlocks.cpp:1.6 llvm/lib/Transforms/Instrumentation/TraceBasicBlocks.cpp:1.7 --- llvm/lib/Transforms/Instrumentation/TraceBasicBlocks.cpp:1.6 Wed Jul 21 15:50:33 2004 +++ llvm/lib/Transforms/Instrumentation/TraceBasicBlocks.cpp Thu Jul 29 12:27:02 2004 @@ -18,9 +18,7 @@ #include "llvm/Module.h" #include "llvm/Pass.h" #include "llvm/Transforms/Utils/BasicBlockUtils.h" -#include "llvm/iOther.h" -#include "llvm/iMemory.h" -#include "llvm/iPHINode.h" +#include "llvm/Instructions.h" #include "ProfilingUtils.h" #include "Support/Debug.h" #include From brukman at cs.uiuc.edu Thu Jul 29 12:28:52 2004 From: brukman at cs.uiuc.edu (Misha Brukman) Date: Thu, 29 Jul 2004 12:28:52 -0500 Subject: [llvm-commits] CVS: llvm/lib/Transforms/IPO/DeadArgumentElimination.cpp FunctionResolution.cpp Inliner.cpp LoopExtractor.cpp PruneEH.cpp RaiseAllocations.cpp Message-ID: <200407291728.MAA15455@zion.cs.uiuc.edu> Changes in directory llvm/lib/Transforms/IPO: DeadArgumentElimination.cpp updated: 1.16 -> 1.17 FunctionResolution.cpp updated: 1.49 -> 1.50 Inliner.cpp updated: 1.19 -> 1.20 LoopExtractor.cpp updated: 1.11 -> 1.12 PruneEH.cpp updated: 1.13 -> 1.14 RaiseAllocations.cpp updated: 1.23 -> 1.24 --- Log message: Fix #includes of i*.h => Instructions.h as per PR403: http://llvm.cs.uiuc.edu/PR403 . --- Diffs of the changes: (+6 -11) Index: llvm/lib/Transforms/IPO/DeadArgumentElimination.cpp diff -u llvm/lib/Transforms/IPO/DeadArgumentElimination.cpp:1.16 llvm/lib/Transforms/IPO/DeadArgumentElimination.cpp:1.17 --- llvm/lib/Transforms/IPO/DeadArgumentElimination.cpp:1.16 Sun Feb 8 15:43:47 2004 +++ llvm/lib/Transforms/IPO/DeadArgumentElimination.cpp Thu Jul 29 12:28:42 2004 @@ -22,8 +22,7 @@ #include "llvm/Pass.h" #include "llvm/DerivedTypes.h" #include "llvm/Constant.h" -#include "llvm/iOther.h" -#include "llvm/iTerminators.h" +#include "llvm/Instructions.h" #include "llvm/Support/CallSite.h" #include "Support/Debug.h" #include "Support/Statistic.h" Index: llvm/lib/Transforms/IPO/FunctionResolution.cpp diff -u llvm/lib/Transforms/IPO/FunctionResolution.cpp:1.49 llvm/lib/Transforms/IPO/FunctionResolution.cpp:1.50 --- llvm/lib/Transforms/IPO/FunctionResolution.cpp:1.49 Sat Jul 17 19:24:14 2004 +++ llvm/lib/Transforms/IPO/FunctionResolution.cpp Thu Jul 29 12:28:42 2004 @@ -22,7 +22,7 @@ #include "llvm/Module.h" #include "llvm/DerivedTypes.h" #include "llvm/Pass.h" -#include "llvm/iOther.h" +#include "llvm/Instructions.h" #include "llvm/Constants.h" #include "llvm/Support/CallSite.h" #include "llvm/Target/TargetData.h" Index: llvm/lib/Transforms/IPO/Inliner.cpp diff -u llvm/lib/Transforms/IPO/Inliner.cpp:1.19 llvm/lib/Transforms/IPO/Inliner.cpp:1.20 --- llvm/lib/Transforms/IPO/Inliner.cpp:1.19 Sun Jul 18 16:34:16 2004 +++ llvm/lib/Transforms/IPO/Inliner.cpp Thu Jul 29 12:28:42 2004 @@ -15,8 +15,7 @@ #include "Inliner.h" #include "llvm/Module.h" -#include "llvm/iOther.h" -#include "llvm/iTerminators.h" +#include "llvm/Instructions.h" #include "llvm/Analysis/CallGraph.h" #include "llvm/Support/CallSite.h" #include "llvm/Transforms/Utils/Cloning.h" Index: llvm/lib/Transforms/IPO/LoopExtractor.cpp diff -u llvm/lib/Transforms/IPO/LoopExtractor.cpp:1.11 llvm/lib/Transforms/IPO/LoopExtractor.cpp:1.12 --- llvm/lib/Transforms/IPO/LoopExtractor.cpp:1.11 Sun Apr 18 17:13:44 2004 +++ llvm/lib/Transforms/IPO/LoopExtractor.cpp Thu Jul 29 12:28:42 2004 @@ -15,7 +15,7 @@ //===----------------------------------------------------------------------===// #include "llvm/Transforms/IPO.h" -#include "llvm/iTerminators.h" +#include "llvm/Instructions.h" #include "llvm/Module.h" #include "llvm/Pass.h" #include "llvm/Analysis/Dominators.h" Index: llvm/lib/Transforms/IPO/PruneEH.cpp diff -u llvm/lib/Transforms/IPO/PruneEH.cpp:1.13 llvm/lib/Transforms/IPO/PruneEH.cpp:1.14 --- llvm/lib/Transforms/IPO/PruneEH.cpp:1.13 Sun Apr 11 23:06:38 2004 +++ llvm/lib/Transforms/IPO/PruneEH.cpp Thu Jul 29 12:28:42 2004 @@ -18,8 +18,7 @@ #include "llvm/CallGraphSCCPass.h" #include "llvm/Function.h" #include "llvm/Intrinsics.h" -#include "llvm/iTerminators.h" -#include "llvm/iOther.h" +#include "llvm/Instructions.h" #include "llvm/Analysis/CallGraph.h" #include "Support/Statistic.h" #include Index: llvm/lib/Transforms/IPO/RaiseAllocations.cpp diff -u llvm/lib/Transforms/IPO/RaiseAllocations.cpp:1.23 llvm/lib/Transforms/IPO/RaiseAllocations.cpp:1.24 --- llvm/lib/Transforms/IPO/RaiseAllocations.cpp:1.23 Sat Jul 17 19:22:14 2004 +++ llvm/lib/Transforms/IPO/RaiseAllocations.cpp Thu Jul 29 12:28:42 2004 @@ -16,9 +16,7 @@ #include "llvm/Constants.h" #include "llvm/DerivedTypes.h" #include "llvm/Module.h" -#include "llvm/iMemory.h" -#include "llvm/iTerminators.h" -#include "llvm/iOther.h" +#include "llvm/Instructions.h" #include "llvm/Pass.h" #include "llvm/Support/CallSite.h" #include "Support/Statistic.h" From brukman at cs.uiuc.edu Thu Jul 29 12:31:06 2004 From: brukman at cs.uiuc.edu (Misha Brukman) Date: Thu, 29 Jul 2004 12:31:06 -0500 Subject: [llvm-commits] CVS: llvm/docs/ExtendingLLVM.html Message-ID: <200407291731.MAA15523@zion.cs.uiuc.edu> Changes in directory llvm/docs: ExtendingLLVM.html updated: 1.7 -> 1.8 --- Log message: Fix #includes of i*.h => Instructions.h as per PR403: http://llvm.cs.uiuc.edu/PR403 . --- Diffs of the changes: (+2 -2) Index: llvm/docs/ExtendingLLVM.html diff -u llvm/docs/ExtendingLLVM.html:1.7 llvm/docs/ExtendingLLVM.html:1.8 --- llvm/docs/ExtendingLLVM.html:1.7 Sun Jun 20 02:53:22 2004 +++ llvm/docs/ExtendingLLVM.html Thu Jul 29 12:30:56 2004 @@ -135,7 +135,7 @@
  • llvm/include/llvm/Instruction.def: add a number for your instruction and an enum name
    • -
  • llvm/include/llvm/i*.h: +
  • llvm/include/llvm/Instructions.h: add a definition for the class that will represent your instruction
  • llvm/include/llvm/Support/InstVisitor.h: @@ -231,7 +231,7 @@ Misha Brukman
    The LLVM Compiler Infrastructure
    - Last modified: $Date: 2004/06/20 07:53:22 $ + Last modified: $Date: 2004/07/29 17:30:56 $ From lattner at cs.uiuc.edu Thu Jul 29 12:32:07 2004 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Thu, 29 Jul 2004 12:32:07 -0500 Subject: [llvm-commits] CVS: llvm/docs/ExtendingLLVM.html Message-ID: <200407291732.MAA09592@apoc.cs.uiuc.edu> Changes in directory llvm/docs: ExtendingLLVM.html updated: 1.8 -> 1.9 --- Log message: Fix #includes of i*.h => Instructions.h as per PR403: http://llvm.cs.uiuc.edu/PR403 : http://llvm.cs.uiuc.edu/PR403: http://llvm.cs.uiuc.edu/PR403 . --- Diffs of the changes: (+3 -3) Index: llvm/docs/ExtendingLLVM.html diff -u llvm/docs/ExtendingLLVM.html:1.8 llvm/docs/ExtendingLLVM.html:1.9 --- llvm/docs/ExtendingLLVM.html:1.8 Thu Jul 29 12:30:56 2004 +++ llvm/docs/ExtendingLLVM.html Thu Jul 29 12:31:57 2004 @@ -154,8 +154,8 @@
  • llvm/lib/VMCore/Instruction.cpp: add a case for how your instruction will be printed out to assembly
    • -
  • llvm/lib/VMCore/i*.cpp: - implement the class you defined in llvm/include/llvm/i*.h
    • +
  • llvm/lib/VMCore/Instructions.cpp: + implement the class you defined in llvm/include/llvm/Instructions.h
    • @@ -231,7 +231,7 @@ Misha Brukman
    The LLVM Compiler Infrastructure
    - Last modified: $Date: 2004/07/29 17:30:56 $ + Last modified: $Date: 2004/07/29 17:31:57 $ From gaeke at cs.uiuc.edu Thu Jul 29 16:31:30 2004 From: gaeke at cs.uiuc.edu (Brian Gaeke) Date: Thu, 29 Jul 2004 16:31:30 -0500 Subject: [llvm-commits] CVS: llvm/lib/CodeGen/InstrSched/InstrScheduling.cpp Message-ID: <200407292131.QAA13817@zion.cs.uiuc.edu> Changes in directory llvm/lib/CodeGen/InstrSched: InstrScheduling.cpp updated: 1.74 -> 1.75 --- Log message: Convert a few assertions with side-effects into regular old runtime checks. These side-effects seem to make a difference when using llc -march=sparcv9 in Release mode (i.e., with -DNDEBUG); when they are left out, lots of instructions just get dropped on the floor, because they never end up in the schedule. --- Diffs of the changes: (+8 -5) Index: llvm/lib/CodeGen/InstrSched/InstrScheduling.cpp diff -u llvm/lib/CodeGen/InstrSched/InstrScheduling.cpp:1.74 llvm/lib/CodeGen/InstrSched/InstrScheduling.cpp:1.75 --- llvm/lib/CodeGen/InstrSched/InstrScheduling.cpp:1.74 Wed Jul 28 14:24:48 2004 +++ llvm/lib/CodeGen/InstrSched/InstrScheduling.cpp Thu Jul 29 16:31:20 2004 @@ -193,7 +193,10 @@ unsigned int slotNum, cycles_t cycle) { InstrGroup* igroup = this->getIGroup(cycle); - assert((*igroup)[slotNum] == NULL && "Slot already filled?"); + if (!((*igroup)[slotNum] == NULL)) { + std::cerr << "Slot already filled?\n"; + abort(); + } igroup->addInstr(node, slotNum); assert(node->getNodeId() < startTime.size()); startTime[node->getNodeId()] = cycle; @@ -626,7 +629,6 @@ { const TargetInstrInfo& mii = S.schedInfo.getInstrInfo(); -#ifndef NDEBUG // Lets make sure we didn't lose any instructions, except possibly // some NOPs from delay slots. Also, PHIs are not included in the schedule. unsigned numInstr = 0; @@ -636,7 +638,6 @@ ++numInstr; assert(S.isched.getNumInstructions() >= numInstr && "Lost some non-NOP instructions during scheduling!"); -#endif if (S.isched.getNumInstructions() == 0) return; // empty basic block! @@ -1174,8 +1175,10 @@ MachineBasicBlock& MBB = node->getMachineBasicBlock(); MachineBasicBlock::iterator MBBI = MBB.begin(); std::advance(MBBI, firstDelaySlotIdx - 1); - assert(&*MBBI++ == brInstr && - "Incorrect instr. index in basic block for brInstr"); + if (!(&*MBBI++ == brInstr)) { + std::cerr << "Incorrect instr. index in basic block for brInstr"; + abort(); + } // First find all useful instructions already in the delay slots // and USE THEM. We'll throw away the unused alternatives below From gaeke at cs.uiuc.edu Thu Jul 29 23:04:54 2004 From: gaeke at cs.uiuc.edu (Brian Gaeke) Date: Thu, 29 Jul 2004 23:04:54 -0500 Subject: [llvm-commits] CVS: reopt/lib/Inst/lib/Phase1/Phase1.cpp PrimInfo.cpp Message-ID: <200407300404.XAA03730@zion.cs.uiuc.edu> Changes in directory reopt/lib/Inst/lib/Phase1: Phase1.cpp updated: 1.32 -> 1.33 PrimInfo.cpp updated: 1.20 -> 1.21 --- Log message: Automatic change: include Instructions.h instead of various i*.h files --- Diffs of the changes: (+2 -5) Index: reopt/lib/Inst/lib/Phase1/Phase1.cpp diff -u reopt/lib/Inst/lib/Phase1/Phase1.cpp:1.32 reopt/lib/Inst/lib/Phase1/Phase1.cpp:1.33 --- reopt/lib/Inst/lib/Phase1/Phase1.cpp:1.32 Tue Jul 20 17:22:59 2004 +++ reopt/lib/Inst/lib/Phase1/Phase1.cpp Thu Jul 29 23:04:44 2004 @@ -16,10 +16,7 @@ #include "llvm/Module.h" #include "llvm/Type.h" #include "llvm/DerivedTypes.h" -#include "llvm/iOther.h" -#include "llvm/iTerminators.h" -#include "llvm/iMemory.h" -#include "llvm/iOperators.h" +#include "llvm/Instructions.h" #include "llvm/Constant.h" #include "llvm/Constants.h" #include "Support/STLExtras.h" Index: reopt/lib/Inst/lib/Phase1/PrimInfo.cpp diff -u reopt/lib/Inst/lib/Phase1/PrimInfo.cpp:1.20 reopt/lib/Inst/lib/Phase1/PrimInfo.cpp:1.21 --- reopt/lib/Inst/lib/Phase1/PrimInfo.cpp:1.20 Tue Jul 20 17:22:59 2004 +++ reopt/lib/Inst/lib/Phase1/PrimInfo.cpp Thu Jul 29 23:04:44 2004 @@ -17,7 +17,7 @@ #include "llvm/Type.h" #include "llvm/DerivedTypes.h" #include "llvm/Constants.h" -#include "llvm/iOther.h" +#include "llvm/Instructions.h" #include "llvm/GlobalVariable.h" #include "llvm/Constant.h" #include "Support/VectorExtras.h" From gaeke at cs.uiuc.edu Thu Jul 29 23:04:54 2004 From: gaeke at cs.uiuc.edu (Brian Gaeke) Date: Thu, 29 Jul 2004 23:04:54 -0500 Subject: [llvm-commits] CVS: reopt/lib/BinInterface/LLVMTrace.cpp Message-ID: <200407300404.XAA03724@zion.cs.uiuc.edu> Changes in directory reopt/lib/BinInterface: LLVMTrace.cpp updated: 1.7 -> 1.8 --- Log message: Automatic change: include Instructions.h instead of various i*.h files --- Diffs of the changes: (+1 -2) Index: reopt/lib/BinInterface/LLVMTrace.cpp diff -u reopt/lib/BinInterface/LLVMTrace.cpp:1.7 reopt/lib/BinInterface/LLVMTrace.cpp:1.8 --- reopt/lib/BinInterface/LLVMTrace.cpp:1.7 Wed Jul 21 15:53:28 2004 +++ reopt/lib/BinInterface/LLVMTrace.cpp Thu Jul 29 23:04:44 2004 @@ -10,9 +10,8 @@ #include "reopt/TraceCache.h" #include "reopt/VirtualMem.h" #include "reopt/InstrUtils.h" -#include "llvm/iTerminators.h" +#include "llvm/Instructions.h" #include "llvm/BasicBlock.h" -#include "llvm/iPHINode.h" #include "Support/Debug.h" using namespace llvm; From gaeke at cs.uiuc.edu Thu Jul 29 23:04:54 2004 From: gaeke at cs.uiuc.edu (Brian Gaeke) Date: Thu, 29 Jul 2004 23:04:54 -0500 Subject: [llvm-commits] CVS: reopt/lib/LightWtProfiling/SLI.cpp SecondTrigger.cpp UnpackTraceFunction.cpp Message-ID: <200407300404.XAA03744@zion.cs.uiuc.edu> Changes in directory reopt/lib/LightWtProfiling: SLI.cpp updated: 1.20 -> 1.21 SecondTrigger.cpp updated: 1.31 -> 1.32 UnpackTraceFunction.cpp updated: 1.105 -> 1.106 --- Log message: Automatic change: include Instructions.h instead of various i*.h files --- Diffs of the changes: (+3 -4) Index: reopt/lib/LightWtProfiling/SLI.cpp diff -u reopt/lib/LightWtProfiling/SLI.cpp:1.20 reopt/lib/LightWtProfiling/SLI.cpp:1.21 --- reopt/lib/LightWtProfiling/SLI.cpp:1.20 Sun May 23 02:46:25 2004 +++ reopt/lib/LightWtProfiling/SLI.cpp Thu Jul 29 23:04:44 2004 @@ -23,7 +23,7 @@ #include "reopt/InstrUtils.h" #include "reopt/TraceCache.h" #include "reopt/VirtualMem.h" -#include "llvm/iTerminators.h" +#include "llvm/Instructions.h" #include "llvm/Support/CFG.h" #include "llvm/Module.h" #include Index: reopt/lib/LightWtProfiling/SecondTrigger.cpp diff -u reopt/lib/LightWtProfiling/SecondTrigger.cpp:1.31 reopt/lib/LightWtProfiling/SecondTrigger.cpp:1.32 --- reopt/lib/LightWtProfiling/SecondTrigger.cpp:1.31 Sun Jun 27 21:28:06 2004 +++ reopt/lib/LightWtProfiling/SecondTrigger.cpp Thu Jul 29 23:04:44 2004 @@ -20,7 +20,7 @@ #include "RegSaveRestore.h" #include "Support/Debug.h" #include "llvm/Function.h" -#include "llvm/iTerminators.h" +#include "llvm/Instructions.h" #include "reopt/GetTraceTime.h" #include "reopt/InstrUtils.h" #include "reopt/MappingInfo.h" Index: reopt/lib/LightWtProfiling/UnpackTraceFunction.cpp diff -u reopt/lib/LightWtProfiling/UnpackTraceFunction.cpp:1.105 reopt/lib/LightWtProfiling/UnpackTraceFunction.cpp:1.106 --- reopt/lib/LightWtProfiling/UnpackTraceFunction.cpp:1.105 Wed Jul 28 13:00:42 2004 +++ reopt/lib/LightWtProfiling/UnpackTraceFunction.cpp Thu Jul 29 23:04:44 2004 @@ -21,8 +21,7 @@ #include "llvm/CodeGen/MachineCodeForInstruction.h" #include "llvm/Support/CFG.h" #include "llvm/Module.h" -#include "llvm/iPHINode.h" -#include "llvm/iTerminators.h" +#include "llvm/Instructions.h" #include "llvm/Assembly/Writer.h" #include "Support/StringExtras.h" // for utostr() #include "Support/Debug.h" From gaeke at cs.uiuc.edu Thu Jul 29 23:04:54 2004 From: gaeke at cs.uiuc.edu (Brian Gaeke) Date: Thu, 29 Jul 2004 23:04:54 -0500 Subject: [llvm-commits] CVS: reopt/lib/Mapping/ValueAllocState.cpp Message-ID: <200407300404.XAA03741@zion.cs.uiuc.edu> Changes in directory reopt/lib/Mapping: ValueAllocState.cpp updated: 1.2 -> 1.3 --- Log message: Automatic change: include Instructions.h instead of various i*.h files --- Diffs of the changes: (+1 -1) Index: reopt/lib/Mapping/ValueAllocState.cpp diff -u reopt/lib/Mapping/ValueAllocState.cpp:1.2 reopt/lib/Mapping/ValueAllocState.cpp:1.3 --- reopt/lib/Mapping/ValueAllocState.cpp:1.2 Wed Jul 21 15:53:28 2004 +++ reopt/lib/Mapping/ValueAllocState.cpp Thu Jul 29 23:04:44 2004 @@ -17,7 +17,7 @@ #include "reopt/MappingInfo.h" #include "llvm/Module.h" #include "llvm/Argument.h" -#include "llvm/iPHINode.h" +#include "llvm/Instructions.h" #include "llvm/Support/InstIterator.h" #include "Support/Debug.h" #include "../../../../lib/Target/SparcV9/RegAlloc/AllocInfo.h" From gaeke at cs.uiuc.edu Thu Jul 29 23:04:54 2004 From: gaeke at cs.uiuc.edu (Brian Gaeke) Date: Thu, 29 Jul 2004 23:04:54 -0500 Subject: [llvm-commits] CVS: reopt/lib/Optimizations/RuntimeLICM.cpp Message-ID: <200407300404.XAA03757@zion.cs.uiuc.edu> Changes in directory reopt/lib/Optimizations: RuntimeLICM.cpp updated: 1.4 -> 1.5 --- Log message: Automatic change: include Instructions.h instead of various i*.h files --- Diffs of the changes: (+1 -2) Index: reopt/lib/Optimizations/RuntimeLICM.cpp diff -u reopt/lib/Optimizations/RuntimeLICM.cpp:1.4 reopt/lib/Optimizations/RuntimeLICM.cpp:1.5 --- reopt/lib/Optimizations/RuntimeLICM.cpp:1.4 Wed Jul 21 15:53:28 2004 +++ reopt/lib/Optimizations/RuntimeLICM.cpp Thu Jul 29 23:04:44 2004 @@ -8,8 +8,7 @@ #include "llvm/BasicBlock.h" #include "llvm/Instruction.h" -#include "llvm/iMemory.h" -#include "llvm/iPHINode.h" +#include "llvm/Instructions.h" #include "reopt/BinInterface/LLVMTrace.h" #include "Support/Debug.h" #include From gaeke at cs.uiuc.edu Thu Jul 29 23:04:54 2004 From: gaeke at cs.uiuc.edu (Brian Gaeke) Date: Thu, 29 Jul 2004 23:04:54 -0500 Subject: [llvm-commits] CVS: reopt/lib/Trigger/Trigger.cpp TriggerAuxillary.cpp Message-ID: <200407300404.XAA03773@zion.cs.uiuc.edu> Changes in directory reopt/lib/Trigger: Trigger.cpp updated: 1.23 -> 1.24 TriggerAuxillary.cpp updated: 1.9 -> 1.10 --- Log message: Automatic change: include Instructions.h instead of various i*.h files --- Diffs of the changes: (+2 -9) Index: reopt/lib/Trigger/Trigger.cpp diff -u reopt/lib/Trigger/Trigger.cpp:1.23 reopt/lib/Trigger/Trigger.cpp:1.24 --- reopt/lib/Trigger/Trigger.cpp:1.23 Wed Nov 19 16:51:53 2003 +++ reopt/lib/Trigger/Trigger.cpp Thu Jul 29 23:04:44 2004 @@ -21,10 +21,7 @@ #include "reopt/InstrUtils.h" #include "llvm/Bytecode/Reader.h" #include "llvm/Module.h" -#include "llvm/iTerminators.h" -#include "llvm/iOther.h" -#include "llvm/iPHINode.h" -#include "llvm/iMemory.h" +#include "llvm/Instructions.h" #include "llvm/Support/CFG.h" #include "TriggerAuxillary.h" #include Index: reopt/lib/Trigger/TriggerAuxillary.cpp diff -u reopt/lib/Trigger/TriggerAuxillary.cpp:1.9 reopt/lib/Trigger/TriggerAuxillary.cpp:1.10 --- reopt/lib/Trigger/TriggerAuxillary.cpp:1.9 Wed Nov 19 16:51:53 2003 +++ reopt/lib/Trigger/TriggerAuxillary.cpp Thu Jul 29 23:04:44 2004 @@ -18,11 +18,7 @@ #include "reopt/InstrUtils.h" #include "llvm/Bytecode/Reader.h" #include "llvm/Module.h" -#include "llvm/iTerminators.h" -#include "llvm/iOther.h" -#include "llvm/iPHINode.h" -#include "llvm/iMemory.h" -#include "llvm/iOperators.h" +#include "llvm/Instructions.h" #include "llvm/Support/CFG.h" #include "TriggerAuxillary.h" #include From gaeke at cs.uiuc.edu Thu Jul 29 23:04:54 2004 From: gaeke at cs.uiuc.edu (Brian Gaeke) Date: Thu, 29 Jul 2004 23:04:54 -0500 Subject: [llvm-commits] CVS: reopt/lib/TraceToFunction/TraceToFunction.cpp Message-ID: <200407300404.XAA03764@zion.cs.uiuc.edu> Changes in directory reopt/lib/TraceToFunction: TraceToFunction.cpp updated: 1.81 -> 1.82 --- Log message: Automatic change: include Instructions.h instead of various i*.h files --- Diffs of the changes: (+1 -4) Index: reopt/lib/TraceToFunction/TraceToFunction.cpp diff -u reopt/lib/TraceToFunction/TraceToFunction.cpp:1.81 reopt/lib/TraceToFunction/TraceToFunction.cpp:1.82 --- reopt/lib/TraceToFunction/TraceToFunction.cpp:1.81 Wed Jul 21 15:53:28 2004 +++ reopt/lib/TraceToFunction/TraceToFunction.cpp Thu Jul 29 23:04:44 2004 @@ -27,10 +27,7 @@ #include "llvm/Module.h" #include "llvm/Argument.h" #include "llvm/DerivedTypes.h" -#include "llvm/iTerminators.h" -#include "llvm/iPHINode.h" -#include "llvm/iMemory.h" -#include "llvm/iOther.h" +#include "llvm/Instructions.h" #include "llvm/Constants.h" #include "llvm/Assembly/Writer.h" #include "llvm/Analysis/Dominators.h" From gaeke at cs.uiuc.edu Thu Jul 29 23:07:46 2004 From: gaeke at cs.uiuc.edu (Brian Gaeke) Date: Thu, 29 Jul 2004 23:07:46 -0500 Subject: [llvm-commits] CVS: reopt/lib/LightWtProfiling/scheduler.cpp Message-ID: <200407300407.XAA06753@zion.cs.uiuc.edu> Changes in directory reopt/lib/LightWtProfiling: scheduler.cpp updated: 1.10 -> 1.11 --- Log message: Include to use errno on Linux. --- Diffs of the changes: (+1 -0) Index: reopt/lib/LightWtProfiling/scheduler.cpp diff -u reopt/lib/LightWtProfiling/scheduler.cpp:1.10 reopt/lib/LightWtProfiling/scheduler.cpp:1.11 --- reopt/lib/LightWtProfiling/scheduler.cpp:1.10 Fri Jun 25 01:25:35 2004 +++ reopt/lib/LightWtProfiling/scheduler.cpp Thu Jul 29 23:07:36 2004 @@ -18,6 +18,7 @@ #include #include #include +#include #if !(defined(__linux__) || (defined(__svr4__) && defined(__sparc__))) // We'll just pop enough stuff in here so that scheduler.cpp compiles. From gaeke at cs.uiuc.edu Thu Jul 29 23:07:46 2004 From: gaeke at cs.uiuc.edu (Brian Gaeke) Date: Thu, 29 Jul 2004 23:07:46 -0500 Subject: [llvm-commits] CVS: reopt/lib/TraceIO/TraceReader.cpp Message-ID: <200407300407.XAA06760@zion.cs.uiuc.edu> Changes in directory reopt/lib/TraceIO: TraceReader.cpp updated: 1.3 -> 1.4 --- Log message: Include to use errno on Linux. --- Diffs of the changes: (+1 -0) Index: reopt/lib/TraceIO/TraceReader.cpp diff -u reopt/lib/TraceIO/TraceReader.cpp:1.3 reopt/lib/TraceIO/TraceReader.cpp:1.4 --- reopt/lib/TraceIO/TraceReader.cpp:1.3 Wed Jul 21 15:53:28 2004 +++ reopt/lib/TraceIO/TraceReader.cpp Thu Jul 29 23:07:36 2004 @@ -5,6 +5,7 @@ #include "llvm/Module.h" #include #include +#include using namespace llvm; namespace llvm { From lattner at cs.uiuc.edu Fri Jul 30 01:59:26 2004 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Fri, 30 Jul 2004 01:59:26 -0500 Subject: [llvm-commits] CVS: llvm/include/llvm/Value.h Message-ID: <200407300659.BAA04601@apoc.cs.uiuc.edu> Changes in directory llvm/include/llvm: Value.h updated: 1.60 -> 1.61 --- Log message: I demand the ability to say 'if (isa(V))'! --- Diffs of the changes: (+5 -0) Index: llvm/include/llvm/Value.h diff -u llvm/include/llvm/Value.h:1.60 llvm/include/llvm/Value.h:1.61 --- llvm/include/llvm/Value.h:1.60 Sun Jul 18 19:57:40 2004 +++ llvm/include/llvm/Value.h Fri Jul 30 01:59:15 2004 @@ -136,6 +136,11 @@ return SubclassID; } + // Methods for support type inquiry through isa, cast, and dyn_cast: + static inline bool classof(const Value *V) { + return true; // Values are always values. + } + private: /// FIXME: this is a gross hack, needed by another gross hack. Eliminate! void setValueType(unsigned VT) { SubclassID = VT; } From lattner at cs.uiuc.edu Fri Jul 30 02:45:10 2004 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Fri, 30 Jul 2004 02:45:10 -0500 Subject: [llvm-commits] CVS: llvm/include/llvm/Support/PatternMatch.h Message-ID: <200407300745.CAA05249@apoc.cs.uiuc.edu> Changes in directory llvm/include/llvm/Support: PatternMatch.h added (r1.1) --- Log message: Check in some useful helper routines for doing ML-style pattern matching on the LLVM IR. --- Diffs of the changes: (+280 -0) Index: llvm/include/llvm/Support/PatternMatch.h diff -c /dev/null llvm/include/llvm/Support/PatternMatch.h:1.1 *** /dev/null Fri Jul 30 02:45:10 2004 --- llvm/include/llvm/Support/PatternMatch.h Fri Jul 30 02:45:00 2004 *************** *** 0 **** --- 1,280 ---- + //===-- llvm/Support/PatternMatch.h - Match on the LLVM IR ------*- C++ -*-===// + // + // The LLVM Compiler Infrastructure + // + // This file was developed by the LLVM research group and is distributed under + // the University of Illinois Open Source License. See LICENSE.TXT for details. + // + //===----------------------------------------------------------------------===// + // + // This file provides a simple and efficient mechanism for performing general + // tree-based pattern matches on the LLVM IR. The power of these routines is + // that it allows you to write concise patterns that are expressive and easy to + // understand. The other major advantage of this is that is allows to you + // trivially capture/bind elements in the pattern to variables. For example, + // you can do something like this: + // + // Value *Exp = ... + // Value *X, *Y; ConstantInt *C1, *C2; // (X & C1) | (Y & C2) + // if (match(Exp, m_Or(m_And(m_Value(X), m_ConstantInt(C1)), + // m_And(m_Value(Y), m_ConstantInt(C2))))) { + // ... Pattern is matched and variables are bound ... + // } + // + // This is primarily useful to things like the instruction combiner, but can + // also be useful for static analysis tools or code generators. + // + //===----------------------------------------------------------------------===// + + #ifndef LLVM_SUPPORT_PATTERNMATCH_H + #define LLVM_SUPPORT_PATTERNMATCH_H + + #include "llvm/Constants.h" + #include "llvm/Instructions.h" + + namespace llvm { + namespace PatternMatch { + + template + bool match(Val *V, Pattern P) { + return P.match(V); + } + + template + struct leaf_ty { + template + bool match(ITy *V) { return isa(V); } + }; + + inline leaf_ty m_Value() { return leaf_ty(); } + inline leaf_ty m_ConstantInt() { return leaf_ty(); } + + template + struct bind_ty { + Class *&VR; + bind_ty(Class*& V) :VR(V) {} + + template + bool match(ITy *V) { + if (Class *CV = dyn_cast(V)) { + VR = CV; + return true; + } + return false; + } + }; + + inline bind_ty m_Value(Value *&V) { return V; } + inline bind_ty m_ConstantInt(ConstantInt *&CI) { return CI; } + + //===----------------------------------------------------------------------===// + // Matchers for specific binary operators + // + + template + struct BinaryOp_match { + LHS_t L; + RHS_t R; + + BinaryOp_match(const LHS_t &LHS, const RHS_t &RHS) : L(LHS), R(RHS) {} + + template + bool match(OpTy *V) { + if (Instruction *I = dyn_cast(V)) + return I->getOpcode() == Opcode && L.match(I->getOperand(0)) && + R.match(I->getOperand(1)); + if (ConstantExpr *CE = dyn_cast(V)) + return CE->getOpcode() == Opcode && L.match(CE->getOperand(0)) && + R.match(CE->getOperand(1)); + return false; + } + }; + + template + inline BinaryOp_match m_Add(const LHS &L, + const RHS &R) { + return BinaryOp_match(L, R); + } + + template + inline BinaryOp_match m_Sub(const LHS &L, + const RHS &R) { + return BinaryOp_match(L, R); + } + + template + inline BinaryOp_match m_Mul(const LHS &L, + const RHS &R) { + return BinaryOp_match(L, R); + } + + template + inline BinaryOp_match m_Div(const LHS &L, + const RHS &R) { + return BinaryOp_match(L, R); + } + + template + inline BinaryOp_match m_Rem(const LHS &L, + const RHS &R) { + return BinaryOp_match(L, R); + } + + template + inline BinaryOp_match m_And(const LHS &L, + const RHS &R) { + return BinaryOp_match(L, R); + } + + template + inline BinaryOp_match m_Or(const LHS &L, + const RHS &R) { + return BinaryOp_match(L, R); + } + + template + inline BinaryOp_match m_Xor(const LHS &L, + const RHS &R) { + return BinaryOp_match(L, R); + } + + //===----------------------------------------------------------------------===// + // Matchers for binary classes + // + + template + struct BinaryOpClass_match { + Instruction::BinaryOps &Opcode; + LHS_t L; + RHS_t R; + + BinaryOpClass_match(Instruction::BinaryOps &Op, const LHS_t &LHS, + const RHS_t &RHS) + : Opcode(Op), L(LHS), R(RHS) {} + + template + bool match(OpTy *V) { + if (Class *I = dyn_cast(V)) + if (L.match(I->getOperand(0)) && R.match(I->getOperand(1))) { + Opcode = I->getOpcode(); + return true; + } + #if 0 // Doesn't handle constantexprs yet! + if (ConstantExpr *CE = dyn_cast(V)) + return CE->getOpcode() == Opcode && L.match(CE->getOperand(0)) && + R.match(CE->getOperand(1)); + #endif + return false; + } + }; + + template + inline BinaryOpClass_match + m_SetCond(Instruction::BinaryOps &Op, const LHS &L, const RHS &R) { + return BinaryOpClass_match(Op, L, R); + } + + + //===----------------------------------------------------------------------===// + // Matchers for unary operators + // + + template + struct neg_match { + LHS_t L; + + neg_match(const LHS_t &LHS) : L(LHS) {} + + template + bool match(OpTy *V) { + if (Instruction *I = dyn_cast(V)) + if (I->getOpcode() == Instruction::Sub) + return matchIfNeg(I->getOperand(0), I->getOperand(1)); + if (ConstantExpr *CE = dyn_cast(V)) + if (CE->getOpcode() == Instruction::Sub) + return matchIfNeg(I->getOperand(0), I->getOperand(1)); + if (ConstantInt *CI = dyn_cast(V)) + return L.match(ConstantExpr::getNeg(CI)); + return false; + } + private: + bool matchIfNeg(Value *LHS, Value *RHS) { + if (!LHS->getType()->isFloatingPoint()) + return LHS == Constant::getNullValue(LHS->getType()) && L.match(RHS); + else + return LHS == ConstantFP::get(Bop->getType(), -0.0) && L.match(RHS); + } + }; + + template + inline neg_match m_Neg(const LHS &L) { return L; } + + + template + struct not_match { + LHS_t L; + + not_match(const LHS_t &LHS) : L(LHS) {} + + template + bool match(OpTy *V) { + if (Instruction *I = dyn_cast(V)) + if (I->getOpcode() == Instruction::Xor) + return matchIfNot(I->getOperand(0), I->getOperand(1)); + if (ConstantExpr *CE = dyn_cast(V)) + if (CE->getOpcode() == Instruction::Xor) + return matchIfNot(CE->getOperand(0), CE->getOperand(1)); + if (ConstantInt *CI = dyn_cast(V)) + return L.match(ConstantExpr::getNot(CI)); + return false; + } + private: + bool matchIfNot(Value *LHS, Value *RHS) { + if (ConstantIntegral *CI = dyn_cast(RHS)) + return CI->isAllOnesValue() && L.match(LHS); + else if (ConstantIntegral *CI = dyn_cast(LHS)) + return CI->isAllOnesValue() && L.match(RHS); + return false; + } + }; + + template + inline not_match m_Not(const LHS &L) { return L; } + + //===----------------------------------------------------------------------===// + // Matchers for control flow + // + + template + struct brc_match { + Cond_t Cond; + BasicBlock *&T, *&F; + brc_match(const Cond_t &C, BasicBlock *&t, BasicBlock *&f) + : Cond(C), T(t), F(f) { + } + + template + bool match(OpTy *V) { + if (BranchInst *BI = dyn_cast(V)) + if (BI->isConditional()) { + if (Cond.match(BI->getCondition())) { + T = BI->getSuccessor(0); + F = BI->getSuccessor(1); + return true; + } + } + return false; + } + }; + + template + inline brc_match m_Br(const Cond_t &C, BasicBlock *&T, BasicBlock *&F){ + return brc_match(C, T, F); + } + + + }} // end llvm::match + + + #endif + From lattner at cs.uiuc.edu Fri Jul 30 02:50:13 2004 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Fri, 30 Jul 2004 02:50:13 -0500 Subject: [llvm-commits] CVS: llvm/lib/Transforms/Scalar/InstructionCombining.cpp Message-ID: <200407300750.CAA05273@apoc.cs.uiuc.edu> Changes in directory llvm/lib/Transforms/Scalar: InstructionCombining.cpp updated: 1.233 -> 1.234 --- Log message: Start using the PatternMatcher a bit. --- Diffs of the changes: (+89 -113) Index: llvm/lib/Transforms/Scalar/InstructionCombining.cpp diff -u llvm/lib/Transforms/Scalar/InstructionCombining.cpp:1.233 llvm/lib/Transforms/Scalar/InstructionCombining.cpp:1.234 --- llvm/lib/Transforms/Scalar/InstructionCombining.cpp:1.233 Tue Jul 27 16:02:21 2004 +++ llvm/lib/Transforms/Scalar/InstructionCombining.cpp Fri Jul 30 02:50:03 2004 @@ -48,10 +48,12 @@ #include "llvm/Support/GetElementPtrTypeIterator.h" #include "llvm/Support/InstIterator.h" #include "llvm/Support/InstVisitor.h" +#include "llvm/Support/PatternMatch.h" #include "Support/Debug.h" #include "Support/Statistic.h" #include using namespace llvm; +using namespace llvm::PatternMatch; namespace { Statistic<> NumCombined ("instcombine", "Number of insts combined"); @@ -308,19 +310,6 @@ return 0; } -// dyn_castMaskingAnd - If this value is an And instruction masking a value with -// a constant, return the constant being anded with. -// -template -static inline Constant *dyn_castMaskingAnd(ValueType *V) { - if (Instruction *I = dyn_cast(V)) - if (I->getOpcode() == Instruction::And) - return dyn_cast(I->getOperand(1)); - - // If this is a constant, it acts just like we were masking with it. - return dyn_cast(V); -} - // Log2 - Calculate the log base 2 for the specified value if it is exactly a // power of 2. static unsigned Log2(uint64_t Val) { @@ -433,9 +422,9 @@ Constant *C2; AddMaskingAnd(Constant *c) : C2(c) {} bool shouldApply(Value *LHS) const { - if (Constant *C1 = dyn_castMaskingAnd(LHS)) - return ConstantExpr::getAnd(C1, C2)->isNullValue(); - return false; + ConstantInt *C1; + return match(LHS, m_And(m_Value(), m_ConstantInt(C1))) && + ConstantExpr::getAnd(C1, C2)->isNullValue(); } Instruction *apply(BinaryOperator &Add) const { return BinaryOperator::createOr(Add.getOperand(0), Add.getOperand(1)); @@ -541,28 +530,21 @@ } // (A & C1)+(B & C2) --> (A & C1)|(B & C2) iff C1&C2 == 0 - if (Constant *C2 = dyn_castMaskingAnd(RHS)) + ConstantInt *C2; + if (match(RHS, m_And(m_Value(), m_ConstantInt(C2)))) if (Instruction *R = AssociativeOpt(I, AddMaskingAnd(C2))) return R; if (ConstantInt *CRHS = dyn_cast(RHS)) { - if (Instruction *ILHS = dyn_cast(LHS)) { - switch (ILHS->getOpcode()) { - case Instruction::Xor: - // ~X + C --> (C-1) - X - if (ConstantInt *XorRHS = dyn_cast(ILHS->getOperand(1))) - if (XorRHS->isAllOnesValue()) - return BinaryOperator::createSub(ConstantExpr::getSub(CRHS, - ConstantInt::get(I.getType(), 1)), - ILHS->getOperand(0)); - break; - case Instruction::Select: - // Try to fold constant add into select arguments. - if (Instruction *R = FoldBinOpIntoSelect(I,cast(ILHS),this)) - return R; - - default: break; - } + Value *X; + if (match(LHS, m_Not(m_Value(X)))) { // ~X + C --> (C-1) - X + Constant *C= ConstantExpr::getSub(CRHS, ConstantInt::get(I.getType(), 1)); + return BinaryOperator::createSub(C, X); } + + // Try to fold constant add into select arguments. + if (SelectInst *SI = dyn_cast(LHS)) + if (Instruction *R = FoldBinOpIntoSelect(I, SI, this)) + return R; } return Changed ? &I : 0; @@ -610,9 +592,9 @@ return BinaryOperator::createNot(Op1); // C - ~X == X + (1+C) - if (BinaryOperator::isNot(Op1)) - return BinaryOperator::createAdd( - BinaryOperator::getNotArgument(cast(Op1)), + Value *X; + if (match(Op1, m_Not(m_Value(X)))) + return BinaryOperator::createAdd(X, ConstantExpr::getAdd(C, ConstantInt::get(I.getType(), 1))); // -((uint)X >> 31) -> ((int)X >> 31) // -((int)X >> 31) -> ((uint)X >> 31) @@ -1173,28 +1155,22 @@ if (RHS->isAllOnesValue()) return ReplaceInstUsesWith(I, Op1); - if (Instruction *Op0I = dyn_cast(Op0)) { - // (X & C1) | C2 --> (X | C2) & (C1|C2) - if (Op0I->getOpcode() == Instruction::And && isOnlyUse(Op0)) - if (ConstantInt *Op0CI = dyn_cast(Op0I->getOperand(1))) { - std::string Op0Name = Op0I->getName(); Op0I->setName(""); - Instruction *Or = BinaryOperator::createOr(Op0I->getOperand(0), RHS, - Op0Name); - InsertNewInstBefore(Or, I); - return BinaryOperator::createAnd(Or, ConstantExpr::getOr(RHS, Op0CI)); - } - - // (X ^ C1) | C2 --> (X | C2) ^ (C1&~C2) - if (Op0I->getOpcode() == Instruction::Xor && isOnlyUse(Op0)) - if (ConstantInt *Op0CI = dyn_cast(Op0I->getOperand(1))) { - std::string Op0Name = Op0I->getName(); Op0I->setName(""); - Instruction *Or = BinaryOperator::createOr(Op0I->getOperand(0), RHS, - Op0Name); - InsertNewInstBefore(Or, I); - return BinaryOperator::createXor(Or, - ConstantExpr::getAnd(Op0CI, - ConstantExpr::getNot(RHS))); - } + ConstantInt *C1; Value *X; + // (X & C1) | C2 --> (X | C2) & (C1|C2) + if (match(Op0, m_And(m_Value(X), m_ConstantInt(C1))) && isOnlyUse(Op0)) { + std::string Op0Name = Op0->getName(); Op0->setName(""); + Instruction *Or = BinaryOperator::createOr(X, RHS, Op0Name); + InsertNewInstBefore(Or, I); + return BinaryOperator::createAnd(Or, ConstantExpr::getOr(RHS, C1)); + } + + // (X ^ C1) | C2 --> (X | C2) ^ (C1&~C2) + if (match(Op0, m_Xor(m_Value(X), m_ConstantInt(C1))) && isOnlyUse(Op0)) { + std::string Op0Name = Op0->getName(); Op0->setName(""); + Instruction *Or = BinaryOperator::createOr(X, RHS, Op0Name); + InsertNewInstBefore(Or, I); + return BinaryOperator::createXor(Or, + ConstantExpr::getAnd(C1, ConstantExpr::getNot(RHS))); } // Try to fold constant and into select arguments. @@ -1204,31 +1180,30 @@ } // (A & C1)|(A & C2) == A & (C1|C2) - if (Instruction *LHS = dyn_cast(Op0)) - if (Instruction *RHS = dyn_cast(Op1)) - if (LHS->getOperand(0) == RHS->getOperand(0)) - if (Constant *C0 = dyn_castMaskingAnd(LHS)) - if (Constant *C1 = dyn_castMaskingAnd(RHS)) - return BinaryOperator::createAnd(LHS->getOperand(0), - ConstantExpr::getOr(C0, C1)); - - Value *Op0NotVal = dyn_castNotVal(Op0); - Value *Op1NotVal = dyn_castNotVal(Op1); + Value *A, *B; ConstantInt *C1, *C2; + if (match(Op0, m_And(m_Value(A), m_ConstantInt(C1))) && + match(Op1, m_And(m_Value(B), m_ConstantInt(C2))) && A == B) + return BinaryOperator::createAnd(A, ConstantExpr::getOr(C1, C2)); + + if (match(Op0, m_Not(m_Value(A)))) { // ~A | Op1 + if (A == Op1) // ~A | A == -1 + return ReplaceInstUsesWith(I, + ConstantIntegral::getAllOnesValue(I.getType())); + } else { + A = 0; + } - if (Op1 == Op0NotVal) // ~A | A == -1 - return ReplaceInstUsesWith(I, - ConstantIntegral::getAllOnesValue(I.getType())); - - if (Op0 == Op1NotVal) // A | ~A == -1 - return ReplaceInstUsesWith(I, - ConstantIntegral::getAllOnesValue(I.getType())); + if (match(Op1, m_Not(m_Value(B)))) { // Op0 | ~B + if (Op0 == B) + return ReplaceInstUsesWith(I, + ConstantIntegral::getAllOnesValue(I.getType())); - // (~A | ~B) == (~(A & B)) - Demorgan's Law - if (Op0NotVal && Op1NotVal && isOnlyUse(Op0) && isOnlyUse(Op1)) { - Value *And = InsertNewInstBefore( - BinaryOperator::createAnd(Op0NotVal, - Op1NotVal,I.getName()+".demorgan"),I); - return BinaryOperator::createNot(And); + // (~A | ~B) == (~(A & B)) - Demorgan's Law + if (A && isOnlyUse(Op0) && isOnlyUse(Op1)) { + Value *And = InsertNewInstBefore(BinaryOperator::createAnd(A, B, + I.getName()+".demorgan"), I); + return BinaryOperator::createNot(And); + } } // (setcc1 A, B) | (setcc2 A, B) --> (setcc3 A, B) @@ -1369,10 +1344,11 @@ } // (A & C1)^(B & C2) -> (A & C1)|(B & C2) iff C1^C2 == 0 - if (Constant *C1 = dyn_castMaskingAnd(Op0)) - if (Constant *C2 = dyn_castMaskingAnd(Op1)) - if (ConstantExpr::getAnd(C1, C2)->isNullValue()) - return BinaryOperator::createOr(Op0, Op1); + Value *A, *B; ConstantInt *C1, *C2; + if (match(Op0, m_And(m_Value(A), m_ConstantInt(C1))) && + match(Op1, m_And(m_Value(B), m_ConstantInt(C2))) && + ConstantExpr::getXor(C1, C2)->isNullValue()) + return BinaryOperator::createOr(Op0, Op1); // (setcc1 A, B) ^ (setcc2 A, B) --> (setcc3 A, B) if (SetCondInst *RHS = dyn_cast(I.getOperand(1))) @@ -3052,38 +3028,38 @@ Instruction *InstCombiner::visitBranchInst(BranchInst &BI) { // Change br (not X), label True, label False to: br X, label False, True - if (BI.isConditional() && !isa(BI.getCondition())) { - if (Value *V = dyn_castNotVal(BI.getCondition())) { - BasicBlock *TrueDest = BI.getSuccessor(0); - BasicBlock *FalseDest = BI.getSuccessor(1); + Value *X; + BasicBlock *TrueDest; + BasicBlock *FalseDest; + if (match(&BI, m_Br(m_Not(m_Value(X)), TrueDest, FalseDest)) && + !isa(X)) { + // Swap Destinations and condition... + BI.setCondition(X); + BI.setSuccessor(0, FalseDest); + BI.setSuccessor(1, TrueDest); + return &BI; + } + + // Cannonicalize setne -> seteq + Instruction::BinaryOps Op; Value *Y; + if (match(&BI, m_Br(m_SetCond(Op, m_Value(X), m_Value(Y)), + TrueDest, FalseDest))) + if ((Op == Instruction::SetNE || Op == Instruction::SetLE || + Op == Instruction::SetGE) && BI.getCondition()->hasOneUse()) { + SetCondInst *I = cast(BI.getCondition()); + std::string Name = I->getName(); I->setName(""); + Instruction::BinaryOps NewOpcode = SetCondInst::getInverseCondition(Op); + Value *NewSCC = BinaryOperator::create(NewOpcode, X, Y, Name, I); // Swap Destinations and condition... - BI.setCondition(V); + BI.setCondition(NewSCC); BI.setSuccessor(0, FalseDest); BI.setSuccessor(1, TrueDest); + removeFromWorkList(I); + I->getParent()->getInstList().erase(I); + WorkList.push_back(cast(NewSCC)); return &BI; - } else if (SetCondInst *I = dyn_cast(BI.getCondition())) { - // Cannonicalize setne -> seteq - if ((I->getOpcode() == Instruction::SetNE || - I->getOpcode() == Instruction::SetLE || - I->getOpcode() == Instruction::SetGE) && I->hasOneUse()) { - std::string Name = I->getName(); I->setName(""); - Instruction::BinaryOps NewOpcode = - SetCondInst::getInverseCondition(I->getOpcode()); - Value *NewSCC = BinaryOperator::create(NewOpcode, I->getOperand(0), - I->getOperand(1), Name, I); - BasicBlock *TrueDest = BI.getSuccessor(0); - BasicBlock *FalseDest = BI.getSuccessor(1); - // Swap Destinations and condition... - BI.setCondition(NewSCC); - BI.setSuccessor(0, FalseDest); - BI.setSuccessor(1, TrueDest); - removeFromWorkList(I); - I->getParent()->getInstList().erase(I); - WorkList.push_back(cast(NewSCC)); - return &BI; - } } - } + return 0; } From brukman at cs.uiuc.edu Fri Jul 30 07:50:18 2004 From: brukman at cs.uiuc.edu (Misha Brukman) Date: Fri, 30 Jul 2004 07:50:18 -0500 Subject: [llvm-commits] CVS: llvm/lib/Transforms/Scalar/InstructionCombining.cpp Message-ID: <200407301250.HAA10407@zion.cs.uiuc.edu> Changes in directory llvm/lib/Transforms/Scalar: InstructionCombining.cpp updated: 1.234 -> 1.235 --- Log message: Fix De Morgan's name. --- Diffs of the changes: (+2 -2) Index: llvm/lib/Transforms/Scalar/InstructionCombining.cpp diff -u llvm/lib/Transforms/Scalar/InstructionCombining.cpp:1.234 llvm/lib/Transforms/Scalar/InstructionCombining.cpp:1.235 --- llvm/lib/Transforms/Scalar/InstructionCombining.cpp:1.234 Fri Jul 30 02:50:03 2004 +++ llvm/lib/Transforms/Scalar/InstructionCombining.cpp Fri Jul 30 07:50:08 2004 @@ -1124,7 +1124,7 @@ if (Op0NotVal == Op1 || Op1NotVal == Op0) // A & ~A == ~A & A == 0 return ReplaceInstUsesWith(I, Constant::getNullValue(I.getType())); - // (~A & ~B) == (~(A | B)) - Demorgan's Law + // (~A & ~B) == (~(A | B)) - De Morgan's Law if (Op0NotVal && Op1NotVal && isOnlyUse(Op0) && isOnlyUse(Op1)) { Instruction *Or = BinaryOperator::createOr(Op0NotVal, Op1NotVal, I.getName()+".demorgan"); @@ -1198,7 +1198,7 @@ return ReplaceInstUsesWith(I, ConstantIntegral::getAllOnesValue(I.getType())); - // (~A | ~B) == (~(A & B)) - Demorgan's Law + // (~A | ~B) == (~(A & B)) - De Morgan's Law if (A && isOnlyUse(Op0) && isOnlyUse(Op1)) { Value *And = InsertNewInstBefore(BinaryOperator::createAnd(A, B, I.getName()+".demorgan"), I); From brukman at cs.uiuc.edu Fri Jul 30 09:33:17 2004 From: brukman at cs.uiuc.edu (Misha Brukman) Date: Fri, 30 Jul 2004 09:33:17 -0500 Subject: [llvm-commits] CVS: llvm/include/llvm/Support/PatternMatch.h Message-ID: <200407301433.JAA14950@zion.cs.uiuc.edu> Changes in directory llvm/include/llvm/Support: PatternMatch.h updated: 1.1 -> 1.2 --- Log message: Enable compilation. --- Diffs of the changes: (+2 -2) Index: llvm/include/llvm/Support/PatternMatch.h diff -u llvm/include/llvm/Support/PatternMatch.h:1.1 llvm/include/llvm/Support/PatternMatch.h:1.2 --- llvm/include/llvm/Support/PatternMatch.h:1.1 Fri Jul 30 02:45:00 2004 +++ llvm/include/llvm/Support/PatternMatch.h Fri Jul 30 09:33:07 2004 @@ -192,7 +192,7 @@ return matchIfNeg(I->getOperand(0), I->getOperand(1)); if (ConstantExpr *CE = dyn_cast(V)) if (CE->getOpcode() == Instruction::Sub) - return matchIfNeg(I->getOperand(0), I->getOperand(1)); + return matchIfNeg(CE->getOperand(0), CE->getOperand(1)); if (ConstantInt *CI = dyn_cast(V)) return L.match(ConstantExpr::getNeg(CI)); return false; @@ -202,7 +202,7 @@ if (!LHS->getType()->isFloatingPoint()) return LHS == Constant::getNullValue(LHS->getType()) && L.match(RHS); else - return LHS == ConstantFP::get(Bop->getType(), -0.0) && L.match(RHS); + return LHS == ConstantFP::get(LHS->getType(), -0.0) && L.match(RHS); } }; From criswell at cs.uiuc.edu Fri Jul 30 16:35:47 2004 From: criswell at cs.uiuc.edu (John Criswell) Date: Fri, 30 Jul 2004 16:35:47 -0500 Subject: [llvm-commits] CVS: llvm/test/Programs/MultiSource/Benchmarks/MallocBench/cfrac/pdefs.h Message-ID: <200407302135.QAA25341@choi.cs.uiuc.edu> Changes in directory llvm/test/Programs/MultiSource/Benchmarks/MallocBench/cfrac: pdefs.h updated: 1.1 -> 1.2 --- Log message: Modified the external declaration of malloc() to match Solaris, Linux, and FreeBSD (minus command line parameters). This should fix build problems on Fedora Core 1 systems. --- Diffs of the changes: (+1 -1) Index: llvm/test/Programs/MultiSource/Benchmarks/MallocBench/cfrac/pdefs.h diff -u llvm/test/Programs/MultiSource/Benchmarks/MallocBench/cfrac/pdefs.h:1.1 llvm/test/Programs/MultiSource/Benchmarks/MallocBench/cfrac/pdefs.h:1.2 --- llvm/test/Programs/MultiSource/Benchmarks/MallocBench/cfrac/pdefs.h:1.1 Thu Feb 19 15:46:33 2004 +++ llvm/test/Programs/MultiSource/Benchmarks/MallocBench/cfrac/pdefs.h Fri Jul 30 16:35:36 2004 @@ -24,7 +24,7 @@ #define allocate(size) (char *) gc_malloc_atomic(size) # else -extern char *malloc(); +extern void *malloc(); #define allocate(size) (char *) malloc(size) # endif From criswell at cs.uiuc.edu Fri Jul 30 17:02:03 2004 From: criswell at cs.uiuc.edu (John Criswell) Date: Fri, 30 Jul 2004 17:02:03 -0500 Subject: [llvm-commits] CVS: llvm/test/Programs/External/SPEC/CINT2000/254.gap/Makefile Message-ID: <200407302202.RAA29503@choi.cs.uiuc.edu> Changes in directory llvm/test/Programs/External/SPEC/CINT2000/254.gap: Makefile updated: 1.4 -> 1.5 --- Log message: Force the inclusion of unistd.h to get the sysconf() definitions. 254.gap is using something that expands to a sysconf() call, but isn't grabbing unistd.h to get value macros/enums. Add another macro indicating that we define certain prototypes since they are now included with unistd.h. --- Diffs of the changes: (+4 -1) Index: llvm/test/Programs/External/SPEC/CINT2000/254.gap/Makefile diff -u llvm/test/Programs/External/SPEC/CINT2000/254.gap/Makefile:1.4 llvm/test/Programs/External/SPEC/CINT2000/254.gap/Makefile:1.5 --- llvm/test/Programs/External/SPEC/CINT2000/254.gap/Makefile:1.4 Wed Feb 25 18:01:20 2004 +++ llvm/test/Programs/External/SPEC/CINT2000/254.gap/Makefile Fri Jul 30 17:01:52 2004 @@ -2,7 +2,10 @@ RUN_OPTIONS = -l ./ -q -m 64M STDOUT_FILENAME = $(RUN_TYPE).out STDIN_FILENAME = $(RUN_TYPE).in -CPPFLAGS = -DSYS_IS_USG -DSYS_HAS_CALLOC_PROTO -DSYS_HAS_IOCTL_PROTO -DSYS_HAS_TIME_PROTO + +# We need to include unistd.h because something with Fedora Core 1 is broken, +# and we need the sysconf() macros. +CPPFLAGS = -include unistd.h -DSYS_IS_USG -DSYS_HAS_CALLOC_PROTO -DSYS_HAS_IOCTL_PROTO -DSYS_HAS_TIME_PROTO -DSYS_HAS_READ_PROTO include ../../Makefile.spec2000 ifeq ($(ARCH),Sparc) CPPFLAGS+= -DSPEC_CPU2000_LP64 From lattner at cs.uiuc.edu Fri Jul 30 17:20:43 2004 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Fri, 30 Jul 2004 17:20:43 -0500 Subject: [llvm-commits] CVS: llvm-www/testresults/index.html Message-ID: <200407302220.RAA14422@apoc.cs.uiuc.edu> Changes in directory llvm-www/testresults: index.html updated: 1.9 -> 1.10 --- Log message: update info --- Diffs of the changes: (+2 -2) Index: llvm-www/testresults/index.html diff -u llvm-www/testresults/index.html:1.9 llvm-www/testresults/index.html:1.10 --- llvm-www/testresults/index.html:1.9 Thu Jul 22 16:25:47 2004 +++ llvm-www/testresults/index.html Fri Jul 30 17:20:33 2004 @@ -25,7 +25,7 @@
  • X86: Linux (Dual P4 Xeon @ 3.06GHz) -- debug build
    • -
  • X86: Linux (P4 @ +
  • X86: Linux (Dual P4 Xeon @ 2.3GHz) -- release build
  • X86: FreeBSD 5.1 (may not be run every day)
    • @@ -41,7 +41,7 @@
    Chris Lattner
    The LLVM Compiler Infrastructure
    - Last modified: $Date: 2004/07/22 21:25:47 $ + Last modified: $Date: 2004/07/30 22:20:33 $ From criswell at cs.uiuc.edu Fri Jul 30 18:00:37 2004 From: criswell at cs.uiuc.edu (John Criswell) Date: Fri, 30 Jul 2004 18:00:37 -0500 Subject: [llvm-commits] CVS: llvm/test/Programs/External/SPEC/CINT2000/252.eon/Makefile Message-ID: <200407302300.SAA04349@choi.cs.uiuc.edu> Changes in directory llvm/test/Programs/External/SPEC/CINT2000/252.eon: Makefile updated: 1.8 -> 1.9 --- Log message: Force the inclusion of errno.h. This is an old program which assumes that it's a variable. Modern UNIX doesn't make that true anymore. --- Diffs of the changes: (+1 -1) Index: llvm/test/Programs/External/SPEC/CINT2000/252.eon/Makefile diff -u llvm/test/Programs/External/SPEC/CINT2000/252.eon/Makefile:1.8 llvm/test/Programs/External/SPEC/CINT2000/252.eon/Makefile:1.9 --- llvm/test/Programs/External/SPEC/CINT2000/252.eon/Makefile:1.8 Tue Apr 13 16:48:26 2004 +++ llvm/test/Programs/External/SPEC/CINT2000/252.eon/Makefile Fri Jul 30 18:00:27 2004 @@ -5,7 +5,7 @@ FP_TOLERANCE := 0.0001 # Yes, we know this is an old crufty C++ benchmark. Don't tell us about it GCC! -CPPFLAGS = -Wno-deprecated -Wno-non-template-friend -DHAS_ERRLIST -DUSE_STRERROR -DSPEC_STDCPP -DNDEBUG +CPPFLAGS = -include errno.h -Wno-deprecated -Wno-non-template-friend -DHAS_ERRLIST -DUSE_STRERROR -DSPEC_STDCPP -DNDEBUG Source = $(addprefix $(SPEC_BENCH_DIR)/src/, \ ggCoverageSolidTexture.cc ggPathDielectricMaterial.cc ggBox2.cc \ From tbrethou at cs.uiuc.edu Fri Jul 30 18:36:21 2004 From: tbrethou at cs.uiuc.edu (Tanya Brethour) Date: Fri, 30 Jul 2004 18:36:21 -0500 (CDT) Subject: [llvm-commits] CVS: llvm/lib/CodeGen/ModuloScheduling/MSSchedule.cpp MSchedGraph.cpp ModuloScheduling.cpp ModuloScheduling.h Message-ID: <200407302336.SAA08418@seraph.cs.uiuc.edu> Changes in directory llvm/lib/CodeGen/ModuloScheduling: MSSchedule.cpp updated: 1.2 -> 1.3 MSchedGraph.cpp updated: 1.4 -> 1.5 ModuloScheduling.cpp updated: 1.20 -> 1.21 ModuloScheduling.h updated: 1.14 -> 1.15 --- Log message: Updated ModuloScheduling. It makes it all the wya through register allocation on the new code!! --- Diffs of the changes: (+745 -298) Index: llvm/lib/CodeGen/ModuloScheduling/MSSchedule.cpp diff -u llvm/lib/CodeGen/ModuloScheduling/MSSchedule.cpp:1.2 llvm/lib/CodeGen/ModuloScheduling/MSSchedule.cpp:1.3 --- llvm/lib/CodeGen/ModuloScheduling/MSSchedule.cpp:1.2 Wed Jul 21 15:50:33 2004 +++ llvm/lib/CodeGen/ModuloScheduling/MSSchedule.cpp Fri Jul 30 18:36:10 2004 @@ -49,12 +49,12 @@ bool MSSchedule::resourcesFree(MSchedGraphNode *node, int cycle) { //Get Resource usage for this instruction - const TargetSchedInfo & msi = node->getParent()->getTarget()->getSchedInfo(); + const TargetSchedInfo *msi = node->getParent()->getTarget()->getSchedInfo(); int currentCycle = cycle; bool success = true; //Get resource usage for this instruction - InstrRUsage rUsage = msi.getInstrRUsage(node->getInst()->getOpcode()); + InstrRUsage rUsage = msi->getInstrRUsage(node->getInst()->getOpcode()); std::vector > resources = rUsage.resourcesByCycle; //Loop over resources in each cycle and increments their usage count @@ -101,7 +101,7 @@ int oldCycle = cycle; DEBUG(std::cerr << "Backtrack\n"); //Get resource usage for this instruction - InstrRUsage rUsage = msi.getInstrRUsage(node->getInst()->getOpcode()); + InstrRUsage rUsage = msi->getInstrRUsage(node->getInst()->getOpcode()); std::vector > resources = rUsage.resourcesByCycle; //Loop over resources in each cycle and increments their usage count Index: llvm/lib/CodeGen/ModuloScheduling/MSchedGraph.cpp diff -u llvm/lib/CodeGen/ModuloScheduling/MSchedGraph.cpp:1.4 llvm/lib/CodeGen/ModuloScheduling/MSchedGraph.cpp:1.5 --- llvm/lib/CodeGen/ModuloScheduling/MSchedGraph.cpp:1.4 Wed Jul 21 15:50:33 2004 +++ llvm/lib/CodeGen/ModuloScheduling/MSchedGraph.cpp Fri Jul 30 18:36:10 2004 @@ -103,7 +103,7 @@ void MSchedGraph::buildNodesAndEdges() { //Get Machine target information for calculating latency - const TargetInstrInfo &MTI = Target.getInstrInfo(); + const TargetInstrInfo *MTI = Target.getInstrInfo(); std::vector memInstructions; std::map > regNumtoNodeMap; @@ -124,16 +124,16 @@ #if 0 // FIXME: LOOK INTO THIS //Check if subsequent instructions can be issued before //the result is ready, if so use min delay. - if(MTI.hasResultInterlock(MIopCode)) - delay = MTI.minLatency(MIopCode); + if(MTI->hasResultInterlock(MIopCode)) + delay = MTI->minLatency(MIopCode); else #endif //Get delay - delay = MTI.maxLatency(opCode); + delay = MTI->maxLatency(opCode); //Create new node for this machine instruction and add to the graph. //Create only if not a nop - if(MTI.isNop(opCode)) + if(MTI->isNop(opCode)) continue; //Add PHI to phi instruction list to be processed later @@ -143,7 +143,7 @@ bool isBranch = false; //We want to flag the branch node to treat it special - if(MTI.isBranch(opCode)) + if(MTI->isBranch(opCode)) isBranch = true; //Node is created and added to the graph automatically @@ -152,7 +152,7 @@ DEBUG(std::cerr << "Created Node: " << *node << "\n"); //Check OpCode to keep track of memory operations to add memory dependencies later. - if(MTI.isLoad(opCode) || MTI.isStore(opCode)) + if(MTI->isLoad(opCode) || MTI->isStore(opCode)) memInstructions.push_back(node); //Loop over all operands, and put them into the register number to @@ -370,7 +370,7 @@ void MSchedGraph::addMemEdges(const std::vector& memInst) { //Get Target machine instruction info - const TargetInstrInfo& TMI = Target.getInstrInfo(); + const TargetInstrInfo *TMI = Target.getInstrInfo(); //Loop over all memory instructions in the vector //Knowing that they are in execution, add true, anti, and output dependencies @@ -383,15 +383,15 @@ for(unsigned destIndex = srcIndex + 1; destIndex < memInst.size(); ++destIndex) { //source is a Load, so add anti-dependencies (store after load) - if(TMI.isLoad(srcNodeOpCode)) - if(TMI.isStore(memInst[destIndex]->getInst()->getOpcode())) + if(TMI->isLoad(srcNodeOpCode)) + if(TMI->isStore(memInst[destIndex]->getInst()->getOpcode())) memInst[srcIndex]->addOutEdge(memInst[destIndex], MSchedGraphEdge::MemoryDep, MSchedGraphEdge::AntiDep); //If source is a store, add output and true dependencies - if(TMI.isStore(srcNodeOpCode)) { - if(TMI.isStore(memInst[destIndex]->getInst()->getOpcode())) + if(TMI->isStore(srcNodeOpCode)) { + if(TMI->isStore(memInst[destIndex]->getInst()->getOpcode())) memInst[srcIndex]->addOutEdge(memInst[destIndex], MSchedGraphEdge::MemoryDep, MSchedGraphEdge::OutputDep); @@ -405,13 +405,13 @@ //All instructions before the src in execution order have an iteration delay of 1 for(unsigned destIndex = 0; destIndex < srcIndex; ++destIndex) { //source is a Load, so add anti-dependencies (store after load) - if(TMI.isLoad(srcNodeOpCode)) - if(TMI.isStore(memInst[destIndex]->getInst()->getOpcode())) + if(TMI->isLoad(srcNodeOpCode)) + if(TMI->isStore(memInst[destIndex]->getInst()->getOpcode())) memInst[srcIndex]->addOutEdge(memInst[destIndex], MSchedGraphEdge::MemoryDep, MSchedGraphEdge::AntiDep, 1); - if(TMI.isStore(srcNodeOpCode)) { - if(TMI.isStore(memInst[destIndex]->getInst()->getOpcode())) + if(TMI->isStore(srcNodeOpCode)) { + if(TMI->isStore(memInst[destIndex]->getInst()->getOpcode())) memInst[srcIndex]->addOutEdge(memInst[destIndex], MSchedGraphEdge::MemoryDep, MSchedGraphEdge::OutputDep, 1); Index: llvm/lib/CodeGen/ModuloScheduling/ModuloScheduling.cpp diff -u llvm/lib/CodeGen/ModuloScheduling/ModuloScheduling.cpp:1.20 llvm/lib/CodeGen/ModuloScheduling/ModuloScheduling.cpp:1.21 --- llvm/lib/CodeGen/ModuloScheduling/ModuloScheduling.cpp:1.20 Wed Jul 21 15:50:33 2004 +++ llvm/lib/CodeGen/ModuloScheduling/ModuloScheduling.cpp Fri Jul 30 18:36:10 2004 @@ -6,17 +6,22 @@ // the University of Illinois Open Source License. See LICENSE.TXT for details. // //===----------------------------------------------------------------------===// -// // -// +// This ModuloScheduling pass is based on the Swing Modulo Scheduling +// algorithm. //===----------------------------------------------------------------------===// #define DEBUG_TYPE "ModuloSched" #include "ModuloScheduling.h" +#include "llvm/Instructions.h" +#include "llvm/Function.h" +#include "llvm/CodeGen/InstrSelection.h" #include "llvm/CodeGen/MachineFunction.h" +#include "llvm/CodeGen/MachineCodeForInstruction.h" #include "llvm/CodeGen/Passes.h" #include "llvm/Support/CFG.h" +#include "Support/Casting.h" #include "llvm/Target/TargetSchedInfo.h" #include "Support/Debug.h" #include "Support/GraphWriter.h" @@ -25,7 +30,8 @@ #include #include #include - +#include "../../Target/SparcV9/SparcV9Internals.h" +#include "../../Target/SparcV9/SparcV9RegisterInfo.h" using namespace llvm; @@ -36,6 +42,8 @@ return new ModuloSchedulingPass(targ); } + +//Graph Traits for printing out the dependence graph template static void WriteGraphToFile(std::ostream &O, const std::string &GraphName, const GraphType >) { @@ -50,6 +58,7 @@ O << "\n"; }; +//Graph Traits for printing out the dependence graph namespace llvm { template<> @@ -100,93 +109,132 @@ return edgelabel; } - - - }; } /// ModuloScheduling::runOnFunction - main transformation entry point +/// The Swing Modulo Schedule algorithm has three basic steps: +/// 1) Computation and Analysis of the dependence graph +/// 2) Ordering of the nodes +/// 3) Scheduling +/// bool ModuloSchedulingPass::runOnFunction(Function &F) { + bool Changed = false; - - DEBUG(std::cerr << "Creating ModuloSchedGraph for each BasicBlock in" + F.getName() + "\n"); + + DEBUG(std::cerr << "Creating ModuloSchedGraph for each valid BasicBlock in" + F.getName() + "\n"); //Get MachineFunction MachineFunction &MF = MachineFunction::get(&F); - - //Iterate over BasicBlocks and do ModuloScheduling if they are valid - for (MachineFunction::const_iterator BI = MF.begin(); BI != MF.end(); ++BI) { - if(MachineBBisValid(BI)) { - MSchedGraph *MSG = new MSchedGraph(BI, target); - - //Write Graph out to file - DEBUG(WriteGraphToFile(std::cerr, F.getName(), MSG)); - - //Print out BB for debugging - DEBUG(BI->print(std::cerr)); - - //Calculate Resource II - int ResMII = calculateResMII(BI); - //Calculate Recurrence II - int RecMII = calculateRecMII(MSG, ResMII); - - II = std::max(RecMII, ResMII); + //Print out machine function + DEBUG(MF.print(std::cerr)); - - DEBUG(std::cerr << "II starts out as " << II << " ( RecMII=" << RecMII << "and ResMII=" << ResMII << "\n"); - - //Calculate Node Properties - calculateNodeAttributes(MSG, ResMII); + //Worklist + std::vector Worklist; + + //Iterate over BasicBlocks and put them into our worklist if they are valid + for (MachineFunction::iterator BI = MF.begin(); BI != MF.end(); ++BI) + if(MachineBBisValid(BI)) + Worklist.push_back(&*BI); + - //Dump node properties if in debug mode - for(std::map::iterator I = nodeToAttributesMap.begin(), E = nodeToAttributesMap.end(); I !=E; ++I) { - DEBUG(std::cerr << "Node: " << *(I->first) << " ASAP: " << I->second.ASAP << " ALAP: " << I->second.ALAP << " MOB: " << I->second.MOB << " Depth: " << I->second.depth << " Height: " << I->second.height << "\n"); - } + //Iterate over the worklist and perform scheduling + for(std::vector::iterator BI = Worklist.begin(), + BE = Worklist.end(); BI != BE; ++BI) { + + MSchedGraph *MSG = new MSchedGraph(*BI, target); + + //Write Graph out to file + DEBUG(WriteGraphToFile(std::cerr, F.getName(), MSG)); + + //Print out BB for debugging + DEBUG((*BI)->print(std::cerr)); + + //Calculate Resource II + int ResMII = calculateResMII(*BI); + + //Calculate Recurrence II + int RecMII = calculateRecMII(MSG, ResMII); + + //Our starting initiation interval is the maximum of RecMII and ResMII + II = std::max(RecMII, ResMII); + + //Print out II, RecMII, and ResMII + DEBUG(std::cerr << "II starts out as " << II << " ( RecMII=" << RecMII << "and ResMII=" << ResMII << "\n"); + + //Calculate Node Properties + calculateNodeAttributes(MSG, ResMII); + + //Dump node properties if in debug mode + DEBUG(for(std::map::iterator I = nodeToAttributesMap.begin(), + E = nodeToAttributesMap.end(); I !=E; ++I) { + std::cerr << "Node: " << *(I->first) << " ASAP: " << I->second.ASAP << " ALAP: " + << I->second.ALAP << " MOB: " << I->second.MOB << " Depth: " << I->second.depth + << " Height: " << I->second.height << "\n"; + }); + + //Put nodes in order to schedule them + computePartialOrder(); + + //Dump out partial order + DEBUG(for(std::vector >::iterator I = partialOrder.begin(), + E = partialOrder.end(); I !=E; ++I) { + std::cerr << "Start set in PO\n"; + for(std::vector::iterator J = I->begin(), JE = I->end(); J != JE; ++J) + std::cerr << "PO:" << **J << "\n"; + }); + + //Place nodes in final order + orderNodes(); + + //Dump out order of nodes + DEBUG(for(std::vector::iterator I = FinalNodeOrder.begin(), E = FinalNodeOrder.end(); I != E; ++I) { + std::cerr << "FO:" << **I << "\n"; + }); + + //Finally schedule nodes + computeSchedule(); + + //Print out final schedule + DEBUG(schedule.print(std::cerr)); - //Put nodes in order to schedule them - computePartialOrder(); - - //Dump out partial order - for(std::vector >::iterator I = partialOrder.begin(), E = partialOrder.end(); I !=E; ++I) { - DEBUG(std::cerr << "Start set in PO\n"); - for(std::vector::iterator J = I->begin(), JE = I->end(); J != JE; ++J) - DEBUG(std::cerr << "PO:" << **J << "\n"); - } - - orderNodes(); - - //Dump out order of nodes - for(std::vector::iterator I = FinalNodeOrder.begin(), E = FinalNodeOrder.end(); I != E; ++I) - DEBUG(std::cerr << "FO:" << **I << "\n"); - - - //Finally schedule nodes - computeSchedule(); - - DEBUG(schedule.print(std::cerr)); - - reconstructLoop(BI); - - nodeToAttributesMap.clear(); - partialOrder.clear(); - recurrenceList.clear(); - FinalNodeOrder.clear(); - schedule.clear(); - } + //Final scheduling step is to reconstruct the loop + reconstructLoop(*BI); + + //Print out new loop + + //Clear out our maps for the next basic block that is processed + nodeToAttributesMap.clear(); + partialOrder.clear(); + recurrenceList.clear(); + FinalNodeOrder.clear(); + schedule.clear(); + + //Clean up. Nuke old MachineBB and llvmBB + //BasicBlock *llvmBB = (BasicBlock*) (*BI)->getBasicBlock(); + //Function *parent = (Function*) llvmBB->getParent(); + //Should't std::find work?? + //parent->getBasicBlockList().erase(std::find(parent->getBasicBlockList().begin(), parent->getBasicBlockList().end(), *llvmBB)); + //parent->getBasicBlockList().erase(llvmBB); + + //delete(llvmBB); + //delete(*BI); } - - + + return Changed; } +/// This function checks if a Machine Basic Block is valid for modulo +/// scheduling. This means that it has no control flow (if/else or +/// calls) in the block. Currently ModuloScheduling only works on +/// single basic block loops. bool ModuloSchedulingPass::MachineBBisValid(const MachineBasicBlock *BI) { - //Valid basic blocks must be loops and can not have if/else statements or calls. bool isLoop = false; //Check first if its a valid loop @@ -196,25 +244,20 @@ isLoop = true; } - if(!isLoop) { - DEBUG(std::cerr << "Basic Block is not a loop\n"); + if(!isLoop) return false; - } - else - DEBUG(std::cerr << "Basic Block is a loop\n"); - + //Get Target machine instruction info - /*const TargetInstrInfo& TMI = targ.getInstrInfo(); + const TargetInstrInfo *TMI = target.getInstrInfo(); - //Check each instruction and look for calls or if/else statements - unsigned count = 0; + //Check each instruction and look for calls for(MachineBasicBlock::const_iterator I = BI->begin(), E = BI->end(); I != E; ++I) { - //Get opcode to check instruction type - MachineOpCode OC = I->getOpcode(); - if(TMI.isControlFlow(OC) && (count+1 < BI->size())) - return false; - count++; - }*/ + //Get opcode to check instruction type + MachineOpCode OC = I->getOpcode(); + if(TMI->isCall(OC)) + return false; + + } return true; } @@ -225,8 +268,8 @@ //for each instruction int ModuloSchedulingPass::calculateResMII(const MachineBasicBlock *BI) { - const TargetInstrInfo & mii = target.getInstrInfo(); - const TargetSchedInfo & msi = target.getSchedInfo(); + const TargetInstrInfo *mii = target.getInstrInfo(); + const TargetSchedInfo *msi = target.getSchedInfo(); int ResMII = 0; @@ -236,7 +279,7 @@ for(MachineBasicBlock::const_iterator I = BI->begin(), E = BI->end(); I != E; ++I) { //Get resource usage for this instruction - InstrRUsage rUsage = msi.getInstrRUsage(I->getOpcode()); + InstrRUsage rUsage = msi->getInstrRUsage(I->getOpcode()); std::vector > resources = rUsage.resourcesByCycle; //Loop over resources in each cycle and increments their usage count @@ -254,7 +297,7 @@ //Find maximum usage count //Get max number of instructions that can be issued at once. (FIXME) - int issueSlots = msi.maxNumIssueTotal; + int issueSlots = msi->maxNumIssueTotal; for(std::map::iterator RB = resourceUsageCount.begin(), RE = resourceUsageCount.end(); RB != RE; ++RB) { @@ -273,19 +316,17 @@ finalUsageCount = ceil(1.0 * usageCount / issueSlots); - DEBUG(std::cerr << "Resource ID: " << RB->first << " (usage=" << usageCount << ", resourceNum=X" << ", issueSlots=" << issueSlots << ", finalUsage=" << finalUsageCount << ")\n"); - //Only keep track of the max ResMII = std::max( (int) finalUsageCount, ResMII); } - DEBUG(std::cerr << "Final Resource MII: " << ResMII << "\n"); - return ResMII; } +/// calculateRecMII - Calculates the value of the highest recurrence +/// By value we mean the total latency int ModuloSchedulingPass::calculateRecMII(MSchedGraph *graph, int MII) { std::vector vNodes; //Loop over all nodes in the graph @@ -297,18 +338,18 @@ int RecMII = 0; for(std::set > >::iterator I = recurrenceList.begin(), E=recurrenceList.end(); I !=E; ++I) { - std::cerr << "Recurrence: \n"; - for(std::vector::const_iterator N = I->second.begin(), NE = I->second.end(); N != NE; ++N) { + DEBUG(for(std::vector::const_iterator N = I->second.begin(), NE = I->second.end(); N != NE; ++N) { std::cerr << **N << "\n"; - } + }); RecMII = std::max(RecMII, I->first); - std::cerr << "End Recurrence with RecMII: " << I->first << "\n"; - } - DEBUG(std::cerr << "RecMII: " << RecMII << "\n"); - + } + return MII; } +/// calculateNodeAttributes - The following properties are calculated for +/// each node in the dependence graph: ASAP, ALAP, Depth, Height, and +/// MOB. void ModuloSchedulingPass::calculateNodeAttributes(MSchedGraph *graph, int MII) { //Loop over the nodes and add them to the map @@ -348,15 +389,18 @@ } +/// ignoreEdge - Checks to see if this edge of a recurrence should be ignored or not bool ModuloSchedulingPass::ignoreEdge(MSchedGraphNode *srcNode, MSchedGraphNode *destNode) { if(destNode == 0 || srcNode ==0) return false; - + bool findEdge = edgesToIgnore.count(std::make_pair(srcNode, destNode->getInEdgeNum(srcNode))); return findEdge; } + +/// calculateASAP - Calculates the int ModuloSchedulingPass::calculateASAP(MSchedGraphNode *node, int MII, MSchedGraphNode *destNode) { DEBUG(std::cerr << "Calculating ASAP for " << *node << "\n"); @@ -789,7 +833,8 @@ for(std::vector >::iterator CurrentSet = partialOrder.begin(), E= partialOrder.end(); CurrentSet != E; ++CurrentSet) { DEBUG(std::cerr << "Processing set in S\n"); - dumpIntersection(*CurrentSet); + DEBUG(dumpIntersection(*CurrentSet)); + //Result of intersection std::vector IntersectCurrent; @@ -989,7 +1034,7 @@ bool success = false; while(!success) { - + //Loop over the final node order and process each node for(std::vector::iterator I = FinalNodeOrder.begin(), E = FinalNodeOrder.end(); I != E; ++I) { @@ -1013,7 +1058,7 @@ if(!ignoreEdge(*schedNode, *I)) { int diff = (*I)->getInEdge(*schedNode).getIteDiff(); int ES_Temp = nodesByCycle->first + (*schedNode)->getLatency() - diff * II; - DEBUG(std::cerr << "Diff: " << diff << " Cycle: " << nodesByCycle->first << "\n"); + DEBUG(std::cerr << "Diff: " << diff << " Cycle: " << nodesByCycle->first << "\n"); DEBUG(std::cerr << "Temp EarlyStart: " << ES_Temp << " Prev EarlyStart: " << EarlyStart << "\n"); EarlyStart = std::max(EarlyStart, ES_Temp); hasPred = true; @@ -1124,76 +1169,85 @@ return success; } -/*void ModuloSchedulingPass::saveValue(const MachineInstr *inst, std::set &valuestoSave, std::vector *valuesForNode) { - int numFound = 0; - Instruction *tmp; - - //For each value* in this inst that is a def, we want to save a copy - //Target info - const TargetInstrInfo & mii = target.getInstrInfo(); - for(unsigned i=0; i < inst->getNumOperands(); ++i) { - //get machine operand - const MachineOperand &mOp = inst->getOperand(i); - if(mOp.getType() == MachineOperand::MO_VirtualRegister && mOp.isDef()) { - //Save copy in tmpInstruction - numFound++; - tmp = TmpInstruction(mii.getMachineCodeFor(mOp.getVRegValue()), - mOp.getVRegValue()); - valuesForNode->push_back(tmp); - } - } - - assert(numFound == 1 && "We should have only found one def to this virtual register!"); -}*/ +void ModuloSchedulingPass::writePrologues(std::vector &prologues, MachineBasicBlock *origBB, std::vector &llvm_prologues, std::map > &valuesToSave, std::map > > &newValues, std::map &newValLocation) { -void ModuloSchedulingPass::writePrologues(std::vector &prologues, const MachineBasicBlock *origBB, std::vector &llvm_prologues) { - + //Keep a map to easily know whats in the kernel std::map > inKernel; int maxStageCount = 0; + MSchedGraphNode *branch = 0; + for(MSSchedule::kernel_iterator I = schedule.kernel_begin(), E = schedule.kernel_end(); I != E; ++I) { maxStageCount = std::max(maxStageCount, I->second); //Ignore the branch, we will handle this separately - if(I->first->isBranch()) + if(I->first->isBranch()) { + branch = I->first; continue; + } //Put int the map so we know what instructions in each stage are in the kernel - if(I->second > 0) { - DEBUG(std::cerr << "Inserting instruction " << *(I->first->getInst()) << " into map at stage " << I->second << "\n"); - inKernel[I->second].insert(I->first->getInst()); - } + DEBUG(std::cerr << "Inserting instruction " << *(I->first->getInst()) << " into map at stage " << I->second << "\n"); + inKernel[I->second].insert(I->first->getInst()); } - //Now write the prologues - for(int i = 1; i <= maxStageCount; ++i) { - BasicBlock *llvmBB = new BasicBlock(); + //Get target information to look at machine operands + const TargetInstrInfo *mii = target.getInstrInfo(); + + //Now write the prologues + for(int i = 0; i < maxStageCount; ++i) { + BasicBlock *llvmBB = new BasicBlock("PROLOGUE", (Function*) (origBB->getBasicBlock()->getParent())); MachineBasicBlock *machineBB = new MachineBasicBlock(llvmBB); - //Loop over original machine basic block. If we see an instruction from this - //stage that is NOT in the kernel, then it needs to be added into the prologue - //We go in order to preserve dependencies - for(MachineBasicBlock::const_iterator MI = origBB->begin(), ME = origBB->end(); ME != MI; ++MI) { - if(inKernel[i].count(&*MI)) { - inKernel[i].erase(&*MI); - if(inKernel[i].size() <= 0) - break; - else - continue; - } - else { - DEBUG(std::cerr << "Writing instruction to prologue\n"); - machineBB->push_back(MI->clone()); + DEBUG(std::cerr << "i=" << i << "\n"); + for(int j = 0; j <= i; ++j) { + for(MachineBasicBlock::const_iterator MI = origBB->begin(), ME = origBB->end(); ME != MI; ++MI) { + if(inKernel[j].count(&*MI)) { + machineBB->push_back(MI->clone()); + + Instruction *tmp; + + //After cloning, we may need to save the value that this instruction defines + for(unsigned opNum=0; opNum < MI->getNumOperands(); ++opNum) { + //get machine operand + const MachineOperand &mOp = MI->getOperand(opNum); + if(mOp.getType() == MachineOperand::MO_VirtualRegister && mOp.isDef()) { + + + //Check if this is a value we should save + if(valuesToSave.count(mOp.getVRegValue())) { + //Save copy in tmpInstruction + tmp = new TmpInstruction(mOp.getVRegValue()); + + DEBUG(std::cerr << "Value: " << mOp.getVRegValue() << " New Value: " << tmp << " Stage: " << i << "\n"); + newValues[mOp.getVRegValue()][i].push_back(tmp); + newValLocation[tmp] = machineBB; + + DEBUG(std::cerr << "Machine Instr Operands: " << mOp.getVRegValue() << ", 0, " << tmp << "\n"); + + //Create machine instruction and put int machineBB + MachineInstr *saveValue = BuildMI(machineBB, V9::ORr, 3).addReg(mOp.getVRegValue()).addImm(0).addRegDef(tmp); + + DEBUG(std::cerr << "Created new machine instr: " << *saveValue << "\n"); + } + } + } + } } } - (((MachineBasicBlock*)origBB)->getParent())->getBasicBlockList().push_back(machineBB); + + //Stick in branch at the end + machineBB->push_back(branch->getInst()->clone()); + + (((MachineBasicBlock*)origBB)->getParent())->getBasicBlockList().push_back(machineBB); prologues.push_back(machineBB); llvm_prologues.push_back(llvmBB); } } -void ModuloSchedulingPass::writeEpilogues(std::vector &epilogues, const MachineBasicBlock *origBB, std::vector &llvm_epilogues) { +void ModuloSchedulingPass::writeEpilogues(std::vector &epilogues, const MachineBasicBlock *origBB, std::vector &llvm_epilogues, std::map > &valuesToSave, std::map > > &newValues,std::map &newValLocation ) { + std::map > inKernel; int maxStageCount = 0; for(MSSchedule::kernel_iterator I = schedule.kernel_begin(), E = schedule.kernel_end(); I != E; ++I) { @@ -1204,197 +1258,585 @@ continue; //Put int the map so we know what instructions in each stage are in the kernel - if(I->second > 0) { - DEBUG(std::cerr << "Inserting instruction " << *(I->first->getInst()) << " into map at stage " << I->second << "\n"); - inKernel[I->second].insert(I->first->getInst()); - } + inKernel[I->second].insert(I->first->getInst()); } + std::map valPHIs; + //Now write the epilogues - for(int i = 1; i <= maxStageCount; ++i) { - BasicBlock *llvmBB = new BasicBlock(); + for(int i = maxStageCount-1; i >= 0; --i) { + BasicBlock *llvmBB = new BasicBlock("EPILOGUE", (Function*) (origBB->getBasicBlock()->getParent())); MachineBasicBlock *machineBB = new MachineBasicBlock(llvmBB); - - bool last = false; - for(MachineBasicBlock::const_iterator MI = origBB->begin(), ME = origBB->end(); ME != MI; ++MI) { - - if(!last) { - if(inKernel[i].count(&*MI)) { - machineBB->push_back(MI->clone()); - inKernel[i].erase(&*MI); - if(inKernel[i].size() <= 0) - last = true; - } + + DEBUG(std::cerr << " i: " << i << "\n"); + + //Spit out phi nodes + for(std::map > >::iterator V = newValues.begin(), E = newValues.end(); + V != E; ++V) { + + DEBUG(std::cerr << "Writing phi for" << *(V->first)); + for(std::map >::iterator I = V->second.begin(), IE = V->second.end(); I != IE; ++I) { + if(I->first == i) { + DEBUG(std::cerr << "BLAH " << i << "\n"); + + //Vector must have two elements in it: + assert(I->second.size() == 2 && "Vector size should be two\n"); + + Instruction *tmp = new TmpInstruction(I->second[0]); + MachineInstr *saveValue = BuildMI(machineBB, V9::PHI, 3).addReg(I->second[0]).addReg(I->second[1]).addRegDef(tmp); + valPHIs[V->first] = tmp; + } } - else - machineBB->push_back(MI->clone()); - + } + for(MachineBasicBlock::const_iterator MI = origBB->begin(), ME = origBB->end(); ME != MI; ++MI) { + for(int j=maxStageCount; j > i; --j) { + if(inKernel[j].count(&*MI)) { + DEBUG(std::cerr << "Cloning instruction " << *MI << "\n"); + MachineInstr *clone = MI->clone(); + + //Update operands that need to use the result from the phi + for(unsigned i=0; i < clone->getNumOperands(); ++i) { + //get machine operand + const MachineOperand &mOp = clone->getOperand(i); + if((mOp.getType() == MachineOperand::MO_VirtualRegister && mOp.isUse())) { + if(valPHIs.count(mOp.getVRegValue())) { + //Update the operand in the cloned instruction + clone->getOperand(i).setValueReg(valPHIs[mOp.getVRegValue()]); + } + } + } + machineBB->push_back(clone); + } + } } + (((MachineBasicBlock*)origBB)->getParent())->getBasicBlockList().push_back(machineBB); epilogues.push_back(machineBB); llvm_epilogues.push_back(llvmBB); } - } +void ModuloSchedulingPass::writeKernel(BasicBlock *llvmBB, MachineBasicBlock *machineBB, std::map > &valuesToSave, std::map > > &newValues, std::map &newValLocation) { + + //Keep track of operands that are read and saved from a previous iteration. The new clone + //instruction will use the result of the phi instead. + std::map finalPHIValue; + std::map kernelValue; + + //Create TmpInstructions for the final phis + for(MSSchedule::kernel_iterator I = schedule.kernel_begin(), E = schedule.kernel_end(); I != E; ++I) { + + //Clone instruction + const MachineInstr *inst = I->first->getInst(); + MachineInstr *instClone = inst->clone(); + + //If this instruction is from a previous iteration, update its operands + if(I->second > 0) { + //Loop over Machine Operands + const MachineInstr *inst = I->first->getInst(); + for(unsigned i=0; i < inst->getNumOperands(); ++i) { + //get machine operand + const MachineOperand &mOp = inst->getOperand(i); + + if(mOp.getType() == MachineOperand::MO_VirtualRegister && mOp.isUse()) { + //If its in the value saved, we need to create a temp instruction and use that instead + if(valuesToSave.count(mOp.getVRegValue())) { + TmpInstruction *tmp = new TmpInstruction(mOp.getVRegValue()); + + //Update the operand in the cloned instruction + instClone->getOperand(i).setValueReg(tmp); + + //save this as our final phi + finalPHIValue[mOp.getVRegValue()] = tmp; + newValLocation[tmp] = machineBB; + } + } + } + //Insert into machine basic block + machineBB->push_back(instClone); -void ModuloSchedulingPass::reconstructLoop(const MachineBasicBlock *BB) { - - //The new loop will consist of an prologue, the kernel, and one or more epilogues. + } + //Otherwise we just check if we need to save a value or not + else { + //Insert into machine basic block + machineBB->push_back(instClone); + + //Loop over Machine Operands + const MachineInstr *inst = I->first->getInst(); + for(unsigned i=0; i < inst->getNumOperands(); ++i) { + //get machine operand + const MachineOperand &mOp = inst->getOperand(i); + + if(mOp.getType() == MachineOperand::MO_VirtualRegister && mOp.isDef()) { + if(valuesToSave.count(mOp.getVRegValue())) { + + TmpInstruction *tmp = new TmpInstruction(mOp.getVRegValue()); + + //Create new machine instr and put in MBB + MachineInstr *saveValue = BuildMI(machineBB, V9::ORr, 3).addReg(mOp.getVRegValue()).addImm(0).addRegDef(tmp); + + //Save for future cleanup + kernelValue[mOp.getVRegValue()] = tmp; + newValLocation[tmp] = machineBB; + } + } + } + } + } - std::vector prologues; - std::vector llvm_prologues; + //Clean up by writing phis + for(std::map > >::iterator V = newValues.begin(), E = newValues.end(); + V != E; ++V) { - //Write prologue - writePrologues(prologues, BB, llvm_prologues); + DEBUG(std::cerr << "Writing phi for" << *(V->first)); + + //FIXME + int maxStage = 1; - //Print out prologue - for(std::vector::iterator I = prologues.begin(), E = prologues.end(); - I != E; ++I) { - std::cerr << "PROLOGUE\n"; - (*I)->print(std::cerr); - } + //Last phi + Instruction *lastPHI = 0; + for(std::map >::iterator I = V->second.begin(), IE = V->second.end(); + I != IE; ++I) { + + int stage = I->first; - std::vector epilogues; - std::vector llvm_epilogues; + DEBUG(std::cerr << "Stage: " << I->first << " vector size: " << I->second.size() << "\n"); - //Write epilogues - writeEpilogues(epilogues, BB, llvm_epilogues); + //Assert if this vector is ever greater then 1. This should not happen + //FIXME: Get rid of vector if we convince ourselves this won't happn + assert(I->second.size() == 1 && "Vector of values should be of size \n"); + + //We must handle the first and last phi specially + if(stage == maxStage) { + //The resulting value must be the Value* we created earlier + assert(lastPHI != 0 && "Last phi is NULL!\n"); + MachineInstr *saveValue = BuildMI(*machineBB, machineBB->begin(), V9::PHI, 3).addReg(lastPHI).addReg(I->second[0]).addRegDef(finalPHIValue[V->first]); + I->second.push_back(finalPHIValue[V->first]); + } + else if(stage == 0) { + lastPHI = new TmpInstruction(I->second[0]); + MachineInstr *saveValue = BuildMI(*machineBB, machineBB->begin(), V9::PHI, 3).addReg(kernelValue[V->first]).addReg(I->second[0]).addRegDef(lastPHI); + I->second.push_back(lastPHI); + newValLocation[lastPHI] = machineBB; + } + else { + Instruction *tmp = new TmpInstruction(I->second[0]); + MachineInstr *saveValue = BuildMI(*machineBB, machineBB->begin(), V9::PHI, 3).addReg(lastPHI).addReg(I->second[0]).addRegDef(tmp); + lastPHI = tmp; + I->second.push_back(lastPHI); + newValLocation[tmp] = machineBB; + } + } + } +} - //Print out prologue - for(std::vector::iterator I = epilogues.begin(), E = epilogues.end(); - I != E; ++I) { - std::cerr << "EPILOGUE\n"; - (*I)->print(std::cerr); - } +void ModuloSchedulingPass::removePHIs(const MachineBasicBlock *origBB, std::vector &prologues, std::vector &epilogues, MachineBasicBlock *kernelBB, std::map &newValLocation) { - //create a vector of epilogues corresponding to each stage - /*std::vector epilogues; + //Worklist to delete things + std::vector > worklist; + + const TargetInstrInfo *TMI = target.getInstrInfo(); + + //Start with the kernel and for each phi insert a copy for the phi def and for each arg + for(MachineBasicBlock::iterator I = kernelBB->begin(), E = kernelBB->end(); I != E; ++I) { + //Get op code and check if its a phi + MachineOpCode OC = I->getOpcode(); + if(TMI->isDummyPhiInstr(OC)) { + Instruction *tmp = 0; + for(unsigned i = 0; i < I->getNumOperands(); ++i) { + //Get Operand + const MachineOperand &mOp = I->getOperand(i); + assert(mOp.getType() == MachineOperand::MO_VirtualRegister && "Should be a Value*\n"); + + if(!tmp) { + tmp = new TmpInstruction(mOp.getVRegValue()); + } + + //Now for all our arguments we read, OR to the new TmpInstruction that we created + if(mOp.isUse()) { + DEBUG(std::cerr << "Use: " << mOp << "\n"); + //Place a copy at the end of its BB but before the branches + assert(newValLocation.count(mOp.getVRegValue()) && "We must know where this value is located\n"); + //Reverse iterate to find the branches, we can safely assume no instructions have been + //put in the nop positions + for(MachineBasicBlock::iterator inst = --(newValLocation[mOp.getVRegValue()])->end(), endBB = (newValLocation[mOp.getVRegValue()])->begin(); inst != endBB; --inst) { + MachineOpCode opc = inst->getOpcode(); + if(TMI->isBranch(opc) || TMI->isNop(opc)) + continue; + else { + BuildMI(*(newValLocation[mOp.getVRegValue()]), ++inst, V9::ORr, 3).addReg(mOp.getVRegValue()).addImm(0).addRegDef(tmp); + break; + } + + } - //Create kernel - MachineBasicBlock *kernel = new MachineBasicBlock(); + } + else { + //Remove the phi and replace it with an OR + DEBUG(std::cerr << "Def: " << mOp << "\n"); + BuildMI(*kernelBB, I, V9::ORr, 3).addReg(tmp).addImm(0).addRegDef(mOp.getVRegValue()); + worklist.push_back(std::make_pair(kernelBB, I)); + } - //keep track of stage count - int stageCount = 0; - - //Target info - const TargetInstrInfo & mii = target.getInstrInfo(); + } + } + + } - //Map for creating MachinePhis - std::map > nodeAndValueMap; - + //Remove phis from epilogue + for(std::vector::iterator MB = epilogues.begin(), ME = epilogues.end(); MB != ME; ++MB) { + for(MachineBasicBlock::iterator I = (*MB)->begin(), E = (*MB)->end(); I != E; ++I) { + //Get op code and check if its a phi + MachineOpCode OC = I->getOpcode(); + if(TMI->isDummyPhiInstr(OC)) { + Instruction *tmp = 0; + for(unsigned i = 0; i < I->getNumOperands(); ++i) { + //Get Operand + const MachineOperand &mOp = I->getOperand(i); + assert(mOp.getType() == MachineOperand::MO_VirtualRegister && "Should be a Value*\n"); + + if(!tmp) { + tmp = new TmpInstruction(mOp.getVRegValue()); + } + + //Now for all our arguments we read, OR to the new TmpInstruction that we created + if(mOp.isUse()) { + DEBUG(std::cerr << "Use: " << mOp << "\n"); + //Place a copy at the end of its BB but before the branches + assert(newValLocation.count(mOp.getVRegValue()) && "We must know where this value is located\n"); + //Reverse iterate to find the branches, we can safely assume no instructions have been + //put in the nop positions + for(MachineBasicBlock::iterator inst = --(newValLocation[mOp.getVRegValue()])->end(), endBB = (newValLocation[mOp.getVRegValue()])->begin(); inst != endBB; --inst) { + MachineOpCode opc = inst->getOpcode(); + if(TMI->isBranch(opc) || TMI->isNop(opc)) + continue; + else { + BuildMI(*(newValLocation[mOp.getVRegValue()]), ++inst, V9::ORr, 3).addReg(mOp.getVRegValue()).addImm(0).addRegDef(tmp); + break; + } + + } + + } + else { + //Remove the phi and replace it with an OR + DEBUG(std::cerr << "Def: " << mOp << "\n"); + BuildMI(**MB, I, V9::ORr, 3).addReg(tmp).addImm(0).addRegDef(mOp.getVRegValue()); + worklist.push_back(std::make_pair(*MB,I)); + } + + } + } + } + } - //Loop through the kernel and clone instructions that need to be put into the prologue - for(MSSchedule::kernel_iterator I = schedule.kernel_begin(), E = schedule.kernel_end(); I != E; ++I) { - //For each pair see if the stage is greater then 0 - //if so, then ALL instructions before this in the original loop, need to be - //copied into the prologue - MachineBasicBlock::const_iterator actualInst; + //Delete the phis + for(std::vector >::iterator I = worklist.begin(), E = worklist.end(); I != E; ++I) { + I->first->erase(I->second); + + } +} - //ignore branch - if(I->first->isBranch()) - continue; - if(I->second > 0) { +void ModuloSchedulingPass::reconstructLoop(MachineBasicBlock *BB) { - assert(I->second >= stageCount && "Visiting instruction from previous stage count.\n"); + //First find the value *'s that we need to "save" + std::map > valuesToSave; - - //Make a set that has all the Value*'s that we read - std::set valuesToSave; + //Loop over kernel and only look at instructions from a stage > 0 + //Look at its operands and save values *'s that are read + for(MSSchedule::kernel_iterator I = schedule.kernel_begin(), E = schedule.kernel_end(); I != E; ++I) { + if(I->second > 0) { //For this instruction, get the Value*'s that it reads and put them into the set. //Assert if there is an operand of another type that we need to save const MachineInstr *inst = I->first->getInst(); for(unsigned i=0; i < inst->getNumOperands(); ++i) { //get machine operand const MachineOperand &mOp = inst->getOperand(i); - + if(mOp.getType() == MachineOperand::MO_VirtualRegister && mOp.isUse()) { //find the value in the map if (const Value* srcI = mOp.getVRegValue()) - valuesToSave.insert(srcI); + valuesToSave[srcI] = std::make_pair(I->first, i); + } if(mOp.getType() != MachineOperand::MO_VirtualRegister && mOp.isUse()) { assert("Our assumption is wrong. We have another type of register that needs to be saved\n"); } } + } + } - //Check if we skipped a stage count, we need to add that stuff here - if(I->second - stageCount > 1) { - int temp = stageCount; - while(I->second - temp > 1) { - for(MachineBasicBlock::const_iterator MI = BB->begin(), ME = BB->end(); ME != MI; ++MI) { - //Check that MI is not a branch before adding, we add branches separately - if(!mii.isBranch(MI->getOpcode()) && !mii.isNop(MI->getOpcode())) { - prologue->push_back(MI->clone()); - saveValue(&*MI, valuesToSave); - } - } - ++temp; - } + //The new loop will consist of one or more prologues, the kernel, and one or more epilogues. + + //Map to keep track of old to new values + std::map > > newValues; + + //Another map to keep track of what machine basic blocks these new value*s are in since + //they have no llvm instruction equivalent + std::map newValLocation; + + std::vector prologues; + std::vector llvm_prologues; + + + //Write prologue + writePrologues(prologues, BB, llvm_prologues, valuesToSave, newValues, newValLocation); + + BasicBlock *llvmKernelBB = new BasicBlock("Kernel", (Function*) (BB->getBasicBlock()->getParent())); + MachineBasicBlock *machineKernelBB = new MachineBasicBlock(llvmKernelBB); + + writeKernel(llvmKernelBB, machineKernelBB, valuesToSave, newValues, newValLocation); + (((MachineBasicBlock*)BB)->getParent())->getBasicBlockList().push_back(machineKernelBB); + + std::vector epilogues; + std::vector llvm_epilogues; + + //Write epilogues + writeEpilogues(epilogues, BB, llvm_epilogues, valuesToSave, newValues, newValLocation); + + + const TargetInstrInfo *TMI = target.getInstrInfo(); + + //Fix up machineBB and llvmBB branches + for(unsigned I = 0; I < prologues.size(); ++I) { + + MachineInstr *branch = 0; + + //Find terminator since getFirstTerminator does not work! + for(MachineBasicBlock::reverse_iterator mInst = prologues[I]->rbegin(), mInstEnd = prologues[I]->rend(); mInst != mInstEnd; ++mInst) { + MachineOpCode OC = mInst->getOpcode(); + if(TMI->isBranch(OC)) { + branch = &*mInst; + DEBUG(std::cerr << *mInst << "\n"); + break; } + } - if(I->second == stageCount) - continue; + + + //Update branch + for(unsigned opNum = 0; opNum < branch->getNumOperands(); ++opNum) { + MachineOperand &mOp = branch->getOperand(opNum); + if (mOp.getType() == MachineOperand::MO_PCRelativeDisp) { + mOp.setValueReg(llvm_epilogues[(llvm_epilogues.size()-1-I)]); + } + } + + //Update llvm basic block with our new branch instr + DEBUG(std::cerr << BB->getBasicBlock()->getTerminator() << "\n"); + const BranchInst *branchVal = dyn_cast(BB->getBasicBlock()->getTerminator()); + TmpInstruction *tmp = new TmpInstruction(branchVal->getCondition()); + if(I == prologues.size()-1) { + TerminatorInst *newBranch = new BranchInst(llvmKernelBB, + llvm_epilogues[(llvm_epilogues.size()-1-I)], + tmp, + llvm_prologues[I]); + } + else + TerminatorInst *newBranch = new BranchInst(llvm_prologues[I+1], + llvm_epilogues[(llvm_epilogues.size()-1-I)], + tmp, + llvm_prologues[I]); + + assert(branch != 0 && "There must be a terminator for this machine basic block!\n"); + + //Push nop onto end of machine basic block + BuildMI(prologues[I], V9::NOP, 0); + + //Now since I don't trust fall throughs, add a unconditional branch to the next prologue + if(I != prologues.size()-1) + BuildMI(prologues[I], V9::BA, 1).addReg(llvm_prologues[I+1]); + else + BuildMI(prologues[I], V9::BA, 1).addReg(llvmKernelBB); + + //Add one more nop! + BuildMI(prologues[I], V9::NOP, 0); + } + + //Fix up kernel machine branches + MachineInstr *branch = 0; + for(MachineBasicBlock::reverse_iterator mInst = machineKernelBB->rbegin(), mInstEnd = machineKernelBB->rend(); mInst != mInstEnd; ++mInst) { + MachineOpCode OC = mInst->getOpcode(); + if(TMI->isBranch(OC)) { + branch = &*mInst; + DEBUG(std::cerr << *mInst << "\n"); + break; + } + } + + assert(branch != 0 && "There must be a terminator for the kernel machine basic block!\n"); + + //Update kernel self loop branch + for(unsigned opNum = 0; opNum < branch->getNumOperands(); ++opNum) { + MachineOperand &mOp = branch->getOperand(opNum); + + if (mOp.getType() == MachineOperand::MO_PCRelativeDisp) { + mOp.setValueReg(llvmKernelBB); + } + } + + //Update kernelLLVM branches + const BranchInst *branchVal = dyn_cast(BB->getBasicBlock()->getTerminator()); + TerminatorInst *newBranch = new BranchInst(llvmKernelBB, + llvm_epilogues[0], + new TmpInstruction(branchVal->getCondition()), + llvmKernelBB); + + //Add kernel noop + BuildMI(machineKernelBB, V9::NOP, 0); + + //Add unconditional branch to first epilogue + BuildMI(machineKernelBB, V9::BA, 1).addReg(llvm_epilogues[0]); - stageCount = I->second; - DEBUG(std::cerr << "Found Instruction from Stage > 0\n"); - //Loop over instructions in original basic block and clone them. Add to the prologue - for (MachineBasicBlock::const_iterator MI = BB->begin(), e = BB->end(); MI != e; ++MI) { - if(&*MI == I->first->getInst()) { - actualInst = MI; + //Add kernel noop + BuildMI(machineKernelBB, V9::NOP, 0); + + //Lastly add unconditional branches for the epilogues + for(unsigned I = 0; I < epilogues.size(); ++I) { + + //Now since I don't trust fall throughs, add a unconditional branch to the next prologue + if(I != epilogues.size()-1) { + BuildMI(epilogues[I], V9::BA, 1).addReg(llvm_epilogues[I+1]); + //Add unconditional branch to end of epilogue + TerminatorInst *newBranch = new BranchInst(llvm_epilogues[I+1], + llvm_epilogues[I]); + + } + else { + MachineBasicBlock *origBlock = (MachineBasicBlock*) BB; + for(MachineBasicBlock::reverse_iterator inst = origBlock->rbegin(), instEnd = origBlock->rend(); inst != instEnd; ++inst) { + MachineOpCode OC = inst->getOpcode(); + if(TMI->isBranch(OC)) { + branch = &*inst; + DEBUG(std::cerr << *inst << "\n"); break; + } - else { - //Check that MI is not a branch before adding, we add branches separately - if(!mii.isBranch(MI->getOpcode()) && !mii.isNop(MI->getOpcode())) - prologue->push_back(MI->clone()); + + for(unsigned opNum = 0; opNum < branch->getNumOperands(); ++opNum) { + MachineOperand &mOp = branch->getOperand(opNum); + + if (mOp.getType() == MachineOperand::MO_PCRelativeDisp) { + BuildMI(epilogues[I], V9::BA, 1).addReg(mOp.getVRegValue()); + break; + } } + } - //Now add in all instructions from this one on to its corresponding epilogue - MachineBasicBlock *epi = new MachineBasicBlock(); - epilogues.push_back(epi); - - for(MachineBasicBlock::const_iterator MI = actualInst, ME = BB->end(); ME != MI; ++MI) { - //Check that MI is not a branch before adding, we add branches separately - if(!mii.isBranch(MI->getOpcode()) && !mii.isNop(MI->getOpcode())) - epi->push_back(MI->clone()); - } + //Update last epilogue exit branch + BranchInst *branchVal = (BranchInst*) dyn_cast(BB->getBasicBlock()->getTerminator()); + //Find where we are supposed to branch to + BasicBlock *nextBlock; + for(unsigned j=0; j getNumSuccessors(); ++j) { + if(branchVal->getSuccessor(j) != BB->getBasicBlock()) + nextBlock = branchVal->getSuccessor(j); + } + TerminatorInst *newBranch = new BranchInst(nextBlock, llvm_epilogues[I]); } - } + //Add one more nop! + BuildMI(epilogues[I], V9::NOP, 0); - //Create kernel - for(MSSchedule::kernel_iterator I = schedule.kernel_begin(), - E = schedule.kernel_end(); I != E; ++I) { - kernel->push_back(I->first->getInst()->clone()); - + } + + //FIX UP Machine BB entry!! + //We are looking at the predecesor of our loop basic block and we want to change its ba instruction + + + //Find all llvm basic blocks that branch to the loop entry and change to our first prologue. + const BasicBlock *llvmBB = BB->getBasicBlock(); + + for(pred_const_iterator P = pred_begin(llvmBB), PE = pred_end(llvmBB); P != PE; ++PE) { + if(*P == llvmBB) + continue; + else { + DEBUG(std::cerr << "Found our entry BB\n"); + //Get the Terminator instruction for this basic block and print it out + DEBUG(std::cerr << *((*P)->getTerminator()) << "\n"); + //Update the terminator + TerminatorInst *term = ((BasicBlock*)*P)->getTerminator(); + for(unsigned i=0; i < term->getNumSuccessors(); ++i) { + if(term->getSuccessor(i) == llvmBB) { + DEBUG(std::cerr << "Replacing successor bb\n"); + if(llvm_prologues.size() > 0) { + term->setSuccessor(i, llvm_prologues[0]); + //Also update its corresponding machine instruction + MachineCodeForInstruction & tempMvec = + MachineCodeForInstruction::get(term); + for (unsigned j = 0; j < tempMvec.size(); j++) { + MachineInstr *temp = tempMvec[j]; + MachineOpCode opc = temp->getOpcode(); + if(TMI->isBranch(opc)) { + DEBUG(std::cerr << *temp << "\n"); + //Update branch + for(unsigned opNum = 0; opNum < temp->getNumOperands(); ++opNum) { + MachineOperand &mOp = temp->getOperand(opNum); + if (mOp.getType() == MachineOperand::MO_PCRelativeDisp) { + mOp.setValueReg(llvm_prologues[0]); + } + } + } + } + } + else { + term->setSuccessor(i, llvmKernelBB); + //Also update its corresponding machine instruction + MachineCodeForInstruction & tempMvec = + MachineCodeForInstruction::get(term); + for (unsigned j = 0; j < tempMvec.size(); j++) { + MachineInstr *temp = tempMvec[j]; + MachineOpCode opc = temp->getOpcode(); + if(TMI->isBranch(opc)) { + DEBUG(std::cerr << *temp << "\n"); + //Update branch + for(unsigned opNum = 0; opNum < temp->getNumOperands(); ++opNum) { + MachineOperand &mOp = temp->getOperand(opNum); + if (mOp.getType() == MachineOperand::MO_PCRelativeDisp) { + mOp.setValueReg(llvmKernelBB); + } + } + } + } + } + } + } + break; } + } + + removePHIs(BB, prologues, epilogues, machineKernelBB, newValLocation); + + + + //Print out epilogues and prologue + DEBUG(for(std::vector::iterator I = prologues.begin(), E = prologues.end(); + I != E; ++I) { + std::cerr << "PROLOGUE\n"; + (*I)->print(std::cerr); + }); + + DEBUG(std::cerr << "KERNEL\n"); + DEBUG(machineKernelBB->print(std::cerr)); + + DEBUG(for(std::vector::iterator I = epilogues.begin(), E = epilogues.end(); + I != E; ++I) { + std::cerr << "EPILOGUE\n"; + (*I)->print(std::cerr); + }); - //Debug stuff - ((MachineBasicBlock*)BB)->getParent()->getBasicBlockList().push_back(prologue); - std::cerr << "PROLOGUE:\n"; - prologue->print(std::cerr); - - ((MachineBasicBlock*)BB)->getParent()->getBasicBlockList().push_back(kernel); - std::cerr << "KERNEL: \n"; - kernel->print(std::cerr); - - for(std::vector::iterator MBB = epilogues.begin(), ME = epilogues.end(); - MBB != ME; ++MBB) { - std::cerr << "EPILOGUE:\n"; - ((MachineBasicBlock*)BB)->getParent()->getBasicBlockList().push_back(*MBB); - (*MBB)->print(std::cerr); - }*/ + DEBUG(std::cerr << "New Machine Function" << "\n"); + DEBUG(std::cerr << BB->getParent() << "\n"); + BB->getParent()->getBasicBlockList().erase(BB); } Index: llvm/lib/CodeGen/ModuloScheduling/ModuloScheduling.h diff -u llvm/lib/CodeGen/ModuloScheduling/ModuloScheduling.h:1.14 llvm/lib/CodeGen/ModuloScheduling/ModuloScheduling.h:1.15 --- llvm/lib/CodeGen/ModuloScheduling/ModuloScheduling.h:1.14 Fri May 28 15:14:12 2004 +++ llvm/lib/CodeGen/ModuloScheduling/ModuloScheduling.h Fri Jul 30 18:36:10 2004 @@ -89,13 +89,18 @@ void predIntersect(std::vector &CurrentSet, std::vector &IntersectResult); void succIntersect(std::vector &CurrentSet, std::vector &IntersectResult); - void reconstructLoop(const MachineBasicBlock*); + void reconstructLoop(MachineBasicBlock*); //void saveValue(const MachineInstr*, const std::set&, std::vector*); - void writePrologues(std::vector &prologues, const MachineBasicBlock *origBB, std::vector &llvm_prologues); + void writePrologues(std::vector &prologues, MachineBasicBlock *origBB, std::vector &llvm_prologues, std::map > &valuesToSave, std::map > > &newValues, std::map &newValLocation); - void writeEpilogues(std::vector &epilogues, const MachineBasicBlock *origBB, std::vector &llvm_epilogues); + void writeEpilogues(std::vector &epilogues, const MachineBasicBlock *origBB, std::vector &llvm_epilogues, std::map > &valuesToSave,std::map > > &newValues, std::map &newValLocation); + + + void writeKernel(BasicBlock *llvmBB, MachineBasicBlock *machineBB, std::map > &valuesToSave, std::map > > &newValues, std::map &newValLocation); + + void removePHIs(const MachineBasicBlock *origBB, std::vector &prologues, std::vector &epilogues, MachineBasicBlock *kernelBB, std::map &newValLocation); public: ModuloSchedulingPass(TargetMachine &targ) : target(targ) {} From lattner at cs.uiuc.edu Fri Jul 30 20:59:26 2004 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Fri, 30 Jul 2004 20:59:26 -0500 Subject: [llvm-commits] CVS: llvm/include/llvm/CodeGen/MachineBasicBlock.h MachineInstr.h Message-ID: <200407310159.UAA30107@apoc.cs.uiuc.edu> Changes in directory llvm/include/llvm/CodeGen: MachineBasicBlock.h updated: 1.35 -> 1.36 MachineInstr.h updated: 1.152 -> 1.153 --- Log message: Add some machine CFG related stuff --- Diffs of the changes: (+25 -9) Index: llvm/include/llvm/CodeGen/MachineBasicBlock.h diff -u llvm/include/llvm/CodeGen/MachineBasicBlock.h:1.35 llvm/include/llvm/CodeGen/MachineBasicBlock.h:1.36 --- llvm/include/llvm/CodeGen/MachineBasicBlock.h:1.35 Tue Jun 8 13:52:47 2004 +++ llvm/include/llvm/CodeGen/MachineBasicBlock.h Fri Jul 30 20:59:11 2004 @@ -115,30 +115,42 @@ pred_iterator pred_end() { return Predecessors.end (); } const_pred_iterator pred_end() const { return Predecessors.end (); } unsigned pred_size() const { return Predecessors.size (); } + bool pred_empty() const { return Predecessors.empty(); } succ_iterator succ_begin() { return Successors.begin (); } const_succ_iterator succ_begin() const { return Successors.begin (); } succ_iterator succ_end() { return Successors.end (); } const_succ_iterator succ_end() const { return Successors.end (); } unsigned succ_size() const { return Successors.size (); } + bool succ_empty() const { return Successors.empty(); } // Machine-CFG mutators /// addSuccessor - Add succ as a successor of this MachineBasicBlock. /// The Predecessors list of succ is automatically updated. /// - void addSuccessor (MachineBasicBlock *succ) { - Successors.push_back (succ); - succ->addPredecessor (this); + void addSuccessor(MachineBasicBlock *succ) { + Successors.push_back(succ); + succ->addPredecessor(this); } - /// removeSuccessor - Remove succ from the successors list of this + /// removeSuccessor - Remove successor from the successors list of this /// MachineBasicBlock. The Predecessors list of succ is automatically updated. /// - void removeSuccessor (MachineBasicBlock *succ) { - succ->removePredecessor (this); - std::vector::iterator goner = - std::find (Successors.begin(), Successors.end (), succ); - Successors.erase (goner); + void removeSuccessor(MachineBasicBlock *succ) { + succ->removePredecessor(this); + succ_iterator I = std::find(Successors.begin(), Successors.end(), succ); + assert(I != Successors.end() && "Not a current successor!"); + Successors.erase(I); + } + + /// removeSuccessor - Remove specified successor from the successors list of + /// this MachineBasicBlock. The Predecessors list of succ is automatically + /// updated. + /// + void removeSuccessor(succ_iterator I) { + assert(I != Successors.end() && "Not a current successor!"); + (*I)->removePredecessor(this); + Successors.erase(I); } /// getFirstTerminator - returns an iterator to the first terminator Index: llvm/include/llvm/CodeGen/MachineInstr.h diff -u llvm/include/llvm/CodeGen/MachineInstr.h:1.152 llvm/include/llvm/CodeGen/MachineInstr.h:1.153 --- llvm/include/llvm/CodeGen/MachineInstr.h:1.152 Mon Jul 19 08:28:39 2004 +++ llvm/include/llvm/CodeGen/MachineInstr.h Fri Jul 30 20:59:11 2004 @@ -255,6 +255,10 @@ assert(isMachineBasicBlock() && "Wrong MachineOperand accessor"); return contents.MBB; } + void setMachineBasicBlock(MachineBasicBlock *MBB) { + assert(isMachineBasicBlock() && "Wrong MachineOperand accessor"); + contents.MBB = MBB; + } int getFrameIndex() const { assert(isFrameIndex() && "Wrong MachineOperand accessor"); return contents.immedVal; From lattner at cs.uiuc.edu Fri Jul 30 21:06:58 2004 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Fri, 30 Jul 2004 21:06:58 -0500 Subject: [llvm-commits] CVS: llvm/include/llvm/Target/TargetInstrInfo.h Message-ID: <200407310206.VAA02855@apoc.cs.uiuc.edu> Changes in directory llvm/include/llvm/Target: TargetInstrInfo.h updated: 1.60 -> 1.61 --- Log message: Add new M_BARRIER_FLAG flag, and isBarrier() method to TargetInstrInfo opCode -> Opcode --- Diffs of the changes: (+54 -47) Index: llvm/include/llvm/Target/TargetInstrInfo.h diff -u llvm/include/llvm/Target/TargetInstrInfo.h:1.60 llvm/include/llvm/Target/TargetInstrInfo.h:1.61 --- llvm/include/llvm/Target/TargetInstrInfo.h:1.60 Wed Jul 28 14:24:48 2004 +++ llvm/include/llvm/Target/TargetInstrInfo.h Fri Jul 30 21:06:48 2004 @@ -46,6 +46,7 @@ const unsigned M_BRANCH_FLAG = 1 << 1; const unsigned M_CALL_FLAG = 1 << 2; const unsigned M_RET_FLAG = 1 << 3; +const unsigned M_BARRIER_FLAG = 1 << 4; const unsigned M_CC_FLAG = 1 << 6; const unsigned M_LOAD_FLAG = 1 << 10; const unsigned M_STORE_FLAG = 1 << 12; @@ -100,30 +101,30 @@ /// get - Return the machine instruction descriptor that corresponds to the /// specified instruction opcode. /// - const TargetInstrDescriptor& get(MachineOpCode opCode) const { - assert((unsigned)opCode < NumOpcodes); - return desc[opCode]; + const TargetInstrDescriptor& get(MachineOpCode Opcode) const { + assert((unsigned)Opcode < NumOpcodes); + return desc[Opcode]; } - const char *getName(MachineOpCode opCode) const { - return get(opCode).Name; + const char *getName(MachineOpCode Opcode) const { + return get(Opcode).Name; } - int getNumOperands(MachineOpCode opCode) const { - return get(opCode).numOperands; + int getNumOperands(MachineOpCode Opcode) const { + return get(Opcode).numOperands; } - InstrSchedClass getSchedClass(MachineOpCode opCode) const { - return get(opCode).schedClass; + InstrSchedClass getSchedClass(MachineOpCode Opcode) const { + return get(Opcode).schedClass; } - const unsigned *getImplicitUses(MachineOpCode opCode) const { - return get(opCode).ImplicitUses; + const unsigned *getImplicitUses(MachineOpCode Opcode) const { + return get(Opcode).ImplicitUses; } - const unsigned *getImplicitDefs(MachineOpCode opCode) const { - return get(opCode).ImplicitDefs; + const unsigned *getImplicitDefs(MachineOpCode Opcode) const { + return get(Opcode).ImplicitDefs; } @@ -131,15 +132,15 @@ // Query instruction class flags according to the machine-independent // flags listed above. // - bool isReturn(MachineOpCode opCode) const { - return get(opCode).Flags & M_RET_FLAG; + bool isReturn(MachineOpCode Opcode) const { + return get(Opcode).Flags & M_RET_FLAG; } - bool isPseudoInstr(MachineOpCode opCode) const { - return get(opCode).Flags & M_PSEUDO_FLAG; + bool isPseudoInstr(MachineOpCode Opcode) const { + return get(Opcode).Flags & M_PSEUDO_FLAG; } - bool isTwoAddrInstr(MachineOpCode opCode) const { - return get(opCode).Flags & M_2_ADDR_FLAG; + bool isTwoAddrInstr(MachineOpCode Opcode) const { + return get(Opcode).Flags & M_2_ADDR_FLAG; } bool isTerminatorInstr(unsigned Opcode) const { return get(Opcode).Flags & M_TERMINATOR_FLAG; @@ -167,60 +168,66 @@ // //------------------------------------------------------------------------- - int getResultPos(MachineOpCode opCode) const { - return get(opCode).resultPos; + int getResultPos(MachineOpCode Opcode) const { + return get(Opcode).resultPos; } - unsigned getNumDelaySlots(MachineOpCode opCode) const { - return get(opCode).numDelaySlots; + unsigned getNumDelaySlots(MachineOpCode Opcode) const { + return get(Opcode).numDelaySlots; } - bool isCCInstr(MachineOpCode opCode) const { - return get(opCode).Flags & M_CC_FLAG; + bool isCCInstr(MachineOpCode Opcode) const { + return get(Opcode).Flags & M_CC_FLAG; } - bool isNop(MachineOpCode opCode) const { - return get(opCode).Flags & M_NOP_FLAG; + bool isNop(MachineOpCode Opcode) const { + return get(Opcode).Flags & M_NOP_FLAG; } - bool isBranch(MachineOpCode opCode) const { - return get(opCode).Flags & M_BRANCH_FLAG; + bool isBranch(MachineOpCode Opcode) const { + return get(Opcode).Flags & M_BRANCH_FLAG; } - bool isCall(MachineOpCode opCode) const { - return get(opCode).Flags & M_CALL_FLAG; + /// isBarrier - Returns true if the specified instruction stops control flow + /// from executing the instruction immediately following it. Examples include + /// unconditional branches and return instructions. + bool isBarrier(MachineOpCode Opcode) const { + return get(Opcode).Flags & M_BARRIER_FLAG; } - bool isLoad(MachineOpCode opCode) const { - return get(opCode).Flags & M_LOAD_FLAG; + bool isCall(MachineOpCode Opcode) const { + return get(Opcode).Flags & M_CALL_FLAG; } - bool isStore(MachineOpCode opCode) const { - return get(opCode).Flags & M_STORE_FLAG; + bool isLoad(MachineOpCode Opcode) const { + return get(Opcode).Flags & M_LOAD_FLAG; } - bool isDummyPhiInstr(MachineOpCode opCode) const { - return get(opCode).Flags & M_DUMMY_PHI_FLAG; + bool isStore(MachineOpCode Opcode) const { + return get(Opcode).Flags & M_STORE_FLAG; + } + bool isDummyPhiInstr(MachineOpCode Opcode) const { + return get(Opcode).Flags & M_DUMMY_PHI_FLAG; } - virtual bool hasResultInterlock(MachineOpCode opCode) const { + virtual bool hasResultInterlock(MachineOpCode Opcode) const { return true; } // // Latencies for individual instructions and instruction pairs // - virtual int minLatency(MachineOpCode opCode) const { - return get(opCode).latency; + virtual int minLatency(MachineOpCode Opcode) const { + return get(Opcode).latency; } - virtual int maxLatency(MachineOpCode opCode) const { - return get(opCode).latency; + virtual int maxLatency(MachineOpCode Opcode) const { + return get(Opcode).latency; } // // Which operand holds an immediate constant? Returns -1 if none // - virtual int getImmedConstantPos(MachineOpCode opCode) const { + virtual int getImmedConstantPos(MachineOpCode Opcode) const { return -1; // immediate position is machine specific, so say -1 == "none" } // Check if the specified constant fits in the immediate field // of this machine instruction // - virtual bool constantFitsInImmedField(MachineOpCode opCode, + virtual bool constantFitsInImmedField(MachineOpCode Opcode, int64_t intValue) const; // Return the largest positive constant that can be held in the IMMED field @@ -229,10 +236,10 @@ // (this is true for all immediate fields in SPARC instructions). // Return 0 if the instruction has no IMMED field. // - virtual uint64_t maxImmedConstant(MachineOpCode opCode, + virtual uint64_t maxImmedConstant(MachineOpCode Opcode, bool &isSignExtended) const { - isSignExtended = get(opCode).immedIsSignExtended; - return get(opCode).maxImmedConst; + isSignExtended = get(Opcode).immedIsSignExtended; + return get(Opcode).maxImmedConst; } }; From lattner at cs.uiuc.edu Fri Jul 30 21:07:17 2004 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Fri, 30 Jul 2004 21:07:17 -0500 Subject: [llvm-commits] CVS: llvm/lib/Target/Target.td Message-ID: <200407310207.VAA02868@apoc.cs.uiuc.edu> Changes in directory llvm/lib/Target: Target.td updated: 1.25 -> 1.26 --- Log message: New flag --- Diffs of the changes: (+1 -0) Index: llvm/lib/Target/Target.td diff -u llvm/lib/Target/Target.td:1.25 llvm/lib/Target/Target.td:1.26 --- llvm/lib/Target/Target.td:1.25 Tue Feb 10 21:08:45 2004 +++ llvm/lib/Target/Target.td Fri Jul 30 21:07:07 2004 @@ -117,6 +117,7 @@ // instruction. bit isReturn = 0; // Is this instruction a return instruction? bit isBranch = 0; // Is this instruction a branch instruction? + bit isBarrier = 0; // Can control flow fall through this instruction? bit isCall = 0; // Is this instruction a call instruction? bit isTwoAddress = 0; // Is this a two address instruction? bit isTerminator = 0; // Is this part of the terminator for a basic block? From lattner at cs.uiuc.edu Fri Jul 30 21:07:36 2004 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Fri, 30 Jul 2004 21:07:36 -0500 Subject: [llvm-commits] CVS: llvm/utils/TableGen/InstrInfoEmitter.cpp Message-ID: <200407310207.VAA03386@apoc.cs.uiuc.edu> Changes in directory llvm/utils/TableGen: InstrInfoEmitter.cpp updated: 1.7 -> 1.8 --- Log message: Support new flag --- Diffs of the changes: (+1 -0) Index: llvm/utils/TableGen/InstrInfoEmitter.cpp diff -u llvm/utils/TableGen/InstrInfoEmitter.cpp:1.7 llvm/utils/TableGen/InstrInfoEmitter.cpp:1.8 --- llvm/utils/TableGen/InstrInfoEmitter.cpp:1.7 Tue Nov 11 16:41:34 2003 +++ llvm/utils/TableGen/InstrInfoEmitter.cpp Fri Jul 30 21:07:26 2004 @@ -107,6 +107,7 @@ // Emit all of the target indepedent flags... if (R->getValueAsBit("isReturn")) OS << "|M_RET_FLAG"; if (R->getValueAsBit("isBranch")) OS << "|M_BRANCH_FLAG"; + if (R->getValueAsBit("isBarrier")) OS << "|M_BARRIER_FLAG"; if (R->getValueAsBit("isCall" )) OS << "|M_CALL_FLAG"; if (R->getValueAsBit("isTwoAddress")) OS << "|M_2_ADDR_FLAG"; if (R->getValueAsBit("isTerminator")) OS << "|M_TERMINATOR_FLAG"; From lattner at cs.uiuc.edu Fri Jul 30 21:11:03 2004 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Fri, 30 Jul 2004 21:11:03 -0500 Subject: [llvm-commits] CVS: llvm/lib/Target/X86/X86InstrInfo.td Message-ID: <200407310211.VAA09243@apoc.cs.uiuc.edu> Changes in directory llvm/lib/Target/X86: X86InstrInfo.td updated: 1.80 -> 1.81 --- Log message: Mark barrier instructions. Execution does not fall through uncond branches or return intructions. --- Diffs of the changes: (+4 -2) Index: llvm/lib/Target/X86/X86InstrInfo.td diff -u llvm/lib/Target/X86/X86InstrInfo.td:1.80 llvm/lib/Target/X86/X86InstrInfo.td:1.81 --- llvm/lib/Target/X86/X86InstrInfo.td:1.80 Thu Jun 10 23:50:14 2004 +++ llvm/lib/Target/X86/X86InstrInfo.td Fri Jul 30 21:10:53 2004 @@ -169,19 +169,21 @@ let isTerminator = 1 in let Defs = [FP0, FP1, FP2, FP3, FP4, FP5, FP6] in def FP_REG_KILL : I<"FP_REG_KILL", 0, Pseudo>; + //===----------------------------------------------------------------------===// // Control Flow Instructions... // // Return instruction... -let isTerminator = 1, isReturn = 1 in +let isTerminator = 1, isReturn = 1, isBarrier = 1 in def RET : I<"ret", 0xC3, RawFrm>, Pattern<(retvoid)>; // All branches are RawFrm, Void, Branch, and Terminators let isBranch = 1, isTerminator = 1 in class IBr opcode> : I; -def JMP : IBr<"jmp", 0xE9>, Pattern<(br basicblock)>; +let isBarrier = 1 in + def JMP : IBr<"jmp", 0xE9>, Pattern<(br basicblock)>; def JB : IBr<"jb" , 0x82>, TB; def JAE : IBr<"jae", 0x83>, TB; def JE : IBr<"je" , 0x84>, TB, Pattern<(isVoid (unspec1 basicblock))>; From alkis at cs.uiuc.edu Sat Jul 31 03:52:40 2004 From: alkis at cs.uiuc.edu (Alkis Evlogimenos) Date: Sat, 31 Jul 2004 03:52:40 -0500 Subject: [llvm-commits] CVS: llvm/include/llvm/Target/TargetInstrInfo.h Message-ID: <200407310852.DAA11522@zion.cs.uiuc.edu> Changes in directory llvm/include/llvm/Target: TargetInstrInfo.h updated: 1.61 -> 1.62 --- Log message: Add declarations for insertGoto and reverseBranchCondition. --- Diffs of the changes: (+15 -1) Index: llvm/include/llvm/Target/TargetInstrInfo.h diff -u llvm/include/llvm/Target/TargetInstrInfo.h:1.61 llvm/include/llvm/Target/TargetInstrInfo.h:1.62 --- llvm/include/llvm/Target/TargetInstrInfo.h:1.61 Fri Jul 30 21:06:48 2004 +++ llvm/include/llvm/Target/TargetInstrInfo.h Sat Jul 31 03:52:30 2004 @@ -14,6 +14,7 @@ #ifndef LLVM_TARGET_TARGETINSTRINFO_H #define LLVM_TARGET_TARGETINSTRINFO_H +#include "llvm/CodeGen/MachineBasicBlock.h" #include "Support/DataTypes.h" #include #include @@ -156,8 +157,21 @@ return false; } + // + // Insert a goto (unconditional branch) sequence to MBB, right + // before MBBI + virtual void insertGoto(const MachineBasicBlock& MBB, + const MachineBasicBlock::iterator MBBI) const { + assert(0 && "Target didn't implement insertGoto!"); + } - + // + // Reverses the branch condition of the MachineInstr pointed by + // MI. The instruction is replaced and the new MI is returned. + virtual MachineBasicBlock::iterator + reverseBranchCondition(const MachineBasicBlock::iterator MI) const { + assert(0 && "Target didn't implement reverseBranchCondition!"); + } //------------------------------------------------------------------------- // Code generation support for creating individual machine instructions From alkis at cs.uiuc.edu Sat Jul 31 03:55:34 2004 From: alkis at cs.uiuc.edu (Alkis Evlogimenos) Date: Sat, 31 Jul 2004 03:55:34 -0500 Subject: [llvm-commits] CVS: llvm/include/llvm/Target/TargetInstrInfo.h Message-ID: <200407310855.DAA11580@zion.cs.uiuc.edu> Changes in directory llvm/include/llvm/Target: TargetInstrInfo.h updated: 1.62 -> 1.63 --- Log message: Remove const from iterators passed by value. --- Diffs of the changes: (+2 -2) Index: llvm/include/llvm/Target/TargetInstrInfo.h diff -u llvm/include/llvm/Target/TargetInstrInfo.h:1.62 llvm/include/llvm/Target/TargetInstrInfo.h:1.63 --- llvm/include/llvm/Target/TargetInstrInfo.h:1.62 Sat Jul 31 03:52:30 2004 +++ llvm/include/llvm/Target/TargetInstrInfo.h Sat Jul 31 03:55:23 2004 @@ -161,7 +161,7 @@ // Insert a goto (unconditional branch) sequence to MBB, right // before MBBI virtual void insertGoto(const MachineBasicBlock& MBB, - const MachineBasicBlock::iterator MBBI) const { + MachineBasicBlock::iterator MBBI) const { assert(0 && "Target didn't implement insertGoto!"); } @@ -169,7 +169,7 @@ // Reverses the branch condition of the MachineInstr pointed by // MI. The instruction is replaced and the new MI is returned. virtual MachineBasicBlock::iterator - reverseBranchCondition(const MachineBasicBlock::iterator MI) const { + reverseBranchCondition(MachineBasicBlock::iterator MI) const { assert(0 && "Target didn't implement reverseBranchCondition!"); } From alkis at cs.uiuc.edu Sat Jul 31 03:57:37 2004 From: alkis at cs.uiuc.edu (Alkis Evlogimenos) Date: Sat, 31 Jul 2004 03:57:37 -0500 Subject: [llvm-commits] CVS: llvm/include/llvm/Target/TargetInstrInfo.h Message-ID: <200407310857.DAA11617@zion.cs.uiuc.edu> Changes in directory llvm/include/llvm/Target: TargetInstrInfo.h updated: 1.63 -> 1.64 --- Log message: Doxygenify some comments. --- Diffs of the changes: (+6 -10) Index: llvm/include/llvm/Target/TargetInstrInfo.h diff -u llvm/include/llvm/Target/TargetInstrInfo.h:1.63 llvm/include/llvm/Target/TargetInstrInfo.h:1.64 --- llvm/include/llvm/Target/TargetInstrInfo.h:1.63 Sat Jul 31 03:55:23 2004 +++ llvm/include/llvm/Target/TargetInstrInfo.h Sat Jul 31 03:57:27 2004 @@ -147,27 +147,23 @@ return get(Opcode).Flags & M_TERMINATOR_FLAG; } - // - // Return true if the instruction is a register to register move and - // leave the source and dest operands in the passed parameters. - // + /// Return true if the instruction is a register to register move + /// and leave the source and dest operands in the passed parameters. virtual bool isMoveInstr(const MachineInstr& MI, unsigned& sourceReg, unsigned& destReg) const { return false; } - // - // Insert a goto (unconditional branch) sequence to MBB, right - // before MBBI + /// Insert a goto (unconditional branch) sequence to MBB, right + /// before MBBI virtual void insertGoto(const MachineBasicBlock& MBB, MachineBasicBlock::iterator MBBI) const { assert(0 && "Target didn't implement insertGoto!"); } - // - // Reverses the branch condition of the MachineInstr pointed by - // MI. The instruction is replaced and the new MI is returned. + /// Reverses the branch condition of the MachineInstr pointed by + /// MI. The instruction is replaced and the new MI is returned. virtual MachineBasicBlock::iterator reverseBranchCondition(MachineBasicBlock::iterator MI) const { assert(0 && "Target didn't implement reverseBranchCondition!"); From alkis at cs.uiuc.edu Sat Jul 31 04:38:02 2004 From: alkis at cs.uiuc.edu (Alkis Evlogimenos) Date: Sat, 31 Jul 2004 04:38:02 -0500 Subject: [llvm-commits] CVS: llvm/include/llvm/Target/TargetInstrInfo.h Message-ID: <200407310938.EAA12048@zion.cs.uiuc.edu> Changes in directory llvm/include/llvm/Target: TargetInstrInfo.h updated: 1.64 -> 1.65 --- Log message: Change signature to take two basic blocks: the target and the one where the goto will be appended. --- Diffs of the changes: (+4 -4) Index: llvm/include/llvm/Target/TargetInstrInfo.h diff -u llvm/include/llvm/Target/TargetInstrInfo.h:1.64 llvm/include/llvm/Target/TargetInstrInfo.h:1.65 --- llvm/include/llvm/Target/TargetInstrInfo.h:1.64 Sat Jul 31 03:57:27 2004 +++ llvm/include/llvm/Target/TargetInstrInfo.h Sat Jul 31 04:37:52 2004 @@ -155,10 +155,10 @@ return false; } - /// Insert a goto (unconditional branch) sequence to MBB, right - /// before MBBI - virtual void insertGoto(const MachineBasicBlock& MBB, - MachineBasicBlock::iterator MBBI) const { + /// Insert a goto (unconditional branch) sequence to TMBB, at the + /// end of MBB + virtual void insertGoto(MachineBasicBlock& MBB, + MachineBasicBlock& TMBB) const { assert(0 && "Target didn't implement insertGoto!"); } From alkis at cs.uiuc.edu Sat Jul 31 04:38:57 2004 From: alkis at cs.uiuc.edu (Alkis Evlogimenos) Date: Sat, 31 Jul 2004 04:38:57 -0500 Subject: [llvm-commits] CVS: llvm/lib/Target/X86/X86InstrInfo.h X86InstrInfo.cpp Message-ID: <200407310938.EAA12092@zion.cs.uiuc.edu> Changes in directory llvm/lib/Target/X86: X86InstrInfo.h updated: 1.40 -> 1.41 X86InstrInfo.cpp updated: 1.26 -> 1.27 --- Log message: Implement insertGoto and reverseBranchCondition for the X86. --- Diffs of the changes: (+43 -0) Index: llvm/lib/Target/X86/X86InstrInfo.h diff -u llvm/lib/Target/X86/X86InstrInfo.h:1.40 llvm/lib/Target/X86/X86InstrInfo.h:1.41 --- llvm/lib/Target/X86/X86InstrInfo.h:1.40 Thu Jun 10 23:41:24 2004 +++ llvm/lib/Target/X86/X86InstrInfo.h Sat Jul 31 04:38:47 2004 @@ -203,6 +203,16 @@ unsigned& sourceReg, unsigned& destReg) const; + /// Insert a goto (unconditional branch) sequence to TMBB, at the + /// end of MBB + virtual void insertGoto(MachineBasicBlock& MBB, + MachineBasicBlock& TMBB) const; + + /// Reverses the branch condition of the MachineInstr pointed by + /// MI. The instruction is replaced and the new MI is returned. + virtual MachineBasicBlock::iterator + reverseBranchCondition(MachineBasicBlock::iterator MI) const; + // getBaseOpcodeFor - This function returns the "base" X86 opcode for the // specified opcode number. // Index: llvm/lib/Target/X86/X86InstrInfo.cpp diff -u llvm/lib/Target/X86/X86InstrInfo.cpp:1.26 llvm/lib/Target/X86/X86InstrInfo.cpp:1.27 --- llvm/lib/Target/X86/X86InstrInfo.cpp:1.26 Sun Feb 29 02:50:03 2004 +++ llvm/lib/Target/X86/X86InstrInfo.cpp Sat Jul 31 04:38:47 2004 @@ -38,3 +38,36 @@ } return false; } + +void X86InstrInfo::insertGoto(MachineBasicBlock& MBB, + MachineBasicBlock& TMBB) const { + BuildMI(MBB, MBB.end(), X86::JMP, 1).addMBB(&TMBB); +} + +MachineBasicBlock::iterator +X86InstrInfo::reverseBranchCondition(MachineBasicBlock::iterator MI) const { + unsigned Opcode = MI->getOpcode(); + assert(isBranch(Opcode) && "MachineInstr must be a branch"); + unsigned ROpcode; + switch (Opcode) { + case X86::JB: ROpcode = X86::JAE; + case X86::JAE: ROpcode = X86::JB; + case X86::JE: ROpcode = X86::JNE; + case X86::JNE: ROpcode = X86::JE; + case X86::JBE: ROpcode = X86::JA; + case X86::JA: ROpcode = X86::JBE; + case X86::JS: ROpcode = X86::JNS; + case X86::JNS: ROpcode = X86::JS; + case X86::JL: ROpcode = X86::JGE; + case X86::JGE: ROpcode = X86::JL; + case X86::JLE: ROpcode = X86::JG; + case X86::JG: ROpcode = X86::JLE; + default: + assert(0 && "Cannot reverse uncodnitional branches!"); + } + MachineBasicBlock* MBB = MI->getParent(); + MachineBasicBlock* TMBB = MI->getOperand(0).getMachineBasicBlock(); + MachineInstrBuilder IB = BuildMI(*MBB, MBB->erase(MI), ROpcode, 1); + IB.addMBB(TMBB); + return IB; +} From alkis at cs.uiuc.edu Sat Jul 31 04:41:54 2004 From: alkis at cs.uiuc.edu (Alkis Evlogimenos) Date: Sat, 31 Jul 2004 04:41:54 -0500 Subject: [llvm-commits] CVS: llvm/lib/Target/X86/X86InstrInfo.cpp Message-ID: <200407310941.EAA12146@zion.cs.uiuc.edu> Changes in directory llvm/lib/Target/X86: X86InstrInfo.cpp updated: 1.27 -> 1.28 --- Log message: Correctly spell 'unconditional'. --- Diffs of the changes: (+1 -1) Index: llvm/lib/Target/X86/X86InstrInfo.cpp diff -u llvm/lib/Target/X86/X86InstrInfo.cpp:1.27 llvm/lib/Target/X86/X86InstrInfo.cpp:1.28 --- llvm/lib/Target/X86/X86InstrInfo.cpp:1.27 Sat Jul 31 04:38:47 2004 +++ llvm/lib/Target/X86/X86InstrInfo.cpp Sat Jul 31 04:41:44 2004 @@ -63,7 +63,7 @@ case X86::JLE: ROpcode = X86::JG; case X86::JG: ROpcode = X86::JLE; default: - assert(0 && "Cannot reverse uncodnitional branches!"); + assert(0 && "Cannot reverse unconditional branches!"); } MachineBasicBlock* MBB = MI->getParent(); MachineBasicBlock* TMBB = MI->getOperand(0).getMachineBasicBlock(); From alkis at cs.uiuc.edu Sat Jul 31 04:44:42 2004 From: alkis at cs.uiuc.edu (Alkis Evlogimenos) Date: Sat, 31 Jul 2004 04:44:42 -0500 Subject: [llvm-commits] CVS: llvm/lib/Target/X86/X86InstrInfo.cpp Message-ID: <200407310944.EAA12171@zion.cs.uiuc.edu> Changes in directory llvm/lib/Target/X86: X86InstrInfo.cpp updated: 1.28 -> 1.29 --- Log message: Simplify code a bit. --- Diffs of the changes: (+1 -3) Index: llvm/lib/Target/X86/X86InstrInfo.cpp diff -u llvm/lib/Target/X86/X86InstrInfo.cpp:1.28 llvm/lib/Target/X86/X86InstrInfo.cpp:1.29 --- llvm/lib/Target/X86/X86InstrInfo.cpp:1.28 Sat Jul 31 04:41:44 2004 +++ llvm/lib/Target/X86/X86InstrInfo.cpp Sat Jul 31 04:44:32 2004 @@ -67,7 +67,5 @@ } MachineBasicBlock* MBB = MI->getParent(); MachineBasicBlock* TMBB = MI->getOperand(0).getMachineBasicBlock(); - MachineInstrBuilder IB = BuildMI(*MBB, MBB->erase(MI), ROpcode, 1); - IB.addMBB(TMBB); - return IB; + return BuildMI(*MBB, MBB->erase(MI), ROpcode, 1).addMBB(TMBB); } From lattner at cs.uiuc.edu Sat Jul 31 04:53:42 2004 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Sat, 31 Jul 2004 04:53:42 -0500 Subject: [llvm-commits] CVS: llvm/lib/Target/X86/X86InstrInfo.cpp Message-ID: <200407310953.EAA11517@apoc.cs.uiuc.edu> Changes in directory llvm/lib/Target/X86: X86InstrInfo.cpp updated: 1.29 -> 1.30 --- Log message: Add breaks --- Diffs of the changes: (+12 -12) Index: llvm/lib/Target/X86/X86InstrInfo.cpp diff -u llvm/lib/Target/X86/X86InstrInfo.cpp:1.29 llvm/lib/Target/X86/X86InstrInfo.cpp:1.30 --- llvm/lib/Target/X86/X86InstrInfo.cpp:1.29 Sat Jul 31 04:44:32 2004 +++ llvm/lib/Target/X86/X86InstrInfo.cpp Sat Jul 31 04:53:31 2004 @@ -50,18 +50,18 @@ assert(isBranch(Opcode) && "MachineInstr must be a branch"); unsigned ROpcode; switch (Opcode) { - case X86::JB: ROpcode = X86::JAE; - case X86::JAE: ROpcode = X86::JB; - case X86::JE: ROpcode = X86::JNE; - case X86::JNE: ROpcode = X86::JE; - case X86::JBE: ROpcode = X86::JA; - case X86::JA: ROpcode = X86::JBE; - case X86::JS: ROpcode = X86::JNS; - case X86::JNS: ROpcode = X86::JS; - case X86::JL: ROpcode = X86::JGE; - case X86::JGE: ROpcode = X86::JL; - case X86::JLE: ROpcode = X86::JG; - case X86::JG: ROpcode = X86::JLE; + case X86::JB: ROpcode = X86::JAE; break; + case X86::JAE: ROpcode = X86::JB; break; + case X86::JE: ROpcode = X86::JNE; break; + case X86::JNE: ROpcode = X86::JE; break; + case X86::JBE: ROpcode = X86::JA; break; + case X86::JA: ROpcode = X86::JBE; break; + case X86::JS: ROpcode = X86::JNS; break; + case X86::JNS: ROpcode = X86::JS; break; + case X86::JL: ROpcode = X86::JGE; break; + case X86::JGE: ROpcode = X86::JL; break; + case X86::JLE: ROpcode = X86::JG; break; + case X86::JG: ROpcode = X86::JLE; break; default: assert(0 && "Cannot reverse unconditional branches!"); } From lattner at cs.uiuc.edu Sat Jul 31 04:59:15 2004 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Sat, 31 Jul 2004 04:59:15 -0500 Subject: [llvm-commits] CVS: llvm/include/llvm/CodeGen/MachineBasicBlock.h Message-ID: <200407310959.EAA12979@apoc.cs.uiuc.edu> Changes in directory llvm/include/llvm/CodeGen: MachineBasicBlock.h updated: 1.36 -> 1.37 --- Log message: Expose some helpful methods --- Diffs of the changes: (+8 -0) Index: llvm/include/llvm/CodeGen/MachineBasicBlock.h diff -u llvm/include/llvm/CodeGen/MachineBasicBlock.h:1.36 llvm/include/llvm/CodeGen/MachineBasicBlock.h:1.37 --- llvm/include/llvm/CodeGen/MachineBasicBlock.h:1.36 Fri Jul 30 20:59:11 2004 +++ llvm/include/llvm/CodeGen/MachineBasicBlock.h Sat Jul 31 04:59:04 2004 @@ -159,6 +159,7 @@ iterator getFirstTerminator(); void pop_front() { Insts.pop_front(); } + void pop_back() { Insts.pop_back(); } void push_back(MachineInstr *MI) { Insts.push_back(MI); } template void insert(iterator I, IT S, IT E) { Insts.insert(I, S, E); } @@ -171,6 +172,13 @@ iterator erase(iterator I, iterator E) { return Insts.erase(I, E); } MachineInstr *remove(MachineInstr *I) { return Insts.remove(I); } void clear() { Insts.clear(); } + + /// splice - Take a block of instructions from MBB 'Other' in the range [From, + /// To), and insert them into this MBB right before 'where'. + void splice(iterator where, MachineBasicBlock *Other, iterator From, + iterator To) { + Insts.splice(where, Other->Insts, From, To); + } // Debugging methods. void dump() const; From lattner at cs.uiuc.edu Sat Jul 31 04:59:24 2004 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Sat, 31 Jul 2004 04:59:24 -0500 Subject: [llvm-commits] CVS: llvm/include/llvm/CodeGen/Passes.h Message-ID: <200407310959.EAA13143@apoc.cs.uiuc.edu> Changes in directory llvm/include/llvm/CodeGen: Passes.h updated: 1.17 -> 1.18 --- Log message: New pass --- Diffs of the changes: (+6 -0) Index: llvm/include/llvm/CodeGen/Passes.h diff -u llvm/include/llvm/CodeGen/Passes.h:1.17 llvm/include/llvm/CodeGen/Passes.h:1.18 --- llvm/include/llvm/CodeGen/Passes.h:1.17 Wed Jul 21 03:24:35 2004 +++ llvm/include/llvm/CodeGen/Passes.h Sat Jul 31 04:59:14 2004 @@ -80,6 +80,12 @@ /// FunctionPass *createPrologEpilogCodeInserter(); + /// BranchFolding Pass - This pass performs machine code CFG based + /// optimizations to delete branches to branches, eliminate branches to + /// successor blocks (creating fall throughs), and eliminating branches over + /// branches. + FunctionPass *createBranchFoldingPass(); + /// MachineCodeDeletion Pass - This pass deletes all of the machine code for /// the current function, which should happen after the function has been /// emitted to a .s file or to memory. From lattner at cs.uiuc.edu Sat Jul 31 05:01:37 2004 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Sat, 31 Jul 2004 05:01:37 -0500 Subject: [llvm-commits] CVS: llvm/lib/CodeGen/BranchFolding.cpp Message-ID: <200407311001.FAA13460@apoc.cs.uiuc.edu> Changes in directory llvm/lib/CodeGen: BranchFolding.cpp added (r1.1) --- Log message: Implement a simple target-independent CFG cleanup pass --- Diffs of the changes: (+201 -0) Index: llvm/lib/CodeGen/BranchFolding.cpp diff -c /dev/null llvm/lib/CodeGen/BranchFolding.cpp:1.1 *** /dev/null Sat Jul 31 05:01:37 2004 --- llvm/lib/CodeGen/BranchFolding.cpp Sat Jul 31 05:01:27 2004 *************** *** 0 **** --- 1,201 ---- + //===-- BranchFolding.cpp - Fold machine code branch instructions ---------===// + // + // The LLVM Compiler Infrastructure + // + // This file was developed by the LLVM research group and is distributed under + // the University of Illinois Open Source License. See LICENSE.TXT for details. + // + //===----------------------------------------------------------------------===// + // + // This pass forwards branches to unconditional branches to make them branch + // directly to the target block. This pass often results in dead MBB's, which + // it then removes. + // + // Note that this pass must be run after register allocation, it cannot handle + // SSA form. + // + //===----------------------------------------------------------------------===// + + #include "llvm/CodeGen/Passes.h" + #include "llvm/CodeGen/MachineFunctionPass.h" + #include "llvm/Target/TargetInstrInfo.h" + #include "llvm/Target/TargetMachine.h" + using namespace llvm; + + namespace { + struct BranchFolder : public MachineFunctionPass { + virtual bool runOnMachineFunction(MachineFunction &MF); + virtual const char *getPassName() const { return "Branch Folder"; } + private: + bool OptimizeBlock(MachineBasicBlock *MBB, const TargetInstrInfo &TII); + + + bool isUncondBranch(const MachineInstr *MI, const TargetInstrInfo &TII) { + return TII.isBarrier(MI->getOpcode()) && TII.isBranch(MI->getOpcode()); + } + bool isCondBranch(const MachineInstr *MI, const TargetInstrInfo &TII) { + return TII.isBranch(MI->getOpcode()) && !TII.isBarrier(MI->getOpcode()); + } + }; + } + + FunctionPass *llvm::createBranchFoldingPass() { return new BranchFolder(); } + + bool BranchFolder::runOnMachineFunction(MachineFunction &MF) { + bool EverMadeChange = false; + bool MadeChange = true; + const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo(); + while (MadeChange) { + MadeChange = false; + for (MachineFunction::iterator MBB = ++MF.begin(), E = MF.end(); MBB != E; + ++MBB) + MadeChange |= OptimizeBlock(MBB, TII); + + // If branches were folded away somehow, do a quick scan and delete any dead + // blocks. + if (MadeChange) { + for (MachineFunction::iterator I = ++MF.begin(), E = MF.end(); I != E; ) { + MachineBasicBlock *MBB = I++; + // Is it dead? + if (MBB->pred_empty()) { + // drop all successors. + while (!MBB->succ_empty()) + MBB->removeSuccessor(MBB->succ_end()-1); + MF.getBasicBlockList().erase(MBB); + } + } + } + + EverMadeChange |= MadeChange; + } + + return EverMadeChange; + } + + /// ReplaceUsesOfBlockWith - Given a machine basic block 'BB' that branched to + /// 'Old', change the code and CFG so that it branches to 'New' instead. + static void ReplaceUsesOfBlockWith(MachineBasicBlock *BB, + MachineBasicBlock *Old, + MachineBasicBlock *New, + const TargetInstrInfo &TII) { + assert(Old != New && "Cannot replace self with self!"); + + MachineBasicBlock::iterator I = BB->end(); + while (I != BB->begin()) { + --I; + if (!TII.isTerminatorInstr(I->getOpcode())) break; + + // Scan the operands of this machine instruction, replacing any uses of Old + // with New. + for (unsigned i = 0, e = I->getNumOperands(); i != e; ++i) + if (I->getOperand(i).isMachineBasicBlock() && + I->getOperand(i).getMachineBasicBlock() == Old) + I->getOperand(i).setMachineBasicBlock(New); + } + + // If BB falls through into Old, insert an unconditional branch to New. + MachineFunction::iterator BBSucc = BB; ++BBSucc; + if (&*BBSucc == Old) + TII.insertGoto(*BB, *New); + + std::vector Succs(BB->succ_begin(), BB->succ_end()); + for (int i = Succs.size()-1; i >= 0; --i) + if (Succs[i] == Old) { + BB->removeSuccessor(Old); + BB->addSuccessor(New); + } + } + + + bool BranchFolder::OptimizeBlock(MachineBasicBlock *MBB, + const TargetInstrInfo &TII) { + // If this block is empty, make everyone use it's fall-through, not the block + // explicitly. + if (MBB->empty()) { + if (MBB->pred_empty()) return false; + MachineFunction::iterator FallThrough = MBB; ++FallThrough; + assert(FallThrough != MBB->getParent()->end() && + "Fell off the end of the function!"); + while (!MBB->pred_empty()) { + MachineBasicBlock *Pred = *(MBB->pred_end()-1); + ReplaceUsesOfBlockWith(Pred, MBB, FallThrough, TII); + } + return true; + } + + if (MBB->pred_size() == 1) { + // If this block has a single predecessor, and if that block has a single + // successor, merge this block into that block. + MachineBasicBlock *Pred = *MBB->pred_begin(); + if (Pred->succ_size() == 1) { + // Delete all of the terminators from end of the pred block. NOTE, this + // assumes that terminators do not have side effects! + while (!Pred->empty() && TII.isTerminatorInstr(Pred->back().getOpcode())) + Pred->pop_back(); + + // Splice the instructions over. + Pred->splice(Pred->end(), MBB, MBB->begin(), MBB->end()); + + // If MBB does not end with a barrier, add a goto instruction to the end. + if (Pred->empty() || !TII.isBarrier(Pred->back().getOpcode())) + TII.insertGoto(*Pred, *++MachineFunction::iterator(MBB)); + + // Update the CFG now. + Pred->removeSuccessor(Pred->succ_begin()); + while (!MBB->succ_empty()) { + Pred->addSuccessor(*(MBB->succ_end()-1)); + MBB->removeSuccessor(MBB->succ_end()-1); + } + return true; + } + } + + // If the first instruction in this block is an unconditional branch, and if + // there are predecessors, fold the branch into the predecessors. + if (!MBB->pred_empty() && isUncondBranch(MBB->begin(), TII)) { + MachineInstr *Br = MBB->begin(); + assert(Br->getNumOperands() == 1 && Br->getOperand(0).isMachineBasicBlock() + && "Uncond branch should take one MBB argument!"); + MachineBasicBlock *Dest = Br->getOperand(0).getMachineBasicBlock(); + + while (!MBB->pred_empty()) { + MachineBasicBlock *Pred = *(MBB->pred_end()-1); + ReplaceUsesOfBlockWith(Pred, MBB, Dest, TII); + } + return true; + } + + // If the last instruction is an unconditional branch and the fall through + // block is the destination, just delete the branch. + if (isUncondBranch(--MBB->end(), TII)) { + MachineBasicBlock::iterator MI = --MBB->end(); + MachineInstr *UncondBr = MI; + MachineFunction::iterator FallThrough = MBB; ++FallThrough; + + MachineBasicBlock *UncondDest = MI->getOperand(0).getMachineBasicBlock(); + if (UncondDest == &*FallThrough) { + // Just delete the branch. This does not effect the CFG. + MBB->erase(UncondBr); + return true; + } + + // Okay, so we don't have a fall-through. Check to see if we have an + // conditional branch that would be a fall through if we reversed it. If + // so, invert the condition and delete the uncond branch. + if (MI != MBB->begin() && isCondBranch(--MI, TII)) { + // We assume that conditional branches always have the branch dest as the + // last operand. This could be generalized in the future if needed. + unsigned LastOpnd = MI->getNumOperands()-1; + if (MI->getOperand(LastOpnd).getMachineBasicBlock() == &*FallThrough) { + // Change the cond branch to go to the uncond dest, nuke the uncond, + // then reverse the condition. + MI->getOperand(LastOpnd).setMachineBasicBlock(UncondDest); + MBB->erase(UncondBr); + TII.reverseBranchCondition(MI); + return true; + } + } + } + + return false; + } From lattner at cs.uiuc.edu Sat Jul 31 05:02:09 2004 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Sat, 31 Jul 2004 05:02:09 -0500 Subject: [llvm-commits] CVS: llvm/lib/Transforms/Utils/BreakCriticalEdges.cpp Message-ID: <200407311002.FAA13474@apoc.cs.uiuc.edu> Changes in directory llvm/lib/Transforms/Utils: BreakCriticalEdges.cpp updated: 1.21 -> 1.22 --- Log message: Expose this as a functionpass --- Diffs of the changes: (+3 -1) Index: llvm/lib/Transforms/Utils/BreakCriticalEdges.cpp diff -u llvm/lib/Transforms/Utils/BreakCriticalEdges.cpp:1.21 llvm/lib/Transforms/Utils/BreakCriticalEdges.cpp:1.22 --- llvm/lib/Transforms/Utils/BreakCriticalEdges.cpp:1.21 Thu Jul 29 12:24:20 2004 +++ llvm/lib/Transforms/Utils/BreakCriticalEdges.cpp Sat Jul 31 05:01:58 2004 @@ -48,7 +48,9 @@ // Publically exposed interface to pass... const PassInfo *llvm::BreakCriticalEdgesID = X.getPassInfo(); -Pass *llvm::createBreakCriticalEdgesPass() { return new BreakCriticalEdges(); } +FunctionPass *llvm::createBreakCriticalEdgesPass() { + return new BreakCriticalEdges(); +} // runOnFunction - Loop over all of the edges in the CFG, breaking critical // edges as they are found. From lattner at cs.uiuc.edu Sat Jul 31 05:02:35 2004 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Sat, 31 Jul 2004 05:02:35 -0500 Subject: [llvm-commits] CVS: llvm/include/llvm/Transforms/Scalar.h Message-ID: <200407311002.FAA13486@apoc.cs.uiuc.edu> Changes in directory llvm/include/llvm/Transforms: Scalar.h updated: 1.43 -> 1.44 --- Log message: Expose breakcriticaledges as a functionpass --- Diffs of the changes: (+1 -1) Index: llvm/include/llvm/Transforms/Scalar.h diff -u llvm/include/llvm/Transforms/Scalar.h:1.43 llvm/include/llvm/Transforms/Scalar.h:1.44 --- llvm/include/llvm/Transforms/Scalar.h:1.43 Tue Jul 27 12:43:21 2004 +++ llvm/include/llvm/Transforms/Scalar.h Sat Jul 31 05:02:24 2004 @@ -239,7 +239,7 @@ // This pass obviously invalidates the CFG, but can update forward dominator // (set, immediate dominators, tree, and frontier) information. // -Pass *createBreakCriticalEdgesPass(); +FunctionPass *createBreakCriticalEdgesPass(); extern const PassInfo *BreakCriticalEdgesID; //===----------------------------------------------------------------------===// From alkis at cs.uiuc.edu Sat Jul 31 05:05:55 2004 From: alkis at cs.uiuc.edu (Alkis Evlogimenos) Date: Sat, 31 Jul 2004 05:05:55 -0500 Subject: [llvm-commits] CVS: llvm/lib/Target/X86/X86InstrInfo.cpp Message-ID: <200407311005.FAA12387@zion.cs.uiuc.edu> Changes in directory llvm/lib/Target/X86: X86InstrInfo.cpp updated: 1.30 -> 1.31 --- Log message: Align breaks. --- Diffs of the changes: (+6 -6) Index: llvm/lib/Target/X86/X86InstrInfo.cpp diff -u llvm/lib/Target/X86/X86InstrInfo.cpp:1.30 llvm/lib/Target/X86/X86InstrInfo.cpp:1.31 --- llvm/lib/Target/X86/X86InstrInfo.cpp:1.30 Sat Jul 31 04:53:31 2004 +++ llvm/lib/Target/X86/X86InstrInfo.cpp Sat Jul 31 05:05:44 2004 @@ -51,16 +51,16 @@ unsigned ROpcode; switch (Opcode) { case X86::JB: ROpcode = X86::JAE; break; - case X86::JAE: ROpcode = X86::JB; break; + case X86::JAE: ROpcode = X86::JB; break; case X86::JE: ROpcode = X86::JNE; break; - case X86::JNE: ROpcode = X86::JE; break; - case X86::JBE: ROpcode = X86::JA; break; + case X86::JNE: ROpcode = X86::JE; break; + case X86::JBE: ROpcode = X86::JA; break; case X86::JA: ROpcode = X86::JBE; break; case X86::JS: ROpcode = X86::JNS; break; - case X86::JNS: ROpcode = X86::JS; break; + case X86::JNS: ROpcode = X86::JS; break; case X86::JL: ROpcode = X86::JGE; break; - case X86::JGE: ROpcode = X86::JL; break; - case X86::JLE: ROpcode = X86::JG; break; + case X86::JGE: ROpcode = X86::JL; break; + case X86::JLE: ROpcode = X86::JG; break; case X86::JG: ROpcode = X86::JLE; break; default: assert(0 && "Cannot reverse unconditional branches!"); From alkis at cs.uiuc.edu Sat Jul 31 10:04:02 2004 From: alkis at cs.uiuc.edu (Alkis Evlogimenos) Date: Sat, 31 Jul 2004 10:04:02 -0500 Subject: [llvm-commits] CVS: llvm/lib/CodeGen/BranchFolding.cpp Message-ID: <200407311504.KAA13547@zion.cs.uiuc.edu> Changes in directory llvm/lib/CodeGen: BranchFolding.cpp updated: 1.1 -> 1.2 --- Log message: Use MachineFunction::iterator instead of a MachineBasicBlock* because FallThrough maybe == to MF.end(). --- Diffs of the changes: (+3 -2) Index: llvm/lib/CodeGen/BranchFolding.cpp diff -u llvm/lib/CodeGen/BranchFolding.cpp:1.1 llvm/lib/CodeGen/BranchFolding.cpp:1.2 --- llvm/lib/CodeGen/BranchFolding.cpp:1.1 Sat Jul 31 05:01:27 2004 +++ llvm/lib/CodeGen/BranchFolding.cpp Sat Jul 31 10:03:52 2004 @@ -172,8 +172,9 @@ MachineInstr *UncondBr = MI; MachineFunction::iterator FallThrough = MBB; ++FallThrough; - MachineBasicBlock *UncondDest = MI->getOperand(0).getMachineBasicBlock(); - if (UncondDest == &*FallThrough) { + MachineFunction::iterator UncondDest = + MI->getOperand(0).getMachineBasicBlock(); + if (UncondDest == FallThrough) { // Just delete the branch. This does not effect the CFG. MBB->erase(UncondBr); return true; From alkis at cs.uiuc.edu Sat Jul 31 10:14:39 2004 From: alkis at cs.uiuc.edu (Alkis Evlogimenos) Date: Sat, 31 Jul 2004 10:14:39 -0500 Subject: [llvm-commits] CVS: llvm/lib/CodeGen/BranchFolding.cpp Message-ID: <200407311514.KAA13606@zion.cs.uiuc.edu> Changes in directory llvm/lib/CodeGen: BranchFolding.cpp updated: 1.2 -> 1.3 --- Log message: Use next() helper to make code more readable. Use MachineFunction::iterator instead of MachineBasicBlock* to avoid dereferencing end iterators. --- Diffs of the changes: (+6 -4) Index: llvm/lib/CodeGen/BranchFolding.cpp diff -u llvm/lib/CodeGen/BranchFolding.cpp:1.2 llvm/lib/CodeGen/BranchFolding.cpp:1.3 --- llvm/lib/CodeGen/BranchFolding.cpp:1.2 Sat Jul 31 10:03:52 2004 +++ llvm/lib/CodeGen/BranchFolding.cpp Sat Jul 31 10:14:29 2004 @@ -20,6 +20,7 @@ #include "llvm/CodeGen/MachineFunctionPass.h" #include "llvm/Target/TargetInstrInfo.h" #include "llvm/Target/TargetMachine.h" +#include "Support/STLExtras.h" using namespace llvm; namespace { @@ -113,7 +114,7 @@ // explicitly. if (MBB->empty()) { if (MBB->pred_empty()) return false; - MachineFunction::iterator FallThrough = MBB; ++FallThrough; + MachineFunction::iterator FallThrough = next(MBB); assert(FallThrough != MBB->getParent()->end() && "Fell off the end of the function!"); while (!MBB->pred_empty()) { @@ -138,7 +139,7 @@ // If MBB does not end with a barrier, add a goto instruction to the end. if (Pred->empty() || !TII.isBarrier(Pred->back().getOpcode())) - TII.insertGoto(*Pred, *++MachineFunction::iterator(MBB)); + TII.insertGoto(*Pred, *next(MBB)); // Update the CFG now. Pred->removeSuccessor(Pred->succ_begin()); @@ -170,7 +171,7 @@ if (isUncondBranch(--MBB->end(), TII)) { MachineBasicBlock::iterator MI = --MBB->end(); MachineInstr *UncondBr = MI; - MachineFunction::iterator FallThrough = MBB; ++FallThrough; + MachineFunction::iterator FallThrough = next(MBB); MachineFunction::iterator UncondDest = MI->getOperand(0).getMachineBasicBlock(); @@ -187,7 +188,8 @@ // We assume that conditional branches always have the branch dest as the // last operand. This could be generalized in the future if needed. unsigned LastOpnd = MI->getNumOperands()-1; - if (MI->getOperand(LastOpnd).getMachineBasicBlock() == &*FallThrough) { + if (MachineFunction::iterator( + MI->getOperand(LastOpnd).getMachineBasicBlock()) == FallThrough) { // Change the cond branch to go to the uncond dest, nuke the uncond, // then reverse the condition. MI->getOperand(LastOpnd).setMachineBasicBlock(UncondDest); From criswell at cs.uiuc.edu Sat Jul 31 11:31:24 2004 From: criswell at cs.uiuc.edu (John Criswell) Date: Sat, 31 Jul 2004 11:31:24 -0500 Subject: [llvm-commits] CVS: llvm/test/Programs/External/SPEC/Makefile Message-ID: <200407311631.LAA06707@choi.cs.uiuc.edu> Changes in directory llvm/test/Programs/External/SPEC: Makefile updated: 1.10 -> 1.11 --- Log message: Changed to PARALLEL_DIRS so that SPEC95 will be tested even if something in SPEC2000 fails. --- Diffs of the changes: (+4 -4) Index: llvm/test/Programs/External/SPEC/Makefile diff -u llvm/test/Programs/External/SPEC/Makefile:1.10 llvm/test/Programs/External/SPEC/Makefile:1.11 --- llvm/test/Programs/External/SPEC/Makefile:1.10 Mon Mar 1 09:46:27 2004 +++ llvm/test/Programs/External/SPEC/Makefile Sat Jul 31 11:31:13 2004 @@ -1,17 +1,17 @@ LEVEL = ../../../.. -DIRS := CFP2000 CINT2000 CINT95 +PARALLEL_DIRS := CFP2000 CINT2000 CINT95 include ${LEVEL}/Makefile.config # # Remove SPEC95 and SPEC2000 per the user's configuration # ifndef USE_SPEC2000 -DIRS := $(filter-out CFP2000/, $(DIRS)) -DIRS := $(filter-out CINT2000/, $(DIRS)) +PARALLEL_DIRS := $(filter-out CFP2000/, $(PARALLEL_DIRS)) +PARALLEL_DIRS := $(filter-out CINT2000/, $(PARALLEL_DIRS)) endif ifndef USE_SPEC95 -DIRS := $(filter-out CINT95/, $(DIRS)) +PARALLEL_DIRS := $(filter-out CINT95/, $(PARALLEL_DIRS)) endif include ${LEVEL}/test/Programs/Makefile.programs From lattner at cs.uiuc.edu Sat Jul 31 13:40:46 2004 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Sat, 31 Jul 2004 13:40:46 -0500 Subject: [llvm-commits] CVS: llvm/lib/CodeGen/BranchFolding.cpp Message-ID: <200407311840.NAA20167@apoc.cs.uiuc.edu> Changes in directory llvm/lib/CodeGen: BranchFolding.cpp updated: 1.3 -> 1.4 --- Log message: Next on a pointer increments the pointer, not an iterator --- Diffs of the changes: (+1 -1) Index: llvm/lib/CodeGen/BranchFolding.cpp diff -u llvm/lib/CodeGen/BranchFolding.cpp:1.3 llvm/lib/CodeGen/BranchFolding.cpp:1.4 --- llvm/lib/CodeGen/BranchFolding.cpp:1.3 Sat Jul 31 10:14:29 2004 +++ llvm/lib/CodeGen/BranchFolding.cpp Sat Jul 31 13:40:36 2004 @@ -114,7 +114,7 @@ // explicitly. if (MBB->empty()) { if (MBB->pred_empty()) return false; - MachineFunction::iterator FallThrough = next(MBB); + MachineFunction::iterator FallThrough =next(MachineFunction::iterator(MBB)); assert(FallThrough != MBB->getParent()->end() && "Fell off the end of the function!"); while (!MBB->pred_empty()) { From alkis at cs.uiuc.edu Sat Jul 31 14:24:51 2004 From: alkis at cs.uiuc.edu (Alkis Evlogimenos) Date: Sat, 31 Jul 2004 14:24:51 -0500 Subject: [llvm-commits] CVS: llvm/lib/CodeGen/BranchFolding.cpp Message-ID: <200407311924.OAA27464@zion.cs.uiuc.edu> Changes in directory llvm/lib/CodeGen: BranchFolding.cpp updated: 1.4 -> 1.5 --- Log message: Make OptimizeBlock take a MachineFunction::iterator instead of a MachineBasicBlock* as a parameter so that nxext() and prior() helper functions can work naturally on it. --- Diffs of the changes: (+4 -4) Index: llvm/lib/CodeGen/BranchFolding.cpp diff -u llvm/lib/CodeGen/BranchFolding.cpp:1.4 llvm/lib/CodeGen/BranchFolding.cpp:1.5 --- llvm/lib/CodeGen/BranchFolding.cpp:1.4 Sat Jul 31 13:40:36 2004 +++ llvm/lib/CodeGen/BranchFolding.cpp Sat Jul 31 14:24:41 2004 @@ -28,8 +28,8 @@ virtual bool runOnMachineFunction(MachineFunction &MF); virtual const char *getPassName() const { return "Branch Folder"; } private: - bool OptimizeBlock(MachineBasicBlock *MBB, const TargetInstrInfo &TII); - + bool OptimizeBlock(MachineFunction::iterator MBB, + const TargetInstrInfo &TII); bool isUncondBranch(const MachineInstr *MI, const TargetInstrInfo &TII) { return TII.isBarrier(MI->getOpcode()) && TII.isBranch(MI->getOpcode()); @@ -108,13 +108,13 @@ } -bool BranchFolder::OptimizeBlock(MachineBasicBlock *MBB, +bool BranchFolder::OptimizeBlock(MachineFunction::iterator MBB, const TargetInstrInfo &TII) { // If this block is empty, make everyone use it's fall-through, not the block // explicitly. if (MBB->empty()) { if (MBB->pred_empty()) return false; - MachineFunction::iterator FallThrough =next(MachineFunction::iterator(MBB)); + MachineFunction::iterator FallThrough =next(MBB); assert(FallThrough != MBB->getParent()->end() && "Fell off the end of the function!"); while (!MBB->pred_empty()) { From lattner at cs.uiuc.edu Sat Jul 31 22:19:39 2004 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Sat, 31 Jul 2004 22:19:39 -0500 Subject: [llvm-commits] CVS: llvm/lib/Target/X86/X86InstrSel.td Message-ID: <200408010319.WAA30725@apoc.cs.uiuc.edu> Changes in directory llvm/lib/Target/X86: X86InstrSel.td (r1.1) removed --- Log message: Remove obsolete file --- Diffs of the changes: (+0 -0) From lattner at cs.uiuc.edu Sat Jul 31 22:23:44 2004 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Sat, 31 Jul 2004 22:23:44 -0500 Subject: [llvm-commits] CVS: llvm/lib/Target/Target.td Message-ID: <200408010323.WAA01515@apoc.cs.uiuc.edu> Changes in directory llvm/lib/Target: Target.td updated: 1.26 -> 1.27 --- Log message: Move the 'Expander' node to later in the file, with the other experimental stuff. The pattern becomes a list, add some stuff, add some comments. --- Diffs of the changes: (+23 -15) Index: llvm/lib/Target/Target.td diff -u llvm/lib/Target/Target.td:1.26 llvm/lib/Target/Target.td:1.27 --- llvm/lib/Target/Target.td:1.26 Fri Jul 30 21:07:07 2004 +++ llvm/lib/Target/Target.td Sat Jul 31 22:23:34 2004 @@ -1,4 +1,4 @@ -//===- Target.td - Target Independent TableGen interface --------*- C++ -*-===// +//===- Target.td - Target Independent TableGen interface ---*- tablegen -*-===// // // The LLVM Compiler Infrastructure // @@ -105,13 +105,22 @@ // Instruction set description - These classes correspond to the C++ classes in // the Target/TargetInstrInfo.h file. // - class Instruction { - string Name; // The opcode string for this instruction + string Name; // The opcode string for this instruction string Namespace = ""; - list Uses = []; // Default to using no non-operand registers - list Defs = []; // Default to modifying no non-operand registers + dag OperandList; // An dag containing the MI operand list. + string AsmString; // The .s format to print the instruction with. + + // Pattern - Set to the DAG pattern for this instruction, if we know of one, + // otherwise, uninitialized. + list Pattern; + + // The follow state will eventually be inferred automatically from the + // instruction pattern. + + list Uses = []; // Default to using no non-operand registers + list Defs = []; // Default to modifying no non-operand registers // These bits capture information about the high-level semantics of the // instruction. @@ -121,15 +130,6 @@ bit isCall = 0; // Is this instruction a call instruction? bit isTwoAddress = 0; // Is this a two address instruction? bit isTerminator = 0; // Is this part of the terminator for a basic block? - - // Pattern - Set to the DAG pattern for this instruction, if we know of one, - // otherwise, uninitialized. - dag Pattern; -} - -class Expander result> { - dag Pattern = pattern; - list Result = result; } @@ -166,8 +166,16 @@ //===----------------------------------------------------------------------===// -// DAG node definitions used by the instruction selector... +// DAG node definitions used by the instruction selector. // +// NOTE: all of this is a work-in-progress and should be ignored for now. +// + +class Expander result> { + dag Pattern = pattern; + list Result = result; +} + class DagNodeValType; def DNVT_any : DagNodeValType; // No constraint on tree node def DNVT_void : DagNodeValType; // Tree node always returns void From lattner at cs.uiuc.edu Sat Jul 31 22:25:11 2004 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Sat, 31 Jul 2004 22:25:11 -0500 Subject: [llvm-commits] CVS: llvm/lib/Target/X86/X86InstrInfo.td Message-ID: <200408010325.WAA01529@apoc.cs.uiuc.edu> Changes in directory llvm/lib/Target/X86: X86InstrInfo.td updated: 1.81 -> 1.82 --- Log message: Entirely eliminate all patterns and expanders from this file. We shall go with an incremental approach rather than a revolutionary approach. --- Diffs of the changes: (+45 -82) Index: llvm/lib/Target/X86/X86InstrInfo.td diff -u llvm/lib/Target/X86/X86InstrInfo.td:1.81 llvm/lib/Target/X86/X86InstrInfo.td:1.82 --- llvm/lib/Target/X86/X86InstrInfo.td:1.81 Fri Jul 30 21:10:53 2004 +++ llvm/lib/Target/X86/X86InstrInfo.td Sat Jul 31 22:25:01 2004 @@ -108,10 +108,6 @@ list Defs = defs; } -class Pattern { - dag Pattern = P; -} - // Prefix byte classes which are used to indicate to the ad-hoc machine code // emitter that various prefix bytes are required. @@ -176,17 +172,17 @@ // Return instruction... let isTerminator = 1, isReturn = 1, isBarrier = 1 in - def RET : I<"ret", 0xC3, RawFrm>, Pattern<(retvoid)>; + def RET : I<"ret", 0xC3, RawFrm>; // All branches are RawFrm, Void, Branch, and Terminators let isBranch = 1, isTerminator = 1 in class IBr opcode> : I; let isBarrier = 1 in - def JMP : IBr<"jmp", 0xE9>, Pattern<(br basicblock)>; + def JMP : IBr<"jmp", 0xE9>; def JB : IBr<"jb" , 0x82>, TB; def JAE : IBr<"jae", 0x83>, TB; -def JE : IBr<"je" , 0x84>, TB, Pattern<(isVoid (unspec1 basicblock))>; +def JE : IBr<"je" , 0x84>, TB; def JNE : IBr<"jne", 0x85>, TB; def JBE : IBr<"jbe", 0x86>, TB; def JA : IBr<"ja" , 0x87>, TB; @@ -274,21 +270,19 @@ //===----------------------------------------------------------------------===// // Move Instructions... // -def MOV8rr : I <"mov", 0x88, MRMDestReg>, Pattern<(set R8 , R8 )>; -def MOV16rr : I <"mov", 0x89, MRMDestReg>, OpSize, Pattern<(set R16, R16)>; -def MOV32rr : I <"mov", 0x89, MRMDestReg>, Pattern<(set R32, R32)>; -def MOV8ri : Ii8 <"mov", 0xB0, AddRegFrm >, Pattern<(set R8 , imm )>; -def MOV16ri : Ii16 <"mov", 0xB8, AddRegFrm >, OpSize, Pattern<(set R16, imm)>; -def MOV32ri : Ii32 <"mov", 0xB8, AddRegFrm >, Pattern<(set R32, imm)>; -def MOV8mi : Im8i8 <"mov", 0xC6, MRM0m >; // [mem8] = imm8 +def MOV8rr : I <"mov", 0x88, MRMDestReg>; +def MOV16rr : I <"mov", 0x89, MRMDestReg>, OpSize; +def MOV32rr : I <"mov", 0x89, MRMDestReg>; +def MOV8ri : Ii8 <"mov", 0xB0, AddRegFrm >; +def MOV16ri : Ii16 <"mov", 0xB8, AddRegFrm >, OpSize; +def MOV32ri : Ii32 <"mov", 0xB8, AddRegFrm >; +def MOV8mi : Im8i8 <"mov", 0xC6, MRM0m >; // [mem8] = imm8 def MOV16mi : Im16i16<"mov", 0xC7, MRM0m >, OpSize; // [mem16] = imm16 def MOV32mi : Im32i32<"mov", 0xC7, MRM0m >; // [mem32] = imm32 def MOV8rm : Im8 <"mov", 0x8A, MRMSrcMem>; // R8 = [mem8] -def MOV16rm : Im16 <"mov", 0x8B, MRMSrcMem>, OpSize, // R16 = [mem16] - Pattern<(set R16, (load (plus R32, (plus (times imm, R32), imm))))>; -def MOV32rm : Im32 <"mov", 0x8B, MRMSrcMem>, // R32 = [mem32] - Pattern<(set R32, (load (plus R32, (plus (times imm, R32), imm))))>; +def MOV16rm : Im16 <"mov", 0x8B, MRMSrcMem>, OpSize; // R16 = [mem16] +def MOV32rm : Im32 <"mov", 0x8B, MRMSrcMem>; // R32 = [mem32] def MOV8mr : Im8 <"mov", 0x88, MRMDestMem>; // [mem8] = R8 def MOV16mr : Im16 <"mov", 0x89, MRMDestMem>, OpSize; // [mem16] = R16 @@ -423,9 +417,9 @@ def DEC32m : Im32<"dec", 0xFF, MRM1m>; // --[mem32] // Logical operators... -def AND8rr : I <"and", 0x20, MRMDestReg>, Pattern<(set R8 , (and R8 , R8 ))>; -def AND16rr : I <"and", 0x21, MRMDestReg>, OpSize, Pattern<(set R16, (and R16, R16))>; -def AND32rr : I <"and", 0x21, MRMDestReg>, Pattern<(set R32, (and R32, R32))>; +def AND8rr : I <"and", 0x20, MRMDestReg>; +def AND16rr : I <"and", 0x21, MRMDestReg>, OpSize; +def AND32rr : I <"and", 0x21, MRMDestReg>; def AND8mr : Im8 <"and", 0x20, MRMDestMem>; // [mem8] &= R8 def AND16mr : Im16 <"and", 0x21, MRMDestMem>, OpSize; // [mem16] &= R16 def AND32mr : Im32 <"and", 0x21, MRMDestMem>; // [mem32] &= R32 @@ -433,9 +427,9 @@ def AND16rm : Im16 <"and", 0x23, MRMSrcMem >, OpSize; // R16 &= [mem16] def AND32rm : Im32 <"and", 0x23, MRMSrcMem >; // R32 &= [mem32] -def AND8ri : Ii8 <"and", 0x80, MRM4r >, Pattern<(set R8 , (and R8 , imm))>; -def AND16ri : Ii16 <"and", 0x81, MRM4r >, OpSize, Pattern<(set R16, (and R16, imm))>; -def AND32ri : Ii32 <"and", 0x81, MRM4r >, Pattern<(set R32, (and R32, imm))>; +def AND8ri : Ii8 <"and", 0x80, MRM4r >; +def AND16ri : Ii16 <"and", 0x81, MRM4r >, OpSize; +def AND32ri : Ii32 <"and", 0x81, MRM4r >; def AND8mi : Im8i8 <"and", 0x80, MRM4m >; // [mem8] &= imm8 def AND16mi : Im16i16<"and", 0x81, MRM4m >, OpSize; // [mem16] &= imm16 def AND32mi : Im32i32<"and", 0x81, MRM4m >; // [mem32] &= imm32 @@ -446,9 +440,9 @@ def AND32mi8 : Im32i8<"and", 0x83, MRM4m >; // [mem32] &= imm8 -def OR8rr : I <"or" , 0x08, MRMDestReg>, Pattern<(set R8 , (or R8 , R8 ))>; -def OR16rr : I <"or" , 0x09, MRMDestReg>, OpSize, Pattern<(set R16, (or R16, R16))>; -def OR32rr : I <"or" , 0x09, MRMDestReg>, Pattern<(set R32, (or R32, R32))>; +def OR8rr : I <"or" , 0x08, MRMDestReg>; +def OR16rr : I <"or" , 0x09, MRMDestReg>, OpSize; +def OR32rr : I <"or" , 0x09, MRMDestReg>; def OR8mr : Im8 <"or" , 0x08, MRMDestMem>; // [mem8] |= R8 def OR16mr : Im16 <"or" , 0x09, MRMDestMem>, OpSize; // [mem16] |= R16 def OR32mr : Im32 <"or" , 0x09, MRMDestMem>; // [mem32] |= R32 @@ -456,9 +450,9 @@ def OR16rm : Im16 <"or" , 0x0B, MRMSrcMem >, OpSize; // R16 |= [mem16] def OR32rm : Im32 <"or" , 0x0B, MRMSrcMem >; // R32 |= [mem32] -def OR8ri : Ii8 <"or" , 0x80, MRM1r >, Pattern<(set R8 , (or R8 , imm))>; -def OR16ri : Ii16 <"or" , 0x81, MRM1r >, OpSize, Pattern<(set R16, (or R16, imm))>; -def OR32ri : Ii32 <"or" , 0x81, MRM1r >, Pattern<(set R32, (or R32, imm))>; +def OR8ri : Ii8 <"or" , 0x80, MRM1r >; +def OR16ri : Ii16 <"or" , 0x81, MRM1r >, OpSize; +def OR32ri : Ii32 <"or" , 0x81, MRM1r >; def OR8mi : Im8i8 <"or" , 0x80, MRM1m >; // [mem8] |= imm8 def OR16mi : Im16i16<"or" , 0x81, MRM1m >, OpSize; // [mem16] |= imm16 def OR32mi : Im32i32<"or" , 0x81, MRM1m >; // [mem32] |= imm32 @@ -469,9 +463,9 @@ def OR32mi8 : Im32i8<"or" , 0x83, MRM1m >; // [mem32] |= imm8 -def XOR8rr : I <"xor", 0x30, MRMDestReg>, Pattern<(set R8 , (xor R8 , R8 ))>; -def XOR16rr : I <"xor", 0x31, MRMDestReg>, OpSize, Pattern<(set R16, (xor R16, R16))>; -def XOR32rr : I <"xor", 0x31, MRMDestReg>, Pattern<(set R32, (xor R32, R32))>; +def XOR8rr : I <"xor", 0x30, MRMDestReg>; +def XOR16rr : I <"xor", 0x31, MRMDestReg>, OpSize; +def XOR32rr : I <"xor", 0x31, MRMDestReg>; def XOR8mr : Im8 <"xor", 0x30, MRMDestMem>; // [mem8] ^= R8 def XOR16mr : Im16 <"xor", 0x31, MRMDestMem>, OpSize; // [mem16] ^= R16 def XOR32mr : Im32 <"xor", 0x31, MRMDestMem>; // [mem32] ^= R32 @@ -479,9 +473,9 @@ def XOR16rm : Im16 <"xor", 0x33, MRMSrcMem >, OpSize; // R16 ^= [mem16] def XOR32rm : Im32 <"xor", 0x33, MRMSrcMem >; // R32 ^= [mem32] -def XOR8ri : Ii8 <"xor", 0x80, MRM6r >, Pattern<(set R8 , (xor R8 , imm))>; -def XOR16ri : Ii16 <"xor", 0x81, MRM6r >, OpSize, Pattern<(set R16, (xor R16, imm))>; -def XOR32ri : Ii32 <"xor", 0x81, MRM6r >, Pattern<(set R32, (xor R32, imm))>; +def XOR8ri : Ii8 <"xor", 0x80, MRM6r >; +def XOR16ri : Ii16 <"xor", 0x81, MRM6r >, OpSize; +def XOR32ri : Ii32 <"xor", 0x81, MRM6r >; def XOR8mi : Im8i8 <"xor", 0x80, MRM6m >; // [mem8] ^= R8 def XOR16mi : Im16i16<"xor", 0x81, MRM6m >, OpSize; // [mem16] ^= R16 def XOR32mi : Im32i32<"xor", 0x81, MRM6m >; // [mem32] ^= R32 @@ -547,9 +541,9 @@ // Arithmetic... -def ADD8rr : I <"add", 0x00, MRMDestReg>, Pattern<(set R8 , (plus R8 , R8 ))>; -def ADD16rr : I <"add", 0x01, MRMDestReg>, OpSize, Pattern<(set R16, (plus R16, R16))>; -def ADD32rr : I <"add", 0x01, MRMDestReg>, Pattern<(set R32, (plus R32, R32))>; +def ADD8rr : I <"add", 0x00, MRMDestReg>; +def ADD16rr : I <"add", 0x01, MRMDestReg>, OpSize; +def ADD32rr : I <"add", 0x01, MRMDestReg>; def ADD8mr : Im8 <"add", 0x00, MRMDestMem>; // [mem8] += R8 def ADD16mr : Im16 <"add", 0x01, MRMDestMem>, OpSize; // [mem16] += R16 def ADD32mr : Im32 <"add", 0x01, MRMDestMem>; // [mem32] += R32 @@ -557,9 +551,9 @@ def ADD16rm : Im16 <"add", 0x03, MRMSrcMem >, OpSize; // R16 += [mem16] def ADD32rm : Im32 <"add", 0x03, MRMSrcMem >; // R32 += [mem32] -def ADD8ri : Ii8 <"add", 0x80, MRM0r >, Pattern<(set R8 , (plus R8 , imm))>; -def ADD16ri : Ii16 <"add", 0x81, MRM0r >, OpSize, Pattern<(set R16, (plus R16, imm))>; -def ADD32ri : Ii32 <"add", 0x81, MRM0r >, Pattern<(set R32, (plus R32, imm))>; +def ADD8ri : Ii8 <"add", 0x80, MRM0r >; +def ADD16ri : Ii16 <"add", 0x81, MRM0r >, OpSize; +def ADD32ri : Ii32 <"add", 0x81, MRM0r >; def ADD8mi : Im8i8 <"add", 0x80, MRM0m >; // [mem8] += I8 def ADD16mi : Im16i16<"add", 0x81, MRM0m >, OpSize; // [mem16] += I16 def ADD32mi : Im32i32<"add", 0x81, MRM0m >; // [mem32] += I32 @@ -577,9 +571,9 @@ def ADC32mi : Im32i32<"adc", 0x81, MRM2m >; // [mem32] += I32+Carry def ADC32mi8 : Im32i8 <"adc", 0x83, MRM2m >; // [mem32] += I8+Carry -def SUB8rr : I <"sub", 0x28, MRMDestReg>, Pattern<(set R8 , (minus R8 , R8 ))>; -def SUB16rr : I <"sub", 0x29, MRMDestReg>, OpSize, Pattern<(set R16, (minus R16, R16))>; -def SUB32rr : I <"sub", 0x29, MRMDestReg>, Pattern<(set R32, (minus R32, R32))>; +def SUB8rr : I <"sub", 0x28, MRMDestReg>; +def SUB16rr : I <"sub", 0x29, MRMDestReg>, OpSize; +def SUB32rr : I <"sub", 0x29, MRMDestReg>; def SUB8mr : Im8 <"sub", 0x28, MRMDestMem>; // [mem8] -= R8 def SUB16mr : Im16 <"sub", 0x29, MRMDestMem>, OpSize; // [mem16] -= R16 def SUB32mr : Im32 <"sub", 0x29, MRMDestMem>; // [mem32] -= R32 @@ -587,9 +581,9 @@ def SUB16rm : Im16 <"sub", 0x2B, MRMSrcMem >, OpSize; // R16 -= [mem16] def SUB32rm : Im32 <"sub", 0x2B, MRMSrcMem >; // R32 -= [mem32] -def SUB8ri : Ii8 <"sub", 0x80, MRM5r >, Pattern<(set R8 , (minus R8 , imm))>; -def SUB16ri : Ii16 <"sub", 0x81, MRM5r >, OpSize, Pattern<(set R16, (minus R16, imm))>; -def SUB32ri : Ii32 <"sub", 0x81, MRM5r >, Pattern<(set R32, (minus R32, imm))>; +def SUB8ri : Ii8 <"sub", 0x80, MRM5r >; +def SUB16ri : Ii16 <"sub", 0x81, MRM5r >, OpSize; +def SUB32ri : Ii32 <"sub", 0x81, MRM5r >; def SUB8mi : Im8i8 <"sub", 0x80, MRM5m >; // [mem8] -= I8 def SUB16mi : Im16i16<"sub", 0x81, MRM5m >, OpSize; // [mem16] -= I16 def SUB32mi : Im32i32<"sub", 0x81, MRM5m >; // [mem32] -= I32 @@ -607,8 +601,8 @@ def SBB32mi : Im32i32<"sbb", 0x81, MRM3m >; // [mem32] -= I32+Carry def SBB32mi8 : Im32i8 <"sbb", 0x83, MRM3m >; // [mem32] -= I8+Carry -def IMUL16rr : I <"imul", 0xAF, MRMSrcReg>, TB, OpSize, Pattern<(set R16, (times R16, R16))>; -def IMUL32rr : I <"imul", 0xAF, MRMSrcReg>, TB , Pattern<(set R32, (times R32, R32))>; +def IMUL16rr : I <"imul", 0xAF, MRMSrcReg>, TB, OpSize; +def IMUL32rr : I <"imul", 0xAF, MRMSrcReg>, TB; def IMUL16rm : Im16 <"imul", 0xAF, MRMSrcMem>, TB, OpSize; def IMUL32rm : Im32 <"imul", 0xAF, MRMSrcMem>, TB ; @@ -679,8 +673,7 @@ // Integer comparisons def CMP8rr : I <"cmp", 0x38, MRMDestReg>; // compare R8, R8 def CMP16rr : I <"cmp", 0x39, MRMDestReg>, OpSize; // compare R16, R16 -def CMP32rr : I <"cmp", 0x39, MRMDestReg>, // compare R32, R32 - Pattern<(isVoid (unspec2 R32, R32))>; +def CMP32rr : I <"cmp", 0x39, MRMDestReg>; // compare R32, R32 def CMP8mr : Im8 <"cmp", 0x38, MRMDestMem>; // compare [mem8], R8 def CMP16mr : Im16 <"cmp", 0x39, MRMDestMem>, OpSize; // compare [mem16], R16 def CMP32mr : Im32 <"cmp", 0x39, MRMDestMem>; // compare [mem32], R32 @@ -876,33 +869,3 @@ def FNSTSW8r : I <"fnstsw" , 0xE0, RawFrm>, DF, Imp<[],[AX]>; // AX = fp flags def FNSTCW16m : Im16<"fnstcw" , 0xD9, MRM7m >; // [mem16] = X87 control world def FLDCW16m : Im16<"fldcw" , 0xD9, MRM5m >; // X87 control world = [mem16] - - -//===----------------------------------------------------------------------===// -// Instruction Expanders -// - -def RET_R32 : Expander<(ret R32:$reg), - [(MOV32rr EAX, R32:$reg), - (RET)]>; - -// FIXME: This should eventually just be implemented by defining a frameidx as a -// value address for a load. -def LOAD_FI16 : Expander<(set R16:$dest, (load frameidx:$fi)), - [(MOV16rm R16:$dest, frameidx:$fi, 1, 0/*NoReg*/, 0)]>; - -def LOAD_FI32 : Expander<(set R32:$dest, (load frameidx:$fi)), - [(MOV32rm R32:$dest, frameidx:$fi, 1, 0/*NoReg*/, 0)]>; - - -def LOAD_R16 : Expander<(set R16:$dest, (load R32:$src)), - [(MOV16rm R16:$dest, R32:$src, 1, 0/*NoReg*/, 0)]>; - -def LOAD_R32 : Expander<(set R32:$dest, (load R32:$src)), - [(MOV32rm R32:$dest, R32:$src, 1, 0/*NoReg*/, 0)]>; - -def BR_EQ : Expander<(brcond (seteq R32:$a1, R32:$a2), - basicblock:$d1, basicblock:$d2), - [(CMP32rr R32:$a1, R32:$a2), - (JE basicblock:$d1), - (JMP basicblock:$d2)]>; From lattner at cs.uiuc.edu Sat Jul 31 22:28:12 2004 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Sat, 31 Jul 2004 22:28:12 -0500 Subject: [llvm-commits] CVS: llvm/lib/Target/X86/X86TargetMachine.cpp Message-ID: <200408010328.WAA03012@apoc.cs.uiuc.edu> Changes in directory llvm/lib/Target/X86: X86TargetMachine.cpp updated: 1.63 -> 1.64 --- Log message: Completely disable the pattern isel until it is more substantial. --- Diffs of the changes: (+4 -0) Index: llvm/lib/Target/X86/X86TargetMachine.cpp diff -u llvm/lib/Target/X86/X86TargetMachine.cpp:1.63 llvm/lib/Target/X86/X86TargetMachine.cpp:1.64 --- llvm/lib/Target/X86/X86TargetMachine.cpp:1.63 Thu Jul 22 16:30:35 2004 +++ llvm/lib/Target/X86/X86TargetMachine.cpp Sat Jul 31 22:28:02 2004 @@ -26,8 +26,12 @@ using namespace llvm; namespace { +#if 0 // FIXME: This will be used in the future. cl::opt NoPatternISel("disable-pattern-isel", cl::init(true), cl::desc("Use the 'simple' X86 instruction selector")); +#else + static const bool NoPatternISel = true; +#endif cl::opt NoSSAPeephole("disable-ssa-peephole", cl::init(true), cl::desc("Disable the ssa-based peephole optimizer " "(defaults to disabled)")); From lattner at cs.uiuc.edu Sat Jul 31 22:55:49 2004 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Sat, 31 Jul 2004 22:55:49 -0500 Subject: [llvm-commits] CVS: llvm/utils/TableGen/CodeEmitterGen.cpp CodeGenWrappers.cpp InstrInfoEmitter.cpp InstrSelectorEmitter.cpp Record.cpp RegisterInfoEmitter.cpp TableGen.cpp TableGenBackend.cpp Message-ID: <200408010355.WAA08326@apoc.cs.uiuc.edu> Changes in directory llvm/utils/TableGen: CodeEmitterGen.cpp updated: 1.29 -> 1.30 CodeGenWrappers.cpp updated: 1.7 -> 1.8 InstrInfoEmitter.cpp updated: 1.8 -> 1.9 InstrSelectorEmitter.cpp updated: 1.38 -> 1.39 Record.cpp updated: 1.34 -> 1.35 RegisterInfoEmitter.cpp updated: 1.15 -> 1.16 TableGen.cpp updated: 1.30 -> 1.31 TableGenBackend.cpp updated: 1.5 -> 1.6 --- Log message: Finegrainify namespacification --- Diffs of the changes: (+21 -41) Index: llvm/utils/TableGen/CodeEmitterGen.cpp diff -u llvm/utils/TableGen/CodeEmitterGen.cpp:1.29 llvm/utils/TableGen/CodeEmitterGen.cpp:1.30 --- llvm/utils/TableGen/CodeEmitterGen.cpp:1.29 Tue Nov 11 16:41:34 2003 +++ llvm/utils/TableGen/CodeEmitterGen.cpp Sat Jul 31 22:55:38 2004 @@ -14,8 +14,7 @@ #include "CodeEmitterGen.h" #include "Record.h" #include "Support/Debug.h" - -namespace llvm { +using namespace llvm; void CodeEmitterGen::run(std::ostream &o) { std::vector Insts = Records.getAllDerivedDefinitions("Instruction"); @@ -226,5 +225,3 @@ EmitSourceFileTail(o); } - -} // End llvm namespace Index: llvm/utils/TableGen/CodeGenWrappers.cpp diff -u llvm/utils/TableGen/CodeGenWrappers.cpp:1.7 llvm/utils/TableGen/CodeGenWrappers.cpp:1.8 --- llvm/utils/TableGen/CodeGenWrappers.cpp:1.7 Fri Jun 4 09:59:42 2004 +++ llvm/utils/TableGen/CodeGenWrappers.cpp Sat Jul 31 22:55:38 2004 @@ -16,16 +16,15 @@ #include "CodeGenWrappers.h" #include "Record.h" - -namespace llvm { +using namespace llvm; /// getValueType - Return the MCV::ValueType that the specified TableGen record /// corresponds to. -MVT::ValueType getValueType(Record *Rec) { +MVT::ValueType llvm::getValueType(Record *Rec) { return (MVT::ValueType)Rec->getValueAsInt("Value"); } -std::string getName(MVT::ValueType T) { +std::string llvm::getName(MVT::ValueType T) { switch (T) { case MVT::Other: return "UNKNOWN"; case MVT::i1: return "i1"; @@ -43,7 +42,7 @@ } } -std::string getEnumName(MVT::ValueType T) { +std::string llvm::getEnumName(MVT::ValueType T) { switch (T) { case MVT::Other: return "Other"; case MVT::i1: return "i1"; @@ -62,12 +61,11 @@ } -std::ostream &operator<<(std::ostream &OS, MVT::ValueType T) { +std::ostream &llvm::operator<<(std::ostream &OS, MVT::ValueType T) { return OS << getName(T); } - /// getTarget - Return the current instance of the Target class. /// CodeGenTarget::CodeGenTarget() : PointerType(MVT::Other) { @@ -99,4 +97,3 @@ return TargetRec->getValueAsDef("InstructionSet"); } -} // End llvm namespace Index: llvm/utils/TableGen/InstrInfoEmitter.cpp diff -u llvm/utils/TableGen/InstrInfoEmitter.cpp:1.8 llvm/utils/TableGen/InstrInfoEmitter.cpp:1.9 --- llvm/utils/TableGen/InstrInfoEmitter.cpp:1.8 Fri Jul 30 21:07:26 2004 +++ llvm/utils/TableGen/InstrInfoEmitter.cpp Sat Jul 31 22:55:38 2004 @@ -15,8 +15,7 @@ #include "InstrInfoEmitter.h" #include "CodeGenWrappers.h" #include "Record.h" - -namespace llvm { +using namespace llvm; // runEnums - Print out enum values for all of the instructions. void InstrInfoEmitter::runEnums(std::ostream &OS) { @@ -175,4 +174,3 @@ throw "In record '" + R->getName() + "' for TSFlag emission."; } -} // End llvm namespace Index: llvm/utils/TableGen/InstrSelectorEmitter.cpp diff -u llvm/utils/TableGen/InstrSelectorEmitter.cpp:1.38 llvm/utils/TableGen/InstrSelectorEmitter.cpp:1.39 --- llvm/utils/TableGen/InstrSelectorEmitter.cpp:1.38 Sat Jan 24 03:23:46 2004 +++ llvm/utils/TableGen/InstrSelectorEmitter.cpp Sat Jul 31 22:55:38 2004 @@ -18,8 +18,7 @@ #include "Support/Debug.h" #include "Support/StringExtras.h" #include - -namespace llvm { +using namespace llvm; NodeType::ArgResultTypes NodeType::Translate(Record *R) { const std::string &Name = R->getName(); @@ -104,7 +103,7 @@ return New; } -std::ostream &operator<<(std::ostream &OS, const TreePatternNode &N) { +std::ostream &llvm::operator<<(std::ostream &OS, const TreePatternNode &N) { if (N.isLeaf()) return OS << N.getType() << ":" << *N.getValue(); OS << "(" << N.getType() << ":"; @@ -359,7 +358,7 @@ -std::ostream &operator<<(std::ostream &OS, const Pattern &P) { +std::ostream &llvm::operator<<(std::ostream &OS, const Pattern &P) { switch (P.getPatternType()) { case Pattern::Nonterminal: OS << "Nonterminal pattern "; break; case Pattern::Instruction: OS << "Instruction pattern "; break; @@ -1296,4 +1295,3 @@ EmitSourceFileTail(OS); } -} // End llvm namespace Index: llvm/utils/TableGen/Record.cpp diff -u llvm/utils/TableGen/Record.cpp:1.34 llvm/utils/TableGen/Record.cpp:1.35 --- llvm/utils/TableGen/Record.cpp:1.34 Mon Jul 26 20:01:21 2004 +++ llvm/utils/TableGen/Record.cpp Sat Jul 31 22:55:38 2004 @@ -11,13 +11,12 @@ //===----------------------------------------------------------------------===// #include "Record.h" +using namespace llvm; //===----------------------------------------------------------------------===// // Type implementations //===----------------------------------------------------------------------===// -namespace llvm { - void RecTy::dump() const { print(std::cerr); } Init *BitRecTy::convertValue(BitsInit *BI) { @@ -568,7 +567,7 @@ void Record::dump() const { std::cerr << *this; } -std::ostream &operator<<(std::ostream &OS, const Record &R) { +std::ostream &llvm::operator<<(std::ostream &OS, const Record &R) { OS << R.getName(); const std::vector &TArgs = R.getTemplateArgs(); @@ -730,7 +729,7 @@ void RecordKeeper::dump() const { std::cerr << *this; } -std::ostream &operator<<(std::ostream &OS, const RecordKeeper &RK) { +std::ostream &llvm::operator<<(std::ostream &OS, const RecordKeeper &RK) { OS << "------------- Classes -----------------\n"; const std::map &Classes = RK.getClasses(); for (std::map::const_iterator I = Classes.begin(), @@ -764,4 +763,3 @@ return Defs; } -} // End llvm namespace Index: llvm/utils/TableGen/RegisterInfoEmitter.cpp diff -u llvm/utils/TableGen/RegisterInfoEmitter.cpp:1.15 llvm/utils/TableGen/RegisterInfoEmitter.cpp:1.16 --- llvm/utils/TableGen/RegisterInfoEmitter.cpp:1.15 Tue Nov 11 16:41:34 2003 +++ llvm/utils/TableGen/RegisterInfoEmitter.cpp Sat Jul 31 22:55:38 2004 @@ -18,8 +18,7 @@ #include "Record.h" #include "Support/StringExtras.h" #include - -namespace llvm { +using namespace llvm; // runEnums - Print out enum values for all of the registers. void RegisterInfoEmitter::runEnums(std::ostream &OS) { @@ -246,5 +245,3 @@ OS << " 0\n };\n return CalleeSaveRegs;\n}\n\n"; EmitSourceFileTail(OS); } - -} // End llvm namespace Index: llvm/utils/TableGen/TableGen.cpp diff -u llvm/utils/TableGen/TableGen.cpp:1.30 llvm/utils/TableGen/TableGen.cpp:1.31 --- llvm/utils/TableGen/TableGen.cpp:1.30 Thu Jul 22 16:32:38 2004 +++ llvm/utils/TableGen/TableGen.cpp Sat Jul 31 22:55:38 2004 @@ -26,8 +26,7 @@ #include #include #include - -namespace llvm { +using namespace llvm; enum ActionType { PrintRecords, @@ -79,10 +78,12 @@ cl::value_desc("directory"), cl::init("")); } +namespace llvm { + void ParseFile(const std::string &Filename, + const std::string &IncludeDir); +} -void ParseFile(const std::string &Filename, const std::string & IncludeDir); - -RecordKeeper Records; +RecordKeeper llvm::Records; static Init *getBit(Record *R, unsigned BitNo) { const std::vector &V = R->getValues(); @@ -408,10 +409,6 @@ } } -} // End llvm namespace - -using namespace llvm; - int main(int argc, char **argv) { cl::ParseCommandLineOptions(argc, argv); ParseFile(InputFilename, IncludeDir); Index: llvm/utils/TableGen/TableGenBackend.cpp diff -u llvm/utils/TableGen/TableGenBackend.cpp:1.5 llvm/utils/TableGen/TableGenBackend.cpp:1.6 --- llvm/utils/TableGen/TableGenBackend.cpp:1.5 Tue Nov 11 16:41:34 2003 +++ llvm/utils/TableGen/TableGenBackend.cpp Sat Jul 31 22:55:39 2004 @@ -14,8 +14,7 @@ #include "TableGenBackend.h" #include "Record.h" #include - -namespace llvm { +using namespace llvm; void TableGenBackend::EmitSourceFileHeader(const std::string &Desc, std::ostream &OS) const { @@ -38,4 +37,3 @@ return Namespace + "::" + R->getName(); } -} // End llvm namespace From lattner at cs.uiuc.edu Sat Jul 31 23:04:46 2004 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Sat, 31 Jul 2004 23:04:46 -0500 Subject: [llvm-commits] CVS: llvm/utils/TableGen/CodeGenTarget.cpp CodeGenTarget.h InstrInfoEmitter.cpp InstrSelectorEmitter.cpp InstrSelectorEmitter.h RegisterInfoEmitter.cpp CodeGenWrappers.cpp CodeGenWrappers.h Message-ID: <200408010404.XAA09302@apoc.cs.uiuc.edu> Changes in directory llvm/utils/TableGen: CodeGenTarget.cpp updated: 1.8 -> 1.9 CodeGenTarget.h updated: 1.7 -> 1.8 InstrInfoEmitter.cpp updated: 1.9 -> 1.10 InstrSelectorEmitter.cpp updated: 1.39 -> 1.40 InstrSelectorEmitter.h updated: 1.23 -> 1.24 RegisterInfoEmitter.cpp updated: 1.16 -> 1.17 CodeGenWrappers.cpp (r1.8) removed CodeGenWrappers.h (r1.7) removed --- Log message: Rename CodeGenWrappers.(cpp|h) -> CodeGenTarget.(cpp|h) --- Diffs of the changes: (+13 -14) Index: llvm/utils/TableGen/CodeGenTarget.cpp diff -u llvm/utils/TableGen/CodeGenTarget.cpp:1.8 llvm/utils/TableGen/CodeGenTarget.cpp:1.9 --- llvm/utils/TableGen/CodeGenTarget.cpp:1.8 Sat Jul 31 22:55:38 2004 +++ llvm/utils/TableGen/CodeGenTarget.cpp Sat Jul 31 23:04:35 2004 @@ -1,4 +1,4 @@ -//===- CodeGenWrappers.cpp - Code Generation Class Wrappers -----*- C++ -*-===// +//===- CodeGenTarget.cpp - CodeGen Target Class Wrapper ---------*- C++ -*-===// // // The LLVM Compiler Infrastructure // @@ -7,14 +7,14 @@ // //===----------------------------------------------------------------------===// // -// These classes wrap target description classes used by the various code +// This class wrap target description classes used by the various code // generation TableGen backends. This makes it easier to access the data and // provides a single place that needs to check it for validity. All of these // classes throw exceptions on error conditions. // //===----------------------------------------------------------------------===// -#include "CodeGenWrappers.h" +#include "CodeGenTarget.h" #include "Record.h" using namespace llvm; Index: llvm/utils/TableGen/CodeGenTarget.h diff -u llvm/utils/TableGen/CodeGenTarget.h:1.7 llvm/utils/TableGen/CodeGenTarget.h:1.8 --- llvm/utils/TableGen/CodeGenTarget.h:1.7 Tue Nov 11 16:41:34 2003 +++ llvm/utils/TableGen/CodeGenTarget.h Sat Jul 31 23:04:35 2004 @@ -1,4 +1,4 @@ -//===- CodeGenWrappers.h - Code Generation Class Wrappers -------*- C++ -*-===// +//===- CodeGenTarget.h - Target Class Wrapper -------------------*- C++ -*-===// // // The LLVM Compiler Infrastructure // @@ -7,15 +7,15 @@ // //===----------------------------------------------------------------------===// // -// These classes wrap target description classes used by the various code -// generation TableGen backends. This makes it easier to access the data and -// provides a single place that needs to check it for validity. All of these -// classes throw exceptions on error conditions. +// This file defines wrappers for the Target class and related global +// functionality. This makes it easier to access the data and provides a single +// place that needs to check it for validity. All of these classes throw +// exceptions on error conditions. // //===----------------------------------------------------------------------===// -#ifndef CODEGENWRAPPERS_H -#define CODEGENWRAPPERS_H +#ifndef CODEGEN_TARGET_H +#define CODEGEN_TARGET_H #include "llvm/CodeGen/ValueTypes.h" #include Index: llvm/utils/TableGen/InstrInfoEmitter.cpp diff -u llvm/utils/TableGen/InstrInfoEmitter.cpp:1.9 llvm/utils/TableGen/InstrInfoEmitter.cpp:1.10 --- llvm/utils/TableGen/InstrInfoEmitter.cpp:1.9 Sat Jul 31 22:55:38 2004 +++ llvm/utils/TableGen/InstrInfoEmitter.cpp Sat Jul 31 23:04:35 2004 @@ -13,7 +13,7 @@ //===----------------------------------------------------------------------===// #include "InstrInfoEmitter.h" -#include "CodeGenWrappers.h" +#include "CodeGenTarget.h" #include "Record.h" using namespace llvm; Index: llvm/utils/TableGen/InstrSelectorEmitter.cpp diff -u llvm/utils/TableGen/InstrSelectorEmitter.cpp:1.39 llvm/utils/TableGen/InstrSelectorEmitter.cpp:1.40 --- llvm/utils/TableGen/InstrSelectorEmitter.cpp:1.39 Sat Jul 31 22:55:38 2004 +++ llvm/utils/TableGen/InstrSelectorEmitter.cpp Sat Jul 31 23:04:35 2004 @@ -13,7 +13,6 @@ //===----------------------------------------------------------------------===// #include "InstrSelectorEmitter.h" -#include "CodeGenWrappers.h" #include "Record.h" #include "Support/Debug.h" #include "Support/StringExtras.h" Index: llvm/utils/TableGen/InstrSelectorEmitter.h diff -u llvm/utils/TableGen/InstrSelectorEmitter.h:1.23 llvm/utils/TableGen/InstrSelectorEmitter.h:1.24 --- llvm/utils/TableGen/InstrSelectorEmitter.h:1.23 Tue Nov 11 16:41:34 2003 +++ llvm/utils/TableGen/InstrSelectorEmitter.h Sat Jul 31 23:04:35 2004 @@ -16,7 +16,7 @@ #define INSTRSELECTOR_EMITTER_H #include "TableGenBackend.h" -#include "CodeGenWrappers.h" +#include "CodeGenTarget.h" #include #include #include Index: llvm/utils/TableGen/RegisterInfoEmitter.cpp diff -u llvm/utils/TableGen/RegisterInfoEmitter.cpp:1.16 llvm/utils/TableGen/RegisterInfoEmitter.cpp:1.17 --- llvm/utils/TableGen/RegisterInfoEmitter.cpp:1.16 Sat Jul 31 22:55:38 2004 +++ llvm/utils/TableGen/RegisterInfoEmitter.cpp Sat Jul 31 23:04:35 2004 @@ -14,7 +14,7 @@ //===----------------------------------------------------------------------===// #include "RegisterInfoEmitter.h" -#include "CodeGenWrappers.h" +#include "CodeGenTarget.h" #include "Record.h" #include "Support/StringExtras.h" #include From lattner at cs.uiuc.edu Sat Jul 31 23:40:53 2004 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Sat, 31 Jul 2004 23:40:53 -0500 Subject: [llvm-commits] CVS: llvm/lib/Target/Target.td Message-ID: <200408010440.XAA14049@apoc.cs.uiuc.edu> Changes in directory llvm/lib/Target: Target.td updated: 1.27 -> 1.28 --- Log message: Add the 'ops' marker, add an AsmString initializer --- Diffs of the changes: (+6 -1) Index: llvm/lib/Target/Target.td diff -u llvm/lib/Target/Target.td:1.27 llvm/lib/Target/Target.td:1.28 --- llvm/lib/Target/Target.td:1.27 Sat Jul 31 22:23:34 2004 +++ llvm/lib/Target/Target.td Sat Jul 31 23:40:43 2004 @@ -110,7 +110,7 @@ string Namespace = ""; dag OperandList; // An dag containing the MI operand list. - string AsmString; // The .s format to print the instruction with. + string AsmString = ""; // The .s format to print the instruction with. // Pattern - Set to the DAG pattern for this instruction, if we know of one, // otherwise, uninitialized. @@ -147,6 +147,11 @@ list TSFlagsShifts = []; } +/// ops definition - This is just a simple marker used to identify the operands +/// list for an instruction. This should be used like this: +/// (ops R32:$dst, R32:$src) or something similar. +def ops; + //===----------------------------------------------------------------------===// // Target - This class contains the "global" target information From lattner at cs.uiuc.edu Sun Aug 1 00:02:50 2004 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Sun, 1 Aug 2004 00:02:50 -0500 Subject: [llvm-commits] CVS: llvm/test/Programs/SingleSource/Benchmarks/Shootout-C++/Makefile Message-ID: <200408010502.AAA20056@apoc.cs.uiuc.edu> Changes in directory llvm/test/Programs/SingleSource/Benchmarks/Shootout-C++: Makefile updated: 1.9 -> 1.10 --- Log message: Allow moments to pass --- Diffs of the changes: (+1 -0) Index: llvm/test/Programs/SingleSource/Benchmarks/Shootout-C++/Makefile diff -u llvm/test/Programs/SingleSource/Benchmarks/Shootout-C++/Makefile:1.9 llvm/test/Programs/SingleSource/Benchmarks/Shootout-C++/Makefile:1.10 --- llvm/test/Programs/SingleSource/Benchmarks/Shootout-C++/Makefile:1.9 Sun Feb 8 16:48:53 2004 +++ llvm/test/Programs/SingleSource/Benchmarks/Shootout-C++/Makefile Sun Aug 1 00:02:39 2004 @@ -4,5 +4,6 @@ LDFLAGS += -lm LIBS += -lstdc++ REQUIRES_EH_SUPPORT=1 +FP_TOLERANCE = 0.00000001 include $(LEVEL)/test/Programs/SingleSource/Makefile.singlesrc From lattner at cs.uiuc.edu Sun Aug 1 00:04:10 2004 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Sun, 1 Aug 2004 00:04:10 -0500 Subject: [llvm-commits] CVS: llvm/utils/TableGen/CodeGenInstruction.h CodeGenTarget.cpp CodeGenTarget.h InstrInfoEmitter.cpp InstrInfoEmitter.h Message-ID: <200408010504.AAA22394@apoc.cs.uiuc.edu> Changes in directory llvm/utils/TableGen: CodeGenInstruction.h added (r1.1) CodeGenTarget.cpp updated: 1.9 -> 1.10 CodeGenTarget.h updated: 1.8 -> 1.9 InstrInfoEmitter.cpp updated: 1.10 -> 1.11 InstrInfoEmitter.h updated: 1.5 -> 1.6 --- Log message: Add, and start using, the CodeGenInstruction class. This class represents an instance of the Instruction tablegen class. --- Diffs of the changes: (+144 -47) Index: llvm/utils/TableGen/CodeGenInstruction.h diff -c /dev/null llvm/utils/TableGen/CodeGenInstruction.h:1.1 *** /dev/null Sun Aug 1 00:04:10 2004 --- llvm/utils/TableGen/CodeGenInstruction.h Sun Aug 1 00:04:00 2004 *************** *** 0 **** --- 1,49 ---- + //===- CodeGenInstruction.h - Instruction Class Wrapper ---------*- C++ -*-===// + // + // The LLVM Compiler Infrastructure + // + // This file was developed by the LLVM research group and is distributed under + // the University of Illinois Open Source License. See LICENSE.TXT for details. + // + //===----------------------------------------------------------------------===// + // + // This file defines a wrapper class for the 'Instruction' TableGen class. + // + //===----------------------------------------------------------------------===// + + #ifndef CODEGEN_INSTRUCTION_H + #define CODEGEN_INSTRUCTION_H + + #include + #include + #include + + namespace llvm { + class Record; + + struct CodeGenInstruction { + Record *TheDef; // The actual record defining this instruction. + std::string Name; // Contents of the 'Name' field. + std::string Namespace; // The namespace the instruction is in. + + /// AsmString - The format string used to emit a .s file for the + /// instruction. + std::string AsmString; + + /// OperandList - The list of declared operands, along with their declared + /// type (which is a record). + std::vector > OperandList; + + // Various boolean values we track for the instruction. + bool isReturn; + bool isBranch; + bool isBarrier; + bool isCall; + bool isTwoAddress; + bool isTerminator; + + CodeGenInstruction(Record *R); + }; + } + + #endif Index: llvm/utils/TableGen/CodeGenTarget.cpp diff -u llvm/utils/TableGen/CodeGenTarget.cpp:1.9 llvm/utils/TableGen/CodeGenTarget.cpp:1.10 --- llvm/utils/TableGen/CodeGenTarget.cpp:1.9 Sat Jul 31 23:04:35 2004 +++ llvm/utils/TableGen/CodeGenTarget.cpp Sun Aug 1 00:04:00 2004 @@ -97,3 +97,39 @@ return TargetRec->getValueAsDef("InstructionSet"); } +void CodeGenTarget::ReadInstructions() const { + std::vector Insts = Records.getAllDerivedDefinitions("Instruction"); + + if (Insts.size() == 0) + throw std::string("No 'Instruction' subclasses defined!"); + + for (unsigned i = 0, e = Insts.size(); i != e; ++i) + Instructions.insert(std::make_pair(Insts[i]->getName(), Insts[i])); +} + +/// getPHIInstruction - Return the designated PHI instruction. +const CodeGenInstruction &CodeGenTarget::getPHIInstruction() const { + Record *PHI = getInstructionSet()->getValueAsDef("PHIInst"); + std::map::const_iterator I = + getInstructions().find(PHI->getName()); + if (I == Instructions.end()) + throw "Could not find PHI instruction named '" + PHI->getName() + "'!"; + return I->second; +} + +CodeGenInstruction::CodeGenInstruction(Record *R) : TheDef(R) { + Name = R->getValueAsString("Name"); + Namespace = R->getValueAsString("Namespace"); + AsmString = R->getValueAsString("AsmString"); + + //TODO: Parse OperandList + + isReturn = R->getValueAsBit("isReturn"); + isBranch = R->getValueAsBit("isBranch"); + isBarrier = R->getValueAsBit("isBarrier"); + isCall = R->getValueAsBit("isCall"); + isTwoAddress = R->getValueAsBit("isTwoAddress"); + isTerminator = R->getValueAsBit("isTerminator"); +} + + Index: llvm/utils/TableGen/CodeGenTarget.h diff -u llvm/utils/TableGen/CodeGenTarget.h:1.8 llvm/utils/TableGen/CodeGenTarget.h:1.9 --- llvm/utils/TableGen/CodeGenTarget.h:1.8 Sat Jul 31 23:04:35 2004 +++ llvm/utils/TableGen/CodeGenTarget.h Sun Aug 1 00:04:00 2004 @@ -17,10 +17,10 @@ #ifndef CODEGEN_TARGET_H #define CODEGEN_TARGET_H +#include "CodeGenInstruction.h" #include "llvm/CodeGen/ValueTypes.h" #include -#include -#include +#include namespace llvm { @@ -43,6 +43,8 @@ std::vector CalleeSavedRegisters; MVT::ValueType PointerType; + mutable std::map Instructions; + void ReadInstructions() const; public: CodeGenTarget(); @@ -55,12 +57,24 @@ MVT::ValueType getPointerType() const { return PointerType; } - // getInstructionSet - Return the InstructionSet object... + // getInstructionSet - Return the InstructionSet object. + /// Record *getInstructionSet() const; - // getInstructionSet - Return the CodeGenInstructionSet object for this - // target, lazily reading it from the record keeper as needed. - // CodeGenInstructionSet *getInstructionSet - + /// getPHIInstruction - Return the designated PHI instruction. + const CodeGenInstruction &getPHIInstruction() const; + + /// getInstructions - Return all of the instructions defined for this target. + /// + const std::map &getInstructions() const { + if (Instructions.empty()) ReadInstructions(); + return Instructions; + } + + typedef std::map::const_iterator inst_iterator; + inst_iterator inst_begin() const { return getInstructions().begin(); } + inst_iterator inst_end() const { return Instructions.end(); } }; } // End llvm namespace Index: llvm/utils/TableGen/InstrInfoEmitter.cpp diff -u llvm/utils/TableGen/InstrInfoEmitter.cpp:1.10 llvm/utils/TableGen/InstrInfoEmitter.cpp:1.11 --- llvm/utils/TableGen/InstrInfoEmitter.cpp:1.10 Sat Jul 31 23:04:35 2004 +++ llvm/utils/TableGen/InstrInfoEmitter.cpp Sun Aug 1 00:04:00 2004 @@ -19,31 +19,28 @@ // runEnums - Print out enum values for all of the instructions. void InstrInfoEmitter::runEnums(std::ostream &OS) { - std::vector Insts = Records.getAllDerivedDefinitions("Instruction"); - - if (Insts.size() == 0) - throw std::string("No 'Instruction' subclasses defined!"); - - std::string Namespace = Insts[0]->getValueAsString("Namespace"); - EmitSourceFileHeader("Target Instruction Enum Values", OS); - if (!Namespace.empty()) - OS << "namespace " << Namespace << " {\n"; - OS << " enum {\n"; - CodeGenTarget Target; // We must emit the PHI opcode first... Record *InstrInfo = Target.getInstructionSet(); Record *PHI = InstrInfo->getValueAsDef("PHIInst"); + std::string Namespace = Target.inst_begin()->second.Namespace; + + if (!Namespace.empty()) + OS << "namespace " << Namespace << " {\n"; + OS << " enum {\n"; + OS << " " << PHI->getName() << ", \t// 0 (fixed for all targets)\n"; - // Print out the rest of the instructions now... - for (unsigned i = 0, e = Insts.size(); i != e; ++i) - if (Insts[i] != PHI) - OS << " " << Insts[i]->getName() << ", \t// " << i+1 << "\n"; + // Print out the rest of the instructions now. + unsigned i = 0; + for (CodeGenTarget::inst_iterator II = Target.inst_begin(), + E = Target.inst_end(); II != E; ++II) + if (II->second.TheDef != PHI) + OS << " " << II->first << ", \t// " << ++i << "\n"; OS << " };\n"; if (!Namespace.empty()) @@ -71,16 +68,14 @@ Record *InstrInfo = Target.getInstructionSet(); Record *PHI = InstrInfo->getValueAsDef("PHIInst"); - std::vector Instructions = - Records.getAllDerivedDefinitions("Instruction"); - // Emit empty implicit uses and defs lists OS << "static const unsigned EmptyImpUses[] = { 0 };\n" << "static const unsigned EmptyImpDefs[] = { 0 };\n"; // Emit all of the instruction's implicit uses and defs... - for (unsigned i = 0, e = Instructions.size(); i != e; ++i) { - Record *Inst = Instructions[i]; + for (CodeGenTarget::inst_iterator II = Target.inst_begin(), + E = Target.inst_end(); II != E; ++II) { + Record *Inst = II->second.TheDef; ListInit *LI = Inst->getValueAsListInit("Uses"); if (LI->getSize()) printDefList(LI, Inst->getName()+"ImpUses", OS); LI = Inst->getValueAsListInit("Defs"); @@ -89,27 +84,28 @@ OS << "\nstatic const TargetInstrDescriptor " << TargetName << "Insts[] = {\n"; - emitRecord(PHI, 0, InstrInfo, OS); + emitRecord(Target.getPHIInstruction(), 0, InstrInfo, OS); - for (unsigned i = 0, e = Instructions.size(); i != e; ++i) - if (Instructions[i] != PHI) - emitRecord(Instructions[i], i+1, InstrInfo, OS); + unsigned i = 0; + for (CodeGenTarget::inst_iterator II = Target.inst_begin(), + E = Target.inst_end(); II != E; ++II) + if (II->second.TheDef != PHI) + emitRecord(II->second, ++i, InstrInfo, OS); OS << "};\n"; EmitSourceFileTail(OS); } -void InstrInfoEmitter::emitRecord(Record *R, unsigned Num, Record *InstrInfo, - std::ostream &OS) { - OS << " { \"" << R->getValueAsString("Name") - << "\",\t-1, -1, 0, false, 0, 0, 0, 0"; +void InstrInfoEmitter::emitRecord(const CodeGenInstruction &Inst, unsigned Num, + Record *InstrInfo, std::ostream &OS) { + OS << " { \"" << Inst.Name << "\",\t-1, -1, 0, false, 0, 0, 0, 0"; // Emit all of the target indepedent flags... - if (R->getValueAsBit("isReturn")) OS << "|M_RET_FLAG"; - if (R->getValueAsBit("isBranch")) OS << "|M_BRANCH_FLAG"; - if (R->getValueAsBit("isBarrier")) OS << "|M_BARRIER_FLAG"; - if (R->getValueAsBit("isCall" )) OS << "|M_CALL_FLAG"; - if (R->getValueAsBit("isTwoAddress")) OS << "|M_2_ADDR_FLAG"; - if (R->getValueAsBit("isTerminator")) OS << "|M_TERMINATOR_FLAG"; + if (Inst.isReturn) OS << "|M_RET_FLAG"; + if (Inst.isBranch) OS << "|M_BRANCH_FLAG"; + if (Inst.isBarrier) OS << "|M_BARRIER_FLAG"; + if (Inst.isCall) OS << "|M_CALL_FLAG"; + if (Inst.isTwoAddress) OS << "|M_2_ADDR_FLAG"; + if (Inst.isTerminator) OS << "|M_TERMINATOR_FLAG"; OS << ", 0"; // Emit all of the target-specific flags... @@ -120,25 +116,25 @@ ":(TargetInfoFields, TargetInfoPositions) must be equal!"; for (unsigned i = 0, e = LI->getSize(); i != e; ++i) - emitShiftedValue(R, dynamic_cast(LI->getElement(i)), + emitShiftedValue(Inst.TheDef, dynamic_cast(LI->getElement(i)), dynamic_cast(Shift->getElement(i)), OS); OS << ", "; // Emit the implicit uses and defs lists... - LI = R->getValueAsListInit("Uses"); + LI = Inst.TheDef->getValueAsListInit("Uses"); if (!LI->getSize()) OS << "EmptyImpUses, "; else - OS << R->getName() << "ImpUses, "; + OS << Inst.TheDef->getName() << "ImpUses, "; - LI = R->getValueAsListInit("Defs"); + LI = Inst.TheDef->getValueAsListInit("Defs"); if (!LI->getSize()) OS << "EmptyImpDefs "; else - OS << R->getName() << "ImpDefs "; + OS << Inst.TheDef->getName() << "ImpDefs "; - OS << " }, // Inst #" << Num << " = " << R->getName() << "\n"; + OS << " }, // Inst #" << Num << " = " << Inst.TheDef->getName() << "\n"; } void InstrInfoEmitter::emitShiftedValue(Record *R, StringInit *Val, Index: llvm/utils/TableGen/InstrInfoEmitter.h diff -u llvm/utils/TableGen/InstrInfoEmitter.h:1.5 llvm/utils/TableGen/InstrInfoEmitter.h:1.6 --- llvm/utils/TableGen/InstrInfoEmitter.h:1.5 Tue Nov 11 16:41:34 2003 +++ llvm/utils/TableGen/InstrInfoEmitter.h Sun Aug 1 00:04:00 2004 @@ -22,6 +22,7 @@ class StringInit; class IntInit; class ListInit; +class CodeGenInstruction; class InstrInfoEmitter : public TableGenBackend { RecordKeeper &Records; @@ -36,7 +37,8 @@ private: void printDefList(ListInit *LI, const std::string &Name, std::ostream &OS) const; - void emitRecord(Record *R, unsigned Num, Record *InstrInfo, std::ostream &OS); + void emitRecord(const CodeGenInstruction &Inst, unsigned Num, + Record *InstrInfo, std::ostream &OS); void emitShiftedValue(Record *R, StringInit *Val, IntInit *Shift, std::ostream &OS); }; From lattner at cs.uiuc.edu Sun Aug 1 00:59:43 2004 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Sun, 1 Aug 2004 00:59:43 -0500 Subject: [llvm-commits] CVS: llvm/utils/TableGen/AsmWriterEmitter.cpp AsmWriterEmitter.h CodeGenTarget.cpp TableGen.cpp Message-ID: <200408010559.AAA00988@apoc.cs.uiuc.edu> Changes in directory llvm/utils/TableGen: AsmWriterEmitter.cpp added (r1.1) AsmWriterEmitter.h added (r1.1) CodeGenTarget.cpp updated: 1.10 -> 1.11 TableGen.cpp updated: 1.31 -> 1.32 --- Log message: Initial cut at an asm writer emitter. So far, this only handles emission of instructions, and only instructions that take no operands at that! --- Diffs of the changes: (+99 -3) Index: llvm/utils/TableGen/AsmWriterEmitter.cpp diff -c /dev/null llvm/utils/TableGen/AsmWriterEmitter.cpp:1.1 *** /dev/null Sun Aug 1 00:59:43 2004 --- llvm/utils/TableGen/AsmWriterEmitter.cpp Sun Aug 1 00:59:33 2004 *************** *** 0 **** --- 1,48 ---- + //===- AsmWriterEmitter.cpp - Generate an assembly writer -----------------===// + // + // The LLVM Compiler Infrastructure + // + // This file was developed by the LLVM research group and is distributed under + // the University of Illinois Open Source License. See LICENSE.TXT for details. + // + //===----------------------------------------------------------------------===// + // + // This tablegen backend is emits an assembly printer for the current target. + // Note that this is currently fairly skeletal, but will grow over time. + // + //===----------------------------------------------------------------------===// + + #include "AsmWriterEmitter.h" + #include "CodeGenTarget.h" + #include + using namespace llvm; + + void AsmWriterEmitter::run(std::ostream &O) { + EmitSourceFileHeader("Assembly Writer Source Fragment", O); + + CodeGenTarget Target; + O << + "/// printInstruction - This method is automatically generated by tablegen\n" + "/// from the instruction set description. This method returns true if the\n" + "/// machine instruction was sufficiently described to print it, otherwise\n" + "/// it returns false.\n" + "bool " << Target.getName() + << "AsmPrinter::printInstruction(const MachineInstr *MI) {\n"; + O << " switch (MI->getOpcode()) {\n" + " default: return false;\n"; + + std::string Namespace = Target.inst_begin()->second.Namespace; + + for (CodeGenTarget::inst_iterator I = Target.inst_begin(), + E = Target.inst_end(); I != E; ++I) + if (!I->second.AsmString.empty()) { + const std::string &AsmString = I->second.AsmString; + O << " case " << Namespace << "::" << I->first << ": O << \"" + << AsmString << "\" << '\\n'; break;\n"; + } + + O << " }\n" + " return true;\n" + "}\n"; + EmitSourceFileTail(O); + } Index: llvm/utils/TableGen/AsmWriterEmitter.h diff -c /dev/null llvm/utils/TableGen/AsmWriterEmitter.h:1.1 *** /dev/null Sun Aug 1 00:59:43 2004 --- llvm/utils/TableGen/AsmWriterEmitter.h Sun Aug 1 00:59:33 2004 *************** *** 0 **** --- 1,31 ---- + //===- AsmWriterEmitter.h - Generate an assembly writer ---------*- C++ -*-===// + // + // The LLVM Compiler Infrastructure + // + // This file was developed by the LLVM research group and is distributed under + // the University of Illinois Open Source License. See LICENSE.TXT for details. + // + //===----------------------------------------------------------------------===// + // + // This tablegen backend is responsible for emitting an assembly printer for the + // code generator. + // + //===----------------------------------------------------------------------===// + + #ifndef ASMWRITER_EMITTER_H + #define ASMWRITER_EMITTER_H + + #include "TableGenBackend.h" + + namespace llvm { + + class AsmWriterEmitter : public TableGenBackend { + RecordKeeper &Records; + public: + AsmWriterEmitter(RecordKeeper &R) : Records(R) {} + + // run - Output the asmwriter, returning true on failure. + void run(std::ostream &o); + }; + } + #endif Index: llvm/utils/TableGen/CodeGenTarget.cpp diff -u llvm/utils/TableGen/CodeGenTarget.cpp:1.10 llvm/utils/TableGen/CodeGenTarget.cpp:1.11 --- llvm/utils/TableGen/CodeGenTarget.cpp:1.10 Sun Aug 1 00:04:00 2004 +++ llvm/utils/TableGen/CodeGenTarget.cpp Sun Aug 1 00:59:33 2004 @@ -122,14 +122,23 @@ Namespace = R->getValueAsString("Namespace"); AsmString = R->getValueAsString("AsmString"); - //TODO: Parse OperandList - isReturn = R->getValueAsBit("isReturn"); isBranch = R->getValueAsBit("isBranch"); isBarrier = R->getValueAsBit("isBarrier"); isCall = R->getValueAsBit("isCall"); isTwoAddress = R->getValueAsBit("isTwoAddress"); isTerminator = R->getValueAsBit("isTerminator"); + + + //TODO: Parse OperandList + try { + DagInit *DI = R->getValueAsDag("OperandList"); + + // Cannot handle instructions with operands yet. + if (DI->getNumArgs()) + AsmString.clear(); + } catch (...) { + } } Index: llvm/utils/TableGen/TableGen.cpp diff -u llvm/utils/TableGen/TableGen.cpp:1.31 llvm/utils/TableGen/TableGen.cpp:1.32 --- llvm/utils/TableGen/TableGen.cpp:1.31 Sat Jul 31 22:55:38 2004 +++ llvm/utils/TableGen/TableGen.cpp Sun Aug 1 00:59:33 2004 @@ -22,6 +22,7 @@ #include "CodeEmitterGen.h" #include "RegisterInfoEmitter.h" #include "InstrInfoEmitter.h" +#include "AsmWriterEmitter.h" #include "InstrSelectorEmitter.h" #include #include @@ -32,7 +33,7 @@ PrintRecords, GenEmitter, GenRegisterEnums, GenRegister, GenRegisterHeader, - GenInstrEnums, GenInstrs, GenInstrSelector, + GenInstrEnums, GenInstrs, GenAsmWriter, GenInstrSelector, PrintEnums, Parse }; @@ -54,6 +55,8 @@ "Generate enum values for instructions"), clEnumValN(GenInstrs, "gen-instr-desc", "Generate instruction descriptions"), + clEnumValN(GenAsmWriter, "gen-asm-writer", + "Generate assembly writer"), clEnumValN(GenInstrSelector, "gen-instr-selector", "Generate an instruction selector"), clEnumValN(PrintEnums, "print-enums", @@ -454,6 +457,11 @@ case GenInstrs: InstrInfoEmitter(Records).run(*Out); break; + + case GenAsmWriter: + AsmWriterEmitter(Records).run(*Out); + break; + case GenInstrSelector: InstrSelectorEmitter(Records).run(*Out); break; From lattner at cs.uiuc.edu Sun Aug 1 01:01:10 2004 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Sun, 1 Aug 2004 01:01:10 -0500 Subject: [llvm-commits] CVS: llvm/lib/Target/X86/X86InstrInfo.td Message-ID: <200408010601.BAA01040@apoc.cs.uiuc.edu> Changes in directory llvm/lib/Target/X86: X86InstrInfo.td updated: 1.82 -> 1.83 --- Log message: Specify an asm string and operands lists for a bunch of instructions. This only really covers no-operand instructions so far. --- Diffs of the changes: (+75 -38) Index: llvm/lib/Target/X86/X86InstrInfo.td diff -u llvm/lib/Target/X86/X86InstrInfo.td:1.82 llvm/lib/Target/X86/X86InstrInfo.td:1.83 --- llvm/lib/Target/X86/X86InstrInfo.td:1.82 Sat Jul 31 22:25:01 2004 +++ llvm/lib/Target/X86/X86InstrInfo.td Sun Aug 1 01:01:00 2004 @@ -108,6 +108,12 @@ list Defs = defs; } +// II - InstructionInfo - this will eventually replace the I class. +class II { + dag OperandList = ops; + string AsmString = AsmStr; +} + // Prefix byte classes which are used to indicate to the ad-hoc machine code // emitter that various prefix bytes are required. @@ -148,15 +154,14 @@ // Helper for shift instructions class UsesCL { list Uses = [CL]; bit printImplicitUsesAfter = 1; } -class PrintImpDefsAfter {bit printImplicitDefsAfter = 1;} //===----------------------------------------------------------------------===// // Instruction list... // -def PHI : I<"PHI", 0, Pseudo>; // PHI node... - -def NOOP : I<"nop", 0x90, RawFrm>; // nop +def PHI : I<"PHI", 0, Pseudo>; // PHI node... +def NOOP : I<"nop", 0x90, RawFrm>, // nop + II<(ops), "nop">; def ADJCALLSTACKDOWN : I<"ADJCALLSTACKDOWN", 0, Pseudo>; def ADJCALLSTACKUP : I<"ADJCALLSTACKUP", 0, Pseudo>; @@ -172,7 +177,8 @@ // Return instruction... let isTerminator = 1, isReturn = 1, isBarrier = 1 in - def RET : I<"ret", 0xC3, RawFrm>; + def RET : I<"ret", 0xC3, RawFrm>, + II<(ops), "ret">; // All branches are RawFrm, Void, Branch, and Terminators let isBranch = 1, isTerminator = 1 in @@ -209,7 +215,8 @@ //===----------------------------------------------------------------------===// // Miscellaneous Instructions... // -def LEAVE : I<"leave", 0xC9, RawFrm>, Imp<[EBP,ESP],[EBP,ESP]>; +def LEAVE : I<"leave", 0xC9, RawFrm>, Imp<[EBP,ESP],[EBP,ESP]>, + II<(ops), "leave">; def POP32r : I<"pop", 0x58, AddRegFrm>, Imp<[ESP],[ESP]>; let isTwoAddress = 1 in // R32 = bswap R32 @@ -230,27 +237,34 @@ def REP_MOVSB : I<"rep movsb", 0xA4, RawFrm>, REP, - Imp<[ECX,EDI,ESI], [ECX,EDI,ESI]>; + Imp<[ECX,EDI,ESI], [ECX,EDI,ESI]>, + II<(ops), "rep movsb">; def REP_MOVSW : I<"rep movsw", 0xA5, RawFrm>, REP, OpSize, - Imp<[ECX,EDI,ESI], [ECX,EDI,ESI]>; + Imp<[ECX,EDI,ESI], [ECX,EDI,ESI]>, + II<(ops), "rep movsw">; def REP_MOVSD : I<"rep movsd", 0xA5, RawFrm>, REP, - Imp<[ECX,EDI,ESI], [ECX,EDI,ESI]>; + Imp<[ECX,EDI,ESI], [ECX,EDI,ESI]>, + II<(ops), "rep movsd">; def REP_STOSB : I<"rep stosb", 0xAA, RawFrm>, REP, - Imp<[AL,ECX,EDI], [ECX,EDI]>; + Imp<[AL,ECX,EDI], [ECX,EDI]>, + II<(ops), "rep stosb">; def REP_STOSW : I<"rep stosw", 0xAB, RawFrm>, REP, OpSize, - Imp<[AX,ECX,EDI], [ECX,EDI]>; + Imp<[AX,ECX,EDI], [ECX,EDI]>, + II<(ops), "rep stosw">; def REP_STOSD : I<"rep stosd", 0xAB, RawFrm>, REP, - Imp<[EAX,ECX,EDI], [ECX,EDI]>; + Imp<[EAX,ECX,EDI], [ECX,EDI]>, + II<(ops), "rep stosd">; //===----------------------------------------------------------------------===// // Input/Output Instructions... // -let printImplicitUsesAfter = 1, printImplicitDefsAfter = 1 in { - def IN8rr : I<"in", 0xEC, RawFrm>, Imp<[DX], [AL]>; // AL = in I/O address DX - def IN16rr : I<"in", 0xED, RawFrm>, Imp<[DX], [AX]>, OpSize; // AX = in I/O address DX - def IN32rr : I<"in", 0xED, RawFrm>, Imp<[DX],[EAX]>; // EAX = in I/O address DX -} +def IN8rr : I<"in", 0xEC, RawFrm>, Imp<[DX], [AL]>, // AL = in I/O address DX + II<(ops), "in AL, DX">; + def IN16rr : I<"in", 0xED, RawFrm>, Imp<[DX], [AX]>, OpSize, // AX = in I/O address DX + II<(ops), "in AX, DX">; +def IN32rr : I<"in", 0xED, RawFrm>, Imp<[DX],[EAX]>, // EAX = in I/O address DX + II<(ops), "in EAX, DX">; let printImplicitDefsBefore = 1 in { def IN8ri : Ii16<"in", 0xE4, RawFrm>, Imp<[], [AL]>; // AL = in [I/O address] @@ -259,9 +273,12 @@ } let printImplicitUsesAfter = 1 in { - def OUT8rr : I<"out", 0xEE, RawFrm>, Imp<[DX, AL], []>; - def OUT16rr : I<"out", 0xEF, RawFrm>, Imp<[DX, AX], []>, OpSize; - def OUT32rr : I<"out", 0xEF, RawFrm>, Imp<[DX, EAX], []>; + def OUT8rr : I<"out", 0xEE, RawFrm>, Imp<[DX, AL], []>, + II<(ops), "out DX, AL">; + def OUT16rr : I<"out", 0xEF, RawFrm>, Imp<[DX, AX], []>, OpSize, + II<(ops), "out DX, AX">; + def OUT32rr : I<"out", 0xEF, RawFrm>, Imp<[DX, EAX], []>, + II<(ops), "out DX, EAX">; def OUT8ir : Ii16<"out", 0xE6, RawFrm>, Imp<[AL], []>; def OUT16ir : Ii16<"out", 0xE7, RawFrm>, Imp<[AX], []>, OpSize; def OUT32ir : Ii16<"out", 0xE7, RawFrm>, Imp<[EAX], []>; @@ -317,9 +334,12 @@ def IDIV32m: Im32<"idiv",0xF7, MRM7m>, Imp<[EAX,EDX],[EAX,EDX]>; // EDX:EAX/[mem32] = EAX,EDX // Sign-extenders for division -def CBW : I<"cbw", 0x98, RawFrm >, Imp<[AL],[AH]>; // AX = signext(AL) -def CWD : I<"cwd", 0x99, RawFrm >, Imp<[AX],[DX]>; // DX:AX = signext(AX) -def CDQ : I<"cdq", 0x99, RawFrm >, Imp<[EAX],[EDX]>; // EDX:EAX = signext(EAX) +def CBW : I<"cbw", 0x98, RawFrm >, Imp<[AL],[AH]>, // AX = signext(AL) + II<(ops), "cbw">; +def CWD : I<"cwd", 0x99, RawFrm >, Imp<[AX],[DX]>, // DX:AX = signext(AX) + II<(ops), "cwd">; +def CDQ : I<"cdq", 0x99, RawFrm >, Imp<[EAX],[EDX]>, // EDX:EAX = signext(EAX) + II<(ops), "cdq">; //===----------------------------------------------------------------------===// // Two address Instructions... @@ -417,7 +437,8 @@ def DEC32m : Im32<"dec", 0xFF, MRM1m>; // --[mem32] // Logical operators... -def AND8rr : I <"and", 0x20, MRMDestReg>; +def AND8rr : I <"and", 0x20, MRMDestReg>, + II<(ops R8:$dst, R8:$src1, R8:$src2), "and $dst, $src2">; def AND16rr : I <"and", 0x21, MRMDestReg>, OpSize; def AND32rr : I <"and", 0x21, MRMDestReg>; def AND8mr : Im8 <"and", 0x20, MRMDestMem>; // [mem8] &= R8 @@ -487,9 +508,12 @@ // Shift instructions // FIXME: provide shorter instructions when imm8 == 1 -def SHL8rCL : I <"shl", 0xD2, MRM4r > , UsesCL; // R8 <<= cl -def SHL16rCL : I <"shl", 0xD3, MRM4r >, OpSize, UsesCL; // R16 <<= cl -def SHL32rCL : I <"shl", 0xD3, MRM4r > , UsesCL; // R32 <<= cl +def SHL8rCL : I <"shl", 0xD2, MRM4r > , UsesCL, // R8 <<= cl + II<(ops R8:$dst, R8:$src), "shl $dst, CL">; +def SHL16rCL : I <"shl", 0xD3, MRM4r >, OpSize, UsesCL, // R16 <<= cl + II<(ops R16:$dst, R16:$src), "shl $dst, CL">; +def SHL32rCL : I <"shl", 0xD3, MRM4r > , UsesCL, // R32 <<= cl + II<(ops R32:$dst, R32:$src), "shl $dst, CL">; def SHL8mCL : Im8 <"shl", 0xD2, MRM4m > , UsesCL; // [mem8] <<= cl def SHL16mCL : Im16 <"shl", 0xD3, MRM4m >, OpSize, UsesCL; // [mem16] <<= cl def SHL32mCL : Im32 <"shl", 0xD3, MRM4m > , UsesCL; // [mem32] <<= cl @@ -501,9 +525,12 @@ def SHL16mi : Im16i8<"shl", 0xC1, MRM4m >, OpSize; // [mem16] <<= imm8 def SHL32mi : Im32i8<"shl", 0xC1, MRM4m >; // [mem32] <<= imm8 -def SHR8rCL : I <"shr", 0xD2, MRM5r > , UsesCL; // R8 >>= cl -def SHR16rCL : I <"shr", 0xD3, MRM5r >, OpSize, UsesCL; // R16 >>= cl -def SHR32rCL : I <"shr", 0xD3, MRM5r > , UsesCL; // R32 >>= cl +def SHR8rCL : I <"shr", 0xD2, MRM5r > , UsesCL, // R8 >>= cl + II<(ops R8:$dst, R8:$src), "shr $dst, CL">; +def SHR16rCL : I <"shr", 0xD3, MRM5r >, OpSize, UsesCL, // R16 >>= cl + II<(ops R16:$dst, R16:$src), "shr $dst, CL">; +def SHR32rCL : I <"shr", 0xD3, MRM5r > , UsesCL, // R32 >>= cl + II<(ops R32:$dst, R32:$src), "shr $dst, CL">; def SHR8mCL : Im8 <"shr", 0xD2, MRM5m > , UsesCL; // [mem8] >>= cl def SHR16mCL : Im16 <"shr", 0xD3, MRM5m >, OpSize, UsesCL; // [mem16] >>= cl def SHR32mCL : Im32 <"shr", 0xD3, MRM5m > , UsesCL; // [mem32] >>= cl @@ -640,8 +667,10 @@ // Condition code ops, incl. set if equal/not equal/... -def SAHF : I <"sahf" , 0x9E, RawFrm>, Imp<[AH],[]>; // flags = AH -def LAHF : I <"lahf" , 0x9F, RawFrm>, Imp<[],[AH]>; // AH = flags +def SAHF : I <"sahf" , 0x9E, RawFrm>, Imp<[AH],[]>, // flags = AH + II<(ops), "sahf">; +def LAHF : I <"lahf" , 0x9F, RawFrm>, Imp<[],[AH]>, // AH = flags + II<(ops), "lahf">; def SETBr : I <"setb" , 0x92, MRM0r>, TB; // R8 = < unsign def SETBm : Im8<"setb" , 0x92, MRM0m>, TB; // [mem8] = < unsign @@ -810,13 +839,17 @@ def FXCH : FPI <"fxch", 0xC8, AddRegFrm, NotFP>, D9; // fxch ST(i), ST(0) // Floating point constant loads... -def FLD0 : FPI<"fldz", 0xEE, RawFrm, ZeroArgFP>, D9; -def FLD1 : FPI<"fld1", 0xE8, RawFrm, ZeroArgFP>, D9; +def FLD0 : FPI<"fldz", 0xEE, RawFrm, ZeroArgFP>, D9, + II<(ops), "fldz">; +def FLD1 : FPI<"fld1", 0xE8, RawFrm, ZeroArgFP>, D9, + II<(ops), "fld1">; // Unary operations... -def FCHS : FPI<"fchs", 0xE0, RawFrm, OneArgFPRW>, D9; // f1 = fchs f2 -def FTST : FPI<"ftst", 0xE4, RawFrm, OneArgFP>, D9; // ftst ST(0) +def FCHS : FPI<"fchs", 0xE0, RawFrm, OneArgFPRW>, D9, // f1 = fchs f2 + II<(ops), "fchs">; +def FTST : FPI<"ftst", 0xE4, RawFrm, OneArgFP>, D9, // ftst ST(0) + II<(ops), "ftst">; // Binary arithmetic operations... class FPST0rInst o> : I, D8 { @@ -858,7 +891,9 @@ // Floating point compares def FUCOMr : FPI<"fucom", 0xE0, AddRegFrm, CompareFP>, DD, Imp<[ST0],[]>; // FPSW = compare ST(0) with ST(i) def FUCOMPr : I<"fucomp" , 0xE8, AddRegFrm>, DD, Imp<[ST0],[]>; // FPSW = compare ST(0) with ST(i), pop -def FUCOMPPr : I<"fucompp", 0xE9, RawFrm >, DA, Imp<[ST0],[]>; // compare ST(0) with ST(1), pop, pop +def FUCOMPPr : I<"fucompp", 0xE9, RawFrm >, DA, Imp<[ST0],[]>, // compare ST(0) with ST(1), pop, pop + II<(ops), "fucompp">; + let printImplicitUsesBefore = 1 in { def FUCOMIr : FPI<"fucomi", 0xE8, AddRegFrm, CompareFP>, DB, Imp<[ST0],[]>; // CC = compare ST(0) with ST(i) @@ -866,6 +901,8 @@ } // Floating point flag ops -def FNSTSW8r : I <"fnstsw" , 0xE0, RawFrm>, DF, Imp<[],[AX]>; // AX = fp flags +def FNSTSW8r : I <"fnstsw" , 0xE0, RawFrm>, DF, Imp<[],[AX]>, // AX = fp flags + II<(ops), "fnstsw">; + def FNSTCW16m : Im16<"fnstcw" , 0xD9, MRM7m >; // [mem16] = X87 control world def FLDCW16m : Im16<"fldcw" , 0xD9, MRM5m >; // X87 control world = [mem16] From lattner at cs.uiuc.edu Sun Aug 1 01:01:42 2004 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Sun, 1 Aug 2004 01:01:42 -0500 Subject: [llvm-commits] CVS: llvm/lib/Target/X86/Makefile Message-ID: <200408010601.BAA01055@apoc.cs.uiuc.edu> Changes in directory llvm/lib/Target/X86: Makefile updated: 1.17 -> 1.18 --- Log message: Factor a bunch of the rules and add support for generating the asmwriter. --- Diffs of the changes: (+23 -21) Index: llvm/lib/Target/X86/Makefile diff -u llvm/lib/Target/X86/Makefile:1.17 llvm/lib/Target/X86/Makefile:1.18 --- llvm/lib/Target/X86/Makefile:1.17 Thu Jul 22 16:30:35 2004 +++ llvm/lib/Target/X86/Makefile Sun Aug 1 01:01:32 2004 @@ -10,42 +10,44 @@ LIBRARYNAME = x86 include $(LEVEL)/Makefile.common +TARGET = X86 + # Make sure that tblgen is run, first thing. $(SourceDepend): X86GenRegisterInfo.h.inc X86GenRegisterNames.inc \ X86GenRegisterInfo.inc X86GenInstrNames.inc \ - X86GenInstrInfo.inc X86GenInstrSelector.inc + X86GenInstrInfo.inc X86GenAsmWriter.inc \ + X86GenInstrSelector.inc + +TDFILES = $(SourceDir)/$(TARGET).td $(wildcard $(SourceDir)/*.td) \ + $(SourceDir)/../Target.td -X86GenRegisterNames.inc:: $(SourceDir)/X86.td $(SourceDir)/X86RegisterInfo.td \ - $(SourceDir)/../Target.td $(TBLGEN) - @echo "Building X86.td register names with tblgen" +$(TARGET)GenRegisterNames.inc:: $(TDFILES) $(TBLGEN) + @echo "Building $(TARGET).td register names with tblgen" $(VERB) $(TBLGEN) -I $(BUILD_SRC_DIR) $< -gen-register-enums -o $@ -X86GenRegisterInfo.h.inc:: $(SourceDir)/X86.td $(SourceDir)/X86RegisterInfo.td \ - $(SourceDir)/../Target.td $(TBLGEN) - @echo "Building X86.td register information header with tblgen" +$(TARGET)GenRegisterInfo.h.inc:: $(TDFILES) $(TBLGEN) + @echo "Building $(TARGET).td register information header with tblgen" $(VERB) $(TBLGEN) -I $(BUILD_SRC_DIR) $< -gen-register-desc-header -o $@ -X86GenRegisterInfo.inc:: $(SourceDir)/X86.td $(SourceDir)/X86RegisterInfo.td \ - $(SourceDir)/../Target.td $(TBLGEN) - @echo "Building X86.td register information implementation with tblgen" +$(TARGET)GenRegisterInfo.inc:: $(TDFILES) $(TBLGEN) + @echo "Building $(TARGET).td register info implementation with tblgen" $(VERB) $(TBLGEN) -I $(BUILD_SRC_DIR) $< -gen-register-desc -o $@ -X86GenInstrNames.inc:: $(SourceDir)/X86.td $(SourceDir)/X86InstrInfo.td \ - $(SourceDir)/../Target.td $(TBLGEN) - @echo "Building X86.td instruction names with tblgen" +$(TARGET)GenInstrNames.inc:: $(TDFILES) $(TBLGEN) + @echo "Building $(TARGET).td instruction names with tblgen" $(VERB) $(TBLGEN) -I $(BUILD_SRC_DIR) $< -gen-instr-enums -o $@ -X86GenInstrInfo.inc:: $(SourceDir)/X86.td $(SourceDir)/X86InstrInfo.td \ - $(SourceDir)/../Target.td $(TBLGEN) - @echo "Building X86.td instruction information with tblgen" +$(TARGET)GenInstrInfo.inc:: $(TDFILES) $(TBLGEN) + @echo "Building $(TARGET).td instruction information with tblgen" $(VERB) $(TBLGEN) -I $(BUILD_SRC_DIR) $< -gen-instr-desc -o $@ -X86GenInstrSelector.inc:: $(SourceDir)/X86.td $(SourceDir)/X86InstrInfo.td \ - $(SourceDir)/../Target.td $(TBLGEN) - @echo "Building X86.td instruction selector with tblgen" - $(VERB) $(TBLGEN) -I $(BUILD_SRC_DIR) $< -gen-instr-selector -o $@ - +$(TARGET)GenAsmWriter.inc:: $(TDFILES) $(TBLGEN) + @echo "Building $(TARGET).td assembly writer with tblgen" + $(VERB) $(TBLGEN) -I $(BUILD_SRC_DIR) $< -gen-asm-writer -o $@ +$(TARGET)GenInstrSelector.inc:: $(TDFILES) $(TBLGEN) + @echo "Building $(TARGET).td instruction selector with tblgen" + $(VERB) $(TBLGEN) -I $(BUILD_SRC_DIR) $< -gen-instr-selector -o $@ clean:: $(VERB) rm -f *.inc From lattner at cs.uiuc.edu Sun Aug 1 01:02:18 2004 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Sun, 1 Aug 2004 01:02:18 -0500 Subject: [llvm-commits] CVS: llvm/lib/Target/X86/X86AsmPrinter.cpp Message-ID: <200408010602.BAA01068@apoc.cs.uiuc.edu> Changes in directory llvm/lib/Target/X86: X86AsmPrinter.cpp updated: 1.106 -> 1.107 --- Log message: Rename the Printer class -> X86AsmPrinter. Include the tablegenerated assembly writer. --- Diffs of the changes: (+47 -35) Index: llvm/lib/Target/X86/X86AsmPrinter.cpp diff -u llvm/lib/Target/X86/X86AsmPrinter.cpp:1.106 llvm/lib/Target/X86/X86AsmPrinter.cpp:1.107 --- llvm/lib/Target/X86/X86AsmPrinter.cpp:1.106 Mon Jul 26 13:48:58 2004 +++ llvm/lib/Target/X86/X86AsmPrinter.cpp Sun Aug 1 01:02:08 2004 @@ -71,7 +71,7 @@ bool firstByte; }; - struct Printer : public MachineFunctionPass { + struct X86AsmPrinter : public MachineFunctionPass { /// Output stream on which we're printing assembly code. /// std::ostream &O; @@ -85,7 +85,7 @@ /// Mangler *Mang; - Printer(std::ostream &o, TargetMachine &tm) : O(o), TM(tm) { } + X86AsmPrinter(std::ostream &o, TargetMachine &tm) : O(o), TM(tm) { } /// Cache of mangled name for current function. This is /// recalculated at the beginning of each call to @@ -97,6 +97,12 @@ return "X86 Assembly Printer"; } + /// printInstruction - This method is automatically generated by tablegen + /// from the instruction set description. This method returns true if the + /// machine instruction was sufficiently described to print it, otherwise it + /// returns false. + bool printInstruction(const MachineInstr *MI); + void printImplUsesBefore(const TargetInstrDescriptor &Desc); bool printImplDefsBefore(const TargetInstrDescriptor &Desc); bool printImplUsesAfter(const TargetInstrDescriptor &Desc, const bool LC); @@ -119,9 +125,14 @@ /// regardless of whether the function is in SSA form. /// FunctionPass *llvm::createX86CodePrinterPass(std::ostream &o,TargetMachine &tm){ - return new Printer(o, tm); + return new X86AsmPrinter(o, tm); } + +// Include the auto-generated portion of the assembly writer. +#include "X86GenAsmWriter.inc" + + /// toOctal - Convert the low order bits of X into an octal digit. /// static inline char toOctal(int X) { @@ -165,7 +176,7 @@ // Print out the specified constant, without a storage class. Only the // constants valid in constant expressions can occur here. -void Printer::emitConstantValueOnly(const Constant *CV) { +void X86AsmPrinter::emitConstantValueOnly(const Constant *CV) { if (CV->isNullValue()) O << "0"; else if (const ConstantBool *CB = dyn_cast(CV)) { @@ -238,7 +249,7 @@ // Print a constant value or values, with the appropriate storage class as a // prefix. -void Printer::emitGlobalConstant(const Constant *CV) { +void X86AsmPrinter::emitGlobalConstant(const Constant *CV) { const TargetData &TD = TM.getTargetData(); if (CV->isNullValue()) { @@ -338,7 +349,7 @@ /// used to print out constants which have been "spilled to memory" by /// the code generator. /// -void Printer::printConstantPool(MachineConstantPool *MCP) { +void X86AsmPrinter::printConstantPool(MachineConstantPool *MCP) { const std::vector &CP = MCP->getConstants(); const TargetData &TD = TM.getTargetData(); @@ -357,7 +368,7 @@ /// runOnMachineFunction - This uses the printMachineInstruction() /// method to print assembly for each instruction. /// -bool Printer::runOnMachineFunction(MachineFunction &MF) { +bool X86AsmPrinter::runOnMachineFunction(MachineFunction &MF) { O << "\n\n"; // What's my mangled name? CurrentFnName = Mang->getValueName(MF.getFunction()); @@ -407,8 +418,8 @@ -void Printer::printOp(const MachineOperand &MO, - bool elideOffsetKeyword /* = false */) { +void X86AsmPrinter::printOp(const MachineOperand &MO, + bool elideOffsetKeyword /* = false */) { const MRegisterInfo &RI = *TM.getRegisterInfo(); switch (MO.getType()) { case MachineOperand::MO_VirtualRegister: @@ -464,7 +475,7 @@ } } -void Printer::printMemReference(const MachineInstr *MI, unsigned Op) { +void X86AsmPrinter::printMemReference(const MachineInstr *MI, unsigned Op) { assert(isMem(MI, Op) && "Invalid memory reference!"); if (MI->getOperand(Op).isFrameIndex()) { @@ -519,11 +530,11 @@ /// printImplUsesBefore - Emit the implicit-use registers for the instruction /// described by DESC, if its PrintImplUsesBefore flag is set. /// -void Printer::printImplUsesBefore(const TargetInstrDescriptor &Desc) { +void X86AsmPrinter::printImplUsesBefore(const TargetInstrDescriptor &Desc) { const MRegisterInfo &RI = *TM.getRegisterInfo(); if (Desc.TSFlags & X86II::PrintImplUsesBefore) { for (const unsigned *p = Desc.ImplicitUses; *p; ++p) { - // Bug Workaround: See note in Printer::doInitialization about %. + // Bug Workaround: See note in X86AsmPrinter::doInitialization about %. O << "%" << RI.get(*p).Name << ", "; } } @@ -533,7 +544,7 @@ /// described by DESC, if its PrintImplUsesBefore flag is set. Return true if /// we printed any registers. /// -bool Printer::printImplDefsBefore(const TargetInstrDescriptor &Desc) { +bool X86AsmPrinter::printImplDefsBefore(const TargetInstrDescriptor &Desc) { bool Printed = false; const MRegisterInfo &RI = *TM.getRegisterInfo(); if (Desc.TSFlags & X86II::PrintImplDefsBefore) { @@ -544,7 +555,7 @@ ++p; } while (*p) { - // Bug Workaround: See note in Printer::doInitialization about %. + // Bug Workaround: See note in X86AsmPrinter::doInitialization about %. O << ", %" << RI.get(*p).Name; ++p; } @@ -564,8 +575,8 @@ /// true - Emitted one or more registers. /// false - Emitted no registers. /// -bool Printer::printImplUsesAfter(const TargetInstrDescriptor &Desc, - const bool Comma = true) { +bool X86AsmPrinter::printImplUsesAfter(const TargetInstrDescriptor &Desc, + const bool Comma = true) { const MRegisterInfo &RI = *TM.getRegisterInfo(); if (Desc.TSFlags & X86II::PrintImplUsesAfter) { bool emitted = false; @@ -576,7 +587,7 @@ ++p; } while (*p) { - // Bug Workaround: See note in Printer::doInitialization about %. + // Bug Workaround: See note in X86AsmPrinter::doInitialization about %. O << ", %" << RI.get(*p).Name; ++p; } @@ -596,8 +607,8 @@ /// true - Emitted one or more registers. /// false - Emitted no registers. /// -bool Printer::printImplDefsAfter(const TargetInstrDescriptor &Desc, - const bool Comma = true) { +bool X86AsmPrinter::printImplDefsAfter(const TargetInstrDescriptor &Desc, + const bool Comma = true) { const MRegisterInfo &RI = *TM.getRegisterInfo(); if (Desc.TSFlags & X86II::PrintImplDefsAfter) { bool emitted = false; @@ -608,7 +619,7 @@ ++p; } while (*p) { - // Bug Workaround: See note in Printer::doInitialization about %. + // Bug Workaround: See note in X86AsmPrinter::doInitialization about %. O << ", %" << RI.get(*p).Name; ++p; } @@ -620,12 +631,15 @@ /// printMachineInstruction -- Print out a single X86 LLVM instruction /// MI in Intel syntax to the current output stream. /// -void Printer::printMachineInstruction(const MachineInstr *MI) { +void X86AsmPrinter::printMachineInstruction(const MachineInstr *MI) { + ++EmittedInsts; + if (printInstruction(MI)) + return; // Printer was automatically generated + unsigned Opcode = MI->getOpcode(); const TargetInstrInfo &TII = *TM.getInstrInfo(); const TargetInstrDescriptor &Desc = TII.get(Opcode); - ++EmittedInsts; switch (Desc.TSFlags & X86II::FormMask) { case X86II::Pseudo: // Print pseudo-instructions as comments; either they should have been @@ -665,17 +679,15 @@ case X86II::RawFrm: { // The accepted forms of Raw instructions are: - // 1. nop - No operand required - // 2. jmp foo - MachineBasicBlock operand - // 3. call bar - GlobalAddress Operand or External Symbol Operand - // 4. in AL, imm - Immediate operand - // - assert(MI->getNumOperands() == 0 || - (MI->getNumOperands() == 1 && - (MI->getOperand(0).isMachineBasicBlock() || - MI->getOperand(0).isGlobalAddress() || - MI->getOperand(0).isExternalSymbol() || - MI->getOperand(0).isImmediate())) && + // 1. jmp foo - MachineBasicBlock operand + // 2. call bar - GlobalAddress Operand or External Symbol Operand + // 3. in AL, imm - Immediate operand + // + assert(MI->getNumOperands() == 1 && + (MI->getOperand(0).isMachineBasicBlock() || + MI->getOperand(0).isGlobalAddress() || + MI->getOperand(0).isExternalSymbol() || + MI->getOperand(0).isImmediate()) && "Illegal raw instruction!"); O << TII.getName(MI->getOpcode()) << " "; @@ -940,7 +952,7 @@ } } -bool Printer::doInitialization(Module &M) { +bool X86AsmPrinter::doInitialization(Module &M) { // Tell gas we are outputting Intel syntax (not AT&T syntax) assembly. // // Bug: gas in `intel_syntax noprefix' mode interprets the symbol `Sp' in an @@ -966,7 +978,7 @@ } } -bool Printer::doFinalization(Module &M) { +bool X86AsmPrinter::doFinalization(Module &M) { const TargetData &TD = TM.getTargetData(); std::string CurSection; From lattner at cs.uiuc.edu Sun Aug 1 02:43:17 2004 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Sun, 1 Aug 2004 02:43:17 -0500 Subject: [llvm-commits] CVS: llvm/utils/TableGen/AsmWriterEmitter.cpp Message-ID: <200408010743.CAA12248@apoc.cs.uiuc.edu> Changes in directory llvm/utils/TableGen: AsmWriterEmitter.cpp updated: 1.1 -> 1.2 --- Log message: Add support for asm printing machine instructions that have operands. --- Diffs of the changes: (+48 -2) Index: llvm/utils/TableGen/AsmWriterEmitter.cpp diff -u llvm/utils/TableGen/AsmWriterEmitter.cpp:1.1 llvm/utils/TableGen/AsmWriterEmitter.cpp:1.2 --- llvm/utils/TableGen/AsmWriterEmitter.cpp:1.1 Sun Aug 1 00:59:33 2004 +++ llvm/utils/TableGen/AsmWriterEmitter.cpp Sun Aug 1 02:43:02 2004 @@ -17,6 +17,13 @@ #include using namespace llvm; +static bool isIdentChar(char C) { + return (C >= 'a' && C <= 'z') || + (C >= 'A' && C <= 'Z') || + (C >= '0' && C <= '9') || + C == '_'; +} + void AsmWriterEmitter::run(std::ostream &O) { EmitSourceFileHeader("Assembly Writer Source Fragment", O); @@ -37,8 +44,47 @@ E = Target.inst_end(); I != E; ++I) if (!I->second.AsmString.empty()) { const std::string &AsmString = I->second.AsmString; - O << " case " << Namespace << "::" << I->first << ": O << \"" - << AsmString << "\" << '\\n'; break;\n"; + O << " case " << Namespace << "::" << I->first << ": O "; + + std::string::size_type LastEmitted = 0; + while (LastEmitted != AsmString.size()) { + std::string::size_type DollarPos = AsmString.find('$', LastEmitted); + if (DollarPos == std::string::npos) DollarPos = AsmString.size(); + + // Emit a constant string fragment. + if (DollarPos != LastEmitted) { + // TODO: this should eventually handle escaping. + O << " << \"" << std::string(AsmString.begin()+LastEmitted, + AsmString.begin()+DollarPos) << "\""; + LastEmitted = DollarPos; + } else if (DollarPos+1 != AsmString.size() && + AsmString[DollarPos+1] == '$') { + O << " << '$'"; // "$$" -> $ + } else { + // Get the name of the variable. + // TODO: should eventually handle ${foo}bar as $foo + std::string::size_type VarEnd = DollarPos+1; + while (VarEnd < AsmString.size() && isIdentChar(AsmString[VarEnd])) + ++VarEnd; + std::string VarName(AsmString.begin()+DollarPos+1, + AsmString.begin()+VarEnd); + if (VarName.empty()) + throw "Stray '$' in '" + I->first + + "' asm string, maybe you want $$?"; + unsigned OpNo = I->second.getOperandNamed(VarName); + + // If this is a two-address instruction and we are not accessing the + // 0th operand, remove an operand. + if (I->second.isTwoAddress && OpNo != 0) + --OpNo; + + O << "; printOperand(MI->getOperand(" << OpNo << "), MVT::" + << getName(I->second.OperandList[OpNo].Ty) << "); O "; + LastEmitted = VarEnd; + } + } + + O << " << '\\n'; break;\n"; } O << " }\n" From lattner at cs.uiuc.edu Sun Aug 1 02:43:20 2004 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Sun, 1 Aug 2004 02:43:20 -0500 Subject: [llvm-commits] CVS: llvm/utils/TableGen/CodeGenTarget.cpp CodeGenTarget.h CodeGenInstruction.h Message-ID: <200408010743.CAA12258@apoc.cs.uiuc.edu> Changes in directory llvm/utils/TableGen: CodeGenTarget.cpp updated: 1.11 -> 1.12 CodeGenTarget.h updated: 1.9 -> 1.10 CodeGenInstruction.h updated: 1.1 -> 1.2 --- Log message: Parse the operand list of the instruction. We currently support register and immediate operands. --- Diffs of the changes: (+54 -7) Index: llvm/utils/TableGen/CodeGenTarget.cpp diff -u llvm/utils/TableGen/CodeGenTarget.cpp:1.11 llvm/utils/TableGen/CodeGenTarget.cpp:1.12 --- llvm/utils/TableGen/CodeGenTarget.cpp:1.11 Sun Aug 1 00:59:33 2004 +++ llvm/utils/TableGen/CodeGenTarget.cpp Sun Aug 1 02:42:39 2004 @@ -129,16 +129,47 @@ isTwoAddress = R->getValueAsBit("isTwoAddress"); isTerminator = R->getValueAsBit("isTerminator"); - - //TODO: Parse OperandList try { DagInit *DI = R->getValueAsDag("OperandList"); - // Cannot handle instructions with operands yet. - if (DI->getNumArgs()) - AsmString.clear(); + for (unsigned i = 0, e = DI->getNumArgs(); i != e; ++i) + if (DefInit *Arg = dynamic_cast(DI->getArg(i))) { + Record *Rec = Arg->getDef(); + MVT::ValueType Ty; + if (Rec->isSubClassOf("RegisterClass")) + Ty = getValueType(Rec->getValueAsDef("RegType")); + else if (Rec->getName() == "i8imm") + Ty = MVT::i8; + else if (Rec->getName() == "i16imm") + Ty = MVT::i16; + else if (Rec->getName() == "i32imm") + Ty = MVT::i32; + else if (Rec->getName() == "i64imm") + Ty = MVT::i64; + else + throw "Unknown operand class '" + Rec->getName() + + "' in instruction '" + R->getName() + "' instruction!"; + + OperandList.push_back(OperandInfo(Rec, Ty, DI->getArgName(i))); + } else { + throw "Illegal operand for the '" + R->getName() + "' instruction!"; + } } catch (...) { + // Error parsing operands list, just ignore it. + AsmString.clear(); + OperandList.clear(); } } + +/// getOperandNamed - Return the index of the operand with the specified +/// non-empty name. If the instruction does not have an operand with the +/// specified name, throw an exception. +unsigned CodeGenInstruction::getOperandNamed(const std::string &Name) const { + assert(!Name.empty() && "Cannot search for operand with no name!"); + for (unsigned i = 0, e = OperandList.size(); i != e; ++i) + if (OperandList[i].Name == Name) return i; + throw "Instruction '" + TheDef->getName() + + "' does not have an operand named '$" + Name + "'!"; +} Index: llvm/utils/TableGen/CodeGenTarget.h diff -u llvm/utils/TableGen/CodeGenTarget.h:1.9 llvm/utils/TableGen/CodeGenTarget.h:1.10 --- llvm/utils/TableGen/CodeGenTarget.h:1.9 Sun Aug 1 00:04:00 2004 +++ llvm/utils/TableGen/CodeGenTarget.h Sun Aug 1 02:42:39 2004 @@ -18,7 +18,6 @@ #define CODEGEN_TARGET_H #include "CodeGenInstruction.h" -#include "llvm/CodeGen/ValueTypes.h" #include #include Index: llvm/utils/TableGen/CodeGenInstruction.h diff -u llvm/utils/TableGen/CodeGenInstruction.h:1.1 llvm/utils/TableGen/CodeGenInstruction.h:1.2 --- llvm/utils/TableGen/CodeGenInstruction.h:1.1 Sun Aug 1 00:04:00 2004 +++ llvm/utils/TableGen/CodeGenInstruction.h Sun Aug 1 02:42:39 2004 @@ -14,6 +14,7 @@ #ifndef CODEGEN_INSTRUCTION_H #define CODEGEN_INSTRUCTION_H +#include "llvm/CodeGen/ValueTypes.h" #include #include #include @@ -29,10 +30,21 @@ /// AsmString - The format string used to emit a .s file for the /// instruction. std::string AsmString; + + /// OperandInfo - For each operand declared in the OperandList of the + /// instruction, keep track of its record (which specifies the class of the + /// operand), its type, and the name given to the operand, if any. + struct OperandInfo { + Record *Rec; + MVT::ValueType Ty; + std::string Name; + OperandInfo(Record *R, MVT::ValueType T, const std::string &N) + : Rec(R), Ty(T), Name(N) {} + }; /// OperandList - The list of declared operands, along with their declared /// type (which is a record). - std::vector > OperandList; + std::vector OperandList; // Various boolean values we track for the instruction. bool isReturn; @@ -43,6 +55,11 @@ bool isTerminator; CodeGenInstruction(Record *R); + + /// getOperandNamed - Return the index of the operand with the specified + /// non-empty name. If the instruction does not have an operand with the + /// specified name, throw an exception. + unsigned getOperandNamed(const std::string &Name) const; }; } From lattner at cs.uiuc.edu Sun Aug 1 02:43:56 2004 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Sun, 1 Aug 2004 02:43:56 -0500 Subject: [llvm-commits] CVS: llvm/lib/Target/X86/X86AsmPrinter.cpp Message-ID: <200408010743.CAA12272@apoc.cs.uiuc.edu> Changes in directory llvm/lib/Target/X86: X86AsmPrinter.cpp updated: 1.107 -> 1.108 --- Log message: The tblgen'erated asmparser wants a way to print operands. --- Diffs of the changes: (+6 -0) Index: llvm/lib/Target/X86/X86AsmPrinter.cpp diff -u llvm/lib/Target/X86/X86AsmPrinter.cpp:1.107 llvm/lib/Target/X86/X86AsmPrinter.cpp:1.108 --- llvm/lib/Target/X86/X86AsmPrinter.cpp:1.107 Sun Aug 1 01:02:08 2004 +++ llvm/lib/Target/X86/X86AsmPrinter.cpp Sun Aug 1 02:43:46 2004 @@ -25,6 +25,7 @@ #include "llvm/CodeGen/MachineConstantPool.h" #include "llvm/CodeGen/MachineFunctionPass.h" #include "llvm/CodeGen/MachineInstr.h" +#include "llvm/CodeGen/ValueTypes.h" #include "llvm/Target/TargetMachine.h" #include "llvm/Support/Mangler.h" #include "Support/Statistic.h" @@ -103,6 +104,11 @@ /// returns false. bool printInstruction(const MachineInstr *MI); + // This method is used by the tablegen'erated instruction printer. + void printOperand(const MachineOperand &MO, MVT::ValueType VT) { + printOp(MO); + } + void printImplUsesBefore(const TargetInstrDescriptor &Desc); bool printImplDefsBefore(const TargetInstrDescriptor &Desc); bool printImplUsesAfter(const TargetInstrDescriptor &Desc, const bool LC); From lattner at cs.uiuc.edu Sun Aug 1 02:44:45 2004 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Sun, 1 Aug 2004 02:44:45 -0500 Subject: [llvm-commits] CVS: llvm/lib/Target/X86/X86InstrInfo.td Message-ID: <200408010744.CAA12283@apoc.cs.uiuc.edu> Changes in directory llvm/lib/Target/X86: X86InstrInfo.td updated: 1.83 -> 1.84 --- Log message: Switch more instructions over to using the asmprinter. Fix bugs in the emission of in/out instructions (missing %'s on registers). --- Diffs of the changes: (+46 -35) Index: llvm/lib/Target/X86/X86InstrInfo.td diff -u llvm/lib/Target/X86/X86InstrInfo.td:1.83 llvm/lib/Target/X86/X86InstrInfo.td:1.84 --- llvm/lib/Target/X86/X86InstrInfo.td:1.83 Sun Aug 1 01:01:00 2004 +++ llvm/lib/Target/X86/X86InstrInfo.td Sun Aug 1 02:44:35 2004 @@ -260,39 +260,48 @@ // Input/Output Instructions... // def IN8rr : I<"in", 0xEC, RawFrm>, Imp<[DX], [AL]>, // AL = in I/O address DX - II<(ops), "in AL, DX">; - def IN16rr : I<"in", 0xED, RawFrm>, Imp<[DX], [AX]>, OpSize, // AX = in I/O address DX - II<(ops), "in AX, DX">; + II<(ops), "in %AL, %DX">; +def IN16rr : I<"in", 0xED, RawFrm>, Imp<[DX], [AX]>, OpSize, // AX = in I/O address DX + II<(ops), "in %AX, %DX">; def IN32rr : I<"in", 0xED, RawFrm>, Imp<[DX],[EAX]>, // EAX = in I/O address DX - II<(ops), "in EAX, DX">; + II<(ops), "in %EAX, %DX">; -let printImplicitDefsBefore = 1 in { - def IN8ri : Ii16<"in", 0xE4, RawFrm>, Imp<[], [AL]>; // AL = in [I/O address] - def IN16ri : Ii16<"in", 0xE5, RawFrm>, Imp<[], [AX]>, OpSize; // AX = in [I/O address] - def IN32ri : Ii16<"in", 0xE5, RawFrm>, Imp<[],[EAX]>; // EAX = in [I/O address] -} - -let printImplicitUsesAfter = 1 in { - def OUT8rr : I<"out", 0xEE, RawFrm>, Imp<[DX, AL], []>, - II<(ops), "out DX, AL">; - def OUT16rr : I<"out", 0xEF, RawFrm>, Imp<[DX, AX], []>, OpSize, - II<(ops), "out DX, AX">; - def OUT32rr : I<"out", 0xEF, RawFrm>, Imp<[DX, EAX], []>, - II<(ops), "out DX, EAX">; - def OUT8ir : Ii16<"out", 0xE6, RawFrm>, Imp<[AL], []>; - def OUT16ir : Ii16<"out", 0xE7, RawFrm>, Imp<[AX], []>, OpSize; - def OUT32ir : Ii16<"out", 0xE7, RawFrm>, Imp<[EAX], []>; -} +def IN8ri : Ii16<"in", 0xE4, RawFrm>, Imp<[], [AL]>, // AL = in [I/O address] + II<(ops i16imm:$port), "in %AL, $port">; +def IN16ri : Ii16<"in", 0xE5, RawFrm>, Imp<[], [AX]>, OpSize, // AX = in [I/O address] + II<(ops i16imm:$port), "in %AX, $port">; +def IN32ri : Ii16<"in", 0xE5, RawFrm>, Imp<[],[EAX]>, // EAX = in [I/O address] + II<(ops i16imm:$port), "in %EAX, $port">; + +def OUT8rr : I<"out", 0xEE, RawFrm>, Imp<[DX, AL], []>, + II<(ops), "out %DX, %AL">; +def OUT16rr : I<"out", 0xEF, RawFrm>, Imp<[DX, AX], []>, OpSize, + II<(ops), "out %DX, %AX">; +def OUT32rr : I<"out", 0xEF, RawFrm>, Imp<[DX, EAX], []>, + II<(ops), "out %DX, %EAX">; + +def OUT8ir : Ii16<"out", 0xE6, RawFrm>, Imp<[AL], []>, + II<(ops i16imm:$port), "out $port, %AL">; +def OUT16ir : Ii16<"out", 0xE7, RawFrm>, Imp<[AX], []>, OpSize, + II<(ops i16imm:$port), "out $port, %AX">; +def OUT32ir : Ii16<"out", 0xE7, RawFrm>, Imp<[EAX], []>, + II<(ops i16imm:$port), "out $port, %EAX">; //===----------------------------------------------------------------------===// // Move Instructions... // -def MOV8rr : I <"mov", 0x88, MRMDestReg>; -def MOV16rr : I <"mov", 0x89, MRMDestReg>, OpSize; -def MOV32rr : I <"mov", 0x89, MRMDestReg>; -def MOV8ri : Ii8 <"mov", 0xB0, AddRegFrm >; -def MOV16ri : Ii16 <"mov", 0xB8, AddRegFrm >, OpSize; -def MOV32ri : Ii32 <"mov", 0xB8, AddRegFrm >; +def MOV8rr : I <"mov", 0x88, MRMDestReg>, + II<(ops R8:$dst, R8:$src), "mov $dst, $src">; +def MOV16rr : I <"mov", 0x89, MRMDestReg>, OpSize, + II<(ops R16:$dst, R16:$src), "mov $dst, $src">; +def MOV32rr : I <"mov", 0x89, MRMDestReg>, + II<(ops R32:$dst, R32:$src), "mov $dst, $src">; +def MOV8ri : Ii8 <"mov", 0xB0, AddRegFrm >, + II<(ops R8:$dst, i8imm:$src), "mov $dst, $src">; +def MOV16ri : Ii16 <"mov", 0xB8, AddRegFrm >, OpSize, + II<(ops R16:$dst, i16imm:$src), "mov $dst, $src">; +def MOV32ri : Ii32 <"mov", 0xB8, AddRegFrm >, + II<(ops R32:$dst, i32imm:$src), "mov $dst, $src">; def MOV8mi : Im8i8 <"mov", 0xC6, MRM0m >; // [mem8] = imm8 def MOV16mi : Im16i16<"mov", 0xC7, MRM0m >, OpSize; // [mem16] = imm16 def MOV32mi : Im32i32<"mov", 0xC7, MRM0m >; // [mem32] = imm32 @@ -439,8 +448,10 @@ // Logical operators... def AND8rr : I <"and", 0x20, MRMDestReg>, II<(ops R8:$dst, R8:$src1, R8:$src2), "and $dst, $src2">; -def AND16rr : I <"and", 0x21, MRMDestReg>, OpSize; -def AND32rr : I <"and", 0x21, MRMDestReg>; +def AND16rr : I <"and", 0x21, MRMDestReg>, OpSize, + II<(ops R32:$dst, R32:$src1, R32:$src2), "and $dst, $src2">; +def AND32rr : I <"and", 0x21, MRMDestReg>, + II<(ops R32:$dst, R32:$src1, R32:$src2), "and $dst, $src2">; def AND8mr : Im8 <"and", 0x20, MRMDestMem>; // [mem8] &= R8 def AND16mr : Im16 <"and", 0x21, MRMDestMem>, OpSize; // [mem16] &= R16 def AND32mr : Im32 <"and", 0x21, MRMDestMem>; // [mem32] &= R32 @@ -509,11 +520,11 @@ // Shift instructions // FIXME: provide shorter instructions when imm8 == 1 def SHL8rCL : I <"shl", 0xD2, MRM4r > , UsesCL, // R8 <<= cl - II<(ops R8:$dst, R8:$src), "shl $dst, CL">; + II<(ops R8:$dst, R8:$src), "shl $dst, %CL">; def SHL16rCL : I <"shl", 0xD3, MRM4r >, OpSize, UsesCL, // R16 <<= cl - II<(ops R16:$dst, R16:$src), "shl $dst, CL">; + II<(ops R16:$dst, R16:$src), "shl $dst, %CL">; def SHL32rCL : I <"shl", 0xD3, MRM4r > , UsesCL, // R32 <<= cl - II<(ops R32:$dst, R32:$src), "shl $dst, CL">; + II<(ops R32:$dst, R32:$src), "shl $dst, %CL">; def SHL8mCL : Im8 <"shl", 0xD2, MRM4m > , UsesCL; // [mem8] <<= cl def SHL16mCL : Im16 <"shl", 0xD3, MRM4m >, OpSize, UsesCL; // [mem16] <<= cl def SHL32mCL : Im32 <"shl", 0xD3, MRM4m > , UsesCL; // [mem32] <<= cl @@ -526,11 +537,11 @@ def SHL32mi : Im32i8<"shl", 0xC1, MRM4m >; // [mem32] <<= imm8 def SHR8rCL : I <"shr", 0xD2, MRM5r > , UsesCL, // R8 >>= cl - II<(ops R8:$dst, R8:$src), "shr $dst, CL">; + II<(ops R8:$dst, R8:$src), "shr $dst, %CL">; def SHR16rCL : I <"shr", 0xD3, MRM5r >, OpSize, UsesCL, // R16 >>= cl - II<(ops R16:$dst, R16:$src), "shr $dst, CL">; + II<(ops R16:$dst, R16:$src), "shr $dst, %CL">; def SHR32rCL : I <"shr", 0xD3, MRM5r > , UsesCL, // R32 >>= cl - II<(ops R32:$dst, R32:$src), "shr $dst, CL">; + II<(ops R32:$dst, R32:$src), "shr $dst, %CL">; def SHR8mCL : Im8 <"shr", 0xD2, MRM5m > , UsesCL; // [mem8] >>= cl def SHR16mCL : Im16 <"shr", 0xD3, MRM5m >, OpSize, UsesCL; // [mem16] >>= cl def SHR32mCL : Im32 <"shr", 0xD3, MRM5m > , UsesCL; // [mem32] >>= cl From lattner at cs.uiuc.edu Sun Aug 1 03:12:23 2004 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Sun, 1 Aug 2004 03:12:23 -0500 Subject: [llvm-commits] CVS: llvm/lib/Target/X86/X86RegisterInfo.td Message-ID: <200408010812.DAA17663@apoc.cs.uiuc.edu> Changes in directory llvm/lib/Target/X86: X86RegisterInfo.td updated: 1.9 -> 1.10 --- Log message: give FP stack registers names --- Diffs of the changes: (+5 -2) Index: llvm/lib/Target/X86/X86RegisterInfo.td diff -u llvm/lib/Target/X86/X86RegisterInfo.td:1.9 llvm/lib/Target/X86/X86RegisterInfo.td:1.10 --- llvm/lib/Target/X86/X86RegisterInfo.td:1.9 Sun Feb 29 03:17:01 2004 +++ llvm/lib/Target/X86/X86RegisterInfo.td Sun Aug 1 03:12:13 2004 @@ -101,7 +101,10 @@ def RFP : RegisterClass; -// Registers which cannot be allocated... and are thus left unnamed. -def : RegisterClass; +// Floating point stack registers. +def RST : RegisterClass; + + +// Registers which cannot be allocated. //def : RegisterClass; From lattner at cs.uiuc.edu Sun Aug 1 03:12:51 2004 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Sun, 1 Aug 2004 03:12:51 -0500 Subject: [llvm-commits] CVS: llvm/lib/Target/X86/X86AsmPrinter.cpp Message-ID: <200408010812.DAA17681@apoc.cs.uiuc.edu> Changes in directory llvm/lib/Target/X86: X86AsmPrinter.cpp updated: 1.108 -> 1.109 --- Log message: Handle registers a bit more efficiently --- Diffs of the changes: (+7 -1) Index: llvm/lib/Target/X86/X86AsmPrinter.cpp diff -u llvm/lib/Target/X86/X86AsmPrinter.cpp:1.108 llvm/lib/Target/X86/X86AsmPrinter.cpp:1.109 --- llvm/lib/Target/X86/X86AsmPrinter.cpp:1.108 Sun Aug 1 02:43:46 2004 +++ llvm/lib/Target/X86/X86AsmPrinter.cpp Sun Aug 1 03:12:41 2004 @@ -106,7 +106,13 @@ // This method is used by the tablegen'erated instruction printer. void printOperand(const MachineOperand &MO, MVT::ValueType VT) { - printOp(MO); + if (MO.getType() == MachineOperand::MO_MachineRegister) { + assert(MRegisterInfo::isPhysicalRegister(MO.getReg())&&"Not physref??"); + // Bug Workaround: See note in Printer::doInitialization about %. + O << "%" << TM.getRegisterInfo()->get(MO.getReg()).Name; + } else { + printOp(MO); + } } void printImplUsesBefore(const TargetInstrDescriptor &Desc); From lattner at cs.uiuc.edu Sun Aug 1 03:13:21 2004 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Sun, 1 Aug 2004 03:13:21 -0500 Subject: [llvm-commits] CVS: llvm/lib/Target/X86/X86InstrInfo.td Message-ID: <200408010813.DAA17693@apoc.cs.uiuc.edu> Changes in directory llvm/lib/Target/X86: X86InstrInfo.td updated: 1.84 -> 1.85 --- Log message: Convert more instructions over to the asmprinter --- Diffs of the changes: (+66 -50) Index: llvm/lib/Target/X86/X86InstrInfo.td diff -u llvm/lib/Target/X86/X86InstrInfo.td:1.84 llvm/lib/Target/X86/X86InstrInfo.td:1.85 --- llvm/lib/Target/X86/X86InstrInfo.td:1.84 Sun Aug 1 02:44:35 2004 +++ llvm/lib/Target/X86/X86InstrInfo.td Sun Aug 1 03:13:11 2004 @@ -152,9 +152,6 @@ class Im16i8 o, Format f> : X86Inst; class Im32i8 o, Format f> : X86Inst; -// Helper for shift instructions -class UsesCL { list Uses = [CL]; bit printImplicitUsesAfter = 1; } - //===----------------------------------------------------------------------===// // Instruction list... // @@ -519,15 +516,17 @@ // Shift instructions // FIXME: provide shorter instructions when imm8 == 1 -def SHL8rCL : I <"shl", 0xD2, MRM4r > , UsesCL, // R8 <<= cl - II<(ops R8:$dst, R8:$src), "shl $dst, %CL">; -def SHL16rCL : I <"shl", 0xD3, MRM4r >, OpSize, UsesCL, // R16 <<= cl - II<(ops R16:$dst, R16:$src), "shl $dst, %CL">; -def SHL32rCL : I <"shl", 0xD3, MRM4r > , UsesCL, // R32 <<= cl - II<(ops R32:$dst, R32:$src), "shl $dst, %CL">; -def SHL8mCL : Im8 <"shl", 0xD2, MRM4m > , UsesCL; // [mem8] <<= cl -def SHL16mCL : Im16 <"shl", 0xD3, MRM4m >, OpSize, UsesCL; // [mem16] <<= cl -def SHL32mCL : Im32 <"shl", 0xD3, MRM4m > , UsesCL; // [mem32] <<= cl +let Uses = [CL], printImplicitUsesAfter = 1 in { + def SHL8rCL : I <"shl", 0xD2, MRM4r > , // R8 <<= cl + II<(ops R8:$dst, R8:$src), "shl $dst, %CL">; + def SHL16rCL : I <"shl", 0xD3, MRM4r >, OpSize, // R16 <<= cl + II<(ops R16:$dst, R16:$src), "shl $dst, %CL">; + def SHL32rCL : I <"shl", 0xD3, MRM4r > , // R32 <<= cl + II<(ops R32:$dst, R32:$src), "shl $dst, %CL">; + def SHL8mCL : Im8 <"shl", 0xD2, MRM4m > ; // [mem8] <<= cl + def SHL16mCL : Im16 <"shl", 0xD3, MRM4m >, OpSize; // [mem16] <<= cl + def SHL32mCL : Im32 <"shl", 0xD3, MRM4m > ; // [mem32] <<= cl +} def SHL8ri : Ii8 <"shl", 0xC0, MRM4r >; // R8 <<= imm8 def SHL16ri : Ii8 <"shl", 0xC1, MRM4r >, OpSize; // R16 <<= imm8 @@ -536,15 +535,17 @@ def SHL16mi : Im16i8<"shl", 0xC1, MRM4m >, OpSize; // [mem16] <<= imm8 def SHL32mi : Im32i8<"shl", 0xC1, MRM4m >; // [mem32] <<= imm8 -def SHR8rCL : I <"shr", 0xD2, MRM5r > , UsesCL, // R8 >>= cl - II<(ops R8:$dst, R8:$src), "shr $dst, %CL">; -def SHR16rCL : I <"shr", 0xD3, MRM5r >, OpSize, UsesCL, // R16 >>= cl - II<(ops R16:$dst, R16:$src), "shr $dst, %CL">; -def SHR32rCL : I <"shr", 0xD3, MRM5r > , UsesCL, // R32 >>= cl - II<(ops R32:$dst, R32:$src), "shr $dst, %CL">; -def SHR8mCL : Im8 <"shr", 0xD2, MRM5m > , UsesCL; // [mem8] >>= cl -def SHR16mCL : Im16 <"shr", 0xD3, MRM5m >, OpSize, UsesCL; // [mem16] >>= cl -def SHR32mCL : Im32 <"shr", 0xD3, MRM5m > , UsesCL; // [mem32] >>= cl +let Uses = [CL], printImplicitUsesAfter = 1 in { + def SHR8rCL : I <"shr", 0xD2, MRM5r > , // R8 >>= cl + II<(ops R8:$dst, R8:$src), "shr $dst, %CL">; + def SHR16rCL : I <"shr", 0xD3, MRM5r >, OpSize, // R16 >>= cl + II<(ops R16:$dst, R16:$src), "shr $dst, %CL">; + def SHR32rCL : I <"shr", 0xD3, MRM5r > , // R32 >>= cl + II<(ops R32:$dst, R32:$src), "shr $dst, %CL">; + def SHR8mCL : Im8 <"shr", 0xD2, MRM5m > ; // [mem8] >>= cl + def SHR16mCL : Im16 <"shr", 0xD3, MRM5m >, OpSize; // [mem16] >>= cl + def SHR32mCL : Im32 <"shr", 0xD3, MRM5m > ; // [mem32] >>= cl +} def SHR8ri : Ii8 <"shr", 0xC0, MRM5r >; // R8 >>= imm8 def SHR16ri : Ii8 <"shr", 0xC1, MRM5r >, OpSize; // R16 >>= imm8 @@ -553,12 +554,17 @@ def SHR16mi : Im16i8<"shr", 0xC1, MRM5m >, OpSize; // [mem16] >>= imm8 def SHR32mi : Im32i8<"shr", 0xC1, MRM5m >; // [mem32] >>= imm8 -def SAR8rCL : I <"sar", 0xD2, MRM7r > , UsesCL; // R8 >>>= cl -def SAR16rCL : I <"sar", 0xD3, MRM7r >, OpSize, UsesCL; // R16 >>>= cl -def SAR32rCL : I <"sar", 0xD3, MRM7r > , UsesCL; // R32 >>>= cl -def SAR8mCL : Im8 <"sar", 0xD2, MRM7m > , UsesCL; // [mem8] >>>= cl -def SAR16mCL : Im16 <"sar", 0xD3, MRM7m >, OpSize, UsesCL; // [mem16] >>>= cl -def SAR32mCL : Im32 <"sar", 0xD3, MRM7m > , UsesCL; // [mem32] >>>= cl +let Uses = [CL], printImplicitUsesAfter = 1 in { + def SAR8rCL : I <"sar", 0xD2, MRM7r >, // R8 >>>= cl + II<(ops R8:$dst, R8:$src), "sar $dst, %CL">; + def SAR16rCL : I <"sar", 0xD3, MRM7r >, OpSize, // R16 >>>= cl + II<(ops R16:$dst, R16:$src), "sar $dst, %CL">; + def SAR32rCL : I <"sar", 0xD3, MRM7r >, // R32 >>>= cl + II<(ops R32:$dst, R32:$src), "sar $dst, %CL">; + def SAR8mCL : Im8 <"sar", 0xD2, MRM7m > ; // [mem8] >>>= cl + def SAR16mCL : Im16 <"sar", 0xD3, MRM7m >, OpSize; // [mem16] >>>= cl + def SAR32mCL : Im32 <"sar", 0xD3, MRM7m > ; // [mem32] >>>= cl +} def SAR8ri : Ii8 <"sar", 0xC0, MRM7r >; // R8 >>>= imm8 def SAR16ri : Ii8 <"sar", 0xC1, MRM7r >, OpSize; // R16 >>>= imm8 @@ -567,13 +573,17 @@ def SAR16mi : Im16i8<"sar", 0xC1, MRM7m >, OpSize; // [mem16] >>>= imm8 def SAR32mi : Im32i8<"sar", 0xC1, MRM7m >; // [mem32] >>>= imm8 -def SHLD32rrCL : I <"shld", 0xA5, MRMDestReg>, TB, UsesCL; // R32 <<= R32,R32 cl -def SHLD32mrCL : Im32 <"shld", 0xA5, MRMDestMem>, TB, UsesCL; // [mem32] <<= [mem32],R32 cl +let Uses = [CL], printImplicitUsesAfter = 1 in { + def SHLD32rrCL : I <"shld", 0xA5, MRMDestReg>, TB, // R32 <<= R32,R32 cl + II<(ops R32:$dst, R32:$src1, R32:$src2), "shld $dst, $src2, %CL">; + def SHLD32mrCL : Im32 <"shld", 0xA5, MRMDestMem>, TB; // [mem32] <<= [mem32],R32 cl + def SHRD32rrCL : I <"shrd", 0xAD, MRMDestReg>, TB, // R32 >>= R32,R32 cl + II<(ops R32:$dst, R32:$src1, R32:$src2), "shrd $dst, $src2, %CL">; + def SHRD32mrCL : Im32 <"shrd", 0xAD, MRMDestMem>, TB; // [mem32] >>= [mem32],R32 cl +} + def SHLD32rri8 : Ii8 <"shld", 0xA4, MRMDestReg>, TB; // R32 <<= R32,R32 imm8 def SHLD32mri8 : Im32i8<"shld", 0xA4, MRMDestMem>, TB; // [mem32] <<= [mem32],R32 imm8 - -def SHRD32rrCL : I <"shrd", 0xAD, MRMDestReg>, TB, UsesCL; // R32 >>= R32,R32 cl -def SHRD32mrCL : Im32 <"shrd", 0xAD, MRMDestMem>, TB, UsesCL; // [mem32] >>= [mem32],R32 cl def SHRD32rri8 : Ii8 <"shrd", 0xAC, MRMDestReg>, TB; // R32 >>= R32,R32 imm8 def SHRD32mri8 : Im32i8<"shrd", 0xAC, MRMDestMem>, TB; // [mem32] >>= [mem32],R32 imm8 @@ -815,13 +825,19 @@ // Floating point cmovs... -let isTwoAddress = 1, Uses = [ST0], Defs = [ST0], printImplicitUsesBefore = 1 in { - def FCMOVB : FPI <"fcmovb" , 0xC0, AddRegFrm, CondMovFP>, DA; // fcmovb ST(i) -> ST(0) - def FCMOVBE : FPI <"fcmovbe", 0xD0, AddRegFrm, CondMovFP>, DA; // fcmovbe ST(i) -> ST(0) - def FCMOVE : FPI <"fcmove" , 0xC8, AddRegFrm, CondMovFP>, DA; // fcmove ST(i) -> ST(0) - def FCMOVAE : FPI <"fcmovae", 0xC0, AddRegFrm, CondMovFP>, DB; // fcmovae ST(i) -> ST(0) - def FCMOVA : FPI <"fcmova" , 0xD0, AddRegFrm, CondMovFP>, DB; // fcmova ST(i) -> ST(0) - def FCMOVNE : FPI <"fcmovne", 0xC8, AddRegFrm, CondMovFP>, DB; // fcmovne ST(i) -> ST(0) +let isTwoAddress = 1, Uses = [ST0], Defs = [ST0] in { + def FCMOVB : FPI<"fcmovb" , 0xC0, AddRegFrm, CondMovFP>, DA, // fcmovb ST(i) -> ST(0) + II<(ops RST:$op), "fcmovb %ST(0), $op">; + def FCMOVBE : FPI<"fcmovbe", 0xD0, AddRegFrm, CondMovFP>, DA, // fcmovbe ST(i) -> ST(0) + II<(ops RST:$op), "fcmovbe %ST(0), $op">; + def FCMOVE : FPI<"fcmove" , 0xC8, AddRegFrm, CondMovFP>, DA, // fcmove ST(i) -> ST(0) + II<(ops RST:$op), "fcmove %ST(0), $op">; + def FCMOVAE : FPI<"fcmovae", 0xC0, AddRegFrm, CondMovFP>, DB, // fcmovae ST(i) -> ST(0) + II<(ops RST:$op), "fcmovae %ST(0), $op">; + def FCMOVA : FPI<"fcmova" , 0xD0, AddRegFrm, CondMovFP>, DB, // fcmova ST(i) -> ST(0) + II<(ops RST:$op), "fcmova %ST(0), $op">; + def FCMOVNE : FPI<"fcmovne", 0xC8, AddRegFrm, CondMovFP>, DB, // fcmovne ST(i) -> ST(0) + II<(ops RST:$op), "fcmovne %ST(0), $op">; } // Floating point loads & stores... @@ -868,7 +884,6 @@ list Defs = [ST0]; } class FPrST0Inst o> : I, DC { - bit printImplicitUsesAfter = 1; list Uses = [ST0]; } class FPrST0PInst o> : I, DE { @@ -876,27 +891,27 @@ } def FADDST0r : FPST0rInst <"fadd", 0xC0>; -def FADDrST0 : FPrST0Inst <"fadd", 0xC0>; +def FADDrST0 : FPrST0Inst <"fadd", 0xC0>, II<(ops RST:$op), "fadd $op, %ST(0)">; def FADDPrST0 : FPrST0PInst<"faddp", 0xC0>; def FSUBRST0r : FPST0rInst <"fsubr", 0xE8>; -def FSUBrST0 : FPrST0Inst <"fsub", 0xE8>; +def FSUBrST0 : FPrST0Inst <"fsub", 0xE8>, II<(ops RST:$op), "fsub $op, %ST(0)">; def FSUBPrST0 : FPrST0PInst<"fsubp", 0xE8>; def FSUBST0r : FPST0rInst <"fsub", 0xE0>; -def FSUBRrST0 : FPrST0Inst <"fsubr", 0xE0>; +def FSUBRrST0 : FPrST0Inst <"fsubr", 0xE0>, II<(ops RST:$op), "fsubr $op, %ST(0)">; def FSUBRPrST0 : FPrST0PInst<"fsubrp", 0xE0>; def FMULST0r : FPST0rInst <"fmul", 0xC8>; -def FMULrST0 : FPrST0Inst <"fmul", 0xC8>; +def FMULrST0 : FPrST0Inst <"fmul", 0xC8>, II<(ops RST:$op), "fmul $op, %ST(0)">; def FMULPrST0 : FPrST0PInst<"fmulp", 0xC8>; def FDIVRST0r : FPST0rInst <"fdivr", 0xF8>; -def FDIVrST0 : FPrST0Inst <"fdiv", 0xF8>; +def FDIVrST0 : FPrST0Inst <"fdiv", 0xF8>, II<(ops RST:$op), "fdiv $op, %ST(0)">; def FDIVPrST0 : FPrST0PInst<"fdivp", 0xF8>; def FDIVST0r : FPST0rInst <"fdiv", 0xF0>; // ST(0) = ST(0) / ST(i) -def FDIVRrST0 : FPrST0Inst <"fdivr", 0xF0>; // ST(i) = ST(0) / ST(i) +def FDIVRrST0 : FPrST0Inst <"fdivr", 0xF0>, II<(ops RST:$op), "fdivr $op, %ST(0)">; // ST(i) = ST(0) / ST(i) def FDIVRPrST0 : FPrST0PInst<"fdivrp", 0xF0>; // ST(i) = ST(0) / ST(i), pop // Floating point compares @@ -906,10 +921,11 @@ II<(ops), "fucompp">; -let printImplicitUsesBefore = 1 in { - def FUCOMIr : FPI<"fucomi", 0xE8, AddRegFrm, CompareFP>, DB, Imp<[ST0],[]>; // CC = compare ST(0) with ST(i) - def FUCOMIPr : I<"fucomip", 0xE8, AddRegFrm>, DF, Imp<[ST0],[]>; // CC = compare ST(0) with ST(i), pop -} +def FUCOMIr : FPI<"fucomi", 0xE8, AddRegFrm, CompareFP>, DB, Imp<[ST0],[]>, // CC = compare ST(0) with ST(i) + II<(ops RST:$reg), "fucomi %ST(0), $reg">; +def FUCOMIPr : I<"fucomip", 0xE8, AddRegFrm>, DF, Imp<[ST0],[]>, // CC = compare ST(0) with ST(i), pop + II<(ops RST:$reg), "fucomip %ST(0), $reg">; + // Floating point flag ops def FNSTSW8r : I <"fnstsw" , 0xE0, RawFrm>, DF, Imp<[],[AX]>, // AX = fp flags From lattner at cs.uiuc.edu Sun Aug 1 03:22:39 2004 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Sun, 1 Aug 2004 03:22:39 -0500 Subject: [llvm-commits] CVS: llvm/lib/Target/X86/X86AsmPrinter.cpp Message-ID: <200408010822.DAA19675@apoc.cs.uiuc.edu> Changes in directory llvm/lib/Target/X86: X86AsmPrinter.cpp updated: 1.109 -> 1.110 --- Log message: Get rid of 3 of the 4 'printimplicit' flags. Implicit operands are now explicitly listed in the asm string. --- Diffs of the changes: (+1 -79) Index: llvm/lib/Target/X86/X86AsmPrinter.cpp diff -u llvm/lib/Target/X86/X86AsmPrinter.cpp:1.109 llvm/lib/Target/X86/X86AsmPrinter.cpp:1.110 --- llvm/lib/Target/X86/X86AsmPrinter.cpp:1.109 Sun Aug 1 03:12:41 2004 +++ llvm/lib/Target/X86/X86AsmPrinter.cpp Sun Aug 1 03:22:29 2004 @@ -115,10 +115,7 @@ } } - void printImplUsesBefore(const TargetInstrDescriptor &Desc); - bool printImplDefsBefore(const TargetInstrDescriptor &Desc); bool printImplUsesAfter(const TargetInstrDescriptor &Desc, const bool LC); - bool printImplDefsAfter(const TargetInstrDescriptor &Desc, const bool LC); void printMachineInstruction(const MachineInstr *MI); void printOp(const MachineOperand &MO, bool elideOffsetKeyword = false); void printMemReference(const MachineInstr *MI, unsigned Op); @@ -538,44 +535,6 @@ O << "]"; } - -/// printImplUsesBefore - Emit the implicit-use registers for the instruction -/// described by DESC, if its PrintImplUsesBefore flag is set. -/// -void X86AsmPrinter::printImplUsesBefore(const TargetInstrDescriptor &Desc) { - const MRegisterInfo &RI = *TM.getRegisterInfo(); - if (Desc.TSFlags & X86II::PrintImplUsesBefore) { - for (const unsigned *p = Desc.ImplicitUses; *p; ++p) { - // Bug Workaround: See note in X86AsmPrinter::doInitialization about %. - O << "%" << RI.get(*p).Name << ", "; - } - } -} - -/// printImplDefsBefore - Emit the implicit-def registers for the instruction -/// described by DESC, if its PrintImplUsesBefore flag is set. Return true if -/// we printed any registers. -/// -bool X86AsmPrinter::printImplDefsBefore(const TargetInstrDescriptor &Desc) { - bool Printed = false; - const MRegisterInfo &RI = *TM.getRegisterInfo(); - if (Desc.TSFlags & X86II::PrintImplDefsBefore) { - const unsigned *p = Desc.ImplicitDefs; - if (*p) { - O << (Printed ? ", %" : "%") << RI.get (*p).Name; - Printed = true; - ++p; - } - while (*p) { - // Bug Workaround: See note in X86AsmPrinter::doInitialization about %. - O << ", %" << RI.get(*p).Name; - ++p; - } - } - return Printed; -} - - /// printImplUsesAfter - Emit the implicit-use registers for the instruction /// described by DESC, if its PrintImplUsesAfter flag is set. /// @@ -608,38 +567,6 @@ return false; } -/// printImplDefsAfter - Emit the implicit-definition registers for the -/// instruction described by DESC, if its PrintImplDefsAfter flag is set. -/// -/// Inputs: -/// Comma - List of registers will need a leading comma. -/// Desc - Description of the Instruction -/// -/// Return value: -/// true - Emitted one or more registers. -/// false - Emitted no registers. -/// -bool X86AsmPrinter::printImplDefsAfter(const TargetInstrDescriptor &Desc, - const bool Comma = true) { - const MRegisterInfo &RI = *TM.getRegisterInfo(); - if (Desc.TSFlags & X86II::PrintImplDefsAfter) { - bool emitted = false; - const unsigned *p = Desc.ImplicitDefs; - if (*p) { - O << (Comma ? ", %" : "%") << RI.get (*p).Name; - emitted = true; - ++p; - } - while (*p) { - // Bug Workaround: See note in X86AsmPrinter::doInitialization about %. - O << ", %" << RI.get(*p).Name; - ++p; - } - return emitted; - } - return false; -} - /// printMachineInstruction -- Print out a single X86 LLVM instruction /// MI in Intel syntax to the current output stream. /// @@ -703,14 +630,11 @@ "Illegal raw instruction!"); O << TII.getName(MI->getOpcode()) << " "; - bool LeadingComma = printImplDefsBefore(Desc); - + bool LeadingComma = false; if (MI->getNumOperands() == 1) { - if (LeadingComma) O << ", "; printOp(MI->getOperand(0), true); // Don't print "OFFSET"... LeadingComma = true; } - LeadingComma = printImplDefsAfter(Desc, LeadingComma) || LeadingComma; printImplUsesAfter(Desc, LeadingComma); O << "\n"; return; @@ -739,8 +663,6 @@ O << TII.getName(MI->getOpcode()) << " "; - printImplUsesBefore(Desc); // fcmov* - printOp(MI->getOperand(0)); if (MI->getNumOperands() == 2 && (!MI->getOperand(1).isRegister() || From lattner at cs.uiuc.edu Sun Aug 1 03:23:27 2004 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Sun, 1 Aug 2004 03:23:27 -0500 Subject: [llvm-commits] CVS: llvm/lib/Target/X86/X86.td X86InstrInfo.h X86InstrInfo.td Message-ID: <200408010823.DAA19692@apoc.cs.uiuc.edu> Changes in directory llvm/lib/Target/X86: X86.td updated: 1.11 -> 1.12 X86InstrInfo.h updated: 1.41 -> 1.42 X86InstrInfo.td updated: 1.85 -> 1.86 --- Log message: Eliminate 3 of the X86 printImplicit* flags. --- Diffs of the changes: (+3 -25) Index: llvm/lib/Target/X86/X86.td diff -u llvm/lib/Target/X86/X86.td:1.11 llvm/lib/Target/X86/X86.td:1.12 --- llvm/lib/Target/X86/X86.td:1.11 Tue Apr 13 12:18:39 2004 +++ llvm/lib/Target/X86/X86.td Sun Aug 1 03:23:17 2004 @@ -40,9 +40,6 @@ "ImmTypeBits", "FPFormBits", "printImplicitUsesAfter", - "printImplicitUsesBefore", - "printImplicitDefsBefore", - "printImplicitDefsAfter", "Opcode"]; let TSFlagsShifts = [0, 5, @@ -51,10 +48,7 @@ 13, 15, 18, - 19, - 20, - 21, - 22]; + 19]; } def X86 : Target { Index: llvm/lib/Target/X86/X86InstrInfo.h diff -u llvm/lib/Target/X86/X86InstrInfo.h:1.41 llvm/lib/Target/X86/X86InstrInfo.h:1.42 --- llvm/lib/Target/X86/X86InstrInfo.h:1.41 Sat Jul 31 04:38:47 2004 +++ llvm/lib/Target/X86/X86InstrInfo.h Sun Aug 1 03:23:17 2004 @@ -169,16 +169,7 @@ // the normal operands. PrintImplUsesAfter = 1 << 18, - // PrintImplUsesBefore - Print out implicit uses in the assembly output - // before the normal operands. - PrintImplUsesBefore = 1 << 19, - - // PrintImplDefsAfter - Print out implicit defs in the assembly output - // after the normal operands. - PrintImplDefsBefore = 1 << 20, - PrintImplDefsAfter = 1 << 21, - - OpcodeShift = 22, + OpcodeShift = 19, OpcodeMask = 0xFF << OpcodeShift, // Bits 27 -> 31 are unused }; Index: llvm/lib/Target/X86/X86InstrInfo.td diff -u llvm/lib/Target/X86/X86InstrInfo.td:1.85 llvm/lib/Target/X86/X86InstrInfo.td:1.86 --- llvm/lib/Target/X86/X86InstrInfo.td:1.85 Sun Aug 1 03:13:11 2004 +++ llvm/lib/Target/X86/X86InstrInfo.td Sun Aug 1 03:23:17 2004 @@ -88,16 +88,9 @@ // bit hasOpSizePrefix = 0; // Does this inst have a 0x66 prefix? - // Flag whether implicit register usage is printed before/after the - // instruction - bit printImplicitUsesBefore = 0; + // Flag whether implicit register usage is printed after the instruction. bit printImplicitUsesAfter = 0; - // Flag whether implicit register definitions are printed before/after the - // instruction - bit printImplicitDefsBefore = 0; - bit printImplicitDefsAfter = 0; - bits<4> Prefix = 0; // Which prefix byte does this inst have? FPFormat FPForm; // What flavor of FP instruction is this? bits<3> FPFormBits = 0; From lattner at cs.uiuc.edu Sun Aug 1 03:38:27 2004 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Sun, 1 Aug 2004 03:38:27 -0500 Subject: [llvm-commits] CVS: llvm/utils/TableGen/InstrInfoEmitter.cpp Message-ID: <200408010838.DAA20380@apoc.cs.uiuc.edu> Changes in directory llvm/utils/TableGen: InstrInfoEmitter.cpp updated: 1.11 -> 1.12 --- Log message: Instructions no longer need to have names. --- Diffs of the changes: (+6 -1) Index: llvm/utils/TableGen/InstrInfoEmitter.cpp diff -u llvm/utils/TableGen/InstrInfoEmitter.cpp:1.11 llvm/utils/TableGen/InstrInfoEmitter.cpp:1.12 --- llvm/utils/TableGen/InstrInfoEmitter.cpp:1.11 Sun Aug 1 00:04:00 2004 +++ llvm/utils/TableGen/InstrInfoEmitter.cpp Sun Aug 1 03:38:17 2004 @@ -97,7 +97,12 @@ void InstrInfoEmitter::emitRecord(const CodeGenInstruction &Inst, unsigned Num, Record *InstrInfo, std::ostream &OS) { - OS << " { \"" << Inst.Name << "\",\t-1, -1, 0, false, 0, 0, 0, 0"; + OS << " { \""; + if (Inst.Name.empty()) + OS << Inst.TheDef->getName(); + else + OS << Inst.Name; + OS << "\",\t-1, -1, 0, false, 0, 0, 0, 0"; // Emit all of the target indepedent flags... if (Inst.isReturn) OS << "|M_RET_FLAG"; From lattner at cs.uiuc.edu Sun Aug 1 03:55:44 2004 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Sun, 1 Aug 2004 03:55:44 -0500 Subject: [llvm-commits] CVS: llvm/utils/TableGen/AsmWriterEmitter.cpp Message-ID: <200408010855.DAA24057@apoc.cs.uiuc.edu> Changes in directory llvm/utils/TableGen: AsmWriterEmitter.cpp updated: 1.2 -> 1.3 --- Log message: Be picky --- Diffs of the changes: (+5 -1) Index: llvm/utils/TableGen/AsmWriterEmitter.cpp diff -u llvm/utils/TableGen/AsmWriterEmitter.cpp:1.2 llvm/utils/TableGen/AsmWriterEmitter.cpp:1.3 --- llvm/utils/TableGen/AsmWriterEmitter.cpp:1.2 Sun Aug 1 02:43:02 2004 +++ llvm/utils/TableGen/AsmWriterEmitter.cpp Sun Aug 1 03:55:34 2004 @@ -75,8 +75,12 @@ // If this is a two-address instruction and we are not accessing the // 0th operand, remove an operand. - if (I->second.isTwoAddress && OpNo != 0) + if (I->second.isTwoAddress && OpNo != 0) { + if (OpNo == 1) + throw "Should refer to operand #0 instead of #1 for two-address" + " instruction '" + I->first + "'!"; --OpNo; + } O << "; printOperand(MI->getOperand(" << OpNo << "), MVT::" << getName(I->second.OperandList[OpNo].Ty) << "); O "; From lattner at cs.uiuc.edu Sun Aug 1 04:36:54 2004 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Sun, 1 Aug 2004 04:36:54 -0500 Subject: [llvm-commits] CVS: llvm/lib/Target/Target.td Message-ID: <200408010936.EAA01552@apoc.cs.uiuc.edu> Changes in directory llvm/lib/Target: Target.td updated: 1.28 -> 1.29 --- Log message: Add some immediate forms, make name optional --- Diffs of the changes: (+5 -2) Index: llvm/lib/Target/Target.td diff -u llvm/lib/Target/Target.td:1.28 llvm/lib/Target/Target.td:1.29 --- llvm/lib/Target/Target.td:1.28 Sat Jul 31 23:40:43 2004 +++ llvm/lib/Target/Target.td Sun Aug 1 04:36:44 2004 @@ -106,7 +106,7 @@ // the Target/TargetInstrInfo.h file. // class Instruction { - string Name; // The opcode string for this instruction + string Name = ""; // The opcode string for this instruction string Namespace = ""; dag OperandList; // An dag containing the MI operand list. @@ -151,7 +151,10 @@ /// list for an instruction. This should be used like this: /// (ops R32:$dst, R32:$src) or something similar. def ops; - +def i8imm; +def i16imm; +def i32imm; +def i64imm; //===----------------------------------------------------------------------===// // Target - This class contains the "global" target information From lattner at cs.uiuc.edu Sun Aug 1 04:51:52 2004 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Sun, 1 Aug 2004 04:51:52 -0500 Subject: [llvm-commits] CVS: llvm/lib/CodeGen/BranchFolding.cpp Message-ID: <200408010951.EAA03829@apoc.cs.uiuc.edu> Changes in directory llvm/lib/CodeGen: BranchFolding.cpp updated: 1.5 -> 1.6 --- Log message: Dereferencing end() is bad. --- Diffs of the changes: (+1 -1) Index: llvm/lib/CodeGen/BranchFolding.cpp diff -u llvm/lib/CodeGen/BranchFolding.cpp:1.5 llvm/lib/CodeGen/BranchFolding.cpp:1.6 --- llvm/lib/CodeGen/BranchFolding.cpp:1.5 Sat Jul 31 14:24:41 2004 +++ llvm/lib/CodeGen/BranchFolding.cpp Sun Aug 1 04:51:42 2004 @@ -96,7 +96,7 @@ // If BB falls through into Old, insert an unconditional branch to New. MachineFunction::iterator BBSucc = BB; ++BBSucc; - if (&*BBSucc == Old) + if (BBSucc != BB->getParent()->end() && &*BBSucc == Old) TII.insertGoto(*BB, *New); std::vector Succs(BB->succ_begin(), BB->succ_end()); From lattner at cs.uiuc.edu Sun Aug 1 04:53:09 2004 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Sun, 1 Aug 2004 04:53:09 -0500 Subject: [llvm-commits] CVS: llvm/lib/Target/X86/X86InstrInfo.td Message-ID: <200408010953.EAA04045@apoc.cs.uiuc.edu> Changes in directory llvm/lib/Target/X86: X86InstrInfo.td updated: 1.86 -> 1.87 --- Log message: Convert all I<> instructions to asmformat. Delete the 'name' field of all instructions that have asmformats. --- Diffs of the changes: (+308 -230) Index: llvm/lib/Target/X86/X86InstrInfo.td diff -u llvm/lib/Target/X86/X86InstrInfo.td:1.86 llvm/lib/Target/X86/X86InstrInfo.td:1.87 --- llvm/lib/Target/X86/X86InstrInfo.td:1.86 Sun Aug 1 03:23:17 2004 +++ llvm/lib/Target/X86/X86InstrInfo.td Sun Aug 1 04:52:59 2004 @@ -126,7 +126,7 @@ //===----------------------------------------------------------------------===// // Instruction templates... -class I o, Format f> : X86Inst; +class I o, Format f> : X86Inst<"", o, f, NoMem, NoImm>; class Im o, Format f, MemType m> : X86Inst; class Im8 o, Format f> : Im; @@ -149,17 +149,16 @@ // Instruction list... // -def PHI : I<"PHI", 0, Pseudo>; // PHI node... -def NOOP : I<"nop", 0x90, RawFrm>, // nop - II<(ops), "nop">; - -def ADJCALLSTACKDOWN : I<"ADJCALLSTACKDOWN", 0, Pseudo>; -def ADJCALLSTACKUP : I<"ADJCALLSTACKUP", 0, Pseudo>; -def IMPLICIT_USE : I<"IMPLICIT_USE", 0, Pseudo>; -def IMPLICIT_DEF : I<"IMPLICIT_DEF", 0, Pseudo>; +def PHI : I<0, Pseudo>; // PHI node. +def NOOP : I<0x90, RawFrm>, II<(ops), "nop">; // nop + +def ADJCALLSTACKDOWN : I<0, Pseudo>; +def ADJCALLSTACKUP : I<0, Pseudo>; +def IMPLICIT_USE : I<0, Pseudo>; +def IMPLICIT_DEF : I<0, Pseudo>; let isTerminator = 1 in let Defs = [FP0, FP1, FP2, FP3, FP4, FP5, FP6] in - def FP_REG_KILL : I<"FP_REG_KILL", 0, Pseudo>; + def FP_REG_KILL : I<0, Pseudo>; //===----------------------------------------------------------------------===// // Control Flow Instructions... @@ -167,27 +166,26 @@ // Return instruction... let isTerminator = 1, isReturn = 1, isBarrier = 1 in - def RET : I<"ret", 0xC3, RawFrm>, - II<(ops), "ret">; + def RET : I<0xC3, RawFrm>, II<(ops), "ret">; // All branches are RawFrm, Void, Branch, and Terminators let isBranch = 1, isTerminator = 1 in - class IBr opcode> : I; + class IBr opcode> : I; let isBarrier = 1 in - def JMP : IBr<"jmp", 0xE9>; -def JB : IBr<"jb" , 0x82>, TB; -def JAE : IBr<"jae", 0x83>, TB; -def JE : IBr<"je" , 0x84>, TB; -def JNE : IBr<"jne", 0x85>, TB; -def JBE : IBr<"jbe", 0x86>, TB; -def JA : IBr<"ja" , 0x87>, TB; -def JS : IBr<"js" , 0x88>, TB; -def JNS : IBr<"jns", 0x89>, TB; -def JL : IBr<"jl" , 0x8C>, TB; -def JGE : IBr<"jge", 0x8D>, TB; -def JLE : IBr<"jle", 0x8E>, TB; -def JG : IBr<"jg" , 0x8F>, TB; + def JMP : IBr<0xE9>, II<(ops i32imm:$dst), "jmp $dst">; +def JB : IBr<0x82>, TB, II<(ops i32imm:$dst), "jb $dst">; +def JAE : IBr<0x83>, TB, II<(ops i32imm:$dst), "jae $dst">; +def JE : IBr<0x84>, TB, II<(ops i32imm:$dst), "je $dst">; +def JNE : IBr<0x85>, TB, II<(ops i32imm:$dst), "jne $dst">; +def JBE : IBr<0x86>, TB, II<(ops i32imm:$dst), "jbe $dst">; +def JA : IBr<0x87>, TB, II<(ops i32imm:$dst), "ja $dst">; +def JS : IBr<0x88>, TB, II<(ops i32imm:$dst), "js $dst">; +def JNS : IBr<0x89>, TB, II<(ops i32imm:$dst), "jns $dst">; +def JL : IBr<0x8C>, TB, II<(ops i32imm:$dst), "jl $dst">; +def JGE : IBr<0x8D>, TB, II<(ops i32imm:$dst), "jge $dst">; +def JLE : IBr<0x8E>, TB, II<(ops i32imm:$dst), "jle $dst">; +def JG : IBr<0x8F>, TB, II<(ops i32imm:$dst), "jg $dst">; //===----------------------------------------------------------------------===// @@ -196,8 +194,8 @@ let isCall = 1 in // All calls clobber the non-callee saved registers... let Defs = [EAX, ECX, EDX, FP0, FP1, FP2, FP3, FP4, FP5, FP6] in { - def CALLpcrel32 : I <"call", 0xE8, RawFrm>; - def CALL32r : I <"call", 0xFF, MRM2r>; + def CALLpcrel32 : X86Inst<"call", 0xE8, RawFrm, NoMem, NoImm>; // FIXME: 'call' doesn't allow 'OFFSET' + def CALL32r : I<0xFF, MRM2r>, II<(ops R32:$dst), "call $dst">; def CALL32m : Im32<"call", 0xFF, MRM2m>; } @@ -205,16 +203,22 @@ //===----------------------------------------------------------------------===// // Miscellaneous Instructions... // -def LEAVE : I<"leave", 0xC9, RawFrm>, Imp<[EBP,ESP],[EBP,ESP]>, +def LEAVE : I<0xC9, RawFrm>, Imp<[EBP,ESP],[EBP,ESP]>, II<(ops), "leave">; -def POP32r : I<"pop", 0x58, AddRegFrm>, Imp<[ESP],[ESP]>; +def POP32r : I<0x58, AddRegFrm>, Imp<[ESP],[ESP]>, + II<(ops R32:$reg), "pop $reg">; let isTwoAddress = 1 in // R32 = bswap R32 - def BSWAP32r : I<"bswap", 0xC8, AddRegFrm>, TB; + def BSWAP32r : I<0xC8, AddRegFrm>, TB, + II<(ops R32:$dst, R32:$src), "bswap $dst">; + +def XCHG8rr : I<0x86, MRMDestReg>, // xchg R8, R8 + II<(ops R8:$src1, R8:$src2), "xchg $src1, $src2">; +def XCHG16rr : I<0x87, MRMDestReg>, OpSize, // xchg R16, R16 + II<(ops R16:$src1, R16:$src2), "xchg $src1, $src2">; +def XCHG32rr : I<0x87, MRMDestReg>, // xchg R32, R32 + II<(ops R32:$src1, R32:$src2), "xchg $src1, $src2">; -def XCHG8rr : I <"xchg", 0x86, MRMDestReg>; // xchg R8, R8 -def XCHG16rr : I <"xchg", 0x87, MRMDestReg>, OpSize; // xchg R16, R16 -def XCHG32rr : I <"xchg", 0x87, MRMDestReg>; // xchg R32, R32 def XCHG8mr : Im8 <"xchg", 0x86, MRMDestMem>; // xchg [mem8], R8 def XCHG16mr : Im16<"xchg", 0x87, MRMDestMem>, OpSize; // xchg [mem16], R16 def XCHG32mr : Im32<"xchg", 0x87, MRMDestMem>; // xchg [mem32], R32 @@ -226,72 +230,66 @@ def LEA32r : Im32<"lea", 0x8D, MRMSrcMem>; // R32 = lea [mem] -def REP_MOVSB : I<"rep movsb", 0xA4, RawFrm>, REP, +def REP_MOVSB : I<0xA4, RawFrm>, REP, Imp<[ECX,EDI,ESI], [ECX,EDI,ESI]>, II<(ops), "rep movsb">; -def REP_MOVSW : I<"rep movsw", 0xA5, RawFrm>, REP, OpSize, +def REP_MOVSW : I<0xA5, RawFrm>, REP, OpSize, Imp<[ECX,EDI,ESI], [ECX,EDI,ESI]>, II<(ops), "rep movsw">; -def REP_MOVSD : I<"rep movsd", 0xA5, RawFrm>, REP, +def REP_MOVSD : I<0xA5, RawFrm>, REP, Imp<[ECX,EDI,ESI], [ECX,EDI,ESI]>, II<(ops), "rep movsd">; -def REP_STOSB : I<"rep stosb", 0xAA, RawFrm>, REP, +def REP_STOSB : I<0xAA, RawFrm>, REP, Imp<[AL,ECX,EDI], [ECX,EDI]>, II<(ops), "rep stosb">; -def REP_STOSW : I<"rep stosw", 0xAB, RawFrm>, REP, OpSize, +def REP_STOSW : I<0xAB, RawFrm>, REP, OpSize, Imp<[AX,ECX,EDI], [ECX,EDI]>, II<(ops), "rep stosw">; -def REP_STOSD : I<"rep stosd", 0xAB, RawFrm>, REP, +def REP_STOSD : I<0xAB, RawFrm>, REP, Imp<[EAX,ECX,EDI], [ECX,EDI]>, II<(ops), "rep stosd">; //===----------------------------------------------------------------------===// // Input/Output Instructions... // -def IN8rr : I<"in", 0xEC, RawFrm>, Imp<[DX], [AL]>, // AL = in I/O address DX +def IN8rr : I<0xEC, RawFrm>, Imp<[DX], [AL]>, // AL = in I/O address DX II<(ops), "in %AL, %DX">; -def IN16rr : I<"in", 0xED, RawFrm>, Imp<[DX], [AX]>, OpSize, // AX = in I/O address DX +def IN16rr : I<0xED, RawFrm>, Imp<[DX], [AX]>, OpSize, // AX = in I/O address DX II<(ops), "in %AX, %DX">; -def IN32rr : I<"in", 0xED, RawFrm>, Imp<[DX],[EAX]>, // EAX = in I/O address DX +def IN32rr : I<0xED, RawFrm>, Imp<[DX],[EAX]>, // EAX = in I/O address DX II<(ops), "in %EAX, %DX">; -def IN8ri : Ii16<"in", 0xE4, RawFrm>, Imp<[], [AL]>, // AL = in [I/O address] +def IN8ri : Ii16<"", 0xE4, RawFrm>, Imp<[], [AL]>, // AL = in [I/O address] II<(ops i16imm:$port), "in %AL, $port">; -def IN16ri : Ii16<"in", 0xE5, RawFrm>, Imp<[], [AX]>, OpSize, // AX = in [I/O address] +def IN16ri : Ii16<"", 0xE5, RawFrm>, Imp<[], [AX]>, OpSize, // AX = in [I/O address] II<(ops i16imm:$port), "in %AX, $port">; -def IN32ri : Ii16<"in", 0xE5, RawFrm>, Imp<[],[EAX]>, // EAX = in [I/O address] +def IN32ri : Ii16<"", 0xE5, RawFrm>, Imp<[],[EAX]>, // EAX = in [I/O address] II<(ops i16imm:$port), "in %EAX, $port">; -def OUT8rr : I<"out", 0xEE, RawFrm>, Imp<[DX, AL], []>, +def OUT8rr : I<0xEE, RawFrm>, Imp<[DX, AL], []>, II<(ops), "out %DX, %AL">; -def OUT16rr : I<"out", 0xEF, RawFrm>, Imp<[DX, AX], []>, OpSize, +def OUT16rr : I<0xEF, RawFrm>, Imp<[DX, AX], []>, OpSize, II<(ops), "out %DX, %AX">; -def OUT32rr : I<"out", 0xEF, RawFrm>, Imp<[DX, EAX], []>, +def OUT32rr : I<0xEF, RawFrm>, Imp<[DX, EAX], []>, II<(ops), "out %DX, %EAX">; -def OUT8ir : Ii16<"out", 0xE6, RawFrm>, Imp<[AL], []>, +def OUT8ir : Ii16<"", 0xE6, RawFrm>, Imp<[AL], []>, II<(ops i16imm:$port), "out $port, %AL">; -def OUT16ir : Ii16<"out", 0xE7, RawFrm>, Imp<[AX], []>, OpSize, +def OUT16ir : Ii16<"", 0xE7, RawFrm>, Imp<[AX], []>, OpSize, II<(ops i16imm:$port), "out $port, %AX">; -def OUT32ir : Ii16<"out", 0xE7, RawFrm>, Imp<[EAX], []>, +def OUT32ir : Ii16<"", 0xE7, RawFrm>, Imp<[EAX], []>, II<(ops i16imm:$port), "out $port, %EAX">; //===----------------------------------------------------------------------===// // Move Instructions... // -def MOV8rr : I <"mov", 0x88, MRMDestReg>, - II<(ops R8:$dst, R8:$src), "mov $dst, $src">; -def MOV16rr : I <"mov", 0x89, MRMDestReg>, OpSize, - II<(ops R16:$dst, R16:$src), "mov $dst, $src">; -def MOV32rr : I <"mov", 0x89, MRMDestReg>, - II<(ops R32:$dst, R32:$src), "mov $dst, $src">; -def MOV8ri : Ii8 <"mov", 0xB0, AddRegFrm >, - II<(ops R8:$dst, i8imm:$src), "mov $dst, $src">; -def MOV16ri : Ii16 <"mov", 0xB8, AddRegFrm >, OpSize, - II<(ops R16:$dst, i16imm:$src), "mov $dst, $src">; -def MOV32ri : Ii32 <"mov", 0xB8, AddRegFrm >, - II<(ops R32:$dst, i32imm:$src), "mov $dst, $src">; +def MOV8rr : I<0x88, MRMDestReg>, II<(ops R8 :$dst, R8 :$src), "mov $dst, $src">; +def MOV16rr : I<0x89, MRMDestReg>, OpSize, II<(ops R16:$dst, R16 :$src), "mov $dst, $src">; +def MOV32rr : I<0x89, MRMDestReg>, II<(ops R32:$dst, R32 :$src), "mov $dst, $src">; +def MOV8ri : Ii8 <"", 0xB0, AddRegFrm >, II<(ops R8 :$dst, i8imm :$src), "mov $dst, $src">; +def MOV16ri : Ii16 <"", 0xB8, AddRegFrm >, OpSize, II<(ops R16:$dst, i16imm:$src), "mov $dst, $src">; +def MOV32ri : Ii32 <"", 0xB8, AddRegFrm >, II<(ops R32:$dst, i32imm:$src), "mov $dst, $src">; def MOV8mi : Im8i8 <"mov", 0xC6, MRM0m >; // [mem8] = imm8 def MOV16mi : Im16i16<"mov", 0xC7, MRM0m >, OpSize; // [mem16] = imm16 def MOV32mi : Im32i32<"mov", 0xC7, MRM0m >; // [mem32] = imm32 @@ -309,36 +307,43 @@ // // Extra precision multiplication -def MUL8r : I <"mul", 0xF6, MRM4r>, Imp<[AL],[AX]>; // AL,AH = AL*R8 -def MUL16r : I <"mul", 0xF7, MRM4r>, Imp<[AX],[AX,DX]>, OpSize; // AX,DX = AX*R16 -def MUL32r : I <"mul", 0xF7, MRM4r>, Imp<[EAX],[EAX,EDX]>; // EAX,EDX = EAX*R32 +def MUL8r : I<0xF6, MRM4r>, Imp<[AL],[AX]>, // AL,AH = AL*R8 + II<(ops R8:$src), "mul $src">; +def MUL16r : I<0xF7, MRM4r>, Imp<[AX],[AX,DX]>, OpSize, // AX,DX = AX*R16 + II<(ops R16:$src), "mul $src">; +def MUL32r : I<0xF7, MRM4r>, Imp<[EAX],[EAX,EDX]>, // EAX,EDX = EAX*R32 + II<(ops R32:$src), "mul $src">; def MUL8m : Im8 <"mul", 0xF6, MRM4m>, Imp<[AL],[AX]>; // AL,AH = AL*[mem8] def MUL16m : Im16<"mul", 0xF7, MRM4m>, Imp<[AX],[AX,DX]>, OpSize; // AX,DX = AX*[mem16] def MUL32m : Im32<"mul", 0xF7, MRM4m>, Imp<[EAX],[EAX,EDX]>; // EAX,EDX = EAX*[mem32] // unsigned division/remainder -def DIV8r : I <"div", 0xF6, MRM6r>, Imp<[AX],[AX]>; // AX/r8 = AL,AH -def DIV16r : I <"div", 0xF7, MRM6r>, Imp<[AX,DX],[AX,DX]>, OpSize; // DX:AX/r16 = AX,DX -def DIV32r : I <"div", 0xF7, MRM6r>, Imp<[EAX,EDX],[EAX,EDX]>; // EDX:EAX/r32 = EAX,EDX +def DIV8r : I<0xF6, MRM6r>, Imp<[AX],[AX]>, // AX/r8 = AL,AH + II<(ops R8:$src), "div $src">; +def DIV16r : I<0xF7, MRM6r>, Imp<[AX,DX],[AX,DX]>, OpSize, // DX:AX/r16 = AX,DX + II<(ops R16:$src), "div $src">; +def DIV32r : I<0xF7, MRM6r>, Imp<[EAX,EDX],[EAX,EDX]>, // EDX:EAX/r32 = EAX,EDX + II<(ops R32:$src), "div $src">; def DIV8m : Im8 <"div", 0xF6, MRM6m>, Imp<[AX],[AX]>; // AX/[mem8] = AL,AH def DIV16m : Im16<"div", 0xF7, MRM6m>, Imp<[AX,DX],[AX,DX]>, OpSize; // DX:AX/[mem16] = AX,DX def DIV32m : Im32<"div", 0xF7, MRM6m>, Imp<[EAX,EDX],[EAX,EDX]>; // EDX:EAX/[mem32] = EAX,EDX -// signed division/remainder -def IDIV8r : I <"idiv",0xF6, MRM7r>, Imp<[AX],[AX]>; // AX/r8 = AL,AH -def IDIV16r: I <"idiv",0xF7, MRM7r>, Imp<[AX,DX],[AX,DX]>, OpSize; // DX:AX/r16 = AX,DX -def IDIV32r: I <"idiv",0xF7, MRM7r>, Imp<[EAX,EDX],[EAX,EDX]>; // EDX:EAX/r32 = EAX,EDX +// Signed division/remainder. +def IDIV8r : I<0xF6, MRM7r>, Imp<[AX],[AX]>, // AX/r8 = AL,AH + II<(ops R8:$src), "idiv $src">; +def IDIV16r: I<0xF7, MRM7r>, Imp<[AX,DX],[AX,DX]>, OpSize, // DX:AX/r16 = AX,DX + II<(ops R16:$src), "idiv $src">; +def IDIV32r: I<0xF7, MRM7r>, Imp<[EAX,EDX],[EAX,EDX]>, // EDX:EAX/r32 = EAX,EDX + II<(ops R32:$src), "idiv $src">; def IDIV8m : Im8 <"idiv",0xF6, MRM7m>, Imp<[AX],[AX]>; // AX/[mem8] = AL,AH def IDIV16m: Im16<"idiv",0xF7, MRM7m>, Imp<[AX,DX],[AX,DX]>, OpSize; // DX:AX/[mem16] = AX,DX def IDIV32m: Im32<"idiv",0xF7, MRM7m>, Imp<[EAX,EDX],[EAX,EDX]>; // EDX:EAX/[mem32] = EAX,EDX -// Sign-extenders for division -def CBW : I<"cbw", 0x98, RawFrm >, Imp<[AL],[AH]>, // AX = signext(AL) - II<(ops), "cbw">; -def CWD : I<"cwd", 0x99, RawFrm >, Imp<[AX],[DX]>, // DX:AX = signext(AX) - II<(ops), "cwd">; -def CDQ : I<"cdq", 0x99, RawFrm >, Imp<[EAX],[EDX]>, // EDX:EAX = signext(EAX) - II<(ops), "cdq">; +// Sign-extenders for division. +def CBW : I<0x98, RawFrm>, Imp<[AL],[AH]>, II<(ops), "cbw">; // AX = signext(AL) +def CWD : I<0x99, RawFrm>, Imp<[AX],[DX]>, II<(ops), "cwd">; // DX:AX = signext(AX) +def CDQ : I<0x99, RawFrm>, Imp<[EAX],[EDX]>, II<(ops), "cdq">; // EDX:EAX = signext(EAX) + //===----------------------------------------------------------------------===// // Two address Instructions... @@ -346,101 +351,137 @@ let isTwoAddress = 1 in { // Conditional moves -def CMOVB16rr : I <"cmovb", 0x42, MRMSrcReg>, TB, OpSize; // if , TB, OpSize, // if ; def CMOVB16rm : Im16<"cmovb", 0x42, MRMSrcMem>, TB, OpSize; // if , TB; // if , TB, // if ; def CMOVB32rm : Im32<"cmovb", 0x42, MRMSrcMem>, TB; // if , TB, OpSize; // if >=u, R16 = R16 +def CMOVAE16rr: I<0x43, MRMSrcReg>, TB, OpSize, // if >=u, R16 = R16 + II<(ops R16:$dst, R16:$src1, R16:$src2), "cmovae $dst, $src2">; def CMOVAE16rm: Im16<"cmovae", 0x43, MRMSrcMem>, TB, OpSize; // if >=u, R16 = [mem16] -def CMOVAE32rr: I <"cmovae", 0x43, MRMSrcReg>, TB; // if >=u, R32 = R32 +def CMOVAE32rr: I<0x43, MRMSrcReg>, TB, // if >=u, R32 = R32 + II<(ops R32:$dst, R32:$src1, R32:$src2), "cmovae $dst, $src2">; def CMOVAE32rm: Im32<"cmovae", 0x43, MRMSrcMem>, TB; // if >=u, R32 = [mem32] -def CMOVE16rr : I <"cmove", 0x44, MRMSrcReg>, TB, OpSize; // if ==, R16 = R16 +def CMOVE16rr : I<0x44, MRMSrcReg>, TB, OpSize, // if ==, R16 = R16 + II<(ops R16:$dst, R16:$src1, R16:$src2), "cmove $dst, $src2">; def CMOVE16rm : Im16<"cmove", 0x44, MRMSrcMem>, TB, OpSize; // if ==, R16 = [mem16] -def CMOVE32rr : I <"cmove", 0x44, MRMSrcReg>, TB; // if ==, R32 = R32 +def CMOVE32rr : I<0x44, MRMSrcReg>, TB, // if ==, R32 = R32 + II<(ops R32:$dst, R32:$src1, R32:$src2), "cmove $dst, $src2">; def CMOVE32rm : Im32<"cmove", 0x44, MRMSrcMem>, TB; // if ==, R32 = [mem32] -def CMOVNE16rr: I <"cmovne",0x45, MRMSrcReg>, TB, OpSize; // if !=, R16 = R16 +def CMOVNE16rr: I<0x45, MRMSrcReg>, TB, OpSize, // if !=, R16 = R16 + II<(ops R16:$dst, R16:$src1, R16:$src2), "cmovne $dst, $src2">; def CMOVNE16rm: Im16<"cmovne",0x45, MRMSrcMem>, TB, OpSize; // if !=, R16 = [mem16] -def CMOVNE32rr: I <"cmovne",0x45, MRMSrcReg>, TB; // if !=, R32 = R32 +def CMOVNE32rr: I<0x45, MRMSrcReg>, TB, // if !=, R32 = R32 + II<(ops R32:$dst, R32:$src1, R32:$src2), "cmovne $dst, $src2">; def CMOVNE32rm: Im32<"cmovne",0x45, MRMSrcMem>, TB; // if !=, R32 = [mem32] -def CMOVBE16rr: I <"cmovbe",0x46, MRMSrcReg>, TB, OpSize; // if <=u, R16 = R16 +def CMOVBE16rr: I<0x46, MRMSrcReg>, TB, OpSize, // if <=u, R16 = R16 + II<(ops R16:$dst, R16:$src1, R16:$src2), "cmovbe $dst, $src2">; def CMOVBE16rm: Im16<"cmovbe",0x46, MRMSrcMem>, TB, OpSize; // if <=u, R16 = [mem16] -def CMOVBE32rr: I <"cmovbe",0x46, MRMSrcReg>, TB; // if <=u, R32 = R32 +def CMOVBE32rr: I<0x46, MRMSrcReg>, TB, // if <=u, R32 = R32 + II<(ops R32:$dst, R32:$src1, R32:$src2), "cmovbe $dst, $src2">; def CMOVBE32rm: Im32<"cmovbe",0x46, MRMSrcMem>, TB; // if <=u, R32 = [mem32] -def CMOVA16rr : I <"cmova", 0x47, MRMSrcReg>, TB, OpSize; // if >u, R16 = R16 +def CMOVA16rr : I<0x47, MRMSrcReg>, TB, OpSize, // if >u, R16 = R16 + II<(ops R16:$dst, R16:$src1, R16:$src2), "cmova $dst, $src2">; def CMOVA16rm : Im16<"cmova", 0x47, MRMSrcMem>, TB, OpSize; // if >u, R16 = [mem16] -def CMOVA32rr : I <"cmova", 0x47, MRMSrcReg>, TB; // if >u, R32 = R32 +def CMOVA32rr : I<0x47, MRMSrcReg>, TB, // if >u, R32 = R32 + II<(ops R32:$dst, R32:$src1, R32:$src2), "cmova $dst, $src2">; def CMOVA32rm : Im32<"cmova", 0x47, MRMSrcMem>, TB; // if >u, R32 = [mem32] -def CMOVS16rr : I <"cmovs", 0x48, MRMSrcReg>, TB, OpSize; // if signed, R16 = R16 +def CMOVS16rr : I<0x48, MRMSrcReg>, TB, OpSize, // if signed, R16 = R16 + II<(ops R16:$dst, R16:$src1, R16:$src2), "cmovs $dst, $src2">; def CMOVS16rm : Im16<"cmovs", 0x48, MRMSrcMem>, TB, OpSize; // if signed, R16 = [mem16] -def CMOVS32rr : I <"cmovs", 0x48, MRMSrcReg>, TB; // if signed, R32 = R32 +def CMOVS32rr : I<0x48, MRMSrcReg>, TB, // if signed, R32 = R32 + II<(ops R32:$dst, R32:$src1, R32:$src2), "cmovs $dst, $src2">; def CMOVS32rm : Im32<"cmovs", 0x48, MRMSrcMem>, TB; // if signed, R32 = [mem32] -def CMOVNS16rr: I <"cmovns",0x49, MRMSrcReg>, TB, OpSize; // if !signed, R16 = R16 +def CMOVNS16rr: I<0x49, MRMSrcReg>, TB, OpSize, // if !signed, R16 = R16 + II<(ops R16:$dst, R16:$src1, R16:$src2), "cmovns $dst, $src2">; def CMOVNS16rm: Im16<"cmovns",0x49, MRMSrcMem>, TB, OpSize; // if !signed, R16 = [mem16] -def CMOVNS32rr: I <"cmovns",0x49, MRMSrcReg>, TB; // if !signed, R32 = R32 +def CMOVNS32rr: I<0x49, MRMSrcReg>, TB, // if !signed, R32 = R32 + II<(ops R32:$dst, R32:$src1, R32:$src2), "cmovns $dst, $src2">; def CMOVNS32rm: Im32<"cmovns",0x49, MRMSrcMem>, TB; // if !signed, R32 = [mem32] -def CMOVL16rr : I <"cmovl", 0x4C, MRMSrcReg>, TB, OpSize; // if , TB, OpSize, // if ; def CMOVL16rm : Im16<"cmovl", 0x4C, MRMSrcMem>, TB, OpSize; // if , TB; // if , TB, // if ; def CMOVL32rm : Im32<"cmovl", 0x4C, MRMSrcMem>, TB; // if , TB, OpSize; // if >=s, R16 = R16 +def CMOVGE16rr: I<0x4D, MRMSrcReg>, TB, OpSize, // if >=s, R16 = R16 + II<(ops R16:$dst, R16:$src1, R16:$src2), "cmovge $dst, $src2">; def CMOVGE16rm: Im16<"cmovge",0x4D, MRMSrcMem>, TB, OpSize; // if >=s, R16 = [mem16] -def CMOVGE32rr: I <"cmovge",0x4D, MRMSrcReg>, TB; // if >=s, R32 = R32 +def CMOVGE32rr: I<0x4D, MRMSrcReg>, TB, // if >=s, R32 = R32 + II<(ops R32:$dst, R32:$src1, R32:$src2), "cmovge $dst, $src2">; def CMOVGE32rm: Im32<"cmovge",0x4D, MRMSrcMem>, TB; // if >=s, R32 = [mem32] -def CMOVLE16rr: I <"cmovle",0x4E, MRMSrcReg>, TB, OpSize; // if <=s, R16 = R16 +def CMOVLE16rr: I<0x4E, MRMSrcReg>, TB, OpSize, // if <=s, R16 = R16 + II<(ops R16:$dst, R16:$src1, R16:$src2), "cmovle $dst, $src2">; def CMOVLE16rm: Im16<"cmovle",0x4E, MRMSrcMem>, TB, OpSize; // if <=s, R16 = [mem16] -def CMOVLE32rr: I <"cmovle",0x4E, MRMSrcReg>, TB; // if <=s, R32 = R32 +def CMOVLE32rr: I<0x4E, MRMSrcReg>, TB, // if <=s, R32 = R32 + II<(ops R32:$dst, R32:$src1, R32:$src2), "cmovle $dst, $src2">; def CMOVLE32rm: Im32<"cmovle",0x4E, MRMSrcMem>, TB; // if <=s, R32 = [mem32] -def CMOVG16rr : I <"cmovg", 0x4F, MRMSrcReg>, TB, OpSize; // if >s, R16 = R16 +def CMOVG16rr : I<0x4F, MRMSrcReg>, TB, OpSize, // if >s, R16 = R16 + II<(ops R16:$dst, R16:$src1, R16:$src2), "cmovg $dst, $src2">; def CMOVG16rm : Im16<"cmovg", 0x4F, MRMSrcMem>, TB, OpSize; // if >s, R16 = [mem16] -def CMOVG32rr : I <"cmovg", 0x4F, MRMSrcReg>, TB; // if >s, R32 = R32 +def CMOVG32rr : I<0x4F, MRMSrcReg>, TB, // if >s, R32 = R32 + II<(ops R32:$dst, R32:$src1, R32:$src2), "cmovg $dst, $src2">; def CMOVG32rm : Im32<"cmovg", 0x4F, MRMSrcMem>, TB; // if >s, R32 = [mem32] // unary instructions -def NEG8r : I <"neg", 0xF6, MRM3r>; // R8 = -R8 = 0-R8 -def NEG16r : I <"neg", 0xF7, MRM3r>, OpSize; // R16 = -R16 = 0-R16 -def NEG32r : I <"neg", 0xF7, MRM3r>; // R32 = -R32 = 0-R32 +def NEG8r : I<0xF6, MRM3r>, // R8 = -R8 = 0-R8 + II<(ops R8:$dst, R8:$src), "neg $dst">; +def NEG16r : I<0xF7, MRM3r>, OpSize, // R16 = -R16 = 0-R16 + II<(ops R16:$dst, R16:$src), "neg $dst">; +def NEG32r : I<0xF7, MRM3r>, // R32 = -R32 = 0-R32 + II<(ops R32:$dst, R32:$src), "neg $dst">; def NEG8m : Im8 <"neg", 0xF6, MRM3m>; // [mem8] = -[mem8] = 0-[mem8] def NEG16m : Im16<"neg", 0xF7, MRM3m>, OpSize; // [mem16] = -[mem16] = 0-[mem16] def NEG32m : Im32<"neg", 0xF7, MRM3m>; // [mem32] = -[mem32] = 0-[mem32] -def NOT8r : I <"not", 0xF6, MRM2r>; // R8 = ~R8 = R8^-1 -def NOT16r : I <"not", 0xF7, MRM2r>, OpSize; // R16 = ~R16 = R16^-1 -def NOT32r : I <"not", 0xF7, MRM2r>; // R32 = ~R32 = R32^-1 +def NOT8r : I<0xF6, MRM2r>, // R8 = ~R8 = R8^-1 + II<(ops R8:$dst, R8:$src), "not $dst">; +def NOT16r : I<0xF7, MRM2r>, OpSize, // R16 = ~R16 = R16^-1 + II<(ops R16:$dst, R16:$src), "not $dst">; +def NOT32r : I<0xF7, MRM2r>, // R32 = ~R32 = R32^-1 + II<(ops R32:$dst, R32:$src), "not $dst">; def NOT8m : Im8 <"not", 0xF6, MRM2m>; // [mem8] = ~[mem8] = [mem8^-1] def NOT16m : Im16<"not", 0xF7, MRM2m>, OpSize; // [mem16] = ~[mem16] = [mem16^-1] def NOT32m : Im32<"not", 0xF7, MRM2m>; // [mem32] = ~[mem32] = [mem32^-1] -def INC8r : I <"inc", 0xFE, MRM0r>; // ++R8 -def INC16r : I <"inc", 0xFF, MRM0r>, OpSize; // ++R16 -def INC32r : I <"inc", 0xFF, MRM0r>; // ++R32 +def INC8r : I<0xFE, MRM0r>, // ++R8 + II<(ops R8:$dst, R8:$src), "inc $dst">; +def INC16r : I<0xFF, MRM0r>, OpSize, // ++R16 + II<(ops R16:$dst, R16:$src), "inc $dst">; +def INC32r : I<0xFF, MRM0r>, // ++R32 + II<(ops R32:$dst, R32:$src), "inc $dst">; def INC8m : Im8 <"inc", 0xFE, MRM0m>; // ++R8 def INC16m : Im16<"inc", 0xFF, MRM0m>, OpSize; // ++R16 def INC32m : Im32<"inc", 0xFF, MRM0m>; // ++R32 -def DEC8r : I <"dec", 0xFE, MRM1r>; // --R8 -def DEC16r : I <"dec", 0xFF, MRM1r>, OpSize; // --R16 -def DEC32r : I <"dec", 0xFF, MRM1r>; // --R32 +def DEC8r : I<0xFE, MRM1r>, // --R8 + II<(ops R8:$dst, R8:$src), "dec $dst">; +def DEC16r : I<0xFF, MRM1r>, OpSize, // --R16 + II<(ops R16:$dst, R16:$src), "dec $dst">; +def DEC32r : I<0xFF, MRM1r>, // --R32 + II<(ops R32:$dst, R32:$src), "dec $dst">; def DEC8m : Im8 <"dec", 0xFE, MRM1m>; // --[mem8] def DEC16m : Im16<"dec", 0xFF, MRM1m>, OpSize; // --[mem16] def DEC32m : Im32<"dec", 0xFF, MRM1m>; // --[mem32] // Logical operators... -def AND8rr : I <"and", 0x20, MRMDestReg>, +def AND8rr : I<0x20, MRMDestReg>, II<(ops R8:$dst, R8:$src1, R8:$src2), "and $dst, $src2">; -def AND16rr : I <"and", 0x21, MRMDestReg>, OpSize, - II<(ops R32:$dst, R32:$src1, R32:$src2), "and $dst, $src2">; -def AND32rr : I <"and", 0x21, MRMDestReg>, +def AND16rr : I<0x21, MRMDestReg>, OpSize, + II<(ops R16:$dst, R16:$src1, R16:$src2), "and $dst, $src2">; +def AND32rr : I<0x21, MRMDestReg>, II<(ops R32:$dst, R32:$src1, R32:$src2), "and $dst, $src2">; def AND8mr : Im8 <"and", 0x20, MRMDestMem>; // [mem8] &= R8 def AND16mr : Im16 <"and", 0x21, MRMDestMem>, OpSize; // [mem16] &= R16 @@ -462,9 +503,12 @@ def AND32mi8 : Im32i8<"and", 0x83, MRM4m >; // [mem32] &= imm8 -def OR8rr : I <"or" , 0x08, MRMDestReg>; -def OR16rr : I <"or" , 0x09, MRMDestReg>, OpSize; -def OR32rr : I <"or" , 0x09, MRMDestReg>; +def OR8rr : I<0x08, MRMDestReg>, + II<(ops R8:$dst, R8:$src1, R8:$src2), "or $dst, $src2">; +def OR16rr : I<0x09, MRMDestReg>, OpSize, + II<(ops R16:$dst, R16:$src1, R16:$src2), "or $dst, $src2">; +def OR32rr : I<0x09, MRMDestReg>, + II<(ops R32:$dst, R32:$src1, R32:$src2), "or $dst, $src2">; def OR8mr : Im8 <"or" , 0x08, MRMDestMem>; // [mem8] |= R8 def OR16mr : Im16 <"or" , 0x09, MRMDestMem>, OpSize; // [mem16] |= R16 def OR32mr : Im32 <"or" , 0x09, MRMDestMem>; // [mem32] |= R32 @@ -485,9 +529,12 @@ def OR32mi8 : Im32i8<"or" , 0x83, MRM1m >; // [mem32] |= imm8 -def XOR8rr : I <"xor", 0x30, MRMDestReg>; -def XOR16rr : I <"xor", 0x31, MRMDestReg>, OpSize; -def XOR32rr : I <"xor", 0x31, MRMDestReg>; +def XOR8rr : I<0x30, MRMDestReg>, + II<(ops R8:$dst, R8:$src1, R8:$src2), "xor $dst, $src2">; +def XOR16rr : I<0x31, MRMDestReg>, OpSize, + II<(ops R16:$dst, R16:$src1, R16:$src2), "xor $dst, $src2">; +def XOR32rr : I<0x31, MRMDestReg>, + II<(ops R32:$dst, R32:$src1, R32:$src2), "xor $dst, $src2">; def XOR8mr : Im8 <"xor", 0x30, MRMDestMem>; // [mem8] ^= R8 def XOR16mr : Im16 <"xor", 0x31, MRMDestMem>, OpSize; // [mem16] ^= R16 def XOR32mr : Im32 <"xor", 0x31, MRMDestMem>; // [mem32] ^= R32 @@ -510,11 +557,11 @@ // Shift instructions // FIXME: provide shorter instructions when imm8 == 1 let Uses = [CL], printImplicitUsesAfter = 1 in { - def SHL8rCL : I <"shl", 0xD2, MRM4r > , // R8 <<= cl + def SHL8rCL : I<0xD2, MRM4r> , // R8 <<= cl II<(ops R8:$dst, R8:$src), "shl $dst, %CL">; - def SHL16rCL : I <"shl", 0xD3, MRM4r >, OpSize, // R16 <<= cl + def SHL16rCL : I<0xD3, MRM4r>, OpSize, // R16 <<= cl II<(ops R16:$dst, R16:$src), "shl $dst, %CL">; - def SHL32rCL : I <"shl", 0xD3, MRM4r > , // R32 <<= cl + def SHL32rCL : I<0xD3, MRM4r> , // R32 <<= cl II<(ops R32:$dst, R32:$src), "shl $dst, %CL">; def SHL8mCL : Im8 <"shl", 0xD2, MRM4m > ; // [mem8] <<= cl def SHL16mCL : Im16 <"shl", 0xD3, MRM4m >, OpSize; // [mem16] <<= cl @@ -529,11 +576,11 @@ def SHL32mi : Im32i8<"shl", 0xC1, MRM4m >; // [mem32] <<= imm8 let Uses = [CL], printImplicitUsesAfter = 1 in { - def SHR8rCL : I <"shr", 0xD2, MRM5r > , // R8 >>= cl + def SHR8rCL : I<0xD2, MRM5r> , // R8 >>= cl II<(ops R8:$dst, R8:$src), "shr $dst, %CL">; - def SHR16rCL : I <"shr", 0xD3, MRM5r >, OpSize, // R16 >>= cl + def SHR16rCL : I<0xD3, MRM5r>, OpSize, // R16 >>= cl II<(ops R16:$dst, R16:$src), "shr $dst, %CL">; - def SHR32rCL : I <"shr", 0xD3, MRM5r > , // R32 >>= cl + def SHR32rCL : I<0xD3, MRM5r> , // R32 >>= cl II<(ops R32:$dst, R32:$src), "shr $dst, %CL">; def SHR8mCL : Im8 <"shr", 0xD2, MRM5m > ; // [mem8] >>= cl def SHR16mCL : Im16 <"shr", 0xD3, MRM5m >, OpSize; // [mem16] >>= cl @@ -548,11 +595,11 @@ def SHR32mi : Im32i8<"shr", 0xC1, MRM5m >; // [mem32] >>= imm8 let Uses = [CL], printImplicitUsesAfter = 1 in { - def SAR8rCL : I <"sar", 0xD2, MRM7r >, // R8 >>>= cl + def SAR8rCL : I<0xD2, MRM7r>, // R8 >>>= cl II<(ops R8:$dst, R8:$src), "sar $dst, %CL">; - def SAR16rCL : I <"sar", 0xD3, MRM7r >, OpSize, // R16 >>>= cl + def SAR16rCL : I<0xD3, MRM7r>, OpSize, // R16 >>>= cl II<(ops R16:$dst, R16:$src), "sar $dst, %CL">; - def SAR32rCL : I <"sar", 0xD3, MRM7r >, // R32 >>>= cl + def SAR32rCL : I<0xD3, MRM7r>, // R32 >>>= cl II<(ops R32:$dst, R32:$src), "sar $dst, %CL">; def SAR8mCL : Im8 <"sar", 0xD2, MRM7m > ; // [mem8] >>>= cl def SAR16mCL : Im16 <"sar", 0xD3, MRM7m >, OpSize; // [mem16] >>>= cl @@ -567,11 +614,11 @@ def SAR32mi : Im32i8<"sar", 0xC1, MRM7m >; // [mem32] >>>= imm8 let Uses = [CL], printImplicitUsesAfter = 1 in { - def SHLD32rrCL : I <"shld", 0xA5, MRMDestReg>, TB, // R32 <<= R32,R32 cl - II<(ops R32:$dst, R32:$src1, R32:$src2), "shld $dst, $src2, %CL">; + def SHLD32rrCL : I<0xA5, MRMDestReg>, TB, // R32 <<= R32,R32 cl + II<(ops R32:$dst, R32:$src1, R32:$src2), "shld $dst, $src2, %CL">; def SHLD32mrCL : Im32 <"shld", 0xA5, MRMDestMem>, TB; // [mem32] <<= [mem32],R32 cl - def SHRD32rrCL : I <"shrd", 0xAD, MRMDestReg>, TB, // R32 >>= R32,R32 cl - II<(ops R32:$dst, R32:$src1, R32:$src2), "shrd $dst, $src2, %CL">; + def SHRD32rrCL : I<0xAD, MRMDestReg>, TB, // R32 >>= R32,R32 cl + II<(ops R32:$dst, R32:$src1, R32:$src2), "shrd $dst, $src2, %CL">; def SHRD32mrCL : Im32 <"shrd", 0xAD, MRMDestMem>, TB; // [mem32] >>= [mem32],R32 cl } @@ -582,9 +629,9 @@ // Arithmetic... -def ADD8rr : I <"add", 0x00, MRMDestReg>; -def ADD16rr : I <"add", 0x01, MRMDestReg>, OpSize; -def ADD32rr : I <"add", 0x01, MRMDestReg>; +def ADD8rr : I<0x00, MRMDestReg>, II<(ops R8:$dst, R8:$src1, R8:$src2), "add $dst, $src2">; +def ADD16rr : I<0x01, MRMDestReg>, OpSize, II<(ops R16:$dst, R16:$src1, R16:$src2), "add $dst, $src2">; +def ADD32rr : I<0x01, MRMDestReg>, II<(ops R32:$dst, R32:$src1, R32:$src2), "add $dst, $src2">; def ADD8mr : Im8 <"add", 0x00, MRMDestMem>; // [mem8] += R8 def ADD16mr : Im16 <"add", 0x01, MRMDestMem>, OpSize; // [mem16] += R16 def ADD32mr : Im32 <"add", 0x01, MRMDestMem>; // [mem32] += R32 @@ -604,7 +651,8 @@ def ADD16mi8 : Im16i8<"add", 0x83, MRM0m >, OpSize; // [mem16] += I8 def ADD32mi8 : Im32i8<"add", 0x83, MRM0m >; // [mem32] += I8 -def ADC32rr : I <"adc", 0x11, MRMDestReg>; // R32 += R32+Carry +def ADC32rr : I<0x11, MRMDestReg>, // R32 += R32+Carry + II<(ops R32:$dst, R32:$src1, R32:$src2), "adc $dst, $src2">; def ADC32mr : Im32 <"adc", 0x11, MRMDestMem>; // [mem32] += R32+Carry def ADC32rm : Im32 <"adc", 0x13, MRMSrcMem >; // R32 += [mem32]+Carry def ADC32ri : Ii32 <"adc", 0x81, MRM2r >; // R32 += I32+Carry @@ -612,9 +660,9 @@ def ADC32mi : Im32i32<"adc", 0x81, MRM2m >; // [mem32] += I32+Carry def ADC32mi8 : Im32i8 <"adc", 0x83, MRM2m >; // [mem32] += I8+Carry -def SUB8rr : I <"sub", 0x28, MRMDestReg>; -def SUB16rr : I <"sub", 0x29, MRMDestReg>, OpSize; -def SUB32rr : I <"sub", 0x29, MRMDestReg>; +def SUB8rr : I<0x28, MRMDestReg>, II<(ops R8:$dst, R8:$src1, R8:$src2), "sub $dst, $src2">; +def SUB16rr : I<0x29, MRMDestReg>, OpSize, II<(ops R16:$dst, R16:$src1, R16:$src2), "sub $dst, $src2">; +def SUB32rr : I<0x29, MRMDestReg>, II<(ops R32:$dst, R32:$src1, R32:$src2), "sub $dst, $src2">; def SUB8mr : Im8 <"sub", 0x28, MRMDestMem>; // [mem8] -= R8 def SUB16mr : Im16 <"sub", 0x29, MRMDestMem>, OpSize; // [mem16] -= R16 def SUB32mr : Im32 <"sub", 0x29, MRMDestMem>; // [mem32] -= R32 @@ -634,7 +682,8 @@ def SUB16mi8 : Im16i8<"sub", 0x83, MRM5m >, OpSize; // [mem16] -= I8 def SUB32mi8 : Im32i8<"sub", 0x83, MRM5m >; // [mem32] -= I8 -def SBB32rr : I <"sbb", 0x19, MRMDestReg>; // R32 -= R32+Carry +def SBB32rr : I<0x19, MRMDestReg>, // R32 -= R32+Carry + II<(ops R32:$dst, R32:$src1, R32:$src2), "adc $dst, $src2">; def SBB32mr : Im32 <"sbb", 0x19, MRMDestMem>; // [mem32] -= R32+Carry def SBB32rm : Im32 <"sbb", 0x1B, MRMSrcMem >; // R32 -= [mem32]+Carry def SBB32ri : Ii32 <"sbb", 0x81, MRM3r >; // R32 -= I32+Carry @@ -642,8 +691,10 @@ def SBB32mi : Im32i32<"sbb", 0x81, MRM3m >; // [mem32] -= I32+Carry def SBB32mi8 : Im32i8 <"sbb", 0x83, MRM3m >; // [mem32] -= I8+Carry -def IMUL16rr : I <"imul", 0xAF, MRMSrcReg>, TB, OpSize; -def IMUL32rr : I <"imul", 0xAF, MRMSrcReg>, TB; +def IMUL16rr : I<0xAF, MRMSrcReg>, TB, OpSize, + II<(ops R16:$dst, R16:$src1, R16:$src2), "imul $dst, $src2">; +def IMUL32rr : I<0xAF, MRMSrcReg>, TB, + II<(ops R32:$dst, R32:$src1, R32:$src2), "imul $dst, $src2">; def IMUL16rm : Im16 <"imul", 0xAF, MRMSrcMem>, TB, OpSize; def IMUL32rm : Im32 <"imul", 0xAF, MRMSrcMem>, TB ; @@ -661,9 +712,12 @@ //===----------------------------------------------------------------------===// // Test instructions are just like AND, except they don't generate a result. -def TEST8rr : I <"test", 0x84, MRMDestReg>; // flags = R8 & R8 -def TEST16rr : I <"test", 0x85, MRMDestReg>, OpSize; // flags = R16 & R16 -def TEST32rr : I <"test", 0x85, MRMDestReg>; // flags = R32 & R32 +def TEST8rr : I<0x84, MRMDestReg>, // flags = R8 & R8 + II<(ops R8:$src1, R8:$src2), "test $src1, $src2">; +def TEST16rr : I<0x85, MRMDestReg>, OpSize, // flags = R16 & R16 + II<(ops R16:$src1, R16:$src2), "test $src1, $src2">; +def TEST32rr : I<0x85, MRMDestReg>, // flags = R32 & R32 + II<(ops R32:$src1, R32:$src2), "test $src1, $src2">; def TEST8mr : Im8 <"test", 0x84, MRMDestMem>; // flags = [mem8] & R8 def TEST16mr : Im16 <"test", 0x85, MRMDestMem>, OpSize; // flags = [mem16] & R16 def TEST32mr : Im32 <"test", 0x85, MRMDestMem>; // flags = [mem32] & R32 @@ -681,42 +735,58 @@ // Condition code ops, incl. set if equal/not equal/... -def SAHF : I <"sahf" , 0x9E, RawFrm>, Imp<[AH],[]>, // flags = AH - II<(ops), "sahf">; -def LAHF : I <"lahf" , 0x9F, RawFrm>, Imp<[],[AH]>, // AH = flags - II<(ops), "lahf">; +def SAHF : I<0x9E, RawFrm>, Imp<[AH],[]>, // flags = AH + II<(ops), "sahf">; +def LAHF : I<0x9F, RawFrm>, Imp<[],[AH]>, // AH = flags + II<(ops), "lahf">; -def SETBr : I <"setb" , 0x92, MRM0r>, TB; // R8 = < unsign +def SETBr : I<0x92, MRM0r>, TB, // R8 = < unsign + II<(ops R8:$dst), "setb $dst">; def SETBm : Im8<"setb" , 0x92, MRM0m>, TB; // [mem8] = < unsign -def SETAEr : I <"setae", 0x93, MRM0r>, TB; // R8 = >= unsign +def SETAEr : I<0x93, MRM0r>, TB, // R8 = >= unsign + II<(ops R8:$dst), "setae $dst">; def SETAEm : Im8<"setae", 0x93, MRM0m>, TB; // [mem8] = >= unsign -def SETEr : I <"sete" , 0x94, MRM0r>, TB; // R8 = == +def SETEr : I<0x94, MRM0r>, TB, // R8 = == + II<(ops R8:$dst), "sete $dst">; def SETEm : Im8<"sete" , 0x94, MRM0m>, TB; // [mem8] = == -def SETNEr : I <"setne", 0x95, MRM0r>, TB; // R8 = != +def SETNEr : I<0x95, MRM0r>, TB, // R8 = != + II<(ops R8:$dst), "setne $dst">; def SETNEm : Im8<"setne", 0x95, MRM0m>, TB; // [mem8] = != -def SETBEr : I <"setbe", 0x96, MRM0r>, TB; // R8 = <= unsign +def SETBEr : I<0x96, MRM0r>, TB, // R8 = <= unsign + II<(ops R8:$dst), "setbe $dst">; def SETBEm : Im8<"setbe", 0x96, MRM0m>, TB; // [mem8] = <= unsign -def SETAr : I <"seta" , 0x97, MRM0r>, TB; // R8 = > signed +def SETAr : I<0x97, MRM0r>, TB, // R8 = > signed + II<(ops R8:$dst), "seta $dst">; def SETAm : Im8<"seta" , 0x97, MRM0m>, TB; // [mem8] = > signed -def SETSr : I <"sets" , 0x98, MRM0r>, TB; // R8 = +def SETSr : I<0x98, MRM0r>, TB, // R8 = + II<(ops R8:$dst), "sets $dst">; def SETSm : Im8<"sets" , 0x98, MRM0m>, TB; // [mem8] = -def SETNSr : I <"setns", 0x99, MRM0r>, TB; // R8 = ! +def SETNSr : I<0x99, MRM0r>, TB, // R8 = ! + II<(ops R8:$dst), "setns $dst">; def SETNSm : Im8<"setns", 0x99, MRM0m>, TB; // [mem8] = ! -def SETPr : I <"setp" , 0x9A, MRM0r>, TB; // R8 = parity +def SETPr : I<0x9A, MRM0r>, TB, // R8 = parity + II<(ops R8:$dst), "setp $dst">; def SETPm : Im8<"setp" , 0x9A, MRM0m>, TB; // [mem8] = parity -def SETLr : I <"setl" , 0x9C, MRM0r>, TB; // R8 = < signed +def SETLr : I<0x9C, MRM0r>, TB, // R8 = < signed + II<(ops R8:$dst), "setl $dst">; def SETLm : Im8<"setl" , 0x9C, MRM0m>, TB; // [mem8] = < signed -def SETGEr : I <"setge", 0x9D, MRM0r>, TB; // R8 = >= signed +def SETGEr : I<0x9D, MRM0r>, TB, // R8 = >= signed + II<(ops R8:$dst), "setge $dst">; def SETGEm : Im8<"setge", 0x9D, MRM0m>, TB; // [mem8] = >= signed -def SETLEr : I <"setle", 0x9E, MRM0r>, TB; // R8 = <= signed +def SETLEr : I<0x9E, MRM0r>, TB, // R8 = <= signed + II<(ops R8:$dst), "setle $dst">; def SETLEm : Im8<"setle", 0x9E, MRM0m>, TB; // [mem8] = <= signed -def SETGr : I <"setg" , 0x9F, MRM0r>, TB; // R8 = < signed +def SETGr : I<0x9F, MRM0r>, TB, // R8 = < signed + II<(ops R8:$dst), "setg $dst">; def SETGm : Im8<"setg" , 0x9F, MRM0m>, TB; // [mem8] = < signed // Integer comparisons -def CMP8rr : I <"cmp", 0x38, MRMDestReg>; // compare R8, R8 -def CMP16rr : I <"cmp", 0x39, MRMDestReg>, OpSize; // compare R16, R16 -def CMP32rr : I <"cmp", 0x39, MRMDestReg>; // compare R32, R32 +def CMP8rr : I<0x38, MRMDestReg>, // compare R8, R8 + II<(ops R8:$src1, R8:$src2), "cmp $src1, $src2">; +def CMP16rr : I<0x39, MRMDestReg>, OpSize, // compare R16, R16 + II<(ops R16:$src1, R16:$src2), "cmp $src1, $src2">; +def CMP32rr : I<0x39, MRMDestReg>, // compare R32, R32 + II<(ops R32:$src1, R32:$src2), "cmp $src1, $src2">; def CMP8mr : Im8 <"cmp", 0x38, MRMDestMem>; // compare [mem8], R8 def CMP16mr : Im16 <"cmp", 0x39, MRMDestMem>, OpSize; // compare [mem16], R16 def CMP32mr : Im32 <"cmp", 0x39, MRMDestMem>; // compare [mem32], R32 @@ -731,16 +801,22 @@ def CMP32mi : Im32i32<"cmp", 0x81, MRM7m >; // compare [mem32], imm32 // Sign/Zero extenders -def MOVSX16rr8 : I <"movsx", 0xBE, MRMSrcReg>, TB, OpSize; // R16 = signext(R8) -def MOVSX32rr8 : I <"movsx", 0xBE, MRMSrcReg>, TB; // R32 = signext(R8) -def MOVSX32rr16: I <"movsx", 0xBF, MRMSrcReg>, TB; // R32 = signext(R16) +def MOVSX16rr8 : I<0xBE, MRMSrcReg>, TB, OpSize, // R16 = signext(R8) + II<(ops R16:$dst, R8:$src), "movsx $dst, $src">; +def MOVSX32rr8 : I<0xBE, MRMSrcReg>, TB, // R32 = signext(R8) + II<(ops R32:$dst, R8:$src), "movsx $dst, $src">; +def MOVSX32rr16: I<0xBF, MRMSrcReg>, TB, // R32 = signext(R16) + II<(ops R32:$dst, R16:$src), "movsx $dst, $src">; def MOVSX16rm8 : Im8 <"movsx", 0xBE, MRMSrcMem>, TB, OpSize; // R16 = signext([mem8]) def MOVSX32rm8 : Im8 <"movsx", 0xBE, MRMSrcMem>, TB; // R32 = signext([mem8]) def MOVSX32rm16: Im16<"movsx", 0xBF, MRMSrcMem>, TB; // R32 = signext([mem16]) -def MOVZX16rr8 : I <"movzx", 0xB6, MRMSrcReg>, TB, OpSize; // R16 = zeroext(R8) -def MOVZX32rr8 : I <"movzx", 0xB6, MRMSrcReg>, TB; // R32 = zeroext(R8) -def MOVZX32rr16: I <"movzx", 0xB7, MRMSrcReg>, TB; // R32 = zeroext(R16) +def MOVZX16rr8 : I<0xB6, MRMSrcReg>, TB, OpSize, // R16 = zeroext(R8) + II<(ops R16:$dst, R8:$src), "movzx $dst, $src">; +def MOVZX32rr8 : I<0xB6, MRMSrcReg>, TB, // R32 = zeroext(R8) + II<(ops R32:$dst, R8:$src), "movzx $dst, $src">; +def MOVZX32rr16: I<0xB7, MRMSrcReg>, TB, // R32 = zeroext(R16) + II<(ops R32:$dst, R16:$src), "movzx $dst, $src">; def MOVZX16rm8 : Im8 <"movzx", 0xB6, MRMSrcMem>, TB, OpSize; // R16 = zeroext([mem8]) def MOVZX32rm8 : Im8 <"movzx", 0xB6, MRMSrcMem>, TB; // R32 = zeroext([mem8]) def MOVZX32rm16: Im16<"movzx", 0xB7, MRMSrcMem>, TB; // R32 = zeroext([mem16]) @@ -769,14 +845,14 @@ // because they can be expanded by the fp spackifier into one of many different // forms of instructions for doing these operations. Until the stackifier runs, // we prefer to be abstract. -def FpMOV : FPI<"FMOV", 0, Pseudo, SpecialFP>; // f1 = fmov f2 -def FpADD : FPI<"FADD", 0, Pseudo, TwoArgFP>; // f1 = fadd f2, f3 -def FpSUB : FPI<"FSUB", 0, Pseudo, TwoArgFP>; // f1 = fsub f2, f3 -def FpMUL : FPI<"FMUL", 0, Pseudo, TwoArgFP>; // f1 = fmul f2, f3 -def FpDIV : FPI<"FDIV", 0, Pseudo, TwoArgFP>; // f1 = fdiv f2, f3 +def FpMOV : FPI<"", 0, Pseudo, SpecialFP>; // f1 = fmov f2 +def FpADD : FPI<"", 0, Pseudo, TwoArgFP>; // f1 = fadd f2, f3 +def FpSUB : FPI<"", 0, Pseudo, TwoArgFP>; // f1 = fsub f2, f3 +def FpMUL : FPI<"", 0, Pseudo, TwoArgFP>; // f1 = fmul f2, f3 +def FpDIV : FPI<"", 0, Pseudo, TwoArgFP>; // f1 = fdiv f2, f3 -def FpGETRESULT : FPI<"FGETRESULT",0, Pseudo, SpecialFP>; // FPR = ST(0) -def FpSETRESULT : FPI<"FSETRESULT",0, Pseudo, SpecialFP>; // ST(0) = FPR +def FpGETRESULT : FPI<"",0, Pseudo, SpecialFP>; // FPR = ST(0) +def FpSETRESULT : FPI<"",0, Pseudo, SpecialFP>; // ST(0) = FPR // FADD reg, mem: Before stackification, these are represented by: R1 = FADD* R2, [mem] def FADD32m : FPI32m<"fadd", 0xD8, MRM0m, OneArgFPRW>; // ST(0) = ST(0) + [mem32real] @@ -819,17 +895,17 @@ // Floating point cmovs... let isTwoAddress = 1, Uses = [ST0], Defs = [ST0] in { - def FCMOVB : FPI<"fcmovb" , 0xC0, AddRegFrm, CondMovFP>, DA, // fcmovb ST(i) -> ST(0) + def FCMOVB : FPI<"" , 0xC0, AddRegFrm, CondMovFP>, DA, // fcmovb ST(i) -> ST(0) II<(ops RST:$op), "fcmovb %ST(0), $op">; - def FCMOVBE : FPI<"fcmovbe", 0xD0, AddRegFrm, CondMovFP>, DA, // fcmovbe ST(i) -> ST(0) + def FCMOVBE : FPI<"", 0xD0, AddRegFrm, CondMovFP>, DA, // fcmovbe ST(i) -> ST(0) II<(ops RST:$op), "fcmovbe %ST(0), $op">; - def FCMOVE : FPI<"fcmove" , 0xC8, AddRegFrm, CondMovFP>, DA, // fcmove ST(i) -> ST(0) + def FCMOVE : FPI<"" , 0xC8, AddRegFrm, CondMovFP>, DA, // fcmove ST(i) -> ST(0) II<(ops RST:$op), "fcmove %ST(0), $op">; - def FCMOVAE : FPI<"fcmovae", 0xC0, AddRegFrm, CondMovFP>, DB, // fcmovae ST(i) -> ST(0) + def FCMOVAE : FPI<"", 0xC0, AddRegFrm, CondMovFP>, DB, // fcmovae ST(i) -> ST(0) II<(ops RST:$op), "fcmovae %ST(0), $op">; - def FCMOVA : FPI<"fcmova" , 0xD0, AddRegFrm, CondMovFP>, DB, // fcmova ST(i) -> ST(0) + def FCMOVA : FPI<"" , 0xD0, AddRegFrm, CondMovFP>, DB, // fcmova ST(i) -> ST(0) II<(ops RST:$op), "fcmova %ST(0), $op">; - def FCMOVNE : FPI<"fcmovne", 0xC8, AddRegFrm, CondMovFP>, DB, // fcmovne ST(i) -> ST(0) + def FCMOVNE : FPI<"", 0xC8, AddRegFrm, CondMovFP>, DB, // fcmovne ST(i) -> ST(0) II<(ops RST:$op), "fcmovne %ST(0), $op">; } @@ -859,70 +935,72 @@ def FXCH : FPI <"fxch", 0xC8, AddRegFrm, NotFP>, D9; // fxch ST(i), ST(0) // Floating point constant loads... -def FLD0 : FPI<"fldz", 0xEE, RawFrm, ZeroArgFP>, D9, +def FLD0 : FPI<"", 0xEE, RawFrm, ZeroArgFP>, D9, II<(ops), "fldz">; -def FLD1 : FPI<"fld1", 0xE8, RawFrm, ZeroArgFP>, D9, +def FLD1 : FPI<"", 0xE8, RawFrm, ZeroArgFP>, D9, II<(ops), "fld1">; // Unary operations... -def FCHS : FPI<"fchs", 0xE0, RawFrm, OneArgFPRW>, D9, // f1 = fchs f2 +def FCHS : FPI<"", 0xE0, RawFrm, OneArgFPRW>, D9, // f1 = fchs f2 II<(ops), "fchs">; -def FTST : FPI<"ftst", 0xE4, RawFrm, OneArgFP>, D9, // ftst ST(0) +def FTST : FPI<"", 0xE4, RawFrm, OneArgFP>, D9, // ftst ST(0) II<(ops), "ftst">; // Binary arithmetic operations... -class FPST0rInst o> : I, D8 { +class FPST0rInst o> : I, D8 { list Uses = [ST0]; list Defs = [ST0]; } -class FPrST0Inst o> : I, DC { +class FPrST0Inst o> : I, DC { list Uses = [ST0]; } -class FPrST0PInst o> : I, DE { +class FPrST0PInst o> : I, DE { list Uses = [ST0]; } -def FADDST0r : FPST0rInst <"fadd", 0xC0>; -def FADDrST0 : FPrST0Inst <"fadd", 0xC0>, II<(ops RST:$op), "fadd $op, %ST(0)">; -def FADDPrST0 : FPrST0PInst<"faddp", 0xC0>; - -def FSUBRST0r : FPST0rInst <"fsubr", 0xE8>; -def FSUBrST0 : FPrST0Inst <"fsub", 0xE8>, II<(ops RST:$op), "fsub $op, %ST(0)">; -def FSUBPrST0 : FPrST0PInst<"fsubp", 0xE8>; - -def FSUBST0r : FPST0rInst <"fsub", 0xE0>; -def FSUBRrST0 : FPrST0Inst <"fsubr", 0xE0>, II<(ops RST:$op), "fsubr $op, %ST(0)">; -def FSUBRPrST0 : FPrST0PInst<"fsubrp", 0xE0>; - -def FMULST0r : FPST0rInst <"fmul", 0xC8>; -def FMULrST0 : FPrST0Inst <"fmul", 0xC8>, II<(ops RST:$op), "fmul $op, %ST(0)">; -def FMULPrST0 : FPrST0PInst<"fmulp", 0xC8>; - -def FDIVRST0r : FPST0rInst <"fdivr", 0xF8>; -def FDIVrST0 : FPrST0Inst <"fdiv", 0xF8>, II<(ops RST:$op), "fdiv $op, %ST(0)">; -def FDIVPrST0 : FPrST0PInst<"fdivp", 0xF8>; - -def FDIVST0r : FPST0rInst <"fdiv", 0xF0>; // ST(0) = ST(0) / ST(i) -def FDIVRrST0 : FPrST0Inst <"fdivr", 0xF0>, II<(ops RST:$op), "fdivr $op, %ST(0)">; // ST(i) = ST(0) / ST(i) -def FDIVRPrST0 : FPrST0PInst<"fdivrp", 0xF0>; // ST(i) = ST(0) / ST(i), pop +def FADDST0r : FPST0rInst <0xC0>, II<(ops RST:$op), "fadd $op">; +def FADDrST0 : FPrST0Inst <0xC0>, II<(ops RST:$op), "fadd $op, %ST(0)">; +def FADDPrST0 : FPrST0PInst<0xC0>, II<(ops RST:$op), "faddp $op">; + +def FSUBRST0r : FPST0rInst <0xE8>, II<(ops RST:$op), "fsubr $op">; +def FSUBrST0 : FPrST0Inst <0xE8>, II<(ops RST:$op), "fsub $op, %ST(0)">; +def FSUBPrST0 : FPrST0PInst<0xE8>, II<(ops RST:$op), "fsubp $op">; + +def FSUBST0r : FPST0rInst <0xE0>, II<(ops RST:$op), "fsub $op">; +def FSUBRrST0 : FPrST0Inst <0xE0>, II<(ops RST:$op), "fsubr $op, %ST(0)">; +def FSUBRPrST0 : FPrST0PInst<0xE0>, II<(ops RST:$op), "fsubrp $op">; + +def FMULST0r : FPST0rInst <0xC8>, II<(ops RST:$op), "fmul $op">; +def FMULrST0 : FPrST0Inst <0xC8>, II<(ops RST:$op), "fmul $op, %ST(0)">; +def FMULPrST0 : FPrST0PInst<0xC8>, II<(ops RST:$op), "fmulp $op">; + +def FDIVRST0r : FPST0rInst <0xF8>, II<(ops RST:$op), "fdivr $op">; +def FDIVrST0 : FPrST0Inst <0xF8>, II<(ops RST:$op), "fdiv $op, %ST(0)">; +def FDIVPrST0 : FPrST0PInst<0xF8>, II<(ops RST:$op), "fdivp $op">; + +def FDIVST0r : FPST0rInst <0xF0>, II<(ops RST:$op), "fdiv $op">; // ST(0) = ST(0) / ST(i) +def FDIVRrST0 : FPrST0Inst <0xF0>, II<(ops RST:$op), "fdivr $op, %ST(0)">; // ST(i) = ST(0) / ST(i) +def FDIVRPrST0 : FPrST0PInst<0xF0>, II<(ops RST:$op), "fdivrp $op">; // ST(i) = ST(0) / ST(i), pop // Floating point compares -def FUCOMr : FPI<"fucom", 0xE0, AddRegFrm, CompareFP>, DD, Imp<[ST0],[]>; // FPSW = compare ST(0) with ST(i) -def FUCOMPr : I<"fucomp" , 0xE8, AddRegFrm>, DD, Imp<[ST0],[]>; // FPSW = compare ST(0) with ST(i), pop -def FUCOMPPr : I<"fucompp", 0xE9, RawFrm >, DA, Imp<[ST0],[]>, // compare ST(0) with ST(1), pop, pop +def FUCOMr : FPI<"", 0xE0, AddRegFrm, CompareFP>, DD, Imp<[ST0],[]>, // FPSW = compare ST(0) with ST(i) + II<(ops RST:$reg), "fucom $reg">; +def FUCOMPr : I<0xE8, AddRegFrm>, DD, Imp<[ST0],[]>, // FPSW = compare ST(0) with ST(i), pop + II<(ops RST:$reg), "fucomp $reg">; +def FUCOMPPr : I<0xE9, RawFrm >, DA, Imp<[ST0],[]>, // compare ST(0) with ST(1), pop, pop II<(ops), "fucompp">; -def FUCOMIr : FPI<"fucomi", 0xE8, AddRegFrm, CompareFP>, DB, Imp<[ST0],[]>, // CC = compare ST(0) with ST(i) +def FUCOMIr : FPI<"", 0xE8, AddRegFrm, CompareFP>, DB, Imp<[ST0],[]>, // CC = compare ST(0) with ST(i) II<(ops RST:$reg), "fucomi %ST(0), $reg">; -def FUCOMIPr : I<"fucomip", 0xE8, AddRegFrm>, DF, Imp<[ST0],[]>, // CC = compare ST(0) with ST(i), pop +def FUCOMIPr : I<0xE8, AddRegFrm>, DF, Imp<[ST0],[]>, // CC = compare ST(0) with ST(i), pop II<(ops RST:$reg), "fucomip %ST(0), $reg">; // Floating point flag ops -def FNSTSW8r : I <"fnstsw" , 0xE0, RawFrm>, DF, Imp<[],[AX]>, // AX = fp flags +def FNSTSW8r : I<0xE0, RawFrm>, DF, Imp<[],[AX]>, // AX = fp flags II<(ops), "fnstsw">; -def FNSTCW16m : Im16<"fnstcw" , 0xD9, MRM7m >; // [mem16] = X87 control world -def FLDCW16m : Im16<"fldcw" , 0xD9, MRM5m >; // X87 control world = [mem16] +def FNSTCW16m : Im16<"fnstcw", 0xD9, MRM7m>; // [mem16] = X87 control world +def FLDCW16m : Im16<"fldcw" , 0xD9, MRM5m>; // X87 control world = [mem16] From llvm at cs.uiuc.edu Sun Aug 1 11:30:34 2004 From: llvm at cs.uiuc.edu (LLVM) Date: Sun, 1 Aug 2004 11:30:34 -0500 Subject: [llvm-commits] CVS: llvm/CREDITS.TXT Message-ID: <200408011630.LAA05992@zion.cs.uiuc.edu> Changes in directory llvm: CREDITS.TXT updated: 1.14 -> 1.15 --- Log message: Update. --- Diffs of the changes: (+2 -1) Index: llvm/CREDITS.TXT diff -u llvm/CREDITS.TXT:1.14 llvm/CREDITS.TXT:1.15 --- llvm/CREDITS.TXT:1.14 Thu Jul 22 17:43:21 2004 +++ llvm/CREDITS.TXT Sun Aug 1 11:30:24 2004 @@ -64,7 +64,8 @@ N: Reid Spencer E: rspencer at x10sys.com W: http://extprosys.sourceforge.net/ -D: Complete 'llvm' namespacification, Stacker, bug fixes, and other improvements +D: 'llvm' namespacification, Stacker FE, VMCore cleanup (SymbolTable, +D: Value != Type, CPR removal, bytecode improvements). N: Bill Wendling E: wendling at isanbard.org From lattner at cs.uiuc.edu Sun Aug 1 13:06:42 2004 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Sun, 1 Aug 2004 13:06:42 -0500 Subject: [llvm-commits] CVS: llvm/test/Regression/Bytecode/constexpr.ll constexpr.ll.bc-13 Message-ID: <200408011806.NAA04884@apoc.cs.uiuc.edu> Changes in directory llvm/test/Regression/Bytecode: constexpr.ll added (r1.1) constexpr.ll.bc-13 added (r1.1) --- Log message: Initial testcase for bytecode compatibility regression test. --- Diffs of the changes: (+97 -0) Index: llvm/test/Regression/Bytecode/constexpr.ll diff -c /dev/null llvm/test/Regression/Bytecode/constexpr.ll:1.1 *** /dev/null Sun Aug 1 13:06:38 2004 --- llvm/test/Regression/Bytecode/constexpr.ll Sun Aug 1 13:06:28 2004 *************** *** 0 **** --- 1,97 ---- + ; This bytecode test pounds on constant expressions + + ; RUN: llvm-as < %s | llvm-dis > %t1 + ; RUN: llvm-dis < %s.bc-13 > %t2 + ; RUN: diff %t1 %t2 + + ; This testcase is for testing expressions constructed from + ; constant values, including constant pointers to globals. + ; + + ;;------------------------------- + ;; Test constant cast expressions + ;;------------------------------- + + global ulong u0x00001 ; hexadecimal unsigned integer constants + global long s0x0012312 ; hexadecimal signed integer constants + + %t2 = global int* %t1 ;; Forward reference without cast + %t3 = global uint* cast (int* %t1 to uint*) ;; Forward reference with cast + %t1 = global int 4 ;; int* %0 + %t4 = global int** cast (uint** %t3 to int**) ;; Cast of a previous cast + %t5 = global uint** %t3 ;; Reference to a previous cast + %t6 = global int*** %t4 ;; Different ref. to a previous cast + %t7 = global float* cast (int 12345678 to float*) ;; Cast ordinary value to ptr + %t9 = global int cast (float cast (int 8 to float) to int) ;; Nested cast expression + + global int* cast (float* %0 to int*) ;; Forward numeric reference + global float* %0 ;; Duplicate forward numeric reference + global float 0.0 + + + ;;--------------------------------------------------- + ;; Test constant getelementpr expressions for arrays + ;;--------------------------------------------------- + + %array = constant [2 x int] [ int 12, int 52 ] + %arrayPtr = global int* getelementptr ([2 x int]* %array, long 0, long 0) ;; int* &%array[0][0] + %arrayPtr5 = global int** getelementptr (int** %arrayPtr, long 5) ;; int* &%arrayPtr[5] + + %somestr = constant [11x sbyte] c"hello world" + %char5 = global sbyte* getelementptr([11x sbyte]* %somestr, long 0, long 5) + + ;; cast of getelementptr + %char8a = global int* cast (sbyte* getelementptr([11x sbyte]* %somestr, long 0, long 8) to int*) + + ;; getelementptr containing casts + %char8b = global sbyte* getelementptr([11x sbyte]* %somestr, long cast (ubyte 0 to long), long cast (sbyte 8 to long)) + + ;;------------------------------------------------------- + ;; TODO: Test constant getelementpr expressions for structures + ;;------------------------------------------------------- + + %SType = type { int , {float, {ubyte} }, ulong } ;; struct containing struct + %SAType = type { int , {[2x float], ulong} } ;; struct containing array + + %S1 = global %SType* null ;; Global initialized to NULL + %S2c = constant %SType { int 1, {float,{ubyte}} {float 2.0, {ubyte} {ubyte 3}}, ulong 4} + + %S3c = constant %SAType { int 1, {[2x float], ulong} {[2x float] [float 2.0, float 3.0], ulong 4} } + + %S1ptr = global %SType** %S1 ;; Ref. to global S1 + %S2 = global %SType* %S2c ;; Ref. to constant S2 + %S3 = global %SAType* %S3c ;; Ref. to constant S3 + + ;; Pointer to float (**%S1).1.0 + %S1fld1a = global float* getelementptr (%SType* %S2c, long 0, ubyte 1, ubyte 0) + ;; Another ptr to the same! + %S1fld1b = global float* getelementptr (%SType* %S2c, long 0, ubyte 1, ubyte 0) + + %S1fld1bptr = global float** %S1fld1b ;; Ref. to previous pointer + + ;; Pointer to ubyte (**%S2).1.1.0 + %S2fld3 = global ubyte* getelementptr (%SType* %S2c, long 0, ubyte 1, ubyte 1, ubyte 0) + + ;; Pointer to float (**%S2).1.0[0] + ;%S3fld3 = global float* getelementptr (%SAType** %S3, long 0, long 0, ubyte 1, ubyte 0, long 0) + + ;;--------------------------------------------------------- + ;; TODO: Test constant expressions for unary and binary operators + ;;--------------------------------------------------------- + + + ;;--------------------------------------------------- + ;; Test duplicate constant expressions + ;;--------------------------------------------------- + + %t4 = global int** cast (uint** %t3 to int**) + + %char8a = global int* cast (sbyte* getelementptr([11x sbyte]* %somestr, long 0, long 8) to int*) + + ;%S3fld3 = global float* getelementptr (%SAType** %S3, long 0, long 0, ubyte 1, ubyte 0, long 0) + + + ;;--------------------------------------------------- + + implementation + Index: llvm/test/Regression/Bytecode/constexpr.ll.bc-13 From lattner at cs.uiuc.edu Sun Aug 1 13:17:46 2004 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Sun, 1 Aug 2004 13:17:46 -0500 Subject: [llvm-commits] CVS: llvm/include/llvm/Target/TargetInstrInfo.h Message-ID: <200408011817.NAA05756@apoc.cs.uiuc.edu> Changes in directory llvm/include/llvm/Target: TargetInstrInfo.h updated: 1.65 -> 1.66 --- Log message: Fix warning --- Diffs of the changes: (+2 -0) Index: llvm/include/llvm/Target/TargetInstrInfo.h diff -u llvm/include/llvm/Target/TargetInstrInfo.h:1.65 llvm/include/llvm/Target/TargetInstrInfo.h:1.66 --- llvm/include/llvm/Target/TargetInstrInfo.h:1.65 Sat Jul 31 04:37:52 2004 +++ llvm/include/llvm/Target/TargetInstrInfo.h Sun Aug 1 13:17:36 2004 @@ -167,6 +167,8 @@ virtual MachineBasicBlock::iterator reverseBranchCondition(MachineBasicBlock::iterator MI) const { assert(0 && "Target didn't implement reverseBranchCondition!"); + abort(); + return MI; } //------------------------------------------------------------------------- From tbrethou at cs.uiuc.edu Sun Aug 1 13:57:49 2004 From: tbrethou at cs.uiuc.edu (Tanya Brethour) Date: Sun, 1 Aug 2004 13:57:49 -0500 (CDT) Subject: [llvm-commits] CVS: llvm/include/llvm/Target/TargetSchedInfo.h Message-ID: <200408011857.NAA05220@seraph.cs.uiuc.edu> Changes in directory llvm/include/llvm/Target: TargetSchedInfo.h updated: 1.28 -> 1.29 --- Log message: Adding friend MSSchedule for ModuloScheduling pass. --- Diffs of the changes: (+1 -0) Index: llvm/include/llvm/Target/TargetSchedInfo.h diff -u llvm/include/llvm/Target/TargetSchedInfo.h:1.28 llvm/include/llvm/Target/TargetSchedInfo.h:1.29 --- llvm/include/llvm/Target/TargetSchedInfo.h:1.28 Mon Jul 26 23:00:54 2004 +++ llvm/include/llvm/Target/TargetSchedInfo.h Sun Aug 1 13:57:38 2004 @@ -305,6 +305,7 @@ friend class ModuloSchedulingPass; + friend class MSSchedule; }; From tbrethou at cs.uiuc.edu Sun Aug 1 14:00:27 2004 From: tbrethou at cs.uiuc.edu (Tanya Brethour) Date: Sun, 1 Aug 2004 14:00:27 -0500 (CDT) Subject: [llvm-commits] CVS: llvm/lib/CodeGen/Makefile Message-ID: <200408011900.OAA05240@seraph.cs.uiuc.edu> Changes in directory llvm/lib/CodeGen: Makefile updated: 1.21 -> 1.22 --- Log message: Adding ModuloScheduling so that it compiles for everyone. --- Diffs of the changes: (+1 -1) Index: llvm/lib/CodeGen/Makefile diff -u llvm/lib/CodeGen/Makefile:1.21 llvm/lib/CodeGen/Makefile:1.22 --- llvm/lib/CodeGen/Makefile:1.21 Tue Jun 22 12:52:30 2004 +++ llvm/lib/CodeGen/Makefile Sun Aug 1 14:00:17 2004 @@ -8,7 +8,7 @@ ##===----------------------------------------------------------------------===## LEVEL = ../.. -PARALLEL_DIRS = InstrSched SelectionDAG +PARALLEL_DIRS = InstrSched SelectionDAG ModuloScheduling LIBRARYNAME = codegen include $(LEVEL)/Makefile.common From lattner at cs.uiuc.edu Sun Aug 1 14:31:40 2004 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Sun, 1 Aug 2004 14:31:40 -0500 Subject: [llvm-commits] CVS: llvm/lib/Target/X86/X86InstrInfo.cpp Message-ID: <200408011931.OAA14473@apoc.cs.uiuc.edu> Changes in directory llvm/lib/Target/X86: X86InstrInfo.cpp updated: 1.31 -> 1.32 --- Log message: Fix a warning --- Diffs of the changes: (+1 -2) Index: llvm/lib/Target/X86/X86InstrInfo.cpp diff -u llvm/lib/Target/X86/X86InstrInfo.cpp:1.31 llvm/lib/Target/X86/X86InstrInfo.cpp:1.32 --- llvm/lib/Target/X86/X86InstrInfo.cpp:1.31 Sat Jul 31 05:05:44 2004 +++ llvm/lib/Target/X86/X86InstrInfo.cpp Sun Aug 1 14:31:30 2004 @@ -50,6 +50,7 @@ assert(isBranch(Opcode) && "MachineInstr must be a branch"); unsigned ROpcode; switch (Opcode) { + default: assert(0 && "Cannot reverse unconditional branches!"); case X86::JB: ROpcode = X86::JAE; break; case X86::JAE: ROpcode = X86::JB; break; case X86::JE: ROpcode = X86::JNE; break; @@ -62,8 +63,6 @@ case X86::JGE: ROpcode = X86::JL; break; case X86::JLE: ROpcode = X86::JG; break; case X86::JG: ROpcode = X86::JLE; break; - default: - assert(0 && "Cannot reverse unconditional branches!"); } MachineBasicBlock* MBB = MI->getParent(); MachineBasicBlock* TMBB = MI->getOperand(0).getMachineBasicBlock(); From lattner at cs.uiuc.edu Sun Aug 1 14:43:09 2004 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Sun, 1 Aug 2004 14:43:09 -0500 Subject: [llvm-commits] CVS: llvm/lib/Transforms/Scalar/InstructionCombining.cpp Message-ID: <200408011943.OAA15099@apoc.cs.uiuc.edu> Changes in directory llvm/lib/Transforms/Scalar: InstructionCombining.cpp updated: 1.235 -> 1.236 --- Log message: Fix a regression in InstCombine/xor.ll --- Diffs of the changes: (+2 -2) Index: llvm/lib/Transforms/Scalar/InstructionCombining.cpp diff -u llvm/lib/Transforms/Scalar/InstructionCombining.cpp:1.235 llvm/lib/Transforms/Scalar/InstructionCombining.cpp:1.236 --- llvm/lib/Transforms/Scalar/InstructionCombining.cpp:1.235 Fri Jul 30 07:50:08 2004 +++ llvm/lib/Transforms/Scalar/InstructionCombining.cpp Sun Aug 1 14:42:59 2004 @@ -1343,11 +1343,11 @@ return ReplaceInstUsesWith(I, Op0I->getOperand(0)); } - // (A & C1)^(B & C2) -> (A & C1)|(B & C2) iff C1^C2 == 0 + // (A & C1)^(B & C2) -> (A & C1)|(B & C2) iff C1&C2 == 0 Value *A, *B; ConstantInt *C1, *C2; if (match(Op0, m_And(m_Value(A), m_ConstantInt(C1))) && match(Op1, m_And(m_Value(B), m_ConstantInt(C2))) && - ConstantExpr::getXor(C1, C2)->isNullValue()) + ConstantExpr::getAnd(C1, C2)->isNullValue()) return BinaryOperator::createOr(Op0, Op1); // (setcc1 A, B) ^ (setcc2 A, B) --> (setcc3 A, B)