From natebegeman at mac.com Mon Aug 16 00:06:53 2004 From: natebegeman at mac.com (Nate Begeman) Date: Mon, 16 Aug 2004 00:06:53 -0500 Subject: [llvm-commits] CVS: llvm/lib/Target/PowerPC/README.txt Message-ID: <200408160506.AAA01233@zion.cs.uiuc.edu> Changes in directory llvm/lib/Target/PowerPC: README.txt updated: 1.14 -> 1.15 --- Log message: Update the current state of the world --- Diffs of the changes: (+1 -6) Index: llvm/lib/Target/PowerPC/README.txt diff -u llvm/lib/Target/PowerPC/README.txt:1.14 llvm/lib/Target/PowerPC/README.txt:1.15 --- llvm/lib/Target/PowerPC/README.txt:1.14 Sun Aug 15 01:43:10 2004 +++ llvm/lib/Target/PowerPC/README.txt Mon Aug 16 00:06:43 2004 @@ -30,19 +30,14 @@ b .LBBl42__2E_expand_function_8_42 ; NewDefault b .LBBl42__2E_expand_function_8_42 ; NewDefault -Currently failing tests: +Currently failing tests that should pass: * SingleSource `- Regression | `- casts (ulong to fp failure) `- Benchmarks | `- Shootout-C++ : most programs fail, miscompilations - `- UnitTests - | `- C++Catch - | `- SimpleC++Test - | `- ConditionalExpr (also C++) * MultiSource |- Applications - | `- burg: miscompilation | `- hbd: miscompilation | `- d (make_dparser): miscompilation `- Benchmarks From lattner at cs.uiuc.edu Mon Aug 16 00:10:10 2004 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Mon, 16 Aug 2004 00:10:10 -0500 Subject: [llvm-commits] CVS: llvm/lib/Target/PowerPC/PowerPCFrameInfo.h Message-ID: <200408160510.AAA09948@apoc.cs.uiuc.edu> Changes in directory llvm/lib/Target/PowerPC: PowerPCFrameInfo.h updated: 1.2 -> 1.3 --- Log message: There is no need for a cast here --- Diffs of the changes: (+1 -1) Index: llvm/lib/Target/PowerPC/PowerPCFrameInfo.h diff -u llvm/lib/Target/PowerPC/PowerPCFrameInfo.h:1.2 llvm/lib/Target/PowerPC/PowerPCFrameInfo.h:1.3 --- llvm/lib/Target/PowerPC/PowerPCFrameInfo.h:1.2 Sun Aug 15 04:17:00 2004 +++ llvm/lib/Target/PowerPC/PowerPCFrameInfo.h Mon Aug 16 00:09:58 2004 @@ -36,7 +36,7 @@ const std::pair * getCalleeSaveSpillSlots(unsigned &NumEntries) const { NumEntries = 1; - return static_cast *>(LR); + return &LR[0]; } }; From lattner at cs.uiuc.edu Mon Aug 16 00:38:15 2004 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Mon, 16 Aug 2004 00:38:15 -0500 Subject: [llvm-commits] CVS: llvm/lib/Analysis/IPA/Andersens.cpp Message-ID: <200408160538.AAA10521@apoc.cs.uiuc.edu> Changes in directory llvm/lib/Analysis/IPA: Andersens.cpp updated: 1.5 -> 1.6 --- Log message: Fix a bug that caused the pass to go into infinite loops on trivial testcases. This is fallout of the Bug 122: http://llvm.cs.uiuc.edu/PR122 changes. --- Diffs of the changes: (+2 -1) Index: llvm/lib/Analysis/IPA/Andersens.cpp diff -u llvm/lib/Analysis/IPA/Andersens.cpp:1.5 llvm/lib/Analysis/IPA/Andersens.cpp:1.6 --- llvm/lib/Analysis/IPA/Andersens.cpp:1.5 Sat Jul 17 19:18:30 2004 +++ llvm/lib/Analysis/IPA/Andersens.cpp Mon Aug 16 00:38:02 2004 @@ -251,7 +251,8 @@ /// Node *getNode(Value *V) { if (Constant *C = dyn_cast(V)) - return getNodeForConstantPointer(C); + if (!isa(C)) + return getNodeForConstantPointer(C); std::map::iterator I = ValueNodes.find(V); if (I == ValueNodes.end()) { From lattner at cs.uiuc.edu Mon Aug 16 00:39:29 2004 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Mon, 16 Aug 2004 00:39:29 -0500 Subject: [llvm-commits] CVS: llvm/test/Regression/Analysis/Andersens/trivialtest.ll Message-ID: <200408160539.AAA10542@apoc.cs.uiuc.edu> Changes in directory llvm/test/Regression/Analysis/Andersens: trivialtest.ll added (r1.1) --- Log message: Believe it or not, this was broken in LLVM 1.3 --- Diffs of the changes: (+3 -0) Index: llvm/test/Regression/Analysis/Andersens/trivialtest.ll diff -c /dev/null llvm/test/Regression/Analysis/Andersens/trivialtest.ll:1.1 *** /dev/null Mon Aug 16 00:39:29 2004 --- llvm/test/Regression/Analysis/Andersens/trivialtest.ll Mon Aug 16 00:39:19 2004 *************** *** 0 **** --- 1,3 ---- + ; RUN: llvm-as < %s | opt -anders-aa -disable-output + + void %foo() { ret void } From lattner at cs.uiuc.edu Mon Aug 16 00:47:10 2004 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Mon, 16 Aug 2004 00:47:10 -0500 Subject: [llvm-commits] CVS: llvm/docs/ReleaseNotes.html Message-ID: <200408160547.AAA10587@apoc.cs.uiuc.edu> Changes in directory llvm/docs: ReleaseNotes.html updated: 1.229 -> 1.230 --- Log message: Bug fixed --- Diffs of the changes: (+3 -2) Index: llvm/docs/ReleaseNotes.html diff -u llvm/docs/ReleaseNotes.html:1.229 llvm/docs/ReleaseNotes.html:1.230 --- llvm/docs/ReleaseNotes.html:1.229 Sun Aug 15 19:20:18 2004 +++ llvm/docs/ReleaseNotes.html Mon Aug 16 00:46:57 2004 @@ -154,7 +154,8 @@

Bugs fixed in the LLVM Core:

    -
  1. +
  2. [anders-aa] Andersen's AA is completely + broken in LLVM 1.3

Bugs in the C/C++ front-end:

@@ -594,7 +595,7 @@ src="http://www.w3.org/Icons/valid-html401" alt="Valid HTML 4.01!" /> The LLVM Compiler Infrastructure
- Last modified: $Date: 2004/08/16 00:20:18 $ + Last modified: $Date: 2004/08/16 05:46:57 $ From lattner at cs.uiuc.edu Mon Aug 16 00:49:35 2004 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Mon, 16 Aug 2004 00:49:35 -0500 Subject: [llvm-commits] CVS: llvm-www/releases/1.3/docs/ReleaseNotes.html Message-ID: <200408160549.AAA10611@apoc.cs.uiuc.edu> Changes in directory llvm-www/releases/1.3/docs: ReleaseNotes.html updated: 1.1 -> 1.2 --- Log message: Unfortunately, anders-aa was completely broken :( --- Diffs of the changes: (+7 -2) Index: llvm-www/releases/1.3/docs/ReleaseNotes.html diff -u llvm-www/releases/1.3/docs/ReleaseNotes.html:1.1 llvm-www/releases/1.3/docs/ReleaseNotes.html:1.2 --- llvm-www/releases/1.3/docs/ReleaseNotes.html:1.1 Fri Aug 13 17:03:04 2004 +++ llvm-www/releases/1.3/docs/ReleaseNotes.html Mon Aug 16 00:49:24 2004 @@ -110,7 +110,9 @@ of aggressive copying and generational collectors.
  • LLVM now includes a simple implementation of Andersen's interprocedural alias -analysis algorithm.
  • +analysis algorithm. NOTE: anders-aa is unfortunately completely broken in LLVM 1.3. See the link +for a trivial patch to fix it.
  • Bugpoint can extract individual basic blocks to track down reduce miscompilation testcases.
  • LLVM and the C front-end now work under Win32 using the @@ -440,6 +442,9 @@ values live across a setjmp as volatile. This missing feature only affects targets whose setjmp/longjmp libraries do not save and restore the entire register file.
  • + +
  • [anders-aa] Andersen's AA is completely + broken in LLVM 1.3
  • @@ -766,7 +771,7 @@ src="http://www.w3.org/Icons/valid-html401" alt="Valid HTML 4.01!" /> The LLVM Compiler Infrastructure
    - Last modified: $Date: 2004/08/13 22:03:04 $ + Last modified: $Date: 2004/08/16 05:49:24 $ From reid at x10sys.com Mon Aug 16 02:06:24 2004 From: reid at x10sys.com (Reid Spencer) Date: Mon, 16 Aug 2004 02:06:24 -0500 Subject: [llvm-commits] CVS: llvm/tools/llvmc/ll Message-ID: <200408160706.CAA02134@zion.cs.uiuc.edu> Changes in directory llvm/tools/llvmc: ll updated: 1.1 -> 1.2 --- Log message: Fix definitions to match tool's actual capabilities. --- Diffs of the changes: (+3 -0) Index: llvm/tools/llvmc/ll diff -u llvm/tools/llvmc/ll:1.1 llvm/tools/llvmc/ll:1.2 --- llvm/tools/llvmc/ll:1.1 Sun Aug 15 03:16:12 2004 +++ llvm/tools/llvmc/ll Mon Aug 16 02:06:13 2004 @@ -4,9 +4,12 @@ preprocessor.required=false translator.command=llvm-as @in@ -o @out@ translator.groks_dash_O=no + translator.groks_optimization=no translator.optimizes=no translator.preprocesses=true translator.required=TRUE optimizer.command=opt @in@ -o @out@ + optimizer.groks_dash_O=no + optimizer.groks_optimization=yes assembler.command=llc @in@ -o @out@ linker.command=llvm-link @in@ -o @out@ From reid at x10sys.com Mon Aug 16 02:06:48 2004 From: reid at x10sys.com (Reid Spencer) Date: Mon, 16 Aug 2004 02:06:48 -0500 Subject: [llvm-commits] CVS: llvm/tools/llvmc/CompilerDriver.cpp CompilerDriver.h Message-ID: <200408160706.CAA02149@zion.cs.uiuc.edu> Changes in directory llvm/tools/llvmc: CompilerDriver.cpp updated: 1.4 -> 1.5 CompilerDriver.h updated: 1.4 -> 1.5 --- Log message: Back out dependencies on lib/System/Path.h --- Diffs of the changes: (+32 -26) Index: llvm/tools/llvmc/CompilerDriver.cpp diff -u llvm/tools/llvmc/CompilerDriver.cpp:1.4 llvm/tools/llvmc/CompilerDriver.cpp:1.5 --- llvm/tools/llvmc/CompilerDriver.cpp:1.4 Sun Aug 15 03:19:46 2004 +++ llvm/tools/llvmc/CompilerDriver.cpp Mon Aug 16 02:06:38 2004 @@ -70,8 +70,19 @@ std::cerr << "Linker: "; DumpAction(&cd->Linker); } -} + void CleanupTempFile(const char* fname) { + if (0 == access(fname, F_OK | R_OK)) + unlink(fname); + } + + /// This specifies the passes to run for OPT_FAST_COMPILE (-O1) + /// which should reduce the volume of code and make compilation + /// faster. This is also safe on any llvm module. + static const char* DefaultOptimizations[] = { + "-simplifycfg", "-mem2reg", "-mergereturn", "-instcombine", + }; +} CompilerDriver::CompilerDriver(ConfigDataProvider& confDatProv ) : cdp(&confDatProv) @@ -215,7 +226,7 @@ } int CompilerDriver::execute(const InputList& InpList, - const sys::Path& Output ) { + const std::string& Output ) { // Echo the configuration of options if we're running verbose if (isDebug) { @@ -248,12 +259,15 @@ std::vector actions; // Create a temporary directory for our temporary files - sys::Path TempDir(sys::Path::CONSTRUCT_TEMP_DIR); - sys::Path TempPreprocessorOut; - sys::Path TempTranslatorOut; - sys::Path TempOptimizerOut; - sys::Path TempAssemblerOut; - sys::Path TempLinkerOut; + char temp_name[64]; + strcpy(temp_name,"/tmp/llvm_XXXXXX"); + if (0 == mkdtemp(temp_name)) + error("Can't create temporary directory"); + std::string TempDir(temp_name); + std::string TempPreprocessorOut(TempDir + "/preproc.tmp"); + std::string TempTranslatorOut(TempDir + "/trans.tmp"); + std::string TempOptimizerOut(TempDir + "/opt.tmp"); + std::string TempAssemblerOut(TempDir + "/asm.tmp"); /// PRE-PROCESSING / TRANSLATION / OPTIMIZATION / ASSEMBLY phases // for each input item @@ -304,8 +318,6 @@ // Get the preprocessing action, if needed, or error if appropriate if (!a.program.empty()) { if (a.isSet(REQUIRED_FLAG) || finalPhase == PREPROCESSING) { - TempPreprocessorOut = TempDir; - TempPreprocessorOut.append_file("preproc.out"); actions.push_back(GetAction(cd,I->first, TempPreprocessorOut,PREPROCESSING)); } @@ -324,8 +336,6 @@ // Get the translation action, if needed, or error if appropriate if (!a.program.empty()) { if (a.isSet(REQUIRED_FLAG) || finalPhase == TRANSLATION) { - TempTranslatorOut = TempDir; - TempTranslatorOut.append_file("trans.out"); actions.push_back(GetAction(cd,I->first,TempTranslatorOut,TRANSLATION)); } } else if (finalPhase == TRANSLATION) { @@ -342,8 +352,6 @@ // Get the optimization action, if needed, or error if appropriate if (!a.program.empty()) { - TempOptimizerOut = TempDir; - TempOptimizerOut.append_file("trans.out"); actions.push_back(GetAction(cd,I->first,TempOptimizerOut,OPTIMIZATION)); } else if (finalPhase == OPTIMIZATION) { error(cd->langName + " does not support optimization"); @@ -367,14 +375,13 @@ } // Cleanup files - if (TempPreprocessorOut.exists()) - TempPreprocessorOut.remove_file(); - if (TempTranslatorOut.exists()) - TempTranslatorOut.remove_file(); - if (TempOptimizerOut.exists()) - TempOptimizerOut.remove_file(); - if (TempDir.exists()) - TempDir.remove_directory(); + CleanupTempFile(TempPreprocessorOut.c_str()); + CleanupTempFile(TempTranslatorOut.c_str()); + CleanupTempFile(TempOptimizerOut.c_str()); + + // Cleanup temporary directory we created + if (0 == access(TempDir.c_str(), F_OK | W_OK)) + rmdir(TempDir.c_str()); return 0; } Index: llvm/tools/llvmc/CompilerDriver.h diff -u llvm/tools/llvmc/CompilerDriver.h:1.4 llvm/tools/llvmc/CompilerDriver.h:1.5 --- llvm/tools/llvmc/CompilerDriver.h:1.4 Sun Aug 15 03:19:46 2004 +++ llvm/tools/llvmc/CompilerDriver.h Mon Aug 16 02:06:38 2004 @@ -14,7 +14,6 @@ #ifndef LLVM_TOOLS_LLVMC_COMPILERDRIVER_H #define LLVM_TOOLS_LLVMC_COMPILERDRIVER_H -#include "llvm/System/Path.h" #include #include @@ -66,7 +65,7 @@ /// a vector of filename/filetype pairs. The filetype is used to look up /// the configuration of the actions to be taken by the driver. /// @brief The Input Data to the execute method - typedef std::vector > InputList; + typedef std::vector > InputList; /// This type is read from configuration files or otherwise provided to /// the CompilerDriver through a "ConfigDataProvider". It serves as both @@ -75,7 +74,7 @@ /// language. struct Action { Action() : inputAt(0) , outputAt(0), flags(0) {} - sys::Path program; ///< The program to execve + std::string program; ///< The program to execve StringVector args; ///< Arguments to the program size_t inputAt; ///< Argument index to insert input file size_t outputAt; ///< Argument index to insert output file @@ -122,7 +121,7 @@ virtual void error(const std::string& errmsg); /// @brief Execute the actions requested for the given input list. - virtual int execute(const InputList& list, const sys::Path& output); + virtual int execute(const InputList& list, const std::string& output); /// @} /// @name Mutators From llvm at cs.uiuc.edu Mon Aug 16 02:08:49 2004 From: llvm at cs.uiuc.edu (LLVM) Date: Mon, 16 Aug 2004 02:08:49 -0500 Subject: [llvm-commits] CVS: llvm/lib/System/linux/ErrorCode.cpp LinuxCommon.h Path.cpp Message-ID: <200408160708.CAA02177@zion.cs.uiuc.edu> Changes in directory llvm/lib/System/linux: ErrorCode.cpp (r1.1) removed LinuxCommon.h (r1.1) removed Path.cpp (r1.1) removed --- Log message: Remove lib/System contents until a satisfactory solution can be provided. --- Diffs of the changes: (+0 -0) From llvm at cs.uiuc.edu Mon Aug 16 02:08:50 2004 From: llvm at cs.uiuc.edu (LLVM) Date: Mon, 16 Aug 2004 02:08:50 -0500 Subject: [llvm-commits] CVS: llvm/lib/System/ErrorCode.cpp Makefile Path.cpp README.txt Message-ID: <200408160708.CAA02180@zion.cs.uiuc.edu> Changes in directory llvm/lib/System: ErrorCode.cpp (r1.1) removed Makefile (r1.1) removed Path.cpp (r1.1) removed README.txt (r1.1) removed --- Log message: Remove lib/System contents until a satisfactory solution can be provided. --- Diffs of the changes: (+0 -0) From llvm at cs.uiuc.edu Mon Aug 16 02:10:20 2004 From: llvm at cs.uiuc.edu (LLVM) Date: Mon, 16 Aug 2004 02:10:20 -0500 Subject: [llvm-commits] CVS: llvm/include/llvm/System/ErrorCode.h Path.h README.txt Message-ID: <200408160710.CAA02225@zion.cs.uiuc.edu> Changes in directory llvm/include/llvm/System: ErrorCode.h (r1.1) removed Path.h (r1.1) removed README.txt (r1.1) removed --- Log message: Back out include/llvm/System changes until a satisfactory solution can be determined. --- Diffs of the changes: (+0 -0) From reid at x10sys.com Mon Aug 16 02:46:44 2004 From: reid at x10sys.com (Reid Spencer) Date: Mon, 16 Aug 2004 02:46:44 -0500 Subject: [llvm-commits] CVS: llvm/lib/VMCore/AsmWriter.cpp Message-ID: <200408160746.CAA02521@zion.cs.uiuc.edu> Changes in directory llvm/lib/VMCore: AsmWriter.cpp updated: 1.153 -> 1.154 --- Log message: Fix PR422: http://llvm.cs.uiuc.edu/PR422 . Ouch! Changes in the lazy initialization code caused each incorporated function to reprocess the entire function on every lookup of a value's slot number. This caused a horrible slowdown in all functions. This fix made llvm-dis go from "longer than I care to wait" (minutes) on a large test case to 0.53 seconds. --- Diffs of the changes: (+11 -2) Index: llvm/lib/VMCore/AsmWriter.cpp diff -u llvm/lib/VMCore/AsmWriter.cpp:1.153 llvm/lib/VMCore/AsmWriter.cpp:1.154 --- llvm/lib/VMCore/AsmWriter.cpp:1.153 Thu Jul 29 11:53:53 2004 +++ llvm/lib/VMCore/AsmWriter.cpp Mon Aug 16 02:46:33 2004 @@ -92,7 +92,10 @@ public: /// If you'd like to deal with a function instead of just a module, use /// this method to get its data into the SlotMachine. - void incorporateFunction(const Function *F) { TheFunction = F; } + void incorporateFunction(const Function *F) { + TheFunction = F; + FunctionProcessed = false; + } /// After calling incorporateFunction, use this method to remove the /// most recently incorporated function from the SlotMachine. This @@ -138,6 +141,7 @@ /// @brief The function for which we are holding slot numbers const Function* TheFunction; + bool FunctionProcessed; /// @brief The TypePlanes map for the module level data TypedPlanes mMap; @@ -1263,6 +1267,7 @@ SlotMachine::SlotMachine(const Module *M) : TheModule(M) ///< Saved for lazy initialization. , TheFunction(0) + , FunctionProcessed(false) , mMap() , mTypes() , fMap() @@ -1275,6 +1280,7 @@ SlotMachine::SlotMachine(const Function *F ) : TheModule( F ? F->getParent() : 0 ) ///< Saved for lazy initialization , TheFunction(F) ///< Saved for lazy initialization + , FunctionProcessed(false) , mMap() , mTypes() , fMap() @@ -1287,7 +1293,7 @@ processModule(); TheModule = 0; ///< Prevent re-processing next time we're called. } - if ( TheFunction ) { + if ( TheFunction && ! FunctionProcessed) { processFunction(); } } @@ -1331,6 +1337,8 @@ } } + FunctionProcessed = true; + SC_DEBUG("end processFunction!\n"); } @@ -1343,6 +1351,7 @@ fMap.clear(); // Simply discard the function level map fTypes.clear(); TheFunction = 0; + FunctionProcessed = false; SC_DEBUG("end purgeFunction!\n"); } From criswell at cs.uiuc.edu Mon Aug 16 09:51:51 2004 From: criswell at cs.uiuc.edu (John Criswell) Date: Mon, 16 Aug 2004 09:51:51 -0500 Subject: [llvm-commits] CVS: llvm/docs/GettingStarted.html Message-ID: <200408161451.JAA19127@choi.cs.uiuc.edu> Changes in directory llvm/docs: GettingStarted.html updated: 1.65 -> 1.66 --- Log message: Merged in release_13 branch. --- Diffs of the changes: (+22 -20) Index: llvm/docs/GettingStarted.html diff -u llvm/docs/GettingStarted.html:1.65 llvm/docs/GettingStarted.html:1.66 --- llvm/docs/GettingStarted.html:1.65 Mon Aug 9 14:57:01 2004 +++ llvm/docs/GettingStarted.html Mon Aug 16 09:51:33 2004 @@ -188,31 +188,31 @@
  • Linux on x86 (Pentium and above)
      -
    • Approximately 1.02 GB of Free Disk Space +
    • Approximately 2.6 GB of Free Disk Space
        -
      • Source code: 45 MB
      • -
      • Object code: 956 MB
      • -
      • GCC front end: 40 MB
      • +
      • Source code: 57 MB
      • +
      • Object code: 2.5 GB
      • +
      • GCC front end: 30 MB
  • Solaris on SparcV9 (Ultrasparc)
      -
    • Approximately 1.75 GB of Free Disk Space +
    • Approximately 2.6 GB of Free Disk Space
        -
      • Source code: 45 MB
      • -
      • Object code: 1.7 GB
      • -
      • GCC front end: 50 MB
      • +
      • Source code: 57 MB
      • +
      • Object code: 2.5 GB
      • +
      • GCC front end: 46 MB
  • FreeBSD on x86 (Pentium and above)
      -
    • Approximately 935 MB of Free Disk Space +
    • Approximately 1 GB of Free Disk Space
        -
      • Source code: 45 MB
      • +
      • Source code: 57 MB
      • Object code: 850 MB
      • GCC front end: 40 MB
    • @@ -221,11 +221,12 @@
    • MacOS X on PowerPC
        -
      • Approximately 1.25 GB of Free Disk Space +
      • Experimental support for static native code generation +
      • Approximately 1.6 GB of Free Disk Space
          -
        • Source code: 45 MB
        • -
        • Object code: 1.2 GB
        • -
        • GCC front end: 40 MB
        • +
        • Source code: 57 MB
        • +
        • Object code: 1.5 GB
        • +
        • GCC front end: 36 MB
    • @@ -442,23 +443,23 @@

      The files are as follows:

      -
      llvm-1.2.tar.gz +
      llvm-1.3.tar.gz
      This is the source code to the LLVM suite.

      -

      cfrontend-1.2.sparc-sun-solaris2.8.tar.gz +
      cfrontend-1.3.sparc-sun-solaris2.8.tar.gz
      This is the binary release of the GCC front end for Solaris/Sparc.

      -

      cfrontend-1.2.i686-redhat-linux-gnu.tar.gz +
      cfrontend-1.3.i686-redhat-linux-gnu.tar.gz
      This is the binary release of the GCC front end for Linux/x86.

      -

      cfrontend-1.2.i386-unknown-freebsd5.1.tar.gz +
      cfrontend-1.3.i386-unknown-freebsd5.1.tar.gz
      This is the binary release of the GCC front end for FreeBSD/x86.

      -

      cfrontend-1.2.powerpc-apple-darwin7.0.0.tar.gz +
      cfrontend-1.3.powerpc-apple-darwin7.0.0.tar.gz
      This is the binary release of the GCC front end for MacOS X/PPC.
      @@ -492,6 +493,7 @@ label:

        +
      • Release 1.3: RELEASE_13
      • Release 1.2: RELEASE_12
      • Release 1.1: RELEASE_11
      • Release 1.0: RELEASE_1
      • @@ -1278,7 +1280,7 @@ Chris Lattner
        The LLVM Compiler Infrastructure
        - Last modified: $Date: 2004/08/09 19:57:01 $ + Last modified: $Date: 2004/08/16 14:51:33 $ From criswell at cs.uiuc.edu Mon Aug 16 10:10:35 2004 From: criswell at cs.uiuc.edu (John Criswell) Date: Mon, 16 Aug 2004 10:10:35 -0500 Subject: [llvm-commits] CVS: llvm/test/QMTest/expectations.darwin.qmr expectations.sunos.qmr Message-ID: <200408161510.KAA11753@choi.cs.uiuc.edu> Changes in directory llvm/test/QMTest: expectations.darwin.qmr updated: 1.5 -> 1.6 expectations.sunos.qmr updated: 1.12 -> 1.13 --- Log message: Merged in RELEASE_13. --- Diffs of the changes: (+2 -2) Index: llvm/test/QMTest/expectations.darwin.qmr diff -u llvm/test/QMTest/expectations.darwin.qmr:1.5 llvm/test/QMTest/expectations.darwin.qmr:1.6 --- llvm/test/QMTest/expectations.darwin.qmr:1.5 Mon Aug 2 10:12:29 2004 +++ llvm/test/QMTest/expectations.darwin.qmr Mon Aug 16 10:10:22 2004 @@ -3,13 +3,13 @@ qoq}q(U _Result__kindqUtestqU_Result__outcomeqUPASSqU_Result__annotationsq}U _Result__idq U0Regression.Assembler.2002-08-16-ConstExprInlinedq U_Result__contextq (cqm.test.context Context -q o}q (U_Context__propertiesq}U_Context__temporariesq}ubub.(hoq}q(hhhhh}h U(Regression.Transforms.PruneEH.simpletestqh (h o}q(h}h}ubub.(hoq}q(hhhhh}h U/Regression.CBackend.2002-08-19-HardConstantExprqh (h o}q(h}h}ubub.(hoq}q(hhhhh}h URegression.Jello.test-shiftqh (h o}q(h}h}ubub.(hoq}q(hhhUFAILqh}h U.Regression.Transforms.CorrelatedExprs.looptestqh (h o}q (h}h}ubub.(hoq!}q"(hhhhh}h U-Regression.Linker.2003-08-23-GlobalVarLinkingq#h (h o}q$(h}h}ubub.(hoq%}q&(hhhhh}h U?Regression.Transforms.Inline.2003-09-22-PHINodesInExceptionDestq'h (h o}q((h}h}ubub.(hoq)}q*(hhhhh}h U,Regression.CFrontend.2003-02-12-NonlocalGotoq+h (h o}q,(h}h}ubub.(hoq-}q.(hhhhh}h U2Regression.Transforms.FunctionResolve.retmismatch1q/h (h o}q0(h}h}ubub.(hoq1}q2(hhhhh}h U>Regression.Transforms.LevelRaise.2002-05-02-BadCastEliminationq3h (h o}q4(h}h}ubub.(hoq5}q6(hhhhh}h U8Regression.Transforms.ADCE.2003-01-22-! PredecessorProblemq7h (h o}q8(h}h}ubub.(hoq9}q:(hhhhh}h U=Regression.Transforms.LevelRaise.2002-10-08-VarArgCallInfLoopq;h (h o}q<(h}h}ubub.(hoq=}q>(hhhhh}h U5Regression.CFrontend.2003-07-22-ArrayAccessTypeSafetyq?h (h o}q@(h}h}ubub.(hoqA}qB(hhhhh}h U8Regression.C++Frontend.2003-09-29-ArgumentNumberMismatchqCh (h o}qD(h}h}ubub.(hoqE}qF(hhhhh}h U1Regression.CFrontend.2002-03-12-StructInitializerqGh (h o}qH(h}h}ubub.(hoqI}qJ(hhhhh}h U+Regression.CFrontend.2002-09-19-StarInLabelqKh (h o}qL(h}h}ubub.(hoqM}qN(hhhhh}h U.Regression.CFrontend.2003-08-23-LocalUnionTestqOh (h o}qP(h}h}ubub.(hoqQ}qR(hhhhh}h U"Regression.Jello.2003-06-05-PHIBugqSh (h o}qT(h}h}ubub.(hoqU}qV(hhhUPASSqWh}h U$Regression.BugPoint.misopt-basictestqXh (h o}qY(h}h}ubub.(hoqZ}q[(hhhhh}h U/Regression.Linker.2003-04-26-NullPtrLinkProblemq\h (h o}q](h}h}ubub.(hoq^}q_(hhhhh}h U)Regression.Transforms.Reassociate.subtestq`h (h o}qa(h}h}! ubub.(hoqb}qc(hhhhh}h U)Regression.Linker.2002-08-20-ConstantExp rqdh (h o}qe(h}h}ubub.(hoqf}qg(hhhhh}h U=Regression.Transforms.Reassociate.2002-05-15-AgressiveSubMoveqhh (h o}qi(h}h}ubub.(hoqj}qk(hhhhh}h UARegression.Transforms.CorrelatedExprs.2002-10-07-DominatorProblemqlh (h o}qm(h}h}ubub.(hoqn}qo(hhhhh}h U>Regression.Transforms.InstCombine.2003-06-22-ConstantExprCrashqph (h o}qq(h}h}ubub.(hoqr}qs(hhhhh}h U3Regression.Transforms.PiNodeInserter.substitutetestqth (h o}qu(h}h}ubub.(hoqv}qw(hhhhh}h U4Regression.Transforms.SCCP.2003-08-26-InvokeHandlingqxh (h o}qy(h}h}ubub.(hoqz}q{(hhhhh}h U$Regression.Jello.2003-01-04-LoopTestq|h (h o}q}(h}h}ubub.(hoq~}q(hhhhh}h U1Regression.Assembler.2002-04-04-PureVirtMethCall2q?h (h o}q?(h}h}ubub.(hoq?}q?(hhhhh}h U)Regression.CFrontend.2002-07-14-MiscTestsq?h (h o}q?(h}h}ubub.(hoq?}q?(hhhhh}h U(hhhhh}h U=Regression.Transforms.LevelRaise.2002-10-08-VarArgCallInfLoopq?h (h o}q@(h}h}ubub.(hoqA}qB(hhhhh}h U5Regression.CFrontend.2003-07-22-ArrayAccessTypeSafetyqCh (h o}qD(h}h}ubub.(hoqE}qF(hhhhh}h U8Regression.C++Frontend.2003-09-29-ArgumentNumberMismatchqGh (h o}qH(h}h}ubub.(hoqI}qJ(hhhhh}h U+Regression.CFrontend.2002-09-19-StarInLabelqKh (h o}qL(h}h}ubub.(hoqM}qN(hhhhh}h U.Regression.CFrontend.2003-08-23-LocalUnionTestqOh (h o}qP(h}h}ubub.(hoqQ}qR(hhhUPASSqSh}h U$Regression.BugPoint.misopt-basictestqTh (h o}qU(h}h}ubub.(hoqV}qW(hhhhh}h U/Regression.Linker.2003-04-26-NullPtrLinkProblemqXh (h o}qY(h}h}ubub.(hoqZ}q[(hhhhh}h U)Regression.Transforms.Reassociate.subtestq\h (h o}q](h}h}ubub.(hoq^}q_(hhhhh}h U)Regression.Linker.2002-08-20-ConstantExprq`h (h o}qa(h}! h}ubub.(hoqb}qc(hhhhh}h U=Regression.Transforms.Reassociate.200 2-05-15-AgressiveSubMoveqdh (h o}qe(h}h}ubub.(hoqf}qg(hhhhh}h UARegression.Transforms.CorrelatedExprs.2002-10-07-DominatorProblemqhh (h o}qi(h}h}ubub.(hoqj}qk(hhhhh}h U3Regression.Transforms.PiNodeInserter.substitutetestqlh (h o}qm(h}h}ubub.(hoqn}qo(hhhhh}h U4Regression.Transforms.SCCP.2003-08-26-InvokeHandlingqph (h o}qq(h}h}ubub.(hoqr}qs(hhhhh}h U-Regression.CFrontend.2002-02-18-64bitConstantqth (h o}qu(h}h}ubub.(hoqv}qw(hhhhh}h U1Regression.Assembler.2002-04-04-PureVirtMethCall2qxh (h o}qy(h}h}ubub.(hoqz}q{(hhhhh}h U(Regression.Reoptimizer.BinInterface.testq|h (h o}q}(h}h}ubub.(hoq~}q(hhhhh}h URegression.Transforms.CorrelatedExprs! .2002-10-08-DominatorTestq?h (h o}q?(h}h}ubub.(hoq?}q?(hhhhh}h URegression.Linker.testlink2q?h (h o}q?(h}h}ubub.(hoq?}q?(hhhhh}h U(Regression.Transforms.GCSE.RLE-Eliminateq?h (h o}q?(h}h}ubub.(hoq?}q?(hhhhh}h U4Regression.C++Frontend.2003-09-30-NestedFunctionDeclq?h (h o}q?(h}h}ubub.(hoq?}q?(hhhhh}h U=Regression.Transforms.CorrelatedExprs.2002-09-23-PHIUpdateBugq?h (h o}q?(h}h}ubub.(hoq?}q?(hhhhh}h U7Regression.Transforms.LowerSwitch.2003-05-01-PHIProblemq?h (h o}q?(h}h}ubub.(hoq?}q?(hhhhh}h U2Regression.Transforms.ADCE.2003-09-15-InfLoopCrashq?h (h o}q?(h}h}ubub.(hoq?}q?(hhhhh}h U*Regression.Transforms.DSAnalysis.recursionq?h (h o}q?(h}h}ubub.(hoq?}q?(hhhhh}h U)Regression.Jello.2003-01-15-AlignmentTestq?h (h o}q?(h}h}ubub.(hoq?}q?(hhhUPASSq?h}h UFeature.mc.simplecalltestq?h (h o}q?(h}h}ubub.(hoq?}q?(hhhhh}h U*Regression.CFrontend.2002-04-07-SwitchStmtq?h (h o}q?(h}h}ubub.(hoq?}q?(hhhhh! }h U!Regression.Jello.2003-01-10-FUCOMq?h (h o}q?(h}h}ubub.(hoq?}q ?(hhhhh}h U(Regression.CFrontend.2003-08-21-StmtExprq?h (h o}q?(h}h}ubub.(hoq?}q?(hhhUPASSq?h}h U*Regression.Transforms.ScalarRepl.basictestq?h (h o}q?(h}h}ubub.(hoq?}q?(hhhh"h}h U6Regression.Transforms.LevelRaise.2002-02-11-ArrayShapeq?h (h o}q?(h}h}ubub.(hoq?}q?(hhhhh}h U1Regression.Assembler.2003-03-03-DuplicateConstantq?h (h o}q?(h}h}ubub.(hoq?}q?(hhhhh}h U.Regression.Transforms.ModuloSched.arith-simpleq?h (h o}q?(h}h}ubub.(hoq?}q?(hhhhh}h U%Regression.Transforms.InstCombine.andq?h (h o}q?(h}h}ubub.(hoq?}q?(hhhhh}h U)Regression.Other.2002-08-02-DomSetProblemq?h (h o}q?(h}h}ubub.(hoq?}q?(hhhhh}h U6Regression.Assembler.2002-07-25-ParserAssertionFailureq?h (h o}q?(h}h}ubub.(hoq?}q?(hhhhh}h U6Regression.Transforms.LevelRaise.2002-03-20-BadCodegenq?h (h o}q?(h}h}ubub.(hoq?}q?(hhhhh}h U%Regression.Transforms.ADCE.basictest1q?h (h o}q?(h}h}ubub.(hoq?}q?(hhhUPASSq?h}h UFeature.mc.recursivetypeq?! h (h o}q?(h}h}ubub.(hoq?}q?(hhhhh}h U$Regression.Transforms.InstCombine.orq?h (h o}q?(h}h}ubub.(hoq?}q?(hhhhh}h U Regression.Verifier.AmbiguousPhiq?h (h o}q?(h}h}ubub.(hoq?}q?(hhhhh}h U'Regression.Analysis.DSGraph.constantizeq?h (h o}q?(h}h}ubub.(hoq?}q?(hhhhh}h U6Regression.Transforms.GlobalDCE.2002-08-17-FunctionDGEq?h (h o}q?(h}h}ubub.(hoq?}q?(hhhhh}h U4Regression.Transforms.SimplifyCFG.2002-06-24-PHINodeq?h (h o}q?(h}h}ubub.(hoq?}q?(hhhhh}h U(Regression.Linker.2003-05-15-TypeProblemq?h (h o}r+++++++++ \ No newline at end of file Index: llvm/test/QMTest/expectations.sunos.qmr diff -u llvm/test/QMTest/expectations.sunos.qmr:1.12 llvm/test/QMTest/expectations.sunos.qmr:1.13 --- llvm/test/QMTest/expectations.sunos.qmr:1.12 Mon Aug 2 10:12:29 2004 +++ llvm/test/QMTest/expectations.sunos.qmr Mon Aug 16 10:10:22 2004 @@ -3,13 +3,13 @@ qoq}q(U _Result__kindqUtestqU_Result__outcomeqUPASSqU_Result__annotationsq}U _Result__idq U0Regression.Assembler.2002-08-16-ConstExprInlinedq U_Result__contextq (cqm.test.context Context -q o}q (U_Context__propertiesq}U_Context__temporariesq}ubub.(hoq}q(hhhhh}h U(Regression.Transforms.PruneEH.simpletestqh (h o}q(h}h}ubub.(hoq}q(hhhhh}h U/Regression.CBackend.2002-08-19-HardConstantExprqh (h o}q(h}h}ubub.(hoq}q(hhhhh}h URegression.Jello.test-shiftqh (h o}q(h}h}ubub.(hoq}q(hhhUFAILqh}h U.Regression.Transforms.CorrelatedExprs.looptestqh (h o}q (h}h}ubub.(hoq!}q"(hhhhh}h U-Regression.Linker.2003-08-23-GlobalVarLinkingq#h (h o}q$(h}h}ubub.(hoq%}q&(hhhhh}h U?Regression.Transforms.Inline.2003-09-22-PHINodesInExceptionDestq'h (h o}q((h}h}ubub.(hoq)}q*(hhhhh}h U,Regression.CFrontend.2003-02-12-NonlocalGotoq+h (h o}q,(h}h}ubub.(hoq-}q.(hhhhh}h U2Regression.Transforms.FunctionResolve.retmismatch1q/h (h o}q0(h}h}ubub.(hoq1}q2(hhhhh}h U8Regression.Transforms.ADCE.2003-01-22-PredecessorProblemq3h (h o}q4(h}h}ubub.(hoq5}q6(hhhhh}h U=Regression.Transforms.LevelRaise.2002-10-08-! VarArgCallInfLoopq7h (h o}q8(h}h}ubub.(hoq9}q:(hhhhh}h U Regression.Reoptimizer.ticm.ticmq;h (h o}q<(h}h}ubub.(hoq=}q>(hhhhh}h U8Regression.C++Frontend.2003-09-29-ArgumentNumberMismatchq?h (h o}q@(h}h}ubub.(hoqA}qB(hhhhh}h U+Regression.CFrontend.2002-09-19-StarInLabelqCh (h o}qD(h}h}ubub.(hoqE}qF(hhhhh}h U.Regression.CFrontend.2003-08-23-LocalUnionTestqGh (h o}qH(h}h}ubub.(hoqI}qJ(hhhhh}h U-Regression.C++Frontend.2003-08-28-SaveExprBugqKh (h o}qL(h}h}ubub.(hoqM}qN(hhhhh}h U"Regression.Jello.2003-06-05-PHIBugqOh (h o}qP(h}h}ubub.(hoqQ}qR(hhhhh}h U/Regression.Linker.2003-04-26-NullPtrLinkProblemqSh (h o}qT(h}h}ubub.(hoqU}qV(hhhhh}h U)Regression.Transforms.Reassociate.subtestqWh (h o}qX(h}h}ubub.(hoqY}qZ(hhhhh}h U)Regression.Linker.2002-08-20-ConstantExprq[h (h o}q\(h}h}ubub.(hoq]}q^(hhhhh}h U=Regression.Transforms.Reassociate.2002-05-15-AgressiveSubMoveq_h (h o}q`(h}h}ubub.(hoqa}qb(hhhhh}h! UARegression.Transforms.CorrelatedExprs.2002-10-07-DominatorProblemqc h (h o}qd(h}h}ubub.(hoqe}qf(hhhhh}h U3Regression.Transforms.PiNodeInserter.substitutetestqgh (h o}qh(h}h}ubub.(hoqi}qj(hhhhh}h U4Regression.Transforms.SCCP.2003-08-26-InvokeHandlingqkh (h o}ql(h}h}ubub.(hoqm}qn(hhhhh}h U$Regression.Jello.2003-01-04-LoopTestqoh (h o}qp(h}h}ubub.(hoqq}qr(hhhhh}h U1Regression.Assembler.2002-04-04-PureVirtMethCall2qsh (h o}qt(h}h}ubub.(hoqu}qv(hhhhh}h U)Regression.CFrontend.2002-07-14-MiscTestsqwh (h o}qx(h}h}ubub.(hoqy}qz(hhhhh}h U(hhhhh}h U Regression.Reoptimizer.ticm.ticmq?h (h o}q@(h}h}ubub.(hoqA}qB(hhhhh}h U8Regression.C++Frontend.2003-09-29-ArgumentNumberMismatchqCh (h o}qD(h}h}ubub.(hoqE}qF(hhhhh}h U+Regression.CFrontend.2002-09-19-StarInLabelqGh (h o}qH(h}h}ubub.(hoqI}qJ(hhhhh}h U.Regression.CFrontend.2003-08-23-LocalUnionTestqKh (h o}qL(h}h}ubub.(hoqM}qN(hhhhh}h U/Regression.Linker.2003-04-26-NullPtrLinkProblemqOh (h o}qP(h}h}ubub.(hoqQ}qR(hhhhh}h U)Regression.Transforms.Reassociate.subtestqSh (h o}qT(h}h}ubub.(hoqU}qV(hhhhh}h U)Regression.Linker.2002-08-20-ConstantExprqWh (h o}qX(h}h}ubub.(hoqY}qZ(hhhhh}h U=Regression.Transforms.Reassociate.2002-05-15-AgressiveSubMoveq[h (h o}q\(h}h}ubub.(hoq]}q^(hhhhh}h UARegression.Transforms.CorrelatedExprs.2002-10-07-DominatorProblemq_! h (h o}q`(h}h}ubub.(hoqa}qb(hhhhh}h U3Regression.Transforms.Pi NodeInserter.substitutetestqch (h o}qd(h}h}ubub.(hoqe}qf(hhhhh}h U4Regression.Transforms.SCCP.2003-08-26-InvokeHandlingqgh (h o}qh(h}h}ubub.(hoqi}qj(hhhhh}h U-Regression.CFrontend.2002-02-18-64bitConstantqkh (h o}ql(h}h}ubub.(hoqm}qn(hhhhh}h U1Regression.Assembler.2002-04-04-PureVirtMethCall2qoh (h o}qp(h}h}ubub.(hoqq}qr(hhhhh}h U(Regression.Reoptimizer.BinInterface.testqsh (h o}qt(h}h}ubub.(hoqu}qv(hhhhh}h U Changes in directory llvm: llvm.spec updated: 1.1 -> 1.2 --- Log message: Updated for 1.3. --- Diffs of the changes: (+1 -1) Index: llvm/llvm.spec diff -u llvm/llvm.spec:1.1 llvm/llvm.spec:1.2 --- llvm/llvm.spec:1.1 Mon Feb 9 21:57:51 2004 +++ llvm/llvm.spec Mon Aug 16 10:17:40 2004 @@ -1,6 +1,6 @@ Summary: Static and JIT research compiler infrastructure Name: llvm -Version: 1.2 +Version: 1.3 Release: 0 License: U of Illinois/NCSA Open Source License Group: Development/Languages From criswell at cs.uiuc.edu Mon Aug 16 10:19:14 2004 From: criswell at cs.uiuc.edu (John Criswell) Date: Mon, 16 Aug 2004 10:19:14 -0500 Subject: [llvm-commits] CVS: llvm/docs/index.html Message-ID: <200408161519.KAA26843@choi.cs.uiuc.edu> Changes in directory llvm/docs: index.html updated: 1.24 -> 1.25 --- Log message: Merged in RELEASE_13. This fixes the Command Guide link when browsing the files from a local filesystem. --- Diffs of the changes: (+3 -3) Index: llvm/docs/index.html diff -u llvm/docs/index.html:1.24 llvm/docs/index.html:1.25 --- llvm/docs/index.html:1.24 Mon Aug 2 16:37:11 2004 +++ llvm/docs/index.html Mon Aug 16 10:19:02 2004 @@ -51,8 +51,8 @@ Everything from unpacking and compilation of the distribution to execution of some tools. -
      • LLVM Command Guide - A reference manual for -the LLVM command line utilities ("man" pages for LLVM tools).
      • +
      • LLVM Command Guide - A reference +manual for the LLVM command line utilities ("man" pages for LLVM tools).
      • Frequently Asked Questions - A list of common questions and problems and their solutions.
      • @@ -195,6 +195,6 @@ src="http://www.w3.org/Icons/valid-html401" alt="Valid HTML 4.01!"> LLVM Compiler Infrastructure
        - Last modified: $Date: 2004/08/02 21:37:11 $ + Last modified: $Date: 2004/08/16 15:19:02 $ From reid at x10sys.com Mon Aug 16 11:48:29 2004 From: reid at x10sys.com (Reid Spencer) Date: Mon, 16 Aug 2004 11:48:29 -0500 Subject: [llvm-commits] CVS: llvm/docs/ReleaseNotes.html Message-ID: <200408161648.LAA08878@zion.cs.uiuc.edu> Changes in directory llvm/docs: ReleaseNotes.html updated: 1.230 -> 1.231 --- Log message: Bug 422: http://llvm.cs.uiuc.edu/PR422 fixed. --- Diffs of the changes: (+3 -1) Index: llvm/docs/ReleaseNotes.html diff -u llvm/docs/ReleaseNotes.html:1.230 llvm/docs/ReleaseNotes.html:1.231 --- llvm/docs/ReleaseNotes.html:1.230 Mon Aug 16 00:46:57 2004 +++ llvm/docs/ReleaseNotes.html Mon Aug 16 11:48:19 2004 @@ -154,6 +154,8 @@

        Bugs fixed in the LLVM Core:

          +
        1. [asmwriter] Asmwriter is really slow for + functions with lots of values
        2. [anders-aa] Andersen's AA is completely broken in LLVM 1.3
        @@ -595,7 +597,7 @@ src="http://www.w3.org/Icons/valid-html401" alt="Valid HTML 4.01!" /> The LLVM Compiler Infrastructure
        - Last modified: $Date: 2004/08/16 05:46:57 $ + Last modified: $Date: 2004/08/16 16:48:19 $ From gaeke at cs.uiuc.edu Mon Aug 16 13:27:37 2004 From: gaeke at cs.uiuc.edu (Brian Gaeke) Date: Mon, 16 Aug 2004 13:27:37 -0500 (CDT) Subject: [llvm-commits] CVS: llvm/lib/CodeGen/MachineFunction.cpp Message-ID: <200408161827.NAA12125@seraph.cs.uiuc.edu> Changes in directory llvm/lib/CodeGen: MachineFunction.cpp updated: 1.68 -> 1.69 --- Log message: Add a note that people shouldn't use MachineFunctionInfo. --- Diffs of the changes: (+2 -0) Index: llvm/lib/CodeGen/MachineFunction.cpp diff -u llvm/lib/CodeGen/MachineFunction.cpp:1.68 llvm/lib/CodeGen/MachineFunction.cpp:1.69 --- llvm/lib/CodeGen/MachineFunction.cpp:1.68 Sun Aug 15 17:02:22 2004 +++ llvm/lib/CodeGen/MachineFunction.cpp Mon Aug 16 13:27:24 2004 @@ -309,6 +309,8 @@ //===----------------------------------------------------------------------===// // MachineFunctionInfo implementation +// NOTE: MachineFunctionInfo and its methods are specific to the SparcV9 +// target - don't use them in other targets. //===----------------------------------------------------------------------===// static unsigned From gaeke at cs.uiuc.edu Mon Aug 16 13:27:37 2004 From: gaeke at cs.uiuc.edu (Brian Gaeke) Date: Mon, 16 Aug 2004 13:27:37 -0500 (CDT) Subject: [llvm-commits] CVS: llvm/lib/Target/SparcV9/SparcV9PrologEpilogInserter.cpp Message-ID: <200408161827.NAA12126@seraph.cs.uiuc.edu> Changes in directory llvm/lib/Target/SparcV9: SparcV9PrologEpilogInserter.cpp updated: 1.44 -> 1.45 --- Log message: Update and consolidate comments. Remove some excess whitespace. --- Diffs of the changes: (+6 -15) Index: llvm/lib/Target/SparcV9/SparcV9PrologEpilogInserter.cpp diff -u llvm/lib/Target/SparcV9/SparcV9PrologEpilogInserter.cpp:1.44 llvm/lib/Target/SparcV9/SparcV9PrologEpilogInserter.cpp:1.45 --- llvm/lib/Target/SparcV9/SparcV9PrologEpilogInserter.cpp:1.44 Thu Aug 12 13:36:28 2004 +++ llvm/lib/Target/SparcV9/SparcV9PrologEpilogInserter.cpp Mon Aug 16 13:27:25 2004 @@ -7,12 +7,12 @@ // //===----------------------------------------------------------------------===// // -// Insert SAVE/RESTORE instructions for the function -// -// Insert prolog code at the unique function entry point. -// Insert epilog code at each function exit point. -// InsertPrologEpilog invokes these only if the function is not compiled -// with the leaf function optimization. +// This is the SparcV9 target's own PrologEpilogInserter. It creates prolog and +// epilog instructions for functions which have not been compiled using "leaf +// function optimizations". These instructions include the SAVE and RESTORE +// instructions used to rotate the SPARC register windows. Prologs are +// attached to the unique function entry, and epilogs are attached to each +// function exit. // //===----------------------------------------------------------------------===// @@ -49,21 +49,14 @@ } // End anonymous namespace -//------------------------------------------------------------------------ -// Create prolog and epilog code for procedure entry and exit -//------------------------------------------------------------------------ - static unsigned getStaticStackSize (MachineFunction &MF) { const TargetFrameInfo& frameInfo = *MF.getTarget().getFrameInfo(); - unsigned staticStackSize = MF.getInfo()->getStaticStackSize(); - if (staticStackSize < (unsigned)SparcV9FrameInfo::MinStackFrameSize) staticStackSize = SparcV9FrameInfo::MinStackFrameSize; if (unsigned padsz = staticStackSize % SparcV9FrameInfo::StackFrameSizeAlignment) staticStackSize += SparcV9FrameInfo::StackFrameSizeAlignment - padsz; - return staticStackSize; } @@ -76,7 +69,6 @@ // The second operand is the stack size. If it does not fit in the // immediate field, we have to use a free register to hold the size. // See the comments below for the choice of this register. - // unsigned staticStackSize = getStaticStackSize (MF); int32_t C = - (int) staticStackSize; int SP = TM.getRegInfo()->getStackPointer(); @@ -119,7 +111,6 @@ // (%i0 ... %i5 if K=6) . // By copying the varargs arguments to the stack, va_arg() then can // simply assume that all vararg arguments are in an array on the stack. - // if (MF.getFunction()->getFunctionType()->isVarArg()) { int numFixedArgs = MF.getFunction()->getFunctionType()->getNumParams(); int numArgRegs = TM.getRegInfo()->getNumOfIntArgRegs(); From brukman at cs.uiuc.edu Mon Aug 16 14:04:47 2004 From: brukman at cs.uiuc.edu (Misha Brukman) Date: Mon, 16 Aug 2004 14:04:47 -0500 Subject: [llvm-commits] CVS: llvm/lib/Support/ConstantRange.cpp Mangler.cpp LeakDetector.cpp Message-ID: <200408161904.OAA00425@zion.cs.uiuc.edu> Changes in directory llvm/lib/Support: ConstantRange.cpp (r1.13) removed Mangler.cpp (r1.13) removed LeakDetector.cpp (r1.10) removed --- Log message: Move these files (which are dependent on VMCore) into VMCore --- Diffs of the changes: (+0 -0) From gaeke at cs.uiuc.edu Mon Aug 16 14:24:27 2004 From: gaeke at cs.uiuc.edu (Brian Gaeke) Date: Mon, 16 Aug 2004 14:24:27 -0500 (CDT) Subject: [llvm-commits] CVS: reopt/test/TEST.reopt.Makefile Message-ID: <200408161924.OAA16050@seraph.cs.uiuc.edu> Changes in directory reopt/test: TEST.reopt.Makefile updated: 1.20 -> 1.21 --- Log message: Copy the SPEC makefile rules from Makefile.spec, and use them instead of our old horrible hack. --- Diffs of the changes: (+5 -2) Index: reopt/test/TEST.reopt.Makefile diff -u reopt/test/TEST.reopt.Makefile:1.20 reopt/test/TEST.reopt.Makefile:1.21 --- reopt/test/TEST.reopt.Makefile:1.20 Thu Aug 5 02:12:50 2004 +++ reopt/test/TEST.reopt.Makefile Mon Aug 16 14:24:16 2004 @@ -91,8 +91,11 @@ $(PROGRAMS_TO_TEST:%=Output/%.out-reopt-llc): \ Output/%.out-reopt-llc: Output/%.reopt-llc @echo "===== Running Reoptimizer version of $(TESTNAME) =====" - -cd Output/llc-train && ../../$< $(RUN_OPTIONS) < $(STDIN_FILENAME) \ - > ../../$@ + $(SPEC_SANDBOX) reopt-llc-$(RUN_TYPE) $@ $(REF_IN_DIR) \ + $(RUNSAFELY) $(STDIN_FILENAME) $(STDOUT_FILENAME) \ + ../../$< $(RUN_OPTIONS) + -(cd Output/reopt-llc-$(RUN_TYPE); cat $(LOCAL_OUTPUTS)) > $@ + -cp Output/reopt-llc-$(RUN_TYPE)/$(STDOUT_FILENAME).time $@.time else $(PROGRAMS_TO_TEST:%=Output/%.out-reopt-llc): \ Output/%.out-reopt-llc: Output/%.reopt-llc From gaeke at cs.uiuc.edu Mon Aug 16 14:24:28 2004 From: gaeke at cs.uiuc.edu (Brian Gaeke) Date: Mon, 16 Aug 2004 14:24:28 -0500 (CDT) Subject: [llvm-commits] CVS: reopt/test/TTFTestHarness.pl Message-ID: <200408161924.OAA16052@seraph.cs.uiuc.edu> Changes in directory reopt/test: TTFTestHarness.pl updated: 1.2 -> 1.3 --- Log message: ttftest default location has moved. --- Diffs of the changes: (+1 -1) Index: reopt/test/TTFTestHarness.pl diff -u reopt/test/TTFTestHarness.pl:1.2 reopt/test/TTFTestHarness.pl:1.3 --- reopt/test/TTFTestHarness.pl:1.2 Wed Aug 4 00:28:04 2004 +++ reopt/test/TTFTestHarness.pl Mon Aug 16 14:24:17 2004 @@ -1,7 +1,7 @@ #!/usr/bin/perl print "looking for ttftest\n"; -if ( -x "../Debug/ttftest" ) { $TTFTEST = "../Debug/ttftest"; } +if ( -x "../../tools/Debug/ttftest" ) { $TTFTEST = "../../tools/Debug/ttftest"; } else { print "looking in path dirs\n"; foreach my $dir ( split ( /:/, $ENV{'PATH'} ) ) { From gaeke at cs.uiuc.edu Mon Aug 16 14:24:28 2004 From: gaeke at cs.uiuc.edu (Brian Gaeke) Date: Mon, 16 Aug 2004 14:24:28 -0500 (CDT) Subject: [llvm-commits] CVS: reopt/test/run-tests Message-ID: <200408161924.OAA16060@seraph.cs.uiuc.edu> Changes in directory reopt/test: run-tests updated: 1.17 -> 1.18 --- Log message: Remove directories with 'reopt' in their name, too. Disable LLVM_REOPT debug options when running SPEC tests, b/c Sandbox.sh doesn't like them. --- Diffs of the changes: (+5 -2) Index: reopt/test/run-tests diff -u reopt/test/run-tests:1.17 reopt/test/run-tests:1.18 --- reopt/test/run-tests:1.17 Wed Aug 4 00:28:05 2004 +++ reopt/test/run-tests Mon Aug 16 14:24:18 2004 @@ -118,7 +118,7 @@ find $fullsubdirpath -name "*.out-llc" -print |xargs rm find $fullsubdirpath -name "*.out-reopt-llc" -print |xargs rm if [ $outputonly -eq 0 ]; then - find $fullsubdirpath -name "*reopt*" -print |xargs rm + find $fullsubdirpath -name "*reopt*" -print |xargs rm -rf fi } @@ -128,7 +128,10 @@ export LLVM_REOPT fi if [ $spectest -eq 1 ]; then - exec gmake SUBDIR=$SUBDIR SPECTEST=1 + # note: SPEC Sandbox.sh does NOT play nice with our debug output! + LLVM_REOPT='--enable-trace-opt' + export LLVM_REOPT + exec gmake SUBDIR=$SUBDIR SPECTEST=1 RUNTIMELIMIT=900 else exec gmake SUBDIR=$SUBDIR fi From reid at x10sys.com Mon Aug 16 14:24:46 2004 From: reid at x10sys.com (Reid Spencer) Date: Mon, 16 Aug 2004 14:24:46 -0500 Subject: [llvm-commits] CVS: llvm/docs/BytecodeFormat.html Message-ID: <200408161924.OAA10248@zion.cs.uiuc.edu> Changes in directory llvm/docs: BytecodeFormat.html updated: 1.24 -> 1.25 --- Log message: Correct the documentation for the module block header which uses the long format instead of the short format used in other blocks. Discrepancy noted by Robert Mykland. Thanks Robert! --- Diffs of the changes: (+23 -5) Index: llvm/docs/BytecodeFormat.html diff -u llvm/docs/BytecodeFormat.html:1.24 llvm/docs/BytecodeFormat.html:1.25 --- llvm/docs/BytecodeFormat.html:1.24 Tue Aug 3 15:57:56 2004 +++ llvm/docs/BytecodeFormat.html Mon Aug 16 14:24:36 2004 @@ -614,10 +614,13 @@ Field Description - block
        - - Module Block Identifier (0x01) and Size
        - + unsigned
        + Module Block Identifier + (0x01) + + + unsigned + Module Block Size uint32_vbr @@ -646,6 +649,21 @@ + + + +
        +

        The block header for the module block uses a longer format than the other + blocks in a bytecode file. Specifically, instead of encoding the type and size + of the block into a 32-bit integer with 5-bits for type and 27-bits for size, + the module block header uses two 32-bit unsigned values, one for type, and one + for size. While the 227 byte limit on block size is sufficient for the blocks + contained in the module, it isn't sufficient for the module block itself + because we want to ensure that bytecode files as large as 232 bytes + are possible. For this reason, the module block (and only the module block) + uses a long format header.

        +
        +
        @@ -1630,7 +1648,7 @@ Reid Spencer and Chris Lattner
        The LLVM Compiler Infrastructure
        -Last modified: $Date: 2004/08/03 20:57:56 $ +Last modified: $Date: 2004/08/16 19:24:36 $ From lattner at cs.uiuc.edu Mon Aug 16 15:20:59 2004 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Mon, 16 Aug 2004 15:20:59 -0500 Subject: [llvm-commits] CVS: llvm/docs/ReleaseNotes.html Message-ID: <200408162020.PAA12897@apoc.cs.uiuc.edu> Changes in directory llvm/docs: ReleaseNotes.html updated: 1.231 -> 1.232 --- Log message: Spaces arg! --- Diffs of the changes: (+4 -2) Index: llvm/docs/ReleaseNotes.html diff -u llvm/docs/ReleaseNotes.html:1.231 llvm/docs/ReleaseNotes.html:1.232 --- llvm/docs/ReleaseNotes.html:1.231 Mon Aug 16 11:48:19 2004 +++ llvm/docs/ReleaseNotes.html Mon Aug 16 15:20:46 2004 @@ -198,7 +198,9 @@ LLVM and the C frontend out of a top-level directory without spaces (e.g., /cygdrive/c/llvm). Also, make sure to install all of the cygwin packages. By default, many important tools are not installed that -are needed by the LLVM build process or test suite (e.g., /bin/time).

        +are needed by the LLVM build process or test suite (e.g., /bin/time). Finally, +please make sure that there are no directories with spaces in them in your +PATH environment variable.

        @@ -597,7 +599,7 @@ src="http://www.w3.org/Icons/valid-html401" alt="Valid HTML 4.01!" /> The LLVM Compiler Infrastructure
        - Last modified: $Date: 2004/08/16 16:48:19 $ + Last modified: $Date: 2004/08/16 20:20:46 $ From lattner at cs.uiuc.edu Mon Aug 16 15:21:28 2004 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Mon, 16 Aug 2004 15:21:28 -0500 Subject: [llvm-commits] CVS: llvm-www/releases/1.3/docs/ReleaseNotes.html Message-ID: <200408162021.PAA12918@apoc.cs.uiuc.edu> Changes in directory llvm-www/releases/1.3/docs: ReleaseNotes.html updated: 1.2 -> 1.3 --- Log message: Spaces in PATH doesn't work --- Diffs of the changes: (+4 -2) Index: llvm-www/releases/1.3/docs/ReleaseNotes.html diff -u llvm-www/releases/1.3/docs/ReleaseNotes.html:1.2 llvm-www/releases/1.3/docs/ReleaseNotes.html:1.3 --- llvm-www/releases/1.3/docs/ReleaseNotes.html:1.2 Mon Aug 16 00:49:24 2004 +++ llvm-www/releases/1.3/docs/ReleaseNotes.html Mon Aug 16 15:21:17 2004 @@ -369,7 +369,9 @@ LLVM and the C frontend out of a top-level directory without spaces (e.g., /cygdrive/c/llvm). Also, make sure to install all of the cygwin packages. By default, many important tools are not installed that -are needed by the LLVM build process or test suite (e.g., /bin/time).

        +are needed by the LLVM build process or test suite (e.g., /bin/time). Finally, +please make sure that there are no directories with spaces in them in your +PATH environment variable.

        @@ -771,7 +773,7 @@ src="http://www.w3.org/Icons/valid-html401" alt="Valid HTML 4.01!" /> The LLVM Compiler Infrastructure
        - Last modified: $Date: 2004/08/16 05:49:24 $ + Last modified: $Date: 2004/08/16 20:21:17 $ From lattner at cs.uiuc.edu Mon Aug 16 16:36:43 2004 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Mon, 16 Aug 2004 16:36:43 -0500 Subject: [llvm-commits] CVS: llvm/lib/CodeGen/MachineCodeForInstruction.cpp Message-ID: <200408162136.QAA26575@apoc.cs.uiuc.edu> Changes in directory llvm/lib/CodeGen: MachineCodeForInstruction.cpp updated: 1.17 -> 1.18 --- Log message: Fold MachineInstrAnnot.cpp into this file --- Diffs of the changes: (+56 -0) Index: llvm/lib/CodeGen/MachineCodeForInstruction.cpp diff -u llvm/lib/CodeGen/MachineCodeForInstruction.cpp:1.17 llvm/lib/CodeGen/MachineCodeForInstruction.cpp:1.18 --- llvm/lib/CodeGen/MachineCodeForInstruction.cpp:1.17 Sun Jun 27 13:52:17 2004 +++ llvm/lib/CodeGen/MachineCodeForInstruction.cpp Mon Aug 16 16:36:31 2004 @@ -24,10 +24,13 @@ #include "llvm/CodeGen/MachineCodeForInstruction.h" #include "llvm/Function.h" +#include "llvm/Instructions.h" +#include "llvm/Type.h" #include "llvm/CodeGen/MachineInstr.h" #include "llvm/CodeGen/MachineFunction.h" #include "llvm/CodeGen/MachineFunctionInfo.h" #include "../Target/SparcV9/MachineInstrAnnot.h" +#include "../Target/SparcV9/SparcV9TmpInstr.h" using namespace llvm; MachineCodeForInstruction &MachineCodeForInstruction::get(const Instruction *I){ @@ -61,3 +64,56 @@ // Free the CallArgsDescriptor if it exists. delete callArgsDesc; } + + +CallArgsDescriptor::CallArgsDescriptor(CallInst* _callInstr, + TmpInstruction* _retAddrReg, + bool _isVarArgs, bool _noPrototype) + : callInstr(_callInstr), + funcPtr(isa(_callInstr->getCalledValue()) + ? NULL : _callInstr->getCalledValue()), + retAddrReg(_retAddrReg), + isVarArgs(_isVarArgs), + noPrototype(_noPrototype) { + unsigned int numArgs = callInstr->getNumOperands(); + argInfoVec.reserve(numArgs); + assert(callInstr->getOperand(0) == callInstr->getCalledValue() + && "Operand 0 is ignored in the loop below!"); + for (unsigned int i=1; i < numArgs; ++i) + argInfoVec.push_back(CallArgInfo(callInstr->getOperand(i))); + + // Enter this object in the MachineCodeForInstr object of the CallInst. + // This transfers ownership of this object. + MachineCodeForInstruction::get(callInstr).setCallArgsDescriptor(this); +} + +CallInst *CallArgsDescriptor::getReturnValue() const { + return (callInstr->getType() == Type::VoidTy? NULL : callInstr); +} + +// Mechanism to get the descriptor for a CALL MachineInstr. +// We get the LLVM CallInstr from the ret. addr. register argument +// of the CALL MachineInstr (which is explicit operand #3 for indirect +// calls or the last implicit operand for direct calls). We then get +// the CallArgsDescriptor from the MachineCodeForInstruction object for +// the CallInstr. +// This is roundabout but avoids adding a new map or annotation just +// to keep track of CallArgsDescriptors. +// +CallArgsDescriptor *CallArgsDescriptor::get(const MachineInstr* MI) { + const TmpInstruction* retAddrReg = + cast(isa(MI->getOperand(0).getVRegValue()) + ? MI->getImplicitRef(MI->getNumImplicitRefs()-1) + : MI->getOperand(2).getVRegValue()); + + assert(retAddrReg->getNumOperands() == 1 && + isa(retAddrReg->getOperand(0)) && + "Location of callInstr arg for CALL instr. changed? FIX THIS CODE!"); + + const CallInst* callInstr = cast(retAddrReg->getOperand(0)); + + CallArgsDescriptor* desc = + MachineCodeForInstruction::get(callInstr).getCallArgsDescriptor(); + assert(desc->getCallInst()==callInstr && "Incorrect call args descriptor?"); + return desc; +} From lattner at cs.uiuc.edu Mon Aug 16 16:36:51 2004 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Mon, 16 Aug 2004 16:36:51 -0500 Subject: [llvm-commits] CVS: llvm/lib/CodeGen/MachineInstrAnnot.cpp Message-ID: <200408162136.QAA26579@apoc.cs.uiuc.edu> Changes in directory llvm/lib/CodeGen: MachineInstrAnnot.cpp (r1.14) removed --- Log message: Nuke this file --- Diffs of the changes: (+0 -0) From lattner at cs.uiuc.edu Mon Aug 16 16:54:43 2004 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Mon, 16 Aug 2004 16:54:43 -0500 Subject: [llvm-commits] CVS: llvm/lib/Target/SparcV9/MachineCodeForInstruction.h MachineFunctionInfo.h MappingInfo.cpp SparcV9AsmPrinter.cpp SparcV9BurgISel.cpp SparcV9CodeEmitter.cpp SparcV9FrameInfo.cpp SparcV9PrologEpilogInserter.cpp SparcV9RegInfo.cpp SparcV9StackSlots.cpp SparcV9TargetMachine.cpp SparcV9TmpInstr.h Message-ID: <200408162154.QAA02468@apoc.cs.uiuc.edu> Changes in directory llvm/lib/Target/SparcV9: MachineCodeForInstruction.h updated: 1.15 -> 1.16 MachineFunctionInfo.h updated: 1.5 -> 1.6 MappingInfo.cpp updated: 1.17 -> 1.18 SparcV9AsmPrinter.cpp updated: 1.117 -> 1.118 SparcV9BurgISel.cpp updated: 1.5 -> 1.6 SparcV9CodeEmitter.cpp updated: 1.69 -> 1.70 SparcV9FrameInfo.cpp updated: 1.5 -> 1.6 SparcV9PrologEpilogInserter.cpp updated: 1.45 -> 1.46 SparcV9RegInfo.cpp updated: 1.134 -> 1.135 SparcV9StackSlots.cpp updated: 1.11 -> 1.12 SparcV9TargetMachine.cpp updated: 1.119 -> 1.120 SparcV9TmpInstr.h updated: 1.1 -> 1.2 --- Log message: Move MachineCodeForInstruction.h and MachineFunctionInfo.h into lib/Target/SparcV9 --- Diffs of the changes: (+22 -25) Index: llvm/lib/Target/SparcV9/MachineCodeForInstruction.h diff -u llvm/lib/Target/SparcV9/MachineCodeForInstruction.h:1.15 llvm/lib/Target/SparcV9/MachineCodeForInstruction.h:1.16 --- llvm/lib/Target/SparcV9/MachineCodeForInstruction.h:1.15 Sun Jun 27 13:50:49 2004 +++ llvm/lib/Target/SparcV9/MachineCodeForInstruction.h Mon Aug 16 16:54:29 2004 @@ -1,4 +1,4 @@ -//===-- llvm/CodeGen/MachineCodeForInstruction.h ----------------*- C++ -*-===// +//===-- MachineCodeForInstruction.h -----------------------------*- C++ -*-===// // // The LLVM Compiler Infrastructure // @@ -25,8 +25,8 @@ // //===----------------------------------------------------------------------===// -#ifndef LLVM_CODEGEN_MACHINECODE_FOR_INSTRUCTION_H -#define LLVM_CODEGEN_MACHINECODE_FOR_INSTRUCTION_H +#ifndef MACHINECODE_FOR_INSTRUCTION_H +#define MACHINECODE_FOR_INSTRUCTION_H #include Index: llvm/lib/Target/SparcV9/MachineFunctionInfo.h diff -u llvm/lib/Target/SparcV9/MachineFunctionInfo.h:1.5 llvm/lib/Target/SparcV9/MachineFunctionInfo.h:1.6 --- llvm/lib/Target/SparcV9/MachineFunctionInfo.h:1.5 Sun Jun 27 13:50:30 2004 +++ llvm/lib/Target/SparcV9/MachineFunctionInfo.h Mon Aug 16 16:54:29 2004 @@ -1,4 +1,4 @@ -//===-- llvm/CodeGen/MachineFunctionInfo.h ----------------------*- C++ -*-===// +//===-- MachineFunctionInfo.h -----------------------------------*- C++ -*-===// // // The LLVM Compiler Infrastructure // @@ -15,10 +15,10 @@ // //===----------------------------------------------------------------------===// -#ifndef LLVM_CODEGEN_MACHINEFUNCTIONINFO_H -#define LLVM_CODEGEN_MACHINEFUNCTIONINFO_H +#ifndef MACHINEFUNCTIONINFO_H +#define MACHINEFUNCTIONINFO_H -#include "llvm/CodeGen/MachineCodeForInstruction.h" +#include "MachineCodeForInstruction.h" #include "Support/HashExtras.h" #include "Support/hash_set" Index: llvm/lib/Target/SparcV9/MappingInfo.cpp diff -u llvm/lib/Target/SparcV9/MappingInfo.cpp:1.17 llvm/lib/Target/SparcV9/MappingInfo.cpp:1.18 --- llvm/lib/Target/SparcV9/MappingInfo.cpp:1.17 Sun Apr 25 02:04:49 2004 +++ llvm/lib/Target/SparcV9/MappingInfo.cpp Mon Aug 16 16:54:29 2004 @@ -46,7 +46,7 @@ #include "llvm/Pass.h" #include "llvm/Module.h" #include "llvm/CodeGen/MachineFunction.h" -#include "llvm/CodeGen/MachineCodeForInstruction.h" +#include "MachineCodeForInstruction.h" #include "Support/StringExtras.h" namespace llvm { Index: llvm/lib/Target/SparcV9/SparcV9AsmPrinter.cpp diff -u llvm/lib/Target/SparcV9/SparcV9AsmPrinter.cpp:1.117 llvm/lib/Target/SparcV9/SparcV9AsmPrinter.cpp:1.118 --- llvm/lib/Target/SparcV9/SparcV9AsmPrinter.cpp:1.117 Wed Aug 4 03:44:43 2004 +++ llvm/lib/Target/SparcV9/SparcV9AsmPrinter.cpp Mon Aug 16 16:54:29 2004 @@ -25,12 +25,12 @@ #include "llvm/Assembly/Writer.h" #include "llvm/CodeGen/MachineConstantPool.h" #include "llvm/CodeGen/MachineFunction.h" -#include "llvm/CodeGen/MachineFunctionInfo.h" #include "llvm/CodeGen/MachineInstr.h" #include "llvm/Support/Mangler.h" #include "Support/StringExtras.h" #include "Support/Statistic.h" #include "SparcV9Internals.h" +#include "MachineFunctionInfo.h" #include using namespace llvm; Index: llvm/lib/Target/SparcV9/SparcV9BurgISel.cpp diff -u llvm/lib/Target/SparcV9/SparcV9BurgISel.cpp:1.5 llvm/lib/Target/SparcV9/SparcV9BurgISel.cpp:1.6 --- llvm/lib/Target/SparcV9/SparcV9BurgISel.cpp:1.5 Thu Aug 12 13:29:05 2004 +++ llvm/lib/Target/SparcV9/SparcV9BurgISel.cpp Mon Aug 16 16:54:30 2004 @@ -21,15 +21,14 @@ #include "SparcV9TmpInstr.h" #include "SparcV9FrameInfo.h" #include "SparcV9RegisterInfo.h" +#include "MachineFunctionInfo.h" #include "llvm/CodeGen/IntrinsicLowering.h" #include "llvm/CodeGen/MachineConstantPool.h" #include "llvm/CodeGen/MachineFunction.h" -#include "llvm/CodeGen/MachineFunctionInfo.h" #include "llvm/CodeGen/MachineInstr.h" #include "llvm/CodeGen/MachineInstrBuilder.h" #include "llvm/Constants.h" #include "llvm/DerivedTypes.h" -#include "llvm/GlobalValue.h" #include "llvm/Instructions.h" #include "llvm/Intrinsics.h" #include "llvm/Module.h" Index: llvm/lib/Target/SparcV9/SparcV9CodeEmitter.cpp diff -u llvm/lib/Target/SparcV9/SparcV9CodeEmitter.cpp:1.69 llvm/lib/Target/SparcV9/SparcV9CodeEmitter.cpp:1.70 --- llvm/lib/Target/SparcV9/SparcV9CodeEmitter.cpp:1.69 Wed Aug 4 16:48:00 2004 +++ llvm/lib/Target/SparcV9/SparcV9CodeEmitter.cpp Mon Aug 16 16:54:30 2004 @@ -26,7 +26,6 @@ #include "llvm/PassManager.h" #include "llvm/CodeGen/MachineCodeEmitter.h" #include "llvm/CodeGen/MachineConstantPool.h" -#include "llvm/CodeGen/MachineFunctionInfo.h" #include "llvm/CodeGen/MachineFunctionPass.h" #include "llvm/CodeGen/MachineInstr.h" #include "llvm/Target/TargetMachine.h" @@ -38,6 +37,7 @@ #include "SparcV9TargetMachine.h" #include "SparcV9RegInfo.h" #include "SparcV9CodeEmitter.h" +#include "MachineFunctionInfo.h" #include "Config/alloca.h" namespace llvm { Index: llvm/lib/Target/SparcV9/SparcV9FrameInfo.cpp diff -u llvm/lib/Target/SparcV9/SparcV9FrameInfo.cpp:1.5 llvm/lib/Target/SparcV9/SparcV9FrameInfo.cpp:1.6 --- llvm/lib/Target/SparcV9/SparcV9FrameInfo.cpp:1.5 Thu Aug 12 13:36:53 2004 +++ llvm/lib/Target/SparcV9/SparcV9FrameInfo.cpp Mon Aug 16 16:54:30 2004 @@ -12,8 +12,8 @@ //===----------------------------------------------------------------------===// #include "llvm/CodeGen/MachineFunction.h" -#include "llvm/CodeGen/MachineFunctionInfo.h" #include "llvm/Target/TargetFrameInfo.h" +#include "MachineFunctionInfo.h" #include "SparcV9FrameInfo.h" using namespace llvm; Index: llvm/lib/Target/SparcV9/SparcV9PrologEpilogInserter.cpp diff -u llvm/lib/Target/SparcV9/SparcV9PrologEpilogInserter.cpp:1.45 llvm/lib/Target/SparcV9/SparcV9PrologEpilogInserter.cpp:1.46 --- llvm/lib/Target/SparcV9/SparcV9PrologEpilogInserter.cpp:1.45 Mon Aug 16 13:27:25 2004 +++ llvm/lib/Target/SparcV9/SparcV9PrologEpilogInserter.cpp Mon Aug 16 16:54:30 2004 @@ -20,9 +20,9 @@ #include "SparcV9RegClassInfo.h" #include "SparcV9RegisterInfo.h" #include "SparcV9FrameInfo.h" +#include "MachineFunctionInfo.h" +#include "MachineCodeForInstruction.h" #include "llvm/CodeGen/MachineFunctionPass.h" -#include "llvm/CodeGen/MachineFunctionInfo.h" -#include "llvm/CodeGen/MachineCodeForInstruction.h" #include "llvm/CodeGen/MachineInstrBuilder.h" #include "llvm/Pass.h" #include "llvm/Function.h" Index: llvm/lib/Target/SparcV9/SparcV9RegInfo.cpp diff -u llvm/lib/Target/SparcV9/SparcV9RegInfo.cpp:1.134 llvm/lib/Target/SparcV9/SparcV9RegInfo.cpp:1.135 --- llvm/lib/Target/SparcV9/SparcV9RegInfo.cpp:1.134 Thu Aug 12 13:29:05 2004 +++ llvm/lib/Target/SparcV9/SparcV9RegInfo.cpp Mon Aug 16 16:54:30 2004 @@ -13,9 +13,9 @@ //===----------------------------------------------------------------------===// #include "llvm/CodeGen/MachineFunction.h" -#include "llvm/CodeGen/MachineFunctionInfo.h" #include "llvm/CodeGen/MachineInstrBuilder.h" -#include "llvm/CodeGen/MachineCodeForInstruction.h" +#include "MachineFunctionInfo.h" +#include "MachineCodeForInstruction.h" #include "MachineInstrAnnot.h" #include "RegAlloc/LiveRangeInfo.h" #include "RegAlloc/LiveRange.h" Index: llvm/lib/Target/SparcV9/SparcV9StackSlots.cpp diff -u llvm/lib/Target/SparcV9/SparcV9StackSlots.cpp:1.11 llvm/lib/Target/SparcV9/SparcV9StackSlots.cpp:1.12 --- llvm/lib/Target/SparcV9/SparcV9StackSlots.cpp:1.11 Sun Apr 25 02:04:49 2004 +++ llvm/lib/Target/SparcV9/SparcV9StackSlots.cpp Mon Aug 16 16:54:30 2004 @@ -17,10 +17,9 @@ #include "llvm/Constant.h" #include "llvm/DerivedTypes.h" #include "llvm/Function.h" -#include "llvm/CodeGen/MachineFunctionInfo.h" #include "llvm/CodeGen/MachineFunctionPass.h" - -namespace llvm { +#include "MachineFunctionInfo.h" +using namespace llvm; namespace { class StackSlots : public MachineFunctionPass { @@ -47,8 +46,7 @@ }; } -Pass *createStackSlotsPass(const TargetMachine &Target) { +Pass *llvm::createStackSlotsPass(const TargetMachine &Target) { return new StackSlots(Target); } -} // End llvm namespace Index: llvm/lib/Target/SparcV9/SparcV9TargetMachine.cpp diff -u llvm/lib/Target/SparcV9/SparcV9TargetMachine.cpp:1.119 llvm/lib/Target/SparcV9/SparcV9TargetMachine.cpp:1.120 --- llvm/lib/Target/SparcV9/SparcV9TargetMachine.cpp:1.119 Wed Aug 4 02:30:04 2004 +++ llvm/lib/Target/SparcV9/SparcV9TargetMachine.cpp Mon Aug 16 16:54:30 2004 @@ -19,13 +19,13 @@ #include "llvm/CodeGen/InstrScheduling.h" #include "llvm/CodeGen/IntrinsicLowering.h" #include "llvm/CodeGen/MachineFunction.h" -#include "llvm/CodeGen/MachineFunctionInfo.h" -#include "llvm/CodeGen/MachineCodeForInstruction.h" #include "llvm/CodeGen/Passes.h" #include "llvm/Target/TargetOptions.h" #include "llvm/Target/TargetMachineRegistry.h" #include "llvm/Transforms/Scalar.h" #include "MappingInfo.h" +#include "MachineFunctionInfo.h" +#include "MachineCodeForInstruction.h" #include "SparcV9Internals.h" #include "SparcV9TargetMachine.h" #include "SparcV9BurgISel.h" Index: llvm/lib/Target/SparcV9/SparcV9TmpInstr.h diff -u llvm/lib/Target/SparcV9/SparcV9TmpInstr.h:1.1 llvm/lib/Target/SparcV9/SparcV9TmpInstr.h:1.2 --- llvm/lib/Target/SparcV9/SparcV9TmpInstr.h:1.1 Wed Aug 4 02:29:04 2004 +++ llvm/lib/Target/SparcV9/SparcV9TmpInstr.h Mon Aug 16 16:54:30 2004 @@ -16,7 +16,7 @@ #define SPARCV9TMPINSTR_H #include "llvm/Instruction.h" -#include "llvm/CodeGen/MachineCodeForInstruction.h" +#include "MachineCodeForInstruction.h" namespace llvm { From lattner at cs.uiuc.edu Mon Aug 16 16:54:43 2004 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Mon, 16 Aug 2004 16:54:43 -0500 Subject: [llvm-commits] CVS: llvm/lib/Target/SparcV9/RegAlloc/PhyRegAlloc.cpp Message-ID: <200408162154.QAA02471@apoc.cs.uiuc.edu> Changes in directory llvm/lib/Target/SparcV9/RegAlloc: PhyRegAlloc.cpp updated: 1.159 -> 1.160 --- Log message: Move MachineCodeForInstruction.h and MachineFunctionInfo.h into lib/Target/SparcV9 --- Diffs of the changes: (+2 -2) Index: llvm/lib/Target/SparcV9/RegAlloc/PhyRegAlloc.cpp diff -u llvm/lib/Target/SparcV9/RegAlloc/PhyRegAlloc.cpp:1.159 llvm/lib/Target/SparcV9/RegAlloc/PhyRegAlloc.cpp:1.160 --- llvm/lib/Target/SparcV9/RegAlloc/PhyRegAlloc.cpp:1.159 Fri Aug 6 14:11:42 2004 +++ llvm/lib/Target/SparcV9/RegAlloc/PhyRegAlloc.cpp Mon Aug 16 16:54:32 2004 @@ -26,6 +26,8 @@ #include "RegAllocCommon.h" #include "RegClass.h" #include "../LiveVar/FunctionLiveVarInfo.h" +#include "../MachineCodeForInstruction.h" +#include "../MachineFunctionInfo.h" #include "../SparcV9InstrInfo.h" #include "../SparcV9TmpInstr.h" #include "llvm/Constants.h" @@ -34,9 +36,7 @@ #include "llvm/Module.h" #include "llvm/Type.h" #include "llvm/Analysis/LoopInfo.h" -#include "llvm/CodeGen/MachineCodeForInstruction.h" #include "llvm/CodeGen/MachineFunction.h" -#include "llvm/CodeGen/MachineFunctionInfo.h" #include "llvm/CodeGen/MachineInstr.h" #include "llvm/CodeGen/MachineInstrBuilder.h" #include "../MachineInstrAnnot.h" From lattner at cs.uiuc.edu Mon Aug 16 16:55:10 2004 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Mon, 16 Aug 2004 16:55:10 -0500 Subject: [llvm-commits] CVS: llvm/lib/CodeGen/MachineCodeForInstruction.cpp MachineFunction.cpp Message-ID: <200408162155.QAA02493@apoc.cs.uiuc.edu> Changes in directory llvm/lib/CodeGen: MachineCodeForInstruction.cpp updated: 1.18 -> 1.19 MachineFunction.cpp updated: 1.69 -> 1.70 --- Log message: Move MachineCodeForInstruction.h and MachineFunctionInfo.h into lib/Target/SparcV9 --- Diffs of the changes: (+3 -3) Index: llvm/lib/CodeGen/MachineCodeForInstruction.cpp diff -u llvm/lib/CodeGen/MachineCodeForInstruction.cpp:1.18 llvm/lib/CodeGen/MachineCodeForInstruction.cpp:1.19 --- llvm/lib/CodeGen/MachineCodeForInstruction.cpp:1.18 Mon Aug 16 16:36:31 2004 +++ llvm/lib/CodeGen/MachineCodeForInstruction.cpp Mon Aug 16 16:54:59 2004 @@ -22,13 +22,13 @@ // //===----------------------------------------------------------------------===// -#include "llvm/CodeGen/MachineCodeForInstruction.h" +#include "../Target/SparcV9/MachineCodeForInstruction.h" #include "llvm/Function.h" #include "llvm/Instructions.h" #include "llvm/Type.h" #include "llvm/CodeGen/MachineInstr.h" #include "llvm/CodeGen/MachineFunction.h" -#include "llvm/CodeGen/MachineFunctionInfo.h" +#include "../Target/SparcV9/MachineFunctionInfo.h" #include "../Target/SparcV9/MachineInstrAnnot.h" #include "../Target/SparcV9/SparcV9TmpInstr.h" using namespace llvm; Index: llvm/lib/CodeGen/MachineFunction.cpp diff -u llvm/lib/CodeGen/MachineFunction.cpp:1.69 llvm/lib/CodeGen/MachineFunction.cpp:1.70 --- llvm/lib/CodeGen/MachineFunction.cpp:1.69 Mon Aug 16 13:27:24 2004 +++ llvm/lib/CodeGen/MachineFunction.cpp Mon Aug 16 16:54:59 2004 @@ -16,7 +16,6 @@ #include "llvm/CodeGen/MachineFunctionPass.h" #include "llvm/CodeGen/MachineInstr.h" #include "llvm/CodeGen/SSARegMap.h" -#include "llvm/CodeGen/MachineFunctionInfo.h" #include "llvm/CodeGen/MachineFrameInfo.h" #include "llvm/CodeGen/MachineConstantPool.h" #include "llvm/CodeGen/Passes.h" @@ -25,6 +24,7 @@ #include "llvm/Function.h" #include "llvm/Instructions.h" #include "llvm/Type.h" +#include "../Target/SparcV9/MachineFunctionInfo.h" // FIXME #include "Support/LeakDetector.h" #include "Support/GraphWriter.h" #include From lattner at cs.uiuc.edu Mon Aug 16 16:55:12 2004 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Mon, 16 Aug 2004 16:55:12 -0500 Subject: [llvm-commits] CVS: llvm/lib/CodeGen/InstrSched/InstrScheduling.cpp SchedGraph.cpp Message-ID: <200408162155.QAA02501@apoc.cs.uiuc.edu> Changes in directory llvm/lib/CodeGen/InstrSched: InstrScheduling.cpp updated: 1.75 -> 1.76 SchedGraph.cpp updated: 1.64 -> 1.65 --- Log message: Move MachineCodeForInstruction.h and MachineFunctionInfo.h into lib/Target/SparcV9 --- Diffs of the changes: (+4 -4) Index: llvm/lib/CodeGen/InstrSched/InstrScheduling.cpp diff -u llvm/lib/CodeGen/InstrSched/InstrScheduling.cpp:1.75 llvm/lib/CodeGen/InstrSched/InstrScheduling.cpp:1.76 --- llvm/lib/CodeGen/InstrSched/InstrScheduling.cpp:1.75 Thu Jul 29 16:31:20 2004 +++ llvm/lib/CodeGen/InstrSched/InstrScheduling.cpp Mon Aug 16 16:55:01 2004 @@ -13,12 +13,12 @@ //===----------------------------------------------------------------------===// #include "SchedPriorities.h" +#include "llvm/BasicBlock.h" #include "llvm/CodeGen/MachineInstr.h" -#include "llvm/CodeGen/MachineCodeForInstruction.h" #include "llvm/CodeGen/MachineFunction.h" -#include "../../Target/SparcV9/LiveVar/FunctionLiveVarInfo.h" #include "llvm/Target/TargetMachine.h" -#include "llvm/BasicBlock.h" +#include "../../Target/SparcV9/MachineCodeForInstruction.h" +#include "../../Target/SparcV9/LiveVar/FunctionLiveVarInfo.h" #include "Support/CommandLine.h" #include #include Index: llvm/lib/CodeGen/InstrSched/SchedGraph.cpp diff -u llvm/lib/CodeGen/InstrSched/SchedGraph.cpp:1.64 llvm/lib/CodeGen/InstrSched/SchedGraph.cpp:1.65 --- llvm/lib/CodeGen/InstrSched/SchedGraph.cpp:1.64 Thu Jul 29 12:06:44 2004 +++ llvm/lib/CodeGen/InstrSched/SchedGraph.cpp Mon Aug 16 16:55:01 2004 @@ -16,10 +16,10 @@ #include "SchedGraph.h" #include "llvm/Function.h" #include "llvm/Instructions.h" -#include "llvm/CodeGen/MachineCodeForInstruction.h" #include "llvm/CodeGen/MachineFunction.h" #include "llvm/Target/TargetInstrInfo.h" #include "llvm/Target/TargetMachine.h" +#include "../../Target/SparcV9/MachineCodeForInstruction.h" #include "../../Target/SparcV9/SparcV9RegInfo.h" #include "Support/STLExtras.h" #include From lattner at cs.uiuc.edu Mon Aug 16 16:55:13 2004 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Mon, 16 Aug 2004 16:55:13 -0500 Subject: [llvm-commits] CVS: llvm/lib/CodeGen/ModuloScheduling/ModuloScheduling.cpp Message-ID: <200408162155.QAA02507@apoc.cs.uiuc.edu> Changes in directory llvm/lib/CodeGen/ModuloScheduling: ModuloScheduling.cpp updated: 1.24 -> 1.25 --- Log message: Move MachineCodeForInstruction.h and MachineFunctionInfo.h into lib/Target/SparcV9 --- Diffs of the changes: (+1 -2) Index: llvm/lib/CodeGen/ModuloScheduling/ModuloScheduling.cpp diff -u llvm/lib/CodeGen/ModuloScheduling/ModuloScheduling.cpp:1.24 llvm/lib/CodeGen/ModuloScheduling/ModuloScheduling.cpp:1.25 --- llvm/lib/CodeGen/ModuloScheduling/ModuloScheduling.cpp:1.24 Wed Aug 4 02:34:57 2004 +++ llvm/lib/CodeGen/ModuloScheduling/ModuloScheduling.cpp Mon Aug 16 16:55:02 2004 @@ -18,10 +18,8 @@ #include "llvm/Instructions.h" #include "llvm/Function.h" #include "llvm/CodeGen/MachineFunction.h" -#include "llvm/CodeGen/MachineCodeForInstruction.h" #include "llvm/CodeGen/Passes.h" #include "llvm/Support/CFG.h" -#include "Support/Casting.h" #include "llvm/Target/TargetSchedInfo.h" #include "Support/Debug.h" #include "Support/GraphWriter.h" @@ -31,6 +29,7 @@ #include #include #include +#include "../../Target/SparcV9/MachineCodeForInstruction.h" #include "../../Target/SparcV9/SparcV9TmpInstr.h" #include "../../Target/SparcV9/SparcV9Internals.h" #include "../../Target/SparcV9/SparcV9RegisterInfo.h" From lattner at cs.uiuc.edu Mon Aug 16 16:56:26 2004 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Mon, 16 Aug 2004 16:56:26 -0500 Subject: [llvm-commits] CVS: llvm/include/llvm/CodeGen/MachineFunctionInfo.h MachineCodeForInstruction.h Message-ID: <200408162156.QAA03578@apoc.cs.uiuc.edu> Changes in directory llvm/include/llvm/CodeGen: MachineFunctionInfo.h (r1.5) removed MachineCodeForInstruction.h (r1.15) removed --- Log message: These files now live in lib/Target/SparcV9 --- Diffs of the changes: (+0 -0) From lattner at cs.uiuc.edu Mon Aug 16 17:35:38 2004 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Mon, 16 Aug 2004 17:35:38 -0500 Subject: [llvm-commits] CVS: llvm/include/llvm/CodeGen/MachineFunction.h Message-ID: <200408162235.RAA13990@apoc.cs.uiuc.edu> Changes in directory llvm/include/llvm/CodeGen: MachineFunction.h updated: 1.38 -> 1.39 --- Log message: Fit into 80 lines, add a gross hack for MachineFunctionInfo --- Diffs of the changes: (+14 -10) Index: llvm/include/llvm/CodeGen/MachineFunction.h diff -u llvm/include/llvm/CodeGen/MachineFunction.h:1.38 llvm/include/llvm/CodeGen/MachineFunction.h:1.39 --- llvm/include/llvm/CodeGen/MachineFunction.h:1.38 Wed Jul 7 19:47:58 2004 +++ llvm/include/llvm/CodeGen/MachineFunction.h Mon Aug 16 17:35:26 2004 @@ -42,26 +42,30 @@ static const MachineBasicBlock* getNext(const MachineBasicBlock* N) { return N->Next; } - static void setPrev(MachineBasicBlock* N, MachineBasicBlock* prev) { N->Prev = prev; } - static void setNext(MachineBasicBlock* N, MachineBasicBlock* next) { N->Next = next; } - + static void setPrev(MachineBasicBlock* N, MachineBasicBlock* prev) { + N->Prev = prev; + } + static void setNext(MachineBasicBlock* N, MachineBasicBlock* next) { + N->Next = next; + } static MachineBasicBlock* createNode(); void addNodeToList(MachineBasicBlock* N); void removeNodeFromList(MachineBasicBlock* N); - void transferNodesFromList( - iplist >& toList, + void transferNodesFromList(iplist > &toList, ilist_iterator first, ilist_iterator last); }; - class Function; class TargetMachine; class SSARegMap; -class MachineFunctionInfo; class MachineFrameInfo; class MachineConstantPool; +// MachineFunctionInfoBase - This is a gross SparcV9 hack +struct MachineFunctionInfoBase { virtual ~MachineFunctionInfoBase() {}; }; +class MachineFunctionInfo; class MachineFunction : private Annotation { const Function *Fn; @@ -73,8 +77,8 @@ // Keeping track of mapping from SSA values to registers SSARegMap *SSARegMapping; - // Used to keep track of frame and constant area information for sparc be - MachineFunctionInfo *MFInfo; + // Used to keep track of frame and constant area information for SparcV9 BE. + mutable MachineFunctionInfoBase *MFInfo; // Keep track of objects allocated on the stack. MachineFrameInfo *FrameInfo; @@ -118,7 +122,7 @@ /// MachineFunctionInfo - Keep track of various per-function pieces of /// information for the sparc backend. /// - MachineFunctionInfo *getInfo() const { return MFInfo; } + MachineFunctionInfo *getInfo() const; /// getBlockNumbered - MachineBasicBlocks are automatically numbered when they /// are inserted into the machine function. The block number for a machine From lattner at cs.uiuc.edu Mon Aug 16 17:36:20 2004 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Mon, 16 Aug 2004 17:36:20 -0500 Subject: [llvm-commits] CVS: llvm/lib/CodeGen/MachineCodeForInstruction.cpp Message-ID: <200408162236.RAA14010@apoc.cs.uiuc.edu> Changes in directory llvm/lib/CodeGen: MachineCodeForInstruction.cpp (r1.19) removed --- Log message: This file is moving to lib/Target/SparcV9 --- Diffs of the changes: (+0 -0) From lattner at cs.uiuc.edu Mon Aug 16 17:36:45 2004 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Mon, 16 Aug 2004 17:36:45 -0500 Subject: [llvm-commits] CVS: llvm/lib/CodeGen/MachineFunction.cpp Message-ID: <200408162236.RAA14021@apoc.cs.uiuc.edu> Changes in directory llvm/lib/CodeGen: MachineFunction.cpp updated: 1.70 -> 1.71 --- Log message: Move this code to lib/Target/SparcV9/MachineFunctionInfo.cpp --- Diffs of the changes: (+1 -158) Index: llvm/lib/CodeGen/MachineFunction.cpp diff -u llvm/lib/CodeGen/MachineFunction.cpp:1.70 llvm/lib/CodeGen/MachineFunction.cpp:1.71 --- llvm/lib/CodeGen/MachineFunction.cpp:1.70 Mon Aug 16 16:54:59 2004 +++ llvm/lib/CodeGen/MachineFunction.cpp Mon Aug 16 17:36:34 2004 @@ -23,8 +23,6 @@ #include "llvm/Target/TargetFrameInfo.h" #include "llvm/Function.h" #include "llvm/Instructions.h" -#include "llvm/Type.h" -#include "../Target/SparcV9/MachineFunctionInfo.h" // FIXME #include "Support/LeakDetector.h" #include "Support/GraphWriter.h" #include @@ -112,7 +110,7 @@ const TargetMachine &TM) : Annotation(MF_AID), Fn(F), Target(TM) { SSARegMapping = new SSARegMap(); - MFInfo = new MachineFunctionInfo(*this); + MFInfo = 0; FrameInfo = new MachineFrameInfo(); ConstantPool = new MachineConstantPool(); BasicBlocks.Parent = this; @@ -307,158 +305,3 @@ void MachineConstantPool::dump() const { print(std::cerr); } -//===----------------------------------------------------------------------===// -// MachineFunctionInfo implementation -// NOTE: MachineFunctionInfo and its methods are specific to the SparcV9 -// target - don't use them in other targets. -//===----------------------------------------------------------------------===// - -static unsigned -ComputeMaxOptionalArgsSize(const TargetMachine& target, const Function *F, - unsigned &maxOptionalNumArgs) -{ - unsigned maxSize = 0; - - for (Function::const_iterator BB = F->begin(), BBE = F->end(); BB !=BBE; ++BB) - for (BasicBlock::const_iterator I = BB->begin(), E = BB->end(); I != E; ++I) - if (const CallInst *callInst = dyn_cast(I)) - { - unsigned numOperands = callInst->getNumOperands() - 1; - int numExtra = numOperands-6; - if (numExtra <= 0) - continue; - - unsigned sizeForThisCall = numExtra * 8; - - if (maxSize < sizeForThisCall) - maxSize = sizeForThisCall; - - if ((int)maxOptionalNumArgs < numExtra) - maxOptionalNumArgs = (unsigned) numExtra; - } - - return maxSize; -} - -// Align data larger than one L1 cache line on L1 cache line boundaries. -// Align all smaller data on the next higher 2^x boundary (4, 8, ...), -// but not higher than the alignment of the largest type we support -// (currently a double word). -- see class TargetData). -// -// This function is similar to the corresponding function in EmitAssembly.cpp -// but they are unrelated. This one does not align at more than a -// double-word boundary whereas that one might. -// -inline unsigned -SizeToAlignment(unsigned size, const TargetMachine& target) -{ - const unsigned short cacheLineSize = 16; - if (size > (unsigned) cacheLineSize / 2) - return cacheLineSize; - else - for (unsigned sz=1; /*no condition*/; sz *= 2) - if (sz >= size || sz >= target.getTargetData().getDoubleAlignment()) - return sz; -} - - -void MachineFunctionInfo::CalculateArgSize() { - maxOptionalArgsSize = ComputeMaxOptionalArgsSize(MF.getTarget(), - MF.getFunction(), - maxOptionalNumArgs); - staticStackSize = maxOptionalArgsSize + 176; -} - -int -MachineFunctionInfo::computeOffsetforLocalVar(const Value* val, - unsigned &getPaddedSize, - unsigned sizeToUse) -{ - if (sizeToUse == 0) { - // All integer types smaller than ints promote to 4 byte integers. - if (val->getType()->isIntegral() && val->getType()->getPrimitiveSize() < 4) - sizeToUse = 4; - else - sizeToUse = MF.getTarget().getTargetData().getTypeSize(val->getType()); - } - unsigned align = SizeToAlignment(sizeToUse, MF.getTarget()); - - bool growUp; - int firstOffset = MF.getTarget().getFrameInfo()->getFirstAutomaticVarOffset(MF, - growUp); - int offset = growUp? firstOffset + getAutomaticVarsSize() - : firstOffset - (getAutomaticVarsSize() + sizeToUse); - - int aligned = MF.getTarget().getFrameInfo()->adjustAlignment(offset, growUp, align); - getPaddedSize = sizeToUse + abs(aligned - offset); - - return aligned; -} - - -int MachineFunctionInfo::allocateLocalVar(const Value* val, - unsigned sizeToUse) { - assert(! automaticVarsAreaFrozen && - "Size of auto vars area has been used to compute an offset so " - "no more automatic vars should be allocated!"); - - // Check if we've allocated a stack slot for this value already - // - hash_map::const_iterator pair = offsets.find(val); - if (pair != offsets.end()) - return pair->second; - - unsigned getPaddedSize; - unsigned offset = computeOffsetforLocalVar(val, getPaddedSize, sizeToUse); - offsets[val] = offset; - incrementAutomaticVarsSize(getPaddedSize); - return offset; -} - -int -MachineFunctionInfo::allocateSpilledValue(const Type* type) -{ - assert(! spillsAreaFrozen && - "Size of reg spills area has been used to compute an offset so " - "no more register spill slots should be allocated!"); - - unsigned size = MF.getTarget().getTargetData().getTypeSize(type); - unsigned char align = MF.getTarget().getTargetData().getTypeAlignment(type); - - bool growUp; - int firstOffset = MF.getTarget().getFrameInfo()->getRegSpillAreaOffset(MF, growUp); - - int offset = growUp? firstOffset + getRegSpillsSize() - : firstOffset - (getRegSpillsSize() + size); - - int aligned = MF.getTarget().getFrameInfo()->adjustAlignment(offset, growUp, align); - size += abs(aligned - offset); // include alignment padding in size - - incrementRegSpillsSize(size); // update size of reg. spills area - - return aligned; -} - -int -MachineFunctionInfo::pushTempValue(unsigned size) -{ - unsigned align = SizeToAlignment(size, MF.getTarget()); - - bool growUp; - int firstOffset = MF.getTarget().getFrameInfo()->getTmpAreaOffset(MF, growUp); - - int offset = growUp? firstOffset + currentTmpValuesSize - : firstOffset - (currentTmpValuesSize + size); - - int aligned = MF.getTarget().getFrameInfo()->adjustAlignment(offset, growUp, - align); - size += abs(aligned - offset); // include alignment padding in size - - incrementTmpAreaSize(size); // update "current" size of tmp area - - return aligned; -} - -void MachineFunctionInfo::popAllTempValues() { - resetTmpAreaSize(); // clear tmp area to reuse -} From lattner at cs.uiuc.edu Mon Aug 16 17:37:28 2004 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Mon, 16 Aug 2004 17:37:28 -0500 Subject: [llvm-commits] CVS: llvm/lib/Target/SparcV9/MachineFunctionInfo.h Message-ID: <200408162237.RAA14042@apoc.cs.uiuc.edu> Changes in directory llvm/lib/Target/SparcV9: MachineFunctionInfo.h updated: 1.6 -> 1.7 --- Log message: Hacks to make the MachineFunction class be able to delete the MFI object without knowing anything about it. --- Diffs of the changes: (+2 -1) Index: llvm/lib/Target/SparcV9/MachineFunctionInfo.h diff -u llvm/lib/Target/SparcV9/MachineFunctionInfo.h:1.6 llvm/lib/Target/SparcV9/MachineFunctionInfo.h:1.7 --- llvm/lib/Target/SparcV9/MachineFunctionInfo.h:1.6 Mon Aug 16 16:54:29 2004 +++ llvm/lib/Target/SparcV9/MachineFunctionInfo.h Mon Aug 16 17:37:18 2004 @@ -19,6 +19,7 @@ #define MACHINEFUNCTIONINFO_H #include "MachineCodeForInstruction.h" +#include "llvm/CodeGen/MachineFunction.h" #include "Support/HashExtras.h" #include "Support/hash_set" @@ -28,7 +29,7 @@ class Constant; class Type; -class MachineFunctionInfo { +class MachineFunctionInfo : public MachineFunctionInfoBase { hash_set constantsForConstPool; hash_map offsets; From lattner at cs.uiuc.edu Mon Aug 16 17:37:34 2004 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Mon, 16 Aug 2004 17:37:34 -0500 Subject: [llvm-commits] CVS: llvm/lib/Target/SparcV9/MachineFunctionInfo.cpp Message-ID: <200408162237.RAA14046@apoc.cs.uiuc.edu> Changes in directory llvm/lib/Target/SparcV9: MachineFunctionInfo.cpp added (r1.1) --- Log message: Code moved out of lib/CodeGen/MachineFunction.cpp --- Diffs of the changes: (+180 -0) Index: llvm/lib/Target/SparcV9/MachineFunctionInfo.cpp diff -c /dev/null llvm/lib/Target/SparcV9/MachineFunctionInfo.cpp:1.1 *** /dev/null Mon Aug 16 17:37:34 2004 --- llvm/lib/Target/SparcV9/MachineFunctionInfo.cpp Mon Aug 16 17:36:54 2004 *************** *** 0 **** --- 1,180 ---- + //===-- MachineFunctionInfo.cpp -------------------------------------------===// + // + // The LLVM Compiler Infrastructure + // + // This file was developed by the LLVM research group and is distributed under + // the University of Illinois Open Source License. See LICENSE.TXT for details. + // + //===----------------------------------------------------------------------===// + // + // This implements the SparcV9 specific MachineFunctionInfo class. + // + //===----------------------------------------------------------------------===// + + #include "MachineFunctionInfo.h" + #include "llvm/Instructions.h" + #include "llvm/Function.h" + #include "llvm/Type.h" + #include "llvm/CodeGen/MachineFunction.h" + #include "llvm/Target/TargetMachine.h" + #include "llvm/Target/TargetFrameInfo.h" + using namespace llvm; + + MachineFunctionInfo *MachineFunction::getInfo() const { + if (!MFInfo) { + MFInfo = new MachineFunctionInfo(*const_cast(this)); + } + return static_cast(MFInfo); + } + + + + static unsigned + ComputeMaxOptionalArgsSize(const TargetMachine& target, const Function *F, + unsigned &maxOptionalNumArgs) + { + unsigned maxSize = 0; + + for (Function::const_iterator BB = F->begin(), BBE = F->end(); BB !=BBE; ++BB) + for (BasicBlock::const_iterator I = BB->begin(), E = BB->end(); I != E; ++I) + if (const CallInst *callInst = dyn_cast(I)) + { + unsigned numOperands = callInst->getNumOperands() - 1; + int numExtra = numOperands-6; + if (numExtra <= 0) + continue; + + unsigned sizeForThisCall = numExtra * 8; + + if (maxSize < sizeForThisCall) + maxSize = sizeForThisCall; + + if ((int)maxOptionalNumArgs < numExtra) + maxOptionalNumArgs = (unsigned) numExtra; + } + + return maxSize; + } + + // Align data larger than one L1 cache line on L1 cache line boundaries. + // Align all smaller data on the next higher 2^x boundary (4, 8, ...), + // but not higher than the alignment of the largest type we support + // (currently a double word). -- see class TargetData). + // + // This function is similar to the corresponding function in EmitAssembly.cpp + // but they are unrelated. This one does not align at more than a + // double-word boundary whereas that one might. + // + inline unsigned + SizeToAlignment(unsigned size, const TargetMachine& target) + { + const unsigned short cacheLineSize = 16; + if (size > (unsigned) cacheLineSize / 2) + return cacheLineSize; + else + for (unsigned sz=1; /*no condition*/; sz *= 2) + if (sz >= size || sz >= target.getTargetData().getDoubleAlignment()) + return sz; + } + + + void MachineFunctionInfo::CalculateArgSize() { + maxOptionalArgsSize = ComputeMaxOptionalArgsSize(MF.getTarget(), + MF.getFunction(), + maxOptionalNumArgs); + staticStackSize = maxOptionalArgsSize + 176; + } + + int + MachineFunctionInfo::computeOffsetforLocalVar(const Value* val, + unsigned &getPaddedSize, + unsigned sizeToUse) + { + if (sizeToUse == 0) { + // All integer types smaller than ints promote to 4 byte integers. + if (val->getType()->isIntegral() && val->getType()->getPrimitiveSize() < 4) + sizeToUse = 4; + else + sizeToUse = MF.getTarget().getTargetData().getTypeSize(val->getType()); + } + unsigned align = SizeToAlignment(sizeToUse, MF.getTarget()); + + bool growUp; + int firstOffset = MF.getTarget().getFrameInfo()->getFirstAutomaticVarOffset(MF, + growUp); + int offset = growUp? firstOffset + getAutomaticVarsSize() + : firstOffset - (getAutomaticVarsSize() + sizeToUse); + + int aligned = MF.getTarget().getFrameInfo()->adjustAlignment(offset, growUp, align); + getPaddedSize = sizeToUse + abs(aligned - offset); + + return aligned; + } + + + int MachineFunctionInfo::allocateLocalVar(const Value* val, + unsigned sizeToUse) { + assert(! automaticVarsAreaFrozen && + "Size of auto vars area has been used to compute an offset so " + "no more automatic vars should be allocated!"); + + // Check if we've allocated a stack slot for this value already + // + hash_map::const_iterator pair = offsets.find(val); + if (pair != offsets.end()) + return pair->second; + + unsigned getPaddedSize; + unsigned offset = computeOffsetforLocalVar(val, getPaddedSize, sizeToUse); + offsets[val] = offset; + incrementAutomaticVarsSize(getPaddedSize); + return offset; + } + + int + MachineFunctionInfo::allocateSpilledValue(const Type* type) + { + assert(! spillsAreaFrozen && + "Size of reg spills area has been used to compute an offset so " + "no more register spill slots should be allocated!"); + + unsigned size = MF.getTarget().getTargetData().getTypeSize(type); + unsigned char align = MF.getTarget().getTargetData().getTypeAlignment(type); + + bool growUp; + int firstOffset = MF.getTarget().getFrameInfo()->getRegSpillAreaOffset(MF, growUp); + + int offset = growUp? firstOffset + getRegSpillsSize() + : firstOffset - (getRegSpillsSize() + size); + + int aligned = MF.getTarget().getFrameInfo()->adjustAlignment(offset, growUp, align); + size += abs(aligned - offset); // include alignment padding in size + + incrementRegSpillsSize(size); // update size of reg. spills area + + return aligned; + } + + int + MachineFunctionInfo::pushTempValue(unsigned size) + { + unsigned align = SizeToAlignment(size, MF.getTarget()); + + bool growUp; + int firstOffset = MF.getTarget().getFrameInfo()->getTmpAreaOffset(MF, growUp); + + int offset = growUp? firstOffset + currentTmpValuesSize + : firstOffset - (currentTmpValuesSize + size); + + int aligned = MF.getTarget().getFrameInfo()->adjustAlignment(offset, growUp, + align); + size += abs(aligned - offset); // include alignment padding in size + + incrementTmpAreaSize(size); // update "current" size of tmp area + + return aligned; + } + + void MachineFunctionInfo::popAllTempValues() { + resetTmpAreaSize(); // clear tmp area to reuse + } From lattner at cs.uiuc.edu Mon Aug 16 17:38:13 2004 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Mon, 16 Aug 2004 17:38:13 -0500 Subject: [llvm-commits] CVS: llvm/lib/Target/SparcV9/MachineCodeForInstruction.cpp Message-ID: <200408162238.RAA14059@apoc.cs.uiuc.edu> Changes in directory llvm/lib/Target/SparcV9: MachineCodeForInstruction.cpp added (r1.1) --- Log message: Moved this file out of lib/CodeGen --- Diffs of the changes: (+119 -0) Index: llvm/lib/Target/SparcV9/MachineCodeForInstruction.cpp diff -c /dev/null llvm/lib/Target/SparcV9/MachineCodeForInstruction.cpp:1.1 *** /dev/null Mon Aug 16 17:38:12 2004 --- llvm/lib/Target/SparcV9/MachineCodeForInstruction.cpp Mon Aug 16 17:38:02 2004 *************** *** 0 **** --- 1,119 ---- + //===-- MachineCodeForInstruction.cpp -------------------------------------===// + // + // The LLVM Compiler Infrastructure + // + // This file was developed by the LLVM research group and is distributed under + // the University of Illinois Open Source License. See LICENSE.TXT for details. + // + //===----------------------------------------------------------------------===// + // + // Representation of the sequence of machine instructions created for a single + // VM instruction. Additionally records information about hidden and implicit + // values used by the machine instructions: about hidden values used by the + // machine instructions: + // + // "Temporary values" are intermediate values used in the machine instruction + // sequence, but not in the VM instruction. Note that such values should be + // treated as pure SSA values with no interpretation of their operands (i.e., as + // a TmpInstruction object which actually represents such a value). + // + // (2) "Implicit uses" are values used in the VM instruction but not in the + // machine instruction sequence + // + //===----------------------------------------------------------------------===// + + #include "MachineCodeForInstruction.h" + #include "llvm/Function.h" + #include "llvm/Instructions.h" + #include "llvm/Type.h" + #include "llvm/CodeGen/MachineInstr.h" + #include "llvm/CodeGen/MachineFunction.h" + #include "MachineFunctionInfo.h" + #include "MachineInstrAnnot.h" + #include "SparcV9TmpInstr.h" + using namespace llvm; + + MachineCodeForInstruction &MachineCodeForInstruction::get(const Instruction *I){ + MachineFunction &MF = MachineFunction::get(I->getParent()->getParent()); + return MF.getInfo()->MCFIEntries[I]; + } + void MachineCodeForInstruction::destroy(const Instruction *I) { + MachineFunction &MF = MachineFunction::get(I->getParent()->getParent()); + MF.getInfo()->MCFIEntries.erase(I); + } + + void + MachineCodeForInstruction::dropAllReferences() + { + for (unsigned i=0, N=tempVec.size(); i < N; i++) + cast(tempVec[i])->dropAllReferences(); + } + + + MachineCodeForInstruction::~MachineCodeForInstruction() { + // Let go of all uses in temp. instructions + dropAllReferences(); + + // Free the Value objects created to hold intermediate values + for (unsigned i=0, N=tempVec.size(); i < N; i++) + delete tempVec[i]; + + // do not free the MachineInstr objects allocated. they are managed + // by the ilist in MachineBasicBlock + + // Free the CallArgsDescriptor if it exists. + delete callArgsDesc; + } + + + CallArgsDescriptor::CallArgsDescriptor(CallInst* _callInstr, + TmpInstruction* _retAddrReg, + bool _isVarArgs, bool _noPrototype) + : callInstr(_callInstr), + funcPtr(isa(_callInstr->getCalledValue()) + ? NULL : _callInstr->getCalledValue()), + retAddrReg(_retAddrReg), + isVarArgs(_isVarArgs), + noPrototype(_noPrototype) { + unsigned int numArgs = callInstr->getNumOperands(); + argInfoVec.reserve(numArgs); + assert(callInstr->getOperand(0) == callInstr->getCalledValue() + && "Operand 0 is ignored in the loop below!"); + for (unsigned int i=1; i < numArgs; ++i) + argInfoVec.push_back(CallArgInfo(callInstr->getOperand(i))); + + // Enter this object in the MachineCodeForInstr object of the CallInst. + // This transfers ownership of this object. + MachineCodeForInstruction::get(callInstr).setCallArgsDescriptor(this); + } + + CallInst *CallArgsDescriptor::getReturnValue() const { + return (callInstr->getType() == Type::VoidTy? NULL : callInstr); + } + + // Mechanism to get the descriptor for a CALL MachineInstr. + // We get the LLVM CallInstr from the ret. addr. register argument + // of the CALL MachineInstr (which is explicit operand #3 for indirect + // calls or the last implicit operand for direct calls). We then get + // the CallArgsDescriptor from the MachineCodeForInstruction object for + // the CallInstr. + // This is roundabout but avoids adding a new map or annotation just + // to keep track of CallArgsDescriptors. + // + CallArgsDescriptor *CallArgsDescriptor::get(const MachineInstr* MI) { + const TmpInstruction* retAddrReg = + cast(isa(MI->getOperand(0).getVRegValue()) + ? MI->getImplicitRef(MI->getNumImplicitRefs()-1) + : MI->getOperand(2).getVRegValue()); + + assert(retAddrReg->getNumOperands() == 1 && + isa(retAddrReg->getOperand(0)) && + "Location of callInstr arg for CALL instr. changed? FIX THIS CODE!"); + + const CallInst* callInstr = cast(retAddrReg->getOperand(0)); + + CallArgsDescriptor* desc = + MachineCodeForInstruction::get(callInstr).getCallArgsDescriptor(); + assert(desc->getCallInst()==callInstr && "Incorrect call args descriptor?"); + return desc; + } From lattner at cs.uiuc.edu Mon Aug 16 18:15:33 2004 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Mon, 16 Aug 2004 18:15:33 -0500 Subject: [llvm-commits] CVS: llvm/include/llvm/CodeGen/AsmPrinter.h Message-ID: <200408162315.SAA18220@apoc.cs.uiuc.edu> Changes in directory llvm/include/llvm/CodeGen: AsmPrinter.h added (r1.1) --- Log message: Initial implementation of the asmprinter base class --- Diffs of the changes: (+65 -0) Index: llvm/include/llvm/CodeGen/AsmPrinter.h diff -c /dev/null llvm/include/llvm/CodeGen/AsmPrinter.h:1.1 *** /dev/null Mon Aug 16 18:15:31 2004 --- llvm/include/llvm/CodeGen/AsmPrinter.h Mon Aug 16 18:15:20 2004 *************** *** 0 **** --- 1,65 ---- + //===-- llvm/CodeGen/AsmPrinter.h - AsmPrinter Framework --------*- C++ -*-===// + // + // The LLVM Compiler Infrastructure + // + // This file was developed by the LLVM research group and is distributed under + // the University of Illinois Open Source License. See LICENSE.TXT for details. + // + //===----------------------------------------------------------------------===// + // + // This class is intended to be used as a base class for target-specific + // asmwriters. This class primarily takes care of printing global constants, + // which are printed in a very similar way across all targets. + // + //===----------------------------------------------------------------------===// + + #ifndef LLVM_CODEGEN_ASMPRINTER_H + #define LLVM_CODEGEN_ASMPRINTER_H + + #include "llvm/CodeGen/MachineFunctionPass.h" + + namespace llvm { + class Constant; + class Mangler; + + class AsmPrinter : public MachineFunctionPass { + protected: + /// Output stream on which we're printing assembly code. + /// + std::ostream &O; + + /// Target machine description. + /// + TargetMachine &TM; + + /// Name-mangler for global names. + /// + Mangler *Mang; + + /// Cache of mangled name for current function. This is recalculated at the + /// beginning of each call to runOnMachineFunction(). + /// + std::string CurrentFnName; + + AsmPrinter(std::ostream &o, TargetMachine &tm) : O(o), TM(tm) { } + + /// doInitialization - Set up the AsmPrinter when we are working on a new + /// module. If your pass overrides this, it must make sure to explicitly + /// call this implementation. + bool doInitialization(Module &M); + + /// doFinalization - Shut down the asmprinter. If you override this in your + /// pass, you must make sure to call it explicitly. + bool doFinalization(Module &M); + + /// setupMachineFunction - This should be called when a new MachineFunction + /// is being processed from runOnMachineFunction. + void setupMachineFunction(MachineFunction &MF); + + /// emitConstantValueOnly - Print out the specified constant, without a + /// storage class. Only constants of first-class type are allowed here. + void emitConstantValueOnly(const Constant *CV); + }; + } + + #endif From lattner at cs.uiuc.edu Mon Aug 16 18:15:33 2004 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Mon, 16 Aug 2004 18:15:33 -0500 Subject: [llvm-commits] CVS: llvm/lib/CodeGen/AsmPrinter.cpp Message-ID: <200408162315.SAA18221@apoc.cs.uiuc.edu> Changes in directory llvm/lib/CodeGen: AsmPrinter.cpp added (r1.1) --- Log message: Initial implementation of the asmprinter base class --- Diffs of the changes: (+110 -0) Index: llvm/lib/CodeGen/AsmPrinter.cpp diff -c /dev/null llvm/lib/CodeGen/AsmPrinter.cpp:1.1 *** /dev/null Mon Aug 16 18:15:32 2004 --- llvm/lib/CodeGen/AsmPrinter.cpp Mon Aug 16 18:15:22 2004 *************** *** 0 **** --- 1,110 ---- + //===-- AsmPrinter.cpp - Common AsmPrinter code ---------------------------===// + // + // The LLVM Compiler Infrastructure + // + // This file was developed by the LLVM research group and is distributed under + // the University of Illinois Open Source License. See LICENSE.TXT for details. + // + //===----------------------------------------------------------------------===// + // + // This file implements the AsmPrinter class. + // + //===----------------------------------------------------------------------===// + + #include "llvm/CodeGen/AsmPrinter.h" + #include "llvm/Constants.h" + #include "llvm/Instruction.h" + #include "llvm/Support/Mangler.h" + #include "llvm/Target/TargetMachine.h" + using namespace llvm; + + bool AsmPrinter::doInitialization(Module &M) { + Mang = new Mangler(M); + return false; + } + + bool AsmPrinter::doFinalization(Module &M) { + delete Mang; Mang = 0; + return false; + } + + void AsmPrinter::setupMachineFunction(MachineFunction &MF) { + // What's my mangled name? + CurrentFnName = Mang->getValueName((Value*)MF.getFunction()); + + } + + + + // Print out the specified constant, without a storage class. Only the + // constants valid in constant expressions can occur here. + void AsmPrinter::emitConstantValueOnly(const Constant *CV) { + if (CV->isNullValue()) + O << "0"; + else if (const ConstantBool *CB = dyn_cast(CV)) { + assert(CB == ConstantBool::True); + O << "1"; + } else if (const ConstantSInt *CI = dyn_cast(CV)) + if (((CI->getValue() << 32) >> 32) == CI->getValue()) + O << CI->getValue(); + else + O << (unsigned long long)CI->getValue(); + else if (const ConstantUInt *CI = dyn_cast(CV)) + O << CI->getValue(); + else if (isa((Value*)CV)) + // This is a constant address for a global variable or function. Use the + // name of the variable or function as the address value. + O << Mang->getValueName(CV); + else if (const ConstantExpr *CE = dyn_cast(CV)) { + const TargetData &TD = TM.getTargetData(); + switch(CE->getOpcode()) { + case Instruction::GetElementPtr: { + // generate a symbolic expression for the byte address + const Constant *ptrVal = CE->getOperand(0); + std::vector idxVec(CE->op_begin()+1, CE->op_end()); + if (unsigned Offset = TD.getIndexedOffset(ptrVal->getType(), idxVec)) { + O << "("; + emitConstantValueOnly(ptrVal); + O << ") + " << Offset; + } else { + emitConstantValueOnly(ptrVal); + } + break; + } + case Instruction::Cast: { + // Support only non-converting or widening casts for now, that is, ones + // that do not involve a change in value. This assertion is really gross, + // and may not even be a complete check. + Constant *Op = CE->getOperand(0); + const Type *OpTy = Op->getType(), *Ty = CE->getType(); + + // Remember, kids, pointers can be losslessly converted back and forth + // into 32-bit or wider integers, regardless of signedness. :-P + assert(((isa(OpTy) + && (Ty == Type::LongTy || Ty == Type::ULongTy + || Ty == Type::IntTy || Ty == Type::UIntTy)) + || (isa(Ty) + && (OpTy == Type::LongTy || OpTy == Type::ULongTy + || OpTy == Type::IntTy || OpTy == Type::UIntTy)) + || (((TD.getTypeSize(Ty) >= TD.getTypeSize(OpTy)) + && OpTy->isLosslesslyConvertibleTo(Ty)))) + && "FIXME: Don't yet support this kind of constant cast expr"); + O << "("; + emitConstantValueOnly(Op); + O << ")"; + break; + } + case Instruction::Add: + O << "("; + emitConstantValueOnly(CE->getOperand(0)); + O << ") + ("; + emitConstantValueOnly(CE->getOperand(1)); + O << ")"; + break; + default: + assert(0 && "Unsupported operator!"); + } + } else { + assert(0 && "Unknown constant value!"); + } + } From lattner at cs.uiuc.edu Mon Aug 16 18:16:17 2004 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Mon, 16 Aug 2004 18:16:17 -0500 Subject: [llvm-commits] CVS: llvm/lib/Target/X86/X86AsmPrinter.cpp Message-ID: <200408162316.SAA18240@apoc.cs.uiuc.edu> Changes in directory llvm/lib/Target/X86: X86AsmPrinter.cpp updated: 1.116 -> 1.117 --- Log message: Start using the AsmPrinter to emit our first class constants. This also drops our half-assed support for cygwin, which noone uses and doesn't work anyway. --- Diffs of the changes: (+11 -109) Index: llvm/lib/Target/X86/X86AsmPrinter.cpp diff -u llvm/lib/Target/X86/X86AsmPrinter.cpp:1.116 llvm/lib/Target/X86/X86AsmPrinter.cpp:1.117 --- llvm/lib/Target/X86/X86AsmPrinter.cpp:1.116 Wed Aug 11 02:07:14 2004 +++ llvm/lib/Target/X86/X86AsmPrinter.cpp Mon Aug 16 18:16:06 2004 @@ -21,6 +21,7 @@ #include "llvm/DerivedTypes.h" #include "llvm/Module.h" #include "llvm/Assembly/Writer.h" +#include "llvm/CodeGen/AsmPrinter.h" #include "llvm/CodeGen/MachineCodeEmitter.h" #include "llvm/CodeGen/MachineConstantPool.h" #include "llvm/CodeGen/MachineFunctionPass.h" @@ -36,11 +37,6 @@ namespace { Statistic<> EmittedInsts("asm-printer", "Number of machine instrs printed"); - // FIXME: This should be automatically picked up by autoconf from the C - // frontend - cl::opt EmitCygwin("enable-cygwin-compatible-output", cl::Hidden, - cl::desc("Emit X86 assembly code suitable for consumption by cygwin")); - struct GasBugWorkaroundEmitter : public MachineCodeEmitter { GasBugWorkaroundEmitter(std::ostream& o) : O(o), OldFlags(O.flags()), firstByte(true) { @@ -71,27 +67,8 @@ bool firstByte; }; - struct X86AsmPrinter : public MachineFunctionPass { - /// Output stream on which we're printing assembly code. - /// - std::ostream &O; - - /// Target machine description which we query for reg. names, data - /// layout, etc. - /// - TargetMachine &TM; - - /// Name-mangler for global names. - /// - Mangler *Mang; - - X86AsmPrinter(std::ostream &o, TargetMachine &tm) : O(o), TM(tm) { } - - /// Cache of mangled name for current function. This is - /// recalculated at the beginning of each call to - /// runOnMachineFunction(). - /// - std::string CurrentFnName; + struct X86AsmPrinter : public AsmPrinter { + X86AsmPrinter(std::ostream &O, TargetMachine &TM) : AsmPrinter(O, TM) { } virtual const char *getPassName() const { return "X86 Assembly Printer"; @@ -104,7 +81,7 @@ bool printInstruction(const MachineInstr *MI); // This method is used by the tablegen'erated instruction printer. - void printOperand(const MachineInstr *MI, unsigned OpNo, MVT::ValueType VT) { + void printOperand(const MachineInstr *MI, unsigned OpNo, MVT::ValueType VT){ const MachineOperand &MO = MI->getOperand(OpNo); if (MO.getType() == MachineOperand::MO_MachineRegister) { assert(MRegisterInfo::isPhysicalRegister(MO.getReg())&&"Not physref??"); @@ -115,7 +92,8 @@ } } - void printCallOperand(const MachineInstr *MI, unsigned OpNo, MVT::ValueType VT) { + void printCallOperand(const MachineInstr *MI, unsigned OpNo, + MVT::ValueType VT) { printOp(MI->getOperand(OpNo), true); // Don't print "OFFSET". } @@ -142,7 +120,6 @@ bool doInitialization(Module &M); bool doFinalization(Module &M); void emitGlobalConstant(const Constant* CV); - void emitConstantValueOnly(const Constant *CV); }; } // end of anonymous namespace @@ -201,79 +178,6 @@ O << "\""; } -// Print out the specified constant, without a storage class. Only the -// constants valid in constant expressions can occur here. -void X86AsmPrinter::emitConstantValueOnly(const Constant *CV) { - if (CV->isNullValue()) - O << "0"; - else if (const ConstantBool *CB = dyn_cast(CV)) { - assert(CB == ConstantBool::True); - O << "1"; - } else if (const ConstantSInt *CI = dyn_cast(CV)) - if (((CI->getValue() << 32) >> 32) == CI->getValue()) - O << CI->getValue(); - else - O << (unsigned long long)CI->getValue(); - else if (const ConstantUInt *CI = dyn_cast(CV)) - O << CI->getValue(); - else if (const GlobalValue *GV = dyn_cast(CV)) - // This is a constant address for a global variable or function. Use the - // name of the variable or function as the address value. - O << Mang->getValueName(GV); - else if (const ConstantExpr *CE = dyn_cast(CV)) { - const TargetData &TD = TM.getTargetData(); - switch(CE->getOpcode()) { - case Instruction::GetElementPtr: { - // generate a symbolic expression for the byte address - const Constant *ptrVal = CE->getOperand(0); - std::vector idxVec(CE->op_begin()+1, CE->op_end()); - if (unsigned Offset = TD.getIndexedOffset(ptrVal->getType(), idxVec)) { - O << "("; - emitConstantValueOnly(ptrVal); - O << ") + " << Offset; - } else { - emitConstantValueOnly(ptrVal); - } - break; - } - case Instruction::Cast: { - // Support only non-converting or widening casts for now, that is, ones - // that do not involve a change in value. This assertion is really gross, - // and may not even be a complete check. - Constant *Op = CE->getOperand(0); - const Type *OpTy = Op->getType(), *Ty = CE->getType(); - - // Remember, kids, pointers on x86 can be losslessly converted back and - // forth into 32-bit or wider integers, regardless of signedness. :-P - assert(((isa(OpTy) - && (Ty == Type::LongTy || Ty == Type::ULongTy - || Ty == Type::IntTy || Ty == Type::UIntTy)) - || (isa(Ty) - && (OpTy == Type::LongTy || OpTy == Type::ULongTy - || OpTy == Type::IntTy || OpTy == Type::UIntTy)) - || (((TD.getTypeSize(Ty) >= TD.getTypeSize(OpTy)) - && OpTy->isLosslesslyConvertibleTo(Ty)))) - && "FIXME: Don't yet support this kind of constant cast expr"); - O << "("; - emitConstantValueOnly(Op); - O << ")"; - break; - } - case Instruction::Add: - O << "("; - emitConstantValueOnly(CE->getOperand(0)); - O << ") + ("; - emitConstantValueOnly(CE->getOperand(1)); - O << ")"; - break; - default: - assert(0 && "Unsupported operator!"); - } - } else { - assert(0 && "Unknown constant value!"); - } -} - // Print a constant value or values, with the appropriate storage class as a // prefix. void X86AsmPrinter::emitGlobalConstant(const Constant *CV) { @@ -394,9 +298,8 @@ /// method to print assembly for each instruction. /// bool X86AsmPrinter::runOnMachineFunction(MachineFunction &MF) { + setupMachineFunction(MF); O << "\n\n"; - // What's my mangled name? - CurrentFnName = Mang->getValueName(MF.getFunction()); // Print out constants referenced by the function printConstantPool(MF.getConstantPool()); @@ -405,8 +308,7 @@ O << "\t.text\n"; O << "\t.align 16\n"; O << "\t.globl\t" << CurrentFnName << "\n"; - if (!EmitCygwin) - O << "\t.type\t" << CurrentFnName << ", @function\n"; + O << "\t.type\t" << CurrentFnName << ", @function\n"; O << CurrentFnName << ":\n"; // Print out code for the function. @@ -586,6 +488,7 @@ } bool X86AsmPrinter::doInitialization(Module &M) { + AsmPrinter::doInitialization(M); // Tell gas we are outputting Intel syntax (not AT&T syntax) assembly. // // Bug: gas in `intel_syntax noprefix' mode interprets the symbol `Sp' in an @@ -595,8 +498,7 @@ // `undefined symbol' errors when linking. Workaround: Do not use `noprefix' // mode, and decorate all register names with percent signs. O << "\t.intel_syntax\n"; - Mang = new Mangler(M, EmitCygwin); - return false; // success + return false; } // SwitchSection - Switch to the specified section of the executable if we are @@ -673,6 +575,6 @@ } } - delete Mang; + AsmPrinter::doFinalization(M); return false; // success } From lattner at cs.uiuc.edu Mon Aug 16 18:25:34 2004 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Mon, 16 Aug 2004 18:25:34 -0500 Subject: [llvm-commits] CVS: llvm/lib/Target/PowerPC/PPC32AsmPrinter.cpp Message-ID: <200408162325.SAA19770@apoc.cs.uiuc.edu> Changes in directory llvm/lib/Target/PowerPC: PPC32AsmPrinter.cpp updated: 1.41 -> 1.42 --- Log message: Finegrainify namespacification Start using the AsmPrinter base class to factor out a bunch of code --- Diffs of the changes: (+15 -109) Index: llvm/lib/Target/PowerPC/PPC32AsmPrinter.cpp diff -u llvm/lib/Target/PowerPC/PPC32AsmPrinter.cpp:1.41 llvm/lib/Target/PowerPC/PPC32AsmPrinter.cpp:1.42 --- llvm/lib/Target/PowerPC/PPC32AsmPrinter.cpp:1.41 Sun Aug 15 00:48:47 2004 +++ llvm/lib/Target/PowerPC/PPC32AsmPrinter.cpp Mon Aug 16 18:25:21 2004 @@ -24,6 +24,7 @@ #include "llvm/DerivedTypes.h" #include "llvm/Module.h" #include "llvm/Assembly/Writer.h" +#include "llvm/CodeGen/AsmPrinter.h" #include "llvm/CodeGen/MachineConstantPool.h" #include "llvm/CodeGen/MachineFunctionPass.h" #include "llvm/CodeGen/MachineInstr.h" @@ -35,36 +36,17 @@ #include "Support/Statistic.h" #include "Support/StringExtras.h" #include - -namespace llvm { +using namespace llvm; namespace { Statistic<> EmittedInsts("asm-printer", "Number of machine instrs printed"); - struct PowerPCAsmPrinter : public MachineFunctionPass { - /// Output stream on which we're printing assembly code. - /// - std::ostream &O; - - /// Target machine description which we query for reg. names, data - /// layout, etc. - /// - PowerPCTargetMachine &TM; - - /// Name-mangler for global names. - /// - Mangler *Mang; + struct PowerPCAsmPrinter : public AsmPrinter { std::set FnStubs, GVStubs, LinkOnceStubs; std::set Strings; - PowerPCAsmPrinter(std::ostream &o, TargetMachine &tm) : O(o), - TM(reinterpret_cast(tm)), LabelNumber(0) {} - - /// Cache of mangled name for current function. This is - /// recalculated at the beginning of each call to - /// runOnMachineFunction(). - /// - std::string CurrentFnName; + PowerPCAsmPrinter(std::ostream &O, TargetMachine &TM) + : AsmPrinter(O, TM), LabelNumber(0) {} /// Unique incrementer for label values for referencing Global values. /// @@ -74,6 +56,10 @@ return "PowerPC Assembly Printer"; } + PowerPCTargetMachine &getTM() { + return static_cast(TM); + } + /// printInstruction - This method is automatically generated by tablegen /// from the instruction set description. This method returns true if the /// machine instruction was sufficiently described to print it, otherwise it @@ -103,10 +89,8 @@ void printConstantPool(MachineConstantPool *MCP); bool runOnMachineFunction(MachineFunction &F); - bool doInitialization(Module &M); bool doFinalization(Module &M); void emitGlobalConstant(const Constant* CV); - void emitConstantValueOnly(const Constant *CV); }; } // end of anonymous namespace @@ -115,7 +99,7 @@ /// using the given target machine description. This should work /// regardless of whether the function is in SSA form or not. /// -FunctionPass *createPPCAsmPrinter(std::ostream &o,TargetMachine &tm) { +FunctionPass *llvm::createPPCAsmPrinter(std::ostream &o,TargetMachine &tm) { return new PowerPCAsmPrinter(o, tm); } @@ -178,76 +162,6 @@ O << "\""; } -// Print out the specified constant, without a storage class. Only the -// constants valid in constant expressions can occur here. -void PowerPCAsmPrinter::emitConstantValueOnly(const Constant *CV) { - if (CV->isNullValue()) - O << "0"; - else if (const ConstantBool *CB = dyn_cast(CV)) { - assert(CB == ConstantBool::True); - O << "1"; - } else if (const ConstantSInt *CI = dyn_cast(CV)) - O << CI->getValue(); - else if (const ConstantUInt *CI = dyn_cast(CV)) - O << CI->getValue(); - else if (const GlobalValue *GV = dyn_cast(CV)) - // This is a constant address for a global variable or function. Use the - // name of the variable or function as the address value. - O << Mang->getValueName(GV); - else if (const ConstantExpr *CE = dyn_cast(CV)) { - const TargetData &TD = TM.getTargetData(); - switch (CE->getOpcode()) { - case Instruction::GetElementPtr: { - // generate a symbolic expression for the byte address - const Constant *ptrVal = CE->getOperand(0); - std::vector idxVec(CE->op_begin()+1, CE->op_end()); - if (unsigned Offset = TD.getIndexedOffset(ptrVal->getType(), idxVec)) { - O << "("; - emitConstantValueOnly(ptrVal); - O << ") + " << Offset; - } else { - emitConstantValueOnly(ptrVal); - } - break; - } - case Instruction::Cast: { - // Support only non-converting or widening casts for now, that is, ones - // that do not involve a change in value. This assertion is really gross, - // and may not even be a complete check. - Constant *Op = CE->getOperand(0); - const Type *OpTy = Op->getType(), *Ty = CE->getType(); - - // Remember, kids, pointers on x86 can be losslessly converted back and - // forth into 32-bit or wider integers, regardless of signedness. :-P - assert(((isa(OpTy) - && (Ty == Type::LongTy || Ty == Type::ULongTy - || Ty == Type::IntTy || Ty == Type::UIntTy)) - || (isa(Ty) - && (OpTy == Type::LongTy || OpTy == Type::ULongTy - || OpTy == Type::IntTy || OpTy == Type::UIntTy)) - || (((TD.getTypeSize(Ty) >= TD.getTypeSize(OpTy)) - && OpTy->isLosslesslyConvertibleTo(Ty)))) - && "FIXME: Don't yet support this kind of constant cast expr"); - O << "("; - emitConstantValueOnly(Op); - O << ")"; - break; - } - case Instruction::Add: - O << "("; - emitConstantValueOnly(CE->getOperand(0)); - O << ") + ("; - emitConstantValueOnly(CE->getOperand(1)); - O << ")"; - break; - default: - assert(0 && "Unsupported operator!"); - } - } else { - assert(0 && "Unknown constant value!"); - } -} - // Print a constant value or values, with the appropriate storage class as a // prefix. void PowerPCAsmPrinter::emitGlobalConstant(const Constant *CV) { @@ -382,9 +296,8 @@ /// method to print assembly for each instruction. /// bool PowerPCAsmPrinter::runOnMachineFunction(MachineFunction &MF) { + setupMachineFunction(MF); O << "\n\n"; - // What's my mangled name? - CurrentFnName = Mang->getValueName(MF.getFunction()); // Print out constants referenced by the function printConstantPool(MF.getConstantPool()); @@ -467,20 +380,20 @@ // are taken. Those should be emitted as $non_lazy_ptr below. Function *F = dyn_cast(GV); if (F && F->isExternal() && !LoadAddrOp && - TM.CalledFunctions.find(F) != TM.CalledFunctions.end()) { + getTM().CalledFunctions.count(F)) { FnStubs.insert(Name); O << "L" << Name << "$stub"; return; } // External global variables need a non-lazily-resolved stub - if (GV->isExternal() && TM.AddressTaken.find(GV) != TM.AddressTaken.end()) { + if (GV->isExternal() && getTM().AddressTaken.count(GV)) { GVStubs.insert(Name); O << "L" << Name << "$non_lazy_ptr"; return; } - if (F && LoadAddrOp && TM.AddressTaken.find(GV) != TM.AddressTaken.end()) { + if (F && LoadAddrOp && getTM().AddressTaken.count(GV)) { LinkOnceStubs.insert(Name); O << "L" << Name << "$non_lazy_ptr"; return; @@ -626,11 +539,6 @@ return; } -bool PowerPCAsmPrinter::doInitialization(Module &M) { - Mang = new Mangler(M, true); - return false; // success -} - // SwitchSection - Switch to the specified section of the executable if we are // not already in it! // @@ -750,8 +658,6 @@ << "\t.long\t" << *i << '\n'; } - delete Mang; + AsmPrinter::doFinalization(M); return false; // success } - -} // End llvm namespace From lattner at cs.uiuc.edu Mon Aug 16 18:30:29 2004 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Mon, 16 Aug 2004 18:30:29 -0500 Subject: [llvm-commits] CVS: llvm/lib/Target/PowerPC/PPC32AsmPrinter.cpp Message-ID: <200408162330.SAA19812@apoc.cs.uiuc.edu> Changes in directory llvm/lib/Target/PowerPC: PPC32AsmPrinter.cpp updated: 1.42 -> 1.43 --- Log message: Minor changes to make the diff be nothing against the X86 version --- Diffs of the changes: (+4 -19) Index: llvm/lib/Target/PowerPC/PPC32AsmPrinter.cpp diff -u llvm/lib/Target/PowerPC/PPC32AsmPrinter.cpp:1.42 llvm/lib/Target/PowerPC/PPC32AsmPrinter.cpp:1.43 --- llvm/lib/Target/PowerPC/PPC32AsmPrinter.cpp:1.42 Mon Aug 16 18:25:21 2004 +++ llvm/lib/Target/PowerPC/PPC32AsmPrinter.cpp Mon Aug 16 18:30:16 2004 @@ -106,21 +106,6 @@ // Include the auto-generated portion of the assembly writer #include "PowerPCGenAsmWriter.inc" -/// isStringCompatible - Can we treat the specified array as a string? -/// Only if it is an array of ubytes or non-negative sbytes. -/// -static bool isStringCompatible(const ConstantArray *CVA) { - const Type *ETy = cast(CVA->getType())->getElementType(); - if (ETy == Type::UByteTy) return true; - if (ETy != Type::SByteTy) return false; - - for (unsigned i = 0; i < CVA->getNumOperands(); ++i) - if (cast(CVA->getOperand(i))->getValue() < 0) - return false; - - return true; -} - /// toOctal - Convert the low order bits of X into an octal digit. /// static inline char toOctal(int X) { @@ -128,13 +113,13 @@ } /// getAsCString - Return the specified array as a C compatible -/// string, only if the predicate isStringCompatible is true. +/// string, only if the predicate isString is true. /// static void printAsCString(std::ostream &O, const ConstantArray *CVA) { - assert(isStringCompatible(CVA) && "Array is not string compatible!"); + assert(CVA->isString() && "Array is not string compatible!"); O << "\""; - for (unsigned i = 0; i < CVA->getNumOperands(); ++i) { + for (unsigned i = 0; i != CVA->getNumOperands(); ++i) { unsigned char C = cast(CVA->getOperand(i))->getRawValue(); if (C == '"') { @@ -144,7 +129,7 @@ } else if (isprint(C)) { O << C; } else { - switch (C) { + switch(C) { case '\b': O << "\\b"; break; case '\f': O << "\\f"; break; case '\n': O << "\\n"; break; From lattner at cs.uiuc.edu Mon Aug 16 18:38:48 2004 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Mon, 16 Aug 2004 18:38:48 -0500 Subject: [llvm-commits] CVS: llvm/lib/Target/PowerPC/PPC32AsmPrinter.cpp Message-ID: <200408162338.SAA19847@apoc.cs.uiuc.edu> Changes in directory llvm/lib/Target/PowerPC: PPC32AsmPrinter.cpp updated: 1.43 -> 1.44 --- Log message: More changes to make PPC32 and X86 more similar --- Diffs of the changes: (+9 -11) Index: llvm/lib/Target/PowerPC/PPC32AsmPrinter.cpp diff -u llvm/lib/Target/PowerPC/PPC32AsmPrinter.cpp:1.43 llvm/lib/Target/PowerPC/PPC32AsmPrinter.cpp:1.44 --- llvm/lib/Target/PowerPC/PPC32AsmPrinter.cpp:1.43 Mon Aug 16 18:30:16 2004 +++ llvm/lib/Target/PowerPC/PPC32AsmPrinter.cpp Mon Aug 16 18:38:36 2004 @@ -152,13 +152,16 @@ void PowerPCAsmPrinter::emitGlobalConstant(const Constant *CV) { const TargetData &TD = TM.getTargetData(); - if (const ConstantArray *CVA = dyn_cast(CV)) { - if (isStringCompatible(CVA)) { - O << "\t.ascii "; + if (CV->isNullValue()) { + O << "\t.space\t" << TD.getTypeSize(CV->getType()) << "\n"; + return; + } else if (const ConstantArray *CVA = dyn_cast(CV)) { + if (CVA->isString()) { + O << "\t.ascii\t"; printAsCString(O, CVA); O << "\n"; } else { // Not a string. Print the values in successive locations - for (unsigned i=0, e = CVA->getNumOperands(); i != e; i++) + for (unsigned i = 0, e = CVA->getNumOperands(); i != e; ++i) emitGlobalConstant(CVA->getOperand(i)); } return; @@ -166,7 +169,7 @@ // Print the fields in successive locations. Pad to align if needed! const StructLayout *cvsLayout = TD.getStructLayout(CVS->getType()); unsigned sizeSoFar = 0; - for (unsigned i = 0, e = CVS->getNumOperands(); i != e; i++) { + for (unsigned i = 0, e = CVS->getNumOperands(); i != e; ++i) { const Constant* field = CVS->getOperand(i); // Check if padding is needed and insert one or more 0s. @@ -243,12 +246,7 @@ case Type::FloatTyID: case Type::DoubleTyID: assert (0 && "Should have already output floating point constant."); default: - if (CV == Constant::getNullValue(type)) { // Zero initializer? - O << ".space\t" << TD.getTypeSize(type) << "\n"; - return; - } - std::cerr << "Can't handle printing: " << *CV; - abort(); + assert (0 && "Can't handle printing this type of thing"); break; } O << "\t"; From reid at x10sys.com Mon Aug 16 19:49:13 2004 From: reid at x10sys.com (Reid Spencer) Date: Mon, 16 Aug 2004 19:49:13 -0500 Subject: [llvm-commits] CVS: llvm/docs/BytecodeFormat.html Message-ID: <200408170049.TAA00942@zion.cs.uiuc.edu> Changes in directory llvm/docs: BytecodeFormat.html updated: 1.25 -> 1.26 --- Log message: Technical Corrections (thanks to Robert Mykland): - Define the "opcode" data type and reference the Instruction.def file - Clean up the definition of symtab by indicating that it is composed of two llists. - Fix some broken links. --- Diffs of the changes: (+27 -19) Index: llvm/docs/BytecodeFormat.html diff -u llvm/docs/BytecodeFormat.html:1.25 llvm/docs/BytecodeFormat.html:1.26 --- llvm/docs/BytecodeFormat.html:1.25 Mon Aug 16 14:24:36 2004 +++ llvm/docs/BytecodeFormat.html Mon Aug 16 19:49:03 2004 @@ -255,6 +255,17 @@ bytes using the signed variable bit rate encoding. + opcode + An enumerated integer value used in the instruction + format that identifies the LLVM instruction opcode referenced. The + specific values used depend on the version of LLVM you're using. See the + + include/llvm/Instruction.def file for the definitive set of + opcode values used for your release. The opcode values are the first + argument to the various HANDLE_*_INST macros. + + char A single unsigned character encoded into one byte @@ -644,7 +655,7 @@ block - Module Symbol Table + Module Symbol Table @@ -1159,7 +1170,7 @@ block - The function's symbol + The function's symbol table containing only those symbols pertinent to the function (mostly block labels). @@ -1269,11 +1280,11 @@ depending on the number of operands to the instruction. Each instruction begins with a uint32_vbr that encodes the type of the instruction as well as other things. The tables -that follow describe the format of this first word of each instruction.

        +that follow describe the format of this first part of each instruction.

        Instruction Format 0

        This format is used for a few instructions that can't easily be -optimized because they have large numbers of operands (e.g. PHI Node or -getelementptr). Each of the opcode, type, and operand fields is as +shortened because they have large numbers of operands (e.g. PHI Node or +getelementptr). Each of the opcode, type, and operand fields is found in successive fields.

        @@ -1329,7 +1340,7 @@ - + @@ -1460,18 +1471,15 @@ - - - - - - + + - - + +
        2-7opcodeopcode Specifies the opcode of the instruction. Note that the maximum opcode value is 63.
        Symbol Table Identifier (0x04)
        uint32_vbrNumber of entries in type plane
        symtab_entry*Provides the slot number of the type and its -name.llist(symtab_entry)A length list of symbol table entries for + Types +
        symtab_plane*A type plane containing value slot number and -name for all values of the same type.llist(symtab_plane)A length list of planes of symbol table + entries for Values
        @@ -1520,8 +1528,8 @@ uint24_vbr - Slot number of the type or value being given -a name. + Slot number of the type or value being given a name. + uint32_vbr @@ -1648,7 +1656,7 @@ Reid Spencer and Chris Lattner
        The LLVM Compiler Infrastructure
        -Last modified: $Date: 2004/08/16 19:24:36 $ +Last modified: $Date: 2004/08/17 00:49:03 $ From lattner at cs.uiuc.edu Mon Aug 16 21:28:24 2004 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Mon, 16 Aug 2004 21:28:24 -0500 Subject: [llvm-commits] CVS: llvm/include/llvm/CodeGen/AsmPrinter.h Message-ID: <200408170228.VAA21484@apoc.cs.uiuc.edu> Changes in directory llvm/include/llvm/CodeGen: AsmPrinter.h updated: 1.1 -> 1.2 --- Log message: Some asmweriters want an _ prefix --- Diffs of the changes: (+9 -1) Index: llvm/include/llvm/CodeGen/AsmPrinter.h diff -u llvm/include/llvm/CodeGen/AsmPrinter.h:1.1 llvm/include/llvm/CodeGen/AsmPrinter.h:1.2 --- llvm/include/llvm/CodeGen/AsmPrinter.h:1.1 Mon Aug 16 18:15:20 2004 +++ llvm/include/llvm/CodeGen/AsmPrinter.h Mon Aug 16 21:28:12 2004 @@ -41,7 +41,15 @@ /// std::string CurrentFnName; - AsmPrinter(std::ostream &o, TargetMachine &tm) : O(o), TM(tm) { } + // Properties to be set by the derived class ctor, used to configure the + // asmwriter. + + /// UsesUnderscorePrefix - If this flag is set to true, all identifiers + /// printed by the asmwriter will include a '_' prefix. + bool UsesUnderscorePrefix; + + AsmPrinter(std::ostream &o, TargetMachine &tm) + : O(o), TM(tm), UsesUnderscorePrefix(false) { } /// doInitialization - Set up the AsmPrinter when we are working on a new /// module. If your pass overrides this, it must make sure to explicitly From lattner at cs.uiuc.edu Mon Aug 16 21:28:36 2004 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Mon, 16 Aug 2004 21:28:36 -0500 Subject: [llvm-commits] CVS: llvm/lib/CodeGen/AsmPrinter.cpp Message-ID: <200408170228.VAA21495@apoc.cs.uiuc.edu> Changes in directory llvm/lib/CodeGen: AsmPrinter.cpp updated: 1.1 -> 1.2 --- Log message: Some asmwriters want an _ prefix --- Diffs of the changes: (+1 -1) Index: llvm/lib/CodeGen/AsmPrinter.cpp diff -u llvm/lib/CodeGen/AsmPrinter.cpp:1.1 llvm/lib/CodeGen/AsmPrinter.cpp:1.2 --- llvm/lib/CodeGen/AsmPrinter.cpp:1.1 Mon Aug 16 18:15:22 2004 +++ llvm/lib/CodeGen/AsmPrinter.cpp Mon Aug 16 21:28:26 2004 @@ -19,7 +19,7 @@ using namespace llvm; bool AsmPrinter::doInitialization(Module &M) { - Mang = new Mangler(M); + Mang = new Mangler(M, UsesUnderscorePrefix); return false; } From lattner at cs.uiuc.edu Mon Aug 16 21:29:10 2004 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Mon, 16 Aug 2004 21:29:10 -0500 Subject: [llvm-commits] CVS: llvm/lib/Target/PowerPC/PPC32AsmPrinter.cpp Message-ID: <200408170229.VAA21503@apoc.cs.uiuc.edu> Changes in directory llvm/lib/Target/PowerPC: PPC32AsmPrinter.cpp updated: 1.44 -> 1.45 --- Log message: Make sure to put an _ prefix on all identifiers! Also, add some (currently disabled) code to print float's as 32-bits. --- Diffs of the changes: (+29 -16) Index: llvm/lib/Target/PowerPC/PPC32AsmPrinter.cpp diff -u llvm/lib/Target/PowerPC/PPC32AsmPrinter.cpp:1.44 llvm/lib/Target/PowerPC/PPC32AsmPrinter.cpp:1.45 --- llvm/lib/Target/PowerPC/PPC32AsmPrinter.cpp:1.44 Mon Aug 16 18:38:36 2004 +++ llvm/lib/Target/PowerPC/PPC32AsmPrinter.cpp Mon Aug 16 21:29:00 2004 @@ -46,7 +46,9 @@ std::set Strings; PowerPCAsmPrinter(std::ostream &O, TargetMachine &TM) - : AsmPrinter(O, TM), LabelNumber(0) {} + : AsmPrinter(O, TM), LabelNumber(0) { + UsesUnderscorePrefix = 1; + } /// Unique incrementer for label values for referencing Global values. /// @@ -193,21 +195,32 @@ // FP Constants are printed as integer constants to avoid losing // precision... double Val = CFP->getValue(); - union DU { // Abide by C TBAA rules - double FVal; - uint64_t UVal; - struct { - uint32_t MSWord; - uint32_t LSWord; - } T; - } U; - U.FVal = Val; - - O << ".long\t" << U.T.MSWord << "\t; double most significant word " - << Val << "\n"; - O << ".long\t" << U.T.LSWord << "\t; double least significant word " - << Val << "\n"; - return; + if (1 || CFP->getType() == Type::DoubleTy) { + union DU { // Abide by C TBAA rules + double FVal; + uint64_t UVal; + struct { + uint32_t MSWord; + uint32_t LSWord; + } T; + } U; + U.FVal = Val; + + O << ".long\t" << U.T.MSWord << "\t; double most significant word " + << Val << "\n"; + O << ".long\t" << U.T.LSWord << "\t; double least significant word " + << Val << "\n"; + return; + } else { + union FU { // Abide by C TBAA rules + float FVal; + int32_t UVal; + } U; + U.FVal = Val; + + O << ".long\t" << U.UVal << "\t; float " << Val << "\n"; + return; + } } else if (CV->getType() == Type::ULongTy || CV->getType() == Type::LongTy) { if (const ConstantInt *CI = dyn_cast(CV)) { union DU { // Abide by C TBAA rules From lattner at cs.uiuc.edu Mon Aug 16 21:48:57 2004 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Mon, 16 Aug 2004 21:48:57 -0500 Subject: [llvm-commits] CVS: llvm/lib/Target/PowerPC/PPC32AsmPrinter.cpp Message-ID: <200408170248.VAA22886@apoc.cs.uiuc.edu> Changes in directory llvm/lib/Target/PowerPC: PPC32AsmPrinter.cpp updated: 1.45 -> 1.46 --- Log message: Print float constants as 4 byte values. Also, fix endianness problems when cross compiling from little-endian host. --- Diffs of the changes: (+25 -22) Index: llvm/lib/Target/PowerPC/PPC32AsmPrinter.cpp diff -u llvm/lib/Target/PowerPC/PPC32AsmPrinter.cpp:1.45 llvm/lib/Target/PowerPC/PPC32AsmPrinter.cpp:1.46 --- llvm/lib/Target/PowerPC/PPC32AsmPrinter.cpp:1.45 Mon Aug 16 21:29:00 2004 +++ llvm/lib/Target/PowerPC/PPC32AsmPrinter.cpp Mon Aug 16 21:48:44 2004 @@ -195,21 +195,24 @@ // FP Constants are printed as integer constants to avoid losing // precision... double Val = CFP->getValue(); - if (1 || CFP->getType() == Type::DoubleTy) { + if (CFP->getType() == Type::DoubleTy) { union DU { // Abide by C TBAA rules double FVal; uint64_t UVal; - struct { - uint32_t MSWord; - uint32_t LSWord; - } T; } U; U.FVal = Val; - - O << ".long\t" << U.T.MSWord << "\t; double most significant word " - << Val << "\n"; - O << ".long\t" << U.T.LSWord << "\t; double least significant word " - << Val << "\n"; + + if (TD.isBigEndian()) { + O << ".long\t" << unsigned(U.UVal >> 32) + << "\t; double most significant word " << Val << "\n"; + O << ".long\t" << unsigned(U.UVal) + << "\t; double least significant word " << Val << "\n"; + } else { + O << ".long\t" << unsigned(U.UVal) + << "\t; double least significant word " << Val << "\n"; + O << ".long\t" << unsigned(U.UVal >> 32) + << "\t; double most significant word " << Val << "\n"; + } return; } else { union FU { // Abide by C TBAA rules @@ -223,19 +226,19 @@ } } else if (CV->getType() == Type::ULongTy || CV->getType() == Type::LongTy) { if (const ConstantInt *CI = dyn_cast(CV)) { - union DU { // Abide by C TBAA rules - int64_t UVal; - struct { - uint32_t MSWord; - uint32_t LSWord; - } T; - } U; - U.UVal = CI->getRawValue(); + uint64_t Val = CI->getRawValue(); - O << ".long\t" << U.T.MSWord << "\t; Double-word most significant word " - << U.UVal << "\n"; - O << ".long\t" << U.T.LSWord << "\t; Double-word least significant word " - << U.UVal << "\n"; + if (TD.isBigEndian()) { + O << ".long\t" << unsigned(Val >> 32) + << "\t; Double-word most significant word " << Val << "\n"; + O << ".long\t" << unsigned(Val) + << "\t; Double-word least significant word " << Val << "\n"; + } else { + O << ".long\t" << unsigned(Val) + << "\t; Double-word least significant word " << Val << "\n"; + O << ".long\t" << unsigned(Val >> 32) + << "\t; Double-word most significant word " << Val << "\n"; + } return; } } From reid at x10sys.com Mon Aug 16 21:59:13 2004 From: reid at x10sys.com (Reid Spencer) Date: Mon, 16 Aug 2004 21:59:13 -0500 Subject: [llvm-commits] CVS: llvm/lib/Bytecode/Writer/Writer.cpp Message-ID: <200408170259.VAA01915@zion.cs.uiuc.edu> Changes in directory llvm/lib/Bytecode/Writer: Writer.cpp updated: 1.73 -> 1.74 --- Log message: Correct the comments in the symbol table writer to reflect reality. --- Diffs of the changes: (+7 -3) Index: llvm/lib/Bytecode/Writer/Writer.cpp diff -u llvm/lib/Bytecode/Writer/Writer.cpp:1.73 llvm/lib/Bytecode/Writer/Writer.cpp:1.74 --- llvm/lib/Bytecode/Writer/Writer.cpp:1.73 Wed Aug 4 03:33:20 2004 +++ llvm/lib/Bytecode/Writer/Writer.cpp Mon Aug 16 21:59:02 2004 @@ -1041,11 +1041,13 @@ BytecodeBlock SymTabBlock(BytecodeFormat::SymbolTableBlockID, *this, true/* ElideIfEmpty*/); - //Symtab block header for types: [num entries] + // Write the number of types output_vbr(MST.num_types()); + + // Write each of the types for (SymbolTable::type_const_iterator TI = MST.type_begin(), TE = MST.type_end(); TI != TE; ++TI ) { - //Symtab entry:[def slot #][name] + // Symtab entry:[def slot #][name] output_typeid((unsigned)Table.getSlot(TI->second)); output(TI->first, /*align=*/false); } @@ -1059,13 +1061,15 @@ if (I == End) continue; // Don't mess with an absent type... - // Symtab block header: [num entries][type id number] + // Write the number of values in this plane output_vbr(MST.type_size(PI->first)); + // Write the slot number of the type for this plane Slot = Table.getSlot(PI->first); assert(Slot != -1 && "Type in symtab, but not in table!"); output_typeid((unsigned)Slot); + // Write each of the values in this plane for (; I != End; ++I) { // Symtab entry: [def slot #][name] Slot = Table.getSlot(I->second); From lattner at cs.uiuc.edu Mon Aug 16 22:08:40 2004 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Mon, 16 Aug 2004 22:08:40 -0500 Subject: [llvm-commits] CVS: llvm/utils/TableGen/AsmWriterEmitter.cpp CodeEmitterGen.cpp InstrInfoEmitter.cpp InstrSelectorEmitter.cpp RegisterInfoEmitter.cpp TableGenBackend.cpp TableGenBackend.h Message-ID: <200408170308.WAA25230@apoc.cs.uiuc.edu> Changes in directory llvm/utils/TableGen: AsmWriterEmitter.cpp updated: 1.6 -> 1.7 CodeEmitterGen.cpp updated: 1.36 -> 1.37 InstrInfoEmitter.cpp updated: 1.12 -> 1.13 InstrSelectorEmitter.cpp updated: 1.40 -> 1.41 RegisterInfoEmitter.cpp updated: 1.19 -> 1.20 TableGenBackend.cpp updated: 1.6 -> 1.7 TableGenBackend.h updated: 1.6 -> 1.7 --- Log message: Do not #include files into the llvm namespace --- Diffs of the changes: (+20 -18) Index: llvm/utils/TableGen/AsmWriterEmitter.cpp diff -u llvm/utils/TableGen/AsmWriterEmitter.cpp:1.6 llvm/utils/TableGen/AsmWriterEmitter.cpp:1.7 --- llvm/utils/TableGen/AsmWriterEmitter.cpp:1.6 Sat Aug 14 17:50:53 2004 +++ llvm/utils/TableGen/AsmWriterEmitter.cpp Mon Aug 16 22:08:27 2004 @@ -27,6 +27,7 @@ void AsmWriterEmitter::run(std::ostream &O) { EmitSourceFileHeader("Assembly Writer Source Fragment", O); + O << "namespace llvm {\n\n"; CodeGenTarget Target; @@ -103,5 +104,5 @@ O << " }\n" " return true;\n" "}\n"; - EmitSourceFileTail(O); + O << "} // End llvm namespace \n"; } Index: llvm/utils/TableGen/CodeEmitterGen.cpp diff -u llvm/utils/TableGen/CodeEmitterGen.cpp:1.36 llvm/utils/TableGen/CodeEmitterGen.cpp:1.37 --- llvm/utils/TableGen/CodeEmitterGen.cpp:1.36 Tue Aug 10 15:54:58 2004 +++ llvm/utils/TableGen/CodeEmitterGen.cpp Mon Aug 16 22:08:27 2004 @@ -24,6 +24,7 @@ std::vector Insts = Records.getAllDerivedDefinitions("Instruction"); EmitSourceFileHeader("Machine Code Emitter", o); + o << "namespace llvm {\n\n"; std::string Namespace = Insts[0]->getValueAsString("Namespace") + "::"; // Emit function declaration @@ -225,5 +226,5 @@ << " return Value;\n" << "}\n"; - EmitSourceFileTail(o); + o << "} // End llvm namespace \n"; } Index: llvm/utils/TableGen/InstrInfoEmitter.cpp diff -u llvm/utils/TableGen/InstrInfoEmitter.cpp:1.12 llvm/utils/TableGen/InstrInfoEmitter.cpp:1.13 --- llvm/utils/TableGen/InstrInfoEmitter.cpp:1.12 Sun Aug 1 03:38:17 2004 +++ llvm/utils/TableGen/InstrInfoEmitter.cpp Mon Aug 16 22:08:27 2004 @@ -20,6 +20,7 @@ // runEnums - Print out enum values for all of the instructions. void InstrInfoEmitter::runEnums(std::ostream &OS) { EmitSourceFileHeader("Target Instruction Enum Values", OS); + OS << "namespace llvm {\n\n"; CodeGenTarget Target; @@ -45,7 +46,7 @@ OS << " };\n"; if (!Namespace.empty()) OS << "}\n"; - EmitSourceFileTail(OS); + OS << "} // End llvm namespace \n"; } void InstrInfoEmitter::printDefList(ListInit *LI, const std::string &Name, @@ -63,6 +64,8 @@ // run - Emit the main instruction description records for the target... void InstrInfoEmitter::run(std::ostream &OS) { EmitSourceFileHeader("Target Instruction Descriptors", OS); + OS << "namespace llvm {\n\n"; + CodeGenTarget Target; const std::string &TargetName = Target.getName(); Record *InstrInfo = Target.getInstructionSet(); @@ -92,7 +95,7 @@ if (II->second.TheDef != PHI) emitRecord(II->second, ++i, InstrInfo, OS); OS << "};\n"; - EmitSourceFileTail(OS); + OS << "} // End llvm namespace \n"; } void InstrInfoEmitter::emitRecord(const CodeGenInstruction &Inst, unsigned Num, Index: llvm/utils/TableGen/InstrSelectorEmitter.cpp diff -u llvm/utils/TableGen/InstrSelectorEmitter.cpp:1.40 llvm/utils/TableGen/InstrSelectorEmitter.cpp:1.41 --- llvm/utils/TableGen/InstrSelectorEmitter.cpp:1.40 Sat Jul 31 23:04:35 2004 +++ llvm/utils/TableGen/InstrSelectorEmitter.cpp Mon Aug 16 22:08:27 2004 @@ -982,6 +982,7 @@ EmitSourceFileHeader("Instruction Selector for the " + Target.getName() + " target", OS); + OS << "namespace llvm {\n\n"; // Output the slot number enums... OS << "\nenum { // Slot numbers...\n" @@ -1291,6 +1292,5 @@ << " }\n\n N->addValue(Val); // Do not ever recalculate this\n" << " return Val;\n}\n\n"; } - EmitSourceFileTail(OS); + OS << "} // End llvm namespace \n"; } - Index: llvm/utils/TableGen/RegisterInfoEmitter.cpp diff -u llvm/utils/TableGen/RegisterInfoEmitter.cpp:1.19 llvm/utils/TableGen/RegisterInfoEmitter.cpp:1.20 --- llvm/utils/TableGen/RegisterInfoEmitter.cpp:1.19 Sun Aug 15 20:10:21 2004 +++ llvm/utils/TableGen/RegisterInfoEmitter.cpp Mon Aug 16 22:08:28 2004 @@ -29,6 +29,7 @@ std::string Namespace = Registers[0].TheDef->getValueAsString("Namespace"); EmitSourceFileHeader("Target Register Enum Values", OS); + OS << "namespace llvm {\n\n"; if (!Namespace.empty()) OS << "namespace " << Namespace << " {\n"; @@ -40,7 +41,7 @@ OS << " };\n"; if (!Namespace.empty()) OS << "}\n"; - EmitSourceFileTail(OS); + OS << "} // End llvm namespace \n"; } void RegisterInfoEmitter::runHeader(std::ostream &OS) { @@ -51,6 +52,8 @@ OS << "#include \"llvm/Target/MRegisterInfo.h\"\n\n"; + OS << "namespace llvm {\n\n"; + OS << "struct " << ClassName << " : public MRegisterInfo {\n" << " " << ClassName << "(int CallFrameSetupOpcode = -1, int CallFrameDestroyOpcode = -1);\n" @@ -67,7 +70,7 @@ OS << " extern TargetRegisterClass *" << Name << "RegisterClass;\n"; } OS << "} // end of namespace " << TargetName << "\n\n"; - EmitSourceFileTail(OS); + OS << "} // End llvm namespace \n"; } // RegisterInfoEmitter::run - Main register file description emitter. @@ -76,6 +79,8 @@ CodeGenTarget Target; EmitSourceFileHeader("Register Information Source Fragment", OS); + OS << "namespace llvm {\n\n"; + // Start out by emitting each of the register classes... to do this, we build // a set of registers which belong to a register class, this is to ensure that // each register is only in a single register class. @@ -236,5 +241,5 @@ for (unsigned i = 0, e = CSR.size(); i != e; ++i) OS << getQualifiedName(CSR[i]) << ", "; OS << " 0\n };\n return CalleeSaveRegs;\n}\n\n"; - EmitSourceFileTail(OS); + OS << "} // End llvm namespace \n"; } Index: llvm/utils/TableGen/TableGenBackend.cpp diff -u llvm/utils/TableGen/TableGenBackend.cpp:1.6 llvm/utils/TableGen/TableGenBackend.cpp:1.7 --- llvm/utils/TableGen/TableGenBackend.cpp:1.6 Sat Jul 31 22:55:39 2004 +++ llvm/utils/TableGen/TableGenBackend.cpp Mon Aug 16 22:08:28 2004 @@ -21,11 +21,7 @@ OS << "//===- TableGen'erated file -------------------------------------*-" " C++ -*-===//\n//\n// " << Desc << "\n//\n// Automatically generate" "d file, do not edit!\n//\n//===------------------------------------" - "----------------------------------===//\n\nnamespace llvm {\n\n"; -} - -void TableGenBackend::EmitSourceFileTail( std::ostream& OS ) const { - OS << "} // End llvm namespace \n"; + "----------------------------------===//\n\n"; } /// getQualifiedName - Return the name of the specified record, with a Index: llvm/utils/TableGen/TableGenBackend.h diff -u llvm/utils/TableGen/TableGenBackend.h:1.6 llvm/utils/TableGen/TableGenBackend.h:1.7 --- llvm/utils/TableGen/TableGenBackend.h:1.6 Tue Nov 11 16:41:34 2003 +++ llvm/utils/TableGen/TableGenBackend.h Mon Aug 16 22:08:28 2004 @@ -36,10 +36,6 @@ /// ostream. void EmitSourceFileHeader(const std::string &Desc, std::ostream &OS) const; - /// EmitSourceFileTail - Output an LLVm styelf ile tail to the specified - /// ostream. - void EmitSourceFileTail( std::ostream& OS ) const; - /// getQualifiedName - Return the name of the specified record, with a /// namespace qualifier if the record contains one. std::string getQualifiedName(Record *R) const; From brukman at cs.uiuc.edu Mon Aug 16 23:55:51 2004 From: brukman at cs.uiuc.edu (Misha Brukman) Date: Mon, 16 Aug 2004 23:55:51 -0500 Subject: [llvm-commits] CVS: llvm/lib/Target/PowerPC/PPC32.td PPC32InstrInfo.cpp PPC32InstrInfo.h PPC32RegisterInfo.cpp PPC32RegisterInfo.h PPC32RegisterInfo.td PPC32AsmPrinter.cpp PPC32ISelSimple.cpp PPC32TargetMachine.h Message-ID: <200408170455.XAA03366@zion.cs.uiuc.edu> Changes in directory llvm/lib/Target/PowerPC: PPC32.td added (r1.1) PPC32InstrInfo.cpp added (r1.1) PPC32InstrInfo.h added (r1.1) PPC32RegisterInfo.cpp added (r1.1) PPC32RegisterInfo.h added (r1.1) PPC32RegisterInfo.td added (r1.1) PPC32AsmPrinter.cpp updated: 1.46 -> 1.47 PPC32ISelSimple.cpp updated: 1.66 -> 1.67 PPC32TargetMachine.h updated: 1.3 -> 1.4 --- Log message: PowerPC 32-/64-bit split: Part I, PPC32* bit files, adapted from former PowerPC* --- Diffs of the changes: (+616 -40) Index: llvm/lib/Target/PowerPC/PPC32.td diff -c /dev/null llvm/lib/Target/PowerPC/PPC32.td:1.1 *** /dev/null Mon Aug 16 23:55:51 2004 --- llvm/lib/Target/PowerPC/PPC32.td Mon Aug 16 23:55:41 2004 *************** *** 0 **** --- 1,45 ---- + //===- PPC32.td - Describe the PowerPC Target Machine ------*- tablegen -*-===// + // + // The LLVM Compiler Infrastructure + // + // This file was developed by the LLVM research group and is distributed under + // the University of Illinois Open Source License. See LICENSE.TXT for details. + // + //===----------------------------------------------------------------------===// + // + // + //===----------------------------------------------------------------------===// + + // Get the target-independent interfaces which we are implementing... + // + include "../Target.td" + + //===----------------------------------------------------------------------===// + // Register File Description + //===----------------------------------------------------------------------===// + + include "PPC32RegisterInfo.td" + include "PowerPCInstrInfo.td" + + def PowerPCInstrInfo : InstrInfo { + let PHIInst = PHI; + + let TSFlagsFields = ["ArgCount", "Arg0Type", "Arg1Type", "Arg2Type", + "Arg3Type", "Arg4Type", "VMX", "PPC64"]; + let TSFlagsShifts = [ 0, 3, 8, 13, 18, 23, 28, 29 ]; + } + + def PPC32 : Target { + // Pointers on PPC32 are 32-bits in size. + let PointerType = i32; + + // According to the Mach-O Runtime ABI, these regs are nonvolatile across + // calls + let CalleeSavedRegisters = [R1, R13, R14, R15, R16, R17, R18, R19, + R20, R21, R22, R23, R24, R25, R26, R27, R28, R29, R30, R31, F14, F15, + F16, F17, F18, F19, F20, F21, F22, F23, F24, F25, F26, F27, F28, F29, + F30, F31, CR2, CR3, CR4, LR]; + + // Pull in Instruction Info: + let InstructionSet = PowerPCInstrInfo; + } Index: llvm/lib/Target/PowerPC/PPC32InstrInfo.cpp diff -c /dev/null llvm/lib/Target/PowerPC/PPC32InstrInfo.cpp:1.1 *** /dev/null Mon Aug 16 23:55:51 2004 --- llvm/lib/Target/PowerPC/PPC32InstrInfo.cpp Mon Aug 16 23:55:41 2004 *************** *** 0 **** --- 1,59 ---- + //===- PPC32InstrInfo.cpp - PowerPC32 Instruction Information ---*- C++ -*-===// + // + // The LLVM Compiler Infrastructure + // + // This file was developed by the LLVM research group and is distributed under + // the University of Illinois Open Source License. See LICENSE.TXT for details. + // + //===----------------------------------------------------------------------===// + // + // This file contains the PowerPC implementation of the TargetInstrInfo class. + // + //===----------------------------------------------------------------------===// + + #include "PPC32InstrInfo.h" + #include "PPC32GenInstrInfo.inc" + #include "PowerPC.h" + #include "llvm/CodeGen/MachineInstrBuilder.h" + #include + using namespace llvm; + + PPC32InstrInfo::PPC32InstrInfo() + : TargetInstrInfo(PPC32Insts, sizeof(PPC32Insts)/sizeof(PPC32Insts[0])) {} + + bool PPC32InstrInfo::isMoveInstr(const MachineInstr& MI, + unsigned& sourceReg, + unsigned& destReg) const { + MachineOpCode oc = MI.getOpcode(); + if (oc == PPC::OR) { // or r1, r2, r2 + assert(MI.getNumOperands() == 3 && + MI.getOperand(0).isRegister() && + MI.getOperand(1).isRegister() && + MI.getOperand(2).isRegister() && + "invalid PPC OR instruction!"); + if (MI.getOperand(1).getReg() == MI.getOperand(2).getReg()) { + sourceReg = MI.getOperand(1).getReg(); + destReg = MI.getOperand(0).getReg(); + return true; + } + } else if (oc == PPC::ADDI) { // addi r1, r2, 0 + assert(MI.getNumOperands() == 3 && + MI.getOperand(0).isRegister() && + MI.getOperand(2).isImmediate() && + "invalid PPC ADDI instruction!"); + if (MI.getOperand(1).isRegister() && MI.getOperand(2).getImmedValue()==0) { + sourceReg = MI.getOperand(1).getReg(); + destReg = MI.getOperand(0).getReg(); + return true; + } + } else if (oc == PPC::FMR) { // fmr r1, r2 + assert(MI.getNumOperands() == 2 && + MI.getOperand(0).isRegister() && + MI.getOperand(1).isRegister() && + "invalid PPC FMR instruction"); + sourceReg = MI.getOperand(1).getReg(); + destReg = MI.getOperand(0).getReg(); + return true; + } + return false; + } Index: llvm/lib/Target/PowerPC/PPC32InstrInfo.h diff -c /dev/null llvm/lib/Target/PowerPC/PPC32InstrInfo.h:1.1 *** /dev/null Mon Aug 16 23:55:51 2004 --- llvm/lib/Target/PowerPC/PPC32InstrInfo.h Mon Aug 16 23:55:41 2004 *************** *** 0 **** --- 1,56 ---- + //===- PPC32InstrInfo.h - PowerPC32 Instruction Information -----*- C++ -*-===// + // + // The LLVM Compiler Infrastructure + // + // This file was developed by the LLVM research group and is distributed under + // the University of Illinois Open Source License. See LICENSE.TXT for details. + // + //===----------------------------------------------------------------------===// + // + // This file contains the PowerPC implementation of the TargetInstrInfo class. + // + //===----------------------------------------------------------------------===// + + #ifndef POWERPC32_INSTRUCTIONINFO_H + #define POWERPC32_INSTRUCTIONINFO_H + + #include "PowerPCInstrInfo.h" + #include "PPC32RegisterInfo.h" + + namespace llvm { + + class PPC32InstrInfo : public TargetInstrInfo { + const PPC32RegisterInfo RI; + public: + PPC32InstrInfo(); + + /// getRegisterInfo - TargetInstrInfo is a superset of MRegister info. As + /// such, whenever a client has an instance of instruction info, it should + /// always be able to get register info as well (through this method). + /// + virtual const MRegisterInfo &getRegisterInfo() const { return RI; } + + // + // Return true if the instruction is a register to register move and + // leave the source and dest operands in the passed parameters. + // + virtual bool isMoveInstr(const MachineInstr& MI, + unsigned& sourceReg, + unsigned& destReg) const; + + static unsigned invertPPCBranchOpcode(unsigned Opcode) { + switch (Opcode) { + default: assert(0 && "Unknown PPC branch opcode!"); + case PPC::BEQ: return PPC::BNE; + case PPC::BNE: return PPC::BEQ; + case PPC::BLT: return PPC::BGE; + case PPC::BGE: return PPC::BLT; + case PPC::BGT: return PPC::BLE; + case PPC::BLE: return PPC::BGT; + } + } + }; + + } + + #endif Index: llvm/lib/Target/PowerPC/PPC32RegisterInfo.cpp diff -c /dev/null llvm/lib/Target/PowerPC/PPC32RegisterInfo.cpp:1.1 *** /dev/null Mon Aug 16 23:55:51 2004 --- llvm/lib/Target/PowerPC/PPC32RegisterInfo.cpp Mon Aug 16 23:55:41 2004 *************** *** 0 **** --- 1,316 ---- + //===- PPC32RegisterInfo.cpp - PowerPC32 Register Information ---*- C++ -*-===// + // + // The LLVM Compiler Infrastructure + // + // This file was developed by the LLVM research group and is distributed under + // the University of Illinois Open Source License. See LICENSE.TXT for details. + // + //===----------------------------------------------------------------------===// + // + // This file contains the PowerPC32 implementation of the MRegisterInfo class. + // + //===----------------------------------------------------------------------===// + + #define DEBUG_TYPE "reginfo" + #include "PowerPC.h" + #include "PowerPCInstrBuilder.h" + #include "PPC32RegisterInfo.h" + #include "llvm/Constants.h" + #include "llvm/Type.h" + #include "llvm/CodeGen/ValueTypes.h" + #include "llvm/CodeGen/MachineInstrBuilder.h" + #include "llvm/CodeGen/MachineFunction.h" + #include "llvm/CodeGen/MachineFrameInfo.h" + #include "llvm/Target/TargetFrameInfo.h" + #include "llvm/Target/TargetMachine.h" + #include "llvm/Target/TargetOptions.h" + #include "Support/CommandLine.h" + #include "Support/Debug.h" + #include "Support/STLExtras.h" + #include + #include + using namespace llvm; + + namespace llvm { + // Switch toggling compilation for AIX + extern cl::opt AIX; + } + + PPC32RegisterInfo::PPC32RegisterInfo() + : PPC32GenRegisterInfo(PPC::ADJCALLSTACKDOWN, PPC::ADJCALLSTACKUP) { + ImmToIdxMap[PPC::LD] = PPC::LDX; ImmToIdxMap[PPC::STD] = PPC::STDX; + ImmToIdxMap[PPC::LBZ] = PPC::LBZX; ImmToIdxMap[PPC::STB] = PPC::STBX; + ImmToIdxMap[PPC::LHZ] = PPC::LHZX; ImmToIdxMap[PPC::LHA] = PPC::LHAX; + ImmToIdxMap[PPC::LWZ] = PPC::LWZX; ImmToIdxMap[PPC::LWA] = PPC::LWAX; + ImmToIdxMap[PPC::LFS] = PPC::LFSX; ImmToIdxMap[PPC::LFD] = PPC::LFDX; + ImmToIdxMap[PPC::STH] = PPC::STHX; ImmToIdxMap[PPC::STW] = PPC::STWX; + ImmToIdxMap[PPC::STFS] = PPC::STFSX; ImmToIdxMap[PPC::STFD] = PPC::STFDX; + ImmToIdxMap[PPC::ADDI] = PPC::ADD; + } + + static unsigned getIdx(const TargetRegisterClass *RC) { + if (RC == PPC32::GPRCRegisterClass) { + switch (RC->getSize()) { + default: assert(0 && "Invalid data size!"); + case 1: return 0; + case 2: return 1; + case 4: return 2; + } + } else if (RC == PPC32::FPRCRegisterClass) { + switch (RC->getSize()) { + default: assert(0 && "Invalid data size!"); + case 4: return 3; + case 8: return 4; + } + } + std::cerr << "Invalid register class to getIdx()!\n"; + abort(); + } + + void + PPC32RegisterInfo::storeRegToStackSlot(MachineBasicBlock &MBB, + MachineBasicBlock::iterator MI, + unsigned SrcReg, int FrameIdx) const { + const TargetRegisterClass *RC = getRegClass(SrcReg); + static const unsigned Opcode[] = { + PPC::STB, PPC::STH, PPC::STW, PPC::STFS, PPC::STFD + }; + + unsigned OC = Opcode[getIdx(RC)]; + if (SrcReg == PPC::LR) { + BuildMI(MBB, MI, PPC::MFLR, 0, PPC::R11); + BuildMI(MBB, MI, PPC::IMPLICIT_DEF, 0, PPC::R0); + addFrameReference(BuildMI(MBB, MI, OC, 3).addReg(PPC::R11),FrameIdx); + } else { + BuildMI(MBB, MI, PPC::IMPLICIT_DEF, 0, PPC::R0); + addFrameReference(BuildMI(MBB, MI, OC, 3).addReg(SrcReg),FrameIdx); + } + } + + void + PPC32RegisterInfo::loadRegFromStackSlot(MachineBasicBlock &MBB, + MachineBasicBlock::iterator MI, + unsigned DestReg, int FrameIdx) const{ + static const unsigned Opcode[] = { + PPC::LBZ, PPC::LHZ, PPC::LWZ, PPC::LFS, PPC::LFD + }; + const TargetRegisterClass *RC = getRegClass(DestReg); + unsigned OC = Opcode[getIdx(RC)]; + if (DestReg == PPC::LR) { + BuildMI(MBB, MI, PPC::IMPLICIT_DEF, 0, PPC::R0); + addFrameReference(BuildMI(MBB, MI, OC, 2, PPC::R11), FrameIdx); + BuildMI(MBB, MI, PPC::MTLR, 1).addReg(PPC::R11); + } else { + BuildMI(MBB, MI, PPC::IMPLICIT_DEF, 0, PPC::R0); + addFrameReference(BuildMI(MBB, MI, OC, 2, DestReg), FrameIdx); + } + } + + void PPC32RegisterInfo::copyRegToReg(MachineBasicBlock &MBB, + MachineBasicBlock::iterator MI, + unsigned DestReg, unsigned SrcReg, + const TargetRegisterClass *RC) const { + MachineInstr *I; + + if (RC == PPC32::GPRCRegisterClass) { + BuildMI(MBB, MI, PPC::OR, 2, DestReg).addReg(SrcReg).addReg(SrcReg); + } else if (RC == PPC32::FPRCRegisterClass) { + BuildMI(MBB, MI, PPC::FMR, 1, DestReg).addReg(SrcReg); + } else { + std::cerr << "Attempt to copy register that is not GPR or FPR"; + abort(); + } + } + + //===----------------------------------------------------------------------===// + // Stack Frame Processing methods + //===----------------------------------------------------------------------===// + + // hasFP - Return true if the specified function should have a dedicated frame + // pointer register. This is true if the function has variable sized allocas or + // if frame pointer elimination is disabled. + // + static bool hasFP(MachineFunction &MF) { + MachineFrameInfo *MFI = MF.getFrameInfo(); + return MFI->hasVarSizedObjects(); + } + + void PPC32RegisterInfo:: + eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB, + MachineBasicBlock::iterator I) const { + if (hasFP(MF)) { + // If we have a frame pointer, convert as follows: + // ADJCALLSTACKDOWN -> addi, r1, r1, -amount + // ADJCALLSTACKUP -> addi, r1, r1, amount + MachineInstr *Old = I; + unsigned Amount = Old->getOperand(0).getImmedValue(); + if (Amount != 0) { + // We need to keep the stack aligned properly. To do this, we round the + // amount of space needed for the outgoing arguments up to the next + // alignment boundary. + unsigned Align = MF.getTarget().getFrameInfo()->getStackAlignment(); + Amount = (Amount+Align-1)/Align*Align; + + // Replace the pseudo instruction with a new instruction... + if (Old->getOpcode() == PPC::ADJCALLSTACKDOWN) { + MBB.insert(I, BuildMI(PPC::ADDI, 2, PPC::R1).addReg(PPC::R1) + .addSImm(-Amount)); + } else { + assert(Old->getOpcode() == PPC::ADJCALLSTACKUP); + MBB.insert(I, BuildMI(PPC::ADDI, 2, PPC::R1).addReg(PPC::R1) + .addSImm(Amount)); + } + } + } + MBB.erase(I); + } + + void + PPC32RegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II) const { + unsigned i = 0; + MachineInstr &MI = *II; + MachineBasicBlock &MBB = *MI.getParent(); + MachineFunction &MF = *MBB.getParent(); + + while (!MI.getOperand(i).isFrameIndex()) { + ++i; + assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!"); + } + + int FrameIndex = MI.getOperand(i).getFrameIndex(); + + // Replace the FrameIndex with base register with GPR1 (SP) or GPR31 (FP). + MI.SetMachineOperandReg(i, hasFP(MF) ? PPC::R31 : PPC::R1); + + // Take into account whether it's an add or mem instruction + unsigned OffIdx = (i == 2) ? 1 : 2; + + // Now add the frame object offset to the offset from r1. + int Offset = MF.getFrameInfo()->getObjectOffset(FrameIndex) + + MI.getOperand(OffIdx).getImmedValue(); + + // If we're not using a Frame Pointer that has been set to the value of the + // SP before having the stack size subtracted from it, then add the stack size + // to Offset to get the correct offset. + Offset += MF.getFrameInfo()->getStackSize(); + + if (Offset > 32767 || Offset < -32768) { + // Insert a set of r0 with the full offset value before the ld, st, or add + MachineBasicBlock *MBB = MI.getParent(); + MBB->insert(II, BuildMI(PPC::LIS, 1, PPC::R0).addSImm(Offset >> 16)); + MBB->insert(II, BuildMI(PPC::ORI, 2, PPC::R0).addReg(PPC::R0) + .addImm(Offset)); + // convert into indexed form of the instruction + // sth 0:rA, 1:imm 2:(rB) ==> sthx 0:rA, 2:rB, 1:r0 + // addi 0:rA 1:rB, 2, imm ==> add 0:rA, 1:rB, 2:r0 + unsigned NewOpcode = const_cast& >(ImmToIdxMap)[MI.getOpcode()]; + assert(NewOpcode && "No indexed form of load or store available!"); + MI.setOpcode(NewOpcode); + MI.SetMachineOperandReg(1, MI.getOperand(i).getReg()); + MI.SetMachineOperandReg(2, PPC::R0); + } else { + MI.SetMachineOperandConst(OffIdx,MachineOperand::MO_SignExtendedImmed,Offset); + } + } + + + void PPC32RegisterInfo::emitPrologue(MachineFunction &MF) const { + MachineBasicBlock &MBB = MF.front(); // Prolog goes in entry BB + MachineBasicBlock::iterator MBBI = MBB.begin(); + MachineFrameInfo *MFI = MF.getFrameInfo(); + MachineInstr *MI; + + // Get the number of bytes to allocate from the FrameInfo + unsigned NumBytes = MFI->getStackSize(); + + // If we have calls, we cannot use the red zone to store callee save registers + // and we must set up a stack frame, so calculate the necessary size here. + if (MFI->hasCalls()) { + // We reserve argument space for call sites in the function immediately on + // entry to the current function. This eliminates the need for add/sub + // brackets around call sites. + NumBytes += MFI->getMaxCallFrameSize(); + } + + // Do we need to allocate space on the stack? + if (NumBytes == 0) return; + + // Add the size of R1 to NumBytes size for the store of R1 to the bottom + // of the stack and round the size to a multiple of the alignment. + unsigned Align = MF.getTarget().getFrameInfo()->getStackAlignment(); + unsigned R1Size = getRegClass(PPC::R1)->getSize(); + unsigned R31Size = getRegClass(PPC::R31)->getSize(); + unsigned Size = (hasFP(MF)) ? R1Size + R31Size : R1Size; + NumBytes = (NumBytes+Size+Align-1)/Align*Align; + + // Update frame info to pretend that this is part of the stack... + MFI->setStackSize(NumBytes); + + // adjust stack pointer: r1 -= numbytes + if (NumBytes <= 32768) { + MI=BuildMI(PPC::STWU,3).addReg(PPC::R1).addSImm(-NumBytes).addReg(PPC::R1); + MBB.insert(MBBI, MI); + } else { + int NegNumbytes = -NumBytes; + MI = BuildMI(PPC::LIS, 1, PPC::R0).addSImm(NegNumbytes >> 16); + MBB.insert(MBBI, MI); + MI = BuildMI(PPC::ORI, 2, PPC::R0).addReg(PPC::R0) + .addImm(NegNumbytes & 0xFFFF); + MBB.insert(MBBI, MI); + MI = BuildMI(PPC::STWUX, 3).addReg(PPC::R1).addReg(PPC::R1).addReg(PPC::R0); + MBB.insert(MBBI, MI); + } + + if (hasFP(MF)) { + MI = BuildMI(PPC::STW, 3).addReg(PPC::R31).addSImm(R1Size).addReg(PPC::R1); + MBB.insert(MBBI, MI); + MI = BuildMI(PPC::OR, 2, PPC::R31).addReg(PPC::R1).addReg(PPC::R1); + MBB.insert(MBBI, MI); + } + } + + void PPC32RegisterInfo::emitEpilogue(MachineFunction &MF, + MachineBasicBlock &MBB) const { + const MachineFrameInfo *MFI = MF.getFrameInfo(); + MachineBasicBlock::iterator MBBI = prior(MBB.end()); + MachineInstr *MI; + assert(MBBI->getOpcode() == PPC::BLR && + "Can only insert epilog into returning blocks"); + + // Get the number of bytes allocated from the FrameInfo... + unsigned NumBytes = MFI->getStackSize(); + + if (NumBytes != 0) { + if (hasFP(MF)) { + MI = BuildMI(PPC::OR, 2, PPC::R1).addReg(PPC::R31).addReg(PPC::R31); + MBB.insert(MBBI, MI); + MI = BuildMI(PPC::LWZ, 2, PPC::R31).addSImm(4).addReg(PPC::R31); + MBB.insert(MBBI, MI); + } + MI = BuildMI(PPC::LWZ, 2, PPC::R1).addSImm(0).addReg(PPC::R1); + MBB.insert(MBBI, MI); + } + } + + #include "PPC32GenRegisterInfo.inc" + + const TargetRegisterClass* + PPC32RegisterInfo::getRegClassForType(const Type* Ty) const { + switch (Ty->getTypeID()) { + default: assert(0 && "Invalid type to getClass!"); + case Type::LongTyID: + case Type::ULongTyID: assert(0 && "Long values can't fit in registers!"); + case Type::BoolTyID: + case Type::SByteTyID: + case Type::UByteTyID: + case Type::ShortTyID: + case Type::UShortTyID: + case Type::IntTyID: + case Type::UIntTyID: + case Type::PointerTyID: return &GPRCInstance; + + case Type::FloatTyID: + case Type::DoubleTyID: return &FPRCInstance; + } + } + Index: llvm/lib/Target/PowerPC/PPC32RegisterInfo.h diff -c /dev/null llvm/lib/Target/PowerPC/PPC32RegisterInfo.h:1.1 *** /dev/null Mon Aug 16 23:55:51 2004 --- llvm/lib/Target/PowerPC/PPC32RegisterInfo.h Mon Aug 16 23:55:41 2004 *************** *** 0 **** --- 1,56 ---- + //===- PPC32RegisterInfo.h - PowerPC32 Register Information Impl -*- C++ -*-==// + // + // The LLVM Compiler Infrastructure + // + // This file was developed by the LLVM research group and is distributed under + // the University of Illinois Open Source License. See LICENSE.TXT for details. + // + //===----------------------------------------------------------------------===// + // + // This file contains the PowerPC implementation of the MRegisterInfo class. + // + //===----------------------------------------------------------------------===// + + #ifndef POWERPC32_REGISTERINFO_H + #define POWERPC32_REGISTERINFO_H + + #include "PowerPC.h" + #include "PPC32GenRegisterInfo.h.inc" + #include + + namespace llvm { + + class Type; + + class PPC32RegisterInfo : public PPC32GenRegisterInfo { + std::map ImmToIdxMap; + public: + PPC32RegisterInfo(); + const TargetRegisterClass* getRegClassForType(const Type* Ty) const; + + /// Code Generation virtual methods... + void storeRegToStackSlot(MachineBasicBlock &MBB, + MachineBasicBlock::iterator MBBI, + unsigned SrcReg, int FrameIndex) const; + + void loadRegFromStackSlot(MachineBasicBlock &MBB, + MachineBasicBlock::iterator MBBI, + unsigned DestReg, int FrameIndex) const; + + void copyRegToReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, + unsigned DestReg, unsigned SrcReg, + const TargetRegisterClass *RC) const; + + void eliminateCallFramePseudoInstr(MachineFunction &MF, + MachineBasicBlock &MBB, + MachineBasicBlock::iterator I) const; + + void eliminateFrameIndex(MachineBasicBlock::iterator II) const; + + void emitPrologue(MachineFunction &MF) const; + void emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const; + }; + + } // end namespace llvm + + #endif Index: llvm/lib/Target/PowerPC/PPC32RegisterInfo.td diff -c /dev/null llvm/lib/Target/PowerPC/PPC32RegisterInfo.td:1.1 *** /dev/null Mon Aug 16 23:55:51 2004 --- llvm/lib/Target/PowerPC/PPC32RegisterInfo.td Mon Aug 16 23:55:41 2004 *************** *** 0 **** --- 1,40 ---- + //===- PPC32RegisterInfo.td - The PowerPC32 Register File --*- tablegen -*-===// + // + // The LLVM Compiler Infrastructure + // + // This file was developed by the LLVM research group and is distributed under + // the University of Illinois Open Source License. See LICENSE.TXT for details. + // + //===----------------------------------------------------------------------===// + // + // + //===----------------------------------------------------------------------===// + + include "PowerPCRegisterInfo.td" + + /// Register classes + // Allocate volatiles first + // then nonvolatiles in reverse order since stmw/lmw save from rN to r31 + def GPRC : RegisterClass + { + let Methods = [{ + iterator allocation_order_begin(MachineFunction &MF) const { + return begin() + (AIX ? 1 : 0); + } + iterator allocation_order_end(MachineFunction &MF) const { + if (hasFP(MF)) + return end()-4; + else + return end()-3; + } + }]; + } + + def FPRC : RegisterClass; + + def CRRC : RegisterClass; Index: llvm/lib/Target/PowerPC/PPC32AsmPrinter.cpp diff -u llvm/lib/Target/PowerPC/PPC32AsmPrinter.cpp:1.46 llvm/lib/Target/PowerPC/PPC32AsmPrinter.cpp:1.47 --- llvm/lib/Target/PowerPC/PPC32AsmPrinter.cpp:1.46 Mon Aug 16 21:48:44 2004 +++ llvm/lib/Target/PowerPC/PPC32AsmPrinter.cpp Mon Aug 16 23:55:41 2004 @@ -18,8 +18,7 @@ #define DEBUG_TYPE "asmprinter" #include "PowerPC.h" -#include "PowerPCInstrInfo.h" -#include "PowerPCTargetMachine.h" +#include "PPC32TargetMachine.h" #include "llvm/Constants.h" #include "llvm/DerivedTypes.h" #include "llvm/Module.h" @@ -29,7 +28,6 @@ #include "llvm/CodeGen/MachineFunctionPass.h" #include "llvm/CodeGen/MachineInstr.h" #include "llvm/CodeGen/ValueTypes.h" -#include "llvm/Target/TargetMachine.h" #include "llvm/Support/Mangler.h" #include "Support/CommandLine.h" #include "Support/Debug.h" @@ -41,11 +39,11 @@ namespace { Statistic<> EmittedInsts("asm-printer", "Number of machine instrs printed"); - struct PowerPCAsmPrinter : public AsmPrinter { + struct PPC32AsmPrinter : public AsmPrinter { std::set FnStubs, GVStubs, LinkOnceStubs; std::set Strings; - PowerPCAsmPrinter(std::ostream &O, TargetMachine &TM) + PPC32AsmPrinter(std::ostream &O, TargetMachine &TM) : AsmPrinter(O, TM), LabelNumber(0) { UsesUnderscorePrefix = 1; } @@ -55,11 +53,11 @@ unsigned LabelNumber; virtual const char *getPassName() const { - return "PowerPC Assembly Printer"; + return "PPC32 Assembly Printer"; } - PowerPCTargetMachine &getTM() { - return static_cast(TM); + PPC32TargetMachine &getTM() { + return static_cast(TM); } /// printInstruction - This method is automatically generated by tablegen @@ -101,8 +99,8 @@ /// using the given target machine description. This should work /// regardless of whether the function is in SSA form or not. /// -FunctionPass *llvm::createPPCAsmPrinter(std::ostream &o,TargetMachine &tm) { - return new PowerPCAsmPrinter(o, tm); +FunctionPass *llvm::createPPC32AsmPrinter(std::ostream &o, TargetMachine &tm) { + return new PPC32AsmPrinter(o, tm); } // Include the auto-generated portion of the assembly writer @@ -151,7 +149,7 @@ // Print a constant value or values, with the appropriate storage class as a // prefix. -void PowerPCAsmPrinter::emitGlobalConstant(const Constant *CV) { +void PPC32AsmPrinter::emitGlobalConstant(const Constant *CV) { const TargetData &TD = TM.getTargetData(); if (CV->isNullValue()) { @@ -275,7 +273,7 @@ /// used to print out constants which have been "spilled to memory" by /// the code generator. /// -void PowerPCAsmPrinter::printConstantPool(MachineConstantPool *MCP) { +void PPC32AsmPrinter::printConstantPool(MachineConstantPool *MCP) { const std::vector &CP = MCP->getConstants(); const TargetData &TD = TM.getTargetData(); @@ -294,7 +292,7 @@ /// runOnMachineFunction - This uses the printMachineInstruction() /// method to print assembly for each instruction. /// -bool PowerPCAsmPrinter::runOnMachineFunction(MachineFunction &MF) { +bool PPC32AsmPrinter::runOnMachineFunction(MachineFunction &MF) { setupMachineFunction(MF); O << "\n\n"; @@ -326,8 +324,8 @@ return false; } -void PowerPCAsmPrinter::printOp(const MachineOperand &MO, - bool LoadAddrOp /* = false */) { +void PPC32AsmPrinter::printOp(const MachineOperand &MO, + bool LoadAddrOp /* = false */) { const MRegisterInfo &RI = *TM.getRegisterInfo(); int new_symbol; @@ -408,7 +406,7 @@ } } -void PowerPCAsmPrinter::printImmOp(const MachineOperand &MO, unsigned ArgType) { +void PPC32AsmPrinter::printImmOp(const MachineOperand &MO, unsigned ArgType) { int Imm = MO.getImmedValue(); if (ArgType == PPCII::Simm16 || ArgType == PPCII::Disimm16) { O << (short)Imm; @@ -420,7 +418,7 @@ /// printMachineInstruction -- Print out a single PowerPC MI in Darwin syntax to /// the current output stream. /// -void PowerPCAsmPrinter::printMachineInstruction(const MachineInstr *MI) { +void PPC32AsmPrinter::printMachineInstruction(const MachineInstr *MI) { ++EmittedInsts; if (printInstruction(MI)) return; // Printer was automatically generated @@ -550,7 +548,7 @@ } } -bool PowerPCAsmPrinter::doFinalization(Module &M) { +bool PPC32AsmPrinter::doFinalization(Module &M) { const TargetData &TD = TM.getTargetData(); std::string CurSection; Index: llvm/lib/Target/PowerPC/PPC32ISelSimple.cpp diff -u llvm/lib/Target/PowerPC/PPC32ISelSimple.cpp:1.66 llvm/lib/Target/PowerPC/PPC32ISelSimple.cpp:1.67 --- llvm/lib/Target/PowerPC/PPC32ISelSimple.cpp:1.66 Sun Aug 15 20:50:22 2004 +++ llvm/lib/Target/PowerPC/PPC32ISelSimple.cpp Mon Aug 16 23:55:41 2004 @@ -1,4 +1,4 @@ -//===-- InstSelectSimple.cpp - A simple instruction selector for PowerPC --===// +//===-- PPC32ISelSimple.cpp - A simple instruction selector PowerPC32 -----===// // // The LLVM Compiler Infrastructure // @@ -98,7 +98,7 @@ unsigned GlobalBaseReg; bool GlobalBaseInitialized; - ISel(TargetMachine &tm) : TM(reinterpret_cast(tm)), + ISel(TargetMachine &tm) : TM(reinterpret_cast(tm)), F(0), BB(0) {} bool doInitialization(Module &M) { @@ -381,10 +381,10 @@ /// high 32 bits of the long value, and the regNum+1 is the low 32 bits. /// unsigned makeAnotherReg(const Type *Ty) { - assert(dynamic_cast(TM.getRegisterInfo()) && + assert(dynamic_cast(TM.getRegisterInfo()) && "Current target doesn't have PPC reg info??"); - const PowerPCRegisterInfo *PPCRI = - static_cast(TM.getRegisterInfo()); + const PPC32RegisterInfo *PPCRI = + static_cast(TM.getRegisterInfo()); if (Ty == Type::LongTy || Ty == Type::ULongTy) { const TargetRegisterClass *RC = PPCRI->getRegClassForType(Type::IntTy); // Create the upper part @@ -1403,7 +1403,7 @@ } else { // Change to the inverse condition... if (BI.getSuccessor(1) != NextBB) { - Opcode = PowerPCInstrInfo::invertPPCBranchOpcode(Opcode); + Opcode = PPC32InstrInfo::invertPPCBranchOpcode(Opcode); BuildMI(BB, PPC::COND_BRANCH, 3).addReg(PPC::CR0).addImm(Opcode) .addMBB(MBBMap[BI.getSuccessor(1)]) .addMBB(MBBMap[BI.getSuccessor(0)]); Index: llvm/lib/Target/PowerPC/PPC32TargetMachine.h diff -u llvm/lib/Target/PowerPC/PPC32TargetMachine.h:1.3 llvm/lib/Target/PowerPC/PPC32TargetMachine.h:1.4 --- llvm/lib/Target/PowerPC/PPC32TargetMachine.h:1.3 Fri Aug 13 04:33:17 2004 +++ llvm/lib/Target/PowerPC/PPC32TargetMachine.h Mon Aug 16 23:55:41 2004 @@ -1,4 +1,4 @@ -//===-- PPC32TargetMachine.h - PowerPC/Darwin TargetMachine ---*- C++ -*-=// +//===-- PPC32TargetMachine.h - Define TargetMachine for PowerPC -*- C++ -*-=// // // The LLVM Compiler Infrastructure // @@ -7,36 +7,42 @@ // //===----------------------------------------------------------------------===// // -// This file declares the PowerPC/Darwin specific subclass of TargetMachine. +// This file declares the PowerPC specific subclass of TargetMachine. // //===----------------------------------------------------------------------===// -#ifndef POWERPC_DARWIN_TARGETMACHINE_H -#define POWERPC_DARWIN_TARGETMACHINE_H +#ifndef POWERPC32_TARGETMACHINE_H +#define POWERPC32_TARGETMACHINE_H -#include "llvm/Target/TargetMachine.h" -#include "llvm/Target/TargetFrameInfo.h" -#include "llvm/PassManager.h" #include "PowerPCTargetMachine.h" +#include "PPC32InstrInfo.h" +#include "llvm/PassManager.h" +#include namespace llvm { +class GlobalValue; class IntrinsicLowering; class PPC32TargetMachine : public PowerPCTargetMachine { + PPC32InstrInfo InstrInfo; + public: PPC32TargetMachine(const Module &M, IntrinsicLowering *IL); + virtual const PPC32InstrInfo *getInstrInfo() const { return &InstrInfo; } + virtual const MRegisterInfo *getRegisterInfo() const { + return &InstrInfo.getRegisterInfo(); + } - /// addPassesToEmitMachineCode - Add passes to the specified pass manager to - /// get machine code emitted. This uses a MachineCodeEmitter object to handle - /// actually outputting the machine code and resolving things like the address - /// of functions. This method should returns true if machine code emission is - /// not supported. - /// - virtual bool addPassesToEmitMachineCode(FunctionPassManager &PM, - MachineCodeEmitter &MCE); - static unsigned getModuleMatchQuality(const Module &M); + + bool addPassesToEmitMachineCode(FunctionPassManager &PM, + MachineCodeEmitter &MCE); + + // Two shared sets between the instruction selector and the printer allow for + // correct linkage on Darwin + std::set CalledFunctions; + std::set AddressTaken; }; } // end namespace llvm From brukman at cs.uiuc.edu Mon Aug 16 23:57:47 2004 From: brukman at cs.uiuc.edu (Misha Brukman) Date: Mon, 16 Aug 2004 23:57:47 -0500 Subject: [llvm-commits] CVS: llvm/lib/Target/PowerPC/PPC64.td PPC64InstrInfo.cpp PPC64InstrInfo.h PPC64RegisterInfo.cpp PPC64RegisterInfo.h PPC64RegisterInfo.td PPC64AsmPrinter.cpp PPC64ISelSimple.cpp PPC64TargetMachine.h Message-ID: <200408170457.XAA03498@zion.cs.uiuc.edu> Changes in directory llvm/lib/Target/PowerPC: PPC64.td added (r1.1) PPC64InstrInfo.cpp added (r1.1) PPC64InstrInfo.h added (r1.1) PPC64RegisterInfo.cpp added (r1.1) PPC64RegisterInfo.h added (r1.1) PPC64RegisterInfo.td added (r1.1) PPC64AsmPrinter.cpp updated: 1.5 -> 1.6 PPC64ISelSimple.cpp updated: 1.4 -> 1.5 PPC64TargetMachine.h updated: 1.2 -> 1.3 --- Log message: PowerPC 32-/64-bit split: Part II, 64-bit customizations on PowerPC --- Diffs of the changes: (+592 -27) Index: llvm/lib/Target/PowerPC/PPC64.td diff -c /dev/null llvm/lib/Target/PowerPC/PPC64.td:1.1 *** /dev/null Mon Aug 16 23:57:47 2004 --- llvm/lib/Target/PowerPC/PPC64.td Mon Aug 16 23:57:37 2004 *************** *** 0 **** --- 1,43 ---- + //===- PPC64.td - Describe the PowerPC64 Target Machine ----*- tablegen -*-===// + // + // The LLVM Compiler Infrastructure + // + // This file was developed by the LLVM research group and is distributed under + // the University of Illinois Open Source License. See LICENSE.TXT for details. + // + //===----------------------------------------------------------------------===// + // + // + //===----------------------------------------------------------------------===// + + // Get the target-independent interfaces which we are implementing... + // + include "../Target.td" + + //===----------------------------------------------------------------------===// + // Register File Description + //===----------------------------------------------------------------------===// + + include "PPC32RegisterInfo.td" + include "PowerPCInstrInfo.td" + + def PowerPCInstrInfo : InstrInfo { + let PHIInst = PHI; + + let TSFlagsFields = ["ArgCount", "Arg0Type", "Arg1Type", "Arg2Type", + "Arg3Type", "Arg4Type", "VMX", "PPC64"]; + let TSFlagsShifts = [ 0, 3, 8, 13, 18, 23, 28, 29 ]; + } + + def PPC64 : Target { + // Pointers on PPC64 are 64-bits in size. + let PointerType = i64; + + let CalleeSavedRegisters = [R1, R13, R14, R15, R16, R17, R18, R19, + R20, R21, R22, R23, R24, R25, R26, R27, R28, R29, R30, R31, F14, F15, + F16, F17, F18, F19, F20, F21, F22, F23, F24, F25, F26, F27, F28, F29, + F30, F31, CR2, CR3, CR4, LR]; + + // Pull in Instruction Info: + let InstructionSet = PowerPCInstrInfo; + } Index: llvm/lib/Target/PowerPC/PPC64InstrInfo.cpp diff -c /dev/null llvm/lib/Target/PowerPC/PPC64InstrInfo.cpp:1.1 *** /dev/null Mon Aug 16 23:57:47 2004 --- llvm/lib/Target/PowerPC/PPC64InstrInfo.cpp Mon Aug 16 23:57:37 2004 *************** *** 0 **** --- 1,59 ---- + //===- PPC64InstrInfo.cpp - PowerPC64 Instruction Information ---*- C++ -*-===// + // + // The LLVM Compiler Infrastructure + // + // This file was developed by the LLVM research group and is distributed under + // the University of Illinois Open Source License. See LICENSE.TXT for details. + // + //===----------------------------------------------------------------------===// + // + // This file contains the PowerPC implementation of the TargetInstrInfo class. + // + //===----------------------------------------------------------------------===// + + #include "PowerPC.h" + #include "PPC64InstrInfo.h" + #include "PPC64GenInstrInfo.inc" + #include "llvm/CodeGen/MachineInstrBuilder.h" + #include + using namespace llvm; + + PPC64InstrInfo::PPC64InstrInfo() + : TargetInstrInfo(PPC64Insts, sizeof(PPC64Insts)/sizeof(PPC64Insts[0])) { } + + bool PPC64InstrInfo::isMoveInstr(const MachineInstr& MI, + unsigned& sourceReg, + unsigned& destReg) const { + MachineOpCode oc = MI.getOpcode(); + if (oc == PPC::OR) { // or r1, r2, r2 + assert(MI.getNumOperands() == 3 && + MI.getOperand(0).isRegister() && + MI.getOperand(1).isRegister() && + MI.getOperand(2).isRegister() && + "invalid PPC OR instruction!"); + if (MI.getOperand(1).getReg() == MI.getOperand(2).getReg()) { + sourceReg = MI.getOperand(1).getReg(); + destReg = MI.getOperand(0).getReg(); + return true; + } + } else if (oc == PPC::ADDI) { // addi r1, r2, 0 + assert(MI.getNumOperands() == 3 && + MI.getOperand(0).isRegister() && + MI.getOperand(2).isImmediate() && + "invalid PPC ADDI instruction!"); + if (MI.getOperand(1).isRegister() && MI.getOperand(2).getImmedValue()==0) { + sourceReg = MI.getOperand(1).getReg(); + destReg = MI.getOperand(0).getReg(); + return true; + } + } else if (oc == PPC::FMR) { // fmr r1, r2 + assert(MI.getNumOperands() == 2 && + MI.getOperand(0).isRegister() && + MI.getOperand(1).isRegister() && + "invalid PPC FMR instruction"); + sourceReg = MI.getOperand(1).getReg(); + destReg = MI.getOperand(0).getReg(); + return true; + } + return false; + } Index: llvm/lib/Target/PowerPC/PPC64InstrInfo.h diff -c /dev/null llvm/lib/Target/PowerPC/PPC64InstrInfo.h:1.1 *** /dev/null Mon Aug 16 23:57:47 2004 --- llvm/lib/Target/PowerPC/PPC64InstrInfo.h Mon Aug 16 23:57:37 2004 *************** *** 0 **** --- 1,56 ---- + //===- PPC64InstrInfo.h - PowerPC64 Instruction Information -----*- C++ -*-===// + // + // The LLVM Compiler Infrastructure + // + // This file was developed by the LLVM research group and is distributed under + // the University of Illinois Open Source License. See LICENSE.TXT for details. + // + //===----------------------------------------------------------------------===// + // + // This file contains the PowerPC64 implementation of the TargetInstrInfo class. + // + //===----------------------------------------------------------------------===// + + #ifndef POWERPC64_INSTRUCTIONINFO_H + #define POWERPC64_INSTRUCTIONINFO_H + + #include "PowerPCInstrInfo.h" + #include "PPC64RegisterInfo.h" + + namespace llvm { + + class PPC64InstrInfo : public TargetInstrInfo { + const PPC64RegisterInfo RI; + public: + PPC64InstrInfo(); + + /// getRegisterInfo - TargetInstrInfo is a superset of MRegister info. As + /// such, whenever a client has an instance of instruction info, it should + /// always be able to get register info as well (through this method). + /// + virtual const MRegisterInfo &getRegisterInfo() const { return RI; } + + // + // Return true if the instruction is a register to register move and + // leave the source and dest operands in the passed parameters. + // + virtual bool isMoveInstr(const MachineInstr& MI, + unsigned& sourceReg, + unsigned& destReg) const; + + static unsigned invertPPCBranchOpcode(unsigned Opcode) { + switch (Opcode) { + default: assert(0 && "Unknown PPC branch opcode!"); + case PPC::BEQ: return PPC::BNE; + case PPC::BNE: return PPC::BEQ; + case PPC::BLT: return PPC::BGE; + case PPC::BGE: return PPC::BLT; + case PPC::BGT: return PPC::BLE; + case PPC::BLE: return PPC::BGT; + } + } + }; + + } + + #endif Index: llvm/lib/Target/PowerPC/PPC64RegisterInfo.cpp diff -c /dev/null llvm/lib/Target/PowerPC/PPC64RegisterInfo.cpp:1.1 *** /dev/null Mon Aug 16 23:57:47 2004 --- llvm/lib/Target/PowerPC/PPC64RegisterInfo.cpp Mon Aug 16 23:57:37 2004 *************** *** 0 **** --- 1,317 ---- + //===- PPC64RegisterInfo.cpp - PowerPC64 Register Information ---*- C++ -*-===// + // + // The LLVM Compiler Infrastructure + // + // This file was developed by the LLVM research group and is distributed under + // the University of Illinois Open Source License. See LICENSE.TXT for details. + // + //===----------------------------------------------------------------------===// + // + // This file contains the PowerPC64 implementation of the MRegisterInfo class. + // + //===----------------------------------------------------------------------===// + + #define DEBUG_TYPE "reginfo" + #include "PowerPC.h" + #include "PowerPCInstrBuilder.h" + #include "PPC64RegisterInfo.h" + #include "llvm/Constants.h" + #include "llvm/Type.h" + #include "llvm/CodeGen/ValueTypes.h" + #include "llvm/CodeGen/MachineInstrBuilder.h" + #include "llvm/CodeGen/MachineFunction.h" + #include "llvm/CodeGen/MachineFrameInfo.h" + #include "llvm/Target/TargetFrameInfo.h" + #include "llvm/Target/TargetMachine.h" + #include "llvm/Target/TargetOptions.h" + #include "Support/CommandLine.h" + #include "Support/Debug.h" + #include "Support/STLExtras.h" + #include + #include + using namespace llvm; + + namespace llvm { + // Switch toggling compilation for AIX + extern cl::opt AIX; + } + + PPC64RegisterInfo::PPC64RegisterInfo() + : PPC64GenRegisterInfo(PPC::ADJCALLSTACKDOWN, PPC::ADJCALLSTACKUP) { + ImmToIdxMap[PPC::LD] = PPC::LDX; ImmToIdxMap[PPC::STD] = PPC::STDX; + ImmToIdxMap[PPC::LBZ] = PPC::LBZX; ImmToIdxMap[PPC::STB] = PPC::STBX; + ImmToIdxMap[PPC::LHZ] = PPC::LHZX; ImmToIdxMap[PPC::LHA] = PPC::LHAX; + ImmToIdxMap[PPC::LWZ] = PPC::LWZX; ImmToIdxMap[PPC::LWA] = PPC::LWAX; + ImmToIdxMap[PPC::LFS] = PPC::LFSX; ImmToIdxMap[PPC::LFD] = PPC::LFDX; + ImmToIdxMap[PPC::STH] = PPC::STHX; ImmToIdxMap[PPC::STW] = PPC::STWX; + ImmToIdxMap[PPC::STFS] = PPC::STFSX; ImmToIdxMap[PPC::STFD] = PPC::STFDX; + ImmToIdxMap[PPC::ADDI] = PPC::ADD; + } + + static unsigned getIdx(const TargetRegisterClass *RC) { + if (RC == PPC64::GPRCRegisterClass) { + switch (RC->getSize()) { + default: assert(0 && "Invalid data size!"); + case 1: return 0; + case 2: return 1; + case 4: return 2; + case 8: return 3; + } + } else if (RC == PPC64::FPRCRegisterClass) { + switch (RC->getSize()) { + default: assert(0 && "Invalid data size!"); + case 4: return 4; + case 8: return 5; + } + } + std::cerr << "Invalid register class to getIdx()!\n"; + abort(); + } + + void + PPC64RegisterInfo::storeRegToStackSlot(MachineBasicBlock &MBB, + MachineBasicBlock::iterator MI, + unsigned SrcReg, int FrameIdx) const { + const TargetRegisterClass *RC = getRegClass(SrcReg); + static const unsigned Opcode[] = { + PPC::STB, PPC::STH, PPC::STW, PPC::STD, PPC::STFS, PPC::STFD + }; + + unsigned OC = Opcode[getIdx(RC)]; + if (SrcReg == PPC::LR) { + BuildMI(MBB, MI, PPC::MFLR, 0, PPC::R11); + BuildMI(MBB, MI, PPC::IMPLICIT_DEF, 0, PPC::R0); + addFrameReference(BuildMI(MBB, MI, OC, 3).addReg(PPC::R11),FrameIdx); + } else { + BuildMI(MBB, MI, PPC::IMPLICIT_DEF, 0, PPC::R0); + addFrameReference(BuildMI(MBB, MI, OC, 3).addReg(SrcReg),FrameIdx); + } + } + + void + PPC64RegisterInfo::loadRegFromStackSlot(MachineBasicBlock &MBB, + MachineBasicBlock::iterator MI, + unsigned DestReg, int FrameIdx) const{ + static const unsigned Opcode[] = { + PPC::LBZ, PPC::LHZ, PPC::LWZ, PPC::LD, PPC::LFS, PPC::LFD + }; + const TargetRegisterClass *RC = getRegClass(DestReg); + unsigned OC = Opcode[getIdx(RC)]; + if (DestReg == PPC::LR) { + BuildMI(MBB, MI, PPC::IMPLICIT_DEF, 0, PPC::R0); + addFrameReference(BuildMI(MBB, MI, OC, 2, PPC::R11), FrameIdx); + BuildMI(MBB, MI, PPC::MTLR, 1).addReg(PPC::R11); + } else { + BuildMI(MBB, MI, PPC::IMPLICIT_DEF, 0, PPC::R0); + addFrameReference(BuildMI(MBB, MI, OC, 2, DestReg), FrameIdx); + } + } + + void PPC64RegisterInfo::copyRegToReg(MachineBasicBlock &MBB, + MachineBasicBlock::iterator MI, + unsigned DestReg, unsigned SrcReg, + const TargetRegisterClass *RC) const { + MachineInstr *I; + + if (RC == PPC64::GPRCRegisterClass) { + BuildMI(MBB, MI, PPC::OR, 2, DestReg).addReg(SrcReg).addReg(SrcReg); + } else if (RC == PPC64::FPRCRegisterClass) { + BuildMI(MBB, MI, PPC::FMR, 1, DestReg).addReg(SrcReg); + } else { + std::cerr << "Attempt to copy register that is not GPR or FPR"; + abort(); + } + } + + //===----------------------------------------------------------------------===// + // Stack Frame Processing methods + //===----------------------------------------------------------------------===// + + // hasFP - Return true if the specified function should have a dedicated frame + // pointer register. This is true if the function has variable sized allocas or + // if frame pointer elimination is disabled. + // + static bool hasFP(MachineFunction &MF) { + MachineFrameInfo *MFI = MF.getFrameInfo(); + return MFI->hasVarSizedObjects(); + } + + void PPC64RegisterInfo:: + eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB, + MachineBasicBlock::iterator I) const { + if (hasFP(MF)) { + // If we have a frame pointer, convert as follows: + // ADJCALLSTACKDOWN -> addi, r1, r1, -amount + // ADJCALLSTACKUP -> addi, r1, r1, amount + MachineInstr *Old = I; + unsigned Amount = Old->getOperand(0).getImmedValue(); + if (Amount != 0) { + // We need to keep the stack aligned properly. To do this, we round the + // amount of space needed for the outgoing arguments up to the next + // alignment boundary. + unsigned Align = MF.getTarget().getFrameInfo()->getStackAlignment(); + Amount = (Amount+Align-1)/Align*Align; + + // Replace the pseudo instruction with a new instruction... + if (Old->getOpcode() == PPC::ADJCALLSTACKDOWN) { + MBB.insert(I, BuildMI(PPC::ADDI, 2, PPC::R1).addReg(PPC::R1) + .addSImm(-Amount)); + } else { + assert(Old->getOpcode() == PPC::ADJCALLSTACKUP); + MBB.insert(I, BuildMI(PPC::ADDI, 2, PPC::R1).addReg(PPC::R1) + .addSImm(Amount)); + } + } + } + MBB.erase(I); + } + + void + PPC64RegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II) const { + unsigned i = 0; + MachineInstr &MI = *II; + MachineBasicBlock &MBB = *MI.getParent(); + MachineFunction &MF = *MBB.getParent(); + + while (!MI.getOperand(i).isFrameIndex()) { + ++i; + assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!"); + } + + int FrameIndex = MI.getOperand(i).getFrameIndex(); + + // Replace the FrameIndex with base register with GPR1 (SP) or GPR31 (FP). + MI.SetMachineOperandReg(i, hasFP(MF) ? PPC::R31 : PPC::R1); + + // Take into account whether it's an add or mem instruction + unsigned OffIdx = (i == 2) ? 1 : 2; + + // Now add the frame object offset to the offset from r1. + int Offset = MF.getFrameInfo()->getObjectOffset(FrameIndex) + + MI.getOperand(OffIdx).getImmedValue(); + + // If we're not using a Frame Pointer that has been set to the value of the + // SP before having the stack size subtracted from it, then add the stack size + // to Offset to get the correct offset. + Offset += MF.getFrameInfo()->getStackSize(); + + if (Offset > 32767 || Offset < -32768) { + // Insert a set of r0 with the full offset value before the ld, st, or add + MachineBasicBlock *MBB = MI.getParent(); + MBB->insert(II, BuildMI(PPC::LIS, 1, PPC::R0).addSImm(Offset >> 16)); + MBB->insert(II, BuildMI(PPC::ORI, 2, PPC::R0).addReg(PPC::R0) + .addImm(Offset)); + // convert into indexed form of the instruction + // sth 0:rA, 1:imm 2:(rB) ==> sthx 0:rA, 2:rB, 1:r0 + // addi 0:rA 1:rB, 2, imm ==> add 0:rA, 1:rB, 2:r0 + unsigned NewOpcode = const_cast& >(ImmToIdxMap)[MI.getOpcode()]; + assert(NewOpcode && "No indexed form of load or store available!"); + MI.setOpcode(NewOpcode); + MI.SetMachineOperandReg(1, MI.getOperand(i).getReg()); + MI.SetMachineOperandReg(2, PPC::R0); + } else { + MI.SetMachineOperandConst(OffIdx,MachineOperand::MO_SignExtendedImmed,Offset); + } + } + + + void PPC64RegisterInfo::emitPrologue(MachineFunction &MF) const { + MachineBasicBlock &MBB = MF.front(); // Prolog goes in entry BB + MachineBasicBlock::iterator MBBI = MBB.begin(); + MachineFrameInfo *MFI = MF.getFrameInfo(); + MachineInstr *MI; + + // Get the number of bytes to allocate from the FrameInfo + unsigned NumBytes = MFI->getStackSize(); + + // If we have calls, we cannot use the red zone to store callee save registers + // and we must set up a stack frame, so calculate the necessary size here. + if (MFI->hasCalls()) { + // We reserve argument space for call sites in the function immediately on + // entry to the current function. This eliminates the need for add/sub + // brackets around call sites. + NumBytes += MFI->getMaxCallFrameSize(); + } + + // Do we need to allocate space on the stack? + if (NumBytes == 0) return; + + // Add the size of R1 to NumBytes size for the store of R1 to the bottom + // of the stack and round the size to a multiple of the alignment. + unsigned Align = MF.getTarget().getFrameInfo()->getStackAlignment(); + unsigned R1Size = getRegClass(PPC::R1)->getSize(); + unsigned R31Size = getRegClass(PPC::R31)->getSize(); + unsigned Size = (hasFP(MF)) ? R1Size + R31Size : R1Size; + NumBytes = (NumBytes+Size+Align-1)/Align*Align; + + // Update frame info to pretend that this is part of the stack... + MFI->setStackSize(NumBytes); + + // adjust stack pointer: r1 -= numbytes + if (NumBytes <= 32768) { + MI=BuildMI(PPC::STDU,3).addReg(PPC::R1).addSImm(-NumBytes).addReg(PPC::R1); + MBB.insert(MBBI, MI); + } else { + int NegNumbytes = -NumBytes; + MI = BuildMI(PPC::LIS, 1, PPC::R0).addSImm(NegNumbytes >> 16); + MBB.insert(MBBI, MI); + MI = BuildMI(PPC::ORI, 2, PPC::R0).addReg(PPC::R0) + .addImm(NegNumbytes & 0xFFFF); + MBB.insert(MBBI, MI); + MI = BuildMI(PPC::STDUX, 3).addReg(PPC::R1).addReg(PPC::R1).addReg(PPC::R0); + MBB.insert(MBBI, MI); + } + + if (hasFP(MF)) { + MI = BuildMI(PPC::STD, 3).addReg(PPC::R31).addSImm(R1Size).addReg(PPC::R1); + MBB.insert(MBBI, MI); + MI = BuildMI(PPC::OR, 2, PPC::R31).addReg(PPC::R1).addReg(PPC::R1); + MBB.insert(MBBI, MI); + } + } + + void PPC64RegisterInfo::emitEpilogue(MachineFunction &MF, + MachineBasicBlock &MBB) const { + const MachineFrameInfo *MFI = MF.getFrameInfo(); + MachineBasicBlock::iterator MBBI = prior(MBB.end()); + MachineInstr *MI; + assert(MBBI->getOpcode() == PPC::BLR && + "Can only insert epilog into returning blocks"); + + // Get the number of bytes allocated from the FrameInfo... + unsigned NumBytes = MFI->getStackSize(); + + if (NumBytes != 0) { + if (hasFP(MF)) { + MI = BuildMI(PPC::OR, 2, PPC::R1).addReg(PPC::R31).addReg(PPC::R31); + MBB.insert(MBBI, MI); + MI = BuildMI(PPC::LD, 2, PPC::R31).addSImm(4).addReg(PPC::R31); + MBB.insert(MBBI, MI); + } + MI = BuildMI(PPC::LD, 2, PPC::R1).addSImm(0).addReg(PPC::R1); + MBB.insert(MBBI, MI); + } + } + + #include "PPC64GenRegisterInfo.inc" + + const TargetRegisterClass* + PPC64RegisterInfo::getRegClassForType(const Type* Ty) const { + switch (Ty->getTypeID()) { + default: assert(0 && "Invalid type to getClass!"); + case Type::BoolTyID: + case Type::SByteTyID: + case Type::UByteTyID: + case Type::ShortTyID: + case Type::UShortTyID: + case Type::IntTyID: + case Type::UIntTyID: + case Type::PointerTyID: + case Type::LongTyID: + case Type::ULongTyID: return &GPRCInstance; + + case Type::FloatTyID: + case Type::DoubleTyID: return &FPRCInstance; + } + } + Index: llvm/lib/Target/PowerPC/PPC64RegisterInfo.h diff -c /dev/null llvm/lib/Target/PowerPC/PPC64RegisterInfo.h:1.1 *** /dev/null Mon Aug 16 23:57:47 2004 --- llvm/lib/Target/PowerPC/PPC64RegisterInfo.h Mon Aug 16 23:57:37 2004 *************** *** 0 **** --- 1,56 ---- + //===- PPC64RegisterInfo.h - PowerPC64 Register Information Impl -*- C++ -*-==// + // + // The LLVM Compiler Infrastructure + // + // This file was developed by the LLVM research group and is distributed under + // the University of Illinois Open Source License. See LICENSE.TXT for details. + // + //===----------------------------------------------------------------------===// + // + // This file contains the PowerPC implementation of the MRegisterInfo class. + // + //===----------------------------------------------------------------------===// + + #ifndef POWERPC64_REGISTERINFO_H + #define POWERPC64_REGISTERINFO_H + + #include "PowerPC.h" + #include "PPC64GenRegisterInfo.h.inc" + #include + + namespace llvm { + + class Type; + + class PPC64RegisterInfo : public PPC64GenRegisterInfo { + std::map ImmToIdxMap; + public: + PPC64RegisterInfo(); + const TargetRegisterClass* getRegClassForType(const Type* Ty) const; + + /// Code Generation virtual methods... + void storeRegToStackSlot(MachineBasicBlock &MBB, + MachineBasicBlock::iterator MBBI, + unsigned SrcReg, int FrameIndex) const; + + void loadRegFromStackSlot(MachineBasicBlock &MBB, + MachineBasicBlock::iterator MBBI, + unsigned DestReg, int FrameIndex) const; + + void copyRegToReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, + unsigned DestReg, unsigned SrcReg, + const TargetRegisterClass *RC) const; + + void eliminateCallFramePseudoInstr(MachineFunction &MF, + MachineBasicBlock &MBB, + MachineBasicBlock::iterator I) const; + + void eliminateFrameIndex(MachineBasicBlock::iterator II) const; + + void emitPrologue(MachineFunction &MF) const; + void emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const; + }; + + } // end namespace llvm + + #endif Index: llvm/lib/Target/PowerPC/PPC64RegisterInfo.td diff -c /dev/null llvm/lib/Target/PowerPC/PPC64RegisterInfo.td:1.1 *** /dev/null Mon Aug 16 23:57:47 2004 --- llvm/lib/Target/PowerPC/PPC64RegisterInfo.td Mon Aug 16 23:57:37 2004 *************** *** 0 **** --- 1,40 ---- + //===- PPC64RegisterInfo.td - The PowerPC64 Register File --*- tablegen -*-===// + // + // The LLVM Compiler Infrastructure + // + // This file was developed by the LLVM research group and is distributed under + // the University of Illinois Open Source License. See LICENSE.TXT for details. + // + //===----------------------------------------------------------------------===// + // + // + //===----------------------------------------------------------------------===// + + include "PowerPCRegisterInfo.td" + + /// Register classes + // Allocate volatiles first + // then nonvolatiles in reverse order since stmw/lmw save from rN to r31 + def GPRC : RegisterClass + { + let Methods = [{ + iterator allocation_order_begin(MachineFunction &MF) const { + return begin() + (AIX ? 1 : 0); + } + iterator allocation_order_end(MachineFunction &MF) const { + if (hasFP(MF)) + return end()-4; + else + return end()-3; + } + }]; + } + + def FPRC : RegisterClass; + + def CRRC : RegisterClass; Index: llvm/lib/Target/PowerPC/PPC64AsmPrinter.cpp diff -u llvm/lib/Target/PowerPC/PPC64AsmPrinter.cpp:1.5 llvm/lib/Target/PowerPC/PPC64AsmPrinter.cpp:1.6 --- llvm/lib/Target/PowerPC/PPC64AsmPrinter.cpp:1.5 Sun Aug 15 00:48:47 2004 +++ llvm/lib/Target/PowerPC/PPC64AsmPrinter.cpp Mon Aug 16 23:57:37 2004 @@ -24,7 +24,6 @@ #include "llvm/CodeGen/MachineConstantPool.h" #include "llvm/CodeGen/MachineFunctionPass.h" #include "llvm/CodeGen/MachineInstr.h" -#include "llvm/Target/TargetMachine.h" #include "llvm/Support/Mangler.h" #include "Support/CommandLine.h" #include "Support/Debug.h" Index: llvm/lib/Target/PowerPC/PPC64ISelSimple.cpp diff -u llvm/lib/Target/PowerPC/PPC64ISelSimple.cpp:1.4 llvm/lib/Target/PowerPC/PPC64ISelSimple.cpp:1.5 --- llvm/lib/Target/PowerPC/PPC64ISelSimple.cpp:1.4 Thu Aug 12 21:20:47 2004 +++ llvm/lib/Target/PowerPC/PPC64ISelSimple.cpp Mon Aug 16 23:57:37 2004 @@ -377,10 +377,10 @@ /// yet used. /// unsigned makeAnotherReg(const Type *Ty) { - assert(dynamic_cast(TM.getRegisterInfo()) && + assert(dynamic_cast(TM.getRegisterInfo()) && "Current target doesn't have PPC reg info??"); - const PowerPCRegisterInfo *PPCRI = - static_cast(TM.getRegisterInfo()); + const PPC64RegisterInfo *PPCRI = + static_cast(TM.getRegisterInfo()); // Add the mapping of regnumber => reg class to MachineFunction const TargetRegisterClass *RC = PPCRI->getRegClassForType(Ty); return F->getSSARegMap()->createVirtualRegister(RC); @@ -1288,7 +1288,7 @@ } else { // Change to the inverse condition... if (BI.getSuccessor(1) != NextBB) { - Opcode = PowerPCInstrInfo::invertPPCBranchOpcode(Opcode); + Opcode = PPC64InstrInfo::invertPPCBranchOpcode(Opcode); BuildMI(BB, PPC::COND_BRANCH, 3).addReg(PPC::CR0).addImm(Opcode) .addMBB(MBBMap[BI.getSuccessor(1)]) .addMBB(MBBMap[BI.getSuccessor(0)]); @@ -1497,8 +1497,6 @@ } // Emit a CALL instruction with PC-relative displacement. TheCall = BuildMI(PPC::CALLpcrel, 1).addGlobalAddress(F, true); - // Add it to the set of functions called to be used by the Printer - TM.CalledFunctions.insert(F); } else { // Emit an indirect call through the CTR unsigned Reg = getReg(CI.getCalledValue()); BuildMI(BB, PPC::MTCTR, 1).addReg(Reg); @@ -1997,7 +1995,6 @@ Args.push_back(ValueRecord(Op0Reg, Type::FloatTy)); Args.push_back(ValueRecord(Op1Reg, Type::FloatTy)); doCall(ValueRecord(ResultReg, Type::FloatTy), TheCall, Args, false); - TM.CalledFunctions.insert(fmodfFn); } return; case cFP64: @@ -2015,7 +2012,6 @@ Args.push_back(ValueRecord(Op0Reg, Type::DoubleTy)); Args.push_back(ValueRecord(Op1Reg, Type::DoubleTy)); doCall(ValueRecord(ResultReg, Type::DoubleTy), TheCall, Args, false); - TM.CalledFunctions.insert(fmodFn); } return; case cLong: { @@ -2031,7 +2027,6 @@ Args.push_back(ValueRecord(Op0Reg, Type::LongTy)); Args.push_back(ValueRecord(Op1Reg, Type::LongTy)); doCall(ValueRecord(ResultReg, Type::LongTy), TheCall, Args, false); - TM.CalledFunctions.insert(Funcs[NameIdx]); return; } case cByte: case cShort: case cInt: @@ -2401,7 +2396,6 @@ MachineInstr *TheCall = BuildMI(PPC::CALLpcrel, 1).addGlobalAddress(floatFn, true); doCall(ValueRecord(DestReg, DestTy), TheCall, Args, false); - TM.CalledFunctions.insert(floatFn); return; } @@ -2473,7 +2467,6 @@ MachineInstr *TheCall = BuildMI(PPC::CALLpcrel, 1).addGlobalAddress(floatFn, true); doCall(ValueRecord(DestReg, DestTy), TheCall, Args, false); - TM.CalledFunctions.insert(floatFn); return; } @@ -3041,7 +3034,6 @@ MachineInstr *TheCall = BuildMI(PPC::CALLpcrel, 1).addGlobalAddress(mallocFn, true); doCall(ValueRecord(getReg(I), I.getType()), TheCall, Args, false); - TM.CalledFunctions.insert(mallocFn); } @@ -3054,7 +3046,6 @@ MachineInstr *TheCall = BuildMI(PPC::CALLpcrel, 1).addGlobalAddress(freeFn, true); doCall(ValueRecord(0, Type::VoidTy), TheCall, Args, false); - TM.CalledFunctions.insert(freeFn); } /// createPPC64ISelSimple - This pass converts an LLVM function into a machine Index: llvm/lib/Target/PowerPC/PPC64TargetMachine.h diff -u llvm/lib/Target/PowerPC/PPC64TargetMachine.h:1.2 llvm/lib/Target/PowerPC/PPC64TargetMachine.h:1.3 --- llvm/lib/Target/PowerPC/PPC64TargetMachine.h:1.2 Wed Aug 11 02:40:04 2004 +++ llvm/lib/Target/PowerPC/PPC64TargetMachine.h Mon Aug 16 23:57:37 2004 @@ -1,4 +1,4 @@ -//===-- PPC64TargetMachine.h - Define AIX/PowerPC TargetMachine --*- C++ -*-=// +//===-- PPC64TargetMachine.h - Define TargetMachine for PowerPC64 -*- C++ -*-=// // // The LLVM Compiler Infrastructure // @@ -7,31 +7,35 @@ // //===----------------------------------------------------------------------===// // -// This file declares the PowerPC/AIX specific subclass of TargetMachine. +// This file declares the PowerPC specific subclass of TargetMachine. // //===----------------------------------------------------------------------===// -#ifndef POWERPC_AIX_TARGETMACHINE_H -#define POWERPC_AIX_TARGETMACHINE_H +#ifndef POWERPC64_TARGETMACHINE_H +#define POWERPC64_TARGETMACHINE_H #include "PowerPCTargetMachine.h" +#include "PPC64InstrInfo.h" +#include "llvm/PassManager.h" namespace llvm { +class IntrinsicLowering; + class PPC64TargetMachine : public PowerPCTargetMachine { + PPC64InstrInfo InstrInfo; + public: PPC64TargetMachine(const Module &M, IntrinsicLowering *IL); + virtual const PPC64InstrInfo *getInstrInfo() const { return &InstrInfo; } + virtual const MRegisterInfo *getRegisterInfo() const { + return &InstrInfo.getRegisterInfo(); + } - /// addPassesToEmitMachineCode - Add passes to the specified pass manager to - /// get machine code emitted. This uses a MachineCodeEmitter object to handle - /// actually outputting the machine code and resolving things like the address - /// of functions. This method should returns true if machine code emission is - /// not supported. - /// - virtual bool addPassesToEmitMachineCode(FunctionPassManager &PM, - MachineCodeEmitter &MCE); - static unsigned getModuleMatchQuality(const Module &M); + + bool addPassesToEmitMachineCode(FunctionPassManager &PM, + MachineCodeEmitter &MCE); }; } // end namespace llvm From brukman at cs.uiuc.edu Mon Aug 16 23:59:00 2004 From: brukman at cs.uiuc.edu (Misha Brukman) Date: Mon, 16 Aug 2004 23:59:00 -0500 Subject: [llvm-commits] CVS: llvm/lib/Target/PowerPC/PowerPCBranchSelector.cpp Message-ID: <200408170459.XAA03582@zion.cs.uiuc.edu> Changes in directory llvm/lib/Target/PowerPC: PowerPCBranchSelector.cpp updated: 1.3 -> 1.4 --- Log message: PowerPCInstrInfo has gone away, PPC32 and PPC64 share opcodes. --- Diffs of the changes: (+2 -1) Index: llvm/lib/Target/PowerPC/PowerPCBranchSelector.cpp diff -u llvm/lib/Target/PowerPC/PowerPCBranchSelector.cpp:1.3 llvm/lib/Target/PowerPC/PowerPCBranchSelector.cpp:1.4 --- llvm/lib/Target/PowerPC/PowerPCBranchSelector.cpp:1.3 Tue Aug 10 17:47:03 2004 +++ llvm/lib/Target/PowerPC/PowerPCBranchSelector.cpp Mon Aug 16 23:58:50 2004 @@ -19,6 +19,7 @@ #include "PowerPC.h" #include "PowerPCInstrBuilder.h" #include "PowerPCInstrInfo.h" +#include "PPC32InstrInfo.h" #include "llvm/CodeGen/MachineFunctionPass.h" #include "llvm/CodeGen/MachineFunction.h" #include "Support/Debug.h" @@ -104,7 +105,7 @@ int Displacement = OffsetMap[trueMBB] - ByteCount; unsigned Opcode = MBBI->getOperand(1).getImmedValue(); - unsigned Inverted = PowerPCInstrInfo::invertPPCBranchOpcode(Opcode); + unsigned Inverted = PPC32InstrInfo::invertPPCBranchOpcode(Opcode); MachineInstr *MI = MBBI; if (Displacement >= -32768 && Displacement <= 32767) { From brukman at cs.uiuc.edu Tue Aug 17 00:00:57 2004 From: brukman at cs.uiuc.edu (Misha Brukman) Date: Tue, 17 Aug 2004 00:00:57 -0500 Subject: [llvm-commits] CVS: llvm/lib/Target/PowerPC/PowerPCInstrInfo.h Message-ID: <200408170500.AAA03714@zion.cs.uiuc.edu> Changes in directory llvm/lib/Target/PowerPC: PowerPCInstrInfo.h updated: 1.6 -> 1.7 --- Log message: The PowerPCInstrInfo class has gone away. --- Diffs of the changes: (+0 -34) Index: llvm/lib/Target/PowerPC/PowerPCInstrInfo.h diff -u llvm/lib/Target/PowerPC/PowerPCInstrInfo.h:1.6 llvm/lib/Target/PowerPC/PowerPCInstrInfo.h:1.7 --- llvm/lib/Target/PowerPC/PowerPCInstrInfo.h:1.6 Wed Aug 11 18:45:43 2004 +++ llvm/lib/Target/PowerPC/PowerPCInstrInfo.h Tue Aug 17 00:00:46 2004 @@ -15,7 +15,6 @@ #define POWERPC_INSTRUCTIONINFO_H #include "PowerPC.h" -#include "PowerPCRegisterInfo.h" #include "llvm/Target/TargetInstrInfo.h" namespace llvm { @@ -62,39 +61,6 @@ }; } -class PowerPCInstrInfo : public TargetInstrInfo { - const PowerPCRegisterInfo RI; - bool is64bit; -public: - PowerPCInstrInfo(bool is64b); - - /// getRegisterInfo - TargetInstrInfo is a superset of MRegister info. As - /// such, whenever a client has an instance of instruction info, it should - /// always be able to get register info as well (through this method). - /// - virtual const MRegisterInfo &getRegisterInfo() const { return RI; } - - // - // Return true if the instruction is a register to register move and - // leave the source and dest operands in the passed parameters. - // - virtual bool isMoveInstr(const MachineInstr& MI, - unsigned& sourceReg, - unsigned& destReg) const; - - static unsigned invertPPCBranchOpcode(unsigned Opcode) { - switch (Opcode) { - default: assert(0 && "Unknown PPC branch opcode!"); - case PPC::BEQ: return PPC::BNE; - case PPC::BNE: return PPC::BEQ; - case PPC::BLT: return PPC::BGE; - case PPC::BGE: return PPC::BLT; - case PPC::BGT: return PPC::BLE; - case PPC::BLE: return PPC::BGT; - } - } -}; - } #endif From brukman at cs.uiuc.edu Tue Aug 17 00:02:28 2004 From: brukman at cs.uiuc.edu (Misha Brukman) Date: Tue, 17 Aug 2004 00:02:28 -0500 Subject: [llvm-commits] CVS: llvm/lib/Target/PowerPC/PowerPCRegisterInfo.h Message-ID: <200408170502.AAA03777@zion.cs.uiuc.edu> Changes in directory llvm/lib/Target/PowerPC: PowerPCRegisterInfo.h updated: 1.6 -> 1.7 --- Log message: PowerPCRegisterInfo no longer takes a bool to differentiate 32 vs 64 bits --- Diffs of the changes: (+3 -6) Index: llvm/lib/Target/PowerPC/PowerPCRegisterInfo.h diff -u llvm/lib/Target/PowerPC/PowerPCRegisterInfo.h:1.6 llvm/lib/Target/PowerPC/PowerPCRegisterInfo.h:1.7 --- llvm/lib/Target/PowerPC/PowerPCRegisterInfo.h:1.6 Sun Aug 15 17:15:56 2004 +++ llvm/lib/Target/PowerPC/PowerPCRegisterInfo.h Tue Aug 17 00:02:18 2004 @@ -11,22 +11,19 @@ // //===----------------------------------------------------------------------===// -#ifndef POWERPCREGISTERINFO_H -#define POWERPCREGISTERINFO_H +#ifndef POWERPC_REGISTERINFO_H +#define POWERPC_REGISTERINFO_H #include "llvm/Target/MRegisterInfo.h" -#include "PowerPCGenRegisterInfo.h.inc" -#include namespace llvm { class Type; class PowerPCRegisterInfo : public PowerPCGenRegisterInfo { - bool is64bit; std::map ImmToIdxMap; public: - PowerPCRegisterInfo(bool is64b); + PowerPCRegisterInfo(); const TargetRegisterClass* getRegClassForType(const Type* Ty) const; /// Code Generation virtual methods... From brukman at cs.uiuc.edu Tue Aug 17 00:03:08 2004 From: brukman at cs.uiuc.edu (Misha Brukman) Date: Tue, 17 Aug 2004 00:03:08 -0500 Subject: [llvm-commits] CVS: llvm/lib/Target/PowerPC/PowerPC.h Message-ID: <200408170503.AAA03891@zion.cs.uiuc.edu> Changes in directory llvm/lib/Target/PowerPC: PowerPC.h updated: 1.8 -> 1.9 --- Log message: Consistently name passed with 32 or 64 in their name --- Diffs of the changes: (+2 -2) Index: llvm/lib/Target/PowerPC/PowerPC.h diff -u llvm/lib/Target/PowerPC/PowerPC.h:1.8 llvm/lib/Target/PowerPC/PowerPC.h:1.9 --- llvm/lib/Target/PowerPC/PowerPC.h:1.8 Sat Aug 14 17:16:36 2004 +++ llvm/lib/Target/PowerPC/PowerPC.h Tue Aug 17 00:02:58 2004 @@ -23,10 +23,10 @@ class TargetMachine; FunctionPass *createPPCBranchSelectionPass(); -FunctionPass *createPPCAsmPrinter(std::ostream &OS,TargetMachine &TM); FunctionPass *createPPC32ISelSimple(TargetMachine &TM); +FunctionPass *createPPC32AsmPrinter(std::ostream &OS, TargetMachine &TM); FunctionPass *createPPC64ISelSimple(TargetMachine &TM); -FunctionPass *createPPC64AsmPrinter(std::ostream &OS,TargetMachine &TM); +FunctionPass *createPPC64AsmPrinter(std::ostream &OS, TargetMachine &TM); } // end namespace llvm; From brukman at cs.uiuc.edu Tue Aug 17 00:05:10 2004 From: brukman at cs.uiuc.edu (Misha Brukman) Date: Tue, 17 Aug 2004 00:05:10 -0500 Subject: [llvm-commits] CVS: llvm/lib/Target/PowerPC/PowerPCInstrInfo.cpp PowerPCRegisterInfo.cpp Message-ID: <200408170505.AAA04003@zion.cs.uiuc.edu> Changes in directory llvm/lib/Target/PowerPC: PowerPCInstrInfo.cpp (r1.8) removed PowerPCRegisterInfo.cpp (r1.32) removed --- Log message: PowerPCInstrInfo and PowerPCRegisterInfo have gone away; they are replaced by 32- and 64-bit customized files, named appropriately. --- Diffs of the changes: (+0 -0) From brukman at cs.uiuc.edu Tue Aug 17 00:06:58 2004 From: brukman at cs.uiuc.edu (Misha Brukman) Date: Tue, 17 Aug 2004 00:06:58 -0500 Subject: [llvm-commits] CVS: llvm/lib/Target/PowerPC/PowerPCTargetMachine.cpp Message-ID: <200408170506.AAA04047@zion.cs.uiuc.edu> Changes in directory llvm/lib/Target/PowerPC: PowerPCTargetMachine.cpp updated: 1.29 -> 1.30 --- Log message: No need for an `is64bit' flag --- Diffs of the changes: (+12 -14) Index: llvm/lib/Target/PowerPC/PowerPCTargetMachine.cpp diff -u llvm/lib/Target/PowerPC/PowerPCTargetMachine.cpp:1.29 llvm/lib/Target/PowerPC/PowerPCTargetMachine.cpp:1.30 --- llvm/lib/Target/PowerPC/PowerPCTargetMachine.cpp:1.29 Sat Aug 14 17:16:36 2004 +++ llvm/lib/Target/PowerPC/PowerPCTargetMachine.cpp Tue Aug 17 00:06:47 2004 @@ -36,8 +36,8 @@ } namespace { - const std::string PPC32 = "PowerPC/32bit"; - const std::string PPC64 = "PowerPC/64bit"; + const std::string PPC32ID = "PowerPC/32bit"; + const std::string PPC64ID = "PowerPC/64bit"; // Register the targets RegisterTarget @@ -50,9 +50,8 @@ IntrinsicLowering *IL, const TargetData &TD, const PowerPCFrameInfo &TFI, - const PowerPCJITInfo &TJI, - bool is64b) - : TargetMachine(name, IL, TD), InstrInfo(is64b), FrameInfo(TFI), JITInfo(TJI) + const PowerPCJITInfo &TJI) + : TargetMachine(name, IL, TD), FrameInfo(TFI), JITInfo(TJI) {} unsigned PowerPCTargetMachine::getJITMatchQuality() { @@ -105,7 +104,7 @@ if (AIX) PM.add(createPPC64AsmPrinter(Out, *this)); else - PM.add(createPPCAsmPrinter(Out, *this)); + PM.add(createPPC32AsmPrinter(Out, *this)); PM.add(createMachineCodeDeleter()); return false; @@ -143,18 +142,17 @@ /// PowerPCTargetMachine ctor - Create an ILP32 architecture model /// -PPC32TargetMachine::PPC32TargetMachine(const Module &M, - IntrinsicLowering *IL) - : PowerPCTargetMachine(PPC32, IL, - TargetData(PPC32,false,4,4,4,4,4,4,2,1,4), - PowerPCFrameInfo(*this), PPC32JITInfo(*this), false) {} +PPC32TargetMachine::PPC32TargetMachine(const Module &M, IntrinsicLowering *IL) + : PowerPCTargetMachine(PPC32ID, IL, + TargetData(PPC32ID,false,4,4,4,4,4,4,2,1,4), + PowerPCFrameInfo(*this), PPC32JITInfo(*this)) {} /// PPC64TargetMachine ctor - Create a LP64 architecture model /// PPC64TargetMachine::PPC64TargetMachine(const Module &M, IntrinsicLowering *IL) - : PowerPCTargetMachine(PPC64, IL, - TargetData(PPC64,false,8,4,4,4,4,4,2,1,4), - PowerPCFrameInfo(*this), PPC64JITInfo(*this), true) {} + : PowerPCTargetMachine(PPC64ID, IL, + TargetData(PPC64ID,false,8,4,4,4,4,4,2,1,4), + PowerPCFrameInfo(*this), PPC64JITInfo(*this)) {} unsigned PPC32TargetMachine::getModuleMatchQuality(const Module &M) { if (M.getEndianness() == Module::BigEndian && From brukman at cs.uiuc.edu Tue Aug 17 00:08:54 2004 From: brukman at cs.uiuc.edu (Misha Brukman) Date: Tue, 17 Aug 2004 00:08:54 -0500 Subject: [llvm-commits] CVS: llvm/lib/Target/PowerPC/PowerPCTargetMachine.h Message-ID: <200408170508.AAA04105@zion.cs.uiuc.edu> Changes in directory llvm/lib/Target/PowerPC: PowerPCTargetMachine.h updated: 1.7 -> 1.8 --- Log message: Move variables and methods which need PPC{32,64}* distinction to subclasses --- Diffs of the changes: (+2 -15) Index: llvm/lib/Target/PowerPC/PowerPCTargetMachine.h diff -u llvm/lib/Target/PowerPC/PowerPCTargetMachine.h:1.7 llvm/lib/Target/PowerPC/PowerPCTargetMachine.h:1.8 --- llvm/lib/Target/PowerPC/PowerPCTargetMachine.h:1.7 Sat Aug 14 17:16:36 2004 +++ llvm/lib/Target/PowerPC/PowerPCTargetMachine.h Tue Aug 17 00:08:44 2004 @@ -7,7 +7,7 @@ // //===----------------------------------------------------------------------===// // -// This file declares the PowerPC specific subclass of TargetMachine. +// This file declares the PowerPC-specific subclass of TargetMachine. // //===----------------------------------------------------------------------===// @@ -15,12 +15,9 @@ #define POWERPC_TARGETMACHINE_H #include "PowerPCFrameInfo.h" -#include "PowerPCInstrInfo.h" #include "PowerPCJITInfo.h" #include "llvm/Target/TargetMachine.h" -#include "llvm/Target/TargetFrameInfo.h" #include "llvm/PassManager.h" -#include namespace llvm { @@ -28,20 +25,15 @@ class IntrinsicLowering; class PowerPCTargetMachine : public TargetMachine { - PowerPCInstrInfo InstrInfo; PowerPCFrameInfo FrameInfo; PowerPCJITInfo JITInfo; protected: PowerPCTargetMachine(const std::string &name, IntrinsicLowering *IL, const TargetData &TD, const PowerPCFrameInfo &TFI, - const PowerPCJITInfo &TJI, bool is64b); + const PowerPCJITInfo &TJI); public: - virtual const PowerPCInstrInfo *getInstrInfo() const { return &InstrInfo; } virtual const TargetFrameInfo *getFrameInfo() const { return &FrameInfo; } - virtual const MRegisterInfo *getRegisterInfo() const { - return &InstrInfo.getRegisterInfo(); - } virtual TargetJITInfo *getJITInfo() { return &JITInfo; } @@ -49,11 +41,6 @@ static unsigned getJITMatchQuality(); virtual bool addPassesToEmitAssembly(PassManager &PM, std::ostream &Out); - - // Two shared sets between the instruction selector and the printer allow for - // correct linkage on Darwin - std::set CalledFunctions; - std::set AddressTaken; }; } // end namespace llvm From brukman at cs.uiuc.edu Tue Aug 17 00:09:21 2004 From: brukman at cs.uiuc.edu (Misha Brukman) Date: Tue, 17 Aug 2004 00:09:21 -0500 Subject: [llvm-commits] CVS: llvm/lib/Target/PowerPC/PowerPC.td Message-ID: <200408170509.AAA04193@zion.cs.uiuc.edu> Changes in directory llvm/lib/Target/PowerPC: PowerPC.td updated: 1.6 -> 1.7 --- Log message: `PowerPC' is no longer a real target --- Diffs of the changes: (+0 -15) Index: llvm/lib/Target/PowerPC/PowerPC.td diff -u llvm/lib/Target/PowerPC/PowerPC.td:1.6 llvm/lib/Target/PowerPC/PowerPC.td:1.7 --- llvm/lib/Target/PowerPC/PowerPC.td:1.6 Tue Aug 10 16:24:44 2004 +++ llvm/lib/Target/PowerPC/PowerPC.td Tue Aug 17 00:09:10 2004 @@ -28,18 +28,3 @@ "Arg3Type", "Arg4Type", "VMX", "PPC64"]; let TSFlagsShifts = [ 0, 3, 8, 13, 18, 23, 28, 29 ]; } - -def PowerPC : Target { - // Pointers are 32-bits in size. - let PointerType = i32; - - // According to the Mach-O Runtime ABI, these regs are nonvolatile across - // calls - let CalleeSavedRegisters = [R1, R13, R14, R15, R16, R17, R18, R19, - R20, R21, R22, R23, R24, R25, R26, R27, R28, R29, R30, R31, F14, F15, - F16, F17, F18, F19, F20, F21, F22, F23, F24, F25, F26, F27, F28, F29, - F30, F31, CR2, CR3, CR4, LR]; - - // Pull in Instruction Info: - let InstructionSet = PowerPCInstrInfo; -} From brukman at cs.uiuc.edu Tue Aug 17 00:09:49 2004 From: brukman at cs.uiuc.edu (Misha Brukman) Date: Tue, 17 Aug 2004 00:09:49 -0500 Subject: [llvm-commits] CVS: llvm/lib/Target/PowerPC/PowerPCFrameInfo.h Message-ID: <200408170509.AAA04254@zion.cs.uiuc.edu> Changes in directory llvm/lib/Target/PowerPC: PowerPCFrameInfo.h updated: 1.3 -> 1.4 --- Log message: #include is not necessary here --- Diffs of the changes: (+2 -4) Index: llvm/lib/Target/PowerPC/PowerPCFrameInfo.h diff -u llvm/lib/Target/PowerPC/PowerPCFrameInfo.h:1.3 llvm/lib/Target/PowerPC/PowerPCFrameInfo.h:1.4 --- llvm/lib/Target/PowerPC/PowerPCFrameInfo.h:1.3 Mon Aug 16 00:09:58 2004 +++ llvm/lib/Target/PowerPC/PowerPCFrameInfo.h Tue Aug 17 00:09:39 2004 @@ -17,7 +17,6 @@ #include "llvm/Target/TargetFrameInfo.h" #include "llvm/Target/TargetMachine.h" #include "llvm/Target/MRegisterInfo.h" -#include namespace llvm { @@ -26,9 +25,8 @@ std::pair LR[1]; public: - - PowerPCFrameInfo(const TargetMachine &inTM) - : TargetFrameInfo(TargetFrameInfo::StackGrowsDown, 16, 0), TM(inTM) { + PowerPCFrameInfo(const TargetMachine &tm) + : TargetFrameInfo(TargetFrameInfo::StackGrowsDown, 16, 0), TM(tm) { LR[0].first = PPC::LR; LR[0].second = 8; } From brukman at cs.uiuc.edu Tue Aug 17 00:10:42 2004 From: brukman at cs.uiuc.edu (Misha Brukman) Date: Tue, 17 Aug 2004 00:10:42 -0500 Subject: [llvm-commits] CVS: llvm/lib/Target/PowerPC/PowerPCRegisterInfo.td Message-ID: <200408170510.AAA04369@zion.cs.uiuc.edu> Changes in directory llvm/lib/Target/PowerPC: PowerPCRegisterInfo.td updated: 1.12 -> 1.13 --- Log message: Register classes are target-dependent --- Diffs of the changes: (+0 -29) Index: llvm/lib/Target/PowerPC/PowerPCRegisterInfo.td diff -u llvm/lib/Target/PowerPC/PowerPCRegisterInfo.td:1.12 llvm/lib/Target/PowerPC/PowerPCRegisterInfo.td:1.13 --- llvm/lib/Target/PowerPC/PowerPCRegisterInfo.td:1.12 Sun Aug 15 20:52:12 2004 +++ llvm/lib/Target/PowerPC/PowerPCRegisterInfo.td Tue Aug 17 00:10:31 2004 @@ -71,32 +71,3 @@ // These are the "time base" registers which are read-only in user mode. def TBL : SPR<4>; def TBU : SPR<5>; - -/// Register classes -// Allocate volatiles first -// then nonvolatiles in reverse order since stmw/lmw save from rN to r31 -def GPRC : - RegisterClass -{ - let Methods = [{ - iterator allocation_order_begin(MachineFunction &MF) const { - return begin() + (AIX ? 1 : 0); - } - iterator allocation_order_end(MachineFunction &MF) const { - if (hasFP(MF)) - return end()-4; - else - return end()-3; - } - }]; -} - -def FPRC : RegisterClass; - -def CRRC : RegisterClass; - From brukman at cs.uiuc.edu Tue Aug 17 00:12:04 2004 From: brukman at cs.uiuc.edu (Misha Brukman) Date: Tue, 17 Aug 2004 00:12:04 -0500 Subject: [llvm-commits] CVS: llvm/lib/Target/PowerPC/Makefile Message-ID: <200408170512.AAA04432@zion.cs.uiuc.edu> Changes in directory llvm/lib/Target/PowerPC: Makefile updated: 1.10 -> 1.11 --- Log message: Rewrite targets/rules to generate files for just PowerPC or PPC{32,64} --- Diffs of the changes: (+18 -19) Index: llvm/lib/Target/PowerPC/Makefile diff -u llvm/lib/Target/PowerPC/Makefile:1.10 llvm/lib/Target/PowerPC/Makefile:1.11 --- llvm/lib/Target/PowerPC/Makefile:1.10 Sat Aug 14 17:06:38 2004 +++ llvm/lib/Target/PowerPC/Makefile Tue Aug 17 00:11:54 2004 @@ -13,39 +13,38 @@ TARGET = PowerPC # Make sure that tblgen is run, first thing. -$(SourceDepend): PowerPCGenRegisterInfo.h.inc PowerPCGenRegisterNames.inc \ - PowerPCGenRegisterInfo.inc PowerPCGenInstrNames.inc \ - PowerPCGenInstrInfo.inc PowerPCGenCodeEmitter.inc \ - PowerPCGenAsmWriter.inc +$(SourceDepend): PowerPCGenInstrNames.inc PowerPCGenRegisterNames.inc \ + PowerPCGenCodeEmitter.inc PowerPCGenAsmWriter.inc \ + PPC32GenRegisterInfo.h.inc PPC32GenRegisterInfo.inc PPC32GenInstrInfo.inc \ + PPC64GenRegisterInfo.h.inc PPC64GenRegisterInfo.inc PPC64GenInstrInfo.inc -TDFILES = $(SourceDir)/$(TARGET).td $(wildcard $(SourceDir)/*.td) \ - $(SourceDir)/../Target.td +TDFILES = $(wildcard $(SourceDir)/*.td) $(SourceDir)/../Target.td -$(TARGET)GenRegisterNames.inc:: $(TDFILES) $(TBLGEN) - @echo "Building $(TARGET).td register names with tblgen" +%GenRegisterNames.inc:: PPC32.td $(TDFILES) $(TBLGEN) + @echo "Building PowerPC register names with tblgen" $(VERB) $(TBLGEN) -I $(BUILD_SRC_DIR) $< -gen-register-enums -o $@ -$(TARGET)GenRegisterInfo.h.inc:: $(TDFILES) $(TBLGEN) - @echo "Building $(TARGET).td register information header with tblgen" +%GenRegisterInfo.h.inc:: %.td $(TDFILES) $(TBLGEN) + @echo "Building `basename $<` register information header with tblgen" $(VERB) $(TBLGEN) -I $(BUILD_SRC_DIR) $< -gen-register-desc-header -o $@ -$(TARGET)GenRegisterInfo.inc:: $(TDFILES) $(TBLGEN) - @echo "Building $(TARGET).td register information implementation with tblgen" +%GenRegisterInfo.inc:: %.td $(TDFILES) $(TBLGEN) + @echo "Building `basename $<` register information implementation with tblgen" $(VERB) $(TBLGEN) -I $(BUILD_SRC_DIR) $< -gen-register-desc -o $@ -$(TARGET)GenInstrNames.inc:: $(TDFILES) $(TBLGEN) - @echo "Building $(TARGET).td instruction names with tblgen" +$(TARGET)GenInstrNames.inc:: PPC32.td $(TDFILES) $(TBLGEN) + @echo "Building $(TARGET) instruction names with tblgen" $(VERB) $(TBLGEN) -I $(BUILD_SRC_DIR) $< -gen-instr-enums -o $@ -$(TARGET)GenInstrInfo.inc:: $(TDFILES) $(TBLGEN) - @echo "Building $(TARGET).td instruction information with tblgen" +%GenInstrInfo.inc:: %.td $(TDFILES) $(TBLGEN) + @echo "Building $(TARGET) instruction information with tblgen" $(VERB) $(TBLGEN) -I $(BUILD_SRC_DIR) $< -gen-instr-desc -o $@ -$(TARGET)GenCodeEmitter.inc:: $(TDFILES) $(TBLGEN) - @echo "Building $(TARGET).td code emitter" +$(TARGET)GenCodeEmitter.inc:: PPC32.td $(TDFILES) $(TBLGEN) + @echo "Building $(TARGET) code emitter" $(VERB) $(TBLGEN) -I $(SourceDir) $< -gen-emitter -o $@ -$(TARGET)GenAsmWriter.inc:: $(TDFILES) $(TBLGEN) +$(TARGET)GenAsmWriter.inc:: PPC32.td $(TDFILES) $(TBLGEN) @echo "Building $(TARGET).td assembly writer with tblgen" $(VERB) $(TBLGEN) -I $(SourceDir) $< -gen-asm-writer -o $@ From lattner at cs.uiuc.edu Tue Aug 17 01:06:01 2004 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Tue, 17 Aug 2004 01:06:01 -0500 Subject: [llvm-commits] CVS: llvm/include/llvm/CodeGen/AsmPrinter.h Message-ID: <200408170606.BAA32322@apoc.cs.uiuc.edu> Changes in directory llvm/include/llvm/CodeGen: AsmPrinter.h updated: 1.2 -> 1.3 --- Log message: We now allow targets to use any prefix they want for global symbols. Lets hear it for ".". --- Diffs of the changes: (+4 -4) Index: llvm/include/llvm/CodeGen/AsmPrinter.h diff -u llvm/include/llvm/CodeGen/AsmPrinter.h:1.2 llvm/include/llvm/CodeGen/AsmPrinter.h:1.3 --- llvm/include/llvm/CodeGen/AsmPrinter.h:1.2 Mon Aug 16 21:28:12 2004 +++ llvm/include/llvm/CodeGen/AsmPrinter.h Tue Aug 17 01:05:48 2004 @@ -44,12 +44,12 @@ // Properties to be set by the derived class ctor, used to configure the // asmwriter. - /// UsesUnderscorePrefix - If this flag is set to true, all identifiers - /// printed by the asmwriter will include a '_' prefix. - bool UsesUnderscorePrefix; + /// GlobalPrefix - If this is set to a non-empty string, it is prepended + /// onto all global symbols. This is often used for "_" or ".". + const char *GlobalPrefix; AsmPrinter(std::ostream &o, TargetMachine &tm) - : O(o), TM(tm), UsesUnderscorePrefix(false) { } + : O(o), TM(tm), GlobalPrefix("") { } /// doInitialization - Set up the AsmPrinter when we are working on a new /// module. If your pass overrides this, it must make sure to explicitly From lattner at cs.uiuc.edu Tue Aug 17 01:06:31 2004 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Tue, 17 Aug 2004 01:06:31 -0500 Subject: [llvm-commits] CVS: llvm/lib/CodeGen/AsmPrinter.cpp Message-ID: <200408170606.BAA00314@apoc.cs.uiuc.edu> Changes in directory llvm/lib/CodeGen: AsmPrinter.cpp updated: 1.2 -> 1.3 --- Log message: We now allow targets to use any prefix they want for global symbols. Lets hear it for ".". --- Diffs of the changes: (+1 -1) Index: llvm/lib/CodeGen/AsmPrinter.cpp diff -u llvm/lib/CodeGen/AsmPrinter.cpp:1.2 llvm/lib/CodeGen/AsmPrinter.cpp:1.3 --- llvm/lib/CodeGen/AsmPrinter.cpp:1.2 Mon Aug 16 21:28:26 2004 +++ llvm/lib/CodeGen/AsmPrinter.cpp Tue Aug 17 01:06:19 2004 @@ -19,7 +19,7 @@ using namespace llvm; bool AsmPrinter::doInitialization(Module &M) { - Mang = new Mangler(M, UsesUnderscorePrefix); + Mang = new Mangler(M, GlobalPrefix); return false; } From lattner at cs.uiuc.edu Tue Aug 17 01:06:49 2004 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Tue, 17 Aug 2004 01:06:49 -0500 Subject: [llvm-commits] CVS: llvm/include/llvm/Support/Mangler.h Message-ID: <200408170606.BAA00326@apoc.cs.uiuc.edu> Changes in directory llvm/include/llvm/Support: Mangler.h updated: 1.10 -> 1.11 --- Log message: Allow an arbitrary prefix. --- Diffs of the changes: (+4 -4) Index: llvm/include/llvm/Support/Mangler.h diff -u llvm/include/llvm/Support/Mangler.h:1.10 llvm/include/llvm/Support/Mangler.h:1.11 --- llvm/include/llvm/Support/Mangler.h:1.10 Thu Jul 8 17:09:07 2004 +++ llvm/include/llvm/Support/Mangler.h Tue Aug 17 01:06:37 2004 @@ -31,7 +31,7 @@ std::set MangledGlobals; Module &M; - bool AddUnderscorePrefix; + const char *Prefix; unsigned TypeCounter; std::map TypeMap; @@ -44,9 +44,9 @@ void InsertName(GlobalValue *GV, std::map &Names); public: - // Mangler ctor - if AddUnderscorePrefix is true, then all public global - // symbols will be prefixed with an underscore. - Mangler(Module &M, bool AddUnderscorePrefix = false); + // Mangler ctor - if a prefix is specified, it will be prepended onto all + // symbols. + Mangler(Module &M, const char *Prefix = ""); /// getTypeID - Return a unique ID for the specified LLVM type. /// From lattner at cs.uiuc.edu Tue Aug 17 01:07:05 2004 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Tue, 17 Aug 2004 01:07:05 -0500 Subject: [llvm-commits] CVS: llvm/lib/VMCore/Mangler.cpp Message-ID: <200408170607.BAA00336@apoc.cs.uiuc.edu> Changes in directory llvm/lib/VMCore: Mangler.cpp updated: 1.13 -> 1.14 --- Log message: Allow an arbitrary prefix --- Diffs of the changes: (+3 -4) Index: llvm/lib/VMCore/Mangler.cpp diff -u llvm/lib/VMCore/Mangler.cpp:1.13 llvm/lib/VMCore/Mangler.cpp:1.14 --- llvm/lib/VMCore/Mangler.cpp:1.13 Thu Jul 8 17:09:34 2004 +++ llvm/lib/VMCore/Mangler.cpp Tue Aug 17 01:06:54 2004 @@ -75,8 +75,7 @@ if (gv && isa(gv) && cast(gv)->getIntrinsicID()) { name = gv->getName(); // Is an intrinsic function } else if (gv && !gv->hasInternalLinkage() && !MangledGlobals.count(gv)) { - name = makeNameProper(gv->getName()); - if (AddUnderscorePrefix) name = "_" + name; + name = Prefix + makeNameProper(gv->getName()); } else { // Non-global, or global with internal linkage / colliding name // -> mangle. @@ -115,8 +114,8 @@ } -Mangler::Mangler(Module &m, bool addUnderscorePrefix) - : M(m), AddUnderscorePrefix(addUnderscorePrefix), TypeCounter(0), Count(0) { +Mangler::Mangler(Module &m, const char *prefix) + : M(m), Prefix(prefix), TypeCounter(0), Count(0) { // Calculate which global values have names that will collide when we throw // away type information. std::map Names; From lattner at cs.uiuc.edu Tue Aug 17 01:07:54 2004 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Tue, 17 Aug 2004 01:07:54 -0500 Subject: [llvm-commits] CVS: llvm/lib/Target/PowerPC/PPC32AsmPrinter.cpp PPC64AsmPrinter.cpp Message-ID: <200408170607.BAA01041@apoc.cs.uiuc.edu> Changes in directory llvm/lib/Target/PowerPC: PPC32AsmPrinter.cpp updated: 1.47 -> 1.48 PPC64AsmPrinter.cpp updated: 1.6 -> 1.7 --- Log message: New, more general, interface. --- Diffs of the changes: (+2 -2) Index: llvm/lib/Target/PowerPC/PPC32AsmPrinter.cpp diff -u llvm/lib/Target/PowerPC/PPC32AsmPrinter.cpp:1.47 llvm/lib/Target/PowerPC/PPC32AsmPrinter.cpp:1.48 --- llvm/lib/Target/PowerPC/PPC32AsmPrinter.cpp:1.47 Mon Aug 16 23:55:41 2004 +++ llvm/lib/Target/PowerPC/PPC32AsmPrinter.cpp Tue Aug 17 01:07:43 2004 @@ -45,7 +45,7 @@ PPC32AsmPrinter(std::ostream &O, TargetMachine &TM) : AsmPrinter(O, TM), LabelNumber(0) { - UsesUnderscorePrefix = 1; + GlobalPrefix = "_"; } /// Unique incrementer for label values for referencing Global values. Index: llvm/lib/Target/PowerPC/PPC64AsmPrinter.cpp diff -u llvm/lib/Target/PowerPC/PPC64AsmPrinter.cpp:1.6 llvm/lib/Target/PowerPC/PPC64AsmPrinter.cpp:1.7 --- llvm/lib/Target/PowerPC/PPC64AsmPrinter.cpp:1.6 Mon Aug 16 23:57:37 2004 +++ llvm/lib/Target/PowerPC/PPC64AsmPrinter.cpp Tue Aug 17 01:07:43 2004 @@ -666,7 +666,7 @@ O << '\n'; } - Mang = new Mangler(M, true); + Mang = new Mangler(M, "_"); return false; // success } From lattner at cs.uiuc.edu Tue Aug 17 01:36:39 2004 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Tue, 17 Aug 2004 01:36:39 -0500 Subject: [llvm-commits] CVS: llvm/include/llvm/CodeGen/AsmPrinter.h Message-ID: <200408170636.BAA08694@apoc.cs.uiuc.edu> Changes in directory llvm/include/llvm/CodeGen: AsmPrinter.h updated: 1.3 -> 1.4 --- Log message: Add some hooks --- Diffs of the changes: (+31 -1) Index: llvm/include/llvm/CodeGen/AsmPrinter.h diff -u llvm/include/llvm/CodeGen/AsmPrinter.h:1.3 llvm/include/llvm/CodeGen/AsmPrinter.h:1.4 --- llvm/include/llvm/CodeGen/AsmPrinter.h:1.3 Tue Aug 17 01:05:48 2004 +++ llvm/include/llvm/CodeGen/AsmPrinter.h Tue Aug 17 01:36:27 2004 @@ -41,6 +41,7 @@ /// std::string CurrentFnName; + //===------------------------------------------------------------------===// // Properties to be set by the derived class ctor, used to configure the // asmwriter. @@ -48,8 +49,33 @@ /// onto all global symbols. This is often used for "_" or ".". const char *GlobalPrefix; + /// ZeroDirective - this should be set to the directive used to get some + /// number of zero bytes emitted to the current section. Common cases are + /// "\t.zero\t" and "\t.space\t". If this is set to null, the + /// Data*bitsDirective's will be used to emit zero bytes. + const char *ZeroDirective; // Defaults to "\t.zero\t" + + /// AsciiDirective - This directive allows emission of an ascii string with + /// the standard C escape characters embedded into it. + const char *AsciiDirective; + + /// DataDirectives - These directives are used to output some unit of + /// integer data to the current section. If a data directive is set to + /// null, smaller data directives will be used to emit the large sizes. + const char *Data8bitsDirective; // Defaults to "\t.byte\t" + const char *Data16bitsDirective; // Defaults to "\t.short\t" + const char *Data32bitsDirective; // Defaults to "\t.long\t" + const char *Data64bitsDirective; // Defaults to "\t.quad\t" + AsmPrinter(std::ostream &o, TargetMachine &tm) - : O(o), TM(tm), GlobalPrefix("") { } + : O(o), TM(tm), + GlobalPrefix(""), + ZeroDirective("\t.zero\t"), + AsciiDirective("\t.ascii\t"), + Data8bitsDirective("\t.byte\t"), + Data16bitsDirective("\t.short\t"), + Data32bitsDirective(".long\t"), + Data64bitsDirective("\t.quad\t") { } /// doInitialization - Set up the AsmPrinter when we are working on a new /// module. If your pass overrides this, it must make sure to explicitly @@ -67,6 +93,10 @@ /// emitConstantValueOnly - Print out the specified constant, without a /// storage class. Only constants of first-class type are allowed here. void emitConstantValueOnly(const Constant *CV); + + /// emitGlobalConstant - Print a general LLVM constant to the .s file. + /// + void emitGlobalConstant(const Constant* CV); }; } From lattner at cs.uiuc.edu Tue Aug 17 01:37:02 2004 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Tue, 17 Aug 2004 01:37:02 -0500 Subject: [llvm-commits] CVS: llvm/lib/CodeGen/AsmPrinter.cpp Message-ID: <200408170637.BAA08707@apoc.cs.uiuc.edu> Changes in directory llvm/lib/CodeGen: AsmPrinter.cpp updated: 1.3 -> 1.4 --- Log message: Implement emitGlobalConstant --- Diffs of the changes: (+161 -0) Index: llvm/lib/CodeGen/AsmPrinter.cpp diff -u llvm/lib/CodeGen/AsmPrinter.cpp:1.3 llvm/lib/CodeGen/AsmPrinter.cpp:1.4 --- llvm/lib/CodeGen/AsmPrinter.cpp:1.3 Tue Aug 17 01:06:19 2004 +++ llvm/lib/CodeGen/AsmPrinter.cpp Tue Aug 17 01:36:49 2004 @@ -108,3 +108,164 @@ assert(0 && "Unknown constant value!"); } } + +/// toOctal - Convert the low order bits of X into an octal digit. +/// +static inline char toOctal(int X) { + return (X&7)+'0'; +} + +/// getAsCString - Return the specified array as a C compatible string, only if +/// the predicate isString is true. +/// +static void printAsCString(std::ostream &O, const ConstantArray *CVA) { + assert(CVA->isString() && "Array is not string compatible!"); + + O << "\""; + for (unsigned i = 0; i != CVA->getNumOperands(); ++i) { + unsigned char C = cast(CVA->getOperand(i))->getRawValue(); + + if (C == '"') { + O << "\\\""; + } else if (C == '\\') { + O << "\\\\"; + } else if (isprint(C)) { + O << C; + } else { + switch(C) { + case '\b': O << "\\b"; break; + case '\f': O << "\\f"; break; + case '\n': O << "\\n"; break; + case '\r': O << "\\r"; break; + case '\t': O << "\\t"; break; + default: + O << '\\'; + O << toOctal(C >> 6); + O << toOctal(C >> 3); + O << toOctal(C >> 0); + break; + } + } + } + O << "\""; +} + +/// emitGlobalConstant - Print a general LLVM constant to the .s file. +/// +void AsmPrinter::emitGlobalConstant(const Constant *CV) { + const TargetData &TD = TM.getTargetData(); + + if (CV->isNullValue()) { + O << ZeroDirective << TD.getTypeSize(CV->getType()) << "\n"; + return; + } else if (const ConstantArray *CVA = dyn_cast(CV)) { + if (CVA->isString()) { + O << AsciiDirective; + printAsCString(O, CVA); + O << "\n"; + } else { // Not a string. Print the values in successive locations + for (unsigned i = 0, e = CVA->getNumOperands(); i != e; ++i) + emitGlobalConstant(CVA->getOperand(i)); + } + return; + } else if (const ConstantStruct *CVS = dyn_cast(CV)) { + // Print the fields in successive locations. Pad to align if needed! + const StructLayout *cvsLayout = TD.getStructLayout(CVS->getType()); + unsigned sizeSoFar = 0; + for (unsigned i = 0, e = CVS->getNumOperands(); i != e; ++i) { + const Constant* field = CVS->getOperand(i); + + // Check if padding is needed and insert one or more 0s. + unsigned fieldSize = TD.getTypeSize(field->getType()); + unsigned padSize = ((i == e-1? cvsLayout->StructSize + : cvsLayout->MemberOffsets[i+1]) + - cvsLayout->MemberOffsets[i]) - fieldSize; + sizeSoFar += fieldSize + padSize; + + // Now print the actual field value + emitGlobalConstant(field); + + // Insert the field padding unless it's zero bytes... + if (padSize) + O << ZeroDirective << padSize << "\n"; + } + assert(sizeSoFar == cvsLayout->StructSize && + "Layout of constant struct may be incorrect!"); + return; + } else if (const ConstantFP *CFP = dyn_cast(CV)) { + // FP Constants are printed as integer constants to avoid losing + // precision... + double Val = CFP->getValue(); + if (CFP->getType() == Type::DoubleTy) { + union DU { // Abide by C TBAA rules + double FVal; + uint64_t UVal; + } U; + U.FVal = Val; + + if (TD.isBigEndian()) { + O << Data32bitsDirective << unsigned(U.UVal >> 32) + << "\t; double most significant word " << Val << "\n"; + O << Data32bitsDirective << unsigned(U.UVal) + << "\t; double least significant word " << Val << "\n"; + } else { + O << Data32bitsDirective << unsigned(U.UVal) + << "\t; double least significant word " << Val << "\n"; + O << Data32bitsDirective << unsigned(U.UVal >> 32) + << "\t; double most significant word " << Val << "\n"; + } + return; + } else { + union FU { // Abide by C TBAA rules + float FVal; + int32_t UVal; + } U; + U.FVal = Val; + + O << Data32bitsDirective << U.UVal << "\t; float " << Val << "\n"; + return; + } + } else if (CV->getType() == Type::ULongTy || CV->getType() == Type::LongTy) { + if (const ConstantInt *CI = dyn_cast(CV)) { + uint64_t Val = CI->getRawValue(); + + if (TD.isBigEndian()) { + O << Data32bitsDirective << unsigned(Val >> 32) + << "\t; Double-word most significant word " << Val << "\n"; + O << Data32bitsDirective << unsigned(Val) + << "\t; Double-word least significant word " << Val << "\n"; + } else { + O << Data32bitsDirective << unsigned(Val) + << "\t; Double-word least significant word " << Val << "\n"; + O << Data32bitsDirective << unsigned(Val >> 32) + << "\t; Double-word most significant word " << Val << "\n"; + } + return; + } + } + + const Type *type = CV->getType(); + O << "\t"; + switch (type->getTypeID()) { + case Type::UByteTyID: case Type::SByteTyID: + O << Data8bitsDirective; + break; + case Type::UShortTyID: case Type::ShortTyID: + O << Data16bitsDirective; + break; + case Type::BoolTyID: + case Type::PointerTyID: + case Type::UIntTyID: case Type::IntTyID: + O << Data32bitsDirective; + break; + case Type::ULongTyID: case Type::LongTyID: + assert (0 && "Should have already output double-word constant."); + case Type::FloatTyID: case Type::DoubleTyID: + assert (0 && "Should have already output floating point constant."); + default: + assert (0 && "Can't handle printing this type of thing"); + break; + } + emitConstantValueOnly(CV); + O << "\n"; +} From lattner at cs.uiuc.edu Tue Aug 17 01:37:24 2004 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Tue, 17 Aug 2004 01:37:24 -0500 Subject: [llvm-commits] CVS: llvm/lib/Target/PowerPC/PPC32AsmPrinter.cpp Message-ID: <200408170637.BAA08717@apoc.cs.uiuc.edu> Changes in directory llvm/lib/Target/PowerPC: PPC32AsmPrinter.cpp updated: 1.48 -> 1.49 --- Log message: Use the emitGlobalConstant defined in AsmPrinter --- Diffs of the changes: (+2 -163) Index: llvm/lib/Target/PowerPC/PPC32AsmPrinter.cpp diff -u llvm/lib/Target/PowerPC/PPC32AsmPrinter.cpp:1.48 llvm/lib/Target/PowerPC/PPC32AsmPrinter.cpp:1.49 --- llvm/lib/Target/PowerPC/PPC32AsmPrinter.cpp:1.48 Tue Aug 17 01:07:43 2004 +++ llvm/lib/Target/PowerPC/PPC32AsmPrinter.cpp Tue Aug 17 01:37:12 2004 @@ -46,6 +46,8 @@ PPC32AsmPrinter(std::ostream &O, TargetMachine &TM) : AsmPrinter(O, TM), LabelNumber(0) { GlobalPrefix = "_"; + ZeroDirective = "\t.space\t"; // ".space N" emits N zeros. + Data64bitsDirective = 0; // we can't emit a 64-bit unit } /// Unique incrementer for label values for referencing Global values. @@ -90,7 +92,6 @@ void printConstantPool(MachineConstantPool *MCP); bool runOnMachineFunction(MachineFunction &F); bool doFinalization(Module &M); - void emitGlobalConstant(const Constant* CV); }; } // end of anonymous namespace @@ -106,168 +107,6 @@ // Include the auto-generated portion of the assembly writer #include "PowerPCGenAsmWriter.inc" -/// toOctal - Convert the low order bits of X into an octal digit. -/// -static inline char toOctal(int X) { - return (X&7)+'0'; -} - -/// getAsCString - Return the specified array as a C compatible -/// string, only if the predicate isString is true. -/// -static void printAsCString(std::ostream &O, const ConstantArray *CVA) { - assert(CVA->isString() && "Array is not string compatible!"); - - O << "\""; - for (unsigned i = 0; i != CVA->getNumOperands(); ++i) { - unsigned char C = cast(CVA->getOperand(i))->getRawValue(); - - if (C == '"') { - O << "\\\""; - } else if (C == '\\') { - O << "\\\\"; - } else if (isprint(C)) { - O << C; - } else { - switch(C) { - case '\b': O << "\\b"; break; - case '\f': O << "\\f"; break; - case '\n': O << "\\n"; break; - case '\r': O << "\\r"; break; - case '\t': O << "\\t"; break; - default: - O << '\\'; - O << toOctal(C >> 6); - O << toOctal(C >> 3); - O << toOctal(C >> 0); - break; - } - } - } - O << "\""; -} - -// Print a constant value or values, with the appropriate storage class as a -// prefix. -void PPC32AsmPrinter::emitGlobalConstant(const Constant *CV) { - const TargetData &TD = TM.getTargetData(); - - if (CV->isNullValue()) { - O << "\t.space\t" << TD.getTypeSize(CV->getType()) << "\n"; - return; - } else if (const ConstantArray *CVA = dyn_cast(CV)) { - if (CVA->isString()) { - O << "\t.ascii\t"; - printAsCString(O, CVA); - O << "\n"; - } else { // Not a string. Print the values in successive locations - for (unsigned i = 0, e = CVA->getNumOperands(); i != e; ++i) - emitGlobalConstant(CVA->getOperand(i)); - } - return; - } else if (const ConstantStruct *CVS = dyn_cast(CV)) { - // Print the fields in successive locations. Pad to align if needed! - const StructLayout *cvsLayout = TD.getStructLayout(CVS->getType()); - unsigned sizeSoFar = 0; - for (unsigned i = 0, e = CVS->getNumOperands(); i != e; ++i) { - const Constant* field = CVS->getOperand(i); - - // Check if padding is needed and insert one or more 0s. - unsigned fieldSize = TD.getTypeSize(field->getType()); - unsigned padSize = ((i == e-1? cvsLayout->StructSize - : cvsLayout->MemberOffsets[i+1]) - - cvsLayout->MemberOffsets[i]) - fieldSize; - sizeSoFar += fieldSize + padSize; - - // Now print the actual field value - emitGlobalConstant(field); - - // Insert the field padding unless it's zero bytes... - if (padSize) - O << "\t.space\t " << padSize << "\n"; - } - assert(sizeSoFar == cvsLayout->StructSize && - "Layout of constant struct may be incorrect!"); - return; - } else if (const ConstantFP *CFP = dyn_cast(CV)) { - // FP Constants are printed as integer constants to avoid losing - // precision... - double Val = CFP->getValue(); - if (CFP->getType() == Type::DoubleTy) { - union DU { // Abide by C TBAA rules - double FVal; - uint64_t UVal; - } U; - U.FVal = Val; - - if (TD.isBigEndian()) { - O << ".long\t" << unsigned(U.UVal >> 32) - << "\t; double most significant word " << Val << "\n"; - O << ".long\t" << unsigned(U.UVal) - << "\t; double least significant word " << Val << "\n"; - } else { - O << ".long\t" << unsigned(U.UVal) - << "\t; double least significant word " << Val << "\n"; - O << ".long\t" << unsigned(U.UVal >> 32) - << "\t; double most significant word " << Val << "\n"; - } - return; - } else { - union FU { // Abide by C TBAA rules - float FVal; - int32_t UVal; - } U; - U.FVal = Val; - - O << ".long\t" << U.UVal << "\t; float " << Val << "\n"; - return; - } - } else if (CV->getType() == Type::ULongTy || CV->getType() == Type::LongTy) { - if (const ConstantInt *CI = dyn_cast(CV)) { - uint64_t Val = CI->getRawValue(); - - if (TD.isBigEndian()) { - O << ".long\t" << unsigned(Val >> 32) - << "\t; Double-word most significant word " << Val << "\n"; - O << ".long\t" << unsigned(Val) - << "\t; Double-word least significant word " << Val << "\n"; - } else { - O << ".long\t" << unsigned(Val) - << "\t; Double-word least significant word " << Val << "\n"; - O << ".long\t" << unsigned(Val >> 32) - << "\t; Double-word most significant word " << Val << "\n"; - } - return; - } - } - - const Type *type = CV->getType(); - O << "\t"; - switch (type->getTypeID()) { - case Type::UByteTyID: case Type::SByteTyID: - O << ".byte"; - break; - case Type::UShortTyID: case Type::ShortTyID: - O << ".short"; - break; - case Type::BoolTyID: - case Type::PointerTyID: - case Type::UIntTyID: case Type::IntTyID: - O << ".long"; - break; - case Type::ULongTyID: case Type::LongTyID: - assert (0 && "Should have already output double-word constant."); - case Type::FloatTyID: case Type::DoubleTyID: - assert (0 && "Should have already output floating point constant."); - default: - assert (0 && "Can't handle printing this type of thing"); - break; - } - O << "\t"; - emitConstantValueOnly(CV); - O << "\n"; -} - /// printConstantPool - Print to the current output stream assembly /// representations of the constants in the constant pool MCP. This is /// used to print out constants which have been "spilled to memory" by From lattner at cs.uiuc.edu Tue Aug 17 01:48:28 2004 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Tue, 17 Aug 2004 01:48:28 -0500 Subject: [llvm-commits] CVS: llvm/lib/CodeGen/AsmPrinter.cpp Message-ID: <200408170648.BAA11451@apoc.cs.uiuc.edu> Changes in directory llvm/lib/CodeGen: AsmPrinter.cpp updated: 1.4 -> 1.5 --- Log message: Add support for targets that have .quad, drop extra tab inserted --- Diffs of the changes: (+6 -6) Index: llvm/lib/CodeGen/AsmPrinter.cpp diff -u llvm/lib/CodeGen/AsmPrinter.cpp:1.4 llvm/lib/CodeGen/AsmPrinter.cpp:1.5 --- llvm/lib/CodeGen/AsmPrinter.cpp:1.4 Tue Aug 17 01:36:49 2004 +++ llvm/lib/CodeGen/AsmPrinter.cpp Tue Aug 17 01:48:16 2004 @@ -31,11 +31,8 @@ void AsmPrinter::setupMachineFunction(MachineFunction &MF) { // What's my mangled name? CurrentFnName = Mang->getValueName((Value*)MF.getFunction()); - } - - // Print out the specified constant, without a storage class. Only the // constants valid in constant expressions can occur here. void AsmPrinter::emitConstantValueOnly(const Constant *CV) { @@ -203,7 +200,9 @@ } U; U.FVal = Val; - if (TD.isBigEndian()) { + if (Data64bitsDirective) + O << Data64bitsDirective << U.UVal << "\n"; + else if (TD.isBigEndian()) { O << Data32bitsDirective << unsigned(U.UVal >> 32) << "\t; double most significant word " << Val << "\n"; O << Data32bitsDirective << unsigned(U.UVal) @@ -229,7 +228,9 @@ if (const ConstantInt *CI = dyn_cast(CV)) { uint64_t Val = CI->getRawValue(); - if (TD.isBigEndian()) { + if (Data64bitsDirective) + O << Data64bitsDirective << Val << "\n"; + else if (TD.isBigEndian()) { O << Data32bitsDirective << unsigned(Val >> 32) << "\t; Double-word most significant word " << Val << "\n"; O << Data32bitsDirective << unsigned(Val) @@ -245,7 +246,6 @@ } const Type *type = CV->getType(); - O << "\t"; switch (type->getTypeID()) { case Type::UByteTyID: case Type::SByteTyID: O << Data8bitsDirective; From lattner at cs.uiuc.edu Tue Aug 17 01:48:44 2004 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Tue, 17 Aug 2004 01:48:44 -0500 Subject: [llvm-commits] CVS: llvm/include/llvm/CodeGen/AsmPrinter.h Message-ID: <200408170648.BAA11463@apoc.cs.uiuc.edu> Changes in directory llvm/include/llvm/CodeGen: AsmPrinter.h updated: 1.4 -> 1.5 --- Log message: Add missing \t --- Diffs of the changes: (+1 -1) Index: llvm/include/llvm/CodeGen/AsmPrinter.h diff -u llvm/include/llvm/CodeGen/AsmPrinter.h:1.4 llvm/include/llvm/CodeGen/AsmPrinter.h:1.5 --- llvm/include/llvm/CodeGen/AsmPrinter.h:1.4 Tue Aug 17 01:36:27 2004 +++ llvm/include/llvm/CodeGen/AsmPrinter.h Tue Aug 17 01:48:34 2004 @@ -74,7 +74,7 @@ AsciiDirective("\t.ascii\t"), Data8bitsDirective("\t.byte\t"), Data16bitsDirective("\t.short\t"), - Data32bitsDirective(".long\t"), + Data32bitsDirective("\t.long\t"), Data64bitsDirective("\t.quad\t") { } /// doInitialization - Set up the AsmPrinter when we are working on a new From lattner at cs.uiuc.edu Tue Aug 17 01:49:05 2004 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Tue, 17 Aug 2004 01:49:05 -0500 Subject: [llvm-commits] CVS: llvm/lib/Target/X86/X86AsmPrinter.cpp Message-ID: <200408170649.BAA11473@apoc.cs.uiuc.edu> Changes in directory llvm/lib/Target/X86: X86AsmPrinter.cpp updated: 1.117 -> 1.118 --- Log message: Use the AsmPrinter emitGlobalConstant. --- Diffs of the changes: (+0 -137) Index: llvm/lib/Target/X86/X86AsmPrinter.cpp diff -u llvm/lib/Target/X86/X86AsmPrinter.cpp:1.117 llvm/lib/Target/X86/X86AsmPrinter.cpp:1.118 --- llvm/lib/Target/X86/X86AsmPrinter.cpp:1.117 Mon Aug 16 18:16:06 2004 +++ llvm/lib/Target/X86/X86AsmPrinter.cpp Tue Aug 17 01:48:55 2004 @@ -119,7 +119,6 @@ bool runOnMachineFunction(MachineFunction &F); bool doInitialization(Module &M); bool doFinalization(Module &M); - void emitGlobalConstant(const Constant* CV); }; } // end of anonymous namespace @@ -137,142 +136,6 @@ #include "X86GenAsmWriter.inc" -/// toOctal - Convert the low order bits of X into an octal digit. -/// -static inline char toOctal(int X) { - return (X&7)+'0'; -} - -/// getAsCString - Return the specified array as a C compatible -/// string, only if the predicate isStringCompatible is true. -/// -static void printAsCString(std::ostream &O, const ConstantArray *CVA) { - assert(CVA->isString() && "Array is not string compatible!"); - - O << "\""; - for (unsigned i = 0; i != CVA->getNumOperands(); ++i) { - unsigned char C = cast(CVA->getOperand(i))->getRawValue(); - - if (C == '"') { - O << "\\\""; - } else if (C == '\\') { - O << "\\\\"; - } else if (isprint(C)) { - O << C; - } else { - switch(C) { - case '\b': O << "\\b"; break; - case '\f': O << "\\f"; break; - case '\n': O << "\\n"; break; - case '\r': O << "\\r"; break; - case '\t': O << "\\t"; break; - default: - O << '\\'; - O << toOctal(C >> 6); - O << toOctal(C >> 3); - O << toOctal(C >> 0); - break; - } - } - } - O << "\""; -} - -// Print a constant value or values, with the appropriate storage class as a -// prefix. -void X86AsmPrinter::emitGlobalConstant(const Constant *CV) { - const TargetData &TD = TM.getTargetData(); - - if (CV->isNullValue()) { - O << "\t.zero\t " << TD.getTypeSize(CV->getType()) << "\n"; - return; - } else if (const ConstantArray *CVA = dyn_cast(CV)) { - if (CVA->isString()) { - O << "\t.ascii\t"; - printAsCString(O, CVA); - O << "\n"; - } else { // Not a string. Print the values in successive locations - for (unsigned i = 0, e = CVA->getNumOperands(); i != e; ++i) - emitGlobalConstant(CVA->getOperand(i)); - } - return; - } else if (const ConstantStruct *CVS = dyn_cast(CV)) { - // Print the fields in successive locations. Pad to align if needed! - const StructLayout *cvsLayout = TD.getStructLayout(CVS->getType()); - unsigned sizeSoFar = 0; - for (unsigned i = 0, e = CVS->getNumOperands(); i != e; ++i) { - const Constant* field = CVS->getOperand(i); - - // Check if padding is needed and insert one or more 0s. - unsigned fieldSize = TD.getTypeSize(field->getType()); - unsigned padSize = ((i == e-1? cvsLayout->StructSize - : cvsLayout->MemberOffsets[i+1]) - - cvsLayout->MemberOffsets[i]) - fieldSize; - sizeSoFar += fieldSize + padSize; - - // Now print the actual field value - emitGlobalConstant(field); - - // Insert the field padding unless it's zero bytes... - if (padSize) - O << "\t.zero\t " << padSize << "\n"; - } - assert(sizeSoFar == cvsLayout->StructSize && - "Layout of constant struct may be incorrect!"); - return; - } else if (const ConstantFP *CFP = dyn_cast(CV)) { - // FP Constants are printed as integer constants to avoid losing - // precision... - double Val = CFP->getValue(); - switch (CFP->getType()->getTypeID()) { - default: assert(0 && "Unknown floating point type!"); - case Type::FloatTyID: { - union FU { // Abide by C TBAA rules - float FVal; - unsigned UVal; - } U; - U.FVal = Val; - O << ".long\t" << U.UVal << "\t# float " << Val << "\n"; - return; - } - case Type::DoubleTyID: { - union DU { // Abide by C TBAA rules - double FVal; - uint64_t UVal; - } U; - U.FVal = Val; - O << ".quad\t" << U.UVal << "\t# double " << Val << "\n"; - return; - } - } - } - - const Type *type = CV->getType(); - O << "\t"; - switch (type->getTypeID()) { - case Type::BoolTyID: case Type::UByteTyID: case Type::SByteTyID: - O << ".byte"; - break; - case Type::UShortTyID: case Type::ShortTyID: - O << ".word"; - break; - case Type::FloatTyID: case Type::PointerTyID: - case Type::UIntTyID: case Type::IntTyID: - O << ".long"; - break; - case Type::DoubleTyID: - case Type::ULongTyID: case Type::LongTyID: - O << ".quad"; - break; - default: - assert (0 && "Can't handle printing this type of thing"); - break; - } - O << "\t"; - emitConstantValueOnly(CV); - O << "\n"; -} - /// printConstantPool - Print to the current output stream assembly /// representations of the constants in the constant pool MCP. This is /// used to print out constants which have been "spilled to memory" by From natebegeman at mac.com Tue Aug 17 02:17:55 2004 From: natebegeman at mac.com (Nate Begeman) Date: Tue, 17 Aug 2004 02:17:55 -0500 Subject: [llvm-commits] CVS: llvm/lib/Target/PowerPC/PPC32ISelSimple.cpp PPC32RegisterInfo.td PPC64RegisterInfo.td Message-ID: <200408170717.CAA04896@zion.cs.uiuc.edu> Changes in directory llvm/lib/Target/PowerPC: PPC32ISelSimple.cpp updated: 1.67 -> 1.68 PPC32RegisterInfo.td updated: 1.1 -> 1.2 PPC64RegisterInfo.td updated: 1.1 -> 1.2 --- Log message: Re-fix hiding the Frame Pointer from the register allocator in functions that have a frame pointer. This change fixes Burg. In addition, make the necessary changes to floating point code gen and constant loading after Chris Lattner's fixes to the asm writer. These changes fix MallocBench/gs --- Diffs of the changes: (+11 -23) Index: llvm/lib/Target/PowerPC/PPC32ISelSimple.cpp diff -u llvm/lib/Target/PowerPC/PPC32ISelSimple.cpp:1.67 llvm/lib/Target/PowerPC/PPC32ISelSimple.cpp:1.68 --- llvm/lib/Target/PowerPC/PPC32ISelSimple.cpp:1.67 Mon Aug 16 23:55:41 2004 +++ llvm/lib/Target/PowerPC/PPC32ISelSimple.cpp Tue Aug 17 02:17:44 2004 @@ -618,13 +618,14 @@ unsigned GlobalBase = makeAnotherReg(Type::IntTy); unsigned Reg1 = makeAnotherReg(Type::IntTy); unsigned Reg2 = makeAnotherReg(Type::IntTy); + unsigned Opcode = (Ty == Type::FloatTy) ? PPC::LFS : PPC::LFD; // Move value at base + distance into return reg copyGlobalBaseToRegister(MBB, IP, GlobalBase); BuildMI(*MBB, IP, PPC::LOADHiAddr, 2, Reg1).addReg(GlobalBase) .addConstantPoolIndex(CPI); BuildMI(*MBB, IP, PPC::LOADLoDirect, 2, Reg2).addReg(Reg1) .addConstantPoolIndex(CPI); - BuildMI(*MBB, IP, PPC::LFD, 2, R).addSImm(0).addReg(Reg2); + BuildMI(*MBB, IP, Opcode, 2, R).addSImm(0).addReg(Reg2); } else if (isa(C)) { // Copy zero (null pointer) to the register. BuildMI(*MBB, IP, PPC::LI, 1, R).addSImm(0); @@ -1824,16 +1825,10 @@ const Type *Ty = Op1->getType(); assert(Ty == Type::FloatTy || Ty == Type::DoubleTy && "Unknown FP type!"); - unsigned Opcode = OpcodeTab[1][OperatorClass]; - unsigned Op1Reg = getReg(Op1C, BB, IP); + unsigned Opcode = OpcodeTab[Ty == Type::DoubleTy][OperatorClass]; unsigned Op0Reg = getReg(Op0, BB, IP); - if (Ty == Type::DoubleTy) { - BuildMI(*BB, IP, Opcode, 2, DestReg).addReg(Op0Reg).addReg(Op1Reg); - } else { - unsigned TmpReg = makeAnotherReg(Type::DoubleTy); - BuildMI(*BB, IP, Opcode, 2, TmpReg).addReg(Op0Reg).addReg(Op1Reg); - BuildMI(*BB, IP, PPC::FRSP, 1, DestReg).addReg(TmpReg); - } + unsigned Op1Reg = getReg(Op1C, BB, IP); + BuildMI(*BB, IP, Opcode, 2, DestReg).addReg(Op0Reg).addReg(Op1Reg); return; } @@ -1851,21 +1846,14 @@ const Type *Ty = Op0C->getType(); assert(Ty == Type::FloatTy || Ty == Type::DoubleTy && "Unknown FP type!"); - unsigned Opcode = OpcodeTab[1][OperatorClass]; + unsigned Opcode = OpcodeTab[Ty == Type::DoubleTy][OperatorClass]; unsigned Op0Reg = getReg(Op0C, BB, IP); unsigned Op1Reg = getReg(Op1, BB, IP); - if (Ty == Type::DoubleTy) { - BuildMI(*BB, IP, Opcode, 2, DestReg).addReg(Op0Reg).addReg(Op1Reg); - } else { - unsigned TmpReg = makeAnotherReg(Type::DoubleTy); - BuildMI(*BB, IP, Opcode, 2, TmpReg).addReg(Op0Reg).addReg(Op1Reg); - BuildMI(*BB, IP, PPC::FRSP, 1, DestReg).addReg(TmpReg); - } + BuildMI(*BB, IP, Opcode, 2, DestReg).addReg(Op0Reg).addReg(Op1Reg); return; } unsigned Opcode = OpcodeTab[Op0->getType() != Type::FloatTy][OperatorClass]; - //unsigned Opcode = OpcodeTab[OperatorClass]; unsigned Op0r = getReg(Op0, BB, IP); unsigned Op1r = getReg(Op1, BB, IP); BuildMI(*BB, IP, Opcode, 2, DestReg).addReg(Op0r).addReg(Op1r); Index: llvm/lib/Target/PowerPC/PPC32RegisterInfo.td diff -u llvm/lib/Target/PowerPC/PPC32RegisterInfo.td:1.1 llvm/lib/Target/PowerPC/PPC32RegisterInfo.td:1.2 --- llvm/lib/Target/PowerPC/PPC32RegisterInfo.td:1.1 Mon Aug 16 23:55:41 2004 +++ llvm/lib/Target/PowerPC/PPC32RegisterInfo.td Tue Aug 17 02:17:44 2004 @@ -17,8 +17,8 @@ // then nonvolatiles in reverse order since stmw/lmw save from rN to r31 def GPRC : RegisterClass + R30, R29, R28, R27, R26, R25, R24, R23, R22, R21, R20, R19, R18, R17, + R16, R15, R14, R13, R31, R0, R1, LR]> { let Methods = [{ iterator allocation_order_begin(MachineFunction &MF) const { Index: llvm/lib/Target/PowerPC/PPC64RegisterInfo.td diff -u llvm/lib/Target/PowerPC/PPC64RegisterInfo.td:1.1 llvm/lib/Target/PowerPC/PPC64RegisterInfo.td:1.2 --- llvm/lib/Target/PowerPC/PPC64RegisterInfo.td:1.1 Mon Aug 16 23:57:37 2004 +++ llvm/lib/Target/PowerPC/PPC64RegisterInfo.td Tue Aug 17 02:17:44 2004 @@ -17,8 +17,8 @@ // then nonvolatiles in reverse order since stmw/lmw save from rN to r31 def GPRC : RegisterClass + R30, R29, R28, R27, R26, R25, R24, R23, R22, R21, R20, R19, R18, R17, + R16, R15, R14, R13, R31, R0, R1, LR]> { let Methods = [{ iterator allocation_order_begin(MachineFunction &MF) const { From reid at x10sys.com Tue Aug 17 02:43:53 2004 From: reid at x10sys.com (Reid Spencer) Date: Tue, 17 Aug 2004 02:43:53 -0500 Subject: [llvm-commits] CVS: llvm/docs/BytecodeFormat.html Message-ID: <200408170743.CAA05048@zion.cs.uiuc.edu> Changes in directory llvm/docs: BytecodeFormat.html updated: 1.26 -> 1.27 --- Log message: Documented the removal of alignment in version 4 bytecode files (version 3 was released with LLVM 1.3). Alignment of fields can add severe size to certain kinds of functions (those with lots of long format instructions) so we decided to do away with alignment altogether in this bc version. --- Diffs of the changes: (+29 -1) Index: llvm/docs/BytecodeFormat.html diff -u llvm/docs/BytecodeFormat.html:1.26 llvm/docs/BytecodeFormat.html:1.27 --- llvm/docs/BytecodeFormat.html:1.26 Mon Aug 16 19:49:03 2004 +++ llvm/docs/BytecodeFormat.html Tue Aug 17 02:43:43 2004 @@ -1556,6 +1556,34 @@

        + + +
        Aligned Data
        +
        +

        In version 1.3, certain data items were aligned to 32-bit boundaries. In + version 1.4, alignment of data was done away with completely. The need for + alignment has gone away and the only thing it adds is bytecode file size + overhead. In most cases this overhead was small. However, in functions with + large numbers of format 0 instructions (GEPs and PHIs with lots of parameters) + or regular instructions with large valued operands (e.g. because there's just + a lot of instructions in the function) the overhead can be extreme. In one + test case, the overhead was 44,000 bytes (34% of the total file size). + Consequently in release 1.4, the decision was made to eliminate alignment + altogether.

        +

        In version 1.3 format, the following bytecode constructs were aligned (i.e. + they were followed by one to three bytes of padding):

        +
          +
        • All blocks.
        • +
        • Instructions using the long format (format 0).
        • +
        • All call instructions that called a var args function.
        • +
        • The target triple (a string field at the end of the module block).
        • +
        • The version field (immediately following the signature).
        • +
        +

        None of these constructs are aligned in version 1.4

        +
        + + @@ -1656,7 +1684,7 @@ Reid Spencer and Chris Lattner
        The LLVM Compiler Infrastructure
        -Last modified: $Date: 2004/08/17 00:49:03 $ +Last modified: $Date: 2004/08/17 07:43:43 $ From reid at x10sys.com Tue Aug 17 02:45:24 2004 From: reid at x10sys.com (Reid Spencer) Date: Tue, 17 Aug 2004 02:45:24 -0500 Subject: [llvm-commits] CVS: llvm/lib/Bytecode/Writer/Writer.cpp WriterInternals.h Message-ID: <200408170745.CAA05080@zion.cs.uiuc.edu> Changes in directory llvm/lib/Bytecode/Writer: Writer.cpp updated: 1.74 -> 1.75 WriterInternals.h updated: 1.22 -> 1.23 --- Log message: Bytecode File Format Changes: - File format version number bumped to 4 - Writer will now align nothing - Reader now only expects alignment for version 3 or earlier --- Diffs of the changes: (+17 -30) Index: llvm/lib/Bytecode/Writer/Writer.cpp diff -u llvm/lib/Bytecode/Writer/Writer.cpp:1.74 llvm/lib/Bytecode/Writer/Writer.cpp:1.75 --- llvm/lib/Bytecode/Writer/Writer.cpp:1.74 Mon Aug 16 21:59:02 2004 +++ llvm/lib/Bytecode/Writer/Writer.cpp Tue Aug 17 02:45:14 2004 @@ -31,6 +31,12 @@ #include using namespace llvm; +/// This value needs to be incremented every time the bytecode format changes +/// so that the reader can distinguish which format of the bytecode file has +/// been written. +/// @brief The bytecode version number +const unsigned BCVersionNum = 4; + static RegisterPass X("emitbytecode", "Bytecode Writer"); static Statistic<> @@ -65,8 +71,7 @@ /// possible. This is useful because many of our "infinite" values are really /// very small most of the time; but can be large a few times. /// Data format used: If you read a byte with the high bit set, use the low -/// seven bits as data and then read another byte. Note that using this may -/// cause the output buffer to become unaligned. +/// seven bits as data and then read another byte. inline void BytecodeWriter::output_vbr(uint64_t i) { while (1) { if (i < 0x80) { // done? @@ -119,21 +124,10 @@ output_vbr((unsigned)i << 1); // Low order bit is clear. } -// align32 - emit the minimal number of bytes that will bring us to 32 bit -// alignment... -// -inline void BytecodeWriter::align32() { - int NumPads = (4-(Out.size() & 3)) & 3; // Bytes to get padding to 32 bits - while (NumPads--) Out.push_back((unsigned char)0xAB); -} - -inline void BytecodeWriter::output(const std::string &s, bool Aligned ) { +inline void BytecodeWriter::output(const std::string &s) { unsigned Len = s.length(); output_vbr(Len ); // Strings may have an arbitrary length... Out.insert(Out.end(), s.begin(), s.end()); - - if (Aligned) - align32(); // Make sure we are now aligned... } inline void BytecodeWriter::output_data(const void *Ptr, const void *End) { @@ -200,7 +194,6 @@ Writer.output(unsigned(Writer.size()-Loc), int(Loc-4)); else Writer.output(unsigned(Writer.size()-Loc) << 5 | (Id & 0x1F), int(Loc-4)); - Writer.align32(); // Blocks must ALWAYS be aligned } //===----------------------------------------------------------------------===// @@ -470,8 +463,6 @@ output_vbr(unsigned(Slot)); } } - - align32(); // We must maintain correct alignment! } @@ -529,7 +520,6 @@ assert(Slot >= 0 && "No slot number for value!?!?"); output_vbr((unsigned)Slot); } - align32(); // We must maintain correct alignment! } @@ -757,10 +747,11 @@ // Output the version identifier... we are currently on bytecode version #2, // which corresponds to LLVM v1.3. - unsigned Version = (3 << 4) | (unsigned)isBigEndian | (hasLongPointers << 1) | - (hasNoEndianness << 2) | (hasNoPointerSize << 3); + unsigned Version = (BCVersionNum << 4) | + (unsigned)isBigEndian | (hasLongPointers << 1) | + (hasNoEndianness << 2) | + (hasNoPointerSize << 3); output_vbr(Version); - align32(); // The Global type plane comes first { @@ -926,11 +917,11 @@ Module::lib_iterator LE = M->lib_end(); output_vbr( unsigned(LE - LI) ); // Put out the number of dependent libraries for ( ; LI != LE; ++LI ) { - output(*LI, /*aligned=*/false); + output(*LI); } // Output the target triple from the module - output(M->getTargetTriple(), /*aligned=*/ true); + output(M->getTargetTriple()); } void BytecodeWriter::outputInstructions(const Function *F) { @@ -1049,7 +1040,7 @@ TE = MST.type_end(); TI != TE; ++TI ) { // Symtab entry:[def slot #][name] output_typeid((unsigned)Table.getSlot(TI->second)); - output(TI->first, /*align=*/false); + output(TI->first); } // Now do each of the type planes in order. @@ -1075,7 +1066,7 @@ Slot = Table.getSlot(I->second); assert(Slot != -1 && "Value in symtab but has no slot number!!"); output_vbr((unsigned)Slot); - output(I->first, false); // Don't force alignment... + output(I->first); } } } Index: llvm/lib/Bytecode/Writer/WriterInternals.h diff -u llvm/lib/Bytecode/Writer/WriterInternals.h:1.22 llvm/lib/Bytecode/Writer/WriterInternals.h:1.23 --- llvm/lib/Bytecode/Writer/WriterInternals.h:1.22 Sun Jul 25 13:07:36 2004 +++ llvm/lib/Bytecode/Writer/WriterInternals.h Tue Aug 17 02:45:14 2004 @@ -92,11 +92,7 @@ /// @brief Signed 32-bit variable bit rate output primitive. inline void output_vbr(int i); - /// Emit the minimal number of bytes that will bring us to 32 bit alignment. - /// @brief 32-bit alignment output primitive - inline void align32(); - - inline void output(const std::string &s, bool Aligned = true); + inline void output(const std::string &s ); inline void output_data(const void *Ptr, const void *End); From reid at x10sys.com Tue Aug 17 02:45:24 2004 From: reid at x10sys.com (Reid Spencer) Date: Tue, 17 Aug 2004 02:45:24 -0500 Subject: [llvm-commits] CVS: llvm/lib/Bytecode/Reader/Reader.cpp Reader.h Message-ID: <200408170745.CAA05085@zion.cs.uiuc.edu> Changes in directory llvm/lib/Bytecode/Reader: Reader.cpp updated: 1.123 -> 1.124 Reader.h updated: 1.11 -> 1.12 --- Log message: Bytecode File Format Changes: - File format version number bumped to 4 - Writer will now align nothing - Reader now only expects alignment for version 3 or earlier --- Diffs of the changes: (+22 -8) Index: llvm/lib/Bytecode/Reader/Reader.cpp diff -u llvm/lib/Bytecode/Reader/Reader.cpp:1.123 llvm/lib/Bytecode/Reader/Reader.cpp:1.124 --- llvm/lib/Bytecode/Reader/Reader.cpp:1.123 Wed Aug 4 17:56:46 2004 +++ llvm/lib/Bytecode/Reader/Reader.cpp Tue Aug 17 02:45:14 2004 @@ -72,12 +72,14 @@ /// Align the buffer position to a 32 bit boundary inline void BytecodeReader::align32() { - BufPtr Save = At; - At = (const unsigned char *)((unsigned long)(At+3) & (~3UL)); - if (At > Save) - if (Handler) Handler->handleAlignment(At - Save); - if (At > BlockEnd) - error("Ran out of data while aligning!"); + if (hasAlignment) { + BufPtr Save = At; + At = (const unsigned char *)((unsigned long)(At+3) & (~3UL)); + if (At > Save) + if (Handler) Handler->handleAlignment(At - Save); + if (At > BlockEnd) + error("Ran out of data while aligning!"); + } } /// Read a whole unsigned integer @@ -1886,6 +1888,7 @@ hasLongBlockHeaders = false; has32BitTypes = false; hasNoDependentLibraries = false; + hasAlignment = false; switch (RevisionNum) { case 0: // LLVM 1.0, 1.1 release version @@ -1937,6 +1940,14 @@ // FALL THROUGH case 3: // LLVM 1.3 release version + /// LLVM 1.3 and earlier caused alignment bytes to be written on some block + /// boundaries and at the end of some strings. In extreme cases (e.g. lots + /// of GEP references to a constant array), this can increase the file size + /// by 30% or more. In version 1.4 alignment is done away with completely. + hasAlignment = true; + + // FALL THROUGH + case 4: break; default: Index: llvm/lib/Bytecode/Reader/Reader.h diff -u llvm/lib/Bytecode/Reader/Reader.h:1.11 llvm/lib/Bytecode/Reader/Reader.h:1.12 --- llvm/lib/Bytecode/Reader/Reader.h:1.11 Tue Aug 3 19:19:23 2004 +++ llvm/lib/Bytecode/Reader/Reader.h Tue Aug 17 02:45:14 2004 @@ -293,8 +293,11 @@ /// features, for use in future versions of LLVM. bool hasNoDependentLibraries; - /// LLVM 1.2 and earlier encoded the file version as part of the module block - /// but this information may be needed to + /// LLVM 1.3 and earlier caused blocks and other fields to start on 32-bit + /// aligned boundaries. This can lead to as much as 30% bytecode size overhead + /// in various corner cases (lots of long instructions). In LLVM 1.4, + /// alignment of bytecode fields was done away with completely. + bool hasAlignment; /// CompactionTypes - If a compaction table is active in the current function, /// this is the mapping that it contains. We keep track of what resolved type From reid at x10sys.com Tue Aug 17 03:02:07 2004 From: reid at x10sys.com (Reid Spencer) Date: Tue, 17 Aug 2004 03:02:07 -0500 Subject: [llvm-commits] CVS: llvm/docs/index.html Message-ID: <200408170802.DAA05248@zion.cs.uiuc.edu> Changes in directory llvm/docs: index.html updated: 1.25 -> 1.26 --- Log message: Add a reference to the ComilerDriver documentation. --- Diffs of the changes: (+5 -1) Index: llvm/docs/index.html diff -u llvm/docs/index.html:1.25 llvm/docs/index.html:1.26 --- llvm/docs/index.html:1.25 Mon Aug 16 10:19:02 2004 +++ llvm/docs/index.html Tue Aug 17 03:01:57 2004 @@ -156,6 +156,10 @@
      • Bugpoint automatic bug finder and test-case reducer description and usage information.
      • +
      • Compiler Driver (llvmc) - This document +describes the design and configuration of the LLVM compiler driver tool, +llvmc.
      • +
      @@ -195,6 +199,6 @@ src="http://www.w3.org/Icons/valid-html401" alt="Valid HTML 4.01!"> LLVM Compiler Infrastructure
      - Last modified: $Date: 2004/08/16 15:19:02 $ + Last modified: $Date: 2004/08/17 08:01:57 $ From reid at x10sys.com Tue Aug 17 04:18:48 2004 From: reid at x10sys.com (Reid Spencer) Date: Tue, 17 Aug 2004 04:18:48 -0500 Subject: [llvm-commits] CVS: llvm/docs/CompilerDriver.html Message-ID: <200408170918.EAA16618@zion.cs.uiuc.edu> Changes in directory llvm/docs: CompilerDriver.html updated: 1.2 -> 1.3 --- Log message: Documented (Java properties file like) syntax of config file format Added definitions for some of the configuration items. Made the document HTML 4.01 Strict compliant. Ran ispell on it. --- Diffs of the changes: (+186 -73) Index: llvm/docs/CompilerDriver.html diff -u llvm/docs/CompilerDriver.html:1.2 llvm/docs/CompilerDriver.html:1.3 --- llvm/docs/CompilerDriver.html:1.2 Tue Aug 10 11:40:56 2004 +++ llvm/docs/CompilerDriver.html Tue Aug 17 04:18:37 2004 @@ -12,7 +12,7 @@ margin-right: 1em; margin-bottom: 1em; } .td_left { border: 2px solid gray; text-align: left; } - + @@ -86,8 +86,7 @@ interfaces need to be understood).
    • Supports source language translator invocation via both dynamically loadable shared objects and invocation of an executable.
    • - -

      +
    @@ -96,7 +95,7 @@

    At a high level, llvmc operation is very simple. The basic action taken by llvmc is to simply invoke some tool or set of tools to fill the user's request for compilation. Every execution of llvmctakes the - following sequence of steps:
    + following sequence of steps:

    Collect Command Line Options
    The command line options provide the marching orders to llvmc @@ -108,9 +107,10 @@
    Based on the options and the suffixes of the filenames presented, a set of configuration files are read to configure the actions llvmc will take. Configuration files are provided by either LLVM or the front end - compiler tools that B invokes. These files determine what actions - llvmc will take in response to the user's request. See the section - on configuration for more details.
    + compiler tools that llvmc invokes. These files determine what + actions llvmc will take in response to the user's request. See + the section on configuration for more details. +
    Determine Phases To Execute
    Based on the command line options and configuration files, llvmc determines the compilation phases that @@ -132,18 +132,18 @@
    If any action fails (returns a non-zero result code), llvmc also fails and returns the result code from the failing action. If everything succeeds, llvmc will return a zero result code.
    -

    +

    llvmc's operation must be simple, regular and predictable. Developers need to be able to rely on it to take a consistent approach to compilation. For example, the invocation:

    -
    -   llvmc -O2 x.c y.c z.c -o xyz
    + + llvmc -O2 x.c y.c z.c -o xyz

    must produce exactly the same results as:

    -
    -   llvmc -O2 x.c
    -   llvmc -O2 y.c
    -   llvmc -O2 z.c
    -   llvmc -O2 x.o y.o z.o -o xyz
    + + llvmc -O2 x.c + llvmc -O2 y.c + llvmc -O2 z.c + llvmc -O2 x.o y.o z.o -o xyz

    To accomplish this, llvmc uses a very simple goal oriented procedure to do its work. The overall goal is to produce a functioning executable. To accomplish this, llvmc always attempts to execute a @@ -254,10 +254,11 @@

    An action, with regard to llvmc is a basic operation that it takes in order to fulfill the user's request. Each phase of compilation will invoke zero or more actions in order to accomplish that phase.

    -

    Actions come in two forms:

      +

      Actions come in two forms:

      +
      • Invokable Executables
      • Functions in a shared library
      • -

      + @@ -274,9 +275,9 @@ llvmc. Configuration information is relatively static for a given release of LLVM and a front end compiler. However, the details may change from release to release of either. Users are encouraged to simply use - the various options of the B command and ignore the configuration of - the tool. These configuration files are for compiler writers and LLVM - developers. Those wishing to simply use B don't need to understand + the various options of the llvmc command and ignore the configuration + of the tool. These configuration files are for compiler writers and LLVM + developers. Those wishing to simply use llvmc don't need to understand this section but it may be instructive on how the tool works.

      @@ -300,9 +301,9 @@ have the same capabilities. Some front ends will simply generate LLVM assembly code, others will be able to generate fully optimized byte code. In general, llvmc doesn't make any assumptions about the capabilities or command -line options of a sub-tool. It simply uses the details found in the configuration -files and leaves it to the compiler writer to specify the configuration -correctly.

      +line options of a sub-tool. It simply uses the details found in the +configuration files and leaves it to the compiler writer to specify the +configuration correctly.

      This approach means that new compiler front ends can be up and working very quickly. As a first cut, a front end can simply compile its source to raw @@ -336,15 +337,12 @@

      Configuration Files
      -

      File Types

      -

      There are two types of configuration files: the master configuration file - and the language specific configuration file. The master configuration file - contains the general configuration of llvmc itself and is supplied - with the tool. It contains information that is source language agnostic. - Language specific configuration files tell llvmc how to invoke the - language's compiler for a variety of different tasks and what other tools - are needed to backfill the compiler's missing features (e.g. - optimization).

      +

      File Contents

      +

      Each configuration file provides the details for a single source language + that is to be compiled. This configuration information tells llvmc + how to invoke the language's pre-processor, translator, optimizer, assembler + and linker. Note that a given source language needn't provide all these tools + as many of them exist in llvm currently.

      Directory Search

      llvmc always looks for files of a specific name. It uses the @@ -365,77 +363,192 @@

    1. If the configuration file sought still can't be found, llvmc will print an error message and exit.
    - The first file found in this search will be used. Other files with the same - name will be ignored even if they exist in one of the subsequent search +

    The first file found in this search will be used. Other files with the + same name will be ignored even if they exist in one of the subsequent search locations.

    File Names

    -

    In the directories searched, a file named master will be - recognized as the master configuration file for llvmc. Note that - users may override the master file with a copy in their home directory - but they are advised not to. This capability is only useful for compiler - implementers needing to alter the master configuration while developing - their compiler front end. When reading the configuration files, the master - files are always read first.

    -

    Language specific configuration files are given specific names to foster - faster lookup. The name of a given language specific configuration file is - the same as the suffix used to identify files containing source in that - language. For example, a configuration file for C++ source might be named - cpp, C, or cxx.

    +

    In the directories searched, each configuration file is given a specific + name to foster faster lookup (so llvmc doesn't have to do directory searches). + The name of a given language specific configuration file is simply the same + as the suffix used to identify files containing source in that language. + For example, a configuration file for C++ source might be named + cpp, C, or cxx. For languages that support multiple + file suffixes, multiple (probably identical) files (or symbolic links) will + need to be provided.

    What Gets Read

    -

    The master configuration file is always read. Which language specific - configuration files are read depends on the command line options and the - suffixes of the file names provided on llvmc's command line. Note +

    Which configuration files are read depends on the command line options and + the suffixes of the file names provided on llvmc's command line. Note that the --x LANGUAGE option alters the language that llvmc - uses for the subsequent files on the command line. Only the language - specific configuration files actually needed to complete llvmc's - task are read. Other language specific files will be ignored.

    + uses for the subsequent files on the command line. Only the configuration + files actually needed to complete llvmc's task are read. Other + language specific files will be ignored.

    Syntax
    -

    The syntax of the configuration files is yet to be determined. There are - two viable options remaining:
    +

    The syntax of the configuration files is very simple and somewhat + compatible with Java's property files. Here are the syntax rules:

      -
    • XML DTD Specific To llvmc
    • -
    • Windows .ini style file with numerous sections
    • -

    +
  • The file encoding is ASCII.
  • +
  • The file is line oriented. There should be one configuration item per + line. Lines are terminated by the newline character (0x0A).
  • +
  • A configuration item consists of a name, an = and a value.
  • +
  • A name consists of a sequence of identifiers separated by period.
  • +
  • An identifier consists of specific keywords made up of only lower case + and upper case letters (e.g. lang.name).
  • +
  • Values come in four flavors: booleans, integers, commands and + strings.
  • +
  • Valid "false" boolean values are false False FALSE no No NO + off Off and OFF.
  • +
  • Valid "true" boolean values are true True TRUE yes Yes YES + on On and ON.
  • +
  • Integers are simply sequences of digits.
  • +
  • Commands start with a program name and are followed by a sequence of + words that are passed to that program as command line arguments. Program + arguments that begin and end with the @ sign will have their value + substituted. Program names beginning with / are considered to be + absolute. Otherwise the PATH will be applied to find the program to + execute.
  • +
  • Strings are composed of multiple sequences of characters from the + character class [-A-Za-z0-9_:%+/\\|,] separated by white + space.
  • +
  • White space on a line is folded. Multiple blanks or tabs will be + reduced to a single blank.
  • +
  • White space before the configuration item's name is ignored.
  • +
  • White space on either side of the = is ignored.
  • +
  • White space in a string value is used to separate the individual + components of the string value but otherwise ignored.
  • +
  • Comments are introduced by the # character. Everything after a + # and before the end of line is ignored.
  • + - +
    -

    The following description of configuration items is syntax-less and simply - uses a naming hierarchy to describe the configuration items. Whatever - syntax is chosen will need to map the hierarchy to the given syntax.

    +

    The table below provides definitions of the allowed configuration items + that may appear in a configuration file. Every item has a default value and + does not need to appear in the configuration file. Missing items will have the + default value. Each identifier may appear as all lower case, first letter + capitalized or all upper case.

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + - + - + + + - - + + + + + + + + + translator generates. + + + + + + + + + + + + + - + - + + + + +
    Name Value Type DescriptionDefault

    LANG ITEMS

    lang.namestringProvides the common name for a language definition. + For example "C++", "Pascal", "FORTRAN", etc.blank
    lang.opt1stringSpecifies the parameters to give the optimizer when -O1 is + specified on the llvmc command line.-simplifycfg -instcombine -mem2reg
    lang.opt2stringSpecifies the parameters to give the optimizer when -O2 is + specified on the llvmc command line.TBD
    lang.opt3stringSpecifies the parameters to give the optimizer when -O3 is + specified on the llvmc command line.TBD
    lang.opt4stringSpecifies the parameters to give the optimizer when -O4 is + specified on the llvmc command line.TBD
    lang.opt5stringSpecifies the parameters to give the optimizer when -O5 is + specified on the llvmc command line.TBD

    PREPROCESSOR ITEMS

    preprocessor.commandcommandThis provides the command prototype that will be used + to run the preprocessor. Valid substitutions are @in@ for the + input file and @out@ for the output file. This is generally only + used with the -E option.<blank>
    Capabilities.hasPreProcessorpreprocessor.required booleanThis item specifies whether the language has a - pre-processing phase or not. This controls whether the B<-E> option works - for the language or not.This item specifies whether the pre-processing phase + is required by the language. If the value is true, then the + preprocessor.command value must not be blank. With this option, + llvmc will always run the preprocessor as it assumes that the + translation and optimization phases don't know how to pre-process their + input.false

    TRANSLATOR ITEMS

    Capabilities.outputFormat"bc" or "ll"translator.commandcommandThis provides the command prototype that will be used + to run the translator. Valid substitutions are @in@ for the + input file and @out@ for the output file.<blank>
    translator.outputnative, bytecode or assembly This item specifies the kind of output the language's - compiler generates. The choices are either bytecode (bc) or LLVM - assembly (ll).bytecode
    translator.preprocessesbooleanIndicates that the translator also preprocesses. If this is true, then + llvmc will skip the pre-processing phase whenever the final + phase is not pre-processing.false
    translator.optimizersbooleanIndicates that the translator also optimizes. If this is true, then + llvmc will skip the optimization phase whenever the final phase + is optimization or later.false
    Capabilities.understandsOptimizationtranslator.groks_dash_o booleanIndicates whether the compiler for this language understands the - -O options or notIndicates that the translator understands the intent of the + various -On options to llvmc. This will cause the + -On option to be based to the translator instead of the + equivalent options provided by lang.optn.false

    OPTIMIZER ITEMS

    ASSEMBLER ITEMS

    LINKER ITEMS

    @@ -502,7 +615,7 @@ src="http://www.w3.org/Icons/valid-html401" alt="Valid HTML 4.01!">Reid Spencer
    The LLVM Compiler Infrastructure
    -Last modified: $Date: 2004/08/10 16:40:56 $ +Last modified: $Date: 2004/08/17 09:18:37 $ From reid at x10sys.com Tue Aug 17 04:39:01 2004 From: reid at x10sys.com (Reid Spencer) Date: Tue, 17 Aug 2004 04:39:01 -0500 Subject: [llvm-commits] CVS: llvm/docs/Lexicon.html index.html Message-ID: <200408170939.EAA19304@zion.cs.uiuc.edu> Changes in directory llvm/docs: Lexicon.html added (r1.1) index.html updated: 1.26 -> 1.27 --- Log message: Added a *very* initial cut at a lexicon for LLVM. I don't plan to write this whole thing. Just use the pattern in the file to add entries as you think of them. This will be really helpful for newbies to advanced compiler optimization techniques such as myself. --- Diffs of the changes: (+65 -1) Index: llvm/docs/Lexicon.html diff -c /dev/null llvm/docs/Lexicon.html:1.1 *** /dev/null Tue Aug 17 04:39:00 2004 --- llvm/docs/Lexicon.html Tue Aug 17 04:38:50 2004 *************** *** 0 **** --- 1,61 ---- + + + + + The LLVM Lexicon + + + + + + +
    The LLVM Lexicon
    +

    NOTE: This document is a work in progress!

    + +
    Table Of Contents
    + +
    + + + + + + + +
    - A -
    ADCE
    +
    + + +
    Definitions
    + + + +
    +
    +
    ADCE
    +
    Aggressive Dead Code Elimination
    +
    +
    + + +
    +
    Valid CSS!Valid HTML 4.01!The LLVM Team
    + The LLVM Compiler Infrastructure
    + Last modified: $Date: 2004/08/17 09:38:50 $ +
    + + + Index: llvm/docs/index.html diff -u llvm/docs/index.html:1.26 llvm/docs/index.html:1.27 --- llvm/docs/index.html:1.26 Tue Aug 17 03:01:57 2004 +++ llvm/docs/index.html Tue Aug 17 04:38:50 2004 @@ -110,6 +110,9 @@
  • Coding Standards - Guidelines for hacking LLVM source.
  • +
  • The LLVM Lexicon - Definition of acronyms, terms +and concepts used in LLVM.
  • +
  • Doxygen generated documentation ( classes)
  • @@ -199,6 +202,6 @@ src="http://www.w3.org/Icons/valid-html401" alt="Valid HTML 4.01!"> LLVM Compiler Infrastructure
    - Last modified: $Date: 2004/08/17 08:01:57 $ + Last modified: $Date: 2004/08/17 09:38:50 $ From lattner at cs.uiuc.edu Tue Aug 17 10:46:02 2004 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Tue, 17 Aug 2004 10:46:02 -0500 Subject: [llvm-commits] CVS: llvm-www/demo/index.cgi Message-ID: <200408171546.KAA13119@apoc.cs.uiuc.edu> Changes in directory llvm-www/demo: index.cgi updated: 1.28 -> 1.29 --- Log message: Now that we're only getting a few hundred hits an hour, reenable the demo page. It should would be nice to get file locking on it tho :) --- Diffs of the changes: (+5 -4) Index: llvm-www/demo/index.cgi diff -u llvm-www/demo/index.cgi:1.28 llvm-www/demo/index.cgi:1.29 --- llvm-www/demo/index.cgi:1.28 Sat Aug 14 16:46:56 2004 +++ llvm-www/demo/index.cgi Tue Aug 17 10:45:51 2004 @@ -5,7 +5,7 @@ # doing remote web JO99C compilations. (It could still be used for that # purpose, though the two scripts have diverged somewhat.) # -# Last modified $Date: 2004/08/14 21:46:56 $ +# Last modified $Date: 2004/08/17 15:45:51 $ # use CGI; @@ -13,6 +13,7 @@ use Mail::Send; $| = 1; +my $DisableForm = 0; open( STDERR, ">&STDOUT" ) or die "can't redirect stderr to stdout"; @@ -193,8 +194,7 @@ ""; print ""; -##print "

    ", $c->submit, "\n", - +print "

    ", $c->submit, "\n" if (!$DisableForm); print $c->endform; print "\n

    If you have questions about the LLVM code generated by the @@ -210,7 +210,8 @@ sub sanitychecktools { my $sanitycheckfail = ''; - barf("The demo page is currently down due to high load, please try again later!"); + barf("The demo page is currently down due to high load, please try again later!") + if ($DisableLoad); # insert tool-specific sanity checks here $sanitycheckfail .= ' gccas' if `gccas --help 2>&1` !~ /assembler for GCC/; From lattner at cs.uiuc.edu Tue Aug 17 11:26:50 2004 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Tue, 17 Aug 2004 11:26:50 -0500 Subject: [llvm-commits] CVS: llvm/include/llvm/CodeGen/AsmPrinter.h Message-ID: <200408171626.LAA16062@apoc.cs.uiuc.edu> Changes in directory llvm/include/llvm/CodeGen: AsmPrinter.h updated: 1.5 -> 1.6 --- Log message: Allow targets to specify a comment character --- Diffs of the changes: (+6 -1) Index: llvm/include/llvm/CodeGen/AsmPrinter.h diff -u llvm/include/llvm/CodeGen/AsmPrinter.h:1.5 llvm/include/llvm/CodeGen/AsmPrinter.h:1.6 --- llvm/include/llvm/CodeGen/AsmPrinter.h:1.5 Tue Aug 17 01:48:34 2004 +++ llvm/include/llvm/CodeGen/AsmPrinter.h Tue Aug 17 11:26:36 2004 @@ -45,9 +45,13 @@ // Properties to be set by the derived class ctor, used to configure the // asmwriter. + /// CommentChar - This indicates the comment character used by the + /// assembler. + const char *CommentChar; + /// GlobalPrefix - If this is set to a non-empty string, it is prepended /// onto all global symbols. This is often used for "_" or ".". - const char *GlobalPrefix; + const char *GlobalPrefix; // Defaults to "" /// ZeroDirective - this should be set to the directive used to get some /// number of zero bytes emitted to the current section. Common cases are @@ -69,6 +73,7 @@ AsmPrinter(std::ostream &o, TargetMachine &tm) : O(o), TM(tm), + CommentChar("#"), GlobalPrefix(""), ZeroDirective("\t.zero\t"), AsciiDirective("\t.ascii\t"), From lattner at cs.uiuc.edu Tue Aug 17 11:27:16 2004 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Tue, 17 Aug 2004 11:27:16 -0500 Subject: [llvm-commits] CVS: llvm/lib/CodeGen/AsmPrinter.cpp Message-ID: <200408171627.LAA16073@apoc.cs.uiuc.edu> Changes in directory llvm/lib/CodeGen: AsmPrinter.cpp updated: 1.5 -> 1.6 --- Log message: Use a designated comment character when printing comments. --- Diffs of the changes: (+18 -9) Index: llvm/lib/CodeGen/AsmPrinter.cpp diff -u llvm/lib/CodeGen/AsmPrinter.cpp:1.5 llvm/lib/CodeGen/AsmPrinter.cpp:1.6 --- llvm/lib/CodeGen/AsmPrinter.cpp:1.5 Tue Aug 17 01:48:16 2004 +++ llvm/lib/CodeGen/AsmPrinter.cpp Tue Aug 17 11:27:05 2004 @@ -204,14 +204,18 @@ O << Data64bitsDirective << U.UVal << "\n"; else if (TD.isBigEndian()) { O << Data32bitsDirective << unsigned(U.UVal >> 32) - << "\t; double most significant word " << Val << "\n"; + << "\t" << CommentChar << " double most significant word " + << Val << "\n"; O << Data32bitsDirective << unsigned(U.UVal) - << "\t; double least significant word " << Val << "\n"; + << "\t" << CommentChar << " double least significant word " + << Val << "\n"; } else { O << Data32bitsDirective << unsigned(U.UVal) - << "\t; double least significant word " << Val << "\n"; + << "\t" << CommentChar << " double least significant word " << Val + << "\n"; O << Data32bitsDirective << unsigned(U.UVal >> 32) - << "\t; double most significant word " << Val << "\n"; + << "\t" << CommentChar << " double most significant word " << Val + << "\n"; } return; } else { @@ -221,7 +225,8 @@ } U; U.FVal = Val; - O << Data32bitsDirective << U.UVal << "\t; float " << Val << "\n"; + O << Data32bitsDirective << U.UVal << "\t" << CommentChar + << " float " << Val << "\n"; return; } } else if (CV->getType() == Type::ULongTy || CV->getType() == Type::LongTy) { @@ -232,14 +237,18 @@ O << Data64bitsDirective << Val << "\n"; else if (TD.isBigEndian()) { O << Data32bitsDirective << unsigned(Val >> 32) - << "\t; Double-word most significant word " << Val << "\n"; + << "\t" << CommentChar << " Double-word most significant word " + << Val << "\n"; O << Data32bitsDirective << unsigned(Val) - << "\t; Double-word least significant word " << Val << "\n"; + << "\t" << CommentChar << " Double-word least significant word " + << Val << "\n"; } else { O << Data32bitsDirective << unsigned(Val) - << "\t; Double-word least significant word " << Val << "\n"; + << "\t" << CommentChar << " Double-word least significant word " + << Val << "\n"; O << Data32bitsDirective << unsigned(Val >> 32) - << "\t; Double-word most significant word " << Val << "\n"; + << "\t" << CommentChar << " Double-word most significant word " + << Val << "\n"; } return; } From lattner at cs.uiuc.edu Tue Aug 17 11:27:37 2004 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Tue, 17 Aug 2004 11:27:37 -0500 Subject: [llvm-commits] CVS: llvm/lib/Target/PowerPC/PPC32AsmPrinter.cpp Message-ID: <200408171627.LAA16086@apoc.cs.uiuc.edu> Changes in directory llvm/lib/Target/PowerPC: PPC32AsmPrinter.cpp updated: 1.49 -> 1.50 --- Log message: Print comments with ; --- Diffs of the changes: (+1 -0) Index: llvm/lib/Target/PowerPC/PPC32AsmPrinter.cpp diff -u llvm/lib/Target/PowerPC/PPC32AsmPrinter.cpp:1.49 llvm/lib/Target/PowerPC/PPC32AsmPrinter.cpp:1.50 --- llvm/lib/Target/PowerPC/PPC32AsmPrinter.cpp:1.49 Tue Aug 17 01:37:12 2004 +++ llvm/lib/Target/PowerPC/PPC32AsmPrinter.cpp Tue Aug 17 11:27:26 2004 @@ -45,6 +45,7 @@ PPC32AsmPrinter(std::ostream &O, TargetMachine &TM) : AsmPrinter(O, TM), LabelNumber(0) { + CommentChar = ";"; GlobalPrefix = "_"; ZeroDirective = "\t.space\t"; // ".space N" emits N zeros. Data64bitsDirective = 0; // we can't emit a 64-bit unit From brukman at cs.uiuc.edu Tue Aug 17 11:59:39 2004 From: brukman at cs.uiuc.edu (Misha Brukman) Date: Tue, 17 Aug 2004 11:59:39 -0500 Subject: [llvm-commits] CVS: llvm-www/ProjectsWithLLVM/index.html Message-ID: <200408171659.LAA10804@zion.cs.uiuc.edu> Changes in directory llvm-www/ProjectsWithLLVM: index.html updated: 1.15 -> 1.16 --- Log message: * Add table of contents * Wrap long lines * Standardize section/subsection headers --- Diffs of the changes: (+50 -21) Index: llvm-www/ProjectsWithLLVM/index.html diff -u llvm-www/ProjectsWithLLVM/index.html:1.15 llvm-www/ProjectsWithLLVM/index.html:1.16 --- llvm-www/ProjectsWithLLVM/index.html:1.15 Sat Jul 17 18:16:54 2004 +++ llvm-www/ProjectsWithLLVM/index.html Tue Aug 17 11:59:28 2004 @@ -4,9 +4,9 @@

    This page is an incomplete list of the projects built with LLVM, sorted in -reverse chronological order. The idea of this list is to show some of the things -that have been done with LLVM for various course projects or for other purposes, -which can be used as a source of ideas for future projects.

    +reverse chronological order. The idea of this list is to show some of the +things that have been done with LLVM for various course projects or for other +purposes, which can be used as a source of ideas for future projects.

    Note that this page is not intended to reflect that current state of LLVM or show endorsement of any particular project over another. This is just a @@ -26,6 +26,30 @@

    + + + + + + @@ -49,11 +73,10 @@ - - +
    @@ -79,26 +102,26 @@ analyses and transformations. In addition, LLVM-TV has been designed to make it easy to add new kinds of program visualization modules. LLVM-TV is based on the wxWidgets -cross-platform GUI framework, and uses AT&T Research's +cross-platform GUI framework, and uses AT&T Research's GraphViz to draw graphs.

    Wiki -page with overview; design doc, user manual & download on the +page with overview; design doc, user manual & download on the LLVM-TV website

    + @@ -117,9 +140,12 @@
    -
    XPS - eXtensible Programming System
    + +
    By: eXtensible Systems, Inc.
    @@ -164,9 +190,11 @@
    - - + +
    @@ -210,10 +238,11 @@
    -SPEDI: Static Patch Extraction and Dynamic Insertion + SPEDI: Static Patch Extraction and Dynamic Insertion
    +
    By: Brian Fahs
    @@ -239,10 +268,10 @@
    - + - @@ -268,11 +297,11 @@
    -Jello: a retargetable Just-In-Time compiler - for LLVM bytecode
    - - + Jello: a retargetable Just-In-Time compiler for + LLVM bytecode + +
    From lattner at cs.uiuc.edu Tue Aug 17 12:26:53 2004 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Tue, 17 Aug 2004 12:26:53 -0500 Subject: [llvm-commits] CVS: llvm/lib/AsmParser/llvmAsmParser.y Message-ID: <200408171726.MAA23608@apoc.cs.uiuc.edu> Changes in directory llvm/lib/AsmParser: llvmAsmParser.y updated: 1.196 -> 1.197 --- Log message: Work around PR424: http://llvm.cs.uiuc.edu/PR424 for old c/c++ frontends. --- Diffs of the changes: (+29 -3) Index: llvm/lib/AsmParser/llvmAsmParser.y diff -u llvm/lib/AsmParser/llvmAsmParser.y:1.196 llvm/lib/AsmParser/llvmAsmParser.y:1.197 --- llvm/lib/AsmParser/llvmAsmParser.y:1.196 Thu Jul 29 07:17:34 2004 +++ llvm/lib/AsmParser/llvmAsmParser.y Tue Aug 17 12:26:41 2004 @@ -916,7 +916,6 @@ %token RET BR SWITCH INVOKE UNWIND // Binary Operators -%type BinaryOps // all the binary operators %type ArithmeticOps LogicalOps SetCondOps // Binops Subcatagories %token ADD SUB MUL DIV REM AND OR XOR %token SETLE SETGE SETLT SETGT SETEQ SETNE // Binary Comarators @@ -955,7 +954,6 @@ ArithmeticOps: ADD | SUB | MUL | DIV | REM; LogicalOps : AND | OR | XOR; SetCondOps : SETLE | SETGE | SETLT | SETGT | SETEQ | SETNE; -BinaryOps : ArithmeticOps | LogicalOps | SetCondOps; ShiftOps : SHL | SHR; @@ -1326,9 +1324,37 @@ ThrowException("Select operand types must match!"); $$ = ConstantExpr::getSelect($3, $5, $7); } - | BinaryOps '(' ConstVal ',' ConstVal ')' { + | ArithmeticOps '(' ConstVal ',' ConstVal ')' { if ($3->getType() != $5->getType()) ThrowException("Binary operator types must match!"); + // HACK: llvm 1.3 and earlier used to emit invalid pointer constant exprs. + // To retain backward compatibility with these early compilers, we emit a + // cast to the appropriate integer type automatically if we are in the + // broken case. See PR424 for more information. + if (!isa($3->getType())) { + $$ = ConstantExpr::get($1, $3, $5); + } else { + const Type *IntPtrTy; + switch (CurModule.CurrentModule->getPointerSize()) { + case Module::Pointer32: IntPtrTy = Type::IntTy; break; + case Module::Pointer64: IntPtrTy = Type::LongTy; break; + default: ThrowException("invalid pointer binary constant expr!"); + } + $$ = ConstantExpr::get($1, ConstantExpr::getCast($3, IntPtrTy), + ConstantExpr::getCast($5, IntPtrTy)); + $$ = ConstantExpr::getCast($$, $3->getType()); + } + } + | LogicalOps '(' ConstVal ',' ConstVal ')' { + if ($3->getType() != $5->getType()) + ThrowException("Logical operator types must match!"); + if (!$3->getType()->isIntegral()) + ThrowException("Logical operands must have integral types!"); + $$ = ConstantExpr::get($1, $3, $5); + } + | SetCondOps '(' ConstVal ',' ConstVal ')' { + if ($3->getType() != $5->getType()) + ThrowException("setcc operand types must match!"); $$ = ConstantExpr::get($1, $3, $5); } | ShiftOps '(' ConstVal ',' ConstVal ')' { From lattner at cs.uiuc.edu Tue Aug 17 12:28:58 2004 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Tue, 17 Aug 2004 12:28:58 -0500 Subject: [llvm-commits] CVS: llvm/lib/VMCore/Constants.cpp Message-ID: <200408171728.MAA24591@apoc.cs.uiuc.edu> Changes in directory llvm/lib/VMCore: Constants.cpp updated: 1.101 -> 1.102 --- Log message: Check constant expression validity more strictly --- Diffs of the changes: (+31 -0) Index: llvm/lib/VMCore/Constants.cpp diff -u llvm/lib/VMCore/Constants.cpp:1.101 llvm/lib/VMCore/Constants.cpp:1.102 --- llvm/lib/VMCore/Constants.cpp:1.101 Wed Aug 4 17:26:13 2004 +++ llvm/lib/VMCore/Constants.cpp Tue Aug 17 12:28:46 2004 @@ -1127,6 +1127,37 @@ } Constant *ConstantExpr::get(unsigned Opcode, Constant *C1, Constant *C2) { +#ifndef NDEBUG + switch (Opcode) { + case Instruction::Add: case Instruction::Sub: + case Instruction::Mul: case Instruction::Div: + case Instruction::Rem: + assert(C1->getType() == C2->getType() && "Op types should be identical!"); + assert((C1->getType()->isInteger() || C1->getType()->isFloatingPoint()) && + "Tried to create an arithmetic operation on a non-arithmetic type!"); + break; + case Instruction::And: + case Instruction::Or: + case Instruction::Xor: + assert(C1->getType() == C2->getType() && "Op types should be identical!"); + assert(C1->getType()->isIntegral() && + "Tried to create an logical operation on a non-integral type!"); + break; + case Instruction::SetLT: case Instruction::SetGT: case Instruction::SetLE: + case Instruction::SetGE: case Instruction::SetEQ: case Instruction::SetNE: + assert(C1->getType() == C2->getType() && "Op types should be identical!"); + break; + case Instruction::Shl: + case Instruction::Shr: + assert(C2->getType() == Type::UByteTy && "Shift should be by ubyte!"); + assert(C1->getType()->isInteger() && + "Tried to create a shift operation on a non-integer type!"); + break; + default: + break; + } +#endif + if (Instruction::isRelational(Opcode)) return getTy(Type::BoolTy, Opcode, C1, C2); else From brukman at cs.uiuc.edu Tue Aug 17 12:52:46 2004 From: brukman at cs.uiuc.edu (Misha Brukman) Date: Tue, 17 Aug 2004 12:52:46 -0500 Subject: [llvm-commits] CVS: llvm/include/llvm/CodeGen/MachineFunction.h Message-ID: <200408171752.MAA03254@zion.cs.uiuc.edu> Changes in directory llvm/include/llvm/CodeGen: MachineFunction.h updated: 1.39 -> 1.40 --- Log message: Ultra-doxygenify some function header comments. --- Diffs of the changes: (+3 -0) Index: llvm/include/llvm/CodeGen/MachineFunction.h diff -u llvm/include/llvm/CodeGen/MachineFunction.h:1.39 llvm/include/llvm/CodeGen/MachineFunction.h:1.40 --- llvm/include/llvm/CodeGen/MachineFunction.h:1.39 Mon Aug 16 17:35:26 2004 +++ llvm/include/llvm/CodeGen/MachineFunction.h Tue Aug 17 12:52:36 2004 @@ -48,6 +48,7 @@ static void setNext(MachineBasicBlock* N, MachineBasicBlock* next) { N->Next = next; } + static MachineBasicBlock* createNode(); void addNodeToList(MachineBasicBlock* N); void removeNodeFromList(MachineBasicBlock* N); @@ -117,6 +118,7 @@ /// getConstantPool - Return the constant pool object for the current /// function. + /// MachineConstantPool *getConstantPool() const { return ConstantPool; } /// MachineFunctionInfo - Keep track of various per-function pieces of @@ -128,6 +130,7 @@ /// are inserted into the machine function. The block number for a machine /// basic block can be found by using the MBB::getBlockNumber method, this /// method provides the inverse mapping. + /// MachineBasicBlock *getBlockNumbered(unsigned N) { assert(N < MBBNumbering.size() && "Illegal block number"); assert(MBBNumbering[N] && "Block was removed from the machine function!"); From brukman at cs.uiuc.edu Tue Aug 17 13:09:02 2004 From: brukman at cs.uiuc.edu (Misha Brukman) Date: Tue, 17 Aug 2004 13:09:02 -0500 Subject: [llvm-commits] CVS: llvm/include/Support/StringExtras.h Message-ID: <200408171809.NAA08741@zion.cs.uiuc.edu> Changes in directory llvm/include/Support: StringExtras.h updated: 1.20 -> 1.21 --- Log message: Add itostr(long) for our furry 64-bit friends. --- Diffs of the changes: (+7 -0) Index: llvm/include/Support/StringExtras.h diff -u llvm/include/Support/StringExtras.h:1.20 llvm/include/Support/StringExtras.h:1.21 --- llvm/include/Support/StringExtras.h:1.20 Tue Jul 20 11:14:06 2004 +++ llvm/include/Support/StringExtras.h Tue Aug 17 13:08:52 2004 @@ -84,6 +84,13 @@ return std::string(BufPtr); } +static inline std::string itostr(long X) { + if (X < 0) + return utostr(static_cast(-X), true); + else + return utostr(static_cast(X)); +} + static inline std::string itostr(int X) { if (X < 0) return utostr(static_cast(-X), true); From lattner at cs.uiuc.edu Tue Aug 17 14:12:57 2004 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Tue, 17 Aug 2004 14:12:57 -0500 Subject: [llvm-commits] CVS: llvm/include/llvm/Target/TargetData.h Message-ID: <200408171912.OAA10577@apoc.cs.uiuc.edu> Changes in directory llvm/include/llvm/Target: TargetData.h updated: 1.25 -> 1.26 --- Log message: Add punctuation, add a new method --- Diffs of the changes: (+6 -2) Index: llvm/include/llvm/Target/TargetData.h diff -u llvm/include/llvm/Target/TargetData.h:1.25 llvm/include/llvm/Target/TargetData.h:1.26 --- llvm/include/llvm/Target/TargetData.h:1.25 Thu Jul 22 20:08:13 2004 +++ llvm/include/llvm/Target/TargetData.h Tue Aug 17 14:12:44 2004 @@ -87,13 +87,17 @@ unsigned char getPointerSize() const { return PointerSize; } /// getTypeSize - Return the number of bytes necessary to hold the specified - /// type + /// type. uint64_t getTypeSize(const Type *Ty) const; /// getTypeAlignment - Return the minimum required alignment for the specified - /// type + /// type. unsigned char getTypeAlignment(const Type *Ty) const; + /// getTypeAlignmentShift - Return the minimum required alignment for the + /// specified type, returned as log2 of the value (a shift amount). + unsigned char getTypeAlignmentShift(const Type *Ty) const; + /// getIntPtrType - Return an unsigned integer type that is the same size or /// greater to the host pointer size. const Type *getIntPtrType() const; From lattner at cs.uiuc.edu Tue Aug 17 14:13:11 2004 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Tue, 17 Aug 2004 14:13:11 -0500 Subject: [llvm-commits] CVS: llvm/lib/Target/TargetData.cpp Message-ID: <200408171913.OAA10585@apoc.cs.uiuc.edu> Changes in directory llvm/lib/Target: TargetData.cpp updated: 1.50 -> 1.51 --- Log message: Add a new helper method to get log2(type alignment) --- Diffs of the changes: (+7 -0) Index: llvm/lib/Target/TargetData.cpp diff -u llvm/lib/Target/TargetData.cpp:1.50 llvm/lib/Target/TargetData.cpp:1.51 --- llvm/lib/Target/TargetData.cpp:1.50 Thu Jul 22 20:09:52 2004 +++ llvm/lib/Target/TargetData.cpp Tue Aug 17 14:13:00 2004 @@ -21,6 +21,7 @@ #include "llvm/DerivedTypes.h" #include "llvm/Constants.h" #include "llvm/Support/GetElementPtrTypeIterator.h" +#include "Support/MathExtras.h" using namespace llvm; // Handle the Pass registration stuff necessary to use TargetData's. @@ -201,6 +202,12 @@ return Align; } +unsigned char TargetData::getTypeAlignmentShift(const Type *Ty) const { + unsigned Align = getTypeAlignment(Ty); + assert(!(Align & (Align-1)) && "Alignment is not a power of two!"); + return log2(Align); +} + /// getIntPtrType - Return an unsigned integer type that is the same size or /// greater to the host pointer size. const Type *TargetData::getIntPtrType() const { From lattner at cs.uiuc.edu Tue Aug 17 14:14:28 2004 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Tue, 17 Aug 2004 14:14:28 -0500 Subject: [llvm-commits] CVS: llvm/include/llvm/CodeGen/AsmPrinter.h Message-ID: <200408171914.OAA10605@apoc.cs.uiuc.edu> Changes in directory llvm/include/llvm/CodeGen: AsmPrinter.h updated: 1.6 -> 1.7 --- Log message: Add support for alignment --- Diffs of the changes: (+21 -2) Index: llvm/include/llvm/CodeGen/AsmPrinter.h diff -u llvm/include/llvm/CodeGen/AsmPrinter.h:1.6 llvm/include/llvm/CodeGen/AsmPrinter.h:1.7 --- llvm/include/llvm/CodeGen/AsmPrinter.h:1.6 Tue Aug 17 11:26:36 2004 +++ llvm/include/llvm/CodeGen/AsmPrinter.h Tue Aug 17 14:14:17 2004 @@ -47,7 +47,7 @@ /// CommentChar - This indicates the comment character used by the /// assembler. - const char *CommentChar; + const char *CommentChar; // Defaults to "#" /// GlobalPrefix - If this is set to a non-empty string, it is prepended /// onto all global symbols. This is often used for "_" or ".". @@ -71,6 +71,17 @@ const char *Data32bitsDirective; // Defaults to "\t.long\t" const char *Data64bitsDirective; // Defaults to "\t.quad\t" + /// AlignDirective - The directive used to emit round up to an alignment + /// boundary. + /// + const char *AlignDirective; // Defaults to "\t.align\t" + + /// AlignmentIsInBytes - If this is true (the default) then the asmprinter + /// emits ".align N" directives, where N is the number of bytes to align to. + /// Otherwise, it emits ".align log2(N)", e.g. 3 to align to an 8 byte + /// boundary. + bool AlignmentIsInBytes; // Defaults to true + AsmPrinter(std::ostream &o, TargetMachine &tm) : O(o), TM(tm), CommentChar("#"), @@ -80,7 +91,10 @@ Data8bitsDirective("\t.byte\t"), Data16bitsDirective("\t.short\t"), Data32bitsDirective("\t.long\t"), - Data64bitsDirective("\t.quad\t") { } + Data64bitsDirective("\t.quad\t"), + AlignDirective("\t.align\t"), + AlignmentIsInBytes(true) { + } /// doInitialization - Set up the AsmPrinter when we are working on a new /// module. If your pass overrides this, it must make sure to explicitly @@ -95,6 +109,11 @@ /// is being processed from runOnMachineFunction. void setupMachineFunction(MachineFunction &MF); + /// emitAlignment - Emit an alignment directive to the specified power of + /// two boundary. For example, if you pass in 3 here, you will get an 8 + /// byte alignment. + void emitAlignment(unsigned NumBits) const; + /// emitConstantValueOnly - Print out the specified constant, without a /// storage class. Only constants of first-class type are allowed here. void emitConstantValueOnly(const Constant *CV); From lattner at cs.uiuc.edu Tue Aug 17 14:14:40 2004 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Tue, 17 Aug 2004 14:14:40 -0500 Subject: [llvm-commits] CVS: llvm/lib/CodeGen/AsmPrinter.cpp Message-ID: <200408171914.OAA10614@apoc.cs.uiuc.edu> Changes in directory llvm/lib/CodeGen: AsmPrinter.cpp updated: 1.6 -> 1.7 --- Log message: Add support for alignment --- Diffs of the changes: (+6 -0) Index: llvm/lib/CodeGen/AsmPrinter.cpp diff -u llvm/lib/CodeGen/AsmPrinter.cpp:1.6 llvm/lib/CodeGen/AsmPrinter.cpp:1.7 --- llvm/lib/CodeGen/AsmPrinter.cpp:1.6 Tue Aug 17 11:27:05 2004 +++ llvm/lib/CodeGen/AsmPrinter.cpp Tue Aug 17 14:14:29 2004 @@ -33,6 +33,12 @@ CurrentFnName = Mang->getValueName((Value*)MF.getFunction()); } +// emitAlignment - Emit an alignment directive to the specified power of two. +void AsmPrinter::emitAlignment(unsigned NumBits) const { + if (AlignmentIsInBytes) NumBits = 1 << NumBits; + O << AlignDirective << NumBits << "\n"; +} + // Print out the specified constant, without a storage class. Only the // constants valid in constant expressions can occur here. void AsmPrinter::emitConstantValueOnly(const Constant *CV) { From lattner at cs.uiuc.edu Tue Aug 17 14:17:23 2004 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Tue, 17 Aug 2004 14:17:23 -0500 Subject: [llvm-commits] CVS: llvm/include/Support/MathExtras.h Message-ID: <200408171917.OAA10646@apoc.cs.uiuc.edu> Changes in directory llvm/include/Support: MathExtras.h updated: 1.13 -> 1.14 --- Log message: Add an overload --- Diffs of the changes: (+7 -0) Index: llvm/include/Support/MathExtras.h diff -u llvm/include/Support/MathExtras.h:1.13 llvm/include/Support/MathExtras.h:1.14 --- llvm/include/Support/MathExtras.h:1.13 Tue Jul 20 22:15:14 2004 +++ llvm/include/Support/MathExtras.h Tue Aug 17 14:17:10 2004 @@ -29,6 +29,13 @@ return getPow; } +inline unsigned log2(unsigned C) { + unsigned getPow; + for (getPow = 0; C > 1; ++getPow) + C >>= 1; + return getPow; +} + inline bool isPowerOf2(int64_t C, unsigned &getPow) { if (C < 0) C = -C; if (C > 0 && C == (C & ~(C - 1))) { From lattner at cs.uiuc.edu Tue Aug 17 14:25:55 2004 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Tue, 17 Aug 2004 14:25:55 -0500 Subject: [llvm-commits] CVS: llvm/lib/Target/X86/X86AsmPrinter.cpp Message-ID: <200408171925.OAA11372@apoc.cs.uiuc.edu> Changes in directory llvm/lib/Target/X86: X86AsmPrinter.cpp updated: 1.118 -> 1.119 --- Log message: Start using alignment output routines from AsmPrinter. Changes to make this more similar to the ppc asmprinter --- Diffs of the changes: (+8 -10) Index: llvm/lib/Target/X86/X86AsmPrinter.cpp diff -u llvm/lib/Target/X86/X86AsmPrinter.cpp:1.118 llvm/lib/Target/X86/X86AsmPrinter.cpp:1.119 --- llvm/lib/Target/X86/X86AsmPrinter.cpp:1.118 Tue Aug 17 01:48:55 2004 +++ llvm/lib/Target/X86/X86AsmPrinter.cpp Tue Aug 17 14:25:42 2004 @@ -149,9 +149,8 @@ for (unsigned i = 0, e = CP.size(); i != e; ++i) { O << "\t.section .rodata\n"; - O << "\t.align " << (unsigned)TD.getTypeAlignment(CP[i]->getType()) - << "\n"; - O << ".CPI" << CurrentFnName << "_" << i << ":\t\t\t\t\t#" + emitAlignment(TD.getTypeAlignmentShift(CP[i]->getType())); + O << ".CPI" << CurrentFnName << "_" << i << ":\t\t\t\t\t" << CommentChar << *CP[i] << "\n"; emitGlobalConstant(CP[i]); } @@ -169,7 +168,7 @@ // Print out labels for the function. O << "\t.text\n"; - O << "\t.align 16\n"; + emitAlignment(4); O << "\t.globl\t" << CurrentFnName << "\n"; O << "\t.type\t" << CurrentFnName << ", @function\n"; O << CurrentFnName << ":\n"; @@ -178,8 +177,8 @@ for (MachineFunction::const_iterator I = MF.begin(), E = MF.end(); I != E; ++I) { // Print a label for the basic block. - O << ".LBB" << CurrentFnName << "_" << I->getNumber() << ":\t# " - << I->getBasicBlock()->getName() << "\n"; + O << ".LBB" << CurrentFnName << "_" << I->getNumber() << ":\t" + << CommentChar << " " << I->getBasicBlock()->getName() << "\n"; for (MachineBasicBlock::const_iterator II = I->begin(), E = I->end(); II != E; ++II) { // Print the assembly for the instruction. @@ -387,7 +386,7 @@ std::string name = Mang->getValueName(I); Constant *C = I->getInitializer(); unsigned Size = TD.getTypeSize(C->getType()); - unsigned Align = TD.getTypeAlignment(C->getType()); + unsigned Align = TD.getTypeAlignmentShift(C->getType()); if (C->isNullValue() && (I->hasLinkOnceLinkage() || I->hasInternalLinkage() || @@ -397,7 +396,7 @@ O << "\t.local " << name << "\n"; O << "\t.comm " << name << "," << TD.getTypeSize(C->getType()) - << "," << (unsigned)TD.getTypeAlignment(C->getType()); + << "," << (1 << Align); O << "\t\t# "; WriteAsOperand(O, I, true, true, &M); O << "\n"; @@ -410,7 +409,6 @@ SwitchSection(O, CurSection, ""); O << "\t.section\t.llvm.linkonce.d." << name << ",\"aw\", at progbits\n"; break; - case GlobalValue::AppendingLinkage: // FIXME: appending linkage variables should go into a section of // their name or something. For now, just emit them as external. @@ -426,7 +424,7 @@ break; } - O << "\t.align " << Align << "\n"; + emitAlignment(Align); O << "\t.type " << name << ", at object\n"; O << "\t.size " << name << "," << Size << "\n"; O << name << ":\t\t\t\t# "; From lattner at cs.uiuc.edu Tue Aug 17 14:26:14 2004 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Tue, 17 Aug 2004 14:26:14 -0500 Subject: [llvm-commits] CVS: llvm/lib/Target/PowerPC/PPC32AsmPrinter.cpp Message-ID: <200408171926.OAA11385@apoc.cs.uiuc.edu> Changes in directory llvm/lib/Target/PowerPC: PPC32AsmPrinter.cpp updated: 1.50 -> 1.51 --- Log message: Start using alignment output routines from AsmPrinter. Changes to make this more similar to the X86 asmprinter Fix overalignment of globals. --- Diffs of the changes: (+12 -12) Index: llvm/lib/Target/PowerPC/PPC32AsmPrinter.cpp diff -u llvm/lib/Target/PowerPC/PPC32AsmPrinter.cpp:1.50 llvm/lib/Target/PowerPC/PPC32AsmPrinter.cpp:1.51 --- llvm/lib/Target/PowerPC/PPC32AsmPrinter.cpp:1.50 Tue Aug 17 11:27:26 2004 +++ llvm/lib/Target/PowerPC/PPC32AsmPrinter.cpp Tue Aug 17 14:26:03 2004 @@ -49,6 +49,7 @@ GlobalPrefix = "_"; ZeroDirective = "\t.space\t"; // ".space N" emits N zeros. Data64bitsDirective = 0; // we can't emit a 64-bit unit + AlignmentIsInBytes = false; // Alignment is by power of 2. } /// Unique incrementer for label values for referencing Global values. @@ -121,9 +122,8 @@ for (unsigned i = 0, e = CP.size(); i != e; ++i) { O << "\t.const\n"; - O << "\t.align " << (unsigned)TD.getTypeAlignment(CP[i]->getType()) - << "\n"; - O << ".CPI" << CurrentFnName << "_" << i << ":\t\t\t\t\t;" + emitAlignment(TD.getTypeAlignmentShift(CP[i]->getType())); + O << ".CPI" << CurrentFnName << "_" << i << ":\t\t\t\t\t" << CommentChar << *CP[i] << "\n"; emitGlobalConstant(CP[i]); } @@ -140,19 +140,19 @@ printConstantPool(MF.getConstantPool()); // Print out labels for the function. - O << "\t.text\n"; + O << "\t.text\n"; + emitAlignment(2); O << "\t.globl\t" << CurrentFnName << "\n"; - O << "\t.align 2\n"; O << CurrentFnName << ":\n"; // Print out code for the function. for (MachineFunction::const_iterator I = MF.begin(), E = MF.end(); I != E; ++I) { // Print a label for the basic block. - O << ".LBB" << CurrentFnName << "_" << I->getNumber() << ":\t; " - << I->getBasicBlock()->getName() << "\n"; + O << ".LBB" << CurrentFnName << "_" << I->getNumber() << ":\t" + << CommentChar << " " << I->getBasicBlock()->getName() << "\n"; for (MachineBasicBlock::const_iterator II = I->begin(), E = I->end(); - II != E; ++II) { + II != E; ++II) { // Print the assembly for the instruction. O << "\t"; printMachineInstruction(II); @@ -399,14 +399,14 @@ std::string name = Mang->getValueName(I); Constant *C = I->getInitializer(); unsigned Size = TD.getTypeSize(C->getType()); - unsigned Align = TD.getTypeAlignment(C->getType()); + unsigned Align = TD.getTypeAlignmentShift(C->getType()); if (C->isNullValue() && /* FIXME: Verify correct */ (I->hasInternalLinkage() || I->hasWeakLinkage())) { SwitchSection(O, CurSection, ".data"); if (I->hasInternalLinkage()) O << ".lcomm " << name << "," << TD.getTypeSize(C->getType()) - << "," << (unsigned)TD.getTypeAlignment(C->getType()); + << "," << Align; else O << ".comm " << name << "," << TD.getTypeSize(C->getType()); O << "\t\t; "; @@ -439,7 +439,7 @@ break; } - O << "\t.align " << Align << "\n"; + emitAlignment(Align); O << name << ":\t\t\t\t; "; WriteAsOperand(O, I, true, true, &M); O << " = "; @@ -455,7 +455,7 @@ { O << ".data\n"; O << ".section __TEXT,__picsymbolstub1,symbol_stubs,pure_instructions,32\n"; - O << "\t.align 2\n"; + emitAlignment(2); O << "L" << *i << "$stub:\n"; O << "\t.indirect_symbol " << *i << "\n"; O << "\tmflr r0\n"; From criswell at cs.uiuc.edu Tue Aug 17 14:36:33 2004 From: criswell at cs.uiuc.edu (John Criswell) Date: Tue, 17 Aug 2004 14:36:33 -0500 Subject: [llvm-commits] CVS: llvm/test/Programs/Makefile.programs Message-ID: <200408171936.OAA01561@choi.cs.uiuc.edu> Changes in directory llvm/test/Programs: Makefile.programs updated: 1.133 -> 1.134 --- Log message: Add rule to update Makefiles. This should get all of the Makefiles, but won't properly update the Makefile Makefiles, like Makefile.multisrc. --- Diffs of the changes: (+8 -0) Index: llvm/test/Programs/Makefile.programs diff -u llvm/test/Programs/Makefile.programs:1.133 llvm/test/Programs/Makefile.programs:1.134 --- llvm/test/Programs/Makefile.programs:1.133 Sat Jul 24 02:54:16 2004 +++ llvm/test/Programs/Makefile.programs Tue Aug 17 14:36:21 2004 @@ -604,3 +604,11 @@ clean:: rm -f report.*.raw.out report.*.txt report.*.html report.*.tex + +# If the Makefile in the source tree has been updated, copy it over into the +# build tree. +Makefile :: $(BUILD_SRC_DIR)/Makefile + @${ECHO} "===== Updating Makefile from source dir: `dirname $<` =====" + $(MKDIR) $(@D) + cp -f $< $@ + From brukman at cs.uiuc.edu Tue Aug 17 15:23:44 2004 From: brukman at cs.uiuc.edu (Misha Brukman) Date: Tue, 17 Aug 2004 15:23:44 -0500 Subject: [llvm-commits] CVS: llvm/lib/Target/PowerPC/PowerPC.td Message-ID: <200408172023.PAA12994@zion.cs.uiuc.edu> Changes in directory llvm/lib/Target/PowerPC: PowerPC.td (r1.7) removed --- Log message: This file is no longer used. --- Diffs of the changes: (+0 -0) From lattner at cs.uiuc.edu Tue Aug 17 16:38:52 2004 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Tue, 17 Aug 2004 16:38:52 -0500 Subject: [llvm-commits] CVS: llvm/lib/CodeGen/AsmPrinter.cpp Message-ID: <200408172138.QAA01779@apoc.cs.uiuc.edu> Changes in directory llvm/lib/CodeGen: AsmPrinter.cpp updated: 1.7 -> 1.8 --- Log message: Add support for targets without a .zero directive --- Diffs of the changes: (+23 -4) Index: llvm/lib/CodeGen/AsmPrinter.cpp diff -u llvm/lib/CodeGen/AsmPrinter.cpp:1.7 llvm/lib/CodeGen/AsmPrinter.cpp:1.8 --- llvm/lib/CodeGen/AsmPrinter.cpp:1.7 Tue Aug 17 14:14:29 2004 +++ llvm/lib/CodeGen/AsmPrinter.cpp Tue Aug 17 16:38:40 2004 @@ -39,6 +39,25 @@ O << AlignDirective << NumBits << "\n"; } +/// emitZeros - Emit a block of zeros. +/// +void AsmPrinter::emitZeros(unsigned NumZeros) const { + if (NumZeros) { + if (ZeroDirective) + O << ZeroDirective << NumZeros << "\n"; + else { + if (NumZeros >= 8 && Data64bitsDirective) { + for (; NumZeros >= 8; NumZeros -= 8) + O << Data64bitsDirective << "0\n"; + } + for (; NumZeros >= 4; NumZeros -= 4) + O << Data32bitsDirective << "0\n"; + for (; NumZeros; --NumZeros) + O << Data8bitsDirective << "0\n"; + } + } +} + // Print out the specified constant, without a storage class. Only the // constants valid in constant expressions can occur here. void AsmPrinter::emitConstantValueOnly(const Constant *CV) { @@ -159,7 +178,7 @@ const TargetData &TD = TM.getTargetData(); if (CV->isNullValue()) { - O << ZeroDirective << TD.getTypeSize(CV->getType()) << "\n"; + emitZeros(TD.getTypeSize(CV->getType())); return; } else if (const ConstantArray *CVA = dyn_cast(CV)) { if (CVA->isString()) { @@ -189,8 +208,7 @@ emitGlobalConstant(field); // Insert the field padding unless it's zero bytes... - if (padSize) - O << ZeroDirective << padSize << "\n"; + emitZeros(padSize); } assert(sizeSoFar == cvsLayout->StructSize && "Layout of constant struct may be incorrect!"); @@ -207,7 +225,8 @@ U.FVal = Val; if (Data64bitsDirective) - O << Data64bitsDirective << U.UVal << "\n"; + O << Data64bitsDirective << U.UVal << "\t" << CommentChar + << " double value: " << Val << "\n"; else if (TD.isBigEndian()) { O << Data32bitsDirective << unsigned(U.UVal >> 32) << "\t" << CommentChar << " double most significant word " From lattner at cs.uiuc.edu Tue Aug 17 16:39:02 2004 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Tue, 17 Aug 2004 16:39:02 -0500 Subject: [llvm-commits] CVS: llvm/include/llvm/CodeGen/AsmPrinter.h Message-ID: <200408172139.QAA01789@apoc.cs.uiuc.edu> Changes in directory llvm/include/llvm/CodeGen: AsmPrinter.h updated: 1.7 -> 1.8 --- Log message: new method --- Diffs of the changes: (+4 -0) Index: llvm/include/llvm/CodeGen/AsmPrinter.h diff -u llvm/include/llvm/CodeGen/AsmPrinter.h:1.7 llvm/include/llvm/CodeGen/AsmPrinter.h:1.8 --- llvm/include/llvm/CodeGen/AsmPrinter.h:1.7 Tue Aug 17 14:14:17 2004 +++ llvm/include/llvm/CodeGen/AsmPrinter.h Tue Aug 17 16:38:51 2004 @@ -114,6 +114,10 @@ /// byte alignment. void emitAlignment(unsigned NumBits) const; + /// emitZeros - Emit a block of zeros. + /// + void emitZeros(unsigned NumZeros) const; + /// emitConstantValueOnly - Print out the specified constant, without a /// storage class. Only constants of first-class type are allowed here. void emitConstantValueOnly(const Constant *CV); From llvm at cs.uiuc.edu Tue Aug 17 17:26:28 2004 From: llvm at cs.uiuc.edu (LLVM) Date: Tue, 17 Aug 2004 17:26:28 -0500 Subject: [llvm-commits] CVS: llvm/projects/Small/ Message-ID: <200408172226.RAA14696@zion.cs.uiuc.edu> Changes in directory llvm/projects/Small: --- Log message: Directory /var/cvs/llvm/llvm/projects/Small added to the repository --- Diffs of the changes: (+0 -0) From lattner at cs.uiuc.edu Tue Aug 17 21:22:46 2004 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Tue, 17 Aug 2004 21:22:46 -0500 Subject: [llvm-commits] CVS: llvm/include/llvm/CodeGen/AsmPrinter.h Message-ID: <200408180222.VAA04946@apoc.cs.uiuc.edu> Changes in directory llvm/include/llvm/CodeGen: AsmPrinter.h updated: 1.8 -> 1.9 --- Log message: Alkis pointed out that this is not a character (we actually support strings) and as such, we should use self revealing names. Hey, makes sense to me! --- Diffs of the changes: (+3 -3) Index: llvm/include/llvm/CodeGen/AsmPrinter.h diff -u llvm/include/llvm/CodeGen/AsmPrinter.h:1.8 llvm/include/llvm/CodeGen/AsmPrinter.h:1.9 --- llvm/include/llvm/CodeGen/AsmPrinter.h:1.8 Tue Aug 17 16:38:51 2004 +++ llvm/include/llvm/CodeGen/AsmPrinter.h Tue Aug 17 21:22:34 2004 @@ -45,9 +45,9 @@ // Properties to be set by the derived class ctor, used to configure the // asmwriter. - /// CommentChar - This indicates the comment character used by the + /// CommentString - This indicates the comment character used by the /// assembler. - const char *CommentChar; // Defaults to "#" + const char *CommentString; // Defaults to "#" /// GlobalPrefix - If this is set to a non-empty string, it is prepended /// onto all global symbols. This is often used for "_" or ".". @@ -84,7 +84,7 @@ AsmPrinter(std::ostream &o, TargetMachine &tm) : O(o), TM(tm), - CommentChar("#"), + CommentString("#"), GlobalPrefix(""), ZeroDirective("\t.zero\t"), AsciiDirective("\t.ascii\t"), From lattner at cs.uiuc.edu Tue Aug 17 21:22:54 2004 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Tue, 17 Aug 2004 21:22:54 -0500 Subject: [llvm-commits] CVS: llvm/lib/CodeGen/AsmPrinter.cpp Message-ID: <200408180222.VAA04957@apoc.cs.uiuc.edu> Changes in directory llvm/lib/CodeGen: AsmPrinter.cpp updated: 1.8 -> 1.9 --- Log message: Rename var --- Diffs of the changes: (+10 -10) Index: llvm/lib/CodeGen/AsmPrinter.cpp diff -u llvm/lib/CodeGen/AsmPrinter.cpp:1.8 llvm/lib/CodeGen/AsmPrinter.cpp:1.9 --- llvm/lib/CodeGen/AsmPrinter.cpp:1.8 Tue Aug 17 16:38:40 2004 +++ llvm/lib/CodeGen/AsmPrinter.cpp Tue Aug 17 21:22:44 2004 @@ -225,21 +225,21 @@ U.FVal = Val; if (Data64bitsDirective) - O << Data64bitsDirective << U.UVal << "\t" << CommentChar + O << Data64bitsDirective << U.UVal << "\t" << CommentString << " double value: " << Val << "\n"; else if (TD.isBigEndian()) { O << Data32bitsDirective << unsigned(U.UVal >> 32) - << "\t" << CommentChar << " double most significant word " + << "\t" << CommentString << " double most significant word " << Val << "\n"; O << Data32bitsDirective << unsigned(U.UVal) - << "\t" << CommentChar << " double least significant word " + << "\t" << CommentString << " double least significant word " << Val << "\n"; } else { O << Data32bitsDirective << unsigned(U.UVal) - << "\t" << CommentChar << " double least significant word " << Val + << "\t" << CommentString << " double least significant word " << Val << "\n"; O << Data32bitsDirective << unsigned(U.UVal >> 32) - << "\t" << CommentChar << " double most significant word " << Val + << "\t" << CommentString << " double most significant word " << Val << "\n"; } return; @@ -250,7 +250,7 @@ } U; U.FVal = Val; - O << Data32bitsDirective << U.UVal << "\t" << CommentChar + O << Data32bitsDirective << U.UVal << "\t" << CommentString << " float " << Val << "\n"; return; } @@ -262,17 +262,17 @@ O << Data64bitsDirective << Val << "\n"; else if (TD.isBigEndian()) { O << Data32bitsDirective << unsigned(Val >> 32) - << "\t" << CommentChar << " Double-word most significant word " + << "\t" << CommentString << " Double-word most significant word " << Val << "\n"; O << Data32bitsDirective << unsigned(Val) - << "\t" << CommentChar << " Double-word least significant word " + << "\t" << CommentString << " Double-word least significant word " << Val << "\n"; } else { O << Data32bitsDirective << unsigned(Val) - << "\t" << CommentChar << " Double-word least significant word " + << "\t" << CommentString << " Double-word least significant word " << Val << "\n"; O << Data32bitsDirective << unsigned(Val >> 32) - << "\t" << CommentChar << " Double-word most significant word " + << "\t" << CommentString << " Double-word most significant word " << Val << "\n"; } return; From lattner at cs.uiuc.edu Tue Aug 17 21:23:03 2004 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Tue, 17 Aug 2004 21:23:03 -0500 Subject: [llvm-commits] CVS: llvm/lib/Target/X86/X86AsmPrinter.cpp Message-ID: <200408180223.VAA04969@apoc.cs.uiuc.edu> Changes in directory llvm/lib/Target/X86: X86AsmPrinter.cpp updated: 1.119 -> 1.120 --- Log message: Rename var --- Diffs of the changes: (+2 -2) Index: llvm/lib/Target/X86/X86AsmPrinter.cpp diff -u llvm/lib/Target/X86/X86AsmPrinter.cpp:1.119 llvm/lib/Target/X86/X86AsmPrinter.cpp:1.120 --- llvm/lib/Target/X86/X86AsmPrinter.cpp:1.119 Tue Aug 17 14:25:42 2004 +++ llvm/lib/Target/X86/X86AsmPrinter.cpp Tue Aug 17 21:22:53 2004 @@ -150,7 +150,7 @@ for (unsigned i = 0, e = CP.size(); i != e; ++i) { O << "\t.section .rodata\n"; emitAlignment(TD.getTypeAlignmentShift(CP[i]->getType())); - O << ".CPI" << CurrentFnName << "_" << i << ":\t\t\t\t\t" << CommentChar + O << ".CPI" << CurrentFnName << "_" << i << ":\t\t\t\t\t" << CommentString << *CP[i] << "\n"; emitGlobalConstant(CP[i]); } @@ -178,7 +178,7 @@ I != E; ++I) { // Print a label for the basic block. O << ".LBB" << CurrentFnName << "_" << I->getNumber() << ":\t" - << CommentChar << " " << I->getBasicBlock()->getName() << "\n"; + << CommentString << " " << I->getBasicBlock()->getName() << "\n"; for (MachineBasicBlock::const_iterator II = I->begin(), E = I->end(); II != E; ++II) { // Print the assembly for the instruction. From lattner at cs.uiuc.edu Tue Aug 17 21:23:05 2004 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Tue, 17 Aug 2004 21:23:05 -0500 Subject: [llvm-commits] CVS: llvm/lib/Target/PowerPC/PPC32AsmPrinter.cpp Message-ID: <200408180223.VAA04975@apoc.cs.uiuc.edu> Changes in directory llvm/lib/Target/PowerPC: PPC32AsmPrinter.cpp updated: 1.51 -> 1.52 --- Log message: Rename var --- Diffs of the changes: (+3 -3) Index: llvm/lib/Target/PowerPC/PPC32AsmPrinter.cpp diff -u llvm/lib/Target/PowerPC/PPC32AsmPrinter.cpp:1.51 llvm/lib/Target/PowerPC/PPC32AsmPrinter.cpp:1.52 --- llvm/lib/Target/PowerPC/PPC32AsmPrinter.cpp:1.51 Tue Aug 17 14:26:03 2004 +++ llvm/lib/Target/PowerPC/PPC32AsmPrinter.cpp Tue Aug 17 21:22:55 2004 @@ -45,7 +45,7 @@ PPC32AsmPrinter(std::ostream &O, TargetMachine &TM) : AsmPrinter(O, TM), LabelNumber(0) { - CommentChar = ";"; + CommentString = ";"; GlobalPrefix = "_"; ZeroDirective = "\t.space\t"; // ".space N" emits N zeros. Data64bitsDirective = 0; // we can't emit a 64-bit unit @@ -123,7 +123,7 @@ for (unsigned i = 0, e = CP.size(); i != e; ++i) { O << "\t.const\n"; emitAlignment(TD.getTypeAlignmentShift(CP[i]->getType())); - O << ".CPI" << CurrentFnName << "_" << i << ":\t\t\t\t\t" << CommentChar + O << ".CPI" << CurrentFnName << "_" << i << ":\t\t\t\t\t" << CommentString << *CP[i] << "\n"; emitGlobalConstant(CP[i]); } @@ -150,7 +150,7 @@ I != E; ++I) { // Print a label for the basic block. O << ".LBB" << CurrentFnName << "_" << I->getNumber() << ":\t" - << CommentChar << " " << I->getBasicBlock()->getName() << "\n"; + << CommentString << " " << I->getBasicBlock()->getName() << "\n"; for (MachineBasicBlock::const_iterator II = I->begin(), E = I->end(); II != E; ++II) { // Print the assembly for the instruction. From lattner at cs.uiuc.edu Wed Aug 18 00:29:20 2004 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Wed, 18 Aug 2004 00:29:20 -0500 Subject: [llvm-commits] CVS: llvm/lib/Target/SparcV9/SparcV9AsmPrinter.cpp SparcV9Internals.h Message-ID: <200408180529.AAA05345@apoc.cs.uiuc.edu> Changes in directory llvm/lib/Target/SparcV9: SparcV9AsmPrinter.cpp updated: 1.118 -> 1.119 SparcV9Internals.h updated: 1.114 -> 1.115 --- Log message: Switch V9 over to using the AsmPrinter base class to do its constant printing Massive thanks to the brg miester for doing the testing. :) --- Diffs of the changes: (+91 -505) Index: llvm/lib/Target/SparcV9/SparcV9AsmPrinter.cpp diff -u llvm/lib/Target/SparcV9/SparcV9AsmPrinter.cpp:1.118 llvm/lib/Target/SparcV9/SparcV9AsmPrinter.cpp:1.119 --- llvm/lib/Target/SparcV9/SparcV9AsmPrinter.cpp:1.118 Mon Aug 16 16:54:29 2004 +++ llvm/lib/Target/SparcV9/SparcV9AsmPrinter.cpp Wed Aug 18 00:29:08 2004 @@ -23,6 +23,7 @@ #include "llvm/Module.h" #include "llvm/Pass.h" #include "llvm/Assembly/Writer.h" +#include "llvm/CodeGen/AsmPrinter.h" #include "llvm/CodeGen/MachineConstantPool.h" #include "llvm/CodeGen/MachineFunction.h" #include "llvm/CodeGen/MachineInstr.h" @@ -36,141 +37,11 @@ namespace { Statistic<> EmittedInsts("asm-printer", "Number of machine instrs printed"); - - //===--------------------------------------------------------------------===// - // Utility functions - - /// getAsCString - Return the specified array as a C compatible string, only - /// if the predicate isString() is true. - /// - std::string getAsCString(const ConstantArray *CVA) { - assert(CVA->isString() && "Array is not string compatible!"); - - std::string Result = "\""; - for (unsigned i = 0; i != CVA->getNumOperands(); ++i) { - unsigned char C = cast(CVA->getOperand(i))->getRawValue(); - - if (C == '"') { - Result += "\\\""; - } else if (C == '\\') { - Result += "\\\\"; - } else if (isprint(C)) { - Result += C; - } else { - Result += '\\'; // print all other chars as octal value - // Convert C to octal representation - Result += ((C >> 6) & 7) + '0'; - Result += ((C >> 3) & 7) + '0'; - Result += ((C >> 0) & 7) + '0'; - } - } - Result += "\""; - - return Result; - } - - inline bool ArrayTypeIsString(const ArrayType* arrayType) { - return (arrayType->getElementType() == Type::UByteTy || - arrayType->getElementType() == Type::SByteTy); - } - - unsigned findOptimalStorageSize(const TargetMachine &TM, const Type *Ty) { - // All integer types smaller than ints promote to 4 byte integers. - if (Ty->isIntegral() && Ty->getPrimitiveSize() < 4) - return 4; - - return TM.getTargetData().getTypeSize(Ty); - } - - - inline const std::string - TypeToDataDirective(const Type* type) { - switch(type->getTypeID()) { - case Type::BoolTyID: case Type::UByteTyID: case Type::SByteTyID: - return ".byte"; - case Type::UShortTyID: case Type::ShortTyID: - return ".half"; - case Type::UIntTyID: case Type::IntTyID: - return ".word"; - case Type::ULongTyID: case Type::LongTyID: case Type::PointerTyID: - return ".xword"; - case Type::FloatTyID: - return ".word"; - case Type::DoubleTyID: - return ".xword"; - case Type::ArrayTyID: - if (ArrayTypeIsString((ArrayType*) type)) - return ".ascii"; - else - return ""; - default: - return ""; - } - } - - /// Get the size of the constant for the given target. - /// If this is an unsized array, return 0. - /// - inline unsigned int - ConstantToSize(const Constant* CV, const TargetMachine& target) { - if (const ConstantArray* CVA = dyn_cast(CV)) { - const ArrayType *aty = cast(CVA->getType()); - if (ArrayTypeIsString(aty)) - return 1 + CVA->getNumOperands(); - } - - return findOptimalStorageSize(target, CV->getType()); - } - - /// Align data larger than one L1 cache line on L1 cache line boundaries. - /// Align all smaller data on the next higher 2^x boundary (4, 8, ...). - /// - inline unsigned int - SizeToAlignment(unsigned int size, const TargetMachine& target) { - const unsigned short cacheLineSize = 16; - if (size > (unsigned) cacheLineSize / 2) - return cacheLineSize; - else - for (unsigned sz=1; /*no condition*/; sz *= 2) - if (sz >= size) - return sz; - } - - /// Get the size of the type and then use SizeToAlignment. - /// - inline unsigned int - TypeToAlignment(const Type* type, const TargetMachine& target) { - return SizeToAlignment(findOptimalStorageSize(target, type), target); - } - - /// Get the size of the constant and then use SizeToAlignment. - /// Handles strings as a special case; - inline unsigned int - ConstantToAlignment(const Constant* CV, const TargetMachine& target) { - if (const ConstantArray* CVA = dyn_cast(CV)) - if (ArrayTypeIsString(cast(CVA->getType()))) - return SizeToAlignment(1 + CVA->getNumOperands(), target); - - return TypeToAlignment(CV->getType(), target); - } - -} // End anonymous namespace - - - -//===---------------------------------------------------------------------===// -// Code abstracted away from the AsmPrinter -//===---------------------------------------------------------------------===// +} namespace { - class AsmPrinter { - // Mangle symbol names appropriately - Mangler *Mang; - + struct SparcV9AsmPrinter : public AsmPrinter { public: - std::ostream &toAsm; - const TargetMachine &Target; - enum Sections { Unknown, Text, @@ -179,64 +50,32 @@ ZeroInitRWData, } CurSection; - AsmPrinter(std::ostream &os, const TargetMachine &T) - : /* idTable(0), */ toAsm(os), Target(T), CurSection(Unknown) {} - - ~AsmPrinter() { - delete Mang; - } - - // (start|end)(Module|Function) - Callback methods invoked by subclasses - void startModule(Module &M) { - Mang = new Mangler(M); + SparcV9AsmPrinter(std::ostream &OS, TargetMachine &TM) + : AsmPrinter(OS, TM), CurSection(Unknown) { + ZeroDirective = 0; // No way to get zeros. + Data16bitsDirective = "\t.half\t"; + Data32bitsDirective = "\t.word\t"; + Data64bitsDirective = "\t.xword\t"; + CommentString = "!"; } - void PrintZeroBytesToPad(int numBytes) { - // - // Always use single unsigned bytes for padding. We don't know upon - // what data size the beginning address is aligned, so using anything - // other than a byte may cause alignment errors in the assembler. - // - while (numBytes--) - printSingleConstantValue(Constant::getNullValue(Type::UByteTy)); + const char *getPassName() const { + return "SparcV9 Assembly Printer"; } - /// Print a single constant value. - /// - void printSingleConstantValue(const Constant* CV); - - /// Print a constant value or values (it may be an aggregate). - /// Uses printSingleConstantValue() to print each individual value. - /// - void printConstantValueOnly(const Constant* CV, int numPadBytesAfter = 0); - // Print a constant (which may be an aggregate) prefixed by all the // appropriate directives. Uses printConstantValueOnly() to print the // value or values. - void printConstant(const Constant* CV, std::string valID = "") { - if (valID.length() == 0) - valID = getID(CV); - - toAsm << "\t.align\t" << ConstantToAlignment(CV, Target) << "\n"; - - // Print .size and .type only if it is not a string. - if (const ConstantArray *CVA = dyn_cast(CV)) - if (CVA->isString()) { - // print it as a string and return - toAsm << valID << ":\n"; - toAsm << "\t" << ".ascii" << "\t" << getAsCString(CVA) << "\n"; - return; - } - - toAsm << "\t.type" << "\t" << valID << ",#object\n"; + void printConstant(const Constant* CV, const std::string &valID) { + emitAlignment(TM.getTargetData().getTypeAlignmentShift(CV->getType())); + O << "\t.type" << "\t" << valID << ",#object\n"; - unsigned int constSize = ConstantToSize(CV, Target); - if (constSize) - toAsm << "\t.size" << "\t" << valID << "," << constSize << "\n"; + unsigned constSize = TM.getTargetData().getTypeSize(CV->getType()); + O << "\t.size" << "\t" << valID << "," << constSize << "\n"; - toAsm << valID << ":\n"; + O << valID << ":\n"; - printConstantValueOnly(CV); + emitGlobalConstant(CV); } // enterSection - Use this method to enter a different section of the output @@ -246,16 +85,16 @@ if (S == CurSection) return; // Only switch section if necessary CurSection = S; - toAsm << "\n\t.section "; + O << "\n\t.section "; switch (S) { default: assert(0 && "Bad section name!"); - case Text: toAsm << "\".text\""; break; - case ReadOnlyData: toAsm << "\".rodata\",#alloc"; break; - case InitRWData: toAsm << "\".data\",#alloc,#write"; break; - case ZeroInitRWData: toAsm << "\".bss\",#alloc,#write"; break; + case Text: O << "\".text\""; break; + case ReadOnlyData: O << "\".rodata\",#alloc"; break; + case InitRWData: O << "\".data\",#alloc,#write"; break; + case ZeroInitRWData: O << "\".bss\",#alloc,#write"; break; } - toAsm << "\n"; + O << "\n"; } // getID Wrappers - Ensure consistent usage @@ -283,263 +122,19 @@ return ""; } - // Combines expressions - inline std::string ConstantArithExprToString(const ConstantExpr* CE, - const TargetMachine &TM, - const std::string &op) { - return "(" + valToExprString(CE->getOperand(0), TM) + op - + valToExprString(CE->getOperand(1), TM) + ")"; - } - - /// ConstantExprToString() - Convert a ConstantExpr to an asm expression - /// and return this as a string. - /// - std::string ConstantExprToString(const ConstantExpr* CE, - const TargetMachine& target); - - /// valToExprString - Helper function for ConstantExprToString(). - /// Appends result to argument string S. - /// - std::string valToExprString(const Value* V, const TargetMachine& target); - }; -} // End anonymous namespace - - -/// Print a single constant value. -/// -void AsmPrinter::printSingleConstantValue(const Constant* CV) { - assert(CV->getType() != Type::VoidTy && - CV->getType() != Type::LabelTy && - "Unexpected type for Constant"); - - assert((!isa(CV) && ! isa(CV)) - && "Aggregate types should be handled outside this function"); - - toAsm << "\t" << TypeToDataDirective(CV->getType()) << "\t"; - - if (const GlobalValue* GV = dyn_cast(CV)) { - toAsm << getID(GV) << "\n"; - } else if (isa(CV)) { - // Null pointer value - toAsm << "0\n"; - } else if (const ConstantExpr* CE = dyn_cast(CV)) { - // Constant expression built from operators, constants, and symbolic addrs - toAsm << ConstantExprToString(CE, Target) << "\n"; - } else if (CV->getType()->isPrimitiveType()) { - // Check primitive types last - if (CV->getType()->isFloatingPoint()) { - // FP Constants are printed as integer constants to avoid losing - // precision... - double Val = cast(CV)->getValue(); - if (CV->getType() == Type::FloatTy) { - float FVal = (float)Val; - char *ProxyPtr = (char*)&FVal; // Abide by C TBAA rules - toAsm << *(unsigned int*)ProxyPtr; - } else if (CV->getType() == Type::DoubleTy) { - char *ProxyPtr = (char*)&Val; // Abide by C TBAA rules - toAsm << *(uint64_t*)ProxyPtr; - } else { - assert(0 && "Unknown floating point type!"); - } - - toAsm << "\t! " << CV->getType()->getDescription() - << " value: " << Val << "\n"; - } else if (const ConstantBool *CB = dyn_cast(CV)) { - toAsm << (int)CB->getValue() << "\n"; - } else { - WriteAsOperand(toAsm, CV, false, false) << "\n"; - } - } else { - assert(0 && "Unknown elementary type for constant"); - } -} - -/// Print a constant value or values (it may be an aggregate). -/// Uses printSingleConstantValue() to print each individual value. -/// -void AsmPrinter::printConstantValueOnly(const Constant* CV, - int numPadBytesAfter) { - if (const ConstantArray *CVA = dyn_cast(CV)) { - if (CVA->isString()) { - // print the string alone and return - toAsm << "\t" << ".ascii" << "\t" << getAsCString(CVA) << "\n"; - } else { - // Not a string. Print the values in successive locations - for (unsigned i = 0, e = CVA->getNumOperands(); i != e; ++i) - printConstantValueOnly(CVA->getOperand(i)); - } - } else if (const ConstantStruct *CVS = dyn_cast(CV)) { - // Print the fields in successive locations. Pad to align if needed! - const StructLayout *cvsLayout = - Target.getTargetData().getStructLayout(CVS->getType()); - unsigned sizeSoFar = 0; - for (unsigned i = 0, e = CVS->getNumOperands(); i != e; ++i) { - const Constant* field = CVS->getOperand(i); - - // Check if padding is needed and insert one or more 0s. - unsigned fieldSize = - Target.getTargetData().getTypeSize(field->getType()); - int padSize = ((i == e-1? cvsLayout->StructSize - : cvsLayout->MemberOffsets[i+1]) - - cvsLayout->MemberOffsets[i]) - fieldSize; - sizeSoFar += (fieldSize + padSize); - - // Now print the actual field value - printConstantValueOnly(field, padSize); - } - assert(sizeSoFar == cvsLayout->StructSize && - "Layout of constant struct may be incorrect!"); - } else if (isa(CV)) { - PrintZeroBytesToPad(Target.getTargetData().getTypeSize(CV->getType())); - } else - printSingleConstantValue(CV); - - if (numPadBytesAfter) - PrintZeroBytesToPad(numPadBytesAfter); -} - -/// ConstantExprToString() - Convert a ConstantExpr to an asm expression -/// and return this as a string. -/// -std::string AsmPrinter::ConstantExprToString(const ConstantExpr* CE, - const TargetMachine& target) { - std::string S; - switch(CE->getOpcode()) { - case Instruction::GetElementPtr: - { // generate a symbolic expression for the byte address - const Value* ptrVal = CE->getOperand(0); - std::vector idxVec(CE->op_begin()+1, CE->op_end()); - const TargetData &TD = target.getTargetData(); - S += "(" + valToExprString(ptrVal, target) + ") + (" - + utostr(TD.getIndexedOffset(ptrVal->getType(),idxVec)) + ")"; - break; - } - - case Instruction::Cast: - // Support only non-converting casts for now, i.e., a no-op. - // This assertion is not a complete check. - assert(target.getTargetData().getTypeSize(CE->getType()) == - target.getTargetData().getTypeSize(CE->getOperand(0)->getType())); - S += "(" + valToExprString(CE->getOperand(0), target) + ")"; - break; - - case Instruction::Add: - S += ConstantArithExprToString(CE, target, ") + ("); - break; - - case Instruction::Sub: - S += ConstantArithExprToString(CE, target, ") - ("); - break; - - case Instruction::Mul: - S += ConstantArithExprToString(CE, target, ") * ("); - break; - - case Instruction::Div: - S += ConstantArithExprToString(CE, target, ") / ("); - break; - - case Instruction::Rem: - S += ConstantArithExprToString(CE, target, ") % ("); - break; - - case Instruction::And: - // Logical && for booleans; bitwise & otherwise - S += ConstantArithExprToString(CE, target, - ((CE->getType() == Type::BoolTy)? ") && (" : ") & (")); - break; - - case Instruction::Or: - // Logical || for booleans; bitwise | otherwise - S += ConstantArithExprToString(CE, target, - ((CE->getType() == Type::BoolTy)? ") || (" : ") | (")); - break; - - case Instruction::Xor: - // Bitwise ^ for all types - S += ConstantArithExprToString(CE, target, ") ^ ("); - break; - - default: - assert(0 && "Unsupported operator in ConstantExprToString()"); - break; - } - - return S; -} - -/// valToExprString - Helper function for ConstantExprToString(). -/// Appends result to argument string S. -/// -std::string AsmPrinter::valToExprString(const Value* V, - const TargetMachine& target) { - std::string S; - bool failed = false; - if (const GlobalValue* GV = dyn_cast(V)) { - S += getID(GV); - } else if (const Constant* CV = dyn_cast(V)) { // symbolic or known - if (const ConstantBool *CB = dyn_cast(CV)) - S += std::string(CB == ConstantBool::True ? "1" : "0"); - else if (const ConstantSInt *CI = dyn_cast(CV)) - S += itostr(CI->getValue()); - else if (const ConstantUInt *CI = dyn_cast(CV)) - S += utostr(CI->getValue()); - else if (const ConstantFP *CFP = dyn_cast(CV)) - S += ftostr(CFP->getValue()); - else if (isa(CV)) - S += "0"; - else if (const ConstantExpr *CE = dyn_cast(CV)) - S += ConstantExprToString(CE, target); - else - failed = true; - } else - failed = true; - - if (failed) { - assert(0 && "Cannot convert value to string"); - S += ""; - } - return S; -} - - -//===----------------------------------------------------------------------===// -// SparcV9AsmPrinter Code -//===----------------------------------------------------------------------===// - -namespace { - - struct SparcV9AsmPrinter : public FunctionPass, public AsmPrinter { - inline SparcV9AsmPrinter(std::ostream &os, const TargetMachine &t) - : AsmPrinter(os, t) {} - - const Function *currFunction; - - const char *getPassName() const { - return "Output SparcV9 Assembly for Functions"; - } - - virtual bool doInitialization(Module &M) { - startModule(M); - return false; - } - - virtual bool runOnFunction(Function &F) { - currFunction = &F; - emitFunction(F); + virtual bool runOnMachineFunction(MachineFunction &MF) { + setupMachineFunction(MF); + emitFunction(MF); return false; } virtual bool doFinalization(Module &M) { emitGlobals(M); + AsmPrinter::doFinalization(M); return false; } - virtual void getAnalysisUsage(AnalysisUsage &AU) const { - AU.setPreservesAll(); - } - - void emitFunction(const Function &F); + void emitFunction(MachineFunction &F); private : void emitBasicBlock(const MachineBasicBlock &MBB); void emitMachineInst(const MachineInstr *MI); @@ -581,33 +176,28 @@ inline bool SparcV9AsmPrinter::OpIsMemoryAddressBase(const MachineInstr *MI, unsigned int opNum) { - if (Target.getInstrInfo()->isLoad(MI->getOpcode())) + if (TM.getInstrInfo()->isLoad(MI->getOpcode())) return (opNum == 0); - else if (Target.getInstrInfo()->isStore(MI->getOpcode())) + else if (TM.getInstrInfo()->isStore(MI->getOpcode())) return (opNum == 1); else return false; } - -#define PrintOp1PlusOp2(mop1, mop2, opCode) \ - printOneOperand(mop1, opCode); \ - toAsm << "+"; \ - printOneOperand(mop2, opCode); - unsigned int -SparcV9AsmPrinter::printOperands(const MachineInstr *MI, - unsigned int opNum) -{ +SparcV9AsmPrinter::printOperands(const MachineInstr *MI, unsigned opNum) { const MachineOperand& mop = MI->getOperand(opNum); - if (OpIsBranchTargetLabel(MI, opNum)) { - PrintOp1PlusOp2(mop, MI->getOperand(opNum+1), MI->getOpcode()); + printOneOperand(mop, MI->getOpcode()); + O << "+"; + printOneOperand(MI->getOperand(opNum+1), MI->getOpcode()); return 2; } else if (OpIsMemoryAddressBase(MI, opNum)) { - toAsm << "["; - PrintOp1PlusOp2(mop, MI->getOperand(opNum+1), MI->getOpcode()); - toAsm << "]"; + O << "["; + printOneOperand(mop, MI->getOpcode()); + O << "+"; + printOneOperand(MI->getOperand(opNum+1), MI->getOpcode()); + O << "]"; return 2; } else { printOneOperand(mop, MI->getOpcode()); @@ -617,18 +207,18 @@ void SparcV9AsmPrinter::printOneOperand(const MachineOperand &mop, - MachineOpCode opCode) + MachineOpCode opCode) { bool needBitsFlag = true; if (mop.isHiBits32()) - toAsm << "%lm("; + O << "%lm("; else if (mop.isLoBits32()) - toAsm << "%lo("; + O << "%lo("; else if (mop.isHiBits64()) - toAsm << "%hh("; + O << "%hh("; else if (mop.isLoBits64()) - toAsm << "%hm("; + O << "%hm("; else needBitsFlag = false; @@ -640,19 +230,18 @@ { int regNum = (int)mop.getReg(); - if (regNum == Target.getRegInfo()->getInvalidRegNum()) { + if (regNum == TM.getRegInfo()->getInvalidRegNum()) { // better to print code with NULL registers than to die - toAsm << ""; + O << ""; } else { - toAsm << "%" << Target.getRegInfo()->getUnifiedRegName(regNum); + O << "%" << TM.getRegInfo()->getUnifiedRegName(regNum); } break; } case MachineOperand::MO_ConstantPoolIndex: { - toAsm << ".CPI_" << getID(currFunction) - << "_" << mop.getConstantPoolIndex(); + O << ".CPI_" << CurrentFnName << "_" << mop.getConstantPoolIndex(); break; } @@ -662,42 +251,42 @@ assert(Val && "\tNULL Value in SparcV9AsmPrinter"); if (const BasicBlock *BB = dyn_cast(Val)) - toAsm << getID(BB); + O << getID(BB); else if (const Function *F = dyn_cast(Val)) - toAsm << getID(F); + O << getID(F); else if (const GlobalVariable *GV = dyn_cast(Val)) - toAsm << getID(GV); + O << getID(GV); else if (const Constant *CV = dyn_cast(Val)) - toAsm << getID(CV); + O << getID(CV); else assert(0 && "Unrecognized value in SparcV9AsmPrinter"); break; } case MachineOperand::MO_SignExtendedImmed: - toAsm << mop.getImmedValue(); + O << mop.getImmedValue(); break; case MachineOperand::MO_UnextendedImmed: - toAsm << (uint64_t) mop.getImmedValue(); + O << (uint64_t) mop.getImmedValue(); break; default: - toAsm << mop; // use dump field + O << mop; // use dump field break; } if (needBitsFlag) - toAsm << ")"; + O << ")"; } void SparcV9AsmPrinter::emitMachineInst(const MachineInstr *MI) { unsigned Opcode = MI->getOpcode(); - if (Target.getInstrInfo()->isDummyPhiInstr(Opcode)) + if (TM.getInstrInfo()->isDummyPhiInstr(Opcode)) return; // IGNORE PHI NODES - toAsm << "\t" << Target.getInstrInfo()->getName(Opcode) << "\t"; + O << "\t" << TM.getInstrInfo()->getName(Opcode) << "\t"; unsigned Mask = getOperandMask(Opcode); @@ -705,74 +294,72 @@ unsigned N = 1; for (unsigned OpNum = 0; OpNum < MI->getNumOperands(); OpNum += N) if (! ((1 << OpNum) & Mask)) { // Ignore this operand? - if (NeedComma) toAsm << ", "; // Handle comma outputting + if (NeedComma) O << ", "; // Handle comma outputting NeedComma = true; N = printOperands(MI, OpNum); } else N = 1; - toAsm << "\n"; + O << "\n"; ++EmittedInsts; } void SparcV9AsmPrinter::emitBasicBlock(const MachineBasicBlock &MBB) { // Emit a label for the basic block - toAsm << getID(MBB.getBasicBlock()) << ":\n"; + O << getID(MBB.getBasicBlock()) << ":\n"; // Loop over all of the instructions in the basic block... for (MachineBasicBlock::const_iterator MII = MBB.begin(), MIE = MBB.end(); MII != MIE; ++MII) emitMachineInst(MII); - toAsm << "\n"; // Separate BB's with newlines + O << "\n"; // Separate BB's with newlines } -void SparcV9AsmPrinter::emitFunction(const Function &F) { - std::string methName = getID(&F); - toAsm << "!****** Outputing Function: " << methName << " ******\n"; +void SparcV9AsmPrinter::emitFunction(MachineFunction &MF) { + O << "!****** Outputing Function: " << CurrentFnName << " ******\n"; // Emit constant pool for this function - const MachineConstantPool *MCP = MachineFunction::get(&F).getConstantPool(); + const MachineConstantPool *MCP = MF.getConstantPool(); const std::vector &CP = MCP->getConstants(); - enterSection(AsmPrinter::ReadOnlyData); + enterSection(ReadOnlyData); for (unsigned i = 0, e = CP.size(); i != e; ++i) { - std::string cpiName = ".CPI_" + methName + "_" + utostr(i); + std::string cpiName = ".CPI_" + CurrentFnName + "_" + utostr(i); printConstant(CP[i], cpiName); } - enterSection(AsmPrinter::Text); - toAsm << "\t.align\t4\n\t.global\t" << methName << "\n"; - //toAsm << "\t.type\t" << methName << ",#function\n"; - toAsm << "\t.type\t" << methName << ", 2\n"; - toAsm << methName << ":\n"; + enterSection(Text); + O << "\t.align\t4\n\t.global\t" << CurrentFnName << "\n"; + //O << "\t.type\t" << CurrentFnName << ",#function\n"; + O << "\t.type\t" << CurrentFnName << ", 2\n"; + O << CurrentFnName << ":\n"; // Output code for all of the basic blocks in the function... - MachineFunction &MF = MachineFunction::get(&F); for (MachineFunction::const_iterator I = MF.begin(), E = MF.end(); I != E;++I) emitBasicBlock(*I); // Output a .size directive so the debugger knows the extents of the function - toAsm << ".EndOf_" << methName << ":\n\t.size " - << methName << ", .EndOf_" - << methName << "-" << methName << "\n"; + O << ".EndOf_" << CurrentFnName << ":\n\t.size " + << CurrentFnName << ", .EndOf_" + << CurrentFnName << "-" << CurrentFnName << "\n"; // Put some spaces between the functions - toAsm << "\n\n"; + O << "\n\n"; } void SparcV9AsmPrinter::printGlobalVariable(const GlobalVariable* GV) { if (GV->hasExternalLinkage()) - toAsm << "\t.global\t" << getID(GV) << "\n"; + O << "\t.global\t" << getID(GV) << "\n"; if (GV->hasInitializer() && ! GV->getInitializer()->isNullValue()) { printConstant(GV->getInitializer(), getID(GV)); } else { - toAsm << "\t.align\t" << TypeToAlignment(GV->getType()->getElementType(), - Target) << "\n"; - toAsm << "\t.type\t" << getID(GV) << ",#object\n"; - toAsm << "\t.reserve\t" << getID(GV) << "," - << findOptimalStorageSize(Target, GV->getType()->getElementType()) - << "\n"; + const Type *ValTy = GV->getType()->getElementType(); + emitAlignment(TM.getTargetData().getTypeAlignmentShift(ValTy)); + O << "\t.type\t" << getID(GV) << ",#object\n"; + O << "\t.reserve\t" << getID(GV) << "," + << TM.getTargetData().getTypeSize(GV->getType()->getElementType()) + << "\n"; } } @@ -782,19 +369,18 @@ if (! GI->isExternal()) { assert(GI->hasInitializer()); if (GI->isConstant()) - enterSection(AsmPrinter::ReadOnlyData); // read-only, initialized data + enterSection(ReadOnlyData); // read-only, initialized data else if (GI->getInitializer()->isNullValue()) - enterSection(AsmPrinter::ZeroInitRWData); // read-write zero data + enterSection(ZeroInitRWData); // read-write zero data else - enterSection(AsmPrinter::InitRWData); // read-write non-zero data + enterSection(InitRWData); // read-write non-zero data printGlobalVariable(GI); } - toAsm << "\n"; + O << "\n"; } -FunctionPass *llvm::createAsmPrinterPass(std::ostream &Out, - const TargetMachine &TM) { +FunctionPass *llvm::createAsmPrinterPass(std::ostream &Out, TargetMachine &TM) { return new SparcV9AsmPrinter(Out, TM); } Index: llvm/lib/Target/SparcV9/SparcV9Internals.h diff -u llvm/lib/Target/SparcV9/SparcV9Internals.h:1.114 llvm/lib/Target/SparcV9/SparcV9Internals.h:1.115 --- llvm/lib/Target/SparcV9/SparcV9Internals.h:1.114 Sun Apr 25 02:04:49 2004 +++ llvm/lib/Target/SparcV9/SparcV9Internals.h Wed Aug 18 00:29:08 2004 @@ -103,7 +103,7 @@ /// Writes out assembly code for the module, one function at a time /// -FunctionPass *createAsmPrinterPass(std::ostream &Out, const TargetMachine &TM); +FunctionPass *createAsmPrinterPass(std::ostream &Out, TargetMachine &TM); /// getPrologEpilogInsertionPass - Inserts prolog/epilog code. /// From lattner at cs.uiuc.edu Wed Aug 18 12:38:48 2004 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Wed, 18 Aug 2004 12:38:48 -0500 Subject: [llvm-commits] CVS: llvm-www/Developers.html Message-ID: <200408181738.MAA07538@apoc.cs.uiuc.edu> Changes in directory llvm-www: Developers.html added (r1.1) --- Log message: Add an LLVM developers page. I'm just doing the checkin for Reid, who did all of the work, thanks Reid! --- Diffs of the changes: (+71 -0) Index: llvm-www/Developers.html diff -c /dev/null llvm-www/Developers.html:1.1 *** /dev/null Wed Aug 18 12:38:47 2004 --- llvm-www/Developers.html Wed Aug 18 12:38:36 2004 *************** *** 0 **** --- 1,71 ---- + + +
    Meet The LLVM Developers
    + +

    The developers of LLVM have a variety of backgrounds and interests. This page + provides links to each developer's home page (or LLVM page if they have one). + If you'd like to get a link added to this page, email or contact us!

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    NamePicture
    Vikram Adve + vadve +
    Nate Begeman + Sampo +
    Tanya Brethour + Tonic +
    Misha Brukman + LLVM Bug
+       #100 +
    John CriswellDogbert
    Brian Gaeke + Repo^H^Hopt Man +
    Brad Jones + KungFooMaster
    Chris LattnerSabre
    Reid Spencer + Reid +
    + + From lattner at cs.uiuc.edu Wed Aug 18 12:41:29 2004 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Wed, 18 Aug 2004 12:41:29 -0500 Subject: [llvm-commits] CVS: llvm-www/header.incl Message-ID: <200408181741.MAA07565@apoc.cs.uiuc.edu> Changes in directory llvm-www: header.incl updated: 1.25 -> 1.26 --- Log message: Add link to the developer page, get closer to validation --- Diffs of the changes: (+2 -1) Index: llvm-www/header.incl diff -u llvm-www/header.incl:1.25 llvm-www/header.incl:1.26 --- llvm-www/header.incl:1.25 Fri Aug 13 17:40:32 2004 +++ llvm-www/header.incl Wed Aug 18 12:41:18 2004 @@ -11,7 +11,7 @@ The LLVM Compiler Infrastructure
    - +
    - - + From gaeke at cs.uiuc.edu Wed Aug 18 15:04:36 2004 From: gaeke at cs.uiuc.edu (Brian Gaeke) Date: Wed, 18 Aug 2004 15:04:36 -0500 (CDT) Subject: [llvm-commits] CVS: llvm/lib/CodeGen/InstrSched/InstrScheduling.cpp Message-ID: <200408182004.PAA02581@kain.cs.uiuc.edu> Changes in directory llvm/lib/CodeGen/InstrSched: InstrScheduling.cpp updated: 1.76 -> 1.77 --- Log message: Instead of using isDummyPhiInstr, we just compare the opcode with V9::PHI. Also, squash a use of TargetInstrInfo::isNop(). --- Diffs of the changes: (+3 -3) Index: llvm/lib/CodeGen/InstrSched/InstrScheduling.cpp diff -u llvm/lib/CodeGen/InstrSched/InstrScheduling.cpp:1.76 llvm/lib/CodeGen/InstrSched/InstrScheduling.cpp:1.77 --- llvm/lib/CodeGen/InstrSched/InstrScheduling.cpp:1.76 Mon Aug 16 16:55:01 2004 +++ llvm/lib/CodeGen/InstrSched/InstrScheduling.cpp Wed Aug 18 15:04:21 2004 @@ -19,6 +19,7 @@ #include "llvm/Target/TargetMachine.h" #include "../../Target/SparcV9/MachineCodeForInstruction.h" #include "../../Target/SparcV9/LiveVar/FunctionLiveVarInfo.h" +#include "../../Target/SparcV9/SparcV9InstrInfo.h" #include "Support/CommandLine.h" #include #include @@ -633,8 +634,7 @@ // some NOPs from delay slots. Also, PHIs are not included in the schedule. unsigned numInstr = 0; for (MachineBasicBlock::iterator I=MBB.begin(); I != MBB.end(); ++I) - if (! mii.isNop(I->getOpcode()) && - ! mii.isDummyPhiInstr(I->getOpcode())) + if (!(I->getOpcode() == V9::NOP || I->getOpcode() == V9::PHI)) ++numInstr; assert(S.isched.getNumInstructions() >= numInstr && "Lost some non-NOP instructions during scheduling!"); @@ -645,7 +645,7 @@ // First find the dummy instructions at the start of the basic block MachineBasicBlock::iterator I = MBB.begin(); for ( ; I != MBB.end(); ++I) - if (! mii.isDummyPhiInstr(I->getOpcode())) + if (I->getOpcode() != V9::PHI) break; // Remove all except the dummy PHI instructions from MBB, and From gaeke at cs.uiuc.edu Wed Aug 18 15:04:36 2004 From: gaeke at cs.uiuc.edu (Brian Gaeke) Date: Wed, 18 Aug 2004 15:04:36 -0500 (CDT) Subject: [llvm-commits] CVS: llvm/lib/Target/SparcV9/RegAlloc/PhyRegAlloc.cpp Message-ID: <200408182004.PAA02584@kain.cs.uiuc.edu> Changes in directory llvm/lib/Target/SparcV9/RegAlloc: PhyRegAlloc.cpp updated: 1.162 -> 1.163 --- Log message: Instead of using isDummyPhiInstr, we just compare the opcode with V9::PHI. --- Diffs of the changes: (+2 -2) Index: llvm/lib/Target/SparcV9/RegAlloc/PhyRegAlloc.cpp diff -u llvm/lib/Target/SparcV9/RegAlloc/PhyRegAlloc.cpp:1.162 llvm/lib/Target/SparcV9/RegAlloc/PhyRegAlloc.cpp:1.163 --- llvm/lib/Target/SparcV9/RegAlloc/PhyRegAlloc.cpp:1.162 Wed Aug 18 13:13:37 2004 +++ llvm/lib/Target/SparcV9/RegAlloc/PhyRegAlloc.cpp Wed Aug 18 15:04:24 2004 @@ -484,7 +484,7 @@ // their assigned registers or insert spill code, as appropriate. // Also, fix operands of call/return instructions. for (MachineBasicBlock::iterator MII = MBB.begin(); MII != MBB.end(); ++MII) - if (! TM.getInstrInfo()->isDummyPhiInstr(MII->getOpcode())) + if (MII->getOpcode() != V9::PHI) updateInstruction(MII, MBB); // Now, move code out of delay slots of branches and returns if needed. @@ -552,7 +552,7 @@ MachineInstr *MInst = MII; // do not process Phis - if (TM.getInstrInfo()->isDummyPhiInstr(MInst->getOpcode())) + if (MInst->getOpcode() == V9::PHI) continue; // if there are any added instructions... From gaeke at cs.uiuc.edu Wed Aug 18 15:04:36 2004 From: gaeke at cs.uiuc.edu (Brian Gaeke) Date: Wed, 18 Aug 2004 15:04:36 -0500 (CDT) Subject: [llvm-commits] CVS: llvm/lib/CodeGen/ModuloScheduling/ModuloScheduling.cpp Message-ID: <200408182004.PAA02587@kain.cs.uiuc.edu> Changes in directory llvm/lib/CodeGen/ModuloScheduling: ModuloScheduling.cpp updated: 1.25 -> 1.26 --- Log message: Instead of using isDummyPhiInstr, we just compare the opcode with V9::PHI. --- Diffs of the changes: (+2 -4) Index: llvm/lib/CodeGen/ModuloScheduling/ModuloScheduling.cpp diff -u llvm/lib/CodeGen/ModuloScheduling/ModuloScheduling.cpp:1.25 llvm/lib/CodeGen/ModuloScheduling/ModuloScheduling.cpp:1.26 --- llvm/lib/CodeGen/ModuloScheduling/ModuloScheduling.cpp:1.25 Mon Aug 16 16:55:02 2004 +++ llvm/lib/CodeGen/ModuloScheduling/ModuloScheduling.cpp Wed Aug 18 15:04:23 2004 @@ -1444,8 +1444,7 @@ //Start with the kernel and for each phi insert a copy for the phi def and for each arg for(MachineBasicBlock::iterator I = kernelBB->begin(), E = kernelBB->end(); I != E; ++I) { //Get op code and check if its a phi - MachineOpCode OC = I->getOpcode(); - if(TMI->isDummyPhiInstr(OC)) { + if(I->getOpcode() == V9::PHI) { Instruction *tmp = 0; for(unsigned i = 0; i < I->getNumOperands(); ++i) { //Get Operand @@ -1491,8 +1490,7 @@ for(std::vector::iterator MB = epilogues.begin(), ME = epilogues.end(); MB != ME; ++MB) { for(MachineBasicBlock::iterator I = (*MB)->begin(), E = (*MB)->end(); I != E; ++I) { //Get op code and check if its a phi - MachineOpCode OC = I->getOpcode(); - if(TMI->isDummyPhiInstr(OC)) { + if(I->getOpcode() == V9::PHI) { Instruction *tmp = 0; for(unsigned i = 0; i < I->getNumOperands(); ++i) { //Get Operand From gaeke at cs.uiuc.edu Wed Aug 18 15:04:37 2004 From: gaeke at cs.uiuc.edu (Brian Gaeke) Date: Wed, 18 Aug 2004 15:04:37 -0500 (CDT) Subject: [llvm-commits] CVS: llvm/lib/CodeGen/InstrSched/SchedGraph.cpp Message-ID: <200408182004.PAA02590@kain.cs.uiuc.edu> Changes in directory llvm/lib/CodeGen/InstrSched: SchedGraph.cpp updated: 1.65 -> 1.66 --- Log message: Instead of using isDummyPhiInstr, we just compare the opcode with V9::PHI. --- Diffs of the changes: (+2 -1) Index: llvm/lib/CodeGen/InstrSched/SchedGraph.cpp diff -u llvm/lib/CodeGen/InstrSched/SchedGraph.cpp:1.65 llvm/lib/CodeGen/InstrSched/SchedGraph.cpp:1.66 --- llvm/lib/CodeGen/InstrSched/SchedGraph.cpp:1.65 Mon Aug 16 16:55:01 2004 +++ llvm/lib/CodeGen/InstrSched/SchedGraph.cpp Wed Aug 18 15:04:23 2004 @@ -21,6 +21,7 @@ #include "llvm/Target/TargetMachine.h" #include "../../Target/SparcV9/MachineCodeForInstruction.h" #include "../../Target/SparcV9/SparcV9RegInfo.h" +#include "../../Target/SparcV9/SparcV9InstrInfo.h" #include "Support/STLExtras.h" #include @@ -561,7 +562,7 @@ unsigned i = 0; for (MachineBasicBlock::iterator I = MBB.begin(), E = MBB.end(); I != E; ++I, ++i) - if (!mii.isDummyPhiInstr(I->getOpcode())) { + if (I->getOpcode() != V9::PHI) { SchedGraphNode* node = new SchedGraphNode(getNumNodes(), &MBB, i, target); noteGraphNodeForInstr(I, node); From gaeke at cs.uiuc.edu Wed Aug 18 15:04:37 2004 From: gaeke at cs.uiuc.edu (Brian Gaeke) Date: Wed, 18 Aug 2004 15:04:37 -0500 (CDT) Subject: [llvm-commits] CVS: llvm/lib/Target/SparcV9/SparcV9AsmPrinter.cpp Message-ID: <200408182004.PAA02593@kain.cs.uiuc.edu> Changes in directory llvm/lib/Target/SparcV9: SparcV9AsmPrinter.cpp updated: 1.119 -> 1.120 --- Log message: Instead of using isDummyPhiInstr, we just compare the opcode with V9::PHI. --- Diffs of the changes: (+2 -2) Index: llvm/lib/Target/SparcV9/SparcV9AsmPrinter.cpp diff -u llvm/lib/Target/SparcV9/SparcV9AsmPrinter.cpp:1.119 llvm/lib/Target/SparcV9/SparcV9AsmPrinter.cpp:1.120 --- llvm/lib/Target/SparcV9/SparcV9AsmPrinter.cpp:1.119 Wed Aug 18 00:29:08 2004 +++ llvm/lib/Target/SparcV9/SparcV9AsmPrinter.cpp Wed Aug 18 15:04:23 2004 @@ -283,8 +283,8 @@ void SparcV9AsmPrinter::emitMachineInst(const MachineInstr *MI) { unsigned Opcode = MI->getOpcode(); - if (TM.getInstrInfo()->isDummyPhiInstr(Opcode)) - return; // IGNORE PHI NODES + if (Opcode == V9::PHI) + return; // Ignore Machine-PHI nodes. O << "\t" << TM.getInstrInfo()->getName(Opcode) << "\t"; From gaeke at cs.uiuc.edu Wed Aug 18 15:04:40 2004 From: gaeke at cs.uiuc.edu (Brian Gaeke) Date: Wed, 18 Aug 2004 15:04:40 -0500 (CDT) Subject: [llvm-commits] CVS: llvm/lib/Target/SparcV9/SparcV9Instr.def Message-ID: <200408182004.PAA02602@kain.cs.uiuc.edu> Changes in directory llvm/lib/Target/SparcV9: SparcV9Instr.def updated: 1.28 -> 1.29 --- Log message: M_DUMMY_PHI_FLAG is no longer used to distinguish V9::PHI. Get rid of it and its TargetInstrInfo accessor. --- Diffs of the changes: (+1 -2) Index: llvm/lib/Target/SparcV9/SparcV9Instr.def diff -u llvm/lib/Target/SparcV9/SparcV9Instr.def:1.28 llvm/lib/Target/SparcV9/SparcV9Instr.def:1.29 --- llvm/lib/Target/SparcV9/SparcV9Instr.def:1.28 Wed Aug 18 12:44:16 2004 +++ llvm/lib/Target/SparcV9/SparcV9Instr.def Wed Aug 18 15:04:28 2004 @@ -530,8 +530,7 @@ // Synthetic phi operation for near-SSA form of machine code // Number of operands is variable, indicated by -1. Result is the first op. -I(PHI, "", -1, 0, 0, false, 0, 0, SPARC_NONE, M_DUMMY_PHI_FLAG) - +I(PHI, "", -1, 0, 0, false, 0, 0, SPARC_NONE, 0) #undef B5 #undef B6 From gaeke at cs.uiuc.edu Wed Aug 18 15:04:41 2004 From: gaeke at cs.uiuc.edu (Brian Gaeke) Date: Wed, 18 Aug 2004 15:04:41 -0500 (CDT) Subject: [llvm-commits] CVS: llvm/include/llvm/Target/TargetInstrInfo.h Message-ID: <200408182004.PAA02605@kain.cs.uiuc.edu> Changes in directory llvm/include/llvm/Target: TargetInstrInfo.h updated: 1.68 -> 1.69 --- Log message: M_DUMMY_PHI_FLAG is no longer used to distinguish V9::PHI. Get rid of it and its TargetInstrInfo accessor. --- Diffs of the changes: (+0 -5) Index: llvm/include/llvm/Target/TargetInstrInfo.h diff -u llvm/include/llvm/Target/TargetInstrInfo.h:1.68 llvm/include/llvm/Target/TargetInstrInfo.h:1.69 --- llvm/include/llvm/Target/TargetInstrInfo.h:1.68 Wed Aug 18 12:44:17 2004 +++ llvm/include/llvm/Target/TargetInstrInfo.h Wed Aug 18 15:04:28 2004 @@ -51,7 +51,6 @@ const unsigned M_CC_FLAG = 1 << 6; const unsigned M_LOAD_FLAG = 1 << 10; const unsigned M_STORE_FLAG = 1 << 12; -const unsigned M_DUMMY_PHI_FLAG = 1 << 13; // 3-addr instructions which really work like 2-addr ones, eg. X86 add/sub const unsigned M_2_ADDR_FLAG = 1 << 15; @@ -203,10 +202,6 @@ bool isStore(MachineOpCode Opcode) const { return get(Opcode).Flags & M_STORE_FLAG; } - bool isDummyPhiInstr(MachineOpCode Opcode) const { - return get(Opcode).Flags & M_DUMMY_PHI_FLAG; - } - virtual bool hasResultInterlock(MachineOpCode Opcode) const { return true; } From reid at x10sys.com Wed Aug 18 15:06:30 2004 From: reid at x10sys.com (Reid Spencer) Date: Wed, 18 Aug 2004 15:06:30 -0500 Subject: [llvm-commits] CVS: llvm/docs/BytecodeFormat.html Message-ID: <200408182006.PAA02138@zion.cs.uiuc.edu> Changes in directory llvm/docs: BytecodeFormat.html updated: 1.27 -> 1.28 --- Log message: Provided opcode definitions. Clarified documentation of symbol tables. Clarified definition of slot numbers. Added the http-equiv meta tag for HTML 4.01 strict compliance. Adjusted line lengths. Differentiated between "type slot" and "value slot" everywhere. ispelled it. --- Diffs of the changes: (+183 -90) Index: llvm/docs/BytecodeFormat.html diff -u llvm/docs/BytecodeFormat.html:1.27 llvm/docs/BytecodeFormat.html:1.28 --- llvm/docs/BytecodeFormat.html:1.27 Tue Aug 17 02:43:43 2004 +++ llvm/docs/BytecodeFormat.html Wed Aug 18 15:06:19 2004 @@ -1,6 +1,7 @@ + LLVM Bytecode File Format
    @@ -26,6 +26,7 @@ Publications
    LLVM Projects
    Current Work
    +LLVM People
    Bug Database
    From lattner at cs.uiuc.edu Wed Aug 18 12:44:04 2004 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Wed, 18 Aug 2004 12:44:04 -0500 Subject: [llvm-commits] CVS: llvm-www/www-index.html Message-ID: <200408181744.MAA07589@apoc.cs.uiuc.edu> Changes in directory llvm-www: www-index.html updated: 1.111 -> 1.112 --- Log message: Add link to developers page --- Diffs of the changes: (+6 -6) Index: llvm-www/www-index.html diff -u llvm-www/www-index.html:1.111 llvm-www/www-index.html:1.112 --- llvm-www/www-index.html:1.111 Fri Aug 13 17:41:20 2004 +++ llvm-www/www-index.html Wed Aug 18 12:43:54 2004 @@ -61,15 +61,15 @@ to do interesting things, even if you only have a semester in a University course.

    -

    LLVM is a product of the LLVM was started by the Lifelong Code Optimization Project, led by Vikram Adve in the Department of Computer Science at the Vikram Adve at the University of Illinois, Urbana-Champaign. Since -our public release, LLVM has grown to include contributions from several -other people! We welcome external contributions, so please send e-mail to +the first public release, LLVM has grown to include contributions from several +other people! We welcome external contributions, +so please send e-mail to llvmdev at cs.uiuc.edu if you are interested in contributing code to the LLVM infrastructure.

    From gaeke at cs.uiuc.edu Wed Aug 18 12:44:28 2004 From: gaeke at cs.uiuc.edu (Brian Gaeke) Date: Wed, 18 Aug 2004 12:44:28 -0500 (CDT) Subject: [llvm-commits] CVS: llvm/lib/Target/SparcV9/SparcV9RegInfo.cpp Message-ID: <200408181744.MAA01589@kain.cs.uiuc.edu> Changes in directory llvm/lib/Target/SparcV9: SparcV9RegInfo.cpp updated: 1.135 -> 1.136 --- Log message: Doxygenify some comments. Clean up cpReg2MemMI and cpMem2RegMI, and doxygenify comments. Get rid of their uses of SETSW, which is a pseudoinstruction. We can't JIT-compile pseudoinstructions at the moment. This was blowing up 252.eon/jit, which has some HUGE stack frames. Reduce the uses of constantFitsInImmedField(). Consolidate some assertions. --- Diffs of the changes: (+88 -98) Index: llvm/lib/Target/SparcV9/SparcV9RegInfo.cpp diff -u llvm/lib/Target/SparcV9/SparcV9RegInfo.cpp:1.135 llvm/lib/Target/SparcV9/SparcV9RegInfo.cpp:1.136 --- llvm/lib/Target/SparcV9/SparcV9RegInfo.cpp:1.135 Mon Aug 16 16:54:30 2004 +++ llvm/lib/Target/SparcV9/SparcV9RegInfo.cpp Wed Aug 18 12:44:14 2004 @@ -744,82 +744,80 @@ mvec.push_back(MI); } -//--------------------------------------------------------------------------- -// Copy from a register to memory (i.e., Store). Register number must -// be the unified register number -//--------------------------------------------------------------------------- - - -void -SparcV9RegInfo::cpReg2MemMI(std::vector& mvec, - unsigned SrcReg, - unsigned PtrReg, - int Offset, int RegType, - int scratchReg) const { - MachineInstr * MI = NULL; - int OffReg = -1; - - // If the Offset will not fit in the signed-immediate field, find an - // unused register to hold the offset value. This takes advantage of - // the fact that all the opcodes used below have the same size immed. field. - // Use the register allocator, PRA, to find an unused reg. at this MI. - // - if (RegType != IntCCRegType) // does not use offset below - if (! target.getInstrInfo()->constantFitsInImmedField(V9::LDXi, Offset)) { -#ifdef CAN_FIND_FREE_REGISTER_TRANSPARENTLY - RegClass* RC = PRA.getRegClassByID(this->getRegClassIDOfRegType(RegType)); - OffReg = PRA.getUnusedUniRegAtMI(RC, RegType, MInst, LVSetBef); -#else - // Default to using register g4 for holding large offsets - OffReg = getUnifiedRegNum(SparcV9RegInfo::IntRegClassID, - SparcV9IntRegClass::g4); -#endif - assert(OffReg >= 0 && "FIXME: cpReg2MemMI cannot find an unused reg."); - mvec.push_back(BuildMI(V9::SETSW, 2).addZImm(Offset).addReg(OffReg)); - } +/// cpReg2MemMI - Generate SparcV9 MachineInstrs to store a register +/// (SrcReg) to memory, at [PtrReg + Offset]. Register numbers must be the +/// unified register numbers. RegType must be the SparcV9 register type +/// of SrcReg. When SrcReg is %ccr, scratchReg must be the +/// number of a free integer register. The newly-generated MachineInstrs +/// are appended to mvec. +/// +void SparcV9RegInfo::cpReg2MemMI(std::vector& mvec, + unsigned SrcReg, unsigned PtrReg, int Offset, + int RegType, int scratchReg) const { + unsigned OffReg = SparcV9::g4; // Use register g4 for holding large offsets + bool useImmediateOffset = true; + + // If the Offset will not fit in the signed-immediate field, we put it in + // register g4. This takes advantage of the fact that all the opcodes + // used below have the same size immed. field. + if (RegType != IntCCRegType + && !target.getInstrInfo()->constantFitsInImmedField(V9::LDXi, Offset)) { + // Put the offset into a register. We could do this in fewer steps, + // in some cases (see CreateSETSWConst()) but we're being lazy. + MachineInstr *MI = BuildMI(V9::SETHI, 2).addZImm(Offset).addMReg(OffReg, + MachineOperand::Def); + MI->getOperand(0).markHi32(); + mvec.push_back(MI); + MI = BuildMI(V9::ORi,3).addMReg(OffReg).addZImm(Offset).addMReg(OffReg, + MachineOperand::Def); + MI->getOperand(1).markLo32(); + mvec.push_back(MI); + MI = BuildMI(V9::SRAi5,3).addMReg(OffReg).addZImm(0).addMReg(OffReg, + MachineOperand::Def); + mvec.push_back(MI); + useImmediateOffset = false; + } + MachineInstr *MI = 0; switch (RegType) { case IntRegType: - if (target.getInstrInfo()->constantFitsInImmedField(V9::STXi, Offset)) + if (useImmediateOffset) MI = BuildMI(V9::STXi,3).addMReg(SrcReg).addMReg(PtrReg).addSImm(Offset); else MI = BuildMI(V9::STXr,3).addMReg(SrcReg).addMReg(PtrReg).addMReg(OffReg); break; case FPSingleRegType: - if (target.getInstrInfo()->constantFitsInImmedField(V9::STFi, Offset)) + if (useImmediateOffset) MI = BuildMI(V9::STFi, 3).addMReg(SrcReg).addMReg(PtrReg).addSImm(Offset); else MI = BuildMI(V9::STFr, 3).addMReg(SrcReg).addMReg(PtrReg).addMReg(OffReg); break; case FPDoubleRegType: - if (target.getInstrInfo()->constantFitsInImmedField(V9::STDFi, Offset)) + if (useImmediateOffset) MI = BuildMI(V9::STDFi,3).addMReg(SrcReg).addMReg(PtrReg).addSImm(Offset); else MI = BuildMI(V9::STDFr,3).addMReg(SrcReg).addMReg(PtrReg).addSImm(OffReg); break; case IntCCRegType: - assert(scratchReg >= 0 && "Need scratch reg to store %ccr to memory"); - assert(getRegType(scratchReg) ==IntRegType && "Invalid scratch reg"); - MI = (BuildMI(V9::RDCCR, 2) - .addMReg(getUnifiedRegNum(SparcV9RegInfo::IntCCRegClassID, - SparcV9IntCCRegClass::ccr)) - .addMReg(scratchReg, MachineOperand::Def)); + assert(scratchReg >= 0 && getRegType(scratchReg) == IntRegType + && "Need a scratch reg of integer type to load or store %ccr"); + MI = BuildMI(V9::RDCCR, 2).addMReg(SparcV9::ccr) + .addMReg(scratchReg, MachineOperand::Def); mvec.push_back(MI); - cpReg2MemMI(mvec, scratchReg, PtrReg, Offset, IntRegType); return; case SpecialRegType: // used only for %fsr itself. case FloatCCRegType: { - unsigned fsrReg = getUnifiedRegNum(SparcV9RegInfo::SpecialRegClassID, - SparcV9SpecialRegClass::fsr); - if (target.getInstrInfo()->constantFitsInImmedField(V9::STXFSRi, Offset)) - MI=BuildMI(V9::STXFSRi,3).addMReg(fsrReg).addMReg(PtrReg).addSImm(Offset); + if (useImmediateOffset) + MI = BuildMI(V9::STXFSRi,3).addMReg(SparcV9::fsr).addMReg(PtrReg) + .addSImm(Offset); else - MI=BuildMI(V9::STXFSRr,3).addMReg(fsrReg).addMReg(PtrReg).addMReg(OffReg); + MI = BuildMI(V9::STXFSRr,3).addMReg(SparcV9::fsr).addMReg(PtrReg) + .addMReg(OffReg); break; } default: @@ -828,45 +826,42 @@ mvec.push_back(MI); } +/// cpMem2RegMI - Generate SparcV9 MachineInstrs to load a register +/// (DestReg) from memory, at [PtrReg + Offset]. Register numbers must be the +/// unified register numbers. RegType must be the SparcV9 register type +/// of DestReg. When DestReg is %ccr, scratchReg must be the +/// number of a free integer register. The newly-generated MachineInstrs +/// are appended to mvec. +/// +void SparcV9RegInfo::cpMem2RegMI(std::vector& mvec, + unsigned PtrReg, int Offset, unsigned DestReg, + int RegType, int scratchReg) const { + unsigned OffReg = SparcV9::g4; // Use register g4 for holding large offsets + bool useImmediateOffset = true; + + // If the Offset will not fit in the signed-immediate field, we put it in + // register g4. This takes advantage of the fact that all the opcodes + // used below have the same size immed. field. + if (RegType != IntCCRegType + && !target.getInstrInfo()->constantFitsInImmedField(V9::LDXi, Offset)) { + MachineInstr *MI = BuildMI(V9::SETHI, 2).addZImm(Offset).addMReg(OffReg, + MachineOperand::Def); + MI->getOperand(0).markHi32(); + mvec.push_back(MI); + MI = BuildMI(V9::ORi,3).addMReg(OffReg).addZImm(Offset).addMReg(OffReg, + MachineOperand::Def); + MI->getOperand(1).markLo32(); + mvec.push_back(MI); + MI = BuildMI(V9::SRAi5,3).addMReg(OffReg).addZImm(0).addMReg(OffReg, + MachineOperand::Def); + mvec.push_back(MI); + useImmediateOffset = false; + } -//--------------------------------------------------------------------------- -// Copy from memory to a reg (i.e., Load) Register number must be the unified -// register number -//--------------------------------------------------------------------------- - - -void -SparcV9RegInfo::cpMem2RegMI(std::vector& mvec, - unsigned PtrReg, - int Offset, - unsigned DestReg, - int RegType, - int scratchReg) const { - MachineInstr * MI = NULL; - int OffReg = -1; - - // If the Offset will not fit in the signed-immediate field, find an - // unused register to hold the offset value. This takes advantage of - // the fact that all the opcodes used below have the same size immed. field. - // Use the register allocator, PRA, to find an unused reg. at this MI. - // - if (RegType != IntCCRegType) // does not use offset below - if (! target.getInstrInfo()->constantFitsInImmedField(V9::LDXi, Offset)) { -#ifdef CAN_FIND_FREE_REGISTER_TRANSPARENTLY - RegClass* RC = PRA.getRegClassByID(this->getRegClassIDOfRegType(RegType)); - OffReg = PRA.getUnusedUniRegAtMI(RC, RegType, MInst, LVSetBef); -#else - // Default to using register g4 for holding large offsets - OffReg = getUnifiedRegNum(SparcV9RegInfo::IntRegClassID, - SparcV9IntRegClass::g4); -#endif - assert(OffReg >= 0 && "FIXME: cpReg2MemMI cannot find an unused reg."); - mvec.push_back(BuildMI(V9::SETSW, 2).addZImm(Offset).addReg(OffReg)); - } - + MachineInstr *MI = 0; switch (RegType) { case IntRegType: - if (target.getInstrInfo()->constantFitsInImmedField(V9::LDXi, Offset)) + if (useImmediateOffset) MI = BuildMI(V9::LDXi, 3).addMReg(PtrReg).addSImm(Offset) .addMReg(DestReg, MachineOperand::Def); else @@ -875,7 +870,7 @@ break; case FPSingleRegType: - if (target.getInstrInfo()->constantFitsInImmedField(V9::LDFi, Offset)) + if (useImmediateOffset) MI = BuildMI(V9::LDFi, 3).addMReg(PtrReg).addSImm(Offset) .addMReg(DestReg, MachineOperand::Def); else @@ -884,7 +879,7 @@ break; case FPDoubleRegType: - if (target.getInstrInfo()->constantFitsInImmedField(V9::LDDFi, Offset)) + if (useImmediateOffset) MI= BuildMI(V9::LDDFi, 3).addMReg(PtrReg).addSImm(Offset) .addMReg(DestReg, MachineOperand::Def); else @@ -893,26 +888,21 @@ break; case IntCCRegType: - assert(scratchReg >= 0 && "Need scratch reg to load %ccr from memory"); - assert(getRegType(scratchReg) ==IntRegType && "Invalid scratch reg"); + assert(scratchReg >= 0 && getRegType(scratchReg) == IntRegType + && "Need a scratch reg of integer type to load or store %ccr"); cpMem2RegMI(mvec, PtrReg, Offset, scratchReg, IntRegType); - MI = (BuildMI(V9::WRCCRr, 3) - .addMReg(scratchReg) - .addMReg(SparcV9IntRegClass::g0) - .addMReg(getUnifiedRegNum(SparcV9RegInfo::IntCCRegClassID, - SparcV9IntCCRegClass::ccr), MachineOperand::Def)); + MI = BuildMI(V9::WRCCRr, 3).addMReg(scratchReg).addMReg(SparcV9::g0) + .addMReg(SparcV9::ccr, MachineOperand::Def); break; case SpecialRegType: // used only for %fsr itself case FloatCCRegType: { - unsigned fsrRegNum = getUnifiedRegNum(SparcV9RegInfo::SpecialRegClassID, - SparcV9SpecialRegClass::fsr); - if (target.getInstrInfo()->constantFitsInImmedField(V9::LDXFSRi, Offset)) + if (useImmediateOffset) MI = BuildMI(V9::LDXFSRi, 3).addMReg(PtrReg).addSImm(Offset) - .addMReg(fsrRegNum, MachineOperand::UseAndDef); + .addMReg(SparcV9::fsr, MachineOperand::Def); else MI = BuildMI(V9::LDXFSRr, 3).addMReg(PtrReg).addMReg(OffReg) - .addMReg(fsrRegNum, MachineOperand::UseAndDef); + .addMReg(SparcV9::fsr, MachineOperand::Def); break; } default: From gaeke at cs.uiuc.edu Wed Aug 18 12:44:28 2004 From: gaeke at cs.uiuc.edu (Brian Gaeke) Date: Wed, 18 Aug 2004 12:44:28 -0500 (CDT) Subject: [llvm-commits] CVS: llvm/lib/Target/SparcV9/SparcV9Instr.def SparcV9InstrInfo.h Message-ID: <200408181744.MAA01593@kain.cs.uiuc.edu> Changes in directory llvm/lib/Target/SparcV9: SparcV9Instr.def updated: 1.27 -> 1.28 SparcV9InstrInfo.h updated: 1.9 -> 1.10 --- Log message: The SparcV9 target no longer uses any pseudoinstructions (SETSW, SETUW, SETX) or M_PSEUDO_FLAG. --- Diffs of the changes: (+1 -9) Index: llvm/lib/Target/SparcV9/SparcV9Instr.def diff -u llvm/lib/Target/SparcV9/SparcV9Instr.def:1.27 llvm/lib/Target/SparcV9/SparcV9Instr.def:1.28 --- llvm/lib/Target/SparcV9/SparcV9Instr.def:1.27 Thu Jul 1 23:57:37 2004 +++ llvm/lib/Target/SparcV9/SparcV9Instr.def Wed Aug 18 12:44:16 2004 @@ -49,13 +49,6 @@ I(NOP, "nop", 0, -1, 0, false, 0, 1, SPARC_NONE, M_NOP_FLAG) -// Synthetic SPARC assembly opcodes for setting a register to a constant. -// Max immediate constant should be ignored for both these instructions. -// Use a latency > 1 since this may generate as many as 3 instructions. -I(SETSW, "setsw", 2, 1, 0, true , 0, 2, SPARC_IEUN, M_PSEUDO_FLAG ) -I(SETUW, "setuw", 2, 1, 0, false, 0, 2, SPARC_IEUN, M_PSEUDO_FLAG ) -I(SETX, "setx", 3, 2, 0, true, 0, 2, SPARC_IEUN, M_PSEUDO_FLAG ) - // Set high-order bits of register and clear low-order bits I(SETHI, "sethi", 2, 1, B22, false, 0, 1, SPARC_IEUN, 0) Index: llvm/lib/Target/SparcV9/SparcV9InstrInfo.h diff -u llvm/lib/Target/SparcV9/SparcV9InstrInfo.h:1.9 llvm/lib/Target/SparcV9/SparcV9InstrInfo.h:1.10 --- llvm/lib/Target/SparcV9/SparcV9InstrInfo.h:1.9 Wed Aug 4 02:29:28 2004 +++ llvm/lib/Target/SparcV9/SparcV9InstrInfo.h Wed Aug 18 12:44:16 2004 @@ -50,8 +50,7 @@ // last store opcode assert(! this->isStore((MachineOpCode) V9::STXFSRi + 1)); - if (opCode == V9::SETSW || opCode == V9::SETUW || - opCode == V9::SETX || opCode == V9::SETHI) + if (opCode == V9::SETHI) return 0; if (opCode >= V9::STBr && opCode <= V9::STXFSRi) return 2; From gaeke at cs.uiuc.edu Wed Aug 18 12:44:29 2004 From: gaeke at cs.uiuc.edu (Brian Gaeke) Date: Wed, 18 Aug 2004 12:44:29 -0500 (CDT) Subject: [llvm-commits] CVS: llvm/include/llvm/Target/TargetInstrInfo.h Message-ID: <200408181744.MAA01602@kain.cs.uiuc.edu> Changes in directory llvm/include/llvm/Target: TargetInstrInfo.h updated: 1.67 -> 1.68 --- Log message: M_PSEUDO_FLAG is no longer used. Get rid of it and its accessor. --- Diffs of the changes: (+0 -4) Index: llvm/include/llvm/Target/TargetInstrInfo.h diff -u llvm/include/llvm/Target/TargetInstrInfo.h:1.67 llvm/include/llvm/Target/TargetInstrInfo.h:1.68 --- llvm/include/llvm/Target/TargetInstrInfo.h:1.67 Wed Aug 4 03:06:30 2004 +++ llvm/include/llvm/Target/TargetInstrInfo.h Wed Aug 18 12:44:17 2004 @@ -52,7 +52,6 @@ const unsigned M_LOAD_FLAG = 1 << 10; const unsigned M_STORE_FLAG = 1 << 12; const unsigned M_DUMMY_PHI_FLAG = 1 << 13; -const unsigned M_PSEUDO_FLAG = 1 << 14; // Pseudo instruction // 3-addr instructions which really work like 2-addr ones, eg. X86 add/sub const unsigned M_2_ADDR_FLAG = 1 << 15; @@ -137,9 +136,6 @@ return get(Opcode).Flags & M_RET_FLAG; } - bool isPseudoInstr(MachineOpCode Opcode) const { - return get(Opcode).Flags & M_PSEUDO_FLAG; - } bool isTwoAddrInstr(MachineOpCode Opcode) const { return get(Opcode).Flags & M_2_ADDR_FLAG; } From gaeke at cs.uiuc.edu Wed Aug 18 12:44:28 2004 From: gaeke at cs.uiuc.edu (Brian Gaeke) Date: Wed, 18 Aug 2004 12:44:28 -0500 (CDT) Subject: [llvm-commits] CVS: llvm/lib/Target/SparcV9/SparcV9BurgISel.cpp Message-ID: <200408181744.MAA01596@kain.cs.uiuc.edu> Changes in directory llvm/lib/Target/SparcV9: SparcV9BurgISel.cpp updated: 1.6 -> 1.7 --- Log message: The Create*Const methods don't need to pass around a TargetMachine reference. Other minor cleanups. --- Diffs of the changes: (+18 -20) Index: llvm/lib/Target/SparcV9/SparcV9BurgISel.cpp diff -u llvm/lib/Target/SparcV9/SparcV9BurgISel.cpp:1.6 llvm/lib/Target/SparcV9/SparcV9BurgISel.cpp:1.7 --- llvm/lib/Target/SparcV9/SparcV9BurgISel.cpp:1.6 Mon Aug 16 16:54:30 2004 +++ llvm/lib/Target/SparcV9/SparcV9BurgISel.cpp Wed Aug 18 12:44:15 2004 @@ -606,7 +606,7 @@ /// (2) isSigned = true and C is a small negative signed value, i.e., /// high bits are 1, and the remaining bits fit in simm13(OR). static inline void -CreateSETUWConst(const TargetMachine& target, uint32_t C, +CreateSETUWConst(uint32_t C, Instruction* dest, std::vector& mvec, bool isSigned = false) { MachineInstr *miSETHI = NULL, *miOR = NULL; @@ -636,7 +636,7 @@ } else { // unsigned or small signed value that fits in simm13 field of OR assert(smallNegValue || (C & ~MAXSIMM) == 0); - miOR = BuildMI(V9::ORi, 3).addMReg(target.getRegInfo()->getZeroRegNum()) + miOR = BuildMI(V9::ORi, 3).addMReg(SparcV9::g0) .addSImm(sC).addRegDef(dest); } mvec.push_back(miOR); @@ -652,10 +652,10 @@ /// (1) SRA is not needed for positive or small negative values. /// static inline void -CreateSETSWConst(const TargetMachine& target, int32_t C, +CreateSETSWConst(int32_t C, Instruction* dest, std::vector& mvec) { // Set the low 32 bits of dest - CreateSETUWConst(target, (uint32_t) C, dest, mvec, /*isSigned*/true); + CreateSETUWConst((uint32_t) C, dest, mvec, /*isSigned*/true); // Sign-extend to the high 32 bits if needed. // NOTE: The value C = 0x80000000 is bad: -C == C and so -C is < MAXSIMM @@ -670,7 +670,7 @@ /// 32 bit word. /// static inline void -CreateSETXConst(const TargetMachine& target, uint64_t C, +CreateSETXConst(uint64_t C, Instruction* tmpReg, Instruction* dest, std::vector& mvec) { assert(C > (unsigned int) ~0 && "Use SETUW/SETSW for 32-bit values!"); @@ -678,14 +678,14 @@ MachineInstr* MI; // Code to set the upper 32 bits of the value in register `tmpReg' - CreateSETUWConst(target, (C >> 32), tmpReg, mvec); + CreateSETUWConst((C >> 32), tmpReg, mvec); // Shift tmpReg left by 32 bits mvec.push_back(BuildMI(V9::SLLXi6, 3).addReg(tmpReg).addZImm(32) .addRegDef(tmpReg)); // Code to set the low 32 bits of the value in register `dest' - CreateSETUWConst(target, C, dest, mvec); + CreateSETUWConst(C, dest, mvec); // dest = OR(tmpReg, dest) mvec.push_back(BuildMI(V9::ORr,3).addReg(dest).addReg(tmpReg).addRegDef(dest)); @@ -695,7 +695,7 @@ /// the register `dest'. /// static inline void -CreateSETUWLabel(const TargetMachine& target, Value* val, +CreateSETUWLabel(Value* val, Instruction* dest, std::vector& mvec) { MachineInstr* MI; @@ -714,7 +714,7 @@ /// register `dest'. /// static inline void -CreateSETXLabel(const TargetMachine& target, Value* val, Instruction* tmpReg, +CreateSETXLabel(Value* val, Instruction* tmpReg, Instruction* dest, std::vector& mvec) { assert(isa(val) && "I only know about constant values and global addresses"); @@ -750,21 +750,20 @@ /// them all). /// static inline void -CreateUIntSetInstruction(const TargetMachine& target, - uint64_t C, Instruction* dest, +CreateUIntSetInstruction(uint64_t C, Instruction* dest, std::vector& mvec, MachineCodeForInstruction& mcfi) { static const uint64_t lo32 = (uint32_t) ~0; if (C <= lo32) // High 32 bits are 0. Set low 32 bits. - CreateSETUWConst(target, (uint32_t) C, dest, mvec); + CreateSETUWConst((uint32_t) C, dest, mvec); else if ((C & ~lo32) == ~lo32 && (C & (1U << 31))) { // All high 33 (not 32) bits are 1s: sign-extension will take care // of high 32 bits, so use the sequence for signed int - CreateSETSWConst(target, (int32_t) C, dest, mvec); + CreateSETSWConst((int32_t) C, dest, mvec); } else if (C > lo32) { // C does not fit in 32 bits TmpInstruction* tmpReg = new TmpInstruction(mcfi, Type::IntTy); - CreateSETXConst(target, C, tmpReg, dest, mvec); + CreateSETXConst(C, tmpReg, dest, mvec); } } @@ -772,11 +771,10 @@ /// register `dest'. Really the same as CreateUIntSetInstruction. /// static inline void -CreateIntSetInstruction(const TargetMachine& target, - int64_t C, Instruction* dest, +CreateIntSetInstruction(int64_t C, Instruction* dest, std::vector& mvec, MachineCodeForInstruction& mcfi) { - CreateUIntSetInstruction(target, (uint64_t) C, dest, mvec, mcfi); + CreateUIntSetInstruction((uint64_t) C, dest, mvec, mcfi); } /// MaxConstantsTableTy - Table mapping LLVM opcodes to the max. immediate @@ -1069,7 +1067,7 @@ if (isa(val)) { TmpInstruction* tmpReg = new TmpInstruction(mcfi, PointerType::get(val->getType()), val); - CreateSETXLabel(target, val, tmpReg, dest, mvec); + CreateSETXLabel(val, tmpReg, dest, mvec); return; } @@ -1077,9 +1075,9 @@ uint64_t C = ConvertConstantToIntType(target, val, dest->getType(), isValid); if (isValid) { if (dest->getType()->isSigned()) - CreateUIntSetInstruction(target, C, dest, mvec, mcfi); + CreateUIntSetInstruction(C, dest, mvec, mcfi); else - CreateIntSetInstruction(target, (int64_t) C, dest, mvec, mcfi); + CreateIntSetInstruction((int64_t) C, dest, mvec, mcfi); } else { // Make an instruction sequence to load the constant, viz: From gaeke at cs.uiuc.edu Wed Aug 18 12:44:29 2004 From: gaeke at cs.uiuc.edu (Brian Gaeke) Date: Wed, 18 Aug 2004 12:44:29 -0500 (CDT) Subject: [llvm-commits] CVS: llvm/lib/Target/SparcV9/RegAlloc/PhyRegAlloc.cpp Message-ID: <200408181744.MAA01599@kain.cs.uiuc.edu> Changes in directory llvm/lib/Target/SparcV9/RegAlloc: PhyRegAlloc.cpp updated: 1.160 -> 1.161 --- Log message: The SparcV9 target no longer uses any pseudoinstructions (SETSW, SETUW, SETX) or M_PSEUDO_FLAG. --- Diffs of the changes: (+0 -9) Index: llvm/lib/Target/SparcV9/RegAlloc/PhyRegAlloc.cpp diff -u llvm/lib/Target/SparcV9/RegAlloc/PhyRegAlloc.cpp:1.160 llvm/lib/Target/SparcV9/RegAlloc/PhyRegAlloc.cpp:1.161 --- llvm/lib/Target/SparcV9/RegAlloc/PhyRegAlloc.cpp:1.160 Mon Aug 16 16:54:32 2004 +++ llvm/lib/Target/SparcV9/RegAlloc/PhyRegAlloc.cpp Wed Aug 18 12:44:16 2004 @@ -256,21 +256,12 @@ LiveRange *LR = LRI->getLiveRangeForValue(*OpI); if (LR) LR->addSpillCost(BBLoopDepthCost); } - - // Mark all operands of pseudo-instructions as interfering with one - // another. This must be done because pseudo-instructions may be - // expanded to multiple instructions by the assembler, so all the - // operands must get distinct registers. - if (TM.getInstrInfo()->isPseudoInstr(MInst->getOpcode())) - addInterf4PseudoInstr(MInst); - // Also add interference for any implicit definitions in a machine // instr (currently, only calls have this). unsigned NumOfImpRefs = MInst->getNumImplicitRefs(); for (unsigned z=0; z < NumOfImpRefs; z++) if (MInst->getImplicitOp(z).isDef()) addInterference( MInst->getImplicitRef(z), &LVSetAI, isCallInst ); - } // for all machine instructions in BB } // for all BBs in function From lattner at cs.uiuc.edu Wed Aug 18 13:13:30 2004 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Wed, 18 Aug 2004 13:13:30 -0500 Subject: [llvm-commits] CVS: llvm/include/llvm/CodeGen/MachineFunction.h Message-ID: <200408181813.NAA29020@apoc.cs.uiuc.edu> Changes in directory llvm/include/llvm/CodeGen: MachineFunction.h updated: 1.40 -> 1.41 --- Log message: All targets are now allowed to have their own MachineFunctionInfo objects, also, make getInfo do some checking and cast to the appropriate concrete type. --- Diffs of the changes: (+24 -12) Index: llvm/include/llvm/CodeGen/MachineFunction.h diff -u llvm/include/llvm/CodeGen/MachineFunction.h:1.40 llvm/include/llvm/CodeGen/MachineFunction.h:1.41 --- llvm/include/llvm/CodeGen/MachineFunction.h:1.40 Tue Aug 17 12:52:36 2004 +++ llvm/include/llvm/CodeGen/MachineFunction.h Wed Aug 18 13:13:16 2004 @@ -23,6 +23,12 @@ namespace llvm { +class Function; +class TargetMachine; +class SSARegMap; +class MachineFrameInfo; +class MachineConstantPool; + // ilist_traits template <> class ilist_traits { @@ -58,15 +64,13 @@ ilist_iterator last); }; - -class Function; -class TargetMachine; -class SSARegMap; -class MachineFrameInfo; -class MachineConstantPool; -// MachineFunctionInfoBase - This is a gross SparcV9 hack -struct MachineFunctionInfoBase { virtual ~MachineFunctionInfoBase() {}; }; -class MachineFunctionInfo; +/// MachineFunctionInfo - This class can be derived from and used by targets to +/// hold private target-specific information for each MachineFunction. Objects +/// of type are accessed/created with MF::getInfo and destroyed when the +/// MachineFunction is destroyed. +struct MachineFunctionInfo { + virtual ~MachineFunctionInfo() {}; +}; class MachineFunction : private Annotation { const Function *Fn; @@ -78,8 +82,9 @@ // Keeping track of mapping from SSA values to registers SSARegMap *SSARegMapping; - // Used to keep track of frame and constant area information for SparcV9 BE. - mutable MachineFunctionInfoBase *MFInfo; + // Used to keep track of target-specific per-machine function information for + // the target implementation. + MachineFunctionInfo *MFInfo; // Keep track of objects allocated on the stack. MachineFrameInfo *FrameInfo; @@ -124,7 +129,14 @@ /// MachineFunctionInfo - Keep track of various per-function pieces of /// information for the sparc backend. /// - MachineFunctionInfo *getInfo() const; + template + Ty *getInfo() { + if (!MFInfo) MFInfo = new Ty(*this); + + assert((void*)dynamic_cast(MFInfo) == (void*)MFInfo && + "Invalid concrete type or multiple inheritence for getInfo"); + return static_cast(MFInfo); + } /// getBlockNumbered - MachineBasicBlocks are automatically numbered when they /// are inserted into the machine function. The block number for a machine From lattner at cs.uiuc.edu Wed Aug 18 13:13:47 2004 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Wed, 18 Aug 2004 13:13:47 -0500 Subject: [llvm-commits] CVS: llvm/lib/Target/SparcV9/MachineCodeForInstruction.cpp MachineFunctionInfo.cpp MachineFunctionInfo.h SparcV9BurgISel.cpp SparcV9FrameInfo.cpp SparcV9PrologEpilogInserter.cpp SparcV9RegInfo.cpp SparcV9StackSlots.cpp SparcV9TargetMachine.cpp Message-ID: <200408181813.NAA29302@apoc.cs.uiuc.edu> Changes in directory llvm/lib/Target/SparcV9: MachineCodeForInstruction.cpp updated: 1.1 -> 1.2 MachineFunctionInfo.cpp updated: 1.1 -> 1.2 MachineFunctionInfo.h updated: 1.7 -> 1.8 SparcV9BurgISel.cpp updated: 1.7 -> 1.8 SparcV9FrameInfo.cpp updated: 1.6 -> 1.7 SparcV9PrologEpilogInserter.cpp updated: 1.46 -> 1.47 SparcV9RegInfo.cpp updated: 1.136 -> 1.137 SparcV9StackSlots.cpp updated: 1.12 -> 1.13 SparcV9TargetMachine.cpp updated: 1.120 -> 1.121 --- Log message: Convert to the new MachineFunctionInfo interface --- Diffs of the changes: (+28 -37) Index: llvm/lib/Target/SparcV9/MachineCodeForInstruction.cpp diff -u llvm/lib/Target/SparcV9/MachineCodeForInstruction.cpp:1.1 llvm/lib/Target/SparcV9/MachineCodeForInstruction.cpp:1.2 --- llvm/lib/Target/SparcV9/MachineCodeForInstruction.cpp:1.1 Mon Aug 16 17:38:02 2004 +++ llvm/lib/Target/SparcV9/MachineCodeForInstruction.cpp Wed Aug 18 13:13:34 2004 @@ -35,11 +35,11 @@ MachineCodeForInstruction &MachineCodeForInstruction::get(const Instruction *I){ MachineFunction &MF = MachineFunction::get(I->getParent()->getParent()); - return MF.getInfo()->MCFIEntries[I]; + return MF.getInfo()->MCFIEntries[I]; } void MachineCodeForInstruction::destroy(const Instruction *I) { MachineFunction &MF = MachineFunction::get(I->getParent()->getParent()); - MF.getInfo()->MCFIEntries.erase(I); + MF.getInfo()->MCFIEntries.erase(I); } void Index: llvm/lib/Target/SparcV9/MachineFunctionInfo.cpp diff -u llvm/lib/Target/SparcV9/MachineFunctionInfo.cpp:1.1 llvm/lib/Target/SparcV9/MachineFunctionInfo.cpp:1.2 --- llvm/lib/Target/SparcV9/MachineFunctionInfo.cpp:1.1 Mon Aug 16 17:36:54 2004 +++ llvm/lib/Target/SparcV9/MachineFunctionInfo.cpp Wed Aug 18 13:13:34 2004 @@ -1,4 +1,4 @@ -//===-- MachineFunctionInfo.cpp -------------------------------------------===// +//===-- SparcV9FunctionInfo.cpp -------------------------------------------===// // // The LLVM Compiler Infrastructure // @@ -20,15 +20,6 @@ #include "llvm/Target/TargetFrameInfo.h" using namespace llvm; -MachineFunctionInfo *MachineFunction::getInfo() const { - if (!MFInfo) { - MFInfo = new MachineFunctionInfo(*const_cast(this)); - } - return static_cast(MFInfo); -} - - - static unsigned ComputeMaxOptionalArgsSize(const TargetMachine& target, const Function *F, unsigned &maxOptionalNumArgs) @@ -78,7 +69,7 @@ } -void MachineFunctionInfo::CalculateArgSize() { +void SparcV9FunctionInfo::CalculateArgSize() { maxOptionalArgsSize = ComputeMaxOptionalArgsSize(MF.getTarget(), MF.getFunction(), maxOptionalNumArgs); @@ -86,7 +77,7 @@ } int -MachineFunctionInfo::computeOffsetforLocalVar(const Value* val, +SparcV9FunctionInfo::computeOffsetforLocalVar(const Value* val, unsigned &getPaddedSize, unsigned sizeToUse) { @@ -112,7 +103,7 @@ } -int MachineFunctionInfo::allocateLocalVar(const Value* val, +int SparcV9FunctionInfo::allocateLocalVar(const Value* val, unsigned sizeToUse) { assert(! automaticVarsAreaFrozen && "Size of auto vars area has been used to compute an offset so " @@ -132,7 +123,7 @@ } int -MachineFunctionInfo::allocateSpilledValue(const Type* type) +SparcV9FunctionInfo::allocateSpilledValue(const Type* type) { assert(! spillsAreaFrozen && "Size of reg spills area has been used to compute an offset so " @@ -156,7 +147,7 @@ } int -MachineFunctionInfo::pushTempValue(unsigned size) +SparcV9FunctionInfo::pushTempValue(unsigned size) { unsigned align = SizeToAlignment(size, MF.getTarget()); @@ -175,6 +166,6 @@ return aligned; } -void MachineFunctionInfo::popAllTempValues() { +void SparcV9FunctionInfo::popAllTempValues() { resetTmpAreaSize(); // clear tmp area to reuse } Index: llvm/lib/Target/SparcV9/MachineFunctionInfo.h diff -u llvm/lib/Target/SparcV9/MachineFunctionInfo.h:1.7 llvm/lib/Target/SparcV9/MachineFunctionInfo.h:1.8 --- llvm/lib/Target/SparcV9/MachineFunctionInfo.h:1.7 Mon Aug 16 17:37:18 2004 +++ llvm/lib/Target/SparcV9/MachineFunctionInfo.h Wed Aug 18 13:13:34 2004 @@ -1,4 +1,4 @@ -//===-- MachineFunctionInfo.h -----------------------------------*- C++ -*-===// +//===-- SparcV9FunctionInfo.h -----------------------------------*- C++ -*-===// // // The LLVM Compiler Infrastructure // @@ -29,7 +29,7 @@ class Constant; class Type; -class MachineFunctionInfo : public MachineFunctionInfoBase { +class SparcV9FunctionInfo : public MachineFunctionInfo { hash_set constantsForConstPool; hash_map offsets; @@ -48,7 +48,7 @@ public: hash_map MCFIEntries; - MachineFunctionInfo(MachineFunction &mf) : MF(mf) { + SparcV9FunctionInfo(MachineFunction &mf) : MF(mf) { staticStackSize = automaticVarsSize = regSpillsSize = 0; maxOptionalArgsSize = maxOptionalNumArgs = currentTmpValuesSize = 0; maxTmpValuesSize = 0; Index: llvm/lib/Target/SparcV9/SparcV9BurgISel.cpp diff -u llvm/lib/Target/SparcV9/SparcV9BurgISel.cpp:1.7 llvm/lib/Target/SparcV9/SparcV9BurgISel.cpp:1.8 --- llvm/lib/Target/SparcV9/SparcV9BurgISel.cpp:1.7 Wed Aug 18 12:44:15 2004 +++ llvm/lib/Target/SparcV9/SparcV9BurgISel.cpp Wed Aug 18 13:13:34 2004 @@ -1149,7 +1149,7 @@ // FIXME: For now, we allocate permanent space because the stack frame // manager does not allow locals to be allocated (e.g., for alloca) after // a temp is allocated! - int offset = MachineFunction::get(F).getInfo()->allocateLocalVar(val); + int offset = MachineFunction::get(F).getInfo()->allocateLocalVar(val); unsigned FPReg = target.getRegInfo()->getFramePointer(); @@ -1248,7 +1248,7 @@ && "Dest type must be float/double"); // Get a stack slot to use for the copy - int offset = MachineFunction::get(F).getInfo()->allocateLocalVar(val); + int offset = MachineFunction::get(F).getInfo()->allocateLocalVar(val); // Get the size of the source value being copied. size_t srcSize = target.getTargetData().getTypeSize(val->getType()); @@ -2568,7 +2568,7 @@ // You've gotta love having only 13 bits for constant offset values :-|. // unsigned paddedSize; - int offsetFromFP = mcInfo.getInfo()->computeOffsetforLocalVar(result, + int offsetFromFP = mcInfo.getInfo()->computeOffsetforLocalVar(result, paddedSize, tsize * numElements); @@ -2581,7 +2581,7 @@ } // else offset fits in immediate field so go ahead and allocate it. - offsetFromFP = mcInfo.getInfo()->allocateLocalVar(result, tsize *numElements); + offsetFromFP = mcInfo.getInfo()->allocateLocalVar(result, tsize *numElements); // Create a temporary Value to hold the constant offset. // This is needed because it may not fit in the immediate field. @@ -3924,8 +3924,8 @@ // allocated (e.g., for alloca) after a temp is // allocated! // - // int tmpOffset = MF.getInfo()->pushTempValue(argSize); - int tmpOffset = MF.getInfo()->allocateLocalVar(argVReg); + // int tmpOffset = MF.getInfo()->pushTempValue(argSize); + int tmpOffset = MF.getInfo()->allocateLocalVar(argVReg); // Generate the store from FP reg to stack unsigned StoreOpcode = ChooseStoreInstruction(argType); @@ -4083,7 +4083,7 @@ if (isa(callee)) callMI->addImplicitRef(retAddrReg, /*isDef*/ true); - MF.getInfo()->popAllTempValues(); // free temps used for this inst + MF.getInfo()->popAllTempValues(); // free temps used for this inst } break; Index: llvm/lib/Target/SparcV9/SparcV9FrameInfo.cpp diff -u llvm/lib/Target/SparcV9/SparcV9FrameInfo.cpp:1.6 llvm/lib/Target/SparcV9/SparcV9FrameInfo.cpp:1.7 --- llvm/lib/Target/SparcV9/SparcV9FrameInfo.cpp:1.6 Mon Aug 16 16:54:30 2004 +++ llvm/lib/Target/SparcV9/SparcV9FrameInfo.cpp Wed Aug 18 13:13:34 2004 @@ -22,15 +22,15 @@ SparcV9FrameInfo::getRegSpillAreaOffset(MachineFunction& mcInfo, bool& pos) const { // ensure no more auto vars are added - mcInfo.getInfo()->freezeAutomaticVarsArea(); + mcInfo.getInfo()->freezeAutomaticVarsArea(); pos = false; // static stack area grows downwards - unsigned autoVarsSize = mcInfo.getInfo()->getAutomaticVarsSize(); + unsigned autoVarsSize = mcInfo.getInfo()->getAutomaticVarsSize(); return StaticAreaOffsetFromFP - autoVarsSize; } int SparcV9FrameInfo::getTmpAreaOffset(MachineFunction& mcInfo, bool& pos) const { - MachineFunctionInfo *MFI = mcInfo.getInfo(); + SparcV9FunctionInfo *MFI = mcInfo.getInfo(); MFI->freezeAutomaticVarsArea(); // ensure no more auto vars are added MFI->freezeSpillsArea(); // ensure no more spill slots are added @@ -48,7 +48,7 @@ // during calls and traps, so they are shifted downwards on each // dynamic-size alloca. pos = false; - unsigned optArgsSize = mcInfo.getInfo()->getMaxOptionalArgsSize(); + unsigned optArgsSize = mcInfo.getInfo()->getMaxOptionalArgsSize(); if (int extra = optArgsSize % 16) optArgsSize += (16 - extra); int offset = optArgsSize + FirstOptionalOutgoingArgOffsetFromSP; Index: llvm/lib/Target/SparcV9/SparcV9PrologEpilogInserter.cpp diff -u llvm/lib/Target/SparcV9/SparcV9PrologEpilogInserter.cpp:1.46 llvm/lib/Target/SparcV9/SparcV9PrologEpilogInserter.cpp:1.47 --- llvm/lib/Target/SparcV9/SparcV9PrologEpilogInserter.cpp:1.46 Mon Aug 16 16:54:30 2004 +++ llvm/lib/Target/SparcV9/SparcV9PrologEpilogInserter.cpp Wed Aug 18 13:13:34 2004 @@ -36,7 +36,7 @@ const char *getPassName() const { return "SparcV9 Prolog/Epilog Inserter"; } bool runOnMachineFunction(MachineFunction &F) { - if (!F.getInfo()->isCompiledAsLeafMethod()) { + if (!F.getInfo()->isCompiledAsLeafMethod()) { InsertPrologCode(F); InsertEpilogCode(F); } @@ -51,7 +51,7 @@ static unsigned getStaticStackSize (MachineFunction &MF) { const TargetFrameInfo& frameInfo = *MF.getTarget().getFrameInfo(); - unsigned staticStackSize = MF.getInfo()->getStaticStackSize(); + unsigned staticStackSize = MF.getInfo()->getStaticStackSize(); if (staticStackSize < (unsigned)SparcV9FrameInfo::MinStackFrameSize) staticStackSize = SparcV9FrameInfo::MinStackFrameSize; if (unsigned padsz = staticStackSize % Index: llvm/lib/Target/SparcV9/SparcV9RegInfo.cpp diff -u llvm/lib/Target/SparcV9/SparcV9RegInfo.cpp:1.136 llvm/lib/Target/SparcV9/SparcV9RegInfo.cpp:1.137 --- llvm/lib/Target/SparcV9/SparcV9RegInfo.cpp:1.136 Wed Aug 18 12:44:14 2004 +++ llvm/lib/Target/SparcV9/SparcV9RegInfo.cpp Wed Aug 18 13:13:34 2004 @@ -466,7 +466,7 @@ regClassIDOfArgReg == IntRegClassID && "This should only be an Int register for an FP argument"); - int TmpOff = MachineFunction::get(Meth).getInfo()->pushTempValue( + int TmpOff = MachineFunction::get(Meth).getInfo()->pushTempValue( getSpilledRegSize(regType)); cpReg2MemMI(InstrnsBefore, UniArgReg, getFramePointer(), TmpOff, IntRegType); Index: llvm/lib/Target/SparcV9/SparcV9StackSlots.cpp diff -u llvm/lib/Target/SparcV9/SparcV9StackSlots.cpp:1.12 llvm/lib/Target/SparcV9/SparcV9StackSlots.cpp:1.13 --- llvm/lib/Target/SparcV9/SparcV9StackSlots.cpp:1.12 Mon Aug 16 16:54:30 2004 +++ llvm/lib/Target/SparcV9/SparcV9StackSlots.cpp Wed Aug 18 13:13:34 2004 @@ -40,7 +40,7 @@ unsigned Size = Target.getTargetData().getTypeSize(PtrInt); Value *V = Constant::getNullValue(Type::IntTy); - MF.getInfo()->allocateLocalVar(V, 2*Size); + MF.getInfo()->allocateLocalVar(V, 2*Size); return true; } }; Index: llvm/lib/Target/SparcV9/SparcV9TargetMachine.cpp diff -u llvm/lib/Target/SparcV9/SparcV9TargetMachine.cpp:1.120 llvm/lib/Target/SparcV9/SparcV9TargetMachine.cpp:1.121 --- llvm/lib/Target/SparcV9/SparcV9TargetMachine.cpp:1.120 Mon Aug 16 16:54:30 2004 +++ llvm/lib/Target/SparcV9/SparcV9TargetMachine.cpp Wed Aug 18 13:13:34 2004 @@ -98,7 +98,7 @@ } bool runOnFunction(Function &F) { - MachineFunction::construct(&F, Target).getInfo()->CalculateArgSize(); + MachineFunction::construct(&F, Target).getInfo()->CalculateArgSize(); return false; } }; From lattner at cs.uiuc.edu Wed Aug 18 13:13:48 2004 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Wed, 18 Aug 2004 13:13:48 -0500 Subject: [llvm-commits] CVS: llvm/lib/Target/SparcV9/RegAlloc/PhyRegAlloc.cpp Message-ID: <200408181813.NAA29308@apoc.cs.uiuc.edu> Changes in directory llvm/lib/Target/SparcV9/RegAlloc: PhyRegAlloc.cpp updated: 1.161 -> 1.162 --- Log message: Convert to the new MachineFunctionInfo interface --- Diffs of the changes: (+6 -6) Index: llvm/lib/Target/SparcV9/RegAlloc/PhyRegAlloc.cpp diff -u llvm/lib/Target/SparcV9/RegAlloc/PhyRegAlloc.cpp:1.161 llvm/lib/Target/SparcV9/RegAlloc/PhyRegAlloc.cpp:1.162 --- llvm/lib/Target/SparcV9/RegAlloc/PhyRegAlloc.cpp:1.161 Wed Aug 18 12:44:16 2004 +++ llvm/lib/Target/SparcV9/RegAlloc/PhyRegAlloc.cpp Wed Aug 18 13:13:37 2004 @@ -424,7 +424,7 @@ unsigned Opcode = MInst->getOpcode(); // Reset tmp stack positions so they can be reused for each machine instr. - MF->getInfo()->popAllTempValues(); + MF->getInfo()->popAllTempValues(); // Mark the operands for which regs have been allocated. bool instrNeedsSpills = markAllocatedRegs(MII); @@ -643,7 +643,7 @@ } #endif - MF->getInfo()->pushTempValue(MRI.getSpilledRegSize(RegType)); + MF->getInfo()->pushTempValue(MRI.getSpilledRegSize(RegType)); std::vector MIBef, MIAft; std::vector AdIMid; @@ -796,7 +796,7 @@ // and add them to InstrnsBefore and InstrnsAfter of the // call instruction int StackOff = - MF->getInfo()->pushTempValue(MRI.getSpilledRegSize(RegType)); + MF->getInfo()->pushTempValue(MRI.getSpilledRegSize(RegType)); //---- Insert code for pushing the reg on stack ---------- @@ -895,7 +895,7 @@ // we couldn't find an unused register. Generate code to free up a reg by // saving it on stack and restoring after the instruction - int TmpOff = MF->getInfo()->pushTempValue(MRI.getSpilledRegSize(RegType)); + int TmpOff = MF->getInfo()->pushTempValue(MRI.getSpilledRegSize(RegType)); RegU = getUniRegNotUsedByThisInst(RC, RegType, MInst); @@ -1103,7 +1103,7 @@ if (HMI->first && HMI->second) { LiveRange *L = HMI->second; // get the LiveRange if (L->isMarkedForSpill()) { // NOTE: allocating size of long Type ** - int stackOffset = MF->getInfo()->allocateSpilledValue(Type::LongTy); + int stackOffset = MF->getInfo()->allocateSpilledValue(Type::LongTy); L->setSpillOffFromFP(stackOffset); if (DEBUG_RA) std::cerr << " LR# " << L->getUserIGNode()->getIndex() @@ -1323,7 +1323,7 @@ // Reset the temp. area on the stack before use by the first instruction. // This will also happen after updating each instruction. - MF->getInfo()->popAllTempValues(); + MF->getInfo()->popAllTempValues(); // color incoming args - if the correct color was not received // insert code to copy to the correct register From brukman at cs.uiuc.edu Wed Aug 18 14:48:50 2004 From: brukman at cs.uiuc.edu (Misha Brukman) Date: Wed, 18 Aug 2004 14:48:50 -0500 Subject: [llvm-commits] CVS: llvm-www/Developers.html Message-ID: <200408181948.OAA23364@zion.cs.uiuc.edu> Changes in directory llvm-www: Developers.html updated: 1.1 -> 1.2 --- Log message: Fix my homepage URL. --- Diffs of the changes: (+4 -4) Index: llvm-www/Developers.html diff -u llvm-www/Developers.html:1.1 llvm-www/Developers.html:1.2 --- llvm-www/Developers.html:1.1 Wed Aug 18 12:38:36 2004 +++ llvm-www/Developers.html Wed Aug 18 14:48:40 2004 @@ -31,10 +31,10 @@
    Misha Brukman - LLVM Bug
-      #100 + Misha Brukman + Misha