This document describes techniques for writing backends for LLVM which + convert the LLVM representation to machine assembly code or other languages.
+ +In general, you want to follow the format of X86 or PowerPC (in + lib/Target).
+ +To create a static compiler (one that emits text assembly), you need to + implement the following:
+ +-
+
- Describe the register set
+
-
+
- Create a TableGen description of + the register set and register classes +
- Implement a subclass of MRegisterInfo +
+ - Describe the instruction set
+
-
+
- Create a TableGen description of + the instruction set +
- Implement a subclass of TargetInstrInfo +
+ - Describe the target machine
+
-
+
- Create a TableGen description of + the target that describes the pointer size and references the instruction + set +
- Implement a subclass of TargetMachine, which + configures TargetData + correctly +
+ - Implement the assembly printer for the architecture. Usually, if you have + described the instruction set with the assembly printer generator in mind, that + step can be almost automated. +
Now, for static code generation you also need to write an instruction + selector for your platform: see lib/Target/*/*ISelSimple.cpp which + is no longer "simple" but it gives you the idea: you have to be able to create + MachineInstrs for any given LLVM instruction using the InstVisitor + pattern, and produce a MachineFunction with + MachineBasicBlocks full of MachineInstrs for a + corresponding LLVM Function. Creating an instruction selector is perhaps the + most time-consuming part of creating a back-end.
+ +To create a JIT for your platform:
+ +-
+
- Create a subclass of TargetJITInfo +
- Create a machine code emitter that will be used to emit binary code + directly into memory, given MachineInstrs +
Note that lib/target/Skeleton is a clean skeleton for a new target, + so you might want to start with that and adapt it for your target, and if you + are wondering how things are done, peek in the X86 or PowerPC target.
+ +The Skeleton target is non-functional but provides the basic building blocks + you will need for your endeavor.
+ +-
+
+
TableGen register info description - describe a class which + will store the register's number in the binary encoding of the instruction + (e.g., for JIT purposes).
+ +You also need to define register classes to contain these registers, such as + the integer register class and floating-point register class, so that you can + allocate virtual registers to instructions from these sets, and let the + target-independent register allocator automatically choose the actual + architected registers.
+ ++++ // class Register is defined in Target.td + class TargetReg : Register { + let Namespace = "Target"; + } + + class IntReg<bits<5> num> : TargetReg { + field bits<5> Num = num; + } + + def R0 : IntReg<0>; + ... + + // class RegisterClass is defined in Target.td + def IReg : RegisterClass<i64, 64, [R0, ... ]>; ++
+
+ TableGen instruction info description - break up instructions into + classes, usually that's already done by the manufacturer (see instruction + manual). Define a class for each instruction category. Define each opcode as a + subclass of the category, with appropriate parameters such as the fixed binary + encoding of opcodes and extended opcodes, and map the register bits to the bits + of the instruction which they are encoded in (for the JIT). Also specify how + the instruction should be printed so it can use the automatic assembly printer, + e.g.:
+ ++++ // class Instruction is defined in Target.td + class Form<bits<6> opcode, dag OL, string asmstr> : Instruction { + field bits<42> Inst; + + let Namespace = "Target"; + let Inst{0-6} = opcode; + let OperandList = OL; + let AsmString = asmstr; + } + + def ADD : Form<42, (ops IReg:$rD, IReg:$rA, IReg:$rB), "add $rD, $rA, $rB">; ++
+
+
For now, just take a look at lib/Target/CBackend for an example of + how the C backend is written.
+ +-
+
- Code generator - + describes some of the classes in code generation at a high level, but + it is not (yet) complete. +
- TableGen fundamentals - + describes how to use TableGen to describe your target information succinctly + +
+ +
+ + The LLVM Compiler Infrastructure +
+ Last modified: $Date: 2004/09/06 22:58:13 $ + + +