LLVM now includes an - Inter-Procedural Sparse Conditional Constant Propagation pass, named + Interprocedural Sparse Conditional Constant Propagation pass, named -ipsccp, which is run by default at link-time.

@@ -105,7 +105,8 @@

Building LLVM in optimized mode + should no longer cause GCC to hit swap in the PowerPC backend.

@@ -565,7 +566,7 @@ src="http://www.w3.org/Icons/valid-html401" alt="Valid HTML 4.01!" /> The LLVM Compiler Infrastructure
- Last modified: $Date: 2005/01/03 04:20:21 $ + Last modified: $Date: 2005/01/22 18:45:35 $ From jeffc at jolt-lang.org Sat Jan 22 12:50:21 2005 From: jeffc at jolt-lang.org (Jeff Cohen) Date: Sat, 22 Jan 2005 12:50:21 -0600 Subject: [llvm-commits] CVS: llvm/utils/TableGen/AsmWriterEmitter.cpp Message-ID: <200501221850.MAA28147@zion.cs.uiuc.edu> Changes in directory llvm/utils/TableGen: AsmWriterEmitter.cpp updated: 1.14 -> 1.15 --- Log message: Fix VC++ compilation error --- Diffs of the changes: (+1 -0) AsmWriterEmitter.cpp | 1 + 1 files changed, 1 insertion(+) Index: llvm/utils/TableGen/AsmWriterEmitter.cpp diff -u llvm/utils/TableGen/AsmWriterEmitter.cpp:1.14 llvm/utils/TableGen/AsmWriterEmitter.cpp:1.15 --- llvm/utils/TableGen/AsmWriterEmitter.cpp:1.14 Sat Jan 22 12:38:13 2005 +++ llvm/utils/TableGen/AsmWriterEmitter.cpp Sat Jan 22 12:50:10 2005 @@ -15,6 +15,7 @@ #include "AsmWriterEmitter.h" #include "CodeGenTarget.h" #include "Record.h" +#include #include using namespace llvm; From lattner at cs.uiuc.edu Sat Jan 22 12:59:06 2005 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Sat, 22 Jan 2005 12:59:06 -0600 Subject: [llvm-commits] CVS: llvm/utils/TableGen/CodeGenTarget.cpp CodeGenTarget.h InstrInfoEmitter.cpp Message-ID: <200501221859.j0MIx6Q8010782@apoc.cs.uiuc.edu> Changes in directory llvm/utils/TableGen: CodeGenTarget.cpp updated: 1.26 -> 1.27 CodeGenTarget.h updated: 1.15 -> 1.16 InstrInfoEmitter.cpp updated: 1.16 -> 1.17 --- Log message: Refactor code for numbering instructions into CodeGenTarget. --- Diffs of the changes: (+29 -10) CodeGenTarget.cpp | 16 ++++++++++++++++ CodeGenTarget.h | 6 ++++++ InstrInfoEmitter.cpp | 17 +++++++---------- 3 files changed, 29 insertions(+), 10 deletions(-) Index: llvm/utils/TableGen/CodeGenTarget.cpp diff -u llvm/utils/TableGen/CodeGenTarget.cpp:1.26 llvm/utils/TableGen/CodeGenTarget.cpp:1.27 --- llvm/utils/TableGen/CodeGenTarget.cpp:1.26 Sat Jan 1 20:29:04 2005 +++ llvm/utils/TableGen/CodeGenTarget.cpp Sat Jan 22 12:58:51 2005 @@ -198,6 +198,22 @@ return I->second; } +/// getInstructionsByEnumValue - Return all of the instructions defined by the +/// target, ordered by their enum value. +void CodeGenTarget:: +getInstructionsByEnumValue(std::vector + &NumberedInstructions) { + + // Print out the rest of the instructions now. + unsigned i = 0; + const CodeGenInstruction *PHI = &getPHIInstruction(); + NumberedInstructions.push_back(PHI); + for (inst_iterator II = inst_begin(), E = inst_end(); II != E; ++II) + if (&II->second != PHI) + NumberedInstructions.push_back(&II->second); +} + + /// isLittleEndianEncoding - Return whether this target encodes its instruction /// in little-endian format, i.e. bits laid out in the order [0..n] /// Index: llvm/utils/TableGen/CodeGenTarget.h diff -u llvm/utils/TableGen/CodeGenTarget.h:1.15 llvm/utils/TableGen/CodeGenTarget.h:1.16 --- llvm/utils/TableGen/CodeGenTarget.h:1.15 Wed Oct 27 11:06:27 2004 +++ llvm/utils/TableGen/CodeGenTarget.h Sat Jan 22 12:58:51 2005 @@ -93,6 +93,12 @@ inst_iterator inst_begin() const { return getInstructions().begin(); } inst_iterator inst_end() const { return Instructions.end(); } + /// getInstructionsByEnumValue - Return all of the instructions defined by the + /// target, ordered by their enum value. + void getInstructionsByEnumValue(std::vector + &NumberedInstructions); + + /// getPHIInstruction - Return the designated PHI instruction. /// const CodeGenInstruction &getPHIInstruction() const; Index: llvm/utils/TableGen/InstrInfoEmitter.cpp diff -u llvm/utils/TableGen/InstrInfoEmitter.cpp:1.16 llvm/utils/TableGen/InstrInfoEmitter.cpp:1.17 --- llvm/utils/TableGen/InstrInfoEmitter.cpp:1.16 Sat Jan 1 20:29:04 2005 +++ llvm/utils/TableGen/InstrInfoEmitter.cpp Sat Jan 22 12:58:51 2005 @@ -26,7 +26,6 @@ // We must emit the PHI opcode first... Record *InstrInfo = Target.getInstructionSet(); - Record *PHI = InstrInfo->getValueAsDef("PHIInst"); std::string Namespace = Target.inst_begin()->second.Namespace; @@ -34,15 +33,13 @@ OS << "namespace " << Namespace << " {\n"; OS << " enum {\n"; - OS << " " << PHI->getName() << ", \t// 0 (fixed for all targets)\n"; - - // Print out the rest of the instructions now. - unsigned i = 0; - for (CodeGenTarget::inst_iterator II = Target.inst_begin(), - E = Target.inst_end(); II != E; ++II) - if (II->second.TheDef != PHI) - OS << " " << II->first << ", \t// " << ++i << "\n"; - + std::vector NumberedInstructions; + Target.getInstructionsByEnumValue(NumberedInstructions); + + for (unsigned i = 0, e = NumberedInstructions.size(); i != e; ++i) { + OS << " " << NumberedInstructions[i]->TheDef->getName() + << ", \t// " << i << "\n"; + } OS << " };\n"; if (!Namespace.empty()) OS << "}\n"; From lattner at cs.uiuc.edu Sat Jan 22 13:22:38 2005 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Sat, 22 Jan 2005 13:22:38 -0600 Subject: [llvm-commits] CVS: llvm/utils/TableGen/AsmWriterEmitter.cpp Message-ID: <200501221922.j0MJMcFZ013364@apoc.cs.uiuc.edu> Changes in directory llvm/utils/TableGen: AsmWriterEmitter.cpp updated: 1.15 -> 1.16 --- Log message: Implement *even more* factoring. In particular, if all of the instruction strings starts out with a constant string, we emit the string first, using a table lookup (instead of a switch statement). Because this is usually the opcode portion of the asm string, the differences between the instructions have now been greatly reduced. This allows many more case statements to be grouped together. This patch also allows instruction cases to be grouped together when the instruction patterns are exactly identical (common after the opcode string has been ripped off), and when the differing operand is a MachineInstr operand that needs to be formatted. The end result of this is a mean and lean generated AsmPrinter! --- Diffs of the changes: (+62 -20) AsmWriterEmitter.cpp | 82 ++++++++++++++++++++++++++++++++++++++------------- 1 files changed, 62 insertions(+), 20 deletions(-) Index: llvm/utils/TableGen/AsmWriterEmitter.cpp diff -u llvm/utils/TableGen/AsmWriterEmitter.cpp:1.15 llvm/utils/TableGen/AsmWriterEmitter.cpp:1.16 --- llvm/utils/TableGen/AsmWriterEmitter.cpp:1.15 Sat Jan 22 12:50:10 2005 +++ llvm/utils/TableGen/AsmWriterEmitter.cpp Sat Jan 22 13:22:23 2005 @@ -64,10 +64,10 @@ AsmWriterInst(const CodeGenInstruction &CGI, unsigned Variant); - /// MatchesAllButOneString - If this instruction is exactly identical to the - /// specified instruction except for one differing literal string, return - /// the operand number of the literal string. Otherwise return ~0. - unsigned MatchesAllButOneString(const AsmWriterInst &Other) const; + /// MatchesAllButOneOp - If this instruction is exactly identical to the + /// specified instruction except for one differing operand, return the + /// differing operand number. Otherwise return ~0. + unsigned MatchesAllButOneOp(const AsmWriterInst &Other) const; private: void AddLiteralString(const std::string &Str) { @@ -183,21 +183,18 @@ AddLiteralString("\\n"); } -/// MatchesAllButOneString - If this instruction is exactly identical to the -/// specified instruction except for one differing literal string, return -/// the operand number of the literal string. Otherwise return ~0. -unsigned AsmWriterInst::MatchesAllButOneString(const AsmWriterInst &Other)const{ - if (Operands.size() != Other.Operands.size()) return ~0; +/// MatchesAllButOneOp - If this instruction is exactly identical to the +/// specified instruction except for one differing operand, return the differing +/// operand number. If more than one operand mismatches, return ~1, otherwise +/// if the instructions are identical return ~0. +unsigned AsmWriterInst::MatchesAllButOneOp(const AsmWriterInst &Other)const{ + if (Operands.size() != Other.Operands.size()) return ~1; unsigned MismatchOperand = ~0U; for (unsigned i = 0, e = Operands.size(); i != e; ++i) { - if (Operands[i].OperandType != Other.Operands[i].OperandType) - return ~0U; - if (Operands[i] != Other.Operands[i]) - if (Operands[i].OperandType == AsmWriterOperand::isMachineInstrOperand || - MismatchOperand != ~0U) - return ~0U; + if (MismatchOperand != ~0U) // Already have one mismatch? + return ~1U; else MismatchOperand = i; } @@ -215,14 +212,14 @@ std::vector SimilarInsts; unsigned DifferingOperand = ~0; for (unsigned i = Insts.size(); i != 0; --i) { - unsigned DiffOp = Insts[i-1].MatchesAllButOneString(FirstInst); - if (DiffOp != ~0U) { + unsigned DiffOp = Insts[i-1].MatchesAllButOneOp(FirstInst); + if (DiffOp != ~1U) { if (DifferingOperand == ~0U) // First match! DifferingOperand = DiffOp; // If this differs in the same operand as the rest of the instructions in // this class, move it to the SimilarInsts list. - if (DifferingOperand == DiffOp) { + if (DifferingOperand == DiffOp || DiffOp == ~0U) { SimilarInsts.push_back(Insts[i-1]); Insts.erase(Insts.begin()+i-1); } @@ -278,8 +275,6 @@ "/// it returns false.\n" "bool " << Target.getName() << ClassName << "::printInstruction(const MachineInstr *MI) {\n"; - O << " switch (MI->getOpcode()) {\n" - " default: return false;\n"; std::string Namespace = Target.inst_begin()->second.Namespace; @@ -290,9 +285,56 @@ if (!I->second.AsmString.empty()) Instructions.push_back(AsmWriterInst(I->second, Variant)); + // If all of the instructions start with a constant string (a very very common + // occurance), emit all of the constant strings as a big table lookup instead + // of requiring a switch for them. + bool AllStartWithString = true; + + for (unsigned i = 0, e = Instructions.size(); i != e; ++i) + if (Instructions[i].Operands.empty() || + Instructions[i].Operands[0].OperandType != + AsmWriterOperand::isLiteralTextOperand) { + AllStartWithString = false; + break; + } + + if (AllStartWithString) { + // Compute the CodeGenInstruction -> AsmWriterInst mapping. Note that not + // all machine instructions are necessarily being printed, so there may be + // target instructions not in this map. + std::map CGIAWIMap; + for (unsigned i = 0, e = Instructions.size(); i != e; ++i) + CGIAWIMap.insert(std::make_pair(Instructions[i].CGI, &Instructions[i])); + + // Emit a table of constant strings. + std::vector NumberedInstructions; + Target.getInstructionsByEnumValue(NumberedInstructions); + + O << " static const char * const OpStrs[] = {\n"; + for (unsigned i = 0, e = NumberedInstructions.size(); i != e; ++i) { + AsmWriterInst *AWI = CGIAWIMap[NumberedInstructions[i]]; + if (AWI == 0) { + // Something not handled by the asmwriter printer. + O << " 0,\t// "; + } else { + O << " \"" << AWI->Operands[0].Str << "\",\t// "; + // Nuke the string from the operand list. It is now handled! + AWI->Operands.erase(AWI->Operands.begin()); + } + O << NumberedInstructions[i]->TheDef->getName() << "\n"; + } + O << " };\n\n" + << " // Emit the opcode for the instruction.\n" + << " if (const char *AsmStr = OpStrs[MI->getOpcode()])\n" + << " O << AsmStr;\n\n"; + } + // Because this is a vector we want to emit from the end. Reverse all of the // elements in the vector. std::reverse(Instructions.begin(), Instructions.end()); + + O << " switch (MI->getOpcode()) {\n" + " default: return false;\n"; while (!Instructions.empty()) EmitInstructions(Instructions, O); From lattner at cs.uiuc.edu Sat Jan 22 14:31:32 2005 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Sat, 22 Jan 2005 14:31:32 -0600 Subject: [llvm-commits] CVS: llvm/utils/TableGen/AsmWriterEmitter.cpp Message-ID: <200501222031.j0MKVWn1014569@apoc.cs.uiuc.edu> Changes in directory llvm/utils/TableGen: AsmWriterEmitter.cpp updated: 1.16 -> 1.17 --- Log message: This is the final big of factoring. This shares cases in suboperand differences, which means that identical instructions (after stripping off the first literal string) do not run any different code at all. On the X86, this turns this code: switch (MI->getOpcode()) { case X86::ADC32mi: printOperand(MI, 4, MVT::i32); break; case X86::ADC32mi8: printOperand(MI, 4, MVT::i8); break; case X86::ADC32mr: printOperand(MI, 4, MVT::i32); break; case X86::ADD32mi: printOperand(MI, 4, MVT::i32); break; case X86::ADD32mi8: printOperand(MI, 4, MVT::i8); break; case X86::ADD32mr: printOperand(MI, 4, MVT::i32); break; case X86::AND32mi: printOperand(MI, 4, MVT::i32); break; case X86::AND32mi8: printOperand(MI, 4, MVT::i8); break; case X86::AND32mr: printOperand(MI, 4, MVT::i32); break; case X86::CMP32mi: printOperand(MI, 4, MVT::i32); break; case X86::CMP32mr: printOperand(MI, 4, MVT::i32); break; case X86::MOV32mi: printOperand(MI, 4, MVT::i32); break; case X86::MOV32mr: printOperand(MI, 4, MVT::i32); break; case X86::OR32mi: printOperand(MI, 4, MVT::i32); break; case X86::OR32mi8: printOperand(MI, 4, MVT::i8); break; case X86::OR32mr: printOperand(MI, 4, MVT::i32); break; case X86::ROL32mi: printOperand(MI, 4, MVT::i8); break; case X86::ROR32mi: printOperand(MI, 4, MVT::i8); break; case X86::SAR32mi: printOperand(MI, 4, MVT::i8); break; case X86::SBB32mi: printOperand(MI, 4, MVT::i32); break; case X86::SBB32mi8: printOperand(MI, 4, MVT::i8); break; case X86::SBB32mr: printOperand(MI, 4, MVT::i32); break; case X86::SHL32mi: printOperand(MI, 4, MVT::i8); break; case X86::SHLD32mrCL: printOperand(MI, 4, MVT::i32); break; case X86::SHR32mi: printOperand(MI, 4, MVT::i8); break; case X86::SHRD32mrCL: printOperand(MI, 4, MVT::i32); break; case X86::SUB32mi: printOperand(MI, 4, MVT::i32); break; case X86::SUB32mi8: printOperand(MI, 4, MVT::i8); break; case X86::SUB32mr: printOperand(MI, 4, MVT::i32); break; case X86::TEST32mi: printOperand(MI, 4, MVT::i32); break; case X86::TEST32mr: printOperand(MI, 4, MVT::i32); break; case X86::TEST8mi: printOperand(MI, 4, MVT::i8); break; case X86::XCHG32mr: printOperand(MI, 4, MVT::i32); break; case X86::XOR32mi: printOperand(MI, 4, MVT::i32); break; case X86::XOR32mi8: printOperand(MI, 4, MVT::i8); break; case X86::XOR32mr: printOperand(MI, 4, MVT::i32); break; } into this: switch (MI->getOpcode()) { case X86::ADC32mi: case X86::ADC32mr: case X86::ADD32mi: case X86::ADD32mr: case X86::AND32mi: case X86::AND32mr: case X86::CMP32mi: case X86::CMP32mr: case X86::MOV32mi: case X86::MOV32mr: case X86::OR32mi: case X86::OR32mr: case X86::SBB32mi: case X86::SBB32mr: case X86::SHLD32mrCL: case X86::SHRD32mrCL: case X86::SUB32mi: case X86::SUB32mr: case X86::TEST32mi: case X86::TEST32mr: case X86::XCHG32mr: case X86::XOR32mi: case X86::XOR32mr: printOperand(MI, 4, MVT::i32); break; case X86::ADC32mi8: case X86::ADD32mi8: case X86::AND32mi8: case X86::OR32mi8: case X86::ROL32mi: case X86::ROR32mi: case X86::SAR32mi: case X86::SBB32mi8: case X86::SHL32mi: case X86::SHR32mi: case X86::SUB32mi8: case X86::TEST8mi: case X86::XOR32mi8: printOperand(MI, 4, MVT::i8); break; } After this, the generated asmwriters look pretty much as though they were generated by hand. This shrinks the X86 asmwriter.inc files from 55101->39669 and 55429->39551 bytes each, and PPC from 16766->12859 bytes. --- Diffs of the changes: (+34 -8) AsmWriterEmitter.cpp | 42 ++++++++++++++++++++++++++++++++++-------- 1 files changed, 34 insertions(+), 8 deletions(-) Index: llvm/utils/TableGen/AsmWriterEmitter.cpp diff -u llvm/utils/TableGen/AsmWriterEmitter.cpp:1.16 llvm/utils/TableGen/AsmWriterEmitter.cpp:1.17 --- llvm/utils/TableGen/AsmWriterEmitter.cpp:1.16 Sat Jan 22 13:22:23 2005 +++ llvm/utils/TableGen/AsmWriterEmitter.cpp Sat Jan 22 14:31:17 2005 @@ -55,6 +55,9 @@ return MIOpNo != Other.MIOpNo || OpVT != Other.OpVT; return false; } + bool operator==(const AsmWriterOperand &Other) const { + return !operator!=(Other); + } void EmitCode(std::ostream &OS) const; }; @@ -201,6 +204,25 @@ return MismatchOperand; } +static void PrintCases(std::vector > &OpsToPrint, std::ostream &O) { + O << " case " << OpsToPrint.back().first << ": "; + AsmWriterOperand TheOp = OpsToPrint.back().second; + OpsToPrint.pop_back(); + + // Check to see if any other operands are identical in this list, and if so, + // emit a case label for them. + for (unsigned i = OpsToPrint.size(); i != 0; --i) + if (OpsToPrint[i-1].second == TheOp) { + O << "\n case " << OpsToPrint[i-1].first << ": "; + OpsToPrint.erase(OpsToPrint.begin()+i-1); + } + + // Finally, emit the code. + TheOp.EmitCode(O); + O << "break;\n"; +} + /// EmitInstructions - Emit the last instruction in the vector and any other /// instructions that are suitably similar to it. @@ -242,16 +264,20 @@ // If this is the operand that varies between all of the instructions, // emit a switch for just this operand now. O << " switch (MI->getOpcode()) {\n"; - O << " case " << Namespace << "::" - << FirstInst.CGI->TheDef->getName() << ": "; - FirstInst.Operands[i].EmitCode(O); - O << "break;\n"; + std::vector > OpsToPrint; + OpsToPrint.push_back(std::make_pair(Namespace+"::"+ + FirstInst.CGI->TheDef->getName(), + FirstInst.Operands[i])); + for (unsigned si = 0, e = SimilarInsts.size(); si != e; ++si) { - O << " case " << Namespace << "::" - << SimilarInsts[si].CGI->TheDef->getName() << ": "; - SimilarInsts[si].Operands[i].EmitCode(O); - O << "break;\n"; + AsmWriterInst &AWI = SimilarInsts[si]; + OpsToPrint.push_back(std::make_pair(Namespace+"::"+ + AWI.CGI->TheDef->getName(), + AWI.Operands[i])); } + std::reverse(OpsToPrint.begin(), OpsToPrint.end()); + while (!OpsToPrint.empty()) + PrintCases(OpsToPrint, O); O << " }"; } O << "\n"; From lattner at cs.uiuc.edu Sat Jan 22 14:59:53 2005 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Sat, 22 Jan 2005 14:59:53 -0600 Subject: [llvm-commits] CVS: llvm/utils/TableGen/AsmWriterEmitter.cpp Message-ID: <200501222059.j0MKxrkG015930@apoc.cs.uiuc.edu> Changes in directory llvm/utils/TableGen: AsmWriterEmitter.cpp updated: 1.17 -> 1.18 --- Log message: Minor fix. --- Diffs of the changes: (+1 -1) AsmWriterEmitter.cpp | 2 +- 1 files changed, 1 insertion(+), 1 deletion(-) Index: llvm/utils/TableGen/AsmWriterEmitter.cpp diff -u llvm/utils/TableGen/AsmWriterEmitter.cpp:1.17 llvm/utils/TableGen/AsmWriterEmitter.cpp:1.18 --- llvm/utils/TableGen/AsmWriterEmitter.cpp:1.17 Sat Jan 22 14:31:17 2005 +++ llvm/utils/TableGen/AsmWriterEmitter.cpp Sat Jan 22 14:59:38 2005 @@ -90,7 +90,7 @@ if (OperandType == isLiteralTextOperand) OS << "O << \"" << Str << "\"; "; else - OS << Str << "(MI, " << MIOpNo << ", MVT::" << getName(OpVT) << "); "; + OS << Str << "(MI, " << MIOpNo << ", MVT::" << getEnumName(OpVT) << "); "; } From reid at x10sys.com Sat Jan 22 15:29:52 2005 From: reid at x10sys.com (Reid Spencer) Date: Sat, 22 Jan 2005 15:29:52 -0600 Subject: [llvm-commits] CVS: llvm/autoconf/configure.ac Message-ID: <200501222129.PAA29439@zion.cs.uiuc.edu> Changes in directory llvm/autoconf: configure.ac updated: 1.164 -> 1.165 --- Log message: We're working towards LLVM 1.5 now so bump the version number. This change won't be propagated to the configure script until there's a need to change configure.ac for some larger purpose. --- Diffs of the changes: (+1 -1) configure.ac | 2 +- 1 files changed, 1 insertion(+), 1 deletion(-) Index: llvm/autoconf/configure.ac diff -u llvm/autoconf/configure.ac:1.164 llvm/autoconf/configure.ac:1.165 --- llvm/autoconf/configure.ac:1.164 Sun Jan 16 03:44:57 2005 +++ llvm/autoconf/configure.ac Sat Jan 22 15:29:42 2005 @@ -31,7 +31,7 @@ dnl===-----------------------------------------------------------------------=== dnl Initialize autoconf and define the package name, version number and dnl email address for reporting bugs. -AC_INIT([[llvm]],[[1.4]],[llvmbugs at cs.uiuc.edu]) +AC_INIT([[llvm]],[[1.5]],[llvmbugs at cs.uiuc.edu]) dnl Provide a copyright substitution and ensure the copyright notice is included dnl in the output of --version option of the generated configure script. From lattner at cs.uiuc.edu Sat Jan 22 15:40:39 2005 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Sat, 22 Jan 2005 15:40:39 -0600 Subject: [llvm-commits] CVS: llvm-www/img/PhotoDuraid.jpg Message-ID: <200501222140.j0MLedqH016021@apoc.cs.uiuc.edu> Changes in directory llvm-www/img: PhotoDuraid.jpg added (r1.1) --- Log message: Add photo --- Diffs of the changes: (+0 -0) PhotoDuraid.jpg | 0 1 files changed Index: llvm-www/img/PhotoDuraid.jpg From lattner at cs.uiuc.edu Sat Jan 22 15:44:45 2005 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Sat, 22 Jan 2005 15:44:45 -0600 Subject: [llvm-commits] CVS: llvm-www/PhotoReid.jpg Message-ID: <200501222144.j0MLijMn016051@apoc.cs.uiuc.edu> Changes in directory llvm-www: PhotoReid.jpg added (r1.1) --- Log message: Add reid's photo --- Diffs of the changes: (+0 -0) PhotoReid.jpg | 0 1 files changed Index: llvm-www/PhotoReid.jpg From lattner at cs.uiuc.edu Sat Jan 22 15:47:17 2005 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Sat, 22 Jan 2005 15:47:17 -0600 Subject: [llvm-commits] CVS: llvm-www/PhotoReid.jpg Message-ID: <200501222147.j0MLlHSJ016097@apoc.cs.uiuc.edu> Changes in directory llvm-www: PhotoReid.jpg (r1.1) removed --- Log message: Reid should be in the img directory, not here. --- Diffs of the changes: (+0 -0) 0 files changed From lattner at cs.uiuc.edu Sat Jan 22 15:47:25 2005 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Sat, 22 Jan 2005 15:47:25 -0600 Subject: [llvm-commits] CVS: llvm-www/img/PhotoReid.jpg Message-ID: <200501222147.j0MLlPnA016111@apoc.cs.uiuc.edu> Changes in directory llvm-www/img: PhotoReid.jpg added (r1.1) --- Log message: Add Reid's photo --- Diffs of the changes: (+0 -0) PhotoReid.jpg | 0 1 files changed Index: llvm-www/img/PhotoReid.jpg From lattner at cs.uiuc.edu Sat Jan 22 15:48:45 2005 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Sat, 22 Jan 2005 15:48:45 -0600 Subject: [llvm-commits] CVS: llvm-www/img/PhotoVikram.jpg Message-ID: <200501222148.j0MLmj7R016139@apoc.cs.uiuc.edu> Changes in directory llvm-www/img: PhotoVikram.jpg added (r1.1) --- Log message: Add vadve's picture --- Diffs of the changes: (+0 -0) PhotoVikram.jpg | 0 1 files changed Index: llvm-www/img/PhotoVikram.jpg From lattner at cs.uiuc.edu Sat Jan 22 15:49:44 2005 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Sat, 22 Jan 2005 15:49:44 -0600 Subject: [llvm-commits] CVS: llvm-www/img/PhotoBrad.jpg Message-ID: <200501222149.j0MLniqw016166@apoc.cs.uiuc.edu> Changes in directory llvm-www/img: PhotoBrad.jpg added (r1.1) --- Log message: Add brad's photo --- Diffs of the changes: (+0 -0) PhotoBrad.jpg | 0 1 files changed Index: llvm-www/img/PhotoBrad.jpg From lattner at cs.uiuc.edu Sat Jan 22 15:50:33 2005 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Sat, 22 Jan 2005 15:50:33 -0600 Subject: [llvm-commits] CVS: llvm-www/img/PhotoNate.jpg Message-ID: <200501222150.j0MLoX05016195@apoc.cs.uiuc.edu> Changes in directory llvm-www/img: PhotoNate.jpg added (r1.1) --- Log message: Add nate's photo --- Diffs of the changes: (+0 -0) PhotoNate.jpg | 0 1 files changed Index: llvm-www/img/PhotoNate.jpg From lattner at cs.uiuc.edu Sat Jan 22 15:54:44 2005 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Sat, 22 Jan 2005 15:54:44 -0600 Subject: [llvm-commits] CVS: llvm-www/img/PhotoJohn.jpg Message-ID: <200501222154.j0MLsi3W016240@apoc.cs.uiuc.edu> Changes in directory llvm-www/img: PhotoJohn.jpg added (r1.1) --- Log message: Add John's "photo" --- Diffs of the changes: (+0 -0) PhotoJohn.jpg | 0 1 files changed Index: llvm-www/img/PhotoJohn.jpg From lattner at cs.uiuc.edu Sat Jan 22 15:55:18 2005 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Sat, 22 Jan 2005 15:55:18 -0600 Subject: [llvm-commits] CVS: llvm-www/img/PhotoJohn.gif PhotoJohn.jpg Message-ID: <200501222155.j0MLtI09016265@apoc.cs.uiuc.edu> Changes in directory llvm-www/img: PhotoJohn.gif added (r1.1) PhotoJohn.jpg (r1.1) removed --- Log message: Except of course that this is a gif, not a jpg --- Diffs of the changes: (+0 -0) PhotoJohn.gif | 0 1 files changed Index: llvm-www/img/PhotoJohn.gif From lattner at cs.uiuc.edu Sat Jan 22 15:56:33 2005 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Sat, 22 Jan 2005 15:56:33 -0600 Subject: [llvm-commits] CVS: llvm-www/img/PhotoBrian.png Message-ID: <200501222156.j0MLuXj6016290@apoc.cs.uiuc.edu> Changes in directory llvm-www/img: PhotoBrian.png added (r1.1) --- Log message: Add brg's picture. --- Diffs of the changes: (+0 -0) PhotoBrian.png | 0 1 files changed Index: llvm-www/img/PhotoBrian.png From lattner at cs.uiuc.edu Sat Jan 22 15:59:35 2005 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Sat, 22 Jan 2005 15:59:35 -0600 Subject: [llvm-commits] CVS: llvm-www/img/PhotoMisha.png Message-ID: <200501222159.j0MLxZTE016321@apoc.cs.uiuc.edu> Changes in directory llvm-www/img: PhotoMisha.png added (r1.1) --- Log message: Add Misha's "photo" --- Diffs of the changes: (+0 -0) PhotoMisha.png | 0 1 files changed Index: llvm-www/img/PhotoMisha.png From lattner at cs.uiuc.edu Sat Jan 22 16:01:38 2005 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Sat, 22 Jan 2005 16:01:38 -0600 Subject: [llvm-commits] CVS: llvm-www/img/PhotoAlkis.jpg PhotoBill.jpg PhotoChris.jpg PhotoTanya.jpg AlkisPhoto.jpg BillWendlingPhoto.jpeg ChrisPhoto.jpg TanyaPhoto.jpg Message-ID: <200501222201.j0MM1cMY016378@apoc.cs.uiuc.edu> Changes in directory llvm-www/img: PhotoAlkis.jpg added (r1.1) PhotoBill.jpg added (r1.1) PhotoChris.jpg added (r1.1) PhotoTanya.jpg added (r1.1) AlkisPhoto.jpg (r1.1) removed BillWendlingPhoto.jpeg (r1.1) removed ChrisPhoto.jpg (r1.1) removed TanyaPhoto.jpg (r1.1) removed --- Log message: Rename all photos to be "Photo" so they sort together. --- Diffs of the changes: (+0 -0) PhotoAlkis.jpg | 0 PhotoBill.jpg | 0 PhotoChris.jpg | 0 PhotoTanya.jpg | 0 4 files changed Index: llvm-www/img/PhotoAlkis.jpg Index: llvm-www/img/PhotoBill.jpg Index: llvm-www/img/PhotoChris.jpg Index: llvm-www/img/PhotoTanya.jpg From lattner at cs.uiuc.edu Sat Jan 22 16:01:44 2005 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Sat, 22 Jan 2005 16:01:44 -0600 Subject: [llvm-commits] CVS: llvm-www/Developers.html Message-ID: <200501222201.j0MM1iQR016387@apoc.cs.uiuc.edu> Changes in directory llvm-www: Developers.html updated: 1.20 -> 1.21 --- Log message: Add Duraid to the list (causing everyone to be pushed down) Move all images to the local server Add height and width tags to all of the images. Rename all photos to be "Photo" so they sort together. --- Diffs of the changes: (+32 -26) Developers.html | 58 ++++++++++++++++++++++++++++++-------------------------- 1 files changed, 32 insertions(+), 26 deletions(-) Index: llvm-www/Developers.html diff -u llvm-www/Developers.html:1.20 llvm-www/Developers.html:1.21 --- llvm-www/Developers.html:1.20 Mon Jan 10 02:30:20 2005 +++ llvm-www/Developers.html Sat Jan 22 16:01:32 2005 @@ -18,59 +18,65 @@ Vikram Adve -

- Brian Gaeke - -

- + Brad Jones + +

Nate Begeman -

- Brad Jones - -

+ + Chris Lattner + +

Misha Brukman -

- Chris Lattner - -

+ + Tanya Lattner + +

+ John Criswell

- Tanya Lattner - -

+ Duraid Madina + +

+ Alkis Evlogimenos -

Reid Spencer -

- - + Brian Gaeke + +

+ Bill Wendling -

From lattner at cs.uiuc.edu Sat Jan 22 17:04:52 2005 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Sat, 22 Jan 2005 17:04:52 -0600 Subject: [llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp Message-ID: <200501222304.j0MN4qUA016685@apoc.cs.uiuc.edu> Changes in directory llvm/lib/CodeGen/SelectionDAG: SelectionDAGISel.cpp updated: 1.28 -> 1.29 --- Log message: Get this to work for 64-bit systems. --- Diffs of the changes: (+11 -6) SelectionDAGISel.cpp | 17 +++++++++++------ 1 files changed, 11 insertions(+), 6 deletions(-) Index: llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp diff -u llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.28 llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.29 --- llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.28 Wed Jan 19 16:31:21 2005 +++ llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp Sat Jan 22 17:04:37 2005 @@ -566,11 +566,13 @@ unsigned Align = TLI.getTargetData().getTypeAlignment(Ty); SDOperand AllocSize = getValue(I.getArraySize()); + MVT::ValueType IntPtr = TLI.getPointerTy(); + if (IntPtr < AllocSize.getValueType()) + AllocSize = DAG.getNode(ISD::TRUNCATE, IntPtr, AllocSize); + else if (IntPtr > AllocSize.getValueType()) + AllocSize = DAG.getNode(ISD::ZERO_EXTEND, IntPtr, AllocSize); - assert(AllocSize.getValueType() == TLI.getPointerTy() && - "FIXME: should extend or truncate to pointer size!"); - - AllocSize = DAG.getNode(ISD::MUL, TLI.getPointerTy(), AllocSize, + AllocSize = DAG.getNode(ISD::MUL, IntPtr, AllocSize, getIntPtrConstant(TySize)); // Handle alignment. If the requested alignment is less than or equal to the @@ -679,8 +681,11 @@ SDOperand Src = getValue(I.getOperand(0)); MVT::ValueType IntPtr = TLI.getPointerTy(); - // FIXME: Extend or truncate to the intptr size. - assert(Src.getValueType() == IntPtr && "Need to adjust the amount!"); + + if (IntPtr < Src.getValueType()) + Src = DAG.getNode(ISD::TRUNCATE, IntPtr, Src); + else if (IntPtr > Src.getValueType()) + Src = DAG.getNode(ISD::ZERO_EXTEND, IntPtr, Src); // Scale the source by the type size. uint64_t ElementSize = TD.getTypeSize(I.getType()->getElementType()); From alenhar2 at cs.uiuc.edu Sat Jan 22 17:39:36 2005 From: alenhar2 at cs.uiuc.edu (Andrew Lenharth) Date: Sat, 22 Jan 2005 17:39:36 -0600 Subject: [llvm-commits] CVS: llvm/lib/Target/Alpha/ Message-ID: <200501222339.RAA19571@niobe.cs.uiuc.edu> Changes in directory llvm/lib/Target/Alpha: --- Log message: Directory /home/vadve/shared/PublicCVS/llvm/lib/Target/Alpha added to the repository --- Diffs of the changes: (+0 -0) 0 files changed From alenhar2 at cs.uiuc.edu Sat Jan 22 17:42:10 2005 From: alenhar2 at cs.uiuc.edu (Andrew Lenharth) Date: Sat, 22 Jan 2005 17:42:10 -0600 Subject: [llvm-commits] CVS: llvm/lib/Target/Alpha/Alpha.h Alpha.td AlphaAsmPrinter.cpp AlphaISelPattern.cpp AlphaInstrBuilder.h AlphaInstrFormats.td AlphaInstrInfo.cpp AlphaInstrInfo.h AlphaInstrInfo.td AlphaRegisterInfo.cpp AlphaRegisterInfo.h AlphaRegisterInfo.td AlphaTargetMachine.cpp AlphaTargetMachine.h Makefile Message-ID: <200501222342.RAA19641@niobe.cs.uiuc.edu> Changes in directory llvm/lib/Target/Alpha: Alpha.h added (r1.1) Alpha.td added (r1.1) AlphaAsmPrinter.cpp added (r1.1) AlphaISelPattern.cpp added (r1.1) AlphaInstrBuilder.h added (r1.1) AlphaInstrFormats.td added (r1.1) AlphaInstrInfo.cpp added (r1.1) AlphaInstrInfo.h added (r1.1) AlphaInstrInfo.td added (r1.1) AlphaRegisterInfo.cpp added (r1.1) AlphaRegisterInfo.h added (r1.1) AlphaRegisterInfo.td added (r1.1) AlphaTargetMachine.cpp added (r1.1) AlphaTargetMachine.h added (r1.1) Makefile added (r1.1) --- Log message: Let me introduce you to the early stages of the llvm backend for the alpha processor --- Diffs of the changes: (+2305 -0) Alpha.h | 41 ++ Alpha.td | 56 +++ AlphaAsmPrinter.cpp | 319 +++++++++++++++++++ AlphaISelPattern.cpp | 797 +++++++++++++++++++++++++++++++++++++++++++++++++ AlphaInstrFormats.td | 109 ++++++ AlphaInstrInfo.cpp | 43 ++ AlphaInstrInfo.h | 42 ++ AlphaInstrInfo.td | 295 ++++++++++++++++++ AlphaRegisterInfo.cpp | 268 ++++++++++++++++ AlphaRegisterInfo.h | 57 +++ AlphaRegisterInfo.td | 93 +++++ AlphaTargetMachine.cpp | 111 ++++++ AlphaTargetMachine.h | 54 +++ Makefile | 20 + 14 files changed, 2305 insertions(+) Index: llvm/lib/Target/Alpha/Alpha.h diff -c /dev/null llvm/lib/Target/Alpha/Alpha.h:1.1 *** /dev/null Sat Jan 22 17:42:05 2005 --- llvm/lib/Target/Alpha/Alpha.h Sat Jan 22 17:41:55 2005 *************** *** 0 **** --- 1,41 ---- + //===-- Alpha.h - Top-level interface for Alpha representation -*- C++ -*-// + // + // The LLVM Compiler Infrastructure + // + // This file was developed by the LLVM research group and is distributed under + // the University of Illinois Open Source License. See LICENSE.TXT for details. + // + //===----------------------------------------------------------------------===// + // + // This file contains the entry points for global functions defined in the LLVM + // Alpha back-end. + // + //===----------------------------------------------------------------------===// + + #ifndef TARGET_ALPHA_H + #define TARGET_ALPHA_H + + #include + + namespace llvm { + + class FunctionPass; + class TargetMachine; + + FunctionPass *createAlphaSimpleInstructionSelector(TargetMachine &TM); + FunctionPass *createAlphaCodePrinterPass(std::ostream &OS, + TargetMachine &TM); + FunctionPass *createAlphaPatternInstructionSelector(TargetMachine &TM); + + } // end namespace llvm; + + // Defines symbolic names for Alpha registers. This defines a mapping from + // register name to register number. + // + #include "AlphaGenRegisterNames.inc" + + // Defines symbolic names for the Alpha instructions. + // + #include "AlphaGenInstrNames.inc" + + #endif Index: llvm/lib/Target/Alpha/Alpha.td diff -c /dev/null llvm/lib/Target/Alpha/Alpha.td:1.1 *** /dev/null Sat Jan 22 17:42:10 2005 --- llvm/lib/Target/Alpha/Alpha.td Sat Jan 22 17:41:55 2005 *************** *** 0 **** --- 1,56 ---- + //===- Alpha.td - Describe the Alpha Target Machine ----*- tablegen -*-===// + // + // The LLVM Compiler Infrastructure + // + // This file was developed by the LLVM research group and is distributed under + // the University of Illinois Open Source License. See LICENSE.TXT for details. + // + //===----------------------------------------------------------------------===// + // + // + //===----------------------------------------------------------------------===// + + // Get the target-independent interfaces which we are implementing... + // + include "../Target.td" + + //Alpha is little endian + + //===----------------------------------------------------------------------===// + // Register File Description + //===----------------------------------------------------------------------===// + + include "AlphaRegisterInfo.td" + + //===----------------------------------------------------------------------===// + // Instruction Descriptions + //===----------------------------------------------------------------------===// + + include "AlphaInstrInfo.td" + + def AlphaInstrInfo : InstrInfo { + let PHIInst = PHI; + + // Define how we want to layout our target-specific information field. + // let TSFlagsFields = []; + // let TSFlagsShifts = []; + } + + def Alpha : Target { + // Pointers on Alpha are 64-bits in size. + let PointerType = i64; + + let CalleeSavedRegisters = + //saved regs + [R9, R10, R11, R12, R13, R14, + //Frame pointer + R15, + //return address + R26, + //Stack Pointer + R30, + F2, F3, F4, F5, F6, F7, F8, F9]; + + // Pull in Instruction Info: + let InstructionSet = AlphaInstrInfo; + } Index: llvm/lib/Target/Alpha/AlphaAsmPrinter.cpp diff -c /dev/null llvm/lib/Target/Alpha/AlphaAsmPrinter.cpp:1.1 *** /dev/null Sat Jan 22 17:42:10 2005 --- llvm/lib/Target/Alpha/AlphaAsmPrinter.cpp Sat Jan 22 17:41:55 2005 *************** *** 0 **** --- 1,319 ---- + //===-- AlphaAsmPrinter.cpp - Alpha LLVM assembly writer --------------===// + // + // The LLVM Compiler Infrastructure + // + // This file was developed by the LLVM research group and is distributed under + // the University of Illinois Open Source License. See LICENSE.TXT for details. + // + //===----------------------------------------------------------------------===// + // + // This file contains a printer that converts from our internal representation + // of machine-dependent LLVM code to GAS-format Alpha assembly language. + // + //===----------------------------------------------------------------------===// + + #include "Alpha.h" + #include "AlphaInstrInfo.h" + #include "llvm/Constants.h" + #include "llvm/DerivedTypes.h" + #include "llvm/Module.h" + #include "llvm/Assembly/Writer.h" + #include "llvm/CodeGen/MachineFunctionPass.h" + #include "llvm/CodeGen/MachineConstantPool.h" + #include "llvm/CodeGen/MachineInstr.h" + #include "llvm/CodeGen/ValueTypes.h" + #include "llvm/CodeGen/AsmPrinter.h" + + #include "llvm/Target/TargetMachine.h" + #include "llvm/Target/MRegisterInfo.h" + #include "llvm/Target/TargetInstrInfo.h" + + #include "llvm/Support/Mangler.h" + #include "llvm/ADT/Statistic.h" + #include "llvm/ADT/StringExtras.h" + #include "llvm/Support/CommandLine.h" + #include + using namespace llvm; + + namespace { + Statistic<> EmittedInsts("asm-printer", "Number of machine instrs printed"); + + struct AlphaAsmPrinter : public AsmPrinter { + + /// Unique incrementer for label values for referencing Global values. + /// + unsigned LabelNumber; + + AlphaAsmPrinter(std::ostream &o, TargetMachine &tm) + : AsmPrinter(o, tm), LabelNumber(0) + { } + + /// We name each basic block in a Function with a unique number, so + /// that we can consistently refer to them later. This is cleared + /// at the beginning of each call to runOnMachineFunction(). + /// + typedef std::map ValueMapTy; + ValueMapTy NumberForBB; + + virtual const char *getPassName() const { + return "Alpha Assembly Printer"; + } + bool printInstruction(const MachineInstr *MI); + void printOp(const MachineOperand &MO, bool IsCallOp = false); + void printConstantPool(MachineConstantPool *MCP); + void printOperand(const MachineInstr *MI, int opNum, MVT::ValueType VT); + void printBaseOffsetPair (const MachineInstr *MI, int i, bool brackets=true); + void printMachineInstruction(const MachineInstr *MI); + bool runOnMachineFunction(MachineFunction &F); + bool doInitialization(Module &M); + bool doFinalization(Module &M); + }; + } // end of anonymous namespace + + /// createAlphaCodePrinterPass - Returns a pass that prints the Alpha + /// assembly code for a MachineFunction to the given output stream, + /// using the given target machine description. This should work + /// regardless of whether the function is in SSA form. + /// + FunctionPass *llvm::createAlphaCodePrinterPass (std::ostream &o, + TargetMachine &tm) { + return new AlphaAsmPrinter(o, tm); + } + + #include "AlphaGenAsmWriter.inc" + + void AlphaAsmPrinter::printOperand(const MachineInstr *MI, int opNum, MVT::ValueType VT) + { + const MachineOperand &MO = MI->getOperand(opNum); + if (MO.getType() == MachineOperand::MO_MachineRegister) { + assert(MRegisterInfo::isPhysicalRegister(MO.getReg())&&"Not physreg??"); + O << LowercaseString(TM.getRegisterInfo()->get(MO.getReg()).Name); + } else if (MO.isImmediate()) { + O << MO.getImmedValue(); + } else { + printOp(MO); + } + } + + + void AlphaAsmPrinter::printOp(const MachineOperand &MO, bool IsCallOp) { + const MRegisterInfo &RI = *TM.getRegisterInfo(); + int new_symbol; + + switch (MO.getType()) { + case MachineOperand::MO_VirtualRegister: + if (Value *V = MO.getVRegValueOrNull()) { + O << "<" << V->getName() << ">"; + return; + } + // FALLTHROUGH + case MachineOperand::MO_MachineRegister: + case MachineOperand::MO_CCRegister: + O << LowercaseString(RI.get(MO.getReg()).Name); + return; + + case MachineOperand::MO_SignExtendedImmed: + case MachineOperand::MO_UnextendedImmed: + std::cerr << "printOp() does not handle immediate values\n"; + abort(); + return; + + case MachineOperand::MO_PCRelativeDisp: + std::cerr << "Shouldn't use addPCDisp() when building PPC MachineInstrs"; + abort(); + return; + + case MachineOperand::MO_MachineBasicBlock: { + MachineBasicBlock *MBBOp = MO.getMachineBasicBlock(); + O << "$LBB" << Mang->getValueName(MBBOp->getParent()->getFunction()) + << "_" << MBBOp->getNumber() << "\t" << CommentString << " " + << MBBOp->getBasicBlock()->getName(); + return; + } + + case MachineOperand::MO_ConstantPoolIndex: + O << "$CPI" << CurrentFnName << "_" << MO.getConstantPoolIndex(); + return; + + case MachineOperand::MO_ExternalSymbol: + O << MO.getSymbolName(); + return; + + case MachineOperand::MO_GlobalAddress: + //std::cerr << "Global Addresses? Are you kidding?\n" + //abort(); + O << Mang->getValueName(MO.getGlobal()); + return; + + default: + O << ""; + return; + } + } + + /// printMachineInstruction -- Print out a single Alpha MI to + /// the current output stream. + /// + void AlphaAsmPrinter::printMachineInstruction(const MachineInstr *MI) { + ++EmittedInsts; + if (printInstruction(MI)) + return; // Printer was automatically generated + + assert(0 && "Unhandled instruction in asm writer!"); + abort(); + return; + } + + + /// runOnMachineFunction - This uses the printMachineInstruction() + /// method to print assembly for each instruction. + /// + bool AlphaAsmPrinter::runOnMachineFunction(MachineFunction &MF) { + setupMachineFunction(MF); + O << "\n\n"; + + if (CurrentFnName.compare("main") == 0) + { + O << "\n\n#HACK\n\t.text\n\t.ent __main\n__main:\n\tret $31,($26),1\n\t.end __main\n#ENDHACK\n\n"; + } + + // Print out constants referenced by the function + printConstantPool(MF.getConstantPool()); + + // Print out labels for the function. + O << "\t.text\n"; + emitAlignment(2); + O << "\t.globl\t" << CurrentFnName << "\n"; + O << "\t.ent\t" << CurrentFnName << "\n"; + + O << CurrentFnName << ":\n"; + + // Print out code for the function. + for (MachineFunction::const_iterator I = MF.begin(), E = MF.end(); + I != E; ++I) { + // Print a label for the basic block. + O << "$LBB" << CurrentFnName << "_" << I->getNumber() << ":\t" + << CommentString << " " << I->getBasicBlock()->getName() << "\n"; + for (MachineBasicBlock::const_iterator II = I->begin(), E = I->end(); + II != E; ++II) { + // Print the assembly for the instruction. + O << "\t"; + printMachineInstruction(II); + } + } + ++LabelNumber; + + O << "\t.end\t" << CurrentFnName << "\n"; + + // We didn't modify anything. + return false; + } + + + /// printConstantPool - Print to the current output stream assembly + /// representations of the constants in the constant pool MCP. This is + /// used to print out constants which have been "spilled to memory" by + /// the code generator. + /// + void AlphaAsmPrinter::printConstantPool(MachineConstantPool *MCP) { + const std::vector &CP = MCP->getConstants(); + const TargetData &TD = TM.getTargetData(); + + if (CP.empty()) return; + + abort(); + // for (unsigned i = 0, e = CP.size(); i != e; ++i) { + // O << "\t.section\t.rodata\n"; + // emitAlignment(TD.getTypeAlignmentShift(CP[i]->getType())); + // O << ".CPI" << CurrentFnName << "_" << i << ":\t\t\t\t\t" << CommentString + // << *CP[i] << "\n"; + // //emitGlobalConstant(CP[i]); + // } + } + + bool AlphaAsmPrinter::doInitialization(Module &M) + { + AsmPrinter::doInitialization(M); + O << "\t.arch ev56\n"; + return false; + } + + + // SwitchSection - Switch to the specified section of the executable if we are + // not already in it! + // + static void SwitchSection(std::ostream &OS, std::string &CurSection, + const char *NewSection) { + if (CurSection != NewSection) { + CurSection = NewSection; + if (!CurSection.empty()) + OS << "\t" << NewSection << "\n"; + } + } + + bool AlphaAsmPrinter::doFinalization(Module &M) { + const TargetData &TD = TM.getTargetData(); + std::string CurSection; + + for (Module::const_giterator I = M.gbegin(), E = M.gend(); I != E; ++I) + if (I->hasInitializer()) { // External global require no code + O << "\n\n"; + std::string name = Mang->getValueName(I); + Constant *C = I->getInitializer(); + unsigned Size = TD.getTypeSize(C->getType()); + unsigned Align = TD.getTypeAlignmentShift(C->getType()); + + if (C->isNullValue() && + (I->hasLinkOnceLinkage() || I->hasInternalLinkage() || + I->hasWeakLinkage() /* FIXME: Verify correct */)) { + SwitchSection(O, CurSection, ".data"); + if (I->hasInternalLinkage()) + O << "\t.local " << name << "\n"; + + O << "\t.comm " << name << "," << TD.getTypeSize(C->getType()) + << "," << (1 << Align); + O << "\t\t# "; + WriteAsOperand(O, I, true, true, &M); + O << "\n"; + } else { + switch (I->getLinkage()) { + case GlobalValue::LinkOnceLinkage: + case GlobalValue::WeakLinkage: // FIXME: Verify correct for weak. + // Nonnull linkonce -> weak + O << "\t.weak " << name << "\n"; + SwitchSection(O, CurSection, ""); + O << "\t.section\t.llvm.linkonce.d." << name << ",\"aw\", at progbits\n"; + break; + case GlobalValue::AppendingLinkage: + // FIXME: appending linkage variables should go into a section of + // their name or something. For now, just emit them as external. + case GlobalValue::ExternalLinkage: + // If external or appending, declare as a global symbol + O << "\t.globl " << name << "\n"; + // FALL THROUGH + case GlobalValue::InternalLinkage: + if (C->isNullValue()) + SwitchSection(O, CurSection, ".bss"); + else + SwitchSection(O, CurSection, ".data"); + break; + case GlobalValue::GhostLinkage: + std::cerr << "GhostLinkage cannot appear in X86AsmPrinter!\n"; + abort(); + } + + emitAlignment(Align); + O << "\t.type " << name << ", at object\n"; + O << "\t.size " << name << "," << Size << "\n"; + O << name << ":\t\t\t\t# "; + WriteAsOperand(O, I, true, true, &M); + O << " = "; + WriteAsOperand(O, C, false, false, &M); + O << "\n"; + emitGlobalConstant(C); + } + } + + AsmPrinter::doFinalization(M); + return false; + } Index: llvm/lib/Target/Alpha/AlphaISelPattern.cpp diff -c /dev/null llvm/lib/Target/Alpha/AlphaISelPattern.cpp:1.1 *** /dev/null Sat Jan 22 17:42:10 2005 --- llvm/lib/Target/Alpha/AlphaISelPattern.cpp Sat Jan 22 17:41:55 2005 *************** *** 0 **** --- 1,797 ---- + //===-- AlphaISelPattern.cpp - A pattern matching inst selector for Alpha -----===// + // + // The LLVM Compiler Infrastructure + // + // This file was developed by the LLVM research group and is distributed under + // the University of Illinois Open Source License. See LICENSE.TXT for details. + // + //===----------------------------------------------------------------------===// + // + // This file defines a pattern matching instruction selector for Alpha. + // + //===----------------------------------------------------------------------===// + + #include "Alpha.h" + //#include "X86InstrBuilder.h" + #include "AlphaRegisterInfo.h" + #include "llvm/Constants.h" // FIXME: REMOVE + #include "llvm/Function.h" + #include "llvm/CodeGen/MachineInstrBuilder.h" + #include "llvm/CodeGen/MachineConstantPool.h" // FIXME: REMOVE + #include "llvm/CodeGen/MachineFunction.h" + #include "llvm/CodeGen/MachineFrameInfo.h" + #include "llvm/CodeGen/SelectionDAG.h" + #include "llvm/CodeGen/SelectionDAGISel.h" + #include "llvm/CodeGen/SSARegMap.h" + #include "llvm/Target/TargetData.h" + #include "llvm/Target/TargetLowering.h" + #include "llvm/Support/MathExtras.h" + #include "llvm/ADT/Statistic.h" + #include + using namespace llvm; + + //===----------------------------------------------------------------------===// + // AlphaTargetLowering - Alpha Implementation of the TargetLowering interface + namespace { + class AlphaTargetLowering : public TargetLowering { + int VarArgsFrameIndex; // FrameIndex for start of varargs area. + unsigned GP; //GOT vreg + public: + AlphaTargetLowering(TargetMachine &TM) : TargetLowering(TM) { + // Set up the TargetLowering object. + addRegisterClass(MVT::i64, Alpha::GPRCRegisterClass); + addRegisterClass(MVT::f64, Alpha::FPRCRegisterClass); + + setOperationAction(ISD::EXTLOAD , MVT::i1 , Expand); + setOperationAction(ISD::EXTLOAD , MVT::i8 , Expand); + setOperationAction(ISD::EXTLOAD , MVT::i16 , Expand); + setOperationAction(ISD::ZEXTLOAD , MVT::i1 , Expand); + setOperationAction(ISD::ZEXTLOAD , MVT::i8 , Expand); + setOperationAction(ISD::ZEXTLOAD , MVT::i16 , Expand); + setOperationAction(ISD::ZEXTLOAD , MVT::i32 , Expand); + setOperationAction(ISD::SEXTLOAD , MVT::i1 , Expand); + setOperationAction(ISD::SEXTLOAD , MVT::i8 , Expand); + setOperationAction(ISD::SEXTLOAD , MVT::i16 , Expand); + + computeRegisterProperties(); + + // setOperationUnsupported(ISD::MUL, MVT::i8); + // setOperationUnsupported(ISD::SELECT, MVT::i1); + // setOperationUnsupported(ISD::SELECT, MVT::i8); + + // addLegalFPImmediate(+0.0); // FLD0 + // addLegalFPImmediate(+1.0); // FLD1 + // addLegalFPImmediate(-0.0); // FLD0/FCHS + // addLegalFPImmediate(-1.0); // FLD1/FCHS + } + + /// LowerArguments - This hook must be implemented to indicate how we should + /// lower the arguments for the specified function, into the specified DAG. + virtual std::vector + LowerArguments(Function &F, SelectionDAG &DAG); + + /// LowerCallTo - This hook lowers an abstract call to a function into an + /// actual call. + virtual std::pair + LowerCallTo(SDOperand Chain, const Type *RetTy, SDOperand Callee, + ArgListTy &Args, SelectionDAG &DAG); + + virtual std::pair + LowerVAStart(SDOperand Chain, SelectionDAG &DAG); + + virtual std::pair + LowerVAArgNext(bool isVANext, SDOperand Chain, SDOperand VAList, + const Type *ArgTy, SelectionDAG &DAG); + + virtual std::pair + LowerFrameReturnAddress(bool isFrameAddr, SDOperand Chain, unsigned Depth, + SelectionDAG &DAG); + + void restoreGP(MachineBasicBlock* BB) + { + BuildMI(BB, Alpha::BIS, 2, Alpha::R29).addReg(GP).addReg(GP); + } + }; + } + + //http://www.cs.arizona.edu/computer.help/policy/DIGITAL_unix/AA-PY8AC-TET1_html/callCH3.html#BLOCK21 + + //For now, just use variable size stack frame format + + //In a standard call, the first six items are passed in registers $16 + //- $21 and/or registers $f16 - $f21. (See Section 4.1.2 for details + //of argument-to-register correspondence.) The remaining items are + //collected in a memory argument list that is a naturally aligned + //array of quadwords. In a standard call, this list, if present, must + //be passed at 0(SP). + //7 ... n 0(SP) ... (n-7)*8(SP) + + std::vector + AlphaTargetLowering::LowerArguments(Function &F, SelectionDAG &DAG) + { + std::vector ArgValues; + + // //#define FP $15 + // //#define RA $26 + // //#define PV $27 + // //#define GP $29 + // //#define SP $30 + + // assert(0 && "TODO"); + MachineFunction &MF = DAG.getMachineFunction(); + MachineFrameInfo *MFI = MF.getFrameInfo(); + + GP = MF.getSSARegMap()->createVirtualRegister(getRegClassFor(MVT::i64)); + MachineBasicBlock& BB = MF.front(); + + //Handle the return address + //BuildMI(&BB, Alpha::IDEF, 0, Alpha::R26); + + unsigned args[] = {Alpha::R16, Alpha::R17, Alpha::R18, + Alpha::R19, Alpha::R20, Alpha::R21}; + std::vector argVreg; + + int count = 0; + for (Function::aiterator I = F.abegin(), E = F.aend(); I != E; ++I) + { + ++count; + assert(count <= 6 && "More than 6 args not supported"); + assert(getValueType(I->getType()) != MVT::f64 && "No floats yet"); + BuildMI(&BB, Alpha::IDEF, 0, args[count - 1]); + argVreg.push_back(MF.getSSARegMap()->createVirtualRegister(getRegClassFor(MVT::i64))); + } + + BuildMI(&BB, Alpha::IDEF, 0, Alpha::R29); + BuildMI(&BB, Alpha::BIS, 2, GP).addReg(Alpha::R29).addReg(Alpha::R29); + count = 0; + for (Function::aiterator I = F.abegin(), E = F.aend(); I != E; ++I) + { + BuildMI(&BB, Alpha::BIS, 2, argVreg[count]).addReg(args[count]).addReg(args[count]); + + SDOperand argt, newroot; + switch (getValueType(I->getType())) + { + case MVT::i64: + argt = newroot = DAG.getCopyFromReg(argVreg[count], MVT::i64, DAG.getRoot()); + break; + case MVT::i32: + argt = newroot = DAG.getCopyFromReg(argVreg[count], MVT::i32, DAG.getRoot()); + break; + default: + newroot = DAG.getCopyFromReg(argVreg[count], MVT::i64, DAG.getRoot()); + argt = DAG.getNode(ISD::TRUNCATE, getValueType(I->getType()), newroot); + } + DAG.setRoot(newroot.getValue(1)); + ArgValues.push_back(argt); + ++count; + } + return ArgValues; + } + + std::pair + AlphaTargetLowering::LowerCallTo(SDOperand Chain, + const Type *RetTy, SDOperand Callee, + ArgListTy &Args, SelectionDAG &DAG) { + int NumBytes = 0; + Chain = DAG.getNode(ISD::ADJCALLSTACKDOWN, MVT::Other, Chain, + DAG.getConstant(NumBytes, getPointerTy())); + std::vector args_to_use; + for (unsigned i = 0, e = Args.size(); i != e; ++i) + { + switch (getValueType(Args[i].second)) { + default: assert(0 && "Unexpected ValueType for argument!"); + case MVT::i1: + case MVT::i8: + case MVT::i16: + case MVT::i32: + // Promote the integer to 64 bits. If the input type is signed use a + // sign extend, otherwise use a zero extend. + if (Args[i].second->isSigned()) + Args[i].first = DAG.getNode(ISD::SIGN_EXTEND, MVT::i64, Args[i].first); + else + Args[i].first = DAG.getNode(ISD::ZERO_EXTEND, MVT::i64, Args[i].first); + break; + case MVT::i64: + break; + } + args_to_use.push_back(Args[i].first); + } + + std::vector RetVals; + MVT::ValueType RetTyVT = getValueType(RetTy); + if (RetTyVT != MVT::isVoid) + RetVals.push_back(RetTyVT); + RetVals.push_back(MVT::Other); + + SDOperand TheCall = SDOperand(DAG.getCall(RetVals, Chain, Callee, args_to_use), 0); + Chain = TheCall.getValue(RetTyVT != MVT::isVoid); + Chain = DAG.getNode(ISD::ADJCALLSTACKUP, MVT::Other, Chain, + DAG.getConstant(NumBytes, getPointerTy())); + return std::make_pair(TheCall, Chain); + } + + std::pair + AlphaTargetLowering::LowerVAStart(SDOperand Chain, SelectionDAG &DAG) { + //vastart just returns the address of the VarArgsFrameIndex slot. + return std::make_pair(DAG.getFrameIndex(VarArgsFrameIndex, MVT::i64), Chain); + } + + std::pair AlphaTargetLowering:: + LowerVAArgNext(bool isVANext, SDOperand Chain, SDOperand VAList, + const Type *ArgTy, SelectionDAG &DAG) { + abort(); + } + + + std::pair AlphaTargetLowering:: + LowerFrameReturnAddress(bool isFrameAddress, SDOperand Chain, unsigned Depth, + SelectionDAG &DAG) { + abort(); + } + + + + + + namespace { + + //===--------------------------------------------------------------------===// + /// ISel - Alpha specific code to select Alpha machine instructions for + /// SelectionDAG operations. + /// + class ISel : public SelectionDAGISel { + + /// AlphaLowering - This object fully describes how to lower LLVM code to an + /// Alpha-specific SelectionDAG. + AlphaTargetLowering AlphaLowering; + + + /// ExprMap - As shared expressions are codegen'd, we keep track of which + /// vreg the value is produced in, so we only emit one copy of each compiled + /// tree. + std::map ExprMap; + std::set LoweredTokens; + + public: + ISel(TargetMachine &TM) : SelectionDAGISel(AlphaLowering), AlphaLowering(TM) { + } + + /// InstructionSelectBasicBlock - This callback is invoked by + /// SelectionDAGISel when it has created a SelectionDAG for us to codegen. + virtual void InstructionSelectBasicBlock(SelectionDAG &DAG) { + // Codegen the basic block. + Select(DAG.getRoot()); + + // Clear state used for selection. + ExprMap.clear(); + LoweredTokens.clear(); + } + + unsigned SelectExpr(SDOperand N); + void Select(SDOperand N); + }; + } + + unsigned ISel::SelectExpr(SDOperand N) { + unsigned Result; + unsigned Tmp1, Tmp2, Tmp3; + unsigned Opc = 0; + + SDNode *Node = N.Val; + + unsigned &Reg = ExprMap[N]; + if (Reg) return Reg; + + if (N.getOpcode() != ISD::CALL) + Reg = Result = (N.getValueType() != MVT::Other) ? + MakeReg(N.getValueType()) : 1; + else { + // If this is a call instruction, make sure to prepare ALL of the result + // values as well as the chain. + if (Node->getNumValues() == 1) + Reg = Result = 1; // Void call, just a chain. + else { + Result = MakeReg(Node->getValueType(0)); + ExprMap[N.getValue(0)] = Result; + for (unsigned i = 1, e = N.Val->getNumValues()-1; i != e; ++i) + ExprMap[N.getValue(i)] = MakeReg(Node->getValueType(i)); + ExprMap[SDOperand(Node, Node->getNumValues()-1)] = 1; + } + } + + switch (N.getOpcode()) { + default: + Node->dump(); + assert(0 && "Node not handled!\n"); + + case ISD::FrameIndex: + Tmp1 = cast(N)->getIndex(); + BuildMI(BB, Alpha::LDA, 2, Result).addImm(Tmp1 * 8).addReg(Alpha::R30); + return Result; + + case ISD::EXTLOAD: + case ISD::SEXTLOAD: + // Make sure we generate both values. + if (Result != 1) + ExprMap[N.getValue(1)] = 1; // Generate the token + else + Result = ExprMap[N.getValue(0)] = MakeReg(N.getValue(0).getValueType()); + + Select(Node->getOperand(0)); // chain + Tmp1 = SelectExpr(Node->getOperand(1)); + switch(Node->getValueType(0)) { + default: assert(0 && "Unknown type to sign extend to."); + case MVT::i64: + switch (cast(Node)->getExtraValueType()) { + default: + assert(0 && "Bad sign extend!"); + case MVT::i32: + BuildMI(BB, Alpha::LDL, 2, Result).addImm(0).addReg(Tmp1); + break; + case MVT::i16: + BuildMI(BB, Alpha::LDW, 2, Result).addImm(0).addReg(Tmp1); + break; + case MVT::i8: + BuildMI(BB, Alpha::LDB, 2, Result).addImm(0).addReg(Tmp1); + break; + } + break; + } + return Result; + + case ISD::GlobalAddress: + AlphaLowering.restoreGP(BB); + BuildMI(BB, Alpha::LOAD_ADDR, 1, Result) + .addGlobalAddress(cast(N)->getGlobal()); + return Result; + + case ISD::CALL: + { + Select(N.getOperand(0)); + + // The chain for this call is now lowered. + ExprMap.insert(std::make_pair(N.getValue(Node->getNumValues()-1), 1)); + + //grab the arguments + std::vector argvregs; + assert(Node->getNumOperands() < 8 && "Only 6 args supported"); + for(int i = 2, e = Node->getNumOperands(); i < e; ++i) + { + argvregs.push_back(SelectExpr(N.getOperand(i))); + } + for(int i = 0, e = argvregs.size(); i < e; ++i) + { + unsigned args[] = {Alpha::R16, Alpha::R17, Alpha::R18, + Alpha::R19, Alpha::R20, Alpha::R21}; + + BuildMI(BB, Alpha::BIS, 2, args[i]).addReg(argvregs[i]).addReg(argvregs[i]); + } + + //build the right kind of call + if (GlobalAddressSDNode *GASD = + dyn_cast(N.getOperand(1))) + { + Select(N.getOperand(0)); + AlphaLowering.restoreGP(BB); + BuildMI(BB, Alpha::CALL, 1).addGlobalAddress(GASD->getGlobal(),true); + } + else if (ExternalSymbolSDNode *ESSDN = + dyn_cast(N.getOperand(1))) + { + Select(N.getOperand(0)); + AlphaLowering.restoreGP(BB); + BuildMI(BB, Alpha::CALL, 0).addExternalSymbol(ESSDN->getSymbol(), true); + } + else { + Select(N.getOperand(0)); + Tmp1 = SelectExpr(N.getOperand(1)); + BuildMI(BB, Alpha::CALL, 1).addReg(Tmp1); + AlphaLowering.restoreGP(BB); + } + + //push the result into a virtual register + // if (Result != 1) + // BuildMI(BB, Alpha::BIS, 2, Result).addReg(Alpha::R0).addReg(Alpha::R0); + + switch (Node->getValueType(0)) { + default: assert(0 && "Unknown value type for call result!"); + case MVT::Other: return 1; + case MVT::i1: + case MVT::i8: + case MVT::i16: + case MVT::i32: + case MVT::i64: + BuildMI(BB, Alpha::BIS, 2, Result).addReg(Alpha::R0).addReg(Alpha::R0); + break; + } + return Result+N.ResNo; + } + + case ISD::SIGN_EXTEND: + { + std::cerr << "DestT: " << N.getValueType() << "\n"; + std::cerr << "SrcT: " << N.getOperand(0).getValueType() << "\n"; + assert(0 && "Sign Extend not there yet"); + return Result; + } + case ISD::SIGN_EXTEND_INREG: + { + Tmp1 = SelectExpr(N.getOperand(0)); + MVTSDNode* MVN = dyn_cast(Node); + std::cerr << "SrcT: " << MVN->getExtraValueType() << "\n"; + switch(MVN->getExtraValueType()) + { + default: + assert(0 && "Sign Extend InReg not there yet"); + break; + case MVT::i32: + { + Tmp2 = MakeReg(MVT::i64); + unsigned Tmp3 = MakeReg(MVT::i64); + BuildMI(BB, Alpha::LOAD_IMM, 1, Tmp2).addImm(16); + BuildMI(BB, Alpha::SL, 2, Tmp3).addReg(Tmp1).addReg(Tmp2); + BuildMI(BB, Alpha::SRA, 2, Result).addReg(Tmp3).addReg(Tmp2); + break; + } + case MVT::i16: + BuildMI(BB, Alpha::SEXTW, 1, Result).addReg(Tmp1); + break; + case MVT::i8: + BuildMI(BB, Alpha::SEXTB, 1, Result).addReg(Tmp1); + break; + } + return Result; + } + case ISD::ZERO_EXTEND_INREG: + { + Tmp1 = SelectExpr(N.getOperand(0)); + MVTSDNode* MVN = dyn_cast(Node); + std::cerr << "SrcT: " << MVN->getExtraValueType() << "\n"; + switch(MVN->getExtraValueType()) + { + default: + assert(0 && "Zero Extend InReg not there yet"); + break; + case MVT::i32: + { + Tmp2 = MakeReg(MVT::i64); + BuildMI(BB, Alpha::LOAD_IMM, 1, Tmp2).addImm(0xf0); + BuildMI(BB, Alpha::ZAP, 2, Result).addReg(Tmp1).addReg(Tmp2); + break; + } + case MVT::i16: + Tmp2 = MakeReg(MVT::i64); + BuildMI(BB, Alpha::LOAD_IMM, 1, Tmp2).addImm(0xfc); + BuildMI(BB, Alpha::ZAP, 2, Result).addReg(Tmp1).addReg(Tmp2); + break; + case MVT::i8: + Tmp2 = MakeReg(MVT::i64); + BuildMI(BB, Alpha::LOAD_IMM, 1, Tmp2).addImm(0xfe); + BuildMI(BB, Alpha::ZAP, 2, Result).addReg(Tmp1).addReg(Tmp2); + break; + } + return Result; + } + + case ISD::SETCC: + Tmp1 = SelectExpr(N.getOperand(0)); + Tmp2 = SelectExpr(N.getOperand(1)); + if (SetCCSDNode *SetCC = dyn_cast(Node)) { + if (MVT::isInteger(SetCC->getOperand(0).getValueType())) { + switch (SetCC->getCondition()) { + default: assert(0 && "Unknown integer comparison!"); + case ISD::SETEQ: + BuildMI(BB, Alpha::CMPEQ, 2, Result).addReg(Tmp1).addReg(Tmp2); + break; + case ISD::SETGT: + BuildMI(BB, Alpha::CMPLT, 2, Result).addReg(Tmp2).addReg(Tmp1); + break; + case ISD::SETGE: + BuildMI(BB, Alpha::CMPLE, 2, Result).addReg(Tmp2).addReg(Tmp1); + break; + case ISD::SETLT: + BuildMI(BB, Alpha::CMPLT, 2, Result).addReg(Tmp1).addReg(Tmp2); + break; + case ISD::SETLE: + BuildMI(BB, Alpha::CMPLE, 2, Result).addReg(Tmp1).addReg(Tmp2); + break; + case ISD::SETNE: + { + unsigned Tmp3 = MakeReg(MVT::i64); + BuildMI(BB, Alpha::CMPEQ, 2, Tmp3).addReg(Tmp1).addReg(Tmp2); + BuildMI(BB, Alpha::CMPEQ, 2, Result).addReg(Tmp3).addReg(Alpha::R31); + break; + } + case ISD::SETULT: + BuildMI(BB, Alpha::CMPULT, 2, Result).addReg(Tmp1).addReg(Tmp2); + break; + case ISD::SETUGT: + BuildMI(BB, Alpha::CMPULT, 2, Result).addReg(Tmp2).addReg(Tmp1); + break; + case ISD::SETULE: + BuildMI(BB, Alpha::CMPULE, 2, Result).addReg(Tmp1).addReg(Tmp2); + break; + case ISD::SETUGE: + BuildMI(BB, Alpha::CMPULE, 2, Result).addReg(Tmp2).addReg(Tmp1); + break; + } + } + else + assert(0 && "only integer"); + } + else + assert(0 && "Not a setcc in setcc"); + + return Result; + + case ISD::CopyFromReg: + { + if (Result == 1) + Result = ExprMap[N.getValue(0)] = MakeReg(N.getValue(0).getValueType()); + + SDOperand Chain = N.getOperand(0); + + Select(Chain); + unsigned r = dyn_cast(Node)->getReg(); + //std::cerr << "CopyFromReg " << Result << " = " << r << "\n"; + BuildMI(BB, Alpha::BIS, 2, Result).addReg(r).addReg(r); + return Result; + } + + case ISD::ADD: + Tmp1 = SelectExpr(N.getOperand(0)); + Tmp2 = SelectExpr(N.getOperand(1)); + BuildMI(BB, Alpha::ADDQ, 2, Result).addReg(Tmp1).addReg(Tmp2); + return Result; + case ISD::SUB: + Tmp1 = SelectExpr(N.getOperand(0)); + Tmp2 = SelectExpr(N.getOperand(1)); + BuildMI(BB, Alpha::SUBQ, 2, Result).addReg(Tmp1).addReg(Tmp2); + return Result; + + case ISD::AND: + Tmp1 = SelectExpr(N.getOperand(0)); + Tmp2 = SelectExpr(N.getOperand(1)); + BuildMI(BB, Alpha::AND, 2, Result).addReg(Tmp1).addReg(Tmp2); + return Result; + case ISD::OR: + Tmp1 = SelectExpr(N.getOperand(0)); + Tmp2 = SelectExpr(N.getOperand(1)); + BuildMI(BB, Alpha::BIS, 2, Result).addReg(Tmp1).addReg(Tmp2); + return Result; + case ISD::XOR: + Tmp1 = SelectExpr(N.getOperand(0)); + Tmp2 = SelectExpr(N.getOperand(1)); + BuildMI(BB, Alpha::XOR, 2, Result).addReg(Tmp1).addReg(Tmp2); + return Result; + + case ISD::MUL: + Tmp1 = SelectExpr(N.getOperand(0)); + Tmp2 = SelectExpr(N.getOperand(1)); + BuildMI(BB, Alpha::MULQ, 2, Result).addReg(Tmp1).addReg(Tmp2); + return Result; + case ISD::UREM: + Tmp1 = SelectExpr(N.getOperand(0)); + Tmp2 = SelectExpr(N.getOperand(1)); + BuildMI(BB, Alpha::REMQU, 2, Result).addReg(Tmp1).addReg(Tmp2); + return Result; + + case ISD::SELECT: + { + Tmp2 = SelectExpr(N.getOperand(1)); //Use if TRUE + Tmp3 = SelectExpr(N.getOperand(2)); //Use if FALSE + Tmp1 = SelectExpr(N.getOperand(0)); //Cond + // Get the condition into the zero flag. + unsigned dummy = MakeReg(MVT::i64); + BuildMI(BB, Alpha::BIS, 2, dummy).addReg(Tmp3).addReg(Tmp3); + BuildMI(BB, Alpha::CMOVEQ, 2, Result).addReg(Tmp2).addReg(Tmp1); + return Result; + } + + case ISD::SHL: + Tmp1 = SelectExpr(N.getOperand(0)); + Tmp2 = SelectExpr(N.getOperand(1)); + BuildMI(BB, Alpha::SL, 2, Result).addReg(Tmp1).addReg(Tmp2); + return Result; + case ISD::SRL: + Tmp1 = SelectExpr(N.getOperand(0)); + Tmp2 = SelectExpr(N.getOperand(1)); + BuildMI(BB, Alpha::SRL, 1, Result).addReg(Tmp1).addReg(Tmp2); + return Result; + case ISD::SRA: + Tmp1 = SelectExpr(N.getOperand(0)); + Tmp2 = SelectExpr(N.getOperand(1)); + BuildMI(BB, Alpha::SRA, 2, Result).addReg(Tmp1).addReg(Tmp2); + return Result; + + case ISD::Constant: + { + long val = cast(N)->getValue(); + BuildMI(BB, Alpha::LOAD_IMM, 1, Result).addImm(val); + return Result; + } + + + + case ISD::LOAD: + { + // Make sure we generate both values. + if (Result != 1) + ExprMap[N.getValue(1)] = 1; // Generate the token + else + Result = ExprMap[N.getValue(0)] = MakeReg(N.getValue(0).getValueType()); + + SDOperand Chain = N.getOperand(0); + SDOperand Address = N.getOperand(1); + + if (Address.getOpcode() == ISD::GlobalAddress) + { + Select(Chain); + AlphaLowering.restoreGP(BB); + BuildMI(BB, Alpha::LOAD, 1, Result).addGlobalAddress(cast(Address)->getGlobal()); + } + else + { + Select(Chain); + Tmp2 = SelectExpr(Address); + BuildMI(BB, Alpha::LDQ, 2, Result).addImm(0).addReg(Tmp2); + } + return Result; + } + } + + return 0; + } + + void ISel::Select(SDOperand N) { + unsigned Tmp1, Tmp2, Opc; + + // FIXME: Disable for our current expansion model! + if (/*!N->hasOneUse() &&*/ !LoweredTokens.insert(N).second) + return; // Already selected. + + SDNode *Node = N.Val; + + switch (N.getOpcode()) { + + default: + Node->dump(); std::cerr << "\n"; + assert(0 && "Node not handled yet!"); + + case ISD::BRCOND: { + MachineBasicBlock *Dest = + cast(N.getOperand(2))->getBasicBlock(); + + Select(N.getOperand(0)); + Tmp1 = SelectExpr(N.getOperand(1)); + BuildMI(BB, Alpha::BNE, 2).addReg(Tmp1).addMBB(Dest); + return; + } + + case ISD::BR: { + MachineBasicBlock *Dest = + cast(N.getOperand(1))->getBasicBlock(); + + Select(N.getOperand(0)); + BuildMI(BB, Alpha::BR, 1, Alpha::R31).addMBB(Dest); + return; + } + + case ISD::ImplicitDef: + Select(N.getOperand(0)); + BuildMI(BB, Alpha::IDEF, 0, cast(N)->getReg()); + return; + + case ISD::EntryToken: return; // Noop + + case ISD::TokenFactor: + for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) + Select(Node->getOperand(i)); + + //N.Val->dump(); std::cerr << "\n"; + //assert(0 && "Node not handled yet!"); + + return; + + case ISD::CopyToReg: + Select(N.getOperand(0)); + Tmp1 = SelectExpr(N.getOperand(1)); + Tmp2 = cast(N)->getReg(); + + if (Tmp1 != Tmp2) { + BuildMI(BB, Alpha::BIS, 2, Tmp2).addReg(Tmp1).addReg(Tmp1); + } + return; + + case ISD::RET: + switch (N.getNumOperands()) { + default: + std::cerr << N.getNumOperands() << "\n"; + for (unsigned i = 0; i < N.getNumOperands(); ++i) + std::cerr << N.getOperand(i).getValueType() << "\n"; + assert(0 && "Unknown return instruction!"); + case 2: + Select(N.getOperand(0)); + Tmp1 = SelectExpr(N.getOperand(1)); + switch (N.getOperand(1).getValueType()) { + default: assert(0 && "All other types should have been promoted!!"); + case MVT::i64: + BuildMI(BB, Alpha::BIS, 2, Alpha::R0).addReg(Tmp1).addReg(Tmp1); + break; + } + break; + case 1: + Select(N.getOperand(0)); + break; + } + //Tmp2 = AlphaLowering.getRetAddr(); + //BuildMI(BB, Alpha::BIS, 2, Alpha::R26).addReg(Tmp2).addReg(Tmp2); + BuildMI(BB, Alpha::RETURN, 0); // Just emit a 'ret' instruction + return; + + case ISD::STORE: + Select(N.getOperand(0)); + Tmp1 = SelectExpr(N.getOperand(1)); //value + if (N.getOperand(2).getOpcode() == ISD::GlobalAddress) + { + AlphaLowering.restoreGP(BB); + BuildMI(BB, Alpha::STORE, 2).addReg(Tmp1).addGlobalAddress(cast(N.getOperand(2))->getGlobal()); + } + else + { + Tmp2 = SelectExpr(N.getOperand(2)); //address + BuildMI(BB, Alpha::STQ, 3).addReg(Tmp1).addImm(0).addReg(Tmp2); + } + return; + + case ISD::EXTLOAD: + case ISD::SEXTLOAD: + case ISD::ZEXTLOAD: + case ISD::LOAD: + case ISD::CopyFromReg: + case ISD::CALL: + // case ISD::DYNAMIC_STACKALLOC: + SelectExpr(N); + return; + + + case ISD::TRUNCSTORE: { // truncstore chain, val, ptr :storety + MVT::ValueType StoredTy = cast(Node)->getExtraValueType(); + assert(StoredTy != MVT::i64 && "Unsupported TRUNCSTORE for this target!"); + + Select(N.getOperand(0)); + Tmp1 = SelectExpr(N.getOperand(1)); + Tmp2 = SelectExpr(N.getOperand(2)); + + switch (StoredTy) { + default: assert(0 && "Unhandled Type"); break; + case MVT::i8: Opc = Alpha::STB; break; + case MVT::i16: Opc = Alpha::STW; break; + case MVT::i32: Opc = Alpha::STL; break; + } + + BuildMI(BB, Opc, 2).addReg(Tmp1).addImm(0).addReg(Tmp2); + return; + } + + case ISD::ADJCALLSTACKDOWN: + case ISD::ADJCALLSTACKUP: + Select(N.getOperand(0)); + Tmp1 = cast(N.getOperand(1))->getValue(); + + Opc = N.getOpcode() == ISD::ADJCALLSTACKDOWN ? Alpha::ADJUSTSTACKDOWN : + Alpha::ADJUSTSTACKUP; + BuildMI(BB, Opc, 1).addImm(Tmp1); + return; + } + assert(0 && "Should not be reached!"); + } + + + /// createAlphaPatternInstructionSelector - This pass converts an LLVM function + /// into a machine code representation using pattern matching and a machine + /// description file. + /// + FunctionPass *llvm::createAlphaPatternInstructionSelector(TargetMachine &TM) { + return new ISel(TM); + } Index: llvm/lib/Target/Alpha/AlphaInstrFormats.td diff -c /dev/null llvm/lib/Target/Alpha/AlphaInstrFormats.td:1.1 *** /dev/null Sat Jan 22 17:42:10 2005 --- llvm/lib/Target/Alpha/AlphaInstrFormats.td Sat Jan 22 17:41:55 2005 *************** *** 0 **** --- 1,109 ---- + //===- AlphaInstrFormats.td - Alpha Instruction Formats --*- tablegen -*-=// + // + // The LLVM Compiler Infrastructure + // + // This file was developed by the LLVM research group and is distributed under + // the University of Illinois Open Source License. See LICENSE.TXT for details. + // + //===----------------------------------------------------------------------===// + // + // + //===----------------------------------------------------------------------===// + + //3.3: + //Memory + //Branch + //Operate + //Floating-point + //PALcode + + //===----------------------------------------------------------------------===// + // Instruction format superclass + //===----------------------------------------------------------------------===// + + class InstAlpha op, dag OL, string asmstr> : Instruction { // Alpha instruction baseline + field bits<32> Inst; + // let Name = asmstr; + let Namespace = "Alpha"; + let OperandList = OL; + let AsmString = asmstr; + + + let Inst{31-26} = op; + } + + //3.3.1 + class MForm opcode, dag OL, string asmstr> : InstAlpha { + bits<5> Ra; + bits<5> Rb; + bits<16> disp; + + let Inst{25-21} = Ra; + let Inst{20-16} = Rb; + let Inst{15-0} = disp; + } + + //3.3.2 + let isBranch = 1, isTerminator = 1 in + class BForm opcode, dag OL, string asmstr> : InstAlpha { + bits<5> Ra; + bits<21> disp; + + let Inst{25-21} = Ra; + let Inst{20-0} = disp; + } + + //3.3.3 + class OForm opcode, bits<7> fun, dag OL, string asmstr> : InstAlpha { + bits<5> Ra; + bits<5> Rb; + bits<3> SBZ; + bits<7> Function = fun; + bits<5> Rc; + + let Inst{25-21} = Ra; + let Inst{20-16} = Rb; + let Inst{15-13} = SBZ; + let Inst{12} = 0; + let Inst{11-5} = Function; + let Inst{4-0} = Rc; + } + + + class OFormL opcode, dag OL, string asmstr> : InstAlpha { + bits<5> Ra; + bits<8> LIT; + bits<7> Function; + bits<5> Rc; + + let Inst{25-21} = Ra; + let Inst{20-13} = LIT; + let Inst{12} = 1; + let Inst{11-5} = Function; + let Inst{4-0} = Rc; + } + + //3.3.4 + class FPForm opcode, dag OL, string asmstr> : InstAlpha { + bits<5> Fa; + bits<5> Fb; + bits<11> Function; + bits<5> Fc; + + let Inst{25-21} = Fa; + let Inst{20-16} = Fb; + let Inst{15-5} = Function; + let Inst{4-0} = Fc; + } + + //3.3.5 + class PALForm opcode, dag OL, string asmstr> : InstAlpha { + bits<26> Function; + + let Inst{25-0} = Function; + } + + + // Pseudo instructions. + class PseudoInstAlpha : InstAlpha<0, OL, nm> { + } Index: llvm/lib/Target/Alpha/AlphaInstrInfo.cpp diff -c /dev/null llvm/lib/Target/Alpha/AlphaInstrInfo.cpp:1.1 *** /dev/null Sat Jan 22 17:42:10 2005 --- llvm/lib/Target/Alpha/AlphaInstrInfo.cpp Sat Jan 22 17:41:55 2005 *************** *** 0 **** --- 1,43 ---- + //===- AlphaInstrInfo.cpp - Alpha Instruction Information ---*- C++ -*-===// + // + // The LLVM Compiler Infrastructure + // + // This file was developed by the LLVM research group and is distributed under + // the University of Illinois Open Source License. See LICENSE.TXT for details. + // + //===----------------------------------------------------------------------===// + // + // This file contains the Alpha implementation of the TargetInstrInfo class. + // + //===----------------------------------------------------------------------===// + + #include "Alpha.h" + #include "AlphaInstrInfo.h" + #include "AlphaGenInstrInfo.inc" + #include "llvm/CodeGen/MachineInstrBuilder.h" + #include + using namespace llvm; + + AlphaInstrInfo::AlphaInstrInfo() + : TargetInstrInfo(AlphaInsts, sizeof(AlphaInsts)/sizeof(AlphaInsts[0])) { } + + + bool AlphaInstrInfo::isMoveInstr(const MachineInstr& MI, + unsigned& sourceReg, + unsigned& destReg) const { + //assert(0 && "TODO"); + MachineOpCode oc = MI.getOpcode(); + if (oc == Alpha::BIS) { // or r1, r2, r2 + assert(MI.getNumOperands() == 3 && + MI.getOperand(0).isRegister() && + MI.getOperand(1).isRegister() && + MI.getOperand(2).isRegister() && + "invalid Alpha BIS instruction!"); + if (MI.getOperand(1).getReg() == MI.getOperand(2).getReg()) { + sourceReg = MI.getOperand(1).getReg(); + destReg = MI.getOperand(0).getReg(); + return true; + } + } + return false; + } Index: llvm/lib/Target/Alpha/AlphaInstrInfo.h diff -c /dev/null llvm/lib/Target/Alpha/AlphaInstrInfo.h:1.1 *** /dev/null Sat Jan 22 17:42:10 2005 --- llvm/lib/Target/Alpha/AlphaInstrInfo.h Sat Jan 22 17:41:55 2005 *************** *** 0 **** --- 1,42 ---- + //===- AlphaInstrInfo.h - Alpha Instruction Information -----*- C++ -*-===// + // + // The LLVM Compiler Infrastructure + // + // This file was developed by the LLVM research group and is distributed under + // the University of Illinois Open Source License. See LICENSE.TXT for details. + // + //===----------------------------------------------------------------------===// + // + // This file contains the Alpha implementation of the TargetInstrInfo class. + // + //===----------------------------------------------------------------------===// + + #ifndef ALPHAINSTRUCTIONINFO_H + #define ALPHAINSTRUCTIONINFO_H + + #include "llvm/Target/TargetInstrInfo.h" + #include "AlphaRegisterInfo.h" + + namespace llvm { + + class AlphaInstrInfo : public TargetInstrInfo { + const AlphaRegisterInfo RI; + public: + AlphaInstrInfo(); + + /// getRegisterInfo - TargetInstrInfo is a superset of MRegister info. As + /// such, whenever a client has an instance of instruction info, it should + /// always be able to get register info as well (through this method). + /// + virtual const MRegisterInfo &getRegisterInfo() const { return RI; } + + /// Return true if the instruction is a register to register move and + /// leave the source and dest operands in the passed parameters. + /// + virtual bool isMoveInstr(const MachineInstr &MI, + unsigned &SrcReg, unsigned &DstReg) const; + }; + + } + + #endif Index: llvm/lib/Target/Alpha/AlphaInstrInfo.td diff -c /dev/null llvm/lib/Target/Alpha/AlphaInstrInfo.td:1.1 *** /dev/null Sat Jan 22 17:42:10 2005 --- llvm/lib/Target/Alpha/AlphaInstrInfo.td Sat Jan 22 17:41:55 2005 *************** *** 0 **** --- 1,295 ---- + //===- AlphaInstrInfo.td - The Alpha Instruction Set -----*- tablegen -*-=// + // + // The LLVM Compiler Infrastructure + // + // This file was developed by the LLVM research group and is distributed under + // the University of Illinois Open Source License. See LICENSE.TXT for details. + // + //===----------------------------------------------------------------------===// + // + // + //===----------------------------------------------------------------------===// + + include "AlphaInstrFormats.td" + + // //#define FP $15 + // //#define RA $26 + // //#define PV $27 + // //#define GP $29 + // //#define SP $30 + + def s14imm : Operand; + def s16imm : Operand; + def s21imm : Operand; + def s64imm : Operand; + + def PHI : PseudoInstAlpha<(ops ), "#phi">; + def IDEF : PseudoInstAlpha<(ops ), "#idef">; + def WTF : PseudoInstAlpha<(ops ), "#wtf">; + def ADJUSTSTACKUP : PseudoInstAlpha<(ops ), "ADJUP">; + def ADJUSTSTACKDOWN : PseudoInstAlpha<(ops ), "ADJDOWN">; + + //***************** + //These are shortcuts, the assembler expands them + //***************** + //AT = R28 + //T0-T7 = R1 - R8 + //T8-T11 = R22-R25 + + let Defs = [R29] in + let Uses = [R27] in + def LDGP : PseudoInstAlpha<(ops), "ldgp $$29, 0($$27)">; + + let isCall = 1, + Defs = [R0, R1, R2, R3, R4, R5, R6, R7, R8, R16, R17, R18, R19, R20, R21, R22, R23, R24, R25, R26, R27, R29], + Uses = [R27, R29] in + def CALL : PseudoInstAlpha< (ops s64imm:$TARGET), "jsr $TARGET">; //Jump to subroutine + + let isReturn = 1, isTerminator = 1 in + def RETURN : PseudoInstAlpha<(ops ), "ret $$31,($$26),1">; //Return from subroutine + + def LOAD_IMM : PseudoInstAlpha<(ops GPRC:$RC, s64imm:$IMM), "ldiq $RC,$IMM">; //Load Immediate Quadword + + let Uses = [R29] in + def STORE : PseudoInstAlpha<(ops GPRC:$RA, s64imm:$DISP), "stq $RA,$DISP">; //Store quadword + + let Uses = [R29] in + def LOAD_ADDR : PseudoInstAlpha<(ops GPRC:$RA, s64imm:$DISP), "lda $RA,$DISP">; //Load address + + let Uses = [R29] in + def LOAD : PseudoInstAlpha<(ops GPRC:$RA, s64imm:$DISP), "ldq $RA,$DISP">; //Load quadword + + def LDW : PseudoInstAlpha<(ops GPRC:$RA, s16imm:$DISP, GPRC:$RB), "ldw $RA,$DISP($RB)">; // Load sign-extended word + def LDB : PseudoInstAlpha<(ops GPRC:$RA, s16imm:$DISP, GPRC:$RB), "ldb $RA,$DISP($RB)">; //Load byte + + let Uses = [R28, R23, R24, R25, R26] in + def REMQU : PseudoInstAlpha<(ops GPRC:$RC, GPRC:$RA, GPRC:$RB), "remqu $RA,$RB,$RC">; //unsigned remander + + //*********************** + //Real instructions + //*********************** + + //Operation Form: + def ADDL : OForm<0x10, 0x00, (ops GPRC:$RC, GPRC:$RA, GPRC:$RB), "addl $RA,$RB,$RC">; //Add longword + def ADDL_V : OForm< 0x10, 0x40, (ops GPRC:$RC, GPRC:$RA, GPRC:$RB), "ADDL/V $RA,$RB,$RC">; + def ADDQ : OForm< 0x10, 0x20, (ops GPRC:$RC, GPRC:$RA, GPRC:$RB), "addq $RA,$RB,$RC">; //Add quadword + def ADDQ_V : OForm< 0x10, 0x60, (ops GPRC:$RC, GPRC:$RA, GPRC:$RB), "ADDQ/V $RA,$RB,$RC">; + def AMASK : OForm< 0x11, 0x61, (ops GPRC:$RC, GPRC:$RA, GPRC:$RB), "AMASK $RA,$RB,$RC">; //Architecture mask + def AND : OForm< 0x11, 0x00, (ops GPRC:$RC, GPRC:$RA, GPRC:$RB), "AND $RA,$RB,$RC">; //Logical product + def BIC : OForm< 0x11, 0x08, (ops GPRC:$RC, GPRC:$RA, GPRC:$RB), "BIC $RA,$RB,$RC">; //Bit clear + def BIS : OForm<0x11, 0x20, (ops GPRC:$RC, GPRC:$RA, GPRC:$RB), "bis $RA,$RB,$RC">; //Logical sum + + //let isTwoAddress = 1 in { + def CMOVEQ : OForm< 0x11, 0x24, + (ops GPRC:$RDEST, GPRC:$RSRC, GPRC:$RCOND), + "cmoveq $RCOND,$RSRC,$RDEST">; //CMOVE if RCOND = zero + def CMOVGE : OForm< 0x11, 0x46, (ops GPRC:$RC, GPRC:$RA, GPRC:$RB), "CMOVGE $RA,$RB,$RC">; //CMOVE if ? zero + def CMOVGT : OForm<0x11, 0x66, (ops GPRC:$RC, GPRC:$RA, GPRC:$RB), "CMOVGT $RA,$RB,$RC">; //CMOVE if > zero + def CMOVLBC : OForm< 0x11, 0x16, (ops GPRC:$RC, GPRC:$RA, GPRC:$RB), "CMOVLBC $RA,$RB,$RC">; //CMOVE if low bit clear + def CMOVLBS : OForm< 0x11, 0x14, (ops GPRC:$RC, GPRC:$RA, GPRC:$RB), "CMOVLBS $RA,$RB,$RC">; //CMOVE if low bit set + def CMOVLE : OForm<0x11, 0x64, (ops GPRC:$RC, GPRC:$RA, GPRC:$RB), "CMOVLE $RA,$RB,$RC">; //CMOVE if ? zero + def CMOVLT : OForm< 0x11, 0x44, (ops GPRC:$RC, GPRC:$RA, GPRC:$RB), "CMOVLT $RA,$RB,$RC">; //CMOVE if < zero + def CMOVNE : OForm< 0x11, 0x26, + (ops GPRC:$RC, GPRC:$DUMMY, GPRC:$RA, GPRC:$RB), + "cmovne $RA,$RB,$RC">; //CMOVE if ? zero + //} + + def CMPBGE : OForm< 0x10, 0x0F, (ops GPRC:$RC, GPRC:$RA, GPRC:$RB), "CMPBGE $RA,$RB,$RC">; //Compare byte + def CMPEQ : OForm< 0x10, 0x2D, (ops GPRC:$RC, GPRC:$RA, GPRC:$RB), "CMPEQ $RA,$RB,$RC">; //Compare signed quadword equal + def CMPLE : OForm< 0x10, 0x6D, (ops GPRC:$RC, GPRC:$RA, GPRC:$RB), "CMPLE $RA,$RB,$RC">; //Compare signed quadword less than or equal + def CMPLT : OForm< 0x10, 0x4D, (ops GPRC:$RC, GPRC:$RA, GPRC:$RB), "CMPLT $RA,$RB,$RC">; //Compare signed quadword less than + def CMPULE : OForm< 0x10, 0x3D, (ops GPRC:$RC, GPRC:$RA, GPRC:$RB), "CMPULE $RA,$RB,$RC">; //Compare unsigned quadword less than or equal + def CMPULT : OForm< 0x10, 0x1D, (ops GPRC:$RC, GPRC:$RA, GPRC:$RB), "CMPULT $RA,$RB,$RC">; //Compare unsigned quadword less than + def CTLZ : OForm< 0x1C, 0x32, (ops GPRC:$RC, GPRC:$RA, GPRC:$RB), "CTLZ $RA,$RB,$RC">; //Count leading zero + def CTPOP : OForm< 0x1C, 0x30, (ops GPRC:$RC, GPRC:$RA, GPRC:$RB), "CTPOP $RA,$RB,$RC">; //Count population + def CTTZ : OForm<0x1C, 0x33, (ops GPRC:$RC, GPRC:$RA, GPRC:$RB), "CTTZ $RA,$RB,$RC">; //Count trailing zero + def EQV : OForm< 0x11, 0x48, (ops GPRC:$RC, GPRC:$RA, GPRC:$RB), "EQV $RA,$RB,$RC">; //Logical equivalence + def EXTBL : OForm< 0x12, 0x06, (ops GPRC:$RC, GPRC:$RA, GPRC:$RB), "EXTBL $RA,$RB,$RC">; //Extract byte low + def EXTLH : OForm< 0x12, 0x6A, (ops GPRC:$RC, GPRC:$RA, GPRC:$RB), "EXTLH $RA,$RB,$RC">; //Extract longword high + def EXTLL : OForm< 0x12, 0x26, (ops GPRC:$RC, GPRC:$RA, GPRC:$RB), "EXTLL $RA,$RB,$RC">; //Extract longword low + def EXTQH : OForm< 0x12, 0x7A, (ops GPRC:$RC, GPRC:$RA, GPRC:$RB), "EXTQH $RA,$RB,$RC">; //Extract quadword high + def EXTQ : OForm< 0x12, 0x36, (ops GPRC:$RC, GPRC:$RA, GPRC:$RB), "EXTQ $RA,$RB,$RC">; //Extract quadword low + def EXTWH : OForm< 0x12, 0x5A, (ops GPRC:$RC, GPRC:$RA, GPRC:$RB), "EXTWH $RA,$RB,$RC">; //Extract word high + def EXTWL : OForm< 0x12, 0x16, (ops GPRC:$RC, GPRC:$RA, GPRC:$RB), "EXTWL $RA,$RB,$RC">; //Extract word low + def IMPLVER : OForm< 0x11, 0x6C, (ops GPRC:$RC, GPRC:$RA, GPRC:$RB), "IMPLVER $RA,$RB,$RC">; //Implementation version + def INSBL : OForm< 0x12, 0x0B, (ops GPRC:$RC, GPRC:$RA, GPRC:$RB), "INSBL $RA,$RB,$RC">; //Insert byte low + def INSLH : OForm< 0x12, 0x67, (ops GPRC:$RC, GPRC:$RA, GPRC:$RB), "INSLH $RA,$RB,$RC">; //Insert longword high + def INSLL : OForm< 0x12, 0x2B, (ops GPRC:$RC, GPRC:$RA, GPRC:$RB), "INSLL $RA,$RB,$RC">; //Insert longword low + def INSQH : OForm< 0x12, 0x77, (ops GPRC:$RC, GPRC:$RA, GPRC:$RB), "INSQH $RA,$RB,$RC">; //Insert quadword high + def INSQL : OForm< 0x12, 0x3B, (ops GPRC:$RC, GPRC:$RA, GPRC:$RB), "INSQL $RA,$RB,$RC">; //Insert quadword low + def INSWH : OForm< 0x12, 0x57, (ops GPRC:$RC, GPRC:$RA, GPRC:$RB), "INSWH $RA,$RB,$RC">; //Insert word high + def INSWL : OForm< 0x12, 0x1B, (ops GPRC:$RC, GPRC:$RA, GPRC:$RB), "INSWL $RA,$RB,$RC">; //Insert word low + def MAXSB8 : OForm<0x1C, 0x3E, (ops GPRC:$RC, GPRC:$RA, GPRC:$RB), "MAXSB8 $RA,$RB,$RC">; //Vector signed byte maximum + def MAXSW4 : OForm< 0x1C, 0x3F, (ops GPRC:$RC, GPRC:$RA, GPRC:$RB), "MAXSW4 $RA,$RB,$RC">; //Vector signed word maximum + def MAXUB8 : OForm<0x1C, 0x3C, (ops GPRC:$RC, GPRC:$RA, GPRC:$RB), "MAXUB8 $RA,$RB,$RC">; //Vector unsigned byte maximum + def MAXUW4 : OForm< 0x1C, 0x3D, (ops GPRC:$RC, GPRC:$RA, GPRC:$RB), "MAXUW4 $RA,$RB,$RC">; //Vector unsigned word maximum + def MINSB8 : OForm< 0x1C, 0x38, (ops GPRC:$RC, GPRC:$RA, GPRC:$RB), "MINSB8 $RA,$RB,$RC">; //Vector signed byte minimum + def MINSW4 : OForm< 0x1C, 0x39, (ops GPRC:$RC, GPRC:$RA, GPRC:$RB), "MINSW4 $RA,$RB,$RC">; //Vector signed word minimum + def MINUB8 : OForm< 0x1C, 0x3A, (ops GPRC:$RC, GPRC:$RA, GPRC:$RB), "MINUB8 $RA,$RB,$RC">; //Vector unsigned byte minimum + def MINUW4 : OForm< 0x1C, 0x3B, (ops GPRC:$RC, GPRC:$RA, GPRC:$RB), "MINUW4 $RA,$RB,$RC">; //Vector unsigned word minimum + def MSKBL : OForm< 0x12, 0x02, (ops GPRC:$RC, GPRC:$RA, GPRC:$RB), "MSKBL $RA,$RB,$RC">; //Mask byte low + def MSKLH : OForm< 0x12, 0x62, (ops GPRC:$RC, GPRC:$RA, GPRC:$RB), "MSKLH $RA,$RB,$RC">; //Mask longword high + def MSKLL : OForm< 0x12, 0x22, (ops GPRC:$RC, GPRC:$RA, GPRC:$RB), "MSKLL $RA,$RB,$RC">; //Mask longword low + def MSKQH : OForm< 0x12, 0x72, (ops GPRC:$RC, GPRC:$RA, GPRC:$RB), "MSKQH $RA,$RB,$RC">; //Mask quadword high + def MSKQL : OForm< 0x12, 0x32, (ops GPRC:$RC, GPRC:$RA, GPRC:$RB), "MSKQL $RA,$RB,$RC">; //Mask quadword low + def MSKWH : OForm< 0x12, 0x52, (ops GPRC:$RC, GPRC:$RA, GPRC:$RB), "MSKWH $RA,$RB,$RC">; //Mask word high + def MSKWL : OForm< 0x12, 0x12, (ops GPRC:$RC, GPRC:$RA, GPRC:$RB), "MSKWL $RA,$RB,$RC">; //Mask word low + def MULL : OForm< 0x13, 0x00, (ops GPRC:$RC, GPRC:$RA, GPRC:$RB), "MULL $RA,$RB,$RC">; //Multiply longword + def MULL_V : OForm< 0x13, 0x40, (ops GPRC:$RC, GPRC:$RA, GPRC:$RB), "MULL/V $RA,$RB,$RC">; + def MULQ : OForm< 0x13, 0x20, (ops GPRC:$RC, GPRC:$RA, GPRC:$RB), "MULQ $RA,$RB,$RC">; //Multiply quadword + def MULQ_V : OForm< 0x13, 0x60, (ops GPRC:$RC, GPRC:$RA, GPRC:$RB), "MULQ/V $RA,$RB,$RC">; + def ORNOT : OForm< 0x11, 0x28, (ops GPRC:$RC, GPRC:$RA, GPRC:$RB), "ORNOT $RA,$RB,$RC">; //Logical sum with complement + def PERR : OForm< 0x1C, 0x31, (ops GPRC:$RC, GPRC:$RA, GPRC:$RB), "PERR $RA,$RB,$RC">; //Pixel error + def PKLB : OForm< 0x1C, 0x37, (ops GPRC:$RC, GPRC:$RA, GPRC:$RB), "PKLB $RA,$RB,$RC">; //Pack longwords to bytes + def PKWB : OForm<0x1C, 0x36, (ops GPRC:$RC, GPRC:$RA, GPRC:$RB), "PKWB $RA,$RB,$RC">; //Pack words to bytes + def S4ADDL : OForm< 0x10, 0x02, (ops GPRC:$RC, GPRC:$RA, GPRC:$RB), "S4ADDL $RA,$RB,$RC">; //Scaled add longword by 4 + def S4ADDQ : OForm< 0x10, 0x22, (ops GPRC:$RC, GPRC:$RA, GPRC:$RB), "S4ADDQ $RA,$RB,$RC">; //Scaled add quadword by 4 + def S4SUBL : OForm< 0x10, 0x0B, (ops GPRC:$RC, GPRC:$RA, GPRC:$RB), "S4SUBL $RA,$RB,$RC">; //Scaled subtract longword by 4 + def S4SUBQ : OForm< 0x10, 0x2B, (ops GPRC:$RC, GPRC:$RA, GPRC:$RB), "S4SUBQ $RA,$RB,$RC">; //Scaled subtract quadword by 4 + def S8ADDL : OForm< 0x10, 0x12, (ops GPRC:$RC, GPRC:$RA, GPRC:$RB), "S8ADDL $RA,$RB,$RC">; //Scaled add longword by 8 + def S8ADDQ : OForm< 0x10, 0x32, (ops GPRC:$RC, GPRC:$RA, GPRC:$RB), "S8ADDQ $RA,$RB,$RC">; //Scaled add quadword by 8 + def S8SUBL : OForm< 0x10, 0x1B, (ops GPRC:$RC, GPRC:$RA, GPRC:$RB), "S8SUBL $RA,$RB,$RC">; //Scaled subtract longword by 8 + def S8SUBQ : OForm< 0x10, 0x3B, (ops GPRC:$RC, GPRC:$RA, GPRC:$RB), "S8SUBQ $RA,$RB,$RC">; //Scaled subtract quadword by 8 + def SEXTB : OForm< 0x1C, 0x00, (ops GPRC:$RC, GPRC:$RB), "sextb $RB,$RC">; //Sign extend byte + def SEXTW : OForm< 0x1C, 0x01, (ops GPRC:$RC, GPRC:$RB), "sextw $RB,$RC">; //Sign extend word + def SL : OForm< 0x12, 0x39, (ops GPRC:$RC, GPRC:$RA, GPRC:$RB), "SLL $RA,$RB,$RC">; //Shift left logical + def SRA : OForm< 0x12, 0x3C, (ops GPRC:$RC, GPRC:$RA, GPRC:$RB), "SRA $RA,$RB,$RC">; //Shift right arithmetic + def SRL : OForm< 0x12, 0x34, (ops GPRC:$RC, GPRC:$RA, GPRC:$RB), "SRL $RA,$RB,$RC">; //Shift right logical + def SUBL : OForm< 0x10, 0x09, (ops GPRC:$RC, GPRC:$RA, GPRC:$RB), "SUBL $RA,$RB,$RC">; //Subtract longword + def SUBL_V : OForm< 0x10, 0x49, (ops GPRC:$RC, GPRC:$RA, GPRC:$RB), "SUBL/V $RA,$RB,$RC">; + def SUBQ : OForm< 0x10, 0x29, (ops GPRC:$RC, GPRC:$RA, GPRC:$RB), "SUBQ $RA,$RB,$RC">; //Subtract quadword + def SUBQ_V : OForm< 0x10, 0x69, (ops GPRC:$RC, GPRC:$RA, GPRC:$RB), "SUBQ/V $RA,$RB,$RC">; + def UMULH : OForm< 0x13, 0x30, (ops GPRC:$RC, GPRC:$RA, GPRC:$RB), "UMULH $RA,$RB,$RC">; //Unsigned multiply quadword high + def UNPKBL : OForm< 0x1C, 0x35, (ops GPRC:$RC, GPRC:$RA, GPRC:$RB), "UNPKBL $RA,$RB,$RC">; //Unpack bytes to longwords + def UNPKBW : OForm< 0x1C, 0x34, (ops GPRC:$RC, GPRC:$RA, GPRC:$RB), "UNPKBW $RA,$RB,$RC">; //Unpack bytes to words + def XOR : OForm< 0x11, 0x40, (ops GPRC:$RC, GPRC:$RA, GPRC:$RB), "XOR $RA,$RB,$RC">; //Logical difference + def ZAP : OForm< 0x12, 0x30, (ops GPRC:$RC, GPRC:$RA, GPRC:$RB), "ZAP $RA,$RB,$RC">; //Zero bytes + def ZAPNOT : OForm< 0x12, 0x31, (ops GPRC:$RC, GPRC:$RA, GPRC:$RB), "ZAPNOT $RA,$RB,$RC">; //Zero bytes not + + let isReturn = 1, isTerminator = 1 in + def RET : MForm< 0x1A, (ops GPRC:$RD, GPRC:$RS), "ret $RD,($RS),1">; //Return from subroutine + + def JMP : MForm< 0x1A, (ops GPRC:$RD, GPRC:$RS), "jmp $RD,($RS),0">; //Jump + let isCall = 1 in + let Defs = [R0, R1, R2, R3, R4, R5, R6, R7, R8, R16, R17, R18, R19, R20, R21, R22, R23, R24, R25, R27, R29] in + def JSR : MForm< 0x1A, (ops GPRC:$RD, GPRC:$RS, s14imm:$DISP), "jsr $RD,($RS),$DISP">; //Jump to subroutine + def JSR_COROUTINE : MForm< 0x1A, (ops GPRC:$RD, GPRC:$RS), "jsr_coroutine $RD,($RS),1">; //Jump to subroutine return + + def BR : BForm<0x30, (ops GPRC:$RD, s21imm:$DISP), "br $RD,$DISP">; //Branch + let isCall = 1 in + let Defs = [R0, R1, R2, R3, R4, R5, R6, R7, R8, R16, R17, R18, R19, R20, R21, R22, R23, R24, R25, R27, R29] in + def BSR : BForm<0x34, (ops GPRC:$RD, s21imm:$DISP), "bsr $RD,$DISP">; //Branch to subroutine + + def STB : MForm<0x0E, (ops GPRC:$RA, s16imm:$DISP, GPRC:$RB), "stb $RA,$DISP($RB)">; // Store byte + def STW : MForm<0x0D, (ops GPRC:$RA, s16imm:$DISP, GPRC:$RB), "stw $RA,$DISP($RB)">; // Store word + def STL : MForm<0x2C, (ops GPRC:$RA, s16imm:$DISP, GPRC:$RB), "stl $RA,$DISP($RB)">; // Store longword + def STQ : MForm<0x2D, (ops GPRC:$RA, s16imm:$DISP, GPRC:$RB), "stq $RA,$DISP($RB)">; //Store quadword + + def LDA : MForm<0x08, (ops GPRC:$RA, s16imm:$DISP, GPRC:$RB), "lda $RA,$DISP($RB)">; //Load address + + def LDL : MForm<0x28, (ops GPRC:$RA, s16imm:$DISP, GPRC:$RB), "ldq $RA,$DISP($RB)">; // Load sign-extended longword + def LDQ : MForm<0x29, (ops GPRC:$RA, s16imm:$DISP, GPRC:$RB), "ldq $RA,$DISP($RB)">; //Load quadword + + def BEQ : BForm<0x39, (ops GPRC:$RA, s21imm:$DISP), "beq $RA,$DISP">; //Branch if = zero + def BGE : BForm<0x3E, (ops GPRC:$RA, s21imm:$DISP), "bge $RA,$DISP">; //Branch if >= zero + def BGT : BForm<0x3F, (ops GPRC:$RA, s21imm:$DISP), "bgt $RA,$DISP">; //Branch if > zero + def BLBC : BForm<0x38, (ops GPRC:$RA, s21imm:$DISP), "blbc $RA,$DISP">; //Branch if low bit clear + def BLBS : BForm<0x3C, (ops GPRC:$RA, s21imm:$DISP), "blbs $RA,$DISP">; //Branch if low bit set + def BLE : BForm<0x3B, (ops GPRC:$RA, s21imm:$DISP), "ble $RA,$DISP">; //Branch if <= zero + def BLT : BForm<0x3A, (ops GPRC:$RA, s21imm:$DISP), "blt $RA,$DISP">; //Branch if < zero + def BNE : BForm<0x3D, (ops GPRC:$RA, s21imm:$DISP), "bne $RA,$DISP">; //Branch if != zero + + //Mnemonic Format Opcode Description + //ADDF F-P 15.080 Add F_floating + //ADDG F-P 15.0A0 Add G_floating + //ADDS F-P 16.080 Add S_floating + //ADDT F-P 16.0A0 Add T_floating + //CALL_PAL Pcd 00 Trap to PALcode + //ECB Mfc 18.E800 Evict cache block + //EXCB Mfc 18.0400 Exception barrier + //FETCH Mfc 18.8000 Prefetch data + //FETCH_M Mfc 18.A000 Prefetch data, modify intent + //LDAH Mem 09 Load address high + //LDBU Mem 0A Load zero-extended byte + //LDWU Mem 0C Load zero-extended word + //LDL_L Mem 2A Load sign-extended longword locked + //LDQ_L Mem 2B Load quadword locked + //LDQ_U Mem 0B Load unaligned quadword + //MB Mfc 18.4000 Memory barrier + //RC Mfc 18.E000 Read and clear + //RPCC Mfc 18.C000 Read process cycle counter + //RS Mfc 18.F000 Read and set + //STL_C Mem 2E Store longword conditional + //STQ_C Mem 2F Store quadword conditional + //STQ_U Mem 0F Store unaligned quadword + //TRAPB Mfc 18.0000 Trap barrier + //WH64 Mfc 18.F800 Write hint 64 bytes + //WMB Mfc 18.4400 Write memory barrier + + + //CMPGEQ F-P 15.0A5 Compare G_floating equal + //CMPGLE F-P 15.0A7 Compare G_floating less than or equal + //CMPGLT F-P 15.0A6 Compare G_floating less than + //CMPTEQ F-P 16.0A5 Compare T_floating equal + //CMPTLE F-P 16.0A7 Compare T_floating less than or equal + //CMPTLT F-P 16.0A6 Compare T_floating less than + //CMPTUN F-P 16.0A4 Compare T_floating unordered + //CPYS F-P 17.020 Copy sign + //CPYSE F-P 17.022 Copy sign and exponent + //CPYSN F-P 17.021 Copy sign negate + //CVTDG F-P 15.09E Convert D_floating to G_floating + //CVTGD F-P 15.0AD Convert G_floating to D_floating + //CVTGF F-P 15.0AC Convert G_floating to F_floating + //CVTGQ F-P 15.0AF Convert G_floating to quadword + //CVTLQ F-P 17.010 Convert longword to quadword + //CVTQF F-P 15.0BC Convert quadword to F_floating + //CVTQG F-P 15.0BE Convert quadword to G_floating + //CVTQL F-P 17.030 Convert quadword to longword + //CVTQS F-P 16.0BC Convert quadword to S_floating + //CVTQT F-P 16.0BE Convert quadword to T_floating + //CVTST F-P 16.2AC Convert S_floating to T_floating + //CVTTQ F-P 16.0AF Convert T_floating to quadword + //CVTTS F-P 16.0AC Convert T_floating to S_floating + //DIVF F-P 15.083 Divide F_floating + //DIVG F-P 15.0A3 Divide G_floating + //DIVS F-P 16.083 Divide S_floating + //DIVT F-P 16.0A3 Divide T_floating + //FBEQ Bra 31 Floating branch if = zero + //FBGE Bra 36 Floating branch if ? zero + //FBGT Bra 37 Floating branch if > zero + //FBLE Bra 33 Floating branch if ? zero + //FBLT Bra 32 Floating branch if < zero + //FBNE Bra 35 Floating branch if ? zero + //FCMOVEQ F-P 17.02A FCMOVE if = zero + //FCMOVGE F-P 17.02D FCMOVE if ? zero + //FCMOVGT F-P 17.02F FCMOVE if > zero + //FCMOVLE F-P 17.02E FCMOVE if ? zero + //FCMOVLT F-P 17.02C FCMOVE if < zero + //FCMOVNE F-P 17.02B FCMOVE if ? zero + //FTOIS F-P 1C.78 Floating to integer move, S_floating + //FTOIT F-P 1C.70 Floating to integer move, T_floating + //ITOFF F-P 14.014 Integer to floating move, F_floating + //ITOFS F-P 14.004 Integer to floating move, S_floating + //ITOFT F-P 14.024 Integer to floating move, T_floating + //LDF Mem 20 Load F_floating + //LDG Mem 21 Load G_floating + //LDS Mem 22 Load S_floating + //LDT Mem 23 Load T_floating + //MF_FPCR F-P 17.025 Move from FPCR + //MT_FPCR F-P 17.024 Move to FPCR + //MULF F-P 15.082 Multiply F_floating + //MULG F-P 15.0A2 Multiply G_floating + //MULS F-P 16.082 Multiply S_floating + //MULT F-P 16.0A2 Multiply T_floating + //SQRTF F-P 14.08A Square root F_floating + //SQRTG F-P 14.0AA Square root G_floating + //SQRTS F-P 14.08B Square root S_floating + //SQRTT F-P 14.0AB Square root T_floating + //STF Mem 24 Store F_floating + //STG Mem 25 Store G_floating + //STS Mem 26 Store S_floating + //STT Mem 27 Store T_floating + //SUBF F-P 15.081 Subtract F_floating + //SUBG F-P 15.0A1 Subtract G_floating + //SUBS F-P 16.081 Subtract S_floating + //SUBT F-P 16.0A1 Subtract T_floating Index: llvm/lib/Target/Alpha/AlphaRegisterInfo.cpp diff -c /dev/null llvm/lib/Target/Alpha/AlphaRegisterInfo.cpp:1.1 *** /dev/null Sat Jan 22 17:42:10 2005 --- llvm/lib/Target/Alpha/AlphaRegisterInfo.cpp Sat Jan 22 17:41:55 2005 *************** *** 0 **** --- 1,268 ---- + //===- PPC64RegisterInfo.cpp - PowerPC64 Register Information ---*- C++ -*-===// + // + // The LLVM Compiler Infrastructure + // + // This file was developed by the LLVM research group and is distributed under + // the University of Illinois Open Source License. See LICENSE.TXT for details. + // + //===----------------------------------------------------------------------===// + // + // This file contains the PowerPC64 implementation of the MRegisterInfo class. + // + //===----------------------------------------------------------------------===// + + #define DEBUG_TYPE "reginfo" + #include "Alpha.h" + #include "AlphaInstrBuilder.h" + #include "AlphaRegisterInfo.h" + #include "llvm/Constants.h" + #include "llvm/Type.h" + #include "llvm/CodeGen/ValueTypes.h" + #include "llvm/CodeGen/MachineInstrBuilder.h" + #include "llvm/CodeGen/MachineFunction.h" + #include "llvm/CodeGen/MachineFrameInfo.h" + #include "llvm/Target/TargetFrameInfo.h" + #include "llvm/Target/TargetMachine.h" + #include "llvm/Target/TargetOptions.h" + #include "llvm/Support/CommandLine.h" + #include "llvm/Support/Debug.h" + #include "llvm/ADT/STLExtras.h" + #include + #include + using namespace llvm; + + + AlphaRegisterInfo::AlphaRegisterInfo() + : AlphaGenRegisterInfo(Alpha::ADJUSTSTACKDOWN, Alpha::ADJUSTSTACKUP) + { + } + + static const TargetRegisterClass *getClass(unsigned SrcReg) { + if (Alpha::FPRCRegisterClass->contains(SrcReg)) + return Alpha::FPRCRegisterClass; + assert(Alpha::GPRCRegisterClass->contains(SrcReg) && "Reg not FPR or GPR"); + return Alpha::GPRCRegisterClass; + } + + void + AlphaRegisterInfo::storeRegToStackSlot(MachineBasicBlock &MBB, + MachineBasicBlock::iterator MI, + unsigned SrcReg, int FrameIdx) const { + std::cerr << "Trying to store " << getPrettyName(SrcReg) << " to " << FrameIdx << "\n"; + //BuildMI(MBB, MI, Alpha::WTF, 0).addReg(SrcReg); + BuildMI(MBB, MI, Alpha::STQ, 3).addReg(SrcReg).addImm(FrameIdx * 8).addReg(Alpha::R30); + // assert(0 && "TODO"); + } + + void + AlphaRegisterInfo::loadRegFromStackSlot(MachineBasicBlock &MBB, + MachineBasicBlock::iterator MI, + unsigned DestReg, int FrameIdx) const{ + std::cerr << "Trying to load " << getPrettyName(DestReg) << " to " << FrameIdx << "\n"; + //BuildMI(MBB, MI, Alpha::WTF, 0, DestReg); + BuildMI(MBB, MI, Alpha::LDQ, 2, DestReg).addImm(FrameIdx * 8).addReg(Alpha::R30); + // assert(0 && "TODO"); + } + + void AlphaRegisterInfo::copyRegToReg(MachineBasicBlock &MBB, + MachineBasicBlock::iterator MI, + unsigned DestReg, unsigned SrcReg, + const TargetRegisterClass *RC) const { + // std::cerr << "copyRegToReg " << DestReg << " <- " << SrcReg << "\n"; + if (RC == Alpha::GPRCRegisterClass) { + BuildMI(MBB, MI, Alpha::BIS, 2, DestReg).addReg(SrcReg).addReg(SrcReg); + // } else if (RC == Alpha::FPRCRegisterClass) { + // BuildMI(MBB, MI, PPC::FMR, 1, DestReg).addReg(SrcReg); + } else { + std::cerr << "Attempt to copy register that is not GPR or FPR"; + abort(); + } + } + + //===----------------------------------------------------------------------===// + // Stack Frame Processing methods + //===----------------------------------------------------------------------===// + + // hasFP - Return true if the specified function should have a dedicated frame + // pointer register. This is true if the function has variable sized allocas or + // if frame pointer elimination is disabled. + // + static bool hasFP(MachineFunction &MF) { + MachineFrameInfo *MFI = MF.getFrameInfo(); + return MFI->hasVarSizedObjects(); + } + + void AlphaRegisterInfo:: + eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB, + MachineBasicBlock::iterator I) const { + if (hasFP(MF)) { + assert(0 && "TODO"); + // If we have a frame pointer, turn the adjcallstackup instruction into a + // 'sub ESP, ' and the adjcallstackdown instruction into 'add ESP, + // ' + MachineInstr *Old = I; + unsigned Amount = Old->getOperand(0).getImmedValue(); + if (Amount != 0) { + // We need to keep the stack aligned properly. To do this, we round the + // amount of space needed for the outgoing arguments up to the next + // alignment boundary. + unsigned Align = MF.getTarget().getFrameInfo()->getStackAlignment(); + Amount = (Amount+Align-1)/Align*Align; + + MachineInstr *New; + // if (Old->getOpcode() == X86::ADJCALLSTACKDOWN) { + // New=BuildMI(X86::SUB32ri, 1, X86::ESP, MachineOperand::UseAndDef) + // .addZImm(Amount); + // } else { + // assert(Old->getOpcode() == X86::ADJCALLSTACKUP); + // New=BuildMI(X86::ADD32ri, 1, X86::ESP, MachineOperand::UseAndDef) + // .addZImm(Amount); + // } + + // Replace the pseudo instruction with a new instruction... + MBB.insert(I, New); + } + } + + MBB.erase(I); + } + + void + AlphaRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II) const { + assert(0 && "TODO"); + // unsigned i = 0; + // MachineInstr &MI = *II; + // MachineBasicBlock &MBB = *MI.getParent(); + // MachineFunction &MF = *MBB.getParent(); + + // while (!MI.getOperand(i).isFrameIndex()) { + // ++i; + // assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!"); + // } + + // int FrameIndex = MI.getOperand(i).getFrameIndex(); + + // // Replace the FrameIndex with base register with GPR1 (SP) or GPR31 (FP). + // MI.SetMachineOperandReg(i, hasFP(MF) ? PPC::R31 : PPC::R1); + + // // Take into account whether it's an add or mem instruction + // unsigned OffIdx = (i == 2) ? 1 : 2; + + // // Now add the frame object offset to the offset from r1. + // int Offset = MF.getFrameInfo()->getObjectOffset(FrameIndex) + + // MI.getOperand(OffIdx).getImmedValue(); + + // // If we're not using a Frame Pointer that has been set to the value of the + // // SP before having the stack size subtracted from it, then add the stack size + // // to Offset to get the correct offset. + // Offset += MF.getFrameInfo()->getStackSize(); + + // if (Offset > 32767 || Offset < -32768) { + // // Insert a set of r0 with the full offset value before the ld, st, or add + // MachineBasicBlock *MBB = MI.getParent(); + // MBB->insert(II, BuildMI(PPC::LIS, 1, PPC::R0).addSImm(Offset >> 16)); + // MBB->insert(II, BuildMI(PPC::ORI, 2, PPC::R0).addReg(PPC::R0) + // .addImm(Offset)); + // // convert into indexed form of the instruction + // // sth 0:rA, 1:imm 2:(rB) ==> sthx 0:rA, 2:rB, 1:r0 + // // addi 0:rA 1:rB, 2, imm ==> add 0:rA, 1:rB, 2:r0 + // unsigned NewOpcode = + // const_cast& >(ImmToIdxMap)[MI.getOpcode()]; + // assert(NewOpcode && "No indexed form of load or store available!"); + // MI.setOpcode(NewOpcode); + // MI.SetMachineOperandReg(1, MI.getOperand(i).getReg()); + // MI.SetMachineOperandReg(2, PPC::R0); + // } else { + // MI.SetMachineOperandConst(OffIdx, MachineOperand::MO_SignExtendedImmed, + // Offset); + // } + } + + + void AlphaRegisterInfo::emitPrologue(MachineFunction &MF) const { + MachineBasicBlock &MBB = MF.front(); // Prolog goes in entry BB + MachineBasicBlock::iterator MBBI = MBB.begin(); + MachineFrameInfo *MFI = MF.getFrameInfo(); + MachineInstr *MI; + + //handle GOP offset + MI = BuildMI(Alpha::LDGP, 0); + MBB.insert(MBBI, MI); + + // Get the number of bytes to allocate from the FrameInfo + unsigned NumBytes = MFI->getStackSize(); + + // Do we need to allocate space on the stack? + if (NumBytes == 0) return; + + // Add the size of R30 to NumBytes size for the store of R30 to the + // stack + // std::cerr << "Spillsize of R30 is " << getSpillSize(Alpha::R30) << "\n"; + // NumBytes = NumBytes + getSpillSize(Alpha::R30)/8; + + // Update frame info to pretend that this is part of the stack... + MFI->setStackSize(NumBytes); + + // adjust stack pointer: r30 -= numbytes + + if (NumBytes <= 32000) //FIXME: do this better + { + MI=BuildMI(Alpha::LDA, 2, Alpha::R30).addImm(-NumBytes).addReg(Alpha::R30); + MBB.insert(MBBI, MI); + } else { + std::cerr << "Too big a stack frame\n"; + abort(); + } + } + + void AlphaRegisterInfo::emitEpilogue(MachineFunction &MF, + MachineBasicBlock &MBB) const { + const MachineFrameInfo *MFI = MF.getFrameInfo(); + MachineBasicBlock::iterator MBBI = prior(MBB.end()); + MachineInstr *MI; + assert((MBBI->getOpcode() == Alpha::RET || MBBI->getOpcode() == Alpha::RETURN) && + "Can only insert epilog into returning blocks"); + + // Get the number of bytes allocated from the FrameInfo... + unsigned NumBytes = MFI->getStackSize(); + + if (NumBytes != 0) + { + if (NumBytes <= 32000) //FIXME: do this better + { + MI=BuildMI(Alpha::LDA, 2, Alpha::R30).addImm(NumBytes).addReg(Alpha::R30); + MBB.insert(MBBI, MI); + } else { + std::cerr << "Too big a stack frame\n"; + abort(); + } + } + } + + #include "AlphaGenRegisterInfo.inc" + + const TargetRegisterClass* + AlphaRegisterInfo::getRegClassForType(const Type* Ty) const { + switch (Ty->getTypeID()) { + default: assert(0 && "Invalid type to getClass!"); + case Type::BoolTyID: + case Type::SByteTyID: + case Type::UByteTyID: + case Type::ShortTyID: + case Type::UShortTyID: + case Type::IntTyID: + case Type::UIntTyID: + case Type::PointerTyID: + case Type::LongTyID: + case Type::ULongTyID: return &GPRCInstance; + + case Type::FloatTyID: + case Type::DoubleTyID: return &FPRCInstance; + } + } + + std::string AlphaRegisterInfo::getPrettyName(unsigned reg) + { + std::string s(RegisterDescriptors[reg].Name); + return s; + } Index: llvm/lib/Target/Alpha/AlphaRegisterInfo.h diff -c /dev/null llvm/lib/Target/Alpha/AlphaRegisterInfo.h:1.1 *** /dev/null Sat Jan 22 17:42:10 2005 --- llvm/lib/Target/Alpha/AlphaRegisterInfo.h Sat Jan 22 17:41:55 2005 *************** *** 0 **** --- 1,57 ---- + //===- AlphaRegisterInfo.h - Alpha Register Information Impl -*- C++ -*-==// + // + // The LLVM Compiler Infrastructure + // + // This file was developed by the LLVM research group and is distributed under + // the University of Illinois Open Source License. See LICENSE.TXT for details. + // + //===----------------------------------------------------------------------===// + // + // This file contains the Alpha implementation of the MRegisterInfo class. + // + //===----------------------------------------------------------------------===// + + #ifndef ALPHAREGISTERINFO_H + #define ALPHAREGISTERINFO_H + + #include "llvm/Target/MRegisterInfo.h" + #include "AlphaGenRegisterInfo.h.inc" + + namespace llvm { + + class Type; + + struct AlphaRegisterInfo : public AlphaGenRegisterInfo { + AlphaRegisterInfo(); + const TargetRegisterClass* getRegClassForType(const Type* Ty) const; + + /// Code Generation virtual methods... + void storeRegToStackSlot(MachineBasicBlock &MBB, + MachineBasicBlock::iterator MBBI, + unsigned SrcReg, int FrameIndex) const; + + void loadRegFromStackSlot(MachineBasicBlock &MBB, + MachineBasicBlock::iterator MBBI, + unsigned DestReg, int FrameIndex) const; + + void copyRegToReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, + unsigned DestReg, unsigned SrcReg, + const TargetRegisterClass *RC) const; + + void eliminateCallFramePseudoInstr(MachineFunction &MF, + MachineBasicBlock &MBB, + MachineBasicBlock::iterator I) const; + + void eliminateFrameIndex(MachineBasicBlock::iterator II) const; + + //void processFunctionBeforeFrameFinalized(MachineFunction &MF) const; + + void emitPrologue(MachineFunction &MF) const; + void emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const; + + static std::string getPrettyName(unsigned reg); + }; + + } // end namespace llvm + + #endif Index: llvm/lib/Target/Alpha/AlphaRegisterInfo.td diff -c /dev/null llvm/lib/Target/Alpha/AlphaRegisterInfo.td:1.1 *** /dev/null Sat Jan 22 17:42:10 2005 --- llvm/lib/Target/Alpha/AlphaRegisterInfo.td Sat Jan 22 17:41:55 2005 *************** *** 0 **** --- 1,93 ---- + //===- AlphaRegisterInfo.td - The Alpha Register File --*- tablegen -*-===// + // + // The LLVM Compiler Infrastructure + // + // This file was developed by the LLVM research group and is distributed under + // the University of Illinois Open Source License. See LICENSE.TXT for details. + // + //===----------------------------------------------------------------------===// + // + // + //===----------------------------------------------------------------------===// + + class AlphaReg : Register { + field bits<5> Num; + let Namespace = "Alpha"; + } + + // We identify all our registers with a 5-bit ID, for consistency's sake. + + // GPR - One of the 32 32-bit general-purpose registers + class GPR num, string n> : AlphaReg { + let Num = num; + } + + // FPR - One of the 32 64-bit floating-point registers + class FPR num, string n> : AlphaReg { + let Num = num; + } + + //#define FP $15 + //#define RA $26 + //#define PV $27 + //#define GP $29 + //#define SP $30 + + // General-purpose registers + def R0 : GPR< 0, "$0">; def R1 : GPR< 1, "$1">; + def R2 : GPR< 2, "$2">; def R3 : GPR< 3, "$3">; + def R4 : GPR< 4, "$4">; def R5 : GPR< 5, "$5">; + def R6 : GPR< 6, "$6">; def R7 : GPR< 7, "$7">; + def R8 : GPR< 8, "$8">; def R9 : GPR< 9, "$9">; + def R10 : GPR<10, "$10">; def R11 : GPR<11, "$11">; + def R12 : GPR<12, "$12">; def R13 : GPR<13, "$13">; + def R14 : GPR<14, "$14">; def R15 : GPR<15, "$15">; + def R16 : GPR<16, "$16">; def R17 : GPR<17, "$17">; + def R18 : GPR<18, "$18">; def R19 : GPR<19, "$19">; + def R20 : GPR<20, "$20">; def R21 : GPR<21, "$21">; + def R22 : GPR<22, "$22">; def R23 : GPR<23, "$23">; + def R24 : GPR<24, "$24">; def R25 : GPR<25, "$25">; + def R26 : GPR<26, "$26">; def R27 : GPR<27, "$27">; + def R28 : GPR<28, "$28">; def R29 : GPR<29, "$29">; + def R30 : GPR<30, "$30">; def R31 : GPR<31, "$31">; + + // Floating-point registers + def F0 : FPR< 0, "F0">; def F1 : FPR< 1, "F1">; + def F2 : FPR< 2, "F2">; def F3 : FPR< 3, "F3">; + def F4 : FPR< 4, "F4">; def F5 : FPR< 5, "F5">; + def F6 : FPR< 6, "F6">; def F7 : FPR< 7, "F7">; + def F8 : FPR< 8, "F8">; def F9 : FPR< 9, "F9">; + def F10 : FPR<10, "F10">; def F11 : FPR<11, "F11">; + def F12 : FPR<12, "F12">; def F13 : FPR<13, "F13">; + def F14 : FPR<14, "F14">; def F15 : FPR<15, "F15">; + def F16 : FPR<16, "F16">; def F17 : FPR<17, "F17">; + def F18 : FPR<18, "F18">; def F19 : FPR<19, "F19">; + def F20 : FPR<20, "F20">; def F21 : FPR<21, "F21">; + def F22 : FPR<22, "F22">; def F23 : FPR<23, "F23">; + def F24 : FPR<24, "F24">; def F25 : FPR<25, "F25">; + def F26 : FPR<26, "F26">; def F27 : FPR<27, "F27">; + def F28 : FPR<28, "F28">; def F29 : FPR<29, "F29">; + def F30 : FPR<30, "F30">; def F31 : FPR<31, "F31">; + + // //#define FP $15 + // //#define RA $26 + // //#define PV $27 + // //#define GP $29 + // //#define SP $30 + // $28 is undefined after any and all calls + + /// Register classes + def GPRC : RegisterClass; + //R28 is reserved for the assembler + + //Don't allocate 15, 29, 30, 31 + //Allocation volatiles only for now + def FPRC : RegisterClass; + + Index: llvm/lib/Target/Alpha/AlphaTargetMachine.cpp diff -c /dev/null llvm/lib/Target/Alpha/AlphaTargetMachine.cpp:1.1 *** /dev/null Sat Jan 22 17:42:10 2005 --- llvm/lib/Target/Alpha/AlphaTargetMachine.cpp Sat Jan 22 17:41:55 2005 *************** *** 0 **** --- 1,111 ---- + //===-- AlphaTargetMachine.cpp - Define TargetMachine for Alpha -------===// + // + // The LLVM Compiler Infrastructure + // + // This file was developed by the LLVM research group and is distributed under + // the University of Illinois Open Source License. See LICENSE.TXT for details. + // + //===----------------------------------------------------------------------===// + // + // + //===----------------------------------------------------------------------===// + + #include "Alpha.h" + #include "AlphaTargetMachine.h" + #include "llvm/Module.h" + #include "llvm/CodeGen/IntrinsicLowering.h" + #include "llvm/CodeGen/MachineFunction.h" + #include "llvm/CodeGen/Passes.h" + #include "llvm/Target/TargetOptions.h" + #include "llvm/Target/TargetMachineRegistry.h" + #include "llvm/Transforms/Scalar.h" + #include "llvm/Support/CommandLine.h" + #include + using namespace llvm; + + namespace { + // Register the targets + RegisterTarget X("alpha", " Alpha (incomplete)"); + } + + AlphaTargetMachine::AlphaTargetMachine( const Module &M, IntrinsicLowering *IL) + : TargetMachine("alpha", IL, true), + FrameInfo(TargetFrameInfo::StackGrowsDown, 8, 0) //TODO: check these + //JITInfo(*this) + {} + + bool AlphaTargetMachine::addPassesToEmitMachineCode(FunctionPassManager &PM, + MachineCodeEmitter &MCE) + { + assert(0 && "TODO"); + return false; + } + + + /// addPassesToEmitAssembly - Add passes to the specified pass manager + /// to implement a static compiler for this target. + /// + bool AlphaTargetMachine::addPassesToEmitAssembly(PassManager &PM, + std::ostream &Out) { + + // FIXME: Implement efficient support for garbage collection intrinsics. + PM.add(createLowerGCPass()); + + // FIXME: Implement the invoke/unwind instructions! + PM.add(createLowerInvokePass()); + + // FIXME: Implement the switch instruction in the instruction selector! + PM.add(createLowerSwitchPass()); + + PM.add(createLowerConstantExpressionsPass()); + + // Make sure that no unreachable blocks are instruction selected. + PM.add(createUnreachableBlockEliminationPass()); + + PM.add(createAlphaPatternInstructionSelector(*this)); + + if (PrintMachineCode) + PM.add(createMachineFunctionPrinterPass(&std::cerr)); + + PM.add(createRegisterAllocator()); + + if (PrintMachineCode) + PM.add(createMachineFunctionPrinterPass(&std::cerr)); + + PM.add(createPrologEpilogCodeInserter()); + + // Must run branch selection immediately preceding the asm printer + //PM.add(createAlphaBranchSelectionPass()); + + PM.add(createAlphaCodePrinterPass(Out, *this)); + + PM.add(createMachineCodeDeleter()); + return false; + } + + //void AlphaJITInfo::addPassesToJITCompile(FunctionPassManager &PM) { + // // FIXME: Implement efficient support for garbage collection intrinsics. + // PM.add(createLowerGCPass()); + + // // FIXME: Implement the invoke/unwind instructions! + // PM.add(createLowerInvokePass()); + + // // FIXME: Implement the switch instruction in the instruction selector! + // PM.add(createLowerSwitchPass()); + + // PM.add(createLowerConstantExpressionsPass()); + + // // Make sure that no unreachable blocks are instruction selected. + // PM.add(createUnreachableBlockEliminationPass()); + + // PM.add(createPPC32ISelSimple(TM)); + // PM.add(createRegisterAllocator()); + // PM.add(createPrologEpilogCodeInserter()); + + // // Must run branch selection immediately preceding the asm printer + // PM.add(createPPCBranchSelectionPass()); + + // if (PrintMachineCode) + // PM.add(createMachineFunctionPrinterPass(&std::cerr)); + //} + Index: llvm/lib/Target/Alpha/AlphaTargetMachine.h diff -c /dev/null llvm/lib/Target/Alpha/AlphaTargetMachine.h:1.1 *** /dev/null Sat Jan 22 17:42:10 2005 --- llvm/lib/Target/Alpha/AlphaTargetMachine.h Sat Jan 22 17:41:55 2005 *************** *** 0 **** --- 1,54 ---- + //===-- AlphaTargetMachine.h - Define TargetMachine for PowerPC -*- C++ -*-=// + // + // The LLVM Compiler Infrastructure + // + // This file was developed by the LLVM research group and is distributed under + // the University of Illinois Open Source License. See LICENSE.TXT for details. + // + //===----------------------------------------------------------------------===// + // + // This file declares the Alpha-specific subclass of TargetMachine. + // + //===----------------------------------------------------------------------===// + + #ifndef ALPHA_TARGETMACHINE_H + #define ALPHA_TARGETMACHINE_H + + #include "llvm/Target/TargetMachine.h" + #include "llvm/Target/TargetFrameInfo.h" + #include "llvm/PassManager.h" + #include "AlphaInstrInfo.h" + //#include "AlphaJITInfo.h" + + namespace llvm { + + class GlobalValue; + class IntrinsicLowering; + + class AlphaTargetMachine : public TargetMachine { + AlphaInstrInfo InstrInfo; + TargetFrameInfo FrameInfo; + // AlphaJITInfo JITInfo; + + public: + AlphaTargetMachine(const Module &M, IntrinsicLowering *IL); + + virtual const AlphaInstrInfo *getInstrInfo() const { return &InstrInfo; } + virtual const TargetFrameInfo *getFrameInfo() const { return &FrameInfo; } + virtual const MRegisterInfo *getRegisterInfo() const { + return &InstrInfo.getRegisterInfo(); + } + // virtual TargetJITInfo *getJITInfo() { + // return &JITInfo; + // } + + virtual bool addPassesToEmitMachineCode(FunctionPassManager &PM, + MachineCodeEmitter &MCE); + + virtual bool addPassesToEmitAssembly(PassManager &PM, std::ostream &Out); + + }; + + } // end namespace llvm + + #endif Index: llvm/lib/Target/Alpha/Makefile diff -c /dev/null llvm/lib/Target/Alpha/Makefile:1.1 *** /dev/null Sat Jan 22 17:42:10 2005 --- llvm/lib/Target/Alpha/Makefile Sat Jan 22 17:41:55 2005 *************** *** 0 **** --- 1,20 ---- + ##===- lib/Target/Alpha/Makefile -------------------------*- Makefile -*-===## + # + # The LLVM Compiler Infrastructure + # + # This file was developed by the LLVM research group and is distributed under + # the University of Illinois Open Source License. See LICENSE.TXT for details. + # + ##===----------------------------------------------------------------------===## + LEVEL = ../../.. + LIBRARYNAME = LLVMAlpha + TARGET = Alpha + SHARED_LIBRARY=1 + + # Make sure that tblgen is run, first thing. + BUILT_SOURCES = AlphaGenRegisterInfo.h.inc AlphaGenRegisterNames.inc \ + AlphaGenRegisterInfo.inc AlphaGenInstrNames.inc \ + AlphaGenInstrInfo.inc AlphaGenCodeEmitter.inc \ + AlphaGenAsmWriter.inc + + include $(LEVEL)/Makefile.common From lattner at cs.uiuc.edu Sat Jan 22 21:11:54 2005 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Sat, 22 Jan 2005 21:11:54 -0600 Subject: [llvm-commits] CVS: llvm/include/llvm/Support/FileUtilities.h Message-ID: <200501230311.j0N3BsUO017895@apoc.cs.uiuc.edu> Changes in directory llvm/include/llvm/Support: FileUtilities.h updated: 1.28 -> 1.29 --- Log message: New method. --- Diffs of the changes: (+13 -0) FileUtilities.h | 13 +++++++++++++ 1 files changed, 13 insertions(+) Index: llvm/include/llvm/Support/FileUtilities.h diff -u llvm/include/llvm/Support/FileUtilities.h:1.28 llvm/include/llvm/Support/FileUtilities.h:1.29 --- llvm/include/llvm/Support/FileUtilities.h:1.28 Thu Jan 20 17:31:35 2005 +++ llvm/include/llvm/Support/FileUtilities.h Sat Jan 22 21:11:38 2005 @@ -28,6 +28,19 @@ bool DiffFiles(const std::string &FileA, const std::string &FileB, std::string *Error = 0); +/// DiffFilesWithTolerance - Compare the two files specified, returning 0 if the +/// files match, 1 if they are different, and 2 if there is a file error. This +/// function differs from DiffFiles in that you can specify an absolete and +/// relative FP error that is allowed to exist. If you specify a string to fill +/// in for the error option, it will set the string to an error message if an +/// error occurs, allowing the caller to distinguish between a failed diff and a +/// file system error. +/// +int DiffFilesWithTolerance(const std::string &FileA, const std::string &FileB, + double AbsTol, double RelTol, + std::string *Error = 0); + + /// MoveFileOverIfUpdated - If the file specified by New is different than Old, /// or if Old does not exist, move the New file over the Old file. Otherwise, /// remove the New file. From lattner at cs.uiuc.edu Sat Jan 22 21:13:56 2005 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Sat, 22 Jan 2005 21:13:56 -0600 Subject: [llvm-commits] CVS: llvm/lib/Support/FileUtilities.cpp Message-ID: <200501230313.j0N3Duii018127@apoc.cs.uiuc.edu> Changes in directory llvm/lib/Support: FileUtilities.cpp updated: 1.35 -> 1.36 --- Log message: Add a new method, refactored out of fpcmp --- Diffs of the changes: (+184 -0) FileUtilities.cpp | 184 ++++++++++++++++++++++++++++++++++++++++++++++++++++++ 1 files changed, 184 insertions(+) Index: llvm/lib/Support/FileUtilities.cpp diff -u llvm/lib/Support/FileUtilities.cpp:1.35 llvm/lib/Support/FileUtilities.cpp:1.36 --- llvm/lib/Support/FileUtilities.cpp:1.35 Sat Jan 22 11:36:16 2005 +++ llvm/lib/Support/FileUtilities.cpp Sat Jan 22 21:13:43 2005 @@ -14,6 +14,9 @@ #include "llvm/Support/FileUtilities.h" #include "llvm/System/Path.h" +#include "llvm/System/MappedFile.h" +#include "llvm/ADT/StringExtras.h" +#include #include #include @@ -64,3 +67,184 @@ std::remove(New.c_str()); } } + +static bool isNumberChar(char C) { + switch (C) { + case '0': case '1': case '2': case '3': case '4': + case '5': case '6': case '7': case '8': case '9': + case '.': case '+': case '-': + case 'e': + case 'E': return true; + default: return false; + } +} + +static char *BackupNumber(char *Pos, char *FirstChar) { + // If we didn't stop in the middle of a number, don't backup. + if (!isNumberChar(*Pos)) return Pos; + + // Otherwise, return to the start of the number. + while (Pos > FirstChar && isNumberChar(Pos[-1])) + --Pos; + return Pos; +} + +/// CompareNumbers - compare two numbers, returning true if they are different. +static bool CompareNumbers(char *&F1P, char *&F2P, char *F1End, char *F2End, + double AbsTolerance, double RelTolerance, + std::string *ErrorMsg) { + char *F1NumEnd, *F2NumEnd; + double V1 = 0.0, V2 = 0.0; + // If we stop on numbers, compare their difference. + if (isNumberChar(*F1P) && isNumberChar(*F2P)) { + V1 = strtod(F1P, &F1NumEnd); + V2 = strtod(F2P, &F2NumEnd); + } else { + // Otherwise, the diff failed. + F1NumEnd = F1P; + F2NumEnd = F2P; + } + + if (F1NumEnd == F1P || F2NumEnd == F2P) { + if (ErrorMsg) *ErrorMsg = "Comparison failed, not a numeric difference."; + return true; + } + + // Check to see if these are inside the absolute tolerance + if (AbsTolerance < std::abs(V1-V2)) { + // Nope, check the relative tolerance... + double Diff; + if (V2) + Diff = std::abs(V1/V2 - 1.0); + else if (V1) + Diff = std::abs(V2/V1 - 1.0); + else + Diff = 0; // Both zero. + if (Diff > RelTolerance) { + if (ErrorMsg) { + *ErrorMsg = "Compared: " + ftostr(V1) + " and " + ftostr(V2) + + ": diff = " + ftostr(Diff) + "\n"; + *ErrorMsg += "Out of tolerance: rel/abs: " + ftostr(RelTolerance) + + "/" + ftostr(AbsTolerance); + } + return true; + } + } + + // Otherwise, advance our read pointers to the end of the numbers. + F1P = F1NumEnd; F2P = F2NumEnd; + return false; +} + +// PadFileIfNeeded - If the files are not identical, we will have to be doing +// numeric comparisons in here. There are bad cases involved where we (i.e., +// strtod) might run off the beginning or end of the file if it starts or ends +// with a number. Because of this, if needed, we pad the file so that it starts +// and ends with a null character. +static void PadFileIfNeeded(char *&FileStart, char *&FileEnd, char *&FP) { + if (isNumberChar(FileStart[0]) || isNumberChar(FileEnd[-1])) { + unsigned FileLen = FileEnd-FileStart; + char *NewFile = new char[FileLen+2]; + NewFile[0] = 0; // Add null padding + NewFile[FileLen+1] = 0; // Add null padding + memcpy(NewFile+1, FileStart, FileLen); + FP = NewFile+(FP-FileStart)+1; + FileStart = NewFile+1; + FileEnd = FileStart+FileLen; + } +} + +/// DiffFilesWithTolerance - Compare the two files specified, returning 0 if the +/// files match, 1 if they are different, and 2 if there is a file error. This +/// function differs from DiffFiles in that you can specify an absolete and +/// relative FP error that is allowed to exist. If you specify a string to fill +/// in for the error option, it will set the string to an error message if an +/// error occurs, allowing the caller to distinguish between a failed diff and a +/// file system error. +/// +int llvm::DiffFilesWithTolerance(const std::string &FileA, + const std::string &FileB, + double AbsTol, double RelTol, + std::string *Error) { + try { + // Map in the files into memory. + sys::MappedFile F1((sys::Path(FileA))); + sys::MappedFile F2((sys::Path(FileB))); + F1.map(); + F2.map(); + + // Okay, now that we opened the files, scan them for the first difference. + char *File1Start = F1.charBase(); + char *File2Start = F2.charBase(); + char *File1End = File1Start+F1.size(); + char *File2End = File2Start+F2.size(); + char *F1P = File1Start; + char *F2P = File2Start; + + // Scan for the end of file or first difference. + while (F1P < File1End && F2P < File2End && *F1P == *F2P) + ++F1P, ++F2P; + + // Common case: identifical files. + if (F1P == File1End && F2P == File2End) return 0; + + char *OrigFile1Start = File1Start; + char *OrigFile2Start = File2Start; + + // If the files need padding, do so now. + PadFileIfNeeded(File1Start, File1End, F1P); + PadFileIfNeeded(File2Start, File2End, F2P); + + bool CompareFailed = false; + while (1) { + // Scan for the end of file or next difference. + while (F1P < File1End && F2P < File2End && *F1P == *F2P) + ++F1P, ++F2P; + + if (F1P >= File1End || F2P >= File2End) break; + + // Okay, we must have found a difference. Backup to the start of the + // current number each stream is at so that we can compare from the + // beginning. + F1P = BackupNumber(F1P, File1Start); + F2P = BackupNumber(F2P, File2Start); + + // Now that we are at the start of the numbers, compare them, exiting if + // they don't match. + if (CompareNumbers(F1P, F2P, File1End, File2End, AbsTol, RelTol, Error)) { + CompareFailed = true; + break; + } + } + + // Okay, we reached the end of file. If both files are at the end, we + // succeeded. + bool F1AtEnd = F1P >= File1End; + bool F2AtEnd = F2P >= File2End; + if (!CompareFailed && (!F1AtEnd || !F2AtEnd)) { + // Else, we might have run off the end due to a number: backup and retry. + if (F1AtEnd && isNumberChar(F1P[-1])) --F1P; + if (F2AtEnd && isNumberChar(F2P[-1])) --F2P; + F1P = BackupNumber(F1P, File1Start); + F2P = BackupNumber(F2P, File2Start); + + // Now that we are at the start of the numbers, compare them, exiting if + // they don't match. + if (CompareNumbers(F1P, F2P, File1End, File2End, AbsTol, RelTol, Error)) + CompareFailed = true; + + // If we found the end, we succeeded. + if (F1P < File1End || F2P < File2End) + CompareFailed = true; + } + + if (OrigFile1Start != File1Start) + delete[] File1Start; + if (OrigFile2Start != File2Start) + delete[] File2Start; + return CompareFailed; + } catch (const std::string &Msg) { + if (Error) *Error = Msg; + return 2; + } +} From lattner at cs.uiuc.edu Sat Jan 22 21:16:00 2005 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Sat, 22 Jan 2005 21:16:00 -0600 Subject: [llvm-commits] CVS: llvm/utils/fpcmp/fpcmp.cpp Message-ID: <200501230316.j0N3G0a1018301@apoc.cs.uiuc.edu> Changes in directory llvm/utils/fpcmp: fpcmp.cpp updated: 1.11 -> 1.12 --- Log message: The meat of this utility has been moved to FileUtilities, where it can be used by other tools. --- Diffs of the changes: (+8 -153) fpcmp.cpp | 161 +++----------------------------------------------------------- 1 files changed, 8 insertions(+), 153 deletions(-) Index: llvm/utils/fpcmp/fpcmp.cpp diff -u llvm/utils/fpcmp/fpcmp.cpp:1.11 llvm/utils/fpcmp/fpcmp.cpp:1.12 --- llvm/utils/fpcmp/fpcmp.cpp:1.11 Mon Dec 13 11:41:13 2004 +++ llvm/utils/fpcmp/fpcmp.cpp Sat Jan 22 21:15:47 2005 @@ -8,12 +8,12 @@ //===----------------------------------------------------------------------===// // // fpcmp is a tool that basically works like the 'cmp' tool, except that it can -// tolerate errors due to floating point noise, with the -r option. +// tolerate errors due to floating point noise, with the -r and -a options. // //===----------------------------------------------------------------------===// #include "llvm/Support/CommandLine.h" -#include "llvm/System/MappedFile.h" +#include "llvm/Support/FileUtilities.h" #include #include @@ -31,159 +31,14 @@ AbsTolerance("a", cl::desc("Absolute error tolerated"), cl::init(0)); } -static bool isNumberChar(char C) { - switch (C) { - case '0': case '1': case '2': case '3': case '4': - case '5': case '6': case '7': case '8': case '9': - case '.': case '+': case '-': - case 'e': - case 'E': return true; - default: return false; - } -} - -static char *BackupNumber(char *Pos, char *FirstChar) { - // If we didn't stop in the middle of a number, don't backup. - if (!isNumberChar(*Pos)) return Pos; - - // Otherwise, return to the start of the number. - while (Pos > FirstChar && isNumberChar(Pos[-1])) - --Pos; - return Pos; -} - -static void CompareNumbers(char *&F1P, char *&F2P, char *F1End, char *F2End) { - char *F1NumEnd, *F2NumEnd; - double V1 = 0.0, V2 = 0.0; - // If we stop on numbers, compare their difference. - if (isNumberChar(*F1P) && isNumberChar(*F2P)) { - V1 = strtod(F1P, &F1NumEnd); - V2 = strtod(F2P, &F2NumEnd); - } else { - // Otherwise, the diff failed. - F1NumEnd = F1P; - F2NumEnd = F2P; - } - - if (F1NumEnd == F1P || F2NumEnd == F2P) { - std::cerr << "Comparison failed, not a numeric difference.\n"; - exit(1); - } - - // Check to see if these are inside the absolute tolerance - if (AbsTolerance < std::abs(V1-V2)) { - // Nope, check the relative tolerance... - double Diff; - if (V2) - Diff = std::abs(V1/V2 - 1.0); - else if (V1) - Diff = std::abs(V2/V1 - 1.0); - else - Diff = 0; // Both zero. - if (Diff > RelTolerance) { - std::cerr << "Compared: " << V1 << " and " << V2 << ": diff = " - << Diff << "\n"; - std::cerr << "Out of tolerance: rel/abs: " << RelTolerance - << "/" << AbsTolerance << "\n"; - exit(1); - } - } - - // Otherwise, advance our read pointers to the end of the numbers. - F1P = F1NumEnd; F2P = F2NumEnd; -} - -// PadFileIfNeeded - If the files are not identical, we will have to be doing -// numeric comparisons in here. There are bad cases involved where we (i.e., -// strtod) might run off the beginning or end of the file if it starts or ends -// with a number. Because of this, if needed, we pad the file so that it starts -// and ends with a null character. -static void PadFileIfNeeded(char *&FileStart, char *&FileEnd, char *&FP) { - if (isNumberChar(FileStart[0]) || isNumberChar(FileEnd[-1])) { - unsigned FileLen = FileEnd-FileStart; - char *NewFile = new char[FileLen+2]; - NewFile[0] = 0; // Add null padding - NewFile[FileLen+1] = 0; // Add null padding - memcpy(NewFile+1, FileStart, FileLen); - FP = NewFile+(FP-FileStart)+1; - FileStart = NewFile+1; - FileEnd = FileStart+FileLen; - } -} - int main(int argc, char **argv) { cl::ParseCommandLineOptions(argc, argv); - try { - // map in the files into memory - sys::Path F1Path(File1); - sys::Path F2Path(File2); - sys::MappedFile F1 ( F1Path ); - sys::MappedFile F2 ( F2Path ); - F1.map(); - F2.map(); - - // Okay, now that we opened the files, scan them for the first difference. - char *File1Start = F1.charBase(); - char *File2Start = F2.charBase(); - char *File1End = File1Start+F1.size(); - char *File2End = File2Start+F2.size(); - char *F1P = File1Start; - char *F2P = File2Start; - - // Scan for the end of file or first difference. - while (F1P < File1End && F2P < File2End && *F1P == *F2P) - ++F1P, ++F2P; - - // Common case: identifical files. - if (F1P == File1End && F2P == File2End) return 0; - - // If the files need padding, do so now. - PadFileIfNeeded(File1Start, File1End, F1P); - PadFileIfNeeded(File2Start, File2End, F2P); - - while (1) { - // Scan for the end of file or next difference. - while (F1P < File1End && F2P < File2End && *F1P == *F2P) - ++F1P, ++F2P; - - if (F1P >= File1End || F2P >= File2End) break; - - // Okay, we must have found a difference. Backup to the start of the - // current number each stream is at so that we can compare from the - // beginning. - F1P = BackupNumber(F1P, File1Start); - F2P = BackupNumber(F2P, File2Start); - - // Now that we are at the start of the numbers, compare them, exiting if - // they don't match. - CompareNumbers(F1P, F2P, File1End, File2End); - } - - // Okay, we reached the end of file. If both files are at the end, we - // succeeded. - bool F1AtEnd = F1P >= File1End; - bool F2AtEnd = F2P >= File2End; - if (F1AtEnd & F2AtEnd) return 0; - - // Else, we might have run off the end due to a number: backup and retry. - if (F1AtEnd && isNumberChar(F1P[-1])) --F1P; - if (F2AtEnd && isNumberChar(F2P[-1])) --F2P; - F1P = BackupNumber(F1P, File1Start); - F2P = BackupNumber(F2P, File2Start); - - // Now that we are at the start of the numbers, compare them, exiting if - // they don't match. - CompareNumbers(F1P, F2P, File1End, File2End); - - // If we found the end, we succeeded. - if (F1P >= File1End && F2P >= File2End) return 0; - - } catch (const std::string& msg) { - std::cerr << argv[0] << ": error: " << msg << "\n"; - return 2; - } - - return 1; + std::string ErrorMsg; + int DF = DiffFilesWithTolerance(File1, File2, AbsTolerance, RelTolerance, + &ErrorMsg); + if (!ErrorMsg.empty()) + std::cerr << argv[0] << ": " << ErrorMsg << "\n"; + return DF; } From lattner at cs.uiuc.edu Sat Jan 22 21:17:09 2005 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Sat, 22 Jan 2005 21:17:09 -0600 Subject: [llvm-commits] CVS: llvm/utils/fpcmp/fpcmp.cpp Message-ID: <200501230317.j0N3H9mg018511@apoc.cs.uiuc.edu> Changes in directory llvm/utils/fpcmp: fpcmp.cpp updated: 1.12 -> 1.13 --- Log message: Drop dead #include --- Diffs of the changes: (+0 -2) fpcmp.cpp | 2 -- 1 files changed, 2 deletions(-) Index: llvm/utils/fpcmp/fpcmp.cpp diff -u llvm/utils/fpcmp/fpcmp.cpp:1.12 llvm/utils/fpcmp/fpcmp.cpp:1.13 --- llvm/utils/fpcmp/fpcmp.cpp:1.12 Sat Jan 22 21:15:47 2005 +++ llvm/utils/fpcmp/fpcmp.cpp Sat Jan 22 21:16:56 2005 @@ -15,8 +15,6 @@ #include "llvm/Support/CommandLine.h" #include "llvm/Support/FileUtilities.h" #include -#include - using namespace llvm; namespace { From lattner at cs.uiuc.edu Sat Jan 22 21:19:26 2005 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Sat, 22 Jan 2005 21:19:26 -0600 Subject: [llvm-commits] CVS: llvm/lib/Support/FileUtilities.cpp Message-ID: <200501230319.j0N3JQHQ018529@apoc.cs.uiuc.edu> Changes in directory llvm/lib/Support: FileUtilities.cpp updated: 1.36 -> 1.37 --- Log message: Fix a bug in previous checkin --- Diffs of the changes: (+2 -2) FileUtilities.cpp | 4 ++-- 1 files changed, 2 insertions(+), 2 deletions(-) Index: llvm/lib/Support/FileUtilities.cpp diff -u llvm/lib/Support/FileUtilities.cpp:1.36 llvm/lib/Support/FileUtilities.cpp:1.37 --- llvm/lib/Support/FileUtilities.cpp:1.36 Sat Jan 22 21:13:43 2005 +++ llvm/lib/Support/FileUtilities.cpp Sat Jan 22 21:19:13 2005 @@ -239,9 +239,9 @@ } if (OrigFile1Start != File1Start) - delete[] File1Start; + delete[] File1Start-1; // Back up past null byte if (OrigFile2Start != File2Start) - delete[] File2Start; + delete[] File2Start-1; // Back up past null byte return CompareFailed; } catch (const std::string &Msg) { if (Error) *Error = Msg; From lattner at cs.uiuc.edu Sat Jan 22 21:30:52 2005 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Sat, 22 Jan 2005 21:30:52 -0600 Subject: [llvm-commits] CVS: llvm/include/llvm/Support/FileUtilities.h Message-ID: <200501230330.j0N3Uqgh029196@apoc.cs.uiuc.edu> Changes in directory llvm/include/llvm/Support: FileUtilities.h updated: 1.29 -> 1.30 --- Log message: Remove two dead methods and improve the comments for DiffFilesWithTolerance. Also, make DiffFilesWithTolerance take sys::Path objects instead of std::strings. --- Diffs of the changes: (+10 -26) FileUtilities.h | 36 ++++++++++-------------------------- 1 files changed, 10 insertions(+), 26 deletions(-) Index: llvm/include/llvm/Support/FileUtilities.h diff -u llvm/include/llvm/Support/FileUtilities.h:1.29 llvm/include/llvm/Support/FileUtilities.h:1.30 --- llvm/include/llvm/Support/FileUtilities.h:1.29 Sat Jan 22 21:11:38 2005 +++ llvm/include/llvm/Support/FileUtilities.h Sat Jan 22 21:30:39 2005 @@ -19,34 +19,18 @@ namespace llvm { -/// DiffFiles - Compare the two files specified, returning true if they are -/// different or if there is a file error. If you specify a string to fill in -/// for the error option, it will set the string to an error message if an error -/// occurs, allowing the caller to distinguish between a failed diff and a file -/// system error. -/// -bool DiffFiles(const std::string &FileA, const std::string &FileB, - std::string *Error = 0); - -/// DiffFilesWithTolerance - Compare the two files specified, returning 0 if the -/// files match, 1 if they are different, and 2 if there is a file error. This -/// function differs from DiffFiles in that you can specify an absolete and -/// relative FP error that is allowed to exist. If you specify a string to fill -/// in for the error option, it will set the string to an error message if an -/// error occurs, allowing the caller to distinguish between a failed diff and a -/// file system error. -/// -int DiffFilesWithTolerance(const std::string &FileA, const std::string &FileB, - double AbsTol, double RelTol, - std::string *Error = 0); + /// DiffFilesWithTolerance - Compare the two files specified, returning 0 if + /// the files match, 1 if they are different, and 2 if there is a file error. + /// This function allows you to specify an absolete and relative FP error that + /// is allowed to exist. If you specify a string to fill in for the error + /// option, it will set the string to an error message if an error occurs, or + /// if the files are different. + /// + int DiffFilesWithTolerance(const sys::Path &FileA, const sys::Path &FileB, + double AbsTol, double RelTol, + std::string *Error = 0); -/// MoveFileOverIfUpdated - If the file specified by New is different than Old, -/// or if Old does not exist, move the New file over the Old file. Otherwise, -/// remove the New file. -/// -void MoveFileOverIfUpdated(const std::string &New, const std::string &Old); - /// FileRemover - This class is a simple object meant to be stack allocated. /// If an exception is thrown from a region, the object removes the filename /// specified (if deleteIt is true). From lattner at cs.uiuc.edu Sat Jan 22 21:31:15 2005 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Sat, 22 Jan 2005 21:31:15 -0600 Subject: [llvm-commits] CVS: llvm/lib/Support/FileUtilities.cpp Message-ID: <200501230331.j0N3VFw7029211@apoc.cs.uiuc.edu> Changes in directory llvm/lib/Support: FileUtilities.cpp updated: 1.37 -> 1.38 --- Log message: Make DiffFilesWithTolerance take sys::Path's instead of std::strings Delete dead functions. --- Diffs of the changes: (+9 -55) FileUtilities.cpp | 64 +++++++----------------------------------------------- 1 files changed, 9 insertions(+), 55 deletions(-) Index: llvm/lib/Support/FileUtilities.cpp diff -u llvm/lib/Support/FileUtilities.cpp:1.37 llvm/lib/Support/FileUtilities.cpp:1.38 --- llvm/lib/Support/FileUtilities.cpp:1.37 Sat Jan 22 21:19:13 2005 +++ llvm/lib/Support/FileUtilities.cpp Sat Jan 22 21:31:02 2005 @@ -17,57 +17,8 @@ #include "llvm/System/MappedFile.h" #include "llvm/ADT/StringExtras.h" #include -#include -#include - using namespace llvm; -/// DiffFiles - Compare the two files specified, returning true if they are -/// different or if there is a file error. If you specify a string to fill in -/// for the error option, it will set the string to an error message if an error -/// occurs, allowing the caller to distinguish between a failed diff and a file -/// system error. -/// -bool llvm::DiffFiles(const std::string &FileA, const std::string &FileB, - std::string *Error) { - std::ios::openmode io_mode = std::ios::in | std::ios::binary; - std::ifstream FileAStream(FileA.c_str(), io_mode); - if (!FileAStream) { - if (Error) *Error = "Couldn't open file '" + FileA + "'"; - return true; - } - - std::ifstream FileBStream(FileB.c_str(), io_mode); - if (!FileBStream) { - if (Error) *Error = "Couldn't open file '" + FileB + "'"; - return true; - } - - // Compare the two files... - int C1, C2; - do { - C1 = FileAStream.get(); - C2 = FileBStream.get(); - if (C1 != C2) return true; - } while (C1 != EOF); - - return false; -} - -/// MoveFileOverIfUpdated - If the file specified by New is different than Old, -/// or if Old does not exist, move the New file over the Old file. Otherwise, -/// remove the New file. -/// -void llvm::MoveFileOverIfUpdated(const std::string &New, - const std::string &Old) { - if (DiffFiles(New, Old)) { - if (std::rename(New.c_str(), Old.c_str())) - std::cerr << "Error renaming '" << New << "' to '" << Old << "'!\n"; - } else { - std::remove(New.c_str()); - } -} - static bool isNumberChar(char C) { switch (C) { case '0': case '1': case '2': case '3': case '4': @@ -162,14 +113,14 @@ /// error occurs, allowing the caller to distinguish between a failed diff and a /// file system error. /// -int llvm::DiffFilesWithTolerance(const std::string &FileA, - const std::string &FileB, +int llvm::DiffFilesWithTolerance(const sys::Path &FileA, + const sys::Path &FileB, double AbsTol, double RelTol, std::string *Error) { try { // Map in the files into memory. - sys::MappedFile F1((sys::Path(FileA))); - sys::MappedFile F2((sys::Path(FileB))); + sys::MappedFile F1(FileA); + sys::MappedFile F2(FileB); F1.map(); F2.map(); @@ -188,6 +139,9 @@ // Common case: identifical files. if (F1P == File1End && F2P == File2End) return 0; + if (AbsTol == 0 && RelTol == 0) + return 1; // Files different! + char *OrigFile1Start = File1Start; char *OrigFile2Start = File2Start; @@ -239,9 +193,9 @@ } if (OrigFile1Start != File1Start) - delete[] File1Start-1; // Back up past null byte + delete[] (File1Start-1); // Back up past null byte if (OrigFile2Start != File2Start) - delete[] File2Start-1; // Back up past null byte + delete[] (File2Start-1); // Back up past null byte return CompareFailed; } catch (const std::string &Msg) { if (Error) *Error = Msg; From lattner at cs.uiuc.edu Sat Jan 22 21:31:52 2005 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Sat, 22 Jan 2005 21:31:52 -0600 Subject: [llvm-commits] CVS: llvm/tools/bugpoint/ExecutionDriver.cpp Message-ID: <200501230331.j0N3Vqvu029230@apoc.cs.uiuc.edu> Changes in directory llvm/tools/bugpoint: ExecutionDriver.cpp updated: 1.51 -> 1.52 --- Log message: Adjust to changed interface. --- Diffs of the changes: (+2 -1) ExecutionDriver.cpp | 3 ++- 1 files changed, 2 insertions(+), 1 deletion(-) Index: llvm/tools/bugpoint/ExecutionDriver.cpp diff -u llvm/tools/bugpoint/ExecutionDriver.cpp:1.51 llvm/tools/bugpoint/ExecutionDriver.cpp:1.52 --- llvm/tools/bugpoint/ExecutionDriver.cpp:1.51 Wed Dec 22 16:33:33 2004 +++ llvm/tools/bugpoint/ExecutionDriver.cpp Sat Jan 22 21:31:39 2005 @@ -303,7 +303,8 @@ std::string Error; bool FilesDifferent = false; - if (DiffFiles(ReferenceOutputFile, Output.toString(), &Error)) { + if (DiffFilesWithTolerance(ReferenceOutputFile, Output.toString(), 0, 0, + &Error)) { if (!Error.empty()) { std::cerr << "While diffing output: " << Error << '\n'; exit(1); From lattner at cs.uiuc.edu Sat Jan 22 21:32:29 2005 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Sat, 22 Jan 2005 21:32:29 -0600 Subject: [llvm-commits] CVS: llvm/utils/fpcmp/fpcmp.cpp Message-ID: <200501230332.j0N3WT4M029397@apoc.cs.uiuc.edu> Changes in directory llvm/utils/fpcmp: fpcmp.cpp updated: 1.13 -> 1.14 --- Log message: This method takes sys::Path objects now. --- Diffs of the changes: (+2 -2) fpcmp.cpp | 4 ++-- 1 files changed, 2 insertions(+), 2 deletions(-) Index: llvm/utils/fpcmp/fpcmp.cpp diff -u llvm/utils/fpcmp/fpcmp.cpp:1.13 llvm/utils/fpcmp/fpcmp.cpp:1.14 --- llvm/utils/fpcmp/fpcmp.cpp:1.13 Sat Jan 22 21:16:56 2005 +++ llvm/utils/fpcmp/fpcmp.cpp Sat Jan 22 21:32:16 2005 @@ -33,8 +33,8 @@ cl::ParseCommandLineOptions(argc, argv); std::string ErrorMsg; - int DF = DiffFilesWithTolerance(File1, File2, AbsTolerance, RelTolerance, - &ErrorMsg); + int DF = DiffFilesWithTolerance(sys::Path(File1), sys::Path(File2), + AbsTolerance, RelTolerance, &ErrorMsg); if (!ErrorMsg.empty()) std::cerr << argv[0] << ": " << ErrorMsg << "\n"; return DF; From lattner at cs.uiuc.edu Sat Jan 22 21:45:41 2005 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Sat, 22 Jan 2005 21:45:41 -0600 Subject: [llvm-commits] CVS: llvm/tools/bugpoint/ExecutionDriver.cpp Message-ID: <200501230345.j0N3jfpL029627@apoc.cs.uiuc.edu> Changes in directory llvm/tools/bugpoint: ExecutionDriver.cpp updated: 1.52 -> 1.53 --- Log message: Add support for fp tolerances --- Diffs of the changes: (+11 -3) ExecutionDriver.cpp | 14 +++++++++++--- 1 files changed, 11 insertions(+), 3 deletions(-) Index: llvm/tools/bugpoint/ExecutionDriver.cpp diff -u llvm/tools/bugpoint/ExecutionDriver.cpp:1.52 llvm/tools/bugpoint/ExecutionDriver.cpp:1.53 --- llvm/tools/bugpoint/ExecutionDriver.cpp:1.52 Sat Jan 22 21:31:39 2005 +++ llvm/tools/bugpoint/ExecutionDriver.cpp Sat Jan 22 21:45:26 2005 @@ -29,6 +29,13 @@ AutoPick, RunLLI, RunJIT, RunLLC, RunCBE }; + cl::opt + AbsTolerance("abs-tolerance", cl::desc("Absolute error tolerated"), + cl::init(0.0)); + cl::opt + RelTolerance("rel-tolerance", cl::desc("Relative error tolerated"), + cl::init(0.0)); + cl::opt InterpreterSel(cl::desc("Specify how LLVM code should be executed:"), cl::values(clEnumValN(AutoPick, "auto", "Use best guess"), @@ -303,9 +310,10 @@ std::string Error; bool FilesDifferent = false; - if (DiffFilesWithTolerance(ReferenceOutputFile, Output.toString(), 0, 0, - &Error)) { - if (!Error.empty()) { + if (int Diff = DiffFilesWithTolerance(sys::Path(ReferenceOutputFile), + sys::Path(Output.toString()), + AbsTolerance, RelTolerance, &Error)) { + if (Diff == 2) { std::cerr << "While diffing output: " << Error << '\n'; exit(1); } From reid at x10sys.com Sat Jan 22 21:52:24 2005 From: reid at x10sys.com (Reid Spencer) Date: Sat, 22 Jan 2005 21:52:24 -0600 Subject: [llvm-commits] CVS: llvm/lib/Target/X86/X86AsmPrinter.cpp Message-ID: <200501230352.VAA32163@zion.cs.uiuc.edu> Changes in directory llvm/lib/Target/X86: X86AsmPrinter.cpp updated: 1.131 -> 1.132 --- Log message: Support Cygwin assembly generation. The cygwin version of Gnu ASsembler doesn't support certain directives and symbols on cygwin are prefixed with an underscore. This patch makes the necessary adjustments to the output. --- Diffs of the changes: (+37 -11) X86AsmPrinter.cpp | 48 +++++++++++++++++++++++++++++++++++++----------- 1 files changed, 37 insertions(+), 11 deletions(-) Index: llvm/lib/Target/X86/X86AsmPrinter.cpp diff -u llvm/lib/Target/X86/X86AsmPrinter.cpp:1.131 llvm/lib/Target/X86/X86AsmPrinter.cpp:1.132 --- llvm/lib/Target/X86/X86AsmPrinter.cpp:1.131 Tue Jan 11 22:07:11 2005 +++ llvm/lib/Target/X86/X86AsmPrinter.cpp Sat Jan 22 21:52:14 2005 @@ -43,10 +43,12 @@ struct X86SharedAsmPrinter : public AsmPrinter { X86SharedAsmPrinter(std::ostream &O, TargetMachine &TM) - : AsmPrinter(O, TM) { } + : AsmPrinter(O, TM), forCygwin(false) { } + bool doInitialization(Module &M); void printConstantPool(MachineConstantPool *MCP); bool doFinalization(Module &M); + bool forCygwin; }; } @@ -77,6 +79,24 @@ } } +/// doInitialization - determine +bool X86SharedAsmPrinter::doInitialization(Module& M) { + forCygwin = false; + const std::string& TT = M.getTargetTriple(); + if (TT.length() > 5) + forCygwin = TT.find("cygwin") != std::string::npos; + else if (TT.empty()) { +#ifdef __CYGWIN__ + forCygwin = true; +#else + forCygwin = false; +#endif + } + if (forCygwin) + GlobalPrefix = "_"; + return AsmPrinter::doInitialization(M); +} + /// printConstantPool - Print to the current output stream assembly /// representations of the constants in the constant pool MCP. This is /// used to print out constants which have been "spilled to memory" by @@ -114,11 +134,12 @@ (I->hasLinkOnceLinkage() || I->hasInternalLinkage() || I->hasWeakLinkage() /* FIXME: Verify correct */)) { SwitchSection(O, CurSection, ".data"); - if (I->hasInternalLinkage()) + if (!forCygwin && I->hasInternalLinkage()) O << "\t.local " << name << "\n"; - O << "\t.comm " << name << "," << TD.getTypeSize(C->getType()) - << "," << (1 << Align); + O << "\t.comm " << name << "," << TD.getTypeSize(C->getType()); + if (!forCygwin) + O << "," << (1 << Align); O << "\t\t# "; WriteAsOperand(O, I, true, true, &M); O << "\n"; @@ -150,8 +171,10 @@ } emitAlignment(Align); - O << "\t.type " << name << ", at object\n"; - O << "\t.size " << name << "," << Size << "\n"; + if (!forCygwin) { + O << "\t.type " << name << ", at object\n"; + O << "\t.size " << name << "," << Size << "\n"; + } O << name << ":\t\t\t\t# "; WriteAsOperand(O, I, true, true, &M); O << " = "; @@ -239,7 +262,8 @@ O << "\t.text\n"; emitAlignment(4); O << "\t.globl\t" << CurrentFnName << "\n"; - O << "\t.type\t" << CurrentFnName << ", @function\n"; + if (!forCygwin) + O << "\t.type\t" << CurrentFnName << ", @function\n"; O << CurrentFnName << ":\n"; // Print out code for the function. @@ -306,7 +330,7 @@ return; } case MachineOperand::MO_ExternalSymbol: - O << MO.getSymbolName(); + O << GlobalPrefix << MO.getSymbolName(); return; default: O << ""; return; @@ -462,7 +486,8 @@ O << "\t.text\n"; emitAlignment(4); O << "\t.globl\t" << CurrentFnName << "\n"; - O << "\t.type\t" << CurrentFnName << ", @function\n"; + if (!forCygwin) + O << "\t.type\t" << CurrentFnName << ", @function\n"; O << CurrentFnName << ":\n"; // Print out code for the function. @@ -523,7 +548,7 @@ } case MachineOperand::MO_ExternalSymbol: if (!isCallOp) O << '$'; - O << MO.getSymbolName(); + O << GlobalPrefix << MO.getSymbolName(); return; default: O << ""; return; @@ -600,7 +625,8 @@ /// FunctionPass *llvm::createX86CodePrinterPass(std::ostream &o,TargetMachine &tm){ switch (AsmWriterFlavor) { - default: assert(0 && "Unknown asm flavor!"); + default: + assert(0 && "Unknown asm flavor!"); case intel: return new X86IntelAsmPrinter(o, tm); case att: From reid at x10sys.com Sat Jan 22 22:32:58 2005 From: reid at x10sys.com (Reid Spencer) Date: Sat, 22 Jan 2005 22:32:58 -0600 Subject: [llvm-commits] CVS: llvm/lib/Target/CBackend/Writer.cpp Message-ID: <200501230432.WAA32386@zion.cs.uiuc.edu> Changes in directory llvm/lib/Target/CBackend: Writer.cpp updated: 1.218 -> 1.219 --- Log message: Fix alloca support for Cygwin. On cygwin its __alloca not __builtin_alloca --- Diffs of the changes: (+4 -1) Writer.cpp | 5 ++++- 1 files changed, 4 insertions(+), 1 deletion(-) Index: llvm/lib/Target/CBackend/Writer.cpp diff -u llvm/lib/Target/CBackend/Writer.cpp:1.218 llvm/lib/Target/CBackend/Writer.cpp:1.219 --- llvm/lib/Target/CBackend/Writer.cpp:1.218 Wed Jan 5 22:21:49 2005 +++ llvm/lib/Target/CBackend/Writer.cpp Sat Jan 22 22:32:47 2005 @@ -723,7 +723,10 @@ static void generateCompilerSpecificCode(std::ostream& Out) { // Alloca is hard to get, and we don't want to include stdlib.h here... Out << "/* get a declaration for alloca */\n" - << "#if defined(__CYGWIN__) || defined(__APPLE__)\n" + << "#if defined(__CYGWIN__)\n" + << "extern void *_alloca(unsigned long);\n" + << "#define alloca(x) _alloca(x)\n" + << "#elif defined(__APPLE__)\n" << "extern void *__builtin_alloca(unsigned long);\n" << "#define alloca(x) __builtin_alloca(x)\n" << "#elif defined(__sun__)\n" From lattner at cs.uiuc.edu Sat Jan 22 22:35:01 2005 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Sat, 22 Jan 2005 22:35:01 -0600 Subject: [llvm-commits] CVS: llvm/lib/Target/Makefile Message-ID: <200501230435.j0N4Z1gI001230@apoc.cs.uiuc.edu> Changes in directory llvm/lib/Target: Makefile updated: 1.21 -> 1.22 --- Log message: Build Alpha by default. --- Diffs of the changes: (+1 -1) Makefile | 2 +- 1 files changed, 1 insertion(+), 1 deletion(-) Index: llvm/lib/Target/Makefile diff -u llvm/lib/Target/Makefile:1.21 llvm/lib/Target/Makefile:1.22 --- llvm/lib/Target/Makefile:1.21 Thu Dec 9 22:54:21 2004 +++ llvm/lib/Target/Makefile Sat Jan 22 22:34:46 2005 @@ -7,7 +7,7 @@ # ##===----------------------------------------------------------------------===## LEVEL = ../.. -PARALLEL_DIRS = CBackend X86 SparcV8 SparcV9 PowerPC Skeleton +PARALLEL_DIRS = CBackend X86 SparcV8 SparcV9 PowerPC Alpha Skeleton LIBRARYNAME = LLVMTarget BUILD_ARCHIVE = 1 From lattner at cs.uiuc.edu Sat Jan 22 22:36:19 2005 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Sat, 22 Jan 2005 22:36:19 -0600 Subject: [llvm-commits] CVS: llvm/include/llvm/CodeGen/SelectionDAG.h Message-ID: <200501230436.j0N4aJmI001252@apoc.cs.uiuc.edu> Changes in directory llvm/include/llvm/CodeGen: SelectionDAG.h updated: 1.17 -> 1.18 --- Log message: Give SelectionDAG a TargetLowering instance instead of TM instance. --- Diffs of the changes: (+5 -4) SelectionDAG.h | 9 +++++---- 1 files changed, 5 insertions(+), 4 deletions(-) Index: llvm/include/llvm/CodeGen/SelectionDAG.h diff -u llvm/include/llvm/CodeGen/SelectionDAG.h:1.17 llvm/include/llvm/CodeGen/SelectionDAG.h:1.18 --- llvm/include/llvm/CodeGen/SelectionDAG.h:1.17 Wed Jan 19 14:19:58 2005 +++ llvm/include/llvm/CodeGen/SelectionDAG.h Sat Jan 22 22:36:06 2005 @@ -36,7 +36,7 @@ /// linear form. /// class SelectionDAG { - const TargetMachine &TM; + TargetLowering &TLI; MachineFunction &MF; // Root - The root of the entire DAG. EntryNode - The starting token. @@ -45,13 +45,14 @@ // AllNodes - All of the nodes in the DAG std::vector AllNodes; public: - SelectionDAG(const TargetMachine &tm, MachineFunction &mf) : TM(tm), MF(mf) { + SelectionDAG(TargetLowering &tli, MachineFunction &mf) : TLI(tli), MF(mf) { EntryNode = Root = getNode(ISD::EntryToken, MVT::Other); } ~SelectionDAG(); MachineFunction &getMachineFunction() const { return MF; } - const TargetMachine &getTarget() { return TM; } + const TargetMachine &getTarget() const; + TargetLowering &getTargetLoweringInfo() const { return TLI; } /// viewGraph - Pop up a ghostview window with the DAG rendered using 'dot'. /// @@ -80,7 +81,7 @@ /// /// Note that this is an involved process that may invalidate pointers into /// the graph. - void Legalize(TargetLowering &TLI); + void Legalize(); /// RemoveDeadNodes - This method deletes all unreachable nodes in the /// SelectionDAG, including nodes (like loads) that have uses of their token From lattner at cs.uiuc.edu Sat Jan 22 22:36:39 2005 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Sat, 22 Jan 2005 22:36:39 -0600 Subject: [llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp Message-ID: <200501230436.j0N4ad7s001268@apoc.cs.uiuc.edu> Changes in directory llvm/lib/CodeGen/SelectionDAG: SelectionDAGISel.cpp updated: 1.29 -> 1.30 --- Log message: Adjust to changes in SelectionDAG interface. --- Diffs of the changes: (+2 -2) SelectionDAGISel.cpp | 4 ++-- 1 files changed, 2 insertions(+), 2 deletions(-) Index: llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp diff -u llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.29 llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.30 --- llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.29 Sat Jan 22 17:04:37 2005 +++ llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp Sat Jan 22 22:36:26 2005 @@ -1018,7 +1018,7 @@ void SelectionDAGISel::SelectBasicBlock(BasicBlock *LLVMBB, MachineFunction &MF, FunctionLoweringInfo &FuncInfo) { - SelectionDAG DAG(TLI.getTargetMachine(), MF); + SelectionDAG DAG(TLI, MF); CurDAG = &DAG; std::vector > PHINodesToUpdate; @@ -1031,7 +1031,7 @@ // Second step, hack on the DAG until it only uses operations and types that // the target supports. - DAG.Legalize(TLI); + DAG.Legalize(); DEBUG(std::cerr << "Legalized selection DAG:\n"); DEBUG(DAG.dump()); From lattner at cs.uiuc.edu Sat Jan 22 22:39:56 2005 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Sat, 22 Jan 2005 22:39:56 -0600 Subject: [llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp Message-ID: <200501230439.j0N4duNf001317@apoc.cs.uiuc.edu> Changes in directory llvm/lib/CodeGen/SelectionDAG: SelectionDAG.cpp updated: 1.49 -> 1.50 --- Log message: Remove the 3 HACK HACK HACKs I put in before, fixing them properly with the new TLI that is available. Implement support for handling out of range shifts. This allows us to compile this code (a 64-bit rotate): unsigned long long f3(unsigned long long x) { return (x << 32) | (x >> (64-32)); } into this: f3: mov %EDX, DWORD PTR [%ESP + 4] mov %EAX, DWORD PTR [%ESP + 8] ret GCC produces this: $ gcc t.c -masm=intel -O3 -S -o - -fomit-frame-pointer .. f3: push %ebx mov %ebx, DWORD PTR [%esp+12] mov %ecx, DWORD PTR [%esp+8] mov %eax, %ebx mov %edx, %ecx pop %ebx ret The Simple ISEL produces (eww gross): f3: sub %ESP, 4 mov DWORD PTR [%ESP], %ESI mov %EDX, DWORD PTR [%ESP + 8] mov %ECX, DWORD PTR [%ESP + 12] mov %EAX, 0 mov %ESI, 0 or %EAX, %ECX or %EDX, %ESI mov %ESI, DWORD PTR [%ESP] add %ESP, 4 ret --- Diffs of the changes: (+27 -14) SelectionDAG.cpp | 41 +++++++++++++++++++++++++++-------------- 1 files changed, 27 insertions(+), 14 deletions(-) Index: llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp diff -u llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp:1.49 llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp:1.50 --- llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp:1.49 Fri Jan 21 18:33:03 2005 +++ llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp Sat Jan 22 22:39:44 2005 @@ -16,6 +16,7 @@ #include "llvm/GlobalValue.h" #include "llvm/Assembly/Writer.h" #include "llvm/CodeGen/MachineBasicBlock.h" +#include "llvm/Target/TargetLowering.h" #include #include #include @@ -141,6 +142,11 @@ return ISD::CondCode(Op1 & Op2); } +const TargetMachine &SelectionDAG::getTarget() const { + return TLI.getTargetMachine(); +} + + /// RemoveDeadNodes - This method deletes all unreachable nodes in the /// SelectionDAG, including nodes (like loads) that have uses of their token /// chain but no other uses and no side effect. If a node is passed in as an @@ -434,6 +440,8 @@ return getSetCC(Cond, VT, N1.getOperand(1), N2.getOperand(1)); } } + + // FIXME: move this stuff to the DAG Combiner when it exists! // Simplify (X+Z) == X --> Z == 0 if (N1.getOperand(0) == N2) @@ -446,10 +454,9 @@ else { assert(N1.getOpcode() == ISD::SUB && "Unexpected operation!"); // (Z-X) == X --> Z == X<<1 - if (N2.getValueType() != MVT::i64) // FIXME: HACK HACK HACK! return getSetCC(Cond, VT, N1.getOperand(0), getNode(ISD::SHL, N2.getValueType(), - N2, getConstant(1, MVT::i8))); + N2, getConstant(1, TLI.getShiftAmountTy()))); } } } @@ -652,29 +659,35 @@ if (N2C->isAllOnesValue()) // mul X, -1 -> 0-X return getNode(ISD::SUB, VT, getConstant(0, VT), N1); - // FIXME: This should only be done if the target supports shift - // operations. + // FIXME: Move this to the DAG combiner when it exists. if ((C2 & C2-1) == 0) { - if (N1.getValueType() != MVT::i64) { // FIXME: HACK HACK HACK! - SDOperand ShAmt = getConstant(ExactLog2(C2), MVT::i8); - return getNode(ISD::SHL, VT, N1, ShAmt); - } + SDOperand ShAmt = getConstant(ExactLog2(C2), TLI.getShiftAmountTy()); + return getNode(ISD::SHL, VT, N1, ShAmt); } break; case ISD::UDIV: - // FIXME: This should only be done if the target supports shift - // operations. + // FIXME: Move this to the DAG combiner when it exists. if ((C2 & C2-1) == 0 && C2) { - if (N1.getValueType() != MVT::i64) { // FIXME: HACK HACK HACK! - SDOperand ShAmt = getConstant(ExactLog2(C2), MVT::i8); - return getNode(ISD::SRL, VT, N1, ShAmt); - } + SDOperand ShAmt = getConstant(ExactLog2(C2), TLI.getShiftAmountTy()); + return getNode(ISD::SRL, VT, N1, ShAmt); } break; case ISD::SHL: case ISD::SRL: + // If the shift amount is bigger than the size of the data, simplify. + if (C2 >= MVT::getSizeInBits(N1.getValueType())) { + if (TLI.getShiftAmountFlavor() == TargetLowering::Mask) { + unsigned NewAmt = + C2 & ((1 << MVT::getSizeInBits(N1.getValueType()))-1); + return getNode(Opcode, VT, N1, getConstant(NewAmt,N2.getValueType())); + } else if (TLI.getShiftAmountFlavor() == TargetLowering::Extend) { + // Shifting all of the bits out? + return getConstant(0, N1.getValueType()); + } + } + // FALL THROUGH. case ISD::SRA: if (C2 == 0) return N1; break; From lattner at cs.uiuc.edu Sat Jan 22 22:43:02 2005 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Sat, 22 Jan 2005 22:43:02 -0600 Subject: [llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp Message-ID: <200501230443.j0N4h2FS001455@apoc.cs.uiuc.edu> Changes in directory llvm/lib/CodeGen/SelectionDAG: LegalizeDAG.cpp updated: 1.51 -> 1.52 --- Log message: Adjust to changes in SelectionDAG interfaces The first half of correct chain insertion for libcalls. This is not enough to fix Fhourstones yet though. --- Diffs of the changes: (+119 -9) LegalizeDAG.cpp | 128 ++++++++++++++++++++++++++++++++++++++++++++++++++++---- 1 files changed, 119 insertions(+), 9 deletions(-) Index: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp diff -u llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.51 llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.52 --- llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.51 Fri Jan 21 18:31:52 2005 +++ llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp Sat Jan 22 22:42:50 2005 @@ -85,7 +85,7 @@ public: - SelectionDAGLegalize(TargetLowering &TLI, SelectionDAG &DAG); + SelectionDAGLegalize(SelectionDAG &DAG); /// Run - While there is still lowering to do, perform a pass over the DAG. /// Most regularization can be done in a single pass, but targets that require @@ -135,9 +135,9 @@ } -SelectionDAGLegalize::SelectionDAGLegalize(TargetLowering &tli, - SelectionDAG &dag) - : TLI(tli), DAG(dag), ValueTypeActions(TLI.getValueTypeActions()) { +SelectionDAGLegalize::SelectionDAGLegalize(SelectionDAG &dag) + : TLI(dag.getTargetLoweringInfo()), DAG(dag), + ValueTypeActions(TLI.getValueTypeActions()) { assert(MVT::LAST_VALUETYPE <= 16 && "Too many value types for ValueTypeActions to hold!"); } @@ -1302,12 +1302,117 @@ return true; } +/// FindLatestAdjCallStackDown - Scan up the dag to find the latest (highest +/// NodeDepth) node that is an AdjCallStackDown operation and occurs later than +/// Found. +static void FindLatestAdjCallStackDown(SDNode *Node, SDNode *&Found) { + if (Node->getNodeDepth() <= Found->getNodeDepth()) return; + + // If we found an ADJCALLSTACKDOWN, we already know this node occurs later + // than the Found node. Just remember this node and return. + if (Node->getOpcode() == ISD::ADJCALLSTACKDOWN) { + Found = Node; + return; + } + + // Otherwise, scan the operands of Node to see if any of them is a call. + assert(Node->getNumOperands() != 0 && + "All leaves should have depth equal to the entry node!"); + for (unsigned i = 0, e = Node->getNumOperands()-1; i != e; ++i) + FindLatestAdjCallStackDown(Node->getOperand(i).Val, Found); + + // Tail recurse for the last iteration. + FindLatestAdjCallStackDown(Node->getOperand(Node->getNumOperands()-1).Val, + Found); +} + + +/// FindEarliestAdjCallStackUp - Scan down the dag to find the earliest (lowest +/// NodeDepth) node that is an AdjCallStackUp operation and occurs more recent +/// than Found. +static void FindEarliestAdjCallStackUp(SDNode *Node, SDNode *&Found) { + if (Found && Node->getNodeDepth() >= Found->getNodeDepth()) return; + + // If we found an ADJCALLSTACKUP, we already know this node occurs earlier + // than the Found node. Just remember this node and return. + if (Node->getOpcode() == ISD::ADJCALLSTACKUP) { + Found = Node; + return; + } + + // Otherwise, scan the operands of Node to see if any of them is a call. + SDNode::use_iterator UI = Node->use_begin(), E = Node->use_end(); + if (UI == E) return; + for (--E; UI != E; ++UI) + FindEarliestAdjCallStackUp(*UI, Found); + + // Tail recurse for the last iteration. + FindEarliestAdjCallStackUp(*UI, Found); +} + +/// FindAdjCallStackUp - Given a chained node that is part of a call sequence, +/// find the ADJCALLSTACKUP node that terminates the call sequence. +static SDNode *FindAdjCallStackUp(SDNode *Node) { + if (Node->getOpcode() == ISD::ADJCALLSTACKUP) + return Node; + assert(!Node->use_empty() && "Could not find ADJCALLSTACKUP!"); + + if (Node->hasOneUse()) // Simple case, only has one user to check. + return FindAdjCallStackUp(*Node->use_begin()); + + SDOperand TheChain(Node, Node->getNumValues()-1); + assert(TheChain.getValueType() == MVT::Other && "Is not a token chain!"); + + for (SDNode::use_iterator UI = Node->use_begin(), + E = Node->use_end(); ; ++UI) { + assert(UI != E && "Didn't find a user of the tokchain, no ADJCALLSTACKUP!"); + + // Make sure to only follow users of our token chain. + SDNode *User = *UI; + for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i) + if (User->getOperand(i) == TheChain) + return FindAdjCallStackUp(User); + } + assert(0 && "Unreachable"); + abort(); +} + +/// FindInputOutputChains - If we are replacing an operation with a call we need +/// to find the call that occurs before and the call that occurs after it to +/// properly serialize the calls in the block. +static SDOperand FindInputOutputChains(SDNode *OpNode, SDNode *&OutChain, + SDOperand Entry) { + SDNode *LatestAdjCallStackDown = Entry.Val; + FindLatestAdjCallStackDown(OpNode, LatestAdjCallStackDown); + //std::cerr << "Found node: "; LatestAdjCallStackDown->dump(); std::cerr <<"\n"; + + SDNode *LatestAdjCallStackUp = FindAdjCallStackUp(LatestAdjCallStackDown); + + + SDNode *EarliestAdjCallStackUp = 0; + FindEarliestAdjCallStackUp(OpNode, EarliestAdjCallStackUp); + + if (EarliestAdjCallStackUp) { + //std::cerr << "Found node: "; + //EarliestAdjCallStackUp->dump(); std::cerr <<"\n"; + } + + return SDOperand(LatestAdjCallStackUp, 0); +} + + + // ExpandLibCall - Expand a node into a call to a libcall. If the result value // does not fit into a register, return the lo part and set the hi part to the // by-reg argument. If it does fit into a single register, return the result // and leave the Hi part unset. SDOperand SelectionDAGLegalize::ExpandLibCall(const char *Name, SDNode *Node, SDOperand &Hi) { + SDNode *OutChain; + SDOperand InChain = FindInputOutputChains(Node, OutChain, + DAG.getEntryNode()); + // TODO. Link in chains. + TargetLowering::ArgListTy Args; for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) { MVT::ValueType ArgVT = Node->getOperand(i).getValueType(); @@ -1320,7 +1425,7 @@ // node as our input and ignore the output chain. This allows us to place // calls wherever we need them to satisfy data dependences. const Type *RetTy = MVT::getTypeForValueType(Node->getValueType(0)); - SDOperand Result = TLI.LowerCallTo(DAG.getEntryNode(), RetTy, Callee, + SDOperand Result = TLI.LowerCallTo(InChain, RetTy, Callee, Args, DAG).first; switch (getTypeAction(Result.getValueType())) { default: assert(0 && "Unknown thing"); @@ -1335,6 +1440,7 @@ } } + /// ExpandIntToFP - Expand a [US]INT_TO_FP operation, assuming that the /// destination type is legal. SDOperand SelectionDAGLegalize:: @@ -1344,6 +1450,10 @@ "This is not an expansion!"); assert(Source.getValueType() == MVT::i64 && "Only handle expand from i64!"); + SDNode *OutChain; + SDOperand InChain = FindInputOutputChains(Source.Val, OutChain, + DAG.getEntryNode()); + const char *FnName; if (isSigned) { if (DestTy == MVT::f32) @@ -1369,8 +1479,8 @@ // node as our input and ignore the output chain. This allows us to place // calls wherever we need them to satisfy data dependences. const Type *RetTy = MVT::getTypeForValueType(DestTy); - return TLI.LowerCallTo(DAG.getEntryNode(), RetTy, Callee, - Args, DAG).first; + return TLI.LowerCallTo(InChain, RetTy, Callee, Args, DAG).first; + } @@ -1592,9 +1702,9 @@ // SelectionDAG::Legalize - This is the entry point for the file. // -void SelectionDAG::Legalize(TargetLowering &TLI) { +void SelectionDAG::Legalize() { /// run - This is the main entry point to this class. /// - SelectionDAGLegalize(TLI, *this).Run(); + SelectionDAGLegalize(*this).Run(); } From lattner at cs.uiuc.edu Sun Jan 23 00:02:53 2005 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Sun, 23 Jan 2005 00:02:53 -0600 Subject: [llvm-commits] CVS: llvm/lib/Support/FileUtilities.cpp Message-ID: <200501230602.j0N62rUD003044@apoc.cs.uiuc.edu> Changes in directory llvm/lib/Support: FileUtilities.cpp updated: 1.38 -> 1.39 --- Log message: Fix crash comparing empty file against nonempty file. --- Diffs of the changes: (+2 -1) FileUtilities.cpp | 3 ++- 1 files changed, 2 insertions(+), 1 deletion(-) Index: llvm/lib/Support/FileUtilities.cpp diff -u llvm/lib/Support/FileUtilities.cpp:1.38 llvm/lib/Support/FileUtilities.cpp:1.39 --- llvm/lib/Support/FileUtilities.cpp:1.38 Sat Jan 22 21:31:02 2005 +++ llvm/lib/Support/FileUtilities.cpp Sun Jan 23 00:02:40 2005 @@ -93,7 +93,8 @@ // with a number. Because of this, if needed, we pad the file so that it starts // and ends with a null character. static void PadFileIfNeeded(char *&FileStart, char *&FileEnd, char *&FP) { - if (isNumberChar(FileStart[0]) || isNumberChar(FileEnd[-1])) { + if (FileStart-FileEnd < 2 || + isNumberChar(FileStart[0]) || isNumberChar(FileEnd[-1])) { unsigned FileLen = FileEnd-FileStart; char *NewFile = new char[FileLen+2]; NewFile[0] = 0; // Add null padding From alkis at cs.uiuc.edu Sun Jan 23 08:40:36 2005 From: alkis at cs.uiuc.edu (Alkis Evlogimenos) Date: Sun, 23 Jan 2005 08:40:36 -0600 Subject: [llvm-commits] CVS: llvm-java/lib/Compiler/Compiler.cpp Message-ID: <200501231440.IAA15196@zion.cs.uiuc.edu> Changes in directory llvm-java/lib/Compiler: Compiler.cpp updated: 1.188 -> 1.189 --- Log message: Eliminate some unneeded casts now that the operand stack implecitly adds thems. --- Diffs of the changes: (+10 -28) Compiler.cpp | 38 ++++++++++---------------------------- 1 files changed, 10 insertions(+), 28 deletions(-) Index: llvm-java/lib/Compiler/Compiler.cpp diff -u llvm-java/lib/Compiler/Compiler.cpp:1.188 llvm-java/lib/Compiler/Compiler.cpp:1.189 --- llvm-java/lib/Compiler/Compiler.cpp:1.188 Fri Jan 21 21:28:12 2005 +++ llvm-java/lib/Compiler/Compiler.cpp Sun Jan 23 08:40:25 2005 @@ -1539,9 +1539,7 @@ void do_aload_common(Type* arrayTy) { Value* index = pop(Type::IntTy); - Value* arrayRef = new CastInst(pop(ObjectBaseRefTy), - PointerType::get(arrayTy), - "cast-to-array", currentBB_); + Value* arrayRef = pop(PointerType::get(arrayTy)); std::vector indices; indices.reserve(3); @@ -1578,9 +1576,7 @@ Value* value = pop(elementTy); Value* index = pop(Type::IntTy); const Type* arrayRefTy = PointerType::get(getArrayInfo(elementTy).type); - Value* arrayRef = new CastInst(pop(ObjectBaseRefTy), - arrayRefTy, - "cast-to-array", currentBB_); + Value* arrayRef = pop(arrayRefTy); std::vector indices; indices.reserve(3); @@ -1830,8 +1826,6 @@ unsigned t, unsigned f) { Value* v2 = pop(type); Value* v1 = pop(type); - if (v1->getType() != v2->getType()) - v1 = new CastInst(v1, v2->getType(), TMP, currentBB_); Value* c = new SetCondInst(cc, v1, v2, TMP, currentBB_); new BranchInst(bbBuilder_->getBasicBlock(t), bbBuilder_->getBasicBlock(f), @@ -2179,8 +2173,7 @@ } void do_newarray(JType type) { - Value* count = pop(Type::IntTy); - count = new CastInst(count, Type::UIntTy, TMP, currentBB_); + Value* count = pop(Type::UIntTy); const ClassInfo& ci = getPrimitiveArrayInfo(type); const VTableInfo& vi = getPrimitiveArrayVTableInfo(type); @@ -2189,8 +2182,7 @@ } void do_anewarray(unsigned index) { - Value* count = pop(Type::IntTy); - count = new CastInst(count, Type::UIntTy, TMP, currentBB_); + Value* count = pop(Type::UIntTy); ConstantClass* classRef = cf_->getConstantClass(index); ClassFile* cf = ClassFile::get(classRef->getName()->str()); @@ -2241,19 +2233,15 @@ } void do_arraylength() { - Value* arrayRef = pop(ObjectBaseRefTy); const ClassInfo& ci = getObjectArrayInfo(); - arrayRef = - new CastInst(arrayRef, PointerType::get(ci.type), TMP, currentBB_); + Value* arrayRef = pop(PointerType::get(ci.type)); Value* lengthPtr = getArrayLengthPtr(arrayRef); Value* length = new LoadInst(lengthPtr, TMP, currentBB_); - length = new CastInst(length, Type::IntTy, TMP, currentBB_); push(length); } void do_athrow() { Value* objRef = pop(ObjectBaseRefTy); - objRef = new CastInst(objRef, ObjectBaseRefTy, TMP, currentBB_); Function* f = module_.getOrInsertFunction( LLVM_JAVA_THROW, Type::IntTy, ObjectBaseRefTy, NULL); @@ -2269,23 +2257,19 @@ tie(ci, vi) = getInfo(classRef->getName()->str()); Value* objRef = pop(ObjectBaseRefTy); - Value* objBase = - new CastInst(objRef, ObjectBaseRefTy, TMP, currentBB_); Function* f = module_.getOrInsertFunction( LLVM_JAVA_ISINSTANCEOF, Type::IntTy, - objBase->getType(), PointerType::get(VTableInfo::VTableBaseTy), NULL); + ObjectBaseRefTy, PointerType::get(VTableInfo::VTableBaseTy), NULL); Value* vtable = new CastInst(vi->vtable, PointerType::get(VTableInfo::VTableBaseTy), TMP, currentBB_); - Value* r = new CallInst(f, objBase, vtable, TMP, currentBB_); + Value* r = new CallInst(f, objRef, vtable, TMP, currentBB_); Value* b = new SetCondInst(Instruction::SetEQ, r, ConstantSInt::get(Type::IntTy, 1), TMP, currentBB_); // FIXME: if b is false we must throw a ClassCast exception - Value* objCast = - new CastInst(objRef, PointerType::get(ci->type), TMP, currentBB_); - push(objCast); + push(objRef); } void do_instanceof(unsigned index) { @@ -2296,15 +2280,13 @@ tie(ci, vi) = getInfo(classRef->getName()->str()); Value* objRef = pop(ObjectBaseRefTy); - Value* objBase = - new CastInst(objRef, ObjectBaseRefTy, TMP, currentBB_); Function* f = module_.getOrInsertFunction( LLVM_JAVA_ISINSTANCEOF, Type::IntTy, - objBase->getType(), PointerType::get(VTableInfo::VTableBaseTy), NULL); + ObjectBaseRefTy, PointerType::get(VTableInfo::VTableBaseTy), NULL); Value* vtable = new CastInst(vi->vtable, PointerType::get(VTableInfo::VTableBaseTy), TMP, currentBB_); - Value* r = new CallInst(f, objBase, vtable, TMP, currentBB_); + Value* r = new CallInst(f, objRef, vtable, TMP, currentBB_); push(r); } From alkis at cs.uiuc.edu Sun Jan 23 08:56:45 2005 From: alkis at cs.uiuc.edu (Alkis Evlogimenos) Date: Sun, 23 Jan 2005 08:56:45 -0600 Subject: [llvm-commits] CVS: llvm-java/test/Programs/SingleSource/UnitTests/Lists3.java Message-ID: <200501231456.IAA15322@zion.cs.uiuc.edu> Changes in directory llvm-java/test/Programs/SingleSource/UnitTests: Lists3.java updated: 1.1 -> 1.2 --- Log message: Make this test pass. --- Diffs of the changes: (+3 -2) Lists3.java | 5 +++-- 1 files changed, 3 insertions(+), 2 deletions(-) Index: llvm-java/test/Programs/SingleSource/UnitTests/Lists3.java diff -u llvm-java/test/Programs/SingleSource/UnitTests/Lists3.java:1.1 llvm-java/test/Programs/SingleSource/UnitTests/Lists3.java:1.2 --- llvm-java/test/Programs/SingleSource/UnitTests/Lists3.java:1.1 Mon Jan 17 20:30:49 2005 +++ llvm-java/test/Programs/SingleSource/UnitTests/Lists3.java Sun Jan 23 08:56:35 2005 @@ -18,7 +18,8 @@ Test.println(((Integer)llist.removeLast()).intValue()); Test.println(llist.size()); - for (Iterator i = llist.iterator(); i.hasNext(); ) - Test.println(((Integer)i.next()).intValue()); + for (int i = 0; i < llist.size(); ++i) { + Test.println(((Integer)llist.get(i)).intValue()); + } } } From alkis at cs.uiuc.edu Sun Jan 23 09:06:44 2005 From: alkis at cs.uiuc.edu (Alkis Evlogimenos) Date: Sun, 23 Jan 2005 09:06:44 -0600 Subject: [llvm-commits] CVS: llvm-java/test/Programs/SingleSource/UnitTests/Lists5.java Message-ID: <200501231506.JAA15455@zion.cs.uiuc.edu> Changes in directory llvm-java/test/Programs/SingleSource/UnitTests: Lists5.java added (r1.1) --- Log message: Add test case distilled from Lists3.java. --- Diffs of the changes: (+10 -0) Lists5.java | 10 ++++++++++ 1 files changed, 10 insertions(+) Index: llvm-java/test/Programs/SingleSource/UnitTests/Lists5.java diff -c /dev/null llvm-java/test/Programs/SingleSource/UnitTests/Lists5.java:1.1 *** /dev/null Sun Jan 23 09:06:43 2005 --- llvm-java/test/Programs/SingleSource/UnitTests/Lists5.java Sun Jan 23 09:06:33 2005 *************** *** 0 **** --- 1,10 ---- + import java.util.*; + + public class Lists5 + { + public static void main(String[] args) { + LinkedList llist = new LinkedList(); + Iterator i = llist.iterator(); + Test.println(i.hasNext()); + } + } From lattner at cs.uiuc.edu Sun Jan 23 14:27:11 2005 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Sun, 23 Jan 2005 14:27:11 -0600 Subject: [llvm-commits] CVS: llvm/lib/Transforms/Scalar/InstructionCombining.cpp Message-ID: <200501232027.j0NKRBkp003563@apoc.cs.uiuc.edu> Changes in directory llvm/lib/Transforms/Scalar: InstructionCombining.cpp updated: 1.309 -> 1.310 --- Log message: Get rid of a several dozen more and instructions in specint. --- Diffs of the changes: (+36 -5) InstructionCombining.cpp | 41 ++++++++++++++++++++++++++++++++++++----- 1 files changed, 36 insertions(+), 5 deletions(-) Index: llvm/lib/Transforms/Scalar/InstructionCombining.cpp diff -u llvm/lib/Transforms/Scalar/InstructionCombining.cpp:1.309 llvm/lib/Transforms/Scalar/InstructionCombining.cpp:1.310 --- llvm/lib/Transforms/Scalar/InstructionCombining.cpp:1.309 Fri Jan 21 17:06:49 2005 +++ llvm/lib/Transforms/Scalar/InstructionCombining.cpp Sun Jan 23 14:26:55 2005 @@ -1298,6 +1298,14 @@ if (ConstantExpr::getAnd(CI, Mask)->isNullValue()) return true; break; + case Instruction::Or: + // If the LHS and the RHS are MaskedValueIsZero, the result is also zero. + return MaskedValueIsZero(I->getOperand(1), Mask) && + MaskedValueIsZero(I->getOperand(0), Mask); + case Instruction::Select: + // If the T and F values are MaskedValueIsZero, the result is also zero. + return MaskedValueIsZero(I->getOperand(2), Mask) && + MaskedValueIsZero(I->getOperand(1), Mask); case Instruction::Cast: { const Type *SrcTy = I->getOperand(0)->getType(); if (SrcTy->isIntegral()) { @@ -1535,9 +1543,9 @@ if (Op0 == Op1) return ReplaceInstUsesWith(I, Op1); - // and X, -1 == X if (ConstantIntegral *AndRHS = dyn_cast(Op1)) { - if (AndRHS->isAllOnesValue()) // and X, -1 == X + // and X, -1 == X + if (AndRHS->isAllOnesValue()) return ReplaceInstUsesWith(I, Op0); if (MaskedValueIsZero(Op0, AndRHS)) // LHS & RHS == 0 @@ -1545,9 +1553,10 @@ // If the mask is not masking out any bits, there is no reason to do the // and in the first place. - if (MaskedValueIsZero(Op0, - cast(ConstantExpr::getNot(AndRHS)))) - return ReplaceInstUsesWith(I, Op0); + ConstantIntegral *NotAndRHS = + cast(ConstantExpr::getNot(AndRHS)); + if (MaskedValueIsZero(Op0, NotAndRHS)) + return ReplaceInstUsesWith(I, Op0); // Optimize a variety of ((val OP C1) & C2) combinations... if (isa(Op0) || isa(Op0)) { @@ -1563,6 +1572,28 @@ return BinaryOperator::createAnd(Op0RHS, AndRHS); if (MaskedValueIsZero(Op0RHS, AndRHS)) return BinaryOperator::createAnd(Op0LHS, AndRHS); + + // If the mask is only needed on one incoming arm, push it up. + if (Op0I->hasOneUse()) { + if (MaskedValueIsZero(Op0LHS, NotAndRHS)) { + // Not masking anything out for the LHS, move to RHS. + Instruction *NewRHS = BinaryOperator::createAnd(Op0RHS, AndRHS, + Op0RHS->getName()+".masked"); + InsertNewInstBefore(NewRHS, I); + return BinaryOperator::create( + cast(Op0I)->getOpcode(), Op0LHS, NewRHS); + } + if (!isa(NotAndRHS) && + MaskedValueIsZero(Op0RHS, NotAndRHS)) { + // Not masking anything out for the RHS, move to LHS. + Instruction *NewLHS = BinaryOperator::createAnd(Op0LHS, AndRHS, + Op0LHS->getName()+".masked"); + InsertNewInstBefore(NewLHS, I); + return BinaryOperator::create( + cast(Op0I)->getOpcode(), NewLHS, Op0RHS); + } + } + break; case Instruction::And: // (X & V) & C2 --> 0 iff (V & C2) == 0 From lattner at cs.uiuc.edu Sun Jan 23 15:45:17 2005 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Sun, 23 Jan 2005 15:45:17 -0600 Subject: [llvm-commits] CVS: llvm/lib/CodeGen/PrologEpilogInserter.cpp Message-ID: <200501232145.j0NLjHJI011854@apoc.cs.uiuc.edu> Changes in directory llvm/lib/CodeGen: PrologEpilogInserter.cpp updated: 1.39 -> 1.40 --- Log message: Speed this up a bit by making ModifiedRegs a vector not vector --- Diffs of the changes: (+5 -6) PrologEpilogInserter.cpp | 11 +++++------ 1 files changed, 5 insertions(+), 6 deletions(-) Index: llvm/lib/CodeGen/PrologEpilogInserter.cpp diff -u llvm/lib/CodeGen/PrologEpilogInserter.cpp:1.39 llvm/lib/CodeGen/PrologEpilogInserter.cpp:1.40 --- llvm/lib/CodeGen/PrologEpilogInserter.cpp:1.39 Fri Jan 21 18:49:16 2005 +++ llvm/lib/CodeGen/PrologEpilogInserter.cpp Sun Jan 23 15:45:01 2005 @@ -112,7 +112,7 @@ return; // This bitset contains an entry for each physical register for the target... - std::vector ModifiedRegs(RegInfo->getNumRegs()); + std::vector ModifiedRegs(RegInfo->getNumRegs()); unsigned MaxCallFrameSize = 0; bool HasCalls = false; @@ -209,7 +209,7 @@ const MRegisterInfo *RegInfo = Fn.getTarget().getRegisterInfo(); // Now that we have a stack slot for each register to be saved, insert spill - // code into the entry block... + // code into the entry block. MachineBasicBlock *MBB = Fn.begin(); MachineBasicBlock::iterator I = MBB->begin(); for (unsigned i = 0, e = RegsToSave.size(); i != e; ++i) { @@ -219,8 +219,8 @@ // Add code to restore the callee-save registers in each exiting block. const TargetInstrInfo &TII = *Fn.getTarget().getInstrInfo(); - for (MachineFunction::iterator FI = Fn.begin(), E = Fn.end(); FI != E; ++FI) { - // If last instruction is a return instruction, add an epilogue + for (MachineFunction::iterator FI = Fn.begin(), E = Fn.end(); FI != E; ++FI) + // If last instruction is a return instruction, add an epilogue. if (!FI->empty() && TII.isReturn(FI->back().getOpcode())) { MBB = FI; I = MBB->end(); --I; @@ -232,12 +232,11 @@ --I; // Insert in reverse order } } - } } /// calculateFrameObjectOffsets - Calculate actual frame offsets for all of the -/// abstract stack objects... +/// abstract stack objects. /// void PEI::calculateFrameObjectOffsets(MachineFunction &Fn) { const TargetFrameInfo &TFI = *Fn.getTarget().getFrameInfo(); From lattner at cs.uiuc.edu Sun Jan 23 16:13:51 2005 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Sun, 23 Jan 2005 16:13:51 -0600 Subject: [llvm-commits] CVS: llvm/include/llvm/CodeGen/MachineFunction.h Message-ID: <200501232213.j0NMDpIv012406@apoc.cs.uiuc.edu> Changes in directory llvm/include/llvm/CodeGen: MachineFunction.h updated: 1.45 -> 1.46 --- Log message: Expose more information from register allocation to passes that run after it. --- Diffs of the changes: (+26 -0) MachineFunction.h | 26 ++++++++++++++++++++++++++ 1 files changed, 26 insertions(+) Index: llvm/include/llvm/CodeGen/MachineFunction.h diff -u llvm/include/llvm/CodeGen/MachineFunction.h:1.45 llvm/include/llvm/CodeGen/MachineFunction.h:1.46 --- llvm/include/llvm/CodeGen/MachineFunction.h:1.45 Wed Oct 27 11:14:51 2004 +++ llvm/include/llvm/CodeGen/MachineFunction.h Sun Jan 23 16:13:36 2005 @@ -97,6 +97,13 @@ // numbered and this vector keeps track of the mapping from ID's to MBB's. std::vector MBBNumbering; + /// UsedPhysRegs - This is a new[]'d array of bools that is computed and set + /// by the register allocator, and must be kept up to date by passes that run + /// after register allocation (though most don't modify this). This is used + /// so that the code generator knows which callee save registers to save and + /// for other target specific uses. + bool *UsedPhysRegs; + public: MachineFunction(const Function *Fn, const TargetMachine &TM); ~MachineFunction(); @@ -138,6 +145,25 @@ return static_cast(MFInfo); } + /// setUsedPhysRegs - The register allocator should call this to initialized + /// the UsedPhysRegs set. This should be passed a new[]'d array with entries + /// for all of the physical registers that the target supports. Each array + /// entry should be set to true iff the physical register is used within the + /// function. + void setUsedPhysRegs(bool *UPR) { UsedPhysRegs = UPR; } + + /// getUsedPhysregs - This returns the UsedPhysRegs array. This returns null + /// before register allocation. + const bool *getUsedPhysregs() { return UsedPhysRegs; } + + /// isPhysRegUsed - Return true if the specified register is used in this + /// function. This only works after register allocation. + bool isPhysRegUsed(unsigned Reg) { return UsedPhysRegs[Reg]; } + + /// changePhyRegUsed - This method allows code that runs after register + /// allocation to keep the PhysRegsUsed array up-to-date. + void changePhyRegUsed(unsigned Reg, bool State) { UsedPhysRegs[Reg] = State; } + /// getBlockNumbered - MachineBasicBlocks are automatically numbered when they /// are inserted into the machine function. The block number for a machine /// basic block can be found by using the MBB::getBlockNumber method, this From lattner at cs.uiuc.edu Sun Jan 23 16:14:11 2005 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Sun, 23 Jan 2005 16:14:11 -0600 Subject: [llvm-commits] CVS: llvm/lib/CodeGen/MachineFunction.cpp Message-ID: <200501232214.j0NMEBjB012417@apoc.cs.uiuc.edu> Changes in directory llvm/lib/CodeGen: MachineFunction.cpp updated: 1.74 -> 1.75 --- Log message: Add support for the PhysRegsUsed array. --- Diffs of the changes: (+3 -2) MachineFunction.cpp | 5 +++-- 1 files changed, 3 insertions(+), 2 deletions(-) Index: llvm/lib/CodeGen/MachineFunction.cpp diff -u llvm/lib/CodeGen/MachineFunction.cpp:1.74 llvm/lib/CodeGen/MachineFunction.cpp:1.75 --- llvm/lib/CodeGen/MachineFunction.cpp:1.74 Sat Jan 8 13:55:00 2005 +++ llvm/lib/CodeGen/MachineFunction.cpp Sun Jan 23 16:13:58 2005 @@ -61,7 +61,7 @@ /// stream is std::cerr; the default banner is empty. /// FunctionPass *llvm::createMachineFunctionPrinterPass(std::ostream *OS, - const std::string &Banner) { + const std::string &Banner){ return new Printer(OS, Banner); } @@ -108,7 +108,7 @@ MachineFunction::MachineFunction(const Function *F, const TargetMachine &TM) - : Annotation(MF_AID), Fn(F), Target(TM) { + : Annotation(MF_AID), Fn(F), Target(TM), UsedPhysRegs(0) { SSARegMapping = new SSARegMap(); MFInfo = 0; FrameInfo = new MachineFrameInfo(); @@ -122,6 +122,7 @@ delete MFInfo; delete FrameInfo; delete ConstantPool; + delete[] UsedPhysRegs; } void MachineFunction::dump() const { print(std::cerr); } From alkis at cs.uiuc.edu Sun Jan 23 16:35:26 2005 From: alkis at cs.uiuc.edu (Alkis Evlogimenos) Date: Sun, 23 Jan 2005 16:35:26 -0600 Subject: [llvm-commits] CVS: llvm-java/test/Programs/SingleSource/UnitTests/MultipleInterfaces.java Message-ID: <200501232235.QAA19294@zion.cs.uiuc.edu> Changes in directory llvm-java/test/Programs/SingleSource/UnitTests: MultipleInterfaces.java updated: 1.5 -> 1.6 --- Log message: Change return types to make the test a bit more interesting. --- Diffs of the changes: (+4 -4) MultipleInterfaces.java | 8 ++++---- 1 files changed, 4 insertions(+), 4 deletions(-) Index: llvm-java/test/Programs/SingleSource/UnitTests/MultipleInterfaces.java diff -u llvm-java/test/Programs/SingleSource/UnitTests/MultipleInterfaces.java:1.5 llvm-java/test/Programs/SingleSource/UnitTests/MultipleInterfaces.java:1.6 --- llvm-java/test/Programs/SingleSource/UnitTests/MultipleInterfaces.java:1.5 Mon Dec 13 21:00:03 2004 +++ llvm-java/test/Programs/SingleSource/UnitTests/MultipleInterfaces.java Sun Jan 23 16:35:15 2005 @@ -2,7 +2,7 @@ { interface I1 { - public int i1(); + public boolean i1(); } interface I2 @@ -12,14 +12,14 @@ interface I3 extends I1, I2 { - public int i3(); + public float i3(); } private static class C1 implements I3 { - public int i1() { return 1; } + public boolean i1() { return true; } public int i2() { return 2; } - public int i3() { return 3; } + public float i3() { return 3.0F; } } public static void main(String[] args) { From lattner at cs.uiuc.edu Sun Jan 23 16:45:28 2005 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Sun, 23 Jan 2005 16:45:28 -0600 Subject: [llvm-commits] CVS: llvm/lib/CodeGen/RegAllocIterativeScan.cpp RegAllocLinearScan.cpp VirtRegMap.cpp Message-ID: <200501232245.j0NMjSJj013418@apoc.cs.uiuc.edu> Changes in directory llvm/lib/CodeGen: RegAllocIterativeScan.cpp updated: 1.20 -> 1.21 RegAllocLinearScan.cpp updated: 1.106 -> 1.107 VirtRegMap.cpp updated: 1.34 -> 1.35 --- Log message: Update these register allocators to set the PhysRegUsed info in MachineFunction. --- Diffs of the changes: (+35 -11) RegAllocIterativeScan.cpp | 10 +++++++++- RegAllocLinearScan.cpp | 11 +++++++++-- VirtRegMap.cpp | 25 +++++++++++++++++-------- 3 files changed, 35 insertions(+), 11 deletions(-) Index: llvm/lib/CodeGen/RegAllocIterativeScan.cpp diff -u llvm/lib/CodeGen/RegAllocIterativeScan.cpp:1.20 llvm/lib/CodeGen/RegAllocIterativeScan.cpp:1.21 --- llvm/lib/CodeGen/RegAllocIterativeScan.cpp:1.20 Sat Jan 8 13:53:50 2005 +++ llvm/lib/CodeGen/RegAllocIterativeScan.cpp Sun Jan 23 16:45:12 2005 @@ -51,6 +51,7 @@ const TargetMachine* tm_; const MRegisterInfo* mri_; LiveIntervals* li_; + bool *PhysRegsUsed; typedef std::vector IntervalPtrs; IntervalPtrs unhandled_, fixed_, active_, inactive_, handled_, spilled_; @@ -145,6 +146,11 @@ tm_ = &fn.getTarget(); mri_ = tm_->getRegisterInfo(); li_ = &getAnalysis(); + + PhysRegsUsed = new bool[mri_->getNumRegs()]; + std::fill(PhysRegsUsed, PhysRegsUsed+mri_->getNumRegs(), false); + fn.setUsedPhysRegs(PhysRegsUsed); + if (!prt_.get()) prt_.reset(new PhysRegTracker(*mri_)); vrm_.reset(new VirtRegMap(*mf_)); if (!spiller_.get()) spiller_.reset(createSpiller()); @@ -256,8 +262,10 @@ for (LiveIntervals::iterator i = li_->begin(), e = li_->end(); i != e; ++i){ unhandled_.push_back(&i->second); - if (MRegisterInfo::isPhysicalRegister(i->second.reg)) + if (MRegisterInfo::isPhysicalRegister(i->second.reg)) { + PhysRegsUsed[i->second.reg] = true; fixed_.push_back(&i->second); + } } } Index: llvm/lib/CodeGen/RegAllocLinearScan.cpp diff -u llvm/lib/CodeGen/RegAllocLinearScan.cpp:1.106 llvm/lib/CodeGen/RegAllocLinearScan.cpp:1.107 --- llvm/lib/CodeGen/RegAllocLinearScan.cpp:1.106 Sat Jan 8 13:53:50 2005 +++ llvm/lib/CodeGen/RegAllocLinearScan.cpp Sun Jan 23 16:45:12 2005 @@ -48,6 +48,7 @@ const TargetMachine* tm_; const MRegisterInfo* mri_; LiveIntervals* li_; + bool *PhysRegsUsed; /// handled_ - Intervals are added to the handled_ set in the order of their /// start value. This is uses for backtracking. @@ -139,6 +140,10 @@ mri_ = tm_->getRegisterInfo(); li_ = &getAnalysis(); + PhysRegsUsed = new bool[mri_->getNumRegs()]; + std::fill(PhysRegsUsed, PhysRegsUsed+mri_->getNumRegs(), false); + fn.setUsedPhysRegs(PhysRegsUsed); + if (!prt_.get()) prt_.reset(new PhysRegTracker(*mri_)); vrm_.reset(new VirtRegMap(*mf_)); if (!spiller_.get()) spiller_.reset(createSpiller()); @@ -147,6 +152,7 @@ linearScan(); + // Rewrite spill code and update the PhysRegsUsed set. spiller_->runOnMachineFunction(*mf_, *vrm_); vrm_.reset(); // Free the VirtRegMap @@ -170,9 +176,10 @@ "interval sets should be empty on initialization"); for (LiveIntervals::iterator i = li_->begin(), e = li_->end(); i != e; ++i) { - if (MRegisterInfo::isPhysicalRegister(i->second.reg)) + if (MRegisterInfo::isPhysicalRegister(i->second.reg)) { + PhysRegsUsed[i->second.reg] = true; fixed_.push_back(std::make_pair(&i->second, i->second.begin())); - else + } else unhandled_.push(&i->second); } } Index: llvm/lib/CodeGen/VirtRegMap.cpp diff -u llvm/lib/CodeGen/VirtRegMap.cpp:1.34 llvm/lib/CodeGen/VirtRegMap.cpp:1.35 --- llvm/lib/CodeGen/VirtRegMap.cpp:1.34 Fri Jan 14 09:54:24 2005 +++ llvm/lib/CodeGen/VirtRegMap.cpp Sun Jan 23 16:45:13 2005 @@ -133,13 +133,14 @@ }; } -bool SimpleSpiller::runOnMachineFunction(MachineFunction& MF, - const VirtRegMap& VRM) { +bool SimpleSpiller::runOnMachineFunction(MachineFunction &MF, + const VirtRegMap &VRM) { DEBUG(std::cerr << "********** REWRITE MACHINE CODE **********\n"); DEBUG(std::cerr << "********** Function: " << MF.getFunction()->getName() << '\n'); - const TargetMachine& TM = MF.getTarget(); - const MRegisterInfo& MRI = *TM.getRegisterInfo(); + const TargetMachine &TM = MF.getTarget(); + const MRegisterInfo &MRI = *TM.getRegisterInfo(); + bool *PhysRegsUsed = MF.getUsedPhysregs(); // LoadedRegs - Keep track of which vregs are loaded, so that we only load // each vreg once (in the case where a spilled vreg is used by multiple @@ -177,6 +178,7 @@ ++NumStores; } } + PhysRegsUsed[PhysReg] = true; MI.SetMachineOperandReg(i, PhysReg); } } @@ -296,6 +298,8 @@ // same stack slot, the original store is deleted. std::map MaybeDeadStores; + bool *PhysRegsUsed = MBB.getParent()->getUsedPhysregs(); + for (MachineBasicBlock::iterator MII = MBB.begin(), E = MBB.end(); MII != E; ) { MachineInstr &MI = *MII; @@ -313,7 +317,9 @@ if (!VRM.hasStackSlot(VirtReg)) { // This virtual register was assigned a physreg! - MI.SetMachineOperandReg(i, VRM.getPhys(VirtReg)); + unsigned Phys = VRM.getPhys(VirtReg); + PhysRegsUsed[Phys] = true; + MI.SetMachineOperandReg(i, Phys); } else { // Is this virtual register a spilled value? if (MO.isUse()) { @@ -397,7 +403,7 @@ } } ContinueReload: - + PhysRegsUsed[PhysReg] = true; MRI->loadRegFromStackSlot(MBB, &MI, PhysReg, StackSlot); // This invalidates PhysReg. ClobberPhysReg(PhysReg, SpillSlotsAvailable, PhysRegsAvailable); @@ -429,9 +435,11 @@ // Loop over all of the implicit defs, clearing them from our available // sets. - const TargetInstrDescriptor &InstrDesc = TII->get(MI.getOpcode()); - for (const unsigned* ImpDef = InstrDesc.ImplicitDefs; *ImpDef; ++ImpDef) + for (const unsigned *ImpDef = TII->getImplicitDefs(MI.getOpcode()); + *ImpDef; ++ImpDef) { + PhysRegsUsed[*ImpDef] = true; ClobberPhysReg(*ImpDef, SpillSlotsAvailable, PhysRegsAvailable); + } DEBUG(std::cerr << '\t' << MI); @@ -516,6 +524,7 @@ else PhysReg = MO.getReg(); + PhysRegsUsed[PhysReg] = true; MRI->storeRegToStackSlot(MBB, next(MII), PhysReg, StackSlot); DEBUG(std::cerr << "Store:\t" << *next(MII)); MI.SetMachineOperandReg(i, PhysReg); From lattner at cs.uiuc.edu Sun Jan 23 16:52:11 2005 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Sun, 23 Jan 2005 16:52:11 -0600 Subject: [llvm-commits] CVS: llvm/lib/CodeGen/RegAllocLocal.cpp Message-ID: <200501232252.j0NMqBwF013564@apoc.cs.uiuc.edu> Changes in directory llvm/lib/CodeGen: RegAllocLocal.cpp updated: 1.70 -> 1.71 --- Log message: Update this pass to set PhysRegsUsed info in MachineFunction. --- Diffs of the changes: (+13 -1) RegAllocLocal.cpp | 14 +++++++++++++- 1 files changed, 13 insertions(+), 1 deletion(-) Index: llvm/lib/CodeGen/RegAllocLocal.cpp diff -u llvm/lib/CodeGen/RegAllocLocal.cpp:1.70 llvm/lib/CodeGen/RegAllocLocal.cpp:1.71 --- llvm/lib/CodeGen/RegAllocLocal.cpp:1.70 Tue Oct 26 10:35:58 2004 +++ llvm/lib/CodeGen/RegAllocLocal.cpp Sun Jan 23 16:51:56 2005 @@ -38,6 +38,7 @@ MachineFunction *MF; const MRegisterInfo *RegInfo; LiveVariables *LV; + bool *PhysRegsEverUsed; // StackSlotForVirtReg - Maps virtual regs to the frame index where these // values are spilled. @@ -478,6 +479,7 @@ RegInfo->loadRegFromStackSlot(MBB, MI, PhysReg, FrameIndex); ++NumLoads; // Update statistics + PhysRegsEverUsed[PhysReg] = true; MI->SetMachineOperandReg(OpNum, PhysReg); // Assign the input register return MI; } @@ -547,6 +549,7 @@ if (MO.isDef() && MO.isRegister() && MO.getReg() && MRegisterInfo::isPhysicalRegister(MO.getReg())) { unsigned Reg = MO.getReg(); + PhysRegsEverUsed[Reg] = true; spillPhysReg(MBB, MI, Reg, true); // Spill any existing value in the reg PhysRegsUsed[Reg] = 0; // It is free and reserved now PhysRegsUseOrder.push_back(Reg); @@ -554,6 +557,7 @@ *AliasSet; ++AliasSet) { PhysRegsUseOrder.push_back(*AliasSet); PhysRegsUsed[*AliasSet] = 0; // It is free and reserved now + PhysRegsEverUsed[*AliasSet] = true; } } } @@ -565,16 +569,19 @@ spillPhysReg(MBB, MI, Reg, true); PhysRegsUseOrder.push_back(Reg); PhysRegsUsed[Reg] = 0; // It is free and reserved now + PhysRegsEverUsed[Reg] = true; + for (const unsigned *AliasSet = RegInfo->getAliasSet(Reg); *AliasSet; ++AliasSet) { PhysRegsUseOrder.push_back(*AliasSet); PhysRegsUsed[*AliasSet] = 0; // It is free and reserved now + PhysRegsEverUsed[*AliasSet] = true; } } // Okay, we have allocated all of the source operands and spilled any values // that would be destroyed by defs of this instruction. Loop over the - // implicit defs and assign them to a register, spilling incoming values if + // explicit defs and assign them to a register, spilling incoming values if // we need to scavenge a register. // for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { @@ -587,6 +594,7 @@ // If DestVirtReg already has a value, use it. if (!(DestPhysReg = getVirt2PhysRegMapSlot(DestVirtReg))) DestPhysReg = getReg(MBB, MI, DestVirtReg); + PhysRegsEverUsed[DestPhysReg] = true; markVirtRegModified(DestVirtReg); MI->SetMachineOperandReg(i, DestPhysReg); // Assign the output register } @@ -652,6 +660,10 @@ RegInfo = TM->getRegisterInfo(); LV = &getAnalysis(); + PhysRegsEverUsed = new bool[RegInfo->getNumRegs()]; + std::fill(PhysRegsEverUsed, PhysRegsEverUsed+RegInfo->getNumRegs(), false); + Fn.setUsedPhysRegs(PhysRegsEverUsed); + PhysRegsUsed.assign(RegInfo->getNumRegs(), -1); // initialize the virtual->physical register map to have a 'null' From lattner at cs.uiuc.edu Sun Jan 23 16:56:00 2005 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Sun, 23 Jan 2005 16:56:00 -0600 Subject: [llvm-commits] CVS: llvm/lib/CodeGen/RegAllocSimple.cpp Message-ID: <200501232256.j0NMu0vd013679@apoc.cs.uiuc.edu> Changes in directory llvm/lib/CodeGen: RegAllocSimple.cpp updated: 1.61 -> 1.62 --- Log message: Update physregsused info. --- Diffs of the changes: (+18 -10) RegAllocSimple.cpp | 28 ++++++++++++++++++---------- 1 files changed, 18 insertions(+), 10 deletions(-) Index: llvm/lib/CodeGen/RegAllocSimple.cpp diff -u llvm/lib/CodeGen/RegAllocSimple.cpp:1.61 llvm/lib/CodeGen/RegAllocSimple.cpp:1.62 --- llvm/lib/CodeGen/RegAllocSimple.cpp:1.61 Wed Sep 1 17:55:35 2004 +++ llvm/lib/CodeGen/RegAllocSimple.cpp Sun Jan 23 16:55:45 2005 @@ -35,6 +35,7 @@ MachineFunction *MF; const TargetMachine *TM; const MRegisterInfo *RegInfo; + bool *PhysRegsEverUsed; // StackSlotForVirtReg - Maps SSA Regs => frame index on the stack where // these values are spilled @@ -118,8 +119,10 @@ assert(RI+regIdx != RE && "Not enough registers!"); unsigned PhysReg = *(RI+regIdx); - if (!RegsUsed[PhysReg]) + if (!RegsUsed[PhysReg]) { + PhysRegsEverUsed[PhysReg] = true; return PhysReg; + } } } @@ -156,19 +159,20 @@ RegsUsed.resize(RegInfo->getNumRegs()); - // a preliminary pass that will invalidate any registers that - // are used by the instruction (including implicit uses) + // This is a preliminary pass that will invalidate any registers that are + // used by the instruction (including implicit uses). unsigned Opcode = MI->getOpcode(); const TargetInstrDescriptor &Desc = TM->getInstrInfo()->get(Opcode); - const unsigned *Regs = Desc.ImplicitUses; - while (*Regs) - RegsUsed[*Regs++] = true; + const unsigned *Regs; + for (Regs = Desc.ImplicitUses; *Regs; ++Regs) + RegsUsed[*Regs] = true; - Regs = Desc.ImplicitDefs; - while (*Regs) - RegsUsed[*Regs++] = true; + for (Regs = Desc.ImplicitDefs; *Regs; ++Regs) { + RegsUsed[*Regs] = true; + PhysRegsEverUsed[*Regs] = true; + } - // Loop over uses, move from memory into registers + // Loop over uses, move from memory into registers. for (int i = MI->getNumOperands() - 1; i >= 0; --i) { MachineOperand &op = MI->getOperand(i); @@ -225,6 +229,10 @@ TM = &MF->getTarget(); RegInfo = TM->getRegisterInfo(); + PhysRegsEverUsed = new bool[RegInfo->getNumRegs()]; + std::fill(PhysRegsEverUsed, PhysRegsEverUsed+RegInfo->getNumRegs(), false); + Fn.setUsedPhysRegs(PhysRegsEverUsed); + // Loop over all of the basic blocks, eliminating virtual register references for (MachineFunction::iterator MBB = Fn.begin(), MBBe = Fn.end(); MBB != MBBe; ++MBB) From lattner at cs.uiuc.edu Sun Jan 23 16:57:42 2005 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Sun, 23 Jan 2005 16:57:42 -0600 Subject: [llvm-commits] CVS: llvm/include/llvm/CodeGen/MachineFunction.h Message-ID: <200501232257.j0NMvgsU013707@apoc.cs.uiuc.edu> Changes in directory llvm/include/llvm/CodeGen: MachineFunction.h updated: 1.46 -> 1.47 --- Log message: Add an accessor. --- Diffs of the changes: (+2 -1) MachineFunction.h | 3 ++- 1 files changed, 2 insertions(+), 1 deletion(-) Index: llvm/include/llvm/CodeGen/MachineFunction.h diff -u llvm/include/llvm/CodeGen/MachineFunction.h:1.46 llvm/include/llvm/CodeGen/MachineFunction.h:1.47 --- llvm/include/llvm/CodeGen/MachineFunction.h:1.46 Sun Jan 23 16:13:36 2005 +++ llvm/include/llvm/CodeGen/MachineFunction.h Sun Jan 23 16:57:27 2005 @@ -154,7 +154,8 @@ /// getUsedPhysregs - This returns the UsedPhysRegs array. This returns null /// before register allocation. - const bool *getUsedPhysregs() { return UsedPhysRegs; } + bool *getUsedPhysregs() { return UsedPhysRegs; } + const bool *getUsedPhysregs() const { return UsedPhysRegs; } /// isPhysRegUsed - Return true if the specified register is used in this /// function. This only works after register allocation. From lattner at cs.uiuc.edu Sun Jan 23 17:13:27 2005 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Sun, 23 Jan 2005 17:13:27 -0600 Subject: [llvm-commits] CVS: llvm/lib/CodeGen/PrologEpilogInserter.cpp Message-ID: <200501232313.j0NNDRwF016805@apoc.cs.uiuc.edu> Changes in directory llvm/lib/CodeGen: PrologEpilogInserter.cpp updated: 1.40 -> 1.41 --- Log message: Simplify/speedup the PEI by not having to scan for uses of the callee saved registers. This information is computed directly by the register allocator now. --- Diffs of the changes: (+5 -19) PrologEpilogInserter.cpp | 24 +++++------------------- 1 files changed, 5 insertions(+), 19 deletions(-) Index: llvm/lib/CodeGen/PrologEpilogInserter.cpp diff -u llvm/lib/CodeGen/PrologEpilogInserter.cpp:1.40 llvm/lib/CodeGen/PrologEpilogInserter.cpp:1.41 --- llvm/lib/CodeGen/PrologEpilogInserter.cpp:1.40 Sun Jan 23 15:45:01 2005 +++ llvm/lib/CodeGen/PrologEpilogInserter.cpp Sun Jan 23 17:13:12 2005 @@ -111,8 +111,6 @@ FrameSetupOpcode == -1 && FrameDestroyOpcode == -1) return; - // This bitset contains an entry for each physical register for the target... - std::vector ModifiedRegs(RegInfo->getNumRegs()); unsigned MaxCallFrameSize = 0; bool HasCalls = false; @@ -127,19 +125,6 @@ HasCalls = true; RegInfo->eliminateCallFramePseudoInstr(Fn, *BB, I++); } else { - for (unsigned i = 0, e = I->getNumOperands(); i != e; ++i) { - MachineOperand &MO = I->getOperand(i); - if (MO.isRegister() && MO.isDef()) { - assert(MRegisterInfo::isPhysicalRegister(MO.getReg()) && - "Register allocation must be performed!"); - ModifiedRegs[MO.getReg()] = true; // Register is modified - } - - // Mark any implicitly defined registers as being modified. - for (const unsigned *ImpDefs = TII.getImplicitDefs(I->getOpcode()); - *ImpDefs; ++ImpDefs) - ModifiedRegs[*ImpDefs] = true; - } ++I; } @@ -150,14 +135,15 @@ // Now figure out which *callee saved* registers are modified by the current // function, thus needing to be saved and restored in the prolog/epilog. // + const bool *PhysRegsUsed = Fn.getUsedPhysregs(); for (unsigned i = 0; CSRegs[i]; ++i) { unsigned Reg = CSRegs[i]; - if (ModifiedRegs[Reg]) { - RegsToSave.push_back(Reg); // If modified register... + if (PhysRegsUsed[Reg]) { + RegsToSave.push_back(Reg); // If the reg is modified, save it! } else { for (const unsigned *AliasSet = RegInfo->getAliasSet(Reg); - *AliasSet; ++AliasSet) { // Check alias registers too... - if (ModifiedRegs[*AliasSet]) { + *AliasSet; ++AliasSet) { // Check alias registers too. + if (PhysRegsUsed[*AliasSet]) { RegsToSave.push_back(Reg); break; } From lattner at cs.uiuc.edu Sun Jan 23 17:14:12 2005 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Sun, 23 Jan 2005 17:14:12 -0600 Subject: [llvm-commits] CVS: llvm/lib/Target/X86/X86FloatingPoint.cpp Message-ID: <200501232314.j0NNECD7016818@apoc.cs.uiuc.edu> Changes in directory llvm/lib/Target/X86: X86FloatingPoint.cpp updated: 1.40 -> 1.41 --- Log message: Allow the FP stackifier to completely ignore functions that do not use FP at all. This should speed up the X86 backend fairly significantly on integer codes. Now if only we didn't have to compute livevar still... ;-) --- Diffs of the changes: (+15 -0) X86FloatingPoint.cpp | 15 +++++++++++++++ 1 files changed, 15 insertions(+) Index: llvm/lib/Target/X86/X86FloatingPoint.cpp diff -u llvm/lib/Target/X86/X86FloatingPoint.cpp:1.40 llvm/lib/Target/X86/X86FloatingPoint.cpp:1.41 --- llvm/lib/Target/X86/X86FloatingPoint.cpp:1.40 Wed Sep 1 17:55:36 2004 +++ llvm/lib/Target/X86/X86FloatingPoint.cpp Sun Jan 23 17:13:59 2005 @@ -157,6 +157,21 @@ /// register references into FP stack references. /// bool FPS::runOnMachineFunction(MachineFunction &MF) { + // We only need to run this pass if there are any FP registers used in this + // function. If it is all integer, there is nothing for us to do! + const bool *PhysRegsUsed = MF.getUsedPhysregs(); + bool FPIsUsed = false; + + assert(X86::FP6 == X86::FP0+6 && "Register enums aren't sorted right!"); + for (unsigned i = 0; i <= 6; ++i) + if (PhysRegsUsed[X86::FP0+i]) { + FPIsUsed = true; + break; + } + + // Early exit. + if (!FPIsUsed) return false; + LV = &getAnalysis(); StackTop = 0; From lattner at cs.uiuc.edu Sun Jan 23 17:19:59 2005 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Sun, 23 Jan 2005 17:19:59 -0600 Subject: [llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp Message-ID: <200501232319.j0NNJxgG018182@apoc.cs.uiuc.edu> Changes in directory llvm/lib/CodeGen/SelectionDAG: LegalizeDAG.cpp updated: 1.52 -> 1.53 --- Log message: Silence optimized warnings. --- Diffs of the changes: (+1 -1) LegalizeDAG.cpp | 2 +- 1 files changed, 1 insertion(+), 1 deletion(-) Index: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp diff -u llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.52 llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.53 --- llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.52 Sat Jan 22 22:42:50 2005 +++ llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp Sun Jan 23 17:19:44 2005 @@ -1454,7 +1454,7 @@ SDOperand InChain = FindInputOutputChains(Source.Val, OutChain, DAG.getEntryNode()); - const char *FnName; + const char *FnName = 0; if (isSigned) { if (DestTy == MVT::f32) FnName = "__floatdisf"; From lattner at cs.uiuc.edu Sun Jan 23 17:20:21 2005 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Sun, 23 Jan 2005 17:20:21 -0600 Subject: [llvm-commits] CVS: llvm/lib/Target/X86/X86ISelPattern.cpp Message-ID: <200501232320.j0NNKLXf018300@apoc.cs.uiuc.edu> Changes in directory llvm/lib/Target/X86: X86ISelPattern.cpp updated: 1.86 -> 1.87 --- Log message: Silence a warning. --- Diffs of the changes: (+1 -1) X86ISelPattern.cpp | 2 +- 1 files changed, 1 insertion(+), 1 deletion(-) Index: llvm/lib/Target/X86/X86ISelPattern.cpp diff -u llvm/lib/Target/X86/X86ISelPattern.cpp:1.86 llvm/lib/Target/X86/X86ISelPattern.cpp:1.87 --- llvm/lib/Target/X86/X86ISelPattern.cpp:1.86 Fri Jan 21 15:43:02 2005 +++ llvm/lib/Target/X86/X86ISelPattern.cpp Sun Jan 23 17:20:06 2005 @@ -2587,7 +2587,7 @@ // Handle: [mem] op= CST SDOperand Op0 = StVal.getOperand(0); SDOperand Op1 = StVal.getOperand(1); - unsigned Opc; + unsigned Opc = 0; if (ConstantSDNode *CN = dyn_cast(Op1)) { switch (Op0.getValueType()) { // Use Op0's type because of shifts. default: break; From lattner at cs.uiuc.edu Sun Jan 23 19:40:33 2005 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Sun, 23 Jan 2005 19:40:33 -0600 Subject: [llvm-commits] CVS: llvm/lib/Target/SparcV9/SparcV9BurgISel.cpp Message-ID: <200501240140.j0O1eXXb025603@apoc.cs.uiuc.edu> Changes in directory llvm/lib/Target/SparcV9: SparcV9BurgISel.cpp updated: 1.14 -> 1.15 --- Log message: Fix a spurious warning. --- Diffs of the changes: (+1 -1) SparcV9BurgISel.cpp | 2 +- 1 files changed, 1 insertion(+), 1 deletion(-) Index: llvm/lib/Target/SparcV9/SparcV9BurgISel.cpp diff -u llvm/lib/Target/SparcV9/SparcV9BurgISel.cpp:1.14 llvm/lib/Target/SparcV9/SparcV9BurgISel.cpp:1.15 --- llvm/lib/Target/SparcV9/SparcV9BurgISel.cpp:1.14 Mon Jan 17 00:47:26 2005 +++ llvm/lib/Target/SparcV9/SparcV9BurgISel.cpp Sun Jan 23 19:40:18 2005 @@ -627,7 +627,7 @@ bool smallNegValue =isSigned && sC < 0 && sC != -sC && -sC < (int32_t)MAXSIMM; //Create TmpInstruction for intermediate values - TmpInstruction *tmpReg; + TmpInstruction *tmpReg = 0; // Set the high 22 bits in dest if non-zero and simm13 field of OR not enough if (!smallNegValue && (C & ~MAXLO) && C > MAXSIMM) { From lattner at cs.uiuc.edu Sun Jan 23 20:08:50 2005 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Sun, 23 Jan 2005 20:08:50 -0600 Subject: [llvm-commits] CVS: llvm/include/llvm/Type.h Message-ID: <200501240208.j0O28oFf005731@apoc.cs.uiuc.edu> Changes in directory llvm/include/llvm: Type.h updated: 1.68 -> 1.69 --- Log message: This giant patch speeds up Type::isSized(). Before, this would have to search large nested types over and over again to determine if they are sized or not. Now, isSized() is able to make snap decisions about all concrete types, which are a common occurance (and includes all primitives). On 177.mesa, this speeds up DSE from 39.5s -> 21.3s and GCSE from 13.2s -> 11.3s, reducing gccas time from 80s -> 61s (this is a debug build). DSE and GCSE are still too slow on this testcase, but this is a simple improvement. --- Diffs of the changes: (+1 -2) Type.h | 3 +-- 1 files changed, 1 insertion(+), 2 deletions(-) Index: llvm/include/llvm/Type.h diff -u llvm/include/llvm/Type.h:1.68 llvm/include/llvm/Type.h:1.69 --- llvm/include/llvm/Type.h:1.68 Mon Dec 13 10:28:53 2004 +++ llvm/include/llvm/Type.h Sun Jan 23 20:08:34 2005 @@ -201,8 +201,7 @@ /// TargetData subsystem to do this. /// bool isSized() const { - return (ID >= BoolTyID && ID <= DoubleTyID) || ID == PointerTyID || - isSizedDerivedType(); + return !isAbstract() || ID == PointerTyID || isSizedDerivedType(); } /// getPrimitiveSize - Return the basic size of this type if it is a primitive From lattner at cs.uiuc.edu Sun Jan 23 22:04:57 2005 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Sun, 23 Jan 2005 22:04:57 -0600 Subject: [llvm-commits] CVS: llvm-test/Makefile.f2c Message-ID: <200501240404.j0O44vXX024934@apoc.cs.uiuc.edu> Changes in directory llvm-test: Makefile.f2c updated: 1.4 -> 1.5 --- Log message: Successfully internalize the f2c tests. --- Diffs of the changes: (+5 -1) Makefile.f2c | 6 +++++- 1 files changed, 5 insertions(+), 1 deletion(-) Index: llvm-test/Makefile.f2c diff -u llvm-test/Makefile.f2c:1.4 llvm-test/Makefile.f2c:1.5 --- llvm-test/Makefile.f2c:1.4 Mon Oct 25 15:21:35 2004 +++ llvm-test/Makefile.f2c Sun Jan 23 22:04:42 2005 @@ -29,7 +29,11 @@ %.c: %.f $(F2C) $< > /dev/null 2>&1 - + CPPFLAGS = -I$(F2C_INC) LDFLAGS += -L$(F2C_LIB) -lf2c + +# 'main' is defined in the f2c runtime library. The function exported from the +# program is named MAIN__ +EXTRA_LINKTIME_OPT_FLAGS += -internalize-public-api-list=MAIN__ \ No newline at end of file From lattner at cs.uiuc.edu Sun Jan 23 22:05:08 2005 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Sun, 23 Jan 2005 22:05:08 -0600 Subject: [llvm-commits] CVS: llvm-test/Makefile.programs Message-ID: <200501240405.j0O458MO024941@apoc.cs.uiuc.edu> Changes in directory llvm-test: Makefile.programs updated: 1.146 -> 1.147 --- Log message: Allow extra options to be specified for gccld. --- Diffs of the changes: (+1 -1) Makefile.programs | 2 +- 1 files changed, 1 insertion(+), 1 deletion(-) Index: llvm-test/Makefile.programs diff -u llvm-test/Makefile.programs:1.146 llvm-test/Makefile.programs:1.147 --- llvm-test/Makefile.programs:1.146 Sun Jan 16 20:03:01 2005 +++ llvm-test/Makefile.programs Sun Jan 23 22:04:25 2005 @@ -207,7 +207,7 @@ $(PROGRAMS_TO_TEST:%=Output/%.llvm.bc): \ Output/%.llvm.bc: Output/%.linked.bc $(LGCCLDPROG) - -$(LGCCLD) $(STATS) $< -lc $(LIBS) -lcrtend -o Output/$*.llvm + -$(LGCCLD) $(STATS) $(EXTRA_LINKTIME_OPT_FLAGS) $< -lc $(LIBS) -lcrtend -o Output/$*.llvm ifneq ($(OPTPASSES),) -$(LOPT) -q $(OPTPASSES) < $@ > $@.tmp $(MV) -f $@.tmp $@