From alenhar2 at cs.uiuc.edu Tue May 31 13:36:02 2005 From: alenhar2 at cs.uiuc.edu (Andrew Lenharth) Date: Tue, 31 May 2005 13:36:02 -0500 Subject: [llvm-commits] CVS: llvm/lib/Target/Alpha/AlphaISelPattern.cpp Message-ID: <200505311836.NAA01646@cypher.cs.uiuc.edu> Changes in directory llvm/lib/Target/Alpha: AlphaISelPattern.cpp updated: 1.114 -> 1.115 --- Log message: switch to the new live in thing --- Diffs of the changes: (+60 -65) AlphaISelPattern.cpp | 125 ++++++++++++++++++++++++--------------------------- 1 files changed, 60 insertions(+), 65 deletions(-) Index: llvm/lib/Target/Alpha/AlphaISelPattern.cpp diff -u llvm/lib/Target/Alpha/AlphaISelPattern.cpp:1.114 llvm/lib/Target/Alpha/AlphaISelPattern.cpp:1.115 --- llvm/lib/Target/Alpha/AlphaISelPattern.cpp:1.114 Thu May 26 13:18:34 2005 +++ llvm/lib/Target/Alpha/AlphaISelPattern.cpp Tue May 31 13:35:43 2005 @@ -140,6 +140,17 @@ }; } +/// AddLiveIn - This helper function adds the specified physical register to the +/// MachineFunction as a live in value. It also creates a corresponding virtual +/// register for it. +static unsigned AddLiveIn(MachineFunction &MF, unsigned PReg, + TargetRegisterClass *RC) { + assert(RC->contains(PReg) && "Not the correct regclass!"); + unsigned VReg = MF.getSSARegMap()->createVirtualRegister(RC); + MF.addLiveIn(PReg, VReg); + return VReg; +} + //http://www.cs.arizona.edu/computer.help/policy/DIGITAL_unix/AA-PY8AC-TET1_html/callCH3.html#BLOCK21 //For now, just use variable size stack frame format @@ -162,14 +173,10 @@ AlphaTargetLowering::LowerArguments(Function &F, SelectionDAG &DAG) { std::vector ArgValues; - std::vector LS; - SDOperand Chain = DAG.getRoot(); - // assert(0 && "TODO"); MachineFunction &MF = DAG.getMachineFunction(); MachineFrameInfo*MFI = MF.getFrameInfo(); - GP = MF.getSSARegMap()->createVirtualRegister(getRegClassFor(MVT::i64)); MachineBasicBlock& BB = MF.front(); //Handle the return address @@ -181,64 +188,35 @@ Alpha::F19, Alpha::F20, Alpha::F21}; int count = 0; - //Def incoming registers - { - Function::arg_iterator I = F.arg_begin(); - Function::arg_iterator E = F.arg_end(); - for (int i = 0; i < 6; ++i) - { - if (F.isVarArg()) { - MF.addLiveIn(args_int[i]); - MF.addLiveIn(args_float[i]); -// BuildMI(&BB, Alpha::IDEF, 0, args_int[i]); -// BuildMI(&BB, Alpha::IDEF, 0, args_float[i]); - } else if (I != E) - { - if(MVT::isInteger(getValueType(I->getType()))) - MF.addLiveIn(args_int[i]); -// BuildMI(&BB, Alpha::IDEF, 0, args_int[i]); - else - MF.addLiveIn(args_float[i]); -// BuildMI(&BB, Alpha::IDEF, 0, args_float[i]); - ++I; - } - } - } - - MF.addLiveIn(Alpha::R29); -// BuildMI(&BB, Alpha::IDEF, 0, Alpha::R29); - BuildMI(&BB, Alpha::BIS, 2, GP).addReg(Alpha::R29).addReg(Alpha::R29); + GP = AddLiveIn(MF, Alpha::R29, getRegClassFor(MVT::i64)); for (Function::arg_iterator I = F.arg_begin(), E = F.arg_end(); I != E; ++I) { - SDOperand newroot, argt; + SDOperand argt; if (count < 6) { unsigned Vreg; MVT::ValueType VT = getValueType(I->getType()); - switch (getValueType(I->getType())) { + switch (VT) { default: std::cerr << "Unknown Type " << VT << "\n"; abort(); case MVT::f64: case MVT::f32: - Vreg = MF.getSSARegMap()->createVirtualRegister(getRegClassFor(VT)); - BuildMI(&BB, Alpha::CPYS, 2, Vreg).addReg(args_float[count]).addReg(args_float[count]); - argt = newroot = DAG.getCopyFromReg(Vreg, - getValueType(I->getType()), - Chain); + args_float[count] = AddLiveIn(MF,args_float[count], getRegClassFor(VT)); + argt = DAG.getCopyFromReg(args_float[count], VT, DAG.getRoot()); break; case MVT::i1: case MVT::i8: case MVT::i16: case MVT::i32: case MVT::i64: - Vreg = MF.getSSARegMap()->createVirtualRegister(getRegClassFor(MVT::i64)); - BuildMI(&BB, Alpha::BIS, 2, Vreg).addReg(args_int[count]).addReg(args_int[count]); - argt = newroot = DAG.getCopyFromReg(Vreg, MVT::i64, Chain); - if (getValueType(I->getType()) != MVT::i64) - argt = DAG.getNode(ISD::TRUNCATE, getValueType(I->getType()), newroot); + args_int[count] = AddLiveIn(MF, args_int[count], getRegClassFor(VT)); + argt = DAG.getCopyFromReg(args_int[count], VT, DAG.getRoot()); + // if (VT != MVT::i64) + // argt = DAG.getNode(ISD::TRUNCATE, VT, argt); break; } + DAG.setRoot(argt.getValue(1)); } else { //more args // Create the frame index object for this incoming parameter... int FI = MFI->CreateFixedObject(8, 8 * (count - 6)); @@ -246,40 +224,35 @@ // Create the SelectionDAG nodes corresponding to a load //from this parameter SDOperand FIN = DAG.getFrameIndex(FI, MVT::i64); - argt = newroot = DAG.getLoad(getValueType(I->getType()), - DAG.getEntryNode(), FIN, DAG.getSrcValue(NULL)); + argt = DAG.getLoad(getValueType(I->getType()), + DAG.getEntryNode(), FIN, DAG.getSrcValue(NULL)); } ++count; - LS.push_back(newroot.getValue(1)); ArgValues.push_back(argt); } // If the functions takes variable number of arguments, copy all regs to stack - if (F.isVarArg()) - for (int i = 0; i < 6; ++i) - { - unsigned Vreg = MF.getSSARegMap()->createVirtualRegister(getRegClassFor(MVT::i64)); - BuildMI(&BB, Alpha::BIS, 2, Vreg).addReg(args_int[i]).addReg(args_int[i]); - SDOperand argt = DAG.getCopyFromReg(Vreg, MVT::i64, Chain); + if (F.isVarArg()) { + std::vector LS; + for (int i = 0; i < 6; ++i) { + if (args_int[i] < 1024) + args_int[i] = AddLiveIn(MF,args_int[i], getRegClassFor(MVT::i64)); + SDOperand argt = DAG.getCopyFromReg(args_int[i], MVT::i64, DAG.getRoot()); int FI = MFI->CreateFixedObject(8, -8 * (6 - i)); SDOperand SDFI = DAG.getFrameIndex(FI, MVT::i64); - LS.push_back(DAG.getNode(ISD::STORE, MVT::Other, Chain, argt, SDFI, DAG.getSrcValue(NULL))); - - Vreg = MF.getSSARegMap()->createVirtualRegister(getRegClassFor(MVT::f64)); - BuildMI(&BB, Alpha::CPYS, 2, Vreg).addReg(args_float[i]).addReg(args_float[i]); - argt = DAG.getCopyFromReg(Vreg, MVT::f64, Chain); + LS.push_back(DAG.getNode(ISD::STORE, MVT::Other, DAG.getRoot(), argt, SDFI, DAG.getSrcValue(NULL))); + + if (args_float[i] < 1024) + args_float[i] = AddLiveIn(MF,args_float[i], getRegClassFor(MVT::f64)); + argt = DAG.getCopyFromReg(args_float[i], MVT::f64, DAG.getRoot()); FI = MFI->CreateFixedObject(8, - 8 * (12 - i)); SDFI = DAG.getFrameIndex(FI, MVT::i64); - LS.push_back(DAG.getNode(ISD::STORE, MVT::Other, Chain, argt, SDFI, DAG.getSrcValue(NULL))); + LS.push_back(DAG.getNode(ISD::STORE, MVT::Other, DAG.getRoot(), argt, SDFI, DAG.getSrcValue(NULL))); } - // If the function takes variable number of arguments, make a frame index for - // the start of the first arg value... for expansion of llvm.va_start. - // if (F.isVarArg()) - // VarArgsFrameIndex = MFI->CreateFixedObject(4, ArgOffset); - - //Set up a token factor with all the stack traffic - DAG.setRoot(DAG.getNode(ISD::TokenFactor, MVT::Other, LS)); + //Set up a token factor with all the stack traffic + DAG.setRoot(DAG.getNode(ISD::TokenFactor, MVT::Other, LS)); + } // Finally, inform the code generator which regs we return values in. switch (getValueType(F.getReturnType())) { @@ -436,6 +409,8 @@ ExprMap.clear(); CCInvMap.clear(); } + + virtual void EmitFunctionEntryCode(Function &Fn, MachineFunction &MF); unsigned SelectExpr(SDOperand N); unsigned SelectExprFP(SDOperand N, unsigned Result); @@ -455,6 +430,26 @@ }; } +void ISel::EmitFunctionEntryCode(Function &Fn, MachineFunction &MF) { + // If this function has live-in values, emit the copies from pregs to vregs at + // the top of the function, before anything else. + MachineBasicBlock *BB = MF.begin(); + if (MF.livein_begin() != MF.livein_end()) { + SSARegMap *RegMap = MF.getSSARegMap(); + for (MachineFunction::livein_iterator LI = MF.livein_begin(), + E = MF.livein_end(); LI != E; ++LI) { + const TargetRegisterClass *RC = RegMap->getRegClass(LI->second); + if (RC == Alpha::GPRCRegisterClass) { + BuildMI(BB, Alpha::BIS, 2, LI->second).addReg(LI->first).addReg(LI->first); + } else if (RC == Alpha::FPRCRegisterClass) { + BuildMI(BB, Alpha::CPYS, 2, LI->second).addReg(LI->first).addReg(LI->first); + } else { + assert(0 && "Unknown regclass!"); + } + } + } +} + //Factorize a number using the list of constants static bool factorize(int v[], int res[], int size, uint64_t c) { From alenhar2 at cs.uiuc.edu Tue May 31 13:37:41 2005 From: alenhar2 at cs.uiuc.edu (Andrew Lenharth) Date: Tue, 31 May 2005 13:37:41 -0500 Subject: [llvm-commits] CVS: llvm/lib/Target/Alpha/AlphaISelPattern.cpp Message-ID: <200505311837.NAA01656@cypher.cs.uiuc.edu> Changes in directory llvm/lib/Target/Alpha: AlphaISelPattern.cpp updated: 1.115 -> 1.116 --- Log message: switch to the new live in thing --- Diffs of the changes: (+2 -2) AlphaISelPattern.cpp | 4 ++-- 1 files changed, 2 insertions(+), 2 deletions(-) Index: llvm/lib/Target/Alpha/AlphaISelPattern.cpp diff -u llvm/lib/Target/Alpha/AlphaISelPattern.cpp:1.115 llvm/lib/Target/Alpha/AlphaISelPattern.cpp:1.116 --- llvm/lib/Target/Alpha/AlphaISelPattern.cpp:1.115 Tue May 31 13:35:43 2005 +++ llvm/lib/Target/Alpha/AlphaISelPattern.cpp Tue May 31 13:37:16 2005 @@ -212,8 +212,8 @@ case MVT::i64: args_int[count] = AddLiveIn(MF, args_int[count], getRegClassFor(VT)); argt = DAG.getCopyFromReg(args_int[count], VT, DAG.getRoot()); - // if (VT != MVT::i64) - // argt = DAG.getNode(ISD::TRUNCATE, VT, argt); + if (VT != MVT::i64) + argt = DAG.getNode(ISD::TRUNCATE, VT, argt); break; } DAG.setRoot(argt.getValue(1)); From alenhar2 at cs.uiuc.edu Tue May 31 13:42:36 2005 From: alenhar2 at cs.uiuc.edu (Andrew Lenharth) Date: Tue, 31 May 2005 13:42:36 -0500 Subject: [llvm-commits] CVS: llvm/lib/Target/Alpha/AlphaISelPattern.cpp Message-ID: <200505311842.NAA01669@cypher.cs.uiuc.edu> Changes in directory llvm/lib/Target/Alpha: AlphaISelPattern.cpp updated: 1.116 -> 1.117 --- Log message: switch to the new live in thing. Really, this time it works --- Diffs of the changes: (+1 -1) AlphaISelPattern.cpp | 2 +- 1 files changed, 1 insertion(+), 1 deletion(-) Index: llvm/lib/Target/Alpha/AlphaISelPattern.cpp diff -u llvm/lib/Target/Alpha/AlphaISelPattern.cpp:1.116 llvm/lib/Target/Alpha/AlphaISelPattern.cpp:1.117 --- llvm/lib/Target/Alpha/AlphaISelPattern.cpp:1.116 Tue May 31 13:37:16 2005 +++ llvm/lib/Target/Alpha/AlphaISelPattern.cpp Tue May 31 13:42:18 2005 @@ -210,7 +210,7 @@ case MVT::i16: case MVT::i32: case MVT::i64: - args_int[count] = AddLiveIn(MF, args_int[count], getRegClassFor(VT)); + args_int[count] = AddLiveIn(MF, args_int[count], getRegClassFor(MVT::i64)); argt = DAG.getCopyFromReg(args_int[count], VT, DAG.getRoot()); if (VT != MVT::i64) argt = DAG.getNode(ISD::TRUNCATE, VT, argt); From alenhar2 at cs.uiuc.edu Tue May 31 14:49:54 2005 From: alenhar2 at cs.uiuc.edu (Andrew Lenharth) Date: Tue, 31 May 2005 14:49:54 -0500 Subject: [llvm-commits] CVS: llvm/lib/Target/Alpha/AlphaISelPattern.cpp Message-ID: <200505311949.OAA01824@cypher.cs.uiuc.edu> Changes in directory llvm/lib/Target/Alpha: AlphaISelPattern.cpp updated: 1.117 -> 1.118 --- Log message: try custom expanders, doesn't seem to expand yet, so disabled --- Diffs of the changes: (+61 -0) AlphaISelPattern.cpp | 61 +++++++++++++++++++++++++++++++++++++++++++++++++++ 1 files changed, 61 insertions(+) Index: llvm/lib/Target/Alpha/AlphaISelPattern.cpp diff -u llvm/lib/Target/Alpha/AlphaISelPattern.cpp:1.117 llvm/lib/Target/Alpha/AlphaISelPattern.cpp:1.118 --- llvm/lib/Target/Alpha/AlphaISelPattern.cpp:1.117 Tue May 31 13:42:18 2005 +++ llvm/lib/Target/Alpha/AlphaISelPattern.cpp Tue May 31 14:49:34 2005 @@ -47,6 +47,24 @@ cl::Hidden); } +namespace { + // Alpha Specific DAG Nodes + namespace AlphaISD { + enum NodeType { + // Start the numbering where the builtin ops leave off. + FIRST_NUMBER = ISD::BUILTIN_OP_END, + + //Convert an int bit pattern in an FP reg to a Double or Float + //Has a dest type and a source + CVTQ, + //Move an Ireg to a FPreg + ITOF, + //Move a FPreg to an Ireg + FTOI, + }; + } +} + //===----------------------------------------------------------------------===// // AlphaTargetLowering - Alpha Implementation of the TargetLowering interface namespace { @@ -104,12 +122,19 @@ //Doesn't work yet setOperationAction(ISD::SETCC, MVT::f32, Promote); + //Try a couple things with a custom expander + //setOperationAction(ISD::SINT_TO_FP , MVT::i64 , Custom); + computeRegisterProperties(); addLegalFPImmediate(+0.0); //F31 addLegalFPImmediate(-0.0); //-F31 } + /// LowerOperation - Provide custom lowering hooks for some operations. + /// + virtual SDOperand LowerOperation(SDOperand Op, SelectionDAG &DAG); + /// LowerArguments - This hook must be implemented to indicate how we should /// lower the arguments for the specified function, into the specified DAG. virtual std::vector @@ -140,6 +165,42 @@ }; } +/// LowerOperation - Provide custom lowering hooks for some operations. +/// +SDOperand AlphaTargetLowering::LowerOperation(SDOperand Op, SelectionDAG &DAG) { + MachineFunction &MF = DAG.getMachineFunction(); + switch (Op.getOpcode()) { + default: assert(0 && "Should not custom lower this!"); +// case ISD::SINT_TO_FP: +// { +// assert (Op.getOperand(0).getValueType() == MVT::i64 +// && "only quads can be loaded from"); +// SDOperand SRC; +// if (EnableAlphaFTOI) +// { +// std::vector RTs; +// RTs.push_back(Op.getValueType()); +// std::vector Ops; +// Ops.push_back(Op.getOperand(0)); +// SRC = DAG.getNode(AlphaISD::ITOF, RTs, Ops); +// } else { +// int SSFI = MF.getFrameInfo()->CreateStackObject(8, 8); +// SDOperand StackSlot = DAG.getFrameIndex(SSFI, getPointerTy()); +// SDOperand Store = DAG.getNode(ISD::STORE, MVT::Other, DAG.getEntryNode(), +// Op.getOperand(0), StackSlot, DAG.getSrcValue(NULL)); +// SRC = DAG.getLoad(Op.getValueType(), Store.getValue(0), StackSlot, +// DAG.getSrcValue(NULL)); +// } +// std::vector RTs; +// RTs.push_back(Op.getValueType()); +// std::vector Ops; +// Ops.push_back(SRC); +// return DAG.getNode(AlphaISD::CVTQ, RTs, Ops); +// } + } +} + + /// AddLiveIn - This helper function adds the specified physical register to the /// MachineFunction as a live in value. It also creates a corresponding virtual /// register for it. From brukman at cs.uiuc.edu Wed Jun 1 12:08:56 2005 From: brukman at cs.uiuc.edu (Misha Brukman) Date: Wed, 1 Jun 2005 12:08:56 -0500 Subject: [llvm-commits] CVS: llvm-www/releases/download.html Message-ID: <200506011708.MAA18835@zion.cs.uiuc.edu> Changes in directory llvm-www/releases: download.html updated: 1.21 -> 1.22 --- Log message: We no longer host files on SourceForge.net --- Diffs of the changes: (+0 -7) download.html | 7 ------- 1 files changed, 7 deletions(-) Index: llvm-www/releases/download.html diff -u llvm-www/releases/download.html:1.21 llvm-www/releases/download.html:1.22 --- llvm-www/releases/download.html:1.21 Wed May 18 14:24:13 2005 +++ llvm-www/releases/download.html Wed Jun 1 12:08:45 2005 @@ -127,13 +127,6 @@ Binaries for FreeBSD/x86 (13M) -

Mirrors:

- - - From reid at x10sys.com Thu Jun 2 00:38:31 2005 From: reid at x10sys.com (Reid Spencer) Date: Thu, 2 Jun 2005 00:38:31 -0500 Subject: [llvm-commits] CVS: llvm/lib/System/Unix/Path.inc Message-ID: <200506020538.AAA01452@zion.cs.uiuc.edu> Changes in directory llvm/lib/System/Unix: Path.inc updated: 1.34 -> 1.35 --- Log message: Put in a hack for Cygwin that prevents mkdtemp from being used since configure seems to find it on Cygwin but linking against it fails. --- Diffs of the changes: (+5 -0) Path.inc | 5 +++++ 1 files changed, 5 insertions(+) Index: llvm/lib/System/Unix/Path.inc diff -u llvm/lib/System/Unix/Path.inc:1.34 llvm/lib/System/Unix/Path.inc:1.35 --- llvm/lib/System/Unix/Path.inc:1.34 Thu May 5 17:33:06 2005 +++ llvm/lib/System/Unix/Path.inc Thu Jun 2 00:38:20 2005 @@ -47,6 +47,11 @@ # endif #endif +// Put in a hack for Cygwin which falsely reports that the mkdtemp function +// is available when it is not. +#ifdef __CYGWIN__ +# undef HAVE_MKDTEMP +#endif namespace llvm { using namespace sys; From reid at x10sys.com Thu Jun 2 16:33:31 2005 From: reid at x10sys.com (Reid Spencer) Date: Thu, 2 Jun 2005 16:33:31 -0500 Subject: [llvm-commits] CVS: llvm/lib/Target/X86/X86JITInfo.cpp Message-ID: <200506022133.QAA01887@zion.cs.uiuc.edu> Changes in directory llvm/lib/Target/X86: X86JITInfo.cpp updated: 1.11 -> 1.12 --- Log message: Make sure that Cygwin assembly includes _ as part of function names. --- Diffs of the changes: (+9 -0) X86JITInfo.cpp | 9 +++++++++ 1 files changed, 9 insertions(+) Index: llvm/lib/Target/X86/X86JITInfo.cpp diff -u llvm/lib/Target/X86/X86JITInfo.cpp:1.11 llvm/lib/Target/X86/X86JITInfo.cpp:1.12 --- llvm/lib/Target/X86/X86JITInfo.cpp:1.11 Fri May 20 16:29:24 2005 +++ llvm/lib/Target/X86/X86JITInfo.cpp Thu Jun 2 16:33:19 2005 @@ -43,13 +43,22 @@ asm( ".text\n" ".align 8\n" +#ifdef __CYGWIN__ + ".globl _X86CompilationCallback\n" + "_X86CompilationCallback:\n" +#else ".globl X86CompilationCallback\n" "X86CompilationCallback:\n" +#endif "pushl %ebp\n" "movl %esp, %ebp\n" // Standard prologue "pushl %eax\n" "pushl %edx\n" // save EAX/EDX +#ifdef __CYGWIN__ + "call _X86CompilationCallback2\n" +#else "call X86CompilationCallback2\n" +#endif "popl %edx\n" "popl %eax\n" "popl %ebp\n" From brukman at cs.uiuc.edu Thu Jun 2 16:52:54 2005 From: brukman at cs.uiuc.edu (Misha Brukman) Date: Thu, 2 Jun 2005 16:52:54 -0500 Subject: [llvm-commits] CVS: llvm-www/OpenProjects.html Message-ID: <200506022152.QAA02153@zion.cs.uiuc.edu> Changes in directory llvm-www: OpenProjects.html updated: 1.6 -> 1.7 --- Log message: * Mention quest, an automated random C-code generator, useful for testing llvm-gcc and opt, suggested by Aaron Gray * Wrap long lines * Use to mark tools, link to their HTML-ized man pages --- Diffs of the changes: (+9 -6) OpenProjects.html | 15 +++++++++------ 1 files changed, 9 insertions(+), 6 deletions(-) Index: llvm-www/OpenProjects.html diff -u llvm-www/OpenProjects.html:1.6 llvm-www/OpenProjects.html:1.7 --- llvm-www/OpenProjects.html:1.6 Sat May 14 17:05:57 2005 +++ llvm-www/OpenProjects.html Thu Jun 2 16:52:43 2005 @@ -286,8 +286,8 @@
    -
  1. Implement GVN-PRE, a - powerful and simple Partial Redundancy Elimination algorithm for SSA form
    2. +
  2. Implement GVN-PRE, a powerful and simple Partial Redundancy Elimination +algorithm for SSA form
  3. Implement a Dependence Analysis Infrastructure
    - Design some way to represent and query dep analysis
  4. Implement a strength reduction pass
    5. @@ -354,10 +354,13 @@
  5. Write a new frontend for some other language (Java? OCaml? Forth?)
  6. Write a disassembler for machine code that would use TableGen to output MachineInstrs for transformations, optimizations, etc.
    7. -
  7. Random test vector generator: Use a C grammar to generate random C code; +
  8. Random test vector generator: Use a C grammar to generate random C code, +e.g., quest; run it through llvm-gcc, then run a random set of passes on it using opt. -Try to crash opt. When opt crashes, use bugpoint to reduce the test case and -mail the result to yourself. Repeat ad infinitum.
    9. +Try to crash opt. When +opt crashes, use bugpoint to reduce the +test case and post it to a website or mailing list. Repeat ad infinitum.
  9. Design a simple, recognizable logo.
@@ -373,7 +376,7 @@ src="http://www.w3.org/Icons/valid-html401" alt="Valid HTML 4.01!"> LLVM Compiler Infrastructure
- Last modified: $Date: 2005/05/14 22:05:57 $ + Last modified: $Date: 2005/06/02 21:52:43 $ From reid at x10sys.com Thu Jun 2 17:35:01 2005 From: reid at x10sys.com (Reid Spencer) Date: Thu, 2 Jun 2005 17:35:01 -0500 Subject: [llvm-commits] CVS: llvm/configure Message-ID: <200506022235.RAA02411@zion.cs.uiuc.edu> Changes in directory llvm: configure updated: 1.189 -> 1.190 --- Log message: Fix the definitions of LLVMGCC and LLVMGXX to include the EXEEXT (the .exe extension) on Cygwin. This fixes the last few remaining Cygwin issues. Thanks to Aaron Gray for tracking this down. --- Diffs of the changes: (+8 -6) configure | 14 ++++++++------ 1 files changed, 8 insertions(+), 6 deletions(-) Index: llvm/configure diff -u llvm/configure:1.189 llvm/configure:1.190 --- llvm/configure:1.189 Thu May 19 03:31:55 2005 +++ llvm/configure Thu Jun 2 17:34:49 2005 @@ -24625,8 +24625,10 @@ if test "$WITH_LLVMGCCDIR" = "default" ; then - # Extract the first word of "llvm-gcc", so it can be a program name with args. -set dummy llvm-gcc; ac_word=$2 + LLVMGCC="llvm-gcc${EXEEXT}" + LLVMGXX="llvm-g++${EXEEXT}" + # Extract the first word of "$LLVMGCC", so it can be a program name with args. +set dummy $LLVMGCC; ac_word=$2 echo "$as_me:$LINENO: checking for $ac_word" >&5 echo $ECHO_N "checking for $ac_word... $ECHO_C" >&6 if test "${ac_cv_path_LLVMGCC+set}" = set; then @@ -24664,8 +24666,8 @@ echo "${ECHO_T}no" >&6 fi - # Extract the first word of "llvm-g++", so it can be a program name with args. -set dummy llvm-g++; ac_word=$2 + # Extract the first word of "$LLVMGXX", so it can be a program name with args. +set dummy $LLVMGXX; ac_word=$2 echo "$as_me:$LINENO: checking for $ac_word" >&5 echo $ECHO_N "checking for $ac_word... $ECHO_C" >&6 if test "${ac_cv_path_LLVMGXX+set}" = set; then @@ -24704,8 +24706,8 @@ fi else - LLVMGCC=$WITH_LLVMGCCDIR/bin/llvm-gcc - LLVMGXX=$WITH_LLVMGCCDIR/bin/llvm-g++ + LLVMGCC="$WITH_LLVMGCCDIR/bin/llvm-gcc${EXEEXT}" + LLVMGXX="$WITH_LLVMGCCDIR/bin/llvm-g++${EXEEXT}" LLVMGCC=$LLVMGCC LLVMGXX=$LLVMGXX From reid at x10sys.com Thu Jun 2 17:35:01 2005 From: reid at x10sys.com (Reid Spencer) Date: Thu, 2 Jun 2005 17:35:01 -0500 Subject: [llvm-commits] CVS: llvm/autoconf/configure.ac Message-ID: <200506022235.RAA02409@zion.cs.uiuc.edu> Changes in directory llvm/autoconf: configure.ac updated: 1.184 -> 1.185 --- Log message: Fix the definitions of LLVMGCC and LLVMGXX to include the EXEEXT (the .exe extension) on Cygwin. This fixes the last few remaining Cygwin issues. Thanks to Aaron Gray for tracking this down. --- Diffs of the changes: (+6 -4) configure.ac | 10 ++++++---- 1 files changed, 6 insertions(+), 4 deletions(-) Index: llvm/autoconf/configure.ac diff -u llvm/autoconf/configure.ac:1.184 llvm/autoconf/configure.ac:1.185 --- llvm/autoconf/configure.ac:1.184 Thu May 19 03:37:50 2005 +++ llvm/autoconf/configure.ac Thu Jun 2 17:34:49 2005 @@ -357,11 +357,13 @@ AC_SUBST(ETAGSFLAGS,$ETAGSFLAGS) if test "$WITH_LLVMGCCDIR" = "default" ; then - AC_PATH_PROG(LLVMGCC, [llvm-gcc], []) - AC_PATH_PROG(LLVMGXX, [llvm-g++], []) + LLVMGCC="llvm-gcc${EXEEXT}" + LLVMGXX="llvm-g++${EXEEXT}" + AC_PATH_PROG(LLVMGCC, $LLVMGCC, []) + AC_PATH_PROG(LLVMGXX, $LLVMGXX, []) else - LLVMGCC=$WITH_LLVMGCCDIR/bin/llvm-gcc - LLVMGXX=$WITH_LLVMGCCDIR/bin/llvm-g++ + LLVMGCC="$WITH_LLVMGCCDIR/bin/llvm-gcc${EXEEXT}" + LLVMGXX="$WITH_LLVMGCCDIR/bin/llvm-g++${EXEEXT}" AC_SUBST(LLVMGCC,$LLVMGCC) AC_SUBST(LLVMGXX,$LLVMGXX) fi From alenhar2 at cs.uiuc.edu Sat Jun 4 07:44:11 2005 From: alenhar2 at cs.uiuc.edu (Andrew Lenharth) Date: Sat, 4 Jun 2005 07:44:11 -0500 Subject: [llvm-commits] CVS: llvm/lib/Transforms/Scalar/InstructionCombining.cpp Message-ID: <200506041244.HAA12176@zion.cs.uiuc.edu> Changes in directory llvm/lib/Transforms/Scalar: InstructionCombining.cpp updated: 1.345 -> 1.346 --- Log message: hack to fix bzip2 (bug 571: http://llvm.cs.uiuc.edu/PR571 ) --- Diffs of the changes: (+2 -0) InstructionCombining.cpp | 2 ++ 1 files changed, 2 insertions(+) Index: llvm/lib/Transforms/Scalar/InstructionCombining.cpp diff -u llvm/lib/Transforms/Scalar/InstructionCombining.cpp:1.345 llvm/lib/Transforms/Scalar/InstructionCombining.cpp:1.346 --- llvm/lib/Transforms/Scalar/InstructionCombining.cpp:1.345 Sat May 14 07:25:32 2005 +++ llvm/lib/Transforms/Scalar/InstructionCombining.cpp Sat Jun 4 07:43:56 2005 @@ -3088,6 +3088,8 @@ return 0; } + return 0; //The rest of this function is broken. See bug 571 + // Okay, we have the two reduced sized operands. If we are doing a <,> // comparison, make sure we perform the compare with the same signedness as // the DestTy. We don't have to do this if the comparison is !=/== or if the