From brukman at cs.uiuc.edu  Mon Jun  6 12:39:57 2005
From: brukman at cs.uiuc.edu (Misha Brukman)
Date: Mon, 6 Jun 2005 12:39:57 -0500
Subject: [llvm-commits] CVS: llvm/lib/Target/Alpha/AlphaISelPattern.cpp 
Message-ID: <200506061739.MAA13580@zion.cs.uiuc.edu>



Changes in directory llvm/lib/Target/Alpha:

AlphaISelPattern.cpp updated: 1.118 -> 1.119
---
Log message:

* Replace block of commented-out lines with #if 0
* Remove warning "control reaches end of non-void function"


---
Diffs of the changes:  (+29 -26)

 AlphaISelPattern.cpp |   55 ++++++++++++++++++++++++++-------------------------
 1 files changed, 29 insertions(+), 26 deletions(-)


Index: llvm/lib/Target/Alpha/AlphaISelPattern.cpp
diff -u llvm/lib/Target/Alpha/AlphaISelPattern.cpp:1.118 llvm/lib/Target/Alpha/AlphaISelPattern.cpp:1.119
--- llvm/lib/Target/Alpha/AlphaISelPattern.cpp:1.118	Tue May 31 14:49:34 2005
+++ llvm/lib/Target/Alpha/AlphaISelPattern.cpp	Mon Jun  6 12:39:46 2005
@@ -171,33 +171,36 @@
     MachineFunction &MF = DAG.getMachineFunction();
     switch (Op.getOpcode()) {
     default: assert(0 && "Should not custom lower this!");
-//     case ISD::SINT_TO_FP:
-//       {
-//         assert (Op.getOperand(0).getValueType() == MVT::i64
-//                 && "only quads can be loaded from");
-//         SDOperand SRC;
-//         if (EnableAlphaFTOI)
-//         {
-//           std::vector<MVT::ValueType> RTs;
-//           RTs.push_back(Op.getValueType());
-//           std::vector<SDOperand> Ops;
-//           Ops.push_back(Op.getOperand(0));
-//           SRC = DAG.getNode(AlphaISD::ITOF, RTs, Ops);
-//         } else {
-//           int SSFI = MF.getFrameInfo()->CreateStackObject(8, 8);
-//           SDOperand StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
-//           SDOperand Store = DAG.getNode(ISD::STORE, MVT::Other, DAG.getEntryNode(),
-//                                         Op.getOperand(0), StackSlot, DAG.getSrcValue(NULL));
-//           SRC = DAG.getLoad(Op.getValueType(), Store.getValue(0), StackSlot,
-//                             DAG.getSrcValue(NULL));
-//         }
-//         std::vector<MVT::ValueType> RTs;
-//         RTs.push_back(Op.getValueType());
-//         std::vector<SDOperand> Ops;
-//         Ops.push_back(SRC);
-//         return DAG.getNode(AlphaISD::CVTQ, RTs, Ops);
-//       }
+#if 0
+    case ISD::SINT_TO_FP:
+      {
+        assert (Op.getOperand(0).getValueType() == MVT::i64
+                && "only quads can be loaded from");
+        SDOperand SRC;
+        if (EnableAlphaFTOI)
+        {
+          std::vector<MVT::ValueType> RTs;
+          RTs.push_back(Op.getValueType());
+          std::vector<SDOperand> Ops;
+          Ops.push_back(Op.getOperand(0));
+          SRC = DAG.getNode(AlphaISD::ITOF, RTs, Ops);
+        } else {
+          int SSFI = MF.getFrameInfo()->CreateStackObject(8, 8);
+          SDOperand StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
+          SDOperand Store = DAG.getNode(ISD::STORE, MVT::Other, DAG.getEntryNode(),
+                                        Op.getOperand(0), StackSlot, DAG.getSrcValue(NULL));
+          SRC = DAG.getLoad(Op.getValueType(), Store.getValue(0), StackSlot,
+                            DAG.getSrcValue(NULL));
+        }
+        std::vector<MVT::ValueType> RTs;
+        RTs.push_back(Op.getValueType());
+        std::vector<SDOperand> Ops;
+        Ops.push_back(SRC);
+        return DAG.getNode(AlphaISD::CVTQ, RTs, Ops);
+      }
+#endif
     }
+    return SDOperand();
 }
 
 





From alenhar2 at cs.uiuc.edu  Mon Jun  6 14:03:28 2005
From: alenhar2 at cs.uiuc.edu (Andrew Lenharth)
Date: Mon, 6 Jun 2005 14:03:28 -0500
Subject: [llvm-commits] CVS: llvm/lib/Target/Alpha/AlphaAsmPrinter.cpp 
Message-ID: <200506061903.OAA14876@cypher.cs.uiuc.edu>



Changes in directory llvm/lib/Target/Alpha:

AlphaAsmPrinter.cpp updated: 1.15 -> 1.16
---
Log message:

hide basic block labels.  The utility of these for debuging is long since passed

---
Diffs of the changes:  (+2 -2)

 AlphaAsmPrinter.cpp |    4 ++--
 1 files changed, 2 insertions(+), 2 deletions(-)


Index: llvm/lib/Target/Alpha/AlphaAsmPrinter.cpp
diff -u llvm/lib/Target/Alpha/AlphaAsmPrinter.cpp:1.15 llvm/lib/Target/Alpha/AlphaAsmPrinter.cpp:1.16
--- llvm/lib/Target/Alpha/AlphaAsmPrinter.cpp:1.15	Thu May 26 22:39:30 2005
+++ llvm/lib/Target/Alpha/AlphaAsmPrinter.cpp	Mon Jun  6 14:03:09 2005
@@ -128,7 +128,7 @@
 
   case MachineOperand::MO_MachineBasicBlock: {
     MachineBasicBlock *MBBOp = MO.getMachineBasicBlock();
-    O << "LBB" << Mang->getValueName(MBBOp->getParent()->getFunction())
+    O << "$LBB" << Mang->getValueName(MBBOp->getParent()->getFunction())
       << "_" << MBBOp->getNumber() << "\t" << CommentString << " "
       << MBBOp->getBasicBlock()->getName();
     return;
@@ -193,7 +193,7 @@
   for (MachineFunction::const_iterator I = MF.begin(), E = MF.end();
        I != E; ++I) {
     // Print a label for the basic block.
-    O << "LBB" << CurrentFnName << "_" << I->getNumber() << ":\t"
+    O << "$LBB" << CurrentFnName << "_" << I->getNumber() << ":\t"
       << CommentString << " " << I->getBasicBlock()->getName() << "\n";
     for (MachineBasicBlock::const_iterator II = I->begin(), E = I->end();
          II != E; ++II) {





From alenhar2 at cs.uiuc.edu  Mon Jun  6 14:04:14 2005
From: alenhar2 at cs.uiuc.edu (Andrew Lenharth)
Date: Mon, 6 Jun 2005 14:04:14 -0500
Subject: [llvm-commits] CVS: llvm/lib/Target/Alpha/AlphaISelPattern.cpp
	AlphaInstrInfo.td 
Message-ID: <200506061904.OAA14890@cypher.cs.uiuc.edu>



Changes in directory llvm/lib/Target/Alpha:

AlphaISelPattern.cpp updated: 1.119 -> 1.120
AlphaInstrInfo.td updated: 1.42 -> 1.43
---
Log message:

allow marking of loads and stores in the instruction stream with enough information to reconstruct the Value* if it existed

---
Diffs of the changes:  (+31 -0)

 AlphaISelPattern.cpp |   30 ++++++++++++++++++++++++++++++
 AlphaInstrInfo.td    |    1 +
 2 files changed, 31 insertions(+)


Index: llvm/lib/Target/Alpha/AlphaISelPattern.cpp
diff -u llvm/lib/Target/Alpha/AlphaISelPattern.cpp:1.119 llvm/lib/Target/Alpha/AlphaISelPattern.cpp:1.120
--- llvm/lib/Target/Alpha/AlphaISelPattern.cpp:1.119	Mon Jun  6 12:39:46 2005
+++ llvm/lib/Target/Alpha/AlphaISelPattern.cpp	Mon Jun  6 14:03:55 2005
@@ -45,6 +45,9 @@
   cl::opt<bool> EnableAlphaCount("enable-alpha-count",
                              cl::desc("Print estimates on live ins and outs"),
                              cl::Hidden);
+  cl::opt<bool> EnableAlphaLSMark("enable-alpha-lsmark",
+                             cl::desc("Emit symbols to corrolate Mem ops to LLVM Values"),
+                             cl::Hidden);
 }
 
 namespace {
@@ -514,6 +517,27 @@
   }
 }
 
+//Find the offset of the arg in it's parent's function
+static int getValueOffset(const Value* v)
+{
+  if (v == NULL)
+    return 0;
+
+  const Instruction* itarget = dyn_cast<Instruction>(v);
+  const BasicBlock* btarget = itarget->getParent();
+  const Function* ftarget = btarget->getParent();
+
+  //offset due to earlier BBs
+  int i = 0;
+  for(Function::const_iterator ii = ftarget->begin(); &*ii != btarget; ++ii)
+    i += ii->size();
+
+  for(BasicBlock::const_iterator ii = btarget->begin(); &*ii != itarget; ++ii)
+    ++i;
+
+  return i;
+}
+
 //Factorize a number using the list of constants
 static bool factorize(int v[], int res[], int size, uint64_t c)
 {
@@ -1119,6 +1143,12 @@
       Select(Chain);
       Opc = DestType == MVT::f64 ? Alpha::LDT : Alpha::LDS;
 
+      if (EnableAlphaLSMark)
+      {
+        int i = getValueOffset(dyn_cast<SrcValueSDNode>(N.getOperand(2))->getValue());
+        BuildMI(BB, Alpha::MEMLABEL, 2).addImm(i);
+      }
+      
       if (Address.getOpcode() == ISD::GlobalAddress) {
         AlphaLowering.restoreGP(BB);
         Opc = GetSymVersion(Opc);


Index: llvm/lib/Target/Alpha/AlphaInstrInfo.td
diff -u llvm/lib/Target/Alpha/AlphaInstrInfo.td:1.42 llvm/lib/Target/Alpha/AlphaInstrInfo.td:1.43
--- llvm/lib/Target/Alpha/AlphaInstrInfo.td:1.42	Tue May  3 12:19:29 2005
+++ llvm/lib/Target/Alpha/AlphaInstrInfo.td	Mon Jun  6 14:03:55 2005
@@ -31,6 +31,7 @@
 def ADJUSTSTACKDOWN : PseudoInstAlpha<(ops ), "ADJDOWN">;
 def ALTENT : PseudoInstAlpha<(ops s64imm:$TARGET), "$TARGET:\n">;
 def PCLABEL : PseudoInstAlpha<(ops s64imm:$num), "PCMARKER_$num:\n">;
+def MEMLABEL : PseudoInstAlpha<(ops s64imm:$i), "LSMARKER_$i:\n">;
 
 //*****************
 //These are shortcuts, the assembler expands them





From brukman at cs.uiuc.edu  Mon Jun  6 14:08:15 2005
From: brukman at cs.uiuc.edu (Misha Brukman)
Date: Mon, 6 Jun 2005 14:08:15 -0500
Subject: [llvm-commits] CVS: llvm/lib/Target/Alpha/AlphaISelPattern.cpp 
Message-ID: <200506061908.OAA28191@zion.cs.uiuc.edu>



Changes in directory llvm/lib/Target/Alpha:

AlphaISelPattern.cpp updated: 1.120 -> 1.121
---
Log message:

Fix spelling of `correlate'


---
Diffs of the changes:  (+1 -1)

 AlphaISelPattern.cpp |    2 +-
 1 files changed, 1 insertion(+), 1 deletion(-)


Index: llvm/lib/Target/Alpha/AlphaISelPattern.cpp
diff -u llvm/lib/Target/Alpha/AlphaISelPattern.cpp:1.120 llvm/lib/Target/Alpha/AlphaISelPattern.cpp:1.121
--- llvm/lib/Target/Alpha/AlphaISelPattern.cpp:1.120	Mon Jun  6 14:03:55 2005
+++ llvm/lib/Target/Alpha/AlphaISelPattern.cpp	Mon Jun  6 14:08:04 2005
@@ -46,7 +46,7 @@
                              cl::desc("Print estimates on live ins and outs"),
                              cl::Hidden);
   cl::opt<bool> EnableAlphaLSMark("enable-alpha-lsmark",
-                             cl::desc("Emit symbols to corrolate Mem ops to LLVM Values"),
+                             cl::desc("Emit symbols to correlate Mem ops to LLVM Values"),
                              cl::Hidden);
 }
 





From brukman at cs.uiuc.edu  Mon Jun  6 14:17:16 2005
From: brukman at cs.uiuc.edu (Misha Brukman)
Date: Mon, 6 Jun 2005 14:17:16 -0500
Subject: [llvm-commits] CVS: llvm/utils/NightlyTest.pl 
Message-ID: <200506061917.OAA28257@zion.cs.uiuc.edu>



Changes in directory llvm/utils:

NightlyTest.pl updated: 1.96 -> 1.97
---
Log message:

* Add ability to specify the target LLVM will compile for via configure
* Minor whitespace cleanups


---
Diffs of the changes:  (+6 -2)

 NightlyTest.pl |    8 ++++++--
 1 files changed, 6 insertions(+), 2 deletions(-)


Index: llvm/utils/NightlyTest.pl
diff -u llvm/utils/NightlyTest.pl:1.96 llvm/utils/NightlyTest.pl:1.97
--- llvm/utils/NightlyTest.pl:1.96	Thu May 26 11:28:55 2005
+++ llvm/utils/NightlyTest.pl	Mon Jun  6 14:17:05 2005
@@ -36,6 +36,7 @@
 #  -gccpath         Path to gcc/g++ used to build LLVM
 #  -cvstag          Check out a specific CVS tag to build LLVM (useful for
 #                   testing release branches)
+#  -target          Specify the target triplet
 #
 # CVSROOT is the CVS repository from which the tree will be checked out,
 #  specified either in the full :method:user at host:/dir syntax, or
@@ -272,7 +273,7 @@
   if (/^-parallel$/)       { $MAKEOPTS = "$MAKEOPTS -j2 -l3.0"; next; }
   if (/^-release$/)        { $MAKEOPTS = "$MAKEOPTS ENABLE_OPTIMIZED=1"; next; }
   if (/^-pedantic$/)       { 
-      $MAKEOPTS   = "$MAKEOPTS CompileOptimizeOpts='-O3 -DNDEBUG -finline-functions -Wpointer-arith -Wcast-align -Wno-deprecated -Wold-style-cast -Wabi -Woverloaded-virtual -ffor-scope'"; 
+      $MAKEOPTS = "$MAKEOPTS CompileOptimizeOpts='-O3 -DNDEBUG -finline-functions -Wpointer-arith -Wcast-align -Wno-deprecated -Wold-style-cast -Wabi -Woverloaded-virtual -ffor-scope'"; 
       next; 
   }
   if (/^-enable-llcbeta$/) { $PROGTESTOPTS .= " ENABLE_LLCBETA=1"; next; }
@@ -292,8 +293,11 @@
     $CONFIGUREARGS .= " CC=$ARGV[0]/gcc CXX=$ARGV[0]/g++"; shift; next; 
   }
   if (/^-cvstag/)          { $CVSCOOPT .= " -r $ARGV[0]"; shift; next; }
+  if (/^-target/)          {
+    $CONFIGUREARGS .= " --target=$ARGV[0]"; shift; next;
+  }
   if (/^-noexternals$/)    { $NOEXTERNALS = 1; next; }
-  if(/^-nodejagnu$/) { $NODEJAGNU = 1; next; }
+  if (/^-nodejagnu$/)      { $NODEJAGNU = 1; next; }
 
   print "Unknown option: $_ : ignoring!\n";
 }





From brukman at cs.uiuc.edu  Mon Jun  6 14:29:47 2005
From: brukman at cs.uiuc.edu (Misha Brukman)
Date: Mon, 6 Jun 2005 14:29:47 -0500
Subject: [llvm-commits] CVS: llvm/autoconf/configure.ac 
Message-ID: <200506061929.OAA28541@zion.cs.uiuc.edu>



Changes in directory llvm/autoconf:

configure.ac updated: 1.185 -> 1.186
---
Log message:

We also have V8, so do not force every Sparc to be treated like a V9.  It is
still possible to force V9 (even if configure doesn't think it's one) via
``./configure --target=sparcv9-sun-solaris2.8'' so nothing is lost.


---
Diffs of the changes:  (+0 -8)

 configure.ac |    8 --------
 1 files changed, 8 deletions(-)


Index: llvm/autoconf/configure.ac
diff -u llvm/autoconf/configure.ac:1.185 llvm/autoconf/configure.ac:1.186
--- llvm/autoconf/configure.ac:1.185	Thu Jun  2 17:34:49 2005
+++ llvm/autoconf/configure.ac	Mon Jun  6 14:29:36 2005
@@ -159,14 +159,6 @@
     ;;
 esac
 
-dnl If we are targetting a Sparc machine running Solaris, pretend that it is
-dnl V9, since that is all that we support at the moment, and autoconf will only
-dnl tell us we're a sparc.
-case $target in
-  sparc*-*-solaris*)  AC_SUBST(target,[[sparcv9-sun-solaris2.8]])
-  ;;
-esac
-
 dnl Determine what our target architecture is and configure accordingly.
 dnl This will allow Makefiles to make a distinction between the hardware and
 dnl the OS.





From alenhar2 at cs.uiuc.edu  Tue Jun  7 19:49:20 2005
From: alenhar2 at cs.uiuc.edu (Andrew Lenharth)
Date: Tue, 7 Jun 2005 19:49:20 -0500
Subject: [llvm-commits] CVS: llvm/lib/Bytecode/Reader/ReaderWrappers.cpp 
Message-ID: <200506080049.TAA00446@zion.cs.uiuc.edu>



Changes in directory llvm/lib/Bytecode/Reader:

ReaderWrappers.cpp updated: 1.46 -> 1.47
---
Log message:

Remove code for conversion from old style va_args.  Preparing the way for
returning to the old style :)



---
Diffs of the changes:  (+3 -76)

 ReaderWrappers.cpp |   79 ++---------------------------------------------------
 1 files changed, 3 insertions(+), 76 deletions(-)


Index: llvm/lib/Bytecode/Reader/ReaderWrappers.cpp
diff -u llvm/lib/Bytecode/Reader/ReaderWrappers.cpp:1.46 llvm/lib/Bytecode/Reader/ReaderWrappers.cpp:1.47
--- llvm/lib/Bytecode/Reader/ReaderWrappers.cpp:1.46	Thu May  5 17:32:13 2005
+++ llvm/lib/Bytecode/Reader/ReaderWrappers.cpp	Tue Jun  7 19:49:08 2005
@@ -149,78 +149,6 @@
 }
 
 //===----------------------------------------------------------------------===//
-//  Varargs transmogrification code...
-//
-
-// CheckVarargs - This is used to automatically translate old-style varargs to
-// new style varargs for backwards compatibility.
-static ModuleProvider *CheckVarargs(ModuleProvider *MP) {
-  Module *M = MP->getModule();
-
-  // Check to see if va_start takes arguments...
-  Function *F = M->getNamedFunction("llvm.va_start");
-  if (F == 0) return MP;  // No varargs use, just return.
-
-  if (F->getFunctionType()->getNumParams() == 0)
-    return MP;  // Modern varargs processing, just return.
-
-  // If we get to this point, we know that we have an old-style module.
-  // Materialize the whole thing to perform the rewriting.
-  MP->materializeModule();
-
-  // If the user is making use of obsolete varargs intrinsics, adjust them for
-  // the user.
-  if (Function *F = M->getNamedFunction("llvm.va_start")) {
-    assert(F->arg_size() == 1 && "Obsolete va_start takes 1 argument!");
-
-    const Type *RetTy = F->getFunctionType()->getParamType(0);
-    RetTy = cast<PointerType>(RetTy)->getElementType();
-    Function *NF = M->getOrInsertFunction("llvm.va_start", RetTy, 0);
-
-    for (Value::use_iterator I = F->use_begin(), E = F->use_end(); I != E; )
-      if (CallInst *CI = dyn_cast<CallInst>(*I++)) {
-        Value *V = new CallInst(NF, "", CI);
-        new StoreInst(V, CI->getOperand(1), CI);
-        CI->getParent()->getInstList().erase(CI);
-      }
-    F->setName("");
-  }
-
-  if (Function *F = M->getNamedFunction("llvm.va_end")) {
-    assert(F->arg_size() == 1 && "Obsolete va_end takes 1 argument!");
-    const Type *ArgTy = F->getFunctionType()->getParamType(0);
-    ArgTy = cast<PointerType>(ArgTy)->getElementType();
-    Function *NF = M->getOrInsertFunction("llvm.va_end", Type::VoidTy,
-                                                  ArgTy, 0);
-
-    for (Value::use_iterator I = F->use_begin(), E = F->use_end(); I != E; )
-      if (CallInst *CI = dyn_cast<CallInst>(*I++)) {
-        Value *V = new LoadInst(CI->getOperand(1), "", CI);
-        new CallInst(NF, V, "", CI);
-        CI->getParent()->getInstList().erase(CI);
-      }
-    F->setName("");
-  }
-
-  if (Function *F = M->getNamedFunction("llvm.va_copy")) {
-    assert(F->arg_size() == 2 && "Obsolete va_copy takes 2 argument!");
-    const Type *ArgTy = F->getFunctionType()->getParamType(0);
-    ArgTy = cast<PointerType>(ArgTy)->getElementType();
-    Function *NF = M->getOrInsertFunction("llvm.va_copy", ArgTy,
-                                                  ArgTy, 0);
-
-    for (Value::use_iterator I = F->use_begin(), E = F->use_end(); I != E; )
-      if (CallInst *CI = dyn_cast<CallInst>(*I++)) {
-        Value *V = new CallInst(NF, CI->getOperand(2), "", CI);
-        new StoreInst(V, CI->getOperand(1), CI);
-        CI->getParent()->getInstList().erase(CI);
-      }
-    F->setName("");
-  }
-  return MP;
-}
-
-//===----------------------------------------------------------------------===//
 // Wrapper functions
 //===----------------------------------------------------------------------===//
 
@@ -231,8 +159,7 @@
                                       unsigned Length,
                                       const std::string &ModuleID,
                                       BytecodeHandler* H ) {
-  return CheckVarargs(
-      new BytecodeBufferReader(Buffer, Length, ModuleID, H));
+  return new BytecodeBufferReader(Buffer, Length, ModuleID, H);
 }
 
 /// ParseBytecodeBuffer - Parse a given bytecode buffer
@@ -255,9 +182,9 @@
 ModuleProvider *llvm::getBytecodeModuleProvider(const std::string &Filename,
                                                 BytecodeHandler* H) {
   if (Filename != std::string("-"))        // Read from a file...
-    return CheckVarargs(new BytecodeFileReader(Filename,H));
+    return new BytecodeFileReader(Filename,H);
   else                                     // Read from stdin
-    return CheckVarargs(new BytecodeStdinReader(H));
+    return new BytecodeStdinReader(H);
 }
 
 /// ParseBytecodeFile - Parse the given bytecode file





From natebegeman at mac.com  Tue Jun  7 20:02:49 2005
From: natebegeman at mac.com (Nate Begeman)
Date: Tue, 7 Jun 2005 20:02:49 -0500
Subject: [llvm-commits] CVS: llvm/lib/Target/X86/X86JITInfo.cpp 
Message-ID: <200506080102.UAA00543@zion.cs.uiuc.edu>



Changes in directory llvm/lib/Target/X86:

X86JITInfo.cpp updated: 1.12 -> 1.13
---
Log message:

Fix lli linking on Mac OS X 10.4.1 for Intel.


---
Diffs of the changes:  (+2 -2)

 X86JITInfo.cpp |    4 ++--
 1 files changed, 2 insertions(+), 2 deletions(-)


Index: llvm/lib/Target/X86/X86JITInfo.cpp
diff -u llvm/lib/Target/X86/X86JITInfo.cpp:1.12 llvm/lib/Target/X86/X86JITInfo.cpp:1.13
--- llvm/lib/Target/X86/X86JITInfo.cpp:1.12	Thu Jun  2 16:33:19 2005
+++ llvm/lib/Target/X86/X86JITInfo.cpp	Tue Jun  7 20:02:38 2005
@@ -43,7 +43,7 @@
   asm(
     ".text\n"
     ".align 8\n"
-#ifdef __CYGWIN__
+#if defined(__CYGWIN__) || defined(__APPLE__)
     ".globl _X86CompilationCallback\n"
   "_X86CompilationCallback:\n"
 #else
@@ -54,7 +54,7 @@
     "movl    %esp, %ebp\n"    // Standard prologue
     "pushl   %eax\n"
     "pushl   %edx\n"          // save EAX/EDX
-#ifdef __CYGWIN__
+#if defined(__CYGWIN__) || defined(__APPLE__)
     "call _X86CompilationCallback2\n"
 #else
     "call X86CompilationCallback2\n"





From natebegeman at mac.com  Tue Jun  7 23:14:55 2005
From: natebegeman at mac.com (Nate Begeman)
Date: Tue, 7 Jun 2005 23:14:55 -0500
Subject: [llvm-commits] CVS: llvm/lib/Target/PowerPC/PPC32ISelPattern.cpp 
Message-ID: <200506080414.XAA01273@zion.cs.uiuc.edu>



Changes in directory llvm/lib/Target/PowerPC:

PPC32ISelPattern.cpp updated: 1.91 -> 1.92
---
Log message:

Handle some more real world cases of rlwimi.  These don't come up that
regularly in "normal" code, but for things like software graphics, they
make a big difference.

For the following code:
unsigned short Trans16Bit(unsigned srcA,unsigned srcB,unsigned alpha)
{
	unsigned tmpA,tmpB,mixed;
	tmpA = ((srcA & 0x03E0) << 15) | (srcA & 0x7C1F);
	tmpB = ((srcB & 0x03E0) << 15) | (srcB & 0x7C1F);
	mixed = (tmpA * alpha) + (tmpB * (32 - alpha));
	return ((mixed >> 5) & 0x7C1F) | ((mixed >> 20) & 0x03E0);
}

We now generate:
_Trans16Bit:
.LBB_Trans16Bit_0:      ; entry
        andi. r2, r4, 31775
        rlwimi r2, r4, 15, 7, 11
        subfic r4, r5, 32
        mullw r2, r2, r4
        andi. r4, r3, 31775
        rlwimi r4, r3, 15, 7, 11
        mullw r3, r4, r5
        add r2, r2, r3
        srwi r3, r2, 5
        andi. r3, r3, 31775
        rlwimi r3, r2, 12, 22, 26
        blr

Instead of:
_Trans16Bit:
.LBB_Trans16Bit_0:      ; entry
        slwi r2, r4, 15
        rlwinm r2, r2, 0, 7, 11
        andi. r4, r4, 31775
        or r2, r2, r4
        subfic r4, r5, 32
        mullw r2, r2, r4
        slwi r4, r3, 15
        rlwinm r4, r4, 0, 7, 11
        andi. r3, r3, 31775
        or r3, r4, r3
        mullw r3, r3, r5
        add r2, r2, r3
        srwi r3, r2, 5
        andi. r3, r3, 31775
        srwi r2, r2, 20
        rlwimi r3, r2, 0, 22, 26
        blr



---
Diffs of the changes:  (+42 -10)

 PPC32ISelPattern.cpp |   52 +++++++++++++++++++++++++++++++++++++++++----------
 1 files changed, 42 insertions(+), 10 deletions(-)


Index: llvm/lib/Target/PowerPC/PPC32ISelPattern.cpp
diff -u llvm/lib/Target/PowerPC/PPC32ISelPattern.cpp:1.91 llvm/lib/Target/PowerPC/PPC32ISelPattern.cpp:1.92
--- llvm/lib/Target/PowerPC/PPC32ISelPattern.cpp:1.91	Sun May 15 14:54:37 2005
+++ llvm/lib/Target/PowerPC/PPC32ISelPattern.cpp	Tue Jun  7 23:14:27 2005
@@ -982,8 +982,12 @@
 bool ISel::SelectBitfieldInsert(SDOperand OR, unsigned Result) {
   bool IsRotate = false;
   unsigned TgtMask = 0xFFFFFFFF, InsMask = 0xFFFFFFFF, Amount = 0;
-  unsigned Op0Opc = OR.getOperand(0).getOpcode();
-  unsigned Op1Opc = OR.getOperand(1).getOpcode();
+  
+  SDOperand Op0 = OR.getOperand(0);
+  SDOperand Op1 = OR.getOperand(1);
+
+  unsigned Op0Opc = Op0.getOpcode();
+  unsigned Op1Opc = Op1.getOpcode();
 
   // Verify that we have the correct opcodes
   if (ISD::SHL != Op0Opc && ISD::SRL != Op0Opc && ISD::AND != Op0Opc)
@@ -993,7 +997,7 @@
 
   // Generate Mask value for Target
   if (ConstantSDNode *CN =
-      dyn_cast<ConstantSDNode>(OR.getOperand(0).getOperand(1).Val)) {
+      dyn_cast<ConstantSDNode>(Op0.getOperand(1).Val)) {
     switch(Op0Opc) {
     case ISD::SHL: TgtMask <<= (unsigned)CN->getValue(); break;
     case ISD::SRL: TgtMask >>= (unsigned)CN->getValue(); break;
@@ -1005,7 +1009,7 @@
 
   // Generate Mask value for Insert
   if (ConstantSDNode *CN =
-      dyn_cast<ConstantSDNode>(OR.getOperand(1).getOperand(1).Val)) {
+      dyn_cast<ConstantSDNode>(Op1.getOperand(1).Val)) {
     switch(Op1Opc) {
     case ISD::SHL:
       Amount = CN->getValue();
@@ -1026,27 +1030,55 @@
     return false;
   }
 
+  unsigned Tmp3 = 0;
+
+  // If both of the inputs are ANDs and one of them has a logical shift by
+  // constant as its input, make that the inserted value so that we can combine
+  // the shift into the rotate part of the rlwimi instruction
+  if (Op0Opc == ISD::AND && Op1Opc == ISD::AND) {
+    if (Op1.getOperand(0).getOpcode() == ISD::SHL || 
+        Op1.getOperand(0).getOpcode() == ISD::SRL) {
+      if (ConstantSDNode *CN = 
+          dyn_cast<ConstantSDNode>(Op1.getOperand(0).getOperand(1).Val)) {
+        Amount = Op1.getOperand(0).getOpcode() == ISD::SHL ? 
+          CN->getValue() : 32 - CN->getValue();
+        Tmp3 = SelectExpr(Op1.getOperand(0).getOperand(0));
+      }
+    } else if (Op0.getOperand(0).getOpcode() == ISD::SHL ||
+               Op0.getOperand(0).getOpcode() == ISD::SRL) {
+      if (ConstantSDNode *CN = 
+          dyn_cast<ConstantSDNode>(Op0.getOperand(0).getOperand(1).Val)) {
+        std::swap(Op0, Op1);
+        std::swap(TgtMask, InsMask);
+        Amount = Op1.getOperand(0).getOpcode() == ISD::SHL ? 
+          CN->getValue() : 32 - CN->getValue();
+        Tmp3 = SelectExpr(Op1.getOperand(0).getOperand(0));
+      }
+    }
+  }
+
   // Verify that the Target mask and Insert mask together form a full word mask
   // and that the Insert mask is a run of set bits (which implies both are runs
   // of set bits).  Given that, Select the arguments and generate the rlwimi
   // instruction.
   unsigned MB, ME;
-  if (((TgtMask ^ InsMask) == 0xFFFFFFFF) && IsRunOfOnes(InsMask, MB, ME)) {
+  if (((TgtMask & InsMask) == 0) && IsRunOfOnes(InsMask, MB, ME)) {
     unsigned Tmp1, Tmp2;
+    bool fullMask = (TgtMask ^ InsMask) == 0xFFFFFFFF;
     // Check for rotlwi / rotrwi here, a special case of bitfield insert
     // where both bitfield halves are sourced from the same value.
-    if (IsRotate &&
+    if (IsRotate && fullMask &&
         OR.getOperand(0).getOperand(0) == OR.getOperand(1).getOperand(0)) {
       Tmp1 = SelectExpr(OR.getOperand(0).getOperand(0));
       BuildMI(BB, PPC::RLWINM, 4, Result).addReg(Tmp1).addImm(Amount)
         .addImm(0).addImm(31);
       return true;
     }
-    if (Op0Opc == ISD::AND)
-      Tmp1 = SelectExpr(OR.getOperand(0).getOperand(0));
+    if (Op0Opc == ISD::AND && fullMask)
+      Tmp1 = SelectExpr(Op0.getOperand(0));
     else
-      Tmp1 = SelectExpr(OR.getOperand(0));
-    Tmp2 = SelectExpr(OR.getOperand(1).getOperand(0));
+      Tmp1 = SelectExpr(Op0);
+    Tmp2 = Tmp3 ? Tmp3 : SelectExpr(Op1.getOperand(0));
     BuildMI(BB, PPC::RLWIMI, 5, Result).addReg(Tmp1).addReg(Tmp2)
       .addImm(Amount).addImm(MB).addImm(ME);
     return true;





From reid at x10sys.com  Wed Jun  8 12:44:59 2005
From: reid at x10sys.com (Reid Spencer)
Date: Wed, 8 Jun 2005 12:44:59 -0500
Subject: [llvm-commits] CVS: llvm/lib/Target/PowerPC/PPC32Relocations.h 
Message-ID: <200506081744.MAA00400@zion.cs.uiuc.edu>



Changes in directory llvm/lib/Target/PowerPC:

PPC32Relocations.h updated: 1.3 -> 1.4
---
Log message:

For PR572: http://llvm.cs.uiuc.edu/PR572 :
Undefine the PPC symbol which is defined by Linux/PPC (erroneously) so it
doesn't pollute the user namespace and clash with our namespace declarations.


---
Diffs of the changes:  (+6 -0)

 PPC32Relocations.h |    6 ++++++
 1 files changed, 6 insertions(+)


Index: llvm/lib/Target/PowerPC/PPC32Relocations.h
diff -u llvm/lib/Target/PowerPC/PPC32Relocations.h:1.3 llvm/lib/Target/PowerPC/PPC32Relocations.h:1.4
--- llvm/lib/Target/PowerPC/PPC32Relocations.h:1.3	Thu Apr 21 18:20:02 2005
+++ llvm/lib/Target/PowerPC/PPC32Relocations.h	Wed Jun  8 12:44:48 2005
@@ -16,6 +16,12 @@
 
 #include "llvm/CodeGen/MachineRelocation.h"
 
+// Hack to rid us of a PPC pre-processor symbol which is erroneously 
+// defined in a PowerPC header file (bug in Linux/PPC)
+#ifdef PPC
+#undef PPC
+#endif
+
 namespace llvm {
   namespace PPC {
     enum RelocationType {





From alenhar2 at cs.uiuc.edu  Wed Jun  8 13:02:40 2005
From: alenhar2 at cs.uiuc.edu (Andrew Lenharth)
Date: Wed, 8 Jun 2005 13:02:40 -0500
Subject: [llvm-commits] CVS: llvm/lib/Target/Alpha/AlphaISelPattern.cpp 
Message-ID: <200506081802.NAA16470@cypher.cs.uiuc.edu>



Changes in directory llvm/lib/Target/Alpha:

AlphaISelPattern.cpp updated: 1.121 -> 1.122
---
Log message:

fix BranchCC with a setCC with an arg of 0

---
Diffs of the changes:  (+3 -3)

 AlphaISelPattern.cpp |    6 +++---
 1 files changed, 3 insertions(+), 3 deletions(-)


Index: llvm/lib/Target/Alpha/AlphaISelPattern.cpp
diff -u llvm/lib/Target/Alpha/AlphaISelPattern.cpp:1.121 llvm/lib/Target/Alpha/AlphaISelPattern.cpp:1.122
--- llvm/lib/Target/Alpha/AlphaISelPattern.cpp:1.121	Mon Jun  6 14:08:04 2005
+++ llvm/lib/Target/Alpha/AlphaISelPattern.cpp	Wed Jun  8 13:02:21 2005
@@ -899,8 +899,8 @@
       //Dropping the CC is only useful if we are comparing to 0
       bool LeftZero = SetCC->getOperand(0).getOpcode() == ISD::Constant &&
         cast<ConstantSDNode>(SetCC->getOperand(0))->getValue() == 0;
-      bool RightZero = SetCC->getOperand(0).getOpcode() == ISD::Constant &&
-        cast<ConstantSDNode>(SetCC->getOperand(0))->getValue() == 0;
+      bool RightZero = SetCC->getOperand(1).getOpcode() == ISD::Constant &&
+        cast<ConstantSDNode>(SetCC->getOperand(1))->getValue() == 0;
       bool isNE = false;
 
       //Fix up CC
@@ -912,7 +912,7 @@
         isNE = true;
 
       if (LeftZero || RightZero) {
-        switch (SetCC->getCondition()) {
+        switch (cCode) {
         default: CC.Val->dump(); assert(0 && "Unknown integer comparison!");
         case ISD::SETEQ:  Opc = Alpha::BEQ; break;
         case ISD::SETLT:  Opc = Alpha::BLT; break;





From alenhar2 at cs.uiuc.edu  Wed Jun  8 17:33:02 2005
From: alenhar2 at cs.uiuc.edu (Andrew Lenharth)
Date: Wed, 8 Jun 2005 17:33:02 -0500
Subject: [llvm-commits] CVS: llvm/tools/llc/Makefile 
Message-ID: <200506082233.RAA03546@zion.cs.uiuc.edu>



Changes in directory llvm/tools/llc:

Makefile updated: 1.72 -> 1.73
---
Log message:

make SparcV8 and V9 seperately configurable

---
Diffs of the changes:  (+6 -2)

 Makefile |    8 ++++++--
 1 files changed, 6 insertions(+), 2 deletions(-)


Index: llvm/tools/llc/Makefile
diff -u llvm/tools/llc/Makefile:1.72 llvm/tools/llc/Makefile:1.73
--- llvm/tools/llc/Makefile:1.72	Sat Apr 23 12:24:33 2005
+++ llvm/tools/llc/Makefile	Wed Jun  8 17:32:51 2005
@@ -29,16 +29,20 @@
 endif
 
 # Check for Sparc target
-ifneq ($(strip $(filter SparcV8,$(TARGETS_TO_BUILD))),)
+ifneq ($(strip $(filter SparcV9,$(TARGETS_TO_BUILD))),)
 USEDLIBS += \
 	LLVMSparcV9ModuloSched \
-	LLVMSparcV8 \
 	LLVMSparcV9 \
 	LLVMSparcV9RegAlloc \
 	LLVMSparcV9InstrSched \
 	LLVMSparcV9LiveVar
 endif
 
+ifneq ($(strip $(filter SparcV8,$(TARGETS_TO_BUILD))),)
+USEDLIBS += LLVMSparcV8
+endif
+
+
 #Check for X86 Target
 ifneq ($(strip $(filter X86,$(TARGETS_TO_BUILD))),)
 USEDLIBS += LLVMX86





From lattner at cs.uiuc.edu  Wed Jun  8 21:59:11 2005
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Wed, 8 Jun 2005 21:59:11 -0500
Subject: [llvm-commits] CVS: llvm/lib/Transforms/IPO/LowerSetJmp.cpp 
Message-ID: <200506090259.VAA26412@zion.cs.uiuc.edu>



Changes in directory llvm/lib/Transforms/IPO:

LowerSetJmp.cpp updated: 1.25 -> 1.26
---
Log message:

Fix a problem on 64-bit targets where we passed (int)0 through ... instead of
(void*)0.


---
Diffs of the changes:  (+7 -7)

 LowerSetJmp.cpp |   14 +++++++-------
 1 files changed, 7 insertions(+), 7 deletions(-)


Index: llvm/lib/Transforms/IPO/LowerSetJmp.cpp
diff -u llvm/lib/Transforms/IPO/LowerSetJmp.cpp:1.25 llvm/lib/Transforms/IPO/LowerSetJmp.cpp:1.26
--- llvm/lib/Transforms/IPO/LowerSetJmp.cpp:1.25	Thu May  5 10:47:43 2005
+++ llvm/lib/Transforms/IPO/LowerSetJmp.cpp	Wed Jun  8 21:59:00 2005
@@ -204,32 +204,32 @@
 
   // void __llvm_sjljeh_init_setjmpmap(void**)
   InitSJMap = M.getOrInsertFunction("__llvm_sjljeh_init_setjmpmap",
-                                    Type::VoidTy, SBPPTy, 0);
+                                    Type::VoidTy, SBPPTy, NULL);
   // void __llvm_sjljeh_destroy_setjmpmap(void**)
   DestroySJMap = M.getOrInsertFunction("__llvm_sjljeh_destroy_setjmpmap",
-                                       Type::VoidTy, SBPPTy, 0);
+                                       Type::VoidTy, SBPPTy, NULL);
 
   // void __llvm_sjljeh_add_setjmp_to_map(void**, void*, unsigned)
   AddSJToMap = M.getOrInsertFunction("__llvm_sjljeh_add_setjmp_to_map",
                                      Type::VoidTy, SBPPTy, SBPTy,
-                                     Type::UIntTy, 0);
+                                     Type::UIntTy, NULL);
 
   // void __llvm_sjljeh_throw_longjmp(int*, int)
   ThrowLongJmp = M.getOrInsertFunction("__llvm_sjljeh_throw_longjmp",
-                                       Type::VoidTy, SBPTy, Type::IntTy, 0);
+                                       Type::VoidTy, SBPTy, Type::IntTy, NULL);
 
   // unsigned __llvm_sjljeh_try_catching_longjmp_exception(void **)
   TryCatchLJ =
     M.getOrInsertFunction("__llvm_sjljeh_try_catching_longjmp_exception",
-                          Type::UIntTy, SBPPTy, 0);
+                          Type::UIntTy, SBPPTy, NULL);
 
   // bool __llvm_sjljeh_is_longjmp_exception()
   IsLJException = M.getOrInsertFunction("__llvm_sjljeh_is_longjmp_exception",
-                                        Type::BoolTy, 0);
+                                        Type::BoolTy, NULL);
 
   // int __llvm_sjljeh_get_longjmp_value()
   GetLJValue = M.getOrInsertFunction("__llvm_sjljeh_get_longjmp_value",
-                                     Type::IntTy, 0);
+                                     Type::IntTy, NULL);
   return true;
 }
 





From lattner at cs.uiuc.edu  Wed Jun  8 22:33:05 2005
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Wed, 8 Jun 2005 22:33:05 -0500
Subject: [llvm-commits] CVS: llvm/lib/Transforms/Scalar/LowerInvoke.cpp 
Message-ID: <200506090333.WAA01733@zion.cs.uiuc.edu>



Changes in directory llvm/lib/Transforms/Scalar:

LowerInvoke.cpp updated: 1.25 -> 1.26
---
Log message:

Fix a 64-bit problem, passing (int)0 through ... instead of (void*)0


---
Diffs of the changes:  (+4 -4)

 LowerInvoke.cpp |    8 ++++----
 1 files changed, 4 insertions(+), 4 deletions(-)


Index: llvm/lib/Transforms/Scalar/LowerInvoke.cpp
diff -u llvm/lib/Transforms/Scalar/LowerInvoke.cpp:1.25 llvm/lib/Transforms/Scalar/LowerInvoke.cpp:1.26
--- llvm/lib/Transforms/Scalar/LowerInvoke.cpp:1.25	Fri May 13 01:27:02 2005
+++ llvm/lib/Transforms/Scalar/LowerInvoke.cpp	Wed Jun  8 22:32:54 2005
@@ -116,14 +116,14 @@
                                       Constant::getNullValue(PtrJBList),
                                       "llvm.sjljeh.jblist", &M);
     SetJmpFn = M.getOrInsertFunction("llvm.setjmp", Type::IntTy,
-                                     PointerType::get(JmpBufTy), 0);
+                                     PointerType::get(JmpBufTy), NULL);
     LongJmpFn = M.getOrInsertFunction("llvm.longjmp", Type::VoidTy,
                                       PointerType::get(JmpBufTy),
-                                      Type::IntTy, 0);
+                                      Type::IntTy, NULL);
   }
 
   // We need the 'write' and 'abort' functions for both models.
-  AbortFn = M.getOrInsertFunction("abort", Type::VoidTy, 0);
+  AbortFn = M.getOrInsertFunction("abort", Type::VoidTy, NULL);
 
   // Unfortunately, 'write' can end up being prototyped in several different
   // ways.  If the user defines a three (or more) operand function named 'write'
@@ -140,7 +140,7 @@
       WriteFn = 0;
   } else {
     WriteFn = M.getOrInsertFunction("write", Type::VoidTy, Type::IntTy,
-                                    VoidPtrTy, Type::IntTy, 0);
+                                    VoidPtrTy, Type::IntTy, NULL);
   }
   return true;
 }





From natebegeman at mac.com  Sun Jun 12 18:50:44 2005
From: natebegeman at mac.com (Nate Begeman)
Date: Sun, 12 Jun 2005 18:50:44 -0500
Subject: [llvm-commits] 
	CVS: llvm/lib/Target/PowerPC/PowerPCBranchSelector.cpp
Message-ID: <200506122350.SAA03512@zion.cs.uiuc.edu>



Changes in directory llvm/lib/Target/PowerPC:

PowerPCBranchSelector.cpp updated: 1.8 -> 1.9
---
Log message:

Fix a memory smasher caught by Mac OS X's debug malloc library.  We were
incorrectly using an iterator after it was invalid.


---
Diffs of the changes:  (+19 -8)

 PowerPCBranchSelector.cpp |   27 +++++++++++++++++++--------
 1 files changed, 19 insertions(+), 8 deletions(-)


Index: llvm/lib/Target/PowerPC/PowerPCBranchSelector.cpp
diff -u llvm/lib/Target/PowerPC/PowerPCBranchSelector.cpp:1.8 llvm/lib/Target/PowerPC/PowerPCBranchSelector.cpp:1.9
--- llvm/lib/Target/PowerPC/PowerPCBranchSelector.cpp:1.8	Thu Apr 21 18:20:02 2005
+++ llvm/lib/Target/PowerPC/PowerPCBranchSelector.cpp	Sun Jun 12 18:50:33 2005
@@ -86,7 +86,14 @@
 
         for (MachineBasicBlock::iterator MBBI = MBB->begin(), EE = MBB->end();
              MBBI != EE; ++MBBI) {
-          if (MBBI->getOpcode() == PPC::COND_BRANCH) {
+          // We may end up deleting the MachineInstr that MBBI points to, so
+          // remember its opcode now so we can refer to it after calling erase()
+          unsigned OpcodeToReplace = MBBI->getOpcode();
+
+          if (OpcodeToReplace == PPC::COND_BRANCH) {
+            MachineBasicBlock::iterator MBBJ = MBBI;
+            ++MBBJ;
+            
             // condbranch operands:
             // 0. CR0 register
             // 1. bc opcode
@@ -101,17 +108,21 @@
             unsigned Opcode = MBBI->getOperand(1).getImmedValue();
             unsigned Inverted = PPC32InstrInfo::invertPPCBranchOpcode(Opcode);
 
-            MachineInstr *MI = MBBI;
             if (Displacement >= -32768 && Displacement <= 32767) {
-              BuildMI(*MBB, MBBI, Opcode, 2).addReg(PPC::CR0).addMBB(trueMBB);
+              BuildMI(*MBB, MBBJ, Opcode, 2).addReg(PPC::CR0).addMBB(trueMBB);
             } else {
-              BuildMI(*MBB, MBBI, Inverted, 2).addReg(PPC::CR0).addSImm(8);
-              BuildMI(*MBB, MBBI, PPC::B, 1).addMBB(trueMBB);
-              BuildMI(*MBB, MBBI, PPC::B, 1).addMBB(falseMBB);
+              BuildMI(*MBB, MBBJ, Inverted, 2).addReg(PPC::CR0).addSImm(8);
+              BuildMI(*MBB, MBBJ, PPC::B, 1).addMBB(trueMBB);
+              BuildMI(*MBB, MBBJ, PPC::B, 1).addMBB(falseMBB);
             }
-            MBB->erase(MI);
+
+            // Erase the psuedo COND_BRANCH instruction, and then back up the
+            // iterator so that when the for loop increments it, we end up in
+            // the correct place rather than iterating off the end.
+            MBB->erase(MBBI);
+            MBBI = --MBBJ;
           }
-          ByteCount += bytesForOpcode(MBBI->getOpcode());
+          ByteCount += bytesForOpcode(OpcodeToReplace);
         }
       }
 





From natebegeman at mac.com  Sun Jun 12 18:53:09 2005
From: natebegeman at mac.com (Nate Begeman)
Date: Sun, 12 Jun 2005 18:53:09 -0500
Subject: [llvm-commits] CVS: llvm/lib/Target/SparcV9/SparcV9Internals.h
	SparcV9RegClassInfo.cpp SparcV9RegClassInfo.h
	SparcV9RegInfo.cpp SparcV9RegInfo.h 
Message-ID: <200506122353.SAA03549@zion.cs.uiuc.edu>



Changes in directory llvm/lib/Target/SparcV9:

SparcV9Internals.h updated: 1.120 -> 1.121
SparcV9RegClassInfo.cpp updated: 1.40 -> 1.41
SparcV9RegClassInfo.h updated: 1.29 -> 1.30
SparcV9RegInfo.cpp updated: 1.140 -> 1.141
SparcV9RegInfo.h updated: 1.18 -> 1.19
---
Log message:

When compiled with GCC 4.0, a latent bug was exposed where both SparcV9
and the target independant register allocator were both using a class named
'LiveRange'.  This lead to the target independant code calling code in the
SparcV9 backend, which crashed.  Fixed by renaming SparcV9's LiveRange to
V9LiveRange.


---
Diffs of the changes:  (+21 -21)

 SparcV9Internals.h      |    2 +-
 SparcV9RegClassInfo.cpp |   12 ++++++------
 SparcV9RegClassInfo.h   |    2 +-
 SparcV9RegInfo.cpp      |   20 ++++++++++----------
 SparcV9RegInfo.h        |    6 +++---
 5 files changed, 21 insertions(+), 21 deletions(-)


Index: llvm/lib/Target/SparcV9/SparcV9Internals.h
diff -u llvm/lib/Target/SparcV9/SparcV9Internals.h:1.120 llvm/lib/Target/SparcV9/SparcV9Internals.h:1.121
--- llvm/lib/Target/SparcV9/SparcV9Internals.h:1.120	Thu Apr 21 18:25:42 2005
+++ llvm/lib/Target/SparcV9/SparcV9Internals.h	Sun Jun 12 18:52:58 2005
@@ -25,7 +25,7 @@
 
 namespace llvm {
 
-class LiveRange;
+class V9LiveRange;
 class SparcV9TargetMachine;
 class ModulePass;
 class GetElementPtrInst;


Index: llvm/lib/Target/SparcV9/SparcV9RegClassInfo.cpp
diff -u llvm/lib/Target/SparcV9/SparcV9RegClassInfo.cpp:1.40 llvm/lib/Target/SparcV9/SparcV9RegClassInfo.cpp:1.41
--- llvm/lib/Target/SparcV9/SparcV9RegClassInfo.cpp:1.40	Thu Apr 21 18:25:42 2005
+++ llvm/lib/Target/SparcV9/SparcV9RegClassInfo.cpp	Sun Jun 12 18:52:58 2005
@@ -39,7 +39,7 @@
 void SparcV9IntRegClass::colorIGNode(IGNode * Node,
                                const std::vector<bool> &IsColorUsedArr) const
 {
-  LiveRange *LR = Node->getParentLR();
+  V9LiveRange *LR = Node->getParentLR();
 
   if (DEBUG_RA)
     std::cerr << "\nColoring LR [CallInt=" << LR->isCallInterference() <<"]:"
@@ -152,7 +152,7 @@
   // spill algorithm cannot find it.  In particular, we have to choose
   // whether to use %xcc or %icc based on type of value compared
   //
-  const LiveRange* ccLR = Node->getParentLR();
+  const V9LiveRange* ccLR = Node->getParentLR();
   const Type* setCCType = (* ccLR->begin())->getType(); // any Value in LR
   assert(setCCType->isIntegral() || isa<PointerType>(setCCType));
   int ccReg = ((isa<PointerType>(setCCType) || setCCType == Type::LongTy)
@@ -161,7 +161,7 @@
 #ifndef NDEBUG
   // Let's just make sure values of two different types have not been
   // coalesced into this LR.
-  for (LiveRange::const_iterator I=ccLR->begin(), E=ccLR->end(); I!=E; ++I) {
+  for (V9LiveRange::const_iterator I=ccLR->begin(), E=ccLR->end(); I!=E; ++I) {
     const Type* ccType = (*I)->getType();
     assert((ccReg == xcc && (isa<PointerType>(ccType)
                              || ccType == Type::LongTy)) ||
@@ -205,7 +205,7 @@
 void SparcV9FloatRegClass::colorIGNode(IGNode * Node,
                                  const std::vector<bool> &IsColorUsedArr) const
 {
-  LiveRange *LR = Node->getParentLR();
+  V9LiveRange *LR = Node->getParentLR();
 
 #ifndef NDEBUG
   // Check that the correct colors have been are marked for fp-doubles.
@@ -222,7 +222,7 @@
   unsigned NumNeighbors =  Node->getNumOfNeighbors();   // total # of neighbors
   for(unsigned n=0; n < NumNeighbors; n++) {            // for each neigh
     IGNode *NeighIGNode = Node->getAdjIGNode(n);
-    LiveRange *NeighLR = NeighIGNode->getParentLR();
+    V9LiveRange *NeighLR = NeighIGNode->getParentLR();
 
     if (NeighLR->hasColor()) {
       assert(IsColorUsedArr[ NeighLR->getColor() ]);
@@ -369,7 +369,7 @@
 // type of the Node (i.e., float/double)
 //-----------------------------------------------------------------------------
 
-int SparcV9FloatRegClass::findFloatColor(const LiveRange *LR,
+int SparcV9FloatRegClass::findFloatColor(const V9LiveRange *LR,
                                        unsigned Start,
                                        unsigned End,
                                const std::vector<bool> &IsColorUsedArr) const


Index: llvm/lib/Target/SparcV9/SparcV9RegClassInfo.h
diff -u llvm/lib/Target/SparcV9/SparcV9RegClassInfo.h:1.29 llvm/lib/Target/SparcV9/SparcV9RegClassInfo.h:1.30
--- llvm/lib/Target/SparcV9/SparcV9RegClassInfo.h:1.29	Thu Apr 21 18:25:42 2005
+++ llvm/lib/Target/SparcV9/SparcV9RegClassInfo.h	Sun Jun 12 18:52:58 2005
@@ -89,7 +89,7 @@
 //-----------------------------------------------------------------------------
 
 class SparcV9FloatRegClass : public TargetRegClassInfo {
-  int findFloatColor(const LiveRange *LR, unsigned Start,
+  int findFloatColor(const V9LiveRange *LR, unsigned Start,
 		     unsigned End,
                      const std::vector<bool> &IsColorUsedArr) const;
 public:


Index: llvm/lib/Target/SparcV9/SparcV9RegInfo.cpp
diff -u llvm/lib/Target/SparcV9/SparcV9RegInfo.cpp:1.140 llvm/lib/Target/SparcV9/SparcV9RegInfo.cpp:1.141
--- llvm/lib/Target/SparcV9/SparcV9RegInfo.cpp:1.140	Thu Apr 21 18:25:42 2005
+++ llvm/lib/Target/SparcV9/SparcV9RegInfo.cpp	Sun Jun 12 18:52:58 2005
@@ -221,7 +221,7 @@
 //---------------------------------------------------------------------------
 
 // The following 4  methods are used to find the RegType (SparcV9Internals.h)
-// of a LiveRange, a Value, and for a given register unified reg number.
+// of a V9LiveRange, a Value, and for a given register unified reg number.
 //
 int SparcV9RegInfo::getRegTypeForClassAndType(unsigned regClassID,
                                                  const Type* type) const
@@ -244,7 +244,7 @@
   return getRegTypeForClassAndType(getRegClassIDOfType(type), type);
 }
 
-int SparcV9RegInfo::getRegTypeForLR(const LiveRange *LR) const
+int SparcV9RegInfo::getRegTypeForLR(const V9LiveRange *LR) const
 {
   return getRegTypeForClassAndType(LR->getRegClassID(), LR->getType());
 }
@@ -330,7 +330,7 @@
   // MachineOperand & MO  = RetMI->getOperand(0);
   // const Value *RetAddrVal = MO.getVRegValue();
   // assert( RetAddrVal && "LR for ret address must be created at start");
-  // LiveRange * RetAddrLR = LRI.getLiveRangeForValue( RetAddrVal);
+  // V9LiveRange * RetAddrLR = LRI.getLiveRangeForValue( RetAddrVal);
   // RetAddrLR->setSuggestedColor(getUnifiedRegNum( IntRegClassID,
   //                              SparcV9IntRegOrdr::i7) );
 }
@@ -349,7 +349,7 @@
   assert(RetAddrVal && "INTERNAL ERROR: Return address value is required");
 
   // A LR must already exist for the return address.
-  LiveRange *RetAddrLR = LRI.getLiveRangeForValue(RetAddrVal);
+  V9LiveRange *RetAddrLR = LRI.getLiveRangeForValue(RetAddrVal);
   assert(RetAddrLR && "INTERNAL ERROR: No LR for return address of call!");
 
   unsigned RegClassID = RetAddrLR->getRegClassID();
@@ -376,7 +376,7 @@
   unsigned argNo=0;
   for(Function::const_arg_iterator I = Meth->arg_begin(), E = Meth->arg_end();
       I != E; ++I, ++argNo) {
-    LiveRange *LR = LRI.getLiveRangeForValue(I);
+    V9LiveRange *LR = LRI.getLiveRangeForValue(I);
     assert(LR && "No live range found for method arg");
 
     unsigned regType = getRegTypeForLR(LR);
@@ -413,7 +413,7 @@
   for(Function::const_arg_iterator I = Meth->arg_begin(), E = Meth->arg_end();
       I != E; ++I, ++argNo) {
     // get the LR of arg
-    LiveRange *LR = LRI.getLiveRangeForValue(I);
+    V9LiveRange *LR = LRI.getLiveRangeForValue(I);
     assert( LR && "No live range found for method arg");
 
     unsigned regType = getRegTypeForLR(LR);
@@ -584,7 +584,7 @@
   // or in %f0 if the value is a float type.
   //
   if (const Value *RetVal = argDesc->getReturnValue()) {
-    LiveRange *RetValLR = LRI.getLiveRangeForValue(RetVal);
+    V9LiveRange *RetValLR = LRI.getLiveRangeForValue(RetVal);
     assert(RetValLR && "No LR for return Value of call!");
 
     unsigned RegClassID = RetValLR->getRegClassID();
@@ -610,7 +610,7 @@
     const Value *CallArg = argDesc->getArgInfo(i).getArgVal();
 
     // get the LR of call operand (parameter)
-    LiveRange *const LR = LRI.getLiveRangeForValue(CallArg);
+    V9LiveRange *const LR = LRI.getLiveRangeForValue(CallArg);
     if (!LR)
       continue;                    // no live ranges for constants and labels
 
@@ -651,7 +651,7 @@
   Value* tmpI = RetMI->getOperand(0).getVRegValue();
   ReturnInst* retI=cast<ReturnInst>(cast<TmpInstruction>(tmpI)->getOperand(0));
   if (const Value *RetVal = retI->getReturnValue())
-    if (LiveRange *const LR = LRI.getLiveRangeForValue(RetVal))
+    if (V9LiveRange *const LR = LRI.getLiveRangeForValue(RetVal))
       LR->setSuggestedColor(LR->getRegClassID() == IntRegClassID
                             ? (unsigned) SparcV9IntRegClass::i0
                             : (unsigned) SparcV9FloatRegClass::f0);
@@ -948,7 +948,7 @@
 // Print the register assigned to a LR
 //---------------------------------------------------------------------------
 
-void SparcV9RegInfo::printReg(const LiveRange *LR) const {
+void SparcV9RegInfo::printReg(const V9LiveRange *LR) const {
   unsigned RegClassID = LR->getRegClassID();
   std::cerr << " Node ";
 


Index: llvm/lib/Target/SparcV9/SparcV9RegInfo.h
diff -u llvm/lib/Target/SparcV9/SparcV9RegInfo.h:1.18 llvm/lib/Target/SparcV9/SparcV9RegInfo.h:1.19
--- llvm/lib/Target/SparcV9/SparcV9RegInfo.h:1.18	Wed May 11 16:40:40 2005
+++ llvm/lib/Target/SparcV9/SparcV9RegInfo.h	Sun Jun 12 18:52:58 2005
@@ -27,7 +27,7 @@
 class Value;
 class LiveRangeInfo;
 class Function;
-class LiveRange;
+class V9LiveRange;
 class AddedInstrns;
 class MachineInstr;
 class BasicBlock;
@@ -324,7 +324,7 @@
 
   // method used for printing a register for debugging purposes
   //
-  void printReg(const LiveRange *LR) const;
+  void printReg(const V9LiveRange *LR) const;
 
   // To obtain the return value and the indirect call address (if any)
   // contained in a CALL machine instruction
@@ -369,7 +369,7 @@
   // The reg class of a LR depends both on the Value types in it and whether
   // they are CC registers or not (for example).
   int getRegTypeForDataType(const Type* type) const;
-  int getRegTypeForLR(const LiveRange *LR) const;
+  int getRegTypeForLR(const V9LiveRange *LR) const;
   int getRegType(int unifiedRegNum) const;
 
   unsigned getFramePointer() const;





From natebegeman at mac.com  Sun Jun 12 18:53:09 2005
From: natebegeman at mac.com (Nate Begeman)
Date: Sun, 12 Jun 2005 18:53:09 -0500
Subject: [llvm-commits] CVS: llvm/lib/Target/SparcV9/RegAlloc/IGNode.h
	InterferenceGraph.cpp InterferenceGraph.h LiveRange.h
	LiveRangeInfo.cpp LiveRangeInfo.h Notes.txt PhyRegAlloc.cpp
	PhyRegAlloc.h RegClass.cpp RegClass.h 
Message-ID: <200506122353.SAA03573@zion.cs.uiuc.edu>



Changes in directory llvm/lib/Target/SparcV9/RegAlloc:

IGNode.h updated: 1.21 -> 1.22
InterferenceGraph.cpp updated: 1.23 -> 1.24
InterferenceGraph.h updated: 1.8 -> 1.9
LiveRange.h updated: 1.30 -> 1.31
LiveRangeInfo.cpp updated: 1.59 -> 1.60
LiveRangeInfo.h updated: 1.27 -> 1.28
Notes.txt updated: 1.1 -> 1.2
PhyRegAlloc.cpp updated: 1.167 -> 1.168
PhyRegAlloc.h updated: 1.70 -> 1.71
RegClass.cpp updated: 1.32 -> 1.33
RegClass.h updated: 1.24 -> 1.25
---
Log message:

When compiled with GCC 4.0, a latent bug was exposed where both SparcV9
and the target independant register allocator were both using a class named
'LiveRange'.  This lead to the target independant code calling code in the
SparcV9 backend, which crashed.  Fixed by renaming SparcV9's LiveRange to
V9LiveRange.


---
Diffs of the changes:  (+87 -85)

 IGNode.h              |    6 +++---
 InterferenceGraph.cpp |   17 +++++++++--------
 InterferenceGraph.h   |   14 +++++++-------
 LiveRange.h           |   11 ++++++-----
 LiveRangeInfo.cpp     |   38 +++++++++++++++++++-------------------
 LiveRangeInfo.h       |   20 ++++++++++----------
 Notes.txt             |    8 ++++----
 PhyRegAlloc.cpp       |   38 +++++++++++++++++++-------------------
 PhyRegAlloc.h         |    2 +-
 RegClass.cpp          |    4 ++--
 RegClass.h            |   14 +++++++-------
 11 files changed, 87 insertions(+), 85 deletions(-)


Index: llvm/lib/Target/SparcV9/RegAlloc/IGNode.h
diff -u llvm/lib/Target/SparcV9/RegAlloc/IGNode.h:1.21 llvm/lib/Target/SparcV9/RegAlloc/IGNode.h:1.22
--- llvm/lib/Target/SparcV9/RegAlloc/IGNode.h:1.21	Thu Apr 21 18:30:14 2005
+++ llvm/lib/Target/SparcV9/RegAlloc/IGNode.h	Sun Jun 12 18:52:58 2005
@@ -55,10 +55,10 @@
   // Decremented when a neighbor is pushed on to the stack.
   // After that, never incremented/set again nor used.
 
-  LiveRange *const ParentLR;
+  V9LiveRange *const ParentLR;
 public:
 
-  IGNode(LiveRange *LR, unsigned index) : Index(index), ParentLR(LR) {
+  IGNode(V9LiveRange *LR, unsigned index) : Index(index), ParentLR(LR) {
     OnStack = false;
     CurDegree = -1;
     ParentLR->setUserIGNode(this);
@@ -115,7 +115,7 @@
 
   inline void setColor(unsigned Col) { ParentLR->setColor(Col);  }
 
-  inline LiveRange *getParentLR() const { return ParentLR; }
+  inline V9LiveRange *getParentLR() const { return ParentLR; }
 };
 
 } // End llvm namespace


Index: llvm/lib/Target/SparcV9/RegAlloc/InterferenceGraph.cpp
diff -u llvm/lib/Target/SparcV9/RegAlloc/InterferenceGraph.cpp:1.23 llvm/lib/Target/SparcV9/RegAlloc/InterferenceGraph.cpp:1.24
--- llvm/lib/Target/SparcV9/RegAlloc/InterferenceGraph.cpp:1.23	Thu Apr 21 18:30:14 2005
+++ llvm/lib/Target/SparcV9/RegAlloc/InterferenceGraph.cpp	Sun Jun 12 18:52:58 2005
@@ -74,7 +74,7 @@
 //-----------------------------------------------------------------------------
 // creates a new IGNode for the given live range and add to IG
 //-----------------------------------------------------------------------------
-void InterferenceGraph::addLRToIG(LiveRange *const LR)
+void InterferenceGraph::addLRToIG(V9LiveRange *const LR)
 {
   IGNodeList.push_back(new IGNode(LR, IGNodeList.size()));
 }
@@ -87,8 +87,8 @@
 // are not updated. LR1 and LR2 must be distinct since if not, it suggests
 // that there is some wrong logic in some other method.
 //-----------------------------------------------------------------------------
-void InterferenceGraph::setInterference(const LiveRange *const LR1,
-					const LiveRange *const LR2 ) {
+void InterferenceGraph::setInterference(const V9LiveRange *const LR1,
+					const V9LiveRange *const LR2 ) {
   assert(LR1 != LR2);
 
   IGNode *IGNode1 = LR1->getUserIGNode();
@@ -119,8 +119,9 @@
 //----------------------------------------------------------------------------
 // return whether two live ranges interfere
 //----------------------------------------------------------------------------
-unsigned InterferenceGraph::getInterference(const LiveRange *const LR1,
-                                            const LiveRange *const LR2) const {
+unsigned InterferenceGraph::getInterference(const V9LiveRange *const LR1,
+                                            const V9LiveRange *const LR2) 
+                                            const {
   assert(LR1 != LR2);
   assertIGNode(this, LR1->getUserIGNode());
   assertIGNode(this, LR2->getUserIGNode());
@@ -145,8 +146,8 @@
 //            LiveRangeInfo::unionAndUpdateLRs for that purpose.
 //----------------------------------------------------------------------------
 
-void InterferenceGraph::mergeIGNodesOfLRs(const LiveRange *LR1,
-					  LiveRange *LR2) {
+void InterferenceGraph::mergeIGNodesOfLRs(const V9LiveRange *LR1,
+					                            V9LiveRange *LR2) {
 
   assert( LR1 != LR2);                  // cannot merge the same live range
 
@@ -168,7 +169,7 @@
   for(unsigned i=0; i < SrcDegree; i++) {
     IGNode *NeighNode = SrcNode->getAdjIGNode(i);
 
-    LiveRange *const LROfNeigh = NeighNode->getParentLR();
+    V9LiveRange *const LROfNeigh = NeighNode->getParentLR();
 
     // delete edge between src and neigh - even neigh == dest
     NeighNode->delAdjIGNode(SrcNode);


Index: llvm/lib/Target/SparcV9/RegAlloc/InterferenceGraph.h
diff -u llvm/lib/Target/SparcV9/RegAlloc/InterferenceGraph.h:1.8 llvm/lib/Target/SparcV9/RegAlloc/InterferenceGraph.h:1.9
--- llvm/lib/Target/SparcV9/RegAlloc/InterferenceGraph.h:1.8	Thu Apr 21 18:30:14 2005
+++ llvm/lib/Target/SparcV9/RegAlloc/InterferenceGraph.h	Sun Jun 12 18:52:58 2005
@@ -33,7 +33,7 @@
 
 namespace llvm {
 
-class LiveRange;
+class V9LiveRange;
 class RegClass;
 class IGNode;
 
@@ -51,15 +51,15 @@
 
   void createGraph();
 
-  void addLRToIG(LiveRange *LR);
+  void addLRToIG(V9LiveRange *LR);
 
-  void setInterference(const LiveRange *LR1,
-                       const LiveRange *LR2);
+  void setInterference(const V9LiveRange *LR1,
+                       const V9LiveRange *LR2);
 
-  unsigned getInterference(const LiveRange *LR1,
-                           const LiveRange *LR2) const ;
+  unsigned getInterference(const V9LiveRange *LR1,
+                           const V9LiveRange *LR2) const ;
 
-  void mergeIGNodesOfLRs(const LiveRange *LR1, LiveRange *LR2);
+  void mergeIGNodesOfLRs(const V9LiveRange *LR1, V9LiveRange *LR2);
 
   std::vector<IGNode *> &getIGNodeList() { return IGNodeList; }
   const std::vector<IGNode *> &getIGNodeList() const { return IGNodeList; }


Index: llvm/lib/Target/SparcV9/RegAlloc/LiveRange.h
diff -u llvm/lib/Target/SparcV9/RegAlloc/LiveRange.h:1.30 llvm/lib/Target/SparcV9/RegAlloc/LiveRange.h:1.31
--- llvm/lib/Target/SparcV9/RegAlloc/LiveRange.h:1.30	Thu Apr 21 18:30:14 2005
+++ llvm/lib/Target/SparcV9/RegAlloc/LiveRange.h	Sun Jun 12 18:52:58 2005
@@ -8,7 +8,7 @@
 //===----------------------------------------------------------------------===//
 //
 // Implements a live range using a SetVector of Value *s.  We keep only
-// defs in a LiveRange.
+// defs in a V9LiveRange.
 //
 //===----------------------------------------------------------------------===//
 
@@ -24,14 +24,14 @@
 class RegClass;
 class IGNode;
 
-class LiveRange {
+class V9LiveRange {
 public:
   typedef SetVector<const Value *> ValueContainerType;
   typedef ValueContainerType::iterator iterator;
   typedef ValueContainerType::const_iterator const_iterator;
 
 private:
-  ValueContainerType MyValues; // Values in this LiveRange
+  ValueContainerType MyValues; // Values in this V9LiveRange
   RegClass *MyRegClass;        // register class (e.g., int, FP) for this LR
 
   /// doesSpanAcrossCalls - Does this live range span across calls?
@@ -82,7 +82,7 @@
   bool insert(const Value *&X)  { return MyValues.insert (X); }
   void insert(iterator b, iterator e) { MyValues.insert (b, e); }
 
-  LiveRange() {
+  V9LiveRange() {
     Color = SuggestedColor = -1;        // not yet colored
     mustSpill = false;
     MyRegClass = 0;
@@ -184,7 +184,8 @@
   }
 };
 
-static inline std::ostream &operator << (std::ostream &os, const LiveRange &lr) {
+static inline std::ostream &operator << (std::ostream &os, 
+                                         const V9LiveRange &lr) {
   os << "LiveRange@" << (void *)(&lr);
   return os;
 };


Index: llvm/lib/Target/SparcV9/RegAlloc/LiveRangeInfo.cpp
diff -u llvm/lib/Target/SparcV9/RegAlloc/LiveRangeInfo.cpp:1.59 llvm/lib/Target/SparcV9/RegAlloc/LiveRangeInfo.cpp:1.60
--- llvm/lib/Target/SparcV9/RegAlloc/LiveRangeInfo.cpp:1.59	Thu Apr 21 18:30:14 2005
+++ llvm/lib/Target/SparcV9/RegAlloc/LiveRangeInfo.cpp	Sun Jun 12 18:52:58 2005
@@ -27,7 +27,7 @@
 
 namespace llvm {
 
-unsigned LiveRange::getRegClassID() const { return getRegClass()->getID(); }
+unsigned V9LiveRange::getRegClassID() const { return getRegClass()->getID(); }
 
 LiveRangeInfo::LiveRangeInfo(const Function *F, const TargetMachine &tm,
 			     std::vector<RegClass *> &RCL)
@@ -39,14 +39,14 @@
        MI != LiveRangeMap.end(); ++MI) {
 
     if (MI->first && MI->second) {
-      LiveRange *LR = MI->second;
+      V9LiveRange *LR = MI->second;
 
       // we need to be careful in deleting LiveRanges in LiveRangeMap
       // since two/more Values in the live range map can point to the same
       // live range. We have to make the other entries NULL when we delete
       // a live range.
 
-      for (LiveRange::iterator LI = LR->begin(); LI != LR->end(); ++LI)
+      for (V9LiveRange::iterator LI = LR->begin(); LI != LR->end(); ++LI)
         LiveRangeMap[*LI] = 0;
 
       delete LR;
@@ -61,14 +61,14 @@
 // LRs don't have suggested colors
 //---------------------------------------------------------------------------
 
-void LiveRangeInfo::unionAndUpdateLRs(LiveRange *L1, LiveRange *L2) {
+void LiveRangeInfo::unionAndUpdateLRs(V9LiveRange *L1, V9LiveRange *L2) {
   assert(L1 != L2 && (!L1->hasSuggestedColor() || !L2->hasSuggestedColor()));
   assert(! (L1->hasColor() && L2->hasColor()) ||
          L1->getColor() == L2->getColor());
 
   L2->insert (L1->begin(), L1->end());   // add elements of L2 to L1
 
-  for(LiveRange::iterator L2It = L2->begin(); L2It != L2->end(); ++L2It) {
+  for(V9LiveRange::iterator L2It = L2->begin(); L2It != L2->end(); ++L2It) {
     L1->insert(*L2It);                  // add the var in L2 to L1
     LiveRangeMap[*L2It] = L1;           // now the elements in L2 should map
                                         //to L1
@@ -101,10 +101,10 @@
 // Note: this function does *not* check that no live range exists for def.
 //---------------------------------------------------------------------------
 
-LiveRange*
+V9LiveRange*
 LiveRangeInfo::createNewLiveRange(const Value* Def, bool isCC /* = false*/)
 {
-  LiveRange* DefRange = new LiveRange();  // Create a new live range,
+  V9LiveRange* DefRange = new V9LiveRange();  // Create a new live range,
   DefRange->insert(Def);                  // add Def to it,
   LiveRangeMap[Def] = DefRange;           // and update the map.
 
@@ -121,10 +121,10 @@
 }
 
 
-LiveRange*
+V9LiveRange*
 LiveRangeInfo::createOrAddToLiveRange(const Value* Def, bool isCC /* = false*/)
 {
-  LiveRange *DefRange = LiveRangeMap[Def];
+  V9LiveRange *DefRange = LiveRangeMap[Def];
 
   // check if the LR is already there (because of multiple defs)
   if (!DefRange) {
@@ -188,10 +188,10 @@
 	  const Value *Def = *OpI;
           bool isCC = (OpI.getMachineOperand().getType()
                        == MachineOperand::MO_CCRegister);
-          LiveRange* LR = createOrAddToLiveRange(Def, isCC);
+          V9LiveRange* LR = createOrAddToLiveRange(Def, isCC);
 
           // If the operand has a pre-assigned register,
-          // set it directly in the LiveRange
+          // set it directly in the V9LiveRange
           if (OpI.getMachineOperand().hasAllocatedReg()) {
             unsigned getClassId;
             LR->setColor(MRI.getClassRegNum(OpI.getMachineOperand().getReg(),
@@ -204,10 +204,10 @@
       for (unsigned i = 0; i < MInst->getNumImplicitRefs(); ++i)
 	if (MInst->getImplicitOp(i).isDef()) {
 	  const Value *Def = MInst->getImplicitRef(i);
-          LiveRange* LR = createOrAddToLiveRange(Def, /*isCC*/ false);
+          V9LiveRange* LR = createOrAddToLiveRange(Def, /*isCC*/ false);
 
           // If the implicit operand has a pre-assigned register,
-          // set it directly in the LiveRange
+          // set it directly in the V9LiveRange
           if (MInst->getImplicitOp(i).hasAllocatedReg()) {
             unsigned getClassId;
             LR->setColor(MRI.getClassRegNum(
@@ -277,10 +277,10 @@
 // Checks if live range LR interferes with any node assigned or suggested to
 // be assigned the specified color
 //
-inline bool InterferesWithColor(const LiveRange& LR, unsigned color) {
+inline bool InterferesWithColor(const V9LiveRange& LR, unsigned color) {
   IGNode* lrNode = LR.getUserIGNode();
   for (unsigned n=0, NN = lrNode->getNumOfNeighbors(); n < NN; n++) {
-    LiveRange *neighLR = lrNode->getAdjIGNode(n)->getParentLR();
+    V9LiveRange *neighLR = lrNode->getAdjIGNode(n)->getParentLR();
     if (neighLR->hasColor() && neighLR->getColor() == color)
       return true;
     if (neighLR->hasSuggestedColor() && neighLR->getSuggestedColor() == color)
@@ -296,8 +296,8 @@
 // (3) LR1 has color and LR2 interferes with any LR that has the same color
 // (4) LR2 has color and LR1 interferes with any LR that has the same color
 //
-inline bool InterfsPreventCoalescing(const LiveRange& LROfDef,
-                                     const LiveRange& LROfUse) {
+inline bool InterfsPreventCoalescing(const V9LiveRange& LROfDef,
+                                     const V9LiveRange& LROfUse) {
   // (4) if they have different suggested colors, cannot coalesce
   if (LROfDef.hasSuggestedColor() && LROfUse.hasSuggestedColor())
     return true;
@@ -341,13 +341,13 @@
       for(MachineInstr::const_val_op_iterator DefI = MI->begin(),
             DefE = MI->end(); DefI != DefE; ++DefI) {
 	if (DefI.isDef()) { // this operand is modified
-	  LiveRange *LROfDef = getLiveRangeForValue( *DefI );
+	  V9LiveRange *LROfDef = getLiveRangeForValue( *DefI );
 	  RegClass *RCOfDef = LROfDef->getRegClass();
 
 	  MachineInstr::const_val_op_iterator UseI = MI->begin(),
             UseE = MI->end();
 	  for( ; UseI != UseE; ++UseI) { // for all uses
- 	    LiveRange *LROfUse = getLiveRangeForValue( *UseI );
+ 	    V9LiveRange *LROfUse = getLiveRangeForValue( *UseI );
 	    if (!LROfUse) {             // if LR of use is not found
 	      //don't warn about labels
 	      if (!isa<BasicBlock>(*UseI) && DEBUG_RA >= RA_DEBUG_LiveRanges)


Index: llvm/lib/Target/SparcV9/RegAlloc/LiveRangeInfo.h
diff -u llvm/lib/Target/SparcV9/RegAlloc/LiveRangeInfo.h:1.27 llvm/lib/Target/SparcV9/RegAlloc/LiveRangeInfo.h:1.28
--- llvm/lib/Target/SparcV9/RegAlloc/LiveRangeInfo.h:1.27	Thu Apr 21 18:30:14 2005
+++ llvm/lib/Target/SparcV9/RegAlloc/LiveRangeInfo.h	Sun Jun 12 18:52:58 2005
@@ -31,7 +31,7 @@
 
 namespace llvm {
 
-class LiveRange;
+class V9LiveRange;
 class MachineInstr;
 class RegClass;
 class SparcV9RegInfo;
@@ -40,7 +40,7 @@
 class Function;
 class Instruction;
 
-typedef hash_map<const Value*, LiveRange*> LiveRangeMapType;
+typedef hash_map<const Value*, V9LiveRange*> LiveRangeMapType;
 
 //----------------------------------------------------------------------------
 // Class LiveRangeInfo
@@ -51,7 +51,7 @@
 
 class LiveRangeInfo {
   const Function *const Meth;       // Func for which live range info is held
-  LiveRangeMapType  LiveRangeMap;   // A map from Value * to LiveRange * to
+  LiveRangeMapType  LiveRangeMap;   // A map from Value * to V9LiveRange * to
                                     // record all live ranges in a method
                                     // created by constructLiveRanges
 
@@ -65,14 +65,14 @@
 
   //------------ Private methods (see LiveRangeInfo.cpp for description)-------
 
-  LiveRange* createNewLiveRange         (const Value* Def,
+  V9LiveRange* createNewLiveRange         (const Value* Def,
                                          bool isCC = false);
 
-  LiveRange* createOrAddToLiveRange     (const Value* Def,
+  V9LiveRange* createOrAddToLiveRange     (const Value* Def,
                                          bool isCC = false);
 
-  void unionAndUpdateLRs                (LiveRange *L1,
-                                         LiveRange *L2);
+  void unionAndUpdateLRs                (V9LiveRange *L1,
+                                         V9LiveRange *L2);
 
   void suggestRegs4CallRets             ();
 public:
@@ -82,7 +82,7 @@
 		std::vector<RegClass *> & RCList);
 
 
-  /// Destructor to destroy all LiveRanges in the LiveRange Map
+  /// Destructor to destroy all LiveRanges in the V9LiveRange Map
   ///
   ~LiveRangeInfo();
 
@@ -98,10 +98,10 @@
   /// Method used to get the live range containing a Value.
   /// This may return NULL if no live range exists for a Value (eg, some consts)
   ///
-  inline LiveRange *getLiveRangeForValue(const Value *Val) {
+  inline V9LiveRange *getLiveRangeForValue(const Value *Val) {
     return LiveRangeMap[Val];
   }
-  inline const LiveRange *getLiveRangeForValue(const Value *Val) const {
+  inline const V9LiveRange *getLiveRangeForValue(const Value *Val) const {
     LiveRangeMapType::const_iterator I = LiveRangeMap.find(Val);
     return I->second;
   }


Index: llvm/lib/Target/SparcV9/RegAlloc/Notes.txt
diff -u llvm/lib/Target/SparcV9/RegAlloc/Notes.txt:1.1 llvm/lib/Target/SparcV9/RegAlloc/Notes.txt:1.2
--- llvm/lib/Target/SparcV9/RegAlloc/Notes.txt:1.1	Mon Aug  2 23:15:02 2004
+++ llvm/lib/Target/SparcV9/RegAlloc/Notes.txt	Sun Jun 12 18:52:58 2005
@@ -92,10 +92,10 @@
 the instruction stream. Note however that, live ranges are not constructed for
 constants which are not defined in the instruction stream. 
 
-A LiveRange is a set of Values (only defs) in that live range. Live range
+A V9LiveRange is a set of Values (only defs) in that live range. Live range
 construction is done in combination for all register classes. All the live
 ranges for a method are entered to a LiveRangeMap which can be accessed using 
-any Value in the LiveRange.
+any Value in the V9LiveRange.
 
 After live ranges have been constructed, we call machine specific code to 
 suggest colors for speical live ranges. For instance, incoming args, call args,
@@ -109,7 +109,7 @@
 copy instructions to move the value into requred registers and its done in
 step 5 above.
 
-See LiveRange.h, LiveRangeInfo.h (and  LiveRange.cpp, LiveRangeInfo.cpp) for
+See LiveRange.h, LiveRangeInfo.h (and LiveRange.cpp, LiveRangeInfo.cpp) for
 algorithms and details. See SparcRegInfo.cpp for suggesting colors for 
 incoming/call arguments and return values.
 
@@ -121,7 +121,7 @@
 graph, building all interference graphs is performed in one pass. Also, the
 adjacency list for each live range is built in this phase. Consequently, each
 register class has an interference graph (which is a bit matrix) and each
-LiveRange has an adjacency list to record its neighbors. Live variable info
+V9LiveRange has an adjacency list to record its neighbors. Live variable info
 is used for finding the interferences.
 
 See IGNode.h, InterferenceGraph.h (and IGNode.h, InterferenceGraph.h) for 


Index: llvm/lib/Target/SparcV9/RegAlloc/PhyRegAlloc.cpp
diff -u llvm/lib/Target/SparcV9/RegAlloc/PhyRegAlloc.cpp:1.167 llvm/lib/Target/SparcV9/RegAlloc/PhyRegAlloc.cpp:1.168
--- llvm/lib/Target/SparcV9/RegAlloc/PhyRegAlloc.cpp:1.167	Thu Apr 21 18:30:14 2005
+++ llvm/lib/Target/SparcV9/RegAlloc/PhyRegAlloc.cpp	Sun Jun 12 18:52:58 2005
@@ -98,7 +98,7 @@
 
   for (; HMI != HMIEnd ; ++HMI ) {
     if (HMI->first) {
-      LiveRange *L = HMI->second;   // get the LiveRange
+      V9LiveRange *L = HMI->second;   // get the V9LiveRange
       if (!L) {
         if (DEBUG_RA && !isa<ConstantIntegral> (HMI->first))
           std::cerr << "\n**** ?!?WARNING: NULL LIVE RANGE FOUND FOR: "
@@ -133,7 +133,7 @@
   ValueSet::const_iterator LIt = LVSet->begin();
 
   // get the live range of instruction
-  const LiveRange *const LROfDef = LRI->getLiveRangeForValue( Def );
+  const V9LiveRange *const LROfDef = LRI->getLiveRangeForValue( Def );
 
   IGNode *const IGNodeOfDef = LROfDef->getUserIGNode();
   assert( IGNodeOfDef );
@@ -147,7 +147,7 @@
       std::cerr << "< Def=" << RAV(Def) << ", Lvar=" << RAV(*LIt) << "> ";
 
     //  get the live range corresponding to live var
-    LiveRange *LROfVar = LRI->getLiveRangeForValue(*LIt);
+    V9LiveRange *LROfVar = LRI->getLiveRangeForValue(*LIt);
 
     // LROfVar can be null if it is a const since a const
     // doesn't have a dominating def - see Assumptions above
@@ -174,7 +174,7 @@
        LIt != LEnd; ++LIt) {
 
     //  get the live range corresponding to live var
-    LiveRange *const LR = LRI->getLiveRangeForValue(*LIt);
+    V9LiveRange *const LR = LRI->getLiveRangeForValue(*LIt);
 
     // LR can be null if it is a const since a const
     // doesn't have a dominating def - see Assumptions above
@@ -195,7 +195,7 @@
   CallArgsDescriptor* argDesc = CallArgsDescriptor::get(MInst);
 
   if (const Value *RetVal = argDesc->getReturnValue()) {
-    LiveRange *RetValLR = LRI->getLiveRangeForValue( RetVal );
+    V9LiveRange *RetValLR = LRI->getLiveRangeForValue( RetVal );
     assert( RetValLR && "No LR for RetValue of call");
     RetValLR->clearCallInterference();
   }
@@ -203,7 +203,7 @@
   // If the CALL is an indirect call, find the LR of the function pointer.
   // That has a call interference because it conflicts with outgoing args.
   if (const Value *AddrVal = argDesc->getIndirectFuncPtr()) {
-    LiveRange *AddrValLR = LRI->getLiveRangeForValue( AddrVal );
+    V9LiveRange *AddrValLR = LRI->getLiveRangeForValue( AddrVal );
     // LR can be null if the function pointer is a constant.
     if (AddrValLR)
       AddrValLR->setCallInterference();
@@ -254,7 +254,7 @@
 	  addInterference(*OpI, &LVSetAI, isCallInst);
 
 	// Calculate the spill cost of each live range
-	LiveRange *LR = LRI->getLiveRangeForValue(*OpI);
+	V9LiveRange *LR = LRI->getLiveRangeForValue(*OpI);
 	if (LR) LR->addSpillCost(BBLoopDepthCost);
       }
       // Also add interference for any implicit definitions in a machine
@@ -284,12 +284,12 @@
   // iterate over MI operands to find defs
   for (MachineInstr::const_val_op_iterator It1 = MInst->begin(),
          ItE = MInst->end(); It1 != ItE; ++It1) {
-    const LiveRange *LROfOp1 = LRI->getLiveRangeForValue(*It1);
+    const V9LiveRange *LROfOp1 = LRI->getLiveRangeForValue(*It1);
     assert((LROfOp1 || It1.isDef()) && "No LR for Def in PSEUDO insruction");
 
     MachineInstr::const_val_op_iterator It2 = It1;
     for (++It2; It2 != ItE; ++It2) {
-      const LiveRange *LROfOp2 = LRI->getLiveRangeForValue(*It2);
+      const V9LiveRange *LROfOp2 = LRI->getLiveRangeForValue(*It2);
 
       if (LROfOp2) {
 	RegClass *RCOfOp1 = LROfOp1->getRegClass();
@@ -398,7 +398,7 @@
       if (Op.getType() ==  MachineOperand::MO_VirtualRegister ||
           Op.getType() ==  MachineOperand::MO_CCRegister) {
           const Value *const Val =  Op.getVRegValue();
-          if (const LiveRange* LR = LRI->getLiveRangeForValue(Val)) {
+          if (const V9LiveRange* LR = LRI->getLiveRangeForValue(Val)) {
             // Remember if any operand needs spilling
             instrNeedsSpills |= LR->isMarkedForSpill();
 
@@ -456,7 +456,7 @@
         if (Op.getType() ==  MachineOperand::MO_VirtualRegister ||
             Op.getType() ==  MachineOperand::MO_CCRegister) {
             const Value* Val = Op.getVRegValue();
-            if (const LiveRange *LR = LRI->getLiveRangeForValue(Val))
+            if (const V9LiveRange *LR = LRI->getLiveRangeForValue(Val))
               if (LR->isMarkedForSpill())
                 insertCode4SpilledLR(LR, MII, MBB, OpNum);
           }
@@ -609,7 +609,7 @@
 /// instruction. Then it uses this register temporarily to accommodate the
 /// spilled value.
 ///
-void PhyRegAlloc::insertCode4SpilledLR(const LiveRange *LR,
+void PhyRegAlloc::insertCode4SpilledLR(const V9LiveRange *LR,
                                        MachineBasicBlock::iterator& MII,
                                        MachineBasicBlock &MBB,
 				       const unsigned OpNum) {
@@ -754,7 +754,7 @@
     assert(tmpRetVal->getOperand(0) == origRetVal &&
            tmpRetVal->getType() == origRetVal->getType() &&
            "Wrong implicit ref?");
-    LiveRange *RetValLR = LRI->getLiveRangeForValue(tmpRetVal);
+    V9LiveRange *RetValLR = LRI->getLiveRangeForValue(tmpRetVal);
     assert(RetValLR && "No LR for RetValue of call");
 
     if (! RetValLR->isMarkedForSpill())
@@ -768,7 +768,7 @@
   // for each live var in live variable set after machine inst
   for( ; LIt != LVSetAft.end(); ++LIt) {
     // get the live range corresponding to live var
-    LiveRange *const LR = LRI->getLiveRangeForValue(*LIt);
+    V9LiveRange *const LR = LRI->getLiveRangeForValue(*LIt);
 
     // LR can be null if it is a const since a const
     // doesn't have a dominating def - see Assumptions above
@@ -945,7 +945,7 @@
   // for each live var in live variable set after machine inst
   for ( ; LIt != LVSetBef->end(); ++LIt) {
     // Get the live range corresponding to live var, and its RegClass
-    LiveRange *const LRofLV = LRI->getLiveRangeForValue(*LIt );
+    V9LiveRange *const LRofLV = LRI->getLiveRangeForValue(*LIt );
 
     // LR can be null if it is a const since a const
     // doesn't have a dominating def - see Assumptions above
@@ -1023,7 +1023,7 @@
 
   // If there are implicit references, mark their allocated regs as well
   for (unsigned z=0; z < MI->getNumImplicitRefs(); z++)
-    if (const LiveRange*
+    if (const V9LiveRange*
         LRofImpRef = LRI->getLiveRangeForValue(MI->getImplicitRef(z)))
       if (LRofImpRef->hasColor())
         // this implicit reference is in a LR that received a color
@@ -1080,7 +1080,7 @@
 
   for (; HMI != HMIEnd ; ++HMI ) {
     if (HMI->first) {
-      LiveRange *L = HMI->second;      // get the LiveRange
+      V9LiveRange *L = HMI->second;      // get the V9LiveRange
       if (L && L->hasSuggestedColor ())
         L->setSuggestedColorUsable
           (!(MRI.isRegVolatile (L->getRegClassID (), L->getSuggestedColor ())
@@ -1102,7 +1102,7 @@
 
   for ( ; HMI != HMIEnd ; ++HMI) {
     if (HMI->first && HMI->second) {
-      LiveRange *L = HMI->second;       // get the LiveRange
+      V9LiveRange *L = HMI->second;       // get the V9LiveRange
       if (L->isMarkedForSpill()) {      // NOTE: allocating size of long Type **
         int stackOffset = MF->getInfo<SparcV9FunctionInfo>()->allocateSpilledValue(Type::LongTy);
         L->setSpillOffFromFP(stackOffset);
@@ -1122,7 +1122,7 @@
   AllocInfo::AllocStateTy AllocState = AllocInfo::NotAllocated;
   int Placement = -1;
   if ((HMI != HMIEnd) && HMI->second) {
-    LiveRange *L = HMI->second;
+    V9LiveRange *L = HMI->second;
     assert ((L->hasColor () || L->isMarkedForSpill ())
             && "Live range exists but not colored or spilled");
     if (L->hasColor ()) {


Index: llvm/lib/Target/SparcV9/RegAlloc/PhyRegAlloc.h
diff -u llvm/lib/Target/SparcV9/RegAlloc/PhyRegAlloc.h:1.70 llvm/lib/Target/SparcV9/RegAlloc/PhyRegAlloc.h:1.71
--- llvm/lib/Target/SparcV9/RegAlloc/PhyRegAlloc.h:1.70	Thu Apr 21 18:30:14 2005
+++ llvm/lib/Target/SparcV9/RegAlloc/PhyRegAlloc.h	Sun Jun 12 18:52:58 2005
@@ -139,7 +139,7 @@
   void markUnusableSugColors();
   void allocateStackSpace4SpilledLRs();
 
-  void insertCode4SpilledLR(const LiveRange *LR,
+  void insertCode4SpilledLR(const V9LiveRange *LR,
                             MachineBasicBlock::iterator& MII,
                             MachineBasicBlock &MBB, unsigned OpNum);
 


Index: llvm/lib/Target/SparcV9/RegAlloc/RegClass.cpp
diff -u llvm/lib/Target/SparcV9/RegAlloc/RegClass.cpp:1.32 llvm/lib/Target/SparcV9/RegAlloc/RegClass.cpp:1.33
--- llvm/lib/Target/SparcV9/RegAlloc/RegClass.cpp:1.32	Thu Apr 21 18:30:14 2005
+++ llvm/lib/Target/SparcV9/RegAlloc/RegClass.cpp	Sun Jun 12 18:52:58 2005
@@ -197,11 +197,11 @@
     clearColorsUsed();
 
     // initialize all colors used by neighbors of this node to true
-    LiveRange *LR = Node->getParentLR();
+    V9LiveRange *LR = Node->getParentLR();
     unsigned NumNeighbors =  Node->getNumOfNeighbors();
     for (unsigned n=0; n < NumNeighbors; n++) {
       IGNode *NeighIGNode = Node->getAdjIGNode(n);
-      LiveRange *NeighLR = NeighIGNode->getParentLR();
+      V9LiveRange *NeighLR = NeighIGNode->getParentLR();
 
       // Don't use a color if it is in use by the neighbor,
       // or is suggested for use by the neighbor,


Index: llvm/lib/Target/SparcV9/RegAlloc/RegClass.h
diff -u llvm/lib/Target/SparcV9/RegAlloc/RegClass.h:1.24 llvm/lib/Target/SparcV9/RegAlloc/RegClass.h:1.25
--- llvm/lib/Target/SparcV9/RegAlloc/RegClass.h:1.24	Thu Apr 21 18:30:14 2005
+++ llvm/lib/Target/SparcV9/RegAlloc/RegClass.h	Sun Jun 12 18:52:58 2005
@@ -109,19 +109,19 @@
   // --- following methods are provided to access the IG contained within this
   // ---- RegClass easilly.
 
-  inline void addLRToIG(LiveRange *const LR)
+  inline void addLRToIG(V9LiveRange *const LR)
     { IG.addLRToIG(LR); }
 
-  inline void setInterference(const LiveRange *const LR1,
-			      const LiveRange *const LR2)
+  inline void setInterference(const V9LiveRange *const LR1,
+			      const V9LiveRange *const LR2)
     { IG.setInterference(LR1, LR2); }
 
-  inline unsigned getInterference(const LiveRange *const LR1,
-			      const LiveRange *const LR2) const
+  inline unsigned getInterference(const V9LiveRange *const LR1,
+			      const V9LiveRange *const LR2) const
     { return IG.getInterference(LR1, LR2); }
 
-  inline void mergeIGNodesOfLRs(const LiveRange *const LR1,
-				LiveRange *const LR2)
+  inline void mergeIGNodesOfLRs(const V9LiveRange *const LR1,
+				V9LiveRange *const LR2)
     { IG.mergeIGNodesOfLRs(LR1, LR2); }