From reid at x10sys.com  Mon Jun 13 01:40:43 2005
From: reid at x10sys.com (Reid Spencer)
Date: Sun, 12 Jun 2005 23:40:43 -0700
Subject: [llvm-commits]  CVS:
	llvm/lib/Transforms/Scalar/InstructionCombining.cpp
In-Reply-To: <200506041244.HAA12176@zion.cs.uiuc.edu>
References: <200506041244.HAA12176@zion.cs.uiuc.edu>
Message-ID: <1118644843.13257.99.camel@bashful.x10sys.com>

Andrew,

This change has broken several of the InstCombine regression tests.
Without your changes, the regression tests all pass so I have reverted
your patch. Could you please find a workaround that doesn't break
InstCombine? In the future, please do "make check" and ensure that all
changes of this nature pass all the Feature and Regression tests (at a
minimum) before you commit them. 

Here's the regression test output:

FAIL: /proj/llvm/build/../llvm/test/Regression/Transforms/InstCombine/2004-11-27-SetCCForCastLargerAndConstant.ll:
        %Y = cast sbyte %SB to uint             ; <uint> [#uses=1]
        %Y = cast sbyte %SB to int              ; <int> [#uses=1]
        %Y = cast sbyte %SB to int              ; <int> [#uses=1]
        %Y = cast ubyte %SB to uint             ; <uint> [#uses=1]
        %Y = cast ubyte %SB to int              ; <int> [#uses=1]
        %Y = cast sbyte %SB to uint             ; <uint> [#uses=1]
        %Y = cast sbyte %SB to int              ; <int> [#uses=1]
        %Y = cast sbyte %SB to int              ; <int> [#uses=1]
        %Y = cast ubyte %SB to uint             ; <uint> [#uses=1]
        %Y = cast ubyte %SB to int              ; <int> [#uses=1]

FAIL: /proj/llvm/build/../llvm/test/Regression/Transforms/InstCombine/JavaCompare.ll:
        %c1 = setgt int %A, %B          ; <bool> [#uses=1]
        %tmp = cast bool %c1 to int             ; <int> [#uses=1]
        %c2 = setlt int %A, %B          ; <bool> [#uses=1]
        %c31 = setlt int %tmp, 1                ; <bool> [#uses=1]
        %c3 = or bool %c2, %c31         ; <bool> [#uses=1]

FAIL: /proj/llvm/build/../llvm/test/Regression/Transforms/InstCombine/cast-set.ll:
        %B = cast bool %A to int                ; <int> [#uses=1]

FAIL: /proj/llvm/build/../llvm/test/Regression/Transforms/InstCombine/cast.ll:
        %c = cast int %X to long                ; <long> [#uses=1]

FAIL: /proj/llvm/build/../llvm/test/Regression/Transforms/InstCombine/set.ll:
        %C = seteq int %a, %b           ; <bool> [#uses=1]

Reid.


On Sat, 2005-06-04 at 07:44 -0500, Andrew Lenharth wrote:
> 
> Changes in directory llvm/lib/Transforms/Scalar:
> 
> InstructionCombining.cpp updated: 1.345 -> 1.346
> ---
> Log message:
> 
> hack to fix bzip2 (bug 571: http://llvm.cs.uiuc.edu/PR571 )
> 
> ---
> Diffs of the changes:  (+2 -0)
> 
>  InstructionCombining.cpp |    2 ++
>  1 files changed, 2 insertions(+)
> 
> 
> Index: llvm/lib/Transforms/Scalar/InstructionCombining.cpp
> diff -u llvm/lib/Transforms/Scalar/InstructionCombining.cpp:1.345 llvm/lib/Transforms/Scalar/InstructionCombining.cpp:1.346
> --- llvm/lib/Transforms/Scalar/InstructionCombining.cpp:1.345	Sat May 14 07:25:32 2005
> +++ llvm/lib/Transforms/Scalar/InstructionCombining.cpp	Sat Jun  4 07:43:56 2005
> @@ -3088,6 +3088,8 @@
>      return 0;
>    }
>  
> +  return 0; //The rest of this function is broken.  See bug 571
> +
>    // Okay, we have the two reduced sized operands.  If we are doing a <,>
>    // comparison, make sure we perform the compare with the same signedness as
>    // the DestTy.  We don't have to do this if the comparison is !=/== or if the
> 
> 
> 
> _______________________________________________
> llvm-commits mailing list
> llvm-commits at cs.uiuc.edu
> http://mail.cs.uiuc.edu/mailman/listinfo/llvm-commits
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From reid at x10sys.com  Mon Jun 13 01:41:37 2005
From: reid at x10sys.com (Reid Spencer)
Date: Mon, 13 Jun 2005 01:41:37 -0500
Subject: [llvm-commits] 
	CVS: llvm/lib/Transforms/Scalar/InstructionCombining.cpp
Message-ID: <200506130641.BAA11792@zion.cs.uiuc.edu>



Changes in directory llvm/lib/Transforms/Scalar:

InstructionCombining.cpp updated: 1.346 -> 1.347
---
Log message:

Unbreak several InstCombine regression checks introduced by a hack to 
fix the bzip2 test. A better hack is needed.


---
Diffs of the changes:  (+0 -2)

 InstructionCombining.cpp |    2 --
 1 files changed, 2 deletions(-)


Index: llvm/lib/Transforms/Scalar/InstructionCombining.cpp
diff -u llvm/lib/Transforms/Scalar/InstructionCombining.cpp:1.346 llvm/lib/Transforms/Scalar/InstructionCombining.cpp:1.347
--- llvm/lib/Transforms/Scalar/InstructionCombining.cpp:1.346	Sat Jun  4 07:43:56 2005
+++ llvm/lib/Transforms/Scalar/InstructionCombining.cpp	Mon Jun 13 01:41:26 2005
@@ -3088,8 +3088,6 @@
     return 0;
   }
 
-  return 0; //The rest of this function is broken.  See bug 571
-
   // Okay, we have the two reduced sized operands.  If we are doing a <,>
   // comparison, make sure we perform the compare with the same signedness as
   // the DestTy.  We don't have to do this if the comparison is !=/== or if the





From natebegeman at mac.com  Mon Jun 13 22:55:35 2005
From: natebegeman at mac.com (Nate Begeman)
Date: Mon, 13 Jun 2005 22:55:35 -0500
Subject: [llvm-commits] CVS: llvm/lib/Target/PowerPC/PPC32ISelPattern.cpp 
Message-ID: <200506140355.WAA14105@zion.cs.uiuc.edu>



Changes in directory llvm/lib/Target/PowerPC:

PPC32ISelPattern.cpp updated: 1.92 -> 1.93
---
Log message:

Commit a small improvement that is already in the x86 and ia64 backends to
not generate unnecessary register copies.  This improves compile time by
2-5% depending on the test.


---
Diffs of the changes:  (+5 -0)

 PPC32ISelPattern.cpp |    5 +++++
 1 files changed, 5 insertions(+)


Index: llvm/lib/Target/PowerPC/PPC32ISelPattern.cpp
diff -u llvm/lib/Target/PowerPC/PPC32ISelPattern.cpp:1.92 llvm/lib/Target/PowerPC/PPC32ISelPattern.cpp:1.93
--- llvm/lib/Target/PowerPC/PPC32ISelPattern.cpp:1.92	Tue Jun  7 23:14:27 2005
+++ llvm/lib/Target/PowerPC/PPC32ISelPattern.cpp	Mon Jun 13 22:55:23 2005
@@ -1572,6 +1572,11 @@
   SDNode *Node = N.Val;
   MVT::ValueType DestType = N.getValueType();
 
+  if (Node->getOpcode() == ISD::CopyFromReg &&
+      MRegisterInfo::isVirtualRegister(cast<RegSDNode>(Node)->getReg()))
+    // Just use the specified register as our input.
+    return cast<RegSDNode>(Node)->getReg();
+
   unsigned &Reg = ExprMap[N];
   if (Reg) return Reg;
 





From duraid at octopus.com.au  Tue Jun 14 02:30:02 2005
From: duraid at octopus.com.au (Duraid Madina)
Date: Tue, 14 Jun 2005 02:30:02 -0500
Subject: [llvm-commits] CVS: llvm/docs/CFEBuildInstrs.html 
Message-ID: <200506140730.CAA15029@zion.cs.uiuc.edu>



Changes in directory llvm/docs:

CFEBuildInstrs.html updated: 1.51 -> 1.52
---
Log message:

nothing funny about building the CFE on Linux/Itanium



---
Diffs of the changes:  (+2 -1)

 CFEBuildInstrs.html |    3 ++-
 1 files changed, 2 insertions(+), 1 deletion(-)


Index: llvm/docs/CFEBuildInstrs.html
diff -u llvm/docs/CFEBuildInstrs.html:1.51 llvm/docs/CFEBuildInstrs.html:1.52
--- llvm/docs/CFEBuildInstrs.html:1.51	Wed May 18 14:43:24 2005
+++ llvm/docs/CFEBuildInstrs.html	Tue Jun 14 02:29:50 2005
@@ -146,6 +146,7 @@
 
 <p>
 <b>Linux/x86:</b><br>
+<b>Linux/IA-64:</b><br>
 <b>MacOS X/PowerPC</b> (requires dlcompat library):<br>
 <b>AIX/PowerPC:</b>
 </p>
@@ -354,7 +355,7 @@
 
   Brian Gaeke<br>
   <a href="http://llvm.cs.uiuc.edu">LLVM Compiler Infrastructure</a><br>
-  Last modified: $Date: 2005/05/18 19:43:24 $
+  Last modified: $Date: 2005/06/14 07:29:50 $
 </address>
 
 </body>





From criswell at cs.uiuc.edu  Tue Jun 14 13:48:09 2005
From: criswell at cs.uiuc.edu (John Criswell)
Date: Tue, 14 Jun 2005 13:48:09 -0500
Subject: [llvm-commits] CVS: llvm-gcc/gcc/llvm-expand.c 
Message-ID: <200506141848.NAA32260@choi.cs.uiuc.edu>



Changes in directory llvm-gcc/gcc:

llvm-expand.c updated: 1.98 -> 1.99
---
Log message:

Spelling correction.


---
Diffs of the changes:  (+1 -1)

 llvm-expand.c |    2 +-
 1 files changed, 1 insertion(+), 1 deletion(-)


Index: llvm-gcc/gcc/llvm-expand.c
diff -u llvm-gcc/gcc/llvm-expand.c:1.98 llvm-gcc/gcc/llvm-expand.c:1.99
--- llvm-gcc/gcc/llvm-expand.c:1.98	Tue May 10 17:33:16 2005
+++ llvm-gcc/gcc/llvm-expand.c	Tue Jun 14 13:47:51 2005
@@ -5158,7 +5158,7 @@
 
 /* llvm_expand_constant_expr - This function is responsible for translating a
  * constant tree expression into a suitable LLVM constant value.  This is
- * seperate from other expresion evaluation code because it is used to compute
+ * seperate from other expression evaluation code because it is used to compute
  * the initializers for global variables, which are required to be constants.
  *
  * ReqTy specifies the type that the result must be.  Note that this may be very





From criswell at cs.uiuc.edu  Tue Jun 14 16:41:13 2005
From: criswell at cs.uiuc.edu (John Criswell)
Date: Tue, 14 Jun 2005 16:41:13 -0500
Subject: [llvm-commits] CVS: llvm-gcc/gcc/llvm-expand.c 
Message-ID: <200506142141.QAA21269@choi.cs.uiuc.edu>



Changes in directory llvm-gcc/gcc:

llvm-expand.c updated: 1.99 -> 1.100
---
Log message:

Fixed another spelling error noticed by Reid.


---
Diffs of the changes:  (+1 -1)

 llvm-expand.c |    2 +-
 1 files changed, 1 insertion(+), 1 deletion(-)


Index: llvm-gcc/gcc/llvm-expand.c
diff -u llvm-gcc/gcc/llvm-expand.c:1.99 llvm-gcc/gcc/llvm-expand.c:1.100
--- llvm-gcc/gcc/llvm-expand.c:1.99	Tue Jun 14 13:47:51 2005
+++ llvm-gcc/gcc/llvm-expand.c	Tue Jun 14 16:40:55 2005
@@ -5158,7 +5158,7 @@
 
 /* llvm_expand_constant_expr - This function is responsible for translating a
  * constant tree expression into a suitable LLVM constant value.  This is
- * seperate from other expression evaluation code because it is used to compute
+ * separate from other expression evaluation code because it is used to compute
  * the initializers for global variables, which are required to be constants.
  *
  * ReqTy specifies the type that the result must be.  Note that this may be very





From natebegeman at mac.com  Wed Jun 15 13:22:55 2005
From: natebegeman at mac.com (Nate Begeman)
Date: Wed, 15 Jun 2005 13:22:55 -0500
Subject: [llvm-commits] CVS: llvm/lib/Target/PowerPC/PPC32ISelPattern.cpp 
Message-ID: <200506151822.NAA18629@zion.cs.uiuc.edu>



Changes in directory llvm/lib/Target/PowerPC:

PPC32ISelPattern.cpp updated: 1.93 -> 1.94
---
Log message:

Commit fix for generating conditional branch pseudo instructions that
avoids dereferencing the end() iterator when selecting the fallthrough 
block.  This requires an ilist change.


---
Diffs of the changes:  (+8 -3)

 PPC32ISelPattern.cpp |   11 ++++++++---
 1 files changed, 8 insertions(+), 3 deletions(-)


Index: llvm/lib/Target/PowerPC/PPC32ISelPattern.cpp
diff -u llvm/lib/Target/PowerPC/PPC32ISelPattern.cpp:1.93 llvm/lib/Target/PowerPC/PPC32ISelPattern.cpp:1.94
--- llvm/lib/Target/PowerPC/PPC32ISelPattern.cpp:1.93	Mon Jun 13 22:55:23 2005
+++ llvm/lib/Target/PowerPC/PPC32ISelPattern.cpp	Wed Jun 15 13:22:43 2005
@@ -1232,9 +1232,9 @@
   Select(N.getOperand(0));  //chain
   CCReg = SelectCC(N.getOperand(1), Opc, Inv, Idx);
 
-  // Iterate to the next basic block, unless we're already at the end of the
-  ilist<MachineBasicBlock>::iterator It = BB, E = BB->getParent()->end();
-  if (++It == E) It = BB;
+  // Iterate to the next basic block
+  ilist<MachineBasicBlock>::iterator It = BB;
+  ++It;
 
   // If this is a two way branch, then grab the fallthrough basic block argument
   // and build a PowerPC branch pseudo-op, suitable for long branch conversion
@@ -1256,6 +1256,11 @@
       }
     }
   } else {
+    // If the fallthrough path is off the end of the function, which would be
+    // undefined behavior, set it to be the same as the current block because
+    // we have nothing better to set it to, and leaving it alone will cause the
+    // PowerPC Branch Selection pass to crash.
+    if (It == BB->getParent()->end()) It = Dest;
     BuildMI(BB, PPC::COND_BRANCH, 4).addReg(CCReg).addImm(Opc)
       .addMBB(Dest).addMBB(It);
   }





From reid at x10sys.com  Wed Jun 15 13:25:41 2005
From: reid at x10sys.com (Reid Spencer)
Date: Wed, 15 Jun 2005 13:25:41 -0500
Subject: [llvm-commits] 
	CVS: llvm/lib/Transforms/Scalar/InstructionCombining.cpp
Message-ID: <200506151825.NAA18673@zion.cs.uiuc.edu>



Changes in directory llvm/lib/Transforms/Scalar:

InstructionCombining.cpp updated: 1.347 -> 1.348
---
Log message:

Put the hack back in that removes features, causes regressions to fail, but
allows test programs to succeed. Actual fix for this is forthcoming.


---
Diffs of the changes:  (+2 -0)

 InstructionCombining.cpp |    2 ++
 1 files changed, 2 insertions(+)


Index: llvm/lib/Transforms/Scalar/InstructionCombining.cpp
diff -u llvm/lib/Transforms/Scalar/InstructionCombining.cpp:1.347 llvm/lib/Transforms/Scalar/InstructionCombining.cpp:1.348
--- llvm/lib/Transforms/Scalar/InstructionCombining.cpp:1.347	Mon Jun 13 01:41:26 2005
+++ llvm/lib/Transforms/Scalar/InstructionCombining.cpp	Wed Jun 15 13:25:30 2005
@@ -3088,6 +3088,8 @@
     return 0;
   }
 
+  return 0; //The rest of this function is broken.  See bug 571
+
   // Okay, we have the two reduced sized operands.  If we are doing a <,>
   // comparison, make sure we perform the compare with the same signedness as
   // the DestTy.  We don't have to do this if the comparison is !=/== or if the





From natebegeman at mac.com  Wed Jun 15 13:28:55 2005
From: natebegeman at mac.com (Nate Begeman)
Date: Wed, 15 Jun 2005 13:28:55 -0500
Subject: [llvm-commits] CVS: llvm/include/llvm/ADT/ilist 
Message-ID: <200506151828.NAA18760@zion.cs.uiuc.edu>



Changes in directory llvm/include/llvm/ADT:

ilist updated: 1.25 -> 1.26
---
Log message:

Add some operators the PowerPC backend needs to efficiently and correctly
generate conditional branches.


---
Diffs of the changes:  (+20 -0)

 ilist |   20 ++++++++++++++++++++
 1 files changed, 20 insertions(+)


Index: llvm/include/llvm/ADT/ilist
diff -u llvm/include/llvm/ADT/ilist:1.25 llvm/include/llvm/ADT/ilist:1.26
--- llvm/include/llvm/ADT/ilist:1.25	Wed Mar 16 16:42:45 2005
+++ llvm/include/llvm/ADT/ilist	Wed Jun 15 13:28:44 2005
@@ -169,6 +169,26 @@
 template<typename T>
 void operator+(ilist_iterator<T>,int);
 
+// operator!=/operator== - Allow mixed comparisons without dereferencing
+// the iterator, which could very likely be pointing to end().
+template<typename T>
+bool operator!=(const T* LHS, const ilist_iterator<const T> &RHS) {
+  return LHS != RHS.getNodePtrUnchecked();
+}
+template<typename T>
+bool operator==(const T* LHS, const ilist_iterator<const T> &RHS) {
+  return LHS == RHS.getNodePtrUnchecked();
+}
+template<typename T>
+bool operator!=(T* LHS, const ilist_iterator<T> &RHS) {
+  return LHS != RHS.getNodePtrUnchecked();
+}
+template<typename T>
+bool operator==(T* LHS, const ilist_iterator<T> &RHS) {
+  return LHS == RHS.getNodePtrUnchecked();
+}
+
+
 // Allow ilist_iterators to convert into pointers to a node automatically when
 // used by the dyn_cast, cast, isa mechanisms...
 





From reid at x10sys.com  Wed Jun 15 13:40:56 2005
From: reid at x10sys.com (Reid Spencer)
Date: Wed, 15 Jun 2005 13:40:56 -0500
Subject: [llvm-commits] CVS: llvm/include/llvm/Support/Annotation.h 
Message-ID: <200506151840.NAA19037@zion.cs.uiuc.edu>



Changes in directory llvm/include/llvm/Support:

Annotation.h updated: 1.19 -> 1.20
---
Log message:

Don't lie to the casual reader about Value subclassing from Annotable.


---
Diffs of the changes:  (+1 -2)

 Annotation.h |    3 +--
 1 files changed, 1 insertion(+), 2 deletions(-)


Index: llvm/include/llvm/Support/Annotation.h
diff -u llvm/include/llvm/Support/Annotation.h:1.19 llvm/include/llvm/Support/Annotation.h:1.20
--- llvm/include/llvm/Support/Annotation.h:1.19	Thu Apr 21 22:35:49 2005
+++ llvm/include/llvm/Support/Annotation.h	Wed Jun 15 13:40:45 2005
@@ -81,8 +81,7 @@
 //===----------------------------------------------------------------------===//
 //
 // Annotable - This class is used as a base class for all objects that would
-// like to have annotation capability.  One notable subclass is Value, which
-// means annotations can be attached to almost everything in LLVM.
+// like to have annotation capability.  
 //
 // Annotable objects keep their annotation list sorted as annotations are
 // inserted and deleted.  This is used to ensure that annotations with identical





From lattner at cs.uiuc.edu  Wed Jun 15 14:01:21 2005
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Wed, 15 Jun 2005 14:01:21 -0500
Subject: [llvm-commits] 
	CVS: llvm-www/pubs/2005-06-13-PLDI-PoolAllocSlides.pdf
	2005-06-13-PLDI-PoolAllocSlides.ppt 2005-05-21-PLDI-PoolAlloc.html 
Message-ID: <200506151901.OAA19362@zion.cs.uiuc.edu>



Changes in directory llvm-www/pubs:

2005-06-13-PLDI-PoolAllocSlides.pdf added (r1.1)
2005-06-13-PLDI-PoolAllocSlides.ppt added (r1.1)
2005-05-21-PLDI-PoolAlloc.html updated: 1.2 -> 1.3
---
Log message:

Add pool allocation slides


---
Diffs of the changes:  (+21 -1)

 2005-05-21-PLDI-PoolAlloc.html      |   22 +++++++++++++++++++++-
 2005-06-13-PLDI-PoolAllocSlides.pdf |    0 
 2005-06-13-PLDI-PoolAllocSlides.ppt |    0 
 3 files changed, 21 insertions(+), 1 deletion(-)


Index: llvm-www/pubs/2005-06-13-PLDI-PoolAllocSlides.pdf


Index: llvm-www/pubs/2005-06-13-PLDI-PoolAllocSlides.ppt


Index: llvm-www/pubs/2005-05-21-PLDI-PoolAlloc.html
diff -u llvm-www/pubs/2005-05-21-PLDI-PoolAlloc.html:1.2 llvm-www/pubs/2005-05-21-PLDI-PoolAlloc.html:1.3
--- llvm-www/pubs/2005-05-21-PLDI-PoolAlloc.html:1.2	Wed Apr 20 23:58:46 2005
+++ llvm-www/pubs/2005-05-21-PLDI-PoolAlloc.html	Wed Jun 15 14:01:08 2005
@@ -44,12 +44,15 @@
 <blockquote>
   "Automatic Pool Allocation: Improving Performance by Controlling Data 
   Structure Layout in the Heap"<br>
-  Chris Lattner and Vikram Adve.
+  Chris Lattner and Vikram Adve.<br>
   Proc. of the 2005 ACM SIGPLAN Conference on Programming Language 
   Design and Implementation (PLDI'05), Chicago, Illinois, Jun, 2005.
 </blockquote>
 
+  <p><b>Awarded PLDI 2005 Best Paper Award</b></p>
+
 <h2>Download:</h2>
+<h3>Paper:</h3>
 <ul>
   <li><a href="2005-05-21-PLDI-PoolAlloc.ps">Automatic Pool Allocation: 
       Improving Performance by Controlling Data Structure Layout in the 
@@ -58,6 +61,23 @@
       Improving Performance by Controlling Data Structure Layout in the 
       Heap</a> (PDF)</li>
 </ul>
+<h3>Slides:</h3>
+<ul>
+  <p>Note, animations do not work in PDF version.  Please use PPT version if
+     possible.</p>
+  <li><a href="2005-06-13-PLDI-PoolAllocSlides.ppt">Automatic Pool Allocation: 
+      Improving Performance by Controlling Data Structure Layout in the 
+      Heap - Slides</a> (PPT)</li>
+  <li><a href="2005-06-13-PLDI-PoolAllocSlides.pdt">Automatic Pool Allocation: 
+      Improving Performance by Controlling Data Structure Layout in the 
+      Heap - Slides</a> (PDF)</li>
+</ul>
+
+<h2>Update:</h2>
+
+<p>A more recent and expanded version of this work is available in <a 
+href="2005-05-04-LattnerPHDThesis.html">Chris Lattner's Ph.D. Thesis</a>.
+</p>
 
 <h2>BibTeX Entry:</h2>
 <pre>





From lattner at cs.uiuc.edu  Wed Jun 15 14:01:59 2005
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Wed, 15 Jun 2005 14:01:59 -0500
Subject: [llvm-commits] CVS: llvm-www/pubs/2005-05-21-PLDI-PoolAlloc.html 
Message-ID: <200506151901.OAA19390@zion.cs.uiuc.edu>



Changes in directory llvm-www/pubs:

2005-05-21-PLDI-PoolAlloc.html updated: 1.3 -> 1.4
---
Log message:

fix typo


---
Diffs of the changes:  (+1 -1)

 2005-05-21-PLDI-PoolAlloc.html |    2 +-
 1 files changed, 1 insertion(+), 1 deletion(-)


Index: llvm-www/pubs/2005-05-21-PLDI-PoolAlloc.html
diff -u llvm-www/pubs/2005-05-21-PLDI-PoolAlloc.html:1.3 llvm-www/pubs/2005-05-21-PLDI-PoolAlloc.html:1.4
--- llvm-www/pubs/2005-05-21-PLDI-PoolAlloc.html:1.3	Wed Jun 15 14:01:08 2005
+++ llvm-www/pubs/2005-05-21-PLDI-PoolAlloc.html	Wed Jun 15 14:01:48 2005
@@ -68,7 +68,7 @@
   <li><a href="2005-06-13-PLDI-PoolAllocSlides.ppt">Automatic Pool Allocation: 
       Improving Performance by Controlling Data Structure Layout in the 
       Heap - Slides</a> (PPT)</li>
-  <li><a href="2005-06-13-PLDI-PoolAllocSlides.pdt">Automatic Pool Allocation: 
+  <li><a href="2005-06-13-PLDI-PoolAllocSlides.pdf">Automatic Pool Allocation: 
       Improving Performance by Controlling Data Structure Layout in the 
       Heap - Slides</a> (PDF)</li>
 </ul>





From lattner at cs.uiuc.edu  Wed Jun 15 14:18:42 2005
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Wed, 15 Jun 2005 14:18:42 -0500
Subject: [llvm-commits] CVS: llvm-www/pubs/2005-06-12-MSP-PointerComp.html
	2005-06-12-MSP-PointerComp.pdf 2005-06-12-MSP-PointerComp.ps
	2005-06-12-MSP-PointerCompSlides.pdf
	2005-06-12-MSP-PointerCompSlides.ppt index.html 
Message-ID: <200506151918.OAA19958@zion.cs.uiuc.edu>



Changes in directory llvm-www/pubs:

2005-06-12-MSP-PointerComp.html added (r1.1)
2005-06-12-MSP-PointerComp.pdf added (r1.1)
2005-06-12-MSP-PointerComp.ps added (r1.1)
2005-06-12-MSP-PointerCompSlides.pdf added (r1.1)
2005-06-12-MSP-PointerCompSlides.ppt added (r1.1)
index.html updated: 1.19 -> 1.20
---
Log message:

Add pointer compression paper


---
Diffs of the changes:  (+54751 -1)

 2005-06-12-MSP-PointerComp.html      |   87 
 2005-06-12-MSP-PointerComp.pdf       |    0 
 2005-06-12-MSP-PointerComp.ps        |54655 +++++++++++++++++++++++++++++++++++
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 2005-06-12-MSP-PointerCompSlides.ppt |    0 
 index.html                           |   10 
 6 files changed, 54751 insertions(+), 1 deletion(-)


Index: llvm-www/pubs/2005-06-12-MSP-PointerComp.html
diff -c /dev/null llvm-www/pubs/2005-06-12-MSP-PointerComp.html:1.1
*** /dev/null	Wed Jun 15 14:18:41 2005
--- llvm-www/pubs/2005-06-12-MSP-PointerComp.html	Wed Jun 15 14:18:31 2005
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*** 0 ****
--- 1,87 ----
+ <!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+ <html>
+ <head>
+   <meta http-equiv="Content-Type" content="text/html; charset=UTF-8">
+   <link rel="stylesheet" href="../llvm.css" type="text/css" media="screen">
+   <title>Transparent Pointer Compression for Linked Data Structures</title>
+ </head>
+ <body>
+ 
+ <div class="pub_title">
+   Transparent Pointer Compression for Linked Data Structures
+ </div>
+ <div class="pub_author">
+   <a href="http://www.nondot.org/sabre/">Chris Lattner</a> and
+   <a href="http://www.cs.uiuc.edu/~vadve">Vikram Adve</a>
+ </div>
+ 
+ <h2>Abstract:</h2>
+ <blockquote>
+ 64-bit address spaces are increasingly important for modern
+ applications, but they come at a price: pointers use twice
+ as much memory, reducing the effective cache capacity and memory
+ bandwidth of the system (compared to 32-bit address spaces). This paper 
+ presents a sophisticated,
+ automatic transformation that shrinks pointers from 64-bits
+ to 32-bits (and potentially less).  The approach is macroscopic, i.e., it
+ operates on an entire logical data structure in the program at a time.  It
+ allows an <i>individual</i> data structure instance or even a subset thereof
+ to grow up to 2<sup>32</sup> bytes in size.  Furthermore, the transformation can
+ choose to compress some data structures in a program but not others (e.g. if
+ only part of the program is type-safe).  We also describe (but have not
+ implemented) a dynamic version of the technique that can transparently expand
+ the pointers in an individual data structure if it exceeds the 4GB limit.
+ For a collection of pointer-intensive benchmarks, we show that the
+ transformation improves performance substantially (20% to 2x) for several of
+ these benchmarks, and also reduces peak heap size by a similar factor.
+ </blockquote>
+ 
+ <h2>Published:</h2>
+ <blockquote>
+   "Transparent Pointer Compression for Linked Data Structures"<br>
+   Chris Lattner and Vikram Adve.<br>
+   Proceedings of the ACM Workshop on Memory System Performance (MSP'05),
+   Chicago, Illinois, June, 2005.
+ </blockquote>
+ 
+ <h2>Download:</h2>
+ <h3>Paper:</h3>
+ <ul>
+   <li><a href="2005-06-12-MSP-PointerComp.ps">Transparent Pointer Compression for Linked Data Structures</a> (PS)</li>
+   <li><a href="2005-06-12-MSP-PointerComp.pdf">Transparent Pointer Compression for Linked Data Structures</a> (PDF)</li>
+ </ul>
+ <h3>Slides:</h3>
+   <p>Note, animations do not work in PDF version.  Please use PPT version if
+      possible.</p>
+ <ul>
+   <li><a href="2005-06-12-MSP-PointerCompSlides.ppt">Transparent Pointer Compression for Linked Data Structures - Slides</a> (PPT)</li>
+   <li><a href="2005-06-12-MSP-PointerCompSlides.pdf">Transparent Pointer Compression for Linked Data Structures - Slides</a> (PDF)</li>
+ </ul>
+ 
+ <h2>Update:</h2>
+ 
+ <p>The full context for this work is available in <a 
+ href="2005-05-04-LattnerPHDThesis.html">Chris Lattner's Ph.D. Thesis</a>.
+ </p>
+ 
+ <h2>BibTeX Entry:</h2>
+ <pre>
+   @InProceedings{PointerComp:MSP05,
+     author    = {Chris Lattner and Vikram Adve},
+     title     = "{Transparent Pointer Compression for Linked Data Structures}",
+     booktitle = "{Proceedings of the ACM Workshop on Memory System Performance (MSP'05)}",
+     address   = {Chigago, Illinois},
+     month     = {June},
+     year      = {2005}
+   }
+ </pre>
+ 
+ <!-- *********************************************************************** -->
+ <hr>
+   <a href="http://jigsaw.w3.org/css-validator/check/referer"><img
+   src="http://jigsaw.w3.org/css-validator/images/vcss" alt="Valid CSS!"></a>
+   <a href="http://validator.w3.org/check/referer"><img
+   src="http://www.w3.org/Icons/valid-html401" alt="Valid HTML 4.01!" /></a>
+ 
+ </body>
+ </html>


Index: llvm-www/pubs/2005-06-12-MSP-PointerComp.pdf


Index: llvm-www/pubs/2005-06-12-MSP-PointerComp.ps
diff -c /dev/null llvm-www/pubs/2005-06-12-MSP-PointerComp.ps:1.1
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+ /radius r1 def
+ newpath
+ xInc 0 eq yInc 0 eq rInc 0 eq and and
+ {
+ 0 getrampcolor
+ cx cy radius 0 360 arc
+ stroke
+ NumSamples 1 sub getrampcolor
+ cx cy radius 72 hires div add 0 360 arc
+ 0 setlinewidth
+ stroke
+ }
+ {
+ 0
+ numsteps
+ {
+ dup
+ subsampling { round cvi } if
+ getrampcolor
+ cx cy radius 0 360 arc
+ /cx cx xInc add def
+ /cy cy yInc add def
+ /radius radius rInc add def
+ cx cy radius 360 0 arcn
+ eofill
+ rampIndxInc add
+ }
+ repeat
+ pop
+ } ifelse
+ ext1 {
+ c2y r2 add r1 lt
+ {
+ c2x c2y r2 0 360 arc
+ fill
+ }
+ {
+ c2y r1 add r2 le
+ {
+ c2x c2y r2 360 0 arcn
+ xMin yMin moveto
+ xMax yMin lineto
+ xMax yMax lineto
+ xMin yMax lineto
+ xMin yMin lineto
+ eofill
+ }
+ {
+ c2x c2y r2 0 360 arc fill
+ r1 r2 eq
+ {
+ /p1x r2 neg def
+ /p1y c2y def
+ /p2x r2 def
+ /p2y c2y def
+ p1x p1y moveto p2x p2y lineto p2x yMax lineto p1x yMax lineto
+ fill
+ }
+ {
+ /AA r2 r1 sub c2y div def
+ /theta AA 1 AA dup mul sub sqrt div 1 atan def
+ /SS1 90 theta add dup sin exch cos div def
+ /p1x r2 SS1 SS1 mul SS1 SS1 mul 1 add div sqrt mul neg def
+ /p1y c2y p1x SS1 div sub def
+ /SS2 90 theta sub dup sin exch cos div def
+ /p2x r2 SS2 SS2 mul SS2 SS2 mul 1 add div sqrt mul def
+ /p2y c2y p2x SS2 div sub def
+ r1 r2 lt
+ {
+ /L1maxX p1x yMax p1y sub SS1 div add def
+ /L2maxX p2x yMax p2y sub SS2 div add def
+ }
+ {
+ /L1maxX 0 def
+ /L2maxX 0 def
+ }ifelse
+ p1x p1y moveto p2x p2y lineto L2maxX L2maxX p2x sub SS2 mul p2y add lineto
+ L1maxX L1maxX p1x sub SS1 mul p1y add lineto
+ fill
+ }
+ ifelse
+ }
+ ifelse
+ } ifelse
+ } if
+ grestore
+ grestore
+ end
+ end
+ end
+ } ifelse
+ } bd
+ /GenStrips {
+ 40 dict begin
+ /background exch def
+ /ext1 exch def
+ /ext0 exch def
+ /BBox exch def
+ /y2 exch def
+ /x2 exch def
+ /y1 exch def
+ /x1 exch def
+ /rampdict exch def
+ gsave
+ BBox length 0 gt {
+ newpath
+ BBox 0 get BBox 1 get moveto
+ BBox 2 get BBox 0 get sub 0 rlineto
+ 0 BBox 3 get BBox 1 get sub rlineto
+ BBox 2 get BBox 0 get sub neg 0 rlineto
+ closepath
+ clip
+ newpath
+ } if
+ x1 x2 eq
+ {
+ y1 y2 lt {/theta 90 def}{/theta 270 def} ifelse
+ }
+ {
+ /slope y2 y1 sub x2 x1 sub div def
+ /theta slope 1 atan def
+ x2 x1 lt y2 y1 ge and { /theta theta 180 sub def} if
+ x2 x1 lt y2 y1 lt and { /theta theta 180 add def} if
+ }
+ ifelse
+ gsave
+ clippath
+ x1 y1 translate
+ theta rotate
+ { pathbbox } stopped
+ { 0 0 0 0 } if
+ /yMax exch def
+ /xMax exch def
+ /yMin exch def
+ /xMin exch def
+ grestore
+ xMax xMin eq yMax yMin eq or
+ {
+ grestore
+ end
+ }
+ {
+ rampdict begin
+ 20 dict begin
+ background length 0 gt { background sssetbackground gsave clippath fill grestore } if
+ gsave
+ x1 y1 translate
+ theta rotate
+ /xStart 0 def
+ /xEnd x2 x1 sub dup mul y2 y1 sub dup mul add 0.5 exp def
+ /ySpan yMax yMin sub def
+ /numsteps NumSamples def
+ /rampIndxInc 1 def
+ /subsampling false def
+ xStart 0 transform
+ xEnd 0 transform
+ 3 -1 roll
+ sub dup mul
+ 3 1 roll
+ sub dup mul
+ add 0.5 exp 72 div
+ 0 72 matrix defaultmatrix dtransform dup mul exch dup mul add sqrt
+ 72 0 matrix defaultmatrix dtransform dup mul exch dup mul add sqrt
+ 1 index 1 index lt { exch } if pop
+ mul
+ /numpix exch def
+ numpix 0 ne
+ {
+ NumSamples numpix div 0.5 gt
+ {
+ /numsteps numpix 2 div round cvi dup 1 le { pop 2 } if def
+ /rampIndxInc NumSamples 1 sub numsteps div def
+ /subsampling true def
+ } if
+ } if
+ ext0 {
+ 0 getrampcolor
+ xMin xStart lt
+ { xMin yMin xMin neg ySpan rectfill } if
+ } if
+ /xInc xEnd xStart sub numsteps div def
+ /x xStart def
+ 0
+ numsteps
+ {
+ dup
+ subsampling { round cvi } if
+ getrampcolor
+ x yMin xInc ySpan rectfill
+ /x x xInc add def
+ rampIndxInc add
+ }
+ repeat
+ pop
+ ext1 {
+ xMax xEnd gt
+ { xEnd yMin xMax xEnd sub ySpan rectfill } if
+ } if
+ grestore
+ grestore
+ end
+ end
+ end
+ } ifelse
+ } bd
+ %%EndResource
+ %%BeginResource: procset pdflev2
+ %%Version: 5.0 15
+ %%Copyright: Copyright 1987-2001 Adobe Systems Incorporated. All Rights Reserved.
+ %%LanguageLevel: 2
+ %%Title: PDF operators, with code specific for Level 2
+ /docinitialize {
+ PDF begin
+ /_defaulthalftone currenthalftone dd
+ /_defaultblackgeneration currentblackgeneration dd
+ /_defaultundercolorremoval currentundercolorremoval dd
+ /_defaultcolortransfer [currentcolortransfer] dd
+ /_defaulttransfer currenttransfer dd
+ end
+ PDFVars /docSetupDone true put
+ } bd
+ /initialize {
+ PDFVars /docSetupDone get {
+ _defaulthalftone sethalftone
+ /_defaultblackgeneration load setblackgeneration
+ /_defaultundercolorremoval load setundercolorremoval
+ _defaultcolortransfer aload pop setcolortransfer
+ } if
+ false setoverprint
+ } bd
+ /terminate { } bd
+ /c /curveto ld
+ /cs /setcolorspace ld
+ /l /lineto ld
+ /m /moveto ld
+ /q /gsave ld
+ /Q /grestore ld
+ /sc /setcolor ld
+ /setSA/setstrokeadjust ld
+ /re {
+ 4 2 roll m
+ 1 index 0 rlineto
+ 0 exch rlineto
+ neg 0 rlineto
+ h
+ } bd
+ /concattransferfuncs {
+ [ 3 1 roll /exec load exch /exec load ] cvx
+ } bd
+ /concatandsettransfer {
+ /_defaulttransfer load concattransferfuncs settransfer
+ } bd
+ /concatandsetcolortransfer {
+ _defaultcolortransfer aload pop
+ 8 -1 roll 5 -1 roll concattransferfuncs 7 1 roll
+ 6 -1 roll 4 -1 roll concattransferfuncs 5 1 roll
+ 4 -1 roll 3 -1 roll concattransferfuncs 3 1 roll
+ concattransferfuncs
+ setcolortransfer
+ } bd
+ /defineRes/defineresource ld
+ /findRes/findresource ld
+ currentglobal
+ true systemdict /setglobal get exec
+ [/Function /ExtGState /Form /Shading /FunctionDictionary /MadePattern /PatternPrototype /DataSource /Image]
+ { /Generic /Category findresource dup length dict copy /Category defineresource pop }
+ forall
+ systemdict /setglobal get exec
+ /ri
+ {
+ /findcolorrendering isdefined?
+ {
+ mark exch
+ findcolorrendering
+ counttomark 2 eq
+ { type /booleantype eq
+ { dup type /nametype eq
+ { dup /ColorRendering resourcestatus
+ { pop pop
+ dup /DefaultColorRendering ne
+ {
+ /ColorRendering findresource
+ setcolorrendering
+ } if
+ } if
+ } if
+ } if
+ } if
+ cleartomark
+ }
+ { pop
+ } ifelse
+ } bd
+ /knownColorants? {
+ pop false
+ } bd
+ /getrampcolor {
+ /indx exch def
+ 0 1 NumComp 1 sub {
+ dup
+ Samples exch get
+ dup type /stringtype eq { indx get } if
+ exch
+ Scaling exch get aload pop
+ 3 1 roll
+ mul add
+ } for
+ setcolor
+ } bd
+ /sssetbackground { aload pop setcolor } bd
+ %%EndResource
+ %%BeginResource: procset pdftext
+ %%Version: 5.0 6
+ %%Copyright: Copyright 1987-2001 Adobe Systems Incorporated. All Rights Reserved.
+ %%Title: Text operators for PDF
+ PDF /PDFText 78 dict dup begin put
+ /docinitialize
+ {
+ /resourcestatus where {
+ pop
+ /CIDParams /ProcSet resourcestatus {
+ pop pop
+ false /CIDParams /ProcSet findresource /SetBuildCompatible get exec
+ } if
+ } if
+ PDF begin
+ PDFText /_pdfDefineIdentity-H known
+ { PDFText /_pdfDefineIdentity-H get exec}
+ if
+ end
+ } bd
+ /initialize {
+ PDFText begin
+ } bd
+ /terminate { end } bd
+ Level2?
+ {
+ /_safeput
+ {
+ 3 -1 roll load 3 1 roll put
+ }
+ bd
+ }
+ {
+ /_safeput
+ {
+ 2 index load dup dup length exch maxlength ge
+ { dup length 5 add dict copy
+ 3 index xdd
+ }
+ { pop }
+ ifelse
+ 3 -1 roll load 3 1 roll put
+ }
+ bd
+ }
+ ifelse
+ /pdf_has_composefont? systemdict /composefont known def
+ /CopyFont {
+ {
+ 1 index /FID ne 2 index /UniqueID ne and
+ { def } { pop pop } ifelse
+ } forall
+ } bd
+ /Type0CopyFont
+ {
+ exch
+ dup length dict
+ begin
+ CopyFont
+ [
+ exch
+ FDepVector
+ {
+ dup /FontType get 0 eq
+ {
+ 1 index Type0CopyFont
+ /_pdfType0 exch definefont
+ }
+ {
+ /_pdfBaseFont exch
+ 2 index exec
+ }
+ ifelse
+ exch
+ }
+ forall
+ pop
+ ]
+ /FDepVector exch def
+ currentdict
+ end
+ } bd
+ Level2? {currentglobal true setglobal} if
+ /cHexEncoding
+ [/c00/c01/c02/c03/c04/c05/c06/c07/c08/c09/c0A/c0B/c0C/c0D/c0E/c0F/c10/c11/c12
+ /c13/c14/c15/c16/c17/c18/c19/c1A/c1B/c1C/c1D/c1E/c1F/c20/c21/c22/c23/c24/c25
+ /c26/c27/c28/c29/c2A/c2B/c2C/c2D/c2E/c2F/c30/c31/c32/c33/c34/c35/c36/c37/c38
+ /c39/c3A/c3B/c3C/c3D/c3E/c3F/c40/c41/c42/c43/c44/c45/c46/c47/c48/c49/c4A/c4B
+ /c4C/c4D/c4E/c4F/c50/c51/c52/c53/c54/c55/c56/c57/c58/c59/c5A/c5B/c5C/c5D/c5E
+ /c5F/c60/c61/c62/c63/c64/c65/c66/c67/c68/c69/c6A/c6B/c6C/c6D/c6E/c6F/c70/c71
+ /c72/c73/c74/c75/c76/c77/c78/c79/c7A/c7B/c7C/c7D/c7E/c7F/c80/c81/c82/c83/c84
+ /c85/c86/c87/c88/c89/c8A/c8B/c8C/c8D/c8E/c8F/c90/c91/c92/c93/c94/c95/c96/c97
+ /c98/c99/c9A/c9B/c9C/c9D/c9E/c9F/cA0/cA1/cA2/cA3/cA4/cA5/cA6/cA7/cA8/cA9/cAA
+ /cAB/cAC/cAD/cAE/cAF/cB0/cB1/cB2/cB3/cB4/cB5/cB6/cB7/cB8/cB9/cBA/cBB/cBC/cBD
+ /cBE/cBF/cC0/cC1/cC2/cC3/cC4/cC5/cC6/cC7/cC8/cC9/cCA/cCB/cCC/cCD/cCE/cCF/cD0
+ /cD1/cD2/cD3/cD4/cD5/cD6/cD7/cD8/cD9/cDA/cDB/cDC/cDD/cDE/cDF/cE0/cE1/cE2/cE3
+ /cE4/cE5/cE6/cE7/cE8/cE9/cEA/cEB/cEC/cED/cEE/cEF/cF0/cF1/cF2/cF3/cF4/cF5/cF6
+ /cF7/cF8/cF9/cFA/cFB/cFC/cFD/cFE/cFF] def
+ Level2? {setglobal} if
+ /modEnc {
+ /_enc xdd
+ /_icode 0 dd
+ counttomark 1 sub -1 0
+ {
+ index
+ dup type /nametype eq
+ {
+ _enc _icode 3 -1 roll put
+ _icode 1 add
+ }
+ if
+ /_icode xdd
+ } for
+ cleartomark
+ _enc
+ } bd
+ /trEnc {
+ /_enc xdd
+ 255 -1 0 {
+ exch dup -1 eq
+ { pop /.notdef }
+ { Encoding exch get }
+ ifelse
+ _enc 3 1 roll put
+ } for
+ pop
+ _enc
+ } bd
+ /TE {
+ /_i xdd
+ StandardEncoding 256 array copy modEnc
+ _pdfEncodings exch _i exch put
+ } bd
+ /TZ
+ {
+ /_usePDFEncoding xdd
+ findfont
+ dup length 6 add dict
+ begin
+ {
+ 1 index /FID ne { def } { pop pop } ifelse
+ } forall
+ /pdf_origFontName FontName def
+ /FontName exch def
+ currentdict /PaintType known
+ { PaintType 2 eq {/PaintType 0 def} if }
+ if
+ _usePDFEncoding 0 ge
+ {
+ /Encoding _pdfEncodings _usePDFEncoding get def
+ pop
+ }
+ {
+ _usePDFEncoding -1 eq
+ {
+ counttomark 0 eq
+ { pop }
+ {
+ Encoding 256 array copy
+ modEnc /Encoding exch def
+ }
+ ifelse
+ }
+ {
+ 256 array
+ trEnc /Encoding exch def
+ }
+ ifelse
+ }
+ ifelse
+ pdf_EuroProcSet pdf_origFontName known
+ {
+ pdf_origFontName pdf_AddEuroGlyphProc
+ } if
+ Level2?
+ {
+ currentdict /pdf_origFontName undef
+ } if
+ FontName currentdict
+ end
+ definefont pop
+ }
+ bd
+ Level2?
+ {
+ /TZG
+ {
+ currentglobal true setglobal
+ 2 index _pdfFontStatus
+ {
+ 2 index findfont
+ false setglobal
+ 3 index findfont
+ true setglobal
+ ne
+ {
+ 2 index findfont dup rcheck
+ {
+ dup length dict begin
+ {
+ 1 index /FID ne { def } { pop pop } ifelse
+ } forall
+ currentdict end
+ }
+ if
+ 3 index exch definefont pop
+ }
+ if
+ } if
+ setglobal
+ TZ
+ } bd
+ }
+ {
+ /TZG {TZ} bd
+ } ifelse
+ Level2?
+ {
+ currentglobal false setglobal
+ userdict /pdftext_data 5 dict put
+ pdftext_data
+ begin
+ /saveStacks
+ {
+ pdftext_data
+ begin
+ /vmmode currentglobal def
+ false setglobal
+ count array astore /os exch def
+ end
+ countdictstack array dictstack pdftext_data exch /ds exch put
+ cleardictstack pdftext_data /dscount countdictstack put
+ pdftext_data /vmmode get setglobal
+ } bind def
+ /restoreStacks
+ {
+ pdftext_data /vmmode currentglobal put false setglobal
+ clear cleardictstack
+ pdftext_data /ds get dup
+ pdftext_data /dscount get 1 2 index length 1 sub
+ { get begin dup } for
+ pop pop
+ pdftext_data /os get aload pop
+ pdftext_data /vmmode get setglobal
+ } bind def
+ /testForClonePrinterBug
+ {
+ currentglobal true setglobal
+ /undefinedCategory /Generic /Category findresource
+ dup length dict copy /Category defineresource pop
+ setglobal
+ pdftext_data /saveStacks get exec
+ pdftext_data /vmmode currentglobal put false setglobal
+ /undefined /undefinedCategory { resourcestatus } stopped
+ pdftext_data exch /bugFound exch put
+ pdftext_data /vmmode get setglobal
+ pdftext_data /restoreStacks get exec
+ pdftext_data /bugFound get
+ } bind def
+ end
+ setglobal
+ /pdf_resourcestatus
+ pdftext_data /testForClonePrinterBug get exec
+ {
+ {
+ pdftext_data /saveStacks get exec
+ pdftext_data /os get dup dup length 1 sub
+ dup 1 sub dup 0 lt { pop 0 } if
+ exch 1 exch { get exch dup } for
+ pop pop
+ { resourcestatus }
+ stopped
+ {
+ clear cleardictstack pdftext_data /restoreStacks get exec
+ { pop pop } stopped pop false
+ }
+ {
+ count array astore pdftext_data exch /results exch put
+ pdftext_data /restoreStacks get exec pop pop
+ pdftext_data /results get aload pop
+ }
+ ifelse
+ }
+ }
+ { { resourcestatus } }
+ ifelse
+ bd
+ }
+ if
+ Level2?
+ {
+ /_pdfUndefineResource
+ {
+ currentglobal 3 1 roll
+ _pdf_FontDirectory 2 index 2 copy known
+ {undef}
+ {pop pop}
+ ifelse
+ 1 index (pdf) exch _pdfConcatNames 1 index
+ 1 index 1 _pdfConcatNames 1 index
+ 5 index 1 _pdfConcatNames 1 index
+ 4
+ {
+ 2 copy pdf_resourcestatus
+ {
+ pop 2 lt
+ {2 copy findresource gcheck setglobal undefineresource}
+ {pop pop}
+ ifelse
+ }
+ { pop pop}
+ ifelse
+ } repeat
+ setglobal
+ } bd
+ }
+ {
+ /_pdfUndefineResource { pop pop} bd
+ }
+ ifelse
+ Level2?
+ {
+ /_pdfFontStatus
+ {
+ currentglobal exch
+ /Font pdf_resourcestatus
+ {pop pop true}
+ {false}
+ ifelse
+ exch setglobal
+ } bd
+ }
+ {
+ /_pdfFontStatusString 50 string def
+ _pdfFontStatusString 0 (fonts/) putinterval
+ /_pdfFontStatus
+ {
+ FontDirectory 1 index known
+ { pop true }
+ {
+ _pdfFontStatusString 6 42 getinterval
+ cvs length 6 add
+ _pdfFontStatusString exch 0 exch getinterval
+ { status } stopped
+ {pop false}
+ {
+ { pop pop pop pop true}
+ { false }
+ ifelse
+ }
+ ifelse
+ }
+ ifelse
+ } bd
+ }
+ ifelse
+ Level2?
+ {
+ /_pdfCIDFontStatus
+ {
+ /CIDFont /Category pdf_resourcestatus
+ {
+ pop pop
+ /CIDFont pdf_resourcestatus
+ {pop pop true}
+ {false}
+ ifelse
+ }
+ { pop false }
+ ifelse
+ } bd
+ }
+ if
+ /_pdfString100 100 string def
+ /_pdfComposeFontName
+ {
+ dup length 1 eq
+ {
+ 0 get
+ 1 index
+ type /nametype eq
+ {
+ _pdfString100 cvs
+ length dup dup _pdfString100 exch (-) putinterval
+ _pdfString100 exch 1 add dup _pdfString100 length exch sub getinterval
+ 2 index exch cvs length
+ add 1 add _pdfString100 exch 0 exch getinterval
+ exch pop
+ true
+ }
+ {
+ pop pop
+ false
+ }
+ ifelse
+ }
+ {
+ false
+ }
+ ifelse
+ dup {exch cvn exch} if
+ } bd
+ /_pdfConcatNames
+ {
+ exch
+ _pdfString100 cvs
+ length dup dup _pdfString100 exch (-) putinterval
+ _pdfString100 exch 1 add dup _pdfString100 length exch sub getinterval
+ 3 -1 roll exch cvs length
+ add 1 add _pdfString100 exch 0 exch getinterval
+ cvn
+ } bind def
+ /_pdfTextTempString 50 string def
+ /_pdfRegOrderingArray [(Adobe-Japan1) (Adobe-CNS1) (Adobe-Korea1) (Adobe-GB1)] def
+ /_pdf_CheckCIDSystemInfo
+ {
+ 1 index _pdfTextTempString cvs
+ (Identity) anchorsearch
+ {
+ pop pop pop pop true
+ }
+ {
+ false
+ _pdfRegOrderingArray
+ {
+ 2 index exch
+ anchorsearch
+ { pop pop pop true exit}
+ { pop }
+ ifelse
+ }
+ forall
+ exch pop
+ exch /CIDFont findresource
+ /CIDSystemInfo get
+ 3 -1 roll /CMap findresource
+ /CIDSystemInfo get
+ exch
+ 3 -1 roll
+ {
+ 2 copy
+ /Supplement get
+ exch
+ dup type /dicttype eq
+ {/Supplement get}
+ {pop 0 }
+ ifelse
+ ge
+ }
+ { true }
+ ifelse
+ {
+ dup /Registry get
+ 2 index /Registry get eq
+ {
+ /Ordering get
+ exch /Ordering get
+ dup type /arraytype eq
+ {
+ 1 index type /arraytype eq
+ {
+ true
+ 1 index length 1 sub -1 0
+ {
+ dup 2 index exch get exch 3 index exch get ne
+ { pop false exit}
+ if
+ } for
+ exch pop exch pop
+ }
+ { pop pop false }
+ ifelse
+ }
+ {
+ eq
+ }
+ ifelse
+ }
+ { pop pop false }
+ ifelse
+ }
+ { pop pop false }
+ ifelse
+ }
+ ifelse
+ } bind def
+ pdf_has_composefont?
+ {
+ /_pdfComposeFont
+ {
+ 2 copy _pdfComposeFontName not
+ {
+ 2 index
+ }
+ if
+ (pdf) exch _pdfConcatNames
+ dup _pdfFontStatus
+ { dup findfont 5 2 roll pop pop pop true}
+ {
+ 4 1 roll
+ 1 index /CMap pdf_resourcestatus
+ {
+ pop pop
+ true
+ }
+ {false}
+ ifelse
+ 1 index true exch
+ {
+ _pdfCIDFontStatus not
+ {pop false exit}
+ if
+ }
+ forall
+ and
+ {
+ 1 index 1 index 0 get _pdf_CheckCIDSystemInfo
+ {
+ 3 -1 roll pop
+ 2 index 3 1 roll
+ composefont true
+ }
+ {
+ pop pop exch pop false
+ }
+ ifelse
+ }
+ {
+ _pdfComposeFontName
+ {
+ dup _pdfFontStatus
+ {
+ exch pop
+ 1 index exch
+ findfont definefont true
+ }
+ {
+ pop exch pop
+ false
+ }
+ ifelse
+ }
+ {
+ exch pop
+ false
+ }
+ ifelse
+ }
+ ifelse
+ { true }
+ {
+ dup _pdfFontStatus
+ { dup findfont true }
+ { pop false }
+ ifelse
+ }
+ ifelse
+ }
+ ifelse
+ } bd
+ }
+ {
+ /_pdfComposeFont
+ {
+ _pdfComposeFontName not
+ {
+ dup
+ }
+ if
+ dup
+ _pdfFontStatus
+ {exch pop dup findfont true}
+ {
+ 1 index
+ dup type /nametype eq
+ {pop}
+ {cvn}
+ ifelse
+ eq
+ {pop false}
+ {
+ dup _pdfFontStatus
+ {dup findfont true}
+ {pop false}
+ ifelse
+ }
+ ifelse
+ }
+ ifelse
+ } bd
+ }
+ ifelse
+ /_pdfStyleDicts 4 dict dup begin
+ /Adobe-Japan1 4 dict dup begin
+ Level2?
+ {
+ /Serif
+ /HeiseiMin-W3-83pv-RKSJ-H _pdfFontStatus
+ {/HeiseiMin-W3}
+ {
+ /HeiseiMin-W3 _pdfCIDFontStatus
+ {/HeiseiMin-W3}
+ {/Ryumin-Light}
+ ifelse
+ }
+ ifelse
+ def
+ /SansSerif
+ /HeiseiKakuGo-W5-83pv-RKSJ-H _pdfFontStatus
+ {/HeiseiKakuGo-W5}
+ {
+ /HeiseiKakuGo-W5 _pdfCIDFontStatus
+ {/HeiseiKakuGo-W5}
+ {/GothicBBB-Medium}
+ ifelse
+ }
+ ifelse
+ def
+ /HeiseiMaruGo-W4-83pv-RKSJ-H _pdfFontStatus
+ {/HeiseiMaruGo-W4}
+ {
+ /HeiseiMaruGo-W4 _pdfCIDFontStatus
+ {/HeiseiMaruGo-W4}
+ {
+ /Jun101-Light-RKSJ-H _pdfFontStatus
+ { /Jun101-Light }
+ { SansSerif }
+ ifelse
+ }
+ ifelse
+ }
+ ifelse
+ /RoundSansSerif exch def
+ /Default Serif def
+ }
+ {
+ /Serif /Ryumin-Light def
+ /SansSerif /GothicBBB-Medium def
+ {
+ (fonts/Jun101-Light-83pv-RKSJ-H) status
+ }stopped
+ {pop}{
+ { pop pop pop pop /Jun101-Light }
+ { SansSerif }
+ ifelse
+ /RoundSansSerif exch def
+ }ifelse
+ /Default Serif def
+ }
+ ifelse
+ end
+ def
+ /Adobe-Korea1 4 dict dup begin
+ /Serif /HYSMyeongJo-Medium def
+ /SansSerif /HYGoThic-Medium def
+ /RoundSansSerif SansSerif def
+ /Default Serif def
+ end
+ def
+ /Adobe-GB1 4 dict dup begin
+ /Serif /STSong-Light def
+ /SansSerif /STHeiti-Regular def
+ /RoundSansSerif SansSerif def
+ /Default Serif def
+ end
+ def
+ /Adobe-CNS1 4 dict dup begin
+ /Serif /MKai-Medium def
+ /SansSerif /MHei-Medium def
+ /RoundSansSerif SansSerif def
+ /Default Serif def
+ end
+ def
+ end
+ def
+ /TZzero
+ {
+ /_wmode xdd
+ /_styleArr xdd
+ /_regOrdering xdd
+ 3 copy
+ _pdfComposeFont
+ {
+ 5 2 roll pop pop pop
+ }
+ {
+ [
+ 0 1 _styleArr length 1 sub
+ {
+ _styleArr exch get
+ _pdfStyleDicts _regOrdering 2 copy known
+ {
+ get
+ exch 2 copy known not
+ { pop /Default }
+ if
+ get
+ }
+ {
+ pop pop pop /Unknown
+ }
+ ifelse
+ }
+ for
+ ]
+ exch pop
+ 2 index 3 1 roll
+ _pdfComposeFont
+ {3 -1 roll pop}
+ {
+ findfont dup /FontName get exch
+ }
+ ifelse
+ }
+ ifelse
+ dup /WMode 2 copy known
+ { get _wmode ne }
+ { pop pop _wmode 1 eq}
+ ifelse
+ {
+ exch _wmode _pdfConcatNames
+ dup _pdfFontStatus
+ { exch pop dup findfont false}
+ { exch true }
+ ifelse
+ }
+ {
+ dup /FontType get 0 ne
+ }
+ ifelse
+ {
+ dup /FontType get 3 eq _wmode 1 eq and
+ {
+ _pdfVerticalRomanT3Font dup length 10 add dict copy
+ begin
+ /_basefont exch
+ dup length 3 add dict
+ begin
+ {1 index /FID ne {def}{pop pop} ifelse }
+ forall
+ /Encoding Encoding dup length array copy
+ dup 16#27 /quotesingle put
+ dup 16#60 /grave put
+ _regOrdering /Adobe-Japan1 eq
+ {dup 16#5c /yen put dup 16#a5 /yen put dup 16#b4 /yen put}
+ if
+ def
+ FontName
+ currentdict
+ end
+ definefont
+ def
+ /Encoding _basefont /Encoding get def
+ /_fauxfont true def
+ }
+ {
+ dup length 3 add dict
+ begin
+ {1 index /FID ne {def}{pop pop} ifelse }
+ forall
+ FontType 0 ne
+ {
+ /Encoding Encoding dup length array copy
+ dup 16#27 /quotesingle put
+ dup 16#60 /grave put
+ _regOrdering /Adobe-Japan1 eq
+ {dup 16#5c /yen put}
+ if
+ def
+ /_fauxfont true def
+ } if
+ } ifelse
+ /WMode _wmode def
+ dup dup /FontName exch def
+ currentdict
+ end
+ definefont pop
+ }
+ {
+ pop
+ }
+ ifelse
+ /_pdf_FontDirectory 3 1 roll _safeput
+ }
+ bd
+ Level2?
+ {
+ /Tf {
+ _pdf_FontDirectory 2 index 2 copy known
+ {get exch 3 -1 roll pop}
+ {pop pop}
+ ifelse
+ selectfont
+ } bd
+ }
+ {
+ /Tf {
+ _pdf_FontDirectory 2 index 2 copy known
+ {get exch 3 -1 roll pop}
+ {pop pop}
+ ifelse
+ exch findfont exch
+ dup type /arraytype eq
+ {makefont}
+ {scalefont}
+ ifelse
+ setfont
+ } bd
+ }
+ ifelse
+ /cshow where
+ {
+ pop /pdf_cshow /cshow load dd
+ /pdf_remove2 {pop pop} dd
+ }
+ {
+ /pdf_cshow {exch forall} dd
+ /pdf_remove2 {} dd
+ } ifelse
+ /pdf_xshow
+ {
+ /_pdf_na xdd
+ /_pdf_i 0 dd
+ currentpoint
+ /_pdf_y xdd
+ /_pdf_x xdd
+ {
+ pdf_remove2
+ _pdf_str1 exch 0 exch put
+ _pdf_str1 /_pdf_showproc load exec
+ {_pdf_na _pdf_i get} stopped
+ { pop pop }
+ {
+ _pdf_x _pdf_y moveto
+ 0
+ rmoveto
+ }
+ ifelse
+ _pdf_i 1 add /_pdf_i xdd
+ currentpoint
+ /_pdf_y xdd
+ /_pdf_x xdd
+ }
+ exch
+ pdf_cshow
+ } bd
+ /pdf_yshow
+ {
+ /_pdf_na xdd
+ /_pdf_i 0 dd
+ currentpoint
+ /_pdf_y xdd
+ /_pdf_x xdd
+ {
+ pdf_remove2
+ _pdf_str1 exch 0 exch put
+ _pdf_str1 /_pdf_showproc load exec
+ {_pdf_na _pdf_i get} stopped
+ { pop pop }
+ {
+ _pdf_x _pdf_y moveto
+ 0 exch
+ rmoveto
+ }
+ ifelse
+ _pdf_i 1 add /_pdf_i xdd
+ currentpoint
+ /_pdf_y xdd
+ /_pdf_x xdd
+ }
+ exch
+ pdf_cshow
+ } bd
+ /pdf_xyshow
+ {
+ /_pdf_na xdd
+ /_pdf_i 0 dd
+ currentpoint
+ /_pdf_y xdd
+ /_pdf_x xdd
+ {
+ pdf_remove2
+ _pdf_str1 exch 0 exch put
+ _pdf_str1 /_pdf_showproc load exec
+ {_pdf_na _pdf_i get} stopped
+ { pop pop }
+ {
+ {_pdf_na _pdf_i 1 add get} stopped
+ { pop pop pop}
+ {
+ _pdf_x _pdf_y moveto
+ rmoveto
+ }
+ ifelse
+ }
+ ifelse
+ _pdf_i 2 add /_pdf_i xdd
+ currentpoint
+ /_pdf_y xdd
+ /_pdf_x xdd
+ }
+ exch
+ pdf_cshow
+ } bd
+ /pdfl1xs {/_pdf_showproc /show load dd pdf_xshow} bd
+ /pdfl1ys {/_pdf_showproc /show load dd pdf_yshow} bd
+ /pdfl1xys {/_pdf_showproc /show load dd pdf_xyshow} bd
+ Level2? _ColorSep5044? not and
+ {
+ /pdfxs {{xshow} stopped {pdfl1xs} if} bd
+ /pdfys {{yshow} stopped {pdfl1ys} if} bd
+ /pdfxys {{xyshow} stopped {pdfl1xys} if} bd
+ }
+ {
+ /pdfxs /pdfl1xs load dd
+ /pdfys /pdfl1ys load dd
+ /pdfxys /pdfl1xys load dd
+ } ifelse
+ /pdf_charpath {false charpath} bd
+ /pdf_xcharpath {/_pdf_showproc /pdf_charpath load dd pdf_xshow} bd
+ /pdf_ycharpath {/_pdf_showproc /pdf_charpath load dd pdf_yshow} bd
+ /pdf_xycharpath {/_pdf_showproc /pdf_charpath load dd pdf_xyshow} bd
+ /pdf_strokepath
+ {
+ {
+ pdf_remove2
+ _pdf_str1 exch 0 exch put
+ _pdf_str1 false charpath
+ currentpoint S moveto
+ } bind
+ exch pdf_cshow
+ } bd
+ /pdf_xstrokepath {/_pdf_showproc {pdf_charpath S} dd pdf_xshow} bd
+ /pdf_ystrokepath {/_pdf_showproc {pdf_charpath S} dd pdf_yshow} bd
+ /pdf_xystrokepath {/_pdf_showproc {pdf_charpath S} dd pdf_xyshow} bd
+ Level2? {currentglobal true setglobal} if
+ /d0/setcharwidth ld
+ /nND {{/.notdef} repeat} bd
+ /T3Defs {
+ /BuildChar
+ {
+ 1 index /Encoding get exch get
+ 1 index /BuildGlyph get exec
+ }
+ def
+ /BuildGlyph {
+ exch begin
+ GlyphProcs exch get exec
+ end
+ } def
+ /_pdfT3Font true def
+ } bd
+ /_pdfBoldRomanWidthProc
+ {
+ stringwidth 1 index 0 ne { exch .03 add exch }if setcharwidth
+ 0 0
+ } bd
+ /_pdfType0WidthProc
+ {
+ dup stringwidth 0 0 moveto
+ 2 index true charpath pathbbox
+ 0 -1
+ 7 index 2 div .88
+ setcachedevice2
+ pop
+ 0 0
+ } bd
+ /_pdfType0WMode1WidthProc
+ {
+ dup stringwidth
+ pop 2 div neg -0.88
+ 2 copy
+ moveto
+ 0 -1
+ 5 -1 roll true charpath pathbbox
+ setcachedevice
+ } bd
+ /_pdfBoldBaseFont
+ 11 dict begin
+ /FontType 3 def
+ /FontMatrix[1 0 0 1 0 0]def
+ /FontBBox[0 0 1 1]def
+ /Encoding cHexEncoding def
+ /_setwidthProc /_pdfBoldRomanWidthProc load def
+ /_bcstr1 1 string def
+ /BuildChar
+ {
+ exch begin
+ _basefont setfont
+ _bcstr1 dup 0 4 -1 roll put
+ dup
+ _setwidthProc
+ 3 copy
+ moveto
+ show
+ _basefonto setfont
+ moveto
+ show
+ end
+ }bd
+ currentdict
+ end
+ def
+ pdf_has_composefont?
+ {
+ /_pdfBoldBaseCIDFont
+ 11 dict begin
+ /CIDFontType 1 def
+ /CIDFontName /_pdfBoldBaseCIDFont def
+ /FontMatrix[1 0 0 1 0 0]def
+ /FontBBox[0 0 1 1]def
+ /_setwidthProc /_pdfType0WidthProc load def
+ /_bcstr2 2 string def
+ /BuildGlyph
+ {
+ exch begin
+ _basefont setfont
+ _bcstr2 1 2 index 256 mod put
+ _bcstr2 0 3 -1 roll 256 idiv put
+ _bcstr2 dup _setwidthProc
+ 3 copy
+ moveto
+ show
+ _basefonto setfont
+ moveto
+ show
+ end
+ }bd
+ currentdict
+ end
+ def
+ /_pdfDefineIdentity-H
+ {
+ /Identity-H /CMap PDFText /pdf_resourcestatus get exec
+ {
+ pop pop
+ }
+ {
+ /CIDInit/ProcSet findresource begin 12 dict begin
+ begincmap
+ /CIDSystemInfo
+ 3 dict begin
+ /Registry (Adobe) def
+ /Ordering (Identity) def
+ /Supplement 0 def
+ currentdict
+ end
+ def
+ /CMapName /Identity-H def
+ /CMapVersion 1 def
+ /CMapType 1 def
+ 1 begincodespacerange
+ <0000> <ffff>
+ endcodespacerange
+ 1 begincidrange
+ <0000> <ffff> 0
+ endcidrange
+ endcmap
+ CMapName currentdict/CMap defineresource pop
+ end
+ end
+ } ifelse
+ } def
+ } if
+ /_pdfVerticalRomanT3Font
+ 10 dict begin
+ /FontType 3 def
+ /FontMatrix[1 0 0 1 0 0]def
+ /FontBBox[0 0 1 1]def
+ /_bcstr1 1 string def
+ /BuildChar
+ {
+ exch begin
+ _basefont setfont
+ _bcstr1 dup 0 4 -1 roll put
+ dup
+ _pdfType0WidthProc
+ moveto
+ show
+ end
+ }bd
+ currentdict
+ end
+ def
+ Level2? {setglobal} if
+ /MakeBoldFont
+ {
+ dup /ct_SyntheticBold known
+ {
+ dup length 3 add dict begin
+ CopyFont
+ /ct_StrokeWidth .03 0 FontMatrix idtransform pop def
+ /ct_SyntheticBold true def
+ currentdict
+ end
+ definefont
+ }
+ {
+ dup dup length 3 add dict
+ begin
+ CopyFont
+ /PaintType 2 def
+ /StrokeWidth .03 0 FontMatrix idtransform pop def
+ /dummybold currentdict
+ end
+ definefont
+ dup /FontType get dup 9 ge exch 11 le and
+ {
+ _pdfBoldBaseCIDFont
+ dup length 3 add dict copy begin
+ dup /CIDSystemInfo get /CIDSystemInfo exch def
+ /_Type0Identity /Identity-H 3 -1 roll [ exch ] composefont
+ /_basefont exch def
+ /_Type0Identity /Identity-H 3 -1 roll [ exch ] composefont
+ /_basefonto exch def
+ currentdict
+ end
+ /CIDFont defineresource
+ }
+ {
+ _pdfBoldBaseFont
+ dup length 3 add dict copy begin
+ /_basefont exch def
+ /_basefonto exch def
+ currentdict
+ end
+ definefont
+ }
+ ifelse
+ }
+ ifelse
+ } bd
+ /MakeBold {
+ 1 index
+ _pdf_FontDirectory 2 index 2 copy known
+ {get}
+ {exch pop}
+ ifelse
+ findfont
+ dup
+ /FontType get 0 eq
+ {
+ dup /WMode known {dup /WMode get 1 eq }{false} ifelse
+ version length 4 ge
+ and
+ {version 0 4 getinterval cvi 2015 ge }
+ {true}
+ ifelse
+ {/_pdfType0WidthProc}
+ {/_pdfType0WMode1WidthProc}
+ ifelse
+ _pdfBoldBaseFont /_setwidthProc 3 -1 roll load put
+ {MakeBoldFont} Type0CopyFont definefont
+ }
+ {
+ dup /_fauxfont known not 1 index /SubstMaster known not and
+ {
+ _pdfBoldBaseFont /_setwidthProc /_pdfBoldRomanWidthProc load put
+ MakeBoldFont
+ }
+ {
+ 2 index 2 index eq
+ { exch pop }
+ {
+ dup length dict begin
+ CopyFont
+ currentdict
+ end
+ definefont
+ }
+ ifelse
+ }
+ ifelse
+ }
+ ifelse
+ pop pop
+ dup /dummybold ne
+ {/_pdf_FontDirectory exch dup _safeput }
+ { pop }
+ ifelse
+ }bd
+ /MakeItalic {
+ _pdf_FontDirectory exch 2 copy known
+ {get}
+ {exch pop}
+ ifelse
+ dup findfont
+ dup /FontInfo 2 copy known
+ {
+ get
+ /ItalicAngle 2 copy known
+ {get 0 eq }
+ { pop pop true}
+ ifelse
+ }
+ { pop pop true}
+ ifelse
+ {
+ exch pop
+ dup /FontType get 0 eq Level2? not and
+ { dup /FMapType get 6 eq }
+ { false }
+ ifelse
+ {
+ dup /WMode 2 copy known
+ {
+ get 1 eq
+ { _italMtx_WMode1Type0 }
+ { _italMtxType0 }
+ ifelse
+ }
+ { pop pop _italMtxType0 }
+ ifelse
+ }
+ {
+ dup /WMode 2 copy known
+ {
+ get 1 eq
+ { _italMtx_WMode1 }
+ { _italMtx }
+ ifelse
+ }
+ { pop pop _italMtx }
+ ifelse
+ }
+ ifelse
+ makefont
+ dup /FontType get 42 eq Level2? not or
+ {
+ dup length dict begin
+ CopyFont
+ currentdict
+ end
+ }
+ if
+ 1 index exch
+ definefont pop
+ /_pdf_FontDirectory exch dup _safeput
+ }
+ {
+ pop
+ 2 copy ne
+ {
+ /_pdf_FontDirectory 3 1 roll _safeput
+ }
+ { pop pop }
+ ifelse
+ }
+ ifelse
+ }bd
+ /MakeBoldItalic {
+ /dummybold exch
+ MakeBold
+ /dummybold
+ MakeItalic
+ }bd
+ Level2?
+ {
+ /pdf_CopyDict
+ {1 index length add dict copy}
+ def
+ }
+ {
+ /pdf_CopyDict
+ {
+ 1 index length add dict
+ 1 index wcheck
+ { copy }
+ { begin
+ {def} forall
+ currentdict
+ end
+ }
+ ifelse
+ }
+ def
+ }
+ ifelse
+ /pdf_AddEuroGlyphProc
+ {
+ currentdict /CharStrings known
+ {
+ CharStrings /Euro known not
+ {
+ dup
+ /CharStrings
+ CharStrings 1 pdf_CopyDict
+ begin
+ /Euro pdf_EuroProcSet 4 -1 roll get def
+ currentdict
+ end
+ def
+ /pdf_PSBuildGlyph /pdf_PSBuildGlyph load def
+ /pdf_PathOps /pdf_PathOps load def
+ /Symbol eq
+ {
+ /Encoding Encoding dup length array copy
+ dup 160 /Euro put def
+ }
+ if
+ }
+ { pop
+ }
+ ifelse
+ }
+ { pop
+ }
+ ifelse
+ }
+ def
+ Level2? {currentglobal true setglobal} if
+ /pdf_PathOps 4 dict dup begin
+ /m {moveto} def
+ /l {lineto} def
+ /c {curveto} def
+ /cp {closepath} def
+ end
+ def
+ /pdf_PSBuildGlyph
+ {
+ gsave
+ 8 -1 roll pop
+ 7 1 roll
+ currentdict /PaintType 2 copy known {get 2 eq}{pop pop false} ifelse
+ dup 9 1 roll
+ {
+ currentdict /StrokeWidth 2 copy known
+ {
+ get 2 div
+ 5 1 roll
+ 4 -1 roll 4 index sub
+ 4 1 roll
+ 3 -1 roll 4 index sub
+ 3 1 roll
+ exch 4 index add exch
+ 4 index add
+ 5 -1 roll pop
+ }
+ {
+ pop pop
+ }
+ ifelse
+ }
+ if
+ setcachedevice
+ pdf_PathOps begin
+ exec
+ end
+ {
+ currentdict /StrokeWidth 2 copy known
+ { get }
+ { pop pop 0 }
+ ifelse
+ setlinewidth stroke
+ }
+ {
+ fill
+ }
+ ifelse
+ grestore
+ } def
+ /pdf_EuroProcSet 13 dict def
+ pdf_EuroProcSet
+ begin
+ /Courier-Bold
+ {
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+ {
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+ cp
+ 600 0 m
+ }
+ pdf_PSBuildGlyph
+ } def
+ /Courier-BoldOblique /Courier-Bold load def
+ /Courier
+ {
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+ {
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+ 37 259 l
+ cp
+ 600 0 m
+ }
+ pdf_PSBuildGlyph
+ } def
+ /Courier-Oblique /Courier load def
+ /Helvetica
+ {
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+ {
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+ pdf_PSBuildGlyph
+ } def
+ /Helvetica-Oblique /Helvetica load def
+ /Helvetica-Bold
+ {
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+ pdf_PSBuildGlyph
+ } def
+ /Helvetica-BoldOblique /Helvetica-Bold load def
+ /Symbol
+ {
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+ pdf_PSBuildGlyph
+ } def
+ /Times-Bold
+ {
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+ }
+ pdf_PSBuildGlyph
+ } def
+ /Times-BoldItalic
+ {
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+ } def
+ /Times-Italic
+ {
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+ pdf_PSBuildGlyph
+ } def
+ /Times-Roman
+ {
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+ 481 462 l
+ 474 691 l
+ 449 691 l
+ 433 670 429 657 410 657 c
+ 394 657 360 692 299 692 c
+ 204 692 94 604 73 403 c
+ 22 403 l
+ 10 362 l
+ 70 362 l
+ 69 352 69 341 69 330 c
+ 69 319 69 308 70 298 c
+ 22 298 l
+ 10 257 l
+ 73 257 l
+ 97 57 216 -12 295 -12 c
+ 364 -12 427 25 484 123 c
+ 458 142 l
+ 425 101 384 37 316 37 c
+ 256 37 189 84 173 257 c
+ 335 257 l
+ cp
+ 500 0 m
+ }
+ pdf_PSBuildGlyph
+ } def
+ end
+ Level2? {setglobal} if
+ currentdict readonly pop end
+ %%EndResource
+ PDFText begin
+ [userdict /pdf_svglb currentglobal put true setglobal
+ 39/quotesingle 96/grave 128/Adieresis/Aring/Ccedilla/Eacute/Ntilde/Odieresis
+ /Udieresis/aacute/agrave/acircumflex/adieresis/atilde/aring/ccedilla/eacute
+ /egrave/ecircumflex/edieresis/iacute/igrave/icircumflex/idieresis/ntilde
+ /oacute/ograve/ocircumflex/odieresis/otilde/uacute/ugrave/ucircumflex
+ /udieresis/dagger/degree/cent/sterling/section/bullet/paragraph/germandbls
+ /registered/copyright/trademark/acute/dieresis/.notdef/AE/Oslash
+ /.notdef/plusminus/.notdef/.notdef/yen/mu/.notdef/.notdef
+ /.notdef/.notdef/.notdef/ordfeminine/ordmasculine/.notdef/ae/oslash
+ /questiondown/exclamdown/logicalnot/.notdef/florin/.notdef/.notdef
+ /guillemotleft/guillemotright/ellipsis/space/Agrave/Atilde/Otilde/OE/oe
+ /endash/emdash/quotedblleft/quotedblright/quoteleft/quoteright/divide
+ /.notdef/ydieresis/Ydieresis/fraction/currency/guilsinglleft/guilsinglright
+ /fi/fl/daggerdbl/periodcentered/quotesinglbase/quotedblbase/perthousand
+ /Acircumflex/Ecircumflex/Aacute/Edieresis/Egrave/Iacute/Icircumflex
+ /Idieresis/Igrave/Oacute/Ocircumflex/.notdef/Ograve/Uacute/Ucircumflex
+ /Ugrave/dotlessi/circumflex/tilde/macron/breve/dotaccent/ring/cedilla
+ /hungarumlaut/ogonek/caron
+ 0 TE
+ [1/dotlessi/caron 39/quotesingle 96/grave 
+ 127/bullet/Euro/bullet/quotesinglbase/florin/quotedblbase/ellipsis
+ /dagger/daggerdbl/circumflex/perthousand/Scaron/guilsinglleft/OE
+ /bullet/Zcaron/bullet/bullet/quoteleft/quoteright/quotedblleft
+ /quotedblright/bullet/endash/emdash/tilde/trademark/scaron
+ /guilsinglright/oe/bullet/zcaron/Ydieresis/space/exclamdown/cent/sterling
+ /currency/yen/brokenbar/section/dieresis/copyright/ordfeminine
+ /guillemotleft/logicalnot/hyphen/registered/macron/degree/plusminus
+ /twosuperior/threesuperior/acute/mu/paragraph/periodcentered/cedilla
+ /onesuperior/ordmasculine/guillemotright/onequarter/onehalf/threequarters
+ /questiondown/Agrave/Aacute/Acircumflex/Atilde/Adieresis/Aring/AE/Ccedilla
+ /Egrave/Eacute/Ecircumflex/Edieresis/Igrave/Iacute/Icircumflex/Idieresis
+ /Eth/Ntilde/Ograve/Oacute/Ocircumflex/Otilde/Odieresis/multiply/Oslash
+ /Ugrave/Uacute/Ucircumflex/Udieresis/Yacute/Thorn/germandbls/agrave
+ /aacute/acircumflex/atilde/adieresis/aring/ae/ccedilla/egrave/eacute
+ /ecircumflex/edieresis/igrave/iacute/icircumflex/idieresis/eth/ntilde
+ /ograve/oacute/ocircumflex/otilde/odieresis/divide/oslash/ugrave/uacute
+ /ucircumflex/udieresis/yacute/thorn/ydieresis
+ 1 TE
+ end
+ 
+ userdict /pdf_svglb get setglobal
+ %%BeginResource: pdfasc.prc
+ %%Version: 4.0 2
+ %%Copyright: Copyright 1992-1997 Adobe Systems Incorporated. All Rights Reserved.
+ /AS {
+ 9 dict begin
+ /shrink? xdd
+ /Pury xdd
+ /Purx xdd
+ /Plly xdd
+ /Pllx xdd
+ gsave newpath clippath pathbbox newpath grestore
+ /Dury xdd
+ /Durx xdd
+ /Dlly xdd
+ /Dllx xdd
+ Durx Dllx sub Dury Dlly sub
+ Pury Plly sub div exch Purx Pllx sub div
+ 2 copy gt { exch } if pop
+ Durx Dllx add 2 div Dury Dlly add 2 div translate
+ shrink? { dup scale } { pop } ifelse
+ Purx Pllx add -2 div Pury Plly add -2 div translate
+ end
+ } [/shrink? /Pury /Purx /Plly /Pllx /Durx /Dury /Dllx /Dlly]
+ bld
+ %%EndResource
+ currentdict readonly pop
+ end end
+ /currentpacking where {pop setpacking}if
+ PDFVars/DocInitAll{[PDF PDFText]{/docinitialize get exec}forall }put
+ PDFVars/InitAll{[PDF PDFText]{/initialize get exec}forall initgs}put
+ PDFVars/TermAll{[PDFText PDF]{/terminate get exec}forall}put
+ PDFVars begin PDF begin
+ PDFVars/DocInitAll get exec PDFVars/InitAll get exec
+ userdict /pdf_svglb currentglobal put true setglobal
+ %%BeginResource: font YUSZLK+CMR6
+ ct_CffDict begin
+ %!FontType1
+ 14 dict begin
+ /FontInfo 13 dict dup begin
+ /Notice (Copyright (C) 1997 American Mathematical Society. All Rights Reserved) def
+ /FullName (CMR6) def
+ /FamilyName (Computer Modern) def
+ /ItalicAngle 0 def
+ /isFixedPitch false  def
+ /UnderlinePosition -100 def
+ /UnderlineThickness 50 def
+ end def
+ /FontName /YUSZLK+CMR6 def
+ /Encoding 256 array
+ 0 1 255 {1 index exch /.notdef put} for
+ dup 0 /.notdef put
+  def
+ /PaintType 0 def
+ /FontType 1 def
+ /FontMatrix [0.001 0 0 0.001 0 0 ] def
+ /FontBBox { 0 -21 564 675 } def
+ /StrokeWidth 0 def
+ currentdict end
+ currentfile eexec A0B00ED5187D9C0F1ECDF51878C3AA5CAA3EC8DC423323
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+ A2AEAD77E33C836B01D3632DEB22D63B3C2572FE1DFC770815B76608523BAFFD
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+ B02928CC6B8E649E7F9AFC81E3B627B74B90567C1BFA4522D1445C8110469C0D
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+ 8DA8CBCF101594CCFA1633CE3366294F157239867A187613DABC3662EA2C9828
+ 5D20A0B6237A1A9CE2D2BBBDEEC217A2D4A4DCEF1E4D51E76C073C2F448A815D
+ D7653647CBB65EEE5B8F2AF61150FCF57831F309227589568E6CB7E931E3BD52
+ DD3BA595223750CE6DCDB5D6F0CE17920D83708E4A9835A093518F53E8C9BFCF
+ ECCC7A3200EFD40030266CEF4DF9B665B3CF71E25664FED56B9360995931212F
+ 3C966FEAD94C942993E7994A8722DD73179039704B3BF28BB56A8836CE147AD7
+ 62F82CB083323CC1D527193F8E6913F51CE8501FBFE47AB2C56729AD8338C803
+ A8BF44153BEA5B82C40A68C2313CFD07C79415BDFB9B5D8E1824A930C7B93FEB
+ B7B92560FE41333CD892912BB9CC111DEAA9B3CA9BC760755A9546D0F88B6D00
+ 5B47F503AECF58011847D41869482AFA6B6F9D7EC51CFDD0B1038EC55FBA7FFD
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+ E298CFE8D80DEF33B5FDE0A86B90A666A52C
+ 0000000000000000000000000000000000000000000000000000000000000000
+ 0000000000000000000000000000000000000000000000000000000000000000
+ 0000000000000000000000000000000000000000000000000000000000000000
+ 0000000000000000000000000000000000000000000000000000000000000000
+ 0000000000000000000000000000000000000000000000000000000000000000
+ 0000000000000000000000000000000000000000000000000000000000000000
+ 0000000000000000000000000000000000000000000000000000000000000000
+ 0000000000000000000000000000000000000000000000000000000000000000
+ cleartomark
+ /YUSZLK+CMR6 findfont /Encoding get
+ dup 0 /.notdef put
+ pop
+ end
+ /YUSZLK+CMR6 findfont /Encoding get
+ dup 0 /.notdef put
+ dup 48 /.notdef put
+ dup 49 /.notdef put
+ dup 50 /.notdef put
+ dup 51 /.notdef put
+ dup 52 /.notdef put
+ dup 53 /.notdef put
+ dup 54 /.notdef put
+ pop
+ %%EndResource
+ 
+ userdict /pdf_svglb get setglobal
+ [/N21/YUSZLK+CMR6 1 TZG
+ userdict /pdf_svglb currentglobal put true setglobal
+ %%BeginResource: font MXUJJG+CMR8
+ ct_CffDict begin
+ %!FontType1
+ 14 dict begin
+ /FontInfo 13 dict dup begin
+ /Notice (Copyright (C) 1997 American Mathematical Society. All Rights Reserved) def
+ /FullName (CMR8) def
+ /FamilyName (Computer Modern) def
+ /ItalicAngle 0 def
+ /isFixedPitch false  def
+ /UnderlinePosition -100 def
+ /UnderlineThickness 50 def
+ end def
+ /FontName /MXUJJG+CMR8 def
+ /Encoding 256 array
+ 0 1 255 {1 index exch /.notdef put} for
+ dup 0 /.notdef put
+  def
+ /PaintType 0 def
+ /FontType 1 def
+ /FontMatrix [0.001 0 0 0.001 0 0 ] def
+ /FontBBox { -36 -250 1070 750 } def
+ /StrokeWidth 0 def
+ currentdict end
+ currentfile eexec A0B00ED5187D9C0F1ECDF51878C3AA5CAA3EC8DC423323
+ 00A152553EC9C9C51591C81BB5A2F58753878D92B1C73E948BB360F467A7D593
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+ A2AEAD77E33C836B01D3632DEB22D63B3C2572FE1DFC770815B76608523BAFFD
+ DA862456E4C538AD97F8DA4503B285C5BF293C8E4F4B65390D8C76DB8184D5F3
+ CAFAE9F941BCE3CB8EE317CA5B51796D7B4B0A38FA07929DD61A147547B4C58F
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+ end
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+ dup 0 /.notdef put
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+ %%EndResource
+ 
+ userdict /pdf_svglb get setglobal
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+ /bullet/bullet/quoteleft/quoteright/quotedblleft/quotedblright
+ /bullet/endash/emdash/tilde/trademark/scaron
+ /guilsinglright/oe/bullet/zcaron/Ydieresis/space
+ /exclamdown/cent/sterling/currency/yen/brokenbar
+ /section/dieresis/copyright/ordfeminine/guillemotleft/logicalnot
+ /hyphen/registered/macron/degree/plusminus/twosuperior
+ /threesuperior/acute/mu/paragraph/periodcentered/cedilla
+ /onesuperior/ordmasculine/guillemotright/onequarter/onehalf/threequarters
+ /questiondown/Agrave/Aacute/Acircumflex/Atilde/Adieresis
+ /Aring/AE/Ccedilla/Egrave/Eacute/Ecircumflex
+ /Edieresis/Igrave/Iacute/Icircumflex/Idieresis/Eth
+ /Ntilde/Ograve/Oacute/Ocircumflex/Otilde/Odieresis
+ /multiply/Oslash/Ugrave/Uacute/Ucircumflex/Udieresis
+ /Yacute/Thorn/germandbls/agrave/aacute/acircumflex
+ /atilde/adieresis/aring/ae/ccedilla/egrave
+ /eacute/ecircumflex/edieresis/igrave/iacute/icircumflex
+ /idieresis/eth/ntilde/ograve/oacute/ocircumflex
+ /otilde/odieresis/divide/oslash/ugrave/uacute
+ /ucircumflex/udieresis/yacute/thorn/ydieresis
+ /N55/EYHIUN+CMMI7 -1 TZG
+ userdict /pdf_svglb currentglobal put true setglobal
+ %%BeginResource: font KTYNWY+CMSY5
+ ct_CffDict begin
+ %!FontType1
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+ /Notice (Copyright (C) 1997 American Mathematical Society. All Rights Reserved) def
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+ /isFixedPitch false  def
+ /UnderlinePosition -100 def
+ /UnderlineThickness 50 def
+ end def
+ /FontName /KTYNWY+CMSY5 def
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+  def
+ /PaintType 0 def
+ /FontType 1 def
+ /FontMatrix [0.001 0 0 0.001 0 0 ] def
+ /FontBBox { 0 0 370 559 } def
+ /StrokeWidth 0 def
+ currentdict end
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+ pop
+ end
+ /KTYNWY+CMSY5 findfont /Encoding get
+ dup 0 /.notdef put
+ dup 48 /prime put
+ pop
+ %%EndResource
+ 
+ userdict /pdf_svglb get setglobal
+ [ 1 /dotlessi/caron 32 /space/exclam/quotedbl/numbersign
+ /dollar/percent/ampersand/quotesingle/parenleft/parenright
+ /asterisk/plus/comma/hyphen/period/slash
+ /prime/one/two/three/four/five
+ /six/seven/eight/nine/colon/semicolon
+ /less/equal/greater/question/at/A
+ /B/C/D/E/F/G
+ /H/I/J/K/L/M
+ /N/O/P/Q/R/S
+ /T/U/V/W/X/Y
+ /Z/bracketleft/backslash/bracketright/asciicircum/underscore
+ /grave/a/b/c/d/e
+ /f/g/h/i/j/k
+ /l/m/n/o/p/q
+ /r/s/t/u/v/w
+ /x/y/z/braceleft/bar/braceright
+ /asciitilde/bullet/Euro/bullet/quotesinglbase/florin
+ /quotedblbase/ellipsis/dagger/daggerdbl/circumflex/perthousand
+ /Scaron/guilsinglleft/OE/bullet/Zcaron/bullet
+ /bullet/quoteleft/quoteright/quotedblleft/quotedblright/bullet
+ /endash/emdash/tilde/trademark/scaron/guilsinglright
+ /oe/bullet/zcaron/Ydieresis/space/exclamdown
+ /cent/sterling/currency/yen/brokenbar/section
+ /dieresis/copyright/ordfeminine/guillemotleft/logicalnot/hyphen
+ /registered/macron/degree/plusminus/twosuperior/threesuperior
+ /acute/mu/paragraph/periodcentered/cedilla/onesuperior
+ /ordmasculine/guillemotright/onequarter/onehalf/threequarters/questiondown
+ /Agrave/Aacute/Acircumflex/Atilde/Adieresis/Aring
+ /AE/Ccedilla/Egrave/Eacute/Ecircumflex/Edieresis
+ /Igrave/Iacute/Icircumflex/Idieresis/Eth/Ntilde
+ /Ograve/Oacute/Ocircumflex/Otilde/Odieresis/multiply
+ /Oslash/Ugrave/Uacute/Ucircumflex/Udieresis/Yacute
+ /Thorn/germandbls/agrave/aacute/acircumflex/atilde
+ /adieresis/aring/ae/ccedilla/egrave/eacute
+ /ecircumflex/edieresis/igrave/iacute/icircumflex/idieresis
+ /eth/ntilde/ograve/oacute/ocircumflex/otilde
+ /odieresis/divide/oslash/ugrave/uacute/ucircumflex
+ /udieresis/yacute/thorn/ydieresis
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+ pop
+ %%EndResource
+ 
+ userdict /pdf_svglb get setglobal
+ [/N98/ATKSOD+Arial-BoldMT 1 TZG
+ /N93 <~It)rtIt)rtIt)rtIt)rtIt)rtIt)rtIt)rtIt)rtIt)rtIt)rtIt)rtIt)rtIt)rt
+ It)rtIt)rtIt)rtIt)rtIt)rtIt)rtIt)rtIt)rtIt)rtIt)rtIt)rtIt)rtIt)rt
+ It)rtIt)rtIt)rtIt)rtIt)rtIt)rtIt)rtIt)rtIt)rtIt)rtIt)rtIt)rtIt)rt
+ It)rtIt)rtIt)rtIt)rtIt)rtIt)rtIt)rtIt)rtIt)rtIt)rtIt)rtIt)rtIt)rt
+ It)rtIt)rtIt)rtIt)rtIt)rtIt)rtIt)rtIt)rtIt)rtIt)rtIt)rtIt)rt~> 15 dict begin
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+ }} ifelse
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+ /Function defineRes pop
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+ }} ifelse
+ def
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+ 0 1 3 2 roll limit rnd
+ end
+ } bind aload pop] cvx readonly
+ /Function defineRes pop
+ 
+ /N100 <~It)rtIt)rtIt)rtIt)rtIt)rtIt)rtIt)rtIt)rtIt)rtIt)rtIt)rtIt)rtIt)rt
+ It)rtIt)rtIt)rtIt)rtIt)rtIt)rtIt)rtIt)rtIt)rtIt)rtIt)rtIt)rtIt)rt
+ It)rtIt)rtIt)rtIt)rtIt)rtIt)rtIt)rtIt)rtIt)rtIt)rtIt)rtIt)rtIt)rt
+ It)rtIt)rtIt)rtIt)rtIt)rtIt)rtIt)rtIt)rtIt)rtIt)rtIt)rtIt)rtIt)rt
+ It)rtIt)rtIt)rtIt)rtIt)rtIt)rtIt)rtIt)rtIt)rtIt)rtIt)rtIt)rt~> 15 dict begin
+ /Sample exch def
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+ dup 1 ge {pop 255}
+ {dup 0 le {pop 0}
+ {255 mul 
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+ } ifelse
+ def
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+ /f0
+ min0 max0 eq
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+ {{
+ [min0 f1 max0 f1
+ 0 1 0 {dup 3 index exch get exch 2 index exch get
+ _tmp0 min0 max0 5 3 roll int
+ 3 1 roll} for pop pop]
+ }} ifelse
+ def
+ /f1
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+  0 255 prm0 limit 8 mul -3 bitshift Sample exch get ]} def
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+ {2.00787 255 div mul 1 sub 
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+ } ifelse
+ -1 1 3 2 roll limit rnd
+ end
+ } bind aload pop] cvx readonly
+ /Function defineRes pop
+ 
+ /N99 <~zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz~> 15 dict begin
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+ dup 1 ge {pop 255}
+ {dup 0 le {pop 0}
+ {255 mul 
+ } ifelse
+ } ifelse
+ def
+ /min0 _tmp0 cvi def
+ /max0 _tmp0 ceiling cvi def
+ /f0
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+ {{min0 f1}}
+ {{
+ [min0 f1 max0 f1
+ 0 1 0 {dup 3 index exch get exch 2 index exch get
+ _tmp0 min0 max0 5 3 roll int
+ 3 1 roll} for pop pop]
+ }} ifelse
+ def
+ /f1
+ {/prm0 exch def [
+  0 255 prm0 limit 8 mul -3 bitshift Sample exch get ]} def
+ /rnd {256 mul 0.5 add floor 256 div} def
+ f0 aload pop
+ dup 255 ge {pop 1}
+ {dup 0 le {pop 0}
+ {255 div 
+ } ifelse
+ } ifelse
+ 0 1 3 2 roll limit rnd
+ end
+ } bind aload pop] cvx readonly
+ /Function defineRes pop
+ 
+ /N103 <~It)rtIt)rtIt)rtIt)rtIt)rtIt)rtIt)rtIt)rtIt)rtIt)rtIt)rtIt)rtIt)rt
+ It)rtIt)rtIt)rtIt)rtIt)rtIt)rtIt)rtIt)rtIt)rtIt)rtIt)rtIt)rtIt)rt
+ It)rtIt)rtIt)rtIt)rtIt)rtIt)rtIt)rtIt)rtIt)rtIt)rtIt)rtIt)rtIt)rt
+ It)rtIt)rtIt)rtIt)rtIt)rtIt)rtIt)rtIt)rtIt)rtIt)rtIt)rtIt)rtIt)rt
+ It)rtIt)rtIt)rtIt)rtIt)rtIt)rtIt)rtIt)rtIt)rtIt)rtIt)rtIt)rt~> 15 dict begin
+ /Sample exch def
+ currentdict end
+ [exch {begin
+ /_x0 exch def
+ /_tmp0 _x0
+ dup 1 ge {pop 255}
+ {dup 0 le {pop 0}
+ {255 mul 
+ } ifelse
+ } ifelse
+ def
+ /min0 _tmp0 cvi def
+ /max0 _tmp0 ceiling cvi def
+ /f0
+ min0 max0 eq
+ {{min0 f1}}
+ {{
+ [min0 f1 max0 f1
+ 0 1 0 {dup 3 index exch get exch 2 index exch get
+ _tmp0 min0 max0 5 3 roll int
+ 3 1 roll} for pop pop]
+ }} ifelse
+ def
+ /f1
+ {/prm0 exch def [
+  0 255 prm0 limit 8 mul -3 bitshift Sample exch get ]} def
+ /rnd {256 mul 0.5 add floor 256 div} def
+ f0 aload pop
+ dup 255 ge {pop 1.00787}
+ {dup 0 le {pop -1}
+ {2.00787 255 div mul 1 sub 
+ } ifelse
+ } ifelse
+ -1 1 3 2 roll limit rnd
+ end
+ } bind aload pop] cvx readonly
+ /Function defineRes pop
+ 
+ /N102 <~zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz~> 15 dict begin
+ /Sample exch def
+ currentdict end
+ [exch {begin
+ /_x0 exch def
+ /_tmp0 _x0
+ dup 1 ge {pop 255}
+ {dup 0 le {pop 0}
+ {255 mul 
+ } ifelse
+ } ifelse
+ def
+ /min0 _tmp0 cvi def
+ /max0 _tmp0 ceiling cvi def
+ /f0
+ min0 max0 eq
+ {{min0 f1}}
+ {{
+ [min0 f1 max0 f1
+ 0 1 0 {dup 3 index exch get exch 2 index exch get
+ _tmp0 min0 max0 5 3 roll int
+ 3 1 roll} for pop pop]
+ }} ifelse
+ def
+ /f1
+ {/prm0 exch def [
+  0 255 prm0 limit 8 mul -3 bitshift Sample exch get ]} def
+ /rnd {256 mul 0.5 add floor 256 div} def
+ f0 aload pop
+ dup 255 ge {pop 1}
+ {dup 0 le {pop 0}
+ {255 div 
+ } ifelse
+ } ifelse
+ 0 1 3 2 roll limit rnd
+ end
+ } bind aload pop] cvx readonly
+ /Function defineRes pop
+ 
+ /N106 <~It)rtIt)rtIt)rtIt)rtIt)rtIt)rtIt)rtIt)rtIt)rtIt)rtIt)rtIt)rtIt)rt
+ It)rtIt)rtIt)rtIt)rtIt)rtIt)rtIt)rtIt)rtIt)rtIt)rtIt)rtIt)rtIt)rt
+ It)rtIt)rtIt)rtIt)rtIt)rtIt)rtIt)rtIt)rtIt)rtIt)rtIt)rtIt)rtIt)rt
+ It)rtIt)rtIt)rtIt)rtIt)rtIt)rtIt)rtIt)rtIt)rtIt)rtIt)rtIt)rtIt)rt
+ It)rtIt)rtIt)rtIt)rtIt)rtIt)rtIt)rtIt)rtIt)rtIt)rtIt)rtIt)rt~> 15 dict begin
+ /Sample exch def
+ currentdict end
+ [exch {begin
+ /_x0 exch def
+ /_tmp0 _x0
+ dup 1 ge {pop 255}
+ {dup 0 le {pop 0}
+ {255 mul 
+ } ifelse
+ } ifelse
+ def
+ /min0 _tmp0 cvi def
+ /max0 _tmp0 ceiling cvi def
+ /f0
+ min0 max0 eq
+ {{min0 f1}}
+ {{
+ [min0 f1 max0 f1
+ 0 1 0 {dup 3 index exch get exch 2 index exch get
+ _tmp0 min0 max0 5 3 roll int
+ 3 1 roll} for pop pop]
+ }} ifelse
+ def
+ /f1
+ {/prm0 exch def [
+  0 255 prm0 limit 8 mul -3 bitshift Sample exch get ]} def
+ /rnd {256 mul 0.5 add floor 256 div} def
+ f0 aload pop
+ dup 255 ge {pop 1.00787}
+ {dup 0 le {pop -1}
+ {2.00787 255 div mul 1 sub 
+ } ifelse
+ } ifelse
+ -1 1 3 2 roll limit rnd
+ end
+ } bind aload pop] cvx readonly
+ /Function defineRes pop
+ 
+ /N105 <~zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz~> 15 dict begin
+ /Sample exch def
+ currentdict end
+ [exch {begin
+ /_x0 exch def
+ /_tmp0 _x0
+ dup 1 ge {pop 255}
+ {dup 0 le {pop 0}
+ {255 mul 
+ } ifelse
+ } ifelse
+ def
+ /min0 _tmp0 cvi def
+ /max0 _tmp0 ceiling cvi def
+ /f0
+ min0 max0 eq
+ {{min0 f1}}
+ {{
+ [min0 f1 max0 f1
+ 0 1 0 {dup 3 index exch get exch 2 index exch get
+ _tmp0 min0 max0 5 3 roll int
+ 3 1 roll} for pop pop]
+ }} ifelse
+ def
+ /f1
+ {/prm0 exch def [
+  0 255 prm0 limit 8 mul -3 bitshift Sample exch get ]} def
+ /rnd {256 mul 0.5 add floor 256 div} def
+ f0 aload pop
+ dup 255 ge {pop 1}
+ {dup 0 le {pop 0}
+ {255 div 
+ } ifelse
+ } ifelse
+ 0 1 3 2 roll limit rnd
+ end
+ } bind aload pop] cvx readonly
+ /Function defineRes pop
+ 
+ /N109 <~It)rtIt)rtIt)rtIt)rtIt)rtIt)rtIt)rtIt)rtIt)rtIt)rtIt)rtIt)rtIt)rt
+ It)rtIt)rtIt)rtIt)rtIt)rtIt)rtIt)rtIt)rtIt)rtIt)rtIt)rtIt)rtIt)rt
+ It)rtIt)rtIt)rtIt)rtIt)rtIt)rtIt)rtIt)rtIt)rtIt)rtIt)rtIt)rtIt)rt
+ It)rtIt)rtIt)rtIt)rtIt)rtIt)rtIt)rtIt)rtIt)rtIt)rtIt)rtIt)rtIt)rt
+ It)rtIt)rtIt)rtIt)rtIt)rtIt)rtIt)rtIt)rtIt)rtIt)rtIt)rtIt)rt~> 15 dict begin
+ /Sample exch def
+ currentdict end
+ [exch {begin
+ /_x0 exch def
+ /_tmp0 _x0
+ dup 1 ge {pop 255}
+ {dup 0 le {pop 0}
+ {255 mul 
+ } ifelse
+ } ifelse
+ def
+ /min0 _tmp0 cvi def
+ /max0 _tmp0 ceiling cvi def
+ /f0
+ min0 max0 eq
+ {{min0 f1}}
+ {{
+ [min0 f1 max0 f1
+ 0 1 0 {dup 3 index exch get exch 2 index exch get
+ _tmp0 min0 max0 5 3 roll int
+ 3 1 roll} for pop pop]
+ }} ifelse
+ def
+ /f1
+ {/prm0 exch def [
+  0 255 prm0 limit 8 mul -3 bitshift Sample exch get ]} def
+ /rnd {256 mul 0.5 add floor 256 div} def
+ f0 aload pop
+ dup 255 ge {pop 1.00787}
+ {dup 0 le {pop -1}
+ {2.00787 255 div mul 1 sub 
+ } ifelse
+ } ifelse
+ -1 1 3 2 roll limit rnd
+ end
+ } bind aload pop] cvx readonly
+ /Function defineRes pop
+ 
+ /N108 <~zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz~> 15 dict begin
+ /Sample exch def
+ currentdict end
+ [exch {begin
+ /_x0 exch def
+ /_tmp0 _x0
+ dup 1 ge {pop 255}
+ {dup 0 le {pop 0}
+ {255 mul 
+ } ifelse
+ } ifelse
+ def
+ /min0 _tmp0 cvi def
+ /max0 _tmp0 ceiling cvi def
+ /f0
+ min0 max0 eq
+ {{min0 f1}}
+ {{
+ [min0 f1 max0 f1
+ 0 1 0 {dup 3 index exch get exch 2 index exch get
+ _tmp0 min0 max0 5 3 roll int
+ 3 1 roll} for pop pop]
+ }} ifelse
+ def
+ /f1
+ {/prm0 exch def [
+  0 255 prm0 limit 8 mul -3 bitshift Sample exch get ]} def
+ /rnd {256 mul 0.5 add floor 256 div} def
+ f0 aload pop
+ dup 255 ge {pop 1}
+ {dup 0 le {pop 0}
+ {255 div 
+ } ifelse
+ } ifelse
+ 0 1 3 2 roll limit rnd
+ end
+ } bind aload pop] cvx readonly
+ /Function defineRes pop
+ 
+ /N112 <~It)rtIt)rtIt)rtIt)rtIt)rtIt)rtIt)rtIt)rtIt)rtIt)rtIt)rtIt)rtIt)rt
+ It)rtIt)rtIt)rtIt)rtIt)rtIt)rtIt)rtIt)rtIt)rtIt)rtIt)rtIt)rtIt)rt
+ It)rtIt)rtIt)rtIt)rtIt)rtIt)rtIt)rtIt)rtIt)rtIt)rtIt)rtIt)rtIt)rt
+ It)rtIt)rtIt)rtIt)rtIt)rtIt)rtIt)rtIt)rtIt)rtIt)rtIt)rtIt)rtIt)rt
+ It)rtIt)rtIt)rtIt)rtIt)rtIt)rtIt)rtIt)rtIt)rtIt)rtIt)rtIt)rt~> 15 dict begin
+ /Sample exch def
+ currentdict end
+ [exch {begin
+ /_x0 exch def
+ /_tmp0 _x0
+ dup 1 ge {pop 255}
+ {dup 0 le {pop 0}
+ {255 mul 
+ } ifelse
+ } ifelse
+ def
+ /min0 _tmp0 cvi def
+ /max0 _tmp0 ceiling cvi def
+ /f0
+ min0 max0 eq
+ {{min0 f1}}
+ {{
+ [min0 f1 max0 f1
+ 0 1 0 {dup 3 index exch get exch 2 index exch get
+ _tmp0 min0 max0 5 3 roll int
+ 3 1 roll} for pop pop]
+ }} ifelse
+ def
+ /f1
+ {/prm0 exch def [
+  0 255 prm0 limit 8 mul -3 bitshift Sample exch get ]} def
+ /rnd {256 mul 0.5 add floor 256 div} def
+ f0 aload pop
+ dup 255 ge {pop 1.00787}
+ {dup 0 le {pop -1}
+ {2.00787 255 div mul 1 sub 
+ } ifelse
+ } ifelse
+ -1 1 3 2 roll limit rnd
+ end
+ } bind aload pop] cvx readonly
+ /Function defineRes pop
+ 
+ /N111 <~zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz~> 15 dict begin
+ /Sample exch def
+ currentdict end
+ [exch {begin
+ /_x0 exch def
+ /_tmp0 _x0
+ dup 1 ge {pop 255}
+ {dup 0 le {pop 0}
+ {255 mul 
+ } ifelse
+ } ifelse
+ def
+ /min0 _tmp0 cvi def
+ /max0 _tmp0 ceiling cvi def
+ /f0
+ min0 max0 eq
+ {{min0 f1}}
+ {{
+ [min0 f1 max0 f1
+ 0 1 0 {dup 3 index exch get exch 2 index exch get
+ _tmp0 min0 max0 5 3 roll int
+ 3 1 roll} for pop pop]
+ }} ifelse
+ def
+ /f1
+ {/prm0 exch def [
+  0 255 prm0 limit 8 mul -3 bitshift Sample exch get ]} def
+ /rnd {256 mul 0.5 add floor 256 div} def
+ f0 aload pop
+ dup 255 ge {pop 1}
+ {dup 0 le {pop 0}
+ {255 div 
+ } ifelse
+ } ifelse
+ 0 1 3 2 roll limit rnd
+ end
+ } bind aload pop] cvx readonly
+ /Function defineRes pop
+ 
+ /N115 <~It)rtIt)rtIt)rtIt)rtIt)rtIt)rtIt)rtIt)rtIt)rtIt)rtIt)rtIt)rtIt)rt
+ It)rtIt)rtIt)rtIt)rtIt)rtIt)rtIt)rtIt)rtIt)rtIt)rtIt)rtIt)rtIt)rt
+ It)rtIt)rtIt)rtIt)rtIt)rtIt)rtIt)rtIt)rtIt)rtIt)rtIt)rtIt)rtIt)rt
+ It)rtIt)rtIt)rtIt)rtIt)rtIt)rtIt)rtIt)rtIt)rtIt)rtIt)rtIt)rtIt)rt
+ It)rtIt)rtIt)rtIt)rtIt)rtIt)rtIt)rtIt)rtIt)rtIt)rtIt)rtIt)rt~> 15 dict begin
+ /Sample exch def
+ currentdict end
+ [exch {begin
+ /_x0 exch def
+ /_tmp0 _x0
+ dup 1 ge {pop 255}
+ {dup 0 le {pop 0}
+ {255 mul 
+ } ifelse
+ } ifelse
+ def
+ /min0 _tmp0 cvi def
+ /max0 _tmp0 ceiling cvi def
+ /f0
+ min0 max0 eq
+ {{min0 f1}}
+ {{
+ [min0 f1 max0 f1
+ 0 1 0 {dup 3 index exch get exch 2 index exch get
+ _tmp0 min0 max0 5 3 roll int
+ 3 1 roll} for pop pop]
+ }} ifelse
+ def
+ /f1
+ {/prm0 exch def [
+  0 255 prm0 limit 8 mul -3 bitshift Sample exch get ]} def
+ /rnd {256 mul 0.5 add floor 256 div} def
+ f0 aload pop
+ dup 255 ge {pop 1.00787}
+ {dup 0 le {pop -1}
+ {2.00787 255 div mul 1 sub 
+ } ifelse
+ } ifelse
+ -1 1 3 2 roll limit rnd
+ end
+ } bind aload pop] cvx readonly
+ /Function defineRes pop
+ 
+ /N114 <~zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz~> 15 dict begin
+ /Sample exch def
+ currentdict end
+ [exch {begin
+ /_x0 exch def
+ /_tmp0 _x0
+ dup 1 ge {pop 255}
+ {dup 0 le {pop 0}
+ {255 mul 
+ } ifelse
+ } ifelse
+ def
+ /min0 _tmp0 cvi def
+ /max0 _tmp0 ceiling cvi def
+ /f0
+ min0 max0 eq
+ {{min0 f1}}
+ {{
+ [min0 f1 max0 f1
+ 0 1 0 {dup 3 index exch get exch 2 index exch get
+ _tmp0 min0 max0 5 3 roll int
+ 3 1 roll} for pop pop]
+ }} ifelse
+ def
+ /f1
+ {/prm0 exch def [
+  0 255 prm0 limit 8 mul -3 bitshift Sample exch get ]} def
+ /rnd {256 mul 0.5 add floor 256 div} def
+ f0 aload pop
+ dup 255 ge {pop 1}
+ {dup 0 le {pop 0}
+ {255 div 
+ } ifelse
+ } ifelse
+ 0 1 3 2 roll limit rnd
+ end
+ } bind aload pop] cvx readonly
+ /Function defineRes pop
+ 
+ /N118 <~It)rtIt)rtIt)rtIt)rtIt)rtIt)rtIt)rtIt)rtIt)rtIt)rtIt)rtIt)rtIt)rt
+ It)rtIt)rtIt)rtIt)rtIt)rtIt)rtIt)rtIt)rtIt)rtIt)rtIt)rtIt)rtIt)rt
+ It)rtIt)rtIt)rtIt)rtIt)rtIt)rtIt)rtIt)rtIt)rtIt)rtIt)rtIt)rtIt)rt
+ It)rtIt)rtIt)rtIt)rtIt)rtIt)rtIt)rtIt)rtIt)rtIt)rtIt)rtIt)rtIt)rt
+ It)rtIt)rtIt)rtIt)rtIt)rtIt)rtIt)rtIt)rtIt)rtIt)rtIt)rtIt)rt~> 15 dict begin
+ /Sample exch def
+ currentdict end
+ [exch {begin
+ /_x0 exch def
+ /_tmp0 _x0
+ dup 1 ge {pop 255}
+ {dup 0 le {pop 0}
+ {255 mul 
+ } ifelse
+ } ifelse
+ def
+ /min0 _tmp0 cvi def
+ /max0 _tmp0 ceiling cvi def
+ /f0
+ min0 max0 eq
+ {{min0 f1}}
+ {{
+ [min0 f1 max0 f1
+ 0 1 0 {dup 3 index exch get exch 2 index exch get
+ _tmp0 min0 max0 5 3 roll int
+ 3 1 roll} for pop pop]
+ }} ifelse
+ def
+ /f1
+ {/prm0 exch def [
+  0 255 prm0 limit 8 mul -3 bitshift Sample exch get ]} def
+ /rnd {256 mul 0.5 add floor 256 div} def
+ f0 aload pop
+ dup 255 ge {pop 1.00787}
+ {dup 0 le {pop -1}
+ {2.00787 255 div mul 1 sub 
+ } ifelse
+ } ifelse
+ -1 1 3 2 roll limit rnd
+ end
+ } bind aload pop] cvx readonly
+ /Function defineRes pop
+ 
+ /N117 <~zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz~> 15 dict begin
+ /Sample exch def
+ currentdict end
+ [exch {begin
+ /_x0 exch def
+ /_tmp0 _x0
+ dup 1 ge {pop 255}
+ {dup 0 le {pop 0}
+ {255 mul 
+ } ifelse
+ } ifelse
+ def
+ /min0 _tmp0 cvi def
+ /max0 _tmp0 ceiling cvi def
+ /f0
+ min0 max0 eq
+ {{min0 f1}}
+ {{
+ [min0 f1 max0 f1
+ 0 1 0 {dup 3 index exch get exch 2 index exch get
+ _tmp0 min0 max0 5 3 roll int
+ 3 1 roll} for pop pop]
+ }} ifelse
+ def
+ /f1
+ {/prm0 exch def [
+  0 255 prm0 limit 8 mul -3 bitshift Sample exch get ]} def
+ /rnd {256 mul 0.5 add floor 256 div} def
+ f0 aload pop
+ dup 255 ge {pop 1}
+ {dup 0 le {pop 0}
+ {255 div 
+ } ifelse
+ } ifelse
+ 0 1 3 2 roll limit rnd
+ end
+ } bind aload pop] cvx readonly
+ /Function defineRes pop
+ 
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+ Q
+ Q
+ PDFVars/TermAll get exec end end
+ userdict /pgsave get restore
+ showpage
+ %%PageTrailer
+ %%EndPage
+ %%Trailer
+ %%DocumentProcessColors: Cyan Magenta Yellow Black
+ %%DocumentNeededResources:
+ %%+ font Times-Bold
+ %%+ font Times-Italic
+ %%+ font Helvetica
+ %%+ font Helvetica-Bold
+ %%+ font Times-Roman
+ %%EOF


Index: llvm-www/pubs/2005-06-12-MSP-PointerCompSlides.pdf


Index: llvm-www/pubs/2005-06-12-MSP-PointerCompSlides.ppt


Index: llvm-www/pubs/index.html
diff -u llvm-www/pubs/index.html:1.19 llvm-www/pubs/index.html:1.20
--- llvm-www/pubs/index.html:1.19	Sun May 15 11:19:01 2005
+++ llvm-www/pubs/index.html	Wed Jun 15 14:18:31 2005
@@ -59,7 +59,15 @@
 Chris Lattner and Vikram Adve.  Proc. of the 2005 <a 
 href="http://research.ihost.com/pldi2005/">ACM SIGPLAN Conference on
 Programming Language Design and Implementation</a> (PLDI'05), Chicago, Illinois,
-Jun, 2005.</li>
+June, 2005.<br>
+<b>Received PLDI 2005 Best Paper Award.</b></li>
+
+<li>"<a href="2005-06-12-MSP-PointerComp.html">Transparent Pointer Compression 
+for Linked Data Structures</a>"<br>
+Chris Lattner and Vikram Adve.  Proceedings of the <a 
+href="http://research.microsoft.com/~zorn/MSP05/home.htm">ACM Workshop on 
+Memory System Performance</a> (MSP'05), Chicago, Illinois, June, 2005.
+</li>
 
 <li>"<a href="2005-02-TECS-SAFECode.html">Memory Safety Without
     Garbage Collection for Embedded Applications</a>"<br> Dinakar





From lattner at cs.uiuc.edu  Wed Jun 15 14:19:01 2005
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Wed, 15 Jun 2005 14:19:01 -0500
Subject: [llvm-commits] CVS: llvm-www/pubs/2005-05-21-PLDI-PoolAlloc.html 
Message-ID: <200506151919.OAA19966@zion.cs.uiuc.edu>



Changes in directory llvm-www/pubs:

2005-05-21-PLDI-PoolAlloc.html updated: 1.4 -> 1.5
---
Log message:

Fix validation error


---
Diffs of the changes:  (+2 -2)

 2005-05-21-PLDI-PoolAlloc.html |    4 ++--
 1 files changed, 2 insertions(+), 2 deletions(-)


Index: llvm-www/pubs/2005-05-21-PLDI-PoolAlloc.html
diff -u llvm-www/pubs/2005-05-21-PLDI-PoolAlloc.html:1.4 llvm-www/pubs/2005-05-21-PLDI-PoolAlloc.html:1.5
--- llvm-www/pubs/2005-05-21-PLDI-PoolAlloc.html:1.4	Wed Jun 15 14:01:48 2005
+++ llvm-www/pubs/2005-05-21-PLDI-PoolAlloc.html	Wed Jun 15 14:18:19 2005
@@ -62,9 +62,9 @@
       Heap</a> (PDF)</li>
 </ul>
 <h3>Slides:</h3>
+<p>Note, animations do not work in PDF version.  Please use PPT version if
+   possible.</p>
 <ul>
-  <p>Note, animations do not work in PDF version.  Please use PPT version if
-     possible.</p>
   <li><a href="2005-06-13-PLDI-PoolAllocSlides.ppt">Automatic Pool Allocation: 
       Improving Performance by Controlling Data Structure Layout in the 
       Heap - Slides</a> (PPT)</li>





From lattner at cs.uiuc.edu  Wed Jun 15 15:52:50 2005
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Wed, 15 Jun 2005 15:52:50 -0500
Subject: [llvm-commits] 
	CVS: llvm/test/Regression/Transforms/InstCombine/2005-06-15-ShiftSetCCCrash.ll
Message-ID: <200506152052.PAA31506@zion.cs.uiuc.edu>



Changes in directory llvm/test/Regression/Transforms/InstCombine:

2005-06-15-ShiftSetCCCrash.ll added (r1.1)
---
Log message:

new testcase for PR577: http://llvm.cs.uiuc.edu/PR577 


---
Diffs of the changes:  (+8 -0)

 2005-06-15-ShiftSetCCCrash.ll |    8 ++++++++
 1 files changed, 8 insertions(+)


Index: llvm/test/Regression/Transforms/InstCombine/2005-06-15-ShiftSetCCCrash.ll
diff -c /dev/null llvm/test/Regression/Transforms/InstCombine/2005-06-15-ShiftSetCCCrash.ll:1.1
*** /dev/null	Wed Jun 15 15:52:49 2005
--- llvm/test/Regression/Transforms/InstCombine/2005-06-15-ShiftSetCCCrash.ll	Wed Jun 15 15:52:39 2005
***************
*** 0 ****
--- 1,8 ----
+ ; RUN: llvm-as < %s | opt -instcombine -disable-output
+ ; PR577
+ 
+ bool %test() {
+ 	%tmp.3 = shl int 0, ubyte 41		; <int> [#uses=1]
+ 	%tmp.4 = setne int %tmp.3, 0		; <bool> [#uses=1]
+ 	ret bool %tmp.4
+ }





From lattner at cs.uiuc.edu  Wed Jun 15 15:53:42 2005
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Wed, 15 Jun 2005 15:53:42 -0500
Subject: [llvm-commits] 
	CVS: llvm/lib/Transforms/Scalar/InstructionCombining.cpp
Message-ID: <200506152053.PAA31523@zion.cs.uiuc.edu>



Changes in directory llvm/lib/Transforms/Scalar:

InstructionCombining.cpp updated: 1.348 -> 1.349
---
Log message:

Fix PR577: http://llvm.cs.uiuc.edu/PR577  and testcase InstCombine/2005-06-15-ShiftSetCCCrash.ll.
Do not perform undefined out of range shifts.


---
Diffs of the changes:  (+16 -2)

 InstructionCombining.cpp |   18 ++++++++++++++++--
 1 files changed, 16 insertions(+), 2 deletions(-)


Index: llvm/lib/Transforms/Scalar/InstructionCombining.cpp
diff -u llvm/lib/Transforms/Scalar/InstructionCombining.cpp:1.348 llvm/lib/Transforms/Scalar/InstructionCombining.cpp:1.349
--- llvm/lib/Transforms/Scalar/InstructionCombining.cpp:1.348	Wed Jun 15 13:25:30 2005
+++ llvm/lib/Transforms/Scalar/InstructionCombining.cpp	Wed Jun 15 15:53:31 2005
@@ -2560,6 +2560,14 @@
           default: break;
           case Instruction::SetEQ:
           case Instruction::SetNE: {
+            unsigned TypeBits = CI->getType()->getPrimitiveSizeInBits();
+
+            // Check that the shift amount is in range.  If not, don't perform
+            // undefined shifts.  When the shift is visited it will be
+            // simplified.
+            if (ShAmt->getValue() >= TypeBits)
+              break;
+
             // If we are comparing against bits always shifted out, the
             // comparison cannot succeed.
             Constant *Comp =
@@ -2573,7 +2581,6 @@
             if (LHSI->hasOneUse()) {
               // Otherwise strength reduce the shift into an and.
               unsigned ShAmtVal = (unsigned)ShAmt->getValue();
-              unsigned TypeBits = CI->getType()->getPrimitiveSizeInBits();
               uint64_t Val = (1ULL << (TypeBits-ShAmtVal))-1;
 
               Constant *Mask;
@@ -2603,6 +2610,14 @@
           default: break;
           case Instruction::SetEQ:
           case Instruction::SetNE: {
+
+            // Check that the shift amount is in range.  If not, don't perform
+            // undefined shifts.  When the shift is visited it will be
+            // simplified.
+            unsigned TypeBits = ShAmt->getType()->getPrimitiveSizeInBits();
+            if (ShAmt->getValue() >= TypeBits)
+              break;
+
             // If we are comparing against bits always shifted out, the
             // comparison cannot succeed.
             Constant *Comp =
@@ -2623,7 +2638,6 @@
 
               Constant *Mask;
               if (CI->getType()->isUnsigned()) {
-                unsigned TypeBits = CI->getType()->getPrimitiveSizeInBits();
                 Val &= ~0ULL >> (64-TypeBits);
                 Mask = ConstantUInt::get(CI->getType(), Val);
               } else {





From lattner at cs.uiuc.edu  Wed Jun 15 16:11:30 2005
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Wed, 15 Jun 2005 16:11:30 -0500
Subject: [llvm-commits] 
	CVS: llvm/test/Regression/Transforms/GlobalOpt/2005-06-15-LocalizeConstExprCrash.ll
Message-ID: <200506152111.QAA32109@zion.cs.uiuc.edu>



Changes in directory llvm/test/Regression/Transforms/GlobalOpt:

2005-06-15-LocalizeConstExprCrash.ll added (r1.1)
---
Log message:

new testcase for PR579: http://llvm.cs.uiuc.edu/PR579 


---
Diffs of the changes:  (+9 -0)

 2005-06-15-LocalizeConstExprCrash.ll |    9 +++++++++
 1 files changed, 9 insertions(+)


Index: llvm/test/Regression/Transforms/GlobalOpt/2005-06-15-LocalizeConstExprCrash.ll
diff -c /dev/null llvm/test/Regression/Transforms/GlobalOpt/2005-06-15-LocalizeConstExprCrash.ll:1.1
*** /dev/null	Wed Jun 15 16:11:28 2005
--- llvm/test/Regression/Transforms/GlobalOpt/2005-06-15-LocalizeConstExprCrash.ll	Wed Jun 15 16:11:18 2005
***************
*** 0 ****
--- 1,9 ----
+ ; RUN: llvm-as < %s | opt -globalopt -disable-output
+ ; PR579
+ 
+ %g_40507551 = internal global short 31038		; <short*> [#uses=1]
+ 
+ void %main() {
+ 	%tmp.4.i.1 = load ubyte* getelementptr (ubyte* cast (short* %g_40507551 to ubyte*), int 1)
+ 	ret void
+ }





From lattner at cs.uiuc.edu  Wed Jun 15 16:11:59 2005
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Wed, 15 Jun 2005 16:11:59 -0500
Subject: [llvm-commits] CVS: llvm/lib/Transforms/IPO/GlobalOpt.cpp 
Message-ID: <200506152111.QAA32120@zion.cs.uiuc.edu>



Changes in directory llvm/lib/Transforms/IPO:

GlobalOpt.cpp updated: 1.40 -> 1.41
---
Log message:

Do not promote globals only used by main to locals if there are constantexprs
or other uses hanging off of them.


---
Diffs of the changes:  (+11 -3)

 GlobalOpt.cpp |   14 +++++++++++---
 1 files changed, 11 insertions(+), 3 deletions(-)


Index: llvm/lib/Transforms/IPO/GlobalOpt.cpp
diff -u llvm/lib/Transforms/IPO/GlobalOpt.cpp:1.40 llvm/lib/Transforms/IPO/GlobalOpt.cpp:1.41
--- llvm/lib/Transforms/IPO/GlobalOpt.cpp:1.40	Sun May  8 17:18:06 2005
+++ llvm/lib/Transforms/IPO/GlobalOpt.cpp	Wed Jun 15 16:11:48 2005
@@ -104,6 +104,10 @@
   Function *AccessingFunction;
   bool HasMultipleAccessingFunctions;
 
+  // HasNonInstructionUser - Set to true if this global has a user that is not
+  // an instruction (e.g. a constant expr or GV initializer).
+  bool HasNonInstructionUser;
+
   /// isNotSuitableForSRA - Keep track of whether any SRA preventing users of
   /// the global exist.  Such users include GEP instruction with variable
   /// indexes, and non-gep/load/store users like constant expr casts.
@@ -111,7 +115,7 @@
 
   GlobalStatus() : isLoaded(false), StoredType(NotStored), StoredOnceValue(0),
                    AccessingFunction(0), HasMultipleAccessingFunctions(false),
-                   isNotSuitableForSRA(false) {}
+                   HasNonInstructionUser(false), isNotSuitableForSRA(false) {}
 };
 
 
@@ -140,6 +144,8 @@
                           std::set<PHINode*> &PHIUsers) {
   for (Value::use_iterator UI = V->use_begin(), E = V->use_end(); UI != E; ++UI)
     if (ConstantExpr *CE = dyn_cast<ConstantExpr>(*UI)) {
+      GS.HasNonInstructionUser = true;
+
       if (AnalyzeGlobal(CE, GS, PHIUsers)) return true;
       if (CE->getOpcode() != Instruction::GetElementPtr)
         GS.isNotSuitableForSRA = true;
@@ -241,11 +247,13 @@
         return true;  // Any other non-load instruction might take address!
       }
     } else if (Constant *C = dyn_cast<Constant>(*UI)) {
+      GS.HasNonInstructionUser = true;
       // We might have a dead and dangling constant hanging off of here.
       if (!ConstantIsDead(C))
         return true;
     } else {
-      // Otherwise must be a global or some other user.
+      GS.HasNonInstructionUser = true;
+      // Otherwise must be some other user.
       return true;
     }
 
@@ -940,7 +948,7 @@
     // NOTE: It doesn't make sense to promote non first class types since we
     // are just replacing static memory to stack memory.
     if (!GS.HasMultipleAccessingFunctions &&
-        GS.AccessingFunction &&
+        GS.AccessingFunction && !GS.HasNonInstructionUser &&
         GV->getType()->getElementType()->isFirstClassType() &&
         GS.AccessingFunction->getName() == "main" &&
         GS.AccessingFunction->hasExternalLinkage()) {





From lattner at cs.uiuc.edu  Wed Jun 15 16:29:06 2005
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Wed, 15 Jun 2005 16:29:06 -0500
Subject: [llvm-commits] 
	CVS: llvm/test/Regression/Transforms/IndVarsSimplify/2005-06-15-InstMoveCrash.ll
Message-ID: <200506152129.QAA00545@zion.cs.uiuc.edu>



Changes in directory llvm/test/Regression/Transforms/IndVarsSimplify:

2005-06-15-InstMoveCrash.ll added (r1.1)
---
Log message:

new testcase for PR582: http://llvm.cs.uiuc.edu/PR582 


---
Diffs of the changes:  (+36 -0)

 2005-06-15-InstMoveCrash.ll |   36 ++++++++++++++++++++++++++++++++++++
 1 files changed, 36 insertions(+)


Index: llvm/test/Regression/Transforms/IndVarsSimplify/2005-06-15-InstMoveCrash.ll
diff -c /dev/null llvm/test/Regression/Transforms/IndVarsSimplify/2005-06-15-InstMoveCrash.ll:1.1
*** /dev/null	Wed Jun 15 16:29:05 2005
--- llvm/test/Regression/Transforms/IndVarsSimplify/2005-06-15-InstMoveCrash.ll	Wed Jun 15 16:28:55 2005
***************
*** 0 ****
--- 1,36 ----
+ ; RUN: llvm-as < %s | opt -indvars -disable-output
+ 
+ void %main() {
+ entry:
+ 	br label %no_exit.1.outer
+ 
+ no_exit.1.outer:		; preds = %endif.0, %entry
+ 	%l_14237116.1.0.ph = phi sbyte [ -46, %entry ], [ 0, %endif.0 ]		; <sbyte> [#uses=1]
+ 	%i.0.0.0.ph = phi int [ 0, %entry ], [ %inc.1, %endif.0 ]		; <int> [#uses=1]
+ 	br label %no_exit.1
+ 
+ no_exit.1:		; preds = %_Z13func_47880058cc.exit, %no_exit.1.outer
+ 	br bool false, label %_Z13func_47880058cc.exit, label %then.i
+ 
+ then.i:		; preds = %no_exit.1
+ 	br label %_Z13func_47880058cc.exit
+ 
+ _Z13func_47880058cc.exit:		; preds = %then.i, %no_exit.1
+ 	br bool false, label %then.0, label %no_exit.1
+ 
+ then.0:		; preds = %_Z13func_47880058cc.exit
+ 	%tmp.6 = cast sbyte %l_14237116.1.0.ph to ubyte		; <ubyte> [#uses=1]
+ 	br bool false, label %endif.0, label %then.1
+ 
+ then.1:		; preds = %then.0
+ 	br label %endif.0
+ 
+ endif.0:		; preds = %then.1, %then.0
+ 	%inc.1 = add int %i.0.0.0.ph, 1		; <int> [#uses=2]
+ 	%tmp.2 = setgt int %inc.1, 99		; <bool> [#uses=1]
+ 	br bool %tmp.2, label %loopexit.0, label %no_exit.1.outer
+ 
+ loopexit.0:		; preds = %endif.0
+ 	%tmp.28 = cast ubyte %tmp.6 to uint		; <uint> [#uses=0]
+ 	ret void
+ }





From lattner at cs.uiuc.edu  Wed Jun 15 16:29:47 2005
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Wed, 15 Jun 2005 16:29:47 -0500
Subject: [llvm-commits] CVS: llvm/lib/Transforms/Scalar/IndVarSimplify.cpp 
Message-ID: <200506152129.QAA00554@zion.cs.uiuc.edu>



Changes in directory llvm/lib/Transforms/Scalar:

IndVarSimplify.cpp updated: 1.77 -> 1.78
---
Log message:

Fix PR582: http://llvm.cs.uiuc.edu/PR582 .  The rewriter can move casts around, which invalidated the 
BB iterator.  This fixes Transforms/IndVarsSimplify/2005-06-15-InstMoveCrash.ll


---
Diffs of the changes:  (+11 -1)

 IndVarSimplify.cpp |   12 +++++++++++-
 1 files changed, 11 insertions(+), 1 deletion(-)


Index: llvm/lib/Transforms/Scalar/IndVarSimplify.cpp
diff -u llvm/lib/Transforms/Scalar/IndVarSimplify.cpp:1.77 llvm/lib/Transforms/Scalar/IndVarSimplify.cpp:1.78
--- llvm/lib/Transforms/Scalar/IndVarSimplify.cpp:1.77	Thu Apr 21 18:45:12 2005
+++ llvm/lib/Transforms/Scalar/IndVarSimplify.cpp	Wed Jun 15 16:29:31 2005
@@ -551,7 +551,7 @@
   for (unsigned i = 0, e = L->getBlocks().size(); i != e; ++i)
     if (LI->getLoopFor(L->getBlocks()[i]) == L) {  // Not in a subloop...
       BasicBlock *BB = L->getBlocks()[i];
-      for (BasicBlock::iterator I = BB->begin(), E = BB->end(); I != E; ++I)
+      for (BasicBlock::iterator I = BB->begin(), E = BB->end(); I != E;) {
         if (I->getType()->isInteger()) {      // Is an integer instruction
           SCEVHandle SH = SE->getSCEV(I);
           if (SH->hasComputableLoopEvolution(L) ||    // Varies predictably
@@ -571,6 +571,10 @@
               if (!isa<SCEVCouldNotCompute>(ExitValue)) {
                 Changed = true;
                 ++NumReplaced;
+                // Remember the next instruction.  The rewriter can move code
+                // around in some cases.
+                BasicBlock::iterator NextI = I; ++NextI;
+
                 Value *NewVal = Rewriter.expandCodeFor(ExitValue, InsertPt,
                                                        I->getType());
 
@@ -582,10 +586,16 @@
                 // If this instruction is dead now, schedule it to be removed.
                 if (I->use_empty())
                   InstructionsToDelete.insert(I);
+                I = NextI;
+                continue;  // Skip the ++I
               }
             }
           }
         }
+
+        // Next instruction.  Continue instruction skips this.
+        ++I;
+      }
     }
 
   DeleteTriviallyDeadInstructions(InstructionsToDelete);





From lattner at cs.uiuc.edu  Wed Jun 15 17:43:04 2005
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Wed, 15 Jun 2005 17:43:04 -0500
Subject: [llvm-commits] 
	CVS: llvm/test/Regression/CFrontend/2005-06-15-ExpandGotoInternalProblem.c
Message-ID: <200506152243.RAA01679@zion.cs.uiuc.edu>



Changes in directory llvm/test/Regression/CFrontend:

2005-06-15-ExpandGotoInternalProblem.c added (r1.1)
---
Log message:

new testcase for PR580: http://llvm.cs.uiuc.edu/PR580 


---
Diffs of the changes:  (+13 -0)

 2005-06-15-ExpandGotoInternalProblem.c |   13 +++++++++++++
 1 files changed, 13 insertions(+)


Index: llvm/test/Regression/CFrontend/2005-06-15-ExpandGotoInternalProblem.c
diff -c /dev/null llvm/test/Regression/CFrontend/2005-06-15-ExpandGotoInternalProblem.c:1.1
*** /dev/null	Wed Jun 15 17:43:03 2005
--- llvm/test/Regression/CFrontend/2005-06-15-ExpandGotoInternalProblem.c	Wed Jun 15 17:42:53 2005
***************
*** 0 ****
--- 1,13 ----
+ // RUN: %llvmgcc -std=c99 %s -S -o - | gccas -o /dev/null
+ // PR580
+ 
+ int X, Y;
+ int foo() {
+   int i;
+         for (i=0; i<100; i++ )
+         {
+                 break;
+                 i = ( X || Y ) ;
+         }
+ }
+ 





From lattner at cs.uiuc.edu  Wed Jun 15 17:44:38 2005
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Wed, 15 Jun 2005 17:44:38 -0500
Subject: [llvm-commits] CVS: llvm-gcc/gcc/llvm-expand.c 
Message-ID: <200506152244.RAA01692@zion.cs.uiuc.edu>



Changes in directory llvm-gcc/gcc:

llvm-expand.c updated: 1.100 -> 1.101
---
Log message:

Rename to llvm_expand_exit_something -> llvm_expand_break_something, as it
inserts code for the 'break' statement.

Fix PR580: http://llvm.cs.uiuc.edu/PR580  by always emitting a new label after emitting an unconditional goto.
This fixes PR580: http://llvm.cs.uiuc.edu/PR580 , including cases where the continue is replaced with a 
break or a goto.

Testcase here: Regression/CFrontend/2005-06-15-ExpandGotoInternalProblem.c



---
Diffs of the changes:  (+29 -7)

 llvm-expand.c |   36 +++++++++++++++++++++++++++++-------
 1 files changed, 29 insertions(+), 7 deletions(-)


Index: llvm-gcc/gcc/llvm-expand.c
diff -u llvm-gcc/gcc/llvm-expand.c:1.100 llvm-gcc/gcc/llvm-expand.c:1.101
--- llvm-gcc/gcc/llvm-expand.c:1.100	Tue Jun 14 16:40:55 2005
+++ llvm-gcc/gcc/llvm-expand.c	Wed Jun 15 17:44:27 2005
@@ -1566,7 +1566,7 @@
 /* Generate LLVM for the start of an if-then.  COND is the expression whose
    truth should be tested.
 
-   If EXITFLAG is nonzero, this conditional is visible to `exit_something'.  */
+   If EXITFLAG is nonzero, this conditional is visible to `break_something'.  */
 
 static void llvm_expand_start_cond (llvm_function *Fn, tree cond, int exitflag,
                                     int has_else) {
@@ -1825,7 +1825,7 @@
 }
 
 /* Generate RTL for the start of a loop.  EXIT_FLAG is nonzero if this
-   loop should be exited by `exit_something'.  This is a loop for which
+   loop should be exited by `break_something'.  This is a loop for which
    `expand_continue' will jump to the top of the loop.
 
    Make an entry on loop_stack to record the labels associated with
@@ -1917,6 +1917,12 @@
 
   whichloop->x.loop.ContinueFound = 1;
   llvm_expand_goto_internal(Fn, whichloop->x.loop.continue_label, 1, 0);
+
+  /* Start a new block so that if statements are emitted after the continue,
+   * that they will have the correct "current block".
+   */
+  llvm_emit_label(Fn, llvm_basicblock_new("dead_block_after_continue"));
+
   return 1;
 }
 
@@ -1992,12 +1998,17 @@
    If not currently inside anything that can be exited,
    return 0 and do nothing; caller will print an error message.  */
 
-static int llvm_expand_exit_something(llvm_function *Fn) {
+static int llvm_expand_break_something(llvm_function *Fn) {
   llvm_nesting *n;
   for (n = Fn->ExpandInfo->InnermostScope; n; n = n->all)
     if (n->exit_block) {
       n->BreakFound = 1;
       llvm_expand_goto_internal(Fn, n->exit_block, 1, 0);
+
+      /* Start a new block so that if statements are emitted after the break,
+       * that they will have the correct "current block".
+       */
+      llvm_emit_label(Fn, llvm_basicblock_new("dead_block_after_break"));
       return 1;
     }
 
@@ -2010,8 +2021,8 @@
    case-labels that are seen and to record the labels generated for the
    statement.
 
-   EXIT_FLAG is nonzero if `exit_something' should exit this case stmt.
-   Otherwise, this construct is transparent for `exit_something'.
+   EXIT_FLAG is nonzero if `break_something' should exit this case stmt.
+   Otherwise, this construct is transparent for `break_something'.
 
    EXPR is the index-expression to be dispatched on.
 */
@@ -2208,14 +2219,25 @@
     append_inst(Fn, create_store_inst(V, Fn->ExpandInfo->IndirectGotoValue, 0));
 
     /* FIXME: This is HORRIBLY INCORRECT in the presence of exception handlers.
-     * There should be one collector block per cleanup level!
+     * There should be one collector block per cleanup level!  Note that
+     * standard GCC gets this wrong as well.
      */
     llvm_expand_goto_internal(Fn, Fn->ExpandInfo->IndirectGotoBlock, 1, 0);
+
+    /* Start a new block so that if statements are emitted after the goto, that
+     * they will have the correct "current block".
+     */
+    llvm_emit_label(Fn, llvm_basicblock_new("dead_block_after_goto"));
     return;
   }
 
   TREE_USED(dest) = 1;
   llvm_expand_goto_internal(Fn, getLabelDeclBlock(dest), 1, 0);
+
+  /* Start a new block so that if statements are emitted after the goto, that
+   * they will have the correct "current block".
+   */
+  llvm_emit_label(Fn, llvm_basicblock_new("dead_block_after_goto"));
 }
 
 /* Generate LLVM code for a RETURN_STMT */
@@ -2766,7 +2788,7 @@
       break;
 
     case BREAK_STMT:
-      if (!llvm_expand_exit_something(Fn))
+      if (!llvm_expand_break_something(Fn))
         error ("break statement not within loop or switch");
       break;
       





From lattner at cs.uiuc.edu  Wed Jun 15 17:49:41 2005
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Wed, 15 Jun 2005 17:49:41 -0500
Subject: [llvm-commits] CVS: llvm/lib/Transforms/IPO/LowerSetJmp.cpp 
Message-ID: <200506152249.RAA01872@zion.cs.uiuc.edu>



Changes in directory llvm/lib/Transforms/IPO:

LowerSetJmp.cpp updated: 1.26 -> 1.27
---
Log message:

Fix PR575: http://llvm.cs.uiuc.edu/PR575 , patch provided by John Mellor-Crummey.  Thanks!



---
Diffs of the changes:  (+1 -0)

 LowerSetJmp.cpp |    1 +
 1 files changed, 1 insertion(+)


Index: llvm/lib/Transforms/IPO/LowerSetJmp.cpp
diff -u llvm/lib/Transforms/IPO/LowerSetJmp.cpp:1.26 llvm/lib/Transforms/IPO/LowerSetJmp.cpp:1.27
--- llvm/lib/Transforms/IPO/LowerSetJmp.cpp:1.26	Wed Jun  8 21:59:00 2005
+++ llvm/lib/Transforms/IPO/LowerSetJmp.cpp	Wed Jun 15 17:49:30 2005
@@ -459,6 +459,7 @@
 
   BasicBlock* NewBB = OldBB->splitBasicBlock(CI);
   assert(NewBB && "Couldn't split BB of \"call\" instruction!!");
+  DFSBlocks.insert(NewBB);
   NewBB->setName("Call2Invoke");
 
   Function* Func = OldBB->getParent();





From lattner at cs.uiuc.edu  Wed Jun 15 20:52:20 2005
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Wed, 15 Jun 2005 20:52:20 -0500
Subject: [llvm-commits] 
	CVS: llvm/lib/Transforms/Scalar/InstructionCombining.cpp
Message-ID: <200506160152.UAA03512@zion.cs.uiuc.edu>



Changes in directory llvm/lib/Transforms/Scalar:

InstructionCombining.cpp updated: 1.349 -> 1.350
---
Log message:

Fix a bug in my previous patch.  Do not get the shift amount type (which
is always ubyte, get the type being shifted).  This unbreaks espresso


---
Diffs of the changes:  (+1 -1)

 InstructionCombining.cpp |    2 +-
 1 files changed, 1 insertion(+), 1 deletion(-)


Index: llvm/lib/Transforms/Scalar/InstructionCombining.cpp
diff -u llvm/lib/Transforms/Scalar/InstructionCombining.cpp:1.349 llvm/lib/Transforms/Scalar/InstructionCombining.cpp:1.350
--- llvm/lib/Transforms/Scalar/InstructionCombining.cpp:1.349	Wed Jun 15 15:53:31 2005
+++ llvm/lib/Transforms/Scalar/InstructionCombining.cpp	Wed Jun 15 20:52:07 2005
@@ -2614,7 +2614,7 @@
             // Check that the shift amount is in range.  If not, don't perform
             // undefined shifts.  When the shift is visited it will be
             // simplified.
-            unsigned TypeBits = ShAmt->getType()->getPrimitiveSizeInBits();
+            unsigned TypeBits = CI->getType()->getPrimitiveSizeInBits();
             if (ShAmt->getValue() >= TypeBits)
               break;
 





From lattner at cs.uiuc.edu  Wed Jun 15 22:00:20 2005
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Wed, 15 Jun 2005 22:00:20 -0500
Subject: [llvm-commits] 
	CVS: llvm/lib/Transforms/Scalar/InstructionCombining.cpp
Message-ID: <200506160300.WAA04006@zion.cs.uiuc.edu>



Changes in directory llvm/lib/Transforms/Scalar:

InstructionCombining.cpp updated: 1.350 -> 1.351
---
Log message:

Fix PR571: http://llvm.cs.uiuc.edu/PR571 , removing code that does just the WRONG thing :)


---
Diffs of the changes:  (+1 -27)

 InstructionCombining.cpp |   28 +---------------------------
 1 files changed, 1 insertion(+), 27 deletions(-)


Index: llvm/lib/Transforms/Scalar/InstructionCombining.cpp
diff -u llvm/lib/Transforms/Scalar/InstructionCombining.cpp:1.350 llvm/lib/Transforms/Scalar/InstructionCombining.cpp:1.351
--- llvm/lib/Transforms/Scalar/InstructionCombining.cpp:1.350	Wed Jun 15 20:52:07 2005
+++ llvm/lib/Transforms/Scalar/InstructionCombining.cpp	Wed Jun 15 22:00:08 2005
@@ -3102,33 +3102,7 @@
     return 0;
   }
 
-  return 0; //The rest of this function is broken.  See bug 571
-
-  // Okay, we have the two reduced sized operands.  If we are doing a <,>
-  // comparison, make sure we perform the compare with the same signedness as
-  // the DestTy.  We don't have to do this if the comparison is !=/== or if the
-  // source is a bool.
-  if (isSignSrc != isSignDest && SrcTy != Type::BoolTy &&
-      SCI.getOpcode() != Instruction::SetEQ &&
-      SCI.getOpcode() != Instruction::SetNE) {
-    // Insert noop casts of the two operands to change the sign of the
-    // comparison.
-    const Type *NewSrcTy;
-    if (isSignDest)
-      NewSrcTy = SrcTy->getSignedVersion();
-    else 
-      NewSrcTy = SrcTy->getUnsignedVersion();
-    
-    // Insert the new casts.
-    LHSCIOp = InsertNewInstBefore(new CastInst(LHSCIOp, NewSrcTy,
-                                               LHSCIOp->getName()), SCI);
-    if (Constant *RHSC = dyn_cast<Constant>(RHSCIOp))
-      RHSCIOp = ConstantExpr::getCast(RHSC, NewSrcTy);
-    else
-      RHSCIOp = InsertNewInstBefore(new CastInst(RHSCIOp, NewSrcTy,
-                                                 RHSCIOp->getName()), SCI);
-  }
-
+  // Okay, just insert a compare of the reduced operands now!
   return BinaryOperator::create(SCI.getOpcode(), LHSCIOp, RHSCIOp);
 }
 





From lattner at cs.uiuc.edu  Wed Jun 15 23:55:40 2005
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Wed, 15 Jun 2005 23:55:40 -0500
Subject: [llvm-commits] 
	CVS: llvm/test/Regression/Transforms/InstCombine/2005-06-15-DivSelectCrash.ll
Message-ID: <200506160455.XAA24216@zion.cs.uiuc.edu>



Changes in directory llvm/test/Regression/Transforms/InstCombine:

2005-06-15-DivSelectCrash.ll added (r1.1)
---
Log message:

new testcase for PR583: http://llvm.cs.uiuc.edu/PR583 


---
Diffs of the changes:  (+9 -0)

 2005-06-15-DivSelectCrash.ll |    9 +++++++++
 1 files changed, 9 insertions(+)


Index: llvm/test/Regression/Transforms/InstCombine/2005-06-15-DivSelectCrash.ll
diff -c /dev/null llvm/test/Regression/Transforms/InstCombine/2005-06-15-DivSelectCrash.ll:1.1
*** /dev/null	Wed Jun 15 23:55:39 2005
--- llvm/test/Regression/Transforms/InstCombine/2005-06-15-DivSelectCrash.ll	Wed Jun 15 23:55:29 2005
***************
*** 0 ****
--- 1,9 ----
+ ; RUN: llvm-as < %s | opt -instcombine -disable-output
+ 
+ int %_Z13func_31585107li(int %l_39521025, int %l_59244666) {
+ 	%shortcirc_val = select bool false, uint 1, uint 0		; <uint> [#uses=1]
+ 	%tmp.8 = div uint 0, %shortcirc_val		; <uint> [#uses=1]
+ 	%tmp.9 = seteq uint %tmp.8, 0		; <bool> [#uses=1]
+ 	%retval = select bool %tmp.9, int %l_59244666, int -1621308501		; <int> [#uses=1]
+ 	ret int %retval
+ }





From lattner at cs.uiuc.edu  Wed Jun 15 23:56:03 2005
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Wed, 15 Jun 2005 23:56:03 -0500
Subject: [llvm-commits] 
	CVS: llvm/lib/Transforms/Scalar/InstructionCombining.cpp
Message-ID: <200506160456.XAA24226@zion.cs.uiuc.edu>



Changes in directory llvm/lib/Transforms/Scalar:

InstructionCombining.cpp updated: 1.351 -> 1.352
---
Log message:

Fix PR583: http://llvm.cs.uiuc.edu/PR583  and testcase Transforms/InstCombine/2005-06-15-DivSelectCrash.ll


---
Diffs of the changes:  (+1 -1)

 InstructionCombining.cpp |    2 +-
 1 files changed, 1 insertion(+), 1 deletion(-)


Index: llvm/lib/Transforms/Scalar/InstructionCombining.cpp
diff -u llvm/lib/Transforms/Scalar/InstructionCombining.cpp:1.351 llvm/lib/Transforms/Scalar/InstructionCombining.cpp:1.352
--- llvm/lib/Transforms/Scalar/InstructionCombining.cpp:1.351	Wed Jun 15 22:00:08 2005
+++ llvm/lib/Transforms/Scalar/InstructionCombining.cpp	Wed Jun 15 23:55:52 2005
@@ -1067,7 +1067,7 @@
           I.setOperand(1, SFO);
           return &I;
         } else if (SFO->getValue() == 0) {
-          I.setOperand(2, STO);
+          I.setOperand(1, STO);
           return &I;
         }
 





From natebegeman at mac.com  Thu Jun 16 02:06:14 2005
From: natebegeman at mac.com (Nate Begeman)
Date: Thu, 16 Jun 2005 02:06:14 -0500
Subject: [llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp 
Message-ID: <200506160706.CAA26941@zion.cs.uiuc.edu>



Changes in directory llvm/lib/CodeGen/SelectionDAG:

SelectionDAG.cpp updated: 1.119 -> 1.120
---
Log message:

Fix bug 537: http://llvm.cs.uiuc.edu/PR537  test 2, which checks to make sure that we fold A+(B-A) -> B for
integer types.  Add a couple checks to not perform these kinds of transform
on floating point values.


---
Diffs of the changes:  (+7 -2)

 SelectionDAG.cpp |    9 +++++++--
 1 files changed, 7 insertions(+), 2 deletions(-)


Index: llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp:1.119 llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp:1.120
--- llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp:1.119	Sun May 15 00:39:08 2005
+++ llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp	Thu Jun 16 02:06:03 2005
@@ -1183,12 +1183,17 @@
     if (N2.getOpcode() == ISD::SUB && isa<ConstantSDNode>(N2.getOperand(0)) &&
         cast<ConstantSDNode>(N2.getOperand(0))->getValue() == 0)
       return getNode(ISD::SUB, VT, N1, N2.getOperand(1)); // A+(0-B) -> A-B
+    if (N2.getOpcode() == ISD::SUB && N1 == N2.Val->getOperand(1) &&
+        !MVT::isFloatingPoint(N2.getValueType()))
+      return N2.Val->getOperand(0); // A+(B-A) -> B
     break;
   case ISD::SUB:
     if (N1.getOpcode() == ISD::ADD) {
-      if (N1.Val->getOperand(0) == N2)
+      if (N1.Val->getOperand(0) == N2 && 
+          !MVT::isFloatingPoint(N2.getValueType()))
         return N1.Val->getOperand(1);         // (A+B)-A == B
-      if (N1.Val->getOperand(1) == N2)
+      if (N1.Val->getOperand(1) == N2 &&
+          !MVT::isFloatingPoint(N2.getValueType()))
         return N1.Val->getOperand(0);         // (A+B)-B == A
     }
     if (N2.getOpcode() == ISD::FNEG)          // (A- (-B) -> A+B





From reid at x10sys.com  Thu Jun 16 02:27:31 2005
From: reid at x10sys.com (Reid Spencer)
Date: Thu, 16 Jun 2005 02:27:31 -0500
Subject: [llvm-commits] CVS: llvm-test/Makefile.programs 
Message-ID: <200506160727.CAA27106@zion.cs.uiuc.edu>



Changes in directory llvm-test:

Makefile.programs updated: 1.155 -> 1.156
---
Log message:

Correct some documentation to reflect reality.


---
Diffs of the changes:  (+1 -1)

 Makefile.programs |    2 +-
 1 files changed, 1 insertion(+), 1 deletion(-)


Index: llvm-test/Makefile.programs
diff -u llvm-test/Makefile.programs:1.155 llvm-test/Makefile.programs:1.156
--- llvm-test/Makefile.programs:1.155	Thu May 12 18:07:00 2005
+++ llvm-test/Makefile.programs	Thu Jun 16 02:27:16 2005
@@ -29,7 +29,7 @@
 #
 # This makefile provides facilities for defining custom tests that are to be run
 # on all of the programs in the test suite.  In order to define one of these
-# tests, create a llvm-test/Makefile.TEST.<testname> file.  This file
+# tests, create a llvm-test/TEST.<testname>.Makefile file.  This file
 # should define a rule 'test.<testname>.%' which is run once for each program in
 # the suite (the % passed in is the program name).  For a simple example, see
 # Makefile.TEST.example.





From lattner at cs.uiuc.edu  Thu Jun 16 20:29:39 2005
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Thu, 16 Jun 2005 20:29:39 -0500
Subject: [llvm-commits] 
	CVS: llvm/lib/Transforms/Scalar/InstructionCombining.cpp
Message-ID: <200506170129.UAA11578@zion.cs.uiuc.edu>



Changes in directory llvm/lib/Transforms/Scalar:

InstructionCombining.cpp updated: 1.352 -> 1.353
---
Log message:

avoid constructing out of range shift amounts.


---
Diffs of the changes:  (+4 -2)

 InstructionCombining.cpp |    6 ++++--
 1 files changed, 4 insertions(+), 2 deletions(-)


Index: llvm/lib/Transforms/Scalar/InstructionCombining.cpp
diff -u llvm/lib/Transforms/Scalar/InstructionCombining.cpp:1.352 llvm/lib/Transforms/Scalar/InstructionCombining.cpp:1.353
--- llvm/lib/Transforms/Scalar/InstructionCombining.cpp:1.352	Wed Jun 15 23:55:52 2005
+++ llvm/lib/Transforms/Scalar/InstructionCombining.cpp	Thu Jun 16 20:29:28 2005
@@ -2511,8 +2511,10 @@
             if (!CanFold) {
               // To test for the bad case of the signed shr, see if any
               // of the bits shifted in could be tested after the mask.
-              Constant *OShAmt = ConstantUInt::get(Type::UByteTy,
-                               Ty->getPrimitiveSizeInBits()-ShAmt->getValue());
+              int ShAmtVal = Ty->getPrimitiveSizeInBits()-ShAmt->getValue();
+              if (ShAmtVal < 0) ShAmtVal = 0; // Out of range shift.
+
+              Constant *OShAmt = ConstantUInt::get(Type::UByteTy, ShAmtVal);
               Constant *ShVal =
                 ConstantExpr::getShl(ConstantInt::getAllOnesValue(Ty), OShAmt);
               if (ConstantExpr::getAnd(ShVal, AndCST)->isNullValue())





From lattner at cs.uiuc.edu  Thu Jun 16 20:45:14 2005
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Thu, 16 Jun 2005 20:45:14 -0500
Subject: [llvm-commits] 
	CVS: llvm/test/Regression/Transforms/SimplifyCFG/2005-06-16-PHICrash.ll
Message-ID: <200506170145.UAA13875@zion.cs.uiuc.edu>



Changes in directory llvm/test/Regression/Transforms/SimplifyCFG:

2005-06-16-PHICrash.ll added (r1.1)
---
Log message:

new testcase for PR584: http://llvm.cs.uiuc.edu/PR584 


---
Diffs of the changes:  (+125 -0)

 2005-06-16-PHICrash.ll |  125 +++++++++++++++++++++++++++++++++++++++++++++++++
 1 files changed, 125 insertions(+)


Index: llvm/test/Regression/Transforms/SimplifyCFG/2005-06-16-PHICrash.ll
diff -c /dev/null llvm/test/Regression/Transforms/SimplifyCFG/2005-06-16-PHICrash.ll:1.1
*** /dev/null	Thu Jun 16 20:45:13 2005
--- llvm/test/Regression/Transforms/SimplifyCFG/2005-06-16-PHICrash.ll	Thu Jun 16 20:45:03 2005
***************
*** 0 ****
--- 1,125 ----
+ ; RUN: llvm-as < %s | opt -simplifycfg -disable-output
+ ; PR584
+ 
+ %g_38098584 = external global uint		; <uint*> [#uses=1]
+ %g_60187400 = external global uint		; <uint*> [#uses=1]
+ %g_59182229 = external global uint		; <uint*> [#uses=2]
+ 
+ implementation   ; Functions:
+ 
+ int %_Z13func_26556482h(ubyte %l_88173906) {
+ entry:
+ 	%tmp.1 = cast ubyte %l_88173906 to sbyte		; <sbyte> [#uses=2]
+ 	%tmp.3 = seteq ubyte %l_88173906, 0		; <bool> [#uses=1]
+ 	br bool %tmp.3, label %else.0, label %then.0
+ 
+ then.0:		; preds = %entry
+ 	%tmp.5 = seteq ubyte %l_88173906, 0		; <bool> [#uses=1]
+ 	br bool %tmp.5, label %else.1, label %then.1
+ 
+ then.1:		; preds = %then.0
+ 	br label %return
+ 
+ else.1:		; preds = %then.0
+ 	br label %loopentry.0
+ 
+ loopentry.0:		; preds = %no_exit.0, %else.1
+ 	%i.0.1 = phi int [ 0, %else.1 ], [ %inc.0, %no_exit.0 ]		; <int> [#uses=2]
+ 	%tmp.9 = setgt int %i.0.1, 99		; <bool> [#uses=1]
+ 	br bool %tmp.9, label %endif.0, label %no_exit.0
+ 
+ no_exit.0:		; preds = %loopentry.0
+ 	%inc.0 = add int %i.0.1, 1		; <int> [#uses=1]
+ 	br label %loopentry.0
+ 
+ else.0:		; preds = %entry
+ 	%tmp.12 = cast sbyte %tmp.1 to int		; <int> [#uses=1]
+ 	br label %return
+ 
+ endif.0:		; preds = %loopentry.0
+ 	%tmp.14 = cast sbyte %tmp.1 to int		; <int> [#uses=1]
+ 	%tmp.16 = cast ubyte %l_88173906 to int		; <int> [#uses=1]
+ 	%tmp.17 = setgt int %tmp.14, %tmp.16		; <bool> [#uses=1]
+ 	%tmp.19 = load uint* %g_59182229		; <uint> [#uses=2]
+ 	br bool %tmp.17, label %cond_true, label %cond_false
+ 
+ cond_true:		; preds = %endif.0
+ 	%tmp.20 = setne uint %tmp.19, 1		; <bool> [#uses=1]
+ 	br label %cond_continue
+ 
+ cond_false:		; preds = %endif.0
+ 	%tmp.22 = setne uint %tmp.19, 0		; <bool> [#uses=1]
+ 	br label %cond_continue
+ 
+ cond_continue:		; preds = %cond_false, %cond_true
+ 	%mem_tmp.0 = phi bool [ %tmp.20, %cond_true ], [ %tmp.22, %cond_false ]		; <bool> [#uses=1]
+ 	br bool %mem_tmp.0, label %then.2, label %else.2
+ 
+ then.2:		; preds = %cond_continue
+ 	%tmp.25 = cast ubyte %l_88173906 to int		; <int> [#uses=1]
+ 	br label %return
+ 
+ else.2:		; preds = %cond_continue
+ 	br label %loopentry.1
+ 
+ loopentry.1:		; preds = %endif.3, %else.2
+ 	%i.1.1 = phi int [ 0, %else.2 ], [ %inc.3, %endif.3 ]		; <int> [#uses=2]
+ 	%i.3.2 = phi int [ undef, %else.2 ], [ %i.3.0, %endif.3 ]		; <int> [#uses=2]
+ 	%l_88173906_addr.1 = phi ubyte [ %l_88173906, %else.2 ], [ %l_88173906_addr.0, %endif.3 ]		; <ubyte> [#uses=3]
+ 	%tmp.29 = setgt int %i.1.1, 99		; <bool> [#uses=1]
+ 	br bool %tmp.29, label %endif.2, label %no_exit.1
+ 
+ no_exit.1:		; preds = %loopentry.1
+ 	%tmp.30 = load uint* %g_38098584		; <uint> [#uses=1]
+ 	%tmp.31 = seteq uint %tmp.30, 0		; <bool> [#uses=1]
+ 	br bool %tmp.31, label %else.3, label %then.3
+ 
+ then.3:		; preds = %no_exit.1
+ 	br label %endif.3
+ 
+ else.3:		; preds = %no_exit.1
+ 	br bool false, label %else.4, label %then.4
+ 
+ then.4:		; preds = %else.3
+ 	br label %endif.3
+ 
+ else.4:		; preds = %else.3
+ 	br bool false, label %else.5, label %then.5
+ 
+ then.5:		; preds = %else.4
+ 	store uint 3290648471, uint* %g_59182229
+ 	br label %return
+ 
+ else.5:		; preds = %else.4
+ 	br label %loopentry.3
+ 
+ loopentry.3:		; preds = %then.7, %else.5
+ 	%i.3.3 = phi int [ 0, %else.5 ], [ %inc.2, %then.7 ]		; <int> [#uses=3]
+ 	%tmp.55 = setgt int %i.3.3, 99		; <bool> [#uses=1]
+ 	br bool %tmp.55, label %endif.3, label %no_exit.3
+ 
+ no_exit.3:		; preds = %loopentry.3
+ 	%tmp.57 = seteq ubyte %l_88173906_addr.1, 0		; <bool> [#uses=1]
+ 	br bool %tmp.57, label %else.7, label %then.7
+ 
+ then.7:		; preds = %no_exit.3
+ 	store uint 16239, uint* %g_60187400
+ 	%inc.2 = add int %i.3.3, 1		; <int> [#uses=1]
+ 	br label %loopentry.3
+ 
+ else.7:		; preds = %no_exit.3
+ 	br label %return
+ 
+ endif.3:		; preds = %loopentry.3, %then.4, %then.3
+ 	%i.3.0 = phi int [ %i.3.2, %then.3 ], [ %i.3.2, %then.4 ], [ %i.3.3, %loopentry.3 ]		; <int> [#uses=1]
+ 	%l_88173906_addr.0 = phi ubyte [ 100, %then.3 ], [ %l_88173906_addr.1, %then.4 ], [ %l_88173906_addr.1, %loopentry.3 ]		; <ubyte> [#uses=1]
+ 	%inc.3 = add int %i.1.1, 1		; <int> [#uses=1]
+ 	br label %loopentry.1
+ 
+ endif.2:		; preds = %loopentry.1
+ 	br label %return
+ 
+ return:		; preds = %endif.2, %else.7, %then.5, %then.2, %else.0, %then.1
+ 	%result.0 = phi int [ 1624650671, %then.1 ], [ %tmp.25, %then.2 ], [ 3379, %then.5 ], [ 52410, %else.7 ], [ -1526438411, %endif.2 ], [ %tmp.12, %else.0 ]		; <int> [#uses=1]
+ 	ret int %result.0
+ }





From lattner at cs.uiuc.edu  Thu Jun 16 20:46:04 2005
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Thu, 16 Jun 2005 20:46:04 -0500
Subject: [llvm-commits] CVS: llvm/lib/Transforms/Utils/SimplifyCFG.cpp 
Message-ID: <200506170146.UAA13887@zion.cs.uiuc.edu>



Changes in directory llvm/lib/Transforms/Utils:

SimplifyCFG.cpp updated: 1.71 -> 1.72
---
Log message:

Don't crash on:  X = phi (X, X).

This fixes PR584: http://llvm.cs.uiuc.edu/PR584  and Transforms/SimplifyCFG/2005-06-16-PHICrash.ll



---
Diffs of the changes:  (+9 -6)

 SimplifyCFG.cpp |   15 +++++++++------
 1 files changed, 9 insertions(+), 6 deletions(-)


Index: llvm/lib/Transforms/Utils/SimplifyCFG.cpp
diff -u llvm/lib/Transforms/Utils/SimplifyCFG.cpp:1.71 llvm/lib/Transforms/Utils/SimplifyCFG.cpp:1.72
--- llvm/lib/Transforms/Utils/SimplifyCFG.cpp:1.71	Fri May 20 17:19:54 2005
+++ llvm/lib/Transforms/Utils/SimplifyCFG.cpp	Thu Jun 16 20:45:53 2005
@@ -1461,12 +1461,15 @@
         BasicBlock::iterator AfterPHIIt = BB->begin();
         while (isa<PHINode>(AfterPHIIt)) {
           PHINode *PN = cast<PHINode>(AfterPHIIt++);
-          if (PN->getIncomingValue(0) == PN->getIncomingValue(1))
-            PN->replaceAllUsesWith(PN->getIncomingValue(0));
-          else if (!DominatesMergePoint(PN->getIncomingValue(0), BB,
-                                        &AggressiveInsts) ||
-                   !DominatesMergePoint(PN->getIncomingValue(1), BB,
-                                        &AggressiveInsts)) {
+          if (PN->getIncomingValue(0) == PN->getIncomingValue(1)) {
+            if (PN->getIncomingValue(0) != PN)
+              PN->replaceAllUsesWith(PN->getIncomingValue(0));
+            else
+              PN->replaceAllUsesWith(UndefValue::get(PN->getType()));
+          } else if (!DominatesMergePoint(PN->getIncomingValue(0), BB,
+                                          &AggressiveInsts) ||
+                     !DominatesMergePoint(PN->getIncomingValue(1), BB,
+                                          &AggressiveInsts)) {
             CanPromote = false;
             break;
           }





From lattner at cs.uiuc.edu  Thu Jun 16 21:04:58 2005
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Thu, 16 Jun 2005 21:04:58 -0500
Subject: [llvm-commits] 
	CVS: llvm/test/Regression/Transforms/InstCombine/2005-06-16-RangeCrash.ll
Message-ID: <200506170204.VAA14458@zion.cs.uiuc.edu>



Changes in directory llvm/test/Regression/Transforms/InstCombine:

2005-06-16-RangeCrash.ll added (r1.1)
---
Log message:

new testcase for PR585: http://llvm.cs.uiuc.edu/PR585 


---
Diffs of the changes:  (+7 -0)

 2005-06-16-RangeCrash.ll |    7 +++++++
 1 files changed, 7 insertions(+)


Index: llvm/test/Regression/Transforms/InstCombine/2005-06-16-RangeCrash.ll
diff -c /dev/null llvm/test/Regression/Transforms/InstCombine/2005-06-16-RangeCrash.ll:1.1
*** /dev/null	Thu Jun 16 21:04:57 2005
--- llvm/test/Regression/Transforms/InstCombine/2005-06-16-RangeCrash.ll	Thu Jun 16 21:04:47 2005
***************
*** 0 ****
--- 1,7 ----
+ ; RUN: llvm-as < %s | opt -instcombine -disable-output
+ ; PR585
+ bool %test() {
+ 	%tmp.26 = div int 0, -2147483648		; <int> [#uses=1]
+ 	%tmp.27 = seteq int %tmp.26, 0		; <bool> [#uses=1]
+ 	ret bool %tmp.27
+ }





From lattner at cs.uiuc.edu  Thu Jun 16 21:06:06 2005
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Thu, 16 Jun 2005 21:06:06 -0500
Subject: [llvm-commits] 
	CVS: llvm/lib/Transforms/Scalar/InstructionCombining.cpp
Message-ID: <200506170206.VAA14471@zion.cs.uiuc.edu>



Changes in directory llvm/lib/Transforms/Scalar:

InstructionCombining.cpp updated: 1.353 -> 1.354
---
Log message:

Don't crash when dealing with INTMIN.  This fixes PR585: http://llvm.cs.uiuc.edu/PR585  and
Transforms/InstCombine/2005-06-16-RangeCrash.ll


---
Diffs of the changes:  (+2 -0)

 InstructionCombining.cpp |    2 ++
 1 files changed, 2 insertions(+)


Index: llvm/lib/Transforms/Scalar/InstructionCombining.cpp
diff -u llvm/lib/Transforms/Scalar/InstructionCombining.cpp:1.353 llvm/lib/Transforms/Scalar/InstructionCombining.cpp:1.354
--- llvm/lib/Transforms/Scalar/InstructionCombining.cpp:1.353	Thu Jun 16 20:29:28 2005
+++ llvm/lib/Transforms/Scalar/InstructionCombining.cpp	Thu Jun 16 21:05:55 2005
@@ -2699,6 +2699,8 @@
             if (CI->isNullValue()) {       // (X / neg) op 0
               LoBound = AddOne(DivRHS);
               HiBound = cast<ConstantInt>(ConstantExpr::getNeg(DivRHS));
+              if (HiBound == DivRHS)
+                LoBound = 0;  // - INTMIN = INTMIN
             } else if (isPositive(CI)) {   // (X / neg) op pos
               HiOverflow = LoOverflow = ProdOV;
               if (!LoOverflow)





From lattner at cs.uiuc.edu  Thu Jun 16 22:58:41 2005
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Thu, 16 Jun 2005 22:58:41 -0500
Subject: [llvm-commits] 
	CVS: llvm/test/Regression/Transforms/InstCombine/2005-06-16-SetCCOrSetCCMiscompile.ll
Message-ID: <200506170358.WAA16530@zion.cs.uiuc.edu>



Changes in directory llvm/test/Regression/Transforms/InstCombine:

2005-06-16-SetCCOrSetCCMiscompile.ll added (r1.1)
---
Log message:

new testcase for PR586: http://llvm.cs.uiuc.edu/PR586 


---
Diffs of the changes:  (+15 -0)

 2005-06-16-SetCCOrSetCCMiscompile.ll |   15 +++++++++++++++
 1 files changed, 15 insertions(+)


Index: llvm/test/Regression/Transforms/InstCombine/2005-06-16-SetCCOrSetCCMiscompile.ll
diff -c /dev/null llvm/test/Regression/Transforms/InstCombine/2005-06-16-SetCCOrSetCCMiscompile.ll:1.1
*** /dev/null	Thu Jun 16 22:58:40 2005
--- llvm/test/Regression/Transforms/InstCombine/2005-06-16-SetCCOrSetCCMiscompile.ll	Thu Jun 16 22:58:30 2005
***************
*** 0 ****
--- 1,15 ----
+ ; RUN: llvm-as < %s | opt -instcombine | llvm-dis | grep 'ret bool true'
+ ; PR586
+ 
+ %g_07918478 = external global uint		; <uint*> [#uses=1]
+ 
+ implementation   ; Functions:
+ 
+ bool %test() {
+ 	%tmp.0 = load uint* %g_07918478		; <uint> [#uses=2]
+ 	%tmp.1 = setne uint %tmp.0, 0		; <bool> [#uses=1]
+ 	%tmp.4 = setlt uint %tmp.0, 4111		; <bool> [#uses=1]
+ 	%bothcond = or bool %tmp.1, %tmp.4		; <bool> [#uses=1]
+ 	ret bool %bothcond
+ }
+ 





From lattner at cs.uiuc.edu  Thu Jun 16 22:59:28 2005
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Thu, 16 Jun 2005 22:59:28 -0500
Subject: [llvm-commits] 
	CVS: llvm/lib/Transforms/Scalar/InstructionCombining.cpp
Message-ID: <200506170359.WAA16543@zion.cs.uiuc.edu>



Changes in directory llvm/lib/Transforms/Scalar:

InstructionCombining.cpp updated: 1.354 -> 1.355
---
Log message:

This is not true: (X != 13 | X < 15) -> X < 15

It is actually always true.  This fixes PR586: http://llvm.cs.uiuc.edu/PR586  and 
Transforms/InstCombine/2005-06-16-SetCCOrSetCCMiscompile.ll



---
Diffs of the changes:  (+1 -2)

 InstructionCombining.cpp |    3 +--
 1 files changed, 1 insertion(+), 2 deletions(-)


Index: llvm/lib/Transforms/Scalar/InstructionCombining.cpp
diff -u llvm/lib/Transforms/Scalar/InstructionCombining.cpp:1.354 llvm/lib/Transforms/Scalar/InstructionCombining.cpp:1.355
--- llvm/lib/Transforms/Scalar/InstructionCombining.cpp:1.354	Thu Jun 16 21:05:55 2005
+++ llvm/lib/Transforms/Scalar/InstructionCombining.cpp	Thu Jun 16 22:59:17 2005
@@ -1967,12 +1967,11 @@
           case Instruction::SetNE:
             switch (RHSCC) {
             default: assert(0 && "Unknown integer condition code!");
-            case Instruction::SetLT:        // (X != 13 | X < 15) -> X < 15
-              return ReplaceInstUsesWith(I, RHS);
             case Instruction::SetEQ:        // (X != 13 | X == 15) -> X != 13
             case Instruction::SetGT:        // (X != 13 | X > 15)  -> X != 13
               return ReplaceInstUsesWith(I, LHS);
             case Instruction::SetNE:        // (X != 13 | X != 15) -> true
+            case Instruction::SetLT:        // (X != 13 | X < 15)  -> true
               return ReplaceInstUsesWith(I, ConstantBool::True);
             }
             break;





From tbrethou at cs.uiuc.edu  Thu Jun 16 23:00:02 2005
From: tbrethou at cs.uiuc.edu (Tanya Brethour)
Date: Thu, 16 Jun 2005 23:00:02 -0500
Subject: [llvm-commits] CVS: llvm/include/llvm/Target/TargetSchedInfo.h 
Message-ID: <200506170400.XAA16588@zion.cs.uiuc.edu>



Changes in directory llvm/include/llvm/Target:

TargetSchedInfo.h updated: 1.35 -> 1.36
---
Log message:

Added ModuloSchedSB as a friend class.


---
Diffs of the changes:  (+3 -0)

 TargetSchedInfo.h |    3 +++
 1 files changed, 3 insertions(+)


Index: llvm/include/llvm/Target/TargetSchedInfo.h
diff -u llvm/include/llvm/Target/TargetSchedInfo.h:1.35 llvm/include/llvm/Target/TargetSchedInfo.h:1.36
--- llvm/include/llvm/Target/TargetSchedInfo.h:1.35	Thu Apr 21 22:46:24 2005
+++ llvm/include/llvm/Target/TargetSchedInfo.h	Thu Jun 16 22:59:51 2005
@@ -280,7 +280,10 @@
 
 
   friend class ModuloSchedulingPass;
+  friend class ModuloSchedulingSBPass;
   friend class MSSchedule;
+  friend class MSScheduleSB;
+  friend class MSchedGraphSB;
 
 };
 





From tbrethou at cs.uiuc.edu  Thu Jun 16 23:00:33 2005
From: tbrethou at cs.uiuc.edu (Tanya Brethour)
Date: Thu, 16 Jun 2005 23:00:33 -0500
Subject: [llvm-commits] 
	CVS: llvm/lib/Target/SparcV9/SparcV9TargetMachine.cpp
Message-ID: <200506170400.XAA16599@zion.cs.uiuc.edu>



Changes in directory llvm/lib/Target/SparcV9:

SparcV9TargetMachine.cpp updated: 1.137 -> 1.138
---
Log message:

Added SMS for superblocks as an option (experimental)


---
Diffs of the changes:  (+10 -1)

 SparcV9TargetMachine.cpp |   11 ++++++++++-
 1 files changed, 10 insertions(+), 1 deletion(-)


Index: llvm/lib/Target/SparcV9/SparcV9TargetMachine.cpp
diff -u llvm/lib/Target/SparcV9/SparcV9TargetMachine.cpp:1.137 llvm/lib/Target/SparcV9/SparcV9TargetMachine.cpp:1.138
--- llvm/lib/Target/SparcV9/SparcV9TargetMachine.cpp:1.137	Fri May 13 14:45:45 2005
+++ llvm/lib/Target/SparcV9/SparcV9TargetMachine.cpp	Thu Jun 16 23:00:22 2005
@@ -64,7 +64,10 @@
                  cl::desc("Emit LLVM-to-MachineCode mapping info to assembly"));
 
   cl::opt<bool> EnableModSched("enable-modsched",
-	 cl::desc("Enable sparcv9 modulo scheduling pass instead of local scheduling"), cl::Hidden);
+		 cl::desc("Enable modulo scheduling pass"), cl::Hidden);
+
+  cl::opt<bool> EnableSBModSched("enable-modschedSB",
+	 cl::desc("Enable superblock modulo scheduling (experimental)"), cl::Hidden);
 
   // Register the target.
   RegisterTarget<SparcV9TargetMachine> X("sparcv9", "  SPARC V9");
@@ -192,6 +195,9 @@
 
   PM.add(createSparcV9BurgInstSelector(*this));
 
+  if(!DisableSched && PrintMachineCode)
+    PM.add(createMachineFunctionPrinterPass(&std::cerr, "Before local scheduling:\n"));
+
   if (!DisableSched)
     PM.add(createInstructionSchedulingWithSSAPass(*this));
 
@@ -202,6 +208,9 @@
   if(EnableModSched)
     PM.add(createModuloSchedulingPass(*this));
 
+  if(EnableSBModSched)
+    PM.add(createModuloSchedulingSBPass(*this));
+
   if (PrintMachineCode)
     PM.add(createMachineFunctionPrinterPass(&std::cerr, "Before reg alloc:\n"));
 





From tbrethou at cs.uiuc.edu  Thu Jun 16 23:01:09 2005
From: tbrethou at cs.uiuc.edu (Tanya Brethour)
Date: Thu, 16 Jun 2005 23:01:09 -0500
Subject: [llvm-commits] 
	CVS: llvm/lib/Target/SparcV9/ModuloScheduling/DependenceAnalyzer.cpp
	MSSchedule.cpp MSSchedule.h ModuloScheduling.cpp
	ModuloScheduling.h ModuloSchedulingSuperBlock.cpp
	ModuloSchedulingSuperBlock.h 
Message-ID: <200506170401.XAA16630@zion.cs.uiuc.edu>



Changes in directory llvm/lib/Target/SparcV9/ModuloScheduling:

DependenceAnalyzer.cpp updated: 1.6 -> 1.7
MSSchedule.cpp updated: 1.15 -> 1.16
MSSchedule.h updated: 1.6 -> 1.7
ModuloScheduling.cpp updated: 1.49 -> 1.50
ModuloScheduling.h updated: 1.30 -> 1.31
ModuloSchedulingSuperBlock.cpp updated: 1.1 -> 1.2
ModuloSchedulingSuperBlock.h updated: 1.1 -> 1.2
---
Log message:

Numerous bug fixes and the completed modschedSB algorithm (minor bugs still exist for course).


---
Diffs of the changes:  (+3305 -195)

 DependenceAnalyzer.cpp         |   25 
 MSSchedule.cpp                 |  203 +-
 MSSchedule.h                   |    8 
 ModuloScheduling.cpp           |  174 +-
 ModuloScheduling.h             |    3 
 ModuloSchedulingSuperBlock.cpp | 2968 ++++++++++++++++++++++++++++++++++++++++-
 ModuloSchedulingSuperBlock.h   |  119 +
 7 files changed, 3305 insertions(+), 195 deletions(-)


Index: llvm/lib/Target/SparcV9/ModuloScheduling/DependenceAnalyzer.cpp
diff -u llvm/lib/Target/SparcV9/ModuloScheduling/DependenceAnalyzer.cpp:1.6 llvm/lib/Target/SparcV9/ModuloScheduling/DependenceAnalyzer.cpp:1.7
--- llvm/lib/Target/SparcV9/ModuloScheduling/DependenceAnalyzer.cpp:1.6	Sat Apr 30 18:07:58 2005
+++ llvm/lib/Target/SparcV9/ModuloScheduling/DependenceAnalyzer.cpp	Thu Jun 16 23:00:57 2005
@@ -159,10 +159,10 @@
   SCEVHandle SV2 = SE->getSCEV(Gep2Idx);
 
   //Now handle special cases of dependence analysis
-  SV1->print(std::cerr);
-  std::cerr << "\n";
-  SV2->print(std::cerr);
-  std::cerr << "\n";
+  //SV1->print(std::cerr);
+  //std::cerr << "\n";
+  //SV2->print(std::cerr);
+  //std::cerr << "\n";
 
   //Check if we have an SCEVAddExpr, cause we can only handle those
   SCEVAddRecExpr *SVAdd1 = dyn_cast<SCEVAddRecExpr>(SV1);
@@ -217,7 +217,7 @@
   
   //Find constant index difference
   int diff = A1->getValue()->getRawValue() - A2->getValue()->getRawValue();
-  std::cerr << diff << "\n";
+  //std::cerr << diff << "\n";
   if(diff > 5)
     diff = 2;
 
@@ -240,14 +240,21 @@
 
   //If load/store pair
   if(valLoad && !val2Load) {
-    //Anti Dep
-    deps.push_back(Dependence(diff, Dependence::AntiDep));
+    if(srcBeforeDest) 
+      //Anti Dep
+      deps.push_back(Dependence(diff, Dependence::AntiDep));
+    else
+      deps.push_back(Dependence(diff, Dependence::TrueDep));
+
     ++NumDeps;
   }
   //If store/load pair
   else if(!valLoad && val2Load) {
-    //True Dep
-    deps.push_back(Dependence(diff, Dependence::TrueDep));
+    if(srcBeforeDest) 
+      //True Dep
+      deps.push_back(Dependence(diff, Dependence::TrueDep));
+    else
+      deps.push_back(Dependence(diff, Dependence::AntiDep));
     ++NumDeps;
   }
   //If store/store pair


Index: llvm/lib/Target/SparcV9/ModuloScheduling/MSSchedule.cpp
diff -u llvm/lib/Target/SparcV9/ModuloScheduling/MSSchedule.cpp:1.15 llvm/lib/Target/SparcV9/ModuloScheduling/MSSchedule.cpp:1.16
--- llvm/lib/Target/SparcV9/ModuloScheduling/MSSchedule.cpp:1.15	Thu Apr 21 18:29:16 2005
+++ llvm/lib/Target/SparcV9/ModuloScheduling/MSSchedule.cpp	Thu Jun 16 23:00:57 2005
@@ -16,18 +16,23 @@
 #include "llvm/Support/Debug.h"
 #include "llvm/Target/TargetSchedInfo.h"
 #include "../SparcV9Internals.h"
+#include "llvm/CodeGen/MachineInstr.h"
 
 using namespace llvm;
 
+//Check if all resources are free
+bool resourcesFree(MSchedGraphNode*, int, 
+std::map<int, std::map<int, int> > &resourceNumPerCycle);
+
 //Returns a boolean indicating if the start cycle needs to be increased/decreased
-bool MSSchedule::insert(MSchedGraphNode *node, int cycle) {
+bool MSSchedule::insert(MSchedGraphNode *node, int cycle, int II) {
 
   //First, check if the cycle has a spot free to start
   if(schedule.find(cycle) != schedule.end()) {
     //Check if we have a free issue slot at this cycle
     if (schedule[cycle].size() < numIssue) {
       //Now check if all the resources in their respective cycles are available
-      if(resourcesFree(node, cycle)) {
+      if(resourcesFree(node, cycle, II)) {
 	//Insert to preserve dependencies
 	addToSchedule(cycle,node);
 	DEBUG(std::cerr << "Found spot in map, and there is an issue slot\n");
@@ -37,7 +42,7 @@
   }
   //Not in the map yet so put it in
   else {
-    if(resourcesFree(node,cycle)) {
+    if(resourcesFree(node,cycle,II)) {
       std::vector<MSchedGraphNode*> nodes;
       nodes.push_back(node);
       schedule[cycle] = nodes;
@@ -68,99 +73,113 @@
   schedule[cycle] =  nodes;
 }
 
+bool MSSchedule::resourceAvailable(int resourceNum, int cycle) {
+  bool isFree = true;
+
+  //Get Map for this cycle
+  if(resourceNumPerCycle.count(cycle)) {
+    if(resourceNumPerCycle[cycle].count(resourceNum)) {
+      int maxRes = CPUResource::getCPUResource(resourceNum)->maxNumUsers;
+      if(resourceNumPerCycle[cycle][resourceNum] >= maxRes)
+	isFree = false;
+    }
+  }
+  
+  return isFree;
+}
+
+void MSSchedule::useResource(int resourceNum, int cycle) {
+  
+  //Get Map for this cycle
+  if(resourceNumPerCycle.count(cycle)) {
+    if(resourceNumPerCycle[cycle].count(resourceNum)) {
+      resourceNumPerCycle[cycle][resourceNum]++;
+    }
+    else {
+      resourceNumPerCycle[cycle][resourceNum] = 1;
+    }
+  }
+  //If no map, create one!
+  else {
+    std::map<int, int> resourceUse;
+    resourceUse[resourceNum] = 1;
+    resourceNumPerCycle[cycle] = resourceUse;
+  }
+  
+}
 
-bool MSSchedule::resourcesFree(MSchedGraphNode *node, int cycle) {
+bool MSSchedule::resourcesFree(MSchedGraphNode *node, int cycle, int II) {
 
   //Get Resource usage for this instruction
   const TargetSchedInfo *msi = node->getParent()->getTarget()->getSchedInfo();
   int currentCycle = cycle;
   bool success = true;
 
-  //Get resource usage for this instruction
-  InstrRUsage rUsage = msi->getInstrRUsage(node->getInst()->getOpcode());
-  std::vector<std::vector<resourceId_t> > resources = rUsage.resourcesByCycle;
-
-  //Loop over resources in each cycle and increments their usage count
-  for(unsigned i=0; i < resources.size(); ++i) {
-    for(unsigned j=0; j < resources[i].size(); ++j) {
-
-      //Get Resource to check its availability
-      int resourceNum = resources[i][j];
-
-      DEBUG(std::cerr << "Attempting to schedule Resource Num: " << resourceNum << " in cycle: " << currentCycle << "\n");
-
-	//Check if this resource is available for this cycle
-	std::map<int, std::map<int,int> >::iterator resourcesForCycle = resourceNumPerCycle.find(currentCycle);
-
-	//First check if map exists for this cycle
-	if(resourcesForCycle != resourceNumPerCycle.end()) {
-	  //A map exists for this cycle, so lets check for the resource
-	  std::map<int, int>::iterator resourceUse = resourcesForCycle->second.find(resourceNum);
-	  if(resourceUse != resourcesForCycle->second.end()) {
-	    //Check if there are enough of this resource and if so, increase count and move on
-	    if(resourceUse->second < CPUResource::getCPUResource(resourceNum)->maxNumUsers)
-	      ++resourceUse->second;
+  //Create vector of starting cycles
+  std::vector<int> cyclesMayConflict;
+  cyclesMayConflict.push_back(cycle);
+
+  if(resourceNumPerCycle.size() > 0) {
+    for(int i = cycle-II; i >= (resourceNumPerCycle.begin()->first); i-=II)
+      cyclesMayConflict.push_back(i);
+    for(int i = cycle+II; i <= resourceNumPerCycle.end()->first; i+=II)
+      cyclesMayConflict.push_back(i);
+  }
+
+  //Now check all cycles for conflicts
+  for(int index = 0; index < (int) cyclesMayConflict.size(); ++index) {
+    currentCycle = cyclesMayConflict[index];
+    
+    //Get resource usage for this instruction
+    InstrRUsage rUsage = msi->getInstrRUsage(node->getInst()->getOpcode());
+    std::vector<std::vector<resourceId_t> > resources = rUsage.resourcesByCycle;
+    
+    //Loop over resources in each cycle and increments their usage count
+    for(unsigned i=0; i < resources.size(); ++i) {
+      for(unsigned j=0; j < resources[i].size(); ++j) {
 	
-	    else {
-	      DEBUG(std::cerr << "No resource num " << resourceNum << " available for cycle " << currentCycle << "\n");
-	      success = false;
-	    }
-	  }
-	  //Not in the map yet, so put it
-	  else
-	    resourcesForCycle->second[resourceNum] = 1;
+	//Get Resource to check its availability
+	int resourceNum = resources[i][j];
+	
+	DEBUG(std::cerr << "Attempting to schedule Resource Num: " << resourceNum << " in cycle: " << currentCycle << "\n");
+	
+	success = resourceAvailable(resourceNum, currentCycle); 
 	
-	}
-	else {
-	  //Create a new map and put in our resource
-	  std::map<int, int> resourceMap;
-	  resourceMap[resourceNum] = 1;
-	  resourceNumPerCycle[currentCycle] = resourceMap;
-	}
 	if(!success)
 	  break;
+	
       }
+      
       if(!success)
 	break;
-	
-
+      
       //Increase cycle
       currentCycle++;
+    }
+    
+    if(!success)
+      return false;
   }
 
-  if(!success) {
-    int oldCycle = cycle;
-    DEBUG(std::cerr << "Backtrack\n");
+  //Actually put resources into the map
+  if(success) {
+
+    int currentCycle = cycle;
     //Get resource usage for this instruction
     InstrRUsage rUsage = msi->getInstrRUsage(node->getInst()->getOpcode());
     std::vector<std::vector<resourceId_t> > resources = rUsage.resourcesByCycle;
-
+    
     //Loop over resources in each cycle and increments their usage count
     for(unsigned i=0; i < resources.size(); ++i) {
-      if(oldCycle < currentCycle) {
-	
-	//Check if this resource is available for this cycle
-	std::map<int, std::map<int,int> >::iterator resourcesForCycle = resourceNumPerCycle.find(oldCycle);
-	if(resourcesForCycle != resourceNumPerCycle.end()) {
-	  for(unsigned j=0; j < resources[i].size(); ++j) {
-	    int resourceNum = resources[i][j];
-	    //remove from map
-	    std::map<int, int>::iterator resourceUse = resourcesForCycle->second.find(resourceNum);
-	    //assert if not in the map.. since it should be!
-	    //assert(resourceUse != resourcesForCycle.end() && "Resource should be in map!");
-	    DEBUG(std::cerr << "Removing resource num " << resourceNum << " from cycle " << oldCycle << "\n");
-	    --resourceUse->second;
-	  }
-	}
+      for(unsigned j=0; j < resources[i].size(); ++j) {
+	int resourceNum = resources[i][j];
+	useResource(resourceNum, currentCycle);
       }
-      else
-	break;
-      oldCycle++;
+      currentCycle++;
     }
-    return false;
-
   }
 
+
   return true;
 
 }
@@ -174,12 +193,9 @@
 
   DEBUG(std::cerr << "Offset: " << offset << "\n");
 
-  //Not sure what happens in this case, but assert if offset is > II
-  //assert(offset > -II && "Offset can not be more then II");
-
+  //Using the schedule, fold up into kernel and check resource conflicts as we go
   std::vector<std::pair<MSchedGraphNode*, int> > tempKernel;
-
-
+  
   int stageNum = ((schedule.rbegin()->first-offset)+1)/ II;
   int maxSN = 0;
 
@@ -192,21 +208,18 @@
 	for(std::vector<MSchedGraphNode*>::iterator I = schedule[i].begin(),
 	      E = schedule[i].end(); I != E; ++I) {
 	  //Check if its a branch
-	  if((*I)->isBranch()) {
-	    assert(count == 0 && "Branch can not be from a previous iteration");
-	    tempKernel.push_back(std::make_pair(*I, count));
-	  }
-	  else {
-	  //FIXME: Check if the instructions in the earlier stage conflict
-	    tempKernel.push_back(std::make_pair(*I, count));
-	    maxSN = std::max(maxSN, count);
-	  }
+	  assert(!(*I)->isBranch() && "Branch should not be schedule!");
+
+	  tempKernel.push_back(std::make_pair(*I, count));
+	  maxSN = std::max(maxSN, count);
+	  
 	}
       }
       ++count;
     }
   }
 
+
   //Add in induction var code
   for(std::vector<std::pair<MSchedGraphNode*, int> >::iterator I = tempKernel.begin(), IE = tempKernel.end();
       I != IE; ++I) {
@@ -253,6 +266,30 @@
   return true;
 }
 
+bool MSSchedule::defPreviousStage(Value *def, int stage) {
+
+  //Loop over kernel and determine if value is being defined in previous stage
+  for(std::vector<std::pair<MachineInstr*, int> >::iterator P = kernel.begin(), PE = kernel.end(); P != PE; ++P) {
+    MachineInstr* inst = P->first;
+
+    //Loop over Machine Operands
+    for(unsigned i=0; i < inst->getNumOperands(); ++i) {
+      //get machine operand
+     const MachineOperand &mOp = inst->getOperand(i);
+     if(mOp.getType() == MachineOperand::MO_VirtualRegister && mOp.isDef()) {
+       if(def == mOp.getVRegValue()) {
+	 if(P->second >= stage)
+	   return false;
+	 else
+	   return true;
+       }
+     }
+    }
+  }
+  
+  assert(0 && "We should always have found the def in our kernel\n");
+}
+
 
 void MSSchedule::print(std::ostream &os) const {
   os << "Schedule:\n";


Index: llvm/lib/Target/SparcV9/ModuloScheduling/MSSchedule.h
diff -u llvm/lib/Target/SparcV9/ModuloScheduling/MSSchedule.h:1.6 llvm/lib/Target/SparcV9/ModuloScheduling/MSSchedule.h:1.7
--- llvm/lib/Target/SparcV9/ModuloScheduling/MSSchedule.h:1.6	Thu Apr 21 18:29:16 2005
+++ llvm/lib/Target/SparcV9/ModuloScheduling/MSSchedule.h	Thu Jun 16 23:00:57 2005
@@ -28,7 +28,9 @@
     std::map<int, std::map<int, int> > resourceNumPerCycle;
 
     //Check if all resources are free
-    bool resourcesFree(MSchedGraphNode*, int);
+    bool resourcesFree(MSchedGraphNode*, int, int II); 
+    bool resourceAvailable(int resourceNum, int cycle);
+    void useResource(int resourceNum, int cycle);
 
     //Resulting kernel
     std::vector<std::pair<MachineInstr*, int> > kernel;
@@ -42,13 +44,13 @@
   public:
     MSSchedule(int num) : numIssue(num) {}
     MSSchedule() : numIssue(4) {}
-    bool insert(MSchedGraphNode *node, int cycle);
+    bool insert(MSchedGraphNode *node, int cycle, int II);
     int getStartCycle(MSchedGraphNode *node);
     void clear() { schedule.clear(); resourceNumPerCycle.clear(); kernel.clear(); }
     std::vector<std::pair<MachineInstr*, int> >* getKernel() { return &kernel; }
     bool constructKernel(int II, std::vector<MSchedGraphNode*> &branches, std::map<const MachineInstr*, unsigned> &indVar);
     int getMaxStage() { return maxStage; }
-
+    bool defPreviousStage(Value *def, int stage);
 
     //iterators
     typedef std::map<int, std::vector<MSchedGraphNode*> >::iterator schedule_iterator;


Index: llvm/lib/Target/SparcV9/ModuloScheduling/ModuloScheduling.cpp
diff -u llvm/lib/Target/SparcV9/ModuloScheduling/ModuloScheduling.cpp:1.49 llvm/lib/Target/SparcV9/ModuloScheduling/ModuloScheduling.cpp:1.50
--- llvm/lib/Target/SparcV9/ModuloScheduling/ModuloScheduling.cpp:1.49	Sat Apr 30 18:07:58 2005
+++ llvm/lib/Target/SparcV9/ModuloScheduling/ModuloScheduling.cpp	Thu Jun 16 23:00:57 2005
@@ -178,7 +178,7 @@
       }
       else
 	++JumboBB;
-      std::cerr << "BB Size: " << BI->size() << "\n";
+      
     }
 
   defaultInst = 0;
@@ -230,7 +230,6 @@
 
     II = std::max(RecMII, ResMII);
     int mII = II;
-    IISum += mII;
 
     //Print out II, RecMII, and ResMII
     DEBUG(std::cerr << "II starts out as " << II << " ( RecMII=" << RecMII << " and ResMII=" << ResMII << ")\n");
@@ -285,12 +284,15 @@
       reconstructLoop(*BI);
       ++MSLoops;
       Changed = true;
+      FinalIISum += II;
+      IISum += mII;
 
       if(schedule.getMaxStage() == 0)
 	++SameStage;
     }
-    else
+    else {
       ++NoSched;
+    }
 
     //Clear out our maps for the next basic block that is processed
     nodeToAttributesMap.clear();
@@ -323,7 +325,9 @@
       if(mOp.getType() == MachineOperand::MO_VirtualRegister && mOp.isDef()) {
 	//assert if this is the second def we have seen
 	//DEBUG(std::cerr << "Putting " << *(mOp.getVRegValue()) << " into map\n");
-	assert(!defMap.count(mOp.getVRegValue()) && "Def already in the map");
+	//assert(!defMap.count(mOp.getVRegValue()) && "Def already in the map");
+	if(defMap.count(mOp.getVRegValue()))
+	  return false;
 
 	defMap[mOp.getVRegValue()] = &*I;
       }
@@ -397,7 +401,7 @@
        || OC == V9::MOVRGEZi || OC == V9::MOVLEr || OC == V9::MOVLEi || OC == V9::MOVLEUr
        || OC == V9::MOVLEUi || OC == V9::MOVFLEr || OC == V9::MOVFLEi
        || OC == V9::MOVNEr || OC == V9::MOVNEi || OC == V9::MOVNEGr || OC == V9::MOVNEGi
-       || OC == V9::MOVFNEr || OC == V9::MOVFNEi) {
+       || OC == V9::MOVFNEr || OC == V9::MOVFNEi || OC == V9::MOVGr || OC == V9::MOVGi) {
       ++LoopsWithCondMov;
       return false;
     }
@@ -579,6 +583,8 @@
     //Divide the usage count by either the max number we can issue or the number of
     //resources (whichever is its upper bound)
     double finalUsageCount;
+    DEBUG(std::cerr << "Resource Num: " << RB->first << " Usage: " << usageCount << " TotalNum: " << resourceNum << "\n");
+
     if( resourceNum <= issueSlots)
       finalUsageCount = ceil(1.0 * usageCount / resourceNum);
     else
@@ -1035,6 +1041,56 @@
 
 }
 
+void ModuloSchedulingPass::addSCC(std::vector<MSchedGraphNode*> &SCC, std::map<MSchedGraphNode*, MSchedGraphNode*> &newNodes) {
+
+  int totalDelay = 0;
+  int totalDistance = 0;
+  std::vector<MSchedGraphNode*> recc;
+  MSchedGraphNode *start = 0;
+  MSchedGraphNode *end = 0;
+
+  //Loop over recurrence, get delay and distance
+  for(std::vector<MSchedGraphNode*>::iterator N = SCC.begin(), NE = SCC.end(); N != NE; ++N) {
+    DEBUG(std::cerr << **N << "\n");
+    totalDelay += (*N)->getLatency();
+    
+    for(unsigned i = 0; i < (*N)->succ_size(); ++i) {
+      MSchedGraphEdge *edge = (*N)->getSuccessor(i);
+      if(find(SCC.begin(), SCC.end(), edge->getDest()) != SCC.end()) {
+	totalDistance += edge->getIteDiff();
+	if(edge->getIteDiff() > 0)
+	  if(!start && !end) {
+	    start = *N;
+	    end = edge->getDest();
+	  }
+	    
+      }
+    }
+
+
+    //Get the original node
+    recc.push_back(newNodes[*N]);
+
+
+  }
+
+  DEBUG(std::cerr << "End Recc\n");
+  CircCount++;
+
+  assert( (start && end) && "Must have start and end node to ignore edge for SCC");
+
+  if(start && end) {	
+    //Insert reccurrence into the list
+    DEBUG(std::cerr << "Ignore Edge from!!: " << *start << " to " << *end << "\n");
+    edgesToIgnore.insert(std::make_pair(newNodes[start], (newNodes[end])->getInEdgeNum(newNodes[start])));
+  }
+
+  int lastII = totalDelay / totalDistance;
+
+
+  recurrenceList.insert(std::make_pair(lastII, recc));
+
+}
 
 void ModuloSchedulingPass::findAllCircuits(MSchedGraph *g, int II) {
 
@@ -1074,6 +1130,7 @@
     std::set<MSchedGraphNode*> Visited;
     std::vector<MSchedGraphNode*> Vk;
     MSchedGraphNode* s = 0;
+    int numEdges = 0;
 
     //Find scc with the least vertex
     for (MSchedGraph::iterator GI = MSG->begin(), E = MSG->end(); GI != E; ++GI)
@@ -1085,7 +1142,19 @@
 	  if (Visited.insert(nextSCC[0]).second) {
 	    Visited.insert(nextSCC.begin()+1, nextSCC.end());
 
-	    DEBUG(std::cerr << "SCC size: " << nextSCC.size() << "\n");
+	    if(nextSCC.size() > 1) {
+	      std::cerr << "SCC size: " << nextSCC.size() << "\n";
+	      
+	      for(unsigned i = 0; i < nextSCC.size(); ++i) {
+		//Loop over successor and see if in scc, then count edge
+		MSchedGraphNode *node = nextSCC[i];
+		for(MSchedGraphNode::succ_iterator S = node->succ_begin(), SE = node->succ_end(); S != SE; ++S) {
+		  if(find(nextSCC.begin(), nextSCC.end(), *S) != nextSCC.end())
+		    numEdges++;
+		}
+	      }
+	      std::cerr << "Num Edges: " << numEdges << "\n";
+	    }
 
 	    //Ignore self loops
 	    if(nextSCC.size() > 1) {
@@ -1120,7 +1189,10 @@
       B[*N].clear();
     }
     if(Vk.size() > 1) {
-      circuit(s, stack, blocked, Vk, s, B, II, newNodes);
+      if(numEdges < 98)
+	circuit(s, stack, blocked, Vk, s, B, II, newNodes);
+      else
+	addSCC(Vk, newNodes);
 
       //Delete nodes from the graph
       //Find all nodes up to s and delete them
@@ -1860,8 +1932,8 @@
 	schedule.clear();
       }
       DEBUG(std::cerr << "Final II: " << II << "\n");
-      FinalIISum += II;
     }
+   
 
     if(II >= capII) {
       DEBUG(std::cerr << "Maximum II reached, giving up\n");
@@ -1900,7 +1972,7 @@
 
     increaseSC = false;
 
-    increaseSC = schedule.insert(node, cycle);
+    increaseSC = schedule.insert(node, cycle, II);
 
     if(!increaseSC)
       return true;
@@ -2034,18 +2106,11 @@
       }
     }
 
-
-    /*for(std::vector<MSchedGraphNode*>::iterator BR = branches.begin(), BE = branches.end(); BR != BE; ++BR) {
-
-      //Stick in branch at the end
-      machineBB->push_back((*BR)->getInst()->clone());
-
-      //Add nop
-      BuildMI(machineBB, V9::NOP, 0);
-      }*/
-
-
-  (((MachineBasicBlock*)origBB)->getParent())->getBasicBlockList().push_back(machineBB);
+    MachineFunction *F = (((MachineBasicBlock*)origBB)->getParent());
+    MachineFunction::BasicBlockListType &BL = F->getBasicBlockList();
+    MachineFunction::BasicBlockListType::iterator BLI = origBB;
+    assert(BLI != BL.end() && "Must find original BB in machine function\n");
+    BL.insert(BLI,machineBB);
     prologues.push_back(machineBB);
     llvm_prologues.push_back(llvmBB);
   }
@@ -2143,12 +2208,16 @@
       }
      }
 
-    (((MachineBasicBlock*)origBB)->getParent())->getBasicBlockList().push_back(machineBB);
-    epilogues.push_back(machineBB);
-    llvm_epilogues.push_back(llvmBB);
-
-    DEBUG(std::cerr << "EPILOGUE #" << i << "\n");
-    DEBUG(machineBB->print(std::cerr));
+     MachineFunction *F = (((MachineBasicBlock*)origBB)->getParent());
+     MachineFunction::BasicBlockListType &BL = F->getBasicBlockList();
+     MachineFunction::BasicBlockListType::iterator BLI = (MachineBasicBlock*) origBB;
+     assert(BLI != BL.end() && "Must find original BB in machine function\n");
+     BL.insert(BLI,machineBB);
+     epilogues.push_back(machineBB);
+     llvm_epilogues.push_back(llvmBB);
+     
+     DEBUG(std::cerr << "EPILOGUE #" << i << "\n");
+     DEBUG(machineBB->print(std::cerr));
   }
 }
 
@@ -2170,14 +2239,6 @@
 
    DEBUG(std::cerr << "Stage: " << I->second << " Inst: " << *(I->first) << "\n";);
 
-   /*if(I->first->isBranch()) {
-     //Clone instruction
-     const MachineInstr *inst = I->first->getInst();
-     MachineInstr *instClone = inst->clone();
-     branches.push_back(instClone);
-     continue;
-     }*/
-
    //Clone instruction
    const MachineInstr *inst = I->first;
    MachineInstr *instClone = inst->clone();
@@ -2208,6 +2269,8 @@
 
 	   //Check if we already have a final PHI value for this
 	   if(!finalPHIValue.count(mOp.getVRegValue())) {
+	     //Only create phi if the operand def is from a stage before this one
+	     if(schedule.defPreviousStage(mOp.getVRegValue(), I->second)) {
 	     TmpInstruction *tmp = new TmpInstruction(mOp.getVRegValue());
 	
 	     //Get machine code for this instruction
@@ -2220,6 +2283,7 @@
 	     //save this as our final phi
 	     finalPHIValue[mOp.getVRegValue()] = tmp;
 	     newValLocation[tmp] = machineBB;
+	     }
 	   }
 	   else {
 	     //Use the previous final phi value
@@ -2538,6 +2602,7 @@
   //Keep track of instructions we have already seen and their stage because
   //we don't want to "save" values if they are used in the kernel immediately
   std::map<const MachineInstr*, int> lastInstrs;
+  std::map<const Value*, int> phiUses;
 
   //Loop over kernel and only look at instructions from a stage > 0
   //Look at its operands and save values *'s that are read
@@ -2557,7 +2622,7 @@
 	  //find the value in the map
 	  if (const Value* srcI = mOp.getVRegValue()) {
 
-	    if(isa<Constant>(srcI) || isa<Argument>(srcI) || isa<PHINode>(srcI))
+	    if(isa<Constant>(srcI) || isa<Argument>(srcI))
 	      continue;
 
 	    //Before we declare this Value* one that we should save
@@ -2582,9 +2647,27 @@
 	      }
 	    }
 	
-	    if(save)
+	    if(save) {
+	      assert(!phiUses.count(srcI) && "Did not expect to see phi use twice");
+	      if(isa<PHINode>(srcI))
+		phiUses[srcI] = I->second;
+	      
 	      valuesToSave[srcI] = std::make_pair(I->first, i);
-	  }	
+
+	    }
+	  }
+	}
+	else if(mOp.getType() == MachineOperand::MO_VirtualRegister && mOp.isDef()) {
+	  if (const Value* destI = mOp.getVRegValue()) {
+	    if(!isa<PHINode>(destI))
+	      continue;
+	    if(phiUses.count(destI)) {
+	      if(phiUses[destI] == I->second) {
+		//remove from save list
+		valuesToSave.erase(destI);
+	      }
+	    }
+	  }
 	}
 	
 	if(mOp.getType() != MachineOperand::MO_VirtualRegister && mOp.isUse()) {
@@ -2623,7 +2706,14 @@
 
   BasicBlock *llvmKernelBB = new BasicBlock("Kernel", (Function*) (BB->getBasicBlock()->getParent()));
   MachineBasicBlock *machineKernelBB = new MachineBasicBlock(llvmKernelBB);
-  (((MachineBasicBlock*)BB)->getParent())->getBasicBlockList().push_back(machineKernelBB);
+ 
+  MachineFunction *F = (((MachineBasicBlock*)BB)->getParent());
+  MachineFunction::BasicBlockListType &BL = F->getBasicBlockList();
+  MachineFunction::BasicBlockListType::iterator BLI = BB;
+  assert(BLI != BL.end() && "Must find original BB in machine function\n");
+  BL.insert(BLI,machineKernelBB);
+
+  //(((MachineBasicBlock*)BB)->getParent())->getBasicBlockList().push_back(machineKernelBB);
   writeKernel(llvmKernelBB, machineKernelBB, valuesToSave, newValues, newValLocation, kernelPHIs);
 
 
@@ -2833,7 +2923,8 @@
 		 for(unsigned opNum = 0; opNum < temp->getNumOperands(); ++opNum) {
 		   MachineOperand &mOp = temp->getOperand(opNum);
 		   if (mOp.getType() == MachineOperand::MO_PCRelativeDisp) {
-		     mOp.setValueReg(llvm_prologues[0]);
+		     if(mOp.getVRegValue() == llvmBB)
+		       mOp.setValueReg(llvm_prologues[0]);
 		   }
 		 }
 	       }
@@ -2853,7 +2944,8 @@
 		 for(unsigned opNum = 0; opNum < temp->getNumOperands(); ++opNum) {
 		   MachineOperand &mOp = temp->getOperand(opNum);
 		   if (mOp.getType() == MachineOperand::MO_PCRelativeDisp) {
-		     mOp.setValueReg(llvmKernelBB);
+		     if(mOp.getVRegValue() == llvmBB)
+		       mOp.setValueReg(llvmKernelBB);
 		   }
 		 }
 	       }


Index: llvm/lib/Target/SparcV9/ModuloScheduling/ModuloScheduling.h
diff -u llvm/lib/Target/SparcV9/ModuloScheduling/ModuloScheduling.h:1.30 llvm/lib/Target/SparcV9/ModuloScheduling/ModuloScheduling.h:1.31
--- llvm/lib/Target/SparcV9/ModuloScheduling/ModuloScheduling.h:1.30	Sat Apr 30 18:07:59 2005
+++ llvm/lib/Target/SparcV9/ModuloScheduling/ModuloScheduling.h	Thu Jun 16 23:00:57 2005
@@ -98,6 +98,7 @@
     void findAllReccurrences(MSchedGraphNode *node,
 			     std::vector<MSchedGraphNode*> &visitedNodes, int II);
     void addReccurrence(std::vector<MSchedGraphNode*> &recurrence, int II, MSchedGraphNode*, MSchedGraphNode*);
+    void addSCC(std::vector<MSchedGraphNode*> &SCC, std::map<MSchedGraphNode*, MSchedGraphNode*> &newNodes);
 
     void findAllCircuits(MSchedGraph *MSG, int II);
     bool circuit(MSchedGraphNode *v, std::vector<MSchedGraphNode*> &stack,
@@ -142,7 +143,7 @@
 
     void writeKernel(BasicBlock *llvmBB, MachineBasicBlock *machineBB, std::map<const Value*, std::pair<const MachineInstr*, int> > &valuesToSave, std::map<Value*, std::map<int, Value*> > &newValues, std::map<Value*, MachineBasicBlock*> &newValLocation, std::map<Value*, std::map<int, Value*> > &kernelPHIs);
 
-    void removePHIs(const MachineBasicBlock *origBB, std::vector<MachineBasicBlock *> &prologues, std::vector<MachineBasicBlock *> &epilogues, MachineBasicBlock *kernelBB, std::map<Value*, MachineBasicBlock*> &newValLocation);
+    void removePHIs(const MachineBasicBlock* SB, std::vector<MachineBasicBlock*> &prologues, std::vector<MachineBasicBlock *> &epilogues, MachineBasicBlock *kernelBB, std::map<Value*, MachineBasicBlock*> &newValLocation);
 
     void connectedComponentSet(MSchedGraphNode *node, std::set<MSchedGraphNode*> &ccSet, std::set<MSchedGraphNode*> &lastNodes);
 


Index: llvm/lib/Target/SparcV9/ModuloScheduling/ModuloSchedulingSuperBlock.cpp
diff -u llvm/lib/Target/SparcV9/ModuloScheduling/ModuloSchedulingSuperBlock.cpp:1.1 llvm/lib/Target/SparcV9/ModuloScheduling/ModuloSchedulingSuperBlock.cpp:1.2
--- llvm/lib/Target/SparcV9/ModuloScheduling/ModuloSchedulingSuperBlock.cpp:1.1	Sat Apr 30 20:27:47 2005
+++ llvm/lib/Target/SparcV9/ModuloScheduling/ModuloSchedulingSuperBlock.cpp	Thu Jun 16 23:00:57 2005
@@ -17,12 +17,16 @@
 
 #include "DependenceAnalyzer.h"
 #include "ModuloSchedulingSuperBlock.h"
+#include "llvm/Constants.h"
 #include "llvm/ADT/Statistic.h"
 #include "llvm/CodeGen/MachineFunction.h"
 #include "llvm/CodeGen/Passes.h"
 #include "llvm/Support/CFG.h"
 #include "llvm/Support/Debug.h"
 #include "llvm/Support/GraphWriter.h"
+#include "llvm/Support/Timer.h"
+#include "llvm/ADT/StringExtras.h"
+#include "llvm/ADT/SCCIterator.h"
 #include "llvm/Instructions.h"
 #include "../MachineCodeForInstruction.h"
 #include "../SparcV9RegisterInfo.h"
@@ -30,6 +34,8 @@
 #include "../SparcV9TmpInstr.h"
 #include <fstream>
 #include <sstream>
+#include <cmath>
+#include <utility>
 
 using namespace llvm;
 /// Create ModuloSchedulingSBPass
@@ -39,9 +45,18 @@
   return new ModuloSchedulingSBPass(targ);
 }
 
+
+#if 1
+#define TIME_REGION(VARNAME, DESC) \
+   NamedRegionTimer VARNAME(DESC)
+#else
+#define TIME_REGION(VARNAME, DESC)
+#endif
+
+
 //Graph Traits for printing out the dependence graph
 template<typename GraphType>
-static void WriteGraphToFile(std::ostream &O, const std::string &GraphName,
+static void WriteGraphToFileSB(std::ostream &O, const std::string &GraphName,
                              const GraphType &GT) {
   std::string Filename = GraphName + ".dot";
   O << "Writing '" << Filename << "'...";
@@ -58,8 +73,82 @@
   Statistic<> NumLoops("moduloschedSB-numLoops", "Total Number of Loops");
   Statistic<> NumSB("moduloschedSB-numSuperBlocks", "Total Number of SuperBlocks");
   Statistic<> BBWithCalls("modulosched-BBCalls", "Basic Blocks rejected due to calls");
-  Statistic<> BBWithCondMov("modulosched-loopCondMov", "Basic Blocks rejected due to conditional moves");
+  Statistic<> BBWithCondMov("modulosched-loopCondMov", 
+			    "Basic Blocks rejected due to conditional moves");
+  Statistic<> SBResourceConstraint("modulosched-resourceConstraint", 
+				 "Loops constrained by resources");
+  Statistic<> SBRecurrenceConstraint("modulosched-recurrenceConstraint", 
+				   "Loops constrained by recurrences");
+  Statistic<> SBFinalIISum("modulosched-finalIISum", "Sum of all final II");
+  Statistic<> SBIISum("modulosched-IISum", "Sum of all theoretical II");
+  Statistic<> SBMSLoops("modulosched-schedLoops", "Number of loops successfully modulo-scheduled");
+  Statistic<> SBNoSched("modulosched-noSched", "No schedule");
+  Statistic<> SBSameStage("modulosched-sameStage", "Max stage is 0");
+  Statistic<> SBBLoops("modulosched-SBBLoops", "Number single basic block loops");
+  Statistic<> SBInvalid("modulosched-SBInvalid", "Number invalid superblock loops");
+  Statistic<> SBValid("modulosched-SBValid", "Number valid superblock loops");
+ Statistic<> SBSize("modulosched-SBSize", "Total size of all valid superblocks");
+
+  template<>
+  struct DOTGraphTraits<MSchedGraphSB*> : public DefaultDOTGraphTraits {
+    static std::string getGraphName(MSchedGraphSB *F) {
+      return "Dependence Graph";
+    }
+
+    static std::string getNodeLabel(MSchedGraphSBNode *Node, MSchedGraphSB *Graph) {
+      if(!Node->isPredicate()) {
+	if (Node->getInst()) {
+	  std::stringstream ss;
+	  ss << *(Node->getInst());
+	  return ss.str(); //((MachineInstr*)Node->getInst());
+	}
+	else
+	  return "No Inst";
+      }
+      else
+	return "Pred Node";
+    }
+    static std::string getEdgeSourceLabel(MSchedGraphSBNode *Node,
+					  MSchedGraphSBNode::succ_iterator I) {
+      //Label each edge with the type of dependence
+      std::string edgelabel = "";
+      switch (I.getEdge().getDepOrderType()) {
+	
+      case MSchedGraphSBEdge::TrueDep:
+	edgelabel = "True";
+	break;
+
+      case MSchedGraphSBEdge::AntiDep:
+	edgelabel =  "Anti";
+	break;
+	
+      case MSchedGraphSBEdge::OutputDep:
+	edgelabel = "Output";
+	break;
+	
+      case MSchedGraphSBEdge::NonDataDep:
+	edgelabel = "Pred";
+	break;
+
+      default:
+	edgelabel = "Unknown";
+	break;
+      }
+
+      //FIXME
+      int iteDiff = I.getEdge().getIteDiff();
+      std::string intStr = "(IteDiff: ";
+      intStr += itostr(iteDiff);
+
+      intStr += ")";
+      edgelabel += intStr;
+
+      return edgelabel;
+    }
+  };
+
   bool ModuloSchedulingSBPass::runOnFunction(Function &F) {
+    alarm(100);
     bool Changed = false;
     
     //Get MachineFunction
@@ -91,14 +180,97 @@
 	continue;
       }
 
-      MSchedGraph *MSG = new MSchedGraph(*SB, target, indVarInstrs[*SB], DA, 
+      MSchedGraphSB *MSG = new MSchedGraphSB(*SB, target, indVarInstrs[*SB], DA, 
 					 machineTollvm[*SB]);
 
       //Write Graph out to file
-      DEBUG(WriteGraphToFile(std::cerr, F.getName(), MSG));
-      DEBUG(MSG->print(std::cerr));
+      DEBUG(WriteGraphToFileSB(std::cerr, F.getName(), MSG));
+      
+      //Calculate Resource II
+      int ResMII = calculateResMII(*SB);
+
+      //Calculate Recurrence II
+      int RecMII = calculateRecMII(MSG, ResMII);
+      
+      DEBUG(std::cerr << "Number of reccurrences found: " << recurrenceList.size() << "\n");
+      
+      //Our starting initiation interval is the maximum of RecMII and ResMII
+      if(RecMII < ResMII)
+	++SBRecurrenceConstraint;
+      else
+	++SBResourceConstraint;
+      
+      II = std::max(RecMII, ResMII);
+      int mII = II;
+    
+      
+      //Print out II, RecMII, and ResMII
+      DEBUG(std::cerr << "II starts out as " << II << " ( RecMII=" << RecMII << " and ResMII=" << ResMII << ")\n");
+     
+      //Calculate Node Properties
+      calculateNodeAttributes(MSG, ResMII);
+      
+      //Dump node properties if in debug mode
+      DEBUG(for(std::map<MSchedGraphSBNode*, MSNodeSBAttributes>::iterator I =  nodeToAttributesMap.begin(),
+		  E = nodeToAttributesMap.end(); I !=E; ++I) {
+	      std::cerr << "Node: " << *(I->first) << " ASAP: " << I->second.ASAP << " ALAP: "
+			<< I->second.ALAP << " MOB: " << I->second.MOB << " Depth: " << I->second.depth
+			<< " Height: " << I->second.height << "\n";
+	    });
+      
+
+      //Put nodes in order to schedule them
+      computePartialOrder();
+ 
+      //Dump out partial order
+      DEBUG(for(std::vector<std::set<MSchedGraphSBNode*> >::iterator I = partialOrder.begin(),
+		  E = partialOrder.end(); I !=E; ++I) {
+	      std::cerr << "Start set in PO\n";
+	      for(std::set<MSchedGraphSBNode*>::iterator J = I->begin(), JE = I->end(); J != JE; ++J)
+		std::cerr << "PO:" << **J << "\n";
+	    });
 
+      //Place nodes in final order
+      orderNodes();
+      
+      //Dump out order of nodes
+      DEBUG(for(std::vector<MSchedGraphSBNode*>::iterator I = FinalNodeOrder.begin(), E = FinalNodeOrder.end(); I != E; ++I) {
+	      std::cerr << "FO:" << **I << "\n";
+	    });
+      
+
+      //Finally schedule nodes
+      bool haveSched = computeSchedule(*SB, MSG);
+      
+      //Print out final schedule
+      DEBUG(schedule.print(std::cerr));
+      
+      //Final scheduling step is to reconstruct the loop only if we actual have
+      //stage > 0
+      if(haveSched) {
+	//schedule.printSchedule(std::cerr);
+	reconstructLoop(*SB);
+	++SBMSLoops;
+	//Changed = true;
+	SBIISum += mII;
+	SBFinalIISum += II;
+	
+      if(schedule.getMaxStage() == 0)
+	++SBSameStage;
+      }
+      else
+	++SBNoSched;
+      
+      //Clear out our maps for the next basic block that is processed
+      nodeToAttributesMap.clear();
+      partialOrder.clear();
+      recurrenceList.clear();
+      FinalNodeOrder.clear();
+      schedule.clear();
+      defMap.clear();
+      
     }
+    alarm(0);
     return Changed;
     
   }
@@ -145,63 +317,211 @@
 	MachineBasicBlock *currentMBB = bbMap[header];
 	bool done = false;
 	bool success = true;
+	unsigned offset = 0;
+	std::map<const MachineInstr*, unsigned> indexMap;
 
 	while(!done) {
-	  
-	  if(MachineBBisValid(currentMBB)) {
-
-	    //Loop over successors of this BB, they should be in the loop block
-	    //and be valid
-	    BasicBlock *next = 0;
-	    for(succ_iterator I = succ_begin(current), E = succ_end(current);
-		I != E; ++I) {
-	      if(L->contains(*I)) {
-		if(!next) 
-		  next = *I;
-		else {
-		  done = true;
-		  success = false;
-		  break;
-		}
-	      }
-	    }
-	    if(success) {
-	      superBlock.push_back(currentMBB);
-	      if(next == header)
-		done = true;
-	      else if(!next->getSinglePredecessor()) {
+	  //Loop over successors of this BB, they should be in the
+	  //loop block and be valid
+	  BasicBlock *next = 0;
+	  for(succ_iterator I = succ_begin(current), E = succ_end(current);
+	      I != E; ++I) {
+	    if(L->contains(*I)) {
+	      if(!next) 
+		next = *I;
+	      else {
 		done = true;
 		success = false;
-	      }
-	      else {
-		//Check that the next BB only has one entry
-		current = next;
-		assert(bbMap.count(current) && "LLVM BB must have corresponding Machine BB");
-		currentMBB = bbMap[current];
+		break;
 	      }
 	    }
 	  }
-	  else {
-	    done = true;
-	    success = false;
+	   
+	  if(success) {
+	    superBlock.push_back(currentMBB);
+	    if(next == header)
+	      done = true;
+	    else if(!next->getSinglePredecessor()) {
+	      done = true;
+	      success = false;
+	    }
+	    else {
+	      //Check that the next BB only has one entry
+	      current = next;
+	      assert(bbMap.count(current) && "LLVM BB must have corresponding Machine BB");
+	      currentMBB = bbMap[current];
+	    }
 	  }
 	}
 
+
+	  
+
+
 	if(success) {
 	  ++NumSB;
-	  Worklist.push_back(superBlock);
+
+	  //Loop over all the blocks in the superblock
+	  for(std::vector<const MachineBasicBlock*>::iterator currentMBB = superBlock.begin(), MBBEnd = superBlock.end(); currentMBB != MBBEnd; ++currentMBB) {
+	    if(!MachineBBisValid(*currentMBB, indexMap, offset)) {
+	      success = false;
+	      break;
+	    }
+	  }
+	}
+	
+	if(success) {
+	  if(getIndVar(superBlock, bbMap, indexMap)) {
+	    ++SBValid;
+	    Worklist.push_back(superBlock);
+	    SBSize += superBlock.size();
+	  }
+	  else
+	    ++SBInvalid;
+	}
+      }
+    }
+  }
+  
+  
+  bool ModuloSchedulingSBPass::getIndVar(std::vector<const MachineBasicBlock*> &superBlock, std::map<BasicBlock*, MachineBasicBlock*> &bbMap, 
+				  std::map<const MachineInstr*, unsigned> &indexMap) {
+    //See if we can get induction var instructions
+    std::set<const BasicBlock*> llvmSuperBlock;
+
+    for(unsigned i =0; i < superBlock.size(); ++i)
+      llvmSuperBlock.insert(superBlock[i]->getBasicBlock());
+
+    //Get Target machine instruction info
+    const TargetInstrInfo *TMI = target.getInstrInfo();
+    
+    //Get the loop back branch
+    BranchInst *b = dyn_cast<BranchInst>(((BasicBlock*) (superBlock[superBlock.size()-1])->getBasicBlock())->getTerminator());
+     std::set<Instruction*> indVar;
+
+    if(b->isConditional()) {
+      //Get the condition for the branch 
+      Value *cond = b->getCondition();
+    
+      DEBUG(std::cerr << "Condition: " << *cond << "\n");
+    
+      //List of instructions associated with induction variable
+      std::vector<Instruction*> stack;
+    
+      //Add branch
+      indVar.insert(b);
+    
+      if(Instruction *I = dyn_cast<Instruction>(cond))
+	if(bbMap.count(I->getParent())) {
+	  if (!assocIndVar(I, indVar, stack, bbMap, superBlock[(superBlock.size()-1)]->getBasicBlock(), llvmSuperBlock))
+	    return false;
+	}
+	else
+	  return false;
+      else
+	return false;
+    }
+    else {
+      indVar.insert(b);
+    }
+
+    //Dump out instructions associate with indvar for debug reasons
+    DEBUG(for(std::set<Instruction*>::iterator N = indVar.begin(), NE = indVar.end(); 
+	      N != NE; ++N) {
+	    std::cerr << **N << "\n";
+	  });
+    
+    //Create map of machine instr to llvm instr
+    std::map<MachineInstr*, Instruction*> mllvm;
+    for(std::vector<const MachineBasicBlock*>::iterator MBB = superBlock.begin(), MBE = superBlock.end(); MBB != MBE; ++MBB) {
+      BasicBlock *BB = (BasicBlock*) (*MBB)->getBasicBlock();
+      for(BasicBlock::iterator I = BB->begin(), E = BB->end(); I != E; ++I) {
+	MachineCodeForInstruction & tempMvec = MachineCodeForInstruction::get(I);
+	for (unsigned j = 0; j < tempMvec.size(); j++) {
+	  mllvm[tempMvec[j]] = I;
 	}
+      }
+    }
 
+      //Convert list of LLVM Instructions to list of Machine instructions
+      std::map<const MachineInstr*, unsigned> mIndVar;
+      for(std::set<Instruction*>::iterator N = indVar.begin(), 
+	    NE = indVar.end(); N != NE; ++N) {
+	      
+	//If we have a load, we can't handle this loop because
+	//there is no way to preserve dependences between loads
+	//and stores
+	if(isa<LoadInst>(*N))
+	  return false;
+
+	MachineCodeForInstruction & tempMvec = MachineCodeForInstruction::get(*N);
+	for (unsigned j = 0; j < tempMvec.size(); j++) {
+	  MachineOpCode OC = (tempMvec[j])->getOpcode();
+	  if(TMI->isNop(OC))
+	    continue;
+	  if(!indexMap.count(tempMvec[j]))
+	    continue;
+	  mIndVar[(MachineInstr*) tempMvec[j]] = indexMap[(MachineInstr*) tempMvec[j]];
+	  DEBUG(std::cerr << *(tempMvec[j]) << " at index " << indexMap[(MachineInstr*) tempMvec[j]] << "\n");
+	}
       }
+      
+      //Put into a map for future access
+      indVarInstrs[superBlock] = mIndVar;
+      machineTollvm[superBlock] = mllvm;
+      
+      return true;
+      
+  }
 
+  bool ModuloSchedulingSBPass::assocIndVar(Instruction *I, 
+					   std::set<Instruction*> &indVar,
+					   std::vector<Instruction*> &stack, 
+				       std::map<BasicBlock*, MachineBasicBlock*> &bbMap, 
+					   const BasicBlock *last, std::set<const BasicBlock*> &llvmSuperBlock) {
+
+    stack.push_back(I);
+    
+    //If this is a phi node, check if its the canonical indvar
+    if(PHINode *PN = dyn_cast<PHINode>(I)) {
+      if(llvmSuperBlock.count(PN->getParent())) {
+	if (Instruction *Inc =
+	    dyn_cast<Instruction>(PN->getIncomingValueForBlock(last)))
+	  if (Inc->getOpcode() == Instruction::Add && Inc->getOperand(0) == PN)
+	    if (ConstantInt *CI = dyn_cast<ConstantInt>(Inc->getOperand(1)))
+	      if (CI->equalsInt(1)) {
+		//We have found the indvar, so add the stack, and inc instruction to the set
+		indVar.insert(stack.begin(), stack.end());
+		indVar.insert(Inc);
+		stack.pop_back();
+		return true;
+	      }
+	return false;
+      }
+    }
+    else {
+      //Loop over each of the instructions operands, check if they are an instruction and in this BB
+      for(unsigned i = 0; i < I->getNumOperands(); ++i) {
+	if(Instruction *N =  dyn_cast<Instruction>(I->getOperand(i))) {
+	  if(bbMap.count(N->getParent()))
+	    if(!assocIndVar(N, indVar, stack, bbMap, last, llvmSuperBlock))
+	      return false;
+	}
+      }
     }
+    
+    stack.pop_back();
+    return true;
   }
   
+
   /// This function checks if a Machine Basic Block is valid for modulo
   /// scheduling. This means that it has no control flow (if/else or
   /// calls) in the block.  Currently ModuloScheduling only works on
   /// single basic block loops.
-  bool ModuloSchedulingSBPass::MachineBBisValid(const MachineBasicBlock *BI) {
+  bool ModuloSchedulingSBPass::MachineBBisValid(const MachineBasicBlock *BI,     
+			std::map<const MachineInstr*, unsigned> &indexMap, 
+						unsigned &offset) {
     
     //Check size of our basic block.. make sure we have more then just the terminator in it
     if(BI->getBasicBlock()->size() == 1)
@@ -210,9 +530,6 @@
     //Get Target machine instruction info
     const TargetInstrInfo *TMI = target.getInstrInfo();
 
-    //Check each instruction and look for calls, keep map to get index later
-    std::map<const MachineInstr*, unsigned> indexMap;
-
     unsigned count = 0;
     for(MachineBasicBlock::const_iterator I = BI->begin(), E = BI->end(); I != E; ++I) {
       //Get opcode to check instruction type
@@ -236,7 +553,7 @@
 	return false;
       }
 
-      indexMap[I] = count;
+      indexMap[I] = count + offset;
 
       if(TMI->isNop(OC))
 	continue;
@@ -244,6 +561,8 @@
       ++count;
     }
 
+    offset += count;
+
     return true;
   }
 }
@@ -258,10 +577,16 @@
       for(unsigned opNum = 0; opNum < I->getNumOperands(); ++opNum) {
 	const MachineOperand &mOp = I->getOperand(opNum);
 	if(mOp.getType() == MachineOperand::MO_VirtualRegister && mOp.isDef()) {
-	  
+	  Value *V = mOp.getVRegValue();
 	  //assert if this is the second def we have seen
-	  assert(!defMap.count(mOp.getVRegValue()) && "Def already in the map");
-	  defMap[mOp.getVRegValue()] = (MachineInstr*) &*I;
+	  if(defMap.count(V) && isa<PHINode>(V))
+	    DEBUG(std::cerr << "FIXME: Dup def for phi!\n");
+	  else {
+	    //assert(!defMap.count(V) && "Def already in the map");
+	    if(defMap.count(V))
+	      return false;
+	    defMap[V] = (MachineInstr*) &*I;
+	  }
 	}
 	
 	//See if we can use this Value* as our defaultInst
@@ -280,3 +605,2554 @@
   return true;
 
 }
+
+
+//ResMII is calculated by determining the usage count for each resource
+//and using the maximum.
+//FIXME: In future there should be a way to get alternative resources
+//for each instruction
+int ModuloSchedulingSBPass::calculateResMII(std::vector<const MachineBasicBlock*> &superBlock) {
+
+  TIME_REGION(X, "calculateResMII");
+
+  const TargetInstrInfo *mii = target.getInstrInfo();
+  const TargetSchedInfo *msi = target.getSchedInfo();
+
+  int ResMII = 0;
+
+  //Map to keep track of usage count of each resource
+  std::map<unsigned, unsigned> resourceUsageCount;
+
+  for(std::vector<const MachineBasicBlock*>::iterator BI = superBlock.begin(), BE = superBlock.end(); BI != BE; ++BI) {
+    for(MachineBasicBlock::const_iterator I = (*BI)->begin(), E = (*BI)->end(); I != E; ++I) {
+
+      //Get resource usage for this instruction
+      InstrRUsage rUsage = msi->getInstrRUsage(I->getOpcode());
+      std::vector<std::vector<resourceId_t> > resources = rUsage.resourcesByCycle;
+
+      //Loop over resources in each cycle and increments their usage count
+      for(unsigned i=0; i < resources.size(); ++i)
+	for(unsigned j=0; j < resources[i].size(); ++j) {
+	  if(!resourceUsageCount.count(resources[i][j])) {
+	    resourceUsageCount[resources[i][j]] = 1;
+	  }
+	  else {
+	    resourceUsageCount[resources[i][j]] =  resourceUsageCount[resources[i][j]] + 1;
+	  }
+	}
+    }
+  }
+
+  //Find maximum usage count
+
+  //Get max number of instructions that can be issued at once. (FIXME)
+  int issueSlots = msi->maxNumIssueTotal;
+
+  for(std::map<unsigned,unsigned>::iterator RB = resourceUsageCount.begin(), RE = resourceUsageCount.end(); RB != RE; ++RB) {
+
+    //Get the total number of the resources in our cpu
+    int resourceNum = CPUResource::getCPUResource(RB->first)->maxNumUsers;
+
+    //Get total usage count for this resources
+    unsigned usageCount = RB->second;
+
+    //Divide the usage count by either the max number we can issue or the number of
+    //resources (whichever is its upper bound)
+    double finalUsageCount;
+    DEBUG(std::cerr << "Resource Num: " << RB->first << " Usage: " << usageCount << " TotalNum: " << resourceNum << "\n");
+
+    if( resourceNum <= issueSlots)
+      finalUsageCount = ceil(1.0 * usageCount / resourceNum);
+    else
+      finalUsageCount = ceil(1.0 * usageCount / issueSlots);
+
+
+    //Only keep track of the max
+    ResMII = std::max( (int) finalUsageCount, ResMII);
+
+  }
+
+  return ResMII;
+  
+}
+
+/// calculateRecMII - Calculates the value of the highest recurrence
+/// By value we mean the total latency/distance
+int ModuloSchedulingSBPass::calculateRecMII(MSchedGraphSB *graph, int MII) {
+  
+  TIME_REGION(X, "calculateRecMII");
+  
+  findAllCircuits(graph, MII);
+  int RecMII = 0;
+  
+  for(std::set<std::pair<int, std::vector<MSchedGraphSBNode*> > >::iterator I = recurrenceList.begin(), E=recurrenceList.end(); I !=E; ++I) {
+    RecMII = std::max(RecMII, I->first);
+  }
+  
+  return MII;
+}
+
+int CircCountSB;
+
+void ModuloSchedulingSBPass::unblock(MSchedGraphSBNode *u, std::set<MSchedGraphSBNode*> &blocked,
+	     std::map<MSchedGraphSBNode*, std::set<MSchedGraphSBNode*> > &B) {
+
+  //Unblock u
+  DEBUG(std::cerr << "Unblocking: " << *u << "\n");
+  blocked.erase(u);
+
+  //std::set<MSchedGraphSBNode*> toErase;
+  while (!B[u].empty()) {
+    MSchedGraphSBNode *W = *B[u].begin();
+    B[u].erase(W);
+    //toErase.insert(*W);
+    DEBUG(std::cerr << "Removed: " << *W << "from B-List\n");
+    if(blocked.count(W))
+      unblock(W, blocked, B);
+  }
+
+}
+
+void ModuloSchedulingSBPass::addSCC(std::vector<MSchedGraphSBNode*> &SCC, std::map<MSchedGraphSBNode*, MSchedGraphSBNode*> &newNodes) {
+
+  int totalDelay = 0;
+  int totalDistance = 0;
+  std::vector<MSchedGraphSBNode*> recc;
+  MSchedGraphSBNode *start = 0;
+  MSchedGraphSBNode *end = 0;
+
+  //Loop over recurrence, get delay and distance
+  for(std::vector<MSchedGraphSBNode*>::iterator N = SCC.begin(), NE = SCC.end(); N != NE; ++N) {
+    DEBUG(std::cerr << **N << "\n");
+    totalDelay += (*N)->getLatency();
+    
+    for(unsigned i = 0; i < (*N)->succ_size(); ++i) {
+      MSchedGraphSBEdge *edge = (*N)->getSuccessor(i);
+      if(find(SCC.begin(), SCC.end(), edge->getDest()) != SCC.end()) {
+	totalDistance += edge->getIteDiff();
+	if(edge->getIteDiff() > 0)
+	  if(!start && !end) {
+	    start = *N;
+	    end = edge->getDest();
+	  }
+	    
+      }
+    }
+
+
+    //Get the original node
+    recc.push_back(newNodes[*N]);
+
+
+  }
+
+  DEBUG(std::cerr << "End Recc\n");
+  
+
+  assert( (start && end) && "Must have start and end node to ignore edge for SCC");
+
+  if(start && end) {	
+    //Insert reccurrence into the list
+    DEBUG(std::cerr << "Ignore Edge from!!: " << *start << " to " << *end << "\n");
+    edgesToIgnore.insert(std::make_pair(newNodes[start], (newNodes[end])->getInEdgeNum(newNodes[start])));
+  }
+
+  int lastII = totalDelay / totalDistance;
+
+
+  recurrenceList.insert(std::make_pair(lastII, recc));
+
+}
+
+bool ModuloSchedulingSBPass::circuit(MSchedGraphSBNode *v, std::vector<MSchedGraphSBNode*> &stack,
+	     std::set<MSchedGraphSBNode*> &blocked, std::vector<MSchedGraphSBNode*> &SCC,
+	     MSchedGraphSBNode *s, std::map<MSchedGraphSBNode*, std::set<MSchedGraphSBNode*> > &B,
+				   int II, std::map<MSchedGraphSBNode*, MSchedGraphSBNode*> &newNodes) {
+  bool f = false;
+
+  DEBUG(std::cerr << "Finding Circuits Starting with: ( " << v << ")"<< *v << "\n");
+
+  //Push node onto the stack
+  stack.push_back(v);
+
+  //block this node
+  blocked.insert(v);
+
+  //Loop over all successors of node v that are in the scc, create Adjaceny list
+  std::set<MSchedGraphSBNode*> AkV;
+  for(MSchedGraphSBNode::succ_iterator I = v->succ_begin(), E = v->succ_end(); I != E; ++I) {
+    if((std::find(SCC.begin(), SCC.end(), *I) != SCC.end())) {
+      AkV.insert(*I);
+    }
+  }
+
+  for(std::set<MSchedGraphSBNode*>::iterator I = AkV.begin(), E = AkV.end(); I != E; ++I) {
+    if(*I == s) {
+      //We have a circuit, so add it to our list
+      addRecc(stack, newNodes);
+      f = true;
+    }
+    else if(!blocked.count(*I)) {
+      if(circuit(*I, stack, blocked, SCC, s, B, II, newNodes))
+	f = true;
+    }
+    else
+      DEBUG(std::cerr << "Blocked: " << **I << "\n");
+  }
+
+
+  if(f) {
+    unblock(v, blocked, B);
+  }
+  else {
+    for(std::set<MSchedGraphSBNode*>::iterator I = AkV.begin(), E = AkV.end(); I != E; ++I)
+      B[*I].insert(v);
+
+  }
+
+  //Pop v
+  stack.pop_back();
+
+  return f;
+
+}
+
+void ModuloSchedulingSBPass::addRecc(std::vector<MSchedGraphSBNode*> &stack, std::map<MSchedGraphSBNode*, MSchedGraphSBNode*> &newNodes) {
+  std::vector<MSchedGraphSBNode*> recc;
+  //Dump recurrence for now
+  DEBUG(std::cerr << "Starting Recc\n");
+	
+  int totalDelay = 0;
+  int totalDistance = 0;
+  MSchedGraphSBNode *lastN = 0;
+  MSchedGraphSBNode *start = 0;
+  MSchedGraphSBNode *end = 0;
+
+  //Loop over recurrence, get delay and distance
+  for(std::vector<MSchedGraphSBNode*>::iterator N = stack.begin(), NE = stack.end(); N != NE; ++N) {
+    DEBUG(std::cerr << **N << "\n");
+    totalDelay += (*N)->getLatency();
+    if(lastN) {
+      int iteDiff = (*N)->getInEdge(lastN).getIteDiff();
+      totalDistance += iteDiff;
+
+      if(iteDiff > 0) {
+	start = lastN;
+	end = *N;
+      }
+    }
+    //Get the original node
+    lastN = *N;
+    recc.push_back(newNodes[*N]);
+
+
+  }
+
+  //Get the loop edge
+  totalDistance += lastN->getIteDiff(*stack.begin());
+
+  DEBUG(std::cerr << "End Recc\n");
+  CircCountSB++;
+
+  if(start && end) {	
+    //Insert reccurrence into the list
+    DEBUG(std::cerr << "Ignore Edge from!!: " << *start << " to " << *end << "\n");
+    edgesToIgnore.insert(std::make_pair(newNodes[start], (newNodes[end])->getInEdgeNum(newNodes[start])));
+  }
+  else {
+    //Insert reccurrence into the list
+    DEBUG(std::cerr << "Ignore Edge from: " << *lastN << " to " << **stack.begin() << "\n");
+    edgesToIgnore.insert(std::make_pair(newNodes[lastN], newNodes[(*stack.begin())]->getInEdgeNum(newNodes[lastN])));
+
+  }
+  //Adjust II until we get close to the inequality delay - II*distance <= 0
+  int RecMII = II; //Starting value
+  int value = totalDelay-(RecMII * totalDistance);
+  int lastII = II;
+  while(value < 0) {
+	  
+    lastII = RecMII;
+    RecMII--;
+    value = totalDelay-(RecMII * totalDistance);
+  }
+
+  recurrenceList.insert(std::make_pair(lastII, recc));
+
+}
+
+
+void ModuloSchedulingSBPass::findAllCircuits(MSchedGraphSB *g, int II) {
+
+  CircCountSB = 0;
+
+  //Keep old to new node mapping information
+  std::map<MSchedGraphSBNode*, MSchedGraphSBNode*> newNodes;
+
+  //copy the graph
+  MSchedGraphSB *MSG = new MSchedGraphSB(*g, newNodes);
+
+  DEBUG(std::cerr << "Finding All Circuits\n");
+
+  //Set of blocked nodes
+  std::set<MSchedGraphSBNode*> blocked;
+
+  //Stack holding current circuit
+  std::vector<MSchedGraphSBNode*> stack;
+
+  //Map for B Lists
+  std::map<MSchedGraphSBNode*, std::set<MSchedGraphSBNode*> > B;
+
+  //current node
+  MSchedGraphSBNode *s;
+
+
+  //Iterate over the graph until its down to one node or empty
+  while(MSG->size() > 1) {
+
+    //Write Graph out to file
+    //WriteGraphToFile(std::cerr, "Graph" + utostr(MSG->size()), MSG);
+
+    DEBUG(std::cerr << "Graph Size: " << MSG->size() << "\n");
+    DEBUG(std::cerr << "Finding strong component Vk with least vertex\n");
+
+    //Iterate over all the SCCs in the graph
+    std::set<MSchedGraphSBNode*> Visited;
+    std::vector<MSchedGraphSBNode*> Vk;
+    MSchedGraphSBNode* s = 0;
+    int numEdges = 0;
+
+    //Find scc with the least vertex
+    for (MSchedGraphSB::iterator GI = MSG->begin(), E = MSG->end(); GI != E; ++GI)
+      if (Visited.insert(GI->second).second) {
+	for (scc_iterator<MSchedGraphSBNode*> SCCI = scc_begin(GI->second),
+	       E = scc_end(GI->second); SCCI != E; ++SCCI) {
+	  std::vector<MSchedGraphSBNode*> &nextSCC = *SCCI;
+
+	  if (Visited.insert(nextSCC[0]).second) {
+	    Visited.insert(nextSCC.begin()+1, nextSCC.end());
+
+	    if(nextSCC.size() > 1) {
+	      DEBUG(std::cerr << "SCC size: " << nextSCC.size() << "\n");
+	      
+	      for(unsigned i = 0; i < nextSCC.size(); ++i) {
+		//Loop over successor and see if in scc, then count edge
+		MSchedGraphSBNode *node = nextSCC[i];
+		for(MSchedGraphSBNode::succ_iterator S = node->succ_begin(), SE = node->succ_end(); S != SE; ++S) {
+		  if(find(nextSCC.begin(), nextSCC.end(), *S) != nextSCC.end())
+		    numEdges++;
+		}
+	      }
+	      DEBUG(std::cerr << "Num Edges: " << numEdges << "\n");
+	    }
+	    
+	    //Ignore self loops
+	    if(nextSCC.size() > 1) {
+
+	      //Get least vertex in Vk
+	      if(!s) {
+		s = nextSCC[0];
+		Vk = nextSCC;
+	      }
+
+	      for(unsigned i = 0; i < nextSCC.size(); ++i) {
+		if(nextSCC[i] < s) {
+		  s = nextSCC[i];
+		  Vk = nextSCC;
+		}
+	      }
+	    }
+	  }
+	}
+      }
+
+
+
+    //Process SCC
+    DEBUG(for(std::vector<MSchedGraphSBNode*>::iterator N = Vk.begin(), NE = Vk.end();
+	      N != NE; ++N) { std::cerr << *((*N)->getInst()); });
+
+    //Iterate over all nodes in this scc
+    for(std::vector<MSchedGraphSBNode*>::iterator N = Vk.begin(), NE = Vk.end();
+	N != NE; ++N) {
+      blocked.erase(*N);
+      B[*N].clear();
+    }
+    if(Vk.size() > 1) {
+      if(numEdges < 98)
+	circuit(s, stack, blocked, Vk, s, B, II, newNodes);
+      else
+	addSCC(Vk, newNodes);
+
+
+      //Delete nodes from the graph
+      //Find all nodes up to s and delete them
+      std::vector<MSchedGraphSBNode*> nodesToRemove;
+      nodesToRemove.push_back(s);
+      for(MSchedGraphSB::iterator N = MSG->begin(), NE = MSG->end(); N != NE; ++N) {
+	if(N->second < s )
+	    nodesToRemove.push_back(N->second);
+      }
+      for(std::vector<MSchedGraphSBNode*>::iterator N = nodesToRemove.begin(), NE = nodesToRemove.end(); N != NE; ++N) {
+	DEBUG(std::cerr << "Deleting Node: " << **N << "\n");
+	MSG->deleteNode(*N);
+      }
+    }
+    else
+      break;
+  }    
+  DEBUG(std::cerr << "Num Circuits found: " << CircCountSB << "\n");
+}
+/// calculateNodeAttributes - The following properties are calculated for
+/// each node in the dependence graph: ASAP, ALAP, Depth, Height, and
+/// MOB.
+void ModuloSchedulingSBPass::calculateNodeAttributes(MSchedGraphSB *graph, int MII) {
+
+  TIME_REGION(X, "calculateNodeAttributes");
+
+  assert(nodeToAttributesMap.empty() && "Node attribute map was not cleared");
+
+  //Loop over the nodes and add them to the map
+  for(MSchedGraphSB::iterator I = graph->begin(), E = graph->end(); I != E; ++I) {
+
+    DEBUG(std::cerr << "Inserting node into attribute map: " << *I->second << "\n");
+
+    //Assert if its already in the map
+    assert(nodeToAttributesMap.count(I->second) == 0 &&
+	   "Node attributes are already in the map");
+
+    //Put into the map with default attribute values
+    nodeToAttributesMap[I->second] = MSNodeSBAttributes();
+  }
+
+  //Create set to deal with reccurrences
+  std::set<MSchedGraphSBNode*> visitedNodes;
+
+  //Now Loop over map and calculate the node attributes
+  for(std::map<MSchedGraphSBNode*, MSNodeSBAttributes>::iterator I = nodeToAttributesMap.begin(), E = nodeToAttributesMap.end(); I != E; ++I) {
+    calculateASAP(I->first, MII, (MSchedGraphSBNode*) 0);
+    visitedNodes.clear();
+  }
+
+  int maxASAP = findMaxASAP();
+  //Calculate ALAP which depends on ASAP being totally calculated
+  for(std::map<MSchedGraphSBNode*, MSNodeSBAttributes>::iterator I = nodeToAttributesMap.begin(), E = nodeToAttributesMap.end(); I != E; ++I) {
+    calculateALAP(I->first, MII, maxASAP, (MSchedGraphSBNode*) 0);
+    visitedNodes.clear();
+  }
+
+  //Calculate MOB which depends on ASAP being totally calculated, also do depth and height
+  for(std::map<MSchedGraphSBNode*, MSNodeSBAttributes>::iterator I = nodeToAttributesMap.begin(), E = nodeToAttributesMap.end(); I != E; ++I) {
+    (I->second).MOB = std::max(0,(I->second).ALAP - (I->second).ASAP);
+
+    DEBUG(std::cerr << "MOB: " << (I->second).MOB << " (" << *(I->first) << ")\n");
+    calculateDepth(I->first, (MSchedGraphSBNode*) 0);
+    calculateHeight(I->first, (MSchedGraphSBNode*) 0);
+  }
+
+
+}
+
+/// ignoreEdge - Checks to see if this edge of a recurrence should be ignored or not
+bool ModuloSchedulingSBPass::ignoreEdge(MSchedGraphSBNode *srcNode, MSchedGraphSBNode *destNode) {
+  if(destNode == 0 || srcNode ==0)
+    return false;
+
+  bool findEdge = edgesToIgnore.count(std::make_pair(srcNode, destNode->getInEdgeNum(srcNode)));
+
+  DEBUG(std::cerr << "Ignoring edge? from: " << *srcNode << " to " << *destNode << "\n");
+
+  return findEdge;
+}
+
+
+/// calculateASAP - Calculates the
+int  ModuloSchedulingSBPass::calculateASAP(MSchedGraphSBNode *node, int MII, MSchedGraphSBNode *destNode) {
+
+  DEBUG(std::cerr << "Calculating ASAP for " << *node << "\n");
+
+  //Get current node attributes
+  MSNodeSBAttributes &attributes = nodeToAttributesMap.find(node)->second;
+
+  if(attributes.ASAP != -1)
+    return attributes.ASAP;
+
+  int maxPredValue = 0;
+
+  //Iterate over all of the predecessors and find max
+  for(MSchedGraphSBNode::pred_iterator P = node->pred_begin(), E = node->pred_end(); P != E; ++P) {
+
+    //Only process if we are not ignoring the edge
+    if(!ignoreEdge(*P, node)) {
+      int predASAP = -1;
+      predASAP = calculateASAP(*P, MII, node);
+
+      assert(predASAP != -1 && "ASAP has not been calculated");
+      int iteDiff = node->getInEdge(*P).getIteDiff();
+
+      int currentPredValue = predASAP + (*P)->getLatency() - (iteDiff * MII);
+      DEBUG(std::cerr << "pred ASAP: " << predASAP << ", iteDiff: " << iteDiff << ", PredLatency: " << (*P)->getLatency() << ", Current ASAP pred: " << currentPredValue << "\n");
+      maxPredValue = std::max(maxPredValue, currentPredValue);
+    }
+  }
+
+  attributes.ASAP = maxPredValue;
+
+  DEBUG(std::cerr << "ASAP: " << attributes.ASAP << " (" << *node << ")\n");
+
+  return maxPredValue;
+}
+
+
+int ModuloSchedulingSBPass::calculateALAP(MSchedGraphSBNode *node, int MII,
+					int maxASAP, MSchedGraphSBNode *srcNode) {
+
+  DEBUG(std::cerr << "Calculating ALAP for " << *node << "\n");
+
+  MSNodeSBAttributes &attributes = nodeToAttributesMap.find(node)->second;
+
+  if(attributes.ALAP != -1)
+    return attributes.ALAP;
+
+  if(node->hasSuccessors()) {
+
+    //Trying to deal with the issue where the node has successors, but
+    //we are ignoring all of the edges to them. So this is my hack for
+    //now.. there is probably a more elegant way of doing this (FIXME)
+    bool processedOneEdge = false;
+
+    //FIXME, set to something high to start
+    int minSuccValue = 9999999;
+
+    //Iterate over all of the predecessors and fine max
+    for(MSchedGraphSBNode::succ_iterator P = node->succ_begin(),
+	  E = node->succ_end(); P != E; ++P) {
+
+      //Only process if we are not ignoring the edge
+      if(!ignoreEdge(node, *P)) {
+	processedOneEdge = true;
+	int succALAP = -1;
+	succALAP = calculateALAP(*P, MII, maxASAP, node);
+	
+	assert(succALAP != -1 && "Successors ALAP should have been caclulated");
+	
+	int iteDiff = P.getEdge().getIteDiff();
+	
+	int currentSuccValue = succALAP - node->getLatency() + iteDiff * MII;
+	
+	DEBUG(std::cerr << "succ ALAP: " << succALAP << ", iteDiff: " << iteDiff << ", SuccLatency: " << (*P)->getLatency() << ", Current ALAP succ: " << currentSuccValue << "\n");
+
+	minSuccValue = std::min(minSuccValue, currentSuccValue);
+      }
+    }
+
+    if(processedOneEdge)
+    	attributes.ALAP = minSuccValue;
+
+    else
+      attributes.ALAP = maxASAP;
+  }
+  else
+    attributes.ALAP = maxASAP;
+
+  DEBUG(std::cerr << "ALAP: " << attributes.ALAP << " (" << *node << ")\n");
+
+  if(attributes.ALAP < 0)
+    attributes.ALAP = 0;
+
+  return attributes.ALAP;
+}
+
+int ModuloSchedulingSBPass::findMaxASAP() {
+  int maxASAP = 0;
+
+  for(std::map<MSchedGraphSBNode*, MSNodeSBAttributes>::iterator I = nodeToAttributesMap.begin(),
+	E = nodeToAttributesMap.end(); I != E; ++I)
+    maxASAP = std::max(maxASAP, I->second.ASAP);
+  return maxASAP;
+}
+
+
+int ModuloSchedulingSBPass::calculateHeight(MSchedGraphSBNode *node,MSchedGraphSBNode *srcNode) {
+
+  MSNodeSBAttributes &attributes = nodeToAttributesMap.find(node)->second;
+
+  if(attributes.height != -1)
+    return attributes.height;
+
+  int maxHeight = 0;
+
+  //Iterate over all of the predecessors and find max
+  for(MSchedGraphSBNode::succ_iterator P = node->succ_begin(),
+	E = node->succ_end(); P != E; ++P) {
+
+
+    if(!ignoreEdge(node, *P)) {
+      int succHeight = calculateHeight(*P, node);
+
+      assert(succHeight != -1 && "Successors Height should have been caclulated");
+
+      int currentHeight = succHeight + node->getLatency();
+      maxHeight = std::max(maxHeight, currentHeight);
+    }
+  }
+  attributes.height = maxHeight;
+  DEBUG(std::cerr << "Height: " << attributes.height << " (" << *node << ")\n");
+  return maxHeight;
+}
+
+
+int ModuloSchedulingSBPass::calculateDepth(MSchedGraphSBNode *node,
+					  MSchedGraphSBNode *destNode) {
+
+  MSNodeSBAttributes &attributes = nodeToAttributesMap.find(node)->second;
+
+  if(attributes.depth != -1)
+    return attributes.depth;
+
+  int maxDepth = 0;
+
+  //Iterate over all of the predecessors and fine max
+  for(MSchedGraphSBNode::pred_iterator P = node->pred_begin(), E = node->pred_end(); P != E; ++P) {
+
+    if(!ignoreEdge(*P, node)) {
+      int predDepth = -1;
+      predDepth = calculateDepth(*P, node);
+
+      assert(predDepth != -1 && "Predecessors ASAP should have been caclulated");
+
+      int currentDepth = predDepth + (*P)->getLatency();
+      maxDepth = std::max(maxDepth, currentDepth);
+    }
+  }
+  attributes.depth = maxDepth;
+
+  DEBUG(std::cerr << "Depth: " << attributes.depth << " (" << *node << "*)\n");
+  return maxDepth;
+}
+
+void ModuloSchedulingSBPass::computePartialOrder() {
+
+  TIME_REGION(X, "calculatePartialOrder");
+  
+  DEBUG(std::cerr << "Computing Partial Order\n");
+
+  //Steps to add a recurrence to the partial order 1) Find reccurrence
+  //with the highest RecMII. Add it to the partial order.  2) For each
+  //recurrence with decreasing RecMII, add it to the partial order
+  //along with any nodes that connect this recurrence to recurrences
+  //already in the partial order
+  for(std::set<std::pair<int, std::vector<MSchedGraphSBNode*> > >::reverse_iterator 
+	I = recurrenceList.rbegin(), E=recurrenceList.rend(); I !=E; ++I) {
+
+    std::set<MSchedGraphSBNode*> new_recurrence;
+
+    //Loop through recurrence and remove any nodes already in the partial order
+    for(std::vector<MSchedGraphSBNode*>::const_iterator N = I->second.begin(),
+	  NE = I->second.end(); N != NE; ++N) {
+
+      bool found = false;
+      for(std::vector<std::set<MSchedGraphSBNode*> >::iterator PO = partialOrder.begin(),
+	    PE = partialOrder.end(); PO != PE; ++PO) {
+	if(PO->count(*N))
+	  found = true;
+      }
+
+      //Check if its a branch, and remove to handle special
+      if(!found) {
+	new_recurrence.insert(*N);
+      }
+
+    }
+
+
+    if(new_recurrence.size() > 0) {
+
+      std::vector<MSchedGraphSBNode*> path;
+      std::set<MSchedGraphSBNode*> nodesToAdd;
+
+      //Dump recc we are dealing with (minus nodes already in PO)
+      DEBUG(std::cerr << "Recc: ");
+      DEBUG(for(std::set<MSchedGraphSBNode*>::iterator R = new_recurrence.begin(), RE = new_recurrence.end(); R != RE; ++R) { std::cerr << **R ; });
+
+      //Add nodes that connect this recurrence to recurrences in the partial path
+      for(std::set<MSchedGraphSBNode*>::iterator N = new_recurrence.begin(),
+          NE = new_recurrence.end(); N != NE; ++N)
+	searchPath(*N, path, nodesToAdd, new_recurrence);
+
+      //Add nodes to this recurrence if they are not already in the partial order
+      for(std::set<MSchedGraphSBNode*>::iterator N = nodesToAdd.begin(), NE = nodesToAdd.end();
+	  N != NE; ++N) {
+	bool found = false;
+	for(std::vector<std::set<MSchedGraphSBNode*> >::iterator PO = partialOrder.begin(),
+	      PE = partialOrder.end(); PO != PE; ++PO) {
+	  if(PO->count(*N))
+	    found = true;
+	}
+	if(!found) {
+	  assert("FOUND CONNECTOR");
+	  new_recurrence.insert(*N);
+	}
+      }
+
+      partialOrder.push_back(new_recurrence);
+    }
+  }
+
+  //Add any nodes that are not already in the partial order
+  //Add them in a set, one set per connected component
+  std::set<MSchedGraphSBNode*> lastNodes;
+  std::set<MSchedGraphSBNode*> noPredNodes;
+  for(std::map<MSchedGraphSBNode*, MSNodeSBAttributes>::iterator I = nodeToAttributesMap.begin(),
+	E = nodeToAttributesMap.end(); I != E; ++I) {
+
+    bool found = false;
+
+    //Check if its already in our partial order, if not add it to the final vector
+    for(std::vector<std::set<MSchedGraphSBNode*> >::iterator PO = partialOrder.begin(),
+	  PE = partialOrder.end(); PO != PE; ++PO) {
+      if(PO->count(I->first))
+	found = true;
+    }
+    if(!found)
+      lastNodes.insert(I->first);
+  }
+
+  //For each node w/out preds, see if there is a path to one of the
+  //recurrences, and if so add them to that current recc
+  /*for(std::set<MSchedGraphSBNode*>::iterator N = noPredNodes.begin(), NE = noPredNodes.end();
+      N != NE; ++N) {
+    DEBUG(std::cerr << "No Pred Path from: " << **N << "\n");
+    for(std::vector<std::set<MSchedGraphSBNode*> >::iterator PO = partialOrder.begin(),
+	  PE = partialOrder.end(); PO != PE; ++PO) {
+      std::vector<MSchedGraphSBNode*> path;
+      pathToRecc(*N, path, *PO, lastNodes);
+    }
+    }*/
+
+
+  //Break up remaining nodes that are not in the partial order
+  ///into their connected compoenents
+    while(lastNodes.size() > 0) {
+      std::set<MSchedGraphSBNode*> ccSet;
+      connectedComponentSet(*(lastNodes.begin()),ccSet, lastNodes);
+      if(ccSet.size() > 0)
+	partialOrder.push_back(ccSet);
+    }
+
+}
+
+void ModuloSchedulingSBPass::connectedComponentSet(MSchedGraphSBNode *node, std::set<MSchedGraphSBNode*> &ccSet, std::set<MSchedGraphSBNode*> &lastNodes) {
+  
+  //Add to final set
+  if( !ccSet.count(node) && lastNodes.count(node)) {
+    lastNodes.erase(node);
+    ccSet.insert(node);
+  }
+  else
+    return;
+
+  //Loop over successors and recurse if we have not seen this node before
+  for(MSchedGraphSBNode::succ_iterator node_succ = node->succ_begin(), end=node->succ_end(); node_succ != end; ++node_succ) {
+    connectedComponentSet(*node_succ, ccSet, lastNodes);
+  }
+
+}
+
+void ModuloSchedulingSBPass::searchPath(MSchedGraphSBNode *node,
+				      std::vector<MSchedGraphSBNode*> &path,
+				      std::set<MSchedGraphSBNode*> &nodesToAdd,
+				     std::set<MSchedGraphSBNode*> &new_reccurrence) {
+  //Push node onto the path
+  path.push_back(node);
+
+  //Loop over all successors and see if there is a path from this node to
+  //a recurrence in the partial order, if so.. add all nodes to be added to recc
+  for(MSchedGraphSBNode::succ_iterator S = node->succ_begin(), SE = node->succ_end(); S != SE;
+      ++S) {
+
+    //Check if we should ignore this edge first
+    if(ignoreEdge(node,*S))
+      continue;
+    
+    //check if successor is in this recurrence, we will get to it eventually
+    if(new_reccurrence.count(*S))
+      continue;
+
+    //If this node exists in a recurrence already in the partial
+    //order, then add all nodes in the path to the set of nodes to add
+     //Check if its already in our partial order, if not add it to the
+     //final vector
+    bool found = false;
+    for(std::vector<std::set<MSchedGraphSBNode*> >::iterator PO = partialOrder.begin(),
+	  PE = partialOrder.end(); PO != PE; ++PO) {
+
+      if(PO->count(*S)) {
+	found = true;
+	break;
+      }
+    }
+
+    if(!found) {
+      nodesToAdd.insert(*S);
+      searchPath(*S, path, nodesToAdd, new_reccurrence);
+    }
+  }
+
+  //Pop Node off the path
+  path.pop_back();
+}
+
+void dumpIntersection(std::set<MSchedGraphSBNode*> &IntersectCurrent) {
+  std::cerr << "Intersection (";
+  for(std::set<MSchedGraphSBNode*>::iterator I = IntersectCurrent.begin(), E = IntersectCurrent.end(); I != E; ++I)
+    std::cerr << **I << ", ";
+  std::cerr << ")\n";
+}
+
+void ModuloSchedulingSBPass::orderNodes() {
+
+  TIME_REGION(X, "orderNodes");
+
+  int BOTTOM_UP = 0;
+  int TOP_DOWN = 1;
+
+  //Set default order
+  int order = BOTTOM_UP;
+
+  //Loop over and find all pred nodes and schedule them first
+  /*for(std::vector<std::set<MSchedGraphSBNode*> >::iterator CurrentSet = partialOrder.begin(), E= partialOrder.end(); CurrentSet != E; ++CurrentSet) {
+    for(std::set<MSchedGraphSBNode*>::iterator N = CurrentSet->begin(), NE = CurrentSet->end(); N != NE; ++N)
+      if((*N)->isPredicate()) {
+	FinalNodeOrder.push_back(*N);
+	CurrentSet->erase(*N);
+      }
+      }*/
+
+
+
+  //Loop over all the sets and place them in the final node order
+  for(std::vector<std::set<MSchedGraphSBNode*> >::iterator CurrentSet = partialOrder.begin(), E= partialOrder.end(); CurrentSet != E; ++CurrentSet) {
+
+    DEBUG(std::cerr << "Processing set in S\n");
+    DEBUG(dumpIntersection(*CurrentSet));
+
+    //Result of intersection
+    std::set<MSchedGraphSBNode*> IntersectCurrent;
+
+    predIntersect(*CurrentSet, IntersectCurrent);
+
+    //If the intersection of predecessor and current set is not empty
+    //sort nodes bottom up
+    if(IntersectCurrent.size() != 0) {
+      DEBUG(std::cerr << "Final Node Order Predecessors and Current Set interesection is NOT empty\n");
+      order = BOTTOM_UP;
+    }
+    //If empty, use successors
+    else {
+      DEBUG(std::cerr << "Final Node Order Predecessors and Current Set interesection is empty\n");
+
+      succIntersect(*CurrentSet, IntersectCurrent);
+
+      //sort top-down
+      if(IntersectCurrent.size() != 0) {
+	 DEBUG(std::cerr << "Final Node Order Successors and Current Set interesection is NOT empty\n");
+	order = TOP_DOWN;
+      }
+      else {
+	DEBUG(std::cerr << "Final Node Order Successors and Current Set interesection is empty\n");
+	//Find node with max ASAP in current Set
+	MSchedGraphSBNode *node;
+	int maxASAP = 0;
+	DEBUG(std::cerr << "Using current set of size " << CurrentSet->size() << "to find max ASAP\n");
+	for(std::set<MSchedGraphSBNode*>::iterator J = CurrentSet->begin(), JE = CurrentSet->end(); J != JE; ++J) {
+	  //Get node attributes
+	  MSNodeSBAttributes nodeAttr= nodeToAttributesMap.find(*J)->second;
+	  //assert(nodeAttr != nodeToAttributesMap.end() && "Node not in attributes map!");
+	
+	  if(maxASAP <= nodeAttr.ASAP) {
+	    maxASAP = nodeAttr.ASAP;
+	    node = *J;
+	  }
+	}
+	assert(node != 0 && "In node ordering node should not be null");
+	IntersectCurrent.insert(node);
+	order = BOTTOM_UP;
+      }
+    }
+
+    //Repeat until all nodes are put into the final order from current set
+    while(IntersectCurrent.size() > 0) {
+
+      if(order == TOP_DOWN) {
+	DEBUG(std::cerr << "Order is TOP DOWN\n");
+
+	while(IntersectCurrent.size() > 0) {
+	  DEBUG(std::cerr << "Intersection is not empty, so find heighest height\n");
+	
+	  int MOB = 0;
+	  int height = 0;
+	  MSchedGraphSBNode *highestHeightNode = *(IntersectCurrent.begin());
+	  	
+	  //Find node in intersection with highest heigh and lowest MOB
+	  for(std::set<MSchedGraphSBNode*>::iterator I = IntersectCurrent.begin(),
+		E = IntersectCurrent.end(); I != E; ++I) {
+	
+	    //Get current nodes properties
+	    MSNodeSBAttributes nodeAttr= nodeToAttributesMap.find(*I)->second;
+
+	    if(height < nodeAttr.height) {
+	      highestHeightNode = *I;
+	      height = nodeAttr.height;
+	      MOB = nodeAttr.MOB;
+	    }
+	    else if(height ==  nodeAttr.height) {
+	      if(MOB > nodeAttr.height) {
+		highestHeightNode = *I;
+		height =  nodeAttr.height;
+		MOB = nodeAttr.MOB;
+	      }
+	    }
+	  }
+	
+	  //Append our node with greatest height to the NodeOrder
+	  if(std::find(FinalNodeOrder.begin(), FinalNodeOrder.end(), highestHeightNode) == FinalNodeOrder.end()) {
+	    DEBUG(std::cerr << "Adding node to Final Order: " << *highestHeightNode << "\n");
+	    FinalNodeOrder.push_back(highestHeightNode);
+	  }
+
+	  //Remove V from IntersectOrder
+	  IntersectCurrent.erase(std::find(IntersectCurrent.begin(),
+				      IntersectCurrent.end(), highestHeightNode));
+
+
+	  //Intersect V's successors with CurrentSet
+	  for(MSchedGraphSBNode::succ_iterator P = highestHeightNode->succ_begin(),
+		E = highestHeightNode->succ_end(); P != E; ++P) {
+	    //if(lower_bound(CurrentSet->begin(),
+	    //	   CurrentSet->end(), *P) != CurrentSet->end()) {
+	    if(std::find(CurrentSet->begin(), CurrentSet->end(), *P) != CurrentSet->end()) {
+	      if(ignoreEdge(highestHeightNode, *P))
+		continue;
+	      //If not already in Intersect, add
+	      if(!IntersectCurrent.count(*P))
+		IntersectCurrent.insert(*P);
+	    }
+	  }
+     	} //End while loop over Intersect Size
+
+	//Change direction
+	order = BOTTOM_UP;
+
+	//Reset Intersect to reflect changes in OrderNodes
+	IntersectCurrent.clear();
+	predIntersect(*CurrentSet, IntersectCurrent);
+	
+      } //End If TOP_DOWN
+	
+	//Begin if BOTTOM_UP
+      else {
+	DEBUG(std::cerr << "Order is BOTTOM UP\n");
+	while(IntersectCurrent.size() > 0) {
+	  DEBUG(std::cerr << "Intersection of size " << IntersectCurrent.size() << ", finding highest depth\n");
+
+	  //dump intersection
+	  DEBUG(dumpIntersection(IntersectCurrent));
+	  //Get node with highest depth, if a tie, use one with lowest
+	  //MOB
+	  int MOB = 0;
+	  int depth = 0;
+	  MSchedGraphSBNode *highestDepthNode = *(IntersectCurrent.begin());
+	
+	  for(std::set<MSchedGraphSBNode*>::iterator I = IntersectCurrent.begin(),
+		E = IntersectCurrent.end(); I != E; ++I) {
+	    //Find node attribute in graph
+	    MSNodeSBAttributes nodeAttr= nodeToAttributesMap.find(*I)->second;
+	
+	    if(depth < nodeAttr.depth) {
+	      highestDepthNode = *I;
+	      depth = nodeAttr.depth;
+	      MOB = nodeAttr.MOB;
+	    }
+	    else if(depth == nodeAttr.depth) {
+	      if(MOB > nodeAttr.MOB) {
+		highestDepthNode = *I;
+		depth = nodeAttr.depth;
+		MOB = nodeAttr.MOB;
+	      }
+	    }
+	  }
+	
+	
+
+	  //Append highest depth node to the NodeOrder
+	   if(std::find(FinalNodeOrder.begin(), FinalNodeOrder.end(), highestDepthNode) == FinalNodeOrder.end()) {
+	     DEBUG(std::cerr << "Adding node to Final Order: " << *highestDepthNode << "\n");
+	     FinalNodeOrder.push_back(highestDepthNode);
+	   }
+	  //Remove heightestDepthNode from IntersectOrder
+	   IntersectCurrent.erase(highestDepthNode);
+	
+
+	  //Intersect heightDepthNode's pred with CurrentSet
+	  for(MSchedGraphSBNode::pred_iterator P = highestDepthNode->pred_begin(),
+		E = highestDepthNode->pred_end(); P != E; ++P) {
+	    if(CurrentSet->count(*P)) {
+	      if(ignoreEdge(*P, highestDepthNode))
+		continue;
+	
+	    //If not already in Intersect, add
+	    if(!IntersectCurrent.count(*P))
+	      IntersectCurrent.insert(*P);
+	    }
+	  }
+	
+	} //End while loop over Intersect Size
+	
+	  //Change order
+	order = TOP_DOWN;
+	
+	//Reset IntersectCurrent to reflect changes in OrderNodes
+	IntersectCurrent.clear();
+	succIntersect(*CurrentSet, IntersectCurrent);
+	} //End if BOTTOM_DOWN
+	
+      DEBUG(std::cerr << "Current Intersection Size: " << IntersectCurrent.size() << "\n");
+    }
+    //End Wrapping while loop
+    DEBUG(std::cerr << "Ending Size of Current Set: " << CurrentSet->size() << "\n");
+  }//End for over all sets of nodes
+
+  //FIXME: As the algorithm stands it will NEVER add an instruction such as ba (with no
+  //data dependencies) to the final order. We add this manually. It will always be
+  //in the last set of S since its not part of a recurrence
+    //Loop over all the sets and place them in the final node order
+  std::vector<std::set<MSchedGraphSBNode*> > ::reverse_iterator LastSet = partialOrder.rbegin();
+  for(std::set<MSchedGraphSBNode*>::iterator CurrentNode = LastSet->begin(), LastNode = LastSet->end();
+      CurrentNode != LastNode; ++CurrentNode) {
+    if((*CurrentNode)->getInst()->getOpcode() == V9::BA)
+      FinalNodeOrder.push_back(*CurrentNode);
+  }
+  //Return final Order
+  //return FinalNodeOrder;
+}
+
+
+void ModuloSchedulingSBPass::predIntersect(std::set<MSchedGraphSBNode*> &CurrentSet, std::set<MSchedGraphSBNode*> &IntersectResult) {
+
+  for(unsigned j=0; j < FinalNodeOrder.size(); ++j) {
+    for(MSchedGraphSBNode::pred_iterator P = FinalNodeOrder[j]->pred_begin(),
+	  E = FinalNodeOrder[j]->pred_end(); P != E; ++P) {
+
+      //Check if we are supposed to ignore this edge or not
+      if(ignoreEdge(*P,FinalNodeOrder[j]))
+	continue;
+	
+      if(CurrentSet.count(*P))
+	if(std::find(FinalNodeOrder.begin(), FinalNodeOrder.end(), *P) == FinalNodeOrder.end())
+	  IntersectResult.insert(*P);
+    }
+  }
+}
+
+void ModuloSchedulingSBPass::succIntersect(std::set<MSchedGraphSBNode*> &CurrentSet, std::set<MSchedGraphSBNode*> &IntersectResult) {
+
+  for(unsigned j=0; j < FinalNodeOrder.size(); ++j) {
+    for(MSchedGraphSBNode::succ_iterator P = FinalNodeOrder[j]->succ_begin(),
+	  E = FinalNodeOrder[j]->succ_end(); P != E; ++P) {
+
+      //Check if we are supposed to ignore this edge or not
+      if(ignoreEdge(FinalNodeOrder[j],*P))
+	continue;
+
+      if(CurrentSet.count(*P))
+	if(std::find(FinalNodeOrder.begin(), FinalNodeOrder.end(), *P) == FinalNodeOrder.end())
+	  IntersectResult.insert(*P);
+    }
+  }
+}
+
+
+
+bool ModuloSchedulingSBPass::computeSchedule(std::vector<const MachineBasicBlock*> &SB, MSchedGraphSB *MSG) {
+
+  TIME_REGION(X, "computeSchedule");
+
+  bool success = false;
+
+  //FIXME: Should be set to max II of the original loop
+  //Cap II in order to prevent infinite loop
+  int capII = MSG->totalDelay();
+
+  while(!success) {
+
+    //Keep track of branches, but do not insert into the schedule
+    std::vector<MSchedGraphSBNode*> branches;
+
+    //Loop over the final node order and process each node
+    for(std::vector<MSchedGraphSBNode*>::iterator I = FinalNodeOrder.begin(),
+	  E = FinalNodeOrder.end(); I != E; ++I) {
+
+      //CalculateEarly and Late start
+      bool initialLSVal = false;
+      bool initialESVal = false;
+      int EarlyStart = 0;
+      int LateStart = 0; 
+      bool hasSucc = false;
+      bool hasPred = false;
+      bool sched;
+
+      if((*I)->isBranch())
+	if((*I)->hasPredecessors())
+	  sched = true;
+	else
+	  sched = false;
+      else
+	sched = true;
+
+      if(sched) {
+	//Loop over nodes in the schedule and determine if they are predecessors
+	//or successors of the node we are trying to schedule
+	for(MSScheduleSB::schedule_iterator nodesByCycle = schedule.begin(), nodesByCycleEnd = schedule.end();
+	    nodesByCycle != nodesByCycleEnd; ++nodesByCycle) {
+	
+	  //For this cycle, get the vector of nodes schedule and loop over it
+	  for(std::vector<MSchedGraphSBNode*>::iterator schedNode = nodesByCycle->second.begin(), SNE = nodesByCycle->second.end(); schedNode != SNE; ++schedNode) {
+	
+	    if((*I)->isPredecessor(*schedNode)) {
+	      int diff = (*I)->getInEdge(*schedNode).getIteDiff();
+	      int ES_Temp = nodesByCycle->first + (*schedNode)->getLatency() - diff * II;
+	      DEBUG(std::cerr << "Diff: " << diff << " Cycle: " << nodesByCycle->first << "\n");
+	      DEBUG(std::cerr << "Temp EarlyStart: " << ES_Temp << " Prev EarlyStart: " << EarlyStart << "\n");
+	      if(initialESVal)
+		EarlyStart = std::max(EarlyStart, ES_Temp);
+	      else {
+		EarlyStart = ES_Temp;
+		initialESVal = true;
+	      }
+	      hasPred = true;
+	    }
+	    if((*I)->isSuccessor(*schedNode)) {
+	      int diff = (*schedNode)->getInEdge(*I).getIteDiff();
+	      int LS_Temp = nodesByCycle->first - (*I)->getLatency() + diff * II;
+	      DEBUG(std::cerr << "Diff: " << diff << " Cycle: " << nodesByCycle->first << "\n");
+	      DEBUG(std::cerr << "Temp LateStart: " << LS_Temp << " Prev LateStart: " << LateStart << "\n");
+	      if(initialLSVal)
+		LateStart = std::min(LateStart, LS_Temp);
+	      else {
+		LateStart = LS_Temp;
+		initialLSVal = true;
+	      }
+	      hasSucc = true;
+	    }
+	  }
+	}
+      }
+      else {
+	branches.push_back(*I);
+	continue;
+      }
+
+      //Check if the node has no pred or successors and set Early Start to its ASAP
+      if(!hasSucc && !hasPred)
+	EarlyStart = nodeToAttributesMap.find(*I)->second.ASAP;
+
+      DEBUG(std::cerr << "Has Successors: " << hasSucc << ", Has Pred: " << hasPred << "\n");
+      DEBUG(std::cerr << "EarlyStart: " << EarlyStart << ", LateStart: " << LateStart << "\n");
+
+      //Now, try to schedule this node depending upon its pred and successor in the schedule
+      //already
+      if(!hasSucc && hasPred)
+	success = scheduleNode(*I, EarlyStart, (EarlyStart + II -1));
+      else if(!hasPred && hasSucc)
+	success = scheduleNode(*I, LateStart, (LateStart - II +1));
+      else if(hasPred && hasSucc) {
+	if(EarlyStart > LateStart) {
+	success = false;
+	  //LateStart = EarlyStart;
+	  DEBUG(std::cerr << "Early Start can not be later then the late start cycle, schedule fails\n");
+	}
+      	else
+	  success = scheduleNode(*I, EarlyStart, std::min(LateStart, (EarlyStart + II -1)));
+      }
+      else
+	success = scheduleNode(*I, EarlyStart, EarlyStart + II - 1);
+
+      if(!success) {
+	++II; 
+	schedule.clear();
+	break;
+      }
+
+    }
+
+    if(success) {
+      DEBUG(std::cerr << "Constructing Schedule Kernel\n");
+      success = schedule.constructKernel(II, branches, indVarInstrs[SB]);
+      DEBUG(std::cerr << "Done Constructing Schedule Kernel\n");
+      if(!success) {
+	++II;
+	schedule.clear();
+      }
+      DEBUG(std::cerr << "Final II: " << II << "\n");
+     
+    }
+
+    if(II >= capII) {
+      DEBUG(std::cerr << "Maximum II reached, giving up\n");
+      return false;
+    }
+
+    assert(II < capII && "The II should not exceed the original loop number of cycles");
+  }
+  return true;
+}
+
+
+bool ModuloSchedulingSBPass::scheduleNode(MSchedGraphSBNode *node,
+				      int start, int end) {
+  bool success = false;
+
+  DEBUG(std::cerr << *node << " (Start Cycle: " << start << ", End Cycle: " << end << ")\n");
+
+  //Make sure start and end are not negative
+  //if(start < 0) {
+  //start = 0;
+
+  //}
+  //if(end < 0)
+  //end = 0;
+
+  bool forward = true;
+  if(start > end)
+    forward = false;
+
+  bool increaseSC = true;
+  int cycle = start ;
+
+
+  while(increaseSC) {
+
+    increaseSC = false;
+
+    increaseSC = schedule.insert(node, cycle, II);
+
+    if(!increaseSC)
+      return true;
+
+    //Increment cycle to try again
+    if(forward) {
+      ++cycle;
+      DEBUG(std::cerr << "Increase cycle: " << cycle << "\n");
+      if(cycle > end)
+	return false;
+    }
+    else {
+      --cycle;
+      DEBUG(std::cerr << "Decrease cycle: " << cycle << "\n");
+      if(cycle < end)
+	return false;
+    }
+  }
+
+  return success;
+}
+
+void ModuloSchedulingSBPass::reconstructLoop(std::vector<const MachineBasicBlock*> &SB) {
+
+  TIME_REGION(X, "reconstructLoop");
+
+
+  DEBUG(std::cerr << "Reconstructing Loop\n");
+
+  //First find the value *'s that we need to "save"
+  std::map<const Value*, std::pair<const MachineInstr*, int> > valuesToSave;
+
+  //Keep track of instructions we have already seen and their stage because
+  //we don't want to "save" values if they are used in the kernel immediately
+  std::map<const MachineInstr*, int> lastInstrs;
+
+
+  std::set<MachineBasicBlock*> seenBranchesBB;
+  const TargetInstrInfo *MTI = target.getInstrInfo();
+  std::map<MachineBasicBlock*, std::vector<std::pair<MachineInstr*, int> > > instrsMovedDown;
+  std::map<MachineBasicBlock*, int> branchStage;
+
+  //Loop over kernel and only look at instructions from a stage > 0
+  //Look at its operands and save values *'s that are read
+  for(MSScheduleSB::kernel_iterator I = schedule.kernel_begin(), E = schedule.kernel_end(); I != E; ++I) {
+    
+    if(I->second !=0) {
+      //For this instruction, get the Value*'s that it reads and put them into the set.
+      //Assert if there is an operand of another type that we need to save
+      const MachineInstr *inst = I->first;
+      lastInstrs[inst] = I->second;
+
+      for(unsigned i=0; i < inst->getNumOperands(); ++i) {
+	//get machine operand
+	const MachineOperand &mOp = inst->getOperand(i);
+	
+	if(mOp.getType() == MachineOperand::MO_VirtualRegister && mOp.isUse()) {
+	  //find the value in the map
+	  if (const Value* srcI = mOp.getVRegValue()) {
+
+	    if(isa<Constant>(srcI) || isa<Argument>(srcI))
+	      continue;
+
+	    //Before we declare this Value* one that we should save
+	    //make sure its def is not of the same stage as this instruction
+	    //because it will be consumed before its used
+	    Instruction *defInst = (Instruction*) srcI;
+	
+	    //Should we save this value?
+	    bool save = true;
+
+	    //Continue if not in the def map, loop invariant code does not need to be saved
+	    if(!defMap.count(srcI))
+	      continue;
+
+	    MachineInstr *defInstr = defMap[srcI];
+	
+
+	    if(lastInstrs.count(defInstr)) {
+	      if(lastInstrs[defInstr] == I->second) {
+		save = false;
+		
+	      }
+	    }
+	
+	    if(save)
+	      valuesToSave[srcI] = std::make_pair(I->first, i);
+	  }	
+	}
+	
+	if(mOp.getType() != MachineOperand::MO_VirtualRegister && mOp.isUse()) {
+	  assert("Our assumption is wrong. We have another type of register that needs to be saved\n");
+	}
+      }
+    }
+    
+    
+    //Do a check to see if instruction was moved below its original branch
+    if(MTI->isBranch(I->first->getOpcode())) {
+      seenBranchesBB.insert(I->first->getParent());
+      branchStage[I->first->getParent()] = I->second;
+    }
+    else {
+      instrsMovedDown[I->first->getParent()].push_back(std::make_pair(I->first, I->second));
+      //assert(seenBranchesBB.count(I->first->getParent()) && "Instruction moved below branch\n");
+    }
+
+  }
+
+  //The new loop will consist of one or more prologues, the kernel, and one or more epilogues.
+
+  //Map to keep track of old to new values
+  std::map<Value*, std::map<int, Value*> > newValues;
+
+  //Map to keep track of old to new values in kernel
+  std::map<Value*, std::map<int, Value*> > kernelPHIs;
+
+  //Another map to keep track of what machine basic blocks these new value*s are in since
+  //they have no llvm instruction equivalent
+  std::map<Value*, MachineBasicBlock*> newValLocation;
+
+  std::vector<std::vector<MachineBasicBlock*> > prologues;
+  std::vector<std::vector<BasicBlock*> > llvm_prologues;
+
+  //Map to keep track of where the inner branches go
+  std::map<const MachineBasicBlock*, Value*> sideExits;
+
+  
+  //Write prologue
+  if(schedule.getMaxStage() != 0)
+    writePrologues(prologues, SB, llvm_prologues, valuesToSave, newValues, newValLocation);
+
+  std::vector<BasicBlock*> llvmKernelBBs;
+  std::vector<MachineBasicBlock*> machineKernelBBs;
+  Function *parent = (Function*) SB[0]->getBasicBlock()->getParent();
+
+  for(unsigned i = 0; i < SB.size(); ++i) {
+    llvmKernelBBs.push_back(new BasicBlock("Kernel", parent));
+    
+    machineKernelBBs.push_back(new MachineBasicBlock(llvmKernelBBs[i]));
+    (((MachineBasicBlock*)SB[0])->getParent())->getBasicBlockList().push_back(machineKernelBBs[i]);
+  }
+
+  writeKernel(llvmKernelBBs, machineKernelBBs, valuesToSave, newValues, newValLocation, kernelPHIs);
+
+
+  std::vector<std::vector<MachineBasicBlock*> > epilogues;
+  std::vector<std::vector<BasicBlock*> > llvm_epilogues;
+
+  //Write epilogues
+  if(schedule.getMaxStage() != 0)
+    writeEpilogues(epilogues, SB, llvm_epilogues, valuesToSave, newValues, newValLocation, kernelPHIs);
+
+
+  //Fix our branches
+  fixBranches(prologues, llvm_prologues, machineKernelBBs, llvmKernelBBs, epilogues, llvm_epilogues, SB, sideExits);
+
+  //Print out epilogues and prologue
+  DEBUG(for(std::vector<std::vector<MachineBasicBlock*> >::iterator PI = prologues.begin(), PE = prologues.end();
+      PI != PE; ++PI) {
+	  std::cerr << "PROLOGUE\n";
+	  for(std::vector<MachineBasicBlock*>::iterator I = PI->begin(), E = PI->end(); I != E; ++I)
+	    (*I)->print(std::cerr);
+	});
+
+  DEBUG(std::cerr << "KERNEL\n");
+  DEBUG(for(std::vector<MachineBasicBlock*>::iterator I = machineKernelBBs.begin(), E = machineKernelBBs.end(); I != E; ++I) { (*I)->print(std::cerr);});
+
+  DEBUG(for(std::vector<std::vector<MachineBasicBlock*> >::iterator EI = epilogues.begin(), EE = epilogues.end();
+      EI != EE; ++EI) {
+    std::cerr << "EPILOGUE\n";
+    for(std::vector<MachineBasicBlock*>::iterator I = EI->begin(), E = EI->end(); I != E; ++I)
+      (*I)->print(std::cerr);
+  });
+
+
+  //Remove phis
+  removePHIs(SB, prologues, epilogues, machineKernelBBs, newValLocation);
+
+  //Print out epilogues and prologue
+  DEBUG(for(std::vector<std::vector<MachineBasicBlock*> >::iterator PI = prologues.begin(), PE = prologues.end();
+      PI != PE; ++PI) {
+	  std::cerr << "PROLOGUE\n";
+	  for(std::vector<MachineBasicBlock*>::iterator I = PI->begin(), E = PI->end(); I != E; ++I)
+	    (*I)->print(std::cerr);
+	});
+
+  DEBUG(std::cerr << "KERNEL\n");
+  DEBUG(for(std::vector<MachineBasicBlock*>::iterator I = machineKernelBBs.begin(), E = machineKernelBBs.end(); I != E; ++I) { (*I)->print(std::cerr);});
+
+  DEBUG(for(std::vector<std::vector<MachineBasicBlock*> >::iterator EI = epilogues.begin(), EE = epilogues.end();
+      EI != EE; ++EI) {
+    std::cerr << "EPILOGUE\n";
+    for(std::vector<MachineBasicBlock*>::iterator I = EI->begin(), E = EI->end(); I != E; ++I)
+      (*I)->print(std::cerr);
+  });
+
+  writeSideExits(prologues, llvm_prologues, epilogues, llvm_epilogues, sideExits, instrsMovedDown, SB, machineKernelBBs, branchStage);
+
+
+  DEBUG(std::cerr << "New Machine Function" << "\n");
+}
+
+
+void ModuloSchedulingSBPass::fixBranches(std::vector<std::vector<MachineBasicBlock*> > &prologues, std::vector<std::vector<BasicBlock*> > &llvm_prologues, std::vector<MachineBasicBlock*> &machineKernelBB, std::vector<BasicBlock*> &llvmKernelBB, std::vector<std::vector<MachineBasicBlock*> > &epilogues, std::vector<std::vector<BasicBlock*> > &llvm_epilogues, std::vector<const MachineBasicBlock*> &SB, std::map<const MachineBasicBlock*, Value*> &sideExits) {
+
+  const TargetInstrInfo *TMI = target.getInstrInfo();
+
+  //Get exit BB
+  BasicBlock *last = (BasicBlock*) SB[SB.size()-1]->getBasicBlock();
+  BasicBlock *kernel_exit = 0;
+  bool sawFirst = false;
+
+  for(succ_iterator I = succ_begin(last),
+	E = succ_end(last); I != E; ++I) {
+    if (*I != SB[0]->getBasicBlock()) {
+      kernel_exit = *I;
+      break;
+    }
+    else
+      sawFirst = true;
+  }
+  if(!kernel_exit && sawFirst) {
+    kernel_exit = (BasicBlock*) SB[0]->getBasicBlock();
+  }
+
+  assert(kernel_exit && "Kernel Exit can not be null");
+
+  if(schedule.getMaxStage() != 0) {
+    //Fix prologue branches
+    for(unsigned i = 0; i <  prologues.size(); ++i) {
+
+      for(unsigned j = 0; j < prologues[i].size(); ++j) {
+
+	MachineBasicBlock *currentMBB = prologues[i][j];
+       
+	//Find terminator since getFirstTerminator does not work!
+	for(MachineBasicBlock::reverse_iterator mInst = currentMBB->rbegin(), mInstEnd = currentMBB->rend(); mInst != mInstEnd; ++mInst) {
+	  MachineOpCode OC = mInst->getOpcode();
+	  //If its a branch update its branchto
+	  if(TMI->isBranch(OC)) {
+	    for(unsigned opNum = 0; opNum < mInst->getNumOperands(); ++opNum) {
+	      MachineOperand &mOp = mInst->getOperand(opNum);
+	      if (mOp.getType() == MachineOperand::MO_PCRelativeDisp) {
+		//Check if we are branching to the kernel, if not branch to epilogue
+		if(mOp.getVRegValue() == SB[0]->getBasicBlock()) {
+		  if(i >= prologues.size()-1)
+		    mOp.setValueReg(llvmKernelBB[0]);
+		  else
+		    mOp.setValueReg(llvm_prologues[i+1][0]);
+		}
+		else if( (mOp.getVRegValue() == kernel_exit) && (j == prologues[i].size()-1)) {
+		  mOp.setValueReg(llvm_epilogues[i][0]);
+		}
+		else if(mOp.getVRegValue() == SB[j+1]->getBasicBlock()) {
+		  mOp.setValueReg(llvm_prologues[i][j+1]);
+		}
+		
+	      }
+	    }
+	    
+	    DEBUG(std::cerr << "New Prologue Branch: " << *mInst << "\n");
+	  }
+	}
+
+	//Update llvm basic block with our new branch instr
+	DEBUG(std::cerr << SB[i]->getBasicBlock()->getTerminator() << "\n");
+	
+	const BranchInst *branchVal = dyn_cast<BranchInst>(SB[i]->getBasicBlock()->getTerminator());
+
+	//Check for inner branch
+	if(j < prologues[i].size()-1) {
+	  //Find our side exit LLVM basic block
+	  BasicBlock *sideExit = 0;
+	  for(unsigned s = 0; s < branchVal->getNumSuccessors(); ++s) {
+	    if(branchVal->getSuccessor(s) != SB[i+1]->getBasicBlock())
+	      sideExit = branchVal->getSuccessor(s);
+	  }
+	  assert(sideExit && "Must have side exit llvm basic block");
+	  TerminatorInst *newBranch = new BranchInst(sideExit,
+					llvm_prologues[i][j+1],
+					branchVal->getCondition(),
+					llvm_prologues[i][j]);
+	}
+	else {
+	  //If last prologue
+	  if(i == prologues.size()-1) {
+	    TerminatorInst *newBranch = new BranchInst(llvmKernelBB[0],
+						       llvm_epilogues[i][0],
+						       branchVal->getCondition(),
+						       llvm_prologues[i][j]);
+	  }
+	  else {
+	    TerminatorInst *newBranch = new BranchInst(llvm_prologues[i+1][0],
+						       llvm_epilogues[i][0],
+						       branchVal->getCondition(),
+						       llvm_prologues[i][j]);
+	  }
+	}
+      }
+    }
+  }
+
+  //Fix up kernel machine branches
+  for(unsigned i = 0; i < machineKernelBB.size(); ++i) {
+    MachineBasicBlock *currentMBB = machineKernelBB[i];
+
+    for(MachineBasicBlock::reverse_iterator mInst = currentMBB->rbegin(), mInstEnd = currentMBB->rend(); mInst != mInstEnd; ++mInst) {
+      MachineOpCode OC = mInst->getOpcode();
+      if(TMI->isBranch(OC)) {
+	for(unsigned opNum = 0; opNum < mInst->getNumOperands(); ++opNum) {
+	  MachineOperand &mOp = mInst->getOperand(opNum);
+	
+	  if(mOp.getType() == MachineOperand::MO_PCRelativeDisp) {
+	    //Deal with inner kernel branches
+	    if(i < machineKernelBB.size()-1) {
+	      if(mOp.getVRegValue() == SB[i+1]->getBasicBlock())
+		mOp.setValueReg(llvmKernelBB[i+1]);
+	      //Side exit!
+	      else {
+		sideExits[SB[i]] = mOp.getVRegValue();
+	      }
+	    }
+	    else {
+	      if(mOp.getVRegValue() == SB[0]->getBasicBlock())
+		mOp.setValueReg(llvmKernelBB[0]);
+	      else {
+		if(llvm_epilogues.size() > 0)
+		  mOp.setValueReg(llvm_epilogues[0][0]);
+	      }
+	    }
+	  }
+	}
+      }
+    }
+
+    //Update kernelLLVM branches
+    const BranchInst *branchVal = dyn_cast<BranchInst>(SB[0]->getBasicBlock()->getTerminator());
+  
+    //deal with inner branch
+    if(i < machineKernelBB.size()-1) {
+      
+      //Find our side exit LLVM basic block
+      BasicBlock *sideExit = 0;
+      for(unsigned s = 0; s < branchVal->getNumSuccessors(); ++s) {
+	if(branchVal->getSuccessor(s) != SB[i+1]->getBasicBlock())
+	  sideExit = branchVal->getSuccessor(s);
+      }
+      assert(sideExit && "Must have side exit llvm basic block");
+      TerminatorInst *newBranch = new BranchInst(sideExit,
+						 llvmKernelBB[i+1],
+						 branchVal->getCondition(),
+						 llvmKernelBB[i]);
+    }
+    else {
+      //Deal with outter branches
+      if(epilogues.size() > 0) {
+	TerminatorInst *newBranch = new BranchInst(llvmKernelBB[0],
+						   llvm_epilogues[0][0],
+						   branchVal->getCondition(),
+						   llvmKernelBB[i]);
+      }
+      else {
+	TerminatorInst *newBranch = new BranchInst(llvmKernelBB[0],
+						   kernel_exit,
+						   branchVal->getCondition(),
+						   llvmKernelBB[i]);
+      }
+    }
+  }
+
+  if(schedule.getMaxStage() != 0) {
+  
+    //Lastly add unconditional branches for the epilogues
+    for(unsigned i = 0; i <  epilogues.size(); ++i) {
+
+      for(unsigned j=0; j < epilogues[i].size(); ++j) {
+	//Now since we don't have fall throughs, add a unconditional
+	//branch to the next prologue
+	
+	//Before adding these, we need to check if the epilogue already has
+	//a branch in it
+	bool hasBranch = false;
+	/*if(j < epilogues[i].size()-1) {
+	  MachineBasicBlock *currentMBB = epilogues[i][j];
+	  for(MachineBasicBlock::reverse_iterator mInst = currentMBB->rbegin(), mInstEnd = currentMBB->rend(); mInst != mInstEnd; ++mInst) {
+	    
+	    MachineOpCode OC = mInst->getOpcode();
+	    
+	    //If its a branch update its branchto
+	    if(TMI->isBranch(OC)) {
+	      hasBranch = true;
+	      for(unsigned opNum = 0; opNum < mInst->getNumOperands(); ++opNum) {
+		MachineOperand &mOp = mInst->getOperand(opNum);
+		if (mOp.getType() == MachineOperand::MO_PCRelativeDisp) {
+		 
+		  if(mOp.getVRegValue() != sideExits[SB[j]]) {
+		    mOp.setValueReg(llvm_epilogues[i][j+1]);
+		  }
+		  
+		}
+	      }
+	      
+	      
+	      DEBUG(std::cerr << "New Epilogue Branch: " << *mInst << "\n");
+	    }
+	  }
+	  if(hasBranch) {
+	    const BranchInst *branchVal = dyn_cast<BranchInst>(SB[j]->getBasicBlock()->getTerminator());
+	    TerminatorInst *newBranch = new BranchInst((BasicBlock*)sideExits[SB[j]],
+						       llvm_epilogues[i][j+1],
+						       branchVal->getCondition(),
+						       llvm_epilogues[i][j]);
+	  }
+	  }*/
+
+	if(!hasBranch) {
+	
+	  //Handle inner branches
+	  if(j < epilogues[i].size()-1) {
+	    BuildMI(epilogues[i][j], V9::BA, 1).addPCDisp(llvm_epilogues[i][j+1]);
+	    TerminatorInst *newBranch = new BranchInst(llvm_epilogues[i][j+1],
+						       llvm_epilogues[i][j]);
+	  }
+	  else {
+	    
+	    //Check if this is the last epilogue
+	    if(i != epilogues.size()-1) {
+	      BuildMI(epilogues[i][j], V9::BA, 1).addPCDisp(llvm_epilogues[i+1][0]);
+	      //Add unconditional branch to end of epilogue
+	      TerminatorInst *newBranch = new BranchInst(llvm_epilogues[i+1][0],
+							 llvm_epilogues[i][j]);
+	      
+	    }
+	    else {
+	      BuildMI(epilogues[i][j], V9::BA, 1).addPCDisp(kernel_exit);
+	      TerminatorInst *newBranch = new BranchInst(kernel_exit, llvm_epilogues[i][j]);
+	    }
+	  }
+	  
+	  //Add one more nop!
+	  BuildMI(epilogues[i][j], V9::NOP, 0);
+	  
+	}
+      }
+    }
+  }
+
+  //Find all llvm basic blocks that branch to the loop entry and
+  //change to our first prologue.
+  const BasicBlock *llvmBB = SB[0]->getBasicBlock();
+  
+  std::vector<const BasicBlock*>Preds (pred_begin(llvmBB), pred_end(llvmBB));
+  
+  for(std::vector<const BasicBlock*>::iterator P = Preds.begin(), 
+	PE = Preds.end(); P != PE; ++P) {
+    if(*P == SB[SB.size()-1]->getBasicBlock())
+       continue;
+     else {
+       DEBUG(std::cerr << "Found our entry BB\n");
+       DEBUG((*P)->print(std::cerr));
+       //Get the Terminator instruction for this basic block and print it out
+       //DEBUG(std::cerr << *((*P)->getTerminator()) << "\n");
+       
+       //Update the terminator
+       TerminatorInst *term = ((BasicBlock*)*P)->getTerminator();
+       for(unsigned i=0; i < term->getNumSuccessors(); ++i) {
+	 if(term->getSuccessor(i) == llvmBB) {
+	   DEBUG(std::cerr << "Replacing successor bb\n");
+	   if(llvm_prologues.size() > 0) {
+	     term->setSuccessor(i, llvm_prologues[0][0]);
+
+	     DEBUG(std::cerr << "New Term" << *((*P)->getTerminator()) << "\n");
+
+	     //Also update its corresponding machine instruction
+	     MachineCodeForInstruction & tempMvec =
+	       MachineCodeForInstruction::get(term);
+	     for (unsigned j = 0; j < tempMvec.size(); j++) {
+	       MachineInstr *temp = tempMvec[j];
+	       MachineOpCode opc = temp->getOpcode();
+	       if(TMI->isBranch(opc)) {
+		 DEBUG(std::cerr << *temp << "\n");
+		 //Update branch
+		 for(unsigned opNum = 0; opNum < temp->getNumOperands(); ++opNum) {
+		   MachineOperand &mOp = temp->getOperand(opNum);
+		   if (mOp.getType() == MachineOperand::MO_PCRelativeDisp) {
+		     if(mOp.getVRegValue() == llvmBB)
+		       mOp.setValueReg(llvm_prologues[0][0]);
+		   }
+		 }
+	       }
+	     }
+	   }
+	   else {
+	     term->setSuccessor(i, llvmKernelBB[0]);
+
+	     //Also update its corresponding machine instruction
+	     MachineCodeForInstruction & tempMvec =
+	       MachineCodeForInstruction::get(term);
+	     for(unsigned j = 0; j < tempMvec.size(); j++) {
+	       MachineInstr *temp = tempMvec[j];
+	       MachineOpCode opc = temp->getOpcode();
+	       if(TMI->isBranch(opc)) {
+		 DEBUG(std::cerr << *temp << "\n");
+		 //Update branch
+		 for(unsigned opNum = 0; opNum < temp->getNumOperands(); ++opNum) {
+		   MachineOperand &mOp = temp->getOperand(opNum);
+		   if(mOp.getType() == MachineOperand::MO_PCRelativeDisp) {
+		     if(mOp.getVRegValue() == llvmBB)
+		       mOp.setValueReg(llvmKernelBB[0]);
+		   }
+		 }
+	       }
+	     }
+	   }
+	 }
+       }
+       break;
+     }
+  }
+
+}
+
+
+void ModuloSchedulingSBPass::writePrologues(std::vector<std::vector<MachineBasicBlock *> > &prologues, std::vector<const MachineBasicBlock*> &origSB, std::vector<std::vector<BasicBlock*> > &llvm_prologues, std::map<const Value*, std::pair<const MachineInstr*, int> > &valuesToSave, std::map<Value*, std::map<int, Value*> > &newValues, std::map<Value*, MachineBasicBlock*> &newValLocation) {
+
+  //Keep a map to easily know whats in the kernel
+  std::map<int, std::set<const MachineInstr*> > inKernel;
+  int maxStageCount = 0;
+
+  //Keep a map of new values we consumed in case they need to be added back
+  std::map<Value*, std::map<int, Value*> > consumedValues;
+
+  DEBUG(schedule.print(std::cerr));
+
+  for(MSScheduleSB::kernel_iterator I = schedule.kernel_begin(), E = schedule.kernel_end(); I != E; ++I) {
+    maxStageCount = std::max(maxStageCount, I->second);
+
+    //Put int the map so we know what instructions in each stage are in the kernel
+    DEBUG(std::cerr << "Inserting instruction " << *(I->first) << " into map at stage " << I->second << "\n");
+    inKernel[I->second].insert(I->first);
+  }
+
+  //Get target information to look at machine operands
+  const TargetInstrInfo *mii = target.getInstrInfo();
+
+ //Now write the prologues
+  for(int i = 0; i < maxStageCount; ++i) {
+    std::vector<MachineBasicBlock*> current_prologue;
+    std::vector<BasicBlock*> current_llvm_prologue;
+
+    for(std::vector<const MachineBasicBlock*>::iterator MB = origSB.begin(), 
+	  MBE = origSB.end(); MB != MBE; ++MB) {
+      const MachineBasicBlock *MBB = *MB;
+      //Create new llvm and machine bb
+      BasicBlock *llvmBB = new BasicBlock("PROLOGUE", (Function*) (MBB->getBasicBlock()->getParent()));
+      MachineBasicBlock *machineBB = new MachineBasicBlock(llvmBB);
+
+      DEBUG(std::cerr << "i=" << i << "\n");
+
+      for(int j = i; j >= 0; --j) {
+	//iterate over instructions in original bb
+	for(MachineBasicBlock::const_iterator MI = MBB->begin(), 
+	      ME = MBB->end(); ME != MI; ++MI) {
+	  if(inKernel[j].count(&*MI)) {
+	    MachineInstr *instClone = MI->clone();
+	    machineBB->push_back(instClone);
+	    
+	    //If its a branch, insert a nop
+	    if(mii->isBranch(instClone->getOpcode()))
+	      BuildMI(machineBB, V9::NOP, 0);
+	
+	    
+	    DEBUG(std::cerr << "Cloning: " << *MI << "\n");
+	    
+	    //After cloning, we may need to save the value that this instruction defines
+	    for(unsigned opNum=0; opNum < MI->getNumOperands(); ++opNum) {
+	      Instruction *tmp;
+	      
+	      //get machine operand
+	      MachineOperand &mOp = instClone->getOperand(opNum);
+	      if(mOp.getType() == MachineOperand::MO_VirtualRegister 
+		 && mOp.isDef()) {
+
+		//Check if this is a value we should save
+		if(valuesToSave.count(mOp.getVRegValue())) {
+		  //Save copy in tmpInstruction
+		  tmp = new TmpInstruction(mOp.getVRegValue());
+		  
+		  //Add TmpInstruction to safe LLVM Instruction MCFI
+		  MachineCodeForInstruction & tempMvec = MachineCodeForInstruction::get(defaultInst);
+		  tempMvec.addTemp((Value*) tmp);
+
+		  DEBUG(std::cerr << "Value: " << *(mOp.getVRegValue()) 
+			<< " New Value: " << *tmp << " Stage: " << i << "\n");
+		
+		newValues[mOp.getVRegValue()][i]= tmp;
+		newValLocation[tmp] = machineBB;
+
+		DEBUG(std::cerr << "Machine Instr Operands: " 
+		      << *(mOp.getVRegValue()) << ", 0, " << *tmp << "\n");
+		
+		//Create machine instruction and put int machineBB
+		MachineInstr *saveValue;
+		if(mOp.getVRegValue()->getType() == Type::FloatTy)
+		  saveValue = BuildMI(machineBB, V9::FMOVS, 3).addReg(mOp.getVRegValue()).addRegDef(tmp);
+		else if(mOp.getVRegValue()->getType() == Type::DoubleTy)
+		  saveValue = BuildMI(machineBB, V9::FMOVD, 3).addReg(mOp.getVRegValue()).addRegDef(tmp);
+		else
+		  saveValue = BuildMI(machineBB, V9::ORr, 3).addReg(mOp.getVRegValue()).addImm(0).addRegDef(tmp);
+	
+
+		DEBUG(std::cerr << "Created new machine instr: " << *saveValue << "\n");
+		}
+	      }
+
+	      //We may also need to update the value that we use if
+	      //its from an earlier prologue
+	      if(j != 0) {
+		if(mOp.getType() == MachineOperand::MO_VirtualRegister && mOp.isUse()) {
+		  if(newValues.count(mOp.getVRegValue())) {
+		    if(newValues[mOp.getVRegValue()].count(i-1)) {
+		      Value *oldV =  mOp.getVRegValue();
+		      DEBUG(std::cerr << "Replaced this value: " << mOp.getVRegValue() << " With:" << (newValues[mOp.getVRegValue()][i-1]) << "\n");
+		      //Update the operand with the right value
+		      mOp.setValueReg(newValues[mOp.getVRegValue()][i-1]);
+		      
+		      //Remove this value since we have consumed it
+		      //NOTE: Should this only be done if j != maxStage?
+		      consumedValues[oldV][i-1] = (newValues[oldV][i-1]);
+		      DEBUG(std::cerr << "Deleted value: " << consumedValues[oldV][i-1] << "\n");
+		      newValues[oldV].erase(i-1);
+		    }
+		  }
+		  else
+		    if(consumedValues.count(mOp.getVRegValue()))
+		      assert(!consumedValues[mOp.getVRegValue()].count(i-1) && "Found a case where we need the value");
+		}
+	      }
+	    }
+	  }
+	}
+      }
+      	(((MachineBasicBlock*)MBB)->getParent())->getBasicBlockList().push_back(machineBB);
+	current_prologue.push_back(machineBB);
+	current_llvm_prologue.push_back(llvmBB);
+    }
+    prologues.push_back(current_prologue);
+    llvm_prologues.push_back(current_llvm_prologue);
+
+  }
+}
+
+
+void ModuloSchedulingSBPass::writeEpilogues(std::vector<std::vector<MachineBasicBlock*> > &epilogues, std::vector<const MachineBasicBlock*> &origSB, std::vector<std::vector<BasicBlock*> > &llvm_epilogues, std::map<const Value*, std::pair<const MachineInstr*, int> > &valuesToSave, std::map<Value*, std::map<int, Value*> > &newValues,std::map<Value*, MachineBasicBlock*> &newValLocation, std::map<Value*, std::map<int, Value*> > &kernelPHIs ) {
+
+  std::map<int, std::set<const MachineInstr*> > inKernel;
+   const TargetInstrInfo *MTI = target.getInstrInfo();
+
+  for(MSScheduleSB::kernel_iterator I = schedule.kernel_begin(), E = schedule.kernel_end(); I != E; ++I) {
+
+    //Put int the map so we know what instructions in each stage are in the kernel
+    inKernel[I->second].insert(I->first);
+  }
+
+  std::map<Value*, Value*> valPHIs;
+
+  //some debug stuff, will remove later
+  DEBUG(for(std::map<Value*, std::map<int, Value*> >::iterator V = newValues.begin(), E = newValues.end(); V !=E; ++V) {
+    std::cerr << "Old Value: " << *(V->first) << "\n";
+    for(std::map<int, Value*>::iterator I = V->second.begin(), IE = V->second.end(); I != IE; ++I)
+      std::cerr << "Stage: " << I->first << " Value: " << *(I->second) << "\n";
+  });
+
+
+  //Now write the epilogues
+  for(int i = schedule.getMaxStage()-1; i >= 0; --i) {
+    std::vector<MachineBasicBlock*> current_epilogue;
+    std::vector<BasicBlock*> current_llvm_epilogue;
+    
+    for(std::vector<const MachineBasicBlock*>::iterator MB = origSB.begin(), MBE = origSB.end(); MB != MBE; ++MB) {
+      const MachineBasicBlock *MBB = *MB;
+
+      BasicBlock *llvmBB = new BasicBlock("EPILOGUE", (Function*) (MBB->getBasicBlock()->getParent()));
+      MachineBasicBlock *machineBB = new MachineBasicBlock(llvmBB);
+      
+      DEBUG(std::cerr << " Epilogue #: " << i << "\n");
+      
+      std::map<Value*, int> inEpilogue;
+      
+      for(MachineBasicBlock::const_iterator MI = MBB->begin(), ME = MBB->end(); ME != MI; ++MI) {
+	for(int j=schedule.getMaxStage(); j > i; --j) {
+	  if(inKernel[j].count(&*MI)) {
+	    DEBUG(std::cerr << "Cloning instruction " << *MI << "\n");
+	    MachineInstr *clone = MI->clone();
+	    
+	    //Update operands that need to use the result from the phi
+	    for(unsigned opNum=0; opNum < clone->getNumOperands(); ++opNum) {
+	      //get machine operand
+	      const MachineOperand &mOp = clone->getOperand(opNum);
+	      
+	      if((mOp.getType() == MachineOperand::MO_VirtualRegister && mOp.isUse())) {
+		
+		DEBUG(std::cerr << "Writing PHI for " << (mOp.getVRegValue()) << "\n");
+		
+		//If this is the last instructions for the max iterations ago, don't update operands
+		if(inEpilogue.count(mOp.getVRegValue()))
+		  if(inEpilogue[mOp.getVRegValue()] == i)
+		    continue;
+		
+		//Quickly write appropriate phis for this operand
+		if(newValues.count(mOp.getVRegValue())) {
+		  if(newValues[mOp.getVRegValue()].count(i)) {
+		    Instruction *tmp = new TmpInstruction(newValues[mOp.getVRegValue()][i]);
+		    
+		    //Get machine code for this instruction
+		    MachineCodeForInstruction & tempMvec = MachineCodeForInstruction::get(defaultInst);
+		    tempMvec.addTemp((Value*) tmp);
+		    
+		    //assert of no kernelPHI for this value
+		    assert(kernelPHIs[mOp.getVRegValue()][i] !=0 && "Must have final kernel phi to construct epilogue phi");
+		    
+		    MachineInstr *saveValue = BuildMI(machineBB, V9::PHI, 3).addReg(newValues[mOp.getVRegValue()][i]).addReg(kernelPHIs[mOp.getVRegValue()][i]).addRegDef(tmp);
+		    DEBUG(std::cerr << "Resulting PHI: " << *saveValue << "\n");
+		    valPHIs[mOp.getVRegValue()] = tmp;
+		  }
+		}
+		
+		if(valPHIs.count(mOp.getVRegValue())) {
+		  //Update the operand in the cloned instruction
+		  clone->getOperand(opNum).setValueReg(valPHIs[mOp.getVRegValue()]);
+		}
+	      }
+	      else if((mOp.getType() == MachineOperand::MO_VirtualRegister && mOp.isDef())) {
+		inEpilogue[mOp.getVRegValue()] = i;
+	      }
+	     
+	    }
+	    machineBB->push_back(clone);
+	    //if(MTI->isBranch(clone->getOpcode()))
+	    //BuildMI(machineBB, V9::NOP, 0);
+	  }
+	}
+      }
+      (((MachineBasicBlock*)MBB)->getParent())->getBasicBlockList().push_back(machineBB);
+      current_epilogue.push_back(machineBB);
+      current_llvm_epilogue.push_back(llvmBB);
+    }
+     
+    DEBUG(std::cerr << "EPILOGUE #" << i << "\n");
+    DEBUG(for(std::vector<MachineBasicBlock*>::iterator B = current_epilogue.begin(), BE = current_epilogue.end(); B != BE; ++B) {
+	    (*B)->print(std::cerr);});
+    
+    epilogues.push_back(current_epilogue);
+    llvm_epilogues.push_back(current_llvm_epilogue);
+  }
+}
+
+void ModuloSchedulingSBPass::writeKernel(std::vector<BasicBlock*> &llvmBB, std::vector<MachineBasicBlock*> &machineBB, std::map<const Value*, std::pair<const MachineInstr*, int> > &valuesToSave, std::map<Value*, std::map<int, Value*> > &newValues, std::map<Value*, MachineBasicBlock*> &newValLocation, std::map<Value*, std::map<int, Value*> > &kernelPHIs) {
+
+  //Keep track of operands that are read and saved from a previous iteration. The new clone
+  //instruction will use the result of the phi instead.
+  std::map<Value*, Value*> finalPHIValue;
+  std::map<Value*, Value*> kernelValue;
+
+  //Branches are a special case
+  std::vector<MachineInstr*> branches;
+
+  //Get target information to look at machine operands
+  const TargetInstrInfo *mii = target.getInstrInfo();
+  unsigned index = 0;
+  int numBr = 0;
+  bool seenBranch = false;
+
+  //Create TmpInstructions for the final phis
+  for(MSScheduleSB::kernel_iterator I = schedule.kernel_begin(), E = schedule.kernel_end(); I != E; ++I) {
+
+   DEBUG(std::cerr << "Stage: " << I->second << " Inst: " << *(I->first) << "\n";);
+
+   //Clone instruction
+   const MachineInstr *inst = I->first;
+   MachineInstr *instClone = inst->clone();
+
+   if(seenBranch && !mii->isBranch(instClone->getOpcode())) {
+     index++;
+     seenBranch = false;
+     numBr = 0;
+   }
+   else if(seenBranch && (numBr == 2)) {
+     index++;
+     numBr = 0;
+   }
+
+   //Insert into machine basic block
+   assert(index < machineBB.size() && "Must have a valid index into kernel MBBs");
+   machineBB[index]->push_back(instClone);
+
+   if(mii->isBranch(instClone->getOpcode())) {
+     BuildMI(machineBB[index], V9::NOP, 0);
+
+     seenBranch = true;
+     numBr++;
+   }
+   
+   DEBUG(std::cerr <<  "Cloned Inst: " << *instClone << "\n");
+
+   //Loop over Machine Operands
+   for(unsigned i=0; i < inst->getNumOperands(); ++i) {
+     //get machine operand
+     const MachineOperand &mOp = inst->getOperand(i);
+
+     if(I->second != 0) {
+       if(mOp.getType() == MachineOperand::MO_VirtualRegister && mOp.isUse()) {
+
+	 //Check to see where this operand is defined if this instruction is from max stage
+	 if(I->second == schedule.getMaxStage()) {
+	   DEBUG(std::cerr << "VREG: " << *(mOp.getVRegValue()) << "\n");
+	 }
+
+	 //If its in the value saved, we need to create a temp instruction and use that instead
+	 if(valuesToSave.count(mOp.getVRegValue())) {
+
+	   //Check if we already have a final PHI value for this
+	   if(!finalPHIValue.count(mOp.getVRegValue())) {
+	     //Only create phi if the operand def is from a stage before this one
+	     if(schedule.defPreviousStage(mOp.getVRegValue(), I->second)) {
+	     TmpInstruction *tmp = new TmpInstruction(mOp.getVRegValue());
+	
+	     //Get machine code for this instruction
+	     MachineCodeForInstruction & tempMvec = MachineCodeForInstruction::get(defaultInst);
+	     tempMvec.addTemp((Value*) tmp);
+	
+	     //Update the operand in the cloned instruction
+	     instClone->getOperand(i).setValueReg(tmp);
+	
+	     //save this as our final phi
+	     finalPHIValue[mOp.getVRegValue()] = tmp;
+	     newValLocation[tmp] = machineBB[index];
+	     }
+	   }
+	   else {
+	     //Use the previous final phi value
+	     instClone->getOperand(i).setValueReg(finalPHIValue[mOp.getVRegValue()]);
+	   }
+	 }
+       }
+     }
+     if(I->second != schedule.getMaxStage()) {
+       if(mOp.getType() == MachineOperand::MO_VirtualRegister && mOp.isDef()) {
+	 if(valuesToSave.count(mOp.getVRegValue())) {
+	
+	   TmpInstruction *tmp = new TmpInstruction(mOp.getVRegValue());
+	
+	   //Get machine code for this instruction
+	   MachineCodeForInstruction & tempVec = MachineCodeForInstruction::get(defaultInst);
+	   tempVec.addTemp((Value*) tmp);
+
+	   //Create new machine instr and put in MBB
+	   MachineInstr *saveValue;
+	   if(mOp.getVRegValue()->getType() == Type::FloatTy)
+	     saveValue = BuildMI(machineBB[index], V9::FMOVS, 3).addReg(mOp.getVRegValue()).addRegDef(tmp);
+	   else if(mOp.getVRegValue()->getType() == Type::DoubleTy)
+	     saveValue = BuildMI(machineBB[index], V9::FMOVD, 3).addReg(mOp.getVRegValue()).addRegDef(tmp);
+	   else
+	     saveValue = BuildMI(machineBB[index], V9::ORr, 3).addReg(mOp.getVRegValue()).addImm(0).addRegDef(tmp);
+	
+	
+	   //Save for future cleanup
+	   kernelValue[mOp.getVRegValue()] = tmp;
+	   newValLocation[tmp] = machineBB[index];
+	   kernelPHIs[mOp.getVRegValue()][schedule.getMaxStage()-1] = tmp;
+	 }
+       }
+     }
+   }
+
+ }
+
+  //Loop over each value we need to generate phis for
+ for(std::map<Value*, std::map<int, Value*> >::iterator V = newValues.begin(),
+       E = newValues.end(); V != E; ++V) {
+
+
+   DEBUG(std::cerr << "Writing phi for" << *(V->first));
+   DEBUG(std::cerr << "\nMap of Value* for this phi\n");
+   DEBUG(for(std::map<int, Value*>::iterator I = V->second.begin(),
+	       IE = V->second.end(); I != IE; ++I) {
+     std::cerr << "Stage: " << I->first;
+     std::cerr << " Value: " << *(I->second) << "\n";
+   });
+
+   //If we only have one current iteration live, its safe to set
+   //lastPhi = to kernel value
+   if(V->second.size() == 1) {
+     assert(kernelValue[V->first] != 0 && "Kernel value* must exist to create phi");
+     MachineInstr *saveValue = BuildMI(*machineBB[0], machineBB[0]->begin(),V9::PHI, 3).addReg(V->second.begin()->second).addReg(kernelValue[V->first]).addRegDef(finalPHIValue[V->first]);
+     DEBUG(std::cerr << "Resulting PHI (one live): " << *saveValue << "\n");
+     kernelPHIs[V->first][V->second.begin()->first] = kernelValue[V->first];
+     DEBUG(std::cerr << "Put kernel phi in at stage: " << schedule.getMaxStage()-1 << " (map stage = " << V->second.begin()->first << ")\n");
+   }
+   else {
+
+     //Keep track of last phi created.
+     Instruction *lastPhi = 0;
+
+     unsigned count = 1;
+     //Loop over the the map backwards to generate phis
+     for(std::map<int, Value*>::reverse_iterator I = V->second.rbegin(), IE = V->second.rend();
+	 I != IE; ++I) {
+
+       if(count < (V->second).size()) {
+	 if(lastPhi == 0) {
+	   lastPhi = new TmpInstruction(I->second);
+
+	   //Get machine code for this instruction
+	   MachineCodeForInstruction & tempMvec = MachineCodeForInstruction::get(defaultInst);
+	   tempMvec.addTemp((Value*) lastPhi);
+
+	   MachineInstr *saveValue = BuildMI(*machineBB[0], machineBB[0]->begin(), V9::PHI, 3).addReg(kernelValue[V->first]).addReg(I->second).addRegDef(lastPhi);
+	   DEBUG(std::cerr << "Resulting PHI: " << *saveValue << "\n");
+	   newValLocation[lastPhi] = machineBB[0];
+	 }
+	 else {
+	   Instruction *tmp = new TmpInstruction(I->second);
+
+	   //Get machine code for this instruction
+	   MachineCodeForInstruction & tempMvec = MachineCodeForInstruction::get(defaultInst);
+	   tempMvec.addTemp((Value*) tmp);
+	
+
+	   MachineInstr *saveValue = BuildMI(*machineBB[0], machineBB[0]->begin(), V9::PHI, 3).addReg(lastPhi).addReg(I->second).addRegDef(tmp);
+	   DEBUG(std::cerr << "Resulting PHI: " << *saveValue << "\n");
+	   lastPhi = tmp;
+	   kernelPHIs[V->first][I->first] = lastPhi;
+	   newValLocation[lastPhi] = machineBB[0];
+	 }
+       }
+       //Final phi value
+       else {
+	 //The resulting value must be the Value* we created earlier
+	 assert(lastPhi != 0 && "Last phi is NULL!\n");
+	 MachineInstr *saveValue = BuildMI(*machineBB[0], machineBB[0]->begin(), V9::PHI, 3).addReg(lastPhi).addReg(I->second).addRegDef(finalPHIValue[V->first]);
+	 DEBUG(std::cerr << "Resulting PHI: " << *saveValue << "\n");
+	 kernelPHIs[V->first][I->first] = finalPHIValue[V->first];
+       }
+
+       ++count;
+     }
+
+   }
+ }
+}
+
+
+void ModuloSchedulingSBPass::removePHIs(std::vector<const MachineBasicBlock*> &SB, std::vector<std::vector<MachineBasicBlock*> > &prologues, std::vector<std::vector<MachineBasicBlock*> > &epilogues, std::vector<MachineBasicBlock*> &kernelBB, std::map<Value*, MachineBasicBlock*> &newValLocation) {
+
+  //Worklist to delete things
+  std::vector<std::pair<MachineBasicBlock*, MachineBasicBlock::iterator> > worklist;
+
+  //Worklist of TmpInstructions that need to be added to a MCFI
+  std::vector<Instruction*> addToMCFI;
+
+  //Worklist to add OR instructions to end of kernel so not to invalidate the iterator
+  //std::vector<std::pair<Instruction*, Value*> > newORs;
+
+  const TargetInstrInfo *TMI = target.getInstrInfo();
+
+  //Start with the kernel and for each phi insert a copy for the phi
+  //def and for each arg
+  //phis are only in the first BB in the kernel
+  for(MachineBasicBlock::iterator I = kernelBB[0]->begin(), E = kernelBB[0]->end(); 
+      I != E; ++I) {
+
+    DEBUG(std::cerr << "Looking at Instr: " << *I << "\n");
+    
+    //Get op code and check if its a phi
+    if(I->getOpcode() == V9::PHI) {
+
+      DEBUG(std::cerr << "Replacing PHI: " << *I << "\n");
+      Instruction *tmp = 0;
+
+      for(unsigned i = 0; i < I->getNumOperands(); ++i) {
+	
+	//Get Operand
+	const MachineOperand &mOp = I->getOperand(i);
+	assert(mOp.getType() == MachineOperand::MO_VirtualRegister 
+	       && "Should be a Value*\n");
+	
+	if(!tmp) {
+	  tmp = new TmpInstruction(mOp.getVRegValue());
+	  addToMCFI.push_back(tmp);
+	}
+
+	//Now for all our arguments we read, OR to the new
+	//TmpInstruction that we created
+	if(mOp.isUse()) {
+	  DEBUG(std::cerr << "Use: " << mOp << "\n");
+	  //Place a copy at the end of its BB but before the branches
+	  assert(newValLocation.count(mOp.getVRegValue()) && "We must know where this value is located\n");
+	  //Reverse iterate to find the branches, we can safely assume no instructions have been
+	  //put in the nop positions
+	  for(MachineBasicBlock::iterator inst = --(newValLocation[mOp.getVRegValue()])->end(), endBB = (newValLocation[mOp.getVRegValue()])->begin(); inst != endBB; --inst) {
+	    MachineOpCode opc = inst->getOpcode();
+	    if(TMI->isBranch(opc) || TMI->isNop(opc))
+	      continue;
+	    else {
+	      if(mOp.getVRegValue()->getType() == Type::FloatTy)
+		BuildMI(*(newValLocation[mOp.getVRegValue()]), ++inst, V9::FMOVS, 3).addReg(mOp.getVRegValue()).addRegDef(tmp);
+	      else if(mOp.getVRegValue()->getType() == Type::DoubleTy)
+		BuildMI(*(newValLocation[mOp.getVRegValue()]), ++inst, V9::FMOVD, 3).addReg(mOp.getVRegValue()).addRegDef(tmp);
+	      else
+		BuildMI(*(newValLocation[mOp.getVRegValue()]), ++inst, V9::ORr, 3).addReg(mOp.getVRegValue()).addImm(0).addRegDef(tmp);
+	
+	      break;
+	    }
+	
+	  }
+
+	}
+	else {
+	  //Remove the phi and replace it with an OR
+	  DEBUG(std::cerr << "Def: " << mOp << "\n");
+	  //newORs.push_back(std::make_pair(tmp, mOp.getVRegValue()));
+	  if(tmp->getType() == Type::FloatTy)
+	    BuildMI(*kernelBB[0], I, V9::FMOVS, 3).addReg(tmp).addRegDef(mOp.getVRegValue());
+	  else if(tmp->getType() == Type::DoubleTy)
+	    BuildMI(*kernelBB[0], I, V9::FMOVD, 3).addReg(tmp).addRegDef(mOp.getVRegValue());
+	  else
+	    BuildMI(*kernelBB[0], I, V9::ORr, 3).addReg(tmp).addImm(0).addRegDef(mOp.getVRegValue());
+	
+	
+	  worklist.push_back(std::make_pair(kernelBB[0], I));
+	}
+	
+      }
+
+    }
+
+
+  }
+
+  //Add TmpInstructions to some MCFI
+  if(addToMCFI.size() > 0) {
+    MachineCodeForInstruction & tempMvec = MachineCodeForInstruction::get(defaultInst);
+    for(unsigned x = 0; x < addToMCFI.size(); ++x) {
+      tempMvec.addTemp(addToMCFI[x]);
+    }
+    addToMCFI.clear();
+  }
+
+
+  //Remove phis from epilogue
+  for(std::vector<std::vector<MachineBasicBlock*> >::iterator MB = epilogues.begin(), 
+	ME = epilogues.end(); MB != ME; ++MB) {
+    
+    for(std::vector<MachineBasicBlock*>::iterator currentMBB = MB->begin(), currentME = MB->end(); currentMBB != currentME; ++currentMBB) {
+      
+      for(MachineBasicBlock::iterator I = (*currentMBB)->begin(), 
+	    E = (*currentMBB)->end(); I != E; ++I) {
+
+	DEBUG(std::cerr << "Looking at Instr: " << *I << "\n");
+	//Get op code and check if its a phi
+	if(I->getOpcode() == V9::PHI) {
+	  Instruction *tmp = 0;
+
+	  for(unsigned i = 0; i < I->getNumOperands(); ++i) {
+	    //Get Operand
+	    const MachineOperand &mOp = I->getOperand(i);
+	    assert(mOp.getType() == MachineOperand::MO_VirtualRegister && "Should be a Value*\n");
+	
+	    if(!tmp) {
+	      tmp = new TmpInstruction(mOp.getVRegValue());
+	      addToMCFI.push_back(tmp);
+	    }
+	
+	    //Now for all our arguments we read, OR to the new TmpInstruction that we created
+	    if(mOp.isUse()) {
+	      DEBUG(std::cerr << "Use: " << mOp << "\n");
+	      //Place a copy at the end of its BB but before the branches
+	      assert(newValLocation.count(mOp.getVRegValue()) && "We must know where this value is located\n");
+	      //Reverse iterate to find the branches, we can safely assume no instructions have been
+	      //put in the nop positions
+	      for(MachineBasicBlock::iterator inst = --(newValLocation[mOp.getVRegValue()])->end(), endBB = (newValLocation[mOp.getVRegValue()])->begin(); inst != endBB; --inst) {
+		MachineOpCode opc = inst->getOpcode();
+		if(TMI->isBranch(opc) || TMI->isNop(opc))
+		  continue;
+		else {
+		  if(mOp.getVRegValue()->getType() == Type::FloatTy)
+		    BuildMI(*(newValLocation[mOp.getVRegValue()]), ++inst, V9::FMOVS, 3).addReg(mOp.getVRegValue()).addRegDef(tmp);
+		  else if(mOp.getVRegValue()->getType() == Type::DoubleTy)
+		    BuildMI(*(newValLocation[mOp.getVRegValue()]), ++inst, V9::FMOVD, 3).addReg(mOp.getVRegValue()).addRegDef(tmp);
+		  else
+		    BuildMI(*(newValLocation[mOp.getVRegValue()]), ++inst, V9::ORr, 3).addReg(mOp.getVRegValue()).addImm(0).addRegDef(tmp);
+		  
+		  
+		  break;
+		}
+		
+	      }
+	      
+	    }
+	    else {
+	      //Remove the phi and replace it with an OR
+	      DEBUG(std::cerr << "Def: " << mOp << "\n");
+	      if(tmp->getType() == Type::FloatTy)
+		BuildMI(**currentMBB, I, V9::FMOVS, 3).addReg(tmp).addRegDef(mOp.getVRegValue());
+	      else if(tmp->getType() == Type::DoubleTy)
+		BuildMI(**currentMBB, I, V9::FMOVD, 3).addReg(tmp).addRegDef(mOp.getVRegValue());
+	      else
+		BuildMI(**currentMBB, I, V9::ORr, 3).addReg(tmp).addImm(0).addRegDef(mOp.getVRegValue());
+	      
+	      worklist.push_back(std::make_pair(*currentMBB,I));
+	    }
+	  }
+	}
+      }
+    }
+  }
+
+
+  if(addToMCFI.size() > 0) {
+    MachineCodeForInstruction & tempMvec = MachineCodeForInstruction::get(defaultInst);
+    for(unsigned x = 0; x < addToMCFI.size(); ++x) {
+      tempMvec.addTemp(addToMCFI[x]);
+    }
+    addToMCFI.clear();
+  }
+  
+    //Delete the phis
+  for(std::vector<std::pair<MachineBasicBlock*, MachineBasicBlock::iterator> >::iterator I =  worklist.begin(), E = worklist.end(); I != E; ++I) {
+    DEBUG(std::cerr << "Deleting PHI " << *I->second << "\n");
+    I->first->erase(I->second);
+		
+  }
+
+
+  assert((addToMCFI.size() == 0) && "We should have added all TmpInstructions to some MachineCodeForInstruction");
+}
+
+
+
+
+void ModuloSchedulingSBPass::writeSideExits(std::vector<std::vector<MachineBasicBlock *> > &prologues, std::vector<std::vector<BasicBlock*> > &llvm_prologues, std::vector<std::vector<MachineBasicBlock *> > &epilogues, std::vector<std::vector<BasicBlock*> > &llvm_epilogues, std::map<const MachineBasicBlock*, Value*> &sideExits, std::map<MachineBasicBlock*, std::vector<std::pair<MachineInstr*, int> > > &instrsMovedDown, std::vector<const MachineBasicBlock*> &SB, std::vector<MachineBasicBlock*> &kernelMBBs, std::map<MachineBasicBlock*, int> branchStage) {
+
+  const TargetInstrInfo *TMI = target.getInstrInfo();
+
+  //Repeat for each side exit
+  for(unsigned sideExitNum = 0; sideExitNum < SB.size()-1; ++sideExitNum) {
+
+    std::vector<std::vector<BasicBlock*> > side_llvm_epilogues;
+    std::vector<std::vector<MachineBasicBlock*> > side_epilogues;
+    MachineBasicBlock* sideMBB;
+    BasicBlock* sideBB;
+
+    //Create side exit blocks
+    //Get the LLVM basic block
+    BasicBlock *bb = (BasicBlock*) SB[sideExitNum]->getBasicBlock();
+    MachineBasicBlock *mbb = (MachineBasicBlock*) SB[sideExitNum];
+    
+    int stage = branchStage[mbb];
+
+    //Create new basic blocks for our side exit instructios that were moved below the branch
+    sideBB = new BasicBlock("SideExit", (Function*) bb->getParent());
+    sideMBB = new MachineBasicBlock(sideBB);
+    (((MachineBasicBlock*)SB[0])->getParent())->getBasicBlockList().push_back(sideMBB);
+
+    
+    if(instrsMovedDown.count(mbb)) {
+      for(std::vector<std::pair<MachineInstr*, int> >::iterator I = instrsMovedDown[mbb].begin(), E = instrsMovedDown[mbb].end(); I != E; ++I) {
+	if(branchStage[mbb] == I->second)
+	  sideMBB->push_back((I->first)->clone());
+      }
+        
+      //Add unconditional branches to original exits
+      BuildMI(sideMBB, V9::BA, 1).addPCDisp(sideExits[mbb]);
+      BuildMI(sideMBB, V9::NOP, 0);
+      
+      //Add unconditioal branch to llvm BB
+      BasicBlock *extBB = dyn_cast<BasicBlock>(sideExits[mbb]);
+      assert(extBB && "Side exit basicblock can not be null");
+      TerminatorInst *newBranch = new BranchInst(extBB, sideBB);
+    }
+
+     //Clone epilogues and update their branches, one cloned epilogue set per side exit
+    //only clone epilogues that are from a greater stage!
+    for(unsigned i = 0; i < epilogues.size()-stage; ++i) {
+      std::vector<MachineBasicBlock*> MB = epilogues[i];
+      
+      std::vector<MachineBasicBlock*> newEp;
+      std::vector<BasicBlock*> newLLVMEp;
+    
+      for(std::vector<MachineBasicBlock*>::iterator currentMBB = MB.begin(), 
+	    lastMBB = MB.end(); currentMBB != lastMBB; ++currentMBB) {
+	BasicBlock *tmpBB = new BasicBlock("SideEpilogue", (Function*) (*currentMBB)->getBasicBlock()->getParent());
+	MachineBasicBlock *tmp = new MachineBasicBlock(tmpBB);
+      
+	//Clone instructions and insert into new MBB
+	for(MachineBasicBlock::iterator I = (*currentMBB)->begin(), 
+	      E = (*currentMBB)->end(); I != E; ++I) {
+	
+	  MachineInstr *clone = I->clone();
+	  if(clone->getOpcode() == V9::BA && (currentMBB+1 == lastMBB)) {
+	    //update branch to side exit
+	    for(unsigned i = 0; i < clone->getNumOperands(); ++i) {
+	      MachineOperand &mOp = clone->getOperand(i);
+	      if (mOp.getType() == MachineOperand::MO_PCRelativeDisp) {
+		mOp.setValueReg(sideBB);
+	      }
+	    }
+	  }
+	
+	  tmp->push_back(clone);
+	
+	}
+      
+	//Add llvm branch
+	TerminatorInst *newBranch = new BranchInst(sideBB, tmpBB);
+      
+	newEp.push_back(tmp);
+	(((MachineBasicBlock*)SB[0])->getParent())->getBasicBlockList().push_back(tmp);
+
+	newLLVMEp.push_back(tmpBB);
+      
+      }
+      side_llvm_epilogues.push_back(newLLVMEp);
+      side_epilogues.push_back(newEp);
+    }
+  
+  //Now stich up all the branches
+  
+  //Loop over prologues, and if its an inner branch and branches to our original side exit
+  //then have it branch to the appropriate epilogue first (if it exists)
+    for(unsigned P = 0; P < prologues.size(); ++P) {
+
+      //Get BB side exit we are dealing with
+      MachineBasicBlock *currentMBB = prologues[P][sideExitNum];
+      if(P >= (unsigned) stage) {
+	//Iterate backwards of machine instructions to find the branch we need to update
+	for(MachineBasicBlock::reverse_iterator mInst = currentMBB->rbegin(), mInstEnd = currentMBB->rend(); mInst != mInstEnd; ++mInst) {
+	  MachineOpCode OC = mInst->getOpcode();
+	  
+	  //If its a branch update its branchto
+	  if(TMI->isBranch(OC)) {
+	    for(unsigned opNum = 0; opNum < mInst->getNumOperands(); ++opNum) {
+	      MachineOperand &mOp = mInst->getOperand(opNum);
+	      if (mOp.getType() == MachineOperand::MO_PCRelativeDisp) {
+		//Check if we branch to side exit
+		if(mOp.getVRegValue() == sideExits[mbb]) {
+		  mOp.setValueReg(side_llvm_epilogues[P][0]);
+		}
+	      }
+	    }
+	    DEBUG(std::cerr << "New Prologue Branch: " << *mInst << "\n");
+	  }
+	}
+	
+	//Update llvm branch
+	TerminatorInst *branchVal = ((BasicBlock*) currentMBB->getBasicBlock())->getTerminator();
+	DEBUG(std::cerr << *branchVal << "\n");
+        
+	for(unsigned i=0; i < branchVal->getNumSuccessors(); ++i) {
+	  if(branchVal->getSuccessor(i) == sideExits[mbb]) {
+	    DEBUG(std::cerr << "Replacing successor bb\n");
+	    branchVal->setSuccessor(i, side_llvm_epilogues[P][0]);
+	  }
+	}
+      }
+      else {
+	//must add BA branch because another prologue or kernel has the actual side exit branch
+	 //Add unconditional branches to original exits
+	assert( (sideExitNum+1) < prologues[P].size() && "must have valid prologue to branch to");
+	BuildMI(prologues[P][sideExitNum], V9::BA, 1).addPCDisp((BasicBlock*)(prologues[P][sideExitNum+1])->getBasicBlock());
+	BuildMI(prologues[P][sideExitNum], V9::NOP, 0);
+
+	TerminatorInst *newBranch = new BranchInst((BasicBlock*) (prologues[P][sideExitNum+1])->getBasicBlock(), (BasicBlock*) (prologues[P][sideExitNum])->getBasicBlock());
+
+      }
+    }
+
+
+    //Update side exits in kernel
+    MachineBasicBlock *currentMBB = kernelMBBs[sideExitNum];
+    //Iterate backwards of machine instructions to find the branch we need to update
+    for(MachineBasicBlock::reverse_iterator mInst = currentMBB->rbegin(), mInstEnd = currentMBB->rend(); mInst != mInstEnd; ++mInst) {
+      MachineOpCode OC = mInst->getOpcode();
+      
+      //If its a branch update its branchto
+      if(TMI->isBranch(OC)) {
+	for(unsigned opNum = 0; opNum < mInst->getNumOperands(); ++opNum) {
+	  MachineOperand &mOp = mInst->getOperand(opNum);
+	  if (mOp.getType() == MachineOperand::MO_PCRelativeDisp) {
+	    //Check if we branch to side exit
+	    if(mOp.getVRegValue() == sideExits[mbb]) {
+	      if(side_llvm_epilogues.size() > 0)
+		mOp.setValueReg(side_llvm_epilogues[0][0]);
+	      else
+		mOp.setValueReg(sideBB);
+	    }
+	  }
+	}
+	DEBUG(std::cerr << "New Prologue Branch: " << *mInst << "\n");
+      }
+    }
+
+    //Update llvm branch
+    //Update llvm branch
+    TerminatorInst *branchVal = ((BasicBlock*)currentMBB->getBasicBlock())->getTerminator();
+    DEBUG(std::cerr << *branchVal << "\n");
+    
+    for(unsigned i=0; i < branchVal->getNumSuccessors(); ++i) {
+      if(branchVal->getSuccessor(i) == sideExits[mbb]) {
+	DEBUG(std::cerr << "Replacing successor bb\n");
+	if(side_llvm_epilogues.size() > 0)
+	  branchVal->setSuccessor(i, side_llvm_epilogues[0][0]);
+	else
+	  branchVal->setSuccessor(i, sideBB);
+      }
+    }
+  }
+}
+


Index: llvm/lib/Target/SparcV9/ModuloScheduling/ModuloSchedulingSuperBlock.h
diff -u llvm/lib/Target/SparcV9/ModuloScheduling/ModuloSchedulingSuperBlock.h:1.1 llvm/lib/Target/SparcV9/ModuloScheduling/ModuloSchedulingSuperBlock.h:1.2
--- llvm/lib/Target/SparcV9/ModuloScheduling/ModuloSchedulingSuperBlock.h:1.1	Sat Apr 30 20:27:47 2005
+++ llvm/lib/Target/SparcV9/ModuloScheduling/ModuloSchedulingSuperBlock.h	Thu Jun 16 23:00:57 2005
@@ -15,22 +15,24 @@
 #define LLVM_MODULOSCHEDULINGSB_H
 
 #include "llvm/Analysis/LoopInfo.h"
+#include "llvm/Analysis/ScalarEvolution.h"
 #include "llvm/Function.h"
 #include "llvm/Pass.h"
 #include "llvm/CodeGen/MachineBasicBlock.h"
-#include "MSSchedule.h"
-#include "MSchedGraph.h"
+#include "MSScheduleSB.h"
+#include "MSchedGraphSB.h"
+
 
 namespace llvm {
 
   //Struct to contain ModuloScheduling Specific Information for each node
-  struct MSNodeAttributes {
+  struct MSNodeSBAttributes {
     int ASAP; //Earliest time at which the opreation can be scheduled
     int ALAP; //Latest time at which the operation can be scheduled.
     int MOB;
     int depth;
     int height;
-    MSNodeAttributes(int asap=-1, int alap=-1, int mob=-1,
+    MSNodeSBAttributes(int asap=-1, int alap=-1, int mob=-1,
 			     int d=-1, int h=-1) : ASAP(asap), ALAP(alap),
 						   MOB(mob), depth(d),
 						   height(h) {}
@@ -55,22 +57,22 @@
     Instruction *defaultInst;
 
     //Map that holds node to node attribute information
-    std::map<MSchedGraphNode*, MSNodeAttributes> nodeToAttributesMap;
+    std::map<MSchedGraphSBNode*, MSNodeSBAttributes> nodeToAttributesMap;
 
     //Map to hold all reccurrences
-    std::set<std::pair<int, std::vector<MSchedGraphNode*> > > recurrenceList;
+    std::set<std::pair<int, std::vector<MSchedGraphSBNode*> > > recurrenceList;
 
     //Set of edges to ignore, stored as src node and index into vector of successors
-    std::set<std::pair<MSchedGraphNode*, unsigned> > edgesToIgnore;
+    std::set<std::pair<MSchedGraphSBNode*, unsigned> > edgesToIgnore;
 
     //Vector containing the partial order
-    std::vector<std::set<MSchedGraphNode*> > partialOrder;
+    std::vector<std::set<MSchedGraphSBNode*> > partialOrder;
 
     //Vector containing the final node order
-    std::vector<MSchedGraphNode*> FinalNodeOrder;
+    std::vector<MSchedGraphSBNode*> FinalNodeOrder;
 
     //Schedule table, key is the cycle number and the vector is resource, node pairs
-    MSSchedule schedule;
+    MSScheduleSB schedule;
 
     //Current initiation interval
     int II;
@@ -78,10 +80,99 @@
     //Internal Functions
     void FindSuperBlocks(Function &F, LoopInfo &LI, 
 			 std::vector<std::vector<const MachineBasicBlock*> > &Worklist);
-    bool MachineBBisValid(const MachineBasicBlock *B);
+    bool MachineBBisValid(const MachineBasicBlock *B,
+			  std::map<const MachineInstr*, unsigned> &indexMap, 
+			  unsigned &offset);
     bool CreateDefMap(std::vector<const MachineBasicBlock*> &SB);
+    bool getIndVar(std::vector<const MachineBasicBlock*> &superBlock, 
+		   std::map<BasicBlock*, MachineBasicBlock*> &bbMap,
+		   std::map<const MachineInstr*, unsigned> &indexMap);
+    bool assocIndVar(Instruction *I, std::set<Instruction*> &indVar,
+		     std::vector<Instruction*> &stack, 
+		     std::map<BasicBlock*, MachineBasicBlock*> &bbMap, 
+		     const BasicBlock *first,
+		     std::set<const BasicBlock*> &llvmSuperBlock);
+    int calculateResMII(std::vector<const MachineBasicBlock*> &superBlock);
+    int calculateRecMII(MSchedGraphSB *graph, int MII);
+    void findAllCircuits(MSchedGraphSB *g, int II);
+    void addRecc(std::vector<MSchedGraphSBNode*> &stack, 
+		 std::map<MSchedGraphSBNode*, MSchedGraphSBNode*> &newNodes);
+    bool circuit(MSchedGraphSBNode *v, std::vector<MSchedGraphSBNode*> &stack,
+		 std::set<MSchedGraphSBNode*> &blocked, std::vector<MSchedGraphSBNode*> &SCC,
+		 MSchedGraphSBNode *s, std::map<MSchedGraphSBNode*, 
+		 std::set<MSchedGraphSBNode*> > &B,
+		 int II, std::map<MSchedGraphSBNode*, MSchedGraphSBNode*> &newNodes);
+    void unblock(MSchedGraphSBNode *u, std::set<MSchedGraphSBNode*> &blocked,
+		 std::map<MSchedGraphSBNode*, std::set<MSchedGraphSBNode*> > &B);
+    void addSCC(std::vector<MSchedGraphSBNode*> &SCC, std::map<MSchedGraphSBNode*, MSchedGraphSBNode*> &newNodes);
+    void calculateNodeAttributes(MSchedGraphSB *graph, int MII);
+    bool ignoreEdge(MSchedGraphSBNode *srcNode, MSchedGraphSBNode *destNode);
+    int  calculateASAP(MSchedGraphSBNode *node, int MII, MSchedGraphSBNode *destNode);
+    int calculateALAP(MSchedGraphSBNode *node, int MII,
+		      int maxASAP, MSchedGraphSBNode *srcNode);
+    int findMaxASAP();
+    int calculateHeight(MSchedGraphSBNode *node,MSchedGraphSBNode *srcNode);
+    int calculateDepth(MSchedGraphSBNode *node, MSchedGraphSBNode *destNode);
+    void computePartialOrder();
+    void connectedComponentSet(MSchedGraphSBNode *node, std::set<MSchedGraphSBNode*> &ccSet, 
+			       std::set<MSchedGraphSBNode*> &lastNodes);
+    void searchPath(MSchedGraphSBNode *node,
+		    std::vector<MSchedGraphSBNode*> &path,
+		    std::set<MSchedGraphSBNode*> &nodesToAdd,
+		    std::set<MSchedGraphSBNode*> &new_reccurrence);
+    void orderNodes();
+    bool computeSchedule(std::vector<const MachineBasicBlock*> &BB, MSchedGraphSB *MSG);
+    bool scheduleNode(MSchedGraphSBNode *node, int start, int end);
+      void predIntersect(std::set<MSchedGraphSBNode*> &CurrentSet, std::set<MSchedGraphSBNode*> &IntersectResult);
+    void succIntersect(std::set<MSchedGraphSBNode*> &CurrentSet, std::set<MSchedGraphSBNode*> &IntersectResult);
+    void reconstructLoop(std::vector<const MachineBasicBlock*> &SB);
+    void fixBranches(std::vector<std::vector<MachineBasicBlock*> > &prologues, 
+		     std::vector<std::vector<BasicBlock*> > &llvm_prologues, 
+		     std::vector<MachineBasicBlock*> &machineKernelBB, 
+		     std::vector<BasicBlock*> &llvmKernelBB, 
+		     std::vector<std::vector<MachineBasicBlock*> > &epilogues, 
+		     std::vector<std::vector<BasicBlock*> > &llvm_epilogues, 
+		     std::vector<const MachineBasicBlock*> &SB,
+		     std::map<const MachineBasicBlock*, Value*> &sideExits);
+
+    void writePrologues(std::vector<std::vector<MachineBasicBlock *> > &prologues, 
+			std::vector<const MachineBasicBlock*> &origBB, 
+			std::vector<std::vector<BasicBlock*> > &llvm_prologues, 
+			std::map<const Value*, std::pair<const MachineInstr*, int> > &valuesToSave, 
+			std::map<Value*, std::map<int, Value*> > &newValues, 
+			std::map<Value*, MachineBasicBlock*> &newValLocation);
+
+    void writeKernel(std::vector<BasicBlock*> &llvmBB, std::vector<MachineBasicBlock*> &machineBB, 
+		     std::map<const Value*, std::pair<const MachineInstr*, int> > &valuesToSave, 
+		     std::map<Value*, std::map<int, Value*> > &newValues, 
+		     std::map<Value*, MachineBasicBlock*> &newValLocation, 
+		     std::map<Value*, std::map<int, Value*> > &kernelPHIs);
+
+    void removePHIs(std::vector<const MachineBasicBlock*> &SB, 
+		    std::vector<std::vector<MachineBasicBlock*> > &prologues, 
+		    std::vector<std::vector<MachineBasicBlock*> > &epilogues, 
+		    std::vector<MachineBasicBlock*> &kernelBB, 
+		    std::map<Value*, MachineBasicBlock*> &newValLocation);
+    
+    void writeEpilogues(std::vector<std::vector<MachineBasicBlock*> > &epilogues, 
+			std::vector<const MachineBasicBlock*> &origSB, 
+			std::vector<std::vector<BasicBlock*> > &llvm_epilogues, 
+			std::map<const Value*, std::pair<const MachineInstr*, int> > &valuesToSave,
+			std::map<Value*, std::map<int, Value*> > &newValues,
+			std::map<Value*, MachineBasicBlock*> &newValLocation, 
+			std::map<Value*, std::map<int, Value*> > &kernelPHIs);
+    
+    void writeSideExits(std::vector<std::vector<MachineBasicBlock *> > &prologues, 
+			std::vector<std::vector<BasicBlock*> > &llvm_prologues, 
+			std::vector<std::vector<MachineBasicBlock *> > &epilogues, 
+			std::vector<std::vector<BasicBlock*> > &llvm_epilogues, 
+			std::map<const MachineBasicBlock*, Value*> &sideExits, 
+			std::map<MachineBasicBlock*, std::vector<std::pair<MachineInstr*, int> > > &instrsMovedDown,
+			std::vector<const MachineBasicBlock*> &SB, 
+			std::vector<MachineBasicBlock*> &kernelMBBs,
+			  std::map<MachineBasicBlock*, int> branchStage);
 
-  public:
+ public:
     ModuloSchedulingSBPass(TargetMachine &targ) : target(targ) {}
       virtual bool runOnFunction(Function &F);
       virtual const char* getPassName() const { return "ModuloScheduling-SuperBlock"; }
@@ -89,7 +180,11 @@
       
       // getAnalysisUsage
       virtual void getAnalysisUsage(AnalysisUsage &AU) const {
+	/// HACK: We don't actually need scev, but we have
+	/// to say we do so that the pass manager does not delete it
+	/// before we run.
 	AU.addRequired<LoopInfo>();
+	AU.addRequired<ScalarEvolution>();
 	AU.addRequired<DependenceAnalyzer>();
       }
   };





From tbrethou at cs.uiuc.edu  Thu Jun 16 23:01:45 2005
From: tbrethou at cs.uiuc.edu (Tanya Brethour)
Date: Thu, 16 Jun 2005 23:01:45 -0500
Subject: [llvm-commits] 
	CVS: llvm/lib/Target/SparcV9/RegAlloc/PhyRegAlloc.cpp
Message-ID: <200506170401.XAA16658@zion.cs.uiuc.edu>



Changes in directory llvm/lib/Target/SparcV9/RegAlloc:

PhyRegAlloc.cpp updated: 1.168 -> 1.169
---
Log message:

Added statistic to count number of spills.


---
Diffs of the changes:  (+3 -0)

 PhyRegAlloc.cpp |    3 +++
 1 files changed, 3 insertions(+)


Index: llvm/lib/Target/SparcV9/RegAlloc/PhyRegAlloc.cpp
diff -u llvm/lib/Target/SparcV9/RegAlloc/PhyRegAlloc.cpp:1.168 llvm/lib/Target/SparcV9/RegAlloc/PhyRegAlloc.cpp:1.169
--- llvm/lib/Target/SparcV9/RegAlloc/PhyRegAlloc.cpp:1.168	Sun Jun 12 18:52:58 2005
+++ llvm/lib/Target/SparcV9/RegAlloc/PhyRegAlloc.cpp	Thu Jun 16 23:01:34 2005
@@ -46,10 +46,12 @@
 #include "llvm/Support/CommandLine.h"
 #include "llvm/ADT/SetOperations.h"
 #include "llvm/ADT/STLExtras.h"
+#include "llvm/ADT/Statistic.h"
 #include <cmath>
 #include <iostream>
 
 namespace llvm {
+ Statistic<> RASpills("regalloc-spills", "Number of registers spilled");
 
 RegAllocDebugLevel_t DEBUG_RA;
 
@@ -703,6 +705,7 @@
   // Finally, insert the entire spill code sequences before/after MInst
   AI.InstrnsBefore.insert(AI.InstrnsBefore.end(), MIBef.begin(), MIBef.end());
   AI.InstrnsAfter.insert(AI.InstrnsAfter.begin(), MIAft.begin(), MIAft.end());
+  ++RASpills;
 
   if (DEBUG_RA) {
     std::cerr << "\nFor Inst:\n  " << *MInst;





From tbrethou at cs.uiuc.edu  Thu Jun 16 23:15:54 2005
From: tbrethou at cs.uiuc.edu (Tanya Brethour)
Date: Thu, 16 Jun 2005 23:15:54 -0500
Subject: [llvm-commits] 
	CVS: llvm/lib/Target/SparcV9/ModuloScheduling/MSScheduleSB.cpp
	MSScheduleSB.h MSchedGraphSB.cpp 
Message-ID: <200506170415.XAA29856@zion.cs.uiuc.edu>



Changes in directory llvm/lib/Target/SparcV9/ModuloScheduling:

MSScheduleSB.cpp added (r1.1)
MSScheduleSB.h added (r1.1)
MSchedGraphSB.cpp added (r1.1)
---
Log message:

Special versions of the dep graph and scheduled for SMS for superblocks.


---
Diffs of the changes:  (+1265 -0)

 MSScheduleSB.cpp  |  324 ++++++++++++++++++++
 MSScheduleSB.h    |   73 ++++
 MSchedGraphSB.cpp |  868 ++++++++++++++++++++++++++++++++++++++++++++++++++++++
 3 files changed, 1265 insertions(+)


Index: llvm/lib/Target/SparcV9/ModuloScheduling/MSScheduleSB.cpp
diff -c /dev/null llvm/lib/Target/SparcV9/ModuloScheduling/MSScheduleSB.cpp:1.1
*** /dev/null	Thu Jun 16 23:15:53 2005
--- llvm/lib/Target/SparcV9/ModuloScheduling/MSScheduleSB.cpp	Thu Jun 16 23:15:43 2005
***************
*** 0 ****
--- 1,324 ----
+ //===-- MSScheduleSB.cpp Schedule ---------------------------------*- C++ -*-===//
+ //
+ //                     The LLVM Compiler Infrastructure
+ //
+ // This file was developed by the LLVM research group and is distributed under
+ // the University of Illinois Open Source License. See LICENSE.TXT for details.
+ //
+ //===----------------------------------------------------------------------===//
+ //
+ //
+ //
+ //===----------------------------------------------------------------------===//
+ #define DEBUG_TYPE "ModuloSchedSB"
+ 
+ #include "MSScheduleSB.h"
+ #include "llvm/Support/Debug.h"
+ #include "llvm/Target/TargetSchedInfo.h"
+ #include "../SparcV9Internals.h"
+ #include "llvm/CodeGen/MachineInstr.h"
+ 
+ using namespace llvm;
+ 
+ //Check if all resources are free
+ bool resourcesFree(MSchedGraphSBNode*, int, 
+ std::map<int, std::map<int, int> > &resourceNumPerCycle);
+ 
+ //Returns a boolean indicating if the start cycle needs to be increased/decreased
+ bool MSScheduleSB::insert(MSchedGraphSBNode *node, int cycle, int II) {
+ 
+   //First, check if the cycle has a spot free to start
+   if(schedule.find(cycle) != schedule.end()) {
+     //Check if we have a free issue slot at this cycle
+     if (schedule[cycle].size() < numIssue) {
+       //Now check if all the resources in their respective cycles are available
+       if(resourcesFree(node, cycle, II)) {
+ 	//Insert to preserve dependencies
+ 	addToSchedule(cycle,node);
+ 	DEBUG(std::cerr << "Found spot in map, and there is an issue slot\n");
+ 	return false;
+       }
+     }
+   }
+   //Not in the map yet so put it in
+   else {
+     if(resourcesFree(node,cycle,II)) {
+       std::vector<MSchedGraphSBNode*> nodes;
+       nodes.push_back(node);
+       schedule[cycle] = nodes;
+       DEBUG(std::cerr << "Nothing in map yet so taking an issue slot\n");
+       return false;
+     }
+   }
+ 
+   DEBUG(std::cerr << "All issue slots taken\n");
+   return true;
+ 
+ }
+ 
+ void MSScheduleSB::addToSchedule(int cycle, MSchedGraphSBNode *node) {
+   std::vector<MSchedGraphSBNode*> nodesAtCycle = schedule[cycle];
+ 
+   std::map<unsigned, MSchedGraphSBNode*> indexMap;
+   for(unsigned i=0; i < nodesAtCycle.size(); ++i) {
+     indexMap[nodesAtCycle[i]->getIndex()] = nodesAtCycle[i];
+   }
+ 
+   indexMap[node->getIndex()] = node;
+ 
+   std::vector<MSchedGraphSBNode*> nodes;
+   for(std::map<unsigned, MSchedGraphSBNode*>::iterator I = indexMap.begin(), E = indexMap.end(); I != E; ++I)
+     nodes.push_back(I->second);
+ 
+   schedule[cycle] =  nodes;
+ }
+ 
+ bool MSScheduleSB::resourceAvailable(int resourceNum, int cycle) {
+   bool isFree = true;
+ 
+   //Get Map for this cycle
+   if(resourceNumPerCycle.count(cycle)) {
+     if(resourceNumPerCycle[cycle].count(resourceNum)) {
+       int maxRes = CPUResource::getCPUResource(resourceNum)->maxNumUsers;
+       if(resourceNumPerCycle[cycle][resourceNum] >= maxRes)
+ 	isFree = false;
+     }
+   }
+   
+   return isFree;
+ }
+ 
+ void MSScheduleSB::useResource(int resourceNum, int cycle) {
+   
+   //Get Map for this cycle
+   if(resourceNumPerCycle.count(cycle)) {
+     if(resourceNumPerCycle[cycle].count(resourceNum)) {
+       resourceNumPerCycle[cycle][resourceNum]++;
+     }
+     else {
+       resourceNumPerCycle[cycle][resourceNum] = 1;
+     }
+   }
+   //If no map, create one!
+   else {
+     std::map<int, int> resourceUse;
+     resourceUse[resourceNum] = 1;
+     resourceNumPerCycle[cycle] = resourceUse;
+   }
+   
+ }
+ 
+ bool MSScheduleSB::resourcesFree(MSchedGraphSBNode *node, int cycle, int II) {
+ 
+   //Get Resource usage for this instruction
+   const TargetSchedInfo *msi = node->getParent()->getTarget()->getSchedInfo();
+   int currentCycle = cycle;
+   bool success = true;
+ 
+   //Create vector of starting cycles
+   std::vector<int> cyclesMayConflict;
+   cyclesMayConflict.push_back(cycle);
+ 
+   if(resourceNumPerCycle.size() > 0) {
+     for(int i = cycle-II; i >= (resourceNumPerCycle.begin()->first); i-=II)
+       cyclesMayConflict.push_back(i);
+     for(int i = cycle+II; i <= resourceNumPerCycle.end()->first; i+=II)
+       cyclesMayConflict.push_back(i);
+   }
+ 
+   //Now check all cycles for conflicts
+   for(int index = 0; index < (int) cyclesMayConflict.size(); ++index) {
+     currentCycle = cyclesMayConflict[index];
+     
+     //Get resource usage for this instruction
+     InstrRUsage rUsage = msi->getInstrRUsage(node->getInst()->getOpcode());
+     std::vector<std::vector<resourceId_t> > resources = rUsage.resourcesByCycle;
+     
+     //Loop over resources in each cycle and increments their usage count
+     for(unsigned i=0; i < resources.size(); ++i) {
+       for(unsigned j=0; j < resources[i].size(); ++j) {
+ 	
+ 	//Get Resource to check its availability
+ 	int resourceNum = resources[i][j];
+ 	
+ 	DEBUG(std::cerr << "Attempting to schedule Resource Num: " << resourceNum << " in cycle: " << currentCycle << "\n");
+ 	
+ 	success = resourceAvailable(resourceNum, currentCycle); 
+ 	
+ 	if(!success)
+ 	  break;
+ 	
+       }
+       
+       if(!success)
+ 	break;
+       
+       //Increase cycle
+       currentCycle++;
+     }
+     
+     if(!success)
+       return false;
+   }
+ 
+   //Actually put resources into the map
+   if(success) {
+ 
+     int currentCycle = cycle;
+     //Get resource usage for this instruction
+     InstrRUsage rUsage = msi->getInstrRUsage(node->getInst()->getOpcode());
+     std::vector<std::vector<resourceId_t> > resources = rUsage.resourcesByCycle;
+     
+     //Loop over resources in each cycle and increments their usage count
+     for(unsigned i=0; i < resources.size(); ++i) {
+       for(unsigned j=0; j < resources[i].size(); ++j) {
+ 	int resourceNum = resources[i][j];
+ 	useResource(resourceNum, currentCycle);
+       }
+       currentCycle++;
+     }
+   }
+ 
+ 
+   return true;
+ 
+ }
+ 
+ bool MSScheduleSB::constructKernel(int II, std::vector<MSchedGraphSBNode*> &branches, std::map<const MachineInstr*, unsigned> &indVar) {
+ 
+   //Our schedule is allowed to have negative numbers, so lets calculate this offset
+   int offset = schedule.begin()->first;
+   if(offset > 0)
+     offset = 0;
+ 
+   DEBUG(std::cerr << "Offset: " << offset << "\n");
+ 
+   //Using the schedule, fold up into kernel and check resource conflicts as we go
+   std::vector<std::pair<MSchedGraphSBNode*, int> > tempKernel;
+   
+   int stageNum = ((schedule.rbegin()->first-offset)+1)/ II;
+   int maxSN = 0;
+ 
+   DEBUG(std::cerr << "Number of Stages: " << stageNum << "\n");
+ 
+   for(int index = offset; index < (II+offset); ++index) {
+     int count = 0;
+     for(int i = index; i <= (schedule.rbegin()->first); i+=II) {
+       if(schedule.count(i)) {
+ 	for(std::vector<MSchedGraphSBNode*>::iterator I = schedule[i].begin(),
+ 	      E = schedule[i].end(); I != E; ++I) {
+ 	  //Check if its a branch
+ 	  assert(!(*I)->isBranch() && "Branch should not be schedule!");
+ 
+ 	  tempKernel.push_back(std::make_pair(*I, count));
+ 	  maxSN = std::max(maxSN, count);
+ 	  
+ 	}
+       }
+       ++count;
+     }
+   }
+ 
+ 
+   //Add in induction var code
+   for(std::vector<std::pair<MSchedGraphSBNode*, int> >::iterator I = tempKernel.begin(), IE = tempKernel.end();
+       I != IE; ++I) {
+     //Add indVar instructions before this one for the current iteration
+     if(I->second == 0) {
+       std::map<unsigned, MachineInstr*> tmpMap;
+ 
+       //Loop over induction variable instructions in the map that come before this instr
+       for(std::map<const MachineInstr*, unsigned>::iterator N = indVar.begin(), NE = indVar.end(); N != NE; ++N) {
+ 
+ 
+ 	if(N->second < I->first->getIndex())
+ 	  tmpMap[N->second] = (MachineInstr*) N->first;
+       }
+ 
+       //Add to kernel, and delete from indVar
+       for(std::map<unsigned, MachineInstr*>::iterator N = tmpMap.begin(), NE = tmpMap.end(); N != NE; ++N) {
+ 	kernel.push_back(std::make_pair(N->second, 0));
+ 	indVar.erase(N->second);
+       }
+     }
+ 
+     kernel.push_back(std::make_pair((MachineInstr*) I->first->getInst(), I->second));
+     if(I->first->isPredicate()) {
+       //assert(I->second == 0 && "Predicate node must be from current iteration\n");
+       std::vector<const MachineInstr*> otherInstrs = I->first->getOtherInstrs();
+       for(std::vector<const MachineInstr*>::iterator O = otherInstrs.begin(), OE = otherInstrs.end(); O != OE; ++O) {
+ 	kernel.push_back(std::make_pair((MachineInstr*) *O, I->second));
+       }
+     }
+ 
+   }
+ 
+   std::map<unsigned, MachineInstr*> tmpMap;
+ 
+   //Add remaining invar instructions
+   for(std::map<const MachineInstr*, unsigned>::iterator N = indVar.begin(), NE = indVar.end(); N != NE; ++N) {
+     tmpMap[N->second] = (MachineInstr*) N->first;
+   }
+ 
+   //Add to kernel, and delete from indVar
+   for(std::map<unsigned, MachineInstr*>::iterator N = tmpMap.begin(), NE = tmpMap.end(); N != NE; ++N) {
+     kernel.push_back(std::make_pair(N->second, 0));
+     indVar.erase(N->second);
+   }
+ 
+ 
+   maxStage = maxSN;
+ 
+ 
+   return true;
+ }
+ 
+ bool MSScheduleSB::defPreviousStage(Value *def, int stage) {
+ 
+   //Loop over kernel and determine if value is being defined in previous stage
+   for(std::vector<std::pair<MachineInstr*, int> >::iterator P = kernel.begin(), PE = kernel.end(); P != PE; ++P) {
+     MachineInstr* inst = P->first;
+ 
+     //Loop over Machine Operands
+     for(unsigned i=0; i < inst->getNumOperands(); ++i) {
+       //get machine operand
+      const MachineOperand &mOp = inst->getOperand(i);
+      if(mOp.getType() == MachineOperand::MO_VirtualRegister && mOp.isDef()) {
+        if(def == mOp.getVRegValue()) {
+ 	 if(P->second >= stage)
+ 	   return false;
+ 	 else
+ 	   return true;
+        }
+      }
+     }
+   }
+   
+   assert(0 && "We should always have found the def in our kernel\n");
+ }
+ 
+ 
+ void MSScheduleSB::print(std::ostream &os) const {
+   os << "Schedule:\n";
+ 
+   for(schedule_const_iterator I =  schedule.begin(), E = schedule.end(); I != E; ++I) {
+     os << "Cycle: " << I->first << "\n";
+     for(std::vector<MSchedGraphSBNode*>::const_iterator node = I->second.begin(), nodeEnd = I->second.end(); node != nodeEnd; ++node)
+     os << **node << "\n";
+   }
+ 
+   os << "Kernel:\n";
+   for(std::vector<std::pair<MachineInstr*, int> >::const_iterator I = kernel.begin(),
+ 	E = kernel.end(); I != E; ++I)
+     os << "Node: " << *(I->first) << " Stage: " << I->second << "\n";
+ }
+ 
+ void MSScheduleSB::printSchedule(std::ostream &os) const {
+   os << "Schedule:\n";
+ 
+   for(schedule_const_iterator I =  schedule.begin(), E = schedule.end(); I != E; ++I) {
+     os << "Cycle: " << I->first << "\n";
+     for(std::vector<MSchedGraphSBNode*>::const_iterator node = I->second.begin(), nodeEnd = I->second.end(); node != nodeEnd; ++node)
+     os << **node << "\n";
+   }
+ }


Index: llvm/lib/Target/SparcV9/ModuloScheduling/MSScheduleSB.h
diff -c /dev/null llvm/lib/Target/SparcV9/ModuloScheduling/MSScheduleSB.h:1.1
*** /dev/null	Thu Jun 16 23:15:54 2005
--- llvm/lib/Target/SparcV9/ModuloScheduling/MSScheduleSB.h	Thu Jun 16 23:15:43 2005
***************
*** 0 ****
--- 1,73 ----
+ //===-- MSScheduleSB.h - Schedule ------- -------------------------*- C++ -*-===//
+ //
+ //                     The LLVM Compiler Infrastructure
+ //
+ // This file was developed by the LLVM research group and is distributed under
+ // the University of Illinois Open Source License. See LICENSE.TXT for details.
+ //
+ //===----------------------------------------------------------------------===//
+ //
+ // The schedule generated by a scheduling algorithm
+ //
+ //===----------------------------------------------------------------------===//
+ 
+ #ifndef LLVM_MSSCHEDULESB_H
+ #define LLVM_MSSCHEDULESB_H
+ 
+ #include "MSchedGraphSB.h"
+ #include <vector>
+ #include <set>
+ 
+ namespace llvm {
+ 
+   class MSScheduleSB {
+     std::map<int, std::vector<MSchedGraphSBNode*> > schedule;
+     unsigned numIssue;
+ 
+     //Internal map to keep track of explicit resources
+     std::map<int, std::map<int, int> > resourceNumPerCycle;
+ 
+     //Check if all resources are free
+     bool resourcesFree(MSchedGraphSBNode*, int, int II); 
+     bool resourceAvailable(int resourceNum, int cycle);
+     void useResource(int resourceNum, int cycle);
+ 
+     //Resulting kernel
+     std::vector<std::pair<MachineInstr*, int> > kernel;
+ 
+     //Max stage count
+     int maxStage;
+ 
+     //add at the right spot in the schedule
+     void addToSchedule(int, MSchedGraphSBNode*);
+ 
+   public:
+     MSScheduleSB(int num) : numIssue(num) {}
+     MSScheduleSB() : numIssue(4) {}
+     bool insert(MSchedGraphSBNode *node, int cycle, int II);
+     int getStartCycle(MSchedGraphSBNode *node);
+     void clear() { schedule.clear(); resourceNumPerCycle.clear(); kernel.clear(); }
+     std::vector<std::pair<MachineInstr*, int> >* getKernel() { return &kernel; }
+     bool constructKernel(int II, std::vector<MSchedGraphSBNode*> &branches, std::map<const MachineInstr*, unsigned> &indVar);
+     int getMaxStage() { return maxStage; }
+     bool defPreviousStage(Value *def, int stage);
+ 
+     //iterators
+     typedef std::map<int, std::vector<MSchedGraphSBNode*> >::iterator schedule_iterator;
+     typedef std::map<int, std::vector<MSchedGraphSBNode*> >::const_iterator schedule_const_iterator;
+     schedule_iterator begin() { return schedule.begin(); };
+     schedule_iterator end() { return schedule.end(); };
+     void print(std::ostream &os) const;
+     void printSchedule(std::ostream &os) const;
+ 
+     typedef std::vector<std::pair<MachineInstr*, int> >::iterator kernel_iterator;
+     typedef std::vector<std::pair<MachineInstr*, int> >::const_iterator kernel_const_iterator;
+     kernel_iterator kernel_begin() { return kernel.begin(); }
+     kernel_iterator kernel_end() { return kernel.end(); }
+ 
+   };
+ 
+ }
+ 
+ 
+ #endif


Index: llvm/lib/Target/SparcV9/ModuloScheduling/MSchedGraphSB.cpp
diff -c /dev/null llvm/lib/Target/SparcV9/ModuloScheduling/MSchedGraphSB.cpp:1.1
*** /dev/null	Thu Jun 16 23:15:54 2005
--- llvm/lib/Target/SparcV9/ModuloScheduling/MSchedGraphSB.cpp	Thu Jun 16 23:15:43 2005
***************
*** 0 ****
--- 1,868 ----
+ //===-- MSchedGraphSB.cpp - Scheduling Graph ----------------------*- C++ -*-===//
+ //
+ //                     The LLVM Compiler Infrastructure
+ //
+ // This file was developed by the LLVM research group and is distributed under
+ // the University of Illinois Open Source License. See LICENSE.TXT for details.
+ //
+ //===----------------------------------------------------------------------===//
+ //
+ // A graph class for dependencies. This graph only contains true, anti, and
+ // output data dependencies for a given MachineBasicBlock. Dependencies
+ // across iterations are also computed. Unless data dependence analysis
+ // is provided, a conservative approach of adding dependencies between all
+ // loads and stores is taken.
+ //===----------------------------------------------------------------------===//
+ #define DEBUG_TYPE "ModuloSchedSB"
+ 
+ #include "MSchedGraphSB.h"
+ #include "../SparcV9RegisterInfo.h"
+ #include "../MachineCodeForInstruction.h"
+ #include "llvm/BasicBlock.h"
+ #include "llvm/Constants.h"
+ #include "llvm/Instructions.h"
+ #include "llvm/Type.h"
+ #include "llvm/CodeGen/MachineBasicBlock.h"
+ #include "llvm/Target/TargetInstrInfo.h"
+ #include "llvm/Support/Debug.h"
+ #include <cstdlib>
+ #include <algorithm>
+ #include <set>
+ #include "llvm/Target/TargetSchedInfo.h"
+ #include "../SparcV9Internals.h"
+ 
+ using namespace llvm;
+ 
+ //MSchedGraphSBNode constructor
+ MSchedGraphSBNode::MSchedGraphSBNode(const MachineInstr* inst,
+ 				 MSchedGraphSB *graph, unsigned idx,
+ 				 unsigned late, bool isBranch) 
+   : Inst(inst), Parent(graph), index(idx), latency(late), 
+     isBranchInstr(isBranch) {
+ 
+   //Add to the graph
+   graph->addNode(inst, this);
+ }
+ 
+ //MSchedGraphSBNode constructor
+ MSchedGraphSBNode::MSchedGraphSBNode(const MachineInstr* inst,
+ 				     std::vector<const MachineInstr*> &other,
+ 				     MSchedGraphSB *graph, unsigned idx,
+ 				     unsigned late, bool isPNode)
+   : Inst(inst), otherInstrs(other), Parent(graph), index(idx), latency(late), isPredicateNode(isPNode) {
+     
+ 
+   isBranchInstr = false;
+ 
+   //Add to the graph
+   graph->addNode(inst, this);
+ }
+ 
+ //MSchedGraphSBNode copy constructor
+ MSchedGraphSBNode::MSchedGraphSBNode(const MSchedGraphSBNode &N)
+   : Predecessors(N.Predecessors), Successors(N.Successors) {
+ 
+   Inst = N.Inst;
+   Parent = N.Parent;
+   index = N.index;
+   latency = N.latency;
+   isBranchInstr = N.isBranchInstr;
+   otherInstrs = N.otherInstrs;
+ }
+ 
+ //Print the node (instruction and latency)
+ void MSchedGraphSBNode::print(std::ostream &os) const {
+   if(!isPredicate())
+     os << "MSchedGraphSBNode: Inst=" << *Inst << ", latency= " << latency << "\n";
+   else
+     os << "Pred Node\n";
+ }
+ 
+ 
+ //Get the edge from a predecessor to this node
+ MSchedGraphSBEdge MSchedGraphSBNode::getInEdge(MSchedGraphSBNode *pred) {
+   //Loop over all the successors of our predecessor
+   //return the edge the corresponds to this in edge
+   for (MSchedGraphSBNode::succ_iterator I = pred->succ_begin(),
+          E = pred->succ_end(); I != E; ++I) {
+     if (*I == this)
+       return I.getEdge();
+   }
+   assert(0 && "Should have found edge between this node and its predecessor!");
+   abort();
+ }
+ 
+ //Get the iteration difference for the edge from this node to its successor
+ unsigned MSchedGraphSBNode::getIteDiff(MSchedGraphSBNode *succ) {
+   for(std::vector<MSchedGraphSBEdge>::iterator I = Successors.begin(), 
+ 	E = Successors.end();
+       I != E; ++I) {
+     if(I->getDest() == succ)
+       return I->getIteDiff();
+   }
+   return 0;
+ }
+ 
+ //Get the index into the vector of edges for the edge from pred to this node
+ unsigned MSchedGraphSBNode::getInEdgeNum(MSchedGraphSBNode *pred) {
+   //Loop over all the successors of our predecessor
+   //return the edge the corresponds to this in edge
+   int count = 0;
+   for(MSchedGraphSBNode::succ_iterator I = pred->succ_begin(), 
+ 	E = pred->succ_end();
+       I != E; ++I) {
+     if(*I == this)
+       return count;
+     count++;
+   }
+   assert(0 && "Should have found edge between this node and its predecessor!");
+   abort();
+ }
+ 
+ //Determine if succ is a successor of this node
+ bool MSchedGraphSBNode::isSuccessor(MSchedGraphSBNode *succ) {
+   for(succ_iterator I = succ_begin(), E = succ_end(); I != E; ++I)
+     if(*I == succ)
+       return true;
+   return false;
+ }
+ 
+ //Dtermine if pred is a predecessor of this node
+ bool MSchedGraphSBNode::isPredecessor(MSchedGraphSBNode *pred) {
+   if(std::find( Predecessors.begin(),  Predecessors.end(), 
+ 		pred) !=   Predecessors.end())
+     return true;
+   else
+     return false;
+ }
+ 
+ //Add a node to the graph
+ void MSchedGraphSB::addNode(const MachineInstr* MI,
+ 			  MSchedGraphSBNode *node) {
+ 
+   //Make sure node does not already exist
+   assert(GraphMap.find(MI) == GraphMap.end()
+ 	 && "New MSchedGraphSBNode already exists for this instruction");
+ 
+   GraphMap[MI] = node;
+ }
+ 
+ //Delete a node to the graph
+ void MSchedGraphSB::deleteNode(MSchedGraphSBNode *node) {
+ 
+   //Delete the edge to this node from all predecessors
+   while(node->pred_size() > 0) {
+     //DEBUG(std::cerr << "Delete edge from: " << **P << " to " << *node << "\n");
+     MSchedGraphSBNode *pred = *(node->pred_begin());
+     pred->deleteSuccessor(node);
+   }
+ 
+   //Remove this node from the graph
+   GraphMap.erase(node->getInst());
+ 
+ }
+ 
+ 
+ //Create a graph for a machine block. The ignoreInstrs map is so that
+ //we ignore instructions associated to the index variable since this
+ //is a special case in Modulo Scheduling.  We only want to deal with
+ //the body of the loop.
+ MSchedGraphSB::MSchedGraphSB(std::vector<const MachineBasicBlock*> &bbs, 
+ 			 const TargetMachine &targ, 
+ 			 std::map<const MachineInstr*, unsigned> &ignoreInstrs, 
+ 			 DependenceAnalyzer &DA, 
+ 			 std::map<MachineInstr*, Instruction*> &machineTollvm)
+   : BBs(bbs), Target(targ) {
+ 
+   //Make sure there is at least one BB and it is not null,
+   assert(((bbs.size() >= 1) &&  bbs[1] != NULL) && "Basic Block is null");
+   
+   std::map<MSchedGraphSBNode*, std::set<MachineInstr*> > liveOutsideTrace;
+   std::set<const BasicBlock*> llvmBBs;
+ 
+   for(std::vector<const MachineBasicBlock*>::iterator MBB = bbs.begin(), ME = bbs.end()-1; 
+       MBB != ME; ++MBB)
+     llvmBBs.insert((*MBB)->getBasicBlock());
+ 
+   //create predicate nodes
+   DEBUG("Create predicate nodes\n");
+   for(std::vector<const MachineBasicBlock*>::iterator MBB = bbs.begin(), ME = bbs.end()-1; 
+        MBB != ME; ++MBB) {
+     //Get LLVM basic block
+     BasicBlock *BB = (BasicBlock*) (*MBB)->getBasicBlock();
+     
+     //Get Terminator
+     BranchInst *b = dyn_cast<BranchInst>(BB->getTerminator());
+ 
+     std::vector<const MachineInstr*> otherInstrs;
+     MachineInstr *instr = 0;
+     
+     //Get the condition for the branch (we already checked if it was conditional)
+     if(b->isConditional()) {
+ 
+       Value *cond = b->getCondition();
+       
+       DEBUG(std::cerr << "Condition: " << *cond << "\n");
+       
+       assert(cond && "Condition must not be null!");
+       
+       if(Instruction *I = dyn_cast<Instruction>(cond)) {
+ 	MachineCodeForInstruction & tempMvec = MachineCodeForInstruction::get(I);
+ 	if(tempMvec.size() > 0) {
+ 	  DEBUG(std::cerr << *(tempMvec[tempMvec.size()-1]) << "\n");;
+ 	  instr = (MachineInstr*) tempMvec[tempMvec.size()-1];
+ 	}
+       }
+     }
+ 
+     //Get Machine target information for calculating latency
+     const TargetInstrInfo *MTI = Target.getInstrInfo();
+     
+     MachineCodeForInstruction & tempMvec = MachineCodeForInstruction::get(b);
+     int offset = tempMvec.size();
+     for (unsigned j = 0; j < tempMvec.size(); j++) {
+       MachineInstr *mi = tempMvec[j];
+       if(MTI->isNop(mi->getOpcode()))
+ 	continue;
+ 
+       if(!instr) {
+ 	instr = mi;
+ 	DEBUG(std::cerr << "No Cond MI: " << *mi << "\n");
+       }
+       else {
+ 	DEBUG(std::cerr << *mi << "\n");;
+ 	otherInstrs.push_back(mi);
+       }
+     }
+     
+     //Node is created and added to the graph automatically
+     MSchedGraphSBNode *node =  new MSchedGraphSBNode(instr, otherInstrs, this, (*MBB)->size()-offset-1, 3, true);
+     
+     DEBUG(std::cerr << "Created Node: " << *node << "\n");
+ 
+     //Now loop over all instructions and see if their def is live outside the trace
+     MachineBasicBlock *mb = (MachineBasicBlock*) *MBB;
+     for(MachineBasicBlock::iterator I = mb->begin(), E = mb->end(); I != E; ++I) {
+       MachineInstr *instr = I;
+       if(MTI->isNop(instr->getOpcode()) || MTI->isBranch(instr->getOpcode()))
+ 	continue;
+       if(node->getInst() == instr)
+ 	continue;
+ 
+       for(unsigned i=0; i < instr->getNumOperands(); ++i) {
+ 	MachineOperand &mOp = instr->getOperand(i);
+ 	if(mOp.isDef() && mOp.getType() == MachineOperand::MO_VirtualRegister) {
+ 	  Value *val = mOp.getVRegValue();
+ 	  //Check if there is a use not in the trace
+ 	  for(Value::use_iterator V = val->use_begin(), VE = val->use_end(); V != VE; ++V) {
+ 	    if (Instruction *Inst = dyn_cast<Instruction>(*V)) {
+ 	      if(llvmBBs.count(Inst->getParent()))
+ 		 liveOutsideTrace[node].insert(instr);
+ 	    }
+ 	  }
+ 	}
+       }
+     }
+ 
+     
+   }
+ 
+   //Create nodes and edges for this BB
+   buildNodesAndEdges(ignoreInstrs, DA, machineTollvm, liveOutsideTrace);
+ 
+ }
+ 
+ 
+ //Copies the graph and keeps a map from old to new nodes
+ MSchedGraphSB::MSchedGraphSB(const MSchedGraphSB &G, 
+ 			 std::map<MSchedGraphSBNode*, MSchedGraphSBNode*> &newNodes) 
+   : Target(G.Target) {
+ 
+   BBs = G.BBs;
+ 
+   std::map<MSchedGraphSBNode*, MSchedGraphSBNode*> oldToNew;
+   //Copy all nodes
+   for(MSchedGraphSB::const_iterator N = G.GraphMap.begin(), 
+ 	NE = G.GraphMap.end(); N != NE; ++N) {
+ 
+     MSchedGraphSBNode *newNode = new MSchedGraphSBNode(*(N->second));
+     oldToNew[&*(N->second)] = newNode;
+     newNodes[newNode] = &*(N->second);
+     GraphMap[&*(N->first)] = newNode;
+   }
+ 
+   //Loop over nodes and update edges to point to new nodes
+   for(MSchedGraphSB::iterator N = GraphMap.begin(), NE = GraphMap.end(); 
+       N != NE; ++N) {
+ 
+     //Get the node we are dealing with
+     MSchedGraphSBNode *node = &*(N->second);
+ 
+     node->setParent(this);
+ 
+     //Loop over nodes successors and predecessors and update to the new nodes
+     for(unsigned i = 0; i < node->pred_size(); ++i) {
+       node->setPredecessor(i, oldToNew[node->getPredecessor(i)]);
+     }
+ 
+     for(unsigned i = 0; i < node->succ_size(); ++i) {
+       MSchedGraphSBEdge *edge = node->getSuccessor(i);
+       MSchedGraphSBNode *oldDest = edge->getDest();
+       edge->setDest(oldToNew[oldDest]);
+     }
+   }
+ }
+ 
+ //Deconstructor, deletes all nodes in the graph
+ MSchedGraphSB::~MSchedGraphSB () {
+   for(MSchedGraphSB::iterator I = GraphMap.begin(), E = GraphMap.end(); 
+       I != E; ++I)
+     delete I->second;
+ }
+ 
+ //Print out graph
+ void MSchedGraphSB::print(std::ostream &os) const {
+   for(MSchedGraphSB::const_iterator N = GraphMap.begin(), NE = GraphMap.end(); 
+       N != NE; ++N) {
+     
+     //Get the node we are dealing with
+     MSchedGraphSBNode *node = &*(N->second);
+ 
+     os << "Node Start\n";
+     node->print(os);
+     os << "Successors:\n";
+     //print successors
+     for(unsigned i = 0; i < node->succ_size(); ++i) {
+       MSchedGraphSBEdge *edge = node->getSuccessor(i);
+       MSchedGraphSBNode *oldDest = edge->getDest();
+       oldDest->print(os);
+     }
+     os << "Node End\n";
+   }
+ }
+ 
+ //Calculate total delay
+ int MSchedGraphSB::totalDelay() {
+   int sum = 0;
+ 
+   for(MSchedGraphSB::const_iterator N = GraphMap.begin(), NE = GraphMap.end(); 
+       N != NE; ++N) {
+     
+     //Get the node we are dealing with
+     MSchedGraphSBNode *node = &*(N->second);
+     sum += node->getLatency();
+   }
+   return sum;
+ }
+ 
+ bool MSchedGraphSB::instrCauseException(MachineOpCode opCode) {
+   //Check for integer divide
+   if(opCode == V9::SDIVXr || opCode == V9::SDIVXi 
+      || opCode == V9::UDIVXr || opCode == V9::UDIVXi)
+     return true;
+   
+   //Check for loads or stores
+   const TargetInstrInfo *MTI = Target.getInstrInfo();
+   //if( MTI->isLoad(opCode) || 
+   if(MTI->isStore(opCode))
+     return true;
+ 
+   //Check for any floating point operation
+   const TargetSchedInfo *msi = Target.getSchedInfo();
+   InstrSchedClass sc = msi->getSchedClass(opCode);
+   if(sc == SPARC_FGA || sc == SPARC_FGM)
+     return true;
+ 
+   return false;
+ }
+ 
+ 
+ //Add edges between the nodes
+ void MSchedGraphSB::buildNodesAndEdges(std::map<const MachineInstr*, unsigned> &ignoreInstrs,
+ 				     DependenceAnalyzer &DA,
+ 				       std::map<MachineInstr*, Instruction*> &machineTollvm,
+ 				       std::map<MSchedGraphSBNode*, std::set<MachineInstr*> > &liveOutsideTrace) {
+   
+ 
+   //Get Machine target information for calculating latency
+   const TargetInstrInfo *MTI = Target.getInstrInfo();
+ 
+   std::vector<MSchedGraphSBNode*> memInstructions;
+   std::map<int, std::vector<OpIndexNodePair> > regNumtoNodeMap;
+   std::map<const Value*, std::vector<OpIndexNodePair> > valuetoNodeMap;
+ 
+   //Save PHI instructions to deal with later
+   std::vector<const MachineInstr*> phiInstrs;
+   unsigned index = 0;
+ 
+   MSchedGraphSBNode *lastPred = 0;
+       
+ 
+   for(std::vector<const MachineBasicBlock*>::iterator B = BBs.begin(), 
+ 	BE = BBs.end(); B != BE; ++B) {
+     
+     const MachineBasicBlock *BB = *B;
+ 
+ 
+     //Loop over instructions in MBB and add nodes and edges
+     for (MachineBasicBlock::const_iterator MI = BB->begin(), e = BB->end(); 
+ 	 MI != e; ++MI) {
+       
+       //Ignore indvar instructions
+       if(ignoreInstrs.count(MI)) {
+ 	++index;
+ 	continue;
+       }
+       
+       //Get each instruction of machine basic block, get the delay
+       //using the op code, create a new node for it, and add to the
+       //graph.
+       
+       MachineOpCode opCode = MI->getOpcode();
+       int delay;
+       
+       //Get delay
+       delay = MTI->maxLatency(opCode);
+       
+       //Create new node for this machine instruction and add to the graph.
+       //Create only if not a nop
+       if(MTI->isNop(opCode))
+ 	continue;
+       
+       //Sparc BE does not use PHI opcode, so assert on this case
+       assert(opCode != TargetInstrInfo::PHI && "Did not expect PHI opcode");
+       
+       bool isBranch = false;
+ 
+       //Skip branches
+       if(MTI->isBranch(opCode))
+ 	continue;
+       
+       //Node is created and added to the graph automatically
+       MSchedGraphSBNode *node = 0;
+       if(!GraphMap.count(MI)){
+ 	node =  new MSchedGraphSBNode(MI, this, index, delay);
+ 	DEBUG(std::cerr << "Created Node: " << *node << "\n");
+       }
+       else {
+ 	node = GraphMap[MI];
+ 	if(node->isPredicate()) {
+ 	  //Create edge between this node and last pred, then switch to new pred
+ 	  if(lastPred) {
+ 	    lastPred->addOutEdge(node, MSchedGraphSBEdge::PredDep,
+ 	    MSchedGraphSBEdge::NonDataDep, 0);
+ 	    
+ 	    if(liveOutsideTrace.count(lastPred)) {
+ 	      for(std::set<MachineInstr*>::iterator L = liveOutsideTrace[lastPred].begin(), LE = liveOutsideTrace[lastPred].end(); L != LE; ++L)
+ 		lastPred->addOutEdge(GraphMap[*L], MSchedGraphSBEdge::PredDep,
+ 				     MSchedGraphSBEdge::NonDataDep, 1);
+ 	    }
+ 
+ 	  }
+ 	      
+ 	  lastPred = node;
+ 	}
+       }
+ 
+       //Add dependencies to instructions that cause exceptions
+       if(lastPred)
+ 	lastPred->print(std::cerr);
+ 
+       if(!node->isPredicate() && instrCauseException(opCode)) {
+ 	if(lastPred) {
+ 	  lastPred->addOutEdge(node, MSchedGraphSBEdge::PredDep,
+ 			       MSchedGraphSBEdge::NonDataDep, 0);
+ 	}
+       }
+       
+ 
+       //Check OpCode to keep track of memory operations to add memory
+       //dependencies later.
+       if(MTI->isLoad(opCode) || MTI->isStore(opCode))
+ 	memInstructions.push_back(node);
+       
+       //Loop over all operands, and put them into the register number to
+       //graph node map for determining dependencies
+       //If an operands is a use/def, we have an anti dependence to itself
+       for(unsigned i=0; i < MI->getNumOperands(); ++i) {
+ 	//Get Operand
+ 	const MachineOperand &mOp = MI->getOperand(i);
+ 	
+ 	//Check if it has an allocated register
+ 	if(mOp.hasAllocatedReg()) {
+ 	  int regNum = mOp.getReg();
+ 	  
+ 	  if(regNum != SparcV9::g0) {
+ 	    //Put into our map
+ 	    regNumtoNodeMap[regNum].push_back(std::make_pair(i, node));
+ 	  }
+ 	  continue;
+ 	}
+ 	
+ 	
+ 	//Add virtual registers dependencies
+ 	//Check if any exist in the value map already and create dependencies
+ 	//between them.
+ 	if(mOp.getType() == MachineOperand::MO_VirtualRegister 
+ 	   ||  mOp.getType() == MachineOperand::MO_CCRegister) {
+ 	  
+ 	  //Make sure virtual register value is not null
+ 	  assert((mOp.getVRegValue() != NULL) && "Null value is defined");
+ 	  
+ 	  //Check if this is a read operation in a phi node, if so DO NOT PROCESS
+ 	  if(mOp.isUse() && (opCode == TargetInstrInfo::PHI)) {
+ 	    DEBUG(std::cerr << "Read Operation in a PHI node\n");
+ 	    continue;
+ 	  }
+ 	  
+ 	  if (const Value* srcI = mOp.getVRegValue()) {
+ 	    
+ 	    //Find value in the map
+ 	    std::map<const Value*, std::vector<OpIndexNodePair> >::iterator V
+ 	      = valuetoNodeMap.find(srcI);
+ 	    
+ 	    //If there is something in the map already, add edges from
+ 	    //those instructions
+ 	    //to this one we are processing
+ 	    if(V != valuetoNodeMap.end()) {
+ 	      addValueEdges(V->second, node, mOp.isUse(), mOp.isDef(), phiInstrs);
+ 	      
+ 	      //Add to value map
+ 	      V->second.push_back(std::make_pair(i,node));
+ 	    }
+ 	    //Otherwise put it in the map
+ 	    else
+ 	      //Put into value map
+ 	      valuetoNodeMap[mOp.getVRegValue()].push_back(std::make_pair(i, node));
+ 	  }
+ 	}
+       }
+       ++index;
+     }
+     
+     //Loop over LLVM BB, examine phi instructions, and add them to our
+     //phiInstr list to process
+     const BasicBlock *llvm_bb = BB->getBasicBlock();
+     for(BasicBlock::const_iterator I = llvm_bb->begin(), E = llvm_bb->end(); 
+ 	I != E; ++I) {
+       if(const PHINode *PN = dyn_cast<PHINode>(I)) {
+ 	MachineCodeForInstruction & tempMvec = MachineCodeForInstruction::get(PN);
+ 	for (unsigned j = 0; j < tempMvec.size(); j++) {
+ 	  if(!ignoreInstrs.count(tempMvec[j])) {
+ 	    DEBUG(std::cerr << "Inserting phi instr into map: " << *tempMvec[j] << "\n");
+ 	    phiInstrs.push_back((MachineInstr*) tempMvec[j]);
+ 	  }
+ 	}
+       }
+       
+     }
+     
+     addMemEdges(memInstructions, DA, machineTollvm);
+     addMachRegEdges(regNumtoNodeMap);
+     
+     //Finally deal with PHI Nodes and Value*
+     for(std::vector<const MachineInstr*>::iterator I = phiInstrs.begin(), 
+ 	  E = phiInstrs.end(); I != E;  ++I) {
+       
+       //Get Node for this instruction
+       std::map<const MachineInstr*, MSchedGraphSBNode*>::iterator X;
+       X = find(*I);
+       
+       if(X == GraphMap.end())
+ 	continue;
+       
+       MSchedGraphSBNode *node = X->second;
+       
+       DEBUG(std::cerr << "Adding ite diff edges for node: " << *node << "\n");
+       
+       //Loop over operands for this instruction and add value edges
+       for(unsigned i=0; i < (*I)->getNumOperands(); ++i) {
+ 	//Get Operand
+ 	const MachineOperand &mOp = (*I)->getOperand(i);
+ 	if((mOp.getType() == MachineOperand::MO_VirtualRegister 
+ 	    ||  mOp.getType() == MachineOperand::MO_CCRegister) && mOp.isUse()) {
+ 	  
+ 	  //find the value in the map
+ 	  if (const Value* srcI = mOp.getVRegValue()) {
+ 	    
+ 	    //Find value in the map
+ 	    std::map<const Value*, std::vector<OpIndexNodePair> >::iterator V
+ 	      = valuetoNodeMap.find(srcI);
+ 	    
+ 	    //If there is something in the map already, add edges from
+ 	    //those instructions
+ 	    //to this one we are processing
+ 	    if(V != valuetoNodeMap.end()) {
+ 	      addValueEdges(V->second, node, mOp.isUse(), mOp.isDef(), 
+ 			    phiInstrs, 1);
+ 	    }
+ 	  }
+ 	}
+       }
+     }
+   }
+ }
+ //Add dependencies for Value*s
+ void MSchedGraphSB::addValueEdges(std::vector<OpIndexNodePair> &NodesInMap,
+ 				MSchedGraphSBNode *destNode, bool nodeIsUse,
+ 				bool nodeIsDef, std::vector<const MachineInstr*> &phiInstrs, int diff) {
+ 
+   for(std::vector<OpIndexNodePair>::iterator I = NodesInMap.begin(),
+ 	E = NodesInMap.end(); I != E; ++I) {
+ 
+     //Get node in vectors machine operand that is the same value as node
+     MSchedGraphSBNode *srcNode = I->second;
+     MachineOperand mOp = srcNode->getInst()->getOperand(I->first);
+ 
+     if(diff > 0)
+       if(std::find(phiInstrs.begin(), phiInstrs.end(), srcNode->getInst()) == phiInstrs.end())
+ 	continue;
+ 
+     //Node is a Def, so add output dep.
+     if(nodeIsDef) {
+       if(mOp.isUse()) {
+ 	DEBUG(std::cerr << "Edge from " << *srcNode << " to " << *destNode << " (itediff=" << diff << ", type=anti)\n");
+ 	srcNode->addOutEdge(destNode, MSchedGraphSBEdge::ValueDep,
+ 			    MSchedGraphSBEdge::AntiDep, diff);
+       }
+       if(mOp.isDef()) {
+ 	DEBUG(std::cerr << "Edge from " << *srcNode << " to " << *destNode << " (itediff=" << diff << ", type=output)\n");
+ 	srcNode->addOutEdge(destNode, MSchedGraphSBEdge::ValueDep,
+ 			    MSchedGraphSBEdge::OutputDep, diff);
+       }
+     }
+     if(nodeIsUse) {
+       if(mOp.isDef()) {
+ 	DEBUG(std::cerr << "Edge from " << *srcNode << " to " << *destNode << " (itediff=" << diff << ", type=true)\n");
+ 	srcNode->addOutEdge(destNode, MSchedGraphSBEdge::ValueDep,
+ 			    MSchedGraphSBEdge::TrueDep, diff);
+       }
+     }
+   }
+ }
+ 
+ //Add dependencies for machine registers across iterations
+ void MSchedGraphSB::addMachRegEdges(std::map<int, std::vector<OpIndexNodePair> >& regNumtoNodeMap) {
+   //Loop over all machine registers in the map, and add dependencies
+   //between the instructions that use it
+   typedef std::map<int, std::vector<OpIndexNodePair> > regNodeMap;
+   for(regNodeMap::iterator I = regNumtoNodeMap.begin(); 
+       I != regNumtoNodeMap.end(); ++I) {
+     //Get the register number
+     int regNum = (*I).first;
+ 
+     //Get Vector of nodes that use this register
+     std::vector<OpIndexNodePair> Nodes = (*I).second;
+ 
+     //Loop over nodes and determine the dependence between the other
+     //nodes in the vector
+     for(unsigned i =0; i < Nodes.size(); ++i) {
+ 
+       //Get src node operator index that uses this machine register
+       int srcOpIndex = Nodes[i].first;
+ 
+       //Get the actual src Node
+       MSchedGraphSBNode *srcNode = Nodes[i].second;
+ 
+       //Get Operand
+       const MachineOperand &srcMOp = srcNode->getInst()->getOperand(srcOpIndex);
+ 
+       bool srcIsUseandDef = srcMOp.isDef() && srcMOp.isUse();
+       bool srcIsUse = srcMOp.isUse() && !srcMOp.isDef();
+ 
+ 
+       //Look at all instructions after this in execution order
+       for(unsigned j=i+1; j < Nodes.size(); ++j) {
+ 	
+ 	//Sink node is a write
+ 	if(Nodes[j].second->getInst()->getOperand(Nodes[j].first).isDef()) {
+ 	              //Src only uses the register (read)
+             if(srcIsUse)
+ 	      srcNode->addOutEdge(Nodes[j].second, 
+ 				  MSchedGraphSBEdge::MachineRegister,
+ 				  MSchedGraphSBEdge::AntiDep);
+ 	
+             else if(srcIsUseandDef) {
+ 	      srcNode->addOutEdge(Nodes[j].second, 
+ 				  MSchedGraphSBEdge::MachineRegister,
+ 				  MSchedGraphSBEdge::AntiDep);
+ 	      
+ 	      srcNode->addOutEdge(Nodes[j].second, 
+ 				  MSchedGraphSBEdge::MachineRegister,
+ 				  MSchedGraphSBEdge::OutputDep);
+ 	    }
+             else
+ 	      srcNode->addOutEdge(Nodes[j].second, 
+ 				  MSchedGraphSBEdge::MachineRegister,
+ 				  MSchedGraphSBEdge::OutputDep);
+ 	}
+ 	//Dest node is a read
+ 	else {
+ 	  if(!srcIsUse || srcIsUseandDef)
+ 	    srcNode->addOutEdge(Nodes[j].second, 
+ 				MSchedGraphSBEdge::MachineRegister,
+ 				MSchedGraphSBEdge::TrueDep);
+ 	}
+ 
+       }
+ 
+       //Look at all the instructions before this one since machine registers
+       //could live across iterations.
+       for(unsigned j = 0; j < i; ++j) {
+ 		//Sink node is a write
+ 	if(Nodes[j].second->getInst()->getOperand(Nodes[j].first).isDef()) {
+ 	              //Src only uses the register (read)
+             if(srcIsUse)
+ 	      srcNode->addOutEdge(Nodes[j].second, 
+ 				  MSchedGraphSBEdge::MachineRegister,
+ 				  MSchedGraphSBEdge::AntiDep, 1);
+             else if(srcIsUseandDef) {
+ 	      srcNode->addOutEdge(Nodes[j].second, 
+ 				  MSchedGraphSBEdge::MachineRegister,
+ 				  MSchedGraphSBEdge::AntiDep, 1);
+ 	      
+ 	      srcNode->addOutEdge(Nodes[j].second, 
+ 				  MSchedGraphSBEdge::MachineRegister,
+ 				  MSchedGraphSBEdge::OutputDep, 1);
+ 	    }
+             else
+ 	      srcNode->addOutEdge(Nodes[j].second, 
+ 				  MSchedGraphSBEdge::MachineRegister,
+ 				  MSchedGraphSBEdge::OutputDep, 1);
+ 	}
+ 	//Dest node is a read
+ 	else {
+ 	  if(!srcIsUse || srcIsUseandDef)
+ 	    srcNode->addOutEdge(Nodes[j].second, 
+ 				MSchedGraphSBEdge::MachineRegister,
+ 				MSchedGraphSBEdge::TrueDep,1 );
+ 	}
+ 	
+ 
+       }
+ 
+     }
+ 
+   }
+ 
+ }
+ 
+ //Add edges between all loads and stores
+ //Can be less strict with alias analysis and data dependence analysis.
+ void MSchedGraphSB::addMemEdges(const std::vector<MSchedGraphSBNode*>& memInst, 
+ 		      DependenceAnalyzer &DA, 
+ 		      std::map<MachineInstr*, Instruction*> &machineTollvm) {
+ 
+   //Get Target machine instruction info
+   const TargetInstrInfo *TMI = Target.getInstrInfo();
+ 
+   //Loop over all memory instructions in the vector
+   //Knowing that they are in execution, add true, anti, and output dependencies
+   for (unsigned srcIndex = 0; srcIndex < memInst.size(); ++srcIndex) {
+ 
+     MachineInstr *srcInst = (MachineInstr*) memInst[srcIndex]->getInst();
+ 
+     //Get the machine opCode to determine type of memory instruction
+     MachineOpCode srcNodeOpCode = srcInst->getOpcode();
+     
+     //All instructions after this one in execution order have an
+     //iteration delay of 0
+     for(unsigned destIndex = 0; destIndex < memInst.size(); ++destIndex) {
+ 
+       //No self loops
+       if(destIndex == srcIndex)
+ 	continue;
+ 
+       MachineInstr *destInst = (MachineInstr*) memInst[destIndex]->getInst();
+ 
+       DEBUG(std::cerr << "MInst1: " << *srcInst << "\n");
+       DEBUG(std::cerr << "MInst2: " << *destInst << "\n");
+       
+       //Assuming instructions without corresponding llvm instructions
+       //are from constant pools.
+       if (!machineTollvm.count(srcInst) || !machineTollvm.count(destInst))
+ 	continue;
+       
+       bool useDepAnalyzer = true;
+ 
+       //Some machine loads and stores are generated by casts, so be
+       //conservative and always add deps
+       Instruction *srcLLVM = machineTollvm[srcInst];
+       Instruction *destLLVM = machineTollvm[destInst];
+       if(!isa<LoadInst>(srcLLVM) 
+ 	 && !isa<StoreInst>(srcLLVM)) {
+ 	if(isa<BinaryOperator>(srcLLVM)) {
+ 	  if(isa<ConstantFP>(srcLLVM->getOperand(0)) || isa<ConstantFP>(srcLLVM->getOperand(1)))
+ 	    continue;
+ 	}
+ 	useDepAnalyzer = false;
+       }
+       if(!isa<LoadInst>(destLLVM) 
+ 	 && !isa<StoreInst>(destLLVM)) {
+ 	if(isa<BinaryOperator>(destLLVM)) {
+ 	  if(isa<ConstantFP>(destLLVM->getOperand(0)) || isa<ConstantFP>(destLLVM->getOperand(1)))
+ 	    continue;
+ 	}
+ 	useDepAnalyzer = false;
+       }
+ 
+       //Use dep analysis when we have corresponding llvm loads/stores
+       if(useDepAnalyzer) {
+ 	bool srcBeforeDest = true;
+ 	if(destIndex < srcIndex)
+ 	  srcBeforeDest = false;
+ 
+ 	DependenceResult dr = DA.getDependenceInfo(machineTollvm[srcInst], 
+ 						   machineTollvm[destInst], 
+ 						   srcBeforeDest);
+ 	
+ 	for(std::vector<Dependence>::iterator d = dr.dependences.begin(), 
+ 	      de = dr.dependences.end(); d != de; ++d) {
+ 	  //Add edge from load to store
+ 	  memInst[srcIndex]->addOutEdge(memInst[destIndex], 
+ 					MSchedGraphSBEdge::MemoryDep, 
+ 					d->getDepType(), d->getIteDiff());
+ 	  
+ 	}
+       }
+       //Otherwise, we can not do any further analysis and must make a dependence
+       else {
+ 		
+ 	//Get the machine opCode to determine type of memory instruction
+ 	MachineOpCode destNodeOpCode = destInst->getOpcode();
+ 
+ 	//Get the Value* that we are reading from the load, always the first op
+ 	const MachineOperand &mOp = srcInst->getOperand(0);
+ 	const MachineOperand &mOp2 = destInst->getOperand(0);
+ 	
+ 	if(mOp.hasAllocatedReg())
+ 	  if(mOp.getReg() == SparcV9::g0)
+ 	    continue;
+ 	if(mOp2.hasAllocatedReg())
+ 	  if(mOp2.getReg() == SparcV9::g0)
+ 	    continue;
+ 
+ 	DEBUG(std::cerr << "Adding dependence for machine instructions\n");
+ 	//Load-Store deps
+ 	if(TMI->isLoad(srcNodeOpCode)) {
+ 
+ 	  if(TMI->isStore(destNodeOpCode))
+ 	    memInst[srcIndex]->addOutEdge(memInst[destIndex], 
+ 					  MSchedGraphSBEdge::MemoryDep, 
+ 					  MSchedGraphSBEdge::AntiDep, 0);
+ 	}
+ 	else if(TMI->isStore(srcNodeOpCode)) {
+ 	  if(TMI->isStore(destNodeOpCode))
+ 	    memInst[srcIndex]->addOutEdge(memInst[destIndex], 
+ 					  MSchedGraphSBEdge::MemoryDep, 
+ 					  MSchedGraphSBEdge::OutputDep, 0);
+ 
+ 	  else
+ 	    memInst[srcIndex]->addOutEdge(memInst[destIndex], 
+ 					  MSchedGraphSBEdge::MemoryDep, 
+ 					  MSchedGraphSBEdge::TrueDep, 0);
+ 	}
+       }
+     }
+   }
+ }





From tbrethou at cs.uiuc.edu  Thu Jun 16 23:16:25 2005
From: tbrethou at cs.uiuc.edu (Tanya Brethour)
Date: Thu, 16 Jun 2005 23:16:25 -0500
Subject: [llvm-commits] 
	CVS: llvm/lib/Target/SparcV9/ModuloScheduling/MSchedGraphSB.h
Message-ID: <200506170416.XAA29868@zion.cs.uiuc.edu>



Changes in directory llvm/lib/Target/SparcV9/ModuloScheduling:

MSchedGraphSB.h added (r1.1)
---
Log message:

Special dep graph for SMS for superblocks.


---
Diffs of the changes:  (+410 -0)

 MSchedGraphSB.h |  410 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++
 1 files changed, 410 insertions(+)


Index: llvm/lib/Target/SparcV9/ModuloScheduling/MSchedGraphSB.h
diff -c /dev/null llvm/lib/Target/SparcV9/ModuloScheduling/MSchedGraphSB.h:1.1
*** /dev/null	Thu Jun 16 23:16:24 2005
--- llvm/lib/Target/SparcV9/ModuloScheduling/MSchedGraphSB.h	Thu Jun 16 23:16:14 2005
***************
*** 0 ****
--- 1,410 ----
+ //===-- MSchedGraphSB.h - Scheduling Graph ------------------------*- C++ -*-===//
+ //
+ //                     The LLVM Compiler Infrastructure
+ //
+ // This file was developed by the LLVM research group and is distributed under
+ // the University of Illinois Open Source License. See LICENSE.TXT for details.
+ //
+ //===----------------------------------------------------------------------===//
+ //
+ // A graph class for dependencies. This graph only contains true, anti, and
+ // output data dependencies for a vector of MachineBasicBlock. Dependencies
+ // across iterations are also computed. Unless data dependence analysis
+ // is provided, a conservative approach of adding dependencies between all
+ // loads and stores is taken. It also includes pseudo predicate nodes for
+ // modulo scheduling superblocks.
+ //===----------------------------------------------------------------------===//
+ 
+ #ifndef LLVM_MSCHEDGRAPHSB_H
+ #define LLVM_MSCHEDGRAPHSB_H
+ #include "DependenceAnalyzer.h"
+ #include "llvm/Analysis/AliasAnalysis.h"
+ #include "llvm/CodeGen/MachineInstr.h"
+ #include "llvm/Target/TargetMachine.h"
+ #include "llvm/Target/TargetData.h"
+ #include "llvm/ADT/GraphTraits.h"
+ #include "llvm/ADT/STLExtras.h"
+ #include "llvm/ADT/iterator"
+ #include <vector>
+ 
+ 
+ namespace llvm {
+ 
+   class MSchedGraphSB;
+   class MSchedGraphSBNode;
+   template<class IteratorType, class NodeType>
+   class MSchedGraphSBNodeIterator;
+ 
+   //MSchedGraphSBEdge encapsulates the data dependence between nodes. It
+   //identifies the dependence type, on what, and the iteration
+   //difference
+   struct MSchedGraphSBEdge {
+     enum DataDepOrderType {
+       TrueDep, AntiDep, OutputDep, NonDataDep
+     };
+ 
+     enum MSchedGraphSBEdgeType {
+       MemoryDep, ValueDep, MachineRegister, PredDep
+     };
+ 
+     //Get or set edge data
+     MSchedGraphSBNode *getDest() const { return dest; }
+     unsigned getIteDiff() { return iteDiff; }
+     unsigned getDepOrderType() { return depOrderType; }
+     void setDest(MSchedGraphSBNode *newDest) { dest = newDest; }
+ 
+   private:
+     friend class MSchedGraphSBNode;
+     MSchedGraphSBEdge(MSchedGraphSBNode *destination, MSchedGraphSBEdgeType type,
+ 		    unsigned deptype, unsigned diff)
+       : dest(destination), depType(type), depOrderType(deptype), iteDiff(diff) {}
+ 
+     MSchedGraphSBNode *dest;
+     MSchedGraphSBEdgeType depType;
+     unsigned depOrderType;
+     unsigned iteDiff;
+   };
+ 
+   //MSchedGraphSBNode represents a machine instruction and its
+   //corresponding latency. Each node also contains a list of its
+   //predecessors and sucessors.
+   class MSchedGraphSBNode {
+ 
+     const MachineInstr* Inst; //Machine Instruction
+     std::vector<const MachineInstr*> otherInstrs;
+ 
+     MSchedGraphSB* Parent; //Graph this node belongs to
+     unsigned index; //Index in BB
+     unsigned latency; //Latency of Instruction
+     bool isBranchInstr; //Is this node the branch instr or not
+     bool isPredicateNode; //Indicate if this node should be treated like a predicate
+ 
+     std::vector<MSchedGraphSBNode*> Predecessors; //Predecessor Nodes
+     std::vector<MSchedGraphSBEdge> Successors; //Successor edges
+ 
+   public:
+     MSchedGraphSBNode(const MachineInstr* inst, MSchedGraphSB *graph,
+ 		    unsigned index, unsigned late=0, bool isBranch=false);
+     MSchedGraphSBNode(const MachineInstr* inst, std::vector<const MachineInstr*> &other, 
+ 		      MSchedGraphSB *graph,
+ 		      unsigned index, unsigned late=0, bool isPNode=true);
+     MSchedGraphSBNode(const MSchedGraphSBNode &N);
+ 
+     //Iterators - Predecessor and Succussor
+     typedef std::vector<MSchedGraphSBNode*>::iterator pred_iterator;
+     pred_iterator pred_begin() { return Predecessors.begin(); }
+     pred_iterator pred_end() { return Predecessors.end(); }
+     unsigned pred_size() { return Predecessors.size(); }
+ 
+     typedef std::vector<MSchedGraphSBNode*>::const_iterator pred_const_iterator;
+     pred_const_iterator pred_begin() const { return Predecessors.begin(); }
+     pred_const_iterator pred_end() const { return Predecessors.end(); }
+ 
+     typedef MSchedGraphSBNodeIterator<std::vector<MSchedGraphSBEdge>::const_iterator,
+ 				    const MSchedGraphSBNode> succ_const_iterator;
+     succ_const_iterator succ_begin() const;
+     succ_const_iterator succ_end() const;
+ 
+     typedef MSchedGraphSBNodeIterator<std::vector<MSchedGraphSBEdge>::iterator,
+ 				    MSchedGraphSBNode> succ_iterator;
+     succ_iterator succ_begin();
+     succ_iterator succ_end();
+     unsigned succ_size() { return Successors.size(); }
+ 
+     //Get or set predecessor nodes, or successor edges
+     void setPredecessor(unsigned index, MSchedGraphSBNode *dest) {
+       Predecessors[index] = dest;
+     }
+ 
+     MSchedGraphSBNode* getPredecessor(unsigned index) {
+       return Predecessors[index];
+     }
+ 
+     MSchedGraphSBEdge* getSuccessor(unsigned index) {
+       return &Successors[index];
+     }
+ 
+     void deleteSuccessor(MSchedGraphSBNode *node) {
+       for (unsigned i = 0; i != Successors.size(); ++i)
+ 	if (Successors[i].getDest() == node) {
+ 	  Successors.erase(Successors.begin()+i);
+ 	  node->Predecessors.erase(std::find(node->Predecessors.begin(),
+ 					     node->Predecessors.end(), this));
+ 	  --i; //Decrease index var since we deleted a node
+ 	}
+     }
+ 
+     void addOutEdge(MSchedGraphSBNode *destination,
+ 		    MSchedGraphSBEdge::MSchedGraphSBEdgeType type,
+ 		    unsigned deptype, unsigned diff=0) {
+       Successors.push_back(MSchedGraphSBEdge(destination, type, deptype,diff));
+       destination->Predecessors.push_back(this);
+     }
+ 
+     //General methods to get and set data for the node
+     const MachineInstr* getInst() { return Inst; }
+     MSchedGraphSB* getParent() { return Parent; }
+     bool hasPredecessors() { return (Predecessors.size() > 0); }
+     bool hasSuccessors() { return (Successors.size() > 0); }
+     unsigned getLatency() { return latency; }
+     unsigned getLatency() const { return latency; }
+     unsigned getIndex() { return index; }
+     unsigned getIteDiff(MSchedGraphSBNode *succ);
+     MSchedGraphSBEdge getInEdge(MSchedGraphSBNode *pred);
+     unsigned getInEdgeNum(MSchedGraphSBNode *pred);
+     bool isSuccessor(MSchedGraphSBNode *);
+     bool isPredecessor(MSchedGraphSBNode *);
+     bool isBranch() { return isBranchInstr; }
+     bool isPredicate() { return isPredicateNode; }
+     bool isPredicate() const { return isPredicateNode; }
+     std::vector<const MachineInstr*> getOtherInstrs() { return otherInstrs; }
+ 
+     //Debug support
+     void print(std::ostream &os) const;
+     void setParent(MSchedGraphSB *p) { Parent = p; }
+   };
+ 
+   //Node iterator for graph generation
+   template<class IteratorType, class NodeType>
+   class MSchedGraphSBNodeIterator : public forward_iterator<NodeType*, ptrdiff_t> {
+     IteratorType I;   // std::vector<MSchedGraphSBEdge>::iterator or const_iterator
+   public:
+     MSchedGraphSBNodeIterator(IteratorType i) : I(i) {}
+ 
+     bool operator==(const MSchedGraphSBNodeIterator RHS) const { return I == RHS.I; }
+     bool operator!=(const MSchedGraphSBNodeIterator RHS) const { return I != RHS.I; }
+ 
+     const MSchedGraphSBNodeIterator &operator=(const MSchedGraphSBNodeIterator &RHS) {
+       I = RHS.I;
+       return *this;
+     }
+ 
+     NodeType* operator*() const {
+       return I->getDest();
+     }
+     NodeType* operator->() const { return operator*(); }
+ 
+     MSchedGraphSBNodeIterator& operator++() {                // Preincrement
+       ++I;
+       return *this;
+     }
+     MSchedGraphSBNodeIterator operator++(int) { // Postincrement
+       MSchedGraphSBNodeIterator tmp = *this; ++*this; return tmp;
+     }
+ 
+     MSchedGraphSBEdge &getEdge() {
+       return *I;
+     }
+     const MSchedGraphSBEdge &getEdge() const {
+       return *I;
+     }
+   };
+ 
+   inline MSchedGraphSBNode::succ_const_iterator MSchedGraphSBNode::succ_begin() const {
+     return succ_const_iterator(Successors.begin());
+   }
+   inline MSchedGraphSBNode::succ_const_iterator MSchedGraphSBNode::succ_end() const {
+     return succ_const_iterator(Successors.end());
+   }
+   inline MSchedGraphSBNode::succ_iterator MSchedGraphSBNode::succ_begin() {
+     return succ_iterator(Successors.begin());
+   }
+   inline MSchedGraphSBNode::succ_iterator MSchedGraphSBNode::succ_end() {
+     return succ_iterator(Successors.end());
+   }
+ 
+   // ostream << operator for MSGraphNode class
+   inline std::ostream &operator<<(std::ostream &os,
+ 				  const MSchedGraphSBNode &node) {
+     node.print(os);
+     return os;
+   }
+ 
+ 
+   // Provide specializations of GraphTraits to be able to use graph
+   // iterators on the scheduling graph!
+   //
+   template <> struct GraphTraits<MSchedGraphSBNode*> {
+     typedef MSchedGraphSBNode NodeType;
+     typedef MSchedGraphSBNode::succ_iterator ChildIteratorType;
+ 
+     static inline ChildIteratorType child_begin(NodeType *N) {
+       return N->succ_begin();
+     }
+     static inline ChildIteratorType child_end(NodeType *N) {
+       return N->succ_end();
+     }
+ 
+     static NodeType *getEntryNode(NodeType* N) { return N; }
+   };
+ 
+ 
+ 
+   //Graph class to represent dependence graph
+   class MSchedGraphSB {
+ 
+     std::vector<const MachineBasicBlock *> BBs; //Machine basic block
+     const TargetMachine &Target; //Target Machine
+ 
+     //Nodes
+     std::map<const MachineInstr*, MSchedGraphSBNode*> GraphMap;
+ 
+     //Add Nodes and Edges to this graph for our BB
+     typedef std::pair<int, MSchedGraphSBNode*> OpIndexNodePair;
+     void buildNodesAndEdges(std::map<const MachineInstr*, unsigned> &ignoreInstrs, DependenceAnalyzer &DA, std::map<MachineInstr*, Instruction*> &machineTollvm, std::map<MSchedGraphSBNode*, std::set<MachineInstr*> > &liveOutsideTrace);
+     void addValueEdges(std::vector<OpIndexNodePair> &NodesInMap,
+ 		       MSchedGraphSBNode *node,
+ 		       bool nodeIsUse, bool nodeIsDef, std::vector<const MachineInstr*> &phiInstrs, int diff=0);
+     void addMachRegEdges(std::map<int,
+ 			 std::vector<OpIndexNodePair> >& regNumtoNodeMap);
+     void addMemEdges(const std::vector<MSchedGraphSBNode*>& memInst,
+ 		     DependenceAnalyzer &DA, std::map<MachineInstr*, Instruction*> &machineTollvm);
+     
+ 
+     bool instrCauseException(MachineOpCode opCode);
+ 
+   public:
+     MSchedGraphSB(const MachineBasicBlock *bb, const TargetMachine &targ,
+ 		std::map<const MachineInstr*, unsigned> &ignoreInstrs,
+ 		DependenceAnalyzer &DA, std::map<MachineInstr*, Instruction*> &machineTollvm);
+ 
+     //Copy constructor with maps to link old nodes to new nodes
+     MSchedGraphSB(const MSchedGraphSB &G, std::map<MSchedGraphSBNode*, MSchedGraphSBNode*> &newNodes);
+     
+     MSchedGraphSB(std::vector<const MachineBasicBlock*> &bbs, 
+ 		const TargetMachine &targ, 
+ 		std::map<const MachineInstr*, unsigned> &ignoreInstrs, 
+ 		DependenceAnalyzer &DA, 
+ 		std::map<MachineInstr*, Instruction*> &machineTollvm);
+ 
+     //Print graph
+     void print(std::ostream &os) const;
+ 
+     //Deconstructor!
+     ~MSchedGraphSB();
+ 
+     //Add or delete nodes from the Graph
+     void addNode(const MachineInstr* MI, MSchedGraphSBNode *node);
+     void deleteNode(MSchedGraphSBNode *node);
+     int totalDelay();
+ 
+     //iterators
+     typedef std::map<const MachineInstr*, MSchedGraphSBNode*>::iterator iterator;
+     typedef std::map<const MachineInstr*, MSchedGraphSBNode*>::const_iterator const_iterator;
+     typedef std::map<const MachineInstr*, MSchedGraphSBNode*>::reverse_iterator reverse_iterator;
+     iterator find(const MachineInstr* I) { return GraphMap.find(I); }
+     iterator end() { return GraphMap.end(); }
+     iterator begin() { return GraphMap.begin(); }
+     unsigned size() { return GraphMap.size(); }
+     reverse_iterator rbegin() { return GraphMap.rbegin(); }
+     reverse_iterator rend() { return GraphMap.rend(); }
+ 
+     //Get Target or original machine basic block
+     const TargetMachine* getTarget() { return &Target; }
+     std::vector<const MachineBasicBlock*> getBBs() { return BBs; }
+   };
+ 
+ 
+ 
+ 
+ 
+   // Provide specializations of GraphTraits to be able to use graph
+   // iterators on the scheduling graph
+   static MSchedGraphSBNode& getSecond(std::pair<const MachineInstr* const,
+ 				    MSchedGraphSBNode*> &Pair) {
+     return *Pair.second;
+   }
+ 
+   template <> struct GraphTraits<MSchedGraphSB*> {
+     typedef MSchedGraphSBNode NodeType;
+     typedef MSchedGraphSBNode::succ_iterator ChildIteratorType;
+ 
+     static inline ChildIteratorType child_begin(NodeType *N) {
+       return N->succ_begin();
+     }
+     static inline ChildIteratorType child_end(NodeType *N) {
+       return N->succ_end();
+     }
+ 
+     typedef std::pointer_to_unary_function<std::pair<const MachineInstr* const,
+            MSchedGraphSBNode*>&, MSchedGraphSBNode&> DerefFun;
+ 
+     typedef mapped_iterator<MSchedGraphSB::iterator, DerefFun> nodes_iterator;
+     static nodes_iterator nodes_begin(MSchedGraphSB *G) {
+       return map_iterator(((MSchedGraphSB*)G)->begin(), DerefFun(getSecond));
+     }
+     static nodes_iterator nodes_end(MSchedGraphSB *G) {
+       return map_iterator(((MSchedGraphSB*)G)->end(), DerefFun(getSecond));
+     }
+ 
+   };
+ 
+   template <> struct GraphTraits<const MSchedGraphSB*> {
+     typedef const MSchedGraphSBNode NodeType;
+     typedef MSchedGraphSBNode::succ_const_iterator ChildIteratorType;
+ 
+     static inline ChildIteratorType child_begin(NodeType *N) {
+       return N->succ_begin();
+     }
+     static inline ChildIteratorType child_end(NodeType *N) {
+       return N->succ_end();
+     }
+     typedef std::pointer_to_unary_function<std::pair<const MachineInstr* const,
+ 						     MSchedGraphSBNode*>&, MSchedGraphSBNode&> DerefFun;
+ 
+     typedef mapped_iterator<MSchedGraphSB::iterator, DerefFun> nodes_iterator;
+     static nodes_iterator nodes_begin(MSchedGraphSB *G) {
+       return map_iterator(((MSchedGraphSB*)G)->begin(), DerefFun(getSecond));
+     }
+     static nodes_iterator nodes_end(MSchedGraphSB *G) {
+       return map_iterator(((MSchedGraphSB*)G)->end(), DerefFun(getSecond));
+     }
+   };
+ 
+   template <> struct GraphTraits<Inverse<MSchedGraphSB*> > {
+     typedef MSchedGraphSBNode NodeType;
+     typedef MSchedGraphSBNode::pred_iterator ChildIteratorType;
+ 
+     static inline ChildIteratorType child_begin(NodeType *N) {
+       return N->pred_begin();
+     }
+     static inline ChildIteratorType child_end(NodeType *N) {
+       return N->pred_end();
+     }
+     typedef std::pointer_to_unary_function<std::pair<const MachineInstr* const,
+            MSchedGraphSBNode*>&, MSchedGraphSBNode&> DerefFun;
+ 
+     typedef mapped_iterator<MSchedGraphSB::iterator, DerefFun> nodes_iterator;
+     static nodes_iterator nodes_begin(MSchedGraphSB *G) {
+       return map_iterator(((MSchedGraphSB*)G)->begin(), DerefFun(getSecond));
+     }
+     static nodes_iterator nodes_end(MSchedGraphSB *G) {
+       return map_iterator(((MSchedGraphSB*)G)->end(), DerefFun(getSecond));
+     }
+   };
+ 
+   template <> struct GraphTraits<Inverse<const MSchedGraphSB*> > {
+     typedef const MSchedGraphSBNode NodeType;
+     typedef MSchedGraphSBNode::pred_const_iterator ChildIteratorType;
+ 
+     static inline ChildIteratorType child_begin(NodeType *N) {
+       return N->pred_begin();
+     }
+     static inline ChildIteratorType child_end(NodeType *N) {
+       return N->pred_end();
+     }
+ 
+     typedef std::pointer_to_unary_function<std::pair<const MachineInstr* const,
+ 						     MSchedGraphSBNode*>&, MSchedGraphSBNode&> DerefFun;
+ 
+     typedef mapped_iterator<MSchedGraphSB::iterator, DerefFun> nodes_iterator;
+     static nodes_iterator nodes_begin(MSchedGraphSB *G) {
+       return map_iterator(((MSchedGraphSB*)G)->begin(), DerefFun(getSecond));
+     }
+     static nodes_iterator nodes_end(MSchedGraphSB *G) {
+       return map_iterator(((MSchedGraphSB*)G)->end(), DerefFun(getSecond));
+     }
+   };
+ }
+ 
+ #endif





From tbrethou at cs.uiuc.edu  Thu Jun 16 23:21:20 2005
From: tbrethou at cs.uiuc.edu (Tanya Brethour)
Date: Thu, 16 Jun 2005 23:21:20 -0500
Subject: [llvm-commits] 
	CVS: llvm/lib/Target/SparcV9/ModuloScheduling/MSchedGraphSB.cpp
Message-ID: <200506170421.XAA31357@zion.cs.uiuc.edu>



Changes in directory llvm/lib/Target/SparcV9/ModuloScheduling:

MSchedGraphSB.cpp updated: 1.1 -> 1.2
---
Log message:

Removed IIIi specific changes. This should be fixed to add floating point deps for the IIi.


---
Diffs of the changes:  (+4 -2)

 MSchedGraphSB.cpp |    6 ++++--
 1 files changed, 4 insertions(+), 2 deletions(-)


Index: llvm/lib/Target/SparcV9/ModuloScheduling/MSchedGraphSB.cpp
diff -u llvm/lib/Target/SparcV9/ModuloScheduling/MSchedGraphSB.cpp:1.1 llvm/lib/Target/SparcV9/ModuloScheduling/MSchedGraphSB.cpp:1.2
--- llvm/lib/Target/SparcV9/ModuloScheduling/MSchedGraphSB.cpp:1.1	Thu Jun 16 23:15:43 2005
+++ llvm/lib/Target/SparcV9/ModuloScheduling/MSchedGraphSB.cpp	Thu Jun 16 23:21:09 2005
@@ -370,8 +370,10 @@
   //Check for any floating point operation
   const TargetSchedInfo *msi = Target.getSchedInfo();
   InstrSchedClass sc = msi->getSchedClass(opCode);
-  if(sc == SPARC_FGA || sc == SPARC_FGM)
-    return true;
+  
+  //FIXME: Should check for floating point instructions!
+  //if(sc == SPARC_FGA || sc == SPARC_FGM)
+  //return true;
 
   return false;
 }





From lattner at cs.uiuc.edu  Fri Jun 17 08:20:28 2005
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Fri, 17 Jun 2005 08:20:28 -0500
Subject: [llvm-commits] CVS: llvm/include/llvm/Support/CommandLine.h 
Message-ID: <200506171320.IAA09737@zion.cs.uiuc.edu>



Changes in directory llvm/include/llvm/Support:

CommandLine.h updated: 1.43 -> 1.44
---
Log message:

silence a huge number of bogus warnings with GCC 4 on Reid's tester.


---
Diffs of the changes:  (+2 -1)

 CommandLine.h |    3 ++-
 1 files changed, 2 insertions(+), 1 deletion(-)


Index: llvm/include/llvm/Support/CommandLine.h
diff -u llvm/include/llvm/Support/CommandLine.h:1.43 llvm/include/llvm/Support/CommandLine.h:1.44
--- llvm/include/llvm/Support/CommandLine.h:1.43	Thu Apr 21 21:31:56 2005
+++ llvm/include/llvm/Support/CommandLine.h	Fri Jun 17 08:20:15 2005
@@ -734,7 +734,8 @@
 
   virtual bool handleOccurrence(unsigned pos, const char *ArgName,
                                 const std::string &Arg) {
-    typename ParserClass::parser_data_type Val;
+    typename ParserClass::parser_data_type Val = 
+       typename ParserClass::parser_data_type();
     if (Parser.parse(*this, ArgName, Arg, Val))
       return true;                            // Parse error!
     setValue(Val);





From lattner at cs.uiuc.edu  Fri Jun 17 08:23:43 2005
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Fri, 17 Jun 2005 08:23:43 -0500
Subject: [llvm-commits] CVS: llvm/lib/Target/X86/X86ISelPattern.cpp 
Message-ID: <200506171323.IAA14036@zion.cs.uiuc.edu>



Changes in directory llvm/lib/Target/X86:

X86ISelPattern.cpp updated: 1.139 -> 1.140
---
Log message:

silence a bogus warning


---
Diffs of the changes:  (+1 -1)

 X86ISelPattern.cpp |    2 +-
 1 files changed, 1 insertion(+), 1 deletion(-)


Index: llvm/lib/Target/X86/X86ISelPattern.cpp
diff -u llvm/lib/Target/X86/X86ISelPattern.cpp:1.139 llvm/lib/Target/X86/X86ISelPattern.cpp:1.140
--- llvm/lib/Target/X86/X86ISelPattern.cpp:1.139	Thu May 19 00:54:33 2005
+++ llvm/lib/Target/X86/X86ISelPattern.cpp	Fri Jun 17 08:23:32 2005
@@ -3862,7 +3862,7 @@
   SDOperand Callee = TailCallNode->getOperand(1);
   bool isDirect = isa<GlobalAddressSDNode>(Callee) ||
                   isa<ExternalSymbolSDNode>(Callee);
-  unsigned CalleeReg;
+  unsigned CalleeReg = 0;
   if (!isDirect) CalleeReg = SelectExpr(Callee);
 
   unsigned RegOp1 = 0;





From lattner at cs.uiuc.edu  Fri Jun 17 08:44:19 2005
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Fri, 17 Jun 2005 08:44:19 -0500
Subject: [llvm-commits] 
	CVS: llvm/lib/Target/PowerPC/PowerPCBranchSelector.cpp
Message-ID: <200506171344.IAA14777@zion.cs.uiuc.edu>



Changes in directory llvm/lib/Target/PowerPC:

PowerPCBranchSelector.cpp updated: 1.9 -> 1.10
---
Log message:

silence incredibly braindead GCC 4 warning


---
Diffs of the changes:  (+0 -2)

 PowerPCBranchSelector.cpp |    2 --
 1 files changed, 2 deletions(-)


Index: llvm/lib/Target/PowerPC/PowerPCBranchSelector.cpp
diff -u llvm/lib/Target/PowerPC/PowerPCBranchSelector.cpp:1.9 llvm/lib/Target/PowerPC/PowerPCBranchSelector.cpp:1.10
--- llvm/lib/Target/PowerPC/PowerPCBranchSelector.cpp:1.9	Sun Jun 12 18:50:33 2005
+++ llvm/lib/Target/PowerPC/PowerPCBranchSelector.cpp	Fri Jun 17 08:44:07 2005
@@ -42,10 +42,8 @@
         return 12;
       case PPC::IMPLICIT_DEF: // no asm emitted
         return 0;
-        break;
       default:
         return 4; // PowerPC instructions are all 4 bytes
-        break;
       }
     }
 





From reid at x10sys.com  Fri Jun 17 10:21:36 2005
From: reid at x10sys.com (Reid Spencer)
Date: Fri, 17 Jun 2005 08:21:36 -0700
Subject: [llvm-commits] CVS: llvm/include/llvm/Support/CommandLine.h
In-Reply-To: <200506171320.IAA09737@zion.cs.uiuc.edu>
References: <200506171320.IAA09737@zion.cs.uiuc.edu>
Message-ID: <1119021696.16576.75.camel@bashful.x10sys.com>

On Fri, 2005-06-17 at 08:20 -0500, Chris Lattner wrote:
> 

> silence a huge number of bogus warnings with GCC 4 on Reid's tester.
> 
> diff -u llvm/include/llvm/Support/CommandLine.h:1.43 llvm/include/llvm/Support/CommandLine.h:1.44
> -    typename ParserClass::parser_data_type Val;
> +    typename ParserClass::parser_data_type Val = 
> +       typename ParserClass::parser_data_type();

I tried this a while back. I think this runs into some issues when
parser_data_type isn't constructible. I've tried various initializations
but there doesn't seem to be a consistent one that works with all
parser_data_type types.  Did all of LLVM recompile correctly with this
change?

Reid.
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From sabre at nondot.org  Fri Jun 17 11:24:33 2005
From: sabre at nondot.org (Chris Lattner)
Date: Fri, 17 Jun 2005 11:24:33 -0500 (CDT)
Subject: [llvm-commits] CVS: llvm/include/llvm/Support/CommandLine.h
In-Reply-To: <1119021696.16576.75.camel@bashful.x10sys.com>
References: <200506171320.IAA09737@zion.cs.uiuc.edu>
	<1119021696.16576.75.camel@bashful.x10sys.com>
Message-ID: <Pine.LNX.4.61.0506171124230.23248@nondot.org>

On Fri, 17 Jun 2005, Reid Spencer wrote:
>> silence a huge number of bogus warnings with GCC 4 on Reid's tester.
>>
>> diff -u llvm/include/llvm/Support/CommandLine.h:1.43 llvm/include/llvm/Support/CommandLine.h:1.44
>> -    typename ParserClass::parser_data_type Val;
>> +    typename ParserClass::parser_data_type Val =
>> +       typename ParserClass::parser_data_type();
>
> I tried this a while back. I think this runs into some issues when
> parser_data_type isn't constructible. I've tried various initializations
> but there doesn't seem to be a consistent one that works with all
> parser_data_type types.  Did all of LLVM recompile correctly with this
> change?

Yes, it does with gcc 3.4

-Chris

-- 
http://nondot.org/sabre/
http://llvm.cs.uiuc.edu/



From alenhar2 at cs.uiuc.edu  Fri Jun 17 11:52:23 2005
From: alenhar2 at cs.uiuc.edu (Andrew Lenharth)
Date: Fri, 17 Jun 2005 11:52:23 -0500
Subject: [llvm-commits] CVS: llvm/lib/Target/SparcV8/SparcV8ISelPattern.cpp 
Message-ID: <200506171652.LAA16088@zion.cs.uiuc.edu>



Changes in directory llvm/lib/Target/SparcV8:

SparcV8ISelPattern.cpp added (r1.1)
---
Log message:

A start at a Sparc V8 Pattern ISel.  Anyone want to implement the calling
convention? ;)




---
Diffs of the changes:  (+479 -0)

 SparcV8ISelPattern.cpp |  479 +++++++++++++++++++++++++++++++++++++++++++++++++
 1 files changed, 479 insertions(+)


Index: llvm/lib/Target/SparcV8/SparcV8ISelPattern.cpp
diff -c /dev/null llvm/lib/Target/SparcV8/SparcV8ISelPattern.cpp:1.1
*** /dev/null	Fri Jun 17 11:52:22 2005
--- llvm/lib/Target/SparcV8/SparcV8ISelPattern.cpp	Fri Jun 17 11:52:12 2005
***************
*** 0 ****
--- 1,479 ----
+ #if 0
+ //===- SparcV8ISelPattern.cpp - A pattern matching isel for SparcV8 -------===//
+ //
+ //                     The LLVM Compiler Infrastructure
+ //
+ // This file was developed by the LLVM research group and is distributed under
+ // the University of Illinois Open Source License. See LICENSE.TXT for details.
+ //
+ //===----------------------------------------------------------------------===//
+ //
+ // This file defines a pattern matching instruction selector for SparcV8.
+ //
+ //===----------------------------------------------------------------------===//
+ 
+ //Please note that this file is a work in progress, and not a high
+ //priority for anyone.
+ 
+ #include "SparcV8.h"
+ #include "SparcV8RegisterInfo.h"
+ #include "llvm/Constants.h"                   // FIXME: REMOVE
+ #include "llvm/Function.h"
+ #include "llvm/CodeGen/MachineInstrBuilder.h"
+ #include "llvm/CodeGen/MachineConstantPool.h" // FIXME: REMOVE
+ #include "llvm/CodeGen/MachineFunction.h"
+ #include "llvm/CodeGen/MachineFrameInfo.h"
+ #include "llvm/CodeGen/SelectionDAG.h"
+ #include "llvm/CodeGen/SelectionDAGISel.h"
+ #include "llvm/CodeGen/SSARegMap.h"
+ #include "llvm/Target/TargetData.h"
+ #include "llvm/Target/TargetLowering.h"
+ #include "llvm/Support/MathExtras.h"
+ #include "llvm/ADT/Statistic.h"
+ #include "llvm/Support/Debug.h"
+ #include "llvm/Support/CommandLine.h"
+ #include <set>
+ #include <algorithm>
+ using namespace llvm;
+ 
+ //===----------------------------------------------------------------------===//
+ //  V8TargetLowering - SparcV8 Implementation of the TargetLowering interface
+ namespace {
+   class V8TargetLowering : public TargetLowering {
+     int VarArgsFrameIndex;            // FrameIndex for start of varargs area.
+   public:
+     V8TargetLowering(TargetMachine &TM) : TargetLowering(TM) {
+       // Set up the TargetLowering object.
+       //I am having problems with shr n ubyte 1
+       setShiftAmountType(MVT::i32);
+       setSetCCResultType(MVT::i32);
+       setSetCCResultContents(ZeroOrOneSetCCResult);
+ 
+       //FIXME: get these right
+       addRegisterClass(MVT::i64, V8::GPRCRegisterClass);
+       addRegisterClass(MVT::f64, V8::FPRCRegisterClass);
+       addRegisterClass(MVT::f32, V8::FPRCRegisterClass);
+ 
+       setOperationAction(ISD::BRCONDTWOWAY, MVT::Other, Expand);
+       setOperationAction(ISD::EXTLOAD, MVT::i1,  Promote);
+       setOperationAction(ISD::EXTLOAD, MVT::f32, Promote);
+ 
+       setOperationAction(ISD::ZEXTLOAD, MVT::i1, Expand);
+       setOperationAction(ISD::SEXTLOAD, MVT::i1, Expand);
+ 
+       setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1,  Expand);
+       setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8,  Expand);
+       setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand);
+       setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i32, Expand);
+ 
+       setOperationAction(ISD::UREM, MVT::i32, Expand);
+       setOperationAction(ISD::SREM, MVT::i32, Expand);
+ 
+       setOperationAction(ISD::CTPOP, MVT::i32, Expand);
+       setOperationAction(ISD::CTTZ, MVT::i32, Expand);
+       setOperationAction(ISD::CTLZ, MVT::i32, Expand);
+ 
+       setOperationAction(ISD::MEMMOVE, MVT::Other, Expand);
+       setOperationAction(ISD::MEMSET,  MVT::Other, Expand);
+       setOperationAction(ISD::MEMCPY,  MVT::Other, Expand);
+ 
+       // We don't support sin/cos/sqrt
+       setOperationAction(ISD::FSIN , MVT::f64, Expand);
+       setOperationAction(ISD::FCOS , MVT::f64, Expand);
+       setOperationAction(ISD::FSQRT, MVT::f64, Expand);
+       setOperationAction(ISD::FSIN , MVT::f32, Expand);
+       setOperationAction(ISD::FCOS , MVT::f32, Expand);
+       setOperationAction(ISD::FSQRT, MVT::f32, Expand);
+ 
+       computeRegisterProperties();
+ 
+       addLegalFPImmediate(+0.0); //F31
+       addLegalFPImmediate(-0.0); //-F31
+     }
+ 
+     /// LowerArguments - This hook must be implemented to indicate how we should
+     /// lower the arguments for the specified function, into the specified DAG.
+     virtual std::vector<SDOperand>
+     LowerArguments(Function &F, SelectionDAG &DAG);
+ 
+     /// LowerCallTo - This hook lowers an abstract call to a function into an
+     /// actual call.
+     virtual std::pair<SDOperand, SDOperand>
+     LowerCallTo(SDOperand Chain, const Type *RetTy, bool isVarArg, unsigned CC,
+                 bool isTailCall, SDOperand Callee, ArgListTy &Args,
+                 SelectionDAG &DAG);
+   };
+ }
+ 
+ /// AddLiveIn - This helper function adds the specified physical register to the
+ /// MachineFunction as a live in value.  It also creates a corresponding virtual
+ /// register for it.
+ static unsigned AddLiveIn(MachineFunction &MF, unsigned PReg,
+                           TargetRegisterClass *RC) {
+   assert(RC->contains(PReg) && "Not the correct regclass!");
+   unsigned VReg = MF.getSSARegMap()->createVirtualRegister(RC);
+   MF.addLiveIn(PReg, VReg);
+   return VReg;
+ }
+ 
+ std::vector<SDOperand>
+ V8TargetLowering::LowerArguments(Function &F, SelectionDAG &DAG)
+ {
+   //FIXME
+   std::vector<SDOperand> ArgValues;
+ 
+   MachineFunction &MF = DAG.getMachineFunction();
+   MachineFrameInfo*MFI = MF.getFrameInfo();
+ 
+   MachineBasicBlock& BB = MF.front();
+ 
+   //return the arguments
+   return ArgValues;
+ }
+ 
+ std::pair<SDOperand, SDOperand>
+ V8TargetLowering::LowerCallTo(SDOperand Chain,
+                                  const Type *RetTy, bool isVarArg,
+                                  unsigned CallingConv, bool isTailCall,
+                                  SDOperand Callee, ArgListTy &Args, 
+                                  SelectionDAG &DAG) {
+   //FIXME
+   return std::make_pair(Chain, Chain);
+ }
+ 
+ namespace {
+ 
+ //===--------------------------------------------------------------------===//
+ /// ISel - V8 specific code to select V8 machine instructions for
+ /// SelectionDAG operations.
+ //===--------------------------------------------------------------------===//
+ class ISel : public SelectionDAGISel {
+ 
+   /// V8Lowering - This object fully describes how to lower LLVM code to an
+   /// V8-specific SelectionDAG.
+   V8TargetLowering V8Lowering;
+ 
+   SelectionDAG *ISelDAG;  // Hack to support us having a dag->dag transform
+                           // for sdiv and udiv until it is put into the future
+                           // dag combiner.
+ 
+   /// ExprMap - As shared expressions are codegen'd, we keep track of which
+   /// vreg the value is produced in, so we only emit one copy of each compiled
+   /// tree.
+   static const unsigned notIn = (unsigned)(-1);
+   std::map<SDOperand, unsigned> ExprMap;
+ 
+ public:
+   ISel(TargetMachine &TM) : SelectionDAGISel(V8Lowering), V8Lowering(TM)
+   {}
+ 
+   /// InstructionSelectBasicBlock - This callback is invoked by
+   /// SelectionDAGISel when it has created a SelectionDAG for us to codegen.
+   virtual void InstructionSelectBasicBlock(SelectionDAG &DAG) {
+     DEBUG(BB->dump());
+ 
+     // Codegen the basic block.
+     ISelDAG = &DAG;
+     max_depth = DAG.getRoot().getNodeDepth();
+     Select(DAG.getRoot());
+ 
+     // Clear state used for selection.
+     ExprMap.clear();
+   }
+   
+   virtual void EmitFunctionEntryCode(Function &Fn, MachineFunction &MF);
+ 
+   unsigned SelectExpr(SDOperand N);
+   void Select(SDOperand N);
+ 
+ };
+ }
+ 
+ void ISel::EmitFunctionEntryCode(Function &Fn, MachineFunction &MF) {
+   // If this function has live-in values, emit the copies from pregs to vregs at
+   // the top of the function, before anything else.
+   MachineBasicBlock *BB = MF.begin();
+   if (MF.livein_begin() != MF.livein_end()) {
+     SSARegMap *RegMap = MF.getSSARegMap();
+     for (MachineFunction::livein_iterator LI = MF.livein_begin(),
+            E = MF.livein_end(); LI != E; ++LI) {
+       const TargetRegisterClass *RC = RegMap->getRegClass(LI->second);
+       if (RC == V8::GPRCRegisterClass) {
+         BuildMI(BB, V8::ORrr, 2, LI->second).addReg(LI->first).addReg(V8::G0);
+       } else if (RC == V8::FPRCRegisterClass) {
+         BuildMI(BB, V8::FMOVSrr, 2, LI->second).addReg(LI->first);
+       } else {
+         assert(0 && "Unknown regclass!");
+       }
+     }
+   }
+ }
+ 
+ //These describe LDAx
+ static const int IMM_LOW  = -32768;
+ static const int IMM_HIGH = 32767;
+ static const int IMM_MULT = 65536;
+ 
+ static long getUpper16(long l)
+ {
+   long y = l / IMM_MULT;
+   if (l % IMM_MULT > IMM_HIGH)
+     ++y;
+   return y;
+ }
+ 
+ static long getLower16(long l)
+ {
+   long h = getUpper16(l);
+   return l - h * IMM_MULT;
+ }
+ 
+ unsigned ISel::SelectExpr(SDOperand N) {
+   unsigned Result;
+   unsigned Tmp1, Tmp2 = 0, Tmp3;
+   unsigned Opc = 0;
+   unsigned opcode = N.getOpcode();
+ 
+   SDNode *Node = N.Val;
+   MVT::ValueType DestType = N.getValueType();
+ 
+   unsigned &Reg = ExprMap[N];
+   if (Reg) return Reg;
+ 
+   if (N.getOpcode() != ISD::CALL && N.getOpcode() != ISD::TAILCALL)
+     Reg = Result = (N.getValueType() != MVT::Other) ?
+       MakeReg(N.getValueType()) : notIn;
+   else {
+     // If this is a call instruction, make sure to prepare ALL of the result
+     // values as well as the chain.
+     if (Node->getNumValues() == 1)
+       Reg = Result = notIn;  // Void call, just a chain.
+     else {
+       Result = MakeReg(Node->getValueType(0));
+       ExprMap[N.getValue(0)] = Result;
+       for (unsigned i = 1, e = N.Val->getNumValues()-1; i != e; ++i)
+         ExprMap[N.getValue(i)] = MakeReg(Node->getValueType(i));
+       ExprMap[SDOperand(Node, Node->getNumValues()-1)] = notIn;
+     }
+   }
+ 
+   switch (opcode) {
+   default:
+     Node->dump();
+     assert(0 && "Node not handled!\n");
+ 
+   case ISD::EXTLOAD:
+   case ISD::ZEXTLOAD:
+   case ISD::SEXTLOAD:
+   case ISD::LOAD:
+     {
+       // Make sure we generate both values.
+       if (Result != notIn)
+         ExprMap[N.getValue(1)] = notIn;   // Generate the token
+       else
+         Result = ExprMap[N.getValue(0)] = MakeReg(N.getValue(0).getValueType());
+ 
+       SDOperand Chain   = N.getOperand(0);
+       SDOperand Address = N.getOperand(1);
+       Select(Chain);
+       unsigned Adr = SelectExpr(Address);
+       switch(cast<MVTSDNode>(Node)->getExtraValueType()) {
+       case MVT::i32: Opc = V8::LD;
+       case MVT::i16: Opc = opcode == ISD::ZEXTLOAD ? V8::LDUH : V8::LDSH; break;
+       case MVT::i8:  Opc = opcode == ISD::ZEXTLOAD ? V8::LDUB : V8::LDSB; break;
+       case MVT::f64: Opc = V8::LDFSRrr;
+       case MVT::f32: Opc = V8::LDDFrr;
+       default:
+         Node->dump(); 
+         assert(0 && "Bad type!");
+         break;
+       }
+       BuildMI(BB, Opc, 1, Result).addReg(Adr);
+       return Result;
+     }
+ 
+   case ISD::TAILCALL:
+   case ISD::CALL:
+     {
+       //FIXME:
+       abort();
+       return Result;
+     }
+ 
+   case ISD::CopyFromReg:
+     {
+       // Make sure we generate both values.
+       if (Result != notIn)
+         ExprMap[N.getValue(1)] = notIn;   // Generate the token
+       else
+         Result = ExprMap[N.getValue(0)] = MakeReg(N.getValue(0).getValueType());
+ 
+       SDOperand Chain   = N.getOperand(0);
+       Select(Chain);
+       unsigned r = dyn_cast<RegSDNode>(Node)->getReg();
+       
+       BuildMI(BB, V8::ORrr, 2, Result).addReg(r).addReg(V8::G0);
+       return Result;
+     }
+ 
+     //Most of the plain arithmetic and logic share the same form, and the same
+     //constant immediate test
+   case ISD::XOR:
+   case ISD::AND:
+   case ISD::OR:
+   case ISD::SHL:
+   case ISD::SRL:
+   case ISD::SRA:
+   case ISD::ADD:
+   case ISD::SUB:
+   case ISD::SDIV:
+   case ISD::UDIV:
+   case ISD::SMUL:
+   case ISD::UMUL:
+     switch(opcode) {
+     case ISD::XOR:  Opc = V8::XORrr; break;
+     case ISD::AND:  Opc = V8::ANDrr; break;
+     case ISD::OR:   Opc = V8::ORrr; break;
+     case ISD::SHL:  Opc = V8::SLLrr; break;
+     case ISD::SRL:  Opc = V8::SRLrr; break;
+     case ISD::SRA:  Opc = V8::SRArr; break;
+     case ISD::ADD:  Opc = V8::ADDrr; break;
+     case ISD::SUB:  Opc = V8::SUBrr; break;
+     case ISD::SDIV: Opc = V8::SDIVrr; break;
+     case ISD::UDIV: Opc = V8::UDIVrr; break;
+     case ISD::SMUL: Opc = V8::SMULrr; break;
+     case ISD::UMUL: Opc = V8::UMULrr; break;
+     }
+     Tmp1 = SelectExpr(N.getOperand(0));
+     Tmp2 = SelectExpr(N.getOperand(1));
+     BuildMI(BB, Opc, 2, Result).addReg(Tmp1).addReg(Tmp2);
+     return Result;
+    
+   }
+   return 0;
+ }
+ 
+ void ISel::Select(SDOperand N) {
+   unsigned Tmp1, Tmp2, Opc;
+   unsigned opcode = N.getOpcode();
+ 
+   if (!ExprMap.insert(std::make_pair(N, notIn)).second)
+     return;  // Already selected.
+ 
+   SDNode *Node = N.Val;
+ 
+   switch (opcode) {
+ 
+   default:
+     Node->dump(); std::cerr << "\n";
+     assert(0 && "Node not handled yet!");
+ 
+   case ISD::BRCOND: {
+     //FIXME
+     abort();
+     return;
+   }
+ 
+   case ISD::BR: {
+     MachineBasicBlock *Dest =
+       cast<BasicBlockSDNode>(N.getOperand(1))->getBasicBlock();
+ 
+     Select(N.getOperand(0));
+     BuildMI(BB, V8::BA, 1).addMBB(Dest);
+     return;
+   }
+ 
+   case ISD::ImplicitDef:
+     Select(N.getOperand(0));
+     BuildMI(BB, V8::IMPLICIT_DEF, 0, cast<RegSDNode>(N)->getReg());
+     return;
+ 
+   case ISD::EntryToken: return;  // Noop
+ 
+   case ISD::TokenFactor:
+     for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i)
+       Select(Node->getOperand(i));
+     return;
+ 
+   case ISD::CopyToReg:
+     Select(N.getOperand(0));
+     Tmp1 = SelectExpr(N.getOperand(1));
+     Tmp2 = cast<RegSDNode>(N)->getReg();
+ 
+     if (Tmp1 != Tmp2) {
+       if (N.getOperand(1).getValueType() == MVT::f64 ||
+           N.getOperand(1).getValueType() == MVT::f32)
+         BuildMI(BB, V8::FMOVS, 2, Tmp2).addReg(Tmp1);
+       else
+         BuildMI(BB, V8::ORrr, 2, Tmp2).addReg(Tmp1).addReg(V8::G0);
+     }
+     return;
+ 
+   case ISD::RET:
+     //FIXME:
+     abort();
+     return;
+ 
+   case ISD::TRUNCSTORE:
+   case ISD::STORE:
+     {
+       SDOperand Chain   = N.getOperand(0);
+       SDOperand Value = N.getOperand(1);
+       SDOperand Address = N.getOperand(2);
+       Select(Chain);
+ 
+       Tmp1 = SelectExpr(Value);
+       Tmp2 = SelectExpr(Address);
+ 
+       unsigned VT = opcode == ISD::STORE ? 
+         Value.getValueType() : cast<MVTSDNode>(Node)->getExtraValueType();
+       switch(VT) {
+       default: assert(0 && "unknown Type in store");
+       case MVT::f64: Opc = V8::STDFrr; break;
+       case MVT::f32: Opc = V8::STFrr; break;
+       case MVT::i1:  //FIXME: DAG does not promote this load
+       case MVT::i8:  Opc = V8::STBrr; break;
+       case MVT::i16: Opc = V8::STHrr; break;
+       case MVT::i32: Opc = V8::STLrr; break;
+       case MVT::i64: Opc = V8::STDrr; break;
+       }
+ 
+       BuildMI(BB,Opc,2).addReg(Tmp1).addReg(Tmp2);
+       return;
+     }
+ 
+   case ISD::EXTLOAD:
+   case ISD::SEXTLOAD:
+   case ISD::ZEXTLOAD:
+   case ISD::LOAD:
+   case ISD::CopyFromReg:
+   case ISD::TAILCALL:
+   case ISD::CALL:
+   case ISD::DYNAMIC_STACKALLOC:
+     ExprMap.erase(N);
+     SelectExpr(N);
+     return;
+ 
+   case ISD::CALLSEQ_START:
+   case ISD::CALLSEQ_END:
+     Select(N.getOperand(0));
+     Tmp1 = cast<ConstantSDNode>(N.getOperand(1))->getValue();
+ 
+     Opc = N.getOpcode() == ISD::CALLSEQ_START ? V8::ADJUSTCALLSTACKDOWN :
+       V8::ADJUSTCALLSTACKUP;
+     BuildMI(BB, Opc, 1).addImm(Tmp1);
+     return;
+   }
+   assert(0 && "Should not be reached!");
+ }
+ 
+ 
+ /// createV8PatternInstructionSelector - This pass converts an LLVM function
+ /// into a machine code representation using pattern matching and a machine
+ /// description file.
+ ///
+ FunctionPass *llvm::createV8PatternInstructionSelector(TargetMachine &TM) {
+   return new ISel(TM);
+ }
+ 
+ #endif





From reid at x10sys.com  Fri Jun 17 12:31:14 2005
From: reid at x10sys.com (Reid Spencer)
Date: Fri, 17 Jun 2005 10:31:14 -0700
Subject: [llvm-commits] CVS: llvm/include/llvm/Support/CommandLine.h
In-Reply-To: <Pine.LNX.4.61.0506171124230.23248@nondot.org>
References: <200506171320.IAA09737@zion.cs.uiuc.edu>
	<1119021696.16576.75.camel@bashful.x10sys.com>
	<Pine.LNX.4.61.0506171124230.23248@nondot.org>
Message-ID: <1119029474.16576.77.camel@bashful.x10sys.com>

On Fri, 2005-06-17 at 11:24 -0500, Chris Lattner wrote:
> On Fri, 17 Jun 2005, Reid Spencer wrote:
> >> silence a huge number of bogus warnings with GCC 4 on Reid's tester.
> >>
> >> diff -u llvm/include/llvm/Support/CommandLine.h:1.43 llvm/include/llvm/Support/CommandLine.h:1.44
> >> -    typename ParserClass::parser_data_type Val;
> >> +    typename ParserClass::parser_data_type Val =
> >> +       typename ParserClass::parser_data_type();
> >
> > I tried this a while back. I think this runs into some issues when
> > parser_data_type isn't constructible. I've tried various initializations
> > but there doesn't seem to be a consistent one that works with all
> > parser_data_type types.  Did all of LLVM recompile correctly with this
> > change?
> 
> Yes, it does with gcc 3.4

Okay, seems to work with 4.0.0 too. Not sure what I tried to do
previously but a similar patch didn't (previously) work with 4.0.0. Glad
this annoying warning is out of the way. Thanks for taking care of it!

Reid
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From reid at x10sys.com  Sat Jun 18 11:53:38 2005
From: reid at x10sys.com (Reid Spencer)
Date: Sat, 18 Jun 2005 11:53:38 -0500
Subject: [llvm-commits] CVS: llvm/include/llvm/Support/CommandLine.h 
Message-ID: <200506181653.LAA24941@zion.cs.uiuc.edu>



Changes in directory llvm/include/llvm/Support:

CommandLine.h updated: 1.44 -> 1.45
---
Log message:

Make sure a variable is initialized before use to clean up a warning from
GCC 4.0.0 in release build.


---
Diffs of the changes:  (+2 -1)

 CommandLine.h |    3 ++-
 1 files changed, 2 insertions(+), 1 deletion(-)


Index: llvm/include/llvm/Support/CommandLine.h
diff -u llvm/include/llvm/Support/CommandLine.h:1.44 llvm/include/llvm/Support/CommandLine.h:1.45
--- llvm/include/llvm/Support/CommandLine.h:1.44	Fri Jun 17 08:20:15 2005
+++ llvm/include/llvm/Support/CommandLine.h	Sat Jun 18 11:53:27 2005
@@ -894,7 +894,8 @@
 
   virtual bool handleOccurrence(unsigned pos, const char *ArgName,
                                 const std::string &Arg) {
-    typename ParserClass::parser_data_type Val;
+    typename ParserClass::parser_data_type Val =
+      typename ParserClass::parser_data_type();
     if (Parser.parse(*this, ArgName, Arg, Val))
       return true;  // Parse Error!
     addValue(Val);





From reid at x10sys.com  Sat Jun 18 12:37:46 2005
From: reid at x10sys.com (Reid Spencer)
Date: Sat, 18 Jun 2005 12:37:46 -0500
Subject: [llvm-commits] 
	CVS: llvm/lib/Target/PowerPC/PowerPCBranchSelector.cpp
Message-ID: <200506181737.MAA25117@zion.cs.uiuc.edu>



Changes in directory llvm/lib/Target/PowerPC:

PowerPCBranchSelector.cpp updated: 1.10 -> 1.11
---
Log message:

Clean up some uninitialized variables and missing return statements that
GCC 4.0.0 compiler (sometimes incorrectly) warns about under release build.


---
Diffs of the changes:  (+2 -1)

 PowerPCBranchSelector.cpp |    3 ++-
 1 files changed, 2 insertions(+), 1 deletion(-)


Index: llvm/lib/Target/PowerPC/PowerPCBranchSelector.cpp
diff -u llvm/lib/Target/PowerPC/PowerPCBranchSelector.cpp:1.10 llvm/lib/Target/PowerPC/PowerPCBranchSelector.cpp:1.11
--- llvm/lib/Target/PowerPC/PowerPCBranchSelector.cpp:1.10	Fri Jun 17 08:44:07 2005
+++ llvm/lib/Target/PowerPC/PowerPCBranchSelector.cpp	Sat Jun 18 12:37:34 2005
@@ -43,8 +43,9 @@
       case PPC::IMPLICIT_DEF: // no asm emitted
         return 0;
       default:
-        return 4; // PowerPC instructions are all 4 bytes
+        break;
       }
+      return 4; // PowerPC instructions are all 4 bytes
     }
 
     virtual bool runOnMachineFunction(MachineFunction &Fn) {





From reid at x10sys.com  Sat Jun 18 12:37:46 2005
From: reid at x10sys.com (Reid Spencer)
Date: Sat, 18 Jun 2005 12:37:46 -0500
Subject: [llvm-commits] CVS: llvm/lib/Target/SparcV9/SparcV9BurgISel.cpp
	SparcV9CodeEmitter.cpp 
Message-ID: <200506181737.MAA25123@zion.cs.uiuc.edu>



Changes in directory llvm/lib/Target/SparcV9:

SparcV9BurgISel.cpp updated: 1.18 -> 1.19
SparcV9CodeEmitter.cpp updated: 1.80 -> 1.81
---
Log message:

Clean up some uninitialized variables and missing return statements that
GCC 4.0.0 compiler (sometimes incorrectly) warns about under release build.


---
Diffs of the changes:  (+3 -2)

 SparcV9BurgISel.cpp    |    3 ++-
 SparcV9CodeEmitter.cpp |    2 +-
 2 files changed, 3 insertions(+), 2 deletions(-)


Index: llvm/lib/Target/SparcV9/SparcV9BurgISel.cpp
diff -u llvm/lib/Target/SparcV9/SparcV9BurgISel.cpp:1.18 llvm/lib/Target/SparcV9/SparcV9BurgISel.cpp:1.19
--- llvm/lib/Target/SparcV9/SparcV9BurgISel.cpp:1.18	Wed May 11 16:45:03 2005
+++ llvm/lib/Target/SparcV9/SparcV9BurgISel.cpp	Sat Jun 18 12:37:34 2005
@@ -2915,8 +2915,9 @@
       return true; break;
 
     default:
-      return false; break;
+      break;
     }
+  return false; 
 }
 
 /// GetInstructionsByRule - Choose machine instructions for the


Index: llvm/lib/Target/SparcV9/SparcV9CodeEmitter.cpp
diff -u llvm/lib/Target/SparcV9/SparcV9CodeEmitter.cpp:1.80 llvm/lib/Target/SparcV9/SparcV9CodeEmitter.cpp:1.81
--- llvm/lib/Target/SparcV9/SparcV9CodeEmitter.cpp:1.80	Thu Apr 21 18:25:42 2005
+++ llvm/lib/Target/SparcV9/SparcV9CodeEmitter.cpp	Sat Jun 18 12:37:34 2005
@@ -56,7 +56,7 @@
 SparcV9CodeEmitter::getRealRegNum(unsigned fakeReg,
                                   MachineInstr &MI) {
   const SparcV9RegInfo &RI = *TM.getRegInfo();
-  unsigned regClass, regType = RI.getRegType(fakeReg);
+  unsigned regClass = 0, regType = RI.getRegType(fakeReg);
   // At least map fakeReg into its class
   fakeReg = RI.getClassRegNum(fakeReg, regClass);
 





From reid at x10sys.com  Sat Jun 18 12:37:46 2005
From: reid at x10sys.com (Reid Spencer)
Date: Sat, 18 Jun 2005 12:37:46 -0500
Subject: [llvm-commits] 
	CVS: llvm/lib/Transforms/Scalar/InstructionCombining.cpp
Message-ID: <200506181737.MAA25127@zion.cs.uiuc.edu>



Changes in directory llvm/lib/Transforms/Scalar:

InstructionCombining.cpp updated: 1.355 -> 1.356
---
Log message:

Clean up some uninitialized variables and missing return statements that
GCC 4.0.0 compiler (sometimes incorrectly) warns about under release build.


---
Diffs of the changes:  (+3 -3)

 InstructionCombining.cpp |    6 +++---
 1 files changed, 3 insertions(+), 3 deletions(-)


Index: llvm/lib/Transforms/Scalar/InstructionCombining.cpp
diff -u llvm/lib/Transforms/Scalar/InstructionCombining.cpp:1.355 llvm/lib/Transforms/Scalar/InstructionCombining.cpp:1.356
--- llvm/lib/Transforms/Scalar/InstructionCombining.cpp:1.355	Thu Jun 16 22:59:17 2005
+++ llvm/lib/Transforms/Scalar/InstructionCombining.cpp	Sat Jun 18 12:37:34 2005
@@ -757,7 +757,7 @@
       return BinaryOperator::createNot(Op1);
 
     // C - ~X == X + (1+C)
-    Value *X;
+    Value *X = 0;
     if (match(Op1, m_Not(m_Value(X))))
       return BinaryOperator::createAdd(X,
                     ConstantExpr::getAdd(C, ConstantInt::get(I.getType(), 1)));
@@ -852,7 +852,7 @@
                                                ConstantExpr::getNeg(DivRHS));
 
       // X - X*C --> X * (1-C)
-      ConstantInt *C2;
+      ConstantInt *C2 = 0;
       if (dyn_castFoldableMul(Op1I, C2) == Op0) {
         Constant *CP1 =
           ConstantExpr::getSub(ConstantInt::get(I.getType(), 1), C2);
@@ -5129,7 +5129,7 @@
 
 Instruction *InstCombiner::visitBranchInst(BranchInst &BI) {
   // Change br (not X), label True, label False to: br X, label False, True
-  Value *X;
+  Value *X = 0;
   BasicBlock *TrueDest;
   BasicBlock *FalseDest;
   if (match(&BI, m_Br(m_Not(m_Value(X)), TrueDest, FalseDest)) &&





From reid at x10sys.com  Sat Jun 18 12:46:40 2005
From: reid at x10sys.com (Reid Spencer)
Date: Sat, 18 Jun 2005 12:46:40 -0500
Subject: [llvm-commits] CVS: llvm/lib/Transforms/IPO/SimplifyLibCalls.cpp 
Message-ID: <200506181746.MAA25612@zion.cs.uiuc.edu>



Changes in directory llvm/lib/Transforms/IPO:

SimplifyLibCalls.cpp updated: 1.42 -> 1.43
---
Log message:

Fix a problem with the strcmp optimization checking the wrong string and
not casting to the correct type. 


---
Diffs of the changes:  (+16 -13)

 SimplifyLibCalls.cpp |   29 ++++++++++++++++-------------
 1 files changed, 16 insertions(+), 13 deletions(-)


Index: llvm/lib/Transforms/IPO/SimplifyLibCalls.cpp
diff -u llvm/lib/Transforms/IPO/SimplifyLibCalls.cpp:1.42 llvm/lib/Transforms/IPO/SimplifyLibCalls.cpp:1.43
--- llvm/lib/Transforms/IPO/SimplifyLibCalls.cpp:1.42	Fri May 20 20:27:04 2005
+++ llvm/lib/Transforms/IPO/SimplifyLibCalls.cpp	Sat Jun 18 12:46:28 2005
@@ -367,8 +367,9 @@
 // auto registers it into the "optlist" global above. 
 namespace {
 
-// Forward declare a utility function.
+// Forward declare utility functions.
 bool getConstantStringLength(Value* V, uint64_t& len, ConstantArray** A = 0 );
+Value *CastToCStr(Value *V, Instruction &IP);
 
 /// This LibCallOptimization will find instances of a call to "exit" that occurs
 /// within the "main" function and change it to a simple "ret" instruction with
@@ -663,7 +664,8 @@
       if (len_1 == 0)
       {
         // strcmp("",x) -> *x
-        LoadInst* load = new LoadInst(s1,ci->getName()+".load",ci);
+        LoadInst* load = 
+          new LoadInst(CastToCStr(s2,*ci), ci->getName()+".load",ci);
         CastInst* cast = 
           new CastInst(load,Type::IntTy,ci->getName()+".int",ci);
         ci->replaceAllUsesWith(cast);
@@ -681,7 +683,8 @@
       if (len_2 == 0)
       {
         // strcmp(x,"") -> *x
-        LoadInst* load = new LoadInst(s2,ci->getName()+".val",ci);
+        LoadInst* load = 
+          new LoadInst(CastToCStr(s1,*ci),ci->getName()+".val",ci);
         CastInst* cast = 
           new CastInst(load,Type::IntTy,ci->getName()+".int",ci);
         ci->replaceAllUsesWith(cast);
@@ -1242,16 +1245,6 @@
   }
 } PowOptimizer;
 
-/// CastToCStr - Return V if it is an sbyte*, otherwise cast it to sbyte*,
-/// inserting the cast before IP, and return the cast.
-/// @brief Cast a value to a "C" string.
-static Value *CastToCStr(Value *V, Instruction &IP) {
-  const Type *SBPTy = PointerType::get(Type::SByteTy);
-  if (V->getType() != SBPTy)
-    return new CastInst(V, SBPTy, V->getName(), &IP);
-  return V;
-}
-
 /// This LibCallOptimization will simplify calls to the "fprintf" library 
 /// function. It looks for cases where the result of fprintf is not used and the
 /// operation can be reduced to something simpler.
@@ -1889,6 +1882,16 @@
   return true; // success!
 }
 
+/// CastToCStr - Return V if it is an sbyte*, otherwise cast it to sbyte*,
+/// inserting the cast before IP, and return the cast.
+/// @brief Cast a value to a "C" string.
+Value *CastToCStr(Value *V, Instruction &IP) {
+  const Type *SBPTy = PointerType::get(Type::SByteTy);
+  if (V->getType() != SBPTy)
+    return new CastInst(V, SBPTy, V->getName(), &IP);
+  return V;
+}
+
 // TODO: 
 //   Additional cases that we need to add to this file:
 //





From alenhar2 at cs.uiuc.edu  Sat Jun 18 13:28:29 2005
From: alenhar2 at cs.uiuc.edu (Andrew Lenharth)
Date: Sat, 18 Jun 2005 13:28:29 -0500
Subject: [llvm-commits] CVS: llvm/docs/LangRef.html 
Message-ID: <200506181828.NAA25788@zion.cs.uiuc.edu>



Changes in directory llvm/docs:

LangRef.html updated: 1.108 -> 1.109
---
Log message:

OK, after checking the backwards compatibility code on X86 and the new code 
path on alpha, now has come the time for new vararg support.  So, with out
further ado, I revert behavior back a couple of years!

Well, ok, I lied.  A few more notes.

First, the Simple ISels cannot be expected to work any longer, but they 
should still compile

Second, there are likely some bugs to track down once the nightly testers
start with this.

Third, the initial patch doesn't include sparcv9, but I'll do that today.

Forth, subsequent patches won't bother being long winded.



---
Diffs of the changes:  (+50 -93)

 LangRef.html |  143 ++++++++++++++++++++---------------------------------------
 1 files changed, 50 insertions(+), 93 deletions(-)


Index: llvm/docs/LangRef.html
diff -u llvm/docs/LangRef.html:1.108 llvm/docs/LangRef.html:1.109
--- llvm/docs/LangRef.html:1.108	Mon May 16 11:17:45 2005
+++ llvm/docs/LangRef.html	Sat Jun 18 13:28:17 2005
@@ -101,7 +101,6 @@
           <li><a href="#i_cast">'<tt>cast .. to</tt>' Instruction</a></li>
           <li><a href="#i_select">'<tt>select</tt>' Instruction</a></li>
           <li><a href="#i_call">'<tt>call</tt>'  Instruction</a></li>
-          <li><a href="#i_vanext">'<tt>vanext</tt>' Instruction</a></li>
           <li><a href="#i_vaarg">'<tt>vaarg</tt>'  Instruction</a></li>
         </ol>
       </li>
@@ -2211,58 +2210,6 @@
 
 <!-- _______________________________________________________________________ -->
 <div class="doc_subsubsection">
-  <a name="i_vanext">'<tt>vanext</tt>' Instruction</a>
-</div>
-
-<div class="doc_text">
-
-<h5>Syntax:</h5>
-
-<pre>
-  &lt;resultarglist&gt; = vanext &lt;va_list&gt; &lt;arglist&gt;, &lt;argty&gt;
-</pre>
-
-<h5>Overview:</h5>
-
-<p>The '<tt>vanext</tt>' instruction is used to access arguments passed
-through the "variable argument" area of a function call.  It is used to
-implement the <tt>va_arg</tt> macro in C.</p>
-
-<h5>Arguments:</h5>
-
-<p>This instruction takes a <tt>va_list</tt> value and the type of the
-argument. It returns another <tt>va_list</tt>. The actual type of
-<tt>va_list</tt> may be defined differently for different targets.  Most targets
-use a <tt>va_list</tt> type of <tt>sbyte*</tt> or some other pointer type.</p>
-
-<h5>Semantics:</h5>
-
-<p>The '<tt>vanext</tt>' instruction advances the specified <tt>va_list</tt>
-past an argument of the specified type.  In conjunction with the <a
- href="#i_vaarg"><tt>vaarg</tt></a> instruction, it is used to implement
-the <tt>va_arg</tt> macro available in C.  For more information, see
-the variable argument handling <a href="#int_varargs">Intrinsic
-Functions</a>.</p>
-
-<p>It is legal for this instruction to be called in a function which
-does not take a variable number of arguments, for example, the <tt>vfprintf</tt>
-function.</p>
-
-<p><tt>vanext</tt> is an LLVM instruction instead of an <a
-href="#intrinsics">intrinsic function</a> because it takes a type as an
-argument.  The type refers to the current argument in the <tt>va_list</tt>; it
-tells the compiler how far on the stack it needs to advance to find the next
-argument.</p>
-
-<h5>Example:</h5>
-
-<p>See the <a href="#int_varargs">variable argument processing</a>
-section.</p>
-
-</div>
-
-<!-- _______________________________________________________________________ -->
-<div class="doc_subsubsection">
   <a name="i_vaarg">'<tt>vaarg</tt>' Instruction</a>
 </div>
 
@@ -2271,34 +2218,35 @@
 <h5>Syntax:</h5>
 
 <pre>
-  &lt;resultval&gt; = vaarg &lt;va_list&gt; &lt;arglist&gt;, &lt;argty&gt;
+  &lt;resultval&gt; = va_arg &lt;va_list*&gt; &lt;arglist&gt;, &lt;argty&gt;
 </pre>
 
 <h5>Overview:</h5>
 
-<p>The '<tt>vaarg</tt>' instruction is used to access arguments passed through
+<p>The '<tt>va_arg</tt>' instruction is used to access arguments passed through
 the "variable argument" area of a function call.  It is used to implement the
 <tt>va_arg</tt> macro in C.</p>
 
 <h5>Arguments:</h5>
 
-<p>This instruction takes a <tt>va_list</tt> value and the type of the
-argument. It returns a value of the specified argument type.  Again, the actual
-type of <tt>va_list</tt> is target specific.</p>
+<p>This instruction takes a <tt>va_list*</tt> value and the type of
+the argument. It returns a value of the specified argument type and
+increments the <tt>va_list</tt> to poin to the next argument.  Again, the
+actual type of <tt>va_list</tt> is target specific.</p>
 
 <h5>Semantics:</h5>
 
-<p>The '<tt>vaarg</tt>' instruction loads an argument of the specified type from
-the specified <tt>va_list</tt>.  In conjunction with the <a
-href="#i_vanext"><tt>vanext</tt></a> instruction, it is used to implement the
-<tt>va_arg</tt> macro available in C.  For more information, see the variable
-argument handling <a href="#int_varargs">Intrinsic Functions</a>.</p>
+<p>The '<tt>va_arg</tt>' instruction loads an argument of the specified
+type from the specified <tt>va_list</tt> and causes the
+<tt>va_list</tt> to point to the next argument.  For more information,
+see the variable argument handling <a href="#int_varargs">Intrinsic
+Functions</a>.</p>
 
 <p>It is legal for this instruction to be called in a function which does not
 take a variable number of arguments, for example, the <tt>vfprintf</tt>
 function.</p>
 
-<p><tt>vaarg</tt> is an LLVM instruction instead of an <a
+<p><tt>va_arg</tt> is an LLVM instruction instead of an <a
 href="#intrinsics">intrinsic function</a> because it takes a type as an
 argument.</p>
 
@@ -2361,20 +2309,20 @@
 <pre>
 int %test(int %X, ...) {
   ; Initialize variable argument processing
-  %ap = call sbyte* %<a href="#i_va_start">llvm.va_start</a>()
+  %ap = alloca sbyte*
+  call void %<a href="#i_va_start">llvm.va_start</a>(sbyte** %ap)
 
   ; Read a single integer argument
-  %tmp = vaarg sbyte* %ap, int
-
-  ; Advance to the next argument
-  %ap2 = vanext sbyte* %ap, int
+  %tmp = va_arg sbyte** %ap, int
 
   ; Demonstrate usage of llvm.va_copy and llvm.va_end
-  %aq = call sbyte* %<a href="#i_va_copy">llvm.va_copy</a>(sbyte* %ap2)
-  call void %<a href="#i_va_end">llvm.va_end</a>(sbyte* %aq)
+  %aq = alloca sbyte*
+  %apv = load sbyte** %ap
+  call void %<a href="#i_va_copy">llvm.va_copy</a>(sbyte** %aq, sbyte* %apv)
+  call void %<a href="#i_va_end">llvm.va_end</a>(sbyte** %aq)
 
   ; Stop processing of arguments.
-  call void %<a href="#i_va_end">llvm.va_end</a>(sbyte* %ap2)
+  call void %<a href="#i_va_end">llvm.va_end</a>(sbyte** %ap)
   ret int %tmp
 }
 </pre>
@@ -2388,19 +2336,25 @@
 
 <div class="doc_text">
 <h5>Syntax:</h5>
-<pre>  declare &lt;va_list&gt; %llvm.va_start()<br></pre>
+<pre>  declare void %llvm.va_start(&lt;va_list&gt;* &lt;arglist&gt;)<br></pre>
 <h5>Overview:</h5>
-<p>The '<tt>llvm.va_start</tt>' intrinsic returns a new <tt>&lt;arglist&gt;</tt>
-for subsequent use by the variable argument intrinsics.</p>
+<P>The '<tt>llvm.va_start</tt>' intrinsic initializes
+<tt>*&lt;arglist&gt;</tt> for subsequent use by <tt><a
+href="#i_va_arg">va_arg</a></tt>.</p>
+
+<h5>Arguments:</h5>
+
+<P>The argument is a pointer to a <tt>va_list</tt> element to initialize.</p>
+
 <h5>Semantics:</h5>
-<p>The '<tt>llvm.va_start</tt>' intrinsic works just like the <tt>va_start</tt>
-macro available in C.  In a target-dependent way, it initializes and
-returns a <tt>va_list</tt> element, so that the next <tt>vaarg</tt>
-will produce the first variable argument passed to the function.  Unlike
-the C <tt>va_start</tt> macro, this intrinsic does not need to know the
-last argument of the function; the compiler can figure that out.</p>
-<p>Note that this intrinsic function is only legal to be called from
-within the body of a variable argument function.</p>
+
+<P>The '<tt>llvm.va_start</tt>' intrinsic works just like the <tt>va_start</tt>
+macro available in C.  In a target-dependent way, it initializes the
+<tt>va_list</tt> element the argument points to, so that the next call to
+<tt>va_arg</tt> will produce the first variable argument passed to the function.
+Unlike the C <tt>va_start</tt> macro, this intrinsic does not need to know the
+last argument of the function, the compiler can figure that out.</p>
+
 </div>
 
 <!-- _______________________________________________________________________ -->
@@ -2410,7 +2364,7 @@
 
 <div class="doc_text">
 <h5>Syntax:</h5>
-<pre>  declare void %llvm.va_end(&lt;va_list&gt; &lt;arglist&gt;)<br></pre>
+<pre>  declare void %llvm.va_end(&lt;va_list*&gt; &lt;arglist&gt;)<br></pre>
 <h5>Overview:</h5>
 <p>The '<tt>llvm.va_end</tt>' intrinsic destroys <tt>&lt;arglist&gt;</tt>
 which has been initialized previously with <tt><a href="#i_va_start">llvm.va_start</a></tt>
@@ -2435,24 +2389,27 @@
 <h5>Syntax:</h5>
 
 <pre>
-  declare &lt;va_list&gt; %llvm.va_copy(&lt;va_list&gt; &lt;destarglist&gt;)
+  declare void %llvm.va_copy(&lt;va_list&gt;* &lt;destarglist&gt;,
+                                          &lt;va_list&gt; &lt;srcarglist&gt;)
 </pre>
 
 <h5>Overview:</h5>
 
-<p>The '<tt>llvm.va_copy</tt>' intrinsic copies the current argument position
-from the source argument list to the destination argument list.</p>
+<p>The '<tt>llvm.va_copy</tt>' intrinsic copies the current argument position from
+the source argument list to the destination argument list.</p>
 
 <h5>Arguments:</h5>
 
-<p>The argument is the <tt>va_list</tt> to copy.</p>
+<p>The first argument is a pointer to a <tt>va_list</tt> element to initialize.
+The second argument is a <tt>va_list</tt> element to copy from.</p>
+
 
 <h5>Semantics:</h5>
 
-<p>The '<tt>llvm.va_copy</tt>' intrinsic works just like the <tt>va_copy</tt>
-macro available in C.  In a target-dependent way, it copies the source
-<tt>va_list</tt> element into the returned list.  This intrinsic is necessary
-because the <tt><a href="#i_va_start">llvm.va_start</a></tt> intrinsic may be
+<p>The '<tt>llvm.va_copy</tt>' intrinsic works just like the <tt>va_copy</tt> macro
+available in C.  In a target-dependent way, it copies the source
+<tt>va_list</tt> element into the destination list.  This intrinsic is necessary
+because the <tt><a href="i_va_begin">llvm.va_begin</a></tt> intrinsic may be
 arbitrarily complex and require memory allocation, for example.</p>
 
 </div>
@@ -3305,7 +3262,7 @@
 
   <a href="mailto:sabre at nondot.org">Chris Lattner</a><br>
   <a href="http://llvm.cs.uiuc.edu">The LLVM Compiler Infrastructure</a><br>
-  Last modified: $Date: 2005/05/16 16:17:45 $
+  Last modified: $Date: 2005/06/18 18:28:17 $
 </address>
 </body>
 </html>





From alenhar2 at cs.uiuc.edu  Sat Jun 18 13:30:49 2005
From: alenhar2 at cs.uiuc.edu (Andrew Lenharth)
Date: Sat, 18 Jun 2005 13:30:49 -0500
Subject: [llvm-commits] CVS: llvm/test/Feature/varargs_new.ll 
Message-ID: <200506181830.NAA25879@zion.cs.uiuc.edu>



Changes in directory llvm/test/Feature:

varargs_new.ll added (r1.1)
---
Log message:

new vararg test

---
Diffs of the changes:  (+33 -0)

 varargs_new.ll |   33 +++++++++++++++++++++++++++++++++
 1 files changed, 33 insertions(+)


Index: llvm/test/Feature/varargs_new.ll
diff -c /dev/null llvm/test/Feature/varargs_new.ll:1.1
*** /dev/null	Sat Jun 18 13:30:47 2005
--- llvm/test/Feature/varargs_new.ll	Sat Jun 18 13:30:37 2005
***************
*** 0 ****
--- 1,33 ----
+ ; RUN: llvm-as %s -o - | llvm-dis > %t1.ll
+ ; RUN: llvm-as %t1.ll -o - | llvm-dis > %t2.ll
+ ; RUN: diff %t1.ll %t2.ll
+ 
+ ; Demonstrate all of the variable argument handling intrinsic functions plus 
+ ; the va_arg instruction.
+ 
+ implementation   ; Functions:
+ declare void %llvm.va_start(sbyte**)
+ declare void %llvm.va_copy(sbyte**, sbyte*)
+ declare void %llvm.va_end(sbyte**)
+ 
+ int %test(int %X, ...) {
+         ; Allocate two va_list items.  On this target, va_list is of type sbyte*
+         %ap = alloca sbyte*             ; <sbyte**> [#uses=4]
+         %aq = alloca sbyte*             ; <sbyte**> [#uses=2]
+ 
+         ; Initialize variable argument processing
+         call void %llvm.va_start(sbyte** %ap)
+ 
+         ; Read a single integer argument
+         %tmp = vaarg sbyte** %ap, int           ; <int> [#uses=1]
+ 
+         ; Demonstrate usage of llvm.va_copy and llvm_va_end
+         %apv = load sbyte** %ap         ; <sbyte*> [#uses=1]
+         call void %llvm.va_copy(sbyte** %aq, sbyte* %apv)
+         call void %llvm.va_end(sbyte** %aq)
+ 
+         ; Stop processing of arguments.
+         call void %llvm.va_end(sbyte** %ap)
+         ret int %tmp
+ 
+ }





From alenhar2 at cs.uiuc.edu  Sat Jun 18 13:31:42 2005
From: alenhar2 at cs.uiuc.edu (Andrew Lenharth)
Date: Sat, 18 Jun 2005 13:31:42 -0500
Subject: [llvm-commits] CVS: llvm/include/llvm/Support/InstVisitor.h 
Message-ID: <200506181831.NAA25929@zion.cs.uiuc.edu>



Changes in directory llvm/include/llvm/Support:

InstVisitor.h updated: 1.35 -> 1.36
---
Log message:

header file changes for varargs

---
Diffs of the changes:  (+0 -1)

 InstVisitor.h |    1 -
 1 files changed, 1 deletion(-)


Index: llvm/include/llvm/Support/InstVisitor.h
diff -u llvm/include/llvm/Support/InstVisitor.h:1.35 llvm/include/llvm/Support/InstVisitor.h:1.36
--- llvm/include/llvm/Support/InstVisitor.h:1.35	Thu Apr 21 15:44:59 2005
+++ llvm/include/llvm/Support/InstVisitor.h	Sat Jun 18 13:31:30 2005
@@ -174,7 +174,6 @@
   RetTy visitSelectInst(SelectInst &I)              { DELEGATE(Instruction); }
   RetTy visitCallInst(CallInst     &I)              { DELEGATE(Instruction); }
   RetTy visitShiftInst(ShiftInst   &I)              { DELEGATE(Instruction); }
-  RetTy visitVANextInst(VANextInst &I)              { DELEGATE(Instruction); }
   RetTy visitVAArgInst(VAArgInst   &I)              { DELEGATE(Instruction); }
 
   // Next level propagators... if the user does not overload a specific





From alenhar2 at cs.uiuc.edu  Sat Jun 18 13:31:42 2005
From: alenhar2 at cs.uiuc.edu (Andrew Lenharth)
Date: Sat, 18 Jun 2005 13:31:42 -0500
Subject: [llvm-commits] CVS: llvm/include/llvm/Instruction.def
	Instructions.h 
Message-ID: <200506181831.NAA25927@zion.cs.uiuc.edu>



Changes in directory llvm/include/llvm:

Instruction.def updated: 1.14 -> 1.15
Instructions.h updated: 1.22 -> 1.23
---
Log message:

header file changes for varargs

---
Diffs of the changes:  (+5 -47)

 Instruction.def |    7 ++++---
 Instructions.h  |   45 +--------------------------------------------
 2 files changed, 5 insertions(+), 47 deletions(-)


Index: llvm/include/llvm/Instruction.def
diff -u llvm/include/llvm/Instruction.def:1.14 llvm/include/llvm/Instruction.def:1.15
--- llvm/include/llvm/Instruction.def:1.14	Sat Oct 16 13:05:37 2004
+++ llvm/include/llvm/Instruction.def	Sat Jun 18 13:31:30 2005
@@ -128,13 +128,14 @@
 
 HANDLE_OTHER_INST(30, Shl    , ShiftInst  )  // Shift operations
 HANDLE_OTHER_INST(31, Shr    , ShiftInst  )
-HANDLE_OTHER_INST(32, VANext , VANextInst )  // vanext instruction
-HANDLE_OTHER_INST(33, VAArg  , VAArgInst  )  // vaarg  instruction
+ //HANDLE_OTHER_INST(32, VANext , VANextInst )  // vanext instruction
+ //HANDLE_OTHER_INST(33, VAArg  , VAArgInst  )  // vaarg  instruction
 HANDLE_OTHER_INST(34, Select , SelectInst )  // select instruction
 
 HANDLE_OTHER_INST(35, UserOp1, Instruction)  // May be used internally in a pass
 HANDLE_OTHER_INST(36, UserOp2, Instruction)
-  LAST_OTHER_INST(36)
+HANDLE_OTHER_INST(37, VAArg  , VAArgInst  )  // vaarg  instruction
+  LAST_OTHER_INST(37)
 
 #undef  FIRST_TERM_INST
 #undef HANDLE_TERM_INST


Index: llvm/include/llvm/Instructions.h
diff -u llvm/include/llvm/Instructions.h:1.22 llvm/include/llvm/Instructions.h:1.23
--- llvm/include/llvm/Instructions.h:1.22	Sun May 15 11:13:11 2005
+++ llvm/include/llvm/Instructions.h	Sat Jun 18 13:31:30 2005
@@ -660,55 +660,12 @@
   }
 };
 
-
-//===----------------------------------------------------------------------===//
-//                                VANextInst Class
-//===----------------------------------------------------------------------===//
-
-/// VANextInst - This class represents the va_next llvm instruction, which
-/// advances a vararg list passed an argument of the specified type, returning
-/// the resultant list.
-///
-class VANextInst : public UnaryInstruction {
-  PATypeHolder ArgTy;
-  VANextInst(const VANextInst &VAN)
-    : UnaryInstruction(VAN.getType(), VANext, VAN.getOperand(0)),
-      ArgTy(VAN.getArgType()) {
-  }
-
-public:
-  VANextInst(Value *List, const Type *Ty, const std::string &Name = "",
-             Instruction *InsertBefore = 0)
-    : UnaryInstruction(List->getType(), VANext, List, Name, InsertBefore),
-      ArgTy(Ty) {
-  }
-  VANextInst(Value *List, const Type *Ty, const std::string &Name,
-             BasicBlock *InsertAtEnd)
-    : UnaryInstruction(List->getType(), VANext, List, Name, InsertAtEnd),
-      ArgTy(Ty) {
-  }
-
-  const Type *getArgType() const { return ArgTy; }
-
-  virtual VANextInst *clone() const;
-
-  // Methods for support type inquiry through isa, cast, and dyn_cast:
-  static inline bool classof(const VANextInst *) { return true; }
-  static inline bool classof(const Instruction *I) {
-    return I->getOpcode() == VANext;
-  }
-  static inline bool classof(const Value *V) {
-    return isa<Instruction>(V) && classof(cast<Instruction>(V));
-  }
-};
-
-
 //===----------------------------------------------------------------------===//
 //                                VAArgInst Class
 //===----------------------------------------------------------------------===//
 
 /// VAArgInst - This class represents the va_arg llvm instruction, which returns
-/// an argument of the specified type given a va_list.
+/// an argument of the specified type given a va_list and increments that list
 ///
 class VAArgInst : public UnaryInstruction {
   VAArgInst(const VAArgInst &VAA)





From alenhar2 at cs.uiuc.edu  Sat Jun 18 13:31:42 2005
From: alenhar2 at cs.uiuc.edu (Andrew Lenharth)
Date: Sat, 18 Jun 2005 13:31:42 -0500
Subject: [llvm-commits] CVS: llvm/include/llvm/Target/TargetLowering.h 
Message-ID: <200506181831.NAA25936@zion.cs.uiuc.edu>



Changes in directory llvm/include/llvm/Target:

TargetLowering.h updated: 1.14 -> 1.15
---
Log message:

header file changes for varargs

---
Diffs of the changes:  (+5 -6)

 TargetLowering.h |   11 +++++------
 1 files changed, 5 insertions(+), 6 deletions(-)


Index: llvm/include/llvm/Target/TargetLowering.h
diff -u llvm/include/llvm/Target/TargetLowering.h:1.14 llvm/include/llvm/Target/TargetLowering.h:1.15
--- llvm/include/llvm/Target/TargetLowering.h:1.14	Sat May 14 00:51:05 2005
+++ llvm/include/llvm/Target/TargetLowering.h	Sat Jun 18 13:31:30 2005
@@ -268,7 +268,7 @@
   /// LowerVAStart - This lowers the llvm.va_start intrinsic.  If not
   /// implemented, this method prints a message and aborts.
   virtual std::pair<SDOperand, SDOperand>
-  LowerVAStart(SDOperand Chain, SelectionDAG &DAG);
+  LowerVAStart(SDOperand Chain, SelectionDAG &DAG, SDOperand Dest);
 
   /// LowerVAEnd - This lowers llvm.va_end and returns the resultant chain.  If
   /// not implemented, this defaults to a noop.
@@ -278,13 +278,12 @@
   /// value/chain pair.  If not implemented, this defaults to returning the
   /// input operand.
   virtual std::pair<SDOperand,SDOperand>
-  LowerVACopy(SDOperand Chain, SDOperand L, SelectionDAG &DAG);
+  LowerVACopy(SDOperand Chain, SDOperand Src, SDOperand Dest, SelectionDAG &DAG);
 
-  /// LowerVAArgNext - This lowers the vaarg and vanext instructions (depending
-  /// on whether the first argument is true).  If not implemented, this prints a
-  /// message and aborts.
+  /// LowerVAArgNext - This lowers the instruction 
+  /// If not implemented, this prints a message and aborts.
   virtual std::pair<SDOperand,SDOperand>
-  LowerVAArgNext(bool isVANext, SDOperand Chain, SDOperand VAList,
+  LowerVAArgNext(SDOperand Chain, SDOperand VAList,
                  const Type *ArgTy, SelectionDAG &DAG);
 
   /// LowerFrameReturnAddress - This hook lowers a call to llvm.returnaddress or





From alenhar2 at cs.uiuc.edu  Sat Jun 18 13:35:07 2005
From: alenhar2 at cs.uiuc.edu (Andrew Lenharth)
Date: Sat, 18 Jun 2005 13:35:07 -0500
Subject: [llvm-commits] CVS: llvm/lib/Analysis/DataStructure/Local.cpp 
Message-ID: <200506181835.NAA26063@zion.cs.uiuc.edu>



Changes in directory llvm/lib/Analysis/DataStructure:

Local.cpp updated: 1.133 -> 1.134
---
Log message:

core changes for varargs

---
Diffs of the changes:  (+1 -5)

 Local.cpp |    6 +-----
 1 files changed, 1 insertion(+), 5 deletions(-)


Index: llvm/lib/Analysis/DataStructure/Local.cpp
diff -u llvm/lib/Analysis/DataStructure/Local.cpp:1.133 llvm/lib/Analysis/DataStructure/Local.cpp:1.134
--- llvm/lib/Analysis/DataStructure/Local.cpp:1.133	Thu Apr 21 16:07:28 2005
+++ llvm/lib/Analysis/DataStructure/Local.cpp	Sat Jun 18 13:34:51 2005
@@ -119,7 +119,6 @@
     void visitInstruction(Instruction &I);
 
     void visitCallSite(CallSite CS);
-    void visitVANextInst(VANextInst &I);
     void visitVAArgInst(VAArgInst   &I);
 
     void MergeConstantInitIntoNode(DSNodeHandle &NH, Constant *C);
@@ -475,11 +474,8 @@
     RetNode->mergeWith(getValueDest(*RI.getOperand(0)));
 }
 
-void GraphBuilder::visitVANextInst(VANextInst &I) {
-  getValueDest(*I.getOperand(0)).mergeWith(getValueDest(I));
-}
-
 void GraphBuilder::visitVAArgInst(VAArgInst &I) {
+  //FIXME: also updates the argument
   DSNodeHandle Ptr = getValueDest(*I.getOperand(0));
   if (Ptr.isNull()) return;
 





From alenhar2 at cs.uiuc.edu  Sat Jun 18 13:35:08 2005
From: alenhar2 at cs.uiuc.edu (Andrew Lenharth)
Date: Sat, 18 Jun 2005 13:35:08 -0500
Subject: [llvm-commits] CVS: llvm/lib/VMCore/AsmWriter.cpp Instruction.cpp
	Instructions.cpp Verifier.cpp 
Message-ID: <200506181835.NAA26073@zion.cs.uiuc.edu>



Changes in directory llvm/lib/VMCore:

AsmWriter.cpp updated: 1.179 -> 1.180
Instruction.cpp updated: 1.46 -> 1.47
Instructions.cpp updated: 1.19 -> 1.20
Verifier.cpp updated: 1.133 -> 1.134
---
Log message:

core changes for varargs

---
Diffs of the changes:  (+3 -12)

 AsmWriter.cpp    |    4 ----
 Instruction.cpp  |    5 +----
 Instructions.cpp |    1 -
 Verifier.cpp     |    5 ++---
 4 files changed, 3 insertions(+), 12 deletions(-)


Index: llvm/lib/VMCore/AsmWriter.cpp
diff -u llvm/lib/VMCore/AsmWriter.cpp:1.179 llvm/lib/VMCore/AsmWriter.cpp:1.180
--- llvm/lib/VMCore/AsmWriter.cpp:1.179	Sun May 15 11:13:11 2005
+++ llvm/lib/VMCore/AsmWriter.cpp	Sat Jun 18 13:34:52 2005
@@ -1188,10 +1188,6 @@
     if (Operand) writeOperand(Operand, true);   // Work with broken code
     Out << ", ";
     printType(I.getType());
-  } else if (const VANextInst *VAN = dyn_cast<VANextInst>(&I)) {
-    if (Operand) writeOperand(Operand, true);   // Work with broken code
-    Out << ", ";
-    printType(VAN->getArgType());
   } else if (Operand) {   // Print the normal way...
 
     // PrintAllTypes - Instructions who have operands of all the same type


Index: llvm/lib/VMCore/Instruction.cpp
diff -u llvm/lib/VMCore/Instruction.cpp:1.46 llvm/lib/VMCore/Instruction.cpp:1.47
--- llvm/lib/VMCore/Instruction.cpp:1.46	Fri May  6 00:50:54 2005
+++ llvm/lib/VMCore/Instruction.cpp	Sat Jun 18 13:34:52 2005
@@ -110,8 +110,7 @@
   case Call:    return "call";
   case Shl:     return "shl";
   case Shr:     return "shr";
-  case VANext:  return "vanext";
-  case VAArg:   return "vaarg";
+  case VAArg:   return "va_arg";
 
   default: return "<Invalid operator> ";
   }
@@ -139,8 +138,6 @@
     return LI->isVolatile() == cast<LoadInst>(I)->isVolatile();
   if (const StoreInst *SI = dyn_cast<StoreInst>(this))
     return SI->isVolatile() == cast<StoreInst>(I)->isVolatile();
-  if (const VANextInst *VAN = dyn_cast<VANextInst>(this))
-    return VAN->getArgType() == cast<VANextInst>(I)->getArgType();
   if (const CallInst *CI = dyn_cast<CallInst>(this))
     return CI->isTailCall() == cast<CallInst>(I)->isTailCall();
   return true;


Index: llvm/lib/VMCore/Instructions.cpp
diff -u llvm/lib/VMCore/Instructions.cpp:1.19 llvm/lib/VMCore/Instructions.cpp:1.20
--- llvm/lib/VMCore/Instructions.cpp:1.19	Fri May  6 15:26:43 2005
+++ llvm/lib/VMCore/Instructions.cpp	Sat Jun 18 13:34:52 2005
@@ -1096,7 +1096,6 @@
 CallInst   *CallInst::clone()   const { return new CallInst(*this); }
 ShiftInst  *ShiftInst::clone()  const { return new ShiftInst(*this); }
 SelectInst *SelectInst::clone() const { return new SelectInst(*this); }
-VANextInst *VANextInst::clone() const { return new VANextInst(*this); }
 VAArgInst  *VAArgInst::clone()  const { return new VAArgInst(*this); }
 PHINode    *PHINode::clone()    const { return new PHINode(*this); }
 ReturnInst *ReturnInst::clone() const { return new ReturnInst(*this); }


Index: llvm/lib/VMCore/Verifier.cpp
diff -u llvm/lib/VMCore/Verifier.cpp:1.133 llvm/lib/VMCore/Verifier.cpp:1.134
--- llvm/lib/VMCore/Verifier.cpp:1.133	Sun May  8 17:27:09 2005
+++ llvm/lib/VMCore/Verifier.cpp	Sat Jun 18 13:34:52 2005
@@ -178,7 +178,6 @@
     void visitPHINode(PHINode &PN);
     void visitBinaryOperator(BinaryOperator &B);
     void visitShiftInst(ShiftInst &SI);
-    void visitVANextInst(VANextInst &VAN) { visitInstruction(VAN); }
     void visitVAArgInst(VAArgInst &VAA) { visitInstruction(VAA); }
     void visitCallInst(CallInst &CI);
     void visitGetElementPtrInst(GetElementPtrInst &GEP);
@@ -655,10 +654,10 @@
     Assert1(CI.getParent()->getParent()->getFunctionType()->isVarArg(),
             "llvm.va_start intrinsic may only occur in function with variable"
             " args!", &CI);
-    NumArgs = 0;
+    NumArgs = 1;
     break;
   case Intrinsic::vaend:          NumArgs = 1; break;
-  case Intrinsic::vacopy:         NumArgs = 1; break;
+  case Intrinsic::vacopy:         NumArgs = 2; break;
 
   case Intrinsic::returnaddress:
   case Intrinsic::frameaddress:





From alenhar2 at cs.uiuc.edu  Sat Jun 18 13:35:09 2005
From: alenhar2 at cs.uiuc.edu (Andrew Lenharth)
Date: Sat, 18 Jun 2005 13:35:09 -0500
Subject: [llvm-commits] 
	CVS: llvm/lib/ExecutionEngine/Interpreter/Execution.cpp
	Interpreter.h 
Message-ID: <200506181835.NAA26083@zion.cs.uiuc.edu>



Changes in directory llvm/lib/ExecutionEngine/Interpreter:

Execution.cpp updated: 1.137 -> 1.138
Interpreter.h updated: 1.70 -> 1.71
---
Log message:

core changes for varargs

---
Diffs of the changes:  (+3 -13)

 Execution.cpp |   15 +++------------
 Interpreter.h |    1 -
 2 files changed, 3 insertions(+), 13 deletions(-)


Index: llvm/lib/ExecutionEngine/Interpreter/Execution.cpp
diff -u llvm/lib/ExecutionEngine/Interpreter/Execution.cpp:1.137 llvm/lib/ExecutionEngine/Interpreter/Execution.cpp:1.138
--- llvm/lib/ExecutionEngine/Interpreter/Execution.cpp:1.137	Thu Apr 21 17:43:08 2005
+++ llvm/lib/ExecutionEngine/Interpreter/Execution.cpp	Sat Jun 18 13:34:52 2005
@@ -988,18 +988,6 @@
   SetValue(&I, executeCastOperation(I.getOperand(0), I.getType(), SF), SF);
 }
 
-void Interpreter::visitVANextInst(VANextInst &I) {
-  ExecutionContext &SF = ECStack.back();
-
-  // Get the incoming valist parameter.  LLI treats the valist as a
-  // (ec-stack-depth var-arg-index) pair.
-  GenericValue VAList = getOperandValue(I.getOperand(0), SF);
-
-  // Move the pointer to the next vararg.
-  ++VAList.UIntPairVal.second;
-  SetValue(&I, VAList, SF);
-}
-
 #define IMPLEMENT_VAARG(TY) \
    case Type::TY##TyID: Dest.TY##Val = Src.TY##Val; break
 
@@ -1033,6 +1021,9 @@
 
   // Set the Value of this Instruction.
   SetValue(&I, Dest, SF);
+
+  // Move the pointer to the next vararg.
+  ++VAList.UIntPairVal.second;
 }
 
 //===----------------------------------------------------------------------===//


Index: llvm/lib/ExecutionEngine/Interpreter/Interpreter.h
diff -u llvm/lib/ExecutionEngine/Interpreter/Interpreter.h:1.70 llvm/lib/ExecutionEngine/Interpreter/Interpreter.h:1.71
--- llvm/lib/ExecutionEngine/Interpreter/Interpreter.h:1.70	Thu Apr 21 23:06:38 2005
+++ llvm/lib/ExecutionEngine/Interpreter/Interpreter.h	Sat Jun 18 13:34:52 2005
@@ -153,7 +153,6 @@
 
   void visitShl(ShiftInst &I);
   void visitShr(ShiftInst &I);
-  void visitVANextInst(VANextInst &I);
   void visitVAArgInst(VAArgInst &I);
   void visitInstruction(Instruction &I) {
     std::cerr << I;





From alenhar2 at cs.uiuc.edu  Sat Jun 18 13:35:09 2005
From: alenhar2 at cs.uiuc.edu (Andrew Lenharth)
Date: Sat, 18 Jun 2005 13:35:09 -0500
Subject: [llvm-commits] CVS: llvm/lib/Analysis/IPA/Andersens.cpp 
Message-ID: <200506181835.NAA26079@zion.cs.uiuc.edu>



Changes in directory llvm/lib/Analysis/IPA:

Andersens.cpp updated: 1.24 -> 1.25
---
Log message:

core changes for varargs

---
Diffs of the changes:  (+0 -5)

 Andersens.cpp |    5 -----
 1 files changed, 5 deletions(-)


Index: llvm/lib/Analysis/IPA/Andersens.cpp
diff -u llvm/lib/Analysis/IPA/Andersens.cpp:1.24 llvm/lib/Analysis/IPA/Andersens.cpp:1.25
--- llvm/lib/Analysis/IPA/Andersens.cpp:1.24	Thu Apr 21 16:08:44 2005
+++ llvm/lib/Analysis/IPA/Andersens.cpp	Sat Jun 18 13:34:51 2005
@@ -330,7 +330,6 @@
     void visitCastInst(CastInst &CI);
     void visitSetCondInst(SetCondInst &SCI) {} // NOOP!
     void visitSelectInst(SelectInst &SI);
-    void visitVANext(VANextInst &I);
     void visitVAArg(VAArgInst &I);
     void visitInstruction(Instruction &I);
   };
@@ -867,10 +866,6 @@
   }
 }
 
-void Andersens::visitVANext(VANextInst &I) {
-  // FIXME: Implement
-  assert(0 && "vanext not handled yet!");
-}
 void Andersens::visitVAArg(VAArgInst &I) {
   assert(0 && "vaarg not handled yet!");
 }





From alenhar2 at cs.uiuc.edu  Sat Jun 18 13:35:10 2005
From: alenhar2 at cs.uiuc.edu (Andrew Lenharth)
Date: Sat, 18 Jun 2005 13:35:10 -0500
Subject: [llvm-commits] CVS: llvm/lib/Target/SparcV8/SparcV8ISelSimple.cpp 
Message-ID: <200506181835.NAA26107@zion.cs.uiuc.edu>



Changes in directory llvm/lib/Target/SparcV8:

SparcV8ISelSimple.cpp updated: 1.91 -> 1.92
---
Log message:

core changes for varargs

---
Diffs of the changes:  (+20 -17)

 SparcV8ISelSimple.cpp |   37 ++++++++++++++++++++-----------------
 1 files changed, 20 insertions(+), 17 deletions(-)


Index: llvm/lib/Target/SparcV8/SparcV8ISelSimple.cpp
diff -u llvm/lib/Target/SparcV8/SparcV8ISelSimple.cpp:1.91 llvm/lib/Target/SparcV8/SparcV8ISelSimple.cpp:1.92
--- llvm/lib/Target/SparcV8/SparcV8ISelSimple.cpp:1.91	Fri Apr 22 13:06:01 2005
+++ llvm/lib/Target/SparcV8/SparcV8ISelSimple.cpp	Sat Jun 18 13:34:52 2005
@@ -102,7 +102,6 @@
     void visitBranchInst(BranchInst &I);
     void visitUnreachableInst(UnreachableInst &I) {}
     void visitCastInst(CastInst &I);
-    void visitVANextInst(VANextInst &I);
     void visitVAArgInst(VAArgInst &I);
     void visitLoadInst(LoadInst &I);
     void visitStoreInst(StoreInst &I);
@@ -1754,8 +1753,10 @@
 
   case Intrinsic::vastart: {
     // Add the VarArgsOffset to the frame pointer, and copy it to the result.
-    unsigned DestReg = getReg (CI);
-    BuildMI (BB, V8::ADDri, 2, DestReg).addReg (V8::FP).addSImm (VarArgsOffset);
+    unsigned DestReg = getReg (CI.getOperand(1));
+    unsigned Tmp = makeAnotherReg(Type::IntTy);
+    BuildMI (BB, V8::ADDri, 2, Tmp).addReg (V8::FP).addSImm (VarArgsOffset);
+    BuildMI(BB, V8::ST, 3).addReg(DestReg).addSImm(0).addReg(Tmp);
     return;
   }
 
@@ -1765,39 +1766,37 @@
 
   case Intrinsic::vacopy: {
     // Copy the va_list ptr (arg1) to the result.
-    unsigned DestReg = getReg (CI), SrcReg = getReg (CI.getOperand (1));
-    BuildMI (BB, V8::ORrr, 2, DestReg).addReg (V8::G0).addReg (SrcReg);
+    unsigned DestReg = getReg (CI.getOperand(1)), SrcReg = getReg (CI.getOperand (2));
+    BuildMI(BB, V8::ST, 3).addReg(DestReg).addSImm(0).addReg(SrcReg);
     return;
   }
   }
 }
 
-void V8ISel::visitVANextInst (VANextInst &I) {
-  // Add the type size to the vararg pointer (arg0).
-  unsigned DestReg = getReg (I);
-  unsigned SrcReg = getReg (I.getOperand (0));
-  unsigned TySize = TM.getTargetData ().getTypeSize (I.getArgType ());
-  BuildMI (BB, V8::ADDri, 2, DestReg).addReg (SrcReg).addSImm (TySize);
-}
-
 void V8ISel::visitVAArgInst (VAArgInst &I) {
-  unsigned VAList = getReg (I.getOperand (0));
+  unsigned VAListPtr = getReg (I.getOperand (0));
   unsigned DestReg = getReg (I);
+  unsigned Size;
+  unsigned VAList = makeAnotherReg(Type::IntTy);
+  BuildMI(BB, V8::LD, 2, VAList).addReg(VAListPtr).addSImm(0);
 
   switch (I.getType ()->getTypeID ()) {
   case Type::PointerTyID:
   case Type::UIntTyID:
   case Type::IntTyID:
+    Size = 4;
     BuildMI (BB, V8::LD, 2, DestReg).addReg (VAList).addSImm (0);
-    return;
+    break;
 
   case Type::ULongTyID:
   case Type::LongTyID:
+    Size = 8;
     BuildMI (BB, V8::LD, 2, DestReg).addReg (VAList).addSImm (0);
     BuildMI (BB, V8::LD, 2, DestReg+1).addReg (VAList).addSImm (4);
-    return;
+    break;
 
   case Type::DoubleTyID: {
+    Size = 8;
     unsigned DblAlign = TM.getTargetData().getDoubleAlignment();
     unsigned TempReg = makeAnotherReg (Type::IntTy);
     unsigned TempReg2 = makeAnotherReg (Type::IntTy);
@@ -1807,7 +1806,7 @@
     BuildMI (BB, V8::ST, 3).addFrameIndex (FI).addSImm (0).addReg (TempReg);
     BuildMI (BB, V8::ST, 3).addFrameIndex (FI).addSImm (4).addReg (TempReg2);
     BuildMI (BB, V8::LDDFri, 2, DestReg).addFrameIndex (FI).addSImm (0);
-    return;
+    break;
   }
 
   default:
@@ -1816,4 +1815,8 @@
     abort ();
     return;
   }
+  unsigned tmp = makeAnotherReg(Type::IntTy);
+  BuildMI (BB, V8::ADDri, 2, tmp).addReg(VAList).addSImm(Size);
+  BuildMI(BB, V8::ST, 3).addReg(VAListPtr).addSImm(0).addReg(VAList);
+  return;
 }





From alenhar2 at cs.uiuc.edu  Sat Jun 18 13:35:09 2005
From: alenhar2 at cs.uiuc.edu (Andrew Lenharth)
Date: Sat, 18 Jun 2005 13:35:09 -0500
Subject: [llvm-commits] CVS: llvm/lib/AsmParser/Lexer.l llvmAsmParser.y 
Message-ID: <200506181835.NAA26091@zion.cs.uiuc.edu>



Changes in directory llvm/lib/AsmParser:

Lexer.l updated: 1.63 -> 1.64
llvmAsmParser.y updated: 1.225 -> 1.226
---
Log message:

core changes for varargs

---
Diffs of the changes:  (+125 -8)

 Lexer.l         |    6 +-
 llvmAsmParser.y |  127 +++++++++++++++++++++++++++++++++++++++++++++++++++++---
 2 files changed, 125 insertions(+), 8 deletions(-)


Index: llvm/lib/AsmParser/Lexer.l
diff -u llvm/lib/AsmParser/Lexer.l:1.63 llvm/lib/AsmParser/Lexer.l:1.64
--- llvm/lib/AsmParser/Lexer.l:1.63	Thu May 19 22:25:47 2005
+++ llvm/lib/AsmParser/Lexer.l	Sat Jun 18 13:34:51 2005
@@ -253,9 +253,9 @@
 select          { RET_TOK(OtherOpVal, Select, SELECT); }
 shl             { RET_TOK(OtherOpVal, Shl, SHL); }
 shr             { RET_TOK(OtherOpVal, Shr, SHR); }
-vanext          { RET_TOK(OtherOpVal, VANext, VANEXT); }
-vaarg           { RET_TOK(OtherOpVal, VAArg , VAARG); }
-
+vanext          { return VANEXT_old; }
+vaarg           { return VAARG_old; }
+va_arg          { RET_TOK(OtherOpVal, VAArg , VAARG); }
 ret             { RET_TOK(TermOpVal, Ret, RET); }
 br              { RET_TOK(TermOpVal, Br, BR); }
 switch          { RET_TOK(TermOpVal, Switch, SWITCH); }


Index: llvm/lib/AsmParser/llvmAsmParser.y
diff -u llvm/lib/AsmParser/llvmAsmParser.y:1.225 llvm/lib/AsmParser/llvmAsmParser.y:1.226
--- llvm/lib/AsmParser/llvmAsmParser.y:1.225	Thu May 19 22:25:47 2005
+++ llvm/lib/AsmParser/llvmAsmParser.y	Sat Jun 18 13:34:51 2005
@@ -47,6 +47,10 @@
 
 #define YYERROR_VERBOSE 1
 
+static bool ObsoleteVarArgs;
+static BasicBlock* CurBB;
+
+
 // This contains info used when building the body of a function.  It is
 // destroyed when the function is completed.
 //
@@ -723,6 +727,7 @@
  static Module * RunParser(Module * M) {
 
   llvmAsmlineno = 1;      // Reset the current line number...
+  ObsoleteVarArgs = false;
 
   CurModule.CurrentModule = M;
   yyparse();       // Parse the file, potentially throwing exception
@@ -730,6 +735,80 @@
   Module *Result = ParserResult;
   ParserResult = 0;
 
+  if(ObsoleteVarArgs) {
+    if(Function* F = Result->getNamedFunction("llvm.va_start")) {
+      assert(F->arg_size() == 0 && "Obsolete va_start takes 0 argument!");
+      
+      //foo = va_start()
+      // ->
+      //bar = alloca typeof(foo)
+      //va_start(bar)
+      //foo = load bar
+
+      const Type* RetTy = Type::getPrimitiveType(Type::VoidTyID);
+      const Type* ArgTy = F->getFunctionType()->getReturnType();
+      const Type* ArgTyPtr = PointerType::get(ArgTy);
+      Function* NF = Result->getOrInsertFunction("llvm.va_start", 
+                                                 RetTy, ArgTyPtr, 0);
+
+      while (!F->use_empty()) {
+        CallInst* CI = cast<CallInst>(F->use_back());
+        AllocaInst* bar = new AllocaInst(ArgTy, 0, "vastart.fix.1", CI);
+        new CallInst(NF, bar, "", CI);
+        Value* foo = new LoadInst(bar, "vastart.fix.2", CI);
+        CI->replaceAllUsesWith(foo);
+        CI->getParent()->getInstList().erase(CI);
+      }
+      Result->getFunctionList().erase(F);
+    }
+    
+    if(Function* F = Result->getNamedFunction("llvm.va_end")) {
+      assert(F->arg_size() == 1 && "Obsolete va_end takes 1 argument!");
+      //vaend foo
+      // ->
+      //bar = alloca 1 of typeof(foo)
+      //vaend bar
+      const Type* RetTy = Type::getPrimitiveType(Type::VoidTyID);
+      const Type* ArgTy = F->getFunctionType()->getParamType(0);
+      const Type* ArgTyPtr = PointerType::get(ArgTy);
+      Function* NF = Result->getOrInsertFunction("llvm.va_end", 
+                                                 RetTy, ArgTyPtr, 0);
+
+      while (!F->use_empty()) {
+        CallInst* CI = cast<CallInst>(F->use_back());
+        AllocaInst* bar = new AllocaInst(ArgTy, 0, "vaend.fix.1", CI);
+        new CallInst(NF, bar, "", CI);
+        CI->getParent()->getInstList().erase(CI);
+      }
+      Result->getFunctionList().erase(F);
+    }
+
+    if(Function* F = Result->getNamedFunction("llvm.va_copy")) {
+      assert(F->arg_size() == 1 && "Obsolete va_copy takes 1 argument!");
+      //foo = vacopy(bar)
+      // ->
+      //a = alloca 1 of typeof(foo)
+      //vacopy(a, bar)
+      //foo = load a
+      
+      const Type* RetTy = Type::getPrimitiveType(Type::VoidTyID);
+      const Type* ArgTy = F->getFunctionType()->getReturnType();
+      const Type* ArgTyPtr = PointerType::get(ArgTy);
+      Function* NF = Result->getOrInsertFunction("llvm.va_copy", 
+                                                 RetTy, ArgTyPtr, ArgTy, 0);
+
+      while (!F->use_empty()) {
+        CallInst* CI = cast<CallInst>(F->use_back());
+        AllocaInst* a = new AllocaInst(ArgTy, 0, "vacopy.fix.1", CI);
+        new CallInst(NF, a, CI->getOperand(1), "", CI);
+        Value* foo = new LoadInst(a, "vacopy.fix.2", CI);
+        CI->replaceAllUsesWith(foo);
+        CI->getParent()->getInstList().erase(CI);
+      }
+      Result->getFunctionList().erase(F);
+    }
+  }
+
   return Result;
 
  }
@@ -866,7 +945,8 @@
 
 // Other Operators
 %type  <OtherOpVal> ShiftOps
-%token <OtherOpVal> PHI_TOK CAST SELECT SHL SHR VAARG VANEXT
+%token <OtherOpVal> PHI_TOK CAST SELECT SHL SHR VAARG
+%token VAARG_old VANEXT_old //OBSOLETE
 
 
 %start Module
@@ -1727,7 +1807,7 @@
     $$ = $1;
   }
   | /* empty */ {
-    $$ = getBBVal(ValID::create((int)CurFun.NextBBNum++), true);
+    $$ = CurBB = getBBVal(ValID::create((int)CurFun.NextBBNum++), true);
 
     // Make sure to move the basic block to the correct location in the
     // function, instead of leaving it inserted wherever it was first
@@ -1737,7 +1817,7 @@
     BBL.splice(BBL.end(), BBL, $$);
   }
   | LABELSTR {
-    $$ = getBBVal(ValID::create($1), true);
+    $$ = CurBB = getBBVal(ValID::create($1), true);
 
     // Make sure to move the basic block to the correct location in the
     // function, instead of leaving it inserted wherever it was first
@@ -1964,8 +2044,45 @@
     $$ = new VAArgInst($2, *$4);
     delete $4;
   }
-  | VANEXT ResolvedVal ',' Types {
-    $$ = new VANextInst($2, *$4);
+  | VAARG_old ResolvedVal ',' Types {
+    ObsoleteVarArgs = true;
+    const Type* ArgTy = $2->getType();
+    Function* NF = CurModule.CurrentModule->
+      getOrInsertFunction("llvm.va_copy", ArgTy, ArgTy, 0);
+
+    //b = vaarg a, t -> 
+    //foo = alloca 1 of t
+    //bar = vacopy a 
+    //store bar -> foo
+    //b = vaarg foo, t
+    AllocaInst* foo = new AllocaInst(ArgTy, 0, "vaarg.fix");
+    CurBB->getInstList().push_back(foo);
+    CallInst* bar = new CallInst(NF, $2);
+    CurBB->getInstList().push_back(bar);
+    CurBB->getInstList().push_back(new StoreInst(bar, foo));
+    $$ = new VAArgInst(foo, *$4);
+    delete $4;
+  }
+  | VANEXT_old ResolvedVal ',' Types {
+    ObsoleteVarArgs = true;
+    const Type* ArgTy = $2->getType();
+    Function* NF = CurModule.CurrentModule->
+      getOrInsertFunction("llvm.va_copy", ArgTy, ArgTy, 0);
+
+    //b = vanext a, t ->
+    //foo = alloca 1 of t
+    //bar = vacopy a
+    //store bar -> foo
+    //tmp = vaarg foo, t
+    //b = load foo
+    AllocaInst* foo = new AllocaInst(ArgTy, 0, "vanext.fix");
+    CurBB->getInstList().push_back(foo);
+    CallInst* bar = new CallInst(NF, $2);
+    CurBB->getInstList().push_back(bar);
+    CurBB->getInstList().push_back(new StoreInst(bar, foo));
+    Instruction* tmp = new VAArgInst(foo, *$4);
+    CurBB->getInstList().push_back(tmp);
+    $$ = new LoadInst(foo);
     delete $4;
   }
   | PHI_TOK PHIList {





From alenhar2 at cs.uiuc.edu  Sat Jun 18 13:35:09 2005
From: alenhar2 at cs.uiuc.edu (Andrew Lenharth)
Date: Sat, 18 Jun 2005 13:35:09 -0500
Subject: [llvm-commits] CVS: llvm/lib/Target/Alpha/AlphaISelPattern.cpp 
Message-ID: <200506181835.NAA26077@zion.cs.uiuc.edu>



Changes in directory llvm/lib/Target/Alpha:

AlphaISelPattern.cpp updated: 1.122 -> 1.123
---
Log message:

core changes for varargs

---
Diffs of the changes:  (+30 -8)

 AlphaISelPattern.cpp |   38 ++++++++++++++++++++++++++++++--------
 1 files changed, 30 insertions(+), 8 deletions(-)


Index: llvm/lib/Target/Alpha/AlphaISelPattern.cpp
diff -u llvm/lib/Target/Alpha/AlphaISelPattern.cpp:1.122 llvm/lib/Target/Alpha/AlphaISelPattern.cpp:1.123
--- llvm/lib/Target/Alpha/AlphaISelPattern.cpp:1.122	Wed Jun  8 13:02:21 2005
+++ llvm/lib/Target/Alpha/AlphaISelPattern.cpp	Sat Jun 18 13:34:52 2005
@@ -72,7 +72,8 @@
 //  AlphaTargetLowering - Alpha Implementation of the TargetLowering interface
 namespace {
   class AlphaTargetLowering : public TargetLowering {
-    int VarArgsFrameIndex;            // FrameIndex for start of varargs area.
+    int VarArgsOffset;  // What is the offset to the first vaarg
+    int VarArgsBase;    // What is the base FrameIndex
     unsigned GP; //GOT vreg
   public:
     AlphaTargetLowering(TargetMachine &TM) : TargetLowering(TM) {
@@ -151,10 +152,10 @@
                 SelectionDAG &DAG);
 
     virtual std::pair<SDOperand, SDOperand>
-    LowerVAStart(SDOperand Chain, SelectionDAG &DAG);
+    LowerVAStart(SDOperand Chain, SelectionDAG &DAG, SDOperand Dest);
 
     virtual std::pair<SDOperand,SDOperand>
-    LowerVAArgNext(bool isVANext, SDOperand Chain, SDOperand VAList,
+    LowerVAArgNext(SDOperand Chain, SDOperand VAList,
                    const Type *ArgTy, SelectionDAG &DAG);
 
     virtual std::pair<SDOperand, SDOperand>
@@ -300,12 +301,14 @@
 
   // If the functions takes variable number of arguments, copy all regs to stack
   if (F.isVarArg()) {
+    VarArgsOffset = count * 8;
     std::vector<SDOperand> LS;
     for (int i = 0; i < 6; ++i) {
       if (args_int[i] < 1024)
         args_int[i] = AddLiveIn(MF,args_int[i], getRegClassFor(MVT::i64));
       SDOperand argt = DAG.getCopyFromReg(args_int[i], MVT::i64, DAG.getRoot());
       int FI = MFI->CreateFixedObject(8, -8 * (6 - i));
+      if (i == 0) VarArgsBase = FI;
       SDOperand SDFI = DAG.getFrameIndex(FI, MVT::i64);
       LS.push_back(DAG.getNode(ISD::STORE, MVT::Other, DAG.getRoot(), argt, SDFI, DAG.getSrcValue(NULL)));
       
@@ -393,15 +396,34 @@
 }
 
 std::pair<SDOperand, SDOperand>
-AlphaTargetLowering::LowerVAStart(SDOperand Chain, SelectionDAG &DAG) {
-  //vastart just returns the address of the VarArgsFrameIndex slot.
-  return std::make_pair(DAG.getFrameIndex(VarArgsFrameIndex, MVT::i64), Chain);
+AlphaTargetLowering::LowerVAStart(SDOperand Chain, SelectionDAG &DAG, SDOperand Dest) {
+  // vastart just stores the address of the VarArgsBase and VarArgsOffset
+  SDOperand FR  = DAG.getFrameIndex(VarArgsBase, MVT::i32);
+  SDOperand S1  = DAG.getNode(ISD::STORE, MVT::Other, Chain, FR, Dest, DAG.getSrcValue(NULL));
+  SDOperand SA2 = DAG.getNode(ISD::ADD, MVT::i64, Dest, DAG.getConstant(8, MVT::i64));
+  SDOperand S2  = DAG.getNode(ISD::STORE, MVT::Other, S1, 
+                              DAG.getConstant(VarArgsOffset, MVT::i64), SA2, 
+                              DAG.getSrcValue(NULL));
+
+  return std::make_pair(S2, S2);
 }
 
 std::pair<SDOperand,SDOperand> AlphaTargetLowering::
-LowerVAArgNext(bool isVANext, SDOperand Chain, SDOperand VAList,
+LowerVAArgNext(SDOperand Chain, SDOperand VAList,
                const Type *ArgTy, SelectionDAG &DAG) {
-  abort();
+  //FIXME: For now, ignore FP
+  SDOperand Base = DAG.getLoad(MVT::i64, Chain, VAList, DAG.getSrcValue(NULL));
+  SDOperand Tmp = DAG.getNode(ISD::ADD, MVT::i64, VAList, 
+                              DAG.getConstant(8, MVT::i64));
+  SDOperand Offset = DAG.getLoad(MVT::i64, Chain, Tmp, DAG.getSrcValue(NULL));
+  SDOperand DataPtr = DAG.getNode(ISD::ADD, MVT::i64, Base, Offset);
+  SDOperand Result = DAG.getLoad(MVT::i64, Chain, DataPtr, 
+                                 DAG.getSrcValue(NULL));
+  SDOperand NewOffset = DAG.getNode(ISD::ADD, MVT::i64, Offset, 
+                                    DAG.getConstant(8, MVT::i64));
+  SDOperand Update = DAG.getNode(ISD::STORE, MVT::Other, Result, NewOffset, 
+                                 Tmp, DAG.getSrcValue(NULL));
+  return std::make_pair(Result, Update);
 }
 
 





From alenhar2 at cs.uiuc.edu  Sat Jun 18 13:35:09 2005
From: alenhar2 at cs.uiuc.edu (Andrew Lenharth)
Date: Sat, 18 Jun 2005 13:35:09 -0500
Subject: [llvm-commits] CVS: llvm/lib/Bytecode/Writer/SlotCalculator.cpp
	Writer.cpp 
Message-ID: <200506181835.NAA26093@zion.cs.uiuc.edu>



Changes in directory llvm/lib/Bytecode/Writer:

SlotCalculator.cpp updated: 1.71 -> 1.72
Writer.cpp updated: 1.105 -> 1.106
---
Log message:

core changes for varargs

---
Diffs of the changes:  (+1 -16)

 SlotCalculator.cpp |    6 ------
 Writer.cpp         |   11 +----------
 2 files changed, 1 insertion(+), 16 deletions(-)


Index: llvm/lib/Bytecode/Writer/SlotCalculator.cpp
diff -u llvm/lib/Bytecode/Writer/SlotCalculator.cpp:1.71 llvm/lib/Bytecode/Writer/SlotCalculator.cpp:1.72
--- llvm/lib/Bytecode/Writer/SlotCalculator.cpp:1.71	Thu May  5 17:32:23 2005
+++ llvm/lib/Bytecode/Writer/SlotCalculator.cpp	Sat Jun 18 13:34:51 2005
@@ -187,8 +187,6 @@
             !isa<GlobalValue>(I->getOperand(op)))
           getOrCreateSlot(I->getOperand(op));
       getOrCreateSlot(I->getType());
-      if (const VANextInst *VAN = dyn_cast<VANextInst>(&*I))
-        getOrCreateSlot(VAN->getArgType());
     }
     processSymbolTableConstants(&F->getSymbolTable());
   }
@@ -320,8 +318,6 @@
     getOrCreateSlot(BB);
     for (BasicBlock::const_iterator I = BB->begin(), E = BB->end(); I!=E; ++I) {
       getOrCreateSlot(I);
-      if (const VANextInst *VAN = dyn_cast<VANextInst>(I))
-        getOrCreateSlot(VAN->getArgType());
     }
   }
 
@@ -472,8 +468,6 @@
     for (unsigned op = 0, e = I->getNumOperands(); op != e; ++op)
       if (isa<Constant>(I->getOperand(op)))
         getOrCreateCompactionTableSlot(I->getOperand(op));
-    if (const VANextInst *VAN = dyn_cast<VANextInst>(&*I))
-      getOrCreateCompactionTableSlot(VAN->getArgType());
   }
 
   // Do the types in the symbol table


Index: llvm/lib/Bytecode/Writer/Writer.cpp
diff -u llvm/lib/Bytecode/Writer/Writer.cpp:1.105 llvm/lib/Bytecode/Writer/Writer.cpp:1.106
--- llvm/lib/Bytecode/Writer/Writer.cpp:1.105	Fri May 13 18:35:47 2005
+++ llvm/lib/Bytecode/Writer/Writer.cpp	Sat Jun 18 13:34:51 2005
@@ -439,7 +439,7 @@
   output_typeid(Type);                      // Result type
 
   unsigned NumArgs = I->getNumOperands();
-  output_vbr(NumArgs + (isa<CastInst>(I) || isa<VANextInst>(I) ||
+  output_vbr(NumArgs + (isa<CastInst>(I)  ||
                         isa<VAArgInst>(I) || Opcode == 56 || Opcode == 58));
 
   if (!isa<GetElementPtrInst>(&I)) {
@@ -453,10 +453,6 @@
       int Slot = Table.getSlot(I->getType());
       assert(Slot != -1 && "Cast return type unknown?");
       output_typeid((unsigned)Slot);
-    } else if (const VANextInst *VAI = dyn_cast<VANextInst>(I)) {
-      int Slot = Table.getSlot(VAI->getArgType());
-      assert(Slot != -1 && "VarArg argument type unknown?");
-      output_typeid((unsigned)Slot);
     } else if (Opcode == 56) {  // Invoke escape sequence
       output_vbr(cast<InvokeInst>(I)->getCallingConv());
     } else if (Opcode == 58) {  // Call escape sequence
@@ -704,11 +700,6 @@
       assert(Slots[1] != ~0U && "Cast return type unknown?");
       if (Slots[1] > MaxOpSlot) MaxOpSlot = Slots[1];
       NumOperands++;
-    } else if (const VANextInst *VANI = dyn_cast<VANextInst>(&I)) {
-      Slots[1] = Table.getSlot(VANI->getArgType());
-      assert(Slots[1] != ~0U && "va_next return type unknown?");
-      if (Slots[1] > MaxOpSlot) MaxOpSlot = Slots[1];
-      NumOperands++;
     } else if (const GetElementPtrInst *GEP = dyn_cast<GetElementPtrInst>(&I)) {
       // We need to encode the type of sequential type indices into their slot #
       unsigned Idx = 1;





From alenhar2 at cs.uiuc.edu  Sat Jun 18 13:35:10 2005
From: alenhar2 at cs.uiuc.edu (Andrew Lenharth)
Date: Sat, 18 Jun 2005 13:35:10 -0500
Subject: [llvm-commits] CVS: llvm/lib/Target/PowerPC/PPC32ISelSimple.cpp
	PPC64ISelPattern.cpp 
Message-ID: <200506181835.NAA26127@zion.cs.uiuc.edu>



Changes in directory llvm/lib/Target/PowerPC:

PPC32ISelSimple.cpp updated: 1.141 -> 1.142
PPC64ISelPattern.cpp updated: 1.21 -> 1.22
---
Log message:

core changes for varargs

---
Diffs of the changes:  (+41 -43)

 PPC32ISelSimple.cpp  |   44 ++++++++++++++------------------------------
 PPC64ISelPattern.cpp |   40 +++++++++++++++++++++++++++-------------
 2 files changed, 41 insertions(+), 43 deletions(-)


Index: llvm/lib/Target/PowerPC/PPC32ISelSimple.cpp
diff -u llvm/lib/Target/PowerPC/PPC32ISelSimple.cpp:1.141 llvm/lib/Target/PowerPC/PPC32ISelSimple.cpp:1.142
--- llvm/lib/Target/PowerPC/PPC32ISelSimple.cpp:1.141	Fri Apr 22 12:54:30 2005
+++ llvm/lib/Target/PowerPC/PPC32ISelSimple.cpp	Sat Jun 18 13:34:52 2005
@@ -310,7 +310,6 @@
     void visitShiftInst(ShiftInst &I);
     void visitPHINode(PHINode &I) {}      // PHI nodes handled by second pass
     void visitCastInst(CastInst &I);
-    void visitVANextInst(VANextInst &I);
     void visitVAArgInst(VAArgInst &I);
 
     void visitInstruction(Instruction &I) {
@@ -1978,6 +1977,7 @@
   unsigned TmpReg1, TmpReg2, TmpReg3;
   switch (ID) {
   case Intrinsic::vastart:
+    //FIXME: need to store, not return a value
     // Get the address of the first vararg value...
     TmpReg1 = getReg(CI);
     addFrameReference(BuildMI(BB, PPC::ADDI, 2, TmpReg1), VarArgsFrameIndex,
@@ -1985,6 +1985,7 @@
     return;
 
   case Intrinsic::vacopy:
+    //FIXME: need to store into first arg the value of the second
     TmpReg1 = getReg(CI);
     TmpReg2 = getReg(CI.getOperand(1));
     BuildMI(BB, PPC::OR, 2, TmpReg1).addReg(TmpReg2).addReg(TmpReg2);
@@ -3679,37 +3680,12 @@
   abort();
 }
 
-/// visitVANextInst - Implement the va_next instruction...
-///
-void PPC32ISel::visitVANextInst(VANextInst &I) {
-  unsigned VAList = getReg(I.getOperand(0));
-  unsigned DestReg = getReg(I);
-
-  unsigned Size;
-  switch (I.getArgType()->getTypeID()) {
-  default:
-    std::cerr << I;
-    assert(0 && "Error: bad type for va_next instruction!");
-    return;
-  case Type::PointerTyID:
-  case Type::UIntTyID:
-  case Type::IntTyID:
-    Size = 4;
-    break;
-  case Type::ULongTyID:
-  case Type::LongTyID:
-  case Type::DoubleTyID:
-    Size = 8;
-    break;
-  }
-
-  // Increment the VAList pointer...
-  BuildMI(BB, PPC::ADDI, 2, DestReg).addReg(VAList).addSImm(Size);
-}
-
 void PPC32ISel::visitVAArgInst(VAArgInst &I) {
-  unsigned VAList = getReg(I.getOperand(0));
+  unsigned VAListPtr = getReg(I.getOperand(0));
   unsigned DestReg = getReg(I);
+  unsigned VAList = makeAnotherReg(Type::IntTy);
+  BuildMI(BB, PPC::LWZ, 2, VAList).addSImm(0).addReg(VAListPtr);
+  int Size;
 
   switch (I.getType()->getTypeID()) {
   default:
@@ -3719,20 +3695,28 @@
   case Type::PointerTyID:
   case Type::UIntTyID:
   case Type::IntTyID:
+    Size = 4;
     BuildMI(BB, PPC::LWZ, 2, DestReg).addSImm(0).addReg(VAList);
     break;
   case Type::ULongTyID:
   case Type::LongTyID:
+    Size = 8;
     BuildMI(BB, PPC::LWZ, 2, DestReg).addSImm(0).addReg(VAList);
     BuildMI(BB, PPC::LWZ, 2, DestReg+1).addSImm(4).addReg(VAList);
     break;
   case Type::FloatTyID:
+    Size = 4; //?? Bad value?
     BuildMI(BB, PPC::LFS, 2, DestReg).addSImm(0).addReg(VAList);
     break;
   case Type::DoubleTyID:
+    Size = 8;
     BuildMI(BB, PPC::LFD, 2, DestReg).addSImm(0).addReg(VAList);
     break;
   }
+  // Increment the VAList pointer...
+  unsigned NP = makeAnotherReg(Type::IntTy);
+  BuildMI(BB, PPC::ADDI, 2, NP).addReg(VAList).addSImm(Size);
+  BuildMI(BB, PPC::STW, 3).addReg(NP).addSImm(0).addReg(VAListPtr);
 }
 
 /// visitGetElementPtrInst - instruction-select GEP instructions


Index: llvm/lib/Target/PowerPC/PPC64ISelPattern.cpp
diff -u llvm/lib/Target/PowerPC/PPC64ISelPattern.cpp:1.21 llvm/lib/Target/PowerPC/PPC64ISelPattern.cpp:1.22
--- llvm/lib/Target/PowerPC/PPC64ISelPattern.cpp:1.21	Sun May 15 14:54:37 2005
+++ llvm/lib/Target/PowerPC/PPC64ISelPattern.cpp	Sat Jun 18 13:34:52 2005
@@ -98,12 +98,16 @@
                 SelectionDAG &DAG);
 
     virtual std::pair<SDOperand, SDOperand>
-    LowerVAStart(SDOperand Chain, SelectionDAG &DAG);
+    LowerVAStart(SDOperand Chain, SelectionDAG &DAG, SDOperand Dest);
 
     virtual std::pair<SDOperand,SDOperand>
-    LowerVAArgNext(bool isVANext, SDOperand Chain, SDOperand VAList,
+    LowerVAArgNext(SDOperand Chain, SDOperand VAList,
                    const Type *ArgTy, SelectionDAG &DAG);
 
+    virtual std::pair<SDOperand,SDOperand>
+    LowerVACopy(SDOperand Chain, SDOperand Src, SDOperand Dest,
+                SelectionDAG &DAG);
+
     virtual std::pair<SDOperand, SDOperand>
     LowerFrameReturnAddress(bool isFrameAddr, SDOperand Chain, unsigned Depth,
                             SelectionDAG &DAG);
@@ -365,26 +369,36 @@
 }
 
 std::pair<SDOperand, SDOperand>
-PPC64TargetLowering::LowerVAStart(SDOperand Chain, SelectionDAG &DAG) {
-  //vastart just returns the address of the VarArgsFrameIndex slot.
-  return std::make_pair(DAG.getFrameIndex(VarArgsFrameIndex, MVT::i64), Chain);
+PPC64TargetLowering::LowerVAStart(SDOperand Chain, SelectionDAG &DAG, SDOperand Dest) {
+  // vastart just stores the address of the VarArgsFrameIndex slot.
+  SDOperand FR = DAG.getFrameIndex(VarArgsFrameIndex, MVT::i64);
+  SDOperand Result = DAG.getNode(ISD::STORE, MVT::Other, Chain, FR, Dest, DAG.getSrcValue(NULL));
+  return std::make_pair(Result, Result);
 }
 
 std::pair<SDOperand,SDOperand> PPC64TargetLowering::
-LowerVAArgNext(bool isVANext, SDOperand Chain, SDOperand VAList,
+LowerVAArgNext(SDOperand Chain, SDOperand VAList,
                const Type *ArgTy, SelectionDAG &DAG) {
   MVT::ValueType ArgVT = getValueType(ArgTy);
   SDOperand Result;
-  if (!isVANext) {
-    Result = DAG.getLoad(ArgVT, DAG.getEntryNode(), VAList,
-                         DAG.getSrcValue(NULL));
-  } else {
-    Result = DAG.getNode(ISD::ADD, VAList.getValueType(), VAList,
-                         DAG.getConstant(8, VAList.getValueType()));
-  }
+  SDOperand Val = DAG.getLoad(MVT::i64, Chain, VAList, DAG.getSrcValue(NULL));
+  Result = DAG.getLoad(ArgVT, Val.getValue(1), Val, DAG.getSrcValue(NULL));
+  Val = DAG.getNode(ISD::ADD, VAList.getValueType(), Val,
+                    DAG.getConstant(8, VAList.getValueType()));
+  Chain = DAG.getNode(ISD::STORE, MVT::Other, Chain,
+                      Val, VAList, DAG.getSrcValue(NULL));
   return std::make_pair(Result, Chain);
 }
 
+std::pair<SDOperand,SDOperand>
+PPC64TargetLowering::LowerVACopy(SDOperand Chain, SDOperand Src, 
+                                 SDOperand Dest, SelectionDAG &DAG)
+{
+  SDOperand Result = DAG.getNode(ISD::STORE, MVT::Other, Chain,
+                                 Src, Dest, DAG.getSrcValue(NULL));
+  return std::make_pair(Result, Result);
+}
+
 
 std::pair<SDOperand, SDOperand> PPC64TargetLowering::
 LowerFrameReturnAddress(bool isFrameAddress, SDOperand Chain, unsigned Depth,





From alenhar2 at cs.uiuc.edu  Sat Jun 18 13:35:09 2005
From: alenhar2 at cs.uiuc.edu (Andrew Lenharth)
Date: Sat, 18 Jun 2005 13:35:09 -0500
Subject: [llvm-commits] 
	CVS: llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
Message-ID: <200506181835.NAA26085@zion.cs.uiuc.edu>



Changes in directory llvm/lib/CodeGen/SelectionDAG:

SelectionDAGISel.cpp updated: 1.60 -> 1.61
---
Log message:

core changes for varargs

---
Diffs of the changes:  (+12 -18)

 SelectionDAGISel.cpp |   30 ++++++++++++------------------
 1 files changed, 12 insertions(+), 18 deletions(-)


Index: llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.60 llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.61
--- llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.60	Sat May 14 08:56:55 2005
+++ llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp	Sat Jun 18 13:34:51 2005
@@ -356,7 +356,6 @@
   void visitCall(CallInst &I);
 
   void visitVAStart(CallInst &I);
-  void visitVANext(VANextInst &I);
   void visitVAArg(VAArgInst &I);
   void visitVAEnd(CallInst &I);
   void visitVACopy(CallInst &I);
@@ -839,7 +838,7 @@
 }
 
 std::pair<SDOperand, SDOperand>
-TargetLowering::LowerVAStart(SDOperand Chain, SelectionDAG &DAG) {
+TargetLowering::LowerVAStart(SDOperand Chain, SelectionDAG &DAG, SDOperand Dest) {
   // We have no sane default behavior, just emit a useful error message and bail
   // out.
   std::cerr << "Variable arguments handling not implemented on this target!\n";
@@ -854,13 +853,16 @@
 }
 
 std::pair<SDOperand,SDOperand>
-TargetLowering::LowerVACopy(SDOperand Chain, SDOperand L, SelectionDAG &DAG) {
-  // Default to returning the input list.
-  return std::make_pair(L, Chain);
+TargetLowering::LowerVACopy(SDOperand Chain, SDOperand Src, SDOperand Dest, 
+                            SelectionDAG &DAG) {
+  // We have no sane default behavior, just emit a useful error message and bail
+  // out.
+  std::cerr << "Variable arguments handling not implemented on this target!\n";
+  abort();
 }
 
 std::pair<SDOperand,SDOperand>
-TargetLowering::LowerVAArgNext(bool isVANext, SDOperand Chain, SDOperand VAList,
+TargetLowering::LowerVAArgNext(SDOperand Chain, SDOperand VAList,
                                const Type *ArgTy, SelectionDAG &DAG) {
   // We have no sane default behavior, just emit a useful error message and bail
   // out.
@@ -871,23 +873,15 @@
 
 
 void SelectionDAGLowering::visitVAStart(CallInst &I) {
-  std::pair<SDOperand,SDOperand> Result = TLI.LowerVAStart(getRoot(), DAG);
+  std::pair<SDOperand,SDOperand> Result = TLI.LowerVAStart(getRoot(), DAG, getValue(I.getOperand(1)));
   setValue(&I, Result.first);
   DAG.setRoot(Result.second);
 }
 
 void SelectionDAGLowering::visitVAArg(VAArgInst &I) {
   std::pair<SDOperand,SDOperand> Result =
-    TLI.LowerVAArgNext(false, getRoot(), getValue(I.getOperand(0)),
-                       I.getType(), DAG);
-  setValue(&I, Result.first);
-  DAG.setRoot(Result.second);
-}
-
-void SelectionDAGLowering::visitVANext(VANextInst &I) {
-  std::pair<SDOperand,SDOperand> Result =
-    TLI.LowerVAArgNext(true, getRoot(), getValue(I.getOperand(0)),
-                       I.getArgType(), DAG);
+    TLI.LowerVAArgNext(getRoot(), getValue(I.getOperand(0)),
+                   I.getType(), DAG);
   setValue(&I, Result.first);
   DAG.setRoot(Result.second);
 }
@@ -898,7 +892,7 @@
 
 void SelectionDAGLowering::visitVACopy(CallInst &I) {
   std::pair<SDOperand,SDOperand> Result =
-    TLI.LowerVACopy(getRoot(), getValue(I.getOperand(1)), DAG);
+    TLI.LowerVACopy(getRoot(), getValue(I.getOperand(2)), getValue(I.getOperand(1)), DAG);
   setValue(&I, Result.first);
   DAG.setRoot(Result.second);
 }





From alenhar2 at cs.uiuc.edu  Sat Jun 18 13:35:10 2005
From: alenhar2 at cs.uiuc.edu (Andrew Lenharth)
Date: Sat, 18 Jun 2005 13:35:10 -0500
Subject: [llvm-commits] CVS: llvm/lib/Bytecode/Reader/Reader.cpp
	ReaderWrappers.cpp 
Message-ID: <200506181835.NAA26121@zion.cs.uiuc.edu>



Changes in directory llvm/lib/Bytecode/Reader:

Reader.cpp updated: 1.163 -> 1.164
ReaderWrappers.cpp updated: 1.47 -> 1.48
---
Log message:

core changes for varargs

---
Diffs of the changes:  (+134 -6)

 Reader.cpp         |   39 ++++++++++++++++++--
 ReaderWrappers.cpp |  101 +++++++++++++++++++++++++++++++++++++++++++++++++++--
 2 files changed, 134 insertions(+), 6 deletions(-)


Index: llvm/lib/Bytecode/Reader/Reader.cpp
diff -u llvm/lib/Bytecode/Reader/Reader.cpp:1.163 llvm/lib/Bytecode/Reader/Reader.cpp:1.164
--- llvm/lib/Bytecode/Reader/Reader.cpp:1.163	Fri May  6 17:35:09 2005
+++ llvm/lib/Bytecode/Reader/Reader.cpp	Sat Jun 18 13:34:51 2005
@@ -658,10 +658,43 @@
     Result = new VAArgInst(getValue(iType, Oprnds[0]),
                            getSanitizedType(Oprnds[1]));
     break;
-  case Instruction::VANext:
-    Result = new VANextInst(getValue(iType, Oprnds[0]),
-                            getSanitizedType(Oprnds[1]));
+  case 32: { //VANext_old
+    const Type* ArgTy = getValue(iType, Oprnds[0])->getType();
+    Function* NF = TheModule->getOrInsertFunction("llvm.va_copy", ArgTy, ArgTy, 0);
+
+    //b = vanext a, t ->
+    //foo = alloca 1 of t
+    //bar = vacopy a
+    //store bar -> foo
+    //tmp = vaarg foo, t
+    //b = load foo
+    AllocaInst* foo = new AllocaInst(ArgTy, 0, "vanext.fix");
+    BB->getInstList().push_back(foo);
+    CallInst* bar = new CallInst(NF, getValue(iType, Oprnds[0]));
+    BB->getInstList().push_back(bar);
+    BB->getInstList().push_back(new StoreInst(bar, foo));
+    Instruction* tmp = new VAArgInst(foo, getSanitizedType(Oprnds[1]));
+    BB->getInstList().push_back(tmp);
+    Result = new LoadInst(foo);
+    break;
+  }
+  case 33: { //VAArg_old
+    const Type* ArgTy = getValue(iType, Oprnds[0])->getType();
+    Function* NF = TheModule->getOrInsertFunction("llvm.va_copy", ArgTy, ArgTy, 0);
+
+    //b = vaarg a, t -> 
+    //foo = alloca 1 of t
+    //bar = vacopy a 
+    //store bar -> foo
+    //b = vaarg foo, t
+    AllocaInst* foo = new AllocaInst(ArgTy, 0, "vaarg.fix");
+    BB->getInstList().push_back(foo);
+    CallInst* bar = new CallInst(NF, getValue(iType, Oprnds[0]));
+    BB->getInstList().push_back(bar);
+    BB->getInstList().push_back(new StoreInst(bar, foo));
+    Result = new VAArgInst(foo, getSanitizedType(Oprnds[1]));
     break;
+  }
   case Instruction::Cast:
     Result = new CastInst(getValue(iType, Oprnds[0]),
                           getSanitizedType(Oprnds[1]));


Index: llvm/lib/Bytecode/Reader/ReaderWrappers.cpp
diff -u llvm/lib/Bytecode/Reader/ReaderWrappers.cpp:1.47 llvm/lib/Bytecode/Reader/ReaderWrappers.cpp:1.48
--- llvm/lib/Bytecode/Reader/ReaderWrappers.cpp:1.47	Tue Jun  7 19:49:08 2005
+++ llvm/lib/Bytecode/Reader/ReaderWrappers.cpp	Sat Jun 18 13:34:51 2005
@@ -149,6 +149,100 @@
 }
 
 //===----------------------------------------------------------------------===//
+// Varargs transmogrification code...
+//
+
+// CheckVarargs - This is used to automatically translate old-style varargs to
+// new style varargs for backwards compatibility.
+static ModuleProvider* CheckVarargs(ModuleProvider* MP) {
+  Module* M = MP->getModule();
+
+  // check to see if va_start takes arguements...
+  Function* F = M->getNamedFunction("llvm.va_start");
+  if(F == 0) return MP; //No varargs use, just return.
+
+  if (F->getFunctionType()->getNumParams() == 1)
+    return MP; // Modern varargs processing, just return.
+
+  // If we get to this point, we know that we have an old-style module.
+  // Materialize the whole thing to perform the rewriting.
+  MP->materializeModule();
+
+  if(Function* F = M->getNamedFunction("llvm.va_start")) {
+    assert(F->arg_size() == 0 && "Obsolete va_start takes 0 argument!");
+    
+    //foo = va_start()
+    // ->
+    //bar = alloca typeof(foo)
+    //va_start(bar)
+    //foo = load bar
+    
+    const Type* RetTy = Type::getPrimitiveType(Type::VoidTyID);
+    const Type* ArgTy = F->getFunctionType()->getReturnType();
+    const Type* ArgTyPtr = PointerType::get(ArgTy);
+    Function* NF = M->getOrInsertFunction("llvm.va_start", 
+                                               RetTy, ArgTyPtr, 0);
+
+    for(Value::use_iterator I = F->use_begin(), E = F->use_end(); I != E;)
+      if (CallInst* CI = dyn_cast<CallInst>(*I++)) {
+        AllocaInst* bar = new AllocaInst(ArgTy, 0, "vastart.fix.1", CI);
+        new CallInst(NF, bar, "", CI);
+        Value* foo = new LoadInst(bar, "vastart.fix.2", CI);
+        CI->replaceAllUsesWith(foo);
+        CI->getParent()->getInstList().erase(CI);
+      }
+    F->setName("");
+  }
+    
+  if(Function* F = M->getNamedFunction("llvm.va_end")) {
+    assert(F->arg_size() == 1 && "Obsolete va_end takes 1 argument!");
+    //vaend foo
+    // ->
+    //bar = alloca 1 of typeof(foo)
+    //vaend bar
+    const Type* RetTy = Type::getPrimitiveType(Type::VoidTyID);
+    const Type* ArgTy = F->getFunctionType()->getParamType(0);
+    const Type* ArgTyPtr = PointerType::get(ArgTy);
+    Function* NF = M->getOrInsertFunction("llvm.va_end", 
+                                                 RetTy, ArgTyPtr, 0);
+    
+    for(Value::use_iterator I = F->use_begin(), E = F->use_end(); I != E;)
+      if (CallInst* CI = dyn_cast<CallInst>(*I++)) {
+        AllocaInst* bar = new AllocaInst(ArgTy, 0, "vaend.fix.1", CI);
+        new CallInst(NF, bar, "", CI);
+        CI->getParent()->getInstList().erase(CI);
+      }
+    F->setName("");
+  }
+  
+  if(Function* F = M->getNamedFunction("llvm.va_copy")) {
+    assert(F->arg_size() == 1 && "Obsolete va_copy takes 1 argument!");
+    //foo = vacopy(bar)
+    // ->
+    //a = alloca 1 of typeof(foo)
+    //vacopy(a, bar)
+    //foo = load a
+    
+    const Type* RetTy = Type::getPrimitiveType(Type::VoidTyID);
+    const Type* ArgTy = F->getFunctionType()->getReturnType();
+    const Type* ArgTyPtr = PointerType::get(ArgTy);
+    Function* NF = M->getOrInsertFunction("llvm.va_copy", 
+                                          RetTy, ArgTyPtr, ArgTy, 0);
+    
+    for(Value::use_iterator I = F->use_begin(), E = F->use_end(); I != E;)
+      if (CallInst* CI = dyn_cast<CallInst>(*I++)) {
+        AllocaInst* a = new AllocaInst(ArgTy, 0, "vacopy.fix.1", CI);
+        new CallInst(NF, a, CI->getOperand(1), "", CI);
+        Value* foo = new LoadInst(a, "vacopy.fix.2", CI);
+        CI->replaceAllUsesWith(foo);
+        CI->getParent()->getInstList().erase(CI);
+      }
+    F->setName("");
+  }
+  return MP;
+}
+
+//===----------------------------------------------------------------------===//
 // Wrapper functions
 //===----------------------------------------------------------------------===//
 
@@ -159,7 +253,8 @@
                                       unsigned Length,
                                       const std::string &ModuleID,
                                       BytecodeHandler* H ) {
-  return new BytecodeBufferReader(Buffer, Length, ModuleID, H);
+  return CheckVarargs(
+     new BytecodeBufferReader(Buffer, Length, ModuleID, H));
 }
 
 /// ParseBytecodeBuffer - Parse a given bytecode buffer
@@ -182,9 +277,9 @@
 ModuleProvider *llvm::getBytecodeModuleProvider(const std::string &Filename,
                                                 BytecodeHandler* H) {
   if (Filename != std::string("-"))        // Read from a file...
-    return new BytecodeFileReader(Filename,H);
+    return CheckVarargs(new BytecodeFileReader(Filename,H));
   else                                     // Read from stdin
-    return new BytecodeStdinReader(H);
+    return CheckVarargs(new BytecodeStdinReader(H));
 }
 
 /// ParseBytecodeFile - Parse the given bytecode file





From alenhar2 at cs.uiuc.edu  Sat Jun 18 13:35:10 2005
From: alenhar2 at cs.uiuc.edu (Andrew Lenharth)
Date: Sat, 18 Jun 2005 13:35:10 -0500
Subject: [llvm-commits] CVS: llvm/lib/Target/X86/X86ISelPattern.cpp
	X86ISelSimple.cpp 
Message-ID: <200506181835.NAA26134@zion.cs.uiuc.edu>



Changes in directory llvm/lib/Target/X86:

X86ISelPattern.cpp updated: 1.140 -> 1.141
X86ISelSimple.cpp updated: 1.319 -> 1.320
---
Log message:

core changes for varargs

---
Diffs of the changes:  (+51 -56)

 X86ISelPattern.cpp |   63 +++++++++++++++++++++++++++++++----------------------
 X86ISelSimple.cpp  |   44 ++++++++++---------------------------
 2 files changed, 51 insertions(+), 56 deletions(-)


Index: llvm/lib/Target/X86/X86ISelPattern.cpp
diff -u llvm/lib/Target/X86/X86ISelPattern.cpp:1.140 llvm/lib/Target/X86/X86ISelPattern.cpp:1.141
--- llvm/lib/Target/X86/X86ISelPattern.cpp:1.140	Fri Jun 17 08:23:32 2005
+++ llvm/lib/Target/X86/X86ISelPattern.cpp	Sat Jun 18 13:34:52 2005
@@ -176,12 +176,16 @@
                 SelectionDAG &DAG);
 
     virtual std::pair<SDOperand, SDOperand>
-    LowerVAStart(SDOperand Chain, SelectionDAG &DAG);
+    LowerVAStart(SDOperand Chain, SelectionDAG &DAG, SDOperand Dest);
 
     virtual std::pair<SDOperand,SDOperand>
-    LowerVAArgNext(bool isVANext, SDOperand Chain, SDOperand VAList,
+    LowerVAArgNext(SDOperand Chain, SDOperand VAList,
                    const Type *ArgTy, SelectionDAG &DAG);
 
+    virtual std::pair<SDOperand,SDOperand>
+    LowerVACopy(SDOperand Chain, SDOperand Src, SDOperand Dest, 
+                SelectionDAG &DAG);
+
     virtual std::pair<SDOperand, SDOperand>
     LowerFrameReturnAddress(bool isFrameAddr, SDOperand Chain, unsigned Depth,
                             SelectionDAG &DAG);
@@ -442,35 +446,44 @@
   return std::make_pair(ResultVal, Chain);
 }
 
-std::pair<SDOperand, SDOperand>
-X86TargetLowering::LowerVAStart(SDOperand Chain, SelectionDAG &DAG) {
-  // vastart just returns the address of the VarArgsFrameIndex slot.
-  return std::make_pair(DAG.getFrameIndex(VarArgsFrameIndex, MVT::i32), Chain);
+std::pair<SDOperand,SDOperand> 
+X86TargetLowering::LowerVAStart(SDOperand Chain, SelectionDAG &DAG, SDOperand Dest) {
+  // vastart just stores the address of the VarArgsFrameIndex slot.
+  SDOperand FR = DAG.getFrameIndex(VarArgsFrameIndex, MVT::i32);
+  SDOperand Result = DAG.getNode(ISD::STORE, MVT::Other, Chain, FR, Dest, DAG.getSrcValue(NULL));
+  return std::make_pair(Result, Result);
 }
 
-std::pair<SDOperand,SDOperand> X86TargetLowering::
-LowerVAArgNext(bool isVANext, SDOperand Chain, SDOperand VAList,
-               const Type *ArgTy, SelectionDAG &DAG) {
+std::pair<SDOperand,SDOperand> 
+X86TargetLowering::LowerVAArgNext(SDOperand Chain, SDOperand VAList,
+                                  const Type *ArgTy, SelectionDAG &DAG) {
   MVT::ValueType ArgVT = getValueType(ArgTy);
-  SDOperand Result;
-  if (!isVANext) {
-    Result = DAG.getLoad(ArgVT, DAG.getEntryNode(), VAList,
-                         DAG.getSrcValue(NULL));
-  } else {
-    unsigned Amt;
-    if (ArgVT == MVT::i32)
-      Amt = 4;
-    else {
-      assert((ArgVT == MVT::i64 || ArgVT == MVT::f64) &&
-             "Other types should have been promoted for varargs!");
-      Amt = 8;
-    }
-    Result = DAG.getNode(ISD::ADD, VAList.getValueType(), VAList,
-                         DAG.getConstant(Amt, VAList.getValueType()));
-  }
+  SDOperand Val = DAG.getLoad(MVT::i32, Chain, VAList, DAG.getSrcValue(NULL));
+  SDOperand Result = DAG.getLoad(ArgVT, Val.getValue(1), Val, DAG.getSrcValue(NULL));
+  unsigned Amt;
+  if (ArgVT == MVT::i32)
+    Amt = 4;
+  else {
+    assert((ArgVT == MVT::i64 || ArgVT == MVT::f64) &&
+           "Other types should have been promoted for varargs!");
+    Amt = 8;
+  }
+  Val = DAG.getNode(ISD::ADD, Val.getValueType(), Val,
+                    DAG.getConstant(Amt, Val.getValueType()));
+  Chain = DAG.getNode(ISD::STORE, MVT::Other, Chain,
+                      Val, VAList, DAG.getSrcValue(NULL));
   return std::make_pair(Result, Chain);
 }
 
+std::pair<SDOperand,SDOperand>
+X86TargetLowering::LowerVACopy(SDOperand Chain, SDOperand Src, 
+                               SDOperand Dest, SelectionDAG &DAG)
+{
+  SDOperand Result = DAG.getNode(ISD::STORE, MVT::Other, Chain,
+                                 Src, Dest, DAG.getSrcValue(NULL));
+  return std::make_pair(Result, Result);
+}
+
 //===----------------------------------------------------------------------===//
 //                    Fast Calling Convention implementation
 //===----------------------------------------------------------------------===//


Index: llvm/lib/Target/X86/X86ISelSimple.cpp
diff -u llvm/lib/Target/X86/X86ISelSimple.cpp:1.319 llvm/lib/Target/X86/X86ISelSimple.cpp:1.320
--- llvm/lib/Target/X86/X86ISelSimple.cpp:1.319	Fri May 13 16:48:20 2005
+++ llvm/lib/Target/X86/X86ISelSimple.cpp	Sat Jun 18 13:34:52 2005
@@ -232,7 +232,6 @@
     void visitShiftInst(ShiftInst &I);
     void visitPHINode(PHINode &I) {}      // PHI nodes handled by second pass
     void visitCastInst(CastInst &I);
-    void visitVANextInst(VANextInst &I);
     void visitVAArgInst(VAArgInst &I);
 
     void visitInstruction(Instruction &I) {
@@ -1838,12 +1837,14 @@
   unsigned TmpReg1, TmpReg2;
   switch (ID) {
   case Intrinsic::vastart:
+    //FIXME: store to first arg, don't return
     // Get the address of the first vararg value...
     TmpReg1 = getReg(CI);
     addFrameReference(BuildMI(BB, X86::LEA32r, 5, TmpReg1), VarArgsFrameIndex);
     return;
 
   case Intrinsic::vacopy:
+    //FIXME: copy val of second into first (which is a ptr)
     TmpReg1 = getReg(CI);
     TmpReg2 = getReg(CI.getOperand(1));
     BuildMI(BB, X86::MOV32rr, 1, TmpReg1).addReg(TmpReg2);
@@ -3745,38 +3746,12 @@
   abort();
 }
 
-/// visitVANextInst - Implement the va_next instruction...
-///
-void X86ISel::visitVANextInst(VANextInst &I) {
-  unsigned VAList = getReg(I.getOperand(0));
-  unsigned DestReg = getReg(I);
-
-  unsigned Size;
-  switch (I.getArgType()->getTypeID()) {
-  default:
-    std::cerr << I;
-    assert(0 && "Error: bad type for va_next instruction!");
-    return;
-  case Type::PointerTyID:
-  case Type::UIntTyID:
-  case Type::IntTyID:
-    Size = 4;
-    break;
-  case Type::ULongTyID:
-  case Type::LongTyID:
-  case Type::DoubleTyID:
-    Size = 8;
-    break;
-  }
-
-  // Increment the VAList pointer...
-  BuildMI(BB, X86::ADD32ri, 2, DestReg).addReg(VAList).addImm(Size);
-}
-
 void X86ISel::visitVAArgInst(VAArgInst &I) {
-  unsigned VAList = getReg(I.getOperand(0));
+  unsigned VAListPtr = getReg(I.getOperand(0));
   unsigned DestReg = getReg(I);
-
+  unsigned VAList = makeAnotherReg(Type::IntTy);
+  addDirectMem(BuildMI(BB, X86::MOV32rm, 4, VAList), VAListPtr);
+  unsigned Size;
   switch (I.getType()->getTypeID()) {
   default:
     std::cerr << I;
@@ -3785,17 +3760,24 @@
   case Type::PointerTyID:
   case Type::UIntTyID:
   case Type::IntTyID:
+    Size = 4;
     addDirectMem(BuildMI(BB, X86::MOV32rm, 4, DestReg), VAList);
     break;
   case Type::ULongTyID:
   case Type::LongTyID:
+    Size = 8;
     addDirectMem(BuildMI(BB, X86::MOV32rm, 4, DestReg), VAList);
     addRegOffset(BuildMI(BB, X86::MOV32rm, 4, DestReg+1), VAList, 4);
     break;
   case Type::DoubleTyID:
+    Size = 8;
     addDirectMem(BuildMI(BB, X86::FLD64m, 4, DestReg), VAList);
     break;
   }
+  // Increment the VAList pointer...
+  unsigned NP = makeAnotherReg(Type::IntTy);
+  BuildMI(BB, X86::ADD32ri, 2, NP).addReg(VAList).addSImm(Size);
+  addDirectMem(BuildMI(BB, X86::MOV32rm, 5), VAListPtr).addReg(VAList);
 }
 
 /// visitGetElementPtrInst - instruction-select GEP instructions





From alenhar2 at cs.uiuc.edu  Sat Jun 18 13:35:10 2005
From: alenhar2 at cs.uiuc.edu (Andrew Lenharth)
Date: Sat, 18 Jun 2005 13:35:10 -0500
Subject: [llvm-commits] CVS: llvm/lib/Transforms/Scalar/LICM.cpp 
Message-ID: <200506181835.NAA26135@zion.cs.uiuc.edu>



Changes in directory llvm/lib/Transforms/Scalar:

LICM.cpp updated: 1.73 -> 1.74
---
Log message:

core changes for varargs

---
Diffs of the changes:  (+1 -1)

 LICM.cpp |    2 +-
 1 files changed, 1 insertion(+), 1 deletion(-)


Index: llvm/lib/Transforms/Scalar/LICM.cpp
diff -u llvm/lib/Transforms/Scalar/LICM.cpp:1.73 llvm/lib/Transforms/Scalar/LICM.cpp:1.74
--- llvm/lib/Transforms/Scalar/LICM.cpp:1.73	Thu Apr 21 18:45:12 2005
+++ llvm/lib/Transforms/Scalar/LICM.cpp	Sat Jun 18 13:34:52 2005
@@ -386,7 +386,7 @@
 
   return isa<BinaryOperator>(I) || isa<ShiftInst>(I) || isa<CastInst>(I) ||
          isa<SelectInst>(I) ||
-         isa<GetElementPtrInst>(I) || isa<VANextInst>(I) || isa<VAArgInst>(I);
+         isa<GetElementPtrInst>(I) || isa<VAArgInst>(I);
 }
 
 /// isNotUsedInLoop - Return true if the only users of this instruction are





From alenhar2 at cs.uiuc.edu  Sat Jun 18 13:35:10 2005
From: alenhar2 at cs.uiuc.edu (Andrew Lenharth)
Date: Sat, 18 Jun 2005 13:35:10 -0500
Subject: [llvm-commits] CVS: llvm/lib/Target/CBackend/Writer.cpp 
Message-ID: <200506181835.NAA26111@zion.cs.uiuc.edu>



Changes in directory llvm/lib/Target/CBackend:

Writer.cpp updated: 1.238 -> 1.239
---
Log message:

core changes for varargs

---
Diffs of the changes:  (+13 -18)

 Writer.cpp |   31 +++++++++++++------------------
 1 files changed, 13 insertions(+), 18 deletions(-)


Index: llvm/lib/Target/CBackend/Writer.cpp
diff -u llvm/lib/Target/CBackend/Writer.cpp:1.238 llvm/lib/Target/CBackend/Writer.cpp:1.239
--- llvm/lib/Target/CBackend/Writer.cpp:1.238	Fri May  6 01:58:42 2005
+++ llvm/lib/Target/CBackend/Writer.cpp	Sat Jun 18 13:34:52 2005
@@ -145,7 +145,7 @@
       // emit it inline where it would go.
       if (I.getType() == Type::VoidTy || !I.hasOneUse() ||
           isa<TerminatorInst>(I) || isa<CallInst>(I) || isa<PHINode>(I) ||
-          isa<LoadInst>(I) || isa<VAArgInst>(I) || isa<VANextInst>(I))
+          isa<LoadInst>(I) || isa<VAArgInst>(I))
         // Don't inline a load across a store or other bad things!
         return false;
 
@@ -196,7 +196,6 @@
     void visitLoadInst  (LoadInst   &I);
     void visitStoreInst (StoreInst  &I);
     void visitGetElementPtrInst(GetElementPtrInst &I);
-    void visitVANextInst(VANextInst &I);
     void visitVAArgInst (VAArgInst &I);
 
     void visitInstruction(Instruction &I) {
@@ -1469,7 +1468,10 @@
       case Intrinsic::vastart:
         Out << "0; ";
 
-        Out << "va_start(*(va_list*)&" << Mang->getValueName(&I) << ", ";
+        //        Out << "va_start(*(va_list*)&" << Mang->getValueName(&I) << ", ";
+        Out << "va_start(*(va_list*)";
+        writeOperand(I.getOperand(1));
+        Out << ", ";
         // Output the last argument to the enclosing function...
         if (I.getParent()->getParent()->arg_empty()) {
           std::cerr << "The C backend does not currently support zero "
@@ -1482,7 +1484,7 @@
         return;
       case Intrinsic::vaend:
         if (!isa<ConstantPointerNull>(I.getOperand(1))) {
-          Out << "va_end(*(va_list*)&";
+          Out << "0; va_end(*(va_list*)";
           writeOperand(I.getOperand(1));
           Out << ')';
         } else {
@@ -1490,10 +1492,11 @@
         }
         return;
       case Intrinsic::vacopy:
-        Out << "0;";
-        Out << "va_copy(*(va_list*)&" << Mang->getValueName(&I) << ", ";
-        Out << "*(va_list*)&";
+        Out << "0; ";
+        Out << "va_copy(*(va_list*)";
         writeOperand(I.getOperand(1));
+        Out << ", *(va_list*)&";
+        writeOperand(I.getOperand(2));
         Out << ')';
         return;
       case Intrinsic::returnaddress:
@@ -1710,20 +1713,12 @@
                           gep_type_end(I));
 }
 
-void CWriter::visitVANextInst(VANextInst &I) {
-  Out << Mang->getValueName(I.getOperand(0));
-  Out << ";  va_arg(*(va_list*)&" << Mang->getValueName(&I) << ", ";
-  printType(Out, I.getArgType());
-  Out << ')';
-}
-
 void CWriter::visitVAArgInst(VAArgInst &I) {
-  Out << "0;\n";
-  Out << "{ va_list Tmp; va_copy(Tmp, *(va_list*)&";
+  Out << "va_arg(*(va_list*)";
   writeOperand(I.getOperand(0));
-  Out << ");\n  " << Mang->getValueName(&I) << " = va_arg(Tmp, ";
+  Out << ", ";
   printType(Out, I.getType());
-  Out << ");\n  va_end(Tmp); }";
+  Out << ");\n ";
 }
 
 //===----------------------------------------------------------------------===//





From alenhar2 at cs.uiuc.edu  Sat Jun 18 13:35:10 2005
From: alenhar2 at cs.uiuc.edu (Andrew Lenharth)
Date: Sat, 18 Jun 2005 13:35:10 -0500
Subject: [llvm-commits] CVS: llvm/lib/Target/IA64/IA64ISelPattern.cpp 
Message-ID: <200506181835.NAA26113@zion.cs.uiuc.edu>



Changes in directory llvm/lib/Target/IA64:

IA64ISelPattern.cpp updated: 1.44 -> 1.45
---
Log message:

core changes for varargs

---
Diffs of the changes:  (+35 -21)

 IA64ISelPattern.cpp |   56 ++++++++++++++++++++++++++++++++--------------------
 1 files changed, 35 insertions(+), 21 deletions(-)


Index: llvm/lib/Target/IA64/IA64ISelPattern.cpp
diff -u llvm/lib/Target/IA64/IA64ISelPattern.cpp:1.44 llvm/lib/Target/IA64/IA64ISelPattern.cpp:1.45
--- llvm/lib/Target/IA64/IA64ISelPattern.cpp:1.44	Fri May 20 06:39:17 2005
+++ llvm/lib/Target/IA64/IA64ISelPattern.cpp	Sat Jun 18 13:34:52 2005
@@ -114,12 +114,16 @@
                 SelectionDAG &DAG);
 
     virtual std::pair<SDOperand, SDOperand>
-    LowerVAStart(SDOperand Chain, SelectionDAG &DAG);
+    LowerVAStart(SDOperand Chain, SelectionDAG &DAG, SDOperand Dest);
 
     virtual std::pair<SDOperand,SDOperand>
-    LowerVAArgNext(bool isVANext, SDOperand Chain, SDOperand VAList,
+    LowerVAArgNext(SDOperand Chain, SDOperand VAList,
                    const Type *ArgTy, SelectionDAG &DAG);
 
+    virtual std::pair<SDOperand,SDOperand>
+    LowerVACopy(SDOperand Chain, SDOperand Src, SDOperand Dest, 
+                SelectionDAG &DAG);
+
     virtual std::pair<SDOperand, SDOperand>
     LowerFrameReturnAddress(bool isFrameAddr, SDOperand Chain, unsigned Depth,
                             SelectionDAG &DAG);
@@ -380,34 +384,44 @@
 }
 
 std::pair<SDOperand, SDOperand>
-IA64TargetLowering::LowerVAStart(SDOperand Chain, SelectionDAG &DAG) {
-  // vastart just returns the address of the VarArgsFrameIndex slot.
-  return std::make_pair(DAG.getFrameIndex(VarArgsFrameIndex, MVT::i64), Chain);
+IA64TargetLowering::LowerVAStart(SDOperand Chain, SelectionDAG &DAG, SDOperand Dest) {
+  // vastart just stores the address of the VarArgsFrameIndex slot.
+  SDOperand FR = DAG.getFrameIndex(VarArgsFrameIndex, MVT::i64);
+  SDOperand Result = DAG.getNode(ISD::STORE, MVT::Other, Chain, FR, Dest, DAG.getSrcValue(NULL));
+  return std::make_pair(Result, Result);
 }
 
 std::pair<SDOperand,SDOperand> IA64TargetLowering::
-LowerVAArgNext(bool isVANext, SDOperand Chain, SDOperand VAList,
+LowerVAArgNext(SDOperand Chain, SDOperand VAList,
                const Type *ArgTy, SelectionDAG &DAG) {
 
   MVT::ValueType ArgVT = getValueType(ArgTy);
-  SDOperand Result;
-  if (!isVANext) {
-    Result = DAG.getLoad(ArgVT, DAG.getEntryNode(), VAList, DAG.getSrcValue(NULL));
-  } else {
-    unsigned Amt;
-    if (ArgVT == MVT::i32 || ArgVT == MVT::f32)
-      Amt = 8;
-    else {
-      assert((ArgVT == MVT::i64 || ArgVT == MVT::f64) &&
-             "Other types should have been promoted for varargs!");
-      Amt = 8;
-    }
-    Result = DAG.getNode(ISD::ADD, VAList.getValueType(), VAList,
-                         DAG.getConstant(Amt, VAList.getValueType()));
-  }
+  SDOperand Val = DAG.getLoad(MVT::i64, Chain, VAList, DAG.getSrcValue(NULL));
+  SDOperand Result = DAG.getLoad(ArgVT, DAG.getEntryNode(), Val, DAG.getSrcValue(NULL));
+  unsigned Amt;
+  if (ArgVT == MVT::i32 || ArgVT == MVT::f32)
+    Amt = 8;
+  else {
+    assert((ArgVT == MVT::i64 || ArgVT == MVT::f64) &&
+           "Other types should have been promoted for varargs!");
+    Amt = 8;
+  }
+  Val = DAG.getNode(ISD::ADD, Val.getValueType(), Val, 
+                    DAG.getConstant(Amt, Val.getValueType()));
+  Chain = DAG.getNode(ISD::STORE, MVT::Other, Chain,
+                      Val, VAList, DAG.getSrcValue(NULL));
   return std::make_pair(Result, Chain);
 }
 
+std::pair<SDOperand,SDOperand>
+IA64TargetLowering::LowerVACopy(SDOperand Chain, SDOperand Src, 
+                                SDOperand Dest, SelectionDAG &DAG)
+{
+  SDOperand Result = DAG.getNode(ISD::STORE, MVT::Other, Chain,
+                                 Src, Dest, DAG.getSrcValue(NULL));
+  return std::make_pair(Result, Result);
+}
+
 std::pair<SDOperand, SDOperand> IA64TargetLowering::
 LowerFrameReturnAddress(bool isFrameAddress, SDOperand Chain, unsigned Depth,
                         SelectionDAG &DAG) {





From alenhar2 at cs.uiuc.edu  Sat Jun 18 13:46:51 2005
From: alenhar2 at cs.uiuc.edu (Andrew Lenharth)
Date: Sat, 18 Jun 2005 13:46:51 -0500
Subject: [llvm-commits] CVS: llvm/lib/Target/SparcV9/SparcV9.burg.in
	SparcV9BurgISel.cpp 
Message-ID: <200506181846.NAA26201@zion.cs.uiuc.edu>



Changes in directory llvm/lib/Target/SparcV9:

SparcV9.burg.in updated: 1.14 -> 1.15
SparcV9BurgISel.cpp updated: 1.19 -> 1.20
---
Log message:

OK, at least get rid of old stuff, and mark what needs to be fixed for V9

---
Diffs of the changes:  (+4 -2)

 SparcV9.burg.in     |    2 --
 SparcV9BurgISel.cpp |    4 ++++
 2 files changed, 4 insertions(+), 2 deletions(-)


Index: llvm/lib/Target/SparcV9/SparcV9.burg.in
diff -u llvm/lib/Target/SparcV9/SparcV9.burg.in:1.14 llvm/lib/Target/SparcV9/SparcV9.burg.in:1.15
--- llvm/lib/Target/SparcV9/SparcV9.burg.in:1.14	Sun Oct 17 00:37:47 2004
+++ llvm/lib/Target/SparcV9/SparcV9.burg.in	Sat Jun 18 13:46:40 2005
@@ -96,7 +96,6 @@
 %term Call=CallOPCODE
 %term Shl=ShlOPCODE
 %term Shr=ShrOPCODE
-%term VANext=VANextOPCODE
 %term VAArg=VAArgOPCODE
 		/* 33...46 are unused */
     /*
@@ -268,7 +267,6 @@
 reg:	Shl(reg,reg)		=   62 (20);	/* 1 for issue restrictions */
 reg:	Shr(reg,reg)		=   63 (20);	/* 1 for issue restrictions */
 reg:	Phi(reg,reg)		=   64 (0);
-reg:	VANext(reg)		=   65 (40);	/* incr stack slot pointer */
 reg:	VAArg(reg)		=   66 (40);	/* get a vararg */
 
 	/*


Index: llvm/lib/Target/SparcV9/SparcV9BurgISel.cpp
diff -u llvm/lib/Target/SparcV9/SparcV9BurgISel.cpp:1.19 llvm/lib/Target/SparcV9/SparcV9BurgISel.cpp:1.20
--- llvm/lib/Target/SparcV9/SparcV9BurgISel.cpp:1.19	Sat Jun 18 12:37:34 2005
+++ llvm/lib/Target/SparcV9/SparcV9BurgISel.cpp	Sat Jun 18 13:46:40 2005
@@ -4216,6 +4216,8 @@
       case 64:	// reg:   Phi(reg,reg)
         break;                          // don't forward the value
 
+#if 0
+//FIXME: new VAArg support
       case 65:	// reg:   VANext(reg):  the va_next(va_list, type) instruction
       { // Increment the va_list pointer register according to the type.
         // All LLVM argument types are <= 64 bits, so use one doubleword.
@@ -4227,7 +4229,9 @@
                        addSImm(argSize).addRegDef(vaNextI));
         break;
       }
+#endif
 
+//FIXME: new VAArg support
       case 66:	// reg:   VAArg (reg): the va_arg instruction
       { // Load argument from stack using current va_list pointer value.
         // Use 64-bit load for all non-FP args, and LDDF or double for FP.





From reid at x10sys.com  Sat Jun 18 14:58:21 2005
From: reid at x10sys.com (Reid Spencer)
Date: Sat, 18 Jun 2005 12:58:21 -0700
Subject: [llvm-commits] CVS: llvm/test/Feature/varargs_new.ll
In-Reply-To: <200506181830.NAA25879@zion.cs.uiuc.edu>
References: <200506181830.NAA25879@zion.cs.uiuc.edu>
Message-ID: <1119124701.16576.90.camel@bashful.x10sys.com>

I get this with your changes:

Running /proj/llvm/build/../llvm/test/Feature/dg.exp ...
FAIL: /proj/llvm/build/../llvm/test/Feature/varargs_new.ll:
llvm-as: /proj/llvm/build/../llvm/lib/AsmParser/llvmAsmParser.y:740:
llvm::Module* RunParser(llvm::Module*): Assertion `F->arg.llvm-as
((anonymous namespace)::PrintStackTrace()+0x1a)[0x82c4142]
llvm-as((anonymous namespace)::SignalHandler(int)+0xd3)[0x82c440b]
/lib/tls/libc.so.6[0xaef8c8]
/lib/ld-linux.so.2[0xa587a2]
/lib/tls/libc.so.6(gsignal+0x55)[0xaef7d5]
/lib/tls/libc.so.6(abort+0xe9)[0xaf1149]
/lib/tls/libc.so.6(__assert_fail+0x101)[0xae8db1]
llvm-as[0x81c0ee0]
llvm-as(llvm::RunVMAsmParser(std::basic_string<char,
std::char_traits<char>, std::allocator<char> > const&,
_IO_FILE*)+0x73)[0]llvm-as(llvm::ParseAssemblyFile
(std::basic_string<char, std::char_traits<char>, std::allocator<char> >
const&)+0x1c1)[0x81afa4]llvm-as(main+0x5a)[0x81ab16e]
/lib/tls/libc.so.6(__libc_start_main+0xd3)[0xadce23]
llvm-as(__gxx_personality_v0+0xd1)[0x81ab091]
llvm-dis: Standard Input empty!
0a1,3
; ModuleID = '<stdin>'
implementation   ; Functions:

Reid

On Sat, 2005-06-18 at 13:30 -0500, Andrew Lenharth wrote:
> 
> Changes in directory llvm/test/Feature:
> 
> varargs_new.ll added (r1.1)
> ---
> Log message:
> 
> new vararg test
> 
> ---
> Diffs of the changes:  (+33 -0)
> 
>  varargs_new.ll |   33 +++++++++++++++++++++++++++++++++
>  1 files changed, 33 insertions(+)
> 
> 
> Index: llvm/test/Feature/varargs_new.ll
> diff -c /dev/null llvm/test/Feature/varargs_new.ll:1.1
> *** /dev/null	Sat Jun 18 13:30:47 2005
> --- llvm/test/Feature/varargs_new.ll	Sat Jun 18 13:30:37 2005
> ***************
> *** 0 ****
> --- 1,33 ----
> + ; RUN: llvm-as %s -o - | llvm-dis > %t1.ll
> + ; RUN: llvm-as %t1.ll -o - | llvm-dis > %t2.ll
> + ; RUN: diff %t1.ll %t2.ll
> + 
> + ; Demonstrate all of the variable argument handling intrinsic functions plus 
> + ; the va_arg instruction.
> + 
> + implementation   ; Functions:
> + declare void %llvm.va_start(sbyte**)
> + declare void %llvm.va_copy(sbyte**, sbyte*)
> + declare void %llvm.va_end(sbyte**)
> + 
> + int %test(int %X, ...) {
> +         ; Allocate two va_list items.  On this target, va_list is of type sbyte*
> +         %ap = alloca sbyte*             ; <sbyte**> [#uses=4]
> +         %aq = alloca sbyte*             ; <sbyte**> [#uses=2]
> + 
> +         ; Initialize variable argument processing
> +         call void %llvm.va_start(sbyte** %ap)
> + 
> +         ; Read a single integer argument
> +         %tmp = vaarg sbyte** %ap, int           ; <int> [#uses=1]
> + 
> +         ; Demonstrate usage of llvm.va_copy and llvm_va_end
> +         %apv = load sbyte** %ap         ; <sbyte*> [#uses=1]
> +         call void %llvm.va_copy(sbyte** %aq, sbyte* %apv)
> +         call void %llvm.va_end(sbyte** %aq)
> + 
> +         ; Stop processing of arguments.
> +         call void %llvm.va_end(sbyte** %ap)
> +         ret int %tmp
> + 
> + }
> 
> 
> 
> _______________________________________________
> llvm-commits mailing list
> llvm-commits at cs.uiuc.edu
> http://mail.cs.uiuc.edu/mailman/listinfo/llvm-commits
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From reid at x10sys.com  Sat Jun 18 15:27:44 2005
From: reid at x10sys.com (Reid Spencer)
Date: Sat, 18 Jun 2005 15:27:44 -0500
Subject: [llvm-commits] CVS: llvm/test/Feature/varargs_new.ll 
Message-ID: <200506182027.PAA26490@zion.cs.uiuc.edu>



Changes in directory llvm/test/Feature:

varargs_new.ll updated: 1.1 -> 1.2
---
Log message:

Fix this test case to actually test the new va_arg instruction not the
old vaarg instruction.


---
Diffs of the changes:  (+1 -1)

 varargs_new.ll |    2 +-
 1 files changed, 1 insertion(+), 1 deletion(-)


Index: llvm/test/Feature/varargs_new.ll
diff -u llvm/test/Feature/varargs_new.ll:1.1 llvm/test/Feature/varargs_new.ll:1.2
--- llvm/test/Feature/varargs_new.ll:1.1	Sat Jun 18 13:30:37 2005
+++ llvm/test/Feature/varargs_new.ll	Sat Jun 18 15:27:32 2005
@@ -19,7 +19,7 @@
         call void %llvm.va_start(sbyte** %ap)
 
         ; Read a single integer argument
-        %tmp = vaarg sbyte** %ap, int           ; <int> [#uses=1]
+        %tmp = va_arg sbyte** %ap, int           ; <int> [#uses=1]
 
         ; Demonstrate usage of llvm.va_copy and llvm_va_end
         %apv = load sbyte** %ap         ; <sbyte*> [#uses=1]





From reid at x10sys.com  Sat Jun 18 15:29:39 2005
From: reid at x10sys.com (Reid Spencer)
Date: Sat, 18 Jun 2005 13:29:39 -0700
Subject: [llvm-commits] CVS: llvm/test/Feature/varargs_new.ll
In-Reply-To: <1119124701.16576.90.camel@bashful.x10sys.com>
References: <200506181830.NAA25879@zion.cs.uiuc.edu>
	<1119124701.16576.90.camel@bashful.x10sys.com>
Message-ID: <1119126579.16576.92.camel@bashful.x10sys.com>

Andrew,

I think I fixed this, but I'd like you to verify my patch, please:

http://mail.cs.uiuc.edu/pipermail/llvm-commits/Week-of-Mon-20050613/026759.html

Thanks,

Reid.

On Sat, 2005-06-18 at 12:58 -0700, Reid Spencer wrote:
> I get this with your changes:
> 
> Running /proj/llvm/build/../llvm/test/Feature/dg.exp ...
> FAIL: /proj/llvm/build/../llvm/test/Feature/varargs_new.ll:
> llvm-as: /proj/llvm/build/../llvm/lib/AsmParser/llvmAsmParser.y:740:
> llvm::Module* RunParser(llvm::Module*): Assertion `F->arg.llvm-as
> ((anonymous namespace)::PrintStackTrace()+0x1a)[0x82c4142]
> llvm-as((anonymous namespace)::SignalHandler(int)+0xd3)[0x82c440b]
> /lib/tls/libc.so.6[0xaef8c8]
> /lib/ld-linux.so.2[0xa587a2]
> /lib/tls/libc.so.6(gsignal+0x55)[0xaef7d5]
> /lib/tls/libc.so.6(abort+0xe9)[0xaf1149]
> /lib/tls/libc.so.6(__assert_fail+0x101)[0xae8db1]
> llvm-as[0x81c0ee0]
> llvm-as(llvm::RunVMAsmParser(std::basic_string<char,
> std::char_traits<char>, std::allocator<char> > const&,
> _IO_FILE*)+0x73)[0]llvm-as(llvm::ParseAssemblyFile
> (std::basic_string<char, std::char_traits<char>, std::allocator<char> >
> const&)+0x1c1)[0x81afa4]llvm-as(main+0x5a)[0x81ab16e]
> /lib/tls/libc.so.6(__libc_start_main+0xd3)[0xadce23]
> llvm-as(__gxx_personality_v0+0xd1)[0x81ab091]
> llvm-dis: Standard Input empty!
> 0a1,3
> ; ModuleID = '<stdin>'
> implementation   ; Functions:
> 
> Reid
> 
> On Sat, 2005-06-18 at 13:30 -0500, Andrew Lenharth wrote:
> > 
> > Changes in directory llvm/test/Feature:
> > 
> > varargs_new.ll added (r1.1)
> > ---
> > Log message:
> > 
> > new vararg test
> > 
> > ---
> > Diffs of the changes:  (+33 -0)
> > 
> >  varargs_new.ll |   33 +++++++++++++++++++++++++++++++++
> >  1 files changed, 33 insertions(+)
> > 
> > 
> > Index: llvm/test/Feature/varargs_new.ll
> > diff -c /dev/null llvm/test/Feature/varargs_new.ll:1.1
> > *** /dev/null	Sat Jun 18 13:30:47 2005
> > --- llvm/test/Feature/varargs_new.ll	Sat Jun 18 13:30:37 2005
> > ***************
> > *** 0 ****
> > --- 1,33 ----
> > + ; RUN: llvm-as %s -o - | llvm-dis > %t1.ll
> > + ; RUN: llvm-as %t1.ll -o - | llvm-dis > %t2.ll
> > + ; RUN: diff %t1.ll %t2.ll
> > + 
> > + ; Demonstrate all of the variable argument handling intrinsic functions plus 
> > + ; the va_arg instruction.
> > + 
> > + implementation   ; Functions:
> > + declare void %llvm.va_start(sbyte**)
> > + declare void %llvm.va_copy(sbyte**, sbyte*)
> > + declare void %llvm.va_end(sbyte**)
> > + 
> > + int %test(int %X, ...) {
> > +         ; Allocate two va_list items.  On this target, va_list is of type sbyte*
> > +         %ap = alloca sbyte*             ; <sbyte**> [#uses=4]
> > +         %aq = alloca sbyte*             ; <sbyte**> [#uses=2]
> > + 
> > +         ; Initialize variable argument processing
> > +         call void %llvm.va_start(sbyte** %ap)
> > + 
> > +         ; Read a single integer argument
> > +         %tmp = vaarg sbyte** %ap, int           ; <int> [#uses=1]
> > + 
> > +         ; Demonstrate usage of llvm.va_copy and llvm_va_end
> > +         %apv = load sbyte** %ap         ; <sbyte*> [#uses=1]
> > +         call void %llvm.va_copy(sbyte** %aq, sbyte* %apv)
> > +         call void %llvm.va_end(sbyte** %aq)
> > + 
> > +         ; Stop processing of arguments.
> > +         call void %llvm.va_end(sbyte** %ap)
> > +         ret int %tmp
> > + 
> > + }
> > 
> > 
> > 
> > _______________________________________________
> > llvm-commits mailing list
> > llvm-commits at cs.uiuc.edu
> > http://mail.cs.uiuc.edu/mailman/listinfo/llvm-commits
> _______________________________________________
> llvm-commits mailing list
> llvm-commits at cs.uiuc.edu
> http://mail.cs.uiuc.edu/mailman/listinfo/llvm-commits
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From reid at x10sys.com  Sat Jun 18 16:02:08 2005
From: reid at x10sys.com (Reid Spencer)
Date: Sat, 18 Jun 2005 14:02:08 -0700
Subject: [llvm-commits] CVS: llvm/test/Feature/varargs_new.ll
In-Reply-To: <1119126579.16576.92.camel@bashful.x10sys.com>
References: <200506181830.NAA25879@zion.cs.uiuc.edu>
	<1119124701.16576.90.camel@bashful.x10sys.com>
	<1119126579.16576.92.camel@bashful.x10sys.com>
Message-ID: <1119128528.16576.96.camel@bashful.x10sys.com>

Andrew,

One more thought on this. You should probably write two XFAIL tests for
this feature that test (a) whether old style vaarg is mixed with new
style intrinsics and (b) whether new style va_arg is mixed with old
style intrinsics. This is just to make sure that that the assembler
correctly rejects programs that mix the styles.

Reid.
 
On Sat, 2005-06-18 at 13:29 -0700, Reid Spencer wrote:
> Andrew,
> 
> I think I fixed this, but I'd like you to verify my patch, please:
> 
> http://mail.cs.uiuc.edu/pipermail/llvm-commits/Week-of-Mon-20050613/026759.html
> 
> Thanks,
> 
> Reid.
> 
> On Sat, 2005-06-18 at 12:58 -0700, Reid Spencer wrote:
> > I get this with your changes:
> > 
> > Running /proj/llvm/build/../llvm/test/Feature/dg.exp ...
> > FAIL: /proj/llvm/build/../llvm/test/Feature/varargs_new.ll:
> > llvm-as: /proj/llvm/build/../llvm/lib/AsmParser/llvmAsmParser.y:740:
> > llvm::Module* RunParser(llvm::Module*): Assertion `F->arg.llvm-as
> > ((anonymous namespace)::PrintStackTrace()+0x1a)[0x82c4142]
> > llvm-as((anonymous namespace)::SignalHandler(int)+0xd3)[0x82c440b]
> > /lib/tls/libc.so.6[0xaef8c8]
> > /lib/ld-linux.so.2[0xa587a2]
> > /lib/tls/libc.so.6(gsignal+0x55)[0xaef7d5]
> > /lib/tls/libc.so.6(abort+0xe9)[0xaf1149]
> > /lib/tls/libc.so.6(__assert_fail+0x101)[0xae8db1]
> > llvm-as[0x81c0ee0]
> > llvm-as(llvm::RunVMAsmParser(std::basic_string<char,
> > std::char_traits<char>, std::allocator<char> > const&,
> > _IO_FILE*)+0x73)[0]llvm-as(llvm::ParseAssemblyFile
> > (std::basic_string<char, std::char_traits<char>, std::allocator<char> >
> > const&)+0x1c1)[0x81afa4]llvm-as(main+0x5a)[0x81ab16e]
> > /lib/tls/libc.so.6(__libc_start_main+0xd3)[0xadce23]
> > llvm-as(__gxx_personality_v0+0xd1)[0x81ab091]
> > llvm-dis: Standard Input empty!
> > 0a1,3
> > ; ModuleID = '<stdin>'
> > implementation   ; Functions:
> > 
> > Reid
> > 
> > On Sat, 2005-06-18 at 13:30 -0500, Andrew Lenharth wrote:
> > > 
> > > Changes in directory llvm/test/Feature:
> > > 
> > > varargs_new.ll added (r1.1)
> > > ---
> > > Log message:
> > > 
> > > new vararg test
> > > 
> > > ---
> > > Diffs of the changes:  (+33 -0)
> > > 
> > >  varargs_new.ll |   33 +++++++++++++++++++++++++++++++++
> > >  1 files changed, 33 insertions(+)
> > > 
> > > 
> > > Index: llvm/test/Feature/varargs_new.ll
> > > diff -c /dev/null llvm/test/Feature/varargs_new.ll:1.1
> > > *** /dev/null	Sat Jun 18 13:30:47 2005
> > > --- llvm/test/Feature/varargs_new.ll	Sat Jun 18 13:30:37 2005
> > > ***************
> > > *** 0 ****
> > > --- 1,33 ----
> > > + ; RUN: llvm-as %s -o - | llvm-dis > %t1.ll
> > > + ; RUN: llvm-as %t1.ll -o - | llvm-dis > %t2.ll
> > > + ; RUN: diff %t1.ll %t2.ll
> > > + 
> > > + ; Demonstrate all of the variable argument handling intrinsic functions plus 
> > > + ; the va_arg instruction.
> > > + 
> > > + implementation   ; Functions:
> > > + declare void %llvm.va_start(sbyte**)
> > > + declare void %llvm.va_copy(sbyte**, sbyte*)
> > > + declare void %llvm.va_end(sbyte**)
> > > + 
> > > + int %test(int %X, ...) {
> > > +         ; Allocate two va_list items.  On this target, va_list is of type sbyte*
> > > +         %ap = alloca sbyte*             ; <sbyte**> [#uses=4]
> > > +         %aq = alloca sbyte*             ; <sbyte**> [#uses=2]
> > > + 
> > > +         ; Initialize variable argument processing
> > > +         call void %llvm.va_start(sbyte** %ap)
> > > + 
> > > +         ; Read a single integer argument
> > > +         %tmp = vaarg sbyte** %ap, int           ; <int> [#uses=1]
> > > + 
> > > +         ; Demonstrate usage of llvm.va_copy and llvm_va_end
> > > +         %apv = load sbyte** %ap         ; <sbyte*> [#uses=1]
> > > +         call void %llvm.va_copy(sbyte** %aq, sbyte* %apv)
> > > +         call void %llvm.va_end(sbyte** %aq)
> > > + 
> > > +         ; Stop processing of arguments.
> > > +         call void %llvm.va_end(sbyte** %ap)
> > > +         ret int %tmp
> > > + 
> > > + }
> > > 
> > > 
> > > 
> > > _______________________________________________
> > > llvm-commits mailing list
> > > llvm-commits at cs.uiuc.edu
> > > http://mail.cs.uiuc.edu/mailman/listinfo/llvm-commits
> > _______________________________________________
> > llvm-commits mailing list
> > llvm-commits at cs.uiuc.edu
> > http://mail.cs.uiuc.edu/mailman/listinfo/llvm-commits
> _______________________________________________
> llvm-commits mailing list
> llvm-commits at cs.uiuc.edu
> http://mail.cs.uiuc.edu/mailman/listinfo/llvm-commits
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From reid at x10sys.com  Sat Jun 18 16:11:31 2005
From: reid at x10sys.com (Reid Spencer)
Date: Sat, 18 Jun 2005 16:11:31 -0500
Subject: [llvm-commits] CVS: llvm-gcc/gcc/llvm-expand.c
	llvm-representation.c llvm-representation.h llvm-types.c 
Message-ID: <200506182111.QAA26657@zion.cs.uiuc.edu>



Changes in directory llvm-gcc/gcc:

llvm-expand.c updated: 1.101 -> 1.102
llvm-representation.c updated: 1.17 -> 1.18
llvm-representation.h updated: 1.15 -> 1.16
llvm-types.c updated: 1.22 -> 1.23
---
Log message:

Clean up some code (no functional changes):
* Correct constructs that GCC 4.0.0 errors on such as functions with no
  return type, inconsistent constness, and under-specified static 
  initializers
* Wrap some long lines
* Comment out some variables that are not used.


---
Diffs of the changes:  (+31 -30)

 llvm-expand.c         |   11 ++++++-----
 llvm-representation.c |   10 +++++-----
 llvm-representation.h |    8 ++++----
 llvm-types.c          |   32 ++++++++++++++++----------------
 4 files changed, 31 insertions(+), 30 deletions(-)


Index: llvm-gcc/gcc/llvm-expand.c
diff -u llvm-gcc/gcc/llvm-expand.c:1.101 llvm-gcc/gcc/llvm-expand.c:1.102
--- llvm-gcc/gcc/llvm-expand.c:1.101	Wed Jun 15 17:44:27 2005
+++ llvm-gcc/gcc/llvm-expand.c	Sat Jun 18 16:11:19 2005
@@ -160,8 +160,9 @@
   return I;
 }
 
-static inline llvm_value *cast_if_type_not_equal(llvm_function *Fn,
-                                                 llvm_value *V, llvm_type *Ty) {
+static inline llvm_value *
+cast_if_type_not_equal(llvm_function *Fn,
+                       llvm_value *V, const llvm_type *Ty) {
   llvm_instruction *Cast;
   if (V->Ty == Ty) return V;  /* No cast required? */
 
@@ -2645,7 +2646,7 @@
  */
 static void llvm_expand_anon_union_decl(llvm_function *Fn, tree decl,
                                         tree decl_elts) {
-  llvm_nesting *InnermostCleanupScope = Fn->ExpandInfo->InnermostBlockScope;
+  /*llvm_nesting *InnermostCleanupScope = Fn->ExpandInfo->InnermostBlockScope;*/
   llvm_value *x;
   tree t;
 
@@ -7438,7 +7439,7 @@
    assembler symbol name. */
 extern int decode_reg_name(const char *);
 void llvm_make_decl_llvm(tree decl, const char *asmspec) {
-  int top_level = (DECL_CONTEXT (decl) == NULL_TREE);
+  /*int top_level = (DECL_CONTEXT (decl) == NULL_TREE); */
   const char *name = 0;
   int reg_number;
 
@@ -8144,7 +8145,7 @@
 
 
 /* Emit intrinsics to mark variable declarations */
-static void llvm_emit_dbg_declare(llvm_function *Fn, tree t){
+static void llvm_emit_dbg_declare(llvm_function * Fn, tree t){
   /* FIXME: need to actually do this.  
 
   See llvm_emit_dbg_stoppoint for an example of how to create a new


Index: llvm-gcc/gcc/llvm-representation.c
diff -u llvm-gcc/gcc/llvm-representation.c:1.17 llvm-gcc/gcc/llvm-representation.c:1.18
--- llvm-gcc/gcc/llvm-representation.c:1.17	Wed Feb 23 11:33:28 2005
+++ llvm-gcc/gcc/llvm-representation.c	Sat Jun 18 16:11:20 2005
@@ -185,12 +185,12 @@
    subsequent values get increasing identifiers.  The name and type of a value
    should not be changed after they are constructed.
  */
-void llvm_value_construct(llvm_value *Val, struct llvm_type *Type,
+void llvm_value_construct(llvm_value *Val, const struct llvm_type *Type,
 			  const char *Name, enum ValueType VT) {
   llvm_value *GlobalVal;
   Val->VTy = VT;
   GlobalVal = llvm_value_is_global(Val) ? Val : 0;
-  Val->Ty = Type;
+  Val->Ty = (struct llvm_type*) Type;
   if (Name[0] == '*') ++Name;
   Val->Name = Name[0] ? IdentifierTableGetName(Name, GlobalVal) : xstrdup(Name);
 }
@@ -267,7 +267,7 @@
 
 /* llvm_constant implementation ********************************************
  */
-void llvm_constant_construct(llvm_constant *C, struct llvm_type *Ty,
+void llvm_constant_construct(llvm_constant *C, const struct llvm_type *Ty,
                              const char *Name, enum ValueType VT,
                              const char *Rep) {
   llvm_value_construct(D2V(C), Ty, Name, VT);
@@ -279,7 +279,7 @@
   llvm_value_destruct(D2V(C));
 }
 
-llvm_value *llvm_constant_new(struct llvm_type *Ty, const char *Rep) {
+llvm_value *llvm_constant_new(const struct llvm_type *Ty, const char *Rep) {
   llvm_constant *C = (llvm_constant*)xcalloc(sizeof(llvm_constant), 1);
   llvm_constant_construct(C, Ty, "", Constant, Rep);
   return D2V(C);
@@ -340,7 +340,7 @@
     llvm_constant_intptr_0 = llvm_constant_int_0;
 }
 
-llvm_value *llvm_constant_get_null(llvm_type *Ty) {
+llvm_value *llvm_constant_get_null(const llvm_type *Ty) {
   if (Ty == UByteTy) return llvm_constant_ubyte_0;
   if (Ty == IntTy)   return llvm_constant_int_0;
   if (Ty == UIntTy)  return llvm_constant_uint_0;


Index: llvm-gcc/gcc/llvm-representation.h
diff -u llvm-gcc/gcc/llvm-representation.h:1.15 llvm-gcc/gcc/llvm-representation.h:1.16
--- llvm-gcc/gcc/llvm-representation.h:1.15	Wed Mar  2 11:03:07 2005
+++ llvm-gcc/gcc/llvm-representation.h	Sat Jun 18 16:11:20 2005
@@ -48,7 +48,7 @@
 } llvm_value;
 
 /* llvm_value_construct make a copy of the name string argument */
-void llvm_value_construct(llvm_value *Val, struct llvm_type *Type,
+void llvm_value_construct(llvm_value *Val, const struct llvm_type *Type,
 			  const char *Name, enum ValueType VT);
 void llvm_value_destruct(llvm_value *Val);
 
@@ -90,11 +90,11 @@
           "Operand to V2C is not a constant"), \
    (llvm_constant*)(VAL))
 
-llvm_value *llvm_constant_new(struct llvm_type *Ty, const char *Rep);
+llvm_value *llvm_constant_new(const struct llvm_type *Ty, const char *Rep);
 llvm_value *llvm_constant_new_integral(struct llvm_type *Ty, long long X);
-llvm_value *llvm_constant_get_null(struct llvm_type *Ty);
+llvm_value *llvm_constant_get_null(const struct llvm_type *Ty);
 int llvm_is_null_constant(llvm_value *V);
-void llvm_constant_construct(llvm_constant *C, struct llvm_type *Ty,
+void llvm_constant_construct(llvm_constant *C, const struct llvm_type *Ty,
                              const char *Name, enum ValueType VT,
                              const char *Rep);
 void llvm_constant_destruct(llvm_constant *C);


Index: llvm-gcc/gcc/llvm-types.c
diff -u llvm-gcc/gcc/llvm-types.c:1.22 llvm-gcc/gcc/llvm-types.c:1.23
--- llvm-gcc/gcc/llvm-types.c:1.22	Fri May 13 00:30:45 2005
+++ llvm-gcc/gcc/llvm-types.c	Sat Jun 18 16:11:20 2005
@@ -70,19 +70,19 @@
 }
 
 /* All of the primitive types... */
-static llvm_type TheVoidTy   = { VoidTyID };
-static llvm_type TheBoolTy   = { BoolTyID };
-static llvm_type TheUByteTy  = { UByteTyID };
-static llvm_type TheSByteTy  = { SByteTyID };
-static llvm_type TheUShortTy = { UShortTyID };
-static llvm_type TheShortTy  = { ShortTyID };
-static llvm_type TheUIntTy   = { UIntTyID };
-static llvm_type TheIntTy    = { IntTyID };
-static llvm_type TheULongTy  = { ULongTyID };
-static llvm_type TheLongTy   = { LongTyID };
-static llvm_type TheFloatTy  = { FloatTyID };
-static llvm_type TheDoubleTy = { DoubleTyID };
-static llvm_type TheLabelTy  = { LabelTyID };
+static llvm_type TheVoidTy   = { VoidTyID, 0, {{0}}, 0, {0} };
+static llvm_type TheBoolTy   = { BoolTyID , 0, {{0}}, 0, {0} };
+static llvm_type TheUByteTy  = { UByteTyID, 0, {{0}}, 0, {0} };
+static llvm_type TheSByteTy  = { SByteTyID, 0, {{0}}, 0, {0} };
+static llvm_type TheUShortTy = { UShortTyID, 0, {{0}}, 0, {0} };
+static llvm_type TheShortTy  = { ShortTyID, 0, {{0}}, 0, {0} };
+static llvm_type TheUIntTy   = { UIntTyID, 0, {{0}}, 0, {0} };
+static llvm_type TheIntTy    = { IntTyID, 0, {{0}}, 0, {0} };
+static llvm_type TheULongTy  = { ULongTyID, 0, {{0}}, 0, {0} };
+static llvm_type TheLongTy   = { LongTyID, 0, {{0}}, 0, {0} };
+static llvm_type TheFloatTy  = { FloatTyID, 0, {{0}}, 0, {0} };
+static llvm_type TheDoubleTy = { DoubleTyID, 0, {{0}}, 0, {0} };
+static llvm_type TheLabelTy  = { LabelTyID, 0, {{0}}, 0, {0} };
 llvm_type *VoidTy   = &TheVoidTy;
 llvm_type *BoolTy   = &TheBoolTy;
 llvm_type *UByteTy  = &TheUByteTy;
@@ -637,8 +637,8 @@
 
 #define DEBUG_STRUCT_LAYOUT 0
 
-static void PrintFieldInfo(tree field ATTRIBUTE_UNUSED) {
 #if DEBUG_STRUCT_LAYOUT
+static void PrintFieldInfo(tree field ATTRIBUTE_UNUSED) {
   llvm_type *FieldTy = llvm_type_get_from_tree(TREE_TYPE(field));
   fprintf(stderr, "FIELD: off=%d size=%d ",
           GetFieldOffset(field), GetDeclSize(field));
@@ -646,8 +646,8 @@
   fprintf(stderr, " name='%s' talign=%d dalign=%d\n", DECL_NAME(field) ? 
           IDENTIFIER_POINTER(DECL_NAME(field)) : "<empty>",
           GetFieldAlignmentInBits(field), TYPE_ALIGN(TREE_TYPE(field))/8);
-#endif
 }
+#endif
 
 
 /* For bit-field layout, "integral" types are treated differently than other
@@ -946,7 +946,7 @@
 /* isStructWithHoles - This function returns true if the specified type is a
  * struct and if it has inter-element gaps.
  */
-static isStructWithHoles(llvm_type *Ty) {
+static int isStructWithHoles(llvm_type *Ty) {
   unsigned i, e;
   if (Ty->ID != StructTyID) return 0;
 





From reid at x10sys.com  Sat Jun 18 17:59:43 2005
From: reid at x10sys.com (Reid Spencer)
Date: Sat, 18 Jun 2005 17:59:43 -0500
Subject: [llvm-commits] CVS: llvm/docs/CommandGuide/.cvsignore 
Message-ID: <200506182259.RAA27081@zion.cs.uiuc.edu>



Changes in directory llvm/docs/CommandGuide:

.cvsignore updated: 1.1 -> 1.2
---
Log message:

Ignore generated files.


---
Diffs of the changes:  (+3 -0)

 .cvsignore |    3 +++
 1 files changed, 3 insertions(+)


Index: llvm/docs/CommandGuide/.cvsignore
diff -u llvm/docs/CommandGuide/.cvsignore:1.1 llvm/docs/CommandGuide/.cvsignore:1.2
--- llvm/docs/CommandGuide/.cvsignore:1.1	Fri Nov 19 15:54:43 2004
+++ llvm/docs/CommandGuide/.cvsignore	Sat Jun 18 17:59:31 2005
@@ -1 +1,4 @@
 pod2htm?.tmp
+*.html
+*.1
+*.ps





From reid at x10sys.com  Sat Jun 18 18:00:45 2005
From: reid at x10sys.com (Reid Spencer)
Date: Sat, 18 Jun 2005 18:00:45 -0500
Subject: [llvm-commits] CVS: llvm/docs/.cvsignore 
Message-ID: <200506182300.SAA27141@zion.cs.uiuc.edu>



Changes in directory llvm/docs:

.cvsignore updated: 1.1 -> 1.2
---
Log message:

Ignore some generated files.


---
Diffs of the changes:  (+3 -1)

 .cvsignore |    4 +++-
 1 files changed, 3 insertions(+), 1 deletion(-)


Index: llvm/docs/.cvsignore
diff -u llvm/docs/.cvsignore:1.1 llvm/docs/.cvsignore:1.2
--- llvm/docs/.cvsignore:1.1	Wed Dec  8 13:00:45 2004
+++ llvm/docs/.cvsignore	Sat Jun 18 18:00:34 2005
@@ -1,2 +1,4 @@
 doxygen.cfg
-
+doxygen
+doxygen.out
+*.tar.gz





From reid at x10sys.com  Sat Jun 18 18:01:37 2005
From: reid at x10sys.com (Reid Spencer)
Date: Sat, 18 Jun 2005 18:01:37 -0500
Subject: [llvm-commits] CVS: llvm/.cvsignore 
Message-ID: <200506182301.SAA27160@zion.cs.uiuc.edu>



Changes in directory llvm:

.cvsignore updated: 1.3 -> 1.4
---
Log message:

Ignore the configure.out file generated by "make reconfigure"


---
Diffs of the changes:  (+1 -0)

 .cvsignore |    1 +
 1 files changed, 1 insertion(+)


Index: llvm/.cvsignore
diff -u llvm/.cvsignore:1.3 llvm/.cvsignore:1.4
--- llvm/.cvsignore:1.3	Fri Dec 24 09:11:23 2004
+++ llvm/.cvsignore	Sat Jun 18 18:01:25 2005
@@ -4,3 +4,4 @@
 config.status
 cvs.out
 autom4te.cache
+configure.out





From sabre at nondot.org  Sat Jun 18 22:17:55 2005
From: sabre at nondot.org (Chris Lattner)
Date: Sat, 18 Jun 2005 22:17:55 -0500 (CDT)
Subject: [llvm-commits] CVS: llvm/test/Feature/varargs_new.ll
In-Reply-To: <1119126579.16576.92.camel@bashful.x10sys.com>
References: <200506181830.NAA25879@zion.cs.uiuc.edu>
	<1119124701.16576.90.camel@bashful.x10sys.com>
	<1119126579.16576.92.camel@bashful.x10sys.com>
Message-ID: <Pine.LNX.4.61.0506182215580.16021@nondot.org>

On Sat, 18 Jun 2005, Reid Spencer wrote:

> Andrew,
> I think I fixed this, but I'd like you to verify my patch, please:
> http://mail.cs.uiuc.edu/pipermail/llvm-commits/Week-of-Mon-20050613/026759.html

Reid: I think this patch should be reverted.  This regression test failing 
indicates a bug in the auto-upgrader for .ll files.  Imagine if an old 
LLVM front-end generated this file: now llvm-as would crash on it.

Not only is this not acceptable from a backwards compatibility 
perspective, llvm-as should not crash on *any* input.

Please revert it back to the old format.  If you'd like, you can check the 
new version in as another test to provide a sanity check for the new-style 
varargs.

Andrew, please fix the .ll file reader :)

-Chris

>> I get this with your changes:
>>
>> Running /proj/llvm/build/../llvm/test/Feature/dg.exp ...
>> FAIL: /proj/llvm/build/../llvm/test/Feature/varargs_new.ll:
>> llvm-as: /proj/llvm/build/../llvm/lib/AsmParser/llvmAsmParser.y:740:
>> llvm::Module* RunParser(llvm::Module*): Assertion `F->arg.llvm-as
>> ((anonymous namespace)::PrintStackTrace()+0x1a)[0x82c4142]
>> llvm-as((anonymous namespace)::SignalHandler(int)+0xd3)[0x82c440b]
>> /lib/tls/libc.so.6[0xaef8c8]
>> /lib/ld-linux.so.2[0xa587a2]
>> /lib/tls/libc.so.6(gsignal+0x55)[0xaef7d5]
>> /lib/tls/libc.so.6(abort+0xe9)[0xaf1149]
>> /lib/tls/libc.so.6(__assert_fail+0x101)[0xae8db1]
>> llvm-as[0x81c0ee0]
>> llvm-as(llvm::RunVMAsmParser(std::basic_string<char,
>> std::char_traits<char>, std::allocator<char> > const&,
>> _IO_FILE*)+0x73)[0]llvm-as(llvm::ParseAssemblyFile
>> (std::basic_string<char, std::char_traits<char>, std::allocator<char> >
>> const&)+0x1c1)[0x81afa4]llvm-as(main+0x5a)[0x81ab16e]
>> /lib/tls/libc.so.6(__libc_start_main+0xd3)[0xadce23]
>> llvm-as(__gxx_personality_v0+0xd1)[0x81ab091]
>> llvm-dis: Standard Input empty!
>> 0a1,3
>> ; ModuleID = '<stdin>'
>> implementation   ; Functions:
>>
>> Reid
>>
>> On Sat, 2005-06-18 at 13:30 -0500, Andrew Lenharth wrote:
>>>
>>> Changes in directory llvm/test/Feature:
>>>
>>> varargs_new.ll added (r1.1)
>>> ---
>>> Log message:
>>>
>>> new vararg test
>>>
>>> ---
>>> Diffs of the changes:  (+33 -0)
>>>
>>>  varargs_new.ll |   33 +++++++++++++++++++++++++++++++++
>>>  1 files changed, 33 insertions(+)
>>>
>>>
>>> Index: llvm/test/Feature/varargs_new.ll
>>> diff -c /dev/null llvm/test/Feature/varargs_new.ll:1.1
>>> *** /dev/null	Sat Jun 18 13:30:47 2005
>>> --- llvm/test/Feature/varargs_new.ll	Sat Jun 18 13:30:37 2005
>>> ***************
>>> *** 0 ****
>>> --- 1,33 ----
>>> + ; RUN: llvm-as %s -o - | llvm-dis > %t1.ll
>>> + ; RUN: llvm-as %t1.ll -o - | llvm-dis > %t2.ll
>>> + ; RUN: diff %t1.ll %t2.ll
>>> +
>>> + ; Demonstrate all of the variable argument handling intrinsic functions plus
>>> + ; the va_arg instruction.
>>> +
>>> + implementation   ; Functions:
>>> + declare void %llvm.va_start(sbyte**)
>>> + declare void %llvm.va_copy(sbyte**, sbyte*)
>>> + declare void %llvm.va_end(sbyte**)
>>> +
>>> + int %test(int %X, ...) {
>>> +         ; Allocate two va_list items.  On this target, va_list is of type sbyte*
>>> +         %ap = alloca sbyte*             ; <sbyte**> [#uses=4]
>>> +         %aq = alloca sbyte*             ; <sbyte**> [#uses=2]
>>> +
>>> +         ; Initialize variable argument processing
>>> +         call void %llvm.va_start(sbyte** %ap)
>>> +
>>> +         ; Read a single integer argument
>>> +         %tmp = vaarg sbyte** %ap, int           ; <int> [#uses=1]
>>> +
>>> +         ; Demonstrate usage of llvm.va_copy and llvm_va_end
>>> +         %apv = load sbyte** %ap         ; <sbyte*> [#uses=1]
>>> +         call void %llvm.va_copy(sbyte** %aq, sbyte* %apv)
>>> +         call void %llvm.va_end(sbyte** %aq)
>>> +
>>> +         ; Stop processing of arguments.
>>> +         call void %llvm.va_end(sbyte** %ap)
>>> +         ret int %tmp
>>> +
>>> + }
>>>
>>>
>>>
>>> _______________________________________________
>>> llvm-commits mailing list
>>> llvm-commits at cs.uiuc.edu
>>> http://mail.cs.uiuc.edu/mailman/listinfo/llvm-commits
>> _______________________________________________
>> llvm-commits mailing list
>> llvm-commits at cs.uiuc.edu
>> http://mail.cs.uiuc.edu/mailman/listinfo/llvm-commits
>

-Chris

-- 
http://nondot.org/sabre/
http://llvm.cs.uiuc.edu/



From alenhar2 at cs.uiuc.edu  Sat Jun 18 22:54:07 2005
From: alenhar2 at cs.uiuc.edu (Andrew Lenharth)
Date: Sat, 18 Jun 2005 22:54:07 -0500
Subject: [llvm-commits] CVS: llvm/lib/AsmParser/llvmAsmParser.y 
Message-ID: <200506190354.WAA28121@zion.cs.uiuc.edu>



Changes in directory llvm/lib/AsmParser:

llvmAsmParser.y updated: 1.226 -> 1.227
---
Log message:

add a check for the mixing of vaarg and vanext with va_arg

---
Diffs of the changes:  (+9 -0)

 llvmAsmParser.y |    9 +++++++++
 1 files changed, 9 insertions(+)


Index: llvm/lib/AsmParser/llvmAsmParser.y
diff -u llvm/lib/AsmParser/llvmAsmParser.y:1.226 llvm/lib/AsmParser/llvmAsmParser.y:1.227
--- llvm/lib/AsmParser/llvmAsmParser.y:1.226	Sat Jun 18 13:34:51 2005
+++ llvm/lib/AsmParser/llvmAsmParser.y	Sat Jun 18 22:53:56 2005
@@ -48,6 +48,7 @@
 #define YYERROR_VERBOSE 1
 
 static bool ObsoleteVarArgs;
+static bool NewVarArgs;
 static BasicBlock* CurBB;
 
 
@@ -728,6 +729,7 @@
 
   llvmAsmlineno = 1;      // Reset the current line number...
   ObsoleteVarArgs = false;
+  NewVarArgs = false;
 
   CurModule.CurrentModule = M;
   yyparse();       // Parse the file, potentially throwing exception
@@ -735,6 +737,12 @@
   Module *Result = ParserResult;
   ParserResult = 0;
 
+  if (ObsoleteVarArgs && NewVarArgs)
+  {
+    std::cerr << "This file is corrupt in that it uses both new and old style varargs\n";
+    abort();
+  }
+
   if(ObsoleteVarArgs) {
     if(Function* F = Result->getNamedFunction("llvm.va_start")) {
       assert(F->arg_size() == 0 && "Obsolete va_start takes 0 argument!");
@@ -2041,6 +2049,7 @@
     $$ = new SelectInst($2, $4, $6);
   }
   | VAARG ResolvedVal ',' Types {
+    NewVarArgs = true;
     $$ = new VAArgInst($2, *$4);
     delete $4;
   }





From alenhar2 at cs.uiuc.edu  Sun Jun 19 00:42:18 2005
From: alenhar2 at cs.uiuc.edu (Andrew Lenharth)
Date: Sun, 19 Jun 2005 00:42:18 -0500
Subject: [llvm-commits] CVS: llvm/test/Feature/varargs_new.ll
In-Reply-To: <Pine.LNX.4.61.0506182215580.16021@nondot.org>
References: <200506181830.NAA25879@zion.cs.uiuc.edu>
	<1119124701.16576.90.camel@bashful.x10sys.com>
	<1119126579.16576.92.camel@bashful.x10sys.com>
	<Pine.LNX.4.61.0506182215580.16021@nondot.org>
Message-ID: <1119159739.13532.9.camel@localhost.localdomain>

On Sat, 2005-06-18 at 22:17 -0500, Chris Lattner wrote:
> Reid: I think this patch should be reverted.  This regression test failing 
> indicates a bug in the auto-upgrader for .ll files.  Imagine if an old 
> LLVM front-end generated this file: now llvm-as would crash on it.

No front end would generate this file.  This is not a bug in the upgrade
code but a matter of what to do on illegal/invalid .ll files.  The
problem here is using oldstyle vaarg with new style va_start (new style
is va_arg, and must be to disambiguate certain legal constructs).

> Not only is this not acceptable from a backwards compatibility 
> perspective, llvm-as should not crash on *any* input.

It already does for similar problems.  try defining llvm.va_start as
taking 5 args.  Verify will hit an assertion.  This is no different than
hitting an arguement number check assertion earlier.

Andrew
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From alenhar2 at cs.uiuc.edu  Sun Jun 19 00:45:12 2005
From: alenhar2 at cs.uiuc.edu (Andrew Lenharth)
Date: Sun, 19 Jun 2005 00:45:12 -0500
Subject: [llvm-commits] CVS: llvm/lib/Target/SparcV9/SparcV9BurgISel.cpp 
Message-ID: <200506190545.AAA28773@zion.cs.uiuc.edu>



Changes in directory llvm/lib/Target/SparcV9:

SparcV9BurgISel.cpp updated: 1.20 -> 1.21
---
Log message:

so this doesn't crash when run.  It is hard to tell if things are right enough to work correctly with all the TmpInstructions running around

---
Diffs of the changes:  (+27 -24)

 SparcV9BurgISel.cpp |   51 +++++++++++++++++++++++++++------------------------
 1 files changed, 27 insertions(+), 24 deletions(-)


Index: llvm/lib/Target/SparcV9/SparcV9BurgISel.cpp
diff -u llvm/lib/Target/SparcV9/SparcV9BurgISel.cpp:1.20 llvm/lib/Target/SparcV9/SparcV9BurgISel.cpp:1.21
--- llvm/lib/Target/SparcV9/SparcV9BurgISel.cpp:1.20	Sat Jun 18 13:46:40 2005
+++ llvm/lib/Target/SparcV9/SparcV9BurgISel.cpp	Sun Jun 19 00:45:00 2005
@@ -2869,8 +2869,11 @@
     int fpReg          = SparcV9::i6;
     int firstVarArgOff = numFixedArgs * 8 +
                          SparcV9FrameInfo::FirstIncomingArgOffsetFromFP;
-    mvec.push_back(BuildMI(V9::ADDi, 3).addMReg(fpReg).addSImm(firstVarArgOff).
-                   addRegDef(&callInstr));
+    //What oh what do we pass to TmpInstruction?
+    MachineCodeForInstruction& m = MachineCodeForInstruction::get(&callInstr);
+    TmpInstruction* T = new TmpInstruction(m, callInstr.getOperand(1)->getType());
+    mvec.push_back(BuildMI(V9::ADDi, 3).addMReg(fpReg).addSImm(firstVarArgOff).addRegDef(T));
+    mvec.push_back(BuildMI(V9::STXr, 3).addReg(T).addReg(callInstr.getOperand(1)).addSImm(0));
     return true;
   }
 
@@ -2878,11 +2881,10 @@
     return true;                        // no-op on SparcV9
 
   case Intrinsic::vacopy:
-    // Simple copy of current va_list (arg1) to new va_list (result)
-    mvec.push_back(BuildMI(V9::ORr, 3).
-                   addMReg(target.getRegInfo()->getZeroRegNum()).
-                   addReg(callInstr.getOperand(1)).
-                   addRegDef(&callInstr));
+    // Simple store of current va_list (arg2) to new va_list (arg1)
+    mvec.push_back(BuildMI(V9::STXi, 3).
+                   addReg(callInstr.getOperand(2)).
+                   addReg(callInstr.getOperand(1)).addSImm(0));
     return true;
   }
 }
@@ -4216,32 +4218,33 @@
       case 64:	// reg:   Phi(reg,reg)
         break;                          // don't forward the value
 
-#if 0
-//FIXME: new VAArg support
-      case 65:	// reg:   VANext(reg):  the va_next(va_list, type) instruction
-      { // Increment the va_list pointer register according to the type.
-        // All LLVM argument types are <= 64 bits, so use one doubleword.
-        Instruction* vaNextI = subtreeRoot->getInstruction();
-        assert(target.getTargetData().getTypeSize(vaNextI->getType()) <= 8 &&
-               "We assumed that all LLVM parameter types <= 8 bytes!");
-        unsigned argSize = SparcV9FrameInfo::SizeOfEachArgOnStack;
-        mvec.push_back(BuildMI(V9::ADDi, 3).addReg(vaNextI->getOperand(0)).
-                       addSImm(argSize).addRegDef(vaNextI));
-        break;
-      }
-#endif
-
-//FIXME: new VAArg support
       case 66:	// reg:   VAArg (reg): the va_arg instruction
       { // Load argument from stack using current va_list pointer value.
         // Use 64-bit load for all non-FP args, and LDDF or double for FP.
         Instruction* vaArgI = subtreeRoot->getInstruction();
+        //but first load the va_list pointer
+        // Create a virtual register to represent it
+        //What oh what do we pass to TmpInstruction?
+        MachineCodeForInstruction& m1 = MachineCodeForInstruction::get(vaArgI);
+        TmpInstruction* VReg = new TmpInstruction(m1, vaArgI->getOperand(0)->getType());
+        mvec.push_back(BuildMI(V9::LDXi, 3).addReg(vaArgI->getOperand(0))
+                       .addSImm(0).addRegDef(VReg));
+        //OK, now do the load
         MachineOpCode loadOp = (vaArgI->getType()->isFloatingPoint()
                                 ? (vaArgI->getType() == Type::FloatTy
                                    ? V9::LDFi : V9::LDDFi)
                                 : V9::LDXi);
-        mvec.push_back(BuildMI(loadOp, 3).addReg(vaArgI->getOperand(0)).
+        mvec.push_back(BuildMI(loadOp, 3).addReg(VReg).
                        addSImm(0).addRegDef(vaArgI));
+        //Also increment the pointer
+        MachineCodeForInstruction& m2 = MachineCodeForInstruction::get(vaArgI);
+        TmpInstruction* VRegA = new TmpInstruction(m2, vaArgI->getOperand(0)->getType());
+        unsigned argSize = SparcV9FrameInfo::SizeOfEachArgOnStack;
+        mvec.push_back(BuildMI(V9::ADDi, 3).addReg(VReg).
+                       addSImm(argSize).addRegDef(VRegA));
+        //And store
+        mvec.push_back(BuildMI(V9::STXr, 3).addReg(VRegA).
+                       addReg(vaArgI->getOperand(0)).addSImm(0));
         break;
       }
 





From reid at x10sys.com  Sun Jun 19 01:25:31 2005
From: reid at x10sys.com (Reid Spencer)
Date: Sat, 18 Jun 2005 23:25:31 -0700
Subject: [llvm-commits] CVS: llvm/test/Feature/varargs_new.ll
In-Reply-To: <Pine.LNX.4.61.0506182215580.16021@nondot.org>
References: <200506181830.NAA25879@zion.cs.uiuc.edu>
	<1119124701.16576.90.camel@bashful.x10sys.com>
	<1119126579.16576.92.camel@bashful.x10sys.com>
	<Pine.LNX.4.61.0506182215580.16021@nondot.org>
Message-ID: <1119162331.16576.105.camel@bashful.x10sys.com>

I don't think my patch is incorrect. The test case needs to test va_arg,
not vaarg. Since it doesn't exist in anyone's release tarball, only in
CVS, it can't hurt since they'd only pick this test up if they also
picked up Andrew's changes. 

I have requested that Andrew add additional tests for mixing vaarg and
vanext with va_arg. He's already committed changes to the assembly
reader to check those combinations. 

As Andrew pointed out, an old front end could not generate this file. 

The change I made is needed to make that one test correct, as Andrew has
confirmed.  However, I agree that the auto-upgrade, validation checking
and the test cases are insufficient. Please talk to Andrew about
completing those tasks. 

Reid

On Sat, 2005-06-18 at 22:17 -0500, Chris Lattner wrote:
> On Sat, 18 Jun 2005, Reid Spencer wrote:
> 
> > Andrew,
> > I think I fixed this, but I'd like you to verify my patch, please:
> > http://mail.cs.uiuc.edu/pipermail/llvm-commits/Week-of-Mon-20050613/026759.html
> 
> Reid: I think this patch should be reverted.  This regression test failing 
> indicates a bug in the auto-upgrader for .ll files.  Imagine if an old 
> LLVM front-end generated this file: now llvm-as would crash on it.
> 
> Not only is this not acceptable from a backwards compatibility 
> perspective, llvm-as should not crash on *any* input.
> 
> Please revert it back to the old format.  If you'd like, you can check the 
> new version in as another test to provide a sanity check for the new-style 
> varargs.
> 
> Andrew, please fix the .ll file reader :)
> 
> -Chris
> 
> >> I get this with your changes:
> >>
> >> Running /proj/llvm/build/../llvm/test/Feature/dg.exp ...
> >> FAIL: /proj/llvm/build/../llvm/test/Feature/varargs_new.ll:
> >> llvm-as: /proj/llvm/build/../llvm/lib/AsmParser/llvmAsmParser.y:740:
> >> llvm::Module* RunParser(llvm::Module*): Assertion `F->arg.llvm-as
> >> ((anonymous namespace)::PrintStackTrace()+0x1a)[0x82c4142]
> >> llvm-as((anonymous namespace)::SignalHandler(int)+0xd3)[0x82c440b]
> >> /lib/tls/libc.so.6[0xaef8c8]
> >> /lib/ld-linux.so.2[0xa587a2]
> >> /lib/tls/libc.so.6(gsignal+0x55)[0xaef7d5]
> >> /lib/tls/libc.so.6(abort+0xe9)[0xaf1149]
> >> /lib/tls/libc.so.6(__assert_fail+0x101)[0xae8db1]
> >> llvm-as[0x81c0ee0]
> >> llvm-as(llvm::RunVMAsmParser(std::basic_string<char,
> >> std::char_traits<char>, std::allocator<char> > const&,
> >> _IO_FILE*)+0x73)[0]llvm-as(llvm::ParseAssemblyFile
> >> (std::basic_string<char, std::char_traits<char>, std::allocator<char> >
> >> const&)+0x1c1)[0x81afa4]llvm-as(main+0x5a)[0x81ab16e]
> >> /lib/tls/libc.so.6(__libc_start_main+0xd3)[0xadce23]
> >> llvm-as(__gxx_personality_v0+0xd1)[0x81ab091]
> >> llvm-dis: Standard Input empty!
> >> 0a1,3
> >> ; ModuleID = '<stdin>'
> >> implementation   ; Functions:
> >>
> >> Reid
> >>
> >> On Sat, 2005-06-18 at 13:30 -0500, Andrew Lenharth wrote:
> >>>
> >>> Changes in directory llvm/test/Feature:
> >>>
> >>> varargs_new.ll added (r1.1)
> >>> ---
> >>> Log message:
> >>>
> >>> new vararg test
> >>>
> >>> ---
> >>> Diffs of the changes:  (+33 -0)
> >>>
> >>>  varargs_new.ll |   33 +++++++++++++++++++++++++++++++++
> >>>  1 files changed, 33 insertions(+)
> >>>
> >>>
> >>> Index: llvm/test/Feature/varargs_new.ll
> >>> diff -c /dev/null llvm/test/Feature/varargs_new.ll:1.1
> >>> *** /dev/null	Sat Jun 18 13:30:47 2005
> >>> --- llvm/test/Feature/varargs_new.ll	Sat Jun 18 13:30:37 2005
> >>> ***************
> >>> *** 0 ****
> >>> --- 1,33 ----
> >>> + ; RUN: llvm-as %s -o - | llvm-dis > %t1.ll
> >>> + ; RUN: llvm-as %t1.ll -o - | llvm-dis > %t2.ll
> >>> + ; RUN: diff %t1.ll %t2.ll
> >>> +
> >>> + ; Demonstrate all of the variable argument handling intrinsic functions plus
> >>> + ; the va_arg instruction.
> >>> +
> >>> + implementation   ; Functions:
> >>> + declare void %llvm.va_start(sbyte**)
> >>> + declare void %llvm.va_copy(sbyte**, sbyte*)
> >>> + declare void %llvm.va_end(sbyte**)
> >>> +
> >>> + int %test(int %X, ...) {
> >>> +         ; Allocate two va_list items.  On this target, va_list is of type sbyte*
> >>> +         %ap = alloca sbyte*             ; <sbyte**> [#uses=4]
> >>> +         %aq = alloca sbyte*             ; <sbyte**> [#uses=2]
> >>> +
> >>> +         ; Initialize variable argument processing
> >>> +         call void %llvm.va_start(sbyte** %ap)
> >>> +
> >>> +         ; Read a single integer argument
> >>> +         %tmp = vaarg sbyte** %ap, int           ; <int> [#uses=1]
> >>> +
> >>> +         ; Demonstrate usage of llvm.va_copy and llvm_va_end
> >>> +         %apv = load sbyte** %ap         ; <sbyte*> [#uses=1]
> >>> +         call void %llvm.va_copy(sbyte** %aq, sbyte* %apv)
> >>> +         call void %llvm.va_end(sbyte** %aq)
> >>> +
> >>> +         ; Stop processing of arguments.
> >>> +         call void %llvm.va_end(sbyte** %ap)
> >>> +         ret int %tmp
> >>> +
> >>> + }
> >>>
> >>>
> >>>
> >>> _______________________________________________
> >>> llvm-commits mailing list
> >>> llvm-commits at cs.uiuc.edu
> >>> http://mail.cs.uiuc.edu/mailman/listinfo/llvm-commits
> >> _______________________________________________
> >> llvm-commits mailing list
> >> llvm-commits at cs.uiuc.edu
> >> http://mail.cs.uiuc.edu/mailman/listinfo/llvm-commits
> >
> 
> -Chris
> 
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From sabre at nondot.org  Sun Jun 19 08:36:11 2005
From: sabre at nondot.org (Chris Lattner)
Date: Sun, 19 Jun 2005 08:36:11 -0500 (CDT)
Subject: [llvm-commits] CVS: llvm/test/Feature/varargs_new.ll
In-Reply-To: <1119159739.13532.9.camel@localhost.localdomain>
References: <200506181830.NAA25879@zion.cs.uiuc.edu> 
	<1119124701.16576.90.camel@bashful.x10sys.com>
	<1119126579.16576.92.camel@bashful.x10sys.com>
	<Pine.LNX.4.61.0506182215580.16021@nondot.org>
	<1119159739.13532.9.camel@localhost.localdomain>
Message-ID: <Pine.LNX.4.61.0506190835370.3447@nondot.org>

On Sun, 19 Jun 2005, Andrew Lenharth wrote:

> On Sat, 2005-06-18 at 22:17 -0500, Chris Lattner wrote:
>> Reid: I think this patch should be reverted.  This regression test failing
>> indicates a bug in the auto-upgrader for .ll files.  Imagine if an old
>> LLVM front-end generated this file: now llvm-as would crash on it.
>
> No front end would generate this file.  This is not a bug in the upgrade
> code but a matter of what to do on illegal/invalid .ll files.  The
> problem here is using oldstyle vaarg with new style va_start (new style
> is va_arg, and must be to disambiguate certain legal constructs).

Ok, makes sense.

>> Not only is this not acceptable from a backwards compatibility
>> perspective, llvm-as should not crash on *any* input.
>
> It already does for similar problems.  try defining llvm.va_start as
> taking 5 args.  Verify will hit an assertion.  This is no different than
> hitting an arguement number check assertion earlier.

That's a bug and should be fixed then :).  It should use ThrowException to 
report the error, which will tack on a line number to the error report.

Sorry for the misunderstanding!

-Chris

-- 
http://nondot.org/sabre/
http://llvm.cs.uiuc.edu/



From sabre at nondot.org  Sun Jun 19 08:37:29 2005
From: sabre at nondot.org (Chris Lattner)
Date: Sun, 19 Jun 2005 08:37:29 -0500 (CDT)
Subject: [llvm-commits] CVS: llvm/test/Feature/varargs_new.ll
In-Reply-To: <1119162331.16576.105.camel@bashful.x10sys.com>
References: <200506181830.NAA25879@zion.cs.uiuc.edu> 
	<1119124701.16576.90.camel@bashful.x10sys.com>
	<1119126579.16576.92.camel@bashful.x10sys.com>
	<Pine.LNX.4.61.0506182215580.16021@nondot.org>
	<1119162331.16576.105.camel@bashful.x10sys.com>
Message-ID: <Pine.LNX.4.61.0506190836150.3447@nondot.org>

On Sat, 18 Jun 2005, Reid Spencer wrote:

> I don't think my patch is incorrect. The test case needs to test va_arg,
> not vaarg. Since it doesn't exist in anyone's release tarball, only in
> CVS, it can't hurt since they'd only pick this test up if they also
> picked up Andrew's changes.

Ok.

> I have requested that Andrew add additional tests for mixing vaarg and
> vanext with va_arg. He's already committed changes to the assembly
> reader to check those combinations.

Ok, great.

> As Andrew pointed out, an old front end could not generate this file.

My mistake :)

> The change I made is needed to make that one test correct, as Andrew has
> confirmed.  However, I agree that the auto-upgrade, validation checking
> and the test cases are insufficient. Please talk to Andrew about
> completing those tasks.

Also, all of the new regressions on X86...

-Chris

> On Sat, 2005-06-18 at 22:17 -0500, Chris Lattner wrote:
>> On Sat, 18 Jun 2005, Reid Spencer wrote:
>>
>>> Andrew,
>>> I think I fixed this, but I'd like you to verify my patch, please:
>>> http://mail.cs.uiuc.edu/pipermail/llvm-commits/Week-of-Mon-20050613/026759.html
>>
>> Reid: I think this patch should be reverted.  This regression test failing
>> indicates a bug in the auto-upgrader for .ll files.  Imagine if an old
>> LLVM front-end generated this file: now llvm-as would crash on it.
>>
>> Not only is this not acceptable from a backwards compatibility
>> perspective, llvm-as should not crash on *any* input.
>>
>> Please revert it back to the old format.  If you'd like, you can check the
>> new version in as another test to provide a sanity check for the new-style
>> varargs.
>>
>> Andrew, please fix the .ll file reader :)
>>
>> -Chris
>>
>>>> I get this with your changes:
>>>>
>>>> Running /proj/llvm/build/../llvm/test/Feature/dg.exp ...
>>>> FAIL: /proj/llvm/build/../llvm/test/Feature/varargs_new.ll:
>>>> llvm-as: /proj/llvm/build/../llvm/lib/AsmParser/llvmAsmParser.y:740:
>>>> llvm::Module* RunParser(llvm::Module*): Assertion `F->arg.llvm-as
>>>> ((anonymous namespace)::PrintStackTrace()+0x1a)[0x82c4142]
>>>> llvm-as((anonymous namespace)::SignalHandler(int)+0xd3)[0x82c440b]
>>>> /lib/tls/libc.so.6[0xaef8c8]
>>>> /lib/ld-linux.so.2[0xa587a2]
>>>> /lib/tls/libc.so.6(gsignal+0x55)[0xaef7d5]
>>>> /lib/tls/libc.so.6(abort+0xe9)[0xaf1149]
>>>> /lib/tls/libc.so.6(__assert_fail+0x101)[0xae8db1]
>>>> llvm-as[0x81c0ee0]
>>>> llvm-as(llvm::RunVMAsmParser(std::basic_string<char,
>>>> std::char_traits<char>, std::allocator<char> > const&,
>>>> _IO_FILE*)+0x73)[0]llvm-as(llvm::ParseAssemblyFile
>>>> (std::basic_string<char, std::char_traits<char>, std::allocator<char> >
>>>> const&)+0x1c1)[0x81afa4]llvm-as(main+0x5a)[0x81ab16e]
>>>> /lib/tls/libc.so.6(__libc_start_main+0xd3)[0xadce23]
>>>> llvm-as(__gxx_personality_v0+0xd1)[0x81ab091]
>>>> llvm-dis: Standard Input empty!
>>>> 0a1,3
>>>> ; ModuleID = '<stdin>'
>>>> implementation   ; Functions:
>>>>
>>>> Reid
>>>>
>>>> On Sat, 2005-06-18 at 13:30 -0500, Andrew Lenharth wrote:
>>>>>
>>>>> Changes in directory llvm/test/Feature:
>>>>>
>>>>> varargs_new.ll added (r1.1)
>>>>> ---
>>>>> Log message:
>>>>>
>>>>> new vararg test
>>>>>
>>>>> ---
>>>>> Diffs of the changes:  (+33 -0)
>>>>>
>>>>>  varargs_new.ll |   33 +++++++++++++++++++++++++++++++++
>>>>>  1 files changed, 33 insertions(+)
>>>>>
>>>>>
>>>>> Index: llvm/test/Feature/varargs_new.ll
>>>>> diff -c /dev/null llvm/test/Feature/varargs_new.ll:1.1
>>>>> *** /dev/null	Sat Jun 18 13:30:47 2005
>>>>> --- llvm/test/Feature/varargs_new.ll	Sat Jun 18 13:30:37 2005
>>>>> ***************
>>>>> *** 0 ****
>>>>> --- 1,33 ----
>>>>> + ; RUN: llvm-as %s -o - | llvm-dis > %t1.ll
>>>>> + ; RUN: llvm-as %t1.ll -o - | llvm-dis > %t2.ll
>>>>> + ; RUN: diff %t1.ll %t2.ll
>>>>> +
>>>>> + ; Demonstrate all of the variable argument handling intrinsic functions plus
>>>>> + ; the va_arg instruction.
>>>>> +
>>>>> + implementation   ; Functions:
>>>>> + declare void %llvm.va_start(sbyte**)
>>>>> + declare void %llvm.va_copy(sbyte**, sbyte*)
>>>>> + declare void %llvm.va_end(sbyte**)
>>>>> +
>>>>> + int %test(int %X, ...) {
>>>>> +         ; Allocate two va_list items.  On this target, va_list is of type sbyte*
>>>>> +         %ap = alloca sbyte*             ; <sbyte**> [#uses=4]
>>>>> +         %aq = alloca sbyte*             ; <sbyte**> [#uses=2]
>>>>> +
>>>>> +         ; Initialize variable argument processing
>>>>> +         call void %llvm.va_start(sbyte** %ap)
>>>>> +
>>>>> +         ; Read a single integer argument
>>>>> +         %tmp = vaarg sbyte** %ap, int           ; <int> [#uses=1]
>>>>> +
>>>>> +         ; Demonstrate usage of llvm.va_copy and llvm_va_end
>>>>> +         %apv = load sbyte** %ap         ; <sbyte*> [#uses=1]
>>>>> +         call void %llvm.va_copy(sbyte** %aq, sbyte* %apv)
>>>>> +         call void %llvm.va_end(sbyte** %aq)
>>>>> +
>>>>> +         ; Stop processing of arguments.
>>>>> +         call void %llvm.va_end(sbyte** %ap)
>>>>> +         ret int %tmp
>>>>> +
>>>>> + }
>>>>>
>>>>>
>>>>>
>>>>> _______________________________________________
>>>>> llvm-commits mailing list
>>>>> llvm-commits at cs.uiuc.edu
>>>>> http://mail.cs.uiuc.edu/mailman/listinfo/llvm-commits
>>>> _______________________________________________
>>>> llvm-commits mailing list
>>>> llvm-commits at cs.uiuc.edu
>>>> http://mail.cs.uiuc.edu/mailman/listinfo/llvm-commits
>>>
>>
>> -Chris
>>
>

-Chris

-- 
http://nondot.org/sabre/
http://llvm.cs.uiuc.edu/



From alenhar2 at cs.uiuc.edu  Sun Jun 19 09:05:07 2005
From: alenhar2 at cs.uiuc.edu (Andrew Lenharth)
Date: Sun, 19 Jun 2005 09:05:07 -0500
Subject: [llvm-commits] CVS: llvm/lib/Bytecode/Reader/ReaderWrappers.cpp 
Message-ID: <200506191405.JAA00998@zion.cs.uiuc.edu>



Changes in directory llvm/lib/Bytecode/Reader:

ReaderWrappers.cpp updated: 1.48 -> 1.49
---
Log message:

va_end fix

---
Diffs of the changes:  (+1 -0)

 ReaderWrappers.cpp |    1 +
 1 files changed, 1 insertion(+)


Index: llvm/lib/Bytecode/Reader/ReaderWrappers.cpp
diff -u llvm/lib/Bytecode/Reader/ReaderWrappers.cpp:1.48 llvm/lib/Bytecode/Reader/ReaderWrappers.cpp:1.49
--- llvm/lib/Bytecode/Reader/ReaderWrappers.cpp:1.48	Sat Jun 18 13:34:51 2005
+++ llvm/lib/Bytecode/Reader/ReaderWrappers.cpp	Sun Jun 19 09:04:55 2005
@@ -209,6 +209,7 @@
     for(Value::use_iterator I = F->use_begin(), E = F->use_end(); I != E;)
       if (CallInst* CI = dyn_cast<CallInst>(*I++)) {
         AllocaInst* bar = new AllocaInst(ArgTy, 0, "vaend.fix.1", CI);
+        new StoreInst(CI->getOperand(1), bar, CI);
         new CallInst(NF, bar, "", CI);
         CI->getParent()->getInstList().erase(CI);
       }





From alenhar2 at cs.uiuc.edu  Sun Jun 19 09:05:07 2005
From: alenhar2 at cs.uiuc.edu (Andrew Lenharth)
Date: Sun, 19 Jun 2005 09:05:07 -0500
Subject: [llvm-commits] CVS: llvm/lib/AsmParser/llvmAsmParser.y 
Message-ID: <200506191405.JAA01002@zion.cs.uiuc.edu>



Changes in directory llvm/lib/AsmParser:

llvmAsmParser.y updated: 1.227 -> 1.228
---
Log message:

va_end fix

---
Diffs of the changes:  (+1 -0)

 llvmAsmParser.y |    1 +
 1 files changed, 1 insertion(+)


Index: llvm/lib/AsmParser/llvmAsmParser.y
diff -u llvm/lib/AsmParser/llvmAsmParser.y:1.227 llvm/lib/AsmParser/llvmAsmParser.y:1.228
--- llvm/lib/AsmParser/llvmAsmParser.y:1.227	Sat Jun 18 22:53:56 2005
+++ llvm/lib/AsmParser/llvmAsmParser.y	Sun Jun 19 09:04:55 2005
@@ -785,6 +785,7 @@
       while (!F->use_empty()) {
         CallInst* CI = cast<CallInst>(F->use_back());
         AllocaInst* bar = new AllocaInst(ArgTy, 0, "vaend.fix.1", CI);
+        new StoreInst(CI->getOperand(1), bar, CI);
         new CallInst(NF, bar, "", CI);
         CI->getParent()->getInstList().erase(CI);
       }





From alenhar2 at cs.uiuc.edu  Sun Jun 19 09:25:07 2005
From: alenhar2 at cs.uiuc.edu (Andrew Lenharth)
Date: Sun, 19 Jun 2005 09:25:07 -0500
Subject: [llvm-commits] CVS: llvm/test/Feature/varargs_new.ll
In-Reply-To: <Pine.LNX.4.61.0506190836150.3447@nondot.org>
References: <200506181830.NAA25879@zion.cs.uiuc.edu>
	<1119124701.16576.90.camel@bashful.x10sys.com>
	<1119126579.16576.92.camel@bashful.x10sys.com>
	<Pine.LNX.4.61.0506182215580.16021@nondot.org>
	<1119162331.16576.105.camel@bashful.x10sys.com>
	<Pine.LNX.4.61.0506190836150.3447@nondot.org>
Message-ID: <1119191107.31839.0.camel@localhost.localdomain>

On Sun, 2005-06-19 at 08:37 -0500, Chris Lattner wrote:
> Also, all of the new regressions on X86...

OK, this is what you get for testing without optimizations :)

instcombine is eating instrinsics.

Andrew
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From alenhar2 at cs.uiuc.edu  Sun Jun 19 09:41:31 2005
From: alenhar2 at cs.uiuc.edu (Andrew Lenharth)
Date: Sun, 19 Jun 2005 09:41:31 -0500
Subject: [llvm-commits] CVS: llvm/lib/Transforms/Utils/Local.cpp 
Message-ID: <200506191441.JAA01145@zion.cs.uiuc.edu>



Changes in directory llvm/lib/Transforms/Utils:

Local.cpp updated: 1.39 -> 1.40
---
Log message:

prevent DCE of vaarg intrinsics.  This should take care of most regressions

---
Diffs of the changes:  (+0 -2)

 Local.cpp |    2 --
 1 files changed, 2 deletions(-)


Index: llvm/lib/Transforms/Utils/Local.cpp
diff -u llvm/lib/Transforms/Utils/Local.cpp:1.39 llvm/lib/Transforms/Utils/Local.cpp:1.40
--- llvm/lib/Transforms/Utils/Local.cpp:1.39	Fri May  6 00:27:34 2005
+++ llvm/lib/Transforms/Utils/Local.cpp	Sun Jun 19 09:41:20 2005
@@ -381,8 +381,6 @@
     if (Function *F = CI->getCalledFunction())
       switch (F->getIntrinsicID()) {
       default: break;
-      case Intrinsic::vastart:
-      case Intrinsic::vacopy:
       case Intrinsic::returnaddress:
       case Intrinsic::frameaddress:
       case Intrinsic::isunordered:





From alenhar2 at cs.uiuc.edu  Sun Jun 19 09:46:32 2005
From: alenhar2 at cs.uiuc.edu (Andrew Lenharth)
Date: Sun, 19 Jun 2005 09:46:32 -0500
Subject: [llvm-commits] CVS: llvm/include/llvm/Instructions.h 
Message-ID: <200506191446.JAA01185@zion.cs.uiuc.edu>



Changes in directory llvm/include/llvm:

Instructions.h updated: 1.23 -> 1.24
---
Log message:

fix DCE + va_arg problem

---
Diffs of the changes:  (+1 -0)

 Instructions.h |    1 +
 1 files changed, 1 insertion(+)


Index: llvm/include/llvm/Instructions.h
diff -u llvm/include/llvm/Instructions.h:1.23 llvm/include/llvm/Instructions.h:1.24
--- llvm/include/llvm/Instructions.h:1.23	Sat Jun 18 13:31:30 2005
+++ llvm/include/llvm/Instructions.h	Sun Jun 19 09:46:20 2005
@@ -681,6 +681,7 @@
   }
 
   virtual VAArgInst *clone() const;
+  bool mayWriteToMemory() const { return true; }
 
   // Methods for support type inquiry through isa, cast, and dyn_cast:
   static inline bool classof(const VAArgInst *) { return true; }





From alenhar2 at cs.uiuc.edu  Sun Jun 19 09:53:30 2005
From: alenhar2 at cs.uiuc.edu (Andrew Lenharth)
Date: Sun, 19 Jun 2005 09:53:30 -0500
Subject: [llvm-commits] CVS: llvm/test/Feature/varargs_new.ll
In-Reply-To: <Pine.LNX.4.61.0506190836150.3447@nondot.org>
References: <200506181830.NAA25879@zion.cs.uiuc.edu>
	<1119124701.16576.90.camel@bashful.x10sys.com>
	<1119126579.16576.92.camel@bashful.x10sys.com>
	<Pine.LNX.4.61.0506182215580.16021@nondot.org>
	<1119162331.16576.105.camel@bashful.x10sys.com>
	<Pine.LNX.4.61.0506190836150.3447@nondot.org>
Message-ID: <1119192810.3450.1.camel@localhost.localdomain>

On Sun, 2005-06-19 at 08:37 -0500, Chris Lattner wrote:
> Also, all of the new regressions on X86...

http://mail.cs.uiuc.edu/pipermail/llvm-commits/Week-of-Mon-20050613/026777.html
http://mail.cs.uiuc.edu/pipermail/llvm-commits/Week-of-Mon-20050613/026776.html

Should do it.

-- 
Andrew Lenharth <alenhar2 at cs.uiuc.edu>
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