From lattner at cs.uiuc.edu  Mon Jun 27 01:28:56 2005
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Mon, 27 Jun 2005 01:28:56 -0500
Subject: [llvm-commits] CVS: llvm/include/llvm/CodeGen/ELFWriter.h 
Message-ID: <200506270628.BAA28553@zion.cs.uiuc.edu>



Changes in directory llvm/include/llvm/CodeGen:

ELFWriter.h added (r1.1)
---
Log message:

iniital checkin of ELFWriter header.

For now, the elf writer is only capable of emitting an empty elf file, with
a section table and a section table string table.  This will be enhanced
in the future :)


---
Diffs of the changes:  (+174 -0)

 ELFWriter.h |  174 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
 1 files changed, 174 insertions(+)


Index: llvm/include/llvm/CodeGen/ELFWriter.h
diff -c /dev/null llvm/include/llvm/CodeGen/ELFWriter.h:1.1
*** /dev/null	Mon Jun 27 01:28:55 2005
--- llvm/include/llvm/CodeGen/ELFWriter.h	Mon Jun 27 01:28:45 2005
***************
*** 0 ****
--- 1,174 ----
+ //===-- ELFWriter.h - Target-independent ELF writer support -----*- C++ -*-===//
+ //
+ //                     The LLVM Compiler Infrastructure
+ //
+ // This file was developed by the LLVM research group and is distributed under
+ // the University of Illinois Open Source License. See LICENSE.TXT for details.
+ //
+ //===----------------------------------------------------------------------===//
+ //
+ // This file defines the ELFWriter class.
+ //
+ //===----------------------------------------------------------------------===//
+ 
+ #ifndef LLVM_CODEGEN_ELFWRITER_H
+ #define LLVM_CODEGEN_ELFWRITER_H
+ 
+ #include "llvm/CodeGen/MachineFunctionPass.h"
+ 
+ namespace llvm {
+   class GlobalVariable;
+ 
+   /// ELFWriter - This class implements the common target-independent code for
+   /// writing ELF files.  Targets should derive a class from this to
+   /// parameterize the output format.
+   ///
+   class ELFWriter : public MachineFunctionPass {
+   protected:
+     ELFWriter(std::ostream &O, TargetMachine &TM);
+ 
+     /// Output stream to send the resultant object file to.
+     ///
+     std::ostream &O;
+ 
+     /// Target machine description.
+     ///
+     TargetMachine &TM;
+ 
+     //===------------------------------------------------------------------===//
+     // Properties to be set by the derived class ctor, used to configure the
+     // ELFWriter.
+ 
+     // e_machine - This field is the target specific value to emit as the
+     // e_machine member of the ELF header.
+     unsigned short e_machine;
+ 
+     // e_flags - The machine flags for the target.  This defaults to zero.
+     unsigned e_flags;
+ 
+     //===------------------------------------------------------------------===//
+     // Properties inferred automatically from the target machine.
+     //
+ 
+     /// is64Bit/isLittleEndian - This information is inferred from the target
+     /// machine directly, indicating whether to emit a 32- or 64-bit ELF file.
+     bool is64Bit, isLittleEndian;
+ 
+     /// doInitialization - Emit the file header and all of the global variables
+     /// for the module to the ELF file.
+     bool doInitialization(Module &M);
+ 
+     bool runOnMachineFunction(MachineFunction &MF);
+ 
+ 
+     /// doFinalization - Now that the module has been completely processed, emit
+     /// the ELF file to 'O'.
+     bool doFinalization(Module &M);
+ 
+   private:
+     // The buffer we are accumulating the file into.  Note that this should be
+     // changed into something much more efficient later (and the bytecode writer
+     // as well!).
+     std::vector<unsigned char> OutputBuffer;
+ 
+     /// ELFSection - This struct contains information about each section that is
+     /// emitted to the OutputBuffer.  This is eventually turned into the section
+     /// header table at the end of the file.
+     struct ELFSection {
+       std::string Name;       // Name of the section.
+       unsigned NameIdx;       // Index in .shstrtab of name, once emitted.
+       unsigned Type;
+       unsigned Flags;
+       uint64_t Addr;
+       unsigned Offset;
+       unsigned Size;
+       unsigned Link;
+       unsigned Info;
+       unsigned Align;
+       unsigned EntSize;
+       ELFSection() : Type(0), Flags(0), Addr(0), Offset(0), Size(0), Link(0),
+                      Info(0), Align(0), EntSize(0) {
+       }
+       ELFSection(const char *name, unsigned offset)
+         : Name(name), Type(0), Flags(0), Addr(0), Offset(offset), Size(0),
+           Link(0), Info(0), Align(0), EntSize(0) {
+       }
+     };
+ 
+     /// SectionList - This is the list of sections that we have emitted to the
+     /// file.  Once the file has been completely built, the section header table
+     /// is constructed from this info.
+     std::vector<ELFSection> SectionList;
+ 
+     // As we accumulate the ELF file into OutputBuffer, we occasionally need to
+     // keep track of locations to update later (e.g. the location of the section
+     // table in the ELF header.  These members keep track of the offset in
+     // OffsetBuffer of these various pieces to update and other locations in the
+     // file.
+     unsigned ELFHeader_e_shoff_Offset;     // e_shoff    in ELF header.
+     unsigned ELFHeader_e_shstrndx_Offset;  // e_shstrndx in ELF header.
+     unsigned ELFHeader_e_shnum_Offset;     // e_shnum    in ELF header.
+ 
+     void outbyte(unsigned char X) { OutputBuffer.push_back(X); }
+     void outhalf(unsigned short X) {
+       if (isLittleEndian) {
+         OutputBuffer.push_back(X&255);
+         OutputBuffer.push_back(X >> 8);
+       } else {
+         OutputBuffer.push_back(X >> 8);
+         OutputBuffer.push_back(X&255);
+       }
+     }
+     void outword(unsigned X) {
+       if (isLittleEndian) {
+         OutputBuffer.push_back((X >>  0) & 255);
+         OutputBuffer.push_back((X >>  8) & 255);
+         OutputBuffer.push_back((X >> 16) & 255);
+         OutputBuffer.push_back((X >> 24) & 255);
+       } else {
+         OutputBuffer.push_back((X >> 24) & 255);
+         OutputBuffer.push_back((X >> 16) & 255);
+         OutputBuffer.push_back((X >>  8) & 255);
+         OutputBuffer.push_back((X >>  0) & 255);
+       }
+     }
+     void outaddr(uint64_t X) {
+       if (!is64Bit)
+         outword((unsigned)X);
+       else
+         assert(0 && "Emission of 64-bit data not implemented yet!");
+     }
+ 
+     // fix functions - Replace an existing entry at an offset.
+     void fixhalf(unsigned short X, unsigned Offset) {
+       unsigned char *P = &OutputBuffer[Offset];
+       P[0] = (X >> (isLittleEndian ?  0 : 8)) & 255;
+       P[1] = (X >> (isLittleEndian ?  8 : 0)) & 255;
+     }
+ 
+     void fixword(unsigned X, unsigned Offset) {
+       unsigned char *P = &OutputBuffer[Offset];
+       P[0] = (X >> (isLittleEndian ?  0 : 24)) & 255;
+       P[1] = (X >> (isLittleEndian ?  8 : 16)) & 255;
+       P[2] = (X >> (isLittleEndian ? 16 :  8)) & 255;
+       P[3] = (X >> (isLittleEndian ? 24 :  0)) & 255;
+     }
+ 
+     void fixaddr(uint64_t X, unsigned Offset) {
+       if (!is64Bit)
+         fixword((unsigned)X, Offset);
+       else
+         assert(0 && "Emission of 64-bit data not implemented yet!");
+     }
+ 
+   private:
+     void EmitDATASectionGlobal(GlobalVariable *GV);
+     void EmitBSSSectionGlobal(GlobalVariable *GV);
+     void EmitGlobal(GlobalVariable *GV);
+ 
+     void EmitSectionTableStringTable();
+     void EmitSectionTable();
+   };
+ }
+ 
+ #endif





From lattner at cs.uiuc.edu  Mon Jun 27 01:29:11 2005
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Mon, 27 Jun 2005 01:29:11 -0500
Subject: [llvm-commits] CVS: llvm/lib/CodeGen/ELFWriter.cpp 
Message-ID: <200506270629.BAA28563@zion.cs.uiuc.edu>



Changes in directory llvm/lib/CodeGen:

ELFWriter.cpp added (r1.1)
---
Log message:

iniital checkin of ELFWriter implementation

For now, the elf writer is only capable of emitting an empty elf file, with
a section table and a section table string table.  This will be enhanced
in the future :)


---
Diffs of the changes:  (+230 -0)

 ELFWriter.cpp |  230 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
 1 files changed, 230 insertions(+)


Index: llvm/lib/CodeGen/ELFWriter.cpp
diff -c /dev/null llvm/lib/CodeGen/ELFWriter.cpp:1.1
*** /dev/null	Mon Jun 27 01:29:10 2005
--- llvm/lib/CodeGen/ELFWriter.cpp	Mon Jun 27 01:29:00 2005
***************
*** 0 ****
--- 1,230 ----
+ //===-- ELFWriter.cpp - Target-independent ELF Writer code ----------------===//
+ //
+ //                     The LLVM Compiler Infrastructure
+ //
+ // This file was developed by the LLVM research group and is distributed under
+ // the University of Illinois Open Source License. See LICENSE.TXT for details.
+ //
+ //===----------------------------------------------------------------------===//
+ //
+ // This file implements the target-independent ELF writer.  This file writes out
+ // the ELF file in the following order:
+ //
+ //  #1. ELF Header
+ //  #2. '.data' section
+ //  #3. '.bss' section
+ //  ...
+ //  #X. '.shstrtab' section
+ //  #Y. Section Table
+ //
+ // The entries in the section table are laid out as:
+ //  #0. Null entry [required]
+ //  #1. ".data" entry - global variables with initializers.     [ if needed ]
+ //  #2. ".bss" entry  - global variables without initializers.  [ if needed ]
+ //  #3. ".text" entry - the program code
+ //  ...
+ //  #N. ".shstrtab" entry - String table for the section names.
+ 
+ //
+ // NOTE: This code should eventually be extended to support 64-bit ELF (this
+ // won't be hard), but we haven't done so yet!
+ //
+ //===----------------------------------------------------------------------===//
+ 
+ #include "llvm/CodeGen/ELFWriter.h"
+ #include "llvm/Module.h"
+ #include "llvm/Target/TargetMachine.h"
+ using namespace llvm;
+ 
+ ELFWriter::ELFWriter(std::ostream &o, TargetMachine &tm) : O(o), TM(tm) {
+   e_machine = 0;  // e_machine defaults to 'No Machine'
+   e_flags = 0;    // e_flags defaults to 0, no flags.
+ 
+   is64Bit = TM.getTargetData().getPointerSizeInBits() == 64;  
+   isLittleEndian = TM.getTargetData().isLittleEndian();
+ }
+ 
+ // doInitialization - Emit the file header and all of the global variables for
+ // the module to the ELF file.
+ bool ELFWriter::doInitialization(Module &M) {
+   outbyte(0x7F);                     // EI_MAG0
+   outbyte('E');                      // EI_MAG1
+   outbyte('L');                      // EI_MAG2
+   outbyte('F');                      // EI_MAG3
+   outbyte(is64Bit ? 2 : 1);          // EI_CLASS
+   outbyte(isLittleEndian ? 1 : 2);   // EI_DATA
+   outbyte(1);                        // EI_VERSION
+   for (unsigned i = OutputBuffer.size(); i != 16; ++i)
+     outbyte(0);                      // EI_PAD up to 16 bytes.
+   
+   // This should change for shared objects.
+   outhalf(1);                        // e_type = ET_REL
+   outhalf(e_machine);                // e_machine = whatever the target wants
+   outword(1);                        // e_version = 1
+   outaddr(0);                        // e_entry = 0 -> no entry point in .o file
+   outaddr(0);                        // e_phoff = 0 -> no program header for .o
+ 
+   ELFHeader_e_shoff_Offset = OutputBuffer.size();
+   outaddr(0);                        // e_shoff
+   outword(e_flags);                  // e_flags = whatever the target wants
+ 
+   assert(!is64Bit && "These sizes need to be adjusted for 64-bit!");
+   outhalf(52);                       // e_ehsize = ELF header size
+   outhalf(0);                        // e_phentsize = prog header entry size
+   outhalf(0);                        // e_phnum     = # prog header entries = 0
+   outhalf(40);                       // e_shentsize = sect header entry size
+ 
+   
+   ELFHeader_e_shnum_Offset = OutputBuffer.size();
+   outhalf(0);                        // e_shnum     = # of section header ents
+   ELFHeader_e_shstrndx_Offset = OutputBuffer.size();
+   outhalf(0);                        // e_shstrndx  = Section # of '.shstrtab'
+ 
+   // Add the null section.
+   SectionList.push_back(ELFSection());
+ 
+   // Okay, the ELF header has been completed, emit the .data section next.
+   ELFSection DataSection(".data", OutputBuffer.size());
+   for (Module::global_iterator I = M.global_begin(), E = M.global_end();
+        I != E; ++I)
+     EmitDATASectionGlobal(I);
+ 
+   // If the .data section is nonempty, add it to our list.
+   if ((DataSection.Size = OutputBuffer.size()-DataSection.Offset)) {
+     DataSection.Align = 4;   // FIXME: Compute!
+     SectionList.push_back(DataSection);
+   }
+ 
+   // Okay, emit the .bss section next.
+   ELFSection BSSSection(".bss", OutputBuffer.size());
+   for (Module::global_iterator I = M.global_begin(), E = M.global_end();
+        I != E; ++I)
+     EmitBSSSectionGlobal(I);
+ 
+   // If the .bss section is nonempty, add it to our list.
+   if ((BSSSection.Size = OutputBuffer.size()-BSSSection.Offset)) {
+     BSSSection.Align = 4;  // FIXME: Compute!
+     SectionList.push_back(BSSSection);
+   }
+ 
+   return false;
+ }
+ 
+ // isCOMM - A global variable should be emitted to the common area if it is zero
+ // initialized and has linkage that permits it to be merged with other globals.
+ static bool isCOMM(GlobalVariable *GV) {
+   return GV->getInitializer()->isNullValue() &&
+     (GV->hasLinkOnceLinkage() || GV->hasInternalLinkage() ||
+      GV->hasWeakLinkage());
+ }
+ 
+ // EmitDATASectionGlobal - Emit a global variable to the .data section if it
+ // belongs there.
+ void ELFWriter::EmitDATASectionGlobal(GlobalVariable *GV) {
+   if (!GV->hasInitializer()) return;
+ 
+   // Do not emit a symbol here if it should be emitted to the common area.
+   if (isCOMM(GV)) return;
+ 
+   EmitGlobal(GV);
+ }
+ 
+ void ELFWriter::EmitBSSSectionGlobal(GlobalVariable *GV) {
+   if (!GV->hasInitializer()) return;
+ 
+   // FIXME: We don't support BSS yet!
+   return;
+ 
+   EmitGlobal(GV);
+ }
+ 
+ void ELFWriter::EmitGlobal(GlobalVariable *GV) {
+ }
+ 
+ 
+ bool ELFWriter::runOnMachineFunction(MachineFunction &MF) {
+   return false;
+ }
+ 
+ /// doFinalization - Now that the module has been completely processed, emit
+ /// the ELF file to 'O'.
+ bool ELFWriter::doFinalization(Module &M) {
+   // Emit the string table for the sections in the ELF file we have.
+   EmitSectionTableStringTable();
+ 
+   // Emit the .o file section table.
+   EmitSectionTable();
+ 
+   // Emit the .o file to the specified stream.
+   O.write((char*)&OutputBuffer[0], OutputBuffer.size());
+ 
+   // Free the output buffer.
+   std::vector<unsigned char>().swap(OutputBuffer);
+   return false;
+ }
+ 
+ /// EmitSectionTableStringTable - This method adds and emits a section for the
+ /// ELF Section Table string table: the string table that holds all of the
+ /// section names.
+ void ELFWriter::EmitSectionTableStringTable() {
+   // First step: add the section for the string table to the list of sections:
+   SectionList.push_back(ELFSection(".shstrtab", OutputBuffer.size()));
+   SectionList.back().Type = 3;     // SHT_STRTAB
+ 
+   // Now that we know which section number is the .shstrtab section, update the
+   // e_shstrndx entry in the ELF header.
+   fixhalf(SectionList.size()-1, ELFHeader_e_shstrndx_Offset);
+ 
+   // Set the NameIdx of each section in the string table and emit the bytes for
+   // the string table.
+   unsigned Index = 0;
+ 
+   for (unsigned i = 0, e = SectionList.size(); i != e; ++i) {
+     // Set the index into the table.  Note if we have lots of entries with
+     // common suffixes, we could memoize them here if we cared.
+     SectionList[i].NameIdx = Index;
+ 
+     // Add the name to the output buffer, including the null terminator.
+     OutputBuffer.insert(OutputBuffer.end(), SectionList[i].Name.begin(),
+                         SectionList[i].Name.end());
+     // Add a null terminator.
+     OutputBuffer.push_back(0);
+ 
+     // Keep track of the number of bytes emitted to this section.
+     Index += SectionList[i].Name.size()+1;
+   }
+ 
+   // Set the size of .shstrtab now that we know what it is.
+   SectionList.back().Size = Index;
+ }
+ 
+ /// EmitSectionTable - Now that we have emitted the entire contents of the file
+ /// (all of the sections), emit the section table which informs the reader where
+ /// the boundaries are.
+ void ELFWriter::EmitSectionTable() {
+   // Now that all of the sections have been emitted, set the e_shnum entry in
+   // the ELF header.
+   fixhalf(SectionList.size(), ELFHeader_e_shnum_Offset);
+   
+   // Now that we know the offset in the file of the section table (which we emit
+   // next), update the e_shoff address in the ELF header.
+   fixaddr(OutputBuffer.size(), ELFHeader_e_shoff_Offset);
+   
+   // Emit all of the section table entries.
+   for (unsigned i = 0, e = SectionList.size(); i != e; ++i) {
+     const ELFSection &S = SectionList[i];
+     outword(S.NameIdx);  // sh_name - Symbol table name idx
+     outword(S.Type);     // sh_type - Section contents & semantics
+     outword(S.Flags);    // sh_flags - Section flags.
+     outaddr(S.Addr);     // sh_addr - The mem address this section appears in.
+     outaddr(S.Offset);   // sh_offset - The offset from the start of the file.
+     outword(S.Size);     // sh_size - The section size.
+     outword(S.Link);     // sh_link - Section header table index link.
+     outword(S.Info);     // sh_info - Auxillary information.
+     outword(S.Align);    // sh_addralign - Alignment of section.
+     outword(S.EntSize);  // sh_entsize - Size of each entry in the section.
+   }
+ 
+   // Release the memory allocated for the section list.
+   std::vector<ELFSection>().swap(SectionList);
+ }





From lattner at cs.uiuc.edu  Mon Jun 27 01:30:24 2005
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Mon, 27 Jun 2005 01:30:24 -0500
Subject: [llvm-commits] CVS: llvm/lib/Target/X86/X86ELFWriter.cpp X86.h
	X86TargetMachine.cpp 
Message-ID: <200506270630.BAA28627@zion.cs.uiuc.edu>



Changes in directory llvm/lib/Target/X86:

X86ELFWriter.cpp added (r1.1)
X86.h updated: 1.31 -> 1.32
X86TargetMachine.cpp updated: 1.79 -> 1.80
---
Log message:

Add support to the X86 backend for emitting ELF files.  To use this, we
currently use: llc t.bc --filetype=obj

This will produce a t.o file which is dumpable with readelf.  Currently
the file produced is empty, but the scaffolding to do more is now in place.


---
Diffs of the changes:  (+55 -2)

 X86.h                |    6 ++++++
 X86ELFWriter.cpp     |   34 ++++++++++++++++++++++++++++++++++
 X86TargetMachine.cpp |   17 +++++++++++++++--
 3 files changed, 55 insertions(+), 2 deletions(-)


Index: llvm/lib/Target/X86/X86ELFWriter.cpp
diff -c /dev/null llvm/lib/Target/X86/X86ELFWriter.cpp:1.1
*** /dev/null	Mon Jun 27 01:30:23 2005
--- llvm/lib/Target/X86/X86ELFWriter.cpp	Mon Jun 27 01:30:12 2005
***************
*** 0 ****
--- 1,34 ----
+ //===-- X86ELFWriter.cpp - Emit an ELF file for the X86 backend -----------===//
+ //
+ //                     The LLVM Compiler Infrastructure
+ //
+ // This file was developed by the LLVM research group and is distributed under
+ // the University of Illinois Open Source License. See LICENSE.TXT for details.
+ //
+ //===----------------------------------------------------------------------===//
+ //
+ // This file implements an ELF writer for the X86 backend.  The public interface
+ // to this file is the createX86ELFObjectWriterPass function.
+ //
+ //===----------------------------------------------------------------------===//
+ 
+ #include "X86.h"
+ #include "llvm/CodeGen/ELFWriter.h"
+ using namespace llvm;
+ 
+ namespace {
+   class X86ELFWriter : public ELFWriter {
+   public:
+     X86ELFWriter(std::ostream &O, TargetMachine &TM) : ELFWriter(O, TM) {
+       e_machine = 3;   // EM_386
+     }
+   };
+ }
+ 
+ /// createX86ELFObjectWriterPass - Returns a pass that outputs the generated
+ /// code as an ELF object file.
+ ///
+ FunctionPass *llvm::createX86ELFObjectWriterPass(std::ostream &O,
+                                                  TargetMachine &TM) {
+   return new X86ELFWriter(O, TM);
+ }


Index: llvm/lib/Target/X86/X86.h
diff -u llvm/lib/Target/X86/X86.h:1.31 llvm/lib/Target/X86/X86.h:1.32
--- llvm/lib/Target/X86/X86.h:1.31	Thu Apr 21 18:38:14 2005
+++ llvm/lib/Target/X86/X86.h	Mon Jun 27 01:30:12 2005
@@ -69,6 +69,12 @@
 ///
 FunctionPass *createX86CodePrinterPass(std::ostream &o,TargetMachine &tm);
 
+/// createX86ELFObjectWriterPass - Returns a pass that outputs the generated
+/// code as an ELF object file.
+///
+FunctionPass *createX86ELFObjectWriterPass(std::ostream &o, TargetMachine &tm);
+
+
 /// createX86EmitCodeToMemory - Returns a pass that converts a register
 /// allocated function into raw machine code in a dynamically
 /// allocated chunk of memory.


Index: llvm/lib/Target/X86/X86TargetMachine.cpp
diff -u llvm/lib/Target/X86/X86TargetMachine.cpp:1.79 llvm/lib/Target/X86/X86TargetMachine.cpp:1.80
--- llvm/lib/Target/X86/X86TargetMachine.cpp:1.79	Fri Jun 24 21:48:37 2005
+++ llvm/lib/Target/X86/X86TargetMachine.cpp	Mon Jun 27 01:30:12 2005
@@ -98,7 +98,8 @@
 // does to emit statically compiled machine code.
 bool X86TargetMachine::addPassesToEmitFile(PassManager &PM, std::ostream &Out,
                                            CodeGenFileType FileType) {
-  if (FileType != TargetMachine::AssemblyFile) return true;
+  if (FileType != TargetMachine::AssemblyFile && 
+      FileType != TargetMachine::ObjectFile) return true;
 
   // FIXME: Implement efficient support for garbage collection intrinsics.
   PM.add(createLowerGCPass());
@@ -146,7 +147,19 @@
     PM.add(createX86CodePrinterPass(std::cerr, *this));
 
   if (!DisableOutput)
-    PM.add(createX86CodePrinterPass(Out, *this));
+    switch (FileType) {
+    default:
+      assert(0 && "Unexpected filetype here!");
+    case TargetMachine::AssemblyFile:
+      PM.add(createX86CodePrinterPass(Out, *this));
+      break;
+    case TargetMachine::ObjectFile:
+      // FIXME: We only support emission of ELF files for now, this should check
+      // the target triple and decide on the format to write (e.g. COFF on
+      // win32).
+      PM.add(createX86ELFObjectWriterPass(Out, *this));
+      break;
+    }
 
   // Delete machine code for this function
   PM.add(createMachineCodeDeleter());





From alenhar2 at cs.uiuc.edu  Mon Jun 27 10:36:59 2005
From: alenhar2 at cs.uiuc.edu (Andrew Lenharth)
Date: Mon, 27 Jun 2005 10:36:59 -0500
Subject: [llvm-commits] CVS: llvm/lib/Target/Alpha/AlphaISelPattern.cpp
	AlphaRegisterInfo.td 
Message-ID: <200506271536.KAA27643@zion.cs.uiuc.edu>



Changes in directory llvm/lib/Target/Alpha:

AlphaISelPattern.cpp updated: 1.129 -> 1.130
AlphaRegisterInfo.td updated: 1.9 -> 1.10
---
Log message:

who said we had to use the return address in the return address register.  Might save a move in many cases

---
Diffs of the changes:  (+8 -5)

 AlphaISelPattern.cpp |    7 +++++--
 AlphaRegisterInfo.td |    6 +++---
 2 files changed, 8 insertions(+), 5 deletions(-)


Index: llvm/lib/Target/Alpha/AlphaISelPattern.cpp
diff -u llvm/lib/Target/Alpha/AlphaISelPattern.cpp:1.129 llvm/lib/Target/Alpha/AlphaISelPattern.cpp:1.130
--- llvm/lib/Target/Alpha/AlphaISelPattern.cpp:1.129	Sun Jun 26 18:01:11 2005
+++ llvm/lib/Target/Alpha/AlphaISelPattern.cpp	Mon Jun 27 10:36:48 2005
@@ -179,6 +179,10 @@
     {
       BuildMI(BB, Alpha::BIS, 2, Alpha::R26).addReg(RA).addReg(RA);
     }
+    unsigned getRA()
+    {
+      return RA;
+    }
 
   };
 }
@@ -2310,8 +2314,7 @@
       Select(N.getOperand(0));
       break;
     }
-    AlphaLowering.restoreRA(BB);
-    BuildMI(BB, Alpha::RET, 1, Alpha::R31).addReg(Alpha::R26); // Just emit a 'ret' instruction
+    BuildMI(BB, Alpha::RET, 1, Alpha::R31).addReg(AlphaLowering.getRA()); // Just emit a 'ret' instruction
     return;
 
   case ISD::TRUNCSTORE:


Index: llvm/lib/Target/Alpha/AlphaRegisterInfo.td
diff -u llvm/lib/Target/Alpha/AlphaRegisterInfo.td:1.9 llvm/lib/Target/Alpha/AlphaRegisterInfo.td:1.10
--- llvm/lib/Target/Alpha/AlphaRegisterInfo.td:1.9	Thu Feb 10 00:25:22 2005
+++ llvm/lib/Target/Alpha/AlphaRegisterInfo.td	Mon Jun 27 10:36:48 2005
@@ -78,14 +78,14 @@
   // $28 is undefined after any and all calls
 
 /// Register classes
+// Don't allocate 15, 28, 30, 31
 def GPRC : RegisterClass<i64, 64,
      // Volatile
      [R0, R1, R2, R3, R4, R5, R6, R7, R8, R16, R17, R18, R19, R20, R21, R22,
-      R23, R24, R25, R27,
+      R23, R24, R25, R26, R27,
      // Non-volatile
-     R9, R10, R11, R12, R13, R14, /*R15,*/ R26, /* R28, */ R29 /* R30, R31*/ ]>;
+     R9, R10, R11, R12, R13, R14, R29 ]>;
      // Note: R28 is reserved for the assembler
-     //leave FP alone
 
 // Don't allocate 15, 29, 30, 31
 // Allocation volatiles only for now





From alenhar2 at cs.uiuc.edu  Mon Jun 27 11:30:05 2005
From: alenhar2 at cs.uiuc.edu (Andrew Lenharth)
Date: Mon, 27 Jun 2005 11:30:05 -0500
Subject: [llvm-commits] CVS: llvm/lib/Target/Alpha/AlphaAsmPrinter.cpp 
Message-ID: <200506271630.LAA27994@zion.cs.uiuc.edu>



Changes in directory llvm/lib/Target/Alpha:

AlphaAsmPrinter.cpp updated: 1.16 -> 1.17
---
Log message:

make constant pool labels local

---
Diffs of the changes:  (+2 -2)

 AlphaAsmPrinter.cpp |    4 ++--
 1 files changed, 2 insertions(+), 2 deletions(-)


Index: llvm/lib/Target/Alpha/AlphaAsmPrinter.cpp
diff -u llvm/lib/Target/Alpha/AlphaAsmPrinter.cpp:1.16 llvm/lib/Target/Alpha/AlphaAsmPrinter.cpp:1.17
--- llvm/lib/Target/Alpha/AlphaAsmPrinter.cpp:1.16	Mon Jun  6 14:03:09 2005
+++ llvm/lib/Target/Alpha/AlphaAsmPrinter.cpp	Mon Jun 27 11:29:54 2005
@@ -135,7 +135,7 @@
   }
 
   case MachineOperand::MO_ConstantPoolIndex:
-    O << "CPI" << CurrentFnName << "_" << MO.getConstantPoolIndex();
+    O << "$CPI" << CurrentFnName << "_" << MO.getConstantPoolIndex();
     return;
 
   case MachineOperand::MO_ExternalSymbol:
@@ -226,7 +226,7 @@
   for (unsigned i = 0, e = CP.size(); i != e; ++i) {
     //    SwitchSection(O, "section .rodata, \"dr\"");
     emitAlignment(TD.getTypeAlignmentShift(CP[i]->getType()));
-    O << "CPI" << CurrentFnName << "_" << i << ":\t\t\t\t\t" << CommentString
+    O << "$CPI" << CurrentFnName << "_" << i << ":\t\t\t\t\t" << CommentString
       << *CP[i] << "\n";
     emitGlobalConstant(CP[i]);
   }





From alenhar2 at cs.uiuc.edu  Mon Jun 27 11:40:37 2005
From: alenhar2 at cs.uiuc.edu (Andrew Lenharth)
Date: Mon, 27 Jun 2005 11:40:37 -0500
Subject: [llvm-commits] CVS: llvm/lib/Target/Alpha/AlphaISelPattern.cpp 
Message-ID: <200506271640.LAA28141@zion.cs.uiuc.edu>



Changes in directory llvm/lib/Target/Alpha:

AlphaISelPattern.cpp updated: 1.130 -> 1.131
---
Log message:

missed a load

---
Diffs of the changes:  (+7 -3)

 AlphaISelPattern.cpp |   10 +++++++---
 1 files changed, 7 insertions(+), 3 deletions(-)


Index: llvm/lib/Target/Alpha/AlphaISelPattern.cpp
diff -u llvm/lib/Target/Alpha/AlphaISelPattern.cpp:1.130 llvm/lib/Target/Alpha/AlphaISelPattern.cpp:1.131
--- llvm/lib/Target/Alpha/AlphaISelPattern.cpp:1.130	Mon Jun 27 10:36:48 2005
+++ llvm/lib/Target/Alpha/AlphaISelPattern.cpp	Mon Jun 27 11:40:26 2005
@@ -265,9 +265,6 @@
 
   MachineBasicBlock& BB = MF.front();
 
-  //Handle the return address
-  //BuildMI(&BB, Alpha::IDEF, 0, Alpha::R26);
-
   unsigned args_int[] = {Alpha::R16, Alpha::R17, Alpha::R18,
                          Alpha::R19, Alpha::R20, Alpha::R21};
   unsigned args_float[] = {Alpha::F16, Alpha::F17, Alpha::F18,
@@ -1307,6 +1304,13 @@
       SDOperand Address = N.getOperand(1);
       Select(Chain);
 
+      if (EnableAlphaLSMark)
+      {
+        int i = getValueOffset(dyn_cast<SrcValueSDNode>(N.getOperand(2))->getValue());
+        int j = getFunctionOffset(BB->getParent()->getFunction());
+        BuildMI(BB, Alpha::MEMLABEL, 3).addImm(j).addImm(i).addImm(getUID());
+      }
+
       if (Address.getOpcode() == ISD::GlobalAddress) {
         AlphaLowering.restoreGP(BB);
         has_sym = true;





From alenhar2 at cs.uiuc.edu  Mon Jun 27 12:15:47 2005
From: alenhar2 at cs.uiuc.edu (Andrew Lenharth)
Date: Mon, 27 Jun 2005 12:15:47 -0500
Subject: [llvm-commits] CVS: llvm/lib/Target/Alpha/AlphaISelPattern.cpp
	AlphaInstrInfo.td 
Message-ID: <200506271715.MAA28830@zion.cs.uiuc.edu>



Changes in directory llvm/lib/Target/Alpha:

AlphaISelPattern.cpp updated: 1.131 -> 1.132
AlphaInstrInfo.td updated: 1.45 -> 1.46
---
Log message:

Reduce use of pseudo ops
Namely, output the rellocation flags explicitly when loading constants.
Added benifit: save a load when loading from the constant pool.



---
Diffs of the changes:  (+41 -8)

 AlphaISelPattern.cpp |   33 +++++++++++++++++++++++++++------
 AlphaInstrInfo.td    |   16 ++++++++++++++--
 2 files changed, 41 insertions(+), 8 deletions(-)


Index: llvm/lib/Target/Alpha/AlphaISelPattern.cpp
diff -u llvm/lib/Target/Alpha/AlphaISelPattern.cpp:1.131 llvm/lib/Target/Alpha/AlphaISelPattern.cpp:1.132
--- llvm/lib/Target/Alpha/AlphaISelPattern.cpp:1.131	Mon Jun 27 11:40:26 2005
+++ llvm/lib/Target/Alpha/AlphaISelPattern.cpp	Mon Jun 27 12:15:36 2005
@@ -852,6 +852,18 @@
   case Alpha::STB: return Alpha::STB_SYM;
   }
 }
+static unsigned GetRelVersion(unsigned opcode)
+{
+  switch (opcode) {
+  default: assert(0 && "unknown load or store"); return 0;
+  case Alpha::LDQ: return Alpha::LDQr;
+  case Alpha::LDS: return Alpha::LDSr;
+  case Alpha::LDT: return Alpha::LDTr;
+  case Alpha::LDL: return Alpha::LDLr;
+  case Alpha::LDBU: return Alpha::LDBUr;
+  case Alpha::LDWU: return Alpha::LDWUr;
+  }
+}
 
 void AlphaISel::MoveFP2Int(unsigned src, unsigned dst, bool isDouble)
 {
@@ -1234,9 +1246,11 @@
       }
       else if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(Address)) {
         AlphaLowering.restoreGP(BB);
-        Opc = GetSymVersion(Opc);
+        Opc = GetRelVersion(Opc);
         has_sym = true;
-        BuildMI(BB, Opc, 1, Result).addConstantPoolIndex(CP->getIndex());
+        Tmp1 = MakeReg(MVT::i64);
+        BuildMI(BB, Alpha::LDAHr, 2, Tmp1).addConstantPoolIndex(CP->getIndex()).addReg(Alpha::R29);
+        BuildMI(BB, Opc, 2, Result).addConstantPoolIndex(CP->getIndex()).addReg(Tmp1);
       }
       else if(Address.getOpcode() == ISD::FrameIndex) {
         BuildMI(BB, Opc, 2, Result)
@@ -1321,7 +1335,9 @@
       {
         AlphaLowering.restoreGP(BB);
         has_sym = true;
-        BuildMI(BB, Alpha::LDS_SYM, 1, Tmp1).addConstantPoolIndex(CP->getIndex());
+        Tmp2 = MakeReg(MVT::i64);
+        BuildMI(BB, Alpha::LDAHr, 2, Tmp2).addConstantPoolIndex(CP->getIndex()).addReg(Alpha::R29);
+        BuildMI(BB, Alpha::LDSr, 2, Tmp1).addConstantPoolIndex(CP->getIndex()).addReg(Tmp2);
       }
       else if(Address.getOpcode() == ISD::FrameIndex) {
         Tmp2 = cast<FrameIndexSDNode>(Address)->getIndex();
@@ -1532,9 +1548,11 @@
       }
       else if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(Address)) {
         AlphaLowering.restoreGP(BB);
-        Opc = GetSymVersion(Opc);
+        Opc = GetRelVersion(Opc);
         has_sym = true;
-        BuildMI(BB, Opc, 1, Result).addConstantPoolIndex(CP->getIndex());
+        Tmp1 = MakeReg(MVT::i64);
+        BuildMI(BB, Alpha::LDAHr, 2, Tmp1).addConstantPoolIndex(CP->getIndex()).addReg(Alpha::R29);
+        BuildMI(BB, Opc, 2, Result).addConstantPoolIndex(CP->getIndex()).addReg(Tmp1);
       }
       else if(Address.getOpcode() == ISD::FrameIndex) {
         BuildMI(BB, Opc, 2, Result)
@@ -2219,7 +2237,10 @@
         ConstantUInt *C = ConstantUInt::get(Type::getPrimitiveType(Type::ULongTyID) , val);
         unsigned CPI = CP->getConstantPoolIndex(C);
         AlphaLowering.restoreGP(BB);
-        BuildMI(BB, Alpha::LDQ_SYM, 1, Result).addConstantPoolIndex(CPI);
+        has_sym = true;
+        Tmp1 = MakeReg(MVT::i64);
+        BuildMI(BB, Alpha::LDAHr, 2, Tmp1).addConstantPoolIndex(CPI).addReg(Alpha::R29);
+        BuildMI(BB, Alpha::LDQr, 2, Result).addConstantPoolIndex(CPI).addReg(Tmp1);
       }
       return Result;
     }


Index: llvm/lib/Target/Alpha/AlphaInstrInfo.td
diff -u llvm/lib/Target/Alpha/AlphaInstrInfo.td:1.45 llvm/lib/Target/Alpha/AlphaInstrInfo.td:1.46
--- llvm/lib/Target/Alpha/AlphaInstrInfo.td:1.45	Thu Jun 23 18:42:05 2005
+++ llvm/lib/Target/Alpha/AlphaInstrInfo.td	Mon Jun 27 12:15:36 2005
@@ -333,7 +333,6 @@
 def JSR_COROUTINE : MForm< 0x1A, (ops GPRC:$RD, GPRC:$RS), "jsr_coroutine $RD,($RS),1">; //Jump to subroutine return
 def BR : BForm<0x30, (ops GPRC:$RD, s21imm:$DISP), "br $RD,$DISP">; //Branch
 
-let Uses = [R28] in {
 //Stores, int
 def STB : MForm<0x0E, (ops GPRC:$RA, s16imm:$DISP, GPRC:$RB), "stb $RA,$DISP($RB)">; // Store byte
 def STW : MForm<0x0D, (ops GPRC:$RA, s16imm:$DISP, GPRC:$RB), "stw $RA,$DISP($RB)">; // Store word
@@ -353,13 +352,26 @@
 //Loads, float
 def LDS : MForm<0x22, (ops FPRC:$RA, s16imm:$DISP, GPRC:$RB), "lds $RA,$DISP($RB)">; //Load S_floating
 def LDT : MForm<0x23, (ops FPRC:$RA, s16imm:$DISP, GPRC:$RB), "ldt $RA,$DISP($RB)">; //Load T_floating
-}
 
 //Load address
 def LDA : MForm<0x08, (ops GPRC:$RA, s16imm:$DISP, GPRC:$RB), "lda $RA,$DISP($RB)">;  //Load address
 def LDAH : MForm<0x08, (ops GPRC:$RA, s16imm:$DISP, GPRC:$RB), "ldah $RA,$DISP($RB)">;  //Load address high
 
 
+//Loads, int, Rellocated form
+def LDLr : MForm<0x28, (ops GPRC:$RA, s16imm:$DISP, GPRC:$RB), "ldl $RA,$DISP($RB) !gprellow">; // Load sign-extended longword
+def LDQr : MForm<0x29, (ops GPRC:$RA, s16imm:$DISP, GPRC:$RB), "ldq $RA,$DISP($RB) !gprellow">; //Load quadword
+def LDBUr : MForm<0x0A, (ops GPRC:$RA, s16imm:$DISP, GPRC:$RB), "ldbu $RA,$DISP($RB) !gprellow">; //Load zero-extended byte
+def LDWUr : MForm<0x0C, (ops GPRC:$RA, s16imm:$DISP, GPRC:$RB), "ldwu $RA,$DISP($RB) !gprellow">; //Load zero-extended word
+
+//Loads, float, Rellocated form
+def LDSr : MForm<0x22, (ops FPRC:$RA, s16imm:$DISP, GPRC:$RB), "lds $RA,$DISP($RB) !gprellow">; //Load S_floating
+def LDTr : MForm<0x23, (ops FPRC:$RA, s16imm:$DISP, GPRC:$RB), "ldt $RA,$DISP($RB) !gprellow">; //Load T_floating
+
+//Load address, rellocated form
+def LDAHr : MForm<0x08, (ops GPRC:$RA, s16imm:$DISP, GPRC:$RB), "ldah $RA,$DISP($RB) !gprelhigh">;  //Load address high
+
+
 //Branches, int
 def BEQ : BForm<0x39, (ops GPRC:$RA, s21imm:$DISP), "beq $RA,$DISP">; //Branch if = zero
 def BGE : BForm<0x3E, (ops GPRC:$RA, s21imm:$DISP), "bge $RA,$DISP">; //Branch if >= zero





From alenhar2 at cs.uiuc.edu  Mon Jun 27 12:39:28 2005
From: alenhar2 at cs.uiuc.edu (Andrew Lenharth)
Date: Mon, 27 Jun 2005 12:39:28 -0500
Subject: [llvm-commits] CVS: llvm/lib/Target/Alpha/AlphaISelPattern.cpp 
Message-ID: <200506271739.MAA29273@zion.cs.uiuc.edu>



Changes in directory llvm/lib/Target/Alpha:

AlphaISelPattern.cpp updated: 1.132 -> 1.133
---
Log message:

Misha happification patch

---
Diffs of the changes:  (+142 -91)

 AlphaISelPattern.cpp |  233 +++++++++++++++++++++++++++++++--------------------
 1 files changed, 142 insertions(+), 91 deletions(-)


Index: llvm/lib/Target/Alpha/AlphaISelPattern.cpp
diff -u llvm/lib/Target/Alpha/AlphaISelPattern.cpp:1.132 llvm/lib/Target/Alpha/AlphaISelPattern.cpp:1.133
--- llvm/lib/Target/Alpha/AlphaISelPattern.cpp:1.132	Mon Jun 27 12:15:36 2005
+++ llvm/lib/Target/Alpha/AlphaISelPattern.cpp	Mon Jun 27 12:39:17 2005
@@ -35,20 +35,20 @@
 
 namespace llvm {
   cl::opt<bool> EnableAlphaIDIV("enable-alpha-intfpdiv",
-                             cl::desc("Use the FP div instruction for integer div when possible"),
+    cl::desc("Use the FP div instruction for integer div when possible"),
                              cl::Hidden);
   cl::opt<bool> EnableAlphaFTOI("enable-alpha-FTOI",
-                             cl::desc("Enable use of ftoi* and itof* instructions (ev6 and higher)"),
+    cl::desc("Enable use of ftoi* and itof* instructions (ev6 and higher)"),
                              cl::Hidden);
   cl::opt<bool> EnableAlphaCT("enable-alpha-CT",
-                              cl::desc("Enable use of the ctpop, ctlz, and cttz instructions"),
+    cl::desc("Enable use of the ctpop, ctlz, and cttz instructions"),
                               cl::Hidden);
   cl::opt<bool> EnableAlphaCount("enable-alpha-count",
-                             cl::desc("Print estimates on live ins and outs"),
-                             cl::Hidden);
+    cl::desc("Print estimates on live ins and outs"),
+    cl::Hidden);
   cl::opt<bool> EnableAlphaLSMark("enable-alpha-lsmark",
-                             cl::desc("Emit symbols to correlate Mem ops to LLVM Values"),
-                             cl::Hidden);
+    cl::desc("Emit symbols to correlate Mem ops to LLVM Values"),
+    cl::Hidden);
 }
 
 namespace {
@@ -209,8 +209,9 @@
         } else {
           int SSFI = MF.getFrameInfo()->CreateStackObject(8, 8);
           SDOperand StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
-          SDOperand Store = DAG.getNode(ISD::STORE, MVT::Other, DAG.getEntryNode(),
-                                        Op.getOperand(0), StackSlot, DAG.getSrcValue(NULL));
+          SDOperand Store = DAG.getNode(ISD::STORE, MVT::Other, 
+                                        DAG.getEntryNode(), Op.getOperand(0), 
+                                        StackSlot, DAG.getSrcValue(NULL));
           SRC = DAG.getLoad(Op.getValueType(), Store.getValue(0), StackSlot,
                             DAG.getSrcValue(NULL));
         }
@@ -294,7 +295,8 @@
       case MVT::i16:
       case MVT::i32:
       case MVT::i64:
-        args_int[count] = AddLiveIn(MF, args_int[count], getRegClassFor(MVT::i64));
+        args_int[count] = AddLiveIn(MF, args_int[count], 
+                                    getRegClassFor(MVT::i64));
         argt = DAG.getCopyFromReg(args_int[count], VT, DAG.getRoot());
         if (VT != MVT::i64)
           argt = DAG.getNode(ISD::TRUNCATE, VT, argt);
@@ -326,14 +328,16 @@
       int FI = MFI->CreateFixedObject(8, -8 * (6 - i));
       if (i == 0) VarArgsBase = FI;
       SDOperand SDFI = DAG.getFrameIndex(FI, MVT::i64);
-      LS.push_back(DAG.getNode(ISD::STORE, MVT::Other, DAG.getRoot(), argt, SDFI, DAG.getSrcValue(NULL)));
+      LS.push_back(DAG.getNode(ISD::STORE, MVT::Other, DAG.getRoot(), argt, 
+                               SDFI, DAG.getSrcValue(NULL)));
       
       if (args_float[i] < 1024)
         args_float[i] = AddLiveIn(MF,args_float[i], getRegClassFor(MVT::f64));
       argt = DAG.getCopyFromReg(args_float[i], MVT::f64, DAG.getRoot());
       FI = MFI->CreateFixedObject(8, - 8 * (12 - i));
       SDFI = DAG.getFrameIndex(FI, MVT::i64);
-      LS.push_back(DAG.getNode(ISD::STORE, MVT::Other, DAG.getRoot(), argt, SDFI, DAG.getSrcValue(NULL)));
+      LS.push_back(DAG.getNode(ISD::STORE, MVT::Other, DAG.getRoot(), argt, 
+                               SDFI, DAG.getSrcValue(NULL)));
     }
 
     //Set up a token factor with all the stack traffic
@@ -412,11 +416,14 @@
 }
 
 std::pair<SDOperand, SDOperand>
-AlphaTargetLowering::LowerVAStart(SDOperand Chain, SelectionDAG &DAG, SDOperand Dest) {
+AlphaTargetLowering::LowerVAStart(SDOperand Chain, SelectionDAG &DAG, 
+                                  SDOperand Dest) {
   // vastart just stores the address of the VarArgsBase and VarArgsOffset
   SDOperand FR  = DAG.getFrameIndex(VarArgsBase, MVT::i64);
-  SDOperand S1  = DAG.getNode(ISD::STORE, MVT::Other, Chain, FR, Dest, DAG.getSrcValue(NULL));
-  SDOperand SA2 = DAG.getNode(ISD::ADD, MVT::i64, Dest, DAG.getConstant(8, MVT::i64));
+  SDOperand S1  = DAG.getNode(ISD::STORE, MVT::Other, Chain, FR, Dest, 
+                              DAG.getSrcValue(NULL));
+  SDOperand SA2 = DAG.getNode(ISD::ADD, MVT::i64, Dest, 
+                              DAG.getConstant(8, MVT::i64));
   SDOperand S2  = DAG.getNode(ISD::TRUNCSTORE, MVT::Other,   S1, 
                               DAG.getConstant(VarArgsOffset, MVT::i64), SA2, 
                               DAG.getSrcValue(NULL), MVT::i32);
@@ -429,8 +436,8 @@
   SDOperand Base = DAG.getLoad(MVT::i64, Chain, VAList, DAG.getSrcValue(NULL));
   SDOperand Tmp = DAG.getNode(ISD::ADD, MVT::i64, VAList, 
                               DAG.getConstant(8, MVT::i64));
-  SDOperand Offset = DAG.getNode(ISD::SEXTLOAD, MVT::i64, Base.getValue(1), Tmp, 
-                                 DAG.getSrcValue(NULL), MVT::i32);
+  SDOperand Offset = DAG.getNode(ISD::SEXTLOAD, MVT::i64, Base.getValue(1), 
+                                 Tmp, DAG.getSrcValue(NULL), MVT::i32);
   SDOperand DataPtr = DAG.getNode(ISD::ADD, MVT::i64, Base, Offset);
   if (ArgTy->isFloatingPoint())
   {
@@ -455,7 +462,8 @@
 
   SDOperand NewOffset = DAG.getNode(ISD::ADD, MVT::i64, Offset, 
                                     DAG.getConstant(8, MVT::i64));
-  SDOperand Update = DAG.getNode(ISD::TRUNCSTORE, MVT::Other, Result.getValue(1), NewOffset, 
+  SDOperand Update = DAG.getNode(ISD::TRUNCSTORE, MVT::Other, 
+                                 Result.getValue(1), NewOffset, 
                                  Tmp, DAG.getSrcValue(NULL), MVT::i32);
   Result = DAG.getNode(ISD::TRUNCATE, getValueType(ArgTy), Result);
 
@@ -466,7 +474,8 @@
 LowerVACopy(SDOperand Chain, SDOperand Src, SDOperand Dest, 
             SelectionDAG &DAG) {
   //Default to returning the input list
-  SDOperand Val = DAG.getLoad(getPointerTy(), Chain, Src, DAG.getSrcValue(NULL));
+  SDOperand Val = DAG.getLoad(getPointerTy(), Chain, Src, 
+                              DAG.getSrcValue(NULL));
   SDOperand Result = DAG.getNode(ISD::STORE, MVT::Other, Val.getValue(1),
                                  Val, Dest, DAG.getSrcValue(NULL));
   SDOperand NP = DAG.getNode(ISD::ADD, MVT::i64, Src, 
@@ -521,7 +530,8 @@
   int max_depth;
 
 public:
-  AlphaISel(TargetMachine &TM) : SelectionDAGISel(AlphaLowering), AlphaLowering(TM)
+  AlphaISel(TargetMachine &TM) : SelectionDAGISel(AlphaLowering), 
+    AlphaLowering(TM)
   {}
 
   /// InstructionSelectBasicBlock - This callback is invoked by
@@ -541,7 +551,8 @@
     if(has_sym)
       ++count_ins;
     if(EnableAlphaCount)
-      std::cerr << "COUNT: " << BB->getParent()->getFunction ()->getName() << " " 
+      std::cerr << "COUNT: " 
+                << BB->getParent()->getFunction ()->getName() << " " 
                 << BB->getNumber() << " " 
                 << max_depth << " "
                 << count_ins << " "
@@ -582,9 +593,11 @@
            E = MF.livein_end(); LI != E; ++LI) {
       const TargetRegisterClass *RC = RegMap->getRegClass(LI->second);
       if (RC == Alpha::GPRCRegisterClass) {
-        BuildMI(BB, Alpha::BIS, 2, LI->second).addReg(LI->first).addReg(LI->first);
+        BuildMI(BB, Alpha::BIS, 2, LI->second).addReg(LI->first)
+          .addReg(LI->first);
       } else if (RC == Alpha::FPRCRegisterClass) {
-        BuildMI(BB, Alpha::CPYS, 2, LI->second).addReg(LI->first).addReg(LI->first);
+        BuildMI(BB, Alpha::CPYS, 2, LI->second).addReg(LI->first)
+          .addReg(LI->first);
       } else {
         assert(0 && "Unknown regclass!");
       }
@@ -911,7 +924,6 @@
   unsigned Opc, Tmp1, Tmp2, Tmp3;
   SetCCSDNode *SetCC = dyn_cast<SetCCSDNode>(Node);
 
-  //assert(SetCC->getOperand(0).getValueType() != MVT::f32 && "SetCC f32 should have been promoted");
   bool rev = false;
   bool inv = false;
 
@@ -1013,7 +1025,8 @@
         case ISD::SETGE:  Opc = Alpha::BGE; break;
         case ISD::SETULT: assert(0 && "x (unsigned) < 0 is never true"); break;
         case ISD::SETUGT: Opc = Alpha::BNE; break;
-        case ISD::SETULE: Opc = Alpha::BEQ; break; //Technically you could have this CC
+        //Technically you could have this CC
+        case ISD::SETULE: Opc = Alpha::BEQ; break;
         case ISD::SETUGE: assert(0 && "x (unsgined >= 0 is always true"); break;
         case ISD::SETNE:  Opc = Alpha::BNE; break;
         }
@@ -1029,8 +1042,8 @@
         return;
       }
     } else { //FP
-      //Any comparison between 2 values should be codegened as an folded branch, as moving
-      //CC to the integer register is very expensive
+      //Any comparison between 2 values should be codegened as an folded 
+      //branch, as moving CC to the integer register is very expensive
       //for a cmp b: c = a - b;
       //a = b: c = 0
       //a < b: c < 0
@@ -1172,7 +1185,8 @@
       else
       {
         Tmp1 = SelectExpr(N.getOperand(0)); //Cond
-        BuildMI(BB, Alpha::FCMOVEQ_INT, 3, Result).addReg(TV).addReg(FV).addReg(Tmp1);
+        BuildMI(BB, Alpha::FCMOVEQ_INT, 3, Result).addReg(TV).addReg(FV)
+          .addReg(Tmp1);
 //         // Spill the cond to memory and reload it from there.
 //         unsigned Tmp4 = MakeReg(MVT::f64);
 //         MoveIntFP(Tmp1, Tmp4, true);
@@ -1233,7 +1247,8 @@
 
       if (EnableAlphaLSMark)
       {
-        int i = getValueOffset(dyn_cast<SrcValueSDNode>(N.getOperand(2))->getValue());
+        int i = getValueOffset(dyn_cast<SrcValueSDNode>(N.getOperand(2))
+                                  ->getValue());
         int j = getFunctionOffset(BB->getParent()->getFunction());
         BuildMI(BB, Alpha::MEMLABEL, 3).addImm(j).addImm(i).addImm(getUID());
       }
@@ -1242,15 +1257,18 @@
         AlphaLowering.restoreGP(BB);
         Opc = GetSymVersion(Opc);
         has_sym = true;
-        BuildMI(BB, Opc, 1, Result).addGlobalAddress(cast<GlobalAddressSDNode>(Address)->getGlobal());
+        BuildMI(BB, Opc, 1, Result)
+          .addGlobalAddress(cast<GlobalAddressSDNode>(Address)->getGlobal());
       }
       else if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(Address)) {
         AlphaLowering.restoreGP(BB);
         Opc = GetRelVersion(Opc);
         has_sym = true;
         Tmp1 = MakeReg(MVT::i64);
-        BuildMI(BB, Alpha::LDAHr, 2, Tmp1).addConstantPoolIndex(CP->getIndex()).addReg(Alpha::R29);
-        BuildMI(BB, Opc, 2, Result).addConstantPoolIndex(CP->getIndex()).addReg(Tmp1);
+        BuildMI(BB, Alpha::LDAHr, 2, Tmp1).addConstantPoolIndex(CP->getIndex())
+          .addReg(Alpha::R29);
+        BuildMI(BB, Opc, 2, Result).addConstantPoolIndex(CP->getIndex())
+          .addReg(Tmp1);
       }
       else if(Address.getOpcode() == ISD::FrameIndex) {
         BuildMI(BB, Opc, 2, Result)
@@ -1266,9 +1284,11 @@
   case ISD::ConstantFP:
     if (ConstantFPSDNode *CN = dyn_cast<ConstantFPSDNode>(N)) {
       if (CN->isExactlyValue(+0.0)) {
-        BuildMI(BB, Alpha::CPYS, 2, Result).addReg(Alpha::F31).addReg(Alpha::F31);
+        BuildMI(BB, Alpha::CPYS, 2, Result).addReg(Alpha::F31)
+          .addReg(Alpha::F31);
       } else if ( CN->isExactlyValue(-0.0)) {
-        BuildMI(BB, Alpha::CPYSN, 2, Result).addReg(Alpha::F31).addReg(Alpha::F31);
+        BuildMI(BB, Alpha::CPYSN, 2, Result).addReg(Alpha::F31)
+          .addReg(Alpha::F31);
       } else {
         abort();
       }
@@ -1279,11 +1299,15 @@
   case ISD::MUL:
   case ISD::ADD:
   case ISD::SUB:
-    switch( opcode ) {
-    case ISD::MUL: Opc = DestType == MVT::f64 ? Alpha::MULT : Alpha::MULS; break;
-    case ISD::ADD: Opc = DestType == MVT::f64 ? Alpha::ADDT : Alpha::ADDS; break;
-    case ISD::SUB: Opc = DestType == MVT::f64 ? Alpha::SUBT : Alpha::SUBS; break;
-    case ISD::SDIV: Opc = DestType == MVT::f64 ? Alpha::DIVT : Alpha::DIVS; break;
+  switch( opcode ) {
+      case ISD::MUL: Opc = DestType == MVT::f64 ? Alpha::MULT : Alpha::MULS; 
+      break;
+      case ISD::ADD: Opc = DestType == MVT::f64 ? Alpha::ADDT : Alpha::ADDS; 
+      break;
+      case ISD::SUB: Opc = DestType == MVT::f64 ? Alpha::SUBT : Alpha::SUBS; 
+      break;
+      case ISD::SDIV: Opc = DestType == MVT::f64 ? Alpha::DIVT : Alpha::DIVS;
+      break;
     };
 
     ConstantFPSDNode *CN;
@@ -1320,7 +1344,8 @@
 
       if (EnableAlphaLSMark)
       {
-        int i = getValueOffset(dyn_cast<SrcValueSDNode>(N.getOperand(2))->getValue());
+        int i = getValueOffset(dyn_cast<SrcValueSDNode>(N.getOperand(2))
+                                  ->getValue());
         int j = getFunctionOffset(BB->getParent()->getFunction());
         BuildMI(BB, Alpha::MEMLABEL, 3).addImm(j).addImm(i).addImm(getUID());
       }
@@ -1328,7 +1353,8 @@
       if (Address.getOpcode() == ISD::GlobalAddress) {
         AlphaLowering.restoreGP(BB);
         has_sym = true;
-        BuildMI(BB, Alpha::LDS_SYM, 1, Tmp1).addGlobalAddress(cast<GlobalAddressSDNode>(Address)->getGlobal());
+        BuildMI(BB, Alpha::LDS_SYM, 1, Tmp1)
+          .addGlobalAddress(cast<GlobalAddressSDNode>(Address)->getGlobal());
       }
       else if (ConstantPoolSDNode *CP =
                dyn_cast<ConstantPoolSDNode>(N.getOperand(1)))
@@ -1336,8 +1362,10 @@
         AlphaLowering.restoreGP(BB);
         has_sym = true;
         Tmp2 = MakeReg(MVT::i64);
-        BuildMI(BB, Alpha::LDAHr, 2, Tmp2).addConstantPoolIndex(CP->getIndex()).addReg(Alpha::R29);
-        BuildMI(BB, Alpha::LDSr, 2, Tmp1).addConstantPoolIndex(CP->getIndex()).addReg(Tmp2);
+        BuildMI(BB, Alpha::LDAHr, 2, Tmp2).addConstantPoolIndex(CP->getIndex())
+          .addReg(Alpha::R29);
+        BuildMI(BB, Alpha::LDSr, 2, Tmp1).addConstantPoolIndex(CP->getIndex())
+          .addReg(Tmp2);
       }
       else if(Address.getOpcode() == ISD::FrameIndex) {
         Tmp2 = cast<FrameIndexSDNode>(Address)->getIndex();
@@ -1437,8 +1465,10 @@
       BuildMI(BB, Alpha::UMULH, 2, Tmp3).addReg(Tmp1).addReg(Tmp2);
       unsigned V1 = MakeReg(MVT::i64);
       unsigned V2 = MakeReg(MVT::i64);
-      BuildMI(BB, Alpha::CMOVGE, 3, V1).addReg(Tmp2).addReg(Alpha::R31).addReg(Tmp1);
-      BuildMI(BB, Alpha::CMOVGE, 3, V2).addReg(Tmp1).addReg(Alpha::R31).addReg(Tmp2);
+      BuildMI(BB, Alpha::CMOVGE, 3, V1).addReg(Tmp2).addReg(Alpha::R31)
+        .addReg(Tmp1);
+      BuildMI(BB, Alpha::CMOVGE, 3, V2).addReg(Tmp1).addReg(Alpha::R31)
+        .addReg(Tmp2);
       unsigned IRes = MakeReg(MVT::i64);
       BuildMI(BB, Alpha::SUBQ, 2, IRes).addReg(Tmp3).addReg(V1);
       BuildMI(BB, Alpha::SUBQ, 2, Result).addReg(IRes).addReg(V2);
@@ -1535,7 +1565,8 @@
 
       if (EnableAlphaLSMark)
       {
-        int i = getValueOffset(dyn_cast<SrcValueSDNode>(N.getOperand(2))->getValue());
+        int i = getValueOffset(dyn_cast<SrcValueSDNode>(N.getOperand(2))
+                                 ->getValue());
         int j = getFunctionOffset(BB->getParent()->getFunction());
         BuildMI(BB, Alpha::MEMLABEL, 3).addImm(j).addImm(i).addImm(getUID());
       }
@@ -1544,15 +1575,18 @@
         AlphaLowering.restoreGP(BB);
         Opc = GetSymVersion(Opc);
         has_sym = true;
-        BuildMI(BB, Opc, 1, Result).addGlobalAddress(cast<GlobalAddressSDNode>(Address)->getGlobal());
+        BuildMI(BB, Opc, 1, Result)
+          .addGlobalAddress(cast<GlobalAddressSDNode>(Address)->getGlobal());
       }
       else if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(Address)) {
         AlphaLowering.restoreGP(BB);
         Opc = GetRelVersion(Opc);
         has_sym = true;
         Tmp1 = MakeReg(MVT::i64);
-        BuildMI(BB, Alpha::LDAHr, 2, Tmp1).addConstantPoolIndex(CP->getIndex()).addReg(Alpha::R29);
-        BuildMI(BB, Opc, 2, Result).addConstantPoolIndex(CP->getIndex()).addReg(Tmp1);
+        BuildMI(BB, Alpha::LDAHr, 2, Tmp1).addConstantPoolIndex(CP->getIndex())
+          .addReg(Alpha::R29);
+        BuildMI(BB, Opc, 2, Result).addConstantPoolIndex(CP->getIndex())
+          .addReg(Tmp1);
       }
       else if(Address.getOpcode() == ISD::FrameIndex) {
         BuildMI(BB, Opc, 2, Result)
@@ -1606,11 +1640,13 @@
         case MVT::i16:
         case MVT::i32:
         case MVT::i64:
-          BuildMI(BB, Alpha::BIS, 2, args_int[i]).addReg(argvregs[i]).addReg(argvregs[i]);
+          BuildMI(BB, Alpha::BIS, 2, args_int[i]).addReg(argvregs[i])
+            .addReg(argvregs[i]);
           break;
         case MVT::f32:
         case MVT::f64:
-          BuildMI(BB, Alpha::CPYS, 2, args_float[i]).addReg(argvregs[i]).addReg(argvregs[i]);
+          BuildMI(BB, Alpha::CPYS, 2, args_float[i]).addReg(argvregs[i])
+            .addReg(argvregs[i]);
           break;
         }
       }
@@ -1629,13 +1665,16 @@
         case MVT::i16:
         case MVT::i32:
         case MVT::i64:
-          BuildMI(BB, Alpha::STQ, 3).addReg(argvregs[i]).addImm((i - 6) * 8).addReg(Alpha::R30);
+          BuildMI(BB, Alpha::STQ, 3).addReg(argvregs[i]).addImm((i - 6) * 8)
+            .addReg(Alpha::R30);
           break;
         case MVT::f32:
-          BuildMI(BB, Alpha::STS, 3).addReg(argvregs[i]).addImm((i - 6) * 8).addReg(Alpha::R30);
+          BuildMI(BB, Alpha::STS, 3).addReg(argvregs[i]).addImm((i - 6) * 8)
+            .addReg(Alpha::R30);
           break;
         case MVT::f64:
-          BuildMI(BB, Alpha::STT, 3).addReg(argvregs[i]).addImm((i - 6) * 8).addReg(Alpha::R30);
+          BuildMI(BB, Alpha::STT, 3).addReg(argvregs[i]).addImm((i - 6) * 8)
+            .addReg(Alpha::R30);
           break;
         }
       }
@@ -1651,7 +1690,8 @@
         } else {
           //use PC relative branch call
           AlphaLowering.restoreGP(BB);
-          BuildMI(BB, Alpha::BSR, 1, Alpha::R26).addGlobalAddress(GASD->getGlobal(),true);
+          BuildMI(BB, Alpha::BSR, 1, Alpha::R26)
+            .addGlobalAddress(GASD->getGlobal(),true);
         }
       }
       else if (ExternalSymbolSDNode *ESSDN =
@@ -1919,33 +1959,33 @@
     //Check operand(0) == Not
     if (N.getOperand(0).getOpcode() == ISD::XOR &&
         N.getOperand(0).getOperand(1).getOpcode() == ISD::Constant &&
-        cast<ConstantSDNode>(N.getOperand(0).getOperand(1))->getSignExtended() == -1)
-      {
-        switch(opcode) {
+        cast<ConstantSDNode>(N.getOperand(0).getOperand(1))->getSignExtended() 
+        == -1) {
+      switch(opcode) {
         case ISD::AND: Opc = Alpha::BIC; break;
         case ISD::OR:  Opc = Alpha::ORNOT; break;
         case ISD::XOR: Opc = Alpha::EQV; break;
-        }
-        Tmp1 = SelectExpr(N.getOperand(1));
-        Tmp2 = SelectExpr(N.getOperand(0).getOperand(0));
-        BuildMI(BB, Opc, 2, Result).addReg(Tmp1).addReg(Tmp2);
-        return Result;
       }
+      Tmp1 = SelectExpr(N.getOperand(1));
+      Tmp2 = SelectExpr(N.getOperand(0).getOperand(0));
+      BuildMI(BB, Opc, 2, Result).addReg(Tmp1).addReg(Tmp2);
+      return Result;
+    }
     //Check operand(1) == Not
     if (N.getOperand(1).getOpcode() == ISD::XOR &&
         N.getOperand(1).getOperand(1).getOpcode() == ISD::Constant &&
-        cast<ConstantSDNode>(N.getOperand(1).getOperand(1))->getSignExtended() == -1)
-      {
-        switch(opcode) {
+        cast<ConstantSDNode>(N.getOperand(1).getOperand(1))->getSignExtended()
+        == -1) {
+      switch(opcode) {
         case ISD::AND: Opc = Alpha::BIC; break;
         case ISD::OR:  Opc = Alpha::ORNOT; break;
         case ISD::XOR: Opc = Alpha::EQV; break;
-        }
-        Tmp1 = SelectExpr(N.getOperand(0));
-        Tmp2 = SelectExpr(N.getOperand(1).getOperand(0));
-        BuildMI(BB, Opc, 2, Result).addReg(Tmp1).addReg(Tmp2);
-        return Result;
       }
+      Tmp1 = SelectExpr(N.getOperand(0));
+      Tmp2 = SelectExpr(N.getOperand(1).getOperand(0));
+      BuildMI(BB, Opc, 2, Result).addReg(Tmp1).addReg(Tmp2);
+      return Result;
+    }
     //Fall through
   case ISD::SHL:
   case ISD::SRL:
@@ -2146,7 +2186,8 @@
 
   case ISD::SELECT:
     {
-      //FIXME: look at parent to decide if intCC can be folded, or if setCC(FP) and can save stack use
+      //FIXME: look at parent to decide if intCC can be folded, or if setCC(FP)
+      //and can save stack use
       //Tmp1 = SelectExpr(N.getOperand(0)); //Cond
       //Tmp2 = SelectExpr(N.getOperand(1)); //Use if TRUE
       //Tmp3 = SelectExpr(N.getOperand(2)); //Use if FALSE
@@ -2185,16 +2226,17 @@
           //Choose the CMOV
           switch (cCode) {
           default: CC.Val->dump(); assert(0 && "Unknown integer comparison!");
-          case ISD::SETEQ:  Opc = useImm?Alpha::CMOVEQi:Alpha::CMOVEQ;      break;
-          case ISD::SETLT:  Opc = useImm?Alpha::CMOVLTi:Alpha::CMOVLT;      break;
-          case ISD::SETLE:  Opc = useImm?Alpha::CMOVLEi:Alpha::CMOVLE;      break;
-          case ISD::SETGT:  Opc = useImm?Alpha::CMOVGTi:Alpha::CMOVGT;      break;
-          case ISD::SETGE:  Opc = useImm?Alpha::CMOVGEi:Alpha::CMOVGE;      break;
-          case ISD::SETULT: assert(0 && "x (unsigned) < 0 is never true");  break;
-          case ISD::SETUGT: Opc = useImm?Alpha::CMOVNEi:Alpha::CMOVNE;      break;
-          case ISD::SETULE: Opc = useImm?Alpha::CMOVEQi:Alpha::CMOVEQ;      break; //Technically you could have this CC
-          case ISD::SETUGE: assert(0 && "x (unsgined >= 0 is always true"); break;
-          case ISD::SETNE:  Opc = useImm?Alpha::CMOVNEi:Alpha::CMOVNE;      break;
+          case ISD::SETEQ: Opc = useImm?Alpha::CMOVEQi:Alpha::CMOVEQ;     break;
+          case ISD::SETLT: Opc = useImm?Alpha::CMOVLTi:Alpha::CMOVLT;     break;
+          case ISD::SETLE: Opc = useImm?Alpha::CMOVLEi:Alpha::CMOVLE;     break;
+          case ISD::SETGT: Opc = useImm?Alpha::CMOVGTi:Alpha::CMOVGT;     break;
+          case ISD::SETGE: Opc = useImm?Alpha::CMOVGEi:Alpha::CMOVGE;     break;
+          case ISD::SETULT: assert(0 && "unsigned < 0 is never true"); break;
+          case ISD::SETUGT: Opc = useImm?Alpha::CMOVNEi:Alpha::CMOVNE;    break;
+          //Technically you could have this CC
+          case ISD::SETULE: Opc = useImm?Alpha::CMOVEQi:Alpha::CMOVEQ;    break;
+          case ISD::SETUGE: assert(0 && "unsgined >= 0 is always true"); break;
+          case ISD::SETNE:  Opc = useImm?Alpha::CMOVNEi:Alpha::CMOVNE;    break;
           }
           Tmp1 = SelectExpr(SetCC->getOperand(0)); //Cond
 
@@ -2215,7 +2257,8 @@
       Tmp1 = SelectExpr(N.getOperand(0)); //Cond
       Tmp2 = SelectExpr(N.getOperand(1)); //Use if TRUE
       Tmp3 = SelectExpr(N.getOperand(2)); //Use if FALSE
-      BuildMI(BB, Alpha::CMOVEQ, 2, Result).addReg(Tmp2).addReg(Tmp3).addReg(Tmp1);
+      BuildMI(BB, Alpha::CMOVEQ, 2, Result).addReg(Tmp2).addReg(Tmp3)
+        .addReg(Tmp1);
 
       return Result;
     }
@@ -2229,18 +2272,22 @@
       else if (val <= (int64_t)IMM_HIGH +(int64_t)IMM_HIGH* (int64_t)IMM_MULT &&
                val >= (int64_t)IMM_LOW + (int64_t)IMM_LOW * (int64_t)IMM_MULT) {
         Tmp1 = MakeReg(MVT::i64);
-        BuildMI(BB, Alpha::LDAH, 2, Tmp1).addImm(getUpper16(val)).addReg(Alpha::R31);
+        BuildMI(BB, Alpha::LDAH, 2, Tmp1).addImm(getUpper16(val))
+          .addReg(Alpha::R31);
         BuildMI(BB, Alpha::LDA, 2, Result).addImm(getLower16(val)).addReg(Tmp1);
       }
       else {
         MachineConstantPool *CP = BB->getParent()->getConstantPool();
-        ConstantUInt *C = ConstantUInt::get(Type::getPrimitiveType(Type::ULongTyID) , val);
+        ConstantUInt *C = 
+          ConstantUInt::get(Type::getPrimitiveType(Type::ULongTyID) , val);
         unsigned CPI = CP->getConstantPoolIndex(C);
         AlphaLowering.restoreGP(BB);
         has_sym = true;
         Tmp1 = MakeReg(MVT::i64);
-        BuildMI(BB, Alpha::LDAHr, 2, Tmp1).addConstantPoolIndex(CPI).addReg(Alpha::R29);
-        BuildMI(BB, Alpha::LDQr, 2, Result).addConstantPoolIndex(CPI).addReg(Tmp1);
+        BuildMI(BB, Alpha::LDAHr, 2, Tmp1).addConstantPoolIndex(CPI)
+          .addReg(Alpha::R29);
+        BuildMI(BB, Alpha::LDQr, 2, Result).addConstantPoolIndex(CPI)
+          .addReg(Tmp1);
       }
       return Result;
     }
@@ -2339,7 +2386,8 @@
       Select(N.getOperand(0));
       break;
     }
-    BuildMI(BB, Alpha::RET, 1, Alpha::R31).addReg(AlphaLowering.getRA()); // Just emit a 'ret' instruction
+    // Just emit a 'ret' instruction
+    BuildMI(BB, Alpha::RET, 1, Alpha::R31).addReg(AlphaLowering.getRA());
     return;
 
   case ISD::TRUNCSTORE:
@@ -2371,7 +2419,8 @@
 
       if (EnableAlphaLSMark)
       {
-        int i = getValueOffset(dyn_cast<SrcValueSDNode>(N.getOperand(3))->getValue());
+        int i = 
+          getValueOffset(dyn_cast<SrcValueSDNode>(N.getOperand(3))->getValue());
         int j = getFunctionOffset(BB->getParent()->getFunction());
         BuildMI(BB, Alpha::MEMLABEL, 3).addImm(j).addImm(i).addImm(getUID());
       }
@@ -2381,7 +2430,8 @@
         AlphaLowering.restoreGP(BB);
         Opc = GetSymVersion(Opc);
         has_sym = true;
-        BuildMI(BB, Opc, 2).addReg(Tmp1).addGlobalAddress(cast<GlobalAddressSDNode>(Address)->getGlobal());
+        BuildMI(BB, Opc, 2).addReg(Tmp1)
+          .addGlobalAddress(cast<GlobalAddressSDNode>(Address)->getGlobal());
       }
       else if(Address.getOpcode() == ISD::FrameIndex)
       {
@@ -2422,7 +2472,8 @@
 
   case ISD::PCMARKER:
     Select(N.getOperand(0)); //Chain
-    BuildMI(BB, Alpha::PCLABEL, 2).addImm( cast<ConstantSDNode>(N.getOperand(1))->getValue());
+    BuildMI(BB, Alpha::PCLABEL, 2)
+      .addImm( cast<ConstantSDNode>(N.getOperand(1))->getValue());
     return;
   }
   assert(0 && "Should not be reached!");





From alenhar2 at cs.uiuc.edu  Mon Jun 27 16:03:07 2005
From: alenhar2 at cs.uiuc.edu (Andrew Lenharth)
Date: Mon, 27 Jun 2005 16:03:07 -0500
Subject: [llvm-commits] CVS: llvm/lib/Target/Alpha/AlphaISelPattern.cpp
	AlphaInstrInfo.td 
Message-ID: <200506272103.QAA31585@zion.cs.uiuc.edu>



Changes in directory llvm/lib/Target/Alpha:

AlphaISelPattern.cpp updated: 1.133 -> 1.134
AlphaInstrInfo.td updated: 1.46 -> 1.47
---
Log message:

generate address of constant pool entries

---
Diffs of the changes:  (+10 -5)

 AlphaISelPattern.cpp |   14 +++++++++-----
 AlphaInstrInfo.td    |    1 +
 2 files changed, 10 insertions(+), 5 deletions(-)


Index: llvm/lib/Target/Alpha/AlphaISelPattern.cpp
diff -u llvm/lib/Target/Alpha/AlphaISelPattern.cpp:1.133 llvm/lib/Target/Alpha/AlphaISelPattern.cpp:1.134
--- llvm/lib/Target/Alpha/AlphaISelPattern.cpp:1.133	Mon Jun 27 12:39:17 2005
+++ llvm/lib/Target/Alpha/AlphaISelPattern.cpp	Mon Jun 27 16:02:56 2005
@@ -1520,11 +1520,15 @@
     BuildMI(BB, Alpha::BIS, 2, Result).addReg(Alpha::R30).addReg(Alpha::R30);
     return Result;
 
-//   case ISD::ConstantPool:
-//     Tmp1 = cast<ConstantPoolSDNode>(N)->getIndex();
-//     AlphaLowering.restoreGP(BB);
-//     BuildMI(BB, Alpha::LDQ_SYM, 1, Result).addConstantPoolIndex(Tmp1);
-//     return Result;
+  case ISD::ConstantPool:
+    Tmp1 = cast<ConstantPoolSDNode>(N)->getIndex();
+    AlphaLowering.restoreGP(BB);
+    Tmp2 = MakeReg(MVT::i64);
+    BuildMI(BB, Alpha::LDAHr, 2, Tmp2).addConstantPoolIndex(Tmp1)
+      .addReg(Alpha::R29);
+    BuildMI(BB, Alpha::LDAr, 2, Result).addConstantPoolIndex(Tmp1)
+      .addReg(Tmp2);
+    return Result;
 
   case ISD::FrameIndex:
     BuildMI(BB, Alpha::LDA, 2, Result)


Index: llvm/lib/Target/Alpha/AlphaInstrInfo.td
diff -u llvm/lib/Target/Alpha/AlphaInstrInfo.td:1.46 llvm/lib/Target/Alpha/AlphaInstrInfo.td:1.47
--- llvm/lib/Target/Alpha/AlphaInstrInfo.td:1.46	Mon Jun 27 12:15:36 2005
+++ llvm/lib/Target/Alpha/AlphaInstrInfo.td	Mon Jun 27 16:02:56 2005
@@ -369,6 +369,7 @@
 def LDTr : MForm<0x23, (ops FPRC:$RA, s16imm:$DISP, GPRC:$RB), "ldt $RA,$DISP($RB) !gprellow">; //Load T_floating
 
 //Load address, rellocated form
+def LDAr : MForm<0x08, (ops GPRC:$RA, s16imm:$DISP, GPRC:$RB), "lda $RA,$DISP($RB) !gprellow">;  //Load address
 def LDAHr : MForm<0x08, (ops GPRC:$RA, s16imm:$DISP, GPRC:$RB), "ldah $RA,$DISP($RB) !gprelhigh">;  //Load address high
 
 





From alenhar2 at cs.uiuc.edu  Mon Jun 27 16:11:51 2005
From: alenhar2 at cs.uiuc.edu (Andrew Lenharth)
Date: Mon, 27 Jun 2005 16:11:51 -0500
Subject: [llvm-commits] CVS: llvm/lib/Target/Alpha/AlphaISelPattern.cpp
	AlphaInstrInfo.td 
Message-ID: <200506272111.QAA31667@zion.cs.uiuc.edu>



Changes in directory llvm/lib/Target/Alpha:

AlphaISelPattern.cpp updated: 1.134 -> 1.135
AlphaInstrInfo.td updated: 1.47 -> 1.48
---
Log message:

get rid of another pseudo op

---
Diffs of the changes:  (+4 -3)

 AlphaISelPattern.cpp |    5 +++--
 AlphaInstrInfo.td    |    2 +-
 2 files changed, 4 insertions(+), 3 deletions(-)


Index: llvm/lib/Target/Alpha/AlphaISelPattern.cpp
diff -u llvm/lib/Target/Alpha/AlphaISelPattern.cpp:1.134 llvm/lib/Target/Alpha/AlphaISelPattern.cpp:1.135
--- llvm/lib/Target/Alpha/AlphaISelPattern.cpp:1.134	Mon Jun 27 16:02:56 2005
+++ llvm/lib/Target/Alpha/AlphaISelPattern.cpp	Mon Jun 27 16:11:40 2005
@@ -1607,8 +1607,9 @@
   case ISD::GlobalAddress:
     AlphaLowering.restoreGP(BB);
     has_sym = true;
-    BuildMI(BB, Alpha::LOAD_ADDR, 1, Result)
-      .addGlobalAddress(cast<GlobalAddressSDNode>(N)->getGlobal());
+    BuildMI(BB, Alpha::LDQrl, 2, Result)
+      .addGlobalAddress(cast<GlobalAddressSDNode>(N)->getGlobal())
+      .addReg(Alpha::R29);
     return Result;
 
   case ISD::TAILCALL:


Index: llvm/lib/Target/Alpha/AlphaInstrInfo.td
diff -u llvm/lib/Target/Alpha/AlphaInstrInfo.td:1.47 llvm/lib/Target/Alpha/AlphaInstrInfo.td:1.48
--- llvm/lib/Target/Alpha/AlphaInstrInfo.td:1.47	Mon Jun 27 16:02:56 2005
+++ llvm/lib/Target/Alpha/AlphaInstrInfo.td	Mon Jun 27 16:11:40 2005
@@ -55,7 +55,6 @@
 
 //These are evil as they get expanded into multiple instructions to take care of reallocation
 let Uses = [R29], Defs = [R28] in {
-  def LOAD_ADDR : PseudoInstAlpha<(ops GPRC:$RA, s64imm:$DISP), "lda $RA,$DISP">;  //Load address
   def LDQ_SYM : PseudoInstAlpha<(ops GPRC:$RA, s64imm:$DISP), "ldq $RA,$DISP">; //Load quadword
   def LDS_SYM : PseudoInstAlpha<(ops GPRC:$RA, s64imm:$DISP), "lds $RA,$DISP">; //Load float
   def LDT_SYM : PseudoInstAlpha<(ops GPRC:$RA, s64imm:$DISP), "ldt $RA,$DISP">; //Load double
@@ -363,6 +362,7 @@
 def LDQr : MForm<0x29, (ops GPRC:$RA, s16imm:$DISP, GPRC:$RB), "ldq $RA,$DISP($RB) !gprellow">; //Load quadword
 def LDBUr : MForm<0x0A, (ops GPRC:$RA, s16imm:$DISP, GPRC:$RB), "ldbu $RA,$DISP($RB) !gprellow">; //Load zero-extended byte
 def LDWUr : MForm<0x0C, (ops GPRC:$RA, s16imm:$DISP, GPRC:$RB), "ldwu $RA,$DISP($RB) !gprellow">; //Load zero-extended word
+def LDQrl : MForm<0x29, (ops GPRC:$RA, s16imm:$DISP, GPRC:$RB), "ldq $RA,$DISP($RB) !literal">; //Load quadword
 
 //Loads, float, Rellocated form
 def LDSr : MForm<0x22, (ops FPRC:$RA, s16imm:$DISP, GPRC:$RB), "lds $RA,$DISP($RB) !gprellow">; //Load S_floating





From natebegeman at mac.com  Mon Jun 27 16:20:42 2005
From: natebegeman at mac.com (Nate Begeman)
Date: Mon, 27 Jun 2005 16:20:42 -0500
Subject: [llvm-commits] CVS: llvm/lib/Target/X86/X86InstrInfo.td
	X86RegisterInfo.td 
Message-ID: <200506272120.QAA31705@zion.cs.uiuc.edu>



Changes in directory llvm/lib/Target/X86:

X86InstrInfo.td updated: 1.127 -> 1.128
X86RegisterInfo.td updated: 1.17 -> 1.18
---
Log message:

Initial set of .td file changes necessary to get scalar fp in xmm registers
working.  The instruction selector changes will hopefully be coming later
this week once they are debugged.  This is necessary to support the darwin
x86 FP model, and is recommended by intel as the replacement for x87.  As
a bonus, the register allocator knows how to deal with these registers
across basic blocks, unliky the FP stackifier.  This leads to significantly
better codegen in several cases.


---
Diffs of the changes:  (+126 -2)

 X86InstrInfo.td    |  116 ++++++++++++++++++++++++++++++++++++++++++++++++++++-
 X86RegisterInfo.td |   12 +++++
 2 files changed, 126 insertions(+), 2 deletions(-)


Index: llvm/lib/Target/X86/X86InstrInfo.td
diff -u llvm/lib/Target/X86/X86InstrInfo.td:1.127 llvm/lib/Target/X86/X86InstrInfo.td:1.128
--- llvm/lib/Target/X86/X86InstrInfo.td:1.127	Sat May 14 22:10:37 2005
+++ llvm/lib/Target/X86/X86InstrInfo.td	Mon Jun 27 16:20:31 2005
@@ -119,6 +119,8 @@
 class DD     { bits<4> Prefix = 8; }
 class DE     { bits<4> Prefix = 9; }
 class DF     { bits<4> Prefix = 10; }
+class XD     { bits<4> Prefix = 11; }
+class XS     { bits<4> Prefix = 12; }
 
 
 //===----------------------------------------------------------------------===//
@@ -338,7 +340,7 @@
                 "mov{w} {$src, $dst|$dst, $src}">, OpSize;
 def MOV32mr : I<0x89, MRMDestMem, (ops i32mem:$dst, R32:$src),
                 "mov{l} {$src, $dst|$dst, $src}">;
-
+                
 //===----------------------------------------------------------------------===//
 //  Fixed-Register Multiplication and Division Instructions...
 //
@@ -1397,9 +1399,119 @@
 def MOVZX32rm16: I<0xB7, MRMSrcMem, (ops R32:$dst, i16mem:$src),
                    "movz{wl|x} {$src, $dst|$dst, $src}">, TB;
 
+//===----------------------------------------------------------------------===//
+// XMM Floating point support (requires SSE2)
+//===----------------------------------------------------------------------===//
+
+def MOVSSrm : I<0x10, MRMSrcMem, (ops RXMM:$dst, f32mem:$src),
+                "movss {$src, $dst|$dst, $src}">, XS;
+def MOVSSmr : I<0x11, MRMDestMem, (ops f32mem:$dst, RXMM:$src),
+                "movss {$src, $dst|$dst, $src}">, XS;
+def MOVSDrm : I<0x10, MRMSrcMem, (ops RXMM:$dst, f64mem:$src),
+                "movsd {$src, $dst|$dst, $src}">, XD;
+def MOVSDmr : I<0x11, MRMDestMem, (ops f64mem:$dst, RXMM:$src),
+                "movsd {$src, $dst|$dst, $src}">, XD;
+def MOVAPSrr: I<0x28, MRMSrcReg, (ops RXMM:$dst, RXMM:$src),
+                "movaps {$src, $dst|$dst, $src}">, TB;
+def MOVAPSrm: I<0x28, MRMSrcMem, (ops RXMM:$dst, f32mem:$src),
+                "movaps {$src, $dst|$dst, $src}">, TB;
+def MOVAPSmr: I<0x29, MRMDestMem, (ops f32mem:$dst, RXMM:$src),
+                "movaps {$src, $dst|$dst, $src}">, TB;
+def MOVAPDrr: I<0x28, MRMSrcReg, (ops RXMM:$dst, RXMM:$src),
+                "movapd {$src, $dst|$dst, $src}">, TB, OpSize;
+def MOVAPDrm: I<0x28, MRMSrcMem, (ops RXMM:$dst, f64mem:$src),
+                "movapd {$src, $dst|$dst, $src}">, TB, OpSize;
+def MOVAPDmr: I<0x29, MRMDestMem, (ops f64mem:$dst, RXMM:$src),
+                "movapd {$src, $dst|$dst, $src}">, TB, OpSize;
+
+def CVTSD2SIrr: I<0x2D, MRMSrcReg, (ops R32:$dst, RXMM:$src),
+                "cvtsd2si {$src, $dst|$dst, $src}">, XD;
+def CVTSD2SIrm: I<0x2D, MRMSrcMem, (ops R32:$dst, f64mem:$src),
+                "cvtsd2si {$src, $dst|$dst, $src}">, XD;
+def CVTSS2SIrr: I<0x2D, MRMSrcReg, (ops R32:$dst, RXMM:$src),
+                "cvtss2si {$src, $dst|$dst, $src}">, XS;
+def CVTSS2SIrm: I<0x2D, MRMSrcMem, (ops R32:$dst, f32mem:$src),
+                "cvtss2si {$src, $dst|$dst, $src}">, XS;
+def CVTSS2SDrr: I<0x5A, MRMSrcReg, (ops R32:$dst, RXMM:$src),
+                "cvtss2sd {$src, $dst|$dst, $src}">, XD;
+def CVTSS2SDrm: I<0x5A, MRMSrcMem, (ops R32:$dst, f32mem:$src),
+                "cvtss2sd {$src, $dst|$dst, $src}">, XD;
+
+def UCOMISDrr: I<0x2E, MRMSrcReg, (ops RXMM:$dst, RXMM:$src),
+                "ucomisd {$src, $dst|$dst, $src}">, TB, OpSize;
+def UCOMISDrm: I<0x2E, MRMSrcMem, (ops RXMM:$dst, f64mem:$src),
+                "ucomisd {$src, $dst|$dst, $src}">, TB, OpSize;
+def UCOMISSrr: I<0x2E, MRMSrcReg, (ops RXMM:$dst, RXMM:$src),
+                "ucomiss {$src, $dst|$dst, $src}">, TB;
+def UCOMISSrm: I<0x2E, MRMSrcMem, (ops RXMM:$dst, f32mem:$src),
+                "ucomiss {$src, $dst|$dst, $src}">, TB;
+
+let isTwoAddress = 1 in {
+let isCommutable = 1 in {
+def ADDSSrr : I<0x58, MRMSrcReg, (ops RXMM:$dst, RXMM:$src1, RXMM:$src),
+                "addss {$src, $dst|$dst, $src}">, XS;
+def ADDSDrr : I<0x58, MRMSrcReg, (ops RXMM:$dst, RXMM:$src1, RXMM:$src),
+                "addsd {$src, $dst|$dst, $src}">, XD;
+def ANDPSrr : I<0x54, MRMSrcReg, (ops RXMM:$dst, RXMM:$src1, RXMM:$src),
+                "andps {$src, $dst|$dst, $src}">, TB;
+def ANDPDrr : I<0x54, MRMSrcReg, (ops RXMM:$dst, RXMM:$src1, RXMM:$src),
+                "andpd {$src, $dst|$dst, $src}">, TB, OpSize;
+def MULSSrr : I<0x59, MRMSrcReg, (ops RXMM:$dst, RXMM:$src1, RXMM:$src),
+                "mulss {$src, $dst|$dst, $src}">, XS;
+def MULSDrr : I<0x59, MRMSrcReg, (ops RXMM:$dst, RXMM:$src1, RXMM:$src),
+                "mulsd {$src, $dst|$dst, $src}">, XD;
+def ORPSrr : I<0x56, MRMSrcReg, (ops RXMM:$dst, RXMM:$src1, RXMM:$src),
+                "orps {$src, $dst|$dst, $src}">, TB;
+def ORPDrr : I<0x56, MRMSrcReg, (ops RXMM:$dst, RXMM:$src1, RXMM:$src),
+                "orpd {$src, $dst|$dst, $src}">, TB, OpSize;
+}
+def ANDNPSrr : I<0x55, MRMSrcReg, (ops RXMM:$dst, RXMM:$src1, RXMM:$src),
+                "andnps {$src, $dst|$dst, $src}">, TB;
+def ANDNPDrr : I<0x55, MRMSrcReg, (ops RXMM:$dst, RXMM:$src1, RXMM:$src),
+                "andnpd {$src, $dst|$dst, $src}">, TB, OpSize;
+def ADDSSrm : I<0x58, MRMSrcMem, (ops RXMM:$dst, RXMM:$src1, f32mem:$src),
+                "addss {$src, $dst|$dst, $src}">, XS;
+def ADDSDrm : I<0x58, MRMSrcMem, (ops RXMM:$dst, RXMM:$src1, f64mem:$src),
+                "addsd {$src, $dst|$dst, $src}">, XD;
+def MULSSrm : I<0x59, MRMSrcMem, (ops RXMM:$dst, RXMM:$src1, f32mem:$src),
+                "mulss {$src, $dst|$dst, $src}">, XS;
+def MULSDrm : I<0x59, MRMSrcMem, (ops RXMM:$dst, RXMM:$src1, f64mem:$src),
+                "mulsd {$src, $dst|$dst, $src}">, XD;
+
+def DIVSSrm : I<0x5E, MRMSrcMem, (ops RXMM:$dst, RXMM:$src1, f32mem:$src),
+                "divss {$src, $dst|$dst, $src}">, XS;
+def DIVSSrr : I<0x5E, MRMSrcReg, (ops RXMM:$dst, RXMM:$src1, RXMM:$src),
+                "divss {$src, $dst|$dst, $src}">, XS;
+def DIVSDrm : I<0x5E, MRMSrcMem, (ops RXMM:$dst, RXMM:$src1, f64mem:$src),
+                "divsd {$src, $dst|$dst, $src}">, XD;
+def DIVSDrr : I<0x5E, MRMSrcReg, (ops RXMM:$dst, RXMM:$src1, RXMM:$src),
+                "divsd {$src, $dst|$dst, $src}">, XD;
+
+def SUBSSrm : I<0x5C, MRMSrcMem, (ops RXMM:$dst, RXMM:$src1, f32mem:$src),
+                "subss {$src, $dst|$dst, $src}">, XS;
+def SUBSSrr : I<0x5C, MRMSrcReg, (ops RXMM:$dst, RXMM:$src1, RXMM:$src),
+                "subss {$src, $dst|$dst, $src}">, XS;
+def SUBSDrm : I<0x5C, MRMSrcMem, (ops RXMM:$dst, RXMM:$src1, f64mem:$src),
+                "subsd {$src, $dst|$dst, $src}">, XD;
+def SUBSDrr : I<0x5C, MRMSrcReg, (ops RXMM:$dst, RXMM:$src1, RXMM:$src),
+                "subsd {$src, $dst|$dst, $src}">, XD;
+
+def CMPSSrr : I<0xC2, MRMSrcReg, 
+                (ops RXMM:$dst, RXMM:$src1, RXMM:$src, i8imm:$pred),
+                "cmpss {$src, $dst, $pred|$dst, $src, $pred}">, XS;
+def CMPSSrm : I<0xC2, MRMSrcMem, 
+                (ops RXMM:$dst, RXMM:$src1, f32mem:$src, i8imm:$pred),
+                "cmpss {$src, $dst, $pred|$dst, $src, $pred}">, XS;
+def CMPSDrr : I<0xC2, MRMSrcReg, 
+                (ops RXMM:$dst, RXMM:$src1, RXMM:$src, i8imm:$pred),
+                "cmpss {$src, $dst, $pred|$dst, $src, $pred}">, XD;
+def CMPSDrm : I<0xC2, MRMSrcMem, 
+                (ops RXMM:$dst, RXMM:$src1, f64mem:$src, i8imm:$pred),
+                "cmpss {$src, $dst, $pred|$dst, $src, $pred}">, XD;
+}
 
 //===----------------------------------------------------------------------===//
-// Floating point support
+// Stack-based Floating point support
 //===----------------------------------------------------------------------===//
 
 // FIXME: These need to indicate mod/ref sets for FP regs... & FP 'TOP'


Index: llvm/lib/Target/X86/X86RegisterInfo.td
diff -u llvm/lib/Target/X86/X86RegisterInfo.td:1.17 llvm/lib/Target/X86/X86RegisterInfo.td:1.18
--- llvm/lib/Target/X86/X86RegisterInfo.td:1.17	Wed Jan  5 10:09:16 2005
+++ llvm/lib/Target/X86/X86RegisterInfo.td	Mon Jun 27 16:20:31 2005
@@ -47,6 +47,12 @@
   def FP4 : Register<"FP4">; def FP5 : Register<"FP5">;
   def FP6 : Register<"FP6">; 
 
+  // XMM Registers, used by the various SSE instruction set extensions
+  def XMM0: Register<"XMM0">; def XMM1: Register<"XMM1">;
+  def XMM2: Register<"XMM2">; def XMM3: Register<"XMM3">;
+  def XMM4: Register<"XMM4">; def XMM5: Register<"XMM5">;
+  def XMM6: Register<"XMM6">; def XMM7: Register<"XMM7">;
+
   // Floating point stack registers
   def ST0 : Register<"ST(0)">; def ST1 : Register<"ST(1)">;
   def ST2 : Register<"ST(2)">; def ST3 : Register<"ST(3)">;
@@ -90,6 +96,12 @@
   }];
 }
 
+// FIXME: These registers can contain both integer and fp values.  We should
+// figure out the right way to deal with that.  For now, since they'll be used
+// for scalar FP, they are being declared f64
+def RXMM : RegisterClass<f64, 128, [XMM0, XMM1, XMM2, XMM3, 
+                                    XMM4, XMM5, XMM6, XMM7]>;
+
 // FIXME: This sets up the floating point register files as though they are f64
 // values, though they really are f80 values.  This will cause us to spill
 // values as 64-bit quantities instead of 80-bit quantities, which is much much





From alenhar2 at cs.uiuc.edu  Mon Jun 27 18:24:22 2005
From: alenhar2 at cs.uiuc.edu (Andrew Lenharth)
Date: Mon, 27 Jun 2005 18:24:22 -0500
Subject: [llvm-commits] CVS: llvm/lib/Target/Alpha/AlphaISelPattern.cpp 
Message-ID: <200506272324.SAA32411@zion.cs.uiuc.edu>



Changes in directory llvm/lib/Target/Alpha:

AlphaISelPattern.cpp updated: 1.135 -> 1.136
---
Log message:

So, it turns out I forgot that one valid way of restoring GP after a call
is to use RA, which assumes the called function uses RA for the register
holding the return address when it issues a ret.



---
Diffs of the changes:  (+3 -3)

 AlphaISelPattern.cpp |    6 +++---
 1 files changed, 3 insertions(+), 3 deletions(-)


Index: llvm/lib/Target/Alpha/AlphaISelPattern.cpp
diff -u llvm/lib/Target/Alpha/AlphaISelPattern.cpp:1.135 llvm/lib/Target/Alpha/AlphaISelPattern.cpp:1.136
--- llvm/lib/Target/Alpha/AlphaISelPattern.cpp:1.135	Mon Jun 27 16:11:40 2005
+++ llvm/lib/Target/Alpha/AlphaISelPattern.cpp	Mon Jun 27 18:24:11 2005
@@ -92,8 +92,7 @@
       setOperationAction(ISD::BRCONDTWOWAY, MVT::Other, Expand);
 
       setOperationAction(ISD::EXTLOAD, MVT::i1,  Promote);
-      setOperationAction(ISD::EXTLOAD, MVT::f32, Promote);
-
+ 
       setOperationAction(ISD::ZEXTLOAD, MVT::i1   , Expand);
       setOperationAction(ISD::ZEXTLOAD, MVT::i32  , Expand);
 
@@ -2392,7 +2391,8 @@
       break;
     }
     // Just emit a 'ret' instruction
-    BuildMI(BB, Alpha::RET, 1, Alpha::R31).addReg(AlphaLowering.getRA());
+    AlphaLowering.restoreRA(BB);
+    BuildMI(BB, Alpha::RET, 1, Alpha::R31).addReg(Alpha::R26);
     return;
 
   case ISD::TRUNCSTORE:





From alenhar2 at cs.uiuc.edu  Mon Jun 27 18:28:43 2005
From: alenhar2 at cs.uiuc.edu (Andrew Lenharth)
Date: Mon, 27 Jun 2005 18:28:43 -0500
Subject: [llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp 
Message-ID: <200506272328.SAA32460@zion.cs.uiuc.edu>



Changes in directory llvm/lib/CodeGen/SelectionDAG:

LegalizeDAG.cpp updated: 1.130 -> 1.131
---
Log message:

Adapt the code for handling uint -> fp conversion for the 32 bit case to
handling it in the 64 bit case.  The two code paths should probably be merged.




---
Diffs of the changes:  (+35 -0)

 LegalizeDAG.cpp |   35 +++++++++++++++++++++++++++++++++++
 1 files changed, 35 insertions(+)


Index: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.130 llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.131
--- llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.130	Sat May 14 03:34:53 2005
+++ llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp	Mon Jun 27 18:28:32 2005
@@ -1314,6 +1314,41 @@
   case ISD::UINT_TO_FP:
     switch (getTypeAction(Node->getOperand(0).getValueType())) {
     case Legal:
+      //still made need to expand if the op is illegal, but the types are legal
+      if (Node->getOpcode() == ISD::UINT_TO_FP &&
+          TLI.getOperationAction(Node->getOpcode(), 
+                                 Node->getOperand(0).getValueType()) 
+          == TargetLowering::Expand) {
+        Tmp1 = DAG.getNode(ISD::SINT_TO_FP, Node->getValueType(0), 
+                           Node->getOperand(0));
+        
+        SDOperand SignSet = DAG.getSetCC(ISD::SETLT, TLI.getSetCCResultTy(), 
+                                         Node->getOperand(0),
+                                         DAG.getConstant(0, 
+                                         Node->getOperand(0).getValueType()));
+        SDOperand Zero = getIntPtrConstant(0), Four = getIntPtrConstant(4);
+        SDOperand CstOffset = DAG.getNode(ISD::SELECT, Zero.getValueType(),
+                                          SignSet, Four, Zero);
+        uint64_t FF = 0x5f800000ULL;
+        if (TLI.isLittleEndian()) FF <<= 32;
+        static Constant *FudgeFactor = ConstantUInt::get(Type::ULongTy, FF);
+
+        MachineConstantPool *CP = DAG.getMachineFunction().getConstantPool();
+        SDOperand CPIdx = DAG.getConstantPool(CP->getConstantPoolIndex(FudgeFactor),
+                                              TLI.getPointerTy());
+        CPIdx = DAG.getNode(ISD::ADD, TLI.getPointerTy(), CPIdx, CstOffset);
+        SDOperand FudgeInReg;
+        if (Node->getValueType(0) == MVT::f32)
+          FudgeInReg = DAG.getLoad(MVT::f32, DAG.getEntryNode(), CPIdx,
+                                   DAG.getSrcValue(NULL));
+        else {
+          assert(Node->getValueType(0) == MVT::f64 && "Unexpected conversion");
+          FudgeInReg = DAG.getNode(ISD::EXTLOAD, MVT::f64, DAG.getEntryNode(),
+                                   CPIdx, DAG.getSrcValue(NULL), MVT::f32);
+        }
+        Result = DAG.getNode(ISD::ADD, Node->getValueType(0), Tmp1, FudgeInReg);
+        break;
+      }
       Tmp1 = LegalizeOp(Node->getOperand(0));
       if (Tmp1 != Node->getOperand(0))
         Result = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1);





From alenhar2 at cs.uiuc.edu  Mon Jun 27 19:00:02 2005
From: alenhar2 at cs.uiuc.edu (Andrew Lenharth)
Date: Mon, 27 Jun 2005 19:00:02 -0500
Subject: [llvm-commits] CVS: llvm/lib/Target/SparcV8/SparcV8ISelPattern.cpp 
Message-ID: <200506280000.TAA32602@zion.cs.uiuc.edu>



Changes in directory llvm/lib/Target/SparcV8:

SparcV8ISelPattern.cpp updated: 1.1 -> 1.2
---
Log message:

some call work

---
Diffs of the changes:  (+64 -1)

 SparcV8ISelPattern.cpp |   65 ++++++++++++++++++++++++++++++++++++++++++++++++-
 1 files changed, 64 insertions(+), 1 deletion(-)


Index: llvm/lib/Target/SparcV8/SparcV8ISelPattern.cpp
diff -u llvm/lib/Target/SparcV8/SparcV8ISelPattern.cpp:1.1 llvm/lib/Target/SparcV8/SparcV8ISelPattern.cpp:1.2
--- llvm/lib/Target/SparcV8/SparcV8ISelPattern.cpp:1.1	Fri Jun 17 11:52:12 2005
+++ llvm/lib/Target/SparcV8/SparcV8ISelPattern.cpp	Mon Jun 27 18:59:51 2005
@@ -119,7 +119,8 @@
 std::vector<SDOperand>
 V8TargetLowering::LowerArguments(Function &F, SelectionDAG &DAG)
 {
-  //FIXME
+  static const unsigned IncomingArgRegs[] = 
+    { V8::I0, V8::I1, V8::I2, V8::I3, V8::I4, V8::I5 };
   std::vector<SDOperand> ArgValues;
 
   MachineFunction &MF = DAG.getMachineFunction();
@@ -127,6 +128,68 @@
 
   MachineBasicBlock& BB = MF.front();
 
+  unsigned ArgNo = 0;
+  unsigned ArgOffset = 92;
+  for (Function::arg_iterator I = F.arg_begin(), E = F.arg_end();
+       I != E; ++I, ++ArgNo) {
+    MVT::ValueType VT = getValueType(I->getType());
+    SDOperand argt;
+    if (ArgNo < 6) {
+      switch(VT) {
+      default:
+        std::cerr << "Unknown Type " << VT << "\n";
+        abort();
+      case MVT::f64:
+      case MVT::i64:
+        //FIXME: figure out the build pair thing
+        assert(0 && "doubles and longs not supported yet");
+      case MVT::f32:
+        argt = DAG.getCopyFromReg(AddLiveIn(MF, IncomingArgRegs[ArgNo],
+                                            MVT::i32),
+                                  VT, DAG.getRoot());
+        //copy out of Int reg
+        argt = DAG.getNode(ISD::FP_TO_UINT, MVT::f32, argt);
+        break;
+      case MVT::i1:
+      case MVT::i8:
+      case MVT::i16:
+      case MVT::i32:
+        argt = DAG.getCopyFromReg(AddLiveIn(MF, IncomingArgRegs[ArgNo], 
+                                            getRegClassFor(MVT::i32)), 
+                                  VT, DAG.getRoot());
+        if (VT != MVT::i32)
+          argt = DAG.getNode(ISD::TRUNCATE, VT, argt);
+        break;
+      }
+      DAG.setRoot(argt.getValue(1));
+    } else {
+      //stack passed
+      switch(VT) {
+      default:
+        std::cerr << "Unknown Type " << VT << "\n";
+        abort();
+      case MVT::f64:
+      case MVT::i64:
+        //FIXME: figure out the build pair thing
+        assert(0 && "doubles and longs not supported yet");
+      case MVT::f32:
+      case MVT::i1:
+      case MVT::i8:
+      case MVT::i16:
+      case MVT::i32:
+      // Create the frame index object for this incoming parameter...
+      int FI = MFI->CreateFixedObject(4, ArgOffset);
+      argt = DAG.getLoad(VT,
+                         DAG.getEntryNode(),
+                         DAG.getFramIndex(FI, MVT::i32),
+                         DAG.getSrcValue(NULL));
+      ArgOffset += 4;
+      break;
+      }
+      ArgValues.push_back(argt);
+    }
+  }
+
   //return the arguments
   return ArgValues;
 }





From jeffc at jolt-lang.org  Mon Jun 27 21:43:16 2005
From: jeffc at jolt-lang.org (Jeff Cohen)
Date: Mon, 27 Jun 2005 21:43:16 -0500
Subject: [llvm-commits] CVS: llvm/win32/CodeGen/CodeGen.vcproj 
Message-ID: <200506280243.VAA08992@zion.cs.uiuc.edu>



Changes in directory llvm/win32/CodeGen:

CodeGen.vcproj updated: 1.11 -> 1.12
---
Log message:

Add ElfWriter stuff to Visual Studio

---
Diffs of the changes:  (+6 -0)

 CodeGen.vcproj |    6 ++++++
 1 files changed, 6 insertions(+)


Index: llvm/win32/CodeGen/CodeGen.vcproj
diff -u llvm/win32/CodeGen/CodeGen.vcproj:1.11 llvm/win32/CodeGen/CodeGen.vcproj:1.12
--- llvm/win32/CodeGen/CodeGen.vcproj:1.11	Sun Jan 30 11:54:11 2005
+++ llvm/win32/CodeGen/CodeGen.vcproj	Mon Jun 27 21:43:03 2005
@@ -113,6 +113,9 @@
 				RelativePath="..\..\lib\CodeGen\BranchFolding.cpp">
 			</File>
 			<File
+				RelativePath="..\..\lib\CodeGen\ELFWriter.cpp">
+			</File>
+			<File
 				RelativePath="..\..\lib\CodeGen\IntrinsicLowering.cpp">
 			</File>
 			<File
@@ -194,6 +197,9 @@
 				RelativePath="..\..\include\llvm\CodeGen\AsmPrinter.h">
 			</File>
 			<File
+				RelativePath="..\..\include\llvm\CodeGen\ELFWriter.h">
+			</File>
+			<File
 				RelativePath="..\..\include\llvm\CodeGen\InstrScheduling.h">
 			</File>
 			<File





From jeffc at jolt-lang.org  Mon Jun 27 21:43:16 2005
From: jeffc at jolt-lang.org (Jeff Cohen)
Date: Mon, 27 Jun 2005 21:43:16 -0500
Subject: [llvm-commits] CVS: llvm/win32/x86/x86.vcproj 
Message-ID: <200506280243.VAA08990@zion.cs.uiuc.edu>



Changes in directory llvm/win32/x86:

x86.vcproj updated: 1.10 -> 1.11
---
Log message:

Add ElfWriter stuff to Visual Studio

---
Diffs of the changes:  (+7 -2)

 x86.vcproj |    9 +++++++--
 1 files changed, 7 insertions(+), 2 deletions(-)


Index: llvm/win32/x86/x86.vcproj
diff -u llvm/win32/x86/x86.vcproj:1.10 llvm/win32/x86/x86.vcproj:1.11
--- llvm/win32/x86/x86.vcproj:1.10	Tue Feb 15 23:06:52 2005
+++ llvm/win32/x86/x86.vcproj	Mon Jun 27 21:43:03 2005
@@ -120,7 +120,8 @@
 ..\$(IntDir)\TableGen.exe -gen-instr-enums -I ..\..\lib\Target\X86 $(InputPath) -o X86GenInstrNames.inc
 ..\$(IntDir)\TableGen.exe -gen-instr-desc -I ..\..\lib\Target\X86 $(InputPath) -o X86GenInstrInfo.inc
 ..\$(IntDir)\TableGen.exe -gen-asm-writer -I ..\..\lib\Target\X86 $(InputPath) -o X86GenAsmWriter.inc
-..\$(IntDir)\TableGen.exe -gen-asm-writer -asmwriternum=1 -I ..\..\lib\Target\X86 $(InputPath) -o X86GenAsmWriter1.inc"
+..\$(IntDir)\TableGen.exe -gen-asm-writer -asmwriternum=1 -I ..\..\lib\Target\X86 $(InputPath) -o X86GenAsmWriter1.inc
+"
 						AdditionalDependencies="$(InputDir)X86InstrInfo.td;$(InputDir)X86RegisterInfo.td;$(InputDir)..\Target.td;$(ProjectDir)..\$(IntDir)\TableGen.exe"
 						Outputs="X86GenRegisterNames.inc;X86GenRegisterInfo.h.inc;X86GenRegisterInfo.inc;X86GenInstrNames.inc;X86GenInstrInfo.inc;X86GenAsmWriter.inc;X86GenAsmWriter1.inc"/>
 				</FileConfiguration>
@@ -135,7 +136,8 @@
 ..\$(IntDir)\TableGen.exe -gen-instr-enums -I ..\..\lib\Target\X86 $(InputPath) -o X86GenInstrNames.inc
 ..\$(IntDir)\TableGen.exe -gen-instr-desc -I ..\..\lib\Target\X86 $(InputPath) -o X86GenInstrInfo.inc
 ..\$(IntDir)\TableGen.exe -gen-asm-writer -I ..\..\lib\Target\X86 $(InputPath) -o X86GenAsmWriter.inc
-..\$(IntDir)\TableGen.exe -gen-asm-writer -asmwriternum=1 -I ..\..\lib\Target\X86 $(InputPath) -o X86GenAsmWriter1.inc"
+..\$(IntDir)\TableGen.exe -gen-asm-writer -asmwriternum=1 -I ..\..\lib\Target\X86 $(InputPath) -o X86GenAsmWriter1.inc
+"
 						AdditionalDependencies="$(InputDir)X86InstrInfo.td;$(InputDir)X86RegisterInfo.td;$(InputDir)..\Target.td;$(ProjectDir)..\$(IntDir)\TableGen.exe"
 						Outputs="X86GenRegisterNames.inc;X86GenRegisterInfo.h.inc;X86GenRegisterInfo.inc;X86GenInstrNames.inc;X86GenInstrInfo.inc;X86GenAsmWriter.inc;X86GenAsmWriter1.inc"/>
 				</FileConfiguration>
@@ -147,6 +149,9 @@
 				RelativePath="..\..\lib\Target\X86\X86CodeEmitter.cpp">
 			</File>
 			<File
+				RelativePath="..\..\lib\Target\X86\X86ELFWriter.cpp">
+			</File>
+			<File
 				RelativePath="..\..\lib\Target\X86\X86FloatingPoint.cpp">
 			</File>
 			<File





From alenhar2 at cs.uiuc.edu  Tue Jun 28 19:31:20 2005
From: alenhar2 at cs.uiuc.edu (Andrew Lenharth)
Date: Tue, 28 Jun 2005 19:31:20 -0500
Subject: [llvm-commits] CVS: llvm/lib/Target/Alpha/AlphaISelPattern.cpp
	AlphaInstrInfo.td AlphaRegisterInfo.td 
Message-ID: <200506290031.TAA01715@zion.cs.uiuc.edu>



Changes in directory llvm/lib/Target/Alpha:

AlphaISelPattern.cpp updated: 1.136 -> 1.137
AlphaInstrInfo.td updated: 1.48 -> 1.49
AlphaRegisterInfo.td updated: 1.10 -> 1.11
---
Log message:

Get rid of all symbolic loads.  I now do gernate all relocations sequences 
rather than relying on the assembler.  Only a few more pseudo instructions 
left.  Also merge load code paths.




---
Diffs of the changes:  (+76 -230)

 AlphaISelPattern.cpp |  265 ++++++++++++---------------------------------------
 AlphaInstrInfo.td    |   33 ------
 AlphaRegisterInfo.td |    8 +
 3 files changed, 76 insertions(+), 230 deletions(-)


Index: llvm/lib/Target/Alpha/AlphaISelPattern.cpp
diff -u llvm/lib/Target/Alpha/AlphaISelPattern.cpp:1.136 llvm/lib/Target/Alpha/AlphaISelPattern.cpp:1.137
--- llvm/lib/Target/Alpha/AlphaISelPattern.cpp:1.136	Mon Jun 27 18:24:11 2005
+++ llvm/lib/Target/Alpha/AlphaISelPattern.cpp	Tue Jun 28 19:31:08 2005
@@ -92,9 +92,10 @@
       setOperationAction(ISD::BRCONDTWOWAY, MVT::Other, Expand);
 
       setOperationAction(ISD::EXTLOAD, MVT::i1,  Promote);
+      setOperationAction(ISD::EXTLOAD, MVT::f32, Expand);
  
-      setOperationAction(ISD::ZEXTLOAD, MVT::i1   , Expand);
-      setOperationAction(ISD::ZEXTLOAD, MVT::i32  , Expand);
+      setOperationAction(ISD::ZEXTLOAD, MVT::i1,  Expand);
+      setOperationAction(ISD::ZEXTLOAD, MVT::i32, Expand);
 
       setOperationAction(ISD::SEXTLOAD, MVT::i1,  Expand);
       setOperationAction(ISD::SEXTLOAD, MVT::i8,  Expand);
@@ -844,26 +845,6 @@
   return l - h * IMM_MULT;
 }
 
-static unsigned GetSymVersion(unsigned opcode)
-{
-  switch (opcode) {
-  default: assert(0 && "unknown load or store"); return 0;
-  case Alpha::LDQ: return Alpha::LDQ_SYM;
-  case Alpha::LDS: return Alpha::LDS_SYM;
-  case Alpha::LDT: return Alpha::LDT_SYM;
-  case Alpha::LDL: return Alpha::LDL_SYM;
-  case Alpha::LDBU: return Alpha::LDBU_SYM;
-  case Alpha::LDWU: return Alpha::LDWU_SYM;
-  case Alpha::LDW: return Alpha::LDW_SYM;
-  case Alpha::LDB: return Alpha::LDB_SYM;
-  case Alpha::STQ: return Alpha::STQ_SYM;
-  case Alpha::STS: return Alpha::STS_SYM;
-  case Alpha::STT: return Alpha::STT_SYM;
-  case Alpha::STL: return Alpha::STL_SYM;
-  case Alpha::STW: return Alpha::STW_SYM;
-  case Alpha::STB: return Alpha::STB_SYM;
-  }
-}
 static unsigned GetRelVersion(unsigned opcode)
 {
   switch (opcode) {
@@ -1212,74 +1193,6 @@
     BuildMI(BB, Alpha::CVTST, 1, Result).addReg(Tmp1);
     return Result;
 
-  case ISD::CopyFromReg:
-    {
-      // Make sure we generate both values.
-      if (Result != notIn)
-        ExprMap[N.getValue(1)] = notIn;   // Generate the token
-      else
-        Result = ExprMap[N.getValue(0)] = MakeReg(N.getValue(0).getValueType());
-
-      SDOperand Chain   = N.getOperand(0);
-
-      Select(Chain);
-      unsigned r = dyn_cast<RegSDNode>(Node)->getReg();
-      //std::cerr << "CopyFromReg " << Result << " = " << r << "\n";
-      BuildMI(BB, Alpha::CPYS, 2, Result).addReg(r).addReg(r);
-      return Result;
-    }
-
-  case ISD::LOAD:
-    {
-      // Make sure we generate both values.
-      if (Result != notIn)
-        ExprMap[N.getValue(1)] = notIn;   // Generate the token
-      else
-        Result = ExprMap[N.getValue(0)] = MakeReg(N.getValue(0).getValueType());
-
-      DestType = N.getValue(0).getValueType();
-
-      SDOperand Chain   = N.getOperand(0);
-      SDOperand Address = N.getOperand(1);
-      Select(Chain);
-      Opc = DestType == MVT::f64 ? Alpha::LDT : Alpha::LDS;
-
-      if (EnableAlphaLSMark)
-      {
-        int i = getValueOffset(dyn_cast<SrcValueSDNode>(N.getOperand(2))
-                                  ->getValue());
-        int j = getFunctionOffset(BB->getParent()->getFunction());
-        BuildMI(BB, Alpha::MEMLABEL, 3).addImm(j).addImm(i).addImm(getUID());
-      }
-      
-      if (Address.getOpcode() == ISD::GlobalAddress) {
-        AlphaLowering.restoreGP(BB);
-        Opc = GetSymVersion(Opc);
-        has_sym = true;
-        BuildMI(BB, Opc, 1, Result)
-          .addGlobalAddress(cast<GlobalAddressSDNode>(Address)->getGlobal());
-      }
-      else if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(Address)) {
-        AlphaLowering.restoreGP(BB);
-        Opc = GetRelVersion(Opc);
-        has_sym = true;
-        Tmp1 = MakeReg(MVT::i64);
-        BuildMI(BB, Alpha::LDAHr, 2, Tmp1).addConstantPoolIndex(CP->getIndex())
-          .addReg(Alpha::R29);
-        BuildMI(BB, Opc, 2, Result).addConstantPoolIndex(CP->getIndex())
-          .addReg(Tmp1);
-      }
-      else if(Address.getOpcode() == ISD::FrameIndex) {
-        BuildMI(BB, Opc, 2, Result)
-          .addFrameIndex(cast<FrameIndexSDNode>(Address)->getIndex())
-          .addReg(Alpha::F31);
-      } else {
-        long offset;
-        SelectAddr(Address, Tmp1, offset);
-        BuildMI(BB, Opc, 2, Result).addImm(offset).addReg(Tmp1);
-      }
-      return Result;
-    }
   case ISD::ConstantFP:
     if (ConstantFPSDNode *CN = dyn_cast<ConstantFPSDNode>(N)) {
       if (CN->isExactlyValue(+0.0)) {
@@ -1323,63 +1236,6 @@
     }
     return Result;
 
-  case ISD::EXTLOAD:
-    {
-      //include a conversion sequence for float loads to double
-      if (Result != notIn)
-        ExprMap[N.getValue(1)] = notIn;   // Generate the token
-      else
-        Result = ExprMap[N.getValue(0)] = MakeReg(N.getValue(0).getValueType());
-
-      Tmp1 = MakeReg(MVT::f32);
-
-      assert(cast<MVTSDNode>(Node)->getExtraValueType() == MVT::f32 &&
-             "EXTLOAD not from f32");
-      assert(Node->getValueType(0) == MVT::f64 && "EXTLOAD not to f64");
-
-      SDOperand Chain   = N.getOperand(0);
-      SDOperand Address = N.getOperand(1);
-      Select(Chain);
-
-      if (EnableAlphaLSMark)
-      {
-        int i = getValueOffset(dyn_cast<SrcValueSDNode>(N.getOperand(2))
-                                  ->getValue());
-        int j = getFunctionOffset(BB->getParent()->getFunction());
-        BuildMI(BB, Alpha::MEMLABEL, 3).addImm(j).addImm(i).addImm(getUID());
-      }
-
-      if (Address.getOpcode() == ISD::GlobalAddress) {
-        AlphaLowering.restoreGP(BB);
-        has_sym = true;
-        BuildMI(BB, Alpha::LDS_SYM, 1, Tmp1)
-          .addGlobalAddress(cast<GlobalAddressSDNode>(Address)->getGlobal());
-      }
-      else if (ConstantPoolSDNode *CP =
-               dyn_cast<ConstantPoolSDNode>(N.getOperand(1)))
-      {
-        AlphaLowering.restoreGP(BB);
-        has_sym = true;
-        Tmp2 = MakeReg(MVT::i64);
-        BuildMI(BB, Alpha::LDAHr, 2, Tmp2).addConstantPoolIndex(CP->getIndex())
-          .addReg(Alpha::R29);
-        BuildMI(BB, Alpha::LDSr, 2, Tmp1).addConstantPoolIndex(CP->getIndex())
-          .addReg(Tmp2);
-      }
-      else if(Address.getOpcode() == ISD::FrameIndex) {
-        Tmp2 = cast<FrameIndexSDNode>(Address)->getIndex();
-        BuildMI(BB, Alpha::LDS, 2, Tmp1)
-          .addFrameIndex(cast<FrameIndexSDNode>(Address)->getIndex())
-          .addReg(Alpha::F31);
-      } else {
-        long offset;
-        SelectAddr(Address, Tmp2, offset);
-        BuildMI(BB, Alpha::LDS, 1, Tmp1).addImm(offset).addReg(Tmp2);
-      }
-      BuildMI(BB, Alpha::CVTST, 1, Result).addReg(Tmp1);
-      return Result;
-    }
-
   case ISD::SINT_TO_FP:
     {
       assert (N.getOperand(0).getValueType() == MVT::i64
@@ -1425,17 +1281,10 @@
     }
   }
 
-  if ((DestType == MVT::f64 || DestType == MVT::f32 ||
-       (
-        (opcode == ISD::LOAD || opcode == ISD::CopyFromReg ||
-         opcode == ISD::EXTLOAD) &&
-        (N.getValue(0).getValueType() == MVT::f32 ||
-         N.getValue(0).getValueType() == MVT::f64)
-       ))
-      && opcode != ISD::CALL && opcode != ISD::TAILCALL
-      )
+  if ((DestType == MVT::f64 || DestType == MVT::f32)
+      && opcode != ISD::CALL && opcode != ISD::TAILCALL)
     return SelectExprFP(N, Result);
-
+  
   switch (opcode) {
   default:
     Node->dump();
@@ -1550,10 +1399,15 @@
       SDOperand Address = N.getOperand(1);
       Select(Chain);
 
-      assert(Node->getValueType(0) == MVT::i64 &&
-             "Unknown type to sign extend to.");
+      bool fpext = true;
+
       if (opcode == ISD::LOAD)
-        Opc = Alpha::LDQ;
+        switch (Node->getValueType(0)) {
+        default: Node->dump(); assert(0 && "Bad load!");
+        case MVT::i64: Opc = Alpha::LDQ; break;
+        case MVT::f64: Opc = Alpha::LDT; break;
+        case MVT::f32: Opc = Alpha::LDS; break;
+        }
       else
         switch (cast<MVTSDNode>(Node)->getExtraValueType()) {
         default: Node->dump(); assert(0 && "Bad sign extend!");
@@ -1566,38 +1420,50 @@
           assert(opcode != ISD::SEXTLOAD && "Not zext"); break;
         }
 
-      if (EnableAlphaLSMark)
-      {
-        int i = getValueOffset(dyn_cast<SrcValueSDNode>(N.getOperand(2))
-                                 ->getValue());
-        int j = getFunctionOffset(BB->getParent()->getFunction());
-        BuildMI(BB, Alpha::MEMLABEL, 3).addImm(j).addImm(i).addImm(getUID());
+      int i = 0, j = 0;
+      if (EnableAlphaLSMark) {
+        i = getValueOffset(dyn_cast<SrcValueSDNode>(N.getOperand(2))
+                           ->getValue());
+        j = getFunctionOffset(BB->getParent()->getFunction());
       }
-
-      if (Address.getOpcode() == ISD::GlobalAddress) {
-        AlphaLowering.restoreGP(BB);
-        Opc = GetSymVersion(Opc);
-        has_sym = true;
-        BuildMI(BB, Opc, 1, Result)
-          .addGlobalAddress(cast<GlobalAddressSDNode>(Address)->getGlobal());
-      }
-      else if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(Address)) {
+      if (GlobalAddressSDNode *GASD = 
+          dyn_cast<GlobalAddressSDNode>(Address)) {
+        if (GASD->getGlobal()->isExternal()) {
+          Tmp1 = SelectExpr(Address);
+          if (EnableAlphaLSMark)
+            BuildMI(BB, Alpha::MEMLABEL, 3).addImm(j).addImm(i).addImm(getUID());
+          BuildMI(BB, Opc, 2, Result).addImm(0).addReg(Tmp1);
+        } else {
+          Tmp1 = MakeReg(MVT::i64);
+          AlphaLowering.restoreGP(BB);
+          BuildMI(BB, Alpha::LDAHr, 2, Tmp1)
+            .addGlobalAddress(GASD->getGlobal()).addReg(Alpha::R29);
+          if (EnableAlphaLSMark)
+            BuildMI(BB, Alpha::MEMLABEL, 3).addImm(j).addImm(i).addImm(getUID());
+          BuildMI(BB, GetRelVersion(Opc), 2, Result)
+            .addGlobalAddress(GASD->getGlobal()).addReg(Tmp1);
+        }
+      } else if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(Address)) {
         AlphaLowering.restoreGP(BB);
-        Opc = GetRelVersion(Opc);
         has_sym = true;
         Tmp1 = MakeReg(MVT::i64);
         BuildMI(BB, Alpha::LDAHr, 2, Tmp1).addConstantPoolIndex(CP->getIndex())
           .addReg(Alpha::R29);
-        BuildMI(BB, Opc, 2, Result).addConstantPoolIndex(CP->getIndex())
-          .addReg(Tmp1);
-      }
-      else if(Address.getOpcode() == ISD::FrameIndex) {
+        if (EnableAlphaLSMark)
+          BuildMI(BB, Alpha::MEMLABEL, 3).addImm(j).addImm(i).addImm(getUID());
+        BuildMI(BB, GetRelVersion(Opc), 2, Result)
+          .addConstantPoolIndex(CP->getIndex()).addReg(Tmp1);
+      } else if(Address.getOpcode() == ISD::FrameIndex) {
+        if (EnableAlphaLSMark)
+          BuildMI(BB, Alpha::MEMLABEL, 3).addImm(j).addImm(i).addImm(getUID());
         BuildMI(BB, Opc, 2, Result)
           .addFrameIndex(cast<FrameIndexSDNode>(Address)->getIndex())
           .addReg(Alpha::F31);
       } else {
         long offset;
         SelectAddr(Address, Tmp1, offset);
+        if (EnableAlphaLSMark)
+          BuildMI(BB, Alpha::MEMLABEL, 3).addImm(j).addImm(i).addImm(getUID());
         BuildMI(BB, Opc, 2, Result).addImm(offset).addReg(Tmp1);
       }
       return Result;
@@ -1606,7 +1472,11 @@
   case ISD::GlobalAddress:
     AlphaLowering.restoreGP(BB);
     has_sym = true;
-    BuildMI(BB, Alpha::LDQrl, 2, Result)
+
+    if (EnableAlphaLSMark)
+      BuildMI(BB, Alpha::MEMLABEL, 3).addImm(0).addImm(0).addImm(getUID());
+
+    BuildMI(BB, Alpha::LDQl, 2, Result)
       .addGlobalAddress(cast<GlobalAddressSDNode>(N)->getGlobal())
       .addReg(Alpha::R29);
     return Result;
@@ -1922,7 +1792,10 @@
       Select(Chain);
       unsigned r = dyn_cast<RegSDNode>(Node)->getReg();
       //std::cerr << "CopyFromReg " << Result << " = " << r << "\n";
-      BuildMI(BB, Alpha::BIS, 2, Result).addReg(r).addReg(r);
+      if (DestType == MVT::f32 || DestType == MVT::f64)
+        BuildMI(BB, Alpha::CPYS, 2, Result).addReg(r).addReg(r);
+      else
+        BuildMI(BB, Alpha::BIS, 2, Result).addReg(r).addReg(r);
       return Result;
     }
 
@@ -2422,32 +2295,24 @@
         }
       }
 
-      if (EnableAlphaLSMark)
-      {
-        int i = 
+      int i = 0, j = 0;
+      if (EnableAlphaLSMark) {
+        i = 
           getValueOffset(dyn_cast<SrcValueSDNode>(N.getOperand(3))->getValue());
-        int j = getFunctionOffset(BB->getParent()->getFunction());
-        BuildMI(BB, Alpha::MEMLABEL, 3).addImm(j).addImm(i).addImm(getUID());
+        j = getFunctionOffset(BB->getParent()->getFunction());
       }
 
-      if (Address.getOpcode() == ISD::GlobalAddress)
-      {
-        AlphaLowering.restoreGP(BB);
-        Opc = GetSymVersion(Opc);
-        has_sym = true;
-        BuildMI(BB, Opc, 2).addReg(Tmp1)
-          .addGlobalAddress(cast<GlobalAddressSDNode>(Address)->getGlobal());
-      }
-      else if(Address.getOpcode() == ISD::FrameIndex)
-      {
+      if(Address.getOpcode() == ISD::FrameIndex) {
+        if (EnableAlphaLSMark)
+          BuildMI(BB, Alpha::MEMLABEL, 3).addImm(j).addImm(i).addImm(getUID());
         BuildMI(BB, Opc, 3).addReg(Tmp1)
           .addFrameIndex(cast<FrameIndexSDNode>(Address)->getIndex())
           .addReg(Alpha::F31);
-      }
-      else
-      {
+      } else {
         long offset;
         SelectAddr(Address, Tmp2, offset);
+        if (EnableAlphaLSMark)
+          BuildMI(BB, Alpha::MEMLABEL, 3).addImm(j).addImm(i).addImm(getUID());
         BuildMI(BB, Opc, 3).addReg(Tmp1).addImm(offset).addReg(Tmp2);
       }
       return;


Index: llvm/lib/Target/Alpha/AlphaInstrInfo.td
diff -u llvm/lib/Target/Alpha/AlphaInstrInfo.td:1.48 llvm/lib/Target/Alpha/AlphaInstrInfo.td:1.49
--- llvm/lib/Target/Alpha/AlphaInstrInfo.td:1.48	Mon Jun 27 16:11:40 2005
+++ llvm/lib/Target/Alpha/AlphaInstrInfo.td	Tue Jun 28 19:31:08 2005
@@ -53,30 +53,6 @@
     Uses = [R29] in
       def CALL : PseudoInstAlpha< (ops s64imm:$TARGET), "jsr $TARGET">; //Jump to subroutine
 
-//These are evil as they get expanded into multiple instructions to take care of reallocation
-let Uses = [R29], Defs = [R28] in {
-  def LDQ_SYM : PseudoInstAlpha<(ops GPRC:$RA, s64imm:$DISP), "ldq $RA,$DISP">; //Load quadword
-  def LDS_SYM : PseudoInstAlpha<(ops GPRC:$RA, s64imm:$DISP), "lds $RA,$DISP">; //Load float
-  def LDT_SYM : PseudoInstAlpha<(ops GPRC:$RA, s64imm:$DISP), "ldt $RA,$DISP">; //Load double
-  def LDL_SYM : PseudoInstAlpha<(ops GPRC:$RA, s16imm:$DISP), "ldl $RA,$DISP">; // Load sign-extended longword
-  def LDBU_SYM : PseudoInstAlpha<(ops GPRC:$RA, s16imm:$DISP), "ldbu $RA,$DISP">; //Load zero-extended byte
-  def LDWU_SYM : PseudoInstAlpha<(ops GPRC:$RA, s16imm:$DISP), "ldwu $RA,$DISP">; //Load zero-extended word
-  def LDW_SYM : PseudoInstAlpha<(ops GPRC:$RA, s16imm:$DISP), "ldw $RA,$DISP">; // Load sign-extended word
-  def LDB_SYM : PseudoInstAlpha<(ops GPRC:$RA, s16imm:$DISP), "ldb $RA,$DISP">; //Load byte
-
-  def LDW : PseudoInstAlpha<(ops GPRC:$RA, s16imm:$DISP, GPRC:$RB), "ldw $RA,$DISP($RB)">; // Load sign-extended word
-  def LDB : PseudoInstAlpha<(ops GPRC:$RA, s16imm:$DISP, GPRC:$RB), "ldb $RA,$DISP($RB)">; //Load byte
-
-  def STB_SYM : PseudoInstAlpha<(ops GPRC:$RA, s16imm:$DISP), "stb $RA,$DISP">; // Store byte
-  def STW_SYM : PseudoInstAlpha<(ops GPRC:$RA, s16imm:$DISP), "stw $RA,$DISP">; // Store word
-  def STL_SYM : PseudoInstAlpha<(ops GPRC:$RA, s16imm:$DISP), "stl $RA,$DISP">; // Store longword
-  def STQ_SYM : PseudoInstAlpha<(ops GPRC:$RA, s16imm:$DISP), "stq $RA,$DISP">; //Store quadword
-
-  def STS_SYM : PseudoInstAlpha<(ops GPRC:$RA, s64imm:$DISP), "sts $RA,$DISP">; //store float
-  def STT_SYM : PseudoInstAlpha<(ops GPRC:$RA, s64imm:$DISP), "stt $RA,$DISP">; //store double
-}
-
-
 //RESULTS of these go to R27
 //These are also evil as the assembler expands them into calls
 let Uses = [R29], 
@@ -357,21 +333,22 @@
 def LDAH : MForm<0x08, (ops GPRC:$RA, s16imm:$DISP, GPRC:$RB), "ldah $RA,$DISP($RB)">;  //Load address high
 
 
-//Loads, int, Rellocated form
+//Loads, int, Rellocated Low form
 def LDLr : MForm<0x28, (ops GPRC:$RA, s16imm:$DISP, GPRC:$RB), "ldl $RA,$DISP($RB) !gprellow">; // Load sign-extended longword
 def LDQr : MForm<0x29, (ops GPRC:$RA, s16imm:$DISP, GPRC:$RB), "ldq $RA,$DISP($RB) !gprellow">; //Load quadword
 def LDBUr : MForm<0x0A, (ops GPRC:$RA, s16imm:$DISP, GPRC:$RB), "ldbu $RA,$DISP($RB) !gprellow">; //Load zero-extended byte
 def LDWUr : MForm<0x0C, (ops GPRC:$RA, s16imm:$DISP, GPRC:$RB), "ldwu $RA,$DISP($RB) !gprellow">; //Load zero-extended word
-def LDQrl : MForm<0x29, (ops GPRC:$RA, s16imm:$DISP, GPRC:$RB), "ldq $RA,$DISP($RB) !literal">; //Load quadword
 
-//Loads, float, Rellocated form
+//Loads, float, Rellocated Low form
 def LDSr : MForm<0x22, (ops FPRC:$RA, s16imm:$DISP, GPRC:$RB), "lds $RA,$DISP($RB) !gprellow">; //Load S_floating
 def LDTr : MForm<0x23, (ops FPRC:$RA, s16imm:$DISP, GPRC:$RB), "ldt $RA,$DISP($RB) !gprellow">; //Load T_floating
 
-//Load address, rellocated form
+//Load address, rellocated low and high form
 def LDAr : MForm<0x08, (ops GPRC:$RA, s16imm:$DISP, GPRC:$RB), "lda $RA,$DISP($RB) !gprellow">;  //Load address
 def LDAHr : MForm<0x08, (ops GPRC:$RA, s16imm:$DISP, GPRC:$RB), "ldah $RA,$DISP($RB) !gprelhigh">;  //Load address high
 
+//Load quad, rellocated literal form
+def LDQl : MForm<0x29, (ops GPRC:$RA, s16imm:$DISP, GPRC:$RB), "ldq $RA,$DISP($RB) !literal">; //Load quadword
 
 //Branches, int
 def BEQ : BForm<0x39, (ops GPRC:$RA, s21imm:$DISP), "beq $RA,$DISP">; //Branch if = zero


Index: llvm/lib/Target/Alpha/AlphaRegisterInfo.td
diff -u llvm/lib/Target/Alpha/AlphaRegisterInfo.td:1.10 llvm/lib/Target/Alpha/AlphaRegisterInfo.td:1.11
--- llvm/lib/Target/Alpha/AlphaRegisterInfo.td:1.10	Mon Jun 27 10:36:48 2005
+++ llvm/lib/Target/Alpha/AlphaRegisterInfo.td	Tue Jun 28 19:31:08 2005
@@ -82,9 +82,13 @@
 def GPRC : RegisterClass<i64, 64,
      // Volatile
      [R0, R1, R2, R3, R4, R5, R6, R7, R8, R16, R17, R18, R19, R20, R21, R22,
-      R23, R24, R25, R26, R27,
+      R23, R24, R25, 
+     //Special meaning, but volatile
+     R27, //procedure address
+     R26, //return address
+     R29, //global offset table address
      // Non-volatile
-     R9, R10, R11, R12, R13, R14, R29 ]>;
+     R9, R10, R11, R12, R13, R14 ]>;
      // Note: R28 is reserved for the assembler
 
 // Don't allocate 15, 29, 30, 31





From alenhar2 at cs.uiuc.edu  Tue Jun 28 19:39:28 2005
From: alenhar2 at cs.uiuc.edu (Andrew Lenharth)
Date: Tue, 28 Jun 2005 19:39:28 -0500
Subject: [llvm-commits] CVS: llvm/lib/Target/Alpha/AlphaISelPattern.cpp
	AlphaInstrInfo.td 
Message-ID: <200506290039.TAA01746@zion.cs.uiuc.edu>



Changes in directory llvm/lib/Target/Alpha:

AlphaISelPattern.cpp updated: 1.137 -> 1.138
AlphaInstrInfo.td updated: 1.49 -> 1.50
---
Log message:

support more relocations for stores also

---
Diffs of the changes:  (+36 -1)

 AlphaISelPattern.cpp |   26 +++++++++++++++++++++++++-
 AlphaInstrInfo.td    |   11 +++++++++++
 2 files changed, 36 insertions(+), 1 deletion(-)


Index: llvm/lib/Target/Alpha/AlphaISelPattern.cpp
diff -u llvm/lib/Target/Alpha/AlphaISelPattern.cpp:1.137 llvm/lib/Target/Alpha/AlphaISelPattern.cpp:1.138
--- llvm/lib/Target/Alpha/AlphaISelPattern.cpp:1.137	Tue Jun 28 19:31:08 2005
+++ llvm/lib/Target/Alpha/AlphaISelPattern.cpp	Tue Jun 28 19:39:17 2005
@@ -855,6 +855,13 @@
   case Alpha::LDL: return Alpha::LDLr;
   case Alpha::LDBU: return Alpha::LDBUr;
   case Alpha::LDWU: return Alpha::LDWUr;
+  case Alpha::STB: return Alpha::STBr;
+  case Alpha::STW: return Alpha::STWr;
+  case Alpha::STL: return Alpha::STLr;
+  case Alpha::STQ: return Alpha::STQr;
+  case Alpha::STS: return Alpha::STSr;
+  case Alpha::STT: return Alpha::STTr;
+
   }
 }
 
@@ -2302,7 +2309,24 @@
         j = getFunctionOffset(BB->getParent()->getFunction());
       }
 
-      if(Address.getOpcode() == ISD::FrameIndex) {
+      if (GlobalAddressSDNode *GASD = 
+          dyn_cast<GlobalAddressSDNode>(Address)) {
+        if (GASD->getGlobal()->isExternal()) {
+          Tmp2 = SelectExpr(Address);
+          if (EnableAlphaLSMark)
+            BuildMI(BB, Alpha::MEMLABEL, 3).addImm(j).addImm(i).addImm(getUID());
+          BuildMI(BB, Opc, 3).addReg(Tmp1).addImm(0).addReg(Tmp2);
+        } else {
+          Tmp2 = MakeReg(MVT::i64);
+          AlphaLowering.restoreGP(BB);
+          BuildMI(BB, Alpha::LDAHr, 2, Tmp2)
+            .addGlobalAddress(GASD->getGlobal()).addReg(Alpha::R29);
+          if (EnableAlphaLSMark)
+            BuildMI(BB, Alpha::MEMLABEL, 3).addImm(j).addImm(i).addImm(getUID());
+          BuildMI(BB, GetRelVersion(Opc), 3).addReg(Tmp1)
+            .addGlobalAddress(GASD->getGlobal()).addReg(Tmp2);
+        }
+      } else if(Address.getOpcode() == ISD::FrameIndex) {
         if (EnableAlphaLSMark)
           BuildMI(BB, Alpha::MEMLABEL, 3).addImm(j).addImm(i).addImm(getUID());
         BuildMI(BB, Opc, 3).addReg(Tmp1)


Index: llvm/lib/Target/Alpha/AlphaInstrInfo.td
diff -u llvm/lib/Target/Alpha/AlphaInstrInfo.td:1.49 llvm/lib/Target/Alpha/AlphaInstrInfo.td:1.50
--- llvm/lib/Target/Alpha/AlphaInstrInfo.td:1.49	Tue Jun 28 19:31:08 2005
+++ llvm/lib/Target/Alpha/AlphaInstrInfo.td	Tue Jun 28 19:39:17 2005
@@ -350,6 +350,17 @@
 //Load quad, rellocated literal form
 def LDQl : MForm<0x29, (ops GPRC:$RA, s16imm:$DISP, GPRC:$RB), "ldq $RA,$DISP($RB) !literal">; //Load quadword
 
+//Stores, int
+def STBr : MForm<0x0E, (ops GPRC:$RA, s16imm:$DISP, GPRC:$RB), "stb $RA,$DISP($RB) !gprellow">; // Store byte
+def STWr : MForm<0x0D, (ops GPRC:$RA, s16imm:$DISP, GPRC:$RB), "stw $RA,$DISP($RB) !gprellow">; // Store word
+def STLr : MForm<0x2C, (ops GPRC:$RA, s16imm:$DISP, GPRC:$RB), "stl $RA,$DISP($RB) !gprellow">; // Store longword
+def STQr : MForm<0x2D, (ops GPRC:$RA, s16imm:$DISP, GPRC:$RB), "stq $RA,$DISP($RB) !gprellow">; //Store quadword
+
+//Stores, float
+def STSr : MForm<0x26, (ops FPRC:$RA, s16imm:$DISP, GPRC:$RB), "sts $RA,$DISP($RB) !gprellow">; //Store S_floating
+def STTr : MForm<0x27, (ops FPRC:$RA, s16imm:$DISP, GPRC:$RB), "stt $RA,$DISP($RB) !gprellow">; //Store T_floating
+
+
 //Branches, int
 def BEQ : BForm<0x39, (ops GPRC:$RA, s21imm:$DISP), "beq $RA,$DISP">; //Branch if = zero
 def BGE : BForm<0x3E, (ops GPRC:$RA, s21imm:$DISP), "bge $RA,$DISP">; //Branch if >= zero





From alenhar2 at cs.uiuc.edu  Wed Jun 29 07:23:45 2005
From: alenhar2 at cs.uiuc.edu (Andrew Lenharth)
Date: Wed, 29 Jun 2005 07:23:45 -0500
Subject: [llvm-commits] CVS: llvm/lib/Target/Alpha/AlphaISelPattern.cpp 
Message-ID: <200506291223.HAA30986@zion.cs.uiuc.edu>



Changes in directory llvm/lib/Target/Alpha:

AlphaISelPattern.cpp updated: 1.138 -> 1.139
---
Log message:

fix most regressions

---
Diffs of the changes:  (+2 -1)

 AlphaISelPattern.cpp |    3 ++-
 1 files changed, 2 insertions(+), 1 deletion(-)


Index: llvm/lib/Target/Alpha/AlphaISelPattern.cpp
diff -u llvm/lib/Target/Alpha/AlphaISelPattern.cpp:1.138 llvm/lib/Target/Alpha/AlphaISelPattern.cpp:1.139
--- llvm/lib/Target/Alpha/AlphaISelPattern.cpp:1.138	Tue Jun 28 19:39:17 2005
+++ llvm/lib/Target/Alpha/AlphaISelPattern.cpp	Wed Jun 29 07:23:34 2005
@@ -1289,7 +1289,8 @@
   }
 
   if ((DestType == MVT::f64 || DestType == MVT::f32)
-      && opcode != ISD::CALL && opcode != ISD::TAILCALL)
+      && opcode != ISD::CALL && opcode != ISD::TAILCALL 
+      && opcode != ISD::CopyFromReg && opcode != ISD::LOAD)
     return SelectExprFP(N, Result);
   
   switch (opcode) {





From alenhar2 at cs.uiuc.edu  Wed Jun 29 07:50:02 2005
From: alenhar2 at cs.uiuc.edu (Andrew Lenharth)
Date: Wed, 29 Jun 2005 07:50:02 -0500
Subject: [llvm-commits] CVS: llvm/lib/Target/Alpha/AlphaISelPattern.cpp 
Message-ID: <200506291250.HAA00521@zion.cs.uiuc.edu>



Changes in directory llvm/lib/Target/Alpha:

AlphaISelPattern.cpp updated: 1.139 -> 1.140
---
Log message:

unify SelectExpr and SelectFP

---
Diffs of the changes:  (+155 -190)

 AlphaISelPattern.cpp |  345 ++++++++++++++++++++++-----------------------------
 1 files changed, 155 insertions(+), 190 deletions(-)


Index: llvm/lib/Target/Alpha/AlphaISelPattern.cpp
diff -u llvm/lib/Target/Alpha/AlphaISelPattern.cpp:1.139 llvm/lib/Target/Alpha/AlphaISelPattern.cpp:1.140
--- llvm/lib/Target/Alpha/AlphaISelPattern.cpp:1.139	Wed Jun 29 07:23:34 2005
+++ llvm/lib/Target/Alpha/AlphaISelPattern.cpp	Wed Jun 29 07:49:51 2005
@@ -566,7 +566,6 @@
   virtual void EmitFunctionEntryCode(Function &Fn, MachineFunction &MF);
 
   unsigned SelectExpr(SDOperand N);
-  unsigned SelectExprFP(SDOperand N, unsigned Result);
   void Select(SDOperand N);
 
   void SelectAddr(SDOperand N, unsigned& Reg, long& offset);
@@ -1081,184 +1080,6 @@
   abort(); //Should never be reached
 }
 
-unsigned AlphaISel::SelectExprFP(SDOperand N, unsigned Result)
-{
-  unsigned Tmp1, Tmp2, Tmp3;
-  unsigned Opc = 0;
-  SDNode *Node = N.Val;
-  MVT::ValueType DestType = N.getValueType();
-  unsigned opcode = N.getOpcode();
-
-  switch (opcode) {
-  default:
-    Node->dump();
-    assert(0 && "Node not handled!\n");
-
-  case ISD::UNDEF: {
-    BuildMI(BB, Alpha::IDEF, 0, Result);
-    return Result;
-  }
-
-  case ISD::FNEG:
-    if(ISD::FABS == N.getOperand(0).getOpcode())
-      {
-        Tmp1 = SelectExpr(N.getOperand(0).getOperand(0));
-        BuildMI(BB, Alpha::CPYSN, 2, Result).addReg(Alpha::F31).addReg(Tmp1);
-      } else {
-        Tmp1 = SelectExpr(N.getOperand(0));
-        BuildMI(BB, Alpha::CPYSN, 2, Result).addReg(Tmp1).addReg(Tmp1);
-      }
-    return Result;
-
-  case ISD::FABS:
-    Tmp1 = SelectExpr(N.getOperand(0));
-    BuildMI(BB, Alpha::CPYS, 2, Result).addReg(Alpha::F31).addReg(Tmp1);
-    return Result;
-
-  case ISD::SELECT:
-    {
-      //Tmp1 = SelectExpr(N.getOperand(0)); //Cond
-      unsigned TV = SelectExpr(N.getOperand(1)); //Use if TRUE
-      unsigned FV = SelectExpr(N.getOperand(2)); //Use if FALSE
-
-      SDOperand CC = N.getOperand(0);
-      SetCCSDNode* SetCC = dyn_cast<SetCCSDNode>(CC.Val);
-
-      if (CC.getOpcode() == ISD::SETCC &&
-          !MVT::isInteger(SetCC->getOperand(0).getValueType()))
-      { //FP Setcc -> Select yay!
-
-
-        //for a cmp b: c = a - b;
-        //a = b: c = 0
-        //a < b: c < 0
-        //a > b: c > 0
-
-        bool invTest = false;
-        unsigned Tmp3;
-
-        ConstantFPSDNode *CN;
-        if ((CN = dyn_cast<ConstantFPSDNode>(SetCC->getOperand(1)))
-            && (CN->isExactlyValue(+0.0) || CN->isExactlyValue(-0.0)))
-          Tmp3 = SelectExpr(SetCC->getOperand(0));
-        else if ((CN = dyn_cast<ConstantFPSDNode>(SetCC->getOperand(0)))
-                 && (CN->isExactlyValue(+0.0) || CN->isExactlyValue(-0.0)))
-        {
-          Tmp3 = SelectExpr(SetCC->getOperand(1));
-          invTest = true;
-        }
-        else
-        {
-          unsigned Tmp1 = SelectExpr(SetCC->getOperand(0));
-          unsigned Tmp2 = SelectExpr(SetCC->getOperand(1));
-          bool isD = SetCC->getOperand(0).getValueType() == MVT::f64;
-          Tmp3 = MakeReg(isD ? MVT::f64 : MVT::f32);
-          BuildMI(BB, isD ? Alpha::SUBT : Alpha::SUBS, 2, Tmp3)
-            .addReg(Tmp1).addReg(Tmp2);
-        }
-
-        switch (SetCC->getCondition()) {
-        default: CC.Val->dump(); assert(0 && "Unknown FP comparison!");
-        case ISD::SETEQ: Opc = invTest ? Alpha::FCMOVNE : Alpha::FCMOVEQ; break;
-        case ISD::SETLT: Opc = invTest ? Alpha::FCMOVGT : Alpha::FCMOVLT; break;
-        case ISD::SETLE: Opc = invTest ? Alpha::FCMOVGE : Alpha::FCMOVLE; break;
-        case ISD::SETGT: Opc = invTest ? Alpha::FCMOVLT : Alpha::FCMOVGT; break;
-        case ISD::SETGE: Opc = invTest ? Alpha::FCMOVLE : Alpha::FCMOVGE; break;
-        case ISD::SETNE: Opc = invTest ? Alpha::FCMOVEQ : Alpha::FCMOVNE; break;
-        }
-        BuildMI(BB, Opc, 3, Result).addReg(FV).addReg(TV).addReg(Tmp3);
-        return Result;
-      }
-      else
-      {
-        Tmp1 = SelectExpr(N.getOperand(0)); //Cond
-        BuildMI(BB, Alpha::FCMOVEQ_INT, 3, Result).addReg(TV).addReg(FV)
-          .addReg(Tmp1);
-//         // Spill the cond to memory and reload it from there.
-//         unsigned Tmp4 = MakeReg(MVT::f64);
-//         MoveIntFP(Tmp1, Tmp4, true);
-//         //now ideally, we don't have to do anything to the flag...
-//         // Get the condition into the zero flag.
-//         BuildMI(BB, Alpha::FCMOVEQ, 3, Result).addReg(TV).addReg(FV).addReg(Tmp4);
-        return Result;
-      }
-    }
-
-  case ISD::FP_ROUND:
-    assert (DestType == MVT::f32 &&
-            N.getOperand(0).getValueType() == MVT::f64 &&
-            "only f64 to f32 conversion supported here");
-    Tmp1 = SelectExpr(N.getOperand(0));
-    BuildMI(BB, Alpha::CVTTS, 1, Result).addReg(Tmp1);
-    return Result;
-
-  case ISD::FP_EXTEND:
-    assert (DestType == MVT::f64 &&
-            N.getOperand(0).getValueType() == MVT::f32 &&
-            "only f32 to f64 conversion supported here");
-    Tmp1 = SelectExpr(N.getOperand(0));
-    BuildMI(BB, Alpha::CVTST, 1, Result).addReg(Tmp1);
-    return Result;
-
-  case ISD::ConstantFP:
-    if (ConstantFPSDNode *CN = dyn_cast<ConstantFPSDNode>(N)) {
-      if (CN->isExactlyValue(+0.0)) {
-        BuildMI(BB, Alpha::CPYS, 2, Result).addReg(Alpha::F31)
-          .addReg(Alpha::F31);
-      } else if ( CN->isExactlyValue(-0.0)) {
-        BuildMI(BB, Alpha::CPYSN, 2, Result).addReg(Alpha::F31)
-          .addReg(Alpha::F31);
-      } else {
-        abort();
-      }
-    }
-    return Result;
-
-  case ISD::SDIV:
-  case ISD::MUL:
-  case ISD::ADD:
-  case ISD::SUB:
-  switch( opcode ) {
-      case ISD::MUL: Opc = DestType == MVT::f64 ? Alpha::MULT : Alpha::MULS; 
-      break;
-      case ISD::ADD: Opc = DestType == MVT::f64 ? Alpha::ADDT : Alpha::ADDS; 
-      break;
-      case ISD::SUB: Opc = DestType == MVT::f64 ? Alpha::SUBT : Alpha::SUBS; 
-      break;
-      case ISD::SDIV: Opc = DestType == MVT::f64 ? Alpha::DIVT : Alpha::DIVS;
-      break;
-    };
-
-    ConstantFPSDNode *CN;
-    if (opcode == ISD::SUB
-        && (CN = dyn_cast<ConstantFPSDNode>(N.getOperand(0)))
-        && (CN->isExactlyValue(+0.0) || CN->isExactlyValue(-0.0)))
-    {
-      Tmp2 = SelectExpr(N.getOperand(1));
-      BuildMI(BB, Alpha::CPYSN, 2, Result).addReg(Tmp2).addReg(Tmp2);
-    } else {
-      Tmp1 = SelectExpr(N.getOperand(0));
-      Tmp2 = SelectExpr(N.getOperand(1));
-      BuildMI(BB, Opc, 2, Result).addReg(Tmp1).addReg(Tmp2);
-    }
-    return Result;
-
-  case ISD::SINT_TO_FP:
-    {
-      assert (N.getOperand(0).getValueType() == MVT::i64
-              && "only quads can be loaded from");
-      Tmp1 = SelectExpr(N.getOperand(0));  // Get the operand register
-      Tmp2 = MakeReg(MVT::f64);
-      MoveInt2FP(Tmp1, Tmp2, true);
-      Opc = DestType == MVT::f64 ? Alpha::CVTQT : Alpha::CVTQS;
-      BuildMI(BB, Opc, 1, Result).addReg(Tmp2);
-      return Result;
-    }
-  }
-  assert(0 && "should not get here");
-  return 0;
-}
-
 unsigned AlphaISel::SelectExpr(SDOperand N) {
   unsigned Result;
   unsigned Tmp1, Tmp2 = 0, Tmp3;
@@ -1267,6 +1088,7 @@
 
   SDNode *Node = N.Val;
   MVT::ValueType DestType = N.getValueType();
+  bool isFP = DestType == MVT::f64 || DestType == MVT::f32;
 
   unsigned &Reg = ExprMap[N];
   if (Reg) return Reg;
@@ -1288,11 +1110,6 @@
     }
   }
 
-  if ((DestType == MVT::f64 || DestType == MVT::f32)
-      && opcode != ISD::CALL && opcode != ISD::TAILCALL 
-      && opcode != ISD::CopyFromReg && opcode != ISD::LOAD)
-    return SelectExprFP(N, Result);
-  
   switch (opcode) {
   default:
     Node->dump();
@@ -1800,7 +1617,7 @@
       Select(Chain);
       unsigned r = dyn_cast<RegSDNode>(Node)->getReg();
       //std::cerr << "CopyFromReg " << Result << " = " << r << "\n";
-      if (DestType == MVT::f32 || DestType == MVT::f64)
+      if (isFP)
         BuildMI(BB, Alpha::CPYS, 2, Result).addReg(r).addReg(r);
       else
         BuildMI(BB, Alpha::BIS, 2, Result).addReg(r).addReg(r);
@@ -1876,7 +1693,6 @@
   case ISD::SRL:
   case ISD::SRA:
   case ISD::MUL:
-    assert (DestType == MVT::i64 && "Only do arithmetic on i64s!");
     if(N.getOperand(1).getOpcode() == ISD::Constant &&
        cast<ConstantSDNode>(N.getOperand(1))->getValue() <= 255)
     {
@@ -1900,7 +1716,10 @@
       case ISD::SHL: Opc = Alpha::SL; break;
       case ISD::SRL: Opc = Alpha::SRL; break;
       case ISD::SRA: Opc = Alpha::SRA; break;
-      case ISD::MUL: Opc = Alpha::MULQ; break;
+      case ISD::MUL: 
+        Opc = isFP ? (DestType == MVT::f64 ? Alpha::MULT : Alpha::MULS) 
+          : Alpha::MULQ;
+        break;
       };
       Tmp1 = SelectExpr(N.getOperand(0));
       Tmp2 = SelectExpr(N.getOperand(1));
@@ -1910,7 +1729,25 @@
 
   case ISD::ADD:
   case ISD::SUB:
-    {
+    if (isFP) {
+      ConstantFPSDNode *CN;
+      if (opcode == ISD::ADD)
+        Opc = DestType == MVT::f64 ? Alpha::ADDT : Alpha::ADDS;
+      else
+        Opc = DestType == MVT::f64 ? Alpha::SUBT : Alpha::SUBS;
+      if (opcode == ISD::SUB
+          && (CN = dyn_cast<ConstantFPSDNode>(N.getOperand(0)))
+          && (CN->isExactlyValue(+0.0) || CN->isExactlyValue(-0.0)))
+      {
+        Tmp2 = SelectExpr(N.getOperand(1));
+        BuildMI(BB, Alpha::CPYSN, 2, Result).addReg(Tmp2).addReg(Tmp2);
+      } else {
+        Tmp1 = SelectExpr(N.getOperand(0));
+        Tmp2 = SelectExpr(N.getOperand(1));
+        BuildMI(BB, Opc, 2, Result).addReg(Tmp1).addReg(Tmp2);
+      }
+      return Result;
+    } else {
       bool isAdd = opcode == ISD::ADD;
 
       //first check for Scaled Adds and Subs!
@@ -1977,7 +1814,12 @@
     }
 
   case ISD::SDIV:
-    {
+    if (isFP) {
+      Tmp1 = SelectExpr(N.getOperand(0));
+      Tmp2 = SelectExpr(N.getOperand(1));
+      BuildMI(BB, DestType == MVT::f64 ? Alpha::DIVT : Alpha::DIVS, 2, Result)
+        .addReg(Tmp1).addReg(Tmp2);
+    } else {
       ConstantSDNode* CSD;
       //check if we can convert into a shift!
       if ((CSD = dyn_cast<ConstantSDNode>(N.getOperand(1).Val)) &&
@@ -2070,7 +1912,73 @@
     }
 
   case ISD::SELECT:
-    {
+    if (isFP) {
+      //Tmp1 = SelectExpr(N.getOperand(0)); //Cond
+      unsigned TV = SelectExpr(N.getOperand(1)); //Use if TRUE
+      unsigned FV = SelectExpr(N.getOperand(2)); //Use if FALSE
+
+      SDOperand CC = N.getOperand(0);
+      SetCCSDNode* SetCC = dyn_cast<SetCCSDNode>(CC.Val);
+
+      if (CC.getOpcode() == ISD::SETCC &&
+          !MVT::isInteger(SetCC->getOperand(0).getValueType()))
+      { //FP Setcc -> Select yay!
+
+        
+        //for a cmp b: c = a - b;
+        //a = b: c = 0
+        //a < b: c < 0
+        //a > b: c > 0
+
+        bool invTest = false;
+        unsigned Tmp3;
+
+        ConstantFPSDNode *CN;
+        if ((CN = dyn_cast<ConstantFPSDNode>(SetCC->getOperand(1)))
+            && (CN->isExactlyValue(+0.0) || CN->isExactlyValue(-0.0)))
+          Tmp3 = SelectExpr(SetCC->getOperand(0));
+        else if ((CN = dyn_cast<ConstantFPSDNode>(SetCC->getOperand(0)))
+                 && (CN->isExactlyValue(+0.0) || CN->isExactlyValue(-0.0)))
+        {
+          Tmp3 = SelectExpr(SetCC->getOperand(1));
+          invTest = true;
+        }
+        else
+        {
+          unsigned Tmp1 = SelectExpr(SetCC->getOperand(0));
+          unsigned Tmp2 = SelectExpr(SetCC->getOperand(1));
+          bool isD = SetCC->getOperand(0).getValueType() == MVT::f64;
+          Tmp3 = MakeReg(isD ? MVT::f64 : MVT::f32);
+          BuildMI(BB, isD ? Alpha::SUBT : Alpha::SUBS, 2, Tmp3)
+            .addReg(Tmp1).addReg(Tmp2);
+        }
+
+        switch (SetCC->getCondition()) {
+        default: CC.Val->dump(); assert(0 && "Unknown FP comparison!");
+        case ISD::SETEQ: Opc = invTest ? Alpha::FCMOVNE : Alpha::FCMOVEQ; break;
+        case ISD::SETLT: Opc = invTest ? Alpha::FCMOVGT : Alpha::FCMOVLT; break;
+        case ISD::SETLE: Opc = invTest ? Alpha::FCMOVGE : Alpha::FCMOVLE; break;
+        case ISD::SETGT: Opc = invTest ? Alpha::FCMOVLT : Alpha::FCMOVGT; break;
+        case ISD::SETGE: Opc = invTest ? Alpha::FCMOVLE : Alpha::FCMOVGE; break;
+        case ISD::SETNE: Opc = invTest ? Alpha::FCMOVEQ : Alpha::FCMOVNE; break;
+        }
+        BuildMI(BB, Opc, 3, Result).addReg(FV).addReg(TV).addReg(Tmp3);
+        return Result;
+      }
+      else
+      {
+        Tmp1 = SelectExpr(N.getOperand(0)); //Cond
+        BuildMI(BB, Alpha::FCMOVEQ_INT, 3, Result).addReg(TV).addReg(FV)
+          .addReg(Tmp1);
+//         // Spill the cond to memory and reload it from there.
+//         unsigned Tmp4 = MakeReg(MVT::f64);
+//         MoveIntFP(Tmp1, Tmp4, true);
+//         //now ideally, we don't have to do anything to the flag...
+//         // Get the condition into the zero flag.
+//         BuildMI(BB, Alpha::FCMOVEQ, 3, Result).addReg(TV).addReg(FV).addReg(Tmp4);
+        return Result;
+      }  
+    } else {
       //FIXME: look at parent to decide if intCC can be folded, or if setCC(FP)
       //and can save stack use
       //Tmp1 = SelectExpr(N.getOperand(0)); //Cond
@@ -2176,6 +2084,63 @@
       }
       return Result;
     }
+  case ISD::FNEG:
+    if(ISD::FABS == N.getOperand(0).getOpcode())
+      {
+        Tmp1 = SelectExpr(N.getOperand(0).getOperand(0));
+        BuildMI(BB, Alpha::CPYSN, 2, Result).addReg(Alpha::F31).addReg(Tmp1);
+      } else {
+        Tmp1 = SelectExpr(N.getOperand(0));
+        BuildMI(BB, Alpha::CPYSN, 2, Result).addReg(Tmp1).addReg(Tmp1);
+      }
+    return Result;
+
+  case ISD::FABS:
+    Tmp1 = SelectExpr(N.getOperand(0));
+    BuildMI(BB, Alpha::CPYS, 2, Result).addReg(Alpha::F31).addReg(Tmp1);
+    return Result;
+
+  case ISD::FP_ROUND:
+    assert (DestType == MVT::f32 &&
+            N.getOperand(0).getValueType() == MVT::f64 &&
+            "only f64 to f32 conversion supported here");
+    Tmp1 = SelectExpr(N.getOperand(0));
+    BuildMI(BB, Alpha::CVTTS, 1, Result).addReg(Tmp1);
+    return Result;
+
+  case ISD::FP_EXTEND:
+    assert (DestType == MVT::f64 &&
+            N.getOperand(0).getValueType() == MVT::f32 &&
+            "only f32 to f64 conversion supported here");
+    Tmp1 = SelectExpr(N.getOperand(0));
+    BuildMI(BB, Alpha::CVTST, 1, Result).addReg(Tmp1);
+    return Result;
+
+  case ISD::ConstantFP:
+    if (ConstantFPSDNode *CN = dyn_cast<ConstantFPSDNode>(N)) {
+      if (CN->isExactlyValue(+0.0)) {
+        BuildMI(BB, Alpha::CPYS, 2, Result).addReg(Alpha::F31)
+          .addReg(Alpha::F31);
+      } else if ( CN->isExactlyValue(-0.0)) {
+        BuildMI(BB, Alpha::CPYSN, 2, Result).addReg(Alpha::F31)
+          .addReg(Alpha::F31);
+      } else {
+        abort();
+      }
+    }
+    return Result;
+
+  case ISD::SINT_TO_FP:
+    {
+      assert (N.getOperand(0).getValueType() == MVT::i64
+              && "only quads can be loaded from");
+      Tmp1 = SelectExpr(N.getOperand(0));  // Get the operand register
+      Tmp2 = MakeReg(MVT::f64);
+      MoveInt2FP(Tmp1, Tmp2, true);
+      Opc = DestType == MVT::f64 ? Alpha::CVTQT : Alpha::CVTQS;
+      BuildMI(BB, Opc, 1, Result).addReg(Tmp2);
+      return Result;
+    }
   }
 
   return 0;





From alenhar2 at cs.uiuc.edu  Wed Jun 29 08:35:17 2005
From: alenhar2 at cs.uiuc.edu (Andrew Lenharth)
Date: Wed, 29 Jun 2005 08:35:17 -0500
Subject: [llvm-commits] CVS: llvm/lib/Target/Alpha/AlphaISelPattern.cpp 
Message-ID: <200506291335.IAA00699@zion.cs.uiuc.edu>



Changes in directory llvm/lib/Target/Alpha:

AlphaISelPattern.cpp updated: 1.140 -> 1.141
---
Log message:

thinko

---
Diffs of the changes:  (+1 -0)

 AlphaISelPattern.cpp |    1 +
 1 files changed, 1 insertion(+)


Index: llvm/lib/Target/Alpha/AlphaISelPattern.cpp
diff -u llvm/lib/Target/Alpha/AlphaISelPattern.cpp:1.140 llvm/lib/Target/Alpha/AlphaISelPattern.cpp:1.141
--- llvm/lib/Target/Alpha/AlphaISelPattern.cpp:1.140	Wed Jun 29 07:49:51 2005
+++ llvm/lib/Target/Alpha/AlphaISelPattern.cpp	Wed Jun 29 08:35:05 2005
@@ -1819,6 +1819,7 @@
       Tmp2 = SelectExpr(N.getOperand(1));
       BuildMI(BB, DestType == MVT::f64 ? Alpha::DIVT : Alpha::DIVS, 2, Result)
         .addReg(Tmp1).addReg(Tmp2);
+      return Result;
     } else {
       ConstantSDNode* CSD;
       //check if we can convert into a shift!





From criswell at cs.uiuc.edu  Wed Jun 29 10:03:35 2005
From: criswell at cs.uiuc.edu (John Criswell)
Date: Wed, 29 Jun 2005 10:03:35 -0500
Subject: [llvm-commits] CVS: llvm/lib/Transforms/IPO/SimplifyLibCalls.cpp 
Message-ID: <200506291503.KAA09199@choi.cs.uiuc.edu>



Changes in directory llvm/lib/Transforms/IPO:

SimplifyLibCalls.cpp updated: 1.43 -> 1.44
---
Log message:

Basic fix for PR#591; don't convert an fprintf() to an fwrite() if there
is a mismatch in their character type pointers (i.e. fprintf() prints an
array of ubytes while fwrite() takes an array of sbytes).
We can probably do better than this (such as casting the ubyte to an
sbyte).


---
Diffs of the changes:  (+9 -0)

 SimplifyLibCalls.cpp |    9 +++++++++
 1 files changed, 9 insertions(+)


Index: llvm/lib/Transforms/IPO/SimplifyLibCalls.cpp
diff -u llvm/lib/Transforms/IPO/SimplifyLibCalls.cpp:1.43 llvm/lib/Transforms/IPO/SimplifyLibCalls.cpp:1.44
--- llvm/lib/Transforms/IPO/SimplifyLibCalls.cpp:1.43	Sat Jun 18 12:46:28 2005
+++ llvm/lib/Transforms/IPO/SimplifyLibCalls.cpp	Wed Jun 29 10:03:18 2005
@@ -1305,6 +1305,15 @@
       Function* fwrite_func = SLC.get_fwrite(FILEptr_type);
       if (!fwrite_func)
         return false;
+
+      // Make sure that the fprintf() and fwrite() functions both take the
+      // same type of char pointer.
+      if (ci->getOperand(2)->getType() !=
+          fwrite_func->getFunctionType()->getParamType(0))
+      {
+        return false;
+      }
+
       std::vector<Value*> args;
       args.push_back(ci->getOperand(2));
       args.push_back(ConstantUInt::get(SLC.getIntPtrType(),len));





From alenhar2 at cs.uiuc.edu  Wed Jun 29 10:57:31 2005
From: alenhar2 at cs.uiuc.edu (Andrew Lenharth)
Date: Wed, 29 Jun 2005 10:57:31 -0500
Subject: [llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
	SelectionDAGISel.cpp 
Message-ID: <200506291557.KAA02380@zion.cs.uiuc.edu>



Changes in directory llvm/lib/CodeGen/SelectionDAG:

SelectionDAG.cpp updated: 1.120 -> 1.121
SelectionDAGISel.cpp updated: 1.62 -> 1.63
---
Log message:

tracking the instructions causing loads and stores provides more information than just the pointer being loaded or stored

---
Diffs of the changes:  (+2 -4)

 SelectionDAG.cpp     |    2 --
 SelectionDAGISel.cpp |    4 ++--
 2 files changed, 2 insertions(+), 4 deletions(-)


Index: llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp:1.120 llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp:1.121
--- llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp:1.120	Thu Jun 16 02:06:03 2005
+++ llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp	Wed Jun 29 10:57:19 2005
@@ -1394,8 +1394,6 @@
 }
 
 SDOperand SelectionDAG::getSrcValue(const Value *V, int Offset) {
-  assert((!V || isa<PointerType>(V->getType())) &&
-         "SrcValue is not a pointer?");
   SDNode *&N = ValueNodes[std::make_pair(V, Offset)];
   if (N) return SDOperand(N, 0);
 


Index: llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.62 llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.63
--- llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.62	Wed Jun 22 16:04:42 2005
+++ llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp	Wed Jun 29 10:57:19 2005
@@ -644,7 +644,7 @@
   }
 
   SDOperand L = DAG.getLoad(TLI.getValueType(I.getType()), Root, Ptr,
-                            DAG.getSrcValue(I.getOperand(0)));
+                            DAG.getSrcValue(&I));
   setValue(&I, L);
 
   if (I.isVolatile())
@@ -659,7 +659,7 @@
   SDOperand Src = getValue(SrcV);
   SDOperand Ptr = getValue(I.getOperand(1));
   DAG.setRoot(DAG.getNode(ISD::STORE, MVT::Other, getRoot(), Src, Ptr,
-                          DAG.getSrcValue(I.getOperand(1))));
+                          DAG.getSrcValue(&I)));
 }
 
 void SelectionDAGLowering::visitCall(CallInst &I) {





From alenhar2 at cs.uiuc.edu  Wed Jun 29 10:57:31 2005
From: alenhar2 at cs.uiuc.edu (Andrew Lenharth)
Date: Wed, 29 Jun 2005 10:57:31 -0500
Subject: [llvm-commits] CVS: llvm/lib/Target/Alpha/AlphaISelPattern.cpp 
Message-ID: <200506291557.KAA02384@zion.cs.uiuc.edu>



Changes in directory llvm/lib/Target/Alpha:

AlphaISelPattern.cpp updated: 1.141 -> 1.142
---
Log message:

tracking the instructions causing loads and stores provides more information than just the pointer being loaded or stored

---
Diffs of the changes:  (+3 -4)

 AlphaISelPattern.cpp |    7 +++----
 1 files changed, 3 insertions(+), 4 deletions(-)


Index: llvm/lib/Target/Alpha/AlphaISelPattern.cpp
diff -u llvm/lib/Target/Alpha/AlphaISelPattern.cpp:1.141 llvm/lib/Target/Alpha/AlphaISelPattern.cpp:1.142
--- llvm/lib/Target/Alpha/AlphaISelPattern.cpp:1.141	Wed Jun 29 08:35:05 2005
+++ llvm/lib/Target/Alpha/AlphaISelPattern.cpp	Wed Jun 29 10:57:19 2005
@@ -607,16 +607,15 @@
 //Find the offset of the arg in it's parent's function
 static int getValueOffset(const Value* v)
 {
-  static int uniqneg = -1;
   if (v == NULL)
-    return uniqneg--;
+    return 0;
 
   const Instruction* itarget = dyn_cast<Instruction>(v);
   const BasicBlock* btarget = itarget->getParent();
   const Function* ftarget = btarget->getParent();
 
   //offset due to earlier BBs
-  int i = 0;
+  int i = 1;
   for(Function::const_iterator ii = ftarget->begin(); &*ii != btarget; ++ii)
     i += ii->size();
 
@@ -1299,7 +1298,7 @@
     has_sym = true;
 
     if (EnableAlphaLSMark)
-      BuildMI(BB, Alpha::MEMLABEL, 3).addImm(0).addImm(0).addImm(getUID());
+      BuildMI(BB, Alpha::MEMLABEL, 3).addImm(0).addImm(1).addImm(getUID());
 
     BuildMI(BB, Alpha::LDQl, 2, Result)
       .addGlobalAddress(cast<GlobalAddressSDNode>(N)->getGlobal())





From criswell at cs.uiuc.edu  Wed Jun 29 10:58:07 2005
From: criswell at cs.uiuc.edu (John Criswell)
Date: Wed, 29 Jun 2005 10:58:07 -0500
Subject: [llvm-commits] CVS: llvm/lib/Transforms/IPO/SimplifyLibCalls.cpp 
Message-ID: <200506291558.KAA02058@choi.cs.uiuc.edu>



Changes in directory llvm/lib/Transforms/IPO:

SimplifyLibCalls.cpp updated: 1.44 -> 1.45
---
Log message:

Doh!  Forgot to LLVMify the style.


---
Diffs of the changes:  (+0 -2)

 SimplifyLibCalls.cpp |    2 --
 1 files changed, 2 deletions(-)


Index: llvm/lib/Transforms/IPO/SimplifyLibCalls.cpp
diff -u llvm/lib/Transforms/IPO/SimplifyLibCalls.cpp:1.44 llvm/lib/Transforms/IPO/SimplifyLibCalls.cpp:1.45
--- llvm/lib/Transforms/IPO/SimplifyLibCalls.cpp:1.44	Wed Jun 29 10:03:18 2005
+++ llvm/lib/Transforms/IPO/SimplifyLibCalls.cpp	Wed Jun 29 10:57:50 2005
@@ -1310,9 +1310,7 @@
       // same type of char pointer.
       if (ci->getOperand(2)->getType() !=
           fwrite_func->getFunctionType()->getParamType(0))
-      {
         return false;
-      }
 
       std::vector<Value*> args;
       args.push_back(ci->getOperand(2));





From criswell at cs.uiuc.edu  Wed Jun 29 11:22:43 2005
From: criswell at cs.uiuc.edu (John Criswell)
Date: Wed, 29 Jun 2005 11:22:43 -0500
Subject: [llvm-commits] CVS: llvm-www/releases/1.5/docs/ReleaseNotes.html 
Message-ID: <200506291622.LAA05092@choi.cs.uiuc.edu>



Changes in directory llvm-www/releases/1.5/docs:

ReleaseNotes.html updated: 1.2 -> 1.3
---
Log message:

Bug found.


---
Diffs of the changes:  (+2 -1)

 ReleaseNotes.html |    3 ++-
 1 files changed, 2 insertions(+), 1 deletion(-)


Index: llvm-www/releases/1.5/docs/ReleaseNotes.html
diff -u llvm-www/releases/1.5/docs/ReleaseNotes.html:1.2 llvm-www/releases/1.5/docs/ReleaseNotes.html:1.3
--- llvm-www/releases/1.5/docs/ReleaseNotes.html:1.2	Wed May 18 11:04:43 2005
+++ llvm-www/releases/1.5/docs/ReleaseNotes.html	Wed Jun 29 11:22:25 2005
@@ -430,6 +430,7 @@
     mark values live across a setjmp as volatile</a>. This missing feature 
   only affects targets whose setjmp/longjmp libraries do not save and restore 
   the entire register file.</li>
+  <li><a href="http://llvm.cs.uiuc.edu/PR591">The simplify-libcalls pass generates ill-formed LLVM code</a>.</li>
 </ul>
 </div>
 
@@ -826,7 +827,7 @@
   src="http://www.w3.org/Icons/valid-html401" alt="Valid HTML 4.01!" /></a>
 
   <a href="http://llvm.cs.uiuc.edu">The LLVM Compiler Infrastructure</a><br>
-  Last modified: $Date: 2005/05/18 16:04:43 $
+  Last modified: $Date: 2005/06/29 16:22:25 $
 </address>
 
 </body>





From criswell at cs.uiuc.edu  Wed Jun 29 11:22:51 2005
From: criswell at cs.uiuc.edu (John Criswell)
Date: Wed, 29 Jun 2005 11:22:51 -0500
Subject: [llvm-commits] CVS: llvm/docs/ReleaseNotes.html 
Message-ID: <200506291622.LAA05154@choi.cs.uiuc.edu>



Changes in directory llvm/docs:

ReleaseNotes.html updated: 1.331 -> 1.332
---
Log message:

Bug fixed.


---
Diffs of the changes:  (+7 -1)

 ReleaseNotes.html |    8 +++++++-
 1 files changed, 7 insertions(+), 1 deletion(-)


Index: llvm/docs/ReleaseNotes.html
diff -u llvm/docs/ReleaseNotes.html:1.331 llvm/docs/ReleaseNotes.html:1.332
--- llvm/docs/ReleaseNotes.html:1.331	Wed May 18 17:23:56 2005
+++ llvm/docs/ReleaseNotes.html	Wed Jun 29 11:22:34 2005
@@ -94,6 +94,12 @@
 <a name="bugfix">Significant Bugs Fixed in LLVM 1.6</a>
 </div>
 
+<div class="doc_text">
+<ol>
+  <li><a href="http://llvm.cs.uiuc.edu/PR591">[simplify-libcalls] The simplify-libcalls pass generates ill-formed LLVM code</a>.</li>
+</ol>
+</div>
+
 <!-- *********************************************************************** -->
 <div class="doc_section">
   <a name="portability">Portability and Supported Platforms</a>
@@ -578,7 +584,7 @@
   src="http://www.w3.org/Icons/valid-html401" alt="Valid HTML 4.01!" /></a>
 
   <a href="http://llvm.cs.uiuc.edu">The LLVM Compiler Infrastructure</a><br>
-  Last modified: $Date: 2005/05/18 22:23:56 $
+  Last modified: $Date: 2005/06/29 16:22:34 $
 </address>
 
 </body>





From lattner at cs.uiuc.edu  Wed Jun 29 12:41:36 2005
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Wed, 29 Jun 2005 12:41:36 -0500
Subject: [llvm-commits] CVS: llvm/include/llvm/Analysis/LoopInfo.h 
Message-ID: <200506291741.MAA04929@zion.cs.uiuc.edu>



Changes in directory llvm/include/llvm/Analysis:

LoopInfo.h updated: 1.48 -> 1.49
---
Log message:

Don't crash on a query where the block is not in any loop.  Thanks to
Sameer D. Sahasrabuddhe for pointing this out!



---
Diffs of the changes:  (+2 -1)

 LoopInfo.h |    3 ++-
 1 files changed, 2 insertions(+), 1 deletion(-)


Index: llvm/include/llvm/Analysis/LoopInfo.h
diff -u llvm/include/llvm/Analysis/LoopInfo.h:1.48 llvm/include/llvm/Analysis/LoopInfo.h:1.49
--- llvm/include/llvm/Analysis/LoopInfo.h:1.48	Sun May 15 12:23:19 2005
+++ llvm/include/llvm/Analysis/LoopInfo.h	Wed Jun 29 12:41:25 2005
@@ -250,7 +250,8 @@
 
   // isLoopHeader - True if the block is a loop header node
   bool isLoopHeader(BasicBlock *BB) const {
-    return getLoopFor(BB)->getHeader() == BB;
+    const Loop *L = getLoopFor(BB);
+    return L && L->getHeader() == BB;
   }
 
   /// runOnFunction - Calculate the natural loop information.





From alenhar2 at cs.uiuc.edu  Wed Jun 29 13:54:13 2005
From: alenhar2 at cs.uiuc.edu (Andrew Lenharth)
Date: Wed, 29 Jun 2005 13:54:13 -0500
Subject: [llvm-commits] CVS: llvm/lib/Target/Alpha/AlphaISelPattern.cpp
	AlphaInstrInfo.td 
Message-ID: <200506291854.NAA07368@zion.cs.uiuc.edu>



Changes in directory llvm/lib/Target/Alpha:

AlphaISelPattern.cpp updated: 1.142 -> 1.143
AlphaInstrInfo.td updated: 1.50 -> 1.51
---
Log message:

restore old srcValueNode behavior and try to to work around it

---
Diffs of the changes:  (+72 -53)

 AlphaISelPattern.cpp |  122 +++++++++++++++++++++++++++++----------------------
 AlphaInstrInfo.td    |    3 -
 2 files changed, 72 insertions(+), 53 deletions(-)


Index: llvm/lib/Target/Alpha/AlphaISelPattern.cpp
diff -u llvm/lib/Target/Alpha/AlphaISelPattern.cpp:1.142 llvm/lib/Target/Alpha/AlphaISelPattern.cpp:1.143
--- llvm/lib/Target/Alpha/AlphaISelPattern.cpp:1.142	Wed Jun 29 10:57:19 2005
+++ llvm/lib/Target/Alpha/AlphaISelPattern.cpp	Wed Jun 29 13:54:02 2005
@@ -604,37 +604,48 @@
   }
 }
 
-//Find the offset of the arg in it's parent's function
-static int getValueOffset(const Value* v)
+static void getValueInfo(const Value* v, int& type, int& fun, int& offset)
 {
-  if (v == NULL)
-    return 0;
-
-  const Instruction* itarget = dyn_cast<Instruction>(v);
-  const BasicBlock* btarget = itarget->getParent();
-  const Function* ftarget = btarget->getParent();
-
-  //offset due to earlier BBs
-  int i = 1;
-  for(Function::const_iterator ii = ftarget->begin(); &*ii != btarget; ++ii)
-    i += ii->size();
-
-  for(BasicBlock::const_iterator ii = btarget->begin(); &*ii != itarget; ++ii)
-    ++i;
-
-  return i;
-}
-//Find the offset of the function in it's module
-static int getFunctionOffset(const Function* fun)
-{
-  const Module* M = fun->getParent();
-
-  //offset due to earlier BBs
-  int i = 0;
-  for(Module::const_iterator ii = M->begin(); &*ii != fun; ++ii)
-    ++i;
-
-  return i;
+  if (v == NULL) {
+    type = 0;
+    fun = 0;
+    offset = 0;
+  } else if (const GlobalValue* GV = dyn_cast<GlobalValue>(v)) {
+    type = 1;
+    fun = 1;
+    const Module* M = GV->getParent();
+      int i = 0;
+      for(Module::const_global_iterator ii = M->global_begin(); &*ii != GV; ++ii)
+        ++i;
+      offset = i;
+  } else if (const Argument* Arg = dyn_cast<Argument>(v)) {
+    type = 2;
+    const Function* F = Arg->getParent();
+    const Module* M = F->getParent();
+    int i = 0;
+    for(Module::const_iterator ii = M->begin(); &*ii != F; ++ii)
+      ++i;
+    fun = i;
+    i = 0;
+    for(Function::const_arg_iterator ii = F->arg_begin(); &*ii != Arg; ++ii)
+      ++i;
+    offset = i;
+  } else if (const Instruction* I = dyn_cast<Instruction>(v)) {
+    type = 3;
+    const BasicBlock* bb = I->getParent();
+    const Function* F = bb->getParent();
+    const Module* M = F->getParent();
+    int i = 0;
+    for(Module::const_iterator ii = M->begin(); &*ii != F; ++ii)
+      ++i;
+    fun = i;
+    i = 0;
+    for(Function::const_iterator ii = F->begin(); &*ii != bb; ++ii)
+      i += ii->size();
+    for(BasicBlock::const_iterator ii = bb->begin(); &*ii != I; ++ii)
+      ++i;
+    offset = i;
+  }
 }
 
 static int getUID()
@@ -1244,18 +1255,18 @@
           assert(opcode != ISD::SEXTLOAD && "Not zext"); break;
         }
 
-      int i = 0, j = 0;
-      if (EnableAlphaLSMark) {
-        i = getValueOffset(dyn_cast<SrcValueSDNode>(N.getOperand(2))
-                           ->getValue());
-        j = getFunctionOffset(BB->getParent()->getFunction());
-      }
+      int i, j, k;
+      if (EnableAlphaLSMark)
+        getValueInfo(dyn_cast<SrcValueSDNode>(N.getOperand(2))->getValue(),
+                     i, j, k);
+
       if (GlobalAddressSDNode *GASD = 
           dyn_cast<GlobalAddressSDNode>(Address)) {
         if (GASD->getGlobal()->isExternal()) {
           Tmp1 = SelectExpr(Address);
           if (EnableAlphaLSMark)
-            BuildMI(BB, Alpha::MEMLABEL, 3).addImm(j).addImm(i).addImm(getUID());
+            BuildMI(BB, Alpha::MEMLABEL, 4).addImm(i).addImm(j).addImm(k)
+              .addImm(getUID());
           BuildMI(BB, Opc, 2, Result).addImm(0).addReg(Tmp1);
         } else {
           Tmp1 = MakeReg(MVT::i64);
@@ -1263,7 +1274,8 @@
           BuildMI(BB, Alpha::LDAHr, 2, Tmp1)
             .addGlobalAddress(GASD->getGlobal()).addReg(Alpha::R29);
           if (EnableAlphaLSMark)
-            BuildMI(BB, Alpha::MEMLABEL, 3).addImm(j).addImm(i).addImm(getUID());
+            BuildMI(BB, Alpha::MEMLABEL, 4).addImm(i).addImm(j).addImm(k)
+              .addImm(getUID());
           BuildMI(BB, GetRelVersion(Opc), 2, Result)
             .addGlobalAddress(GASD->getGlobal()).addReg(Tmp1);
         }
@@ -1274,12 +1286,14 @@
         BuildMI(BB, Alpha::LDAHr, 2, Tmp1).addConstantPoolIndex(CP->getIndex())
           .addReg(Alpha::R29);
         if (EnableAlphaLSMark)
-          BuildMI(BB, Alpha::MEMLABEL, 3).addImm(j).addImm(i).addImm(getUID());
+          BuildMI(BB, Alpha::MEMLABEL, 4).addImm(i).addImm(j).addImm(k)
+            .addImm(getUID());
         BuildMI(BB, GetRelVersion(Opc), 2, Result)
           .addConstantPoolIndex(CP->getIndex()).addReg(Tmp1);
       } else if(Address.getOpcode() == ISD::FrameIndex) {
         if (EnableAlphaLSMark)
-          BuildMI(BB, Alpha::MEMLABEL, 3).addImm(j).addImm(i).addImm(getUID());
+          BuildMI(BB, Alpha::MEMLABEL, 4).addImm(i).addImm(j).addImm(k)
+            .addImm(getUID());
         BuildMI(BB, Opc, 2, Result)
           .addFrameIndex(cast<FrameIndexSDNode>(Address)->getIndex())
           .addReg(Alpha::F31);
@@ -1287,7 +1301,8 @@
         long offset;
         SelectAddr(Address, Tmp1, offset);
         if (EnableAlphaLSMark)
-          BuildMI(BB, Alpha::MEMLABEL, 3).addImm(j).addImm(i).addImm(getUID());
+          BuildMI(BB, Alpha::MEMLABEL, 4).addImm(i).addImm(j).addImm(k)
+            .addImm(getUID());
         BuildMI(BB, Opc, 2, Result).addImm(offset).addReg(Tmp1);
       }
       return Result;
@@ -1298,7 +1313,8 @@
     has_sym = true;
 
     if (EnableAlphaLSMark)
-      BuildMI(BB, Alpha::MEMLABEL, 3).addImm(0).addImm(1).addImm(getUID());
+      BuildMI(BB, Alpha::MEMLABEL, 4).addImm(0).addImm(0).addImm(0)
+        .addImm(getUID());
 
     BuildMI(BB, Alpha::LDQl, 2, Result)
       .addGlobalAddress(cast<GlobalAddressSDNode>(N)->getGlobal())
@@ -2268,19 +2284,18 @@
         }
       }
 
-      int i = 0, j = 0;
-      if (EnableAlphaLSMark) {
-        i = 
-          getValueOffset(dyn_cast<SrcValueSDNode>(N.getOperand(3))->getValue());
-        j = getFunctionOffset(BB->getParent()->getFunction());
-      }
+      int i, j, k;
+      if (EnableAlphaLSMark) 
+        getValueInfo(dyn_cast<SrcValueSDNode>(N.getOperand(3))->getValue(), 
+                     i, j, k);
 
       if (GlobalAddressSDNode *GASD = 
           dyn_cast<GlobalAddressSDNode>(Address)) {
         if (GASD->getGlobal()->isExternal()) {
           Tmp2 = SelectExpr(Address);
           if (EnableAlphaLSMark)
-            BuildMI(BB, Alpha::MEMLABEL, 3).addImm(j).addImm(i).addImm(getUID());
+            BuildMI(BB, Alpha::MEMLABEL, 4).addImm(i).addImm(j).addImm(k)
+              .addImm(getUID());
           BuildMI(BB, Opc, 3).addReg(Tmp1).addImm(0).addReg(Tmp2);
         } else {
           Tmp2 = MakeReg(MVT::i64);
@@ -2288,13 +2303,15 @@
           BuildMI(BB, Alpha::LDAHr, 2, Tmp2)
             .addGlobalAddress(GASD->getGlobal()).addReg(Alpha::R29);
           if (EnableAlphaLSMark)
-            BuildMI(BB, Alpha::MEMLABEL, 3).addImm(j).addImm(i).addImm(getUID());
+            BuildMI(BB, Alpha::MEMLABEL, 4).addImm(i).addImm(j).addImm(k)
+              .addImm(getUID());
           BuildMI(BB, GetRelVersion(Opc), 3).addReg(Tmp1)
             .addGlobalAddress(GASD->getGlobal()).addReg(Tmp2);
         }
       } else if(Address.getOpcode() == ISD::FrameIndex) {
         if (EnableAlphaLSMark)
-          BuildMI(BB, Alpha::MEMLABEL, 3).addImm(j).addImm(i).addImm(getUID());
+          BuildMI(BB, Alpha::MEMLABEL, 4).addImm(i).addImm(j).addImm(k)
+            .addImm(getUID());
         BuildMI(BB, Opc, 3).addReg(Tmp1)
           .addFrameIndex(cast<FrameIndexSDNode>(Address)->getIndex())
           .addReg(Alpha::F31);
@@ -2302,7 +2319,8 @@
         long offset;
         SelectAddr(Address, Tmp2, offset);
         if (EnableAlphaLSMark)
-          BuildMI(BB, Alpha::MEMLABEL, 3).addImm(j).addImm(i).addImm(getUID());
+          BuildMI(BB, Alpha::MEMLABEL, 4).addImm(i).addImm(j).addImm(k)
+            .addImm(getUID());
         BuildMI(BB, Opc, 3).addReg(Tmp1).addImm(offset).addReg(Tmp2);
       }
       return;


Index: llvm/lib/Target/Alpha/AlphaInstrInfo.td
diff -u llvm/lib/Target/Alpha/AlphaInstrInfo.td:1.50 llvm/lib/Target/Alpha/AlphaInstrInfo.td:1.51
--- llvm/lib/Target/Alpha/AlphaInstrInfo.td:1.50	Tue Jun 28 19:39:17 2005
+++ llvm/lib/Target/Alpha/AlphaInstrInfo.td	Wed Jun 29 13:54:02 2005
@@ -31,7 +31,8 @@
 def ADJUSTSTACKDOWN : PseudoInstAlpha<(ops ), "ADJDOWN">;
 def ALTENT : PseudoInstAlpha<(ops s64imm:$TARGET), "$TARGET:\n">;
 def PCLABEL : PseudoInstAlpha<(ops s64imm:$num), "PCMARKER_$num:\n">;
-def MEMLABEL : PseudoInstAlpha<(ops s64imm:$i, s64imm:$j, s64imm:$k), "LSMARKER$$$i$$$j$$$k:\n">;
+def MEMLABEL : PseudoInstAlpha<(ops s64imm:$i, s64imm:$j, s64imm:$k, s64imm:$m),
+         "LSMARKER$$$i$$$j$$$k$$$m:\n">;
 
 //*****************
 //These are shortcuts, the assembler expands them





From alenhar2 at cs.uiuc.edu  Wed Jun 29 13:54:14 2005
From: alenhar2 at cs.uiuc.edu (Andrew Lenharth)
Date: Wed, 29 Jun 2005 13:54:14 -0500
Subject: [llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
	SelectionDAGISel.cpp 
Message-ID: <200506291854.NAA07374@zion.cs.uiuc.edu>



Changes in directory llvm/lib/CodeGen/SelectionDAG:

SelectionDAG.cpp updated: 1.121 -> 1.122
SelectionDAGISel.cpp updated: 1.63 -> 1.64
---
Log message:

restore old srcValueNode behavior and try to to work around it

---
Diffs of the changes:  (+4 -2)

 SelectionDAG.cpp     |    2 ++
 SelectionDAGISel.cpp |    4 ++--
 2 files changed, 4 insertions(+), 2 deletions(-)


Index: llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp:1.121 llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp:1.122
--- llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp:1.121	Wed Jun 29 10:57:19 2005
+++ llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp	Wed Jun 29 13:54:02 2005
@@ -1394,6 +1394,8 @@
 }
 
 SDOperand SelectionDAG::getSrcValue(const Value *V, int Offset) {
+  assert((!V || isa<PointerType>(V->getType())) &&
+         "SrcValue is not a pointer?");
   SDNode *&N = ValueNodes[std::make_pair(V, Offset)];
   if (N) return SDOperand(N, 0);
 


Index: llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.63 llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.64
--- llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.63	Wed Jun 29 10:57:19 2005
+++ llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp	Wed Jun 29 13:54:02 2005
@@ -644,7 +644,7 @@
   }
 
   SDOperand L = DAG.getLoad(TLI.getValueType(I.getType()), Root, Ptr,
-                            DAG.getSrcValue(&I));
+                            DAG.getSrcValue(I.getOperand(0)));
   setValue(&I, L);
 
   if (I.isVolatile())
@@ -659,7 +659,7 @@
   SDOperand Src = getValue(SrcV);
   SDOperand Ptr = getValue(I.getOperand(1));
   DAG.setRoot(DAG.getNode(ISD::STORE, MVT::Other, getRoot(), Src, Ptr,
-                          DAG.getSrcValue(&I)));
+                          DAG.getSrcValue(I.getOperand(1))));
 }
 
 void SelectionDAGLowering::visitCall(CallInst &I) {





From natebegeman at mac.com  Wed Jun 29 19:53:32 2005
From: natebegeman at mac.com (Nate Begeman)
Date: Wed, 29 Jun 2005 19:53:32 -0500
Subject: [llvm-commits] CVS: llvm/lib/Target/X86/X86AsmPrinter.cpp 
Message-ID: <200506300053.TAA09298@zion.cs.uiuc.edu>



Changes in directory llvm/lib/Target/X86:

X86AsmPrinter.cpp updated: 1.137 -> 1.138
---
Log message:

Make the x86 asm printer darwin-aware.  This mostly entails doing the same
thing as cygwin most of the time, and printing our alignments in log2
rather than number of bytes.


---
Diffs of the changes:  (+15 -12)

 X86AsmPrinter.cpp |   27 +++++++++++++++------------
 1 files changed, 15 insertions(+), 12 deletions(-)


Index: llvm/lib/Target/X86/X86AsmPrinter.cpp
diff -u llvm/lib/Target/X86/X86AsmPrinter.cpp:1.137 llvm/lib/Target/X86/X86AsmPrinter.cpp:1.138
--- llvm/lib/Target/X86/X86AsmPrinter.cpp:1.137	Mon Jun 20 14:59:22 2005
+++ llvm/lib/Target/X86/X86AsmPrinter.cpp	Wed Jun 29 19:53:20 2005
@@ -44,12 +44,13 @@
 
   struct X86SharedAsmPrinter : public AsmPrinter {
     X86SharedAsmPrinter(std::ostream &O, TargetMachine &TM)
-      : AsmPrinter(O, TM), forCygwin(false) { }
+      : AsmPrinter(O, TM), forCygwin(false), forDarwin(false) { }
 
     bool doInitialization(Module &M);
     void printConstantPool(MachineConstantPool *MCP);
     bool doFinalization(Module &M);
     bool forCygwin;
+    bool forDarwin;
   };
 }
 
@@ -82,20 +83,22 @@
 
 /// doInitialization - determine
 bool X86SharedAsmPrinter::doInitialization(Module& M) {
-  forCygwin = false;
   const std::string& TT = M.getTargetTriple();
-  if (TT.length() > 5)
+  if (TT.length() > 5) {
     forCygwin = TT.find("cygwin") != std::string::npos ||
                 TT.find("mingw")  != std::string::npos;
-  else if (TT.empty()) {
+    forDarwin = TT.find("darwin") != std::string::npos;
+  } else if (TT.empty()) {
 #if defined(__CYGWIN__) || defined(__MINGW32__)
     forCygwin = true;
-#else
-    forCygwin = false;
+#elif defined(__MACOSX__)
+    forDarwin = true;
 #endif
   }
-  if (forCygwin)
+  if (forCygwin || forDarwin)
     GlobalPrefix = "_";
+  if (forDarwin)
+    AlignmentIsInBytes = false;
   return AsmPrinter::doInitialization(M);
 }
 
@@ -173,7 +176,7 @@
         }
 
         emitAlignment(Align);
-        if (!forCygwin) {
+        if (!forCygwin && !forDarwin) {
           O << "\t.type " << name << ", at object\n";
           O << "\t.size " << name << "," << Size << "\n";
         }
@@ -264,7 +267,7 @@
   O << "\t.text\n";
   emitAlignment(4);
   O << "\t.globl\t" << CurrentFnName << "\n";
-  if (!forCygwin)
+  if (!forCygwin && !forDarwin)
     O << "\t.type\t" << CurrentFnName << ", @function\n";
   O << CurrentFnName << ":\n";
 
@@ -312,7 +315,7 @@
   case MachineOperand::MO_MachineBasicBlock: {
     MachineBasicBlock *MBBOp = MO.getMachineBasicBlock();
     O << ".LBB" << Mang->getValueName(MBBOp->getParent()->getFunction())
-      << "_" << MBBOp->getNumber () << "\t# "
+      << "_" << MBBOp->getNumber () << '\t' << CommentString
       << MBBOp->getBasicBlock ()->getName ();
     return;
   }
@@ -488,7 +491,7 @@
   O << "\t.text\n";
   emitAlignment(4);
   O << "\t.globl\t" << CurrentFnName << "\n";
-  if (!forCygwin)
+  if (!forCygwin && !forDarwin)
     O << "\t.type\t" << CurrentFnName << ", @function\n";
   O << CurrentFnName << ":\n";
 
@@ -530,7 +533,7 @@
   case MachineOperand::MO_MachineBasicBlock: {
     MachineBasicBlock *MBBOp = MO.getMachineBasicBlock();
     O << ".LBB" << Mang->getValueName(MBBOp->getParent()->getFunction())
-      << "_" << MBBOp->getNumber () << "\t# "
+      << "_" << MBBOp->getNumber () << '\t' << CommentString
       << MBBOp->getBasicBlock ()->getName ();
     return;
   }





From lattner at cs.uiuc.edu  Thu Jun 30 02:29:07 2005
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Thu, 30 Jun 2005 02:29:07 -0500
Subject: [llvm-commits] 
	CVS: llvm/test/Regression/Transforms/Mem2Reg/2005-06-30-ReadBeforeWrite.ll
Message-ID: <200506300729.CAA15648@zion.cs.uiuc.edu>



Changes in directory llvm/test/Regression/Transforms/Mem2Reg:

2005-06-30-ReadBeforeWrite.ll added (r1.1)
---
Log message:

new testcase for PR590: http://llvm.cs.uiuc.edu/PR590 


---
Diffs of the changes:  (+51 -0)

 2005-06-30-ReadBeforeWrite.ll |   51 ++++++++++++++++++++++++++++++++++++++++++
 1 files changed, 51 insertions(+)


Index: llvm/test/Regression/Transforms/Mem2Reg/2005-06-30-ReadBeforeWrite.ll
diff -c /dev/null llvm/test/Regression/Transforms/Mem2Reg/2005-06-30-ReadBeforeWrite.ll:1.1
*** /dev/null	Thu Jun 30 02:29:04 2005
--- llvm/test/Regression/Transforms/Mem2Reg/2005-06-30-ReadBeforeWrite.ll	Thu Jun 30 02:28:54 2005
***************
*** 0 ****
--- 1,51 ----
+ ; RUN: llvm-as < %s | opt -mem2reg -instcombine | llvm-dis | grep store
+ ; PR590
+ 
+ void %zero(sbyte* %p, int %n) {
+ entry:
+ 	%p_addr = alloca sbyte*		; <sbyte**> [#uses=2]
+ 	%n_addr = alloca int		; <int*> [#uses=2]
+ 	%i = alloca int		; <int*> [#uses=6]
+ 	%out = alloca int		; <int*> [#uses=2]
+ 	%undef = alloca int		; <int*> [#uses=2]
+ 	store sbyte* %p, sbyte** %p_addr
+ 	store int %n, int* %n_addr
+ 	store int 0, int* %i
+ 	br label %loopentry
+ 
+ loopentry:		; preds = %endif, %entry
+ 	%tmp.0 = load int* %n_addr		; <int> [#uses=1]
+ 	%tmp.1 = add int %tmp.0, 1		; <int> [#uses=1]
+ 	%tmp.2 = load int* %i		; <int> [#uses=1]
+ 	%tmp.3 = setgt int %tmp.1, %tmp.2		; <bool> [#uses=2]
+ 	%tmp.4 = cast bool %tmp.3 to int		; <int> [#uses=0]
+ 	br bool %tmp.3, label %no_exit, label %return
+ 
+ no_exit:		; preds = %loopentry
+ 	%tmp.5 = load int* %undef		; <int> [#uses=1]
+ 	store int %tmp.5, int* %out
+ 	store int 0, int* %undef
+ 	%tmp.6 = load int* %i		; <int> [#uses=1]
+ 	%tmp.7 = setgt int %tmp.6, 0		; <bool> [#uses=2]
+ 	%tmp.8 = cast bool %tmp.7 to int		; <int> [#uses=0]
+ 	br bool %tmp.7, label %then, label %endif
+ 
+ then:		; preds = %no_exit
+ 	%tmp.9 = load sbyte** %p_addr		; <sbyte*> [#uses=1]
+ 	%tmp.10 = load int* %i		; <int> [#uses=1]
+ 	%tmp.11 = sub int %tmp.10, 1		; <int> [#uses=1]
+ 	%tmp.12 = getelementptr sbyte* %tmp.9, int %tmp.11		; <sbyte*> [#uses=1]
+ 	%tmp.13 = load int* %out		; <int> [#uses=1]
+ 	%tmp.14 = cast int %tmp.13 to sbyte		; <sbyte> [#uses=1]
+ 	store sbyte %tmp.14, sbyte* %tmp.12
+ 	br label %endif
+ 
+ endif:		; preds = %then, %no_exit
+ 	%tmp.15 = load int* %i		; <int> [#uses=1]
+ 	%inc = add int %tmp.15, 1		; <int> [#uses=1]
+ 	store int %inc, int* %i
+ 	br label %loopentry
+ 
+ return:		; preds = %loopentry
+ 	ret void
+ }





From lattner at cs.uiuc.edu  Thu Jun 30 02:29:55 2005
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Thu, 30 Jun 2005 02:29:55 -0500
Subject: [llvm-commits] 
	CVS: llvm/lib/Transforms/Utils/PromoteMemoryToRegister.cpp
Message-ID: <200506300729.CAA15673@zion.cs.uiuc.edu>



Changes in directory llvm/lib/Transforms/Utils:

PromoteMemoryToRegister.cpp updated: 1.76 -> 1.77
---
Log message:

Fix PR590: http://llvm.cs.uiuc.edu/PR590  and Transforms/Mem2Reg/2005-06-30-ReadBeforeWrite.ll.

The optimization for locally used allocas was not safe for allocas that
were read before they were written.  This change disables that optimization
in that case.



---
Diffs of the changes:  (+65 -19)

 PromoteMemoryToRegister.cpp |   84 ++++++++++++++++++++++++++++++++++----------
 1 files changed, 65 insertions(+), 19 deletions(-)


Index: llvm/lib/Transforms/Utils/PromoteMemoryToRegister.cpp
diff -u llvm/lib/Transforms/Utils/PromoteMemoryToRegister.cpp:1.76 llvm/lib/Transforms/Utils/PromoteMemoryToRegister.cpp:1.77
--- llvm/lib/Transforms/Utils/PromoteMemoryToRegister.cpp:1.76	Thu Apr 21 18:45:34 2005
+++ llvm/lib/Transforms/Utils/PromoteMemoryToRegister.cpp	Thu Jun 30 02:29:44 2005
@@ -57,6 +57,7 @@
     /// Allocas - The alloca instructions being promoted.
     ///
     std::vector<AllocaInst*> Allocas;
+    std::vector<AllocaInst*> &RetryList;
     DominatorTree &DT;
     DominanceFrontier &DF;
     const TargetData &TD;
@@ -88,10 +89,11 @@
     StableBasicBlockNumbering BBNumbers;
 
   public:
-    PromoteMem2Reg(const std::vector<AllocaInst*> &A, DominatorTree &dt,
+    PromoteMem2Reg(const std::vector<AllocaInst*> &A,
+                   std::vector<AllocaInst*> &Retry, DominatorTree &dt,
                    DominanceFrontier &df, const TargetData &td,
                    AliasSetTracker *ast)
-      : Allocas(A), DT(dt), DF(df), TD(td), AST(ast) {}
+      : Allocas(A), RetryList(Retry), DT(dt), DF(df), TD(td), AST(ast) {}
 
     void run();
 
@@ -106,7 +108,7 @@
   private:
     void MarkDominatingPHILive(BasicBlock *BB, unsigned AllocaNum,
                                std::set<PHINode*> &DeadPHINodes);
-    void PromoteLocallyUsedAlloca(BasicBlock *BB, AllocaInst *AI);
+    bool PromoteLocallyUsedAlloca(BasicBlock *BB, AllocaInst *AI);
     void PromoteLocallyUsedAllocas(BasicBlock *BB,
                                    const std::vector<AllocaInst*> &AIs);
 
@@ -277,15 +279,21 @@
   // Process all allocas which are only used in a single basic block.
   for (std::map<BasicBlock*, std::vector<AllocaInst*> >::iterator I =
          LocallyUsedAllocas.begin(), E = LocallyUsedAllocas.end(); I != E; ++I){
-    const std::vector<AllocaInst*> &Allocas = I->second;
-    assert(!Allocas.empty() && "empty alloca list??");
+    const std::vector<AllocaInst*> &LocAllocas = I->second;
+    assert(!LocAllocas.empty() && "empty alloca list??");
 
     // It's common for there to only be one alloca in the list.  Handle it
     // efficiently.
-    if (Allocas.size() == 1)
-      PromoteLocallyUsedAlloca(I->first, Allocas[0]);
-    else
-      PromoteLocallyUsedAllocas(I->first, Allocas);
+    if (LocAllocas.size() == 1) {
+      // If we can do the quick promotion pass, do so now.
+      if (PromoteLocallyUsedAlloca(I->first, LocAllocas[0]))
+        RetryList.push_back(LocAllocas[0]);  // Failed, retry later.
+    } else {
+      // Locally promote anything possible.  Note that if this is unable to
+      // promote a particular alloca, it puts the alloca onto the Allocas vector
+      // for global processing.
+      PromoteLocallyUsedAllocas(I->first, LocAllocas);
+    }
   }
 
   if (Allocas.empty())
@@ -430,7 +438,16 @@
 /// potentially useless PHI nodes by just performing a single linear pass over
 /// the basic block using the Alloca.
 ///
-void PromoteMem2Reg::PromoteLocallyUsedAlloca(BasicBlock *BB, AllocaInst *AI) {
+/// If we cannot promote this alloca (because it is read before it is written),
+/// return true.  This is necessary in cases where, due to control flow, the
+/// alloca is potentially undefined on some control flow paths.  e.g. code like
+/// this is potentially correct:
+///
+///   for (...) { if (c) { A = undef; undef = B; } }
+///
+/// ... so long as A is not used before undef is set.
+///
+bool PromoteMem2Reg::PromoteLocallyUsedAlloca(BasicBlock *BB, AllocaInst *AI) {
   assert(!AI->use_empty() && "There are no uses of the alloca!");
 
   // Handle degenerate cases quickly.
@@ -448,12 +465,14 @@
     BB->getInstList().erase(U);
   } else {
     // Uses of the uninitialized memory location shall get undef.
-    Value *CurVal = UndefValue::get(AI->getAllocatedType());
+    Value *CurVal = 0;
 
     for (BasicBlock::iterator I = BB->begin(), E = BB->end(); I != E; ) {
       Instruction *Inst = I++;
       if (LoadInst *LI = dyn_cast<LoadInst>(Inst)) {
         if (LI->getOperand(0) == AI) {
+          if (!CurVal) return true;  // Could not locally promote!
+
           // Loads just returns the "current value"...
           LI->replaceAllUsesWith(CurVal);
           if (AST && isa<PointerType>(LI->getType()))
@@ -475,6 +494,7 @@
   assert(AI->use_empty() && "Uses of alloca from more than one BB??");
   if (AST) AST->deleteValue(AI);
   AI->getParent()->getInstList().erase(AI);
+  return false;
 }
 
 /// PromoteLocallyUsedAllocas - This method is just like
@@ -495,13 +515,19 @@
       if (AllocaInst *AI = dyn_cast<AllocaInst>(LI->getOperand(0))) {
         std::map<AllocaInst*, Value*>::iterator AIt = CurValues.find(AI);
         if (AIt != CurValues.end()) {
-          // Loads just returns the "current value"...
-          if (AIt->second == 0)   // Uninitialized value??
-            AIt->second = UndefValue::get(AIt->first->getAllocatedType());
-          LI->replaceAllUsesWith(AIt->second);
-          if (AST && isa<PointerType>(LI->getType()))
-            AST->deleteValue(LI);
-          BB->getInstList().erase(LI);
+          // If loading an uninitialized value, allow the inter-block case to
+          // handle it.  Due to control flow, this might actually be ok.
+          if (AIt->second == 0) {  // Use of locally uninitialized value??
+            RetryList.push_back(AI);   // Retry elsewhere.
+            CurValues.erase(AIt);   // Stop tracking this here.
+            if (CurValues.empty()) return;
+          } else {
+            // Loads just returns the "current value"...
+            LI->replaceAllUsesWith(AIt->second);
+            if (AST && isa<PointerType>(LI->getType()))
+              AST->deleteValue(LI);
+            BB->getInstList().erase(LI);
+          }
         }
       }
     } else if (StoreInst *SI = dyn_cast<StoreInst>(Inst)) {
@@ -627,5 +653,25 @@
                            const TargetData &TD, AliasSetTracker *AST) {
   // If there is nothing to do, bail out...
   if (Allocas.empty()) return;
-  PromoteMem2Reg(Allocas, DT, DF, TD, AST).run();
+
+  std::vector<AllocaInst*> RetryList;
+  PromoteMem2Reg(Allocas, RetryList, DT, DF, TD, AST).run();
+
+  // PromoteMem2Reg may not have been able to promote all of the allocas in one
+  // pass, run it again if needed.
+  while (!RetryList.empty()) {
+    // If we need to retry some allocas, this is due to there being no store
+    // before a read in a local block.  To counteract this, insert a store of
+    // undef into the alloca right after the alloca itself.
+    for (unsigned i = 0, e = RetryList.size(); i != e; ++i) {
+      BasicBlock::iterator BBI = RetryList[i];
+      
+      new StoreInst(UndefValue::get(RetryList[i]->getAllocatedType()),
+                    RetryList[i], ++BBI);
+    }
+
+    std::vector<AllocaInst*> NewAllocas;
+    std::swap(NewAllocas, RetryList);
+    PromoteMem2Reg(NewAllocas, RetryList, DT, DF, TD, AST).run();
+  }
 }





From alenhar2 at cs.uiuc.edu  Thu Jun 30 14:22:48 2005
From: alenhar2 at cs.uiuc.edu (Andrew Lenharth)
Date: Thu, 30 Jun 2005 14:22:48 -0500
Subject: [llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp 
Message-ID: <200506301922.OAA15770@zion.cs.uiuc.edu>



Changes in directory llvm/lib/CodeGen/SelectionDAG:

LegalizeDAG.cpp updated: 1.131 -> 1.132
---
Log message:

FP EXTLOAD is not support on all archs, expand to LOAD and FP_EXTEND

---
Diffs of the changes:  (+9 -0)

 LegalizeDAG.cpp |    9 +++++++++
 1 files changed, 9 insertions(+)


Index: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.131 llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.132
--- llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.131	Mon Jun 27 18:28:32 2005
+++ llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp	Thu Jun 30 14:22:37 2005
@@ -522,6 +522,15 @@
       AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1));
       return Result.getValue(Op.ResNo);
     case TargetLowering::Expand:
+      //f64 = EXTLOAD f32 should expand to LOAD, FP_EXTEND
+      if (SrcVT == MVT::f32 && Node->getValueType(0) == MVT::f64) {
+        SDOperand Load = DAG.getLoad(SrcVT, Tmp1, Tmp2, Node->getOperand(2));
+        Result = 
+          DAG.getNode(ISD::FP_EXTEND, Node->getValueType(0), Load, SrcVT);
+        if (Op.ResNo)
+          return Load.getValue(1);
+        return Result;
+      }
       assert(Node->getOpcode() != ISD::EXTLOAD &&
              "EXTLOAD should always be supported!");
       // Turn the unsupported load into an EXTLOAD followed by an explicit





From alenhar2 at cs.uiuc.edu  Thu Jun 30 14:33:09 2005
From: alenhar2 at cs.uiuc.edu (Andrew Lenharth)
Date: Thu, 30 Jun 2005 14:33:09 -0500
Subject: [llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp 
Message-ID: <200506301933.OAA15836@zion.cs.uiuc.edu>



Changes in directory llvm/lib/CodeGen/SelectionDAG:

LegalizeDAG.cpp updated: 1.132 -> 1.133
---
Log message:

oops

---
Diffs of the changes:  (+1 -2)

 LegalizeDAG.cpp |    3 +--
 1 files changed, 1 insertion(+), 2 deletions(-)


Index: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.132 llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.133
--- llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.132	Thu Jun 30 14:22:37 2005
+++ llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp	Thu Jun 30 14:32:57 2005
@@ -525,8 +525,7 @@
       //f64 = EXTLOAD f32 should expand to LOAD, FP_EXTEND
       if (SrcVT == MVT::f32 && Node->getValueType(0) == MVT::f64) {
         SDOperand Load = DAG.getLoad(SrcVT, Tmp1, Tmp2, Node->getOperand(2));
-        Result = 
-          DAG.getNode(ISD::FP_EXTEND, Node->getValueType(0), Load, SrcVT);
+        Result = DAG.getNode(ISD::FP_EXTEND, Node->getValueType(0), Load);
         if (Op.ResNo)
           return Load.getValue(1);
         return Result;





From lattner at cs.uiuc.edu  Fri Jul  1 01:41:09 2005
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Fri, 1 Jul 2005 01:41:09 -0500
Subject: [llvm-commits] 
	CVS: llvm/lib/Target/SparcV9/ModuloScheduling/ModuloSchedulingSuperBlock.cpp
Message-ID: <200507010641.BAA18648@zion.cs.uiuc.edu>



Changes in directory llvm/lib/Target/SparcV9/ModuloScheduling:

ModuloSchedulingSuperBlock.cpp updated: 1.2 -> 1.3
---
Log message:

remove some debugging code


---
Diffs of the changes:  (+0 -3)

 ModuloSchedulingSuperBlock.cpp |    3 ---
 1 files changed, 3 deletions(-)


Index: llvm/lib/Target/SparcV9/ModuloScheduling/ModuloSchedulingSuperBlock.cpp
diff -u llvm/lib/Target/SparcV9/ModuloScheduling/ModuloSchedulingSuperBlock.cpp:1.2 llvm/lib/Target/SparcV9/ModuloScheduling/ModuloSchedulingSuperBlock.cpp:1.3
--- llvm/lib/Target/SparcV9/ModuloScheduling/ModuloSchedulingSuperBlock.cpp:1.2	Thu Jun 16 23:00:57 2005
+++ llvm/lib/Target/SparcV9/ModuloScheduling/ModuloSchedulingSuperBlock.cpp	Fri Jul  1 01:40:58 2005
@@ -148,7 +148,6 @@
   };
 
   bool ModuloSchedulingSBPass::runOnFunction(Function &F) {
-    alarm(100);
     bool Changed = false;
     
     //Get MachineFunction
@@ -270,9 +269,7 @@
       defMap.clear();
       
     }
-    alarm(0);
     return Changed;
-    
   }
 
   void ModuloSchedulingSBPass::FindSuperBlocks(Function &F, LoopInfo &LI,





From alenhar2 at cs.uiuc.edu  Fri Jul  1 14:12:25 2005
From: alenhar2 at cs.uiuc.edu (Andrew Lenharth)
Date: Fri, 1 Jul 2005 14:12:25 -0500
Subject: [llvm-commits] CVS: llvm/lib/Target/Alpha/AlphaISelPattern.cpp
	AlphaInstrInfo.td AlphaRegisterInfo.cpp 
Message-ID: <200507011912.OAA26567@zion.cs.uiuc.edu>



Changes in directory llvm/lib/Target/Alpha:

AlphaISelPattern.cpp updated: 1.143 -> 1.144
AlphaInstrInfo.td updated: 1.51 -> 1.52
AlphaRegisterInfo.cpp updated: 1.22 -> 1.23
---
Log message:

simplify call code, remove pseudo ops for div and rem, track more loads and stores

---
Diffs of the changes:  (+92 -80)

 AlphaISelPattern.cpp  |  144 +++++++++++++++++++++++++-------------------------
 AlphaInstrInfo.td     |   12 +---
 AlphaRegisterInfo.cpp |   16 +++++
 3 files changed, 92 insertions(+), 80 deletions(-)


Index: llvm/lib/Target/Alpha/AlphaISelPattern.cpp
diff -u llvm/lib/Target/Alpha/AlphaISelPattern.cpp:1.143 llvm/lib/Target/Alpha/AlphaISelPattern.cpp:1.144
--- llvm/lib/Target/Alpha/AlphaISelPattern.cpp:1.143	Wed Jun 29 13:54:02 2005
+++ llvm/lib/Target/Alpha/AlphaISelPattern.cpp	Fri Jul  1 14:12:13 2005
@@ -612,7 +612,7 @@
     offset = 0;
   } else if (const GlobalValue* GV = dyn_cast<GlobalValue>(v)) {
     type = 1;
-    fun = 1;
+    fun = 0;
     const Module* M = GV->getParent();
       int i = 0;
       for(Module::const_global_iterator ii = M->global_begin(); &*ii != GV; ++ii)
@@ -646,6 +646,8 @@
       ++i;
     offset = i;
   }
+  //type = 4: register spilling
+  //type = 5: global address loading or constant loading
 }
 
 static int getUID()
@@ -887,8 +889,15 @@
     MachineFunction *F = BB->getParent();
     int FrameIdx = F->getFrameInfo()->CreateStackObject(Size, 8);
 
+    if (EnableAlphaLSMark)
+      BuildMI(BB, Alpha::MEMLABEL, 4).addImm(4).addImm(0).addImm(0)
+        .addImm(getUID());
     Opc = isDouble ? Alpha::STT : Alpha::STS;
     BuildMI(BB, Opc, 3).addReg(src).addFrameIndex(FrameIdx).addReg(Alpha::F31);
+
+    if (EnableAlphaLSMark)
+      BuildMI(BB, Alpha::MEMLABEL, 4).addImm(4).addImm(0).addImm(0)
+        .addImm(getUID());
     Opc = isDouble ? Alpha::LDQ : Alpha::LDL;
     BuildMI(BB, Alpha::LDQ, 2, dst).addFrameIndex(FrameIdx).addReg(Alpha::F31);
   }
@@ -907,8 +916,15 @@
     MachineFunction *F = BB->getParent();
     int FrameIdx = F->getFrameInfo()->CreateStackObject(Size, 8);
 
+    if (EnableAlphaLSMark)
+      BuildMI(BB, Alpha::MEMLABEL, 4).addImm(4).addImm(0).addImm(0)
+        .addImm(getUID());
     Opc = isDouble ? Alpha::STQ : Alpha::STL;
     BuildMI(BB, Opc, 3).addReg(src).addFrameIndex(FrameIdx).addReg(Alpha::F31);
+
+    if (EnableAlphaLSMark)
+      BuildMI(BB, Alpha::MEMLABEL, 4).addImm(4).addImm(0).addImm(0)
+        .addImm(getUID());
     Opc = isDouble ? Alpha::LDT : Alpha::LDS;
     BuildMI(BB, Opc, 2, dst).addFrameIndex(FrameIdx).addReg(Alpha::F31);
   }
@@ -1260,25 +1276,17 @@
         getValueInfo(dyn_cast<SrcValueSDNode>(N.getOperand(2))->getValue(),
                      i, j, k);
 
-      if (GlobalAddressSDNode *GASD = 
-          dyn_cast<GlobalAddressSDNode>(Address)) {
-        if (GASD->getGlobal()->isExternal()) {
-          Tmp1 = SelectExpr(Address);
-          if (EnableAlphaLSMark)
-            BuildMI(BB, Alpha::MEMLABEL, 4).addImm(i).addImm(j).addImm(k)
-              .addImm(getUID());
-          BuildMI(BB, Opc, 2, Result).addImm(0).addReg(Tmp1);
-        } else {
-          Tmp1 = MakeReg(MVT::i64);
-          AlphaLowering.restoreGP(BB);
-          BuildMI(BB, Alpha::LDAHr, 2, Tmp1)
-            .addGlobalAddress(GASD->getGlobal()).addReg(Alpha::R29);
-          if (EnableAlphaLSMark)
-            BuildMI(BB, Alpha::MEMLABEL, 4).addImm(i).addImm(j).addImm(k)
-              .addImm(getUID());
-          BuildMI(BB, GetRelVersion(Opc), 2, Result)
-            .addGlobalAddress(GASD->getGlobal()).addReg(Tmp1);
-        }
+      GlobalAddressSDNode *GASD = dyn_cast<GlobalAddressSDNode>(Address);
+      if (GASD && !GASD->getGlobal()->isExternal()) {
+        Tmp1 = MakeReg(MVT::i64);
+        AlphaLowering.restoreGP(BB);
+        BuildMI(BB, Alpha::LDAHr, 2, Tmp1)
+          .addGlobalAddress(GASD->getGlobal()).addReg(Alpha::R29);
+        if (EnableAlphaLSMark)
+          BuildMI(BB, Alpha::MEMLABEL, 4).addImm(i).addImm(j).addImm(k)
+            .addImm(getUID());
+        BuildMI(BB, GetRelVersion(Opc), 2, Result)
+          .addGlobalAddress(GASD->getGlobal()).addReg(Tmp1);
       } else if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(Address)) {
         AlphaLowering.restoreGP(BB);
         has_sym = true;
@@ -1313,7 +1321,7 @@
     has_sym = true;
 
     if (EnableAlphaLSMark)
-      BuildMI(BB, Alpha::MEMLABEL, 4).addImm(0).addImm(0).addImm(0)
+      BuildMI(BB, Alpha::MEMLABEL, 4).addImm(5).addImm(0).addImm(0)
         .addImm(getUID());
 
     BuildMI(BB, Alpha::LDQl, 2, Result)
@@ -1321,6 +1329,19 @@
       .addReg(Alpha::R29);
     return Result;
 
+  case ISD::ExternalSymbol:
+    AlphaLowering.restoreGP(BB);
+    has_sym = true;
+
+    if (EnableAlphaLSMark)
+      BuildMI(BB, Alpha::MEMLABEL, 4).addImm(5).addImm(0).addImm(0)
+        .addImm(getUID());
+
+    BuildMI(BB, Alpha::LDQl, 2, Result)
+      .addExternalSymbol(cast<ExternalSymbolSDNode>(N)->getSymbol())
+      .addReg(Alpha::R29);
+    return Result;
+
   case ISD::TAILCALL:
   case ISD::CALL:
     {
@@ -1393,27 +1414,12 @@
         }
       }
       //build the right kind of call
-      if (GlobalAddressSDNode *GASD =
-          dyn_cast<GlobalAddressSDNode>(N.getOperand(1)))
-      {
-        if (GASD->getGlobal()->isExternal()) {
-          //use safe calling convention
-          AlphaLowering.restoreGP(BB);
-          has_sym = true;
-          BuildMI(BB, Alpha::CALL, 1).addGlobalAddress(GASD->getGlobal());
-        } else {
-          //use PC relative branch call
-          AlphaLowering.restoreGP(BB);
-          BuildMI(BB, Alpha::BSR, 1, Alpha::R26)
-            .addGlobalAddress(GASD->getGlobal(),true);
-        }
-      }
-      else if (ExternalSymbolSDNode *ESSDN =
-               dyn_cast<ExternalSymbolSDNode>(N.getOperand(1)))
-      {
+      GlobalAddressSDNode *GASD = dyn_cast<GlobalAddressSDNode>(N.getOperand(1));
+      if (GASD && !GASD->getGlobal()->isExternal()) {
+        //use PC relative branch call
         AlphaLowering.restoreGP(BB);
-        has_sym = true;
-        BuildMI(BB, Alpha::CALL, 1).addExternalSymbol(ESSDN->getSymbol(), true);
+        BuildMI(BB, Alpha::BSR, 1, Alpha::R26)
+          .addGlobalAddress(GASD->getGlobal(),true);
       } else {
         //no need to restore GP as we are doing an indirect call
         Tmp1 = SelectExpr(N.getOperand(1));
@@ -1886,26 +1892,27 @@
     }
     //else fall though
   case ISD::UREM:
-  case ISD::SREM:
-    //FIXME: alpha really doesn't support any of these operations,
-    // the ops are expanded into special library calls with
-    // special calling conventions
-    //Restore GP because it is a call after all...
+  case ISD::SREM: {
+    const char* opstr = 0;
     switch(opcode) {
-    case ISD::UREM: Opc = Alpha::REMQU; break;
-    case ISD::SREM: Opc = Alpha::REMQ; break;
-    case ISD::UDIV: Opc = Alpha::DIVQU; break;
-    case ISD::SDIV: Opc = Alpha::DIVQ; break;
+    case ISD::UREM: opstr = "__remqu"; break;
+    case ISD::SREM: opstr = "__remq";  break;
+    case ISD::UDIV: opstr = "__divqu"; break;
+    case ISD::SDIV: opstr = "__divq";  break;
     }
     Tmp1 = SelectExpr(N.getOperand(0));
     Tmp2 = SelectExpr(N.getOperand(1));
+    SDOperand Addr = 
+      ISelDAG->getExternalSymbol(opstr, AlphaLowering.getPointerTy());
+    Tmp3 = SelectExpr(Addr);
     //set up regs explicitly (helps Reg alloc)
     BuildMI(BB, Alpha::BIS, 2, Alpha::R24).addReg(Tmp1).addReg(Tmp1);
     BuildMI(BB, Alpha::BIS, 2, Alpha::R25).addReg(Tmp2).addReg(Tmp2);
-    AlphaLowering.restoreGP(BB);
-    BuildMI(BB, Opc, 2).addReg(Alpha::R24).addReg(Alpha::R25);
+    BuildMI(BB, Alpha::BIS, 2, Alpha::R27).addReg(Tmp3).addReg(Tmp3);
+    BuildMI(BB, Alpha::JSRs, 2, Alpha::R23).addReg(Alpha::R27).addImm(0);
     BuildMI(BB, Alpha::BIS, 2, Result).addReg(Alpha::R27).addReg(Alpha::R27);
     return Result;
+  }
 
   case ISD::FP_TO_UINT:
   case ISD::FP_TO_SINT:
@@ -2095,6 +2102,9 @@
         Tmp1 = MakeReg(MVT::i64);
         BuildMI(BB, Alpha::LDAHr, 2, Tmp1).addConstantPoolIndex(CPI)
           .addReg(Alpha::R29);
+        if (EnableAlphaLSMark)
+          BuildMI(BB, Alpha::MEMLABEL, 4).addImm(5).addImm(0).addImm(0)
+            .addImm(getUID());
         BuildMI(BB, Alpha::LDQr, 2, Result).addConstantPoolIndex(CPI)
           .addReg(Tmp1);
       }
@@ -2289,25 +2299,17 @@
         getValueInfo(dyn_cast<SrcValueSDNode>(N.getOperand(3))->getValue(), 
                      i, j, k);
 
-      if (GlobalAddressSDNode *GASD = 
-          dyn_cast<GlobalAddressSDNode>(Address)) {
-        if (GASD->getGlobal()->isExternal()) {
-          Tmp2 = SelectExpr(Address);
-          if (EnableAlphaLSMark)
-            BuildMI(BB, Alpha::MEMLABEL, 4).addImm(i).addImm(j).addImm(k)
-              .addImm(getUID());
-          BuildMI(BB, Opc, 3).addReg(Tmp1).addImm(0).addReg(Tmp2);
-        } else {
-          Tmp2 = MakeReg(MVT::i64);
-          AlphaLowering.restoreGP(BB);
-          BuildMI(BB, Alpha::LDAHr, 2, Tmp2)
-            .addGlobalAddress(GASD->getGlobal()).addReg(Alpha::R29);
-          if (EnableAlphaLSMark)
-            BuildMI(BB, Alpha::MEMLABEL, 4).addImm(i).addImm(j).addImm(k)
-              .addImm(getUID());
-          BuildMI(BB, GetRelVersion(Opc), 3).addReg(Tmp1)
-            .addGlobalAddress(GASD->getGlobal()).addReg(Tmp2);
-        }
+      GlobalAddressSDNode *GASD = dyn_cast<GlobalAddressSDNode>(Address);
+      if (GASD && !GASD->getGlobal()->isExternal()) {
+        Tmp2 = MakeReg(MVT::i64);
+        AlphaLowering.restoreGP(BB);
+        BuildMI(BB, Alpha::LDAHr, 2, Tmp2)
+          .addGlobalAddress(GASD->getGlobal()).addReg(Alpha::R29);
+        if (EnableAlphaLSMark)
+          BuildMI(BB, Alpha::MEMLABEL, 4).addImm(i).addImm(j).addImm(k)
+            .addImm(getUID());
+        BuildMI(BB, GetRelVersion(Opc), 3).addReg(Tmp1)
+          .addGlobalAddress(GASD->getGlobal()).addReg(Tmp2);
       } else if(Address.getOpcode() == ISD::FrameIndex) {
         if (EnableAlphaLSMark)
           BuildMI(BB, Alpha::MEMLABEL, 4).addImm(i).addImm(j).addImm(k)


Index: llvm/lib/Target/Alpha/AlphaInstrInfo.td
diff -u llvm/lib/Target/Alpha/AlphaInstrInfo.td:1.51 llvm/lib/Target/Alpha/AlphaInstrInfo.td:1.52
--- llvm/lib/Target/Alpha/AlphaInstrInfo.td:1.51	Wed Jun 29 13:54:02 2005
+++ llvm/lib/Target/Alpha/AlphaInstrInfo.td	Fri Jul  1 14:12:13 2005
@@ -45,15 +45,6 @@
   let Uses = [R27] in
     def LDGP : PseudoInstAlpha<(ops), "ldgp $$29, 0($$27)">;
 
-let isCall = 1,
-    Defs = [R0, R1, R2, R3, R4, R5, R6, R7, R8, R16, R17, R18, R19,
-            R20, R21, R22, R23, R24, R25, R26, R27, R28, R29,
-            F0, F1,
-            F10, F11, F12, F13, F14, F15, F16, F17, F18, F19,
-            F20, F21, F22, F23, F24, F25, F26, F27, F28, F29, F30],
-    Uses = [R29] in
-      def CALL : PseudoInstAlpha< (ops s64imm:$TARGET), "jsr $TARGET">; //Jump to subroutine
-
 //RESULTS of these go to R27
 //These are also evil as the assembler expands them into calls
 let Uses = [R29], 
@@ -305,6 +296,9 @@
     def JSR : MForm< 0x1A, (ops GPRC:$RD, GPRC:$RS, s14imm:$DISP), "jsr $RD,($RS),$DISP">; //Jump to subroutine
     def BSR : BForm<0x34, (ops GPRC:$RD, s21imm:$DISP), "bsr $RD,$DISP">; //Branch to subroutine
 }
+let isCall = 1, Defs = [R24, R25, R27, R28], Uses = [R24, R25] in
+  def JSRs : MForm< 0x1A, (ops GPRC:$RD, GPRC:$RS, s14imm:$DISP), "jsr $RD,($RS),$DISP">; //Jump to div or rem
+
 
 def JSR_COROUTINE : MForm< 0x1A, (ops GPRC:$RD, GPRC:$RS), "jsr_coroutine $RD,($RS),1">; //Jump to subroutine return
 def BR : BForm<0x30, (ops GPRC:$RD, s21imm:$DISP), "br $RD,$DISP">; //Branch


Index: llvm/lib/Target/Alpha/AlphaRegisterInfo.cpp
diff -u llvm/lib/Target/Alpha/AlphaRegisterInfo.cpp:1.22 llvm/lib/Target/Alpha/AlphaRegisterInfo.cpp:1.23
--- llvm/lib/Target/Alpha/AlphaRegisterInfo.cpp:1.22	Thu Jun 23 18:42:05 2005
+++ llvm/lib/Target/Alpha/AlphaRegisterInfo.cpp	Fri Jul  1 14:12:13 2005
@@ -31,6 +31,10 @@
 #include <iostream>
 using namespace llvm;
 
+namespace llvm {
+  extern cl::opt<bool> EnableAlphaLSMark;
+}
+
 //These describe LDAx
 static const int IMM_LOW  = -32768;
 static const int IMM_HIGH = 32767;
@@ -50,6 +54,12 @@
   return l - h * IMM_MULT;
 }
 
+static int getUID()
+{
+  static int id = 0;
+  return ++id;
+}
+
 AlphaRegisterInfo::AlphaRegisterInfo()
   : AlphaGenRegisterInfo(Alpha::ADJUSTSTACKDOWN, Alpha::ADJUSTSTACKUP)
 {
@@ -68,6 +78,9 @@
                                        unsigned SrcReg, int FrameIdx) const {
   //std::cerr << "Trying to store " << getPrettyName(SrcReg) << " to " << FrameIdx << "\n";
   //BuildMI(MBB, MI, Alpha::WTF, 0).addReg(SrcReg);
+  if (EnableAlphaLSMark)
+    BuildMI(MBB, MI, Alpha::MEMLABEL, 4).addImm(4).addImm(0).addImm(1)
+      .addImm(getUID());
   if (getClass(SrcReg) == Alpha::FPRCRegisterClass)
     BuildMI(MBB, MI, Alpha::STT, 3).addReg(SrcReg).addFrameIndex(FrameIdx).addReg(Alpha::F31);
   else if (getClass(SrcReg) == Alpha::GPRCRegisterClass)
@@ -81,6 +94,9 @@
                                         MachineBasicBlock::iterator MI,
                                         unsigned DestReg, int FrameIdx) const{
   //std::cerr << "Trying to load " << getPrettyName(DestReg) << " to " << FrameIdx << "\n";
+  if (EnableAlphaLSMark)
+    BuildMI(MBB, MI, Alpha::MEMLABEL, 4).addImm(4).addImm(0).addImm(2)
+      .addImm(getUID());
   if (getClass(DestReg) == Alpha::FPRCRegisterClass)
     BuildMI(MBB, MI, Alpha::LDT, 2, DestReg).addFrameIndex(FrameIdx).addReg(Alpha::F31);
   else if (getClass(DestReg) == Alpha::GPRCRegisterClass)





From alenhar2 at cs.uiuc.edu  Fri Jul  1 14:14:14 2005
From: alenhar2 at cs.uiuc.edu (Andrew Lenharth)
Date: Fri, 1 Jul 2005 14:14:14 -0500
Subject: [llvm-commits] CVS: llvm/lib/Target/Alpha/AlphaInstrInfo.td 
Message-ID: <200507011914.OAA26648@zion.cs.uiuc.edu>



Changes in directory llvm/lib/Target/Alpha:

AlphaInstrInfo.td updated: 1.52 -> 1.53
---
Log message:

simplify call code, remove pseudo ops for div and rem, track more loads and stores

---
Diffs of the changes:  (+0 -17)

 AlphaInstrInfo.td |   17 -----------------
 1 files changed, 17 deletions(-)


Index: llvm/lib/Target/Alpha/AlphaInstrInfo.td
diff -u llvm/lib/Target/Alpha/AlphaInstrInfo.td:1.52 llvm/lib/Target/Alpha/AlphaInstrInfo.td:1.53
--- llvm/lib/Target/Alpha/AlphaInstrInfo.td:1.52	Fri Jul  1 14:12:13 2005
+++ llvm/lib/Target/Alpha/AlphaInstrInfo.td	Fri Jul  1 14:14:02 2005
@@ -45,23 +45,6 @@
   let Uses = [R27] in
     def LDGP : PseudoInstAlpha<(ops), "ldgp $$29, 0($$27)">;
 
-//RESULTS of these go to R27
-//These are also evil as the assembler expands them into calls
-let Uses = [R29], 
-    Defs = [R28, R23, R24, R25, R27] in
-{
-  def REMQU : PseudoInstAlpha<(ops GPRC:$RA, GPRC:$RB), "remqu $RA,$RB,$$27">; //unsigned remander
-  def REMQ  : PseudoInstAlpha<(ops GPRC:$RA, GPRC:$RB), "remq $RA,$RB,$$27">; //signed remander
-  def DIVQU : PseudoInstAlpha<(ops GPRC:$RA, GPRC:$RB), "divqu $RA,$RB,$$27">; //unsigned division
-  def DIVQ  : PseudoInstAlpha<(ops GPRC:$RA, GPRC:$RB), "divq $RA,$RB,$$27">; //signed division
-}
-
-//This is an improvement on the old style setcc (FP)
-//def CC2INT_INV : PseudoInstAlpha<(ops GPRC:$RES, FPRC:$COND), 
-//  "lda $RES,1($$31)\n\tfbeq $COND, 42f\n\tbis $$31,$$31,$RES\n42:\n">;
-//def CC2INT : PseudoInstAlpha<(ops GPRC:$RES, FPRC:$COND), 
-//  "lda $RES,1($$31)\n\tfbne $COND, 42f\n\tbis $$31,$$31,$RES\n42:\n">;
-
 //An even better improvement on the Int = SetCC(FP):  SelectCC!
 //These are evil because they hide control flow in a MBB
 //really the ISel should emit multiple MBB





From lattner at cs.uiuc.edu  Fri Jul  1 17:44:20 2005
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Fri, 1 Jul 2005 17:44:20 -0500
Subject: [llvm-commits] CVS: llvm/lib/Target/X86/X86ATTAsmPrinter.cpp
	X86ATTAsmPrinter.h X86AsmPrinter.h X86IntelAsmPrinter.cpp
	X86IntelAsmPrinter.h X86AsmPrinter.cpp 
Message-ID: <200507012244.RAA04062@zion.cs.uiuc.edu>



Changes in directory llvm/lib/Target/X86:

X86ATTAsmPrinter.cpp added (r1.1)
X86ATTAsmPrinter.h added (r1.1)
X86AsmPrinter.h added (r1.1)
X86IntelAsmPrinter.cpp added (r1.1)
X86IntelAsmPrinter.h added (r1.1)
X86AsmPrinter.cpp updated: 1.138 -> 1.139
---
Log message:

Refactor X86AsmPrinter.cpp into multiple files.  Patch contributed
by Aaron Gray, cleaned up by me.


---
Diffs of the changes:  (+759 -640)

 X86ATTAsmPrinter.cpp   |  171 ++++++++++
 X86ATTAsmPrinter.h     |   61 +++
 X86AsmPrinter.cpp      |  812 ++++++++++---------------------------------------
 X86AsmPrinter.h        |   69 ++++
 X86IntelAsmPrinter.cpp |  205 ++++++++++++
 X86IntelAsmPrinter.h   |   81 ++++
 6 files changed, 759 insertions(+), 640 deletions(-)


Index: llvm/lib/Target/X86/X86ATTAsmPrinter.cpp
diff -c /dev/null llvm/lib/Target/X86/X86ATTAsmPrinter.cpp:1.1
*** /dev/null	Fri Jul  1 17:44:19 2005
--- llvm/lib/Target/X86/X86ATTAsmPrinter.cpp	Fri Jul  1 17:44:09 2005
***************
*** 0 ****
--- 1,171 ----
+ //===-- X86ATTAsmPrinter.cpp - Convert X86 LLVM code to Intel assembly ----===//
+ //
+ //                     The LLVM Compiler Infrastructure
+ //
+ // This file was developed by the LLVM research group and is distributed under
+ // the University of Illinois Open Source License. See LICENSE.TXT for details.
+ //
+ //===----------------------------------------------------------------------===//
+ //
+ // This file contains a printer that converts from our internal representation
+ // of machine-dependent LLVM code to AT&T format assembly
+ // language. This printer is the output mechanism used by `llc'.
+ //
+ //===----------------------------------------------------------------------===//
+ 
+ #include "X86ATTAsmPrinter.h"
+ #include "X86.h"
+ #include "X86TargetMachine.h"
+ #include "llvm/Module.h"
+ #include "llvm/Support/Mangler.h"
+ using namespace llvm;
+ using namespace x86;
+ 
+ /// runOnMachineFunction - This uses the printMachineInstruction()
+ /// method to print assembly for each instruction.
+ ///
+ bool X86ATTAsmPrinter::runOnMachineFunction(MachineFunction &MF) {
+   setupMachineFunction(MF);
+   O << "\n\n";
+ 
+   // Print out constants referenced by the function
+   printConstantPool(MF.getConstantPool());
+ 
+   // Print out labels for the function.
+   O << "\t.text\n";
+   emitAlignment(4);
+   O << "\t.globl\t" << CurrentFnName << "\n";
+   if (!forCygwin && !forDarwin)
+     O << "\t.type\t" << CurrentFnName << ", @function\n";
+   O << CurrentFnName << ":\n";
+ 
+   // Print out code for the function.
+   for (MachineFunction::const_iterator I = MF.begin(), E = MF.end();
+        I != E; ++I) {
+     // Print a label for the basic block.
+     if (I->pred_begin() != I->pred_end())
+       O << ".LBB" << CurrentFnName << "_" << I->getNumber() << ":\t"
+         << CommentString << " " << I->getBasicBlock()->getName() << "\n";
+     for (MachineBasicBlock::const_iterator II = I->begin(), E = I->end();
+          II != E; ++II) {
+       // Print the assembly for the instruction.
+       O << "\t";
+       printMachineInstruction(II);
+     }
+   }
+ 
+   // We didn't modify anything.
+   return false;
+ }
+ 
+ void X86ATTAsmPrinter::printOp(const MachineOperand &MO, bool isCallOp) {
+   const MRegisterInfo &RI = *TM.getRegisterInfo();
+   switch (MO.getType()) {
+   case MachineOperand::MO_VirtualRegister:
+   case MachineOperand::MO_MachineRegister:
+     assert(MRegisterInfo::isPhysicalRegister(MO.getReg()) &&
+            "Virtual registers should not make it this far!");
+     O << '%';
+     for (const char *Name = RI.get(MO.getReg()).Name; *Name; ++Name)
+       O << (char)tolower(*Name);
+     return;
+ 
+   case MachineOperand::MO_SignExtendedImmed:
+   case MachineOperand::MO_UnextendedImmed:
+     O << '$' << (int)MO.getImmedValue();
+     return;
+   case MachineOperand::MO_MachineBasicBlock: {
+     MachineBasicBlock *MBBOp = MO.getMachineBasicBlock();
+     O << ".LBB" << Mang->getValueName(MBBOp->getParent()->getFunction())
+       << "_" << MBBOp->getNumber () << "\t# "
+       << MBBOp->getBasicBlock ()->getName ();
+     return;
+   }
+   case MachineOperand::MO_PCRelativeDisp:
+     std::cerr << "Shouldn't use addPCDisp() when building X86 MachineInstrs";
+     abort ();
+     return;
+   case MachineOperand::MO_GlobalAddress: {
+     if (!isCallOp) O << '$';
+     O << Mang->getValueName(MO.getGlobal());
+     int Offset = MO.getOffset();
+     if (Offset > 0)
+       O << "+" << Offset;
+     else if (Offset < 0)
+       O << Offset;
+     return;
+   }
+   case MachineOperand::MO_ExternalSymbol:
+     if (!isCallOp) O << '$';
+     O << GlobalPrefix << MO.getSymbolName();
+     return;
+   default:
+     O << "<unknown operand type>"; return;
+   }
+ }
+ 
+ void X86ATTAsmPrinter::printMemReference(const MachineInstr *MI, unsigned Op){
+   assert(isMem(MI, Op) && "Invalid memory reference!");
+ 
+   const MachineOperand &BaseReg  = MI->getOperand(Op);
+   int ScaleVal                   = MI->getOperand(Op+1).getImmedValue();
+   const MachineOperand &IndexReg = MI->getOperand(Op+2);
+   const MachineOperand &DispSpec = MI->getOperand(Op+3);
+ 
+   if (BaseReg.isFrameIndex()) {
+     O << "[frame slot #" << BaseReg.getFrameIndex();
+     if (DispSpec.getImmedValue())
+       O << " + " << DispSpec.getImmedValue();
+     O << "]";
+     return;
+   } else if (BaseReg.isConstantPoolIndex()) {
+     O << ".CPI" << CurrentFnName << "_"
+       << BaseReg.getConstantPoolIndex();
+     if (DispSpec.getImmedValue())
+       O << "+" << DispSpec.getImmedValue();
+     if (IndexReg.getReg()) {
+       O << "(,";
+       printOp(IndexReg);
+       if (ScaleVal != 1)
+         O << "," << ScaleVal;
+       O << ")";
+     }
+     return;
+   }
+ 
+   if (DispSpec.isGlobalAddress()) {
+     printOp(DispSpec, true);
+   } else {
+     int DispVal = DispSpec.getImmedValue();
+     if (DispVal || (!IndexReg.getReg() && !BaseReg.getReg()))
+       O << DispVal;
+   }
+ 
+   if (IndexReg.getReg() || BaseReg.getReg()) {
+     O << "(";
+     if (BaseReg.getReg())
+       printOp(BaseReg);
+ 
+     if (IndexReg.getReg()) {
+       O << ",";
+       printOp(IndexReg);
+       if (ScaleVal != 1)
+         O << "," << ScaleVal;
+     }
+ 
+     O << ")";
+   }
+ }
+ 
+ /// printMachineInstruction -- Print out a single X86 LLVM instruction
+ /// MI in Intel syntax to the current output stream.
+ ///
+ void X86ATTAsmPrinter::printMachineInstruction(const MachineInstr *MI) {
+   ++EmittedInsts;
+   // Call the autogenerated instruction printer routines.
+   printInstruction(MI);
+ }
+ 
+ // Include the auto-generated portion of the assembly writer.
+ #include "X86GenAsmWriter.inc"
+ 


Index: llvm/lib/Target/X86/X86ATTAsmPrinter.h
diff -c /dev/null llvm/lib/Target/X86/X86ATTAsmPrinter.h:1.1
*** /dev/null	Fri Jul  1 17:44:20 2005
--- llvm/lib/Target/X86/X86ATTAsmPrinter.h	Fri Jul  1 17:44:09 2005
***************
*** 0 ****
--- 1,61 ----
+ //===-- X86ATTAsmPrinter.h - Convert X86 LLVM code to Intel assembly ------===//
+ //
+ //                     The LLVM Compiler Infrastructure
+ //
+ // This file was developed by the LLVM research group and is distributed under
+ // the University of Illinois Open Source License. See LICENSE.TXT for details.
+ //
+ //===----------------------------------------------------------------------===//
+ //
+ // AT&T assembly code printer class.
+ //
+ //===----------------------------------------------------------------------===//
+ 
+ #ifndef X86ATTASMPRINTER_H
+ #define X86ATTASMPRINTER_H
+ 
+ #include "X86AsmPrinter.h"
+ #include "llvm/CodeGen/ValueTypes.h"
+ 
+ namespace llvm {
+ namespace x86 {
+ 
+ struct X86ATTAsmPrinter : public X86SharedAsmPrinter {
+   X86ATTAsmPrinter(std::ostream &O, TargetMachine &TM)
+     : X86SharedAsmPrinter(O, TM) { }
+ 
+   virtual const char *getPassName() const {
+     return "X86 AT&T-Style Assembly Printer";
+   }
+ 
+   /// printInstruction - This method is automatically generated by tablegen
+   /// from the instruction set description.  This method returns true if the
+   /// machine instruction was sufficiently described to print it, otherwise it
+   /// returns false.
+   bool printInstruction(const MachineInstr *MI);
+ 
+   // This method is used by the tablegen'erated instruction printer.
+   void printOperand(const MachineInstr *MI, unsigned OpNo, MVT::ValueType VT){
+     printOp(MI->getOperand(OpNo));
+   }
+ 
+   void printCallOperand(const MachineInstr *MI, unsigned OpNo,
+                         MVT::ValueType VT) {
+     printOp(MI->getOperand(OpNo), true); // Don't print '$' prefix.
+   }
+ 
+   void printMemoryOperand(const MachineInstr *MI, unsigned OpNo,
+                           MVT::ValueType VT) {
+     printMemReference(MI, OpNo);
+   }
+ 
+   void printMachineInstruction(const MachineInstr *MI);
+   void printOp(const MachineOperand &MO, bool isCallOperand = false);
+   void printMemReference(const MachineInstr *MI, unsigned Op);
+   bool runOnMachineFunction(MachineFunction &F);
+ };
+ 
+ } // end namespace x86
+ } // end namespace llvm
+ 
+ #endif


Index: llvm/lib/Target/X86/X86AsmPrinter.h
diff -c /dev/null llvm/lib/Target/X86/X86AsmPrinter.h:1.1
*** /dev/null	Fri Jul  1 17:44:20 2005
--- llvm/lib/Target/X86/X86AsmPrinter.h	Fri Jul  1 17:44:09 2005
***************
*** 0 ****
--- 1,69 ----
+ //===-- X86AsmPrinter.h - Convert X86 LLVM code to Intel assembly ---------===//
+ //
+ //                     The LLVM Compiler Infrastructure
+ //
+ // This file was developed by the LLVM research group and is distributed under
+ // the University of Illinois Open Source License. See LICENSE.TXT for details.
+ //
+ //===----------------------------------------------------------------------===//
+ //
+ // This file the shared super class printer that converts from our internal
+ // representation of machine-dependent LLVM code to Intel and AT&T format
+ // assembly language.  This printer is the output mechanism used by `llc'.
+ //
+ //===----------------------------------------------------------------------===//
+ 
+ #ifndef X86ASMPRINTER_H
+ #define X86ASMPRINTER_H
+ 
+ #include "X86.h"
+ #include "llvm/CodeGen/AsmPrinter.h"
+ #include "llvm/ADT/Statistic.h"
+ 
+ namespace llvm {
+ namespace x86 {
+ 
+ extern Statistic<> EmittedInsts;
+ 
+ struct X86SharedAsmPrinter : public AsmPrinter {
+   X86SharedAsmPrinter(std::ostream &O, TargetMachine &TM)
+     : AsmPrinter(O, TM), forCygwin(false), forDarwin(false) { }
+ 
+   bool doInitialization(Module &M);
+   void printConstantPool(MachineConstantPool *MCP);
+   bool doFinalization(Module &M);
+ 
+   bool forCygwin;
+   bool forDarwin;
+ 
+   inline static bool isScale(const MachineOperand &MO) {
+     return MO.isImmediate() &&
+           (MO.getImmedValue() == 1 || MO.getImmedValue() == 2 ||
+           MO.getImmedValue() == 4 || MO.getImmedValue() == 8);
+   }
+ 
+   inline static bool isMem(const MachineInstr *MI, unsigned Op) {
+     if (MI->getOperand(Op).isFrameIndex()) return true;
+     if (MI->getOperand(Op).isConstantPoolIndex()) return true;
+     return Op+4 <= MI->getNumOperands() &&
+       MI->getOperand(Op  ).isRegister() && isScale(MI->getOperand(Op+1)) &&
+       MI->getOperand(Op+2).isRegister() && (MI->getOperand(Op+3).isImmediate()||
+       MI->getOperand(Op+3).isGlobalAddress());
+   }
+ 
+   // SwitchSection - Switch to the specified section of the executable if we are
+   // not already in it!
+   inline static void SwitchSection(std::ostream &OS, std::string &CurSection,
+                                    const char *NewSection) {
+     if (CurSection != NewSection) {
+       CurSection = NewSection;
+       if (!CurSection.empty())
+         OS << "\t" << NewSection << "\n";
+     }
+   }
+ };
+ 
+ } // end namespace x86
+ } // end namespace llvm
+ 
+ #endif


Index: llvm/lib/Target/X86/X86IntelAsmPrinter.cpp
diff -c /dev/null llvm/lib/Target/X86/X86IntelAsmPrinter.cpp:1.1
*** /dev/null	Fri Jul  1 17:44:20 2005
--- llvm/lib/Target/X86/X86IntelAsmPrinter.cpp	Fri Jul  1 17:44:09 2005
***************
*** 0 ****
--- 1,205 ----
+ //===-- X86IntelAsmPrinter.cpp - Convert X86 LLVM code to Intel assembly --===//
+ //
+ //                     The LLVM Compiler Infrastructure
+ //
+ // This file was developed by the LLVM research group and is distributed under
+ // the University of Illinois Open Source License. See LICENSE.TXT for details.
+ //
+ //===----------------------------------------------------------------------===//
+ //
+ // This file contains a printer that converts from our internal representation
+ // of machine-dependent LLVM code to Intel format assembly language.
+ // This printer is the output mechanism used by `llc'.
+ //
+ //===----------------------------------------------------------------------===//
+ 
+ #include "X86IntelAsmPrinter.h"
+ #include "X86.h"
+ #include "llvm/Module.h"
+ #include "llvm/Assembly/Writer.h"
+ #include "llvm/Support/Mangler.h"
+ using namespace llvm;
+ using namespace x86;
+ 
+ /// runOnMachineFunction - This uses the printMachineInstruction()
+ /// method to print assembly for each instruction.
+ ///
+ bool X86IntelAsmPrinter::runOnMachineFunction(MachineFunction &MF) {
+   setupMachineFunction(MF);
+   O << "\n\n";
+ 
+   // Print out constants referenced by the function
+   printConstantPool(MF.getConstantPool());
+ 
+   // Print out labels for the function.
+   O << "\t.text\n";
+   emitAlignment(4);
+   O << "\t.globl\t" << CurrentFnName << "\n";
+   if (!forCygwin && !forDarwin)
+     O << "\t.type\t" << CurrentFnName << ", @function\n";
+   O << CurrentFnName << ":\n";
+ 
+   // Print out code for the function.
+   for (MachineFunction::const_iterator I = MF.begin(), E = MF.end();
+        I != E; ++I) {
+     // Print a label for the basic block if there are any predecessors.
+     if (I->pred_begin() != I->pred_end())
+       O << ".LBB" << CurrentFnName << "_" << I->getNumber() << ":\t"
+         << CommentString << " " << I->getBasicBlock()->getName() << "\n";
+     for (MachineBasicBlock::const_iterator II = I->begin(), E = I->end();
+          II != E; ++II) {
+       // Print the assembly for the instruction.
+       O << "\t";
+       printMachineInstruction(II);
+     }
+   }
+ 
+   // We didn't modify anything.
+   return false;
+ }
+ 
+ void X86IntelAsmPrinter::printOp(const MachineOperand &MO,
+                                  bool elideOffsetKeyword /* = false */) {
+   const MRegisterInfo &RI = *TM.getRegisterInfo();
+   switch (MO.getType()) {
+   case MachineOperand::MO_VirtualRegister:
+     if (Value *V = MO.getVRegValueOrNull()) {
+       O << "<" << V->getName() << ">";
+       return;
+     }
+     // FALLTHROUGH
+   case MachineOperand::MO_MachineRegister:
+     if (MRegisterInfo::isPhysicalRegister(MO.getReg()))
+       // Bug Workaround: See note in Printer::doInitialization about %.
+       O << "%" << RI.get(MO.getReg()).Name;
+     else
+       O << "%reg" << MO.getReg();
+     return;
+ 
+   case MachineOperand::MO_SignExtendedImmed:
+   case MachineOperand::MO_UnextendedImmed:
+     O << (int)MO.getImmedValue();
+     return;
+   case MachineOperand::MO_MachineBasicBlock: {
+     MachineBasicBlock *MBBOp = MO.getMachineBasicBlock();
+     O << ".LBB" << Mang->getValueName(MBBOp->getParent()->getFunction())
+       << "_" << MBBOp->getNumber () << "\t# "
+       << MBBOp->getBasicBlock ()->getName ();
+     return;
+   }
+   case MachineOperand::MO_PCRelativeDisp:
+     std::cerr << "Shouldn't use addPCDisp() when building X86 MachineInstrs";
+     abort ();
+     return;
+   case MachineOperand::MO_GlobalAddress: {
+     if (!elideOffsetKeyword)
+       O << "OFFSET ";
+     O << Mang->getValueName(MO.getGlobal());
+     int Offset = MO.getOffset();
+     if (Offset > 0)
+       O << " + " << Offset;
+     else if (Offset < 0)
+       O << " - " << -Offset;
+     return;
+   }
+   case MachineOperand::MO_ExternalSymbol:
+     O << GlobalPrefix << MO.getSymbolName();
+     return;
+   default:
+     O << "<unknown operand type>"; return;
+   }
+ }
+ 
+ void X86IntelAsmPrinter::printMemReference(const MachineInstr *MI, unsigned Op){
+   assert(isMem(MI, Op) && "Invalid memory reference!");
+ 
+   const MachineOperand &BaseReg  = MI->getOperand(Op);
+   int ScaleVal                   = MI->getOperand(Op+1).getImmedValue();
+   const MachineOperand &IndexReg = MI->getOperand(Op+2);
+   const MachineOperand &DispSpec = MI->getOperand(Op+3);
+ 
+   if (BaseReg.isFrameIndex()) {
+     O << "[frame slot #" << BaseReg.getFrameIndex();
+     if (DispSpec.getImmedValue())
+       O << " + " << DispSpec.getImmedValue();
+     O << "]";
+     return;
+   } else if (BaseReg.isConstantPoolIndex()) {
+     O << "[.CPI" << CurrentFnName << "_"
+       << BaseReg.getConstantPoolIndex();
+ 
+     if (IndexReg.getReg()) {
+       O << " + ";
+       if (ScaleVal != 1)
+         O << ScaleVal << "*";
+       printOp(IndexReg);
+     }
+ 
+     if (DispSpec.getImmedValue())
+       O << " + " << DispSpec.getImmedValue();
+     O << "]";
+     return;
+   }
+ 
+   O << "[";
+   bool NeedPlus = false;
+   if (BaseReg.getReg()) {
+     printOp(BaseReg, true);
+     NeedPlus = true;
+   }
+ 
+   if (IndexReg.getReg()) {
+     if (NeedPlus) O << " + ";
+     if (ScaleVal != 1)
+       O << ScaleVal << "*";
+     printOp(IndexReg);
+     NeedPlus = true;
+   }
+ 
+   if (DispSpec.isGlobalAddress()) {
+     if (NeedPlus)
+       O << " + ";
+     printOp(DispSpec, true);
+   } else {
+     int DispVal = DispSpec.getImmedValue();
+     if (DispVal || (!BaseReg.getReg() && !IndexReg.getReg())) {
+       if (NeedPlus)
+         if (DispVal > 0)
+           O << " + ";
+         else {
+           O << " - ";
+           DispVal = -DispVal;
+         }
+       O << DispVal;
+     }
+   }
+   O << "]";
+ }
+ 
+ 
+ /// printMachineInstruction -- Print out a single X86 LLVM instruction
+ /// MI in Intel syntax to the current output stream.
+ ///
+ void X86IntelAsmPrinter::printMachineInstruction(const MachineInstr *MI) {
+   ++EmittedInsts;
+ 
+   // Call the autogenerated instruction printer routines.
+   printInstruction(MI);
+ }
+ 
+ bool X86IntelAsmPrinter::doInitialization(Module &M) {
+   AsmPrinter::doInitialization(M);
+   // Tell gas we are outputting Intel syntax (not AT&T syntax) assembly.
+   //
+   // Bug: gas in `intel_syntax noprefix' mode interprets the symbol `Sp' in an
+   // instruction as a reference to the register named sp, and if you try to
+   // reference a symbol `Sp' (e.g. `mov ECX, OFFSET Sp') then it gets lowercased
+   // before being looked up in the symbol table. This creates spurious
+   // `undefined symbol' errors when linking. Workaround: Do not use `noprefix'
+   // mode, and decorate all register names with percent signs.
+   O << "\t.intel_syntax\n";
+   return false;
+ }
+ 
+ // Include the auto-generated portion of the assembly writer.
+ #include "X86GenAsmWriter1.inc"


Index: llvm/lib/Target/X86/X86IntelAsmPrinter.h
diff -c /dev/null llvm/lib/Target/X86/X86IntelAsmPrinter.h:1.1
*** /dev/null	Fri Jul  1 17:44:20 2005
--- llvm/lib/Target/X86/X86IntelAsmPrinter.h	Fri Jul  1 17:44:09 2005
***************
*** 0 ****
--- 1,81 ----
+ //===-- X86IntelAsmPrinter.h - Convert X86 LLVM code to Intel assembly ----===//
+ //
+ //                     The LLVM Compiler Infrastructure
+ //
+ // This file was developed by the LLVM research group and is distributed under
+ // the University of Illinois Open Source License. See LICENSE.TXT for details.
+ //
+ //===----------------------------------------------------------------------===//
+ //
+ // Intel assembly code printer class.
+ //
+ //===----------------------------------------------------------------------===//
+ 
+ #ifndef X86INTELASMPRINTER_H
+ #define X86INTELASMPRINTER_H
+ 
+ #include "X86AsmPrinter.h"
+ #include "llvm/CodeGen/ValueTypes.h"
+ #include "llvm/Target/TargetMachine.h"
+ #include "llvm/Target/MRegisterInfo.h"
+ 
+ namespace llvm {
+ namespace x86 {
+ 
+ struct X86IntelAsmPrinter : public X86SharedAsmPrinter {
+   X86IntelAsmPrinter(std::ostream &O, TargetMachine &TM)
+     : X86SharedAsmPrinter(O, TM) { }
+ 
+   virtual const char *getPassName() const {
+     return "X86 Intel-Style Assembly Printer";
+   }
+ 
+   /// printInstruction - This method is automatically generated by tablegen
+   /// from the instruction set description.  This method returns true if the
+   /// machine instruction was sufficiently described to print it, otherwise it
+   /// returns false.
+   bool printInstruction(const MachineInstr *MI);
+ 
+   // This method is used by the tablegen'erated instruction printer.
+   void printOperand(const MachineInstr *MI, unsigned OpNo, MVT::ValueType VT){
+     const MachineOperand &MO = MI->getOperand(OpNo);
+     if (MO.getType() == MachineOperand::MO_MachineRegister) {
+       assert(MRegisterInfo::isPhysicalRegister(MO.getReg())&&"Not physref??");
+       // Bug Workaround: See note in Printer::doInitialization about %.
+       O << "%" << TM.getRegisterInfo()->get(MO.getReg()).Name;
+     } else {
+       printOp(MO);
+     }
+   }
+ 
+   void printCallOperand(const MachineInstr *MI, unsigned OpNo,
+                         MVT::ValueType VT) {
+     printOp(MI->getOperand(OpNo), true); // Don't print "OFFSET".
+   }
+ 
+   void printMemoryOperand(const MachineInstr *MI, unsigned OpNo,
+                           MVT::ValueType VT) {
+     switch (VT) {
+     default: assert(0 && "Unknown arg size!");
+     case MVT::i8:   O << "BYTE PTR "; break;
+     case MVT::i16:  O << "WORD PTR "; break;
+     case MVT::i32:
+     case MVT::f32:  O << "DWORD PTR "; break;
+     case MVT::i64:
+     case MVT::f64:  O << "QWORD PTR "; break;
+     case MVT::f80:  O << "XWORD PTR "; break;
+     }
+     printMemReference(MI, OpNo);
+   }
+ 
+   void printMachineInstruction(const MachineInstr *MI);
+   void printOp(const MachineOperand &MO, bool elideOffsetKeyword = false);
+   void printMemReference(const MachineInstr *MI, unsigned Op);
+   bool runOnMachineFunction(MachineFunction &F);
+   bool doInitialization(Module &M);
+ };
+ 
+ } // end namespace x86
+ } // end namespace llvm
+ 
+ #endif


Index: llvm/lib/Target/X86/X86AsmPrinter.cpp
diff -u llvm/lib/Target/X86/X86AsmPrinter.cpp:1.138 llvm/lib/Target/X86/X86AsmPrinter.cpp:1.139
--- llvm/lib/Target/X86/X86AsmPrinter.cpp:1.138	Wed Jun 29 19:53:20 2005
+++ llvm/lib/Target/X86/X86AsmPrinter.cpp	Fri Jul  1 17:44:09 2005
@@ -1,640 +1,172 @@
-//===-- X86AsmPrinter.cpp - Convert X86 LLVM code to Intel assembly -------===//
-//
-//                     The LLVM Compiler Infrastructure
-//
-// This file was developed by the LLVM research group and is distributed under
-// the University of Illinois Open Source License. See LICENSE.TXT for details.
-//
-//===----------------------------------------------------------------------===//
-//
-// This file contains a printer that converts from our internal representation
-// of machine-dependent LLVM code to Intel and AT&T format assembly
-// language. This printer is the output mechanism used by `llc' and `lli
-// -print-machineinstrs' on X86.
-//
-//===----------------------------------------------------------------------===//
-
-#include "X86.h"
-#include "X86TargetMachine.h"
-#include "llvm/Module.h"
-#include "llvm/Type.h"
-#include "llvm/Assembly/Writer.h"
-#include "llvm/CodeGen/AsmPrinter.h"
-#include "llvm/CodeGen/MachineConstantPool.h"
-#include "llvm/CodeGen/MachineFunctionPass.h"
-#include "llvm/CodeGen/ValueTypes.h"
-#include "llvm/Target/TargetMachine.h"
-#include "llvm/Support/Mangler.h"
-#include "llvm/ADT/Statistic.h"
-#include "llvm/Support/CommandLine.h"
-using namespace llvm;
-
-namespace {
-  Statistic<> EmittedInsts("asm-printer", "Number of machine instrs printed");
-  enum AsmWriterFlavor { att, intel };
-
-  cl::opt<AsmWriterFlavor>
-  AsmWriterFlavor("x86-asm-syntax",
-                  cl::desc("Choose style of code to emit from X86 backend:"),
-                  cl::values(
-                             clEnumVal(att,   "  Emit AT&T-style assembly"),
-                             clEnumVal(intel, "  Emit Intel-style assembly"),
-                             clEnumValEnd),
-                  cl::init(att));
-
-  struct X86SharedAsmPrinter : public AsmPrinter {
-    X86SharedAsmPrinter(std::ostream &O, TargetMachine &TM)
-      : AsmPrinter(O, TM), forCygwin(false), forDarwin(false) { }
-
-    bool doInitialization(Module &M);
-    void printConstantPool(MachineConstantPool *MCP);
-    bool doFinalization(Module &M);
-    bool forCygwin;
-    bool forDarwin;
-  };
-}
-
-static bool isScale(const MachineOperand &MO) {
-  return MO.isImmediate() &&
-    (MO.getImmedValue() == 1 || MO.getImmedValue() == 2 ||
-     MO.getImmedValue() == 4 || MO.getImmedValue() == 8);
-}
-
-static bool isMem(const MachineInstr *MI, unsigned Op) {
-  if (MI->getOperand(Op).isFrameIndex()) return true;
-  if (MI->getOperand(Op).isConstantPoolIndex()) return true;
-  return Op+4 <= MI->getNumOperands() &&
-    MI->getOperand(Op  ).isRegister() && isScale(MI->getOperand(Op+1)) &&
-    MI->getOperand(Op+2).isRegister() && (MI->getOperand(Op+3).isImmediate() ||
-        MI->getOperand(Op+3).isGlobalAddress());
-}
-
-// SwitchSection - Switch to the specified section of the executable if we are
-// not already in it!
-//
-static void SwitchSection(std::ostream &OS, std::string &CurSection,
-                          const char *NewSection) {
-  if (CurSection != NewSection) {
-    CurSection = NewSection;
-    if (!CurSection.empty())
-      OS << "\t" << NewSection << "\n";
-  }
-}
-
-/// doInitialization - determine
-bool X86SharedAsmPrinter::doInitialization(Module& M) {
-  const std::string& TT = M.getTargetTriple();
-  if (TT.length() > 5) {
-    forCygwin = TT.find("cygwin") != std::string::npos ||
-                TT.find("mingw")  != std::string::npos;
-    forDarwin = TT.find("darwin") != std::string::npos;
-  } else if (TT.empty()) {
-#if defined(__CYGWIN__) || defined(__MINGW32__)
-    forCygwin = true;
-#elif defined(__MACOSX__)
-    forDarwin = true;
-#endif
-  }
-  if (forCygwin || forDarwin)
-    GlobalPrefix = "_";
-  if (forDarwin)
-    AlignmentIsInBytes = false;
-  return AsmPrinter::doInitialization(M);
-}
-
-/// printConstantPool - Print to the current output stream assembly
-/// representations of the constants in the constant pool MCP. This is
-/// used to print out constants which have been "spilled to memory" by
-/// the code generator.
-///
-void X86SharedAsmPrinter::printConstantPool(MachineConstantPool *MCP) {
-  const std::vector<Constant*> &CP = MCP->getConstants();
-  const TargetData &TD = TM.getTargetData();
-
-  if (CP.empty()) return;
-
-  for (unsigned i = 0, e = CP.size(); i != e; ++i) {
-    O << "\t.section .rodata\n";
-    emitAlignment(TD.getTypeAlignmentShift(CP[i]->getType()));
-    O << ".CPI" << CurrentFnName << "_" << i << ":\t\t\t\t\t" << CommentString
-      << *CP[i] << "\n";
-    emitGlobalConstant(CP[i]);
-  }
-}
-
-bool X86SharedAsmPrinter::doFinalization(Module &M) {
-  const TargetData &TD = TM.getTargetData();
-  std::string CurSection;
-
-  // Print out module-level global variables here.
-  for (Module::const_global_iterator I = M.global_begin(), E = M.global_end(); I != E; ++I)
-    if (I->hasInitializer()) {   // External global require no code
-      O << "\n\n";
-      std::string name = Mang->getValueName(I);
-      Constant *C = I->getInitializer();
-      unsigned Size = TD.getTypeSize(C->getType());
-      unsigned Align = TD.getTypeAlignmentShift(C->getType());
-
-      if (C->isNullValue() &&
-          (I->hasLinkOnceLinkage() || I->hasInternalLinkage() ||
-           I->hasWeakLinkage() /* FIXME: Verify correct */)) {
-        SwitchSection(O, CurSection, ".data");
-        if (!forCygwin && I->hasInternalLinkage())
-          O << "\t.local " << name << "\n";
-
-        O << "\t.comm " << name << "," << TD.getTypeSize(C->getType());
-        if (!forCygwin)
-          O << "," << (1 << Align);
-        O << "\t\t# ";
-        WriteAsOperand(O, I, true, true, &M);
-        O << "\n";
-      } else {
-        switch (I->getLinkage()) {
-        case GlobalValue::LinkOnceLinkage:
-        case GlobalValue::WeakLinkage:   // FIXME: Verify correct for weak.
-          // Nonnull linkonce -> weak
-          O << "\t.weak " << name << "\n";
-          SwitchSection(O, CurSection, "");
-          O << "\t.section\t.llvm.linkonce.d." << name << ",\"aw\", at progbits\n";
-          break;
-        case GlobalValue::AppendingLinkage:
-          // FIXME: appending linkage variables should go into a section of
-          // their name or something.  For now, just emit them as external.
-        case GlobalValue::ExternalLinkage:
-          // If external or appending, declare as a global symbol
-          O << "\t.globl " << name << "\n";
-          // FALL THROUGH
-        case GlobalValue::InternalLinkage:
-          if (C->isNullValue())
-            SwitchSection(O, CurSection, ".bss");
-          else
-            SwitchSection(O, CurSection, ".data");
-          break;
-        case GlobalValue::GhostLinkage:
-          std::cerr << "GhostLinkage cannot appear in X86AsmPrinter!\n";
-          abort();
-        }
-
-        emitAlignment(Align);
-        if (!forCygwin && !forDarwin) {
-          O << "\t.type " << name << ", at object\n";
-          O << "\t.size " << name << "," << Size << "\n";
-        }
-        O << name << ":\t\t\t\t# ";
-        WriteAsOperand(O, I, true, true, &M);
-        O << " = ";
-        WriteAsOperand(O, C, false, false, &M);
-        O << "\n";
-        emitGlobalConstant(C);
-      }
-    }
-
-  AsmPrinter::doFinalization(M);
-  return false; // success
-}
-
-namespace {
-  struct X86IntelAsmPrinter : public X86SharedAsmPrinter {
-    X86IntelAsmPrinter(std::ostream &O, TargetMachine &TM)
-      : X86SharedAsmPrinter(O, TM) { }
-
-    virtual const char *getPassName() const {
-      return "X86 Intel-Style Assembly Printer";
-    }
-
-    /// printInstruction - This method is automatically generated by tablegen
-    /// from the instruction set description.  This method returns true if the
-    /// machine instruction was sufficiently described to print it, otherwise it
-    /// returns false.
-    bool printInstruction(const MachineInstr *MI);
-
-    // This method is used by the tablegen'erated instruction printer.
-    void printOperand(const MachineInstr *MI, unsigned OpNo, MVT::ValueType VT){
-      const MachineOperand &MO = MI->getOperand(OpNo);
-      if (MO.getType() == MachineOperand::MO_MachineRegister) {
-        assert(MRegisterInfo::isPhysicalRegister(MO.getReg())&&"Not physref??");
-        // Bug Workaround: See note in Printer::doInitialization about %.
-        O << "%" << TM.getRegisterInfo()->get(MO.getReg()).Name;
-      } else {
-        printOp(MO);
-      }
-    }
-
-    void printCallOperand(const MachineInstr *MI, unsigned OpNo,
-                          MVT::ValueType VT) {
-      printOp(MI->getOperand(OpNo), true); // Don't print "OFFSET".
-    }
-
-    void printMemoryOperand(const MachineInstr *MI, unsigned OpNo,
-                            MVT::ValueType VT) {
-      switch (VT) {
-      default: assert(0 && "Unknown arg size!");
-      case MVT::i8:   O << "BYTE PTR "; break;
-      case MVT::i16:  O << "WORD PTR "; break;
-      case MVT::i32:
-      case MVT::f32:  O << "DWORD PTR "; break;
-      case MVT::i64:
-      case MVT::f64:  O << "QWORD PTR "; break;
-      case MVT::f80:  O << "XWORD PTR "; break;
-      }
-      printMemReference(MI, OpNo);
-    }
-
-    void printMachineInstruction(const MachineInstr *MI);
-    void printOp(const MachineOperand &MO, bool elideOffsetKeyword = false);
-    void printMemReference(const MachineInstr *MI, unsigned Op);
-    bool runOnMachineFunction(MachineFunction &F);
-    bool doInitialization(Module &M);
-  };
-} // end of anonymous namespace
-
-
-// Include the auto-generated portion of the assembly writer.
-#include "X86GenAsmWriter1.inc"
-
-
-/// runOnMachineFunction - This uses the printMachineInstruction()
-/// method to print assembly for each instruction.
-///
-bool X86IntelAsmPrinter::runOnMachineFunction(MachineFunction &MF) {
-  setupMachineFunction(MF);
-  O << "\n\n";
-
-  // Print out constants referenced by the function
-  printConstantPool(MF.getConstantPool());
-
-  // Print out labels for the function.
-  O << "\t.text\n";
-  emitAlignment(4);
-  O << "\t.globl\t" << CurrentFnName << "\n";
-  if (!forCygwin && !forDarwin)
-    O << "\t.type\t" << CurrentFnName << ", @function\n";
-  O << CurrentFnName << ":\n";
-
-  // Print out code for the function.
-  for (MachineFunction::const_iterator I = MF.begin(), E = MF.end();
-       I != E; ++I) {
-    // Print a label for the basic block if there are any predecessors.
-    if (I->pred_begin() != I->pred_end())
-      O << ".LBB" << CurrentFnName << "_" << I->getNumber() << ":\t"
-        << CommentString << " " << I->getBasicBlock()->getName() << "\n";
-    for (MachineBasicBlock::const_iterator II = I->begin(), E = I->end();
-         II != E; ++II) {
-      // Print the assembly for the instruction.
-      O << "\t";
-      printMachineInstruction(II);
-    }
-  }
-
-  // We didn't modify anything.
-  return false;
-}
-
-void X86IntelAsmPrinter::printOp(const MachineOperand &MO,
-                                 bool elideOffsetKeyword /* = false */) {
-  const MRegisterInfo &RI = *TM.getRegisterInfo();
-  switch (MO.getType()) {
-  case MachineOperand::MO_VirtualRegister:
-    if (Value *V = MO.getVRegValueOrNull()) {
-      O << "<" << V->getName() << ">";
-      return;
-    }
-    // FALLTHROUGH
-  case MachineOperand::MO_MachineRegister:
-    if (MRegisterInfo::isPhysicalRegister(MO.getReg()))
-      // Bug Workaround: See note in Printer::doInitialization about %.
-      O << "%" << RI.get(MO.getReg()).Name;
-    else
-      O << "%reg" << MO.getReg();
-    return;
-
-  case MachineOperand::MO_SignExtendedImmed:
-  case MachineOperand::MO_UnextendedImmed:
-    O << (int)MO.getImmedValue();
-    return;
-  case MachineOperand::MO_MachineBasicBlock: {
-    MachineBasicBlock *MBBOp = MO.getMachineBasicBlock();
-    O << ".LBB" << Mang->getValueName(MBBOp->getParent()->getFunction())
-      << "_" << MBBOp->getNumber () << '\t' << CommentString
-      << MBBOp->getBasicBlock ()->getName ();
-    return;
-  }
-  case MachineOperand::MO_PCRelativeDisp:
-    std::cerr << "Shouldn't use addPCDisp() when building X86 MachineInstrs";
-    abort ();
-    return;
-  case MachineOperand::MO_GlobalAddress: {
-    if (!elideOffsetKeyword)
-      O << "OFFSET ";
-    O << Mang->getValueName(MO.getGlobal());
-    int Offset = MO.getOffset();
-    if (Offset > 0)
-      O << " + " << Offset;
-    else if (Offset < 0)
-      O << " - " << -Offset;
-    return;
-  }
-  case MachineOperand::MO_ExternalSymbol:
-    O << GlobalPrefix << MO.getSymbolName();
-    return;
-  default:
-    O << "<unknown operand type>"; return;
-  }
-}
-
-void X86IntelAsmPrinter::printMemReference(const MachineInstr *MI, unsigned Op){
-  assert(isMem(MI, Op) && "Invalid memory reference!");
-
-  const MachineOperand &BaseReg  = MI->getOperand(Op);
-  int ScaleVal                   = MI->getOperand(Op+1).getImmedValue();
-  const MachineOperand &IndexReg = MI->getOperand(Op+2);
-  const MachineOperand &DispSpec = MI->getOperand(Op+3);
-
-  if (BaseReg.isFrameIndex()) {
-    O << "[frame slot #" << BaseReg.getFrameIndex();
-    if (DispSpec.getImmedValue())
-      O << " + " << DispSpec.getImmedValue();
-    O << "]";
-    return;
-  } else if (BaseReg.isConstantPoolIndex()) {
-    O << "[.CPI" << CurrentFnName << "_"
-      << BaseReg.getConstantPoolIndex();
-
-    if (IndexReg.getReg()) {
-      O << " + ";
-      if (ScaleVal != 1)
-        O << ScaleVal << "*";
-      printOp(IndexReg);
-    }
-
-    if (DispSpec.getImmedValue())
-      O << " + " << DispSpec.getImmedValue();
-    O << "]";
-    return;
-  }
-
-  O << "[";
-  bool NeedPlus = false;
-  if (BaseReg.getReg()) {
-    printOp(BaseReg, true);
-    NeedPlus = true;
-  }
-
-  if (IndexReg.getReg()) {
-    if (NeedPlus) O << " + ";
-    if (ScaleVal != 1)
-      O << ScaleVal << "*";
-    printOp(IndexReg);
-    NeedPlus = true;
-  }
-
-  if (DispSpec.isGlobalAddress()) {
-    if (NeedPlus)
-      O << " + ";
-    printOp(DispSpec, true);
-  } else {
-    int DispVal = DispSpec.getImmedValue();
-    if (DispVal || (!BaseReg.getReg() && !IndexReg.getReg())) {
-      if (NeedPlus)
-        if (DispVal > 0)
-          O << " + ";
-        else {
-          O << " - ";
-          DispVal = -DispVal;
-        }
-      O << DispVal;
-    }
-  }
-  O << "]";
-}
-
-
-/// printMachineInstruction -- Print out a single X86 LLVM instruction
-/// MI in Intel syntax to the current output stream.
-///
-void X86IntelAsmPrinter::printMachineInstruction(const MachineInstr *MI) {
-  ++EmittedInsts;
-
-  // Call the autogenerated instruction printer routines.
-  printInstruction(MI);
-}
-
-bool X86IntelAsmPrinter::doInitialization(Module &M) {
-  AsmPrinter::doInitialization(M);
-  // Tell gas we are outputting Intel syntax (not AT&T syntax) assembly.
-  //
-  // Bug: gas in `intel_syntax noprefix' mode interprets the symbol `Sp' in an
-  // instruction as a reference to the register named sp, and if you try to
-  // reference a symbol `Sp' (e.g. `mov ECX, OFFSET Sp') then it gets lowercased
-  // before being looked up in the symbol table. This creates spurious
-  // `undefined symbol' errors when linking. Workaround: Do not use `noprefix'
-  // mode, and decorate all register names with percent signs.
-  O << "\t.intel_syntax\n";
-  return false;
-}
-
-
-
-namespace {
-  struct X86ATTAsmPrinter : public X86SharedAsmPrinter {
-    X86ATTAsmPrinter(std::ostream &O, TargetMachine &TM)
-      : X86SharedAsmPrinter(O, TM) { }
-
-    virtual const char *getPassName() const {
-      return "X86 AT&T-Style Assembly Printer";
-    }
-
-    /// printInstruction - This method is automatically generated by tablegen
-    /// from the instruction set description.  This method returns true if the
-    /// machine instruction was sufficiently described to print it, otherwise it
-    /// returns false.
-    bool printInstruction(const MachineInstr *MI);
-
-    // This method is used by the tablegen'erated instruction printer.
-    void printOperand(const MachineInstr *MI, unsigned OpNo, MVT::ValueType VT){
-      printOp(MI->getOperand(OpNo));
-    }
-
-    void printCallOperand(const MachineInstr *MI, unsigned OpNo,
-                          MVT::ValueType VT) {
-      printOp(MI->getOperand(OpNo), true); // Don't print '$' prefix.
-    }
-
-    void printMemoryOperand(const MachineInstr *MI, unsigned OpNo,
-                            MVT::ValueType VT) {
-      printMemReference(MI, OpNo);
-    }
-
-    void printMachineInstruction(const MachineInstr *MI);
-    void printOp(const MachineOperand &MO, bool isCallOperand = false);
-    void printMemReference(const MachineInstr *MI, unsigned Op);
-    bool runOnMachineFunction(MachineFunction &F);
-  };
-} // end of anonymous namespace
-
-
-// Include the auto-generated portion of the assembly writer.
-#include "X86GenAsmWriter.inc"
-
-
-/// runOnMachineFunction - This uses the printMachineInstruction()
-/// method to print assembly for each instruction.
-///
-bool X86ATTAsmPrinter::runOnMachineFunction(MachineFunction &MF) {
-  setupMachineFunction(MF);
-  O << "\n\n";
-
-  // Print out constants referenced by the function
-  printConstantPool(MF.getConstantPool());
-
-  // Print out labels for the function.
-  O << "\t.text\n";
-  emitAlignment(4);
-  O << "\t.globl\t" << CurrentFnName << "\n";
-  if (!forCygwin && !forDarwin)
-    O << "\t.type\t" << CurrentFnName << ", @function\n";
-  O << CurrentFnName << ":\n";
-
-  // Print out code for the function.
-  for (MachineFunction::const_iterator I = MF.begin(), E = MF.end();
-       I != E; ++I) {
-    // Print a label for the basic block.
-    if (I->pred_begin() != I->pred_end())
-      O << ".LBB" << CurrentFnName << "_" << I->getNumber() << ":\t"
-        << CommentString << " " << I->getBasicBlock()->getName() << "\n";
-    for (MachineBasicBlock::const_iterator II = I->begin(), E = I->end();
-         II != E; ++II) {
-      // Print the assembly for the instruction.
-      O << "\t";
-      printMachineInstruction(II);
-    }
-  }
-
-  // We didn't modify anything.
-  return false;
-}
-
-void X86ATTAsmPrinter::printOp(const MachineOperand &MO, bool isCallOp) {
-  const MRegisterInfo &RI = *TM.getRegisterInfo();
-  switch (MO.getType()) {
-  case MachineOperand::MO_VirtualRegister:
-  case MachineOperand::MO_MachineRegister:
-    assert(MRegisterInfo::isPhysicalRegister(MO.getReg()) &&
-           "Virtual registers should not make it this far!");
-    O << '%';
-    for (const char *Name = RI.get(MO.getReg()).Name; *Name; ++Name)
-      O << (char)tolower(*Name);
-    return;
-
-  case MachineOperand::MO_SignExtendedImmed:
-  case MachineOperand::MO_UnextendedImmed:
-    O << '$' << (int)MO.getImmedValue();
-    return;
-  case MachineOperand::MO_MachineBasicBlock: {
-    MachineBasicBlock *MBBOp = MO.getMachineBasicBlock();
-    O << ".LBB" << Mang->getValueName(MBBOp->getParent()->getFunction())
-      << "_" << MBBOp->getNumber () << '\t' << CommentString
-      << MBBOp->getBasicBlock ()->getName ();
-    return;
-  }
-  case MachineOperand::MO_PCRelativeDisp:
-    std::cerr << "Shouldn't use addPCDisp() when building X86 MachineInstrs";
-    abort ();
-    return;
-  case MachineOperand::MO_GlobalAddress: {
-    if (!isCallOp) O << '$';
-    O << Mang->getValueName(MO.getGlobal());
-    int Offset = MO.getOffset();
-    if (Offset > 0)
-      O << "+" << Offset;
-    else if (Offset < 0)
-      O << Offset;
-    return;
-  }
-  case MachineOperand::MO_ExternalSymbol:
-    if (!isCallOp) O << '$';
-    O << GlobalPrefix << MO.getSymbolName();
-    return;
-  default:
-    O << "<unknown operand type>"; return;
-  }
-}
-
-void X86ATTAsmPrinter::printMemReference(const MachineInstr *MI, unsigned Op){
-  assert(isMem(MI, Op) && "Invalid memory reference!");
-
-  const MachineOperand &BaseReg  = MI->getOperand(Op);
-  int ScaleVal                   = MI->getOperand(Op+1).getImmedValue();
-  const MachineOperand &IndexReg = MI->getOperand(Op+2);
-  const MachineOperand &DispSpec = MI->getOperand(Op+3);
-
-  if (BaseReg.isFrameIndex()) {
-    O << "[frame slot #" << BaseReg.getFrameIndex();
-    if (DispSpec.getImmedValue())
-      O << " + " << DispSpec.getImmedValue();
-    O << "]";
-    return;
-  } else if (BaseReg.isConstantPoolIndex()) {
-    O << ".CPI" << CurrentFnName << "_"
-      << BaseReg.getConstantPoolIndex();
-    if (DispSpec.getImmedValue())
-      O << "+" << DispSpec.getImmedValue();
-    if (IndexReg.getReg()) {
-      O << "(,";
-      printOp(IndexReg);
-      if (ScaleVal != 1)
-        O << "," << ScaleVal;
-      O << ")";
-    }
-    return;
-  }
-
-  if (DispSpec.isGlobalAddress()) {
-    printOp(DispSpec, true);
-  } else {
-    int DispVal = DispSpec.getImmedValue();
-    if (DispVal || (!IndexReg.getReg() && !BaseReg.getReg()))
-      O << DispVal;
-  }
-
-  if (IndexReg.getReg() || BaseReg.getReg()) {
-    O << "(";
-    if (BaseReg.getReg())
-      printOp(BaseReg);
-
-    if (IndexReg.getReg()) {
-      O << ",";
-      printOp(IndexReg);
-      if (ScaleVal != 1)
-        O << "," << ScaleVal;
-    }
-
-    O << ")";
-  }
-}
-
-
-/// printMachineInstruction -- Print out a single X86 LLVM instruction
-/// MI in Intel syntax to the current output stream.
-///
-void X86ATTAsmPrinter::printMachineInstruction(const MachineInstr *MI) {
-  ++EmittedInsts;
-  // Call the autogenerated instruction printer routines.
-  printInstruction(MI);
-}
-
-
-/// createX86CodePrinterPass - Returns a pass that prints the X86 assembly code
-/// for a MachineFunction to the given output stream, using the given target
-/// machine description.
-///
-FunctionPass *llvm::createX86CodePrinterPass(std::ostream &o,TargetMachine &tm){
-  switch (AsmWriterFlavor) {
-  default:
-    assert(0 && "Unknown asm flavor!");
-  case intel:
-    return new X86IntelAsmPrinter(o, tm);
-  case att:
-    return new X86ATTAsmPrinter(o, tm);
-  }
-}
+//===-- X86AsmPrinter.cpp - Convert X86 LLVM IR to X86 assembly -----------===//
+//
+//                     The LLVM Compiler Infrastructure
+//
+// This file was developed by the LLVM research group and is distributed under
+// the University of Illinois Open Source License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+//
+// This file the shared super class printer that converts from our internal
+// representation of machine-dependent LLVM code to Intel and AT&T format
+// assembly language.
+// This printer is the output mechanism used by `llc'.
+//
+//===----------------------------------------------------------------------===//
+
+#include "X86ATTAsmPrinter.h"
+#include "X86IntelAsmPrinter.h"
+#include "X86.h"
+#include "llvm/Module.h"
+#include "llvm/Assembly/Writer.h"
+#include "llvm/CodeGen/MachineConstantPool.h"
+#include "llvm/Support/Mangler.h"
+#include "llvm/Support/CommandLine.h"
+using namespace llvm;
+using namespace x86;
+
+Statistic<> EmittedInsts("asm-printer", "Number of machine instrs printed");
+
+enum AsmWriterFlavorTy { att, intel };
+cl::opt<AsmWriterFlavorTy>
+AsmWriterFlavor("x86-asm-syntax",
+	cl::desc("Choose style of code to emit from X86 backend:"),
+	cl::values(
+				clEnumVal(att,   "  Emit AT&T-style assembly"),
+				clEnumVal(intel, "  Emit Intel-style assembly"),
+				clEnumValEnd),
+	cl::init(att));
+
+/// doInitialization
+bool X86SharedAsmPrinter::doInitialization(Module& M) {
+  bool leadingUnderscore = false;
+  forCygwin = false;
+  const std::string& TT = M.getTargetTriple();
+  if (TT.length() > 5) {
+    forCygwin = TT.find("cygwin") != std::string::npos ||
+                TT.find("mingw")  != std::string::npos;
+    forDarwin = TT.find("darwin") != std::string::npos;
+  } else if (TT.empty()) {
+  #if defined(__CYGWIN__) || defined(__MINGW32__)
+    forCygwin = true;
+  #elif defined(__MACOSX__)
+    forDarwin = true;
+  #elif defined(_WIN32)
+    leadingUnderscore = true;
+  #else
+    leadingUnderscore = false;
+  #endif
+  }
+  if (leadingUnderscore || forCygwin || forDarwin)
+    GlobalPrefix = "_";
+
+  if (forDarwin)
+    AlignmentIsInBytes = false;
+
+  return AsmPrinter::doInitialization(M);
+}
+
+/// printConstantPool - Print to the current output stream assembly
+/// representations of the constants in the constant pool MCP. This is
+/// used to print out constants which have been "spilled to memory" by
+/// the code generator.
+///
+void X86SharedAsmPrinter::printConstantPool(MachineConstantPool *MCP) {
+  const std::vector<Constant*> &CP = MCP->getConstants();
+  const TargetData &TD = TM.getTargetData();
+
+  if (CP.empty()) return;
+
+  for (unsigned i = 0, e = CP.size(); i != e; ++i) {
+    O << "\t.section .rodata\n";
+    emitAlignment(TD.getTypeAlignmentShift(CP[i]->getType()));
+    O << ".CPI" << CurrentFnName << "_" << i << ":\t\t\t\t\t" << CommentString
+      << *CP[i] << "\n";
+    emitGlobalConstant(CP[i]);
+  }
+}
+
+bool X86SharedAsmPrinter::doFinalization(Module &M) {
+  const TargetData &TD = TM.getTargetData();
+  std::string CurSection;
+
+  // Print out module-level global variables here.
+  for (Module::const_global_iterator I = M.global_begin(), E = M.global_end(); I != E; ++I)
+  	if (I->hasInitializer()) {   // External global require no code
+  	  O << "\n\n";
+  	  std::string name = Mang->getValueName(I);
+  	  Constant *C = I->getInitializer();
+  	  unsigned Size = TD.getTypeSize(C->getType());
+  	  unsigned Align = TD.getTypeAlignmentShift(C->getType());
+
+  	  if (C->isNullValue() &&
+  		(I->hasLinkOnceLinkage() || I->hasInternalLinkage() ||
+  			I->hasWeakLinkage() /* FIXME: Verify correct */)) {
+  		SwitchSection(O, CurSection, ".data");
+  		if (!forCygwin && I->hasInternalLinkage())
+  		  O << "\t.local " << name << "\n";
+  		O << "\t.comm " << name << "," << TD.getTypeSize(C->getType());
+  		if (!forCygwin)
+  		  O << "," << (1 << Align);
+  		O << "\t\t# ";
+  		WriteAsOperand(O, I, true, true, &M);
+  		O << "\n";
+  	  } else {
+  		switch (I->getLinkage()) {
+  		case GlobalValue::LinkOnceLinkage:
+  		case GlobalValue::WeakLinkage:   // FIXME: Verify correct for weak.
+  		  // Nonnull linkonce -> weak
+  		  O << "\t.weak " << name << "\n";
+  		  SwitchSection(O, CurSection, "");
+  		  O << "\t.section\t.llvm.linkonce.d." << name << ",\"aw\", at progbits\n";
+  		  break;
+  		case GlobalValue::AppendingLinkage:
+  		  // FIXME: appending linkage variables should go into a section of
+  		  // their name or something.  For now, just emit them as external.
+  		case GlobalValue::ExternalLinkage:
+  		  // If external or appending, declare as a global symbol
+  		  O << "\t.globl " << name << "\n";
+  		  // FALL THROUGH
+  		case GlobalValue::InternalLinkage:
+  		  if (C->isNullValue())
+  		    SwitchSection(O, CurSection, ".bss");
+  		  else
+  		    SwitchSection(O, CurSection, ".data");
+  		  break;
+  		case GlobalValue::GhostLinkage:
+  		  std::cerr << "GhostLinkage cannot appear in X86AsmPrinter!\n";
+  		  abort();
+  		}
+
+  		emitAlignment(Align);
+  		if (!forCygwin && !forDarwin) {
+  		  O << "\t.type " << name << ", at object\n";
+  		  O << "\t.size " << name << "," << Size << "\n";
+  		}
+  		O << name << ":\t\t\t\t# ";
+  		WriteAsOperand(O, I, true, true, &M);
+  		O << " = ";
+  		WriteAsOperand(O, C, false, false, &M);
+  		O << "\n";
+  		emitGlobalConstant(C);
+  	  }
+    }
+
+  AsmPrinter::doFinalization(M);
+  return false; // success
+}
+
+/// createX86CodePrinterPass - Returns a pass that prints the X86 assembly code
+/// for a MachineFunction to the given output stream, using the given target
+/// machine description.
+///
+FunctionPass *llvm::createX86CodePrinterPass(std::ostream &o,TargetMachine &tm){
+  switch (AsmWriterFlavor) {
+  default:
+    assert(0 && "Unknown asm flavor!");
+  case intel:
+    return new X86IntelAsmPrinter(o, tm);
+  case att:
+    return new X86ATTAsmPrinter(o, tm);
+  }
+}





From lattner at cs.uiuc.edu  Fri Jul  1 18:10:54 2005
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Fri, 1 Jul 2005 18:10:54 -0500
Subject: [llvm-commits] 
	CVS: llvm-test/MultiSource/Benchmarks/Prolangs-C/unix-tbl/t1.c
Message-ID: <200507012310.SAA06194@zion.cs.uiuc.edu>



Changes in directory llvm-test/MultiSource/Benchmarks/Prolangs-C/unix-tbl:

t1.c updated: 1.1 -> 1.2
---
Log message:

Make this work with Mac OS/X


---
Diffs of the changes:  (+0 -2)

 t1.c |    2 --
 1 files changed, 2 deletions(-)


Index: llvm-test/MultiSource/Benchmarks/Prolangs-C/unix-tbl/t1.c
diff -u llvm-test/MultiSource/Benchmarks/Prolangs-C/unix-tbl/t1.c:1.1 llvm-test/MultiSource/Benchmarks/Prolangs-C/unix-tbl/t1.c:1.2
--- llvm-test/MultiSource/Benchmarks/Prolangs-C/unix-tbl/t1.c:1.1	Tue Oct  5 16:26:49 2004
+++ llvm-test/MultiSource/Benchmarks/Prolangs-C/unix-tbl/t1.c	Fri Jul  1 18:10:43 2005
@@ -12,10 +12,8 @@
 extern FILE *_f[];
 # endif
 
-# ifdef unix
 # define MACROS "/usr/lib/tmac.s"
 # define PYMACS "/usr/lib/tmac.m"
-# endif
 
 # ifdef gcos
 # define MACROS "cc/troff/smac"





From lattner at cs.uiuc.edu  Fri Jul  1 18:12:07 2005
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Fri, 1 Jul 2005 18:12:07 -0500
Subject: [llvm-commits] CVS: llvm/lib/Target/PowerPC/PPC32ISelPattern.cpp 
Message-ID: <200507012312.SAA06291@zion.cs.uiuc.edu>



Changes in directory llvm/lib/Target/PowerPC:

PPC32ISelPattern.cpp updated: 1.94 -> 1.95
---
Log message:

Varargs is apparently currently broken on PPC.  This hacks it so that it 
is at least overloading the right virtual methods.  The implementations
are currently wrong though.  This fixes Ptrdist/bc, but not other programs
(e.g. siod).


---
Diffs of the changes:  (+9 -4)

 PPC32ISelPattern.cpp |   13 +++++++++----
 1 files changed, 9 insertions(+), 4 deletions(-)


Index: llvm/lib/Target/PowerPC/PPC32ISelPattern.cpp
diff -u llvm/lib/Target/PowerPC/PPC32ISelPattern.cpp:1.94 llvm/lib/Target/PowerPC/PPC32ISelPattern.cpp:1.95
--- llvm/lib/Target/PowerPC/PPC32ISelPattern.cpp:1.94	Wed Jun 15 13:22:43 2005
+++ llvm/lib/Target/PowerPC/PPC32ISelPattern.cpp	Fri Jul  1 18:11:56 2005
@@ -98,10 +98,10 @@
                 SelectionDAG &DAG);
 
     virtual std::pair<SDOperand, SDOperand>
-    LowerVAStart(SDOperand Chain, SelectionDAG &DAG);
+    LowerVAStart(SDOperand Chain, SelectionDAG &DAG, SDOperand Dest);
 
     virtual std::pair<SDOperand,SDOperand>
-    LowerVAArgNext(bool isVANext, SDOperand Chain, SDOperand VAList,
+    LowerVAArgNext(SDOperand Chain, SDOperand VAList,
                    const Type *ArgTy, SelectionDAG &DAG);
 
     virtual std::pair<SDOperand, SDOperand>
@@ -464,14 +464,19 @@
 }
 
 std::pair<SDOperand, SDOperand>
-PPC32TargetLowering::LowerVAStart(SDOperand Chain, SelectionDAG &DAG) {
+PPC32TargetLowering::LowerVAStart(SDOperand Chain, SelectionDAG &DAG, SDOperand Dest) {
   //vastart just returns the address of the VarArgsFrameIndex slot.
   return std::make_pair(DAG.getFrameIndex(VarArgsFrameIndex, MVT::i32), Chain);
 }
 
 std::pair<SDOperand,SDOperand> PPC32TargetLowering::
-LowerVAArgNext(bool isVANext, SDOperand Chain, SDOperand VAList,
+LowerVAArgNext(SDOperand Chain, SDOperand VAList,
                const Type *ArgTy, SelectionDAG &DAG) {
+  // FIXME: THIS IS BROKEN!!!
+
+  bool isVANext = true;
+  
+  
   MVT::ValueType ArgVT = getValueType(ArgTy);
   SDOperand Result;
   if (!isVANext) {





From natebegeman at mac.com  Fri Jul  1 18:56:49 2005
From: natebegeman at mac.com (Nate Begeman)
Date: Fri, 1 Jul 2005 18:56:49 -0500
Subject: [llvm-commits] CVS: llvm/lib/Target/X86/X86AsmPrinter.cpp 
Message-ID: <200507012356.SAA07905@zion.cs.uiuc.edu>



Changes in directory llvm/lib/Target/X86:

X86AsmPrinter.cpp updated: 1.139 -> 1.140
---
Log message:

The statistic needs to be in the correct namespace.


---
Diffs of the changes:  (+2 -1)

 X86AsmPrinter.cpp |    3 ++-
 1 files changed, 2 insertions(+), 1 deletion(-)


Index: llvm/lib/Target/X86/X86AsmPrinter.cpp
diff -u llvm/lib/Target/X86/X86AsmPrinter.cpp:1.139 llvm/lib/Target/X86/X86AsmPrinter.cpp:1.140
--- llvm/lib/Target/X86/X86AsmPrinter.cpp:1.139	Fri Jul  1 17:44:09 2005
+++ llvm/lib/Target/X86/X86AsmPrinter.cpp	Fri Jul  1 18:56:38 2005
@@ -25,7 +25,8 @@
 using namespace llvm;
 using namespace x86;
 
-Statistic<> EmittedInsts("asm-printer", "Number of machine instrs printed");
+Statistic<> llvm::x86::EmittedInsts("asm-printer", 
+                                    "Number of machine instrs printed");
 
 enum AsmWriterFlavorTy { att, intel };
 cl::opt<AsmWriterFlavorTy>





From jeffc at jolt-lang.org  Fri Jul  1 21:04:37 2005
From: jeffc at jolt-lang.org (Jeff Cohen)
Date: Fri, 1 Jul 2005 21:04:37 -0500
Subject: [llvm-commits] CVS: llvm/win32/x86/x86.vcproj 
Message-ID: <200507020204.VAA26745@zion.cs.uiuc.edu>



Changes in directory llvm/win32/x86:

x86.vcproj updated: 1.11 -> 1.12
---
Log message:

Adding new files to Visual Studio projects.

---
Diffs of the changes:  (+12 -0)

 x86.vcproj |   12 ++++++++++++
 1 files changed, 12 insertions(+)


Index: llvm/win32/x86/x86.vcproj
diff -u llvm/win32/x86/x86.vcproj:1.11 llvm/win32/x86/x86.vcproj:1.12
--- llvm/win32/x86/x86.vcproj:1.11	Mon Jun 27 21:43:03 2005
+++ llvm/win32/x86/x86.vcproj	Fri Jul  1 21:04:26 2005
@@ -146,6 +146,9 @@
 				RelativePath="..\..\lib\Target\X86\X86AsmPrinter.cpp">
 			</File>
 			<File
+				RelativePath="..\..\lib\Target\X86\X86ATTAsmPrinter.cpp">
+			</File>
+			<File
 				RelativePath="..\..\lib\Target\X86\X86CodeEmitter.cpp">
 			</File>
 			<File
@@ -158,6 +161,9 @@
 				RelativePath="..\..\lib\Target\X86\X86InstrInfo.cpp">
 			</File>
 			<File
+				RelativePath="..\..\lib\Target\X86\X86IntelAsmPrinter.cpp">
+			</File>
+			<File
 				RelativePath="..\..\lib\Target\X86\X86ISelPattern.cpp">
 			</File>
 			<File
@@ -187,6 +193,9 @@
 				RelativePath="..\..\lib\Target\X86\X86.h">
 			</File>
 			<File
+				RelativePath="..\..\lib\Target\X86\X86ATTAsmPrinter.h">
+			</File>
+			<File
 				RelativePath="..\..\lib\Target\X86\X86InstrBuilder.h">
 			</File>
 			<File
@@ -196,6 +205,9 @@
 				RelativePath="..\..\lib\Target\X86\X86InstrInfo.td">
 			</File>
 			<File
+				RelativePath="..\..\lib\Target\X86\X86IntelAsmPrinter.h">
+			</File>
+			<File
 				RelativePath="..\..\lib\Target\X86\X86JITInfo.h">
 			</File>
 			<File





From alenhar2 at cs.uiuc.edu  Sat Jul  2 15:59:07 2005
From: alenhar2 at cs.uiuc.edu (Andrew Lenharth)
Date: Sat, 2 Jul 2005 15:59:07 -0500
Subject: [llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp 
Message-ID: <200507022059.PAA03071@zion.cs.uiuc.edu>



Changes in directory llvm/lib/CodeGen/SelectionDAG:

LegalizeDAG.cpp updated: 1.133 -> 1.134
---
Log message:

I really didn't think this was necessary.  But, Legalize wasn't running again
and legalizing the extload.  Strange.  Should fix most alpha regressions.



---
Diffs of the changes:  (+3 -2)

 LegalizeDAG.cpp |    5 +++--
 1 files changed, 3 insertions(+), 2 deletions(-)


Index: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.133 llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.134
--- llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.133	Thu Jun 30 14:32:57 2005
+++ llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp	Sat Jul  2 15:58:53 2005
@@ -1351,8 +1351,9 @@
                                    DAG.getSrcValue(NULL));
         else {
           assert(Node->getValueType(0) == MVT::f64 && "Unexpected conversion");
-          FudgeInReg = DAG.getNode(ISD::EXTLOAD, MVT::f64, DAG.getEntryNode(),
-                                   CPIdx, DAG.getSrcValue(NULL), MVT::f32);
+          FudgeInReg = 
+            LegalizeOp(DAG.getNode(ISD::EXTLOAD, MVT::f64, DAG.getEntryNode(),
+                                   CPIdx, DAG.getSrcValue(NULL), MVT::f32));
         }
         Result = DAG.getNode(ISD::ADD, Node->getValueType(0), Tmp1, FudgeInReg);
         break;





From lattner at cs.uiuc.edu  Sun Jul  3 12:34:50 2005
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Sun, 3 Jul 2005 12:34:50 -0500
Subject: [llvm-commits] CVS: llvm/lib/Target/X86/X86IntelAsmPrinter.cpp 
Message-ID: <200507031734.MAA09958@zion.cs.uiuc.edu>



Changes in directory llvm/lib/Target/X86:

X86IntelAsmPrinter.cpp updated: 1.1 -> 1.2
---
Log message:

Percolate the call up to the right superclass


---
Diffs of the changes:  (+1 -1)

 X86IntelAsmPrinter.cpp |    2 +-
 1 files changed, 1 insertion(+), 1 deletion(-)


Index: llvm/lib/Target/X86/X86IntelAsmPrinter.cpp
diff -u llvm/lib/Target/X86/X86IntelAsmPrinter.cpp:1.1 llvm/lib/Target/X86/X86IntelAsmPrinter.cpp:1.2
--- llvm/lib/Target/X86/X86IntelAsmPrinter.cpp:1.1	Fri Jul  1 17:44:09 2005
+++ llvm/lib/Target/X86/X86IntelAsmPrinter.cpp	Sun Jul  3 12:34:39 2005
@@ -188,7 +188,7 @@
 }
 
 bool X86IntelAsmPrinter::doInitialization(Module &M) {
-  AsmPrinter::doInitialization(M);
+  X86SharedAsmPrinter::doInitialization(M);
   // Tell gas we are outputting Intel syntax (not AT&T syntax) assembly.
   //
   // Bug: gas in `intel_syntax noprefix' mode interprets the symbol `Sp' in an





From alenhar2 at cs.uiuc.edu  Sun Jul  3 15:06:25 2005
From: alenhar2 at cs.uiuc.edu (Andrew Lenharth)
Date: Sun, 3 Jul 2005 15:06:25 -0500
Subject: [llvm-commits] CVS: llvm/lib/Target/Alpha/AlphaISelPattern.cpp 
Message-ID: <200507032006.PAA10507@zion.cs.uiuc.edu>



Changes in directory llvm/lib/Target/Alpha:

AlphaISelPattern.cpp updated: 1.144 -> 1.145
---
Log message:

fix loading address of fp symbols


---
Diffs of the changes:  (+4 -0)

 AlphaISelPattern.cpp |    4 ++++
 1 files changed, 4 insertions(+)


Index: llvm/lib/Target/Alpha/AlphaISelPattern.cpp
diff -u llvm/lib/Target/Alpha/AlphaISelPattern.cpp:1.144 llvm/lib/Target/Alpha/AlphaISelPattern.cpp:1.145
--- llvm/lib/Target/Alpha/AlphaISelPattern.cpp:1.144	Fri Jul  1 14:12:13 2005
+++ llvm/lib/Target/Alpha/AlphaISelPattern.cpp	Sun Jul  3 15:06:13 2005
@@ -1319,6 +1319,8 @@
   case ISD::GlobalAddress:
     AlphaLowering.restoreGP(BB);
     has_sym = true;
+ 
+    Reg = Result = MakeReg(MVT::i64);
 
     if (EnableAlphaLSMark)
       BuildMI(BB, Alpha::MEMLABEL, 4).addImm(5).addImm(0).addImm(0)
@@ -1333,6 +1335,8 @@
     AlphaLowering.restoreGP(BB);
     has_sym = true;
 
+    Reg = Result = MakeReg(MVT::i64);
+
     if (EnableAlphaLSMark)
       BuildMI(BB, Alpha::MEMLABEL, 4).addImm(5).addImm(0).addImm(0)
         .addImm(getUID());