[llvm-commits] CVS: llvm/lib/Target/Alpha/AlphaISelPattern.cpp AlphaRegisterInfo.td

Andrew Lenharth alenhar2 at cs.uiuc.edu
Mon Jun 27 10:36:59 CDT 2005



Changes in directory llvm/lib/Target/Alpha:

AlphaISelPattern.cpp updated: 1.129 -> 1.130
AlphaRegisterInfo.td updated: 1.9 -> 1.10
---
Log message:

who said we had to use the return address in the return address register.  Might save a move in many cases

---
Diffs of the changes:  (+8 -5)

 AlphaISelPattern.cpp |    7 +++++--
 AlphaRegisterInfo.td |    6 +++---
 2 files changed, 8 insertions(+), 5 deletions(-)


Index: llvm/lib/Target/Alpha/AlphaISelPattern.cpp
diff -u llvm/lib/Target/Alpha/AlphaISelPattern.cpp:1.129 llvm/lib/Target/Alpha/AlphaISelPattern.cpp:1.130
--- llvm/lib/Target/Alpha/AlphaISelPattern.cpp:1.129	Sun Jun 26 18:01:11 2005
+++ llvm/lib/Target/Alpha/AlphaISelPattern.cpp	Mon Jun 27 10:36:48 2005
@@ -179,6 +179,10 @@
     {
       BuildMI(BB, Alpha::BIS, 2, Alpha::R26).addReg(RA).addReg(RA);
     }
+    unsigned getRA()
+    {
+      return RA;
+    }
 
   };
 }
@@ -2310,8 +2314,7 @@
       Select(N.getOperand(0));
       break;
     }
-    AlphaLowering.restoreRA(BB);
-    BuildMI(BB, Alpha::RET, 1, Alpha::R31).addReg(Alpha::R26); // Just emit a 'ret' instruction
+    BuildMI(BB, Alpha::RET, 1, Alpha::R31).addReg(AlphaLowering.getRA()); // Just emit a 'ret' instruction
     return;
 
   case ISD::TRUNCSTORE:


Index: llvm/lib/Target/Alpha/AlphaRegisterInfo.td
diff -u llvm/lib/Target/Alpha/AlphaRegisterInfo.td:1.9 llvm/lib/Target/Alpha/AlphaRegisterInfo.td:1.10
--- llvm/lib/Target/Alpha/AlphaRegisterInfo.td:1.9	Thu Feb 10 00:25:22 2005
+++ llvm/lib/Target/Alpha/AlphaRegisterInfo.td	Mon Jun 27 10:36:48 2005
@@ -78,14 +78,14 @@
   // $28 is undefined after any and all calls
 
 /// Register classes
+// Don't allocate 15, 28, 30, 31
 def GPRC : RegisterClass<i64, 64,
      // Volatile
      [R0, R1, R2, R3, R4, R5, R6, R7, R8, R16, R17, R18, R19, R20, R21, R22,
-      R23, R24, R25, R27,
+      R23, R24, R25, R26, R27,
      // Non-volatile
-     R9, R10, R11, R12, R13, R14, /*R15,*/ R26, /* R28, */ R29 /* R30, R31*/ ]>;
+     R9, R10, R11, R12, R13, R14, R29 ]>;
      // Note: R28 is reserved for the assembler
-     //leave FP alone
 
 // Don't allocate 15, 29, 30, 31
 // Allocation volatiles only for now






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