From lattner at cs.uiuc.edu  Mon Jul 18 18:07:44 2005
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Mon, 18 Jul 2005 18:07:44 -0500
Subject: [llvm-commits] 
	CVS: llvm/lib/Transforms/Scalar/InstructionCombining.cpp
Message-ID: <200507182307.SAA29750@zion.cs.uiuc.edu>



Changes in directory llvm/lib/Transforms/Scalar:

InstructionCombining.cpp updated: 1.357 -> 1.358
---
Log message:

When transforming &A[i] < &A[j]  ->  i < j, make sure to perform the comparison
as a signed compare.  This patch may fix PR597: http://llvm.cs.uiuc.edu/PR597 , but is correct in any case.



---
Diffs of the changes:  (+11 -4)

 InstructionCombining.cpp |   15 +++++++++++----
 1 files changed, 11 insertions(+), 4 deletions(-)


Index: llvm/lib/Transforms/Scalar/InstructionCombining.cpp
diff -u llvm/lib/Transforms/Scalar/InstructionCombining.cpp:1.357 llvm/lib/Transforms/Scalar/InstructionCombining.cpp:1.358
--- llvm/lib/Transforms/Scalar/InstructionCombining.cpp:1.357	Thu Jul  7 15:40:38 2005
+++ llvm/lib/Transforms/Scalar/InstructionCombining.cpp	Mon Jul 18 18:07:33 2005
@@ -2367,10 +2367,17 @@
       else if (NumDifferences == 1) {
         Value *LHSV = GEPLHS->getOperand(DiffOperand);
         Value *RHSV = GEPRHS->getOperand(DiffOperand);
-        if (LHSV->getType() != RHSV->getType())
-          LHSV = InsertNewInstBefore(new CastInst(LHSV, RHSV->getType(),
-                                                  LHSV->getName()+".c"), I);
-          return new SetCondInst(Cond, LHSV, RHSV);
+
+        // Convert the operands to signed values to make sure to perform a
+        // signed comparison.
+        const Type *NewTy = LHSV->getType()->getSignedVersion();
+        if (LHSV->getType() != NewTy)
+          LHSV = InsertNewInstBefore(new CastInst(LHSV, NewTy,
+                                                  LHSV->getName()), I);
+        if (RHSV->getType() != NewTy)
+          RHSV = InsertNewInstBefore(new CastInst(RHSV, NewTy,
+                                                  RHSV->getName()), I);
+        return new SetCondInst(Cond, LHSV, RHSV);
       }
     }
 





From reid at x10sys.com  Mon Jul 18 20:36:47 2005
From: reid at x10sys.com (Reid Spencer)
Date: Mon, 18 Jul 2005 20:36:47 -0500
Subject: [llvm-commits] CVS: llvm/docs/CodeGenerator.html 
Message-ID: <200507190136.UAA32763@zion.cs.uiuc.edu>



Changes in directory llvm/docs:

CodeGenerator.html updated: 1.15 -> 1.16
---
Log message:

Provide descriptions for the TargetInstrInfo and TargetFrameInfo classes.


---
Diffs of the changes:  (+21 -1)

 CodeGenerator.html |   22 +++++++++++++++++++++-
 1 files changed, 21 insertions(+), 1 deletion(-)


Index: llvm/docs/CodeGenerator.html
diff -u llvm/docs/CodeGenerator.html:1.15 llvm/docs/CodeGenerator.html:1.16
--- llvm/docs/CodeGenerator.html:1.15	Mon Jul 11 19:20:49 2005
+++ llvm/docs/CodeGenerator.html	Mon Jul 18 20:36:35 2005
@@ -383,11 +383,31 @@
   <a name="targetinstrinfo">The <tt>TargetInstrInfo</tt> class</a>
 </div>
 
+<div class="doc_text">
+  <p>The <tt>TargetInstrInfo</tt> class is used to describe the machine 
+  instructions supported by the target. It is essentially an array of 
+  <tt>TargetInstrDescriptor</tt> objects, each of which describes one
+  instruction the target supports. Descriptors define things like the mnemonic
+  for the opcode, the number of operands, the size of the largets immediate
+  field the instruction can contain, the latency of the instruction in machine
+  cycles, etc.</p>
+</div>
+
 <!-- ======================================================================= -->
 <div class="doc_subsection">
   <a name="targetframeinfo">The <tt>TargetFrameInfo</tt> class</a>
 </div>
 
+<div class="doc_text">
+  <p>The <tt>TargetFrameInfo</tt> class is used to provide information about the
+  stack frame layout of the target. It holds the direction of stack growth, 
+  the known stack alignment on entry to each function, and the offset to the 
+  locals area.  The offset to the local area is the offset from the stack 
+  pointer on function entry to the first location where function data (local 
+  variables, spill locations) can be stored.</p>
+  <p>The class also provides several functions for computing alignment and
+  offsets for various situations.</p>
+</div>
 <!-- ======================================================================= -->
 <div class="doc_subsection">
   <a name="targetjitinfo">The <tt>TargetJITInfo</tt> class</a>
@@ -1014,7 +1034,7 @@
 
   <a href="mailto:sabre at nondot.org">Chris Lattner</a><br>
   <a href="http://llvm.cs.uiuc.edu">The LLVM Compiler Infrastructure</a><br>
-  Last modified: $Date: 2005/07/12 00:20:49 $
+  Last modified: $Date: 2005/07/19 01:36:35 $
 </address>
 
 </body>





From lattner at cs.uiuc.edu  Mon Jul 18 22:37:59 2005
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Mon, 18 Jul 2005 22:37:59 -0500
Subject: [llvm-commits] CVS: llvm/docs/CodeGenerator.html 
Message-ID: <200507190337.WAA00901@zion.cs.uiuc.edu>



Changes in directory llvm/docs:

CodeGenerator.html updated: 1.16 -> 1.17
---
Log message:

remove some sparc-v9-specific information


---
Diffs of the changes:  (+4 -6)

 CodeGenerator.html |   10 ++++------
 1 files changed, 4 insertions(+), 6 deletions(-)


Index: llvm/docs/CodeGenerator.html
diff -u llvm/docs/CodeGenerator.html:1.16 llvm/docs/CodeGenerator.html:1.17
--- llvm/docs/CodeGenerator.html:1.16	Mon Jul 18 20:36:35 2005
+++ llvm/docs/CodeGenerator.html	Mon Jul 18 22:37:48 2005
@@ -388,9 +388,9 @@
   instructions supported by the target. It is essentially an array of 
   <tt>TargetInstrDescriptor</tt> objects, each of which describes one
   instruction the target supports. Descriptors define things like the mnemonic
-  for the opcode, the number of operands, the size of the largets immediate
-  field the instruction can contain, the latency of the instruction in machine
-  cycles, etc.</p>
+  for the opcode, the number of operands, the list of implicit register uses
+  and defs, whether the instruction has certain target-independent properties 
+  (accesses memory, is commutable, etc), and holds any target-specific flags.</p>
 </div>
 
 <!-- ======================================================================= -->
@@ -405,8 +405,6 @@
   locals area.  The offset to the local area is the offset from the stack 
   pointer on function entry to the first location where function data (local 
   variables, spill locations) can be stored.</p>
-  <p>The class also provides several functions for computing alignment and
-  offsets for various situations.</p>
 </div>
 <!-- ======================================================================= -->
 <div class="doc_subsection">
@@ -1034,7 +1032,7 @@
 
   <a href="mailto:sabre at nondot.org">Chris Lattner</a><br>
   <a href="http://llvm.cs.uiuc.edu">The LLVM Compiler Infrastructure</a><br>
-  Last modified: $Date: 2005/07/19 01:36:35 $
+  Last modified: $Date: 2005/07/19 03:37:48 $
 </address>
 
 </body>





From reid at x10sys.com  Mon Jul 18 23:52:56 2005
From: reid at x10sys.com (Reid Spencer)
Date: Mon, 18 Jul 2005 23:52:56 -0500
Subject: [llvm-commits] CVS: llvm/lib/Target/X86/X86ISelPattern.cpp 
Message-ID: <200507190452.XAA01525@zion.cs.uiuc.edu>



Changes in directory llvm/lib/Target/X86:

X86ISelPattern.cpp updated: 1.153 -> 1.154
---
Log message:

For: memory operations -> stores
This is the first incremental patch to implement this feature. It adds no
functionality to LLVM but setup up the information needed from targets in
order to implement the optimization correctly. Each target needs to specify
the maximum number of store operations for conversion of the llvm.memset, 
llvm.memcpy, and llvm.memmove intrinsics into a sequence of store operations.
The limit needs to be chosen at the threshold of performance for such an
optimization (generally smallish). The target also needs to specify whether
the target can support unaligned stores for multi-byte store operations. 
This helps ensure the optimization doesn't generate code that will trap on
an alignment errors.
More patches to follow.


---
Diffs of the changes:  (+5 -0)

 X86ISelPattern.cpp |    5 +++++
 1 files changed, 5 insertions(+)


Index: llvm/lib/Target/X86/X86ISelPattern.cpp
diff -u llvm/lib/Target/X86/X86ISelPattern.cpp:1.153 llvm/lib/Target/X86/X86ISelPattern.cpp:1.154
--- llvm/lib/Target/X86/X86ISelPattern.cpp:1.153	Fri Jul 15 21:02:34 2005
+++ llvm/lib/Target/X86/X86ISelPattern.cpp	Mon Jul 18 23:52:44 2005
@@ -189,6 +189,11 @@
         addLegalFPImmediate(-1.0); // FLD1/FCHS
       }
       computeRegisterProperties();
+
+      maxStoresPerMemSet = 8; // For %llvm.memset -> sequence of stores
+      maxStoresPerMemCpy = 8; // For %llvm.memcpy -> sequence of stores
+      maxStoresPerMemMove = 8; // For %llvm.memmove -> sequence of stores
+      allowUnalignedStores = true; // x86 supports it!
     }
     
     // Return the number of bytes that a function should pop when it returns (in





From reid at x10sys.com  Mon Jul 18 23:52:56 2005
From: reid at x10sys.com (Reid Spencer)
Date: Mon, 18 Jul 2005 23:52:56 -0500
Subject: [llvm-commits] CVS: llvm/lib/Target/TargetLowering.cpp 
Message-ID: <200507190452.XAA01516@zion.cs.uiuc.edu>



Changes in directory llvm/lib/Target:

TargetLowering.cpp updated: 1.8 -> 1.9
---
Log message:

For: memory operations -> stores
This is the first incremental patch to implement this feature. It adds no
functionality to LLVM but setup up the information needed from targets in
order to implement the optimization correctly. Each target needs to specify
the maximum number of store operations for conversion of the llvm.memset, 
llvm.memcpy, and llvm.memmove intrinsics into a sequence of store operations.
The limit needs to be chosen at the threshold of performance for such an
optimization (generally smallish). The target also needs to specify whether
the target can support unaligned stores for multi-byte store operations. 
This helps ensure the optimization doesn't generate code that will trap on
an alignment errors.
More patches to follow.


---
Diffs of the changes:  (+2 -0)

 TargetLowering.cpp |    2 ++
 1 files changed, 2 insertions(+)


Index: llvm/lib/Target/TargetLowering.cpp
diff -u llvm/lib/Target/TargetLowering.cpp:1.8 llvm/lib/Target/TargetLowering.cpp:1.9
--- llvm/lib/Target/TargetLowering.cpp:1.8	Thu Apr 21 17:55:34 2005
+++ llvm/lib/Target/TargetLowering.cpp	Mon Jul 18 23:52:44 2005
@@ -27,6 +27,8 @@
   ShiftAmountTy = SetCCResultTy = PointerTy = getValueType(TD.getIntPtrType());
   ShiftAmtHandling = Undefined;
   memset(RegClassForVT, 0,MVT::LAST_VALUETYPE*sizeof(TargetRegisterClass*));
+  maxStoresPerMemSet = maxStoresPerMemCpy = maxStoresPerMemMove = 0;
+  allowUnalignedStores = false;
 }
 
 TargetLowering::~TargetLowering() {}





From reid at x10sys.com  Mon Jul 18 23:52:56 2005
From: reid at x10sys.com (Reid Spencer)
Date: Mon, 18 Jul 2005 23:52:56 -0500
Subject: [llvm-commits] CVS: llvm/include/llvm/Target/TargetLowering.h 
Message-ID: <200507190452.XAA01518@zion.cs.uiuc.edu>



Changes in directory llvm/include/llvm/Target:

TargetLowering.h updated: 1.16 -> 1.17
---
Log message:

For: memory operations -> stores
This is the first incremental patch to implement this feature. It adds no
functionality to LLVM but setup up the information needed from targets in
order to implement the optimization correctly. Each target needs to specify
the maximum number of store operations for conversion of the llvm.memset, 
llvm.memcpy, and llvm.memmove intrinsics into a sequence of store operations.
The limit needs to be chosen at the threshold of performance for such an
optimization (generally smallish). The target also needs to specify whether
the target can support unaligned stores for multi-byte store operations. 
This helps ensure the optimization doesn't generate code that will trap on
an alignment errors.
More patches to follow.


---
Diffs of the changes:  (+67 -0)

 TargetLowering.h |   67 +++++++++++++++++++++++++++++++++++++++++++++++++++++++
 1 files changed, 67 insertions(+)


Index: llvm/include/llvm/Target/TargetLowering.h
diff -u llvm/include/llvm/Target/TargetLowering.h:1.16 llvm/include/llvm/Target/TargetLowering.h:1.17
--- llvm/include/llvm/Target/TargetLowering.h:1.16	Tue Jul  5 14:57:17 2005
+++ llvm/include/llvm/Target/TargetLowering.h	Mon Jul 18 23:52:44 2005
@@ -12,6 +12,7 @@
 //
 //  1. Which ValueTypes are natively supported by the target.
 //  2. Which operations are supported for supported ValueTypes.
+//  3. Cost thresholds for alternative implementations of certain operations.
 //
 // In addition it has a few other components, like information about FP
 // immediates.
@@ -187,6 +188,31 @@
     return NumElementsForVT[VT];
   }
 
+  /// This function returns the maximum number of store operations permitted
+  /// to replace a call to llvm.memset. The value is set by the target at the
+  /// performance threshold for such a replacement.
+  /// @brief Get maximum # of store operations permitted for llvm.memset
+  unsigned getMaxStoresPerMemSet() const { return maxStoresPerMemSet; }
+
+  /// This function returns the maximum number of store operations permitted
+  /// to replace a call to llvm.memcpy. The value is set by the target at the
+  /// performance threshold for such a replacement.
+  /// @brief Get maximum # of store operations permitted for llvm.memcpy
+  unsigned getMaxStoresPerMemCpy() const { return maxStoresPerMemCpy; }
+
+  /// This function returns the maximum number of store operations permitted
+  /// to replace a call to llvm.memmove. The value is set by the target at the
+  /// performance threshold for such a replacement.
+  /// @brief Get maximum # of store operations permitted for llvm.memmove
+  unsigned getMaxStoresPerMemMove() const { return maxStoresPerMemMove; }
+
+  /// This function returns true if the target allows unaligned stores. This is
+  /// used in situations where an array copy/move/set is converted to a sequence
+  /// of store operations. It ensures that such replacements don't generate 
+  /// code that causes an alignment error (trap) on the target machine. 
+  /// @brief Determine if the target supports unaligned stores.
+  bool allowsUnalignedStores() const { return allowUnalignedStores; }
+
   //===--------------------------------------------------------------------===//
   // TargetLowering Configuration Methods - These methods should be invoked by
   // the derived class constructor to configure this object for the target.
@@ -365,6 +391,47 @@
 
   std::vector<std::pair<MVT::ValueType,
                         TargetRegisterClass*> > AvailableRegClasses;
+
+protected:
+  /// When lowering %llvm.memset this field specifies the maximum number of
+  /// store operations that may be substituted for the call to memset. Targets
+  /// must set this value based on the cost threshold for that target. Targets
+  /// should assume that the memset will be done using as many of the largest
+  /// store operations first, followed by smaller ones, if necessary, per
+  /// alignment restrictions. For example, storing 9 bytes on a 32-bit machine
+  /// with 16-bit alignment would result in four 2-byte stores and one 1-byte 
+  /// store.  This only applies to setting a constant array of a constant size.
+  /// @brief Specify maximum number of store instructions per memset call.
+  unsigned maxStoresPerMemSet;
+
+  /// When lowering %llvm.memcpy this field specifies the maximum number of
+  /// store operations that may be substituted for a call to memcpy. Targets
+  /// must set this value based on the cost threshold for that target. Targets
+  /// should assume that the memcpy will be done using as many of the largest
+  /// store operations first, followed by smaller ones, if necessary, per
+  /// alignment restrictions. For example, storing 7 bytes on a 32-bit machine
+  /// with 32-bit alignment would result in one 4-byte store, a one 2-byte store
+  /// and one 1-byte store. This only applies to copying a constant array of
+  /// constant size.
+  /// @brief Specify maximum bytes of store instructions per memcpy call.
+  unsigned maxStoresPerMemCpy;
+
+  /// When lowering %llvm.memmove this field specifies the maximum number of
+  /// store instructions that may be substituted for a call to memmove. Targets
+  /// must set this value based on the cost threshold for that target. Targets
+  /// should assume that the memmove will be done using as many of the largest
+  /// store operations first, followed by smaller ones, if necessary, per
+  /// alignment restrictions. For example, moving 9 bytes on a 32-bit machine 
+  /// with 8-bit alignment would result in nine 1-byte stores.  This only 
+  /// applies to copying a constant array of constant size.
+  /// @brief Specify maximum bytes of store instructions per memmove call.
+  unsigned maxStoresPerMemMove;
+
+  /// This field specifies whether the target machine permits unaligned stores.
+  /// This is used to determine the size of store operations for copying 
+  /// small arrays and other similar tasks.
+  /// @brief Indicate whether the target machine permits unaligned stores.
+  bool allowUnalignedStores;
 };
 } // end llvm namespace
 





From natebegeman at mac.com  Tue Jul 19 11:50:15 2005
From: natebegeman at mac.com (Nate Begeman)
Date: Tue, 19 Jul 2005 11:50:15 -0500
Subject: [llvm-commits] 
	CVS: llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
Message-ID: <200507191650.LAA01162@zion.cs.uiuc.edu>



Changes in directory llvm/lib/CodeGen/SelectionDAG:

SelectionDAGISel.cpp updated: 1.65 -> 1.66
---
Log message:

Remove unnecessary FP_EXTEND. This causes worse codegen for SSE.


---
Diffs of the changes:  (+0 -3)

 SelectionDAGISel.cpp |    3 ---
 1 files changed, 3 deletions(-)


Index: llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.65 llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.66
--- llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.65	Tue Jul  5 14:57:53 2005
+++ llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp	Tue Jul 19 11:50:03 2005
@@ -403,9 +403,6 @@
       Op1 = DAG.getNode(ISD::ZERO_EXTEND, TmpVT, Op1);
     break;
   case MVT::f32:
-    // Extend float to double.
-    Op1 = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Op1);
-    break;
   case MVT::i64:
   case MVT::f64:
     break; // No extension needed!





From natebegeman at mac.com  Tue Jul 19 11:51:16 2005
From: natebegeman at mac.com (Nate Begeman)
Date: Tue, 19 Jul 2005 11:51:16 -0500
Subject: [llvm-commits] CVS: llvm/lib/Target/PowerPC/PPC32ISelPattern.cpp
	PowerPC.h PowerPCTargetMachine.cpp 
Message-ID: <200507191651.LAA01198@zion.cs.uiuc.edu>



Changes in directory llvm/lib/Target/PowerPC:

PPC32ISelPattern.cpp updated: 1.99 -> 1.100
PowerPC.h updated: 1.15 -> 1.16
PowerPCTargetMachine.cpp updated: 1.52 -> 1.53
---
Log message:

Integrate SelectFPExpr into SelectExpr.  This gets PPC32 closer to being
automatically generated from a target description.


---
Diffs of the changes:  (+242 -346)

 PPC32ISelPattern.cpp     |  580 +++++++++++++++++++----------------------------
 PowerPC.h                |    2 
 PowerPCTargetMachine.cpp |    6 
 3 files changed, 242 insertions(+), 346 deletions(-)


Index: llvm/lib/Target/PowerPC/PPC32ISelPattern.cpp
diff -u llvm/lib/Target/PowerPC/PPC32ISelPattern.cpp:1.99 llvm/lib/Target/PowerPC/PPC32ISelPattern.cpp:1.100
--- llvm/lib/Target/PowerPC/PPC32ISelPattern.cpp:1.99	Sat Jul  9 20:56:13 2005
+++ llvm/lib/Target/PowerPC/PPC32ISelPattern.cpp	Tue Jul 19 11:51:05 2005
@@ -17,9 +17,9 @@
 #include "PowerPCInstrBuilder.h"
 #include "PowerPCInstrInfo.h"
 #include "PPC32TargetMachine.h"
-#include "llvm/Constants.h"                   // FIXME: REMOVE
+#include "llvm/Constants.h"
 #include "llvm/Function.h"
-#include "llvm/CodeGen/MachineConstantPool.h" // FIXME: REMOVE
+#include "llvm/CodeGen/MachineConstantPool.h"
 #include "llvm/CodeGen/MachineFunction.h"
 #include "llvm/CodeGen/MachineFrameInfo.h"
 #include "llvm/CodeGen/SelectionDAG.h"
@@ -563,7 +563,6 @@
   unsigned SelectCC(SDOperand CC, unsigned &Opc, bool &Inv, unsigned &Idx);
   unsigned SelectCCExpr(SDOperand N, unsigned& Opc, bool &Inv, unsigned &Idx);
   unsigned SelectExpr(SDOperand N, bool Recording=false);
-  unsigned SelectExprFP(SDOperand N, unsigned Result);
   void Select(SDOperand N);
 
   bool SelectAddr(SDOperand N, unsigned& Reg, int& offset);
@@ -1155,8 +1154,6 @@
       BuildMI(BB, CompareOpc, 2, Result).addReg(Tmp1).addReg(Tmp2);
     }
   } else {
-    if (PPCCRopts)
-      return SelectCCExpr(CC, Opc, Inv, Idx);
     // If this isn't a SetCC, then select the value and compare it against zero,
     // treating it as if it were a boolean.
     Opc = PPC::BNE;
@@ -1271,307 +1268,6 @@
   return;
 }
 
-unsigned ISel::SelectExprFP(SDOperand N, unsigned Result)
-{
-  unsigned Tmp1, Tmp2, Tmp3;
-  unsigned Opc = 0;
-  SDNode *Node = N.Val;
-  MVT::ValueType DestType = N.getValueType();
-  unsigned opcode = N.getOpcode();
-
-  switch (opcode) {
-  default:
-    Node->dump();
-    assert(0 && "Node not handled!\n");
-
-  case ISD::SELECT: {
-    // Attempt to generate FSEL.  We can do this whenever we have an FP result,
-    // and an FP comparison in the SetCC node.
-    SetCCSDNode* SetCC = dyn_cast<SetCCSDNode>(N.getOperand(0).Val);
-    if (SetCC && N.getOperand(0).getOpcode() == ISD::SETCC &&
-        !MVT::isInteger(SetCC->getOperand(0).getValueType()) &&
-        SetCC->getCondition() != ISD::SETEQ &&
-        SetCC->getCondition() != ISD::SETNE) {
-      MVT::ValueType VT = SetCC->getOperand(0).getValueType();
-      unsigned TV = SelectExpr(N.getOperand(1)); // Use if TRUE
-      unsigned FV = SelectExpr(N.getOperand(2)); // Use if FALSE
-
-      ConstantFPSDNode *CN = dyn_cast<ConstantFPSDNode>(SetCC->getOperand(1));
-      if (CN && (CN->isExactlyValue(-0.0) || CN->isExactlyValue(0.0))) {
-        switch(SetCC->getCondition()) {
-        default: assert(0 && "Invalid FSEL condition"); abort();
-        case ISD::SETULT:
-        case ISD::SETLT:
-          std::swap(TV, FV);  // fsel is natively setge, swap operands for setlt
-        case ISD::SETUGE:
-        case ISD::SETGE:
-          Tmp1 = SelectExpr(SetCC->getOperand(0));   // Val to compare against
-          BuildMI(BB, PPC::FSEL, 3, Result).addReg(Tmp1).addReg(TV).addReg(FV);
-          return Result;
-        case ISD::SETUGT:
-        case ISD::SETGT:
-          std::swap(TV, FV);  // fsel is natively setge, swap operands for setlt
-        case ISD::SETULE:
-        case ISD::SETLE: {
-          if (SetCC->getOperand(0).getOpcode() == ISD::FNEG) {
-            Tmp2 = SelectExpr(SetCC->getOperand(0).getOperand(0));
-          } else {
-            Tmp2 = MakeReg(VT);
-            Tmp1 = SelectExpr(SetCC->getOperand(0));   // Val to compare against
-            BuildMI(BB, PPC::FNEG, 1, Tmp2).addReg(Tmp1);
-          }
-          BuildMI(BB, PPC::FSEL, 3, Result).addReg(Tmp2).addReg(TV).addReg(FV);
-          return Result;
-        }
-        }
-      } else {
-        Opc = (MVT::f64 == VT) ? PPC::FSUB : PPC::FSUBS;
-        Tmp1 = SelectExpr(SetCC->getOperand(0));   // Val to compare against
-        Tmp2 = SelectExpr(SetCC->getOperand(1));
-        Tmp3 =  MakeReg(VT);
-        switch(SetCC->getCondition()) {
-        default: assert(0 && "Invalid FSEL condition"); abort();
-        case ISD::SETULT:
-        case ISD::SETLT:
-          BuildMI(BB, Opc, 2, Tmp3).addReg(Tmp1).addReg(Tmp2);
-          BuildMI(BB, PPC::FSEL, 3, Result).addReg(Tmp3).addReg(FV).addReg(TV);
-          return Result;
-        case ISD::SETUGE:
-        case ISD::SETGE:
-          BuildMI(BB, Opc, 2, Tmp3).addReg(Tmp1).addReg(Tmp2);
-          BuildMI(BB, PPC::FSEL, 3, Result).addReg(Tmp3).addReg(TV).addReg(FV);
-          return Result;
-        case ISD::SETUGT:
-        case ISD::SETGT:
-          BuildMI(BB, Opc, 2, Tmp3).addReg(Tmp2).addReg(Tmp1);
-          BuildMI(BB, PPC::FSEL, 3, Result).addReg(Tmp3).addReg(FV).addReg(TV);
-          return Result;
-        case ISD::SETULE:
-        case ISD::SETLE:
-          BuildMI(BB, Opc, 2, Tmp3).addReg(Tmp2).addReg(Tmp1);
-          BuildMI(BB, PPC::FSEL, 3, Result).addReg(Tmp3).addReg(TV).addReg(FV);
-          return Result;
-        }
-      }
-      assert(0 && "Should never get here");
-      return 0;
-    }
-
-    bool Inv;
-    unsigned TrueValue = SelectExpr(N.getOperand(1)); //Use if TRUE
-    unsigned FalseValue = SelectExpr(N.getOperand(2)); //Use if FALSE
-    unsigned CCReg = SelectCC(N.getOperand(0), Opc, Inv, Tmp3);
-
-    // Create an iterator with which to insert the MBB for copying the false
-    // value and the MBB to hold the PHI instruction for this SetCC.
-    MachineBasicBlock *thisMBB = BB;
-    const BasicBlock *LLVM_BB = BB->getBasicBlock();
-    ilist<MachineBasicBlock>::iterator It = BB;
-    ++It;
-
-    //  thisMBB:
-    //  ...
-    //   TrueVal = ...
-    //   cmpTY ccX, r1, r2
-    //   bCC copy1MBB
-    //   fallthrough --> copy0MBB
-    MachineBasicBlock *copy0MBB = new MachineBasicBlock(LLVM_BB);
-    MachineBasicBlock *sinkMBB = new MachineBasicBlock(LLVM_BB);
-    BuildMI(BB, Opc, 2).addReg(CCReg).addMBB(sinkMBB);
-    MachineFunction *F = BB->getParent();
-    F->getBasicBlockList().insert(It, copy0MBB);
-    F->getBasicBlockList().insert(It, sinkMBB);
-    // Update machine-CFG edges
-    BB->addSuccessor(copy0MBB);
-    BB->addSuccessor(sinkMBB);
-
-    //  copy0MBB:
-    //   %FalseValue = ...
-    //   # fallthrough to sinkMBB
-    BB = copy0MBB;
-    // Update machine-CFG edges
-    BB->addSuccessor(sinkMBB);
-
-    //  sinkMBB:
-    //   %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
-    //  ...
-    BB = sinkMBB;
-    BuildMI(BB, PPC::PHI, 4, Result).addReg(FalseValue)
-      .addMBB(copy0MBB).addReg(TrueValue).addMBB(thisMBB);
-    return Result;
-  }
-
-  case ISD::FNEG:
-    if (!NoExcessFPPrecision &&
-        ISD::ADD == N.getOperand(0).getOpcode() &&
-        N.getOperand(0).Val->hasOneUse() &&
-        ISD::MUL == N.getOperand(0).getOperand(0).getOpcode() &&
-        N.getOperand(0).getOperand(0).Val->hasOneUse()) {
-      ++FusedFP; // Statistic
-      Tmp1 = SelectExpr(N.getOperand(0).getOperand(0).getOperand(0));
-      Tmp2 = SelectExpr(N.getOperand(0).getOperand(0).getOperand(1));
-      Tmp3 = SelectExpr(N.getOperand(0).getOperand(1));
-      Opc = DestType == MVT::f64 ? PPC::FNMADD : PPC::FNMADDS;
-      BuildMI(BB, Opc, 3, Result).addReg(Tmp1).addReg(Tmp2).addReg(Tmp3);
-    } else if (!NoExcessFPPrecision &&
-        ISD::ADD == N.getOperand(0).getOpcode() &&
-        N.getOperand(0).Val->hasOneUse() &&
-        ISD::MUL == N.getOperand(0).getOperand(1).getOpcode() &&
-        N.getOperand(0).getOperand(1).Val->hasOneUse()) {
-      ++FusedFP; // Statistic
-      Tmp1 = SelectExpr(N.getOperand(0).getOperand(1).getOperand(0));
-      Tmp2 = SelectExpr(N.getOperand(0).getOperand(1).getOperand(1));
-      Tmp3 = SelectExpr(N.getOperand(0).getOperand(0));
-      Opc = DestType == MVT::f64 ? PPC::FNMADD : PPC::FNMADDS;
-      BuildMI(BB, Opc, 3, Result).addReg(Tmp1).addReg(Tmp2).addReg(Tmp3);
-    } else if (ISD::FABS == N.getOperand(0).getOpcode()) {
-      Tmp1 = SelectExpr(N.getOperand(0).getOperand(0));
-      BuildMI(BB, PPC::FNABS, 1, Result).addReg(Tmp1);
-    } else {
-      Tmp1 = SelectExpr(N.getOperand(0));
-      BuildMI(BB, PPC::FNEG, 1, Result).addReg(Tmp1);
-    }
-    return Result;
-
-  case ISD::FABS:
-    Tmp1 = SelectExpr(N.getOperand(0));
-    BuildMI(BB, PPC::FABS, 1, Result).addReg(Tmp1);
-    return Result;
-
-  case ISD::FP_ROUND:
-    assert (DestType == MVT::f32 &&
-            N.getOperand(0).getValueType() == MVT::f64 &&
-            "only f64 to f32 conversion supported here");
-    Tmp1 = SelectExpr(N.getOperand(0));
-    BuildMI(BB, PPC::FRSP, 1, Result).addReg(Tmp1);
-    return Result;
-
-  case ISD::FP_EXTEND:
-    assert (DestType == MVT::f64 &&
-            N.getOperand(0).getValueType() == MVT::f32 &&
-            "only f32 to f64 conversion supported here");
-    Tmp1 = SelectExpr(N.getOperand(0));
-    BuildMI(BB, PPC::FMR, 1, Result).addReg(Tmp1);
-    return Result;
-
-  case ISD::CopyFromReg:
-    if (Result == 1)
-      Result = ExprMap[N.getValue(0)] = MakeReg(N.getValue(0).getValueType());
-    Tmp1 = dyn_cast<RegSDNode>(Node)->getReg();
-    BuildMI(BB, PPC::FMR, 1, Result).addReg(Tmp1);
-    return Result;
-
-  case ISD::ConstantFP: {
-    ConstantFPSDNode *CN = cast<ConstantFPSDNode>(N);
-    Result = getConstDouble(CN->getValue(), Result);
-    return Result;
-  }
-
-  case ISD::ADD:
-    if (!NoExcessFPPrecision && N.getOperand(0).getOpcode() == ISD::MUL &&
-        N.getOperand(0).Val->hasOneUse()) {
-      ++FusedFP; // Statistic
-      Tmp1 = SelectExpr(N.getOperand(0).getOperand(0));
-      Tmp2 = SelectExpr(N.getOperand(0).getOperand(1));
-      Tmp3 = SelectExpr(N.getOperand(1));
-      Opc = DestType == MVT::f64 ? PPC::FMADD : PPC::FMADDS;
-      BuildMI(BB, Opc, 3, Result).addReg(Tmp1).addReg(Tmp2).addReg(Tmp3);
-      return Result;
-    }
-    if (!NoExcessFPPrecision && N.getOperand(1).getOpcode() == ISD::MUL &&
-        N.getOperand(1).Val->hasOneUse()) {
-      ++FusedFP; // Statistic
-      Tmp1 = SelectExpr(N.getOperand(1).getOperand(0));
-      Tmp2 = SelectExpr(N.getOperand(1).getOperand(1));
-      Tmp3 = SelectExpr(N.getOperand(0));
-      Opc = DestType == MVT::f64 ? PPC::FMADD : PPC::FMADDS;
-      BuildMI(BB, Opc, 3, Result).addReg(Tmp1).addReg(Tmp2).addReg(Tmp3);
-      return Result;
-    }
-    Opc = DestType == MVT::f64 ? PPC::FADD : PPC::FADDS;
-    Tmp1 = SelectExpr(N.getOperand(0));
-    Tmp2 = SelectExpr(N.getOperand(1));
-    BuildMI(BB, Opc, 2, Result).addReg(Tmp1).addReg(Tmp2);
-    return Result;
-
-  case ISD::SUB:
-    if (!NoExcessFPPrecision && N.getOperand(0).getOpcode() == ISD::MUL &&
-        N.getOperand(0).Val->hasOneUse()) {
-      ++FusedFP; // Statistic
-      Tmp1 = SelectExpr(N.getOperand(0).getOperand(0));
-      Tmp2 = SelectExpr(N.getOperand(0).getOperand(1));
-      Tmp3 = SelectExpr(N.getOperand(1));
-      Opc = DestType == MVT::f64 ? PPC::FMSUB : PPC::FMSUBS;
-      BuildMI(BB, Opc, 3, Result).addReg(Tmp1).addReg(Tmp2).addReg(Tmp3);
-      return Result;
-    }
-    if (!NoExcessFPPrecision && N.getOperand(1).getOpcode() == ISD::MUL &&
-        N.getOperand(1).Val->hasOneUse()) {
-      ++FusedFP; // Statistic
-      Tmp1 = SelectExpr(N.getOperand(1).getOperand(0));
-      Tmp2 = SelectExpr(N.getOperand(1).getOperand(1));
-      Tmp3 = SelectExpr(N.getOperand(0));
-      Opc = DestType == MVT::f64 ? PPC::FNMSUB : PPC::FNMSUBS;
-      BuildMI(BB, Opc, 3, Result).addReg(Tmp1).addReg(Tmp2).addReg(Tmp3);
-      return Result;
-    }
-    Opc = DestType == MVT::f64 ? PPC::FSUB : PPC::FSUBS;
-    Tmp1 = SelectExpr(N.getOperand(0));
-    Tmp2 = SelectExpr(N.getOperand(1));
-    BuildMI(BB, Opc, 2, Result).addReg(Tmp1).addReg(Tmp2);
-    return Result;
-
-  case ISD::MUL:
-  case ISD::SDIV:
-    switch( opcode ) {
-    case ISD::MUL:  Opc = DestType == MVT::f64 ? PPC::FMUL : PPC::FMULS; break;
-    case ISD::SDIV: Opc = DestType == MVT::f64 ? PPC::FDIV : PPC::FDIVS; break;
-    };
-    Tmp1 = SelectExpr(N.getOperand(0));
-    Tmp2 = SelectExpr(N.getOperand(1));
-    BuildMI(BB, Opc, 2, Result).addReg(Tmp1).addReg(Tmp2);
-    return Result;
-
-  case ISD::UINT_TO_FP:
-  case ISD::SINT_TO_FP: {
-    assert (N.getOperand(0).getValueType() == MVT::i32
-            && "int to float must operate on i32");
-    bool IsUnsigned = (ISD::UINT_TO_FP == opcode);
-    Tmp1 = SelectExpr(N.getOperand(0));  // Get the operand register
-    Tmp2 = MakeReg(MVT::f64); // temp reg to load the integer value into
-    Tmp3 = MakeReg(MVT::i32); // temp reg to hold the conversion constant
-
-    int FrameIdx = BB->getParent()->getFrameInfo()->CreateStackObject(8, 8);
-    MachineConstantPool *CP = BB->getParent()->getConstantPool();
-
-    if (IsUnsigned) {
-      unsigned ConstF = getConstDouble(0x1.000000p52);
-      // Store the hi & low halves of the fp value, currently in int regs
-      BuildMI(BB, PPC::LIS, 1, Tmp3).addSImm(0x4330);
-      addFrameReference(BuildMI(BB, PPC::STW, 3).addReg(Tmp3), FrameIdx);
-      addFrameReference(BuildMI(BB, PPC::STW, 3).addReg(Tmp1), FrameIdx, 4);
-      addFrameReference(BuildMI(BB, PPC::LFD, 2, Tmp2), FrameIdx);
-      // Generate the return value with a subtract
-      BuildMI(BB, PPC::FSUB, 2, Result).addReg(Tmp2).addReg(ConstF);
-    } else {
-      unsigned ConstF = getConstDouble(0x1.000008p52);
-      unsigned TmpL = MakeReg(MVT::i32);
-      // Store the hi & low halves of the fp value, currently in int regs
-      BuildMI(BB, PPC::LIS, 1, Tmp3).addSImm(0x4330);
-      addFrameReference(BuildMI(BB, PPC::STW, 3).addReg(Tmp3), FrameIdx);
-      BuildMI(BB, PPC::XORIS, 2, TmpL).addReg(Tmp1).addImm(0x8000);
-      addFrameReference(BuildMI(BB, PPC::STW, 3).addReg(TmpL), FrameIdx, 4);
-      addFrameReference(BuildMI(BB, PPC::LFD, 2, Tmp2), FrameIdx);
-      // Generate the return value with a subtract
-      BuildMI(BB, PPC::FSUB, 2, Result).addReg(Tmp2).addReg(ConstF);
-    }
-    return Result;
-  }
-  }
-  assert(0 && "Should never get here");
-  return 0;
-}
-
 unsigned ISel::SelectExpr(SDOperand N, bool Recording) {
   unsigned Result;
   unsigned Tmp1, Tmp2, Tmp3;
@@ -1620,14 +1316,6 @@
     break;
   }
 
-  if (ISD::CopyFromReg == opcode)
-    DestType = N.getValue(0).getValueType();
-
-  if (DestType == MVT::f64 || DestType == MVT::f32)
-    if (ISD::LOAD != opcode && ISD::EXTLOAD != opcode &&
-        ISD::UNDEF != opcode && ISD::CALL != opcode && ISD::TAILCALL != opcode)
-      return SelectExprFP(N, Result);
-
   switch (opcode) {
   default:
     Node->dump();
@@ -1843,10 +1531,14 @@
     return Result;
 
   case ISD::CopyFromReg:
+    DestType = N.getValue(0).getValueType();
     if (Result == 1)
-      Result = ExprMap[N.getValue(0)] = MakeReg(N.getValue(0).getValueType());
+      Result = ExprMap[N.getValue(0)] = MakeReg(DestType);
     Tmp1 = dyn_cast<RegSDNode>(Node)->getReg();
-    BuildMI(BB, PPC::OR, 2, Result).addReg(Tmp1).addReg(Tmp1);
+    if (MVT::isInteger(DestType))
+      BuildMI(BB, PPC::OR, 2, Result).addReg(Tmp1).addReg(Tmp1);
+    else
+      BuildMI(BB, PPC::FMR, 1, Result).addReg(Tmp1);
     return Result;
 
   case ISD::SHL:
@@ -1890,7 +1582,33 @@
     return Result;
 
   case ISD::ADD:
-    assert (DestType == MVT::i32 && "Only do arithmetic on i32s!");
+    if (!MVT::isInteger(DestType)) {
+      if (!NoExcessFPPrecision && N.getOperand(0).getOpcode() == ISD::MUL &&
+          N.getOperand(0).Val->hasOneUse()) {
+        ++FusedFP; // Statistic
+        Tmp1 = SelectExpr(N.getOperand(0).getOperand(0));
+        Tmp2 = SelectExpr(N.getOperand(0).getOperand(1));
+        Tmp3 = SelectExpr(N.getOperand(1));
+        Opc = DestType == MVT::f64 ? PPC::FMADD : PPC::FMADDS;
+        BuildMI(BB, Opc, 3, Result).addReg(Tmp1).addReg(Tmp2).addReg(Tmp3);
+        return Result;
+      }
+      if (!NoExcessFPPrecision && N.getOperand(1).getOpcode() == ISD::MUL &&
+          N.getOperand(1).Val->hasOneUse()) {
+        ++FusedFP; // Statistic
+        Tmp1 = SelectExpr(N.getOperand(1).getOperand(0));
+        Tmp2 = SelectExpr(N.getOperand(1).getOperand(1));
+        Tmp3 = SelectExpr(N.getOperand(0));
+        Opc = DestType == MVT::f64 ? PPC::FMADD : PPC::FMADDS;
+        BuildMI(BB, Opc, 3, Result).addReg(Tmp1).addReg(Tmp2).addReg(Tmp3);
+        return Result;
+      }
+      Opc = DestType == MVT::f64 ? PPC::FADD : PPC::FADDS;
+      Tmp1 = SelectExpr(N.getOperand(0));
+      Tmp2 = SelectExpr(N.getOperand(1));
+      BuildMI(BB, Opc, 2, Result).addReg(Tmp1).addReg(Tmp2);
+      return Result;
+    }
     Tmp1 = SelectExpr(N.getOperand(0));
     switch(getImmediateForOpcode(N.getOperand(1), opcode, Tmp2)) {
       default: assert(0 && "unhandled result code");
@@ -1908,15 +1626,6 @@
     return Result;
 
   case ISD::AND:
-    if (PPCCRopts) {
-      if (N.getOperand(0).getOpcode() == ISD::SETCC ||
-          N.getOperand(1).getOpcode() == ISD::SETCC) {
-        bool Inv;
-        Tmp1 = SelectCCExpr(N, Opc, Inv, Tmp2);
-        MoveCRtoGPR(Tmp1, Inv, Tmp2, Result);
-        return Result;
-      }
-    }
     // FIXME: should add check in getImmediateForOpcode to return a value
     // indicating the immediate is a run of set bits so we can emit a bitfield
     // clear with RLWINM instead.
@@ -1977,15 +1686,6 @@
   case ISD::OR:
     if (SelectBitfieldInsert(N, Result))
       return Result;
-    if (PPCCRopts) {
-      if (N.getOperand(0).getOpcode() == ISD::SETCC ||
-          N.getOperand(1).getOpcode() == ISD::SETCC) {
-        bool Inv;
-        Tmp1 = SelectCCExpr(N, Opc, Inv, Tmp2);
-        MoveCRtoGPR(Tmp1, Inv, Tmp2, Result);
-        return Result;
-      }
-    }
     Tmp1 = SelectExpr(N.getOperand(0));
     switch(getImmediateForOpcode(N.getOperand(1), opcode, Tmp2)) {
       default: assert(0 && "unhandled result code");
@@ -2058,6 +1758,33 @@
   }
 
   case ISD::SUB:
+    if (!MVT::isInteger(DestType)) {
+      if (!NoExcessFPPrecision && N.getOperand(0).getOpcode() == ISD::MUL &&
+          N.getOperand(0).Val->hasOneUse()) {
+        ++FusedFP; // Statistic
+        Tmp1 = SelectExpr(N.getOperand(0).getOperand(0));
+        Tmp2 = SelectExpr(N.getOperand(0).getOperand(1));
+        Tmp3 = SelectExpr(N.getOperand(1));
+        Opc = DestType == MVT::f64 ? PPC::FMSUB : PPC::FMSUBS;
+        BuildMI(BB, Opc, 3, Result).addReg(Tmp1).addReg(Tmp2).addReg(Tmp3);
+        return Result;
+      }
+      if (!NoExcessFPPrecision && N.getOperand(1).getOpcode() == ISD::MUL &&
+          N.getOperand(1).Val->hasOneUse()) {
+        ++FusedFP; // Statistic
+        Tmp1 = SelectExpr(N.getOperand(1).getOperand(0));
+        Tmp2 = SelectExpr(N.getOperand(1).getOperand(1));
+        Tmp3 = SelectExpr(N.getOperand(0));
+        Opc = DestType == MVT::f64 ? PPC::FNMSUB : PPC::FNMSUBS;
+        BuildMI(BB, Opc, 3, Result).addReg(Tmp1).addReg(Tmp2).addReg(Tmp3);
+        return Result;
+      }
+      Opc = DestType == MVT::f64 ? PPC::FSUB : PPC::FSUBS;
+      Tmp1 = SelectExpr(N.getOperand(0));
+      Tmp2 = SelectExpr(N.getOperand(1));
+      BuildMI(BB, Opc, 2, Result).addReg(Tmp1).addReg(Tmp2);
+      return Result;
+    }
     if (1 == getImmediateForOpcode(N.getOperand(0), opcode, Tmp1, true)) {
       Tmp2 = SelectExpr(N.getOperand(1));
       BuildMI(BB, PPC::SUBFIC, 2, Result).addReg(Tmp2).addSImm(Tmp1);
@@ -2077,7 +1804,13 @@
       BuildMI(BB, PPC::MULLI, 2, Result).addReg(Tmp1).addSImm(Tmp2);
     else {
       Tmp2 = SelectExpr(N.getOperand(1));
-      BuildMI(BB, PPC::MULLW, 2, Result).addReg(Tmp1).addReg(Tmp2);
+      switch (DestType) {
+      default: assert(0 && "Unknown type to ISD::MUL"); break;
+      case MVT::i32: Opc = PPC::MULLW; break;
+      case MVT::f32: Opc = PPC::FMULS; break;
+      case MVT::f64: Opc = PPC::FMUL; break;
+      }
+      BuildMI(BB, Opc, 2, Result).addReg(Tmp1).addReg(Tmp2);
     }
     return Result;
 
@@ -2115,10 +1848,15 @@
         return SelectExpr(BuildSDIVSequence(N));
       else
         return SelectExpr(BuildUDIVSequence(N));
-    }
+    }    
     Tmp1 = SelectExpr(N.getOperand(0));
     Tmp2 = SelectExpr(N.getOperand(1));
-    Opc = (ISD::UDIV == opcode) ? PPC::DIVWU : PPC::DIVW;
+    switch (DestType) {
+    default: assert(0 && "Unknown type to ISD::SDIV"); break;
+    case MVT::i32: Opc = (ISD::UDIV == opcode) ? PPC::DIVWU : PPC::DIVW; break;
+    case MVT::f32: Opc = PPC::FDIVS; break;
+    case MVT::f64: Opc = PPC::FDIV; break;
+    }
     BuildMI(BB, Opc, 2, Result).addReg(Tmp1).addReg(Tmp2);
     return Result;
 
@@ -2355,6 +2093,78 @@
     return 0;
 
   case ISD::SELECT: {
+    SetCCSDNode* SetCC = dyn_cast<SetCCSDNode>(N.getOperand(0).Val);
+    if (SetCC && N.getOperand(0).getOpcode() == ISD::SETCC &&
+        !MVT::isInteger(SetCC->getOperand(0).getValueType()) &&
+        !MVT::isInteger(N.getOperand(1).getValueType()) &&
+        !MVT::isInteger(N.getOperand(2).getValueType()) &&
+        SetCC->getCondition() != ISD::SETEQ &&
+        SetCC->getCondition() != ISD::SETNE) {
+      MVT::ValueType VT = SetCC->getOperand(0).getValueType();
+      unsigned TV = SelectExpr(N.getOperand(1)); // Use if TRUE
+      unsigned FV = SelectExpr(N.getOperand(2)); // Use if FALSE
+
+      ConstantFPSDNode *CN = dyn_cast<ConstantFPSDNode>(SetCC->getOperand(1));
+      if (CN && (CN->isExactlyValue(-0.0) || CN->isExactlyValue(0.0))) {
+        switch(SetCC->getCondition()) {
+        default: assert(0 && "Invalid FSEL condition"); abort();
+        case ISD::SETULT:
+        case ISD::SETLT:
+          std::swap(TV, FV);  // fsel is natively setge, swap operands for setlt
+        case ISD::SETUGE:
+        case ISD::SETGE:
+          Tmp1 = SelectExpr(SetCC->getOperand(0));   // Val to compare against
+          BuildMI(BB, PPC::FSEL, 3, Result).addReg(Tmp1).addReg(TV).addReg(FV);
+          return Result;
+        case ISD::SETUGT:
+        case ISD::SETGT:
+          std::swap(TV, FV);  // fsel is natively setge, swap operands for setlt
+        case ISD::SETULE:
+        case ISD::SETLE: {
+          if (SetCC->getOperand(0).getOpcode() == ISD::FNEG) {
+            Tmp2 = SelectExpr(SetCC->getOperand(0).getOperand(0));
+          } else {
+            Tmp2 = MakeReg(VT);
+            Tmp1 = SelectExpr(SetCC->getOperand(0));   // Val to compare against
+            BuildMI(BB, PPC::FNEG, 1, Tmp2).addReg(Tmp1);
+          }
+          BuildMI(BB, PPC::FSEL, 3, Result).addReg(Tmp2).addReg(TV).addReg(FV);
+          return Result;
+        }
+        }
+      } else {
+        Opc = (MVT::f64 == VT) ? PPC::FSUB : PPC::FSUBS;
+        Tmp1 = SelectExpr(SetCC->getOperand(0));   // Val to compare against
+        Tmp2 = SelectExpr(SetCC->getOperand(1));
+        Tmp3 =  MakeReg(VT);
+        switch(SetCC->getCondition()) {
+        default: assert(0 && "Invalid FSEL condition"); abort();
+        case ISD::SETULT:
+        case ISD::SETLT:
+          BuildMI(BB, Opc, 2, Tmp3).addReg(Tmp1).addReg(Tmp2);
+          BuildMI(BB, PPC::FSEL, 3, Result).addReg(Tmp3).addReg(FV).addReg(TV);
+          return Result;
+        case ISD::SETUGE:
+        case ISD::SETGE:
+          BuildMI(BB, Opc, 2, Tmp3).addReg(Tmp1).addReg(Tmp2);
+          BuildMI(BB, PPC::FSEL, 3, Result).addReg(Tmp3).addReg(TV).addReg(FV);
+          return Result;
+        case ISD::SETUGT:
+        case ISD::SETGT:
+          BuildMI(BB, Opc, 2, Tmp3).addReg(Tmp2).addReg(Tmp1);
+          BuildMI(BB, PPC::FSEL, 3, Result).addReg(Tmp3).addReg(FV).addReg(TV);
+          return Result;
+        case ISD::SETULE:
+        case ISD::SETLE:
+          BuildMI(BB, Opc, 2, Tmp3).addReg(Tmp2).addReg(Tmp1);
+          BuildMI(BB, PPC::FSEL, 3, Result).addReg(Tmp3).addReg(TV).addReg(FV);
+          return Result;
+        }
+      }
+      assert(0 && "Should never get here");
+      return 0;
+    }
+
     bool Inv;
     unsigned TrueValue = SelectExpr(N.getOperand(1)); //Use if TRUE
     unsigned FalseValue = SelectExpr(N.getOperand(2)); //Use if FALSE
@@ -2419,8 +2229,102 @@
       }
     }
     return Result;
+
+  case ISD::ConstantFP: {
+    ConstantFPSDNode *CN = cast<ConstantFPSDNode>(N);
+    Result = getConstDouble(CN->getValue(), Result);
+    return Result;
   }
 
+  case ISD::FNEG:
+    if (!NoExcessFPPrecision &&
+        ISD::ADD == N.getOperand(0).getOpcode() &&
+        N.getOperand(0).Val->hasOneUse() &&
+        ISD::MUL == N.getOperand(0).getOperand(0).getOpcode() &&
+        N.getOperand(0).getOperand(0).Val->hasOneUse()) {
+      ++FusedFP; // Statistic
+      Tmp1 = SelectExpr(N.getOperand(0).getOperand(0).getOperand(0));
+      Tmp2 = SelectExpr(N.getOperand(0).getOperand(0).getOperand(1));
+      Tmp3 = SelectExpr(N.getOperand(0).getOperand(1));
+      Opc = DestType == MVT::f64 ? PPC::FNMADD : PPC::FNMADDS;
+      BuildMI(BB, Opc, 3, Result).addReg(Tmp1).addReg(Tmp2).addReg(Tmp3);
+    } else if (!NoExcessFPPrecision &&
+        ISD::ADD == N.getOperand(0).getOpcode() &&
+        N.getOperand(0).Val->hasOneUse() &&
+        ISD::MUL == N.getOperand(0).getOperand(1).getOpcode() &&
+        N.getOperand(0).getOperand(1).Val->hasOneUse()) {
+      ++FusedFP; // Statistic
+      Tmp1 = SelectExpr(N.getOperand(0).getOperand(1).getOperand(0));
+      Tmp2 = SelectExpr(N.getOperand(0).getOperand(1).getOperand(1));
+      Tmp3 = SelectExpr(N.getOperand(0).getOperand(0));
+      Opc = DestType == MVT::f64 ? PPC::FNMADD : PPC::FNMADDS;
+      BuildMI(BB, Opc, 3, Result).addReg(Tmp1).addReg(Tmp2).addReg(Tmp3);
+    } else if (ISD::FABS == N.getOperand(0).getOpcode()) {
+      Tmp1 = SelectExpr(N.getOperand(0).getOperand(0));
+      BuildMI(BB, PPC::FNABS, 1, Result).addReg(Tmp1);
+    } else {
+      Tmp1 = SelectExpr(N.getOperand(0));
+      BuildMI(BB, PPC::FNEG, 1, Result).addReg(Tmp1);
+    }
+    return Result;
+
+  case ISD::FABS:
+    Tmp1 = SelectExpr(N.getOperand(0));
+    BuildMI(BB, PPC::FABS, 1, Result).addReg(Tmp1);
+    return Result;
+
+  case ISD::FP_ROUND:
+    assert (DestType == MVT::f32 &&
+            N.getOperand(0).getValueType() == MVT::f64 &&
+            "only f64 to f32 conversion supported here");
+    Tmp1 = SelectExpr(N.getOperand(0));
+    BuildMI(BB, PPC::FRSP, 1, Result).addReg(Tmp1);
+    return Result;
+
+  case ISD::FP_EXTEND:
+    assert (DestType == MVT::f64 &&
+            N.getOperand(0).getValueType() == MVT::f32 &&
+            "only f32 to f64 conversion supported here");
+    Tmp1 = SelectExpr(N.getOperand(0));
+    BuildMI(BB, PPC::FMR, 1, Result).addReg(Tmp1);
+    return Result;
+
+  case ISD::UINT_TO_FP:
+  case ISD::SINT_TO_FP: {
+    assert (N.getOperand(0).getValueType() == MVT::i32
+            && "int to float must operate on i32");
+    bool IsUnsigned = (ISD::UINT_TO_FP == opcode);
+    Tmp1 = SelectExpr(N.getOperand(0));  // Get the operand register
+    Tmp2 = MakeReg(MVT::f64); // temp reg to load the integer value into
+    Tmp3 = MakeReg(MVT::i32); // temp reg to hold the conversion constant
+
+    int FrameIdx = BB->getParent()->getFrameInfo()->CreateStackObject(8, 8);
+    MachineConstantPool *CP = BB->getParent()->getConstantPool();
+
+    if (IsUnsigned) {
+      unsigned ConstF = getConstDouble(0x1.000000p52);
+      // Store the hi & low halves of the fp value, currently in int regs
+      BuildMI(BB, PPC::LIS, 1, Tmp3).addSImm(0x4330);
+      addFrameReference(BuildMI(BB, PPC::STW, 3).addReg(Tmp3), FrameIdx);
+      addFrameReference(BuildMI(BB, PPC::STW, 3).addReg(Tmp1), FrameIdx, 4);
+      addFrameReference(BuildMI(BB, PPC::LFD, 2, Tmp2), FrameIdx);
+      // Generate the return value with a subtract
+      BuildMI(BB, PPC::FSUB, 2, Result).addReg(Tmp2).addReg(ConstF);
+    } else {
+      unsigned ConstF = getConstDouble(0x1.000008p52);
+      unsigned TmpL = MakeReg(MVT::i32);
+      // Store the hi & low halves of the fp value, currently in int regs
+      BuildMI(BB, PPC::LIS, 1, Tmp3).addSImm(0x4330);
+      addFrameReference(BuildMI(BB, PPC::STW, 3).addReg(Tmp3), FrameIdx);
+      BuildMI(BB, PPC::XORIS, 2, TmpL).addReg(Tmp1).addImm(0x8000);
+      addFrameReference(BuildMI(BB, PPC::STW, 3).addReg(TmpL), FrameIdx, 4);
+      addFrameReference(BuildMI(BB, PPC::LFD, 2, Tmp2), FrameIdx);
+      // Generate the return value with a subtract
+      BuildMI(BB, PPC::FSUB, 2, Result).addReg(Tmp2).addReg(ConstF);
+    }
+    return Result;
+  }
+  }
   return 0;
 }
 


Index: llvm/lib/Target/PowerPC/PowerPC.h
diff -u llvm/lib/Target/PowerPC/PowerPC.h:1.15 llvm/lib/Target/PowerPC/PowerPC.h:1.16
--- llvm/lib/Target/PowerPC/PowerPC.h:1.15	Thu Apr 21 18:20:02 2005
+++ llvm/lib/Target/PowerPC/PowerPC.h	Tue Jul 19 11:51:05 2005
@@ -28,8 +28,6 @@
 FunctionPass *createPPC64ISelPattern(TargetMachine &TM);
 FunctionPass *createDarwinAsmPrinter(std::ostream &OS, TargetMachine &TM);
 FunctionPass *createAIXAsmPrinter(std::ostream &OS, TargetMachine &TM);
-
-extern bool PPCCRopts;
 } // end namespace llvm;
 
 // GCC #defines PPC on Linux but we use it as our namespace name


Index: llvm/lib/Target/PowerPC/PowerPCTargetMachine.cpp
diff -u llvm/lib/Target/PowerPC/PowerPCTargetMachine.cpp:1.52 llvm/lib/Target/PowerPC/PowerPCTargetMachine.cpp:1.53
--- llvm/lib/Target/PowerPC/PowerPCTargetMachine.cpp:1.52	Fri Jun 24 21:48:37 2005
+++ llvm/lib/Target/PowerPC/PowerPCTargetMachine.cpp	Tue Jul 19 11:51:05 2005
@@ -30,18 +30,12 @@
 using namespace llvm;
 
 namespace llvm {
-  bool PPCCRopts;
   cl::opt<bool> AIX("aix",
                     cl::desc("Generate AIX/xcoff instead of Darwin/MachO"),
                     cl::Hidden);
   cl::opt<bool> EnablePPCLSR("enable-lsr-for-ppc",
                              cl::desc("Enable LSR for PPC (beta)"),
                              cl::Hidden);
-  cl::opt<bool, true> EnablePPCCRopts("enable-cc-opts",
-                            cl::desc("Enable opts using condition regs (beta)"),
-                            cl::location(PPCCRopts),
-                            cl::init(false),
-                            cl::Hidden);
 }
 
 namespace {





From sabre at nondot.org  Tue Jul 19 11:56:29 2005
From: sabre at nondot.org (Chris Lattner)
Date: Tue, 19 Jul 2005 11:56:29 -0500 (CDT)
Subject: [llvm-commits] CVS:
	llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
In-Reply-To: <200507191650.LAA01162@zion.cs.uiuc.edu>
References: <200507191650.LAA01162@zion.cs.uiuc.edu>
Message-ID: <Pine.LNX.4.61.0507191156040.20967@nondot.org>

On Tue, 19 Jul 2005, Nate Begeman wrote:
> Remove unnecessary FP_EXTEND. This causes worse codegen for SSE.

This actually caused incorrect code to be generated, right?

-Chris

> Diffs of the changes:  (+0 -3)
>
> SelectionDAGISel.cpp |    3 ---
> 1 files changed, 3 deletions(-)
>
>
> Index: llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
> diff -u llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.65 llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.66
> --- llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.65	Tue Jul  5 14:57:53 2005
> +++ llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp	Tue Jul 19 11:50:03 2005
> @@ -403,9 +403,6 @@
>       Op1 = DAG.getNode(ISD::ZERO_EXTEND, TmpVT, Op1);
>     break;
>   case MVT::f32:
> -    // Extend float to double.
> -    Op1 = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Op1);
> -    break;
>   case MVT::i64:
>   case MVT::f64:
>     break; // No extension needed!
>
>
>
> _______________________________________________
> llvm-commits mailing list
> llvm-commits at cs.uiuc.edu
> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
>

-Chris

-- 
http://nondot.org/sabre/
http://llvm.org/



From lattner at cs.uiuc.edu  Tue Jul 19 13:25:34 2005
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Tue, 19 Jul 2005 13:25:34 -0500
Subject: [llvm-commits] CVS: llvm-test/Makefile.nagfortran Makefile.FORTRAN 
Message-ID: <200507191825.NAA03842@zion.cs.uiuc.edu>



Changes in directory llvm-test:

Makefile.nagfortran added (r1.1)
Makefile.FORTRAN added (r1.1)
---
Log message:

initial support for NAG fortran


---
Diffs of the changes:  (+75 -0)

 Makefile.FORTRAN    |   36 ++++++++++++++++++++++++++++++++++++
 Makefile.nagfortran |   39 +++++++++++++++++++++++++++++++++++++++
 2 files changed, 75 insertions(+)


Index: llvm-test/Makefile.nagfortran
diff -c /dev/null llvm-test/Makefile.nagfortran:1.1
*** /dev/null	Tue Jul 19 13:25:33 2005
--- llvm-test/Makefile.nagfortran	Tue Jul 19 13:25:23 2005
***************
*** 0 ****
--- 1,39 ----
+ ##===- Makefile.nagfortran ---------------------------------*- Makefile -*-===##
+ #
+ #                     The LLVM Compiler Infrastructure
+ #
+ # This file was developed by Chris Lattner and is distributed under
+ # the University of Illinois Open Source License. See LICENSE.TXT for details.
+ # 
+ #===------------------------------------------------------------------------===#
+ #
+ # Enable running Fortran programs with LLVM by using NAGWare Fortran front-end
+ # to convert it to C.
+ #
+ ##===----------------------------------------------------------------------===##
+ 
+ include $(LEVEL)/Makefile.config
+ 
+ # Make sure the correct targets come first.
+ ifdef TEST
+ test::
+ else
+ all::
+ endif
+ 
+ ifneq ($(USE_F95),1)
+ all test::
+ 	echo "The f2c program was not found"
+ 	exit 1
+ endif
+ 
+ .PRECIOUS: %.c
+ 
+ clean::
+ 	rm -f $(Source:%.f=%.c)
+ 
+ %.c: %.f
+ 	$(F95) -w -S -O2 $< -o $@ $(NAGFORTRAN_FLAGS)
+ 
+ CPPFLAGS = -I$(F95_DIR)/lib/NAGWare 
+ LDFLAGS += $(F95_DIR)/lib/NAGWare/libf97.dylib $(F95_DIR)/lib/NAGWare/libf96.a


Index: llvm-test/Makefile.FORTRAN
diff -c /dev/null llvm-test/Makefile.FORTRAN:1.1
*** /dev/null	Tue Jul 19 13:25:34 2005
--- llvm-test/Makefile.FORTRAN	Tue Jul 19 13:25:23 2005
***************
*** 0 ****
--- 1,36 ----
+ ##===- Makefile.FORTRAN ------------------------------------*- Makefile -*-===##
+ #
+ #                     The LLVM Compiler Infrastructure
+ #
+ # This file was developed by Chris Lattner and is distributed under
+ # the University of Illinois Open Source License. See LICENSE.TXT for details.
+ # 
+ #===------------------------------------------------------------------------===#
+ #
+ # Enable running FORTRAN programs with LLVM using any available FORTRAN support.
+ #
+ ##===----------------------------------------------------------------------===##
+ 
+ include $(LEVEL)/Makefile.config
+ 
+ # Make sure the correct targets come first.
+ ifdef TEST
+ test::
+ else
+ all::
+ endif
+ 
+ # Include the correct Makefile given how FORTRAN is currently being supported.
+ 
+ ifeq ($(USE_F95),1)
+ include $(LEVEL)/Makefile.nagfortran
+ else
+ ifeq ($(USE_F2C),1)
+ include $(LEVEL)/Makefile.f2c
+ else
+ 
+ ## If FORTRAN is not supported, do nothing.
+ bytecode:
+ 
+ endif
+ endif





From lattner at cs.uiuc.edu  Tue Jul 19 13:57:23 2005
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Tue, 19 Jul 2005 13:57:23 -0500
Subject: [llvm-commits] CVS: llvm-test/Makefile.FORTRAN Makefile.nagfortran 
Message-ID: <200507191857.NAA04006@zion.cs.uiuc.edu>



Changes in directory llvm-test:

Makefile.FORTRAN updated: 1.1 -> 1.2
Makefile.nagfortran updated: 1.1 -> 1.2
---
Log message:

minor tweaks


---
Diffs of the changes:  (+1 -7)

 Makefile.FORTRAN    |    6 ------
 Makefile.nagfortran |    2 +-
 2 files changed, 1 insertion(+), 7 deletions(-)


Index: llvm-test/Makefile.FORTRAN
diff -u llvm-test/Makefile.FORTRAN:1.1 llvm-test/Makefile.FORTRAN:1.2
--- llvm-test/Makefile.FORTRAN:1.1	Tue Jul 19 13:25:23 2005
+++ llvm-test/Makefile.FORTRAN	Tue Jul 19 13:57:12 2005
@@ -21,16 +21,10 @@
 endif
 
 # Include the correct Makefile given how FORTRAN is currently being supported.
-
 ifeq ($(USE_F95),1)
 include $(LEVEL)/Makefile.nagfortran
 else
 ifeq ($(USE_F2C),1)
 include $(LEVEL)/Makefile.f2c
-else
-
-## If FORTRAN is not supported, do nothing.
-bytecode:
-
 endif
 endif


Index: llvm-test/Makefile.nagfortran
diff -u llvm-test/Makefile.nagfortran:1.1 llvm-test/Makefile.nagfortran:1.2
--- llvm-test/Makefile.nagfortran:1.1	Tue Jul 19 13:25:23 2005
+++ llvm-test/Makefile.nagfortran	Tue Jul 19 13:57:12 2005
@@ -23,7 +23,7 @@
 
 ifneq ($(USE_F95),1)
 all test::
-	echo "The f2c program was not found"
+	echo "NAG Fortran is not support?"
 	exit 1
 endif
 





From lattner at cs.uiuc.edu  Tue Jul 19 14:05:58 2005
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Tue, 19 Jul 2005 14:05:58 -0500
Subject: [llvm-commits] 
	CVS: llvm-test/External/SPEC/CFP2000/172.mgrid/Makefile
Message-ID: <200507191905.OAA04202@zion.cs.uiuc.edu>



Changes in directory llvm-test/External/SPEC/CFP2000/172.mgrid:

Makefile updated: 1.2 -> 1.3
---
Log message:

Make these tests all work with NAG fortran or F2C


---
Diffs of the changes:  (+1 -2)

 Makefile |    3 +--
 1 files changed, 1 insertion(+), 2 deletions(-)


Index: llvm-test/External/SPEC/CFP2000/172.mgrid/Makefile
diff -u llvm-test/External/SPEC/CFP2000/172.mgrid/Makefile:1.2 llvm-test/External/SPEC/CFP2000/172.mgrid/Makefile:1.3
--- llvm-test/External/SPEC/CFP2000/172.mgrid/Makefile:1.2	Wed Mar 16 22:48:30 2005
+++ llvm-test/External/SPEC/CFP2000/172.mgrid/Makefile	Tue Jul 19 14:05:46 2005
@@ -1,13 +1,12 @@
 LEVEL = ../../../..
 
 Source = mgrid.f
-include $(LEVEL)/Makefile.f2c
 
 FP_ABSTOLERANCE=1.0e-12
 FP_TOLERANCE=0.001
 
-
 STDIN_FILENAME  = mgrid.in
 STDOUT_FILENAME = mgrid.out
 
+include $(LEVEL)/Makefile.FORTRAN
 include ../../Makefile.spec2000





From lattner at cs.uiuc.edu  Tue Jul 19 14:05:58 2005
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Tue, 19 Jul 2005 14:05:58 -0500
Subject: [llvm-commits] 
	CVS: llvm-test/External/SPEC/CFP2000/173.applu/Makefile
Message-ID: <200507191905.OAA04210@zion.cs.uiuc.edu>



Changes in directory llvm-test/External/SPEC/CFP2000/173.applu:

Makefile updated: 1.1 -> 1.2
---
Log message:

Make these tests all work with NAG fortran or F2C


---
Diffs of the changes:  (+1 -1)

 Makefile |    2 +-
 1 files changed, 1 insertion(+), 1 deletion(-)


Index: llvm-test/External/SPEC/CFP2000/173.applu/Makefile
diff -u llvm-test/External/SPEC/CFP2000/173.applu/Makefile:1.1 llvm-test/External/SPEC/CFP2000/173.applu/Makefile:1.2
--- llvm-test/External/SPEC/CFP2000/173.applu/Makefile:1.1	Wed Oct  6 16:40:22 2004
+++ llvm-test/External/SPEC/CFP2000/173.applu/Makefile	Tue Jul 19 14:05:46 2005
@@ -1,9 +1,9 @@
 LEVEL = ../../../..
 
 Source = applu.f
-include $(LEVEL)/Makefile.f2c
 
 STDIN_FILENAME  = applu.in
 STDOUT_FILENAME = applu.out
 
+include $(LEVEL)/Makefile.FORTRAN
 include ../../Makefile.spec2000





From lattner at cs.uiuc.edu  Tue Jul 19 14:05:58 2005
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Tue, 19 Jul 2005 14:05:58 -0500
Subject: [llvm-commits] 
	CVS: llvm-test/External/SPEC/CFP2000/171.swim/Makefile
Message-ID: <200507191905.OAA04204@zion.cs.uiuc.edu>



Changes in directory llvm-test/External/SPEC/CFP2000/171.swim:

Makefile updated: 1.1 -> 1.2
---
Log message:

Make these tests all work with NAG fortran or F2C


---
Diffs of the changes:  (+2 -2)

 Makefile |    4 ++--
 1 files changed, 2 insertions(+), 2 deletions(-)


Index: llvm-test/External/SPEC/CFP2000/171.swim/Makefile
diff -u llvm-test/External/SPEC/CFP2000/171.swim/Makefile:1.1 llvm-test/External/SPEC/CFP2000/171.swim/Makefile:1.2
--- llvm-test/External/SPEC/CFP2000/171.swim/Makefile:1.1	Wed Oct  6 16:37:29 2004
+++ llvm-test/External/SPEC/CFP2000/171.swim/Makefile	Tue Jul 19 14:05:46 2005
@@ -1,10 +1,10 @@
 LEVEL = ../../../..
 
 Source = swim.f
-include $(LEVEL)/Makefile.f2c
-
+NAGFORTRAN_FLAGS = 
 STDIN_FILENAME  = swim.in
 STDOUT_FILENAME = swim.out
 FP_ABSTOLERANCE = 0.000001
 
+include $(LEVEL)/Makefile.FORTRAN
 include ../../Makefile.spec2000





From lattner at cs.uiuc.edu  Tue Jul 19 14:05:58 2005
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Tue, 19 Jul 2005 14:05:58 -0500
Subject: [llvm-commits] 
	CVS: llvm-test/External/SPEC/CFP2000/168.wupwise/Makefile
Message-ID: <200507191905.OAA04214@zion.cs.uiuc.edu>



Changes in directory llvm-test/External/SPEC/CFP2000/168.wupwise:

Makefile updated: 1.1 -> 1.2
---
Log message:

Make these tests all work with NAG fortran or F2C


---
Diffs of the changes:  (+2 -2)

 Makefile |    4 ++--
 1 files changed, 2 insertions(+), 2 deletions(-)


Index: llvm-test/External/SPEC/CFP2000/168.wupwise/Makefile
diff -u llvm-test/External/SPEC/CFP2000/168.wupwise/Makefile:1.1 llvm-test/External/SPEC/CFP2000/168.wupwise/Makefile:1.2
--- llvm-test/External/SPEC/CFP2000/168.wupwise/Makefile:1.1	Wed Oct  6 15:47:56 2004
+++ llvm-test/External/SPEC/CFP2000/168.wupwise/Makefile	Tue Jul 19 14:05:46 2005
@@ -5,9 +5,9 @@
          dlarnd.f  lsame.f   muldoe.f  su3mul.f  zaxpy.f    zscal.f \
          dznrm2.f  phinit.f  uinith.f  zcopy.f
 
-include $(LEVEL)/Makefile.f2c
-
 STDIN_FILENAME  = wupwise.in
 STDOUT_FILENAME = wupwise.out
+NAGFORTRAN_FLAGS = -dusty -dcfuns
 
+include $(LEVEL)/Makefile.FORTRAN
 include ../../Makefile.spec2000





From lattner at cs.uiuc.edu  Tue Jul 19 17:32:26 2005
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Tue, 19 Jul 2005 17:32:26 -0500
Subject: [llvm-commits] CVS: llvm-test/External/SPEC/CFP2000/200.sixtrack/
Message-ID: <200507192232.RAA08108@zion.cs.uiuc.edu>



Changes in directory llvm-test/External/SPEC/CFP2000/200.sixtrack:

---
Log message:

Directory /var/cvs/llvm/llvm-test/External/SPEC/CFP2000/200.sixtrack added to the repository


---
Diffs of the changes:  (+0 -0)

 0 files changed





From lattner at cs.uiuc.edu  Tue Jul 19 17:33:22 2005
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Tue, 19 Jul 2005 17:33:22 -0500
Subject: [llvm-commits] 
	CVS: llvm-test/External/SPEC/CFP2000/200.sixtrack/Makefile
Message-ID: <200507192233.RAA08183@zion.cs.uiuc.edu>



Changes in directory llvm-test/External/SPEC/CFP2000/200.sixtrack:

Makefile added (r1.1)
---
Log message:

NAG fortran supports this program, though f2c doesn't.


---
Diffs of the changes:  (+45 -0)

 Makefile |   45 +++++++++++++++++++++++++++++++++++++++++++++
 1 files changed, 45 insertions(+)


Index: llvm-test/External/SPEC/CFP2000/200.sixtrack/Makefile
diff -c /dev/null llvm-test/External/SPEC/CFP2000/200.sixtrack/Makefile:1.1
*** /dev/null	Tue Jul 19 17:33:21 2005
--- llvm-test/External/SPEC/CFP2000/200.sixtrack/Makefile	Tue Jul 19 17:33:11 2005
***************
*** 0 ****
--- 1,45 ----
+ LEVEL = ../../../..
+ 
+ Source = abend.f         dinv.f          intd6.f         search.f   \
+          adia.f          dist1.f         intepr.f        sinpro.f   \
+          adib.f          distance.f      join.f          sixdaco6.f \
+          ambm6.f         dlie6.f         lie6.f          subre.f    \
+          analie6.f       eig66.f         linopt.f        subsea.f   \
+          betalf.f        envada.f        loesd.f         sumpos.f   \
+          block.f         envar.f         lostpar2.f      synoda.f   \
+          blockdis.f      envardis.f      lostpar3.f      synuthck.f \
+          caconv.f        envars.f        lostpart.f      take6.f    \
+          calrms.f        envarsv.f       maincr.f        taked6.f   \
+          chroma.f        envquad.f       mainia6.f       thck4d.f   \
+          cinvar.f        errf.f          matrix.f        thck6d.f   \
+          clor6.f         errff.f         maxmin.f        thck6dua.f \
+          clorb.f         error.f         midbloc6.f      thin4d.f   \
+          clorb2.f        fexpo6.f        mul66.f         thin6d.f   \
+          combel.f        fft.f           mywwerf.f       thin6dua.f \
+          comnul.f        fit.f           orbinit.f       trauthck.f \
+          corrorb.f       flush.f         ord.f           trauthin.f \
+          cpart6.f        forest6.f       orderma6.f      trx6.f     \
+          cphase.f        foxys.f         phasad.f        tuer6.f    \
+          cpltwis.f       gam6.f          postpr.f        umlau6.f   \
+          creat6.f        gbm6.f          putorb.f        umlauf.f   \
+          ctrbasi6.f      gofix6.f        qmod.f          write4.f   \
+          dacond6.f       hbook.f         ranecu.f        write6.f   \
+          dacopd6.f       htal.f          resb6.f         writebin.f \
+          dalie6s.f       htbl.f          resex.f         writelin.f \
+          dalind6.f       htls.f          resl6.f         wzset.f    \
+          daprid6.f       htrl.f          rext6.f         wzsubf.f   \
+          daten.f         htul.f          ripple.f        wzsubv.f   \
+          decoup.f        hyper6.f        rmod.f          xuflow.f   \
+          detune.f        igmeta.f        rotatio6.f
+ 
+ FP_ABSTOLERANCE=0.0005
+ FP_TOLERANCE=0.0005
+ 
+ STDIN_FILENAME  = inp.in
+ STDOUT_FILENAME = inp.out
+ NAGFORTRAN_FLAGS = -dusty
+ 
+ include $(LEVEL)/Makefile.FORTRAN
+ include ../../Makefile.spec2000
+ 
+ CPPFLAGS += -DINT64='long long'





From lattner at cs.uiuc.edu  Tue Jul 19 19:59:55 2005
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Tue, 19 Jul 2005 19:59:55 -0500
Subject: [llvm-commits] CVS: llvm-test/External/SPEC/CFP2000/191.fma3d/
Message-ID: <200507200059.TAA08737@zion.cs.uiuc.edu>



Changes in directory llvm-test/External/SPEC/CFP2000/191.fma3d:

---
Log message:

Directory /var/cvs/llvm/llvm-test/External/SPEC/CFP2000/191.fma3d added to the repository


---
Diffs of the changes:  (+0 -0)

 0 files changed





From lattner at cs.uiuc.edu  Tue Jul 19 20:00:46 2005
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Tue, 19 Jul 2005 20:00:46 -0500
Subject: [llvm-commits] 
	CVS: llvm-test/External/SPEC/CFP2000/191.fma3d/Makefile
Message-ID: <200507200100.UAA08828@zion.cs.uiuc.edu>



Changes in directory llvm-test/External/SPEC/CFP2000/191.fma3d:

Makefile added (r1.1)
---
Log message:

Add info for this to compile with NAG


---
Diffs of the changes:  (+75 -0)

 Makefile |   75 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
 1 files changed, 75 insertions(+)


Index: llvm-test/External/SPEC/CFP2000/191.fma3d/Makefile
diff -c /dev/null llvm-test/External/SPEC/CFP2000/191.fma3d/Makefile:1.1
*** /dev/null	Tue Jul 19 20:00:45 2005
--- llvm-test/External/SPEC/CFP2000/191.fma3d/Makefile	Tue Jul 19 20:00:35 2005
***************
*** 0 ****
--- 1,75 ----
+ LEVEL = ../../../..
+ 
+ Source = fma3d.f90 beam_.f90 include_file_.f90 penta_.f90 segment_set_.f90 \
+          body_force_.f90 indx_.f90 periodic_bc_.f90 sliding_interface_.f90 \
+          constrained_node_.f90 layering_.f90 plate_pair_.f90 sliding_node_.f90 \
+          contact_node_.f90 location_.f90 platq_.f90 spot_weld_.f90 \
+          contact_surface_.f90 lsold_.f90 platt_.f90 spring_.f90 coord_.f90 massprop_.f90 \
+          pressure_bc_.f90 spring_bc_.f90 damper_.f90 material_.f90 property_.f90 \
+          state_variables_.f90 damper_bc_.f90 mean_stress_.f90 shared_common_data.f90 \
+          stress_.f90 displacement_bc_.f90 membq_.f90 qa_record_.f90 \
+          tabulated_function_.f90 element_set_.f90 membt_.f90 relink_scratch_.f90 \
+          tetra_.f90 enumerated_sets_.f90 motion_.f90 results_.f90 tied_bc_.f90 \
+          force_.f90 nodal_point_mass_.f90 rigid_body_.f90 truss_.f90 force_bc_.f90 \
+          node_.f90 rigid_body_mass_.f90 value_.f90 gauge1d_.f90 node_set_.f90 \
+          rigid_wall_bc_.f90 velocity_ic_.f90 gauge2d_.f90 nonreflecting_bc_.f90 \
+          section_1d_.f90 gauge3d_.f90 nrbc_data_.f90 section_2d_.f90 hexah_.f90 \
+          output_.f90 segment_.f90 .f90 lsold.f90 damper.f90 spring.f90 material_00.f90 \
+          material_10.f90 material_11.f90 material_17.f90 material_22.f90 \
+          material_25.f90 material_32.f90 material_33.f90 material_34a.f90 \
+          material_36.f90 material_38.f90 material_dm.f90 material_sp.f90 .f90 sort.f90 \
+          pdb.f90 beam.f90 membq.f90 membt.f90 penta.f90 tetra.f90 hexah.f90 platq.f90 \
+          truss.f90 platt.f90 fma1.f90 getirv.f90 relink.f90 output.f90 fma2.f90 \
+          partition.f90 strain.f90 slide.f90
+ 
+ FP_ABSTOLERANCE=1e-7
+ FP_TOLERANCE=0.04
+ 
+ STDIN_FILENAME  = fma3d.in
+ STDOUT_FILENAME = fma3d.out
+ NAGFORTRAN_FLAGS = -dusty -maxcontin=69
+ 
+ 
+ 
+ include $(LEVEL)/Makefile.FORTRAN
+ include ../../Makefile.spec2000
+ #CPPFLAGS += -DINT64='long long'
+ 
+ 
+ # Dependencies between files (due to use of modules) autogenerated by Chris' script
+ # from 'USE' directives in the source.
+ 
+ beam.c: $(addsuffix .c,  beam_ material_ mean_stress_ motion_ node_ section_1d_ shared_common_data state_variables_)
+ damper.c: $(addsuffix .c,  damper_ material_ motion_ node_ shared_common_data state_variables_)
+ fma1.c: $(addsuffix .c,  beam_ body_force_ constrained_node_ contact_node_ contact_surface_ coord_ damper_ damper_bc_ displacement_bc_ element_set_ enumerated_sets_ enumerated_sets_ force_ force_bc_ gauge1d_ gauge2d_ gauge3d_ hexah_ hexah_ include_file_ indx_ layering_ location_ lsold_ massprop_ material_ mean_stress_ membq_ membq_ membt_ motion_ nodal_point_mass_ node_ node_set_ nonreflecting_bc_ nrbc_data_ output_ penta_ periodic_bc_ plate_pair_ platq_ platt_ pressure_bc_ property_ qa_record_ relink_scratch_ results_ rigid_body_ rigid_body_mass_ rigid_wall_bc_ section_1d_ section_2d_ segment_ segment_set_ shared_common_data sliding_interface_ sliding_node_ spot_weld_ spring_ spring_bc_ state_variables_ stress_ tabulated_function_ tetra_ tied_bc_ truss_ value_ velocity_ic_)
+ fma2.c: $(addsuffix .c,  beam_ body_force_ constrained_node_ contact_node_ contact_surface_ coord_ damper_ damper_bc_ displacement_bc_ element_set_ enumerated_sets_ enumerated_sets_ force_ force_bc_ gauge1d_ gauge2d_ gauge3d_ hexah_ indx_ layering_ lsold_ massprop_ material_ membq_ membt_ motion_ nodal_point_mass_ node_ node_set_ nonreflecting_bc_ nrbc_data_ penta_ periodic_bc_ plate_pair_ platq_ platt_ pressure_bc_ qa_record_ results_ rigid_body_ rigid_body_mass_ rigid_wall_bc_ section_1d_ section_2d_ segment_ segment_set_ shared_common_data sliding_interface_ sliding_node_ spot_weld_ spring_ spring_bc_ state_variables_ stress_ tabulated_function_ tetra_ tied_bc_ truss_)
+ getirv.c: $(addsuffix .c,  shared_common_data value_)
+ hexah.c: $(addsuffix .c,  hexah_ material_ motion_ node_ shared_common_data state_variables_)
+ lsold.c: $(addsuffix .c,  force_ hexah_ hexah_ hexah layering_ lsold_ material_ membq_ membq_ motion_ node_ section_2d_ shared_common_data state_variables_)
+ material_00.c: $(addsuffix .c,  beam_ damper_ damper_bc_ hexah_ layering_ lsold_ material_ membq_ membt_ penta_ platq_ platt_ section_1d_ section_2d_ shared_common_data spring_ spring_bc_ state_variables_ stress_ tabulated_function_ tetra_ truss_)
+ material_10.c: $(addsuffix .c,  layering_ material_ section_1d_ section_2d_ shared_common_data state_variables_)
+ material_11.c: $(addsuffix .c,  layering_ material_ section_1d_ section_2d_ shared_common_data state_variables_)
+ material_17.c: $(addsuffix .c,  layering_ material_ section_1d_ section_2d_ shared_common_data state_variables_)
+ material_22.c: $(addsuffix .c,  material_ section_2d_ shared_common_data state_variables_)
+ material_25.c: $(addsuffix .c,  layering_ material_ section_1d_ section_2d_ shared_common_data state_variables_)
+ material_32.c: $(addsuffix .c,  layering_ material_ shared_common_data state_variables_)
+ material_33.c: $(addsuffix .c,  layering_ material_ shared_common_data state_variables_)
+ material_34a.c: $(addsuffix .c,  layering_ material_ shared_common_data state_variables_)
+ material_36.c: $(addsuffix .c,  layering_ material_ shared_common_data state_variables_)
+ material_38.c: $(addsuffix .c,  layering_ material_ shared_common_data state_variables_ tabulated_function_)
+ material_dm.c: $(addsuffix .c,  material_ section_1d_ shared_common_data state_variables_)
+ material_sp.c: $(addsuffix .c,  material_ section_1d_ shared_common_data state_variables_)
+ membq.c: $(addsuffix .c,  material_ membq_ motion_ node_ section_2d_ shared_common_data state_variables_)
+ membt.c: $(addsuffix .c,  material_ membt_ motion_ node_ section_2d_ shared_common_data state_variables_)
+ output.c: $(addsuffix .c,  beam_ body_force_ constrained_node_ contact_node_ contact_surface_ coord_ damper_ damper_bc_ displacement_bc_ element_set_ enumerated_sets_ force_ force_bc_ gauge1d_ gauge2d_ gauge3d_ hexah_ include_file_ indx_ layering_ lsold_ massprop_ material_ membq_ membt_ motion_ nodal_point_mass_ node_ node_set_ nonreflecting_bc_ nrbc_data_ penta_ periodic_bc_ plate_pair_ platq_ platt_ pressure_bc_ property_ qa_record_ results_ rigid_body_ rigid_body_mass_ rigid_wall_bc_ section_1d_ section_2d_ segment_ segment_set_ shared_common_data sliding_interface_ sliding_node_ spot_weld_ spring_ spring_bc_ state_variables_ stress_ tabulated_function_ tetra_ tied_bc_ truss_)
+ partition.c: $(addsuffix .c,  beam_ constrained_node_ contact_node_ damper_ damper_bc_ displacement_bc_ enumerated_sets_ hexah_ lsold_ membq_ membt_ node_ node_set_ nonreflecting_bc_ penta_ periodic_bc_ platq_ platt_ rigid_body_ rigid_wall_bc_ segment_ shared_common_data spot_weld_ spring_ spring_bc_ tetra_ tied_bc_ truss_)
+ pdb.c: $(addsuffix .c,  beam_ body_force_ constrained_node_ contact_node_ contact_surface_ coord_ damper_ damper_bc_ displacement_bc_ element_set_ enumerated_sets_ force_ force_bc_ gauge1d_ gauge2d_ gauge3d_ hexah_ indx_ layering_ lsold_ massprop_ material_ membq_ membt_ motion_ nodal_point_mass_ node_ node_set_ nonreflecting_bc_ nrbc_data_ penta_ periodic_bc_ plate_pair_ platq_ platt_ pressure_bc_ qa_record_ results_ rigid_body_ rigid_body_mass_ rigid_wall_bc_ section_1d_ section_2d_ segment_ segment_set_ shared_common_data sliding_interface_ sliding_node_ spot_weld_ spring_ spring_bc_ state_variables_ stress_ tabulated_function_ tetra_ tied_bc_ truss_)
+ penta.c: $(addsuffix .c,  material_ motion_ node_ penta_ shared_common_data state_variables_)
+ platq.c: $(addsuffix .c,  material_ motion_ node_ platq_ section_2d_ shared_common_data state_variables_ stress_ tabulated_function_)
+ platt.c: $(addsuffix .c,  material_ motion_ node_ platt_ section_2d_ shared_common_data state_variables_ stress_ tabulated_function_)
+ relink.c: $(addsuffix .c,  beam_ body_force_ constrained_node_ damper_ damper_bc_ displacement_bc_ element_set_ enumerated_sets_ force_ force_bc_ gauge1d_ gauge2d_ gauge3d_ hexah_ layering_ lsold_ massprop_ material_ membq_ membt_ motion_ nodal_point_mass_ node_ node_set_ nonreflecting_bc_ output_ penta_ periodic_bc_ plate_pair_ platq_ platt_ pressure_bc_ qa_record_ relink_scratch_ results_ rigid_body_ rigid_body_mass_ rigid_wall_bc_ section_1d_ section_2d_ segment_ segment_set_ shared_common_data sliding_interface_ spot_weld_ spring_ spring_bc_ tabulated_function_ tetra_ tied_bc_ truss_ velocity_ic_)
+ slide.c: $(addsuffix .c,  contact_node_ contact_surface_ coord_ force_ indx_ motion_ node_ shared_common_data sliding_interface_ sliding_node_)
+ spring.c: $(addsuffix .c,  material_ motion_ node_ shared_common_data spring_ state_variables_)
+ strain.c: $(addsuffix .c,  beam_ gauge1d_ gauge2d_ gauge3d_ hexah_ lsold_ membq_ membt_ motion_ node_ penta_ platq_ platt_ section_1d_ section_2d_ shared_common_data tetra_ truss_)
+ tetra.c: $(addsuffix .c,  material_ motion_ node_ shared_common_data state_variables_ tetra_)
+ truss.c: $(addsuffix .c,  material_ motion_ node_ section_1d_ shared_common_data state_variables_ truss_)





From lattner at cs.uiuc.edu  Tue Jul 19 20:08:41 2005
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Tue, 19 Jul 2005 20:08:41 -0500
Subject: [llvm-commits] CVS: llvm-test/External/SPEC/CFP2000/189.lucas/
Message-ID: <200507200108.UAA08898@zion.cs.uiuc.edu>



Changes in directory llvm-test/External/SPEC/CFP2000/189.lucas:

---
Log message:

Directory /var/cvs/llvm/llvm-test/External/SPEC/CFP2000/189.lucas added to the repository


---
Diffs of the changes:  (+0 -0)

 0 files changed





From lattner at cs.uiuc.edu  Tue Jul 19 20:09:06 2005
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Tue, 19 Jul 2005 20:09:06 -0500
Subject: [llvm-commits] 
	CVS: llvm-test/External/SPEC/CFP2000/189.lucas/Makefile
Message-ID: <200507200109.UAA08955@zion.cs.uiuc.edu>



Changes in directory llvm-test/External/SPEC/CFP2000/189.lucas:

Makefile added (r1.1)
---
Log message:

add lucas with the NAG fortran fe


---
Diffs of the changes:  (+15 -0)

 Makefile |   15 +++++++++++++++
 1 files changed, 15 insertions(+)


Index: llvm-test/External/SPEC/CFP2000/189.lucas/Makefile
diff -c /dev/null llvm-test/External/SPEC/CFP2000/189.lucas/Makefile:1.1
*** /dev/null	Tue Jul 19 20:09:05 2005
--- llvm-test/External/SPEC/CFP2000/189.lucas/Makefile	Tue Jul 19 20:08:55 2005
***************
*** 0 ****
--- 1,15 ----
+ LEVEL = ../../../..
+ 
+ Source = lucas_distrib_spec.f90
+ 
+ #FP_ABSTOLERANCE=1e-7
+ #FP_TOLERANCE=0.04
+ 
+ STDIN_FILENAME  = lucas2.in
+ STDOUT_FILENAME = lucas2.out
+ #NAGFORTRAN_FLAGS = -dusty -maxcontin=69
+ 
+ include $(LEVEL)/Makefile.FORTRAN
+ include ../../Makefile.spec2000
+ CPPFLAGS += -DINT64='long long'
+ 





From lattner at cs.uiuc.edu  Tue Jul 19 20:13:53 2005
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Tue, 19 Jul 2005 20:13:53 -0500
Subject: [llvm-commits] CVS: llvm-test/Makefile.nagfortran 
Message-ID: <200507200113.UAA09020@zion.cs.uiuc.edu>



Changes in directory llvm-test:

Makefile.nagfortran updated: 1.2 -> 1.3
---
Log message:

add support for files with the .f90 suffix, pass extra link options to 
build programs correctly


---
Diffs of the changes:  (+5 -1)

 Makefile.nagfortran |    6 +++++-
 1 files changed, 5 insertions(+), 1 deletion(-)


Index: llvm-test/Makefile.nagfortran
diff -u llvm-test/Makefile.nagfortran:1.2 llvm-test/Makefile.nagfortran:1.3
--- llvm-test/Makefile.nagfortran:1.2	Tue Jul 19 13:57:12 2005
+++ llvm-test/Makefile.nagfortran	Tue Jul 19 20:13:42 2005
@@ -35,5 +35,9 @@
 %.c: %.f
 	$(F95) -w -S -O2 $< -o $@ $(NAGFORTRAN_FLAGS)
 
+%.c: %.f90
+	$(F95) -w -S -O2 $< -o $@ $(NAGFORTRAN_FLAGS)
+
+
 CPPFLAGS = -I$(F95_DIR)/lib/NAGWare 
-LDFLAGS += $(F95_DIR)/lib/NAGWare/libf97.dylib $(F95_DIR)/lib/NAGWare/libf96.a
+LDFLAGS += $(F95_DIR)/lib/NAGWare/quickfit.o -Xlinker -flat_namespace $(F95_DIR)/lib/NAGWare/libf97.dylib $(F95_DIR)/lib/NAGWare/libf96.a





From lattner at cs.uiuc.edu  Tue Jul 19 20:32:59 2005
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Tue, 19 Jul 2005 20:32:59 -0500
Subject: [llvm-commits] CVS: llvm-test/External/SPEC/CFP2000/187.facerec/
Message-ID: <200507200132.UAA09086@zion.cs.uiuc.edu>



Changes in directory llvm-test/External/SPEC/CFP2000/187.facerec:

---
Log message:

Directory /var/cvs/llvm/llvm-test/External/SPEC/CFP2000/187.facerec added to the repository


---
Diffs of the changes:  (+0 -0)

 0 files changed





From lattner at cs.uiuc.edu  Tue Jul 19 20:33:54 2005
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Tue, 19 Jul 2005 20:33:54 -0500
Subject: [llvm-commits] 
	CVS: llvm-test/External/SPEC/CFP2000/187.facerec/Makefile
Message-ID: <200507200133.UAA09143@zion.cs.uiuc.edu>



Changes in directory llvm-test/External/SPEC/CFP2000/187.facerec:

Makefile added (r1.1)
---
Log message:

add facerec, which works with NAG


---
Diffs of the changes:  (+23 -0)

 Makefile |   23 +++++++++++++++++++++++
 1 files changed, 23 insertions(+)


Index: llvm-test/External/SPEC/CFP2000/187.facerec/Makefile
diff -c /dev/null llvm-test/External/SPEC/CFP2000/187.facerec/Makefile:1.1
*** /dev/null	Tue Jul 19 20:33:53 2005
--- llvm-test/External/SPEC/CFP2000/187.facerec/Makefile	Tue Jul 19 20:33:43 2005
***************
*** 0 ****
--- 1,23 ----
+ LEVEL = ../../../..
+ 
+ Source = cfftb.f90 cfftf.f90 cffti.f90 FaceRec.f90 fft2d.f90 \
+          imageRoutines.f90 fft2d.f90 graphRoutines.f90 \
+          gaborRoutines.f90 parameterRoutines.f90 FaceRecTypes.f90
+ 
+ FP_ABSTOLERANCE=2.0e-7
+ FP_TOLERANCE=0.001
+ 
+ STDIN_FILENAME  = $(RUN_TYPE).in
+ STDOUT_FILENAME = $(RUN_TYPE).out
+ NAGFORTRAN_FLAGS = -kind=byte -dusty -I $(SPEC_BENCH_DIR)/src
+ 
+ 
+ include $(LEVEL)/Makefile.FORTRAN
+ include ../../Makefile.spec2000
+ CPPFLAGS += -DINT64='long long'
+ 
+ FaceRec.c: FaceRecTypes.c gaborRoutines.c graphRoutines.c imageRoutines.c parameterRoutines.c
+ gaborRoutines.c: FaceRecTypes.c fft2d.c imageRoutines.c 
+ graphRoutines.c: FaceRecTypes.c gaborRoutines.c imageRoutines.c FaceRecTypes.c 
+ imageRoutines.c: FaceRecTypes.c fft2d.c
+ parameterRoutines.c: FaceRecTypes.c





From lattner at cs.uiuc.edu  Tue Jul 19 22:56:59 2005
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Tue, 19 Jul 2005 22:56:59 -0500
Subject: [llvm-commits] 
	CVS: llvm/test/Regression/CodeGen/X86/commute-two-addr.ll
Message-ID: <200507200356.WAA09603@zion.cs.uiuc.edu>



Changes in directory llvm/test/Regression/CodeGen/X86:

commute-two-addr.ll updated: 1.2 -> 1.3
---
Log message:

set the target triple so that we don't fail due to X86 abi issues


---
Diffs of the changes:  (+3 -0)

 commute-two-addr.ll |    3 +++
 1 files changed, 3 insertions(+)


Index: llvm/test/Regression/CodeGen/X86/commute-two-addr.ll
diff -u llvm/test/Regression/CodeGen/X86/commute-two-addr.ll:1.2 llvm/test/Regression/CodeGen/X86/commute-two-addr.ll:1.3
--- llvm/test/Regression/CodeGen/X86/commute-two-addr.ll:1.2	Mon May  9 00:54:27 2005
+++ llvm/test/Regression/CodeGen/X86/commute-two-addr.ll	Tue Jul 19 22:56:48 2005
@@ -4,6 +4,9 @@
 ; Make sure there are only 3 mov's for each testcase
 ; RUN: llvm-as < %s | llc -march=x86 -x86-asm-syntax=intel | grep 'mov ' | wc -l | grep 6
 
+
+target triple = "i686-pc-linux-gnu"
+
 %G = external global int
 
 declare void %ext(int)





From lattner at cs.uiuc.edu  Wed Jul 20 11:29:32 2005
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Wed, 20 Jul 2005 11:29:32 -0500
Subject: [llvm-commits] CVS: llvm/lib/ExecutionEngine/JIT/JITEmitter.cpp 
Message-ID: <200507201629.LAA19115@zion.cs.uiuc.edu>



Changes in directory llvm/lib/ExecutionEngine/JIT:

JITEmitter.cpp updated: 1.68 -> 1.69
---
Log message:

count the number of relocations performed.


---
Diffs of the changes:  (+3 -0)

 JITEmitter.cpp |    3 +++
 1 files changed, 3 insertions(+)


Index: llvm/lib/ExecutionEngine/JIT/JITEmitter.cpp
diff -u llvm/lib/ExecutionEngine/JIT/JITEmitter.cpp:1.68 llvm/lib/ExecutionEngine/JIT/JITEmitter.cpp:1.69
--- llvm/lib/ExecutionEngine/JIT/JITEmitter.cpp:1.68	Tue Jul 12 10:51:55 2005
+++ llvm/lib/ExecutionEngine/JIT/JITEmitter.cpp	Wed Jul 20 11:29:20 2005
@@ -30,6 +30,7 @@
 
 namespace {
   Statistic<> NumBytes("jit", "Number of bytes of machine code compiled");
+  Statistic<> NumRelos("jit", "Number of relocations applied");
   JIT *TheJIT = 0;
 }
 
@@ -391,6 +392,8 @@
   NumBytes += CurByte-CurBlock;
 
   if (!Relocations.empty()) {
+    NumRelos += Relocations.size();
+
     // Resolve the relocations to concrete pointers.
     for (unsigned i = 0, e = Relocations.size(); i != e; ++i) {
       MachineRelocation &MR = Relocations[i];





From lattner at cs.uiuc.edu  Wed Jul 20 12:05:19 2005
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Wed, 20 Jul 2005 12:05:19 -0500
Subject: [llvm-commits] CVS: llvm-test/External/SPEC/CFP2000/178.galgel/
Message-ID: <200507201705.MAA19470@zion.cs.uiuc.edu>



Changes in directory llvm-test/External/SPEC/CFP2000/178.galgel:

---
Log message:

Directory /var/cvs/llvm/llvm-test/External/SPEC/CFP2000/178.galgel added to the repository


---
Diffs of the changes:  (+0 -0)

 0 files changed





From lattner at cs.uiuc.edu  Wed Jul 20 12:06:09 2005
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Wed, 20 Jul 2005 12:06:09 -0500
Subject: [llvm-commits] 
	CVS: llvm-test/External/SPEC/CFP2000/178.galgel/Makefile
Message-ID: <200507201706.MAA19527@zion.cs.uiuc.edu>



Changes in directory llvm-test/External/SPEC/CFP2000/178.galgel:

Makefile added (r1.1)
---
Log message:

add 178.galgel


---
Diffs of the changes:  (+30 -0)

 Makefile |   30 ++++++++++++++++++++++++++++++
 1 files changed, 30 insertions(+)


Index: llvm-test/External/SPEC/CFP2000/178.galgel/Makefile
diff -c /dev/null llvm-test/External/SPEC/CFP2000/178.galgel/Makefile:1.1
*** /dev/null	Wed Jul 20 12:06:08 2005
--- llvm-test/External/SPEC/CFP2000/178.galgel/Makefile	Wed Jul 20 12:05:57 2005
***************
*** 0 ****
--- 1,30 ----
+ LEVEL = ../../../..
+ 
+ Source = modules.f90 ab.f90 arhbt.f90 arhim.f90 bifg21.f90 bifgel.f90          \
+             bifoag.f90 cyklap.f90 eigQR.f90 farhim.f90 funht.f90 funns.f90     \
+             galgel.f90 grsyst.f90 htxyl.f90 htxynl.f90 newtap.f90 newtlap.f90  \
+             nsxyar.f90 nsxyl.f90 nsxynl.f90 pollin.f90 polnel.f90 pro.f90      \
+             syshtL.f90 syshtN.f90 sysnsL.f90 sysnsN.f90 tempbt.f90 tempo.f90   \
+             tminit.f90 tnelgo.f90 tsubo.f90 vxrigid.f90 vyfree.f90 xconduc.f90 \
+             yadiab.f90 lapak.f90
+ 
+ FP_ABSTOLERANCE=2.0e-8
+ FP_TOLERANCE=0.01
+ 
+ STDIN_FILENAME  = galgel.in
+ STDOUT_FILENAME = galgel.out
+ NAGFORTRAN_FLAGS = -fixed -kind=byte -dcfuns -dusty
+ # -I $(SPEC_BENCH_DIR)/src
+ 
+ 
+ include $(LEVEL)/Makefile.FORTRAN
+ include ../../Makefile.spec2000
+ CPPFLAGS += -DINT64='long long'
+ 
+ ab.c arhbt.c arhim.c bifg21.c bifgel.c          \
+             bifoag.c cyklap.c eigQR.c farhim.c funht.c funns.c     \
+             galgel.c grsyst.c htxyl.c htxynl.c newtap.c newtlap.c  \
+             nsxyar.c nsxyl.c nsxynl.c pollin.c polnel.c pro.c      \
+             syshtL.c syshtN.c sysnsL.c sysnsN.c tempbt.c tempo.c   \
+             tminit.c tnelgo.c tsubo.c vxrigid.c vyfree.c xconduc.c \
+             yadiab.c lapak.c: modules.c





From lattner at cs.uiuc.edu  Wed Jul 20 12:07:38 2005
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Wed, 20 Jul 2005 12:07:38 -0500
Subject: [llvm-commits] CVS: llvm-test/External/SPEC/CFP2000/Makefile 
Message-ID: <200507201707.MAA19586@zion.cs.uiuc.edu>



Changes in directory llvm-test/External/SPEC/CFP2000:

Makefile updated: 1.11 -> 1.12
---
Log message:

If we have NAG Fortran, run ALL of the CFP2000 tests


---
Diffs of the changes:  (+18 -2)

 Makefile |   20 ++++++++++++++++++--
 1 files changed, 18 insertions(+), 2 deletions(-)


Index: llvm-test/External/SPEC/CFP2000/Makefile
diff -u llvm-test/External/SPEC/CFP2000/Makefile:1.11 llvm-test/External/SPEC/CFP2000/Makefile:1.12
--- llvm-test/External/SPEC/CFP2000/Makefile:1.11	Tue Mar 15 14:31:02 2005
+++ llvm-test/External/SPEC/CFP2000/Makefile	Wed Jul 20 12:07:27 2005
@@ -1,24 +1,40 @@
 LEVEL = ../../..
+
 include $(LEVEL)/Makefile.config
 
+## C Programs
 PARALLEL_DIRS :=   \
 	177.mesa   \
 	179.art    \
 	183.equake \
 	188.ammp
 
+ifdef USE_F95
+PARALLEL_DIRS += \
+        168.wupwise \
+        171.swim    \
+        172.mgrid   \
+        173.applu   \
+        178.galgel  \
+	187.facerec \
+	189.lucas   \
+	191.fma3d   \
+        200.sixtrack \
+        301.apsi
+else
+ifdef USE_F2C
+
 # These are f90 and hence cannot be converted with f2c:
 # 178.galgel, 187.facerec, 189.lucas, 191.fma3d
 #
 # These are broken with f2c: output does not compile natively
 # 200.sixtrack, 301.apsi
-
-ifdef USE_F2C
 PARALLEL_DIRS += \
 	168.wupwise \
 	171.swim    \
 	172.mgrid   \
 	173.applu
 endif
+endif   # End USE_F95
 
 include $(LEVEL)/Makefile.programs





From lattner at cs.uiuc.edu  Wed Jul 20 13:49:39 2005
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Wed, 20 Jul 2005 13:49:39 -0500
Subject: [llvm-commits] 
	CVS: llvm/lib/Transforms/Scalar/InstructionCombining.cpp
Message-ID: <200507201849.NAA20038@zion.cs.uiuc.edu>



Changes in directory llvm/lib/Transforms/Scalar:

InstructionCombining.cpp updated: 1.358 -> 1.359
---
Log message:

Do not let MaskedValueIsZero consider undef to be zero, for reasons
explained in the comment.

This fixes UnitTests/2003-09-18-BitFieldTest on darwin


---
Diffs of the changes:  (+8 -2)

 InstructionCombining.cpp |   10 ++++++++--
 1 files changed, 8 insertions(+), 2 deletions(-)


Index: llvm/lib/Transforms/Scalar/InstructionCombining.cpp
diff -u llvm/lib/Transforms/Scalar/InstructionCombining.cpp:1.358 llvm/lib/Transforms/Scalar/InstructionCombining.cpp:1.359
--- llvm/lib/Transforms/Scalar/InstructionCombining.cpp:1.358	Mon Jul 18 18:07:33 2005
+++ llvm/lib/Transforms/Scalar/InstructionCombining.cpp	Wed Jul 20 13:49:28 2005
@@ -1317,7 +1317,13 @@
 /// this predicate to simplify operations downstream.  V and Mask are known to
 /// be the same type.
 static bool MaskedValueIsZero(Value *V, ConstantIntegral *Mask) {
-  if (isa<UndefValue>(V) || Mask->isNullValue())
+  // Note, we cannot consider 'undef' to be "IsZero" here.  The problem is that
+  // we cannot optimize based on the assumption that it is zero without changing
+  // to to an explicit zero.  If we don't change it to zero, other code could 
+  // optimized based on the contradictory assumption that it is non-zero.
+  // Because instcombine aggressively folds operations with undef args anyway,
+  // this won't lose us code quality.
+  if (Mask->isNullValue())
     return true;
   if (ConstantIntegral *CI = dyn_cast<ConstantIntegral>(V))
     return ConstantExpr::getAnd(CI, Mask)->isNullValue();
@@ -3134,7 +3140,7 @@
       return ReplaceInstUsesWith(I, Constant::getNullValue(I.getType()));
   }
   if (isa<UndefValue>(Op1)) {
-    if (isLeftShift || I.getType()->isUnsigned())
+    if (isLeftShift || I.getType()->isUnsigned())// X << undef, X >>u undef -> 0
       return ReplaceInstUsesWith(I, Constant::getNullValue(I.getType()));
     else
       return ReplaceInstUsesWith(I, Op0);          // X >>s undef -> X





From lattner at cs.uiuc.edu  Wed Jul 20 14:06:59 2005
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Wed, 20 Jul 2005 14:06:59 -0500
Subject: [llvm-commits] CVS: llvm-gcc/gcc/llvm-expand.c 
Message-ID: <200507201906.OAA21100@zion.cs.uiuc.edu>



Changes in directory llvm-gcc/gcc:

llvm-expand.c updated: 1.104 -> 1.105
---
Log message:

Fix CONSTRUCTOR lowering on big-endian bitfield systems, like Darwin.  This
fixes SingleSource/UnitTests/2004-06-20-StaticBitfieldInit.c.  This corrects
code like this:

struct T {
  unsigned X : 5;
  unsigned Y : 6;
  unsigned Z : 5;
};

struct T GV = { 1, 5, 1 };

Initializing GV to the correct constant for big-endian order.



---
Diffs of the changes:  (+7 -1)

 llvm-expand.c |    8 +++++++-
 1 files changed, 7 insertions(+), 1 deletion(-)


Index: llvm-gcc/gcc/llvm-expand.c
diff -u llvm-gcc/gcc/llvm-expand.c:1.104 llvm-gcc/gcc/llvm-expand.c:1.105
--- llvm-gcc/gcc/llvm-expand.c:1.104	Fri Jul 15 21:14:08 2005
+++ llvm-gcc/gcc/llvm-expand.c	Wed Jul 20 14:06:48 2005
@@ -3985,13 +3985,19 @@
           assert(llvm_type_is_integral(FieldType) && "Bad bitfield member ty!");
           assert(ElVal->Ty == FieldType && "Types do not agree!");
           
+          /* If this target lays out bitfields in big-endian order, compute the
+           * actual bit number before we insert the value.
+           */
+          if (BITS_BIG_ENDIAN)
+            FieldOffset = llvm_type_get_size(FieldType)*8-FieldOffset-FieldSize;
+          
           /* If there is already a value set for this field, mask out any bits
            * that are part of the current field (in case the current field is
            * multiply initialized to different values).  LLVM will constant fold
            * all of the constant expressions generated.
            */
           if (Result[FieldIndexVal]) {
-            long long MaskVal = ~(((1 << FieldSize)-1) << FieldOffset);
+            long long MaskVal = ~(((1ULL << FieldSize)-1) << FieldOffset);
             llvm_value *Mask;
             assert(sizeof(long long) == 8 && "Must have 64-bit long long!");
 





From lattner at cs.uiuc.edu  Wed Jul 20 14:12:11 2005
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Wed, 20 Jul 2005 14:12:11 -0500
Subject: [llvm-commits] 
	CVS: llvm/test/Regression/CodeGen/X86/fast-cc-merge-stack-adj.ll
Message-ID: <200507201912.OAA21477@zion.cs.uiuc.edu>



Changes in directory llvm/test/Regression/CodeGen/X86:

fast-cc-merge-stack-adj.ll updated: 1.2 -> 1.3
---
Log message:

Allow this to pass on non-linux systems as well, such as darwin


---
Diffs of the changes:  (+2 -0)

 fast-cc-merge-stack-adj.ll |    2 ++
 1 files changed, 2 insertions(+)


Index: llvm/test/Regression/CodeGen/X86/fast-cc-merge-stack-adj.ll
diff -u llvm/test/Regression/CodeGen/X86/fast-cc-merge-stack-adj.ll:1.2 llvm/test/Regression/CodeGen/X86/fast-cc-merge-stack-adj.ll:1.3
--- llvm/test/Regression/CodeGen/X86/fast-cc-merge-stack-adj.ll:1.2	Sat May 14 18:54:55 2005
+++ llvm/test/Regression/CodeGen/X86/fast-cc-merge-stack-adj.ll	Wed Jul 20 14:12:00 2005
@@ -1,5 +1,7 @@
 ; RUN: llvm-as < %s | llc -march=x86 -x86-asm-syntax=intel -enable-x86-fastcc  | grep 'add %ESP, 8'
 
+target triple = "i686-pc-linux-gnu"
+
 declare fastcc void %func(int *%X, long %Y)
 
 fastcc void %caller(int, long) {





From brukman at cs.uiuc.edu  Wed Jul 20 16:07:03 2005
From: brukman at cs.uiuc.edu (Misha Brukman)
Date: Wed, 20 Jul 2005 16:07:03 -0500
Subject: [llvm-commits] CVS: llvm/docs/CommandGuide/llvmc.pod 
Message-ID: <200507202107.QAA23049@zion.cs.uiuc.edu>



Changes in directory llvm/docs/CommandGuide:

llvmc.pod updated: 1.9 -> 1.10
---
Log message:

* "GNU Compiler Collection's gcc tool" is redundant
* Made bullet points start with a verb and lowercase, since they are not
  complete sentences
* Cleaned up grammar, removed extraneous verbosity


---
Diffs of the changes:  (+9 -10)

 llvmc.pod |   19 +++++++++----------
 1 files changed, 9 insertions(+), 10 deletions(-)


Index: llvm/docs/CommandGuide/llvmc.pod
diff -u llvm/docs/CommandGuide/llvmc.pod:1.9 llvm/docs/CommandGuide/llvmc.pod:1.10
--- llvm/docs/CommandGuide/llvmc.pod:1.9	Thu Apr 21 21:16:19 2005
+++ llvm/docs/CommandGuide/llvmc.pod	Wed Jul 20 16:06:37 2005
@@ -10,23 +10,22 @@
 
 =head1 DESCRIPTION
 
-The B<llvmc> command is a configurable driver for invoking other 
-LLVM (and non-LLVM) tools in order to compile, optimize and link software
-for multiple languages. For those familiar with the GNU Compiler 
-Collection's B<gcc> tool, it is very similar. This tool has the
-following main goals or purposes:
+B<llvmc> is a configurable driver for invoking other LLVM (and non-LLVM) tools
+in order to compile, optimize and link software for multiple languages. For
+those familiar with FSF's B<gcc> tool, it is very similar.  B<llvmc> has the
+following goals:
 
 =over
 
-=item * A Single point of access to the LLVM tool set.
+=item * provide a single point of access to the LLVM tool set,
 
-=item * Hide the complexities of the LLVM tools through a single interface.
+=item * hide the complexities of the LLVM tools through a single interface,
 
-=item * Make integration of existing non-LLVM tools simple.
+=item * make integration of existing non-LLVM tools simple,
 
-=item * Extend the capabilities of minimal front ends.
+=item * extend the capabilities of minimal front ends, and
 
-=item * Make the interface for compiling consistent for all languages.
+=item * make the interface for compiling consistent for all languages.
 
 =back
 





From natebegeman at mac.com  Wed Jul 20 17:42:11 2005
From: natebegeman at mac.com (Nate Begeman)
Date: Wed, 20 Jul 2005 17:42:11 -0500
Subject: [llvm-commits] CVS: llvm/lib/Target/PowerPC/PPC32CodeEmitter.cpp
	PPC32ISelPattern.cpp PowerPCAsmPrinter.cpp
	PowerPCInstrInfo.td PowerPCTargetMachine.cpp 
Message-ID: <200507202242.RAA24378@zion.cs.uiuc.edu>



Changes in directory llvm/lib/Target/PowerPC:

PPC32CodeEmitter.cpp updated: 1.30 -> 1.31
PPC32ISelPattern.cpp updated: 1.100 -> 1.101
PowerPCAsmPrinter.cpp updated: 1.79 -> 1.80
PowerPCInstrInfo.td updated: 1.73 -> 1.74
PowerPCTargetMachine.cpp updated: 1.53 -> 1.54
---
Log message:

Generate mfocrf when targeting g5.  Generate fsqrt/fsqrts when targetin g5.
8-byte align doubles.


---
Diffs of the changes:  (+54 -22)

 PPC32CodeEmitter.cpp     |    4 ++--
 PPC32ISelPattern.cpp     |   21 ++++++++++++++++++---
 PowerPCAsmPrinter.cpp    |   37 +++++++++++++++++++++++--------------
 PowerPCInstrInfo.td      |   10 +++++++++-
 PowerPCTargetMachine.cpp |    4 ++--
 5 files changed, 54 insertions(+), 22 deletions(-)


Index: llvm/lib/Target/PowerPC/PPC32CodeEmitter.cpp
diff -u llvm/lib/Target/PowerPC/PPC32CodeEmitter.cpp:1.30 llvm/lib/Target/PowerPC/PPC32CodeEmitter.cpp:1.31
--- llvm/lib/Target/PowerPC/PPC32CodeEmitter.cpp:1.30	Thu Apr 21 18:20:02 2005
+++ llvm/lib/Target/PowerPC/PPC32CodeEmitter.cpp	Wed Jul 20 17:42:00 2005
@@ -187,9 +187,9 @@
   if (MO.isRegister()) {
     rv = enumRegToMachineReg(MO.getReg());
 
-    // Special encoding for MTCRF and MFCRF, which uses a bit mask for the
+    // Special encoding for MTCRF and MFOCRF, which uses a bit mask for the
     // register, not the register number directly.
-    if ((MI.getOpcode() == PPC::MTCRF || MI.getOpcode() == PPC::MFCRF) &&
+    if ((MI.getOpcode() == PPC::MTCRF || MI.getOpcode() == PPC::MFOCRF) &&
         (MO.getReg() >= PPC::CR0 && MO.getReg() <= PPC::CR7)) {
       rv = 0x80 >> rv;
     }


Index: llvm/lib/Target/PowerPC/PPC32ISelPattern.cpp
diff -u llvm/lib/Target/PowerPC/PPC32ISelPattern.cpp:1.100 llvm/lib/Target/PowerPC/PPC32ISelPattern.cpp:1.101
--- llvm/lib/Target/PowerPC/PPC32ISelPattern.cpp:1.100	Tue Jul 19 11:51:05 2005
+++ llvm/lib/Target/PowerPC/PPC32ISelPattern.cpp	Wed Jul 20 17:42:00 2005
@@ -35,6 +35,11 @@
 #include <algorithm>
 using namespace llvm;
 
+// FIXME: temporary.
+#include "llvm/Support/CommandLine.h"
+static cl::opt<bool> EnableGPOPT("enable-gpopt", cl::Hidden,
+                                 cl::desc("Enable optimizations for GP cpus"));
+
 //===----------------------------------------------------------------------===//
 //  PPC32TargetLowering - PPC32 Implementation of the TargetLowering interface
 namespace {
@@ -67,13 +72,17 @@
       // We don't support sin/cos/sqrt/fmod
       setOperationAction(ISD::FSIN , MVT::f64, Expand);
       setOperationAction(ISD::FCOS , MVT::f64, Expand);
-      setOperationAction(ISD::FSQRT, MVT::f64, Expand);
       setOperationAction(ISD::SREM , MVT::f64, Expand);
       setOperationAction(ISD::FSIN , MVT::f32, Expand);
       setOperationAction(ISD::FCOS , MVT::f32, Expand);
-      setOperationAction(ISD::FSQRT, MVT::f32, Expand);
       setOperationAction(ISD::SREM , MVT::f32, Expand);
 
+      // If we're enabling GP optimizations, use hardware square root
+      if (!EnableGPOPT) {
+        setOperationAction(ISD::FSQRT, MVT::f64, Expand);
+        setOperationAction(ISD::FSQRT, MVT::f32, Expand);
+      }
+            
       //PowerPC does not have CTPOP or CTTZ
       setOperationAction(ISD::CTPOP, MVT::i32  , Expand);
       setOperationAction(ISD::CTTZ , MVT::i32  , Expand);
@@ -961,7 +970,7 @@
 void ISel::MoveCRtoGPR(unsigned CCReg, bool Inv, unsigned Idx, unsigned Result){
   unsigned IntCR = MakeReg(MVT::i32);
   BuildMI(BB, PPC::MCRF, 1, PPC::CR7).addReg(CCReg);
-  BuildMI(BB, PPC::MFCR, 1, IntCR).addReg(PPC::CR7);
+  BuildMI(BB, EnableGPOPT ? PPC::MFOCRF : PPC::MFCR, 1, IntCR).addReg(PPC::CR7);
   if (Inv) {
     unsigned Tmp1 = MakeReg(MVT::i32);
     BuildMI(BB, PPC::RLWINM, 4, Tmp1).addReg(IntCR).addImm(32-(3-Idx))
@@ -2273,6 +2282,12 @@
     BuildMI(BB, PPC::FABS, 1, Result).addReg(Tmp1);
     return Result;
 
+  case ISD::FSQRT:
+    Tmp1 = SelectExpr(N.getOperand(0));
+    Opc = DestType == MVT::f64 ? PPC::FSQRT : PPC::FSQRTS;
+    BuildMI(BB, Opc, 1, Result).addReg(Tmp1);
+    return Result;
+
   case ISD::FP_ROUND:
     assert (DestType == MVT::f32 &&
             N.getOperand(0).getValueType() == MVT::f64 &&


Index: llvm/lib/Target/PowerPC/PowerPCAsmPrinter.cpp
diff -u llvm/lib/Target/PowerPC/PowerPCAsmPrinter.cpp:1.79 llvm/lib/Target/PowerPC/PowerPCAsmPrinter.cpp:1.80
--- llvm/lib/Target/PowerPC/PowerPCAsmPrinter.cpp:1.79	Tue Jul 12 13:34:15 2005
+++ llvm/lib/Target/PowerPC/PowerPCAsmPrinter.cpp	Wed Jul 20 17:42:00 2005
@@ -60,6 +60,21 @@
       return static_cast<PowerPCTargetMachine&>(TM);
     }
 
+    unsigned enumRegToMachineReg(unsigned enumReg) {
+      switch (enumReg) {
+      default: assert(0 && "Unhandled register!"); break;
+      case PPC::CR0:  return  0;
+      case PPC::CR1:  return  1;
+      case PPC::CR2:  return  2;
+      case PPC::CR3:  return  3;
+      case PPC::CR4:  return  4;
+      case PPC::CR5:  return  5;
+      case PPC::CR6:  return  6;
+      case PPC::CR7:  return  7;
+      }
+      abort();
+    }
+
     /// printInstruction - This method is automatically generated by tablegen
     /// from the instruction set description.  This method returns true if the
     /// machine instruction was sufficiently described to print it, otherwise it
@@ -141,22 +156,16 @@
                        MVT::ValueType VT) {
       unsigned char value = MI->getOperand(OpNo).getImmedValue();
       assert(value <= 3 && "Invalid crbit argument!");
-      unsigned RegNo, CCReg = MI->getOperand(OpNo-1).getReg();
-      switch (CCReg) {
-      case PPC::CR0:  RegNo = 0; break;
-      case PPC::CR1:  RegNo = 1; break;
-      case PPC::CR2:  RegNo = 2; break;
-      case PPC::CR3:  RegNo = 3; break;
-      case PPC::CR4:  RegNo = 4; break;
-      case PPC::CR5:  RegNo = 5; break;
-      case PPC::CR6:  RegNo = 6; break;
-      case PPC::CR7:  RegNo = 7; break;
-      default:
-        std::cerr << "Unhandled reg in enumRegToRealReg!\n";
-        abort();
-      }
+      unsigned CCReg = MI->getOperand(OpNo-1).getReg();
+      unsigned RegNo = enumRegToMachineReg(CCReg);
       O << 4 * RegNo + value;
     }
+    void printcrbitm(const MachineInstr *MI, unsigned OpNo,
+                       MVT::ValueType VT) {
+      unsigned CCReg = MI->getOperand(OpNo).getReg();
+      unsigned RegNo = enumRegToMachineReg(CCReg);
+      O << (0x80 >> RegNo);
+    }
 
     virtual void printConstantPool(MachineConstantPool *MCP) = 0;
     virtual bool runOnMachineFunction(MachineFunction &F) = 0;


Index: llvm/lib/Target/PowerPC/PowerPCInstrInfo.td
diff -u llvm/lib/Target/PowerPC/PowerPCInstrInfo.td:1.73 llvm/lib/Target/PowerPC/PowerPCInstrInfo.td:1.74
--- llvm/lib/Target/PowerPC/PowerPCInstrInfo.td:1.73	Sun May 15 15:11:44 2005
+++ llvm/lib/Target/PowerPC/PowerPCInstrInfo.td	Wed Jul 20 17:42:00 2005
@@ -55,6 +55,9 @@
 def crbit: Operand<i8> {
   let PrintMethod = "printcrbit";
 }
+def crbitm: Operand<i8> {
+  let PrintMethod = "printcrbitm";
+}
 
 // Pseudo-instructions:
 def PHI : Pseudo<(ops), "; PHI">;
@@ -314,6 +317,11 @@
                       "fneg $frD, $frB">;
 def FRSP   : XForm_26<63, 12, (ops FPRC:$frD, FPRC:$frB),
                       "frsp $frD, $frB">;
+def FSQRT  : XForm_26<63, 22, (ops FPRC:$frD, FPRC:$frB),
+                      "fsqrt $frD, $frB">;
+def FSQRTS : XForm_26<59, 22, (ops FPRC:$frD, FPRC:$frB),
+                      "fsqrts $frD, $frB">;
+                      
 let isStore = 1 in {
 def STFSX : XForm_28<31, 663, (ops FPRC:$frS, GPRC:$rA, GPRC:$rB),
                      "stfsx $frS, $rA, $rB">;
@@ -360,7 +368,7 @@
 def MFCR  : XFXForm_3<31, 19, (ops GPRC:$rT), "mfcr $rT">;
 def MTCRF : XFXForm_5<31, 0, 144, (ops CRRC:$FXM, GPRC:$rS),
                       "mtcrf $FXM, $rS">;
-def MFCRF : XFXForm_5<31, 1, 19, (ops GPRC:$rT, CRRC:$FXM),
+def MFOCRF : XFXForm_5<31, 1, 19, (ops GPRC:$rT, crbitm:$FXM),
                       "mfcr $rT, $FXM">;
 def MTCTR : XFXForm_7_ext<31, 467, 288, (ops GPRC:$rS), "mtctr $rS">;
 def MTLR  : XFXForm_7_ext<31, 467, 256, (ops GPRC:$rS), "mtlr $rS">;


Index: llvm/lib/Target/PowerPC/PowerPCTargetMachine.cpp
diff -u llvm/lib/Target/PowerPC/PowerPCTargetMachine.cpp:1.53 llvm/lib/Target/PowerPC/PowerPCTargetMachine.cpp:1.54
--- llvm/lib/Target/PowerPC/PowerPCTargetMachine.cpp:1.53	Tue Jul 19 11:51:05 2005
+++ llvm/lib/Target/PowerPC/PowerPCTargetMachine.cpp	Wed Jul 20 17:42:00 2005
@@ -170,14 +170,14 @@
 ///
 PPC32TargetMachine::PPC32TargetMachine(const Module &M, IntrinsicLowering *IL)
   : PowerPCTargetMachine(PPC32ID, IL,
-                         TargetData(PPC32ID,false,4,4,4,4,4,4,2,1,1),
+                         TargetData(PPC32ID,false,4,4,8,4,4,4,2,1,1),
                          PowerPCFrameInfo(*this, false)), JITInfo(*this) {}
 
 /// PPC64TargetMachine ctor - Create a LP64 architecture model
 ///
 PPC64TargetMachine::PPC64TargetMachine(const Module &M, IntrinsicLowering *IL)
   : PowerPCTargetMachine(PPC64ID, IL,
-                         TargetData(PPC64ID,false,8,4,4,4,4,4,2,1,1),
+                         TargetData(PPC64ID,false,8,4,8,4,4,4,2,1,1),
                          PowerPCFrameInfo(*this, true)) {}
 
 unsigned PPC32TargetMachine::getModuleMatchQuality(const Module &M) {





From natebegeman at mac.com  Wed Jul 20 17:44:03 2005
From: natebegeman at mac.com (Nate Begeman)
Date: Wed, 20 Jul 2005 17:44:03 -0500
Subject: [llvm-commits] CVS: llvm-test/Makefile.programs 
Message-ID: <200507202244.RAA24393@zion.cs.uiuc.edu>



Changes in directory llvm-test:

Makefile.programs updated: 1.156 -> 1.157
---
Log message:

Enable new flag for llcbeta on powerpc.  This option requires a G5, which
is okay for the nightly tester.


---
Diffs of the changes:  (+1 -1)

 Makefile.programs |    2 +-
 1 files changed, 1 insertion(+), 1 deletion(-)


Index: llvm-test/Makefile.programs
diff -u llvm-test/Makefile.programs:1.156 llvm-test/Makefile.programs:1.157
--- llvm-test/Makefile.programs:1.156	Thu Jun 16 02:27:16 2005
+++ llvm-test/Makefile.programs	Wed Jul 20 17:43:51 2005
@@ -187,7 +187,7 @@
 endif#DISABLE_DIFFS
 
 ifeq ($(ARCH),PowerPC)
-LLCBETAOPTION := -enable-cc-opts
+LLCBETAOPTION := -enable-gpopt
 endif
 ifeq ($(ARCH),Alpha)
 LLCBETAOPTION := -enable-alpha-intfpdiv -enable-alpha-ftoi





From lattner at cs.uiuc.edu  Wed Jul 20 19:57:11 2005
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Wed, 20 Jul 2005 19:57:11 -0500
Subject: [llvm-commits] CVS: llvm-gcc/gcc/llvm-expand.c 
Message-ID: <200507210057.TAA27958@zion.cs.uiuc.edu>



Changes in directory llvm-gcc/gcc:

llvm-expand.c updated: 1.105 -> 1.106
---
Log message:

Expand sqrt* calls to llvm.sqrt if errno doesn't matter


---
Diffs of the changes:  (+11 -3)

 llvm-expand.c |   14 +++++++++++---
 1 files changed, 11 insertions(+), 3 deletions(-)


Index: llvm-gcc/gcc/llvm-expand.c
diff -u llvm-gcc/gcc/llvm-expand.c:1.105 llvm-gcc/gcc/llvm-expand.c:1.106
--- llvm-gcc/gcc/llvm-expand.c:1.105	Wed Jul 20 14:06:48 2005
+++ llvm-gcc/gcc/llvm-expand.c	Wed Jul 20 19:56:59 2005
@@ -4683,9 +4683,6 @@
 
   /* Generate library calls for functions that we can do so for. */
   switch (fcode) {
-  case BUILT_IN_SQRT:
-  case BUILT_IN_SQRTF:
-  case BUILT_IN_SQRTL:
   case BUILT_IN_SIN:
   case BUILT_IN_SINF:
   case BUILT_IN_SINL:
@@ -4751,6 +4748,17 @@
   case BUILT_IN_NEARBYINTL:
     return llvm_expand_call (Fn, exp, DestLoc);
 
+  case BUILT_IN_SQRT:
+  case BUILT_IN_SQRTF:
+  case BUILT_IN_SQRTL:
+    // If errno math has been disabled, expand these to llvm.sqrt calls.
+    if (!flag_errno_math) {
+      return llvm_expand_builtin_unaryop(Fn, DestTy, arglist, "llvm.sqrt");
+    } else {
+      // Otherwise, expand as a call to sqrt*.
+      return llvm_expand_call (Fn, exp, DestLoc);
+    }
+    
   case BUILT_IN_MEMCPY:
     assert(DestLoc == 0 && "memcpy doesn't return aggregate!");
     return llvm_expand_builtin_memcpy(Fn, arglist);





From lattner at cs.uiuc.edu  Wed Jul 20 19:57:55 2005
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Wed, 20 Jul 2005 19:57:55 -0500
Subject: [llvm-commits] CVS: llvm-gcc/gcc/config/rs6000/darwin.h 
Message-ID: <200507210057.TAA28015@zion.cs.uiuc.edu>



Changes in directory llvm-gcc/gcc/config/rs6000:

darwin.h updated: 1.1.1.2 -> 1.2
---
Log message:

Darwin's libm doesn't support errno


---
Diffs of the changes:  (+1 -0)

 darwin.h |    1 +
 1 files changed, 1 insertion(+)


Index: llvm-gcc/gcc/config/rs6000/darwin.h
diff -u llvm-gcc/gcc/config/rs6000/darwin.h:1.1.1.2 llvm-gcc/gcc/config/rs6000/darwin.h:1.2
--- llvm-gcc/gcc/config/rs6000/darwin.h:1.1.1.2	Tue Jan 13 10:49:53 2004
+++ llvm-gcc/gcc/config/rs6000/darwin.h	Wed Jul 20 19:57:44 2005
@@ -71,6 +71,7 @@
 #define SUBTARGET_OVERRIDE_OPTIONS				  	\
 do {									\
   rs6000_altivec_abi = 1;						\
+  flag_errno_math = 0; /* Darwin doesn't support libm errno's */\
   if (DEFAULT_ABI == ABI_DARWIN)					\
   {									\
     if (MACHO_DYNAMIC_NO_PIC_P)						\





From lattner at cs.uiuc.edu  Wed Jul 20 20:00:04 2005
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Wed, 20 Jul 2005 20:00:04 -0500
Subject: [llvm-commits] CVS: llvm-gcc/gcc/config/i386/darwin.h 
Message-ID: <200507210100.UAA28079@zion.cs.uiuc.edu>



Changes in directory llvm-gcc/gcc/config/i386:

darwin.h updated: 1.1.1.1 -> 1.2
---
Log message:

darwin's libm doesn't support errno


---
Diffs of the changes:  (+6 -0)

 darwin.h |    6 ++++++
 1 files changed, 6 insertions(+)


Index: llvm-gcc/gcc/config/i386/darwin.h
diff -u llvm-gcc/gcc/config/i386/darwin.h:1.1.1.1 llvm-gcc/gcc/config/i386/darwin.h:1.2
--- llvm-gcc/gcc/config/i386/darwin.h:1.1.1.1	Thu Jan  8 15:58:50 2004
+++ llvm-gcc/gcc/config/i386/darwin.h	Wed Jul 20 19:59:53 2005
@@ -25,6 +25,12 @@
 
 #define TARGET_VERSION fprintf (stderr, " (i386 Darwin)");
 
+#define SUBTARGET_OVERRIDE_OPTIONS                                      \
+do {                                                                    \
+  flag_errno_math = 0; /* Darwin doesn't support libm errno's */        \
+} while(0)
+
+
 #define TARGET_OS_CPP_BUILTINS()                \
   do                                            \
     {                                           \





From lattner at cs.uiuc.edu  Wed Jul 20 20:09:38 2005
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Wed, 20 Jul 2005 20:09:38 -0500
Subject: [llvm-commits] 
	CVS: llvm/test/Regression/CFrontend/2005-07-20-SqrtNoErrno.c
Message-ID: <200507210109.UAA28180@zion.cs.uiuc.edu>



Changes in directory llvm/test/Regression/CFrontend:

2005-07-20-SqrtNoErrno.c added (r1.1)
---
Log message:

If errno doesn't matter (e.g. in -ffast-math scenarios), sqrt* should be
compiled to llvm.sqrt.


---
Diffs of the changes:  (+7 -0)

 2005-07-20-SqrtNoErrno.c |    7 +++++++
 1 files changed, 7 insertions(+)


Index: llvm/test/Regression/CFrontend/2005-07-20-SqrtNoErrno.c
diff -c /dev/null llvm/test/Regression/CFrontend/2005-07-20-SqrtNoErrno.c:1.1
*** /dev/null	Wed Jul 20 20:09:37 2005
--- llvm/test/Regression/CFrontend/2005-07-20-SqrtNoErrno.c	Wed Jul 20 20:09:27 2005
***************
*** 0 ****
--- 1,7 ----
+ // RUN: %llvmgcc %s -S -o - -fno-math-errno | gccas | llvm-dis | grep llvm.sqrt
+ #include <math.h>
+ 
+ float foo(float X) {
+   // Check that this compiles to llvm.sqrt when errno is ignored.
+   return sqrtf(X);
+ }





From natebegeman at mac.com  Wed Jul 20 20:26:01 2005
From: natebegeman at mac.com (Nate Begeman)
Date: Wed, 20 Jul 2005 20:26:01 -0500
Subject: [llvm-commits] CVS: llvm/lib/Target/PowerPC/PowerPCAsmPrinter.cpp 
Message-ID: <200507210126.UAA28304@zion.cs.uiuc.edu>



Changes in directory llvm/lib/Target/PowerPC:

PowerPCAsmPrinter.cpp updated: 1.80 -> 1.81
---
Log message:

Support assembling fsqrt on darwin.  This will be implemented better when
PowerPC gets subtarget support up.


---
Diffs of the changes:  (+9 -0)

 PowerPCAsmPrinter.cpp |    9 +++++++++
 1 files changed, 9 insertions(+)


Index: llvm/lib/Target/PowerPC/PowerPCAsmPrinter.cpp
diff -u llvm/lib/Target/PowerPC/PowerPCAsmPrinter.cpp:1.80 llvm/lib/Target/PowerPC/PowerPCAsmPrinter.cpp:1.81
--- llvm/lib/Target/PowerPC/PowerPCAsmPrinter.cpp:1.80	Wed Jul 20 17:42:00 2005
+++ llvm/lib/Target/PowerPC/PowerPCAsmPrinter.cpp	Wed Jul 20 20:25:49 2005
@@ -192,6 +192,7 @@
 
     void printConstantPool(MachineConstantPool *MCP);
     bool runOnMachineFunction(MachineFunction &F);
+    bool doInitialization(Module &M);
     bool doFinalization(Module &M);
   };
 
@@ -426,6 +427,14 @@
   }
 }
 
+bool DarwinAsmPrinter::doInitialization(Module &M) {
+  // FIXME: implment subtargets for PowerPC and pick this up from there.
+  O << "\t.machine ppc970\n";
+
+  AsmPrinter::doInitialization(M);
+  return false;
+}
+
 bool DarwinAsmPrinter::doFinalization(Module &M) {
   const TargetData &TD = TM.getTargetData();
   std::string CurSection;





From lattner at cs.uiuc.edu  Wed Jul 20 20:29:27 2005
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Wed, 20 Jul 2005 20:29:27 -0500
Subject: [llvm-commits] CVS: llvm/docs/LangRef.html 
Message-ID: <200507210129.UAA28410@zion.cs.uiuc.edu>



Changes in directory llvm/docs:

LangRef.html updated: 1.111 -> 1.112
---
Log message:

llvm.sqrt somehow escaped documentation.


---
Diffs of the changes:  (+38 -1)

 LangRef.html |   39 ++++++++++++++++++++++++++++++++++++++-
 1 files changed, 38 insertions(+), 1 deletion(-)


Index: llvm/docs/LangRef.html
diff -u llvm/docs/LangRef.html:1.111 llvm/docs/LangRef.html:1.112
--- llvm/docs/LangRef.html:1.111	Fri Jun 24 12:22:57 2005
+++ llvm/docs/LangRef.html	Wed Jul 20 20:29:16 2005
@@ -143,6 +143,8 @@
           <li><a href="#i_memmove">'<tt>llvm.memmove</tt>' Intrinsic</a></li>
           <li><a href="#i_memset">'<tt>llvm.memset</tt>' Intrinsic</a></li>
           <li><a href="#i_isunordered">'<tt>llvm.isunordered</tt>' Intrinsic</a></li>
+          <li><a href="#i_sqrt">'<tt>llvm.sqrt</tt>' Intrinsic</a></li>
+
         </ol>
       </li>
       <li><a href="#int_count">Bit counting Intrinsics</a>
@@ -3133,6 +3135,41 @@
 </div>
 
 
+<!-- _______________________________________________________________________ -->
+<div class="doc_subsubsection">
+  <a name="i_sqrt">'<tt>llvm.sqrt</tt>' Intrinsic</a>
+</div>
+
+<div class="doc_text">
+
+<h5>Syntax:</h5>
+<pre>
+  declare &lt;float or double&gt; %llvm.sqrt(&lt;float or double&gt; Val)
+</pre>
+
+<h5>Overview:</h5>
+
+<p>
+The '<tt>llvm.sqrt</tt>' intrinsic returns the sqrt of the specified operand,
+returning the same value as the libm '<tt>sqrt</tt>' function would.  Unlike
+<tt>sqrt</tt> in libm, however, <tt>llvm.sqrt</tt> has undefined behavior for
+negative numbers (which allows for better optimization).
+</p>
+
+<h5>Arguments:</h5>
+
+<p>
+The argument and return value are floating point numbers of the same type.
+</p>
+
+<h5>Semantics:</h5>
+
+<p>
+This function returns the sqrt of the specified operand if it is a positive
+floating point number.
+</p>
+</div>
+
 <!-- ======================================================================= -->
 <div class="doc_subsection">
   <a name="int_count">Bit Counting Intrinsics</a>
@@ -3277,7 +3314,7 @@
 
   <a href="mailto:sabre at nondot.org">Chris Lattner</a><br>
   <a href="http://llvm.cs.uiuc.edu">The LLVM Compiler Infrastructure</a><br>
-  Last modified: $Date: 2005/06/24 17:22:57 $
+  Last modified: $Date: 2005/07/21 01:29:16 $
 </address>
 </body>
 </html>





From lattner at cs.uiuc.edu  Wed Jul 20 20:37:56 2005
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Wed, 20 Jul 2005 20:37:56 -0500
Subject: [llvm-commits] CVS: llvm-test/External/SPEC/CFP2000/301.apsi/
Message-ID: <200507210137.UAA28517@zion.cs.uiuc.edu>



Changes in directory llvm-test/External/SPEC/CFP2000/301.apsi:

---
Log message:

Directory /var/cvs/llvm/llvm-test/External/SPEC/CFP2000/301.apsi added to the repository


---
Diffs of the changes:  (+0 -0)

 0 files changed





From lattner at cs.uiuc.edu  Wed Jul 20 20:38:38 2005
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Wed, 20 Jul 2005 20:38:38 -0500
Subject: [llvm-commits] 
	CVS: llvm-test/External/SPEC/CFP2000/301.apsi/Makefile
Message-ID: <200507210138.UAA28575@zion.cs.uiuc.edu>



Changes in directory llvm-test/External/SPEC/CFP2000/301.apsi:

Makefile added (r1.1)
---
Log message:

Add 301.apsi, which I forgot to check in earlier


---
Diffs of the changes:  (+13 -0)

 Makefile |   13 +++++++++++++
 1 files changed, 13 insertions(+)


Index: llvm-test/External/SPEC/CFP2000/301.apsi/Makefile
diff -c /dev/null llvm-test/External/SPEC/CFP2000/301.apsi/Makefile:1.1
*** /dev/null	Wed Jul 20 20:38:37 2005
--- llvm-test/External/SPEC/CFP2000/301.apsi/Makefile	Wed Jul 20 20:38:27 2005
***************
*** 0 ****
--- 1,13 ----
+ LEVEL = ../../../..
+ 
+ Source = apsi.f
+ 
+ FP_ABSTOLERANCE=0.0000001
+ FP_TOLERANCE=0.01
+ 
+ #STDIN_FILENAME  = apsi.in
+ STDOUT_FILENAME = apsi.out
+ NAGFORTRAN_FLAGS = -dusty
+ 
+ include $(LEVEL)/Makefile.FORTRAN
+ include ../../Makefile.spec2000





From brukman at cs.uiuc.edu  Thu Jul 21 12:31:03 2005
From: brukman at cs.uiuc.edu (Misha Brukman)
Date: Thu, 21 Jul 2005 12:31:03 -0500
Subject: [llvm-commits] CVS: llvm-tv/lib/Snapshot/WriteSnapshot.cpp 
Message-ID: <200507211731.MAA31013@zion.cs.uiuc.edu>



Changes in directory llvm-tv/lib/Snapshot:

WriteSnapshot.cpp updated: 1.11 -> 1.12
---
Log message:

Adjust to changes in Pass/ModulePass and System::Path APIs


---
Diffs of the changes:  (+9 -9)

 WriteSnapshot.cpp |   18 +++++++++---------
 1 files changed, 9 insertions(+), 9 deletions(-)


Index: llvm-tv/lib/Snapshot/WriteSnapshot.cpp
diff -u llvm-tv/lib/Snapshot/WriteSnapshot.cpp:1.11 llvm-tv/lib/Snapshot/WriteSnapshot.cpp:1.12
--- llvm-tv/lib/Snapshot/WriteSnapshot.cpp:1.11	Mon Apr 18 13:40:17 2005
+++ llvm-tv/lib/Snapshot/WriteSnapshot.cpp	Thu Jul 21 12:30:52 2005
@@ -39,16 +39,16 @@
 extern char **environ;
 
 namespace {
-  struct Snapshot : public Pass {
+  struct Snapshot : public ModulePass {
     /// getAnalysisUsage - this pass does not require or invalidate any analysis
     ///
     virtual void getAnalysisUsage(AnalysisUsage &AU) {
       AU.setPreservesAll();
     }
     
-    /// runPass - save the Module in a pre-defined location with our naming
+    /// runOnModule - save the Module in a pre-defined location with our naming
     /// strategy
-    bool runPass(Module &M);
+    bool runOnModule(Module &M);
 
   private:
     bool sendSignalToLLVMTV();
@@ -64,11 +64,11 @@
 }
 
 
-/// runPass - save snapshot to a pre-defined directory with a consecutive number
-/// in the name (for alphabetization) and the name of the pass that ran just
-/// before this one. Signal llvm-tv that fresh bytecode file has arrived for
-/// consumption.
-bool Snapshot::runPass(Module &M) {
+/// runOnModule - save snapshot to a pre-defined directory with a consecutive
+/// number in the name (for alphabetization) and the name of the pass that ran
+/// just before this one. Signal llvm-tv that fresh bytecode file has arrived
+/// for consumption.
+bool Snapshot::runOnModule(Module &M) {
   // Make sure the snapshots dir exists, which it will unless this
   // is the first time we've ever run the -snapshot pass.
   EnsureDirectoryExists (llvmtvPath);
@@ -93,7 +93,7 @@
   // instance of llvm-tv, start a new instance and send a signal to it.
   sys::Path llvmtvExe = FindExecutable("llvm-tv", ""); 
   if (llvmtvExe.isValid() && !llvmtvExe.isEmpty() && llvmtvExe.isFile() &&
-      llvmtvExe.executable()) {
+      llvmtvExe.canExecute()) {
     int pid = fork();
     // Child process morphs into llvm-tv
     if (!pid) {





From lattner at cs.uiuc.edu  Thu Jul 21 14:17:29 2005
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Thu, 21 Jul 2005 14:17:29 -0500
Subject: [llvm-commits] 
	CVS: llvm/lib/Target/PowerPC/PowerPCTargetMachine.cpp
Message-ID: <200507211917.OAA02875@zion.cs.uiuc.edu>



Changes in directory llvm/lib/Target/PowerPC:

PowerPCTargetMachine.cpp updated: 1.54 -> 1.55
---
Log message:

revert to using 4-byte alignment for doubles, as specified by the ABI


---
Diffs of the changes:  (+1 -1)

 PowerPCTargetMachine.cpp |    2 +-
 1 files changed, 1 insertion(+), 1 deletion(-)


Index: llvm/lib/Target/PowerPC/PowerPCTargetMachine.cpp
diff -u llvm/lib/Target/PowerPC/PowerPCTargetMachine.cpp:1.54 llvm/lib/Target/PowerPC/PowerPCTargetMachine.cpp:1.55
--- llvm/lib/Target/PowerPC/PowerPCTargetMachine.cpp:1.54	Wed Jul 20 17:42:00 2005
+++ llvm/lib/Target/PowerPC/PowerPCTargetMachine.cpp	Thu Jul 21 14:17:18 2005
@@ -177,7 +177,7 @@
 ///
 PPC64TargetMachine::PPC64TargetMachine(const Module &M, IntrinsicLowering *IL)
   : PowerPCTargetMachine(PPC64ID, IL,
-                         TargetData(PPC64ID,false,8,4,8,4,4,4,2,1,1),
+                         TargetData(PPC64ID,false,8,4,4,4,4,4,2,1,1),
                          PowerPCFrameInfo(*this, true)) {}
 
 unsigned PPC32TargetMachine::getModuleMatchQuality(const Module &M) {





From natebegeman at mac.com  Thu Jul 21 15:44:54 2005
From: natebegeman at mac.com (Nate Begeman)
Date: Thu, 21 Jul 2005 15:44:54 -0500
Subject: [llvm-commits] CVS: llvm/lib/Target/PowerPC/PPC32CodeEmitter.cpp
	PPC32ISelPattern.cpp PPC32ISelSimple.cpp PPC64ISelPattern.cpp
	PowerPC.h PowerPCAsmPrinter.cpp PowerPCInstrInfo.td
	PowerPCTargetMachine.cpp 
Message-ID: <200507212044.PAA10009@zion.cs.uiuc.edu>



Changes in directory llvm/lib/Target/PowerPC:

PPC32CodeEmitter.cpp updated: 1.31 -> 1.32
PPC32ISelPattern.cpp updated: 1.101 -> 1.102
PPC32ISelSimple.cpp updated: 1.142 -> 1.143
PPC64ISelPattern.cpp updated: 1.25 -> 1.26
PowerPC.h updated: 1.16 -> 1.17
PowerPCAsmPrinter.cpp updated: 1.81 -> 1.82
PowerPCInstrInfo.td updated: 1.74 -> 1.75
PowerPCTargetMachine.cpp updated: 1.55 -> 1.56
---
Log message:

Support building non-PIC
Remove the LoadHiAddr pseudo-instruction.
Optimization of stores to and loads from statics.  
Force JIT to use new non-PIC codepaths.


---
Diffs of the changes:  (+179 -123)

 PPC32CodeEmitter.cpp     |   65 ++++++++++-----------
 PPC32ISelPattern.cpp     |  142 ++++++++++++++++++++++++++++-------------------
 PPC32ISelSimple.cpp      |    4 -
 PPC64ISelPattern.cpp     |   10 +--
 PowerPC.h                |    3 
 PowerPCAsmPrinter.cpp    |   42 ++++++++++---
 PowerPCInstrInfo.td      |   24 +++----
 PowerPCTargetMachine.cpp |   12 +++
 8 files changed, 179 insertions(+), 123 deletions(-)


Index: llvm/lib/Target/PowerPC/PPC32CodeEmitter.cpp
diff -u llvm/lib/Target/PowerPC/PPC32CodeEmitter.cpp:1.31 llvm/lib/Target/PowerPC/PPC32CodeEmitter.cpp:1.32
--- llvm/lib/Target/PowerPC/PPC32CodeEmitter.cpp:1.31	Wed Jul 20 17:42:00 2005
+++ llvm/lib/Target/PowerPC/PPC32CodeEmitter.cpp	Thu Jul 21 15:44:42 2005
@@ -28,10 +28,6 @@
     TargetMachine &TM;
     MachineCodeEmitter &MCE;
 
-    /// MovePCtoLROffset - When/if we see a MovePCtoLR instruction, we record
-    /// its address in the function into this pointer.
-    void *MovePCtoLROffset;
-
     // Tracks which instruction references which BasicBlock
     std::vector<std::pair<MachineBasicBlock*, unsigned*> > BBRefs;
     // Tracks where each BasicBlock starts
@@ -87,7 +83,6 @@
 }
 
 bool PPC32CodeEmitter::runOnMachineFunction(MachineFunction &MF) {
-  MovePCtoLROffset = 0;
   MCE.startFunction(MF);
   MCE.emitConstantPool(MF.getConstantPool());
   for (MachineFunction::iterator BB = MF.begin(), E = MF.end(); BB != E; ++BB)
@@ -120,6 +115,7 @@
 }
 
 void PPC32CodeEmitter::emitBasicBlock(MachineBasicBlock &MBB) {
+  assert(!PICEnabled && "CodeEmitter does not support PIC!");
   BBLocations[&MBB] = MCE.getCurrentPCValue();
   for (MachineBasicBlock::iterator I = MBB.begin(), E = MBB.end(); I != E; ++I){
     MachineInstr &MI = *I;
@@ -131,10 +127,7 @@
     case PPC::IMPLICIT_DEF:
       break; // pseudo opcode, no side effects
     case PPC::MovePCtoLR:
-      assert(MovePCtoLROffset == 0 &&
-             "Multiple MovePCtoLR instructions in the function?");
-      MovePCtoLROffset = (void*)(intptr_t)MCE.getCurrentPCValue();
-      emitWord(0x48000005);    // bl 1
+      assert(0 && "CodeEmitter does not support MovePCtoLR instruction");
       break;
     }
   }
@@ -200,55 +193,59 @@
                       MO.getGlobal()->hasWeakLinkage() ||
                       MO.getGlobal()->isExternal();
     unsigned Reloc = 0;
-    int Offset = 0;
     if (MI.getOpcode() == PPC::CALLpcrel)
       Reloc = PPC::reloc_pcrel_bx;
     else {
-      assert(MovePCtoLROffset && "MovePCtoLR not seen yet?");
-      Offset = -((intptr_t)MovePCtoLROffset+4);
-
-      if (MI.getOpcode() == PPC::LOADHiAddr) {
+      switch (MI.getOpcode()) {
+      default: MI.dump(); assert(0 && "Unknown instruction for relocation!");
+      case PPC::LIS:
         if (isExternal)
           Reloc = PPC::reloc_absolute_ptr_high;   // Pointer to stub
-        else
+        else 
           Reloc = PPC::reloc_absolute_high;       // Pointer to symbol
-
-      } else if (MI.getOpcode() == PPC::LA) {
+        break;
+      case PPC::LA:
         assert(!isExternal && "Something in the ISEL changed\n");
-
         Reloc = PPC::reloc_absolute_low;
-      } else if (MI.getOpcode() == PPC::LWZ) {
-        Reloc = PPC::reloc_absolute_ptr_low;
-
-        assert(isExternal && "Something in the ISEL changed\n");
-      } else {
-        // These don't show up for global value references AFAIK, only for
-        // constant pool refs: PPC::LFS, PPC::LFD
-        assert(0 && "Unknown instruction for relocation!");
+        break;
+      case PPC::LBZ:
+      case PPC::LHA:
+      case PPC::LHZ:
+      case PPC::LWZ:
+      case PPC::LFS:
+      case PPC::LFD:
+      case PPC::STB:
+      case PPC::STH:
+      case PPC::STW:
+      case PPC::STFS:
+      case PPC::STFD:
+        if (isExternal)
+          Reloc = PPC::reloc_absolute_ptr_low;
+        else 
+          Reloc = PPC::reloc_absolute_low;
+        break;
       }
     }
     if (MO.isGlobalAddress())
       MCE.addRelocation(MachineRelocation(MCE.getCurrentPCOffset(),
-                                          Reloc, MO.getGlobal(), Offset));
+                                          Reloc, MO.getGlobal(), 0));
     else
       MCE.addRelocation(MachineRelocation(MCE.getCurrentPCOffset(),
-                                          Reloc, MO.getSymbolName(), Offset));
+                                          Reloc, MO.getSymbolName(), 0));
   } else if (MO.isMachineBasicBlock()) {
     unsigned* CurrPC = (unsigned*)(intptr_t)MCE.getCurrentPCValue();
     BBRefs.push_back(std::make_pair(MO.getMachineBasicBlock(), CurrPC));
   } else if (MO.isConstantPoolIndex()) {
     unsigned index = MO.getConstantPoolIndex();
-    assert(MovePCtoLROffset && "MovePCtoLR not seen yet?");
-    rv = MCE.getConstantPoolEntryAddress(index) - (intptr_t)MovePCtoLROffset-4;
-
     unsigned Opcode = MI.getOpcode();
-    if (Opcode == PPC::LOADHiAddr) {
-      // LoadHiAddr wants hi16(addr - &MovePCtoLR)
+    rv = MCE.getConstantPoolEntryAddress(index);
+    if (Opcode == PPC::LIS) {
+      // lis wants hi16(addr)
       if ((short)rv < 0) rv += 1 << 16;
       rv >>= 16;
     } else if (Opcode == PPC::LWZ || Opcode == PPC::LA ||
                Opcode == PPC::LFS || Opcode == PPC::LFD) {
-      // These load opcodes want lo16(addr - &MovePCtoLR)
+      // These load opcodes want lo16(addr)
       rv &= 0xffff;
     } else {
       assert(0 && "Unknown constant pool using instruction!");


Index: llvm/lib/Target/PowerPC/PPC32ISelPattern.cpp
diff -u llvm/lib/Target/PowerPC/PPC32ISelPattern.cpp:1.101 llvm/lib/Target/PowerPC/PPC32ISelPattern.cpp:1.102
--- llvm/lib/Target/PowerPC/PPC32ISelPattern.cpp:1.101	Wed Jul 20 17:42:00 2005
+++ llvm/lib/Target/PowerPC/PPC32ISelPattern.cpp	Thu Jul 21 15:44:42 2005
@@ -35,11 +35,6 @@
 #include <algorithm>
 using namespace llvm;
 
-// FIXME: temporary.
-#include "llvm/Support/CommandLine.h"
-static cl::opt<bool> EnableGPOPT("enable-gpopt", cl::Hidden,
-                                 cl::desc("Enable optimizations for GP cpus"));
-
 //===----------------------------------------------------------------------===//
 //  PPC32TargetLowering - PPC32 Implementation of the TargetLowering interface
 namespace {
@@ -78,7 +73,7 @@
       setOperationAction(ISD::SREM , MVT::f32, Expand);
 
       // If we're enabling GP optimizations, use hardware square root
-      if (!EnableGPOPT) {
+      if (!GPOPT) {
         setOperationAction(ISD::FSQRT, MVT::f64, Expand);
         setOperationAction(ISD::FSQRT, MVT::f32, Expand);
       }
@@ -959,8 +954,11 @@
   MachineConstantPool *CP = BB->getParent()->getConstantPool();
   ConstantFP *CFP = ConstantFP::get(Type::DoubleTy, doubleVal);
   unsigned CPI = CP->getConstantPoolIndex(CFP);
-  BuildMI(BB, PPC::LOADHiAddr, 2, Tmp1).addReg(getGlobalBaseReg())
-    .addConstantPoolIndex(CPI);
+  if (PICEnabled)
+    BuildMI(BB, PPC::ADDIS, 2, Tmp1).addReg(getGlobalBaseReg())
+      .addConstantPoolIndex(CPI);
+  else
+    BuildMI(BB, PPC::LIS, 1, Tmp1).addConstantPoolIndex(CPI);
   BuildMI(BB, PPC::LFD, 2, Result).addConstantPoolIndex(CPI).addReg(Tmp1);
   return Result;
 }
@@ -970,7 +968,7 @@
 void ISel::MoveCRtoGPR(unsigned CCReg, bool Inv, unsigned Idx, unsigned Result){
   unsigned IntCR = MakeReg(MVT::i32);
   BuildMI(BB, PPC::MCRF, 1, PPC::CR7).addReg(CCReg);
-  BuildMI(BB, EnableGPOPT ? PPC::MFOCRF : PPC::MFCR, 1, IntCR).addReg(PPC::CR7);
+  BuildMI(BB, GPOPT ? PPC::MFOCRF : PPC::MFCR, 1, IntCR).addReg(PPC::CR7);
   if (Inv) {
     unsigned Tmp1 = MakeReg(MVT::i32);
     BuildMI(BB, PPC::RLWINM, 4, Tmp1).addReg(IntCR).addImm(32-(3-Idx))
@@ -1359,8 +1357,11 @@
   case ISD::ConstantPool:
     Tmp1 = cast<ConstantPoolSDNode>(N)->getIndex();
     Tmp2 = MakeReg(MVT::i32);
-    BuildMI(BB, PPC::LOADHiAddr, 2, Tmp2).addReg(getGlobalBaseReg())
-      .addConstantPoolIndex(Tmp1);
+    if (PICEnabled)
+      BuildMI(BB, PPC::ADDIS, 2, Tmp2).addReg(getGlobalBaseReg())
+        .addConstantPoolIndex(Tmp1);
+    else
+      BuildMI(BB, PPC::LIS, 1, Tmp2).addConstantPoolIndex(Tmp1);
     BuildMI(BB, PPC::LA, 2, Result).addReg(Tmp2).addConstantPoolIndex(Tmp1);
     return Result;
 
@@ -1372,8 +1373,11 @@
   case ISD::GlobalAddress: {
     GlobalValue *GV = cast<GlobalAddressSDNode>(N)->getGlobal();
     Tmp1 = MakeReg(MVT::i32);
-    BuildMI(BB, PPC::LOADHiAddr, 2, Tmp1).addReg(getGlobalBaseReg())
-      .addGlobalAddress(GV);
+    if (PICEnabled)
+      BuildMI(BB, PPC::ADDIS, 2, Tmp1).addReg(getGlobalBaseReg())
+        .addGlobalAddress(GV);
+    else
+      BuildMI(BB, PPC::LIS, 2, Tmp1).addGlobalAddress(GV);
     if (GV->hasWeakLinkage() || GV->isExternal()) {
       BuildMI(BB, PPC::LWZ, 2, Result).addGlobalAddress(GV).addReg(Tmp1);
     } else {
@@ -1413,13 +1417,29 @@
     if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(Address)) {
       Tmp1 = MakeReg(MVT::i32);
       int CPI = CP->getIndex();
-      BuildMI(BB, PPC::LOADHiAddr, 2, Tmp1).addReg(getGlobalBaseReg())
-        .addConstantPoolIndex(CPI);
+      if (PICEnabled)
+        BuildMI(BB, PPC::ADDIS, 2, Tmp1).addReg(getGlobalBaseReg())
+          .addConstantPoolIndex(CPI);
+      else
+        BuildMI(BB, PPC::LIS, 1, Tmp1).addConstantPoolIndex(CPI);
       BuildMI(BB, Opc, 2, Result).addConstantPoolIndex(CPI).addReg(Tmp1);
-    }
-    else if(Address.getOpcode() == ISD::FrameIndex) {
+    } else if (Address.getOpcode() == ISD::FrameIndex) {
       Tmp1 = cast<FrameIndexSDNode>(Address)->getIndex();
       addFrameReference(BuildMI(BB, Opc, 2, Result), (int)Tmp1);
+    } else if(GlobalAddressSDNode *GN = dyn_cast<GlobalAddressSDNode>(Address)){
+      GlobalValue *GV = GN->getGlobal();
+      Tmp1 = MakeReg(MVT::i32);
+      if (PICEnabled)
+        BuildMI(BB, PPC::ADDIS, 2, Tmp1).addReg(getGlobalBaseReg())
+          .addGlobalAddress(GV);
+      else
+        BuildMI(BB, PPC::LIS, 2, Tmp1).addGlobalAddress(GV);
+      if (GV->hasWeakLinkage() || GV->isExternal()) {
+        Tmp2 = MakeReg(MVT::i32);
+        BuildMI(BB, PPC::LWZ, 2, Tmp2).addGlobalAddress(GV).addReg(Tmp1);
+        Tmp1 = Tmp2;
+      }
+      BuildMI(BB, Opc, 2, Result).addGlobalAddress(GV).addReg(Tmp1);
     } else {
       int offset;
       bool idx = SelectAddr(Address, Tmp1, offset);
@@ -2344,7 +2364,7 @@
 }
 
 void ISel::Select(SDOperand N) {
-  unsigned Tmp1, Tmp2, Opc;
+  unsigned Tmp1, Tmp2, Tmp3, Opc;
   unsigned opcode = N.getOpcode();
 
   if (!ExprMap.insert(std::make_pair(N, 1)).second)
@@ -2432,49 +2452,59 @@
     BuildMI(BB, PPC::BLR, 0); // Just emit a 'ret' instruction
     return;
   case ISD::TRUNCSTORE:
-  case ISD::STORE:
-    {
-      SDOperand Chain   = N.getOperand(0);
-      SDOperand Value   = N.getOperand(1);
-      SDOperand Address = N.getOperand(2);
-      Select(Chain);
-
-      Tmp1 = SelectExpr(Value); //value
-
-      if (opcode == ISD::STORE) {
-        switch(Value.getValueType()) {
-        default: assert(0 && "unknown Type in store");
-        case MVT::i32: Opc = PPC::STW; break;
-        case MVT::f64: Opc = PPC::STFD; break;
-        case MVT::f32: Opc = PPC::STFS; break;
-        }
-      } else { //ISD::TRUNCSTORE
-        switch(cast<VTSDNode>(Node->getOperand(4))->getVT()) {
-        default: assert(0 && "unknown Type in store");
-        case MVT::i1:
-        case MVT::i8: Opc  = PPC::STB; break;
-        case MVT::i16: Opc = PPC::STH; break;
-        }
-      }
+  case ISD::STORE: {
+    SDOperand Chain   = N.getOperand(0);
+    SDOperand Value   = N.getOperand(1);
+    SDOperand Address = N.getOperand(2);
+    Select(Chain);
 
-      if(Address.getOpcode() == ISD::FrameIndex)
-      {
-        Tmp2 = cast<FrameIndexSDNode>(Address)->getIndex();
-        addFrameReference(BuildMI(BB, Opc, 3).addReg(Tmp1), (int)Tmp2);
+    Tmp1 = SelectExpr(Value); //value
+
+    if (opcode == ISD::STORE) {
+      switch(Value.getValueType()) {
+      default: assert(0 && "unknown Type in store");
+      case MVT::i32: Opc = PPC::STW; break;
+      case MVT::f64: Opc = PPC::STFD; break;
+      case MVT::f32: Opc = PPC::STFS; break;
+      }
+    } else { //ISD::TRUNCSTORE
+      switch(cast<VTSDNode>(Node->getOperand(4))->getVT()) {
+      default: assert(0 && "unknown Type in store");
+      case MVT::i1:
+      case MVT::i8: Opc  = PPC::STB; break;
+      case MVT::i16: Opc = PPC::STH; break;
       }
+    }
+
+    if(Address.getOpcode() == ISD::FrameIndex) {
+      Tmp2 = cast<FrameIndexSDNode>(Address)->getIndex();
+      addFrameReference(BuildMI(BB, Opc, 3).addReg(Tmp1), (int)Tmp2);
+    } else if(GlobalAddressSDNode *GN = dyn_cast<GlobalAddressSDNode>(Address)){
+      GlobalValue *GV = GN->getGlobal();
+      Tmp2 = MakeReg(MVT::i32);
+      if (PICEnabled)
+        BuildMI(BB, PPC::ADDIS, 2, Tmp2).addReg(getGlobalBaseReg())
+          .addGlobalAddress(GV);
       else
-      {
-        int offset;
-        bool idx = SelectAddr(Address, Tmp2, offset);
-        if (idx) {
-          Opc = IndexedOpForOp(Opc);
-          BuildMI(BB, Opc, 3).addReg(Tmp1).addReg(Tmp2).addReg(offset);
-        } else {
-          BuildMI(BB, Opc, 3).addReg(Tmp1).addImm(offset).addReg(Tmp2);
-        }
+        BuildMI(BB, PPC::LIS, 2, Tmp2).addGlobalAddress(GV);
+      if (GV->hasWeakLinkage() || GV->isExternal()) {
+        Tmp3 = MakeReg(MVT::i32);
+        BuildMI(BB, PPC::LWZ, 2, Tmp3).addGlobalAddress(GV).addReg(Tmp2);
+        Tmp2 = Tmp3;
+      }
+      BuildMI(BB, Opc, 3).addReg(Tmp1).addGlobalAddress(GV).addReg(Tmp2);
+    } else {
+      int offset;
+      bool idx = SelectAddr(Address, Tmp2, offset);
+      if (idx) {
+        Opc = IndexedOpForOp(Opc);
+        BuildMI(BB, Opc, 3).addReg(Tmp1).addReg(Tmp2).addReg(offset);
+      } else {
+        BuildMI(BB, Opc, 3).addReg(Tmp1).addImm(offset).addReg(Tmp2);
       }
-      return;
     }
+    return;
+  }
   case ISD::EXTLOAD:
   case ISD::SEXTLOAD:
   case ISD::ZEXTLOAD:


Index: llvm/lib/Target/PowerPC/PPC32ISelSimple.cpp
diff -u llvm/lib/Target/PowerPC/PPC32ISelSimple.cpp:1.142 llvm/lib/Target/PowerPC/PPC32ISelSimple.cpp:1.143
--- llvm/lib/Target/PowerPC/PPC32ISelSimple.cpp:1.142	Sat Jun 18 13:34:52 2005
+++ llvm/lib/Target/PowerPC/PPC32ISelSimple.cpp	Thu Jul 21 15:44:42 2005
@@ -685,7 +685,7 @@
     unsigned Reg1 = makeAnotherReg(Type::IntTy);
     unsigned Opcode = (Ty == Type::FloatTy) ? PPC::LFS : PPC::LFD;
     // Move value at base + distance into return reg
-    BuildMI(*MBB, IP, PPC::LOADHiAddr, 2, Reg1)
+    BuildMI(*MBB, IP, PPC::ADDIS, 2, Reg1)
       .addReg(getGlobalBaseReg()).addConstantPoolIndex(CPI);
     BuildMI(*MBB, IP, Opcode, 2, R).addConstantPoolIndex(CPI).addReg(Reg1);
   } else if (isa<ConstantPointerNull>(C)) {
@@ -696,7 +696,7 @@
     unsigned TmpReg = makeAnotherReg(GV->getType());
 
     // Move value at base + distance into return reg
-    BuildMI(*MBB, IP, PPC::LOADHiAddr, 2, TmpReg)
+    BuildMI(*MBB, IP, PPC::ADDIS, 2, TmpReg)
       .addReg(getGlobalBaseReg()).addGlobalAddress(GV);
 
     if (GV->hasWeakLinkage() || GV->isExternal()) {


Index: llvm/lib/Target/PowerPC/PPC64ISelPattern.cpp
diff -u llvm/lib/Target/PowerPC/PPC64ISelPattern.cpp:1.25 llvm/lib/Target/PowerPC/PPC64ISelPattern.cpp:1.26
--- llvm/lib/Target/PowerPC/PPC64ISelPattern.cpp:1.25	Sat Jul  9 20:56:13 2005
+++ llvm/lib/Target/PowerPC/PPC64ISelPattern.cpp	Thu Jul 21 15:44:42 2005
@@ -563,7 +563,7 @@
   MachineConstantPool *CP = BB->getParent()->getConstantPool();
   ConstantFP *CFP = ConstantFP::get(Type::DoubleTy, doubleVal);
   unsigned CPI = CP->getConstantPoolIndex(CFP);
-  BuildMI(BB, PPC::LOADHiAddr, 2, Tmp1).addReg(getGlobalBaseReg())
+  BuildMI(BB, PPC::ADDIS, 2, Tmp1).addReg(getGlobalBaseReg())
     .addConstantPoolIndex(CPI);
   BuildMI(BB, PPC::LFD, 2, Result).addConstantPoolIndex(CPI).addReg(Tmp1);
   return Result;
@@ -909,7 +909,7 @@
       // Load constant fp value
       unsigned Tmp4 = MakeReg(MVT::i32);
       unsigned TmpL = MakeReg(MVT::i32);
-      BuildMI(BB, PPC::LOADHiAddr, 2, Tmp4).addReg(getGlobalBaseReg())
+      BuildMI(BB, PPC::ADDIS, 2, Tmp4).addReg(getGlobalBaseReg())
         .addConstantPoolIndex(CPI);
       BuildMI(BB, PPC::LFD, 2, ConstF).addConstantPoolIndex(CPI).addReg(Tmp4);
       // Store the hi & low halves of the fp value, currently in int regs
@@ -1002,7 +1002,7 @@
   case ISD::ConstantPool:
     Tmp1 = cast<ConstantPoolSDNode>(N)->getIndex();
     Tmp2 = MakeReg(MVT::i64);
-    BuildMI(BB, PPC::LOADHiAddr, 2, Tmp2).addReg(getGlobalBaseReg())
+    BuildMI(BB, PPC::ADDIS, 2, Tmp2).addReg(getGlobalBaseReg())
       .addConstantPoolIndex(Tmp1);
     BuildMI(BB, PPC::LA, 2, Result).addReg(Tmp2).addConstantPoolIndex(Tmp1);
     return Result;
@@ -1015,7 +1015,7 @@
   case ISD::GlobalAddress: {
     GlobalValue *GV = cast<GlobalAddressSDNode>(N)->getGlobal();
     Tmp1 = MakeReg(MVT::i64);
-    BuildMI(BB, PPC::LOADHiAddr, 2, Tmp1).addReg(getGlobalBaseReg())
+    BuildMI(BB, PPC::ADDIS, 2, Tmp1).addReg(getGlobalBaseReg())
       .addGlobalAddress(GV);
     if (GV->hasWeakLinkage() || GV->isExternal()) {
       BuildMI(BB, PPC::LD, 2, Result).addGlobalAddress(GV).addReg(Tmp1);
@@ -1057,7 +1057,7 @@
     if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(Address)) {
       Tmp1 = MakeReg(MVT::i64);
       int CPI = CP->getIndex();
-      BuildMI(BB, PPC::LOADHiAddr, 2, Tmp1).addReg(getGlobalBaseReg())
+      BuildMI(BB, PPC::ADDIS, 2, Tmp1).addReg(getGlobalBaseReg())
         .addConstantPoolIndex(CPI);
       BuildMI(BB, Opc, 2, Result).addConstantPoolIndex(CPI).addReg(Tmp1);
     }


Index: llvm/lib/Target/PowerPC/PowerPC.h
diff -u llvm/lib/Target/PowerPC/PowerPC.h:1.16 llvm/lib/Target/PowerPC/PowerPC.h:1.17
--- llvm/lib/Target/PowerPC/PowerPC.h:1.16	Tue Jul 19 11:51:05 2005
+++ llvm/lib/Target/PowerPC/PowerPC.h	Thu Jul 21 15:44:42 2005
@@ -28,6 +28,9 @@
 FunctionPass *createPPC64ISelPattern(TargetMachine &TM);
 FunctionPass *createDarwinAsmPrinter(std::ostream &OS, TargetMachine &TM);
 FunctionPass *createAIXAsmPrinter(std::ostream &OS, TargetMachine &TM);
+
+extern bool GPOPT;
+extern bool PICEnabled;
 } // end namespace llvm;
 
 // GCC #defines PPC on Linux but we use it as our namespace name


Index: llvm/lib/Target/PowerPC/PowerPCAsmPrinter.cpp
diff -u llvm/lib/Target/PowerPC/PowerPCAsmPrinter.cpp:1.81 llvm/lib/Target/PowerPC/PowerPCAsmPrinter.cpp:1.82
--- llvm/lib/Target/PowerPC/PowerPCAsmPrinter.cpp:1.81	Wed Jul 20 20:25:49 2005
+++ llvm/lib/Target/PowerPC/PowerPCAsmPrinter.cpp	Thu Jul 21 15:44:42 2005
@@ -135,21 +135,28 @@
     }
     void printSymbolHi(const MachineInstr *MI, unsigned OpNo,
                        MVT::ValueType VT) {
-      O << "ha16(";
-      printOp(MI->getOperand(OpNo));
-      O << "-\"L0000" << LabelNumber << "$pb\")";
+      if (MI->getOperand(OpNo).isImmediate()) {
+        printS16ImmOperand(MI, OpNo, VT);
+      } else {
+        O << "ha16(";
+        printOp(MI->getOperand(OpNo));
+        if (PICEnabled)
+          O << "-\"L0000" << LabelNumber << "$pb\")";
+        else
+          O << ')';
+      }
     }
     void printSymbolLo(const MachineInstr *MI, unsigned OpNo,
                        MVT::ValueType VT) {
-      // FIXME: Because LFS, LFD, and LWZ can be used either with a s16imm or
-      // a lo16 of a global or constant pool operand, we must handle both here.
-      // this isn't a great design, but it works for now.
       if (MI->getOperand(OpNo).isImmediate()) {
-        O << (short)MI->getOperand(OpNo).getImmedValue();
+        printS16ImmOperand(MI, OpNo, VT);
       } else {
         O << "lo16(";
         printOp(MI->getOperand(OpNo));
-        O << "-\"L0000" << LabelNumber << "$pb\")";
+        if (PICEnabled)
+          O << "-\"L0000" << LabelNumber << "$pb\")";
+        else
+          O << ')';
       }
     }
     void printcrbit(const MachineInstr *MI, unsigned OpNo,
@@ -428,9 +435,7 @@
 }
 
 bool DarwinAsmPrinter::doInitialization(Module &M) {
-  // FIXME: implment subtargets for PowerPC and pick this up from there.
-  O << "\t.machine ppc970\n";
-
+  if (GPOPT) O << "\t.machine ppc970\n";
   AsmPrinter::doInitialization(M);
   return false;
 }
@@ -504,6 +509,7 @@
   for (std::set<std::string>::iterator i = FnStubs.begin(), e = FnStubs.end();
        i != e; ++i)
   {
+    if (PICEnabled) {
     O << ".data\n";
     O << ".section __TEXT,__picsymbolstub1,symbol_stubs,pure_instructions,32\n";
     emitAlignment(2);
@@ -523,6 +529,20 @@
     O << "L" << *i << "$lazy_ptr:\n";
     O << "\t.indirect_symbol " << *i << "\n";
     O << "\t.long dyld_stub_binding_helper\n";
+    } else {
+    O << "\t.section __TEXT,__symbol_stub1,symbol_stubs,pure_instructions,16\n";
+    emitAlignment(4);
+    O << "L" << *i << "$stub:\n";
+    O << "\t.indirect_symbol " << *i << "\n";
+    O << "\tlis r11,ha16(L" << *i << "$lazy_ptr)\n";
+    O << "\tlwzu r12,lo16(L" << *i << "$lazy_ptr)(r11)\n";
+    O << "\tmtctr r12\n";
+    O << "\tbctr\n";
+    O << "\t.lazy_symbol_pointer\n";
+    O << "L" << *i << "$lazy_ptr:\n";
+    O << "\t.indirect_symbol " << *i << "\n";
+    O << "\t.long dyld_stub_binding_helper\n";
+    }
   }
 
   O << "\n";


Index: llvm/lib/Target/PowerPC/PowerPCInstrInfo.td
diff -u llvm/lib/Target/PowerPC/PowerPCInstrInfo.td:1.74 llvm/lib/Target/PowerPC/PowerPCInstrInfo.td:1.75
--- llvm/lib/Target/PowerPC/PowerPCInstrInfo.td:1.74	Wed Jul 20 17:42:00 2005
+++ llvm/lib/Target/PowerPC/PowerPCInstrInfo.td	Thu Jul 21 15:44:43 2005
@@ -108,17 +108,17 @@
 // register and an immediate are of this type.
 //
 let isLoad = 1 in {
-def LBZ : DForm_1<34, (ops GPRC:$rD, s16imm:$disp, GPRC:$rA),
+def LBZ : DForm_1<34, (ops GPRC:$rD, symbolLo:$disp, GPRC:$rA),
                   "lbz $rD, $disp($rA)">;
-def LHA : DForm_1<42, (ops GPRC:$rD, s16imm:$disp, GPRC:$rA),
+def LHA : DForm_1<42, (ops GPRC:$rD, symbolLo:$disp, GPRC:$rA),
                   "lha $rD, $disp($rA)">;
-def LHZ : DForm_1<40, (ops GPRC:$rD, s16imm:$disp, GPRC:$rA),
+def LHZ : DForm_1<40, (ops GPRC:$rD, symbolLo:$disp, GPRC:$rA),
                   "lhz $rD, $disp($rA)">;
 def LMW : DForm_1<46, (ops GPRC:$rD, s16imm:$disp, GPRC:$rA),
                   "lmw $rD, $disp($rA)">;
 def LWZ : DForm_1<32, (ops GPRC:$rD, symbolLo:$disp, GPRC:$rA),
                   "lwz $rD, $disp($rA)">;
-def LWZU : DForm_1<35, (ops GPRC:$rD, symbolLo:$disp, GPRC:$rA),
+def LWZU : DForm_1<35, (ops GPRC:$rD, s16imm:$disp, GPRC:$rA),
                    "lwzu $rD, $disp($rA)">;
 }
 def ADDI   : DForm_2<14, (ops GPRC:$rD, GPRC:$rA, s16imm:$imm),
@@ -127,28 +127,26 @@
                      "addic $rD, $rA, $imm">;
 def ADDICo : DForm_2<13, (ops GPRC:$rD, GPRC:$rA, s16imm:$imm),
                      "addic. $rD, $rA, $imm">;
-def ADDIS  : DForm_2<15, (ops GPRC:$rD, GPRC:$rA, s16imm:$imm),
+def ADDIS  : DForm_2<15, (ops GPRC:$rD, GPRC:$rA, symbolHi:$imm),
                      "addis $rD, $rA, $imm">;
 def LA     : DForm_2<14, (ops GPRC:$rD, GPRC:$rA, symbolLo:$sym),
                      "la $rD, $sym($rA)">;
-def LOADHiAddr : DForm_2<15, (ops GPRC:$rD, GPRC:$rA, symbolHi:$sym),
-                         "addis $rD, $rA, $sym">;
 def MULLI  : DForm_2< 7, (ops GPRC:$rD, GPRC:$rA, s16imm:$imm),
                      "mulli $rD, $rA, $imm">;
 def SUBFIC : DForm_2< 8, (ops GPRC:$rD, GPRC:$rA, s16imm:$imm),
                      "subfic $rD, $rA, $imm">;
 def LI  : DForm_2_r0<14, (ops GPRC:$rD, s16imm:$imm),
                      "li $rD, $imm">;
-def LIS : DForm_2_r0<15, (ops GPRC:$rD, s16imm:$imm),
+def LIS : DForm_2_r0<15, (ops GPRC:$rD, symbolHi:$imm),
                      "lis $rD, $imm">;
 let isStore = 1 in {
 def STMW : DForm_3<47, (ops GPRC:$rS, s16imm:$disp, GPRC:$rA),
                    "stmw $rS, $disp($rA)">;
-def STB  : DForm_3<38, (ops GPRC:$rS, s16imm:$disp, GPRC:$rA),
+def STB  : DForm_3<38, (ops GPRC:$rS, symbolLo:$disp, GPRC:$rA),
                    "stb $rS, $disp($rA)">;
-def STH  : DForm_3<44, (ops GPRC:$rS, s16imm:$disp, GPRC:$rA),
+def STH  : DForm_3<44, (ops GPRC:$rS, symbolLo:$disp, GPRC:$rA),
                    "sth $rS, $disp($rA)">;
-def STW  : DForm_3<36, (ops GPRC:$rS, s16imm:$disp, GPRC:$rA),
+def STW  : DForm_3<36, (ops GPRC:$rS, symbolLo:$disp, GPRC:$rA),
                    "stw $rS, $disp($rA)">;
 def STWU : DForm_3<37, (ops GPRC:$rS, s16imm:$disp, GPRC:$rA),
                    "stwu $rS, $disp($rA)">;
@@ -185,9 +183,9 @@
                   "lfd $rD, $disp($rA)">;
 }
 let isStore = 1 in {
-def STFS : DForm_9<52, (ops GPRC:$rS, s16imm:$disp, GPRC:$rA),
+def STFS : DForm_9<52, (ops GPRC:$rS, symbolLo:$disp, GPRC:$rA),
                    "stfs $rS, $disp($rA)">;
-def STFD : DForm_9<54, (ops GPRC:$rS, s16imm:$disp, GPRC:$rA),
+def STFD : DForm_9<54, (ops GPRC:$rS, symbolLo:$disp, GPRC:$rA),
                    "stfd $rS, $disp($rA)">;
 }
 


Index: llvm/lib/Target/PowerPC/PowerPCTargetMachine.cpp
diff -u llvm/lib/Target/PowerPC/PowerPCTargetMachine.cpp:1.55 llvm/lib/Target/PowerPC/PowerPCTargetMachine.cpp:1.56
--- llvm/lib/Target/PowerPC/PowerPCTargetMachine.cpp:1.55	Thu Jul 21 14:17:18 2005
+++ llvm/lib/Target/PowerPC/PowerPCTargetMachine.cpp	Thu Jul 21 15:44:43 2005
@@ -29,6 +29,8 @@
 #include <iostream>
 using namespace llvm;
 
+bool llvm::GPOPT = false;
+
 namespace llvm {
   cl::opt<bool> AIX("aix",
                     cl::desc("Generate AIX/xcoff instead of Darwin/MachO"),
@@ -36,6 +38,9 @@
   cl::opt<bool> EnablePPCLSR("enable-lsr-for-ppc",
                              cl::desc("Enable LSR for PPC (beta)"),
                              cl::Hidden);
+  cl::opt<bool, true> EnableGPOPT("enable-gpopt", cl::Hidden,
+                                  cl::location(GPOPT),
+                                  cl::desc("Enable optimizations for GP cpus"));
 }
 
 namespace {
@@ -127,8 +132,11 @@
 }
 
 void PowerPCJITInfo::addPassesToJITCompile(FunctionPassManager &PM) {
-  bool LP64 = (0 != dynamic_cast<PPC64TargetMachine *>(&TM));
+  // The JIT does not support or need PIC.
+  PICEnabled = false;
 
+  bool LP64 = (0 != dynamic_cast<PPC64TargetMachine *>(&TM));
+  
   if (EnablePPCLSR) {
     PM.add(createLoopStrengthReducePass());
     PM.add(createCFGSimplificationPass());
@@ -170,7 +178,7 @@
 ///
 PPC32TargetMachine::PPC32TargetMachine(const Module &M, IntrinsicLowering *IL)
   : PowerPCTargetMachine(PPC32ID, IL,
-                         TargetData(PPC32ID,false,4,4,8,4,4,4,2,1,1),
+                         TargetData(PPC32ID,false,4,4,4,4,4,4,2,1,1),
                          PowerPCFrameInfo(*this, false)), JITInfo(*this) {}
 
 /// PPC64TargetMachine ctor - Create a LP64 architecture model





From lattner at cs.uiuc.edu  Thu Jul 21 16:55:19 2005
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Thu, 21 Jul 2005 16:55:19 -0500
Subject: [llvm-commits] 
	CVS: llvm/test/Regression/C++Frontend/2005-07-21-VirtualBaseAccess.cpp
Message-ID: <200507212155.QAA17330@zion.cs.uiuc.edu>



Changes in directory llvm/test/Regression/C++Frontend:

2005-07-21-VirtualBaseAccess.cpp added (r1.1)
---
Log message:

new testcase for PR602: http://llvm.cs.uiuc.edu/PR602 


---
Diffs of the changes:  (+14 -0)

 2005-07-21-VirtualBaseAccess.cpp |   14 ++++++++++++++
 1 files changed, 14 insertions(+)


Index: llvm/test/Regression/C++Frontend/2005-07-21-VirtualBaseAccess.cpp
diff -c /dev/null llvm/test/Regression/C++Frontend/2005-07-21-VirtualBaseAccess.cpp:1.1
*** /dev/null	Thu Jul 21 16:55:18 2005
--- llvm/test/Regression/C++Frontend/2005-07-21-VirtualBaseAccess.cpp	Thu Jul 21 16:55:08 2005
***************
*** 0 ****
--- 1,14 ----
+ // RUN: %llvmgxx -xc++ %s -c -o - | llvm-dis | not grep cast
+ 
+ void foo(int*);
+ 
+ struct FOO {
+   int X;
+ };
+ 
+ struct BAR : virtual FOO { BAR(); };
+ 
+ int testfn() {
+   BAR B;
+   foo(&B.X);
+ }





From lattner at cs.uiuc.edu  Thu Jul 21 16:56:14 2005
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Thu, 21 Jul 2005 16:56:14 -0500
Subject: [llvm-commits] CVS: llvm-gcc/gcc/cp/class.c 
Message-ID: <200507212156.QAA17367@zion.cs.uiuc.edu>



Changes in directory llvm-gcc/gcc/cp:

class.c updated: 1.1.1.2 -> 1.2
---
Log message:

Fix PR602: http://llvm.cs.uiuc.edu/PR602  and Regression/C++Frontend/2005-07-21-VirtualBaseAccess.cpp, 
by forcing GCC to be more careful about the way it emits its unsafe pointer
casts.



---
Diffs of the changes:  (+15 -1)

 class.c |   16 +++++++++++++++-
 1 files changed, 15 insertions(+), 1 deletion(-)


Index: llvm-gcc/gcc/cp/class.c
diff -u llvm-gcc/gcc/cp/class.c:1.1.1.2 llvm-gcc/gcc/cp/class.c:1.2
--- llvm-gcc/gcc/cp/class.c:1.1.1.2	Tue Jan 13 10:49:36 2004
+++ llvm-gcc/gcc/cp/class.c	Thu Jul 21 16:56:03 2005
@@ -36,6 +36,7 @@
 #include "lex.h"
 #include "target.h"
 #include "convert.h"
+#include "llvm-out.h"
 
 /* The number of nested classes being processed.  If we are not in the
    scope of any class, this is zero.  */
@@ -356,12 +357,25 @@
   if (want_pointer)
     target_type = ptr_target_type;
   
-  expr = build1 (NOP_EXPR, ptr_target_type, expr);
+  /* To go from a derived class to a base member, do NOT first cast from
+   * derived* to base* then add an offset.  This sort of evil behavior results
+   * in invalid getelementptr instructions.
+   */
+#ifdef EMIT_LLVM
+  if (!integer_zerop (offset))
+    expr = build (code, ptr_target_type, expr, offset);
+  else
+    null_test = NULL;
 
+  expr = build1 (NOP_EXPR, ptr_target_type, expr);
+#else
+  expr = build1 (NOP_EXPR, ptr_target_type, expr);
+  
   if (!integer_zerop (offset))
     expr = build (code, ptr_target_type, expr, offset);
   else
     null_test = NULL;
+#endif  
   
   if (!want_pointer)
     expr = build_indirect_ref (expr, NULL);





From lattner at cs.uiuc.edu  Fri Jul 22 13:50:42 2005
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Fri, 22 Jul 2005 13:50:42 -0500
Subject: [llvm-commits] CVS: llvm-gcc/gcc/llvm-internals.h llvm-expand.c 
Message-ID: <200507221850.NAA03192@zion.cs.uiuc.edu>



Changes in directory llvm-gcc/gcc:

llvm-internals.h updated: 1.3 -> 1.4
llvm-expand.c updated: 1.106 -> 1.107
---
Log message:

eliminate a warning in llvm-types.c


---
Diffs of the changes:  (+1 -3)

 llvm-expand.c    |    3 ---
 llvm-internals.h |    1 +
 2 files changed, 1 insertion(+), 3 deletions(-)


Index: llvm-gcc/gcc/llvm-internals.h
diff -u llvm-gcc/gcc/llvm-internals.h:1.3 llvm-gcc/gcc/llvm-internals.h:1.4
--- llvm-gcc/gcc/llvm-internals.h:1.3	Sun Nov 28 01:52:17 2004
+++ llvm-gcc/gcc/llvm-internals.h	Fri Jul 22 13:50:31 2005
@@ -69,6 +69,7 @@
                                            unsigned *BitStart,
                                            unsigned *BitSize);
 
+extern int isPassedByInvisibleReference(union tree_node *Type);
 
 void llvm_expand_function_end(struct llvm_function *Fn, union tree_node *subr,
                               int end_bindings);


Index: llvm-gcc/gcc/llvm-expand.c
diff -u llvm-gcc/gcc/llvm-expand.c:1.106 llvm-gcc/gcc/llvm-expand.c:1.107
--- llvm-gcc/gcc/llvm-expand.c:1.106	Wed Jul 20 19:56:59 2005
+++ llvm-gcc/gcc/llvm-expand.c	Fri Jul 22 13:50:31 2005
@@ -62,9 +62,6 @@
 static void llvm_expand_expr_stmt_value(llvm_function *Fn, tree exp,
                                         int isLast);
 
-extern int isPassedByInvisibleReference(tree Type);
-
-
 /* Debugging info emitter functions. */
 static void llvm_emit_dbg_stoppoint(llvm_function *Fn, unsigned lineNo, 
                                     unsigned colNo);





From lattner at cs.uiuc.edu  Fri Jul 22 13:51:22 2005
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Fri, 22 Jul 2005 13:51:22 -0500
Subject: [llvm-commits] CVS: llvm-gcc/gcc/llvm-out.h 
Message-ID: <200507221851.NAA03251@zion.cs.uiuc.edu>



Changes in directory llvm-gcc/gcc:

llvm-out.h updated: 1.5 -> 1.6
---
Log message:

This is in theory more portable.  It probably doesn't make a difference
in practice


---
Diffs of the changes:  (+1 -0)

 llvm-out.h |    1 +
 1 files changed, 1 insertion(+)


Index: llvm-gcc/gcc/llvm-out.h
diff -u llvm-gcc/gcc/llvm-out.h:1.5 llvm-gcc/gcc/llvm-out.h:1.6
--- llvm-gcc/gcc/llvm-out.h:1.5	Thu Nov 18 14:44:23 2004
+++ llvm-gcc/gcc/llvm-out.h	Fri Jul 22 13:51:11 2005
@@ -26,6 +26,7 @@
 #ifndef GCC_LLVM_OUT_H
 #define GCC_LLVM_OUT_H
 
+#include <stdarg.h>
 #include <stdio.h>
 
 #define EMIT_LLVM 1





From lattner at cs.uiuc.edu  Fri Jul 22 13:53:49 2005
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Fri, 22 Jul 2005 13:53:49 -0500
Subject: [llvm-commits] CVS: llvm-gcc/gcc/llvm-representation.h llvm-types.c
Message-ID: <200507221853.NAA03370@zion.cs.uiuc.edu>



Changes in directory llvm-gcc/gcc:

llvm-representation.h updated: 1.17 -> 1.18
llvm-types.c updated: 1.23 -> 1.24
---
Log message:

Two changes: 
  1. fix some warnings in llvm-types.c
  2. Add the ability to determine the alignment of llvm-types as the LLVM
     code generator will see them.  This will be used in the future.

No functionality change here.



---
Diffs of the changes:  (+106 -4)

 llvm-representation.h |   10 ++++-
 llvm-types.c          |  100 ++++++++++++++++++++++++++++++++++++++++++++++++--
 2 files changed, 106 insertions(+), 4 deletions(-)


Index: llvm-gcc/gcc/llvm-representation.h
diff -u llvm-gcc/gcc/llvm-representation.h:1.17 llvm-gcc/gcc/llvm-representation.h:1.18
--- llvm-gcc/gcc/llvm-representation.h:1.17	Thu Jul  7 12:32:46 2005
+++ llvm-gcc/gcc/llvm-representation.h	Fri Jul 22 13:53:38 2005
@@ -392,7 +392,8 @@
     struct {
       char *TypeName;          /* Name given to the type */
       unsigned Size;           /* The size (in bytes) of the structure */
-
+      unsigned Alignment;      /* The LLVM alignment of the struct */
+      
       /* MemberOffsets - If non-null, contains an entry for each type element
        * with its offset from start of the structure.
        */
@@ -400,6 +401,7 @@
     } Struct;
     struct {
       unsigned Size;           /* Number of elements in the array */
+      unsigned Alignment;      /* LLVM Alignment of the type */
     } Array;
     struct {
       char *TypeName;          /* Name given to opaque struct type */
@@ -433,6 +435,12 @@
 
 unsigned llvm_type_get_size(llvm_type *Ty);
 
+/* llvm_type_get_alignment - Return the alignment of the specified LLVM type as
+ * it will be handled by the target.  Note that LLVM types may be less aligned
+ * than the corresponding C types.
+ */
+unsigned llvm_type_get_alignment(llvm_type *Ty);
+
 unsigned llvm_type_get_composite_num_elements(llvm_type *Ty);
 llvm_type *llvm_type_get_composite_element(llvm_type *Ty, unsigned N);
 llvm_type *llvm_type_get_integer(unsigned NumBits, int isUnsigned);


Index: llvm-gcc/gcc/llvm-types.c
diff -u llvm-gcc/gcc/llvm-types.c:1.23 llvm-gcc/gcc/llvm-types.c:1.24
--- llvm-gcc/gcc/llvm-types.c:1.23	Sat Jun 18 16:11:20 2005
+++ llvm-gcc/gcc/llvm-types.c	Fri Jul 22 13:53:38 2005
@@ -27,6 +27,7 @@
 #include "llvm-representation.h"
 #include "llvm-internals.h"
 #include "hashtab.h"
+#include "langhooks.h"
 #include <assert.h>
 #include <string.h>
 
@@ -69,6 +70,84 @@
   }
 }
 
+/* PrimitiveAlignments - This contains the alignments of all of the primitive
+ * LLVM types on this target.
+ */
+static unsigned PrimitiveAlignments[OpaqueTyID];
+
+static unsigned getMinTargetAlignment(tree Type) {
+  unsigned BasicAlignment = TYPE_ALIGN(Type);
+  unsigned TestAlignment;
+  
+  /* Some targets do funny things with structs.  Form a struct that has a
+   * character member as the first element, then Type as the second element.
+   * If that alignment is less than BasicAlignment, use it.
+   */
+  tree recordtype = (*lang_hooks.types.make_type) (RECORD_TYPE);
+  tree field, fields;
+  /* First character field. */
+  fields = build_decl (FIELD_DECL, NULL_TREE, unsigned_intQI_type_node);
+
+  /* A field of type Type. */
+  field = build_decl (FIELD_DECL, NULL_TREE, Type);
+  TREE_CHAIN (field) = fields;
+  finish_builtin_struct(recordtype, "", field, NULL_TREE);
+
+  llvm_type_dump(llvm_type_get_from_tree(recordtype));
+  
+  TestAlignment = TYPE_ALIGN(recordtype);
+  BasicAlignment = MIN(BasicAlignment, TestAlignment);
+  return BasicAlignment/8;
+}
+
+static void InitializeAlignments(void) {
+  /* Figure out the alignments of the primitive types. */
+  PrimitiveAlignments[BoolTyID]   = 1;
+  PrimitiveAlignments[SByteTyID]  = 1;
+  PrimitiveAlignments[UByteTyID]  = 1;
+  PrimitiveAlignments[ShortTyID]  = getMinTargetAlignment(intHI_type_node);
+  PrimitiveAlignments[UShortTyID] =
+    getMinTargetAlignment(unsigned_intHI_type_node);
+  PrimitiveAlignments[IntTyID]  = getMinTargetAlignment(intSI_type_node);
+  PrimitiveAlignments[UIntTyID] = 
+    getMinTargetAlignment(unsigned_intSI_type_node);
+  PrimitiveAlignments[LongTyID]  = getMinTargetAlignment(intDI_type_node);
+  PrimitiveAlignments[ULongTyID] =
+    getMinTargetAlignment(unsigned_intDI_type_node);
+  PrimitiveAlignments[FloatTyID] = getMinTargetAlignment(float_type_node);
+  PrimitiveAlignments[DoubleTyID]  = getMinTargetAlignment(double_type_node);
+  PrimitiveAlignments[PointerTyID] = getMinTargetAlignment(ptr_type_node);
+}
+
+unsigned llvm_type_get_alignment(llvm_type *Ty) {
+  switch (Ty->ID) {
+    case BoolTyID:   
+    case SByteTyID:  
+    case UByteTyID:  return 1;
+    case ShortTyID:  
+    case UShortTyID: 
+    case UIntTyID:   
+    case FloatTyID:  
+    case IntTyID:    
+    case ULongTyID:  
+    case LongTyID:   
+    case DoubleTyID:
+    case PointerTyID: {/* Target dependant pointer size */
+      static int AlignmentInited = 0;
+      if (AlignmentInited == 0) { AlignmentInited = 1; InitializeAlignments(); }
+      return PrimitiveAlignments[Ty->ID];
+    }
+    case ArrayTyID: return Ty->x.Array.Alignment;
+    case StructTyID: return Ty->x.Struct.Alignment;
+    default: 
+      fprintf(stderr, "ERROR: Type doesn't have size: ");
+      llvm_type_dump(Ty);
+      fprintf(stderr, "\n");
+      abort();
+  }
+}
+
+
 /* All of the primitive types... */
 static llvm_type TheVoidTy   = { VoidTyID, 0, {{0}}, 0, {0} };
 static llvm_type TheBoolTy   = { BoolTyID , 0, {{0}}, 0, {0} };
@@ -203,11 +282,11 @@
 
   /* Commonly used derived types... */
   VoidPtrTy = llvm_type_get_pointer(VoidTy);
-
   IntPtrTy = llvm_type_get_size(VoidPtrTy) == 4 ? IntTy : LongTy;
 }
 
 llvm_type *llvm_type_get_cannonical_struct(llvm_type *Ty) {
+  unsigned i, e, MaxAlignment;
   void **Slot = htab_find_slot(StructTable, Ty, INSERT);
   if (*Slot) {    /* Found a match! */
     if (*Slot != Ty) free(Ty);
@@ -220,6 +299,14 @@
   Ty->NextTypeLink = DerivedTypesList;
   DerivedTypesList = Ty;
 
+  /* Set the alignment of the struct as the max alignment of all members. */
+  MaxAlignment = 1;
+  for (i = 0, e = Ty->NumElements; i != e; ++i) {
+    unsigned EltAlign = llvm_type_get_alignment(Ty->Elements[i]);
+    if (EltAlign > MaxAlignment) MaxAlignment = EltAlign;
+  }
+  Ty->x.Struct.Alignment = MaxAlignment;
+
   /*printf("Created new type: "); DebugType(Ty); printf("\n"); */
   return *Slot = Ty;
 }
@@ -259,6 +346,11 @@
   Result->NumElements = 1;
   Result->Elements[0] = Ty;
   Result->x.Array.Size = NumElements;
+
+  /* Alignment of the array is alignment of the element. */
+  Result->x.Array.Alignment = llvm_type_get_alignment(Ty);
+  
+  /* Add array to list of arrays we have seen. */
   Result->NextTypeLink = ArrayTypesList;
   ArrayTypesList = Result;
   return Result;
@@ -304,6 +396,7 @@
 llvm_type *llvm_type_create_struct(unsigned NumElements, unsigned Size) {
   /* The amount of space  we need to allocate for the type */
   unsigned type_size;
+  llvm_type *Result;
 
   /*
    * Determine the amount of memory needed for the type.  Note that
@@ -313,7 +406,7 @@
   type_size += ((NumElements) ? (NumElements-1)*sizeof(llvm_type*) : 0);
 
   /* Do the memory allocation and type initialization. */
-  llvm_type * Result = (llvm_type*)xcalloc(1, type_size);
+  Result = (llvm_type*)xcalloc(1, type_size);
   Result->ID = StructTyID;
   Result->NumElements = NumElements;
   Result->x.Struct.Size = Size;
@@ -617,8 +710,9 @@
  * structure.
  */
 static unsigned GetFieldOffset(tree Field) {
+  unsigned Result;
   assert(DECL_FIELD_BIT_OFFSET(Field) != 0 && DECL_FIELD_OFFSET(Field) != 0);
-  unsigned Result = TREE_INT_CST_LOW(DECL_FIELD_BIT_OFFSET(Field));
+  Result = TREE_INT_CST_LOW(DECL_FIELD_BIT_OFFSET(Field));
   if (TREE_CODE(DECL_FIELD_OFFSET(Field)) == INTEGER_CST)
     Result += TREE_INT_CST_LOW(DECL_FIELD_OFFSET(Field))*8;
   return Result;





From alenhar2 at cs.uiuc.edu  Fri Jul 22 15:46:54 2005
From: alenhar2 at cs.uiuc.edu (Andrew Lenharth)
Date: Fri, 22 Jul 2005 15:46:54 -0500
Subject: [llvm-commits] CVS: llvm/include/llvm/CodeGen/MachineRelocation.h 
Message-ID: <200507222046.PAA03764@zion.cs.uiuc.edu>



Changes in directory llvm/include/llvm/CodeGen:

MachineRelocation.h updated: 1.5 -> 1.6
---
Log message:

allow constants to be relocated like GV (necessary for alpha, as constants are relocated with globals, not with .text), and allow targets to have a GOT managed for them

---
Diffs of the changes:  (+57 -6)

 MachineRelocation.h |   63 +++++++++++++++++++++++++++++++++++++++++++++++-----
 1 files changed, 57 insertions(+), 6 deletions(-)


Index: llvm/include/llvm/CodeGen/MachineRelocation.h
diff -u llvm/include/llvm/CodeGen/MachineRelocation.h:1.5 llvm/include/llvm/CodeGen/MachineRelocation.h:1.6
--- llvm/include/llvm/CodeGen/MachineRelocation.h:1.5	Thu Apr 21 15:38:00 2005
+++ llvm/include/llvm/CodeGen/MachineRelocation.h	Fri Jul 22 15:46:42 2005
@@ -32,23 +32,33 @@
 ///   4. An optional constant value to be added to the reference.
 ///   5. A bit, CanRewrite, which indicates to the JIT that a function stub is
 ///      not needed for the relocation.
+///   6. An index into the GOT, if the target uses a GOT
 ///
 class MachineRelocation {
   /// OffsetTypeExternal - The low 24-bits of this value is the offset from the
   /// start of the code buffer of the relocation to perform.  Bit 24 of this is
   /// set if Target should use ExtSym instead of GV, Bit 25 is the CanRewrite
   /// bit, and the high 6 bits hold the relocation type.
+  // FIXME: with the additional types of relocatable things, rearrange the
+  // storage of things to be a bit more effiecient
   unsigned OffsetTypeExternal;
   union {
     GlobalValue *GV;     // If this is a pointer to an LLVM global
     const char *ExtSym;  // If this is a pointer to a named symbol
     void *Result;        // If this has been resolved to a resolved pointer
+    unsigned GOTIndex;   // Index in the GOT of this symbol/global
+    unsigned CPool;      // Index in the Constant Pool
   } Target;
   intptr_t ConstantVal;
+  bool GOTRelative; //out of bits in OffsetTypeExternal
+  bool isConstPool;
+
 public:
   MachineRelocation(unsigned Offset, unsigned RelocationType, GlobalValue *GV,
-                    intptr_t cst = 0, bool DoesntNeedFunctionStub = 0)
-    : OffsetTypeExternal(Offset + (RelocationType << 26)), ConstantVal(cst) {
+                    intptr_t cst = 0, bool DoesntNeedFunctionStub = 0, 
+                    bool GOTrelative = 0)
+    : OffsetTypeExternal(Offset + (RelocationType << 26)), ConstantVal(cst),
+      GOTRelative(GOTrelative), isConstPool(0) {
     assert((Offset & ~((1 << 24)-1)) == 0 && "Code offset too large!");
     assert((RelocationType & ~63) == 0 && "Relocation type too large!");
     Target.GV = GV;
@@ -57,14 +67,23 @@
   }
 
   MachineRelocation(unsigned Offset, unsigned RelocationType, const char *ES,
-                    intptr_t cst = 0)
+                    intptr_t cst = 0, bool GOTrelative = 0)
     : OffsetTypeExternal(Offset + (1 << 24) + (RelocationType << 26)),
-    ConstantVal(cst) {
+      ConstantVal(cst), GOTRelative(GOTrelative), isConstPool(0) {
     assert((Offset & ~((1 << 24)-1)) == 0 && "Code offset too large!");
     assert((RelocationType & ~63) == 0 && "Relocation type too large!");
     Target.ExtSym = ES;
   }
 
+  MachineRelocation(unsigned Offset, unsigned RelocationType, unsigned CPI,
+                    intptr_t cst = 0)
+    : OffsetTypeExternal(Offset + (RelocationType << 26)),
+      ConstantVal(cst), GOTRelative(0), isConstPool(1) {
+    assert((Offset & ~((1 << 24)-1)) == 0 && "Code offset too large!");
+    assert((RelocationType & ~63) == 0 && "Relocation type too large!");
+    Target.CPool = CPI;
+  }
+
   /// getMachineCodeOffset - Return the offset into the code buffer that the
   /// relocation should be performed.
   unsigned getMachineCodeOffset() const {
@@ -87,13 +106,25 @@
   /// isGlobalValue - Return true if this relocation is a GlobalValue, as
   /// opposed to a constant string.
   bool isGlobalValue() const {
-    return (OffsetTypeExternal & (1 << 24)) == 0;
+    return (OffsetTypeExternal & (1 << 24)) == 0 && !isConstantPoolIndex();
   }
 
   /// isString - Return true if this is a constant string.
   ///
   bool isString() const {
-    return !isGlobalValue();
+    return !isGlobalValue() && !isConstantPoolIndex();
+  }
+
+  /// isConstantPoolIndex - Return true if this is a constant pool reference.
+  ///
+  bool isConstantPoolIndex() const {
+    return isConstPool;
+  }
+
+  /// isGOTRelative - Return true the target wants the index into the GOT of
+  /// the symbol rather than the address of the symbol.
+  bool isGOTRelative() const {
+    return GOTRelative;
   }
 
   /// doesntNeedFunctionStub - This function returns true if the JIT for this
@@ -119,6 +150,13 @@
     return Target.ExtSym;
   }
 
+  /// getConstantPoolIndex - If this is a const pool reference, return
+  /// the index into the constant pool.
+  unsigned getConstantPoolIndex() const {
+    assert(isConstantPoolIndex() && "This is not a constant pool reference!");
+    return Target.CPool;
+  }
+
   /// getResultPointer - Once this has been resolved to point to an actual
   /// address, this returns the pointer.
   void *getResultPointer() const {
@@ -130,6 +168,19 @@
   void setResultPointer(void *Ptr) {
     Target.Result = Ptr;
   }
+
+  /// setGOTIndex - Set the GOT index to a specific value.
+  void setGOTIndex(unsigned idx) {
+    Target.GOTIndex = idx;
+  }
+
+  /// getGOTIndex - Once this has been resolved to an entry in the GOT,
+  /// this returns that index.  The index is from the lowest address entry 
+  /// in the GOT.
+  unsigned getGOTIndex() const {
+    return Target.GOTIndex;
+  }
+
 };
 
 }





From alenhar2 at cs.uiuc.edu  Fri Jul 22 15:46:54 2005
From: alenhar2 at cs.uiuc.edu (Andrew Lenharth)
Date: Fri, 22 Jul 2005 15:46:54 -0500
Subject: [llvm-commits] CVS: llvm/include/llvm/Target/TargetJITInfo.h 
Message-ID: <200507222046.PAA03768@zion.cs.uiuc.edu>



Changes in directory llvm/include/llvm/Target:

TargetJITInfo.h updated: 1.6 -> 1.7
---
Log message:

allow constants to be relocated like GV (necessary for alpha, as constants are relocated with globals, not with .text), and allow targets to have a GOT managed for them

---
Diffs of the changes:  (+9 -1)

 TargetJITInfo.h |   10 +++++++++-
 1 files changed, 9 insertions(+), 1 deletion(-)


Index: llvm/include/llvm/Target/TargetJITInfo.h
diff -u llvm/include/llvm/Target/TargetJITInfo.h:1.6 llvm/include/llvm/Target/TargetJITInfo.h:1.7
--- llvm/include/llvm/Target/TargetJITInfo.h:1.6	Thu Apr 21 15:53:44 2005
+++ llvm/include/llvm/Target/TargetJITInfo.h	Fri Jul 22 15:46:42 2005
@@ -77,9 +77,17 @@
     /// it must rewrite the code to contain the actual addresses of any
     /// referenced global symbols.
     virtual void relocate(void *Function, MachineRelocation *MR,
-                          unsigned NumRelocs) {
+                          unsigned NumRelocs, unsigned char* GOTBase) {
       assert(NumRelocs == 0 && "This target does not have relocations!");
     }
+
+    /// needsGOT - Allows a target to specify that it would like the
+    // JIT to manage a GOT for it.
+    bool needsGOT() const { return useGOT; }
+
+  protected:
+    bool useGOT;
+
   };
 } // End llvm namespace
 





From alenhar2 at cs.uiuc.edu  Fri Jul 22 15:48:23 2005
From: alenhar2 at cs.uiuc.edu (Andrew Lenharth)
Date: Fri, 22 Jul 2005 15:48:23 -0500
Subject: [llvm-commits] CVS: llvm/lib/ExecutionEngine/JIT/JITEmitter.cpp 
Message-ID: <200507222048.PAA03823@zion.cs.uiuc.edu>



Changes in directory llvm/lib/ExecutionEngine/JIT:

JITEmitter.cpp updated: 1.69 -> 1.70
---
Log message:

the JIT memory manager will construct a GOT if you want it too.  Also, it places the constants in the allocated memory, rather than a malloc area

---
Diffs of the changes:  (+51 -9)

 JITEmitter.cpp |   60 ++++++++++++++++++++++++++++++++++++++++++++++++---------
 1 files changed, 51 insertions(+), 9 deletions(-)


Index: llvm/lib/ExecutionEngine/JIT/JITEmitter.cpp
diff -u llvm/lib/ExecutionEngine/JIT/JITEmitter.cpp:1.69 llvm/lib/ExecutionEngine/JIT/JITEmitter.cpp:1.70
--- llvm/lib/ExecutionEngine/JIT/JITEmitter.cpp:1.69	Wed Jul 20 11:29:20 2005
+++ llvm/lib/ExecutionEngine/JIT/JITEmitter.cpp	Fri Jul 22 15:48:12 2005
@@ -52,8 +52,9 @@
     unsigned char *FunctionBase; // Start of the function body area
     unsigned char *ConstantPool; // Memory allocated for constant pools
     unsigned char *CurStubPtr, *CurFunctionPtr, *CurConstantPtr;
+    unsigned char *GOTBase; //Target Specific reserved memory
   public:
-    JITMemoryManager();
+    JITMemoryManager(bool useGOT);
     ~JITMemoryManager();
 
     inline unsigned char *allocateStub(unsigned StubSize);
@@ -61,26 +62,34 @@
                                            unsigned Alignment);
     inline unsigned char *startFunctionBody();
     inline void endFunctionBody(unsigned char *FunctionEnd);
+    inline unsigned char* getGOTBase() const;
+
+    inline bool isManagingGOT() const;
   };
 }
 
-JITMemoryManager::JITMemoryManager() {
+JITMemoryManager::JITMemoryManager(bool useGOT) {
   // Allocate a 16M block of memory...
   MemBlock = sys::Memory::AllocateRWX((16 << 20));
   MemBase = reinterpret_cast<unsigned char*>(MemBlock.base());
-  FunctionBase = MemBase + 512*1024; // Use 512k for stubs
+  ConstantPool = MemBase;
+  GOTBase = ConstantPool + 512*1024; //512 for constants
+  //8k number of entries in the GOT
+  FunctionBase = GOTBase + 8192 * sizeof(void*) + 512*1024; // Use 512k for stubs
+
+  //make it easier to tell if we are managing the GOT
+  if (!useGOT)
+    GOTBase = NULL;
 
   // Allocate stubs backwards from the function base, allocate functions forward
   // from the function base.
   CurStubPtr = CurFunctionPtr = FunctionBase;
 
-  ConstantPool = new unsigned char [512*1024]; // Use 512k for constant pools
   CurConstantPtr = ConstantPool + 512*1024;
 }
 
 JITMemoryManager::~JITMemoryManager() {
   sys::Memory::ReleaseRWX(MemBlock);
-  delete[] ConstantPool;
 }
 
 unsigned char *JITMemoryManager::allocateStub(unsigned StubSize) {
@@ -117,6 +126,14 @@
   CurFunctionPtr = FunctionEnd;
 }
 
+unsigned char* JITMemoryManager::getGOTBase() const {
+  return GOTBase;
+}
+
+bool JITMemoryManager::isManagingGOT() const {
+  return GOTBase != NULL;
+}
+
 //===----------------------------------------------------------------------===//
 // JIT lazy compilation code.
 //
@@ -320,8 +337,17 @@
     /// Relocations - These are the relocations that the function needs, as
     /// emitted.
     std::vector<MachineRelocation> Relocations;
+
   public:
-    JITEmitter(JIT &jit) { TheJIT = &jit; }
+    JITEmitter(JIT &jit)
+      :MemMgr(jit.getJITInfo().needsGOT()), 
+       nextGOTIndex(0)
+    {
+      TheJIT = &jit; 
+      DEBUG(std::cerr << 
+            (MemMgr.isManagingGOT() ? "JIT is managing GOT\n" 
+             : "JIT is not managing GOT\n"));
+    }
 
     virtual void startFunction(MachineFunction &F);
     virtual void finishFunction(MachineFunction &F);
@@ -342,6 +368,8 @@
 
   private:
     void *getPointerToGlobal(GlobalValue *GV, void *Reference, bool NoNeedStub);
+    unsigned nextGOTIndex;
+    std::map<void*, unsigned> revGOTMap;
   };
 }
 
@@ -388,7 +416,6 @@
 
 void JITEmitter::finishFunction(MachineFunction &F) {
   MemMgr.endFunctionBody(CurByte);
-  ConstantPoolAddresses.clear();
   NumBytes += CurByte-CurBlock;
 
   if (!Relocations.empty()) {
@@ -404,15 +431,29 @@
         // If the target REALLY wants a stub for this function, emit it now.
         if (!MR.doesntNeedFunctionStub())
           ResultPtr = getJITResolver(this).getExternalFunctionStub(ResultPtr);
-      } else
+      } else if (MR.isGlobalValue()) 
         ResultPtr = getPointerToGlobal(MR.getGlobalValue(),
                                        CurBlock+MR.getMachineCodeOffset(),
                                        MR.doesntNeedFunctionStub());
+      else //ConstantPoolIndex
+        ResultPtr = 
+          (void*)getConstantPoolEntryAddress(MR.getConstantPoolIndex());
+      
       MR.setResultPointer(ResultPtr);
+
+      // if we are managing the got, check to see if this pointer has all ready
+      // been allocated a GOT entry.  If not, give it the next one.
+      if (MemMgr.isManagingGOT()) {
+        if (!revGOTMap[ResultPtr])
+          revGOTMap[ResultPtr] = ++nextGOTIndex;
+        ((void**)MemMgr.getGOTBase())[revGOTMap[ResultPtr]] = ResultPtr;
+        if(MR.isGOTRelative())
+          MR.setGOTIndex(revGOTMap[ResultPtr]);
+      }
     }
 
     TheJIT->getJITInfo().relocate(CurBlock, &Relocations[0],
-                                  Relocations.size());
+                                  Relocations.size(), MemMgr.getGOTBase());
   }
 
   DEBUG(std::cerr << "JIT: Finished CodeGen of [" << (void*)CurBlock
@@ -420,6 +461,7 @@
                   << ": " << CurByte-CurBlock << " bytes of text, "
                   << Relocations.size() << " relocations\n");
   Relocations.clear();
+  ConstantPoolAddresses.clear();
 }
 
 void JITEmitter::emitConstantPool(MachineConstantPool *MCP) {





From alenhar2 at cs.uiuc.edu  Fri Jul 22 15:49:49 2005
From: alenhar2 at cs.uiuc.edu (Andrew Lenharth)
Date: Fri, 22 Jul 2005 15:49:49 -0500
Subject: [llvm-commits] CVS: llvm/lib/Target/PowerPC/PPC32JITInfo.cpp
	PPC32JITInfo.h 
Message-ID: <200507222049.PAA03890@zion.cs.uiuc.edu>



Changes in directory llvm/lib/Target/PowerPC:

PPC32JITInfo.cpp updated: 1.13 -> 1.14
PPC32JITInfo.h updated: 1.5 -> 1.6
---
Log message:

update interface

---
Diffs of the changes:  (+2 -2)

 PPC32JITInfo.cpp |    2 +-
 PPC32JITInfo.h   |    2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)


Index: llvm/lib/Target/PowerPC/PPC32JITInfo.cpp
diff -u llvm/lib/Target/PowerPC/PPC32JITInfo.cpp:1.13 llvm/lib/Target/PowerPC/PPC32JITInfo.cpp:1.14
--- llvm/lib/Target/PowerPC/PPC32JITInfo.cpp:1.13	Thu Apr 21 18:20:02 2005
+++ llvm/lib/Target/PowerPC/PPC32JITInfo.cpp	Fri Jul 22 15:49:37 2005
@@ -188,7 +188,7 @@
 
 
 void PPC32JITInfo::relocate(void *Function, MachineRelocation *MR,
-                            unsigned NumRelocs) {
+                            unsigned NumRelocs, unsigned char* GOTBase) {
   for (unsigned i = 0; i != NumRelocs; ++i, ++MR) {
     unsigned *RelocPos = (unsigned*)Function + MR->getMachineCodeOffset()/4;
     intptr_t ResultPtr = (intptr_t)MR->getResultPointer();


Index: llvm/lib/Target/PowerPC/PPC32JITInfo.h
diff -u llvm/lib/Target/PowerPC/PPC32JITInfo.h:1.5 llvm/lib/Target/PowerPC/PPC32JITInfo.h:1.6
--- llvm/lib/Target/PowerPC/PPC32JITInfo.h:1.5	Thu Apr 21 18:20:02 2005
+++ llvm/lib/Target/PowerPC/PPC32JITInfo.h	Fri Jul 22 15:49:37 2005
@@ -27,7 +27,7 @@
     virtual void *emitFunctionStub(void *Fn, MachineCodeEmitter &MCE);
     virtual LazyResolverFn getLazyResolverFunction(JITCompilerFn);
     virtual void relocate(void *Function, MachineRelocation *MR,
-                          unsigned NumRelocs);
+                          unsigned NumRelocs, unsigned char* GOTBase);
 
     /// replaceMachineCodeForFunction - Make it so that calling the function
     /// whose machine code is at OLD turns into a call to NEW, perhaps by





From alenhar2 at cs.uiuc.edu  Fri Jul 22 15:49:49 2005
From: alenhar2 at cs.uiuc.edu (Andrew Lenharth)
Date: Fri, 22 Jul 2005 15:49:49 -0500
Subject: [llvm-commits] CVS: llvm/lib/Target/X86/X86JITInfo.cpp X86JITInfo.h
Message-ID: <200507222049.PAA03896@zion.cs.uiuc.edu>



Changes in directory llvm/lib/Target/X86:

X86JITInfo.cpp updated: 1.13 -> 1.14
X86JITInfo.h updated: 1.5 -> 1.6
---
Log message:

update interface

---
Diffs of the changes:  (+2 -2)

 X86JITInfo.cpp |    2 +-
 X86JITInfo.h   |    2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)


Index: llvm/lib/Target/X86/X86JITInfo.cpp
diff -u llvm/lib/Target/X86/X86JITInfo.cpp:1.13 llvm/lib/Target/X86/X86JITInfo.cpp:1.14
--- llvm/lib/Target/X86/X86JITInfo.cpp:1.13	Tue Jun  7 20:02:38 2005
+++ llvm/lib/Target/X86/X86JITInfo.cpp	Fri Jul 22 15:49:37 2005
@@ -174,7 +174,7 @@
 /// it must rewrite the code to contain the actual addresses of any
 /// referenced global symbols.
 void X86JITInfo::relocate(void *Function, MachineRelocation *MR,
-                          unsigned NumRelocs) {
+                          unsigned NumRelocs, unsigned char* GOTBase) {
   for (unsigned i = 0; i != NumRelocs; ++i, ++MR) {
     void *RelocPos = (char*)Function + MR->getMachineCodeOffset();
     intptr_t ResultPtr = (intptr_t)MR->getResultPointer();


Index: llvm/lib/Target/X86/X86JITInfo.h
diff -u llvm/lib/Target/X86/X86JITInfo.h:1.5 llvm/lib/Target/X86/X86JITInfo.h:1.6
--- llvm/lib/Target/X86/X86JITInfo.h:1.5	Thu Apr 21 18:38:14 2005
+++ llvm/lib/Target/X86/X86JITInfo.h	Fri Jul 22 15:49:37 2005
@@ -50,7 +50,7 @@
     /// it must rewrite the code to contain the actual addresses of any
     /// referenced global symbols.
     virtual void relocate(void *Function, MachineRelocation *MR,
-                          unsigned NumRelocs);
+                          unsigned NumRelocs, unsigned char* GOTBase);
   };
 }
 





From alenhar2 at cs.uiuc.edu  Fri Jul 22 15:49:49 2005
From: alenhar2 at cs.uiuc.edu (Andrew Lenharth)
Date: Fri, 22 Jul 2005 15:49:49 -0500
Subject: [llvm-commits] CVS: llvm/lib/Target/SparcV9/SparcV9JITInfo.h
	SparcV9JITInfo.cpp 
Message-ID: <200507222049.PAA03902@zion.cs.uiuc.edu>



Changes in directory llvm/lib/Target/SparcV9:

SparcV9JITInfo.h updated: 1.8 -> 1.9
SparcV9JITInfo.cpp updated: 1.2 -> 1.3
---
Log message:

update interface

---
Diffs of the changes:  (+2 -2)

 SparcV9JITInfo.cpp |    2 +-
 SparcV9JITInfo.h   |    2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)


Index: llvm/lib/Target/SparcV9/SparcV9JITInfo.h
diff -u llvm/lib/Target/SparcV9/SparcV9JITInfo.h:1.8 llvm/lib/Target/SparcV9/SparcV9JITInfo.h:1.9
--- llvm/lib/Target/SparcV9/SparcV9JITInfo.h:1.8	Thu Apr 21 18:25:42 2005
+++ llvm/lib/Target/SparcV9/SparcV9JITInfo.h	Fri Jul 22 15:49:37 2005
@@ -55,7 +55,7 @@
     /// it must rewrite the code to contain the actual addresses of any
     /// referenced global symbols.
     virtual void relocate(void *Function, MachineRelocation *MR,
-                          unsigned NumRelocs);
+                          unsigned NumRelocs, unsigned char* GOTBase);
   };
 }
 


Index: llvm/lib/Target/SparcV9/SparcV9JITInfo.cpp
diff -u llvm/lib/Target/SparcV9/SparcV9JITInfo.cpp:1.2 llvm/lib/Target/SparcV9/SparcV9JITInfo.cpp:1.3
--- llvm/lib/Target/SparcV9/SparcV9JITInfo.cpp:1.2	Thu Apr 21 18:25:42 2005
+++ llvm/lib/Target/SparcV9/SparcV9JITInfo.cpp	Fri Jul 22 15:49:37 2005
@@ -323,7 +323,7 @@
 }
 
 void SparcV9JITInfo::relocate(void *Function, MachineRelocation *MR,
-                              unsigned NumRelocs) {
+                              unsigned NumRelocs, unsigned char* GOTBase) {
   for (unsigned i = 0; i != NumRelocs; ++i, ++MR) {
     unsigned *RelocPos = (unsigned*)Function + MR->getMachineCodeOffset()/4;
     intptr_t ResultPtr = (intptr_t)MR->getResultPointer();





From alenhar2 at cs.uiuc.edu  Fri Jul 22 15:50:40 2005
From: alenhar2 at cs.uiuc.edu (Andrew Lenharth)
Date: Fri, 22 Jul 2005 15:50:40 -0500
Subject: [llvm-commits] CVS: llvm/lib/Target/Alpha/AlphaInstrInfo.td
	AlphaInstrFormats.td AlphaISelPattern.cpp 
Message-ID: <200507222050.PAA03930@zion.cs.uiuc.edu>



Changes in directory llvm/lib/Target/Alpha:

AlphaInstrInfo.td updated: 1.53 -> 1.54
AlphaInstrFormats.td updated: 1.4 -> 1.5
AlphaISelPattern.cpp updated: 1.151 -> 1.152
---
Log message:

simpilfy instruction encoding (and make the lines way shorter, aka Misha happification)

---
Diffs of the changes:  (+281 -223)

 AlphaISelPattern.cpp |   14 -
 AlphaInstrFormats.td |   82 +++++++++-
 AlphaInstrInfo.td    |  408 +++++++++++++++++++++++++--------------------------
 3 files changed, 281 insertions(+), 223 deletions(-)


Index: llvm/lib/Target/Alpha/AlphaInstrInfo.td
diff -u llvm/lib/Target/Alpha/AlphaInstrInfo.td:1.53 llvm/lib/Target/Alpha/AlphaInstrInfo.td:1.54
--- llvm/lib/Target/Alpha/AlphaInstrInfo.td:1.53	Fri Jul  1 14:14:02 2005
+++ llvm/lib/Target/Alpha/AlphaInstrInfo.td	Fri Jul 22 15:50:29 2005
@@ -18,12 +18,6 @@
   // //#define GP    $29
   // //#define SP    $30
 
-def u8imm   : Operand<i8>;
-def s14imm  : Operand<i16>;
-def s16imm  : Operand<i16>;
-def s21imm  : Operand<i32>;
-def s64imm  : Operand<i64>;
-
 def PHI : PseudoInstAlpha<(ops ), "#phi">;
 def IDEF : PseudoInstAlpha<(ops GPRC:$RA), "#idef $RA">;
 def WTF : PseudoInstAlpha<(ops ), "#wtf">;
@@ -41,10 +35,6 @@
 //T0-T7 = R1 - R8
 //T8-T11 = R22-R25
 
-let Defs = [R29] in 
-  let Uses = [R27] in
-    def LDGP : PseudoInstAlpha<(ops), "ldgp $$29, 0($$27)">;
-
 //An even better improvement on the Int = SetCC(FP):  SelectCC!
 //These are evil because they hide control flow in a MBB
 //really the ISel should emit multiple MBB
@@ -74,37 +64,37 @@
 
 let isTwoAddress = 1 in {
 //conditional moves, int
- def CMOVEQ   : OForm<  0x11, 0x24, (ops GPRC:$RDEST, GPRC:$RSRC2, GPRC:$RSRC, GPRC:$RCOND),
+ def CMOVEQ   : OcmForm<  0x11, 0x24, (ops GPRC:$RDEST, GPRC:$RSRC2, GPRC:$RSRC, GPRC:$RCOND),
         "cmoveq $RCOND,$RSRC,$RDEST">; //CMOVE if RCOND =  zero
- def CMOVEQi  : OFormL< 0x11, 0x24, (ops GPRC:$RDEST, GPRC:$RSRC2, u8imm:$L, GPRC:$RCOND),
+ def CMOVEQi  : OcmFormL< 0x11, 0x24, (ops GPRC:$RDEST, GPRC:$RSRC2, u8imm:$L, GPRC:$RCOND),
         "cmoveq $RCOND,$L,$RDEST">; //CMOVE if RCOND =  zero
- def CMOVGE   : OForm<  0x11, 0x46, (ops GPRC:$RDEST, GPRC:$RSRC2, GPRC:$RSRC, GPRC:$RCOND),
+ def CMOVGE   : OcmForm<  0x11, 0x46, (ops GPRC:$RDEST, GPRC:$RSRC2, GPRC:$RSRC, GPRC:$RCOND),
         "cmovge $RCOND,$RSRC,$RDEST">; //CMOVE if RCOND >= zero
- def CMOVGEi  : OFormL< 0x11, 0x46, (ops GPRC:$RDEST, GPRC:$RSRC2, u8imm:$L, GPRC:$RCOND),
+ def CMOVGEi  : OcmFormL< 0x11, 0x46, (ops GPRC:$RDEST, GPRC:$RSRC2, u8imm:$L, GPRC:$RCOND),
         "cmovge $RCOND,$L,$RDEST">; //CMOVE if RCOND >= zero
- def CMOVGT   : OForm<  0x11, 0x66, (ops GPRC:$RDEST, GPRC:$RSRC2, GPRC:$RSRC, GPRC:$RCOND),
+ def CMOVGT   : OcmForm<  0x11, 0x66, (ops GPRC:$RDEST, GPRC:$RSRC2, GPRC:$RSRC, GPRC:$RCOND),
         "cmovgt $RCOND,$RSRC,$RDEST">; //CMOVE if RCOND > zero
- def CMOVGTi  : OFormL< 0x11, 0x66, (ops GPRC:$RDEST, GPRC:$RSRC2, u8imm:$L, GPRC:$RCOND),
+ def CMOVGTi  : OcmFormL< 0x11, 0x66, (ops GPRC:$RDEST, GPRC:$RSRC2, u8imm:$L, GPRC:$RCOND),
         "cmovgt $RCOND,$L,$RDEST">; //CMOVE if RCOND > zero
- def CMOVLBC  : OForm<  0x11, 0x16, (ops GPRC:$RDEST, GPRC:$RSRC2, GPRC:$RSRC, GPRC:$RCOND),
+ def CMOVLBC  : OcmForm<  0x11, 0x16, (ops GPRC:$RDEST, GPRC:$RSRC2, GPRC:$RSRC, GPRC:$RCOND),
         "cmovlbc $RCOND,$RSRC,$RDEST">; //CMOVE if RCOND low bit clear
- def CMOVLBCi : OFormL< 0x11, 0x16, (ops GPRC:$RDEST, GPRC:$RSRC2, u8imm:$L, GPRC:$RCOND),
+ def CMOVLBCi : OcmFormL< 0x11, 0x16, (ops GPRC:$RDEST, GPRC:$RSRC2, u8imm:$L, GPRC:$RCOND),
         "cmovlbc $RCOND,$L,$RDEST">; //CMOVE if RCOND low bit clear
- def CMOVLBS  : OForm<  0x11, 0x14, (ops GPRC:$RDEST, GPRC:$RSRC2, GPRC:$RSRC, GPRC:$RCOND),
+ def CMOVLBS  : OcmForm<  0x11, 0x14, (ops GPRC:$RDEST, GPRC:$RSRC2, GPRC:$RSRC, GPRC:$RCOND),
         "cmovlbs $RCOND,$RSRC,$RDEST">; //CMOVE if RCOND low bit set
- def CMOVLBSi : OFormL< 0x11, 0x14, (ops GPRC:$RDEST, GPRC:$RSRC2, u8imm:$L, GPRC:$RCOND),
+ def CMOVLBSi : OcmFormL< 0x11, 0x14, (ops GPRC:$RDEST, GPRC:$RSRC2, u8imm:$L, GPRC:$RCOND),
         "cmovlbs $RCOND,$L,$RDEST">; //CMOVE if RCOND low bit set
- def CMOVLE   : OForm<  0x11, 0x64, (ops GPRC:$RDEST, GPRC:$RSRC2, GPRC:$RSRC, GPRC:$RCOND),
+ def CMOVLE   : OcmForm<  0x11, 0x64, (ops GPRC:$RDEST, GPRC:$RSRC2, GPRC:$RSRC, GPRC:$RCOND),
         "cmovle $RCOND,$RSRC,$RDEST">; //CMOVE if RCOND <= zero
- def CMOVLEi  : OFormL< 0x11, 0x64, (ops GPRC:$RDEST, GPRC:$RSRC2, u8imm:$L, GPRC:$RCOND),
+ def CMOVLEi  : OcmFormL< 0x11, 0x64, (ops GPRC:$RDEST, GPRC:$RSRC2, u8imm:$L, GPRC:$RCOND),
         "cmovle $RCOND,$L,$RDEST">; //CMOVE if RCOND <= zero
- def CMOVLT   : OForm<  0x11, 0x44, (ops GPRC:$RDEST, GPRC:$RSRC2, GPRC:$RSRC, GPRC:$RCOND),
+ def CMOVLT   : OcmForm<  0x11, 0x44, (ops GPRC:$RDEST, GPRC:$RSRC2, GPRC:$RSRC, GPRC:$RCOND),
         "cmovlt $RCOND,$RSRC,$RDEST">; //CMOVE if RCOND < zero
- def CMOVLTi  : OFormL< 0x11, 0x44, (ops GPRC:$RDEST, GPRC:$RSRC2, u8imm:$L, GPRC:$RCOND),
+ def CMOVLTi  : OcmFormL< 0x11, 0x44, (ops GPRC:$RDEST, GPRC:$RSRC2, u8imm:$L, GPRC:$RCOND),
         "cmovlt $RCOND,$L,$RDEST">; //CMOVE if RCOND < zero
- def CMOVNE   : OForm<  0x11, 0x26, (ops GPRC:$RDEST, GPRC:$RSRC2, GPRC:$RSRC, GPRC:$RCOND),
+ def CMOVNE   : OcmForm<  0x11, 0x26, (ops GPRC:$RDEST, GPRC:$RSRC2, GPRC:$RSRC, GPRC:$RCOND),
         "cmovne $RCOND,$RSRC,$RDEST">; //CMOVE if RCOND != zero
- def CMOVNEi  : OFormL< 0x11, 0x26, (ops GPRC:$RDEST, GPRC:$RSRC2, u8imm:$L, GPRC:$RCOND),
+ def CMOVNEi  : OcmFormL< 0x11, 0x26, (ops GPRC:$RDEST, GPRC:$RSRC2, u8imm:$L, GPRC:$RCOND),
         "cmovne $RCOND,$L,$RDEST">; //CMOVE if RCOND != zero
 
 //conditional moves, fp
@@ -122,126 +112,124 @@
         "fcmovne $RCOND,$RSRC,$RDEST">; //FCMOVE if != zero
 }
 
-def ADDL     : OForm< 0x10, 0x00, (ops GPRC:$RC, GPRC:$RA, GPRC:$RB), "addl $RA,$RB,$RC">; //Add longword
-def ADDLi    : OFormL<0x10, 0x00, (ops GPRC:$RC, GPRC:$RA, u8imm:$L), "addl $RA,$L,$RC">; //Add longword
-def ADDQ     : OForm< 0x10, 0x20, (ops GPRC:$RC, GPRC:$RA, GPRC:$RB), "addq $RA,$RB,$RC">; //Add quadword
-def ADDQi    : OFormL<0x10, 0x20, (ops GPRC:$RC, GPRC:$RA, u8imm:$L), "addq $RA,$L,$RC">; //Add quadword
-def AMASK    : OForm< 0x11, 0x61, (ops GPRC:$RC, GPRC:$RA, GPRC:$RB), "AMASK $RA,$RB,$RC">; //Architecture mask
-def AMASKi   : OFormL<0x11, 0x61, (ops GPRC:$RC, GPRC:$RA, u8imm:$L), "AMASK $RA,$L,$RC">; //Architecture mask
-def AND      : OForm< 0x11, 0x00, (ops GPRC:$RC, GPRC:$RA, GPRC:$RB), "and $RA,$RB,$RC">; //Logical product
-def ANDi     : OFormL<0x11, 0x00, (ops GPRC:$RC, GPRC:$RA, u8imm:$L), "and $RA,$L,$RC">; //Logical product
-def BIC      : OForm< 0x11, 0x08, (ops GPRC:$RC, GPRC:$RA, GPRC:$RB), "bic $RA,$RB,$RC">; //Bit clear
-def BICi     : OFormL<0x11, 0x08, (ops GPRC:$RC, GPRC:$RA, u8imm:$L), "bic $RA,$L,$RC">; //Bit clear
-def BIS      : OForm< 0x11, 0x20, (ops GPRC:$RC, GPRC:$RA, GPRC:$RB), "bis $RA,$RB,$RC">; //Logical sum
-def BISi     : OFormL<0x11, 0x20, (ops GPRC:$RC, GPRC:$RA, u8imm:$L), "bis $RA,$L,$RC">; //Logical sum
-def CTLZ     : OForm< 0x1C, 0x32, (ops GPRC:$RC, GPRC:$RB), "CTLZ $RB,$RC">; //Count leading zero
-def CTPOP    : OForm< 0x1C, 0x30, (ops GPRC:$RC, GPRC:$RB), "CTPOP $RB,$RC">; //Count population
-def CTTZ     : OForm< 0x1C, 0x33, (ops GPRC:$RC, GPRC:$RB), "CTTZ $RB,$RC">; //Count trailing zero
-def EQV      : OForm< 0x11, 0x48, (ops GPRC:$RC, GPRC:$RA, GPRC:$RB), "eqv $RA,$RB,$RC">; //Logical equivalence
-def EQVi     : OFormL<0x11, 0x48, (ops GPRC:$RC, GPRC:$RA, u8imm:$L), "eqv $RA,$L,$RC">; //Logical equivalence
-def EXTBL    : OForm< 0x12, 0x06, (ops GPRC:$RC, GPRC:$RA, GPRC:$RB), "EXTBL $RA,$RB,$RC">; //Extract byte low
-def EXTBLi   : OFormL<0x12, 0x06, (ops GPRC:$RC, GPRC:$RA, u8imm:$L), "EXTBL $RA,$L,$RC">; //Extract byte low
-def EXTLH    : OForm< 0x12, 0x6A, (ops GPRC:$RC, GPRC:$RA, GPRC:$RB), "EXTLH $RA,$RB,$RC">; //Extract longword high
-def EXTLHi   : OFormL<0x12, 0x6A, (ops GPRC:$RC, GPRC:$RA, u8imm:$L), "EXTLH $RA,$L,$RC">; //Extract longword high
-def EXTLL    : OForm< 0x12, 0x26, (ops GPRC:$RC, GPRC:$RA, GPRC:$RB), "EXTLL $RA,$RB,$RC">; //Extract longword low
-def EXTLLi   : OFormL<0x12, 0x26, (ops GPRC:$RC, GPRC:$RA, u8imm:$L), "EXTLL $RA,$L,$RC">; //Extract longword low
-def EXTQH    : OForm< 0x12, 0x7A, (ops GPRC:$RC, GPRC:$RA, GPRC:$RB), "EXTQH $RA,$RB,$RC">; //Extract quadword high
-def EXTQHi   : OFormL<0x12, 0x7A, (ops GPRC:$RC, GPRC:$RA, u8imm:$L), "EXTQH $RA,$L,$RC">; //Extract quadword high
-def EXTQ     : OForm< 0x12, 0x36, (ops GPRC:$RC, GPRC:$RA, GPRC:$RB), "EXTQ $RA,$RB,$RC">; //Extract quadword low
-def EXTQi    : OFormL<0x12, 0x36, (ops GPRC:$RC, GPRC:$RA, u8imm:$L), "EXTQ $RA,$L,$RC">; //Extract quadword low
-def EXTWH    : OForm< 0x12, 0x5A, (ops GPRC:$RC, GPRC:$RA, GPRC:$RB), "EXTWH $RA,$RB,$RC">; //Extract word high
-def EXTWHi   : OFormL<0x12, 0x5A, (ops GPRC:$RC, GPRC:$RA, u8imm:$L), "EXTWH $RA,$L,$RC">; //Extract word high
-def EXTWL    : OForm< 0x12, 0x16, (ops GPRC:$RC, GPRC:$RA, GPRC:$RB), "EXTWL $RA,$RB,$RC">; //Extract word low
-def EXTWLi   : OFormL<0x12, 0x16, (ops GPRC:$RC, GPRC:$RA, u8imm:$L), "EXTWL $RA,$L,$RC">; //Extract word low
-def IMPLVER  : OForm< 0x11, 0x6C, (ops GPRC:$RC, GPRC:$RA, GPRC:$RB), "IMPLVER $RA,$RB,$RC">; //Implementation version
-def IMPLVERi : OFormL<0x11, 0x6C, (ops GPRC:$RC, GPRC:$RA, u8imm:$L), "IMPLVER $RA,$L,$RC">; //Implementation version
-def INSBL    : OForm< 0x12, 0x0B, (ops GPRC:$RC, GPRC:$RA, GPRC:$RB), "INSBL $RA,$RB,$RC">; //Insert byte low
-def INSBLi   : OFormL<0x12, 0x0B, (ops GPRC:$RC, GPRC:$RA, u8imm:$L), "INSBL $RA,$L,$RC">; //Insert byte low
-def INSLH    : OForm< 0x12, 0x67, (ops GPRC:$RC, GPRC:$RA, GPRC:$RB), "INSLH $RA,$RB,$RC">; //Insert longword high
-def INSLHi   : OFormL<0x12, 0x67, (ops GPRC:$RC, GPRC:$RA, u8imm:$L), "INSLH $RA,$L,$RC">; //Insert longword high
-def INSLL    : OForm< 0x12, 0x2B, (ops GPRC:$RC, GPRC:$RA, GPRC:$RB), "INSLL $RA,$RB,$RC">; //Insert longword low
-def INSLLi   : OFormL<0x12, 0x2B, (ops GPRC:$RC, GPRC:$RA, u8imm:$L), "INSLL $RA,$L,$RC">; //Insert longword low
-def INSQH    : OForm< 0x12, 0x77, (ops GPRC:$RC, GPRC:$RA, GPRC:$RB), "INSQH $RA,$RB,$RC">; //Insert quadword high
-def INSQHi   : OFormL<0x12, 0x77, (ops GPRC:$RC, GPRC:$RA, u8imm:$L), "INSQH $RA,$L,$RC">; //Insert quadword high
-def INSQL    : OForm< 0x12, 0x3B, (ops GPRC:$RC, GPRC:$RA, GPRC:$RB), "INSQL $RA,$RB,$RC">; //Insert quadword low
-def INSQLi   : OFormL<0x12, 0x3B, (ops GPRC:$RC, GPRC:$RA, u8imm:$L), "INSQL $RA,$L,$RC">; //Insert quadword low
-def INSWH    : OForm< 0x12, 0x57, (ops GPRC:$RC, GPRC:$RA, GPRC:$RB), "INSWH $RA,$RB,$RC">; //Insert word high
-def INSWHi   : OFormL<0x12, 0x57, (ops GPRC:$RC, GPRC:$RA, u8imm:$L), "INSWH $RA,$L,$RC">; //Insert word high
-def INSWL    : OForm< 0x12, 0x1B, (ops GPRC:$RC, GPRC:$RA, GPRC:$RB), "INSWL $RA,$RB,$RC">; //Insert word low
-def INSWLi   : OFormL<0x12, 0x1B, (ops GPRC:$RC, GPRC:$RA, u8imm:$L), "INSWL $RA,$L,$RC">; //Insert word low
-def MSKBL    : OForm< 0x12, 0x02, (ops GPRC:$RC, GPRC:$RA, GPRC:$RB), "MSKBL $RA,$RB,$RC">; //Mask byte low
-def MSKBLi   : OFormL<0x12, 0x02, (ops GPRC:$RC, GPRC:$RA, u8imm:$L), "MSKBL $RA,$L,$RC">; //Mask byte low
-def MSKLH    : OForm< 0x12, 0x62, (ops GPRC:$RC, GPRC:$RA, GPRC:$RB), "MSKLH $RA,$RB,$RC">; //Mask longword high
-def MSKLHi   : OFormL<0x12, 0x62, (ops GPRC:$RC, GPRC:$RA, u8imm:$L), "MSKLH $RA,$L,$RC">; //Mask longword high
-def MSKLL    : OForm< 0x12, 0x22, (ops GPRC:$RC, GPRC:$RA, GPRC:$RB), "MSKLL $RA,$RB,$RC">; //Mask longword low
-def MSKLLi   : OFormL<0x12, 0x22, (ops GPRC:$RC, GPRC:$RA, u8imm:$L), "MSKLL $RA,$L,$RC">; //Mask longword low
-def MSKQH    : OForm< 0x12, 0x72, (ops GPRC:$RC, GPRC:$RA, GPRC:$RB), "MSKQH $RA,$RB,$RC">; //Mask quadword high
-def MSKQHi   : OFormL<0x12, 0x72, (ops GPRC:$RC, GPRC:$RA, u8imm:$L), "MSKQH $RA,$L,$RC">; //Mask quadword high
-def MSKQL    : OForm< 0x12, 0x32, (ops GPRC:$RC, GPRC:$RA, GPRC:$RB), "MSKQL $RA,$RB,$RC">; //Mask quadword low
-def MSKQLi   : OFormL<0x12, 0x32, (ops GPRC:$RC, GPRC:$RA, u8imm:$L), "MSKQL $RA,$L,$RC">; //Mask quadword low
-def MSKWH    : OForm< 0x12, 0x52, (ops GPRC:$RC, GPRC:$RA, GPRC:$RB), "MSKWH $RA,$RB,$RC">; //Mask word high
-def MSKWHi   : OFormL<0x12, 0x52, (ops GPRC:$RC, GPRC:$RA, u8imm:$L), "MSKWH $RA,$L,$RC">; //Mask word high
-def MSKWL    : OForm< 0x12, 0x12, (ops GPRC:$RC, GPRC:$RA, GPRC:$RB), "MSKWL $RA,$RB,$RC">; //Mask word low
-def MSKWLi   : OFormL<0x12, 0x12, (ops GPRC:$RC, GPRC:$RA, u8imm:$L), "MSKWL $RA,$L,$RC">; //Mask word low
-def MULL     : OForm< 0x13, 0x00, (ops GPRC:$RC, GPRC:$RA, GPRC:$RB), "mull $RA,$RB,$RC">; //Multiply longword
-def MULLi    : OFormL<0x13, 0x00, (ops GPRC:$RC, GPRC:$RA, u8imm:$L), "mull $RA,$L,$RC">; //Multiply longword
-def MULQ     : OForm< 0x13, 0x20, (ops GPRC:$RC, GPRC:$RA, GPRC:$RB), "mulq $RA,$RB,$RC">; //Multiply quadword
-def MULQi    : OFormL<0x13, 0x20, (ops GPRC:$RC, GPRC:$RA, u8imm:$L), "mulq $RA,$L,$RC">; //Multiply quadword
-def ORNOT    : OForm< 0x11, 0x28, (ops GPRC:$RC, GPRC:$RA, GPRC:$RB), "ornot $RA,$RB,$RC">; //Logical sum with complement
-def ORNOTi   : OFormL<0x11, 0x28, (ops GPRC:$RC, GPRC:$RA, u8imm:$L), "ornot $RA,$L,$RC">; //Logical sum with complement
-def S4ADDL   : OForm< 0x10, 0x02, (ops GPRC:$RC, GPRC:$RA, GPRC:$RB), "s4addl $RA,$RB,$RC">; //Scaled add longword by 4
-def S4ADDLi  : OFormL<0x10, 0x02, (ops GPRC:$RC, GPRC:$RA, u8imm:$L), "s4addl $RA,$L,$RC">; //Scaled add longword by 4
-def S4ADDQ   : OForm< 0x10, 0x22, (ops GPRC:$RC, GPRC:$RA, GPRC:$RB), "s4addq $RA,$RB,$RC">; //Scaled add quadword by 4
-def S4ADDQi  : OFormL<0x10, 0x22, (ops GPRC:$RC, GPRC:$RA, u8imm:$L), "s4addq $RA,$L,$RC">; //Scaled add quadword by 4
-def S4SUBL   : OForm< 0x10, 0x0B, (ops GPRC:$RC, GPRC:$RA, GPRC:$RB), "s4subl $RA,$RB,$RC">; //Scaled subtract longword by 4
-def S4SUBLi  : OFormL<0x10, 0x0B, (ops GPRC:$RC, GPRC:$RA, u8imm:$L), "s4subl $RA,$L,$RC">; //Scaled subtract longword by 4
-def S4SUBQ   : OForm< 0x10, 0x2B, (ops GPRC:$RC, GPRC:$RA, GPRC:$RB), "s4subq $RA,$RB,$RC">; //Scaled subtract quadword by 4
-def S4SUBQi  : OFormL<0x10, 0x2B, (ops GPRC:$RC, GPRC:$RA, u8imm:$L), "s4subq $RA,$L,$RC">; //Scaled subtract quadword by 4
-def S8ADDL   : OForm< 0x10, 0x12, (ops GPRC:$RC, GPRC:$RA, GPRC:$RB), "s8addl $RA,$RB,$RC">; //Scaled add longword by 8
-def S8ADDLi  : OFormL<0x10, 0x12, (ops GPRC:$RC, GPRC:$RA, u8imm:$L), "s8addl $RA,$L,$RC">; //Scaled add longword by 8
-def S8ADDQ   : OForm< 0x10, 0x32, (ops GPRC:$RC, GPRC:$RA, GPRC:$RB), "s8addq $RA,$RB,$RC">; //Scaled add quadword by 8
-def S8ADDQi  : OFormL<0x10, 0x32, (ops GPRC:$RC, GPRC:$RA, u8imm:$L), "s8addq $RA,$L,$RC">; //Scaled add quadword by 8
-def S8SUBL   : OForm< 0x10, 0x1B, (ops GPRC:$RC, GPRC:$RA, GPRC:$RB), "s8subl $RA,$RB,$RC">; //Scaled subtract longword by 8
-def S8SUBLi  : OFormL<0x10, 0x1B, (ops GPRC:$RC, GPRC:$RA, u8imm:$L), "s8subl $RA,$L,$RC">; //Scaled subtract longword by 8
-def S8SUBQ   : OForm< 0x10, 0x3B, (ops GPRC:$RC, GPRC:$RA, GPRC:$RB), "s8subq $RA,$RB,$RC">; //Scaled subtract quadword by 8
-def S8SUBQi  : OFormL<0x10, 0x3B, (ops GPRC:$RC, GPRC:$RA, u8imm:$L), "s8subq $RA,$L,$RC">; //Scaled subtract quadword by 8
-def SEXTB    : OForm< 0x1C, 0x00, (ops GPRC:$RC, GPRC:$RB), "sextb $RB,$RC">; //Sign extend byte
-def SEXTBi   : OFormL<0x1C, 0x00, (ops GPRC:$RC, u8imm:$L), "sextb $L,$RC">; //Sign extend byte
-def SEXTW    : OForm< 0x1C, 0x01, (ops GPRC:$RC, GPRC:$RB), "sextw $RB,$RC">; //Sign extend word
-def SEXTWi   : OFormL<0x1C, 0x01, (ops GPRC:$RC, u8imm:$L), "sextw $L,$RC">; //Sign extend word
-def SL       : OForm< 0x12, 0x39, (ops GPRC:$RC, GPRC:$RA, GPRC:$RB), "sll $RA,$RB,$RC">; //Shift left logical
-def SLi      : OFormL<0x12, 0x39, (ops GPRC:$RC, GPRC:$RA, u8imm:$L), "sll $RA,$L,$RC">; //Shift left logical
-def SRA      : OForm< 0x12, 0x3C, (ops GPRC:$RC, GPRC:$RA, GPRC:$RB), "sra $RA,$RB,$RC">; //Shift right arithmetic
-def SRAi     : OFormL<0x12, 0x3C, (ops GPRC:$RC, GPRC:$RA, u8imm:$L), "sra $RA,$L,$RC">; //Shift right arithmetic
-def SRL      : OForm< 0x12, 0x34, (ops GPRC:$RC, GPRC:$RA, GPRC:$RB), "srl $RA,$RB,$RC">; //Shift right logical
-
-def SRLi     : OFormL<0x12, 0x34, (ops GPRC:$RC, GPRC:$RA, u8imm:$L), "srl $RA,$L,$RC">; //Shift right logical
-def SUBL     : OForm< 0x10, 0x09, (ops GPRC:$RC, GPRC:$RA, GPRC:$RB), "subl $RA,$RB,$RC">; //Subtract longword
-def SUBLi    : OFormL<0x10, 0x09, (ops GPRC:$RC, GPRC:$RA, u8imm:$L), "subl $RA,$L,$RC">; //Subtract longword
-def SUBQ     : OForm< 0x10, 0x29, (ops GPRC:$RC, GPRC:$RA, GPRC:$RB), "subq $RA,$RB,$RC">; //Subtract quadword
-def SUBQi    : OFormL<0x10, 0x29, (ops GPRC:$RC, GPRC:$RA, u8imm:$L), "subq $RA,$L,$RC">; //Subtract quadword
-def UMULH    : OForm< 0x13, 0x30, (ops GPRC:$RC, GPRC:$RA, GPRC:$RB), "umulh $RA,$RB,$RC">; //Unsigned multiply quadword high
-def UMULHi   : OFormL<0x13, 0x30, (ops GPRC:$RC, GPRC:$RA, u8imm:$L), "umulh $RA,$L,$RC">; //Unsigned multiply quadword high
-def XOR      : OForm< 0x11, 0x40, (ops GPRC:$RC, GPRC:$RA, GPRC:$RB), "xor $RA,$RB,$RC">; //Logical difference
-def XORi     : OFormL<0x11, 0x40, (ops GPRC:$RC, GPRC:$RA, u8imm:$L), "xor $RA,$L,$RC">; //Logical difference
-def ZAP      : OForm< 0x12, 0x30, (ops GPRC:$RC, GPRC:$RA, GPRC:$RB), "zap $RA,$RB,$RC">; //Zero bytes
-def ZAPi     : OFormL<0x12, 0x30, (ops GPRC:$RC, GPRC:$RA, u8imm:$L), "zap $RA,$L,$RC">; //Zero bytes
-def ZAPNOT   : OForm< 0x12, 0x31, (ops GPRC:$RC, GPRC:$RA, GPRC:$RB), "zapnot $RA,$RB,$RC">; //Zero bytes not
-def ZAPNOTi  : OFormL<0x12, 0x31, (ops GPRC:$RC, GPRC:$RA, u8imm:$L), "zapnot $RA,$L,$RC">; //Zero bytes not
+def ADDL     : OForm< 0x10, 0x00, "addl $RA,$RB,$RC">; //Add longword
+def ADDLi    : OFormL<0x10, 0x00, "addl $RA,$L,$RC">; //Add longword
+def ADDQ     : OForm< 0x10, 0x20, "addq $RA,$RB,$RC">; //Add quadword
+def ADDQi    : OFormL<0x10, 0x20, "addq $RA,$L,$RC">; //Add quadword
+def AMASK    : OForm< 0x11, 0x61, "AMASK $RA,$RB,$RC">; //Architecture mask
+def AMASKi   : OFormL<0x11, 0x61, "AMASK $RA,$L,$RC">; //Architecture mask
+def AND      : OForm< 0x11, 0x00, "and $RA,$RB,$RC">; //Logical product
+def ANDi     : OFormL<0x11, 0x00, "and $RA,$L,$RC">; //Logical product
+def BIC      : OForm< 0x11, 0x08, "bic $RA,$RB,$RC">; //Bit clear
+def BICi     : OFormL<0x11, 0x08, "bic $RA,$L,$RC">; //Bit clear
+def BIS      : OForm< 0x11, 0x20, "bis $RA,$RB,$RC">; //Logical sum
+def BISi     : OFormL<0x11, 0x20, "bis $RA,$L,$RC">; //Logical sum
+def CTLZ     : OForm< 0x1C, 0x32, "CTLZ $RB,$RC">; //Count leading zero
+def CTPOP    : OForm< 0x1C, 0x30, "CTPOP $RB,$RC">; //Count population
+def CTTZ     : OForm< 0x1C, 0x33, "CTTZ $RB,$RC">; //Count trailing zero
+def EQV      : OForm< 0x11, 0x48, "eqv $RA,$RB,$RC">; //Logical equivalence
+def EQVi     : OFormL<0x11, 0x48, "eqv $RA,$L,$RC">; //Logical equivalence
+def EXTBL    : OForm< 0x12, 0x06, "EXTBL $RA,$RB,$RC">; //Extract byte low
+def EXTBLi   : OFormL<0x12, 0x06, "EXTBL $RA,$L,$RC">; //Extract byte low
+def EXTLH    : OForm< 0x12, 0x6A, "EXTLH $RA,$RB,$RC">; //Extract longword high
+def EXTLHi   : OFormL<0x12, 0x6A, "EXTLH $RA,$L,$RC">; //Extract longword high
+def EXTLL    : OForm< 0x12, 0x26, "EXTLL $RA,$RB,$RC">; //Extract longword low
+def EXTLLi   : OFormL<0x12, 0x26, "EXTLL $RA,$L,$RC">; //Extract longword low
+def EXTQH    : OForm< 0x12, 0x7A, "EXTQH $RA,$RB,$RC">; //Extract quadword high
+def EXTQHi   : OFormL<0x12, 0x7A, "EXTQH $RA,$L,$RC">; //Extract quadword high
+def EXTQ     : OForm< 0x12, 0x36, "EXTQ $RA,$RB,$RC">; //Extract quadword low
+def EXTQi    : OFormL<0x12, 0x36, "EXTQ $RA,$L,$RC">; //Extract quadword low
+def EXTWH    : OForm< 0x12, 0x5A, "EXTWH $RA,$RB,$RC">; //Extract word high
+def EXTWHi   : OFormL<0x12, 0x5A, "EXTWH $RA,$L,$RC">; //Extract word high
+def EXTWL    : OForm< 0x12, 0x16, "EXTWL $RA,$RB,$RC">; //Extract word low
+def EXTWLi   : OFormL<0x12, 0x16, "EXTWL $RA,$L,$RC">; //Extract word low
+def IMPLVER  : OForm< 0x11, 0x6C, "IMPLVER $RA,$RB,$RC">; //Implementation version
+def IMPLVERi : OFormL<0x11, 0x6C, "IMPLVER $RA,$L,$RC">; //Implementation version
+def INSBL    : OForm< 0x12, 0x0B, "INSBL $RA,$RB,$RC">; //Insert byte low
+def INSBLi   : OFormL<0x12, 0x0B, "INSBL $RA,$L,$RC">; //Insert byte low
+def INSLH    : OForm< 0x12, 0x67, "INSLH $RA,$RB,$RC">; //Insert longword high
+def INSLHi   : OFormL<0x12, 0x67, "INSLH $RA,$L,$RC">; //Insert longword high
+def INSLL    : OForm< 0x12, 0x2B, "INSLL $RA,$RB,$RC">; //Insert longword low
+def INSLLi   : OFormL<0x12, 0x2B, "INSLL $RA,$L,$RC">; //Insert longword low
+def INSQH    : OForm< 0x12, 0x77, "INSQH $RA,$RB,$RC">; //Insert quadword high
+def INSQHi   : OFormL<0x12, 0x77, "INSQH $RA,$L,$RC">; //Insert quadword high
+def INSQL    : OForm< 0x12, 0x3B, "INSQL $RA,$RB,$RC">; //Insert quadword low
+def INSQLi   : OFormL<0x12, 0x3B, "INSQL $RA,$L,$RC">; //Insert quadword low
+def INSWH    : OForm< 0x12, 0x57, "INSWH $RA,$RB,$RC">; //Insert word high
+def INSWHi   : OFormL<0x12, 0x57, "INSWH $RA,$L,$RC">; //Insert word high
+def INSWL    : OForm< 0x12, 0x1B, "INSWL $RA,$RB,$RC">; //Insert word low
+def INSWLi   : OFormL<0x12, 0x1B, "INSWL $RA,$L,$RC">; //Insert word low
+def MSKBL    : OForm< 0x12, 0x02, "MSKBL $RA,$RB,$RC">; //Mask byte low
+def MSKBLi   : OFormL<0x12, 0x02, "MSKBL $RA,$L,$RC">; //Mask byte low
+def MSKLH    : OForm< 0x12, 0x62, "MSKLH $RA,$RB,$RC">; //Mask longword high
+def MSKLHi   : OFormL<0x12, 0x62, "MSKLH $RA,$L,$RC">; //Mask longword high
+def MSKLL    : OForm< 0x12, 0x22, "MSKLL $RA,$RB,$RC">; //Mask longword low
+def MSKLLi   : OFormL<0x12, 0x22, "MSKLL $RA,$L,$RC">; //Mask longword low
+def MSKQH    : OForm< 0x12, 0x72, "MSKQH $RA,$RB,$RC">; //Mask quadword high
+def MSKQHi   : OFormL<0x12, 0x72, "MSKQH $RA,$L,$RC">; //Mask quadword high
+def MSKQL    : OForm< 0x12, 0x32, "MSKQL $RA,$RB,$RC">; //Mask quadword low
+def MSKQLi   : OFormL<0x12, 0x32, "MSKQL $RA,$L,$RC">; //Mask quadword low
+def MSKWH    : OForm< 0x12, 0x52, "MSKWH $RA,$RB,$RC">; //Mask word high
+def MSKWHi   : OFormL<0x12, 0x52, "MSKWH $RA,$L,$RC">; //Mask word high
+def MSKWL    : OForm< 0x12, 0x12, "MSKWL $RA,$RB,$RC">; //Mask word low
+def MSKWLi   : OFormL<0x12, 0x12, "MSKWL $RA,$L,$RC">; //Mask word low
+def MULL     : OForm< 0x13, 0x00, "mull $RA,$RB,$RC">; //Multiply longword
+def MULLi    : OFormL<0x13, 0x00, "mull $RA,$L,$RC">; //Multiply longword
+def MULQ     : OForm< 0x13, 0x20, "mulq $RA,$RB,$RC">; //Multiply quadword
+def MULQi    : OFormL<0x13, 0x20, "mulq $RA,$L,$RC">; //Multiply quadword
+def ORNOT    : OForm< 0x11, 0x28, "ornot $RA,$RB,$RC">; //Logical sum with complement
+def ORNOTi   : OFormL<0x11, 0x28, "ornot $RA,$L,$RC">; //Logical sum with complement
+def S4ADDL   : OForm< 0x10, 0x02, "s4addl $RA,$RB,$RC">; //Scaled add longword by 4
+def S4ADDLi  : OFormL<0x10, 0x02, "s4addl $RA,$L,$RC">; //Scaled add longword by 4
+def S4ADDQ   : OForm< 0x10, 0x22, "s4addq $RA,$RB,$RC">; //Scaled add quadword by 4
+def S4ADDQi  : OFormL<0x10, 0x22, "s4addq $RA,$L,$RC">; //Scaled add quadword by 4
+def S4SUBL   : OForm< 0x10, 0x0B, "s4subl $RA,$RB,$RC">; //Scaled subtract longword by 4
+def S4SUBLi  : OFormL<0x10, 0x0B, "s4subl $RA,$L,$RC">; //Scaled subtract longword by 4
+def S4SUBQ   : OForm< 0x10, 0x2B, "s4subq $RA,$RB,$RC">; //Scaled subtract quadword by 4
+def S4SUBQi  : OFormL<0x10, 0x2B, "s4subq $RA,$L,$RC">; //Scaled subtract quadword by 4
+def S8ADDL   : OForm< 0x10, 0x12, "s8addl $RA,$RB,$RC">; //Scaled add longword by 8
+def S8ADDLi  : OFormL<0x10, 0x12, "s8addl $RA,$L,$RC">; //Scaled add longword by 8
+def S8ADDQ   : OForm< 0x10, 0x32, "s8addq $RA,$RB,$RC">; //Scaled add quadword by 8
+def S8ADDQi  : OFormL<0x10, 0x32, "s8addq $RA,$L,$RC">; //Scaled add quadword by 8
+def S8SUBL   : OForm< 0x10, 0x1B, "s8subl $RA,$RB,$RC">; //Scaled subtract longword by 8
+def S8SUBLi  : OFormL<0x10, 0x1B, "s8subl $RA,$L,$RC">; //Scaled subtract longword by 8
+def S8SUBQ   : OForm< 0x10, 0x3B, "s8subq $RA,$RB,$RC">; //Scaled subtract quadword by 8
+def S8SUBQi  : OFormL<0x10, 0x3B, "s8subq $RA,$L,$RC">; //Scaled subtract quadword by 8
+def SEXTB    : OForm< 0x1C, 0x00, "sextb $RB,$RC">; //Sign extend byte
+def SEXTW    : OForm< 0x1C, 0x01, "sextw $RB,$RC">; //Sign extend word
+def SL       : OForm< 0x12, 0x39, "sll $RA,$RB,$RC">; //Shift left logical
+def SLi      : OFormL<0x12, 0x39, "sll $RA,$L,$RC">; //Shift left logical
+def SRA      : OForm< 0x12, 0x3C, "sra $RA,$RB,$RC">; //Shift right arithmetic
+def SRAi     : OFormL<0x12, 0x3C, "sra $RA,$L,$RC">; //Shift right arithmetic
+def SRL      : OForm< 0x12, 0x34, "srl $RA,$RB,$RC">; //Shift right logical
+
+def SRLi     : OFormL<0x12, 0x34, "srl $RA,$L,$RC">; //Shift right logical
+def SUBL     : OForm< 0x10, 0x09, "subl $RA,$RB,$RC">; //Subtract longword
+def SUBLi    : OFormL<0x10, 0x09, "subl $RA,$L,$RC">; //Subtract longword
+def SUBQ     : OForm< 0x10, 0x29, "subq $RA,$RB,$RC">; //Subtract quadword
+def SUBQi    : OFormL<0x10, 0x29, "subq $RA,$L,$RC">; //Subtract quadword
+def UMULH    : OForm< 0x13, 0x30, "umulh $RA,$RB,$RC">; //Unsigned multiply quadword high
+def UMULHi   : OFormL<0x13, 0x30, "umulh $RA,$L,$RC">; //Unsigned multiply quadword high
+def XOR      : OForm< 0x11, 0x40, "xor $RA,$RB,$RC">; //Logical difference
+def XORi     : OFormL<0x11, 0x40, "xor $RA,$L,$RC">; //Logical difference
+def ZAP      : OForm< 0x12, 0x30, "zap $RA,$RB,$RC">; //Zero bytes
+def ZAPi     : OFormL<0x12, 0x30, "zap $RA,$L,$RC">; //Zero bytes
+def ZAPNOT   : OForm< 0x12, 0x31, "zapnot $RA,$RB,$RC">; //Zero bytes not
+def ZAPNOTi  : OFormL<0x12, 0x31, "zapnot $RA,$L,$RC">; //Zero bytes not
 
 //Comparison, int
-def CMPBGE   : OForm< 0x10, 0x0F, (ops GPRC:$RC, GPRC:$RA, GPRC:$RB), "cmpbge $RA,$RB,$RC">; //Compare byte
-def CMPBGEi  : OFormL<0x10, 0x0F, (ops GPRC:$RC, GPRC:$RA, u8imm:$L), "cmpbge $RA,$L,$RC">; //Compare byte
-def CMPEQ    : OForm< 0x10, 0x2D, (ops GPRC:$RC, GPRC:$RA, GPRC:$RB), "cmpeq $RA,$RB,$RC">; //Compare signed quadword equal
-def CMPEQi   : OFormL<0x10, 0x2D, (ops GPRC:$RC, GPRC:$RA, u8imm:$L), "cmpeq $RA,$L,$RC">; //Compare signed quadword equal
-def CMPLE    : OForm< 0x10, 0x6D, (ops GPRC:$RC, GPRC:$RA, GPRC:$RB), "cmple $RA,$RB,$RC">; //Compare signed quadword less than or equal
-def CMPLEi   : OFormL<0x10, 0x6D, (ops GPRC:$RC, GPRC:$RA, u8imm:$L), "cmple $RA,$L,$RC">; //Compare signed quadword less than or equal
-def CMPLT    : OForm< 0x10, 0x4D, (ops GPRC:$RC, GPRC:$RA, GPRC:$RB), "cmplt $RA,$RB,$RC">; //Compare signed quadword less than
-def CMPLTi   : OFormL<0x10, 0x4D, (ops GPRC:$RC, GPRC:$RA, u8imm:$L), "cmplt $RA,$L,$RC">; //Compare signed quadword less than
-def CMPULE   : OForm< 0x10, 0x3D, (ops GPRC:$RC, GPRC:$RA, GPRC:$RB), "cmpule $RA,$RB,$RC">; //Compare unsigned quadword less than or equal
-def CMPULEi  : OFormL<0x10, 0x3D, (ops GPRC:$RC, GPRC:$RA, u8imm:$L), "cmpule $RA,$L,$RC">; //Compare unsigned quadword less than or equal
-def CMPULT   : OForm< 0x10, 0x1D, (ops GPRC:$RC, GPRC:$RA, GPRC:$RB), "cmpult $RA,$RB,$RC">; //Compare unsigned quadword less than
-def CMPULTi  : OFormL<0x10, 0x1D, (ops GPRC:$RC, GPRC:$RA, u8imm:$L), "cmpult $RA,$L,$RC">; //Compare unsigned quadword less than
+def CMPBGE   : OForm< 0x10, 0x0F, "cmpbge $RA,$RB,$RC">; //Compare byte
+def CMPBGEi  : OFormL<0x10, 0x0F, "cmpbge $RA,$L,$RC">; //Compare byte
+def CMPEQ    : OForm< 0x10, 0x2D, "cmpeq $RA,$RB,$RC">; //Compare signed quadword equal
+def CMPEQi   : OFormL<0x10, 0x2D, "cmpeq $RA,$L,$RC">; //Compare signed quadword equal
+def CMPLE    : OForm< 0x10, 0x6D, "cmple $RA,$RB,$RC">; //Compare signed quadword less than or equal
+def CMPLEi   : OFormL<0x10, 0x6D, "cmple $RA,$L,$RC">; //Compare signed quadword less than or equal
+def CMPLT    : OForm< 0x10, 0x4D, "cmplt $RA,$RB,$RC">; //Compare signed quadword less than
+def CMPLTi   : OFormL<0x10, 0x4D, "cmplt $RA,$L,$RC">; //Compare signed quadword less than
+def CMPULE   : OForm< 0x10, 0x3D, "cmpule $RA,$RB,$RC">; //Compare unsigned quadword less than or equal
+def CMPULEi  : OFormL<0x10, 0x3D, "cmpule $RA,$L,$RC">; //Compare unsigned quadword less than or equal
+def CMPULT   : OForm< 0x10, 0x1D, "cmpult $RA,$RB,$RC">; //Compare unsigned quadword less than
+def CMPULTi  : OFormL<0x10, 0x1D, "cmpult $RA,$L,$RC">; //Compare unsigned quadword less than
 
 //Comparison, FP
 def CMPTEQ : FPForm<0x16, 0x0A5, (ops FPRC:$RC, FPRC:$RA, FPRC:$RB), "cmpteq/su $RA,$RB,$RC">;  //Compare T_floating equal
@@ -250,112 +238,116 @@
 def CMPTUN : FPForm<0x16, 0x0A4, (ops FPRC:$RC, FPRC:$RA, FPRC:$RB), "cmptun/su $RA,$RB,$RC">;  //Compare T_floating unordered
 
 //There are in the Multimedia extentions, so let's not use them yet
-def MAXSB8  : OForm<0x1C, 0x3E, (ops GPRC:$RC, GPRC:$RA, GPRC:$RB), "MAXSB8 $RA,$RB,$RC">; //Vector signed byte maximum
-def MAXSW4 : OForm< 0x1C, 0x3F, (ops GPRC:$RC, GPRC:$RA, GPRC:$RB), "MAXSW4 $RA,$RB,$RC">; //Vector signed word maximum
-def MAXUB8  : OForm<0x1C, 0x3C, (ops GPRC:$RC, GPRC:$RA, GPRC:$RB), "MAXUB8 $RA,$RB,$RC">; //Vector unsigned byte maximum
-def MAXUW4 : OForm< 0x1C, 0x3D, (ops GPRC:$RC, GPRC:$RA, GPRC:$RB), "MAXUW4 $RA,$RB,$RC">; //Vector unsigned word maximum
-def MINSB8 : OForm< 0x1C, 0x38, (ops GPRC:$RC, GPRC:$RA, GPRC:$RB), "MINSB8 $RA,$RB,$RC">; //Vector signed byte minimum
-def MINSW4 : OForm< 0x1C, 0x39, (ops GPRC:$RC, GPRC:$RA, GPRC:$RB), "MINSW4 $RA,$RB,$RC">; //Vector signed word minimum
-def MINUB8 : OForm< 0x1C, 0x3A, (ops GPRC:$RC, GPRC:$RA, GPRC:$RB), "MINUB8 $RA,$RB,$RC">; //Vector unsigned byte minimum
-def MINUW4 : OForm< 0x1C, 0x3B, (ops GPRC:$RC, GPRC:$RA, GPRC:$RB), "MINUW4 $RA,$RB,$RC">; //Vector unsigned word minimum
-def PERR : OForm< 0x1C, 0x31, (ops GPRC:$RC, GPRC:$RA, GPRC:$RB), "PERR $RA,$RB,$RC">; //Pixel error
-def PKLB : OForm< 0x1C, 0x37, (ops GPRC:$RC, GPRC:$RA, GPRC:$RB), "PKLB $RA,$RB,$RC">; //Pack longwords to bytes
-def PKWB  : OForm<0x1C, 0x36, (ops GPRC:$RC, GPRC:$RA, GPRC:$RB), "PKWB $RA,$RB,$RC">; //Pack words to bytes
-def UNPKBL : OForm< 0x1C, 0x35, (ops GPRC:$RC, GPRC:$RA, GPRC:$RB), "UNPKBL $RA,$RB,$RC">; //Unpack bytes to longwords
-def UNPKBW : OForm< 0x1C, 0x34, (ops GPRC:$RC, GPRC:$RA, GPRC:$RB), "UNPKBW $RA,$RB,$RC">; //Unpack bytes to words
+def MAXSB8  : OForm<0x1C, 0x3E, "MAXSB8 $RA,$RB,$RC">; //Vector signed byte maximum
+def MAXSW4 : OForm< 0x1C, 0x3F, "MAXSW4 $RA,$RB,$RC">; //Vector signed word maximum
+def MAXUB8  : OForm<0x1C, 0x3C, "MAXUB8 $RA,$RB,$RC">; //Vector unsigned byte maximum
+def MAXUW4 : OForm< 0x1C, 0x3D, "MAXUW4 $RA,$RB,$RC">; //Vector unsigned word maximum
+def MINSB8 : OForm< 0x1C, 0x38, "MINSB8 $RA,$RB,$RC">; //Vector signed byte minimum
+def MINSW4 : OForm< 0x1C, 0x39, "MINSW4 $RA,$RB,$RC">; //Vector signed word minimum
+def MINUB8 : OForm< 0x1C, 0x3A, "MINUB8 $RA,$RB,$RC">; //Vector unsigned byte minimum
+def MINUW4 : OForm< 0x1C, 0x3B, "MINUW4 $RA,$RB,$RC">; //Vector unsigned word minimum
+def PERR : OForm< 0x1C, 0x31, "PERR $RA,$RB,$RC">; //Pixel error
+def PKLB : OForm< 0x1C, 0x37, "PKLB $RA,$RB,$RC">; //Pack longwords to bytes
+def PKWB  : OForm<0x1C, 0x36, "PKWB $RA,$RB,$RC">; //Pack words to bytes
+def UNPKBL : OForm< 0x1C, 0x35, "UNPKBL $RA,$RB,$RC">; //Unpack bytes to longwords
+def UNPKBW : OForm< 0x1C, 0x34, "UNPKBW $RA,$RB,$RC">; //Unpack bytes to words
 
 //End operate
 
 let isReturn = 1, isTerminator = 1 in
-  def RET : MForm< 0x1A, (ops GPRC:$RD, GPRC:$RS), "ret $RD,($RS),1">; //Return from subroutine
+  def RET : MbrForm< 0x1A, 0x02, (ops GPRC:$RD, GPRC:$RS, s64imm:$DISP), "ret $RD,($RS),$DISP">; //Return from subroutine
 
-def JMP : MForm< 0x1A, (ops GPRC:$RD, GPRC:$RS), "jmp $RD,($RS),0">; //Jump
+def JMP : MbrForm< 0x1A, 0x00, (ops GPRC:$RD, GPRC:$RS, GPRC:$DISP), "jmp $RD,($RS),$DISP">; //Jump
 let isCall = 1,
     Defs = [R0, R1, R2, R3, R4, R5, R6, R7, R8, R16, R17, R18, R19,
             R20, R21, R22, R23, R24, R25, R27, R28, R29,
             F0, F1,
             F10, F11, F12, F13, F14, F15, F16, F17, F18, F19,
             F20, F21, F22, F23, F24, F25, F26, F27, F28, F29, F30], Uses = [R29] in {
-    def JSR : MForm< 0x1A, (ops GPRC:$RD, GPRC:$RS, s14imm:$DISP), "jsr $RD,($RS),$DISP">; //Jump to subroutine
-    def BSR : BForm<0x34, (ops GPRC:$RD, s21imm:$DISP), "bsr $RD,$DISP">; //Branch to subroutine
+    def JSR : MbrForm< 0x1A, 0x01, (ops GPRC:$RD, GPRC:$RS, s14imm:$DISP), "jsr $RD,($RS),$DISP">; //Jump to subroutine
+    def BSR : BForm<0x34, "bsr $RA,$DISP">; //Branch to subroutine
 }
 let isCall = 1, Defs = [R24, R25, R27, R28], Uses = [R24, R25] in
-  def JSRs : MForm< 0x1A, (ops GPRC:$RD, GPRC:$RS, s14imm:$DISP), "jsr $RD,($RS),$DISP">; //Jump to div or rem
-
+  def JSRs : MbrForm< 0x1A, 0x01, (ops GPRC:$RD, GPRC:$RS, s14imm:$DISP), "jsr $RD,($RS),$DISP">; //Jump to div or rem
 
-def JSR_COROUTINE : MForm< 0x1A, (ops GPRC:$RD, GPRC:$RS), "jsr_coroutine $RD,($RS),1">; //Jump to subroutine return
-def BR : BForm<0x30, (ops GPRC:$RD, s21imm:$DISP), "br $RD,$DISP">; //Branch
+def JSR_COROUTINE : MbrForm< 0x1A, 0x03, (ops GPRC:$RD, GPRC:$RS, s14imm:$DISP), "jsr_coroutine $RD,($RS),$DISP">; //Jump to subroutine return
+def BR : BForm<0x30, "br $RA,$DISP">; //Branch
 
 //Stores, int
-def STB : MForm<0x0E, (ops GPRC:$RA, s16imm:$DISP, GPRC:$RB), "stb $RA,$DISP($RB)">; // Store byte
-def STW : MForm<0x0D, (ops GPRC:$RA, s16imm:$DISP, GPRC:$RB), "stw $RA,$DISP($RB)">; // Store word
-def STL : MForm<0x2C, (ops GPRC:$RA, s16imm:$DISP, GPRC:$RB), "stl $RA,$DISP($RB)">; // Store longword
-def STQ : MForm<0x2D, (ops GPRC:$RA, s16imm:$DISP, GPRC:$RB), "stq $RA,$DISP($RB)">; //Store quadword
+def STB : MForm<0x0E, "stb $RA,$DISP($RB)">; // Store byte
+def STW : MForm<0x0D, "stw $RA,$DISP($RB)">; // Store word
+def STL : MForm<0x2C, "stl $RA,$DISP($RB)">; // Store longword
+def STQ : MForm<0x2D, "stq $RA,$DISP($RB)">; //Store quadword
 
 //Loads, int
-def LDL : MForm<0x28, (ops GPRC:$RA, s16imm:$DISP, GPRC:$RB), "ldl $RA,$DISP($RB)">; // Load sign-extended longword
-def LDQ : MForm<0x29, (ops GPRC:$RA, s16imm:$DISP, GPRC:$RB), "ldq $RA,$DISP($RB)">; //Load quadword
-def LDBU : MForm<0x0A, (ops GPRC:$RA, s16imm:$DISP, GPRC:$RB), "ldbu $RA,$DISP($RB)">; //Load zero-extended byte
-def LDWU : MForm<0x0C, (ops GPRC:$RA, s16imm:$DISP, GPRC:$RB), "ldwu $RA,$DISP($RB)">; //Load zero-extended word
+def LDL : MForm<0x28,  "ldl $RA,$DISP($RB)">; // Load sign-extended longword
+def LDQ : MForm<0x29,  "ldq $RA,$DISP($RB)">; //Load quadword
+def LDBU : MForm<0x0A, "ldbu $RA,$DISP($RB)">; //Load zero-extended byte
+def LDWU : MForm<0x0C, "ldwu $RA,$DISP($RB)">; //Load zero-extended word
 
 //Stores, float
-def STS : MForm<0x26, (ops FPRC:$RA, s16imm:$DISP, GPRC:$RB), "sts $RA,$DISP($RB)">; //Store S_floating
-def STT : MForm<0x27, (ops FPRC:$RA, s16imm:$DISP, GPRC:$RB), "stt $RA,$DISP($RB)">; //Store T_floating
+def STS : MForm<0x26, "sts $RA,$DISP($RB)">; //Store S_floating
+def STT : MForm<0x27, "stt $RA,$DISP($RB)">; //Store T_floating
 
 //Loads, float
-def LDS : MForm<0x22, (ops FPRC:$RA, s16imm:$DISP, GPRC:$RB), "lds $RA,$DISP($RB)">; //Load S_floating
-def LDT : MForm<0x23, (ops FPRC:$RA, s16imm:$DISP, GPRC:$RB), "ldt $RA,$DISP($RB)">; //Load T_floating
+def LDS : MForm<0x22, "lds $RA,$DISP($RB)">; //Load S_floating
+def LDT : MForm<0x23, "ldt $RA,$DISP($RB)">; //Load T_floating
 
 //Load address
-def LDA : MForm<0x08, (ops GPRC:$RA, s16imm:$DISP, GPRC:$RB), "lda $RA,$DISP($RB)">;  //Load address
-def LDAH : MForm<0x08, (ops GPRC:$RA, s16imm:$DISP, GPRC:$RB), "ldah $RA,$DISP($RB)">;  //Load address high
+def LDA : MForm<0x08,  "lda $RA,$DISP($RB)">;  //Load address
+def LDAH : MForm<0x09, "ldah $RA,$DISP($RB)">;  //Load address high
 
 
 //Loads, int, Rellocated Low form
-def LDLr : MForm<0x28, (ops GPRC:$RA, s16imm:$DISP, GPRC:$RB), "ldl $RA,$DISP($RB) !gprellow">; // Load sign-extended longword
-def LDQr : MForm<0x29, (ops GPRC:$RA, s16imm:$DISP, GPRC:$RB), "ldq $RA,$DISP($RB) !gprellow">; //Load quadword
-def LDBUr : MForm<0x0A, (ops GPRC:$RA, s16imm:$DISP, GPRC:$RB), "ldbu $RA,$DISP($RB) !gprellow">; //Load zero-extended byte
-def LDWUr : MForm<0x0C, (ops GPRC:$RA, s16imm:$DISP, GPRC:$RB), "ldwu $RA,$DISP($RB) !gprellow">; //Load zero-extended word
+def LDLr : MForm<0x28,  "ldl $RA,$DISP($RB) !gprellow">; // Load sign-extended longword
+def LDQr : MForm<0x29,  "ldq $RA,$DISP($RB) !gprellow">; //Load quadword
+def LDBUr : MForm<0x0A, "ldbu $RA,$DISP($RB) !gprellow">; //Load zero-extended byte
+def LDWUr : MForm<0x0C, "ldwu $RA,$DISP($RB) !gprellow">; //Load zero-extended word
 
 //Loads, float, Rellocated Low form
-def LDSr : MForm<0x22, (ops FPRC:$RA, s16imm:$DISP, GPRC:$RB), "lds $RA,$DISP($RB) !gprellow">; //Load S_floating
-def LDTr : MForm<0x23, (ops FPRC:$RA, s16imm:$DISP, GPRC:$RB), "ldt $RA,$DISP($RB) !gprellow">; //Load T_floating
+def LDSr : MForm<0x22, "lds $RA,$DISP($RB) !gprellow">; //Load S_floating
+def LDTr : MForm<0x23, "ldt $RA,$DISP($RB) !gprellow">; //Load T_floating
 
 //Load address, rellocated low and high form
-def LDAr : MForm<0x08, (ops GPRC:$RA, s16imm:$DISP, GPRC:$RB), "lda $RA,$DISP($RB) !gprellow">;  //Load address
-def LDAHr : MForm<0x08, (ops GPRC:$RA, s16imm:$DISP, GPRC:$RB), "ldah $RA,$DISP($RB) !gprelhigh">;  //Load address high
+def LDAr : MForm<0x08,  "lda $RA,$DISP($RB) !gprellow">;  //Load address
+def LDAHr : MForm<0x09, "ldah $RA,$DISP($RB) !gprelhigh">;  //Load address high
+
+//load address, rellocated gpdist form
+def LDAg : MgForm<0x08,  "lda $RA,0($RB) !gpdisp!$NUM">;  //Load address
+def LDAHg : MgForm<0x09, "ldah $RA,0($RB) !gpdisp!$NUM">;  //Load address
+
 
 //Load quad, rellocated literal form
-def LDQl : MForm<0x29, (ops GPRC:$RA, s16imm:$DISP, GPRC:$RB), "ldq $RA,$DISP($RB) !literal">; //Load quadword
+def LDQl : MForm<0x29, "ldq $RA,$DISP($RB) !literal">; //Load quadword
 
 //Stores, int
-def STBr : MForm<0x0E, (ops GPRC:$RA, s16imm:$DISP, GPRC:$RB), "stb $RA,$DISP($RB) !gprellow">; // Store byte
-def STWr : MForm<0x0D, (ops GPRC:$RA, s16imm:$DISP, GPRC:$RB), "stw $RA,$DISP($RB) !gprellow">; // Store word
-def STLr : MForm<0x2C, (ops GPRC:$RA, s16imm:$DISP, GPRC:$RB), "stl $RA,$DISP($RB) !gprellow">; // Store longword
-def STQr : MForm<0x2D, (ops GPRC:$RA, s16imm:$DISP, GPRC:$RB), "stq $RA,$DISP($RB) !gprellow">; //Store quadword
+def STBr : MForm<0x0E, "stb $RA,$DISP($RB) !gprellow">; // Store byte
+def STWr : MForm<0x0D, "stw $RA,$DISP($RB) !gprellow">; // Store word
+def STLr : MForm<0x2C, "stl $RA,$DISP($RB) !gprellow">; // Store longword
+def STQr : MForm<0x2D, "stq $RA,$DISP($RB) !gprellow">; //Store quadword
 
 //Stores, float
-def STSr : MForm<0x26, (ops FPRC:$RA, s16imm:$DISP, GPRC:$RB), "sts $RA,$DISP($RB) !gprellow">; //Store S_floating
-def STTr : MForm<0x27, (ops FPRC:$RA, s16imm:$DISP, GPRC:$RB), "stt $RA,$DISP($RB) !gprellow">; //Store T_floating
+def STSr : MForm<0x26, "sts $RA,$DISP($RB) !gprellow">; //Store S_floating
+def STTr : MForm<0x27, "stt $RA,$DISP($RB) !gprellow">; //Store T_floating
 
 
 //Branches, int
-def BEQ : BForm<0x39, (ops GPRC:$RA, s21imm:$DISP), "beq $RA,$DISP">; //Branch if = zero
-def BGE : BForm<0x3E, (ops GPRC:$RA, s21imm:$DISP), "bge $RA,$DISP">; //Branch if >= zero
-def BGT : BForm<0x3F, (ops GPRC:$RA, s21imm:$DISP), "bgt $RA,$DISP">; //Branch if > zero
-def BLBC : BForm<0x38, (ops GPRC:$RA, s21imm:$DISP), "blbc $RA,$DISP">; //Branch if low bit clear
-def BLBS : BForm<0x3C, (ops GPRC:$RA, s21imm:$DISP), "blbs $RA,$DISP">; //Branch if low bit set
-def BLE : BForm<0x3B, (ops GPRC:$RA, s21imm:$DISP), "ble $RA,$DISP">; //Branch if <= zero
-def BLT : BForm<0x3A, (ops GPRC:$RA, s21imm:$DISP), "blt $RA,$DISP">; //Branch if < zero
-def BNE : BForm<0x3D, (ops GPRC:$RA, s21imm:$DISP), "bne $RA,$DISP">; //Branch if != zero
+def BEQ : BForm<0x39,  "beq $RA,$DISP">; //Branch if = zero
+def BGE : BForm<0x3E,  "bge $RA,$DISP">; //Branch if >= zero
+def BGT : BForm<0x3F,  "bgt $RA,$DISP">; //Branch if > zero
+def BLBC : BForm<0x38, "blbc $RA,$DISP">; //Branch if low bit clear
+def BLBS : BForm<0x3C, "blbs $RA,$DISP">; //Branch if low bit set
+def BLE : BForm<0x3B,  "ble $RA,$DISP">; //Branch if <= zero
+def BLT : BForm<0x3A,  "blt $RA,$DISP">; //Branch if < zero
+def BNE : BForm<0x3D,  "bne $RA,$DISP">; //Branch if != zero
 
 //Branches, float
-def FBEQ : BForm<0x31, (ops FPRC:$RA, s21imm:$DISP), "fbeq $RA,$DISP">; //Floating branch if =  zero
-def FBGE : BForm<0x36, (ops FPRC:$RA, s21imm:$DISP), "fbge $RA,$DISP">; //Floating branch if >= zero
-def FBGT : BForm<0x37, (ops FPRC:$RA, s21imm:$DISP), "fbgt $RA,$DISP">; //Floating branch if > zero
-def FBLE : BForm<0x33, (ops FPRC:$RA, s21imm:$DISP), "fble $RA,$DISP">; //Floating branch if <= zero
-def FBLT : BForm<0x32, (ops FPRC:$RA, s21imm:$DISP), "fblt $RA,$DISP">; //Floating branch if < zero
-def FBNE : BForm<0x35, (ops FPRC:$RA, s21imm:$DISP), "fbne $RA,$DISP">; //Floating branch if != zero
+def FBEQ : FBForm<0x31, "fbeq $RA,$DISP">; //Floating branch if =  zero
+def FBGE : FBForm<0x36, "fbge $RA,$DISP">; //Floating branch if >= zero
+def FBGT : FBForm<0x37, "fbgt $RA,$DISP">; //Floating branch if > zero
+def FBLE : FBForm<0x33, "fble $RA,$DISP">; //Floating branch if <= zero
+def FBLT : FBForm<0x32, "fblt $RA,$DISP">; //Floating branch if < zero
+def FBNE : FBForm<0x35, "fbne $RA,$DISP">; //Floating branch if != zero
 
 //Funky Floating point ops
 def CPYS  : FPForm<0x17, 0x020, (ops FPRC:$RC, FPRC:$RA, FPRC:$RB), "cpys $RA,$RB,$RC">;  //Copy sign


Index: llvm/lib/Target/Alpha/AlphaInstrFormats.td
diff -u llvm/lib/Target/Alpha/AlphaInstrFormats.td:1.4 llvm/lib/Target/Alpha/AlphaInstrFormats.td:1.5
--- llvm/lib/Target/Alpha/AlphaInstrFormats.td:1.4	Fri Feb  4 20:24:26 2005
+++ llvm/lib/Target/Alpha/AlphaInstrFormats.td	Fri Jul 22 15:50:29 2005
@@ -17,6 +17,12 @@
 //Floating-point
 //PALcode
 
+def u8imm   : Operand<i8>;
+def s14imm  : Operand<i16>;
+def s16imm  : Operand<i16>;
+def s21imm  : Operand<i32>;
+def s64imm  : Operand<i64>;
+
 //===----------------------------------------------------------------------===//
 // Instruction format superclass
 //===----------------------------------------------------------------------===//
@@ -32,19 +38,53 @@
 }
 
 //3.3.1
-class MForm<bits<6> opcode, dag OL, string asmstr> : InstAlpha<opcode, OL, asmstr> {
+class MForm<bits<6> opcode, string asmstr> 
+        : InstAlpha<opcode, (ops GPRC:$RA, s16imm:$DISP, GPRC:$RB), asmstr> {
   bits<5> Ra;
+  bits<16> disp;
   bits<5> Rb;
+
+  let Inst{25-21} = Ra;
+  let Inst{20-16} = Rb;
+  let Inst{15-0} = disp;
+}
+
+class MgForm<bits<6> opcode, string asmstr> 
+        : InstAlpha<opcode, (ops GPRC:$RA, s16imm:$DISP, GPRC:$RB, s16imm:$NUM), asmstr> {
+  bits<5> Ra;
   bits<16> disp;
+  bits<5> Rb;
 
   let Inst{25-21} = Ra;
   let Inst{20-16} = Rb;
   let Inst{15-0} = disp;
 }
 
+class MbrForm<bits<6> opcode, bits<2> TB, dag OL, string asmstr> : InstAlpha<opcode, OL, asmstr> {
+  bits<5> Ra;
+  bits<5> Rb;
+  bits<14> disp;
+
+  let Inst{25-21} = Ra;
+  let Inst{20-16} = Rb;
+  let Inst{15-14} = TB;
+  let Inst{13-0} = disp;
+}
+
 //3.3.2
 let isBranch = 1, isTerminator = 1 in
-class BForm<bits<6> opcode, dag OL, string asmstr> : InstAlpha<opcode, OL, asmstr> {
+class BForm<bits<6> opcode, string asmstr> 
+    : InstAlpha<opcode, (ops GPRC:$RA, s21imm:$DISP), asmstr> {
+  bits<5> Ra;
+  bits<21> disp;
+
+  let Inst{25-21} = Ra;
+  let Inst{20-0} = disp;
+}
+
+let isBranch = 1, isTerminator = 1 in
+class FBForm<bits<6> opcode, string asmstr> 
+    : InstAlpha<opcode, (ops FPRC:$RA, s21imm:$DISP), asmstr> {
   bits<5> Ra;
   bits<21> disp;
 
@@ -53,23 +93,53 @@
 }
 
 //3.3.3
-class OForm<bits<6> opcode, bits<7> fun, dag OL, string asmstr> : InstAlpha<opcode, OL, asmstr> {
+class OForm<bits<6> opcode, bits<7> fun, string asmstr> 
+        : InstAlpha<opcode, (ops GPRC:$RC, GPRC:$RA, GPRC:$RB), asmstr> {
+  bits<5> Rc;
+  bits<5> Ra;
+  bits<5> Rb;
+  bits<7> Function = fun;
+
+  let Inst{25-21} = Ra;
+  let Inst{20-16} = Rb;
+  let Inst{15-13} = 0;
+  let Inst{12} = 0;
+  let Inst{11-5} = Function;
+  let Inst{4-0} = Rc;
+}
+
+class OcmForm<bits<6> opcode, bits<7> fun, dag OL, string asmstr> 
+        : InstAlpha<opcode, OL, asmstr> {
   bits<5> Ra;
   bits<5> Rb;
-  bits<3> SBZ;
   bits<7> Function = fun;
   bits<5> Rc;
 
   let Inst{25-21} = Ra;
   let Inst{20-16} = Rb;
-  let Inst{15-13} = SBZ;
+  let Inst{15-13} = 0;
   let Inst{12} = 0;
   let Inst{11-5} = Function;
   let Inst{4-0} = Rc;
 }
 
 
-class OFormL<bits<6> opcode, bits<7> fun, dag OL, string asmstr> : InstAlpha<opcode, OL, asmstr> {
+class OFormL<bits<6> opcode, bits<7> fun, string asmstr> 
+        : InstAlpha<opcode, (ops GPRC:$RC, GPRC:$RA, u8imm:$L), asmstr> {
+  bits<5> Rc;
+  bits<5> Ra;
+  bits<8> LIT;
+  bits<7> Function = fun;
+
+  let Inst{25-21} = Ra;
+  let Inst{20-13} = LIT;
+  let Inst{12} = 1;
+  let Inst{11-5} = Function;
+  let Inst{4-0} = Rc;
+}
+
+class OcmFormL<bits<6> opcode, bits<7> fun, dag OL, string asmstr> 
+        : InstAlpha<opcode, OL, asmstr> {
   bits<5> Ra;
   bits<8> LIT;
   bits<7> Function = fun;


Index: llvm/lib/Target/Alpha/AlphaISelPattern.cpp
diff -u llvm/lib/Target/Alpha/AlphaISelPattern.cpp:1.151 llvm/lib/Target/Alpha/AlphaISelPattern.cpp:1.152
--- llvm/lib/Target/Alpha/AlphaISelPattern.cpp:1.151	Mon Jul 11 23:20:52 2005
+++ llvm/lib/Target/Alpha/AlphaISelPattern.cpp	Fri Jul 22 15:50:29 2005
@@ -1125,7 +1125,7 @@
     Opc = opcode == ISD::CTPOP ? Alpha::CTPOP :
     (opcode == ISD::CTTZ ? Alpha::CTTZ : Alpha::CTLZ);
     Tmp1 = SelectExpr(N.getOperand(0));
-    BuildMI(BB, Opc, 1, Result).addReg(Tmp1);
+    BuildMI(BB, Opc, 1, Result).addReg(Alpha::R31).addReg(Tmp1);
     return Result;
 
   case ISD::MULHU:
@@ -1331,7 +1331,7 @@
       Select(N.getOperand(0));
 
       // The chain for this call is now lowered.
-      ExprMap.insert(std::make_pair(N.getValue(Node->getNumValues()-1), notIn));
+      ExprMap[N.getValue(Node->getNumValues()-1)] = notIn;
 
       //grab the arguments
       std::vector<unsigned> argvregs;
@@ -1404,10 +1404,6 @@
         BuildMI(BB, Alpha::BSR, 1, Alpha::R26)
           .addGlobalAddress(GASD->getGlobal(),true);
       } else {
-        //Must always reread relocation table before a call
-        if (GASD)
-          ExprMap.erase(N.getOperand(1));
-
         //no need to restore GP as we are doing an indirect call
         Tmp1 = SelectExpr(N.getOperand(1));
         BuildMI(BB, Alpha::BIS, 2, Alpha::R27).addReg(Tmp1).addReg(Tmp1);
@@ -1522,10 +1518,10 @@
           break;
         }
       case MVT::i16:
-        BuildMI(BB, Alpha::SEXTW, 1, Result).addReg(Tmp1);
+        BuildMI(BB, Alpha::SEXTW, 1, Result).addReg(Alpha::R31).addReg(Tmp1);
         break;
       case MVT::i8:
-        BuildMI(BB, Alpha::SEXTB, 1, Result).addReg(Tmp1);
+        BuildMI(BB, Alpha::SEXTB, 1, Result).addReg(Alpha::R31).addReg(Tmp1);
         break;
       case MVT::i1:
         Tmp2 = MakeReg(MVT::i64);
@@ -2247,7 +2243,7 @@
     }
     // Just emit a 'ret' instruction
     AlphaLowering.restoreRA(BB);
-    BuildMI(BB, Alpha::RET, 1, Alpha::R31).addReg(Alpha::R26);
+    BuildMI(BB, Alpha::RET, 2, Alpha::R31).addReg(Alpha::R26).addImm(1);
     return;
 
   case ISD::TRUNCSTORE:





From alenhar2 at cs.uiuc.edu  Fri Jul 22 15:52:27 2005
From: alenhar2 at cs.uiuc.edu (Andrew Lenharth)
Date: Fri, 22 Jul 2005 15:52:27 -0500
Subject: [llvm-commits] CVS: llvm/lib/Target/Alpha/AlphaCodeEmitter.cpp
	AlphaJITInfo.cpp AlphaJITInfo.h AlphaRelocations.h Alpha.h
	AlphaAsmPrinter.cpp AlphaRegisterInfo.cpp
	AlphaTargetMachine.cpp AlphaTargetMachine.h 
Message-ID: <200507222052.PAA03983@zion.cs.uiuc.edu>



Changes in directory llvm/lib/Target/Alpha:

AlphaCodeEmitter.cpp added (r1.1)
AlphaJITInfo.cpp added (r1.1)
AlphaJITInfo.h added (r1.1)
AlphaRelocations.h added (r1.1)
Alpha.h updated: 1.3 -> 1.4
AlphaAsmPrinter.cpp updated: 1.17 -> 1.18
AlphaRegisterInfo.cpp updated: 1.24 -> 1.25
AlphaTargetMachine.cpp updated: 1.8 -> 1.9
AlphaTargetMachine.h updated: 1.7 -> 1.8
---
Log message:

Alpha JIT (beta)

---
Diffs of the changes:  (+673 -3)

 Alpha.h                |    3 
 AlphaAsmPrinter.cpp    |    1 
 AlphaCodeEmitter.cpp   |  231 +++++++++++++++++++++++++++++++++++++++++
 AlphaJITInfo.cpp       |  273 +++++++++++++++++++++++++++++++++++++++++++++++++
 AlphaJITInfo.h         |   56 ++++++++++
 AlphaRegisterInfo.cpp  |   10 +
 AlphaRelocations.h     |   30 +++++
 AlphaTargetMachine.cpp |   56 +++++++++-
 AlphaTargetMachine.h   |   16 ++
 9 files changed, 673 insertions(+), 3 deletions(-)


Index: llvm/lib/Target/Alpha/AlphaCodeEmitter.cpp
diff -c /dev/null llvm/lib/Target/Alpha/AlphaCodeEmitter.cpp:1.1
*** /dev/null	Fri Jul 22 15:52:26 2005
--- llvm/lib/Target/Alpha/AlphaCodeEmitter.cpp	Fri Jul 22 15:52:16 2005
***************
*** 0 ****
--- 1,231 ----
+ //===-- Alpha/AlphaCodeEmitter.cpp - Convert Alpha code to machine code ---===//
+ //
+ //                     The LLVM Compiler Infrastructure
+ //
+ // This file was developed by the LLVM research group and is distributed under
+ // the University of Illinois Open Source License. See LICENSE.TXT for details.
+ //
+ //===----------------------------------------------------------------------===//
+ //
+ // This file contains the pass that transforms the Alpha machine instructions
+ // into relocatable machine code.
+ //
+ //===----------------------------------------------------------------------===//
+ 
+ #include "AlphaTargetMachine.h"
+ #include "AlphaRelocations.h"
+ #include "Alpha.h"
+ #include "llvm/PassManager.h"
+ #include "llvm/CodeGen/MachineCodeEmitter.h"
+ #include "llvm/CodeGen/MachineFunctionPass.h"
+ #include "llvm/CodeGen/MachineInstr.h"
+ #include "llvm/CodeGen/Passes.h"
+ #include "llvm/Function.h"
+ #include "llvm/Support/Debug.h"
+ #include "llvm/ADT/Statistic.h"
+ using namespace llvm;
+ 
+ namespace {
+   Statistic<>
+   NumEmitted("alpha-emitter", "Number of machine instructions emitted");
+ }
+ 
+ namespace {
+   class AlphaCodeEmitter : public MachineFunctionPass {
+     const AlphaInstrInfo  *II;
+     MachineCodeEmitter  &MCE;
+     std::map<const MachineBasicBlock*, unsigned*> BasicBlockAddrs;
+     std::vector<std::pair<const MachineBasicBlock *, unsigned*> > BBRefs;
+ 
+     /// getMachineOpValue - evaluates the MachineOperand of a given MachineInstr
+     ///
+     int getMachineOpValue(MachineInstr &MI, MachineOperand &MO);
+ 
+   public:
+     explicit AlphaCodeEmitter(MachineCodeEmitter &mce) : II(0), MCE(mce) {}
+     AlphaCodeEmitter(MachineCodeEmitter &mce, const AlphaInstrInfo& ii)
+         : II(&ii), MCE(mce) {}
+ 
+     bool runOnMachineFunction(MachineFunction &MF);
+ 
+     virtual const char *getPassName() const {
+       return "Alpha Machine Code Emitter";
+     }
+ 
+     void emitInstruction(const MachineInstr &MI);
+ 
+     /// emitWord - write a 32-bit word to memory at the current PC
+     ///
+     void emitWord(unsigned w) { MCE.emitWord(w); }
+ 
+     /// getBinaryCodeForInstr - This function, generated by the
+     /// CodeEmitterGenerator using TableGen, produces the binary encoding for
+     /// machine instructions.
+     ///
+     unsigned getBinaryCodeForInstr(MachineInstr &MI);
+ 
+   private:
+     void emitBasicBlock(MachineBasicBlock &MBB);
+ 
+   };
+ }
+ 
+ /// createAlphaCodeEmitterPass - Return a pass that emits the collected Alpha code
+ /// to the specified MCE object.
+ FunctionPass *llvm::createAlphaCodeEmitterPass(MachineCodeEmitter &MCE) {
+   return new AlphaCodeEmitter(MCE);
+ }
+ 
+ bool AlphaCodeEmitter::runOnMachineFunction(MachineFunction &MF) {
+   II = ((AlphaTargetMachine&)MF.getTarget()).getInstrInfo();
+ 
+   MCE.startFunction(MF);
+   MCE.emitConstantPool(MF.getConstantPool());
+   for (MachineFunction::iterator I = MF.begin(), E = MF.end(); I != E; ++I)
+     emitBasicBlock(*I);
+   MCE.finishFunction(MF);
+ 
+   // Resolve all forward branches now...
+   for (unsigned i = 0, e = BBRefs.size(); i != e; ++i) {
+     unsigned* Location = (unsigned*)BasicBlockAddrs[BBRefs[i].first];
+     unsigned* Ref = (unsigned*)BBRefs[i].second;
+     intptr_t BranchTargetDisp = (((unsigned char*)Location  - (unsigned char*)Ref) >> 2) - 1;
+     DEBUG(std::cerr << "Fixup @ " << (void*)Ref << " to " << (void*)Location
+           << " Disp " << BranchTargetDisp << " using " <<  (BranchTargetDisp & ((1 << 22)-1)) << "\n");
+     *Ref |= (BranchTargetDisp & ((1 << 21)-1));
+   }
+   BBRefs.clear();
+   BasicBlockAddrs.clear();
+ 
+   return false;
+ }
+ 
+ void AlphaCodeEmitter::emitBasicBlock(MachineBasicBlock &MBB) {
+   uint64_t Addr = MCE.getCurrentPCValue();
+   BasicBlockAddrs[&MBB] = (unsigned*)Addr;
+ 
+   for (MachineBasicBlock::iterator I = MBB.begin(), E = MBB.end();
+        I != E; ++I) {
+     MachineInstr &MI = *I;
+     unsigned Opcode = MI.getOpcode();
+     switch(MI.getOpcode()) {
+     default:
+       emitWord(getBinaryCodeForInstr(*I));
+       break;
+     case Alpha::ALTENT:
+     case Alpha::PCLABEL:
+     case Alpha::MEMLABEL:
+       break; //skip these
+     }
+   }
+ }
+ 
+ static unsigned getAlphaRegNumber(unsigned Reg) {
+   switch (Reg) {
+   case Alpha::R0  : case Alpha::F0  : return 0;
+   case Alpha::R1  : case Alpha::F1  : return 1;
+   case Alpha::R2  : case Alpha::F2  : return 2;
+   case Alpha::R3  : case Alpha::F3  : return 3;
+   case Alpha::R4  : case Alpha::F4  : return 4;
+   case Alpha::R5  : case Alpha::F5  : return 5;
+   case Alpha::R6  : case Alpha::F6  : return 6;
+   case Alpha::R7  : case Alpha::F7  : return 7;
+   case Alpha::R8  : case Alpha::F8  : return 8;
+   case Alpha::R9  : case Alpha::F9  : return 9;
+   case Alpha::R10 : case Alpha::F10 : return 10;
+   case Alpha::R11 : case Alpha::F11 : return 11;
+   case Alpha::R12 : case Alpha::F12 : return 12;
+   case Alpha::R13 : case Alpha::F13 : return 13;
+   case Alpha::R14 : case Alpha::F14 : return 14;
+   case Alpha::R15 : case Alpha::F15 : return 15;
+   case Alpha::R16 : case Alpha::F16 : return 16;
+   case Alpha::R17 : case Alpha::F17 : return 17;
+   case Alpha::R18 : case Alpha::F18 : return 18;
+   case Alpha::R19 : case Alpha::F19 : return 19;
+   case Alpha::R20 : case Alpha::F20 : return 20;
+   case Alpha::R21 : case Alpha::F21 : return 21;
+   case Alpha::R22 : case Alpha::F22 : return 22;
+   case Alpha::R23 : case Alpha::F23 : return 23;
+   case Alpha::R24 : case Alpha::F24 : return 24;
+   case Alpha::R25 : case Alpha::F25 : return 25;
+   case Alpha::R26 : case Alpha::F26 : return 26;
+   case Alpha::R27 : case Alpha::F27 : return 27;
+   case Alpha::R28 : case Alpha::F28 : return 28;
+   case Alpha::R29 : case Alpha::F29 : return 29;
+   case Alpha::R30 : case Alpha::F30 : return 30;
+   case Alpha::R31 : case Alpha::F31 : return 31;
+   default:
+     assert(0 && "Unhandled reg");
+     abort();
+   }
+ }
+ 
+ int AlphaCodeEmitter::getMachineOpValue(MachineInstr &MI, MachineOperand &MO) {
+ 
+   int rv = 0; // Return value; defaults to 0 for unhandled cases
+               // or things that get fixed up later by the JIT.
+ 
+   if (MO.isRegister()) {
+     rv = getAlphaRegNumber(MO.getReg());
+   } else if (MO.isImmediate()) {
+     rv = MO.getImmedValue();
+   } else if (MO.isGlobalAddress() || MO.isExternalSymbol() 
+              || MO.isConstantPoolIndex()) {
+     DEBUG(std::cerr << MO << " is a relocated op for " << MI << "\n";);
+     bool isExternal = MO.isExternalSymbol() || 
+       (MO.isGlobalAddress() && 
+        ( MO.getGlobal()->hasWeakLinkage() ||
+          MO.getGlobal()->isExternal()) );
+     unsigned Reloc = 0;
+     int Offset = 0;
+     switch (MI.getOpcode()) {
+     case Alpha::LDLr:
+     case Alpha::LDQr:
+     case Alpha::LDBUr:
+     case Alpha::LDWUr:
+     case Alpha::LDSr:
+     case Alpha::LDTr:
+     case Alpha::LDAr:
+       Reloc = Alpha::reloc_gprellow;
+       break;
+     case Alpha::LDAHr:
+       Reloc = Alpha::reloc_gprelhigh;
+       break;
+     case Alpha::LDQl:
+       Reloc = Alpha::reloc_literal;
+       break;
+     case Alpha::LDAg:
+     case Alpha::LDAHg:
+       Reloc = Alpha::reloc_gpdist;
+       Offset = MI.getOperand(3).getImmedValue();
+       break;
+     default:
+       assert(0 && "unknown relocatable instruction");
+       abort();
+     }
+     if (MO.isGlobalAddress())
+       MCE.addRelocation(MachineRelocation((unsigned)MCE.getCurrentPCOffset(),
+                                           Reloc, MO.getGlobal(), Offset,
+                                           true, true));
+     else if (MO.isExternalSymbol())
+       MCE.addRelocation(MachineRelocation((unsigned)MCE.getCurrentPCOffset(),
+                                           Reloc, MO.getSymbolName(), Offset,
+                                           true));
+     else
+       MCE.addRelocation(MachineRelocation((unsigned)MCE.getCurrentPCOffset(),
+                                           Reloc, MO.getConstantPoolIndex(), 
+                                           Offset));
+   } else if (MO.isMachineBasicBlock()) {
+     unsigned* CurrPC = (unsigned*)MCE.getCurrentPCValue();
+     BBRefs.push_back(std::make_pair(MO.getMachineBasicBlock(), CurrPC));
+   }else {
+     std::cerr << "ERROR: Unknown type of MachineOperand: " << MO << "\n";
+     abort();
+   }
+ 
+   return rv;
+ }
+ 
+ 
+ #include "AlphaGenCodeEmitter.inc"
+ 


Index: llvm/lib/Target/Alpha/AlphaJITInfo.cpp
diff -c /dev/null llvm/lib/Target/Alpha/AlphaJITInfo.cpp:1.1
*** /dev/null	Fri Jul 22 15:52:27 2005
--- llvm/lib/Target/Alpha/AlphaJITInfo.cpp	Fri Jul 22 15:52:16 2005
***************
*** 0 ****
--- 1,273 ----
+ //===-- AlphaJITInfo.cpp - Implement the JIT interfaces for the Alpha ---===//
+ //
+ //                     The LLVM Compiler Infrastructure
+ //
+ // This file was developed by the LLVM research group and is distributed under
+ // the University of Illinois Open Source License. See LICENSE.TXT for details.
+ //
+ //===----------------------------------------------------------------------===//
+ //
+ // This file implements the JIT interfaces for the Alpha target.
+ //
+ //===----------------------------------------------------------------------===//
+ 
+ #define DEBUG_TYPE "jit"
+ #include "AlphaJITInfo.h"
+ #include "AlphaRelocations.h"
+ #include "llvm/CodeGen/MachineCodeEmitter.h"
+ #include "llvm/Config/alloca.h"
+ #include "llvm/Support/Debug.h"
+ #include <cstdlib>
+ #include <iostream>
+ #include <map>
+ using namespace std;
+ using namespace llvm;
+ 
+ #define BUILD_LDA(RD, RS, IMM16) \
+   ((0x08 << 26) | ((RD) << 21) | ((RS) << 16) | ((IMM16) & 65535))
+ #define BUILD_LDAH(RD, RS, IMM16) \
+   ((0x09 << 26) | ((RD) << 21) | ((RS) << 16) | ((IMM16) & 65535))
+ 
+ #define MERGE_PARTS(HH, HL, LH, LL) \
+   (((HH * 65536 + HL) << 32) + (LH * 65536 + LL))
+ 
+ #define BUILD_LDQ(RD, RS, IMM16) \
+   ((0x29 << 26) | ((RD) << 21) | ((RS) << 16) | ((IMM16) & 0xFFFF))
+ 
+ #define BUILD_JMP(RD, RS, IMM16) \
+   ((0x1A << 26) | ((RD) << 21) | ((RS) << 16) | ((IMM16) & 0xFFFF))
+ 
+ static void EmitBranchToAt(void *At, void *To, bool isCall) {
+   //FIXME
+   assert(0);
+ }
+ 
+ void AlphaJITInfo::replaceMachineCodeForFunction(void *Old, void *New) {
+   //FIXME
+   assert(0);
+ }
+ 
+ static TargetJITInfo::JITCompilerFn JITCompilerFunction;
+ //static AlphaJITInfo* AlphaJTI;
+ 
+ extern "C" {
+ #if 0
+ 
+   void AlphaCompilationCallbackC(long* oldsp)
+   {
+     void* CameFromStub = (void*)*(oldsp - 1);
+     void* CameFromOrig = (void*)*(oldsp - 2);
+ 
+     void* Target = JITCompilerFunction(CameFromStub);
+     
+     //rewrite the stub to an unconditional branch
+     EmitBranchToAt(CameFromStub, Target, false);
+ 
+     //Change pv to new Target
+     *(oldsp - 1) = (long)Target;
+ 
+     //special epilog
+     register long* RSP asm ("$0") = oldsp;
+     __asm__ __volatile__ (
+       "ldq $16,   0($0)\n"
+       "ldq $17,   8($0)\n"
+       "ldq $18,  16($0)\n"
+       "ldq $19,  24($0)\n"
+       "ldq $20,  32($0)\n"
+       "ldq $21,  40($0)\n"
+       "ldt $f16, 48($0)\n"
+       "ldt $f17, 56($0)\n"
+       "ldt $f18, 64($0)\n"
+       "ldt $f19, 72($0)\n"
+       "ldt $f20, 80($0)\n"
+       "ldt $f21, 88($0)\n"
+       "ldq $9,   96($0)\n"
+       "ldq $10, 104($0)\n"
+       "ldq $11, 112($0)\n"
+       "ldq $12, 120($0)\n"
+       "ldq $13, 128($0)\n"
+       "ldq $14, 136($0)\n"
+       "ldt $f2, 144($0)\n"
+       "ldt $f3, 152($0)\n"
+       "ldt $f4, 160($0)\n"
+       "ldt $f5, 168($0)\n"
+       "ldt $f6, 176($0)\n"
+       "ldt $f7, 184($0)\n"
+       "ldt $f8, 192($0)\n"
+       "ldt $f9, 200($0)\n"
+       "ldq $15, 208($0)\n"
+       "ldq $26, 216($0)\n"
+       "ldq $27, 224($0)\n"
+       "bis $30, $0, $0\n" //restore sp
+       "jmp $31, ($27)\n" //jump to the new function
+       "and $0, $31, $31\n" //dummy use of r0
+     );
+   }
+ 
+   void AlphaCompilationCallback(void);
+ 
+   asm(
+       ".text\n"
+       ".globl AlphaComilationCallbackC\n"
+       ".align 4\n"
+       ".globl AlphaCompilationCallback\n"
+       ".ent AlphaCompilationCallback\n"
+ "AlphaCompilationCallback:\n"
+       //      //get JIT's GOT
+       //      "ldgp\n"
+       //Save args, callee saved, and perhaps others?
+       //args: $16-$21 $f16-$f21     (12)
+       //callee: $9-$14 $f2-$f9      (14)
+       //others: fp:$15 ra:$26 pv:$27 (3)
+       "bis $0, $30, $30\n" //0 = sp
+       "lda $30, -232($30)\n"
+       "stq $16,   0($30)\n"
+       "stq $17,   8($30)\n"
+       "stq $18,  16($30)\n"
+       "stq $19,  24($30)\n"
+       "stq $20,  32($30)\n"
+       "stq $21,  40($30)\n"
+       "stt $f16, 48($30)\n"
+       "stt $f17, 56($30)\n"
+       "stt $f18, 64($30)\n"
+       "stt $f19, 72($30)\n"
+       "stt $f20, 80($30)\n"
+       "stt $f21, 88($30)\n"
+       "stq $9,   96($30)\n"
+       "stq $10, 104($30)\n"
+       "stq $11, 112($30)\n"
+       "stq $12, 120($30)\n"
+       "stq $13, 128($30)\n"
+       "stq $14, 136($30)\n"
+       "stt $f2, 144($30)\n"
+       "stt $f3, 152($30)\n"
+       "stt $f4, 160($30)\n"
+       "stt $f5, 168($30)\n"
+       "stt $f6, 176($30)\n"
+       "stt $f7, 184($30)\n"
+       "stt $f8, 192($30)\n"
+       "stt $f9, 200($30)\n"
+       "stq $15, 208($30)\n"
+       "stq $26, 216($30)\n"
+       "stq $27, 224($30)\n"
+       "bis $16, $0, $0\n" //pass the old sp as the first arg
+       "bsr $31, AlphaCompilationCallbackC\n"
+       ".end AlphaCompilationCallback\n"
+       );
+ #else
+   void AlphaCompilationCallback() {
+     std::cerr << "Cannot call AlphaCompilationCallback() on a non-Alpha arch!\n";
+     abort();
+   }
+ #endif
+ }
+ 
+ void *AlphaJITInfo::emitFunctionStub(void *Fn, MachineCodeEmitter &MCE) {
+ //   // If this is just a call to an external function, emit a branch instead of a
+ //   // call.  This means looking up Fn and storing that in R27 so as to appear to
+ //   // have called there originally
+ //   if (Fn != AlphaCompilationCallback) {
+ //     int idx = AlphaJTI->getNewGOTEntry(Fn);
+ //     //R27 = ldq idx(R29)
+ //     //R31 = JMP R27, 0
+ //     MCE.startFunctionStub(2*4);
+ //     void *Addr = (void*)(intptr_t)MCE.getCurrentPCValue();
+ //     MCE.emitWord(BUILD_LDQ(27, 29, idx << 3));
+ //     MCE.emitWord(BUILD_JMP(31, 27, 0));
+ //     return MCE.finishFunctionStub(0);
+ //   }
+ 
+   assert(0 && "Need to be able to jump to this guy too");
+ }
+ 
+ TargetJITInfo::LazyResolverFn
+ AlphaJITInfo::getLazyResolverFunction(JITCompilerFn F) {
+   JITCompilerFunction = F;
+   //  setZerothGOTEntry((void*)AlphaCompilationCallback);
+   return AlphaCompilationCallback;
+ }
+ 
+ //These describe LDAx
+ static const int IMM_LOW  = -32768;
+ static const int IMM_HIGH = 32767;
+ static const int IMM_MULT = 65536;
+ 
+ static long getUpper16(long l)
+ {
+   long y = l / IMM_MULT;
+   if (l % IMM_MULT > IMM_HIGH)
+     ++y;
+   if (l % IMM_MULT < IMM_LOW)
+     --y;
+   assert((short)y == y && "displacement out of range");
+   return y;
+ }
+ 
+ static long getLower16(long l)
+ {
+   long h = getUpper16(l);
+   long y = l - h * IMM_MULT;
+   assert(y == (short)y && "Displacement out of range");
+   return y;
+ }
+ 
+ void AlphaJITInfo::relocate(void *Function, MachineRelocation *MR,
+                             unsigned NumRelocs, unsigned char* GOTBase) {
+   //because gpdist are paired and relative to the pc of the first inst,
+   //we need to have some state
+ 
+   static map<pair<void*, int>, void*> gpdistmap;
+ 
+   for (unsigned i = 0; i != NumRelocs; ++i, ++MR) {
+     unsigned *RelocPos = (unsigned*)Function + MR->getMachineCodeOffset()/4;
+     long idx = 0;
+     switch ((Alpha::RelocationType)MR->getRelocationType()) {
+     default: assert(0 && "Unknown relocation type!");
+     case Alpha::reloc_literal:
+       //This is a LDQl
+       idx = MR->getGOTIndex();
+       DEBUG(std::cerr << "Literal relocation to slot " << idx);
+       idx = (idx - GOToffset) * 8;
+       DEBUG(std::cerr << " offset " << idx << "\n");
+       break;
+     case Alpha::reloc_gprellow:
+       idx = (unsigned char*)MR->getResultPointer() - &GOTBase[GOToffset * 8];
+       idx = getLower16(idx);
+       DEBUG(std::cerr << "gprellow relocation offset " << idx << "\n");
+       DEBUG(std::cerr << " Pointer is " << (void*)MR->getResultPointer()
+             << " GOT is " << (void*)&GOTBase[GOToffset * 8] << "\n");
+       break;
+     case Alpha::reloc_gprelhigh:
+       idx = (unsigned char*)MR->getResultPointer() - &GOTBase[GOToffset * 8];
+       idx = getUpper16(idx);
+       DEBUG(std::cerr << "gprelhigh relocation offset " << idx << "\n");
+       DEBUG(std::cerr << " Pointer is " << (void*)MR->getResultPointer()
+             << " GOT is " << (void*)&GOTBase[GOToffset * 8] << "\n");
+       break;
+     case Alpha::reloc_gpdist:
+       switch (*RelocPos >> 26) {
+       case 0x09: //LDAH
+         idx = &GOTBase[GOToffset * 8] - (unsigned char*)RelocPos;
+         idx = getUpper16(idx);
+         DEBUG(std::cerr << "LDAH: " << idx << "\n");
+         //add the relocation to the map
+         gpdistmap[make_pair(Function, MR->getConstantVal())] = RelocPos;
+         break;
+       case 0x08: //LDA
+         assert(gpdistmap[make_pair(Function, MR->getConstantVal())] &&
+                "LDAg without seeing LDAHg");
+         idx = &GOTBase[GOToffset * 8] - 
+           (unsigned char*)gpdistmap[make_pair(Function, MR->getConstantVal())];
+         idx = getLower16(idx);
+         DEBUG(std::cerr << "LDA: " << idx << "\n");
+         break;
+       default:
+         assert(0 && "Cannot handle gpdist yet");
+       }
+       break;
+     }
+     short x = (short)idx;
+     assert(x == idx);
+     *(short*)RelocPos = x;
+   }
+ }


Index: llvm/lib/Target/Alpha/AlphaJITInfo.h
diff -c /dev/null llvm/lib/Target/Alpha/AlphaJITInfo.h:1.1
*** /dev/null	Fri Jul 22 15:52:27 2005
--- llvm/lib/Target/Alpha/AlphaJITInfo.h	Fri Jul 22 15:52:16 2005
***************
*** 0 ****
--- 1,56 ----
+ //===- AlphaJITInfo.h - Alpha impl. of the JIT interface ----*- C++ -*-===//
+ //
+ //                     The LLVM Compiler Infrastructure
+ //
+ // This file was developed by the LLVM research group and is distributed under
+ // the University of Illinois Open Source License. See LICENSE.TXT for details.
+ //
+ //===----------------------------------------------------------------------===//
+ //
+ // This file contains the Alpha implementation of the TargetJITInfo class.
+ //
+ //===----------------------------------------------------------------------===//
+ 
+ #ifndef ALPHA_JITINFO_H
+ #define ALPHA_JITINFO_H
+ 
+ #include "llvm/Target/TargetJITInfo.h"
+ #include "llvm/GlobalValue.h"
+ #include <string>
+ #include <map>
+ 
+ namespace llvm {
+   class TargetMachine;
+ 
+   class AlphaJITInfo : public TargetJITInfo {
+   protected:
+     TargetMachine &TM;
+   public:
+     AlphaJITInfo(TargetMachine &tm) : TM(tm)
+     { useGOT = true; }
+ 
+     /// addPassesToJITCompile - Add passes to the specified pass manager to
+     /// implement a fast dynamic compiler for this target.  Return true if this
+     /// is not supported for this target.
+     ///
+     virtual void addPassesToJITCompile(FunctionPassManager &PM);
+ 
+     virtual void *emitFunctionStub(void *Fn, MachineCodeEmitter &MCE);
+     virtual LazyResolverFn getLazyResolverFunction(JITCompilerFn);
+     virtual void relocate(void *Function, MachineRelocation *MR,
+                           unsigned NumRelocs, unsigned char* GOTBase);
+ 
+     /// replaceMachineCodeForFunction - Make it so that calling the function
+     /// whose machine code is at OLD turns into a call to NEW, perhaps by
+     /// overwriting OLD with a branch to NEW.  This is used for self-modifying
+     /// code.
+     ///
+     virtual void replaceMachineCodeForFunction(void *Old, void *New);
+ 
+   private:
+     static const unsigned GOToffset = 4096;
+ 
+   };
+ }
+ 
+ #endif


Index: llvm/lib/Target/Alpha/AlphaRelocations.h
diff -c /dev/null llvm/lib/Target/Alpha/AlphaRelocations.h:1.1
*** /dev/null	Fri Jul 22 15:52:27 2005
--- llvm/lib/Target/Alpha/AlphaRelocations.h	Fri Jul 22 15:52:16 2005
***************
*** 0 ****
--- 1,30 ----
+ //===- AlphaRelocations.h - Alpha Code Relocations --------------*- C++ -*-===//
+ //
+ //                     The LLVM Compiler Infrastructure
+ //
+ // This file was developed by the LLVM research group and is distributed under
+ // the University of Illinois Open Source License. See LICENSE.TXT for details.
+ //
+ //===----------------------------------------------------------------------===//
+ //
+ // This file defines the Alpha target-specific relocation types.
+ //
+ //===----------------------------------------------------------------------===//
+ 
+ #ifndef ALPHARELOCATIONS_H
+ #define ALPHARELOCATIONS_H
+ 
+ #include "llvm/CodeGen/MachineRelocation.h"
+ 
+ namespace llvm {
+   namespace Alpha {
+     enum RelocationType {
+       reloc_literal,
+       reloc_gprellow,
+       reloc_gprelhigh,
+       reloc_gpdist,
+     };
+   }
+ }
+ 
+ #endif


Index: llvm/lib/Target/Alpha/Alpha.h
diff -u llvm/lib/Target/Alpha/Alpha.h:1.3 llvm/lib/Target/Alpha/Alpha.h:1.4
--- llvm/lib/Target/Alpha/Alpha.h:1.3	Thu Apr 21 18:10:23 2005
+++ llvm/lib/Target/Alpha/Alpha.h	Fri Jul 22 15:52:16 2005
@@ -21,12 +21,13 @@
 
   class FunctionPass;
   class TargetMachine;
+  class MachineCodeEmitter;
 
   FunctionPass *createAlphaSimpleInstructionSelector(TargetMachine &TM);
   FunctionPass *createAlphaCodePrinterPass(std::ostream &OS,
                                              TargetMachine &TM);
   FunctionPass *createAlphaPatternInstructionSelector(TargetMachine &TM);
-
+  FunctionPass *createAlphaCodeEmitterPass(MachineCodeEmitter &MCE);
 } // end namespace llvm;
 
 // Defines symbolic names for Alpha registers.  This defines a mapping from


Index: llvm/lib/Target/Alpha/AlphaAsmPrinter.cpp
diff -u llvm/lib/Target/Alpha/AlphaAsmPrinter.cpp:1.17 llvm/lib/Target/Alpha/AlphaAsmPrinter.cpp:1.18
--- llvm/lib/Target/Alpha/AlphaAsmPrinter.cpp:1.17	Mon Jun 27 11:29:54 2005
+++ llvm/lib/Target/Alpha/AlphaAsmPrinter.cpp	Fri Jul 22 15:52:16 2005
@@ -239,6 +239,7 @@
     O << "\t.arch ev6\n";
   else
     O << "\t.arch ev56\n";
+  O << "\t.set noat\n";
   return false;
 }
 


Index: llvm/lib/Target/Alpha/AlphaRegisterInfo.cpp
diff -u llvm/lib/Target/Alpha/AlphaRegisterInfo.cpp:1.24 llvm/lib/Target/Alpha/AlphaRegisterInfo.cpp:1.25
--- llvm/lib/Target/Alpha/AlphaRegisterInfo.cpp:1.24	Thu Jul  7 14:52:58 2005
+++ llvm/lib/Target/Alpha/AlphaRegisterInfo.cpp	Fri Jul 22 15:52:16 2005
@@ -226,8 +226,16 @@
   MachineFrameInfo *MFI = MF.getFrameInfo();
   bool FP = hasFP(MF);
 
+  static int curgpdist = 0;
+
   //handle GOP offset
-  BuildMI(MBB, MBBI, Alpha::LDGP, 0);
+  BuildMI(MBB, MBBI, Alpha::LDAHg, 3, Alpha::R29)
+    .addGlobalAddress(const_cast<Function*>(MF.getFunction()))
+    .addReg(Alpha::R27).addImm(++curgpdist);
+  BuildMI(MBB, MBBI, Alpha::LDAg, 3, Alpha::R29)
+    .addGlobalAddress(const_cast<Function*>(MF.getFunction()))
+    .addReg(Alpha::R29).addImm(curgpdist);
+
   //evil const_cast until MO stuff setup to handle const
   BuildMI(MBB, MBBI, Alpha::ALTENT, 1).addGlobalAddress(const_cast<Function*>(MF.getFunction()), true);
 


Index: llvm/lib/Target/Alpha/AlphaTargetMachine.cpp
diff -u llvm/lib/Target/Alpha/AlphaTargetMachine.cpp:1.8 llvm/lib/Target/Alpha/AlphaTargetMachine.cpp:1.9
--- llvm/lib/Target/Alpha/AlphaTargetMachine.cpp:1.8	Fri Jun 24 21:48:34 2005
+++ llvm/lib/Target/Alpha/AlphaTargetMachine.cpp	Fri Jul 22 15:52:16 2005
@@ -11,6 +11,7 @@
 //===----------------------------------------------------------------------===//
 
 #include "Alpha.h"
+#include "AlphaJITInfo.h"
 #include "AlphaTargetMachine.h"
 #include "llvm/Module.h"
 #include "llvm/CodeGen/Passes.h"
@@ -49,9 +50,18 @@
   return 0;
 }
 
+unsigned AlphaTargetMachine::getJITMatchQuality() {
+#if 0
+  return 10;
+#else
+  return 0;
+#endif
+}
+
 AlphaTargetMachine::AlphaTargetMachine( const Module &M, IntrinsicLowering *IL)
   : TargetMachine("alpha", IL, true),
-    FrameInfo(TargetFrameInfo::StackGrowsDown, 8, 0) //TODO: check these
+    FrameInfo(TargetFrameInfo::StackGrowsDown, 8, 0), //TODO: check these
+    JITInfo(*this)
 {}
 
 /// addPassesToEmitFile - Add passes to the specified pass manager to implement
@@ -99,3 +109,47 @@
   PM.add(createMachineCodeDeleter());
   return false;
 }
+
+void AlphaJITInfo::addPassesToJITCompile(FunctionPassManager &PM) {
+
+  if (EnableAlphaLSR) {
+    PM.add(createLoopStrengthReducePass());
+    PM.add(createCFGSimplificationPass());
+  }
+
+  // FIXME: Implement efficient support for garbage collection intrinsics.
+  PM.add(createLowerGCPass());
+
+  // FIXME: Implement the invoke/unwind instructions!
+  PM.add(createLowerInvokePass());
+
+  // FIXME: Implement the switch instruction in the instruction selector!
+  PM.add(createLowerSwitchPass());
+
+  // Make sure that no unreachable blocks are instruction selected.
+  PM.add(createUnreachableBlockEliminationPass());
+
+  PM.add(createAlphaPatternInstructionSelector(TM));
+
+  if (PrintMachineCode)
+    PM.add(createMachineFunctionPrinterPass(&std::cerr));
+
+  PM.add(createRegisterAllocator());
+
+  if (PrintMachineCode)
+    PM.add(createMachineFunctionPrinterPass(&std::cerr));
+
+  PM.add(createPrologEpilogCodeInserter());
+
+  // Must run branch selection immediately preceding the asm printer
+  //PM.add(createAlphaBranchSelectionPass());
+
+}
+
+bool AlphaTargetMachine::addPassesToEmitMachineCode(FunctionPassManager &PM,
+                                                    MachineCodeEmitter &MCE) {
+  PM.add(createAlphaCodeEmitterPass(MCE));
+  // Delete machine code for this function
+  PM.add(createMachineCodeDeleter());
+  return false;
+}


Index: llvm/lib/Target/Alpha/AlphaTargetMachine.h
diff -u llvm/lib/Target/Alpha/AlphaTargetMachine.h:1.7 llvm/lib/Target/Alpha/AlphaTargetMachine.h:1.8
--- llvm/lib/Target/Alpha/AlphaTargetMachine.h:1.7	Fri Jun 24 21:48:34 2005
+++ llvm/lib/Target/Alpha/AlphaTargetMachine.h	Fri Jul 22 15:52:16 2005
@@ -18,6 +18,7 @@
 #include "llvm/Target/TargetFrameInfo.h"
 #include "llvm/PassManager.h"
 #include "AlphaInstrInfo.h"
+#include "AlphaJITInfo.h"
 
 namespace llvm {
 
@@ -27,6 +28,7 @@
 class AlphaTargetMachine : public TargetMachine {
   AlphaInstrInfo InstrInfo;
   TargetFrameInfo FrameInfo;
+  AlphaJITInfo JITInfo;
 
 public:
   AlphaTargetMachine(const Module &M, IntrinsicLowering *IL);
@@ -36,6 +38,20 @@
   virtual const MRegisterInfo *getRegisterInfo() const {
     return &InstrInfo.getRegisterInfo();
   }
+  virtual TargetJITInfo* getJITInfo() {
+    return &JITInfo;
+  }
+
+  static unsigned getJITMatchQuality();
+
+  /// addPassesToEmitMachineCode - Add passes to the specified pass manager to
+  /// get machine code emitted.  This uses a MachineCodeEmitter object to handle
+  /// actually outputting the machine code and resolving things like the address
+  /// of functions.  This method should returns true if machine code emission is
+  /// not supported.
+  ///
+  virtual bool addPassesToEmitMachineCode(FunctionPassManager &PM,
+                                          MachineCodeEmitter &MCE);
 
   virtual bool addPassesToEmitFile(PassManager &PM, std::ostream &Out,
                                    CodeGenFileType FileType);





From alenhar2 at cs.uiuc.edu  Fri Jul 22 15:54:13 2005
From: alenhar2 at cs.uiuc.edu (Andrew Lenharth)
Date: Fri, 22 Jul 2005 15:54:13 -0500
Subject: [llvm-commits] CVS: llvm/configure Makefile.rules 
Message-ID: <200507222054.PAA04039@zion.cs.uiuc.edu>



Changes in directory llvm:

configure updated: 1.195 -> 1.196
Makefile.rules updated: 1.314 -> 1.315
---
Log message:

Alpha has JIT

---
Diffs of the changes:  (+13 -1)

 Makefile.rules |   12 ++++++++++++
 configure      |    2 +-
 2 files changed, 13 insertions(+), 1 deletion(-)


Index: llvm/configure
diff -u llvm/configure:1.195 llvm/configure:1.196
--- llvm/configure:1.195	Thu Jul 14 00:19:12 2005
+++ llvm/configure	Fri Jul 22 15:54:00 2005
@@ -2997,7 +2997,7 @@
  ;;
     x86_64)  JIT=
  ;;
-    Alpha)   JIT=
+    Alpha)   JIT=TARGET_HAS_JIT=1
  ;;
     IA64)    JIT=
  ;;


Index: llvm/Makefile.rules
diff -u llvm/Makefile.rules:1.314 llvm/Makefile.rules:1.315
--- llvm/Makefile.rules:1.314	Mon May 23 21:33:20 2005
+++ llvm/Makefile.rules	Fri Jul 22 15:54:01 2005
@@ -602,6 +602,18 @@
   JIT_LIBS += LLVMPowerPC LLVMSelectionDAG
 endif
 
+# You can enable the Alpha JIT on a non-Alpha host by setting the flag
+# ENABLE_ALPHA_JIT on the make command line. If not, it will still be
+# enabled automagically on an PowerPC host.
+ifeq ($(ARCH), Alpha)
+  ENABLE_ALPHA_JIT = 1
+endif
+
+# What the PowerPC JIT requires
+ifdef ENABLE_ALPHA_JIT
+  JIT_LIBS += LLVMAlpha LLVMSelectionDAG
+endif
+
 LLVMLIBS := $(JIT_LIBS) LLVMScalarOpts LLVMAnalysis.a LLVMTransformUtils.a \
             LLVMBCReader LLVMCore LLVMSupport.a LLVMTarget.a LLVMbzip2 \
             LLVMSystem.a $(PLATFORMLIBDL)





From alenhar2 at cs.uiuc.edu  Fri Jul 22 15:54:13 2005
From: alenhar2 at cs.uiuc.edu (Andrew Lenharth)
Date: Fri, 22 Jul 2005 15:54:13 -0500
Subject: [llvm-commits] CVS: llvm/autoconf/configure.ac 
Message-ID: <200507222054.PAA04033@zion.cs.uiuc.edu>



Changes in directory llvm/autoconf:

configure.ac updated: 1.191 -> 1.192
---
Log message:

Alpha has JIT

---
Diffs of the changes:  (+1 -1)

 configure.ac |    2 +-
 1 files changed, 1 insertion(+), 1 deletion(-)


Index: llvm/autoconf/configure.ac
diff -u llvm/autoconf/configure.ac:1.191 llvm/autoconf/configure.ac:1.192
--- llvm/autoconf/configure.ac:1.191	Thu Jul 14 00:19:12 2005
+++ llvm/autoconf/configure.ac	Fri Jul 22 15:54:01 2005
@@ -212,7 +212,7 @@
     Sparc)   AC_SUBST(JIT,[[TARGET_HAS_JIT=1]]) ;;
     PowerPC) AC_SUBST(JIT,[[TARGET_HAS_JIT=1]]) ;;
     x86_64)  AC_SUBST(JIT,[[]]) ;;
-    Alpha)   AC_SUBST(JIT,[[]]) ;;
+    Alpha)   AC_SUBST(JIT,[[TARGET_HAS_JIT=1]]) ;;
     IA64)    AC_SUBST(JIT,[[]]) ;;
     *)       AC_SUBST(JIT,[[]]) ;;
   esac





From alenhar2 at cs.uiuc.edu  Fri Jul 22 16:00:41 2005
From: alenhar2 at cs.uiuc.edu (Andrew Lenharth)
Date: Fri, 22 Jul 2005 16:00:41 -0500
Subject: [llvm-commits] CVS: llvm/lib/Target/Alpha/AlphaJITInfo.cpp
	AlphaTargetMachine.cpp 
Message-ID: <200507222100.QAA04171@zion.cs.uiuc.edu>



Changes in directory llvm/lib/Target/Alpha:

AlphaJITInfo.cpp updated: 1.1 -> 1.2
AlphaTargetMachine.cpp updated: 1.9 -> 1.10
---
Log message:

finally found the gcc defined constants

---
Diffs of the changes:  (+2 -2)

 AlphaJITInfo.cpp       |    2 +-
 AlphaTargetMachine.cpp |    2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)


Index: llvm/lib/Target/Alpha/AlphaJITInfo.cpp
diff -u llvm/lib/Target/Alpha/AlphaJITInfo.cpp:1.1 llvm/lib/Target/Alpha/AlphaJITInfo.cpp:1.2
--- llvm/lib/Target/Alpha/AlphaJITInfo.cpp:1.1	Fri Jul 22 15:52:16 2005
+++ llvm/lib/Target/Alpha/AlphaJITInfo.cpp	Fri Jul 22 16:00:30 2005
@@ -51,7 +51,7 @@
 //static AlphaJITInfo* AlphaJTI;
 
 extern "C" {
-#if 0
+#ifdef __alpha
 
   void AlphaCompilationCallbackC(long* oldsp)
   {


Index: llvm/lib/Target/Alpha/AlphaTargetMachine.cpp
diff -u llvm/lib/Target/Alpha/AlphaTargetMachine.cpp:1.9 llvm/lib/Target/Alpha/AlphaTargetMachine.cpp:1.10
--- llvm/lib/Target/Alpha/AlphaTargetMachine.cpp:1.9	Fri Jul 22 15:52:16 2005
+++ llvm/lib/Target/Alpha/AlphaTargetMachine.cpp	Fri Jul 22 16:00:30 2005
@@ -51,7 +51,7 @@
 }
 
 unsigned AlphaTargetMachine::getJITMatchQuality() {
-#if 0
+#ifdef __alpha
   return 10;
 #else
   return 0;





From alenhar2 at cs.uiuc.edu  Fri Jul 22 16:53:47 2005
From: alenhar2 at cs.uiuc.edu (Andrew Lenharth)
Date: Fri, 22 Jul 2005 16:53:47 -0500
Subject: [llvm-commits] CVS: llvm/test/Regression/CodeGen/Alpha/i32_sub_1.ll
Message-ID: <200507222153.QAA04365@zion.cs.uiuc.edu>



Changes in directory llvm/test/Regression/CodeGen/Alpha:

i32_sub_1.ll added (r1.1)
---
Log message:

make sure we always handle small negatives well

---
Diffs of the changes:  (+10 -0)

 i32_sub_1.ll |   10 ++++++++++
 1 files changed, 10 insertions(+)


Index: llvm/test/Regression/CodeGen/Alpha/i32_sub_1.ll
diff -c /dev/null llvm/test/Regression/CodeGen/Alpha/i32_sub_1.ll:1.1
*** /dev/null	Fri Jul 22 16:53:45 2005
--- llvm/test/Regression/CodeGen/Alpha/i32_sub_1.ll	Fri Jul 22 16:53:35 2005
***************
*** 0 ****
--- 1,10 ----
+ ; Make sure this testcase codegens to the ctpop instruction
+ ; RUN: llvm-as < %s | llc -march=alpha | grep -i 'subl $16,1,$0'
+ 
+ implementation   ; Functions:
+ 
+ int %foo(int %x) {
+ entry:
+ 	%tmp.1 = add int %x, -1		; <int> [#uses=1]
+ 	ret int %tmp.1
+ }





From alenhar2 at cs.uiuc.edu  Fri Jul 22 17:00:35 2005
From: alenhar2 at cs.uiuc.edu (Andrew Lenharth)
Date: Fri, 22 Jul 2005 17:00:35 -0500
Subject: [llvm-commits] CVS: llvm/Makefile.rules 
Message-ID: <200507222200.RAA04425@zion.cs.uiuc.edu>



Changes in directory llvm:

Makefile.rules updated: 1.315 -> 1.316
---
Log message:

I know PowerPC wishes it could be alpha, but it cannot.  so there

---
Diffs of the changes:  (+1 -1)

 Makefile.rules |    2 +-
 1 files changed, 1 insertion(+), 1 deletion(-)


Index: llvm/Makefile.rules
diff -u llvm/Makefile.rules:1.315 llvm/Makefile.rules:1.316
--- llvm/Makefile.rules:1.315	Fri Jul 22 15:54:01 2005
+++ llvm/Makefile.rules	Fri Jul 22 17:00:24 2005
@@ -609,7 +609,7 @@
   ENABLE_ALPHA_JIT = 1
 endif
 
-# What the PowerPC JIT requires
+# What the Alpha JIT requires
 ifdef ENABLE_ALPHA_JIT
   JIT_LIBS += LLVMAlpha LLVMSelectionDAG
 endif





From alenhar2 at cs.uiuc.edu  Fri Jul 22 17:24:12 2005
From: alenhar2 at cs.uiuc.edu (Andrew Lenharth)
Date: Fri, 22 Jul 2005 17:24:12 -0500
Subject: [llvm-commits] CVS: llvm/lib/Target/Alpha/AlphaISelPattern.cpp 
Message-ID: <200507222224.RAA04586@zion.cs.uiuc.edu>



Changes in directory llvm/lib/Target/Alpha:

AlphaISelPattern.cpp updated: 1.152 -> 1.153
---
Log message:

Handle more imm forms, and load small negative i32 constants without hitting memory (should do the same for arbitrary zero extended small negative constants)

---
Diffs of the changes:  (+45 -2)

 AlphaISelPattern.cpp |   47 +++++++++++++++++++++++++++++++++++++++++++++--
 1 files changed, 45 insertions(+), 2 deletions(-)


Index: llvm/lib/Target/Alpha/AlphaISelPattern.cpp
diff -u llvm/lib/Target/Alpha/AlphaISelPattern.cpp:1.152 llvm/lib/Target/Alpha/AlphaISelPattern.cpp:1.153
--- llvm/lib/Target/Alpha/AlphaISelPattern.cpp:1.152	Fri Jul 22 15:50:29 2005
+++ llvm/lib/Target/Alpha/AlphaISelPattern.cpp	Fri Jul 22 17:24:01 2005
@@ -1493,6 +1493,19 @@
               Tmp2 = cast<ConstantSDNode>(N.getOperand(0).getOperand(1))->getValue();
               BuildMI(BB, Opc, 2, Result).addReg(Tmp1).addImm(Tmp2);
             }
+            else if(N.getOperand(0).getOperand(1).getOpcode() == ISD::Constant &&
+                    !isMul &&
+                    (CSD = dyn_cast<ConstantSDNode>(N.getOperand(0).getOperand(1))) &&
+                    (((int64_t)(CSD->getValue() << 32) >> 32) >= -255) &&
+                    (((int64_t)(CSD->getValue() << 32) >> 32) <= 0))
+            { //handle canonicalization
+              Opc = isAdd ? Alpha::SUBLi : Alpha::ADDLi;
+              Tmp1 = SelectExpr(N.getOperand(0).getOperand(0));
+              int64_t t = cast<ConstantSDNode>(N.getOperand(0).getOperand(1))->getValue();
+              t = 0 - ((t << 32) >> 32);
+              assert(t >= 0 && t <= 255);
+              BuildMI(BB, Opc, 2, Result).addReg(Tmp1).addImm(t);
+            }
             else
             { //Normal add/sub
               Opc = isAdd ? Alpha::ADDL : (isMul ? Alpha::MULL : Alpha::SUBL);
@@ -1792,6 +1805,14 @@
         Tmp1 = SelectExpr(N.getOperand(0));
         BuildMI(BB, Opc, 2, Result).addReg(Tmp1).addImm(CSD->getValue());
       }
+      else if((CSD = dyn_cast<ConstantSDNode>(N.getOperand(1))) &&
+              (int64_t)CSD->getValue() >= 255 &&
+              (int64_t)CSD->getValue() <= 0)              
+      { //inverted imm add/sub
+        Opc = isAdd ? Alpha::SUBQi : Alpha::ADDQi;
+        Tmp1 = SelectExpr(N.getOperand(0));
+        BuildMI(BB, Opc, 2, Result).addReg(Tmp1).addImm((int64_t)CSD->getValue());
+      }
       //larger addi
       else if((CSD = dyn_cast<ConstantSDNode>(N.getOperand(1))) &&
               CSD->getSignExtended() <= 32767 &&
@@ -2061,17 +2082,39 @@
   case ISD::Constant:
     {
       int64_t val = (int64_t)cast<ConstantSDNode>(N)->getValue();
+      int zero_extend_top = 0;
+      if (val > 0 && (val & 0xFFFFFFFF00000000) == 0 &&
+          ((int32_t)val < 0)) {
+        //try a small load and zero extend
+        val = (int32_t)val;
+        zero_extend_top = 15;
+      }
+
       if (val <= IMM_HIGH && val >= IMM_LOW) {
-        BuildMI(BB, Alpha::LDA, 2, Result).addImm(val).addReg(Alpha::R31);
+        if(!zero_extend_top)
+          BuildMI(BB, Alpha::LDA, 2, Result).addImm(val).addReg(Alpha::R31);
+        else {
+          Tmp1 = MakeReg(MVT::i64);
+          BuildMI(BB, Alpha::LDA, 2, Tmp1).addImm(val).addReg(Alpha::R31);
+          BuildMI(BB, Alpha::ZAPNOT, 2, Result).addReg(Tmp1).addImm(zero_extend_top);
+        }
       }
       else if (val <= (int64_t)IMM_HIGH +(int64_t)IMM_HIGH* (int64_t)IMM_MULT &&
                val >= (int64_t)IMM_LOW + (int64_t)IMM_LOW * (int64_t)IMM_MULT) {
         Tmp1 = MakeReg(MVT::i64);
         BuildMI(BB, Alpha::LDAH, 2, Tmp1).addImm(getUpper16(val))
           .addReg(Alpha::R31);
-        BuildMI(BB, Alpha::LDA, 2, Result).addImm(getLower16(val)).addReg(Tmp1);
+        if (!zero_extend_top)
+          BuildMI(BB, Alpha::LDA, 2, Result).addImm(getLower16(val)).addReg(Tmp1);
+        else {
+          Tmp3 = MakeReg(MVT::i64);
+          BuildMI(BB, Alpha::LDA, 2, Tmp3).addImm(getLower16(val)).addReg(Tmp1);
+          BuildMI(BB, Alpha::ZAPNOT, 2, Result).addReg(Tmp3).addImm(zero_extend_top);
+        }
       }
       else {
+        //re-get the val since we are going to mem anyway
+        val = (int64_t)cast<ConstantSDNode>(N)->getValue();
         MachineConstantPool *CP = BB->getParent()->getConstantPool();
         ConstantUInt *C = 
           ConstantUInt::get(Type::getPrimitiveType(Type::ULongTyID) , val);





From brukman at cs.uiuc.edu  Fri Jul 22 17:43:51 2005
From: brukman at cs.uiuc.edu (Misha Brukman)
Date: Fri, 22 Jul 2005 17:43:51 -0500
Subject: [llvm-commits] CVS: llvm/Makefile.rules 
Message-ID: <200507222243.RAA04730@zion.cs.uiuc.edu>



Changes in directory llvm:

Makefile.rules updated: 1.316 -> 1.317
---
Log message:

No, really, it's an Alpha!  And you probably thought it was a PowerPC.


---
Diffs of the changes:  (+1 -1)

 Makefile.rules |    2 +-
 1 files changed, 1 insertion(+), 1 deletion(-)


Index: llvm/Makefile.rules
diff -u llvm/Makefile.rules:1.316 llvm/Makefile.rules:1.317
--- llvm/Makefile.rules:1.316	Fri Jul 22 17:00:24 2005
+++ llvm/Makefile.rules	Fri Jul 22 17:43:40 2005
@@ -604,7 +604,7 @@
 
 # You can enable the Alpha JIT on a non-Alpha host by setting the flag
 # ENABLE_ALPHA_JIT on the make command line. If not, it will still be
-# enabled automagically on an PowerPC host.
+# enabled automagically on an Alpha host.
 ifeq ($(ARCH), Alpha)
   ENABLE_ALPHA_JIT = 1
 endif





From lattner at cs.uiuc.edu  Fri Jul 22 17:58:45 2005
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Fri, 22 Jul 2005 17:58:45 -0500
Subject: [llvm-commits] CVS: llvm/lib/Target/PowerPC/PPC32ISelPattern.cpp 
Message-ID: <200507222258.RAA04860@zion.cs.uiuc.edu>



Changes in directory llvm/lib/Target/PowerPC:

PPC32ISelPattern.cpp updated: 1.102 -> 1.103
---
Log message:

PowerPC no-pic code is not quite ready for prime-time


---
Diffs of the changes:  (+1 -0)

 PPC32ISelPattern.cpp |    1 +
 1 files changed, 1 insertion(+)


Index: llvm/lib/Target/PowerPC/PPC32ISelPattern.cpp
diff -u llvm/lib/Target/PowerPC/PPC32ISelPattern.cpp:1.102 llvm/lib/Target/PowerPC/PPC32ISelPattern.cpp:1.103
--- llvm/lib/Target/PowerPC/PPC32ISelPattern.cpp:1.102	Thu Jul 21 15:44:42 2005
+++ llvm/lib/Target/PowerPC/PPC32ISelPattern.cpp	Fri Jul 22 17:58:34 2005
@@ -45,6 +45,7 @@
     PPC32TargetLowering(TargetMachine &TM) : TargetLowering(TM) {
       // Fold away setcc operations if possible.
       setSetCCIsExpensive();
+      PICEnabled = true;
 
       // Set up the register classes.
       addRegisterClass(MVT::i32, PPC32::GPRCRegisterClass);





From alenhar2 at cs.uiuc.edu  Sat Jul 23 02:46:59 2005
From: alenhar2 at cs.uiuc.edu (Andrew Lenharth)
Date: Sat, 23 Jul 2005 02:46:59 -0500
Subject: [llvm-commits] CVS: llvm/lib/Target/Alpha/AlphaISelPattern.cpp 
Message-ID: <200507230746.CAA06679@zion.cs.uiuc.edu>



Changes in directory llvm/lib/Target/Alpha:

AlphaISelPattern.cpp updated: 1.153 -> 1.154
---
Log message:

fix compile error

---
Diffs of the changes:  (+1 -1)

 AlphaISelPattern.cpp |    2 +-
 1 files changed, 1 insertion(+), 1 deletion(-)


Index: llvm/lib/Target/Alpha/AlphaISelPattern.cpp
diff -u llvm/lib/Target/Alpha/AlphaISelPattern.cpp:1.153 llvm/lib/Target/Alpha/AlphaISelPattern.cpp:1.154
--- llvm/lib/Target/Alpha/AlphaISelPattern.cpp:1.153	Fri Jul 22 17:24:01 2005
+++ llvm/lib/Target/Alpha/AlphaISelPattern.cpp	Sat Jul 23 02:46:48 2005
@@ -2083,7 +2083,7 @@
     {
       int64_t val = (int64_t)cast<ConstantSDNode>(N)->getValue();
       int zero_extend_top = 0;
-      if (val > 0 && (val & 0xFFFFFFFF00000000) == 0 &&
+      if (val > 0 && (val & 0xFFFFFFFF00000000ULL) == 0 &&
           ((int32_t)val < 0)) {
         //try a small load and zero extend
         val = (int32_t)val;