From reid at x10sys.com Mon Jul 25 15:25:19 2005 From: reid at x10sys.com (Reid Spencer) Date: Mon, 25 Jul 2005 15:25:19 -0500 Subject: [llvm-commits] CVS: llvm/autoconf/m4/find_std_program.m4 Message-ID: <200507252025.PAA19731@zion.cs.uiuc.edu> Changes in directory llvm/autoconf/m4: find_std_program.m4 updated: 1.2 -> 1.3 --- Log message: Get rid of bash specific syntax for variable dereferencing, replacing it with the more crufty (but more widely available) "eval" command. --- Diffs of the changes: (+22 -22) find_std_program.m4 | 44 ++++++++++++++++++++++---------------------- 1 files changed, 22 insertions(+), 22 deletions(-) Index: llvm/autoconf/m4/find_std_program.m4 diff -u llvm/autoconf/m4/find_std_program.m4:1.2 llvm/autoconf/m4/find_std_program.m4:1.3 --- llvm/autoconf/m4/find_std_program.m4:1.2 Sun Jul 17 00:30:33 2005 +++ llvm/autoconf/m4/find_std_program.m4 Mon Jul 25 15:25:08 2005 @@ -48,22 +48,22 @@ AS_HELP_STRING([--with-]stdprog_long_name()[-inc=DIR], [Specify that the ]stdprog_long_name()[ includes are in DIR]), $1[incdir=$withval],$1[incdir=nada]) -pfxvar=$1pfxdir -binvar=$1bindir -incvar=$1incdir -libvar=$1libdir -if test "${!pfxvar}" != "nada" ; then - CHECK_STD_PROGRAM(${!pfxvar},$1,$2,$3) -elif test "${!binvar}" != "nada" ; then - if test "${!libvar}" != "nada" ; then - if test "${!incvar}" != "nada" ; then - if test -d "${!binvar}" ; then - if test -d "${!incvar}" ; then - if test -d "${!libvar}" ; then - AC_SUBST(allcapsname(),${!binvar}/$1) - AC_SUBST(allcapsname()[_BIN],${!binvar}) - AC_SUBST(allcapsname()[_INC],${!incvar}) - AC_SUBST(allcapsname()[_LIB],${!libvar}) +eval pfxval=\$\{$1pfxdir\} +eval binval=\$\{$1bindir\} +eval incval=\$\{$1incdir\} +eval libvar=\$\{$1libdir\} +if test "${pfxval}" != "nada" ; then + CHECK_STD_PROGRAM(${pfxval},$1,$2,$3) +elif test "${binval}" != "nada" ; then + if test "${libval}" != "nada" ; then + if test "${incval}" != "nada" ; then + if test -d "${binval}" ; then + if test -d "${incval}" ; then + if test -d "${libval}" ; then + AC_SUBST(allcapsname(),${binval}/$1) + AC_SUBST(allcapsname()[_BIN],${binval}) + AC_SUBST(allcapsname()[_INC],${incval}) + AC_SUBST(allcapsname()[_LIB],${libval}) AC_SUBST([USE_]allcapsname(),[1]) AC_MSG_RESULT([found via --with options]) else @@ -95,17 +95,17 @@ AC_MSG_RESULT([found in PATH at ]$tmppfxdir) else checkresult="yes" - checkvar="USE_"allcapsname() + eval checkval=\$\{"USE_"allcapsname()\} CHECK_STD_PROGRAM([/usr],$1,$2,$3) - if test -z "${!checkvar}" ; then + if test -z "${checkval}" ; then CHECK_STD_PROGRAM([/usr/local],$1,$2,$3) - if test -z "${!checkvar}" ; then + if test -z "${checkval}" ; then CHECK_STD_PROGRAM([/sw],$1,$2,$3) - if test -z "${!checkvar}" ; then + if test -z "${checkval}" ; then CHECK_STD_PROGRAM([/opt],$1,$2,$3) - if test -z "${!checkvar}" ; then + if test -z "${checkval}" ; then CHECK_STD_PROGRAM([/],$1,$2,$3) - if test -z "${!checkvar}" ; then + if test -z "${checkval}" ; then checkresult="no" fi fi From reid at x10sys.com Mon Jul 25 15:30:46 2005 From: reid at x10sys.com (Reid Spencer) Date: Mon, 25 Jul 2005 15:30:46 -0500 Subject: [llvm-commits] CVS: llvm-test/MultiSource/Makefile.multisrc Message-ID: <200507252030.PAA19772@zion.cs.uiuc.edu> Changes in directory llvm-test/MultiSource: Makefile.multisrc updated: 1.47 -> 1.48 --- Log message: Make the configure script work on Solaris too, by removing bash specific shell syntax (from LLVM's find_std_program.m4 script). --- Diffs of the changes: (+1 -1) Makefile.multisrc | 2 +- 1 files changed, 1 insertion(+), 1 deletion(-) Index: llvm-test/MultiSource/Makefile.multisrc diff -u llvm-test/MultiSource/Makefile.multisrc:1.47 llvm-test/MultiSource/Makefile.multisrc:1.48 --- llvm-test/MultiSource/Makefile.multisrc:1.47 Sun May 15 14:47:13 2005 +++ llvm-test/MultiSource/Makefile.multisrc Mon Jul 25 15:30:35 2005 @@ -15,7 +15,7 @@ ## LLVM bytecode libraries that must be linked with an application # FIXME: LIBS SHOULD BE SPECIFIED -LIBS += -lm +LIBS += -lm -ldl include $(LEVEL)/Makefile.programs From reid at x10sys.com Mon Jul 25 15:30:47 2005 From: reid at x10sys.com (Reid Spencer) Date: Mon, 25 Jul 2005 15:30:47 -0500 Subject: [llvm-commits] CVS: llvm-test/configure Message-ID: <200507252030.PAA19776@zion.cs.uiuc.edu> Changes in directory llvm-test: configure updated: 1.26 -> 1.27 --- Log message: Make the configure script work on Solaris too, by removing bash specific shell syntax (from LLVM's find_std_program.m4 script). --- Diffs of the changes: (+58 -58) configure | 116 +++++++++++++++++++++++++++++++------------------------------- 1 files changed, 58 insertions(+), 58 deletions(-) Index: llvm-test/configure diff -u llvm-test/configure:1.26 llvm-test/configure:1.27 --- llvm-test/configure:1.26 Sun Jul 17 00:37:54 2005 +++ llvm-test/configure Mon Jul 25 15:30:35 2005 @@ -18793,44 +18793,44 @@ else f2cincdir=nada fi; -pfxvar=f2cpfxdir -binvar=f2cbindir -incvar=f2cincdir -libvar=f2clibdir -if test "${!pfxvar}" != "nada" ; then +eval pfxval=\$\{f2cpfxdir\} +eval binval=\$\{f2cbindir\} +eval incval=\$\{f2cincdir\} +eval libvar=\$\{f2clibdir\} +if test "${pfxval}" != "nada" ; then -if test -n "${!pfxvar}" -a -d "${!pfxvar}" -a -n "f2c" -a -d "${!pfxvar}/bin" -a -x "${!pfxvar}/bin/f2c" ; then +if test -n "${pfxval}" -a -d "${pfxval}" -a -n "f2c" -a -d "${pfxval}/bin" -a -x "${pfxval}/bin/f2c" ; then USE_F2C="USE_F2C = 1" - F2C=${!pfxvar}/bin/f2c + F2C=${pfxval}/bin/f2c - F2C_BIN=${!pfxvar}/bin + F2C_BIN=${pfxval}/bin - F2C_DIR=${!pfxvar} + F2C_DIR=${pfxval} - if test -n "f2c.h" -a -d "${!pfxvar}/include" -a -f "${!pfxvar}/include/f2c.h" ; then - F2C_INC=${!pfxvar}/include + if test -n "f2c.h" -a -d "${pfxval}/include" -a -f "${pfxval}/include/f2c.h" ; then + F2C_INC=${pfxval}/include fi - if test -n "libf2c.a" -a -d "${!pfxvar}/lib" -a -f "${!pfxvar}/lib/libf2c.a" ; then - F2C_LIB=${!pfxvar}/lib + if test -n "libf2c.a" -a -d "${pfxval}/lib" -a -f "${pfxval}/lib/libf2c.a" ; then + F2C_LIB=${pfxval}/lib fi fi -elif test "${!binvar}" != "nada" ; then - if test "${!libvar}" != "nada" ; then - if test "${!incvar}" != "nada" ; then - if test -d "${!binvar}" ; then - if test -d "${!incvar}" ; then - if test -d "${!libvar}" ; then - F2C=${!binvar}/f2c +elif test "${binval}" != "nada" ; then + if test "${libval}" != "nada" ; then + if test "${incval}" != "nada" ; then + if test -d "${binval}" ; then + if test -d "${incval}" ; then + if test -d "${libval}" ; then + F2C=${binval}/f2c - F2C_BIN=${!binvar} + F2C_BIN=${binval} - F2C_INC=${!incvar} + F2C_INC=${incval} - F2C_LIB=${!libvar} + F2C_LIB=${libval} USE_F2C=1 @@ -18900,7 +18900,7 @@ echo "${ECHO_T}found in PATH at $tmppfxdir" >&6 else checkresult="yes" - checkvar="USE_"F2C + eval checkval=\$\{"USE_"F2C\} if test -n "/usr" -a -d "/usr" -a -n "f2c" -a -d "/usr/bin" -a -x "/usr/bin/f2c" ; then USE_F2C="USE_F2C = 1" @@ -18921,7 +18921,7 @@ fi fi - if test -z "${!checkvar}" ; then + if test -z "${checkval}" ; then if test -n "/usr/local" -a -d "/usr/local" -a -n "f2c" -a -d "/usr/local/bin" -a -x "/usr/local/bin/f2c" ; then USE_F2C="USE_F2C = 1" @@ -18942,7 +18942,7 @@ fi fi - if test -z "${!checkvar}" ; then + if test -z "${checkval}" ; then if test -n "/sw" -a -d "/sw" -a -n "f2c" -a -d "/sw/bin" -a -x "/sw/bin/f2c" ; then USE_F2C="USE_F2C = 1" @@ -18963,7 +18963,7 @@ fi fi - if test -z "${!checkvar}" ; then + if test -z "${checkval}" ; then if test -n "/opt" -a -d "/opt" -a -n "f2c" -a -d "/opt/bin" -a -x "/opt/bin/f2c" ; then USE_F2C="USE_F2C = 1" @@ -18984,7 +18984,7 @@ fi fi - if test -z "${!checkvar}" ; then + if test -z "${checkval}" ; then if test -n "/" -a -d "/" -a -n "f2c" -a -d "//bin" -a -x "//bin/f2c" ; then USE_F2C="USE_F2C = 1" @@ -19005,7 +19005,7 @@ fi fi - if test -z "${!checkvar}" ; then + if test -z "${checkval}" ; then checkresult="no" fi fi @@ -19053,44 +19053,44 @@ else f95incdir=nada fi; -pfxvar=f95pfxdir -binvar=f95bindir -incvar=f95incdir -libvar=f95libdir -if test "${!pfxvar}" != "nada" ; then +eval pfxval=\$\{f95pfxdir\} +eval binval=\$\{f95bindir\} +eval incval=\$\{f95incdir\} +eval libvar=\$\{f95libdir\} +if test "${pfxval}" != "nada" ; then -if test -n "${!pfxvar}" -a -d "${!pfxvar}" -a -n "f95" -a -d "${!pfxvar}/bin" -a -x "${!pfxvar}/bin/f95" ; then +if test -n "${pfxval}" -a -d "${pfxval}" -a -n "f95" -a -d "${pfxval}/bin" -a -x "${pfxval}/bin/f95" ; then USE_F95="USE_F95 = 1" - F95=${!pfxvar}/bin/f95 + F95=${pfxval}/bin/f95 - F95_BIN=${!pfxvar}/bin + F95_BIN=${pfxval}/bin - F95_DIR=${!pfxvar} + F95_DIR=${pfxval} - if test -n "" -a -d "${!pfxvar}/include" -a -f "${!pfxvar}/include/" ; then - F95_INC=${!pfxvar}/include + if test -n "" -a -d "${pfxval}/include" -a -f "${pfxval}/include/" ; then + F95_INC=${pfxval}/include fi - if test -n "libf97.dylib" -a -d "${!pfxvar}/lib" -a -f "${!pfxvar}/lib/libf97.dylib" ; then - F95_LIB=${!pfxvar}/lib + if test -n "libf97.dylib" -a -d "${pfxval}/lib" -a -f "${pfxval}/lib/libf97.dylib" ; then + F95_LIB=${pfxval}/lib fi fi -elif test "${!binvar}" != "nada" ; then - if test "${!libvar}" != "nada" ; then - if test "${!incvar}" != "nada" ; then - if test -d "${!binvar}" ; then - if test -d "${!incvar}" ; then - if test -d "${!libvar}" ; then - F95=${!binvar}/f95 +elif test "${binval}" != "nada" ; then + if test "${libval}" != "nada" ; then + if test "${incval}" != "nada" ; then + if test -d "${binval}" ; then + if test -d "${incval}" ; then + if test -d "${libval}" ; then + F95=${binval}/f95 - F95_BIN=${!binvar} + F95_BIN=${binval} - F95_INC=${!incvar} + F95_INC=${incval} - F95_LIB=${!libvar} + F95_LIB=${libval} USE_F95=1 @@ -19160,7 +19160,7 @@ echo "${ECHO_T}found in PATH at $tmppfxdir" >&6 else checkresult="yes" - checkvar="USE_"F95 + eval checkval=\$\{"USE_"F95\} if test -n "/usr" -a -d "/usr" -a -n "f95" -a -d "/usr/bin" -a -x "/usr/bin/f95" ; then USE_F95="USE_F95 = 1" @@ -19181,7 +19181,7 @@ fi fi - if test -z "${!checkvar}" ; then + if test -z "${checkval}" ; then if test -n "/usr/local" -a -d "/usr/local" -a -n "f95" -a -d "/usr/local/bin" -a -x "/usr/local/bin/f95" ; then USE_F95="USE_F95 = 1" @@ -19202,7 +19202,7 @@ fi fi - if test -z "${!checkvar}" ; then + if test -z "${checkval}" ; then if test -n "/sw" -a -d "/sw" -a -n "f95" -a -d "/sw/bin" -a -x "/sw/bin/f95" ; then USE_F95="USE_F95 = 1" @@ -19223,7 +19223,7 @@ fi fi - if test -z "${!checkvar}" ; then + if test -z "${checkval}" ; then if test -n "/opt" -a -d "/opt" -a -n "f95" -a -d "/opt/bin" -a -x "/opt/bin/f95" ; then USE_F95="USE_F95 = 1" @@ -19244,7 +19244,7 @@ fi fi - if test -z "${!checkvar}" ; then + if test -z "${checkval}" ; then if test -n "/" -a -d "/" -a -n "f95" -a -d "//bin" -a -x "//bin/f95" ; then USE_F95="USE_F95 = 1" @@ -19265,7 +19265,7 @@ fi fi - if test -z "${!checkvar}" ; then + if test -z "${checkval}" ; then checkresult="no" fi fi From reid at x10sys.com Mon Jul 25 15:32:11 2005 From: reid at x10sys.com (Reid Spencer) Date: Mon, 25 Jul 2005 15:32:11 -0500 Subject: [llvm-commits] CVS: llvm-test/MultiSource/Makefile.multisrc Message-ID: <200507252032.PAA19800@zion.cs.uiuc.edu> Changes in directory llvm-test/MultiSource: Makefile.multisrc updated: 1.48 -> 1.49 --- Log message: Oops .. local change committed by accident. --- Diffs of the changes: (+1 -1) Makefile.multisrc | 2 +- 1 files changed, 1 insertion(+), 1 deletion(-) Index: llvm-test/MultiSource/Makefile.multisrc diff -u llvm-test/MultiSource/Makefile.multisrc:1.48 llvm-test/MultiSource/Makefile.multisrc:1.49 --- llvm-test/MultiSource/Makefile.multisrc:1.48 Mon Jul 25 15:30:35 2005 +++ llvm-test/MultiSource/Makefile.multisrc Mon Jul 25 15:32:00 2005 @@ -15,7 +15,7 @@ ## LLVM bytecode libraries that must be linked with an application # FIXME: LIBS SHOULD BE SPECIFIED -LIBS += -lm -ldl +LIBS += -lm include $(LEVEL)/Makefile.programs From natebegeman at mac.com Mon Jul 25 16:15:39 2005 From: natebegeman at mac.com (Nate Begeman) Date: Mon, 25 Jul 2005 16:15:39 -0500 Subject: [llvm-commits] CVS: llvm/lib/Target/PowerPC/PPC32ISelPattern.cpp Message-ID: <200507252115.QAA20047@zion.cs.uiuc.edu> Changes in directory llvm/lib/Target/PowerPC: PPC32ISelPattern.cpp updated: 1.103 -> 1.104 --- Log message: Fix an optimization put in for accessing static globals. This obviates the need to build PIC. --- Diffs of the changes: (+6 -5) PPC32ISelPattern.cpp | 11 ++++++----- 1 files changed, 6 insertions(+), 5 deletions(-) Index: llvm/lib/Target/PowerPC/PPC32ISelPattern.cpp diff -u llvm/lib/Target/PowerPC/PPC32ISelPattern.cpp:1.103 llvm/lib/Target/PowerPC/PPC32ISelPattern.cpp:1.104 --- llvm/lib/Target/PowerPC/PPC32ISelPattern.cpp:1.103 Fri Jul 22 17:58:34 2005 +++ llvm/lib/Target/PowerPC/PPC32ISelPattern.cpp Mon Jul 25 16:15:28 2005 @@ -45,7 +45,6 @@ PPC32TargetLowering(TargetMachine &TM) : TargetLowering(TM) { // Fold away setcc operations if possible. setSetCCIsExpensive(); - PICEnabled = true; // Set up the register classes. addRegisterClass(MVT::i32, PPC32::GPRCRegisterClass); @@ -1438,9 +1437,10 @@ if (GV->hasWeakLinkage() || GV->isExternal()) { Tmp2 = MakeReg(MVT::i32); BuildMI(BB, PPC::LWZ, 2, Tmp2).addGlobalAddress(GV).addReg(Tmp1); - Tmp1 = Tmp2; + BuildMI(BB, Opc, 2, Result).addSImm(0).addReg(Tmp2); + } else { + BuildMI(BB, Opc, 2, Result).addGlobalAddress(GV).addReg(Tmp1); } - BuildMI(BB, Opc, 2, Result).addGlobalAddress(GV).addReg(Tmp1); } else { int offset; bool idx = SelectAddr(Address, Tmp1, offset); @@ -2491,9 +2491,10 @@ if (GV->hasWeakLinkage() || GV->isExternal()) { Tmp3 = MakeReg(MVT::i32); BuildMI(BB, PPC::LWZ, 2, Tmp3).addGlobalAddress(GV).addReg(Tmp2); - Tmp2 = Tmp3; + BuildMI(BB, Opc, 3).addReg(Tmp1).addSImm(0).addReg(Tmp3); + } else { + BuildMI(BB, Opc, 3).addReg(Tmp1).addGlobalAddress(GV).addReg(Tmp2); } - BuildMI(BB, Opc, 3).addReg(Tmp1).addGlobalAddress(GV).addReg(Tmp2); } else { int offset; bool idx = SelectAddr(Address, Tmp2, offset); From lattner at cs.uiuc.edu Mon Jul 25 18:43:09 2005 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Mon, 25 Jul 2005 18:43:09 -0500 Subject: [llvm-commits] CVS: llvm/lib/ExecutionEngine/JIT/JITEmitter.cpp Message-ID: <200507252343.SAA21206@zion.cs.uiuc.edu> Changes in directory llvm/lib/ExecutionEngine/JIT: JITEmitter.cpp updated: 1.70 -> 1.71 --- Log message: fix a warning on 32-bit systems --- Diffs of the changes: (+1 -1) JITEmitter.cpp | 2 +- 1 files changed, 1 insertion(+), 1 deletion(-) Index: llvm/lib/ExecutionEngine/JIT/JITEmitter.cpp diff -u llvm/lib/ExecutionEngine/JIT/JITEmitter.cpp:1.70 llvm/lib/ExecutionEngine/JIT/JITEmitter.cpp:1.71 --- llvm/lib/ExecutionEngine/JIT/JITEmitter.cpp:1.70 Fri Jul 22 15:48:12 2005 +++ llvm/lib/ExecutionEngine/JIT/JITEmitter.cpp Mon Jul 25 18:42:58 2005 @@ -437,7 +437,7 @@ MR.doesntNeedFunctionStub()); else //ConstantPoolIndex ResultPtr = - (void*)getConstantPoolEntryAddress(MR.getConstantPoolIndex()); + (void*)(intptr_t)getConstantPoolEntryAddress(MR.getConstantPoolIndex()); MR.setResultPointer(ResultPtr); From lattner at cs.uiuc.edu Mon Jul 25 19:41:32 2005 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Mon, 25 Jul 2005 19:41:32 -0500 Subject: [llvm-commits] CVS: llvm-gcc/gcc/config/rs6000/darwin.h Message-ID: <200507260041.TAA22587@zion.cs.uiuc.edu> Changes in directory llvm-gcc/gcc/config/rs6000: darwin.h updated: 1.2 -> 1.3 --- Log message: Add a flag to hack darwin, which has funky alignment rules --- Diffs of the changes: (+6 -0) darwin.h | 6 ++++++ 1 files changed, 6 insertions(+) Index: llvm-gcc/gcc/config/rs6000/darwin.h diff -u llvm-gcc/gcc/config/rs6000/darwin.h:1.2 llvm-gcc/gcc/config/rs6000/darwin.h:1.3 --- llvm-gcc/gcc/config/rs6000/darwin.h:1.2 Wed Jul 20 19:57:44 2005 +++ llvm-gcc/gcc/config/rs6000/darwin.h Mon Jul 25 19:41:21 2005 @@ -270,6 +270,12 @@ : TREE_TYPE (FIELD)) == DFmode \ ? MIN ((COMPUTED), 32) : (COMPUTED))) +/* The maximum alignment for this target (according to LLVM) is 4 bytes, + * this prevents the type layout machinery from thinking darwin's doubles + * and 'long long's are 64-bit aligned. + */ +#define LLVM_TARGET_MAX_ALIGN_IS_POINTER_SIZE 1 + /* Darwin increases natural record alignment to doubleword if the first field is an FP double while the FP fields remain word aligned. */ #define ROUND_TYPE_ALIGN(STRUCT, COMPUTED, SPECIFIED) \ From lattner at cs.uiuc.edu Mon Jul 25 20:14:41 2005 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Mon, 25 Jul 2005 20:14:41 -0500 Subject: [llvm-commits] CVS: llvm-test/SingleSource/Regression/C++/ofstream_ctor.cpp Message-ID: <200507260114.UAA23535@zion.cs.uiuc.edu> Changes in directory llvm-test/SingleSource/Regression/C++: ofstream_ctor.cpp added (r1.1) --- Log message: new testcase, from PR449: http://llvm.cs.uiuc.edu/PR449 --- Diffs of the changes: (+6 -0) ofstream_ctor.cpp | 6 ++++++ 1 files changed, 6 insertions(+) Index: llvm-test/SingleSource/Regression/C++/ofstream_ctor.cpp diff -c /dev/null llvm-test/SingleSource/Regression/C++/ofstream_ctor.cpp:1.1 *** /dev/null Mon Jul 25 20:14:40 2005 --- llvm-test/SingleSource/Regression/C++/ofstream_ctor.cpp Mon Jul 25 20:14:30 2005 *************** *** 0 **** --- 1,6 ---- + // PR449 + #include + int main() { + std::ofstream X; + } + From lattner at cs.uiuc.edu Mon Jul 25 20:17:33 2005 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Mon, 25 Jul 2005 20:17:33 -0500 Subject: [llvm-commits] CVS: llvm-gcc/gcc/llvm-types.c Message-ID: <200507260117.UAA23579@zion.cs.uiuc.edu> Changes in directory llvm-gcc/gcc: llvm-types.c updated: 1.24 -> 1.25 --- Log message: Fix PR449: http://llvm.cs.uiuc.edu/PR449 and PR603: http://llvm.cs.uiuc.edu/PR603 by being VERY VERY careful to match the target layout when laying out the LLVM type for a C type. In particular, do not assume silly things (like types always having the same alignment whenever they are used) that hold for every target but darwin. This fixes Regression/C++/ofstream_ctor.cpp. --- Diffs of the changes: (+113 -74) llvm-types.c | 187 +++++++++++++++++++++++++++++++++++------------------------ 1 files changed, 113 insertions(+), 74 deletions(-) Index: llvm-gcc/gcc/llvm-types.c diff -u llvm-gcc/gcc/llvm-types.c:1.24 llvm-gcc/gcc/llvm-types.c:1.25 --- llvm-gcc/gcc/llvm-types.c:1.24 Fri Jul 22 13:53:38 2005 +++ llvm-gcc/gcc/llvm-types.c Mon Jul 25 20:17:22 2005 @@ -75,48 +75,30 @@ */ static unsigned PrimitiveAlignments[OpaqueTyID]; -static unsigned getMinTargetAlignment(tree Type) { - unsigned BasicAlignment = TYPE_ALIGN(Type); - unsigned TestAlignment; +static void InitializeAlignments(void) { + unsigned MaxAlign = BIGGEST_ALIGNMENT; +#ifdef BIGGEST_FIELD_ALIGNMENT + MaxAlign = MIN(MaxAlign, BIGGEST_FIELD_ALIGNMENT); +#endif - /* Some targets do funny things with structs. Form a struct that has a - * character member as the first element, then Type as the second element. - * If that alignment is less than BasicAlignment, use it. - */ - tree recordtype = (*lang_hooks.types.make_type) (RECORD_TYPE); - tree field, fields; - /* First character field. */ - fields = build_decl (FIELD_DECL, NULL_TREE, unsigned_intQI_type_node); - - /* A field of type Type. */ - field = build_decl (FIELD_DECL, NULL_TREE, Type); - TREE_CHAIN (field) = fields; - finish_builtin_struct(recordtype, "", field, NULL_TREE); - - llvm_type_dump(llvm_type_get_from_tree(recordtype)); +#ifdef LLVM_TARGET_MAX_ALIGN_IS_POINTER_SIZE + /* Targets like PowerPC where the longs and doubles are 4-byte aligned. */ + MaxAlign = MIN(MaxAlign, POINTER_SIZE/BITS_PER_UNIT); +#endif - TestAlignment = TYPE_ALIGN(recordtype); - BasicAlignment = MIN(BasicAlignment, TestAlignment); - return BasicAlignment/8; -} - -static void InitializeAlignments(void) { /* Figure out the alignments of the primitive types. */ PrimitiveAlignments[BoolTyID] = 1; PrimitiveAlignments[SByteTyID] = 1; PrimitiveAlignments[UByteTyID] = 1; - PrimitiveAlignments[ShortTyID] = getMinTargetAlignment(intHI_type_node); - PrimitiveAlignments[UShortTyID] = - getMinTargetAlignment(unsigned_intHI_type_node); - PrimitiveAlignments[IntTyID] = getMinTargetAlignment(intSI_type_node); - PrimitiveAlignments[UIntTyID] = - getMinTargetAlignment(unsigned_intSI_type_node); - PrimitiveAlignments[LongTyID] = getMinTargetAlignment(intDI_type_node); - PrimitiveAlignments[ULongTyID] = - getMinTargetAlignment(unsigned_intDI_type_node); - PrimitiveAlignments[FloatTyID] = getMinTargetAlignment(float_type_node); - PrimitiveAlignments[DoubleTyID] = getMinTargetAlignment(double_type_node); - PrimitiveAlignments[PointerTyID] = getMinTargetAlignment(ptr_type_node); + PrimitiveAlignments[ShortTyID] = PrimitiveAlignments[UShortTyID] + = MIN(2, MaxAlign); + PrimitiveAlignments[IntTyID] = PrimitiveAlignments[UIntTyID] + = MIN(4, MaxAlign); + PrimitiveAlignments[ULongTyID] = PrimitiveAlignments[LongTyID] + = MIN(8, MaxAlign); + PrimitiveAlignments[FloatTyID] = MIN(4, MaxAlign); + PrimitiveAlignments[DoubleTyID] = MIN(8, MaxAlign); + PrimitiveAlignments[PointerTyID] = MIN(POINTER_SIZE/BITS_PER_UNIT, MaxAlign); } unsigned llvm_type_get_alignment(llvm_type *Ty) { @@ -739,7 +721,7 @@ llvm_type_print(FieldTy, stderr); fprintf(stderr, " name='%s' talign=%d dalign=%d\n", DECL_NAME(field) ? IDENTIFIER_POINTER(DECL_NAME(field)) : "", - GetFieldAlignmentInBits(field), TYPE_ALIGN(TREE_TYPE(field))/8); + GetFieldAlignmentInBytes(field), TYPE_ALIGN(TREE_TYPE(field))/8); } #endif @@ -787,32 +769,33 @@ llvm_type *Ty = llvm_type_get_from_tree(TREE_TYPE(field)); /* Get the starting offset in the record... */ unsigned StartOffset = GetFieldOffset(field); /* In bits */ - unsigned BitAlignment = GetFieldAlignmentInBits(field); /* In bits */ - unsigned ByteAlignment = (BitAlignment+7)/8; + unsigned ByteAlignment = llvm_type_get_alignment(Ty); if (!TypeIsRecursivelyIntegral(Ty)) { /* Not an integral field? */ + unsigned OrigSize = *Size; /* If this field is not an integral type, just include it directly. */ assert((StartOffset & 7) == 0 && "Member not byte aligned??"); /* Round *Size up to take into consideration alignment of this field */ *Size = (*Size + ByteAlignment - 1) & ~(ByteAlignment-1); - /* Check to see if there is "magic padding" that got inserted into the - * structure. This can happen, for example, when the C++ ABI declares that - * two types to not exist at the same offset. For this reason, a byte of - * padding is inserted, and then the layout of the next element occurs at - * whatever alignment is reasonable for it. + /* Check to see if the next element starts further from the previous element + * than the LLVM alignment would put it. If so, insert some dummy padding + * to ensure that the LLVM conception of where this element lands is the + * same as what GCC thinks. */ - if (*Size < StartOffset/8) - /* Only fix things if it is because of this "magic padding" */ - if (*Size + ByteAlignment == StartOffset/8) { - ElementTys[*Idx] = UByteTy; /* Random pad element */ - ElementOffsets[*Idx] = *Size; - ElementAlignments[*Idx] = 1; - ++*Idx; - *Size = StartOffset/8; - } - + if (*Size < StartOffset/8) { + unsigned PadBytes = StartOffset/8 - OrigSize; + if (PadBytes == 1) + ElementTys[*Idx] = UByteTy; + else + ElementTys[*Idx] = llvm_type_get_array(UByteTy, PadBytes); + ElementOffsets[*Idx] = OrigSize; + ElementAlignments[*Idx] = 1; + ++*Idx; + *Size = OrigSize + PadBytes; + } + #if 0 /* FIXME: This assertion should be kept!!! */ assert(*Size == StartOffset/8 && "Member does not start where we think it does?"); @@ -826,14 +809,17 @@ DECL_BIT_FIELD(field)) { unsigned NumPads; unsigned DeclSize = GetDeclSize(field); + unsigned FieldCBitAlignment = GetFieldAlignmentInBits(field); + unsigned FieldCByteAlignment = (FieldCBitAlignment+7)/8; /* Is it attempting to align the current offset to some value? */ if (DeclSize == 0) { - NumPads = ByteAlignment - (*Size % ByteAlignment); - if (NumPads == ByteAlignment) NumPads = 0; - assert((*Size+NumPads) % ByteAlignment == 0 &&"Incorrect padding calc?"); + NumPads = FieldCByteAlignment - (*Size % FieldCByteAlignment); + if (NumPads == FieldCByteAlignment) NumPads = 0; + assert((*Size+NumPads) % FieldCByteAlignment == 0 && + "Incorrect padding calc?"); #if DEBUG_STRUCT_LAYOUT fprintf(stderr, "Anon field: align=%db pads = %d ", - BitAlignment, NumPads); + FieldCByteAlignment, NumPads); PrintFieldInfo(field); #endif } else { @@ -864,15 +850,18 @@ * if the alignment allows for it. Thus, we start out with the element * size, and round up to the alignment as necessary. */ - unsigned ElSize = GetDeclSize(field); /* In bits */ + unsigned ElSizeInBits = GetDeclSize(field); /* In bits */ + unsigned FieldCBitAlignment = GetFieldAlignmentInBits(field); + unsigned FieldCByteAlignment = (FieldCBitAlignment+7)/8; + int HasSignedField; unsigned StartByte; - if (ElSize && BitAlignment > ElSize) ElSize = BitAlignment; + if (ElSizeInBits) ElSizeInBits = MAX(ElSizeInBits, FieldCBitAlignment); HasSignedField = !TREE_UNSIGNED(TREE_TYPE(field)); /* Calculate the first byte occupied by this field */ - StartByte = StartOffset/8 - (StartOffset/8) % ByteAlignment; + StartByte = StartOffset/8 - (StartOffset/8) % FieldCByteAlignment; /* Check to see if we have emitted any structure elements that overlap with * the current bitfield. @@ -882,9 +871,9 @@ * encompasses this type. If so, we just have to update the signedness if * the field is not yet signed. */ - if (StartByte*8+ElSize <= *Size * 8) { + if (StartByte*8+ElSizeInBits <= *Size * 8) { assert(ElementOffsets[*Idx-1] <= StartByte && - ElementAlignments[*Idx-1] >= ByteAlignment && + ElementAlignments[*Idx-1] >= FieldCByteAlignment && "Less aligned field overlaps with later, more aligned, field?"); /* If the last field is a bool, expand it to be a uchar */ if (ElementTys[*Idx-1] == BoolTy) @@ -910,8 +899,8 @@ } while (*Idx && *Size > StartByte); /* Output this as a series of integer fields. */ - while (ElSize > 64) { - unsigned UnitSize = ElSize & 63; + while (ElSizeInBits > 64) { + unsigned UnitSize = ElSizeInBits & 63; /* Eliminate all but one bit from the size */ if ((UnitSize & (UnitSize-1)) != 0) UnitSize = UnitSize ^ (UnitSize & (UnitSize-1)); @@ -923,10 +912,27 @@ ElementAlignments[*Idx] = 1; ++*Idx; StartByte += UnitSize/8; - ElSize -= UnitSize; + ElSizeInBits -= UnitSize; } - Ty = llvm_type_get_integer(ElSize, !HasSignedField); + Ty = llvm_type_get_integer(ElSizeInBits, !HasSignedField); + } + + /* Check to see if the next element starts further from the previous element + * than the LLVM alignment would put it. If so, insert some dummy padding + * to ensure that the LLVM conception of where this element lands is the + * same as what GCC thinks. + */ + if (((*Size + ByteAlignment - 1) & ~(ByteAlignment-1)) < StartOffset/8) { + unsigned PadBytes = StartOffset/8 - *Size; + if (PadBytes == 1) + ElementTys[*Idx] = UByteTy; + else + ElementTys[*Idx] = llvm_type_get_array(UByteTy, PadBytes); + ElementOffsets[*Idx] = *Size; + ElementAlignments[*Idx] = 1; + ++*Idx; + *Size = *Size + PadBytes; } /* Check to see if there is "magic padding" that got inserted into the @@ -939,7 +945,7 @@ /* Only fix things if it is because of this "magic padding" */ if (*Size + ByteAlignment == StartByte) { /* Random pad element */ - ElementTys[*Idx] = llvm_type_get_integer(BitAlignment, 1); + ElementTys[*Idx] = llvm_type_get_integer(ByteAlignment*8, 1); ElementOffsets[*Idx] = *Size; ElementAlignments[*Idx] = ByteAlignment; ++*Idx; @@ -1443,13 +1449,46 @@ #endif } - /* Empty C++ structures == { ubyte } in LLVM so that sizes are correct. */ - if (Idx == 0 && (int)TREE_INT_CST_LOW(TYPE_SIZE(type)) == 8) { - StructElements[0] = UByteTy; - ElementOffsets[0] = 0; - ++Idx; - } + /* If we are missing elements from the end of the structure (which + * contribute to its size but are not accessed by the program), add dummy + * elements so that the LLVM code will have the right size for the + * structure. + */ + { + unsigned GCCTypeSize = ((unsigned)TREE_INT_CST_LOW(TYPE_SIZE(type))+7)/8; + unsigned LLVMTypeSize, LLVMStructAlign = 1, i; + + /* To determine what LLVM will think the size of this struct is, compute + * the LLVM alignment the struct will have. + */ + for (i = 0; i != Idx; ++i) { + unsigned EltAlign = llvm_type_get_alignment(StructElements[i]); + LLVMStructAlign = MAX(LLVMStructAlign, EltAlign); + } + + /* The LLVM size of the struct will be the current size, rounded up to the + * next multiple of StructAlign. + */ + assert((LLVMStructAlign & (LLVMStructAlign-1)) == 0 && + "Alignment not a power of 2!"); + LLVMTypeSize = (Size+LLVMStructAlign-1) & ~(LLVMStructAlign-1); + /* If the LLVM type will end up being too small, add elements to the end + * of the struct to pad it out. + */ + if (LLVMTypeSize < GCCTypeSize) { + unsigned PadBytes = GCCTypeSize - Size; + if (PadBytes == 1) + StructElements[Idx] = UByteTy; + else + StructElements[Idx] = llvm_type_get_array(UByteTy, PadBytes); + ElementOffsets[Idx] = Size; + ElementAlignments[Idx] = 1; + ++Idx; + Size += PadBytes; + } + } + /* End of the hack, set the real number of elements. */ Result->NumElements = Idx; From lattner at cs.uiuc.edu Tue Jul 26 11:38:40 2005 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Tue, 26 Jul 2005 11:38:40 -0500 Subject: [llvm-commits] CVS: llvm/lib/Transforms/ExprTypeConvert.cpp LevelRaise.cpp TransformInternals.cpp TransformInternals.h Message-ID: <200507261638.LAA32602@zion.cs.uiuc.edu> Changes in directory llvm/lib/Transforms: ExprTypeConvert.cpp updated: 1.106 -> 1.107 LevelRaise.cpp updated: 1.107 -> 1.108 TransformInternals.cpp updated: 1.48 -> 1.49 TransformInternals.h updated: 1.26 -> 1.27 --- Log message: ConvertibleToGEP always returns 0, remove some old crufty code which is actually dead because of this! --- Diffs of the changes: (+0 -369) ExprTypeConvert.cpp | 185 ------------------------------------------------- LevelRaise.cpp | 157 ----------------------------------------- TransformInternals.cpp | 13 --- TransformInternals.h | 14 --- 4 files changed, 369 deletions(-) Index: llvm/lib/Transforms/ExprTypeConvert.cpp diff -u llvm/lib/Transforms/ExprTypeConvert.cpp:1.106 llvm/lib/Transforms/ExprTypeConvert.cpp:1.107 --- llvm/lib/Transforms/ExprTypeConvert.cpp:1.106 Sat May 14 07:28:32 2005 +++ llvm/lib/Transforms/ExprTypeConvert.cpp Tue Jul 26 11:38:28 2005 @@ -252,32 +252,6 @@ if (ElTy) break; // Found a number of zeros we can strip off! - // Otherwise, we can convert a GEP from one form to the other iff the - // current gep is of the form 'getelementptr sbyte*, long N - // and we could convert this to an appropriate GEP for the new type. - // - if (GEP->getNumOperands() == 2 && - GEP->getType() == PointerType::get(Type::SByteTy)) { - - // Do not Check to see if our incoming pointer can be converted - // to be a ptr to an array of the right type... because in more cases than - // not, it is simply not analyzable because of pointer/array - // discrepancies. To fix this, we will insert a cast before the GEP. - // - - // Check to see if 'N' is an expression that can be converted to - // the appropriate size... if so, allow it. - // - std::vector Indices; - const Type *ElTy = ConvertibleToGEP(PTy, I->getOperand(1), Indices, TD); - if (ElTy == PVTy) { - if (!ExpressionConvertibleToType(I->getOperand(0), - PointerType::get(ElTy), CTMap, TD)) - return false; // Can't continue, ExConToTy might have polluted set! - break; - } - } - // Otherwise, it could be that we have something like this: // getelementptr [[sbyte] *] * %reg115, long %reg138 ; [sbyte]** // and want to convert it into something like this: @@ -459,32 +433,6 @@ } } - if (Res == 0 && GEP->getNumOperands() == 2 && - GEP->getType() == PointerType::get(Type::SByteTy)) { - - // Otherwise, we can convert a GEP from one form to the other iff the - // current gep is of the form 'getelementptr sbyte*, unsigned N - // and we could convert this to an appropriate GEP for the new type. - // - const PointerType *NewSrcTy = PointerType::get(PVTy); - BasicBlock::iterator It = I; - - // Check to see if 'N' is an expression that can be converted to - // the appropriate size... if so, allow it. - // - std::vector Indices; - const Type *ElTy = ConvertibleToGEP(NewSrcTy, I->getOperand(1), - Indices, TD, &It); - if (ElTy) { - assert(ElTy == PVTy && "Internal error, setup wrong!"); - Res = new GetElementPtrInst(Constant::getNullValue(NewSrcTy), - Indices, Name); - VMC.ExprMap[I] = Res; - Res->setOperand(0, ConvertExpressionToType(I->getOperand(0), - NewSrcTy, VMC, TD)); - } - } - // Otherwise, it could be that we have something like this: // getelementptr [[sbyte] *] * %reg115, uint %reg138 ; [sbyte]** // and want to convert it into something like this: @@ -637,23 +585,6 @@ return true; case Instruction::Add: - if (isa(Ty)) { - Value *IndexVal = I->getOperand(V == I->getOperand(0) ? 1 : 0); - std::vector Indices; - if (const Type *ETy = ConvertibleToGEP(Ty, IndexVal, Indices, TD)) { - const Type *RetTy = PointerType::get(ETy); - - // Only successful if we can convert this type to the required type - if (ValueConvertibleToType(I, RetTy, CTMap, TD)) { - CTMap[I] = RetTy; - return true; - } - // We have to return failure here because ValueConvertibleToType could - // have polluted our map - return false; - } - } - // FALLTHROUGH case Instruction::Sub: { if (!Ty->isInteger() && !Ty->isFloatingPoint()) return false; @@ -780,47 +711,6 @@ return false; } - case Instruction::GetElementPtr: - if (V != I->getOperand(0) || !isa(Ty)) return false; - - // If we have a two operand form of getelementptr, this is really little - // more than a simple addition. As with addition, check to see if the - // getelementptr instruction can be changed to index into the new type. - // - if (I->getNumOperands() == 2) { - const Type *OldElTy = cast(I->getType())->getElementType(); - uint64_t DataSize = TD.getTypeSize(OldElTy); - Value *Index = I->getOperand(1); - Instruction *TempScale = 0; - - // If the old data element is not unit sized, we have to create a scale - // instruction so that ConvertibleToGEP will know the REAL amount we are - // indexing by. Note that this is never inserted into the instruction - // stream, so we have to delete it when we're done. - // - if (DataSize != 1) { - Value *CST; - if (Index->getType()->isSigned()) - CST = ConstantSInt::get(Index->getType(), DataSize); - else - CST = ConstantUInt::get(Index->getType(), DataSize); - - TempScale = BinaryOperator::create(Instruction::Mul, Index, CST); - Index = TempScale; - } - - // Check to see if the second argument is an expression that can - // be converted to the appropriate size... if so, allow it. - // - std::vector Indices; - const Type *ElTy = ConvertibleToGEP(Ty, Index, Indices, TD); - delete TempScale; // Free our temporary multiply if we made it - - if (ElTy == 0) return false; // Cannot make conversion... - return ValueConvertibleToType(I, PointerType::get(ElTy), CTMap, TD); - } - return false; - case Instruction::PHI: { PHINode *PN = cast(I); // Be conservative if we find a giant PHI node. @@ -964,23 +854,6 @@ break; case Instruction::Add: - if (isa(NewTy)) { - Value *IndexVal = I->getOperand(OldVal == I->getOperand(0) ? 1 : 0); - std::vector Indices; - BasicBlock::iterator It = I; - - if (const Type *ETy = ConvertibleToGEP(NewTy, IndexVal, Indices, TD,&It)){ - // If successful, convert the add to a GEP - //const Type *RetTy = PointerType::get(ETy); - // First operand is actually the given pointer... - Res = new GetElementPtrInst(NewVal, Indices, Name); - assert(cast(Res->getType())->getElementType() == ETy && - "ConvertibleToGEP broken!"); - break; - } - } - // FALLTHROUGH - case Instruction::Sub: case Instruction::SetEQ: case Instruction::SetNE: { @@ -1102,64 +975,6 @@ break; } - - case Instruction::GetElementPtr: { - // Convert a one index getelementptr into just about anything that is - // desired. - // - BasicBlock::iterator It = I; - const Type *OldElTy = cast(I->getType())->getElementType(); - uint64_t DataSize = TD.getTypeSize(OldElTy); - Value *Index = I->getOperand(1); - - if (DataSize != 1) { - // Insert a multiply of the old element type is not a unit size... - Value *CST; - if (Index->getType()->isSigned()) - CST = ConstantSInt::get(Index->getType(), DataSize); - else - CST = ConstantUInt::get(Index->getType(), DataSize); - - Index = BinaryOperator::create(Instruction::Mul, Index, CST, "scale", It); - } - - // Perform the conversion now... - // - std::vector Indices; - const Type *ElTy = ConvertibleToGEP(NewVal->getType(),Index,Indices,TD,&It); - assert(ElTy != 0 && "GEP Conversion Failure!"); - Res = new GetElementPtrInst(NewVal, Indices, Name); - assert(Res->getType() == PointerType::get(ElTy) && - "ConvertibleToGet failed!"); - } -#if 0 - if (I->getType() == PointerType::get(Type::SByteTy)) { - // Convert a getelementptr sbyte * %reg111, uint 16 freely back to - // anything that is a pointer type... - // - BasicBlock::iterator It = I; - - // Check to see if the second argument is an expression that can - // be converted to the appropriate size... if so, allow it. - // - std::vector Indices; - const Type *ElTy = ConvertibleToGEP(NewVal->getType(), I->getOperand(1), - Indices, TD, &It); - assert(ElTy != 0 && "GEP Conversion Failure!"); - - Res = new GetElementPtrInst(NewVal, Indices, Name); - } else { - // Convert a getelementptr ulong * %reg123, uint %N - // to getelementptr long * %reg123, uint %N - // ... where the type must simply stay the same size... - // - GetElementPtrInst *GEP = cast(I); - std::vector Indices(GEP->idx_begin(), GEP->idx_end()); - Res = new GetElementPtrInst(NewVal, Indices, Name); - } -#endif - break; - case Instruction::PHI: { PHINode *OldPN = cast(I); PHINode *NewPN = new PHINode(NewTy, Name); Index: llvm/lib/Transforms/LevelRaise.cpp diff -u llvm/lib/Transforms/LevelRaise.cpp:1.107 llvm/lib/Transforms/LevelRaise.cpp:1.108 --- llvm/lib/Transforms/LevelRaise.cpp:1.107 Sat May 14 07:28:32 2005 +++ llvm/lib/Transforms/LevelRaise.cpp Tue Jul 26 11:38:28 2005 @@ -96,143 +96,6 @@ return!CI->getOperand(0)->getType()->isLosslesslyConvertibleTo(CI->getType()); } - -// Peephole optimize the following instructions: -// %t1 = cast ? to x * -// %t2 = add x * %SP, %t1 ;; Constant must be 2nd operand -// -// Into: %t3 = getelementptr {<...>} * %SP, -// %t2 = cast * %t3 to {<...>}* -// -static bool HandleCastToPointer(BasicBlock::iterator BI, - const PointerType *DestPTy, - const TargetData &TD) { - CastInst &CI = cast(*BI); - if (CI.use_empty()) return false; - - // Scan all of the uses, looking for any uses that are not add or sub - // instructions. If we have non-adds, do not make this transformation. - // - bool HasSubUse = false; // Keep track of any subtracts... - for (Value::use_iterator I = CI.use_begin(), E = CI.use_end(); - I != E; ++I) - if (BinaryOperator *BO = dyn_cast(*I)) { - if ((BO->getOpcode() != Instruction::Add && - BO->getOpcode() != Instruction::Sub) || - // Avoid add sbyte* %X, %X cases... - BO->getOperand(0) == BO->getOperand(1)) - return false; - else - HasSubUse |= BO->getOpcode() == Instruction::Sub; - } else { - return false; - } - - std::vector Indices; - Value *Src = CI.getOperand(0); - const Type *Result = ConvertibleToGEP(DestPTy, Src, Indices, TD, &BI); - if (Result == 0) return false; // Not convertible... - - // Cannot handle subtracts if there is more than one index required... - if (HasSubUse && Indices.size() != 1) return false; - - PRINT_PEEPHOLE2("cast-add-to-gep:in", *Src, CI); - - // If we have a getelementptr capability... transform all of the - // add instruction uses into getelementptr's. - while (!CI.use_empty()) { - BinaryOperator *I = cast(*CI.use_begin()); - assert((I->getOpcode() == Instruction::Add || - I->getOpcode() == Instruction::Sub) && - "Use is not a valid add instruction!"); - - // Get the value added to the cast result pointer... - Value *OtherPtr = I->getOperand((I->getOperand(0) == &CI) ? 1 : 0); - - Instruction *GEP = new GetElementPtrInst(OtherPtr, Indices, I->getName()); - PRINT_PEEPHOLE1("cast-add-to-gep:i", *I); - - // If the instruction is actually a subtract, we are guaranteed to only have - // one index (from code above), so we just need to negate the pointer index - // long value. - if (I->getOpcode() == Instruction::Sub) { - Instruction *Neg = BinaryOperator::createNeg(GEP->getOperand(1), - GEP->getOperand(1)->getName()+".neg", I); - GEP->setOperand(1, Neg); - } - - if (GEP->getType() == I->getType()) { - // Replace the old add instruction with the shiny new GEP inst - ReplaceInstWithInst(I, GEP); - } else { - // If the type produced by the gep instruction differs from the original - // add instruction type, insert a cast now. - // - - // Insert the GEP instruction before the old add instruction... - I->getParent()->getInstList().insert(I, GEP); - - PRINT_PEEPHOLE1("cast-add-to-gep:o", *GEP); - GEP = new CastInst(GEP, I->getType()); - - // Replace the old add instruction with the shiny new GEP inst - ReplaceInstWithInst(I, GEP); - } - - PRINT_PEEPHOLE1("cast-add-to-gep:o", *GEP); - } - return true; -} - -// Peephole optimize the following instructions: -// %t1 = cast ulong to {<...>} * -// %t2 = add {<...>} * %SP, %t1 ;; Constant must be 2nd operand -// -// or -// %t1 = cast {<...>}* %SP to int* -// %t5 = cast ulong to int* -// %t2 = add int* %t1, %t5 ;; int is same size as field -// -// Into: %t3 = getelementptr {<...>} * %SP, -// %t2 = cast * %t3 to {<...>}* -// -static bool PeepholeOptimizeAddCast(BasicBlock *BB, BasicBlock::iterator &BI, - Value *AddOp1, CastInst *AddOp2, - const TargetData &TD) { - const CompositeType *CompTy; - Value *OffsetVal = AddOp2->getOperand(0); - Value *SrcPtr = 0; // Of type pointer to struct... - - if ((CompTy = getPointedToComposite(AddOp1->getType()))) { - SrcPtr = AddOp1; // Handle the first case... - } else if (CastInst *AddOp1c = dyn_cast(AddOp1)) { - SrcPtr = AddOp1c->getOperand(0); // Handle the second case... - CompTy = getPointedToComposite(SrcPtr->getType()); - } - - // Only proceed if we have detected all of our conditions successfully... - if (!CompTy || !SrcPtr || !OffsetVal->getType()->isInteger()) - return false; - - std::vector Indices; - if (!ConvertibleToGEP(SrcPtr->getType(), OffsetVal, Indices, TD, &BI)) - return false; // Not convertible... perhaps next time - - if (getPointedToComposite(AddOp1->getType())) { // case 1 - PRINT_PEEPHOLE2("add-to-gep1:in", *AddOp2, *BI); - } else { - PRINT_PEEPHOLE3("add-to-gep2:in", *AddOp1, *AddOp2, *BI); - } - - GetElementPtrInst *GEP = new GetElementPtrInst(SrcPtr, Indices, - AddOp2->getName(), BI); - - Instruction *NCI = new CastInst(GEP, AddOp1->getType()); - ReplaceInstWithInst(BB->getInstList(), BI, NCI); - PRINT_PEEPHOLE2("add-to-gep:out", *GEP, *NCI); - return true; -} - bool RPR::PeepholeOptimize(BasicBlock *BB, BasicBlock::iterator &BI) { Instruction *I = BI; const TargetData &TD = getAnalysis(); @@ -321,18 +184,6 @@ } } - // Otherwise find out it this cast is a cast to a pointer type, which is - // then added to some other pointer, then loaded or stored through. If - // so, convert the add into a getelementptr instruction... - // - if (const PointerType *DestPTy = dyn_cast(DestTy)) { - if (HandleCastToPointer(BI, DestPTy, TD)) { - BI = BB->begin(); // Rescan basic block. BI might be invalidated. - ++NumGEPInstFormed; - return true; - } - } - // Check to see if we are casting from a structure pointer to a pointer to // the first element of the structure... to avoid munching other peepholes, // we only let this happen if there are no add uses of the cast. @@ -494,14 +345,6 @@ return true; } - } else if (I->getOpcode() == Instruction::Add && - isa(I->getOperand(1))) { - - if (PeepholeOptimizeAddCast(BB, BI, I->getOperand(0), - cast(I->getOperand(1)), TD)) { - ++NumGEPInstFormed; - return true; - } } else if (CallInst *CI = dyn_cast(I)) { // If we have a call with all varargs arguments, convert the call to use the // actual argument types present... Index: llvm/lib/Transforms/TransformInternals.cpp diff -u llvm/lib/Transforms/TransformInternals.cpp:1.48 llvm/lib/Transforms/TransformInternals.cpp:1.49 --- llvm/lib/Transforms/TransformInternals.cpp:1.48 Thu Apr 21 18:45:55 2005 +++ llvm/lib/Transforms/TransformInternals.cpp Tue Jul 26 11:38:28 2005 @@ -90,16 +90,3 @@ Offset = unsigned(ThisOffset + SubOffs); return LeafTy; } - -// ConvertibleToGEP - This function returns true if the specified value V is -// a valid index into a pointer of type Ty. If it is valid, Idx is filled in -// with the values that would be appropriate to make this a getelementptr -// instruction. The type returned is the root type that the GEP would point to -// -const Type *llvm::ConvertibleToGEP(const Type *Ty, Value *OffsetVal, - std::vector &Indices, - const TargetData &TD, - BasicBlock::iterator *BI) { - return 0; -} - Index: llvm/lib/Transforms/TransformInternals.h diff -u llvm/lib/Transforms/TransformInternals.h:1.26 llvm/lib/Transforms/TransformInternals.h:1.27 --- llvm/lib/Transforms/TransformInternals.h:1.26 Thu Apr 21 18:45:55 2005 +++ llvm/lib/Transforms/TransformInternals.h Tue Jul 26 11:38:28 2005 @@ -37,20 +37,6 @@ return PT ? dyn_cast(PT->getElementType()) : 0; } -// ConvertibleToGEP - This function returns true if the specified value V is -// a valid index into a pointer of type Ty. If it is valid, Idx is filled in -// with the values that would be appropriate to make this a getelementptr -// instruction. The type returned is the root type that the GEP would point -// to if it were synthesized with this operands. -// -// If BI is nonnull, cast instructions are inserted as appropriate for the -// arguments of the getelementptr. -// -const Type *ConvertibleToGEP(const Type *Ty, Value *V, - std::vector &Indices, - const TargetData &TD, - BasicBlock::iterator *BI = 0); - //===----------------------------------------------------------------------===// // ValueHandle Class - Smart pointer that occupies a slot on the users USE list From lattner at cs.uiuc.edu Tue Jul 26 11:50:44 2005 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Tue, 26 Jul 2005 11:50:44 -0500 Subject: [llvm-commits] CVS: llvm-gcc/gcc/config/rs6000/darwin.h rs6000-protos.h rs6000.c Message-ID: <200507261650.LAA32738@zion.cs.uiuc.edu> Changes in directory llvm-gcc/gcc/config/rs6000: darwin.h updated: 1.3 -> 1.4 rs6000-protos.h updated: 1.1.1.2 -> 1.2 rs6000.c updated: 1.1.1.2 -> 1.2 --- Log message: Sync up with mainline GCC for this code. This provides a minor bugfix in cases like this C++ class: struct X { enum { A }; double D; int X; }; --- Diffs of the changes: (+20 -2) darwin.h | 3 +-- rs6000-protos.h | 1 + rs6000.c | 18 ++++++++++++++++++ 3 files changed, 20 insertions(+), 2 deletions(-) Index: llvm-gcc/gcc/config/rs6000/darwin.h diff -u llvm-gcc/gcc/config/rs6000/darwin.h:1.3 llvm-gcc/gcc/config/rs6000/darwin.h:1.4 --- llvm-gcc/gcc/config/rs6000/darwin.h:1.3 Mon Jul 25 19:41:21 2005 +++ llvm-gcc/gcc/config/rs6000/darwin.h Tue Jul 26 11:50:33 2005 @@ -284,8 +284,7 @@ || TREE_CODE (STRUCT) == QUAL_UNION_TYPE) \ && TYPE_FIELDS (STRUCT) != 0 \ && TARGET_ALIGN_NATURAL == 0 \ - && DECL_MODE (TYPE_FIELDS (STRUCT)) == DFmode \ - ? MAX (MAX ((COMPUTED), (SPECIFIED)), 64) \ + ? rs6000_special_round_type_align (STRUCT, COMPUTED, SPECIFIED) \ : (TARGET_ALTIVEC && TREE_CODE (STRUCT) == VECTOR_TYPE) \ ? MAX (MAX ((COMPUTED), (SPECIFIED)), 128) \ : MAX ((COMPUTED), (SPECIFIED))) Index: llvm-gcc/gcc/config/rs6000/rs6000-protos.h diff -u llvm-gcc/gcc/config/rs6000/rs6000-protos.h:1.1.1.2 llvm-gcc/gcc/config/rs6000/rs6000-protos.h:1.2 --- llvm-gcc/gcc/config/rs6000/rs6000-protos.h:1.1.1.2 Tue Jan 13 10:49:53 2004 +++ llvm-gcc/gcc/config/rs6000/rs6000-protos.h Tue Jul 26 11:50:33 2005 @@ -31,6 +31,7 @@ extern void rs6000_va_start (tree, rtx); #endif /* TREE_CODE */ +extern unsigned int rs6000_special_round_type_align (tree, int, int); extern struct rtx_def *rs6000_got_register (rtx); extern struct rtx_def *find_addr_reg (rtx); extern int any_operand (rtx, enum machine_mode); Index: llvm-gcc/gcc/config/rs6000/rs6000.c diff -u llvm-gcc/gcc/config/rs6000/rs6000.c:1.1.1.2 llvm-gcc/gcc/config/rs6000/rs6000.c:1.2 --- llvm-gcc/gcc/config/rs6000/rs6000.c:1.1.1.2 Tue Jan 13 10:49:53 2004 +++ llvm-gcc/gcc/config/rs6000/rs6000.c Tue Jul 26 11:50:33 2005 @@ -2096,6 +2096,24 @@ || (op == XEXP (DECL_RTL (current_function_decl), 0)))); } +/* Darwin, AIX increases natural record alignment to doubleword if the first +field is an FP double while the FP fields remain word aligned. */ + +unsigned int +rs6000_special_round_type_align (tree type, int computed, int specified) +{ + tree field = TYPE_FIELDS (type); + + /* Skip all non field decls */ + while (field != NULL && TREE_CODE (field) != FIELD_DECL) + field = TREE_CHAIN (field); + + if (field == NULL || field == type || DECL_MODE (field) != DFmode) + return MAX (computed, specified); + + return MAX (MAX (computed, specified), 64); +} + /* Return 1 if this operand is a valid input for a move insn. */ int From lattner at cs.uiuc.edu Tue Jul 26 13:02:53 2005 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Tue, 26 Jul 2005 13:02:53 -0500 Subject: [llvm-commits] CVS: llvm-gcc/gcc/config/rs6000/darwin.h rs6000.c Message-ID: <200507261802.NAA00778@zion.cs.uiuc.edu> Changes in directory llvm-gcc/gcc/config/rs6000: darwin.h updated: 1.4 -> 1.5 rs6000.c updated: 1.2 -> 1.3 --- Log message: Fix a problem where we were not handle 'long long' the same was as 'double' in structs, which is required by the darwin ABI. This patch fixes part of LLVM PR604: http://llvm.cs.uiuc.edu/PR604 , as well as GCC PR23067: http://llvm.cs.uiuc.edu/PR23067 , which is the corresponding mainline GCC version of the problem. --- Diffs of the changes: (+5 -4) darwin.h | 6 +++--- rs6000.c | 3 ++- 2 files changed, 5 insertions(+), 4 deletions(-) Index: llvm-gcc/gcc/config/rs6000/darwin.h diff -u llvm-gcc/gcc/config/rs6000/darwin.h:1.4 llvm-gcc/gcc/config/rs6000/darwin.h:1.5 --- llvm-gcc/gcc/config/rs6000/darwin.h:1.4 Tue Jul 26 11:50:33 2005 +++ llvm-gcc/gcc/config/rs6000/darwin.h Tue Jul 26 13:02:42 2005 @@ -262,12 +262,12 @@ #define ALWAYS_PUSH_CONSTS_USING_REGS_P 1 /* This now supports a natural alignment mode */ -/* Darwin word-aligns FP doubles but doubleword-aligns 64-bit ints. */ +/* Darwin word-aligns FP doubles and 64-bit ints. */ #define ADJUST_FIELD_ALIGN(FIELD, COMPUTED) \ (TARGET_ALIGN_NATURAL ? (COMPUTED) : \ - (TYPE_MODE (TREE_CODE (TREE_TYPE (FIELD)) == ARRAY_TYPE \ + ((1 << (TYPE_MODE (TREE_CODE (TREE_TYPE (FIELD)) == ARRAY_TYPE \ ? get_inner_array_type (FIELD) \ - : TREE_TYPE (FIELD)) == DFmode \ + : TREE_TYPE (FIELD))) & ((1 << DFmode)|(1 << DImode))) \ ? MIN ((COMPUTED), 32) : (COMPUTED))) /* The maximum alignment for this target (according to LLVM) is 4 bytes, Index: llvm-gcc/gcc/config/rs6000/rs6000.c diff -u llvm-gcc/gcc/config/rs6000/rs6000.c:1.2 llvm-gcc/gcc/config/rs6000/rs6000.c:1.3 --- llvm-gcc/gcc/config/rs6000/rs6000.c:1.2 Tue Jul 26 11:50:33 2005 +++ llvm-gcc/gcc/config/rs6000/rs6000.c Tue Jul 26 13:02:42 2005 @@ -2108,7 +2108,8 @@ while (field != NULL && TREE_CODE (field) != FIELD_DECL) field = TREE_CHAIN (field); - if (field == NULL || field == type || DECL_MODE (field) != DFmode) + if (field == NULL || field == type + || (DECL_MODE (field) != DFmode && DECL_MODE(field) != DImode)) return MAX (computed, specified); return MAX (MAX (computed, specified), 64); From natebegeman at mac.com Tue Jul 26 13:59:18 2005 From: natebegeman at mac.com (Nate Begeman) Date: Tue, 26 Jul 2005 13:59:18 -0500 Subject: [llvm-commits] CVS: llvm/lib/Target/PowerPC/README.txt Message-ID: <200507261859.NAA01862@zion.cs.uiuc.edu> Changes in directory llvm/lib/Target/PowerPC: README.txt updated: 1.22 -> 1.23 --- Log message: Update the PPC readme --- Diffs of the changes: (+2 -6) README.txt | 8 ++------ 1 files changed, 2 insertions(+), 6 deletions(-) Index: llvm/lib/Target/PowerPC/README.txt diff -u llvm/lib/Target/PowerPC/README.txt:1.22 llvm/lib/Target/PowerPC/README.txt:1.23 --- llvm/lib/Target/PowerPC/README.txt:1.22 Mon Apr 11 15:48:57 2005 +++ llvm/lib/Target/PowerPC/README.txt Tue Jul 26 13:59:06 2005 @@ -1,16 +1,12 @@ TODO: -* condition register allocation * gpr0 allocation * implement do-loop -> bdnz transform * implement powerpc-64 for darwin * use stfiwx in float->int +* be able to combine sequences like the following into 2 instructions: + lis r2, ha16(l2__ZTV4Cell) la r2, lo16(l2__ZTV4Cell)(r2) addi r2, r2, 8 * should hint to the branch select pass that it doesn't need to print the second unconditional branch, so we don't end up with things like: b .LBBl42__2E_expand_function_8_674 ; loopentry.24 b .LBBl42__2E_expand_function_8_42 ; NewDefault b .LBBl42__2E_expand_function_8_42 ; NewDefault - -Currently failing tests that should pass: -* MultiSource - |- Applications - | `- hbd: miscompilation From lattner at cs.uiuc.edu Tue Jul 26 14:03:38 2005 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Tue, 26 Jul 2005 14:03:38 -0500 Subject: [llvm-commits] CVS: llvm/lib/Target/PowerPC/PowerPCAsmPrinter.cpp Message-ID: <200507261903.OAA02001@zion.cs.uiuc.edu> Changes in directory llvm/lib/Target/PowerPC: PowerPCAsmPrinter.cpp updated: 1.82 -> 1.83 --- Log message: Wrap some long lines, fix emission of weak global variables --- Diffs of the changes: (+9 -8) PowerPCAsmPrinter.cpp | 17 +++++++++-------- 1 files changed, 9 insertions(+), 8 deletions(-) Index: llvm/lib/Target/PowerPC/PowerPCAsmPrinter.cpp diff -u llvm/lib/Target/PowerPC/PowerPCAsmPrinter.cpp:1.82 llvm/lib/Target/PowerPC/PowerPCAsmPrinter.cpp:1.83 --- llvm/lib/Target/PowerPC/PowerPCAsmPrinter.cpp:1.82 Thu Jul 21 15:44:42 2005 +++ llvm/lib/Target/PowerPC/PowerPCAsmPrinter.cpp Tue Jul 26 14:03:27 2005 @@ -474,11 +474,9 @@ << ".section __DATA,__datacoal_nt,coalesced,no_toc\n"; LinkOnceStubs.insert(name); break; - case GlobalValue::WeakLinkage: // FIXME: Verify correct for weak. - // Nonnull linkonce -> weak - O << "\t.weak " << name << "\n"; - SwitchSection(O, CurSection, ""); - O << "\t.section\t.llvm.linkonce.d." << name << ",\"aw\", at progbits\n"; + case GlobalValue::WeakLinkage: + O << ".weak_definition " << name << '\n' + << ".private_extern " << name << '\n'; break; case GlobalValue::AppendingLinkage: // FIXME: appending linkage variables should go into a section of @@ -647,7 +645,8 @@ << "\t.csect .text[PR]\n"; // Print out module-level global variables - for (Module::const_global_iterator I = M.global_begin(), E = M.global_end(); I != E; ++I) { + for (Module::const_global_iterator I = M.global_begin(), E = M.global_end(); + I != E; ++I) { if (!I->hasInitializer()) continue; @@ -666,7 +665,8 @@ // Output labels for globals if (M.global_begin() != M.global_end()) O << "\t.toc\n"; - for (Module::const_global_iterator I = M.global_begin(), E = M.global_end(); I != E; ++I) { + for (Module::const_global_iterator I = M.global_begin(), E = M.global_end(); + I != E; ++I) { const GlobalVariable *GV = I; // Do not output labels for unused variables if (GV->isExternal() && GV->use_begin() == GV->use_end()) @@ -688,7 +688,8 @@ bool AIXAsmPrinter::doFinalization(Module &M) { const TargetData &TD = TM.getTargetData(); // Print out module-level global variables - for (Module::const_global_iterator I = M.global_begin(), E = M.global_end(); I != E; ++I) { + for (Module::const_global_iterator I = M.global_begin(), E = M.global_end(); + I != E; ++I) { if (I->hasInitializer() || I->hasExternalLinkage()) continue; From lattner at cs.uiuc.edu Tue Jul 26 14:08:02 2005 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Tue, 26 Jul 2005 14:08:02 -0500 Subject: [llvm-commits] CVS: llvm/lib/Target/PowerPC/README.txt Message-ID: <200507261908.OAA02104@zion.cs.uiuc.edu> Changes in directory llvm/lib/Target/PowerPC: README.txt updated: 1.23 -> 1.24 --- Log message: add a note about the red zone --- Diffs of the changes: (+5 -1) README.txt | 6 +++++- 1 files changed, 5 insertions(+), 1 deletion(-) Index: llvm/lib/Target/PowerPC/README.txt diff -u llvm/lib/Target/PowerPC/README.txt:1.23 llvm/lib/Target/PowerPC/README.txt:1.24 --- llvm/lib/Target/PowerPC/README.txt:1.23 Tue Jul 26 13:59:06 2005 +++ llvm/lib/Target/PowerPC/README.txt Tue Jul 26 14:07:51 2005 @@ -3,8 +3,12 @@ * implement do-loop -> bdnz transform * implement powerpc-64 for darwin * use stfiwx in float->int +* take advantage of the darwin red zone in PPC32RegisterInfo.cpp * be able to combine sequences like the following into 2 instructions: - lis r2, ha16(l2__ZTV4Cell) la r2, lo16(l2__ZTV4Cell)(r2) addi r2, r2, 8 + lis r2, ha16(l2__ZTV4Cell) + la r2, lo16(l2__ZTV4Cell)(r2) + addi r2, r2, 8 + * should hint to the branch select pass that it doesn't need to print the second unconditional branch, so we don't end up with things like: b .LBBl42__2E_expand_function_8_674 ; loopentry.24 From lattner at cs.uiuc.edu Tue Jul 26 17:06:15 2005 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Tue, 26 Jul 2005 17:06:15 -0500 Subject: [llvm-commits] CVS: llvm-gcc/gcc/llvm-expand.c Message-ID: <200507262206.RAA06315@zion.cs.uiuc.edu> Changes in directory llvm-gcc/gcc: llvm-expand.c updated: 1.107 -> 1.108 --- Log message: * Fix a whole bunch of random warnings compiling this file. * The isConstructorAllZeros part of the patch fixes PR607: http://llvm.cs.uiuc.edu/PR607 . --- Diffs of the changes: (+48 -16) llvm-expand.c | 64 +++++++++++++++++++++++++++++++++++++++++++--------------- 1 files changed, 48 insertions(+), 16 deletions(-) Index: llvm-gcc/gcc/llvm-expand.c diff -u llvm-gcc/gcc/llvm-expand.c:1.107 llvm-gcc/gcc/llvm-expand.c:1.108 --- llvm-gcc/gcc/llvm-expand.c:1.107 Fri Jul 22 13:50:31 2005 +++ llvm-gcc/gcc/llvm-expand.c Tue Jul 26 17:05:49 2005 @@ -725,7 +725,7 @@ /* Debug info */ llvm_value *dbg_global_memloc; - int LastDebugLine, LastDebugCol; + unsigned LastDebugLine, LastDebugCol; llvm_basicblock *LastDebugBB; } llvm_expand_info; @@ -3935,9 +3935,6 @@ unsigned FieldIndexVal = llvm_constant_get_integer_val(V2C(FieldIndex)); llvm_type *FieldType = GET_STRUCT_TYPE_ELEMENT(Ty, FieldIndexVal); unsigned FieldOffset = GetFieldOffset(field); - assert(TREE_CODE(DECL_FIELD_OFFSET(field)) == INTEGER_CST && - "Can't handle structures with variable sized objects in them"); - /* * Attempt to get the size of the field. @@ -3946,6 +3943,9 @@ tree FieldSizeTree = DECL_SIZE(field); llvm_value *ElVal; + assert(TREE_CODE(DECL_FIELD_OFFSET(field)) == INTEGER_CST && + "Can't handle structures with variable sized objects in them"); + /* * TODO: * Currently, we can skip the size checking code if we don't know the @@ -4398,9 +4398,9 @@ tree fndecl = TREE_OPERAND (TREE_OPERAND (exp, 0), 0); llvm_type *FnType = llvm_type_get_from_tree(TREE_TYPE(fndecl)); llvm_type *VAListTy = GET_FUNCTION_TYPE_ARGUMENT(FnType, 0); - llvm_type *FnTy = llvm_type_create_function(1, VoidTy); + llvm_type *FnTy, *Ty = llvm_type_create_function(1, VoidTy); FnTy->Elements[1] = VAListTy; - llvm_type *Ty = llvm_type_get_cannonical_function(FnTy); + Ty = llvm_type_get_cannonical_function(FnTy); llvm_va_start_fn = CreateIntrinsicFnWithType("llvm.va_start", Ty); } @@ -4469,6 +4469,10 @@ static llvm_function *llvm_va_copy_fn = 0; llvm_type *VAListType; + tree SrcArg; + llvm_value *DestAddr; + llvm_instruction *I; + if (!llvm_va_copy_fn) { llvm_type *VACopyTy = llvm_type_get_from_tree(TREE_TYPE(fndecl)); llvm_type *VAListTyPtr = GET_FUNCTION_TYPE_ARGUMENT(VACopyTy, 0); @@ -4479,9 +4483,9 @@ llvm_va_copy_fn = CreateIntrinsicFnWithType("llvm.va_copy", FnTy); } - tree SrcArg = TREE_VALUE(TREE_CHAIN(TREE_OPERAND(exp, 1))); - llvm_value *DestAddr = llvm_expand_expr(Fn, TREE_VALUE(TREE_OPERAND(exp, 1)), 0); - llvm_instruction *I = llvm_instruction_new(VoidTy, "", O_Call, 3); + SrcArg = TREE_VALUE(TREE_CHAIN(TREE_OPERAND(exp, 1))); + DestAddr = llvm_expand_expr(Fn, TREE_VALUE(TREE_OPERAND(exp, 1)), 0); + I = llvm_instruction_new(VoidTy, "", O_Call, 3); I->Operands[0] = G2V(llvm_va_copy_fn); I->Operands[1] = DestAddr; I->Operands[2] = llvm_expand_lvalue_expr(Fn, SrcArg, 0, 0); @@ -4553,7 +4557,7 @@ struct UnaryBuiltinList *Next; }; -llvm_function *GetUnaryBuiltin(const char *Name, llvm_type *ArgTy) { +static llvm_function *GetUnaryBuiltin(const char *Name, llvm_type *ArgTy) { llvm_type *FnTy; static struct UnaryBuiltinList *UnaryBuiltins = 0; @@ -4748,11 +4752,11 @@ case BUILT_IN_SQRT: case BUILT_IN_SQRTF: case BUILT_IN_SQRTL: - // If errno math has been disabled, expand these to llvm.sqrt calls. + /* If errno math has been disabled, expand these to llvm.sqrt calls. */ if (!flag_errno_math) { return llvm_expand_builtin_unaryop(Fn, DestTy, arglist, "llvm.sqrt"); } else { - // Otherwise, expand as a call to sqrt*. + /* Otherwise, expand as a call to sqrt*. */ return llvm_expand_call (Fn, exp, DestLoc); } @@ -5184,6 +5188,29 @@ return V2C(llvm_constant_new(llvm_type_get_array(ElTy, Len), Buffer)); } +/* isConstructorAllZeros - This little hack is used to tell if a constructor + * is all zeros, in which case we can use zeroinitializer. + */ +static bool isConstructorAllZeros(tree cst) { + tree elt; + if (TREE_CODE(cst) == INTEGER_CST) + return (unsigned HOST_WIDE_INT)TREE_INT_CST_HIGH(cst) == 0 && + (unsigned HOST_WIDE_INT)TREE_INT_CST_LOW(cst) == 0; + else if (TREE_CODE(cst) == REAL_CST) { + long RealArr[2]; + RealArr[0] = RealArr[1] = 0; + REAL_VALUE_TO_TARGET_DOUBLE(TREE_REAL_CST(cst), RealArr); + return RealArr[0] == 0 && RealArr[1] == 0; + } else if (TREE_CODE(cst) != CONSTRUCTOR) + return 0; + + for (elt = CONSTRUCTOR_ELTS(cst); elt; elt = TREE_CHAIN(elt)) + if (TREE_VALUE(elt)) /* Ignore missing fields. */ + if (!isConstructorAllZeros(TREE_VALUE (elt))) + return 0; + return 1; +} + /* llvm_expand_constant_expr - This function is responsible for translating a * constant tree expression into a suitable LLVM constant value. This is * separate from other expression evaluation code because it is used to compute @@ -5335,7 +5362,11 @@ llvm_value **Elements = llvm_expand_constructor_elements(0, 0, exp, 0); if (Elements[0]->Ty == ReqTy) Val = Elements[0]; - else { + else if (isConstructorAllZeros(exp)) { + /* If we can use zeroinitializer, do so. */ + Val = llvm_constant_get_null(ReqTy); + } else { + /* Cannot expand an aggregate constructor into a scalar context. */ assert(0 && "Couldn't expand constructor in this context!"); } } else { @@ -6668,9 +6699,10 @@ /* If the divisor is a power of two, we can do the xform. */ if (Divisor && (Divisor & (Divisor-1)) == 0) { + unsigned ShAmt; Opcode = O_Shr; /* Perform a signed SHR */ - unsigned ShAmt = 0; + ShAmt = 0; for (; Divisor > 1; Divisor >>= 1) ++ShAmt; op1 = llvm_constant_new_integral(UByteTy, ShAmt); @@ -8111,7 +8143,7 @@ append_inst(Fn, load_dbg_inst); append_inst(Fn, stoppoint_inst); - store_dbg_inst = create_store_inst(stoppoint_inst, + store_dbg_inst = create_store_inst(D2V(stoppoint_inst), Fn->ExpandInfo->dbg_global_memloc, 0); append_inst(Fn, store_dbg_inst); @@ -8137,7 +8169,7 @@ /* see above for description of the 'alloca trick':*/ - store_dbg_inst = create_store_inst(dbg_call_reg_end_inst, + store_dbg_inst = create_store_inst(D2V(dbg_call_reg_end_inst), Fn->ExpandInfo->dbg_global_memloc, 0); llvm_ilist_push_front(llvm_instruction, last_block->Instructions, From lattner at cs.uiuc.edu Tue Jul 26 17:09:05 2005 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Tue, 26 Jul 2005 17:09:05 -0500 Subject: [llvm-commits] CVS: llvm/test/Regression/CFrontend/2005-07-26-UnionInitCrash.c Message-ID: <200507262209.RAA06407@zion.cs.uiuc.edu> Changes in directory llvm/test/Regression/CFrontend: 2005-07-26-UnionInitCrash.c added (r1.1) --- Log message: Testcase for PR607: http://llvm.cs.uiuc.edu/PR607 --- Diffs of the changes: (+3 -0) 2005-07-26-UnionInitCrash.c | 3 +++ 1 files changed, 3 insertions(+) Index: llvm/test/Regression/CFrontend/2005-07-26-UnionInitCrash.c diff -c /dev/null llvm/test/Regression/CFrontend/2005-07-26-UnionInitCrash.c:1.1 *** /dev/null Tue Jul 26 17:09:03 2005 --- llvm/test/Regression/CFrontend/2005-07-26-UnionInitCrash.c Tue Jul 26 17:08:53 2005 *************** *** 0 **** --- 1,3 ---- + // PR607 + // RUN: %llvmgcc %s -S -o - + union { char bytes[8]; double alignment; }EQ1 = {0,0,0,0,0,0,0,0}; From lattner at cs.uiuc.edu Tue Jul 26 19:24:52 2005 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Tue, 26 Jul 2005 19:24:52 -0500 Subject: [llvm-commits] CVS: llvm-gcc/gcc/llvm-expand.c Message-ID: <200507270024.TAA07991@zion.cs.uiuc.edu> Changes in directory llvm-gcc/gcc: llvm-expand.c updated: 1.108 -> 1.109 --- Log message: fix a major 'oops' in my previous patch --- Diffs of the changes: (+1 -1) llvm-expand.c | 2 +- 1 files changed, 1 insertion(+), 1 deletion(-) Index: llvm-gcc/gcc/llvm-expand.c diff -u llvm-gcc/gcc/llvm-expand.c:1.108 llvm-gcc/gcc/llvm-expand.c:1.109 --- llvm-gcc/gcc/llvm-expand.c:1.108 Tue Jul 26 17:05:49 2005 +++ llvm-gcc/gcc/llvm-expand.c Tue Jul 26 19:24:41 2005 @@ -4398,7 +4398,7 @@ tree fndecl = TREE_OPERAND (TREE_OPERAND (exp, 0), 0); llvm_type *FnType = llvm_type_get_from_tree(TREE_TYPE(fndecl)); llvm_type *VAListTy = GET_FUNCTION_TYPE_ARGUMENT(FnType, 0); - llvm_type *FnTy, *Ty = llvm_type_create_function(1, VoidTy); + llvm_type *Ty, *FnTy = llvm_type_create_function(1, VoidTy); FnTy->Elements[1] = VAListTy; Ty = llvm_type_get_cannonical_function(FnTy); llvm_va_start_fn = CreateIntrinsicFnWithType("llvm.va_start", Ty); From jeffc at jolt-lang.org Wed Jul 27 00:53:59 2005 From: jeffc at jolt-lang.org (Jeff Cohen) Date: Wed, 27 Jul 2005 00:53:59 -0500 Subject: [llvm-commits] CVS: llvm/include/llvm/Config/config.h.in Message-ID: <200507270553.AAA12801@zion.cs.uiuc.edu> Changes in directory llvm/include/llvm/Config: config.h.in updated: 1.53 -> 1.54 --- Log message: Eliminate tabs and trailing spaces. --- Diffs of the changes: (+3 -3) config.h.in | 6 +++--- 1 files changed, 3 insertions(+), 3 deletions(-) Index: llvm/include/llvm/Config/config.h.in diff -u llvm/include/llvm/Config/config.h.in:1.53 llvm/include/llvm/Config/config.h.in:1.54 --- llvm/include/llvm/Config/config.h.in:1.53 Thu Jul 14 00:19:12 2005 +++ llvm/include/llvm/Config/config.h.in Wed Jul 27 00:53:43 2005 @@ -449,9 +449,9 @@ /* If using the C implementation of alloca, define if you know the direction of stack growth for your system; otherwise it will be automatically deduced at run-time. - STACK_DIRECTION > 0 => grows toward higher addresses - STACK_DIRECTION < 0 => grows toward lower addresses - STACK_DIRECTION = 0 => direction of growth unknown */ + STACK_DIRECTION > 0 => grows toward higher addresses + STACK_DIRECTION < 0 => grows toward lower addresses + STACK_DIRECTION = 0 => direction of growth unknown */ #undef STACK_DIRECTION /* Define to 1 if the `S_IS*' macros in do not work properly. */ From jeffc at jolt-lang.org Wed Jul 27 00:54:00 2005 From: jeffc at jolt-lang.org (Jeff Cohen) Date: Wed, 27 Jul 2005 00:54:00 -0500 Subject: [llvm-commits] CVS: llvm/include/llvm/BasicBlock.h Message-ID: <200507270554.AAA12811@zion.cs.uiuc.edu> Changes in directory llvm/include/llvm: BasicBlock.h updated: 1.54 -> 1.55 --- Log message: Eliminate tabs and trailing spaces. --- Diffs of the changes: (+1 -1) BasicBlock.h | 2 +- 1 files changed, 1 insertion(+), 1 deletion(-) Index: llvm/include/llvm/BasicBlock.h diff -u llvm/include/llvm/BasicBlock.h:1.54 llvm/include/llvm/BasicBlock.h:1.55 --- llvm/include/llvm/BasicBlock.h:1.54 Sun Apr 24 19:31:53 2005 +++ llvm/include/llvm/BasicBlock.h Wed Jul 27 00:53:43 2005 @@ -160,7 +160,7 @@ /// splitBasicBlock - This splits a basic block into two at the specified /// instruction. Note that all instructions BEFORE the specified iterator /// stay as part of the original basic block, an unconditional branch is added - /// to the original BB, and the rest of the instructions in the BB are moved + /// to the original BB, and the rest of the instructions in the BB are moved /// to the new BB, including the old terminator. The newly formed BasicBlock /// is returned. This function invalidates the specified iterator. /// From jeffc at jolt-lang.org Wed Jul 27 00:54:00 2005 From: jeffc at jolt-lang.org (Jeff Cohen) Date: Wed, 27 Jul 2005 00:54:00 -0500 Subject: [llvm-commits] CVS: llvm/lib/Target/X86/X86InstrInfo.h X86Subtarget.h Message-ID: <200507270554.AAA12807@zion.cs.uiuc.edu> Changes in directory llvm/lib/Target/X86: X86InstrInfo.h updated: 1.47 -> 1.48 X86Subtarget.h updated: 1.2 -> 1.3 --- Log message: Eliminate tabs and trailing spaces. --- Diffs of the changes: (+6 -6) X86InstrInfo.h | 2 +- X86Subtarget.h | 10 +++++----- 2 files changed, 6 insertions(+), 6 deletions(-) Index: llvm/lib/Target/X86/X86InstrInfo.h diff -u llvm/lib/Target/X86/X86InstrInfo.h:1.47 llvm/lib/Target/X86/X86InstrInfo.h:1.48 --- llvm/lib/Target/X86/X86InstrInfo.h:1.47 Wed Jul 6 13:59:04 2005 +++ llvm/lib/Target/X86/X86InstrInfo.h Wed Jul 27 00:53:44 2005 @@ -107,7 +107,7 @@ DA = 5 << Op0Shift, DB = 6 << Op0Shift, DC = 7 << Op0Shift, DD = 8 << Op0Shift, DE = 9 << Op0Shift, DF = 10 << Op0Shift, - + // XS, XD - These prefix codes are for single and double precision scalar // floating point operations performed in the SSE registers. XD = 11 << Op0Shift, XS = 12 << Op0Shift, Index: llvm/lib/Target/X86/X86Subtarget.h diff -u llvm/lib/Target/X86/X86Subtarget.h:1.2 llvm/lib/Target/X86/X86Subtarget.h:1.3 --- llvm/lib/Target/X86/X86Subtarget.h:1.2 Mon Jul 11 21:36:10 2005 +++ llvm/lib/Target/X86/X86Subtarget.h Wed Jul 27 00:53:44 2005 @@ -24,10 +24,10 @@ /// stackAlignment - The minimum alignment known to hold of the stack frame on /// entry to the function and which must be maintained by every function. unsigned stackAlignment; - + /// Used by instruction selector bool indirectExternAndWeakGlobals; - + /// Used by the asm printer bool asmDarwinLinkerStubs; bool asmLeadingUnderscore; @@ -36,7 +36,7 @@ bool asmPrintDotLCommConstants; bool asmPrintConstantAlignment; public: - /// This constructor initializes the data members to match that + /// This constructor initializes the data members to match that /// of the specified module. /// X86Subtarget(const Module &M); @@ -45,9 +45,9 @@ /// stack frame on entry to the function and which must be maintained by every /// function for this subtarget. unsigned getStackAlignment() const { return stackAlignment; } - + /// Returns true if the instruction selector should treat global values - /// referencing external or weak symbols as indirect rather than direct + /// referencing external or weak symbols as indirect rather than direct /// references. bool getIndirectExternAndWeakGlobals() const { return indirectExternAndWeakGlobals; From jeffc at jolt-lang.org Wed Jul 27 00:54:00 2005 From: jeffc at jolt-lang.org (Jeff Cohen) Date: Wed, 27 Jul 2005 00:54:00 -0500 Subject: [llvm-commits] CVS: llvm/include/llvm/CodeGen/MachineRelocation.h SelectionDAGNodes.h Message-ID: <200507270554.AAA12815@zion.cs.uiuc.edu> Changes in directory llvm/include/llvm/CodeGen: MachineRelocation.h updated: 1.6 -> 1.7 SelectionDAGNodes.h updated: 1.44 -> 1.45 --- Log message: Eliminate tabs and trailing spaces. --- Diffs of the changes: (+4 -4) MachineRelocation.h | 4 ++-- SelectionDAGNodes.h | 4 ++-- 2 files changed, 4 insertions(+), 4 deletions(-) Index: llvm/include/llvm/CodeGen/MachineRelocation.h diff -u llvm/include/llvm/CodeGen/MachineRelocation.h:1.6 llvm/include/llvm/CodeGen/MachineRelocation.h:1.7 --- llvm/include/llvm/CodeGen/MachineRelocation.h:1.6 Fri Jul 22 15:46:42 2005 +++ llvm/include/llvm/CodeGen/MachineRelocation.h Wed Jul 27 00:53:43 2005 @@ -55,7 +55,7 @@ public: MachineRelocation(unsigned Offset, unsigned RelocationType, GlobalValue *GV, - intptr_t cst = 0, bool DoesntNeedFunctionStub = 0, + intptr_t cst = 0, bool DoesntNeedFunctionStub = 0, bool GOTrelative = 0) : OffsetTypeExternal(Offset + (RelocationType << 26)), ConstantVal(cst), GOTRelative(GOTrelative), isConstPool(0) { @@ -175,7 +175,7 @@ } /// getGOTIndex - Once this has been resolved to an entry in the GOT, - /// this returns that index. The index is from the lowest address entry + /// this returns that index. The index is from the lowest address entry /// in the GOT. unsigned getGOTIndex() const { return Target.GOTIndex; Index: llvm/include/llvm/CodeGen/SelectionDAGNodes.h diff -u llvm/include/llvm/CodeGen/SelectionDAGNodes.h:1.44 llvm/include/llvm/CodeGen/SelectionDAGNodes.h:1.45 --- llvm/include/llvm/CodeGen/SelectionDAGNodes.h:1.44 Sat Jul 9 20:55:14 2005 +++ llvm/include/llvm/CodeGen/SelectionDAGNodes.h Wed Jul 27 00:53:43 2005 @@ -508,7 +508,7 @@ assert(ResNo < Values.size() && "Illegal result number!"); return Values[ResNo]; } - + typedef std::vector::const_iterator value_iterator; value_iterator value_begin() const { return Values.begin(); } value_iterator value_end() const { return Values.end(); } @@ -523,7 +523,7 @@ /// setAdjCallChain - This method should only be used by the legalizer. void setAdjCallChain(SDOperand N); - + protected: friend class SelectionDAG; From jeffc at jolt-lang.org Wed Jul 27 00:54:01 2005 From: jeffc at jolt-lang.org (Jeff Cohen) Date: Wed, 27 Jul 2005 00:54:01 -0500 Subject: [llvm-commits] CVS: llvm/include/llvm/Analysis/Interval.h Message-ID: <200507270554.AAA12819@zion.cs.uiuc.edu> Changes in directory llvm/include/llvm/Analysis: Interval.h updated: 1.20 -> 1.21 --- Log message: Eliminate tabs and trailing spaces. --- Diffs of the changes: (+2 -2) Interval.h | 4 ++-- 1 files changed, 2 insertions(+), 2 deletions(-) Index: llvm/include/llvm/Analysis/Interval.h diff -u llvm/include/llvm/Analysis/Interval.h:1.20 llvm/include/llvm/Analysis/Interval.h:1.21 --- llvm/include/llvm/Analysis/Interval.h:1.20 Thu Apr 21 15:16:31 2005 +++ llvm/include/llvm/Analysis/Interval.h Wed Jul 27 00:53:43 2005 @@ -110,7 +110,7 @@ inline Interval::succ_iterator succ_end(Interval *I) { return I->Successors.end(); } - + /// pred_begin/pred_end - define methods so that Intervals may be used /// just like BasicBlocks can with the pred_* functions, and *::pred_iterator. /// @@ -128,7 +128,7 @@ static NodeType *getEntryNode(Interval *I) { return I; } /// nodes_iterator/begin/end - Allow iteration over all nodes in the graph - static inline ChildIteratorType child_begin(NodeType *N) { + static inline ChildIteratorType child_begin(NodeType *N) { return succ_begin(N); } static inline ChildIteratorType child_end(NodeType *N) { From jeffc at jolt-lang.org Wed Jul 27 00:54:01 2005 From: jeffc at jolt-lang.org (Jeff Cohen) Date: Wed, 27 Jul 2005 00:54:01 -0500 Subject: [llvm-commits] CVS: llvm/include/llvm/System/Mutex.h Path.h Process.h Message-ID: <200507270554.AAA12825@zion.cs.uiuc.edu> Changes in directory llvm/include/llvm/System: Mutex.h updated: 1.3 -> 1.4 Path.h updated: 1.26 -> 1.27 Process.h updated: 1.8 -> 1.9 --- Log message: Eliminate tabs and trailing spaces. --- Diffs of the changes: (+32 -32) Mutex.h | 6 +++--- Path.h | 56 ++++++++++++++++++++++++++++---------------------------- Process.h | 2 +- 3 files changed, 32 insertions(+), 32 deletions(-) Index: llvm/include/llvm/System/Mutex.h diff -u llvm/include/llvm/System/Mutex.h:1.3 llvm/include/llvm/System/Mutex.h:1.4 --- llvm/include/llvm/System/Mutex.h:1.3 Tue Jul 12 21:19:59 2005 +++ llvm/include/llvm/System/Mutex.h Wed Jul 27 00:53:43 2005 @@ -49,7 +49,7 @@ /// Attempts to release the lock. If the lock is held by the current /// thread, the lock is released allowing other threads to acquire the - /// lock. + /// lock. /// @returns false if any kind of error occurs, true otherwise. /// @brief Unconditionally release the lock. bool release(void); @@ -61,7 +61,7 @@ /// available, true otherwise. /// @brief Try to acquire the lock. bool tryacquire(); - + //@} /// @name Platform Dependent Data /// @{ @@ -71,7 +71,7 @@ /// @} /// @name Do Not Implement /// @{ - private: + private: Mutex(const Mutex & original); void operator=(const Mutex &); /// @} Index: llvm/include/llvm/System/Path.h diff -u llvm/include/llvm/System/Path.h:1.26 llvm/include/llvm/System/Path.h:1.27 --- llvm/include/llvm/System/Path.h:1.26 Thu Jul 7 22:08:58 2005 +++ llvm/include/llvm/System/Path.h Wed Jul 27 00:53:43 2005 @@ -27,20 +27,20 @@ /// in the operating system's filesystem and provides various basic operations /// on it. Note that this class only represents the name of a path to a file /// or directory which may or may not be valid for a given machine's file - /// system. The class is patterned after the java.io.File class with various - /// extensions and several omissions (not relevant to LLVM). A Path object - /// ensures that the path it encapsulates is syntactically valid for the - /// operating system it is running on but does not ensure correctness for - /// any particular file system. That is, a syntactically valid path might + /// system. The class is patterned after the java.io.File class with various + /// extensions and several omissions (not relevant to LLVM). A Path object + /// ensures that the path it encapsulates is syntactically valid for the + /// operating system it is running on but does not ensure correctness for + /// any particular file system. That is, a syntactically valid path might /// specify path components that do not exist in the file system and using /// such a Path to act on the file system could produce errors. There is one - /// invalid Path value which is permitted: the empty path. The class should - /// never allow a syntactically invalid non-empty path name to be assigned. + /// invalid Path value which is permitted: the empty path. The class should + /// never allow a syntactically invalid non-empty path name to be assigned. /// Empty paths are required in order to indicate an error result in some - /// situations. If the path is empty, the isValid operation will return - /// false. All operations will fail if isValid is false. Operations that + /// situations. If the path is empty, the isValid operation will return + /// false. All operations will fail if isValid is false. Operations that /// change the path will either return false if it would cause a syntactically - /// invalid path name (in which case the Path object is left unchanged) or + /// invalid path name (in which case the Path object is left unchanged) or /// throw an std::string exception indicating the error. The methods are /// grouped into four basic categories: Path Accessors (provide information /// about the path without accessing disk), Disk Accessors (provide @@ -323,16 +323,16 @@ bool isDynamicLibrary() const; /// This function determines if the path name references an existing file - /// or directory in the file system. - /// @returns true if the pathname references an existing file or + /// or directory in the file system. + /// @returns true if the pathname references an existing file or /// directory. /// @brief Determines if the path is a file or directory in /// the file system. bool exists() const; /// This function determines if the path name references a readable file - /// or directory in the file system. This function checks for - /// the existence and readability (by the current program) of the file + /// or directory in the file system. This function checks for + /// the existence and readability (by the current program) of the file /// or directory. /// @returns true if the pathname references a readable file. /// @brief Determines if the path is a readable file or directory @@ -340,8 +340,8 @@ bool canRead() const; /// This function determines if the path name references a writable file - /// or directory in the file system. This function checks for the - /// existence and writability (by the current program) of the file or + /// or directory in the file system. This function checks for the + /// existence and writability (by the current program) of the file or /// directory. /// @returns true if the pathname references a writable file. /// @brief Determines if the path is a writable file or directory @@ -349,7 +349,7 @@ bool canWrite() const; /// This function determines if the path name references an executable - /// file in the file system. This function checks for the existence and + /// file in the file system. This function checks for the existence and /// executability (by the current program) of the file. /// @returns true if the pathname references an executable file. /// @brief Determines if the path is an executable file in the file @@ -400,7 +400,7 @@ /// This method sets the Path object to \p unverified_path. This can fail /// if the \p unverified_path does not pass the syntactic checks of the - /// isValid() method. If verification fails, the Path object remains + /// isValid() method. If verification fails, the Path object remains /// unchanged and false is returned. Otherwise true is returned and the /// Path object takes on the path value of \p unverified_path /// @returns true if the path was set, false otherwise. @@ -417,7 +417,7 @@ /// The \p component is added to the end of the Path if it is a legal /// name for the operating system. A directory separator will be added if - /// needed. + /// needed. /// @returns false if the path component could not be added. /// @brief Appends one path component to the Path. bool appendComponent( const std::string& component ); @@ -469,7 +469,7 @@ /// @brief Make the file readable; void makeExecutableOnDisk(); - /// This method allows the last modified time stamp and permission bits + /// This method allows the last modified time stamp and permission bits /// to be set on the disk object referenced by the Path. /// @throws std::string if an error occurs. /// @returns true @@ -480,8 +480,8 @@ /// same name as the Path object. The \p create_parents parameter controls /// whether intermediate directories are created or not. if \p /// create_parents is true, then an attempt will be made to create all - /// intermediate directories, as needed. If \p create_parents is false, - /// then only the final directory component of the Path name will be + /// intermediate directories, as needed. If \p create_parents is false, + /// then only the final directory component of the Path name will be /// created. The created directory will have no entries. /// @returns false if the Path does not reference a directory, true /// otherwise. @@ -507,7 +507,7 @@ /// file is created. Note that this will both change the Path object /// *and* create the corresponding file. This function will ensure that /// the newly generated temporary file name is unique in the file system. - /// @param reuse_current When set to true, this parameter indicates that + /// @param reuse_current When set to true, this parameter indicates that /// if the current file name does not exist then it will be used without /// modification. /// @returns true if successful, false if the file couldn't be created. @@ -517,18 +517,18 @@ bool createTemporaryFileOnDisk(bool reuse_current = false); /// This method renames the file referenced by \p this as \p newName. The - /// file referenced by \p this must exist. The file referenced by + /// file referenced by \p this must exist. The file referenced by /// \p newName does not need to exist. /// @returns true /// @throws std::string if there is an file system error. /// @brief Rename one file as another. bool renamePathOnDisk(const Path& newName); - /// This method attempts to destroy the file or directory named by the + /// This method attempts to destroy the file or directory named by the /// last component of the Path. If the Path refers to a directory and the - /// \p destroy_contents is false, an attempt will be made to remove just - /// the directory (the final Path component). If \p destroy_contents is - /// true, an attempt will be made to remove the entire contents of the + /// \p destroy_contents is false, an attempt will be made to remove just + /// the directory (the final Path component). If \p destroy_contents is + /// true, an attempt will be made to remove the entire contents of the /// directory, recursively. If the Path refers to a file, the /// \p destroy_contents parameter is ignored. /// @param destroy_contents Indicates whether the contents of a destroyed Index: llvm/include/llvm/System/Process.h diff -u llvm/include/llvm/System/Process.h:1.8 llvm/include/llvm/System/Process.h:1.9 --- llvm/include/llvm/System/Process.h:1.8 Thu May 5 17:31:47 2005 +++ llvm/include/llvm/System/Process.h Wed Jul 27 00:53:43 2005 @@ -67,7 +67,7 @@ /// Not all operating systems support this feature. Where it is not /// supported, the function should return 65536 as the value. static int GetCurrentUserId(); - + /// This static function will return the process' current group id number. /// Not all operating systems support this feature. Where it is not /// supported, the function should return 65536 as the value. From jeffc at jolt-lang.org Wed Jul 27 00:54:01 2005 From: jeffc at jolt-lang.org (Jeff Cohen) Date: Wed, 27 Jul 2005 00:54:01 -0500 Subject: [llvm-commits] CVS: llvm/lib/Target/PowerPC/PPC32Relocations.h Message-ID: <200507270554.AAA12900@zion.cs.uiuc.edu> Changes in directory llvm/lib/Target/PowerPC: PPC32Relocations.h updated: 1.4 -> 1.5 --- Log message: Eliminate tabs and trailing spaces. --- Diffs of the changes: (+1 -1) PPC32Relocations.h | 2 +- 1 files changed, 1 insertion(+), 1 deletion(-) Index: llvm/lib/Target/PowerPC/PPC32Relocations.h diff -u llvm/lib/Target/PowerPC/PPC32Relocations.h:1.4 llvm/lib/Target/PowerPC/PPC32Relocations.h:1.5 --- llvm/lib/Target/PowerPC/PPC32Relocations.h:1.4 Wed Jun 8 12:44:48 2005 +++ llvm/lib/Target/PowerPC/PPC32Relocations.h Wed Jul 27 00:53:43 2005 @@ -16,7 +16,7 @@ #include "llvm/CodeGen/MachineRelocation.h" -// Hack to rid us of a PPC pre-processor symbol which is erroneously +// Hack to rid us of a PPC pre-processor symbol which is erroneously // defined in a PowerPC header file (bug in Linux/PPC) #ifdef PPC #undef PPC From jeffc at jolt-lang.org Wed Jul 27 00:54:01 2005 From: jeffc at jolt-lang.org (Jeff Cohen) Date: Wed, 27 Jul 2005 00:54:01 -0500 Subject: [llvm-commits] CVS: llvm/lib/Target/SparcV9/LiveVar/BBLiveVar.cpp Message-ID: <200507270554.AAA12870@zion.cs.uiuc.edu> Changes in directory llvm/lib/Target/SparcV9/LiveVar: BBLiveVar.cpp updated: 1.49 -> 1.50 --- Log message: Eliminate tabs and trailing spaces. --- Diffs of the changes: (+15 -15) BBLiveVar.cpp | 30 +++++++++++++++--------------- 1 files changed, 15 insertions(+), 15 deletions(-) Index: llvm/lib/Target/SparcV9/LiveVar/BBLiveVar.cpp diff -u llvm/lib/Target/SparcV9/LiveVar/BBLiveVar.cpp:1.49 llvm/lib/Target/SparcV9/LiveVar/BBLiveVar.cpp:1.50 --- llvm/lib/Target/SparcV9/LiveVar/BBLiveVar.cpp:1.49 Thu Apr 21 18:27:35 2005 +++ llvm/lib/Target/SparcV9/LiveVar/BBLiveVar.cpp Wed Jul 27 00:53:43 2005 @@ -54,12 +54,12 @@ for (MachineInstr::const_val_op_iterator OpI = MI->begin(), OpE = MI->end(); OpI != OpE; ++OpI) if (OpI.isDef()) // add to Defs if this operand is a def - addDef(*OpI); + addDef(*OpI); // do for implicit operands as well for (unsigned i = 0; i < MI->getNumImplicitRefs(); ++i) if (MI->getImplicitOp(i).isDef()) - addDef(MI->getImplicitRef(i)); + addDef(MI->getImplicitRef(i)); // iterate over MI operands to find uses for (MachineInstr::const_val_op_iterator OpI = MI->begin(), OpE = MI->end(); @@ -67,7 +67,7 @@ const Value *Op = *OpI; if (isa(Op)) - continue; // don't process labels + continue; // don't process labels if (OpI.isUse()) { // add to Uses only if this operand is a use // @@ -79,16 +79,16 @@ // Put Phi operands in UseSet for the incoming edge, not node. // They must not "hide" later defs, and must be handled specially // during set propagation over the CFG. - if (MI->getOpcode() == V9::PHI) { // for a phi node + if (MI->getOpcode() == V9::PHI) { // for a phi node const Value *ArgVal = Op; - const BasicBlock *PredBB = cast(*++OpI); // next ptr is BB - - PredToEdgeInSetMap[PredBB].insert(ArgVal); - - if (DEBUG_LV >= LV_DEBUG_Verbose) - std::cerr << " - phi operand " << RAV(ArgVal) << " came from BB " + const BasicBlock *PredBB = cast(*++OpI); // next ptr is BB + + PredToEdgeInSetMap[PredBB].insert(ArgVal); + + if (DEBUG_LV >= LV_DEBUG_Verbose) + std::cerr << " - phi operand " << RAV(ArgVal) << " came from BB " << RAV(PredBB) << "\n"; - } // if( IsPhi ) + } // if( IsPhi ) else { // It is not a Phi use: add to regular use set and remove later defs. addUse(Op); @@ -102,16 +102,16 @@ const Value *Op = MI->getImplicitRef(i); if (Op->getType() == Type::LabelTy) // don't process labels - continue; + continue; if (MI->getImplicitOp(i).isUse()) - addUse(Op); + addUse(Op); } } // for all machine instructions } - + //----------------------------------------------------------------------------- // To add an operand which is a def //----------------------------------------------------------------------------- @@ -208,7 +208,7 @@ // if the predec POID is lower than mine if (PredLVBB->getPOId() <= POID) - needAnotherIt = true; + needAnotherIt = true; } } // for From jeffc at jolt-lang.org Wed Jul 27 00:54:01 2005 From: jeffc at jolt-lang.org (Jeff Cohen) Date: Wed, 27 Jul 2005 00:54:01 -0500 Subject: [llvm-commits] CVS: llvm/include/llvm/Support/Annotation.h CommandLine.h DataTypes.h.in MutexGuard.h Message-ID: <200507270554.AAA12880@zion.cs.uiuc.edu> Changes in directory llvm/include/llvm/Support: Annotation.h updated: 1.20 -> 1.21 CommandLine.h updated: 1.45 -> 1.46 DataTypes.h.in updated: 1.19 -> 1.20 MutexGuard.h updated: 1.5 -> 1.6 --- Log message: Eliminate tabs and trailing spaces. --- Diffs of the changes: (+8 -8) Annotation.h | 2 +- CommandLine.h | 2 +- DataTypes.h.in | 4 ++-- MutexGuard.h | 8 ++++---- 4 files changed, 8 insertions(+), 8 deletions(-) Index: llvm/include/llvm/Support/Annotation.h diff -u llvm/include/llvm/Support/Annotation.h:1.20 llvm/include/llvm/Support/Annotation.h:1.21 --- llvm/include/llvm/Support/Annotation.h:1.20 Wed Jun 15 13:40:45 2005 +++ llvm/include/llvm/Support/Annotation.h Wed Jul 27 00:53:43 2005 @@ -81,7 +81,7 @@ //===----------------------------------------------------------------------===// // // Annotable - This class is used as a base class for all objects that would -// like to have annotation capability. +// like to have annotation capability. // // Annotable objects keep their annotation list sorted as annotations are // inserted and deleted. This is used to ensure that annotations with identical Index: llvm/include/llvm/Support/CommandLine.h diff -u llvm/include/llvm/Support/CommandLine.h:1.45 llvm/include/llvm/Support/CommandLine.h:1.46 --- llvm/include/llvm/Support/CommandLine.h:1.45 Sat Jun 18 11:53:27 2005 +++ llvm/include/llvm/Support/CommandLine.h Wed Jul 27 00:53:43 2005 @@ -734,7 +734,7 @@ virtual bool handleOccurrence(unsigned pos, const char *ArgName, const std::string &Arg) { - typename ParserClass::parser_data_type Val = + typename ParserClass::parser_data_type Val = typename ParserClass::parser_data_type(); if (Parser.parse(*this, ArgName, Arg, Val)) return true; // Parse error! Index: llvm/include/llvm/Support/DataTypes.h.in diff -u llvm/include/llvm/Support/DataTypes.h.in:1.19 llvm/include/llvm/Support/DataTypes.h.in:1.20 --- llvm/include/llvm/Support/DataTypes.h.in:1.19 Tue Jan 18 23:08:31 2005 +++ llvm/include/llvm/Support/DataTypes.h.in Wed Jul 27 00:53:43 2005 @@ -1,10 +1,10 @@ //===-- include/Support/DataTypes.h - Define fixed size types ---*- C++ -*-===// -// +// // The LLVM Compiler Infrastructure // // This file was developed by the LLVM research group and is distributed under // the University of Illinois Open Source License. See LICENSE.TXT for details. -// +// //===----------------------------------------------------------------------===// // // This file contains definitions to figure out the size of _HOST_ data types. Index: llvm/include/llvm/Support/MutexGuard.h diff -u llvm/include/llvm/Support/MutexGuard.h:1.5 llvm/include/llvm/Support/MutexGuard.h:1.6 --- llvm/include/llvm/Support/MutexGuard.h:1.5 Tue Jul 12 10:51:55 2005 +++ llvm/include/llvm/Support/MutexGuard.h Wed Jul 27 00:53:43 2005 @@ -1,10 +1,10 @@ //===-- Support/MutexGuard.h - Acquire/Release Mutex In Scope ---*- C++ -*-===// -// +// // The LLVM Compiler Infrastructure // // This file was developed by the LLVM research group and is distributed under // the University of Illinois Open Source License. See LICENSE.TXT for details. -// +// //===----------------------------------------------------------------------===// // // This file defines a guard for a block of code that ensures a Mutex is locked @@ -18,7 +18,7 @@ #include namespace llvm { - /// Instances of this class acquire a given Mutex Lock when constructed and + /// Instances of this class acquire a given Mutex Lock when constructed and /// hold that lock until destruction. The intention is to instantiate one of /// these on the stack at the top of some scope to be assured that C++ /// destruction of the object will always release the Mutex and thus avoid @@ -34,7 +34,7 @@ /// holds - Returns true if this locker instance holds the specified lock. /// This is mostly used in assertions to validate that the correct mutex /// is held. - bool holds(const sys::Mutex& lock) const { return &M == &lock; } + bool holds(const sys::Mutex& lock) const { return &M == &lock; } }; } From jeffc at jolt-lang.org Wed Jul 27 00:54:01 2005 From: jeffc at jolt-lang.org (Jeff Cohen) Date: Wed, 27 Jul 2005 00:54:01 -0500 Subject: [llvm-commits] CVS: llvm/lib/System/ltdl.h Message-ID: <200507270554.AAA12909@zion.cs.uiuc.edu> Changes in directory llvm/lib/System: ltdl.h updated: 1.1 -> 1.2 --- Log message: Eliminate tabs and trailing spaces. --- Diffs of the changes: (+134 -134) ltdl.h | 268 ++++++++++++++++++++++++++++++++--------------------------------- 1 files changed, 134 insertions(+), 134 deletions(-) Index: llvm/lib/System/ltdl.h diff -u llvm/lib/System/ltdl.h:1.1 llvm/lib/System/ltdl.h:1.2 --- llvm/lib/System/ltdl.h:1.1 Mon Nov 29 06:02:48 2004 +++ llvm/lib/System/ltdl.h Wed Jul 27 00:53:43 2005 @@ -28,24 +28,24 @@ #ifndef LTDL_H #define LTDL_H 1 -#include /* for size_t declaration */ +#include /* for size_t declaration */ /* --- MACROS FOR PORTABILITY --- */ /* Saves on those hard to debug '\0' typos.... */ -#define LT_EOS_CHAR '\0' +#define LT_EOS_CHAR '\0' /* LTDL_BEGIN_C_DECLS should be used at the beginning of your declarations, so that C++ compilers don't mangle their names. Use LTDL_END_C_DECLS at the end of C declarations. */ #ifdef __cplusplus -# define LT_BEGIN_C_DECLS extern "C" { -# define LT_END_C_DECLS } +# define LT_BEGIN_C_DECLS extern "C" { +# define LT_END_C_DECLS } #else -# define LT_BEGIN_C_DECLS /* empty */ -# define LT_END_C_DECLS /* empty */ +# define LT_BEGIN_C_DECLS /* empty */ +# define LT_END_C_DECLS /* empty */ #endif LT_BEGIN_C_DECLS @@ -55,11 +55,11 @@ that don't understand ANSI C prototypes still work, and ANSI C compilers can issue warnings about type mismatches. */ #if defined (__STDC__) || defined (_AIX) || (defined (__mips) && defined (_SYSTYPE_SVR4)) || defined(WIN32) || defined(__cplusplus) -# define LT_PARAMS(protos) protos -# define lt_ptr void* +# define LT_PARAMS(protos) protos +# define lt_ptr void* #else -# define LT_PARAMS(protos) () -# define lt_ptr char* +# define LT_PARAMS(protos) () +# define lt_ptr char* #endif /* LT_STMT_START/END are used to create macros which expand to a @@ -80,13 +80,13 @@ /* LT_CONC creates a new concatenated symbol for the compiler in a portable way. */ #if defined(__STDC__) || defined(__cplusplus) || defined(_MSC_VER) -# define LT_CONC(s,t) s##t +# define LT_CONC(s,t) s##t #else -# define LT_CONC(s,t) s/**/t +# define LT_CONC(s,t) s/**/t #endif /* LT_STRLEN can be used safely on NULL pointers. */ -#define LT_STRLEN(s) (((s) && (s)[0]) ? strlen (s) : 0) +#define LT_STRLEN(s) (((s) && (s)[0]) ? strlen (s) : 0) @@ -116,27 +116,27 @@ # ifndef __CYGWIN__ /* LT_DIRSEP_CHAR is accepted *in addition* to '/' as a directory separator when it is set. */ -# define LT_DIRSEP_CHAR '\\' -# define LT_PATHSEP_CHAR ';' +# define LT_DIRSEP_CHAR '\\' +# define LT_PATHSEP_CHAR ';' # endif #endif #ifndef LT_PATHSEP_CHAR -# define LT_PATHSEP_CHAR ':' +# define LT_PATHSEP_CHAR ':' #endif /* DLL building support on win32 hosts; mostly to workaround their ridiculous implementation of data symbol exporting. */ #ifndef LT_SCOPE # ifdef __WINDOWS__ -# ifdef DLL_EXPORT /* defined by libtool (if required) */ -# define LT_SCOPE __declspec(dllexport) +# ifdef DLL_EXPORT /* defined by libtool (if required) */ +# define LT_SCOPE __declspec(dllexport) # endif -# ifdef LIBLTDL_DLL_IMPORT /* define if linking with this dll */ -# define LT_SCOPE extern __declspec(dllimport) +# ifdef LIBLTDL_DLL_IMPORT /* define if linking with this dll */ +# define LT_SCOPE extern __declspec(dllimport) # endif # endif -# ifndef LT_SCOPE /* static linking or !__WINDOWS__ */ -# define LT_SCOPE extern +# ifndef LT_SCOPE /* static linking or !__WINDOWS__ */ +# define LT_SCOPE extern # endif #endif @@ -150,34 +150,34 @@ /* --- DYNAMIC MODULE LOADING API --- */ -typedef struct lt_dlhandle_struct *lt_dlhandle; /* A loaded module. */ +typedef struct lt_dlhandle_struct *lt_dlhandle; /* A loaded module. */ /* Initialisation and finalisation functions for libltdl. */ -LT_SCOPE int lt_dlinit LT_PARAMS((void)); -LT_SCOPE int lt_dlexit LT_PARAMS((void)); +LT_SCOPE int lt_dlinit LT_PARAMS((void)); +LT_SCOPE int lt_dlexit LT_PARAMS((void)); /* Module search path manipulation. */ -LT_SCOPE int lt_dladdsearchdir LT_PARAMS((const char *search_dir)); -LT_SCOPE int lt_dlinsertsearchdir LT_PARAMS((const char *before, - const char *search_dir)); -LT_SCOPE int lt_dlsetsearchpath LT_PARAMS((const char *search_path)); -LT_SCOPE const char *lt_dlgetsearchpath LT_PARAMS((void)); -LT_SCOPE int lt_dlforeachfile LT_PARAMS(( - const char *search_path, - int (*func) (const char *filename, lt_ptr data), - lt_ptr data)); +LT_SCOPE int lt_dladdsearchdir LT_PARAMS((const char *search_dir)); +LT_SCOPE int lt_dlinsertsearchdir LT_PARAMS((const char *before, + const char *search_dir)); +LT_SCOPE int lt_dlsetsearchpath LT_PARAMS((const char *search_path)); +LT_SCOPE const char *lt_dlgetsearchpath LT_PARAMS((void)); +LT_SCOPE int lt_dlforeachfile LT_PARAMS(( + const char *search_path, + int (*func) (const char *filename, lt_ptr data), + lt_ptr data)); /* Portable libltdl versions of the system dlopen() API. */ -LT_SCOPE lt_dlhandle lt_dlopen LT_PARAMS((const char *filename)); -LT_SCOPE lt_dlhandle lt_dlopenext LT_PARAMS((const char *filename)); -LT_SCOPE lt_ptr lt_dlsym LT_PARAMS((lt_dlhandle handle, - const char *name)); -LT_SCOPE const char *lt_dlerror LT_PARAMS((void)); -LT_SCOPE int lt_dlclose LT_PARAMS((lt_dlhandle handle)); +LT_SCOPE lt_dlhandle lt_dlopen LT_PARAMS((const char *filename)); +LT_SCOPE lt_dlhandle lt_dlopenext LT_PARAMS((const char *filename)); +LT_SCOPE lt_ptr lt_dlsym LT_PARAMS((lt_dlhandle handle, + const char *name)); +LT_SCOPE const char *lt_dlerror LT_PARAMS((void)); +LT_SCOPE int lt_dlclose LT_PARAMS((lt_dlhandle handle)); /* Module residency management. */ -LT_SCOPE int lt_dlmakeresident LT_PARAMS((lt_dlhandle handle)); -LT_SCOPE int lt_dlisresident LT_PARAMS((lt_dlhandle handle)); +LT_SCOPE int lt_dlmakeresident LT_PARAMS((lt_dlhandle handle)); +LT_SCOPE int lt_dlisresident LT_PARAMS((lt_dlhandle handle)); @@ -185,15 +185,15 @@ /* --- MUTEX LOCKING --- */ -typedef void lt_dlmutex_lock LT_PARAMS((void)); -typedef void lt_dlmutex_unlock LT_PARAMS((void)); -typedef void lt_dlmutex_seterror LT_PARAMS((const char *errmsg)); -typedef const char *lt_dlmutex_geterror LT_PARAMS((void)); - -LT_SCOPE int lt_dlmutex_register LT_PARAMS((lt_dlmutex_lock *lock, - lt_dlmutex_unlock *unlock, - lt_dlmutex_seterror *seterror, - lt_dlmutex_geterror *geterror)); +typedef void lt_dlmutex_lock LT_PARAMS((void)); +typedef void lt_dlmutex_unlock LT_PARAMS((void)); +typedef void lt_dlmutex_seterror LT_PARAMS((const char *errmsg)); +typedef const char *lt_dlmutex_geterror LT_PARAMS((void)); + +LT_SCOPE int lt_dlmutex_register LT_PARAMS((lt_dlmutex_lock *lock, + lt_dlmutex_unlock *unlock, + lt_dlmutex_seterror *seterror, + lt_dlmutex_geterror *geterror)); @@ -206,9 +206,9 @@ libltdl relies on a featureful realloc, but if you are sure yours has the right semantics then you can assign it directly. Generally, it is safe to assign just a malloc() and a free() function. */ -LT_SCOPE lt_ptr (*lt_dlmalloc) LT_PARAMS((size_t size)); -LT_SCOPE lt_ptr (*lt_dlrealloc) LT_PARAMS((lt_ptr ptr, size_t size)); -LT_SCOPE void (*lt_dlfree) LT_PARAMS((lt_ptr ptr)); +LT_SCOPE lt_ptr (*lt_dlmalloc) LT_PARAMS((size_t size)); +LT_SCOPE lt_ptr (*lt_dlrealloc) LT_PARAMS((lt_ptr ptr, size_t size)); +LT_SCOPE void (*lt_dlfree) LT_PARAMS((lt_ptr ptr)); @@ -223,14 +223,14 @@ lt_ptr address; } lt_dlsymlist; -LT_SCOPE int lt_dlpreload LT_PARAMS((const lt_dlsymlist *preloaded)); -LT_SCOPE int lt_dlpreload_default - LT_PARAMS((const lt_dlsymlist *preloaded)); - -#define LTDL_SET_PRELOADED_SYMBOLS() LT_STMT_START{ \ - extern const lt_dlsymlist lt_preloaded_symbols[]; \ - lt_dlpreload_default(lt_preloaded_symbols); \ - }LT_STMT_END +LT_SCOPE int lt_dlpreload LT_PARAMS((const lt_dlsymlist *preloaded)); +LT_SCOPE int lt_dlpreload_default + LT_PARAMS((const lt_dlsymlist *preloaded)); + +#define LTDL_SET_PRELOADED_SYMBOLS() LT_STMT_START{ \ + extern const lt_dlsymlist lt_preloaded_symbols[]; \ + lt_dlpreload_default(lt_preloaded_symbols); \ + }LT_STMT_END @@ -239,67 +239,67 @@ /* Read only information pertaining to a loaded module. */ -typedef struct { - char *filename; /* file name */ - char *name; /* module name */ - int ref_count; /* number of times lt_dlopened minus - number of times lt_dlclosed. */ +typedef struct { + char *filename; /* file name */ + char *name; /* module name */ + int ref_count; /* number of times lt_dlopened minus + number of times lt_dlclosed. */ } lt_dlinfo; -LT_SCOPE const lt_dlinfo *lt_dlgetinfo LT_PARAMS((lt_dlhandle handle)); -LT_SCOPE lt_dlhandle lt_dlhandle_next LT_PARAMS((lt_dlhandle place)); -LT_SCOPE int lt_dlforeach LT_PARAMS(( - int (*func) (lt_dlhandle handle, lt_ptr data), - lt_ptr data)); +LT_SCOPE const lt_dlinfo *lt_dlgetinfo LT_PARAMS((lt_dlhandle handle)); +LT_SCOPE lt_dlhandle lt_dlhandle_next LT_PARAMS((lt_dlhandle place)); +LT_SCOPE int lt_dlforeach LT_PARAMS(( + int (*func) (lt_dlhandle handle, lt_ptr data), + lt_ptr data)); /* Associating user data with loaded modules. */ typedef unsigned lt_dlcaller_id; -LT_SCOPE lt_dlcaller_id lt_dlcaller_register LT_PARAMS((void)); -LT_SCOPE lt_ptr lt_dlcaller_set_data LT_PARAMS((lt_dlcaller_id key, - lt_dlhandle handle, - lt_ptr data)); -LT_SCOPE lt_ptr lt_dlcaller_get_data LT_PARAMS((lt_dlcaller_id key, - lt_dlhandle handle)); +LT_SCOPE lt_dlcaller_id lt_dlcaller_register LT_PARAMS((void)); +LT_SCOPE lt_ptr lt_dlcaller_set_data LT_PARAMS((lt_dlcaller_id key, + lt_dlhandle handle, + lt_ptr data)); +LT_SCOPE lt_ptr lt_dlcaller_get_data LT_PARAMS((lt_dlcaller_id key, + lt_dlhandle handle)); /* --- USER MODULE LOADER API --- */ -typedef struct lt_dlloader lt_dlloader; -typedef lt_ptr lt_user_data; -typedef lt_ptr lt_module; +typedef struct lt_dlloader lt_dlloader; +typedef lt_ptr lt_user_data; +typedef lt_ptr lt_module; /* Function pointer types for creating user defined module loaders. */ -typedef lt_module lt_module_open LT_PARAMS((lt_user_data loader_data, - const char *filename)); -typedef int lt_module_close LT_PARAMS((lt_user_data loader_data, - lt_module handle)); -typedef lt_ptr lt_find_sym LT_PARAMS((lt_user_data loader_data, - lt_module handle, - const char *symbol)); -typedef int lt_dlloader_exit LT_PARAMS((lt_user_data loader_data)); +typedef lt_module lt_module_open LT_PARAMS((lt_user_data loader_data, + const char *filename)); +typedef int lt_module_close LT_PARAMS((lt_user_data loader_data, + lt_module handle)); +typedef lt_ptr lt_find_sym LT_PARAMS((lt_user_data loader_data, + lt_module handle, + const char *symbol)); +typedef int lt_dlloader_exit LT_PARAMS((lt_user_data loader_data)); struct lt_user_dlloader { - const char *sym_prefix; + const char *sym_prefix; lt_module_open *module_open; lt_module_close *module_close; - lt_find_sym *find_sym; + lt_find_sym *find_sym; lt_dlloader_exit *dlloader_exit; - lt_user_data dlloader_data; + lt_user_data dlloader_data; }; -LT_SCOPE lt_dlloader *lt_dlloader_next LT_PARAMS((lt_dlloader *place)); -LT_SCOPE lt_dlloader *lt_dlloader_find LT_PARAMS(( - const char *loader_name)); -LT_SCOPE const char *lt_dlloader_name LT_PARAMS((lt_dlloader *place)); -LT_SCOPE lt_user_data *lt_dlloader_data LT_PARAMS((lt_dlloader *place)); -LT_SCOPE int lt_dlloader_add LT_PARAMS((lt_dlloader *place, - const struct lt_user_dlloader *dlloader, - const char *loader_name)); -LT_SCOPE int lt_dlloader_remove LT_PARAMS(( - const char *loader_name)); +LT_SCOPE lt_dlloader *lt_dlloader_next LT_PARAMS((lt_dlloader *place)); +LT_SCOPE lt_dlloader *lt_dlloader_find LT_PARAMS(( + const char *loader_name)); +LT_SCOPE const char *lt_dlloader_name LT_PARAMS((lt_dlloader *place)); +LT_SCOPE lt_user_data *lt_dlloader_data LT_PARAMS((lt_dlloader *place)); +LT_SCOPE int lt_dlloader_add LT_PARAMS((lt_dlloader *place, + const struct lt_user_dlloader *dlloader, + const char *loader_name)); +LT_SCOPE int lt_dlloader_remove LT_PARAMS(( + const char *loader_name)); @@ -310,39 +310,39 @@ this way allows us to expand the macro in different contexts with confidence that the enumeration of symbolic names will map correctly onto the table of error strings. */ -#define lt_dlerror_table \ - LT_ERROR(UNKNOWN, "unknown error") \ - LT_ERROR(DLOPEN_NOT_SUPPORTED, "dlopen support not available") \ - LT_ERROR(INVALID_LOADER, "invalid loader") \ - LT_ERROR(INIT_LOADER, "loader initialization failed") \ - LT_ERROR(REMOVE_LOADER, "loader removal failed") \ - LT_ERROR(FILE_NOT_FOUND, "file not found") \ - LT_ERROR(DEPLIB_NOT_FOUND, "dependency library not found") \ - LT_ERROR(NO_SYMBOLS, "no symbols defined") \ - LT_ERROR(CANNOT_OPEN, "can't open the module") \ - LT_ERROR(CANNOT_CLOSE, "can't close the module") \ - LT_ERROR(SYMBOL_NOT_FOUND, "symbol not found") \ - LT_ERROR(NO_MEMORY, "not enough memory") \ - LT_ERROR(INVALID_HANDLE, "invalid module handle") \ - LT_ERROR(BUFFER_OVERFLOW, "internal buffer overflow") \ - LT_ERROR(INVALID_ERRORCODE, "invalid errorcode") \ - LT_ERROR(SHUTDOWN, "library already shutdown") \ - LT_ERROR(CLOSE_RESIDENT_MODULE, "can't close resident module") \ +#define lt_dlerror_table \ + LT_ERROR(UNKNOWN, "unknown error") \ + LT_ERROR(DLOPEN_NOT_SUPPORTED, "dlopen support not available") \ + LT_ERROR(INVALID_LOADER, "invalid loader") \ + LT_ERROR(INIT_LOADER, "loader initialization failed") \ + LT_ERROR(REMOVE_LOADER, "loader removal failed") \ + LT_ERROR(FILE_NOT_FOUND, "file not found") \ + LT_ERROR(DEPLIB_NOT_FOUND, "dependency library not found") \ + LT_ERROR(NO_SYMBOLS, "no symbols defined") \ + LT_ERROR(CANNOT_OPEN, "can't open the module") \ + LT_ERROR(CANNOT_CLOSE, "can't close the module") \ + LT_ERROR(SYMBOL_NOT_FOUND, "symbol not found") \ + LT_ERROR(NO_MEMORY, "not enough memory") \ + LT_ERROR(INVALID_HANDLE, "invalid module handle") \ + LT_ERROR(BUFFER_OVERFLOW, "internal buffer overflow") \ + LT_ERROR(INVALID_ERRORCODE, "invalid errorcode") \ + LT_ERROR(SHUTDOWN, "library already shutdown") \ + LT_ERROR(CLOSE_RESIDENT_MODULE, "can't close resident module") \ LT_ERROR(INVALID_MUTEX_ARGS, "invalid mutex handler registration") \ - LT_ERROR(INVALID_POSITION, "invalid search path insert position") + LT_ERROR(INVALID_POSITION, "invalid search path insert position") /* Enumerate the symbolic error names. */ enum { -#define LT_ERROR(name, diagnostic) LT_CONC(LT_ERROR_, name), - lt_dlerror_table +#define LT_ERROR(name, diagnostic) LT_CONC(LT_ERROR_, name), + lt_dlerror_table #undef LT_ERROR - LT_ERROR_MAX + LT_ERROR_MAX }; /* These functions are only useful from inside custom module loaders. */ -LT_SCOPE int lt_dladderror LT_PARAMS((const char *diagnostic)); -LT_SCOPE int lt_dlseterror LT_PARAMS((int errorcode)); +LT_SCOPE int lt_dladderror LT_PARAMS((const char *diagnostic)); +LT_SCOPE int lt_dlseterror LT_PARAMS((int errorcode)); @@ -351,14 +351,14 @@ #ifdef LT_NON_POSIX_NAMESPACE -# define lt_ptr_t lt_ptr -# define lt_module_t lt_module -# define lt_module_open_t lt_module_open -# define lt_module_close_t lt_module_close -# define lt_find_sym_t lt_find_sym -# define lt_dlloader_exit_t lt_dlloader_exit -# define lt_dlloader_t lt_dlloader -# define lt_dlloader_data_t lt_user_data +# define lt_ptr_t lt_ptr +# define lt_module_t lt_module +# define lt_module_open_t lt_module_open +# define lt_module_close_t lt_module_close +# define lt_find_sym_t lt_find_sym +# define lt_dlloader_exit_t lt_dlloader_exit +# define lt_dlloader_t lt_dlloader +# define lt_dlloader_data_t lt_user_data #endif LT_END_C_DECLS From jeffc at jolt-lang.org Wed Jul 27 00:54:01 2005 From: jeffc at jolt-lang.org (Jeff Cohen) Date: Wed, 27 Jul 2005 00:54:01 -0500 Subject: [llvm-commits] CVS: llvm/include/llvm/Target/TargetLowering.h TargetMachine.h Message-ID: <200507270554.AAA12922@zion.cs.uiuc.edu> Changes in directory llvm/include/llvm/Target: TargetLowering.h updated: 1.17 -> 1.18 TargetMachine.h updated: 1.55 -> 1.56 --- Log message: Eliminate tabs and trailing spaces. --- Diffs of the changes: (+7 -7) TargetLowering.h | 12 ++++++------ TargetMachine.h | 2 +- 2 files changed, 7 insertions(+), 7 deletions(-) Index: llvm/include/llvm/Target/TargetLowering.h diff -u llvm/include/llvm/Target/TargetLowering.h:1.17 llvm/include/llvm/Target/TargetLowering.h:1.18 --- llvm/include/llvm/Target/TargetLowering.h:1.17 Mon Jul 18 23:52:44 2005 +++ llvm/include/llvm/Target/TargetLowering.h Wed Jul 27 00:53:43 2005 @@ -208,8 +208,8 @@ /// This function returns true if the target allows unaligned stores. This is /// used in situations where an array copy/move/set is converted to a sequence - /// of store operations. It ensures that such replacements don't generate - /// code that causes an alignment error (trap) on the target machine. + /// of store operations. It ensures that such replacements don't generate + /// code that causes an alignment error (trap) on the target machine. /// @brief Determine if the target supports unaligned stores. bool allowsUnalignedStores() const { return allowUnalignedStores; } @@ -399,7 +399,7 @@ /// should assume that the memset will be done using as many of the largest /// store operations first, followed by smaller ones, if necessary, per /// alignment restrictions. For example, storing 9 bytes on a 32-bit machine - /// with 16-bit alignment would result in four 2-byte stores and one 1-byte + /// with 16-bit alignment would result in four 2-byte stores and one 1-byte /// store. This only applies to setting a constant array of a constant size. /// @brief Specify maximum number of store instructions per memset call. unsigned maxStoresPerMemSet; @@ -421,14 +421,14 @@ /// must set this value based on the cost threshold for that target. Targets /// should assume that the memmove will be done using as many of the largest /// store operations first, followed by smaller ones, if necessary, per - /// alignment restrictions. For example, moving 9 bytes on a 32-bit machine - /// with 8-bit alignment would result in nine 1-byte stores. This only + /// alignment restrictions. For example, moving 9 bytes on a 32-bit machine + /// with 8-bit alignment would result in nine 1-byte stores. This only /// applies to copying a constant array of constant size. /// @brief Specify maximum bytes of store instructions per memmove call. unsigned maxStoresPerMemMove; /// This field specifies whether the target machine permits unaligned stores. - /// This is used to determine the size of store operations for copying + /// This is used to determine the size of store operations for copying /// small arrays and other similar tasks. /// @brief Indicate whether the target machine permits unaligned stores. bool allowUnalignedStores; Index: llvm/include/llvm/Target/TargetMachine.h diff -u llvm/include/llvm/Target/TargetMachine.h:1.55 llvm/include/llvm/Target/TargetMachine.h:1.56 --- llvm/include/llvm/Target/TargetMachine.h:1.55 Mon Jul 11 22:04:49 2005 +++ llvm/include/llvm/Target/TargetMachine.h Wed Jul 27 00:53:43 2005 @@ -102,7 +102,7 @@ virtual const TargetFrameInfo *getFrameInfo() const { return 0; } const TargetData &getTargetData() const { return DataLayout; } - /// getSubtarget - This method returns a pointer to the specified type of + /// getSubtarget - This method returns a pointer to the specified type of /// TargetSubtarget. In debug builds, it verifies that the object being /// returned is of the correct type. template STC *getSubtarget() const { From jeffc at jolt-lang.org Wed Jul 27 00:54:01 2005 From: jeffc at jolt-lang.org (Jeff Cohen) Date: Wed, 27 Jul 2005 00:54:01 -0500 Subject: [llvm-commits] CVS: llvm/lib/Target/SparcV9/RegAlloc/InterferenceGraph.cpp LiveRange.h LiveRangeInfo.cpp LiveRangeInfo.h PhyRegAlloc.cpp PhyRegAlloc.h RegClass.cpp RegClass.h Message-ID: <200507270554.AAA12869@zion.cs.uiuc.edu> Changes in directory llvm/lib/Target/SparcV9/RegAlloc: InterferenceGraph.cpp updated: 1.24 -> 1.25 LiveRange.h updated: 1.31 -> 1.32 LiveRangeInfo.cpp updated: 1.60 -> 1.61 LiveRangeInfo.h updated: 1.28 -> 1.29 PhyRegAlloc.cpp updated: 1.169 -> 1.170 PhyRegAlloc.h updated: 1.71 -> 1.72 RegClass.cpp updated: 1.33 -> 1.34 RegClass.h updated: 1.25 -> 1.26 --- Log message: Eliminate tabs and trailing spaces. --- Diffs of the changes: (+131 -131) InterferenceGraph.cpp | 8 +-- LiveRange.h | 2 LiveRangeInfo.cpp | 96 ++++++++++++++++++++-------------------- LiveRangeInfo.h | 4 - PhyRegAlloc.cpp | 118 +++++++++++++++++++++++++------------------------- PhyRegAlloc.h | 8 +-- RegClass.cpp | 16 +++--- RegClass.h | 10 ++-- 8 files changed, 131 insertions(+), 131 deletions(-) Index: llvm/lib/Target/SparcV9/RegAlloc/InterferenceGraph.cpp diff -u llvm/lib/Target/SparcV9/RegAlloc/InterferenceGraph.cpp:1.24 llvm/lib/Target/SparcV9/RegAlloc/InterferenceGraph.cpp:1.25 --- llvm/lib/Target/SparcV9/RegAlloc/InterferenceGraph.cpp:1.24 Sun Jun 12 18:52:58 2005 +++ llvm/lib/Target/SparcV9/RegAlloc/InterferenceGraph.cpp Wed Jul 27 00:53:44 2005 @@ -68,7 +68,7 @@ // init IG matrix for(unsigned int i=0; i < Size; i++) for(unsigned int j=0; j < Size; j++) - IG[i][j] = 0; + IG[i][j] = 0; } //----------------------------------------------------------------------------- @@ -88,7 +88,7 @@ // that there is some wrong logic in some other method. //----------------------------------------------------------------------------- void InterferenceGraph::setInterference(const V9LiveRange *const LR1, - const V9LiveRange *const LR2 ) { + const V9LiveRange *const LR2 ) { assert(LR1 != LR2); IGNode *IGNode1 = LR1->getUserIGNode(); @@ -147,7 +147,7 @@ //---------------------------------------------------------------------------- void InterferenceGraph::mergeIGNodesOfLRs(const V9LiveRange *LR1, - V9LiveRange *LR2) { + V9LiveRange *LR2) { assert( LR1 != LR2); // cannot merge the same live range @@ -226,7 +226,7 @@ std::cerr << " [" << i << "] "; for( unsigned int j=0; j < Size; j++) - if(IG[i][j]) + if(IG[i][j]) std::cerr << "(" << i << "," << j << ") "; std::cerr << "\n"; } Index: llvm/lib/Target/SparcV9/RegAlloc/LiveRange.h diff -u llvm/lib/Target/SparcV9/RegAlloc/LiveRange.h:1.31 llvm/lib/Target/SparcV9/RegAlloc/LiveRange.h:1.32 --- llvm/lib/Target/SparcV9/RegAlloc/LiveRange.h:1.31 Sun Jun 12 18:52:58 2005 +++ llvm/lib/Target/SparcV9/RegAlloc/LiveRange.h Wed Jul 27 00:53:44 2005 @@ -184,7 +184,7 @@ } }; -static inline std::ostream &operator << (std::ostream &os, +static inline std::ostream &operator << (std::ostream &os, const V9LiveRange &lr) { os << "LiveRange@" << (void *)(&lr); return os; Index: llvm/lib/Target/SparcV9/RegAlloc/LiveRangeInfo.cpp diff -u llvm/lib/Target/SparcV9/RegAlloc/LiveRangeInfo.cpp:1.60 llvm/lib/Target/SparcV9/RegAlloc/LiveRangeInfo.cpp:1.61 --- llvm/lib/Target/SparcV9/RegAlloc/LiveRangeInfo.cpp:1.60 Sun Jun 12 18:52:58 2005 +++ llvm/lib/Target/SparcV9/RegAlloc/LiveRangeInfo.cpp Wed Jul 27 00:53:44 2005 @@ -30,7 +30,7 @@ unsigned V9LiveRange::getRegClassID() const { return getRegClass()->getID(); } LiveRangeInfo::LiveRangeInfo(const Function *F, const TargetMachine &tm, - std::vector &RCL) + std::vector &RCL) : Meth(F), TM(tm), RegClassList(RCL), MRI(*tm.getRegInfo()) { } @@ -177,15 +177,15 @@ // CallRetInstrList for processing its args, ret value, and ret addr. // if(TM.getInstrInfo()->isReturn(MInst->getOpcode()) || - TM.getInstrInfo()->isCall(MInst->getOpcode())) - CallRetInstrList.push_back(MInst); + TM.getInstrInfo()->isCall(MInst->getOpcode())) + CallRetInstrList.push_back(MInst); // iterate over explicit MI operands and create a new LR // for each operand that is defined by the instruction for (MachineInstr::val_op_iterator OpI = MInst->begin(), OpE = MInst->end(); OpI != OpE; ++OpI) - if (OpI.isDef()) { - const Value *Def = *OpI; + if (OpI.isDef()) { + const Value *Def = *OpI; bool isCC = (OpI.getMachineOperand().getType() == MachineOperand::MO_CCRegister); V9LiveRange* LR = createOrAddToLiveRange(Def, isCC); @@ -197,13 +197,13 @@ LR->setColor(MRI.getClassRegNum(OpI.getMachineOperand().getReg(), getClassId)); } - } + } // iterate over implicit MI operands and create a new LR // for each operand that is defined by the instruction for (unsigned i = 0; i < MInst->getNumImplicitRefs(); ++i) - if (MInst->getImplicitOp(i).isDef()) { - const Value *Def = MInst->getImplicitRef(i); + if (MInst->getImplicitOp(i).isDef()) { + const Value *Def = MInst->getImplicitRef(i); V9LiveRange* LR = createOrAddToLiveRange(Def, /*isCC*/ false); // If the implicit operand has a pre-assigned register, @@ -214,7 +214,7 @@ MInst->getImplicitOp(i).getReg(), getClassId)); } - } + } } // for all machine instructions in the BB } // for all BBs in function @@ -265,10 +265,10 @@ for each definition (def) in inst for each operand (op) of inst that is a use if the def and op are of the same register type - if the def and op do not interfere //i.e., not simultaneously live - if (degree(LR of def) + degree(LR of op)) <= # avail regs - if both LRs do not have suggested colors - merge2IGNodes(def, op) // i.e., merge 2 LRs + if the def and op do not interfere //i.e., not simultaneously live + if (degree(LR of def) + degree(LR of op)) <= # avail regs + if both LRs do not have suggested colors + merge2IGNodes(def, op) // i.e., merge 2 LRs */ //--------------------------------------------------------------------------- @@ -332,40 +332,40 @@ const MachineInstr *MI = MII; if( DEBUG_RA >= RA_DEBUG_LiveRanges) { - std::cerr << " *Iterating over machine instr "; - MI->dump(); - std::cerr << "\n"; + std::cerr << " *Iterating over machine instr "; + MI->dump(); + std::cerr << "\n"; } // iterate over MI operands to find defs for(MachineInstr::const_val_op_iterator DefI = MI->begin(), DefE = MI->end(); DefI != DefE; ++DefI) { - if (DefI.isDef()) { // this operand is modified - V9LiveRange *LROfDef = getLiveRangeForValue( *DefI ); - RegClass *RCOfDef = LROfDef->getRegClass(); + if (DefI.isDef()) { // this operand is modified + V9LiveRange *LROfDef = getLiveRangeForValue( *DefI ); + RegClass *RCOfDef = LROfDef->getRegClass(); - MachineInstr::const_val_op_iterator UseI = MI->begin(), + MachineInstr::const_val_op_iterator UseI = MI->begin(), UseE = MI->end(); - for( ; UseI != UseE; ++UseI) { // for all uses - V9LiveRange *LROfUse = getLiveRangeForValue( *UseI ); - if (!LROfUse) { // if LR of use is not found - //don't warn about labels - if (!isa(*UseI) && DEBUG_RA >= RA_DEBUG_LiveRanges) - std::cerr << " !! Warning: No LR for use " << RAV(*UseI)<< "\n"; - continue; // ignore and continue - } + for( ; UseI != UseE; ++UseI) { // for all uses + V9LiveRange *LROfUse = getLiveRangeForValue( *UseI ); + if (!LROfUse) { // if LR of use is not found + //don't warn about labels + if (!isa(*UseI) && DEBUG_RA >= RA_DEBUG_LiveRanges) + std::cerr << " !! Warning: No LR for use " << RAV(*UseI)<< "\n"; + continue; // ignore and continue + } - if (LROfUse == LROfDef) // nothing to merge if they are same - continue; + if (LROfUse == LROfDef) // nothing to merge if they are same + continue; - if (MRI.getRegTypeForLR(LROfDef) == + if (MRI.getRegTypeForLR(LROfDef) == MRI.getRegTypeForLR(LROfUse)) { - // If the two RegTypes are the same - if (!RCOfDef->getInterference(LROfDef, LROfUse) ) { + // If the two RegTypes are the same + if (!RCOfDef->getInterference(LROfDef, LROfUse) ) { - unsigned CombinedDegree = - LROfDef->getUserIGNode()->getNumOfNeighbors() + - LROfUse->getUserIGNode()->getNumOfNeighbors(); + unsigned CombinedDegree = + LROfDef->getUserIGNode()->getNumOfNeighbors() + + LROfUse->getUserIGNode()->getNumOfNeighbors(); if (CombinedDegree > RCOfDef->getNumOfAvailRegs()) { // get more precise estimate of combined degree @@ -373,19 +373,19 @@ getCombinedDegree(LROfUse->getUserIGNode()); } - if (CombinedDegree <= RCOfDef->getNumOfAvailRegs()) { - // if both LRs do not have different pre-assigned colors - // and both LRs do not have suggested colors + if (CombinedDegree <= RCOfDef->getNumOfAvailRegs()) { + // if both LRs do not have different pre-assigned colors + // and both LRs do not have suggested colors if (! InterfsPreventCoalescing(*LROfDef, *LROfUse)) { - RCOfDef->mergeIGNodesOfLRs(LROfDef, LROfUse); - unionAndUpdateLRs(LROfDef, LROfUse); - } - - } // if combined degree is less than # of regs - } // if def and use do not interfere - }// if reg classes are the same - } // for all uses - } // if def + RCOfDef->mergeIGNodesOfLRs(LROfDef, LROfUse); + unionAndUpdateLRs(LROfDef, LROfUse); + } + + } // if combined degree is less than # of regs + } // if def and use do not interfere + }// if reg classes are the same + } // for all uses + } // if def } // for all defs } // for all machine instructions } // for all BBs Index: llvm/lib/Target/SparcV9/RegAlloc/LiveRangeInfo.h diff -u llvm/lib/Target/SparcV9/RegAlloc/LiveRangeInfo.h:1.28 llvm/lib/Target/SparcV9/RegAlloc/LiveRangeInfo.h:1.29 --- llvm/lib/Target/SparcV9/RegAlloc/LiveRangeInfo.h:1.28 Sun Jun 12 18:52:58 2005 +++ llvm/lib/Target/SparcV9/RegAlloc/LiveRangeInfo.h Wed Jul 27 00:53:44 2005 @@ -78,8 +78,8 @@ public: LiveRangeInfo(const Function *F, - const TargetMachine& tm, - std::vector & RCList); + const TargetMachine& tm, + std::vector & RCList); /// Destructor to destroy all LiveRanges in the V9LiveRange Map Index: llvm/lib/Target/SparcV9/RegAlloc/PhyRegAlloc.cpp diff -u llvm/lib/Target/SparcV9/RegAlloc/PhyRegAlloc.cpp:1.169 llvm/lib/Target/SparcV9/RegAlloc/PhyRegAlloc.cpp:1.170 --- llvm/lib/Target/SparcV9/RegAlloc/PhyRegAlloc.cpp:1.169 Thu Jun 16 23:01:34 2005 +++ llvm/lib/Target/SparcV9/RegAlloc/PhyRegAlloc.cpp Wed Jul 27 00:53:44 2005 @@ -131,7 +131,7 @@ /// instruction. /// void PhyRegAlloc::addInterference(const Value *Def, const ValueSet *LVSet, - bool isCallInst) { + bool isCallInst) { ValueSet::const_iterator LIt = LVSet->begin(); // get the live range of instruction @@ -167,7 +167,7 @@ /// the return value does not interfere with that call itself). /// void PhyRegAlloc::setCallInterferences(const MachineInstr *MInst, - const ValueSet *LVSetAft) { + const ValueSet *LVSetAft) { if (DEBUG_RA >= RA_DEBUG_Interference) std::cerr << "\n For call inst: " << *MInst; @@ -185,7 +185,7 @@ std::cerr << "\n\tLR after Call: " << *LR << "\n"; LR->setCallInterference(); if (DEBUG_RA >= RA_DEBUG_Interference) - std::cerr << "\n ++After adding call interference for LR: " << *LR << "\n"; + std::cerr << "\n ++After adding call interference for LR: " << *LR << "\n"; } } @@ -242,29 +242,29 @@ bool isCallInst = TM.getInstrInfo()->isCall(MInst->getOpcode()); if (isCallInst) { - // set the isCallInterference flag of each live range which extends - // across this call instruction. This information is used by graph - // coloring algorithm to avoid allocating volatile colors to live ranges - // that span across calls (since they have to be saved/restored) - setCallInterferences(MInst, &LVSetAI); + // set the isCallInterference flag of each live range which extends + // across this call instruction. This information is used by graph + // coloring algorithm to avoid allocating volatile colors to live ranges + // that span across calls (since they have to be saved/restored) + setCallInterferences(MInst, &LVSetAI); } // iterate over all MI operands to find defs for (MachineInstr::const_val_op_iterator OpI = MInst->begin(), OpE = MInst->end(); OpI != OpE; ++OpI) { - if (OpI.isDef()) // create a new LR since def - addInterference(*OpI, &LVSetAI, isCallInst); + if (OpI.isDef()) // create a new LR since def + addInterference(*OpI, &LVSetAI, isCallInst); - // Calculate the spill cost of each live range - V9LiveRange *LR = LRI->getLiveRangeForValue(*OpI); - if (LR) LR->addSpillCost(BBLoopDepthCost); + // Calculate the spill cost of each live range + V9LiveRange *LR = LRI->getLiveRangeForValue(*OpI); + if (LR) LR->addSpillCost(BBLoopDepthCost); } // Also add interference for any implicit definitions in a machine // instr (currently, only calls have this). unsigned NumOfImpRefs = MInst->getNumImplicitRefs(); for (unsigned z=0; z < NumOfImpRefs; z++) if (MInst->getImplicitOp(z).isDef()) - addInterference( MInst->getImplicitRef(z), &LVSetAI, isCallInst ); + addInterference( MInst->getImplicitRef(z), &LVSetAI, isCallInst ); } // for all machine instructions in BB } // for all BBs in function @@ -294,13 +294,13 @@ const V9LiveRange *LROfOp2 = LRI->getLiveRangeForValue(*It2); if (LROfOp2) { - RegClass *RCOfOp1 = LROfOp1->getRegClass(); - RegClass *RCOfOp2 = LROfOp2->getRegClass(); + RegClass *RCOfOp1 = LROfOp1->getRegClass(); + RegClass *RCOfOp2 = LROfOp2->getRegClass(); - if (RCOfOp1 == RCOfOp2 ){ - RCOfOp1->setInterference( LROfOp1, LROfOp2 ); - setInterf = true; - } + if (RCOfOp1 == RCOfOp2 ){ + RCOfOp1->setInterference( LROfOp1, LROfOp2 ); + setInterf = true; + } } // if Op2 has a LR } // for all other defs in machine instr } // for all operands in an instruction @@ -556,7 +556,7 @@ // do not process Phis if (MInst->getOpcode() == V9::PHI) - continue; + continue; // if there are any added instructions... if (AddedInstrMap.count(MInst)) { @@ -614,14 +614,14 @@ void PhyRegAlloc::insertCode4SpilledLR(const V9LiveRange *LR, MachineBasicBlock::iterator& MII, MachineBasicBlock &MBB, - const unsigned OpNum) { + const unsigned OpNum) { MachineInstr *MInst = MII; const BasicBlock *BB = MBB.getBasicBlock(); assert((! TM.getInstrInfo()->isCall(MInst->getOpcode()) || OpNum == 0) && "Outgoing arg of a call must be handled elsewhere (func arg ok)"); assert(! TM.getInstrInfo()->isReturn(MInst->getOpcode()) && - "Return value of a ret must be handled elsewhere"); + "Return value of a ret must be handled elsewhere"); MachineOperand& Op = MInst->getOperand(OpNum); bool isDef = Op.isDef(); @@ -778,33 +778,33 @@ if (LR) { if (! LR->isMarkedForSpill()) { assert(LR->hasColor() && "LR is neither spilled nor colored?"); - unsigned RCID = LR->getRegClassID(); - unsigned Color = LR->getColor(); + unsigned RCID = LR->getRegClassID(); + unsigned Color = LR->getColor(); - if (MRI.isRegVolatile(RCID, Color) ) { - // if this is a call to the first-level reoptimizer - // instrumentation entry point, and the register is not - // modified by call, don't save and restore it. - if (isLLVMFirstTrigger && !MRI.modifiedByCall(RCID, Color)) - continue; - - // if the value is in both LV sets (i.e., live before and after - // the call machine instruction) - unsigned Reg = MRI.getUnifiedRegNum(RCID, Color); - - // if we haven't already pushed this register... - if( PushedRegSet.find(Reg) == PushedRegSet.end() ) { - unsigned RegType = MRI.getRegTypeForLR(LR); - - // Now get two instructions - to push on stack and pop from stack - // and add them to InstrnsBefore and InstrnsAfter of the - // call instruction - int StackOff = + if (MRI.isRegVolatile(RCID, Color) ) { + // if this is a call to the first-level reoptimizer + // instrumentation entry point, and the register is not + // modified by call, don't save and restore it. + if (isLLVMFirstTrigger && !MRI.modifiedByCall(RCID, Color)) + continue; + + // if the value is in both LV sets (i.e., live before and after + // the call machine instruction) + unsigned Reg = MRI.getUnifiedRegNum(RCID, Color); + + // if we haven't already pushed this register... + if( PushedRegSet.find(Reg) == PushedRegSet.end() ) { + unsigned RegType = MRI.getRegTypeForLR(LR); + + // Now get two instructions - to push on stack and pop from stack + // and add them to InstrnsBefore and InstrnsAfter of the + // call instruction + int StackOff = MF->getInfo()->pushTempValue(MRI.getSpilledRegSize(RegType)); - //---- Insert code for pushing the reg on stack ---------- + //---- Insert code for pushing the reg on stack ---------- - std::vector AdIBef, AdIAft; + std::vector AdIBef, AdIAft; // We may need a scratch register to copy the saved value // to/from memory. This may itself have to insert code to @@ -834,8 +834,8 @@ instrnsBefore.insert(instrnsBefore.end(), AdIAft.begin(), AdIAft.end()); - //---- Insert code for popping the reg from the stack ---------- - AdIBef.clear(); + //---- Insert code for popping the reg from the stack ---------- + AdIBef.clear(); AdIAft.clear(); // We may need a scratch register to copy the saved value @@ -855,26 +855,26 @@ instrnsAfter.insert(instrnsAfter.end(), AdIBef.begin(), AdIBef.end()); - MRI.cpMem2RegMI(instrnsAfter, MRI.getFramePointer(), StackOff, + MRI.cpMem2RegMI(instrnsAfter, MRI.getFramePointer(), StackOff, Reg, RegType, scratchReg); if (AdIAft.size() > 0) instrnsAfter.insert(instrnsAfter.end(), AdIAft.begin(), AdIAft.end()); - - PushedRegSet.insert(Reg); + + PushedRegSet.insert(Reg); - if(DEBUG_RA) { - std::cerr << "\nFor call inst:" << *CallMI; - std::cerr << " -inserted caller saving instrs: Before:\n\t "; + if(DEBUG_RA) { + std::cerr << "\nFor call inst:" << *CallMI; + std::cerr << " -inserted caller saving instrs: Before:\n\t "; for_each(instrnsBefore.begin(), instrnsBefore.end(), std::mem_fun(&MachineInstr::dump)); - std::cerr << " -and After:\n\t "; + std::cerr << " -and After:\n\t "; for_each(instrnsAfter.begin(), instrnsAfter.end(), std::mem_fun(&MachineInstr::dump)); - } - } // if not already pushed - } // if LR has a volatile color + } + } // if not already pushed + } // if LR has a volatile color } // if LR has color } // if there is a LR for Var } // for each value in the LV set after instruction @@ -1280,7 +1280,7 @@ // RegClassList. This must be done before calling constructLiveRanges(). for (unsigned rc = 0; rc != NumOfRegClasses; ++rc) RegClassList.push_back (new RegClass (Fn, TM.getRegInfo(), - MRI.getMachineRegClass(rc))); + MRI.getMachineRegClass(rc))); LRI->constructLiveRanges(); // create LR info if (DEBUG_RA >= RA_DEBUG_LiveRanges) Index: llvm/lib/Target/SparcV9/RegAlloc/PhyRegAlloc.h diff -u llvm/lib/Target/SparcV9/RegAlloc/PhyRegAlloc.h:1.71 llvm/lib/Target/SparcV9/RegAlloc/PhyRegAlloc.h:1.72 --- llvm/lib/Target/SparcV9/RegAlloc/PhyRegAlloc.h:1.71 Sun Jun 12 18:52:58 2005 +++ llvm/lib/Target/SparcV9/RegAlloc/PhyRegAlloc.h Wed Jul 27 00:53:44 2005 @@ -118,7 +118,7 @@ SavedStateMapTy FnAllocState; void addInterference(const Value *Def, const ValueSet *LVSet, - bool isCallInst); + bool isCallInst); bool markAllocatedRegs(MachineInstr* MInst); void addInterferencesForArgs(); @@ -131,10 +131,10 @@ void finishSavingState(Module &M); void setCallInterferences(const MachineInstr *MI, - const ValueSet *LVSetAft); + const ValueSet *LVSetAft); void move2DelayedInstr(const MachineInstr *OrigMI, - const MachineInstr *DelayedMI); + const MachineInstr *DelayedMI); void markUnusableSugColors(); void allocateStackSpace4SpilledLRs(); @@ -158,7 +158,7 @@ MachineBasicBlock &MBB); int getUsableUniRegAtMI(int RegType, const ValueSet *LVSetBef, - MachineInstr *MI, + MachineInstr *MI, std::vector& MIBef, std::vector& MIAft); Index: llvm/lib/Target/SparcV9/RegAlloc/RegClass.cpp diff -u llvm/lib/Target/SparcV9/RegAlloc/RegClass.cpp:1.33 llvm/lib/Target/SparcV9/RegAlloc/RegClass.cpp:1.34 --- llvm/lib/Target/SparcV9/RegAlloc/RegClass.cpp:1.33 Sun Jun 12 18:52:58 2005 +++ llvm/lib/Target/SparcV9/RegAlloc/RegClass.cpp Wed Jul 27 00:53:44 2005 @@ -25,7 +25,7 @@ //---------------------------------------------------------------------------- RegClass::RegClass(const Function *M, const SparcV9RegInfo *_MRI_, - const TargetRegClassInfo *_MRC_) + const TargetRegClassInfo *_MRC_) : Meth(M), MRI(_MRI_), MRC(_MRC_), RegClassID( _MRC_->getRegClassID() ), IG(this), IGNodeStack() { @@ -136,7 +136,7 @@ IGNode->pushOnStack(); // set OnStack and dec deg of neighs if (DEBUG_RA >= RA_DEBUG_Coloring) { - std::cerr << " pushed un-constrained IGNode " << IGNode->getIndex() + std::cerr << " pushed un-constrained IGNode " << IGNode->getIndex() << " on to stack\n"; } } @@ -169,15 +169,15 @@ if (!IGNode->isOnStack()) { double SpillCost = (double) IGNode->getParentLR()->getSpillCost() / - (double) (IGNode->getCurDegree() + 1); + (double) (IGNode->getCurDegree() + 1); if (isFirstNode) { // for the first IG node - MinSpillCost = SpillCost; - MinCostIGNode = IGNode; - isFirstNode = false; + MinSpillCost = SpillCost; + MinCostIGNode = IGNode; + isFirstNode = false; } else if (MinSpillCost > SpillCost) { - MinSpillCost = SpillCost; - MinCostIGNode = IGNode; + MinSpillCost = SpillCost; + MinCostIGNode = IGNode; } } } Index: llvm/lib/Target/SparcV9/RegAlloc/RegClass.h diff -u llvm/lib/Target/SparcV9/RegAlloc/RegClass.h:1.25 llvm/lib/Target/SparcV9/RegAlloc/RegClass.h:1.26 --- llvm/lib/Target/SparcV9/RegAlloc/RegClass.h:1.25 Sun Jun 12 18:52:58 2005 +++ llvm/lib/Target/SparcV9/RegAlloc/RegClass.h Wed Jul 27 00:53:44 2005 @@ -87,8 +87,8 @@ public: RegClass(const Function *M, - const SparcV9RegInfo *_MRI_, - const TargetRegClassInfo *_MRC_); + const SparcV9RegInfo *_MRI_, + const TargetRegClassInfo *_MRC_); inline void createInterferenceGraph() { IG.createGraph(); } @@ -113,15 +113,15 @@ { IG.addLRToIG(LR); } inline void setInterference(const V9LiveRange *const LR1, - const V9LiveRange *const LR2) + const V9LiveRange *const LR2) { IG.setInterference(LR1, LR2); } inline unsigned getInterference(const V9LiveRange *const LR1, - const V9LiveRange *const LR2) const + const V9LiveRange *const LR2) const { return IG.getInterference(LR1, LR2); } inline void mergeIGNodesOfLRs(const V9LiveRange *const LR1, - V9LiveRange *const LR2) + V9LiveRange *const LR2) { IG.mergeIGNodesOfLRs(LR1, LR2); } From lattner at cs.uiuc.edu Wed Jul 27 00:58:12 2005 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Wed, 27 Jul 2005 00:58:12 -0500 Subject: [llvm-commits] CVS: llvm/lib/Target/Alpha/AlphaCodeEmitter.cpp Message-ID: <200507270558.AAA20849@zion.cs.uiuc.edu> Changes in directory llvm/lib/Target/Alpha: AlphaCodeEmitter.cpp updated: 1.1 -> 1.2 --- Log message: fix some warnings when compiled with 32-bit hosts --- Diffs of the changes: (+2 -2) AlphaCodeEmitter.cpp | 4 ++-- 1 files changed, 2 insertions(+), 2 deletions(-) Index: llvm/lib/Target/Alpha/AlphaCodeEmitter.cpp diff -u llvm/lib/Target/Alpha/AlphaCodeEmitter.cpp:1.1 llvm/lib/Target/Alpha/AlphaCodeEmitter.cpp:1.2 --- llvm/lib/Target/Alpha/AlphaCodeEmitter.cpp:1.1 Fri Jul 22 15:52:16 2005 +++ llvm/lib/Target/Alpha/AlphaCodeEmitter.cpp Wed Jul 27 00:58:01 2005 @@ -101,7 +101,7 @@ } void AlphaCodeEmitter::emitBasicBlock(MachineBasicBlock &MBB) { - uint64_t Addr = MCE.getCurrentPCValue(); + uintptr_t Addr = MCE.getCurrentPCValue(); BasicBlockAddrs[&MBB] = (unsigned*)Addr; for (MachineBasicBlock::iterator I = MBB.begin(), E = MBB.end(); @@ -216,7 +216,7 @@ Reloc, MO.getConstantPoolIndex(), Offset)); } else if (MO.isMachineBasicBlock()) { - unsigned* CurrPC = (unsigned*)MCE.getCurrentPCValue(); + unsigned* CurrPC = (unsigned*)(intptr_t)MCE.getCurrentPCValue(); BBRefs.push_back(std::make_pair(MO.getMachineBasicBlock(), CurrPC)); }else { std::cerr << "ERROR: Unknown type of MachineOperand: " << MO << "\n"; From natebegeman at mac.com Wed Jul 27 01:06:41 2005 From: natebegeman at mac.com (Nate Begeman) Date: Wed, 27 Jul 2005 01:06:41 -0500 Subject: [llvm-commits] CVS: llvm/lib/Target/PowerPC/PPC32RegisterInfo.cpp README.txt Message-ID: <200507270606.BAA27805@zion.cs.uiuc.edu> Changes in directory llvm/lib/Target/PowerPC: PPC32RegisterInfo.cpp updated: 1.12 -> 1.13 README.txt updated: 1.24 -> 1.25 --- Log message: Implement the optimization for the Red Zone on Darwin. This removes the unnecessary SP manipulation in leaf routines that don't need it. --- Diffs of the changes: (+8 -4) PPC32RegisterInfo.cpp | 11 ++++++++--- README.txt | 1 - 2 files changed, 8 insertions(+), 4 deletions(-) Index: llvm/lib/Target/PowerPC/PPC32RegisterInfo.cpp diff -u llvm/lib/Target/PowerPC/PPC32RegisterInfo.cpp:1.12 llvm/lib/Target/PowerPC/PPC32RegisterInfo.cpp:1.13 --- llvm/lib/Target/PowerPC/PPC32RegisterInfo.cpp:1.12 Fri Apr 22 12:54:30 2005 +++ llvm/lib/Target/PowerPC/PPC32RegisterInfo.cpp Wed Jul 27 01:06:29 2005 @@ -245,8 +245,13 @@ NumBytes += MFI->getMaxCallFrameSize(); } - // Do we need to allocate space on the stack? - if (NumBytes == 0) return; + // If we are a leaf function, and use up to 224 bytes of stack space, + // and don't have a frame pointer, then we do not need to adjust the stack + // pointer (we fit in the Red Zone). + if ((NumBytes == 0) || (NumBytes <= 224 && !hasFP(MF) && !MFI->hasCalls())) { + MFI->setStackSize(0); + return; + } // Add the size of R1 to NumBytes size for the store of R1 to the bottom // of the stack and round the size to a multiple of the alignment. @@ -258,7 +263,7 @@ // Update frame info to pretend that this is part of the stack... MFI->setStackSize(NumBytes); - // adjust stack pointer: r1 -= numbytes + // If , adjust stack pointer: r1 -= numbytes. if (NumBytes <= 32768) { MI=BuildMI(PPC::STWU,3).addReg(PPC::R1).addSImm(-NumBytes).addReg(PPC::R1); MBB.insert(MBBI, MI); Index: llvm/lib/Target/PowerPC/README.txt diff -u llvm/lib/Target/PowerPC/README.txt:1.24 llvm/lib/Target/PowerPC/README.txt:1.25 --- llvm/lib/Target/PowerPC/README.txt:1.24 Tue Jul 26 14:07:51 2005 +++ llvm/lib/Target/PowerPC/README.txt Wed Jul 27 01:06:29 2005 @@ -3,7 +3,6 @@ * implement do-loop -> bdnz transform * implement powerpc-64 for darwin * use stfiwx in float->int -* take advantage of the darwin red zone in PPC32RegisterInfo.cpp * be able to combine sequences like the following into 2 instructions: lis r2, ha16(l2__ZTV4Cell) la r2, lo16(l2__ZTV4Cell)(r2) From jeffc at jolt-lang.org Wed Jul 27 01:12:55 2005 From: jeffc at jolt-lang.org (Jeff Cohen) Date: Wed, 27 Jul 2005 01:12:55 -0500 Subject: [llvm-commits] CVS: llvm/lib/Analysis/DataStructure/BottomUpClosure.cpp Message-ID: <200507270612.BAA32115@zion.cs.uiuc.edu> Changes in directory llvm/lib/Analysis/DataStructure: BottomUpClosure.cpp updated: 1.115 -> 1.116 --- Log message: Eliminate all remaining tabs and trailing spaces. --- Diffs of the changes: (+1 -1) BottomUpClosure.cpp | 2 +- 1 files changed, 1 insertion(+), 1 deletion(-) Index: llvm/lib/Analysis/DataStructure/BottomUpClosure.cpp diff -u llvm/lib/Analysis/DataStructure/BottomUpClosure.cpp:1.115 llvm/lib/Analysis/DataStructure/BottomUpClosure.cpp:1.116 --- llvm/lib/Analysis/DataStructure/BottomUpClosure.cpp:1.115 Mon Apr 25 14:16:31 2005 +++ llvm/lib/Analysis/DataStructure/BottomUpClosure.cpp Wed Jul 27 01:12:33 2005 @@ -418,7 +418,7 @@ DSG->getReturnNodes().insert(std::make_pair(F, DSNodeHandle())); if (F->getName() == "free") { // Taking the address of free. - + // Free should take a single pointer argument, mark it as heap memory. DSNode *N = new DSNode(0, DSG); N->setHeapNodeMarker(); From jeffc at jolt-lang.org Wed Jul 27 01:12:58 2005 From: jeffc at jolt-lang.org (Jeff Cohen) Date: Wed, 27 Jul 2005 01:12:58 -0500 Subject: [llvm-commits] CVS: llvm/lib/Target/SparcV9/InstrSched/InstrScheduling.cpp SchedGraph.cpp SchedGraphCommon.cpp SchedPriorities.cpp Message-ID: <200507270612.BAA32197@zion.cs.uiuc.edu> Changes in directory llvm/lib/Target/SparcV9/InstrSched: InstrScheduling.cpp updated: 1.84 -> 1.85 SchedGraph.cpp updated: 1.70 -> 1.71 SchedGraphCommon.cpp updated: 1.10 -> 1.11 SchedPriorities.cpp updated: 1.38 -> 1.39 --- Log message: Eliminate all remaining tabs and trailing spaces. --- Diffs of the changes: (+20 -20) InstrScheduling.cpp | 26 +++++++++++++------------- SchedGraph.cpp | 8 ++++---- SchedGraphCommon.cpp | 4 ++-- SchedPriorities.cpp | 2 +- 4 files changed, 20 insertions(+), 20 deletions(-) Index: llvm/lib/Target/SparcV9/InstrSched/InstrScheduling.cpp diff -u llvm/lib/Target/SparcV9/InstrSched/InstrScheduling.cpp:1.84 llvm/lib/Target/SparcV9/InstrSched/InstrScheduling.cpp:1.85 --- llvm/lib/Target/SparcV9/InstrSched/InstrScheduling.cpp:1.84 Wed Jul 27 00:53:43 2005 +++ llvm/lib/Target/SparcV9/InstrSched/InstrScheduling.cpp Wed Jul 27 01:12:34 2005 @@ -672,14 +672,14 @@ && ! S.schedPrio.nodeIsReady(*SI)) { // successor not scheduled and not marked ready; check *its* preds. - + bool succIsReady = true; for (sg_pred_const_iterator P=pred_begin(*SI); P != pred_end(*SI); ++P) if (! (*P)->isDummyNode() && ! S.isScheduled(*P)) { succIsReady = false; break; } - + if (succIsReady) // add the successor to the ready list S.schedPrio.insertReady(*SI); } @@ -828,7 +828,7 @@ S.addChoiceToSlot(s, S.getChoice(i)); noSlotFound = false; } - + // No slot before `delayedNodeSlot' was found for this opCode // Use a later slot, and allow some delay slots to fall in // the next cycle. @@ -838,9 +838,9 @@ S.addChoiceToSlot(s, S.getChoice(i)); break; } - + assert(s < S.nslots && "No feasible slot for instruction?"); - + highestSlotUsed = std::max(highestSlotUsed, (int) s); } @@ -867,7 +867,7 @@ const SchedGraphNode* breakingNode=S.getChoice(indexForBreakingNode); unsigned breakingSlot = INT_MAX; unsigned int nslotsToUse = S.nslots; - + // Find the last possible slot for this instruction. for (int s = S.nslots-1; s >= (int) startSlot; s--) if (S.schedInfo.instrCanUseSlot(breakingNode->getOpcode(), s)) { @@ -884,7 +884,7 @@ i < S.getNumChoices() && i < indexForBreakingNode; i++) { MachineOpCode opCode =S.getChoice(i)->getOpcode(); - + // If a higher priority instruction cannot be assigned to // any earlier slots, don't schedule the breaking instruction. // @@ -896,10 +896,10 @@ foundLowerSlot = true; nslotsToUse = breakingSlot; // RESETS LOOP UPPER BOUND! } - + S.addChoiceToSlot(s, S.getChoice(i)); } - + if (!foundLowerSlot) breakingSlot = INT_MAX; // disable breaking instr } @@ -912,7 +912,7 @@ nslotsToUse = breakingSlot; } else nslotsToUse = S.nslots; - + // For lower priority instructions than the one that breaks the // group, only assign them to slots lower than the breaking slot. // Otherwise, just ignore the instruction. @@ -1198,7 +1198,7 @@ sdelayNodeVec.push_back(graph->getGraphNodeForInstr(MBBI)); else { nopNodeVec.push_back(graph->getGraphNodeForInstr(MBBI)); - + //remove the MI from the Machine Code For Instruction const TerminatorInst *TI = MBB.getBasicBlock()->getTerminator(); MachineCodeForInstruction& llvmMvec = @@ -1350,7 +1350,7 @@ nextTime++; } } while (S.isched.getInstr(nextSlot, nextTime) != NULL); - + S.scheduleInstr(delayNodeVec[i], nextSlot, nextTime); break; } @@ -1457,7 +1457,7 @@ bool InstructionSchedulingWithSSA::runOnFunction(Function &F) { - SchedGraphSet graphSet(&F, target); + SchedGraphSet graphSet(&F, target); if (SchedDebugLevel >= Sched_PrintSchedGraphs) { std::cerr << "\n*** SCHEDULING GRAPHS FOR INSTRUCTION SCHEDULING\n"; Index: llvm/lib/Target/SparcV9/InstrSched/SchedGraph.cpp diff -u llvm/lib/Target/SparcV9/InstrSched/SchedGraph.cpp:1.70 llvm/lib/Target/SparcV9/InstrSched/SchedGraph.cpp:1.71 --- llvm/lib/Target/SparcV9/InstrSched/SchedGraph.cpp:1.70 Wed Jul 27 00:53:43 2005 +++ llvm/lib/Target/SparcV9/InstrSched/SchedGraph.cpp Wed Jul 27 01:12:34 2005 @@ -365,7 +365,7 @@ new SchedGraphEdge(prevNode, node, regNum, SchedGraphEdge::AntiDep); } - + if (prevIsDef) if (!isDef || isDefAndUse) new SchedGraphEdge(prevNode, node, regNum, @@ -646,7 +646,7 @@ this->addMachineRegEdges(regToRefVecMap, target); // Finally, add edges from the dummy root and to dummy leaf - this->addDummyEdges(); + this->addDummyEdges(); } @@ -691,13 +691,13 @@ << sink->getNodeId() << "] : "; switch(depType) { - case SchedGraphEdge::CtrlDep: + case SchedGraphEdge::CtrlDep: os<< "Control Dep"; break; case SchedGraphEdge::ValueDep: os<< "Reg Value " << *val; break; - case SchedGraphEdge::MemoryDep: + case SchedGraphEdge::MemoryDep: os<< "Memory Dep"; break; case SchedGraphEdge::MachineRegister: Index: llvm/lib/Target/SparcV9/InstrSched/SchedGraphCommon.cpp diff -u llvm/lib/Target/SparcV9/InstrSched/SchedGraphCommon.cpp:1.10 llvm/lib/Target/SparcV9/InstrSched/SchedGraphCommon.cpp:1.11 --- llvm/lib/Target/SparcV9/InstrSched/SchedGraphCommon.cpp:1.10 Wed Jul 27 00:53:43 2005 +++ llvm/lib/Target/SparcV9/InstrSched/SchedGraphCommon.cpp Wed Jul 27 01:12:34 2005 @@ -173,8 +173,8 @@ void SchedGraphCommon::eraseIncidentEdges(SchedGraphNodeCommon* node, bool addDummyEdges) { - this->eraseIncomingEdges(node, addDummyEdges); - this->eraseOutgoingEdges(node, addDummyEdges); + this->eraseIncomingEdges(node, addDummyEdges); + this->eraseOutgoingEdges(node, addDummyEdges); } } // End llvm namespace Index: llvm/lib/Target/SparcV9/InstrSched/SchedPriorities.cpp diff -u llvm/lib/Target/SparcV9/InstrSched/SchedPriorities.cpp:1.38 llvm/lib/Target/SparcV9/InstrSched/SchedPriorities.cpp:1.39 --- llvm/lib/Target/SparcV9/InstrSched/SchedPriorities.cpp:1.38 Wed Jul 27 00:53:43 2005 +++ llvm/lib/Target/SparcV9/InstrSched/SchedPriorities.cpp Wed Jul 27 01:12:34 2005 @@ -173,7 +173,7 @@ inline int SchedPriorities::chooseByRule3(std::vector& mcands) { assert(mcands.size() >= 1 && "Should have at least one candidate here."); - int maxUses = candsAsHeap.getNode(mcands[0])->getNumOutEdges(); + int maxUses = candsAsHeap.getNode(mcands[0])->getNumOutEdges(); int indexWithMaxUses = 0; for (unsigned i=1, N = mcands.size(); i < N; i++) { int numUses = candsAsHeap.getNode(mcands[i])->getNumOutEdges(); From jeffc at jolt-lang.org Wed Jul 27 01:12:57 2005 From: jeffc at jolt-lang.org (Jeff Cohen) Date: Wed, 27 Jul 2005 01:12:57 -0500 Subject: [llvm-commits] CVS: llvm/lib/Bytecode/Writer/Writer.cpp Message-ID: <200507270612.BAA32119@zion.cs.uiuc.edu> Changes in directory llvm/lib/Bytecode/Writer: Writer.cpp updated: 1.106 -> 1.107 --- Log message: Eliminate all remaining tabs and trailing spaces. --- Diffs of the changes: (+1 -1) Writer.cpp | 2 +- 1 files changed, 1 insertion(+), 1 deletion(-) Index: llvm/lib/Bytecode/Writer/Writer.cpp diff -u llvm/lib/Bytecode/Writer/Writer.cpp:1.106 llvm/lib/Bytecode/Writer/Writer.cpp:1.107 --- llvm/lib/Bytecode/Writer/Writer.cpp:1.106 Sat Jun 18 13:34:51 2005 +++ llvm/lib/Bytecode/Writer/Writer.cpp Wed Jul 27 01:12:33 2005 @@ -628,7 +628,7 @@ Opcode = 57; // FastCC invoke. else if (II->getCallingConv() != CallingConv::C) Opcode = 56; // Invoke escape sequence. - + } else if (isa(I) && cast(I).isVolatile()) { Opcode = 62; } else if (isa(I) && cast(I).isVolatile()) { From jeffc at jolt-lang.org Wed Jul 27 01:12:57 2005 From: jeffc at jolt-lang.org (Jeff Cohen) Date: Wed, 27 Jul 2005 01:12:57 -0500 Subject: [llvm-commits] CVS: llvm/lib/System/Mutex.cpp Message-ID: <200507270612.BAA32142@zion.cs.uiuc.edu> Changes in directory llvm/lib/System: Mutex.cpp updated: 1.3 -> 1.4 --- Log message: Eliminate all remaining tabs and trailing spaces. --- Diffs of the changes: (+7 -7) Mutex.cpp | 14 +++++++------- 1 files changed, 7 insertions(+), 7 deletions(-) Index: llvm/lib/System/Mutex.cpp diff -u llvm/lib/System/Mutex.cpp:1.3 llvm/lib/System/Mutex.cpp:1.4 --- llvm/lib/System/Mutex.cpp:1.3 Tue Jul 12 22:02:06 2005 +++ llvm/lib/System/Mutex.cpp Wed Jul 27 01:12:33 2005 @@ -29,9 +29,9 @@ #include // This variable is useful for situations where the pthread library has been -// compiled with weak linkage for its interface symbols. This allows the +// compiled with weak linkage for its interface symbols. This allows the // threading support to be turned off by simply not linking against -lpthread. -// In that situation, the value of pthread_mutex_init will be 0 and +// In that situation, the value of pthread_mutex_init will be 0 and // consequently pthread_enabled will be false. In such situations, all the // pthread operations become no-ops and the functions all return false. If // pthread_mutex_init does have an address, then mutex support is enabled. @@ -48,7 +48,7 @@ if (pthread_enabled) { // Declare the pthread_mutex data structures - pthread_mutex_t* mutex = + pthread_mutex_t* mutex = static_cast(malloc(sizeof(pthread_mutex_t))); pthread_mutexattr_t attr; @@ -92,10 +92,10 @@ } } -bool +bool Mutex::acquire() { - if (pthread_enabled) + if (pthread_enabled) { pthread_mutex_t* mutex = reinterpret_cast(data_); assert(mutex != 0); @@ -106,7 +106,7 @@ return false; } -bool +bool Mutex::release() { if (pthread_enabled) @@ -120,7 +120,7 @@ return false; } -bool +bool Mutex::tryacquire() { if (pthread_enabled) From jeffc at jolt-lang.org Wed Jul 27 01:12:58 2005 From: jeffc at jolt-lang.org (Jeff Cohen) Date: Wed, 27 Jul 2005 01:12:58 -0500 Subject: [llvm-commits] CVS: llvm/lib/Target/PowerPC/PPC32CodeEmitter.cpp PPC32ISelPattern.cpp PowerPCBranchSelector.cpp PowerPCTargetMachine.cpp Message-ID: <200507270612.BAA32179@zion.cs.uiuc.edu> Changes in directory llvm/lib/Target/PowerPC: PPC32CodeEmitter.cpp updated: 1.32 -> 1.33 PPC32ISelPattern.cpp updated: 1.104 -> 1.105 PowerPCBranchSelector.cpp updated: 1.11 -> 1.12 PowerPCTargetMachine.cpp updated: 1.56 -> 1.57 --- Log message: Eliminate all remaining tabs and trailing spaces. --- Diffs of the changes: (+15 -15) PPC32CodeEmitter.cpp | 4 ++-- PPC32ISelPattern.cpp | 22 +++++++++++----------- PowerPCBranchSelector.cpp | 2 +- PowerPCTargetMachine.cpp | 2 +- 4 files changed, 15 insertions(+), 15 deletions(-) Index: llvm/lib/Target/PowerPC/PPC32CodeEmitter.cpp diff -u llvm/lib/Target/PowerPC/PPC32CodeEmitter.cpp:1.32 llvm/lib/Target/PowerPC/PPC32CodeEmitter.cpp:1.33 --- llvm/lib/Target/PowerPC/PPC32CodeEmitter.cpp:1.32 Thu Jul 21 15:44:42 2005 +++ llvm/lib/Target/PowerPC/PPC32CodeEmitter.cpp Wed Jul 27 01:12:33 2005 @@ -201,7 +201,7 @@ case PPC::LIS: if (isExternal) Reloc = PPC::reloc_absolute_ptr_high; // Pointer to stub - else + else Reloc = PPC::reloc_absolute_high; // Pointer to symbol break; case PPC::LA: @@ -221,7 +221,7 @@ case PPC::STFD: if (isExternal) Reloc = PPC::reloc_absolute_ptr_low; - else + else Reloc = PPC::reloc_absolute_low; break; } Index: llvm/lib/Target/PowerPC/PPC32ISelPattern.cpp diff -u llvm/lib/Target/PowerPC/PPC32ISelPattern.cpp:1.104 llvm/lib/Target/PowerPC/PPC32ISelPattern.cpp:1.105 --- llvm/lib/Target/PowerPC/PPC32ISelPattern.cpp:1.104 Mon Jul 25 16:15:28 2005 +++ llvm/lib/Target/PowerPC/PPC32ISelPattern.cpp Wed Jul 27 01:12:33 2005 @@ -77,7 +77,7 @@ setOperationAction(ISD::FSQRT, MVT::f64, Expand); setOperationAction(ISD::FSQRT, MVT::f32, Expand); } - + //PowerPC does not have CTPOP or CTTZ setOperationAction(ISD::CTPOP, MVT::i32 , Expand); setOperationAction(ISD::CTTZ , MVT::i32 , Expand); @@ -103,11 +103,11 @@ virtual SDOperand LowerVAStart(SDOperand Chain, SDOperand VAListP, Value *VAListV, SelectionDAG &DAG); - + virtual std::pair LowerVAArg(SDOperand Chain, SDOperand VAListP, Value *VAListV, const Type *ArgTy, SelectionDAG &DAG); - + virtual std::pair LowerFrameReturnAddress(bool isFrameAddr, SDOperand Chain, unsigned Depth, SelectionDAG &DAG); @@ -288,7 +288,7 @@ std::pair PPC32TargetLowering::LowerCallTo(SDOperand Chain, const Type *RetTy, bool isVarArg, - unsigned CallingConv, bool isTailCall, + unsigned CallingConv, bool isTailCall, SDOperand Callee, ArgListTy &Args, SelectionDAG &DAG) { // args_to_use will accumulate outgoing args for the ISD::CALL case in @@ -992,7 +992,7 @@ bool ISel::SelectBitfieldInsert(SDOperand OR, unsigned Result) { bool IsRotate = false; unsigned TgtMask = 0xFFFFFFFF, InsMask = 0xFFFFFFFF, Amount = 0; - + SDOperand Op0 = OR.getOperand(0); SDOperand Op1 = OR.getOperand(1); @@ -1046,21 +1046,21 @@ // constant as its input, make that the inserted value so that we can combine // the shift into the rotate part of the rlwimi instruction if (Op0Opc == ISD::AND && Op1Opc == ISD::AND) { - if (Op1.getOperand(0).getOpcode() == ISD::SHL || + if (Op1.getOperand(0).getOpcode() == ISD::SHL || Op1.getOperand(0).getOpcode() == ISD::SRL) { - if (ConstantSDNode *CN = + if (ConstantSDNode *CN = dyn_cast(Op1.getOperand(0).getOperand(1).Val)) { - Amount = Op1.getOperand(0).getOpcode() == ISD::SHL ? + Amount = Op1.getOperand(0).getOpcode() == ISD::SHL ? CN->getValue() : 32 - CN->getValue(); Tmp3 = SelectExpr(Op1.getOperand(0).getOperand(0)); } } else if (Op0.getOperand(0).getOpcode() == ISD::SHL || Op0.getOperand(0).getOpcode() == ISD::SRL) { - if (ConstantSDNode *CN = + if (ConstantSDNode *CN = dyn_cast(Op0.getOperand(0).getOperand(1).Val)) { std::swap(Op0, Op1); std::swap(TgtMask, InsMask); - Amount = Op1.getOperand(0).getOpcode() == ISD::SHL ? + Amount = Op1.getOperand(0).getOpcode() == ISD::SHL ? CN->getValue() : 32 - CN->getValue(); Tmp3 = SelectExpr(Op1.getOperand(0).getOperand(0)); } @@ -1878,7 +1878,7 @@ return SelectExpr(BuildSDIVSequence(N)); else return SelectExpr(BuildUDIVSequence(N)); - } + } Tmp1 = SelectExpr(N.getOperand(0)); Tmp2 = SelectExpr(N.getOperand(1)); switch (DestType) { Index: llvm/lib/Target/PowerPC/PowerPCBranchSelector.cpp diff -u llvm/lib/Target/PowerPC/PowerPCBranchSelector.cpp:1.11 llvm/lib/Target/PowerPC/PowerPCBranchSelector.cpp:1.12 --- llvm/lib/Target/PowerPC/PowerPCBranchSelector.cpp:1.11 Sat Jun 18 12:37:34 2005 +++ llvm/lib/Target/PowerPC/PowerPCBranchSelector.cpp Wed Jul 27 01:12:33 2005 @@ -92,7 +92,7 @@ if (OpcodeToReplace == PPC::COND_BRANCH) { MachineBasicBlock::iterator MBBJ = MBBI; ++MBBJ; - + // condbranch operands: // 0. CR0 register // 1. bc opcode Index: llvm/lib/Target/PowerPC/PowerPCTargetMachine.cpp diff -u llvm/lib/Target/PowerPC/PowerPCTargetMachine.cpp:1.56 llvm/lib/Target/PowerPC/PowerPCTargetMachine.cpp:1.57 --- llvm/lib/Target/PowerPC/PowerPCTargetMachine.cpp:1.56 Thu Jul 21 15:44:43 2005 +++ llvm/lib/Target/PowerPC/PowerPCTargetMachine.cpp Wed Jul 27 01:12:33 2005 @@ -136,7 +136,7 @@ PICEnabled = false; bool LP64 = (0 != dynamic_cast(&TM)); - + if (EnablePPCLSR) { PM.add(createLoopStrengthReducePass()); PM.add(createCFGSimplificationPass()); From jeffc at jolt-lang.org Wed Jul 27 01:12:58 2005 From: jeffc at jolt-lang.org (Jeff Cohen) Date: Wed, 27 Jul 2005 01:12:58 -0500 Subject: [llvm-commits] CVS: llvm/lib/CodeGen/ELFWriter.cpp IntrinsicLowering.cpp Message-ID: <200507270612.BAA32145@zion.cs.uiuc.edu> Changes in directory llvm/lib/CodeGen: ELFWriter.cpp updated: 1.12 -> 1.13 IntrinsicLowering.cpp updated: 1.33 -> 1.34 --- Log message: Eliminate all remaining tabs and trailing spaces. --- Diffs of the changes: (+14 -14) ELFWriter.cpp | 26 +++++++++++++------------- IntrinsicLowering.cpp | 2 +- 2 files changed, 14 insertions(+), 14 deletions(-) Index: llvm/lib/CodeGen/ELFWriter.cpp diff -u llvm/lib/CodeGen/ELFWriter.cpp:1.12 llvm/lib/CodeGen/ELFWriter.cpp:1.13 --- llvm/lib/CodeGen/ELFWriter.cpp:1.12 Sat Jul 16 12:41:06 2005 +++ llvm/lib/CodeGen/ELFWriter.cpp Wed Jul 27 01:12:33 2005 @@ -108,15 +108,15 @@ ELFWriter::ELFSection::SHF_EXECINSTR | ELFWriter::ELFSection::SHF_ALLOC); OutBuffer = &ES->SectionData; - + // Upgrade the section alignment if required. if (ES->Align < Align) ES->Align = Align; - + // Add padding zeros to the end of the buffer to make sure that the // function will start on the correct byte alignment within the section. size_t SectionOff = OutBuffer->size(); ELFWriter::align(*OutBuffer, Align); - + FnStart = OutBuffer->size(); } @@ -125,7 +125,7 @@ void ELFCodeEmitter::finishFunction(MachineFunction &F) { // We now know the size of the function, add a symbol to represent it. ELFWriter::ELFSym FnSym(F.getFunction()); - + // Figure out the binding (linkage) of the symbol. switch (F.getFunction()->getLinkage()) { default: @@ -149,7 +149,7 @@ FnSym.SectionIdx = ES->SectionIdx; FnSym.Value = FnStart; // Value = Offset from start of Section. FnSym.Size = OutBuffer->size()-FnStart; - + // Finally, add it to the symtab. EW.SymbolTable.push_back(FnSym); } @@ -162,7 +162,7 @@ e_machine = 0; // e_machine defaults to 'No Machine' e_flags = 0; // e_flags defaults to 0, no flags. - is64Bit = TM.getTargetData().getPointerSizeInBits() == 64; + is64Bit = TM.getTargetData().getPointerSizeInBits() == 64; isLittleEndian = TM.getTargetData().isLittleEndian(); // Create the machine code emitter object for this target. @@ -181,7 +181,7 @@ // Local alias to shortenify coming code. std::vector &FH = FileHeader; - + outbyte(FH, 0x7F); // EI_MAG0 outbyte(FH, 'E'); // EI_MAG1 outbyte(FH, 'L'); // EI_MAG2 @@ -190,7 +190,7 @@ outbyte(FH, isLittleEndian ? 1 : 2); // EI_DATA outbyte(FH, 1); // EI_VERSION FH.resize(16); // EI_PAD up to 16 bytes. - + // This should change for shared objects. outhalf(FH, 1); // e_type = ET_REL outhalf(FH, e_machine); // e_machine = whatever the target wants @@ -207,7 +207,7 @@ outhalf(FH, 0); // e_phnum = # prog header entries = 0 outhalf(FH, is64Bit ? 64 : 40); // e_shentsize = sect hdr entry size - + ELFHeader_e_shnum_Offset = FH.size(); outhalf(FH, 0); // e_shnum = # of section header ents ELFHeader_e_shstrndx_Offset = FH.size(); @@ -235,7 +235,7 @@ SymbolTable.push_back(ExternalSym); return; } - + const Type *GVType = (const Type*)GV->getType(); unsigned Align = TM.getTargetData().getTypeAlignment(GVType); unsigned Size = TM.getTargetData().getTypeSize(GVType); @@ -473,11 +473,11 @@ // Now that we know where all of the sections will be emitted, set the e_shnum // entry in the ELF header. fixhalf(FileHeader, NumSections, ELFHeader_e_shnum_Offset); - + // Now that we know the offset in the file of the section table, update the // e_shoff address in the ELF header. fixaddr(FileHeader, FileOff, ELFHeader_e_shoff_Offset); - + // Now that we know all of the data in the file header, emit it and all of the // sections! O.write((char*)&FileHeader[0], FileHeader.size()); @@ -516,7 +516,7 @@ for (size_t NewFileOff = (FileOff+TableAlign-1) & ~(TableAlign-1); FileOff != NewFileOff; ++FileOff) O.put(0xAB); - + // Emit the section table itself. O.write((char*)&Table[0], Table.size()); } Index: llvm/lib/CodeGen/IntrinsicLowering.cpp diff -u llvm/lib/CodeGen/IntrinsicLowering.cpp:1.33 llvm/lib/CodeGen/IntrinsicLowering.cpp:1.34 --- llvm/lib/CodeGen/IntrinsicLowering.cpp:1.33 Wed May 11 15:24:12 2005 +++ llvm/lib/CodeGen/IntrinsicLowering.cpp Wed Jul 27 01:12:33 2005 @@ -150,7 +150,7 @@ ConstantExpr::getCast(ConstantUInt::get(Type::ULongTy, MaskValues[ct]), V->getType()); Value *LHS = BinaryOperator::createAnd(V, MaskCst, "cppop.and1", IP); - Value *VShift = new ShiftInst(Instruction::Shr, V, + Value *VShift = new ShiftInst(Instruction::Shr, V, ConstantInt::get(Type::UByteTy, i), "ctpop.sh", IP); Value *RHS = BinaryOperator::createAnd(VShift, MaskCst, "cppop.and2", IP); V = BinaryOperator::createAdd(LHS, RHS, "ctpop.step", IP); From jeffc at jolt-lang.org Wed Jul 27 01:12:57 2005 From: jeffc at jolt-lang.org (Jeff Cohen) Date: Wed, 27 Jul 2005 01:12:57 -0500 Subject: [llvm-commits] CVS: llvm/lib/Target/TargetFrameInfo.cpp TargetSubtarget.cpp Message-ID: <200507270612.BAA32127@zion.cs.uiuc.edu> Changes in directory llvm/lib/Target: TargetFrameInfo.cpp updated: 1.6 -> 1.7 TargetSubtarget.cpp updated: 1.2 -> 1.3 --- Log message: Eliminate all remaining tabs and trailing spaces. --- Diffs of the changes: (+2 -2) TargetFrameInfo.cpp | 2 +- TargetSubtarget.cpp | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) Index: llvm/lib/Target/TargetFrameInfo.cpp diff -u llvm/lib/Target/TargetFrameInfo.cpp:1.6 llvm/lib/Target/TargetFrameInfo.cpp:1.7 --- llvm/lib/Target/TargetFrameInfo.cpp:1.6 Sun Apr 24 21:55:55 2005 +++ llvm/lib/Target/TargetFrameInfo.cpp Wed Jul 27 01:12:33 2005 @@ -16,7 +16,7 @@ using namespace llvm; -TargetFrameInfo::~TargetFrameInfo() +TargetFrameInfo::~TargetFrameInfo() { } Index: llvm/lib/Target/TargetSubtarget.cpp diff -u llvm/lib/Target/TargetSubtarget.cpp:1.2 llvm/lib/Target/TargetSubtarget.cpp:1.3 --- llvm/lib/Target/TargetSubtarget.cpp:1.2 Mon Jul 11 21:59:38 2005 +++ llvm/lib/Target/TargetSubtarget.cpp Wed Jul 27 01:12:33 2005 @@ -2,7 +2,7 @@ // // The LLVM Compiler Infrastructure // -// This file was developed by Nate Begeman and is distributed under the +// This file was developed by Nate Begeman and is distributed under the // University of Illinois Open Source License. See LICENSE.TXT for details. // //===----------------------------------------------------------------------===// From jeffc at jolt-lang.org Wed Jul 27 01:12:58 2005 From: jeffc at jolt-lang.org (Jeff Cohen) Date: Wed, 27 Jul 2005 01:12:58 -0500 Subject: [llvm-commits] CVS: llvm/lib/Support/Compressor.cpp Message-ID: <200507270612.BAA32161@zion.cs.uiuc.edu> Changes in directory llvm/lib/Support: Compressor.cpp updated: 1.18 -> 1.19 --- Log message: Eliminate all remaining tabs and trailing spaces. --- Diffs of the changes: (+1 -1) Compressor.cpp | 2 +- 1 files changed, 1 insertion(+), 1 deletion(-) Index: llvm/lib/Support/Compressor.cpp diff -u llvm/lib/Support/Compressor.cpp:1.18 llvm/lib/Support/Compressor.cpp:1.19 --- llvm/lib/Support/Compressor.cpp:1.18 Fri May 13 02:05:37 2005 +++ llvm/lib/Support/Compressor.cpp Wed Jul 27 01:12:33 2005 @@ -408,7 +408,7 @@ // Decompress it int bzerr = BZ_OK; - while ( BZ_OK == (bzerr = BZ2_bzDecompress(&bzdata)) && + while ( BZ_OK == (bzerr = BZ2_bzDecompress(&bzdata)) && bzdata.avail_in != 0 ) { if (0 != getdata_uns(bzdata.next_out, bzdata.avail_out,cb,context)) { BZ2_bzDecompressEnd(&bzdata); From jeffc at jolt-lang.org Wed Jul 27 01:12:58 2005 From: jeffc at jolt-lang.org (Jeff Cohen) Date: Wed, 27 Jul 2005 01:12:58 -0500 Subject: [llvm-commits] CVS: llvm/lib/ExecutionEngine/Interpreter/Interpreter.cpp Message-ID: <200507270612.BAA32180@zion.cs.uiuc.edu> Changes in directory llvm/lib/ExecutionEngine/Interpreter: Interpreter.cpp updated: 1.24 -> 1.25 --- Log message: Eliminate all remaining tabs and trailing spaces. --- Diffs of the changes: (+1 -1) Interpreter.cpp | 2 +- 1 files changed, 1 insertion(+), 1 deletion(-) Index: llvm/lib/ExecutionEngine/Interpreter/Interpreter.cpp diff -u llvm/lib/ExecutionEngine/Interpreter/Interpreter.cpp:1.24 llvm/lib/ExecutionEngine/Interpreter/Interpreter.cpp:1.25 --- llvm/lib/ExecutionEngine/Interpreter/Interpreter.cpp:1.24 Thu Apr 21 23:06:38 2005 +++ llvm/lib/ExecutionEngine/Interpreter/Interpreter.cpp Wed Jul 27 01:12:33 2005 @@ -77,7 +77,7 @@ /// run - Start execution with the specified function and arguments. /// -GenericValue +GenericValue Interpreter::runFunction(Function *F, const std::vector &ArgValues) { assert (F && "Function *F was null at entry to run()"); From jeffc at jolt-lang.org Wed Jul 27 01:12:58 2005 From: jeffc at jolt-lang.org (Jeff Cohen) Date: Wed, 27 Jul 2005 01:12:58 -0500 Subject: [llvm-commits] CVS: llvm/lib/Target/SparcV9/RegAlloc/InterferenceGraph.cpp PhyRegAlloc.cpp Message-ID: <200507270612.BAA32217@zion.cs.uiuc.edu> Changes in directory llvm/lib/Target/SparcV9/RegAlloc: InterferenceGraph.cpp updated: 1.25 -> 1.26 PhyRegAlloc.cpp updated: 1.170 -> 1.171 --- Log message: Eliminate all remaining tabs and trailing spaces. --- Diffs of the changes: (+4 -4) InterferenceGraph.cpp | 2 +- PhyRegAlloc.cpp | 6 +++--- 2 files changed, 4 insertions(+), 4 deletions(-) Index: llvm/lib/Target/SparcV9/RegAlloc/InterferenceGraph.cpp diff -u llvm/lib/Target/SparcV9/RegAlloc/InterferenceGraph.cpp:1.25 llvm/lib/Target/SparcV9/RegAlloc/InterferenceGraph.cpp:1.26 --- llvm/lib/Target/SparcV9/RegAlloc/InterferenceGraph.cpp:1.25 Wed Jul 27 00:53:44 2005 +++ llvm/lib/Target/SparcV9/RegAlloc/InterferenceGraph.cpp Wed Jul 27 01:12:34 2005 @@ -120,7 +120,7 @@ // return whether two live ranges interfere //---------------------------------------------------------------------------- unsigned InterferenceGraph::getInterference(const V9LiveRange *const LR1, - const V9LiveRange *const LR2) + const V9LiveRange *const LR2) const { assert(LR1 != LR2); assertIGNode(this, LR1->getUserIGNode()); Index: llvm/lib/Target/SparcV9/RegAlloc/PhyRegAlloc.cpp diff -u llvm/lib/Target/SparcV9/RegAlloc/PhyRegAlloc.cpp:1.170 llvm/lib/Target/SparcV9/RegAlloc/PhyRegAlloc.cpp:1.171 --- llvm/lib/Target/SparcV9/RegAlloc/PhyRegAlloc.cpp:1.170 Wed Jul 27 00:53:44 2005 +++ llvm/lib/Target/SparcV9/RegAlloc/PhyRegAlloc.cpp Wed Jul 27 01:12:34 2005 @@ -791,7 +791,7 @@ // if the value is in both LV sets (i.e., live before and after // the call machine instruction) unsigned Reg = MRI.getUnifiedRegNum(RCID, Color); - + // if we haven't already pushed this register... if( PushedRegSet.find(Reg) == PushedRegSet.end() ) { unsigned RegType = MRI.getRegTypeForLR(LR); @@ -861,7 +861,7 @@ if (AdIAft.size() > 0) instrnsAfter.insert(instrnsAfter.end(), AdIAft.begin(), AdIAft.end()); - + PushedRegSet.insert(Reg); if(DEBUG_RA) { @@ -872,7 +872,7 @@ std::cerr << " -and After:\n\t "; for_each(instrnsAfter.begin(), instrnsAfter.end(), std::mem_fun(&MachineInstr::dump)); - } + } } // if not already pushed } // if LR has a volatile color } // if LR has color From jeffc at jolt-lang.org Wed Jul 27 01:12:58 2005 From: jeffc at jolt-lang.org (Jeff Cohen) Date: Wed, 27 Jul 2005 01:12:58 -0500 Subject: [llvm-commits] CVS: llvm/lib/ExecutionEngine/JIT/JIT.cpp JITEmitter.cpp Message-ID: <200507270612.BAA32163@zion.cs.uiuc.edu> Changes in directory llvm/lib/ExecutionEngine/JIT: JIT.cpp updated: 1.56 -> 1.57 JITEmitter.cpp updated: 1.71 -> 1.72 --- Log message: Eliminate all remaining tabs and trailing spaces. --- Diffs of the changes: (+11 -11) JIT.cpp | 2 +- JITEmitter.cpp | 20 ++++++++++---------- 2 files changed, 11 insertions(+), 11 deletions(-) Index: llvm/lib/ExecutionEngine/JIT/JIT.cpp diff -u llvm/lib/ExecutionEngine/JIT/JIT.cpp:1.56 llvm/lib/ExecutionEngine/JIT/JIT.cpp:1.57 --- llvm/lib/ExecutionEngine/JIT/JIT.cpp:1.56 Tue Jul 12 10:51:55 2005 +++ llvm/lib/ExecutionEngine/JIT/JIT.cpp Wed Jul 27 01:12:33 2005 @@ -218,7 +218,7 @@ void JIT::runJITOnFunction(Function *F) { static bool isAlreadyCodeGenerating = false; assert(!isAlreadyCodeGenerating && "Error: Recursive compilation detected!"); - + MutexGuard locked(lock); // JIT the function Index: llvm/lib/ExecutionEngine/JIT/JITEmitter.cpp diff -u llvm/lib/ExecutionEngine/JIT/JITEmitter.cpp:1.71 llvm/lib/ExecutionEngine/JIT/JITEmitter.cpp:1.72 --- llvm/lib/ExecutionEngine/JIT/JITEmitter.cpp:1.71 Mon Jul 25 18:42:58 2005 +++ llvm/lib/ExecutionEngine/JIT/JITEmitter.cpp Wed Jul 27 01:12:33 2005 @@ -147,19 +147,19 @@ /// StubToFunctionMap - Keep track of the function that each stub /// corresponds to. std::map StubToFunctionMap; - + public: std::map& getFunctionToStubMap(const MutexGuard& locked) { assert(locked.holds(TheJIT->lock)); return FunctionToStubMap; } - + std::map& getStubToFunctionMap(const MutexGuard& locked) { assert(locked.holds(TheJIT->lock)); return StubToFunctionMap; } }; - + /// JITResolver - Keep track of, and resolve, call sites for functions that /// have not yet been compiled. class JITResolver { @@ -340,12 +340,12 @@ public: JITEmitter(JIT &jit) - :MemMgr(jit.getJITInfo().needsGOT()), + :MemMgr(jit.getJITInfo().needsGOT()), nextGOTIndex(0) { - TheJIT = &jit; - DEBUG(std::cerr << - (MemMgr.isManagingGOT() ? "JIT is managing GOT\n" + TheJIT = &jit; + DEBUG(std::cerr << + (MemMgr.isManagingGOT() ? "JIT is managing GOT\n" : "JIT is not managing GOT\n")); } @@ -431,14 +431,14 @@ // If the target REALLY wants a stub for this function, emit it now. if (!MR.doesntNeedFunctionStub()) ResultPtr = getJITResolver(this).getExternalFunctionStub(ResultPtr); - } else if (MR.isGlobalValue()) + } else if (MR.isGlobalValue()) ResultPtr = getPointerToGlobal(MR.getGlobalValue(), CurBlock+MR.getMachineCodeOffset(), MR.doesntNeedFunctionStub()); else //ConstantPoolIndex - ResultPtr = + ResultPtr = (void*)(intptr_t)getConstantPoolEntryAddress(MR.getConstantPoolIndex()); - + MR.setResultPointer(ResultPtr); // if we are managing the got, check to see if this pointer has all ready From jeffc at jolt-lang.org Wed Jul 27 01:12:58 2005 From: jeffc at jolt-lang.org (Jeff Cohen) Date: Wed, 27 Jul 2005 01:12:58 -0500 Subject: [llvm-commits] CVS: llvm/tools/bugpoint/ExecutionDriver.cpp Miscompilation.cpp Message-ID: <200507270612.BAA32175@zion.cs.uiuc.edu> Changes in directory llvm/tools/bugpoint: ExecutionDriver.cpp updated: 1.56 -> 1.57 Miscompilation.cpp updated: 1.68 -> 1.69 --- Log message: Eliminate all remaining tabs and trailing spaces. --- Diffs of the changes: (+7 -7) ExecutionDriver.cpp | 2 +- Miscompilation.cpp | 12 ++++++------ 2 files changed, 7 insertions(+), 7 deletions(-) Index: llvm/tools/bugpoint/ExecutionDriver.cpp diff -u llvm/tools/bugpoint/ExecutionDriver.cpp:1.56 llvm/tools/bugpoint/ExecutionDriver.cpp:1.57 --- llvm/tools/bugpoint/ExecutionDriver.cpp:1.56 Thu Jul 7 22:08:58 2005 +++ llvm/tools/bugpoint/ExecutionDriver.cpp Wed Jul 27 01:12:34 2005 @@ -324,7 +324,7 @@ Output.eraseFromDisk(); // Remove the bytecode file if we are supposed to. - if (RemoveBytecode) + if (RemoveBytecode) sys::Path(BytecodeFile).eraseFromDisk(); return FilesDifferent; } Index: llvm/tools/bugpoint/Miscompilation.cpp diff -u llvm/tools/bugpoint/Miscompilation.cpp:1.68 llvm/tools/bugpoint/Miscompilation.cpp:1.69 --- llvm/tools/bugpoint/Miscompilation.cpp:1.68 Mon Jul 11 20:00:32 2005 +++ llvm/tools/bugpoint/Miscompilation.cpp Wed Jul 27 01:12:34 2005 @@ -692,7 +692,7 @@ GlobalVariable *Cache = new GlobalVariable(F->getType(), false,GlobalValue::InternalLinkage, NullPtr,F->getName()+".fpcache", F->getParent()); - + // Construct a new stub function that will re-route calls to F const FunctionType *FuncTy = F->getFunctionType(); Function *FuncWrapper = new Function(FuncTy, @@ -702,13 +702,13 @@ BasicBlock *EntryBB = new BasicBlock("entry", FuncWrapper); BasicBlock *DoCallBB = new BasicBlock("usecache", FuncWrapper); BasicBlock *LookupBB = new BasicBlock("lookupfp", FuncWrapper); - + // Check to see if we already looked up the value. Value *CachedVal = new LoadInst(Cache, "fpcache", EntryBB); Value *IsNull = new SetCondInst(Instruction::SetEQ, CachedVal, NullPtr, "isNull", EntryBB); new BranchInst(LookupBB, DoCallBB, IsNull, EntryBB); - + // Resolve the call to function F via the JIT API: // // call resolver(GetElementPtr...) @@ -721,11 +721,11 @@ // Save the value in our cache. new StoreInst(CastedResolver, Cache, LookupBB); new BranchInst(DoCallBB, LookupBB); - + PHINode *FuncPtr = new PHINode(NullPtr->getType(), "fp", DoCallBB); FuncPtr->addIncoming(CastedResolver, LookupBB); FuncPtr->addIncoming(CachedVal, EntryBB); - + // Save the argument list. std::vector Args; for (Function::arg_iterator i = FuncWrapper->arg_begin(), @@ -740,7 +740,7 @@ CallInst *Call = new CallInst(FuncPtr, Args, "retval", DoCallBB); new ReturnInst(Call, DoCallBB); } - + // Use the wrapper function instead of the old function F->replaceAllUsesWith(FuncWrapper); } From jeffc at jolt-lang.org Wed Jul 27 01:12:58 2005 From: jeffc at jolt-lang.org (Jeff Cohen) Date: Wed, 27 Jul 2005 01:12:58 -0500 Subject: [llvm-commits] CVS: llvm/lib/Target/SparcV8/FPMover.cpp SparcV8ISelPattern.cpp Message-ID: <200507270612.BAA32199@zion.cs.uiuc.edu> Changes in directory llvm/lib/Target/SparcV8: FPMover.cpp updated: 1.5 -> 1.6 SparcV8ISelPattern.cpp updated: 1.4 -> 1.5 --- Log message: Eliminate all remaining tabs and trailing spaces. --- Diffs of the changes: (+19 -19) FPMover.cpp | 20 ++++++++++---------- SparcV8ISelPattern.cpp | 18 +++++++++--------- 2 files changed, 19 insertions(+), 19 deletions(-) Index: llvm/lib/Target/SparcV8/FPMover.cpp diff -u llvm/lib/Target/SparcV8/FPMover.cpp:1.5 llvm/lib/Target/SparcV8/FPMover.cpp:1.6 --- llvm/lib/Target/SparcV8/FPMover.cpp:1.5 Wed May 18 15:37:33 2005 +++ llvm/lib/Target/SparcV8/FPMover.cpp Wed Jul 27 01:12:33 2005 @@ -53,19 +53,19 @@ return new FPMover (tm); } -static void doubleToSingleRegPair(unsigned doubleReg, unsigned &singleReg1, +static void doubleToSingleRegPair(unsigned doubleReg, unsigned &singleReg1, unsigned &singleReg2) { - const unsigned EvenHalvesOfPairs[] = { - V8::F0, V8::F2, V8::F4, V8::F6, V8::F8, V8::F10, V8::F12, V8::F14, - V8::F16, V8::F18, V8::F20, V8::F22, V8::F24, V8::F26, V8::F28, V8::F30 + const unsigned EvenHalvesOfPairs[] = { + V8::F0, V8::F2, V8::F4, V8::F6, V8::F8, V8::F10, V8::F12, V8::F14, + V8::F16, V8::F18, V8::F20, V8::F22, V8::F24, V8::F26, V8::F28, V8::F30 }; - const unsigned OddHalvesOfPairs[] = { - V8::F1, V8::F3, V8::F5, V8::F7, V8::F9, V8::F11, V8::F13, V8::F15, - V8::F17, V8::F19, V8::F21, V8::F23, V8::F25, V8::F27, V8::F29, V8::F31 + const unsigned OddHalvesOfPairs[] = { + V8::F1, V8::F3, V8::F5, V8::F7, V8::F9, V8::F11, V8::F13, V8::F15, + V8::F17, V8::F19, V8::F21, V8::F23, V8::F25, V8::F27, V8::F29, V8::F31 }; - const unsigned DoubleRegsInOrder[] = { - V8::D0, V8::D1, V8::D2, V8::D3, V8::D4, V8::D5, V8::D6, V8::D7, V8::D8, - V8::D9, V8::D10, V8::D11, V8::D12, V8::D13, V8::D14, V8::D15 + const unsigned DoubleRegsInOrder[] = { + V8::D0, V8::D1, V8::D2, V8::D3, V8::D4, V8::D5, V8::D6, V8::D7, V8::D8, + V8::D9, V8::D10, V8::D11, V8::D12, V8::D13, V8::D14, V8::D15 }; for (unsigned i = 0; i < sizeof(DoubleRegsInOrder)/sizeof(unsigned); ++i) if (DoubleRegsInOrder[i] == doubleReg) { Index: llvm/lib/Target/SparcV8/SparcV8ISelPattern.cpp diff -u llvm/lib/Target/SparcV8/SparcV8ISelPattern.cpp:1.4 llvm/lib/Target/SparcV8/SparcV8ISelPattern.cpp:1.5 --- llvm/lib/Target/SparcV8/SparcV8ISelPattern.cpp:1.4 Sat Jul 9 20:56:13 2005 +++ llvm/lib/Target/SparcV8/SparcV8ISelPattern.cpp Wed Jul 27 01:12:33 2005 @@ -119,7 +119,7 @@ std::vector V8TargetLowering::LowerArguments(Function &F, SelectionDAG &DAG) { - static const unsigned IncomingArgRegs[] = + static const unsigned IncomingArgRegs[] = { V8::I0, V8::I1, V8::I2, V8::I3, V8::I4, V8::I5 }; std::vector ArgValues; @@ -154,8 +154,8 @@ case MVT::i8: case MVT::i16: case MVT::i32: - argt = DAG.getCopyFromReg(AddLiveIn(MF, IncomingArgRegs[ArgNo], - getRegClassFor(MVT::i32)), + argt = DAG.getCopyFromReg(AddLiveIn(MF, IncomingArgRegs[ArgNo], + getRegClassFor(MVT::i32)), VT, DAG.getRoot()); if (VT != MVT::i32) argt = DAG.getNode(ISD::TRUNCATE, VT, argt); @@ -198,7 +198,7 @@ V8TargetLowering::LowerCallTo(SDOperand Chain, const Type *RetTy, bool isVarArg, unsigned CallingConv, bool isTailCall, - SDOperand Callee, ArgListTy &Args, + SDOperand Callee, ArgListTy &Args, SelectionDAG &DAG) { //FIXME return std::make_pair(Chain, Chain); @@ -243,7 +243,7 @@ // Clear state used for selection. ExprMap.clear(); } - + virtual void EmitFunctionEntryCode(Function &Fn, MachineFunction &MF); unsigned SelectExpr(SDOperand N); @@ -347,7 +347,7 @@ case MVT::f64: Opc = V8::LDFSRrr; case MVT::f32: Opc = V8::LDDFrr; default: - Node->dump(); + Node->dump(); assert(0 && "Bad type!"); break; } @@ -374,7 +374,7 @@ SDOperand Chain = N.getOperand(0); Select(Chain); unsigned r = dyn_cast(Node)->getReg(); - + BuildMI(BB, V8::ORrr, 2, Result).addReg(r).addReg(V8::G0); return Result; } @@ -411,7 +411,7 @@ Tmp2 = SelectExpr(N.getOperand(1)); BuildMI(BB, Opc, 2, Result).addReg(Tmp1).addReg(Tmp2); return Result; - + } return 0; } @@ -488,7 +488,7 @@ Tmp1 = SelectExpr(Value); Tmp2 = SelectExpr(Address); - unsigned VT = opcode == ISD::STORE ? + unsigned VT = opcode == ISD::STORE ? Value.getValueType() : cast(Node->getOperand(4))->getVT(); switch(VT) { default: assert(0 && "unknown Type in store"); From jeffc at jolt-lang.org Wed Jul 27 01:12:58 2005 From: jeffc at jolt-lang.org (Jeff Cohen) Date: Wed, 27 Jul 2005 01:12:58 -0500 Subject: [llvm-commits] CVS: llvm/tools/llvmc/CompilerDriver.cpp llvmc.cpp Message-ID: <200507270612.BAA32235@zion.cs.uiuc.edu> Changes in directory llvm/tools/llvmc: CompilerDriver.cpp updated: 1.34 -> 1.35 llvmc.cpp updated: 1.27 -> 1.28 --- Log message: Eliminate all remaining tabs and trailing spaces. --- Diffs of the changes: (+2 -2) CompilerDriver.cpp | 2 +- llvmc.cpp | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) Index: llvm/tools/llvmc/CompilerDriver.cpp diff -u llvm/tools/llvmc/CompilerDriver.cpp:1.34 llvm/tools/llvmc/CompilerDriver.cpp:1.35 --- llvm/tools/llvmc/CompilerDriver.cpp:1.34 Thu Jul 7 22:08:58 2005 +++ llvm/tools/llvmc/CompilerDriver.cpp Wed Jul 27 01:12:34 2005 @@ -302,7 +302,7 @@ tmp.replace(0,9,LLVMGXX); else if (*PI == "%llvmcc1%") tmp.replace(0,9,LLVMCC1); - else if (*PI == "%llvmcc1plus%") + else if (*PI == "%llvmcc1plus%") tmp.replace(0,9,LLVMCC1); else found = false; Index: llvm/tools/llvmc/llvmc.cpp diff -u llvm/tools/llvmc/llvmc.cpp:1.27 llvm/tools/llvmc/llvmc.cpp:1.28 --- llvm/tools/llvmc/llvmc.cpp:1.27 Thu May 5 17:38:21 2005 +++ llvm/tools/llvmc/llvmc.cpp Wed Jul 27 01:12:34 2005 @@ -343,7 +343,7 @@ if (filePos != 0 && (libPos == 0 || filePos < libPos)) { // Add a source file - InpList.push_back(std::make_pair(*fileIt, + InpList.push_back(std::make_pair(*fileIt, GetFileType(*fileIt, filePos))); ++fileIt; } else if ( libPos != 0 && (filePos == 0 || libPos < filePos) ) { From jeffc at jolt-lang.org Wed Jul 27 01:12:58 2005 From: jeffc at jolt-lang.org (Jeff Cohen) Date: Wed, 27 Jul 2005 01:12:58 -0500 Subject: [llvm-commits] CVS: llvm/lib/Transforms/Utils/CloneModule.cpp InlineFunction.cpp Local.cpp PromoteMemoryToRegister.cpp Message-ID: <200507270612.BAA32267@zion.cs.uiuc.edu> Changes in directory llvm/lib/Transforms/Utils: CloneModule.cpp updated: 1.13 -> 1.14 InlineFunction.cpp updated: 1.34 -> 1.35 Local.cpp updated: 1.40 -> 1.41 PromoteMemoryToRegister.cpp updated: 1.77 -> 1.78 --- Log message: Eliminate all remaining tabs and trailing spaces. --- Diffs of the changes: (+6 -6) CloneModule.cpp | 2 +- InlineFunction.cpp | 2 +- Local.cpp | 6 +++--- PromoteMemoryToRegister.cpp | 2 +- 4 files changed, 6 insertions(+), 6 deletions(-) Index: llvm/lib/Transforms/Utils/CloneModule.cpp diff -u llvm/lib/Transforms/Utils/CloneModule.cpp:1.13 llvm/lib/Transforms/Utils/CloneModule.cpp:1.14 --- llvm/lib/Transforms/Utils/CloneModule.cpp:1.13 Sun May 8 20:04:34 2005 +++ llvm/lib/Transforms/Utils/CloneModule.cpp Wed Jul 27 01:12:34 2005 @@ -55,7 +55,7 @@ // Loop over the functions in the module, making external functions as before for (Module::const_iterator I = M->begin(), E = M->end(); I != E; ++I) { - Function *NF = + Function *NF = new Function(cast(I->getType()->getElementType()), GlobalValue::ExternalLinkage, I->getName(), New); NF->setCallingConv(I->getCallingConv()); Index: llvm/lib/Transforms/Utils/InlineFunction.cpp diff -u llvm/lib/Transforms/Utils/InlineFunction.cpp:1.34 llvm/lib/Transforms/Utils/InlineFunction.cpp:1.35 --- llvm/lib/Transforms/Utils/InlineFunction.cpp:1.34 Sun May 8 20:04:34 2005 +++ llvm/lib/Transforms/Utils/InlineFunction.cpp Wed Jul 27 01:12:34 2005 @@ -107,7 +107,7 @@ } } - // If we are inlining tail call instruction through an invoke or + // If we are inlining tail call instruction through an invoke or if (MustClearTailCallFlags) { for (Function::iterator BB = FirstNewBlock, E = Caller->end(); BB != E; ++BB) Index: llvm/lib/Transforms/Utils/Local.cpp diff -u llvm/lib/Transforms/Utils/Local.cpp:1.40 llvm/lib/Transforms/Utils/Local.cpp:1.41 --- llvm/lib/Transforms/Utils/Local.cpp:1.40 Sun Jun 19 09:41:20 2005 +++ llvm/lib/Transforms/Utils/Local.cpp Wed Jul 27 01:12:34 2005 @@ -245,10 +245,10 @@ switch (Name[0]) { case 'a': - return Name == "acos" || Name == "asin" || Name == "atan" || + return Name == "acos" || Name == "asin" || Name == "atan" || Name == "atan2"; case 'c': - return Name == "ceil" || Name == "cos" || Name == "cosf" || + return Name == "ceil" || Name == "cos" || Name == "cosf" || Name == "cosh"; case 'e': return Name == "exp"; @@ -374,7 +374,7 @@ bool llvm::isInstructionTriviallyDead(Instruction *I) { if (!I->use_empty() || isa(I)) return false; - + if (!I->mayWriteToMemory()) return true; if (CallInst *CI = dyn_cast(I)) Index: llvm/lib/Transforms/Utils/PromoteMemoryToRegister.cpp diff -u llvm/lib/Transforms/Utils/PromoteMemoryToRegister.cpp:1.77 llvm/lib/Transforms/Utils/PromoteMemoryToRegister.cpp:1.78 --- llvm/lib/Transforms/Utils/PromoteMemoryToRegister.cpp:1.77 Thu Jun 30 02:29:44 2005 +++ llvm/lib/Transforms/Utils/PromoteMemoryToRegister.cpp Wed Jul 27 01:12:34 2005 @@ -665,7 +665,7 @@ // undef into the alloca right after the alloca itself. for (unsigned i = 0, e = RetryList.size(); i != e; ++i) { BasicBlock::iterator BBI = RetryList[i]; - + new StoreInst(UndefValue::get(RetryList[i]->getAllocatedType()), RetryList[i], ++BBI); } From jeffc at jolt-lang.org Wed Jul 27 01:12:58 2005 From: jeffc at jolt-lang.org (Jeff Cohen) Date: Wed, 27 Jul 2005 01:12:58 -0500 Subject: [llvm-commits] CVS: llvm/lib/Target/SparcV9/LiveVar/BBLiveVar.cpp Message-ID: <200507270612.BAA32239@zion.cs.uiuc.edu> Changes in directory llvm/lib/Target/SparcV9/LiveVar: BBLiveVar.cpp updated: 1.50 -> 1.51 --- Log message: Eliminate all remaining tabs and trailing spaces. --- Diffs of the changes: (+3 -3) BBLiveVar.cpp | 6 +++--- 1 files changed, 3 insertions(+), 3 deletions(-) Index: llvm/lib/Target/SparcV9/LiveVar/BBLiveVar.cpp diff -u llvm/lib/Target/SparcV9/LiveVar/BBLiveVar.cpp:1.50 llvm/lib/Target/SparcV9/LiveVar/BBLiveVar.cpp:1.51 --- llvm/lib/Target/SparcV9/LiveVar/BBLiveVar.cpp:1.50 Wed Jul 27 00:53:43 2005 +++ llvm/lib/Target/SparcV9/LiveVar/BBLiveVar.cpp Wed Jul 27 01:12:34 2005 @@ -82,9 +82,9 @@ if (MI->getOpcode() == V9::PHI) { // for a phi node const Value *ArgVal = Op; const BasicBlock *PredBB = cast(*++OpI); // next ptr is BB - + PredToEdgeInSetMap[PredBB].insert(ArgVal); - + if (DEBUG_LV >= LV_DEBUG_Verbose) std::cerr << " - phi operand " << RAV(ArgVal) << " came from BB " << RAV(PredBB) << "\n"; @@ -111,7 +111,7 @@ } - + //----------------------------------------------------------------------------- // To add an operand which is a def //----------------------------------------------------------------------------- From jeffc at jolt-lang.org Wed Jul 27 01:12:58 2005 From: jeffc at jolt-lang.org (Jeff Cohen) Date: Wed, 27 Jul 2005 01:12:58 -0500 Subject: [llvm-commits] CVS: llvm/lib/Target/SparcV9/SparcV9BurgISel.cpp SparcV9RegInfo.cpp SparcV9TmpInstr.cpp Message-ID: <200507270612.BAA32220@zion.cs.uiuc.edu> Changes in directory llvm/lib/Target/SparcV9: SparcV9BurgISel.cpp updated: 1.23 -> 1.24 SparcV9RegInfo.cpp updated: 1.142 -> 1.143 SparcV9TmpInstr.cpp updated: 1.6 -> 1.7 --- Log message: Eliminate all remaining tabs and trailing spaces. --- Diffs of the changes: (+7 -7) SparcV9BurgISel.cpp | 10 +++++----- SparcV9RegInfo.cpp | 2 +- SparcV9TmpInstr.cpp | 2 +- 3 files changed, 7 insertions(+), 7 deletions(-) Index: llvm/lib/Target/SparcV9/SparcV9BurgISel.cpp diff -u llvm/lib/Target/SparcV9/SparcV9BurgISel.cpp:1.23 llvm/lib/Target/SparcV9/SparcV9BurgISel.cpp:1.24 --- llvm/lib/Target/SparcV9/SparcV9BurgISel.cpp:1.23 Wed Jul 27 00:53:43 2005 +++ llvm/lib/Target/SparcV9/SparcV9BurgISel.cpp Wed Jul 27 01:12:33 2005 @@ -11,7 +11,7 @@ // construct a forest of BURG instruction trees (class InstrForest) and then // uses the BURG-generated tree grammar (BURM) to find the optimal instruction // sequences for the SparcV9. -// +// //===----------------------------------------------------------------------===// #include "MachineInstrAnnot.h" @@ -2339,7 +2339,7 @@ CreateShiftInstructions(target, F, opCode, lval, NULL, pow, tmpNeg, mvec, mcfi); } - + } if (mvec.size() > 0 && needNeg) { @@ -2883,9 +2883,9 @@ case Intrinsic::vacopy: { MachineCodeForInstruction& m1 = MachineCodeForInstruction::get(&callInstr); - TmpInstruction* VReg = + TmpInstruction* VReg = new TmpInstruction(m1, callInstr.getOperand(1)->getType()); - + // Simple store of current va_list (arg2) to new va_list (arg1) mvec.push_back(BuildMI(V9::LDXi, 3). addReg(callInstr.getOperand(2)).addSImm(0).addRegDef(VReg)); @@ -2926,7 +2926,7 @@ default: break; } - return false; + return false; } /// GetInstructionsByRule - Choose machine instructions for the Index: llvm/lib/Target/SparcV9/SparcV9RegInfo.cpp diff -u llvm/lib/Target/SparcV9/SparcV9RegInfo.cpp:1.142 llvm/lib/Target/SparcV9/SparcV9RegInfo.cpp:1.143 --- llvm/lib/Target/SparcV9/SparcV9RegInfo.cpp:1.142 Wed Jul 27 00:53:43 2005 +++ llvm/lib/Target/SparcV9/SparcV9RegInfo.cpp Wed Jul 27 01:12:33 2005 @@ -474,7 +474,7 @@ cpMem2RegMI(InstrnsBefore, getFramePointer(), TmpOff, UniLRReg, regType); } - else { + else { cpReg2RegMI(InstrnsBefore, UniArgReg, UniLRReg, regType); } } Index: llvm/lib/Target/SparcV9/SparcV9TmpInstr.cpp diff -u llvm/lib/Target/SparcV9/SparcV9TmpInstr.cpp:1.6 llvm/lib/Target/SparcV9/SparcV9TmpInstr.cpp:1.7 --- llvm/lib/Target/SparcV9/SparcV9TmpInstr.cpp:1.6 Wed Jul 27 00:53:43 2005 +++ llvm/lib/Target/SparcV9/SparcV9TmpInstr.cpp Wed Jul 27 01:12:33 2005 @@ -9,7 +9,7 @@ // // Methods of class for temporary intermediate values used within the current // SparcV9 backend. -// +// //===----------------------------------------------------------------------===// #include "SparcV9TmpInstr.h" From jeffc at jolt-lang.org Wed Jul 27 01:12:57 2005 From: jeffc at jolt-lang.org (Jeff Cohen) Date: Wed, 27 Jul 2005 01:12:57 -0500 Subject: [llvm-commits] CVS: llvm/lib/VMCore/Type.cpp Message-ID: <200507270612.BAA32117@zion.cs.uiuc.edu> Changes in directory llvm/lib/VMCore: Type.cpp updated: 1.128 -> 1.129 --- Log message: Eliminate all remaining tabs and trailing spaces. --- Diffs of the changes: (+3 -3) Type.cpp | 6 +++--- 1 files changed, 3 insertions(+), 3 deletions(-) Index: llvm/lib/VMCore/Type.cpp diff -u llvm/lib/VMCore/Type.cpp:1.128 llvm/lib/VMCore/Type.cpp:1.129 --- llvm/lib/VMCore/Type.cpp:1.128 Wed Apr 27 13:57:15 2005 +++ llvm/lib/VMCore/Type.cpp Wed Jul 27 01:12:34 2005 @@ -143,8 +143,8 @@ case Type::UByteTyID: return 1; case Type::UShortTyID: case Type::ShortTyID: return 2; - case Type::FloatTyID: - case Type::IntTyID: + case Type::FloatTyID: + case Type::IntTyID: case Type::UIntTyID: return 4; case Type::LongTyID: case Type::ULongTyID: @@ -160,7 +160,7 @@ case Type::UByteTyID: return 8; case Type::UShortTyID: case Type::ShortTyID: return 16; - case Type::FloatTyID: + case Type::FloatTyID: case Type::IntTyID: case Type::UIntTyID: return 32; case Type::LongTyID: From jeffc at jolt-lang.org Wed Jul 27 01:12:58 2005 From: jeffc at jolt-lang.org (Jeff Cohen) Date: Wed, 27 Jul 2005 01:12:58 -0500 Subject: [llvm-commits] CVS: llvm/utils/TableGen/AsmWriterEmitter.cpp Message-ID: <200507270612.BAA32223@zion.cs.uiuc.edu> Changes in directory llvm/utils/TableGen: AsmWriterEmitter.cpp updated: 1.21 -> 1.22 --- Log message: Eliminate all remaining tabs and trailing spaces. --- Diffs of the changes: (+4 -4) AsmWriterEmitter.cpp | 8 ++++---- 1 files changed, 4 insertions(+), 4 deletions(-) Index: llvm/utils/TableGen/AsmWriterEmitter.cpp diff -u llvm/utils/TableGen/AsmWriterEmitter.cpp:1.21 llvm/utils/TableGen/AsmWriterEmitter.cpp:1.22 --- llvm/utils/TableGen/AsmWriterEmitter.cpp:1.21 Fri Jul 15 17:43:04 2005 +++ llvm/utils/TableGen/AsmWriterEmitter.cpp Wed Jul 27 01:12:35 2005 @@ -116,7 +116,7 @@ LastEmitted = DollarPos; } else if (AsmString[DollarPos] == '{') { if (inVariant) - throw "Nested variants found for instruction '" + + throw "Nested variants found for instruction '" + CGI.TheDef->getName() + "'!"; LastEmitted = DollarPos+1; inVariant = true; // We are now inside of the variant! @@ -127,7 +127,7 @@ std::string::size_type NP = AsmString.find_first_of("|}", LastEmitted); if (NP == std::string::npos) - throw "Incomplete variant for instruction '" + + throw "Incomplete variant for instruction '" + CGI.TheDef->getName() + "'!"; LastEmitted = NP+1; if (AsmString[NP] == '}') { @@ -142,7 +142,7 @@ // Move to the end of variant list. std::string::size_type NP = AsmString.find('}', LastEmitted); if (NP == std::string::npos) - throw "Incomplete variant for instruction '" + + throw "Incomplete variant for instruction '" + CGI.TheDef->getName() + "'!"; LastEmitted = NP+1; inVariant = false; @@ -188,7 +188,7 @@ ++VarEnd; } if (VarName.empty()) - throw "Stray '$' in '" + CGI.TheDef->getName() + + throw "Stray '$' in '" + CGI.TheDef->getName() + "' asm string, maybe you want $$?"; unsigned OpNo = CGI.getOperandNamed(VarName); From jeffc at jolt-lang.org Wed Jul 27 01:12:58 2005 From: jeffc at jolt-lang.org (Jeff Cohen) Date: Wed, 27 Jul 2005 01:12:58 -0500 Subject: [llvm-commits] CVS: llvm/lib/Bytecode/Reader/Reader.cpp ReaderWrappers.cpp Message-ID: <200507270612.BAA32151@zion.cs.uiuc.edu> Changes in directory llvm/lib/Bytecode/Reader: Reader.cpp updated: 1.164 -> 1.165 ReaderWrappers.cpp updated: 1.50 -> 1.51 --- Log message: Eliminate all remaining tabs and trailing spaces. --- Diffs of the changes: (+12 -12) Reader.cpp | 4 ++-- ReaderWrappers.cpp | 20 ++++++++++---------- 2 files changed, 12 insertions(+), 12 deletions(-) Index: llvm/lib/Bytecode/Reader/Reader.cpp diff -u llvm/lib/Bytecode/Reader/Reader.cpp:1.164 llvm/lib/Bytecode/Reader/Reader.cpp:1.165 --- llvm/lib/Bytecode/Reader/Reader.cpp:1.164 Sat Jun 18 13:34:51 2005 +++ llvm/lib/Bytecode/Reader/Reader.cpp Wed Jul 27 01:12:33 2005 @@ -682,9 +682,9 @@ const Type* ArgTy = getValue(iType, Oprnds[0])->getType(); Function* NF = TheModule->getOrInsertFunction("llvm.va_copy", ArgTy, ArgTy, 0); - //b = vaarg a, t -> + //b = vaarg a, t -> //foo = alloca 1 of t - //bar = vacopy a + //bar = vacopy a //store bar -> foo //b = vaarg foo, t AllocaInst* foo = new AllocaInst(ArgTy, 0, "vaarg.fix"); Index: llvm/lib/Bytecode/Reader/ReaderWrappers.cpp diff -u llvm/lib/Bytecode/Reader/ReaderWrappers.cpp:1.50 llvm/lib/Bytecode/Reader/ReaderWrappers.cpp:1.51 --- llvm/lib/Bytecode/Reader/ReaderWrappers.cpp:1.50 Wed Jun 22 16:04:42 2005 +++ llvm/lib/Bytecode/Reader/ReaderWrappers.cpp Wed Jul 27 01:12:33 2005 @@ -170,17 +170,17 @@ if(Function* F = M->getNamedFunction("llvm.va_start")) { assert(F->arg_size() == 0 && "Obsolete va_start takes 0 argument!"); - + //foo = va_start() // -> //bar = alloca typeof(foo) //va_start(bar) //foo = load bar - + const Type* RetTy = Type::getPrimitiveType(Type::VoidTyID); const Type* ArgTy = F->getFunctionType()->getReturnType(); const Type* ArgTyPtr = PointerType::get(ArgTy); - Function* NF = M->getOrInsertFunction("llvm.va_start", + Function* NF = M->getOrInsertFunction("llvm.va_start", RetTy, ArgTyPtr, 0); for(Value::use_iterator I = F->use_begin(), E = F->use_end(); I != E;) @@ -193,7 +193,7 @@ } F->setName(""); } - + if(Function* F = M->getNamedFunction("llvm.va_end")) { assert(F->arg_size() == 1 && "Obsolete va_end takes 1 argument!"); //vaend foo @@ -203,9 +203,9 @@ const Type* RetTy = Type::getPrimitiveType(Type::VoidTyID); const Type* ArgTy = F->getFunctionType()->getParamType(0); const Type* ArgTyPtr = PointerType::get(ArgTy); - Function* NF = M->getOrInsertFunction("llvm.va_end", + Function* NF = M->getOrInsertFunction("llvm.va_end", RetTy, ArgTyPtr, 0); - + for(Value::use_iterator I = F->use_begin(), E = F->use_end(); I != E;) if (CallInst* CI = dyn_cast(*I++)) { AllocaInst* bar = new AllocaInst(ArgTy, 0, "vaend.fix.1", CI); @@ -215,7 +215,7 @@ } F->setName(""); } - + if(Function* F = M->getNamedFunction("llvm.va_copy")) { assert(F->arg_size() == 1 && "Obsolete va_copy takes 1 argument!"); //foo = vacopy(bar) @@ -225,13 +225,13 @@ //store bar -> b //vacopy(a, b) //foo = load a - + const Type* RetTy = Type::getPrimitiveType(Type::VoidTyID); const Type* ArgTy = F->getFunctionType()->getReturnType(); const Type* ArgTyPtr = PointerType::get(ArgTy); - Function* NF = M->getOrInsertFunction("llvm.va_copy", + Function* NF = M->getOrInsertFunction("llvm.va_copy", RetTy, ArgTyPtr, ArgTyPtr, 0); - + for(Value::use_iterator I = F->use_begin(), E = F->use_end(); I != E;) if (CallInst* CI = dyn_cast(*I++)) { AllocaInst* a = new AllocaInst(ArgTy, 0, "vacopy.fix.1", CI); From lattner at persephone.cs.uiuc.edu Wed Jul 27 01:23:40 2005 From: lattner at persephone.cs.uiuc.edu (Chris Lattner) Date: Wed, 27 Jul 2005 01:23:40 -0500 (CDT) Subject: [llvm-commits] CVS: llvm-test/Makefile.programs Message-ID: <20050727062340.9BC4E12DBF65@persephone.cs.uiuc.edu> Changes in directory llvm-test: Makefile.programs updated: 1.157 -> 1.158 --- Log message: On darwin, pass a special flag to make the assembler happy with G5-specific instructions --- Diffs of the changes: (+6 -6) Makefile.programs | 12 ++++++------ 1 files changed, 6 insertions, 6 deletions Index: llvm-test/Makefile.programs diff -u llvm-test/Makefile.programs:1.157 llvm-test/Makefile.programs:1.158 --- llvm-test/Makefile.programs:1.157 Wed Jul 20 17:43:51 2005 +++ llvm-test/Makefile.programs Wed Jul 27 01:23:17 2005 @@ -285,20 +285,20 @@ Output/%.llc-beta.s: Output/%.llvm.bc $(LLC) -$(LLC) $(LLCFLAGS) -f $(LLCBETAOPTION) $< -o $@ +# On darwin, pass -force_cpusubtype_ALL to allow all ppc instructions. +ifeq ($(ARCH),PowerPC) +LLCASSEMBLERFLAGS = -force_cpusubtype_ALL +endif -## Alternative command to run llc remotely on another machine: -## This is very useful when debugging: -## -rsh psmith "cd `/bin/pwd`; llc $(LLCFLAGS) -f $< -o $@" - # Assemble (and link) an LLVM-linked program using the system assembler... # $(PROGRAMS_TO_TEST:%=Output/%.llc): \ Output/%.llc: Output/%.llc.s - -$(CC) $(CFLAGS) $< $(LLCLIBS) $(LDFLAGS) -o $@ + -$(CC) $(CFLAGS) $< $(LLCLIBS) $(LLCASSEMBLERFLAGS) $(LDFLAGS) -o $@ $(PROGRAMS_TO_TEST:%=Output/%.llc-beta): \ Output/%.llc-beta: Output/%.llc-beta.s - -$(CC) $(CFLAGS) $< $(LLCLIBS) $(LDFLAGS) -o $@ + -$(CC) $(CFLAGS) $< $(LLCLIBS) $(LLCASSEMBLERFLAGS) $(LDFLAGS) -o $@ # From jeffc at jolt-lang.org Wed Jul 27 01:12:58 2005 From: jeffc at jolt-lang.org (Jeff Cohen) Date: Wed, 27 Jul 2005 01:12:58 -0500 Subject: [llvm-commits] CVS: llvm/lib/Transforms/Scalar/InstructionCombining.cpp Reassociate.cpp TailRecursionElimination.cpp Message-ID: <200507270612.BAA32135@zion.cs.uiuc.edu> Changes in directory llvm/lib/Transforms/Scalar: InstructionCombining.cpp updated: 1.359 -> 1.360 Reassociate.cpp updated: 1.49 -> 1.50 TailRecursionElimination.cpp updated: 1.17 -> 1.18 --- Log message: Eliminate all remaining tabs and trailing spaces. --- Diffs of the changes: (+18 -18) InstructionCombining.cpp | 14 +++++++------- Reassociate.cpp | 20 ++++++++++---------- TailRecursionElimination.cpp | 2 +- 3 files changed, 18 insertions(+), 18 deletions(-) Index: llvm/lib/Transforms/Scalar/InstructionCombining.cpp diff -u llvm/lib/Transforms/Scalar/InstructionCombining.cpp:1.359 llvm/lib/Transforms/Scalar/InstructionCombining.cpp:1.360 --- llvm/lib/Transforms/Scalar/InstructionCombining.cpp:1.359 Wed Jul 20 13:49:28 2005 +++ llvm/lib/Transforms/Scalar/InstructionCombining.cpp Wed Jul 27 01:12:34 2005 @@ -1319,7 +1319,7 @@ static bool MaskedValueIsZero(Value *V, ConstantIntegral *Mask) { // Note, we cannot consider 'undef' to be "IsZero" here. The problem is that // we cannot optimize based on the assumption that it is zero without changing - // to to an explicit zero. If we don't change it to zero, other code could + // to to an explicit zero. If we don't change it to zero, other code could // optimized based on the contradictory assumption that it is non-zero. // Because instcombine aggressively folds operations with undef args anyway, // this won't lose us code quality. @@ -2308,7 +2308,7 @@ // compare the base pointer. if (PtrBase != GEPRHS->getOperand(0)) { bool IndicesTheSame = GEPLHS->getNumOperands()==GEPRHS->getNumOperands(); - IndicesTheSame &= GEPLHS->getOperand(0)->getType() == + IndicesTheSame &= GEPLHS->getOperand(0)->getType() == GEPRHS->getOperand(0)->getType(); if (IndicesTheSame) for (unsigned i = 1, e = GEPLHS->getNumOperands(); i != e; ++i) @@ -3103,7 +3103,7 @@ } } - // Finally, return the value computed. + // Finally, return the value computed. if (SCI.getOpcode() == Instruction::SetLT) { return ReplaceInstUsesWith(SCI, Result); } else { @@ -3167,7 +3167,7 @@ return new CastInst(V, I.getType()); } } - + if (ConstantUInt *CUI = dyn_cast(Op1)) { // shl uint X, 32 = 0 and shr ubyte Y, 9 = 0, ... just don't eliminate shr // of a signed value. @@ -3623,7 +3623,7 @@ if (ConstantInt *Op1C = dyn_cast(Op1)) { if (Op1C->getRawValue() == 0) { // If the input only has the low bit set, simplify directly. - Constant *Not1 = + Constant *Not1 = ConstantExpr::getNot(ConstantInt::get(Op0->getType(), 1)); // cast (X != 0) to int --> X if X&~1 == 0 if (MaskedValueIsZero(Op0, cast(Not1))) { @@ -3666,7 +3666,7 @@ if ((Op1C->getRawValue() & Op1C->getRawValue()-1) == 0) { // cast (X == 1) to int -> X iff X has only the low bit set. if (Op1C->getRawValue() == 1) { - Constant *Not1 = + Constant *Not1 = ConstantExpr::getNot(ConstantInt::get(Op0->getType(), 1)); if (MaskedValueIsZero(Op0, cast(Not1))) { if (CI.getType() == Op0->getType()) @@ -5247,7 +5247,7 @@ E = df_ext_end(&F.front(), Visited); BB != E; ++BB) for (BasicBlock::iterator I = BB->begin(), E = BB->end(); I != E; ++I) WorkList.push_back(I); - + // Do a quick scan over the function. If we find any blocks that are // unreachable, remove any instructions inside of them. This prevents // the instcombine code from having to deal with some bad special cases. Index: llvm/lib/Transforms/Scalar/Reassociate.cpp diff -u llvm/lib/Transforms/Scalar/Reassociate.cpp:1.49 llvm/lib/Transforms/Scalar/Reassociate.cpp:1.50 --- llvm/lib/Transforms/Scalar/Reassociate.cpp:1.49 Mon May 9 22:39:25 2005 +++ llvm/lib/Transforms/Scalar/Reassociate.cpp Wed Jul 27 01:12:34 2005 @@ -121,7 +121,7 @@ unsigned &CachedRank = ValueRankMap[I]; if (CachedRank) return CachedRank; // Rank already known? - + // If this is an expression, return the 1+MAX(rank(LHS), rank(RHS)) so that // we can reassociate expressions for code motion! Since we do not recurse // for PHI nodes, we cannot have infinite recursion here, because there @@ -130,7 +130,7 @@ for (unsigned i = 0, e = I->getNumOperands(); i != e && Rank != MaxRank; ++i) Rank = std::max(Rank, getRank(I->getOperand(i))); - + // If this is a not or neg instruction, do not count it for rank. This // assures us that X and ~X will have the same rank. if (!I->getType()->isIntegral() || @@ -139,7 +139,7 @@ //DEBUG(std::cerr << "Calculated Rank[" << V->getName() << "] = " //<< Rank << "\n"); - + return CachedRank = Rank; } @@ -176,7 +176,7 @@ void Reassociate::LinearizeExpr(BinaryOperator *I) { BinaryOperator *LHS = cast(I->getOperand(0)); BinaryOperator *RHS = cast(I->getOperand(1)); - assert(isReassociableOp(LHS, I->getOpcode()) && + assert(isReassociableOp(LHS, I->getOpcode()) && isReassociableOp(RHS, I->getOpcode()) && "Not an expression that needs linearization?"); @@ -190,7 +190,7 @@ I->setOperand(1, RHS->getOperand(0)); RHS->setOperand(0, LHS); I->setOperand(0, RHS); - + ++NumLinear; MadeChange = true; DEBUG(std::cerr << "Linearized: " << *I); @@ -363,7 +363,7 @@ // Everyone now refers to the add instruction. Sub->replaceAllUsesWith(New); Sub->eraseFromParent(); - + DEBUG(std::cerr << "Negated: " << *New); return New; } @@ -536,7 +536,7 @@ //case Instruction::Mul: } - if (IterateOptimization) + if (IterateOptimization) OptimizeExpression(Opcode, Ops); } @@ -590,13 +590,13 @@ // If this instruction is a commutative binary operator, process it. if (!BI->isAssociative()) continue; BinaryOperator *I = cast(BI); - + // If this is an interior node of a reassociable tree, ignore it until we // get to the root of the tree, to avoid N^2 analysis. if (I->hasOneUse() && isReassociableOp(I->use_back(), I->getOpcode())) continue; - // First, walk the expression tree, linearizing the tree, collecting + // First, walk the expression tree, linearizing the tree, collecting std::vector Ops; LinearizeExprTree(I, Ops); @@ -619,7 +619,7 @@ // this is a multiply tree used only by an add, and the immediate is a -1. // In this case we reassociate to put the negation on the outside so that we // can fold the negation into the add: (-X)*Y + Z -> Z-X*Y - if (I->getOpcode() == Instruction::Mul && I->hasOneUse() && + if (I->getOpcode() == Instruction::Mul && I->hasOneUse() && cast(I->use_back())->getOpcode() == Instruction::Add && isa(Ops.back().Op) && cast(Ops.back().Op)->isAllOnesValue()) { Index: llvm/lib/Transforms/Scalar/TailRecursionElimination.cpp diff -u llvm/lib/Transforms/Scalar/TailRecursionElimination.cpp:1.17 llvm/lib/Transforms/Scalar/TailRecursionElimination.cpp:1.18 --- llvm/lib/Transforms/Scalar/TailRecursionElimination.cpp:1.17 Mon May 9 18:51:13 2005 +++ llvm/lib/Transforms/Scalar/TailRecursionElimination.cpp Wed Jul 27 01:12:34 2005 @@ -117,7 +117,7 @@ for (Function::iterator BB = F.begin(), E = F.end(); BB != E; ++BB) { if (!FunctionContainsEscapingAllocas) FunctionContainsEscapingAllocas = CheckForEscapingAllocas(BB); - + if (ReturnInst *Ret = dyn_cast(BB->getTerminator())) MadeChange |= ProcessReturningBlock(Ret, OldEntry, ArgumentPHIs); } From jeffc at jolt-lang.org Wed Jul 27 01:12:58 2005 From: jeffc at jolt-lang.org (Jeff Cohen) Date: Wed, 27 Jul 2005 01:12:58 -0500 Subject: [llvm-commits] CVS: llvm/examples/ParallelJIT/ParallelJIT.cpp Message-ID: <200507270612.BAA32141@zion.cs.uiuc.edu> Changes in directory llvm/examples/ParallelJIT: ParallelJIT.cpp updated: 1.2 -> 1.3 --- Log message: Eliminate all remaining tabs and trailing spaces. --- Diffs of the changes: (+55 -55) ParallelJIT.cpp | 110 ++++++++++++++++++++++++++++---------------------------- 1 files changed, 55 insertions(+), 55 deletions(-) Index: llvm/examples/ParallelJIT/ParallelJIT.cpp diff -u llvm/examples/ParallelJIT/ParallelJIT.cpp:1.2 llvm/examples/ParallelJIT/ParallelJIT.cpp:1.3 --- llvm/examples/ParallelJIT/ParallelJIT.cpp:1.2 Wed Jul 13 18:20:24 2005 +++ llvm/examples/ParallelJIT/ParallelJIT.cpp Wed Jul 27 01:12:33 2005 @@ -9,7 +9,7 @@ // // Parallel JIT // -// This test program creates two LLVM functions then calls them from three +// This test program creates two LLVM functions then calls them from three // separate threads. It requires the pthreads library. // The three threads are created and then block waiting on a condition variable. // Once all threads are blocked on the conditional variable, the main thread @@ -28,32 +28,32 @@ #include using namespace llvm; -static Function* createAdd1( Module* M ) +static Function* createAdd1(Module* M) { // Create the add1 function entry and insert this entry into module M. The // function will have a return type of "int" and take an argument of "int". // The '0' terminates the list of argument types. Function *Add1F = M->getOrInsertFunction("add1", Type::IntTy, Type::IntTy, 0); - + // Add a basic block to the function. As before, it automatically inserts // because of the last argument. BasicBlock *BB = new BasicBlock("EntryBlock", Add1F); - + // Get pointers to the constant `1'. Value *One = ConstantSInt::get(Type::IntTy, 1); - + // Get pointers to the integer argument of the add1 function... assert(Add1F->arg_begin() != Add1F->arg_end()); // Make sure there's an arg Argument *ArgX = Add1F->arg_begin(); // Get the arg ArgX->setName("AnArg"); // Give it a nice symbolic name for fun. - + // Create the add instruction, inserting it into the end of BB. Instruction *Add = BinaryOperator::createAdd(One, ArgX, "addresult", BB); - + // Create the return instruction and add it to the basic block new ReturnInst(Add, BB); - - // Now, function add1 is ready. + + // Now, function add1 is ready. return Add1F; } @@ -62,45 +62,45 @@ // Create the fib function and insert it into module M. This function is said // to return an int and take an int parameter. Function *FibF = M->getOrInsertFunction("fib", Type::IntTy, Type::IntTy, 0); - + // Add a basic block to the function. BasicBlock *BB = new BasicBlock("EntryBlock", FibF); - + // Get pointers to the constants. Value *One = ConstantSInt::get(Type::IntTy, 1); Value *Two = ConstantSInt::get(Type::IntTy, 2); - + // Get pointer to the integer argument of the add1 function... Argument *ArgX = FibF->arg_begin(); // Get the arg. ArgX->setName("AnArg"); // Give it a nice symbolic name for fun. - + // Create the true_block. BasicBlock *RetBB = new BasicBlock("return", FibF); // Create an exit block. BasicBlock* RecurseBB = new BasicBlock("recurse", FibF); - + // Create the "if (arg < 2) goto exitbb" Value *CondInst = BinaryOperator::createSetLE(ArgX, Two, "cond", BB); new BranchInst(RetBB, RecurseBB, CondInst, BB); - + // Create: ret int 1 new ReturnInst(One, RetBB); - + // create fib(x-1) Value *Sub = BinaryOperator::createSub(ArgX, One, "arg", RecurseBB); Value *CallFibX1 = new CallInst(FibF, Sub, "fibx1", RecurseBB); - + // create fib(x-2) Sub = BinaryOperator::createSub(ArgX, Two, "arg", RecurseBB); Value *CallFibX2 = new CallInst(FibF, Sub, "fibx2", RecurseBB); - + // fib(x-1)+fib(x-2) - Value *Sum = + Value *Sum = BinaryOperator::createAdd(CallFibX1, CallFibX2, "addresult", RecurseBB); - + // Create the return instruction and add it to the basic block new ReturnInst(Sum, RecurseBB); - + return FibF; } @@ -120,23 +120,23 @@ { n = 0; waitFor = 0; - + int result = pthread_cond_init( &condition, NULL ); assert( result == 0 ); - + result = pthread_mutex_init( &mutex, NULL ); assert( result == 0 ); } - + ~WaitForThreads() { int result = pthread_cond_destroy( &condition ); assert( result == 0 ); - + result = pthread_mutex_destroy( &mutex ); assert( result == 0 ); } - + // All threads will stop here until another thread calls releaseThreads void block() { @@ -144,26 +144,26 @@ assert( result == 0 ); n ++; //~ std::cout << "block() n " << n << " waitFor " << waitFor << std::endl; - + assert( waitFor == 0 || n <= waitFor ); - if ( waitFor > 0 && n == waitFor ) + if ( waitFor > 0 && n == waitFor ) { // There are enough threads blocked that we can release all of them std::cout << "Unblocking threads from block()" << std::endl; unblockThreads(); - } - else + } + else { // We just need to wait until someone unblocks us result = pthread_cond_wait( &condition, &mutex ); assert( result == 0 ); } - + // unlock the mutex before returning result = pthread_mutex_unlock( &mutex ); assert( result == 0 ); } - + // If there are num or more threads blocked, it will signal them all // Otherwise, this thread blocks until there are enough OTHER threads // blocked @@ -171,22 +171,22 @@ { int result = pthread_mutex_lock( &mutex ); assert( result == 0 ); - + if ( n >= num ) { std::cout << "Unblocking threads from releaseThreads()" << std::endl; unblockThreads(); - } - else + } + else { waitFor = num; pthread_cond_wait( &condition, &mutex ); } - + // unlock the mutex before returning result = pthread_mutex_unlock( &mutex ); assert( result == 0 ); } - + private: void unblockThreads() { @@ -194,7 +194,7 @@ // enter while threads are exiting, they will block instead // of triggering a new release of threads n = 0; - + // Reset waitFor to zero: this way, if waitFor threads enter // while threads are exiting, they will block instead of // triggering a new release of threads @@ -203,7 +203,7 @@ int result = pthread_cond_broadcast( &condition ); assert( result == 0 ); } - + size_t n; size_t waitFor; pthread_cond_t condition; @@ -215,60 +215,60 @@ void* callFunc( void* param ) { struct threadParams* p = (struct threadParams*) param; - + // Call the `foo' function with no arguments: std::vector Args(1); Args[0].IntVal = p->value; - + synchronize.block(); // wait until other threads are at this point GenericValue gv = p->EE->runFunction(p->F, Args); - + return (void*) intptr_t(gv.IntVal); } -int main() +int main() { // Create some module to put our function into it. Module *M = new Module("test"); - + Function* add1F = createAdd1( M ); Function* fibF = CreateFibFunction( M ); - + // Now we create the JIT. ExistingModuleProvider* MP = new ExistingModuleProvider(M); ExecutionEngine* EE = ExecutionEngine::create(MP, false); - + //~ std::cout << "We just constructed this LLVM module:\n\n" << *M; //~ std::cout << "\n\nRunning foo: " << std::flush; - + // Create one thread for add1 and two threads for fib struct threadParams add1 = { EE, add1F, 1000 }; struct threadParams fib1 = { EE, fibF, 39 }; struct threadParams fib2 = { EE, fibF, 42 }; - + pthread_t add1Thread; int result = pthread_create( &add1Thread, NULL, callFunc, &add1 ); if ( result != 0 ) { std::cerr << "Could not create thread" << std::endl; return 1; } - + pthread_t fibThread1; result = pthread_create( &fibThread1, NULL, callFunc, &fib1 ); if ( result != 0 ) { std::cerr << "Could not create thread" << std::endl; return 1; } - + pthread_t fibThread2; result = pthread_create( &fibThread2, NULL, callFunc, &fib2 ); if ( result != 0 ) { std::cerr << "Could not create thread" << std::endl; return 1; } - + synchronize.releaseThreads(3); // wait until other threads are at this point - + void* returnValue; result = pthread_join( add1Thread, &returnValue ); if ( result != 0 ) { @@ -276,20 +276,20 @@ return 1; } std::cout << "Add1 returned " << intptr_t(returnValue) << std::endl; - + result = pthread_join( fibThread1, &returnValue ); if ( result != 0 ) { std::cerr << "Could not join thread" << std::endl; return 1; } std::cout << "Fib1 returned " << intptr_t(returnValue) << std::endl; - + result = pthread_join( fibThread2, &returnValue ); if ( result != 0 ) { std::cerr << "Could not join thread" << std::endl; return 1; } std::cout << "Fib2 returned " << intptr_t(returnValue) << std::endl; - + return 0; } From jeffc at jolt-lang.org Wed Jul 27 01:12:58 2005 From: jeffc at jolt-lang.org (Jeff Cohen) Date: Wed, 27 Jul 2005 01:12:58 -0500 Subject: [llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp SelectionDAG.cpp SelectionDAGISel.cpp Message-ID: <200507270612.BAA32195@zion.cs.uiuc.edu> Changes in directory llvm/lib/CodeGen/SelectionDAG: LegalizeDAG.cpp updated: 1.143 -> 1.144 SelectionDAG.cpp updated: 1.125 -> 1.126 SelectionDAGISel.cpp updated: 1.66 -> 1.67 --- Log message: Eliminate all remaining tabs and trailing spaces. --- Diffs of the changes: (+42 -42) LegalizeDAG.cpp | 72 +++++++++++++++++++++++++-------------------------- SelectionDAG.cpp | 8 ++--- SelectionDAGISel.cpp | 4 +- 3 files changed, 42 insertions(+), 42 deletions(-) Index: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp diff -u llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.143 llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.144 --- llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.143 Sun Jul 17 23:31:14 2005 +++ llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp Wed Jul 27 01:12:33 2005 @@ -128,7 +128,7 @@ SDOperand ExpandLegalUINT_TO_FP(SDOperand LegalOp, MVT::ValueType DestVT); SDOperand PromoteLegalINT_TO_FP(SDOperand LegalOp, MVT::ValueType DestVT, bool isSigned); - + bool ExpandShift(unsigned Opc, SDOperand Op, SDOperand Amt, SDOperand &Lo, SDOperand &Hi); void ExpandShiftParts(unsigned NodeOp, SDOperand Op, SDOperand Amt, @@ -152,22 +152,22 @@ "Too many value types for ValueTypeActions to hold!"); } -/// ExpandLegalUINT_TO_FP - This function is responsible for legalizing a +/// ExpandLegalUINT_TO_FP - This function is responsible for legalizing a /// UINT_TO_FP operation of the specified operand when the target requests that /// we expand it. At this point, we know that the result and operand types are /// legal for the target. SDOperand SelectionDAGLegalize::ExpandLegalUINT_TO_FP(SDOperand Op0, MVT::ValueType DestVT) { SDOperand Tmp1 = DAG.getNode(ISD::SINT_TO_FP, DestVT, Op0); - - SDOperand SignSet = DAG.getSetCC(ISD::SETLT, TLI.getSetCCResultTy(), + + SDOperand SignSet = DAG.getSetCC(ISD::SETLT, TLI.getSetCCResultTy(), Op0, - DAG.getConstant(0, + DAG.getConstant(0, Op0.getValueType())); SDOperand Zero = getIntPtrConstant(0), Four = getIntPtrConstant(4); SDOperand CstOffset = DAG.getNode(ISD::SELECT, Zero.getValueType(), SignSet, Four, Zero); - + // If the sign bit of the integer is set, the large number will be treated as // a negative number. To counteract this, the dynamic code adds an offset // depending on the data type. @@ -181,7 +181,7 @@ } if (TLI.isLittleEndian()) FF <<= 32; static Constant *FudgeFactor = ConstantUInt::get(Type::ULongTy, FF); - + MachineConstantPool *CP = DAG.getMachineFunction().getConstantPool(); SDOperand CPIdx = DAG.getConstantPool(CP->getConstantPoolIndex(FudgeFactor), TLI.getPointerTy()); @@ -196,12 +196,12 @@ DAG.getEntryNode(), CPIdx, DAG.getSrcValue(NULL), MVT::f32)); } - + NeedsAnotherIteration = true; return DAG.getNode(ISD::ADD, DestVT, Tmp1, FudgeInReg); } -/// PromoteLegalUINT_TO_FP - This function is responsible for legalizing a +/// PromoteLegalUINT_TO_FP - This function is responsible for legalizing a /// UINT_TO_FP operation of the specified operand when the target requests that /// we promote it. At this point, we know that the result and operand types are /// legal for the target, and that there is a legal UINT_TO_FP or SINT_TO_FP @@ -211,14 +211,14 @@ bool isSigned) { // First step, figure out the appropriate *INT_TO_FP operation to use. MVT::ValueType NewInTy = LegalOp.getValueType(); - + unsigned OpToUse = 0; - + // Scan for the appropriate larger type to use. while (1) { NewInTy = (MVT::ValueType)(NewInTy+1); assert(MVT::isInteger(NewInTy) && "Ran out of possibilities!"); - + // If the target supports SINT_TO_FP of this type, use it. switch (TLI.getOperationAction(ISD::SINT_TO_FP, NewInTy)) { default: break; @@ -232,7 +232,7 @@ } if (OpToUse) break; if (isSigned) continue; - + // If the target supports UINT_TO_FP of this type, use it. switch (TLI.getOperationAction(ISD::UINT_TO_FP, NewInTy)) { default: break; @@ -245,13 +245,13 @@ break; } if (OpToUse) break; - + // Otherwise, try a larger type. } // Make sure to legalize any nodes we create here in the next pass. NeedsAnotherIteration = true; - + // Okay, we found the operation and type to use. Zero extend our input to the // desired type then run the operation on it. return DAG.getNode(OpToUse, DestVT, @@ -760,7 +760,7 @@ float F; } V; V.F = CFP->getValue(); - Result = DAG.getNode(ISD::STORE, MVT::Other, Tmp1, + Result = DAG.getNode(ISD::STORE, MVT::Other, Tmp1, DAG.getConstant(V.I, MVT::i32), Tmp2, Node->getOperand(3)); } else { @@ -770,7 +770,7 @@ double F; } V; V.F = CFP->getValue(); - Result = DAG.getNode(ISD::STORE, MVT::Other, Tmp1, + Result = DAG.getNode(ISD::STORE, MVT::Other, Tmp1, DAG.getConstant(V.I, MVT::i64), Tmp2, Node->getOperand(3)); } @@ -1282,15 +1282,15 @@ break; case ISD::CTTZ: //if Tmp1 == sizeinbits(NVT) then Tmp1 = sizeinbits(Old VT) - Tmp2 = DAG.getSetCC(ISD::SETEQ, TLI.getSetCCResultTy(), Tmp1, + Tmp2 = DAG.getSetCC(ISD::SETEQ, TLI.getSetCCResultTy(), Tmp1, DAG.getConstant(getSizeInBits(NVT), NVT)); - Result = DAG.getNode(ISD::SELECT, NVT, Tmp2, + Result = DAG.getNode(ISD::SELECT, NVT, Tmp2, DAG.getConstant(getSizeInBits(OVT),NVT), Tmp1); break; case ISD::CTLZ: //Tmp1 = Tmp1 - (sizeinbits(NVT) - sizeinbits(Old VT)) - Result = DAG.getNode(ISD::SUB, NVT, Tmp1, - DAG.getConstant(getSizeInBits(NVT) - + Result = DAG.getNode(ISD::SUB, NVT, Tmp1, + DAG.getConstant(getSizeInBits(NVT) - getSizeInBits(OVT), NVT)); break; } @@ -1314,7 +1314,7 @@ //x = (x & mask[i][len/8]) + (x >> (1 << i) & mask[i][len/8]) Tmp2 = DAG.getConstant(mask[i], VT); Tmp3 = DAG.getConstant(1ULL << i, ShVT); - Tmp1 = DAG.getNode(ISD::ADD, VT, + Tmp1 = DAG.getNode(ISD::ADD, VT, DAG.getNode(ISD::AND, VT, Tmp1, Tmp2), DAG.getNode(ISD::AND, VT, DAG.getNode(ISD::SRL, VT, Tmp1, Tmp3), @@ -1329,16 +1329,16 @@ x = x | (x >> 2); ... x = x | (x >>16); - x = x | (x >>32); // for 64-bit input + x = x | (x >>32); // for 64-bit input return popcount(~x); - + but see also: http://www.hackersdelight.org/HDcode/nlz.cc */ MVT::ValueType VT = Tmp1.getValueType(); MVT::ValueType ShVT = TLI.getShiftAmountTy(); unsigned len = getSizeInBits(VT); for (unsigned i = 0; (1U << i) <= (len / 2); ++i) { Tmp3 = DAG.getConstant(1ULL << i, ShVT); - Tmp1 = DAG.getNode(ISD::OR, VT, Tmp1, + Tmp1 = DAG.getNode(ISD::OR, VT, Tmp1, DAG.getNode(ISD::SRL, VT, Tmp1, Tmp3)); } Tmp3 = DAG.getNode(ISD::XOR, VT, Tmp1, DAG.getConstant(~0ULL, VT)); @@ -1346,20 +1346,20 @@ break; } case ISD::CTTZ: { - // for now, we use: { return popcount(~x & (x - 1)); } + // for now, we use: { return popcount(~x & (x - 1)); } // unless the target has ctlz but not ctpop, in which case we use: // { return 32 - nlz(~x & (x-1)); } // see also http://www.hackersdelight.org/HDcode/ntz.cc MVT::ValueType VT = Tmp1.getValueType(); Tmp2 = DAG.getConstant(~0ULL, VT); - Tmp3 = DAG.getNode(ISD::AND, VT, + Tmp3 = DAG.getNode(ISD::AND, VT, DAG.getNode(ISD::XOR, VT, Tmp1, Tmp2), DAG.getNode(ISD::SUB, VT, Tmp1, DAG.getConstant(1, VT))); // If ISD::CTLZ is legal and CTPOP isn't, then do that instead if (TLI.getOperationAction(ISD::CTPOP, VT) != TargetLowering::Legal && TLI.getOperationAction(ISD::CTLZ, VT) == TargetLowering::Legal) { - Result = LegalizeOp(DAG.getNode(ISD::SUB, VT, + Result = LegalizeOp(DAG.getNode(ISD::SUB, VT, DAG.getConstant(getSizeInBits(VT), VT), DAG.getNode(ISD::CTLZ, VT, Tmp3))); } else { @@ -1374,7 +1374,7 @@ break; } break; - + // Unary operators case ISD::FABS: case ISD::FNEG: @@ -1453,7 +1453,7 @@ if (Node->getOpcode() == ISD::UINT_TO_FP || Node->getOpcode() == ISD::SINT_TO_FP) { bool isSigned = Node->getOpcode() == ISD::SINT_TO_FP; - switch (TLI.getOperationAction(Node->getOpcode(), + switch (TLI.getOperationAction(Node->getOpcode(), Node->getOperand(0).getValueType())) { default: assert(0 && "Unknown operation action!"); case TargetLowering::Expand: @@ -1936,15 +1936,15 @@ break; case ISD::CTTZ: //if Tmp1 == sizeinbits(NVT) then Tmp1 = sizeinbits(Old VT) - Tmp2 = DAG.getSetCC(ISD::SETEQ, MVT::i1, Tmp1, + Tmp2 = DAG.getSetCC(ISD::SETEQ, MVT::i1, Tmp1, DAG.getConstant(getSizeInBits(NVT), NVT)); - Result = DAG.getNode(ISD::SELECT, NVT, Tmp2, + Result = DAG.getNode(ISD::SELECT, NVT, Tmp2, DAG.getConstant(getSizeInBits(VT),NVT), Tmp1); break; case ISD::CTLZ: //Tmp1 = Tmp1 - (sizeinbits(NVT) - sizeinbits(Old VT)) - Result = DAG.getNode(ISD::SUB, NVT, Tmp1, - DAG.getConstant(getSizeInBits(NVT) - + Result = DAG.getNode(ISD::SUB, NVT, Tmp1, + DAG.getConstant(getSizeInBits(NVT) - getSizeInBits(VT), NVT)); break; } @@ -2282,7 +2282,7 @@ return SDOperand(LatestCallSeqEnd, 0); } -/// SpliceCallInto - Given the result chain of a libcall (CallResult), and a +/// SpliceCallInto - Given the result chain of a libcall (CallResult), and a void SelectionDAGLegalize::SpliceCallInto(const SDOperand &CallResult, SDNode *OutChain) { // Nothing to splice it into? @@ -2558,7 +2558,7 @@ unsigned IncrementSize = MVT::getSizeInBits(Lo.getValueType())/8; Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr, getIntPtrConstant(IncrementSize)); - //Is this safe? declaring that the two parts of the split load + //Is this safe? declaring that the two parts of the split load //are from the same instruction? Hi = DAG.getLoad(NVT, Ch, Ptr, Node->getOperand(2)); Index: llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp diff -u llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp:1.125 llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp:1.126 --- llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp:1.125 Sat Jul 9 20:55:33 2005 +++ llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp Wed Jul 27 01:12:33 2005 @@ -1212,7 +1212,7 @@ break; case ISD::SUB: if (N1.getOpcode() == ISD::ADD) { - if (N1.Val->getOperand(0) == N2 && + if (N1.Val->getOperand(0) == N2 && !MVT::isFloatingPoint(N2.getValueType())) return N1.Val->getOperand(1); // (A+B)-A == B if (N1.Val->getOperand(1) == N2 && @@ -1233,7 +1233,7 @@ if (N1.getOpcode() == ISD::SIGN_EXTEND_INREG) if (cast(N1.getOperand(1))->getVT() <= EVT) return N1; - + // If we are sign extending a sextload, return just the load. if (N1.getOpcode() == ISD::SEXTLOAD) if (cast(N1.getOperand(3))->getVT() <= EVT) @@ -1311,7 +1311,7 @@ SDOperand SelectionDAG::getLoad(MVT::ValueType VT, - SDOperand Chain, SDOperand Ptr, + SDOperand Chain, SDOperand Ptr, SDOperand SV) { SDNode *&N = Loads[std::make_pair(Ptr, std::make_pair(Chain, VT))]; if (N) return SDOperand(N, 0); @@ -1457,7 +1457,7 @@ } SDOperand SelectionDAG::getNode(unsigned Opcode, MVT::ValueType VT, - SDOperand N1, SDOperand N2, SDOperand N3, + SDOperand N1, SDOperand N2, SDOperand N3, SDOperand N4) { std::vector Ops; Ops.reserve(4); Index: llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp diff -u llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.66 llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.67 --- llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.66 Tue Jul 19 11:50:03 2005 +++ llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp Wed Jul 27 01:12:33 2005 @@ -716,7 +716,7 @@ Ops.push_back(getValue(I.getOperand(1))); Tmp = DAG.getNode(F->getIntrinsicID() == Intrinsic::readport ? ISD::READPORT : ISD::READIO, VTs, Ops); - + setValue(&I, Tmp); DAG.setRoot(Tmp.getValue(1)); return; @@ -887,7 +887,7 @@ } void SelectionDAGLowering::visitVAEnd(CallInst &I) { - DAG.setRoot(TLI.LowerVAEnd(getRoot(), getValue(I.getOperand(1)), + DAG.setRoot(TLI.LowerVAEnd(getRoot(), getValue(I.getOperand(1)), I.getOperand(1), DAG)); } From jeffc at jolt-lang.org Wed Jul 27 01:12:58 2005 From: jeffc at jolt-lang.org (Jeff Cohen) Date: Wed, 27 Jul 2005 01:12:58 -0500 Subject: [llvm-commits] CVS: llvm/lib/Target/IA64/IA64ISelPattern.cpp Message-ID: <200507270612.BAA32182@zion.cs.uiuc.edu> Changes in directory llvm/lib/Target/IA64: IA64ISelPattern.cpp updated: 1.49 -> 1.50 --- Log message: Eliminate all remaining tabs and trailing spaces. --- Diffs of the changes: (+84 -84) IA64ISelPattern.cpp | 168 ++++++++++++++++++++++++++-------------------------- 1 files changed, 84 insertions(+), 84 deletions(-) Index: llvm/lib/Target/IA64/IA64ISelPattern.cpp diff -u llvm/lib/Target/IA64/IA64ISelPattern.cpp:1.49 llvm/lib/Target/IA64/IA64ISelPattern.cpp:1.50 --- llvm/lib/Target/IA64/IA64ISelPattern.cpp:1.49 Sat Jul 9 20:56:13 2005 +++ llvm/lib/Target/IA64/IA64ISelPattern.cpp Wed Jul 27 01:12:33 2005 @@ -226,7 +226,7 @@ // Create the frame index object for this incoming parameter... ArgOffset = 16 + 8 * (count - 8); int FI = MFI->CreateFixedObject(8, ArgOffset); - + // Create the SelectionDAG nodes corresponding to a load //from this parameter SDOperand FIN = DAG.getFrameIndex(FI, MVT::i64); @@ -307,7 +307,7 @@ IA64TargetLowering::LowerCallTo(SDOperand Chain, const Type *RetTy, bool isVarArg, unsigned CallingConv, bool isTailCall, - SDOperand Callee, ArgListTy &Args, + SDOperand Callee, ArgListTy &Args, SelectionDAG &DAG) { MachineFunction &MF = DAG.getMachineFunction(); @@ -400,7 +400,7 @@ "Other types should have been promoted for varargs!"); Amt = 8; } - Val = DAG.getNode(ISD::ADD, Val.getValueType(), Val, + Val = DAG.getNode(ISD::ADD, Val.getValueType(), Val, DAG.getConstant(Amt, Val.getValueType())); Chain = DAG.getNode(ISD::STORE, MVT::Other, Chain, Val, VAListP, DAG.getSrcValue(VAListV)); @@ -494,22 +494,22 @@ int lim=inString.size(); while(curpos1) { - inString.replace(curpos, runlength+1, replaceString); - curpos+=runlength-1; + inString.replace(curpos, runlength+1, replaceString); + curpos+=runlength-1; } else - curpos++; + curpos++; } else { // a zero, we just keep chugging along curpos++; } @@ -529,7 +529,7 @@ struct shiftaddblob { // this encodes stuff like (x=) "A << B [+-] C << D" unsigned firstVal; // A - unsigned firstShift; // B + unsigned firstShift; // B unsigned secondVal; // C unsigned secondShift; // D bool isSub; @@ -555,7 +555,7 @@ } std::vector p,n; - + for(int i=0; i<=length; i++) { if (s.c_str()[length-i]=='P') { p.push_back(i); @@ -609,49 +609,49 @@ int z=abs(int_d)-1; if(int_d>0) { - + for(unsigned base=0; basegetConstant(ops[i].firstShift, MVT::i64); @@ -830,11 +830,11 @@ if(preliminaryShift) { SDOperand finalshift = ISelDAG->getConstant(preliminaryShift, MVT::i64); shiftedresult = ISelDAG->getNode(ISD::SHL, MVT::i64, - results[ops.size()-1], finalshift); + results[ops.size()-1], finalshift); } else { // there was no preliminary divide-by-power-of-2 required shiftedresult = results[ops.size()-1]; } - + SDOperand finalresult; if(flippedSign) { // if we were multiplying by a negative constant: SDOperand zero = ISelDAG->getConstant(0, MVT::i64); @@ -843,8 +843,8 @@ } else { // there was no preliminary multiply by -1 required finalresult = shiftedresult; } - - return finalresult; + + return finalresult; } /// ExactLog2 - This function solves for (Val == 1 << (N-1)) and returns N. It @@ -1098,7 +1098,7 @@ .addReg(Tmp1); break; } - + return Result; } @@ -1316,7 +1316,7 @@ Tmp1 = SelectExpr(N.getOperand(0).getOperand(0)); int shl_amt = CSD->getValue(); Tmp3 = SelectExpr(N.getOperand(1)); - + BuildMI(BB, IA64::SHLADD, 3, Result) .addReg(Tmp1).addImm(shl_amt).addReg(Tmp3); return Result; // early exit @@ -1344,21 +1344,21 @@ if(DestType != MVT::f64) { // TODO: speed! if(N.getOperand(1).getOpcode() != ISD::Constant) { // if not a const mul - // boring old integer multiply with xma - Tmp1 = SelectExpr(N.getOperand(0)); - Tmp2 = SelectExpr(N.getOperand(1)); - - unsigned TempFR1=MakeReg(MVT::f64); - unsigned TempFR2=MakeReg(MVT::f64); - unsigned TempFR3=MakeReg(MVT::f64); - BuildMI(BB, IA64::SETFSIG, 1, TempFR1).addReg(Tmp1); - BuildMI(BB, IA64::SETFSIG, 1, TempFR2).addReg(Tmp2); - BuildMI(BB, IA64::XMAL, 1, TempFR3).addReg(TempFR1).addReg(TempFR2) - .addReg(IA64::F0); - BuildMI(BB, IA64::GETFSIG, 1, Result).addReg(TempFR3); - return Result; // early exit + // boring old integer multiply with xma + Tmp1 = SelectExpr(N.getOperand(0)); + Tmp2 = SelectExpr(N.getOperand(1)); + + unsigned TempFR1=MakeReg(MVT::f64); + unsigned TempFR2=MakeReg(MVT::f64); + unsigned TempFR3=MakeReg(MVT::f64); + BuildMI(BB, IA64::SETFSIG, 1, TempFR1).addReg(Tmp1); + BuildMI(BB, IA64::SETFSIG, 1, TempFR2).addReg(Tmp2); + BuildMI(BB, IA64::XMAL, 1, TempFR3).addReg(TempFR1).addReg(TempFR2) + .addReg(IA64::F0); + BuildMI(BB, IA64::GETFSIG, 1, Result).addReg(TempFR3); + return Result; // early exit } else { // we are multiplying by an integer constant! yay - return Reg = SelectExpr(BuildConstmulSequence(N)); // avert your eyes! + return Reg = SelectExpr(BuildConstmulSequence(N)); // avert your eyes! } } else { // floating point multiply @@ -1799,7 +1799,7 @@ unsigned ModulusResult = MakeReg(MVT::f64); unsigned TmpF = MakeReg(MVT::f64); unsigned TmpI = MakeReg(MVT::i64); - + BuildMI(BB, IA64::SUB, 2, TmpI).addReg(IA64::r0).addReg(Tmp2); BuildMI(BB, IA64::SETFSIG, 1, TmpF).addReg(TmpI); BuildMI(BB, IA64::XMAL, 3, ModulusResult) @@ -1843,7 +1843,7 @@ Tmp2 = SelectExpr(N.getOperand(1)); } else // not comparing against a constant Tmp2 = SelectExpr(N.getOperand(1)); - + switch (SetCC->getCondition()) { default: assert(0 && "Unknown integer comparison!"); case ISD::SETEQ: @@ -1956,7 +1956,7 @@ case MVT::i16: Opc = IA64::LD2; break; case MVT::i32: Opc = IA64::LD4; break; case MVT::i64: Opc = IA64::LD8; break; - + case MVT::f32: Opc = IA64::LDF4; break; case MVT::f64: Opc = IA64::LDF8; break; } @@ -2037,7 +2037,7 @@ BuildMI(BB, Opc, 1, dummy).addReg(Tmp2); // we compare to 0. true? 0. false? 1. BuildMI(BB, IA64::CMPNE, 2, Result).addReg(dummy).addReg(IA64::r0); - } + } } return Result; @@ -2114,7 +2114,7 @@ for (int i = 8, e = argvregs.size(); i < e; ++i) { unsigned tempAddr = MakeReg(MVT::i64); - + switch(N.getOperand(i+2).getValueType()) { default: Node->dump(); @@ -2157,7 +2157,7 @@ } else { // otherwise we need to get the function descriptor // load the branch target (function)'s entry point and - // GP, then branch + // GP, then branch Tmp1 = SelectExpr(N.getOperand(1)); unsigned targetEntryPoint=MakeReg(MVT::i64); @@ -2355,7 +2355,7 @@ case MVT::i16: Opc = IA64::ST2; break; case MVT::i32: Opc = IA64::ST4; break; case MVT::i64: Opc = IA64::ST8; break; - + case MVT::f32: Opc = IA64::STF4; break; case MVT::f64: Opc = IA64::STF8; break; } @@ -2394,7 +2394,7 @@ } else if(N.getOperand(2).getOpcode() == ISD::FrameIndex) { // FIXME? (what about bools?) - + unsigned dummy = MakeReg(MVT::i64); BuildMI(BB, IA64::MOV, 1, dummy) .addFrameIndex(cast(N.getOperand(2))->getIndex()); From jeffc at jolt-lang.org Wed Jul 27 01:12:57 2005 From: jeffc at jolt-lang.org (Jeff Cohen) Date: Wed, 27 Jul 2005 01:12:57 -0500 Subject: [llvm-commits] CVS: llvm/lib/Target/Alpha/AlphaCodeEmitter.cpp AlphaISelPattern.cpp AlphaJITInfo.cpp Message-ID: <200507270612.BAA32137@zion.cs.uiuc.edu> Changes in directory llvm/lib/Target/Alpha: AlphaCodeEmitter.cpp updated: 1.2 -> 1.3 AlphaISelPattern.cpp updated: 1.154 -> 1.155 AlphaJITInfo.cpp updated: 1.2 -> 1.3 --- Log message: Eliminate all remaining tabs and trailing spaces. --- Diffs of the changes: (+48 -48) AlphaCodeEmitter.cpp | 8 ++-- AlphaISelPattern.cpp | 84 +++++++++++++++++++++++++-------------------------- AlphaJITInfo.cpp | 4 +- 3 files changed, 48 insertions(+), 48 deletions(-) Index: llvm/lib/Target/Alpha/AlphaCodeEmitter.cpp diff -u llvm/lib/Target/Alpha/AlphaCodeEmitter.cpp:1.2 llvm/lib/Target/Alpha/AlphaCodeEmitter.cpp:1.3 --- llvm/lib/Target/Alpha/AlphaCodeEmitter.cpp:1.2 Wed Jul 27 00:58:01 2005 +++ llvm/lib/Target/Alpha/AlphaCodeEmitter.cpp Wed Jul 27 01:12:33 2005 @@ -169,11 +169,11 @@ rv = getAlphaRegNumber(MO.getReg()); } else if (MO.isImmediate()) { rv = MO.getImmedValue(); - } else if (MO.isGlobalAddress() || MO.isExternalSymbol() + } else if (MO.isGlobalAddress() || MO.isExternalSymbol() || MO.isConstantPoolIndex()) { DEBUG(std::cerr << MO << " is a relocated op for " << MI << "\n";); - bool isExternal = MO.isExternalSymbol() || - (MO.isGlobalAddress() && + bool isExternal = MO.isExternalSymbol() || + (MO.isGlobalAddress() && ( MO.getGlobal()->hasWeakLinkage() || MO.getGlobal()->isExternal()) ); unsigned Reloc = 0; @@ -213,7 +213,7 @@ true)); else MCE.addRelocation(MachineRelocation((unsigned)MCE.getCurrentPCOffset(), - Reloc, MO.getConstantPoolIndex(), + Reloc, MO.getConstantPoolIndex(), Offset)); } else if (MO.isMachineBasicBlock()) { unsigned* CurrPC = (unsigned*)(intptr_t)MCE.getCurrentPCValue(); Index: llvm/lib/Target/Alpha/AlphaISelPattern.cpp diff -u llvm/lib/Target/Alpha/AlphaISelPattern.cpp:1.154 llvm/lib/Target/Alpha/AlphaISelPattern.cpp:1.155 --- llvm/lib/Target/Alpha/AlphaISelPattern.cpp:1.154 Sat Jul 23 02:46:48 2005 +++ llvm/lib/Target/Alpha/AlphaISelPattern.cpp Wed Jul 27 01:12:33 2005 @@ -64,7 +64,7 @@ //Move an Ireg to a FPreg ITOF, //Move a FPreg to an Ireg - FTOI, + FTOI, }; } } @@ -93,7 +93,7 @@ setOperationAction(ISD::EXTLOAD, MVT::i1, Promote); setOperationAction(ISD::EXTLOAD, MVT::f32, Expand); - + setOperationAction(ISD::ZEXTLOAD, MVT::i1, Promote); setOperationAction(ISD::ZEXTLOAD, MVT::i32, Expand); @@ -164,7 +164,7 @@ virtual std::pair LowerVAArg(SDOperand Chain, SDOperand VAListP, Value *VAListV, const Type *ArgTy, SelectionDAG &DAG); - + void restoreGP(MachineBasicBlock* BB) { BuildMI(BB, Alpha::BIS, 2, Alpha::R29).addReg(GP).addReg(GP); @@ -203,8 +203,8 @@ } else { int SSFI = MF.getFrameInfo()->CreateStackObject(8, 8); SDOperand StackSlot = DAG.getFrameIndex(SSFI, getPointerTy()); - SDOperand Store = DAG.getNode(ISD::STORE, MVT::Other, - DAG.getEntryNode(), Op.getOperand(0), + SDOperand Store = DAG.getNode(ISD::STORE, MVT::Other, + DAG.getEntryNode(), Op.getOperand(0), StackSlot, DAG.getSrcValue(NULL)); SRC = DAG.getLoad(Op.getValueType(), Store.getValue(0), StackSlot, DAG.getSrcValue(NULL)); @@ -289,7 +289,7 @@ case MVT::i16: case MVT::i32: case MVT::i64: - args_int[count] = AddLiveIn(MF, args_int[count], + args_int[count] = AddLiveIn(MF, args_int[count], getRegClassFor(MVT::i64)); argt = DAG.getCopyFromReg(args_int[count], VT, DAG.getRoot()); if (VT != MVT::i64) @@ -322,15 +322,15 @@ int FI = MFI->CreateFixedObject(8, -8 * (6 - i)); if (i == 0) VarArgsBase = FI; SDOperand SDFI = DAG.getFrameIndex(FI, MVT::i64); - LS.push_back(DAG.getNode(ISD::STORE, MVT::Other, DAG.getRoot(), argt, + LS.push_back(DAG.getNode(ISD::STORE, MVT::Other, DAG.getRoot(), argt, SDFI, DAG.getSrcValue(NULL))); - + if (args_float[i] < 1024) args_float[i] = AddLiveIn(MF,args_float[i], getRegClassFor(MVT::f64)); argt = DAG.getCopyFromReg(args_float[i], MVT::f64, DAG.getRoot()); FI = MFI->CreateFixedObject(8, - 8 * (12 - i)); SDFI = DAG.getFrameIndex(FI, MVT::i64); - LS.push_back(DAG.getNode(ISD::STORE, MVT::Other, DAG.getRoot(), argt, + LS.push_back(DAG.getNode(ISD::STORE, MVT::Other, DAG.getRoot(), argt, SDFI, DAG.getSrcValue(NULL))); } @@ -363,7 +363,7 @@ AlphaTargetLowering::LowerCallTo(SDOperand Chain, const Type *RetTy, bool isVarArg, unsigned CallingConv, bool isTailCall, - SDOperand Callee, ArgListTy &Args, + SDOperand Callee, ArgListTy &Args, SelectionDAG &DAG) { int NumBytes = 0; if (Args.size() > 6) @@ -413,12 +413,12 @@ Value *VAListV, SelectionDAG &DAG) { // vastart stores the address of the VarArgsBase and VarArgsOffset SDOperand FR = DAG.getFrameIndex(VarArgsBase, MVT::i64); - SDOperand S1 = DAG.getNode(ISD::STORE, MVT::Other, Chain, FR, VAListP, + SDOperand S1 = DAG.getNode(ISD::STORE, MVT::Other, Chain, FR, VAListP, DAG.getSrcValue(VAListV)); - SDOperand SA2 = DAG.getNode(ISD::ADD, MVT::i64, VAListP, + SDOperand SA2 = DAG.getNode(ISD::ADD, MVT::i64, VAListP, DAG.getConstant(8, MVT::i64)); - return DAG.getNode(ISD::TRUNCSTORE, MVT::Other, S1, - DAG.getConstant(VarArgsOffset, MVT::i64), SA2, + return DAG.getNode(ISD::TRUNCSTORE, MVT::Other, S1, + DAG.getConstant(VarArgsOffset, MVT::i64), SA2, DAG.getSrcValue(VAListV, 8), DAG.getValueType(MVT::i32)); } @@ -427,9 +427,9 @@ const Type *ArgTy, SelectionDAG &DAG) { SDOperand Base = DAG.getLoad(MVT::i64, Chain, VAListP, DAG.getSrcValue(VAListV)); - SDOperand Tmp = DAG.getNode(ISD::ADD, MVT::i64, VAListP, + SDOperand Tmp = DAG.getNode(ISD::ADD, MVT::i64, VAListP, DAG.getConstant(8, MVT::i64)); - SDOperand Offset = DAG.getExtLoad(ISD::SEXTLOAD, MVT::i64, Base.getValue(1), + SDOperand Offset = DAG.getExtLoad(ISD::SEXTLOAD, MVT::i64, Base.getValue(1), Tmp, DAG.getSrcValue(VAListV, 8), MVT::i32); SDOperand DataPtr = DAG.getNode(ISD::ADD, MVT::i64, Base, Offset); if (ArgTy->isFloatingPoint()) @@ -437,7 +437,7 @@ //if fp && Offset < 6*8, then subtract 6*8 from DataPtr SDOperand FPDataPtr = DAG.getNode(ISD::SUB, MVT::i64, DataPtr, DAG.getConstant(8*6, MVT::i64)); - SDOperand CC = DAG.getSetCC(ISD::SETLT, MVT::i64, + SDOperand CC = DAG.getSetCC(ISD::SETLT, MVT::i64, Offset, DAG.getConstant(8*6, MVT::i64)); DataPtr = DAG.getNode(ISD::SELECT, MVT::i64, CC, FPDataPtr, DataPtr); } @@ -450,13 +450,13 @@ Result = DAG.getExtLoad(ISD::ZEXTLOAD, MVT::i64, Offset.getValue(1), DataPtr, DAG.getSrcValue(NULL), MVT::i32); else - Result = DAG.getLoad(getValueType(ArgTy), Offset.getValue(1), DataPtr, + Result = DAG.getLoad(getValueType(ArgTy), Offset.getValue(1), DataPtr, DAG.getSrcValue(NULL)); - SDOperand NewOffset = DAG.getNode(ISD::ADD, MVT::i64, Offset, + SDOperand NewOffset = DAG.getNode(ISD::ADD, MVT::i64, Offset, DAG.getConstant(8, MVT::i64)); - SDOperand Update = DAG.getNode(ISD::TRUNCSTORE, MVT::Other, - Result.getValue(1), NewOffset, + SDOperand Update = DAG.getNode(ISD::TRUNCSTORE, MVT::Other, + Result.getValue(1), NewOffset, Tmp, DAG.getSrcValue(VAListV, 8), DAG.getValueType(MVT::i32)); Result = DAG.getNode(ISD::TRUNCATE, getValueType(ArgTy), Result); @@ -468,15 +468,15 @@ SDOperand AlphaTargetLowering:: LowerVACopy(SDOperand Chain, SDOperand SrcP, Value *SrcV, SDOperand DestP, Value *DestV, SelectionDAG &DAG) { - SDOperand Val = DAG.getLoad(getPointerTy(), Chain, SrcP, + SDOperand Val = DAG.getLoad(getPointerTy(), Chain, SrcP, DAG.getSrcValue(SrcV)); SDOperand Result = DAG.getNode(ISD::STORE, MVT::Other, Val.getValue(1), Val, DestP, DAG.getSrcValue(DestV)); - SDOperand NP = DAG.getNode(ISD::ADD, MVT::i64, SrcP, + SDOperand NP = DAG.getNode(ISD::ADD, MVT::i64, SrcP, DAG.getConstant(8, MVT::i64)); Val = DAG.getExtLoad(ISD::SEXTLOAD, MVT::i64, Result, NP, DAG.getSrcValue(SrcV, 8), MVT::i32); - SDOperand NPD = DAG.getNode(ISD::ADD, MVT::i64, DestP, + SDOperand NPD = DAG.getNode(ISD::ADD, MVT::i64, DestP, DAG.getConstant(8, MVT::i64)); return DAG.getNode(ISD::TRUNCSTORE, MVT::Other, Val.getValue(1), Val, NPD, DAG.getSrcValue(DestV, 8), @@ -514,7 +514,7 @@ int max_depth; public: - AlphaISel(TargetMachine &TM) : SelectionDAGISel(AlphaLowering), + AlphaISel(TargetMachine &TM) : SelectionDAGISel(AlphaLowering), AlphaLowering(TM) {} @@ -535,9 +535,9 @@ if(has_sym) ++count_ins; if(EnableAlphaCount) - std::cerr << "COUNT: " - << BB->getParent()->getFunction ()->getName() << " " - << BB->getNumber() << " " + std::cerr << "COUNT: " + << BB->getParent()->getFunction ()->getName() << " " + << BB->getNumber() << " " << max_depth << " " << count_ins << " " << count_outs << "\n"; @@ -546,7 +546,7 @@ ExprMap.clear(); CCInvMap.clear(); } - + virtual void EmitFunctionEntryCode(Function &Fn, MachineFunction &MF); unsigned SelectExpr(SDOperand N); @@ -1032,7 +1032,7 @@ return; } } else { //FP - //Any comparison between 2 values should be codegened as an folded + //Any comparison between 2 values should be codegened as an folded //branch, as moving CC to the integer register is very expensive //for a cmp b: c = a - b; //a = b: c = 0 @@ -1298,7 +1298,7 @@ case ISD::GlobalAddress: AlphaLowering.restoreGP(BB); has_sym = true; - + Reg = Result = MakeReg(MVT::i64); if (EnableAlphaLSMark) @@ -1559,7 +1559,7 @@ switch (SetCC->getCondition()) { default: Node->dump(); assert(0 && "Unknown integer comparison!"); - case ISD::SETEQ: + case ISD::SETEQ: Opc = isConst ? Alpha::CMPEQi : Alpha::CMPEQ; dir=1; break; case ISD::SETLT: Opc = isConst ? Alpha::CMPLTi : Alpha::CMPLT; dir = 1; break; @@ -1675,7 +1675,7 @@ //Check operand(0) == Not if (N.getOperand(0).getOpcode() == ISD::XOR && N.getOperand(0).getOperand(1).getOpcode() == ISD::Constant && - cast(N.getOperand(0).getOperand(1))->getSignExtended() + cast(N.getOperand(0).getOperand(1))->getSignExtended() == -1) { switch(opcode) { case ISD::AND: Opc = Alpha::BIC; break; @@ -1730,8 +1730,8 @@ case ISD::SHL: Opc = Alpha::SL; break; case ISD::SRL: Opc = Alpha::SRL; break; case ISD::SRA: Opc = Alpha::SRA; break; - case ISD::MUL: - Opc = isFP ? (DestType == MVT::f64 ? Alpha::MULT : Alpha::MULS) + case ISD::MUL: + Opc = isFP ? (DestType == MVT::f64 ? Alpha::MULT : Alpha::MULS) : Alpha::MULQ; break; }; @@ -1807,7 +1807,7 @@ } else if((CSD = dyn_cast(N.getOperand(1))) && (int64_t)CSD->getValue() >= 255 && - (int64_t)CSD->getValue() <= 0) + (int64_t)CSD->getValue() <= 0) { //inverted imm add/sub Opc = isAdd ? Alpha::SUBQi : Alpha::ADDQi; Tmp1 = SelectExpr(N.getOperand(0)); @@ -1903,7 +1903,7 @@ } Tmp1 = SelectExpr(N.getOperand(0)); Tmp2 = SelectExpr(N.getOperand(1)); - SDOperand Addr = + SDOperand Addr = ISelDAG->getExternalSymbol(opstr, AlphaLowering.getPointerTy()); Tmp3 = SelectExpr(Addr); //set up regs explicitly (helps Reg alloc) @@ -1947,7 +1947,7 @@ if (SetCC && !MVT::isInteger(SetCC->getOperand(0).getValueType())) { //FP Setcc -> Select yay! - + //for a cmp b: c = a - b; //a = b: c = 0 //a < b: c < 0 @@ -2000,7 +2000,7 @@ // // Get the condition into the zero flag. // BuildMI(BB, Alpha::FCMOVEQ, 3, Result).addReg(TV).addReg(FV).addReg(Tmp4); return Result; - } + } } else { //FIXME: look at parent to decide if intCC can be folded, or if setCC(FP) //and can save stack use @@ -2116,7 +2116,7 @@ //re-get the val since we are going to mem anyway val = (int64_t)cast(N)->getValue(); MachineConstantPool *CP = BB->getParent()->getConstantPool(); - ConstantUInt *C = + ConstantUInt *C = ConstantUInt::get(Type::getPrimitiveType(Type::ULongTyID) , val); unsigned CPI = CP->getConstantPoolIndex(C); AlphaLowering.restoreGP(BB); @@ -2317,8 +2317,8 @@ } int i, j, k; - if (EnableAlphaLSMark) - getValueInfo(cast(N.getOperand(3))->getValue(), + if (EnableAlphaLSMark) + getValueInfo(cast(N.getOperand(3))->getValue(), i, j, k); GlobalAddressSDNode *GASD = dyn_cast(Address); Index: llvm/lib/Target/Alpha/AlphaJITInfo.cpp diff -u llvm/lib/Target/Alpha/AlphaJITInfo.cpp:1.2 llvm/lib/Target/Alpha/AlphaJITInfo.cpp:1.3 --- llvm/lib/Target/Alpha/AlphaJITInfo.cpp:1.2 Fri Jul 22 16:00:30 2005 +++ llvm/lib/Target/Alpha/AlphaJITInfo.cpp Wed Jul 27 01:12:33 2005 @@ -59,7 +59,7 @@ void* CameFromOrig = (void*)*(oldsp - 2); void* Target = JITCompilerFunction(CameFromStub); - + //rewrite the stub to an unconditional branch EmitBranchToAt(CameFromStub, Target, false); @@ -256,7 +256,7 @@ case 0x08: //LDA assert(gpdistmap[make_pair(Function, MR->getConstantVal())] && "LDAg without seeing LDAHg"); - idx = &GOTBase[GOToffset * 8] - + idx = &GOTBase[GOToffset * 8] - (unsigned char*)gpdistmap[make_pair(Function, MR->getConstantVal())]; idx = getLower16(idx); DEBUG(std::cerr << "LDA: " << idx << "\n"); From jeffc at jolt-lang.org Wed Jul 27 01:12:58 2005 From: jeffc at jolt-lang.org (Jeff Cohen) Date: Wed, 27 Jul 2005 01:12:58 -0500 Subject: [llvm-commits] CVS: llvm/lib/Target/X86/X86ATTAsmPrinter.cpp X86AsmPrinter.cpp X86ISelPattern.cpp X86ISelSimple.cpp X86PeepholeOpt.cpp X86RegisterInfo.cpp X86Subtarget.cpp X86TargetMachine.cpp Message-ID: <200507270612.BAA32281@zion.cs.uiuc.edu> Changes in directory llvm/lib/Target/X86: X86ATTAsmPrinter.cpp updated: 1.7 -> 1.8 X86AsmPrinter.cpp updated: 1.144 -> 1.145 X86ISelPattern.cpp updated: 1.154 -> 1.155 X86ISelSimple.cpp updated: 1.320 -> 1.321 X86PeepholeOpt.cpp updated: 1.39 -> 1.40 X86RegisterInfo.cpp updated: 1.106 -> 1.107 X86Subtarget.cpp updated: 1.3 -> 1.4 X86TargetMachine.cpp updated: 1.83 -> 1.84 --- Log message: Eliminate all remaining tabs and trailing spaces. --- Diffs of the changes: (+72 -72) X86ATTAsmPrinter.cpp | 2 - X86AsmPrinter.cpp | 16 ++++----- X86ISelPattern.cpp | 86 +++++++++++++++++++++++++-------------------------- X86ISelSimple.cpp | 2 - X86PeepholeOpt.cpp | 22 ++++++------- X86RegisterInfo.cpp | 8 ++-- X86Subtarget.cpp | 6 +-- X86TargetMachine.cpp | 2 - 8 files changed, 72 insertions(+), 72 deletions(-) Index: llvm/lib/Target/X86/X86ATTAsmPrinter.cpp diff -u llvm/lib/Target/X86/X86ATTAsmPrinter.cpp:1.7 llvm/lib/Target/X86/X86ATTAsmPrinter.cpp:1.8 --- llvm/lib/Target/X86/X86ATTAsmPrinter.cpp:1.7 Thu Jul 14 17:52:25 2005 +++ llvm/lib/Target/X86/X86ATTAsmPrinter.cpp Wed Jul 27 01:12:34 2005 @@ -102,7 +102,7 @@ FnStubs.insert(Name); O << "L" << Name << "$stub"; } else if (GV->hasLinkOnceLinkage()) { - // Link-once, External, or Weakly-linked global variables need + // Link-once, External, or Weakly-linked global variables need // non-lazily-resolved stubs LinkOnceStubs.insert(Name); O << "L" << Name << "$non_lazy_ptr"; Index: llvm/lib/Target/X86/X86AsmPrinter.cpp diff -u llvm/lib/Target/X86/X86AsmPrinter.cpp:1.144 llvm/lib/Target/X86/X86AsmPrinter.cpp:1.145 --- llvm/lib/Target/X86/X86AsmPrinter.cpp:1.144 Fri Jul 15 20:59:47 2005 +++ llvm/lib/Target/X86/X86AsmPrinter.cpp Wed Jul 27 01:12:34 2005 @@ -25,7 +25,7 @@ using namespace llvm; using namespace x86; -Statistic<> llvm::x86::EmittedInsts("asm-printer", +Statistic<> llvm::x86::EmittedInsts("asm-printer", "Number of machine instrs printed"); enum AsmWriterFlavorTy { att, intel }; @@ -58,7 +58,7 @@ leadingUnderscore = false; #endif } - + if (leadingUnderscore || forCygwin || forDarwin) GlobalPrefix = "_"; @@ -67,7 +67,7 @@ Data64bitsDirective = 0; // we can't emit a 64-bit unit ZeroDirective = "\t.space\t"; // ".space N" emits N zeros. } - + return AsmPrinter::doInitialization(M); } @@ -107,7 +107,7 @@ Constant *C = I->getInitializer(); unsigned Size = TD.getTypeSize(C->getType()); unsigned Align = TD.getTypeAlignmentShift(C->getType()); - + if (C->isNullValue() && (I->hasLinkOnceLinkage() || I->hasInternalLinkage() || I->hasWeakLinkage() /* FIXME: Verify correct */)) { @@ -116,7 +116,7 @@ O << "\t.local " << name << "\n"; if (forDarwin && I->hasInternalLinkage()) O << "\t.lcomm " << name << "," << Size << "," << Align; - else + else O << "\t.comm " << name << "," << Size; if (!forCygwin && !forDarwin) O << "," << (1 << Align); @@ -147,7 +147,7 @@ SwitchSection(O, CurSection, ".data"); break; } - + emitAlignment(Align); if (!forCygwin && !forDarwin) { O << "\t.type " << name << ", at object\n"; @@ -161,7 +161,7 @@ emitGlobalConstant(C); } } - + if (forDarwin) { // Output stubs for external global variables if (GVStubs.begin() != GVStubs.end()) @@ -191,7 +191,7 @@ } O << "\n"; - + // Output stubs for link-once variables if (LinkOnceStubs.begin() != LinkOnceStubs.end()) O << ".data\n.align 2\n"; Index: llvm/lib/Target/X86/X86ISelPattern.cpp diff -u llvm/lib/Target/X86/X86ISelPattern.cpp:1.154 llvm/lib/Target/X86/X86ISelPattern.cpp:1.155 --- llvm/lib/Target/X86/X86ISelPattern.cpp:1.154 Mon Jul 18 23:52:44 2005 +++ llvm/lib/Target/X86/X86ISelPattern.cpp Wed Jul 27 01:12:34 2005 @@ -105,7 +105,7 @@ addRegisterClass(MVT::i8, X86::R8RegisterClass); addRegisterClass(MVT::i16, X86::R16RegisterClass); addRegisterClass(MVT::i32, X86::R32RegisterClass); - + // Promote all UINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have this // operation. setOperationAction(ISD::UINT_TO_FP , MVT::i1 , Promote); @@ -117,10 +117,10 @@ // this operation. setOperationAction(ISD::SINT_TO_FP , MVT::i1 , Promote); setOperationAction(ISD::SINT_TO_FP , MVT::i8 , Promote); - + // We can handle SINT_TO_FP from i64 even though i64 isn't legal. setOperationAction(ISD::SINT_TO_FP , MVT::i64 , Custom); - + setOperationAction(ISD::BRCONDTWOWAY , MVT::Other, Expand); setOperationAction(ISD::MEMMOVE , MVT::Other, Expand); setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16 , Expand); @@ -137,7 +137,7 @@ setOperationAction(ISD::CTPOP , MVT::i32 , Expand); setOperationAction(ISD::CTTZ , MVT::i32 , Expand); setOperationAction(ISD::CTLZ , MVT::i32 , Expand); - + setOperationAction(ISD::READIO , MVT::i1 , Expand); setOperationAction(ISD::READIO , MVT::i8 , Expand); setOperationAction(ISD::READIO , MVT::i16 , Expand); @@ -146,16 +146,16 @@ setOperationAction(ISD::WRITEIO , MVT::i8 , Expand); setOperationAction(ISD::WRITEIO , MVT::i16 , Expand); setOperationAction(ISD::WRITEIO , MVT::i32 , Expand); - + // These should be promoted to a larger select which is supported. setOperationAction(ISD::SELECT , MVT::i1 , Promote); setOperationAction(ISD::SELECT , MVT::i8 , Promote); - + if (X86ScalarSSE) { // Set up the FP register classes. addRegisterClass(MVT::f32, X86::RXMMRegisterClass); addRegisterClass(MVT::f64, X86::RXMMRegisterClass); - + // SSE has no load+extend ops setOperationAction(ISD::EXTLOAD, MVT::f32, Expand); setOperationAction(ISD::ZEXTLOAD, MVT::f32, Expand); @@ -177,12 +177,12 @@ } else { // Set up the FP register classes. addRegisterClass(MVT::f64, X86::RFPRegisterClass); - + if (!UnsafeFPMath) { setOperationAction(ISD::FSIN , MVT::f64 , Expand); setOperationAction(ISD::FCOS , MVT::f64 , Expand); } - + addLegalFPImmediate(+0.0); // FLD0 addLegalFPImmediate(+1.0); // FLD1 addLegalFPImmediate(-0.0); // FLD0/FCHS @@ -195,7 +195,7 @@ maxStoresPerMemMove = 8; // For %llvm.memmove -> sequence of stores allowUnalignedStores = true; // x86 supports it! } - + // Return the number of bytes that a function should pop when it returns (in // addition to the space used by the return address). // @@ -217,7 +217,7 @@ /// LowerCallTo - This hook lowers an abstract call to a function into an /// actual call. virtual std::pair - LowerCallTo(SDOperand Chain, const Type *RetTy, bool isVarArg, unsigned CC, + LowerCallTo(SDOperand Chain, const Type *RetTy, bool isVarArg, unsigned CC, bool isTailCall, SDOperand Callee, ArgListTy &Args, SelectionDAG &DAG); @@ -226,7 +226,7 @@ virtual std::pair LowerVAArg(SDOperand Chain, SDOperand VAListP, Value *VAListV, const Type *ArgTy, SelectionDAG &DAG); - + virtual std::pair LowerFrameReturnAddress(bool isFrameAddr, SDOperand Chain, unsigned Depth, SelectionDAG &DAG); @@ -240,7 +240,7 @@ LowerCCCCallTo(SDOperand Chain, const Type *RetTy, bool isVarArg, bool isTailCall, SDOperand Callee, ArgListTy &Args, SelectionDAG &DAG); - + // Fast Calling Convention implementation. std::vector LowerFastCCArguments(Function &F, SelectionDAG &DAG); std::pair @@ -259,7 +259,7 @@ std::pair X86TargetLowering::LowerCallTo(SDOperand Chain, const Type *RetTy, bool isVarArg, unsigned CallingConv, - bool isTailCall, + bool isTailCall, SDOperand Callee, ArgListTy &Args, SelectionDAG &DAG) { assert((!isVarArg || CallingConv == CallingConv::C) && @@ -579,7 +579,7 @@ unsigned ArgIncrement = 4; unsigned ObjSize = 0; SDOperand ArgValue; - + switch (ObjectVT) { default: assert(0 && "Unhandled argument type!"); case MVT::i1: @@ -1025,8 +1025,8 @@ /// TheDAG - The DAG being selected during Select* operations. SelectionDAG *TheDAG; - - /// Subtarget - Keep a pointer to the X86Subtarget around so that we can + + /// Subtarget - Keep a pointer to the X86Subtarget around so that we can /// make the right decision when generating code for different targets. const X86Subtarget *Subtarget; public: @@ -1353,7 +1353,7 @@ // the value at address GV, not the value of GV itself. This means that // the GlobalAddress must be in the base or index register of the address, // not the GV offset field. - if (Subtarget->getIndirectExternAndWeakGlobals() && + if (Subtarget->getIndirectExternAndWeakGlobals() && (GV->hasWeakLinkage() || GV->isExternal())) { break; } else { @@ -1788,7 +1788,7 @@ // There's no SSE equivalent of FCMOVE. In some cases we can fake it up, in // Others we will have to do the PowerPC thing and generate an MBB for the // true and false values and select between them with a PHI. - if (X86ScalarSSE && (SVT == MVT::f32 || SVT == MVT::f64)) { + if (X86ScalarSSE && (SVT == MVT::f32 || SVT == MVT::f64)) { if (0 && CondCode != NOT_SET) { // FIXME: check for min and max } else { @@ -1846,7 +1846,7 @@ case MVT::f64: Opc = CMOVTABFP[CondCode]; break; } } - + // Finally, if we weren't able to fold this, just emit the condition and test // it. if (CondCode == NOT_SET || Opc == 0) { @@ -2186,12 +2186,12 @@ Node->dump(); assert(0 && "Node not handled!\n"); case ISD::FP_EXTEND: - assert(X86ScalarSSE && "Scalar SSE FP must be enabled to use f32"); + assert(X86ScalarSSE && "Scalar SSE FP must be enabled to use f32"); Tmp1 = SelectExpr(N.getOperand(0)); BuildMI(BB, X86::CVTSS2SDrr, 1, Result).addReg(Tmp1); return Result; case ISD::FP_ROUND: - assert(X86ScalarSSE && "Scalar SSE FP must be enabled to use f32"); + assert(X86ScalarSSE && "Scalar SSE FP must be enabled to use f32"); Tmp1 = SelectExpr(N.getOperand(0)); BuildMI(BB, X86::CVTSD2SSrr, 1, Result).addReg(Tmp1); return Result; @@ -2216,7 +2216,7 @@ BuildMI(BB, X86::MOV32rr, 1, Result).addReg(cast(Node)->getReg()); return Result; - } + } case ISD::FrameIndex: Tmp1 = cast(N)->getIndex(); @@ -2266,7 +2266,7 @@ GlobalValue *GV = cast(N)->getGlobal(); // For Darwin, external and weak symbols are indirect, so we want to load // the value at address GV, not the value of GV itself. - if (Subtarget->getIndirectExternAndWeakGlobals() && + if (Subtarget->getIndirectExternAndWeakGlobals() && (GV->hasWeakLinkage() || GV->isExternal())) { BuildMI(BB, X86::MOV32rm, 4, Result).addReg(0).addZImm(1).addReg(0) .addGlobalAddress(GV, false, 0); @@ -2383,7 +2383,7 @@ BuildMI(BB, Opc, 1, Result).addReg(Tmp1); return Result; } - + ContainsFPCode = true; // Spill the integer to memory and reload it from there. @@ -2423,7 +2423,7 @@ abort(); } return Result; - } + } // Change the floating point control register to use "round towards zero" // mode when truncating to an integer value. @@ -2836,8 +2836,8 @@ case MVT::i32: Opc = 7; break; case MVT::f32: Opc = 8; break; // For F64, handle promoted load operations (from F32) as well! - case MVT::f64: - assert((!X86ScalarSSE || Op1.getOpcode() == ISD::LOAD) && + case MVT::f64: + assert((!X86ScalarSSE || Op1.getOpcode() == ISD::LOAD) && "SSE load should have been promoted"); Opc = Op1.getOpcode() == ISD::LOAD ? 9 : 8; break; } @@ -3273,12 +3273,12 @@ case MVT::i16: Opc = X86::MOV16rm; break; case MVT::i32: Opc = X86::MOV32rm; break; case MVT::f32: Opc = X86::MOVSSrm; break; - case MVT::f64: + case MVT::f64: if (X86ScalarSSE) { Opc = X86::MOVSDrm; } else { Opc = X86::FLD64m; - ContainsFPCode = true; + ContainsFPCode = true; } break; } @@ -3497,7 +3497,7 @@ unsigned RegOp1 = SelectExpr(N.getOperand(4)); unsigned RegOp2 = Node->getNumOperands() > 5 ? SelectExpr(N.getOperand(5)) : 0; - + switch (N.getOperand(4).getValueType()) { default: assert(0 && "Bad thing to pass in regs"); case MVT::i1: @@ -3595,7 +3595,7 @@ assert(0 && "readport already emitted!?"); } else Result = ExprMap[N.getValue(0)] = MakeReg(N.getValue(0).getValueType()); - + Select(Node->getOperand(0)); // Select the chain. // If the port is a single-byte constant, use the immediate form. @@ -3640,7 +3640,7 @@ std::cerr << "Cannot do input on this data type"; exit(1); } - + } return 0; @@ -4066,7 +4066,7 @@ RegOp1 = SelectExpr(TailCallNode->getOperand(4)); if (TailCallNode->getNumOperands() > 5) RegOp2 = SelectExpr(TailCallNode->getOperand(5)); - + switch (TailCallNode->getOperand(4).getValueType()) { default: assert(0 && "Bad thing to pass in regs"); case MVT::i1: @@ -4167,12 +4167,12 @@ case MVT::i16: Opc = X86::MOV16rr; break; case MVT::i32: Opc = X86::MOV32rr; break; case MVT::f32: Opc = X86::MOVAPSrr; break; - case MVT::f64: + case MVT::f64: if (X86ScalarSSE) { Opc = X86::MOVAPDrr; } else { - Opc = X86::FpMOV; - ContainsFPCode = true; + Opc = X86::FpMOV; + ContainsFPCode = true; } break; } @@ -4191,8 +4191,8 @@ assert(0 && "Unknown return instruction!"); case 3: assert(N.getOperand(1).getValueType() == MVT::i32 && - N.getOperand(2).getValueType() == MVT::i32 && - "Unknown two-register value!"); + N.getOperand(2).getValueType() == MVT::i32 && + "Unknown two-register value!"); if (getRegPressure(N.getOperand(1)) > getRegPressure(N.getOperand(2))) { Tmp1 = SelectExpr(N.getOperand(1)); Tmp2 = SelectExpr(N.getOperand(2)); @@ -4224,7 +4224,7 @@ addFrameReference(BuildMI(BB, X86::MOVSSmr, 5), FrameIdx).addReg(Tmp1); addFrameReference(BuildMI(BB, X86::FLD32m, 4, X86::FP0), FrameIdx); BuildMI(BB, X86::FpSETRESULT, 1).addReg(X86::FP0); - ContainsFPCode = true; + ContainsFPCode = true; } else { assert(0 && "MVT::f32 only legal with scalar sse fp"); abort(); @@ -4239,7 +4239,7 @@ addFrameReference(BuildMI(BB, X86::MOVSDmr, 5), FrameIdx).addReg(Tmp1); addFrameReference(BuildMI(BB, X86::FLD64m, 4, X86::FP0), FrameIdx); BuildMI(BB, X86::FpSETRESULT, 1).addReg(X86::FP0); - ContainsFPCode = true; + ContainsFPCode = true; } else { BuildMI(BB, X86::FpSETRESULT, 1).addReg(Tmp1); } @@ -4367,7 +4367,7 @@ default: assert(0 && "Cannot truncstore this type!"); case MVT::i1: Opc = X86::MOV8mr; break; case MVT::f32: - assert(!X86ScalarSSE && "Cannot truncstore scalar SSE regs"); + assert(!X86ScalarSSE && "Cannot truncstore scalar SSE regs"); Opc = X86::FST32m; break; } @@ -4426,7 +4426,7 @@ GlobalValue *GV = GA->getGlobal(); // For Darwin, external and weak symbols are indirect, so we want to load // the value at address GV, not the value of GV itself. - if (Subtarget->getIndirectExternAndWeakGlobals() && + if (Subtarget->getIndirectExternAndWeakGlobals() && (GV->hasWeakLinkage() || GV->isExternal())) { Tmp1 = MakeReg(MVT::i32); BuildMI(BB, X86::MOV32rm, 4, Tmp1).addReg(0).addZImm(1).addReg(0) Index: llvm/lib/Target/X86/X86ISelSimple.cpp diff -u llvm/lib/Target/X86/X86ISelSimple.cpp:1.320 llvm/lib/Target/X86/X86ISelSimple.cpp:1.321 --- llvm/lib/Target/X86/X86ISelSimple.cpp:1.320 Sat Jun 18 13:34:52 2005 +++ llvm/lib/Target/X86/X86ISelSimple.cpp Wed Jul 27 01:12:34 2005 @@ -3510,7 +3510,7 @@ unsigned FltAlign = TM.getTargetData().getFloatAlignment(); int FrameIdx = F->getFrameInfo()->CreateStackObject(4, FltAlign); addFrameReference(BuildMI(*BB, IP, X86::FST32m, 5), - FrameIdx).addReg(SrcReg); + FrameIdx).addReg(SrcReg); addFrameReference(BuildMI(*BB, IP, X86::FLD32m, 5, DestReg), FrameIdx); } } else if (SrcClass == cLong) { Index: llvm/lib/Target/X86/X86PeepholeOpt.cpp diff -u llvm/lib/Target/X86/X86PeepholeOpt.cpp:1.39 llvm/lib/Target/X86/X86PeepholeOpt.cpp:1.40 --- llvm/lib/Target/X86/X86PeepholeOpt.cpp:1.39 Thu Apr 21 18:38:14 2005 +++ llvm/lib/Target/X86/X86PeepholeOpt.cpp Wed Jul 27 01:12:34 2005 @@ -30,7 +30,7 @@ virtual bool runOnMachineFunction(MachineFunction &MF); bool PeepholeOptimize(MachineBasicBlock &MBB, - MachineBasicBlock::iterator &I); + MachineBasicBlock::iterator &I); virtual const char *getPassName() const { return "X86 Peephole Optimizer"; } }; @@ -44,17 +44,17 @@ for (MachineFunction::iterator BI = MF.begin(), E = MF.end(); BI != E; ++BI) for (MachineBasicBlock::iterator I = BI->begin(); I != BI->end(); ) if (PeepholeOptimize(*BI, I)) { - Changed = true; + Changed = true; ++NumPHOpts; } else - ++I; + ++I; return Changed; } bool PH::PeepholeOptimize(MachineBasicBlock &MBB, - MachineBasicBlock::iterator &I) { + MachineBasicBlock::iterator &I) { assert(I != MBB.end()); MachineBasicBlock::iterator NextI = next(I); @@ -218,20 +218,20 @@ if (MI->getOperand(1).isImmediate()) { // avoid mov EAX, int Val = MI->getOperand(1).getImmedValue(); if (Val == 0) { // mov EAX, 0 -> xor EAX, EAX - static const unsigned Opcode[] ={X86::XOR8rr,X86::XOR16rr,X86::XOR32rr}; - unsigned Reg = MI->getOperand(0).getReg(); - I = MBB.insert(MBB.erase(I), + static const unsigned Opcode[] ={X86::XOR8rr,X86::XOR16rr,X86::XOR32rr}; + unsigned Reg = MI->getOperand(0).getReg(); + I = MBB.insert(MBB.erase(I), BuildMI(Opcode[Size], 2, Reg).addReg(Reg).addReg(Reg)); - return true; + return true; } else if (Val == -1) { // mov EAX, -1 -> or EAX, -1 - // TODO: 'or Reg, -1' has a smaller encoding than 'mov Reg, -1' + // TODO: 'or Reg, -1' has a smaller encoding than 'mov Reg, -1' } } return false; #endif case X86::BSWAP32r: // Change bswap EAX, bswap EAX into nothing if (Next->getOpcode() == X86::BSWAP32r && - MI->getOperand(0).getReg() == Next->getOperand(0).getReg()) { + MI->getOperand(0).getReg() == Next->getOperand(0).getReg()) { I = MBB.erase(MBB.erase(I)); return true; } @@ -314,7 +314,7 @@ virtual bool runOnMachineFunction(MachineFunction &MF); bool PeepholeOptimize(MachineBasicBlock &MBB, - MachineBasicBlock::iterator &I); + MachineBasicBlock::iterator &I); virtual const char *getPassName() const { return "X86 SSA-based Peephole Optimizer"; Index: llvm/lib/Target/X86/X86RegisterInfo.cpp diff -u llvm/lib/Target/X86/X86RegisterInfo.cpp:1.106 llvm/lib/Target/X86/X86RegisterInfo.cpp:1.107 --- llvm/lib/Target/X86/X86RegisterInfo.cpp:1.106 Wed Jul 6 13:59:04 2005 +++ llvm/lib/Target/X86/X86RegisterInfo.cpp Wed Jul 27 01:12:34 2005 @@ -387,10 +387,10 @@ MachineInstr *New = 0; if (Old->getOpcode() == X86::ADJCALLSTACKDOWN) { - New=BuildMI(X86::SUB32ri, 1, X86::ESP, MachineOperand::UseAndDef) + New=BuildMI(X86::SUB32ri, 1, X86::ESP, MachineOperand::UseAndDef) .addZImm(Amount); } else { - assert(Old->getOpcode() == X86::ADJCALLSTACKUP); + assert(Old->getOpcode() == X86::ADJCALLSTACKUP); // factor out the amount the callee already popped. unsigned CalleeAmt = Old->getOperand(1).getImmedValue(); Amount -= CalleeAmt; @@ -407,7 +407,7 @@ // something off the stack pointer, add it back. We do this until we have // more advanced stack pointer tracking ability. if (unsigned CalleeAmt = I->getOperand(1).getImmedValue()) { - MachineInstr *New = + MachineInstr *New = BuildMI(X86::SUB32ri, 1, X86::ESP, MachineOperand::UseAndDef).addZImm(CalleeAmt); MBB.insert(I, New); @@ -475,7 +475,7 @@ // Save EBP into the appropriate stack slot... MI = addRegOffset(BuildMI(X86::MOV32mr, 5), // mov [ESP-], EBP - X86::ESP, EBPOffset+NumBytes).addReg(X86::EBP); + X86::ESP, EBPOffset+NumBytes).addReg(X86::EBP); MBB.insert(MBBI, MI); // Update EBP with the new base value... Index: llvm/lib/Target/X86/X86Subtarget.cpp diff -u llvm/lib/Target/X86/X86Subtarget.cpp:1.3 llvm/lib/Target/X86/X86Subtarget.cpp:1.4 --- llvm/lib/Target/X86/X86Subtarget.cpp:1.3 Mon Jul 11 21:41:19 2005 +++ llvm/lib/Target/X86/X86Subtarget.cpp Wed Jul 27 01:12:34 2005 @@ -15,8 +15,8 @@ #include "llvm/Module.h" using namespace llvm; -X86Subtarget::X86Subtarget(const Module &M) - : TargetSubtarget(), stackAlignment(8), +X86Subtarget::X86Subtarget(const Module &M) + : TargetSubtarget(), stackAlignment(8), indirectExternAndWeakGlobals(false), asmDarwinLinkerStubs(false), asmLeadingUnderscore(false), asmAlignmentIsInBytes(false), asmPrintDotLocalConstants(false), asmPrintDotLCommConstants(false), @@ -25,7 +25,7 @@ bool forCygwin = false; bool forDarwin = false; bool forWindows = false; - + // Set the boolean corresponding to the current target triple, or the default // if one cannot be determined, to true. const std::string& TT = M.getTargetTriple(); Index: llvm/lib/Target/X86/X86TargetMachine.cpp diff -u llvm/lib/Target/X86/X86TargetMachine.cpp:1.83 llvm/lib/Target/X86/X86TargetMachine.cpp:1.84 --- llvm/lib/Target/X86/X86TargetMachine.cpp:1.83 Mon Jul 11 20:41:54 2005 +++ llvm/lib/Target/X86/X86TargetMachine.cpp Wed Jul 27 01:12:34 2005 @@ -105,7 +105,7 @@ // does to emit statically compiled machine code. bool X86TargetMachine::addPassesToEmitFile(PassManager &PM, std::ostream &Out, CodeGenFileType FileType) { - if (FileType != TargetMachine::AssemblyFile && + if (FileType != TargetMachine::AssemblyFile && FileType != TargetMachine::ObjectFile) return true; // FIXME: Implement efficient support for garbage collection intrinsics. From jeffc at jolt-lang.org Wed Jul 27 01:12:58 2005 From: jeffc at jolt-lang.org (Jeff Cohen) Date: Wed, 27 Jul 2005 01:12:58 -0500 Subject: [llvm-commits] CVS: llvm/lib/Transforms/IPO/PruneEH.cpp SimplifyLibCalls.cpp Message-ID: <200507270612.BAA32262@zion.cs.uiuc.edu> Changes in directory llvm/lib/Transforms/IPO: PruneEH.cpp updated: 1.22 -> 1.23 SimplifyLibCalls.cpp updated: 1.45 -> 1.46 --- Log message: Eliminate all remaining tabs and trailing spaces. --- Diffs of the changes: (+157 -157) PruneEH.cpp | 10 - SimplifyLibCalls.cpp | 304 +++++++++++++++++++++++++-------------------------- 2 files changed, 157 insertions(+), 157 deletions(-) Index: llvm/lib/Transforms/IPO/PruneEH.cpp diff -u llvm/lib/Transforms/IPO/PruneEH.cpp:1.22 llvm/lib/Transforms/IPO/PruneEH.cpp:1.23 --- llvm/lib/Transforms/IPO/PruneEH.cpp:1.22 Sun May 8 20:05:50 2005 +++ llvm/lib/Transforms/IPO/PruneEH.cpp Wed Jul 27 01:12:34 2005 @@ -149,24 +149,24 @@ II->op_end()), Name, II); Call->setCallingConv(II->getCallingConv()); - + // Anything that used the value produced by the invoke instruction // now uses the value produced by the call instruction. II->replaceAllUsesWith(Call); BasicBlock *UnwindBlock = II->getUnwindDest(); UnwindBlock->removePredecessor(II->getParent()); - + // Insert a branch to the normal destination right before the // invoke. new BranchInst(II->getNormalDest(), II); - + // Finally, delete the invoke instruction! BB->getInstList().pop_back(); // If the unwind block is now dead, nuke it. if (pred_begin(UnwindBlock) == pred_end(UnwindBlock)) DeleteBasicBlock(UnwindBlock); // Delete the new BB. - + ++NumRemoved; MadeChange = true; } @@ -221,6 +221,6 @@ for (unsigned i = 0, e = Succs.size(); i != e; ++i) Succs[i]->removePredecessor(BB); - + BB->eraseFromParent(); } Index: llvm/lib/Transforms/IPO/SimplifyLibCalls.cpp diff -u llvm/lib/Transforms/IPO/SimplifyLibCalls.cpp:1.45 llvm/lib/Transforms/IPO/SimplifyLibCalls.cpp:1.46 --- llvm/lib/Transforms/IPO/SimplifyLibCalls.cpp:1.45 Wed Jun 29 10:57:50 2005 +++ llvm/lib/Transforms/IPO/SimplifyLibCalls.cpp Wed Jul 27 01:12:34 2005 @@ -2,18 +2,18 @@ // // The LLVM Compiler Infrastructure // -// This file was developed by Reid Spencer and is distributed under the +// This file was developed by Reid Spencer and is distributed under the // University of Illinois Open Source License. See LICENSE.TXT for details. // //===----------------------------------------------------------------------===// // -// This file implements a module pass that applies a variety of small -// optimizations for calls to specific well-known function calls (e.g. runtime -// library functions). For example, a call to the function "exit(3)" that +// This file implements a module pass that applies a variety of small +// optimizations for calls to specific well-known function calls (e.g. runtime +// library functions). For example, a call to the function "exit(3)" that // occurs within the main() function can be transformed into a simple "return 3" -// instruction. Any optimization that takes this form (replace call to library -// function with simpler code that provides the same result) belongs in this -// file. +// instruction. Any optimization that takes this form (replace call to library +// function with simpler code that provides the same result) belongs in this +// file. // //===----------------------------------------------------------------------===// @@ -35,7 +35,7 @@ /// This statistic keeps track of the total number of library calls that have /// been simplified regardless of which call it is. -Statistic<> SimplifiedLibCalls("simplify-libcalls", +Statistic<> SimplifiedLibCalls("simplify-libcalls", "Total number of library calls simplified"); // Forward declarations @@ -53,21 +53,21 @@ /// corresponds to one library call. The SimplifyLibCalls pass will call the /// ValidateCalledFunction method to ask the optimization if a given Function /// is the kind that the optimization can handle. If the subclass returns true, -/// then SImplifyLibCalls will also call the OptimizeCall method to perform, +/// then SImplifyLibCalls will also call the OptimizeCall method to perform, /// or attempt to perform, the optimization(s) for the library call. Otherwise, /// OptimizeCall won't be called. Subclasses are responsible for providing the /// name of the library call (strlen, strcpy, etc.) to the LibCallOptimization /// constructor. This is used to efficiently select which call instructions to -/// optimize. The criteria for a "lib call" is "anything with well known +/// optimize. The criteria for a "lib call" is "anything with well known /// semantics", typically a library function that is defined by an international -/// standard. Because the semantics are well known, the optimizations can +/// standard. Because the semantics are well known, the optimizations can /// generally short-circuit actually calling the function if there's a simpler /// way (e.g. strlen(X) can be reduced to a constant if X is a constant global). /// @brief Base class for library call optimizations class LibCallOptimization { public: - /// The \p fname argument must be the name of the library function being + /// The \p fname argument must be the name of the library function being /// optimized by the subclass. /// @brief Constructor that registers the optimization. LibCallOptimization(const char* fname, const char* description ) @@ -84,12 +84,12 @@ virtual ~LibCallOptimization() { optlist.erase(func_name); } /// The implementation of this function in subclasses should determine if - /// \p F is suitable for the optimization. This method is called by - /// SimplifyLibCalls::runOnModule to short circuit visiting all the call - /// sites of such a function if that function is not suitable in the first + /// \p F is suitable for the optimization. This method is called by + /// SimplifyLibCalls::runOnModule to short circuit visiting all the call + /// sites of such a function if that function is not suitable in the first /// place. If the called function is suitabe, this method should return true; - /// false, otherwise. This function should also perform any lazy - /// initialization that the LibCallOptimization needs to do, if its to return + /// false, otherwise. This function should also perform any lazy + /// initialization that the LibCallOptimization needs to do, if its to return /// true. This avoids doing initialization until the optimizer is actually /// going to be called upon to do some optimization. /// @brief Determine if the function is suitable for optimization @@ -98,10 +98,10 @@ SimplifyLibCalls& SLC ///< The pass object invoking us ) = 0; - /// The implementations of this function in subclasses is the heart of the - /// SimplifyLibCalls algorithm. Sublcasses of this class implement + /// The implementations of this function in subclasses is the heart of the + /// SimplifyLibCalls algorithm. Sublcasses of this class implement /// OptimizeCall to determine if (a) the conditions are right for optimizing - /// the call and (b) to perform the optimization. If an action is taken + /// the call and (b) to perform the optimization. If an action is taken /// against ci, the subclass is responsible for returning true and ensuring /// that ci is erased from its parent. /// @brief Optimize a call, if possible. @@ -125,15 +125,15 @@ #endif }; -/// This class is an LLVM Pass that applies each of the LibCallOptimization +/// This class is an LLVM Pass that applies each of the LibCallOptimization /// instances to all the call sites in a module, relatively efficiently. The -/// purpose of this pass is to provide optimizations for calls to well-known +/// purpose of this pass is to provide optimizations for calls to well-known /// functions with well-known semantics, such as those in the c library. The -/// class provides the basic infrastructure for handling runOnModule. Whenever /// this pass finds a function call, it asks the appropriate optimizer to +/// class provides the basic infrastructure for handling runOnModule. Whenever /// this pass finds a function call, it asks the appropriate optimizer to /// validate the call (ValidateLibraryCall). If it is validated, then /// the OptimizeCall method is also called. /// @brief A ModulePass for optimizing well-known function calls. -class SimplifyLibCalls : public ModulePass +class SimplifyLibCalls : public ModulePass { public: /// We need some target data for accurate signature details that are @@ -157,8 +157,8 @@ // The call optimizations can be recursive. That is, the optimization might // generate a call to another function which can also be optimized. This way - // we make the LibCallOptimization instances very specific to the case they - // handle. It also means we need to keep running over the function calls in + // we make the LibCallOptimization instances very specific to the case they + // handle. It also means we need to keep running over the function calls in // the module until we don't get any more optimizations possible. bool found_optimization = false; do @@ -167,8 +167,8 @@ for (Module::iterator FI = M.begin(), FE = M.end(); FI != FE; ++FI) { // All the "well-known" functions are external and have external linkage - // because they live in a runtime library somewhere and were (probably) - // not compiled by LLVM. So, we only act on external functions that + // because they live in a runtime library somewhere and were (probably) + // not compiled by LLVM. So, we only act on external functions that // have external linkage and non-empty uses. if (!FI->isExternal() || !FI->hasExternalLinkage() || FI->use_empty()) continue; @@ -183,7 +183,7 @@ continue; // Loop over each of the uses of the function - for (Value::use_iterator UI = FI->use_begin(), UE = FI->use_end(); + for (Value::use_iterator UI = FI->use_begin(), UE = FI->use_end(); UI != UE ; ) { // If the use of the function is a call instruction @@ -222,7 +222,7 @@ std::vector args; args.push_back(Type::IntTy); args.push_back(FILEptr_type); - FunctionType* fputc_type = + FunctionType* fputc_type = FunctionType::get(Type::IntTy, args, false); fputc_func = M->getOrInsertFunction("fputc",fputc_type); } @@ -239,7 +239,7 @@ args.push_back(TD->getIntPtrType()); args.push_back(TD->getIntPtrType()); args.push_back(FILEptr_type); - FunctionType* fwrite_type = + FunctionType* fwrite_type = FunctionType::get(TD->getIntPtrType(), args, false); fwrite_func = M->getOrInsertFunction("fwrite",fwrite_type); } @@ -253,7 +253,7 @@ { std::vector args; args.push_back(Type::DoubleTy); - FunctionType* sqrt_type = + FunctionType* sqrt_type = FunctionType::get(Type::DoubleTy, args, false); sqrt_func = M->getOrInsertFunction("sqrt",sqrt_type); } @@ -268,7 +268,7 @@ std::vector args; args.push_back(PointerType::get(Type::SByteTy)); args.push_back(PointerType::get(Type::SByteTy)); - FunctionType* strcpy_type = + FunctionType* strcpy_type = FunctionType::get(PointerType::get(Type::SByteTy), args, false); strcpy_func = M->getOrInsertFunction("strcpy",strcpy_type); } @@ -282,7 +282,7 @@ { std::vector args; args.push_back(PointerType::get(Type::SByteTy)); - FunctionType* strlen_type = + FunctionType* strlen_type = FunctionType::get(TD->getIntPtrType(), args, false); strlen_func = M->getOrInsertFunction("strlen",strlen_type); } @@ -350,21 +350,21 @@ }; // Register the pass -RegisterOpt +RegisterOpt X("simplify-libcalls","Simplify well-known library calls"); } // anonymous namespace // The only public symbol in this file which just instantiates the pass object -ModulePass *llvm::createSimplifyLibCallsPass() -{ - return new SimplifyLibCalls(); +ModulePass *llvm::createSimplifyLibCallsPass() +{ + return new SimplifyLibCalls(); } // Classes below here, in the anonymous namespace, are all subclasses of the // LibCallOptimization class, each implementing all optimizations possible for a // single well-known library call. Each has a static singleton instance that -// auto registers it into the "optlist" global above. +// auto registers it into the "optlist" global above. namespace { // Forward declare utility functions. @@ -383,7 +383,7 @@ virtual ~ExitInMainOptimization() {} // Make sure the called function looks like exit (int argument, int return - // type, external linkage, not varargs). + // type, external linkage, not varargs). virtual bool ValidateCalledFunction(const Function* f, SimplifyLibCalls& SLC) { if (f->arg_size() >= 1) @@ -396,18 +396,18 @@ { // To be careful, we check that the call to exit is coming from "main", that // main has external linkage, and the return type of main and the argument - // to exit have the same type. + // to exit have the same type. Function *from = ci->getParent()->getParent(); if (from->hasExternalLinkage()) if (from->getReturnType() == ci->getOperand(1)->getType()) if (from->getName() == "main") { - // Okay, time to actually do the optimization. First, get the basic + // Okay, time to actually do the optimization. First, get the basic // block of the call instruction BasicBlock* bb = ci->getParent(); - // Create a return instruction that we'll replace the call with. - // Note that the argument of the return is the argument of the call + // Create a return instruction that we'll replace the call with. + // Note that the argument of the return is the argument of the call // instruction. ReturnInst* ri = new ReturnInst(ci->getOperand(1), ci); @@ -433,10 +433,10 @@ } } ExitInMainOptimizer; -/// This LibCallOptimization will simplify a call to the strcat library -/// function. The simplification is possible only if the string being -/// concatenated is a constant array or a constant expression that results in -/// a constant string. In this case we can replace it with strlen + llvm.memcpy +/// This LibCallOptimization will simplify a call to the strcat library +/// function. The simplification is possible only if the string being +/// concatenated is a constant array or a constant expression that results in +/// a constant string. In this case we can replace it with strlen + llvm.memcpy /// of the constant string. Both of these calls are further reduced, if possible /// on subsequent passes. /// @brief Simplify the strcat library function. @@ -452,10 +452,10 @@ virtual ~StrCatOptimization() {} /// @brief Make sure that the "strcat" function has the right prototype - virtual bool ValidateCalledFunction(const Function* f, SimplifyLibCalls& SLC) + virtual bool ValidateCalledFunction(const Function* f, SimplifyLibCalls& SLC) { if (f->getReturnType() == PointerType::get(Type::SByteTy)) - if (f->arg_size() == 2) + if (f->arg_size() == 2) { Function::const_arg_iterator AI = f->arg_begin(); if (AI++->getType() == PointerType::get(Type::SByteTy)) @@ -476,7 +476,7 @@ Value* dest = ci->getOperand(1); Value* src = ci->getOperand(2); - // Extract the initializer (while making numerous checks) from the + // Extract the initializer (while making numerous checks) from the // source operand of the call to strcat. If we get null back, one of // a variety of checks in get_GVInitializer failed uint64_t len = 0; @@ -495,19 +495,19 @@ // terminator as well. len++; - // We need to find the end of the destination string. That's where the - // memory is to be moved to. We just generate a call to strlen (further - // optimized in another pass). Note that the SLC.get_strlen() call + // We need to find the end of the destination string. That's where the + // memory is to be moved to. We just generate a call to strlen (further + // optimized in another pass). Note that the SLC.get_strlen() call // caches the Function* for us. - CallInst* strlen_inst = + CallInst* strlen_inst = new CallInst(SLC.get_strlen(), dest, dest->getName()+".len",ci); - // Now that we have the destination's length, we must index into the + // Now that we have the destination's length, we must index into the // destination's pointer to get the actual memcpy destination (end of // the string .. we're concatenating). std::vector idx; idx.push_back(strlen_inst); - GetElementPtrInst* gep = + GetElementPtrInst* gep = new GetElementPtrInst(dest,idx,dest->getName()+".indexed",ci); // We have enough information to now generate the memcpy call to @@ -519,8 +519,8 @@ vals.push_back(ConstantUInt::get(Type::UIntTy,1)); // alignment new CallInst(SLC.get_memcpy(), vals, "", ci); - // Finally, substitute the first operand of the strcat call for the - // strcat call itself since strcat returns its first operand; and, + // Finally, substitute the first operand of the strcat call for the + // strcat call itself since strcat returns its first operand; and, // kill the strcat CallInst. ci->replaceAllUsesWith(dest); ci->eraseFromParent(); @@ -528,7 +528,7 @@ } } StrCatOptimizer; -/// This LibCallOptimization will simplify a call to the strchr library +/// This LibCallOptimization will simplify a call to the strchr library /// function. It optimizes out cases where the arguments are both constant /// and the result can be determined statically. /// @brief Simplify the strcmp library function. @@ -540,9 +540,9 @@ virtual ~StrChrOptimization() {} /// @brief Make sure that the "strchr" function has the right prototype - virtual bool ValidateCalledFunction(const Function* f, SimplifyLibCalls& SLC) + virtual bool ValidateCalledFunction(const Function* f, SimplifyLibCalls& SLC) { - if (f->getReturnType() == PointerType::get(Type::SByteTy) && + if (f->getReturnType() == PointerType::get(Type::SByteTy) && f->arg_size() == 2) return true; return false; @@ -620,7 +620,7 @@ } } StrChrOptimizer; -/// This LibCallOptimization will simplify a call to the strcmp library +/// This LibCallOptimization will simplify a call to the strcmp library /// function. It optimizes out cases where one or both arguments are constant /// and the result can be determined statically. /// @brief Simplify the strcmp library function. @@ -632,7 +632,7 @@ virtual ~StrCmpOptimization() {} /// @brief Make sure that the "strcmp" function has the right prototype - virtual bool ValidateCalledFunction(const Function* f, SimplifyLibCalls& SLC) + virtual bool ValidateCalledFunction(const Function* f, SimplifyLibCalls& SLC) { if (f->getReturnType() == Type::IntTy && f->arg_size() == 2) return true; @@ -644,7 +644,7 @@ { // First, check to see if src and destination are the same. If they are, // then the optimization is to replace the CallInst with a constant 0 - // because the call is a no-op. + // because the call is a no-op. Value* s1 = ci->getOperand(1); Value* s2 = ci->getOperand(2); if (s1 == s2) @@ -664,9 +664,9 @@ if (len_1 == 0) { // strcmp("",x) -> *x - LoadInst* load = + LoadInst* load = new LoadInst(CastToCStr(s2,*ci), ci->getName()+".load",ci); - CastInst* cast = + CastInst* cast = new CastInst(load,Type::IntTy,ci->getName()+".int",ci); ci->replaceAllUsesWith(cast); ci->eraseFromParent(); @@ -683,9 +683,9 @@ if (len_2 == 0) { // strcmp(x,"") -> *x - LoadInst* load = + LoadInst* load = new LoadInst(CastToCStr(s1,*ci),ci->getName()+".val",ci); - CastInst* cast = + CastInst* cast = new CastInst(load,Type::IntTy,ci->getName()+".int",ci); ci->replaceAllUsesWith(cast); ci->eraseFromParent(); @@ -707,7 +707,7 @@ } } StrCmpOptimizer; -/// This LibCallOptimization will simplify a call to the strncmp library +/// This LibCallOptimization will simplify a call to the strncmp library /// function. It optimizes out cases where one or both arguments are constant /// and the result can be determined statically. /// @brief Simplify the strncmp library function. @@ -719,7 +719,7 @@ virtual ~StrNCmpOptimization() {} /// @brief Make sure that the "strncmp" function has the right prototype - virtual bool ValidateCalledFunction(const Function* f, SimplifyLibCalls& SLC) + virtual bool ValidateCalledFunction(const Function* f, SimplifyLibCalls& SLC) { if (f->getReturnType() == Type::IntTy && f->arg_size() == 3) return true; @@ -731,7 +731,7 @@ { // First, check to see if src and destination are the same. If they are, // then the optimization is to replace the CallInst with a constant 0 - // because the call is a no-op. + // because the call is a no-op. Value* s1 = ci->getOperand(1); Value* s2 = ci->getOperand(2); if (s1 == s2) @@ -756,7 +756,7 @@ ci->replaceAllUsesWith(ConstantInt::get(Type::IntTy,0)); ci->eraseFromParent(); return true; - } + } } bool isstr_1 = false; @@ -769,7 +769,7 @@ { // strncmp("",x) -> *x LoadInst* load = new LoadInst(s1,ci->getName()+".load",ci); - CastInst* cast = + CastInst* cast = new CastInst(load,Type::IntTy,ci->getName()+".int",ci); ci->replaceAllUsesWith(cast); ci->eraseFromParent(); @@ -787,7 +787,7 @@ { // strncmp(x,"") -> *x LoadInst* load = new LoadInst(s2,ci->getName()+".val",ci); - CastInst* cast = + CastInst* cast = new CastInst(load,Type::IntTy,ci->getName()+".int",ci); ci->replaceAllUsesWith(cast); ci->eraseFromParent(); @@ -809,8 +809,8 @@ } } StrNCmpOptimizer; -/// This LibCallOptimization will simplify a call to the strcpy library -/// function. Two optimizations are possible: +/// This LibCallOptimization will simplify a call to the strcpy library +/// function. Two optimizations are possible: /// (1) If src and dest are the same and not volatile, just return dest /// (2) If the src is a constant then we can convert to llvm.memmove /// @brief Simplify the strcpy library function. @@ -822,10 +822,10 @@ virtual ~StrCpyOptimization() {} /// @brief Make sure that the "strcpy" function has the right prototype - virtual bool ValidateCalledFunction(const Function* f, SimplifyLibCalls& SLC) + virtual bool ValidateCalledFunction(const Function* f, SimplifyLibCalls& SLC) { if (f->getReturnType() == PointerType::get(Type::SByteTy)) - if (f->arg_size() == 2) + if (f->arg_size() == 2) { Function::const_arg_iterator AI = f->arg_begin(); if (AI++->getType() == PointerType::get(Type::SByteTy)) @@ -843,7 +843,7 @@ { // First, check to see if src and destination are the same. If they are, // then the optimization is to replace the CallInst with the destination - // because the call is a no-op. Note that this corresponds to the + // because the call is a no-op. Note that this corresponds to the // degenerate strcpy(X,X) case which should have "undefined" results // according to the C specification. However, it occurs sometimes and // we optimize it as a no-op. @@ -855,7 +855,7 @@ ci->eraseFromParent(); return true; } - + // Get the length of the constant string referenced by the second operand, // the "src" parameter. Fail the optimization if we can't get the length // (note that getConstantStringLength does lots of checks to make sure this @@ -890,8 +890,8 @@ vals.push_back(ConstantUInt::get(Type::UIntTy,1)); // alignment new CallInst(SLC.get_memcpy(), vals, "", ci); - // Finally, substitute the first operand of the strcat call for the - // strcat call itself since strcat returns its first operand; and, + // Finally, substitute the first operand of the strcat call for the + // strcat call itself since strcat returns its first operand; and, // kill the strcat CallInst. ci->replaceAllUsesWith(dest); ci->eraseFromParent(); @@ -899,8 +899,8 @@ } } StrCpyOptimizer; -/// This LibCallOptimization will simplify a call to the strlen library -/// function by replacing it with a constant value if the string provided to +/// This LibCallOptimization will simplify a call to the strlen library +/// function by replacing it with a constant value if the string provided to /// it is a constant array. /// @brief Simplify the strlen library function. struct StrLenOptimization : public LibCallOptimization @@ -913,7 +913,7 @@ virtual bool ValidateCalledFunction(const Function* f, SimplifyLibCalls& SLC) { if (f->getReturnType() == SLC.getTargetData()->getIntPtrType()) - if (f->arg_size() == 1) + if (f->arg_size() == 1) if (Function::const_arg_iterator AI = f->arg_begin()) if (AI->getType() == PointerType::get(Type::SByteTy)) return true; @@ -929,7 +929,7 @@ return false; // Does the call to strlen have exactly one use? - if (ci->hasOneUse()) + if (ci->hasOneUse()) // Is that single use a binary operator? if (BinaryOperator* bop = dyn_cast(ci->use_back())) // Is it compared against a constant integer? @@ -969,8 +969,8 @@ } } StrLenOptimizer; -/// This LibCallOptimization will simplify a call to the memcpy library -/// function by expanding it out to a single store of size 0, 1, 2, 4, or 8 +/// This LibCallOptimization will simplify a call to the memcpy library +/// function by expanding it out to a single store of size 0, 1, 2, 4, or 8 /// bytes depending on the length of the string and the alignment. Additional /// optimizations are possible in code generation (sequence of immediate store) /// @brief Simplify the memcpy library function. @@ -981,7 +981,7 @@ "Number of 'llvm.memcpy' calls simplified") {} protected: - /// @brief Subclass Constructor + /// @brief Subclass Constructor LLVMMemCpyOptimization(const char* fname, const char* desc) : LibCallOptimization(fname, desc) {} public: @@ -1038,9 +1038,9 @@ } // Cast source and dest to the right sized primitive and then load/store - CastInst* SrcCast = + CastInst* SrcCast = new CastInst(src,PointerType::get(castType),src->getName()+".cast",ci); - CastInst* DestCast = + CastInst* DestCast = new CastInst(dest,PointerType::get(castType),dest->getName()+".cast",ci); LoadInst* LI = new LoadInst(SrcCast,SrcCast->getName()+".val",ci); StoreInst* SI = new StoreInst(LI, DestCast, ci); @@ -1049,8 +1049,8 @@ } } LLVMMemCpyOptimizer; -/// This LibCallOptimization will simplify a call to the memmove library -/// function. It is identical to MemCopyOptimization except for the name of +/// This LibCallOptimization will simplify a call to the memmove library +/// function. It is identical to MemCopyOptimization except for the name of /// the intrinsic. /// @brief Simplify the memmove library function. struct LLVMMemMoveOptimization : public LLVMMemCpyOptimization @@ -1061,9 +1061,9 @@ } LLVMMemMoveOptimizer; -/// This LibCallOptimization will simplify a call to the memset library -/// function by expanding it out to a single store of size 0, 1, 2, 4, or 8 -/// bytes depending on the length argument. +/// This LibCallOptimization will simplify a call to the memset library +/// function by expanding it out to a single store of size 0, 1, 2, 4, or 8 +/// bytes depending on the length argument. struct LLVMMemSetOptimization : public LibCallOptimization { /// @brief Default Constructor @@ -1084,7 +1084,7 @@ /// Because of alignment and instruction information that we don't have, we /// leave the bulk of this to the code generators. The optimization here just /// deals with a few degenerate cases where the length parameter is constant - /// and the alignment matches the sizes of our intrinsic types so we can do + /// and the alignment matches the sizes of our intrinsic types so we can do /// store instead of the memcpy call. Other calls are transformed into the /// llvm.memset intrinsic. /// @brief Perform the memset optimization. @@ -1127,7 +1127,7 @@ return false; // memset(s,c,n) -> store s, c (for n=1,2,4,8) - + // Extract the fill character uint64_t fill_char = FILL->getValue(); uint64_t fill_value = fill_char; @@ -1138,18 +1138,18 @@ Type* castType = 0; switch (len) { - case 1: - castType = Type::UByteTy; + case 1: + castType = Type::UByteTy; break; - case 2: - castType = Type::UShortTy; + case 2: + castType = Type::UShortTy; fill_value |= fill_char << 8; break; - case 4: + case 4: castType = Type::UIntTy; fill_value |= fill_char << 8 | fill_char << 16 | fill_char << 24; break; - case 8: + case 8: castType = Type::ULongTy; fill_value |= fill_char << 8 | fill_char << 16 | fill_char << 24; fill_value |= fill_char << 32 | fill_char << 40 | fill_char << 48; @@ -1160,7 +1160,7 @@ } // Cast dest to the right sized primitive and then load/store - CastInst* DestCast = + CastInst* DestCast = new CastInst(dest,PointerType::get(castType),dest->getName()+".cast",ci); new StoreInst(ConstantUInt::get(castType,fill_value),DestCast, ci); ci->eraseFromParent(); @@ -1168,8 +1168,8 @@ } } LLVMMemSetOptimizer; -/// This LibCallOptimization will simplify calls to the "pow" library -/// function. It looks for cases where the result of pow is well known and +/// This LibCallOptimization will simplify calls to the "pow" library +/// function. It looks for cases where the result of pow is well known and /// substitutes the appropriate value. /// @brief Simplify the pow library function. struct PowOptimization : public LibCallOptimization @@ -1204,8 +1204,8 @@ ci->eraseFromParent(); return true; } - } - else if (ConstantFP* Op2 = dyn_cast(expn)) + } + else if (ConstantFP* Op2 = dyn_cast(expn)) { double Op2V = Op2->getValue(); if (Op2V == 0.0) @@ -1245,7 +1245,7 @@ } } PowOptimizer; -/// This LibCallOptimization will simplify calls to the "fprintf" library +/// This LibCallOptimization will simplify calls to the "fprintf" library /// function. It looks for cases where the result of fprintf is not used and the /// operation can be reduced to something simpler. /// @brief Simplify the pow library function. @@ -1273,14 +1273,14 @@ if (ci->getNumOperands() > 4 || ci->getNumOperands() <= 2) return false; - // If the result of the fprintf call is used, none of these optimizations + // If the result of the fprintf call is used, none of these optimizations // can be made. - if (!ci->hasNUses(0)) + if (!ci->hasNUses(0)) return false; // All the optimizations depend on the length of the second argument and the // fact that it is a constant string array. Check that now - uint64_t len = 0; + uint64_t len = 0; ConstantArray* CA = 0; if (!getConstantStringLength(ci->getOperand(2), len, &CA)) return false; @@ -1296,11 +1296,11 @@ if (CI->getRawValue() == '%') return false; // we found end of string } - else + else return false; } - // fprintf(file,fmt) -> fwrite(fmt,strlen(fmt),file) + // fprintf(file,fmt) -> fwrite(fmt,strlen(fmt),file) const Type* FILEptr_type = ci->getOperand(1)->getType(); Function* fwrite_func = SLC.get_fwrite(FILEptr_type); if (!fwrite_func) @@ -1339,12 +1339,12 @@ { case 's': { - uint64_t len = 0; + uint64_t len = 0; ConstantArray* CA = 0; if (!getConstantStringLength(ci->getOperand(3), len, &CA)) return false; - // fprintf(file,"%s",str) -> fwrite(fmt,strlen(fmt),1,file) + // fprintf(file,"%s",str) -> fwrite(fmt,strlen(fmt),1,file) const Type* FILEptr_type = ci->getOperand(1)->getType(); Function* fwrite_func = SLC.get_fwrite(FILEptr_type); if (!fwrite_func) @@ -1381,7 +1381,7 @@ } } FPrintFOptimizer; -/// This LibCallOptimization will simplify calls to the "sprintf" library +/// This LibCallOptimization will simplify calls to the "sprintf" library /// function. It looks for cases where the result of sprintf is not used and the /// operation can be reduced to something simpler. /// @brief Simplify the pow library function. @@ -1411,7 +1411,7 @@ // All the optimizations depend on the length of the second argument and the // fact that it is a constant string array. Check that now - uint64_t len = 0; + uint64_t len = 0; ConstantArray* CA = 0; if (!getConstantStringLength(ci->getOperand(2), len, &CA)) return false; @@ -1436,14 +1436,14 @@ if (CI->getRawValue() == '%') return false; // we found a %, can't optimize } - else + else return false; // initializer is not constant int, can't optimize } // Increment length because we want to copy the null byte too len++; - // sprintf(str,fmt) -> llvm.memcpy(str,fmt,strlen(fmt),1) + // sprintf(str,fmt) -> llvm.memcpy(str,fmt,strlen(fmt),1) Function* memcpy_func = SLC.get_memcpy(); if (!memcpy_func) return false; @@ -1477,7 +1477,7 @@ uint64_t len = 0; if (ci->hasNUses(0)) { - // sprintf(dest,"%s",str) -> strcpy(dest,str) + // sprintf(dest,"%s",str) -> strcpy(dest,str) Function* strcpy_func = SLC.get_strcpy(); if (!strcpy_func) return false; @@ -1506,7 +1506,7 @@ case 'c': { // sprintf(dest,"%c",chr) -> store chr, dest - CastInst* cast = + CastInst* cast = new CastInst(ci->getOperand(3),Type::SByteTy,"char",ci); new StoreInst(cast, ci->getOperand(1), ci); GetElementPtrInst* gep = new GetElementPtrInst(ci->getOperand(1), @@ -1524,7 +1524,7 @@ } } SPrintFOptimizer; -/// This LibCallOptimization will simplify calls to the "fputs" library +/// This LibCallOptimization will simplify calls to the "fputs" library /// function. It looks for cases where the result of fputs is not used and the /// operation can be reduced to something simpler. /// @brief Simplify the pow library function. @@ -1549,12 +1549,12 @@ virtual bool OptimizeCall(CallInst* ci, SimplifyLibCalls& SLC) { // If the result is used, none of these optimizations work - if (!ci->hasNUses(0)) + if (!ci->hasNUses(0)) return false; // All the optimizations depend on the length of the first argument and the // fact that it is a constant string array. Check that now - uint64_t len = 0; + uint64_t len = 0; if (!getConstantStringLength(ci->getOperand(1), len)) return false; @@ -1578,7 +1578,7 @@ break; } default: - { + { // fputs(s,F) -> fwrite(s,1,len,F) (if s is constant and strlen(s) > 1) const Type* FILEptr_type = ci->getOperand(2)->getType(); Function* fwrite_func = SLC.get_fwrite(FILEptr_type); @@ -1598,7 +1598,7 @@ } } PutsOptimizer; -/// This LibCallOptimization will simplify calls to the "isdigit" library +/// This LibCallOptimization will simplify calls to the "isdigit" library /// function. It simply does range checks the parameter explicitly. /// @brief Simplify the isdigit library function. struct IsDigitOptimization : public LibCallOptimization @@ -1634,7 +1634,7 @@ } // isdigit(c) -> (unsigned)c - '0' <= 9 - CastInst* cast = + CastInst* cast = new CastInst(ci->getOperand(1),Type::UIntTy, ci->getOperand(1)->getName()+".uint",ci); BinaryOperator* sub_inst = BinaryOperator::create(Instruction::Sub,cast, @@ -1643,7 +1643,7 @@ SetCondInst* setcond_inst = new SetCondInst(Instruction::SetLE,sub_inst, ConstantUInt::get(Type::UIntTy,9), ci->getOperand(1)->getName()+".cmp",ci); - CastInst* c2 = + CastInst* c2 = new CastInst(setcond_inst,Type::IntTy, ci->getOperand(1)->getName()+".isdigit",ci); ci->replaceAllUsesWith(c2); @@ -1652,7 +1652,7 @@ } } IsDigitOptimizer; -/// This LibCallOptimization will simplify calls to the "toascii" library +/// This LibCallOptimization will simplify calls to the "toascii" library /// function. It simply does the corresponding and operation to restrict the /// range of values to the ASCII character set (0-127). /// @brief Simplify the toascii library function. @@ -1687,7 +1687,7 @@ } ToAsciiOptimizer; /// This LibCallOptimization will simplify calls to the "ffs" library -/// calls which find the first set bit in an int, long, or long long. The +/// calls which find the first set bit in an int, long, or long long. The /// optimization is to compute the result at compile time if the argument is /// a constant. /// @brief Simplify the ffs library function. @@ -1742,10 +1742,10 @@ std::vector args; args.push_back(arg_type); FunctionType* llvm_cttz_type = FunctionType::get(arg_type,args,false); - Function* F = + Function* F = SLC.getModule()->getOrInsertFunction("llvm.cttz",llvm_cttz_type); std::string inst_name(ci->getName()+".ffs"); - Instruction* call = + Instruction* call = new CallInst(F, ci->getOperand(1), inst_name, ci); if (arg_type != Type::IntTy) call = new CastInst(call, Type::IntTy, inst_name, ci); @@ -1788,10 +1788,10 @@ } FFSLLOptimizer; /// A function to compute the length of a null-terminated constant array of -/// integers. This function can't rely on the size of the constant array -/// because there could be a null terminator in the middle of the array. -/// We also have to bail out if we find a non-integer constant initializer -/// of one of the elements or if there is no null-terminator. The logic +/// integers. This function can't rely on the size of the constant array +/// because there could be a null terminator in the middle of the array. +/// We also have to bail out if we find a non-integer constant initializer +/// of one of the elements or if there is no null-terminator. The logic /// below checks each of these conditions and will return true only if all /// conditions are met. In that case, the \p len parameter is set to the length /// of the null-terminated string. If false is returned, the conditions were @@ -1800,10 +1800,10 @@ bool getConstantStringLength(Value* V, uint64_t& len, ConstantArray** CA ) { assert(V != 0 && "Invalid args to getConstantStringLength"); - len = 0; // make sure we initialize this + len = 0; // make sure we initialize this User* GEP = 0; - // If the value is not a GEP instruction nor a constant expression with a - // GEP instruction, then return false because ConstantArray can't occur + // If the value is not a GEP instruction nor a constant expression with a + // GEP instruction, then return false because ConstantArray can't occur // any other way if (GetElementPtrInst* GEPI = dyn_cast(V)) GEP = GEPI; @@ -1820,7 +1820,7 @@ return false; // Check to make sure that the first operand of the GEP is an integer and - // has value 0 so that we are sure we're indexing into the initializer. + // has value 0 so that we are sure we're indexing into the initializer. if (ConstantInt* op1 = dyn_cast(GEP->getOperand(1))) { if (!op1->isNullValue()) @@ -1830,7 +1830,7 @@ return false; // Ensure that the second operand is a ConstantInt. If it isn't then this - // GEP is wonky and we're not really sure what were referencing into and + // GEP is wonky and we're not really sure what were referencing into and // better of not optimizing it. While we're at it, get the second index // value. We'll need this later for indexing the ConstantArray. uint64_t start_idx = 0; @@ -1867,7 +1867,7 @@ uint64_t max_elems = A->getType()->getNumElements(); // Traverse the constant array from start_idx (derived above) which is - // the place the GEP refers to in the array. + // the place the GEP refers to in the array. for ( len = start_idx; len < max_elems; len++) { if (ConstantInt* CI = dyn_cast(A->getOperand(len))) @@ -1899,7 +1899,7 @@ return V; } -// TODO: +// TODO: // Additional cases that we need to add to this file: // // cbrt: @@ -1915,7 +1915,7 @@ // // isascii: // * isascii(c) -> ((c & ~0x7f) == 0) -// +// // isdigit: // * isdigit(c) -> (unsigned)(c) - '0' <= 9 // @@ -1939,7 +1939,7 @@ // * memcmp(x,y,1) -> *x - *y // // memmove: -// * memmove(d,s,l,a) -> memcpy(d,s,l,a) +// * memmove(d,s,l,a) -> memcpy(d,s,l,a) // (if s is a global constant array) // // pow, powf, powl: @@ -1996,14 +1996,14 @@ // // strstr: // * strstr(x,x) -> x -// * strstr(s1,s2) -> offset_of_s2_in(s1) +// * strstr(s1,s2) -> offset_of_s2_in(s1) // (if s1 and s2 are constant strings) -// +// // tan, tanf, tanl: // * tan(atan(x)) -> x -// +// // trunc, truncf, truncl: // * trunc(cnst) -> cnst' // -// +// } From reid at x10sys.com Wed Jul 27 16:58:50 2005 From: reid at x10sys.com (Reid Spencer) Date: Wed, 27 Jul 2005 16:58:50 -0500 Subject: [llvm-commits] CVS: llvm/autoconf/configure.ac Message-ID: <200507272158.QAA22274@zion.cs.uiuc.edu> Changes in directory llvm/autoconf: configure.ac updated: 1.192 -> 1.193 --- Log message: Fix PR608: http://llvm.cs.uiuc.edu/PR608 : Previously the script assumed the version number was the last field, now it assumes it is the first sequence of digits. --- Diffs of the changes: (+1 -1) configure.ac | 2 +- 1 files changed, 1 insertion(+), 1 deletion(-) Index: llvm/autoconf/configure.ac diff -u llvm/autoconf/configure.ac:1.192 llvm/autoconf/configure.ac:1.193 --- llvm/autoconf/configure.ac:1.192 Fri Jul 22 15:54:01 2005 +++ llvm/autoconf/configure.ac Wed Jul 27 16:58:38 2005 @@ -404,7 +404,7 @@ dnl Verify that GCC is version 3.0 or higher if test "$GCC" = "yes" then - gccmajor=`$CC --version | head -n 1 | awk '{print $NF;}' | cut -d. -f1` + gccmajor=`$CC --version | head -n 1 | sed 's/[[^0-9]]*\([[0-9.]]\).*/\1/'` if test "$gccmajor" -lt "3" then AC_MSG_ERROR([gcc 3.x required, but you have a lower version]) From reid at x10sys.com Wed Jul 27 16:58:50 2005 From: reid at x10sys.com (Reid Spencer) Date: Wed, 27 Jul 2005 16:58:50 -0500 Subject: [llvm-commits] CVS: llvm/include/llvm/Config/config.h.in Message-ID: <200507272158.QAA22278@zion.cs.uiuc.edu> Changes in directory llvm/include/llvm/Config: config.h.in updated: 1.54 -> 1.55 --- Log message: Fix PR608: http://llvm.cs.uiuc.edu/PR608 : Previously the script assumed the version number was the last field, now it assumes it is the first sequence of digits. --- Diffs of the changes: (+3 -3) config.h.in | 6 +++--- 1 files changed, 3 insertions(+), 3 deletions(-) Index: llvm/include/llvm/Config/config.h.in diff -u llvm/include/llvm/Config/config.h.in:1.54 llvm/include/llvm/Config/config.h.in:1.55 --- llvm/include/llvm/Config/config.h.in:1.54 Wed Jul 27 00:53:43 2005 +++ llvm/include/llvm/Config/config.h.in Wed Jul 27 16:58:38 2005 @@ -449,9 +449,9 @@ /* If using the C implementation of alloca, define if you know the direction of stack growth for your system; otherwise it will be automatically deduced at run-time. - STACK_DIRECTION > 0 => grows toward higher addresses - STACK_DIRECTION < 0 => grows toward lower addresses - STACK_DIRECTION = 0 => direction of growth unknown */ + STACK_DIRECTION > 0 => grows toward higher addresses + STACK_DIRECTION < 0 => grows toward lower addresses + STACK_DIRECTION = 0 => direction of growth unknown */ #undef STACK_DIRECTION /* Define to 1 if the `S_IS*' macros in do not work properly. */ From reid at x10sys.com Wed Jul 27 16:58:50 2005 From: reid at x10sys.com (Reid Spencer) Date: Wed, 27 Jul 2005 16:58:50 -0500 Subject: [llvm-commits] CVS: llvm/configure Message-ID: <200507272158.QAA22282@zion.cs.uiuc.edu> Changes in directory llvm: configure updated: 1.196 -> 1.197 --- Log message: Fix PR608: http://llvm.cs.uiuc.edu/PR608 : Previously the script assumed the version number was the last field, now it assumes it is the first sequence of digits. --- Diffs of the changes: (+1 -1) configure | 2 +- 1 files changed, 1 insertion(+), 1 deletion(-) Index: llvm/configure diff -u llvm/configure:1.196 llvm/configure:1.197 --- llvm/configure:1.196 Fri Jul 22 15:54:00 2005 +++ llvm/configure Wed Jul 27 16:58:38 2005 @@ -24842,7 +24842,7 @@ if test "$GCC" = "yes" then - gccmajor=`$CC --version | head -n 1 | awk '{print $NF;}' | cut -d. -f1` + gccmajor=`$CC --version | head -n 1 | sed 's/[^0-9]*\([0-9.]\).*/\1/'` if test "$gccmajor" -lt "3" then { { echo "$as_me:$LINENO: error: gcc 3.x required, but you have a lower version" >&5 From lattner at cs.uiuc.edu Wed Jul 27 18:03:50 2005 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Wed, 27 Jul 2005 18:03:50 -0500 Subject: [llvm-commits] CVS: llvm/lib/CodeGen/LiveIntervalAnalysis.cpp Message-ID: <200507272303.SAA01157@zion.cs.uiuc.edu> Changes in directory llvm/lib/CodeGen: LiveIntervalAnalysis.cpp updated: 1.141 -> 1.142 --- Log message: Print symbolic register names in debug dumps --- Diffs of the changes: (+4 -2) LiveIntervalAnalysis.cpp | 6 ++++-- 1 files changed, 4 insertions(+), 2 deletions(-) Index: llvm/lib/CodeGen/LiveIntervalAnalysis.cpp diff -u llvm/lib/CodeGen/LiveIntervalAnalysis.cpp:1.141 llvm/lib/CodeGen/LiveIntervalAnalysis.cpp:1.142 --- llvm/lib/CodeGen/LiveIntervalAnalysis.cpp:1.141 Sat May 14 00:34:15 2005 +++ llvm/lib/CodeGen/LiveIntervalAnalysis.cpp Wed Jul 27 18:03:38 2005 @@ -206,8 +206,10 @@ /// print - Implement the dump method. void LiveIntervals::print(std::ostream &O, const Module* ) const { O << "********** INTERVALS **********\n"; - for (const_iterator I = begin(), E = end(); I != E; ++I) - O << " " << I->second << "\n"; + for (const_iterator I = begin(), E = end(); I != E; ++I) { + I->second.print(std::cerr, mri_); + std::cerr << "\n"; + } O << "********** MACHINEINSTRS **********\n"; for (MachineFunction::iterator mbbi = mf_->begin(), mbbe = mf_->end(); From lattner at cs.uiuc.edu Wed Jul 27 18:11:37 2005 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Wed, 27 Jul 2005 18:11:37 -0500 Subject: [llvm-commits] CVS: llvm/lib/CodeGen/LiveIntervalAnalysis.cpp Message-ID: <200507272311.SAA06505@zion.cs.uiuc.edu> Changes in directory llvm/lib/CodeGen: LiveIntervalAnalysis.cpp updated: 1.142 -> 1.143 --- Log message: Fix debug info to not print out recently freed memory. --- Diffs of the changes: (+1 -1) LiveIntervalAnalysis.cpp | 2 +- 1 files changed, 1 insertion(+), 1 deletion(-) Index: llvm/lib/CodeGen/LiveIntervalAnalysis.cpp diff -u llvm/lib/CodeGen/LiveIntervalAnalysis.cpp:1.142 llvm/lib/CodeGen/LiveIntervalAnalysis.cpp:1.143 --- llvm/lib/CodeGen/LiveIntervalAnalysis.cpp:1.142 Wed Jul 27 18:03:38 2005 +++ llvm/lib/CodeGen/LiveIntervalAnalysis.cpp Wed Jul 27 18:11:25 2005 @@ -671,6 +671,7 @@ if ((TriviallyJoinable || IntB.joinable(IntA, MIDefIdx)) && !overlapsAliases(&IntA, &IntB)) { IntB.join(IntA, MIDefIdx); + DEBUG(std::cerr << "Joined. Result = " << IntB << "\n"); if (!MRegisterInfo::isPhysicalRegister(regA)) { r2iMap_.erase(regA); @@ -683,7 +684,6 @@ IntA.swap(IntB); r2iMap_.erase(regB); } - DEBUG(std::cerr << "Joined. Result = " << IntB << "\n"); ++numJoins; } else { DEBUG(std::cerr << "Interference!\n"); From natebegeman at mac.com Wed Jul 27 18:11:38 2005 From: natebegeman at mac.com (Nate Begeman) Date: Wed, 27 Jul 2005 18:11:38 -0500 Subject: [llvm-commits] CVS: llvm/lib/Target/PowerPC/PPC32ISelPattern.cpp PPC32RegisterInfo.cpp Message-ID: <200507272311.SAA06511@zion.cs.uiuc.edu> Changes in directory llvm/lib/Target/PowerPC: PPC32ISelPattern.cpp updated: 1.105 -> 1.106 PPC32RegisterInfo.cpp updated: 1.13 -> 1.14 --- Log message: Fix some comments --- Diffs of the changes: (+2 -4) PPC32ISelPattern.cpp | 4 +--- PPC32RegisterInfo.cpp | 2 +- 2 files changed, 2 insertions(+), 4 deletions(-) Index: llvm/lib/Target/PowerPC/PPC32ISelPattern.cpp diff -u llvm/lib/Target/PowerPC/PPC32ISelPattern.cpp:1.105 llvm/lib/Target/PowerPC/PPC32ISelPattern.cpp:1.106 --- llvm/lib/Target/PowerPC/PPC32ISelPattern.cpp:1.105 Wed Jul 27 01:12:33 2005 +++ llvm/lib/Target/PowerPC/PPC32ISelPattern.cpp Wed Jul 27 18:11:27 2005 @@ -1656,9 +1656,6 @@ return Result; case ISD::AND: - // FIXME: should add check in getImmediateForOpcode to return a value - // indicating the immediate is a run of set bits so we can emit a bitfield - // clear with RLWINM instead. switch(getImmediateForOpcode(N.getOperand(1), opcode, Tmp2)) { default: assert(0 && "unhandled result code"); case 0: // No immediate @@ -1690,6 +1687,7 @@ Tmp3 = Tmp2 >> 16; // MB Tmp2 &= 0xFFFF; // ME + // FIXME: Catch SHL-AND in addition to SRL-AND in this block. if (N.getOperand(0).getOpcode() == ISD::SRL) if (ConstantSDNode *SA = dyn_cast(N.getOperand(0).getOperand(1))) { Index: llvm/lib/Target/PowerPC/PPC32RegisterInfo.cpp diff -u llvm/lib/Target/PowerPC/PPC32RegisterInfo.cpp:1.13 llvm/lib/Target/PowerPC/PPC32RegisterInfo.cpp:1.14 --- llvm/lib/Target/PowerPC/PPC32RegisterInfo.cpp:1.13 Wed Jul 27 01:06:29 2005 +++ llvm/lib/Target/PowerPC/PPC32RegisterInfo.cpp Wed Jul 27 18:11:27 2005 @@ -263,7 +263,7 @@ // Update frame info to pretend that this is part of the stack... MFI->setStackSize(NumBytes); - // If , adjust stack pointer: r1 -= numbytes. + // Adjust stack pointer: r1 -= numbytes. if (NumBytes <= 32768) { MI=BuildMI(PPC::STWU,3).addReg(PPC::R1).addSImm(-NumBytes).addReg(PPC::R1); MBB.insert(MBBI, MI); From jeffc at jolt-lang.org Wed Jul 27 21:04:55 2005 From: jeffc at jolt-lang.org (Jeff Cohen) Date: Wed, 27 Jul 2005 21:04:55 -0500 Subject: [llvm-commits] CVS: llvm/include/llvm/Config/config.h.in Message-ID: <200507280204.VAA07561@zion.cs.uiuc.edu> Changes in directory llvm/include/llvm/Config: config.h.in updated: 1.55 -> 1.56 --- Log message: Please do not reintroduce tabs. --- Diffs of the changes: (+3 -3) config.h.in | 6 +++--- 1 files changed, 3 insertions(+), 3 deletions(-) Index: llvm/include/llvm/Config/config.h.in diff -u llvm/include/llvm/Config/config.h.in:1.55 llvm/include/llvm/Config/config.h.in:1.56 --- llvm/include/llvm/Config/config.h.in:1.55 Wed Jul 27 16:58:38 2005 +++ llvm/include/llvm/Config/config.h.in Wed Jul 27 21:04:44 2005 @@ -449,9 +449,9 @@ /* If using the C implementation of alloca, define if you know the direction of stack growth for your system; otherwise it will be automatically deduced at run-time. - STACK_DIRECTION > 0 => grows toward higher addresses - STACK_DIRECTION < 0 => grows toward lower addresses - STACK_DIRECTION = 0 => direction of growth unknown */ + STACK_DIRECTION > 0 => grows toward higher addresses + STACK_DIRECTION < 0 => grows toward lower addresses + STACK_DIRECTION = 0 => direction of growth unknown */ #undef STACK_DIRECTION /* Define to 1 if the `S_IS*' macros in do not work properly. */ From reid at x10sys.com Wed Jul 27 21:25:41 2005 From: reid at x10sys.com (Reid Spencer) Date: Wed, 27 Jul 2005 21:25:41 -0500 Subject: [llvm-commits] CVS: llvm/tools/llc/llc.cpp Message-ID: <200507280225.VAA07655@zion.cs.uiuc.edu> Changes in directory llvm/tools/llc: llc.cpp updated: 1.108 -> 1.109 --- Log message: Make the verifier pass run (in debug mode) in llc. This adds a sanity check to llc when debugging. Also allow other passes to be run from llc. Patch contributed by Michael McCracken. --- Diffs of the changes: (+29 -0) llc.cpp | 29 +++++++++++++++++++++++++++++ 1 files changed, 29 insertions(+) Index: llvm/tools/llc/llc.cpp diff -u llvm/tools/llc/llc.cpp:1.108 llvm/tools/llc/llc.cpp:1.109 --- llvm/tools/llc/llc.cpp:1.108 Fri Jun 24 22:32:05 2005 +++ llvm/tools/llc/llc.cpp Wed Jul 27 21:25:30 2005 @@ -22,6 +22,8 @@ #include "llvm/Pass.h" #include "llvm/Support/CommandLine.h" #include "llvm/Support/PluginLoader.h" +#include "llvm/Support/PassNameParser.h" +#include "llvm/Analysis/Verifier.h" #include "llvm/System/Signals.h" #include "llvm/Config/config.h" #include @@ -57,6 +59,14 @@ " Emit a native dynamic library ('.so') file"), clEnumValEnd)); +// The LLCPassList is populated with passes that were registered using +// PassInfo::LLC by the FilteredPassNameParser: +cl::list > +LLCPassList(cl::desc("Passes Available")); + +cl::opt NoVerify("disable-verify", cl::Hidden, + cl::desc("Do not verify input module")); + // GetFileNameRoot - Helper function to get the basename of a filename. static inline std::string @@ -113,6 +123,25 @@ PassManager Passes; Passes.add(new TargetData(TD)); +#ifndef NDEBUG + if(!NoVerify) + Passes.add(createVerifierPass()); +#endif + + // Create a new pass for each one specified on the command line + for (unsigned i = 0; i < LLCPassList.size(); ++i) { + const PassInfo *aPass = LLCPassList[i]; + + if (aPass->getNormalCtor()) { + Pass *P = aPass->getNormalCtor()(); + Passes.add(P); + } else { + std::cerr << argv[0] << ": cannot create pass: " + << aPass->getPassName() << "\n"; + } + } + + // Figure out where we are going to send the output... std::ostream *Out = 0; if (OutputFilename != "") { From reid at x10sys.com Wed Jul 27 21:29:21 2005 From: reid at x10sys.com (Reid Spencer) Date: Wed, 27 Jul 2005 19:29:21 -0700 Subject: [llvm-commits] CVS: llvm/include/llvm/Config/config.h.in In-Reply-To: <200507280204.VAA07561@zion.cs.uiuc.edu> References: <200507280204.VAA07561@zion.cs.uiuc.edu> Message-ID: <1122517761.30526.187.camel@bashful.x10sys.com> Jeff, This is an auto-generated file. The tabs are going to get re-introduced every time we rebuild the configure script. While I appreciate your diligent efforts to rid LLVM from tabs, I think we can survive these three. Please ignore this file in your future detabification quests. Thanks, Reid. On Wed, 2005-07-27 at 21:04 -0500, Jeff Cohen wrote: > > Changes in directory llvm/include/llvm/Config: > > config.h.in updated: 1.55 -> 1.56 > --- > Log message: > > Please do not reintroduce tabs. > > --- > Diffs of the changes: (+3 -3) > > config.h.in | 6 +++--- > 1 files changed, 3 insertions(+), 3 deletions(-) > > > Index: llvm/include/llvm/Config/config.h.in > diff -u llvm/include/llvm/Config/config.h.in:1.55 llvm/include/llvm/Config/config.h.in:1.56 > --- llvm/include/llvm/Config/config.h.in:1.55 Wed Jul 27 16:58:38 2005 > +++ llvm/include/llvm/Config/config.h.in Wed Jul 27 21:04:44 2005 > @@ -449,9 +449,9 @@ > /* If using the C implementation of alloca, define if you know the > direction of stack growth for your system; otherwise it will be > automatically deduced at run-time. > - STACK_DIRECTION > 0 => grows toward higher addresses > - STACK_DIRECTION < 0 => grows toward lower addresses > - STACK_DIRECTION = 0 => direction of growth unknown */ > + STACK_DIRECTION > 0 => grows toward higher addresses > + STACK_DIRECTION < 0 => grows toward lower addresses > + STACK_DIRECTION = 0 => direction of growth unknown */ > #undef STACK_DIRECTION > > /* Define to 1 if the `S_IS*' macros in do not work properly. */ > > > > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits -------------- next part -------------- A non-text attachment was scrubbed... Name: not available Type: application/pgp-signature Size: 189 bytes Desc: This is a digitally signed message part Url : http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20050727/280e17be/attachment.bin From natebegeman at mac.com Wed Jul 27 22:02:16 2005 From: natebegeman at mac.com (Nate Begeman) Date: Wed, 27 Jul 2005 22:02:16 -0500 Subject: [llvm-commits] CVS: llvm/lib/Target/PowerPC/PPC32ISelPattern.cpp Message-ID: <200507280302.WAA07770@zion.cs.uiuc.edu> Changes in directory llvm/lib/Target/PowerPC: PPC32ISelPattern.cpp updated: 1.106 -> 1.107 --- Log message: Fold constant adds into loads and stores to frame indices. For the following code: double %ext(int %A.0__, long %A.1__) { %A_addr = alloca %typedef.DComplex ; <%typedef.DComplex*> [#uses=2] %tmp.1 = cast %typedef.DComplex* %A_addr to int* ; [#uses=1] store int %A.0__, int* %tmp.1 %tmp.2 = getelementptr %typedef.DComplex* %A_addr, int 0, uint 1 ; [#uses=2] %tmp.3 = cast double* %tmp.2 to long* ; [#uses=1] store long %A.1__, long* %tmp.3 %tmp.5 = load double* %tmp.2 ; [#uses=1] ret double %tmp.5 } We now generate: _ext: .LBB_ext_0: ; stw r3, -12(r1) stw r4, -8(r1) stw r5, -4(r1) lfd f1, -8(r1) blr Instead of: _ext: .LBB_ext_0: ; stw r3, -12(r1) addi r2, r1, -12 stw r4, 4(r2) stw r5, 8(r2) lfd f1, 4(r2) blr This also fires hundreds of times on MultiSource. --- Diffs of the changes: (+37 -17) PPC32ISelPattern.cpp | 54 ++++++++++++++++++++++++++++++++++----------------- 1 files changed, 37 insertions(+), 17 deletions(-) Index: llvm/lib/Target/PowerPC/PPC32ISelPattern.cpp diff -u llvm/lib/Target/PowerPC/PPC32ISelPattern.cpp:1.106 llvm/lib/Target/PowerPC/PPC32ISelPattern.cpp:1.107 --- llvm/lib/Target/PowerPC/PPC32ISelPattern.cpp:1.106 Wed Jul 27 18:11:27 2005 +++ llvm/lib/Target/PowerPC/PPC32ISelPattern.cpp Wed Jul 27 22:02:05 2005 @@ -511,7 +511,7 @@ namespace { Statistic<>Recorded("ppc-codegen", "Number of recording ops emitted"); Statistic<>FusedFP("ppc-codegen", "Number of fused fp operations"); -Statistic<>MultiBranch("ppc-codegen", "Number of setcc logical ops collapsed"); +Statistic<>FrameOff("ppc-codegen", "Number of frame idx offsets collapsed"); //===--------------------------------------------------------------------===// /// ISel - PPC32 specific code to select PPC32 machine instructions for /// SelectionDAG operations. @@ -569,7 +569,7 @@ unsigned SelectExpr(SDOperand N, bool Recording=false); void Select(SDOperand N); - bool SelectAddr(SDOperand N, unsigned& Reg, int& offset); + unsigned SelectAddr(SDOperand N, unsigned& Reg, int& offset); void SelectBranchCC(SDOperand N); }; @@ -1189,7 +1189,6 @@ break; case ISD::OR: case ISD::AND: - ++MultiBranch; Tmp1 = SelectCCExpr(N.getOperand(0), Opc, Inv0, Idx0); Tmp2 = SelectCCExpr(N.getOperand(1), Opc1, Inv1, Idx1); CROpc = getCROpForSetCC(N.getOpcode(), Inv0, Inv1); @@ -1213,21 +1212,30 @@ } /// Check to see if the load is a constant offset from a base register -bool ISel::SelectAddr(SDOperand N, unsigned& Reg, int& offset) +unsigned ISel::SelectAddr(SDOperand N, unsigned& Reg, int& offset) { unsigned imm = 0, opcode = N.getOpcode(); if (N.getOpcode() == ISD::ADD) { - Reg = SelectExpr(N.getOperand(0)); + bool isFrame = N.getOperand(0).getOpcode() == ISD::FrameIndex; if (1 == getImmediateForOpcode(N.getOperand(1), opcode, imm)) { offset = imm; - return false; + if (isFrame) { + ++FrameOff; + Reg = cast(N.getOperand(0))->getIndex(); + return 1; + } else { + Reg = SelectExpr(N.getOperand(0)); + return 0; + } + } else { + Reg = SelectExpr(N.getOperand(0)); + offset = SelectExpr(N.getOperand(1)); + return 2; } - offset = SelectExpr(N.getOperand(1)); - return true; } Reg = SelectExpr(N); offset = 0; - return false; + return 0; } void ISel::SelectBranchCC(SDOperand N) @@ -1443,12 +1451,18 @@ } } else { int offset; - bool idx = SelectAddr(Address, Tmp1, offset); - if (idx) { + switch(SelectAddr(Address, Tmp1, offset)) { + default: assert(0 && "Unhandled return value from SelectAddr"); + case 0: // imm offset, no frame, no index + BuildMI(BB, Opc, 2, Result).addSImm(offset).addReg(Tmp1); + break; + case 1: // imm offset + frame index + addFrameReference(BuildMI(BB, Opc, 2, Result), (int)Tmp1, offset); + break; + case 2: // base+index addressing Opc = IndexedOpForOp(Opc); BuildMI(BB, Opc, 2, Result).addReg(Tmp1).addReg(offset); - } else { - BuildMI(BB, Opc, 2, Result).addSImm(offset).addReg(Tmp1); + break; } } return Result; @@ -2495,12 +2509,18 @@ } } else { int offset; - bool idx = SelectAddr(Address, Tmp2, offset); - if (idx) { + switch(SelectAddr(Address, Tmp2, offset)) { + default: assert(0 && "Unhandled return value from SelectAddr"); + case 0: // imm offset, no frame, no index + BuildMI(BB, Opc, 3).addReg(Tmp1).addSImm(offset).addReg(Tmp2); + break; + case 1: // imm offset + frame index + addFrameReference(BuildMI(BB, Opc, 3).addReg(Tmp1), (int)Tmp2, offset); + break; + case 2: // base+index addressing Opc = IndexedOpForOp(Opc); BuildMI(BB, Opc, 3).addReg(Tmp1).addReg(Tmp2).addReg(offset); - } else { - BuildMI(BB, Opc, 3).addReg(Tmp1).addImm(offset).addReg(Tmp2); + break; } } return; From sabre at nondot.org Wed Jul 27 22:49:45 2005 From: sabre at nondot.org (Chris Lattner) Date: Wed, 27 Jul 2005 22:49:45 -0500 (CDT) Subject: [llvm-commits] CVS: llvm/tools/llc/llc.cpp In-Reply-To: <200507280225.VAA07655@zion.cs.uiuc.edu> References: <200507280225.VAA07655@zion.cs.uiuc.edu> Message-ID: On Wed, 27 Jul 2005, Reid Spencer wrote: > // GetFileNameRoot - Helper function to get the basename of a filename. > static inline std::string > @@ -113,6 +123,25 @@ > PassManager Passes; > Passes.add(new TargetData(TD)); > > +#ifndef NDEBUG > + if(!NoVerify) > + Passes.add(createVerifierPass()); > +#endif Shouldn't the verifier be run AFTER the passes below? This just verifies that the bytecode file isn't corrupt, which isn't super useful since gccld verifies it is fine before writing it. -Chris > + // Create a new pass for each one specified on the command line > + for (unsigned i = 0; i < LLCPassList.size(); ++i) { > + const PassInfo *aPass = LLCPassList[i]; > + > + if (aPass->getNormalCtor()) { > + Pass *P = aPass->getNormalCtor()(); > + Passes.add(P); > + } else { > + std::cerr << argv[0] << ": cannot create pass: " > + << aPass->getPassName() << "\n"; > + } > + } > + > + > // Figure out where we are going to send the output... > std::ostream *Out = 0; > if (OutputFilename != "") { > > > > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits > -Chris -- http://nondot.org/sabre/ http://llvm.org/ From reid at x10sys.com Wed Jul 27 22:58:11 2005 From: reid at x10sys.com (Reid Spencer) Date: Wed, 27 Jul 2005 20:58:11 -0700 Subject: [llvm-commits] CVS: llvm/tools/llc/llc.cpp In-Reply-To: References: <200507280225.VAA07655@zion.cs.uiuc.edu> Message-ID: <1122523091.30526.189.camel@bashful.x10sys.com> On Wed, 2005-07-27 at 22:49 -0500, Chris Lattner wrote: > On Wed, 27 Jul 2005, Reid Spencer wrote: > > > // GetFileNameRoot - Helper function to get the basename of a filename. > > static inline std::string > > @@ -113,6 +123,25 @@ > > PassManager Passes; > > Passes.add(new TargetData(TD)); > > > > +#ifndef NDEBUG > > + if(!NoVerify) > > + Passes.add(createVerifierPass()); > > +#endif > > > Shouldn't the verifier be run AFTER the passes below? This just verifies > that the bytecode file isn't corrupt, which isn't super useful since gccld > verifies it is fine before writing it. > > -Chris Yes. I'll fix it. Thanks. Reid. -------------- next part -------------- A non-text attachment was scrubbed... Name: not available Type: application/pgp-signature Size: 189 bytes Desc: This is a digitally signed message part Url : http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20050727/5d95764b/attachment.bin From reid at x10sys.com Wed Jul 27 23:01:00 2005 From: reid at x10sys.com (Reid Spencer) Date: Wed, 27 Jul 2005 23:01:00 -0500 Subject: [llvm-commits] CVS: llvm/tools/llc/llc.cpp Message-ID: <200507280401.XAA07989@zion.cs.uiuc.edu> Changes in directory llvm/tools/llc: llc.cpp updated: 1.109 -> 1.110 --- Log message: Run the verifier pass after all the other passes rather than before them. This catches mistakes in the passes rather than just verifying the bytecode input to llc. --- Diffs of the changes: (+4 -5) llc.cpp | 9 ++++----- 1 files changed, 4 insertions(+), 5 deletions(-) Index: llvm/tools/llc/llc.cpp diff -u llvm/tools/llc/llc.cpp:1.109 llvm/tools/llc/llc.cpp:1.110 --- llvm/tools/llc/llc.cpp:1.109 Wed Jul 27 21:25:30 2005 +++ llvm/tools/llc/llc.cpp Wed Jul 27 23:00:49 2005 @@ -123,11 +123,6 @@ PassManager Passes; Passes.add(new TargetData(TD)); -#ifndef NDEBUG - if(!NoVerify) - Passes.add(createVerifierPass()); -#endif - // Create a new pass for each one specified on the command line for (unsigned i = 0; i < LLCPassList.size(); ++i) { const PassInfo *aPass = LLCPassList[i]; @@ -141,6 +136,10 @@ } } +#ifndef NDEBUG + if(!NoVerify) + Passes.add(createVerifierPass()); +#endif // Figure out where we are going to send the output... std::ostream *Out = 0; From lattner at cs.uiuc.edu Wed Jul 27 23:42:22 2005 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Wed, 27 Jul 2005 23:42:22 -0500 Subject: [llvm-commits] CVS: llvm/lib/Target/PowerPC/PPC32ISelPattern.cpp Message-ID: <200507280442.XAA10358@zion.cs.uiuc.edu> Changes in directory llvm/lib/Target/PowerPC: PPC32ISelPattern.cpp updated: 1.107 -> 1.108 --- Log message: Specify the correct number of operands --- Diffs of the changes: (+3 -3) PPC32ISelPattern.cpp | 6 +++--- 1 files changed, 3 insertions(+), 3 deletions(-) Index: llvm/lib/Target/PowerPC/PPC32ISelPattern.cpp diff -u llvm/lib/Target/PowerPC/PPC32ISelPattern.cpp:1.107 llvm/lib/Target/PowerPC/PPC32ISelPattern.cpp:1.108 --- llvm/lib/Target/PowerPC/PPC32ISelPattern.cpp:1.107 Wed Jul 27 22:02:05 2005 +++ llvm/lib/Target/PowerPC/PPC32ISelPattern.cpp Wed Jul 27 23:42:11 2005 @@ -1385,7 +1385,7 @@ BuildMI(BB, PPC::ADDIS, 2, Tmp1).addReg(getGlobalBaseReg()) .addGlobalAddress(GV); else - BuildMI(BB, PPC::LIS, 2, Tmp1).addGlobalAddress(GV); + BuildMI(BB, PPC::LIS, 1, Tmp1).addGlobalAddress(GV); if (GV->hasWeakLinkage() || GV->isExternal()) { BuildMI(BB, PPC::LWZ, 2, Result).addGlobalAddress(GV).addReg(Tmp1); } else { @@ -1441,7 +1441,7 @@ BuildMI(BB, PPC::ADDIS, 2, Tmp1).addReg(getGlobalBaseReg()) .addGlobalAddress(GV); else - BuildMI(BB, PPC::LIS, 2, Tmp1).addGlobalAddress(GV); + BuildMI(BB, PPC::LIS, 1, Tmp1).addGlobalAddress(GV); if (GV->hasWeakLinkage() || GV->isExternal()) { Tmp2 = MakeReg(MVT::i32); BuildMI(BB, PPC::LWZ, 2, Tmp2).addGlobalAddress(GV).addReg(Tmp1); @@ -2499,7 +2499,7 @@ BuildMI(BB, PPC::ADDIS, 2, Tmp2).addReg(getGlobalBaseReg()) .addGlobalAddress(GV); else - BuildMI(BB, PPC::LIS, 2, Tmp2).addGlobalAddress(GV); + BuildMI(BB, PPC::LIS, 1, Tmp2).addGlobalAddress(GV); if (GV->hasWeakLinkage() || GV->isExternal()) { Tmp3 = MakeReg(MVT::i32); BuildMI(BB, PPC::LWZ, 2, Tmp3).addGlobalAddress(GV).addReg(Tmp2); From lattner at cs.uiuc.edu Thu Jul 28 00:23:54 2005 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Thu, 28 Jul 2005 00:23:54 -0500 Subject: [llvm-commits] CVS: llvm/lib/Target/PowerPC/PPC32ISelPattern.cpp Message-ID: <200507280523.AAA10978@zion.cs.uiuc.edu> Changes in directory llvm/lib/Target/PowerPC: PPC32ISelPattern.cpp updated: 1.108 -> 1.109 --- Log message: Eliminate an extra copy from R1 that Nate noticed on function calls that have to write arguments to the stack --- Diffs of the changes: (+2 -1) PPC32ISelPattern.cpp | 3 ++- 1 files changed, 2 insertions(+), 1 deletion(-) Index: llvm/lib/Target/PowerPC/PPC32ISelPattern.cpp diff -u llvm/lib/Target/PowerPC/PPC32ISelPattern.cpp:1.108 llvm/lib/Target/PowerPC/PPC32ISelPattern.cpp:1.109 --- llvm/lib/Target/PowerPC/PPC32ISelPattern.cpp:1.108 Wed Jul 27 23:42:11 2005 +++ llvm/lib/Target/PowerPC/PPC32ISelPattern.cpp Thu Jul 28 00:23:43 2005 @@ -1293,7 +1293,8 @@ MVT::ValueType DestType = N.getValueType(); if (Node->getOpcode() == ISD::CopyFromReg && - MRegisterInfo::isVirtualRegister(cast(Node)->getReg())) + (MRegisterInfo::isVirtualRegister(cast(Node)->getReg()) || + cast(Node)->getReg() == PPC::R1)) // Just use the specified register as our input. return cast(Node)->getReg(); From alenhar2 at cs.uiuc.edu Thu Jul 28 07:44:25 2005 From: alenhar2 at cs.uiuc.edu (Andrew Lenharth) Date: Thu, 28 Jul 2005 07:44:25 -0500 Subject: [llvm-commits] CVS: llvm/include/llvm/CodeGen/MachineCodeEmitter.h Message-ID: <200507281244.HAA20749@zion.cs.uiuc.edu> Changes in directory llvm/include/llvm/CodeGen: MachineCodeEmitter.h updated: 1.26 -> 1.27 --- Log message: Like constants, globals on some platforms are GOT relative. This means they have to be allocated near the GOT, which new doesn't do. So break out the allocate into a new function. Also move GOT index handling into JITResolver. This lets it update the mapping when a Lazy function is JITed. It doesn't managed the table, just the mapping. Note that this is still non-ideal, as any function that takes a function address should also take a GOT index, but that is a lot of changes. The relocation resolve process updates any GOT entry it sees is out of date. --- Diffs of the changes: (+6 -0) MachineCodeEmitter.h | 6 ++++++ 1 files changed, 6 insertions(+) Index: llvm/include/llvm/CodeGen/MachineCodeEmitter.h diff -u llvm/include/llvm/CodeGen/MachineCodeEmitter.h:1.26 llvm/include/llvm/CodeGen/MachineCodeEmitter.h:1.27 --- llvm/include/llvm/CodeGen/MachineCodeEmitter.h:1.26 Thu Apr 21 15:38:00 2005 +++ llvm/include/llvm/CodeGen/MachineCodeEmitter.h Thu Jul 28 07:44:13 2005 @@ -94,6 +94,12 @@ // virtual uint64_t getConstantPoolEntryAddress(unsigned Index) = 0; + // allocateGlobal - Allocate some space for a global variable. This is + // used by the JIT to allocate space in the global variable region. + virtual unsigned char* allocateGlobal(unsigned size, unsigned alignment) { + return new unsigned char[(size_t)size]; + } + /// createDebugEmitter - Return a dynamically allocated machine /// code emitter, which just prints the opcodes and fields out the cout. This /// can be used for debugging users of the MachineCodeEmitter interface. From alenhar2 at cs.uiuc.edu Thu Jul 28 07:44:25 2005 From: alenhar2 at cs.uiuc.edu (Andrew Lenharth) Date: Thu, 28 Jul 2005 07:44:25 -0500 Subject: [llvm-commits] CVS: llvm/lib/ExecutionEngine/JIT/JIT.cpp JITEmitter.cpp Message-ID: <200507281244.HAA20748@zion.cs.uiuc.edu> Changes in directory llvm/lib/ExecutionEngine/JIT: JIT.cpp updated: 1.57 -> 1.58 JITEmitter.cpp updated: 1.72 -> 1.73 --- Log message: Like constants, globals on some platforms are GOT relative. This means they have to be allocated near the GOT, which new doesn't do. So break out the allocate into a new function. Also move GOT index handling into JITResolver. This lets it update the mapping when a Lazy function is JITed. It doesn't managed the table, just the mapping. Note that this is still non-ideal, as any function that takes a function address should also take a GOT index, but that is a lot of changes. The relocation resolve process updates any GOT entry it sees is out of date. --- Diffs of the changes: (+78 -14) JIT.cpp | 3 + JITEmitter.cpp | 89 ++++++++++++++++++++++++++++++++++++++++++++++++--------- 2 files changed, 78 insertions(+), 14 deletions(-) Index: llvm/lib/ExecutionEngine/JIT/JIT.cpp diff -u llvm/lib/ExecutionEngine/JIT/JIT.cpp:1.57 llvm/lib/ExecutionEngine/JIT/JIT.cpp:1.58 --- llvm/lib/ExecutionEngine/JIT/JIT.cpp:1.57 Wed Jul 27 01:12:33 2005 +++ llvm/lib/ExecutionEngine/JIT/JIT.cpp Thu Jul 28 07:44:13 2005 @@ -294,7 +294,8 @@ // actually initialize the global after current function has finished // compilation. uint64_t S = getTargetData().getTypeSize(GV->getType()->getElementType()); - Ptr = new char[(size_t)S]; + unsigned char A = getTargetData().getTypeAlignment(GV->getType()->getElementType()); + Ptr = MCE->allocateGlobal(S, A); state.getPendingGlobals(locked).push_back(GV); } addGlobalMapping(GV, Ptr); Index: llvm/lib/ExecutionEngine/JIT/JITEmitter.cpp diff -u llvm/lib/ExecutionEngine/JIT/JITEmitter.cpp:1.72 llvm/lib/ExecutionEngine/JIT/JITEmitter.cpp:1.73 --- llvm/lib/ExecutionEngine/JIT/JITEmitter.cpp:1.72 Wed Jul 27 01:12:33 2005 +++ llvm/lib/ExecutionEngine/JIT/JITEmitter.cpp Thu Jul 28 07:44:13 2005 @@ -60,6 +60,8 @@ inline unsigned char *allocateStub(unsigned StubSize); inline unsigned char *allocateConstant(unsigned ConstantSize, unsigned Alignment); + inline unsigned char* allocateGlobal(unsigned Size, + unsigned Alignment); inline unsigned char *startFunctionBody(); inline void endFunctionBody(unsigned char *FunctionEnd); inline unsigned char* getGOTBase() const; @@ -115,6 +117,21 @@ return CurConstantPtr; } +unsigned char *JITMemoryManager::allocateGlobal(unsigned Size, + unsigned Alignment) { + // For now, intersperse them with Constants + // Reserve space and align pointer. + CurConstantPtr -= Size; + CurConstantPtr = + (unsigned char *)((intptr_t)CurConstantPtr & ~((intptr_t)Alignment - 1)); + + if (CurConstantPtr < ConstantPool) { + std::cerr << "JIT ran out of memory for Globals!\n"; + abort(); + } + return CurConstantPtr; +} + unsigned char *JITMemoryManager::startFunctionBody() { // Round up to an even multiple of 8 bytes, this should eventually be target // specific. @@ -175,8 +192,13 @@ /// ExternalFnToStubMap - This is the equivalent of FunctionToStubMap for /// external functions. std::map ExternalFnToStubMap; + + //map addresses to indexes in the GOT + std::map revGOTMap; + unsigned nextGOTIndex; + public: - JITResolver(MachineCodeEmitter &mce) : MCE(mce) { + JITResolver(MachineCodeEmitter &mce) : MCE(mce), nextGOTIndex(0) { LazyResolverFn = TheJIT->getJITInfo().getLazyResolverFunction(JITCompilerFn); } @@ -199,6 +221,11 @@ return (void*)LazyResolverFn; } + /// getGOTIndexForAddress - Return a new or existing index in the GOT for + /// and address. This function only manages slots, it does not manage the + /// contents of the slots or the memory associated with the GOT. + unsigned getGOTIndexForAddr(void* addr); + /// JITCompilerFn - This function is called to resolve a stub to a compiled /// address. If the LLVM Function corresponding to the stub has not yet /// been compiled, this function compiles it first. @@ -261,6 +288,17 @@ return Stub; } +unsigned JITResolver::getGOTIndexForAddr(void* addr) { + unsigned idx = revGOTMap[addr]; + if (!idx) { + idx = ++nextGOTIndex; + revGOTMap[addr] = idx; + DEBUG(std::cerr << "Adding GOT entry " << idx + << " for addr " << addr << "\n"); + // ((void**)MemMgr.getGOTBase())[idx] = addr; + } + return idx; +} /// JITCompilerFn - This function is called when a lazy compilation stub has /// been entered. It looks up which function this stub corresponds to, compiles @@ -294,6 +332,15 @@ JR.state.getFunctionToStubMap(locked).erase(F); // FIXME: We could rewrite all references to this stub if we knew them. + + // What we will do is set the compiled function address to map to the + // same GOT entry as the stub so that later clients may update the GOT + // if they see it still using the stub address. + // Note: this is done so the Resolver doesn't have to manage GOT memory + // Do this without allocating map space if the target isn't using a GOT + if(JR.revGOTMap.find(Stub) != JR.revGOTMap.end()) + JR.revGOTMap[Result] = JR.revGOTMap[Stub]; + return Result; } @@ -340,8 +387,7 @@ public: JITEmitter(JIT &jit) - :MemMgr(jit.getJITInfo().needsGOT()), - nextGOTIndex(0) + :MemMgr(jit.getJITInfo().needsGOT()) { TheJIT = &jit; DEBUG(std::cerr << @@ -365,11 +411,10 @@ virtual uint64_t getCurrentPCValue(); virtual uint64_t getCurrentPCOffset(); virtual uint64_t getConstantPoolEntryAddress(unsigned Entry); + virtual unsigned char* allocateGlobal(unsigned size, unsigned alignment); private: void *getPointerToGlobal(GlobalValue *GV, void *Reference, bool NoNeedStub); - unsigned nextGOTIndex; - std::map revGOTMap; }; } @@ -441,14 +486,17 @@ MR.setResultPointer(ResultPtr); - // if we are managing the got, check to see if this pointer has all ready - // been allocated a GOT entry. If not, give it the next one. - if (MemMgr.isManagingGOT()) { - if (!revGOTMap[ResultPtr]) - revGOTMap[ResultPtr] = ++nextGOTIndex; - ((void**)MemMgr.getGOTBase())[revGOTMap[ResultPtr]] = ResultPtr; - if(MR.isGOTRelative()) - MR.setGOTIndex(revGOTMap[ResultPtr]); + // if we are managing the GOT and the relocation wants an index, + // give it one + if (MemMgr.isManagingGOT() && !MR.isConstantPoolIndex() && + MR.isGOTRelative()) { + unsigned idx = getJITResolver(this).getGOTIndexForAddr(ResultPtr); + MR.setGOTIndex(idx); + if (((void**)MemMgr.getGOTBase())[idx] != ResultPtr) { + DEBUG(std::cerr << "GOT was out of date for " << ResultPtr + << " pointing at " << ((void**)MemMgr.getGOTBase())[idx] << "\n"); + ((void**)MemMgr.getGOTBase())[idx] = ResultPtr; + } } } @@ -456,6 +504,16 @@ Relocations.size(), MemMgr.getGOTBase()); } + //Update the GOT entry for F to point to the new code. + if(MemMgr.isManagingGOT()) { + unsigned idx = getJITResolver(this).getGOTIndexForAddr((void*)CurBlock); + if (((void**)MemMgr.getGOTBase())[idx] != (void*)CurBlock) { + DEBUG(std::cerr << "GOT was out of date for " << (void*)CurBlock + << " pointing at " << ((void**)MemMgr.getGOTBase())[idx] << "\n"); + ((void**)MemMgr.getGOTBase())[idx] = (void*)CurBlock; + } + } + DEBUG(std::cerr << "JIT: Finished CodeGen of [" << (void*)CurBlock << "] Function: " << F.getFunction()->getName() << ": " << CurByte-CurBlock << " bytes of text, " @@ -516,6 +574,11 @@ return (intptr_t)ConstantPoolAddresses[ConstantNum]; } +unsigned char* JITEmitter::allocateGlobal(unsigned size, unsigned alignment) +{ + return MemMgr.allocateGlobal(size, alignment); +} + // getCurrentPCValue - This returns the address that the next emitted byte // will be output to. // From alenhar2 at cs.uiuc.edu Thu Jul 28 07:45:31 2005 From: alenhar2 at cs.uiuc.edu (Andrew Lenharth) Date: Thu, 28 Jul 2005 07:45:31 -0500 Subject: [llvm-commits] CVS: llvm/lib/Target/Alpha/AlphaCodeEmitter.cpp AlphaJITInfo.cpp Message-ID: <200507281245.HAA20990@zion.cs.uiuc.edu> Changes in directory llvm/lib/Target/Alpha: AlphaCodeEmitter.cpp updated: 1.3 -> 1.4 AlphaJITInfo.cpp updated: 1.3 -> 1.4 --- Log message: get lazy JITing working. Some of shootout runs now --- Diffs of the changes: (+96 -70) AlphaCodeEmitter.cpp | 4 - AlphaJITInfo.cpp | 162 +++++++++++++++++++++++++++++---------------------- 2 files changed, 96 insertions(+), 70 deletions(-) Index: llvm/lib/Target/Alpha/AlphaCodeEmitter.cpp diff -u llvm/lib/Target/Alpha/AlphaCodeEmitter.cpp:1.3 llvm/lib/Target/Alpha/AlphaCodeEmitter.cpp:1.4 --- llvm/lib/Target/Alpha/AlphaCodeEmitter.cpp:1.3 Wed Jul 27 01:12:33 2005 +++ llvm/lib/Target/Alpha/AlphaCodeEmitter.cpp Thu Jul 28 07:45:20 2005 @@ -178,6 +178,7 @@ MO.getGlobal()->isExternal()) ); unsigned Reloc = 0; int Offset = 0; + bool useGOT = false; switch (MI.getOpcode()) { case Alpha::LDLr: case Alpha::LDQr: @@ -193,6 +194,7 @@ break; case Alpha::LDQl: Reloc = Alpha::reloc_literal; + useGOT = true; break; case Alpha::LDAg: case Alpha::LDAHg: @@ -206,7 +208,7 @@ if (MO.isGlobalAddress()) MCE.addRelocation(MachineRelocation((unsigned)MCE.getCurrentPCOffset(), Reloc, MO.getGlobal(), Offset, - true, true)); + false, useGOT)); else if (MO.isExternalSymbol()) MCE.addRelocation(MachineRelocation((unsigned)MCE.getCurrentPCOffset(), Reloc, MO.getSymbolName(), Offset, Index: llvm/lib/Target/Alpha/AlphaJITInfo.cpp diff -u llvm/lib/Target/Alpha/AlphaJITInfo.cpp:1.3 llvm/lib/Target/Alpha/AlphaJITInfo.cpp:1.4 --- llvm/lib/Target/Alpha/AlphaJITInfo.cpp:1.3 Wed Jul 27 01:12:33 2005 +++ llvm/lib/Target/Alpha/AlphaJITInfo.cpp Thu Jul 28 07:45:20 2005 @@ -23,23 +23,52 @@ using namespace std; using namespace llvm; +#define BUILD_OFormatI(Op, RA, LIT, FUN, RC) \ + ((Op << 26) | (RA << 21) | (LIT << 13) | (1 << 12) | (FUN << 5) | (RC)) +#define BUILD_OFormat(Op, RA, RB, FUN, RC) \ + ((Op << 26) | (RA << 21) | (RB << 16) | (FUN << 5) | (RC)) + #define BUILD_LDA(RD, RS, IMM16) \ ((0x08 << 26) | ((RD) << 21) | ((RS) << 16) | ((IMM16) & 65535)) #define BUILD_LDAH(RD, RS, IMM16) \ ((0x09 << 26) | ((RD) << 21) | ((RS) << 16) | ((IMM16) & 65535)) -#define MERGE_PARTS(HH, HL, LH, LL) \ - (((HH * 65536 + HL) << 32) + (LH * 65536 + LL)) - #define BUILD_LDQ(RD, RS, IMM16) \ ((0x29 << 26) | ((RD) << 21) | ((RS) << 16) | ((IMM16) & 0xFFFF)) #define BUILD_JMP(RD, RS, IMM16) \ - ((0x1A << 26) | ((RD) << 21) | ((RS) << 16) | ((IMM16) & 0xFFFF)) + ((0x1A << 26) | ((RD) << 21) | ((RS) << 16) | (0x00 << 14) | ((IMM16) & 0x3FFF)) +#define BUILD_JSR(RD, RS, IMM16) \ + ((0x1A << 26) | ((RD) << 21) | ((RS) << 16) | (0x01 << 14) | ((IMM16) & 0x3FFF)) -static void EmitBranchToAt(void *At, void *To, bool isCall) { - //FIXME - assert(0); +#define BUILD_SLLi(RD, RS, IMM8) \ + (BUILD_OFormatI(0x12, RS, IMM8, 0x39, RD)) + +#define BUILD_ORi(RD, RS, IMM8) \ + (BUILD_OFormatI(0x11, RS, IMM8, 0x20, RD)) + +#define BUILD_OR(RD, RS, RT) \ + (BUILD_OFormat(0x11, RS, RT, 0x20, RD)) + + + +static void EmitBranchToAt(void *At, void *To) { + unsigned long Fn = (unsigned long)To; + + unsigned *AtI = (unsigned*)At; + + AtI[0] = BUILD_OR(0, 27, 27); + + DEBUG(std::cerr << "Stub targeting " << To << "\n"); + + for (int x = 1; x <= 8; ++x) { + AtI[2*x - 1] = BUILD_SLLi(27,27,8); + unsigned d = (Fn >> (64 - 8 * x)) & 0x00FF; + DEBUG(std::cerr << "outputing " << hex << d << dec << "\n"); + AtI[2*x] = BUILD_ORi(27, 27, d); + } + AtI[17] = BUILD_JMP(31,27,0); //jump, preserving ra, and setting pv + AtI[18] = 0x00FFFFFF; //mark this as a stub } void AlphaJITInfo::replaceMachineCodeForFunction(void *Old, void *New) { @@ -53,55 +82,22 @@ extern "C" { #ifdef __alpha - void AlphaCompilationCallbackC(long* oldsp) + void AlphaCompilationCallbackC(long* oldpv, void* CameFromStub) { - void* CameFromStub = (void*)*(oldsp - 1); - void* CameFromOrig = (void*)*(oldsp - 2); - void* Target = JITCompilerFunction(CameFromStub); //rewrite the stub to an unconditional branch - EmitBranchToAt(CameFromStub, Target, false); + if (((unsigned*)CameFromStub)[18] == 0x00FFFFFF) { + DEBUG(std::cerr << "Came from a stub, rewriting\n"); + EmitBranchToAt(CameFromStub, Target); + } else { + DEBUG(std::cerr << "confused, didn't come from stub at " << CameFromStub + << " old jump vector " << oldpv + << " new jump vector " << Target << "\n"); + } //Change pv to new Target - *(oldsp - 1) = (long)Target; - - //special epilog - register long* RSP asm ("$0") = oldsp; - __asm__ __volatile__ ( - "ldq $16, 0($0)\n" - "ldq $17, 8($0)\n" - "ldq $18, 16($0)\n" - "ldq $19, 24($0)\n" - "ldq $20, 32($0)\n" - "ldq $21, 40($0)\n" - "ldt $f16, 48($0)\n" - "ldt $f17, 56($0)\n" - "ldt $f18, 64($0)\n" - "ldt $f19, 72($0)\n" - "ldt $f20, 80($0)\n" - "ldt $f21, 88($0)\n" - "ldq $9, 96($0)\n" - "ldq $10, 104($0)\n" - "ldq $11, 112($0)\n" - "ldq $12, 120($0)\n" - "ldq $13, 128($0)\n" - "ldq $14, 136($0)\n" - "ldt $f2, 144($0)\n" - "ldt $f3, 152($0)\n" - "ldt $f4, 160($0)\n" - "ldt $f5, 168($0)\n" - "ldt $f6, 176($0)\n" - "ldt $f7, 184($0)\n" - "ldt $f8, 192($0)\n" - "ldt $f9, 200($0)\n" - "ldq $15, 208($0)\n" - "ldq $26, 216($0)\n" - "ldq $27, 224($0)\n" - "bis $30, $0, $0\n" //restore sp - "jmp $31, ($27)\n" //jump to the new function - "and $0, $31, $31\n" //dummy use of r0 - ); + *oldpv = (long)Target; } void AlphaCompilationCallback(void); @@ -114,12 +110,11 @@ ".ent AlphaCompilationCallback\n" "AlphaCompilationCallback:\n" // //get JIT's GOT - // "ldgp\n" + "ldgp $29, 0($27)\n" //Save args, callee saved, and perhaps others? //args: $16-$21 $f16-$f21 (12) //callee: $9-$14 $f2-$f9 (14) //others: fp:$15 ra:$26 pv:$27 (3) - "bis $0, $30, $30\n" //0 = sp "lda $30, -232($30)\n" "stq $16, 0($30)\n" "stq $17, 8($30)\n" @@ -150,8 +145,43 @@ "stq $15, 208($30)\n" "stq $26, 216($30)\n" "stq $27, 224($30)\n" - "bis $16, $0, $0\n" //pass the old sp as the first arg - "bsr $31, AlphaCompilationCallbackC\n" + + "addq $30, 224, $16\n" //pass the addr of saved pv as the first arg + "bis $0, $0, $17\n" //pass the roughly stub addr in second arg + "jsr $26, AlphaCompilationCallbackC\n" //call without saving ra + + "ldq $16, 0($30)\n" + "ldq $17, 8($30)\n" + "ldq $18, 16($30)\n" + "ldq $19, 24($30)\n" + "ldq $20, 32($30)\n" + "ldq $21, 40($30)\n" + "ldt $f16, 48($30)\n" + "ldt $f17, 56($30)\n" + "ldt $f18, 64($30)\n" + "ldt $f19, 72($30)\n" + "ldt $f20, 80($30)\n" + "ldt $f21, 88($30)\n" + "ldq $9, 96($30)\n" + "ldq $10, 104($30)\n" + "ldq $11, 112($30)\n" + "ldq $12, 120($30)\n" + "ldq $13, 128($30)\n" + "ldq $14, 136($30)\n" + "ldt $f2, 144($30)\n" + "ldt $f3, 152($30)\n" + "ldt $f4, 160($30)\n" + "ldt $f5, 168($30)\n" + "ldt $f6, 176($30)\n" + "ldt $f7, 184($30)\n" + "ldt $f8, 192($30)\n" + "ldt $f9, 200($30)\n" + "ldq $15, 208($30)\n" + "ldq $26, 216($30)\n" + "ldq $27, 224($30)\n" //this was updated in the callback with the target + + "lda $30, 232($30)\n" //restore sp + "jmp $31, ($27)\n" //jump to the new function ".end AlphaCompilationCallback\n" ); #else @@ -163,21 +193,15 @@ } void *AlphaJITInfo::emitFunctionStub(void *Fn, MachineCodeEmitter &MCE) { -// // If this is just a call to an external function, emit a branch instead of a -// // call. This means looking up Fn and storing that in R27 so as to appear to -// // have called there originally -// if (Fn != AlphaCompilationCallback) { -// int idx = AlphaJTI->getNewGOTEntry(Fn); -// //R27 = ldq idx(R29) -// //R31 = JMP R27, 0 -// MCE.startFunctionStub(2*4); -// void *Addr = (void*)(intptr_t)MCE.getCurrentPCValue(); -// MCE.emitWord(BUILD_LDQ(27, 29, idx << 3)); -// MCE.emitWord(BUILD_JMP(31, 27, 0)); -// return MCE.finishFunctionStub(0); -// } - - assert(0 && "Need to be able to jump to this guy too"); + //assert(Fn == AlphaCompilationCallback && "Where are you going?\n"); + //Do things in a stupid slow way! + MCE.startFunctionStub(19*4); + void* Addr = (void*)(intptr_t)MCE.getCurrentPCValue(); + for (int x = 0; x < 19; ++ x) + MCE.emitWord(0); + EmitBranchToAt(Addr, Fn); + DEBUG(std::cerr << "Emitting Stub to " << Fn << " at [" << Addr << "]\n"); + return MCE.finishFunctionStub(0); } TargetJITInfo::LazyResolverFn From reid at x10sys.com Thu Jul 28 11:26:08 2005 From: reid at x10sys.com (Reid Spencer) Date: Thu, 28 Jul 2005 11:26:08 -0500 Subject: [llvm-commits] CVS: llvm/lib/System/Unix/Path.inc Message-ID: <200507281626.LAA23156@zion.cs.uiuc.edu> Changes in directory llvm/lib/System/Unix: Path.inc updated: 1.43 -> 1.44 --- Log message: Fix a problem in getDirectoryContents where sub-directory names were appended to a path string that didn't end in a slash, yielding invalid path names. Path contribute by Nicholas Riley. --- Diffs of the changes: (+14 -6) Path.inc | 20 ++++++++++++++------ 1 files changed, 14 insertions(+), 6 deletions(-) Index: llvm/lib/System/Unix/Path.inc diff -u llvm/lib/System/Unix/Path.inc:1.43 llvm/lib/System/Unix/Path.inc:1.44 --- llvm/lib/System/Unix/Path.inc:1.43 Sat Jul 9 13:42:02 2005 +++ llvm/lib/System/Unix/Path.inc Thu Jul 28 11:25:57 2005 @@ -53,6 +53,13 @@ # undef HAVE_MKDTEMP #endif +namespace { +inline bool lastIsSlash(const std::string& path) { + return !path.empty() && path[path.length() - 1] == '/'; +} + +} + namespace llvm { using namespace sys; @@ -437,11 +444,15 @@ if (direntries == 0) ThrowErrno(path + ": can't open directory"); + std::string dirPath = path; + if (!lastIsSlash(dirPath)) + dirPath += '/'; + result.clear(); struct dirent* de = ::readdir(direntries); for ( ; de != 0; de = ::readdir(direntries)) { if (de->d_name[0] != '.') { - Path aPath(path + (const char*)de->d_name); + Path aPath(dirPath + (const char*)de->d_name); struct stat buf; if (0 != stat(aPath.path.c_str(), &buf)) { int stat_errno = errno; @@ -477,11 +488,8 @@ if (name.empty()) return false; std::string save(path); - if (!path.empty()) { - size_t last = path.size() - 1; - if (path[last] != '/') - path += '/'; - } + if (!lastIsSlash(path)) + path += '/'; path += name; if (!isValid()) { path = save; From alenhar2 at cs.uiuc.edu Thu Jul 28 12:02:18 2005 From: alenhar2 at cs.uiuc.edu (Andrew Lenharth) Date: Thu, 28 Jul 2005 12:02:18 -0500 Subject: [llvm-commits] CVS: llvm-test/RunSafely.sh RunSafelyAndStable.sh Message-ID: <200507281702.MAA24016@zion.cs.uiuc.edu> Changes in directory llvm-test: RunSafely.sh updated: 1.17 -> 1.18 RunSafelyAndStable.sh updated: 1.3 -> 1.4 --- Log message: So if gdb gets in a loop reading stack frames, disks fill up. a backtrace of 100 frames should be enough for anybody --- Diffs of the changes: (+2 -2) RunSafely.sh | 2 +- RunSafelyAndStable.sh | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) Index: llvm-test/RunSafely.sh diff -u llvm-test/RunSafely.sh:1.17 llvm-test/RunSafely.sh:1.18 --- llvm-test/RunSafely.sh:1.17 Wed Dec 29 21:10:38 2004 +++ llvm-test/RunSafely.sh Thu Jul 28 12:02:07 2005 @@ -67,7 +67,7 @@ fi corefile=`ls core* | head -n 1` - echo "where" > StackTrace.$$ + echo "where 100" > StackTrace.$$ $GDB -q -batch --command=StackTrace.$$ --core=$corefile $PROGRAM < /dev/null rm -f StackTrace.$$ $corefile fi Index: llvm-test/RunSafelyAndStable.sh diff -u llvm-test/RunSafelyAndStable.sh:1.3 llvm-test/RunSafelyAndStable.sh:1.4 --- llvm-test/RunSafelyAndStable.sh:1.3 Wed Nov 10 13:49:27 2004 +++ llvm-test/RunSafelyAndStable.sh Thu Jul 28 12:02:07 2005 @@ -63,7 +63,7 @@ fi corefile=`ls core* | head -n 1` - echo "where" > StackTrace.$$ + echo "where 100" > StackTrace.$$ $GDB -q -batch --command=StackTrace.$$ --core=$corefile $PROGRAM < /dev/null rm -f StackTrace.$$ $corefile exit 0 From lattner at cs.uiuc.edu Thu Jul 28 12:54:12 2005 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Thu, 28 Jul 2005 12:54:12 -0500 Subject: [llvm-commits] CVS: llvm-test/External/SPEC/CFP2000/168.wupwise/Makefile Message-ID: <200507281754.MAA25488@zion.cs.uiuc.edu> Changes in directory llvm-test/External/SPEC/CFP2000/168.wupwise: Makefile updated: 1.2 -> 1.3 --- Log message: Add the tolerance allowed by spec --- Diffs of the changes: (+2 -0) Makefile | 2 ++ 1 files changed, 2 insertions(+) Index: llvm-test/External/SPEC/CFP2000/168.wupwise/Makefile diff -u llvm-test/External/SPEC/CFP2000/168.wupwise/Makefile:1.2 llvm-test/External/SPEC/CFP2000/168.wupwise/Makefile:1.3 --- llvm-test/External/SPEC/CFP2000/168.wupwise/Makefile:1.2 Tue Jul 19 14:05:46 2005 +++ llvm-test/External/SPEC/CFP2000/168.wupwise/Makefile Thu Jul 28 12:54:01 2005 @@ -9,5 +9,7 @@ STDOUT_FILENAME = wupwise.out NAGFORTRAN_FLAGS = -dusty -dcfuns +FP_TOLERANCE=0.005 + include $(LEVEL)/Makefile.FORTRAN include ../../Makefile.spec2000 From alenhar2 at cs.uiuc.edu Thu Jul 28 13:14:11 2005 From: alenhar2 at cs.uiuc.edu (Andrew Lenharth) Date: Thu, 28 Jul 2005 13:14:11 -0500 Subject: [llvm-commits] CVS: llvm/include/llvm/CodeGen/MachineCodeEmitter.h Message-ID: <200507281814.NAA25695@zion.cs.uiuc.edu> Changes in directory llvm/include/llvm/CodeGen: MachineCodeEmitter.h updated: 1.27 -> 1.28 --- Log message: new is not a valid default anywhere, so make this pure virtual --- Diffs of the changes: (+2 -5) MachineCodeEmitter.h | 7 ++----- 1 files changed, 2 insertions(+), 5 deletions(-) Index: llvm/include/llvm/CodeGen/MachineCodeEmitter.h diff -u llvm/include/llvm/CodeGen/MachineCodeEmitter.h:1.27 llvm/include/llvm/CodeGen/MachineCodeEmitter.h:1.28 --- llvm/include/llvm/CodeGen/MachineCodeEmitter.h:1.27 Thu Jul 28 07:44:13 2005 +++ llvm/include/llvm/CodeGen/MachineCodeEmitter.h Thu Jul 28 13:13:59 2005 @@ -94,11 +94,8 @@ // virtual uint64_t getConstantPoolEntryAddress(unsigned Index) = 0; - // allocateGlobal - Allocate some space for a global variable. This is - // used by the JIT to allocate space in the global variable region. - virtual unsigned char* allocateGlobal(unsigned size, unsigned alignment) { - return new unsigned char[(size_t)size]; - } + // allocateGlobal - Allocate some space for a global variable. + virtual unsigned char* allocateGlobal(unsigned size, unsigned alignment) = 0; /// createDebugEmitter - Return a dynamically allocated machine /// code emitter, which just prints the opcodes and fields out the cout. This From alenhar2 at cs.uiuc.edu Thu Jul 28 13:14:11 2005 From: alenhar2 at cs.uiuc.edu (Andrew Lenharth) Date: Thu, 28 Jul 2005 13:14:11 -0500 Subject: [llvm-commits] CVS: llvm/lib/CodeGen/MachineCodeEmitter.cpp ELFWriter.cpp Message-ID: <200507281814.NAA25693@zion.cs.uiuc.edu> Changes in directory llvm/lib/CodeGen: MachineCodeEmitter.cpp updated: 1.23 -> 1.24 ELFWriter.cpp updated: 1.13 -> 1.14 --- Log message: new is not a valid default anywhere, so make this pure virtual --- Diffs of the changes: (+12 -0) ELFWriter.cpp | 5 +++++ MachineCodeEmitter.cpp | 7 +++++++ 2 files changed, 12 insertions(+) Index: llvm/lib/CodeGen/MachineCodeEmitter.cpp diff -u llvm/lib/CodeGen/MachineCodeEmitter.cpp:1.23 llvm/lib/CodeGen/MachineCodeEmitter.cpp:1.24 --- llvm/lib/CodeGen/MachineCodeEmitter.cpp:1.23 Thu Apr 21 17:33:33 2005 +++ llvm/lib/CodeGen/MachineCodeEmitter.cpp Thu Jul 28 13:13:59 2005 @@ -51,6 +51,9 @@ std::cout << " "; } + virtual unsigned char* allocateGlobal(unsigned size, unsigned alignment) + { return 0; } + uint64_t getConstantPoolEntryAddress(unsigned Num) { return 0; } uint64_t getCurrentPCValue() { return 0; } uint64_t getCurrentPCOffset() { return 0; } @@ -142,6 +145,10 @@ uint64_t getConstantPoolEntryAddress(unsigned Num) { return MCE.getConstantPoolEntryAddress(Num); } + + virtual unsigned char* allocateGlobal(unsigned size, unsigned alignment) + { return MCE.allocateGlobal(size, alignment); } + uint64_t getCurrentPCValue() { return MCE.getCurrentPCValue(); } Index: llvm/lib/CodeGen/ELFWriter.cpp diff -u llvm/lib/CodeGen/ELFWriter.cpp:1.13 llvm/lib/CodeGen/ELFWriter.cpp:1.14 --- llvm/lib/CodeGen/ELFWriter.cpp:1.13 Wed Jul 27 01:12:33 2005 +++ llvm/lib/CodeGen/ELFWriter.cpp Thu Jul 28 13:13:59 2005 @@ -85,6 +85,11 @@ return 0; } + virtual unsigned char* allocateGlobal(unsigned size, unsigned alignment) { + assert(0 && "Globals not implemented yet!"); + return 0; + } + /// JIT SPECIFIC FUNCTIONS - DO NOT IMPLEMENT THESE HERE! void startFunctionStub(unsigned StubSize) { assert(0 && "JIT specific function called!"); From alenhar2 at cs.uiuc.edu Thu Jul 28 13:14:59 2005 From: alenhar2 at cs.uiuc.edu (Andrew Lenharth) Date: Thu, 28 Jul 2005 13:14:59 -0500 Subject: [llvm-commits] CVS: llvm/lib/Target/Alpha/AlphaCodeEmitter.cpp AlphaISelPattern.cpp AlphaInstrFormats.td AlphaInstrInfo.td AlphaJITInfo.cpp AlphaRelocations.h Message-ID: <200507281814.NAA25741@zion.cs.uiuc.edu> Changes in directory llvm/lib/Target/Alpha: AlphaCodeEmitter.cpp updated: 1.4 -> 1.5 AlphaISelPattern.cpp updated: 1.155 -> 1.156 AlphaInstrFormats.td updated: 1.5 -> 1.6 AlphaInstrInfo.td updated: 1.54 -> 1.55 AlphaJITInfo.cpp updated: 1.4 -> 1.5 AlphaRelocations.h updated: 1.1 -> 1.2 --- Log message: support bsr, and more .td simplification --- Diffs of the changes: (+76 -48) AlphaCodeEmitter.cpp | 3 ++ AlphaISelPattern.cpp | 24 +++++++++---------- AlphaInstrFormats.td | 16 +++++++++++- AlphaInstrInfo.td | 64 +++++++++++++++++++++++++-------------------------- AlphaJITInfo.cpp | 16 ++++++++++-- AlphaRelocations.h | 1 6 files changed, 76 insertions(+), 48 deletions(-) Index: llvm/lib/Target/Alpha/AlphaCodeEmitter.cpp diff -u llvm/lib/Target/Alpha/AlphaCodeEmitter.cpp:1.4 llvm/lib/Target/Alpha/AlphaCodeEmitter.cpp:1.5 --- llvm/lib/Target/Alpha/AlphaCodeEmitter.cpp:1.4 Thu Jul 28 07:45:20 2005 +++ llvm/lib/Target/Alpha/AlphaCodeEmitter.cpp Thu Jul 28 13:14:47 2005 @@ -180,6 +180,9 @@ int Offset = 0; bool useGOT = false; switch (MI.getOpcode()) { + case Alpha::BSR: + Reloc = Alpha::reloc_bsr; + break; case Alpha::LDLr: case Alpha::LDQr: case Alpha::LDBUr: Index: llvm/lib/Target/Alpha/AlphaISelPattern.cpp diff -u llvm/lib/Target/Alpha/AlphaISelPattern.cpp:1.155 llvm/lib/Target/Alpha/AlphaISelPattern.cpp:1.156 --- llvm/lib/Target/Alpha/AlphaISelPattern.cpp:1.155 Wed Jul 27 01:12:33 2005 +++ llvm/lib/Target/Alpha/AlphaISelPattern.cpp Thu Jul 28 13:14:47 2005 @@ -859,7 +859,7 @@ unsigned Opc; if (EnableAlphaFTOI) { Opc = isDouble ? Alpha::FTOIT : Alpha::FTOIS; - BuildMI(BB, Opc, 1, dst).addReg(src); + BuildMI(BB, Opc, 1, dst).addReg(src).addReg(Alpha::F31); } else { //The hard way: // Spill the integer to memory and reload it from there. @@ -886,7 +886,7 @@ unsigned Opc; if (EnableAlphaFTOI) { Opc = isDouble?Alpha::ITOFT:Alpha::ITOFS; - BuildMI(BB, Opc, 1, dst).addReg(src); + BuildMI(BB, Opc, 1, dst).addReg(src).addReg(Alpha::R31); } else { //The hard way: // Spill the integer to memory and reload it from there. @@ -946,7 +946,7 @@ //assert(0 && "Setcc On float?\n"); std::cerr << "Setcc on float!\n"; Tmp3 = MakeReg(MVT::f64); - BuildMI(BB, Alpha::CVTST, 1, Tmp3).addReg(Tmp1); + BuildMI(BB, Alpha::CVTST, 1, Tmp3).addReg(Alpha::F31).addReg(Tmp1); Tmp1 = Tmp3; } if (SetCC->getOperand(1).getValueType() == MVT::f32) @@ -954,7 +954,7 @@ //assert (0 && "Setcc On float?\n"); std::cerr << "Setcc on float!\n"; Tmp3 = MakeReg(MVT::f64); - BuildMI(BB, Alpha::CVTST, 1, Tmp3).addReg(Tmp2); + BuildMI(BB, Alpha::CVTST, 1, Tmp3).addReg(Alpha::F31).addReg(Tmp2); Tmp2 = Tmp3; } @@ -1447,10 +1447,10 @@ Tmp2 = SelectExpr(N.getOperand(0).getOperand(1)); MoveInt2FP(Tmp1, Tmp4, true); MoveInt2FP(Tmp2, Tmp5, true); - BuildMI(BB, Alpha::CVTQT, 1, Tmp6).addReg(Tmp4); - BuildMI(BB, Alpha::CVTQT, 1, Tmp7).addReg(Tmp5); + BuildMI(BB, Alpha::CVTQT, 1, Tmp6).addReg(Alpha::F31).addReg(Tmp4); + BuildMI(BB, Alpha::CVTQT, 1, Tmp7).addReg(Alpha::F31).addReg(Tmp5); BuildMI(BB, Alpha::DIVT, 2, Tmp8).addReg(Tmp6).addReg(Tmp7); - BuildMI(BB, Alpha::CVTTQ, 1, Tmp9).addReg(Tmp8); + BuildMI(BB, Alpha::CVTTQ, 1, Tmp9).addReg(Alpha::F31).addReg(Tmp8); MoveFP2Int(Tmp9, Result, true); return Result; } @@ -1925,11 +1925,11 @@ if (SrcType == MVT::f32) { Tmp2 = MakeReg(MVT::f64); - BuildMI(BB, Alpha::CVTST, 1, Tmp2).addReg(Tmp1); + BuildMI(BB, Alpha::CVTST, 1, Tmp2).addReg(Alpha::F31).addReg(Tmp1); Tmp1 = Tmp2; } Tmp2 = MakeReg(MVT::f64); - BuildMI(BB, Alpha::CVTTQ, 1, Tmp2).addReg(Tmp1); + BuildMI(BB, Alpha::CVTTQ, 1, Tmp2).addReg(Alpha::F31).addReg(Tmp1); MoveFP2Int(Tmp2, Result, true); return Result; @@ -2153,7 +2153,7 @@ N.getOperand(0).getValueType() == MVT::f64 && "only f64 to f32 conversion supported here"); Tmp1 = SelectExpr(N.getOperand(0)); - BuildMI(BB, Alpha::CVTTS, 1, Result).addReg(Tmp1); + BuildMI(BB, Alpha::CVTTS, 1, Result).addReg(Alpha::F31).addReg(Tmp1); return Result; case ISD::FP_EXTEND: @@ -2161,7 +2161,7 @@ N.getOperand(0).getValueType() == MVT::f32 && "only f32 to f64 conversion supported here"); Tmp1 = SelectExpr(N.getOperand(0)); - BuildMI(BB, Alpha::CVTST, 1, Result).addReg(Tmp1); + BuildMI(BB, Alpha::CVTST, 1, Result).addReg(Alpha::F31).addReg(Tmp1); return Result; case ISD::ConstantFP: @@ -2186,7 +2186,7 @@ Tmp2 = MakeReg(MVT::f64); MoveInt2FP(Tmp1, Tmp2, true); Opc = DestType == MVT::f64 ? Alpha::CVTQT : Alpha::CVTQS; - BuildMI(BB, Opc, 1, Result).addReg(Tmp2); + BuildMI(BB, Opc, 1, Result).addReg(Alpha::F31).addReg(Tmp2); return Result; } } Index: llvm/lib/Target/Alpha/AlphaInstrFormats.td diff -u llvm/lib/Target/Alpha/AlphaInstrFormats.td:1.5 llvm/lib/Target/Alpha/AlphaInstrFormats.td:1.6 --- llvm/lib/Target/Alpha/AlphaInstrFormats.td:1.5 Fri Jul 22 15:50:29 2005 +++ llvm/lib/Target/Alpha/AlphaInstrFormats.td Thu Jul 28 13:14:47 2005 @@ -153,11 +153,25 @@ } //3.3.4 -class FPForm opcode, bits<11> fun, dag OL, string asmstr> : InstAlpha { +class FPForm opcode, bits<11> fun, string asmstr> + : InstAlpha { + bits<5> Fc; bits<5> Fa; bits<5> Fb; bits<11> Function = fun; + + let Inst{25-21} = Fa; + let Inst{20-16} = Fb; + let Inst{15-5} = Function; + let Inst{4-0} = Fc; +} + +class FPFormCM opcode, bits<11> fun, dag OL, string asmstr> + : InstAlpha { bits<5> Fc; + bits<5> Fa; + bits<5> Fb; + bits<11> Function = fun; let Inst{25-21} = Fa; let Inst{20-16} = Fb; Index: llvm/lib/Target/Alpha/AlphaInstrInfo.td diff -u llvm/lib/Target/Alpha/AlphaInstrInfo.td:1.54 llvm/lib/Target/Alpha/AlphaInstrInfo.td:1.55 --- llvm/lib/Target/Alpha/AlphaInstrInfo.td:1.54 Fri Jul 22 15:50:29 2005 +++ llvm/lib/Target/Alpha/AlphaInstrInfo.td Thu Jul 28 13:14:47 2005 @@ -98,17 +98,17 @@ "cmovne $RCOND,$L,$RDEST">; //CMOVE if RCOND != zero //conditional moves, fp - def FCMOVEQ : FPForm<0x17, 0x02A, (ops FPRC:$RDEST, FPRC:$RSRC2, FPRC:$RSRC, FPRC:$RCOND), + def FCMOVEQ : FPFormCM<0x17, 0x02A, (ops FPRC:$RDEST, FPRC:$RSRC2, FPRC:$RSRC, FPRC:$RCOND), "fcmoveq $RCOND,$RSRC,$RDEST">; //FCMOVE if = zero - def FCMOVGE : FPForm<0x17, 0x02D, (ops FPRC:$RDEST, FPRC:$RSRC2, FPRC:$RSRC, FPRC:$RCOND), + def FCMOVGE : FPFormCM<0x17, 0x02D, (ops FPRC:$RDEST, FPRC:$RSRC2, FPRC:$RSRC, FPRC:$RCOND), "fcmovge $RCOND,$RSRC,$RDEST">; //FCMOVE if >= zero - def FCMOVGT : FPForm<0x17, 0x02F, (ops FPRC:$RDEST, FPRC:$RSRC2, FPRC:$RSRC, FPRC:$RCOND), + def FCMOVGT : FPFormCM<0x17, 0x02F, (ops FPRC:$RDEST, FPRC:$RSRC2, FPRC:$RSRC, FPRC:$RCOND), "fcmovgt $RCOND,$RSRC,$RDEST">; //FCMOVE if > zero - def FCMOVLE : FPForm<0x17, 0x02E, (ops FPRC:$RDEST, FPRC:$RSRC2, FPRC:$RSRC, FPRC:$RCOND), + def FCMOVLE : FPFormCM<0x17, 0x02E, (ops FPRC:$RDEST, FPRC:$RSRC2, FPRC:$RSRC, FPRC:$RCOND), "fcmovle $RCOND,$RSRC,$RDEST">; //FCMOVE if <= zero - def FCMOVLT : FPForm<0x17, 0x02, (ops FPRC:$RDEST, FPRC:$RSRC2, FPRC:$RSRC, FPRC:$RCOND), + def FCMOVLT : FPFormCM<0x17, 0x02, (ops FPRC:$RDEST, FPRC:$RSRC2, FPRC:$RSRC, FPRC:$RCOND), "fcmovlt $RCOND,$RSRC,$RDEST">; // FCMOVE if < zero - def FCMOVNE : FPForm<0x17, 0x02B, (ops FPRC:$RDEST, FPRC:$RSRC2, FPRC:$RSRC, FPRC:$RCOND), + def FCMOVNE : FPFormCM<0x17, 0x02B, (ops FPRC:$RDEST, FPRC:$RSRC2, FPRC:$RSRC, FPRC:$RCOND), "fcmovne $RCOND,$RSRC,$RDEST">; //FCMOVE if != zero } @@ -232,10 +232,10 @@ def CMPULTi : OFormL<0x10, 0x1D, "cmpult $RA,$L,$RC">; //Compare unsigned quadword less than //Comparison, FP -def CMPTEQ : FPForm<0x16, 0x0A5, (ops FPRC:$RC, FPRC:$RA, FPRC:$RB), "cmpteq/su $RA,$RB,$RC">; //Compare T_floating equal -def CMPTLE : FPForm<0x16, 0x0A7, (ops FPRC:$RC, FPRC:$RA, FPRC:$RB), "cmptle/su $RA,$RB,$RC">; //Compare T_floating less than or equal -def CMPTLT : FPForm<0x16, 0x0A6, (ops FPRC:$RC, FPRC:$RA, FPRC:$RB), "cmptlt/su $RA,$RB,$RC">; //Compare T_floating less than -def CMPTUN : FPForm<0x16, 0x0A4, (ops FPRC:$RC, FPRC:$RA, FPRC:$RB), "cmptun/su $RA,$RB,$RC">; //Compare T_floating unordered +def CMPTEQ : FPForm<0x16, 0x0A5, "cmpteq/su $RA,$RB,$RC">; //Compare T_floating equal +def CMPTLE : FPForm<0x16, 0x0A7, "cmptle/su $RA,$RB,$RC">; //Compare T_floating less than or equal +def CMPTLT : FPForm<0x16, 0x0A6, "cmptlt/su $RA,$RB,$RC">; //Compare T_floating less than +def CMPTUN : FPForm<0x16, 0x0A4, "cmptun/su $RA,$RB,$RC">; //Compare T_floating unordered //There are in the Multimedia extentions, so let's not use them yet def MAXSB8 : OForm<0x1C, 0x3E, "MAXSB8 $RA,$RB,$RC">; //Vector signed byte maximum @@ -350,37 +350,37 @@ def FBNE : FBForm<0x35, "fbne $RA,$DISP">; //Floating branch if != zero //Funky Floating point ops -def CPYS : FPForm<0x17, 0x020, (ops FPRC:$RC, FPRC:$RA, FPRC:$RB), "cpys $RA,$RB,$RC">; //Copy sign -def CPYSE : FPForm<0x17, 0x022, (ops FPRC:$RC, FPRC:$RA, FPRC:$RB), "cpyse $RA,$RB,$RC">; //Copy sign and exponent -def CPYSN : FPForm<0x17, 0x021, (ops FPRC:$RC, FPRC:$RA, FPRC:$RB), "cpysn $RA,$RB,$RC">; //Copy sign negate +def CPYS : FPForm<0x17, 0x020, "cpys $RA,$RB,$RC">; //Copy sign +def CPYSE : FPForm<0x17, 0x022, "cpyse $RA,$RB,$RC">; //Copy sign and exponent +def CPYSN : FPForm<0x17, 0x021, "cpysn $RA,$RB,$RC">; //Copy sign negate //Basic Floating point ops -def ADDS : FPForm<0x16, 0x080, (ops FPRC:$RC, FPRC:$RA, FPRC:$RB), "adds/su $RA,$RB,$RC">; //Add S_floating -def ADDT : FPForm<0x16, 0x0A0, (ops FPRC:$RC, FPRC:$RA, FPRC:$RB), "addt/su $RA,$RB,$RC">; //Add T_floating -def SUBS : FPForm<0x16, 0x081, (ops FPRC:$RC, FPRC:$RA, FPRC:$RB), "subs/su $RA,$RB,$RC">; //Subtract S_floating -def SUBT : FPForm<0x16, 0x0A1, (ops FPRC:$RC, FPRC:$RA, FPRC:$RB), "subt/su $RA,$RB,$RC">; //Subtract T_floating -def DIVS : FPForm<0x16, 0x083, (ops FPRC:$RC, FPRC:$RA, FPRC:$RB), "divs/su $RA,$RB,$RC">; //Divide S_floating -def DIVT : FPForm<0x16, 0x0A3, (ops FPRC:$RC, FPRC:$RA, FPRC:$RB), "divt/su $RA,$RB,$RC">; //Divide T_floating -def MULS : FPForm<0x16, 0x082, (ops FPRC:$RC, FPRC:$RA, FPRC:$RB), "muls/su $RA,$RB,$RC">; //Multiply S_floating -def MULT : FPForm<0x16, 0x0A2, (ops FPRC:$RC, FPRC:$RA, FPRC:$RB), "mult/su $RA,$RB,$RC">; //Multiply T_floating -def SQRTS : FPForm<0x14, 0x08B, (ops FPRC:$RC, FPRC:$RA, FPRC:$RB), "sqrts $RA,$RB,$RC">; //Square root S_floating -def SQRTT : FPForm<0x14, 0x0AB, (ops FPRC:$RC, FPRC:$RA, FPRC:$RB), "sqrtt $RA,$RB,$RC">; //Square root T_floating +def ADDS : FPForm<0x16, 0x080, "adds/su $RA,$RB,$RC">; //Add S_floating +def ADDT : FPForm<0x16, 0x0A0, "addt/su $RA,$RB,$RC">; //Add T_floating +def SUBS : FPForm<0x16, 0x081, "subs/su $RA,$RB,$RC">; //Subtract S_floating +def SUBT : FPForm<0x16, 0x0A1, "subt/su $RA,$RB,$RC">; //Subtract T_floating +def DIVS : FPForm<0x16, 0x083, "divs/su $RA,$RB,$RC">; //Divide S_floating +def DIVT : FPForm<0x16, 0x0A3, "divt/su $RA,$RB,$RC">; //Divide T_floating +def MULS : FPForm<0x16, 0x082, "muls/su $RA,$RB,$RC">; //Multiply S_floating +def MULT : FPForm<0x16, 0x0A2, "mult/su $RA,$RB,$RC">; //Multiply T_floating +def SQRTS : FPForm<0x14, 0x08B, "sqrts $RA,$RB,$RC">; //Square root S_floating +def SQRTT : FPForm<0x14, 0x0AB, "sqrtt $RA,$RB,$RC">; //Square root T_floating //INT reg to FP reg and back again //not supported on 21164 -def FTOIS : FPForm<0x1C, 0x078, (ops FPRC:$RC, GPRC:$RA), "ftois $RA,$RC">; //Floating to integer move, S_floating -def FTOIT : FPForm<0x1C, 0x070, (ops FPRC:$RC, GPRC:$RA), "ftoit $RA,$RC">; //Floating to integer move, T_floating -def ITOFS : FPForm<0x14, 0x004, (ops FPRC:$RC, GPRC:$RA), "itofs $RA,$RC">; //Integer to floating move, S_floating -def ITOFT : FPForm<0x14, 0x024, (ops FPRC:$RC, GPRC:$RA), "itoft $RA,$RC">; //Integer to floating move, T_floating +def FTOIS : FPForm<0x1C, 0x078, "ftois $RA,$RC">; //Floating to integer move, S_floating +def FTOIT : FPForm<0x1C, 0x070, "ftoit $RA,$RC">; //Floating to integer move, T_floating +def ITOFS : FPForm<0x14, 0x004, "itofs $RA,$RC">; //Integer to floating move, S_floating +def ITOFT : FPForm<0x14, 0x024, "itoft $RA,$RC">; //Integer to floating move, T_floating //CVTLQ F-P 17.010 Convert longword to quadword //CVTQL F-P 17.030 Convert quadword to longword //These use SW completion, may not have function code for that set right (matters for JIT) -def CVTQS : FPForm<0x16, 0x0BC, (ops FPRC:$RC, FPRC:$RA), "cvtqs $RA,$RC">; //Convert quadword to S_floating -def CVTQT : FPForm<0x16, 0x0BE, (ops FPRC:$RC, FPRC:$RA), "cvtqt $RA,$RC">; //Convert quadword to T_floating -def CVTST : FPForm<0x16, 0x2AC, (ops FPRC:$RC, FPRC:$RA), "cvtsts $RA,$RC">; //Convert S_floating to T_floating -def CVTTQ : FPForm<0x16, 0x0AF, (ops FPRC:$RC, FPRC:$RA), "cvttq/svc $RA,$RC">; //Convert T_floating to quadword -def CVTTS : FPForm<0x16, 0x2AC, (ops FPRC:$RC, FPRC:$RA), "cvtts/su $RA,$RC">; //Convert T_floating to S_floating +def CVTQS : FPForm<0x16, 0x0BC, "cvtqs $RB,$RC">; //Convert quadword to S_floating +def CVTQT : FPForm<0x16, 0x0BE, "cvtqt $RB,$RC">; //Convert quadword to T_floating +def CVTST : FPForm<0x16, 0x2AC, "cvtsts $RB,$RC">; //Convert S_floating to T_floating +def CVTTQ : FPForm<0x16, 0x0AF, "cvttq/svc $RB,$RC">; //Convert T_floating to quadword +def CVTTS : FPForm<0x16, 0x2AC, "cvtts/su $RB,$RC">; //Convert T_floating to S_floating //S_floating : IEEE Single //T_floating : IEEE Double Index: llvm/lib/Target/Alpha/AlphaJITInfo.cpp diff -u llvm/lib/Target/Alpha/AlphaJITInfo.cpp:1.4 llvm/lib/Target/Alpha/AlphaJITInfo.cpp:1.5 --- llvm/lib/Target/Alpha/AlphaJITInfo.cpp:1.4 Thu Jul 28 07:45:20 2005 +++ llvm/lib/Target/Alpha/AlphaJITInfo.cpp Thu Jul 28 13:14:47 2005 @@ -245,6 +245,7 @@ for (unsigned i = 0; i != NumRelocs; ++i, ++MR) { unsigned *RelocPos = (unsigned*)Function + MR->getMachineCodeOffset()/4; long idx = 0; + bool doCommon = true; switch ((Alpha::RelocationType)MR->getRelocationType()) { default: assert(0 && "Unknown relocation type!"); case Alpha::reloc_literal: @@ -289,9 +290,18 @@ assert(0 && "Cannot handle gpdist yet"); } break; + case Alpha::reloc_bsr: { + idx = (((unsigned char*)MR->getResultPointer() - + (unsigned char*)RelocPos) >> 2) + 1; //skip first 2 inst of fun + *RelocPos |= (idx & ((1 << 21)-1)); + doCommon = false; + break; + } + } + if (doCommon) { + short x = (short)idx; + assert(x == idx); + *(short*)RelocPos = x; } - short x = (short)idx; - assert(x == idx); - *(short*)RelocPos = x; } } Index: llvm/lib/Target/Alpha/AlphaRelocations.h diff -u llvm/lib/Target/Alpha/AlphaRelocations.h:1.1 llvm/lib/Target/Alpha/AlphaRelocations.h:1.2 --- llvm/lib/Target/Alpha/AlphaRelocations.h:1.1 Fri Jul 22 15:52:16 2005 +++ llvm/lib/Target/Alpha/AlphaRelocations.h Thu Jul 28 13:14:47 2005 @@ -23,6 +23,7 @@ reloc_gprellow, reloc_gprelhigh, reloc_gpdist, + reloc_bsr, }; } } From lattner at cs.uiuc.edu Thu Jul 28 13:50:42 2005 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Thu, 28 Jul 2005 13:50:42 -0500 Subject: [llvm-commits] CVS: llvm-gcc/gcc/llvm-expand.c llvm-representation.h llvm-types.c Message-ID: <200507281850.NAA26020@zion.cs.uiuc.edu> Changes in directory llvm-gcc/gcc: llvm-expand.c updated: 1.109 -> 1.110 llvm-representation.h updated: 1.18 -> 1.19 llvm-types.c updated: 1.25 -> 1.26 --- Log message: Add a new set of LLVM_TARGET_ARG_* macros, which can be used by targets to customize the calling convention used by the CFE for specific targets. This is useful on targets that like to do wacky things like pass FP values in integer registers. --- Diffs of the changes: (+161 -55) llvm-expand.c | 95 ++++++++++++++++++++++++++++++++++---------------- llvm-representation.h | 60 +++++++++++++++++++++++++++++++ llvm-types.c | 61 +++++++++++++++++++------------- 3 files changed, 161 insertions(+), 55 deletions(-) Index: llvm-gcc/gcc/llvm-expand.c diff -u llvm-gcc/gcc/llvm-expand.c:1.109 llvm-gcc/gcc/llvm-expand.c:1.110 --- llvm-gcc/gcc/llvm-expand.c:1.109 Tue Jul 26 19:24:41 2005 +++ llvm-gcc/gcc/llvm-expand.c Thu Jul 28 13:50:28 2005 @@ -159,7 +159,7 @@ static inline llvm_value * cast_if_type_not_equal(llvm_function *Fn, - llvm_value *V, const llvm_type *Ty) { + llvm_value *V, llvm_type *Ty) { llvm_instruction *Cast; if (V->Ty == Ty) return V; /* No cast required? */ @@ -3023,24 +3023,38 @@ static unsigned PassStructureByValue(llvm_function *Fn, llvm_value *ArgAddr, llvm_instruction *Call, llvm_type *CalledFuncType, - unsigned ArgOffset, unsigned NumArgs) { + unsigned ArgOffset, unsigned NumArgs, + LLVM_TARGET_ARG_ACCUM_TYPE *ArgAccum) { llvm_type *ValTy = GET_POINTER_TYPE_ELEMENT(ArgAddr->Ty); + if (!llvm_type_is_composite(ValTy)) { /* Finally got down to a simple scalar value. Load it out. */ - llvm_value *Val = append_inst(Fn, create_load_inst("tmp", ArgAddr, 0)); + llvm_value *Val; + + LLVM_TARGET_ARG_MODIFY_ARG_TYPE_IF_NEEDED(*ArgAccum, ValTy); + + if (ValTy != GET_POINTER_TYPE_ELEMENT(ArgAddr->Ty)) + ArgAddr = cast_if_type_not_equal(Fn, ArgAddr, + llvm_type_get_pointer(ValTy)); + + Val = append_inst(Fn, create_load_inst("tmp", ArgAddr, 0)); Call->Operands[NumArgs+ArgOffset] = Val; CalledFuncType->Elements[1+NumArgs] = Val->Ty; return NumArgs+1; } else { unsigned i, e; + LLVM_TARGET_ARG_DEFINE_COMPOSITE_ACCUM(COMPACCUM); + LLVM_TARGET_ARG_ENTER_COMPOSITE(*ArgAccum, COMPACCUM, ValTy); + for (i = 0, e = llvm_type_get_composite_num_elements(ValTy); i != e; ++i) { llvm_value *Element = llvm_constant_new_integral(ValTy->ID == StructTyID ? UIntTy : IntPtrTy, i); llvm_value *Addr = append_inst(Fn, create_gep3(ArgAddr, llvm_constant_intptr_0, Element)); NumArgs = PassStructureByValue(Fn, Addr, Call, CalledFuncType, - ArgOffset, NumArgs); + ArgOffset, NumArgs, ArgAccum); } + LLVM_TARGET_ARG_EXIT_COMPOSITE(*ArgAccum, COMPACCUM, ValTy); return NumArgs; } } @@ -3059,6 +3073,7 @@ unsigned ArgOffset; int FunctionMatches = 1; llvm_type *CalledFuncType; + LLVM_TARGET_ARG_ACCUM_TYPE ArgAccumulator = LLVM_TARGET_ARG_ACCUM_INIT; /* Check to see if this is an intrinsic. If so, do not turn it into an * invoke! @@ -3123,6 +3138,7 @@ ArgTy = GET_FUNCTION_TYPE_ARGUMENT(FnType, 0); else if (!FnType->x.Function.isVarArg) FunctionMatches = 0; + LLVM_TARGET_ARG_MODIFY_ARG_TYPE_IF_NEEDED(ArgAccumulator, ArgTy); DestLoc = cast_if_type_not_equal(Fn, DestLoc, ArgTy); Call->Operands[ArgOffset] = DestLoc; CalledFuncType->Elements[1] = DestLoc->Ty; @@ -3146,7 +3162,8 @@ if (isPassedByInvisibleReference(TREE_TYPE(TREE_VALUE(arg)))) { /* Get the address of the parameters passed in. */ ArgVal = llvm_expand_lvalue_expr(Fn, TREE_VALUE(arg), 0, 0); - if (ArgTy) ArgVal = cast_if_type_not_equal(Fn, ArgVal, ArgTy); + LLVM_TARGET_ARG_MODIFY_ARG_TYPE_IF_NEEDED(ArgAccumulator, ArgTy); + ArgVal = cast_if_type_not_equal(Fn, ArgVal, ArgTy); Call->Operands[NumArgs+ArgOffset] = ArgVal; CalledFuncType->Elements[1+NumArgs] = ArgVal->Ty; ++NumArgs; @@ -3157,11 +3174,11 @@ llvm_value *ArgAddr = llvm_expand_lvalue_expr(Fn, TREE_VALUE(arg), 0, 0); assert(ActualArgTy == GET_POINTER_TYPE_ELEMENT(ArgAddr->Ty)); NumArgs = PassStructureByValue(Fn, ArgAddr, Call, CalledFuncType, - ArgOffset, NumArgs); + ArgOffset, NumArgs, &ArgAccumulator); } else { /* Otherwise it is a simple scalar argument. */ ArgVal = llvm_expand_expr(Fn, TREE_VALUE(arg), 0); - if (ArgTy) - ArgVal = cast_if_type_not_equal(Fn, ArgVal, ArgTy); + LLVM_TARGET_ARG_MODIFY_ARG_TYPE_IF_NEEDED(ArgAccumulator, ArgTy); + ArgVal = cast_if_type_not_equal(Fn, ArgVal, ArgTy); Call->Operands[NumArgs+ArgOffset] = ArgVal; CalledFuncType->Elements[1+NumArgs] = ArgVal->Ty; ++NumArgs; @@ -4468,7 +4485,6 @@ tree fndecl = TREE_OPERAND (TREE_OPERAND (exp, 0), 0); static llvm_function *llvm_va_copy_fn = 0; - llvm_type *VAListType; tree SrcArg; llvm_value *DestAddr; llvm_instruction *I; @@ -4581,7 +4597,7 @@ } static llvm_value * -llvm_expand_builtin_unaryop(llvm_function *Fn, const llvm_type *DestTy, +llvm_expand_builtin_unaryop(llvm_function *Fn, llvm_type *DestTy, tree arglist, const char *FnName) { llvm_value *arg; llvm_instruction *TheCall; @@ -7041,27 +7057,34 @@ * specified memory location. */ static void AddArguments(llvm_function *Fn, llvm_type *Ty, const char *Name, - llvm_value *Address, unsigned *ArgNo) { + llvm_value *Address, unsigned *ArgNo, + LLVM_TARGET_ARG_ACCUM_TYPE *ArgAccumulator) { if (!llvm_type_is_composite(Ty)) { llvm_type *FuncTy = GET_POINTER_TYPE_ELEMENT(G2V(Fn)->Ty); llvm_type *ArgTy = Ty; llvm_argument *Arg; - if (*ArgNo < GET_FUNCTION_TYPE_NUMARGS(FuncTy) && - ArgTy != GET_FUNCTION_TYPE_ARGUMENT(FuncTy, *ArgNo)) { - fprintf(stderr, "WARNING: Function declared to have type '"); - llvm_type_print(GET_FUNCTION_TYPE_ARGUMENT(FuncTy, *ArgNo), stderr); - fprintf(stderr, "' but it actually has type '"); - llvm_type_print(ArgTy, stderr); - ArgTy = GET_FUNCTION_TYPE_ARGUMENT(FuncTy, *ArgNo); - fprintf(stderr, "'!\n"); - } + LLVM_TARGET_ARG_MODIFY_ARG_TYPE_IF_NEEDED(*ArgAccumulator, ArgTy); + assert((*ArgNo >= GET_FUNCTION_TYPE_NUMARGS(FuncTy) || + ArgTy == GET_FUNCTION_TYPE_ARGUMENT(FuncTy, *ArgNo)) && + "ERROR: Function type mismatch!"); + Arg = llvm_argument_new(ArgTy, Name); llvm_ilist_push_back(llvm_argument, Fn->Arguments, Arg); if (Address) { - llvm_value *ArgV = cast_if_type_not_equal(Fn, D2V(Arg), - GET_POINTER_TYPE_ELEMENT(Address->Ty)); + llvm_value *ArgV = D2V(Arg); + + /* If LLVM_TARGET_* modified type type, cast the destination pointer, + * otherwise cast the input value. + */ + if (ArgTy == Ty) { + ArgV = cast_if_type_not_equal(Fn, ArgV, + GET_POINTER_TYPE_ELEMENT(Address->Ty)); + } else { + Address = cast_if_type_not_equal(Fn, Address, + llvm_type_get_pointer(ArgTy)); + } append_inst(Fn, create_store_inst(ArgV, Address, 0)); } ++*ArgNo; @@ -7072,6 +7095,9 @@ unsigned i, NameLen = strlen(Name); char *SubName = (char*)xmalloc(NameLen+6); /* Should use alloca, oh well */ llvm_type *ElIdxTy = Ty->ID == StructTyID ? UIntTy : IntPtrTy; + LLVM_TARGET_ARG_DEFINE_COMPOSITE_ACCUM(COMPACCUM); + + LLVM_TARGET_ARG_ENTER_COMPOSITE(*ArgAccumulator, COMPACCUM, Ty); strcpy(SubName, Name); for (i = 0; i != llvm_type_get_composite_num_elements(Ty); ++i) { llvm_type *ElTy = llvm_type_get_composite_element(Ty, i); @@ -7086,9 +7112,10 @@ llvm_constant_new(ElIdxTy, SubName+NameLen+1)); Offset = append_inst(Fn, GEP); /* Add the inst to the stream */ } - AddArguments(Fn, ElTy, SubName, Offset, ArgNo); + AddArguments(Fn, ElTy, SubName, Offset, ArgNo, ArgAccumulator); } free(SubName); + LLVM_TARGET_ARG_EXIT_COMPOSITE(*ArgAccumulator, COMPACCUM, Ty); } } @@ -7108,6 +7135,7 @@ int isExternal = !DECL_SAVED_TREE(fd); /* no body? */ tree Args; unsigned NumArgs = 0; + LLVM_TARGET_ARG_ACCUM_TYPE ArgAccumulator = LLVM_TARGET_ARG_ACCUM_INIT; assert(TREE_CODE(fd) == FUNCTION_DECL); if (isExternal) return BaseType; /* Still external, used declared type. */ @@ -7135,13 +7163,17 @@ if (DECL_RESULT(fd)) { RetType = llvm_type_get_from_tree(TREE_TYPE(DECL_RESULT(fd))); - if (llvm_type_is_composite(RetType)) - BaseType->Elements[NumArgs++] = llvm_type_get_pointer(RetType); + if (llvm_type_is_composite(RetType)) { + llvm_type *ArgTy = llvm_type_get_pointer(RetType); + LLVM_TARGET_ARG_MODIFY_ARG_TYPE_IF_NEEDED(ArgAccumulator, ArgTy); + BaseType->Elements[NumArgs++] = ArgTy; + } } for (Args = DECL_ARGUMENTS(fd); Args; Args = TREE_CHAIN(Args)) { - llvm_type *Ty = llvm_type_get_from_tree(TREE_TYPE(Args)); - NumArgs += SetFunctionArgs(BaseType, NumArgs, Ty); + NumArgs += SetFunctionArgs(BaseType, NumArgs, + llvm_type_get_from_tree(TREE_TYPE(Args)), + &ArgAccumulator); } return llvm_type_get_cannonical_function(BaseType); @@ -7159,6 +7191,7 @@ int isExternal = !DECL_SAVED_TREE(subr); /* no body, YET */ llvm_type *DeclResultTy; int ReturnsComposite = 0; + LLVM_TARGET_ARG_ACCUM_TYPE ArgAccumulator = LLVM_TARGET_ARG_ACCUM_INIT; if (!isExternal && FnTy->x.Function.isVarArg && Args == 0) { /* Check to see if this is a false varargs function. In C, declaring a @@ -7268,8 +7301,10 @@ if (DECL_RESULT(subr)) { DeclResultTy = llvm_type_get_from_tree(TREE_TYPE(DECL_RESULT(subr))); if (llvm_type_is_composite(DeclResultTy)) { - llvm_argument *Arg =llvm_argument_new(llvm_type_get_pointer(DeclResultTy), - "agg.result"); + llvm_type *ArgTy = llvm_type_get_pointer(DeclResultTy); + llvm_argument *Arg; + LLVM_TARGET_ARG_MODIFY_ARG_TYPE_IF_NEEDED(ArgAccumulator, ArgTy); + Arg = llvm_argument_new(ArgTy, "agg.result"); llvm_ilist_push_back(llvm_argument, Fn->Arguments, Arg); SET_DECL_LLVM(DECL_RESULT(subr), D2V(Arg)); ReturnsComposite = 1; @@ -7319,7 +7354,7 @@ * this could cause multiple LLVM arguments to be added for this one C * argument. */ - AddArguments(Fn, Ty, Name, D2V(A), &ArgNo); + AddArguments(Fn, Ty, Name, D2V(A), &ArgNo, &ArgAccumulator); /* If the value is passed by "invisible reference", the l-value for the * argument IS the argument itself. Index: llvm-gcc/gcc/llvm-representation.h diff -u llvm-gcc/gcc/llvm-representation.h:1.18 llvm-gcc/gcc/llvm-representation.h:1.19 --- llvm-gcc/gcc/llvm-representation.h:1.18 Fri Jul 22 13:53:38 2005 +++ llvm-gcc/gcc/llvm-representation.h Thu Jul 28 13:50:28 2005 @@ -506,7 +506,65 @@ void llvm_type_print_all_named(FILE *F); -unsigned SetFunctionArgs(llvm_type *FuncTy, unsigned ArgNo, llvm_type *ArgTy); +/*===---------------------------------------------------------------------=== + * Argument passing ABI hooks. + * + * These hooks are used by targets that do not pass arguments in the standard + * way or need to change specific portions of the calling convention for + * certain arguments. + * + * If the target doesn't define these, we provide defaults below. We also + * describe what these are supposed to do below. + */ + +/* LLVM_TARGET_ARG_ACCUM_TYPE - This is the name of a C type that is used to + * implement the state machine for the target. + */ +#ifndef LLVM_TARGET_ARG_ACCUM_TYPE +#define LLVM_TARGET_ARG_ACCUM_TYPE int +#endif + +/* LLVM_TARGET_ARG_ACCUM_INIT - This is the value to initialize the state + * machine with. + */ +#ifndef LLVM_TARGET_ARG_ACCUM_INIT +#define LLVM_TARGET_ARG_ACCUM_INIT 0 +#endif + +/* LLVM_TARGET_ARG_DEFINE_COMPOSITE_ACCUM - This is the type of a value used + * when recursing into a composite type like a structure or array. + */ +#ifndef LLVM_TARGET_ARG_DEFINE_COMPOSITE_ACCUM +#define LLVM_TARGET_ARG_DEFINE_COMPOSITE_ACCUM(NAME) +#endif + +/* LLVM_TARGET_ARG_ENTER_COMPOSITE - This is invoked when entering a composite + * type. The first argument is the ARG_ACCUM for the entire call, the second + * argument is the composite accumulator for the composite type we are entering, + * and the third is the composite llvm_type itself. + */ +#ifndef LLVM_TARGET_ARG_ENTER_COMPOSITE +#define LLVM_TARGET_ARG_ENTER_COMPOSITE(ACCUM, COMPACCUM, TY) +#endif + +/* LLVM_TARGET_ARG_EXIT_COMPOSITE - When recursing out of a composite type + * this callback is invoked with the same arguments as .._ENTER_COMPOSITE. + */ +#ifndef LLVM_TARGET_ARG_EXIT_COMPOSITE +#define LLVM_TARGET_ARG_EXIT_COMPOSITE(ACCUM, COMPACCUM, TY) +#endif + +/* LLVM_TARGET_ARG_MODIFY_ARG_TYPE_IF_NEEDED - This is the callback that is + * actually used to modify types passed to functions. Given the specified + * accumulator, this may modify TY, an lvalue for the current scalar llvm_type + * which is trying to be passed to a function. + */ +#ifndef LLVM_TARGET_ARG_MODIFY_ARG_TYPE_IF_NEEDED +#define LLVM_TARGET_ARG_MODIFY_ARG_TYPE_IF_NEEDED(ACCUM, TY) +#endif + +unsigned SetFunctionArgs(llvm_type *FuncTy, unsigned ArgNo, llvm_type *ArgTy, + LLVM_TARGET_ARG_ACCUM_TYPE *ACCUM); /*===---------------------------------------------------------------------===*/ Index: llvm-gcc/gcc/llvm-types.c diff -u llvm-gcc/gcc/llvm-types.c:1.25 llvm-gcc/gcc/llvm-types.c:1.26 --- llvm-gcc/gcc/llvm-types.c:1.25 Mon Jul 25 20:17:22 2005 +++ llvm-gcc/gcc/llvm-types.c Thu Jul 28 13:50:28 2005 @@ -607,27 +607,6 @@ return 1; } -/* SetFunctionArgs - Add ArgTy to the list of arguments in MethTy. This could - * be a composite type, expanding into many actual LLVM arguments. Insert them - * into the method type at location ArgNo, and return the actual number of - * arguments inserted. - */ -unsigned SetFunctionArgs(llvm_type *FuncTy, unsigned ArgNo, llvm_type *ArgTy) { - if (llvm_type_is_composite(ArgTy)) { - unsigned NumInserted = 0, i; - for (i = 0; i < llvm_type_get_composite_num_elements(ArgTy); ++i) { - unsigned NI = SetFunctionArgs(FuncTy, ArgNo, - llvm_type_get_composite_element(ArgTy, i)); - ArgNo += NI; - NumInserted += NI; - } - return NumInserted; - } else { - FuncTy->Elements[ArgNo] = ArgTy; - return 1; - } -} - llvm_type *llvm_type_get_integer(unsigned NumBits, int isUnsigned) { switch (NumBits*2+!isUnsigned) { case 8*2+0 : return UByteTy; @@ -1033,6 +1012,33 @@ return memcpy(Buffer, Prefix, strlen(Prefix)); } +/* SetFunctionArgs - Add ArgTy to the list of arguments in FuncTy. This could +* be a composite type, expanding into many actual LLVM arguments. Insert them +* into the function type at location ArgNo, and return the actual number of +* arguments inserted. +*/ +unsigned SetFunctionArgs(llvm_type *FuncTy, unsigned ArgNo, llvm_type *ArgTy, + LLVM_TARGET_ARG_ACCUM_TYPE *ACCUM) { + if (llvm_type_is_composite(ArgTy)) { + unsigned NumInserted = 0, i; + LLVM_TARGET_ARG_DEFINE_COMPOSITE_ACCUM(COMACCUM); + LLVM_TARGET_ARG_ENTER_COMPOSITE(*ACCUM, COMACCUM, ArgTy); + for (i = 0; i < llvm_type_get_composite_num_elements(ArgTy); ++i) { + unsigned NI = SetFunctionArgs(FuncTy, ArgNo, + llvm_type_get_composite_element(ArgTy, i), + ACCUM); + ArgNo += NI; + NumInserted += NI; + } + LLVM_TARGET_ARG_EXIT_COMPOSITE(*ACCUM, COMACCUM, ArgTy); + return NumInserted; + } else { + LLVM_TARGET_ARG_MODIFY_ARG_TYPE_IF_NEEDED(*ACCUM, ArgTy); + FuncTy->Elements[ArgNo] = ArgTy; + return 1; + } +} + /* isPassedByInvisibleReference - Return true if an argument of the specified * type should be passed in by invisible reference. */ @@ -1066,6 +1072,7 @@ return 0; } + /* llvm_type_get_tree_type - Return the LLVM type that corresponds to the * specified tree type. If this is the first time we have seen a structure * type, we assign indexes to all of the FIELD_DECLs in it. @@ -1086,7 +1093,9 @@ llvm_type *RetType = llvm_type_get_from_tree(TREE_TYPE(type)); llvm_type *FirstArgTy = 0; /* Non-null if returning a struct */ unsigned NumArgs = 0, i; - + + LLVM_TARGET_ARG_ACCUM_TYPE ArgAccumulator = LLVM_TARGET_ARG_ACCUM_INIT; + /* Loop over all of the args, counting how many there are */ tree Args = TYPE_ARG_TYPES(type); for (; Args && TREE_VALUE(Args) != void_type_node; Args = TREE_CHAIN(Args)){ @@ -1118,7 +1127,11 @@ Result = llvm_type_create_function(NumArgs, RetType); if (!Args) Result->x.Function.isVarArg = 1; - if (FirstArgTy) Result->Elements[1] = FirstArgTy; + + if (FirstArgTy) { + LLVM_TARGET_ARG_MODIFY_ARG_TYPE_IF_NEEDED(ArgAccumulator, FirstArgTy); + Result->Elements[1] = FirstArgTy; + } Args = TYPE_ARG_TYPES(type); for (i = (FirstArgTy != 0)+1; i < NumArgs+1; Args = TREE_CHAIN(Args)) { @@ -1128,7 +1141,7 @@ if (isPassedByInvisibleReference(TREE_VALUE(Args))) Ty = llvm_type_get_pointer(Ty); - i += SetFunctionArgs(Result, i, Ty); + i += SetFunctionArgs(Result, i, Ty, &ArgAccumulator); } return llvm_type_get_cannonical_function(Result); } From lattner at cs.uiuc.edu Thu Jul 28 13:52:18 2005 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Thu, 28 Jul 2005 13:52:18 -0500 Subject: [llvm-commits] CVS: llvm-gcc/gcc/config/rs6000/darwin.h Message-ID: <200507281852.NAA26084@zion.cs.uiuc.edu> Changes in directory llvm-gcc/gcc/config/rs6000: darwin.h updated: 1.5 -> 1.6 --- Log message: Fix PR609: http://llvm.cs.uiuc.edu/PR609 , by adding a description of the darwin calling conventions. Darwin wants to pass FP values in integer registers in some cases. This fixes 252.eon, 168.wupwise, 178.galgel, and 301.apsi on darwin. --- Diffs of the changes: (+49 -6) darwin.h | 55 +++++++++++++++++++++++++++++++++++++++++++++++++------ 1 files changed, 49 insertions(+), 6 deletions(-) Index: llvm-gcc/gcc/config/rs6000/darwin.h diff -u llvm-gcc/gcc/config/rs6000/darwin.h:1.5 llvm-gcc/gcc/config/rs6000/darwin.h:1.6 --- llvm-gcc/gcc/config/rs6000/darwin.h:1.5 Tue Jul 26 13:02:42 2005 +++ llvm-gcc/gcc/config/rs6000/darwin.h Thu Jul 28 13:52:07 2005 @@ -22,6 +22,55 @@ #undef TARGET_VERSION #define TARGET_VERSION fprintf (stderr, " (Darwin/PowerPC)"); + +/* The maximum alignment for this target (according to LLVM) is 4 bytes, +* this prevents the type layout machinery from thinking darwin's doubles +* and 'long long's are 64-bit aligned. +*/ +#define LLVM_TARGET_MAX_ALIGN_IS_POINTER_SIZE 1 + +/*===---------------------------------------------------------------------=== +* LLVM Argument passing ABI hooks. +* +* The darwin ABI specifies that structure elements passed through the first +* 8 words of memory should be passed in the GPRs, even if the element is a +* floating point value. The exception to this is single-element structures +* and arrays, which are passed in either the FP or integer regs depending on +* their type. +* +* To implement this, we just have a little state machine in an integer. The +* low bit is a 'transform next element' flag. The upper bits are a count of +* the number of integer registers have been used. +*/ +#define LLVM_TARGET_ARG_ACCUM_TYPE unsigned +#define LLVM_TARGET_ARG_ACCUM_INIT 0 +#define LLVM_TARGET_ARG_DEFINE_COMPOSITE_ACCUM(NAME) unsigned NAME = 0 +#define LLVM_TARGET_ARG_ENTER_COMPOSITE(ACCUM, COMPACCUM, TY) \ +do { \ + COMPACCUM = ACCUM & 1; /* Save old flag */ \ + if (COMPACCUM == 0) \ + if ((TY->ID == StructTyID && TY->NumElements != 1) || \ + (TY->ID == ArrayTyID && TY->x.Array.Size != 1)) \ + ACCUM |= 1; /* Start transforming elements. */ \ +} while (0) + +#define LLVM_TARGET_ARG_EXIT_COMPOSITE(ACCUM, COMPACCUM, TY) \ +do { \ + ACCUM = (ACCUM & ~1) | COMPACCUM; /* restore flag */ \ +} while (0) + +#define LLVM_TARGET_ARG_MODIFY_ARG_TYPE_IF_NEEDED(ACCUM, TY) \ +do { \ + if ((ACCUM >> 1) < 8) { /* Not already on the stack? */ \ + if (ACCUM & 1) { /* If we are converting this, do so. */ \ + if (llvm_type_is_fp(TY)) \ + TY = TY->ID == FloatTyID ? IntTy : LongTy; \ + } \ + ACCUM += (TY->ID == DoubleTyID || TY->ID == LongTyID) ? 4 : 2; \ + } \ +} while (0) + + /* The "Darwin ABI" is mostly like AIX, but with some key differences. */ #define DEFAULT_ABI ABI_DARWIN @@ -270,12 +319,6 @@ : TREE_TYPE (FIELD))) & ((1 << DFmode)|(1 << DImode))) \ ? MIN ((COMPUTED), 32) : (COMPUTED))) -/* The maximum alignment for this target (according to LLVM) is 4 bytes, - * this prevents the type layout machinery from thinking darwin's doubles - * and 'long long's are 64-bit aligned. - */ -#define LLVM_TARGET_MAX_ALIGN_IS_POINTER_SIZE 1 - /* Darwin increases natural record alignment to doubleword if the first field is an FP double while the FP fields remain word aligned. */ #define ROUND_TYPE_ALIGN(STRUCT, COMPUTED, SPECIFIED) \ From lattner at cs.uiuc.edu Thu Jul 28 14:25:34 2005 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Thu, 28 Jul 2005 14:25:34 -0500 Subject: [llvm-commits] CVS: llvm-test/SingleSource/Regression/C++/BuiltinTypeInfo.cpp Message-ID: <200507281925.OAA26319@zion.cs.uiuc.edu> Changes in directory llvm-test/SingleSource/Regression/C++: BuiltinTypeInfo.cpp added (r1.1) --- Log message: Ensure that a corner case in the CFE never gets broken --- Diffs of the changes: (+6 -0) BuiltinTypeInfo.cpp | 6 ++++++ 1 files changed, 6 insertions(+) Index: llvm-test/SingleSource/Regression/C++/BuiltinTypeInfo.cpp diff -c /dev/null llvm-test/SingleSource/Regression/C++/BuiltinTypeInfo.cpp:1.1 *** /dev/null Thu Jul 28 14:25:33 2005 --- llvm-test/SingleSource/Regression/C++/BuiltinTypeInfo.cpp Thu Jul 28 14:25:23 2005 *************** *** 0 **** --- 1,6 ---- + #include + #include + + int main() { + printf("%d", typeid(int) == typeid(float)); + } From lattner at cs.uiuc.edu Thu Jul 28 15:18:44 2005 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Thu, 28 Jul 2005 15:18:44 -0500 Subject: [llvm-commits] CVS: llvm/test/Regression/CFrontend/2005-07-28-IncorrectWeakGlobal.c Message-ID: <200507282018.PAA26904@zion.cs.uiuc.edu> Changes in directory llvm/test/Regression/CFrontend: 2005-07-28-IncorrectWeakGlobal.c added (r1.1) --- Log message: New testcase for PR610: http://llvm.cs.uiuc.edu/PR610 --- Diffs of the changes: (+5 -0) 2005-07-28-IncorrectWeakGlobal.c | 5 +++++ 1 files changed, 5 insertions(+) Index: llvm/test/Regression/CFrontend/2005-07-28-IncorrectWeakGlobal.c diff -c /dev/null llvm/test/Regression/CFrontend/2005-07-28-IncorrectWeakGlobal.c:1.1 *** /dev/null Thu Jul 28 15:18:43 2005 --- llvm/test/Regression/CFrontend/2005-07-28-IncorrectWeakGlobal.c Thu Jul 28 15:18:33 2005 *************** *** 0 **** --- 1,5 ---- + // RUN: %llvmgcc %s -S -o - | grep TheGlobal | not grep weak + + extern int TheGlobal; + int foo() { return TheGlobal; } + int TheGlobal = 1; From lattner at cs.uiuc.edu Thu Jul 28 15:19:04 2005 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Thu, 28 Jul 2005 15:19:04 -0500 Subject: [llvm-commits] CVS: llvm-gcc/gcc/llvm-expand.c Message-ID: <200507282019.PAA27074@zion.cs.uiuc.edu> Changes in directory llvm-gcc/gcc: llvm-expand.c updated: 1.110 -> 1.111 --- Log message: Fix PR610: http://llvm.cs.uiuc.edu/PR610 and Regression/CFrontend/2005-07-28-IncorrectWeakGlobal.c --- Diffs of the changes: (+15 -13) llvm-expand.c | 28 +++++++++++++++------------- 1 files changed, 15 insertions(+), 13 deletions(-) Index: llvm-gcc/gcc/llvm-expand.c diff -u llvm-gcc/gcc/llvm-expand.c:1.110 llvm-gcc/gcc/llvm-expand.c:1.111 --- llvm-gcc/gcc/llvm-expand.c:1.110 Thu Jul 28 13:50:28 2005 +++ llvm-gcc/gcc/llvm-expand.c Thu Jul 28 15:18:53 2005 @@ -7653,19 +7653,6 @@ if (PName && strcmp(PName, G2V(G)->Name)) G->PrettyGlobalName = xstrdup(PName); - if (!TREE_PUBLIC(decl) || lang_hooks.llvm_is_in_anon(decl)) { - G->Linkage = L_Internal; - } else if (DECL_COMDAT(decl) || /*) { - - FIXME: This is disabled, because with it we lose the definitions of _ZTIi - and friends (typeinfo for builtin types). It looks like these are being - incorrectly marked as COMDAT even while compiling tinfo2.cc, where they - should be emitted as strong symbols. - - G->Linkage = L_LinkOnce; - } else if (*/DECL_WEAK(decl) || DECL_COMMON(decl) || DECL_VIRTUAL_P(decl)) - G->Linkage = L_Weak; - if (TREE_READONLY(decl) && !TREE_SIDE_EFFECTS(decl)) { if (DECL_EXTERNAL(decl)) { /* Mark external globals constant even though they could be marked @@ -7717,6 +7704,21 @@ OldGlobal->ForwardedGlobal = G; assert(G2V(G)->Ty == Ty && "LLVM type not correctly set??"); } + + if (!TREE_PUBLIC(decl) || lang_hooks.llvm_is_in_anon(decl)) { + G->Linkage = L_Internal; + } else if (DECL_COMDAT(decl) || /*) { + + FIXME: This is disabled, because with it we lose the definitions of _ZTIi + and friends (typeinfo for builtin types). It looks like these are being + incorrectly marked as COMDAT even while compiling tinfo2.cc, where they + should be emitted as strong symbols. This is tested by + SingleSource/Regression/C++/BuiltinTypeInfo.cpp + + G->Linkage = L_LinkOnce; + } else if (*/DECL_WEAK(decl) || DECL_COMMON(decl) || DECL_VIRTUAL_P(decl)) { + G->Linkage = L_Weak; + } if (DECL_INITIAL(decl) && DECL_INITIAL(decl) != error_mark_node) { /* An initializer was specified for the global */ From lattner at cs.uiuc.edu Thu Jul 28 17:03:04 2005 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Thu, 28 Jul 2005 17:03:04 -0500 Subject: [llvm-commits] CVS: llvm-gcc/gcc/llvm-types.c Message-ID: <200507282203.RAA27709@zion.cs.uiuc.edu> Changes in directory llvm-gcc/gcc: llvm-types.c updated: 1.26 -> 1.27 --- Log message: Do not crash on variable sized structures. This fixes CFrontend/2004-11-27-VariableSizeInStructure.c which Reid noticed was failing --- Diffs of the changes: (+1 -1) llvm-types.c | 2 +- 1 files changed, 1 insertion(+), 1 deletion(-) Index: llvm-gcc/gcc/llvm-types.c diff -u llvm-gcc/gcc/llvm-types.c:1.26 llvm-gcc/gcc/llvm-types.c:1.27 --- llvm-gcc/gcc/llvm-types.c:1.26 Thu Jul 28 13:50:28 2005 +++ llvm-gcc/gcc/llvm-types.c Thu Jul 28 17:02:53 2005 @@ -1467,7 +1467,7 @@ * elements so that the LLVM code will have the right size for the * structure. */ - { + if (TYPE_SIZE(type) && TREE_CODE(TYPE_SIZE(type)) == INTEGER_CST) { unsigned GCCTypeSize = ((unsigned)TREE_INT_CST_LOW(TYPE_SIZE(type))+7)/8; unsigned LLVMTypeSize, LLVMStructAlign = 1, i; From lattner at cs.uiuc.edu Thu Jul 28 17:37:32 2005 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Thu, 28 Jul 2005 17:37:32 -0500 Subject: [llvm-commits] CVS: llvm-gcc/gcc/llvm-expand.c Message-ID: <200507282237.RAA11293@zion.cs.uiuc.edu> Changes in directory llvm-gcc/gcc: llvm-expand.c updated: 1.111 -> 1.112 --- Log message: Add a workaround for a "GCC's trees are not type consistent" problem. --- Diffs of the changes: (+8 -4) llvm-expand.c | 12 ++++++++---- 1 files changed, 8 insertions(+), 4 deletions(-) Index: llvm-gcc/gcc/llvm-expand.c diff -u llvm-gcc/gcc/llvm-expand.c:1.111 llvm-gcc/gcc/llvm-expand.c:1.112 --- llvm-gcc/gcc/llvm-expand.c:1.111 Thu Jul 28 15:18:53 2005 +++ llvm-gcc/gcc/llvm-expand.c Thu Jul 28 17:37:20 2005 @@ -7066,10 +7066,14 @@ LLVM_TARGET_ARG_MODIFY_ARG_TYPE_IF_NEEDED(*ArgAccumulator, ArgTy); - assert((*ArgNo >= GET_FUNCTION_TYPE_NUMARGS(FuncTy) || - ArgTy == GET_FUNCTION_TYPE_ARGUMENT(FuncTy, *ArgNo)) && - "ERROR: Function type mismatch!"); - + /* GCC is extremely lax about types being equal. If the types are slightly + * different, convert to the one that LLVM expects from the function + * prototype. + */ + if (*ArgNo < GET_FUNCTION_TYPE_NUMARGS(FuncTy) && + ArgTy != GET_FUNCTION_TYPE_ARGUMENT(FuncTy, *ArgNo)) + ArgTy = GET_FUNCTION_TYPE_ARGUMENT(FuncTy, *ArgNo); + Arg = llvm_argument_new(ArgTy, Name); llvm_ilist_push_back(llvm_argument, Fn->Arguments, Arg); if (Address) { From lattner at cs.uiuc.edu Thu Jul 28 18:31:24 2005 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Thu, 28 Jul 2005 18:31:24 -0500 Subject: [llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp Message-ID: <200507282331.SAA14834@zion.cs.uiuc.edu> Changes in directory llvm/lib/CodeGen/SelectionDAG: LegalizeDAG.cpp updated: 1.144 -> 1.145 --- Log message: instead of having all conversions be handled by one case value, and then have subcases inside, break things out earlier. --- Diffs of the changes: (+86 -64) LegalizeDAG.cpp | 150 ++++++++++++++++++++++++++++++++------------------------ 1 files changed, 86 insertions(+), 64 deletions(-) Index: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp diff -u llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.144 llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.145 --- llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.144 Wed Jul 27 01:12:33 2005 +++ llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp Thu Jul 28 18:31:12 2005 @@ -1438,62 +1438,103 @@ break; // Conversion operators. The source and destination have different types. + case ISD::SINT_TO_FP: + case ISD::UINT_TO_FP: { + bool isSigned = Node->getOpcode() == ISD::SINT_TO_FP; + switch (getTypeAction(Node->getOperand(0).getValueType())) { + case Legal: + switch (TLI.getOperationAction(Node->getOpcode(), + Node->getOperand(0).getValueType())) { + default: assert(0 && "Unknown operation action!"); + case TargetLowering::Expand: + assert(!isSigned && "Legalize cannot Expand SINT_TO_FP yet"); + Result = ExpandLegalUINT_TO_FP(LegalizeOp(Node->getOperand(0)), + Node->getValueType(0)); + AddLegalizedOperand(Op, Result); + return Result; + case TargetLowering::Promote: + Result = PromoteLegalINT_TO_FP(LegalizeOp(Node->getOperand(0)), + Node->getValueType(0), + isSigned); + AddLegalizedOperand(Op, Result); + return Result; + case TargetLowering::Legal: + break; + } + + Tmp1 = LegalizeOp(Node->getOperand(0)); + if (Tmp1 != Node->getOperand(0)) + Result = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1); + break; + case Expand: + Result = ExpandIntToFP(Node->getOpcode() == ISD::SINT_TO_FP, + Node->getValueType(0), Node->getOperand(0)); + break; + case Promote: + if (isSigned) { + Result = PromoteOp(Node->getOperand(0)); + Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(), + Result, DAG.getValueType(Node->getOperand(0).getValueType())); + Result = DAG.getNode(ISD::SINT_TO_FP, Op.getValueType(), Result); + } else { + Result = PromoteOp(Node->getOperand(0)); + Result = DAG.getZeroExtendInReg(Result, + Node->getOperand(0).getValueType()); + Result = DAG.getNode(ISD::UINT_TO_FP, Op.getValueType(), Result); + } + break; + } + break; + } + case ISD::TRUNCATE: + switch (getTypeAction(Node->getOperand(0).getValueType())) { + case Legal: + Tmp1 = LegalizeOp(Node->getOperand(0)); + if (Tmp1 != Node->getOperand(0)) + Result = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1); + break; + case Expand: + ExpandOp(Node->getOperand(0), Tmp1, Tmp2); + + // Since the result is legal, we should just be able to truncate the low + // part of the source. + Result = DAG.getNode(ISD::TRUNCATE, Node->getValueType(0), Tmp1); + break; + case Promote: + Result = PromoteOp(Node->getOperand(0)); + Result = DAG.getNode(ISD::TRUNCATE, Op.getValueType(), Result); + break; + } + break; + + case ISD::FP_TO_SINT: + case ISD::FP_TO_UINT: + switch (getTypeAction(Node->getOperand(0).getValueType())) { + case Legal: + Tmp1 = LegalizeOp(Node->getOperand(0)); + if (Tmp1 != Node->getOperand(0)) + Result = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1); + break; + case Expand: + assert(0 && "Shouldn't need to expand other operators here!"); + case Promote: + Result = PromoteOp(Node->getOperand(0)); + Result = DAG.getNode(Node->getOpcode(), Op.getValueType(), Result); + break; + } + break; + case ISD::ZERO_EXTEND: case ISD::SIGN_EXTEND: - case ISD::TRUNCATE: case ISD::FP_EXTEND: case ISD::FP_ROUND: - case ISD::FP_TO_SINT: - case ISD::FP_TO_UINT: - case ISD::SINT_TO_FP: - case ISD::UINT_TO_FP: switch (getTypeAction(Node->getOperand(0).getValueType())) { case Legal: - //still made need to expand if the op is illegal, but the types are legal - if (Node->getOpcode() == ISD::UINT_TO_FP || - Node->getOpcode() == ISD::SINT_TO_FP) { - bool isSigned = Node->getOpcode() == ISD::SINT_TO_FP; - switch (TLI.getOperationAction(Node->getOpcode(), - Node->getOperand(0).getValueType())) { - default: assert(0 && "Unknown operation action!"); - case TargetLowering::Expand: - if (!isSigned) - Result = ExpandLegalUINT_TO_FP(LegalizeOp(Node->getOperand(0)), - Node->getValueType(0)); - else - assert(0 && "Legalize cannot Expand SINT_TO_FP yet"); - AddLegalizedOperand(Op, Result); - return Result; - case TargetLowering::Promote: - Result = PromoteLegalINT_TO_FP(LegalizeOp(Node->getOperand(0)), - Node->getValueType(0), - isSigned); - AddLegalizedOperand(Op, Result); - return Result; - case TargetLowering::Legal: - break; - } - } Tmp1 = LegalizeOp(Node->getOperand(0)); if (Tmp1 != Node->getOperand(0)) Result = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1); break; case Expand: - if (Node->getOpcode() == ISD::SINT_TO_FP || - Node->getOpcode() == ISD::UINT_TO_FP) { - Result = ExpandIntToFP(Node->getOpcode() == ISD::SINT_TO_FP, - Node->getValueType(0), Node->getOperand(0)); - break; - } else if (Node->getOpcode() == ISD::TRUNCATE) { - // In the expand case, we must be dealing with a truncate, because - // otherwise the result would be larger than the source. - ExpandOp(Node->getOperand(0), Tmp1, Tmp2); - - // Since the result is legal, we should just be able to truncate the low - // part of the source. - Result = DAG.getNode(ISD::TRUNCATE, Node->getValueType(0), Tmp1); - break; - } assert(0 && "Shouldn't need to expand other operators here!"); case Promote: @@ -1513,10 +1554,6 @@ Result, DAG.getValueType(Node->getOperand(0).getValueType())); break; - case ISD::TRUNCATE: - Result = PromoteOp(Node->getOperand(0)); - Result = DAG.getNode(ISD::TRUNCATE, Op.getValueType(), Result); - break; case ISD::FP_EXTEND: Result = PromoteOp(Node->getOperand(0)); if (Result.getValueType() != Op.getValueType()) @@ -1524,24 +1561,9 @@ Result = DAG.getNode(ISD::FP_EXTEND, Op.getValueType(), Result); break; case ISD::FP_ROUND: - case ISD::FP_TO_SINT: - case ISD::FP_TO_UINT: Result = PromoteOp(Node->getOperand(0)); Result = DAG.getNode(Node->getOpcode(), Op.getValueType(), Result); break; - case ISD::SINT_TO_FP: - Result = PromoteOp(Node->getOperand(0)); - Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(), - Result, - DAG.getValueType(Node->getOperand(0).getValueType())); - Result = DAG.getNode(ISD::SINT_TO_FP, Op.getValueType(), Result); - break; - case ISD::UINT_TO_FP: - Result = PromoteOp(Node->getOperand(0)); - Result = DAG.getZeroExtendInReg(Result, - Node->getOperand(0).getValueType()); - Result = DAG.getNode(ISD::UINT_TO_FP, Op.getValueType(), Result); - break; } } break; From lattner at cs.uiuc.edu Thu Jul 28 19:12:07 2005 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Thu, 28 Jul 2005 19:12:07 -0500 Subject: [llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp Message-ID: <200507290012.TAA15052@zion.cs.uiuc.edu> Changes in directory llvm/lib/CodeGen/SelectionDAG: LegalizeDAG.cpp updated: 1.145 -> 1.146 --- Log message: allow a target to request that unknown FP_TO_*INT conversion be promoted to a larger integer destination. --- Diffs of the changes: (+74 -1) LegalizeDAG.cpp | 75 +++++++++++++++++++++++++++++++++++++++++++++++++++++++- 1 files changed, 74 insertions(+), 1 deletion(-) Index: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp diff -u llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.145 llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.146 --- llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.145 Thu Jul 28 18:31:12 2005 +++ llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp Thu Jul 28 19:11:56 2005 @@ -128,6 +128,8 @@ SDOperand ExpandLegalUINT_TO_FP(SDOperand LegalOp, MVT::ValueType DestVT); SDOperand PromoteLegalINT_TO_FP(SDOperand LegalOp, MVT::ValueType DestVT, bool isSigned); + SDOperand PromoteLegalFP_TO_INT(SDOperand LegalOp, MVT::ValueType DestVT, + bool isSigned); bool ExpandShift(unsigned Opc, SDOperand Op, SDOperand Amt, SDOperand &Lo, SDOperand &Hi); @@ -202,7 +204,7 @@ } /// PromoteLegalUINT_TO_FP - This function is responsible for legalizing a -/// UINT_TO_FP operation of the specified operand when the target requests that +/// *INT_TO_FP operation of the specified operand when the target requests that /// we promote it. At this point, we know that the result and operand types are /// legal for the target, and that there is a legal UINT_TO_FP or SINT_TO_FP /// operation that takes a larger input. @@ -259,6 +261,63 @@ NewInTy, LegalOp)); } +/// PromoteLegalFP_TO_INT - This function is responsible for legalizing a +/// FP_TO_*INT operation of the specified operand when the target requests that +/// we promote it. At this point, we know that the result and operand types are +/// legal for the target, and that there is a legal FP_TO_UINT or FP_TO_SINT +/// operation that returns a larger result. +SDOperand SelectionDAGLegalize::PromoteLegalFP_TO_INT(SDOperand LegalOp, + MVT::ValueType DestVT, + bool isSigned) { + // First step, figure out the appropriate FP_TO*INT operation to use. + MVT::ValueType NewOutTy = DestVT; + + unsigned OpToUse = 0; + + // Scan for the appropriate larger type to use. + while (1) { + NewOutTy = (MVT::ValueType)(NewOutTy+1); + assert(MVT::isInteger(NewOutTy) && "Ran out of possibilities!"); + + // If the target supports FP_TO_SINT returning this type, use it. + switch (TLI.getOperationAction(ISD::FP_TO_SINT, NewOutTy)) { + default: break; + case TargetLowering::Legal: + if (!TLI.hasNativeSupportFor(NewOutTy)) + break; // Can't use this datatype. + // FALL THROUGH. + case TargetLowering::Custom: + OpToUse = ISD::FP_TO_SINT; + break; + } + if (OpToUse) break; + + // If the target supports FP_TO_UINT of this type, use it. + switch (TLI.getOperationAction(ISD::FP_TO_UINT, NewOutTy)) { + default: break; + case TargetLowering::Legal: + if (!TLI.hasNativeSupportFor(NewOutTy)) + break; // Can't use this datatype. + // FALL THROUGH. + case TargetLowering::Custom: + OpToUse = ISD::FP_TO_UINT; + break; + } + if (OpToUse) break; + + // Otherwise, try a larger type. + } + + // Make sure to legalize any nodes we create here in the next pass. + NeedsAnotherIteration = true; + + // Okay, we found the operation and type to use. Truncate the result of the + // extended FP_TO_*INT operation to the desired size. + return DAG.getNode(ISD::TRUNCATE, DestVT, + DAG.getNode(OpToUse, NewOutTy, LegalOp)); +} + + void SelectionDAGLegalize::LegalizeDAG() { SDOperand OldRoot = DAG.getRoot(); SDOperand NewRoot = LegalizeOp(OldRoot); @@ -1511,6 +1570,20 @@ case ISD::FP_TO_UINT: switch (getTypeAction(Node->getOperand(0).getValueType())) { case Legal: + switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))){ + default: assert(0 && "Unknown operation action!"); + case TargetLowering::Expand: + assert(0 && "Cannot expand FP_TO*INT yet"); + case TargetLowering::Promote: + Result = PromoteLegalFP_TO_INT(LegalizeOp(Node->getOperand(0)), + Node->getValueType(0), + Node->getOpcode() == ISD::FP_TO_SINT); + AddLegalizedOperand(Op, Result); + return Result; + case TargetLowering::Legal: + break; + } + Tmp1 = LegalizeOp(Node->getOperand(0)); if (Tmp1 != Node->getOperand(0)) Result = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1); From lattner at cs.uiuc.edu Thu Jul 28 19:33:43 2005 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Thu, 28 Jul 2005 19:33:43 -0500 Subject: [llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp Message-ID: <200507290033.TAA15168@zion.cs.uiuc.edu> Changes in directory llvm/lib/CodeGen/SelectionDAG: LegalizeDAG.cpp updated: 1.146 -> 1.147 --- Log message: Allow targets to define custom expanders for FP_TO_*INT --- Diffs of the changes: (+18 -0) LegalizeDAG.cpp | 18 ++++++++++++++++++ 1 files changed, 18 insertions(+) Index: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp diff -u llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.146 llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.147 --- llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.146 Thu Jul 28 19:11:56 2005 +++ llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp Thu Jul 28 19:33:32 2005 @@ -2772,12 +2772,30 @@ // These operators cannot be expanded directly, emit them as calls to // library functions. case ISD::FP_TO_SINT: + if (TLI.getOperationAction(ISD::FP_TO_SINT, VT) == TargetLowering::Custom) { + SDOperand Op = DAG.getNode(ISD::FP_TO_SINT, VT, + LegalizeOp(Node->getOperand(0))); + // Now that the custom expander is done, expand the result, which is still + // VT. + ExpandOp(TLI.LowerOperation(Op, DAG), Lo, Hi); + break; + } + if (Node->getOperand(0).getValueType() == MVT::f32) Lo = ExpandLibCall("__fixsfdi", Node, Hi); else Lo = ExpandLibCall("__fixdfdi", Node, Hi); break; case ISD::FP_TO_UINT: + if (TLI.getOperationAction(ISD::FP_TO_UINT, VT) == TargetLowering::Custom) { + SDOperand Op = DAG.getNode(ISD::FP_TO_UINT, VT, + LegalizeOp(Node->getOperand(0))); + // Now that the custom expander is done, expand the result, which is still + // VT. + ExpandOp(TLI.LowerOperation(Op, DAG), Lo, Hi); + break; + } + if (Node->getOperand(0).getValueType() == MVT::f32) Lo = ExpandLibCall("__fixunssfdi", Node, Hi); else From lattner at cs.uiuc.edu Thu Jul 28 19:40:14 2005 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Thu, 28 Jul 2005 19:40:14 -0500 Subject: [llvm-commits] CVS: llvm/lib/Target/X86/X86ISelPattern.cpp Message-ID: <200507290040.TAA15306@zion.cs.uiuc.edu> Changes in directory llvm/lib/Target/X86: X86ISelPattern.cpp updated: 1.155 -> 1.156 --- Log message: Use a custom expander to compile this: long %test4(double %X) { %tmp.1 = cast double %X to long ; [#uses=1] ret long %tmp.1 } to this: _test4: sub %ESP, 12 fld QWORD PTR [%ESP + 16] fistp QWORD PTR [%ESP] mov %EDX, DWORD PTR [%ESP + 4] mov %EAX, DWORD PTR [%ESP] add %ESP, 12 ret instead of this: _test4: sub %ESP, 28 fld QWORD PTR [%ESP + 32] fstp QWORD PTR [%ESP] call ___fixdfdi add %ESP, 28 ret --- Diffs of the changes: (+57 -13) X86ISelPattern.cpp | 70 +++++++++++++++++++++++++++++++++++++++++++---------- 1 files changed, 57 insertions(+), 13 deletions(-) Index: llvm/lib/Target/X86/X86ISelPattern.cpp diff -u llvm/lib/Target/X86/X86ISelPattern.cpp:1.155 llvm/lib/Target/X86/X86ISelPattern.cpp:1.156 --- llvm/lib/Target/X86/X86ISelPattern.cpp:1.155 Wed Jul 27 01:12:34 2005 +++ llvm/lib/Target/X86/X86ISelPattern.cpp Thu Jul 28 19:40:01 2005 @@ -54,6 +54,12 @@ /// address) and two outputs (FP value and token chain). FILD64m, + /// FISTP64m - This instruction implements FP_TO_SINT with a + /// 64-bit destination in memory and a FP reg source. This corresponds to + /// the X86::FISTP64m instruction. It has two inputs (token chain and + /// address) and two outputs (FP value and token chain). + FISTP64m, + /// CALL/TAILCALL - These operations represent an abstract X86 call /// instruction, which includes a bunch of information. In particular the /// operands of these node are: @@ -118,9 +124,13 @@ setOperationAction(ISD::SINT_TO_FP , MVT::i1 , Promote); setOperationAction(ISD::SINT_TO_FP , MVT::i8 , Promote); - // We can handle SINT_TO_FP from i64 even though i64 isn't legal. - setOperationAction(ISD::SINT_TO_FP , MVT::i64 , Custom); - + if (!X86ScalarSSE) { + // We can handle SINT_TO_FP and FP_TO_SINT from/TO i64 even though i64 + // isn't legal. + setOperationAction(ISD::SINT_TO_FP , MVT::i64 , Custom); + setOperationAction(ISD::FP_TO_SINT , MVT::i64 , Custom); + } + setOperationAction(ISD::BRCONDTWOWAY , MVT::Other, Expand); setOperationAction(ISD::MEMMOVE , MVT::Other, Expand); setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16 , Expand); @@ -944,7 +954,7 @@ SDOperand X86TargetLowering::LowerOperation(SDOperand Op, SelectionDAG &DAG) { switch (Op.getOpcode()) { default: assert(0 && "Should not custom lower this!"); - case ISD::SINT_TO_FP: + case ISD::SINT_TO_FP: { assert(Op.getValueType() == MVT::f64 && Op.getOperand(0).getValueType() == MVT::i64 && "Unknown SINT_TO_FP to lower!"); @@ -963,6 +973,27 @@ Ops.push_back(StackSlot); return DAG.getNode(X86ISD::FILD64m, RTs, Ops); } + case ISD::FP_TO_SINT: { + assert(Op.getValueType() == MVT::i64 && + Op.getOperand(0).getValueType() == MVT::f64 && + "Unknown FP_TO_SINT to lower!"); + // We lower FP->sint64 into FISTP64, followed by a load, all to a temporary + // stack slot. + MachineFunction &MF = DAG.getMachineFunction(); + int SSFI = MF.getFrameInfo()->CreateStackObject(8, 8); + SDOperand StackSlot = DAG.getFrameIndex(SSFI, getPointerTy()); + + // Build the FISTP64 + std::vector Ops; + Ops.push_back(DAG.getEntryNode()); + Ops.push_back(Op.getOperand(0)); + Ops.push_back(StackSlot); + SDOperand FISTP = DAG.getNode(X86ISD::FISTP64m, MVT::Other, Ops); + + // Load the result. + return DAG.getLoad(MVT::i64, FISTP, StackSlot, DAG.getSrcValue(NULL)); + } + } } @@ -2475,7 +2506,8 @@ break; case MVT::i64: addFrameReference(BuildMI(BB, X86::FISTP64m, 5), FrameIdx).addReg(Tmp1); - break; } + break; + } switch (Node->getValueType(0)) { default: @@ -3320,16 +3352,11 @@ SelectAddress(Address, AM); Select(Chain); } - if (X86ScalarSSE) { - addFullAddress(BuildMI(BB, X86::FILD64m, 4, X86::FP0), AM); - addFullAddress(BuildMI(BB, X86::FST64m, 5), AM).addReg(X86::FP0); - addFullAddress(BuildMI(BB, X86::MOVSDrm, 4, Result), AM); - } else { - addFullAddress(BuildMI(BB, X86::FILD64m, 4, Result), AM); - } + + addFullAddress(BuildMI(BB, X86::FILD64m, 4, Result), AM); } return Result; - + case ISD::EXTLOAD: // Arbitrarily codegen extloads as MOVZX* case ISD::ZEXTLOAD: { // Make sure we generate both values. @@ -4328,6 +4355,23 @@ ExprMap.erase(N); SelectExpr(N.getValue(0)); return; + + case X86ISD::FISTP64m: { + assert(N.getOperand(1).getValueType() == MVT::f64); + X86AddressMode AM; + Select(N.getOperand(0)); // Select the token chain + + unsigned ValReg; + if (getRegPressure(N.getOperand(1)) > getRegPressure(N.getOperand(2))) { + ValReg = SelectExpr(N.getOperand(1)); + SelectAddress(N.getOperand(2), AM); + } else { + SelectAddress(N.getOperand(2), AM); + ValReg = SelectExpr(N.getOperand(1)); + } + addFullAddress(BuildMI(BB, X86::FISTP64m, 5), AM).addReg(ValReg); + return; + } case ISD::TRUNCSTORE: { // truncstore chain, val, ptr, SRCVALUE, storety X86AddressMode AM; From lattner at cs.uiuc.edu Thu Jul 28 19:54:45 2005 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Thu, 28 Jul 2005 19:54:45 -0500 Subject: [llvm-commits] CVS: llvm/lib/Target/X86/X86ISelPattern.cpp Message-ID: <200507290054.TAA15428@zion.cs.uiuc.edu> Changes in directory llvm/lib/Target/X86: X86ISelPattern.cpp updated: 1.156 -> 1.157 --- Log message: Don't forget to diddle with the control word when performing an FISTP64. --- Diffs of the changes: (+36 -8) X86ISelPattern.cpp | 44 ++++++++++++++++++++++++++++++++++++-------- 1 files changed, 36 insertions(+), 8 deletions(-) Index: llvm/lib/Target/X86/X86ISelPattern.cpp diff -u llvm/lib/Target/X86/X86ISelPattern.cpp:1.156 llvm/lib/Target/X86/X86ISelPattern.cpp:1.157 --- llvm/lib/Target/X86/X86ISelPattern.cpp:1.156 Thu Jul 28 19:40:01 2005 +++ llvm/lib/Target/X86/X86ISelPattern.cpp Thu Jul 28 19:54:34 2005 @@ -54,11 +54,12 @@ /// address) and two outputs (FP value and token chain). FILD64m, - /// FISTP64m - This instruction implements FP_TO_SINT with a - /// 64-bit destination in memory and a FP reg source. This corresponds to - /// the X86::FISTP64m instruction. It has two inputs (token chain and - /// address) and two outputs (FP value and token chain). - FISTP64m, + /// FP_TO_INT*_IN_MEM - This instruction implements FP_TO_SINT with the + /// integer destination in memory and a FP reg source. This corresponds + /// to the X86::FIST*m instructions and the rounding mode change stuff. It + /// has two inputs (token chain and address) and two outputs (FP value and + /// token chain). + FP_TO_INT64_IN_MEM, /// CALL/TAILCALL - These operations represent an abstract X86 call /// instruction, which includes a bunch of information. In particular the @@ -988,10 +989,10 @@ Ops.push_back(DAG.getEntryNode()); Ops.push_back(Op.getOperand(0)); Ops.push_back(StackSlot); - SDOperand FISTP = DAG.getNode(X86ISD::FISTP64m, MVT::Other, Ops); + SDOperand FIST = DAG.getNode(X86ISD::FP_TO_INT64_IN_MEM, MVT::Other, Ops); // Load the result. - return DAG.getLoad(MVT::i64, FISTP, StackSlot, DAG.getSrcValue(NULL)); + return DAG.getLoad(MVT::i64, FIST, StackSlot, DAG.getSrcValue(NULL)); } } } @@ -4356,7 +4357,7 @@ SelectExpr(N.getValue(0)); return; - case X86ISD::FISTP64m: { + case X86ISD::FP_TO_INT64_IN_MEM: { assert(N.getOperand(1).getValueType() == MVT::f64); X86AddressMode AM; Select(N.getOperand(0)); // Select the token chain @@ -4369,7 +4370,34 @@ SelectAddress(N.getOperand(2), AM); ValReg = SelectExpr(N.getOperand(1)); } + + // Change the floating point control register to use "round towards zero" + // mode when truncating to an integer value. + // + MachineFunction *F = BB->getParent(); + int CWFrameIdx = F->getFrameInfo()->CreateStackObject(2, 2); + addFrameReference(BuildMI(BB, X86::FNSTCW16m, 4), CWFrameIdx); + + // Load the old value of the high byte of the control word... + unsigned HighPartOfCW = MakeReg(MVT::i8); + addFrameReference(BuildMI(BB, X86::MOV8rm, 4, HighPartOfCW), + CWFrameIdx, 1); + + // Set the high part to be round to zero... + addFrameReference(BuildMI(BB, X86::MOV8mi, 5), + CWFrameIdx, 1).addImm(12); + + // Reload the modified control word now... + addFrameReference(BuildMI(BB, X86::FLDCW16m, 4), CWFrameIdx); + + // Restore the memory image of control word to original value + addFrameReference(BuildMI(BB, X86::MOV8mr, 5), + CWFrameIdx, 1).addReg(HighPartOfCW); + addFullAddress(BuildMI(BB, X86::FISTP64m, 5), AM).addReg(ValReg); + + // Reload the original control word now. + addFrameReference(BuildMI(BB, X86::FLDCW16m, 4), CWFrameIdx); return; } From lattner at cs.uiuc.edu Thu Jul 28 20:00:40 2005 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Thu, 28 Jul 2005 20:00:40 -0500 Subject: [llvm-commits] CVS: llvm/lib/Target/X86/X86ISelPattern.cpp Message-ID: <200507290100.UAA15533@zion.cs.uiuc.edu> Changes in directory llvm/lib/Target/X86: X86ISelPattern.cpp updated: 1.157 -> 1.158 --- Log message: Implement a FIXME: move a bunch of cruft for handling FP_TO_*INT operations that the X86 does not support to the legalizer. This allows it to be better optimized, etc, and will help with SSE support. --- Diffs of the changes: (+17 -27) X86ISelPattern.cpp | 44 +++++++++++++++++--------------------------- 1 files changed, 17 insertions(+), 27 deletions(-) Index: llvm/lib/Target/X86/X86ISelPattern.cpp diff -u llvm/lib/Target/X86/X86ISelPattern.cpp:1.157 llvm/lib/Target/X86/X86ISelPattern.cpp:1.158 --- llvm/lib/Target/X86/X86ISelPattern.cpp:1.157 Thu Jul 28 19:54:34 2005 +++ llvm/lib/Target/X86/X86ISelPattern.cpp Thu Jul 28 20:00:29 2005 @@ -132,6 +132,18 @@ setOperationAction(ISD::FP_TO_SINT , MVT::i64 , Custom); } + // Handle FP_TO_UINT by promoting the destination to a larger signed + // conversion. + setOperationAction(ISD::FP_TO_UINT , MVT::i1 , Promote); + setOperationAction(ISD::FP_TO_UINT , MVT::i8 , Promote); + setOperationAction(ISD::FP_TO_UINT , MVT::i16 , Promote); + setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Promote); + + // Promote i1/i8 FP_TO_SINT to larger FP_TO_SINTS's, as X86 doesn't have + // this operation. + setOperationAction(ISD::FP_TO_SINT , MVT::i1 , Promote); + setOperationAction(ISD::FP_TO_SINT , MVT::i8 , Promote); + setOperationAction(ISD::BRCONDTWOWAY , MVT::Other, Expand); setOperationAction(ISD::MEMMOVE , MVT::Other, Expand); setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16 , Expand); @@ -2437,15 +2449,13 @@ } return Result; } - case ISD::FP_TO_SINT: - case ISD::FP_TO_UINT: { - // FIXME: Most of this grunt work should be done by legalize! + case ISD::FP_TO_SINT: { Tmp1 = SelectExpr(N.getOperand(0)); // Get the operand register // If the target supports SSE2 and is performing FP operations in SSE regs // instead of the FP stack, then we can use the efficient CVTSS2SI and // CVTSD2SI instructions. - if (ISD::FP_TO_SINT == N.getOpcode() && X86ScalarSSE) { + if (X86ScalarSSE) { if (MVT::f32 == N.getOperand(0).getValueType()) { BuildMI(BB, X86::CVTTSS2SIrr, 1, Result).addReg(Tmp1); } else if (MVT::f64 == N.getOperand(0).getValueType()) { @@ -2480,34 +2490,18 @@ addFrameReference(BuildMI(BB, X86::MOV8mr, 5), CWFrameIdx, 1).addReg(HighPartOfCW); - // We don't have the facilities for directly storing byte sized data to - // memory. Promote it to 16 bits. We also must promote unsigned values to - // larger classes because we only have signed FP stores. - MVT::ValueType StoreClass = Node->getValueType(0); - if (StoreClass == MVT::i8 || Node->getOpcode() == ISD::FP_TO_UINT) - switch (StoreClass) { - case MVT::i1: - case MVT::i8: StoreClass = MVT::i16; break; - case MVT::i16: StoreClass = MVT::i32; break; - case MVT::i32: StoreClass = MVT::i64; break; - default: assert(0 && "Unknown store class!"); - } - // Spill the integer to memory and reload it from there. - unsigned Size = MVT::getSizeInBits(StoreClass)/8; + unsigned Size = MVT::getSizeInBits(Node->getValueType(0))/8; int FrameIdx = F->getFrameInfo()->CreateStackObject(Size, Size); - switch (StoreClass) { - default: assert(0 && "Unknown store class!"); + switch (Node->getValueType(0)) { + default: assert(0 && "Unsupported store class!"); case MVT::i16: addFrameReference(BuildMI(BB, X86::FIST16m, 5), FrameIdx).addReg(Tmp1); break; case MVT::i32: addFrameReference(BuildMI(BB, X86::FIST32m, 5), FrameIdx).addReg(Tmp1); break; - case MVT::i64: - addFrameReference(BuildMI(BB, X86::FISTP64m, 5), FrameIdx).addReg(Tmp1); - break; } switch (Node->getValueType(0)) { @@ -2519,10 +2513,6 @@ case MVT::i16: addFrameReference(BuildMI(BB, X86::MOV16rm, 4, Result), FrameIdx); break; - case MVT::i8: - case MVT::i1: - addFrameReference(BuildMI(BB, X86::MOV8rm, 4, Result), FrameIdx); - break; } // Reload the original control word now. From lattner at cs.uiuc.edu Fri Jul 29 13:09:04 2005 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Fri, 29 Jul 2005 13:09:04 -0500 Subject: [llvm-commits] CVS: llvm-test/MultiSource/Applications/spiff/Makefile Message-ID: <200507291809.NAA20619@zion.cs.uiuc.edu> Changes in directory llvm-test/MultiSource/Applications/spiff: Makefile updated: 1.2 -> 1.3 --- Log message: Allow this to find input files with SRCDIR != OBJDIR --- Diffs of the changes: (+1 -1) Makefile | 2 +- 1 files changed, 1 insertion(+), 1 deletion(-) Index: llvm-test/MultiSource/Applications/spiff/Makefile diff -u llvm-test/MultiSource/Applications/spiff/Makefile:1.2 llvm-test/MultiSource/Applications/spiff/Makefile:1.3 --- llvm-test/MultiSource/Applications/spiff/Makefile:1.2 Wed Sep 1 09:33:20 2004 +++ llvm-test/MultiSource/Applications/spiff/Makefile Fri Jul 29 13:08:48 2005 @@ -4,7 +4,7 @@ CFLAGS = LDFLAGS = -RUN_OPTIONS = ./Sample.1 ./Sample.2 +RUN_OPTIONS = $(PROJ_SRC_DIR)/Sample.1 $(PROJ_SRC_DIR)/Sample.2 #RUN_OPTIONS = ./Sample.3 ./Sample.4 #RUN_OPTIONS = ./one ./two # you get the idea... From lattner at cs.uiuc.edu Fri Jul 29 14:25:38 2005 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Fri, 29 Jul 2005 14:25:38 -0500 Subject: [llvm-commits] CVS: llvm-gcc/gcc/llvm-types.c Message-ID: <200507291925.OAA02718@zion.cs.uiuc.edu> Changes in directory llvm-gcc/gcc: llvm-types.c updated: 1.27 -> 1.28 --- Log message: Add an assert that catches the miscompilation of MallocBench/gs --- Diffs of the changes: (+6 -2) llvm-types.c | 8 ++++++-- 1 files changed, 6 insertions(+), 2 deletions(-) Index: llvm-gcc/gcc/llvm-types.c diff -u llvm-gcc/gcc/llvm-types.c:1.27 llvm-gcc/gcc/llvm-types.c:1.28 --- llvm-gcc/gcc/llvm-types.c:1.27 Thu Jul 28 17:02:53 2005 +++ llvm-gcc/gcc/llvm-types.c Fri Jul 29 14:25:27 2005 @@ -119,8 +119,12 @@ if (AlignmentInited == 0) { AlignmentInited = 1; InitializeAlignments(); } return PrimitiveAlignments[Ty->ID]; } - case ArrayTyID: return Ty->x.Array.Alignment; - case StructTyID: return Ty->x.Struct.Alignment; + case ArrayTyID: + assert(Ty->x.Array.Alignment && "Array does not have alignment set!"); + return Ty->x.Array.Alignment; + case StructTyID: + assert(Ty->x.Struct.Alignment && "Struct does not have alignment set!"); + return Ty->x.Struct.Alignment; default: fprintf(stderr, "ERROR: Type doesn't have size: "); llvm_type_dump(Ty); From lattner at cs.uiuc.edu Fri Jul 29 18:14:15 2005 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Fri, 29 Jul 2005 18:14:15 -0500 Subject: [llvm-commits] CVS: llvm-gcc/gcc/llvm-types.c Message-ID: <200507292314.SAA03828@zion.cs.uiuc.edu> Changes in directory llvm-gcc/gcc: llvm-types.c updated: 1.28 -> 1.29 --- Log message: Fix the compiler crash on MallocBench/gs --- Diffs of the changes: (+7 -6) llvm-types.c | 13 +++++++------ 1 files changed, 7 insertions(+), 6 deletions(-) Index: llvm-gcc/gcc/llvm-types.c diff -u llvm-gcc/gcc/llvm-types.c:1.28 llvm-gcc/gcc/llvm-types.c:1.29 --- llvm-gcc/gcc/llvm-types.c:1.28 Fri Jul 29 14:25:27 2005 +++ llvm-gcc/gcc/llvm-types.c Fri Jul 29 18:14:04 2005 @@ -119,12 +119,12 @@ if (AlignmentInited == 0) { AlignmentInited = 1; InitializeAlignments(); } return PrimitiveAlignments[Ty->ID]; } - case ArrayTyID: - assert(Ty->x.Array.Alignment && "Array does not have alignment set!"); - return Ty->x.Array.Alignment; + case ArrayTyID: + //assert(Ty->x.Array.Alignment && "Array does not have alignment set!"); + return Ty->x.Array.Alignment ? Ty->x.Array.Alignment : 4; case StructTyID: - assert(Ty->x.Struct.Alignment && "Struct does not have alignment set!"); - return Ty->x.Struct.Alignment; + //assert(Ty->x.Struct.Alignment && "Struct does not have alignment set!"); + return Ty->x.Struct.Alignment ? Ty->x.Struct.Alignment : 4; default: fprintf(stderr, "ERROR: Type doesn't have size: "); llvm_type_dump(Ty); @@ -1449,7 +1449,8 @@ if (Field && TREE_CODE(Field) != FIELD_DECL) Field = GetNextFieldDecl(Field); for (fieldcount = 0; Field; fieldcount++,Field = GetNextFieldDecl(Field)) { - assert ((fieldcount<256*4) && "LLVM can only have 1023 structure members!"); + assert ((fieldcount<256*4) && + "LLVM can only have 1023 structure members!"); DecodeFieldDecl(Field, StructElements, ElementOffsets, ElementAlignments, &Idx, &Size); From alenhar2 at cs.uiuc.edu Fri Jul 29 18:32:14 2005 From: alenhar2 at cs.uiuc.edu (Andrew Lenharth) Date: Fri, 29 Jul 2005 18:32:14 -0500 Subject: [llvm-commits] CVS: llvm/lib/Target/X86/X86JITInfo.h Message-ID: <200507292332.SAA06094@zion.cs.uiuc.edu> Changes in directory llvm/lib/Target/X86: X86JITInfo.h updated: 1.6 -> 1.7 --- Log message: turn off GOT on archs that didn't use it (not that it appeard to harm them much with it on) --- Diffs of the changes: (+1 -1) X86JITInfo.h | 2 +- 1 files changed, 1 insertion(+), 1 deletion(-) Index: llvm/lib/Target/X86/X86JITInfo.h diff -u llvm/lib/Target/X86/X86JITInfo.h:1.6 llvm/lib/Target/X86/X86JITInfo.h:1.7 --- llvm/lib/Target/X86/X86JITInfo.h:1.6 Fri Jul 22 15:49:37 2005 +++ llvm/lib/Target/X86/X86JITInfo.h Fri Jul 29 18:32:02 2005 @@ -23,7 +23,7 @@ class X86JITInfo : public TargetJITInfo { TargetMachine &TM; public: - X86JITInfo(TargetMachine &tm) : TM(tm) {} + X86JITInfo(TargetMachine &tm) : TM(tm) {useGOT = 0;} /// addPassesToJITCompile - Add passes to the specified pass manager to /// implement a fast dynamic compiler for this target. Return true if this From alenhar2 at cs.uiuc.edu Fri Jul 29 18:32:14 2005 From: alenhar2 at cs.uiuc.edu (Andrew Lenharth) Date: Fri, 29 Jul 2005 18:32:14 -0500 Subject: [llvm-commits] CVS: llvm/lib/Target/PowerPC/PowerPCJITInfo.h Message-ID: <200507292332.SAA06098@zion.cs.uiuc.edu> Changes in directory llvm/lib/Target/PowerPC: PowerPCJITInfo.h updated: 1.5 -> 1.6 --- Log message: turn off GOT on archs that didn't use it (not that it appeard to harm them much with it on) --- Diffs of the changes: (+1 -1) PowerPCJITInfo.h | 2 +- 1 files changed, 1 insertion(+), 1 deletion(-) Index: llvm/lib/Target/PowerPC/PowerPCJITInfo.h diff -u llvm/lib/Target/PowerPC/PowerPCJITInfo.h:1.5 llvm/lib/Target/PowerPC/PowerPCJITInfo.h:1.6 --- llvm/lib/Target/PowerPC/PowerPCJITInfo.h:1.5 Thu Apr 21 18:20:02 2005 +++ llvm/lib/Target/PowerPC/PowerPCJITInfo.h Fri Jul 29 18:32:02 2005 @@ -23,7 +23,7 @@ protected: TargetMachine &TM; public: - PowerPCJITInfo(TargetMachine &tm) : TM(tm) {} + PowerPCJITInfo(TargetMachine &tm) : TM(tm) {useGOT = 0;} /// addPassesToJITCompile - Add passes to the specified pass manager to /// implement a fast dynamic compiler for this target. Return true if this From alenhar2 at cs.uiuc.edu Fri Jul 29 18:32:14 2005 From: alenhar2 at cs.uiuc.edu (Andrew Lenharth) Date: Fri, 29 Jul 2005 18:32:14 -0500 Subject: [llvm-commits] CVS: llvm/lib/Target/SparcV9/SparcV9JITInfo.h Message-ID: <200507292332.SAA06102@zion.cs.uiuc.edu> Changes in directory llvm/lib/Target/SparcV9: SparcV9JITInfo.h updated: 1.9 -> 1.10 --- Log message: turn off GOT on archs that didn't use it (not that it appeard to harm them much with it on) --- Diffs of the changes: (+1 -1) SparcV9JITInfo.h | 2 +- 1 files changed, 1 insertion(+), 1 deletion(-) Index: llvm/lib/Target/SparcV9/SparcV9JITInfo.h diff -u llvm/lib/Target/SparcV9/SparcV9JITInfo.h:1.9 llvm/lib/Target/SparcV9/SparcV9JITInfo.h:1.10 --- llvm/lib/Target/SparcV9/SparcV9JITInfo.h:1.9 Fri Jul 22 15:49:37 2005 +++ llvm/lib/Target/SparcV9/SparcV9JITInfo.h Fri Jul 29 18:32:02 2005 @@ -24,7 +24,7 @@ class SparcV9JITInfo : public TargetJITInfo { TargetMachine &TM; public: - SparcV9JITInfo(TargetMachine &tm) : TM(tm) {} + SparcV9JITInfo(TargetMachine &tm) : TM(tm) {useGOT = 0;} /// addPassesToJITCompile - Add passes to the specified pass manager to /// implement a fast dynamic compiler for this target. Return true if this From alenhar2 at cs.uiuc.edu Fri Jul 29 18:38:53 2005 From: alenhar2 at cs.uiuc.edu (Andrew Lenharth) Date: Fri, 29 Jul 2005 18:38:53 -0500 Subject: [llvm-commits] CVS: llvm/include/llvm/System/Memory.h Message-ID: <200507292338.SAA06170@zion.cs.uiuc.edu> Changes in directory llvm/include/llvm/System: Memory.h updated: 1.5 -> 1.6 --- Log message: support near allocations for the JIT --- Diffs of the changes: (+3 -1) Memory.h | 4 +++- 1 files changed, 3 insertions(+), 1 deletion(-) Index: llvm/include/llvm/System/Memory.h diff -u llvm/include/llvm/System/Memory.h:1.5 llvm/include/llvm/System/Memory.h:1.6 --- llvm/include/llvm/System/Memory.h:1.5 Thu May 5 17:31:47 2005 +++ llvm/include/llvm/System/Memory.h Fri Jul 29 18:38:42 2005 @@ -43,9 +43,11 @@ /// This method allocates a block of Read/Write/Execute memory that is /// suitable for executing dynamically generated code (e.g. JIT). An /// attempt to allocate \p NumBytes bytes of virtual memory is made. + /// \p NearBlock may point to an existing allocation in which case + /// an attempt is made to allocate more memory near the existing block. /// @throws std::string if an error occurred. /// @brief Allocate Read/Write/Execute memory. - static MemoryBlock AllocateRWX(unsigned NumBytes); + static MemoryBlock AllocateRWX(unsigned NumBytes, const MemoryBlock* NearBlock); /// This method releases a block of Read/Write/Execute memory that was /// allocated with the AllocateRWX method. It should not be used to From alenhar2 at cs.uiuc.edu Fri Jul 29 18:39:37 2005 From: alenhar2 at cs.uiuc.edu (Andrew Lenharth) Date: Fri, 29 Jul 2005 18:39:37 -0500 Subject: [llvm-commits] CVS: llvm/lib/System/Unix/Memory.inc Message-ID: <200507292339.SAA06214@zion.cs.uiuc.edu> Changes in directory llvm/lib/System/Unix: Memory.inc updated: 1.3 -> 1.4 --- Log message: support near allocations for the JIT --- Diffs of the changes: (+9 -3) Memory.inc | 12 +++++++++--- 1 files changed, 9 insertions(+), 3 deletions(-) Index: llvm/lib/System/Unix/Memory.inc diff -u llvm/lib/System/Unix/Memory.inc:1.3 llvm/lib/System/Unix/Memory.inc:1.4 --- llvm/lib/System/Unix/Memory.inc:1.3 Thu May 5 17:33:06 2005 +++ llvm/lib/System/Unix/Memory.inc Fri Jul 29 18:39:25 2005 @@ -25,7 +25,7 @@ /// to emit code to the memory then jump to it. Getting this type of memory /// is very OS specific. /// -MemoryBlock Memory::AllocateRWX(unsigned NumBytes) { +MemoryBlock Memory::AllocateRWX(unsigned NumBytes, const MemoryBlock* NearBlock) { if (NumBytes == 0) return MemoryBlock(); long pageSize = Process::GetPageSize(); @@ -47,10 +47,16 @@ MAP_ANON #endif ; - void *pa = ::mmap(0, pageSize*NumPages, PROT_READ|PROT_WRITE|PROT_EXEC, + + void* start = NearBlock ? (unsigned char*) NearBlock->base() + NearBlock->size() : 0; + + void *pa = ::mmap(start, pageSize*NumPages, PROT_READ|PROT_WRITE|PROT_EXEC, flags, fd, 0); if (pa == MAP_FAILED) { - ThrowErrno("Can't allocate RWX Memory"); + if (NearBlock) //Try again without a near hint + return AllocateRWX(NumBytes, 0); + else + ThrowErrno("Can't allocate RWX Memory"); } MemoryBlock result; result.Address = pa; From alenhar2 at cs.uiuc.edu Fri Jul 29 18:39:37 2005 From: alenhar2 at cs.uiuc.edu (Andrew Lenharth) Date: Fri, 29 Jul 2005 18:39:37 -0500 Subject: [llvm-commits] CVS: llvm/lib/System/Win32/Memory.inc Message-ID: <200507292339.SAA06218@zion.cs.uiuc.edu> Changes in directory llvm/lib/System/Win32: Memory.inc updated: 1.5 -> 1.6 --- Log message: support near allocations for the JIT --- Diffs of the changes: (+3 -1) Memory.inc | 4 +++- 1 files changed, 3 insertions(+), 1 deletion(-) Index: llvm/lib/System/Win32/Memory.inc diff -u llvm/lib/System/Win32/Memory.inc:1.5 llvm/lib/System/Win32/Memory.inc:1.6 --- llvm/lib/System/Win32/Memory.inc:1.5 Thu May 5 17:33:09 2005 +++ llvm/lib/System/Win32/Memory.inc Fri Jul 29 18:39:25 2005 @@ -23,12 +23,14 @@ //=== and must not be UNIX code //===----------------------------------------------------------------------===// -MemoryBlock Memory::AllocateRWX(unsigned NumBytes) { +MemoryBlock Memory::AllocateRWX(unsigned NumBytes, const MemoryBlock* NearBlock) { if (NumBytes == 0) return MemoryBlock(); static const long pageSize = Process::GetPageSize(); unsigned NumPages = (NumBytes+pageSize-1)/pageSize; + //FIXME: support NearBlock if ever needed on Win64. + void *pa = VirtualAlloc(NULL, NumPages*pageSize, MEM_COMMIT, PAGE_EXECUTE_READWRITE); if (pa == NULL) { From alenhar2 at cs.uiuc.edu Fri Jul 29 18:40:27 2005 From: alenhar2 at cs.uiuc.edu (Andrew Lenharth) Date: Fri, 29 Jul 2005 18:40:27 -0500 Subject: [llvm-commits] CVS: llvm/lib/ExecutionEngine/JIT/JITEmitter.cpp Message-ID: <200507292340.SAA06250@zion.cs.uiuc.edu> Changes in directory llvm/lib/ExecutionEngine/JIT: JITEmitter.cpp updated: 1.73 -> 1.74 --- Log message: support near allocations for the JIT --- Diffs of the changes: (+75 -35) JITEmitter.cpp | 110 ++++++++++++++++++++++++++++++++++++++------------------- 1 files changed, 75 insertions(+), 35 deletions(-) Index: llvm/lib/ExecutionEngine/JIT/JITEmitter.cpp diff -u llvm/lib/ExecutionEngine/JIT/JITEmitter.cpp:1.73 llvm/lib/ExecutionEngine/JIT/JITEmitter.cpp:1.74 --- llvm/lib/ExecutionEngine/JIT/JITEmitter.cpp:1.73 Thu Jul 28 07:44:13 2005 +++ llvm/lib/ExecutionEngine/JIT/JITEmitter.cpp Fri Jul 29 18:40:16 2005 @@ -26,6 +26,8 @@ #include "llvm/Support/Debug.h" #include "llvm/ADT/Statistic.h" #include "llvm/System/Memory.h" +#include +#include using namespace llvm; namespace { @@ -47,12 +49,15 @@ /// are emitting is. This never bothers to release the memory, because when /// we are ready to destroy the JIT, the program exits. class JITMemoryManager { - sys::MemoryBlock MemBlock; // Virtual memory block allocated RWX - unsigned char *MemBase; // Base of block of memory, start of stub mem + std::list Blocks; // List of blocks allocated by the JIT unsigned char *FunctionBase; // Start of the function body area - unsigned char *ConstantPool; // Memory allocated for constant pools - unsigned char *CurStubPtr, *CurFunctionPtr, *CurConstantPtr; + unsigned char *GlobalBase; // Start of the Global area + unsigned char *ConstantBase; // Memory allocated for constant pools + unsigned char *CurStubPtr, *CurFunctionPtr, *CurConstantPtr, *CurGlobalPtr; unsigned char *GOTBase; //Target Specific reserved memory + + // centralize memory block allocation + sys::MemoryBlock getNewMemoryBlock(unsigned size); public: JITMemoryManager(bool useGOT); ~JITMemoryManager(); @@ -71,32 +76,45 @@ } JITMemoryManager::JITMemoryManager(bool useGOT) { - // Allocate a 16M block of memory... - MemBlock = sys::Memory::AllocateRWX((16 << 20)); - MemBase = reinterpret_cast(MemBlock.base()); - ConstantPool = MemBase; - GOTBase = ConstantPool + 512*1024; //512 for constants - //8k number of entries in the GOT - FunctionBase = GOTBase + 8192 * sizeof(void*) + 512*1024; // Use 512k for stubs - - //make it easier to tell if we are managing the GOT - if (!useGOT) - GOTBase = NULL; - - // Allocate stubs backwards from the function base, allocate functions forward - // from the function base. - CurStubPtr = CurFunctionPtr = FunctionBase; + // Allocate a 16M block of memory for functions + sys::MemoryBlock FunBlock = getNewMemoryBlock(16 << 20); + // Allocate a 1M block of memory for Constants + sys::MemoryBlock ConstBlock = getNewMemoryBlock(1 << 20); + // Allocate a 1M Block of memory for Globals + sys::MemoryBlock GVBlock = getNewMemoryBlock(1 << 20); + + Blocks.push_front(FunBlock); + Blocks.push_front(ConstBlock); + Blocks.push_front(GVBlock); + + FunctionBase = reinterpret_cast(FunBlock.base()); + ConstantBase = reinterpret_cast(ConstBlock.base()); + GlobalBase = reinterpret_cast(GVBlock.base()); + + //Allocate the GOT just like a global array + GOTBase = NULL; + if (useGOT) + GOTBase = allocateGlobal(sizeof(void*) * 8192, 8); + + // Allocate stubs backwards from the base, allocate functions forward + // from the base. + CurStubPtr = CurFunctionPtr = FunctionBase + 512*1024;// Use 512k for stubs - CurConstantPtr = ConstantPool + 512*1024; + CurConstantPtr = ConstantBase + ConstBlock.size(); + CurGlobalPtr = GlobalBase + GVBlock.size(); } JITMemoryManager::~JITMemoryManager() { - sys::Memory::ReleaseRWX(MemBlock); + for (std::list::iterator ib = Blocks.begin(), ie = Blocks.end(); + ib != ie; ++ib) + sys::Memory::ReleaseRWX(*ib); + Blocks.clear(); } unsigned char *JITMemoryManager::allocateStub(unsigned StubSize) { CurStubPtr -= StubSize; - if (CurStubPtr < MemBase) { + if (CurStubPtr < FunctionBase) { + //FIXME: allocate a new block std::cerr << "JIT ran out of memory for function stubs!\n"; abort(); } @@ -110,26 +128,31 @@ CurConstantPtr = (unsigned char *)((intptr_t)CurConstantPtr & ~((intptr_t)Alignment - 1)); - if (CurConstantPtr < ConstantPool) { - std::cerr << "JIT ran out of memory for constant pools!\n"; - abort(); + if (CurConstantPtr < ConstantBase) { + //Either allocate another MB or 2xConstantSize + sys::MemoryBlock ConstBlock = getNewMemoryBlock(2 * ConstantSize); + ConstantBase = reinterpret_cast(ConstBlock.base()); + CurConstantPtr = ConstantBase + ConstBlock.size(); + return allocateConstant(ConstantSize, Alignment); } return CurConstantPtr; } unsigned char *JITMemoryManager::allocateGlobal(unsigned Size, unsigned Alignment) { - // For now, intersperse them with Constants - // Reserve space and align pointer. - CurConstantPtr -= Size; - CurConstantPtr = - (unsigned char *)((intptr_t)CurConstantPtr & ~((intptr_t)Alignment - 1)); - - if (CurConstantPtr < ConstantPool) { - std::cerr << "JIT ran out of memory for Globals!\n"; - abort(); + // Reserve space and align pointer. + CurGlobalPtr -= Size; + CurGlobalPtr = + (unsigned char *)((intptr_t)CurGlobalPtr & ~((intptr_t)Alignment - 1)); + + if (CurGlobalPtr < GlobalBase) { + //Either allocate another MB or 2xSize + sys::MemoryBlock GVBlock = getNewMemoryBlock(2 * Size); + GlobalBase = reinterpret_cast(GVBlock.base()); + CurGlobalPtr = GlobalBase + GVBlock.size(); + return allocateGlobal(Size, Alignment); } - return CurConstantPtr; + return CurGlobalPtr; } unsigned char *JITMemoryManager::startFunctionBody() { @@ -151,6 +174,23 @@ return GOTBase != NULL; } +sys::MemoryBlock JITMemoryManager::getNewMemoryBlock(unsigned size) { + const sys::MemoryBlock* BOld = 0; + if (Blocks.size()) + BOld = &Blocks.front(); + //never allocate less than 1 MB + sys::MemoryBlock B; + try { + B = sys::Memory::AllocateRWX(std::max(((unsigned)1 << 20), size), BOld); + } catch (std::string& err) { + std::cerr << "Allocation failed when allocating new memory in the JIT\n"; + std::cerr << err << "\n"; + abort(); + } + Blocks.push_front(B); + return B; +} + //===----------------------------------------------------------------------===// // JIT lazy compilation code. // From lattner at cs.uiuc.edu Fri Jul 29 19:04:23 2005 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Fri, 29 Jul 2005 19:04:23 -0500 Subject: [llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp Message-ID: <200507300004.TAA06432@zion.cs.uiuc.edu> Changes in directory llvm/lib/CodeGen/SelectionDAG: LegalizeDAG.cpp updated: 1.147 -> 1.148 --- Log message: Allow targets to have custom expanders for FP_TO_*INT conversions where both the src and dest values are legal --- Diffs of the changes: (+9 -3) LegalizeDAG.cpp | 12 +++++++++--- 1 files changed, 9 insertions(+), 3 deletions(-) Index: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp diff -u llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.147 llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.148 --- llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.147 Thu Jul 28 19:33:32 2005 +++ llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp Fri Jul 29 19:04:12 2005 @@ -1570,21 +1570,27 @@ case ISD::FP_TO_UINT: switch (getTypeAction(Node->getOperand(0).getValueType())) { case Legal: + Tmp1 = LegalizeOp(Node->getOperand(0)); + switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))){ default: assert(0 && "Unknown operation action!"); case TargetLowering::Expand: assert(0 && "Cannot expand FP_TO*INT yet"); case TargetLowering::Promote: - Result = PromoteLegalFP_TO_INT(LegalizeOp(Node->getOperand(0)), - Node->getValueType(0), + Result = PromoteLegalFP_TO_INT(Tmp1, Node->getValueType(0), Node->getOpcode() == ISD::FP_TO_SINT); AddLegalizedOperand(Op, Result); return Result; case TargetLowering::Legal: break; + case TargetLowering::Custom: + Result = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1); + Result = TLI.LowerOperation(Result, DAG); + AddLegalizedOperand(Op, Result); + NeedsAnotherIteration = true; + return Result; } - Tmp1 = LegalizeOp(Node->getOperand(0)); if (Tmp1 != Node->getOperand(0)) Result = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1); break; From lattner at cs.uiuc.edu Fri Jul 29 19:06:05 2005 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Fri, 29 Jul 2005 19:06:05 -0500 Subject: [llvm-commits] CVS: llvm/lib/Target/X86/X86ISelPattern.cpp Message-ID: <200507300006.TAA06505@zion.cs.uiuc.edu> Changes in directory llvm/lib/Target/X86: X86ISelPattern.cpp updated: 1.158 -> 1.159 --- Log message: Use a custom expander for all FP to int conversions, as the X86 only has FP-to-int-in-memory: this exposes the load from the stored slot to the selection dag, allowing it to be folded into other operaions. --- Diffs of the changes: (+41 -71) X86ISelPattern.cpp | 112 +++++++++++++++++++---------------------------------- 1 files changed, 41 insertions(+), 71 deletions(-) Index: llvm/lib/Target/X86/X86ISelPattern.cpp diff -u llvm/lib/Target/X86/X86ISelPattern.cpp:1.158 llvm/lib/Target/X86/X86ISelPattern.cpp:1.159 --- llvm/lib/Target/X86/X86ISelPattern.cpp:1.158 Thu Jul 28 20:00:29 2005 +++ llvm/lib/Target/X86/X86ISelPattern.cpp Fri Jul 29 19:05:54 2005 @@ -59,6 +59,8 @@ /// to the X86::FIST*m instructions and the rounding mode change stuff. It /// has two inputs (token chain and address) and two outputs (FP value and /// token chain). + FP_TO_INT16_IN_MEM, + FP_TO_INT32_IN_MEM, FP_TO_INT64_IN_MEM, /// CALL/TAILCALL - These operations represent an abstract X86 call @@ -128,8 +130,10 @@ if (!X86ScalarSSE) { // We can handle SINT_TO_FP and FP_TO_SINT from/TO i64 even though i64 // isn't legal. - setOperationAction(ISD::SINT_TO_FP , MVT::i64 , Custom); - setOperationAction(ISD::FP_TO_SINT , MVT::i64 , Custom); + setOperationAction(ISD::SINT_TO_FP , MVT::i64 , Custom); + setOperationAction(ISD::FP_TO_SINT , MVT::i64 , Custom); + setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom); + setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Custom); } // Handle FP_TO_UINT by promoting the destination to a larger signed @@ -987,24 +991,34 @@ return DAG.getNode(X86ISD::FILD64m, RTs, Ops); } case ISD::FP_TO_SINT: { - assert(Op.getValueType() == MVT::i64 && + assert(Op.getValueType() <= MVT::i64 && Op.getValueType() >= MVT::i16 && Op.getOperand(0).getValueType() == MVT::f64 && "Unknown FP_TO_SINT to lower!"); // We lower FP->sint64 into FISTP64, followed by a load, all to a temporary // stack slot. MachineFunction &MF = DAG.getMachineFunction(); - int SSFI = MF.getFrameInfo()->CreateStackObject(8, 8); + unsigned MemSize = MVT::getSizeInBits(Op.getValueType())/8; + int SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize); SDOperand StackSlot = DAG.getFrameIndex(SSFI, getPointerTy()); - // Build the FISTP64 + unsigned Opc; + switch (Op.getValueType()) { + default: assert(0 && "Invalid FP_TO_SINT to lower!"); + case MVT::i16: Opc = X86ISD::FP_TO_INT16_IN_MEM; break; + case MVT::i32: Opc = X86ISD::FP_TO_INT32_IN_MEM; break; + case MVT::i64: Opc = X86ISD::FP_TO_INT64_IN_MEM; break; + } + + // Build the FP_TO_INT*_IN_MEM std::vector Ops; Ops.push_back(DAG.getEntryNode()); Ops.push_back(Op.getOperand(0)); Ops.push_back(StackSlot); - SDOperand FIST = DAG.getNode(X86ISD::FP_TO_INT64_IN_MEM, MVT::Other, Ops); + SDOperand FIST = DAG.getNode(Opc, MVT::Other, Ops); // Load the result. - return DAG.getLoad(MVT::i64, FIST, StackSlot, DAG.getSrcValue(NULL)); + return DAG.getLoad(Op.getValueType(), FIST, StackSlot, + DAG.getSrcValue(NULL)); } } } @@ -2449,76 +2463,23 @@ } return Result; } - case ISD::FP_TO_SINT: { + case ISD::FP_TO_SINT: Tmp1 = SelectExpr(N.getOperand(0)); // Get the operand register // If the target supports SSE2 and is performing FP operations in SSE regs // instead of the FP stack, then we can use the efficient CVTSS2SI and // CVTSD2SI instructions. - if (X86ScalarSSE) { - if (MVT::f32 == N.getOperand(0).getValueType()) { - BuildMI(BB, X86::CVTTSS2SIrr, 1, Result).addReg(Tmp1); - } else if (MVT::f64 == N.getOperand(0).getValueType()) { - BuildMI(BB, X86::CVTTSD2SIrr, 1, Result).addReg(Tmp1); - } else { - assert(0 && "Not an f32 or f64?"); - abort(); - } - return Result; - } - - // Change the floating point control register to use "round towards zero" - // mode when truncating to an integer value. - // - MachineFunction *F = BB->getParent(); - int CWFrameIdx = F->getFrameInfo()->CreateStackObject(2, 2); - addFrameReference(BuildMI(BB, X86::FNSTCW16m, 4), CWFrameIdx); - - // Load the old value of the high byte of the control word... - unsigned HighPartOfCW = MakeReg(MVT::i8); - addFrameReference(BuildMI(BB, X86::MOV8rm, 4, HighPartOfCW), - CWFrameIdx, 1); - - // Set the high part to be round to zero... - addFrameReference(BuildMI(BB, X86::MOV8mi, 5), - CWFrameIdx, 1).addImm(12); - - // Reload the modified control word now... - addFrameReference(BuildMI(BB, X86::FLDCW16m, 4), CWFrameIdx); - - // Restore the memory image of control word to original value - addFrameReference(BuildMI(BB, X86::MOV8mr, 5), - CWFrameIdx, 1).addReg(HighPartOfCW); - - // Spill the integer to memory and reload it from there. - unsigned Size = MVT::getSizeInBits(Node->getValueType(0))/8; - int FrameIdx = F->getFrameInfo()->CreateStackObject(Size, Size); - - switch (Node->getValueType(0)) { - default: assert(0 && "Unsupported store class!"); - case MVT::i16: - addFrameReference(BuildMI(BB, X86::FIST16m, 5), FrameIdx).addReg(Tmp1); - break; - case MVT::i32: - addFrameReference(BuildMI(BB, X86::FIST32m, 5), FrameIdx).addReg(Tmp1); - break; - } - - switch (Node->getValueType(0)) { - default: - assert(0 && "Unknown integer type!"); - case MVT::i32: - addFrameReference(BuildMI(BB, X86::MOV32rm, 4, Result), FrameIdx); - break; - case MVT::i16: - addFrameReference(BuildMI(BB, X86::MOV16rm, 4, Result), FrameIdx); - break; + assert(X86ScalarSSE); + if (MVT::f32 == N.getOperand(0).getValueType()) { + BuildMI(BB, X86::CVTTSS2SIrr, 1, Result).addReg(Tmp1); + } else if (MVT::f64 == N.getOperand(0).getValueType()) { + BuildMI(BB, X86::CVTTSD2SIrr, 1, Result).addReg(Tmp1); + } else { + assert(0 && "Not an f32 or f64?"); + abort(); } - - // Reload the original control word now. - addFrameReference(BuildMI(BB, X86::FLDCW16m, 4), CWFrameIdx); return Result; - } + case ISD::ADD: Op0 = N.getOperand(0); Op1 = N.getOperand(1); @@ -4347,6 +4308,8 @@ SelectExpr(N.getValue(0)); return; + case X86ISD::FP_TO_INT16_IN_MEM: + case X86ISD::FP_TO_INT32_IN_MEM: case X86ISD::FP_TO_INT64_IN_MEM: { assert(N.getOperand(1).getValueType() == MVT::f64); X86AddressMode AM; @@ -4383,8 +4346,15 @@ // Restore the memory image of control word to original value addFrameReference(BuildMI(BB, X86::MOV8mr, 5), CWFrameIdx, 1).addReg(HighPartOfCW); + + // Get the X86 opcode to use. + switch (N.getOpcode()) { + case X86ISD::FP_TO_INT16_IN_MEM: Tmp1 = X86::FIST16m; break; + case X86ISD::FP_TO_INT32_IN_MEM: Tmp1 = X86::FIST32m; break; + case X86ISD::FP_TO_INT64_IN_MEM: Tmp1 = X86::FISTP64m; break; + } - addFullAddress(BuildMI(BB, X86::FISTP64m, 5), AM).addReg(ValReg); + addFullAddress(BuildMI(BB, Tmp1, 5), AM).addReg(ValReg); // Reload the original control word now. addFrameReference(BuildMI(BB, X86::FLDCW16m, 4), CWFrameIdx); From natebegeman at mac.com Fri Jul 29 19:12:31 2005 From: natebegeman at mac.com (Nate Begeman) Date: Fri, 29 Jul 2005 19:12:31 -0500 Subject: [llvm-commits] CVS: llvm/include/llvm/Analysis/ScalarEvolutionExpander.h Message-ID: <200507300012.TAA06554@zion.cs.uiuc.edu> Changes in directory llvm/include/llvm/Analysis: ScalarEvolutionExpander.h added (r1.1) --- Log message: Break SCEVExpander out of IndVarSimplify into its own .h/.cpp file so that other passes may use it. --- Diffs of the changes: (+180 -0) ScalarEvolutionExpander.h | 180 ++++++++++++++++++++++++++++++++++++++++++++++ 1 files changed, 180 insertions(+) Index: llvm/include/llvm/Analysis/ScalarEvolutionExpander.h diff -c /dev/null llvm/include/llvm/Analysis/ScalarEvolutionExpander.h:1.1 *** /dev/null Fri Jul 29 19:12:29 2005 --- llvm/include/llvm/Analysis/ScalarEvolutionExpander.h Fri Jul 29 19:12:19 2005 *************** *** 0 **** --- 1,180 ---- + //===---- llvm/Analysis/ScalarEvolutionExpander.h - SCEV Exprs --*- C++ -*-===// + // + // The LLVM Compiler Infrastructure + // + // This file was developed by the LLVM research group and is distributed under + // the University of Illinois Open Source License. See LICENSE.TXT for details. + // + //===----------------------------------------------------------------------===// + // + // This file defines the classes used to generate code from scalar expressions. + // + //===----------------------------------------------------------------------===// + + #ifndef LLVM_ANALYSIS_SCALAREVOLUTION_EXPANDER_H + #define LLVM_ANALYSIS_SCALAREVOLUTION_EXPANDER_H + + #include "llvm/BasicBlock.h" + #include "llvm/Constants.h" + #include "llvm/Instructions.h" + #include "llvm/Type.h" + #include "llvm/Analysis/ScalarEvolution.h" + #include "llvm/Analysis/ScalarEvolutionExpressions.h" + #include "llvm/Support/CFG.h" + + namespace llvm { + /// SCEVExpander - This class uses information about analyze scalars to + /// rewrite expressions in canonical form. + /// + /// Clients should create an instance of this class when rewriting is needed, + /// and destroying it when finished to allow the release of the associated + /// memory. + struct SCEVExpander : public SCEVVisitor { + ScalarEvolution &SE; + LoopInfo &LI; + std::map InsertedExpressions; + std::set InsertedInstructions; + + Instruction *InsertPt; + + friend struct SCEVVisitor; + public: + SCEVExpander(ScalarEvolution &se, LoopInfo &li) : SE(se), LI(li) {} + + /// clear - Erase the contents of the InsertedExpressions map so that users + /// trying to expand the same expression into multiple BasicBlocks or + /// different places within the same BasicBlock can do so. + void clear() { InsertedExpressions.clear(); } + + /// isInsertedInstruction - Return true if the specified instruction was + /// inserted by the code rewriter. If so, the client should not modify the + /// instruction. + bool isInsertedInstruction(Instruction *I) const { + return InsertedInstructions.count(I); + } + + /// getOrInsertCanonicalInductionVariable - This method returns the + /// canonical induction variable of the specified type for the specified + /// loop (inserting one if there is none). A canonical induction variable + /// starts at zero and steps by one on each iteration. + Value *getOrInsertCanonicalInductionVariable(const Loop *L, const Type *Ty){ + assert((Ty->isInteger() || Ty->isFloatingPoint()) && + "Can only insert integer or floating point induction variables!"); + SCEVHandle H = SCEVAddRecExpr::get(SCEVUnknown::getIntegerSCEV(0, Ty), + SCEVUnknown::getIntegerSCEV(1, Ty), L); + return expand(H); + } + + /// addInsertedValue - Remember the specified instruction as being the + /// canonical form for the specified SCEV. + void addInsertedValue(Instruction *I, SCEV *S) { + InsertedExpressions[S] = (Value*)I; + InsertedInstructions.insert(I); + } + + /// expandCodeFor - Insert code to directly compute the specified SCEV + /// expression into the program. The inserted code is inserted into the + /// specified block. + /// + /// If a particular value sign is required, a type may be specified for the + /// result. + Value *expandCodeFor(SCEVHandle SH, Instruction *IP, const Type *Ty = 0) { + // Expand the code for this SCEV. + this->InsertPt = IP; + return expandInTy(SH, Ty); + } + + protected: + Value *expand(SCEV *S) { + // Check to see if we already expanded this. + std::map::iterator I = InsertedExpressions.find(S); + if (I != InsertedExpressions.end()) + return I->second; + + Value *V = visit(S); + InsertedExpressions[S] = V; + return V; + } + + Value *expandInTy(SCEV *S, const Type *Ty) { + Value *V = expand(S); + if (Ty && V->getType() != Ty) { + // FIXME: keep track of the cast instruction. + if (Constant *C = dyn_cast(V)) + return ConstantExpr::getCast(C, Ty); + else if (Instruction *I = dyn_cast(V)) { + // Check to see if there is already a cast. If there is, use it. + for (Value::use_iterator UI = I->use_begin(), E = I->use_end(); + UI != E; ++UI) { + if ((*UI)->getType() == Ty) + if (CastInst *CI = dyn_cast(cast(*UI))) { + BasicBlock::iterator It = I; ++It; + if (isa(I)) + It = cast(I)->getNormalDest()->begin(); + while (isa(It)) ++It; + if (It != BasicBlock::iterator(CI)) { + // Splice the cast immediately after the operand in question. + BasicBlock::InstListType &InstList = + It->getParent()->getInstList(); + InstList.splice(It, CI->getParent()->getInstList(), CI); + } + return CI; + } + } + BasicBlock::iterator IP = I; ++IP; + if (InvokeInst *II = dyn_cast(I)) + IP = II->getNormalDest()->begin(); + while (isa(IP)) ++IP; + return new CastInst(V, Ty, V->getName(), IP); + } else { + // FIXME: check to see if there is already a cast! + return new CastInst(V, Ty, V->getName(), InsertPt); + } + } + return V; + } + + Value *visitConstant(SCEVConstant *S) { + return S->getValue(); + } + + Value *visitTruncateExpr(SCEVTruncateExpr *S) { + Value *V = expand(S->getOperand()); + return new CastInst(V, S->getType(), "tmp.", InsertPt); + } + + Value *visitZeroExtendExpr(SCEVZeroExtendExpr *S) { + Value *V = expandInTy(S->getOperand(),S->getType()->getUnsignedVersion()); + return new CastInst(V, S->getType(), "tmp.", InsertPt); + } + + Value *visitAddExpr(SCEVAddExpr *S) { + const Type *Ty = S->getType(); + Value *V = expandInTy(S->getOperand(S->getNumOperands()-1), Ty); + + // Emit a bunch of add instructions + for (int i = S->getNumOperands()-2; i >= 0; --i) + V = BinaryOperator::createAdd(V, expandInTy(S->getOperand(i), Ty), + "tmp.", InsertPt); + return V; + } + + Value *visitMulExpr(SCEVMulExpr *S); + + Value *visitUDivExpr(SCEVUDivExpr *S) { + const Type *Ty = S->getType(); + Value *LHS = expandInTy(S->getLHS(), Ty); + Value *RHS = expandInTy(S->getRHS(), Ty); + return BinaryOperator::createDiv(LHS, RHS, "tmp.", InsertPt); + } + + Value *visitAddRecExpr(SCEVAddRecExpr *S); + + Value *visitUnknown(SCEVUnknown *S) { + return S->getValue(); + } + }; + } + + #endif + From natebegeman at mac.com Fri Jul 29 19:12:31 2005 From: natebegeman at mac.com (Nate Begeman) Date: Fri, 29 Jul 2005 19:12:31 -0500 Subject: [llvm-commits] CVS: llvm/lib/Analysis/ScalarEvolutionExpander.cpp Message-ID: <200507300012.TAA06562@zion.cs.uiuc.edu> Changes in directory llvm/lib/Analysis: ScalarEvolutionExpander.cpp added (r1.1) --- Log message: Break SCEVExpander out of IndVarSimplify into its own .h/.cpp file so that other passes may use it. --- Diffs of the changes: (+105 -0) ScalarEvolutionExpander.cpp | 105 ++++++++++++++++++++++++++++++++++++++++++++ 1 files changed, 105 insertions(+) Index: llvm/lib/Analysis/ScalarEvolutionExpander.cpp diff -c /dev/null llvm/lib/Analysis/ScalarEvolutionExpander.cpp:1.1 *** /dev/null Fri Jul 29 19:12:29 2005 --- llvm/lib/Analysis/ScalarEvolutionExpander.cpp Fri Jul 29 19:12:19 2005 *************** *** 0 **** --- 1,105 ---- + //===- ScalarEvolutionExpander.cpp - Scalar Evolution Analysis --*- C++ -*-===// + // + // The LLVM Compiler Infrastructure + // + // This file was developed by the LLVM research group and is distributed under + // the University of Illinois Open Source License. See LICENSE.TXT for details. + // + //===----------------------------------------------------------------------===// + // + // This file contains the implementation of the scalar evolution expander, + // which is used to generate the code corresponding to a given scalar evolution + // expression. + // + //===----------------------------------------------------------------------===// + + #include "llvm/Analysis/LoopInfo.h" + #include "llvm/Analysis/ScalarEvolutionExpander.h" + using namespace llvm; + + Value *SCEVExpander::visitMulExpr(SCEVMulExpr *S) { + const Type *Ty = S->getType(); + int FirstOp = 0; // Set if we should emit a subtract. + if (SCEVConstant *SC = dyn_cast(S->getOperand(0))) + if (SC->getValue()->isAllOnesValue()) + FirstOp = 1; + + int i = S->getNumOperands()-2; + Value *V = expandInTy(S->getOperand(i+1), Ty); + + // Emit a bunch of multiply instructions + for (; i >= FirstOp; --i) + V = BinaryOperator::createMul(V, expandInTy(S->getOperand(i), Ty), + "tmp.", InsertPt); + // -1 * ... ---> 0 - ... + if (FirstOp == 1) + V = BinaryOperator::createNeg(V, "tmp.", InsertPt); + return V; + } + + Value *SCEVExpander::visitAddRecExpr(SCEVAddRecExpr *S) { + const Type *Ty = S->getType(); + const Loop *L = S->getLoop(); + // We cannot yet do fp recurrences, e.g. the xform of {X,+,F} --> X+{0,+,F} + assert(Ty->isIntegral() && "Cannot expand fp recurrences yet!"); + + // {X,+,F} --> X + {0,+,F} + if (!isa(S->getStart()) || + !cast(S->getStart())->getValue()->isNullValue()) { + Value *Start = expandInTy(S->getStart(), Ty); + std::vector NewOps(S->op_begin(), S->op_end()); + NewOps[0] = SCEVUnknown::getIntegerSCEV(0, Ty); + Value *Rest = expandInTy(SCEVAddRecExpr::get(NewOps, L), Ty); + + // FIXME: look for an existing add to use. + return BinaryOperator::createAdd(Rest, Start, "tmp.", InsertPt); + } + + // {0,+,1} --> Insert a canonical induction variable into the loop! + if (S->getNumOperands() == 2 && + S->getOperand(1) == SCEVUnknown::getIntegerSCEV(1, Ty)) { + // Create and insert the PHI node for the induction variable in the + // specified loop. + BasicBlock *Header = L->getHeader(); + PHINode *PN = new PHINode(Ty, "indvar", Header->begin()); + PN->addIncoming(Constant::getNullValue(Ty), L->getLoopPreheader()); + + pred_iterator HPI = pred_begin(Header); + assert(HPI != pred_end(Header) && "Loop with zero preds???"); + if (!L->contains(*HPI)) ++HPI; + assert(HPI != pred_end(Header) && L->contains(*HPI) && + "No backedge in loop?"); + + // Insert a unit add instruction right before the terminator corresponding + // to the back-edge. + Constant *One = Ty->isFloatingPoint() ? (Constant*)ConstantFP::get(Ty, 1.0) + : ConstantInt::get(Ty, 1); + Instruction *Add = BinaryOperator::createAdd(PN, One, "indvar.next", + (*HPI)->getTerminator()); + + pred_iterator PI = pred_begin(Header); + if (*PI == L->getLoopPreheader()) + ++PI; + PN->addIncoming(Add, *PI); + return PN; + } + + // Get the canonical induction variable I for this loop. + Value *I = getOrInsertCanonicalInductionVariable(L, Ty); + + if (S->getNumOperands() == 2) { // {0,+,F} --> i*F + Value *F = expandInTy(S->getOperand(1), Ty); + return BinaryOperator::createMul(I, F, "tmp.", InsertPt); + } + + // If this is a chain of recurrences, turn it into a closed form, using the + // folders, then expandCodeFor the closed form. This allows the folders to + // simplify the expression without having to build a bunch of special code + // into this folder. + SCEVHandle IH = SCEVUnknown::get(I); // Get I as a "symbolic" SCEV. + + SCEVHandle V = S->evaluateAtIteration(IH); + //std::cerr << "Evaluated: " << *this << "\n to: " << *V << "\n"; + + return expandInTy(V, Ty); + } From natebegeman at mac.com Fri Jul 29 19:12:31 2005 From: natebegeman at mac.com (Nate Begeman) Date: Fri, 29 Jul 2005 19:12:31 -0500 Subject: [llvm-commits] CVS: llvm/lib/Transforms/Scalar/IndVarSimplify.cpp Message-ID: <200507300012.TAA06558@zion.cs.uiuc.edu> Changes in directory llvm/lib/Transforms/Scalar: IndVarSimplify.cpp updated: 1.78 -> 1.79 --- Log message: Break SCEVExpander out of IndVarSimplify into its own .h/.cpp file so that other passes may use it. --- Diffs of the changes: (+1 -238) IndVarSimplify.cpp | 239 ----------------------------------------------------- 1 files changed, 1 insertion(+), 238 deletions(-) Index: llvm/lib/Transforms/Scalar/IndVarSimplify.cpp diff -u llvm/lib/Transforms/Scalar/IndVarSimplify.cpp:1.78 llvm/lib/Transforms/Scalar/IndVarSimplify.cpp:1.79 --- llvm/lib/Transforms/Scalar/IndVarSimplify.cpp:1.78 Wed Jun 15 16:29:31 2005 +++ llvm/lib/Transforms/Scalar/IndVarSimplify.cpp Fri Jul 29 19:12:19 2005 @@ -42,7 +42,7 @@ #include "llvm/Constants.h" #include "llvm/Instructions.h" #include "llvm/Type.h" -#include "llvm/Analysis/ScalarEvolutionExpressions.h" +#include "llvm/Analysis/ScalarEvolutionExpander.h" #include "llvm/Analysis/LoopInfo.h" #include "llvm/Support/CFG.h" #include "llvm/Support/GetElementPtrTypeIterator.h" @@ -52,243 +52,6 @@ using namespace llvm; namespace { - /// SCEVExpander - This class uses information about analyze scalars to - /// rewrite expressions in canonical form. - /// - /// Clients should create an instance of this class when rewriting is needed, - /// and destroying it when finished to allow the release of the associated - /// memory. - struct SCEVExpander : public SCEVVisitor { - ScalarEvolution &SE; - LoopInfo &LI; - std::map InsertedExpressions; - std::set InsertedInstructions; - - Instruction *InsertPt; - - friend struct SCEVVisitor; - public: - SCEVExpander(ScalarEvolution &se, LoopInfo &li) : SE(se), LI(li) {} - - /// isInsertedInstruction - Return true if the specified instruction was - /// inserted by the code rewriter. If so, the client should not modify the - /// instruction. - bool isInsertedInstruction(Instruction *I) const { - return InsertedInstructions.count(I); - } - - /// getOrInsertCanonicalInductionVariable - This method returns the - /// canonical induction variable of the specified type for the specified - /// loop (inserting one if there is none). A canonical induction variable - /// starts at zero and steps by one on each iteration. - Value *getOrInsertCanonicalInductionVariable(const Loop *L, const Type *Ty){ - assert((Ty->isInteger() || Ty->isFloatingPoint()) && - "Can only insert integer or floating point induction variables!"); - SCEVHandle H = SCEVAddRecExpr::get(SCEVUnknown::getIntegerSCEV(0, Ty), - SCEVUnknown::getIntegerSCEV(1, Ty), L); - return expand(H); - } - - /// addInsertedValue - Remember the specified instruction as being the - /// canonical form for the specified SCEV. - void addInsertedValue(Instruction *I, SCEV *S) { - InsertedExpressions[S] = (Value*)I; - InsertedInstructions.insert(I); - } - - /// expandCodeFor - Insert code to directly compute the specified SCEV - /// expression into the program. The inserted code is inserted into the - /// specified block. - /// - /// If a particular value sign is required, a type may be specified for the - /// result. - Value *expandCodeFor(SCEVHandle SH, Instruction *IP, const Type *Ty = 0) { - // Expand the code for this SCEV. - this->InsertPt = IP; - return expandInTy(SH, Ty); - } - - protected: - Value *expand(SCEV *S) { - // Check to see if we already expanded this. - std::map::iterator I = InsertedExpressions.find(S); - if (I != InsertedExpressions.end()) - return I->second; - - Value *V = visit(S); - InsertedExpressions[S] = V; - return V; - } - - Value *expandInTy(SCEV *S, const Type *Ty) { - Value *V = expand(S); - if (Ty && V->getType() != Ty) { - // FIXME: keep track of the cast instruction. - if (Constant *C = dyn_cast(V)) - return ConstantExpr::getCast(C, Ty); - else if (Instruction *I = dyn_cast(V)) { - // Check to see if there is already a cast. If there is, use it. - for (Value::use_iterator UI = I->use_begin(), E = I->use_end(); - UI != E; ++UI) { - if ((*UI)->getType() == Ty) - if (CastInst *CI = dyn_cast(cast(*UI))) { - BasicBlock::iterator It = I; ++It; - if (isa(I)) - It = cast(I)->getNormalDest()->begin(); - while (isa(It)) ++It; - if (It != BasicBlock::iterator(CI)) { - // Splice the cast immediately after the operand in question. - BasicBlock::InstListType &InstList = - It->getParent()->getInstList(); - InstList.splice(It, CI->getParent()->getInstList(), CI); - } - return CI; - } - } - BasicBlock::iterator IP = I; ++IP; - if (InvokeInst *II = dyn_cast(I)) - IP = II->getNormalDest()->begin(); - while (isa(IP)) ++IP; - return new CastInst(V, Ty, V->getName(), IP); - } else { - // FIXME: check to see if there is already a cast! - return new CastInst(V, Ty, V->getName(), InsertPt); - } - } - return V; - } - - Value *visitConstant(SCEVConstant *S) { - return S->getValue(); - } - - Value *visitTruncateExpr(SCEVTruncateExpr *S) { - Value *V = expand(S->getOperand()); - return new CastInst(V, S->getType(), "tmp.", InsertPt); - } - - Value *visitZeroExtendExpr(SCEVZeroExtendExpr *S) { - Value *V = expandInTy(S->getOperand(),S->getType()->getUnsignedVersion()); - return new CastInst(V, S->getType(), "tmp.", InsertPt); - } - - Value *visitAddExpr(SCEVAddExpr *S) { - const Type *Ty = S->getType(); - Value *V = expandInTy(S->getOperand(S->getNumOperands()-1), Ty); - - // Emit a bunch of add instructions - for (int i = S->getNumOperands()-2; i >= 0; --i) - V = BinaryOperator::createAdd(V, expandInTy(S->getOperand(i), Ty), - "tmp.", InsertPt); - return V; - } - - Value *visitMulExpr(SCEVMulExpr *S); - - Value *visitUDivExpr(SCEVUDivExpr *S) { - const Type *Ty = S->getType(); - Value *LHS = expandInTy(S->getLHS(), Ty); - Value *RHS = expandInTy(S->getRHS(), Ty); - return BinaryOperator::createDiv(LHS, RHS, "tmp.", InsertPt); - } - - Value *visitAddRecExpr(SCEVAddRecExpr *S); - - Value *visitUnknown(SCEVUnknown *S) { - return S->getValue(); - } - }; -} - -Value *SCEVExpander::visitMulExpr(SCEVMulExpr *S) { - const Type *Ty = S->getType(); - int FirstOp = 0; // Set if we should emit a subtract. - if (SCEVConstant *SC = dyn_cast(S->getOperand(0))) - if (SC->getValue()->isAllOnesValue()) - FirstOp = 1; - - int i = S->getNumOperands()-2; - Value *V = expandInTy(S->getOperand(i+1), Ty); - - // Emit a bunch of multiply instructions - for (; i >= FirstOp; --i) - V = BinaryOperator::createMul(V, expandInTy(S->getOperand(i), Ty), - "tmp.", InsertPt); - // -1 * ... ---> 0 - ... - if (FirstOp == 1) - V = BinaryOperator::createNeg(V, "tmp.", InsertPt); - return V; -} - -Value *SCEVExpander::visitAddRecExpr(SCEVAddRecExpr *S) { - const Type *Ty = S->getType(); - const Loop *L = S->getLoop(); - // We cannot yet do fp recurrences, e.g. the xform of {X,+,F} --> X+{0,+,F} - assert(Ty->isIntegral() && "Cannot expand fp recurrences yet!"); - - // {X,+,F} --> X + {0,+,F} - if (!isa(S->getStart()) || - !cast(S->getStart())->getValue()->isNullValue()) { - Value *Start = expandInTy(S->getStart(), Ty); - std::vector NewOps(S->op_begin(), S->op_end()); - NewOps[0] = SCEVUnknown::getIntegerSCEV(0, Ty); - Value *Rest = expandInTy(SCEVAddRecExpr::get(NewOps, L), Ty); - - // FIXME: look for an existing add to use. - return BinaryOperator::createAdd(Rest, Start, "tmp.", InsertPt); - } - - // {0,+,1} --> Insert a canonical induction variable into the loop! - if (S->getNumOperands() == 2 && - S->getOperand(1) == SCEVUnknown::getIntegerSCEV(1, Ty)) { - // Create and insert the PHI node for the induction variable in the - // specified loop. - BasicBlock *Header = L->getHeader(); - PHINode *PN = new PHINode(Ty, "indvar", Header->begin()); - PN->addIncoming(Constant::getNullValue(Ty), L->getLoopPreheader()); - - pred_iterator HPI = pred_begin(Header); - assert(HPI != pred_end(Header) && "Loop with zero preds???"); - if (!L->contains(*HPI)) ++HPI; - assert(HPI != pred_end(Header) && L->contains(*HPI) && - "No backedge in loop?"); - - // Insert a unit add instruction right before the terminator corresponding - // to the back-edge. - Constant *One = Ty->isFloatingPoint() ? (Constant*)ConstantFP::get(Ty, 1.0) - : ConstantInt::get(Ty, 1); - Instruction *Add = BinaryOperator::createAdd(PN, One, "indvar.next", - (*HPI)->getTerminator()); - - pred_iterator PI = pred_begin(Header); - if (*PI == L->getLoopPreheader()) - ++PI; - PN->addIncoming(Add, *PI); - return PN; - } - - // Get the canonical induction variable I for this loop. - Value *I = getOrInsertCanonicalInductionVariable(L, Ty); - - if (S->getNumOperands() == 2) { // {0,+,F} --> i*F - Value *F = expandInTy(S->getOperand(1), Ty); - return BinaryOperator::createMul(I, F, "tmp.", InsertPt); - } - - // If this is a chain of recurrences, turn it into a closed form, using the - // folders, then expandCodeFor the closed form. This allows the folders to - // simplify the expression without having to build a bunch of special code - // into this folder. - SCEVHandle IH = SCEVUnknown::get(I); // Get I as a "symbolic" SCEV. - - SCEVHandle V = S->evaluateAtIteration(IH); - //std::cerr << "Evaluated: " << *this << "\n to: " << *V << "\n"; - - return expandInTy(V, Ty); -} - - -namespace { Statistic<> NumRemoved ("indvars", "Number of aux indvars removed"); Statistic<> NumPointer ("indvars", "Number of pointer indvars promoted"); Statistic<> NumInserted("indvars", "Number of canonical indvars added"); From lattner at cs.uiuc.edu Fri Jul 29 19:18:04 2005 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Fri, 29 Jul 2005 19:18:04 -0500 Subject: [llvm-commits] CVS: llvm/lib/Target/X86/X86ISelPattern.cpp Message-ID: <200507300018.TAA06698@zion.cs.uiuc.edu> Changes in directory llvm/lib/Target/X86: X86ISelPattern.cpp updated: 1.159 -> 1.160 --- Log message: Change the fp to integer code to not perform 2-byte stores followed by 1 byte loads and other operations. This is bad for store-forwarding on common CPUs. We now do this: fnstcw WORD PTR [%ESP] mov %AX, WORD PTR [%ESP] instead of: fnstcw WORD PTR [%ESP] mov %AL, BYTE PTR [%ESP + 1] --- Diffs of the changes: (+4 -7) X86ISelPattern.cpp | 11 ++++------- 1 files changed, 4 insertions(+), 7 deletions(-) Index: llvm/lib/Target/X86/X86ISelPattern.cpp diff -u llvm/lib/Target/X86/X86ISelPattern.cpp:1.159 llvm/lib/Target/X86/X86ISelPattern.cpp:1.160 --- llvm/lib/Target/X86/X86ISelPattern.cpp:1.159 Fri Jul 29 19:05:54 2005 +++ llvm/lib/Target/X86/X86ISelPattern.cpp Fri Jul 29 19:17:52 2005 @@ -4332,20 +4332,17 @@ addFrameReference(BuildMI(BB, X86::FNSTCW16m, 4), CWFrameIdx); // Load the old value of the high byte of the control word... - unsigned HighPartOfCW = MakeReg(MVT::i8); - addFrameReference(BuildMI(BB, X86::MOV8rm, 4, HighPartOfCW), - CWFrameIdx, 1); + unsigned OldCW = MakeReg(MVT::i16); + addFrameReference(BuildMI(BB, X86::MOV16rm, 4, OldCW), CWFrameIdx); // Set the high part to be round to zero... - addFrameReference(BuildMI(BB, X86::MOV8mi, 5), - CWFrameIdx, 1).addImm(12); + addFrameReference(BuildMI(BB, X86::MOV16mi, 5), CWFrameIdx).addImm(0xB7F); // Reload the modified control word now... addFrameReference(BuildMI(BB, X86::FLDCW16m, 4), CWFrameIdx); // Restore the memory image of control word to original value - addFrameReference(BuildMI(BB, X86::MOV8mr, 5), - CWFrameIdx, 1).addReg(HighPartOfCW); + addFrameReference(BuildMI(BB, X86::MOV16mr, 5), CWFrameIdx).addReg(OldCW); // Get the X86 opcode to use. switch (N.getOpcode()) { From natebegeman at mac.com Fri Jul 29 19:21:42 2005 From: natebegeman at mac.com (Nate Begeman) Date: Fri, 29 Jul 2005 19:21:42 -0500 Subject: [llvm-commits] CVS: llvm/lib/Transforms/Scalar/LoopStrengthReduce.cpp Message-ID: <200507300021.TAA06722@zion.cs.uiuc.edu> Changes in directory llvm/lib/Transforms/Scalar: LoopStrengthReduce.cpp updated: 1.14 -> 1.15 --- Log message: Ack, typo --- Diffs of the changes: (+1 -1) LoopStrengthReduce.cpp | 2 +- 1 files changed, 1 insertion(+), 1 deletion(-) Index: llvm/lib/Transforms/Scalar/LoopStrengthReduce.cpp diff -u llvm/lib/Transforms/Scalar/LoopStrengthReduce.cpp:1.14 llvm/lib/Transforms/Scalar/LoopStrengthReduce.cpp:1.15 --- llvm/lib/Transforms/Scalar/LoopStrengthReduce.cpp:1.14 Fri Jul 29 19:15:07 2005 +++ llvm/lib/Transforms/Scalar/LoopStrengthReduce.cpp Fri Jul 29 19:21:31 2005 @@ -331,7 +331,7 @@ /// reducible SCEV, recursively add its users to the IVUsesByStride set and /// return true. Otherwise, return false. bool LoopStrengthReduce::AddUsersIfInteresting(Instruction *I, Loop *L) { - if (I->getType() == Type::VoidTy) return false + if (I->getType() == Type::VoidTy) return false; SCEVHandle ISE = SE->getSCEV(I); if (!CanReduceSCEV(ISE, L)) return false; From lattner at cs.uiuc.edu Fri Jul 29 19:43:12 2005 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Fri, 29 Jul 2005 19:43:12 -0500 Subject: [llvm-commits] CVS: llvm/lib/Target/X86/X86ISelPattern.cpp Message-ID: <200507300043.TAA14162@zion.cs.uiuc.edu> Changes in directory llvm/lib/Target/X86: X86ISelPattern.cpp updated: 1.160 -> 1.161 --- Log message: fix a typeo --- Diffs of the changes: (+1 -1) X86ISelPattern.cpp | 2 +- 1 files changed, 1 insertion(+), 1 deletion(-) Index: llvm/lib/Target/X86/X86ISelPattern.cpp diff -u llvm/lib/Target/X86/X86ISelPattern.cpp:1.160 llvm/lib/Target/X86/X86ISelPattern.cpp:1.161 --- llvm/lib/Target/X86/X86ISelPattern.cpp:1.160 Fri Jul 29 19:17:52 2005 +++ llvm/lib/Target/X86/X86ISelPattern.cpp Fri Jul 29 19:43:00 2005 @@ -4336,7 +4336,7 @@ addFrameReference(BuildMI(BB, X86::MOV16rm, 4, OldCW), CWFrameIdx); // Set the high part to be round to zero... - addFrameReference(BuildMI(BB, X86::MOV16mi, 5), CWFrameIdx).addImm(0xB7F); + addFrameReference(BuildMI(BB, X86::MOV16mi, 5), CWFrameIdx).addImm(0xC7F); // Reload the modified control word now... addFrameReference(BuildMI(BB, X86::FLDCW16m, 4), CWFrameIdx); From lattner at cs.uiuc.edu Fri Jul 29 20:33:49 2005 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Fri, 29 Jul 2005 20:33:49 -0500 Subject: [llvm-commits] CVS: llvm/test/Regression/CodeGen/Generic/fp_to_int.ll Message-ID: <200507300133.UAA14416@zion.cs.uiuc.edu> Changes in directory llvm/test/Regression/CodeGen/Generic: fp_to_int.ll added (r1.1) --- Log message: this tests every fp-to-integer conversion --- Diffs of the changes: (+67 -0) fp_to_int.ll | 67 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ 1 files changed, 67 insertions(+) Index: llvm/test/Regression/CodeGen/Generic/fp_to_int.ll diff -c /dev/null llvm/test/Regression/CodeGen/Generic/fp_to_int.ll:1.1 *** /dev/null Fri Jul 29 20:33:48 2005 --- llvm/test/Regression/CodeGen/Generic/fp_to_int.ll Fri Jul 29 20:33:38 2005 *************** *** 0 **** --- 1,67 ---- + ; RUN: llvm-as < %s | llc + + sbyte %test1(double %X) { + %tmp.1 = cast double %X to sbyte + ret sbyte %tmp.1 + } + short %test2(double %X) { + %tmp.1 = cast double %X to short + ret short %tmp.1 + } + int %test3(double %X) { + %tmp.1 = cast double %X to int + ret int %tmp.1 + } + long %test4(double %X) { + %tmp.1 = cast double %X to long + ret long %tmp.1 + } + ubyte %test1u(double %X) { + %tmp.1 = cast double %X to ubyte + ret ubyte %tmp.1 + } + ushort %test2u(double %X) { + %tmp.1 = cast double %X to ushort + ret ushort %tmp.1 + } + uint %test3u(double %X) { + %tmp.1 = cast double %X to uint + ret uint %tmp.1 + } + ulong %test4u(double %X) { + %tmp.1 = cast double %X to ulong + ret ulong %tmp.1 + } + + sbyte %test1f(float %X) { + %tmp.1 = cast float %X to sbyte + ret sbyte %tmp.1 + } + short %test2f(float %X) { + %tmp.1 = cast float %X to short + ret short %tmp.1 + } + int %test3f(float %X) { + %tmp.1 = cast float %X to int + ret int %tmp.1 + } + long %test4f(float %X) { + %tmp.1 = cast float %X to long + ret long %tmp.1 + } + ubyte %test1uf(float %X) { + %tmp.1 = cast float %X to ubyte + ret ubyte %tmp.1 + } + ushort %test2uf(float %X) { + %tmp.1 = cast float %X to ushort + ret ushort %tmp.1 + } + uint %test3uf(float %X) { + %tmp.1 = cast float %X to uint + ret uint %tmp.1 + } + ulong %test4uf(float %X) { + %tmp.1 = cast float %X to ulong + ret ulong %tmp.1 + } From lattner at cs.uiuc.edu Fri Jul 29 20:41:08 2005 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Fri, 29 Jul 2005 20:41:08 -0500 Subject: [llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp Message-ID: <200507300141.UAA14489@zion.cs.uiuc.edu> Changes in directory llvm/lib/CodeGen/SelectionDAG: LegalizeDAG.cpp updated: 1.148 -> 1.149 --- Log message: fix float->long conversions on x86 --- Diffs of the changes: (+10 -3) LegalizeDAG.cpp | 13 ++++++++++--- 1 files changed, 10 insertions(+), 3 deletions(-) Index: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp diff -u llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.148 llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.149 --- llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.148 Fri Jul 29 19:04:12 2005 +++ llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp Fri Jul 29 20:40:57 2005 @@ -2779,11 +2779,18 @@ // library functions. case ISD::FP_TO_SINT: if (TLI.getOperationAction(ISD::FP_TO_SINT, VT) == TargetLowering::Custom) { - SDOperand Op = DAG.getNode(ISD::FP_TO_SINT, VT, - LegalizeOp(Node->getOperand(0))); + SDOperand Op; + switch (getTypeAction(Node->getOperand(0).getValueType())) { + case Expand: assert(0 && "cannot expand FP!"); + case Legal: Op = LegalizeOp(Node->getOperand(0)); break; + case Promote: Op = PromoteOp(Node->getOperand(0)); break; + } + + Op = TLI.LowerOperation(DAG.getNode(ISD::FP_TO_SINT, VT, Op), DAG); + // Now that the custom expander is done, expand the result, which is still // VT. - ExpandOp(TLI.LowerOperation(Op, DAG), Lo, Hi); + ExpandOp(Op, Lo, Hi); break; } From reid at x10sys.com Fri Jul 29 21:04:24 2005 From: reid at x10sys.com (Reid Spencer) Date: Fri, 29 Jul 2005 19:04:24 -0700 Subject: [llvm-commits] CVS: llvm/include/llvm/System/Memory.h In-Reply-To: <200507292338.SAA06170@zion.cs.uiuc.edu> References: <200507292338.SAA06170@zion.cs.uiuc.edu> Message-ID: <1122689064.1120.2.camel@bashful.x10sys.com> On Fri, 2005-07-29 at 18:38 -0500, Andrew Lenharth wrote: > > support near allocations for the JIT > /// This method allocates a block of Read/Write/Execute memory that is > /// suitable for executing dynamically generated code (e.g. JIT). An > /// attempt to allocate \p NumBytes bytes of virtual memory is made. > + /// \p NearBlock may point to an existing allocation in which case > + /// an attempt is made to allocate more memory near the existing block. > /// @throws std::string if an error occurred. > /// @brief Allocate Read/Write/Execute memory. > - static MemoryBlock AllocateRWX(unsigned NumBytes); > + static MemoryBlock AllocateRWX(unsigned NumBytes, const MemoryBlock* NearBlock); What if one does NOT want to allocate something near another block? Shouldn't the second argument be initialized to zero in order to retain the existing API? A zero value would indicate that the "NearBlock" constraint should be ignored and the function is permitted to allocate memory anywhere available. Furthermore, this needs to be "hint" as is done with the mmap(2) system call. Reid -------------- next part -------------- A non-text attachment was scrubbed... Name: not available Type: application/pgp-signature Size: 189 bytes Desc: This is a digitally signed message part Url : http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20050729/6d8a7af5/attachment.bin From jeffc at jolt-lang.org Sat Jul 30 13:22:39 2005 From: jeffc at jolt-lang.org (Jeff Cohen) Date: Sat, 30 Jul 2005 13:22:39 -0500 Subject: [llvm-commits] CVS: llvm/lib/Transforms/Scalar/LoopStrengthReduce.cpp Message-ID: <200507301822.NAA15241@zion.cs.uiuc.edu> Changes in directory llvm/lib/Transforms/Scalar: LoopStrengthReduce.cpp updated: 1.15 -> 1.16 --- Log message: Fix VC++ build problems. --- Diffs of the changes: (+1 -0) LoopStrengthReduce.cpp | 1 + 1 files changed, 1 insertion(+) Index: llvm/lib/Transforms/Scalar/LoopStrengthReduce.cpp diff -u llvm/lib/Transforms/Scalar/LoopStrengthReduce.cpp:1.15 llvm/lib/Transforms/Scalar/LoopStrengthReduce.cpp:1.16 --- llvm/lib/Transforms/Scalar/LoopStrengthReduce.cpp:1.15 Fri Jul 29 19:21:31 2005 +++ llvm/lib/Transforms/Scalar/LoopStrengthReduce.cpp Sat Jul 30 13:22:27 2005 @@ -29,6 +29,7 @@ #include "llvm/Target/TargetData.h" #include "llvm/ADT/Statistic.h" #include "llvm/Support/Debug.h" +#include #include using namespace llvm; From jeffc at jolt-lang.org Sat Jul 30 13:22:39 2005 From: jeffc at jolt-lang.org (Jeff Cohen) Date: Sat, 30 Jul 2005 13:22:39 -0500 Subject: [llvm-commits] CVS: llvm/win32/Analysis/Analysis.vcproj Message-ID: <200507301822.NAA15245@zion.cs.uiuc.edu> Changes in directory llvm/win32/Analysis: Analysis.vcproj updated: 1.11 -> 1.12 --- Log message: Fix VC++ build problems. --- Diffs of the changes: (+6 -0) Analysis.vcproj | 6 ++++++ 1 files changed, 6 insertions(+) Index: llvm/win32/Analysis/Analysis.vcproj diff -u llvm/win32/Analysis/Analysis.vcproj:1.11 llvm/win32/Analysis/Analysis.vcproj:1.12 --- llvm/win32/Analysis/Analysis.vcproj:1.11 Tue Mar 15 00:31:46 2005 +++ llvm/win32/Analysis/Analysis.vcproj Sat Jul 30 13:22:27 2005 @@ -158,6 +158,9 @@ RelativePath="..\..\lib\Analysis\ScalarEvolution.cpp"> + + + + Changes in directory llvm/tools/llc: llc.cpp updated: 1.110 -> 1.111 --- Log message: Keep tabs and trailing spaces out. --- Diffs of the changes: (+1 -1) llc.cpp | 2 +- 1 files changed, 1 insertion(+), 1 deletion(-) Index: llvm/tools/llc/llc.cpp diff -u llvm/tools/llc/llc.cpp:1.110 llvm/tools/llc/llc.cpp:1.111 --- llvm/tools/llc/llc.cpp:1.110 Wed Jul 27 23:00:49 2005 +++ llvm/tools/llc/llc.cpp Sat Jul 30 13:33:25 2005 @@ -65,7 +65,7 @@ LLCPassList(cl::desc("Passes Available")); cl::opt NoVerify("disable-verify", cl::Hidden, - cl::desc("Do not verify input module")); + cl::desc("Do not verify input module")); // GetFileNameRoot - Helper function to get the basename of a filename. From jeffc at jolt-lang.org Sat Jul 30 13:33:38 2005 From: jeffc at jolt-lang.org (Jeff Cohen) Date: Sat, 30 Jul 2005 13:33:38 -0500 Subject: [llvm-commits] CVS: llvm/lib/ExecutionEngine/JIT/JITEmitter.cpp Message-ID: <200507301833.NAA15350@zion.cs.uiuc.edu> Changes in directory llvm/lib/ExecutionEngine/JIT: JITEmitter.cpp updated: 1.74 -> 1.75 --- Log message: Keep tabs and trailing spaces out. --- Diffs of the changes: (+4 -4) JITEmitter.cpp | 8 ++++---- 1 files changed, 4 insertions(+), 4 deletions(-) Index: llvm/lib/ExecutionEngine/JIT/JITEmitter.cpp diff -u llvm/lib/ExecutionEngine/JIT/JITEmitter.cpp:1.74 llvm/lib/ExecutionEngine/JIT/JITEmitter.cpp:1.75 --- llvm/lib/ExecutionEngine/JIT/JITEmitter.cpp:1.74 Fri Jul 29 18:40:16 2005 +++ llvm/lib/ExecutionEngine/JIT/JITEmitter.cpp Sat Jul 30 13:33:25 2005 @@ -65,7 +65,7 @@ inline unsigned char *allocateStub(unsigned StubSize); inline unsigned char *allocateConstant(unsigned ConstantSize, unsigned Alignment); - inline unsigned char* allocateGlobal(unsigned Size, + inline unsigned char* allocateGlobal(unsigned Size, unsigned Alignment); inline unsigned char *startFunctionBody(); inline void endFunctionBody(unsigned char *FunctionEnd); @@ -373,8 +373,8 @@ // FIXME: We could rewrite all references to this stub if we knew them. - // What we will do is set the compiled function address to map to the - // same GOT entry as the stub so that later clients may update the GOT + // What we will do is set the compiled function address to map to the + // same GOT entry as the stub so that later clients may update the GOT // if they see it still using the stub address. // Note: this is done so the Resolver doesn't have to manage GOT memory // Do this without allocating map space if the target isn't using a GOT @@ -548,7 +548,7 @@ if(MemMgr.isManagingGOT()) { unsigned idx = getJITResolver(this).getGOTIndexForAddr((void*)CurBlock); if (((void**)MemMgr.getGOTBase())[idx] != (void*)CurBlock) { - DEBUG(std::cerr << "GOT was out of date for " << (void*)CurBlock + DEBUG(std::cerr << "GOT was out of date for " << (void*)CurBlock << " pointing at " << ((void**)MemMgr.getGOTBase())[idx] << "\n"); ((void**)MemMgr.getGOTBase())[idx] = (void*)CurBlock; } From jeffc at jolt-lang.org Sat Jul 30 13:33:39 2005 From: jeffc at jolt-lang.org (Jeff Cohen) Date: Sat, 30 Jul 2005 13:33:39 -0500 Subject: [llvm-commits] CVS: llvm/lib/Target/PowerPC/PPC32RegisterInfo.cpp Message-ID: <200507301833.NAA15358@zion.cs.uiuc.edu> Changes in directory llvm/lib/Target/PowerPC: PPC32RegisterInfo.cpp updated: 1.14 -> 1.15 --- Log message: Keep tabs and trailing spaces out. --- Diffs of the changes: (+1 -1) PPC32RegisterInfo.cpp | 2 +- 1 files changed, 1 insertion(+), 1 deletion(-) Index: llvm/lib/Target/PowerPC/PPC32RegisterInfo.cpp diff -u llvm/lib/Target/PowerPC/PPC32RegisterInfo.cpp:1.14 llvm/lib/Target/PowerPC/PPC32RegisterInfo.cpp:1.15 --- llvm/lib/Target/PowerPC/PPC32RegisterInfo.cpp:1.14 Wed Jul 27 18:11:27 2005 +++ llvm/lib/Target/PowerPC/PPC32RegisterInfo.cpp Sat Jul 30 13:33:25 2005 @@ -245,7 +245,7 @@ NumBytes += MFI->getMaxCallFrameSize(); } - // If we are a leaf function, and use up to 224 bytes of stack space, + // If we are a leaf function, and use up to 224 bytes of stack space, // and don't have a frame pointer, then we do not need to adjust the stack // pointer (we fit in the Red Zone). if ((NumBytes == 0) || (NumBytes <= 224 && !hasFP(MF) && !MFI->hasCalls())) { From jeffc at jolt-lang.org Sat Jul 30 13:33:39 2005 From: jeffc at jolt-lang.org (Jeff Cohen) Date: Sat, 30 Jul 2005 13:33:39 -0500 Subject: [llvm-commits] CVS: llvm/lib/Transforms/Scalar/LoopStrengthReduce.cpp Message-ID: <200507301833.NAA15362@zion.cs.uiuc.edu> Changes in directory llvm/lib/Transforms/Scalar: LoopStrengthReduce.cpp updated: 1.16 -> 1.17 --- Log message: Keep tabs and trailing spaces out. --- Diffs of the changes: (+23 -23) LoopStrengthReduce.cpp | 46 +++++++++++++++++++++++----------------------- 1 files changed, 23 insertions(+), 23 deletions(-) Index: llvm/lib/Transforms/Scalar/LoopStrengthReduce.cpp diff -u llvm/lib/Transforms/Scalar/LoopStrengthReduce.cpp:1.16 llvm/lib/Transforms/Scalar/LoopStrengthReduce.cpp:1.17 --- llvm/lib/Transforms/Scalar/LoopStrengthReduce.cpp:1.16 Sat Jul 30 13:22:27 2005 +++ llvm/lib/Transforms/Scalar/LoopStrengthReduce.cpp Sat Jul 30 13:33:25 2005 @@ -172,7 +172,7 @@ if (SCEVUnknown *SU = dyn_cast(AddRec->getOperand(1))) if (SU->getValue()->getType()->isUnsigned()) return true; - + // Otherwise, no, we can't handle it yet. return false; } @@ -192,7 +192,7 @@ // This index is scaled by the type size being indexed. if (TySize != 1) - Result = SCEVMulExpr::get(Result, + Result = SCEVMulExpr::get(Result, SCEVConstant::get(ConstantUInt::get(UIntPtrTy, TySize))); return Result; @@ -216,7 +216,7 @@ Value *BasePtr; if (Constant *CB = dyn_cast(GEP->getOperand(0))) BasePtr = ConstantExpr::getCast(CB, UIntPtrTy); - else { + else { Value *&BP = CastedBasePointers[GEP->getOperand(0)]; if (BP == 0) { BasicBlock::iterator InsertPt; @@ -321,7 +321,7 @@ DEBUG(std::cerr << "FOUND USER: " << *User << " OF STRIDE: " << *Step << " BASE = " << *Base << "\n"); - + // Okay, we found a user that we cannot reduce. Analyze the instruction // and decide what to do with it. IVUsesByStride[Step].addUser(Base, User, GEP); @@ -351,7 +351,7 @@ assert(Step->getType()->isUnsigned() && "Bad step value!"); std::set AnalyzedGEPs; - + for (Value::use_iterator UI = I->use_begin(), E = I->use_end(); UI != E;++UI){ Instruction *User = cast(*UI); @@ -364,12 +364,12 @@ if (LI->getLoopFor(User->getParent()) != L) continue; - // Next, see if this user is analyzable itself! + // Next, see if this user is analyzable itself! if (!AddUsersIfInteresting(User, L)) { if (GetElementPtrInst *GEP = dyn_cast(User)) { // If this is a getelementptr instruction, figure out what linear // expression of induction variable is actually being used. - // + // if (AnalyzedGEPs.insert(GEP).second) // Not already analyzed? AnalyzeGetElementPtrUsers(GEP, I, L); } else { @@ -426,12 +426,12 @@ /// isTargetConstant - Return true if the following can be referenced by the /// immediate field of a target instruction. static bool isTargetConstant(const SCEVHandle &V) { - + // FIXME: Look at the target to decide if &GV is a legal constant immediate. if (isa(V)) return true; - + return false; // ENABLE this for x86 - + if (SCEVUnknown *SU = dyn_cast(V)) if (ConstantExpr *CE = dyn_cast(SU->getValue())) if (CE->getOpcode() == Instruction::Cast) @@ -455,7 +455,7 @@ for (; i != SAE->getNumOperands(); ++i) if (isTargetConstant(SAE->getOperand(i))) { SCEVHandle ImmVal = SAE->getOperand(i); - + // If there are any other immediates that we can handle here, pull them // out too. for (++i; i != SAE->getNumOperands(); ++i) @@ -481,8 +481,8 @@ // eventually emit the object. std::vector > UsersToProcess; UsersToProcess.reserve(Uses.Users.size()); - - SCEVHandle ZeroBase = SCEVUnknown::getIntegerSCEV(0, + + SCEVHandle ZeroBase = SCEVUnknown::getIntegerSCEV(0, Uses.Users[0].first->getType()); for (unsigned i = 0, e = Uses.Users.size(); i != e; ++i) @@ -497,7 +497,7 @@ for (unsigned i = 0, e = UsersToProcess.size(); i != e; ++i) { bool isAddress = isa(UsersToProcess[i].second.Inst) || isa(UsersToProcess[i].second.Inst); - UsersToProcess[i].second.Imm = GetImmediateValues(UsersToProcess[i].first, + UsersToProcess[i].second.Imm = GetImmediateValues(UsersToProcess[i].first, isAddress); UsersToProcess[i].first = SCEV::getMinusSCEV(UsersToProcess[i].first, UsersToProcess[i].second.Imm); @@ -511,14 +511,14 @@ Instruction *PreInsertPt = Preheader->getTerminator(); Instruction *PhiInsertBefore = L->getHeader()->begin(); - assert(isa(PhiInsertBefore) && + assert(isa(PhiInsertBefore) && "How could this loop have IV's without any phis?"); PHINode *SomeLoopPHI = cast(PhiInsertBefore); assert(SomeLoopPHI->getNumIncomingValues() == 2 && "This loop isn't canonicalized right"); BasicBlock *LatchBlock = SomeLoopPHI->getIncomingBlock(SomeLoopPHI->getIncomingBlock(0) == Preheader); - + // FIXME: This loop needs increasing levels of intelligence. // STAGE 0: just emit everything as its own base. <-- We are here // STAGE 1: factor out common vars from bases, and try and push resulting @@ -534,7 +534,7 @@ PHINode *NewPHI = new PHINode(ReplacedTy, Replaced->getName()+".str", PhiInsertBefore); - // Emit the initial base value into the loop preheader, and add it to the + // Emit the initial base value into the loop preheader, and add it to the // Phi node. Value *BaseV = Rewriter.expandCodeFor(UsersToProcess.front().first, PreInsertPt, ReplacedTy); @@ -552,7 +552,7 @@ // Emit the code to add the immediate offset to the Phi value, just before // the instruction that we identified as using this stride and base. - // First, empty the SCEVExpander's expression map so that we are guaranteed + // First, empty the SCEVExpander's expression map so that we are guaranteed // to have the code emitted where we expect it. Rewriter.clear(); SCEVHandle NewValSCEV = SCEVAddExpr::get(SCEVUnknown::get(NewPHI), @@ -560,16 +560,16 @@ Value *newVal = Rewriter.expandCodeFor(NewValSCEV, UsersToProcess.front().second.Inst, ReplacedTy); - + // Replace the use of the operand Value with the new Phi we just created. - DEBUG(std::cerr << "REPLACING: " << *Replaced << "IN: " << + DEBUG(std::cerr << "REPLACING: " << *Replaced << "IN: " << *UsersToProcess.front().second.Inst << "WITH: "<< *newVal << '\n'); UsersToProcess.front().second.Inst->replaceUsesOfWith(Replaced, newVal); - + // Mark old value we replaced as possibly dead, so that it is elminated // if we just replaced the last use of that value. DeadInsts.insert(cast(Replaced)); - + UsersToProcess.erase(UsersToProcess.begin()); ++NumReduced; @@ -578,7 +578,7 @@ // IMPORTANT TODO: Figure out how to partition the IV's with this stride, but // different starting values, into different PHIs. - + // BEFORE writing this, it's probably useful to handle GEP's. // NOTE: pull all constants together, for REG+IMM addressing, include &GV in From jeffc at jolt-lang.org Sat Jul 30 13:33:39 2005 From: jeffc at jolt-lang.org (Jeff Cohen) Date: Sat, 30 Jul 2005 13:33:39 -0500 Subject: [llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp Message-ID: <200507301833.NAA15366@zion.cs.uiuc.edu> Changes in directory llvm/lib/CodeGen/SelectionDAG: LegalizeDAG.cpp updated: 1.149 -> 1.150 --- Log message: Keep tabs and trailing spaces out. --- Diffs of the changes: (+15 -14) LegalizeDAG.cpp | 29 +++++++++++++++-------------- 1 files changed, 15 insertions(+), 14 deletions(-) Index: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp diff -u llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.149 llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.150 --- llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.149 Fri Jul 29 20:40:57 2005 +++ llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp Sat Jul 30 13:33:25 2005 @@ -271,14 +271,14 @@ bool isSigned) { // First step, figure out the appropriate FP_TO*INT operation to use. MVT::ValueType NewOutTy = DestVT; - + unsigned OpToUse = 0; - + // Scan for the appropriate larger type to use. while (1) { NewOutTy = (MVT::ValueType)(NewOutTy+1); assert(MVT::isInteger(NewOutTy) && "Ran out of possibilities!"); - + // If the target supports FP_TO_SINT returning this type, use it. switch (TLI.getOperationAction(ISD::FP_TO_SINT, NewOutTy)) { default: break; @@ -291,7 +291,7 @@ break; } if (OpToUse) break; - + // If the target supports FP_TO_UINT of this type, use it. switch (TLI.getOperationAction(ISD::FP_TO_UINT, NewOutTy)) { default: break; @@ -304,13 +304,13 @@ break; } if (OpToUse) break; - + // Otherwise, try a larger type. } - + // Make sure to legalize any nodes we create here in the next pass. NeedsAnotherIteration = true; - + // Okay, we found the operation and type to use. Truncate the result of the // extended FP_TO_*INT operation to the desired size. return DAG.getNode(ISD::TRUNCATE, DestVT, @@ -1502,7 +1502,7 @@ bool isSigned = Node->getOpcode() == ISD::SINT_TO_FP; switch (getTypeAction(Node->getOperand(0).getValueType())) { case Legal: - switch (TLI.getOperationAction(Node->getOpcode(), + switch (TLI.getOperationAction(Node->getOpcode(), Node->getOperand(0).getValueType())) { default: assert(0 && "Unknown operation action!"); case TargetLowering::Expand: @@ -1565,7 +1565,7 @@ break; } break; - + case ISD::FP_TO_SINT: case ISD::FP_TO_UINT: switch (getTypeAction(Node->getOperand(0).getValueType())) { @@ -1590,7 +1590,7 @@ NeedsAnotherIteration = true; return Result; } - + if (Tmp1 != Node->getOperand(0)) Result = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1); break; @@ -1602,7 +1602,7 @@ break; } break; - + case ISD::ZERO_EXTEND: case ISD::SIGN_EXTEND: case ISD::FP_EXTEND: @@ -2785,7 +2785,7 @@ case Legal: Op = LegalizeOp(Node->getOperand(0)); break; case Promote: Op = PromoteOp(Node->getOperand(0)); break; } - + Op = TLI.LowerOperation(DAG.getNode(ISD::FP_TO_SINT, VT, Op), DAG); // Now that the custom expander is done, expand the result, which is still @@ -2793,12 +2793,13 @@ ExpandOp(Op, Lo, Hi); break; } - + if (Node->getOperand(0).getValueType() == MVT::f32) Lo = ExpandLibCall("__fixsfdi", Node, Hi); else Lo = ExpandLibCall("__fixdfdi", Node, Hi); break; + case ISD::FP_TO_UINT: if (TLI.getOperationAction(ISD::FP_TO_UINT, VT) == TargetLowering::Custom) { SDOperand Op = DAG.getNode(ISD::FP_TO_UINT, VT, @@ -2808,7 +2809,7 @@ ExpandOp(TLI.LowerOperation(Op, DAG), Lo, Hi); break; } - + if (Node->getOperand(0).getValueType() == MVT::f32) Lo = ExpandLibCall("__fixunssfdi", Node, Hi); else From jeffc at jolt-lang.org Sat Jul 30 13:33:39 2005 From: jeffc at jolt-lang.org (Jeff Cohen) Date: Sat, 30 Jul 2005 13:33:39 -0500 Subject: [llvm-commits] CVS: llvm/lib/Target/Alpha/AlphaJITInfo.cpp Message-ID: <200507301833.NAA15371@zion.cs.uiuc.edu> Changes in directory llvm/lib/Target/Alpha: AlphaJITInfo.cpp updated: 1.5 -> 1.6 --- Log message: Keep tabs and trailing spaces out. --- Diffs of the changes: (+2 -2) AlphaJITInfo.cpp | 4 ++-- 1 files changed, 2 insertions(+), 2 deletions(-) Index: llvm/lib/Target/Alpha/AlphaJITInfo.cpp diff -u llvm/lib/Target/Alpha/AlphaJITInfo.cpp:1.5 llvm/lib/Target/Alpha/AlphaJITInfo.cpp:1.6 --- llvm/lib/Target/Alpha/AlphaJITInfo.cpp:1.5 Thu Jul 28 13:14:47 2005 +++ llvm/lib/Target/Alpha/AlphaJITInfo.cpp Sat Jul 30 13:33:25 2005 @@ -92,7 +92,7 @@ EmitBranchToAt(CameFromStub, Target); } else { DEBUG(std::cerr << "confused, didn't come from stub at " << CameFromStub - << " old jump vector " << oldpv + << " old jump vector " << oldpv << " new jump vector " << Target << "\n"); } @@ -291,7 +291,7 @@ } break; case Alpha::reloc_bsr: { - idx = (((unsigned char*)MR->getResultPointer() - + idx = (((unsigned char*)MR->getResultPointer() - (unsigned char*)RelocPos) >> 2) + 1; //skip first 2 inst of fun *RelocPos |= (idx & ((1 << 21)-1)); doCommon = false; From jeffc at jolt-lang.org Sat Jul 30 13:33:39 2005 From: jeffc at jolt-lang.org (Jeff Cohen) Date: Sat, 30 Jul 2005 13:33:39 -0500 Subject: [llvm-commits] CVS: llvm/include/llvm/Analysis/ScalarEvolutionExpander.h Message-ID: <200507301833.NAA15372@zion.cs.uiuc.edu> Changes in directory llvm/include/llvm/Analysis: ScalarEvolutionExpander.h updated: 1.1 -> 1.2 --- Log message: Keep tabs and trailing spaces out. --- Diffs of the changes: (+2 -2) ScalarEvolutionExpander.h | 4 ++-- 1 files changed, 2 insertions(+), 2 deletions(-) Index: llvm/include/llvm/Analysis/ScalarEvolutionExpander.h diff -u llvm/include/llvm/Analysis/ScalarEvolutionExpander.h:1.1 llvm/include/llvm/Analysis/ScalarEvolutionExpander.h:1.2 --- llvm/include/llvm/Analysis/ScalarEvolutionExpander.h:1.1 Fri Jul 29 19:12:19 2005 +++ llvm/include/llvm/Analysis/ScalarEvolutionExpander.h Sat Jul 30 13:33:25 2005 @@ -42,10 +42,10 @@ SCEVExpander(ScalarEvolution &se, LoopInfo &li) : SE(se), LI(li) {} /// clear - Erase the contents of the InsertedExpressions map so that users - /// trying to expand the same expression into multiple BasicBlocks or + /// trying to expand the same expression into multiple BasicBlocks or /// different places within the same BasicBlock can do so. void clear() { InsertedExpressions.clear(); } - + /// isInsertedInstruction - Return true if the specified instruction was /// inserted by the code rewriter. If so, the client should not modify the /// instruction. From jeffc at jolt-lang.org Sat Jul 30 13:33:39 2005 From: jeffc at jolt-lang.org (Jeff Cohen) Date: Sat, 30 Jul 2005 13:33:39 -0500 Subject: [llvm-commits] CVS: llvm/lib/Target/X86/X86ISelPattern.cpp Message-ID: <200507301833.NAA15378@zion.cs.uiuc.edu> Changes in directory llvm/lib/Target/X86: X86ISelPattern.cpp updated: 1.161 -> 1.162 --- Log message: Keep tabs and trailing spaces out. --- Diffs of the changes: (+14 -14) X86ISelPattern.cpp | 28 ++++++++++++++-------------- 1 files changed, 14 insertions(+), 14 deletions(-) Index: llvm/lib/Target/X86/X86ISelPattern.cpp diff -u llvm/lib/Target/X86/X86ISelPattern.cpp:1.161 llvm/lib/Target/X86/X86ISelPattern.cpp:1.162 --- llvm/lib/Target/X86/X86ISelPattern.cpp:1.161 Fri Jul 29 19:43:00 2005 +++ llvm/lib/Target/X86/X86ISelPattern.cpp Sat Jul 30 13:33:25 2005 @@ -62,7 +62,7 @@ FP_TO_INT16_IN_MEM, FP_TO_INT32_IN_MEM, FP_TO_INT64_IN_MEM, - + /// CALL/TAILCALL - These operations represent an abstract X86 call /// instruction, which includes a bunch of information. In particular the /// operands of these node are: @@ -135,7 +135,7 @@ setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom); setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Custom); } - + // Handle FP_TO_UINT by promoting the destination to a larger signed // conversion. setOperationAction(ISD::FP_TO_UINT , MVT::i1 , Promote); @@ -147,7 +147,7 @@ // this operation. setOperationAction(ISD::FP_TO_SINT , MVT::i1 , Promote); setOperationAction(ISD::FP_TO_SINT , MVT::i8 , Promote); - + setOperationAction(ISD::BRCONDTWOWAY , MVT::Other, Expand); setOperationAction(ISD::MEMMOVE , MVT::Other, Expand); setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16 , Expand); @@ -1008,14 +1008,14 @@ case MVT::i32: Opc = X86ISD::FP_TO_INT32_IN_MEM; break; case MVT::i64: Opc = X86ISD::FP_TO_INT64_IN_MEM; break; } - + // Build the FP_TO_INT*_IN_MEM std::vector Ops; Ops.push_back(DAG.getEntryNode()); Ops.push_back(Op.getOperand(0)); Ops.push_back(StackSlot); SDOperand FIST = DAG.getNode(Opc, MVT::Other, Ops); - + // Load the result. return DAG.getLoad(Op.getValueType(), FIST, StackSlot, DAG.getSrcValue(NULL)); @@ -3308,7 +3308,7 @@ addFullAddress(BuildMI(BB, X86::FILD64m, 4, Result), AM); } return Result; - + case ISD::EXTLOAD: // Arbitrarily codegen extloads as MOVZX* case ISD::ZEXTLOAD: { // Make sure we generate both values. @@ -4307,7 +4307,7 @@ ExprMap.erase(N); SelectExpr(N.getValue(0)); return; - + case X86ISD::FP_TO_INT16_IN_MEM: case X86ISD::FP_TO_INT32_IN_MEM: case X86ISD::FP_TO_INT64_IN_MEM: { @@ -4323,24 +4323,24 @@ SelectAddress(N.getOperand(2), AM); ValReg = SelectExpr(N.getOperand(1)); } - + // Change the floating point control register to use "round towards zero" // mode when truncating to an integer value. // MachineFunction *F = BB->getParent(); int CWFrameIdx = F->getFrameInfo()->CreateStackObject(2, 2); addFrameReference(BuildMI(BB, X86::FNSTCW16m, 4), CWFrameIdx); - + // Load the old value of the high byte of the control word... unsigned OldCW = MakeReg(MVT::i16); addFrameReference(BuildMI(BB, X86::MOV16rm, 4, OldCW), CWFrameIdx); - + // Set the high part to be round to zero... addFrameReference(BuildMI(BB, X86::MOV16mi, 5), CWFrameIdx).addImm(0xC7F); - + // Reload the modified control word now... addFrameReference(BuildMI(BB, X86::FLDCW16m, 4), CWFrameIdx); - + // Restore the memory image of control word to original value addFrameReference(BuildMI(BB, X86::MOV16mr, 5), CWFrameIdx).addReg(OldCW); @@ -4350,9 +4350,9 @@ case X86ISD::FP_TO_INT32_IN_MEM: Tmp1 = X86::FIST32m; break; case X86ISD::FP_TO_INT64_IN_MEM: Tmp1 = X86::FISTP64m; break; } - + addFullAddress(BuildMI(BB, Tmp1, 5), AM).addReg(ValReg); - + // Reload the original control word now. addFrameReference(BuildMI(BB, X86::FLDCW16m, 4), CWFrameIdx); return; From sabre at nondot.org Sun Jul 31 19:47:29 2005 From: sabre at nondot.org (Chris Lattner) Date: Sun, 31 Jul 2005 19:47:29 -0500 (CDT) Subject: [llvm-commits] CVS: llvm/tools/llc/llc.cpp In-Reply-To: <200507301833.NAA15354@zion.cs.uiuc.edu> References: <200507301833.NAA15354@zion.cs.uiuc.edu> Message-ID: > Keep tabs and trailing spaces out. Hey Jeff, While I appreciate the work, I would really rather that you didn't do this sort of patch. This makes 'cvs annotate' completely useless, which is really annoying. :( -Chris > > llc.cpp | 2 +- > 1 files changed, 1 insertion(+), 1 deletion(-) > > > Index: llvm/tools/llc/llc.cpp > diff -u llvm/tools/llc/llc.cpp:1.110 llvm/tools/llc/llc.cpp:1.111 > --- llvm/tools/llc/llc.cpp:1.110 Wed Jul 27 23:00:49 2005 > +++ llvm/tools/llc/llc.cpp Sat Jul 30 13:33:25 2005 > @@ -65,7 +65,7 @@ > LLCPassList(cl::desc("Passes Available")); > > cl::opt NoVerify("disable-verify", cl::Hidden, > - cl::desc("Do not verify input module")); > + cl::desc("Do not verify input module")); > > > // GetFileNameRoot - Helper function to get the basename of a filename. > > > > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits > -Chris -- http://nondot.org/sabre/ http://llvm.org/ From natebegeman at mac.com Fri Jul 29 19:15:18 2005 From: natebegeman at mac.com (Nate Begeman) Date: Fri, 29 Jul 2005 19:15:18 -0500 Subject: [llvm-commits] CVS: llvm/lib/Transforms/Scalar/LoopStrengthReduce.cpp Message-ID: <200507300015.TAA06635@zion.cs.uiuc.edu> Changes in directory llvm/lib/Transforms/Scalar: LoopStrengthReduce.cpp updated: 1.13 -> 1.14 --- Log message: Commit a new LoopStrengthReduce pass that can use scalar evolutions and target data to decide which loop induction variables to strength reduce and how to do so. This work is mostly by Chris Lattner, with tweaks by me to get it working on some of MultiSource. --- Diffs of the changes: (+518 -180) LoopStrengthReduce.cpp | 698 ++++++++++++++++++++++++++++++++++++------------- 1 files changed, 518 insertions(+), 180 deletions(-) Index: llvm/lib/Transforms/Scalar/LoopStrengthReduce.cpp diff -u llvm/lib/Transforms/Scalar/LoopStrengthReduce.cpp:1.13 llvm/lib/Transforms/Scalar/LoopStrengthReduce.cpp:1.14 --- llvm/lib/Transforms/Scalar/LoopStrengthReduce.cpp:1.13 Thu Apr 21 18:45:12 2005 +++ llvm/lib/Transforms/Scalar/LoopStrengthReduce.cpp Fri Jul 29 19:15:07 2005 @@ -13,9 +13,6 @@ // access for the first iteration, and then creating a new GEP instruction in // the loop to increment the value by the appropriate amount. // -// There are currently several deficiencies in the implementation, marked with -// FIXME in the code. -// //===----------------------------------------------------------------------===// #include "llvm/Transforms/Scalar.h" @@ -25,10 +22,13 @@ #include "llvm/DerivedTypes.h" #include "llvm/Analysis/Dominators.h" #include "llvm/Analysis/LoopInfo.h" +#include "llvm/Analysis/ScalarEvolutionExpander.h" #include "llvm/Support/CFG.h" +#include "llvm/Support/GetElementPtrTypeIterator.h" #include "llvm/Transforms/Utils/Local.h" #include "llvm/Target/TargetData.h" #include "llvm/ADT/Statistic.h" +#include "llvm/Support/Debug.h" #include using namespace llvm; @@ -50,11 +50,40 @@ std::map Map; }; + struct IVUse { + /// Users - Keep track of all of the users of this stride as well as the + /// initial value. + std::vector > Users; + std::vector UserOperands; + + void addUser(SCEVHandle &SH, Instruction *U, Instruction *V) { + Users.push_back(std::make_pair(SH, U)); + UserOperands.push_back(V); + } + }; + + class LoopStrengthReduce : public FunctionPass { LoopInfo *LI; DominatorSet *DS; + ScalarEvolution *SE; + const TargetData *TD; + const Type *UIntPtrTy; bool Changed; unsigned MaxTargetAMSize; + + /// IVUsesByStride - Keep track of all uses of induction variables that we + /// are interested in. The key of the map is the stride of the access. + std::map IVUsesByStride; + + /// CastedBasePointers - As we need to lower getelementptr instructions, we + /// cast the pointer input to uintptr_t. This keeps track of the casted + /// values for the pointers we have processed so far. + std::map CastedBasePointers; + + /// DeadInsts - Keep track of instructions we may have made dead, so that + /// we can remove them after we are done working. + std::set DeadInsts; public: LoopStrengthReduce(unsigned MTAMS = 1) : MaxTargetAMSize(MTAMS) { @@ -63,6 +92,9 @@ virtual bool runOnFunction(Function &) { LI = &getAnalysis(); DS = &getAnalysis(); + SE = &getAnalysis(); + TD = &getAnalysis(); + UIntPtrTy = TD->getIntPtrType(); Changed = false; for (LoopInfo::iterator I = LI->begin(), E = LI->end(); I != E; ++I) @@ -76,9 +108,17 @@ AU.addRequired(); AU.addRequired(); AU.addRequired(); + AU.addRequired(); } private: void runOnLoop(Loop *L); + bool AddUsersIfInteresting(Instruction *I, Loop *L); + void AnalyzeGetElementPtrUsers(GetElementPtrInst *GEP, Instruction *I, + Loop *L); + + void StrengthReduceStridedIVUsers(Value *Stride, IVUse &Uses, Loop *L, + bool isOnlyStride); + void strengthReduceGEP(GetElementPtrInst *GEPI, Loop *L, GEPCache* GEPCache, Instruction *InsertBefore, @@ -111,207 +151,505 @@ } } -void LoopStrengthReduce::strengthReduceGEP(GetElementPtrInst *GEPI, Loop *L, - GEPCache *Cache, - Instruction *InsertBefore, - std::set &DeadInsts) { - // We will strength reduce the GEP by splitting it into two parts. The first - // is a GEP to hold the initial value of the non-strength-reduced GEP upon - // entering the loop, which we will insert at the end of the loop preheader. - // The second is a GEP to hold the incremented value of the initial GEP. - // The LoopIndVarSimplify pass guarantees that loop counts start at zero, so - // we will replace the indvar with a constant zero value to create the first - // GEP. - // - // We currently only handle GEP instructions that consist of zero or more - // constants or loop invariable expressions prior to an instance of the - // canonical induction variable. - unsigned indvar = 0; - std::vector pre_op_vector; - std::vector inc_op_vector; - const Type *ty = GEPI->getOperand(0)->getType(); - Value *CanonicalIndVar = L->getCanonicalInductionVariable(); - BasicBlock *Header = L->getHeader(); - BasicBlock *Preheader = L->getLoopPreheader(); - bool AllConstantOperands = true; - Cache = Cache->get(GEPI->getOperand(0)); - - for (unsigned op = 1, e = GEPI->getNumOperands(); op != e; ++op) { - Value *operand = GEPI->getOperand(op); - if (ty->getTypeID() == Type::StructTyID) { - assert(isa(operand)); - ConstantUInt *c = dyn_cast(operand); - ty = ty->getContainedType(unsigned(c->getValue())); - } else { - ty = ty->getContainedType(0); + +/// CanReduceSCEV - Return true if we can strength reduce this scalar evolution +/// in the specified loop. +static bool CanReduceSCEV(const SCEVHandle &SH, Loop *L) { + SCEVAddRecExpr *AddRec = dyn_cast(SH); + if (!AddRec || AddRec->getLoop() != L) return false; + + // FIXME: Generalize to non-affine IV's. + if (!AddRec->isAffine()) return false; + + // FIXME: generalize to IV's with more complex strides (must emit stride + // expression outside of loop!) + if (isa(AddRec->getOperand(1))) + return true; + + // We handle steps by unsigned values, because we know we won't have to insert + // a cast for them. + if (SCEVUnknown *SU = dyn_cast(AddRec->getOperand(1))) + if (SU->getValue()->getType()->isUnsigned()) + return true; + + // Otherwise, no, we can't handle it yet. + return false; +} + + +/// GetAdjustedIndex - Adjust the specified GEP sequential type index to match +/// the size of the pointer type, and scale it by the type size. +static SCEVHandle GetAdjustedIndex(const SCEVHandle &Idx, uint64_t TySize, + const Type *UIntPtrTy) { + SCEVHandle Result = Idx; + if (Result->getType()->getUnsignedVersion() != UIntPtrTy) { + if (UIntPtrTy->getPrimitiveSize() < Result->getType()->getPrimitiveSize()) + Result = SCEVTruncateExpr::get(Result, UIntPtrTy); + else + Result = SCEVZeroExtendExpr::get(Result, UIntPtrTy); + } + + // This index is scaled by the type size being indexed. + if (TySize != 1) + Result = SCEVMulExpr::get(Result, + SCEVConstant::get(ConstantUInt::get(UIntPtrTy, + TySize))); + return Result; +} + +/// AnalyzeGetElementPtrUsers - Analyze all of the users of the specified +/// getelementptr instruction, adding them to the IVUsesByStride table. Note +/// that we only want to analyze a getelementptr instruction once, and it can +/// have multiple operands that are uses of the indvar (e.g. A[i][i]). Because +/// of this, we only process a GEP instruction if its first recurrent operand is +/// "op", otherwise we will either have already processed it or we will sometime +/// later. +void LoopStrengthReduce::AnalyzeGetElementPtrUsers(GetElementPtrInst *GEP, + Instruction *Op, Loop *L) { + // Analyze all of the subscripts of this getelementptr instruction, looking + // for uses that are determined by the trip count of L. First, skip all + // operands the are not dependent on the IV. + + // Build up the base expression. Insert an LLVM cast of the pointer to + // uintptr_t first. + Value *BasePtr; + if (Constant *CB = dyn_cast(GEP->getOperand(0))) + BasePtr = ConstantExpr::getCast(CB, UIntPtrTy); + else { + Value *&BP = CastedBasePointers[GEP->getOperand(0)]; + if (BP == 0) { + BasicBlock::iterator InsertPt; + if (isa(GEP->getOperand(0))) { + InsertPt = GEP->getParent()->getParent()->begin()->begin(); + } else { + InsertPt = cast(GEP->getOperand(0)); + if (InvokeInst *II = dyn_cast(GEP->getOperand(0))) + InsertPt = II->getNormalDest()->begin(); + else + ++InsertPt; + } + BP = new CastInst(GEP->getOperand(0), UIntPtrTy, + GEP->getOperand(0)->getName(), InsertPt); } + BasePtr = BP; + } - if (operand == CanonicalIndVar) { - // FIXME: use getCanonicalInductionVariableIncrement to choose between - // one and neg one maybe? We need to support int *foo = GEP base, -1 - const Type *Ty = CanonicalIndVar->getType(); - pre_op_vector.push_back(Constant::getNullValue(Ty)); - inc_op_vector.push_back(ConstantInt::get(Ty, 1)); - indvar = op; - break; - } else if (isa(operand)) { - pre_op_vector.push_back(operand); - AllConstantOperands = false; - } else if (isa(operand)) { - pre_op_vector.push_back(operand); - } else if (Instruction *inst = dyn_cast(operand)) { - if (!DS->dominates(inst, Preheader->getTerminator())) - return; - pre_op_vector.push_back(operand); - AllConstantOperands = false; + SCEVHandle Base = SCEVUnknown::get(BasePtr); + + gep_type_iterator GTI = gep_type_begin(GEP); + unsigned i = 1; + for (; GEP->getOperand(i) != Op; ++i, ++GTI) { + // If this is a use of a recurrence that we can analyze, and it comes before + // Op does in the GEP operand list, we will handle this when we process this + // operand. + if (const StructType *STy = dyn_cast(*GTI)) { + const StructLayout *SL = TD->getStructLayout(STy); + unsigned Idx = cast(GEP->getOperand(i))->getValue(); + uint64_t Offset = SL->MemberOffsets[Idx]; + Base = SCEVAddExpr::get(Base, SCEVUnknown::getIntegerSCEV(Offset, + UIntPtrTy)); } else { - return; // Cannot handle this. + SCEVHandle Idx = SE->getSCEV(GEP->getOperand(i)); + if (CanReduceSCEV(Idx, L)) + return; + Base = SCEVAddExpr::get(Base, GetAdjustedIndex(Idx, + TD->getTypeSize(GTI.getIndexedType()), UIntPtrTy)); } - Cache = Cache->get(operand); } - assert(indvar > 0 && "Indvar used by GEP not found in operand list"); - // Ensure the pointer base is loop invariant. While strength reduction - // makes sense even if the pointer changed on every iteration, there is no - // realistic way of handling it unless GEPs were completely decomposed into - // their constituent operations so we have explicit multiplications to work - // with. - if (Instruction *GepPtrOp = dyn_cast(GEPI->getOperand(0))) - if (!DS->dominates(GepPtrOp, Preheader->getTerminator())) - return; - - // Don't reduce multiplies that the target can handle via addressing modes. - uint64_t sz = getAnalysis().getTypeSize(ty); - if (sz && (sz & (sz-1)) == 0) // Power of two? - if (sz <= (1ULL << (MaxTargetAMSize-1))) - return; - - // If all operands of the GEP we are going to insert into the preheader - // are constants, generate a GEP ConstantExpr instead. - // - // If there is only one operand after the initial non-constant one, we know - // that it was the induction variable, and has been replaced by a constant - // null value. In this case, replace the GEP with a use of pointer directly. - PHINode *NewPHI; - if (Cache->CachedPHINode == 0) { - Value *PreGEP; - if (AllConstantOperands && isa(GEPI->getOperand(0))) { - Constant *C = dyn_cast(GEPI->getOperand(0)); - PreGEP = ConstantExpr::getGetElementPtr(C, pre_op_vector); - } else if (pre_op_vector.size() == 1) { - PreGEP = GEPI->getOperand(0); + // Get the index, convert it to intptr_t. + SCEVHandle GEPIndexExpr = + GetAdjustedIndex(SE->getSCEV(Op), TD->getTypeSize(GTI.getIndexedType()), + UIntPtrTy); + + // Process all remaining subscripts in the GEP instruction. + for (++i, ++GTI; i != GEP->getNumOperands(); ++i, ++GTI) + if (const StructType *STy = dyn_cast(*GTI)) { + const StructLayout *SL = TD->getStructLayout(STy); + unsigned Idx = cast(GEP->getOperand(i))->getValue(); + uint64_t Offset = SL->MemberOffsets[Idx]; + Base = SCEVAddExpr::get(Base, SCEVUnknown::getIntegerSCEV(Offset, + UIntPtrTy)); } else { - PreGEP = new GetElementPtrInst(GEPI->getOperand(0), - pre_op_vector, GEPI->getName()+".pre", - Preheader->getTerminator()); - } - - // The next step of the strength reduction is to create a PHI that will - // choose between the initial GEP we created and inserted into the - // preheader, and the incremented GEP that we will create below and insert - // into the loop body. - NewPHI = new PHINode(PreGEP->getType(), - GEPI->getName()+".str", InsertBefore); - NewPHI->addIncoming(PreGEP, Preheader); - - // Now, create the GEP instruction to increment by one the value selected - // by the PHI instruction we just created above, and add it as the second - // incoming Value/BasicBlock pair to the PHINode. It is inserted before - // the increment of the canonical induction variable. - Instruction *IncrInst = - const_cast(L->getCanonicalInductionVariableIncrement()); - GetElementPtrInst *StrGEP = new GetElementPtrInst(NewPHI, inc_op_vector, - GEPI->getName()+".inc", - IncrInst); - pred_iterator PI = pred_begin(Header); - if (*PI == Preheader) - ++PI; - NewPHI->addIncoming(StrGEP, *PI); - Cache->CachedPHINode = NewPHI; - } else { - // Reuse previously created pointer, as it is identical to the one we were - // about to create. - NewPHI = Cache->CachedPHINode; + SCEVHandle Idx = SE->getSCEV(GEP->getOperand(i)); + if (CanReduceSCEV(Idx, L)) { // Another IV subscript + GEPIndexExpr = SCEVAddExpr::get(GEPIndexExpr, + GetAdjustedIndex(Idx, TD->getTypeSize(GTI.getIndexedType()), + UIntPtrTy)); + assert(CanReduceSCEV(GEPIndexExpr, L) && + "Cannot reduce the sum of two reducible SCEV's??"); + } else { + Base = SCEVAddExpr::get(Base, GetAdjustedIndex(Idx, + TD->getTypeSize(GTI.getIndexedType()), UIntPtrTy)); + } + } + + assert(CanReduceSCEV(GEPIndexExpr, L) && "Non reducible idx??"); + + Base = SCEVAddExpr::get(Base, cast(GEPIndexExpr)->getStart()); + SCEVHandle Stride = cast(GEPIndexExpr)->getOperand(1); + + DEBUG(std::cerr << "GEP BASE : " << *Base << "\n"); + DEBUG(std::cerr << "GEP STRIDE: " << *Stride << "\n"); + + Value *Step = 0; // Step of ISE. + if (SCEVConstant *SC = dyn_cast(Stride)) + /// Always get the step value as an unsigned value. + Step = ConstantExpr::getCast(SC->getValue(), + SC->getValue()->getType()->getUnsignedVersion()); + else + Step = cast(Stride)->getValue(); + assert(Step->getType()->isUnsigned() && "Bad step value!"); + + + // Now that we know the base and stride contributed by the GEP instruction, + // process all users. + for (Value::use_iterator UI = GEP->use_begin(), E = GEP->use_end(); + UI != E; ++UI) { + Instruction *User = cast(*UI); + + // Do not infinitely recurse on PHI nodes. + if (isa(User) && User->getParent() == L->getHeader()) + continue; + + // If this is an instruction defined in a nested loop, or outside this loop, + // don't mess with it. + if (LI->getLoopFor(User->getParent()) != L) + continue; + + DEBUG(std::cerr << "FOUND USER: " << *User + << " OF STRIDE: " << *Step << " BASE = " << *Base << "\n"); + + + // Okay, we found a user that we cannot reduce. Analyze the instruction + // and decide what to do with it. + IVUsesByStride[Step].addUser(Base, User, GEP); + } +} + +/// AddUsersIfInteresting - Inspect the specified instruction. If it is a +/// reducible SCEV, recursively add its users to the IVUsesByStride set and +/// return true. Otherwise, return false. +bool LoopStrengthReduce::AddUsersIfInteresting(Instruction *I, Loop *L) { + if (I->getType() == Type::VoidTy) return false + SCEVHandle ISE = SE->getSCEV(I); + if (!CanReduceSCEV(ISE, L)) return false; + + SCEVAddRecExpr *AR = cast(ISE); + SCEVHandle Start = AR->getStart(); + + // Get the step value, canonicalizing to an unsigned integer type so that + // lookups in the map will match. + Value *Step = 0; // Step of ISE. + if (SCEVConstant *SC = dyn_cast(AR->getOperand(1))) + /// Always get the step value as an unsigned value. + Step = ConstantExpr::getCast(SC->getValue(), + SC->getValue()->getType()->getUnsignedVersion()); + else + Step = cast(AR->getOperand(1))->getValue(); + assert(Step->getType()->isUnsigned() && "Bad step value!"); + + std::set AnalyzedGEPs; + + for (Value::use_iterator UI = I->use_begin(), E = I->use_end(); UI != E;++UI){ + Instruction *User = cast(*UI); + + // Do not infinitely recurse on PHI nodes. + if (isa(User) && User->getParent() == L->getHeader()) + continue; + + // If this is an instruction defined in a nested loop, or outside this loop, + // don't mess with it. + if (LI->getLoopFor(User->getParent()) != L) + continue; + + // Next, see if this user is analyzable itself! + if (!AddUsersIfInteresting(User, L)) { + if (GetElementPtrInst *GEP = dyn_cast(User)) { + // If this is a getelementptr instruction, figure out what linear + // expression of induction variable is actually being used. + // + if (AnalyzedGEPs.insert(GEP).second) // Not already analyzed? + AnalyzeGetElementPtrUsers(GEP, I, L); + } else { + DEBUG(std::cerr << "FOUND USER: " << *User + << " OF SCEV: " << *ISE << "\n"); + + // Okay, we found a user that we cannot reduce. Analyze the instruction + // and decide what to do with it. + IVUsesByStride[Step].addUser(Start, User, I); + } + } } + return true; +} + +namespace { + /// BasedUser - For a particular base value, keep information about how we've + /// partitioned the expression so far. + struct BasedUser { + /// Inst - The instruction using the induction variable. + Instruction *Inst; + + /// Op - The value to replace with the EmittedBase. + Value *Op; + + /// Imm - The immediate value that should be added to the base immediately + /// before Inst, because it will be folded into the imm field of the + /// instruction. + SCEVHandle Imm; + + /// EmittedBase - The actual value* to use for the base value of this + /// operation. This is null if we should just use zero so far. + Value *EmittedBase; + + BasedUser(Instruction *I, Value *V, const SCEVHandle &IMM) + : Inst(I), Op(V), Imm(IMM), EmittedBase(0) {} + + + // No need to compare these. + bool operator<(const BasedUser &BU) const { return 0; } + + void dump() const; + }; +} + +void BasedUser::dump() const { + std::cerr << " Imm=" << *Imm; + if (EmittedBase) + std::cerr << " EB=" << *EmittedBase; + + std::cerr << " Inst: " << *Inst; +} - if (GEPI->getNumOperands() - 1 == indvar) { - // If there were no operands following the induction variable, replace all - // uses of the old GEP instruction with the new PHI. - GEPI->replaceAllUsesWith(NewPHI); - } else { - // Create a new GEP instruction using the new PHI as the base. The - // operands of the original GEP past the induction variable become - // operands of this new GEP. - std::vector op_vector; - const Type *Ty = CanonicalIndVar->getType(); - op_vector.push_back(Constant::getNullValue(Ty)); - for (unsigned op = indvar + 1; op < GEPI->getNumOperands(); op++) - op_vector.push_back(GEPI->getOperand(op)); - GetElementPtrInst *newGEP = new GetElementPtrInst(NewPHI, op_vector, - GEPI->getName() + ".lsr", - GEPI); - GEPI->replaceAllUsesWith(newGEP); +/// isTargetConstant - Return true if the following can be referenced by the +/// immediate field of a target instruction. +static bool isTargetConstant(const SCEVHandle &V) { + + // FIXME: Look at the target to decide if &GV is a legal constant immediate. + if (isa(V)) return true; + + return false; // ENABLE this for x86 + + if (SCEVUnknown *SU = dyn_cast(V)) + if (ConstantExpr *CE = dyn_cast(SU->getValue())) + if (CE->getOpcode() == Instruction::Cast) + if (isa(CE->getOperand(0))) + // FIXME: should check to see that the dest is uintptr_t! + return true; + return false; +} + +/// GetImmediateValues - Look at Val, and pull out any additions of constants +/// that can fit into the immediate field of instructions in the target. +static SCEVHandle GetImmediateValues(SCEVHandle Val, bool isAddress) { + if (!isAddress) + return SCEVUnknown::getIntegerSCEV(0, Val->getType()); + if (isTargetConstant(Val)) + return Val; + + SCEVAddExpr *SAE = dyn_cast(Val); + if (SAE) { + unsigned i = 0; + for (; i != SAE->getNumOperands(); ++i) + if (isTargetConstant(SAE->getOperand(i))) { + SCEVHandle ImmVal = SAE->getOperand(i); + + // If there are any other immediates that we can handle here, pull them + // out too. + for (++i; i != SAE->getNumOperands(); ++i) + if (isTargetConstant(SAE->getOperand(i))) + ImmVal = SCEVAddExpr::get(ImmVal, SAE->getOperand(i)); + return ImmVal; + } + } + + return SCEVUnknown::getIntegerSCEV(0, Val->getType()); +} + +/// StrengthReduceStridedIVUsers - Strength reduce all of the users of a single +/// stride of IV. All of the users may have different starting values, and this +/// may not be the only stride (we know it is if isOnlyStride is true). +void LoopStrengthReduce::StrengthReduceStridedIVUsers(Value *Stride, + IVUse &Uses, Loop *L, + bool isOnlyStride) { + // Transform our list of users and offsets to a bit more complex table. In + // this new vector, the first entry for each element is the base of the + // strided access, and the second is the BasedUser object for the use. We + // progressively move information from the first to the second entry, until we + // eventually emit the object. + std::vector > UsersToProcess; + UsersToProcess.reserve(Uses.Users.size()); + + SCEVHandle ZeroBase = SCEVUnknown::getIntegerSCEV(0, + Uses.Users[0].first->getType()); + + for (unsigned i = 0, e = Uses.Users.size(); i != e; ++i) + UsersToProcess.push_back(std::make_pair(Uses.Users[i].first, + BasedUser(Uses.Users[i].second, + Uses.UserOperands[i], + ZeroBase))); + + // First pass, figure out what we can represent in the immediate fields of + // instructions. If we can represent anything there, move it to the imm + // fields of the BasedUsers. + for (unsigned i = 0, e = UsersToProcess.size(); i != e; ++i) { + bool isAddress = isa(UsersToProcess[i].second.Inst) || + isa(UsersToProcess[i].second.Inst); + UsersToProcess[i].second.Imm = GetImmediateValues(UsersToProcess[i].first, + isAddress); + UsersToProcess[i].first = SCEV::getMinusSCEV(UsersToProcess[i].first, + UsersToProcess[i].second.Imm); + + DEBUG(std::cerr << "BASE: " << *UsersToProcess[i].first); + DEBUG(UsersToProcess[i].second.dump()); } - // The old GEP is now dead. - DeadInsts.insert(GEPI); - ++NumReduced; + SCEVExpander Rewriter(*SE, *LI); + BasicBlock *Preheader = L->getLoopPreheader(); + Instruction *PreInsertPt = Preheader->getTerminator(); + Instruction *PhiInsertBefore = L->getHeader()->begin(); + + assert(isa(PhiInsertBefore) && + "How could this loop have IV's without any phis?"); + PHINode *SomeLoopPHI = cast(PhiInsertBefore); + assert(SomeLoopPHI->getNumIncomingValues() == 2 && + "This loop isn't canonicalized right"); + BasicBlock *LatchBlock = + SomeLoopPHI->getIncomingBlock(SomeLoopPHI->getIncomingBlock(0) == Preheader); + + // FIXME: This loop needs increasing levels of intelligence. + // STAGE 0: just emit everything as its own base. <-- We are here + // STAGE 1: factor out common vars from bases, and try and push resulting + // constants into Imm field. + // STAGE 2: factor out large constants to try and make more constants + // acceptable for target loads and stores. + std::sort(UsersToProcess.begin(), UsersToProcess.end()); + + while (!UsersToProcess.empty()) { + // Create a new Phi for this base, and stick it in the loop header. + Value *Replaced = UsersToProcess.front().second.Op; + const Type *ReplacedTy = Replaced->getType(); + PHINode *NewPHI = new PHINode(ReplacedTy, Replaced->getName()+".str", + PhiInsertBefore); + + // Emit the initial base value into the loop preheader, and add it to the + // Phi node. + Value *BaseV = Rewriter.expandCodeFor(UsersToProcess.front().first, + PreInsertPt, ReplacedTy); + NewPHI->addIncoming(BaseV, Preheader); + + // Emit the increment of the base value before the terminator of the loop + // latch block, and add it to the Phi node. + SCEVHandle Inc = SCEVAddExpr::get(SCEVUnknown::get(NewPHI), + SCEVUnknown::get(Stride)); + + Value *IncV = Rewriter.expandCodeFor(Inc, LatchBlock->getTerminator(), + ReplacedTy); + IncV->setName(NewPHI->getName()+".inc"); + NewPHI->addIncoming(IncV, LatchBlock); + + // Emit the code to add the immediate offset to the Phi value, just before + // the instruction that we identified as using this stride and base. + // First, empty the SCEVExpander's expression map so that we are guaranteed + // to have the code emitted where we expect it. + Rewriter.clear(); + SCEVHandle NewValSCEV = SCEVAddExpr::get(SCEVUnknown::get(NewPHI), + UsersToProcess.front().second.Imm); + Value *newVal = Rewriter.expandCodeFor(NewValSCEV, + UsersToProcess.front().second.Inst, + ReplacedTy); + + // Replace the use of the operand Value with the new Phi we just created. + DEBUG(std::cerr << "REPLACING: " << *Replaced << "IN: " << + *UsersToProcess.front().second.Inst << "WITH: "<< *newVal << '\n'); + UsersToProcess.front().second.Inst->replaceUsesOfWith(Replaced, newVal); + + // Mark old value we replaced as possibly dead, so that it is elminated + // if we just replaced the last use of that value. + DeadInsts.insert(cast(Replaced)); + + UsersToProcess.erase(UsersToProcess.begin()); + ++NumReduced; + + // TODO: Next, find out which base index is the most common, pull it out. + } + + // IMPORTANT TODO: Figure out how to partition the IV's with this stride, but + // different starting values, into different PHIs. + + // BEFORE writing this, it's probably useful to handle GEP's. + + // NOTE: pull all constants together, for REG+IMM addressing, include &GV in + // 'IMM' if the target supports it. } + void LoopStrengthReduce::runOnLoop(Loop *L) { // First step, transform all loops nesting inside of this loop. for (LoopInfo::iterator I = L->begin(), E = L->end(); I != E; ++I) runOnLoop(*I); - // Next, get the first PHINode since it is guaranteed to be the canonical - // induction variable for the loop by the preceding IndVarSimplify pass. - PHINode *PN = L->getCanonicalInductionVariable(); - if (0 == PN) - return; - - // FIXME: Need to use SCEV to detect GEP uses of the indvar, since indvars - // pass creates code like this, which we can't currently detect: - // %tmp.1 = sub uint 2000, %indvar - // %tmp.8 = getelementptr int* %y, uint %tmp.1 - - // Strength reduce all GEPs in the Loop. Insert secondary PHI nodes for the - // strength reduced pointers we'll be creating after the canonical induction - // variable's PHI. - std::set DeadInsts; - GEPCache Cache; - for (Value::use_iterator UI = PN->use_begin(), UE = PN->use_end(); - UI != UE; ++UI) - if (GetElementPtrInst *GEPI = dyn_cast(*UI)) - strengthReduceGEP(GEPI, L, &Cache, PN->getNext(), DeadInsts); + // Next, find all uses of induction variables in this loop, and catagorize + // them by stride. Start by finding all of the PHI nodes in the header for + // this loop. If they are induction variables, inspect their uses. + for (BasicBlock::iterator I = L->getHeader()->begin(); isa(I); ++I) + AddUsersIfInteresting(I, L); + + // If we have nothing to do, return. + //if (IVUsesByStride.empty()) return; + + // FIXME: We can widen subreg IV's here for RISC targets. e.g. instead of + // doing computation in byte values, promote to 32-bit values if safe. + + // FIXME: Attempt to reuse values across multiple IV's. In particular, we + // could have something like "for(i) { foo(i*8); bar(i*16) }", which should be + // codegened as "for (j = 0;; j+=8) { foo(j); bar(j+j); }" on X86/PPC. Need + // to be careful that IV's are all the same type. Only works for intptr_t + // indvars. + + // If we only have one stride, we can more aggressively eliminate some things. + bool HasOneStride = IVUsesByStride.size() == 1; + + for (std::map::iterator SI = IVUsesByStride.begin(), + E = IVUsesByStride.end(); SI != E; ++SI) + StrengthReduceStridedIVUsers(SI->first, SI->second, L, HasOneStride); // Clean up after ourselves if (!DeadInsts.empty()) { DeleteTriviallyDeadInstructions(DeadInsts); - // At this point, we know that we have killed one or more GEP instructions. - // It is worth checking to see if the cann indvar is also dead, so that we - // can remove it as well. The requirements for the cann indvar to be - // considered dead are: - // 1. the cann indvar has one use - // 2. the use is an add instruction - // 3. the add has one use - // 4. the add is used by the cann indvar - // If all four cases above are true, then we can remove both the add and - // the cann indvar. - // FIXME: this needs to eliminate an induction variable even if it's being - // compared against some value to decide loop termination. - if (PN->hasOneUse()) { - BinaryOperator *BO = dyn_cast(*(PN->use_begin())); - if (BO && BO->getOpcode() == Instruction::Add) - if (BO->hasOneUse()) { - if (PN == dyn_cast(*(BO->use_begin()))) { - DeadInsts.insert(BO); - // Break the cycle, then delete the PHI. - PN->replaceAllUsesWith(UndefValue::get(PN->getType())); - PN->eraseFromParent(); - DeleteTriviallyDeadInstructions(DeadInsts); + BasicBlock::iterator I = L->getHeader()->begin(); + PHINode *PN; + for (; (PN = dyn_cast(I)); ++I) { + // At this point, we know that we have killed one or more GEP instructions. + // It is worth checking to see if the cann indvar is also dead, so that we + // can remove it as well. The requirements for the cann indvar to be + // considered dead are: + // 1. the cann indvar has one use + // 2. the use is an add instruction + // 3. the add has one use + // 4. the add is used by the cann indvar + // If all four cases above are true, then we can remove both the add and + // the cann indvar. + // FIXME: this needs to eliminate an induction variable even if it's being + // compared against some value to decide loop termination. + if (PN->hasOneUse()) { + BinaryOperator *BO = dyn_cast(*(PN->use_begin())); + if (BO && BO->getOpcode() == Instruction::Add) + if (BO->hasOneUse()) { + if (PN == dyn_cast(*(BO->use_begin()))) { + DeadInsts.insert(BO); + // Break the cycle, then delete the PHI. + PN->replaceAllUsesWith(UndefValue::get(PN->getType())); + PN->eraseFromParent(); + } } - } + } } + DeleteTriviallyDeadInstructions(DeadInsts); } + + IVUsesByStride.clear(); + return; } From jeffc at jolt-lang.org Wed Jul 27 00:54:01 2005 From: jeffc at jolt-lang.org (Jeff Cohen) Date: Wed, 27 Jul 2005 00:54:01 -0500 Subject: [llvm-commits] CVS: llvm/lib/Target/SparcV9/InstrSched/InstrScheduling.cpp SchedGraph.cpp SchedGraph.h SchedGraphCommon.cpp SchedPriorities.cpp SchedPriorities.h Message-ID: <200507270554.AAA12858@zion.cs.uiuc.edu> Changes in directory llvm/lib/Target/SparcV9/InstrSched: InstrScheduling.cpp updated: 1.83 -> 1.84 SchedGraph.cpp updated: 1.69 -> 1.70 SchedGraph.h updated: 1.41 -> 1.42 SchedGraphCommon.cpp updated: 1.9 -> 1.10 SchedPriorities.cpp updated: 1.37 -> 1.38 SchedPriorities.h updated: 1.29 -> 1.30 --- Log message: Eliminate tabs and trailing spaces. --- Diffs of the changes: (+258 -258) InstrScheduling.cpp | 220 +++++++++++++++++++++++++-------------------------- SchedGraph.cpp | 88 ++++++++++---------- SchedGraph.h | 48 +++++------ SchedGraphCommon.cpp | 54 ++++++------ SchedPriorities.cpp | 26 +++--- SchedPriorities.h | 80 +++++++++--------- 6 files changed, 258 insertions(+), 258 deletions(-) Index: llvm/lib/Target/SparcV9/InstrSched/InstrScheduling.cpp diff -u llvm/lib/Target/SparcV9/InstrSched/InstrScheduling.cpp:1.83 llvm/lib/Target/SparcV9/InstrSched/InstrScheduling.cpp:1.84 --- llvm/lib/Target/SparcV9/InstrSched/InstrScheduling.cpp:1.83 Fri May 13 14:42:31 2005 +++ llvm/lib/Target/SparcV9/InstrSched/InstrScheduling.cpp Wed Jul 27 00:53:43 2005 @@ -68,15 +68,15 @@ private: friend class InstrSchedule; - inline void addInstr(const SchedGraphNode* node, unsigned int slotNum) { + inline void addInstr(const SchedGraphNode* node, unsigned int slotNum) { assert(slotNum < group.size()); group[slotNum] = node; } - /*ctor*/ InstrGroup(unsigned int nslots) + /*ctor*/ InstrGroup(unsigned int nslots) : group(nslots, NULL) {} - /*ctor*/ InstrGroup(); // disable: DO NOT IMPLEMENT + /*ctor*/ InstrGroup(); // disable: DO NOT IMPLEMENT private: std::vector group; @@ -100,8 +100,8 @@ typedef ScheduleIterator<_NodeType> _Self; /*ctor*/ inline ScheduleIterator(const InstrSchedule& _schedule, - unsigned _cycleNum, - unsigned _slotNum) + unsigned _cycleNum, + unsigned _slotNum) : cycleNum(_cycleNum), slotNum(_slotNum), S(_schedule) { skipToNextInstr(); } @@ -118,8 +118,8 @@ inline _NodeType* operator*() const; inline _NodeType* operator->() const { return operator*(); } - _Self& operator++(); // Preincrement - inline _Self operator++(int) { // Postincrement + _Self& operator++(); // Preincrement + inline _Self operator++(int) { // Postincrement _Self tmp(*this); ++*this; return tmp; } @@ -128,7 +128,7 @@ private: inline _Self& operator=(const _Self& x); // DISABLE -- DO NOT IMPLEMENT - void skipToNextInstr(); + void skipToNextInstr(); }; @@ -141,8 +141,8 @@ class InstrSchedule { const unsigned int nslots; unsigned int numInstr; - std::vector groups; // indexed by cycle number - std::vector startTime; // indexed by node id + std::vector groups; // indexed by cycle number + std::vector startTime; // indexed by node id InstrSchedule(InstrSchedule&); // DO NOT IMPLEMENT void operator=(InstrSchedule&); // DO NOT IMPLEMENT @@ -157,18 +157,18 @@ const_iterator end() const { return const_iterator::end(*this); } public: // constructors and destructor - /*ctor*/ InstrSchedule (unsigned int _nslots, - unsigned int _numNodes); - /*dtor*/ ~InstrSchedule (); + /*ctor*/ InstrSchedule (unsigned int _nslots, + unsigned int _numNodes); + /*dtor*/ ~InstrSchedule (); public: // accessor functions to query chosen schedule - const SchedGraphNode* getInstr (unsigned int slotNum, - CycleCount_t c) { + const SchedGraphNode* getInstr (unsigned int slotNum, + CycleCount_t c) { const InstrGroup* igroup = this->getIGroup(c); return (igroup == NULL)? NULL : (*igroup)[slotNum]; } - inline InstrGroup* getIGroup (CycleCount_t c) { + inline InstrGroup* getIGroup (CycleCount_t c) { if ((unsigned)c >= groups.size()) groups.resize(c+1); if (groups[c] == NULL) @@ -176,23 +176,23 @@ return groups[c]; } - inline const InstrGroup* getIGroup (CycleCount_t c) const { + inline const InstrGroup* getIGroup (CycleCount_t c) const { assert((unsigned)c < groups.size()); return groups[c]; } - inline CycleCount_t getStartTime (unsigned int nodeId) const { + inline CycleCount_t getStartTime (unsigned int nodeId) const { assert(nodeId < startTime.size()); return startTime[nodeId]; } - unsigned int getNumInstructions() const { + unsigned int getNumInstructions() const { return numInstr; } - inline void scheduleInstr (const SchedGraphNode* node, - unsigned int slotNum, - CycleCount_t cycle) { + inline void scheduleInstr (const SchedGraphNode* node, + unsigned int slotNum, + CycleCount_t cycle) { InstrGroup* igroup = this->getIGroup(cycle); if (!((*igroup)[slotNum] == NULL)) { std::cerr << "Slot already filled?\n"; @@ -207,7 +207,7 @@ private: friend class ScheduleIterator; friend class ScheduleIterator; - /*ctor*/ InstrSchedule (); // Disable: DO NOT IMPLEMENT. + /*ctor*/ InstrSchedule (); // Disable: DO NOT IMPLEMENT. }; template @@ -221,8 +221,8 @@ InstrSchedule::InstrSchedule(unsigned int _nslots, unsigned int _numNodes) : nslots(_nslots), numInstr(0), - groups(2 * _numNodes / _nslots), // 2 x lower-bound for #cycles - startTime(_numNodes, (CycleCount_t) -1) // set all to -1 + groups(2 * _numNodes / _nslots), // 2 x lower-bound for #cycles + startTime(_numNodes, (CycleCount_t) -1) // set all to -1 { } @@ -232,7 +232,7 @@ { for (unsigned c=0, NC=groups.size(); c < NC; c++) if (groups[c] != NULL) - delete groups[c]; // delete InstrGroup objects + delete groups[c]; // delete InstrGroup objects } @@ -242,17 +242,17 @@ ScheduleIterator<_NodeType>::skipToNextInstr() { while(cycleNum < S.groups.size() && S.groups[cycleNum] == NULL) - ++cycleNum; // skip cycles with no instructions + ++cycleNum; // skip cycles with no instructions while (cycleNum < S.groups.size() && - (*S.groups[cycleNum])[slotNum] == NULL) + (*S.groups[cycleNum])[slotNum] == NULL) { ++slotNum; if (slotNum == S.nslots) { ++cycleNum; slotNum = 0; while(cycleNum < S.groups.size() && S.groups[cycleNum] == NULL) - ++cycleNum; // skip cycles with no instructions + ++cycleNum; // skip cycles with no instructions } } } @@ -260,7 +260,7 @@ template inline ScheduleIterator<_NodeType>& -ScheduleIterator<_NodeType>::operator++() // Preincrement +ScheduleIterator<_NodeType>::operator++() // Preincrement { ++slotNum; if (slotNum == S.nslots) { @@ -303,12 +303,12 @@ DelaySlotInfo(const DelaySlotInfo &); // DO NOT IMPLEMENT void operator=(const DelaySlotInfo&); // DO NOT IMPLEMENT public: - /*ctor*/ DelaySlotInfo (const SchedGraphNode* _brNode, - unsigned _ndelays) + /*ctor*/ DelaySlotInfo (const SchedGraphNode* _brNode, + unsigned _ndelays) : brNode(_brNode), ndelays(_ndelays), delayedNodeCycle(0), delayedNodeSlotNum(0) {} - inline unsigned getNumDelays () { + inline unsigned getNumDelays () { return ndelays; } @@ -316,17 +316,17 @@ return delayNodeVec; } - inline void addDelayNode (const SchedGraphNode* node) { + inline void addDelayNode (const SchedGraphNode* node) { delayNodeVec.push_back(node); assert(delayNodeVec.size() <= ndelays && "Too many delay slot instrs!"); } - inline void recordChosenSlot (CycleCount_t cycle, unsigned slotNum) { + inline void recordChosenSlot (CycleCount_t cycle, unsigned slotNum) { delayedNodeCycle = cycle; delayedNodeSlotNum = slotNum; } - unsigned scheduleDelayedNode (SchedulingManager& S); + unsigned scheduleDelayedNode (SchedulingManager& S); }; @@ -348,14 +348,14 @@ private: unsigned totalInstrCount; CycleCount_t curTime; - CycleCount_t nextEarliestIssueTime; // next cycle we can issue + CycleCount_t nextEarliestIssueTime; // next cycle we can issue // indexed by slot# std::vector > choicesForSlot; - std::vector choiceVec; // indexed by node ptr - std::vector numInClass; // indexed by sched class - std::vector nextEarliestStartTime; // indexed by opCode + std::vector choiceVec; // indexed by node ptr + std::vector numInClass; // indexed by sched class + std::vector nextEarliestStartTime; // indexed by opCode hash_map delaySlotInfoForBranches; - // indexed by branch node ptr + // indexed by branch node ptr public: SchedulingManager(const TargetMachine& _target, const SchedGraph* graph, @@ -371,7 +371,7 @@ // Simplify access to the machine instruction info //---------------------------------------------------------------------- - inline const TargetInstrInfo& getInstrInfo () const { + inline const TargetInstrInfo& getInstrInfo () const { return schedInfo.getInstrInfo(); } @@ -379,21 +379,21 @@ // Interface for checking and updating the current time //---------------------------------------------------------------------- - inline CycleCount_t getTime () const { + inline CycleCount_t getTime () const { return curTime; } - inline CycleCount_t getEarliestIssueTime() const { + inline CycleCount_t getEarliestIssueTime() const { return nextEarliestIssueTime; } - inline CycleCount_t getEarliestStartTimeForOp(MachineOpCode opCode) const { + inline CycleCount_t getEarliestStartTimeForOp(MachineOpCode opCode) const { assert(opCode < (int) nextEarliestStartTime.size()); return nextEarliestStartTime[opCode]; } // Update current time to specified cycle - inline void updateTime (CycleCount_t c) { + inline void updateTime (CycleCount_t c) { curTime = c; schedPrio.updateTime(c); } @@ -406,17 +406,17 @@ // between choices for a single cycle //---------------------------------------------------------------------- - inline unsigned int getNumChoices () const { + inline unsigned int getNumChoices () const { return choiceVec.size(); } - inline unsigned getNumChoicesInClass (const InstrSchedClass& sc) const { + inline unsigned getNumChoicesInClass (const InstrSchedClass& sc) const { assert(sc < numInClass.size() && "Invalid op code or sched class!"); return numInClass[sc]; } inline const SchedGraphNode* getChoice(unsigned int i) const { - // assert(i < choiceVec.size()); don't check here. + // assert(i < choiceVec.size()); don't check here. return choiceVec[i]; } @@ -425,7 +425,7 @@ return choicesForSlot[slotNum]; } - inline void addChoice (const SchedGraphNode* node) { + inline void addChoice (const SchedGraphNode* node) { // Append the instruction to the vector of choices for current cycle. // Increment numInClass[c] for the sched class to which the instr belongs. choiceVec.push_back(node); @@ -434,14 +434,14 @@ numInClass[sc]++; } - inline void addChoiceToSlot (unsigned int slotNum, - const SchedGraphNode* node) { + inline void addChoiceToSlot (unsigned int slotNum, + const SchedGraphNode* node) { // Add the instruction to the choice set for the specified slot assert(slotNum < nslots); choicesForSlot[slotNum].insert(node); } - inline void resetChoices () { + inline void resetChoices () { choiceVec.clear(); for (unsigned int s=0; s < nslots; s++) choicesForSlot[s].clear(); @@ -453,21 +453,21 @@ // Code to query and manage the partial instruction schedule so far //---------------------------------------------------------------------- - inline unsigned int getNumScheduled () const { + inline unsigned int getNumScheduled () const { return isched.getNumInstructions(); } - inline unsigned int getNumUnscheduled() const { + inline unsigned int getNumUnscheduled() const { return totalInstrCount - isched.getNumInstructions(); } - inline bool isScheduled (const SchedGraphNode* node) const { + inline bool isScheduled (const SchedGraphNode* node) const { return (isched.getStartTime(node->getNodeId()) >= 0); } - inline void scheduleInstr (const SchedGraphNode* node, - unsigned int slotNum, - CycleCount_t cycle) + inline void scheduleInstr (const SchedGraphNode* node, + unsigned int slotNum, + CycleCount_t cycle) { assert(! isScheduled(node) && "Instruction already scheduled?"); @@ -493,7 +493,7 @@ //---------------------------------------------------------------------- inline DelaySlotInfo* getDelaySlotInfoForInstr(const SchedGraphNode* bn, - bool createIfMissing=false) + bool createIfMissing=false) { hash_map::const_iterator I = delaySlotInfoForBranches.find(bn); @@ -515,8 +515,8 @@ /*ctor*/ SchedulingManager::SchedulingManager(const TargetMachine& target, - const SchedGraph* graph, - SchedPriorities& _schedPrio) + const SchedGraph* graph, + SchedPriorities& _schedPrio) : nslots(target.getSchedInfo()->getMaxNumIssueTotal()), schedInfo(*target.getSchedInfo()), schedPrio(_schedPrio), @@ -524,9 +524,9 @@ totalInstrCount(graph->getNumNodes() - 2), nextEarliestIssueTime(0), choicesForSlot(nslots), - numInClass(target.getSchedInfo()->getNumSchedClasses(), 0), // set all to 0 + numInClass(target.getSchedInfo()->getNumSchedClasses(), 0), // set all to 0 nextEarliestStartTime(target.getInstrInfo()->getNumOpcodes(), - (CycleCount_t) 0) // set all to 0 + (CycleCount_t) 0) // set all to 0 { updateTime(0); @@ -540,12 +540,12 @@ void SchedulingManager::updateEarliestStartTimes(const SchedGraphNode* node, - CycleCount_t schedTime) + CycleCount_t schedTime) { if (schedInfo.numBubblesAfter(node->getOpcode()) > 0) { // Update next earliest time before which *nothing* can issue. nextEarliestIssueTime = std::max(nextEarliestIssueTime, - curTime + 1 + schedInfo.numBubblesAfter(node->getOpcode())); + curTime + 1 + schedInfo.numBubblesAfter(node->getOpcode())); } const std::vector& @@ -637,10 +637,10 @@ if (!(I->getOpcode() == V9::NOP || I->getOpcode() == V9::PHI)) ++numInstr; assert(S.isched.getNumInstructions() >= numInstr && - "Lost some non-NOP instructions during scheduling!"); + "Lost some non-NOP instructions during scheduling!"); if (S.isched.getNumInstructions() == 0) - return; // empty basic block! + return; // empty basic block! // First find the dummy instructions at the start of the basic block MachineBasicBlock::iterator I = MBB.begin(); @@ -668,19 +668,19 @@ // for (sg_succ_const_iterator SI = succ_begin(node); SI !=succ_end(node); ++SI) if (! (*SI)->isDummyNode() - && ! S.isScheduled(*SI) - && ! S.schedPrio.nodeIsReady(*SI)) + && ! S.isScheduled(*SI) + && ! S.schedPrio.nodeIsReady(*SI)) { // successor not scheduled and not marked ready; check *its* preds. - + bool succIsReady = true; for (sg_pred_const_iterator P=pred_begin(*SI); P != pred_end(*SI); ++P) if (! (*P)->isDummyNode() && ! S.isScheduled(*P)) { succIsReady = false; break; } - - if (succIsReady) // add the successor to the ready list + + if (succIsReady) // add the successor to the ready list S.schedPrio.insertReady(*SI); } } @@ -692,12 +692,12 @@ // of chosen instructions can be issued in a single group. // // Return value: -// maxIssue : total number of feasible instructions -// S.choicesForSlot[i=0..nslots] : set of instructions feasible in slot i +// maxIssue : total number of feasible instructions +// S.choicesForSlot[i=0..nslots] : set of instructions feasible in slot i // static unsigned FindSlotChoices(SchedulingManager& S, - DelaySlotInfo*& getDelaySlotInfo) + DelaySlotInfo*& getDelaySlotInfo) { // initialize result vectors to empty S.resetChoices(); @@ -727,7 +727,7 @@ while (S.getNumChoices() < S.nslots - startSlot) { const SchedGraphNode* nextNode=S.schedPrio.getNextHighest(S,S.getTime()); if (nextNode == NULL) - break; // no more instructions for this cycle + break; // no more instructions for this cycle if (S.getInstrInfo().getNumDelaySlots(nextNode->getOpcode()) > 0) { delaySlotInfo = S.getDelaySlotInfoForInstr(nextNode); @@ -758,12 +758,12 @@ } if (indexForDelayedInstr < S.nslots) - break; // leave the rest for delay slots + break; // leave the rest for delay slots } assert(S.getNumChoices() <= S.nslots); assert(! (indexForDelayedInstr < S.nslots && - indexForBreakingNode < S.nslots) && "Cannot have both in a cycle"); + indexForBreakingNode < S.nslots) && "Cannot have both in a cycle"); // Assign each chosen instruction to all possible slots for that instr. // But if only one instruction was chosen, put it only in the first @@ -828,7 +828,7 @@ S.addChoiceToSlot(s, S.getChoice(i)); noSlotFound = false; } - + // No slot before `delayedNodeSlot' was found for this opCode // Use a later slot, and allow some delay slots to fall in // the next cycle. @@ -838,9 +838,9 @@ S.addChoiceToSlot(s, S.getChoice(i)); break; } - + assert(s < S.nslots && "No feasible slot for instruction?"); - + highestSlotUsed = std::max(highestSlotUsed, (int) s); } @@ -867,7 +867,7 @@ const SchedGraphNode* breakingNode=S.getChoice(indexForBreakingNode); unsigned breakingSlot = INT_MAX; unsigned int nslotsToUse = S.nslots; - + // Find the last possible slot for this instruction. for (int s = S.nslots-1; s >= (int) startSlot; s--) if (S.schedInfo.instrCanUseSlot(breakingNode->getOpcode(), s)) { @@ -884,24 +884,24 @@ i < S.getNumChoices() && i < indexForBreakingNode; i++) { MachineOpCode opCode =S.getChoice(i)->getOpcode(); - + // If a higher priority instruction cannot be assigned to // any earlier slots, don't schedule the breaking instruction. // bool foundLowerSlot = false; - nslotsToUse = S.nslots; // May be modified in the loop + nslotsToUse = S.nslots; // May be modified in the loop for (unsigned int s=startSlot; s < nslotsToUse; s++) if (S.schedInfo.instrCanUseSlot(opCode, s)) { if (breakingSlot < S.nslots && s < breakingSlot) { foundLowerSlot = true; nslotsToUse = breakingSlot; // RESETS LOOP UPPER BOUND! } - + S.addChoiceToSlot(s, S.getChoice(i)); } - + if (!foundLowerSlot) - breakingSlot = INT_MAX; // disable breaking instr + breakingSlot = INT_MAX; // disable breaking instr } // Assign the breaking instruction (if any) to a single slot @@ -912,7 +912,7 @@ nslotsToUse = breakingSlot; } else nslotsToUse = S.nslots; - + // For lower priority instructions than the one that breaks the // group, only assign them to slots lower than the breaking slot. // Otherwise, just ignore the instruction. @@ -932,7 +932,7 @@ ChooseOneGroup(SchedulingManager& S) { assert(S.schedPrio.getNumReady() > 0 - && "Don't get here without ready instructions."); + && "Don't get here without ready instructions."); CycleCount_t firstCycle = S.getTime(); DelaySlotInfo* getDelaySlotInfo = NULL; @@ -1022,9 +1022,9 @@ static bool NodeCanFillDelaySlot(const SchedulingManager& S, - const SchedGraphNode* node, - const SchedGraphNode* brNode, - bool nodeIsPredecessor) + const SchedGraphNode* node, + const SchedGraphNode* brNode, + bool nodeIsPredecessor) { assert(! node->isDummyNode()); @@ -1042,8 +1042,8 @@ for (SchedGraphNode::const_iterator EI = node->beginInEdges(); EI != node->endInEdges(); ++EI) if (! ((SchedGraphNode*)(*EI)->getSrc())->isDummyNode() - && mii.isLoad(((SchedGraphNode*)(*EI)->getSrc())->getOpcode()) - && (*EI)->getDepType() == SchedGraphEdge::CtrlDep) + && mii.isLoad(((SchedGraphNode*)(*EI)->getSrc())->getOpcode()) + && (*EI)->getDepType() == SchedGraphEdge::CtrlDep) return false; // Finally, if the instruction precedes the branch, we make sure the @@ -1072,10 +1072,10 @@ static void MarkNodeForDelaySlot(SchedulingManager& S, - SchedGraph* graph, - SchedGraphNode* node, - const SchedGraphNode* brNode, - bool nodeIsPredecessor) + SchedGraph* graph, + SchedGraphNode* node, + const SchedGraphNode* brNode, + bool nodeIsPredecessor) { if (nodeIsPredecessor) { // If node is in the same basic block (i.e., precedes brNode), @@ -1115,8 +1115,8 @@ for (sg_pred_iterator P = pred_begin(brNode); P != pred_end(brNode) && sdelayNodeVec.size() < ndelays; ++P) if (! (*P)->isDummyNode() && - ! mii.isNop((*P)->getOpcode()) && - NodeCanFillDelaySlot(S, *P, brNode, /*pred*/ true)) + ! mii.isNop((*P)->getOpcode()) && + NodeCanFillDelaySlot(S, *P, brNode, /*pred*/ true)) { if (mii.maxLatency((*P)->getOpcode()) > 1) mdelayNodeVec.push_back(*P); @@ -1198,7 +1198,7 @@ sdelayNodeVec.push_back(graph->getGraphNodeForInstr(MBBI)); else { nopNodeVec.push_back(graph->getGraphNodeForInstr(MBBI)); - + //remove the MI from the Machine Code For Instruction const TerminatorInst *TI = MBB.getBasicBlock()->getTerminator(); MachineCodeForInstruction& llvmMvec = @@ -1241,7 +1241,7 @@ // static void ChooseInstructionsForDelaySlots(SchedulingManager& S, MachineBasicBlock &MBB, - SchedGraph *graph) + SchedGraph *graph) { const TargetInstrInfo& mii = S.getInstrInfo(); @@ -1301,7 +1301,7 @@ { assert(delayedNodeSlotNum < S.nslots && "Illegal slot for branch"); assert(S.isched.getInstr(delayedNodeSlotNum, delayedNodeCycle) == NULL - && "Slot for branch should be empty"); + && "Slot for branch should be empty"); unsigned int nextSlot = delayedNodeSlotNum; CycleCount_t nextTime = delayedNodeCycle; @@ -1350,7 +1350,7 @@ nextTime++; } } while (S.isched.getInstr(nextSlot, nextTime) != NULL); - + S.scheduleInstr(delayNodeVec[i], nextSlot, nextTime); break; } @@ -1364,7 +1364,7 @@ // static inline bool ConflictsWithChoices(const SchedulingManager& S, - MachineOpCode opCode) + MachineOpCode opCode) { // Check if the instruction must issue by itself, and some feasible // choices have already been made for this cycle @@ -1394,8 +1394,8 @@ static inline bool ViolatesMinimumGap(const SchedulingManager& S, - MachineOpCode opCode, - const CycleCount_t inCycle) + MachineOpCode opCode, + const CycleCount_t inCycle) { return (inCycle < S.getEarliestStartTimeForOp(opCode)); } @@ -1411,7 +1411,7 @@ bool instrIsFeasible(const SchedulingManager& S, - MachineOpCode opCode) + MachineOpCode opCode) { // skip the instruction if it cannot be issued due to issue restrictions // caused by previously issued instructions @@ -1457,7 +1457,7 @@ bool InstructionSchedulingWithSSA::runOnFunction(Function &F) { - SchedGraphSet graphSet(&F, target); + SchedGraphSet graphSet(&F, target); if (SchedDebugLevel >= Sched_PrintSchedGraphs) { std::cerr << "\n*** SCHEDULING GRAPHS FOR INSTRUCTION SCHEDULING\n"; Index: llvm/lib/Target/SparcV9/InstrSched/SchedGraph.cpp diff -u llvm/lib/Target/SparcV9/InstrSched/SchedGraph.cpp:1.69 llvm/lib/Target/SparcV9/InstrSched/SchedGraph.cpp:1.70 --- llvm/lib/Target/SparcV9/InstrSched/SchedGraph.cpp:1.69 Thu Apr 21 18:27:12 2005 +++ llvm/lib/Target/SparcV9/InstrSched/SchedGraph.cpp Wed Jul 27 00:53:43 2005 @@ -72,12 +72,12 @@ // Method: SchedGraphNode Destructor // // Description: -// Free memory allocated by the SchedGraphNode object. +// Free memory allocated by the SchedGraphNode object. // // Notes: -// Do not delete the edges here. The base class will take care of that. -// Only handle subclass specific stuff here (where currently there is -// none). +// Do not delete the edges here. The base class will take care of that. +// Only handle subclass specific stuff here (where currently there is +// none). // SchedGraphNode::~SchedGraphNode() { } @@ -94,11 +94,11 @@ // Method: SchedGraph Destructor // // Description: -// This method deletes memory allocated by the SchedGraph object. +// This method deletes memory allocated by the SchedGraph object. // // Notes: -// Do not delete the graphRoot or graphLeaf here. The base class handles -// that bit of work. +// Do not delete the graphRoot or graphLeaf here. The base class handles +// that bit of work. // SchedGraph::~SchedGraph() { for (const_iterator I = begin(); I != end(); ++I) @@ -139,7 +139,7 @@ void SchedGraph::addCDEdges(const TerminatorInst* term, - const TargetMachine& target) { + const TargetMachine& target) { const TargetInstrInfo& mii = *target.getInstrInfo(); MachineCodeForInstruction &termMvec = MachineCodeForInstruction::get(term); @@ -150,7 +150,7 @@ ! mii.isReturn(termMvec[first]->getOpcode())) ++first; assert(first < termMvec.size() && - "No branch instructions for terminator? Ok, but weird!"); + "No branch instructions for terminator? Ok, but weird!"); if (first == termMvec.size()) return; @@ -171,7 +171,7 @@ assert(brNode && "No node for instr generated for branch/ret?"); (void) new SchedGraphEdge(brNode, toNode, SchedGraphEdge::CtrlDep, SchedGraphEdge::NonDataDep, 0); - break; // only one incoming edge is enough + break; // only one incoming edge is enough } } @@ -194,7 +194,7 @@ SchedGraphNode* fromNode = getGraphNodeForInstr(I); if (fromNode == NULL) - continue; // dummy instruction, e.g., PHI + continue; // dummy instruction, e.g., PHI (void) new SchedGraphEdge(fromNode, firstBrNode, SchedGraphEdge::CtrlDep, @@ -241,7 +241,7 @@ // latency does not otherwise matter (true dependences enforce that). // void SchedGraph::addMemEdges(const std::vector& memNodeVec, - const TargetMachine& target) { + const TargetMachine& target) { const TargetInstrInfo& mii = *target.getInstrInfo(); // Instructions in memNodeVec are in execution order within the basic block, @@ -273,7 +273,7 @@ // like with control dependences. // void SchedGraph::addCallDepEdges(const std::vector& callDepNodeVec, - const TargetMachine& target) { + const TargetMachine& target) { const TargetInstrInfo& mii = *target.getInstrInfo(); // Instructions in memNodeVec are in execution order within the basic block, @@ -283,15 +283,15 @@ if (mii.isCall(callDepNodeVec[ic]->getOpcode())) { // Add SG_CALL_REF edges from all preds to this instruction. for (unsigned jc=0; jc < ic; jc++) - (void) new SchedGraphEdge(callDepNodeVec[jc], callDepNodeVec[ic], - SchedGraphEdge::MachineRegister, - MachineIntRegsRID, 0); + (void) new SchedGraphEdge(callDepNodeVec[jc], callDepNodeVec[ic], + SchedGraphEdge::MachineRegister, + MachineIntRegsRID, 0); // And do the same from this instruction to all successors. for (unsigned jc=ic+1; jc < NC; jc++) - (void) new SchedGraphEdge(callDepNodeVec[ic], callDepNodeVec[jc], - SchedGraphEdge::MachineRegister, - MachineIntRegsRID, 0); + (void) new SchedGraphEdge(callDepNodeVec[ic], callDepNodeVec[jc], + SchedGraphEdge::MachineRegister, + MachineIntRegsRID, 0); } #ifdef CALL_DEP_NODE_VEC_CANNOT_WORK @@ -331,7 +331,7 @@ void SchedGraph::addMachineRegEdges(RegToRefVecMap& regToRefVecMap, - const TargetMachine& target) { + const TargetMachine& target) { // This code assumes that two registers with different numbers are // not aliased! // @@ -365,7 +365,7 @@ new SchedGraphEdge(prevNode, node, regNum, SchedGraphEdge::AntiDep); } - + if (prevIsDef) if (!isDef || isDefAndUse) new SchedGraphEdge(prevNode, node, regNum, @@ -382,11 +382,11 @@ // We do not consider other uses because we are not building use-use deps. // void SchedGraph::addEdgesForValue(SchedGraphNode* refNode, - const RefVec& defVec, - const Value* defValue, - bool refNodeIsDef, - bool refNodeIsUse, - const TargetMachine& target) { + const RefVec& defVec, + const Value* defValue, + bool refNodeIsDef, + bool refNodeIsUse, + const TargetMachine& target) { // Add true or output dep edges from all def nodes before refNode in BB. // Add anti or output dep edges to all def nodes after refNode. for (RefVec::const_iterator I=defVec.begin(), E=defVec.end(); I != E; ++I) { @@ -415,8 +415,8 @@ void SchedGraph::addEdgesForInstruction(const MachineInstr& MI, - const ValueToDefVecMap& valueToDefVecMap, - const TargetMachine& target) { + const ValueToDefVecMap& valueToDefVecMap, + const TargetMachine& target) { SchedGraphNode* node = getGraphNodeForInstr(&MI); if (node == NULL) return; @@ -443,7 +443,7 @@ case MachineOperand::MO_UnextendedImmed: case MachineOperand::MO_PCRelativeDisp: case MachineOperand::MO_ConstantPoolIndex: - break; // nothing to do for immediate fields + break; // nothing to do for immediate fields default: assert(0 && "Unknown machine operand type in SchedGraph builder"); @@ -468,11 +468,11 @@ void SchedGraph::findDefUseInfoAtInstr(const TargetMachine& target, - SchedGraphNode* node, - std::vector& memNodeVec, - std::vector& callDepNodeVec, - RegToRefVecMap& regToRefVecMap, - ValueToDefVecMap& valueToDefVecMap) { + SchedGraphNode* node, + std::vector& memNodeVec, + std::vector& callDepNodeVec, + RegToRefVecMap& regToRefVecMap, + ValueToDefVecMap& valueToDefVecMap) { const TargetInstrInfo& mii = *target.getInstrInfo(); MachineOpCode opCode = node->getOpcode(); @@ -550,11 +550,11 @@ void SchedGraph::buildNodesForBB(const TargetMachine& target, - MachineBasicBlock& MBB, - std::vector& memNodeVec, - std::vector& callDepNodeVec, - RegToRefVecMap& regToRefVecMap, - ValueToDefVecMap& valueToDefVecMap) { + MachineBasicBlock& MBB, + std::vector& memNodeVec, + std::vector& callDepNodeVec, + RegToRefVecMap& regToRefVecMap, + ValueToDefVecMap& valueToDefVecMap) { const TargetInstrInfo& mii = *target.getInstrInfo(); // Build graph nodes for each VM instruction and gather def/use info. @@ -646,7 +646,7 @@ this->addMachineRegEdges(regToRefVecMap, target); // Finally, add edges from the dummy root and to dummy leaf - this->addDummyEdges(); + this->addDummyEdges(); } @@ -654,7 +654,7 @@ // class SchedGraphSet // SchedGraphSet::SchedGraphSet(const Function* _function, - const TargetMachine& target) : + const TargetMachine& target) : function(_function) { buildGraphsForMethod(function, target); } @@ -679,7 +679,7 @@ void SchedGraphSet::buildGraphsForMethod(const Function *F, - const TargetMachine& target) { + const TargetMachine& target) { MachineFunction &MF = MachineFunction::get(F); for (MachineFunction::iterator I = MF.begin(), E = MF.end(); I != E; ++I) addGraph(new SchedGraph(*I, target)); @@ -691,13 +691,13 @@ << sink->getNodeId() << "] : "; switch(depType) { - case SchedGraphEdge::CtrlDep: + case SchedGraphEdge::CtrlDep: os<< "Control Dep"; break; case SchedGraphEdge::ValueDep: os<< "Reg Value " << *val; break; - case SchedGraphEdge::MemoryDep: + case SchedGraphEdge::MemoryDep: os<< "Memory Dep"; break; case SchedGraphEdge::MachineRegister: Index: llvm/lib/Target/SparcV9/InstrSched/SchedGraph.h diff -u llvm/lib/Target/SparcV9/InstrSched/SchedGraph.h:1.41 llvm/lib/Target/SparcV9/InstrSched/SchedGraph.h:1.42 --- llvm/lib/Target/SparcV9/InstrSched/SchedGraph.h:1.41 Thu Apr 21 18:27:12 2005 +++ llvm/lib/Target/SparcV9/InstrSched/SchedGraph.h Wed Jul 27 00:53:43 2005 @@ -38,11 +38,11 @@ SchedGraphNode(unsigned nodeId, MachineBasicBlock *mbb, int indexInBB, - const TargetMachine& Target); + const TargetMachine& Target); ~SchedGraphNode(); - friend class SchedGraph; // give access for ctor and dtor - friend class SchedGraphEdge; // give access for adding edges + friend class SchedGraph; // give access for ctor and dtor + friend class SchedGraphEdge; // give access for adding edges public: @@ -95,10 +95,10 @@ } private: - friend class SchedGraphSet; // give access to ctor + friend class SchedGraphSet; // give access to ctor - inline void noteGraphNodeForInstr (const MachineInstr* minstr, - SchedGraphNode* node) { + inline void noteGraphNodeForInstr (const MachineInstr* minstr, + SchedGraphNode* node) { assert((*this)[minstr] == NULL); (*this)[minstr] = node; } @@ -109,41 +109,41 @@ void buildGraph(const TargetMachine& target); void buildNodesForBB(const TargetMachine& target,MachineBasicBlock &MBB, - std::vector& memNV, - std::vector& callNV, - RegToRefVecMap& regToRefVecMap, - ValueToDefVecMap& valueToDefVecMap); + std::vector& memNV, + std::vector& callNV, + RegToRefVecMap& regToRefVecMap, + ValueToDefVecMap& valueToDefVecMap); void findDefUseInfoAtInstr(const TargetMachine& target, SchedGraphNode* node, - std::vector& memNV, - std::vector& callNV, - RegToRefVecMap& regToRefVecMap, - ValueToDefVecMap& valueToDefVecMap); + std::vector& memNV, + std::vector& callNV, + RegToRefVecMap& regToRefVecMap, + ValueToDefVecMap& valueToDefVecMap); void addEdgesForInstruction(const MachineInstr& minstr, - const ValueToDefVecMap& valueToDefVecMap, - const TargetMachine& target); + const ValueToDefVecMap& valueToDefVecMap, + const TargetMachine& target); void addCDEdges(const TerminatorInst* term, const TargetMachine& target); void addMemEdges(const std::vector& memNod, - const TargetMachine& target); + const TargetMachine& target); void addCallCCEdges(const std::vector& memNod, - MachineBasicBlock& bbMvec, - const TargetMachine& target); + MachineBasicBlock& bbMvec, + const TargetMachine& target); void addCallDepEdges(const std::vector& callNV, - const TargetMachine& target); + const TargetMachine& target); void addMachineRegEdges(RegToRefVecMap& regToRefVecMap, - const TargetMachine& target); + const TargetMachine& target); void addEdgesForValue(SchedGraphNode* refNode, const RefVec& defVec, - const Value* defValue, bool refNodeIsDef, - bool refNodeIsDefAndUse, - const TargetMachine& target); + const Value* defValue, bool refNodeIsDef, + bool refNodeIsDefAndUse, + const TargetMachine& target); void addDummyEdges(); Index: llvm/lib/Target/SparcV9/InstrSched/SchedGraphCommon.cpp diff -u llvm/lib/Target/SparcV9/InstrSched/SchedGraphCommon.cpp:1.9 llvm/lib/Target/SparcV9/InstrSched/SchedGraphCommon.cpp:1.10 --- llvm/lib/Target/SparcV9/InstrSched/SchedGraphCommon.cpp:1.9 Thu Apr 21 18:27:12 2005 +++ llvm/lib/Target/SparcV9/InstrSched/SchedGraphCommon.cpp Wed Jul 27 00:53:43 2005 @@ -25,10 +25,10 @@ // class SchedGraphEdge // SchedGraphEdge::SchedGraphEdge(SchedGraphNodeCommon* _src, - SchedGraphNodeCommon* _sink, - SchedGraphEdgeDepType _depType, - unsigned int _depOrderType, - int _minDelay) + SchedGraphNodeCommon* _sink, + SchedGraphEdgeDepType _depType, + unsigned int _depOrderType, + int _minDelay) : src(_src), sink(_sink), depType(_depType), depOrderType(_depOrderType), minDelay((_minDelay >= 0)? _minDelay : _src->getLatency()), val(NULL) { @@ -39,10 +39,10 @@ } SchedGraphEdge::SchedGraphEdge(SchedGraphNodeCommon* _src, - SchedGraphNodeCommon* _sink, - const Value* _val, - unsigned int _depOrderType, - int _minDelay) + SchedGraphNodeCommon* _sink, + const Value* _val, + unsigned int _depOrderType, + int _minDelay) : src(_src), sink(_sink), depType(ValueDep), depOrderType(_depOrderType), minDelay((_minDelay >= 0)? _minDelay : _src->getLatency()), val(_val) { iteDiff=0; @@ -52,10 +52,10 @@ } SchedGraphEdge::SchedGraphEdge(SchedGraphNodeCommon* _src, - SchedGraphNodeCommon* _sink, - unsigned int _regNum, - unsigned int _depOrderType, - int _minDelay) + SchedGraphNodeCommon* _sink, + unsigned int _regNum, + unsigned int _depOrderType, + int _minDelay) : src(_src), sink(_sink), depType(MachineRegister), depOrderType(_depOrderType), minDelay((_minDelay >= 0)? _minDelay : _src->getLatency()), @@ -67,9 +67,9 @@ } SchedGraphEdge::SchedGraphEdge(SchedGraphNodeCommon* _src, - SchedGraphNodeCommon* _sink, - ResourceId _resourceId, - int _minDelay) + SchedGraphNodeCommon* _sink, + ResourceId _resourceId, + int _minDelay) : src(_src), sink(_sink), depType(MachineResource), depOrderType(NonDataDep), minDelay((_minDelay >= 0)? _minDelay : _src->getLatency()), resourceId(_resourceId) { @@ -125,7 +125,7 @@ void SchedGraphCommon::eraseIncomingEdges(SchedGraphNodeCommon* node, - bool addDummyEdges) { + bool addDummyEdges) { // Delete and disconnect all in-edges for the node for (SchedGraphNodeCommon::iterator I = node->beginInEdges(); I != node->endInEdges(); ++I) { @@ -134,13 +134,13 @@ delete *I; if (addDummyEdges && srcNode != getRoot() && - srcNode->beginOutEdges() == srcNode->endOutEdges()) { + srcNode->beginOutEdges() == srcNode->endOutEdges()) { // srcNode has no more out edges, so add an edge to dummy EXIT node assert(node != getLeaf() && "Adding edge that was just removed?"); (void) new SchedGraphEdge(srcNode, getLeaf(), - SchedGraphEdge::CtrlDep, - SchedGraphEdge::NonDataDep, 0); + SchedGraphEdge::CtrlDep, + SchedGraphEdge::NonDataDep, 0); } } @@ -148,7 +148,7 @@ } void SchedGraphCommon::eraseOutgoingEdges(SchedGraphNodeCommon* node, - bool addDummyEdges) { + bool addDummyEdges) { // Delete and disconnect all out-edges for the node for (SchedGraphNodeCommon::iterator I = node->beginOutEdges(); I != node->endOutEdges(); ++I) { @@ -157,14 +157,14 @@ delete *I; if (addDummyEdges && - sinkNode != getLeaf() && - sinkNode->beginInEdges() == sinkNode->endInEdges()) { + sinkNode != getLeaf() && + sinkNode->beginInEdges() == sinkNode->endInEdges()) { //sinkNode has no more in edges, so add an edge from dummy ENTRY node assert(node != getRoot() && "Adding edge that was just removed?"); (void) new SchedGraphEdge(getRoot(), sinkNode, - SchedGraphEdge::CtrlDep, - SchedGraphEdge::NonDataDep, 0); + SchedGraphEdge::CtrlDep, + SchedGraphEdge::NonDataDep, 0); } } @@ -172,9 +172,9 @@ } void SchedGraphCommon::eraseIncidentEdges(SchedGraphNodeCommon* node, - bool addDummyEdges) { - this->eraseIncomingEdges(node, addDummyEdges); - this->eraseOutgoingEdges(node, addDummyEdges); + bool addDummyEdges) { + this->eraseIncomingEdges(node, addDummyEdges); + this->eraseOutgoingEdges(node, addDummyEdges); } } // End llvm namespace Index: llvm/lib/Target/SparcV9/InstrSched/SchedPriorities.cpp diff -u llvm/lib/Target/SparcV9/InstrSched/SchedPriorities.cpp:1.37 llvm/lib/Target/SparcV9/InstrSched/SchedPriorities.cpp:1.38 --- llvm/lib/Target/SparcV9/InstrSched/SchedPriorities.cpp:1.37 Thu Apr 21 18:27:12 2005 +++ llvm/lib/Target/SparcV9/InstrSched/SchedPriorities.cpp Wed Jul 27 00:53:43 2005 @@ -28,7 +28,7 @@ std::ostream &operator<<(std::ostream &os, const NodeDelayPair* nd) { return os << "Delay for node " << nd->node->getNodeId() - << " = " << (long)nd->delay << "\n"; + << " = " << (long)nd->delay << "\n"; } @@ -118,7 +118,7 @@ void SchedPriorities::issuedReadyNodeAt(CycleCount_t curTime, - const SchedGraphNode* node) { + const SchedGraphNode* node) { candsAsHeap.removeNode(node); candsAsSet.erase(node); mcands.clear(); // ensure reset choices is called before any more choices @@ -156,8 +156,8 @@ inline int SchedPriorities::chooseByRule1(std::vector& mcands) { - return (mcands.size() == 1)? 0 // only one choice exists so take it - : -1; // -1 indicates multiple choices + return (mcands.size() == 1)? 0 // only one choice exists so take it + : -1; // -1 indicates multiple choices } inline int @@ -165,7 +165,7 @@ assert(mcands.size() >= 1 && "Should have at least one candidate here."); for (unsigned i=0, N = mcands.size(); i < N; i++) if (instructionHasLastUse(methodLiveVarInfo, - candsAsHeap.getNode(mcands[i]))) + candsAsHeap.getNode(mcands[i]))) return i; return -1; } @@ -173,7 +173,7 @@ inline int SchedPriorities::chooseByRule3(std::vector& mcands) { assert(mcands.size() >= 1 && "Should have at least one candidate here."); - int maxUses = candsAsHeap.getNode(mcands[0])->getNumOutEdges(); + int maxUses = candsAsHeap.getNode(mcands[0])->getNumOutEdges(); int indexWithMaxUses = 0; for (unsigned i=1, N = mcands.size(); i < N; i++) { int numUses = candsAsHeap.getNode(mcands[i])->getNumOutEdges(); @@ -187,7 +187,7 @@ const SchedGraphNode* SchedPriorities::getNextHighest(const SchedulingManager& S, - CycleCount_t curTime) { + CycleCount_t curTime) { int nextIdx = -1; const SchedGraphNode* nextChoice = NULL; @@ -195,7 +195,7 @@ findSetWithMaxDelay(mcands, S); while (nextIdx < 0 && mcands.size() > 0) { - nextIdx = chooseByRule1(mcands); // rule 1 + nextIdx = chooseByRule1(mcands); // rule 1 if (nextIdx == -1) nextIdx = chooseByRule2(mcands); // rule 2 @@ -204,7 +204,7 @@ nextIdx = chooseByRule3(mcands); // rule 3 if (nextIdx == -1) - nextIdx = 0; // default to first choice by delays + nextIdx = 0; // default to first choice by delays // We have found the next best candidate. Check if it ready in // the current cycle, and if it is feasible. @@ -231,7 +231,7 @@ void SchedPriorities::findSetWithMaxDelay(std::vector& mcands, - const SchedulingManager& S) + const SchedulingManager& S) { if (mcands.size() == 0 && nextToTry != candsAsHeap.end()) { // out of choices at current maximum delay; @@ -239,8 +239,8 @@ candIndex next = nextToTry; CycleCount_t maxDelay = candsAsHeap.getDelay(next); for (; next != candsAsHeap.end() - && candsAsHeap.getDelay(next) == maxDelay; ++next) - mcands.push_back(next); + && candsAsHeap.getDelay(next) == maxDelay; ++next) + mcands.push_back(next); nextToTry = next; @@ -258,7 +258,7 @@ bool SchedPriorities::instructionHasLastUse(FunctionLiveVarInfo &LVI, - const SchedGraphNode* graphNode) { + const SchedGraphNode* graphNode) { const MachineInstr *MI = graphNode->getMachineInstr(); hash_map::const_iterator Index: llvm/lib/Target/SparcV9/InstrSched/SchedPriorities.h diff -u llvm/lib/Target/SparcV9/InstrSched/SchedPriorities.h:1.29 llvm/lib/Target/SparcV9/InstrSched/SchedPriorities.h:1.30 --- llvm/lib/Target/SparcV9/InstrSched/SchedPriorities.h:1.29 Thu Apr 21 18:27:12 2005 +++ llvm/lib/Target/SparcV9/InstrSched/SchedPriorities.h Wed Jul 27 00:53:43 2005 @@ -84,40 +84,40 @@ inline unsigned size() const { return _size; } - const SchedGraphNode* getNode (const_iterator i) const { return (*i)->node; } - CycleCount_t getDelay(const_iterator i) const { return (*i)->delay;} + const SchedGraphNode* getNode (const_iterator i) const { return (*i)->node; } + CycleCount_t getDelay(const_iterator i) const { return (*i)->delay;} - inline void makeHeap() { + inline void makeHeap() { // make_heap(begin(), end(), NDPLessThan); } - inline iterator findNode(const SchedGraphNode* node) { + inline iterator findNode(const SchedGraphNode* node) { for (iterator I=begin(); I != end(); ++I) if (getNode(I) == node) - return I; + return I; return end(); } - inline void removeNode (const SchedGraphNode* node) { + inline void removeNode (const SchedGraphNode* node) { iterator ndpPtr = findNode(node); if (ndpPtr != end()) { - delete *ndpPtr; - erase(ndpPtr); - --_size; + delete *ndpPtr; + erase(ndpPtr); + --_size; } }; - void insert(const SchedGraphNode* node, CycleCount_t delay) { + void insert(const SchedGraphNode* node, CycleCount_t delay) { NodeDelayPair* ndp = new NodeDelayPair(node, delay); if (_size == 0 || front()->delay < delay) push_front(ndp); else { - iterator I=begin(); - for ( ; I != end() && getDelay(I) >= delay; ++I) - ; - std::list::insert(I, ndp); + iterator I=begin(); + for ( ; I != end() && getDelay(I) >= delay; ++I) + ; + std::list::insert(I, ndp); } _size++; } @@ -135,25 +135,25 @@ // This must be called before scheduling begins. - void initialize (); + void initialize (); - CycleCount_t getTime () const { return curTime; } - CycleCount_t getEarliestReadyTime () const { return earliestReadyTime; } - unsigned getNumReady () const { return candsAsHeap.size(); } - bool nodeIsReady (const SchedGraphNode* node) const { + CycleCount_t getTime () const { return curTime; } + CycleCount_t getEarliestReadyTime () const { return earliestReadyTime; } + unsigned getNumReady () const { return candsAsHeap.size(); } + bool nodeIsReady (const SchedGraphNode* node) const { return (candsAsSet.find(node) != candsAsSet.end()); } - void issuedReadyNodeAt (CycleCount_t curTime, - const SchedGraphNode* node); + void issuedReadyNodeAt (CycleCount_t curTime, + const SchedGraphNode* node); - void insertReady (const SchedGraphNode* node); + void insertReady (const SchedGraphNode* node); - void updateTime (CycleCount_t /*unused*/); + void updateTime (CycleCount_t /*unused*/); - const SchedGraphNode* getNextHighest (const SchedulingManager& S, - CycleCount_t curTime); - // choose next highest priority instr + const SchedGraphNode* getNextHighest (const SchedulingManager& S, + CycleCount_t curTime); + // choose next highest priority instr private: typedef NodeHeap::iterator candIndex; @@ -167,30 +167,30 @@ std::vector nodeEarliestUseVec; std::vector earliestReadyTimeForNode; CycleCount_t earliestReadyTime; - NodeHeap candsAsHeap; // candidate nodes, ready to go + NodeHeap candsAsHeap; // candidate nodes, ready to go hash_set candsAsSet; //same entries as candsAsHeap, - // but as set for fast lookup + // but as set for fast lookup std::vector mcands; // holds pointers into cands - candIndex nextToTry; // next cand after the last - // one tried in this cycle + candIndex nextToTry; // next cand after the last + // one tried in this cycle - int chooseByRule1 (std::vector& mcands); - int chooseByRule2 (std::vector& mcands); - int chooseByRule3 (std::vector& mcands); + int chooseByRule1 (std::vector& mcands); + int chooseByRule2 (std::vector& mcands); + int chooseByRule3 (std::vector& mcands); - void findSetWithMaxDelay (std::vector& mcands, - const SchedulingManager& S); + void findSetWithMaxDelay (std::vector& mcands, + const SchedulingManager& S); - void computeDelays (const SchedGraph* graph); + void computeDelays (const SchedGraph* graph); - void initializeReadyHeap (const SchedGraph* graph); + void initializeReadyHeap (const SchedGraph* graph); - bool instructionHasLastUse (FunctionLiveVarInfo& LVI, - const SchedGraphNode* graphNode); + bool instructionHasLastUse (FunctionLiveVarInfo& LVI, + const SchedGraphNode* graphNode); // NOTE: The next two return references to the actual vector entries. // Use the following two if you don't need to modify the value. - CycleCount_t& getNodeDelayRef (const SchedGraphNode* node) { + CycleCount_t& getNodeDelayRef (const SchedGraphNode* node) { assert(node->getNodeId() < nodeDelayVec.size()); return nodeDelayVec[node->getNodeId()]; } From jeffc at jolt-lang.org Wed Jul 27 00:54:01 2005 From: jeffc at jolt-lang.org (Jeff Cohen) Date: Wed, 27 Jul 2005 00:54:01 -0500 Subject: [llvm-commits] CVS: llvm/lib/Target/SparcV9/EmitBytecodeToAssembly.cpp MachineFunctionInfo.cpp MachineFunctionInfo.h MappingInfo.cpp MappingInfo.h SparcV9BurgISel.cpp SparcV9FrameInfo.h SparcV9InstrForest.h SparcV9Internals.h SparcV9PrologEpilogInserter.cpp SparcV9RegClassInfo.cpp SparcV9RegClassInfo.h SparcV9RegInfo.cpp SparcV9RegInfo.h SparcV9SchedInfo.cpp SparcV9TargetMachine.cpp SparcV9TmpInstr.cpp Message-ID: <200507270554.AAA12914@zion.cs.uiuc.edu> Changes in directory llvm/lib/Target/SparcV9: EmitBytecodeToAssembly.cpp updated: 1.16 -> 1.17 MachineFunctionInfo.cpp updated: 1.3 -> 1.4 MachineFunctionInfo.h updated: 1.10 -> 1.11 MappingInfo.cpp updated: 1.22 -> 1.23 MappingInfo.h updated: 1.11 -> 1.12 SparcV9BurgISel.cpp updated: 1.22 -> 1.23 SparcV9FrameInfo.h updated: 1.9 -> 1.10 SparcV9InstrForest.h updated: 1.3 -> 1.4 SparcV9Internals.h updated: 1.121 -> 1.122 SparcV9PrologEpilogInserter.cpp updated: 1.48 -> 1.49 SparcV9RegClassInfo.cpp updated: 1.41 -> 1.42 SparcV9RegClassInfo.h updated: 1.30 -> 1.31 SparcV9RegInfo.cpp updated: 1.141 -> 1.142 SparcV9RegInfo.h updated: 1.19 -> 1.20 SparcV9SchedInfo.cpp updated: 1.14 -> 1.15 SparcV9TargetMachine.cpp updated: 1.139 -> 1.140 SparcV9TmpInstr.cpp updated: 1.5 -> 1.6 --- Log message: Eliminate tabs and trailing spaces. --- Diffs of the changes: (+334 -334) EmitBytecodeToAssembly.cpp | 4 MachineFunctionInfo.cpp | 10 - MachineFunctionInfo.h | 14 +- MappingInfo.cpp | 4 MappingInfo.h | 6 SparcV9BurgISel.cpp | 254 ++++++++++++++++++++-------------------- SparcV9FrameInfo.h | 2 SparcV9InstrForest.h | 88 ++++++------- SparcV9Internals.h | 24 +-- SparcV9PrologEpilogInserter.cpp | 4 SparcV9RegClassInfo.cpp | 24 +-- SparcV9RegClassInfo.h | 2 SparcV9RegInfo.cpp | 62 ++++----- SparcV9RegInfo.h | 6 SparcV9SchedInfo.cpp | 158 ++++++++++++------------ SparcV9TargetMachine.cpp | 4 SparcV9TmpInstr.cpp | 2 17 files changed, 334 insertions(+), 334 deletions(-) Index: llvm/lib/Target/SparcV9/EmitBytecodeToAssembly.cpp diff -u llvm/lib/Target/SparcV9/EmitBytecodeToAssembly.cpp:1.16 llvm/lib/Target/SparcV9/EmitBytecodeToAssembly.cpp:1.17 --- llvm/lib/Target/SparcV9/EmitBytecodeToAssembly.cpp:1.16 Thu Apr 21 18:25:42 2005 +++ llvm/lib/Target/SparcV9/EmitBytecodeToAssembly.cpp Wed Jul 27 00:53:43 2005 @@ -62,7 +62,7 @@ }; static void writePrologue (std::ostream &Out, const std::string &comment, - const std::string &symName) { + const std::string &symName) { // Prologue: // Output a comment describing the object. Out << "!" << comment << "\n"; @@ -80,7 +80,7 @@ Out << ".end_" << symName << ":\n"; // Output size directive giving the size of the object: Out << "\t.size " << symName << ", .end_" << symName << "-" << symName - << "\n"; + << "\n"; } // SparcV9BytecodeWriter - Write bytecode out to a stream that is sparc'ified Index: llvm/lib/Target/SparcV9/MachineFunctionInfo.cpp diff -u llvm/lib/Target/SparcV9/MachineFunctionInfo.cpp:1.3 llvm/lib/Target/SparcV9/MachineFunctionInfo.cpp:1.4 --- llvm/lib/Target/SparcV9/MachineFunctionInfo.cpp:1.3 Thu Apr 21 18:25:42 2005 +++ llvm/lib/Target/SparcV9/MachineFunctionInfo.cpp Wed Jul 27 00:53:43 2005 @@ -71,15 +71,15 @@ void SparcV9FunctionInfo::CalculateArgSize() { maxOptionalArgsSize = ComputeMaxOptionalArgsSize(MF.getTarget(), - MF.getFunction(), + MF.getFunction(), maxOptionalNumArgs); staticStackSize = maxOptionalArgsSize + 176; } int SparcV9FunctionInfo::computeOffsetforLocalVar(const Value* val, - unsigned &getPaddedSize, - unsigned sizeToUse) + unsigned &getPaddedSize, + unsigned sizeToUse) { if (sizeToUse == 0) { // All integer types smaller than ints promote to 4 byte integers. @@ -92,7 +92,7 @@ bool growUp; int firstOffset = MF.getTarget().getFrameInfo()->getFirstAutomaticVarOffset(MF, - growUp); + growUp); int offset = growUp? firstOffset + getAutomaticVarsSize() : firstOffset - (getAutomaticVarsSize() + sizeToUse); @@ -158,7 +158,7 @@ : firstOffset - (currentTmpValuesSize + size); int aligned = MF.getTarget().getFrameInfo()->adjustAlignment(offset, growUp, - align); + align); size += abs(aligned - offset); // include alignment padding in size incrementTmpAreaSize(size); // update "current" size of tmp area Index: llvm/lib/Target/SparcV9/MachineFunctionInfo.h diff -u llvm/lib/Target/SparcV9/MachineFunctionInfo.h:1.10 llvm/lib/Target/SparcV9/MachineFunctionInfo.h:1.11 --- llvm/lib/Target/SparcV9/MachineFunctionInfo.h:1.10 Thu Apr 21 18:25:42 2005 +++ llvm/lib/Target/SparcV9/MachineFunctionInfo.h Wed Jul 27 00:53:43 2005 @@ -33,13 +33,13 @@ hash_set constantsForConstPool; hash_map offsets; - unsigned staticStackSize; - unsigned automaticVarsSize; - unsigned regSpillsSize; - unsigned maxOptionalArgsSize; - unsigned maxOptionalNumArgs; - unsigned currentTmpValuesSize; - unsigned maxTmpValuesSize; + unsigned staticStackSize; + unsigned automaticVarsSize; + unsigned regSpillsSize; + unsigned maxOptionalArgsSize; + unsigned maxOptionalNumArgs; + unsigned currentTmpValuesSize; + unsigned maxTmpValuesSize; bool compiledAsLeaf; bool spillsAreaFrozen; bool automaticVarsAreaFrozen; Index: llvm/lib/Target/SparcV9/MappingInfo.cpp diff -u llvm/lib/Target/SparcV9/MappingInfo.cpp:1.22 llvm/lib/Target/SparcV9/MappingInfo.cpp:1.23 --- llvm/lib/Target/SparcV9/MappingInfo.cpp:1.22 Thu Apr 21 18:25:42 2005 +++ llvm/lib/Target/SparcV9/MappingInfo.cpp Wed Jul 27 00:53:43 2005 @@ -158,11 +158,11 @@ void MappingInfo::byteVector::dumpAssembly (std::ostream &Out) { for (iterator i = begin (), e = end (); i != e; ++i) - Out << ".byte " << (int)*i << "\n"; + Out << ".byte " << (int)*i << "\n"; } static void writePrologue (std::ostream &Out, const std::string &comment, - const std::string &symName) { + const std::string &symName) { // Prologue: // Output a comment describing the object. Out << "!" << comment << "\n"; Index: llvm/lib/Target/SparcV9/MappingInfo.h diff -u llvm/lib/Target/SparcV9/MappingInfo.h:1.11 llvm/lib/Target/SparcV9/MappingInfo.h:1.12 --- llvm/lib/Target/SparcV9/MappingInfo.h:1.11 Thu Apr 21 18:25:42 2005 +++ llvm/lib/Target/SparcV9/MappingInfo.h Wed Jul 27 00:53:43 2005 @@ -37,11 +37,11 @@ public: void outByte (unsigned char b) { bytes.push_back (b); } MappingInfo (std::string Comment, std::string SymbolPrefix, - unsigned FunctionNumber) : comment(Comment), - symbolPrefix(SymbolPrefix), functionNumber(FunctionNumber) {} + unsigned FunctionNumber) : comment(Comment), + symbolPrefix(SymbolPrefix), functionNumber(FunctionNumber) {} void dumpAssembly (std::ostream &Out); unsigned char *getBytes (unsigned &length) { - length = bytes.size(); return &bytes[0]; + length = bytes.size(); return &bytes[0]; } }; Index: llvm/lib/Target/SparcV9/SparcV9BurgISel.cpp diff -u llvm/lib/Target/SparcV9/SparcV9BurgISel.cpp:1.22 llvm/lib/Target/SparcV9/SparcV9BurgISel.cpp:1.23 --- llvm/lib/Target/SparcV9/SparcV9BurgISel.cpp:1.22 Wed Jun 22 16:04:42 2005 +++ llvm/lib/Target/SparcV9/SparcV9BurgISel.cpp Wed Jul 27 00:53:43 2005 @@ -11,7 +11,7 @@ // construct a forest of BURG instruction trees (class InstrForest) and then // uses the BURG-generated tree grammar (BURM) to find the optimal instruction // sequences for the SparcV9. -// +// //===----------------------------------------------------------------------===// #include "MachineInstrAnnot.h" @@ -157,8 +157,8 @@ RootSet treeRoots; public: - /*ctor*/ InstrForest (Function *F); - /*dtor*/ ~InstrForest (); + /*ctor*/ InstrForest (Function *F); + /*dtor*/ ~InstrForest (); /// getTreeNodeForInstr - Returns the tree node for an Instruction. /// @@ -203,18 +203,18 @@ // Distinguish special cases of some instructions such as Ret and Br // if (opLabel == Instruction::Ret && cast(I)->getReturnValue()) { - opLabel = RetValueOp; // ret(value) operation + opLabel = RetValueOp; // ret(value) operation } else if (opLabel ==Instruction::Br && !cast(I)->isUnconditional()) { - opLabel = BrCondOp; // br(cond) operation + opLabel = BrCondOp; // br(cond) operation } else if (opLabel >= Instruction::SetEQ && opLabel <= Instruction::SetGT) { - opLabel = SetCCOp; // common label for all SetCC ops + opLabel = SetCCOp; // common label for all SetCC ops } else if (opLabel == Instruction::Alloca && I->getNumOperands() > 0) { - opLabel = AllocaN; // Alloca(ptr, N) operation + opLabel = AllocaN; // Alloca(ptr, N) operation } else if (opLabel == Instruction::GetElementPtr && cast(I)->hasIndices()) { - opLabel = opLabel + 100; // getElem with index vector + opLabel = opLabel + 100; // getElem with index vector } else if (opLabel == Instruction::Xor && BinaryOperator::isNot(I)) { opLabel = (I->getType() == Type::BoolTy)? NotOp // boolean Not operator @@ -223,7 +223,7 @@ opLabel == Instruction::Xor) { // Distinguish bitwise operators from logical operators! if (I->getType() != Type::BoolTy) - opLabel = opLabel + 100; // bitwise operator + opLabel = opLabel + 100; // bitwise operator } else if (opLabel == Instruction::Cast) { const Type *ITy = I->getType(); switch(ITy->getTypeID()) @@ -310,7 +310,7 @@ inline void InstrForest::noteTreeNodeForInstr(Instruction *instr, InstructionNode *treeNode) { (*this)[instr] = treeNode; - treeRoots.push_back(treeNode); // mark node as root of a new tree + treeRoots.push_back(treeNode); // mark node as root of a new tree } inline void InstrForest::setLeftChild(InstrTreeNode *parent, @@ -369,19 +369,19 @@ // that should be considered a data value. // Check latter condition here just to simplify the next IF. bool includeAddressOperand = - (isa(operand) || isa(operand)) - && !instr->isTerminator(); + (isa(operand) || isa(operand)) + && !instr->isTerminator(); if (includeAddressOperand || isa(operand) || - isa(operand) || isa(operand)) { + isa(operand) || isa(operand)) { // This operand is a data value. // An instruction that computes the incoming value is added as a // child of the current instruction if: // the value has only a single use // AND both instructions are in the same basic block. // AND the current instruction is not a PHI (because the incoming - // value is conceptually in a predecessor block, - // even though it may be in the same static block) + // value is conceptually in a predecessor block, + // even though it may be in the same static block) // (Note that if the value has only a single use (viz., `instr'), // the def of the value can be safely moved just before instr // and therefore it is safe to combine these two instructions.) @@ -667,7 +667,7 @@ static inline void CreateSETSWConst(int32_t C, Instruction* dest, std::vector& mvec, - MachineCodeForInstruction& mcfi, Value* val) { + MachineCodeForInstruction& mcfi, Value* val) { //TmpInstruction for intermediate values TmpInstruction *tmpReg = new TmpInstruction(mcfi, (Instruction*) val); @@ -693,7 +693,7 @@ CreateSETXConst(uint64_t C, Instruction* tmpReg, Instruction* dest, std::vector& mvec, - MachineCodeForInstruction& mcfi, Value* val) { + MachineCodeForInstruction& mcfi, Value* val) { assert(C > (unsigned int) ~0 && "Use SETUW/SETSW for 32-bit values!"); MachineInstr* MI; @@ -746,7 +746,7 @@ static inline void CreateSETXLabel(Value* val, Instruction* tmpReg, Instruction* dest, std::vector& mvec, - MachineCodeForInstruction& mcfi) { + MachineCodeForInstruction& mcfi) { assert(isa(val) && "I only know about constant values and global addresses"); @@ -1396,8 +1396,8 @@ MachineOperand::MachineOperandType ChooseRegOrImmed(Value* val, MachineOpCode opCode, const TargetMachine& target, - bool canUseImmed, unsigned int& getMachineRegNum, - int64_t& getImmedValue) { + bool canUseImmed, unsigned int& getMachineRegNum, + int64_t& getImmedValue) { getMachineRegNum = 0; getImmedValue = 0; @@ -2130,7 +2130,7 @@ // Cases worth optimizing are: // (1) Add with 0 for float or double: use an FMOV of appropriate type, - // instead of an FADD (1 vs 3 cycles). There is no integer MOV. + // instead of an FADD (1 vs 3 cycles). There is no integer MOV. if (ConstantFP *FPC = dyn_cast(constOp)) { double dval = FPC->getValue(); if (dval == 0.0) @@ -2166,7 +2166,7 @@ // Cases worth optimizing are: // (1) Sub with 0 for float or double: use an FMOV of appropriate type, - // instead of an FSUB (1 vs 3 cycles). There is no integer MOV. + // instead of an FSUB (1 vs 3 cycles). There is no integer MOV. if (ConstantFP *FPC = dyn_cast(constOp)) { double dval = FPC->getValue(); if (dval == 0.0) @@ -2324,31 +2324,31 @@ M = BuildMI(V9::ADDr,3).addReg(lval).addMReg(Zero).addRegDef(destVal); mvec.push_back(M); } else if (isPowerOf2(C, pow)) { - if(!needNeg) { + if(!needNeg) { unsigned opSize = target.getTargetData().getTypeSize(resultType); MachineOpCode opCode = (opSize <= 32)? V9::SLLr5 : V9::SLLXr6; CreateShiftInstructions(target, F, opCode, lval, NULL, pow, destVal, mvec, mcfi); - } - else { - //Create tmp instruction to hold intermeidate value, since we need - //to negate the result - tmpNeg = new TmpInstruction(mcfi, lval); - unsigned opSize = target.getTargetData().getTypeSize(resultType); - MachineOpCode opCode = (opSize <= 32)? V9::SLLr5 : V9::SLLXr6; - CreateShiftInstructions(target, F, opCode, lval, NULL, pow, - tmpNeg, mvec, mcfi); - } - + } + else { + //Create tmp instruction to hold intermeidate value, since we need + //to negate the result + tmpNeg = new TmpInstruction(mcfi, lval); + unsigned opSize = target.getTargetData().getTypeSize(resultType); + MachineOpCode opCode = (opSize <= 32)? V9::SLLr5 : V9::SLLXr6; + CreateShiftInstructions(target, F, opCode, lval, NULL, pow, + tmpNeg, mvec, mcfi); + } + } if (mvec.size() > 0 && needNeg) { - MachineInstr* M = 0; - if(tmpNeg) + MachineInstr* M = 0; + if(tmpNeg) // insert after the instr to flip the sign - M = CreateIntNegInstruction(target, tmpNeg, destVal); - else - M = CreateIntNegInstruction(target, destVal); + M = CreateIntNegInstruction(target, tmpNeg, destVal); + else + M = CreateIntNegInstruction(target, destVal); mvec.push_back(M); } } @@ -2495,13 +2495,13 @@ // sra N, 31, t1 // t1 = ~0, if N < 0, 0 else // srl t1, 32-k, t2 // t2 = 2^k - 1, if N < 0, 0 else // add t2, N, t3 // t3 = N + 2^k -1, if N < 0, N else - // sra t3, k, result // result = N / 2^k + // sra t3, k, result // result = N / 2^k // // If N is 64 bits, use: // srax N, k-1, t1 // t1 = sign bit in high k positions // srlx t1, 64-k, t2 // t2 = 2^k - 1, if N < 0, 0 else // add t2, N, t3 // t3 = N + 2^k -1, if N < 0, N else - // sra t3, k, result // result = N / 2^k + // sra t3, k, result // result = N / 2^k TmpInstruction *sraTmp, *srlTmp, *addTmp; MachineCodeForInstruction& mcfi = MachineCodeForInstruction::get(destVal); @@ -2661,8 +2661,8 @@ if (((int)paddedSize) > 8 * SparcV9FrameInfo::SizeOfEachArgOnStack || !target.getInstrInfo()->constantFitsInImmedField(V9::LDXi,offsetFromFP)) { CreateCodeForVariableSizeAlloca(target, result, tsize, - ConstantSInt::get(Type::IntTy,numElements), - getMvec); + ConstantSInt::get(Type::IntTy,numElements), + getMvec); return; } @@ -2684,8 +2684,8 @@ /// offset is not a constant or if it cannot fit in the offset field. Use /// [reg+offset] in all other cases. This assumes that all array refs are /// "lowered" to one of these forms: -/// %x = load (subarray*) ptr, constant ; single constant offset -/// %x = load (subarray*) ptr, offsetVal ; single non-constant offset +/// %x = load (subarray*) ptr, constant ; single constant offset +/// %x = load (subarray*) ptr, offsetVal ; single non-constant offset /// Generally, this should happen via strength reduction + LICM. Also, strength /// reduction should take care of using the same register for the loop index /// variable and an array index, when that is profitable. @@ -2900,7 +2900,7 @@ /// extern bool ThisIsAChainRule(int eruleno) { switch(eruleno) { - case 111: // stmt: reg + case 111: // stmt: reg case 123: case 124: case 125: @@ -2936,7 +2936,7 @@ void GetInstructionsByRule(InstructionNode* subtreeRoot, int ruleForNode, short* nts, TargetMachine &target, std::vector& mvec) { - bool checkCast = false; // initialize here to use fall-through + bool checkCast = false; // initialize here to use fall-through bool maskUnsignedResult = false; int nextRule; int forwardOperandNum = -1; @@ -2967,11 +2967,11 @@ case 1: // stmt: Ret case 2: // stmt: RetValue(reg) { // NOTE: Prepass of register allocation is responsible - // for moving return value to appropriate register. + // for moving return value to appropriate register. // Copy the return value to the required return register. // Mark the return Value as an implicit ref of the RET instr.. // Mark the return-address register as a hidden virtual reg. - // Finally put a NOP in the delay slot. + // Finally put a NOP in the delay slot. ReturnInst *returnInstr=cast(subtreeRoot->getInstruction()); Value* retVal = returnInstr->getReturnValue(); MachineCodeForInstruction& mcfi = @@ -3047,14 +3047,14 @@ break; } - case 3: // stmt: Store(reg,reg) - case 4: // stmt: Store(reg,ptrreg) + case 3: // stmt: Store(reg,reg) + case 4: // stmt: Store(reg,ptrreg) SetOperandsForMemInstr(ChooseStoreInstruction( subtreeRoot->leftChild()->getValue()->getType()), mvec, subtreeRoot, target); break; - case 5: // stmt: BrUncond + case 5: // stmt: BrUncond { BranchInst *BI = cast(subtreeRoot->getInstruction()); mvec.push_back(BuildMI(V9::BA, 1).addPCDisp(BI->getSuccessor(0))); @@ -3064,7 +3064,7 @@ break; } - case 206: // stmt: BrCond(setCCconst) + case 206: // stmt: BrCond(setCCconst) { // setCCconst => boolean was computed with `%b = setCC type reg1 const' // If the constant is ZERO, we can use the branch-on-integer-register // instructions and avoid the SUBcc instruction entirely. @@ -3111,7 +3111,7 @@ // ELSE FALL THROUGH } - case 6: // stmt: BrCond(setCC) + case 6: // stmt: BrCond(setCC) { // bool => boolean was computed with SetCC. // The branch to use depends on whether it is FP, signed, or unsigned. // If it is an integer CC, we also need to find the unique @@ -3139,7 +3139,7 @@ break; } - case 208: // stmt: BrCond(boolconst) + case 208: // stmt: BrCond(boolconst) { // boolconst => boolean is a constant; use BA to first or second label Constant* constVal = @@ -3155,7 +3155,7 @@ break; } - case 8: // stmt: BrCond(boolreg) + case 8: // stmt: BrCond(boolreg) { // boolreg => boolean is recorded in an integer register. // Use branch-on-integer-register instruction. // @@ -3175,15 +3175,15 @@ break; } - case 9: // stmt: Switch(reg) + case 9: // stmt: Switch(reg) assert(0 && "*** SWITCH instruction is not implemented yet."); break; - case 10: // reg: VRegList(reg, reg) + case 10: // reg: VRegList(reg, reg) assert(0 && "VRegList should never be the topmost non-chain rule"); break; - case 21: // bool: Not(bool,reg): Compute with a conditional-move-on-reg + case 21: // bool: Not(bool,reg): Compute with a conditional-move-on-reg { // First find the unary operand. It may be left or right, usually right. Instruction* notI = subtreeRoot->getInstruction(); Value* notArg = BinaryOperator::getNotArgument( @@ -3202,7 +3202,7 @@ break; } - case 421: // reg: BNot(reg,reg): Compute as reg = reg XOR-NOT 0 + case 421: // reg: BNot(reg,reg): Compute as reg = reg XOR-NOT 0 { // First find the unary operand. It may be left or right, usually right. Value* notArg = BinaryOperator::getNotArgument( cast(subtreeRoot->getInstruction())); @@ -3212,18 +3212,18 @@ break; } - case 322: // reg: Not(tobool, reg): + case 322: // reg: Not(tobool, reg): // Fold CAST-TO-BOOL with NOT by inverting the sense of cast-to-bool foldCase = true; // Just fall through! - case 22: // reg: ToBoolTy(reg): + case 22: // reg: ToBoolTy(reg): { Instruction* castI = subtreeRoot->getInstruction(); Value* opVal = subtreeRoot->leftChild()->getValue(); - MachineCodeForInstruction &mcfi = MachineCodeForInstruction::get(castI); - TmpInstruction* tempReg = - new TmpInstruction(mcfi, opVal); + MachineCodeForInstruction &mcfi = MachineCodeForInstruction::get(castI); + TmpInstruction* tempReg = + new TmpInstruction(mcfi, opVal); @@ -3243,14 +3243,14 @@ break; } - case 23: // reg: ToUByteTy(reg) - case 24: // reg: ToSByteTy(reg) - case 25: // reg: ToUShortTy(reg) - case 26: // reg: ToShortTy(reg) - case 27: // reg: ToUIntTy(reg) - case 28: // reg: ToIntTy(reg) - case 29: // reg: ToULongTy(reg) - case 30: // reg: ToLongTy(reg) + case 23: // reg: ToUByteTy(reg) + case 24: // reg: ToSByteTy(reg) + case 25: // reg: ToUShortTy(reg) + case 26: // reg: ToShortTy(reg) + case 27: // reg: ToUIntTy(reg) + case 28: // reg: ToIntTy(reg) + case 29: // reg: ToULongTy(reg) + case 30: // reg: ToLongTy(reg) { //====================================================================== // Rules for integer conversions: @@ -3356,9 +3356,9 @@ break; } - case 31: // reg: ToFloatTy(reg): - case 32: // reg: ToDoubleTy(reg): - case 232: // reg: ToDoubleTy(Constant): + case 31: // reg: ToFloatTy(reg): + case 32: // reg: ToDoubleTy(reg): + case 232: // reg: ToDoubleTy(Constant): // If this instruction has a parent (a user) in the tree // and the user is translated as an FsMULd instruction, @@ -3415,12 +3415,12 @@ } break; - case 19: // reg: ToArrayTy(reg): - case 20: // reg: ToPointerTy(reg): + case 19: // reg: ToArrayTy(reg): + case 20: // reg: ToPointerTy(reg): forwardOperandNum = 0; // forward first operand to user break; - case 233: // reg: Add(reg, Constant) + case 233: // reg: Add(reg, Constant) maskUnsignedResult = true; M = CreateAddConstInstruction(subtreeRoot); if (M != NULL) { @@ -3429,12 +3429,12 @@ } // ELSE FALL THROUGH - case 33: // reg: Add(reg, reg) + case 33: // reg: Add(reg, reg) maskUnsignedResult = true; Add3OperandInstr(ChooseAddInstruction(subtreeRoot), subtreeRoot, mvec); break; - case 234: // reg: Sub(reg, Constant) + case 234: // reg: Sub(reg, Constant) maskUnsignedResult = true; M = CreateSubConstInstruction(subtreeRoot); if (M != NULL) { @@ -3443,18 +3443,18 @@ } // ELSE FALL THROUGH - case 34: // reg: Sub(reg, reg) + case 34: // reg: Sub(reg, reg) maskUnsignedResult = true; Add3OperandInstr(ChooseSubInstructionByType( subtreeRoot->getInstruction()->getType()), subtreeRoot, mvec); break; - case 135: // reg: Mul(todouble, todouble) + case 135: // reg: Mul(todouble, todouble) checkCast = true; // FALL THROUGH - case 35: // reg: Mul(reg, reg) + case 35: // reg: Mul(reg, reg) { maskUnsignedResult = true; MachineOpCode forceOp = ((checkCast && BothFloatToDouble(subtreeRoot)) @@ -3468,11 +3468,11 @@ MachineCodeForInstruction::get(mulInstr),forceOp); break; } - case 335: // reg: Mul(todouble, todoubleConst) + case 335: // reg: Mul(todouble, todoubleConst) checkCast = true; // FALL THROUGH - case 235: // reg: Mul(reg, Constant) + case 235: // reg: Mul(reg, Constant) { maskUnsignedResult = true; MachineOpCode forceOp = ((checkCast && BothFloatToDouble(subtreeRoot)) @@ -3487,7 +3487,7 @@ forceOp); break; } - case 236: // reg: Div(reg, Constant) + case 236: // reg: Div(reg, Constant) maskUnsignedResult = true; L = mvec.size(); CreateDivConstInstruction(target, subtreeRoot, mvec); @@ -3495,7 +3495,7 @@ break; // ELSE FALL THROUGH - case 36: // reg: Div(reg, reg) + case 36: // reg: Div(reg, reg) { maskUnsignedResult = true; @@ -3533,8 +3533,8 @@ break; } - case 37: // reg: Rem(reg, reg) - case 237: // reg: Rem(reg, Constant) + case 37: // reg: Rem(reg, reg) + case 237: // reg: Rem(reg, Constant) { maskUnsignedResult = true; @@ -3579,15 +3579,15 @@ break; } - case 38: // bool: And(bool, bool) - case 138: // bool: And(bool, not) - case 238: // bool: And(bool, boolconst) - case 338: // reg : BAnd(reg, reg) - case 538: // reg : BAnd(reg, Constant) + case 38: // bool: And(bool, bool) + case 138: // bool: And(bool, not) + case 238: // bool: And(bool, boolconst) + case 338: // reg : BAnd(reg, reg) + case 538: // reg : BAnd(reg, Constant) Add3OperandInstr(V9::ANDr, subtreeRoot, mvec); break; - case 438: // bool: BAnd(bool, bnot) + case 438: // bool: BAnd(bool, bnot) { // Use the argument of NOT as the second argument! // Mark the NOT node so that no code is generated for it. // If the type is boolean, set 1 or 0 in the result register. @@ -3609,15 +3609,15 @@ break; } - case 39: // bool: Or(bool, bool) - case 139: // bool: Or(bool, not) - case 239: // bool: Or(bool, boolconst) - case 339: // reg : BOr(reg, reg) - case 539: // reg : BOr(reg, Constant) + case 39: // bool: Or(bool, bool) + case 139: // bool: Or(bool, not) + case 239: // bool: Or(bool, boolconst) + case 339: // reg : BOr(reg, reg) + case 539: // reg : BOr(reg, Constant) Add3OperandInstr(V9::ORr, subtreeRoot, mvec); break; - case 439: // bool: BOr(bool, bnot) + case 439: // bool: BOr(bool, bnot) { // Use the argument of NOT as the second argument! // Mark the NOT node so that no code is generated for it. // If the type is boolean, set 1 or 0 in the result register. @@ -3640,15 +3640,15 @@ break; } - case 40: // bool: Xor(bool, bool) - case 140: // bool: Xor(bool, not) - case 240: // bool: Xor(bool, boolconst) - case 340: // reg : BXor(reg, reg) - case 540: // reg : BXor(reg, Constant) + case 40: // bool: Xor(bool, bool) + case 140: // bool: Xor(bool, not) + case 240: // bool: Xor(bool, boolconst) + case 340: // reg : BXor(reg, reg) + case 540: // reg : BXor(reg, Constant) Add3OperandInstr(V9::XORr, subtreeRoot, mvec); break; - case 440: // bool: BXor(bool, bnot) + case 440: // bool: BXor(bool, bnot) { // Use the argument of NOT as the second argument! // Mark the NOT node so that no code is generated for it. // If the type is boolean, set 1 or 0 in the result register. @@ -3669,7 +3669,7 @@ break; } - case 41: // setCCconst: SetCC(reg, Constant) + case 41: // setCCconst: SetCC(reg, Constant) { // Comparison is with a constant: // // If the bool result must be computed into a register (see below), @@ -3720,7 +3720,7 @@ // ELSE FALL THROUGH } - case 42: // bool: SetCC(reg, reg): + case 42: // bool: SetCC(reg, reg): { // This generates a SUBCC instruction, putting the difference in a // result reg. if needed, and/or setting a condition code if needed. @@ -3816,22 +3816,22 @@ break; } - case 51: // reg: Load(reg) - case 52: // reg: Load(ptrreg) + case 51: // reg: Load(reg) + case 52: // reg: Load(ptrreg) SetOperandsForMemInstr(ChooseLoadInstruction( subtreeRoot->getValue()->getType()), mvec, subtreeRoot, target); break; - case 55: // reg: GetElemPtr(reg) - case 56: // reg: GetElemPtrIdx(reg,reg) + case 55: // reg: GetElemPtr(reg) + case 56: // reg: GetElemPtrIdx(reg,reg) // If the GetElemPtr was folded into the user (parent), it will be // caught above. For other cases, we have to compute the address. SetOperandsForMemInstr(V9::ADDr, mvec, subtreeRoot, target); break; - case 57: // reg: Alloca: Implement as 1 instruction: - { // add %fp, offsetFromFP -> result + case 57: // reg: Alloca: Implement as 1 instruction: + { // add %fp, offsetFromFP -> result AllocationInst* instr = cast(subtreeRoot->getInstruction()); unsigned tsize = @@ -3841,10 +3841,10 @@ break; } - case 58: // reg: Alloca(reg): Implement as 3 instructions: - // mul num, typeSz -> tmp - // sub %sp, tmp -> %sp - { // add %sp, frameSizeBelowDynamicArea -> result + case 58: // reg: Alloca(reg): Implement as 3 instructions: + // mul num, typeSz -> tmp + // sub %sp, tmp -> %sp + { // add %sp, frameSizeBelowDynamicArea -> result AllocationInst* instr = cast(subtreeRoot->getInstruction()); const Type* eltType = instr->getAllocatedType(); @@ -3868,7 +3868,7 @@ break; } - case 61: // reg: Call + case 61: // reg: Call { // Generate a direct (CALL) or indirect (JMPL) call. // Mark the return-address register, the indirection // register (for indirect calls), the operands of the Call, @@ -4191,7 +4191,7 @@ break; } - case 62: // reg: Shl(reg, reg) + case 62: // reg: Shl(reg, reg) { Value* argVal1 = subtreeRoot->leftChild()->getValue(); Value* argVal2 = subtreeRoot->rightChild()->getValue(); @@ -4209,7 +4209,7 @@ break; } - case 63: // reg: Shr(reg, reg) + case 63: // reg: Shr(reg, reg) { const Type* opType = subtreeRoot->leftChild()->getValue()->getType(); assert((opType->isInteger() || isa(opType)) && @@ -4222,10 +4222,10 @@ break; } - case 64: // reg: Phi(reg,reg) + case 64: // reg: Phi(reg,reg) break; // don't forward the value - case 66: // reg: VAArg (reg): the va_arg instruction + case 66: // reg: VAArg (reg): the va_arg instruction { // Load argument from stack using current va_list pointer value. // Use 64-bit load for all non-FP args, and LDDF or double for FP. Instruction* vaArgI = subtreeRoot->getInstruction(); @@ -4255,8 +4255,8 @@ break; } - case 71: // reg: VReg - case 72: // reg: Constant + case 71: // reg: VReg + case 72: // reg: Constant break; // don't forward the value default: Index: llvm/lib/Target/SparcV9/SparcV9FrameInfo.h diff -u llvm/lib/Target/SparcV9/SparcV9FrameInfo.h:1.9 llvm/lib/Target/SparcV9/SparcV9FrameInfo.h:1.10 --- llvm/lib/Target/SparcV9/SparcV9FrameInfo.h:1.9 Thu Apr 21 18:25:42 2005 +++ llvm/lib/Target/SparcV9/SparcV9FrameInfo.h Wed Jul 27 00:53:43 2005 @@ -53,7 +53,7 @@ } virtual int getOutgoingArgOffset(MachineFunction& mcInfo, - unsigned argNum) const { + unsigned argNum) const { return FirstOutgoingArgOffsetFromSP + argNum * SizeOfEachArgOnStack; } Index: llvm/lib/Target/SparcV9/SparcV9InstrForest.h diff -u llvm/lib/Target/SparcV9/SparcV9InstrForest.h:1.3 llvm/lib/Target/SparcV9/SparcV9InstrForest.h:1.4 --- llvm/lib/Target/SparcV9/SparcV9InstrForest.h:1.3 Thu Apr 21 18:25:42 2005 +++ llvm/lib/Target/SparcV9/SparcV9InstrForest.h Wed Jul 27 00:53:43 2005 @@ -10,7 +10,7 @@ // A forest of BURG instruction trees (class InstrForest) which represents // a function to the BURG-based instruction selector, and a bunch of constants // and declarations used by the generated BURG code. -// +// //===----------------------------------------------------------------------===// #ifndef SPARCV9INSTRFOREST_H @@ -24,36 +24,36 @@ /// opcode returned by Instruction::getOpcode(). /// static const int - InvalidOp = -1, + InvalidOp = -1, VRegListOp = 97, - VRegNodeOp = 98, + VRegNodeOp = 98, ConstantNodeOp = 99, - LabelNodeOp = 100, - RetValueOp = 100 + Instruction::Ret, // 101 - BrCondOp = 100 + Instruction::Br, // 102 + LabelNodeOp = 100, + RetValueOp = 100 + Instruction::Ret, // 101 + BrCondOp = 100 + Instruction::Br, // 102 BAndOp = 100 + Instruction::And, // 111 BOrOp = 100 + Instruction::Or, // 112 BXorOp = 100 + Instruction::Xor, // 113 BNotOp = 200 + Instruction::Xor, // 213 NotOp = 300 + Instruction::Xor, // 313 - SetCCOp = 100 + Instruction::SetEQ, // 114 - AllocaN = 100 + Instruction::Alloca, // 122 - LoadIdx = 100 + Instruction::Load, // 123 - GetElemPtrIdx = 100 + Instruction::GetElementPtr, // 125 - ToBoolTy = 100 + Instruction::Cast; // 127 + SetCCOp = 100 + Instruction::SetEQ, // 114 + AllocaN = 100 + Instruction::Alloca, // 122 + LoadIdx = 100 + Instruction::Load, // 123 + GetElemPtrIdx = 100 + Instruction::GetElementPtr, // 125 + ToBoolTy = 100 + Instruction::Cast; // 127 static const int - ToUByteTy = ToBoolTy + 1, - ToSByteTy = ToBoolTy + 2, - ToUShortTy = ToBoolTy + 3, - ToShortTy = ToBoolTy + 4, - ToUIntTy = ToBoolTy + 5, - ToIntTy = ToBoolTy + 6, - ToULongTy = ToBoolTy + 7, - ToLongTy = ToBoolTy + 8, - ToFloatTy = ToBoolTy + 9, - ToDoubleTy = ToBoolTy + 10, - ToArrayTy = ToBoolTy + 11, - ToPointerTy = ToBoolTy + 12; + ToUByteTy = ToBoolTy + 1, + ToSByteTy = ToBoolTy + 2, + ToUShortTy = ToBoolTy + 3, + ToShortTy = ToBoolTy + 4, + ToUIntTy = ToBoolTy + 5, + ToIntTy = ToBoolTy + 6, + ToULongTy = ToBoolTy + 7, + ToLongTy = ToBoolTy + 8, + ToFloatTy = ToBoolTy + 9, + ToDoubleTy = ToBoolTy + 10, + ToArrayTy = ToBoolTy + 11, + ToPointerTy = ToBoolTy + 12; /// Data types needed by BURG /// @@ -65,17 +65,17 @@ namespace llvm { class InstrTreeNode; }; -extern short* burm_nts[]; -extern StateLabel burm_label (InstrTreeNode* p); -extern StateLabel burm_state (OpLabel op, StateLabel leftState, - StateLabel rightState); -extern StateLabel burm_rule (StateLabel state, int goalNT); -extern InstrTreeNode** burm_kids (InstrTreeNode* p, int eruleno, - InstrTreeNode* kids[]); -extern void printcover (InstrTreeNode*, int, int); -extern void printtree (InstrTreeNode*); -extern int treecost (InstrTreeNode*, int, int); -extern void printMatches (InstrTreeNode*); +extern short* burm_nts[]; +extern StateLabel burm_label (InstrTreeNode* p); +extern StateLabel burm_state (OpLabel op, StateLabel leftState, + StateLabel rightState); +extern StateLabel burm_rule (StateLabel state, int goalNT); +extern InstrTreeNode** burm_kids (InstrTreeNode* p, int eruleno, + InstrTreeNode* kids[]); +extern void printcover (InstrTreeNode*, int, int); +extern void printtree (InstrTreeNode*); +extern int treecost (InstrTreeNode*, int, int); +extern void printMatches (InstrTreeNode*); namespace llvm { @@ -87,10 +87,10 @@ void operator=(const InstrTreeNode &); // DO NOT IMPLEMENT public: enum InstrTreeNodeType { NTInstructionNode, - NTVRegListNode, - NTVRegNode, - NTConstNode, - NTLabelNode }; + NTVRegListNode, + NTVRegNode, + NTConstNode, + NTLabelNode }; InstrTreeNode* LeftChild; InstrTreeNode* RightChild; InstrTreeNode* Parent; @@ -99,7 +99,7 @@ protected: InstrTreeNodeType treeNodeType; - Value* val; + Value* val; public: InstrTreeNode(InstrTreeNodeType nodeType, Value* _val) @@ -111,17 +111,17 @@ delete LeftChild; delete RightChild; } - InstrTreeNodeType getNodeType () const { return treeNodeType; } - Value* getValue () const { return val; } - inline OpLabel getOpLabel () const { return opLabel; } + InstrTreeNodeType getNodeType () const { return treeNodeType; } + Value* getValue () const { return val; } + inline OpLabel getOpLabel () const { return opLabel; } inline InstrTreeNode *leftChild () const { return LeftChild; } inline InstrTreeNode *parent () const { return Parent; } // If right child is a list node, recursively get its *left* child inline InstrTreeNode* rightChild() const { return (!RightChild ? 0 : - (RightChild->getOpLabel() == VRegListOp - ? RightChild->LeftChild : RightChild)); + (RightChild->getOpLabel() == VRegListOp + ? RightChild->LeftChild : RightChild)); } void dump(int dumpChildren, int indent) const; protected: Index: llvm/lib/Target/SparcV9/SparcV9Internals.h diff -u llvm/lib/Target/SparcV9/SparcV9Internals.h:1.121 llvm/lib/Target/SparcV9/SparcV9Internals.h:1.122 --- llvm/lib/Target/SparcV9/SparcV9Internals.h:1.121 Sun Jun 12 18:52:58 2005 +++ llvm/lib/Target/SparcV9/SparcV9Internals.h Wed Jul 27 00:53:43 2005 @@ -31,18 +31,18 @@ class GetElementPtrInst; enum SparcV9InstrSchedClass { - SPARC_NONE, /* Instructions with no scheduling restrictions */ - SPARC_IEUN, /* Integer class that can use IEU0 or IEU1 */ - SPARC_IEU0, /* Integer class IEU0 */ - SPARC_IEU1, /* Integer class IEU1 */ - SPARC_FPM, /* FP Multiply or Divide instructions */ - SPARC_FPA, /* All other FP instructions */ - SPARC_CTI, /* Control-transfer instructions */ - SPARC_LD, /* Load instructions */ - SPARC_ST, /* Store instructions */ - SPARC_SINGLE, /* Instructions that must issue by themselves */ + SPARC_NONE, /* Instructions with no scheduling restrictions */ + SPARC_IEUN, /* Integer class that can use IEU0 or IEU1 */ + SPARC_IEU0, /* Integer class IEU0 */ + SPARC_IEU1, /* Integer class IEU1 */ + SPARC_FPM, /* FP Multiply or Divide instructions */ + SPARC_FPA, /* All other FP instructions */ + SPARC_CTI, /* Control-transfer instructions */ + SPARC_LD, /* Load instructions */ + SPARC_ST, /* Store instructions */ + SPARC_SINGLE, /* Instructions that must issue by themselves */ - SPARC_INV, /* This should stay at the end for the next value */ + SPARC_INV, /* This should stay at the end for the next value */ SPARC_NUM_SCHED_CLASSES = SPARC_INV }; @@ -65,7 +65,7 @@ // End-of-array marker INVALID_OPCODE, - NUM_REAL_OPCODES = PHI, // number of valid opcodes + NUM_REAL_OPCODES = PHI, // number of valid opcodes NUM_TOTAL_OPCODES = INVALID_OPCODE }; } Index: llvm/lib/Target/SparcV9/SparcV9PrologEpilogInserter.cpp diff -u llvm/lib/Target/SparcV9/SparcV9PrologEpilogInserter.cpp:1.48 llvm/lib/Target/SparcV9/SparcV9PrologEpilogInserter.cpp:1.49 --- llvm/lib/Target/SparcV9/SparcV9PrologEpilogInserter.cpp:1.48 Thu Apr 21 18:25:42 2005 +++ llvm/lib/Target/SparcV9/SparcV9PrologEpilogInserter.cpp Wed Jul 27 00:53:43 2005 @@ -82,8 +82,8 @@ // Do this by creating a code sequence equivalent to: // SETSW -(stackSize), %g1 int uregNum = TM.getRegInfo()->getUnifiedRegNum( - TM.getRegInfo()->getRegClassIDOfType(Type::IntTy), - SparcV9IntRegClass::g1); + TM.getRegInfo()->getRegClassIDOfType(Type::IntTy), + SparcV9IntRegClass::g1); MachineInstr* M = BuildMI(V9::SETHI, 2).addSImm(C) .addMReg(uregNum, MachineOperand::Def); Index: llvm/lib/Target/SparcV9/SparcV9RegClassInfo.cpp diff -u llvm/lib/Target/SparcV9/SparcV9RegClassInfo.cpp:1.41 llvm/lib/Target/SparcV9/SparcV9RegClassInfo.cpp:1.42 --- llvm/lib/Target/SparcV9/SparcV9RegClassInfo.cpp:1.41 Sun Jun 12 18:52:58 2005 +++ llvm/lib/Target/SparcV9/SparcV9RegClassInfo.cpp Wed Jul 27 00:53:43 2005 @@ -49,13 +49,13 @@ unsigned SugCol = LR->getSuggestedColor(); if (!IsColorUsedArr[SugCol]) { if (LR->isSuggestedColorUsable()) { - // if the suggested color is volatile, we should use it only if - // there are no call interferences. Otherwise, it will get spilled. - if (DEBUG_RA) - std::cerr << "\n -Coloring with sug color: " << SugCol; + // if the suggested color is volatile, we should use it only if + // there are no call interferences. Otherwise, it will get spilled. + if (DEBUG_RA) + std::cerr << "\n -Coloring with sug color: " << SugCol; - LR->setColor(LR->getSuggestedColor()); - return; + LR->setColor(LR->getSuggestedColor()); + return; } else if(DEBUG_RA) { std::cerr << "\n Couldn't alloc Sug col - LR volatile & calls interf"; } @@ -195,8 +195,8 @@ // If the LR is a double try to allocate f32 - f63 // If the above fails or LR is single precision // If the LR does not interfere with a call -// start allocating from f0 -// Else start allocating from f6 +// start allocating from f0 +// Else start allocating from f6 // If a color is still not found because LR interferes with a call // Search in f0 - f6. If found mark for spill across calls. // If a color is still not fond, mark for spilling @@ -298,8 +298,8 @@ // color could be found. // Now try to allocate even a volatile color ColorFound = findFloatColor(LR, SparcV9FloatRegClass::StartOfAllRegs, - SparcV9FloatRegClass::StartOfNonVolatileRegs, - IsColorUsedArr); + SparcV9FloatRegClass::StartOfNonVolatileRegs, + IsColorUsedArr); } if (ColorFound >= 0) { @@ -355,7 +355,7 @@ for (unsigned c = 0; c < NC; c+=2) if (!IsColorUsedArr[c]) { assert(!IsColorUsedArr[c+1] && "Incorrect used regs for FP double!"); - return c; + return c; } return -1; } @@ -381,7 +381,7 @@ if (!IsColorUsedArr[c]) { assert(!IsColorUsedArr[c+1] && "Incorrect marking of used regs for SparcV9 FP double!"); - return c; + return c; } } else { // find first unused color for a single Index: llvm/lib/Target/SparcV9/SparcV9RegClassInfo.h diff -u llvm/lib/Target/SparcV9/SparcV9RegClassInfo.h:1.30 llvm/lib/Target/SparcV9/SparcV9RegClassInfo.h:1.31 --- llvm/lib/Target/SparcV9/SparcV9RegClassInfo.h:1.30 Sun Jun 12 18:52:58 2005 +++ llvm/lib/Target/SparcV9/SparcV9RegClassInfo.h Wed Jul 27 00:53:43 2005 @@ -90,7 +90,7 @@ class SparcV9FloatRegClass : public TargetRegClassInfo { int findFloatColor(const V9LiveRange *LR, unsigned Start, - unsigned End, + unsigned End, const std::vector &IsColorUsedArr) const; public: SparcV9FloatRegClass(unsigned ID) Index: llvm/lib/Target/SparcV9/SparcV9RegInfo.cpp diff -u llvm/lib/Target/SparcV9/SparcV9RegInfo.cpp:1.141 llvm/lib/Target/SparcV9/SparcV9RegInfo.cpp:1.142 --- llvm/lib/Target/SparcV9/SparcV9RegInfo.cpp:1.141 Sun Jun 12 18:52:58 2005 +++ llvm/lib/Target/SparcV9/SparcV9RegInfo.cpp Wed Jul 27 00:53:43 2005 @@ -211,7 +211,7 @@ getInvalidRegNum() : SparcV9FloatRegClass::f0 + (argNo * 2); else assert(0 && "Illegal FP register type"); - return 0; + return 0; } } @@ -313,7 +313,7 @@ // We always suggest %i7 by convention. //--------------------------------------------------------------------------- void SparcV9RegInfo::suggestReg4RetAddr(MachineInstr *RetMI, - LiveRangeInfo& LRI) const { + LiveRangeInfo& LRI) const { assert(target.getInstrInfo()->isReturn(RetMI->getOpcode())); @@ -366,7 +366,7 @@ // done - it will be colored (or spilled) as a normal live range. //--------------------------------------------------------------------------- void SparcV9RegInfo::suggestRegs4MethodArgs(const Function *Meth, - LiveRangeInfo& LRI) const + LiveRangeInfo& LRI) const { // Check if this is a varArgs function. needed for choosing regs. bool isVarArgs = isVarArgsFunction(Meth->getType()); @@ -444,7 +444,7 @@ // if LR received the correct color, nothing to do // if( UniLRReg == UniArgReg ) - continue; + continue; // We are here because the LR did not receive the suggested // but LR received another register. @@ -455,36 +455,36 @@ // the UniLRReg register // if( isArgInReg ) { - if( regClassIDOfArgReg != RegClassID ) { - // NOTE: This code has not been well-tested. + if( regClassIDOfArgReg != RegClassID ) { + // NOTE: This code has not been well-tested. - // It is a variable argument call: the float reg must go in a %o reg. - // We have to move an int reg to a float reg via memory. + // It is a variable argument call: the float reg must go in a %o reg. + // We have to move an int reg to a float reg via memory. // assert(isVarArgs && RegClassID == FloatRegClassID && regClassIDOfArgReg == IntRegClassID && "This should only be an Int register for an FP argument"); - int TmpOff = MachineFunction::get(Meth).getInfo()->pushTempValue( + int TmpOff = MachineFunction::get(Meth).getInfo()->pushTempValue( getSpilledRegSize(regType)); - cpReg2MemMI(InstrnsBefore, + cpReg2MemMI(InstrnsBefore, UniArgReg, getFramePointer(), TmpOff, IntRegType); - cpMem2RegMI(InstrnsBefore, + cpMem2RegMI(InstrnsBefore, getFramePointer(), TmpOff, UniLRReg, regType); - } - else { - cpReg2RegMI(InstrnsBefore, UniArgReg, UniLRReg, regType); - } + } + else { + cpReg2RegMI(InstrnsBefore, UniArgReg, UniLRReg, regType); + } } else { - // Now the arg is coming on stack. Since the LR received a register, - // we just have to load the arg on stack into that register - // + // Now the arg is coming on stack. Since the LR received a register, + // we just have to load the arg on stack into that register + // const TargetFrameInfo& frameInfo = *target.getFrameInfo(); - int offsetFromFP = + int offsetFromFP = frameInfo.getIncomingArgOffset(MachineFunction::get(Meth), argNo); @@ -498,7 +498,7 @@ offsetFromFP += slotSize - argSize; } - cpMem2RegMI(InstrnsBefore, + cpMem2RegMI(InstrnsBefore, getFramePointer(), offsetFromFP, UniLRReg, regType); } @@ -513,12 +513,12 @@ if( isArgInReg ) { - if( regClassIDOfArgReg != RegClassID ) { + if( regClassIDOfArgReg != RegClassID ) { assert(0 && "FP arguments to a varargs function should be explicitly " "copied to/from int registers by instruction selection!"); - // It must be a float arg for a variable argument call, which + // It must be a float arg for a variable argument call, which // must come in a %o reg. Move the int reg to the stack. // assert(isVarArgs && regClassIDOfArgReg == IntRegClassID && @@ -535,14 +535,14 @@ else { - // Now the arg is coming on stack. Since the LR did NOT - // received a register as well, it is allocated a stack position. We - // can simply change the stack position of the LR. We can do this, - // since this method is called before any other method that makes - // uses of the stack pos of the LR (e.g., updateMachineInstr) + // Now the arg is coming on stack. Since the LR did NOT + // received a register as well, it is allocated a stack position. We + // can simply change the stack position of the LR. We can do this, + // since this method is called before any other method that makes + // uses of the stack pos of the LR (e.g., updateMachineInstr) // const TargetFrameInfo& frameInfo = *target.getFrameInfo(); - int offsetFromFP = + int offsetFromFP = frameInfo.getIncomingArgOffset(MachineFunction::get(Meth), argNo); @@ -556,7 +556,7 @@ offsetFromFP += slotSize - argSize; } - LR->modifySpillOffFromFP( offsetFromFP ); + LR->modifySpillOffFromFP( offsetFromFP ); } } @@ -572,7 +572,7 @@ // outgoing call args and the return value of the call. //--------------------------------------------------------------------------- void SparcV9RegInfo::suggestRegs4CallArgs(MachineInstr *CallMI, - LiveRangeInfo& LRI) const { + LiveRangeInfo& LRI) const { assert ( (target.getInstrInfo())->isCall(CallMI->getOpcode()) ); CallArgsDescriptor* argDesc = CallArgsDescriptor::get(CallMI); @@ -690,7 +690,7 @@ int RegType) const { assert( ((int)SrcReg != getInvalidRegNum()) && ((int)DestReg != getInvalidRegNum()) && - "Invalid Register"); + "Invalid Register"); MachineInstr * MI = NULL; Index: llvm/lib/Target/SparcV9/SparcV9RegInfo.h diff -u llvm/lib/Target/SparcV9/SparcV9RegInfo.h:1.19 llvm/lib/Target/SparcV9/SparcV9RegInfo.h:1.20 --- llvm/lib/Target/SparcV9/SparcV9RegInfo.h:1.19 Sun Jun 12 18:52:58 2005 +++ llvm/lib/Target/SparcV9/SparcV9RegInfo.h Wed Jul 27 00:53:43 2005 @@ -129,7 +129,7 @@ // To find the register class used for a specified Type // unsigned getRegClassIDOfType (const Type *type, - bool isCCReg = false) const; + bool isCCReg = false) const; // To find the register class to which a specified register belongs // @@ -165,7 +165,7 @@ LiveRangeInfo& LRI) const; void suggestReg4RetValue(MachineInstr *RetI, - LiveRangeInfo& LRI) const; + LiveRangeInfo& LRI) const; void colorMethodArgs(const Function *Func, LiveRangeInfo &LRI, @@ -259,7 +259,7 @@ // as required. See SparcV9RegInfo.cpp for the implementation. // void suggestReg4RetAddr(MachineInstr *RetMI, - LiveRangeInfo &LRI) const; + LiveRangeInfo &LRI) const; void suggestReg4CallAddr(MachineInstr *CallMI, LiveRangeInfo &LRI) const; Index: llvm/lib/Target/SparcV9/SparcV9SchedInfo.cpp diff -u llvm/lib/Target/SparcV9/SparcV9SchedInfo.cpp:1.14 llvm/lib/Target/SparcV9/SparcV9SchedInfo.cpp:1.15 --- llvm/lib/Target/SparcV9/SparcV9SchedInfo.cpp:1.14 Thu Apr 21 18:25:42 2005 +++ llvm/lib/Target/SparcV9/SparcV9SchedInfo.cpp Wed Jul 27 00:53:43 2005 @@ -71,7 +71,7 @@ -- Shift instructions cannot be grouped with other IEU0-specific instructions. -- CC setting instructions cannot be grouped with other IEU1-specific instrs. -- Several instructions must be issued in a single-instruction group: - MOVcc or MOVr, MULs/x and DIVs/x, SAVE/RESTORE, many others + MOVcc or MOVr, MULs/x and DIVs/x, SAVE/RESTORE, many others -- A CALL or JMPL breaks a group, ie, is not combined with subsequent instrs. -- -- @@ -357,7 +357,7 @@ /*numEntries*/ 4, /* V[] */ { /*Cycle G */ { AllIssueSlots.rid, 0, 1 }, - { CTIIssueSlots.rid, 0, 1 }, + { CTIIssueSlots.rid, 0, 1 }, /*Cycle E */ { IAlu0.rid, 1, 1 }, /*Cycles E-C */ { CTIDelayCycle.rid, 1, 2 } /*Cycle C */ @@ -423,79 +423,79 @@ // opCode, isSingleIssue, breaksGroup, numBubbles - // Special cases for single-issue only - // Other single issue cases are below. -//{ V9::LDDA, true, true, 0 }, -//{ V9::STDA, true, true, 0 }, -//{ V9::LDDF, true, true, 0 }, -//{ V9::LDDFA, true, true, 0 }, - { V9::ADDCr, true, true, 0 }, - { V9::ADDCi, true, true, 0 }, - { V9::ADDCccr, true, true, 0 }, - { V9::ADDCcci, true, true, 0 }, - { V9::SUBCr, true, true, 0 }, - { V9::SUBCi, true, true, 0 }, - { V9::SUBCccr, true, true, 0 }, - { V9::SUBCcci, true, true, 0 }, -//{ V9::LDSTUB, true, true, 0 }, -//{ V9::SWAP, true, true, 0 }, -//{ V9::SWAPA, true, true, 0 }, -//{ V9::CAS, true, true, 0 }, -//{ V9::CASA, true, true, 0 }, -//{ V9::CASX, true, true, 0 }, -//{ V9::CASXA, true, true, 0 }, -//{ V9::LDFSR, true, true, 0 }, -//{ V9::LDFSRA, true, true, 0 }, -//{ V9::LDXFSR, true, true, 0 }, -//{ V9::LDXFSRA, true, true, 0 }, -//{ V9::STFSR, true, true, 0 }, -//{ V9::STFSRA, true, true, 0 }, -//{ V9::STXFSR, true, true, 0 }, -//{ V9::STXFSRA, true, true, 0 }, -//{ V9::SAVED, true, true, 0 }, -//{ V9::RESTORED, true, true, 0 }, -//{ V9::FLUSH, true, true, 9 }, -//{ V9::FLUSHW, true, true, 9 }, -//{ V9::ALIGNADDR, true, true, 0 }, -//{ V9::DONE, true, true, 0 }, -//{ V9::RETRY, true, true, 0 }, -//{ V9::TCC, true, true, 0 }, -//{ V9::SHUTDOWN, true, true, 0 }, - - // Special cases for breaking group *before* - // CURRENTLY NOT SUPPORTED! - { V9::CALL, false, false, 0 }, - { V9::JMPLCALLr, false, false, 0 }, - { V9::JMPLCALLi, false, false, 0 }, - { V9::JMPLRETr, false, false, 0 }, - { V9::JMPLRETi, false, false, 0 }, - - // Special cases for breaking the group *after* - { V9::MULXr, true, true, (4+34)/2 }, - { V9::MULXi, true, true, (4+34)/2 }, - { V9::FDIVS, false, true, 0 }, - { V9::FDIVD, false, true, 0 }, - { V9::FDIVQ, false, true, 0 }, - { V9::FSQRTS, false, true, 0 }, - { V9::FSQRTD, false, true, 0 }, - { V9::FSQRTQ, false, true, 0 }, + // Special cases for single-issue only + // Other single issue cases are below. +//{ V9::LDDA, true, true, 0 }, +//{ V9::STDA, true, true, 0 }, +//{ V9::LDDF, true, true, 0 }, +//{ V9::LDDFA, true, true, 0 }, + { V9::ADDCr, true, true, 0 }, + { V9::ADDCi, true, true, 0 }, + { V9::ADDCccr, true, true, 0 }, + { V9::ADDCcci, true, true, 0 }, + { V9::SUBCr, true, true, 0 }, + { V9::SUBCi, true, true, 0 }, + { V9::SUBCccr, true, true, 0 }, + { V9::SUBCcci, true, true, 0 }, +//{ V9::LDSTUB, true, true, 0 }, +//{ V9::SWAP, true, true, 0 }, +//{ V9::SWAPA, true, true, 0 }, +//{ V9::CAS, true, true, 0 }, +//{ V9::CASA, true, true, 0 }, +//{ V9::CASX, true, true, 0 }, +//{ V9::CASXA, true, true, 0 }, +//{ V9::LDFSR, true, true, 0 }, +//{ V9::LDFSRA, true, true, 0 }, +//{ V9::LDXFSR, true, true, 0 }, +//{ V9::LDXFSRA, true, true, 0 }, +//{ V9::STFSR, true, true, 0 }, +//{ V9::STFSRA, true, true, 0 }, +//{ V9::STXFSR, true, true, 0 }, +//{ V9::STXFSRA, true, true, 0 }, +//{ V9::SAVED, true, true, 0 }, +//{ V9::RESTORED, true, true, 0 }, +//{ V9::FLUSH, true, true, 9 }, +//{ V9::FLUSHW, true, true, 9 }, +//{ V9::ALIGNADDR, true, true, 0 }, +//{ V9::DONE, true, true, 0 }, +//{ V9::RETRY, true, true, 0 }, +//{ V9::TCC, true, true, 0 }, +//{ V9::SHUTDOWN, true, true, 0 }, + + // Special cases for breaking group *before* + // CURRENTLY NOT SUPPORTED! + { V9::CALL, false, false, 0 }, + { V9::JMPLCALLr, false, false, 0 }, + { V9::JMPLCALLi, false, false, 0 }, + { V9::JMPLRETr, false, false, 0 }, + { V9::JMPLRETi, false, false, 0 }, + + // Special cases for breaking the group *after* + { V9::MULXr, true, true, (4+34)/2 }, + { V9::MULXi, true, true, (4+34)/2 }, + { V9::FDIVS, false, true, 0 }, + { V9::FDIVD, false, true, 0 }, + { V9::FDIVQ, false, true, 0 }, + { V9::FSQRTS, false, true, 0 }, + { V9::FSQRTD, false, true, 0 }, + { V9::FSQRTQ, false, true, 0 }, //{ V9::FCMP{LE,GT,NE,EQ}, false, true, 0 }, - // Instructions that introduce bubbles -//{ V9::MULScc, true, true, 2 }, -//{ V9::SMULcc, true, true, (4+18)/2 }, -//{ V9::UMULcc, true, true, (4+19)/2 }, - { V9::SDIVXr, true, true, 68 }, - { V9::SDIVXi, true, true, 68 }, - { V9::UDIVXr, true, true, 68 }, - { V9::UDIVXi, true, true, 68 }, -//{ V9::SDIVcc, true, true, 36 }, -//{ V9::UDIVcc, true, true, 37 }, - { V9::WRCCRr, true, true, 4 }, - { V9::WRCCRi, true, true, 4 }, -//{ V9::WRPR, true, true, 4 }, -//{ V9::RDCCR, true, true, 0 }, // no bubbles after, but see below -//{ V9::RDPR, true, true, 0 }, + // Instructions that introduce bubbles +//{ V9::MULScc, true, true, 2 }, +//{ V9::SMULcc, true, true, (4+18)/2 }, +//{ V9::UMULcc, true, true, (4+19)/2 }, + { V9::SDIVXr, true, true, 68 }, + { V9::SDIVXi, true, true, 68 }, + { V9::UDIVXr, true, true, 68 }, + { V9::UDIVXi, true, true, 68 }, +//{ V9::SDIVcc, true, true, 36 }, +//{ V9::UDIVcc, true, true, 37 }, + { V9::WRCCRr, true, true, 4 }, + { V9::WRCCRi, true, true, 4 }, +//{ V9::WRPR, true, true, 4 }, +//{ V9::RDCCR, true, true, 0 }, // no bubbles after, but see below +//{ V9::RDPR, true, true, 0 }, }; @@ -738,14 +738,14 @@ SparcV9SchedInfo::SparcV9SchedInfo(const TargetMachine& tgt) : TargetSchedInfo(tgt, (unsigned int) SPARC_NUM_SCHED_CLASSES, - SparcV9RUsageDesc, - SparcV9InstrUsageDeltas, - SparcV9InstrIssueDeltas, - sizeof(SparcV9InstrUsageDeltas)/sizeof(InstrRUsageDelta), - sizeof(SparcV9InstrIssueDeltas)/sizeof(InstrIssueDelta)) + SparcV9RUsageDesc, + SparcV9InstrUsageDeltas, + SparcV9InstrIssueDeltas, + sizeof(SparcV9InstrUsageDeltas)/sizeof(InstrRUsageDelta), + sizeof(SparcV9InstrIssueDeltas)/sizeof(InstrIssueDelta)) { maxNumIssueTotal = 4; - longestIssueConflict = 0; // computed from issuesGaps[] + longestIssueConflict = 0; // computed from issuesGaps[] // must be called after above parameters are initialized. initializeResources(); Index: llvm/lib/Target/SparcV9/SparcV9TargetMachine.cpp diff -u llvm/lib/Target/SparcV9/SparcV9TargetMachine.cpp:1.139 llvm/lib/Target/SparcV9/SparcV9TargetMachine.cpp:1.140 --- llvm/lib/Target/SparcV9/SparcV9TargetMachine.cpp:1.139 Fri Jun 24 21:48:37 2005 +++ llvm/lib/Target/SparcV9/SparcV9TargetMachine.cpp Wed Jul 27 00:53:43 2005 @@ -64,10 +64,10 @@ cl::desc("Emit LLVM-to-MachineCode mapping info to assembly")); cl::opt EnableModSched("enable-modsched", - cl::desc("Enable modulo scheduling pass"), cl::Hidden); + cl::desc("Enable modulo scheduling pass"), cl::Hidden); cl::opt EnableSBModSched("enable-modschedSB", - cl::desc("Enable superblock modulo scheduling (experimental)"), cl::Hidden); + cl::desc("Enable superblock modulo scheduling (experimental)"), cl::Hidden); // Register the target. RegisterTarget X("sparcv9", " SPARC V9"); Index: llvm/lib/Target/SparcV9/SparcV9TmpInstr.cpp diff -u llvm/lib/Target/SparcV9/SparcV9TmpInstr.cpp:1.5 llvm/lib/Target/SparcV9/SparcV9TmpInstr.cpp:1.6 --- llvm/lib/Target/SparcV9/SparcV9TmpInstr.cpp:1.5 Thu Apr 21 18:25:42 2005 +++ llvm/lib/Target/SparcV9/SparcV9TmpInstr.cpp Wed Jul 27 00:53:43 2005 @@ -9,7 +9,7 @@ // // Methods of class for temporary intermediate values used within the current // SparcV9 backend. -// +// //===----------------------------------------------------------------------===// #include "SparcV9TmpInstr.h" From jeffc at jolt-lang.org Wed Jul 27 01:12:58 2005 From: jeffc at jolt-lang.org (Jeff Cohen) Date: Wed, 27 Jul 2005 01:12:58 -0500 Subject: [llvm-commits] CVS: llvm/lib/Target/SparcV9/ModuloScheduling/DependenceAnalyzer.cpp MSSchedule.cpp MSScheduleSB.cpp MSchedGraph.cpp MSchedGraphSB.cpp ModuloScheduling.cpp ModuloSchedulingSuperBlock.cpp Message-ID: <200507270612.BAA32283@zion.cs.uiuc.edu> Changes in directory llvm/lib/Target/SparcV9/ModuloScheduling: DependenceAnalyzer.cpp updated: 1.8 -> 1.9 MSSchedule.cpp updated: 1.17 -> 1.18 MSScheduleSB.cpp updated: 1.2 -> 1.3 MSchedGraph.cpp updated: 1.22 -> 1.23 MSchedGraphSB.cpp updated: 1.4 -> 1.5 ModuloScheduling.cpp updated: 1.51 -> 1.52 ModuloSchedulingSuperBlock.cpp updated: 1.4 -> 1.5 --- Log message: Eliminate all remaining tabs and trailing spaces. --- Diffs of the changes: (+638 -638) DependenceAnalyzer.cpp | 80 +++--- MSSchedule.cpp | 38 +-- MSScheduleSB.cpp | 38 +-- MSchedGraph.cpp | 218 +++++++++--------- MSchedGraphSB.cpp | 234 ++++++++++---------- ModuloScheduling.cpp | 194 ++++++++-------- ModuloSchedulingSuperBlock.cpp | 474 ++++++++++++++++++++--------------------- 7 files changed, 638 insertions(+), 638 deletions(-) Index: llvm/lib/Target/SparcV9/ModuloScheduling/DependenceAnalyzer.cpp diff -u llvm/lib/Target/SparcV9/ModuloScheduling/DependenceAnalyzer.cpp:1.8 llvm/lib/Target/SparcV9/ModuloScheduling/DependenceAnalyzer.cpp:1.9 --- llvm/lib/Target/SparcV9/ModuloScheduling/DependenceAnalyzer.cpp:1.8 Wed Jul 27 00:53:44 2005 +++ llvm/lib/Target/SparcV9/ModuloScheduling/DependenceAnalyzer.cpp Wed Jul 27 01:12:34 2005 @@ -25,14 +25,14 @@ /// Create ModuloSchedulingPass FunctionPass *createDependenceAnalyzer() { - return new DependenceAnalyzer(); + return new DependenceAnalyzer(); } } Statistic<> NoDeps("depanalyzer-nodeps", "Number of dependences eliminated"); -Statistic<> NumDeps("depanalyzer-deps", +Statistic<> NumDeps("depanalyzer-deps", "Number of dependences could not eliminate"); -Statistic<> AdvDeps("depanalyzer-advdeps", +Statistic<> AdvDeps("depanalyzer-advdeps", "Number of dependences using advanced techniques"); bool DependenceAnalyzer::runOnFunction(Function &F) { @@ -43,25 +43,25 @@ return false; } -static RegisterAnalysisX("depanalyzer", +static RegisterAnalysisX("depanalyzer", "Dependence Analyzer"); - + // - Get inter and intra dependences between loads and stores // -// Overview of Method: -// Step 1: Use alias analysis to determine dependencies if values are loop -// invariant -// Step 2: If pointers are not GEP, then there is a dependence. -// Step 3: Compare GEP base pointers with AA. If no alias, no dependence. -// If may alias, then add a dependence. If must alias, then analyze -// further (Step 4) +// Overview of Method: +// Step 1: Use alias analysis to determine dependencies if values are loop +// invariant +// Step 2: If pointers are not GEP, then there is a dependence. +// Step 3: Compare GEP base pointers with AA. If no alias, no dependence. +// If may alias, then add a dependence. If must alias, then analyze +// further (Step 4) // Step 4: do advanced analysis -void DependenceAnalyzer::AnalyzeDeps(Value *val, Value *val2, bool valLoad, - bool val2Load, - std::vector &deps, - BasicBlock *BB, +void DependenceAnalyzer::AnalyzeDeps(Value *val, Value *val2, bool valLoad, + bool val2Load, + std::vector &deps, + BasicBlock *BB, bool srcBeforeDest) { - + bool loopInvariant = true; //Check if both are instructions and prove not loop invariant if possible @@ -71,8 +71,8 @@ if(Instruction *val2Inst = dyn_cast(val2)) if(val2Inst->getParent() == BB) loopInvariant = false; - - + + //If Loop invariant, let AA decide if(loopInvariant) { if(AA->alias(val, (unsigned)TD->getTypeSize(val->getType()), @@ -84,7 +84,7 @@ ++NoDeps; return; } - + //Otherwise, continue with step 2 GetElementPtrInst *GP = dyn_cast(val); @@ -120,7 +120,7 @@ // advancedDepAnalysis - Do advanced data dependence tests -void DependenceAnalyzer::advancedDepAnalysis(GetElementPtrInst *gp1, +void DependenceAnalyzer::advancedDepAnalysis(GetElementPtrInst *gp1, GetElementPtrInst *gp2, bool valLoad, bool val2Load, @@ -139,7 +139,7 @@ if(Constant *c2 = dyn_cast(gp2->getOperand(1))) if(c1->isNullValue() && c2->isNullValue()) GPok = true; - + if(!GPok) { createDep(deps, valLoad, val2Load, srcBeforeDest); return; @@ -153,7 +153,7 @@ Gep1Idx = c1->getOperand(0); if(CastInst *c2 = dyn_cast(Gep2Idx)) Gep2Idx = c2->getOperand(0); - + //Get SCEV for each index into the area SCEVHandle SV1 = SE->getSCEV(Gep1Idx); SCEVHandle SV2 = SE->getSCEV(Gep2Idx); @@ -188,7 +188,7 @@ createDep(deps, valLoad, val2Load, srcBeforeDest); return; } - + if(B1->getValue()->getRawValue() != 1 || B2->getValue()->getRawValue() != 1) { createDep(deps, valLoad, val2Load, srcBeforeDest); return; @@ -214,7 +214,7 @@ ++NoDeps; return; } - + //Find constant index difference int diff = A1->getValue()->getRawValue() - A2->getValue()->getRawValue(); //std::cerr << diff << "\n"; @@ -223,14 +223,14 @@ if(diff > 0) createDep(deps, valLoad, val2Load, srcBeforeDest, diff); - + //assert(diff > 0 && "Expected diff to be greater then 0"); } // Create dependences once its determined these two instructions // references the same memory -void DependenceAnalyzer::createDep(std::vector &deps, - bool valLoad, bool val2Load, +void DependenceAnalyzer::createDep(std::vector &deps, + bool valLoad, bool val2Load, bool srcBeforeDest, int diff) { //If the source instruction occurs after the destination instruction @@ -240,7 +240,7 @@ //If load/store pair if(valLoad && !val2Load) { - if(srcBeforeDest) + if(srcBeforeDest) //Anti Dep deps.push_back(Dependence(diff, Dependence::AntiDep)); else @@ -250,7 +250,7 @@ } //If store/load pair else if(!valLoad && val2Load) { - if(srcBeforeDest) + if(srcBeforeDest) //True Dep deps.push_back(Dependence(diff, Dependence::TrueDep)); else @@ -266,10 +266,10 @@ } - + //Get Dependence Info for a pair of Instructions -DependenceResult DependenceAnalyzer::getDependenceInfo(Instruction *inst1, - Instruction *inst2, +DependenceResult DependenceAnalyzer::getDependenceInfo(Instruction *inst1, + Instruction *inst2, bool srcBeforeDest) { std::vector deps; @@ -281,24 +281,24 @@ return DependenceResult(deps); if(LoadInst *ldInst = dyn_cast(inst1)) { - + if(StoreInst *stInst = dyn_cast(inst2)) - AnalyzeDeps(ldInst->getOperand(0), stInst->getOperand(1), + AnalyzeDeps(ldInst->getOperand(0), stInst->getOperand(1), true, false, deps, ldInst->getParent(), srcBeforeDest); } else if(StoreInst *stInst = dyn_cast(inst1)) { - + if(LoadInst *ldInst = dyn_cast(inst2)) - AnalyzeDeps(stInst->getOperand(1), ldInst->getOperand(0), false, true, + AnalyzeDeps(stInst->getOperand(1), ldInst->getOperand(0), false, true, deps, ldInst->getParent(), srcBeforeDest); - + else if(StoreInst *stInst2 = dyn_cast(inst2)) - AnalyzeDeps(stInst->getOperand(1), stInst2->getOperand(1), false, false, + AnalyzeDeps(stInst->getOperand(1), stInst2->getOperand(1), false, false, deps, stInst->getParent(), srcBeforeDest); } else assert(0 && "Expected a load or a store\n"); - + DependenceResult dr = DependenceResult(deps); return dr; } Index: llvm/lib/Target/SparcV9/ModuloScheduling/MSSchedule.cpp diff -u llvm/lib/Target/SparcV9/ModuloScheduling/MSSchedule.cpp:1.17 llvm/lib/Target/SparcV9/ModuloScheduling/MSSchedule.cpp:1.18 --- llvm/lib/Target/SparcV9/ModuloScheduling/MSSchedule.cpp:1.17 Wed Jul 27 00:53:44 2005 +++ llvm/lib/Target/SparcV9/ModuloScheduling/MSSchedule.cpp Wed Jul 27 01:12:34 2005 @@ -21,7 +21,7 @@ using namespace llvm; //Check if all resources are free -bool resourcesFree(MSchedGraphNode*, int, +bool resourcesFree(MSchedGraphNode*, int, std::map > &resourceNumPerCycle); //Returns a boolean indicating if the start cycle needs to be increased/decreased @@ -84,12 +84,12 @@ isFree = false; } } - + return isFree; } void MSSchedule::useResource(int resourceNum, int cycle) { - + //Get Map for this cycle if(resourceNumPerCycle.count(cycle)) { if(resourceNumPerCycle[cycle].count(resourceNum)) { @@ -105,7 +105,7 @@ resourceUse[resourceNum] = 1; resourceNumPerCycle[cycle] = resourceUse; } - + } bool MSSchedule::resourcesFree(MSchedGraphNode *node, int cycle, int II) { @@ -129,34 +129,34 @@ //Now check all cycles for conflicts for(int index = 0; index < (int) cyclesMayConflict.size(); ++index) { currentCycle = cyclesMayConflict[index]; - + //Get resource usage for this instruction InstrRUsage rUsage = msi->getInstrRUsage(node->getInst()->getOpcode()); std::vector > resources = rUsage.resourcesByCycle; - + //Loop over resources in each cycle and increments their usage count for(unsigned i=0; i < resources.size(); ++i) { for(unsigned j=0; j < resources[i].size(); ++j) { - + //Get Resource to check its availability int resourceNum = resources[i][j]; - + DEBUG(std::cerr << "Attempting to schedule Resource Num: " << resourceNum << " in cycle: " << currentCycle << "\n"); - - success = resourceAvailable(resourceNum, currentCycle); - + + success = resourceAvailable(resourceNum, currentCycle); + if(!success) break; - + } - + if(!success) break; - + //Increase cycle currentCycle++; } - + if(!success) return false; } @@ -168,7 +168,7 @@ //Get resource usage for this instruction InstrRUsage rUsage = msi->getInstrRUsage(node->getInst()->getOpcode()); std::vector > resources = rUsage.resourcesByCycle; - + //Loop over resources in each cycle and increments their usage count for(unsigned i=0; i < resources.size(); ++i) { for(unsigned j=0; j < resources[i].size(); ++j) { @@ -195,7 +195,7 @@ //Using the schedule, fold up into kernel and check resource conflicts as we go std::vector > tempKernel; - + int stageNum = ((schedule.rbegin()->first-offset)+1)/ II; int maxSN = 0; @@ -212,7 +212,7 @@ tempKernel.push_back(std::make_pair(*I, count)); maxSN = std::max(maxSN, count); - + } } ++count; @@ -286,7 +286,7 @@ } } } - + assert(0 && "We should always have found the def in our kernel\n"); } Index: llvm/lib/Target/SparcV9/ModuloScheduling/MSScheduleSB.cpp diff -u llvm/lib/Target/SparcV9/ModuloScheduling/MSScheduleSB.cpp:1.2 llvm/lib/Target/SparcV9/ModuloScheduling/MSScheduleSB.cpp:1.3 --- llvm/lib/Target/SparcV9/ModuloScheduling/MSScheduleSB.cpp:1.2 Wed Jul 27 00:53:44 2005 +++ llvm/lib/Target/SparcV9/ModuloScheduling/MSScheduleSB.cpp Wed Jul 27 01:12:34 2005 @@ -21,7 +21,7 @@ using namespace llvm; //Check if all resources are free -bool resourcesFree(MSchedGraphSBNode*, int, +bool resourcesFree(MSchedGraphSBNode*, int, std::map > &resourceNumPerCycle); //Returns a boolean indicating if the start cycle needs to be increased/decreased @@ -84,12 +84,12 @@ isFree = false; } } - + return isFree; } void MSScheduleSB::useResource(int resourceNum, int cycle) { - + //Get Map for this cycle if(resourceNumPerCycle.count(cycle)) { if(resourceNumPerCycle[cycle].count(resourceNum)) { @@ -105,7 +105,7 @@ resourceUse[resourceNum] = 1; resourceNumPerCycle[cycle] = resourceUse; } - + } bool MSScheduleSB::resourcesFree(MSchedGraphSBNode *node, int cycle, int II) { @@ -129,34 +129,34 @@ //Now check all cycles for conflicts for(int index = 0; index < (int) cyclesMayConflict.size(); ++index) { currentCycle = cyclesMayConflict[index]; - + //Get resource usage for this instruction InstrRUsage rUsage = msi->getInstrRUsage(node->getInst()->getOpcode()); std::vector > resources = rUsage.resourcesByCycle; - + //Loop over resources in each cycle and increments their usage count for(unsigned i=0; i < resources.size(); ++i) { for(unsigned j=0; j < resources[i].size(); ++j) { - + //Get Resource to check its availability int resourceNum = resources[i][j]; - + DEBUG(std::cerr << "Attempting to schedule Resource Num: " << resourceNum << " in cycle: " << currentCycle << "\n"); - - success = resourceAvailable(resourceNum, currentCycle); - + + success = resourceAvailable(resourceNum, currentCycle); + if(!success) break; - + } - + if(!success) break; - + //Increase cycle currentCycle++; } - + if(!success) return false; } @@ -168,7 +168,7 @@ //Get resource usage for this instruction InstrRUsage rUsage = msi->getInstrRUsage(node->getInst()->getOpcode()); std::vector > resources = rUsage.resourcesByCycle; - + //Loop over resources in each cycle and increments their usage count for(unsigned i=0; i < resources.size(); ++i) { for(unsigned j=0; j < resources[i].size(); ++j) { @@ -195,7 +195,7 @@ //Using the schedule, fold up into kernel and check resource conflicts as we go std::vector > tempKernel; - + int stageNum = ((schedule.rbegin()->first-offset)+1)/ II; int maxSN = 0; @@ -212,7 +212,7 @@ tempKernel.push_back(std::make_pair(*I, count)); maxSN = std::max(maxSN, count); - + } } ++count; @@ -293,7 +293,7 @@ } } } - + assert(0 && "We should always have found the def in our kernel\n"); } Index: llvm/lib/Target/SparcV9/ModuloScheduling/MSchedGraph.cpp diff -u llvm/lib/Target/SparcV9/ModuloScheduling/MSchedGraph.cpp:1.22 llvm/lib/Target/SparcV9/ModuloScheduling/MSchedGraph.cpp:1.23 --- llvm/lib/Target/SparcV9/ModuloScheduling/MSchedGraph.cpp:1.22 Wed Jul 27 00:53:44 2005 +++ llvm/lib/Target/SparcV9/ModuloScheduling/MSchedGraph.cpp Wed Jul 27 01:12:34 2005 @@ -34,8 +34,8 @@ //MSchedGraphNode constructor MSchedGraphNode::MSchedGraphNode(const MachineInstr* inst, MSchedGraph *graph, unsigned idx, - unsigned late, bool isBranch) - : Inst(inst), Parent(graph), index(idx), latency(late), + unsigned late, bool isBranch) + : Inst(inst), Parent(graph), index(idx), latency(late), isBranchInstr(isBranch) { //Add to the graph @@ -75,7 +75,7 @@ //Get the iteration difference for the edge from this node to its successor unsigned MSchedGraphNode::getIteDiff(MSchedGraphNode *succ) { - for(std::vector::iterator I = Successors.begin(), + for(std::vector::iterator I = Successors.begin(), E = Successors.end(); I != E; ++I) { if(I->getDest() == succ) @@ -89,7 +89,7 @@ //Loop over all the successors of our predecessor //return the edge the corresponds to this in edge int count = 0; - for(MSchedGraphNode::succ_iterator I = pred->succ_begin(), + for(MSchedGraphNode::succ_iterator I = pred->succ_begin(), E = pred->succ_end(); I != E; ++I) { if(*I == this) @@ -110,7 +110,7 @@ //Dtermine if pred is a predecessor of this node bool MSchedGraphNode::isPredecessor(MSchedGraphNode *pred) { - if(std::find( Predecessors.begin(), Predecessors.end(), + if(std::find( Predecessors.begin(), Predecessors.end(), pred) != Predecessors.end()) return true; else @@ -148,10 +148,10 @@ //we ignore instructions associated to the index variable since this //is a special case in Modulo Scheduling. We only want to deal with //the body of the loop. -MSchedGraph::MSchedGraph(const MachineBasicBlock *bb, - const TargetMachine &targ, - std::map &ignoreInstrs, - DependenceAnalyzer &DA, +MSchedGraph::MSchedGraph(const MachineBasicBlock *bb, + const TargetMachine &targ, + std::map &ignoreInstrs, + DependenceAnalyzer &DA, std::map &machineTollvm) : Target(targ) { @@ -159,7 +159,7 @@ assert(bb != NULL && "Basic Block is null"); BBs.push_back(bb); - + //Create nodes and edges for this BB buildNodesAndEdges(ignoreInstrs, DA, machineTollvm); @@ -171,16 +171,16 @@ //we ignore instructions associated to the index variable since this //is a special case in Modulo Scheduling. We only want to deal with //the body of the loop. -MSchedGraph::MSchedGraph(std::vector &bbs, - const TargetMachine &targ, - std::map &ignoreInstrs, - DependenceAnalyzer &DA, +MSchedGraph::MSchedGraph(std::vector &bbs, + const TargetMachine &targ, + std::map &ignoreInstrs, + DependenceAnalyzer &DA, std::map &machineTollvm) : BBs(bbs), Target(targ) { //Make sure there is at least one BB and it is not null, assert(((bbs.size() >= 1) && bbs[1] != NULL) && "Basic Block is null"); - + //Create nodes and edges for this BB buildNodesAndEdges(ignoreInstrs, DA, machineTollvm); @@ -190,15 +190,15 @@ //Copies the graph and keeps a map from old to new nodes -MSchedGraph::MSchedGraph(const MSchedGraph &G, - std::map &newNodes) +MSchedGraph::MSchedGraph(const MSchedGraph &G, + std::map &newNodes) : Target(G.Target) { BBs = G.BBs; std::map oldToNew; //Copy all nodes - for(MSchedGraph::const_iterator N = G.GraphMap.begin(), + for(MSchedGraph::const_iterator N = G.GraphMap.begin(), NE = G.GraphMap.end(); N != NE; ++N) { MSchedGraphNode *newNode = new MSchedGraphNode(*(N->second)); @@ -208,7 +208,7 @@ } //Loop over nodes and update edges to point to new nodes - for(MSchedGraph::iterator N = GraphMap.begin(), NE = GraphMap.end(); + for(MSchedGraph::iterator N = GraphMap.begin(), NE = GraphMap.end(); N != NE; ++N) { //Get the node we are dealing with @@ -231,16 +231,16 @@ //Deconstructor, deletes all nodes in the graph MSchedGraph::~MSchedGraph () { - for(MSchedGraph::iterator I = GraphMap.begin(), E = GraphMap.end(); + for(MSchedGraph::iterator I = GraphMap.begin(), E = GraphMap.end(); I != E; ++I) delete I->second; } //Print out graph void MSchedGraph::print(std::ostream &os) const { - for(MSchedGraph::const_iterator N = GraphMap.begin(), NE = GraphMap.end(); + for(MSchedGraph::const_iterator N = GraphMap.begin(), NE = GraphMap.end(); N != NE; ++N) { - + //Get the node we are dealing with MSchedGraphNode *node = &*(N->second); @@ -261,9 +261,9 @@ int MSchedGraph::totalDelay() { int sum = 0; - for(MSchedGraph::const_iterator N = GraphMap.begin(), NE = GraphMap.end(); + for(MSchedGraph::const_iterator N = GraphMap.begin(), NE = GraphMap.end(); N != NE; ++N) { - + //Get the node we are dealing with MSchedGraphNode *node = &*(N->second); sum += node->getLatency(); @@ -271,7 +271,7 @@ return sum; } //Experimental code to add edges from the branch to all nodes dependent upon it. -void hasPath(MSchedGraphNode *node, std::set &visited, +void hasPath(MSchedGraphNode *node, std::set &visited, std::set &branches, MSchedGraphNode *startNode, std::set > &newEdges ) { @@ -298,7 +298,7 @@ std::set branches; std::set nodes; - for(MSchedGraph::iterator I = GraphMap.begin(), E = GraphMap.end(); + for(MSchedGraph::iterator I = GraphMap.begin(), E = GraphMap.end(); I != E; ++I) { if(I->second->isBranch()) if(I->second->hasPredecessors()) @@ -308,7 +308,7 @@ //See if there is a path first instruction to the branches, if so, add an //iteration dependence between that node and the branch std::set > newEdges; - for(MSchedGraph::iterator I = GraphMap.begin(), E = GraphMap.end(); + for(MSchedGraph::iterator I = GraphMap.begin(), E = GraphMap.end(); I != E; ++I) { std::set visited; hasPath((I->second), visited, branches, (I->second), newEdges); @@ -347,7 +347,7 @@ void MSchedGraph::buildNodesAndEdges(std::map &ignoreInstrs, DependenceAnalyzer &DA, std::map &machineTollvm) { - + //Get Machine target information for calculating latency const TargetInstrInfo *MTI = Target.getInstrInfo(); @@ -360,28 +360,28 @@ std::vector phiInstrs; unsigned index = 0; - for(std::vector::iterator B = BBs.begin(), + for(std::vector::iterator B = BBs.begin(), BE = BBs.end(); B != BE; ++B) { - + const MachineBasicBlock *BB = *B; //Loop over instructions in MBB and add nodes and edges - for (MachineBasicBlock::const_iterator MI = BB->begin(), e = BB->end(); + for (MachineBasicBlock::const_iterator MI = BB->begin(), e = BB->end(); MI != e; ++MI) { - + //Ignore indvar instructions if(ignoreInstrs.count(MI)) { ++index; continue; } - + //Get each instruction of machine basic block, get the delay //using the op code, create a new node for it, and add to the //graph. - + MachineOpCode opCode = MI->getOpcode(); int delay; - + #if 0 // FIXME: LOOK INTO THIS //Check if subsequent instructions can be issued before //the result is ready, if so use min delay. @@ -391,78 +391,78 @@ #endif //Get delay delay = MTI->maxLatency(opCode); - + //Create new node for this machine instruction and add to the graph. //Create only if not a nop if(MTI->isNop(opCode)) continue; - + //Sparc BE does not use PHI opcode, so assert on this case assert(opCode != TargetInstrInfo::PHI && "Did not expect PHI opcode"); - + bool isBranch = false; - + //We want to flag the branch node to treat it special if(MTI->isBranch(opCode)) isBranch = true; - + //Node is created and added to the graph automatically - MSchedGraphNode *node = new MSchedGraphNode(MI, this, index, delay, + MSchedGraphNode *node = new MSchedGraphNode(MI, this, index, delay, isBranch); - + DEBUG(std::cerr << "Created Node: " << *node << "\n"); - + //Check OpCode to keep track of memory operations to add memory //dependencies later. if(MTI->isLoad(opCode) || MTI->isStore(opCode)) memInstructions.push_back(node); - + //Loop over all operands, and put them into the register number to //graph node map for determining dependencies //If an operands is a use/def, we have an anti dependence to itself for(unsigned i=0; i < MI->getNumOperands(); ++i) { //Get Operand const MachineOperand &mOp = MI->getOperand(i); - + //Check if it has an allocated register if(mOp.hasAllocatedReg()) { int regNum = mOp.getReg(); - + if(regNum != SparcV9::g0) { //Put into our map regNumtoNodeMap[regNum].push_back(std::make_pair(i, node)); } continue; } - - + + //Add virtual registers dependencies //Check if any exist in the value map already and create dependencies //between them. - if(mOp.getType() == MachineOperand::MO_VirtualRegister + if(mOp.getType() == MachineOperand::MO_VirtualRegister || mOp.getType() == MachineOperand::MO_CCRegister) { - + //Make sure virtual register value is not null assert((mOp.getVRegValue() != NULL) && "Null value is defined"); - + //Check if this is a read operation in a phi node, if so DO NOT PROCESS if(mOp.isUse() && (opCode == TargetInstrInfo::PHI)) { DEBUG(std::cerr << "Read Operation in a PHI node\n"); continue; } - + if (const Value* srcI = mOp.getVRegValue()) { - + //Find value in the map std::map >::iterator V = valuetoNodeMap.find(srcI); - + //If there is something in the map already, add edges from //those instructions //to this one we are processing if(V != valuetoNodeMap.end()) { addValueEdges(V->second, node, mOp.isUse(), mOp.isDef(), phiInstrs); - + //Add to value map V->second.push_back(std::make_pair(i,node)); } @@ -475,11 +475,11 @@ } ++index; } - + //Loop over LLVM BB, examine phi instructions, and add them to our //phiInstr list to process const BasicBlock *llvm_bb = BB->getBasicBlock(); - for(BasicBlock::const_iterator I = llvm_bb->begin(), E = llvm_bb->end(); + for(BasicBlock::const_iterator I = llvm_bb->begin(), E = llvm_bb->end(); I != E; ++I) { if(const PHINode *PN = dyn_cast(I)) { MachineCodeForInstruction & tempMvec = MachineCodeForInstruction::get(PN); @@ -490,46 +490,46 @@ } } } - + } - + addMemEdges(memInstructions, DA, machineTollvm); addMachRegEdges(regNumtoNodeMap); - + //Finally deal with PHI Nodes and Value* - for(std::vector::iterator I = phiInstrs.begin(), + for(std::vector::iterator I = phiInstrs.begin(), E = phiInstrs.end(); I != E; ++I) { - + //Get Node for this instruction std::map::iterator X; X = find(*I); - + if(X == GraphMap.end()) continue; - + MSchedGraphNode *node = X->second; - + DEBUG(std::cerr << "Adding ite diff edges for node: " << *node << "\n"); - + //Loop over operands for this instruction and add value edges for(unsigned i=0; i < (*I)->getNumOperands(); ++i) { //Get Operand const MachineOperand &mOp = (*I)->getOperand(i); - if((mOp.getType() == MachineOperand::MO_VirtualRegister + if((mOp.getType() == MachineOperand::MO_VirtualRegister || mOp.getType() == MachineOperand::MO_CCRegister) && mOp.isUse()) { - + //find the value in the map if (const Value* srcI = mOp.getVRegValue()) { - + //Find value in the map std::map >::iterator V = valuetoNodeMap.find(srcI); - + //If there is something in the map already, add edges from //those instructions //to this one we are processing if(V != valuetoNodeMap.end()) { - addValueEdges(V->second, node, mOp.isUse(), mOp.isDef(), + addValueEdges(V->second, node, mOp.isUse(), mOp.isDef(), phiInstrs, 1); } } @@ -582,7 +582,7 @@ //Loop over all machine registers in the map, and add dependencies //between the instructions that use it typedef std::map > regNodeMap; - for(regNodeMap::iterator I = regNumtoNodeMap.begin(); + for(regNodeMap::iterator I = regNumtoNodeMap.begin(); I != regNumtoNodeMap.end(); ++I) { //Get the register number int regNum = (*I).first; @@ -609,33 +609,33 @@ //Look at all instructions after this in execution order for(unsigned j=i+1; j < Nodes.size(); ++j) { - + //Sink node is a write if(Nodes[j].second->getInst()->getOperand(Nodes[j].first).isDef()) { //Src only uses the register (read) if(srcIsUse) - srcNode->addOutEdge(Nodes[j].second, + srcNode->addOutEdge(Nodes[j].second, MSchedGraphEdge::MachineRegister, MSchedGraphEdge::AntiDep); - + else if(srcIsUseandDef) { - srcNode->addOutEdge(Nodes[j].second, + srcNode->addOutEdge(Nodes[j].second, MSchedGraphEdge::MachineRegister, MSchedGraphEdge::AntiDep); - - srcNode->addOutEdge(Nodes[j].second, + + srcNode->addOutEdge(Nodes[j].second, MSchedGraphEdge::MachineRegister, MSchedGraphEdge::OutputDep); } else - srcNode->addOutEdge(Nodes[j].second, + srcNode->addOutEdge(Nodes[j].second, MSchedGraphEdge::MachineRegister, MSchedGraphEdge::OutputDep); } //Dest node is a read else { if(!srcIsUse || srcIsUseandDef) - srcNode->addOutEdge(Nodes[j].second, + srcNode->addOutEdge(Nodes[j].second, MSchedGraphEdge::MachineRegister, MSchedGraphEdge::TrueDep); } @@ -649,31 +649,31 @@ if(Nodes[j].second->getInst()->getOperand(Nodes[j].first).isDef()) { //Src only uses the register (read) if(srcIsUse) - srcNode->addOutEdge(Nodes[j].second, + srcNode->addOutEdge(Nodes[j].second, MSchedGraphEdge::MachineRegister, MSchedGraphEdge::AntiDep, 1); else if(srcIsUseandDef) { - srcNode->addOutEdge(Nodes[j].second, + srcNode->addOutEdge(Nodes[j].second, MSchedGraphEdge::MachineRegister, MSchedGraphEdge::AntiDep, 1); - - srcNode->addOutEdge(Nodes[j].second, + + srcNode->addOutEdge(Nodes[j].second, MSchedGraphEdge::MachineRegister, MSchedGraphEdge::OutputDep, 1); } else - srcNode->addOutEdge(Nodes[j].second, + srcNode->addOutEdge(Nodes[j].second, MSchedGraphEdge::MachineRegister, MSchedGraphEdge::OutputDep, 1); } //Dest node is a read else { if(!srcIsUse || srcIsUseandDef) - srcNode->addOutEdge(Nodes[j].second, + srcNode->addOutEdge(Nodes[j].second, MSchedGraphEdge::MachineRegister, MSchedGraphEdge::TrueDep,1 ); } - + } @@ -685,8 +685,8 @@ //Add edges between all loads and stores //Can be less strict with alias analysis and data dependence analysis. -void MSchedGraph::addMemEdges(const std::vector& memInst, - DependenceAnalyzer &DA, +void MSchedGraph::addMemEdges(const std::vector& memInst, + DependenceAnalyzer &DA, std::map &machineTollvm) { //Get Target machine instruction info @@ -700,7 +700,7 @@ //Get the machine opCode to determine type of memory instruction MachineOpCode srcNodeOpCode = srcInst->getOpcode(); - + //All instructions after this one in execution order have an //iteration delay of 0 for(unsigned destIndex = 0; destIndex < memInst.size(); ++destIndex) { @@ -713,19 +713,19 @@ DEBUG(std::cerr << "MInst1: " << *srcInst << "\n"); DEBUG(std::cerr << "MInst2: " << *destInst << "\n"); - + //Assuming instructions without corresponding llvm instructions //are from constant pools. if (!machineTollvm.count(srcInst) || !machineTollvm.count(destInst)) continue; - + bool useDepAnalyzer = true; //Some machine loads and stores are generated by casts, so be //conservative and always add deps Instruction *srcLLVM = machineTollvm[srcInst]; Instruction *destLLVM = machineTollvm[destInst]; - if(!isa(srcLLVM) + if(!isa(srcLLVM) && !isa(srcLLVM)) { if(isa(srcLLVM)) { if(isa(srcLLVM->getOperand(0)) || isa(srcLLVM->getOperand(1))) @@ -733,7 +733,7 @@ } useDepAnalyzer = false; } - if(!isa(destLLVM) + if(!isa(destLLVM) && !isa(destLLVM)) { if(isa(destLLVM)) { if(isa(destLLVM->getOperand(0)) || isa(destLLVM->getOperand(1))) @@ -748,29 +748,29 @@ if(destIndex < srcIndex) srcBeforeDest = false; - DependenceResult dr = DA.getDependenceInfo(machineTollvm[srcInst], - machineTollvm[destInst], + DependenceResult dr = DA.getDependenceInfo(machineTollvm[srcInst], + machineTollvm[destInst], srcBeforeDest); - - for(std::vector::iterator d = dr.dependences.begin(), + + for(std::vector::iterator d = dr.dependences.begin(), de = dr.dependences.end(); d != de; ++d) { //Add edge from load to store - memInst[srcIndex]->addOutEdge(memInst[destIndex], - MSchedGraphEdge::MemoryDep, + memInst[srcIndex]->addOutEdge(memInst[destIndex], + MSchedGraphEdge::MemoryDep, d->getDepType(), d->getIteDiff()); - + } } //Otherwise, we can not do any further analysis and must make a dependence else { - + //Get the machine opCode to determine type of memory instruction MachineOpCode destNodeOpCode = destInst->getOpcode(); //Get the Value* that we are reading from the load, always the first op const MachineOperand &mOp = srcInst->getOperand(0); const MachineOperand &mOp2 = destInst->getOperand(0); - + if(mOp.hasAllocatedReg()) if(mOp.getReg() == SparcV9::g0) continue; @@ -783,19 +783,19 @@ if(TMI->isLoad(srcNodeOpCode)) { if(TMI->isStore(destNodeOpCode)) - memInst[srcIndex]->addOutEdge(memInst[destIndex], - MSchedGraphEdge::MemoryDep, + memInst[srcIndex]->addOutEdge(memInst[destIndex], + MSchedGraphEdge::MemoryDep, MSchedGraphEdge::AntiDep, 0); } else if(TMI->isStore(srcNodeOpCode)) { if(TMI->isStore(destNodeOpCode)) - memInst[srcIndex]->addOutEdge(memInst[destIndex], - MSchedGraphEdge::MemoryDep, + memInst[srcIndex]->addOutEdge(memInst[destIndex], + MSchedGraphEdge::MemoryDep, MSchedGraphEdge::OutputDep, 0); else - memInst[srcIndex]->addOutEdge(memInst[destIndex], - MSchedGraphEdge::MemoryDep, + memInst[srcIndex]->addOutEdge(memInst[destIndex], + MSchedGraphEdge::MemoryDep, MSchedGraphEdge::TrueDep, 0); } } Index: llvm/lib/Target/SparcV9/ModuloScheduling/MSchedGraphSB.cpp diff -u llvm/lib/Target/SparcV9/ModuloScheduling/MSchedGraphSB.cpp:1.4 llvm/lib/Target/SparcV9/ModuloScheduling/MSchedGraphSB.cpp:1.5 --- llvm/lib/Target/SparcV9/ModuloScheduling/MSchedGraphSB.cpp:1.4 Wed Jul 27 00:53:44 2005 +++ llvm/lib/Target/SparcV9/ModuloScheduling/MSchedGraphSB.cpp Wed Jul 27 01:12:34 2005 @@ -36,8 +36,8 @@ //MSchedGraphSBNode constructor MSchedGraphSBNode::MSchedGraphSBNode(const MachineInstr* inst, MSchedGraphSB *graph, unsigned idx, - unsigned late, bool isBranch) - : Inst(inst), Parent(graph), index(idx), latency(late), + unsigned late, bool isBranch) + : Inst(inst), Parent(graph), index(idx), latency(late), isBranchInstr(isBranch) { //Add to the graph @@ -50,7 +50,7 @@ MSchedGraphSB *graph, unsigned idx, unsigned late, bool isPNode) : Inst(inst), otherInstrs(other), Parent(graph), index(idx), latency(late), isPredicateNode(isPNode) { - + isBranchInstr = false; @@ -94,7 +94,7 @@ //Get the iteration difference for the edge from this node to its successor unsigned MSchedGraphSBNode::getIteDiff(MSchedGraphSBNode *succ) { - for(std::vector::iterator I = Successors.begin(), + for(std::vector::iterator I = Successors.begin(), E = Successors.end(); I != E; ++I) { if(I->getDest() == succ) @@ -108,7 +108,7 @@ //Loop over all the successors of our predecessor //return the edge the corresponds to this in edge int count = 0; - for(MSchedGraphSBNode::succ_iterator I = pred->succ_begin(), + for(MSchedGraphSBNode::succ_iterator I = pred->succ_begin(), E = pred->succ_end(); I != E; ++I) { if(*I == this) @@ -129,7 +129,7 @@ //Dtermine if pred is a predecessor of this node bool MSchedGraphSBNode::isPredecessor(MSchedGraphSBNode *pred) { - if(std::find( Predecessors.begin(), Predecessors.end(), + if(std::find( Predecessors.begin(), Predecessors.end(), pred) != Predecessors.end()) return true; else @@ -167,45 +167,45 @@ //we ignore instructions associated to the index variable since this //is a special case in Modulo Scheduling. We only want to deal with //the body of the loop. -MSchedGraphSB::MSchedGraphSB(std::vector &bbs, - const TargetMachine &targ, - std::map &ignoreInstrs, - DependenceAnalyzer &DA, +MSchedGraphSB::MSchedGraphSB(std::vector &bbs, + const TargetMachine &targ, + std::map &ignoreInstrs, + DependenceAnalyzer &DA, std::map &machineTollvm) : BBs(bbs), Target(targ) { //Make sure there is at least one BB and it is not null, assert(((bbs.size() >= 1) && bbs[1] != NULL) && "Basic Block is null"); - + std::map > liveOutsideTrace; std::set llvmBBs; - for(std::vector::iterator MBB = bbs.begin(), ME = bbs.end()-1; + for(std::vector::iterator MBB = bbs.begin(), ME = bbs.end()-1; MBB != ME; ++MBB) llvmBBs.insert((*MBB)->getBasicBlock()); //create predicate nodes DEBUG(std::cerr << "Create predicate nodes\n"); - for(std::vector::iterator MBB = bbs.begin(), ME = bbs.end()-1; + for(std::vector::iterator MBB = bbs.begin(), ME = bbs.end()-1; MBB != ME; ++MBB) { //Get LLVM basic block BasicBlock *BB = (BasicBlock*) (*MBB)->getBasicBlock(); - + //Get Terminator BranchInst *b = dyn_cast(BB->getTerminator()); std::vector otherInstrs; MachineInstr *instr = 0; - + //Get the condition for the branch (we already checked if it was conditional) if(b->isConditional()) { Value *cond = b->getCondition(); - + DEBUG(std::cerr << "Condition: " << *cond << "\n"); - + assert(cond && "Condition must not be null!"); - + if(Instruction *I = dyn_cast(cond)) { MachineCodeForInstruction & tempMvec = MachineCodeForInstruction::get(I); if(tempMvec.size() > 0) { @@ -217,7 +217,7 @@ //Get Machine target information for calculating latency const TargetInstrInfo *MTI = Target.getInstrInfo(); - + MachineCodeForInstruction & tempMvec = MachineCodeForInstruction::get(b); int offset = tempMvec.size(); for (unsigned j = 0; j < tempMvec.size(); j++) { @@ -234,10 +234,10 @@ otherInstrs.push_back(mi); } } - + //Node is created and added to the graph automatically MSchedGraphSBNode *node = new MSchedGraphSBNode(instr, otherInstrs, this, (*MBB)->size()-offset-1, 3, true); - + DEBUG(std::cerr << "Created Node: " << *node << "\n"); //Now loop over all instructions and see if their def is live outside the trace @@ -264,7 +264,7 @@ } } - + } //Create nodes and edges for this BB @@ -274,15 +274,15 @@ //Copies the graph and keeps a map from old to new nodes -MSchedGraphSB::MSchedGraphSB(const MSchedGraphSB &G, - std::map &newNodes) +MSchedGraphSB::MSchedGraphSB(const MSchedGraphSB &G, + std::map &newNodes) : Target(G.Target) { BBs = G.BBs; std::map oldToNew; //Copy all nodes - for(MSchedGraphSB::const_iterator N = G.GraphMap.begin(), + for(MSchedGraphSB::const_iterator N = G.GraphMap.begin(), NE = G.GraphMap.end(); N != NE; ++N) { MSchedGraphSBNode *newNode = new MSchedGraphSBNode(*(N->second)); @@ -292,7 +292,7 @@ } //Loop over nodes and update edges to point to new nodes - for(MSchedGraphSB::iterator N = GraphMap.begin(), NE = GraphMap.end(); + for(MSchedGraphSB::iterator N = GraphMap.begin(), NE = GraphMap.end(); N != NE; ++N) { //Get the node we are dealing with @@ -315,16 +315,16 @@ //Deconstructor, deletes all nodes in the graph MSchedGraphSB::~MSchedGraphSB () { - for(MSchedGraphSB::iterator I = GraphMap.begin(), E = GraphMap.end(); + for(MSchedGraphSB::iterator I = GraphMap.begin(), E = GraphMap.end(); I != E; ++I) delete I->second; } //Print out graph void MSchedGraphSB::print(std::ostream &os) const { - for(MSchedGraphSB::const_iterator N = GraphMap.begin(), NE = GraphMap.end(); + for(MSchedGraphSB::const_iterator N = GraphMap.begin(), NE = GraphMap.end(); N != NE; ++N) { - + //Get the node we are dealing with MSchedGraphSBNode *node = &*(N->second); @@ -345,9 +345,9 @@ int MSchedGraphSB::totalDelay() { int sum = 0; - for(MSchedGraphSB::const_iterator N = GraphMap.begin(), NE = GraphMap.end(); + for(MSchedGraphSB::const_iterator N = GraphMap.begin(), NE = GraphMap.end(); N != NE; ++N) { - + //Get the node we are dealing with MSchedGraphSBNode *node = &*(N->second); sum += node->getLatency(); @@ -357,20 +357,20 @@ bool MSchedGraphSB::instrCauseException(MachineOpCode opCode) { //Check for integer divide - if(opCode == V9::SDIVXr || opCode == V9::SDIVXi + if(opCode == V9::SDIVXr || opCode == V9::SDIVXi || opCode == V9::UDIVXr || opCode == V9::UDIVXi) return true; - + //Check for loads or stores const TargetInstrInfo *MTI = Target.getInstrInfo(); - //if( MTI->isLoad(opCode) || + //if( MTI->isLoad(opCode) || if(MTI->isStore(opCode)) return true; //Check for any floating point operation const TargetSchedInfo *msi = Target.getSchedInfo(); InstrSchedClass sc = msi->getSchedClass(opCode); - + //FIXME: Should check for floating point instructions! //if(sc == SPARC_FGA || sc == SPARC_FGM) //return true; @@ -384,7 +384,7 @@ DependenceAnalyzer &DA, std::map &machineTollvm, std::map > &liveOutsideTrace) { - + //Get Machine target information for calculating latency const TargetInstrInfo *MTI = Target.getInstrInfo(); @@ -398,48 +398,48 @@ unsigned index = 0; MSchedGraphSBNode *lastPred = 0; - - for(std::vector::iterator B = BBs.begin(), + + for(std::vector::iterator B = BBs.begin(), BE = BBs.end(); B != BE; ++B) { - + const MachineBasicBlock *BB = *B; //Loop over instructions in MBB and add nodes and edges - for (MachineBasicBlock::const_iterator MI = BB->begin(), e = BB->end(); + for (MachineBasicBlock::const_iterator MI = BB->begin(), e = BB->end(); MI != e; ++MI) { - + //Ignore indvar instructions if(ignoreInstrs.count(MI)) { ++index; continue; } - + //Get each instruction of machine basic block, get the delay //using the op code, create a new node for it, and add to the //graph. - + MachineOpCode opCode = MI->getOpcode(); int delay; - + //Get delay delay = MTI->maxLatency(opCode); - + //Create new node for this machine instruction and add to the graph. //Create only if not a nop if(MTI->isNop(opCode)) continue; - + //Sparc BE does not use PHI opcode, so assert on this case assert(opCode != TargetInstrInfo::PHI && "Did not expect PHI opcode"); - + bool isBranch = false; //Skip branches if(MTI->isBranch(opCode)) continue; - + //Node is created and added to the graph automatically MSchedGraphSBNode *node = 0; if(!GraphMap.count(MI)){ @@ -453,7 +453,7 @@ if(lastPred) { lastPred->addOutEdge(node, MSchedGraphSBEdge::PredDep, MSchedGraphSBEdge::NonDataDep, 0); - + if(liveOutsideTrace.count(lastPred)) { for(std::set::iterator L = liveOutsideTrace[lastPred].begin(), LE = liveOutsideTrace[lastPred].end(); L != LE; ++L) lastPred->addOutEdge(GraphMap[*L], MSchedGraphSBEdge::PredDep, @@ -461,7 +461,7 @@ } } - + lastPred = node; } } @@ -476,59 +476,59 @@ MSchedGraphSBEdge::NonDataDep, 0); } } - + //Check OpCode to keep track of memory operations to add memory //dependencies later. if(MTI->isLoad(opCode) || MTI->isStore(opCode)) memInstructions.push_back(node); - + //Loop over all operands, and put them into the register number to //graph node map for determining dependencies //If an operands is a use/def, we have an anti dependence to itself for(unsigned i=0; i < MI->getNumOperands(); ++i) { //Get Operand const MachineOperand &mOp = MI->getOperand(i); - + //Check if it has an allocated register if(mOp.hasAllocatedReg()) { int regNum = mOp.getReg(); - + if(regNum != SparcV9::g0) { //Put into our map regNumtoNodeMap[regNum].push_back(std::make_pair(i, node)); } continue; } - - + + //Add virtual registers dependencies //Check if any exist in the value map already and create dependencies //between them. - if(mOp.getType() == MachineOperand::MO_VirtualRegister + if(mOp.getType() == MachineOperand::MO_VirtualRegister || mOp.getType() == MachineOperand::MO_CCRegister) { - + //Make sure virtual register value is not null assert((mOp.getVRegValue() != NULL) && "Null value is defined"); - + //Check if this is a read operation in a phi node, if so DO NOT PROCESS if(mOp.isUse() && (opCode == TargetInstrInfo::PHI)) { DEBUG(std::cerr << "Read Operation in a PHI node\n"); continue; } - + if (const Value* srcI = mOp.getVRegValue()) { - + //Find value in the map std::map >::iterator V = valuetoNodeMap.find(srcI); - + //If there is something in the map already, add edges from //those instructions //to this one we are processing if(V != valuetoNodeMap.end()) { addValueEdges(V->second, node, mOp.isUse(), mOp.isDef(), phiInstrs); - + //Add to value map V->second.push_back(std::make_pair(i,node)); } @@ -541,11 +541,11 @@ } ++index; } - + //Loop over LLVM BB, examine phi instructions, and add them to our //phiInstr list to process const BasicBlock *llvm_bb = BB->getBasicBlock(); - for(BasicBlock::const_iterator I = llvm_bb->begin(), E = llvm_bb->end(); + for(BasicBlock::const_iterator I = llvm_bb->begin(), E = llvm_bb->end(); I != E; ++I) { if(const PHINode *PN = dyn_cast(I)) { MachineCodeForInstruction & tempMvec = MachineCodeForInstruction::get(PN); @@ -556,46 +556,46 @@ } } } - + } - + addMemEdges(memInstructions, DA, machineTollvm); addMachRegEdges(regNumtoNodeMap); - + //Finally deal with PHI Nodes and Value* - for(std::vector::iterator I = phiInstrs.begin(), + for(std::vector::iterator I = phiInstrs.begin(), E = phiInstrs.end(); I != E; ++I) { - + //Get Node for this instruction std::map::iterator X; X = find(*I); - + if(X == GraphMap.end()) continue; - + MSchedGraphSBNode *node = X->second; - + DEBUG(std::cerr << "Adding ite diff edges for node: " << *node << "\n"); - + //Loop over operands for this instruction and add value edges for(unsigned i=0; i < (*I)->getNumOperands(); ++i) { //Get Operand const MachineOperand &mOp = (*I)->getOperand(i); - if((mOp.getType() == MachineOperand::MO_VirtualRegister + if((mOp.getType() == MachineOperand::MO_VirtualRegister || mOp.getType() == MachineOperand::MO_CCRegister) && mOp.isUse()) { - + //find the value in the map if (const Value* srcI = mOp.getVRegValue()) { - + //Find value in the map std::map >::iterator V = valuetoNodeMap.find(srcI); - + //If there is something in the map already, add edges from //those instructions //to this one we are processing if(V != valuetoNodeMap.end()) { - addValueEdges(V->second, node, mOp.isUse(), mOp.isDef(), + addValueEdges(V->second, node, mOp.isUse(), mOp.isDef(), phiInstrs, 1); } } @@ -648,7 +648,7 @@ //Loop over all machine registers in the map, and add dependencies //between the instructions that use it typedef std::map > regNodeMap; - for(regNodeMap::iterator I = regNumtoNodeMap.begin(); + for(regNodeMap::iterator I = regNumtoNodeMap.begin(); I != regNumtoNodeMap.end(); ++I) { //Get the register number int regNum = (*I).first; @@ -675,33 +675,33 @@ //Look at all instructions after this in execution order for(unsigned j=i+1; j < Nodes.size(); ++j) { - + //Sink node is a write if(Nodes[j].second->getInst()->getOperand(Nodes[j].first).isDef()) { //Src only uses the register (read) if(srcIsUse) - srcNode->addOutEdge(Nodes[j].second, + srcNode->addOutEdge(Nodes[j].second, MSchedGraphSBEdge::MachineRegister, MSchedGraphSBEdge::AntiDep); - + else if(srcIsUseandDef) { - srcNode->addOutEdge(Nodes[j].second, + srcNode->addOutEdge(Nodes[j].second, MSchedGraphSBEdge::MachineRegister, MSchedGraphSBEdge::AntiDep); - - srcNode->addOutEdge(Nodes[j].second, + + srcNode->addOutEdge(Nodes[j].second, MSchedGraphSBEdge::MachineRegister, MSchedGraphSBEdge::OutputDep); } else - srcNode->addOutEdge(Nodes[j].second, + srcNode->addOutEdge(Nodes[j].second, MSchedGraphSBEdge::MachineRegister, MSchedGraphSBEdge::OutputDep); } //Dest node is a read else { if(!srcIsUse || srcIsUseandDef) - srcNode->addOutEdge(Nodes[j].second, + srcNode->addOutEdge(Nodes[j].second, MSchedGraphSBEdge::MachineRegister, MSchedGraphSBEdge::TrueDep); } @@ -715,31 +715,31 @@ if(Nodes[j].second->getInst()->getOperand(Nodes[j].first).isDef()) { //Src only uses the register (read) if(srcIsUse) - srcNode->addOutEdge(Nodes[j].second, + srcNode->addOutEdge(Nodes[j].second, MSchedGraphSBEdge::MachineRegister, MSchedGraphSBEdge::AntiDep, 1); else if(srcIsUseandDef) { - srcNode->addOutEdge(Nodes[j].second, + srcNode->addOutEdge(Nodes[j].second, MSchedGraphSBEdge::MachineRegister, MSchedGraphSBEdge::AntiDep, 1); - - srcNode->addOutEdge(Nodes[j].second, + + srcNode->addOutEdge(Nodes[j].second, MSchedGraphSBEdge::MachineRegister, MSchedGraphSBEdge::OutputDep, 1); } else - srcNode->addOutEdge(Nodes[j].second, + srcNode->addOutEdge(Nodes[j].second, MSchedGraphSBEdge::MachineRegister, MSchedGraphSBEdge::OutputDep, 1); } //Dest node is a read else { if(!srcIsUse || srcIsUseandDef) - srcNode->addOutEdge(Nodes[j].second, + srcNode->addOutEdge(Nodes[j].second, MSchedGraphSBEdge::MachineRegister, MSchedGraphSBEdge::TrueDep,1 ); } - + } @@ -751,8 +751,8 @@ //Add edges between all loads and stores //Can be less strict with alias analysis and data dependence analysis. -void MSchedGraphSB::addMemEdges(const std::vector& memInst, - DependenceAnalyzer &DA, +void MSchedGraphSB::addMemEdges(const std::vector& memInst, + DependenceAnalyzer &DA, std::map &machineTollvm) { //Get Target machine instruction info @@ -766,7 +766,7 @@ //Get the machine opCode to determine type of memory instruction MachineOpCode srcNodeOpCode = srcInst->getOpcode(); - + //All instructions after this one in execution order have an //iteration delay of 0 for(unsigned destIndex = 0; destIndex < memInst.size(); ++destIndex) { @@ -779,19 +779,19 @@ DEBUG(std::cerr << "MInst1: " << *srcInst << "\n"); DEBUG(std::cerr << "MInst2: " << *destInst << "\n"); - + //Assuming instructions without corresponding llvm instructions //are from constant pools. if (!machineTollvm.count(srcInst) || !machineTollvm.count(destInst)) continue; - + bool useDepAnalyzer = true; //Some machine loads and stores are generated by casts, so be //conservative and always add deps Instruction *srcLLVM = machineTollvm[srcInst]; Instruction *destLLVM = machineTollvm[destInst]; - if(!isa(srcLLVM) + if(!isa(srcLLVM) && !isa(srcLLVM)) { if(isa(srcLLVM)) { if(isa(srcLLVM->getOperand(0)) || isa(srcLLVM->getOperand(1))) @@ -799,7 +799,7 @@ } useDepAnalyzer = false; } - if(!isa(destLLVM) + if(!isa(destLLVM) && !isa(destLLVM)) { if(isa(destLLVM)) { if(isa(destLLVM->getOperand(0)) || isa(destLLVM->getOperand(1))) @@ -814,29 +814,29 @@ if(destIndex < srcIndex) srcBeforeDest = false; - DependenceResult dr = DA.getDependenceInfo(machineTollvm[srcInst], - machineTollvm[destInst], + DependenceResult dr = DA.getDependenceInfo(machineTollvm[srcInst], + machineTollvm[destInst], srcBeforeDest); - - for(std::vector::iterator d = dr.dependences.begin(), + + for(std::vector::iterator d = dr.dependences.begin(), de = dr.dependences.end(); d != de; ++d) { //Add edge from load to store - memInst[srcIndex]->addOutEdge(memInst[destIndex], - MSchedGraphSBEdge::MemoryDep, + memInst[srcIndex]->addOutEdge(memInst[destIndex], + MSchedGraphSBEdge::MemoryDep, d->getDepType(), d->getIteDiff()); - + } } //Otherwise, we can not do any further analysis and must make a dependence else { - + //Get the machine opCode to determine type of memory instruction MachineOpCode destNodeOpCode = destInst->getOpcode(); //Get the Value* that we are reading from the load, always the first op const MachineOperand &mOp = srcInst->getOperand(0); const MachineOperand &mOp2 = destInst->getOperand(0); - + if(mOp.hasAllocatedReg()) if(mOp.getReg() == SparcV9::g0) continue; @@ -849,19 +849,19 @@ if(TMI->isLoad(srcNodeOpCode)) { if(TMI->isStore(destNodeOpCode)) - memInst[srcIndex]->addOutEdge(memInst[destIndex], - MSchedGraphSBEdge::MemoryDep, + memInst[srcIndex]->addOutEdge(memInst[destIndex], + MSchedGraphSBEdge::MemoryDep, MSchedGraphSBEdge::AntiDep, 0); } else if(TMI->isStore(srcNodeOpCode)) { if(TMI->isStore(destNodeOpCode)) - memInst[srcIndex]->addOutEdge(memInst[destIndex], - MSchedGraphSBEdge::MemoryDep, + memInst[srcIndex]->addOutEdge(memInst[destIndex], + MSchedGraphSBEdge::MemoryDep, MSchedGraphSBEdge::OutputDep, 0); else - memInst[srcIndex]->addOutEdge(memInst[destIndex], - MSchedGraphSBEdge::MemoryDep, + memInst[srcIndex]->addOutEdge(memInst[destIndex], + MSchedGraphSBEdge::MemoryDep, MSchedGraphSBEdge::TrueDep, 0); } } Index: llvm/lib/Target/SparcV9/ModuloScheduling/ModuloScheduling.cpp diff -u llvm/lib/Target/SparcV9/ModuloScheduling/ModuloScheduling.cpp:1.51 llvm/lib/Target/SparcV9/ModuloScheduling/ModuloScheduling.cpp:1.52 --- llvm/lib/Target/SparcV9/ModuloScheduling/ModuloScheduling.cpp:1.51 Wed Jul 27 00:53:44 2005 +++ llvm/lib/Target/SparcV9/ModuloScheduling/ModuloScheduling.cpp Wed Jul 27 01:12:34 2005 @@ -112,7 +112,7 @@ //Label each edge with the type of dependence std::string edgelabel = ""; switch (I.getEdge().getDepOrderType()) { - + case MSchedGraphEdge::TrueDep: edgelabel = "True"; break; @@ -120,11 +120,11 @@ case MSchedGraphEdge::AntiDep: edgelabel = "Anti"; break; - + case MSchedGraphEdge::OutputDep: edgelabel = "Output"; break; - + default: edgelabel = "Unknown"; break; @@ -171,14 +171,14 @@ //Iterate over BasicBlocks and put them into our worklist if they are valid for (MachineFunction::iterator BI = MF.begin(); BI != MF.end(); ++BI) - if(MachineBBisValid(BI)) { + if(MachineBBisValid(BI)) { if(BI->size() < 100) { Worklist.push_back(&*BI); ++ValidLoops; } else ++JumboBB; - + } defaultInst = 0; @@ -393,7 +393,7 @@ ++LoopsWithCalls; return false; } - + //Look for conditional move if(OC == V9::MOVRZr || OC == V9::MOVRZi || OC == V9::MOVRLEZr || OC == V9::MOVRLEZi || OC == V9::MOVRLZr || OC == V9::MOVRLZi || OC == V9::MOVRNZr || OC == V9::MOVRNZi @@ -752,13 +752,13 @@ processedOneEdge = true; int succALAP = -1; succALAP = calculateALAP(*P, MII, maxASAP, node); - + assert(succALAP != -1 && "Successors ALAP should have been caclulated"); - + int iteDiff = P.getEdge().getIteDiff(); - + int currentSuccValue = succALAP - node->getLatency() + iteDiff * MII; - + DEBUG(std::cerr << "succ ALAP: " << succALAP << ", iteDiff: " << iteDiff << ", SuccLatency: " << (*P)->getLatency() << ", Current ALAP succ: " << currentSuccValue << "\n"); minSuccValue = std::min(minSuccValue, currentSuccValue); @@ -893,7 +893,7 @@ destBENode = recurrence[i+1]; break; } - + } } @@ -982,7 +982,7 @@ std::vector recc; //Dump recurrence for now DEBUG(std::cerr << "Starting Recc\n"); - + int totalDelay = 0; int totalDistance = 0; MSchedGraphNode *lastN = 0; @@ -1015,7 +1015,7 @@ DEBUG(std::cerr << "End Recc\n"); CircCount++; - if(start && end) { + if(start && end) { //Insert reccurrence into the list DEBUG(std::cerr << "Ignore Edge from!!: " << *start << " to " << *end << "\n"); edgesToIgnore.insert(std::make_pair(newNodes[start], (newNodes[end])->getInEdgeNum(newNodes[start]))); @@ -1031,7 +1031,7 @@ int value = totalDelay-(RecMII * totalDistance); int lastII = II; while(value < 0) { - + lastII = RecMII; RecMII--; value = totalDelay-(RecMII * totalDistance); @@ -1053,7 +1053,7 @@ for(std::vector::iterator N = SCC.begin(), NE = SCC.end(); N != NE; ++N) { DEBUG(std::cerr << **N << "\n"); totalDelay += (*N)->getLatency(); - + for(unsigned i = 0; i < (*N)->succ_size(); ++i) { MSchedGraphEdge *edge = (*N)->getSuccessor(i); if(find(SCC.begin(), SCC.end(), edge->getDest()) != SCC.end()) { @@ -1063,7 +1063,7 @@ start = *N; end = edge->getDest(); } - + } } @@ -1079,7 +1079,7 @@ assert( (start && end) && "Must have start and end node to ignore edge for SCC"); - if(start && end) { + if(start && end) { //Insert reccurrence into the list DEBUG(std::cerr << "Ignore Edge from!!: " << *start << " to " << *end << "\n"); edgesToIgnore.insert(std::make_pair(newNodes[start], (newNodes[end])->getInEdgeNum(newNodes[start]))); @@ -1144,7 +1144,7 @@ if(nextSCC.size() > 1) { std::cerr << "SCC size: " << nextSCC.size() << "\n"; - + for(unsigned i = 0; i < nextSCC.size(); ++i) { //Loop over successor and see if in scc, then count edge MSchedGraphNode *node = nextSCC[i]; @@ -1209,7 +1209,7 @@ } else break; - } + } DEBUG(std::cerr << "Num Circuits found: " << CircCount << "\n"); } @@ -1303,7 +1303,7 @@ //Check if we should ignore this edge first if(ignoreEdge(node,*S)) continue; - + //check if successor is in this recurrence, we will get to it eventually if(new_reccurrence.count(*S)) continue; @@ -1372,7 +1372,7 @@ void ModuloSchedulingPass::computePartialOrder() { TIME_REGION(X, "calculatePartialOrder"); - + DEBUG(std::cerr << "Computing Partial Order\n"); //Only push BA branches onto the final node order, we put other @@ -1380,13 +1380,13 @@ //it a specific order instead of relying on BA being there? std::vector branches; - + //Steps to add a recurrence to the partial order 1) Find reccurrence //with the highest RecMII. Add it to the partial order. 2) For each //recurrence with decreasing RecMII, add it to the partial order //along with any nodes that connect this recurrence to recurrences //already in the partial order - for(std::set > >::reverse_iterator + for(std::set > >::reverse_iterator I = recurrenceList.rbegin(), E=recurrenceList.rend(); I !=E; ++I) { std::set new_recurrence; @@ -1445,15 +1445,15 @@ partialOrder.push_back(new_recurrence); - + //Dump out partial order - DEBUG(for(std::vector >::iterator I = partialOrder.begin(), + DEBUG(for(std::vector >::iterator I = partialOrder.begin(), E = partialOrder.end(); I !=E; ++I) { std::cerr << "Start set in PO\n"; for(std::set::iterator J = I->begin(), JE = I->end(); J != JE; ++J) std::cerr << "PO:" << **J << "\n"; }); - + } } @@ -1530,7 +1530,7 @@ //Check if we are supposed to ignore this edge or not if(ignoreEdge(*P,FinalNodeOrder[j])) continue; - + if(CurrentSet.count(*P)) if(std::find(FinalNodeOrder.begin(), FinalNodeOrder.end(), *P) == FinalNodeOrder.end()) IntersectResult.insert(*P); @@ -1617,7 +1617,7 @@ //Get node attributes MSNodeAttributes nodeAttr= nodeToAttributesMap.find(*J)->second; //assert(nodeAttr != nodeToAttributesMap.end() && "Node not in attributes map!"); - + if(maxASAP <= nodeAttr.ASAP) { maxASAP = nodeAttr.ASAP; node = *J; @@ -1637,15 +1637,15 @@ while(IntersectCurrent.size() > 0) { DEBUG(std::cerr << "Intersection is not empty, so find heighest height\n"); - + int MOB = 0; int height = 0; MSchedGraphNode *highestHeightNode = *(IntersectCurrent.begin()); - + //Find node in intersection with highest heigh and lowest MOB for(std::set::iterator I = IntersectCurrent.begin(), E = IntersectCurrent.end(); I != E; ++I) { - + //Get current nodes properties MSNodeAttributes nodeAttr= nodeToAttributesMap.find(*I)->second; @@ -1662,7 +1662,7 @@ } } } - + //Append our node with greatest height to the NodeOrder if(std::find(FinalNodeOrder.begin(), FinalNodeOrder.end(), highestHeightNode) == FinalNodeOrder.end()) { DEBUG(std::cerr << "Adding node to Final Order: " << *highestHeightNode << "\n"); @@ -1695,9 +1695,9 @@ //Reset Intersect to reflect changes in OrderNodes IntersectCurrent.clear(); predIntersect(*CurrentSet, IntersectCurrent); - + } //End If TOP_DOWN - + //Begin if BOTTOM_UP else { DEBUG(std::cerr << "Order is BOTTOM UP\n"); @@ -1711,12 +1711,12 @@ int MOB = 0; int depth = 0; MSchedGraphNode *highestDepthNode = *(IntersectCurrent.begin()); - + for(std::set::iterator I = IntersectCurrent.begin(), E = IntersectCurrent.end(); I != E; ++I) { //Find node attribute in graph MSNodeAttributes nodeAttr= nodeToAttributesMap.find(*I)->second; - + if(depth < nodeAttr.depth) { highestDepthNode = *I; depth = nodeAttr.depth; @@ -1730,8 +1730,8 @@ } } } - - + + //Append highest depth node to the NodeOrder if(std::find(FinalNodeOrder.begin(), FinalNodeOrder.end(), highestDepthNode) == FinalNodeOrder.end()) { @@ -1740,7 +1740,7 @@ } //Remove heightestDepthNode from IntersectOrder IntersectCurrent.erase(highestDepthNode); - + //Intersect heightDepthNode's pred with CurrentSet for(MSchedGraphNode::pred_iterator P = highestDepthNode->pred_begin(), @@ -1748,23 +1748,23 @@ if(CurrentSet->count(*P)) { if(ignoreEdge(*P, highestDepthNode)) continue; - + //If not already in Intersect, add if(!IntersectCurrent.count(*P)) IntersectCurrent.insert(*P); } } - + } //End while loop over Intersect Size - + //Change order order = TOP_DOWN; - + //Reset IntersectCurrent to reflect changes in OrderNodes IntersectCurrent.clear(); succIntersect(*CurrentSet, IntersectCurrent); } //End if BOTTOM_DOWN - + DEBUG(std::cerr << "Current Intersection Size: " << IntersectCurrent.size() << "\n"); } //End Wrapping while loop @@ -1808,7 +1808,7 @@ bool initialLSVal = false; bool initialESVal = false; int EarlyStart = 0; - int LateStart = 0; + int LateStart = 0; bool hasSucc = false; bool hasPred = false; bool sched; @@ -1826,10 +1826,10 @@ //or successors of the node we are trying to schedule for(MSSchedule::schedule_iterator nodesByCycle = schedule.begin(), nodesByCycleEnd = schedule.end(); nodesByCycle != nodesByCycleEnd; ++nodesByCycle) { - + //For this cycle, get the vector of nodes schedule and loop over it for(std::vector::iterator schedNode = nodesByCycle->second.begin(), SNE = nodesByCycle->second.end(); schedNode != SNE; ++schedNode) { - + if((*I)->isPredecessor(*schedNode)) { int diff = (*I)->getInEdge(*schedNode).getIteDiff(); int ES_Temp = nodesByCycle->first + (*schedNode)->getLatency() - diff * II; @@ -1877,7 +1877,7 @@ EarlyStart = std::max(EarlyStart, ES_Temp); hasPred = true; } - + if((*I)->isSuccessor(*B)) { int diff = (*B)->getInEdge(*I).getIteDiff(); int LS_Temp = (II+count-1) - (*I)->getLatency() + diff * II; @@ -1886,7 +1886,7 @@ LateStart = std::min(LateStart, LS_Temp); hasSucc = true; } - + count--; }*/ @@ -1916,7 +1916,7 @@ success = scheduleNode(*I, EarlyStart, EarlyStart + II - 1); if(!success) { - ++II; + ++II; schedule.clear(); break; } @@ -1933,7 +1933,7 @@ } DEBUG(std::cerr << "Final II: " << II << "\n"); } - + if(II >= capII) { DEBUG(std::cerr << "Maximum II reached, giving up\n"); @@ -2033,18 +2033,18 @@ if(inKernel[j].count(&*MI)) { MachineInstr *instClone = MI->clone(); machineBB->push_back(instClone); - + //If its a branch, insert a nop if(mii->isBranch(instClone->getOpcode())) BuildMI(machineBB, V9::NOP, 0); - + DEBUG(std::cerr << "Cloning: " << *MI << "\n"); //After cloning, we may need to save the value that this instruction defines for(unsigned opNum=0; opNum < MI->getNumOperands(); ++opNum) { Instruction *tmp; - + //get machine operand MachineOperand &mOp = instClone->getOperand(opNum); if(mOp.getType() == MachineOperand::MO_VirtualRegister && mOp.isDef()) { @@ -2053,18 +2053,18 @@ if(valuesToSave.count(mOp.getVRegValue())) { //Save copy in tmpInstruction tmp = new TmpInstruction(mOp.getVRegValue()); - + //Add TmpInstruction to safe LLVM Instruction MCFI MachineCodeForInstruction & tempMvec = MachineCodeForInstruction::get(defaultInst); tempMvec.addTemp((Value*) tmp); DEBUG(std::cerr << "Value: " << *(mOp.getVRegValue()) << " New Value: " << *tmp << " Stage: " << i << "\n"); - + newValues[mOp.getVRegValue()][i]= tmp; newValLocation[tmp] = machineBB; DEBUG(std::cerr << "Machine Instr Operands: " << *(mOp.getVRegValue()) << ", 0, " << *tmp << "\n"); - + //Create machine instruction and put int machineBB MachineInstr *saveValue; if(mOp.getVRegValue()->getType() == Type::FloatTy) @@ -2073,7 +2073,7 @@ saveValue = BuildMI(machineBB, V9::FMOVD, 3).addReg(mOp.getVRegValue()).addRegDef(tmp); else saveValue = BuildMI(machineBB, V9::ORr, 3).addReg(mOp.getVRegValue()).addImm(0).addRegDef(tmp); - + DEBUG(std::cerr << "Created new machine instr: " << *saveValue << "\n"); } @@ -2161,26 +2161,26 @@ if(inKernel[j].count(&*MI)) { DEBUG(std::cerr << "Cloning instruction " << *MI << "\n"); MachineInstr *clone = MI->clone(); - + //Update operands that need to use the result from the phi for(unsigned opNum=0; opNum < clone->getNumOperands(); ++opNum) { //get machine operand const MachineOperand &mOp = clone->getOperand(opNum); - + if((mOp.getType() == MachineOperand::MO_VirtualRegister && mOp.isUse())) { - + DEBUG(std::cerr << "Writing PHI for " << (mOp.getVRegValue()) << "\n"); - + //If this is the last instructions for the max iterations ago, don't update operands if(inEpilogue.count(mOp.getVRegValue())) if(inEpilogue[mOp.getVRegValue()] == i) continue; - + //Quickly write appropriate phis for this operand if(newValues.count(mOp.getVRegValue())) { if(newValues[mOp.getVRegValue()].count(i)) { Instruction *tmp = new TmpInstruction(newValues[mOp.getVRegValue()][i]); - + //Get machine code for this instruction MachineCodeForInstruction & tempMvec = MachineCodeForInstruction::get(defaultInst); tempMvec.addTemp((Value*) tmp); @@ -2193,7 +2193,7 @@ valPHIs[mOp.getVRegValue()] = tmp; } } - + if(valPHIs.count(mOp.getVRegValue())) { //Update the operand in the cloned instruction clone->getOperand(opNum).setValueReg(valPHIs[mOp.getVRegValue()]); @@ -2215,7 +2215,7 @@ BL.insert(BLI,machineBB); epilogues.push_back(machineBB); llvm_epilogues.push_back(llvmBB); - + DEBUG(std::cerr << "EPILOGUE #" << i << "\n"); DEBUG(machineBB->print(std::cerr)); } @@ -2272,14 +2272,14 @@ //Only create phi if the operand def is from a stage before this one if(schedule.defPreviousStage(mOp.getVRegValue(), I->second)) { TmpInstruction *tmp = new TmpInstruction(mOp.getVRegValue()); - + //Get machine code for this instruction MachineCodeForInstruction & tempMvec = MachineCodeForInstruction::get(defaultInst); tempMvec.addTemp((Value*) tmp); - + //Update the operand in the cloned instruction instClone->getOperand(i).setValueReg(tmp); - + //save this as our final phi finalPHIValue[mOp.getVRegValue()] = tmp; newValLocation[tmp] = machineBB; @@ -2295,9 +2295,9 @@ if(I->second != schedule.getMaxStage()) { if(mOp.getType() == MachineOperand::MO_VirtualRegister && mOp.isDef()) { if(valuesToSave.count(mOp.getVRegValue())) { - + TmpInstruction *tmp = new TmpInstruction(mOp.getVRegValue()); - + //Get machine code for this instruction MachineCodeForInstruction & tempVec = MachineCodeForInstruction::get(defaultInst); tempVec.addTemp((Value*) tmp); @@ -2310,8 +2310,8 @@ saveValue = BuildMI(machineBB, V9::FMOVD, 3).addReg(mOp.getVRegValue()).addRegDef(tmp); else saveValue = BuildMI(machineBB, V9::ORr, 3).addReg(mOp.getVRegValue()).addImm(0).addRegDef(tmp); - - + + //Save for future cleanup kernelValue[mOp.getVRegValue()] = tmp; newValLocation[tmp] = machineBB; @@ -2383,7 +2383,7 @@ //Get machine code for this instruction MachineCodeForInstruction & tempMvec = MachineCodeForInstruction::get(defaultInst); tempMvec.addTemp((Value*) tmp); - + MachineInstr *saveValue = BuildMI(*machineBB, machineBB->begin(), V9::PHI, 3).addReg(lastPhi).addReg(I->second).addRegDef(tmp); DEBUG(std::cerr << "Resulting PHI: " << *saveValue << "\n"); @@ -2439,7 +2439,7 @@ //Get Operand const MachineOperand &mOp = I->getOperand(i); assert(mOp.getType() == MachineOperand::MO_VirtualRegister && "Should be a Value*\n"); - + if(!tmp) { tmp = new TmpInstruction(mOp.getVRegValue()); addToMCFI.push_back(tmp); @@ -2463,10 +2463,10 @@ BuildMI(*(newValLocation[mOp.getVRegValue()]), ++inst, V9::FMOVD, 3).addReg(mOp.getVRegValue()).addRegDef(tmp); else BuildMI(*(newValLocation[mOp.getVRegValue()]), ++inst, V9::ORr, 3).addReg(mOp.getVRegValue()).addImm(0).addRegDef(tmp); - + break; } - + } } @@ -2480,11 +2480,11 @@ BuildMI(*kernelBB, I, V9::FMOVD, 3).addReg(tmp).addRegDef(mOp.getVRegValue()); else BuildMI(*kernelBB, I, V9::ORr, 3).addReg(tmp).addImm(0).addRegDef(mOp.getVRegValue()); - - + + worklist.push_back(std::make_pair(kernelBB, I)); } - + } } @@ -2515,12 +2515,12 @@ //Get Operand const MachineOperand &mOp = I->getOperand(i); assert(mOp.getType() == MachineOperand::MO_VirtualRegister && "Should be a Value*\n"); - + if(!tmp) { tmp = new TmpInstruction(mOp.getVRegValue()); addToMCFI.push_back(tmp); } - + //Now for all our arguments we read, OR to the new TmpInstruction that we created if(mOp.isUse()) { DEBUG(std::cerr << "Use: " << mOp << "\n"); @@ -2539,13 +2539,13 @@ BuildMI(*(newValLocation[mOp.getVRegValue()]), ++inst, V9::FMOVD, 3).addReg(mOp.getVRegValue()).addRegDef(tmp); else BuildMI(*(newValLocation[mOp.getVRegValue()]), ++inst, V9::ORr, 3).addReg(mOp.getVRegValue()).addImm(0).addRegDef(tmp); - + break; } - + } - + } else { //Remove the phi and replace it with an OR @@ -2559,7 +2559,7 @@ worklist.push_back(std::make_pair(*MB,I)); } - + } } @@ -2581,7 +2581,7 @@ DEBUG(std::cerr << "Deleting PHI " << *I->second << "\n"); I->first->erase(I->second); - + } @@ -2617,7 +2617,7 @@ for(unsigned i=0; i < inst->getNumOperands(); ++i) { //get machine operand const MachineOperand &mOp = inst->getOperand(i); - + if(mOp.getType() == MachineOperand::MO_VirtualRegister && mOp.isUse()) { //find the value in the map if (const Value* srcI = mOp.getVRegValue()) { @@ -2629,7 +2629,7 @@ //make sure its def is not of the same stage as this instruction //because it will be consumed before its used Instruction *defInst = (Instruction*) srcI; - + //Should we save this value? bool save = true; @@ -2638,20 +2638,20 @@ continue; MachineInstr *defInstr = defMap[srcI]; - + if(lastInstrs.count(defInstr)) { if(lastInstrs[defInstr] == I->second) { save = false; - + } } - + if(save) { assert(!phiUses.count(srcI) && "Did not expect to see phi use twice"); if(isa(srcI)) phiUses[srcI] = I->second; - + valuesToSave[srcI] = std::make_pair(I->first, i); } @@ -2669,7 +2669,7 @@ } } } - + if(mOp.getType() != MachineOperand::MO_VirtualRegister && mOp.isUse()) { assert("Our assumption is wrong. We have another type of register that needs to be saved\n"); } @@ -2706,7 +2706,7 @@ BasicBlock *llvmKernelBB = new BasicBlock("Kernel", (Function*) (BB->getBasicBlock()->getParent())); MachineBasicBlock *machineKernelBB = new MachineBasicBlock(llvmKernelBB); - + MachineFunction *F = (((MachineBasicBlock*)BB)->getParent()); MachineFunction::BasicBlockListType &BL = F->getBasicBlockList(); MachineFunction::BasicBlockListType::iterator BLI = BB; @@ -2815,14 +2815,14 @@ if(TMI->isBranch(OC)) { for(unsigned opNum = 0; opNum < mInst->getNumOperands(); ++opNum) { MachineOperand &mOp = mInst->getOperand(opNum); - + if(mOp.getType() == MachineOperand::MO_PCRelativeDisp) { if(mOp.getVRegValue() == BB->getBasicBlock()) mOp.setValueReg(llvmKernelBB); else if(llvm_epilogues.size() > 0) { assert(origBranchExit == 0 && "There should only be one branch out of the loop"); - + origBranchExit = mOp.getVRegValue(); mOp.setValueReg(llvm_epilogues[0]); } Index: llvm/lib/Target/SparcV9/ModuloScheduling/ModuloSchedulingSuperBlock.cpp diff -u llvm/lib/Target/SparcV9/ModuloScheduling/ModuloSchedulingSuperBlock.cpp:1.4 llvm/lib/Target/SparcV9/ModuloScheduling/ModuloSchedulingSuperBlock.cpp:1.5 --- llvm/lib/Target/SparcV9/ModuloScheduling/ModuloSchedulingSuperBlock.cpp:1.4 Wed Jul 27 00:53:44 2005 +++ llvm/lib/Target/SparcV9/ModuloScheduling/ModuloSchedulingSuperBlock.cpp Wed Jul 27 01:12:34 2005 @@ -73,11 +73,11 @@ Statistic<> NumLoops("moduloschedSB-numLoops", "Total Number of Loops"); Statistic<> NumSB("moduloschedSB-numSuperBlocks", "Total Number of SuperBlocks"); Statistic<> BBWithCalls("modulosched-BBCalls", "Basic Blocks rejected due to calls"); - Statistic<> BBWithCondMov("modulosched-loopCondMov", + Statistic<> BBWithCondMov("modulosched-loopCondMov", "Basic Blocks rejected due to conditional moves"); - Statistic<> SBResourceConstraint("modulosched-resourceConstraint", + Statistic<> SBResourceConstraint("modulosched-resourceConstraint", "Loops constrained by resources"); - Statistic<> SBRecurrenceConstraint("modulosched-recurrenceConstraint", + Statistic<> SBRecurrenceConstraint("modulosched-recurrenceConstraint", "Loops constrained by recurrences"); Statistic<> SBFinalIISum("modulosched-finalIISum", "Sum of all final II"); Statistic<> SBIISum("modulosched-IISum", "Sum of all theoretical II"); @@ -113,7 +113,7 @@ //Label each edge with the type of dependence std::string edgelabel = ""; switch (I.getEdge().getDepOrderType()) { - + case MSchedGraphSBEdge::TrueDep: edgelabel = "True"; break; @@ -121,11 +121,11 @@ case MSchedGraphSBEdge::AntiDep: edgelabel = "Anti"; break; - + case MSchedGraphSBEdge::OutputDep: edgelabel = "Output"; break; - + case MSchedGraphSBEdge::NonDataDep: edgelabel = "Pred"; break; @@ -149,7 +149,7 @@ bool ModuloSchedulingSBPass::runOnFunction(Function &F) { bool Changed = false; - + //Get MachineFunction MachineFunction &MF = MachineFunction::get(&F); @@ -160,55 +160,55 @@ //Worklist of superblocks std::vector > Worklist; FindSuperBlocks(F, LI, Worklist); - + DEBUG(if(Worklist.size() == 0) std::cerr << "No superblocks in function to ModuloSchedule\n"); - + //Loop over worklist and ModuloSchedule each SuperBlock for(std::vector >::iterator SB = Worklist.begin(), SBE = Worklist.end(); SB != SBE; ++SB) { - + //Print out Superblock DEBUG(std::cerr << "ModuloScheduling SB: \n"; - for(std::vector::const_iterator BI = SB->begin(), + for(std::vector::const_iterator BI = SB->begin(), BE = SB->end(); BI != BE; ++BI) { (*BI)->print(std::cerr);}); - + if(!CreateDefMap(*SB)) { defaultInst = 0; defMap.clear(); continue; } - MSchedGraphSB *MSG = new MSchedGraphSB(*SB, target, indVarInstrs[*SB], DA, + MSchedGraphSB *MSG = new MSchedGraphSB(*SB, target, indVarInstrs[*SB], DA, machineTollvm[*SB]); //Write Graph out to file DEBUG(WriteGraphToFileSB(std::cerr, F.getName(), MSG)); - + //Calculate Resource II int ResMII = calculateResMII(*SB); //Calculate Recurrence II int RecMII = calculateRecMII(MSG, ResMII); - + DEBUG(std::cerr << "Number of reccurrences found: " << recurrenceList.size() << "\n"); - + //Our starting initiation interval is the maximum of RecMII and ResMII if(RecMII < ResMII) ++SBRecurrenceConstraint; else ++SBResourceConstraint; - + II = std::max(RecMII, ResMII); int mII = II; - - + + //Print out II, RecMII, and ResMII DEBUG(std::cerr << "II starts out as " << II << " ( RecMII=" << RecMII << " and ResMII=" << ResMII << ")\n"); - + //Calculate Node Properties calculateNodeAttributes(MSG, ResMII); - + //Dump node properties if in debug mode DEBUG(for(std::map::iterator I = nodeToAttributesMap.begin(), E = nodeToAttributesMap.end(); I !=E; ++I) { @@ -216,11 +216,11 @@ << I->second.ALAP << " MOB: " << I->second.MOB << " Depth: " << I->second.depth << " Height: " << I->second.height << "\n"; }); - + //Put nodes in order to schedule them computePartialOrder(); - + //Dump out partial order DEBUG(for(std::vector >::iterator I = partialOrder.begin(), E = partialOrder.end(); I !=E; ++I) { @@ -231,19 +231,19 @@ //Place nodes in final order orderNodes(); - + //Dump out order of nodes DEBUG(for(std::vector::iterator I = FinalNodeOrder.begin(), E = FinalNodeOrder.end(); I != E; ++I) { std::cerr << "FO:" << **I << "\n"; }); - + //Finally schedule nodes bool haveSched = computeSchedule(*SB, MSG); - + //Print out final schedule DEBUG(schedule.print(std::cerr)); - + //Final scheduling step is to reconstruct the loop only if we actual have //stage > 0 if(haveSched) { @@ -253,13 +253,13 @@ //Changed = true; SBIISum += mII; SBFinalIISum += II; - + if(schedule.getMaxStage() == 0) ++SBSameStage; } else ++SBNoSched; - + //Clear out our maps for the next basic block that is processed nodeToAttributesMap.clear(); partialOrder.clear(); @@ -267,7 +267,7 @@ FinalNodeOrder.clear(); schedule.clear(); defMap.clear(); - + } return Changed; } @@ -277,7 +277,7 @@ //Get MachineFunction MachineFunction &MF = MachineFunction::get(&F); - + //Map of LLVM BB to machine BB std::map bbMap; @@ -295,16 +295,16 @@ //If loop is not single entry, try the next one if(!L->getLoopPreheader()) continue; - + //Check size of this loop, we don't want SBB loops if(L->getBlocks().size() == 1) continue; - + //Check if this loop contains no sub loops if(L->getSubLoops().size() == 0) { - + std::vector superBlock; - + //Get Loop Headers BasicBlock *header = L->getHeader(); @@ -324,7 +324,7 @@ for(succ_iterator I = succ_begin(current), E = succ_end(current); I != E; ++I) { if(L->contains(*I)) { - if(!next) + if(!next) next = *I; else { done = true; @@ -333,7 +333,7 @@ } } } - + if(success) { superBlock.push_back(currentMBB); if(next == header) @@ -352,7 +352,7 @@ } - + if(success) { @@ -366,7 +366,7 @@ } } } - + if(success) { if(getIndVar(superBlock, bbMap, indexMap)) { ++SBValid; @@ -379,9 +379,9 @@ } } } - - - bool ModuloSchedulingSBPass::getIndVar(std::vector &superBlock, std::map &bbMap, + + + bool ModuloSchedulingSBPass::getIndVar(std::vector &superBlock, std::map &bbMap, std::map &indexMap) { //See if we can get induction var instructions std::set llvmSuperBlock; @@ -391,23 +391,23 @@ //Get Target machine instruction info const TargetInstrInfo *TMI = target.getInstrInfo(); - + //Get the loop back branch BranchInst *b = dyn_cast(((BasicBlock*) (superBlock[superBlock.size()-1])->getBasicBlock())->getTerminator()); std::set indVar; if(b->isConditional()) { - //Get the condition for the branch + //Get the condition for the branch Value *cond = b->getCondition(); - + DEBUG(std::cerr << "Condition: " << *cond << "\n"); - + //List of instructions associated with induction variable std::vector stack; - + //Add branch indVar.insert(b); - + if(Instruction *I = dyn_cast(cond)) if(bbMap.count(I->getParent())) { if (!assocIndVar(I, indVar, stack, bbMap, superBlock[(superBlock.size()-1)]->getBasicBlock(), llvmSuperBlock)) @@ -423,11 +423,11 @@ } //Dump out instructions associate with indvar for debug reasons - DEBUG(for(std::set::iterator N = indVar.begin(), NE = indVar.end(); + DEBUG(for(std::set::iterator N = indVar.begin(), NE = indVar.end(); N != NE; ++N) { std::cerr << **N << "\n"; }); - + //Create map of machine instr to llvm instr std::map mllvm; for(std::vector::iterator MBB = superBlock.begin(), MBE = superBlock.end(); MBB != MBE; ++MBB) { @@ -442,9 +442,9 @@ //Convert list of LLVM Instructions to list of Machine instructions std::map mIndVar; - for(std::set::iterator N = indVar.begin(), + for(std::set::iterator N = indVar.begin(), NE = indVar.end(); N != NE; ++N) { - + //If we have a load, we can't handle this loop because //there is no way to preserve dependences between loads //and stores @@ -462,23 +462,23 @@ DEBUG(std::cerr << *(tempMvec[j]) << " at index " << indexMap[(MachineInstr*) tempMvec[j]] << "\n"); } } - + //Put into a map for future access indVarInstrs[superBlock] = mIndVar; machineTollvm[superBlock] = mllvm; - + return true; - + } - bool ModuloSchedulingSBPass::assocIndVar(Instruction *I, + bool ModuloSchedulingSBPass::assocIndVar(Instruction *I, std::set &indVar, - std::vector &stack, - std::map &bbMap, + std::vector &stack, + std::map &bbMap, const BasicBlock *last, std::set &llvmSuperBlock) { stack.push_back(I); - + //If this is a phi node, check if its the canonical indvar if(PHINode *PN = dyn_cast(I)) { if(llvmSuperBlock.count(PN->getParent())) { @@ -506,24 +506,24 @@ } } } - + stack.pop_back(); return true; } - + /// This function checks if a Machine Basic Block is valid for modulo /// scheduling. This means that it has no control flow (if/else or /// calls) in the block. Currently ModuloScheduling only works on /// single basic block loops. - bool ModuloSchedulingSBPass::MachineBBisValid(const MachineBasicBlock *BI, - std::map &indexMap, + bool ModuloSchedulingSBPass::MachineBBisValid(const MachineBasicBlock *BI, + std::map &indexMap, unsigned &offset) { - + //Check size of our basic block.. make sure we have more then just the terminator in it if(BI->getBasicBlock()->size() == 1) return false; - + //Get Target machine instruction info const TargetInstrInfo *TMI = target.getInstrInfo(); @@ -537,7 +537,7 @@ ++BBWithCalls; return false; } - + //Look for conditional move if(OC == V9::MOVRZr || OC == V9::MOVRZi || OC == V9::MOVRLEZr || OC == V9::MOVRLEZi || OC == V9::MOVRLZr || OC == V9::MOVRLZi || OC == V9::MOVRNZr || OC == V9::MOVRNZi @@ -567,7 +567,7 @@ bool ModuloSchedulingSBPass::CreateDefMap(std::vector &SB) { defaultInst = 0; - for(std::vector::iterator BI = SB.begin(), + for(std::vector::iterator BI = SB.begin(), BE = SB.end(); BI != BE; ++BI) { for(MachineBasicBlock::const_iterator I = (*BI)->begin(), E = (*BI)->end(); I != E; ++I) { @@ -585,7 +585,7 @@ defMap[V] = (MachineInstr*) &*I; } } - + //See if we can use this Value* as our defaultInst if(!defaultInst && mOp.getType() == MachineOperand::MO_VirtualRegister) { Value *V = mOp.getVRegValue(); @@ -595,10 +595,10 @@ } } } - + if(!defaultInst) return false; - + return true; } @@ -670,22 +670,22 @@ } return ResMII; - + } /// calculateRecMII - Calculates the value of the highest recurrence /// By value we mean the total latency/distance int ModuloSchedulingSBPass::calculateRecMII(MSchedGraphSB *graph, int MII) { - + TIME_REGION(X, "calculateRecMII"); - + findAllCircuits(graph, MII); int RecMII = 0; - + for(std::set > >::iterator I = recurrenceList.begin(), E=recurrenceList.end(); I !=E; ++I) { RecMII = std::max(RecMII, I->first); } - + return MII; } @@ -722,7 +722,7 @@ for(std::vector::iterator N = SCC.begin(), NE = SCC.end(); N != NE; ++N) { DEBUG(std::cerr << **N << "\n"); totalDelay += (*N)->getLatency(); - + for(unsigned i = 0; i < (*N)->succ_size(); ++i) { MSchedGraphSBEdge *edge = (*N)->getSuccessor(i); if(find(SCC.begin(), SCC.end(), edge->getDest()) != SCC.end()) { @@ -732,7 +732,7 @@ start = *N; end = edge->getDest(); } - + } } @@ -744,11 +744,11 @@ } DEBUG(std::cerr << "End Recc\n"); - + assert( (start && end) && "Must have start and end node to ignore edge for SCC"); - if(start && end) { + if(start && end) { //Insert reccurrence into the list DEBUG(std::cerr << "Ignore Edge from!!: " << *start << " to " << *end << "\n"); edgesToIgnore.insert(std::make_pair(newNodes[start], (newNodes[end])->getInEdgeNum(newNodes[start]))); @@ -818,7 +818,7 @@ std::vector recc; //Dump recurrence for now DEBUG(std::cerr << "Starting Recc\n"); - + int totalDelay = 0; int totalDistance = 0; MSchedGraphSBNode *lastN = 0; @@ -851,7 +851,7 @@ DEBUG(std::cerr << "End Recc\n"); CircCountSB++; - if(start && end) { + if(start && end) { //Insert reccurrence into the list DEBUG(std::cerr << "Ignore Edge from!!: " << *start << " to " << *end << "\n"); edgesToIgnore.insert(std::make_pair(newNodes[start], (newNodes[end])->getInEdgeNum(newNodes[start]))); @@ -867,7 +867,7 @@ int value = totalDelay-(RecMII * totalDistance); int lastII = II; while(value < 0) { - + lastII = RecMII; RecMII--; value = totalDelay-(RecMII * totalDistance); @@ -930,7 +930,7 @@ if(nextSCC.size() > 1) { DEBUG(std::cerr << "SCC size: " << nextSCC.size() << "\n"); - + for(unsigned i = 0; i < nextSCC.size(); ++i) { //Loop over successor and see if in scc, then count edge MSchedGraphSBNode *node = nextSCC[i]; @@ -941,7 +941,7 @@ } DEBUG(std::cerr << "Num Edges: " << numEdges << "\n"); } - + //Ignore self loops if(nextSCC.size() > 1) { @@ -996,7 +996,7 @@ } else break; - } + } DEBUG(std::cerr << "Num Circuits found: " << CircCountSB << "\n"); } /// calculateNodeAttributes - The following properties are calculated for @@ -1129,13 +1129,13 @@ processedOneEdge = true; int succALAP = -1; succALAP = calculateALAP(*P, MII, maxASAP, node); - + assert(succALAP != -1 && "Successors ALAP should have been caclulated"); - + int iteDiff = P.getEdge().getIteDiff(); - + int currentSuccValue = succALAP - node->getLatency() + iteDiff * MII; - + DEBUG(std::cerr << "succ ALAP: " << succALAP << ", iteDiff: " << iteDiff << ", SuccLatency: " << (*P)->getLatency() << ", Current ALAP succ: " << currentSuccValue << "\n"); minSuccValue = std::min(minSuccValue, currentSuccValue); @@ -1230,7 +1230,7 @@ void ModuloSchedulingSBPass::computePartialOrder() { TIME_REGION(X, "calculatePartialOrder"); - + DEBUG(std::cerr << "Computing Partial Order\n"); //Steps to add a recurrence to the partial order 1) Find reccurrence @@ -1238,7 +1238,7 @@ //recurrence with decreasing RecMII, add it to the partial order //along with any nodes that connect this recurrence to recurrences //already in the partial order - for(std::set > >::reverse_iterator + for(std::set > >::reverse_iterator I = recurrenceList.rbegin(), E=recurrenceList.rend(); I !=E; ++I) { std::set new_recurrence; @@ -1339,7 +1339,7 @@ } void ModuloSchedulingSBPass::connectedComponentSet(MSchedGraphSBNode *node, std::set &ccSet, std::set &lastNodes) { - + //Add to final set if( !ccSet.count(node) && lastNodes.count(node)) { lastNodes.erase(node); @@ -1370,7 +1370,7 @@ //Check if we should ignore this edge first if(ignoreEdge(node,*S)) continue; - + //check if successor is in this recurrence, we will get to it eventually if(new_reccurrence.count(*S)) continue; @@ -1465,7 +1465,7 @@ //Get node attributes MSNodeSBAttributes nodeAttr= nodeToAttributesMap.find(*J)->second; //assert(nodeAttr != nodeToAttributesMap.end() && "Node not in attributes map!"); - + if(maxASAP <= nodeAttr.ASAP) { maxASAP = nodeAttr.ASAP; node = *J; @@ -1485,15 +1485,15 @@ while(IntersectCurrent.size() > 0) { DEBUG(std::cerr << "Intersection is not empty, so find heighest height\n"); - + int MOB = 0; int height = 0; MSchedGraphSBNode *highestHeightNode = *(IntersectCurrent.begin()); - + //Find node in intersection with highest heigh and lowest MOB for(std::set::iterator I = IntersectCurrent.begin(), E = IntersectCurrent.end(); I != E; ++I) { - + //Get current nodes properties MSNodeSBAttributes nodeAttr= nodeToAttributesMap.find(*I)->second; @@ -1510,7 +1510,7 @@ } } } - + //Append our node with greatest height to the NodeOrder if(std::find(FinalNodeOrder.begin(), FinalNodeOrder.end(), highestHeightNode) == FinalNodeOrder.end()) { DEBUG(std::cerr << "Adding node to Final Order: " << *highestHeightNode << "\n"); @@ -1543,9 +1543,9 @@ //Reset Intersect to reflect changes in OrderNodes IntersectCurrent.clear(); predIntersect(*CurrentSet, IntersectCurrent); - + } //End If TOP_DOWN - + //Begin if BOTTOM_UP else { DEBUG(std::cerr << "Order is BOTTOM UP\n"); @@ -1559,12 +1559,12 @@ int MOB = 0; int depth = 0; MSchedGraphSBNode *highestDepthNode = *(IntersectCurrent.begin()); - + for(std::set::iterator I = IntersectCurrent.begin(), E = IntersectCurrent.end(); I != E; ++I) { //Find node attribute in graph MSNodeSBAttributes nodeAttr= nodeToAttributesMap.find(*I)->second; - + if(depth < nodeAttr.depth) { highestDepthNode = *I; depth = nodeAttr.depth; @@ -1578,8 +1578,8 @@ } } } - - + + //Append highest depth node to the NodeOrder if(std::find(FinalNodeOrder.begin(), FinalNodeOrder.end(), highestDepthNode) == FinalNodeOrder.end()) { @@ -1588,7 +1588,7 @@ } //Remove heightestDepthNode from IntersectOrder IntersectCurrent.erase(highestDepthNode); - + //Intersect heightDepthNode's pred with CurrentSet for(MSchedGraphSBNode::pred_iterator P = highestDepthNode->pred_begin(), @@ -1596,23 +1596,23 @@ if(CurrentSet->count(*P)) { if(ignoreEdge(*P, highestDepthNode)) continue; - + //If not already in Intersect, add if(!IntersectCurrent.count(*P)) IntersectCurrent.insert(*P); } } - + } //End while loop over Intersect Size - + //Change order order = TOP_DOWN; - + //Reset IntersectCurrent to reflect changes in OrderNodes IntersectCurrent.clear(); succIntersect(*CurrentSet, IntersectCurrent); } //End if BOTTOM_DOWN - + DEBUG(std::cerr << "Current Intersection Size: " << IntersectCurrent.size() << "\n"); } //End Wrapping while loop @@ -1643,7 +1643,7 @@ //Check if we are supposed to ignore this edge or not if(ignoreEdge(*P,FinalNodeOrder[j])) continue; - + if(CurrentSet.count(*P)) if(std::find(FinalNodeOrder.begin(), FinalNodeOrder.end(), *P) == FinalNodeOrder.end()) IntersectResult.insert(*P); @@ -1693,7 +1693,7 @@ bool initialLSVal = false; bool initialESVal = false; int EarlyStart = 0; - int LateStart = 0; + int LateStart = 0; bool hasSucc = false; bool hasPred = false; bool sched; @@ -1711,10 +1711,10 @@ //or successors of the node we are trying to schedule for(MSScheduleSB::schedule_iterator nodesByCycle = schedule.begin(), nodesByCycleEnd = schedule.end(); nodesByCycle != nodesByCycleEnd; ++nodesByCycle) { - + //For this cycle, get the vector of nodes schedule and loop over it for(std::vector::iterator schedNode = nodesByCycle->second.begin(), SNE = nodesByCycle->second.end(); schedNode != SNE; ++schedNode) { - + if((*I)->isPredecessor(*schedNode)) { int diff = (*I)->getInEdge(*schedNode).getIteDiff(); int ES_Temp = nodesByCycle->first + (*schedNode)->getLatency() - diff * II; @@ -1775,7 +1775,7 @@ success = scheduleNode(*I, EarlyStart, EarlyStart + II - 1); if(!success) { - ++II; + ++II; schedule.clear(); break; } @@ -1791,7 +1791,7 @@ schedule.clear(); } DEBUG(std::cerr << "Final II: " << II << "\n"); - + } if(II >= capII) { @@ -1877,7 +1877,7 @@ //Loop over kernel and only look at instructions from a stage > 0 //Look at its operands and save values *'s that are read for(MSScheduleSB::kernel_iterator I = schedule.kernel_begin(), E = schedule.kernel_end(); I != E; ++I) { - + if(I->second !=0) { //For this instruction, get the Value*'s that it reads and put them into the set. //Assert if there is an operand of another type that we need to save @@ -1887,7 +1887,7 @@ for(unsigned i=0; i < inst->getNumOperands(); ++i) { //get machine operand const MachineOperand &mOp = inst->getOperand(i); - + if(mOp.getType() == MachineOperand::MO_VirtualRegister && mOp.isUse()) { //find the value in the map if (const Value* srcI = mOp.getVRegValue()) { @@ -1899,7 +1899,7 @@ //make sure its def is not of the same stage as this instruction //because it will be consumed before its used Instruction *defInst = (Instruction*) srcI; - + //Should we save this value? bool save = true; @@ -1908,27 +1908,27 @@ continue; MachineInstr *defInstr = defMap[srcI]; - + if(lastInstrs.count(defInstr)) { if(lastInstrs[defInstr] == I->second) { save = false; - + } } - + if(save) valuesToSave[srcI] = std::make_pair(I->first, i); - } + } } - + if(mOp.getType() != MachineOperand::MO_VirtualRegister && mOp.isUse()) { assert("Our assumption is wrong. We have another type of register that needs to be saved\n"); } } } - - + + //Do a check to see if instruction was moved below its original branch if(MTI->isBranch(I->first->getOpcode())) { seenBranchesBB.insert(I->first->getParent()); @@ -1959,7 +1959,7 @@ //Map to keep track of where the inner branches go std::map sideExits; - + //Write prologue if(schedule.getMaxStage() != 0) writePrologues(prologues, SB, llvm_prologues, valuesToSave, newValues, newValLocation); @@ -1970,7 +1970,7 @@ for(unsigned i = 0; i < SB.size(); ++i) { llvmKernelBBs.push_back(new BasicBlock("Kernel", parent)); - + machineKernelBBs.push_back(new MachineBasicBlock(llvmKernelBBs[i])); (((MachineBasicBlock*)SB[0])->getParent())->getBasicBlockList().push_back(machineKernelBBs[i]); } @@ -2067,7 +2067,7 @@ for(unsigned j = 0; j < prologues[i].size(); ++j) { MachineBasicBlock *currentMBB = prologues[i][j]; - + //Find terminator since getFirstTerminator does not work! for(MachineBasicBlock::reverse_iterator mInst = currentMBB->rbegin(), mInstEnd = currentMBB->rend(); mInst != mInstEnd; ++mInst) { MachineOpCode OC = mInst->getOpcode(); @@ -2089,17 +2089,17 @@ else if(mOp.getVRegValue() == SB[j+1]->getBasicBlock()) { mOp.setValueReg(llvm_prologues[i][j+1]); } - + } } - + DEBUG(std::cerr << "New Prologue Branch: " << *mInst << "\n"); } } //Update llvm basic block with our new branch instr DEBUG(std::cerr << SB[i]->getBasicBlock()->getTerminator() << "\n"); - + const BranchInst *branchVal = dyn_cast(SB[i]->getBasicBlock()->getTerminator()); //Check for inner branch @@ -2144,7 +2144,7 @@ if(TMI->isBranch(OC)) { for(unsigned opNum = 0; opNum < mInst->getNumOperands(); ++opNum) { MachineOperand &mOp = mInst->getOperand(opNum); - + if(mOp.getType() == MachineOperand::MO_PCRelativeDisp) { //Deal with inner kernel branches if(i < machineKernelBB.size()-1) { @@ -2170,10 +2170,10 @@ //Update kernelLLVM branches const BranchInst *branchVal = dyn_cast(SB[0]->getBasicBlock()->getTerminator()); - + //deal with inner branch if(i < machineKernelBB.size()-1) { - + //Find our side exit LLVM basic block BasicBlock *sideExit = 0; for(unsigned s = 0; s < branchVal->getNumSuccessors(); ++s) { @@ -2204,38 +2204,38 @@ } if(schedule.getMaxStage() != 0) { - + //Lastly add unconditional branches for the epilogues for(unsigned i = 0; i < epilogues.size(); ++i) { for(unsigned j=0; j < epilogues[i].size(); ++j) { //Now since we don't have fall throughs, add a unconditional //branch to the next prologue - + //Before adding these, we need to check if the epilogue already has //a branch in it bool hasBranch = false; /*if(j < epilogues[i].size()-1) { MachineBasicBlock *currentMBB = epilogues[i][j]; for(MachineBasicBlock::reverse_iterator mInst = currentMBB->rbegin(), mInstEnd = currentMBB->rend(); mInst != mInstEnd; ++mInst) { - + MachineOpCode OC = mInst->getOpcode(); - + //If its a branch update its branchto if(TMI->isBranch(OC)) { hasBranch = true; for(unsigned opNum = 0; opNum < mInst->getNumOperands(); ++opNum) { MachineOperand &mOp = mInst->getOperand(opNum); if (mOp.getType() == MachineOperand::MO_PCRelativeDisp) { - + if(mOp.getVRegValue() != sideExits[SB[j]]) { mOp.setValueReg(llvm_epilogues[i][j+1]); } - + } } - - + + DEBUG(std::cerr << "New Epilogue Branch: " << *mInst << "\n"); } } @@ -2249,7 +2249,7 @@ }*/ if(!hasBranch) { - + //Handle inner branches if(j < epilogues[i].size()-1) { BuildMI(epilogues[i][j], V9::BA, 1).addPCDisp(llvm_epilogues[i][j+1]); @@ -2257,24 +2257,24 @@ llvm_epilogues[i][j]); } else { - + //Check if this is the last epilogue if(i != epilogues.size()-1) { BuildMI(epilogues[i][j], V9::BA, 1).addPCDisp(llvm_epilogues[i+1][0]); //Add unconditional branch to end of epilogue TerminatorInst *newBranch = new BranchInst(llvm_epilogues[i+1][0], llvm_epilogues[i][j]); - + } else { BuildMI(epilogues[i][j], V9::BA, 1).addPCDisp(kernel_exit); TerminatorInst *newBranch = new BranchInst(kernel_exit, llvm_epilogues[i][j]); } } - + //Add one more nop! BuildMI(epilogues[i][j], V9::NOP, 0); - + } } } @@ -2283,10 +2283,10 @@ //Find all llvm basic blocks that branch to the loop entry and //change to our first prologue. const BasicBlock *llvmBB = SB[0]->getBasicBlock(); - + std::vectorPreds (pred_begin(llvmBB), pred_end(llvmBB)); - - for(std::vector::iterator P = Preds.begin(), + + for(std::vector::iterator P = Preds.begin(), PE = Preds.end(); P != PE; ++P) { if(*P == SB[SB.size()-1]->getBasicBlock()) continue; @@ -2295,7 +2295,7 @@ DEBUG((*P)->print(std::cerr)); //Get the Terminator instruction for this basic block and print it out //DEBUG(std::cerr << *((*P)->getTerminator()) << "\n"); - + //Update the terminator TerminatorInst *term = ((BasicBlock*)*P)->getTerminator(); for(unsigned i=0; i < term->getNumSuccessors(); ++i) { @@ -2383,7 +2383,7 @@ std::vector current_prologue; std::vector current_llvm_prologue; - for(std::vector::iterator MB = origSB.begin(), + for(std::vector::iterator MB = origSB.begin(), MBE = origSB.end(); MB != MBE; ++MB) { const MachineBasicBlock *MBB = *MB; //Create new llvm and machine bb @@ -2394,46 +2394,46 @@ for(int j = i; j >= 0; --j) { //iterate over instructions in original bb - for(MachineBasicBlock::const_iterator MI = MBB->begin(), + for(MachineBasicBlock::const_iterator MI = MBB->begin(), ME = MBB->end(); ME != MI; ++MI) { if(inKernel[j].count(&*MI)) { MachineInstr *instClone = MI->clone(); machineBB->push_back(instClone); - + //If its a branch, insert a nop if(mii->isBranch(instClone->getOpcode())) BuildMI(machineBB, V9::NOP, 0); - - + + DEBUG(std::cerr << "Cloning: " << *MI << "\n"); - + //After cloning, we may need to save the value that this instruction defines for(unsigned opNum=0; opNum < MI->getNumOperands(); ++opNum) { Instruction *tmp; - + //get machine operand MachineOperand &mOp = instClone->getOperand(opNum); - if(mOp.getType() == MachineOperand::MO_VirtualRegister + if(mOp.getType() == MachineOperand::MO_VirtualRegister && mOp.isDef()) { //Check if this is a value we should save if(valuesToSave.count(mOp.getVRegValue())) { //Save copy in tmpInstruction tmp = new TmpInstruction(mOp.getVRegValue()); - + //Add TmpInstruction to safe LLVM Instruction MCFI MachineCodeForInstruction & tempMvec = MachineCodeForInstruction::get(defaultInst); tempMvec.addTemp((Value*) tmp); - DEBUG(std::cerr << "Value: " << *(mOp.getVRegValue()) + DEBUG(std::cerr << "Value: " << *(mOp.getVRegValue()) << " New Value: " << *tmp << " Stage: " << i << "\n"); - + newValues[mOp.getVRegValue()][i]= tmp; newValLocation[tmp] = machineBB; - DEBUG(std::cerr << "Machine Instr Operands: " + DEBUG(std::cerr << "Machine Instr Operands: " << *(mOp.getVRegValue()) << ", 0, " << *tmp << "\n"); - + //Create machine instruction and put int machineBB MachineInstr *saveValue; if(mOp.getVRegValue()->getType() == Type::FloatTy) @@ -2442,7 +2442,7 @@ saveValue = BuildMI(machineBB, V9::FMOVD, 3).addReg(mOp.getVRegValue()).addRegDef(tmp); else saveValue = BuildMI(machineBB, V9::ORr, 3).addReg(mOp.getVRegValue()).addImm(0).addRegDef(tmp); - + DEBUG(std::cerr << "Created new machine instr: " << *saveValue << "\n"); } @@ -2458,7 +2458,7 @@ DEBUG(std::cerr << "Replaced this value: " << mOp.getVRegValue() << " With:" << (newValues[mOp.getVRegValue()][i-1]) << "\n"); //Update the operand with the right value mOp.setValueReg(newValues[mOp.getVRegValue()][i-1]); - + //Remove this value since we have consumed it //NOTE: Should this only be done if j != maxStage? consumedValues[oldV][i-1] = (newValues[oldV][i-1]); @@ -2511,55 +2511,55 @@ for(int i = schedule.getMaxStage()-1; i >= 0; --i) { std::vector current_epilogue; std::vector current_llvm_epilogue; - + for(std::vector::iterator MB = origSB.begin(), MBE = origSB.end(); MB != MBE; ++MB) { const MachineBasicBlock *MBB = *MB; BasicBlock *llvmBB = new BasicBlock("EPILOGUE", (Function*) (MBB->getBasicBlock()->getParent())); MachineBasicBlock *machineBB = new MachineBasicBlock(llvmBB); - + DEBUG(std::cerr << " Epilogue #: " << i << "\n"); - + std::map inEpilogue; - + for(MachineBasicBlock::const_iterator MI = MBB->begin(), ME = MBB->end(); ME != MI; ++MI) { for(int j=schedule.getMaxStage(); j > i; --j) { if(inKernel[j].count(&*MI)) { DEBUG(std::cerr << "Cloning instruction " << *MI << "\n"); MachineInstr *clone = MI->clone(); - + //Update operands that need to use the result from the phi for(unsigned opNum=0; opNum < clone->getNumOperands(); ++opNum) { //get machine operand const MachineOperand &mOp = clone->getOperand(opNum); - + if((mOp.getType() == MachineOperand::MO_VirtualRegister && mOp.isUse())) { - + DEBUG(std::cerr << "Writing PHI for " << (mOp.getVRegValue()) << "\n"); - + //If this is the last instructions for the max iterations ago, don't update operands if(inEpilogue.count(mOp.getVRegValue())) if(inEpilogue[mOp.getVRegValue()] == i) continue; - + //Quickly write appropriate phis for this operand if(newValues.count(mOp.getVRegValue())) { if(newValues[mOp.getVRegValue()].count(i)) { Instruction *tmp = new TmpInstruction(newValues[mOp.getVRegValue()][i]); - + //Get machine code for this instruction MachineCodeForInstruction & tempMvec = MachineCodeForInstruction::get(defaultInst); tempMvec.addTemp((Value*) tmp); - + //assert of no kernelPHI for this value assert(kernelPHIs[mOp.getVRegValue()][i] !=0 && "Must have final kernel phi to construct epilogue phi"); - + MachineInstr *saveValue = BuildMI(machineBB, V9::PHI, 3).addReg(newValues[mOp.getVRegValue()][i]).addReg(kernelPHIs[mOp.getVRegValue()][i]).addRegDef(tmp); DEBUG(std::cerr << "Resulting PHI: " << *saveValue << "\n"); valPHIs[mOp.getVRegValue()] = tmp; } } - + if(valPHIs.count(mOp.getVRegValue())) { //Update the operand in the cloned instruction clone->getOperand(opNum).setValueReg(valPHIs[mOp.getVRegValue()]); @@ -2568,7 +2568,7 @@ else if((mOp.getType() == MachineOperand::MO_VirtualRegister && mOp.isDef())) { inEpilogue[mOp.getVRegValue()] = i; } - + } machineBB->push_back(clone); //if(MTI->isBranch(clone->getOpcode())) @@ -2580,11 +2580,11 @@ current_epilogue.push_back(machineBB); current_llvm_epilogue.push_back(llvmBB); } - + DEBUG(std::cerr << "EPILOGUE #" << i << "\n"); DEBUG(for(std::vector::iterator B = current_epilogue.begin(), BE = current_epilogue.end(); B != BE; ++B) { (*B)->print(std::cerr);}); - + epilogues.push_back(current_epilogue); llvm_epilogues.push_back(current_llvm_epilogue); } @@ -2635,7 +2635,7 @@ seenBranch = true; numBr++; } - + DEBUG(std::cerr << "Cloned Inst: " << *instClone << "\n"); //Loop over Machine Operands @@ -2659,14 +2659,14 @@ //Only create phi if the operand def is from a stage before this one if(schedule.defPreviousStage(mOp.getVRegValue(), I->second)) { TmpInstruction *tmp = new TmpInstruction(mOp.getVRegValue()); - + //Get machine code for this instruction MachineCodeForInstruction & tempMvec = MachineCodeForInstruction::get(defaultInst); tempMvec.addTemp((Value*) tmp); - + //Update the operand in the cloned instruction instClone->getOperand(i).setValueReg(tmp); - + //save this as our final phi finalPHIValue[mOp.getVRegValue()] = tmp; newValLocation[tmp] = machineBB[index]; @@ -2682,9 +2682,9 @@ if(I->second != schedule.getMaxStage()) { if(mOp.getType() == MachineOperand::MO_VirtualRegister && mOp.isDef()) { if(valuesToSave.count(mOp.getVRegValue())) { - + TmpInstruction *tmp = new TmpInstruction(mOp.getVRegValue()); - + //Get machine code for this instruction MachineCodeForInstruction & tempVec = MachineCodeForInstruction::get(defaultInst); tempVec.addTemp((Value*) tmp); @@ -2697,8 +2697,8 @@ saveValue = BuildMI(machineBB[index], V9::FMOVD, 3).addReg(mOp.getVRegValue()).addRegDef(tmp); else saveValue = BuildMI(machineBB[index], V9::ORr, 3).addReg(mOp.getVRegValue()).addImm(0).addRegDef(tmp); - - + + //Save for future cleanup kernelValue[mOp.getVRegValue()] = tmp; newValLocation[tmp] = machineBB[index]; @@ -2760,7 +2760,7 @@ //Get machine code for this instruction MachineCodeForInstruction & tempMvec = MachineCodeForInstruction::get(defaultInst); tempMvec.addTemp((Value*) tmp); - + MachineInstr *saveValue = BuildMI(*machineBB[0], machineBB[0]->begin(), V9::PHI, 3).addReg(lastPhi).addReg(I->second).addRegDef(tmp); DEBUG(std::cerr << "Resulting PHI: " << *saveValue << "\n"); @@ -2802,11 +2802,11 @@ //Start with the kernel and for each phi insert a copy for the phi //def and for each arg //phis are only in the first BB in the kernel - for(MachineBasicBlock::iterator I = kernelBB[0]->begin(), E = kernelBB[0]->end(); + for(MachineBasicBlock::iterator I = kernelBB[0]->begin(), E = kernelBB[0]->end(); I != E; ++I) { DEBUG(std::cerr << "Looking at Instr: " << *I << "\n"); - + //Get op code and check if its a phi if(I->getOpcode() == V9::PHI) { @@ -2814,12 +2814,12 @@ Instruction *tmp = 0; for(unsigned i = 0; i < I->getNumOperands(); ++i) { - + //Get Operand const MachineOperand &mOp = I->getOperand(i); - assert(mOp.getType() == MachineOperand::MO_VirtualRegister + assert(mOp.getType() == MachineOperand::MO_VirtualRegister && "Should be a Value*\n"); - + if(!tmp) { tmp = new TmpInstruction(mOp.getVRegValue()); addToMCFI.push_back(tmp); @@ -2844,10 +2844,10 @@ BuildMI(*(newValLocation[mOp.getVRegValue()]), ++inst, V9::FMOVD, 3).addReg(mOp.getVRegValue()).addRegDef(tmp); else BuildMI(*(newValLocation[mOp.getVRegValue()]), ++inst, V9::ORr, 3).addReg(mOp.getVRegValue()).addImm(0).addRegDef(tmp); - + break; } - + } } @@ -2861,11 +2861,11 @@ BuildMI(*kernelBB[0], I, V9::FMOVD, 3).addReg(tmp).addRegDef(mOp.getVRegValue()); else BuildMI(*kernelBB[0], I, V9::ORr, 3).addReg(tmp).addImm(0).addRegDef(mOp.getVRegValue()); - - + + worklist.push_back(std::make_pair(kernelBB[0], I)); } - + } } @@ -2884,12 +2884,12 @@ //Remove phis from epilogue - for(std::vector >::iterator MB = epilogues.begin(), + for(std::vector >::iterator MB = epilogues.begin(), ME = epilogues.end(); MB != ME; ++MB) { - + for(std::vector::iterator currentMBB = MB->begin(), currentME = MB->end(); currentMBB != currentME; ++currentMBB) { - - for(MachineBasicBlock::iterator I = (*currentMBB)->begin(), + + for(MachineBasicBlock::iterator I = (*currentMBB)->begin(), E = (*currentMBB)->end(); I != E; ++I) { DEBUG(std::cerr << "Looking at Instr: " << *I << "\n"); @@ -2901,12 +2901,12 @@ //Get Operand const MachineOperand &mOp = I->getOperand(i); assert(mOp.getType() == MachineOperand::MO_VirtualRegister && "Should be a Value*\n"); - + if(!tmp) { tmp = new TmpInstruction(mOp.getVRegValue()); addToMCFI.push_back(tmp); } - + //Now for all our arguments we read, OR to the new TmpInstruction that we created if(mOp.isUse()) { DEBUG(std::cerr << "Use: " << mOp << "\n"); @@ -2925,13 +2925,13 @@ BuildMI(*(newValLocation[mOp.getVRegValue()]), ++inst, V9::FMOVD, 3).addReg(mOp.getVRegValue()).addRegDef(tmp); else BuildMI(*(newValLocation[mOp.getVRegValue()]), ++inst, V9::ORr, 3).addReg(mOp.getVRegValue()).addImm(0).addRegDef(tmp); - - + + break; } - + } - + } else { //Remove the phi and replace it with an OR @@ -2942,7 +2942,7 @@ BuildMI(**currentMBB, I, V9::FMOVD, 3).addReg(tmp).addRegDef(mOp.getVRegValue()); else BuildMI(**currentMBB, I, V9::ORr, 3).addReg(tmp).addImm(0).addRegDef(mOp.getVRegValue()); - + worklist.push_back(std::make_pair(*currentMBB,I)); } } @@ -2959,12 +2959,12 @@ } addToMCFI.clear(); } - + //Delete the phis for(std::vector >::iterator I = worklist.begin(), E = worklist.end(); I != E; ++I) { DEBUG(std::cerr << "Deleting PHI " << *I->second << "\n"); I->first->erase(I->second); - + } @@ -2990,7 +2990,7 @@ //Get the LLVM basic block BasicBlock *bb = (BasicBlock*) SB[sideExitNum]->getBasicBlock(); MachineBasicBlock *mbb = (MachineBasicBlock*) SB[sideExitNum]; - + int stage = branchStage[mbb]; //Create new basic blocks for our side exit instructios that were moved below the branch @@ -2998,17 +2998,17 @@ sideMBB = new MachineBasicBlock(sideBB); (((MachineBasicBlock*)SB[0])->getParent())->getBasicBlockList().push_back(sideMBB); - + if(instrsMovedDown.count(mbb)) { for(std::vector >::iterator I = instrsMovedDown[mbb].begin(), E = instrsMovedDown[mbb].end(); I != E; ++I) { if(branchStage[mbb] == I->second) sideMBB->push_back((I->first)->clone()); } - + //Add unconditional branches to original exits BuildMI(sideMBB, V9::BA, 1).addPCDisp(sideExits[mbb]); BuildMI(sideMBB, V9::NOP, 0); - + //Add unconditioal branch to llvm BB BasicBlock *extBB = dyn_cast(sideExits[mbb]); assert(extBB && "Side exit basicblock can not be null"); @@ -3019,19 +3019,19 @@ //only clone epilogues that are from a greater stage! for(unsigned i = 0; i < epilogues.size()-stage; ++i) { std::vector MB = epilogues[i]; - + std::vector newEp; std::vector newLLVMEp; - - for(std::vector::iterator currentMBB = MB.begin(), + + for(std::vector::iterator currentMBB = MB.begin(), lastMBB = MB.end(); currentMBB != lastMBB; ++currentMBB) { BasicBlock *tmpBB = new BasicBlock("SideEpilogue", (Function*) (*currentMBB)->getBasicBlock()->getParent()); MachineBasicBlock *tmp = new MachineBasicBlock(tmpBB); - + //Clone instructions and insert into new MBB - for(MachineBasicBlock::iterator I = (*currentMBB)->begin(), + for(MachineBasicBlock::iterator I = (*currentMBB)->begin(), E = (*currentMBB)->end(); I != E; ++I) { - + MachineInstr *clone = I->clone(); if(clone->getOpcode() == V9::BA && (currentMBB+1 == lastMBB)) { //update branch to side exit @@ -3042,26 +3042,26 @@ } } } - + tmp->push_back(clone); - + } - + //Add llvm branch TerminatorInst *newBranch = new BranchInst(sideBB, tmpBB); - + newEp.push_back(tmp); (((MachineBasicBlock*)SB[0])->getParent())->getBasicBlockList().push_back(tmp); newLLVMEp.push_back(tmpBB); - + } side_llvm_epilogues.push_back(newLLVMEp); side_epilogues.push_back(newEp); } - + //Now stich up all the branches - + //Loop over prologues, and if its an inner branch and branches to our original side exit //then have it branch to the appropriate epilogue first (if it exists) for(unsigned P = 0; P < prologues.size(); ++P) { @@ -3072,7 +3072,7 @@ //Iterate backwards of machine instructions to find the branch we need to update for(MachineBasicBlock::reverse_iterator mInst = currentMBB->rbegin(), mInstEnd = currentMBB->rend(); mInst != mInstEnd; ++mInst) { MachineOpCode OC = mInst->getOpcode(); - + //If its a branch update its branchto if(TMI->isBranch(OC)) { for(unsigned opNum = 0; opNum < mInst->getNumOperands(); ++opNum) { @@ -3087,11 +3087,11 @@ DEBUG(std::cerr << "New Prologue Branch: " << *mInst << "\n"); } } - + //Update llvm branch TerminatorInst *branchVal = ((BasicBlock*) currentMBB->getBasicBlock())->getTerminator(); DEBUG(std::cerr << *branchVal << "\n"); - + for(unsigned i=0; i < branchVal->getNumSuccessors(); ++i) { if(branchVal->getSuccessor(i) == sideExits[mbb]) { DEBUG(std::cerr << "Replacing successor bb\n"); @@ -3117,7 +3117,7 @@ //Iterate backwards of machine instructions to find the branch we need to update for(MachineBasicBlock::reverse_iterator mInst = currentMBB->rbegin(), mInstEnd = currentMBB->rend(); mInst != mInstEnd; ++mInst) { MachineOpCode OC = mInst->getOpcode(); - + //If its a branch update its branchto if(TMI->isBranch(OC)) { for(unsigned opNum = 0; opNum < mInst->getNumOperands(); ++opNum) { @@ -3140,7 +3140,7 @@ //Update llvm branch TerminatorInst *branchVal = ((BasicBlock*)currentMBB->getBasicBlock())->getTerminator(); DEBUG(std::cerr << *branchVal << "\n"); - + for(unsigned i=0; i < branchVal->getNumSuccessors(); ++i) { if(branchVal->getSuccessor(i) == sideExits[mbb]) { DEBUG(std::cerr << "Replacing successor bb\n"); From jeffc at jolt-lang.org Wed Jul 27 00:54:01 2005 From: jeffc at jolt-lang.org (Jeff Cohen) Date: Wed, 27 Jul 2005 00:54:01 -0500 Subject: [llvm-commits] CVS: llvm/lib/Target/SparcV9/ModuloScheduling/DependenceAnalyzer.cpp DependenceAnalyzer.h MSSchedule.cpp MSSchedule.h MSScheduleSB.cpp MSScheduleSB.h MSchedGraph.cpp MSchedGraph.h MSchedGraphSB.cpp MSchedGraphSB.h ModuloScheduling.cpp ModuloScheduling.h ModuloSchedulingSuperBlock.cpp ModuloSchedulingSuperBlock.h Message-ID: <200507270554.AAA12950@zion.cs.uiuc.edu> Changes in directory llvm/lib/Target/SparcV9/ModuloScheduling: DependenceAnalyzer.cpp updated: 1.7 -> 1.8 DependenceAnalyzer.h updated: 1.3 -> 1.4 MSSchedule.cpp updated: 1.16 -> 1.17 MSSchedule.h updated: 1.7 -> 1.8 MSScheduleSB.cpp updated: 1.1 -> 1.2 MSScheduleSB.h updated: 1.1 -> 1.2 MSchedGraph.cpp updated: 1.21 -> 1.22 MSchedGraph.h updated: 1.14 -> 1.15 MSchedGraphSB.cpp updated: 1.3 -> 1.4 MSchedGraphSB.h updated: 1.1 -> 1.2 ModuloScheduling.cpp updated: 1.50 -> 1.51 ModuloScheduling.h updated: 1.31 -> 1.32 ModuloSchedulingSuperBlock.cpp updated: 1.3 -> 1.4 ModuloSchedulingSuperBlock.h updated: 1.2 -> 1.3 --- Log message: Eliminate tabs and trailing spaces. --- Diffs of the changes: (+2995 -2995) DependenceAnalyzer.cpp | 44 DependenceAnalyzer.h | 28 MSSchedule.cpp | 74 - MSSchedule.h | 2 MSScheduleSB.cpp | 76 - MSScheduleSB.h | 2 MSchedGraph.cpp | 516 ++++---- MSchedGraph.h | 56 MSchedGraphSB.cpp | 576 ++++----- MSchedGraphSB.h | 64 - ModuloScheduling.cpp | 1854 +++++++++++++++--------------- ModuloScheduling.h | 38 ModuloSchedulingSuperBlock.cpp | 2494 ++++++++++++++++++++--------------------- ModuloSchedulingSuperBlock.h | 166 +- 14 files changed, 2995 insertions(+), 2995 deletions(-) Index: llvm/lib/Target/SparcV9/ModuloScheduling/DependenceAnalyzer.cpp diff -u llvm/lib/Target/SparcV9/ModuloScheduling/DependenceAnalyzer.cpp:1.7 llvm/lib/Target/SparcV9/ModuloScheduling/DependenceAnalyzer.cpp:1.8 --- llvm/lib/Target/SparcV9/ModuloScheduling/DependenceAnalyzer.cpp:1.7 Thu Jun 16 23:00:57 2005 +++ llvm/lib/Target/SparcV9/ModuloScheduling/DependenceAnalyzer.cpp Wed Jul 27 00:53:44 2005 @@ -31,9 +31,9 @@ Statistic<> NoDeps("depanalyzer-nodeps", "Number of dependences eliminated"); Statistic<> NumDeps("depanalyzer-deps", - "Number of dependences could not eliminate"); + "Number of dependences could not eliminate"); Statistic<> AdvDeps("depanalyzer-advdeps", - "Number of dependences using advanced techniques"); + "Number of dependences using advanced techniques"); bool DependenceAnalyzer::runOnFunction(Function &F) { AA = &getAnalysis(); @@ -44,7 +44,7 @@ } static RegisterAnalysisX("depanalyzer", - "Dependence Analyzer"); + "Dependence Analyzer"); // - Get inter and intra dependences between loads and stores // @@ -57,10 +57,10 @@ // further (Step 4) // Step 4: do advanced analysis void DependenceAnalyzer::AnalyzeDeps(Value *val, Value *val2, bool valLoad, - bool val2Load, - std::vector &deps, - BasicBlock *BB, - bool srcBeforeDest) { + bool val2Load, + std::vector &deps, + BasicBlock *BB, + bool srcBeforeDest) { bool loopInvariant = true; @@ -76,7 +76,7 @@ //If Loop invariant, let AA decide if(loopInvariant) { if(AA->alias(val, (unsigned)TD->getTypeSize(val->getType()), - val2,(unsigned)TD->getTypeSize(val2->getType())) + val2,(unsigned)TD->getTypeSize(val2->getType())) != AliasAnalysis::NoAlias) { createDep(deps, valLoad, val2Load, srcBeforeDest); } @@ -102,7 +102,7 @@ Value *GPop = GP->getOperand(0); Value *GP2op = GP2->getOperand(0); int alias = AA->alias(GPop, (unsigned)TD->getTypeSize(GPop->getType()), - GP2op,(unsigned)TD->getTypeSize(GP2op->getType())); + GP2op,(unsigned)TD->getTypeSize(GP2op->getType())); if(alias == AliasAnalysis::MustAlias) { @@ -121,11 +121,11 @@ // advancedDepAnalysis - Do advanced data dependence tests void DependenceAnalyzer::advancedDepAnalysis(GetElementPtrInst *gp1, - GetElementPtrInst *gp2, - bool valLoad, - bool val2Load, - std::vector &deps, - bool srcBeforeDest) { + GetElementPtrInst *gp2, + bool valLoad, + bool val2Load, + std::vector &deps, + bool srcBeforeDest) { //Check if both GEPs are in a simple form: 3 ops, constant 0 as second arg if(gp1->getNumOperands() != 3 || gp2->getNumOperands() != 3) { @@ -138,7 +138,7 @@ if(Constant *c1 = dyn_cast(gp1->getOperand(1))) if(Constant *c2 = dyn_cast(gp2->getOperand(1))) if(c1->isNullValue() && c2->isNullValue()) - GPok = true; + GPok = true; if(!GPok) { createDep(deps, valLoad, val2Load, srcBeforeDest); @@ -230,8 +230,8 @@ // Create dependences once its determined these two instructions // references the same memory void DependenceAnalyzer::createDep(std::vector &deps, - bool valLoad, bool val2Load, - bool srcBeforeDest, int diff) { + bool valLoad, bool val2Load, + bool srcBeforeDest, int diff) { //If the source instruction occurs after the destination instruction //(execution order), then this dependence is across iterations @@ -269,8 +269,8 @@ //Get Dependence Info for a pair of Instructions DependenceResult DependenceAnalyzer::getDependenceInfo(Instruction *inst1, - Instruction *inst2, - bool srcBeforeDest) { + Instruction *inst2, + bool srcBeforeDest) { std::vector deps; DEBUG(std::cerr << "Inst1: " << *inst1 << "\n"); @@ -284,17 +284,17 @@ if(StoreInst *stInst = dyn_cast(inst2)) AnalyzeDeps(ldInst->getOperand(0), stInst->getOperand(1), - true, false, deps, ldInst->getParent(), srcBeforeDest); + true, false, deps, ldInst->getParent(), srcBeforeDest); } else if(StoreInst *stInst = dyn_cast(inst1)) { if(LoadInst *ldInst = dyn_cast(inst2)) AnalyzeDeps(stInst->getOperand(1), ldInst->getOperand(0), false, true, - deps, ldInst->getParent(), srcBeforeDest); + deps, ldInst->getParent(), srcBeforeDest); else if(StoreInst *stInst2 = dyn_cast(inst2)) AnalyzeDeps(stInst->getOperand(1), stInst2->getOperand(1), false, false, - deps, stInst->getParent(), srcBeforeDest); + deps, stInst->getParent(), srcBeforeDest); } else assert(0 && "Expected a load or a store\n"); Index: llvm/lib/Target/SparcV9/ModuloScheduling/DependenceAnalyzer.h diff -u llvm/lib/Target/SparcV9/ModuloScheduling/DependenceAnalyzer.h:1.3 llvm/lib/Target/SparcV9/ModuloScheduling/DependenceAnalyzer.h:1.4 --- llvm/lib/Target/SparcV9/ModuloScheduling/DependenceAnalyzer.h:1.3 Fri Apr 22 01:32:48 2005 +++ llvm/lib/Target/SparcV9/ModuloScheduling/DependenceAnalyzer.h Wed Jul 27 00:53:44 2005 @@ -22,7 +22,7 @@ #include namespace llvm { - + //class to represent a dependence struct Dependence { @@ -49,22 +49,22 @@ class DependenceAnalyzer : public FunctionPass { - + AliasAnalysis *AA; TargetData *TD; ScalarEvolution *SE; - void advancedDepAnalysis(GetElementPtrInst *gp1, GetElementPtrInst *gp2, - bool valLoad, bool val2Load, - std::vector &deps, bool srcBeforeDest); - - void AnalyzeDeps(Value *val, Value *val2, bool val1Load, bool val2Load, - std::vector &deps, BasicBlock *BB, - bool srcBeforeDest); - - void createDep(std::vector &deps, bool valLoad, bool val2Load, - bool srcBeforeDest, int diff = 0); + void advancedDepAnalysis(GetElementPtrInst *gp1, GetElementPtrInst *gp2, + bool valLoad, bool val2Load, + std::vector &deps, bool srcBeforeDest); + + void AnalyzeDeps(Value *val, Value *val2, bool val1Load, bool val2Load, + std::vector &deps, BasicBlock *BB, + bool srcBeforeDest); + + void createDep(std::vector &deps, bool valLoad, bool val2Load, + bool srcBeforeDest, int diff = 0); public: DependenceAnalyzer() { AA = 0; TD = 0; SE = 0; } @@ -80,8 +80,8 @@ } //get dependence info - DependenceResult getDependenceInfo(Instruction *inst1, Instruction *inst2, - bool srcBeforeDest); + DependenceResult getDependenceInfo(Instruction *inst1, Instruction *inst2, + bool srcBeforeDest); }; Index: llvm/lib/Target/SparcV9/ModuloScheduling/MSSchedule.cpp diff -u llvm/lib/Target/SparcV9/ModuloScheduling/MSSchedule.cpp:1.16 llvm/lib/Target/SparcV9/ModuloScheduling/MSSchedule.cpp:1.17 --- llvm/lib/Target/SparcV9/ModuloScheduling/MSSchedule.cpp:1.16 Thu Jun 16 23:00:57 2005 +++ llvm/lib/Target/SparcV9/ModuloScheduling/MSSchedule.cpp Wed Jul 27 00:53:44 2005 @@ -33,10 +33,10 @@ if (schedule[cycle].size() < numIssue) { //Now check if all the resources in their respective cycles are available if(resourcesFree(node, cycle, II)) { - //Insert to preserve dependencies - addToSchedule(cycle,node); - DEBUG(std::cerr << "Found spot in map, and there is an issue slot\n"); - return false; + //Insert to preserve dependencies + addToSchedule(cycle,node); + DEBUG(std::cerr << "Found spot in map, and there is an issue slot\n"); + return false; } } } @@ -81,7 +81,7 @@ if(resourceNumPerCycle[cycle].count(resourceNum)) { int maxRes = CPUResource::getCPUResource(resourceNum)->maxNumUsers; if(resourceNumPerCycle[cycle][resourceNum] >= maxRes) - isFree = false; + isFree = false; } } @@ -137,21 +137,21 @@ //Loop over resources in each cycle and increments their usage count for(unsigned i=0; i < resources.size(); ++i) { for(unsigned j=0; j < resources[i].size(); ++j) { - - //Get Resource to check its availability - int resourceNum = resources[i][j]; - - DEBUG(std::cerr << "Attempting to schedule Resource Num: " << resourceNum << " in cycle: " << currentCycle << "\n"); - - success = resourceAvailable(resourceNum, currentCycle); - - if(!success) - break; - + + //Get Resource to check its availability + int resourceNum = resources[i][j]; + + DEBUG(std::cerr << "Attempting to schedule Resource Num: " << resourceNum << " in cycle: " << currentCycle << "\n"); + + success = resourceAvailable(resourceNum, currentCycle); + + if(!success) + break; + } if(!success) - break; + break; //Increase cycle currentCycle++; @@ -172,8 +172,8 @@ //Loop over resources in each cycle and increments their usage count for(unsigned i=0; i < resources.size(); ++i) { for(unsigned j=0; j < resources[i].size(); ++j) { - int resourceNum = resources[i][j]; - useResource(resourceNum, currentCycle); + int resourceNum = resources[i][j]; + useResource(resourceNum, currentCycle); } currentCycle++; } @@ -205,15 +205,15 @@ int count = 0; for(int i = index; i <= (schedule.rbegin()->first); i+=II) { if(schedule.count(i)) { - for(std::vector::iterator I = schedule[i].begin(), - E = schedule[i].end(); I != E; ++I) { - //Check if its a branch - assert(!(*I)->isBranch() && "Branch should not be schedule!"); - - tempKernel.push_back(std::make_pair(*I, count)); - maxSN = std::max(maxSN, count); - - } + for(std::vector::iterator I = schedule[i].begin(), + E = schedule[i].end(); I != E; ++I) { + //Check if its a branch + assert(!(*I)->isBranch() && "Branch should not be schedule!"); + + tempKernel.push_back(std::make_pair(*I, count)); + maxSN = std::max(maxSN, count); + + } } ++count; } @@ -231,14 +231,14 @@ for(std::map::iterator N = indVar.begin(), NE = indVar.end(); N != NE; ++N) { - if(N->second < I->first->getIndex()) - tmpMap[N->second] = (MachineInstr*) N->first; + if(N->second < I->first->getIndex()) + tmpMap[N->second] = (MachineInstr*) N->first; } //Add to kernel, and delete from indVar for(std::map::iterator N = tmpMap.begin(), NE = tmpMap.end(); N != NE; ++N) { - kernel.push_back(std::make_pair(N->second, 0)); - indVar.erase(N->second); + kernel.push_back(std::make_pair(N->second, 0)); + indVar.erase(N->second); } } @@ -278,10 +278,10 @@ const MachineOperand &mOp = inst->getOperand(i); if(mOp.getType() == MachineOperand::MO_VirtualRegister && mOp.isDef()) { if(def == mOp.getVRegValue()) { - if(P->second >= stage) - return false; - else - return true; + if(P->second >= stage) + return false; + else + return true; } } } @@ -302,7 +302,7 @@ os << "Kernel:\n"; for(std::vector >::const_iterator I = kernel.begin(), - E = kernel.end(); I != E; ++I) + E = kernel.end(); I != E; ++I) os << "Node: " << *(I->first) << " Stage: " << I->second << "\n"; } Index: llvm/lib/Target/SparcV9/ModuloScheduling/MSSchedule.h diff -u llvm/lib/Target/SparcV9/ModuloScheduling/MSSchedule.h:1.7 llvm/lib/Target/SparcV9/ModuloScheduling/MSSchedule.h:1.8 --- llvm/lib/Target/SparcV9/ModuloScheduling/MSSchedule.h:1.7 Thu Jun 16 23:00:57 2005 +++ llvm/lib/Target/SparcV9/ModuloScheduling/MSSchedule.h Wed Jul 27 00:53:44 2005 @@ -28,7 +28,7 @@ std::map > resourceNumPerCycle; //Check if all resources are free - bool resourcesFree(MSchedGraphNode*, int, int II); + bool resourcesFree(MSchedGraphNode*, int, int II); bool resourceAvailable(int resourceNum, int cycle); void useResource(int resourceNum, int cycle); Index: llvm/lib/Target/SparcV9/ModuloScheduling/MSScheduleSB.cpp diff -u llvm/lib/Target/SparcV9/ModuloScheduling/MSScheduleSB.cpp:1.1 llvm/lib/Target/SparcV9/ModuloScheduling/MSScheduleSB.cpp:1.2 --- llvm/lib/Target/SparcV9/ModuloScheduling/MSScheduleSB.cpp:1.1 Thu Jun 16 23:15:43 2005 +++ llvm/lib/Target/SparcV9/ModuloScheduling/MSScheduleSB.cpp Wed Jul 27 00:53:44 2005 @@ -33,10 +33,10 @@ if (schedule[cycle].size() < numIssue) { //Now check if all the resources in their respective cycles are available if(resourcesFree(node, cycle, II)) { - //Insert to preserve dependencies - addToSchedule(cycle,node); - DEBUG(std::cerr << "Found spot in map, and there is an issue slot\n"); - return false; + //Insert to preserve dependencies + addToSchedule(cycle,node); + DEBUG(std::cerr << "Found spot in map, and there is an issue slot\n"); + return false; } } } @@ -81,7 +81,7 @@ if(resourceNumPerCycle[cycle].count(resourceNum)) { int maxRes = CPUResource::getCPUResource(resourceNum)->maxNumUsers; if(resourceNumPerCycle[cycle][resourceNum] >= maxRes) - isFree = false; + isFree = false; } } @@ -137,21 +137,21 @@ //Loop over resources in each cycle and increments their usage count for(unsigned i=0; i < resources.size(); ++i) { for(unsigned j=0; j < resources[i].size(); ++j) { - - //Get Resource to check its availability - int resourceNum = resources[i][j]; - - DEBUG(std::cerr << "Attempting to schedule Resource Num: " << resourceNum << " in cycle: " << currentCycle << "\n"); - - success = resourceAvailable(resourceNum, currentCycle); - - if(!success) - break; - + + //Get Resource to check its availability + int resourceNum = resources[i][j]; + + DEBUG(std::cerr << "Attempting to schedule Resource Num: " << resourceNum << " in cycle: " << currentCycle << "\n"); + + success = resourceAvailable(resourceNum, currentCycle); + + if(!success) + break; + } if(!success) - break; + break; //Increase cycle currentCycle++; @@ -172,8 +172,8 @@ //Loop over resources in each cycle and increments their usage count for(unsigned i=0; i < resources.size(); ++i) { for(unsigned j=0; j < resources[i].size(); ++j) { - int resourceNum = resources[i][j]; - useResource(resourceNum, currentCycle); + int resourceNum = resources[i][j]; + useResource(resourceNum, currentCycle); } currentCycle++; } @@ -205,15 +205,15 @@ int count = 0; for(int i = index; i <= (schedule.rbegin()->first); i+=II) { if(schedule.count(i)) { - for(std::vector::iterator I = schedule[i].begin(), - E = schedule[i].end(); I != E; ++I) { - //Check if its a branch - assert(!(*I)->isBranch() && "Branch should not be schedule!"); - - tempKernel.push_back(std::make_pair(*I, count)); - maxSN = std::max(maxSN, count); - - } + for(std::vector::iterator I = schedule[i].begin(), + E = schedule[i].end(); I != E; ++I) { + //Check if its a branch + assert(!(*I)->isBranch() && "Branch should not be schedule!"); + + tempKernel.push_back(std::make_pair(*I, count)); + maxSN = std::max(maxSN, count); + + } } ++count; } @@ -231,14 +231,14 @@ for(std::map::iterator N = indVar.begin(), NE = indVar.end(); N != NE; ++N) { - if(N->second < I->first->getIndex()) - tmpMap[N->second] = (MachineInstr*) N->first; + if(N->second < I->first->getIndex()) + tmpMap[N->second] = (MachineInstr*) N->first; } //Add to kernel, and delete from indVar for(std::map::iterator N = tmpMap.begin(), NE = tmpMap.end(); N != NE; ++N) { - kernel.push_back(std::make_pair(N->second, 0)); - indVar.erase(N->second); + kernel.push_back(std::make_pair(N->second, 0)); + indVar.erase(N->second); } } @@ -247,7 +247,7 @@ //assert(I->second == 0 && "Predicate node must be from current iteration\n"); std::vector otherInstrs = I->first->getOtherInstrs(); for(std::vector::iterator O = otherInstrs.begin(), OE = otherInstrs.end(); O != OE; ++O) { - kernel.push_back(std::make_pair((MachineInstr*) *O, I->second)); + kernel.push_back(std::make_pair((MachineInstr*) *O, I->second)); } } @@ -285,10 +285,10 @@ const MachineOperand &mOp = inst->getOperand(i); if(mOp.getType() == MachineOperand::MO_VirtualRegister && mOp.isDef()) { if(def == mOp.getVRegValue()) { - if(P->second >= stage) - return false; - else - return true; + if(P->second >= stage) + return false; + else + return true; } } } @@ -309,7 +309,7 @@ os << "Kernel:\n"; for(std::vector >::const_iterator I = kernel.begin(), - E = kernel.end(); I != E; ++I) + E = kernel.end(); I != E; ++I) os << "Node: " << *(I->first) << " Stage: " << I->second << "\n"; } Index: llvm/lib/Target/SparcV9/ModuloScheduling/MSScheduleSB.h diff -u llvm/lib/Target/SparcV9/ModuloScheduling/MSScheduleSB.h:1.1 llvm/lib/Target/SparcV9/ModuloScheduling/MSScheduleSB.h:1.2 --- llvm/lib/Target/SparcV9/ModuloScheduling/MSScheduleSB.h:1.1 Thu Jun 16 23:15:43 2005 +++ llvm/lib/Target/SparcV9/ModuloScheduling/MSScheduleSB.h Wed Jul 27 00:53:44 2005 @@ -28,7 +28,7 @@ std::map > resourceNumPerCycle; //Check if all resources are free - bool resourcesFree(MSchedGraphSBNode*, int, int II); + bool resourcesFree(MSchedGraphSBNode*, int, int II); bool resourceAvailable(int resourceNum, int cycle); void useResource(int resourceNum, int cycle); Index: llvm/lib/Target/SparcV9/ModuloScheduling/MSchedGraph.cpp diff -u llvm/lib/Target/SparcV9/ModuloScheduling/MSchedGraph.cpp:1.21 llvm/lib/Target/SparcV9/ModuloScheduling/MSchedGraph.cpp:1.22 --- llvm/lib/Target/SparcV9/ModuloScheduling/MSchedGraph.cpp:1.21 Sat Apr 30 20:25:53 2005 +++ llvm/lib/Target/SparcV9/ModuloScheduling/MSchedGraph.cpp Wed Jul 27 00:53:44 2005 @@ -33,8 +33,8 @@ //MSchedGraphNode constructor MSchedGraphNode::MSchedGraphNode(const MachineInstr* inst, - MSchedGraph *graph, unsigned idx, - unsigned late, bool isBranch) + MSchedGraph *graph, unsigned idx, + unsigned late, bool isBranch) : Inst(inst), Parent(graph), index(idx), latency(late), isBranchInstr(isBranch) { @@ -76,7 +76,7 @@ //Get the iteration difference for the edge from this node to its successor unsigned MSchedGraphNode::getIteDiff(MSchedGraphNode *succ) { for(std::vector::iterator I = Successors.begin(), - E = Successors.end(); + E = Successors.end(); I != E; ++I) { if(I->getDest() == succ) return I->getIteDiff(); @@ -90,7 +90,7 @@ //return the edge the corresponds to this in edge int count = 0; for(MSchedGraphNode::succ_iterator I = pred->succ_begin(), - E = pred->succ_end(); + E = pred->succ_end(); I != E; ++I) { if(*I == this) return count; @@ -111,7 +111,7 @@ //Dtermine if pred is a predecessor of this node bool MSchedGraphNode::isPredecessor(MSchedGraphNode *pred) { if(std::find( Predecessors.begin(), Predecessors.end(), - pred) != Predecessors.end()) + pred) != Predecessors.end()) return true; else return false; @@ -119,11 +119,11 @@ //Add a node to the graph void MSchedGraph::addNode(const MachineInstr *MI, - MSchedGraphNode *node) { + MSchedGraphNode *node) { //Make sure node does not already exist assert(GraphMap.find(MI) == GraphMap.end() - && "New MSchedGraphNode already exists for this instruction"); + && "New MSchedGraphNode already exists for this instruction"); GraphMap[MI] = node; } @@ -149,10 +149,10 @@ //is a special case in Modulo Scheduling. We only want to deal with //the body of the loop. MSchedGraph::MSchedGraph(const MachineBasicBlock *bb, - const TargetMachine &targ, - std::map &ignoreInstrs, - DependenceAnalyzer &DA, - std::map &machineTollvm) + const TargetMachine &targ, + std::map &ignoreInstrs, + DependenceAnalyzer &DA, + std::map &machineTollvm) : Target(targ) { //Make sure BB is not null, @@ -172,10 +172,10 @@ //is a special case in Modulo Scheduling. We only want to deal with //the body of the loop. MSchedGraph::MSchedGraph(std::vector &bbs, - const TargetMachine &targ, - std::map &ignoreInstrs, - DependenceAnalyzer &DA, - std::map &machineTollvm) + const TargetMachine &targ, + std::map &ignoreInstrs, + DependenceAnalyzer &DA, + std::map &machineTollvm) : BBs(bbs), Target(targ) { //Make sure there is at least one BB and it is not null, @@ -191,7 +191,7 @@ //Copies the graph and keeps a map from old to new nodes MSchedGraph::MSchedGraph(const MSchedGraph &G, - std::map &newNodes) + std::map &newNodes) : Target(G.Target) { BBs = G.BBs; @@ -199,7 +199,7 @@ std::map oldToNew; //Copy all nodes for(MSchedGraph::const_iterator N = G.GraphMap.begin(), - NE = G.GraphMap.end(); N != NE; ++N) { + NE = G.GraphMap.end(); N != NE; ++N) { MSchedGraphNode *newNode = new MSchedGraphNode(*(N->second)); oldToNew[&*(N->second)] = newNode; @@ -272,8 +272,8 @@ } //Experimental code to add edges from the branch to all nodes dependent upon it. void hasPath(MSchedGraphNode *node, std::set &visited, - std::set &branches, MSchedGraphNode *startNode, - std::set > &newEdges ) { + std::set &branches, MSchedGraphNode *startNode, + std::set > &newEdges ) { visited.insert(node); DEBUG(std::cerr << "Visiting: " << *node << "\n"); @@ -287,7 +287,7 @@ //only visit if we have not already else if(!visited.count(dest)) { if(edge->getIteDiff() == 0) - hasPath(dest, visited, branches, startNode, newEdges);} + hasPath(dest, visited, branches, startNode, newEdges);} } @@ -302,7 +302,7 @@ I != E; ++I) { if(I->second->isBranch()) if(I->second->hasPredecessors()) - branches.insert(I->second); + branches.insert(I->second); } //See if there is a path first instruction to the branches, if so, add an @@ -318,8 +318,8 @@ unsigned min = GraphMap.size(); if(newEdges.size() == 1) { ((newEdges.begin())->first)->addOutEdge(((newEdges.begin())->second), - MSchedGraphEdge::BranchDep, - MSchedGraphEdge::NonDataDep, 1); + MSchedGraphEdge::BranchDep, + MSchedGraphEdge::NonDataDep, 1); } else { @@ -331,13 +331,13 @@ DEBUG(std::cerr << "Branch Edge from: " << *(I->first) << " to " << *(I->second) << "\n"); // if(I->second->getIndex() <= min) { - start = I->first; - end = I->second; - //min = I->second->getIndex(); - //} - start->addOutEdge(end, - MSchedGraphEdge::BranchDep, - MSchedGraphEdge::NonDataDep, 1); + start = I->first; + end = I->second; + //min = I->second->getIndex(); + //} + start->addOutEdge(end, + MSchedGraphEdge::BranchDep, + MSchedGraphEdge::NonDataDep, 1); } } } @@ -345,8 +345,8 @@ //Add edges between the nodes void MSchedGraph::buildNodesAndEdges(std::map &ignoreInstrs, - DependenceAnalyzer &DA, - std::map &machineTollvm) { + DependenceAnalyzer &DA, + std::map &machineTollvm) { //Get Machine target information for calculating latency @@ -361,18 +361,18 @@ unsigned index = 0; for(std::vector::iterator B = BBs.begin(), - BE = BBs.end(); B != BE; ++B) { + BE = BBs.end(); B != BE; ++B) { const MachineBasicBlock *BB = *B; //Loop over instructions in MBB and add nodes and edges for (MachineBasicBlock::const_iterator MI = BB->begin(), e = BB->end(); - MI != e; ++MI) { + MI != e; ++MI) { //Ignore indvar instructions if(ignoreInstrs.count(MI)) { - ++index; - continue; + ++index; + continue; } //Get each instruction of machine basic block, get the delay @@ -386,16 +386,16 @@ //Check if subsequent instructions can be issued before //the result is ready, if so use min delay. if(MTI->hasResultInterlock(MIopCode)) - delay = MTI->minLatency(MIopCode); + delay = MTI->minLatency(MIopCode); else #endif - //Get delay - delay = MTI->maxLatency(opCode); + //Get delay + delay = MTI->maxLatency(opCode); //Create new node for this machine instruction and add to the graph. //Create only if not a nop if(MTI->isNop(opCode)) - continue; + continue; //Sparc BE does not use PHI opcode, so assert on this case assert(opCode != TargetInstrInfo::PHI && "Did not expect PHI opcode"); @@ -404,74 +404,74 @@ //We want to flag the branch node to treat it special if(MTI->isBranch(opCode)) - isBranch = true; + isBranch = true; //Node is created and added to the graph automatically MSchedGraphNode *node = new MSchedGraphNode(MI, this, index, delay, - isBranch); + isBranch); DEBUG(std::cerr << "Created Node: " << *node << "\n"); //Check OpCode to keep track of memory operations to add memory //dependencies later. if(MTI->isLoad(opCode) || MTI->isStore(opCode)) - memInstructions.push_back(node); + memInstructions.push_back(node); //Loop over all operands, and put them into the register number to //graph node map for determining dependencies //If an operands is a use/def, we have an anti dependence to itself for(unsigned i=0; i < MI->getNumOperands(); ++i) { - //Get Operand - const MachineOperand &mOp = MI->getOperand(i); - - //Check if it has an allocated register - if(mOp.hasAllocatedReg()) { - int regNum = mOp.getReg(); - - if(regNum != SparcV9::g0) { - //Put into our map - regNumtoNodeMap[regNum].push_back(std::make_pair(i, node)); - } - continue; - } - - - //Add virtual registers dependencies - //Check if any exist in the value map already and create dependencies - //between them. - if(mOp.getType() == MachineOperand::MO_VirtualRegister - || mOp.getType() == MachineOperand::MO_CCRegister) { - - //Make sure virtual register value is not null - assert((mOp.getVRegValue() != NULL) && "Null value is defined"); - - //Check if this is a read operation in a phi node, if so DO NOT PROCESS - if(mOp.isUse() && (opCode == TargetInstrInfo::PHI)) { - DEBUG(std::cerr << "Read Operation in a PHI node\n"); - continue; - } - - if (const Value* srcI = mOp.getVRegValue()) { - - //Find value in the map - std::map >::iterator V - = valuetoNodeMap.find(srcI); - - //If there is something in the map already, add edges from - //those instructions - //to this one we are processing - if(V != valuetoNodeMap.end()) { - addValueEdges(V->second, node, mOp.isUse(), mOp.isDef(), phiInstrs); - - //Add to value map - V->second.push_back(std::make_pair(i,node)); - } - //Otherwise put it in the map - else - //Put into value map - valuetoNodeMap[mOp.getVRegValue()].push_back(std::make_pair(i, node)); - } - } + //Get Operand + const MachineOperand &mOp = MI->getOperand(i); + + //Check if it has an allocated register + if(mOp.hasAllocatedReg()) { + int regNum = mOp.getReg(); + + if(regNum != SparcV9::g0) { + //Put into our map + regNumtoNodeMap[regNum].push_back(std::make_pair(i, node)); + } + continue; + } + + + //Add virtual registers dependencies + //Check if any exist in the value map already and create dependencies + //between them. + if(mOp.getType() == MachineOperand::MO_VirtualRegister + || mOp.getType() == MachineOperand::MO_CCRegister) { + + //Make sure virtual register value is not null + assert((mOp.getVRegValue() != NULL) && "Null value is defined"); + + //Check if this is a read operation in a phi node, if so DO NOT PROCESS + if(mOp.isUse() && (opCode == TargetInstrInfo::PHI)) { + DEBUG(std::cerr << "Read Operation in a PHI node\n"); + continue; + } + + if (const Value* srcI = mOp.getVRegValue()) { + + //Find value in the map + std::map >::iterator V + = valuetoNodeMap.find(srcI); + + //If there is something in the map already, add edges from + //those instructions + //to this one we are processing + if(V != valuetoNodeMap.end()) { + addValueEdges(V->second, node, mOp.isUse(), mOp.isDef(), phiInstrs); + + //Add to value map + V->second.push_back(std::make_pair(i,node)); + } + //Otherwise put it in the map + else + //Put into value map + valuetoNodeMap[mOp.getVRegValue()].push_back(std::make_pair(i, node)); + } + } } ++index; } @@ -480,15 +480,15 @@ //phiInstr list to process const BasicBlock *llvm_bb = BB->getBasicBlock(); for(BasicBlock::const_iterator I = llvm_bb->begin(), E = llvm_bb->end(); - I != E; ++I) { + I != E; ++I) { if(const PHINode *PN = dyn_cast(I)) { - MachineCodeForInstruction & tempMvec = MachineCodeForInstruction::get(PN); - for (unsigned j = 0; j < tempMvec.size(); j++) { - if(!ignoreInstrs.count(tempMvec[j])) { - DEBUG(std::cerr << "Inserting phi instr into map: " << *tempMvec[j] << "\n"); - phiInstrs.push_back((MachineInstr*) tempMvec[j]); - } - } + MachineCodeForInstruction & tempMvec = MachineCodeForInstruction::get(PN); + for (unsigned j = 0; j < tempMvec.size(); j++) { + if(!ignoreInstrs.count(tempMvec[j])) { + DEBUG(std::cerr << "Inserting phi instr into map: " << *tempMvec[j] << "\n"); + phiInstrs.push_back((MachineInstr*) tempMvec[j]); + } + } } } @@ -498,14 +498,14 @@ //Finally deal with PHI Nodes and Value* for(std::vector::iterator I = phiInstrs.begin(), - E = phiInstrs.end(); I != E; ++I) { + E = phiInstrs.end(); I != E; ++I) { //Get Node for this instruction std::map::iterator X; X = find(*I); if(X == GraphMap.end()) - continue; + continue; MSchedGraphNode *node = X->second; @@ -513,38 +513,38 @@ //Loop over operands for this instruction and add value edges for(unsigned i=0; i < (*I)->getNumOperands(); ++i) { - //Get Operand - const MachineOperand &mOp = (*I)->getOperand(i); - if((mOp.getType() == MachineOperand::MO_VirtualRegister - || mOp.getType() == MachineOperand::MO_CCRegister) && mOp.isUse()) { - - //find the value in the map - if (const Value* srcI = mOp.getVRegValue()) { - - //Find value in the map - std::map >::iterator V - = valuetoNodeMap.find(srcI); - - //If there is something in the map already, add edges from - //those instructions - //to this one we are processing - if(V != valuetoNodeMap.end()) { - addValueEdges(V->second, node, mOp.isUse(), mOp.isDef(), - phiInstrs, 1); - } - } - } + //Get Operand + const MachineOperand &mOp = (*I)->getOperand(i); + if((mOp.getType() == MachineOperand::MO_VirtualRegister + || mOp.getType() == MachineOperand::MO_CCRegister) && mOp.isUse()) { + + //find the value in the map + if (const Value* srcI = mOp.getVRegValue()) { + + //Find value in the map + std::map >::iterator V + = valuetoNodeMap.find(srcI); + + //If there is something in the map already, add edges from + //those instructions + //to this one we are processing + if(V != valuetoNodeMap.end()) { + addValueEdges(V->second, node, mOp.isUse(), mOp.isDef(), + phiInstrs, 1); + } + } + } } } } } //Add dependencies for Value*s void MSchedGraph::addValueEdges(std::vector &NodesInMap, - MSchedGraphNode *destNode, bool nodeIsUse, - bool nodeIsDef, std::vector &phiInstrs, int diff) { + MSchedGraphNode *destNode, bool nodeIsUse, + bool nodeIsDef, std::vector &phiInstrs, int diff) { for(std::vector::iterator I = NodesInMap.begin(), - E = NodesInMap.end(); I != E; ++I) { + E = NodesInMap.end(); I != E; ++I) { //Get node in vectors machine operand that is the same value as node MSchedGraphNode *srcNode = I->second; @@ -552,26 +552,26 @@ if(diff > 0) if(std::find(phiInstrs.begin(), phiInstrs.end(), srcNode->getInst()) == phiInstrs.end()) - continue; + continue; //Node is a Def, so add output dep. if(nodeIsDef) { if(mOp.isUse()) { - DEBUG(std::cerr << "Edge from " << *srcNode << " to " << *destNode << " (itediff=" << diff << ", type=anti)\n"); - srcNode->addOutEdge(destNode, MSchedGraphEdge::ValueDep, - MSchedGraphEdge::AntiDep, diff); + DEBUG(std::cerr << "Edge from " << *srcNode << " to " << *destNode << " (itediff=" << diff << ", type=anti)\n"); + srcNode->addOutEdge(destNode, MSchedGraphEdge::ValueDep, + MSchedGraphEdge::AntiDep, diff); } if(mOp.isDef()) { - DEBUG(std::cerr << "Edge from " << *srcNode << " to " << *destNode << " (itediff=" << diff << ", type=output)\n"); - srcNode->addOutEdge(destNode, MSchedGraphEdge::ValueDep, - MSchedGraphEdge::OutputDep, diff); + DEBUG(std::cerr << "Edge from " << *srcNode << " to " << *destNode << " (itediff=" << diff << ", type=output)\n"); + srcNode->addOutEdge(destNode, MSchedGraphEdge::ValueDep, + MSchedGraphEdge::OutputDep, diff); } } if(nodeIsUse) { if(mOp.isDef()) { - DEBUG(std::cerr << "Edge from " << *srcNode << " to " << *destNode << " (itediff=" << diff << ", type=true)\n"); - srcNode->addOutEdge(destNode, MSchedGraphEdge::ValueDep, - MSchedGraphEdge::TrueDep, diff); + DEBUG(std::cerr << "Edge from " << *srcNode << " to " << *destNode << " (itediff=" << diff << ", type=true)\n"); + srcNode->addOutEdge(destNode, MSchedGraphEdge::ValueDep, + MSchedGraphEdge::TrueDep, diff); } } } @@ -609,71 +609,71 @@ //Look at all instructions after this in execution order for(unsigned j=i+1; j < Nodes.size(); ++j) { - - //Sink node is a write - if(Nodes[j].second->getInst()->getOperand(Nodes[j].first).isDef()) { - //Src only uses the register (read) + + //Sink node is a write + if(Nodes[j].second->getInst()->getOperand(Nodes[j].first).isDef()) { + //Src only uses the register (read) if(srcIsUse) - srcNode->addOutEdge(Nodes[j].second, - MSchedGraphEdge::MachineRegister, - MSchedGraphEdge::AntiDep); - + srcNode->addOutEdge(Nodes[j].second, + MSchedGraphEdge::MachineRegister, + MSchedGraphEdge::AntiDep); + else if(srcIsUseandDef) { - srcNode->addOutEdge(Nodes[j].second, - MSchedGraphEdge::MachineRegister, - MSchedGraphEdge::AntiDep); - - srcNode->addOutEdge(Nodes[j].second, - MSchedGraphEdge::MachineRegister, - MSchedGraphEdge::OutputDep); - } + srcNode->addOutEdge(Nodes[j].second, + MSchedGraphEdge::MachineRegister, + MSchedGraphEdge::AntiDep); + + srcNode->addOutEdge(Nodes[j].second, + MSchedGraphEdge::MachineRegister, + MSchedGraphEdge::OutputDep); + } else - srcNode->addOutEdge(Nodes[j].second, - MSchedGraphEdge::MachineRegister, - MSchedGraphEdge::OutputDep); - } - //Dest node is a read - else { - if(!srcIsUse || srcIsUseandDef) - srcNode->addOutEdge(Nodes[j].second, - MSchedGraphEdge::MachineRegister, - MSchedGraphEdge::TrueDep); - } + srcNode->addOutEdge(Nodes[j].second, + MSchedGraphEdge::MachineRegister, + MSchedGraphEdge::OutputDep); + } + //Dest node is a read + else { + if(!srcIsUse || srcIsUseandDef) + srcNode->addOutEdge(Nodes[j].second, + MSchedGraphEdge::MachineRegister, + MSchedGraphEdge::TrueDep); + } } //Look at all the instructions before this one since machine registers //could live across iterations. for(unsigned j = 0; j < i; ++j) { - //Sink node is a write - if(Nodes[j].second->getInst()->getOperand(Nodes[j].first).isDef()) { - //Src only uses the register (read) + //Sink node is a write + if(Nodes[j].second->getInst()->getOperand(Nodes[j].first).isDef()) { + //Src only uses the register (read) if(srcIsUse) - srcNode->addOutEdge(Nodes[j].second, - MSchedGraphEdge::MachineRegister, - MSchedGraphEdge::AntiDep, 1); + srcNode->addOutEdge(Nodes[j].second, + MSchedGraphEdge::MachineRegister, + MSchedGraphEdge::AntiDep, 1); else if(srcIsUseandDef) { - srcNode->addOutEdge(Nodes[j].second, - MSchedGraphEdge::MachineRegister, - MSchedGraphEdge::AntiDep, 1); - - srcNode->addOutEdge(Nodes[j].second, - MSchedGraphEdge::MachineRegister, - MSchedGraphEdge::OutputDep, 1); - } + srcNode->addOutEdge(Nodes[j].second, + MSchedGraphEdge::MachineRegister, + MSchedGraphEdge::AntiDep, 1); + + srcNode->addOutEdge(Nodes[j].second, + MSchedGraphEdge::MachineRegister, + MSchedGraphEdge::OutputDep, 1); + } else - srcNode->addOutEdge(Nodes[j].second, - MSchedGraphEdge::MachineRegister, - MSchedGraphEdge::OutputDep, 1); - } - //Dest node is a read - else { - if(!srcIsUse || srcIsUseandDef) - srcNode->addOutEdge(Nodes[j].second, - MSchedGraphEdge::MachineRegister, - MSchedGraphEdge::TrueDep,1 ); - } - + srcNode->addOutEdge(Nodes[j].second, + MSchedGraphEdge::MachineRegister, + MSchedGraphEdge::OutputDep, 1); + } + //Dest node is a read + else { + if(!srcIsUse || srcIsUseandDef) + srcNode->addOutEdge(Nodes[j].second, + MSchedGraphEdge::MachineRegister, + MSchedGraphEdge::TrueDep,1 ); + } + } @@ -686,8 +686,8 @@ //Add edges between all loads and stores //Can be less strict with alias analysis and data dependence analysis. void MSchedGraph::addMemEdges(const std::vector& memInst, - DependenceAnalyzer &DA, - std::map &machineTollvm) { + DependenceAnalyzer &DA, + std::map &machineTollvm) { //Get Target machine instruction info const TargetInstrInfo *TMI = Target.getInstrInfo(); @@ -707,7 +707,7 @@ //No self loops if(destIndex == srcIndex) - continue; + continue; MachineInstr *destInst = (MachineInstr*) memInst[destIndex]->getInst(); @@ -717,7 +717,7 @@ //Assuming instructions without corresponding llvm instructions //are from constant pools. if (!machineTollvm.count(srcInst) || !machineTollvm.count(destInst)) - continue; + continue; bool useDepAnalyzer = true; @@ -726,78 +726,78 @@ Instruction *srcLLVM = machineTollvm[srcInst]; Instruction *destLLVM = machineTollvm[destInst]; if(!isa(srcLLVM) - && !isa(srcLLVM)) { - if(isa(srcLLVM)) { - if(isa(srcLLVM->getOperand(0)) || isa(srcLLVM->getOperand(1))) - continue; - } - useDepAnalyzer = false; + && !isa(srcLLVM)) { + if(isa(srcLLVM)) { + if(isa(srcLLVM->getOperand(0)) || isa(srcLLVM->getOperand(1))) + continue; + } + useDepAnalyzer = false; } if(!isa(destLLVM) - && !isa(destLLVM)) { - if(isa(destLLVM)) { - if(isa(destLLVM->getOperand(0)) || isa(destLLVM->getOperand(1))) - continue; - } - useDepAnalyzer = false; + && !isa(destLLVM)) { + if(isa(destLLVM)) { + if(isa(destLLVM->getOperand(0)) || isa(destLLVM->getOperand(1))) + continue; + } + useDepAnalyzer = false; } //Use dep analysis when we have corresponding llvm loads/stores if(useDepAnalyzer) { - bool srcBeforeDest = true; - if(destIndex < srcIndex) - srcBeforeDest = false; - - DependenceResult dr = DA.getDependenceInfo(machineTollvm[srcInst], - machineTollvm[destInst], - srcBeforeDest); - - for(std::vector::iterator d = dr.dependences.begin(), - de = dr.dependences.end(); d != de; ++d) { - //Add edge from load to store - memInst[srcIndex]->addOutEdge(memInst[destIndex], - MSchedGraphEdge::MemoryDep, - d->getDepType(), d->getIteDiff()); - - } + bool srcBeforeDest = true; + if(destIndex < srcIndex) + srcBeforeDest = false; + + DependenceResult dr = DA.getDependenceInfo(machineTollvm[srcInst], + machineTollvm[destInst], + srcBeforeDest); + + for(std::vector::iterator d = dr.dependences.begin(), + de = dr.dependences.end(); d != de; ++d) { + //Add edge from load to store + memInst[srcIndex]->addOutEdge(memInst[destIndex], + MSchedGraphEdge::MemoryDep, + d->getDepType(), d->getIteDiff()); + + } } //Otherwise, we can not do any further analysis and must make a dependence else { - - //Get the machine opCode to determine type of memory instruction - MachineOpCode destNodeOpCode = destInst->getOpcode(); - - //Get the Value* that we are reading from the load, always the first op - const MachineOperand &mOp = srcInst->getOperand(0); - const MachineOperand &mOp2 = destInst->getOperand(0); - - if(mOp.hasAllocatedReg()) - if(mOp.getReg() == SparcV9::g0) - continue; - if(mOp2.hasAllocatedReg()) - if(mOp2.getReg() == SparcV9::g0) - continue; - - DEBUG(std::cerr << "Adding dependence for machine instructions\n"); - //Load-Store deps - if(TMI->isLoad(srcNodeOpCode)) { - - if(TMI->isStore(destNodeOpCode)) - memInst[srcIndex]->addOutEdge(memInst[destIndex], - MSchedGraphEdge::MemoryDep, - MSchedGraphEdge::AntiDep, 0); - } - else if(TMI->isStore(srcNodeOpCode)) { - if(TMI->isStore(destNodeOpCode)) - memInst[srcIndex]->addOutEdge(memInst[destIndex], - MSchedGraphEdge::MemoryDep, - MSchedGraphEdge::OutputDep, 0); - - else - memInst[srcIndex]->addOutEdge(memInst[destIndex], - MSchedGraphEdge::MemoryDep, - MSchedGraphEdge::TrueDep, 0); - } + + //Get the machine opCode to determine type of memory instruction + MachineOpCode destNodeOpCode = destInst->getOpcode(); + + //Get the Value* that we are reading from the load, always the first op + const MachineOperand &mOp = srcInst->getOperand(0); + const MachineOperand &mOp2 = destInst->getOperand(0); + + if(mOp.hasAllocatedReg()) + if(mOp.getReg() == SparcV9::g0) + continue; + if(mOp2.hasAllocatedReg()) + if(mOp2.getReg() == SparcV9::g0) + continue; + + DEBUG(std::cerr << "Adding dependence for machine instructions\n"); + //Load-Store deps + if(TMI->isLoad(srcNodeOpCode)) { + + if(TMI->isStore(destNodeOpCode)) + memInst[srcIndex]->addOutEdge(memInst[destIndex], + MSchedGraphEdge::MemoryDep, + MSchedGraphEdge::AntiDep, 0); + } + else if(TMI->isStore(srcNodeOpCode)) { + if(TMI->isStore(destNodeOpCode)) + memInst[srcIndex]->addOutEdge(memInst[destIndex], + MSchedGraphEdge::MemoryDep, + MSchedGraphEdge::OutputDep, 0); + + else + memInst[srcIndex]->addOutEdge(memInst[destIndex], + MSchedGraphEdge::MemoryDep, + MSchedGraphEdge::TrueDep, 0); + } } } } Index: llvm/lib/Target/SparcV9/ModuloScheduling/MSchedGraph.h diff -u llvm/lib/Target/SparcV9/ModuloScheduling/MSchedGraph.h:1.14 llvm/lib/Target/SparcV9/ModuloScheduling/MSchedGraph.h:1.15 --- llvm/lib/Target/SparcV9/ModuloScheduling/MSchedGraph.h:1.14 Sat Apr 30 20:25:53 2005 +++ llvm/lib/Target/SparcV9/ModuloScheduling/MSchedGraph.h Wed Jul 27 00:53:44 2005 @@ -54,7 +54,7 @@ private: friend class MSchedGraphNode; MSchedGraphEdge(MSchedGraphNode *destination, MSchedGraphEdgeType type, - unsigned deptype, unsigned diff) + unsigned deptype, unsigned diff) : dest(destination), depType(type), depOrderType(deptype), iteDiff(diff) {} MSchedGraphNode *dest; @@ -79,7 +79,7 @@ public: MSchedGraphNode(const MachineInstr *inst, MSchedGraph *graph, - unsigned index, unsigned late=0, bool isBranch=false); + unsigned index, unsigned late=0, bool isBranch=false); MSchedGraphNode(const MSchedGraphNode &N); @@ -94,12 +94,12 @@ pred_const_iterator pred_end() const { return Predecessors.end(); } typedef MSchedGraphNodeIterator::const_iterator, - const MSchedGraphNode> succ_const_iterator; + const MSchedGraphNode> succ_const_iterator; succ_const_iterator succ_begin() const; succ_const_iterator succ_end() const; typedef MSchedGraphNodeIterator::iterator, - MSchedGraphNode> succ_iterator; + MSchedGraphNode> succ_iterator; succ_iterator succ_begin(); succ_iterator succ_end(); unsigned succ_size() { return Successors.size(); } @@ -119,17 +119,17 @@ void deleteSuccessor(MSchedGraphNode *node) { for (unsigned i = 0; i != Successors.size(); ++i) - if (Successors[i].getDest() == node) { - Successors.erase(Successors.begin()+i); - node->Predecessors.erase(std::find(node->Predecessors.begin(), - node->Predecessors.end(), this)); - --i; //Decrease index var since we deleted a node - } + if (Successors[i].getDest() == node) { + Successors.erase(Successors.begin()+i); + node->Predecessors.erase(std::find(node->Predecessors.begin(), + node->Predecessors.end(), this)); + --i; //Decrease index var since we deleted a node + } } void addOutEdge(MSchedGraphNode *destination, - MSchedGraphEdge::MSchedGraphEdgeType type, - unsigned deptype, unsigned diff=0) { + MSchedGraphEdge::MSchedGraphEdgeType type, + unsigned deptype, unsigned diff=0) { Successors.push_back(MSchedGraphEdge(destination, type, deptype,diff)); destination->Predecessors.push_back(this); } @@ -205,7 +205,7 @@ // ostream << operator for MSGraphNode class inline std::ostream &operator<<(std::ostream &os, - const MSchedGraphNode &node) { + const MSchedGraphNode &node) { node.print(os); return os; } @@ -243,27 +243,27 @@ typedef std::pair OpIndexNodePair; void buildNodesAndEdges(std::map &ignoreInstrs, DependenceAnalyzer &DA, std::map &machineTollvm); void addValueEdges(std::vector &NodesInMap, - MSchedGraphNode *node, - bool nodeIsUse, bool nodeIsDef, std::vector &phiInstrs, int diff=0); + MSchedGraphNode *node, + bool nodeIsUse, bool nodeIsDef, std::vector &phiInstrs, int diff=0); void addMachRegEdges(std::map >& regNumtoNodeMap); + std::vector >& regNumtoNodeMap); void addMemEdges(const std::vector& memInst, - DependenceAnalyzer &DA, std::map &machineTollvm); + DependenceAnalyzer &DA, std::map &machineTollvm); void addBranchEdges(); public: MSchedGraph(const MachineBasicBlock *bb, const TargetMachine &targ, - std::map &ignoreInstrs, - DependenceAnalyzer &DA, std::map &machineTollvm); + std::map &ignoreInstrs, + DependenceAnalyzer &DA, std::map &machineTollvm); //Copy constructor with maps to link old nodes to new nodes MSchedGraph(const MSchedGraph &G, std::map &newNodes); - - MSchedGraph(std::vector &bbs, - const TargetMachine &targ, - std::map &ignoreInstrs, - DependenceAnalyzer &DA, - std::map &machineTollvm); + + MSchedGraph(std::vector &bbs, + const TargetMachine &targ, + std::map &ignoreInstrs, + DependenceAnalyzer &DA, + std::map &machineTollvm); //Print graph void print(std::ostream &os) const; @@ -299,7 +299,7 @@ // Provide specializations of GraphTraits to be able to use graph // iterators on the scheduling graph static MSchedGraphNode& getSecond(std::pair &Pair) { + MSchedGraphNode*> &Pair) { return *Pair.second; } @@ -338,7 +338,7 @@ return N->succ_end(); } typedef std::pointer_to_unary_function&, MSchedGraphNode&> DerefFun; + MSchedGraphNode*>&, MSchedGraphNode&> DerefFun; typedef mapped_iterator nodes_iterator; static nodes_iterator nodes_begin(MSchedGraph *G) { @@ -383,7 +383,7 @@ } typedef std::pointer_to_unary_function&, MSchedGraphNode&> DerefFun; + MSchedGraphNode*>&, MSchedGraphNode&> DerefFun; typedef mapped_iterator nodes_iterator; static nodes_iterator nodes_begin(MSchedGraph *G) { Index: llvm/lib/Target/SparcV9/ModuloScheduling/MSchedGraphSB.cpp diff -u llvm/lib/Target/SparcV9/ModuloScheduling/MSchedGraphSB.cpp:1.3 llvm/lib/Target/SparcV9/ModuloScheduling/MSchedGraphSB.cpp:1.4 --- llvm/lib/Target/SparcV9/ModuloScheduling/MSchedGraphSB.cpp:1.3 Mon Jul 11 17:46:18 2005 +++ llvm/lib/Target/SparcV9/ModuloScheduling/MSchedGraphSB.cpp Wed Jul 27 00:53:44 2005 @@ -35,8 +35,8 @@ //MSchedGraphSBNode constructor MSchedGraphSBNode::MSchedGraphSBNode(const MachineInstr* inst, - MSchedGraphSB *graph, unsigned idx, - unsigned late, bool isBranch) + MSchedGraphSB *graph, unsigned idx, + unsigned late, bool isBranch) : Inst(inst), Parent(graph), index(idx), latency(late), isBranchInstr(isBranch) { @@ -46,9 +46,9 @@ //MSchedGraphSBNode constructor MSchedGraphSBNode::MSchedGraphSBNode(const MachineInstr* inst, - std::vector &other, - MSchedGraphSB *graph, unsigned idx, - unsigned late, bool isPNode) + std::vector &other, + MSchedGraphSB *graph, unsigned idx, + unsigned late, bool isPNode) : Inst(inst), otherInstrs(other), Parent(graph), index(idx), latency(late), isPredicateNode(isPNode) { @@ -95,7 +95,7 @@ //Get the iteration difference for the edge from this node to its successor unsigned MSchedGraphSBNode::getIteDiff(MSchedGraphSBNode *succ) { for(std::vector::iterator I = Successors.begin(), - E = Successors.end(); + E = Successors.end(); I != E; ++I) { if(I->getDest() == succ) return I->getIteDiff(); @@ -109,7 +109,7 @@ //return the edge the corresponds to this in edge int count = 0; for(MSchedGraphSBNode::succ_iterator I = pred->succ_begin(), - E = pred->succ_end(); + E = pred->succ_end(); I != E; ++I) { if(*I == this) return count; @@ -130,7 +130,7 @@ //Dtermine if pred is a predecessor of this node bool MSchedGraphSBNode::isPredecessor(MSchedGraphSBNode *pred) { if(std::find( Predecessors.begin(), Predecessors.end(), - pred) != Predecessors.end()) + pred) != Predecessors.end()) return true; else return false; @@ -138,11 +138,11 @@ //Add a node to the graph void MSchedGraphSB::addNode(const MachineInstr* MI, - MSchedGraphSBNode *node) { + MSchedGraphSBNode *node) { //Make sure node does not already exist assert(GraphMap.find(MI) == GraphMap.end() - && "New MSchedGraphSBNode already exists for this instruction"); + && "New MSchedGraphSBNode already exists for this instruction"); GraphMap[MI] = node; } @@ -168,10 +168,10 @@ //is a special case in Modulo Scheduling. We only want to deal with //the body of the loop. MSchedGraphSB::MSchedGraphSB(std::vector &bbs, - const TargetMachine &targ, - std::map &ignoreInstrs, - DependenceAnalyzer &DA, - std::map &machineTollvm) + const TargetMachine &targ, + std::map &ignoreInstrs, + DependenceAnalyzer &DA, + std::map &machineTollvm) : BBs(bbs), Target(targ) { //Make sure there is at least one BB and it is not null, @@ -207,11 +207,11 @@ assert(cond && "Condition must not be null!"); if(Instruction *I = dyn_cast(cond)) { - MachineCodeForInstruction & tempMvec = MachineCodeForInstruction::get(I); - if(tempMvec.size() > 0) { - DEBUG(std::cerr << *(tempMvec[tempMvec.size()-1]) << "\n");; - instr = (MachineInstr*) tempMvec[tempMvec.size()-1]; - } + MachineCodeForInstruction & tempMvec = MachineCodeForInstruction::get(I); + if(tempMvec.size() > 0) { + DEBUG(std::cerr << *(tempMvec[tempMvec.size()-1]) << "\n");; + instr = (MachineInstr*) tempMvec[tempMvec.size()-1]; + } } } @@ -223,15 +223,15 @@ for (unsigned j = 0; j < tempMvec.size(); j++) { MachineInstr *mi = tempMvec[j]; if(MTI->isNop(mi->getOpcode())) - continue; + continue; if(!instr) { - instr = mi; - DEBUG(std::cerr << "No Cond MI: " << *mi << "\n"); + instr = mi; + DEBUG(std::cerr << "No Cond MI: " << *mi << "\n"); } else { - DEBUG(std::cerr << *mi << "\n");; - otherInstrs.push_back(mi); + DEBUG(std::cerr << *mi << "\n");; + otherInstrs.push_back(mi); } } @@ -245,22 +245,22 @@ for(MachineBasicBlock::iterator I = mb->begin(), E = mb->end(); I != E; ++I) { MachineInstr *instr = I; if(MTI->isNop(instr->getOpcode()) || MTI->isBranch(instr->getOpcode())) - continue; + continue; if(node->getInst() == instr) - continue; + continue; for(unsigned i=0; i < instr->getNumOperands(); ++i) { - MachineOperand &mOp = instr->getOperand(i); - if(mOp.isDef() && mOp.getType() == MachineOperand::MO_VirtualRegister) { - Value *val = mOp.getVRegValue(); - //Check if there is a use not in the trace - for(Value::use_iterator V = val->use_begin(), VE = val->use_end(); V != VE; ++V) { - if (Instruction *Inst = dyn_cast(*V)) { - if(llvmBBs.count(Inst->getParent())) - liveOutsideTrace[node].insert(instr); - } - } - } + MachineOperand &mOp = instr->getOperand(i); + if(mOp.isDef() && mOp.getType() == MachineOperand::MO_VirtualRegister) { + Value *val = mOp.getVRegValue(); + //Check if there is a use not in the trace + for(Value::use_iterator V = val->use_begin(), VE = val->use_end(); V != VE; ++V) { + if (Instruction *Inst = dyn_cast(*V)) { + if(llvmBBs.count(Inst->getParent())) + liveOutsideTrace[node].insert(instr); + } + } + } } } @@ -275,7 +275,7 @@ //Copies the graph and keeps a map from old to new nodes MSchedGraphSB::MSchedGraphSB(const MSchedGraphSB &G, - std::map &newNodes) + std::map &newNodes) : Target(G.Target) { BBs = G.BBs; @@ -283,7 +283,7 @@ std::map oldToNew; //Copy all nodes for(MSchedGraphSB::const_iterator N = G.GraphMap.begin(), - NE = G.GraphMap.end(); N != NE; ++N) { + NE = G.GraphMap.end(); N != NE; ++N) { MSchedGraphSBNode *newNode = new MSchedGraphSBNode(*(N->second)); oldToNew[&*(N->second)] = newNode; @@ -381,9 +381,9 @@ //Add edges between the nodes void MSchedGraphSB::buildNodesAndEdges(std::map &ignoreInstrs, - DependenceAnalyzer &DA, - std::map &machineTollvm, - std::map > &liveOutsideTrace) { + DependenceAnalyzer &DA, + std::map &machineTollvm, + std::map > &liveOutsideTrace) { //Get Machine target information for calculating latency @@ -401,19 +401,19 @@ for(std::vector::iterator B = BBs.begin(), - BE = BBs.end(); B != BE; ++B) { + BE = BBs.end(); B != BE; ++B) { const MachineBasicBlock *BB = *B; //Loop over instructions in MBB and add nodes and edges for (MachineBasicBlock::const_iterator MI = BB->begin(), e = BB->end(); - MI != e; ++MI) { + MI != e; ++MI) { //Ignore indvar instructions if(ignoreInstrs.count(MI)) { - ++index; - continue; + ++index; + continue; } //Get each instruction of machine basic block, get the delay @@ -429,7 +429,7 @@ //Create new node for this machine instruction and add to the graph. //Create only if not a nop if(MTI->isNop(opCode)) - continue; + continue; //Sparc BE does not use PHI opcode, so assert on this case assert(opCode != TargetInstrInfo::PHI && "Did not expect PHI opcode"); @@ -438,106 +438,106 @@ //Skip branches if(MTI->isBranch(opCode)) - continue; + continue; //Node is created and added to the graph automatically MSchedGraphSBNode *node = 0; if(!GraphMap.count(MI)){ - node = new MSchedGraphSBNode(MI, this, index, delay); - DEBUG(std::cerr << "Created Node: " << *node << "\n"); + node = new MSchedGraphSBNode(MI, this, index, delay); + DEBUG(std::cerr << "Created Node: " << *node << "\n"); } else { - node = GraphMap[MI]; - if(node->isPredicate()) { - //Create edge between this node and last pred, then switch to new pred - if(lastPred) { - lastPred->addOutEdge(node, MSchedGraphSBEdge::PredDep, - MSchedGraphSBEdge::NonDataDep, 0); - - if(liveOutsideTrace.count(lastPred)) { - for(std::set::iterator L = liveOutsideTrace[lastPred].begin(), LE = liveOutsideTrace[lastPred].end(); L != LE; ++L) - lastPred->addOutEdge(GraphMap[*L], MSchedGraphSBEdge::PredDep, - MSchedGraphSBEdge::NonDataDep, 1); - } - - } - - lastPred = node; - } + node = GraphMap[MI]; + if(node->isPredicate()) { + //Create edge between this node and last pred, then switch to new pred + if(lastPred) { + lastPred->addOutEdge(node, MSchedGraphSBEdge::PredDep, + MSchedGraphSBEdge::NonDataDep, 0); + + if(liveOutsideTrace.count(lastPred)) { + for(std::set::iterator L = liveOutsideTrace[lastPred].begin(), LE = liveOutsideTrace[lastPred].end(); L != LE; ++L) + lastPred->addOutEdge(GraphMap[*L], MSchedGraphSBEdge::PredDep, + MSchedGraphSBEdge::NonDataDep, 1); + } + + } + + lastPred = node; + } } //Add dependencies to instructions that cause exceptions if(lastPred) - lastPred->print(std::cerr); + lastPred->print(std::cerr); if(!node->isPredicate() && instrCauseException(opCode)) { - if(lastPred) { - lastPred->addOutEdge(node, MSchedGraphSBEdge::PredDep, - MSchedGraphSBEdge::NonDataDep, 0); - } + if(lastPred) { + lastPred->addOutEdge(node, MSchedGraphSBEdge::PredDep, + MSchedGraphSBEdge::NonDataDep, 0); + } } //Check OpCode to keep track of memory operations to add memory //dependencies later. if(MTI->isLoad(opCode) || MTI->isStore(opCode)) - memInstructions.push_back(node); + memInstructions.push_back(node); //Loop over all operands, and put them into the register number to //graph node map for determining dependencies //If an operands is a use/def, we have an anti dependence to itself for(unsigned i=0; i < MI->getNumOperands(); ++i) { - //Get Operand - const MachineOperand &mOp = MI->getOperand(i); - - //Check if it has an allocated register - if(mOp.hasAllocatedReg()) { - int regNum = mOp.getReg(); - - if(regNum != SparcV9::g0) { - //Put into our map - regNumtoNodeMap[regNum].push_back(std::make_pair(i, node)); - } - continue; - } - - - //Add virtual registers dependencies - //Check if any exist in the value map already and create dependencies - //between them. - if(mOp.getType() == MachineOperand::MO_VirtualRegister - || mOp.getType() == MachineOperand::MO_CCRegister) { - - //Make sure virtual register value is not null - assert((mOp.getVRegValue() != NULL) && "Null value is defined"); - - //Check if this is a read operation in a phi node, if so DO NOT PROCESS - if(mOp.isUse() && (opCode == TargetInstrInfo::PHI)) { - DEBUG(std::cerr << "Read Operation in a PHI node\n"); - continue; - } - - if (const Value* srcI = mOp.getVRegValue()) { - - //Find value in the map - std::map >::iterator V - = valuetoNodeMap.find(srcI); - - //If there is something in the map already, add edges from - //those instructions - //to this one we are processing - if(V != valuetoNodeMap.end()) { - addValueEdges(V->second, node, mOp.isUse(), mOp.isDef(), phiInstrs); - - //Add to value map - V->second.push_back(std::make_pair(i,node)); - } - //Otherwise put it in the map - else - //Put into value map - valuetoNodeMap[mOp.getVRegValue()].push_back(std::make_pair(i, node)); - } - } + //Get Operand + const MachineOperand &mOp = MI->getOperand(i); + + //Check if it has an allocated register + if(mOp.hasAllocatedReg()) { + int regNum = mOp.getReg(); + + if(regNum != SparcV9::g0) { + //Put into our map + regNumtoNodeMap[regNum].push_back(std::make_pair(i, node)); + } + continue; + } + + + //Add virtual registers dependencies + //Check if any exist in the value map already and create dependencies + //between them. + if(mOp.getType() == MachineOperand::MO_VirtualRegister + || mOp.getType() == MachineOperand::MO_CCRegister) { + + //Make sure virtual register value is not null + assert((mOp.getVRegValue() != NULL) && "Null value is defined"); + + //Check if this is a read operation in a phi node, if so DO NOT PROCESS + if(mOp.isUse() && (opCode == TargetInstrInfo::PHI)) { + DEBUG(std::cerr << "Read Operation in a PHI node\n"); + continue; + } + + if (const Value* srcI = mOp.getVRegValue()) { + + //Find value in the map + std::map >::iterator V + = valuetoNodeMap.find(srcI); + + //If there is something in the map already, add edges from + //those instructions + //to this one we are processing + if(V != valuetoNodeMap.end()) { + addValueEdges(V->second, node, mOp.isUse(), mOp.isDef(), phiInstrs); + + //Add to value map + V->second.push_back(std::make_pair(i,node)); + } + //Otherwise put it in the map + else + //Put into value map + valuetoNodeMap[mOp.getVRegValue()].push_back(std::make_pair(i, node)); + } + } } ++index; } @@ -546,15 +546,15 @@ //phiInstr list to process const BasicBlock *llvm_bb = BB->getBasicBlock(); for(BasicBlock::const_iterator I = llvm_bb->begin(), E = llvm_bb->end(); - I != E; ++I) { + I != E; ++I) { if(const PHINode *PN = dyn_cast(I)) { - MachineCodeForInstruction & tempMvec = MachineCodeForInstruction::get(PN); - for (unsigned j = 0; j < tempMvec.size(); j++) { - if(!ignoreInstrs.count(tempMvec[j])) { - DEBUG(std::cerr << "Inserting phi instr into map: " << *tempMvec[j] << "\n"); - phiInstrs.push_back((MachineInstr*) tempMvec[j]); - } - } + MachineCodeForInstruction & tempMvec = MachineCodeForInstruction::get(PN); + for (unsigned j = 0; j < tempMvec.size(); j++) { + if(!ignoreInstrs.count(tempMvec[j])) { + DEBUG(std::cerr << "Inserting phi instr into map: " << *tempMvec[j] << "\n"); + phiInstrs.push_back((MachineInstr*) tempMvec[j]); + } + } } } @@ -564,14 +564,14 @@ //Finally deal with PHI Nodes and Value* for(std::vector::iterator I = phiInstrs.begin(), - E = phiInstrs.end(); I != E; ++I) { + E = phiInstrs.end(); I != E; ++I) { //Get Node for this instruction std::map::iterator X; X = find(*I); if(X == GraphMap.end()) - continue; + continue; MSchedGraphSBNode *node = X->second; @@ -579,38 +579,38 @@ //Loop over operands for this instruction and add value edges for(unsigned i=0; i < (*I)->getNumOperands(); ++i) { - //Get Operand - const MachineOperand &mOp = (*I)->getOperand(i); - if((mOp.getType() == MachineOperand::MO_VirtualRegister - || mOp.getType() == MachineOperand::MO_CCRegister) && mOp.isUse()) { - - //find the value in the map - if (const Value* srcI = mOp.getVRegValue()) { - - //Find value in the map - std::map >::iterator V - = valuetoNodeMap.find(srcI); - - //If there is something in the map already, add edges from - //those instructions - //to this one we are processing - if(V != valuetoNodeMap.end()) { - addValueEdges(V->second, node, mOp.isUse(), mOp.isDef(), - phiInstrs, 1); - } - } - } + //Get Operand + const MachineOperand &mOp = (*I)->getOperand(i); + if((mOp.getType() == MachineOperand::MO_VirtualRegister + || mOp.getType() == MachineOperand::MO_CCRegister) && mOp.isUse()) { + + //find the value in the map + if (const Value* srcI = mOp.getVRegValue()) { + + //Find value in the map + std::map >::iterator V + = valuetoNodeMap.find(srcI); + + //If there is something in the map already, add edges from + //those instructions + //to this one we are processing + if(V != valuetoNodeMap.end()) { + addValueEdges(V->second, node, mOp.isUse(), mOp.isDef(), + phiInstrs, 1); + } + } + } } } } } //Add dependencies for Value*s void MSchedGraphSB::addValueEdges(std::vector &NodesInMap, - MSchedGraphSBNode *destNode, bool nodeIsUse, - bool nodeIsDef, std::vector &phiInstrs, int diff) { + MSchedGraphSBNode *destNode, bool nodeIsUse, + bool nodeIsDef, std::vector &phiInstrs, int diff) { for(std::vector::iterator I = NodesInMap.begin(), - E = NodesInMap.end(); I != E; ++I) { + E = NodesInMap.end(); I != E; ++I) { //Get node in vectors machine operand that is the same value as node MSchedGraphSBNode *srcNode = I->second; @@ -618,26 +618,26 @@ if(diff > 0) if(std::find(phiInstrs.begin(), phiInstrs.end(), srcNode->getInst()) == phiInstrs.end()) - continue; + continue; //Node is a Def, so add output dep. if(nodeIsDef) { if(mOp.isUse()) { - DEBUG(std::cerr << "Edge from " << *srcNode << " to " << *destNode << " (itediff=" << diff << ", type=anti)\n"); - srcNode->addOutEdge(destNode, MSchedGraphSBEdge::ValueDep, - MSchedGraphSBEdge::AntiDep, diff); + DEBUG(std::cerr << "Edge from " << *srcNode << " to " << *destNode << " (itediff=" << diff << ", type=anti)\n"); + srcNode->addOutEdge(destNode, MSchedGraphSBEdge::ValueDep, + MSchedGraphSBEdge::AntiDep, diff); } if(mOp.isDef()) { - DEBUG(std::cerr << "Edge from " << *srcNode << " to " << *destNode << " (itediff=" << diff << ", type=output)\n"); - srcNode->addOutEdge(destNode, MSchedGraphSBEdge::ValueDep, - MSchedGraphSBEdge::OutputDep, diff); + DEBUG(std::cerr << "Edge from " << *srcNode << " to " << *destNode << " (itediff=" << diff << ", type=output)\n"); + srcNode->addOutEdge(destNode, MSchedGraphSBEdge::ValueDep, + MSchedGraphSBEdge::OutputDep, diff); } } if(nodeIsUse) { if(mOp.isDef()) { - DEBUG(std::cerr << "Edge from " << *srcNode << " to " << *destNode << " (itediff=" << diff << ", type=true)\n"); - srcNode->addOutEdge(destNode, MSchedGraphSBEdge::ValueDep, - MSchedGraphSBEdge::TrueDep, diff); + DEBUG(std::cerr << "Edge from " << *srcNode << " to " << *destNode << " (itediff=" << diff << ", type=true)\n"); + srcNode->addOutEdge(destNode, MSchedGraphSBEdge::ValueDep, + MSchedGraphSBEdge::TrueDep, diff); } } } @@ -675,71 +675,71 @@ //Look at all instructions after this in execution order for(unsigned j=i+1; j < Nodes.size(); ++j) { - - //Sink node is a write - if(Nodes[j].second->getInst()->getOperand(Nodes[j].first).isDef()) { - //Src only uses the register (read) + + //Sink node is a write + if(Nodes[j].second->getInst()->getOperand(Nodes[j].first).isDef()) { + //Src only uses the register (read) if(srcIsUse) - srcNode->addOutEdge(Nodes[j].second, - MSchedGraphSBEdge::MachineRegister, - MSchedGraphSBEdge::AntiDep); - + srcNode->addOutEdge(Nodes[j].second, + MSchedGraphSBEdge::MachineRegister, + MSchedGraphSBEdge::AntiDep); + else if(srcIsUseandDef) { - srcNode->addOutEdge(Nodes[j].second, - MSchedGraphSBEdge::MachineRegister, - MSchedGraphSBEdge::AntiDep); - - srcNode->addOutEdge(Nodes[j].second, - MSchedGraphSBEdge::MachineRegister, - MSchedGraphSBEdge::OutputDep); - } + srcNode->addOutEdge(Nodes[j].second, + MSchedGraphSBEdge::MachineRegister, + MSchedGraphSBEdge::AntiDep); + + srcNode->addOutEdge(Nodes[j].second, + MSchedGraphSBEdge::MachineRegister, + MSchedGraphSBEdge::OutputDep); + } else - srcNode->addOutEdge(Nodes[j].second, - MSchedGraphSBEdge::MachineRegister, - MSchedGraphSBEdge::OutputDep); - } - //Dest node is a read - else { - if(!srcIsUse || srcIsUseandDef) - srcNode->addOutEdge(Nodes[j].second, - MSchedGraphSBEdge::MachineRegister, - MSchedGraphSBEdge::TrueDep); - } + srcNode->addOutEdge(Nodes[j].second, + MSchedGraphSBEdge::MachineRegister, + MSchedGraphSBEdge::OutputDep); + } + //Dest node is a read + else { + if(!srcIsUse || srcIsUseandDef) + srcNode->addOutEdge(Nodes[j].second, + MSchedGraphSBEdge::MachineRegister, + MSchedGraphSBEdge::TrueDep); + } } //Look at all the instructions before this one since machine registers //could live across iterations. for(unsigned j = 0; j < i; ++j) { - //Sink node is a write - if(Nodes[j].second->getInst()->getOperand(Nodes[j].first).isDef()) { - //Src only uses the register (read) + //Sink node is a write + if(Nodes[j].second->getInst()->getOperand(Nodes[j].first).isDef()) { + //Src only uses the register (read) if(srcIsUse) - srcNode->addOutEdge(Nodes[j].second, - MSchedGraphSBEdge::MachineRegister, - MSchedGraphSBEdge::AntiDep, 1); + srcNode->addOutEdge(Nodes[j].second, + MSchedGraphSBEdge::MachineRegister, + MSchedGraphSBEdge::AntiDep, 1); else if(srcIsUseandDef) { - srcNode->addOutEdge(Nodes[j].second, - MSchedGraphSBEdge::MachineRegister, - MSchedGraphSBEdge::AntiDep, 1); - - srcNode->addOutEdge(Nodes[j].second, - MSchedGraphSBEdge::MachineRegister, - MSchedGraphSBEdge::OutputDep, 1); - } + srcNode->addOutEdge(Nodes[j].second, + MSchedGraphSBEdge::MachineRegister, + MSchedGraphSBEdge::AntiDep, 1); + + srcNode->addOutEdge(Nodes[j].second, + MSchedGraphSBEdge::MachineRegister, + MSchedGraphSBEdge::OutputDep, 1); + } else - srcNode->addOutEdge(Nodes[j].second, - MSchedGraphSBEdge::MachineRegister, - MSchedGraphSBEdge::OutputDep, 1); - } - //Dest node is a read - else { - if(!srcIsUse || srcIsUseandDef) - srcNode->addOutEdge(Nodes[j].second, - MSchedGraphSBEdge::MachineRegister, - MSchedGraphSBEdge::TrueDep,1 ); - } - + srcNode->addOutEdge(Nodes[j].second, + MSchedGraphSBEdge::MachineRegister, + MSchedGraphSBEdge::OutputDep, 1); + } + //Dest node is a read + else { + if(!srcIsUse || srcIsUseandDef) + srcNode->addOutEdge(Nodes[j].second, + MSchedGraphSBEdge::MachineRegister, + MSchedGraphSBEdge::TrueDep,1 ); + } + } @@ -752,8 +752,8 @@ //Add edges between all loads and stores //Can be less strict with alias analysis and data dependence analysis. void MSchedGraphSB::addMemEdges(const std::vector& memInst, - DependenceAnalyzer &DA, - std::map &machineTollvm) { + DependenceAnalyzer &DA, + std::map &machineTollvm) { //Get Target machine instruction info const TargetInstrInfo *TMI = Target.getInstrInfo(); @@ -773,7 +773,7 @@ //No self loops if(destIndex == srcIndex) - continue; + continue; MachineInstr *destInst = (MachineInstr*) memInst[destIndex]->getInst(); @@ -783,7 +783,7 @@ //Assuming instructions without corresponding llvm instructions //are from constant pools. if (!machineTollvm.count(srcInst) || !machineTollvm.count(destInst)) - continue; + continue; bool useDepAnalyzer = true; @@ -792,78 +792,78 @@ Instruction *srcLLVM = machineTollvm[srcInst]; Instruction *destLLVM = machineTollvm[destInst]; if(!isa(srcLLVM) - && !isa(srcLLVM)) { - if(isa(srcLLVM)) { - if(isa(srcLLVM->getOperand(0)) || isa(srcLLVM->getOperand(1))) - continue; - } - useDepAnalyzer = false; + && !isa(srcLLVM)) { + if(isa(srcLLVM)) { + if(isa(srcLLVM->getOperand(0)) || isa(srcLLVM->getOperand(1))) + continue; + } + useDepAnalyzer = false; } if(!isa(destLLVM) - && !isa(destLLVM)) { - if(isa(destLLVM)) { - if(isa(destLLVM->getOperand(0)) || isa(destLLVM->getOperand(1))) - continue; - } - useDepAnalyzer = false; + && !isa(destLLVM)) { + if(isa(destLLVM)) { + if(isa(destLLVM->getOperand(0)) || isa(destLLVM->getOperand(1))) + continue; + } + useDepAnalyzer = false; } //Use dep analysis when we have corresponding llvm loads/stores if(useDepAnalyzer) { - bool srcBeforeDest = true; - if(destIndex < srcIndex) - srcBeforeDest = false; - - DependenceResult dr = DA.getDependenceInfo(machineTollvm[srcInst], - machineTollvm[destInst], - srcBeforeDest); - - for(std::vector::iterator d = dr.dependences.begin(), - de = dr.dependences.end(); d != de; ++d) { - //Add edge from load to store - memInst[srcIndex]->addOutEdge(memInst[destIndex], - MSchedGraphSBEdge::MemoryDep, - d->getDepType(), d->getIteDiff()); - - } + bool srcBeforeDest = true; + if(destIndex < srcIndex) + srcBeforeDest = false; + + DependenceResult dr = DA.getDependenceInfo(machineTollvm[srcInst], + machineTollvm[destInst], + srcBeforeDest); + + for(std::vector::iterator d = dr.dependences.begin(), + de = dr.dependences.end(); d != de; ++d) { + //Add edge from load to store + memInst[srcIndex]->addOutEdge(memInst[destIndex], + MSchedGraphSBEdge::MemoryDep, + d->getDepType(), d->getIteDiff()); + + } } //Otherwise, we can not do any further analysis and must make a dependence else { - - //Get the machine opCode to determine type of memory instruction - MachineOpCode destNodeOpCode = destInst->getOpcode(); - - //Get the Value* that we are reading from the load, always the first op - const MachineOperand &mOp = srcInst->getOperand(0); - const MachineOperand &mOp2 = destInst->getOperand(0); - - if(mOp.hasAllocatedReg()) - if(mOp.getReg() == SparcV9::g0) - continue; - if(mOp2.hasAllocatedReg()) - if(mOp2.getReg() == SparcV9::g0) - continue; - - DEBUG(std::cerr << "Adding dependence for machine instructions\n"); - //Load-Store deps - if(TMI->isLoad(srcNodeOpCode)) { - - if(TMI->isStore(destNodeOpCode)) - memInst[srcIndex]->addOutEdge(memInst[destIndex], - MSchedGraphSBEdge::MemoryDep, - MSchedGraphSBEdge::AntiDep, 0); - } - else if(TMI->isStore(srcNodeOpCode)) { - if(TMI->isStore(destNodeOpCode)) - memInst[srcIndex]->addOutEdge(memInst[destIndex], - MSchedGraphSBEdge::MemoryDep, - MSchedGraphSBEdge::OutputDep, 0); - - else - memInst[srcIndex]->addOutEdge(memInst[destIndex], - MSchedGraphSBEdge::MemoryDep, - MSchedGraphSBEdge::TrueDep, 0); - } + + //Get the machine opCode to determine type of memory instruction + MachineOpCode destNodeOpCode = destInst->getOpcode(); + + //Get the Value* that we are reading from the load, always the first op + const MachineOperand &mOp = srcInst->getOperand(0); + const MachineOperand &mOp2 = destInst->getOperand(0); + + if(mOp.hasAllocatedReg()) + if(mOp.getReg() == SparcV9::g0) + continue; + if(mOp2.hasAllocatedReg()) + if(mOp2.getReg() == SparcV9::g0) + continue; + + DEBUG(std::cerr << "Adding dependence for machine instructions\n"); + //Load-Store deps + if(TMI->isLoad(srcNodeOpCode)) { + + if(TMI->isStore(destNodeOpCode)) + memInst[srcIndex]->addOutEdge(memInst[destIndex], + MSchedGraphSBEdge::MemoryDep, + MSchedGraphSBEdge::AntiDep, 0); + } + else if(TMI->isStore(srcNodeOpCode)) { + if(TMI->isStore(destNodeOpCode)) + memInst[srcIndex]->addOutEdge(memInst[destIndex], + MSchedGraphSBEdge::MemoryDep, + MSchedGraphSBEdge::OutputDep, 0); + + else + memInst[srcIndex]->addOutEdge(memInst[destIndex], + MSchedGraphSBEdge::MemoryDep, + MSchedGraphSBEdge::TrueDep, 0); + } } } } Index: llvm/lib/Target/SparcV9/ModuloScheduling/MSchedGraphSB.h diff -u llvm/lib/Target/SparcV9/ModuloScheduling/MSchedGraphSB.h:1.1 llvm/lib/Target/SparcV9/ModuloScheduling/MSchedGraphSB.h:1.2 --- llvm/lib/Target/SparcV9/ModuloScheduling/MSchedGraphSB.h:1.1 Thu Jun 16 23:16:14 2005 +++ llvm/lib/Target/SparcV9/ModuloScheduling/MSchedGraphSB.h Wed Jul 27 00:53:44 2005 @@ -56,7 +56,7 @@ private: friend class MSchedGraphSBNode; MSchedGraphSBEdge(MSchedGraphSBNode *destination, MSchedGraphSBEdgeType type, - unsigned deptype, unsigned diff) + unsigned deptype, unsigned diff) : dest(destination), depType(type), depOrderType(deptype), iteDiff(diff) {} MSchedGraphSBNode *dest; @@ -84,10 +84,10 @@ public: MSchedGraphSBNode(const MachineInstr* inst, MSchedGraphSB *graph, - unsigned index, unsigned late=0, bool isBranch=false); - MSchedGraphSBNode(const MachineInstr* inst, std::vector &other, - MSchedGraphSB *graph, - unsigned index, unsigned late=0, bool isPNode=true); + unsigned index, unsigned late=0, bool isBranch=false); + MSchedGraphSBNode(const MachineInstr* inst, std::vector &other, + MSchedGraphSB *graph, + unsigned index, unsigned late=0, bool isPNode=true); MSchedGraphSBNode(const MSchedGraphSBNode &N); //Iterators - Predecessor and Succussor @@ -101,12 +101,12 @@ pred_const_iterator pred_end() const { return Predecessors.end(); } typedef MSchedGraphSBNodeIterator::const_iterator, - const MSchedGraphSBNode> succ_const_iterator; + const MSchedGraphSBNode> succ_const_iterator; succ_const_iterator succ_begin() const; succ_const_iterator succ_end() const; typedef MSchedGraphSBNodeIterator::iterator, - MSchedGraphSBNode> succ_iterator; + MSchedGraphSBNode> succ_iterator; succ_iterator succ_begin(); succ_iterator succ_end(); unsigned succ_size() { return Successors.size(); } @@ -126,17 +126,17 @@ void deleteSuccessor(MSchedGraphSBNode *node) { for (unsigned i = 0; i != Successors.size(); ++i) - if (Successors[i].getDest() == node) { - Successors.erase(Successors.begin()+i); - node->Predecessors.erase(std::find(node->Predecessors.begin(), - node->Predecessors.end(), this)); - --i; //Decrease index var since we deleted a node - } + if (Successors[i].getDest() == node) { + Successors.erase(Successors.begin()+i); + node->Predecessors.erase(std::find(node->Predecessors.begin(), + node->Predecessors.end(), this)); + --i; //Decrease index var since we deleted a node + } } void addOutEdge(MSchedGraphSBNode *destination, - MSchedGraphSBEdge::MSchedGraphSBEdgeType type, - unsigned deptype, unsigned diff=0) { + MSchedGraphSBEdge::MSchedGraphSBEdgeType type, + unsigned deptype, unsigned diff=0) { Successors.push_back(MSchedGraphSBEdge(destination, type, deptype,diff)); destination->Predecessors.push_back(this); } @@ -215,7 +215,7 @@ // ostream << operator for MSGraphNode class inline std::ostream &operator<<(std::ostream &os, - const MSchedGraphSBNode &node) { + const MSchedGraphSBNode &node) { node.print(os); return os; } @@ -253,29 +253,29 @@ typedef std::pair OpIndexNodePair; void buildNodesAndEdges(std::map &ignoreInstrs, DependenceAnalyzer &DA, std::map &machineTollvm, std::map > &liveOutsideTrace); void addValueEdges(std::vector &NodesInMap, - MSchedGraphSBNode *node, - bool nodeIsUse, bool nodeIsDef, std::vector &phiInstrs, int diff=0); + MSchedGraphSBNode *node, + bool nodeIsUse, bool nodeIsDef, std::vector &phiInstrs, int diff=0); void addMachRegEdges(std::map >& regNumtoNodeMap); + std::vector >& regNumtoNodeMap); void addMemEdges(const std::vector& memInst, - DependenceAnalyzer &DA, std::map &machineTollvm); - + DependenceAnalyzer &DA, std::map &machineTollvm); + bool instrCauseException(MachineOpCode opCode); public: MSchedGraphSB(const MachineBasicBlock *bb, const TargetMachine &targ, - std::map &ignoreInstrs, - DependenceAnalyzer &DA, std::map &machineTollvm); + std::map &ignoreInstrs, + DependenceAnalyzer &DA, std::map &machineTollvm); //Copy constructor with maps to link old nodes to new nodes MSchedGraphSB(const MSchedGraphSB &G, std::map &newNodes); - - MSchedGraphSB(std::vector &bbs, - const TargetMachine &targ, - std::map &ignoreInstrs, - DependenceAnalyzer &DA, - std::map &machineTollvm); + + MSchedGraphSB(std::vector &bbs, + const TargetMachine &targ, + std::map &ignoreInstrs, + DependenceAnalyzer &DA, + std::map &machineTollvm); //Print graph void print(std::ostream &os) const; @@ -311,7 +311,7 @@ // Provide specializations of GraphTraits to be able to use graph // iterators on the scheduling graph static MSchedGraphSBNode& getSecond(std::pair &Pair) { + MSchedGraphSBNode*> &Pair) { return *Pair.second; } @@ -350,7 +350,7 @@ return N->succ_end(); } typedef std::pointer_to_unary_function&, MSchedGraphSBNode&> DerefFun; + MSchedGraphSBNode*>&, MSchedGraphSBNode&> DerefFun; typedef mapped_iterator nodes_iterator; static nodes_iterator nodes_begin(MSchedGraphSB *G) { @@ -395,7 +395,7 @@ } typedef std::pointer_to_unary_function&, MSchedGraphSBNode&> DerefFun; + MSchedGraphSBNode*>&, MSchedGraphSBNode&> DerefFun; typedef mapped_iterator nodes_iterator; static nodes_iterator nodes_begin(MSchedGraphSB *G) { Index: llvm/lib/Target/SparcV9/ModuloScheduling/ModuloScheduling.cpp diff -u llvm/lib/Target/SparcV9/ModuloScheduling/ModuloScheduling.cpp:1.50 llvm/lib/Target/SparcV9/ModuloScheduling/ModuloScheduling.cpp:1.51 --- llvm/lib/Target/SparcV9/ModuloScheduling/ModuloScheduling.cpp:1.50 Thu Jun 16 23:00:57 2005 +++ llvm/lib/Target/SparcV9/ModuloScheduling/ModuloScheduling.cpp Wed Jul 27 00:53:44 2005 @@ -100,34 +100,34 @@ static std::string getNodeLabel(MSchedGraphNode *Node, MSchedGraph *Graph) { if (Node->getInst()) { - std::stringstream ss; - ss << *(Node->getInst()); - return ss.str(); //((MachineInstr*)Node->getInst()); + std::stringstream ss; + ss << *(Node->getInst()); + return ss.str(); //((MachineInstr*)Node->getInst()); } else - return "No Inst"; + return "No Inst"; } static std::string getEdgeSourceLabel(MSchedGraphNode *Node, - MSchedGraphNode::succ_iterator I) { + MSchedGraphNode::succ_iterator I) { //Label each edge with the type of dependence std::string edgelabel = ""; switch (I.getEdge().getDepOrderType()) { - + case MSchedGraphEdge::TrueDep: - edgelabel = "True"; - break; + edgelabel = "True"; + break; case MSchedGraphEdge::AntiDep: - edgelabel = "Anti"; - break; - + edgelabel = "Anti"; + break; + case MSchedGraphEdge::OutputDep: - edgelabel = "Output"; - break; - + edgelabel = "Output"; + break; + default: - edgelabel = "Unknown"; - break; + edgelabel = "Unknown"; + break; } //FIXME @@ -173,11 +173,11 @@ for (MachineFunction::iterator BI = MF.begin(); BI != MF.end(); ++BI) if(MachineBBisValid(BI)) { if(BI->size() < 100) { - Worklist.push_back(&*BI); - ++ValidLoops; + Worklist.push_back(&*BI); + ++ValidLoops; } else - ++JumboBB; + ++JumboBB; } @@ -187,7 +187,7 @@ //Iterate over the worklist and perform scheduling for(std::vector::iterator BI = Worklist.begin(), - BE = Worklist.end(); BI != BE; ++BI) { + BE = Worklist.end(); BI != BE; ++BI) { //Print out BB for debugging DEBUG(std::cerr << "BB Size: " << (*BI)->size() << "\n"); @@ -236,41 +236,41 @@ //Dump node properties if in debug mode DEBUG(for(std::map::iterator I = nodeToAttributesMap.begin(), - E = nodeToAttributesMap.end(); I !=E; ++I) { - std::cerr << "Node: " << *(I->first) << " ASAP: " << I->second.ASAP << " ALAP: " - << I->second.ALAP << " MOB: " << I->second.MOB << " Depth: " << I->second.depth - << " Height: " << I->second.height << "\n"; - }); + E = nodeToAttributesMap.end(); I !=E; ++I) { + std::cerr << "Node: " << *(I->first) << " ASAP: " << I->second.ASAP << " ALAP: " + << I->second.ALAP << " MOB: " << I->second.MOB << " Depth: " << I->second.depth + << " Height: " << I->second.height << "\n"; + }); //Calculate Node Properties calculateNodeAttributes(MSG, ResMII); //Dump node properties if in debug mode DEBUG(for(std::map::iterator I = nodeToAttributesMap.begin(), - E = nodeToAttributesMap.end(); I !=E; ++I) { - std::cerr << "Node: " << *(I->first) << " ASAP: " << I->second.ASAP << " ALAP: " - << I->second.ALAP << " MOB: " << I->second.MOB << " Depth: " << I->second.depth - << " Height: " << I->second.height << "\n"; - }); + E = nodeToAttributesMap.end(); I !=E; ++I) { + std::cerr << "Node: " << *(I->first) << " ASAP: " << I->second.ASAP << " ALAP: " + << I->second.ALAP << " MOB: " << I->second.MOB << " Depth: " << I->second.depth + << " Height: " << I->second.height << "\n"; + }); //Put nodes in order to schedule them computePartialOrder(); //Dump out partial order DEBUG(for(std::vector >::iterator I = partialOrder.begin(), - E = partialOrder.end(); I !=E; ++I) { - std::cerr << "Start set in PO\n"; - for(std::set::iterator J = I->begin(), JE = I->end(); J != JE; ++J) - std::cerr << "PO:" << **J << "\n"; - }); + E = partialOrder.end(); I !=E; ++I) { + std::cerr << "Start set in PO\n"; + for(std::set::iterator J = I->begin(), JE = I->end(); J != JE; ++J) + std::cerr << "PO:" << **J << "\n"; + }); //Place nodes in final order orderNodes(); //Dump out order of nodes DEBUG(for(std::vector::iterator I = FinalNodeOrder.begin(), E = FinalNodeOrder.end(); I != E; ++I) { - std::cerr << "FO:" << **I << "\n"; - }); + std::cerr << "FO:" << **I << "\n"; + }); //Finally schedule nodes bool haveSched = computeSchedule(*BI, MSG); @@ -288,7 +288,7 @@ IISum += mII; if(schedule.getMaxStage() == 0) - ++SameStage; + ++SameStage; } else { ++NoSched; @@ -323,20 +323,20 @@ for(unsigned opNum = 0; opNum < I->getNumOperands(); ++opNum) { const MachineOperand &mOp = I->getOperand(opNum); if(mOp.getType() == MachineOperand::MO_VirtualRegister && mOp.isDef()) { - //assert if this is the second def we have seen - //DEBUG(std::cerr << "Putting " << *(mOp.getVRegValue()) << " into map\n"); - //assert(!defMap.count(mOp.getVRegValue()) && "Def already in the map"); - if(defMap.count(mOp.getVRegValue())) - return false; + //assert if this is the second def we have seen + //DEBUG(std::cerr << "Putting " << *(mOp.getVRegValue()) << " into map\n"); + //assert(!defMap.count(mOp.getVRegValue()) && "Def already in the map"); + if(defMap.count(mOp.getVRegValue())) + return false; - defMap[mOp.getVRegValue()] = &*I; + defMap[mOp.getVRegValue()] = &*I; } //See if we can use this Value* as our defaultInst if(!defaultInst && mOp.getType() == MachineOperand::MO_VirtualRegister) { - Value *V = mOp.getVRegValue(); - if(!isa(V) && !isa(V) && !isa(V) && !isa(V)) - defaultInst = (Instruction*) V; + Value *V = mOp.getVRegValue(); + if(!isa(V) && !isa(V) && !isa(V) && !isa(V)) + defaultInst = (Instruction*) V; } } } @@ -357,7 +357,7 @@ //Check first if its a valid loop for(succ_const_iterator I = succ_begin(BI->getBasicBlock()), - E = succ_end(BI->getBasicBlock()); I != E; ++I) { + E = succ_end(BI->getBasicBlock()); I != E; ++I) { if (*I == BI->getBasicBlock()) // has single block loop isLoop = true; } @@ -437,8 +437,8 @@ if(Instruction *I = dyn_cast(cond)) if(I->getParent() == BB) { if (!assocIndVar(I, indVar, stack, BB)) { - ++InvalidLoops; - return false; + ++InvalidLoops; + return false; } } else { @@ -455,8 +455,8 @@ //Dump out instructions associate with indvar for debug reasons DEBUG(for(std::set::iterator N = indVar.begin(), NE = indVar.end(); N != NE; ++N) { - std::cerr << **N << "\n"; - }); + std::cerr << **N << "\n"; + }); //Create map of machine instr to llvm instr std::map mllvm; @@ -480,9 +480,9 @@ for (unsigned j = 0; j < tempMvec.size(); j++) { MachineOpCode OC = (tempMvec[j])->getOpcode(); if(TMI->isNop(OC)) - continue; + continue; if(!indexMap.count(tempMvec[j])) - continue; + continue; mIndVar[(MachineInstr*) tempMvec[j]] = indexMap[(MachineInstr*) tempMvec[j]]; DEBUG(std::cerr << *(tempMvec[j]) << " at index " << indexMap[(MachineInstr*) tempMvec[j]] << "\n"); } @@ -499,7 +499,7 @@ } bool ModuloSchedulingPass::assocIndVar(Instruction *I, std::set &indVar, - std::vector &stack, BasicBlock *BB) { + std::vector &stack, BasicBlock *BB) { stack.push_back(I); @@ -510,21 +510,21 @@ if (Inc->getOpcode() == Instruction::Add && Inc->getOperand(0) == PN) if (ConstantInt *CI = dyn_cast(Inc->getOperand(1))) if (CI->equalsInt(1)) { - //We have found the indvar, so add the stack, and inc instruction to the set - indVar.insert(stack.begin(), stack.end()); - indVar.insert(Inc); - stack.pop_back(); - return true; - } + //We have found the indvar, so add the stack, and inc instruction to the set + indVar.insert(stack.begin(), stack.end()); + indVar.insert(Inc); + stack.pop_back(); + return true; + } return false; } else { //Loop over each of the instructions operands, check if they are an instruction and in this BB for(unsigned i = 0; i < I->getNumOperands(); ++i) { if(Instruction *N = dyn_cast(I->getOperand(i))) { - if(N->getParent() == BB) - if(!assocIndVar(N, indVar, stack, BB)) - return false; + if(N->getParent() == BB) + if(!assocIndVar(N, indVar, stack, BB)) + return false; } } } @@ -558,12 +558,12 @@ //Loop over resources in each cycle and increments their usage count for(unsigned i=0; i < resources.size(); ++i) for(unsigned j=0; j < resources[i].size(); ++j) { - if(!resourceUsageCount.count(resources[i][j])) { - resourceUsageCount[resources[i][j]] = 1; - } - else { - resourceUsageCount[resources[i][j]] = resourceUsageCount[resources[i][j]] + 1; - } + if(!resourceUsageCount.count(resources[i][j])) { + resourceUsageCount[resources[i][j]] = 1; + } + else { + resourceUsageCount[resources[i][j]] = resourceUsageCount[resources[i][j]] + 1; + } } } @@ -638,7 +638,7 @@ //Assert if its already in the map assert(nodeToAttributesMap.count(I->second) == 0 && - "Node attributes are already in the map"); + "Node attributes are already in the map"); //Put into the map with default attribute values nodeToAttributesMap[I->second] = MSNodeAttributes(); @@ -724,7 +724,7 @@ int ModuloSchedulingPass::calculateALAP(MSchedGraphNode *node, int MII, - int maxASAP, MSchedGraphNode *srcNode) { + int maxASAP, MSchedGraphNode *srcNode) { DEBUG(std::cerr << "Calculating ALAP for " << *node << "\n"); @@ -745,28 +745,28 @@ //Iterate over all of the predecessors and fine max for(MSchedGraphNode::succ_iterator P = node->succ_begin(), - E = node->succ_end(); P != E; ++P) { + E = node->succ_end(); P != E; ++P) { //Only process if we are not ignoring the edge if(!ignoreEdge(node, *P)) { - processedOneEdge = true; - int succALAP = -1; - succALAP = calculateALAP(*P, MII, maxASAP, node); - - assert(succALAP != -1 && "Successors ALAP should have been caclulated"); - - int iteDiff = P.getEdge().getIteDiff(); - - int currentSuccValue = succALAP - node->getLatency() + iteDiff * MII; - - DEBUG(std::cerr << "succ ALAP: " << succALAP << ", iteDiff: " << iteDiff << ", SuccLatency: " << (*P)->getLatency() << ", Current ALAP succ: " << currentSuccValue << "\n"); + processedOneEdge = true; + int succALAP = -1; + succALAP = calculateALAP(*P, MII, maxASAP, node); + + assert(succALAP != -1 && "Successors ALAP should have been caclulated"); + + int iteDiff = P.getEdge().getIteDiff(); + + int currentSuccValue = succALAP - node->getLatency() + iteDiff * MII; + + DEBUG(std::cerr << "succ ALAP: " << succALAP << ", iteDiff: " << iteDiff << ", SuccLatency: " << (*P)->getLatency() << ", Current ALAP succ: " << currentSuccValue << "\n"); - minSuccValue = std::min(minSuccValue, currentSuccValue); + minSuccValue = std::min(minSuccValue, currentSuccValue); } } if(processedOneEdge) - attributes.ALAP = minSuccValue; + attributes.ALAP = minSuccValue; else attributes.ALAP = maxASAP; @@ -786,7 +786,7 @@ int maxASAP = 0; for(std::map::iterator I = nodeToAttributesMap.begin(), - E = nodeToAttributesMap.end(); I != E; ++I) + E = nodeToAttributesMap.end(); I != E; ++I) maxASAP = std::max(maxASAP, I->second.ASAP); return maxASAP; } @@ -803,7 +803,7 @@ //Iterate over all of the predecessors and find max for(MSchedGraphNode::succ_iterator P = node->succ_begin(), - E = node->succ_end(); P != E; ++P) { + E = node->succ_end(); P != E; ++P) { if(!ignoreEdge(node, *P)) { @@ -822,7 +822,7 @@ int ModuloSchedulingPass::calculateDepth(MSchedGraphNode *node, - MSchedGraphNode *destNode) { + MSchedGraphNode *destNode) { MSNodeAttributes &attributes = nodeToAttributesMap.find(node)->second; @@ -865,16 +865,16 @@ if(R->second.size() == recurrence.size()) { for(std::vector::const_iterator node = R->second.begin(), end = R->second.end(); node != end; ++node) { - if(std::find(recurrence.begin(), recurrence.end(), *node) == recurrence.end()) { - all_same = all_same && false; - break; - } - else - all_same = all_same && true; + if(std::find(recurrence.begin(), recurrence.end(), *node) == recurrence.end()) { + all_same = all_same && false; + break; + } + else + all_same = all_same && true; } if(all_same) { - same = true; - break; + same = true; + break; } } } @@ -888,12 +888,12 @@ //DEBUG(std::cerr << "NOT A BACKEDGE\n"); //find actual backedge HACK HACK for(unsigned i=0; i< recurrence.size()-1; ++i) { - if(recurrence[i+1]->getInEdge(recurrence[i]).getIteDiff() == 1) { - srcBENode = recurrence[i]; - destBENode = recurrence[i+1]; - break; - } - + if(recurrence[i+1]->getInEdge(recurrence[i]).getIteDiff() == 1) { + srcBENode = recurrence[i]; + destBENode = recurrence[i+1]; + break; + } + } } @@ -907,7 +907,7 @@ int CircCount; void ModuloSchedulingPass::unblock(MSchedGraphNode *u, std::set &blocked, - std::map > &B) { + std::map > &B) { //Unblock u DEBUG(std::cerr << "Unblocking: " << *u << "\n"); @@ -926,9 +926,9 @@ } bool ModuloSchedulingPass::circuit(MSchedGraphNode *v, std::vector &stack, - std::set &blocked, std::vector &SCC, - MSchedGraphNode *s, std::map > &B, - int II, std::map &newNodes) { + std::set &blocked, std::vector &SCC, + MSchedGraphNode *s, std::map > &B, + int II, std::map &newNodes) { bool f = false; DEBUG(std::cerr << "Finding Circuits Starting with: ( " << v << ")"<< *v << "\n"); @@ -955,7 +955,7 @@ } else if(!blocked.count(*I)) { if(circuit(*I, stack, blocked, SCC, s, B, II, newNodes)) - f = true; + f = true; } else DEBUG(std::cerr << "Blocked: " << **I << "\n"); @@ -982,7 +982,7 @@ std::vector recc; //Dump recurrence for now DEBUG(std::cerr << "Starting Recc\n"); - + int totalDelay = 0; int totalDistance = 0; MSchedGraphNode *lastN = 0; @@ -998,8 +998,8 @@ totalDistance += iteDiff; if(iteDiff > 0) { - start = lastN; - end = *N; + start = lastN; + end = *N; } } //Get the original node @@ -1015,7 +1015,7 @@ DEBUG(std::cerr << "End Recc\n"); CircCount++; - if(start && end) { + if(start && end) { //Insert reccurrence into the list DEBUG(std::cerr << "Ignore Edge from!!: " << *start << " to " << *end << "\n"); edgesToIgnore.insert(std::make_pair(newNodes[start], (newNodes[end])->getInEdgeNum(newNodes[start]))); @@ -1031,7 +1031,7 @@ int value = totalDelay-(RecMII * totalDistance); int lastII = II; while(value < 0) { - + lastII = RecMII; RecMII--; value = totalDelay-(RecMII * totalDistance); @@ -1057,13 +1057,13 @@ for(unsigned i = 0; i < (*N)->succ_size(); ++i) { MSchedGraphEdge *edge = (*N)->getSuccessor(i); if(find(SCC.begin(), SCC.end(), edge->getDest()) != SCC.end()) { - totalDistance += edge->getIteDiff(); - if(edge->getIteDiff() > 0) - if(!start && !end) { - start = *N; - end = edge->getDest(); - } - + totalDistance += edge->getIteDiff(); + if(edge->getIteDiff() > 0) + if(!start && !end) { + start = *N; + end = edge->getDest(); + } + } } @@ -1079,7 +1079,7 @@ assert( (start && end) && "Must have start and end node to ignore edge for SCC"); - if(start && end) { + if(start && end) { //Insert reccurrence into the list DEBUG(std::cerr << "Ignore Edge from!!: " << *start << " to " << *end << "\n"); edgesToIgnore.insert(std::make_pair(newNodes[start], (newNodes[end])->getInEdgeNum(newNodes[start]))); @@ -1135,76 +1135,76 @@ //Find scc with the least vertex for (MSchedGraph::iterator GI = MSG->begin(), E = MSG->end(); GI != E; ++GI) if (Visited.insert(GI->second).second) { - for (scc_iterator SCCI = scc_begin(GI->second), - E = scc_end(GI->second); SCCI != E; ++SCCI) { - std::vector &nextSCC = *SCCI; - - if (Visited.insert(nextSCC[0]).second) { - Visited.insert(nextSCC.begin()+1, nextSCC.end()); - - if(nextSCC.size() > 1) { - std::cerr << "SCC size: " << nextSCC.size() << "\n"; - - for(unsigned i = 0; i < nextSCC.size(); ++i) { - //Loop over successor and see if in scc, then count edge - MSchedGraphNode *node = nextSCC[i]; - for(MSchedGraphNode::succ_iterator S = node->succ_begin(), SE = node->succ_end(); S != SE; ++S) { - if(find(nextSCC.begin(), nextSCC.end(), *S) != nextSCC.end()) - numEdges++; - } - } - std::cerr << "Num Edges: " << numEdges << "\n"; - } - - //Ignore self loops - if(nextSCC.size() > 1) { - - //Get least vertex in Vk - if(!s) { - s = nextSCC[0]; - Vk = nextSCC; - } - - for(unsigned i = 0; i < nextSCC.size(); ++i) { - if(nextSCC[i] < s) { - s = nextSCC[i]; - Vk = nextSCC; - } - } - } - } - } + for (scc_iterator SCCI = scc_begin(GI->second), + E = scc_end(GI->second); SCCI != E; ++SCCI) { + std::vector &nextSCC = *SCCI; + + if (Visited.insert(nextSCC[0]).second) { + Visited.insert(nextSCC.begin()+1, nextSCC.end()); + + if(nextSCC.size() > 1) { + std::cerr << "SCC size: " << nextSCC.size() << "\n"; + + for(unsigned i = 0; i < nextSCC.size(); ++i) { + //Loop over successor and see if in scc, then count edge + MSchedGraphNode *node = nextSCC[i]; + for(MSchedGraphNode::succ_iterator S = node->succ_begin(), SE = node->succ_end(); S != SE; ++S) { + if(find(nextSCC.begin(), nextSCC.end(), *S) != nextSCC.end()) + numEdges++; + } + } + std::cerr << "Num Edges: " << numEdges << "\n"; + } + + //Ignore self loops + if(nextSCC.size() > 1) { + + //Get least vertex in Vk + if(!s) { + s = nextSCC[0]; + Vk = nextSCC; + } + + for(unsigned i = 0; i < nextSCC.size(); ++i) { + if(nextSCC[i] < s) { + s = nextSCC[i]; + Vk = nextSCC; + } + } + } + } + } } //Process SCC DEBUG(for(std::vector::iterator N = Vk.begin(), NE = Vk.end(); - N != NE; ++N) { std::cerr << *((*N)->getInst()); }); + N != NE; ++N) { std::cerr << *((*N)->getInst()); }); //Iterate over all nodes in this scc for(std::vector::iterator N = Vk.begin(), NE = Vk.end(); - N != NE; ++N) { + N != NE; ++N) { blocked.erase(*N); B[*N].clear(); } if(Vk.size() > 1) { if(numEdges < 98) - circuit(s, stack, blocked, Vk, s, B, II, newNodes); + circuit(s, stack, blocked, Vk, s, B, II, newNodes); else - addSCC(Vk, newNodes); + addSCC(Vk, newNodes); //Delete nodes from the graph //Find all nodes up to s and delete them std::vector nodesToRemove; nodesToRemove.push_back(s); for(MSchedGraph::iterator N = MSG->begin(), NE = MSG->end(); N != NE; ++N) { - if(N->second < s ) - nodesToRemove.push_back(N->second); + if(N->second < s ) + nodesToRemove.push_back(N->second); } for(std::vector::iterator N = nodesToRemove.begin(), NE = nodesToRemove.end(); N != NE; ++N) { - DEBUG(std::cerr << "Deleting Node: " << **N << "\n"); - MSG->deleteNode(*N); + DEBUG(std::cerr << "Deleting Node: " << **N << "\n"); + MSG->deleteNode(*N); } } else @@ -1215,8 +1215,8 @@ void ModuloSchedulingPass::findAllReccurrences(MSchedGraphNode *node, - std::vector &visitedNodes, - int II) { + std::vector &visitedNodes, + int II) { if(std::find(visitedNodes.begin(), visitedNodes.end(), node) != visitedNodes.end()) { @@ -1232,22 +1232,22 @@ for(std::vector::iterator I = visitedNodes.begin(), E = visitedNodes.end(); - I !=E; ++I) { + I !=E; ++I) { if(*I == node) - first = false; + first = false; if(first) - continue; + continue; delay = delay + (*I)->getLatency(); if(*I != node) { - int diff = (*I)->getInEdge(last).getIteDiff(); - distance += diff; - if(diff > 0) { - srcBackEdge = last; - destBackEdge = *I; - } + int diff = (*I)->getInEdge(last).getIteDiff(); + distance += diff; + if(diff > 0) { + srcBackEdge = last; + destBackEdge = *I; + } } recurrence.push_back(*I); @@ -1289,9 +1289,9 @@ } void ModuloSchedulingPass::searchPath(MSchedGraphNode *node, - std::vector &path, - std::set &nodesToAdd, - std::set &new_reccurrence) { + std::vector &path, + std::set &nodesToAdd, + std::set &new_reccurrence) { //Push node onto the path path.push_back(node); @@ -1314,11 +1314,11 @@ //final vector bool found = false; for(std::vector >::iterator PO = partialOrder.begin(), - PE = partialOrder.end(); PO != PE; ++PO) { + PE = partialOrder.end(); PO != PE; ++PO) { if(PO->count(*S)) { - found = true; - break; + found = true; + break; } } @@ -1333,9 +1333,9 @@ } void ModuloSchedulingPass::pathToRecc(MSchedGraphNode *node, - std::vector &path, - std::set &poSet, - std::set &lastNodes) { + std::vector &path, + std::set &poSet, + std::set &lastNodes) { //Push node onto the path path.push_back(node); @@ -1354,11 +1354,11 @@ DEBUG(std::cerr << "Found path to recc from no pred\n"); //Loop over path, if it exists in lastNodes, then add to poset, and remove from lastNodes for(std::vector::iterator I = path.begin(), IE = path.end(); I != IE; ++I) { - if(lastNodes.count(*I)) { - DEBUG(std::cerr << "Inserting node into recc: " << **I << "\n"); - poSet.insert(*I); - lastNodes.erase(*I); - } + if(lastNodes.count(*I)) { + DEBUG(std::cerr << "Inserting node into recc: " << **I << "\n"); + poSet.insert(*I); + lastNodes.erase(*I); + } } } else @@ -1387,28 +1387,28 @@ //along with any nodes that connect this recurrence to recurrences //already in the partial order for(std::set > >::reverse_iterator - I = recurrenceList.rbegin(), E=recurrenceList.rend(); I !=E; ++I) { + I = recurrenceList.rbegin(), E=recurrenceList.rend(); I !=E; ++I) { std::set new_recurrence; //Loop through recurrence and remove any nodes already in the partial order for(std::vector::const_iterator N = I->second.begin(), - NE = I->second.end(); N != NE; ++N) { + NE = I->second.end(); N != NE; ++N) { bool found = false; for(std::vector >::iterator PO = partialOrder.begin(), - PE = partialOrder.end(); PO != PE; ++PO) { - if(PO->count(*N)) - found = true; + PE = partialOrder.end(); PO != PE; ++PO) { + if(PO->count(*N)) + found = true; } //Check if its a branch, and remove to handle special if(!found) { - if((*N)->isBranch() && !(*N)->hasPredecessors()) { - branches.push_back(*N); - } - else - new_recurrence.insert(*N); + if((*N)->isBranch() && !(*N)->hasPredecessors()) { + branches.push_back(*N); + } + else + new_recurrence.insert(*N); } } @@ -1426,21 +1426,21 @@ //Add nodes that connect this recurrence to recurrences in the partial path for(std::set::iterator N = new_recurrence.begin(), NE = new_recurrence.end(); N != NE; ++N) - searchPath(*N, path, nodesToAdd, new_recurrence); + searchPath(*N, path, nodesToAdd, new_recurrence); //Add nodes to this recurrence if they are not already in the partial order for(std::set::iterator N = nodesToAdd.begin(), NE = nodesToAdd.end(); - N != NE; ++N) { - bool found = false; - for(std::vector >::iterator PO = partialOrder.begin(), - PE = partialOrder.end(); PO != PE; ++PO) { - if(PO->count(*N)) - found = true; - } - if(!found) { - assert("FOUND CONNECTOR"); - new_recurrence.insert(*N); - } + N != NE; ++N) { + bool found = false; + for(std::vector >::iterator PO = partialOrder.begin(), + PE = partialOrder.end(); PO != PE; ++PO) { + if(PO->count(*N)) + found = true; + } + if(!found) { + assert("FOUND CONNECTOR"); + new_recurrence.insert(*N); + } } partialOrder.push_back(new_recurrence); @@ -1448,11 +1448,11 @@ //Dump out partial order DEBUG(for(std::vector >::iterator I = partialOrder.begin(), - E = partialOrder.end(); I !=E; ++I) { - std::cerr << "Start set in PO\n"; - for(std::set::iterator J = I->begin(), JE = I->end(); J != JE; ++J) - std::cerr << "PO:" << **J << "\n"; - }); + E = partialOrder.end(); I !=E; ++I) { + std::cerr << "Start set in PO\n"; + for(std::set::iterator J = I->begin(), JE = I->end(); J != JE; ++J) + std::cerr << "PO:" << **J << "\n"; + }); } } @@ -1462,15 +1462,15 @@ std::set lastNodes; std::set noPredNodes; for(std::map::iterator I = nodeToAttributesMap.begin(), - E = nodeToAttributesMap.end(); I != E; ++I) { + E = nodeToAttributesMap.end(); I != E; ++I) { bool found = false; //Check if its already in our partial order, if not add it to the final vector for(std::vector >::iterator PO = partialOrder.begin(), - PE = partialOrder.end(); PO != PE; ++PO) { + PE = partialOrder.end(); PO != PE; ++PO) { if(PO->count(I->first)) - found = true; + found = true; } if(!found) lastNodes.insert(I->first); @@ -1482,7 +1482,7 @@ N != NE; ++N) { DEBUG(std::cerr << "No Pred Path from: " << **N << "\n"); for(std::vector >::iterator PO = partialOrder.begin(), - PE = partialOrder.end(); PO != PE; ++PO) { + PE = partialOrder.end(); PO != PE; ++PO) { std::vector path; pathToRecc(*N, path, *PO, lastNodes); } @@ -1495,7 +1495,7 @@ std::set ccSet; connectedComponentSet(*(lastNodes.begin()),ccSet, lastNodes); if(ccSet.size() > 0) - partialOrder.push_back(ccSet); + partialOrder.push_back(ccSet); } @@ -1525,15 +1525,15 @@ for(unsigned j=0; j < FinalNodeOrder.size(); ++j) { for(MSchedGraphNode::pred_iterator P = FinalNodeOrder[j]->pred_begin(), - E = FinalNodeOrder[j]->pred_end(); P != E; ++P) { + E = FinalNodeOrder[j]->pred_end(); P != E; ++P) { //Check if we are supposed to ignore this edge or not if(ignoreEdge(*P,FinalNodeOrder[j])) - continue; - + continue; + if(CurrentSet.count(*P)) - if(std::find(FinalNodeOrder.begin(), FinalNodeOrder.end(), *P) == FinalNodeOrder.end()) - IntersectResult.insert(*P); + if(std::find(FinalNodeOrder.begin(), FinalNodeOrder.end(), *P) == FinalNodeOrder.end()) + IntersectResult.insert(*P); } } } @@ -1546,15 +1546,15 @@ for(unsigned j=0; j < FinalNodeOrder.size(); ++j) { for(MSchedGraphNode::succ_iterator P = FinalNodeOrder[j]->succ_begin(), - E = FinalNodeOrder[j]->succ_end(); P != E; ++P) { + E = FinalNodeOrder[j]->succ_end(); P != E; ++P) { //Check if we are supposed to ignore this edge or not if(ignoreEdge(FinalNodeOrder[j],*P)) - continue; + continue; if(CurrentSet.count(*P)) - if(std::find(FinalNodeOrder.begin(), FinalNodeOrder.end(), *P) == FinalNodeOrder.end()) - IntersectResult.insert(*P); + if(std::find(FinalNodeOrder.begin(), FinalNodeOrder.end(), *P) == FinalNodeOrder.end()) + IntersectResult.insert(*P); } } } @@ -1604,28 +1604,28 @@ //sort top-down if(IntersectCurrent.size() != 0) { - DEBUG(std::cerr << "Final Node Order Successors and Current Set interesection is NOT empty\n"); - order = TOP_DOWN; + DEBUG(std::cerr << "Final Node Order Successors and Current Set interesection is NOT empty\n"); + order = TOP_DOWN; } else { - DEBUG(std::cerr << "Final Node Order Successors and Current Set interesection is empty\n"); - //Find node with max ASAP in current Set - MSchedGraphNode *node; - int maxASAP = 0; - DEBUG(std::cerr << "Using current set of size " << CurrentSet->size() << "to find max ASAP\n"); - for(std::set::iterator J = CurrentSet->begin(), JE = CurrentSet->end(); J != JE; ++J) { - //Get node attributes - MSNodeAttributes nodeAttr= nodeToAttributesMap.find(*J)->second; - //assert(nodeAttr != nodeToAttributesMap.end() && "Node not in attributes map!"); - - if(maxASAP <= nodeAttr.ASAP) { - maxASAP = nodeAttr.ASAP; - node = *J; - } - } - assert(node != 0 && "In node ordering node should not be null"); - IntersectCurrent.insert(node); - order = BOTTOM_UP; + DEBUG(std::cerr << "Final Node Order Successors and Current Set interesection is empty\n"); + //Find node with max ASAP in current Set + MSchedGraphNode *node; + int maxASAP = 0; + DEBUG(std::cerr << "Using current set of size " << CurrentSet->size() << "to find max ASAP\n"); + for(std::set::iterator J = CurrentSet->begin(), JE = CurrentSet->end(); J != JE; ++J) { + //Get node attributes + MSNodeAttributes nodeAttr= nodeToAttributesMap.find(*J)->second; + //assert(nodeAttr != nodeToAttributesMap.end() && "Node not in attributes map!"); + + if(maxASAP <= nodeAttr.ASAP) { + maxASAP = nodeAttr.ASAP; + node = *J; + } + } + assert(node != 0 && "In node ordering node should not be null"); + IntersectCurrent.insert(node); + order = BOTTOM_UP; } } @@ -1633,138 +1633,138 @@ while(IntersectCurrent.size() > 0) { if(order == TOP_DOWN) { - DEBUG(std::cerr << "Order is TOP DOWN\n"); + DEBUG(std::cerr << "Order is TOP DOWN\n"); - while(IntersectCurrent.size() > 0) { - DEBUG(std::cerr << "Intersection is not empty, so find heighest height\n"); - - int MOB = 0; - int height = 0; - MSchedGraphNode *highestHeightNode = *(IntersectCurrent.begin()); - - //Find node in intersection with highest heigh and lowest MOB - for(std::set::iterator I = IntersectCurrent.begin(), - E = IntersectCurrent.end(); I != E; ++I) { - - //Get current nodes properties - MSNodeAttributes nodeAttr= nodeToAttributesMap.find(*I)->second; - - if(height < nodeAttr.height) { - highestHeightNode = *I; - height = nodeAttr.height; - MOB = nodeAttr.MOB; - } - else if(height == nodeAttr.height) { - if(MOB > nodeAttr.height) { - highestHeightNode = *I; - height = nodeAttr.height; - MOB = nodeAttr.MOB; - } - } - } - - //Append our node with greatest height to the NodeOrder - if(std::find(FinalNodeOrder.begin(), FinalNodeOrder.end(), highestHeightNode) == FinalNodeOrder.end()) { - DEBUG(std::cerr << "Adding node to Final Order: " << *highestHeightNode << "\n"); - FinalNodeOrder.push_back(highestHeightNode); - } - - //Remove V from IntersectOrder - IntersectCurrent.erase(std::find(IntersectCurrent.begin(), - IntersectCurrent.end(), highestHeightNode)); - - - //Intersect V's successors with CurrentSet - for(MSchedGraphNode::succ_iterator P = highestHeightNode->succ_begin(), - E = highestHeightNode->succ_end(); P != E; ++P) { - //if(lower_bound(CurrentSet->begin(), - // CurrentSet->end(), *P) != CurrentSet->end()) { - if(std::find(CurrentSet->begin(), CurrentSet->end(), *P) != CurrentSet->end()) { - if(ignoreEdge(highestHeightNode, *P)) - continue; - //If not already in Intersect, add - if(!IntersectCurrent.count(*P)) - IntersectCurrent.insert(*P); - } - } - } //End while loop over Intersect Size - - //Change direction - order = BOTTOM_UP; - - //Reset Intersect to reflect changes in OrderNodes - IntersectCurrent.clear(); - predIntersect(*CurrentSet, IntersectCurrent); - + while(IntersectCurrent.size() > 0) { + DEBUG(std::cerr << "Intersection is not empty, so find heighest height\n"); + + int MOB = 0; + int height = 0; + MSchedGraphNode *highestHeightNode = *(IntersectCurrent.begin()); + + //Find node in intersection with highest heigh and lowest MOB + for(std::set::iterator I = IntersectCurrent.begin(), + E = IntersectCurrent.end(); I != E; ++I) { + + //Get current nodes properties + MSNodeAttributes nodeAttr= nodeToAttributesMap.find(*I)->second; + + if(height < nodeAttr.height) { + highestHeightNode = *I; + height = nodeAttr.height; + MOB = nodeAttr.MOB; + } + else if(height == nodeAttr.height) { + if(MOB > nodeAttr.height) { + highestHeightNode = *I; + height = nodeAttr.height; + MOB = nodeAttr.MOB; + } + } + } + + //Append our node with greatest height to the NodeOrder + if(std::find(FinalNodeOrder.begin(), FinalNodeOrder.end(), highestHeightNode) == FinalNodeOrder.end()) { + DEBUG(std::cerr << "Adding node to Final Order: " << *highestHeightNode << "\n"); + FinalNodeOrder.push_back(highestHeightNode); + } + + //Remove V from IntersectOrder + IntersectCurrent.erase(std::find(IntersectCurrent.begin(), + IntersectCurrent.end(), highestHeightNode)); + + + //Intersect V's successors with CurrentSet + for(MSchedGraphNode::succ_iterator P = highestHeightNode->succ_begin(), + E = highestHeightNode->succ_end(); P != E; ++P) { + //if(lower_bound(CurrentSet->begin(), + // CurrentSet->end(), *P) != CurrentSet->end()) { + if(std::find(CurrentSet->begin(), CurrentSet->end(), *P) != CurrentSet->end()) { + if(ignoreEdge(highestHeightNode, *P)) + continue; + //If not already in Intersect, add + if(!IntersectCurrent.count(*P)) + IntersectCurrent.insert(*P); + } + } + } //End while loop over Intersect Size + + //Change direction + order = BOTTOM_UP; + + //Reset Intersect to reflect changes in OrderNodes + IntersectCurrent.clear(); + predIntersect(*CurrentSet, IntersectCurrent); + } //End If TOP_DOWN - - //Begin if BOTTOM_UP + + //Begin if BOTTOM_UP else { - DEBUG(std::cerr << "Order is BOTTOM UP\n"); - while(IntersectCurrent.size() > 0) { - DEBUG(std::cerr << "Intersection of size " << IntersectCurrent.size() << ", finding highest depth\n"); - - //dump intersection - DEBUG(dumpIntersection(IntersectCurrent)); - //Get node with highest depth, if a tie, use one with lowest - //MOB - int MOB = 0; - int depth = 0; - MSchedGraphNode *highestDepthNode = *(IntersectCurrent.begin()); - - for(std::set::iterator I = IntersectCurrent.begin(), - E = IntersectCurrent.end(); I != E; ++I) { - //Find node attribute in graph - MSNodeAttributes nodeAttr= nodeToAttributesMap.find(*I)->second; - - if(depth < nodeAttr.depth) { - highestDepthNode = *I; - depth = nodeAttr.depth; - MOB = nodeAttr.MOB; - } - else if(depth == nodeAttr.depth) { - if(MOB > nodeAttr.MOB) { - highestDepthNode = *I; - depth = nodeAttr.depth; - MOB = nodeAttr.MOB; - } - } - } - - - - //Append highest depth node to the NodeOrder - if(std::find(FinalNodeOrder.begin(), FinalNodeOrder.end(), highestDepthNode) == FinalNodeOrder.end()) { - DEBUG(std::cerr << "Adding node to Final Order: " << *highestDepthNode << "\n"); - FinalNodeOrder.push_back(highestDepthNode); - } - //Remove heightestDepthNode from IntersectOrder - IntersectCurrent.erase(highestDepthNode); - - - //Intersect heightDepthNode's pred with CurrentSet - for(MSchedGraphNode::pred_iterator P = highestDepthNode->pred_begin(), - E = highestDepthNode->pred_end(); P != E; ++P) { - if(CurrentSet->count(*P)) { - if(ignoreEdge(*P, highestDepthNode)) - continue; - - //If not already in Intersect, add - if(!IntersectCurrent.count(*P)) - IntersectCurrent.insert(*P); - } - } - - } //End while loop over Intersect Size - - //Change order - order = TOP_DOWN; - - //Reset IntersectCurrent to reflect changes in OrderNodes - IntersectCurrent.clear(); - succIntersect(*CurrentSet, IntersectCurrent); - } //End if BOTTOM_DOWN - + DEBUG(std::cerr << "Order is BOTTOM UP\n"); + while(IntersectCurrent.size() > 0) { + DEBUG(std::cerr << "Intersection of size " << IntersectCurrent.size() << ", finding highest depth\n"); + + //dump intersection + DEBUG(dumpIntersection(IntersectCurrent)); + //Get node with highest depth, if a tie, use one with lowest + //MOB + int MOB = 0; + int depth = 0; + MSchedGraphNode *highestDepthNode = *(IntersectCurrent.begin()); + + for(std::set::iterator I = IntersectCurrent.begin(), + E = IntersectCurrent.end(); I != E; ++I) { + //Find node attribute in graph + MSNodeAttributes nodeAttr= nodeToAttributesMap.find(*I)->second; + + if(depth < nodeAttr.depth) { + highestDepthNode = *I; + depth = nodeAttr.depth; + MOB = nodeAttr.MOB; + } + else if(depth == nodeAttr.depth) { + if(MOB > nodeAttr.MOB) { + highestDepthNode = *I; + depth = nodeAttr.depth; + MOB = nodeAttr.MOB; + } + } + } + + + + //Append highest depth node to the NodeOrder + if(std::find(FinalNodeOrder.begin(), FinalNodeOrder.end(), highestDepthNode) == FinalNodeOrder.end()) { + DEBUG(std::cerr << "Adding node to Final Order: " << *highestDepthNode << "\n"); + FinalNodeOrder.push_back(highestDepthNode); + } + //Remove heightestDepthNode from IntersectOrder + IntersectCurrent.erase(highestDepthNode); + + + //Intersect heightDepthNode's pred with CurrentSet + for(MSchedGraphNode::pred_iterator P = highestDepthNode->pred_begin(), + E = highestDepthNode->pred_end(); P != E; ++P) { + if(CurrentSet->count(*P)) { + if(ignoreEdge(*P, highestDepthNode)) + continue; + + //If not already in Intersect, add + if(!IntersectCurrent.count(*P)) + IntersectCurrent.insert(*P); + } + } + + } //End while loop over Intersect Size + + //Change order + order = TOP_DOWN; + + //Reset IntersectCurrent to reflect changes in OrderNodes + IntersectCurrent.clear(); + succIntersect(*CurrentSet, IntersectCurrent); + } //End if BOTTOM_DOWN + DEBUG(std::cerr << "Current Intersection Size: " << IntersectCurrent.size() << "\n"); } //End Wrapping while loop @@ -1802,7 +1802,7 @@ //Loop over the final node order and process each node for(std::vector::iterator I = FinalNodeOrder.begin(), - E = FinalNodeOrder.end(); I != E; ++I) { + E = FinalNodeOrder.end(); I != E; ++I) { //CalculateEarly and Late start bool initialLSVal = false; @@ -1814,85 +1814,85 @@ bool sched; if((*I)->isBranch()) - if((*I)->hasPredecessors()) - sched = true; - else - sched = false; + if((*I)->hasPredecessors()) + sched = true; + else + sched = false; else - sched = true; + sched = true; if(sched) { - //Loop over nodes in the schedule and determine if they are predecessors - //or successors of the node we are trying to schedule - for(MSSchedule::schedule_iterator nodesByCycle = schedule.begin(), nodesByCycleEnd = schedule.end(); - nodesByCycle != nodesByCycleEnd; ++nodesByCycle) { - - //For this cycle, get the vector of nodes schedule and loop over it - for(std::vector::iterator schedNode = nodesByCycle->second.begin(), SNE = nodesByCycle->second.end(); schedNode != SNE; ++schedNode) { - - if((*I)->isPredecessor(*schedNode)) { - int diff = (*I)->getInEdge(*schedNode).getIteDiff(); - int ES_Temp = nodesByCycle->first + (*schedNode)->getLatency() - diff * II; - DEBUG(std::cerr << "Diff: " << diff << " Cycle: " << nodesByCycle->first << "\n"); - DEBUG(std::cerr << "Temp EarlyStart: " << ES_Temp << " Prev EarlyStart: " << EarlyStart << "\n"); - if(initialESVal) - EarlyStart = std::max(EarlyStart, ES_Temp); - else { - EarlyStart = ES_Temp; - initialESVal = true; - } - hasPred = true; - } - if((*I)->isSuccessor(*schedNode)) { - int diff = (*schedNode)->getInEdge(*I).getIteDiff(); - int LS_Temp = nodesByCycle->first - (*I)->getLatency() + diff * II; - DEBUG(std::cerr << "Diff: " << diff << " Cycle: " << nodesByCycle->first << "\n"); - DEBUG(std::cerr << "Temp LateStart: " << LS_Temp << " Prev LateStart: " << LateStart << "\n"); - if(initialLSVal) - LateStart = std::min(LateStart, LS_Temp); - else { - LateStart = LS_Temp; - initialLSVal = true; - } - hasSucc = true; - } - } - } + //Loop over nodes in the schedule and determine if they are predecessors + //or successors of the node we are trying to schedule + for(MSSchedule::schedule_iterator nodesByCycle = schedule.begin(), nodesByCycleEnd = schedule.end(); + nodesByCycle != nodesByCycleEnd; ++nodesByCycle) { + + //For this cycle, get the vector of nodes schedule and loop over it + for(std::vector::iterator schedNode = nodesByCycle->second.begin(), SNE = nodesByCycle->second.end(); schedNode != SNE; ++schedNode) { + + if((*I)->isPredecessor(*schedNode)) { + int diff = (*I)->getInEdge(*schedNode).getIteDiff(); + int ES_Temp = nodesByCycle->first + (*schedNode)->getLatency() - diff * II; + DEBUG(std::cerr << "Diff: " << diff << " Cycle: " << nodesByCycle->first << "\n"); + DEBUG(std::cerr << "Temp EarlyStart: " << ES_Temp << " Prev EarlyStart: " << EarlyStart << "\n"); + if(initialESVal) + EarlyStart = std::max(EarlyStart, ES_Temp); + else { + EarlyStart = ES_Temp; + initialESVal = true; + } + hasPred = true; + } + if((*I)->isSuccessor(*schedNode)) { + int diff = (*schedNode)->getInEdge(*I).getIteDiff(); + int LS_Temp = nodesByCycle->first - (*I)->getLatency() + diff * II; + DEBUG(std::cerr << "Diff: " << diff << " Cycle: " << nodesByCycle->first << "\n"); + DEBUG(std::cerr << "Temp LateStart: " << LS_Temp << " Prev LateStart: " << LateStart << "\n"); + if(initialLSVal) + LateStart = std::min(LateStart, LS_Temp); + else { + LateStart = LS_Temp; + initialLSVal = true; + } + hasSucc = true; + } + } + } } else { - branches.push_back(*I); - continue; + branches.push_back(*I); + continue; } //Check if this node is a pred or succ to a branch, and restrict its placement //even though the branch is not in the schedule /*int count = branches.size(); for(std::vector::iterator B = branches.begin(), BE = branches.end(); - B != BE; ++B) { - if((*I)->isPredecessor(*B)) { - int diff = (*I)->getInEdge(*B).getIteDiff(); - int ES_Temp = (II+count-1) + (*B)->getLatency() - diff * II; - DEBUG(std::cerr << "Diff: " << diff << " Cycle: " << (II+count)-1 << "\n"); - DEBUG(std::cerr << "Temp EarlyStart: " << ES_Temp << " Prev EarlyStart: " << EarlyStart << "\n"); - EarlyStart = std::max(EarlyStart, ES_Temp); - hasPred = true; - } - - if((*I)->isSuccessor(*B)) { - int diff = (*B)->getInEdge(*I).getIteDiff(); - int LS_Temp = (II+count-1) - (*I)->getLatency() + diff * II; - DEBUG(std::cerr << "Diff: " << diff << " Cycle: " << (II+count-1) << "\n"); - DEBUG(std::cerr << "Temp LateStart: " << LS_Temp << " Prev LateStart: " << LateStart << "\n"); - LateStart = std::min(LateStart, LS_Temp); - hasSucc = true; - } - - count--; + B != BE; ++B) { + if((*I)->isPredecessor(*B)) { + int diff = (*I)->getInEdge(*B).getIteDiff(); + int ES_Temp = (II+count-1) + (*B)->getLatency() - diff * II; + DEBUG(std::cerr << "Diff: " << diff << " Cycle: " << (II+count)-1 << "\n"); + DEBUG(std::cerr << "Temp EarlyStart: " << ES_Temp << " Prev EarlyStart: " << EarlyStart << "\n"); + EarlyStart = std::max(EarlyStart, ES_Temp); + hasPred = true; + } + + if((*I)->isSuccessor(*B)) { + int diff = (*B)->getInEdge(*I).getIteDiff(); + int LS_Temp = (II+count-1) - (*I)->getLatency() + diff * II; + DEBUG(std::cerr << "Diff: " << diff << " Cycle: " << (II+count-1) << "\n"); + DEBUG(std::cerr << "Temp LateStart: " << LS_Temp << " Prev LateStart: " << LateStart << "\n"); + LateStart = std::min(LateStart, LS_Temp); + hasSucc = true; + } + + count--; }*/ //Check if the node has no pred or successors and set Early Start to its ASAP if(!hasSucc && !hasPred) - EarlyStart = nodeToAttributesMap.find(*I)->second.ASAP; + EarlyStart = nodeToAttributesMap.find(*I)->second.ASAP; DEBUG(std::cerr << "Has Successors: " << hasSucc << ", Has Pred: " << hasPred << "\n"); DEBUG(std::cerr << "EarlyStart: " << EarlyStart << ", LateStart: " << LateStart << "\n"); @@ -1900,25 +1900,25 @@ //Now, try to schedule this node depending upon its pred and successor in the schedule //already if(!hasSucc && hasPred) - success = scheduleNode(*I, EarlyStart, (EarlyStart + II -1)); + success = scheduleNode(*I, EarlyStart, (EarlyStart + II -1)); else if(!hasPred && hasSucc) - success = scheduleNode(*I, LateStart, (LateStart - II +1)); + success = scheduleNode(*I, LateStart, (LateStart - II +1)); else if(hasPred && hasSucc) { - if(EarlyStart > LateStart) { - success = false; - //LateStart = EarlyStart; - DEBUG(std::cerr << "Early Start can not be later then the late start cycle, schedule fails\n"); - } - else - success = scheduleNode(*I, EarlyStart, std::min(LateStart, (EarlyStart + II -1))); + if(EarlyStart > LateStart) { + success = false; + //LateStart = EarlyStart; + DEBUG(std::cerr << "Early Start can not be later then the late start cycle, schedule fails\n"); + } + else + success = scheduleNode(*I, EarlyStart, std::min(LateStart, (EarlyStart + II -1))); } else - success = scheduleNode(*I, EarlyStart, EarlyStart + II - 1); + success = scheduleNode(*I, EarlyStart, EarlyStart + II - 1); if(!success) { - ++II; - schedule.clear(); - break; + ++II; + schedule.clear(); + break; } } @@ -1928,8 +1928,8 @@ success = schedule.constructKernel(II, branches, indVarInstrs[BB]); DEBUG(std::cerr << "Done Constructing Schedule Kernel\n"); if(!success) { - ++II; - schedule.clear(); + ++II; + schedule.clear(); } DEBUG(std::cerr << "Final II: " << II << "\n"); } @@ -1947,7 +1947,7 @@ bool ModuloSchedulingPass::scheduleNode(MSchedGraphNode *node, - int start, int end) { + int start, int end) { bool success = false; DEBUG(std::cerr << *node << " (Start Cycle: " << start << ", End Cycle: " << end << ")\n"); @@ -1982,13 +1982,13 @@ ++cycle; DEBUG(std::cerr << "Increase cycle: " << cycle << "\n"); if(cycle > end) - return false; + return false; } else { --cycle; DEBUG(std::cerr << "Decrease cycle: " << cycle << "\n"); if(cycle < end) - return false; + return false; } } @@ -2030,79 +2030,79 @@ DEBUG(std::cerr << "i=" << i << "\n"); for(int j = i; j >= 0; --j) { for(MachineBasicBlock::const_iterator MI = origBB->begin(), ME = origBB->end(); ME != MI; ++MI) { - if(inKernel[j].count(&*MI)) { - MachineInstr *instClone = MI->clone(); - machineBB->push_back(instClone); - - //If its a branch, insert a nop - if(mii->isBranch(instClone->getOpcode())) - BuildMI(machineBB, V9::NOP, 0); - - - DEBUG(std::cerr << "Cloning: " << *MI << "\n"); - - //After cloning, we may need to save the value that this instruction defines - for(unsigned opNum=0; opNum < MI->getNumOperands(); ++opNum) { - Instruction *tmp; - - //get machine operand - MachineOperand &mOp = instClone->getOperand(opNum); - if(mOp.getType() == MachineOperand::MO_VirtualRegister && mOp.isDef()) { - - //Check if this is a value we should save - if(valuesToSave.count(mOp.getVRegValue())) { - //Save copy in tmpInstruction - tmp = new TmpInstruction(mOp.getVRegValue()); - - //Add TmpInstruction to safe LLVM Instruction MCFI - MachineCodeForInstruction & tempMvec = MachineCodeForInstruction::get(defaultInst); - tempMvec.addTemp((Value*) tmp); - - DEBUG(std::cerr << "Value: " << *(mOp.getVRegValue()) << " New Value: " << *tmp << " Stage: " << i << "\n"); - - newValues[mOp.getVRegValue()][i]= tmp; - newValLocation[tmp] = machineBB; - - DEBUG(std::cerr << "Machine Instr Operands: " << *(mOp.getVRegValue()) << ", 0, " << *tmp << "\n"); - - //Create machine instruction and put int machineBB - MachineInstr *saveValue; - if(mOp.getVRegValue()->getType() == Type::FloatTy) - saveValue = BuildMI(machineBB, V9::FMOVS, 3).addReg(mOp.getVRegValue()).addRegDef(tmp); - else if(mOp.getVRegValue()->getType() == Type::DoubleTy) - saveValue = BuildMI(machineBB, V9::FMOVD, 3).addReg(mOp.getVRegValue()).addRegDef(tmp); - else - saveValue = BuildMI(machineBB, V9::ORr, 3).addReg(mOp.getVRegValue()).addImm(0).addRegDef(tmp); - - - DEBUG(std::cerr << "Created new machine instr: " << *saveValue << "\n"); - } - } - - //We may also need to update the value that we use if its from an earlier prologue - if(j != 0) { - if(mOp.getType() == MachineOperand::MO_VirtualRegister && mOp.isUse()) { - if(newValues.count(mOp.getVRegValue())) { - if(newValues[mOp.getVRegValue()].count(i-1)) { - Value *oldV = mOp.getVRegValue(); - DEBUG(std::cerr << "Replaced this value: " << mOp.getVRegValue() << " With:" << (newValues[mOp.getVRegValue()][i-1]) << "\n"); - //Update the operand with the right value - mOp.setValueReg(newValues[mOp.getVRegValue()][i-1]); - - //Remove this value since we have consumed it - //NOTE: Should this only be done if j != maxStage? - consumedValues[oldV][i-1] = (newValues[oldV][i-1]); - DEBUG(std::cerr << "Deleted value: " << consumedValues[oldV][i-1] << "\n"); - newValues[oldV].erase(i-1); - } - } - else - if(consumedValues.count(mOp.getVRegValue())) - assert(!consumedValues[mOp.getVRegValue()].count(i-1) && "Found a case where we need the value"); - } - } - } - } + if(inKernel[j].count(&*MI)) { + MachineInstr *instClone = MI->clone(); + machineBB->push_back(instClone); + + //If its a branch, insert a nop + if(mii->isBranch(instClone->getOpcode())) + BuildMI(machineBB, V9::NOP, 0); + + + DEBUG(std::cerr << "Cloning: " << *MI << "\n"); + + //After cloning, we may need to save the value that this instruction defines + for(unsigned opNum=0; opNum < MI->getNumOperands(); ++opNum) { + Instruction *tmp; + + //get machine operand + MachineOperand &mOp = instClone->getOperand(opNum); + if(mOp.getType() == MachineOperand::MO_VirtualRegister && mOp.isDef()) { + + //Check if this is a value we should save + if(valuesToSave.count(mOp.getVRegValue())) { + //Save copy in tmpInstruction + tmp = new TmpInstruction(mOp.getVRegValue()); + + //Add TmpInstruction to safe LLVM Instruction MCFI + MachineCodeForInstruction & tempMvec = MachineCodeForInstruction::get(defaultInst); + tempMvec.addTemp((Value*) tmp); + + DEBUG(std::cerr << "Value: " << *(mOp.getVRegValue()) << " New Value: " << *tmp << " Stage: " << i << "\n"); + + newValues[mOp.getVRegValue()][i]= tmp; + newValLocation[tmp] = machineBB; + + DEBUG(std::cerr << "Machine Instr Operands: " << *(mOp.getVRegValue()) << ", 0, " << *tmp << "\n"); + + //Create machine instruction and put int machineBB + MachineInstr *saveValue; + if(mOp.getVRegValue()->getType() == Type::FloatTy) + saveValue = BuildMI(machineBB, V9::FMOVS, 3).addReg(mOp.getVRegValue()).addRegDef(tmp); + else if(mOp.getVRegValue()->getType() == Type::DoubleTy) + saveValue = BuildMI(machineBB, V9::FMOVD, 3).addReg(mOp.getVRegValue()).addRegDef(tmp); + else + saveValue = BuildMI(machineBB, V9::ORr, 3).addReg(mOp.getVRegValue()).addImm(0).addRegDef(tmp); + + + DEBUG(std::cerr << "Created new machine instr: " << *saveValue << "\n"); + } + } + + //We may also need to update the value that we use if its from an earlier prologue + if(j != 0) { + if(mOp.getType() == MachineOperand::MO_VirtualRegister && mOp.isUse()) { + if(newValues.count(mOp.getVRegValue())) { + if(newValues[mOp.getVRegValue()].count(i-1)) { + Value *oldV = mOp.getVRegValue(); + DEBUG(std::cerr << "Replaced this value: " << mOp.getVRegValue() << " With:" << (newValues[mOp.getVRegValue()][i-1]) << "\n"); + //Update the operand with the right value + mOp.setValueReg(newValues[mOp.getVRegValue()][i-1]); + + //Remove this value since we have consumed it + //NOTE: Should this only be done if j != maxStage? + consumedValues[oldV][i-1] = (newValues[oldV][i-1]); + DEBUG(std::cerr << "Deleted value: " << consumedValues[oldV][i-1] << "\n"); + newValues[oldV].erase(i-1); + } + } + else + if(consumedValues.count(mOp.getVRegValue())) + assert(!consumedValues[mOp.getVRegValue()].count(i-1) && "Found a case where we need the value"); + } + } + } + } } } @@ -2158,53 +2158,53 @@ for(MachineBasicBlock::const_iterator MI = origBB->begin(), ME = origBB->end(); ME != MI; ++MI) { for(int j=schedule.getMaxStage(); j > i; --j) { - if(inKernel[j].count(&*MI)) { - DEBUG(std::cerr << "Cloning instruction " << *MI << "\n"); - MachineInstr *clone = MI->clone(); - - //Update operands that need to use the result from the phi - for(unsigned opNum=0; opNum < clone->getNumOperands(); ++opNum) { - //get machine operand - const MachineOperand &mOp = clone->getOperand(opNum); - - if((mOp.getType() == MachineOperand::MO_VirtualRegister && mOp.isUse())) { - - DEBUG(std::cerr << "Writing PHI for " << (mOp.getVRegValue()) << "\n"); - - //If this is the last instructions for the max iterations ago, don't update operands - if(inEpilogue.count(mOp.getVRegValue())) - if(inEpilogue[mOp.getVRegValue()] == i) - continue; - - //Quickly write appropriate phis for this operand - if(newValues.count(mOp.getVRegValue())) { - if(newValues[mOp.getVRegValue()].count(i)) { - Instruction *tmp = new TmpInstruction(newValues[mOp.getVRegValue()][i]); - - //Get machine code for this instruction - MachineCodeForInstruction & tempMvec = MachineCodeForInstruction::get(defaultInst); - tempMvec.addTemp((Value*) tmp); - - //assert of no kernelPHI for this value - assert(kernelPHIs[mOp.getVRegValue()][i] !=0 && "Must have final kernel phi to construct epilogue phi"); - - MachineInstr *saveValue = BuildMI(machineBB, V9::PHI, 3).addReg(newValues[mOp.getVRegValue()][i]).addReg(kernelPHIs[mOp.getVRegValue()][i]).addRegDef(tmp); - DEBUG(std::cerr << "Resulting PHI: " << *saveValue << "\n"); - valPHIs[mOp.getVRegValue()] = tmp; - } - } - - if(valPHIs.count(mOp.getVRegValue())) { - //Update the operand in the cloned instruction - clone->getOperand(opNum).setValueReg(valPHIs[mOp.getVRegValue()]); - } - } - else if((mOp.getType() == MachineOperand::MO_VirtualRegister && mOp.isDef())) { - inEpilogue[mOp.getVRegValue()] = i; - } - } - machineBB->push_back(clone); - } + if(inKernel[j].count(&*MI)) { + DEBUG(std::cerr << "Cloning instruction " << *MI << "\n"); + MachineInstr *clone = MI->clone(); + + //Update operands that need to use the result from the phi + for(unsigned opNum=0; opNum < clone->getNumOperands(); ++opNum) { + //get machine operand + const MachineOperand &mOp = clone->getOperand(opNum); + + if((mOp.getType() == MachineOperand::MO_VirtualRegister && mOp.isUse())) { + + DEBUG(std::cerr << "Writing PHI for " << (mOp.getVRegValue()) << "\n"); + + //If this is the last instructions for the max iterations ago, don't update operands + if(inEpilogue.count(mOp.getVRegValue())) + if(inEpilogue[mOp.getVRegValue()] == i) + continue; + + //Quickly write appropriate phis for this operand + if(newValues.count(mOp.getVRegValue())) { + if(newValues[mOp.getVRegValue()].count(i)) { + Instruction *tmp = new TmpInstruction(newValues[mOp.getVRegValue()][i]); + + //Get machine code for this instruction + MachineCodeForInstruction & tempMvec = MachineCodeForInstruction::get(defaultInst); + tempMvec.addTemp((Value*) tmp); + + //assert of no kernelPHI for this value + assert(kernelPHIs[mOp.getVRegValue()][i] !=0 && "Must have final kernel phi to construct epilogue phi"); + + MachineInstr *saveValue = BuildMI(machineBB, V9::PHI, 3).addReg(newValues[mOp.getVRegValue()][i]).addReg(kernelPHIs[mOp.getVRegValue()][i]).addRegDef(tmp); + DEBUG(std::cerr << "Resulting PHI: " << *saveValue << "\n"); + valPHIs[mOp.getVRegValue()] = tmp; + } + } + + if(valPHIs.count(mOp.getVRegValue())) { + //Update the operand in the cloned instruction + clone->getOperand(opNum).setValueReg(valPHIs[mOp.getVRegValue()]); + } + } + else if((mOp.getType() == MachineOperand::MO_VirtualRegister && mOp.isDef())) { + inEpilogue[mOp.getVRegValue()] = i; + } + } + machineBB->push_back(clone); + } } } @@ -2259,64 +2259,64 @@ if(I->second != 0) { if(mOp.getType() == MachineOperand::MO_VirtualRegister && mOp.isUse()) { - //Check to see where this operand is defined if this instruction is from max stage - if(I->second == schedule.getMaxStage()) { - DEBUG(std::cerr << "VREG: " << *(mOp.getVRegValue()) << "\n"); - } - - //If its in the value saved, we need to create a temp instruction and use that instead - if(valuesToSave.count(mOp.getVRegValue())) { - - //Check if we already have a final PHI value for this - if(!finalPHIValue.count(mOp.getVRegValue())) { - //Only create phi if the operand def is from a stage before this one - if(schedule.defPreviousStage(mOp.getVRegValue(), I->second)) { - TmpInstruction *tmp = new TmpInstruction(mOp.getVRegValue()); - - //Get machine code for this instruction - MachineCodeForInstruction & tempMvec = MachineCodeForInstruction::get(defaultInst); - tempMvec.addTemp((Value*) tmp); - - //Update the operand in the cloned instruction - instClone->getOperand(i).setValueReg(tmp); - - //save this as our final phi - finalPHIValue[mOp.getVRegValue()] = tmp; - newValLocation[tmp] = machineBB; - } - } - else { - //Use the previous final phi value - instClone->getOperand(i).setValueReg(finalPHIValue[mOp.getVRegValue()]); - } - } + //Check to see where this operand is defined if this instruction is from max stage + if(I->second == schedule.getMaxStage()) { + DEBUG(std::cerr << "VREG: " << *(mOp.getVRegValue()) << "\n"); + } + + //If its in the value saved, we need to create a temp instruction and use that instead + if(valuesToSave.count(mOp.getVRegValue())) { + + //Check if we already have a final PHI value for this + if(!finalPHIValue.count(mOp.getVRegValue())) { + //Only create phi if the operand def is from a stage before this one + if(schedule.defPreviousStage(mOp.getVRegValue(), I->second)) { + TmpInstruction *tmp = new TmpInstruction(mOp.getVRegValue()); + + //Get machine code for this instruction + MachineCodeForInstruction & tempMvec = MachineCodeForInstruction::get(defaultInst); + tempMvec.addTemp((Value*) tmp); + + //Update the operand in the cloned instruction + instClone->getOperand(i).setValueReg(tmp); + + //save this as our final phi + finalPHIValue[mOp.getVRegValue()] = tmp; + newValLocation[tmp] = machineBB; + } + } + else { + //Use the previous final phi value + instClone->getOperand(i).setValueReg(finalPHIValue[mOp.getVRegValue()]); + } + } } } if(I->second != schedule.getMaxStage()) { if(mOp.getType() == MachineOperand::MO_VirtualRegister && mOp.isDef()) { - if(valuesToSave.count(mOp.getVRegValue())) { - - TmpInstruction *tmp = new TmpInstruction(mOp.getVRegValue()); - - //Get machine code for this instruction - MachineCodeForInstruction & tempVec = MachineCodeForInstruction::get(defaultInst); - tempVec.addTemp((Value*) tmp); - - //Create new machine instr and put in MBB - MachineInstr *saveValue; - if(mOp.getVRegValue()->getType() == Type::FloatTy) - saveValue = BuildMI(machineBB, V9::FMOVS, 3).addReg(mOp.getVRegValue()).addRegDef(tmp); - else if(mOp.getVRegValue()->getType() == Type::DoubleTy) - saveValue = BuildMI(machineBB, V9::FMOVD, 3).addReg(mOp.getVRegValue()).addRegDef(tmp); - else - saveValue = BuildMI(machineBB, V9::ORr, 3).addReg(mOp.getVRegValue()).addImm(0).addRegDef(tmp); - - - //Save for future cleanup - kernelValue[mOp.getVRegValue()] = tmp; - newValLocation[tmp] = machineBB; - kernelPHIs[mOp.getVRegValue()][schedule.getMaxStage()-1] = tmp; - } + if(valuesToSave.count(mOp.getVRegValue())) { + + TmpInstruction *tmp = new TmpInstruction(mOp.getVRegValue()); + + //Get machine code for this instruction + MachineCodeForInstruction & tempVec = MachineCodeForInstruction::get(defaultInst); + tempVec.addTemp((Value*) tmp); + + //Create new machine instr and put in MBB + MachineInstr *saveValue; + if(mOp.getVRegValue()->getType() == Type::FloatTy) + saveValue = BuildMI(machineBB, V9::FMOVS, 3).addReg(mOp.getVRegValue()).addRegDef(tmp); + else if(mOp.getVRegValue()->getType() == Type::DoubleTy) + saveValue = BuildMI(machineBB, V9::FMOVD, 3).addReg(mOp.getVRegValue()).addRegDef(tmp); + else + saveValue = BuildMI(machineBB, V9::ORr, 3).addReg(mOp.getVRegValue()).addImm(0).addRegDef(tmp); + + + //Save for future cleanup + kernelValue[mOp.getVRegValue()] = tmp; + newValLocation[tmp] = machineBB; + kernelPHIs[mOp.getVRegValue()][schedule.getMaxStage()-1] = tmp; + } } } } @@ -2342,7 +2342,7 @@ DEBUG(std::cerr << "Writing phi for" << *(V->first)); DEBUG(std::cerr << "\nMap of Value* for this phi\n"); DEBUG(for(std::map::iterator I = V->second.begin(), - IE = V->second.end(); I != IE; ++I) { + IE = V->second.end(); I != IE; ++I) { std::cerr << "Stage: " << I->first; std::cerr << " Value: " << *(I->second) << "\n"; }); @@ -2363,42 +2363,42 @@ unsigned count = 1; //Loop over the the map backwards to generate phis for(std::map::reverse_iterator I = V->second.rbegin(), IE = V->second.rend(); - I != IE; ++I) { + I != IE; ++I) { if(count < (V->second).size()) { - if(lastPhi == 0) { - lastPhi = new TmpInstruction(I->second); + if(lastPhi == 0) { + lastPhi = new TmpInstruction(I->second); - //Get machine code for this instruction - MachineCodeForInstruction & tempMvec = MachineCodeForInstruction::get(defaultInst); - tempMvec.addTemp((Value*) lastPhi); - - MachineInstr *saveValue = BuildMI(*machineBB, machineBB->begin(), V9::PHI, 3).addReg(kernelValue[V->first]).addReg(I->second).addRegDef(lastPhi); - DEBUG(std::cerr << "Resulting PHI: " << *saveValue << "\n"); - newValLocation[lastPhi] = machineBB; - } - else { - Instruction *tmp = new TmpInstruction(I->second); - - //Get machine code for this instruction - MachineCodeForInstruction & tempMvec = MachineCodeForInstruction::get(defaultInst); - tempMvec.addTemp((Value*) tmp); - - - MachineInstr *saveValue = BuildMI(*machineBB, machineBB->begin(), V9::PHI, 3).addReg(lastPhi).addReg(I->second).addRegDef(tmp); - DEBUG(std::cerr << "Resulting PHI: " << *saveValue << "\n"); - lastPhi = tmp; - kernelPHIs[V->first][I->first] = lastPhi; - newValLocation[lastPhi] = machineBB; - } + //Get machine code for this instruction + MachineCodeForInstruction & tempMvec = MachineCodeForInstruction::get(defaultInst); + tempMvec.addTemp((Value*) lastPhi); + + MachineInstr *saveValue = BuildMI(*machineBB, machineBB->begin(), V9::PHI, 3).addReg(kernelValue[V->first]).addReg(I->second).addRegDef(lastPhi); + DEBUG(std::cerr << "Resulting PHI: " << *saveValue << "\n"); + newValLocation[lastPhi] = machineBB; + } + else { + Instruction *tmp = new TmpInstruction(I->second); + + //Get machine code for this instruction + MachineCodeForInstruction & tempMvec = MachineCodeForInstruction::get(defaultInst); + tempMvec.addTemp((Value*) tmp); + + + MachineInstr *saveValue = BuildMI(*machineBB, machineBB->begin(), V9::PHI, 3).addReg(lastPhi).addReg(I->second).addRegDef(tmp); + DEBUG(std::cerr << "Resulting PHI: " << *saveValue << "\n"); + lastPhi = tmp; + kernelPHIs[V->first][I->first] = lastPhi; + newValLocation[lastPhi] = machineBB; + } } //Final phi value else { - //The resulting value must be the Value* we created earlier - assert(lastPhi != 0 && "Last phi is NULL!\n"); - MachineInstr *saveValue = BuildMI(*machineBB, machineBB->begin(), V9::PHI, 3).addReg(lastPhi).addReg(I->second).addRegDef(finalPHIValue[V->first]); - DEBUG(std::cerr << "Resulting PHI: " << *saveValue << "\n"); - kernelPHIs[V->first][I->first] = finalPHIValue[V->first]; + //The resulting value must be the Value* we created earlier + assert(lastPhi != 0 && "Last phi is NULL!\n"); + MachineInstr *saveValue = BuildMI(*machineBB, machineBB->begin(), V9::PHI, 3).addReg(lastPhi).addReg(I->second).addRegDef(finalPHIValue[V->first]); + DEBUG(std::cerr << "Resulting PHI: " << *saveValue << "\n"); + kernelPHIs[V->first][I->first] = finalPHIValue[V->first]; } ++count; @@ -2436,55 +2436,55 @@ Instruction *tmp = 0; for(unsigned i = 0; i < I->getNumOperands(); ++i) { - //Get Operand - const MachineOperand &mOp = I->getOperand(i); - assert(mOp.getType() == MachineOperand::MO_VirtualRegister && "Should be a Value*\n"); - - if(!tmp) { - tmp = new TmpInstruction(mOp.getVRegValue()); - addToMCFI.push_back(tmp); - } - - //Now for all our arguments we read, OR to the new TmpInstruction that we created - if(mOp.isUse()) { - DEBUG(std::cerr << "Use: " << mOp << "\n"); - //Place a copy at the end of its BB but before the branches - assert(newValLocation.count(mOp.getVRegValue()) && "We must know where this value is located\n"); - //Reverse iterate to find the branches, we can safely assume no instructions have been - //put in the nop positions - for(MachineBasicBlock::iterator inst = --(newValLocation[mOp.getVRegValue()])->end(), endBB = (newValLocation[mOp.getVRegValue()])->begin(); inst != endBB; --inst) { - MachineOpCode opc = inst->getOpcode(); - if(TMI->isBranch(opc) || TMI->isNop(opc)) - continue; - else { - if(mOp.getVRegValue()->getType() == Type::FloatTy) - BuildMI(*(newValLocation[mOp.getVRegValue()]), ++inst, V9::FMOVS, 3).addReg(mOp.getVRegValue()).addRegDef(tmp); - else if(mOp.getVRegValue()->getType() == Type::DoubleTy) - BuildMI(*(newValLocation[mOp.getVRegValue()]), ++inst, V9::FMOVD, 3).addReg(mOp.getVRegValue()).addRegDef(tmp); - else - BuildMI(*(newValLocation[mOp.getVRegValue()]), ++inst, V9::ORr, 3).addReg(mOp.getVRegValue()).addImm(0).addRegDef(tmp); - - break; - } - - } - - } - else { - //Remove the phi and replace it with an OR - DEBUG(std::cerr << "Def: " << mOp << "\n"); - //newORs.push_back(std::make_pair(tmp, mOp.getVRegValue())); - if(tmp->getType() == Type::FloatTy) - BuildMI(*kernelBB, I, V9::FMOVS, 3).addReg(tmp).addRegDef(mOp.getVRegValue()); - else if(tmp->getType() == Type::DoubleTy) - BuildMI(*kernelBB, I, V9::FMOVD, 3).addReg(tmp).addRegDef(mOp.getVRegValue()); - else - BuildMI(*kernelBB, I, V9::ORr, 3).addReg(tmp).addImm(0).addRegDef(mOp.getVRegValue()); - - - worklist.push_back(std::make_pair(kernelBB, I)); - } - + //Get Operand + const MachineOperand &mOp = I->getOperand(i); + assert(mOp.getType() == MachineOperand::MO_VirtualRegister && "Should be a Value*\n"); + + if(!tmp) { + tmp = new TmpInstruction(mOp.getVRegValue()); + addToMCFI.push_back(tmp); + } + + //Now for all our arguments we read, OR to the new TmpInstruction that we created + if(mOp.isUse()) { + DEBUG(std::cerr << "Use: " << mOp << "\n"); + //Place a copy at the end of its BB but before the branches + assert(newValLocation.count(mOp.getVRegValue()) && "We must know where this value is located\n"); + //Reverse iterate to find the branches, we can safely assume no instructions have been + //put in the nop positions + for(MachineBasicBlock::iterator inst = --(newValLocation[mOp.getVRegValue()])->end(), endBB = (newValLocation[mOp.getVRegValue()])->begin(); inst != endBB; --inst) { + MachineOpCode opc = inst->getOpcode(); + if(TMI->isBranch(opc) || TMI->isNop(opc)) + continue; + else { + if(mOp.getVRegValue()->getType() == Type::FloatTy) + BuildMI(*(newValLocation[mOp.getVRegValue()]), ++inst, V9::FMOVS, 3).addReg(mOp.getVRegValue()).addRegDef(tmp); + else if(mOp.getVRegValue()->getType() == Type::DoubleTy) + BuildMI(*(newValLocation[mOp.getVRegValue()]), ++inst, V9::FMOVD, 3).addReg(mOp.getVRegValue()).addRegDef(tmp); + else + BuildMI(*(newValLocation[mOp.getVRegValue()]), ++inst, V9::ORr, 3).addReg(mOp.getVRegValue()).addImm(0).addRegDef(tmp); + + break; + } + + } + + } + else { + //Remove the phi and replace it with an OR + DEBUG(std::cerr << "Def: " << mOp << "\n"); + //newORs.push_back(std::make_pair(tmp, mOp.getVRegValue())); + if(tmp->getType() == Type::FloatTy) + BuildMI(*kernelBB, I, V9::FMOVS, 3).addReg(tmp).addRegDef(mOp.getVRegValue()); + else if(tmp->getType() == Type::DoubleTy) + BuildMI(*kernelBB, I, V9::FMOVD, 3).addReg(tmp).addRegDef(mOp.getVRegValue()); + else + BuildMI(*kernelBB, I, V9::ORr, 3).addReg(tmp).addImm(0).addRegDef(mOp.getVRegValue()); + + + worklist.push_back(std::make_pair(kernelBB, I)); + } + } } @@ -2509,58 +2509,58 @@ DEBUG(std::cerr << "Looking at Instr: " << *I << "\n"); //Get op code and check if its a phi if(I->getOpcode() == V9::PHI) { - Instruction *tmp = 0; + Instruction *tmp = 0; - for(unsigned i = 0; i < I->getNumOperands(); ++i) { - //Get Operand - const MachineOperand &mOp = I->getOperand(i); - assert(mOp.getType() == MachineOperand::MO_VirtualRegister && "Should be a Value*\n"); - - if(!tmp) { - tmp = new TmpInstruction(mOp.getVRegValue()); - addToMCFI.push_back(tmp); - } - - //Now for all our arguments we read, OR to the new TmpInstruction that we created - if(mOp.isUse()) { - DEBUG(std::cerr << "Use: " << mOp << "\n"); - //Place a copy at the end of its BB but before the branches - assert(newValLocation.count(mOp.getVRegValue()) && "We must know where this value is located\n"); - //Reverse iterate to find the branches, we can safely assume no instructions have been - //put in the nop positions - for(MachineBasicBlock::iterator inst = --(newValLocation[mOp.getVRegValue()])->end(), endBB = (newValLocation[mOp.getVRegValue()])->begin(); inst != endBB; --inst) { - MachineOpCode opc = inst->getOpcode(); - if(TMI->isBranch(opc) || TMI->isNop(opc)) - continue; - else { - if(mOp.getVRegValue()->getType() == Type::FloatTy) - BuildMI(*(newValLocation[mOp.getVRegValue()]), ++inst, V9::FMOVS, 3).addReg(mOp.getVRegValue()).addRegDef(tmp); - else if(mOp.getVRegValue()->getType() == Type::DoubleTy) - BuildMI(*(newValLocation[mOp.getVRegValue()]), ++inst, V9::FMOVD, 3).addReg(mOp.getVRegValue()).addRegDef(tmp); - else - BuildMI(*(newValLocation[mOp.getVRegValue()]), ++inst, V9::ORr, 3).addReg(mOp.getVRegValue()).addImm(0).addRegDef(tmp); - - - break; - } - - } - - } - else { - //Remove the phi and replace it with an OR - DEBUG(std::cerr << "Def: " << mOp << "\n"); - if(tmp->getType() == Type::FloatTy) - BuildMI(**MB, I, V9::FMOVS, 3).addReg(tmp).addRegDef(mOp.getVRegValue()); - else if(tmp->getType() == Type::DoubleTy) - BuildMI(**MB, I, V9::FMOVD, 3).addReg(tmp).addRegDef(mOp.getVRegValue()); - else - BuildMI(**MB, I, V9::ORr, 3).addReg(tmp).addImm(0).addRegDef(mOp.getVRegValue()); - - worklist.push_back(std::make_pair(*MB,I)); - } - - } + for(unsigned i = 0; i < I->getNumOperands(); ++i) { + //Get Operand + const MachineOperand &mOp = I->getOperand(i); + assert(mOp.getType() == MachineOperand::MO_VirtualRegister && "Should be a Value*\n"); + + if(!tmp) { + tmp = new TmpInstruction(mOp.getVRegValue()); + addToMCFI.push_back(tmp); + } + + //Now for all our arguments we read, OR to the new TmpInstruction that we created + if(mOp.isUse()) { + DEBUG(std::cerr << "Use: " << mOp << "\n"); + //Place a copy at the end of its BB but before the branches + assert(newValLocation.count(mOp.getVRegValue()) && "We must know where this value is located\n"); + //Reverse iterate to find the branches, we can safely assume no instructions have been + //put in the nop positions + for(MachineBasicBlock::iterator inst = --(newValLocation[mOp.getVRegValue()])->end(), endBB = (newValLocation[mOp.getVRegValue()])->begin(); inst != endBB; --inst) { + MachineOpCode opc = inst->getOpcode(); + if(TMI->isBranch(opc) || TMI->isNop(opc)) + continue; + else { + if(mOp.getVRegValue()->getType() == Type::FloatTy) + BuildMI(*(newValLocation[mOp.getVRegValue()]), ++inst, V9::FMOVS, 3).addReg(mOp.getVRegValue()).addRegDef(tmp); + else if(mOp.getVRegValue()->getType() == Type::DoubleTy) + BuildMI(*(newValLocation[mOp.getVRegValue()]), ++inst, V9::FMOVD, 3).addReg(mOp.getVRegValue()).addRegDef(tmp); + else + BuildMI(*(newValLocation[mOp.getVRegValue()]), ++inst, V9::ORr, 3).addReg(mOp.getVRegValue()).addImm(0).addRegDef(tmp); + + + break; + } + + } + + } + else { + //Remove the phi and replace it with an OR + DEBUG(std::cerr << "Def: " << mOp << "\n"); + if(tmp->getType() == Type::FloatTy) + BuildMI(**MB, I, V9::FMOVS, 3).addReg(tmp).addRegDef(mOp.getVRegValue()); + else if(tmp->getType() == Type::DoubleTy) + BuildMI(**MB, I, V9::FMOVD, 3).addReg(tmp).addRegDef(mOp.getVRegValue()); + else + BuildMI(**MB, I, V9::ORr, 3).addReg(tmp).addImm(0).addRegDef(mOp.getVRegValue()); + + worklist.push_back(std::make_pair(*MB,I)); + } + + } } @@ -2581,7 +2581,7 @@ DEBUG(std::cerr << "Deleting PHI " << *I->second << "\n"); I->first->erase(I->second); - + } @@ -2615,64 +2615,64 @@ lastInstrs[inst] = I->second; for(unsigned i=0; i < inst->getNumOperands(); ++i) { - //get machine operand - const MachineOperand &mOp = inst->getOperand(i); - - if(mOp.getType() == MachineOperand::MO_VirtualRegister && mOp.isUse()) { - //find the value in the map - if (const Value* srcI = mOp.getVRegValue()) { - - if(isa(srcI) || isa(srcI)) - continue; - - //Before we declare this Value* one that we should save - //make sure its def is not of the same stage as this instruction - //because it will be consumed before its used - Instruction *defInst = (Instruction*) srcI; - - //Should we save this value? - bool save = true; - - //Continue if not in the def map, loop invariant code does not need to be saved - if(!defMap.count(srcI)) - continue; - - MachineInstr *defInstr = defMap[srcI]; - - - if(lastInstrs.count(defInstr)) { - if(lastInstrs[defInstr] == I->second) { - save = false; - - } - } - - if(save) { - assert(!phiUses.count(srcI) && "Did not expect to see phi use twice"); - if(isa(srcI)) - phiUses[srcI] = I->second; - - valuesToSave[srcI] = std::make_pair(I->first, i); - - } - } - } - else if(mOp.getType() == MachineOperand::MO_VirtualRegister && mOp.isDef()) { - if (const Value* destI = mOp.getVRegValue()) { - if(!isa(destI)) - continue; - if(phiUses.count(destI)) { - if(phiUses[destI] == I->second) { - //remove from save list - valuesToSave.erase(destI); - } - } - } - } - - if(mOp.getType() != MachineOperand::MO_VirtualRegister && mOp.isUse()) { - assert("Our assumption is wrong. We have another type of register that needs to be saved\n"); - } + //get machine operand + const MachineOperand &mOp = inst->getOperand(i); + + if(mOp.getType() == MachineOperand::MO_VirtualRegister && mOp.isUse()) { + //find the value in the map + if (const Value* srcI = mOp.getVRegValue()) { + + if(isa(srcI) || isa(srcI)) + continue; + + //Before we declare this Value* one that we should save + //make sure its def is not of the same stage as this instruction + //because it will be consumed before its used + Instruction *defInst = (Instruction*) srcI; + + //Should we save this value? + bool save = true; + + //Continue if not in the def map, loop invariant code does not need to be saved + if(!defMap.count(srcI)) + continue; + + MachineInstr *defInstr = defMap[srcI]; + + + if(lastInstrs.count(defInstr)) { + if(lastInstrs[defInstr] == I->second) { + save = false; + + } + } + + if(save) { + assert(!phiUses.count(srcI) && "Did not expect to see phi use twice"); + if(isa(srcI)) + phiUses[srcI] = I->second; + + valuesToSave[srcI] = std::make_pair(I->first, i); + + } + } + } + else if(mOp.getType() == MachineOperand::MO_VirtualRegister && mOp.isDef()) { + if (const Value* destI = mOp.getVRegValue()) { + if(!isa(destI)) + continue; + if(phiUses.count(destI)) { + if(phiUses[destI] == I->second) { + //remove from save list + valuesToSave.erase(destI); + } + } + } + } + + if(mOp.getType() != MachineOperand::MO_VirtualRegister && mOp.isUse()) { + assert("Our assumption is wrong. We have another type of register that needs to be saved\n"); + } } } } @@ -2764,27 +2764,27 @@ //Find terminator since getFirstTerminator does not work! for(MachineBasicBlock::reverse_iterator mInst = prologues[I]->rbegin(), mInstEnd = prologues[I]->rend(); mInst != mInstEnd; ++mInst) { - MachineOpCode OC = mInst->getOpcode(); - //If its a branch update its branchto - if(TMI->isBranch(OC)) { - for(unsigned opNum = 0; opNum < mInst->getNumOperands(); ++opNum) { - MachineOperand &mOp = mInst->getOperand(opNum); - if (mOp.getType() == MachineOperand::MO_PCRelativeDisp) { - //Check if we are branching to the kernel, if not branch to epilogue - if(mOp.getVRegValue() == BB->getBasicBlock()) { - if(I == prologues.size()-1) - mOp.setValueReg(llvmKernelBB); - else - mOp.setValueReg(llvm_prologues[I+1]); - } - else { - mOp.setValueReg(llvm_epilogues[(llvm_epilogues.size()-1-I)]); - } - } - } + MachineOpCode OC = mInst->getOpcode(); + //If its a branch update its branchto + if(TMI->isBranch(OC)) { + for(unsigned opNum = 0; opNum < mInst->getNumOperands(); ++opNum) { + MachineOperand &mOp = mInst->getOperand(opNum); + if (mOp.getType() == MachineOperand::MO_PCRelativeDisp) { + //Check if we are branching to the kernel, if not branch to epilogue + if(mOp.getVRegValue() == BB->getBasicBlock()) { + if(I == prologues.size()-1) + mOp.setValueReg(llvmKernelBB); + else + mOp.setValueReg(llvm_prologues[I+1]); + } + else { + mOp.setValueReg(llvm_epilogues[(llvm_epilogues.size()-1-I)]); + } + } + } - DEBUG(std::cerr << "New Prologue Branch: " << *mInst << "\n"); - } + DEBUG(std::cerr << "New Prologue Branch: " << *mInst << "\n"); + } } @@ -2793,16 +2793,16 @@ const BranchInst *branchVal = dyn_cast(BB->getBasicBlock()->getTerminator()); if(I == prologues.size()-1) { - TerminatorInst *newBranch = new BranchInst(llvmKernelBB, - llvm_epilogues[(llvm_epilogues.size()-1-I)], - branchVal->getCondition(), - llvm_prologues[I]); + TerminatorInst *newBranch = new BranchInst(llvmKernelBB, + llvm_epilogues[(llvm_epilogues.size()-1-I)], + branchVal->getCondition(), + llvm_prologues[I]); } else - TerminatorInst *newBranch = new BranchInst(llvm_prologues[I+1], - llvm_epilogues[(llvm_epilogues.size()-1-I)], - branchVal->getCondition(), - llvm_prologues[I]); + TerminatorInst *newBranch = new BranchInst(llvm_prologues[I+1], + llvm_epilogues[(llvm_epilogues.size()-1-I)], + branchVal->getCondition(), + llvm_prologues[I]); } } @@ -2814,21 +2814,21 @@ MachineOpCode OC = mInst->getOpcode(); if(TMI->isBranch(OC)) { for(unsigned opNum = 0; opNum < mInst->getNumOperands(); ++opNum) { - MachineOperand &mOp = mInst->getOperand(opNum); - - if(mOp.getType() == MachineOperand::MO_PCRelativeDisp) { - if(mOp.getVRegValue() == BB->getBasicBlock()) - mOp.setValueReg(llvmKernelBB); - else - if(llvm_epilogues.size() > 0) { - assert(origBranchExit == 0 && "There should only be one branch out of the loop"); - - origBranchExit = mOp.getVRegValue(); - mOp.setValueReg(llvm_epilogues[0]); - } - else - origBranchExit = mOp.getVRegValue(); - } + MachineOperand &mOp = mInst->getOperand(opNum); + + if(mOp.getType() == MachineOperand::MO_PCRelativeDisp) { + if(mOp.getVRegValue() == BB->getBasicBlock()) + mOp.setValueReg(llvmKernelBB); + else + if(llvm_epilogues.size() > 0) { + assert(origBranchExit == 0 && "There should only be one branch out of the loop"); + + origBranchExit = mOp.getVRegValue(); + mOp.setValueReg(llvm_epilogues[0]); + } + else + origBranchExit = mOp.getVRegValue(); + } } } } @@ -2840,17 +2840,17 @@ if(epilogues.size() > 0) { TerminatorInst *newBranch = new BranchInst(llvmKernelBB, - llvm_epilogues[0], - branchVal->getCondition(), - llvmKernelBB); + llvm_epilogues[0], + branchVal->getCondition(), + llvmKernelBB); } else { BasicBlock *origBBExit = dyn_cast(origBranchExit); assert(origBBExit !=0 && "Original exit basic block must be set"); TerminatorInst *newBranch = new BranchInst(llvmKernelBB, - origBBExit, - branchVal->getCondition(), - llvmKernelBB); + origBBExit, + branchVal->getCondition(), + llvmKernelBB); } if(schedule.getMaxStage() != 0) { @@ -2862,7 +2862,7 @@ BuildMI(epilogues[I], V9::BA, 1).addPCDisp(llvm_epilogues[I+1]); //Add unconditional branch to end of epilogue TerminatorInst *newBranch = new BranchInst(llvm_epilogues[I+1], - llvm_epilogues[I]); + llvm_epilogues[I]); } else { @@ -2874,8 +2874,8 @@ //Find where we are supposed to branch to BasicBlock *nextBlock = 0; for(unsigned j=0; j getNumSuccessors(); ++j) { - if(branchVal->getSuccessor(j) != BB->getBasicBlock()) - nextBlock = branchVal->getSuccessor(j); + if(branchVal->getSuccessor(j) != BB->getBasicBlock()) + nextBlock = branchVal->getSuccessor(j); } assert((nextBlock != 0) && "Next block should not be null!"); @@ -2907,51 +2907,51 @@ //Update the terminator TerminatorInst *term = ((BasicBlock*)*P)->getTerminator(); for(unsigned i=0; i < term->getNumSuccessors(); ++i) { - if(term->getSuccessor(i) == llvmBB) { - DEBUG(std::cerr << "Replacing successor bb\n"); - if(llvm_prologues.size() > 0) { - term->setSuccessor(i, llvm_prologues[0]); - //Also update its corresponding machine instruction - MachineCodeForInstruction & tempMvec = - MachineCodeForInstruction::get(term); - for (unsigned j = 0; j < tempMvec.size(); j++) { - MachineInstr *temp = tempMvec[j]; - MachineOpCode opc = temp->getOpcode(); - if(TMI->isBranch(opc)) { - DEBUG(std::cerr << *temp << "\n"); - //Update branch - for(unsigned opNum = 0; opNum < temp->getNumOperands(); ++opNum) { - MachineOperand &mOp = temp->getOperand(opNum); - if (mOp.getType() == MachineOperand::MO_PCRelativeDisp) { - if(mOp.getVRegValue() == llvmBB) - mOp.setValueReg(llvm_prologues[0]); - } - } - } - } - } - else { - term->setSuccessor(i, llvmKernelBB); - //Also update its corresponding machine instruction - MachineCodeForInstruction & tempMvec = - MachineCodeForInstruction::get(term); - for (unsigned j = 0; j < tempMvec.size(); j++) { - MachineInstr *temp = tempMvec[j]; - MachineOpCode opc = temp->getOpcode(); - if(TMI->isBranch(opc)) { - DEBUG(std::cerr << *temp << "\n"); - //Update branch - for(unsigned opNum = 0; opNum < temp->getNumOperands(); ++opNum) { - MachineOperand &mOp = temp->getOperand(opNum); - if (mOp.getType() == MachineOperand::MO_PCRelativeDisp) { - if(mOp.getVRegValue() == llvmBB) - mOp.setValueReg(llvmKernelBB); - } - } - } - } - } - } + if(term->getSuccessor(i) == llvmBB) { + DEBUG(std::cerr << "Replacing successor bb\n"); + if(llvm_prologues.size() > 0) { + term->setSuccessor(i, llvm_prologues[0]); + //Also update its corresponding machine instruction + MachineCodeForInstruction & tempMvec = + MachineCodeForInstruction::get(term); + for (unsigned j = 0; j < tempMvec.size(); j++) { + MachineInstr *temp = tempMvec[j]; + MachineOpCode opc = temp->getOpcode(); + if(TMI->isBranch(opc)) { + DEBUG(std::cerr << *temp << "\n"); + //Update branch + for(unsigned opNum = 0; opNum < temp->getNumOperands(); ++opNum) { + MachineOperand &mOp = temp->getOperand(opNum); + if (mOp.getType() == MachineOperand::MO_PCRelativeDisp) { + if(mOp.getVRegValue() == llvmBB) + mOp.setValueReg(llvm_prologues[0]); + } + } + } + } + } + else { + term->setSuccessor(i, llvmKernelBB); + //Also update its corresponding machine instruction + MachineCodeForInstruction & tempMvec = + MachineCodeForInstruction::get(term); + for (unsigned j = 0; j < tempMvec.size(); j++) { + MachineInstr *temp = tempMvec[j]; + MachineOpCode opc = temp->getOpcode(); + if(TMI->isBranch(opc)) { + DEBUG(std::cerr << *temp << "\n"); + //Update branch + for(unsigned opNum = 0; opNum < temp->getNumOperands(); ++opNum) { + MachineOperand &mOp = temp->getOperand(opNum); + if (mOp.getType() == MachineOperand::MO_PCRelativeDisp) { + if(mOp.getVRegValue() == llvmBB) + mOp.setValueReg(llvmKernelBB); + } + } + } + } + } + } } break; } Index: llvm/lib/Target/SparcV9/ModuloScheduling/ModuloScheduling.h diff -u llvm/lib/Target/SparcV9/ModuloScheduling/ModuloScheduling.h:1.31 llvm/lib/Target/SparcV9/ModuloScheduling/ModuloScheduling.h:1.32 --- llvm/lib/Target/SparcV9/ModuloScheduling/ModuloScheduling.h:1.31 Thu Jun 16 23:00:57 2005 +++ llvm/lib/Target/SparcV9/ModuloScheduling/ModuloScheduling.h Wed Jul 27 00:53:44 2005 @@ -34,9 +34,9 @@ int depth; int height; MSNodeAttributes(int asap=-1, int alap=-1, int mob=-1, - int d=-1, int h=-1) : ASAP(asap), ALAP(alap), - MOB(mob), depth(d), - height(h) {} + int d=-1, int h=-1) : ASAP(asap), ALAP(alap), + MOB(mob), depth(d), + height(h) {} }; @@ -80,7 +80,7 @@ bool CreateDefMap(MachineBasicBlock *BI); bool MachineBBisValid(const MachineBasicBlock *BI); bool assocIndVar(Instruction *I, std::set &indVar, - std::vector &stack, BasicBlock *BB); + std::vector &stack, BasicBlock *BB); int calculateResMII(const MachineBasicBlock *BI); int calculateRecMII(MSchedGraph *graph, int MII); void calculateNodeAttributes(MSchedGraph *graph, int MII); @@ -96,36 +96,36 @@ int findMaxASAP(); void orderNodes(); void findAllReccurrences(MSchedGraphNode *node, - std::vector &visitedNodes, int II); + std::vector &visitedNodes, int II); void addReccurrence(std::vector &recurrence, int II, MSchedGraphNode*, MSchedGraphNode*); void addSCC(std::vector &SCC, std::map &newNodes); void findAllCircuits(MSchedGraph *MSG, int II); bool circuit(MSchedGraphNode *v, std::vector &stack, - std::set &blocked, - std::vector &SCC, MSchedGraphNode *s, - std::map > &B, int II, - std::map &newNodes); + std::set &blocked, + std::vector &SCC, MSchedGraphNode *s, + std::map > &B, int II, + std::map &newNodes); void unblock(MSchedGraphNode *u, std::set &blocked, - std::map > &B); + std::map > &B); void addRecc(std::vector &stack, std::map &newNodes); - void searchPath(MSchedGraphNode *node, - std::vector &path, - std::set &nodesToAdd, - std::set &new_reccurence); + void searchPath(MSchedGraphNode *node, + std::vector &path, + std::set &nodesToAdd, + std::set &new_reccurence); void pathToRecc(MSchedGraphNode *node, - std::vector &path, - std::set &poSet, std::set &lastNodes); + std::vector &path, + std::set &poSet, std::set &lastNodes); void computePartialOrder(); bool computeSchedule(const MachineBasicBlock *BB, MSchedGraph *MSG); - bool scheduleNode(MSchedGraphNode *node, - int start, int end); + bool scheduleNode(MSchedGraphNode *node, + int start, int end); void predIntersect(std::set &CurrentSet, std::set &IntersectResult); void succIntersect(std::set &CurrentSet, std::set &IntersectResult); @@ -159,7 +159,7 @@ /// before we run. AU.addRequired(); AU.addRequired(); - + AU.addRequired(); } Index: llvm/lib/Target/SparcV9/ModuloScheduling/ModuloSchedulingSuperBlock.cpp diff -u llvm/lib/Target/SparcV9/ModuloScheduling/ModuloSchedulingSuperBlock.cpp:1.3 llvm/lib/Target/SparcV9/ModuloScheduling/ModuloSchedulingSuperBlock.cpp:1.4 --- llvm/lib/Target/SparcV9/ModuloScheduling/ModuloSchedulingSuperBlock.cpp:1.3 Fri Jul 1 01:40:58 2005 +++ llvm/lib/Target/SparcV9/ModuloScheduling/ModuloSchedulingSuperBlock.cpp Wed Jul 27 00:53:44 2005 @@ -74,11 +74,11 @@ Statistic<> NumSB("moduloschedSB-numSuperBlocks", "Total Number of SuperBlocks"); Statistic<> BBWithCalls("modulosched-BBCalls", "Basic Blocks rejected due to calls"); Statistic<> BBWithCondMov("modulosched-loopCondMov", - "Basic Blocks rejected due to conditional moves"); + "Basic Blocks rejected due to conditional moves"); Statistic<> SBResourceConstraint("modulosched-resourceConstraint", - "Loops constrained by resources"); + "Loops constrained by resources"); Statistic<> SBRecurrenceConstraint("modulosched-recurrenceConstraint", - "Loops constrained by recurrences"); + "Loops constrained by recurrences"); Statistic<> SBFinalIISum("modulosched-finalIISum", "Sum of all final II"); Statistic<> SBIISum("modulosched-IISum", "Sum of all theoretical II"); Statistic<> SBMSLoops("modulosched-schedLoops", "Number of loops successfully modulo-scheduled"); @@ -97,42 +97,42 @@ static std::string getNodeLabel(MSchedGraphSBNode *Node, MSchedGraphSB *Graph) { if(!Node->isPredicate()) { - if (Node->getInst()) { - std::stringstream ss; - ss << *(Node->getInst()); - return ss.str(); //((MachineInstr*)Node->getInst()); - } - else - return "No Inst"; + if (Node->getInst()) { + std::stringstream ss; + ss << *(Node->getInst()); + return ss.str(); //((MachineInstr*)Node->getInst()); + } + else + return "No Inst"; } else - return "Pred Node"; + return "Pred Node"; } static std::string getEdgeSourceLabel(MSchedGraphSBNode *Node, - MSchedGraphSBNode::succ_iterator I) { + MSchedGraphSBNode::succ_iterator I) { //Label each edge with the type of dependence std::string edgelabel = ""; switch (I.getEdge().getDepOrderType()) { - + case MSchedGraphSBEdge::TrueDep: - edgelabel = "True"; - break; + edgelabel = "True"; + break; case MSchedGraphSBEdge::AntiDep: - edgelabel = "Anti"; - break; - + edgelabel = "Anti"; + break; + case MSchedGraphSBEdge::OutputDep: - edgelabel = "Output"; - break; - + edgelabel = "Output"; + break; + case MSchedGraphSBEdge::NonDataDep: - edgelabel = "Pred"; - break; + edgelabel = "Pred"; + break; default: - edgelabel = "Unknown"; - break; + edgelabel = "Unknown"; + break; } //FIXME @@ -165,22 +165,22 @@ //Loop over worklist and ModuloSchedule each SuperBlock for(std::vector >::iterator SB = Worklist.begin(), - SBE = Worklist.end(); SB != SBE; ++SB) { + SBE = Worklist.end(); SB != SBE; ++SB) { //Print out Superblock DEBUG(std::cerr << "ModuloScheduling SB: \n"; - for(std::vector::const_iterator BI = SB->begin(), - BE = SB->end(); BI != BE; ++BI) { - (*BI)->print(std::cerr);}); + for(std::vector::const_iterator BI = SB->begin(), + BE = SB->end(); BI != BE; ++BI) { + (*BI)->print(std::cerr);}); if(!CreateDefMap(*SB)) { - defaultInst = 0; - defMap.clear(); - continue; + defaultInst = 0; + defMap.clear(); + continue; } MSchedGraphSB *MSG = new MSchedGraphSB(*SB, target, indVarInstrs[*SB], DA, - machineTollvm[*SB]); + machineTollvm[*SB]); //Write Graph out to file DEBUG(WriteGraphToFileSB(std::cerr, F.getName(), MSG)); @@ -195,9 +195,9 @@ //Our starting initiation interval is the maximum of RecMII and ResMII if(RecMII < ResMII) - ++SBRecurrenceConstraint; + ++SBRecurrenceConstraint; else - ++SBResourceConstraint; + ++SBResourceConstraint; II = std::max(RecMII, ResMII); int mII = II; @@ -211,11 +211,11 @@ //Dump node properties if in debug mode DEBUG(for(std::map::iterator I = nodeToAttributesMap.begin(), - E = nodeToAttributesMap.end(); I !=E; ++I) { - std::cerr << "Node: " << *(I->first) << " ASAP: " << I->second.ASAP << " ALAP: " - << I->second.ALAP << " MOB: " << I->second.MOB << " Depth: " << I->second.depth - << " Height: " << I->second.height << "\n"; - }); + E = nodeToAttributesMap.end(); I !=E; ++I) { + std::cerr << "Node: " << *(I->first) << " ASAP: " << I->second.ASAP << " ALAP: " + << I->second.ALAP << " MOB: " << I->second.MOB << " Depth: " << I->second.depth + << " Height: " << I->second.height << "\n"; + }); //Put nodes in order to schedule them @@ -223,19 +223,19 @@ //Dump out partial order DEBUG(for(std::vector >::iterator I = partialOrder.begin(), - E = partialOrder.end(); I !=E; ++I) { - std::cerr << "Start set in PO\n"; - for(std::set::iterator J = I->begin(), JE = I->end(); J != JE; ++J) - std::cerr << "PO:" << **J << "\n"; - }); + E = partialOrder.end(); I !=E; ++I) { + std::cerr << "Start set in PO\n"; + for(std::set::iterator J = I->begin(), JE = I->end(); J != JE; ++J) + std::cerr << "PO:" << **J << "\n"; + }); //Place nodes in final order orderNodes(); //Dump out order of nodes DEBUG(for(std::vector::iterator I = FinalNodeOrder.begin(), E = FinalNodeOrder.end(); I != E; ++I) { - std::cerr << "FO:" << **I << "\n"; - }); + std::cerr << "FO:" << **I << "\n"; + }); //Finally schedule nodes @@ -247,18 +247,18 @@ //Final scheduling step is to reconstruct the loop only if we actual have //stage > 0 if(haveSched) { - //schedule.printSchedule(std::cerr); - reconstructLoop(*SB); - ++SBMSLoops; - //Changed = true; - SBIISum += mII; - SBFinalIISum += II; - + //schedule.printSchedule(std::cerr); + reconstructLoop(*SB); + ++SBMSLoops; + //Changed = true; + SBIISum += mII; + SBFinalIISum += II; + if(schedule.getMaxStage() == 0) - ++SBSameStage; + ++SBSameStage; } else - ++SBNoSched; + ++SBNoSched; //Clear out our maps for the next basic block that is processed nodeToAttributesMap.clear(); @@ -273,7 +273,7 @@ } void ModuloSchedulingSBPass::FindSuperBlocks(Function &F, LoopInfo &LI, - std::vector > &Worklist) { + std::vector > &Worklist) { //Get MachineFunction MachineFunction &MF = MachineFunction::get(&F); @@ -294,95 +294,95 @@ //If loop is not single entry, try the next one if(!L->getLoopPreheader()) - continue; + continue; //Check size of this loop, we don't want SBB loops if(L->getBlocks().size() == 1) - continue; + continue; //Check if this loop contains no sub loops if(L->getSubLoops().size() == 0) { - - std::vector superBlock; - - //Get Loop Headers - BasicBlock *header = L->getHeader(); - - //Follow the header and make sure each BB only has one entry and is valid - BasicBlock *current = header; - assert(bbMap.count(current) && "LLVM BB must have corresponding Machine BB\n"); - MachineBasicBlock *currentMBB = bbMap[header]; - bool done = false; - bool success = true; - unsigned offset = 0; - std::map indexMap; - - while(!done) { - //Loop over successors of this BB, they should be in the - //loop block and be valid - BasicBlock *next = 0; - for(succ_iterator I = succ_begin(current), E = succ_end(current); - I != E; ++I) { - if(L->contains(*I)) { - if(!next) - next = *I; - else { - done = true; - success = false; - break; - } - } - } - - if(success) { - superBlock.push_back(currentMBB); - if(next == header) - done = true; - else if(!next->getSinglePredecessor()) { - done = true; - success = false; - } - else { - //Check that the next BB only has one entry - current = next; - assert(bbMap.count(current) && "LLVM BB must have corresponding Machine BB"); - currentMBB = bbMap[current]; - } - } - } - - - - - - if(success) { - ++NumSB; - - //Loop over all the blocks in the superblock - for(std::vector::iterator currentMBB = superBlock.begin(), MBBEnd = superBlock.end(); currentMBB != MBBEnd; ++currentMBB) { - if(!MachineBBisValid(*currentMBB, indexMap, offset)) { - success = false; - break; - } - } - } - - if(success) { - if(getIndVar(superBlock, bbMap, indexMap)) { - ++SBValid; - Worklist.push_back(superBlock); - SBSize += superBlock.size(); - } - else - ++SBInvalid; - } + + std::vector superBlock; + + //Get Loop Headers + BasicBlock *header = L->getHeader(); + + //Follow the header and make sure each BB only has one entry and is valid + BasicBlock *current = header; + assert(bbMap.count(current) && "LLVM BB must have corresponding Machine BB\n"); + MachineBasicBlock *currentMBB = bbMap[header]; + bool done = false; + bool success = true; + unsigned offset = 0; + std::map indexMap; + + while(!done) { + //Loop over successors of this BB, they should be in the + //loop block and be valid + BasicBlock *next = 0; + for(succ_iterator I = succ_begin(current), E = succ_end(current); + I != E; ++I) { + if(L->contains(*I)) { + if(!next) + next = *I; + else { + done = true; + success = false; + break; + } + } + } + + if(success) { + superBlock.push_back(currentMBB); + if(next == header) + done = true; + else if(!next->getSinglePredecessor()) { + done = true; + success = false; + } + else { + //Check that the next BB only has one entry + current = next; + assert(bbMap.count(current) && "LLVM BB must have corresponding Machine BB"); + currentMBB = bbMap[current]; + } + } + } + + + + + + if(success) { + ++NumSB; + + //Loop over all the blocks in the superblock + for(std::vector::iterator currentMBB = superBlock.begin(), MBBEnd = superBlock.end(); currentMBB != MBBEnd; ++currentMBB) { + if(!MachineBBisValid(*currentMBB, indexMap, offset)) { + success = false; + break; + } + } + } + + if(success) { + if(getIndVar(superBlock, bbMap, indexMap)) { + ++SBValid; + Worklist.push_back(superBlock); + SBSize += superBlock.size(); + } + else + ++SBInvalid; + } } } } bool ModuloSchedulingSBPass::getIndVar(std::vector &superBlock, std::map &bbMap, - std::map &indexMap) { + std::map &indexMap) { //See if we can get induction var instructions std::set llvmSuperBlock; @@ -409,14 +409,14 @@ indVar.insert(b); if(Instruction *I = dyn_cast(cond)) - if(bbMap.count(I->getParent())) { - if (!assocIndVar(I, indVar, stack, bbMap, superBlock[(superBlock.size()-1)]->getBasicBlock(), llvmSuperBlock)) - return false; - } - else - return false; + if(bbMap.count(I->getParent())) { + if (!assocIndVar(I, indVar, stack, bbMap, superBlock[(superBlock.size()-1)]->getBasicBlock(), llvmSuperBlock)) + return false; + } + else + return false; else - return false; + return false; } else { indVar.insert(b); @@ -424,43 +424,43 @@ //Dump out instructions associate with indvar for debug reasons DEBUG(for(std::set::iterator N = indVar.begin(), NE = indVar.end(); - N != NE; ++N) { - std::cerr << **N << "\n"; - }); + N != NE; ++N) { + std::cerr << **N << "\n"; + }); //Create map of machine instr to llvm instr std::map mllvm; for(std::vector::iterator MBB = superBlock.begin(), MBE = superBlock.end(); MBB != MBE; ++MBB) { BasicBlock *BB = (BasicBlock*) (*MBB)->getBasicBlock(); for(BasicBlock::iterator I = BB->begin(), E = BB->end(); I != E; ++I) { - MachineCodeForInstruction & tempMvec = MachineCodeForInstruction::get(I); - for (unsigned j = 0; j < tempMvec.size(); j++) { - mllvm[tempMvec[j]] = I; - } + MachineCodeForInstruction & tempMvec = MachineCodeForInstruction::get(I); + for (unsigned j = 0; j < tempMvec.size(); j++) { + mllvm[tempMvec[j]] = I; + } } } //Convert list of LLVM Instructions to list of Machine instructions std::map mIndVar; for(std::set::iterator N = indVar.begin(), - NE = indVar.end(); N != NE; ++N) { - - //If we have a load, we can't handle this loop because - //there is no way to preserve dependences between loads - //and stores - if(isa(*N)) - return false; - - MachineCodeForInstruction & tempMvec = MachineCodeForInstruction::get(*N); - for (unsigned j = 0; j < tempMvec.size(); j++) { - MachineOpCode OC = (tempMvec[j])->getOpcode(); - if(TMI->isNop(OC)) - continue; - if(!indexMap.count(tempMvec[j])) - continue; - mIndVar[(MachineInstr*) tempMvec[j]] = indexMap[(MachineInstr*) tempMvec[j]]; - DEBUG(std::cerr << *(tempMvec[j]) << " at index " << indexMap[(MachineInstr*) tempMvec[j]] << "\n"); - } + NE = indVar.end(); N != NE; ++N) { + + //If we have a load, we can't handle this loop because + //there is no way to preserve dependences between loads + //and stores + if(isa(*N)) + return false; + + MachineCodeForInstruction & tempMvec = MachineCodeForInstruction::get(*N); + for (unsigned j = 0; j < tempMvec.size(); j++) { + MachineOpCode OC = (tempMvec[j])->getOpcode(); + if(TMI->isNop(OC)) + continue; + if(!indexMap.count(tempMvec[j])) + continue; + mIndVar[(MachineInstr*) tempMvec[j]] = indexMap[(MachineInstr*) tempMvec[j]]; + DEBUG(std::cerr << *(tempMvec[j]) << " at index " << indexMap[(MachineInstr*) tempMvec[j]] << "\n"); + } } //Put into a map for future access @@ -472,38 +472,38 @@ } bool ModuloSchedulingSBPass::assocIndVar(Instruction *I, - std::set &indVar, - std::vector &stack, - std::map &bbMap, - const BasicBlock *last, std::set &llvmSuperBlock) { + std::set &indVar, + std::vector &stack, + std::map &bbMap, + const BasicBlock *last, std::set &llvmSuperBlock) { stack.push_back(I); //If this is a phi node, check if its the canonical indvar if(PHINode *PN = dyn_cast(I)) { if(llvmSuperBlock.count(PN->getParent())) { - if (Instruction *Inc = - dyn_cast(PN->getIncomingValueForBlock(last))) - if (Inc->getOpcode() == Instruction::Add && Inc->getOperand(0) == PN) - if (ConstantInt *CI = dyn_cast(Inc->getOperand(1))) - if (CI->equalsInt(1)) { - //We have found the indvar, so add the stack, and inc instruction to the set - indVar.insert(stack.begin(), stack.end()); - indVar.insert(Inc); - stack.pop_back(); - return true; - } - return false; + if (Instruction *Inc = + dyn_cast(PN->getIncomingValueForBlock(last))) + if (Inc->getOpcode() == Instruction::Add && Inc->getOperand(0) == PN) + if (ConstantInt *CI = dyn_cast(Inc->getOperand(1))) + if (CI->equalsInt(1)) { + //We have found the indvar, so add the stack, and inc instruction to the set + indVar.insert(stack.begin(), stack.end()); + indVar.insert(Inc); + stack.pop_back(); + return true; + } + return false; } } else { //Loop over each of the instructions operands, check if they are an instruction and in this BB for(unsigned i = 0; i < I->getNumOperands(); ++i) { - if(Instruction *N = dyn_cast(I->getOperand(i))) { - if(bbMap.count(N->getParent())) - if(!assocIndVar(N, indVar, stack, bbMap, last, llvmSuperBlock)) - return false; - } + if(Instruction *N = dyn_cast(I->getOperand(i))) { + if(bbMap.count(N->getParent())) + if(!assocIndVar(N, indVar, stack, bbMap, last, llvmSuperBlock)) + return false; + } } } @@ -517,8 +517,8 @@ /// calls) in the block. Currently ModuloScheduling only works on /// single basic block loops. bool ModuloSchedulingSBPass::MachineBBisValid(const MachineBasicBlock *BI, - std::map &indexMap, - unsigned &offset) { + std::map &indexMap, + unsigned &offset) { //Check size of our basic block.. make sure we have more then just the terminator in it if(BI->getBasicBlock()->size() == 1) @@ -534,26 +534,26 @@ //Look for calls if(TMI->isCall(OC)) { - ++BBWithCalls; - return false; + ++BBWithCalls; + return false; } //Look for conditional move if(OC == V9::MOVRZr || OC == V9::MOVRZi || OC == V9::MOVRLEZr || OC == V9::MOVRLEZi - || OC == V9::MOVRLZr || OC == V9::MOVRLZi || OC == V9::MOVRNZr || OC == V9::MOVRNZi - || OC == V9::MOVRGZr || OC == V9::MOVRGZi || OC == V9::MOVRGEZr - || OC == V9::MOVRGEZi || OC == V9::MOVLEr || OC == V9::MOVLEi || OC == V9::MOVLEUr - || OC == V9::MOVLEUi || OC == V9::MOVFLEr || OC == V9::MOVFLEi - || OC == V9::MOVNEr || OC == V9::MOVNEi || OC == V9::MOVNEGr || OC == V9::MOVNEGi - || OC == V9::MOVFNEr || OC == V9::MOVFNEi) { - ++BBWithCondMov; - return false; + || OC == V9::MOVRLZr || OC == V9::MOVRLZi || OC == V9::MOVRNZr || OC == V9::MOVRNZi + || OC == V9::MOVRGZr || OC == V9::MOVRGZi || OC == V9::MOVRGEZr + || OC == V9::MOVRGEZi || OC == V9::MOVLEr || OC == V9::MOVLEi || OC == V9::MOVLEUr + || OC == V9::MOVLEUi || OC == V9::MOVFLEr || OC == V9::MOVFLEi + || OC == V9::MOVNEr || OC == V9::MOVNEi || OC == V9::MOVNEGr || OC == V9::MOVNEGi + || OC == V9::MOVFNEr || OC == V9::MOVFNEi) { + ++BBWithCondMov; + return false; } indexMap[I] = count + offset; if(TMI->isNop(OC)) - continue; + continue; ++count; } @@ -568,30 +568,30 @@ defaultInst = 0; for(std::vector::iterator BI = SB.begin(), - BE = SB.end(); BI != BE; ++BI) { + BE = SB.end(); BI != BE; ++BI) { for(MachineBasicBlock::const_iterator I = (*BI)->begin(), E = (*BI)->end(); I != E; ++I) { for(unsigned opNum = 0; opNum < I->getNumOperands(); ++opNum) { - const MachineOperand &mOp = I->getOperand(opNum); - if(mOp.getType() == MachineOperand::MO_VirtualRegister && mOp.isDef()) { - Value *V = mOp.getVRegValue(); - //assert if this is the second def we have seen - if(defMap.count(V) && isa(V)) - DEBUG(std::cerr << "FIXME: Dup def for phi!\n"); - else { - //assert(!defMap.count(V) && "Def already in the map"); - if(defMap.count(V)) - return false; - defMap[V] = (MachineInstr*) &*I; - } - } - - //See if we can use this Value* as our defaultInst - if(!defaultInst && mOp.getType() == MachineOperand::MO_VirtualRegister) { - Value *V = mOp.getVRegValue(); - if(!isa(V) && !isa(V) && !isa(V) && !isa(V)) - defaultInst = (Instruction*) V; - } + const MachineOperand &mOp = I->getOperand(opNum); + if(mOp.getType() == MachineOperand::MO_VirtualRegister && mOp.isDef()) { + Value *V = mOp.getVRegValue(); + //assert if this is the second def we have seen + if(defMap.count(V) && isa(V)) + DEBUG(std::cerr << "FIXME: Dup def for phi!\n"); + else { + //assert(!defMap.count(V) && "Def already in the map"); + if(defMap.count(V)) + return false; + defMap[V] = (MachineInstr*) &*I; + } + } + + //See if we can use this Value* as our defaultInst + if(!defaultInst && mOp.getType() == MachineOperand::MO_VirtualRegister) { + Value *V = mOp.getVRegValue(); + if(!isa(V) && !isa(V) && !isa(V) && !isa(V)) + defaultInst = (Instruction*) V; + } } } } @@ -629,14 +629,14 @@ //Loop over resources in each cycle and increments their usage count for(unsigned i=0; i < resources.size(); ++i) - for(unsigned j=0; j < resources[i].size(); ++j) { - if(!resourceUsageCount.count(resources[i][j])) { - resourceUsageCount[resources[i][j]] = 1; - } - else { - resourceUsageCount[resources[i][j]] = resourceUsageCount[resources[i][j]] + 1; - } - } + for(unsigned j=0; j < resources[i].size(); ++j) { + if(!resourceUsageCount.count(resources[i][j])) { + resourceUsageCount[resources[i][j]] = 1; + } + else { + resourceUsageCount[resources[i][j]] = resourceUsageCount[resources[i][j]] + 1; + } + } } } @@ -692,7 +692,7 @@ int CircCountSB; void ModuloSchedulingSBPass::unblock(MSchedGraphSBNode *u, std::set &blocked, - std::map > &B) { + std::map > &B) { //Unblock u DEBUG(std::cerr << "Unblocking: " << *u << "\n"); @@ -726,13 +726,13 @@ for(unsigned i = 0; i < (*N)->succ_size(); ++i) { MSchedGraphSBEdge *edge = (*N)->getSuccessor(i); if(find(SCC.begin(), SCC.end(), edge->getDest()) != SCC.end()) { - totalDistance += edge->getIteDiff(); - if(edge->getIteDiff() > 0) - if(!start && !end) { - start = *N; - end = edge->getDest(); - } - + totalDistance += edge->getIteDiff(); + if(edge->getIteDiff() > 0) + if(!start && !end) { + start = *N; + end = edge->getDest(); + } + } } @@ -748,7 +748,7 @@ assert( (start && end) && "Must have start and end node to ignore edge for SCC"); - if(start && end) { + if(start && end) { //Insert reccurrence into the list DEBUG(std::cerr << "Ignore Edge from!!: " << *start << " to " << *end << "\n"); edgesToIgnore.insert(std::make_pair(newNodes[start], (newNodes[end])->getInEdgeNum(newNodes[start]))); @@ -762,9 +762,9 @@ } bool ModuloSchedulingSBPass::circuit(MSchedGraphSBNode *v, std::vector &stack, - std::set &blocked, std::vector &SCC, - MSchedGraphSBNode *s, std::map > &B, - int II, std::map &newNodes) { + std::set &blocked, std::vector &SCC, + MSchedGraphSBNode *s, std::map > &B, + int II, std::map &newNodes) { bool f = false; DEBUG(std::cerr << "Finding Circuits Starting with: ( " << v << ")"<< *v << "\n"); @@ -791,7 +791,7 @@ } else if(!blocked.count(*I)) { if(circuit(*I, stack, blocked, SCC, s, B, II, newNodes)) - f = true; + f = true; } else DEBUG(std::cerr << "Blocked: " << **I << "\n"); @@ -818,7 +818,7 @@ std::vector recc; //Dump recurrence for now DEBUG(std::cerr << "Starting Recc\n"); - + int totalDelay = 0; int totalDistance = 0; MSchedGraphSBNode *lastN = 0; @@ -834,8 +834,8 @@ totalDistance += iteDiff; if(iteDiff > 0) { - start = lastN; - end = *N; + start = lastN; + end = *N; } } //Get the original node @@ -851,7 +851,7 @@ DEBUG(std::cerr << "End Recc\n"); CircCountSB++; - if(start && end) { + if(start && end) { //Insert reccurrence into the list DEBUG(std::cerr << "Ignore Edge from!!: " << *start << " to " << *end << "\n"); edgesToIgnore.insert(std::make_pair(newNodes[start], (newNodes[end])->getInEdgeNum(newNodes[start]))); @@ -867,7 +867,7 @@ int value = totalDelay-(RecMII * totalDistance); int lastII = II; while(value < 0) { - + lastII = RecMII; RecMII--; value = totalDelay-(RecMII * totalDistance); @@ -921,64 +921,64 @@ //Find scc with the least vertex for (MSchedGraphSB::iterator GI = MSG->begin(), E = MSG->end(); GI != E; ++GI) if (Visited.insert(GI->second).second) { - for (scc_iterator SCCI = scc_begin(GI->second), - E = scc_end(GI->second); SCCI != E; ++SCCI) { - std::vector &nextSCC = *SCCI; - - if (Visited.insert(nextSCC[0]).second) { - Visited.insert(nextSCC.begin()+1, nextSCC.end()); - - if(nextSCC.size() > 1) { - DEBUG(std::cerr << "SCC size: " << nextSCC.size() << "\n"); - - for(unsigned i = 0; i < nextSCC.size(); ++i) { - //Loop over successor and see if in scc, then count edge - MSchedGraphSBNode *node = nextSCC[i]; - for(MSchedGraphSBNode::succ_iterator S = node->succ_begin(), SE = node->succ_end(); S != SE; ++S) { - if(find(nextSCC.begin(), nextSCC.end(), *S) != nextSCC.end()) - numEdges++; - } - } - DEBUG(std::cerr << "Num Edges: " << numEdges << "\n"); - } - - //Ignore self loops - if(nextSCC.size() > 1) { - - //Get least vertex in Vk - if(!s) { - s = nextSCC[0]; - Vk = nextSCC; - } - - for(unsigned i = 0; i < nextSCC.size(); ++i) { - if(nextSCC[i] < s) { - s = nextSCC[i]; - Vk = nextSCC; - } - } - } - } - } + for (scc_iterator SCCI = scc_begin(GI->second), + E = scc_end(GI->second); SCCI != E; ++SCCI) { + std::vector &nextSCC = *SCCI; + + if (Visited.insert(nextSCC[0]).second) { + Visited.insert(nextSCC.begin()+1, nextSCC.end()); + + if(nextSCC.size() > 1) { + DEBUG(std::cerr << "SCC size: " << nextSCC.size() << "\n"); + + for(unsigned i = 0; i < nextSCC.size(); ++i) { + //Loop over successor and see if in scc, then count edge + MSchedGraphSBNode *node = nextSCC[i]; + for(MSchedGraphSBNode::succ_iterator S = node->succ_begin(), SE = node->succ_end(); S != SE; ++S) { + if(find(nextSCC.begin(), nextSCC.end(), *S) != nextSCC.end()) + numEdges++; + } + } + DEBUG(std::cerr << "Num Edges: " << numEdges << "\n"); + } + + //Ignore self loops + if(nextSCC.size() > 1) { + + //Get least vertex in Vk + if(!s) { + s = nextSCC[0]; + Vk = nextSCC; + } + + for(unsigned i = 0; i < nextSCC.size(); ++i) { + if(nextSCC[i] < s) { + s = nextSCC[i]; + Vk = nextSCC; + } + } + } + } + } } //Process SCC DEBUG(for(std::vector::iterator N = Vk.begin(), NE = Vk.end(); - N != NE; ++N) { std::cerr << *((*N)->getInst()); }); + N != NE; ++N) { std::cerr << *((*N)->getInst()); }); //Iterate over all nodes in this scc for(std::vector::iterator N = Vk.begin(), NE = Vk.end(); - N != NE; ++N) { + N != NE; ++N) { blocked.erase(*N); B[*N].clear(); } if(Vk.size() > 1) { if(numEdges < 98) - circuit(s, stack, blocked, Vk, s, B, II, newNodes); + circuit(s, stack, blocked, Vk, s, B, II, newNodes); else - addSCC(Vk, newNodes); + addSCC(Vk, newNodes); //Delete nodes from the graph @@ -986,12 +986,12 @@ std::vector nodesToRemove; nodesToRemove.push_back(s); for(MSchedGraphSB::iterator N = MSG->begin(), NE = MSG->end(); N != NE; ++N) { - if(N->second < s ) - nodesToRemove.push_back(N->second); + if(N->second < s ) + nodesToRemove.push_back(N->second); } for(std::vector::iterator N = nodesToRemove.begin(), NE = nodesToRemove.end(); N != NE; ++N) { - DEBUG(std::cerr << "Deleting Node: " << **N << "\n"); - MSG->deleteNode(*N); + DEBUG(std::cerr << "Deleting Node: " << **N << "\n"); + MSG->deleteNode(*N); } } else @@ -1015,7 +1015,7 @@ //Assert if its already in the map assert(nodeToAttributesMap.count(I->second) == 0 && - "Node attributes are already in the map"); + "Node attributes are already in the map"); //Put into the map with default attribute values nodeToAttributesMap[I->second] = MSNodeSBAttributes(); @@ -1101,7 +1101,7 @@ int ModuloSchedulingSBPass::calculateALAP(MSchedGraphSBNode *node, int MII, - int maxASAP, MSchedGraphSBNode *srcNode) { + int maxASAP, MSchedGraphSBNode *srcNode) { DEBUG(std::cerr << "Calculating ALAP for " << *node << "\n"); @@ -1122,28 +1122,28 @@ //Iterate over all of the predecessors and fine max for(MSchedGraphSBNode::succ_iterator P = node->succ_begin(), - E = node->succ_end(); P != E; ++P) { + E = node->succ_end(); P != E; ++P) { //Only process if we are not ignoring the edge if(!ignoreEdge(node, *P)) { - processedOneEdge = true; - int succALAP = -1; - succALAP = calculateALAP(*P, MII, maxASAP, node); - - assert(succALAP != -1 && "Successors ALAP should have been caclulated"); - - int iteDiff = P.getEdge().getIteDiff(); - - int currentSuccValue = succALAP - node->getLatency() + iteDiff * MII; - - DEBUG(std::cerr << "succ ALAP: " << succALAP << ", iteDiff: " << iteDiff << ", SuccLatency: " << (*P)->getLatency() << ", Current ALAP succ: " << currentSuccValue << "\n"); + processedOneEdge = true; + int succALAP = -1; + succALAP = calculateALAP(*P, MII, maxASAP, node); + + assert(succALAP != -1 && "Successors ALAP should have been caclulated"); + + int iteDiff = P.getEdge().getIteDiff(); + + int currentSuccValue = succALAP - node->getLatency() + iteDiff * MII; + + DEBUG(std::cerr << "succ ALAP: " << succALAP << ", iteDiff: " << iteDiff << ", SuccLatency: " << (*P)->getLatency() << ", Current ALAP succ: " << currentSuccValue << "\n"); - minSuccValue = std::min(minSuccValue, currentSuccValue); + minSuccValue = std::min(minSuccValue, currentSuccValue); } } if(processedOneEdge) - attributes.ALAP = minSuccValue; + attributes.ALAP = minSuccValue; else attributes.ALAP = maxASAP; @@ -1163,7 +1163,7 @@ int maxASAP = 0; for(std::map::iterator I = nodeToAttributesMap.begin(), - E = nodeToAttributesMap.end(); I != E; ++I) + E = nodeToAttributesMap.end(); I != E; ++I) maxASAP = std::max(maxASAP, I->second.ASAP); return maxASAP; } @@ -1180,7 +1180,7 @@ //Iterate over all of the predecessors and find max for(MSchedGraphSBNode::succ_iterator P = node->succ_begin(), - E = node->succ_end(); P != E; ++P) { + E = node->succ_end(); P != E; ++P) { if(!ignoreEdge(node, *P)) { @@ -1199,7 +1199,7 @@ int ModuloSchedulingSBPass::calculateDepth(MSchedGraphSBNode *node, - MSchedGraphSBNode *destNode) { + MSchedGraphSBNode *destNode) { MSNodeSBAttributes &attributes = nodeToAttributesMap.find(node)->second; @@ -1239,24 +1239,24 @@ //along with any nodes that connect this recurrence to recurrences //already in the partial order for(std::set > >::reverse_iterator - I = recurrenceList.rbegin(), E=recurrenceList.rend(); I !=E; ++I) { + I = recurrenceList.rbegin(), E=recurrenceList.rend(); I !=E; ++I) { std::set new_recurrence; //Loop through recurrence and remove any nodes already in the partial order for(std::vector::const_iterator N = I->second.begin(), - NE = I->second.end(); N != NE; ++N) { + NE = I->second.end(); N != NE; ++N) { bool found = false; for(std::vector >::iterator PO = partialOrder.begin(), - PE = partialOrder.end(); PO != PE; ++PO) { - if(PO->count(*N)) - found = true; + PE = partialOrder.end(); PO != PE; ++PO) { + if(PO->count(*N)) + found = true; } //Check if its a branch, and remove to handle special if(!found) { - new_recurrence.insert(*N); + new_recurrence.insert(*N); } } @@ -1274,21 +1274,21 @@ //Add nodes that connect this recurrence to recurrences in the partial path for(std::set::iterator N = new_recurrence.begin(), NE = new_recurrence.end(); N != NE; ++N) - searchPath(*N, path, nodesToAdd, new_recurrence); + searchPath(*N, path, nodesToAdd, new_recurrence); //Add nodes to this recurrence if they are not already in the partial order for(std::set::iterator N = nodesToAdd.begin(), NE = nodesToAdd.end(); - N != NE; ++N) { - bool found = false; - for(std::vector >::iterator PO = partialOrder.begin(), - PE = partialOrder.end(); PO != PE; ++PO) { - if(PO->count(*N)) - found = true; - } - if(!found) { - assert("FOUND CONNECTOR"); - new_recurrence.insert(*N); - } + N != NE; ++N) { + bool found = false; + for(std::vector >::iterator PO = partialOrder.begin(), + PE = partialOrder.end(); PO != PE; ++PO) { + if(PO->count(*N)) + found = true; + } + if(!found) { + assert("FOUND CONNECTOR"); + new_recurrence.insert(*N); + } } partialOrder.push_back(new_recurrence); @@ -1300,15 +1300,15 @@ std::set lastNodes; std::set noPredNodes; for(std::map::iterator I = nodeToAttributesMap.begin(), - E = nodeToAttributesMap.end(); I != E; ++I) { + E = nodeToAttributesMap.end(); I != E; ++I) { bool found = false; //Check if its already in our partial order, if not add it to the final vector for(std::vector >::iterator PO = partialOrder.begin(), - PE = partialOrder.end(); PO != PE; ++PO) { + PE = partialOrder.end(); PO != PE; ++PO) { if(PO->count(I->first)) - found = true; + found = true; } if(!found) lastNodes.insert(I->first); @@ -1320,7 +1320,7 @@ N != NE; ++N) { DEBUG(std::cerr << "No Pred Path from: " << **N << "\n"); for(std::vector >::iterator PO = partialOrder.begin(), - PE = partialOrder.end(); PO != PE; ++PO) { + PE = partialOrder.end(); PO != PE; ++PO) { std::vector path; pathToRecc(*N, path, *PO, lastNodes); } @@ -1333,7 +1333,7 @@ std::set ccSet; connectedComponentSet(*(lastNodes.begin()),ccSet, lastNodes); if(ccSet.size() > 0) - partialOrder.push_back(ccSet); + partialOrder.push_back(ccSet); } } @@ -1356,9 +1356,9 @@ } void ModuloSchedulingSBPass::searchPath(MSchedGraphSBNode *node, - std::vector &path, - std::set &nodesToAdd, - std::set &new_reccurrence) { + std::vector &path, + std::set &nodesToAdd, + std::set &new_reccurrence) { //Push node onto the path path.push_back(node); @@ -1381,11 +1381,11 @@ //final vector bool found = false; for(std::vector >::iterator PO = partialOrder.begin(), - PE = partialOrder.end(); PO != PE; ++PO) { + PE = partialOrder.end(); PO != PE; ++PO) { if(PO->count(*S)) { - found = true; - break; + found = true; + break; } } @@ -1420,8 +1420,8 @@ /*for(std::vector >::iterator CurrentSet = partialOrder.begin(), E= partialOrder.end(); CurrentSet != E; ++CurrentSet) { for(std::set::iterator N = CurrentSet->begin(), NE = CurrentSet->end(); N != NE; ++N) if((*N)->isPredicate()) { - FinalNodeOrder.push_back(*N); - CurrentSet->erase(*N); + FinalNodeOrder.push_back(*N); + CurrentSet->erase(*N); } }*/ @@ -1452,28 +1452,28 @@ //sort top-down if(IntersectCurrent.size() != 0) { - DEBUG(std::cerr << "Final Node Order Successors and Current Set interesection is NOT empty\n"); - order = TOP_DOWN; + DEBUG(std::cerr << "Final Node Order Successors and Current Set interesection is NOT empty\n"); + order = TOP_DOWN; } else { - DEBUG(std::cerr << "Final Node Order Successors and Current Set interesection is empty\n"); - //Find node with max ASAP in current Set - MSchedGraphSBNode *node; - int maxASAP = 0; - DEBUG(std::cerr << "Using current set of size " << CurrentSet->size() << "to find max ASAP\n"); - for(std::set::iterator J = CurrentSet->begin(), JE = CurrentSet->end(); J != JE; ++J) { - //Get node attributes - MSNodeSBAttributes nodeAttr= nodeToAttributesMap.find(*J)->second; - //assert(nodeAttr != nodeToAttributesMap.end() && "Node not in attributes map!"); - - if(maxASAP <= nodeAttr.ASAP) { - maxASAP = nodeAttr.ASAP; - node = *J; - } - } - assert(node != 0 && "In node ordering node should not be null"); - IntersectCurrent.insert(node); - order = BOTTOM_UP; + DEBUG(std::cerr << "Final Node Order Successors and Current Set interesection is empty\n"); + //Find node with max ASAP in current Set + MSchedGraphSBNode *node; + int maxASAP = 0; + DEBUG(std::cerr << "Using current set of size " << CurrentSet->size() << "to find max ASAP\n"); + for(std::set::iterator J = CurrentSet->begin(), JE = CurrentSet->end(); J != JE; ++J) { + //Get node attributes + MSNodeSBAttributes nodeAttr= nodeToAttributesMap.find(*J)->second; + //assert(nodeAttr != nodeToAttributesMap.end() && "Node not in attributes map!"); + + if(maxASAP <= nodeAttr.ASAP) { + maxASAP = nodeAttr.ASAP; + node = *J; + } + } + assert(node != 0 && "In node ordering node should not be null"); + IntersectCurrent.insert(node); + order = BOTTOM_UP; } } @@ -1481,138 +1481,138 @@ while(IntersectCurrent.size() > 0) { if(order == TOP_DOWN) { - DEBUG(std::cerr << "Order is TOP DOWN\n"); + DEBUG(std::cerr << "Order is TOP DOWN\n"); - while(IntersectCurrent.size() > 0) { - DEBUG(std::cerr << "Intersection is not empty, so find heighest height\n"); - - int MOB = 0; - int height = 0; - MSchedGraphSBNode *highestHeightNode = *(IntersectCurrent.begin()); - - //Find node in intersection with highest heigh and lowest MOB - for(std::set::iterator I = IntersectCurrent.begin(), - E = IntersectCurrent.end(); I != E; ++I) { - - //Get current nodes properties - MSNodeSBAttributes nodeAttr= nodeToAttributesMap.find(*I)->second; - - if(height < nodeAttr.height) { - highestHeightNode = *I; - height = nodeAttr.height; - MOB = nodeAttr.MOB; - } - else if(height == nodeAttr.height) { - if(MOB > nodeAttr.height) { - highestHeightNode = *I; - height = nodeAttr.height; - MOB = nodeAttr.MOB; - } - } - } - - //Append our node with greatest height to the NodeOrder - if(std::find(FinalNodeOrder.begin(), FinalNodeOrder.end(), highestHeightNode) == FinalNodeOrder.end()) { - DEBUG(std::cerr << "Adding node to Final Order: " << *highestHeightNode << "\n"); - FinalNodeOrder.push_back(highestHeightNode); - } - - //Remove V from IntersectOrder - IntersectCurrent.erase(std::find(IntersectCurrent.begin(), - IntersectCurrent.end(), highestHeightNode)); - - - //Intersect V's successors with CurrentSet - for(MSchedGraphSBNode::succ_iterator P = highestHeightNode->succ_begin(), - E = highestHeightNode->succ_end(); P != E; ++P) { - //if(lower_bound(CurrentSet->begin(), - // CurrentSet->end(), *P) != CurrentSet->end()) { - if(std::find(CurrentSet->begin(), CurrentSet->end(), *P) != CurrentSet->end()) { - if(ignoreEdge(highestHeightNode, *P)) - continue; - //If not already in Intersect, add - if(!IntersectCurrent.count(*P)) - IntersectCurrent.insert(*P); - } - } - } //End while loop over Intersect Size - - //Change direction - order = BOTTOM_UP; - - //Reset Intersect to reflect changes in OrderNodes - IntersectCurrent.clear(); - predIntersect(*CurrentSet, IntersectCurrent); - + while(IntersectCurrent.size() > 0) { + DEBUG(std::cerr << "Intersection is not empty, so find heighest height\n"); + + int MOB = 0; + int height = 0; + MSchedGraphSBNode *highestHeightNode = *(IntersectCurrent.begin()); + + //Find node in intersection with highest heigh and lowest MOB + for(std::set::iterator I = IntersectCurrent.begin(), + E = IntersectCurrent.end(); I != E; ++I) { + + //Get current nodes properties + MSNodeSBAttributes nodeAttr= nodeToAttributesMap.find(*I)->second; + + if(height < nodeAttr.height) { + highestHeightNode = *I; + height = nodeAttr.height; + MOB = nodeAttr.MOB; + } + else if(height == nodeAttr.height) { + if(MOB > nodeAttr.height) { + highestHeightNode = *I; + height = nodeAttr.height; + MOB = nodeAttr.MOB; + } + } + } + + //Append our node with greatest height to the NodeOrder + if(std::find(FinalNodeOrder.begin(), FinalNodeOrder.end(), highestHeightNode) == FinalNodeOrder.end()) { + DEBUG(std::cerr << "Adding node to Final Order: " << *highestHeightNode << "\n"); + FinalNodeOrder.push_back(highestHeightNode); + } + + //Remove V from IntersectOrder + IntersectCurrent.erase(std::find(IntersectCurrent.begin(), + IntersectCurrent.end(), highestHeightNode)); + + + //Intersect V's successors with CurrentSet + for(MSchedGraphSBNode::succ_iterator P = highestHeightNode->succ_begin(), + E = highestHeightNode->succ_end(); P != E; ++P) { + //if(lower_bound(CurrentSet->begin(), + // CurrentSet->end(), *P) != CurrentSet->end()) { + if(std::find(CurrentSet->begin(), CurrentSet->end(), *P) != CurrentSet->end()) { + if(ignoreEdge(highestHeightNode, *P)) + continue; + //If not already in Intersect, add + if(!IntersectCurrent.count(*P)) + IntersectCurrent.insert(*P); + } + } + } //End while loop over Intersect Size + + //Change direction + order = BOTTOM_UP; + + //Reset Intersect to reflect changes in OrderNodes + IntersectCurrent.clear(); + predIntersect(*CurrentSet, IntersectCurrent); + } //End If TOP_DOWN - - //Begin if BOTTOM_UP + + //Begin if BOTTOM_UP else { - DEBUG(std::cerr << "Order is BOTTOM UP\n"); - while(IntersectCurrent.size() > 0) { - DEBUG(std::cerr << "Intersection of size " << IntersectCurrent.size() << ", finding highest depth\n"); - - //dump intersection - DEBUG(dumpIntersection(IntersectCurrent)); - //Get node with highest depth, if a tie, use one with lowest - //MOB - int MOB = 0; - int depth = 0; - MSchedGraphSBNode *highestDepthNode = *(IntersectCurrent.begin()); - - for(std::set::iterator I = IntersectCurrent.begin(), - E = IntersectCurrent.end(); I != E; ++I) { - //Find node attribute in graph - MSNodeSBAttributes nodeAttr= nodeToAttributesMap.find(*I)->second; - - if(depth < nodeAttr.depth) { - highestDepthNode = *I; - depth = nodeAttr.depth; - MOB = nodeAttr.MOB; - } - else if(depth == nodeAttr.depth) { - if(MOB > nodeAttr.MOB) { - highestDepthNode = *I; - depth = nodeAttr.depth; - MOB = nodeAttr.MOB; - } - } - } - - - - //Append highest depth node to the NodeOrder - if(std::find(FinalNodeOrder.begin(), FinalNodeOrder.end(), highestDepthNode) == FinalNodeOrder.end()) { - DEBUG(std::cerr << "Adding node to Final Order: " << *highestDepthNode << "\n"); - FinalNodeOrder.push_back(highestDepthNode); - } - //Remove heightestDepthNode from IntersectOrder - IntersectCurrent.erase(highestDepthNode); - - - //Intersect heightDepthNode's pred with CurrentSet - for(MSchedGraphSBNode::pred_iterator P = highestDepthNode->pred_begin(), - E = highestDepthNode->pred_end(); P != E; ++P) { - if(CurrentSet->count(*P)) { - if(ignoreEdge(*P, highestDepthNode)) - continue; - - //If not already in Intersect, add - if(!IntersectCurrent.count(*P)) - IntersectCurrent.insert(*P); - } - } - - } //End while loop over Intersect Size - - //Change order - order = TOP_DOWN; - - //Reset IntersectCurrent to reflect changes in OrderNodes - IntersectCurrent.clear(); - succIntersect(*CurrentSet, IntersectCurrent); - } //End if BOTTOM_DOWN - + DEBUG(std::cerr << "Order is BOTTOM UP\n"); + while(IntersectCurrent.size() > 0) { + DEBUG(std::cerr << "Intersection of size " << IntersectCurrent.size() << ", finding highest depth\n"); + + //dump intersection + DEBUG(dumpIntersection(IntersectCurrent)); + //Get node with highest depth, if a tie, use one with lowest + //MOB + int MOB = 0; + int depth = 0; + MSchedGraphSBNode *highestDepthNode = *(IntersectCurrent.begin()); + + for(std::set::iterator I = IntersectCurrent.begin(), + E = IntersectCurrent.end(); I != E; ++I) { + //Find node attribute in graph + MSNodeSBAttributes nodeAttr= nodeToAttributesMap.find(*I)->second; + + if(depth < nodeAttr.depth) { + highestDepthNode = *I; + depth = nodeAttr.depth; + MOB = nodeAttr.MOB; + } + else if(depth == nodeAttr.depth) { + if(MOB > nodeAttr.MOB) { + highestDepthNode = *I; + depth = nodeAttr.depth; + MOB = nodeAttr.MOB; + } + } + } + + + + //Append highest depth node to the NodeOrder + if(std::find(FinalNodeOrder.begin(), FinalNodeOrder.end(), highestDepthNode) == FinalNodeOrder.end()) { + DEBUG(std::cerr << "Adding node to Final Order: " << *highestDepthNode << "\n"); + FinalNodeOrder.push_back(highestDepthNode); + } + //Remove heightestDepthNode from IntersectOrder + IntersectCurrent.erase(highestDepthNode); + + + //Intersect heightDepthNode's pred with CurrentSet + for(MSchedGraphSBNode::pred_iterator P = highestDepthNode->pred_begin(), + E = highestDepthNode->pred_end(); P != E; ++P) { + if(CurrentSet->count(*P)) { + if(ignoreEdge(*P, highestDepthNode)) + continue; + + //If not already in Intersect, add + if(!IntersectCurrent.count(*P)) + IntersectCurrent.insert(*P); + } + } + + } //End while loop over Intersect Size + + //Change order + order = TOP_DOWN; + + //Reset IntersectCurrent to reflect changes in OrderNodes + IntersectCurrent.clear(); + succIntersect(*CurrentSet, IntersectCurrent); + } //End if BOTTOM_DOWN + DEBUG(std::cerr << "Current Intersection Size: " << IntersectCurrent.size() << "\n"); } //End Wrapping while loop @@ -1638,15 +1638,15 @@ for(unsigned j=0; j < FinalNodeOrder.size(); ++j) { for(MSchedGraphSBNode::pred_iterator P = FinalNodeOrder[j]->pred_begin(), - E = FinalNodeOrder[j]->pred_end(); P != E; ++P) { + E = FinalNodeOrder[j]->pred_end(); P != E; ++P) { //Check if we are supposed to ignore this edge or not if(ignoreEdge(*P,FinalNodeOrder[j])) - continue; - + continue; + if(CurrentSet.count(*P)) - if(std::find(FinalNodeOrder.begin(), FinalNodeOrder.end(), *P) == FinalNodeOrder.end()) - IntersectResult.insert(*P); + if(std::find(FinalNodeOrder.begin(), FinalNodeOrder.end(), *P) == FinalNodeOrder.end()) + IntersectResult.insert(*P); } } } @@ -1655,15 +1655,15 @@ for(unsigned j=0; j < FinalNodeOrder.size(); ++j) { for(MSchedGraphSBNode::succ_iterator P = FinalNodeOrder[j]->succ_begin(), - E = FinalNodeOrder[j]->succ_end(); P != E; ++P) { + E = FinalNodeOrder[j]->succ_end(); P != E; ++P) { //Check if we are supposed to ignore this edge or not if(ignoreEdge(FinalNodeOrder[j],*P)) - continue; + continue; if(CurrentSet.count(*P)) - if(std::find(FinalNodeOrder.begin(), FinalNodeOrder.end(), *P) == FinalNodeOrder.end()) - IntersectResult.insert(*P); + if(std::find(FinalNodeOrder.begin(), FinalNodeOrder.end(), *P) == FinalNodeOrder.end()) + IntersectResult.insert(*P); } } } @@ -1687,7 +1687,7 @@ //Loop over the final node order and process each node for(std::vector::iterator I = FinalNodeOrder.begin(), - E = FinalNodeOrder.end(); I != E; ++I) { + E = FinalNodeOrder.end(); I != E; ++I) { //CalculateEarly and Late start bool initialLSVal = false; @@ -1699,59 +1699,59 @@ bool sched; if((*I)->isBranch()) - if((*I)->hasPredecessors()) - sched = true; - else - sched = false; + if((*I)->hasPredecessors()) + sched = true; + else + sched = false; else - sched = true; + sched = true; if(sched) { - //Loop over nodes in the schedule and determine if they are predecessors - //or successors of the node we are trying to schedule - for(MSScheduleSB::schedule_iterator nodesByCycle = schedule.begin(), nodesByCycleEnd = schedule.end(); - nodesByCycle != nodesByCycleEnd; ++nodesByCycle) { - - //For this cycle, get the vector of nodes schedule and loop over it - for(std::vector::iterator schedNode = nodesByCycle->second.begin(), SNE = nodesByCycle->second.end(); schedNode != SNE; ++schedNode) { - - if((*I)->isPredecessor(*schedNode)) { - int diff = (*I)->getInEdge(*schedNode).getIteDiff(); - int ES_Temp = nodesByCycle->first + (*schedNode)->getLatency() - diff * II; - DEBUG(std::cerr << "Diff: " << diff << " Cycle: " << nodesByCycle->first << "\n"); - DEBUG(std::cerr << "Temp EarlyStart: " << ES_Temp << " Prev EarlyStart: " << EarlyStart << "\n"); - if(initialESVal) - EarlyStart = std::max(EarlyStart, ES_Temp); - else { - EarlyStart = ES_Temp; - initialESVal = true; - } - hasPred = true; - } - if((*I)->isSuccessor(*schedNode)) { - int diff = (*schedNode)->getInEdge(*I).getIteDiff(); - int LS_Temp = nodesByCycle->first - (*I)->getLatency() + diff * II; - DEBUG(std::cerr << "Diff: " << diff << " Cycle: " << nodesByCycle->first << "\n"); - DEBUG(std::cerr << "Temp LateStart: " << LS_Temp << " Prev LateStart: " << LateStart << "\n"); - if(initialLSVal) - LateStart = std::min(LateStart, LS_Temp); - else { - LateStart = LS_Temp; - initialLSVal = true; - } - hasSucc = true; - } - } - } + //Loop over nodes in the schedule and determine if they are predecessors + //or successors of the node we are trying to schedule + for(MSScheduleSB::schedule_iterator nodesByCycle = schedule.begin(), nodesByCycleEnd = schedule.end(); + nodesByCycle != nodesByCycleEnd; ++nodesByCycle) { + + //For this cycle, get the vector of nodes schedule and loop over it + for(std::vector::iterator schedNode = nodesByCycle->second.begin(), SNE = nodesByCycle->second.end(); schedNode != SNE; ++schedNode) { + + if((*I)->isPredecessor(*schedNode)) { + int diff = (*I)->getInEdge(*schedNode).getIteDiff(); + int ES_Temp = nodesByCycle->first + (*schedNode)->getLatency() - diff * II; + DEBUG(std::cerr << "Diff: " << diff << " Cycle: " << nodesByCycle->first << "\n"); + DEBUG(std::cerr << "Temp EarlyStart: " << ES_Temp << " Prev EarlyStart: " << EarlyStart << "\n"); + if(initialESVal) + EarlyStart = std::max(EarlyStart, ES_Temp); + else { + EarlyStart = ES_Temp; + initialESVal = true; + } + hasPred = true; + } + if((*I)->isSuccessor(*schedNode)) { + int diff = (*schedNode)->getInEdge(*I).getIteDiff(); + int LS_Temp = nodesByCycle->first - (*I)->getLatency() + diff * II; + DEBUG(std::cerr << "Diff: " << diff << " Cycle: " << nodesByCycle->first << "\n"); + DEBUG(std::cerr << "Temp LateStart: " << LS_Temp << " Prev LateStart: " << LateStart << "\n"); + if(initialLSVal) + LateStart = std::min(LateStart, LS_Temp); + else { + LateStart = LS_Temp; + initialLSVal = true; + } + hasSucc = true; + } + } + } } else { - branches.push_back(*I); - continue; + branches.push_back(*I); + continue; } //Check if the node has no pred or successors and set Early Start to its ASAP if(!hasSucc && !hasPred) - EarlyStart = nodeToAttributesMap.find(*I)->second.ASAP; + EarlyStart = nodeToAttributesMap.find(*I)->second.ASAP; DEBUG(std::cerr << "Has Successors: " << hasSucc << ", Has Pred: " << hasPred << "\n"); DEBUG(std::cerr << "EarlyStart: " << EarlyStart << ", LateStart: " << LateStart << "\n"); @@ -1759,25 +1759,25 @@ //Now, try to schedule this node depending upon its pred and successor in the schedule //already if(!hasSucc && hasPred) - success = scheduleNode(*I, EarlyStart, (EarlyStart + II -1)); + success = scheduleNode(*I, EarlyStart, (EarlyStart + II -1)); else if(!hasPred && hasSucc) - success = scheduleNode(*I, LateStart, (LateStart - II +1)); + success = scheduleNode(*I, LateStart, (LateStart - II +1)); else if(hasPred && hasSucc) { - if(EarlyStart > LateStart) { - success = false; - //LateStart = EarlyStart; - DEBUG(std::cerr << "Early Start can not be later then the late start cycle, schedule fails\n"); - } - else - success = scheduleNode(*I, EarlyStart, std::min(LateStart, (EarlyStart + II -1))); + if(EarlyStart > LateStart) { + success = false; + //LateStart = EarlyStart; + DEBUG(std::cerr << "Early Start can not be later then the late start cycle, schedule fails\n"); + } + else + success = scheduleNode(*I, EarlyStart, std::min(LateStart, (EarlyStart + II -1))); } else - success = scheduleNode(*I, EarlyStart, EarlyStart + II - 1); + success = scheduleNode(*I, EarlyStart, EarlyStart + II - 1); if(!success) { - ++II; - schedule.clear(); - break; + ++II; + schedule.clear(); + break; } } @@ -1787,8 +1787,8 @@ success = schedule.constructKernel(II, branches, indVarInstrs[SB]); DEBUG(std::cerr << "Done Constructing Schedule Kernel\n"); if(!success) { - ++II; - schedule.clear(); + ++II; + schedule.clear(); } DEBUG(std::cerr << "Final II: " << II << "\n"); @@ -1806,7 +1806,7 @@ bool ModuloSchedulingSBPass::scheduleNode(MSchedGraphSBNode *node, - int start, int end) { + int start, int end) { bool success = false; DEBUG(std::cerr << *node << " (Start Cycle: " << start << ", End Cycle: " << end << ")\n"); @@ -1841,13 +1841,13 @@ ++cycle; DEBUG(std::cerr << "Increase cycle: " << cycle << "\n"); if(cycle > end) - return false; + return false; } else { --cycle; DEBUG(std::cerr << "Decrease cycle: " << cycle << "\n"); if(cycle < end) - return false; + return false; } } @@ -1885,46 +1885,46 @@ lastInstrs[inst] = I->second; for(unsigned i=0; i < inst->getNumOperands(); ++i) { - //get machine operand - const MachineOperand &mOp = inst->getOperand(i); - - if(mOp.getType() == MachineOperand::MO_VirtualRegister && mOp.isUse()) { - //find the value in the map - if (const Value* srcI = mOp.getVRegValue()) { - - if(isa(srcI) || isa(srcI)) - continue; - - //Before we declare this Value* one that we should save - //make sure its def is not of the same stage as this instruction - //because it will be consumed before its used - Instruction *defInst = (Instruction*) srcI; - - //Should we save this value? - bool save = true; - - //Continue if not in the def map, loop invariant code does not need to be saved - if(!defMap.count(srcI)) - continue; - - MachineInstr *defInstr = defMap[srcI]; - - - if(lastInstrs.count(defInstr)) { - if(lastInstrs[defInstr] == I->second) { - save = false; - - } - } - - if(save) - valuesToSave[srcI] = std::make_pair(I->first, i); - } - } - - if(mOp.getType() != MachineOperand::MO_VirtualRegister && mOp.isUse()) { - assert("Our assumption is wrong. We have another type of register that needs to be saved\n"); - } + //get machine operand + const MachineOperand &mOp = inst->getOperand(i); + + if(mOp.getType() == MachineOperand::MO_VirtualRegister && mOp.isUse()) { + //find the value in the map + if (const Value* srcI = mOp.getVRegValue()) { + + if(isa(srcI) || isa(srcI)) + continue; + + //Before we declare this Value* one that we should save + //make sure its def is not of the same stage as this instruction + //because it will be consumed before its used + Instruction *defInst = (Instruction*) srcI; + + //Should we save this value? + bool save = true; + + //Continue if not in the def map, loop invariant code does not need to be saved + if(!defMap.count(srcI)) + continue; + + MachineInstr *defInstr = defMap[srcI]; + + + if(lastInstrs.count(defInstr)) { + if(lastInstrs[defInstr] == I->second) { + save = false; + + } + } + + if(save) + valuesToSave[srcI] = std::make_pair(I->first, i); + } + } + + if(mOp.getType() != MachineOperand::MO_VirtualRegister && mOp.isUse()) { + assert("Our assumption is wrong. We have another type of register that needs to be saved\n"); + } } } @@ -1992,10 +1992,10 @@ //Print out epilogues and prologue DEBUG(for(std::vector >::iterator PI = prologues.begin(), PE = prologues.end(); PI != PE; ++PI) { - std::cerr << "PROLOGUE\n"; - for(std::vector::iterator I = PI->begin(), E = PI->end(); I != E; ++I) - (*I)->print(std::cerr); - }); + std::cerr << "PROLOGUE\n"; + for(std::vector::iterator I = PI->begin(), E = PI->end(); I != E; ++I) + (*I)->print(std::cerr); + }); DEBUG(std::cerr << "KERNEL\n"); DEBUG(for(std::vector::iterator I = machineKernelBBs.begin(), E = machineKernelBBs.end(); I != E; ++I) { (*I)->print(std::cerr);}); @@ -2014,10 +2014,10 @@ //Print out epilogues and prologue DEBUG(for(std::vector >::iterator PI = prologues.begin(), PE = prologues.end(); PI != PE; ++PI) { - std::cerr << "PROLOGUE\n"; - for(std::vector::iterator I = PI->begin(), E = PI->end(); I != E; ++I) - (*I)->print(std::cerr); - }); + std::cerr << "PROLOGUE\n"; + for(std::vector::iterator I = PI->begin(), E = PI->end(); I != E; ++I) + (*I)->print(std::cerr); + }); DEBUG(std::cerr << "KERNEL\n"); DEBUG(for(std::vector::iterator I = machineKernelBBs.begin(), E = machineKernelBBs.end(); I != E; ++I) { (*I)->print(std::cerr);}); @@ -2046,7 +2046,7 @@ bool sawFirst = false; for(succ_iterator I = succ_begin(last), - E = succ_end(last); I != E; ++I) { + E = succ_end(last); I != E; ++I) { if (*I != SB[0]->getBasicBlock()) { kernel_exit = *I; break; @@ -2066,71 +2066,71 @@ for(unsigned j = 0; j < prologues[i].size(); ++j) { - MachineBasicBlock *currentMBB = prologues[i][j]; + MachineBasicBlock *currentMBB = prologues[i][j]; - //Find terminator since getFirstTerminator does not work! - for(MachineBasicBlock::reverse_iterator mInst = currentMBB->rbegin(), mInstEnd = currentMBB->rend(); mInst != mInstEnd; ++mInst) { - MachineOpCode OC = mInst->getOpcode(); - //If its a branch update its branchto - if(TMI->isBranch(OC)) { - for(unsigned opNum = 0; opNum < mInst->getNumOperands(); ++opNum) { - MachineOperand &mOp = mInst->getOperand(opNum); - if (mOp.getType() == MachineOperand::MO_PCRelativeDisp) { - //Check if we are branching to the kernel, if not branch to epilogue - if(mOp.getVRegValue() == SB[0]->getBasicBlock()) { - if(i >= prologues.size()-1) - mOp.setValueReg(llvmKernelBB[0]); - else - mOp.setValueReg(llvm_prologues[i+1][0]); - } - else if( (mOp.getVRegValue() == kernel_exit) && (j == prologues[i].size()-1)) { - mOp.setValueReg(llvm_epilogues[i][0]); - } - else if(mOp.getVRegValue() == SB[j+1]->getBasicBlock()) { - mOp.setValueReg(llvm_prologues[i][j+1]); - } - - } - } - - DEBUG(std::cerr << "New Prologue Branch: " << *mInst << "\n"); - } - } - - //Update llvm basic block with our new branch instr - DEBUG(std::cerr << SB[i]->getBasicBlock()->getTerminator() << "\n"); - - const BranchInst *branchVal = dyn_cast(SB[i]->getBasicBlock()->getTerminator()); - - //Check for inner branch - if(j < prologues[i].size()-1) { - //Find our side exit LLVM basic block - BasicBlock *sideExit = 0; - for(unsigned s = 0; s < branchVal->getNumSuccessors(); ++s) { - if(branchVal->getSuccessor(s) != SB[i+1]->getBasicBlock()) - sideExit = branchVal->getSuccessor(s); - } - assert(sideExit && "Must have side exit llvm basic block"); - TerminatorInst *newBranch = new BranchInst(sideExit, - llvm_prologues[i][j+1], - branchVal->getCondition(), - llvm_prologues[i][j]); - } - else { - //If last prologue - if(i == prologues.size()-1) { - TerminatorInst *newBranch = new BranchInst(llvmKernelBB[0], - llvm_epilogues[i][0], - branchVal->getCondition(), - llvm_prologues[i][j]); - } - else { - TerminatorInst *newBranch = new BranchInst(llvm_prologues[i+1][0], - llvm_epilogues[i][0], - branchVal->getCondition(), - llvm_prologues[i][j]); - } - } + //Find terminator since getFirstTerminator does not work! + for(MachineBasicBlock::reverse_iterator mInst = currentMBB->rbegin(), mInstEnd = currentMBB->rend(); mInst != mInstEnd; ++mInst) { + MachineOpCode OC = mInst->getOpcode(); + //If its a branch update its branchto + if(TMI->isBranch(OC)) { + for(unsigned opNum = 0; opNum < mInst->getNumOperands(); ++opNum) { + MachineOperand &mOp = mInst->getOperand(opNum); + if (mOp.getType() == MachineOperand::MO_PCRelativeDisp) { + //Check if we are branching to the kernel, if not branch to epilogue + if(mOp.getVRegValue() == SB[0]->getBasicBlock()) { + if(i >= prologues.size()-1) + mOp.setValueReg(llvmKernelBB[0]); + else + mOp.setValueReg(llvm_prologues[i+1][0]); + } + else if( (mOp.getVRegValue() == kernel_exit) && (j == prologues[i].size()-1)) { + mOp.setValueReg(llvm_epilogues[i][0]); + } + else if(mOp.getVRegValue() == SB[j+1]->getBasicBlock()) { + mOp.setValueReg(llvm_prologues[i][j+1]); + } + + } + } + + DEBUG(std::cerr << "New Prologue Branch: " << *mInst << "\n"); + } + } + + //Update llvm basic block with our new branch instr + DEBUG(std::cerr << SB[i]->getBasicBlock()->getTerminator() << "\n"); + + const BranchInst *branchVal = dyn_cast(SB[i]->getBasicBlock()->getTerminator()); + + //Check for inner branch + if(j < prologues[i].size()-1) { + //Find our side exit LLVM basic block + BasicBlock *sideExit = 0; + for(unsigned s = 0; s < branchVal->getNumSuccessors(); ++s) { + if(branchVal->getSuccessor(s) != SB[i+1]->getBasicBlock()) + sideExit = branchVal->getSuccessor(s); + } + assert(sideExit && "Must have side exit llvm basic block"); + TerminatorInst *newBranch = new BranchInst(sideExit, + llvm_prologues[i][j+1], + branchVal->getCondition(), + llvm_prologues[i][j]); + } + else { + //If last prologue + if(i == prologues.size()-1) { + TerminatorInst *newBranch = new BranchInst(llvmKernelBB[0], + llvm_epilogues[i][0], + branchVal->getCondition(), + llvm_prologues[i][j]); + } + else { + TerminatorInst *newBranch = new BranchInst(llvm_prologues[i+1][0], + llvm_epilogues[i][0], + branchVal->getCondition(), + llvm_prologues[i][j]); + } + } } } } @@ -2142,29 +2142,29 @@ for(MachineBasicBlock::reverse_iterator mInst = currentMBB->rbegin(), mInstEnd = currentMBB->rend(); mInst != mInstEnd; ++mInst) { MachineOpCode OC = mInst->getOpcode(); if(TMI->isBranch(OC)) { - for(unsigned opNum = 0; opNum < mInst->getNumOperands(); ++opNum) { - MachineOperand &mOp = mInst->getOperand(opNum); - - if(mOp.getType() == MachineOperand::MO_PCRelativeDisp) { - //Deal with inner kernel branches - if(i < machineKernelBB.size()-1) { - if(mOp.getVRegValue() == SB[i+1]->getBasicBlock()) - mOp.setValueReg(llvmKernelBB[i+1]); - //Side exit! - else { - sideExits[SB[i]] = mOp.getVRegValue(); - } - } - else { - if(mOp.getVRegValue() == SB[0]->getBasicBlock()) - mOp.setValueReg(llvmKernelBB[0]); - else { - if(llvm_epilogues.size() > 0) - mOp.setValueReg(llvm_epilogues[0][0]); - } - } - } - } + for(unsigned opNum = 0; opNum < mInst->getNumOperands(); ++opNum) { + MachineOperand &mOp = mInst->getOperand(opNum); + + if(mOp.getType() == MachineOperand::MO_PCRelativeDisp) { + //Deal with inner kernel branches + if(i < machineKernelBB.size()-1) { + if(mOp.getVRegValue() == SB[i+1]->getBasicBlock()) + mOp.setValueReg(llvmKernelBB[i+1]); + //Side exit! + else { + sideExits[SB[i]] = mOp.getVRegValue(); + } + } + else { + if(mOp.getVRegValue() == SB[0]->getBasicBlock()) + mOp.setValueReg(llvmKernelBB[0]); + else { + if(llvm_epilogues.size() > 0) + mOp.setValueReg(llvm_epilogues[0][0]); + } + } + } + } } } @@ -2177,28 +2177,28 @@ //Find our side exit LLVM basic block BasicBlock *sideExit = 0; for(unsigned s = 0; s < branchVal->getNumSuccessors(); ++s) { - if(branchVal->getSuccessor(s) != SB[i+1]->getBasicBlock()) - sideExit = branchVal->getSuccessor(s); + if(branchVal->getSuccessor(s) != SB[i+1]->getBasicBlock()) + sideExit = branchVal->getSuccessor(s); } assert(sideExit && "Must have side exit llvm basic block"); TerminatorInst *newBranch = new BranchInst(sideExit, - llvmKernelBB[i+1], - branchVal->getCondition(), - llvmKernelBB[i]); + llvmKernelBB[i+1], + branchVal->getCondition(), + llvmKernelBB[i]); } else { //Deal with outter branches if(epilogues.size() > 0) { - TerminatorInst *newBranch = new BranchInst(llvmKernelBB[0], - llvm_epilogues[0][0], - branchVal->getCondition(), - llvmKernelBB[i]); + TerminatorInst *newBranch = new BranchInst(llvmKernelBB[0], + llvm_epilogues[0][0], + branchVal->getCondition(), + llvmKernelBB[i]); } else { - TerminatorInst *newBranch = new BranchInst(llvmKernelBB[0], - kernel_exit, - branchVal->getCondition(), - llvmKernelBB[i]); + TerminatorInst *newBranch = new BranchInst(llvmKernelBB[0], + kernel_exit, + branchVal->getCondition(), + llvmKernelBB[i]); } } } @@ -2209,73 +2209,73 @@ for(unsigned i = 0; i < epilogues.size(); ++i) { for(unsigned j=0; j < epilogues[i].size(); ++j) { - //Now since we don't have fall throughs, add a unconditional - //branch to the next prologue - - //Before adding these, we need to check if the epilogue already has - //a branch in it - bool hasBranch = false; - /*if(j < epilogues[i].size()-1) { - MachineBasicBlock *currentMBB = epilogues[i][j]; - for(MachineBasicBlock::reverse_iterator mInst = currentMBB->rbegin(), mInstEnd = currentMBB->rend(); mInst != mInstEnd; ++mInst) { - - MachineOpCode OC = mInst->getOpcode(); - - //If its a branch update its branchto - if(TMI->isBranch(OC)) { - hasBranch = true; - for(unsigned opNum = 0; opNum < mInst->getNumOperands(); ++opNum) { - MachineOperand &mOp = mInst->getOperand(opNum); - if (mOp.getType() == MachineOperand::MO_PCRelativeDisp) { - - if(mOp.getVRegValue() != sideExits[SB[j]]) { - mOp.setValueReg(llvm_epilogues[i][j+1]); - } - - } - } - - - DEBUG(std::cerr << "New Epilogue Branch: " << *mInst << "\n"); - } - } - if(hasBranch) { - const BranchInst *branchVal = dyn_cast(SB[j]->getBasicBlock()->getTerminator()); - TerminatorInst *newBranch = new BranchInst((BasicBlock*)sideExits[SB[j]], - llvm_epilogues[i][j+1], - branchVal->getCondition(), - llvm_epilogues[i][j]); - } - }*/ - - if(!hasBranch) { - - //Handle inner branches - if(j < epilogues[i].size()-1) { - BuildMI(epilogues[i][j], V9::BA, 1).addPCDisp(llvm_epilogues[i][j+1]); - TerminatorInst *newBranch = new BranchInst(llvm_epilogues[i][j+1], - llvm_epilogues[i][j]); - } - else { - - //Check if this is the last epilogue - if(i != epilogues.size()-1) { - BuildMI(epilogues[i][j], V9::BA, 1).addPCDisp(llvm_epilogues[i+1][0]); - //Add unconditional branch to end of epilogue - TerminatorInst *newBranch = new BranchInst(llvm_epilogues[i+1][0], - llvm_epilogues[i][j]); - - } - else { - BuildMI(epilogues[i][j], V9::BA, 1).addPCDisp(kernel_exit); - TerminatorInst *newBranch = new BranchInst(kernel_exit, llvm_epilogues[i][j]); - } - } - - //Add one more nop! - BuildMI(epilogues[i][j], V9::NOP, 0); - - } + //Now since we don't have fall throughs, add a unconditional + //branch to the next prologue + + //Before adding these, we need to check if the epilogue already has + //a branch in it + bool hasBranch = false; + /*if(j < epilogues[i].size()-1) { + MachineBasicBlock *currentMBB = epilogues[i][j]; + for(MachineBasicBlock::reverse_iterator mInst = currentMBB->rbegin(), mInstEnd = currentMBB->rend(); mInst != mInstEnd; ++mInst) { + + MachineOpCode OC = mInst->getOpcode(); + + //If its a branch update its branchto + if(TMI->isBranch(OC)) { + hasBranch = true; + for(unsigned opNum = 0; opNum < mInst->getNumOperands(); ++opNum) { + MachineOperand &mOp = mInst->getOperand(opNum); + if (mOp.getType() == MachineOperand::MO_PCRelativeDisp) { + + if(mOp.getVRegValue() != sideExits[SB[j]]) { + mOp.setValueReg(llvm_epilogues[i][j+1]); + } + + } + } + + + DEBUG(std::cerr << "New Epilogue Branch: " << *mInst << "\n"); + } + } + if(hasBranch) { + const BranchInst *branchVal = dyn_cast(SB[j]->getBasicBlock()->getTerminator()); + TerminatorInst *newBranch = new BranchInst((BasicBlock*)sideExits[SB[j]], + llvm_epilogues[i][j+1], + branchVal->getCondition(), + llvm_epilogues[i][j]); + } + }*/ + + if(!hasBranch) { + + //Handle inner branches + if(j < epilogues[i].size()-1) { + BuildMI(epilogues[i][j], V9::BA, 1).addPCDisp(llvm_epilogues[i][j+1]); + TerminatorInst *newBranch = new BranchInst(llvm_epilogues[i][j+1], + llvm_epilogues[i][j]); + } + else { + + //Check if this is the last epilogue + if(i != epilogues.size()-1) { + BuildMI(epilogues[i][j], V9::BA, 1).addPCDisp(llvm_epilogues[i+1][0]); + //Add unconditional branch to end of epilogue + TerminatorInst *newBranch = new BranchInst(llvm_epilogues[i+1][0], + llvm_epilogues[i][j]); + + } + else { + BuildMI(epilogues[i][j], V9::BA, 1).addPCDisp(kernel_exit); + TerminatorInst *newBranch = new BranchInst(kernel_exit, llvm_epilogues[i][j]); + } + } + + //Add one more nop! + BuildMI(epilogues[i][j], V9::NOP, 0); + + } } } } @@ -2287,7 +2287,7 @@ std::vectorPreds (pred_begin(llvmBB), pred_end(llvmBB)); for(std::vector::iterator P = Preds.begin(), - PE = Preds.end(); P != PE; ++P) { + PE = Preds.end(); P != PE; ++P) { if(*P == SB[SB.size()-1]->getBasicBlock()) continue; else { @@ -2299,55 +2299,55 @@ //Update the terminator TerminatorInst *term = ((BasicBlock*)*P)->getTerminator(); for(unsigned i=0; i < term->getNumSuccessors(); ++i) { - if(term->getSuccessor(i) == llvmBB) { - DEBUG(std::cerr << "Replacing successor bb\n"); - if(llvm_prologues.size() > 0) { - term->setSuccessor(i, llvm_prologues[0][0]); - - DEBUG(std::cerr << "New Term" << *((*P)->getTerminator()) << "\n"); - - //Also update its corresponding machine instruction - MachineCodeForInstruction & tempMvec = - MachineCodeForInstruction::get(term); - for (unsigned j = 0; j < tempMvec.size(); j++) { - MachineInstr *temp = tempMvec[j]; - MachineOpCode opc = temp->getOpcode(); - if(TMI->isBranch(opc)) { - DEBUG(std::cerr << *temp << "\n"); - //Update branch - for(unsigned opNum = 0; opNum < temp->getNumOperands(); ++opNum) { - MachineOperand &mOp = temp->getOperand(opNum); - if (mOp.getType() == MachineOperand::MO_PCRelativeDisp) { - if(mOp.getVRegValue() == llvmBB) - mOp.setValueReg(llvm_prologues[0][0]); - } - } - } - } - } - else { - term->setSuccessor(i, llvmKernelBB[0]); - - //Also update its corresponding machine instruction - MachineCodeForInstruction & tempMvec = - MachineCodeForInstruction::get(term); - for(unsigned j = 0; j < tempMvec.size(); j++) { - MachineInstr *temp = tempMvec[j]; - MachineOpCode opc = temp->getOpcode(); - if(TMI->isBranch(opc)) { - DEBUG(std::cerr << *temp << "\n"); - //Update branch - for(unsigned opNum = 0; opNum < temp->getNumOperands(); ++opNum) { - MachineOperand &mOp = temp->getOperand(opNum); - if(mOp.getType() == MachineOperand::MO_PCRelativeDisp) { - if(mOp.getVRegValue() == llvmBB) - mOp.setValueReg(llvmKernelBB[0]); - } - } - } - } - } - } + if(term->getSuccessor(i) == llvmBB) { + DEBUG(std::cerr << "Replacing successor bb\n"); + if(llvm_prologues.size() > 0) { + term->setSuccessor(i, llvm_prologues[0][0]); + + DEBUG(std::cerr << "New Term" << *((*P)->getTerminator()) << "\n"); + + //Also update its corresponding machine instruction + MachineCodeForInstruction & tempMvec = + MachineCodeForInstruction::get(term); + for (unsigned j = 0; j < tempMvec.size(); j++) { + MachineInstr *temp = tempMvec[j]; + MachineOpCode opc = temp->getOpcode(); + if(TMI->isBranch(opc)) { + DEBUG(std::cerr << *temp << "\n"); + //Update branch + for(unsigned opNum = 0; opNum < temp->getNumOperands(); ++opNum) { + MachineOperand &mOp = temp->getOperand(opNum); + if (mOp.getType() == MachineOperand::MO_PCRelativeDisp) { + if(mOp.getVRegValue() == llvmBB) + mOp.setValueReg(llvm_prologues[0][0]); + } + } + } + } + } + else { + term->setSuccessor(i, llvmKernelBB[0]); + + //Also update its corresponding machine instruction + MachineCodeForInstruction & tempMvec = + MachineCodeForInstruction::get(term); + for(unsigned j = 0; j < tempMvec.size(); j++) { + MachineInstr *temp = tempMvec[j]; + MachineOpCode opc = temp->getOpcode(); + if(TMI->isBranch(opc)) { + DEBUG(std::cerr << *temp << "\n"); + //Update branch + for(unsigned opNum = 0; opNum < temp->getNumOperands(); ++opNum) { + MachineOperand &mOp = temp->getOperand(opNum); + if(mOp.getType() == MachineOperand::MO_PCRelativeDisp) { + if(mOp.getVRegValue() == llvmBB) + mOp.setValueReg(llvmKernelBB[0]); + } + } + } + } + } + } } break; } @@ -2384,7 +2384,7 @@ std::vector current_llvm_prologue; for(std::vector::iterator MB = origSB.begin(), - MBE = origSB.end(); MB != MBE; ++MB) { + MBE = origSB.end(); MB != MBE; ++MB) { const MachineBasicBlock *MBB = *MB; //Create new llvm and machine bb BasicBlock *llvmBB = new BasicBlock("PROLOGUE", (Function*) (MBB->getBasicBlock()->getParent())); @@ -2393,91 +2393,91 @@ DEBUG(std::cerr << "i=" << i << "\n"); for(int j = i; j >= 0; --j) { - //iterate over instructions in original bb - for(MachineBasicBlock::const_iterator MI = MBB->begin(), - ME = MBB->end(); ME != MI; ++MI) { - if(inKernel[j].count(&*MI)) { - MachineInstr *instClone = MI->clone(); - machineBB->push_back(instClone); - - //If its a branch, insert a nop - if(mii->isBranch(instClone->getOpcode())) - BuildMI(machineBB, V9::NOP, 0); - - - DEBUG(std::cerr << "Cloning: " << *MI << "\n"); - - //After cloning, we may need to save the value that this instruction defines - for(unsigned opNum=0; opNum < MI->getNumOperands(); ++opNum) { - Instruction *tmp; - - //get machine operand - MachineOperand &mOp = instClone->getOperand(opNum); - if(mOp.getType() == MachineOperand::MO_VirtualRegister - && mOp.isDef()) { - - //Check if this is a value we should save - if(valuesToSave.count(mOp.getVRegValue())) { - //Save copy in tmpInstruction - tmp = new TmpInstruction(mOp.getVRegValue()); - - //Add TmpInstruction to safe LLVM Instruction MCFI - MachineCodeForInstruction & tempMvec = MachineCodeForInstruction::get(defaultInst); - tempMvec.addTemp((Value*) tmp); - - DEBUG(std::cerr << "Value: " << *(mOp.getVRegValue()) - << " New Value: " << *tmp << " Stage: " << i << "\n"); - - newValues[mOp.getVRegValue()][i]= tmp; - newValLocation[tmp] = machineBB; - - DEBUG(std::cerr << "Machine Instr Operands: " - << *(mOp.getVRegValue()) << ", 0, " << *tmp << "\n"); - - //Create machine instruction and put int machineBB - MachineInstr *saveValue; - if(mOp.getVRegValue()->getType() == Type::FloatTy) - saveValue = BuildMI(machineBB, V9::FMOVS, 3).addReg(mOp.getVRegValue()).addRegDef(tmp); - else if(mOp.getVRegValue()->getType() == Type::DoubleTy) - saveValue = BuildMI(machineBB, V9::FMOVD, 3).addReg(mOp.getVRegValue()).addRegDef(tmp); - else - saveValue = BuildMI(machineBB, V9::ORr, 3).addReg(mOp.getVRegValue()).addImm(0).addRegDef(tmp); - - - DEBUG(std::cerr << "Created new machine instr: " << *saveValue << "\n"); - } - } - - //We may also need to update the value that we use if - //its from an earlier prologue - if(j != 0) { - if(mOp.getType() == MachineOperand::MO_VirtualRegister && mOp.isUse()) { - if(newValues.count(mOp.getVRegValue())) { - if(newValues[mOp.getVRegValue()].count(i-1)) { - Value *oldV = mOp.getVRegValue(); - DEBUG(std::cerr << "Replaced this value: " << mOp.getVRegValue() << " With:" << (newValues[mOp.getVRegValue()][i-1]) << "\n"); - //Update the operand with the right value - mOp.setValueReg(newValues[mOp.getVRegValue()][i-1]); - - //Remove this value since we have consumed it - //NOTE: Should this only be done if j != maxStage? - consumedValues[oldV][i-1] = (newValues[oldV][i-1]); - DEBUG(std::cerr << "Deleted value: " << consumedValues[oldV][i-1] << "\n"); - newValues[oldV].erase(i-1); - } - } - else - if(consumedValues.count(mOp.getVRegValue())) - assert(!consumedValues[mOp.getVRegValue()].count(i-1) && "Found a case where we need the value"); - } - } - } - } - } - } - (((MachineBasicBlock*)MBB)->getParent())->getBasicBlockList().push_back(machineBB); - current_prologue.push_back(machineBB); - current_llvm_prologue.push_back(llvmBB); + //iterate over instructions in original bb + for(MachineBasicBlock::const_iterator MI = MBB->begin(), + ME = MBB->end(); ME != MI; ++MI) { + if(inKernel[j].count(&*MI)) { + MachineInstr *instClone = MI->clone(); + machineBB->push_back(instClone); + + //If its a branch, insert a nop + if(mii->isBranch(instClone->getOpcode())) + BuildMI(machineBB, V9::NOP, 0); + + + DEBUG(std::cerr << "Cloning: " << *MI << "\n"); + + //After cloning, we may need to save the value that this instruction defines + for(unsigned opNum=0; opNum < MI->getNumOperands(); ++opNum) { + Instruction *tmp; + + //get machine operand + MachineOperand &mOp = instClone->getOperand(opNum); + if(mOp.getType() == MachineOperand::MO_VirtualRegister + && mOp.isDef()) { + + //Check if this is a value we should save + if(valuesToSave.count(mOp.getVRegValue())) { + //Save copy in tmpInstruction + tmp = new TmpInstruction(mOp.getVRegValue()); + + //Add TmpInstruction to safe LLVM Instruction MCFI + MachineCodeForInstruction & tempMvec = MachineCodeForInstruction::get(defaultInst); + tempMvec.addTemp((Value*) tmp); + + DEBUG(std::cerr << "Value: " << *(mOp.getVRegValue()) + << " New Value: " << *tmp << " Stage: " << i << "\n"); + + newValues[mOp.getVRegValue()][i]= tmp; + newValLocation[tmp] = machineBB; + + DEBUG(std::cerr << "Machine Instr Operands: " + << *(mOp.getVRegValue()) << ", 0, " << *tmp << "\n"); + + //Create machine instruction and put int machineBB + MachineInstr *saveValue; + if(mOp.getVRegValue()->getType() == Type::FloatTy) + saveValue = BuildMI(machineBB, V9::FMOVS, 3).addReg(mOp.getVRegValue()).addRegDef(tmp); + else if(mOp.getVRegValue()->getType() == Type::DoubleTy) + saveValue = BuildMI(machineBB, V9::FMOVD, 3).addReg(mOp.getVRegValue()).addRegDef(tmp); + else + saveValue = BuildMI(machineBB, V9::ORr, 3).addReg(mOp.getVRegValue()).addImm(0).addRegDef(tmp); + + + DEBUG(std::cerr << "Created new machine instr: " << *saveValue << "\n"); + } + } + + //We may also need to update the value that we use if + //its from an earlier prologue + if(j != 0) { + if(mOp.getType() == MachineOperand::MO_VirtualRegister && mOp.isUse()) { + if(newValues.count(mOp.getVRegValue())) { + if(newValues[mOp.getVRegValue()].count(i-1)) { + Value *oldV = mOp.getVRegValue(); + DEBUG(std::cerr << "Replaced this value: " << mOp.getVRegValue() << " With:" << (newValues[mOp.getVRegValue()][i-1]) << "\n"); + //Update the operand with the right value + mOp.setValueReg(newValues[mOp.getVRegValue()][i-1]); + + //Remove this value since we have consumed it + //NOTE: Should this only be done if j != maxStage? + consumedValues[oldV][i-1] = (newValues[oldV][i-1]); + DEBUG(std::cerr << "Deleted value: " << consumedValues[oldV][i-1] << "\n"); + newValues[oldV].erase(i-1); + } + } + else + if(consumedValues.count(mOp.getVRegValue())) + assert(!consumedValues[mOp.getVRegValue()].count(i-1) && "Found a case where we need the value"); + } + } + } + } + } + } + (((MachineBasicBlock*)MBB)->getParent())->getBasicBlockList().push_back(machineBB); + current_prologue.push_back(machineBB); + current_llvm_prologue.push_back(llvmBB); } prologues.push_back(current_prologue); llvm_prologues.push_back(current_llvm_prologue); @@ -2523,58 +2523,58 @@ std::map inEpilogue; for(MachineBasicBlock::const_iterator MI = MBB->begin(), ME = MBB->end(); ME != MI; ++MI) { - for(int j=schedule.getMaxStage(); j > i; --j) { - if(inKernel[j].count(&*MI)) { - DEBUG(std::cerr << "Cloning instruction " << *MI << "\n"); - MachineInstr *clone = MI->clone(); - - //Update operands that need to use the result from the phi - for(unsigned opNum=0; opNum < clone->getNumOperands(); ++opNum) { - //get machine operand - const MachineOperand &mOp = clone->getOperand(opNum); - - if((mOp.getType() == MachineOperand::MO_VirtualRegister && mOp.isUse())) { - - DEBUG(std::cerr << "Writing PHI for " << (mOp.getVRegValue()) << "\n"); - - //If this is the last instructions for the max iterations ago, don't update operands - if(inEpilogue.count(mOp.getVRegValue())) - if(inEpilogue[mOp.getVRegValue()] == i) - continue; - - //Quickly write appropriate phis for this operand - if(newValues.count(mOp.getVRegValue())) { - if(newValues[mOp.getVRegValue()].count(i)) { - Instruction *tmp = new TmpInstruction(newValues[mOp.getVRegValue()][i]); - - //Get machine code for this instruction - MachineCodeForInstruction & tempMvec = MachineCodeForInstruction::get(defaultInst); - tempMvec.addTemp((Value*) tmp); - - //assert of no kernelPHI for this value - assert(kernelPHIs[mOp.getVRegValue()][i] !=0 && "Must have final kernel phi to construct epilogue phi"); - - MachineInstr *saveValue = BuildMI(machineBB, V9::PHI, 3).addReg(newValues[mOp.getVRegValue()][i]).addReg(kernelPHIs[mOp.getVRegValue()][i]).addRegDef(tmp); - DEBUG(std::cerr << "Resulting PHI: " << *saveValue << "\n"); - valPHIs[mOp.getVRegValue()] = tmp; - } - } - - if(valPHIs.count(mOp.getVRegValue())) { - //Update the operand in the cloned instruction - clone->getOperand(opNum).setValueReg(valPHIs[mOp.getVRegValue()]); - } - } - else if((mOp.getType() == MachineOperand::MO_VirtualRegister && mOp.isDef())) { - inEpilogue[mOp.getVRegValue()] = i; - } - - } - machineBB->push_back(clone); - //if(MTI->isBranch(clone->getOpcode())) - //BuildMI(machineBB, V9::NOP, 0); - } - } + for(int j=schedule.getMaxStage(); j > i; --j) { + if(inKernel[j].count(&*MI)) { + DEBUG(std::cerr << "Cloning instruction " << *MI << "\n"); + MachineInstr *clone = MI->clone(); + + //Update operands that need to use the result from the phi + for(unsigned opNum=0; opNum < clone->getNumOperands(); ++opNum) { + //get machine operand + const MachineOperand &mOp = clone->getOperand(opNum); + + if((mOp.getType() == MachineOperand::MO_VirtualRegister && mOp.isUse())) { + + DEBUG(std::cerr << "Writing PHI for " << (mOp.getVRegValue()) << "\n"); + + //If this is the last instructions for the max iterations ago, don't update operands + if(inEpilogue.count(mOp.getVRegValue())) + if(inEpilogue[mOp.getVRegValue()] == i) + continue; + + //Quickly write appropriate phis for this operand + if(newValues.count(mOp.getVRegValue())) { + if(newValues[mOp.getVRegValue()].count(i)) { + Instruction *tmp = new TmpInstruction(newValues[mOp.getVRegValue()][i]); + + //Get machine code for this instruction + MachineCodeForInstruction & tempMvec = MachineCodeForInstruction::get(defaultInst); + tempMvec.addTemp((Value*) tmp); + + //assert of no kernelPHI for this value + assert(kernelPHIs[mOp.getVRegValue()][i] !=0 && "Must have final kernel phi to construct epilogue phi"); + + MachineInstr *saveValue = BuildMI(machineBB, V9::PHI, 3).addReg(newValues[mOp.getVRegValue()][i]).addReg(kernelPHIs[mOp.getVRegValue()][i]).addRegDef(tmp); + DEBUG(std::cerr << "Resulting PHI: " << *saveValue << "\n"); + valPHIs[mOp.getVRegValue()] = tmp; + } + } + + if(valPHIs.count(mOp.getVRegValue())) { + //Update the operand in the cloned instruction + clone->getOperand(opNum).setValueReg(valPHIs[mOp.getVRegValue()]); + } + } + else if((mOp.getType() == MachineOperand::MO_VirtualRegister && mOp.isDef())) { + inEpilogue[mOp.getVRegValue()] = i; + } + + } + machineBB->push_back(clone); + //if(MTI->isBranch(clone->getOpcode())) + //BuildMI(machineBB, V9::NOP, 0); + } + } } (((MachineBasicBlock*)MBB)->getParent())->getBasicBlockList().push_back(machineBB); current_epilogue.push_back(machineBB); @@ -2583,7 +2583,7 @@ DEBUG(std::cerr << "EPILOGUE #" << i << "\n"); DEBUG(for(std::vector::iterator B = current_epilogue.begin(), BE = current_epilogue.end(); B != BE; ++B) { - (*B)->print(std::cerr);}); + (*B)->print(std::cerr);}); epilogues.push_back(current_epilogue); llvm_epilogues.push_back(current_llvm_epilogue); @@ -2646,64 +2646,64 @@ if(I->second != 0) { if(mOp.getType() == MachineOperand::MO_VirtualRegister && mOp.isUse()) { - //Check to see where this operand is defined if this instruction is from max stage - if(I->second == schedule.getMaxStage()) { - DEBUG(std::cerr << "VREG: " << *(mOp.getVRegValue()) << "\n"); - } - - //If its in the value saved, we need to create a temp instruction and use that instead - if(valuesToSave.count(mOp.getVRegValue())) { - - //Check if we already have a final PHI value for this - if(!finalPHIValue.count(mOp.getVRegValue())) { - //Only create phi if the operand def is from a stage before this one - if(schedule.defPreviousStage(mOp.getVRegValue(), I->second)) { - TmpInstruction *tmp = new TmpInstruction(mOp.getVRegValue()); - - //Get machine code for this instruction - MachineCodeForInstruction & tempMvec = MachineCodeForInstruction::get(defaultInst); - tempMvec.addTemp((Value*) tmp); - - //Update the operand in the cloned instruction - instClone->getOperand(i).setValueReg(tmp); - - //save this as our final phi - finalPHIValue[mOp.getVRegValue()] = tmp; - newValLocation[tmp] = machineBB[index]; - } - } - else { - //Use the previous final phi value - instClone->getOperand(i).setValueReg(finalPHIValue[mOp.getVRegValue()]); - } - } + //Check to see where this operand is defined if this instruction is from max stage + if(I->second == schedule.getMaxStage()) { + DEBUG(std::cerr << "VREG: " << *(mOp.getVRegValue()) << "\n"); + } + + //If its in the value saved, we need to create a temp instruction and use that instead + if(valuesToSave.count(mOp.getVRegValue())) { + + //Check if we already have a final PHI value for this + if(!finalPHIValue.count(mOp.getVRegValue())) { + //Only create phi if the operand def is from a stage before this one + if(schedule.defPreviousStage(mOp.getVRegValue(), I->second)) { + TmpInstruction *tmp = new TmpInstruction(mOp.getVRegValue()); + + //Get machine code for this instruction + MachineCodeForInstruction & tempMvec = MachineCodeForInstruction::get(defaultInst); + tempMvec.addTemp((Value*) tmp); + + //Update the operand in the cloned instruction + instClone->getOperand(i).setValueReg(tmp); + + //save this as our final phi + finalPHIValue[mOp.getVRegValue()] = tmp; + newValLocation[tmp] = machineBB[index]; + } + } + else { + //Use the previous final phi value + instClone->getOperand(i).setValueReg(finalPHIValue[mOp.getVRegValue()]); + } + } } } if(I->second != schedule.getMaxStage()) { if(mOp.getType() == MachineOperand::MO_VirtualRegister && mOp.isDef()) { - if(valuesToSave.count(mOp.getVRegValue())) { - - TmpInstruction *tmp = new TmpInstruction(mOp.getVRegValue()); - - //Get machine code for this instruction - MachineCodeForInstruction & tempVec = MachineCodeForInstruction::get(defaultInst); - tempVec.addTemp((Value*) tmp); - - //Create new machine instr and put in MBB - MachineInstr *saveValue; - if(mOp.getVRegValue()->getType() == Type::FloatTy) - saveValue = BuildMI(machineBB[index], V9::FMOVS, 3).addReg(mOp.getVRegValue()).addRegDef(tmp); - else if(mOp.getVRegValue()->getType() == Type::DoubleTy) - saveValue = BuildMI(machineBB[index], V9::FMOVD, 3).addReg(mOp.getVRegValue()).addRegDef(tmp); - else - saveValue = BuildMI(machineBB[index], V9::ORr, 3).addReg(mOp.getVRegValue()).addImm(0).addRegDef(tmp); - - - //Save for future cleanup - kernelValue[mOp.getVRegValue()] = tmp; - newValLocation[tmp] = machineBB[index]; - kernelPHIs[mOp.getVRegValue()][schedule.getMaxStage()-1] = tmp; - } + if(valuesToSave.count(mOp.getVRegValue())) { + + TmpInstruction *tmp = new TmpInstruction(mOp.getVRegValue()); + + //Get machine code for this instruction + MachineCodeForInstruction & tempVec = MachineCodeForInstruction::get(defaultInst); + tempVec.addTemp((Value*) tmp); + + //Create new machine instr and put in MBB + MachineInstr *saveValue; + if(mOp.getVRegValue()->getType() == Type::FloatTy) + saveValue = BuildMI(machineBB[index], V9::FMOVS, 3).addReg(mOp.getVRegValue()).addRegDef(tmp); + else if(mOp.getVRegValue()->getType() == Type::DoubleTy) + saveValue = BuildMI(machineBB[index], V9::FMOVD, 3).addReg(mOp.getVRegValue()).addRegDef(tmp); + else + saveValue = BuildMI(machineBB[index], V9::ORr, 3).addReg(mOp.getVRegValue()).addImm(0).addRegDef(tmp); + + + //Save for future cleanup + kernelValue[mOp.getVRegValue()] = tmp; + newValLocation[tmp] = machineBB[index]; + kernelPHIs[mOp.getVRegValue()][schedule.getMaxStage()-1] = tmp; + } } } } @@ -2718,7 +2718,7 @@ DEBUG(std::cerr << "Writing phi for" << *(V->first)); DEBUG(std::cerr << "\nMap of Value* for this phi\n"); DEBUG(for(std::map::iterator I = V->second.begin(), - IE = V->second.end(); I != IE; ++I) { + IE = V->second.end(); I != IE; ++I) { std::cerr << "Stage: " << I->first; std::cerr << " Value: " << *(I->second) << "\n"; }); @@ -2740,42 +2740,42 @@ unsigned count = 1; //Loop over the the map backwards to generate phis for(std::map::reverse_iterator I = V->second.rbegin(), IE = V->second.rend(); - I != IE; ++I) { + I != IE; ++I) { if(count < (V->second).size()) { - if(lastPhi == 0) { - lastPhi = new TmpInstruction(I->second); + if(lastPhi == 0) { + lastPhi = new TmpInstruction(I->second); - //Get machine code for this instruction - MachineCodeForInstruction & tempMvec = MachineCodeForInstruction::get(defaultInst); - tempMvec.addTemp((Value*) lastPhi); - - MachineInstr *saveValue = BuildMI(*machineBB[0], machineBB[0]->begin(), V9::PHI, 3).addReg(kernelValue[V->first]).addReg(I->second).addRegDef(lastPhi); - DEBUG(std::cerr << "Resulting PHI: " << *saveValue << "\n"); - newValLocation[lastPhi] = machineBB[0]; - } - else { - Instruction *tmp = new TmpInstruction(I->second); - - //Get machine code for this instruction - MachineCodeForInstruction & tempMvec = MachineCodeForInstruction::get(defaultInst); - tempMvec.addTemp((Value*) tmp); - - - MachineInstr *saveValue = BuildMI(*machineBB[0], machineBB[0]->begin(), V9::PHI, 3).addReg(lastPhi).addReg(I->second).addRegDef(tmp); - DEBUG(std::cerr << "Resulting PHI: " << *saveValue << "\n"); - lastPhi = tmp; - kernelPHIs[V->first][I->first] = lastPhi; - newValLocation[lastPhi] = machineBB[0]; - } + //Get machine code for this instruction + MachineCodeForInstruction & tempMvec = MachineCodeForInstruction::get(defaultInst); + tempMvec.addTemp((Value*) lastPhi); + + MachineInstr *saveValue = BuildMI(*machineBB[0], machineBB[0]->begin(), V9::PHI, 3).addReg(kernelValue[V->first]).addReg(I->second).addRegDef(lastPhi); + DEBUG(std::cerr << "Resulting PHI: " << *saveValue << "\n"); + newValLocation[lastPhi] = machineBB[0]; + } + else { + Instruction *tmp = new TmpInstruction(I->second); + + //Get machine code for this instruction + MachineCodeForInstruction & tempMvec = MachineCodeForInstruction::get(defaultInst); + tempMvec.addTemp((Value*) tmp); + + + MachineInstr *saveValue = BuildMI(*machineBB[0], machineBB[0]->begin(), V9::PHI, 3).addReg(lastPhi).addReg(I->second).addRegDef(tmp); + DEBUG(std::cerr << "Resulting PHI: " << *saveValue << "\n"); + lastPhi = tmp; + kernelPHIs[V->first][I->first] = lastPhi; + newValLocation[lastPhi] = machineBB[0]; + } } //Final phi value else { - //The resulting value must be the Value* we created earlier - assert(lastPhi != 0 && "Last phi is NULL!\n"); - MachineInstr *saveValue = BuildMI(*machineBB[0], machineBB[0]->begin(), V9::PHI, 3).addReg(lastPhi).addReg(I->second).addRegDef(finalPHIValue[V->first]); - DEBUG(std::cerr << "Resulting PHI: " << *saveValue << "\n"); - kernelPHIs[V->first][I->first] = finalPHIValue[V->first]; + //The resulting value must be the Value* we created earlier + assert(lastPhi != 0 && "Last phi is NULL!\n"); + MachineInstr *saveValue = BuildMI(*machineBB[0], machineBB[0]->begin(), V9::PHI, 3).addReg(lastPhi).addReg(I->second).addRegDef(finalPHIValue[V->first]); + DEBUG(std::cerr << "Resulting PHI: " << *saveValue << "\n"); + kernelPHIs[V->first][I->first] = finalPHIValue[V->first]; } ++count; @@ -2814,58 +2814,58 @@ Instruction *tmp = 0; for(unsigned i = 0; i < I->getNumOperands(); ++i) { - - //Get Operand - const MachineOperand &mOp = I->getOperand(i); - assert(mOp.getType() == MachineOperand::MO_VirtualRegister - && "Should be a Value*\n"); - - if(!tmp) { - tmp = new TmpInstruction(mOp.getVRegValue()); - addToMCFI.push_back(tmp); - } - - //Now for all our arguments we read, OR to the new - //TmpInstruction that we created - if(mOp.isUse()) { - DEBUG(std::cerr << "Use: " << mOp << "\n"); - //Place a copy at the end of its BB but before the branches - assert(newValLocation.count(mOp.getVRegValue()) && "We must know where this value is located\n"); - //Reverse iterate to find the branches, we can safely assume no instructions have been - //put in the nop positions - for(MachineBasicBlock::iterator inst = --(newValLocation[mOp.getVRegValue()])->end(), endBB = (newValLocation[mOp.getVRegValue()])->begin(); inst != endBB; --inst) { - MachineOpCode opc = inst->getOpcode(); - if(TMI->isBranch(opc) || TMI->isNop(opc)) - continue; - else { - if(mOp.getVRegValue()->getType() == Type::FloatTy) - BuildMI(*(newValLocation[mOp.getVRegValue()]), ++inst, V9::FMOVS, 3).addReg(mOp.getVRegValue()).addRegDef(tmp); - else if(mOp.getVRegValue()->getType() == Type::DoubleTy) - BuildMI(*(newValLocation[mOp.getVRegValue()]), ++inst, V9::FMOVD, 3).addReg(mOp.getVRegValue()).addRegDef(tmp); - else - BuildMI(*(newValLocation[mOp.getVRegValue()]), ++inst, V9::ORr, 3).addReg(mOp.getVRegValue()).addImm(0).addRegDef(tmp); - - break; - } - - } - - } - else { - //Remove the phi and replace it with an OR - DEBUG(std::cerr << "Def: " << mOp << "\n"); - //newORs.push_back(std::make_pair(tmp, mOp.getVRegValue())); - if(tmp->getType() == Type::FloatTy) - BuildMI(*kernelBB[0], I, V9::FMOVS, 3).addReg(tmp).addRegDef(mOp.getVRegValue()); - else if(tmp->getType() == Type::DoubleTy) - BuildMI(*kernelBB[0], I, V9::FMOVD, 3).addReg(tmp).addRegDef(mOp.getVRegValue()); - else - BuildMI(*kernelBB[0], I, V9::ORr, 3).addReg(tmp).addImm(0).addRegDef(mOp.getVRegValue()); - - - worklist.push_back(std::make_pair(kernelBB[0], I)); - } - + + //Get Operand + const MachineOperand &mOp = I->getOperand(i); + assert(mOp.getType() == MachineOperand::MO_VirtualRegister + && "Should be a Value*\n"); + + if(!tmp) { + tmp = new TmpInstruction(mOp.getVRegValue()); + addToMCFI.push_back(tmp); + } + + //Now for all our arguments we read, OR to the new + //TmpInstruction that we created + if(mOp.isUse()) { + DEBUG(std::cerr << "Use: " << mOp << "\n"); + //Place a copy at the end of its BB but before the branches + assert(newValLocation.count(mOp.getVRegValue()) && "We must know where this value is located\n"); + //Reverse iterate to find the branches, we can safely assume no instructions have been + //put in the nop positions + for(MachineBasicBlock::iterator inst = --(newValLocation[mOp.getVRegValue()])->end(), endBB = (newValLocation[mOp.getVRegValue()])->begin(); inst != endBB; --inst) { + MachineOpCode opc = inst->getOpcode(); + if(TMI->isBranch(opc) || TMI->isNop(opc)) + continue; + else { + if(mOp.getVRegValue()->getType() == Type::FloatTy) + BuildMI(*(newValLocation[mOp.getVRegValue()]), ++inst, V9::FMOVS, 3).addReg(mOp.getVRegValue()).addRegDef(tmp); + else if(mOp.getVRegValue()->getType() == Type::DoubleTy) + BuildMI(*(newValLocation[mOp.getVRegValue()]), ++inst, V9::FMOVD, 3).addReg(mOp.getVRegValue()).addRegDef(tmp); + else + BuildMI(*(newValLocation[mOp.getVRegValue()]), ++inst, V9::ORr, 3).addReg(mOp.getVRegValue()).addImm(0).addRegDef(tmp); + + break; + } + + } + + } + else { + //Remove the phi and replace it with an OR + DEBUG(std::cerr << "Def: " << mOp << "\n"); + //newORs.push_back(std::make_pair(tmp, mOp.getVRegValue())); + if(tmp->getType() == Type::FloatTy) + BuildMI(*kernelBB[0], I, V9::FMOVS, 3).addReg(tmp).addRegDef(mOp.getVRegValue()); + else if(tmp->getType() == Type::DoubleTy) + BuildMI(*kernelBB[0], I, V9::FMOVD, 3).addReg(tmp).addRegDef(mOp.getVRegValue()); + else + BuildMI(*kernelBB[0], I, V9::ORr, 3).addReg(tmp).addImm(0).addRegDef(mOp.getVRegValue()); + + + worklist.push_back(std::make_pair(kernelBB[0], I)); + } + } } @@ -2885,68 +2885,68 @@ //Remove phis from epilogue for(std::vector >::iterator MB = epilogues.begin(), - ME = epilogues.end(); MB != ME; ++MB) { + ME = epilogues.end(); MB != ME; ++MB) { for(std::vector::iterator currentMBB = MB->begin(), currentME = MB->end(); currentMBB != currentME; ++currentMBB) { for(MachineBasicBlock::iterator I = (*currentMBB)->begin(), - E = (*currentMBB)->end(); I != E; ++I) { + E = (*currentMBB)->end(); I != E; ++I) { - DEBUG(std::cerr << "Looking at Instr: " << *I << "\n"); - //Get op code and check if its a phi - if(I->getOpcode() == V9::PHI) { - Instruction *tmp = 0; - - for(unsigned i = 0; i < I->getNumOperands(); ++i) { - //Get Operand - const MachineOperand &mOp = I->getOperand(i); - assert(mOp.getType() == MachineOperand::MO_VirtualRegister && "Should be a Value*\n"); - - if(!tmp) { - tmp = new TmpInstruction(mOp.getVRegValue()); - addToMCFI.push_back(tmp); - } - - //Now for all our arguments we read, OR to the new TmpInstruction that we created - if(mOp.isUse()) { - DEBUG(std::cerr << "Use: " << mOp << "\n"); - //Place a copy at the end of its BB but before the branches - assert(newValLocation.count(mOp.getVRegValue()) && "We must know where this value is located\n"); - //Reverse iterate to find the branches, we can safely assume no instructions have been - //put in the nop positions - for(MachineBasicBlock::iterator inst = --(newValLocation[mOp.getVRegValue()])->end(), endBB = (newValLocation[mOp.getVRegValue()])->begin(); inst != endBB; --inst) { - MachineOpCode opc = inst->getOpcode(); - if(TMI->isBranch(opc) || TMI->isNop(opc)) - continue; - else { - if(mOp.getVRegValue()->getType() == Type::FloatTy) - BuildMI(*(newValLocation[mOp.getVRegValue()]), ++inst, V9::FMOVS, 3).addReg(mOp.getVRegValue()).addRegDef(tmp); - else if(mOp.getVRegValue()->getType() == Type::DoubleTy) - BuildMI(*(newValLocation[mOp.getVRegValue()]), ++inst, V9::FMOVD, 3).addReg(mOp.getVRegValue()).addRegDef(tmp); - else - BuildMI(*(newValLocation[mOp.getVRegValue()]), ++inst, V9::ORr, 3).addReg(mOp.getVRegValue()).addImm(0).addRegDef(tmp); - - - break; - } - - } - - } - else { - //Remove the phi and replace it with an OR - DEBUG(std::cerr << "Def: " << mOp << "\n"); - if(tmp->getType() == Type::FloatTy) - BuildMI(**currentMBB, I, V9::FMOVS, 3).addReg(tmp).addRegDef(mOp.getVRegValue()); - else if(tmp->getType() == Type::DoubleTy) - BuildMI(**currentMBB, I, V9::FMOVD, 3).addReg(tmp).addRegDef(mOp.getVRegValue()); - else - BuildMI(**currentMBB, I, V9::ORr, 3).addReg(tmp).addImm(0).addRegDef(mOp.getVRegValue()); - - worklist.push_back(std::make_pair(*currentMBB,I)); - } - } - } + DEBUG(std::cerr << "Looking at Instr: " << *I << "\n"); + //Get op code and check if its a phi + if(I->getOpcode() == V9::PHI) { + Instruction *tmp = 0; + + for(unsigned i = 0; i < I->getNumOperands(); ++i) { + //Get Operand + const MachineOperand &mOp = I->getOperand(i); + assert(mOp.getType() == MachineOperand::MO_VirtualRegister && "Should be a Value*\n"); + + if(!tmp) { + tmp = new TmpInstruction(mOp.getVRegValue()); + addToMCFI.push_back(tmp); + } + + //Now for all our arguments we read, OR to the new TmpInstruction that we created + if(mOp.isUse()) { + DEBUG(std::cerr << "Use: " << mOp << "\n"); + //Place a copy at the end of its BB but before the branches + assert(newValLocation.count(mOp.getVRegValue()) && "We must know where this value is located\n"); + //Reverse iterate to find the branches, we can safely assume no instructions have been + //put in the nop positions + for(MachineBasicBlock::iterator inst = --(newValLocation[mOp.getVRegValue()])->end(), endBB = (newValLocation[mOp.getVRegValue()])->begin(); inst != endBB; --inst) { + MachineOpCode opc = inst->getOpcode(); + if(TMI->isBranch(opc) || TMI->isNop(opc)) + continue; + else { + if(mOp.getVRegValue()->getType() == Type::FloatTy) + BuildMI(*(newValLocation[mOp.getVRegValue()]), ++inst, V9::FMOVS, 3).addReg(mOp.getVRegValue()).addRegDef(tmp); + else if(mOp.getVRegValue()->getType() == Type::DoubleTy) + BuildMI(*(newValLocation[mOp.getVRegValue()]), ++inst, V9::FMOVD, 3).addReg(mOp.getVRegValue()).addRegDef(tmp); + else + BuildMI(*(newValLocation[mOp.getVRegValue()]), ++inst, V9::ORr, 3).addReg(mOp.getVRegValue()).addImm(0).addRegDef(tmp); + + + break; + } + + } + + } + else { + //Remove the phi and replace it with an OR + DEBUG(std::cerr << "Def: " << mOp << "\n"); + if(tmp->getType() == Type::FloatTy) + BuildMI(**currentMBB, I, V9::FMOVS, 3).addReg(tmp).addRegDef(mOp.getVRegValue()); + else if(tmp->getType() == Type::DoubleTy) + BuildMI(**currentMBB, I, V9::FMOVD, 3).addReg(tmp).addRegDef(mOp.getVRegValue()); + else + BuildMI(**currentMBB, I, V9::ORr, 3).addReg(tmp).addImm(0).addRegDef(mOp.getVRegValue()); + + worklist.push_back(std::make_pair(*currentMBB,I)); + } + } + } } } } @@ -2964,7 +2964,7 @@ for(std::vector >::iterator I = worklist.begin(), E = worklist.end(); I != E; ++I) { DEBUG(std::cerr << "Deleting PHI " << *I->second << "\n"); I->first->erase(I->second); - + } @@ -3001,8 +3001,8 @@ if(instrsMovedDown.count(mbb)) { for(std::vector >::iterator I = instrsMovedDown[mbb].begin(), E = instrsMovedDown[mbb].end(); I != E; ++I) { - if(branchStage[mbb] == I->second) - sideMBB->push_back((I->first)->clone()); + if(branchStage[mbb] == I->second) + sideMBB->push_back((I->first)->clone()); } //Add unconditional branches to original exits @@ -3024,36 +3024,36 @@ std::vector newLLVMEp; for(std::vector::iterator currentMBB = MB.begin(), - lastMBB = MB.end(); currentMBB != lastMBB; ++currentMBB) { - BasicBlock *tmpBB = new BasicBlock("SideEpilogue", (Function*) (*currentMBB)->getBasicBlock()->getParent()); - MachineBasicBlock *tmp = new MachineBasicBlock(tmpBB); - - //Clone instructions and insert into new MBB - for(MachineBasicBlock::iterator I = (*currentMBB)->begin(), - E = (*currentMBB)->end(); I != E; ++I) { - - MachineInstr *clone = I->clone(); - if(clone->getOpcode() == V9::BA && (currentMBB+1 == lastMBB)) { - //update branch to side exit - for(unsigned i = 0; i < clone->getNumOperands(); ++i) { - MachineOperand &mOp = clone->getOperand(i); - if (mOp.getType() == MachineOperand::MO_PCRelativeDisp) { - mOp.setValueReg(sideBB); - } - } - } - - tmp->push_back(clone); - - } + lastMBB = MB.end(); currentMBB != lastMBB; ++currentMBB) { + BasicBlock *tmpBB = new BasicBlock("SideEpilogue", (Function*) (*currentMBB)->getBasicBlock()->getParent()); + MachineBasicBlock *tmp = new MachineBasicBlock(tmpBB); + + //Clone instructions and insert into new MBB + for(MachineBasicBlock::iterator I = (*currentMBB)->begin(), + E = (*currentMBB)->end(); I != E; ++I) { + + MachineInstr *clone = I->clone(); + if(clone->getOpcode() == V9::BA && (currentMBB+1 == lastMBB)) { + //update branch to side exit + for(unsigned i = 0; i < clone->getNumOperands(); ++i) { + MachineOperand &mOp = clone->getOperand(i); + if (mOp.getType() == MachineOperand::MO_PCRelativeDisp) { + mOp.setValueReg(sideBB); + } + } + } + + tmp->push_back(clone); + + } - //Add llvm branch - TerminatorInst *newBranch = new BranchInst(sideBB, tmpBB); + //Add llvm branch + TerminatorInst *newBranch = new BranchInst(sideBB, tmpBB); - newEp.push_back(tmp); - (((MachineBasicBlock*)SB[0])->getParent())->getBasicBlockList().push_back(tmp); + newEp.push_back(tmp); + (((MachineBasicBlock*)SB[0])->getParent())->getBasicBlockList().push_back(tmp); - newLLVMEp.push_back(tmpBB); + newLLVMEp.push_back(tmpBB); } side_llvm_epilogues.push_back(newLLVMEp); @@ -3069,44 +3069,44 @@ //Get BB side exit we are dealing with MachineBasicBlock *currentMBB = prologues[P][sideExitNum]; if(P >= (unsigned) stage) { - //Iterate backwards of machine instructions to find the branch we need to update - for(MachineBasicBlock::reverse_iterator mInst = currentMBB->rbegin(), mInstEnd = currentMBB->rend(); mInst != mInstEnd; ++mInst) { - MachineOpCode OC = mInst->getOpcode(); - - //If its a branch update its branchto - if(TMI->isBranch(OC)) { - for(unsigned opNum = 0; opNum < mInst->getNumOperands(); ++opNum) { - MachineOperand &mOp = mInst->getOperand(opNum); - if (mOp.getType() == MachineOperand::MO_PCRelativeDisp) { - //Check if we branch to side exit - if(mOp.getVRegValue() == sideExits[mbb]) { - mOp.setValueReg(side_llvm_epilogues[P][0]); - } - } - } - DEBUG(std::cerr << "New Prologue Branch: " << *mInst << "\n"); - } - } - - //Update llvm branch - TerminatorInst *branchVal = ((BasicBlock*) currentMBB->getBasicBlock())->getTerminator(); - DEBUG(std::cerr << *branchVal << "\n"); - - for(unsigned i=0; i < branchVal->getNumSuccessors(); ++i) { - if(branchVal->getSuccessor(i) == sideExits[mbb]) { - DEBUG(std::cerr << "Replacing successor bb\n"); - branchVal->setSuccessor(i, side_llvm_epilogues[P][0]); - } - } + //Iterate backwards of machine instructions to find the branch we need to update + for(MachineBasicBlock::reverse_iterator mInst = currentMBB->rbegin(), mInstEnd = currentMBB->rend(); mInst != mInstEnd; ++mInst) { + MachineOpCode OC = mInst->getOpcode(); + + //If its a branch update its branchto + if(TMI->isBranch(OC)) { + for(unsigned opNum = 0; opNum < mInst->getNumOperands(); ++opNum) { + MachineOperand &mOp = mInst->getOperand(opNum); + if (mOp.getType() == MachineOperand::MO_PCRelativeDisp) { + //Check if we branch to side exit + if(mOp.getVRegValue() == sideExits[mbb]) { + mOp.setValueReg(side_llvm_epilogues[P][0]); + } + } + } + DEBUG(std::cerr << "New Prologue Branch: " << *mInst << "\n"); + } + } + + //Update llvm branch + TerminatorInst *branchVal = ((BasicBlock*) currentMBB->getBasicBlock())->getTerminator(); + DEBUG(std::cerr << *branchVal << "\n"); + + for(unsigned i=0; i < branchVal->getNumSuccessors(); ++i) { + if(branchVal->getSuccessor(i) == sideExits[mbb]) { + DEBUG(std::cerr << "Replacing successor bb\n"); + branchVal->setSuccessor(i, side_llvm_epilogues[P][0]); + } + } } else { - //must add BA branch because another prologue or kernel has the actual side exit branch - //Add unconditional branches to original exits - assert( (sideExitNum+1) < prologues[P].size() && "must have valid prologue to branch to"); - BuildMI(prologues[P][sideExitNum], V9::BA, 1).addPCDisp((BasicBlock*)(prologues[P][sideExitNum+1])->getBasicBlock()); - BuildMI(prologues[P][sideExitNum], V9::NOP, 0); + //must add BA branch because another prologue or kernel has the actual side exit branch + //Add unconditional branches to original exits + assert( (sideExitNum+1) < prologues[P].size() && "must have valid prologue to branch to"); + BuildMI(prologues[P][sideExitNum], V9::BA, 1).addPCDisp((BasicBlock*)(prologues[P][sideExitNum+1])->getBasicBlock()); + BuildMI(prologues[P][sideExitNum], V9::NOP, 0); - TerminatorInst *newBranch = new BranchInst((BasicBlock*) (prologues[P][sideExitNum+1])->getBasicBlock(), (BasicBlock*) (prologues[P][sideExitNum])->getBasicBlock()); + TerminatorInst *newBranch = new BranchInst((BasicBlock*) (prologues[P][sideExitNum+1])->getBasicBlock(), (BasicBlock*) (prologues[P][sideExitNum])->getBasicBlock()); } } @@ -3120,19 +3120,19 @@ //If its a branch update its branchto if(TMI->isBranch(OC)) { - for(unsigned opNum = 0; opNum < mInst->getNumOperands(); ++opNum) { - MachineOperand &mOp = mInst->getOperand(opNum); - if (mOp.getType() == MachineOperand::MO_PCRelativeDisp) { - //Check if we branch to side exit - if(mOp.getVRegValue() == sideExits[mbb]) { - if(side_llvm_epilogues.size() > 0) - mOp.setValueReg(side_llvm_epilogues[0][0]); - else - mOp.setValueReg(sideBB); - } - } - } - DEBUG(std::cerr << "New Prologue Branch: " << *mInst << "\n"); + for(unsigned opNum = 0; opNum < mInst->getNumOperands(); ++opNum) { + MachineOperand &mOp = mInst->getOperand(opNum); + if (mOp.getType() == MachineOperand::MO_PCRelativeDisp) { + //Check if we branch to side exit + if(mOp.getVRegValue() == sideExits[mbb]) { + if(side_llvm_epilogues.size() > 0) + mOp.setValueReg(side_llvm_epilogues[0][0]); + else + mOp.setValueReg(sideBB); + } + } + } + DEBUG(std::cerr << "New Prologue Branch: " << *mInst << "\n"); } } @@ -3143,11 +3143,11 @@ for(unsigned i=0; i < branchVal->getNumSuccessors(); ++i) { if(branchVal->getSuccessor(i) == sideExits[mbb]) { - DEBUG(std::cerr << "Replacing successor bb\n"); - if(side_llvm_epilogues.size() > 0) - branchVal->setSuccessor(i, side_llvm_epilogues[0][0]); - else - branchVal->setSuccessor(i, sideBB); + DEBUG(std::cerr << "Replacing successor bb\n"); + if(side_llvm_epilogues.size() > 0) + branchVal->setSuccessor(i, side_llvm_epilogues[0][0]); + else + branchVal->setSuccessor(i, sideBB); } } } Index: llvm/lib/Target/SparcV9/ModuloScheduling/ModuloSchedulingSuperBlock.h diff -u llvm/lib/Target/SparcV9/ModuloScheduling/ModuloSchedulingSuperBlock.h:1.2 llvm/lib/Target/SparcV9/ModuloScheduling/ModuloSchedulingSuperBlock.h:1.3 --- llvm/lib/Target/SparcV9/ModuloScheduling/ModuloSchedulingSuperBlock.h:1.2 Thu Jun 16 23:00:57 2005 +++ llvm/lib/Target/SparcV9/ModuloScheduling/ModuloSchedulingSuperBlock.h Wed Jul 27 00:53:44 2005 @@ -33,9 +33,9 @@ int depth; int height; MSNodeSBAttributes(int asap=-1, int alap=-1, int mob=-1, - int d=-1, int h=-1) : ASAP(asap), ALAP(alap), - MOB(mob), depth(d), - height(h) {} + int d=-1, int h=-1) : ASAP(asap), ALAP(alap), + MOB(mob), depth(d), + height(h) {} }; @@ -43,7 +43,7 @@ class ModuloSchedulingSBPass : public FunctionPass { const TargetMachine ⌖ - + //Map to hold Value* defs std::map defMap; @@ -52,7 +52,7 @@ //Map to hold machine to llvm instrs for each valid BB std::map > machineTollvm; - + //LLVM Instruction we know we can add TmpInstructions to its MCFI Instruction *defaultInst; @@ -76,116 +76,116 @@ //Current initiation interval int II; - + //Internal Functions - void FindSuperBlocks(Function &F, LoopInfo &LI, - std::vector > &Worklist); + void FindSuperBlocks(Function &F, LoopInfo &LI, + std::vector > &Worklist); bool MachineBBisValid(const MachineBasicBlock *B, - std::map &indexMap, - unsigned &offset); + std::map &indexMap, + unsigned &offset); bool CreateDefMap(std::vector &SB); - bool getIndVar(std::vector &superBlock, - std::map &bbMap, - std::map &indexMap); + bool getIndVar(std::vector &superBlock, + std::map &bbMap, + std::map &indexMap); bool assocIndVar(Instruction *I, std::set &indVar, - std::vector &stack, - std::map &bbMap, - const BasicBlock *first, - std::set &llvmSuperBlock); + std::vector &stack, + std::map &bbMap, + const BasicBlock *first, + std::set &llvmSuperBlock); int calculateResMII(std::vector &superBlock); int calculateRecMII(MSchedGraphSB *graph, int MII); void findAllCircuits(MSchedGraphSB *g, int II); - void addRecc(std::vector &stack, - std::map &newNodes); + void addRecc(std::vector &stack, + std::map &newNodes); bool circuit(MSchedGraphSBNode *v, std::vector &stack, - std::set &blocked, std::vector &SCC, - MSchedGraphSBNode *s, std::map > &B, - int II, std::map &newNodes); + std::set &blocked, std::vector &SCC, + MSchedGraphSBNode *s, std::map > &B, + int II, std::map &newNodes); void unblock(MSchedGraphSBNode *u, std::set &blocked, - std::map > &B); + std::map > &B); void addSCC(std::vector &SCC, std::map &newNodes); void calculateNodeAttributes(MSchedGraphSB *graph, int MII); bool ignoreEdge(MSchedGraphSBNode *srcNode, MSchedGraphSBNode *destNode); int calculateASAP(MSchedGraphSBNode *node, int MII, MSchedGraphSBNode *destNode); int calculateALAP(MSchedGraphSBNode *node, int MII, - int maxASAP, MSchedGraphSBNode *srcNode); + int maxASAP, MSchedGraphSBNode *srcNode); int findMaxASAP(); int calculateHeight(MSchedGraphSBNode *node,MSchedGraphSBNode *srcNode); int calculateDepth(MSchedGraphSBNode *node, MSchedGraphSBNode *destNode); void computePartialOrder(); - void connectedComponentSet(MSchedGraphSBNode *node, std::set &ccSet, - std::set &lastNodes); + void connectedComponentSet(MSchedGraphSBNode *node, std::set &ccSet, + std::set &lastNodes); void searchPath(MSchedGraphSBNode *node, - std::vector &path, - std::set &nodesToAdd, - std::set &new_reccurrence); + std::vector &path, + std::set &nodesToAdd, + std::set &new_reccurrence); void orderNodes(); bool computeSchedule(std::vector &BB, MSchedGraphSB *MSG); bool scheduleNode(MSchedGraphSBNode *node, int start, int end); void predIntersect(std::set &CurrentSet, std::set &IntersectResult); void succIntersect(std::set &CurrentSet, std::set &IntersectResult); void reconstructLoop(std::vector &SB); - void fixBranches(std::vector > &prologues, - std::vector > &llvm_prologues, - std::vector &machineKernelBB, - std::vector &llvmKernelBB, - std::vector > &epilogues, - std::vector > &llvm_epilogues, - std::vector &SB, - std::map &sideExits); - - void writePrologues(std::vector > &prologues, - std::vector &origBB, - std::vector > &llvm_prologues, - std::map > &valuesToSave, - std::map > &newValues, - std::map &newValLocation); - - void writeKernel(std::vector &llvmBB, std::vector &machineBB, - std::map > &valuesToSave, - std::map > &newValues, - std::map &newValLocation, - std::map > &kernelPHIs); - - void removePHIs(std::vector &SB, - std::vector > &prologues, - std::vector > &epilogues, - std::vector &kernelBB, - std::map &newValLocation); - - void writeEpilogues(std::vector > &epilogues, - std::vector &origSB, - std::vector > &llvm_epilogues, - std::map > &valuesToSave, - std::map > &newValues, - std::map &newValLocation, - std::map > &kernelPHIs); - - void writeSideExits(std::vector > &prologues, - std::vector > &llvm_prologues, - std::vector > &epilogues, - std::vector > &llvm_epilogues, - std::map &sideExits, - std::map > > &instrsMovedDown, - std::vector &SB, - std::vector &kernelMBBs, - std::map branchStage); + void fixBranches(std::vector > &prologues, + std::vector > &llvm_prologues, + std::vector &machineKernelBB, + std::vector &llvmKernelBB, + std::vector > &epilogues, + std::vector > &llvm_epilogues, + std::vector &SB, + std::map &sideExits); + + void writePrologues(std::vector > &prologues, + std::vector &origBB, + std::vector > &llvm_prologues, + std::map > &valuesToSave, + std::map > &newValues, + std::map &newValLocation); + + void writeKernel(std::vector &llvmBB, std::vector &machineBB, + std::map > &valuesToSave, + std::map > &newValues, + std::map &newValLocation, + std::map > &kernelPHIs); + + void removePHIs(std::vector &SB, + std::vector > &prologues, + std::vector > &epilogues, + std::vector &kernelBB, + std::map &newValLocation); + + void writeEpilogues(std::vector > &epilogues, + std::vector &origSB, + std::vector > &llvm_epilogues, + std::map > &valuesToSave, + std::map > &newValues, + std::map &newValLocation, + std::map > &kernelPHIs); + + void writeSideExits(std::vector > &prologues, + std::vector > &llvm_prologues, + std::vector > &epilogues, + std::vector > &llvm_epilogues, + std::map &sideExits, + std::map > > &instrsMovedDown, + std::vector &SB, + std::vector &kernelMBBs, + std::map branchStage); public: ModuloSchedulingSBPass(TargetMachine &targ) : target(targ) {} virtual bool runOnFunction(Function &F); virtual const char* getPassName() const { return "ModuloScheduling-SuperBlock"; } - - + + // getAnalysisUsage virtual void getAnalysisUsage(AnalysisUsage &AU) const { - /// HACK: We don't actually need scev, but we have - /// to say we do so that the pass manager does not delete it - /// before we run. - AU.addRequired(); - AU.addRequired(); - AU.addRequired(); + /// HACK: We don't actually need scev, but we have + /// to say we do so that the pass manager does not delete it + /// before we run. + AU.addRequired(); + AU.addRequired(); + AU.addRequired(); } }; }