From alenhar2 at cs.uiuc.edu  Mon Aug 15 09:31:49 2005
From: alenhar2 at cs.uiuc.edu (Andrew Lenharth)
Date: Mon, 15 Aug 2005 09:31:49 -0500
Subject: [llvm-commits] CVS: llvm/lib/Target/Alpha/AlphaISelPattern.cpp 
Message-ID: <200508151431.JAA06965@zion.cs.uiuc.edu>



Changes in directory llvm/lib/Target/Alpha:

AlphaISelPattern.cpp updated: 1.160 -> 1.161
---
Log message:

isIntImmediate is a good Idea.  Add a flavor that checks bounds while it is at it

---
Diffs of the changes:  (+97 -105)

 AlphaISelPattern.cpp |  202 ++++++++++++++++++++++++---------------------------
 1 files changed, 97 insertions(+), 105 deletions(-)


Index: llvm/lib/Target/Alpha/AlphaISelPattern.cpp
diff -u llvm/lib/Target/Alpha/AlphaISelPattern.cpp:1.160 llvm/lib/Target/Alpha/AlphaISelPattern.cpp:1.161
--- llvm/lib/Target/Alpha/AlphaISelPattern.cpp:1.160	Tue Aug  9 15:21:09 2005
+++ llvm/lib/Target/Alpha/AlphaISelPattern.cpp	Mon Aug 15 09:31:37 2005
@@ -588,6 +588,46 @@
   }
 }
 
+static bool isSIntImmediate(SDOperand N, int64_t& Imm) {
+  // test for constant
+  if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N)) {
+    // retrieve value
+    Imm = CN->getSignExtended();
+    // passes muster
+    return true;
+  }
+  // not a constant
+  return false;
+}
+
+// isSIntImmediateBounded - This method tests to see if a constant operand
+// bounded s.t. low <= Imm <= high
+// If so Imm will receive the 64 bit value.
+static bool isSIntImmediateBounded(SDOperand N, int64_t& Imm, 
+                                   int64_t low, int64_t high) {
+  if (isSIntImmediate(N, Imm) && Imm <= high && Imm >= high)
+    return true;
+  return false;
+}
+static bool isUIntImmediate(SDOperand N, uint64_t& Imm) {
+  // test for constant
+  if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N)) {
+    // retrieve value
+    Imm = (uint64_t)CN->getValue();
+    // passes muster
+    return true;
+  }
+  // not a constant
+  return false;
+}
+
+static bool isUIntImmediateBounded(SDOperand N, uint64_t& Imm, 
+                                   uint64_t low, uint64_t high) {
+  if (isUIntImmediate(N, Imm) && Imm <= high && Imm >= high)
+    return true;
+  return false;
+}
+
 static void getValueInfo(const Value* v, int& type, int& fun, int& offset)
 {
   fun = type = offset = 0;
@@ -1072,6 +1112,8 @@
   unsigned Tmp1, Tmp2 = 0, Tmp3;
   unsigned Opc = 0;
   unsigned opcode = N.getOpcode();
+  int64_t SImm;
+  uint64_t UImm;
 
   SDNode *Node = N.Val;
   MVT::ValueType DestType = N.getValueType();
@@ -1158,18 +1200,9 @@
     }
 
     Select(N.getOperand(0));
-    if (ConstantSDNode* CN = dyn_cast<ConstantSDNode>(N.getOperand(1)))
-    {
-      if (CN->getValue() < 32000)
-      {
-        BuildMI(BB, Alpha::LDA, 2, Alpha::R30)
-          .addImm(-CN->getValue()).addReg(Alpha::R30);
-      } else {
-        Tmp1 = SelectExpr(N.getOperand(1));
-        // Subtract size from stack pointer, thereby allocating some space.
-        BuildMI(BB, Alpha::SUBQ, 2, Alpha::R30).addReg(Alpha::R30).addReg(Tmp1);
-      }
-    } else {
+    if (isSIntImmediateBounded(N.getOperand(1), SImm, 0, 32767))
+      BuildMI(BB, Alpha::LDA, 2, Alpha::R30).addImm(-SImm).addReg(Alpha::R30);
+    else {
       Tmp1 = SelectExpr(N.getOperand(1));
       // Subtract size from stack pointer, thereby allocating some space.
       BuildMI(BB, Alpha::SUBQ, 2, Alpha::R30).addReg(Alpha::R30).addReg(Tmp1);
@@ -1448,46 +1481,37 @@
             bool isAdd = N.getOperand(0).getOpcode() == ISD::ADD;
             bool isMul = N.getOperand(0).getOpcode() == ISD::MUL;
             //FIXME: first check for Scaled Adds and Subs!
-            ConstantSDNode* CSD = NULL;
             if(!isMul && N.getOperand(0).getOperand(0).getOpcode() == ISD::SHL &&
-               (CSD = dyn_cast<ConstantSDNode>(N.getOperand(0).getOperand(0).getOperand(1))) &&
-               (CSD->getValue() == 2 || CSD->getValue() == 3))
+               isSIntImmediateBounded(N.getOperand(0).getOperand(0).getOperand(1), SImm, 2, 3))
             {
-              bool use4 = CSD->getValue() == 2;
+              bool use4 = SImm == 2;
               Tmp1 = SelectExpr(N.getOperand(0).getOperand(0).getOperand(0));
               Tmp2 = SelectExpr(N.getOperand(0).getOperand(1));
               BuildMI(BB, isAdd?(use4?Alpha::S4ADDL:Alpha::S8ADDL):(use4?Alpha::S4SUBL:Alpha::S8SUBL),
                       2,Result).addReg(Tmp1).addReg(Tmp2);
             }
             else if(isAdd && N.getOperand(0).getOperand(1).getOpcode() == ISD::SHL &&
-                    (CSD = dyn_cast<ConstantSDNode>(N.getOperand(0).getOperand(1).getOperand(1))) &&
-                    (CSD->getValue() == 2 || CSD->getValue() == 3))
+                    isSIntImmediateBounded(N.getOperand(0).getOperand(1).getOperand(1), SImm, 2, 3))
             {
-              bool use4 = CSD->getValue() == 2;
+              bool use4 = SImm == 2;
               Tmp1 = SelectExpr(N.getOperand(0).getOperand(1).getOperand(0));
               Tmp2 = SelectExpr(N.getOperand(0).getOperand(0));
               BuildMI(BB, use4?Alpha::S4ADDL:Alpha::S8ADDL, 2,Result).addReg(Tmp1).addReg(Tmp2);
             }
-            else if(N.getOperand(0).getOperand(1).getOpcode() == ISD::Constant &&
-                    cast<ConstantSDNode>(N.getOperand(0).getOperand(1))->getValue() <= 255)
+            else if(isSIntImmediateBounded(N.getOperand(0).getOperand(1), SImm, 0, 255)) 
             { //Normal imm add/sub
               Opc = isAdd ? Alpha::ADDLi : (isMul ? Alpha::MULLi : Alpha::SUBLi);
               Tmp1 = SelectExpr(N.getOperand(0).getOperand(0));
-              Tmp2 = cast<ConstantSDNode>(N.getOperand(0).getOperand(1))->getValue();
-              BuildMI(BB, Opc, 2, Result).addReg(Tmp1).addImm(Tmp2);
+              BuildMI(BB, Opc, 2, Result).addReg(Tmp1).addImm(SImm);
             }
-            else if(N.getOperand(0).getOperand(1).getOpcode() == ISD::Constant &&
-                    !isMul &&
-                    (CSD = dyn_cast<ConstantSDNode>(N.getOperand(0).getOperand(1))) &&
-                    (((int64_t)(CSD->getValue() << 32) >> 32) >= -255) &&
-                    (((int64_t)(CSD->getValue() << 32) >> 32) <= 0))
+            else if(!isMul && isSIntImmediate(N.getOperand(0).getOperand(1), SImm) &&
+                    (((SImm << 32) >> 32) >= -255) && (((SImm << 32) >> 32) <= 0))
             { //handle canonicalization
               Opc = isAdd ? Alpha::SUBLi : Alpha::ADDLi;
               Tmp1 = SelectExpr(N.getOperand(0).getOperand(0));
-              int64_t t = cast<ConstantSDNode>(N.getOperand(0).getOperand(1))->getValue();
-              t = 0 - ((t << 32) >> 32);
-              assert(t >= 0 && t <= 255);
-              BuildMI(BB, Opc, 2, Result).addReg(Tmp1).addImm(t);
+              SImm = 0 - ((SImm << 32) >> 32);
+              assert(SImm >= 0 && SImm <= 255);
+              BuildMI(BB, Opc, 2, Result).addReg(Tmp1).addImm(SImm);
             }
             else
             { //Normal add/sub
@@ -1536,8 +1560,7 @@
         int dir;
 
         //Tmp1 = SelectExpr(N.getOperand(0));
-        if(N.getOperand(1).getOpcode() == ISD::Constant &&
-           cast<ConstantSDNode>(N.getOperand(1))->getValue() <= 255)
+        if(isSIntImmediate(N.getOperand(1), SImm) && SImm <= 255 && SImm >= 0)
           isConst = true;
 
         switch (CC) {
@@ -1573,8 +1596,7 @@
         if (dir == 1) {
           Tmp1 = SelectExpr(N.getOperand(0));
           if (isConst) {
-            Tmp2 = cast<ConstantSDNode>(N.getOperand(1))->getValue();
-            BuildMI(BB, Opc, 2, Result).addReg(Tmp1).addImm(Tmp2);
+            BuildMI(BB, Opc, 2, Result).addReg(Tmp1).addImm(SImm);
           } else {
             Tmp2 = SelectExpr(N.getOperand(1));
             BuildMI(BB, Opc, 2, Result).addReg(Tmp1).addReg(Tmp2);
@@ -1624,27 +1646,24 @@
     //constant immediate test
   case ISD::XOR:
     //Match Not
-    if (N.getOperand(1).getOpcode() == ISD::Constant &&
-        cast<ConstantSDNode>(N.getOperand(1))->getSignExtended() == -1)
-      {
-        Tmp1 = SelectExpr(N.getOperand(0));
-        BuildMI(BB, Alpha::ORNOT, 2, Result).addReg(Alpha::R31).addReg(Tmp1);
-        return Result;
-      }
+    if (isSIntImmediate(N.getOperand(1), SImm) && SImm == -1) {
+      Tmp1 = SelectExpr(N.getOperand(0));
+      BuildMI(BB, Alpha::ORNOT, 2, Result).addReg(Alpha::R31).addReg(Tmp1);
+      return Result;
+    }
     //Fall through
   case ISD::AND:
     //handle zap
-    if (opcode == ISD::AND && N.getOperand(1).getOpcode() == ISD::Constant)
+    if (opcode == ISD::AND && isUIntImmediate(N.getOperand(1), UImm))
     {
-      uint64_t k = cast<ConstantSDNode>(N.getOperand(1))->getValue();
       unsigned int build = 0;
       for(int i = 0; i < 8; ++i)
       {
-        if ((k & 0x00FF) == 0x00FF)
+        if ((UImm & 0x00FF) == 0x00FF)
           build |= 1 << i;
-        else if ((k & 0x00FF) != 0)
+        else if ((UImm & 0x00FF) != 0)
         { build = 0; break; }
-        k >>= 8;
+        UImm >>= 8;
       }
       if (build)
       {
@@ -1656,9 +1675,7 @@
   case ISD::OR:
     //Check operand(0) == Not
     if (N.getOperand(0).getOpcode() == ISD::XOR &&
-        N.getOperand(0).getOperand(1).getOpcode() == ISD::Constant &&
-        cast<ConstantSDNode>(N.getOperand(0).getOperand(1))->getSignExtended()
-        == -1) {
+        isSIntImmediate(N.getOperand(0).getOperand(1), SImm) && SImm == -1) {
       switch(opcode) {
         case ISD::AND: Opc = Alpha::BIC; break;
         case ISD::OR:  Opc = Alpha::ORNOT; break;
@@ -1671,9 +1688,7 @@
     }
     //Check operand(1) == Not
     if (N.getOperand(1).getOpcode() == ISD::XOR &&
-        N.getOperand(1).getOperand(1).getOpcode() == ISD::Constant &&
-        cast<ConstantSDNode>(N.getOperand(1).getOperand(1))->getSignExtended()
-        == -1) {
+        isSIntImmediate(N.getOperand(1).getOperand(1), SImm) && SImm == -1) {
       switch(opcode) {
         case ISD::AND: Opc = Alpha::BIC; break;
         case ISD::OR:  Opc = Alpha::ORNOT; break;
@@ -1689,9 +1704,7 @@
   case ISD::SRL:
   case ISD::SRA:
   case ISD::MUL:
-    if(N.getOperand(1).getOpcode() == ISD::Constant &&
-       cast<ConstantSDNode>(N.getOperand(1))->getValue() <= 255)
-    {
+    if(isSIntImmediateBounded(N.getOperand(1), SImm, 0, 255)) {
       switch(opcode) {
       case ISD::AND: Opc = Alpha::ANDi; break;
       case ISD::OR:  Opc = Alpha::BISi; break;
@@ -1702,8 +1715,7 @@
       case ISD::MUL: Opc = Alpha::MULQi; break;
       };
       Tmp1 = SelectExpr(N.getOperand(0));
-      Tmp2 = cast<ConstantSDNode>(N.getOperand(1))->getValue();
-      BuildMI(BB, Opc, 2, Result).addReg(Tmp1).addImm(Tmp2);
+      BuildMI(BB, Opc, 2, Result).addReg(Tmp1).addImm(SImm);
     } else {
       switch(opcode) {
       case ISD::AND: Opc = Alpha::AND; break;
@@ -1748,16 +1760,14 @@
 
       //first check for Scaled Adds and Subs!
       //Valid for add and sub
-      ConstantSDNode* CSD = NULL;
-      if(N.getOperand(0).getOpcode() == ISD::SHL &&
-         (CSD = dyn_cast<ConstantSDNode>(N.getOperand(0).getOperand(1))) &&
-         (CSD->getValue() == 2 || CSD->getValue() == 3))
-      {
-        bool use4 = CSD->getValue() == 2;
+      if(N.getOperand(0).getOpcode() == ISD::SHL && 
+         isSIntImmediate(N.getOperand(0).getOperand(1), SImm) &&
+         (SImm == 2 || SImm == 3)) {
+        bool use4 = SImm == 2;
         Tmp2 = SelectExpr(N.getOperand(0).getOperand(0));
-        if ((CSD = dyn_cast<ConstantSDNode>(N.getOperand(1))) && CSD->getValue() <= 255)
+        if (isSIntImmediateBounded(N.getOperand(1), SImm, 0, 255))
           BuildMI(BB, isAdd?(use4?Alpha::S4ADDQi:Alpha::S8ADDQi):(use4?Alpha::S4SUBQi:Alpha::S8SUBQi),
-                  2, Result).addReg(Tmp2).addImm(CSD->getValue());
+                  2, Result).addReg(Tmp2).addImm(SImm);
         else {
           Tmp1 = SelectExpr(N.getOperand(1));
           BuildMI(BB, isAdd?(use4?Alpha::S4ADDQi:Alpha::S8ADDQi):(use4?Alpha::S4SUBQi:Alpha::S8SUBQi),
@@ -1766,45 +1776,37 @@
       }
       //Position prevents subs
       else if(N.getOperand(1).getOpcode() == ISD::SHL && isAdd &&
-              (CSD = dyn_cast<ConstantSDNode>(N.getOperand(1).getOperand(1))) &&
-              (CSD->getValue() == 2 || CSD->getValue() == 3))
-      {
-        bool use4 = CSD->getValue() == 2;
+              isSIntImmediate(N.getOperand(1).getOperand(1), SImm) &&
+              (SImm == 2 || SImm == 3)) {
+        bool use4 = SImm == 2;
         Tmp2 = SelectExpr(N.getOperand(1).getOperand(0));
-        if ((CSD = dyn_cast<ConstantSDNode>(N.getOperand(0))) && CSD->getValue() <= 255)
-          BuildMI(BB, use4?Alpha::S4ADDQi:Alpha::S8ADDQi, 2, Result).addReg(Tmp2)
-            .addImm(CSD->getValue());
+        if (isSIntImmediateBounded(N.getOperand(0), SImm, 0, 255))
+          BuildMI(BB, use4?Alpha::S4ADDQi:Alpha::S8ADDQi, 2, Result).addReg(Tmp2).addImm(SImm);
         else {
           Tmp1 = SelectExpr(N.getOperand(0));
           BuildMI(BB, use4?Alpha::S4ADDQ:Alpha::S8ADDQ, 2, Result).addReg(Tmp2).addReg(Tmp1);
         }
       }
       //small addi
-      else if((CSD = dyn_cast<ConstantSDNode>(N.getOperand(1))) &&
-              CSD->getValue() <= 255)
+      else if(isSIntImmediateBounded(N.getOperand(1), SImm, 0, 255))
       { //Normal imm add/sub
         Opc = isAdd ? Alpha::ADDQi : Alpha::SUBQi;
         Tmp1 = SelectExpr(N.getOperand(0));
-        BuildMI(BB, Opc, 2, Result).addReg(Tmp1).addImm(CSD->getValue());
+        BuildMI(BB, Opc, 2, Result).addReg(Tmp1).addImm(SImm);
       }
-      else if((CSD = dyn_cast<ConstantSDNode>(N.getOperand(1))) &&
-              (int64_t)CSD->getValue() >= 255 &&
-              (int64_t)CSD->getValue() <= 0)
+      else if(isSIntImmediateBounded(N.getOperand(1), SImm, -255, 0))
       { //inverted imm add/sub
         Opc = isAdd ? Alpha::SUBQi : Alpha::ADDQi;
         Tmp1 = SelectExpr(N.getOperand(0));
-        BuildMI(BB, Opc, 2, Result).addReg(Tmp1).addImm((int64_t)CSD->getValue());
+        BuildMI(BB, Opc, 2, Result).addReg(Tmp1).addImm(-SImm);
       }
       //larger addi
-      else if((CSD = dyn_cast<ConstantSDNode>(N.getOperand(1))) &&
-              CSD->getSignExtended() <= 32767 &&
-              CSD->getSignExtended() >= -32767)
+      else if(isSIntImmediateBounded(N.getOperand(1), SImm, -32767, 32767))
       { //LDA
         Tmp1 = SelectExpr(N.getOperand(0));
-        Tmp2 = (long)CSD->getSignExtended();
         if (!isAdd)
-          Tmp2 = -Tmp2;
-        BuildMI(BB, Alpha::LDA, 2, Result).addImm(Tmp2).addReg(Tmp1);
+          SImm = -SImm;
+        BuildMI(BB, Alpha::LDA, 2, Result).addImm(SImm).addReg(Tmp1);
       }
       //give up and do the operation
       else {
@@ -1825,12 +1827,10 @@
         .addReg(Tmp1).addReg(Tmp2);
       return Result;
     } else {
-      ConstantSDNode* CSD;
       //check if we can convert into a shift!
-      if ((CSD = dyn_cast<ConstantSDNode>(N.getOperand(1).Val)) &&
-          (int64_t)CSD->getSignExtended() != 0 &&
-          isPowerOf2_64(llabs(CSD->getSignExtended()))) {
-        unsigned k = Log2_64(llabs(CSD->getSignExtended()));
+      if (isSIntImmediate(N.getOperand(1), SImm) &&
+          SImm != 0 && isPowerOf2_64(llabs(SImm))) {
+        unsigned k = Log2_64(llabs(SImm));
         Tmp1 = SelectExpr(N.getOperand(0));
         if (k == 1)
           Tmp2 = Tmp1;
@@ -1843,7 +1843,7 @@
         BuildMI(BB, Alpha::SRLi, 2, Tmp3).addReg(Tmp2).addImm(64-k);
         unsigned Tmp4 = MakeReg(MVT::i64);
         BuildMI(BB, Alpha::ADDQ, 2, Tmp4).addReg(Tmp3).addReg(Tmp1);
-        if ((int64_t)CSD->getSignExtended() > 0)
+        if (SImm > 0)
           BuildMI(BB, Alpha::SRAi, 2, Result).addReg(Tmp4).addImm(k);
         else
         {
@@ -1858,10 +1858,7 @@
 
   case ISD::UDIV:
     {
-      ConstantSDNode* CSD;
-      if ((CSD = dyn_cast<ConstantSDNode>(N.getOperand(1).Val)) &&
-          ((int64_t)CSD->getSignExtended() >= 2 ||
-           (int64_t)CSD->getSignExtended() <= -2))
+      if (isSIntImmediate(N.getOperand(1), SImm) && (SImm >= 2 || SImm <= -2))
       {
         // If this is a divide by constant, we can emit code using some magic
         // constants to implement it as a multiply instead.
@@ -2007,12 +2004,9 @@
       if (CC.getOpcode() == ISD::SETCC) {
         //Int SetCC -> Select
         //Dropping the CC is only useful if we are comparing to 0
-        if((CC.getOperand(1).getOpcode() == ISD::Constant &&
-            cast<ConstantSDNode>(CC.getOperand(1))->getValue() == 0))
-        {
+        if(isSIntImmediateBounded(CC.getOperand(1), SImm, 0, 0)) {
           //figure out a few things
-          bool useImm = N.getOperand(2).getOpcode() == ISD::Constant &&
-            cast<ConstantSDNode>(N.getOperand(2))->getValue() <= 255;
+          bool useImm = isSIntImmediateBounded(N.getOperand(2), SImm, 0, 255);
 
           //Fix up CC
           ISD::CondCode cCode= cast<CondCodeSDNode>(CC.getOperand(2))->get();
@@ -2038,9 +2032,7 @@
 
           if (useImm) {
             Tmp3 = SelectExpr(N.getOperand(1)); //Use if FALSE
-            BuildMI(BB, Opc, 2, Result).addReg(Tmp3)
-                .addImm(cast<ConstantSDNode>(N.getOperand(2))->getValue())
-                .addReg(Tmp1);
+            BuildMI(BB, Opc, 2, Result).addReg(Tmp3).addImm(SImm).addReg(Tmp1);
           } else {
             Tmp2 = SelectExpr(N.getOperand(1)); //Use if TRUE
             Tmp3 = SelectExpr(N.getOperand(2)); //Use if FALSE





From jlaskey at apple.com  Mon Aug 15 12:14:30 2005
From: jlaskey at apple.com (Jim Laskey)
Date: Mon, 15 Aug 2005 12:14:30 -0500
Subject: [llvm-commits] CVS: llvm/lib/Target/PowerPC/PPC32ISelPattern.cpp 
Message-ID: <200508151714.MAA08642@zion.cs.uiuc.edu>



Changes in directory llvm/lib/Target/PowerPC:

PPC32ISelPattern.cpp updated: 1.139 -> 1.140
---
Log message:


Changed code gen for int to f32 to use rounding.  This makes FP results
consistent with gcc.


---
Diffs of the changes:  (+2 -2)

 PPC32ISelPattern.cpp |    4 ++--
 1 files changed, 2 insertions(+), 2 deletions(-)


Index: llvm/lib/Target/PowerPC/PPC32ISelPattern.cpp
diff -u llvm/lib/Target/PowerPC/PPC32ISelPattern.cpp:1.139 llvm/lib/Target/PowerPC/PPC32ISelPattern.cpp:1.140
--- llvm/lib/Target/PowerPC/PPC32ISelPattern.cpp:1.139	Sun Aug 14 13:38:32 2005
+++ llvm/lib/Target/PowerPC/PPC32ISelPattern.cpp	Mon Aug 15 12:14:19 2005
@@ -2312,7 +2312,7 @@
       addFrameReference(BuildMI(BB, PPC::STW, 3).addReg(Tmp1), FrameIdx, 4);
       addFrameReference(BuildMI(BB, PPC::LFD, 2, Tmp2), FrameIdx);
       // Generate the return value with a subtract
-      BuildMI(BB, PPC::FSUB, 2, Result).addReg(Tmp2).addReg(ConstF);
+      BuildMI(BB, DestType == MVT::f64 ? PPC::FSUB : PPC::FSUBS, 2, Result).addReg(Tmp2).addReg(ConstF);
     } else {
       unsigned ConstF = getConstDouble(0x1.000008p52);
       unsigned TmpL = MakeIntReg();
@@ -2323,7 +2323,7 @@
       addFrameReference(BuildMI(BB, PPC::STW, 3).addReg(TmpL), FrameIdx, 4);
       addFrameReference(BuildMI(BB, PPC::LFD, 2, Tmp2), FrameIdx);
       // Generate the return value with a subtract
-      BuildMI(BB, PPC::FSUB, 2, Result).addReg(Tmp2).addReg(ConstF);
+      BuildMI(BB, DestType == MVT::f64 ? PPC::FSUB : PPC::FSUBS, 2, Result).addReg(Tmp2).addReg(ConstF);
     }
     return Result;
   }





From jlaskey at apple.com  Mon Aug 15 12:35:37 2005
From: jlaskey at apple.com (Jim Laskey)
Date: Mon, 15 Aug 2005 12:35:37 -0500
Subject: [llvm-commits] CVS: llvm/lib/Target/PowerPC/PPC32ISelPattern.cpp 
Message-ID: <200508151735.MAA08904@zion.cs.uiuc.edu>



Changes in directory llvm/lib/Target/PowerPC:

PPC32ISelPattern.cpp updated: 1.140 -> 1.141
---
Log message:

Broke 80 column rule.



---
Diffs of the changes:  (+3 -2)

 PPC32ISelPattern.cpp |    5 +++--
 1 files changed, 3 insertions(+), 2 deletions(-)


Index: llvm/lib/Target/PowerPC/PPC32ISelPattern.cpp
diff -u llvm/lib/Target/PowerPC/PPC32ISelPattern.cpp:1.140 llvm/lib/Target/PowerPC/PPC32ISelPattern.cpp:1.141
--- llvm/lib/Target/PowerPC/PPC32ISelPattern.cpp:1.140	Mon Aug 15 12:14:19 2005
+++ llvm/lib/Target/PowerPC/PPC32ISelPattern.cpp	Mon Aug 15 12:35:26 2005
@@ -2303,6 +2303,7 @@
 
     int FrameIdx = BB->getParent()->getFrameInfo()->CreateStackObject(8, 8);
     MachineConstantPool *CP = BB->getParent()->getConstantPool();
+    Opc = DestType == MVT::f64 ? PPC::FSUB : PPC::FSUBS;
 
     if (IsUnsigned) {
       unsigned ConstF = getConstDouble(0x1.000000p52);
@@ -2312,7 +2313,7 @@
       addFrameReference(BuildMI(BB, PPC::STW, 3).addReg(Tmp1), FrameIdx, 4);
       addFrameReference(BuildMI(BB, PPC::LFD, 2, Tmp2), FrameIdx);
       // Generate the return value with a subtract
-      BuildMI(BB, DestType == MVT::f64 ? PPC::FSUB : PPC::FSUBS, 2, Result).addReg(Tmp2).addReg(ConstF);
+      BuildMI(BB, Opc, 2, Result).addReg(Tmp2).addReg(ConstF);
     } else {
       unsigned ConstF = getConstDouble(0x1.000008p52);
       unsigned TmpL = MakeIntReg();
@@ -2323,7 +2324,7 @@
       addFrameReference(BuildMI(BB, PPC::STW, 3).addReg(TmpL), FrameIdx, 4);
       addFrameReference(BuildMI(BB, PPC::LFD, 2, Tmp2), FrameIdx);
       // Generate the return value with a subtract
-      BuildMI(BB, DestType == MVT::f64 ? PPC::FSUB : PPC::FSUBS, 2, Result).addReg(Tmp2).addReg(ConstF);
+      BuildMI(BB, Opc, 2, Result).addReg(Tmp2).addReg(ConstF);
     }
     return Result;
   }





From lattner at cs.uiuc.edu  Mon Aug 15 18:34:03 2005
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Mon, 15 Aug 2005 18:34:03 -0500
Subject: [llvm-commits] CVS: llvm/lib/Analysis/ScalarEvolution.cpp 
Message-ID: <200508152334.SAA10814@zion.cs.uiuc.edu>



Changes in directory llvm/lib/Analysis:

ScalarEvolution.cpp updated: 1.40 -> 1.41
---
Log message:

Teach LLVM to know how many times a loop executes when constructed with
a < expression, e.g.: for (i = m; i < n; ++i)



---
Diffs of the changes:  (+110 -2)

 ScalarEvolution.cpp |  112 +++++++++++++++++++++++++++++++++++++++++++++++++++-
 1 files changed, 110 insertions(+), 2 deletions(-)


Index: llvm/lib/Analysis/ScalarEvolution.cpp
diff -u llvm/lib/Analysis/ScalarEvolution.cpp:1.40 llvm/lib/Analysis/ScalarEvolution.cpp:1.41
--- llvm/lib/Analysis/ScalarEvolution.cpp:1.40	Tue Aug  9 19:59:40 2005
+++ llvm/lib/Analysis/ScalarEvolution.cpp	Mon Aug 15 18:33:51 2005
@@ -1168,14 +1168,19 @@
 
     /// HowFarToZero - Return the number of times a backedge comparing the
     /// specified value to zero will execute.  If not computable, return
-    /// UnknownValue
+    /// UnknownValue.
     SCEVHandle HowFarToZero(SCEV *V, const Loop *L);
 
     /// HowFarToNonZero - Return the number of times a backedge checking the
     /// specified value for nonzero will execute.  If not computable, return
-    /// UnknownValue
+    /// UnknownValue.
     SCEVHandle HowFarToNonZero(SCEV *V, const Loop *L);
 
+    /// HowManyLessThans - Return the number of times a backedge containing the
+    /// specified less-than comparison will execute.  If not computable, return
+    /// UnknownValue.
+    SCEVHandle HowManyLessThans(SCEV *LHS, SCEV *RHS, const Loop *L);
+
     /// getConstantEvolutionLoopExitValue - If we know that the specified Phi is
     /// in the header of its containing loop, we know the loop executes a
     /// constant number of times, and the PHI node is just a recurrence
@@ -1530,6 +1535,20 @@
       if (!isa<SCEVCouldNotCompute>(TC)) return TC;
     }
     break;
+  case Instruction::SetLT:
+    if (LHS->getType()->isInteger() && 
+        ExitCond->getOperand(0)->getType()->isSigned()) {
+      SCEVHandle TC = HowManyLessThans(LHS, RHS, L);
+      if (!isa<SCEVCouldNotCompute>(TC)) return TC;
+    }
+    break;
+  case Instruction::SetGT:
+    if (LHS->getType()->isInteger() &&
+        ExitCond->getOperand(0)->getType()->isSigned()) {
+      SCEVHandle TC = HowManyLessThans(RHS, LHS, L);
+      if (!isa<SCEVCouldNotCompute>(TC)) return TC;
+    }
+    break;
   default:
 #if 0
     std::cerr << "ComputeIterationCount ";
@@ -2169,6 +2188,95 @@
   return UnknownValue;
 }
 
+/// HowManyLessThans - Return the number of times a backedge containing the
+/// specified less-than comparison will execute.  If not computable, return
+/// UnknownValue.
+SCEVHandle ScalarEvolutionsImpl::
+HowManyLessThans(SCEV *LHS, SCEV *RHS, const Loop *L) {
+  // Only handle:  "ADDREC < LoopInvariant".
+  if (!RHS->isLoopInvariant(L)) return UnknownValue;
+
+  SCEVAddRecExpr *AddRec = dyn_cast<SCEVAddRecExpr>(LHS);
+  if (!AddRec || AddRec->getLoop() != L)
+    return UnknownValue;
+
+  if (AddRec->isAffine()) {
+    // FORNOW: We only support unit strides.
+    SCEVHandle One = SCEVUnknown::getIntegerSCEV(1, RHS->getType());
+    if (AddRec->getOperand(1) != One)
+      return UnknownValue;
+
+    // The number of iterations for "[n,+,1] < m", is m-n.  However, we don't
+    // know that m is >= n on input to the loop.  If it is, the condition return
+    // true zero times.  What we really should return, for full generality, is
+    // SMAX(0, m-n).  Since we cannot check this, we will instead check for a
+    // canonical loop form: most do-loops will have a check that dominates the
+    // loop, that only enters the loop if [n-1]<m.  If we can find this check,
+    // we know that the SMAX will evaluate to m-n, because we know that m >= n.
+
+    // Search for the check.
+    BasicBlock *Preheader = L->getLoopPreheader();
+    BasicBlock *PreheaderDest = L->getHeader();
+    if (Preheader == 0) return UnknownValue;
+
+    BranchInst *LoopEntryPredicate =
+      dyn_cast<BranchInst>(Preheader->getTerminator());
+    if (!LoopEntryPredicate) return UnknownValue;
+
+    // This might be a critical edge broken out.  If the loop preheader ends in
+    // an unconditional branch to the loop, check to see if the preheader has a
+    // single predecessor, and if so, look for its terminator.
+    while (LoopEntryPredicate->isUnconditional()) {
+      PreheaderDest = Preheader;
+      Preheader = Preheader->getSinglePredecessor();
+      if (!Preheader) return UnknownValue;  // Multiple preds.
+      
+      LoopEntryPredicate =
+        dyn_cast<BranchInst>(Preheader->getTerminator());
+      if (!LoopEntryPredicate) return UnknownValue;
+    }
+
+    // Now that we found a conditional branch that dominates the loop, check to
+    // see if it is the comparison we are looking for.
+    SetCondInst *SCI =dyn_cast<SetCondInst>(LoopEntryPredicate->getCondition());
+    if (!SCI) return UnknownValue;
+    Value *PreCondLHS = SCI->getOperand(0);
+    Value *PreCondRHS = SCI->getOperand(1);
+    Instruction::BinaryOps Cond;
+    if (LoopEntryPredicate->getSuccessor(0) == PreheaderDest)
+      Cond = SCI->getOpcode();
+    else
+      Cond = SCI->getInverseCondition();
+    
+    switch (Cond) {
+    case Instruction::SetGT:
+      std::swap(PreCondLHS, PreCondRHS);
+      Cond = Instruction::SetLT;
+      // Fall Through.
+    case Instruction::SetLT:
+      if (PreCondLHS->getType()->isInteger() &&
+          PreCondLHS->getType()->isSigned()) { 
+        if (RHS != getSCEV(PreCondRHS))
+          return UnknownValue;  // Not a comparison against 'm'.
+
+        if (SCEV::getMinusSCEV(AddRec->getOperand(0), One)
+                    != getSCEV(PreCondLHS))
+          return UnknownValue;  // Not a comparison against 'n-1'.
+        break;
+      } else {
+        return UnknownValue;
+      }
+    default: break;
+    }
+
+    //std::cerr << "Computed Loop Trip Count as: " <<
+    //  *SCEV::getMinusSCEV(RHS, AddRec->getOperand(0)) << "\n";
+    return SCEV::getMinusSCEV(RHS, AddRec->getOperand(0));
+  }
+
+  return UnknownValue;
+}
+
 /// getNumIterationsInRange - Return the number of iterations of this loop that
 /// produce values in the specified constant range.  Another way of looking at
 /// this is that it returns the first iteration number where the value is not in





From lattner at cs.uiuc.edu  Mon Aug 15 18:47:16 2005
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Mon, 15 Aug 2005 18:47:16 -0500
Subject: [llvm-commits] 
	CVS: llvm/lib/Target/PowerPC/PowerPCTargetMachine.cpp
Message-ID: <200508152347.SAA10902@zion.cs.uiuc.edu>



Changes in directory llvm/lib/Target/PowerPC:

PowerPCTargetMachine.cpp updated: 1.62 -> 1.63
---
Log message:

Turn loop strength reduction on by default.
Only run createLowerConstantExpressionsPass for the simple isel.  The DAG
isel has no need for it.


---
Diffs of the changes:  (+14 -20)

 PowerPCTargetMachine.cpp |   34 ++++++++++++++--------------------
 1 files changed, 14 insertions(+), 20 deletions(-)


Index: llvm/lib/Target/PowerPC/PowerPCTargetMachine.cpp
diff -u llvm/lib/Target/PowerPC/PowerPCTargetMachine.cpp:1.62 llvm/lib/Target/PowerPC/PowerPCTargetMachine.cpp:1.63
--- llvm/lib/Target/PowerPC/PowerPCTargetMachine.cpp:1.62	Sat Aug 13 00:59:16 2005
+++ llvm/lib/Target/PowerPC/PowerPCTargetMachine.cpp	Mon Aug 15 18:47:04 2005
@@ -7,6 +7,7 @@
 //
 //===----------------------------------------------------------------------===//
 //
+// Top-level implementation for the PowerPC target.
 //
 //===----------------------------------------------------------------------===//
 
@@ -28,9 +29,6 @@
 #include <iostream>
 using namespace llvm;
 
-static cl::opt<bool> EnablePPCLSR("enable-lsr-for-ppc", cl::Hidden,
-                                  cl::desc("Enable LSR for PPC (beta)"));
-
 namespace {
   const std::string PPC32ID = "PowerPC/32bit";
 
@@ -67,11 +65,9 @@
                                                 CodeGenFileType FileType) {
   if (FileType != TargetMachine::AssemblyFile) return true;
 
-  if (EnablePPCLSR) {
-    PM.add(createLoopStrengthReducePass());
-    PM.add(createVerifierPass());
-    PM.add(createCFGSimplificationPass());
-  }
+  // Run loop strength reduction before anything else.
+  PM.add(createLoopStrengthReducePass());
+  PM.add(createCFGSimplificationPass());
 
   // FIXME: Implement efficient support for garbage collection intrinsics.
   PM.add(createLowerGCPass());
@@ -82,15 +78,14 @@
   // FIXME: Implement the switch instruction in the instruction selector!
   PM.add(createLowerSwitchPass());
 
-  PM.add(createLowerConstantExpressionsPass());
-
   // Make sure that no unreachable blocks are instruction selected.
   PM.add(createUnreachableBlockEliminationPass());
 
   // Default to pattern ISel
-  if (PatternISelTriState == 0)
+  if (PatternISelTriState == 0) {
+    PM.add(createLowerConstantExpressionsPass());
     PM.add(createPPC32ISelSimple(*this));
-  else
+  } else
     PM.add(createPPC32ISelPattern(*this));
 
   if (PrintMachineCode)
@@ -126,10 +121,9 @@
   // The JIT does not support or need PIC.
   PICEnabled = false;
 
-  if (EnablePPCLSR) {
-    PM.add(createLoopStrengthReducePass());
-    PM.add(createCFGSimplificationPass());
-  }
+  // Run loop strength reduction before anything else.
+  PM.add(createLoopStrengthReducePass());
+  PM.add(createCFGSimplificationPass());
 
   // FIXME: Implement efficient support for garbage collection intrinsics.
   PM.add(createLowerGCPass());
@@ -140,16 +134,16 @@
   // FIXME: Implement the switch instruction in the instruction selector!
   PM.add(createLowerSwitchPass());
 
-  PM.add(createLowerConstantExpressionsPass());
-
   // Make sure that no unreachable blocks are instruction selected.
   PM.add(createUnreachableBlockEliminationPass());
 
   // Default to pattern ISel
-  if (PatternISelTriState == 0)
+  if (PatternISelTriState == 0) {
+    PM.add(createLowerConstantExpressionsPass());
     PM.add(createPPC32ISelSimple(TM));
-  else
+  } else {
     PM.add(createPPC32ISelPattern(TM));
+  }
 
   PM.add(createRegisterAllocator());
   PM.add(createPrologEpilogCodeInserter());





From lattner at cs.uiuc.edu  Mon Aug 15 18:48:33 2005
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Mon, 15 Aug 2005 18:48:33 -0500
Subject: [llvm-commits] CVS: llvm-test/Makefile.programs 
Message-ID: <200508152348.SAA10982@zion.cs.uiuc.edu>



Changes in directory llvm-test:

Makefile.programs updated: 1.161 -> 1.162
---
Log message:

This flag is gone now.


---
Diffs of the changes:  (+1 -2)

 Makefile.programs |    3 +--
 1 files changed, 1 insertion(+), 2 deletions(-)


Index: llvm-test/Makefile.programs
diff -u llvm-test/Makefile.programs:1.161 llvm-test/Makefile.programs:1.162
--- llvm-test/Makefile.programs:1.161	Sun Aug  7 18:26:17 2005
+++ llvm-test/Makefile.programs	Mon Aug 15 18:48:22 2005
@@ -187,8 +187,7 @@
 endif#DISABLE_DIFFS
 
 ifeq ($(ARCH),PowerPC)
-LLCBETAOPTION := -enable-lsr-for-ppc
-#-enable-gpopt
+LLCBETAOPTION := 
 endif
 ifeq ($(ARCH),Alpha)
 LLCBETAOPTION := -enable-alpha-FTOI -enable-lsr-for-alpha





From lattner at cs.uiuc.edu  Mon Aug 15 19:36:24 2005
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Mon, 15 Aug 2005 19:36:24 -0500
Subject: [llvm-commits] 
	CVS: llvm/test/Regression/Transforms/LoopStrengthReduce/2005-08-15-AddRecIV.ll
Message-ID: <200508160036.TAA11218@zion.cs.uiuc.edu>



Changes in directory llvm/test/Regression/Transforms/LoopStrengthReduce:

2005-08-15-AddRecIV.ll added (r1.1)
---
Log message:

testcase that crashes lsr, distilled from 175.vpr


---
Diffs of the changes:  (+77 -0)

 2005-08-15-AddRecIV.ll |   77 +++++++++++++++++++++++++++++++++++++++++++++++++
 1 files changed, 77 insertions(+)


Index: llvm/test/Regression/Transforms/LoopStrengthReduce/2005-08-15-AddRecIV.ll
diff -c /dev/null llvm/test/Regression/Transforms/LoopStrengthReduce/2005-08-15-AddRecIV.ll:1.1
*** /dev/null	Mon Aug 15 19:36:22 2005
--- llvm/test/Regression/Transforms/LoopStrengthReduce/2005-08-15-AddRecIV.ll	Mon Aug 15 19:36:12 2005
***************
*** 0 ****
--- 1,77 ----
+ ; RUN: llvm-as < %s | opt -loop-reduce -disable-output
+ 
+ void %try_swap() {
+ entry:
+ 	br bool false, label %cond_continue.0.i, label %cond_false.0.i
+ 
+ cond_false.0.i:		; preds = %entry
+ 	ret void
+ 
+ cond_continue.0.i:		; preds = %entry
+ 	br bool false, label %cond_continue.1.i, label %cond_false.1.i
+ 
+ cond_false.1.i:		; preds = %cond_continue.0.i
+ 	ret void
+ 
+ cond_continue.1.i:		; preds = %cond_continue.0.i
+ 	br bool false, label %endif.3.i, label %else.0.i
+ 
+ endif.3.i:		; preds = %cond_continue.1.i
+ 	br bool false, label %my_irand.exit82, label %endif.0.i62
+ 
+ else.0.i:		; preds = %cond_continue.1.i
+ 	ret void
+ 
+ endif.0.i62:		; preds = %endif.3.i
+ 	ret void
+ 
+ my_irand.exit82:		; preds = %endif.3.i
+ 	br bool false, label %else.2, label %then.4
+ 
+ then.4:		; preds = %my_irand.exit82
+ 	ret void
+ 
+ else.2:		; preds = %my_irand.exit82
+ 	br bool false, label %find_affected_nets.exit, label %loopentry.1.i107.outer.preheader
+ 
+ loopentry.1.i107.outer.preheader:		; preds = %else.2
+ 	ret void
+ 
+ find_affected_nets.exit:		; preds = %else.2
+ 	br bool false, label %save_region_occ.exit, label %loopentry.1
+ 
+ save_region_occ.exit:		; preds = %find_affected_nets.exit
+ 	br bool false, label %no_exit.1.preheader, label %loopexit.1
+ 
+ loopentry.1:		; preds = %find_affected_nets.exit
+ 	ret void
+ 
+ no_exit.1.preheader:		; preds = %save_region_occ.exit
+ 	ret void
+ 
+ loopexit.1:		; preds = %save_region_occ.exit
+ 	br bool false, label %then.10, label %loopentry.3
+ 
+ then.10:		; preds = %loopexit.1
+ 	ret void
+ 
+ loopentry.3:		; preds = %endif.16, %loopexit.1
+ 	%indvar342 = phi uint [ %indvar.next343, %endif.16 ], [ 0, %loopexit.1 ]		; <uint> [#uses=2]
+ 	br bool false, label %loopexit.3, label %endif.16
+ 
+ endif.16:		; preds = %loopentry.3
+ 	%indvar.next343 = add uint %indvar342, 1		; <uint> [#uses=1]
+ 	br label %loopentry.3
+ 
+ loopexit.3:		; preds = %loopentry.3
+ 	br label %loopentry.4
+ 
+ loopentry.4:		; preds = %loopentry.4, %loopexit.3
+ 	%indvar340 = phi uint [ 0, %loopexit.3 ], [ %indvar.next341, %loopentry.4 ]		; <uint> [#uses=2]
+ 	%tmp. = add uint %indvar340, %indvar342		; <uint> [#uses=1]
+ 	%tmp.526 = load int** null		; <int*> [#uses=1]
+ 	%tmp.528 = getelementptr int* %tmp.526, uint %tmp.		; <int*> [#uses=1]
+ 	store int 0, int* %tmp.528
+ 	%indvar.next341 = add uint %indvar340, 1		; <uint> [#uses=1]
+ 	br label %loopentry.4
+ }





From lattner at cs.uiuc.edu  Mon Aug 15 19:37:12 2005
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Mon, 15 Aug 2005 19:37:12 -0500
Subject: [llvm-commits] CVS: llvm/lib/Analysis/ScalarEvolution.cpp 
Message-ID: <200508160037.TAA11276@zion.cs.uiuc.edu>



Changes in directory llvm/lib/Analysis:

ScalarEvolution.cpp updated: 1.41 -> 1.42
---
Log message:

Fix Transforms/LoopStrengthReduce/2005-08-15-AddRecIV.ll


---
Diffs of the changes:  (+3 -2)

 ScalarEvolution.cpp |    5 +++--
 1 files changed, 3 insertions(+), 2 deletions(-)


Index: llvm/lib/Analysis/ScalarEvolution.cpp
diff -u llvm/lib/Analysis/ScalarEvolution.cpp:1.41 llvm/lib/Analysis/ScalarEvolution.cpp:1.42
--- llvm/lib/Analysis/ScalarEvolution.cpp:1.41	Mon Aug 15 18:33:51 2005
+++ llvm/lib/Analysis/ScalarEvolution.cpp	Mon Aug 15 19:37:01 2005
@@ -347,8 +347,9 @@
 
 bool SCEVAddRecExpr::isLoopInvariant(const Loop *QueryLoop) const {
   // This recurrence is invariant w.r.t to QueryLoop iff QueryLoop doesn't
-  // contain L.
-  return !QueryLoop->contains(L->getHeader());
+  // contain L and if the start is invariant.
+  return !QueryLoop->contains(L->getHeader()) &&
+         getOperand(0)->isLoopInvariant(QueryLoop);
 }
 
 





From lattner at cs.uiuc.edu  Mon Aug 15 19:38:22 2005
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Mon, 15 Aug 2005 19:38:22 -0500
Subject: [llvm-commits] 
	CVS: llvm/lib/Transforms/Scalar/LoopStrengthReduce.cpp
Message-ID: <200508160038.TAA11309@zion.cs.uiuc.edu>



Changes in directory llvm/lib/Transforms/Scalar:

LoopStrengthReduce.cpp updated: 1.51 -> 1.52
---
Log message:

Fix a bad case in gzip where we put lots of things in registers across the
loop, because a IV-dependent value was used outside of the loop and didn't
have immediate-folding capability


---
Diffs of the changes:  (+17 -9)

 LoopStrengthReduce.cpp |   26 +++++++++++++++++---------
 1 files changed, 17 insertions(+), 9 deletions(-)


Index: llvm/lib/Transforms/Scalar/LoopStrengthReduce.cpp
diff -u llvm/lib/Transforms/Scalar/LoopStrengthReduce.cpp:1.51 llvm/lib/Transforms/Scalar/LoopStrengthReduce.cpp:1.52
--- llvm/lib/Transforms/Scalar/LoopStrengthReduce.cpp:1.51	Sat Aug 13 02:42:01 2005
+++ llvm/lib/Transforms/Scalar/LoopStrengthReduce.cpp	Mon Aug 15 19:38:11 2005
@@ -737,15 +737,23 @@
   // fields of the BasedUsers.  We do this so that it increases the commonality
   // of the remaining uses.
   for (unsigned i = 0, e = UsersToProcess.size(); i != e; ++i) {
-    // Addressing modes can be folded into loads and stores.  Be careful that
-    // the store is through the expression, not of the expression though.
-    bool isAddress = isa<LoadInst>(UsersToProcess[i].Inst);
-    if (StoreInst *SI = dyn_cast<StoreInst>(UsersToProcess[i].Inst))
-      if (SI->getOperand(1) == UsersToProcess[i].OperandValToReplace)
-        isAddress = true;
-    
-    MoveImmediateValues(UsersToProcess[i].Base, UsersToProcess[i].Imm,
-                        isAddress, L);
+    // If the user is not in the current loop, this means it is using the exit
+    // value of the IV.  Do not put anything in the base, make sure it's all in
+    // the immediate field to allow as much factoring as possible.
+    if (!L->contains(UsersToProcess[i].Inst->getParent())) {
+      std::swap(UsersToProcess[i].Base, UsersToProcess[i].Imm);
+    } else {
+      
+      // Addressing modes can be folded into loads and stores.  Be careful that
+      // the store is through the expression, not of the expression though.
+      bool isAddress = isa<LoadInst>(UsersToProcess[i].Inst);
+      if (StoreInst *SI = dyn_cast<StoreInst>(UsersToProcess[i].Inst))
+        if (SI->getOperand(1) == UsersToProcess[i].OperandValToReplace)
+          isAddress = true;
+      
+      MoveImmediateValues(UsersToProcess[i].Base, UsersToProcess[i].Imm,
+                          isAddress, L);
+    }
   }
  
   // Now that we know what we need to do, insert the PHI node itself.





From lattner at cs.uiuc.edu  Tue Aug 16 12:14:53 2005
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Tue, 16 Aug 2005 12:14:53 -0500
Subject: [llvm-commits] CVS: llvm/lib/Target/PowerPC/PPC32ISelLowering.cpp
	PPC32ISelLowering.h PPC32ISelPattern.cpp 
Message-ID: <200508161714.MAA17305@zion.cs.uiuc.edu>



Changes in directory llvm/lib/Target/PowerPC:

PPC32ISelLowering.cpp added (r1.1)
PPC32ISelLowering.h added (r1.1)
PPC32ISelPattern.cpp updated: 1.141 -> 1.142
---
Log message:

Pull the LLVM -> DAG lowering code out of the pattern selector so that it
can be shared with the DAG->DAG selector.


---
Diffs of the changes:  (+526 -484)

 PPC32ISelLowering.cpp |  472 ++++++++++++++++++++++++++++++++++++++++++++++++
 PPC32ISelLowering.h   |   53 +++++
 PPC32ISelPattern.cpp  |  485 --------------------------------------------------
 3 files changed, 526 insertions(+), 484 deletions(-)


Index: llvm/lib/Target/PowerPC/PPC32ISelLowering.cpp
diff -c /dev/null llvm/lib/Target/PowerPC/PPC32ISelLowering.cpp:1.1
*** /dev/null	Tue Aug 16 12:14:52 2005
--- llvm/lib/Target/PowerPC/PPC32ISelLowering.cpp	Tue Aug 16 12:14:42 2005
***************
*** 0 ****
--- 1,472 ----
+ //===-- PPC32ISelLowering.cpp - PPC32 DAG Lowering Implementation ---------===//
+ //
+ //                     The LLVM Compiler Infrastructure
+ //
+ // This file was developed by Chris Lattner and is distributed under
+ // the University of Illinois Open Source License. See LICENSE.TXT for details.
+ //
+ //===----------------------------------------------------------------------===//
+ //
+ // This file implements the PPC32ISelLowering class.
+ //
+ //===----------------------------------------------------------------------===//
+ 
+ #include "PPC32ISelLowering.h"
+ #include "PPC32TargetMachine.h"
+ #include "llvm/CodeGen/MachineFrameInfo.h"
+ #include "llvm/CodeGen/MachineFunction.h"
+ #include "llvm/CodeGen/SelectionDAG.h"
+ #include "llvm/Function.h"
+ 
+ using namespace llvm;
+ 
+ PPC32TargetLowering::PPC32TargetLowering(TargetMachine &TM)
+   : TargetLowering(TM) {
+     
+   // Fold away setcc operations if possible.
+   setSetCCIsExpensive();
+   
+   // Set up the register classes.
+   addRegisterClass(MVT::i32, PPC32::GPRCRegisterClass);
+   addRegisterClass(MVT::f32, PPC32::FPRCRegisterClass);
+   addRegisterClass(MVT::f64, PPC32::FPRCRegisterClass);
+   
+   // PowerPC has no intrinsics for these particular operations
+   setOperationAction(ISD::MEMMOVE, MVT::Other, Expand);
+   setOperationAction(ISD::MEMSET, MVT::Other, Expand);
+   setOperationAction(ISD::MEMCPY, MVT::Other, Expand);
+   
+   // PowerPC has an i16 but no i8 (or i1) SEXTLOAD
+   setOperationAction(ISD::SEXTLOAD, MVT::i1, Expand);
+   setOperationAction(ISD::SEXTLOAD, MVT::i8, Expand);
+   
+   // PowerPC has no SREM/UREM instructions
+   setOperationAction(ISD::SREM, MVT::i32, Expand);
+   setOperationAction(ISD::UREM, MVT::i32, Expand);
+   
+   // We don't support sin/cos/sqrt/fmod
+   setOperationAction(ISD::FSIN , MVT::f64, Expand);
+   setOperationAction(ISD::FCOS , MVT::f64, Expand);
+   setOperationAction(ISD::SREM , MVT::f64, Expand);
+   setOperationAction(ISD::FSIN , MVT::f32, Expand);
+   setOperationAction(ISD::FCOS , MVT::f32, Expand);
+   setOperationAction(ISD::SREM , MVT::f32, Expand);
+   
+   // If we're enabling GP optimizations, use hardware square root
+   if (!TM.getSubtarget<PPCSubtarget>().isGigaProcessor()) {
+     setOperationAction(ISD::FSQRT, MVT::f64, Expand);
+     setOperationAction(ISD::FSQRT, MVT::f32, Expand);
+   }
+   
+   // PowerPC does not have CTPOP or CTTZ
+   setOperationAction(ISD::CTPOP, MVT::i32  , Expand);
+   setOperationAction(ISD::CTTZ , MVT::i32  , Expand);
+   
+   // PowerPC does not have Select
+   setOperationAction(ISD::SELECT, MVT::i32, Expand);
+   setOperationAction(ISD::SELECT, MVT::f32, Expand);
+   setOperationAction(ISD::SELECT, MVT::f64, Expand);
+   
+   // PowerPC does not have FP_TO_UINT
+   setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand);
+   
+   setSetCCResultContents(ZeroOrOneSetCCResult);
+   addLegalFPImmediate(+0.0); // Necessary for FSEL
+   addLegalFPImmediate(-0.0); //
+   
+   computeRegisterProperties();
+ }
+ 
+ std::vector<SDOperand>
+ PPC32TargetLowering::LowerArguments(Function &F, SelectionDAG &DAG) {
+   //
+   // add beautiful description of PPC stack frame format, or at least some docs
+   //
+   MachineFunction &MF = DAG.getMachineFunction();
+   MachineFrameInfo *MFI = MF.getFrameInfo();
+   MachineBasicBlock& BB = MF.front();
+   std::vector<SDOperand> ArgValues;
+   
+   // Due to the rather complicated nature of the PowerPC ABI, rather than a
+   // fixed size array of physical args, for the sake of simplicity let the STL
+   // handle tracking them for us.
+   std::vector<unsigned> argVR, argPR, argOp;
+   unsigned ArgOffset = 24;
+   unsigned GPR_remaining = 8;
+   unsigned FPR_remaining = 13;
+   unsigned GPR_idx = 0, FPR_idx = 0;
+   static const unsigned GPR[] = {
+     PPC::R3, PPC::R4, PPC::R5, PPC::R6,
+     PPC::R7, PPC::R8, PPC::R9, PPC::R10,
+   };
+   static const unsigned FPR[] = {
+     PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7,
+     PPC::F8, PPC::F9, PPC::F10, PPC::F11, PPC::F12, PPC::F13
+   };
+   
+   // Add DAG nodes to load the arguments...  On entry to a function on PPC,
+   // the arguments start at offset 24, although they are likely to be passed
+   // in registers.
+   for (Function::arg_iterator I = F.arg_begin(), E = F.arg_end(); I != E; ++I) {
+     SDOperand newroot, argt;
+     unsigned ObjSize;
+     bool needsLoad = false;
+     bool ArgLive = !I->use_empty();
+     MVT::ValueType ObjectVT = getValueType(I->getType());
+     
+     switch (ObjectVT) {
+       default: assert(0 && "Unhandled argument type!");
+       case MVT::i1:
+       case MVT::i8:
+       case MVT::i16:
+       case MVT::i32:
+         ObjSize = 4;
+         if (!ArgLive) break;
+           if (GPR_remaining > 0) {
+             MF.addLiveIn(GPR[GPR_idx]);
+             argt = newroot = DAG.getCopyFromReg(GPR[GPR_idx], MVT::i32,
+                                                 DAG.getRoot());
+             if (ObjectVT != MVT::i32)
+               argt = DAG.getNode(ISD::TRUNCATE, ObjectVT, newroot);
+           } else {
+             needsLoad = true;
+           }
+             break;
+       case MVT::i64: ObjSize = 8;
+         if (!ArgLive) break;
+           if (GPR_remaining > 0) {
+             SDOperand argHi, argLo;
+             MF.addLiveIn(GPR[GPR_idx]);
+             argHi = DAG.getCopyFromReg(GPR[GPR_idx], MVT::i32, DAG.getRoot());
+             // If we have two or more remaining argument registers, then both halves
+             // of the i64 can be sourced from there.  Otherwise, the lower half will
+             // have to come off the stack.  This can happen when an i64 is preceded
+             // by 28 bytes of arguments.
+             if (GPR_remaining > 1) {
+               MF.addLiveIn(GPR[GPR_idx+1]);
+               argLo = DAG.getCopyFromReg(GPR[GPR_idx+1], MVT::i32, argHi);
+             } else {
+               int FI = MFI->CreateFixedObject(4, ArgOffset+4);
+               SDOperand FIN = DAG.getFrameIndex(FI, MVT::i32);
+               argLo = DAG.getLoad(MVT::i32, DAG.getEntryNode(), FIN,
+                                   DAG.getSrcValue(NULL));
+             }
+             // Build the outgoing arg thingy
+             argt = DAG.getNode(ISD::BUILD_PAIR, MVT::i64, argLo, argHi);
+             newroot = argLo;
+           } else {
+             needsLoad = true;
+           }
+             break;
+       case MVT::f32:
+       case MVT::f64:
+         ObjSize = (ObjectVT == MVT::f64) ? 8 : 4;
+         if (!ArgLive) break;
+           if (FPR_remaining > 0) {
+             MF.addLiveIn(FPR[FPR_idx]);
+             argt = newroot = DAG.getCopyFromReg(FPR[FPR_idx], ObjectVT,
+                                                 DAG.getRoot());
+             --FPR_remaining;
+             ++FPR_idx;
+           } else {
+             needsLoad = true;
+           }
+             break;
+     }
+     
+     // We need to load the argument to a virtual register if we determined above
+     // that we ran out of physical registers of the appropriate type
+     if (needsLoad) {
+       unsigned SubregOffset = 0;
+       if (ObjectVT == MVT::i8 || ObjectVT == MVT::i1) SubregOffset = 3;
+       if (ObjectVT == MVT::i16) SubregOffset = 2;
+       int FI = MFI->CreateFixedObject(ObjSize, ArgOffset);
+       SDOperand FIN = DAG.getFrameIndex(FI, MVT::i32);
+       FIN = DAG.getNode(ISD::ADD, MVT::i32, FIN,
+                         DAG.getConstant(SubregOffset, MVT::i32));
+       argt = newroot = DAG.getLoad(ObjectVT, DAG.getEntryNode(), FIN,
+                                    DAG.getSrcValue(NULL));
+     }
+     
+     // Every 4 bytes of argument space consumes one of the GPRs available for
+     // argument passing.
+     if (GPR_remaining > 0) {
+       unsigned delta = (GPR_remaining > 1 && ObjSize == 8) ? 2 : 1;
+       GPR_remaining -= delta;
+       GPR_idx += delta;
+     }
+     ArgOffset += ObjSize;
+     if (newroot.Val)
+       DAG.setRoot(newroot.getValue(1));
+     
+     ArgValues.push_back(argt);
+   }
+   
+   // If the function takes variable number of arguments, make a frame index for
+   // the start of the first vararg value... for expansion of llvm.va_start.
+   if (F.isVarArg()) {
+     VarArgsFrameIndex = MFI->CreateFixedObject(4, ArgOffset);
+     SDOperand FIN = DAG.getFrameIndex(VarArgsFrameIndex, MVT::i32);
+     // If this function is vararg, store any remaining integer argument regs
+     // to their spots on the stack so that they may be loaded by deferencing the
+     // result of va_next.
+     std::vector<SDOperand> MemOps;
+     for (; GPR_remaining > 0; --GPR_remaining, ++GPR_idx) {
+       MF.addLiveIn(GPR[GPR_idx]);
+       SDOperand Val = DAG.getCopyFromReg(GPR[GPR_idx], MVT::i32, DAG.getRoot());
+       SDOperand Store = DAG.getNode(ISD::STORE, MVT::Other, Val.getValue(1),
+                                     Val, FIN, DAG.getSrcValue(NULL));
+       MemOps.push_back(Store);
+       // Increment the address by four for the next argument to store
+       SDOperand PtrOff = DAG.getConstant(4, getPointerTy());
+       FIN = DAG.getNode(ISD::ADD, MVT::i32, FIN, PtrOff);
+     }
+     DAG.setRoot(DAG.getNode(ISD::TokenFactor, MVT::Other, MemOps));
+   }
+   
+   // Finally, inform the code generator which regs we return values in.
+   switch (getValueType(F.getReturnType())) {
+     default: assert(0 && "Unknown type!");
+     case MVT::isVoid: break;
+     case MVT::i1:
+     case MVT::i8:
+     case MVT::i16:
+     case MVT::i32:
+       MF.addLiveOut(PPC::R3);
+       break;
+     case MVT::i64:
+       MF.addLiveOut(PPC::R3);
+       MF.addLiveOut(PPC::R4);
+       break;
+     case MVT::f32:
+     case MVT::f64:
+       MF.addLiveOut(PPC::F1);
+       break;
+   }
+   
+   return ArgValues;
+ }
+ 
+ std::pair<SDOperand, SDOperand>
+ PPC32TargetLowering::LowerCallTo(SDOperand Chain,
+                                  const Type *RetTy, bool isVarArg,
+                                  unsigned CallingConv, bool isTailCall,
+                                  SDOperand Callee, ArgListTy &Args,
+                                  SelectionDAG &DAG) {
+   // args_to_use will accumulate outgoing args for the ISD::CALL case in
+   // SelectExpr to use to put the arguments in the appropriate registers.
+   std::vector<SDOperand> args_to_use;
+   
+   // Count how many bytes are to be pushed on the stack, including the linkage
+   // area, and parameter passing area.
+   unsigned NumBytes = 24;
+   
+   if (Args.empty()) {
+     Chain = DAG.getNode(ISD::CALLSEQ_START, MVT::Other, Chain,
+                         DAG.getConstant(NumBytes, getPointerTy()));
+   } else {
+     for (unsigned i = 0, e = Args.size(); i != e; ++i)
+       switch (getValueType(Args[i].second)) {
+         default: assert(0 && "Unknown value type!");
+         case MVT::i1:
+         case MVT::i8:
+         case MVT::i16:
+         case MVT::i32:
+         case MVT::f32:
+           NumBytes += 4;
+           break;
+         case MVT::i64:
+         case MVT::f64:
+           NumBytes += 8;
+           break;
+       }
+         
+         // Just to be safe, we'll always reserve the full 24 bytes of linkage area
+         // plus 32 bytes of argument space in case any called code gets funky on us.
+         // (Required by ABI to support var arg)
+         if (NumBytes < 56) NumBytes = 56;
+     
+     // Adjust the stack pointer for the new arguments...
+     // These operations are automatically eliminated by the prolog/epilog pass
+     Chain = DAG.getNode(ISD::CALLSEQ_START, MVT::Other, Chain,
+                         DAG.getConstant(NumBytes, getPointerTy()));
+     
+     // Set up a copy of the stack pointer for use loading and storing any
+     // arguments that may not fit in the registers available for argument
+     // passing.
+     SDOperand StackPtr = DAG.getCopyFromReg(PPC::R1, MVT::i32,
+                                             DAG.getEntryNode());
+     
+     // Figure out which arguments are going to go in registers, and which in
+     // memory.  Also, if this is a vararg function, floating point operations
+     // must be stored to our stack, and loaded into integer regs as well, if
+     // any integer regs are available for argument passing.
+     unsigned ArgOffset = 24;
+     unsigned GPR_remaining = 8;
+     unsigned FPR_remaining = 13;
+     
+     std::vector<SDOperand> MemOps;
+     for (unsigned i = 0, e = Args.size(); i != e; ++i) {
+       // PtrOff will be used to store the current argument to the stack if a
+       // register cannot be found for it.
+       SDOperand PtrOff = DAG.getConstant(ArgOffset, getPointerTy());
+       PtrOff = DAG.getNode(ISD::ADD, MVT::i32, StackPtr, PtrOff);
+       MVT::ValueType ArgVT = getValueType(Args[i].second);
+       
+       switch (ArgVT) {
+         default: assert(0 && "Unexpected ValueType for argument!");
+         case MVT::i1:
+         case MVT::i8:
+         case MVT::i16:
+           // Promote the integer to 32 bits.  If the input type is signed use a
+           // sign extend, otherwise use a zero extend.
+           if (Args[i].second->isSigned())
+             Args[i].first =DAG.getNode(ISD::SIGN_EXTEND, MVT::i32, Args[i].first);
+           else
+             Args[i].first =DAG.getNode(ISD::ZERO_EXTEND, MVT::i32, Args[i].first);
+           // FALL THROUGH
+         case MVT::i32:
+           if (GPR_remaining > 0) {
+             args_to_use.push_back(Args[i].first);
+             --GPR_remaining;
+           } else {
+             MemOps.push_back(DAG.getNode(ISD::STORE, MVT::Other, Chain,
+                                          Args[i].first, PtrOff,
+                                          DAG.getSrcValue(NULL)));
+           }
+           ArgOffset += 4;
+           break;
+         case MVT::i64:
+           // If we have one free GPR left, we can place the upper half of the i64
+           // in it, and store the other half to the stack.  If we have two or more
+           // free GPRs, then we can pass both halves of the i64 in registers.
+           if (GPR_remaining > 0) {
+             SDOperand Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32,
+                                        Args[i].first, DAG.getConstant(1, MVT::i32));
+             SDOperand Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32,
+                                        Args[i].first, DAG.getConstant(0, MVT::i32));
+             args_to_use.push_back(Hi);
+             --GPR_remaining;
+             if (GPR_remaining > 0) {
+               args_to_use.push_back(Lo);
+               --GPR_remaining;
+             } else {
+               SDOperand ConstFour = DAG.getConstant(4, getPointerTy());
+               PtrOff = DAG.getNode(ISD::ADD, MVT::i32, PtrOff, ConstFour);
+               MemOps.push_back(DAG.getNode(ISD::STORE, MVT::Other, Chain,
+                                            Lo, PtrOff, DAG.getSrcValue(NULL)));
+             }
+           } else {
+             MemOps.push_back(DAG.getNode(ISD::STORE, MVT::Other, Chain,
+                                          Args[i].first, PtrOff,
+                                          DAG.getSrcValue(NULL)));
+           }
+           ArgOffset += 8;
+           break;
+         case MVT::f32:
+         case MVT::f64:
+           if (FPR_remaining > 0) {
+             args_to_use.push_back(Args[i].first);
+             --FPR_remaining;
+             if (isVarArg) {
+               SDOperand Store = DAG.getNode(ISD::STORE, MVT::Other, Chain,
+                                             Args[i].first, PtrOff,
+                                             DAG.getSrcValue(NULL));
+               MemOps.push_back(Store);
+               // Float varargs are always shadowed in available integer registers
+               if (GPR_remaining > 0) {
+                 SDOperand Load = DAG.getLoad(MVT::i32, Store, PtrOff,
+                                              DAG.getSrcValue(NULL));
+                 MemOps.push_back(Load);
+                 args_to_use.push_back(Load);
+                 --GPR_remaining;
+               }
+               if (GPR_remaining > 0 && MVT::f64 == ArgVT) {
+                 SDOperand ConstFour = DAG.getConstant(4, getPointerTy());
+                 PtrOff = DAG.getNode(ISD::ADD, MVT::i32, PtrOff, ConstFour);
+                 SDOperand Load = DAG.getLoad(MVT::i32, Store, PtrOff,
+                                              DAG.getSrcValue(NULL));
+                 MemOps.push_back(Load);
+                 args_to_use.push_back(Load);
+                 --GPR_remaining;
+               }
+             } else {
+               // If we have any FPRs remaining, we may also have GPRs remaining.
+               // Args passed in FPRs consume either 1 (f32) or 2 (f64) available
+               // GPRs.
+               if (GPR_remaining > 0) {
+                 args_to_use.push_back(DAG.getNode(ISD::UNDEF, MVT::i32));
+                 --GPR_remaining;
+               }
+               if (GPR_remaining > 0 && MVT::f64 == ArgVT) {
+                 args_to_use.push_back(DAG.getNode(ISD::UNDEF, MVT::i32));
+                 --GPR_remaining;
+               }
+             }
+           } else {
+             MemOps.push_back(DAG.getNode(ISD::STORE, MVT::Other, Chain,
+                                          Args[i].first, PtrOff,
+                                          DAG.getSrcValue(NULL)));
+           }
+           ArgOffset += (ArgVT == MVT::f32) ? 4 : 8;
+           break;
+       }
+     }
+     if (!MemOps.empty())
+       Chain = DAG.getNode(ISD::TokenFactor, MVT::Other, MemOps);
+   }
+   
+   std::vector<MVT::ValueType> RetVals;
+   MVT::ValueType RetTyVT = getValueType(RetTy);
+   if (RetTyVT != MVT::isVoid)
+     RetVals.push_back(RetTyVT);
+   RetVals.push_back(MVT::Other);
+   
+   SDOperand TheCall = SDOperand(DAG.getCall(RetVals,
+                                             Chain, Callee, args_to_use), 0);
+   Chain = TheCall.getValue(RetTyVT != MVT::isVoid);
+   Chain = DAG.getNode(ISD::CALLSEQ_END, MVT::Other, Chain,
+                       DAG.getConstant(NumBytes, getPointerTy()));
+   return std::make_pair(TheCall, Chain);
+ }
+ 
+ SDOperand PPC32TargetLowering::LowerVAStart(SDOperand Chain, SDOperand VAListP,
+                                             Value *VAListV, SelectionDAG &DAG) {
+   // vastart just stores the address of the VarArgsFrameIndex slot into the
+   // memory location argument.
+   SDOperand FR = DAG.getFrameIndex(VarArgsFrameIndex, MVT::i32);
+   return DAG.getNode(ISD::STORE, MVT::Other, Chain, FR, VAListP,
+                      DAG.getSrcValue(VAListV));
+ }
+ 
+ std::pair<SDOperand,SDOperand>
+ PPC32TargetLowering::LowerVAArg(SDOperand Chain,
+                                 SDOperand VAListP, Value *VAListV,
+                                 const Type *ArgTy, SelectionDAG &DAG) {
+   MVT::ValueType ArgVT = getValueType(ArgTy);
+   
+   SDOperand VAList =
+     DAG.getLoad(MVT::i32, Chain, VAListP, DAG.getSrcValue(VAListV));
+   SDOperand Result = DAG.getLoad(ArgVT, Chain, VAList, DAG.getSrcValue(NULL));
+   unsigned Amt;
+   if (ArgVT == MVT::i32 || ArgVT == MVT::f32)
+     Amt = 4;
+   else {
+     assert((ArgVT == MVT::i64 || ArgVT == MVT::f64) &&
+            "Other types should have been promoted for varargs!");
+     Amt = 8;
+   }
+   VAList = DAG.getNode(ISD::ADD, VAList.getValueType(), VAList,
+                        DAG.getConstant(Amt, VAList.getValueType()));
+   Chain = DAG.getNode(ISD::STORE, MVT::Other, Chain,
+                       VAList, VAListP, DAG.getSrcValue(VAListV));
+   return std::make_pair(Result, Chain);
+ }
+ 
+ 
+ std::pair<SDOperand, SDOperand> PPC32TargetLowering::
+ LowerFrameReturnAddress(bool isFrameAddress, SDOperand Chain, unsigned Depth,
+                         SelectionDAG &DAG) {
+   assert(0 && "LowerFrameReturnAddress unimplemented");
+   abort();
+ }


Index: llvm/lib/Target/PowerPC/PPC32ISelLowering.h
diff -c /dev/null llvm/lib/Target/PowerPC/PPC32ISelLowering.h:1.1
*** /dev/null	Tue Aug 16 12:14:53 2005
--- llvm/lib/Target/PowerPC/PPC32ISelLowering.h	Tue Aug 16 12:14:42 2005
***************
*** 0 ****
--- 1,53 ----
+ //===-- PPC32ISelLowering.cpp - PPC32 DAG Lowering Impl. --------*- C++ -*-===//
+ //
+ //                     The LLVM Compiler Infrastructure
+ //
+ // This file was developed by Chris Lattner and is distributed under
+ // the University of Illinois Open Source License. See LICENSE.TXT for details.
+ //
+ //===----------------------------------------------------------------------===//
+ //
+ // This file defines the interfaces that PPC uses to lower LLVM code into a
+ // selection DAG.
+ //
+ //===----------------------------------------------------------------------===//
+ 
+ #ifndef LLVM_TARGET_POWERPC_PPC32ISELLOWERING_H
+ #define LLVM_TARGET_POWERPC_PPC32ISELLOWERING_H
+ 
+ #include "llvm/Target/TargetLowering.h"
+ 
+ namespace llvm {
+   class PPC32TargetLowering : public TargetLowering {
+     int VarArgsFrameIndex;            // FrameIndex for start of varargs area.
+     int ReturnAddrIndex;              // FrameIndex for return slot.
+   public:
+     PPC32TargetLowering(TargetMachine &TM);
+     
+     /// LowerArguments - This hook must be implemented to indicate how we should
+     /// lower the arguments for the specified function, into the specified DAG.
+     virtual std::vector<SDOperand>
+       LowerArguments(Function &F, SelectionDAG &DAG);
+     
+     /// LowerCallTo - This hook lowers an abstract call to a function into an
+     /// actual call.
+     virtual std::pair<SDOperand, SDOperand>
+       LowerCallTo(SDOperand Chain, const Type *RetTy, bool isVarArg,
+                   unsigned CC,
+                   bool isTailCall, SDOperand Callee, ArgListTy &Args,
+                   SelectionDAG &DAG);
+     
+     virtual SDOperand LowerVAStart(SDOperand Chain, SDOperand VAListP,
+                                    Value *VAListV, SelectionDAG &DAG);
+     
+     virtual std::pair<SDOperand,SDOperand>
+       LowerVAArg(SDOperand Chain, SDOperand VAListP, Value *VAListV,
+                  const Type *ArgTy, SelectionDAG &DAG);
+     
+     virtual std::pair<SDOperand, SDOperand>
+       LowerFrameReturnAddress(bool isFrameAddr, SDOperand Chain, unsigned Depth,
+                               SelectionDAG &DAG);
+   };
+ }
+ 
+ #endif   // LLVM_TARGET_POWERPC_PPC32ISELLOWERING_H


Index: llvm/lib/Target/PowerPC/PPC32ISelPattern.cpp
diff -u llvm/lib/Target/PowerPC/PPC32ISelPattern.cpp:1.141 llvm/lib/Target/PowerPC/PPC32ISelPattern.cpp:1.142
--- llvm/lib/Target/PowerPC/PPC32ISelPattern.cpp:1.141	Mon Aug 15 12:35:26 2005
+++ llvm/lib/Target/PowerPC/PPC32ISelPattern.cpp	Tue Aug 16 12:14:42 2005
@@ -17,6 +17,7 @@
 #include "PowerPCInstrBuilder.h"
 #include "PowerPCInstrInfo.h"
 #include "PPC32TargetMachine.h"
+#include "PPC32ISelLowering.h"
 #include "llvm/Constants.h"
 #include "llvm/Function.h"
 #include "llvm/CodeGen/MachineConstantPool.h"
@@ -26,7 +27,6 @@
 #include "llvm/CodeGen/SelectionDAGISel.h"
 #include "llvm/CodeGen/SSARegMap.h"
 #include "llvm/Target/TargetData.h"
-#include "llvm/Target/TargetLowering.h"
 #include "llvm/Target/TargetOptions.h"
 #include "llvm/Support/Debug.h"
 #include "llvm/Support/MathExtras.h"
@@ -35,489 +35,6 @@
 #include <algorithm>
 using namespace llvm;
 
-
-//===----------------------------------------------------------------------===//
-//  PPC32TargetLowering - PPC32 Implementation of the TargetLowering interface
-namespace {
-  class PPC32TargetLowering : public TargetLowering {
-    int VarArgsFrameIndex;            // FrameIndex for start of varargs area.
-    int ReturnAddrIndex;              // FrameIndex for return slot.
-  public:
-    PPC32TargetLowering(TargetMachine &TM) : TargetLowering(TM) {
-      // Fold away setcc operations if possible.
-      setSetCCIsExpensive();
-
-      // Set up the register classes.
-      addRegisterClass(MVT::i32, PPC32::GPRCRegisterClass);
-      addRegisterClass(MVT::f32, PPC32::FPRCRegisterClass);
-      addRegisterClass(MVT::f64, PPC32::FPRCRegisterClass);
-
-      // PowerPC has no intrinsics for these particular operations
-      setOperationAction(ISD::MEMMOVE, MVT::Other, Expand);
-      setOperationAction(ISD::MEMSET, MVT::Other, Expand);
-      setOperationAction(ISD::MEMCPY, MVT::Other, Expand);
-
-      // PowerPC has an i16 but no i8 (or i1) SEXTLOAD
-      setOperationAction(ISD::SEXTLOAD, MVT::i1, Expand);
-      setOperationAction(ISD::SEXTLOAD, MVT::i8, Expand);
-
-      // PowerPC has no SREM/UREM instructions
-      setOperationAction(ISD::SREM, MVT::i32, Expand);
-      setOperationAction(ISD::UREM, MVT::i32, Expand);
-
-      // We don't support sin/cos/sqrt/fmod
-      setOperationAction(ISD::FSIN , MVT::f64, Expand);
-      setOperationAction(ISD::FCOS , MVT::f64, Expand);
-      setOperationAction(ISD::SREM , MVT::f64, Expand);
-      setOperationAction(ISD::FSIN , MVT::f32, Expand);
-      setOperationAction(ISD::FCOS , MVT::f32, Expand);
-      setOperationAction(ISD::SREM , MVT::f32, Expand);
-
-      // If we're enabling GP optimizations, use hardware square root
-      if (!TM.getSubtarget<PPCSubtarget>().isGigaProcessor()) {
-        setOperationAction(ISD::FSQRT, MVT::f64, Expand);
-        setOperationAction(ISD::FSQRT, MVT::f32, Expand);
-      }
-
-      // PowerPC does not have CTPOP or CTTZ
-      setOperationAction(ISD::CTPOP, MVT::i32  , Expand);
-      setOperationAction(ISD::CTTZ , MVT::i32  , Expand);
-      
-      // PowerPC does not have Select
-      setOperationAction(ISD::SELECT, MVT::i32, Expand);
-      setOperationAction(ISD::SELECT, MVT::f32, Expand);
-      setOperationAction(ISD::SELECT, MVT::f64, Expand);
-
-      // PowerPC does not have FP_TO_UINT
-      setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand);
-      
-      setSetCCResultContents(ZeroOrOneSetCCResult);
-      addLegalFPImmediate(+0.0); // Necessary for FSEL
-      addLegalFPImmediate(-0.0); //
-
-      computeRegisterProperties();
-    }
-
-    /// LowerArguments - This hook must be implemented to indicate how we should
-    /// lower the arguments for the specified function, into the specified DAG.
-    virtual std::vector<SDOperand>
-    LowerArguments(Function &F, SelectionDAG &DAG);
-
-    /// LowerCallTo - This hook lowers an abstract call to a function into an
-    /// actual call.
-    virtual std::pair<SDOperand, SDOperand>
-    LowerCallTo(SDOperand Chain, const Type *RetTy, bool isVarArg, unsigned CC,
-                bool isTailCall, SDOperand Callee, ArgListTy &Args,
-                SelectionDAG &DAG);
-
-    virtual SDOperand LowerVAStart(SDOperand Chain, SDOperand VAListP,
-                                   Value *VAListV, SelectionDAG &DAG);
-
-    virtual std::pair<SDOperand,SDOperand>
-      LowerVAArg(SDOperand Chain, SDOperand VAListP, Value *VAListV,
-                 const Type *ArgTy, SelectionDAG &DAG);
-
-    virtual std::pair<SDOperand, SDOperand>
-    LowerFrameReturnAddress(bool isFrameAddr, SDOperand Chain, unsigned Depth,
-                            SelectionDAG &DAG);
-  };
-}
-
-
-std::vector<SDOperand>
-PPC32TargetLowering::LowerArguments(Function &F, SelectionDAG &DAG) {
-  //
-  // add beautiful description of PPC stack frame format, or at least some docs
-  //
-  MachineFunction &MF = DAG.getMachineFunction();
-  MachineFrameInfo *MFI = MF.getFrameInfo();
-  MachineBasicBlock& BB = MF.front();
-  std::vector<SDOperand> ArgValues;
-
-  // Due to the rather complicated nature of the PowerPC ABI, rather than a
-  // fixed size array of physical args, for the sake of simplicity let the STL
-  // handle tracking them for us.
-  std::vector<unsigned> argVR, argPR, argOp;
-  unsigned ArgOffset = 24;
-  unsigned GPR_remaining = 8;
-  unsigned FPR_remaining = 13;
-  unsigned GPR_idx = 0, FPR_idx = 0;
-  static const unsigned GPR[] = {
-    PPC::R3, PPC::R4, PPC::R5, PPC::R6,
-    PPC::R7, PPC::R8, PPC::R9, PPC::R10,
-  };
-  static const unsigned FPR[] = {
-    PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7,
-    PPC::F8, PPC::F9, PPC::F10, PPC::F11, PPC::F12, PPC::F13
-  };
-
-  // Add DAG nodes to load the arguments...  On entry to a function on PPC,
-  // the arguments start at offset 24, although they are likely to be passed
-  // in registers.
-  for (Function::arg_iterator I = F.arg_begin(), E = F.arg_end(); I != E; ++I) {
-    SDOperand newroot, argt;
-    unsigned ObjSize;
-    bool needsLoad = false;
-    bool ArgLive = !I->use_empty();
-    MVT::ValueType ObjectVT = getValueType(I->getType());
-
-    switch (ObjectVT) {
-    default: assert(0 && "Unhandled argument type!");
-    case MVT::i1:
-    case MVT::i8:
-    case MVT::i16:
-    case MVT::i32:
-      ObjSize = 4;
-      if (!ArgLive) break;
-      if (GPR_remaining > 0) {
-        MF.addLiveIn(GPR[GPR_idx]);
-        argt = newroot = DAG.getCopyFromReg(GPR[GPR_idx], MVT::i32,
-                                            DAG.getRoot());
-        if (ObjectVT != MVT::i32)
-          argt = DAG.getNode(ISD::TRUNCATE, ObjectVT, newroot);
-      } else {
-        needsLoad = true;
-      }
-      break;
-      case MVT::i64: ObjSize = 8;
-      if (!ArgLive) break;
-      if (GPR_remaining > 0) {
-        SDOperand argHi, argLo;
-        MF.addLiveIn(GPR[GPR_idx]);
-        argHi = DAG.getCopyFromReg(GPR[GPR_idx], MVT::i32, DAG.getRoot());
-        // If we have two or more remaining argument registers, then both halves
-        // of the i64 can be sourced from there.  Otherwise, the lower half will
-        // have to come off the stack.  This can happen when an i64 is preceded
-        // by 28 bytes of arguments.
-        if (GPR_remaining > 1) {
-          MF.addLiveIn(GPR[GPR_idx+1]);
-          argLo = DAG.getCopyFromReg(GPR[GPR_idx+1], MVT::i32, argHi);
-        } else {
-          int FI = MFI->CreateFixedObject(4, ArgOffset+4);
-          SDOperand FIN = DAG.getFrameIndex(FI, MVT::i32);
-          argLo = DAG.getLoad(MVT::i32, DAG.getEntryNode(), FIN,
-                              DAG.getSrcValue(NULL));
-        }
-        // Build the outgoing arg thingy
-        argt = DAG.getNode(ISD::BUILD_PAIR, MVT::i64, argLo, argHi);
-        newroot = argLo;
-      } else {
-        needsLoad = true;
-      }
-      break;
-      case MVT::f32:
-      case MVT::f64:
-      ObjSize = (ObjectVT == MVT::f64) ? 8 : 4;
-      if (!ArgLive) break;
-      if (FPR_remaining > 0) {
-        MF.addLiveIn(FPR[FPR_idx]);
-        argt = newroot = DAG.getCopyFromReg(FPR[FPR_idx], ObjectVT,
-                                            DAG.getRoot());
-        --FPR_remaining;
-        ++FPR_idx;
-      } else {
-        needsLoad = true;
-      }
-      break;
-    }
-
-    // We need to load the argument to a virtual register if we determined above
-    // that we ran out of physical registers of the appropriate type
-    if (needsLoad) {
-      unsigned SubregOffset = 0;
-      if (ObjectVT == MVT::i8 || ObjectVT == MVT::i1) SubregOffset = 3;
-      if (ObjectVT == MVT::i16) SubregOffset = 2;
-      int FI = MFI->CreateFixedObject(ObjSize, ArgOffset);
-      SDOperand FIN = DAG.getFrameIndex(FI, MVT::i32);
-      FIN = DAG.getNode(ISD::ADD, MVT::i32, FIN,
-                        DAG.getConstant(SubregOffset, MVT::i32));
-      argt = newroot = DAG.getLoad(ObjectVT, DAG.getEntryNode(), FIN,
-                                   DAG.getSrcValue(NULL));
-    }
-
-    // Every 4 bytes of argument space consumes one of the GPRs available for
-    // argument passing.
-    if (GPR_remaining > 0) {
-      unsigned delta = (GPR_remaining > 1 && ObjSize == 8) ? 2 : 1;
-      GPR_remaining -= delta;
-      GPR_idx += delta;
-    }
-    ArgOffset += ObjSize;
-    if (newroot.Val)
-      DAG.setRoot(newroot.getValue(1));
-
-    ArgValues.push_back(argt);
-  }
-
-  // If the function takes variable number of arguments, make a frame index for
-  // the start of the first vararg value... for expansion of llvm.va_start.
-  if (F.isVarArg()) {
-    VarArgsFrameIndex = MFI->CreateFixedObject(4, ArgOffset);
-    SDOperand FIN = DAG.getFrameIndex(VarArgsFrameIndex, MVT::i32);
-    // If this function is vararg, store any remaining integer argument regs
-    // to their spots on the stack so that they may be loaded by deferencing the
-    // result of va_next.
-    std::vector<SDOperand> MemOps;
-    for (; GPR_remaining > 0; --GPR_remaining, ++GPR_idx) {
-      MF.addLiveIn(GPR[GPR_idx]);
-      SDOperand Val = DAG.getCopyFromReg(GPR[GPR_idx], MVT::i32, DAG.getRoot());
-      SDOperand Store = DAG.getNode(ISD::STORE, MVT::Other, Val.getValue(1),
-                                    Val, FIN, DAG.getSrcValue(NULL));
-      MemOps.push_back(Store);
-      // Increment the address by four for the next argument to store
-      SDOperand PtrOff = DAG.getConstant(4, getPointerTy());
-      FIN = DAG.getNode(ISD::ADD, MVT::i32, FIN, PtrOff);
-    }
-    DAG.setRoot(DAG.getNode(ISD::TokenFactor, MVT::Other, MemOps));
-  }
-
-  // Finally, inform the code generator which regs we return values in.
-  switch (getValueType(F.getReturnType())) {
-  default: assert(0 && "Unknown type!");
-  case MVT::isVoid: break;
-  case MVT::i1:
-  case MVT::i8:
-  case MVT::i16:
-  case MVT::i32:
-    MF.addLiveOut(PPC::R3);
-    break;
-  case MVT::i64:
-    MF.addLiveOut(PPC::R3);
-    MF.addLiveOut(PPC::R4);
-    break;
-  case MVT::f32:
-  case MVT::f64:
-    MF.addLiveOut(PPC::F1);
-    break;
-  }
-
-  return ArgValues;
-}
-
-std::pair<SDOperand, SDOperand>
-PPC32TargetLowering::LowerCallTo(SDOperand Chain,
-                                 const Type *RetTy, bool isVarArg,
-                                 unsigned CallingConv, bool isTailCall,
-                                 SDOperand Callee, ArgListTy &Args,
-                                 SelectionDAG &DAG) {
-  // args_to_use will accumulate outgoing args for the ISD::CALL case in
-  // SelectExpr to use to put the arguments in the appropriate registers.
-  std::vector<SDOperand> args_to_use;
-
-  // Count how many bytes are to be pushed on the stack, including the linkage
-  // area, and parameter passing area.
-  unsigned NumBytes = 24;
-
-  if (Args.empty()) {
-    Chain = DAG.getNode(ISD::CALLSEQ_START, MVT::Other, Chain,
-                        DAG.getConstant(NumBytes, getPointerTy()));
-  } else {
-    for (unsigned i = 0, e = Args.size(); i != e; ++i)
-      switch (getValueType(Args[i].second)) {
-      default: assert(0 && "Unknown value type!");
-      case MVT::i1:
-      case MVT::i8:
-      case MVT::i16:
-      case MVT::i32:
-      case MVT::f32:
-        NumBytes += 4;
-        break;
-      case MVT::i64:
-      case MVT::f64:
-        NumBytes += 8;
-        break;
-      }
-
-    // Just to be safe, we'll always reserve the full 24 bytes of linkage area
-    // plus 32 bytes of argument space in case any called code gets funky on us.
-    // (Required by ABI to support var arg)
-    if (NumBytes < 56) NumBytes = 56;
-
-    // Adjust the stack pointer for the new arguments...
-    // These operations are automatically eliminated by the prolog/epilog pass
-    Chain = DAG.getNode(ISD::CALLSEQ_START, MVT::Other, Chain,
-                        DAG.getConstant(NumBytes, getPointerTy()));
-
-    // Set up a copy of the stack pointer for use loading and storing any
-    // arguments that may not fit in the registers available for argument
-    // passing.
-    SDOperand StackPtr = DAG.getCopyFromReg(PPC::R1, MVT::i32,
-                                            DAG.getEntryNode());
-
-    // Figure out which arguments are going to go in registers, and which in
-    // memory.  Also, if this is a vararg function, floating point operations
-    // must be stored to our stack, and loaded into integer regs as well, if
-    // any integer regs are available for argument passing.
-    unsigned ArgOffset = 24;
-    unsigned GPR_remaining = 8;
-    unsigned FPR_remaining = 13;
-
-    std::vector<SDOperand> MemOps;
-    for (unsigned i = 0, e = Args.size(); i != e; ++i) {
-      // PtrOff will be used to store the current argument to the stack if a
-      // register cannot be found for it.
-      SDOperand PtrOff = DAG.getConstant(ArgOffset, getPointerTy());
-      PtrOff = DAG.getNode(ISD::ADD, MVT::i32, StackPtr, PtrOff);
-      MVT::ValueType ArgVT = getValueType(Args[i].second);
-
-      switch (ArgVT) {
-      default: assert(0 && "Unexpected ValueType for argument!");
-      case MVT::i1:
-      case MVT::i8:
-      case MVT::i16:
-        // Promote the integer to 32 bits.  If the input type is signed use a
-        // sign extend, otherwise use a zero extend.
-        if (Args[i].second->isSigned())
-          Args[i].first =DAG.getNode(ISD::SIGN_EXTEND, MVT::i32, Args[i].first);
-        else
-          Args[i].first =DAG.getNode(ISD::ZERO_EXTEND, MVT::i32, Args[i].first);
-        // FALL THROUGH
-      case MVT::i32:
-        if (GPR_remaining > 0) {
-          args_to_use.push_back(Args[i].first);
-          --GPR_remaining;
-        } else {
-          MemOps.push_back(DAG.getNode(ISD::STORE, MVT::Other, Chain,
-                                       Args[i].first, PtrOff,
-                                       DAG.getSrcValue(NULL)));
-        }
-        ArgOffset += 4;
-        break;
-      case MVT::i64:
-        // If we have one free GPR left, we can place the upper half of the i64
-        // in it, and store the other half to the stack.  If we have two or more
-        // free GPRs, then we can pass both halves of the i64 in registers.
-        if (GPR_remaining > 0) {
-          SDOperand Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32,
-            Args[i].first, DAG.getConstant(1, MVT::i32));
-          SDOperand Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32,
-            Args[i].first, DAG.getConstant(0, MVT::i32));
-          args_to_use.push_back(Hi);
-          --GPR_remaining;
-          if (GPR_remaining > 0) {
-            args_to_use.push_back(Lo);
-            --GPR_remaining;
-          } else {
-            SDOperand ConstFour = DAG.getConstant(4, getPointerTy());
-            PtrOff = DAG.getNode(ISD::ADD, MVT::i32, PtrOff, ConstFour);
-            MemOps.push_back(DAG.getNode(ISD::STORE, MVT::Other, Chain,
-                                         Lo, PtrOff, DAG.getSrcValue(NULL)));
-          }
-        } else {
-          MemOps.push_back(DAG.getNode(ISD::STORE, MVT::Other, Chain,
-                                       Args[i].first, PtrOff,
-                                       DAG.getSrcValue(NULL)));
-        }
-        ArgOffset += 8;
-        break;
-      case MVT::f32:
-      case MVT::f64:
-        if (FPR_remaining > 0) {
-          args_to_use.push_back(Args[i].first);
-          --FPR_remaining;
-          if (isVarArg) {
-            SDOperand Store = DAG.getNode(ISD::STORE, MVT::Other, Chain,
-                                          Args[i].first, PtrOff,
-                                          DAG.getSrcValue(NULL));
-            MemOps.push_back(Store);
-            // Float varargs are always shadowed in available integer registers
-            if (GPR_remaining > 0) {
-              SDOperand Load = DAG.getLoad(MVT::i32, Store, PtrOff,
-                                           DAG.getSrcValue(NULL));
-              MemOps.push_back(Load);
-              args_to_use.push_back(Load);
-              --GPR_remaining;
-            }
-            if (GPR_remaining > 0 && MVT::f64 == ArgVT) {
-              SDOperand ConstFour = DAG.getConstant(4, getPointerTy());
-              PtrOff = DAG.getNode(ISD::ADD, MVT::i32, PtrOff, ConstFour);
-              SDOperand Load = DAG.getLoad(MVT::i32, Store, PtrOff,
-                                           DAG.getSrcValue(NULL));
-              MemOps.push_back(Load);
-              args_to_use.push_back(Load);
-              --GPR_remaining;
-            }
-          } else {
-            // If we have any FPRs remaining, we may also have GPRs remaining.
-            // Args passed in FPRs consume either 1 (f32) or 2 (f64) available
-            // GPRs.
-            if (GPR_remaining > 0) {
-              args_to_use.push_back(DAG.getNode(ISD::UNDEF, MVT::i32));
-              --GPR_remaining;
-            }
-            if (GPR_remaining > 0 && MVT::f64 == ArgVT) {
-              args_to_use.push_back(DAG.getNode(ISD::UNDEF, MVT::i32));
-              --GPR_remaining;
-            }
-          }
-        } else {
-          MemOps.push_back(DAG.getNode(ISD::STORE, MVT::Other, Chain,
-                                       Args[i].first, PtrOff,
-                                       DAG.getSrcValue(NULL)));
-        }
-        ArgOffset += (ArgVT == MVT::f32) ? 4 : 8;
-        break;
-      }
-    }
-    if (!MemOps.empty())
-      Chain = DAG.getNode(ISD::TokenFactor, MVT::Other, MemOps);
-  }
-
-  std::vector<MVT::ValueType> RetVals;
-  MVT::ValueType RetTyVT = getValueType(RetTy);
-  if (RetTyVT != MVT::isVoid)
-    RetVals.push_back(RetTyVT);
-  RetVals.push_back(MVT::Other);
-
-  SDOperand TheCall = SDOperand(DAG.getCall(RetVals,
-                                            Chain, Callee, args_to_use), 0);
-  Chain = TheCall.getValue(RetTyVT != MVT::isVoid);
-  Chain = DAG.getNode(ISD::CALLSEQ_END, MVT::Other, Chain,
-                      DAG.getConstant(NumBytes, getPointerTy()));
-  return std::make_pair(TheCall, Chain);
-}
-
-SDOperand PPC32TargetLowering::LowerVAStart(SDOperand Chain, SDOperand VAListP,
-                                            Value *VAListV, SelectionDAG &DAG) {
-  // vastart just stores the address of the VarArgsFrameIndex slot into the
-  // memory location argument.
-  SDOperand FR = DAG.getFrameIndex(VarArgsFrameIndex, MVT::i32);
-  return DAG.getNode(ISD::STORE, MVT::Other, Chain, FR, VAListP,
-                     DAG.getSrcValue(VAListV));
-}
-
-std::pair<SDOperand,SDOperand>
-PPC32TargetLowering::LowerVAArg(SDOperand Chain,
-                                SDOperand VAListP, Value *VAListV,
-                                const Type *ArgTy, SelectionDAG &DAG) {
-  MVT::ValueType ArgVT = getValueType(ArgTy);
-
-  SDOperand VAList =
-    DAG.getLoad(MVT::i32, Chain, VAListP, DAG.getSrcValue(VAListV));
-  SDOperand Result = DAG.getLoad(ArgVT, Chain, VAList, DAG.getSrcValue(NULL));
-  unsigned Amt;
-  if (ArgVT == MVT::i32 || ArgVT == MVT::f32)
-    Amt = 4;
-  else {
-    assert((ArgVT == MVT::i64 || ArgVT == MVT::f64) &&
-           "Other types should have been promoted for varargs!");
-    Amt = 8;
-  }
-  VAList = DAG.getNode(ISD::ADD, VAList.getValueType(), VAList,
-                      DAG.getConstant(Amt, VAList.getValueType()));
-  Chain = DAG.getNode(ISD::STORE, MVT::Other, Chain,
-                      VAList, VAListP, DAG.getSrcValue(VAListV));
-  return std::make_pair(Result, Chain);
-}
-
-
-std::pair<SDOperand, SDOperand> PPC32TargetLowering::
-LowerFrameReturnAddress(bool isFrameAddress, SDOperand Chain, unsigned Depth,
-                        SelectionDAG &DAG) {
-  assert(0 && "LowerFrameReturnAddress unimplemented");
-  abort();
-}
-
 namespace {
 Statistic<>Recorded("ppc-codegen", "Number of recording ops emitted");
 Statistic<>FusedFP("ppc-codegen", "Number of fused fp operations");





From lattner at cs.uiuc.edu  Tue Aug 16 13:16:35 2005
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Tue, 16 Aug 2005 13:16:35 -0500
Subject: [llvm-commits] CVS: llvm/include/llvm/CodeGen/SelectionDAG.h
	SelectionDAGNodes.h 
Message-ID: <200508161816.NAA21337@zion.cs.uiuc.edu>



Changes in directory llvm/include/llvm/CodeGen:

SelectionDAG.h updated: 1.36 -> 1.37
SelectionDAGNodes.h updated: 1.47 -> 1.48
---
Log message:

add some methods for dag->dag isel


---
Diffs of the changes:  (+40 -9)

 SelectionDAG.h      |   19 ++++++++++++++-----
 SelectionDAGNodes.h |   30 ++++++++++++++++++++++++++----
 2 files changed, 40 insertions(+), 9 deletions(-)


Index: llvm/include/llvm/CodeGen/SelectionDAG.h
diff -u llvm/include/llvm/CodeGen/SelectionDAG.h:1.36 llvm/include/llvm/CodeGen/SelectionDAG.h:1.37
--- llvm/include/llvm/CodeGen/SelectionDAG.h:1.36	Sat Aug 13 01:14:17 2005
+++ llvm/include/llvm/CodeGen/SelectionDAG.h	Tue Aug 16 13:16:24 2005
@@ -204,14 +204,23 @@
   // getSrcValue - construct a node to track a Value* through the backend
   SDOperand getSrcValue(const Value* I, int offset = 0);
 
-  void replaceAllUsesWith(SDOperand Old, SDOperand New) {
-    assert(Old != New && "RAUW self!");
-    assert(0 && "Unimplemented!");
-  }
-
+  
+  /// SelectNodeTo - These are used for target selectors to *mutate* the
+  /// specified node to have the specified return type, Target opcode, and
+  /// operands.  Note that target opcodes are stored as
+  /// ISD::BUILTIN_OP_END+TargetOpcode in the node opcode field.
+  void SelectNodeTo(SDNode *N, MVT::ValueType VT, unsigned TargetOpc,
+                    SDOperand Op1);
+  void SelectNodeTo(SDNode *N, MVT::ValueType VT, unsigned TargetOpc,
+                    SDOperand Op1, SDOperand Op2);
+  void SelectNodeTo(SDNode *N, MVT::ValueType VT, unsigned TargetOpc,
+                    SDOperand Op1, SDOperand Op2, SDOperand Op3);
+  
+  
   void dump() const;
 
 private:
+  void RemoveNodeFromCSEMaps(SDNode *N);
   void DeleteNodeIfDead(SDNode *N, void *NodeSet);
   
   /// SimplifySetCC - Try to simplify a setcc built with the specified operands 


Index: llvm/include/llvm/CodeGen/SelectionDAGNodes.h
diff -u llvm/include/llvm/CodeGen/SelectionDAGNodes.h:1.47 llvm/include/llvm/CodeGen/SelectionDAGNodes.h:1.48
--- llvm/include/llvm/CodeGen/SelectionDAGNodes.h:1.47	Wed Aug 10 15:50:42 2005
+++ llvm/include/llvm/CodeGen/SelectionDAGNodes.h	Tue Aug 16 13:16:24 2005
@@ -592,10 +592,17 @@
     NodeDepth = ND+1;
   }
 
-  virtual ~SDNode() {
-    // FIXME: Drop uses.
-  }
+  virtual ~SDNode() {}
 
+  /// MorphNodeTo - This clears the return value and operands list, and sets the
+  /// opcode of the node to the specified value.  This should only be used by
+  /// the SelectionDAG class.
+  void MorphNodeTo(unsigned Opc) {
+    NodeType = Opc;
+    Values.clear();
+    Operands.clear();
+  }
+  
   void setValueTypes(MVT::ValueType VT) {
     Values.reserve(1);
     Values.push_back(VT);
@@ -609,7 +616,22 @@
   void setValueTypes(std::vector<MVT::ValueType> &VTs) {
     std::swap(Values, VTs);
   }
-
+  
+  void setOperands(SDOperand Op0) {
+    Operands.reserve(1);
+    Operands.push_back(Op0);
+  }
+  void setOperands(SDOperand Op0, SDOperand Op1) {
+    Operands.reserve(2);
+    Operands.push_back(Op0);
+    Operands.push_back(Op1);
+  }
+  void setOperands(SDOperand Op0, SDOperand Op1, SDOperand Op2) {
+    Operands.reserve(3);
+    Operands.push_back(Op0);
+    Operands.push_back(Op1);
+    Operands.push_back(Op2);
+  }
   void removeUser(SDNode *User) {
     // Remove this user from the operand's use list.
     for (unsigned i = Uses.size(); ; --i) {





From lattner at cs.uiuc.edu  Tue Aug 16 13:17:21 2005
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Tue, 16 Aug 2005 13:17:21 -0500
Subject: [llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
	SelectionDAG.cpp 
Message-ID: <200508161817.NAA21375@zion.cs.uiuc.edu>



Changes in directory llvm/lib/CodeGen/SelectionDAG:

LegalizeDAG.cpp updated: 1.160 -> 1.161
SelectionDAG.cpp updated: 1.139 -> 1.140
---
Log message:

Add some methods for dag->dag isel.
Split RemoveNodeFromCSEMaps out of DeleteNodesIfDead to do it.


---
Diffs of the changes:  (+59 -19)

 LegalizeDAG.cpp  |    2 -
 SelectionDAG.cpp |   76 +++++++++++++++++++++++++++++++++++++++++--------------
 2 files changed, 59 insertions(+), 19 deletions(-)


Index: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.160 llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.161
--- llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.160	Sun Aug 14 13:38:32 2005
+++ llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp	Tue Aug 16 13:17:10 2005
@@ -203,7 +203,7 @@
   return DAG.getNode(ISD::ADD, DestVT, Tmp1, FudgeInReg);
 }
 
-/// PromoteLegalUINT_TO_FP - This function is responsible for legalizing a
+/// PromoteLegalINT_TO_FP - This function is responsible for legalizing a
 /// *INT_TO_FP operation of the specified operand when the target requests that
 /// we promote it.  At this point, we know that the result and operand types are
 /// legal for the target, and that there is a legal UINT_TO_FP or SINT_TO_FP


Index: llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp:1.139 llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp:1.140
--- llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp:1.139	Sat Aug 13 01:14:17 2005
+++ llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp	Tue Aug 16 13:17:10 2005
@@ -177,12 +177,40 @@
   delete DummyNode;
 }
 
+
 void SelectionDAG::DeleteNodeIfDead(SDNode *N, void *NodeSet) {
   if (!N->use_empty())
     return;
 
   // Okay, we really are going to delete this node.  First take this out of the
   // appropriate CSE map.
+  RemoveNodeFromCSEMaps(N);
+  
+  // Next, brutally remove the operand list.  This is safe to do, as there are
+  // no cycles in the graph.
+  while (!N->Operands.empty()) {
+    SDNode *O = N->Operands.back().Val;
+    N->Operands.pop_back();
+    O->removeUser(N);
+    
+    // Now that we removed this operand, see if there are no uses of it left.
+    DeleteNodeIfDead(O, NodeSet);
+  }
+  
+  // Remove the node from the nodes set and delete it.
+  std::set<SDNode*> &AllNodeSet = *(std::set<SDNode*>*)NodeSet;
+  AllNodeSet.erase(N);
+  
+  // Now that the node is gone, check to see if any of the operands of this node
+  // are dead now.
+  delete N;  
+}
+
+/// RemoveNodeFromCSEMaps - Take the specified node out of the CSE map that
+/// correspond to it.  This is useful when we're about to delete or repurpose
+/// the node.  We don't want future request for structurally identical nodes
+/// to return N anymore.
+void SelectionDAG::RemoveNodeFromCSEMaps(SDNode *N) {
   switch (N->getOpcode()) {
   case ISD::Constant:
     Constants.erase(std::make_pair(cast<ConstantSDNode>(N)->getValue(),
@@ -253,24 +281,6 @@
     }
     break;
   }
-
-  // Next, brutally remove the operand list.
-  while (!N->Operands.empty()) {
-    SDNode *O = N->Operands.back().Val;
-    N->Operands.pop_back();
-    O->removeUser(N);
-
-    // Now that we removed this operand, see if there are no uses of it left.
-    DeleteNodeIfDead(O, NodeSet);
-  }
-
-  // Remove the node from the nodes set and delete it.
-  std::set<SDNode*> &AllNodeSet = *(std::set<SDNode*>*)NodeSet;
-  AllNodeSet.erase(N);
-
-  // Now that the node is gone, check to see if any of the operands of this node
-  // are dead now.
-  delete N;
 }
 
 
@@ -1679,6 +1689,36 @@
   return SDOperand(N, 0);
 }
 
+
+/// SelectNodeTo - These are used for target selectors to *mutate* the
+/// specified node to have the specified return type, Target opcode, and
+/// operands.  Note that target opcodes are stored as
+/// ISD::BUILTIN_OP_END+TargetOpcode in the node opcode field.
+void SelectionDAG::SelectNodeTo(SDNode *N, MVT::ValueType VT,
+                                unsigned TargetOpc, SDOperand Op1) {
+  RemoveNodeFromCSEMaps(N);
+  N->MorphNodeTo(ISD::BUILTIN_OP_END+TargetOpc);
+  N->setValueTypes(VT);
+  N->setOperands(Op1);
+}
+void SelectionDAG::SelectNodeTo(SDNode *N, MVT::ValueType VT,
+                                unsigned TargetOpc, SDOperand Op1,
+                                SDOperand Op2) {
+  RemoveNodeFromCSEMaps(N);
+  N->MorphNodeTo(ISD::BUILTIN_OP_END+TargetOpc);
+  N->setValueTypes(VT);
+  N->setOperands(Op1, Op2);
+}
+void SelectionDAG::SelectNodeTo(SDNode *N, MVT::ValueType VT,
+                                unsigned TargetOpc, SDOperand Op1,
+                                SDOperand Op2, SDOperand Op3) {
+  RemoveNodeFromCSEMaps(N);
+  N->MorphNodeTo(ISD::BUILTIN_OP_END+TargetOpc);
+  N->setValueTypes(VT);
+  N->setOperands(Op1, Op2, Op3);
+}
+
+
 /// hasNUsesOfValue - Return true if there are exactly NUSES uses of the
 /// indicated value.  This method ignores uses of other values defined by this
 /// operation.





From lattner at cs.uiuc.edu  Tue Aug 16 13:31:34 2005
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Tue, 16 Aug 2005 13:31:34 -0500
Subject: [llvm-commits] 
	CVS: llvm/lib/CodeGen/SelectionDAG/SelectionDAGPrinter.cpp
Message-ID: <200508161831.NAA21523@zion.cs.uiuc.edu>



Changes in directory llvm/lib/CodeGen/SelectionDAG:

SelectionDAGPrinter.cpp updated: 1.18 -> 1.19
---
Log message:

Use a extant helper to do this.


---
Diffs of the changes:  (+7 -19)

 SelectionDAGPrinter.cpp |   26 +++++++-------------------
 1 files changed, 7 insertions(+), 19 deletions(-)


Index: llvm/lib/CodeGen/SelectionDAG/SelectionDAGPrinter.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/SelectionDAGPrinter.cpp:1.18 llvm/lib/CodeGen/SelectionDAG/SelectionDAGPrinter.cpp:1.19
--- llvm/lib/CodeGen/SelectionDAG/SelectionDAGPrinter.cpp:1.18	Thu Aug  4 09:22:41 2005
+++ llvm/lib/CodeGen/SelectionDAG/SelectionDAGPrinter.cpp	Tue Aug 16 13:31:23 2005
@@ -47,26 +47,14 @@
 
 std::string DOTGraphTraits<SelectionDAG*>::getNodeLabel(const SDNode *Node,
                                                         const SelectionDAG *G) {
-  std::string Op = Node->getOperationName();
-
-  for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i) {
-    switch (Node->getValueType(i)) {
-    default: Op += ":unknownvt!"; break;
-    case MVT::Other: Op += ":ch"; break;
-    case MVT::i1:    Op += ":i1"; break;
-    case MVT::i8:    Op += ":i8"; break;
-    case MVT::i16:   Op += ":i16"; break;
-    case MVT::i32:   Op += ":i32"; break;
-    case MVT::i64:   Op += ":i64"; break;
-    case MVT::i128:  Op += ":i128"; break;
-    case MVT::f32:   Op += ":f32"; break;
-    case MVT::f64:   Op += ":f64"; break;
-    case MVT::f80:   Op += ":f80"; break;
-    case MVT::f128:  Op += ":f128"; break;
-    case MVT::isVoid: Op += ":void"; break;
-    }
-  }
+  std::string Op = Node->getOperationName(G);
 
+  for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i)
+    if (Node->getValueType(i) == MVT::Other)
+      Op += ":ch";
+    else
+      Op = Op + ":" + MVT::getValueTypeString(Node->getValueType(i));
+    
   if (const ConstantSDNode *CSDN = dyn_cast<ConstantSDNode>(Node)) {
     Op += ": " + utostr(CSDN->getValue());
   } else if (const ConstantFPSDNode *CSDN = dyn_cast<ConstantFPSDNode>(Node)) {





From lattner at cs.uiuc.edu  Tue Aug 16 13:32:29 2005
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Tue, 16 Aug 2005 13:32:29 -0500
Subject: [llvm-commits] CVS: llvm/include/llvm/CodeGen/SelectionDAGNodes.h 
Message-ID: <200508161832.NAA21606@zion.cs.uiuc.edu>



Changes in directory llvm/include/llvm/CodeGen:

SelectionDAGNodes.h updated: 1.48 -> 1.49
---
Log message:

allow passing a dag into getOperationName and dump


---
Diffs of the changes:  (+2 -1)

 SelectionDAGNodes.h |    3 ++-
 1 files changed, 2 insertions(+), 1 deletion(-)


Index: llvm/include/llvm/CodeGen/SelectionDAGNodes.h
diff -u llvm/include/llvm/CodeGen/SelectionDAGNodes.h:1.48 llvm/include/llvm/CodeGen/SelectionDAGNodes.h:1.49
--- llvm/include/llvm/CodeGen/SelectionDAGNodes.h:1.48	Tue Aug 16 13:16:24 2005
+++ llvm/include/llvm/CodeGen/SelectionDAGNodes.h	Tue Aug 16 13:32:18 2005
@@ -521,8 +521,9 @@
 
   /// getOperationName - Return the opcode of this operation for printing.
   ///
-  const char* getOperationName() const;
+  const char* getOperationName(const SelectionDAG *G = 0) const;
   void dump() const;
+  void dump(const SelectionDAG *G) const;
 
   static bool classof(const SDNode *) { return true; }
 





From lattner at cs.uiuc.edu  Tue Aug 16 13:33:18 2005
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Tue, 16 Aug 2005 13:33:18 -0500
Subject: [llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp 
Message-ID: <200508161833.NAA21641@zion.cs.uiuc.edu>



Changes in directory llvm/lib/CodeGen/SelectionDAG:

SelectionDAG.cpp updated: 1.140 -> 1.141
---
Log message:

Allow passing a dag into dump and getOperationName.  If one is available
when printing a node, use it to render target operations with their 
target instruction name instead of "<<unknown>>".


---
Diffs of the changes:  (+21 -9)

 SelectionDAG.cpp |   30 +++++++++++++++++++++---------
 1 files changed, 21 insertions(+), 9 deletions(-)


Index: llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp:1.140 llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp:1.141
--- llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp:1.140	Tue Aug 16 13:17:10 2005
+++ llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp	Tue Aug 16 13:33:07 2005
@@ -18,6 +18,8 @@
 #include "llvm/CodeGen/MachineBasicBlock.h"
 #include "llvm/Support/MathExtras.h"
 #include "llvm/Target/TargetLowering.h"
+#include "llvm/Target/TargetInstrInfo.h"
+#include "llvm/Target/TargetMachine.h"
 #include <iostream>
 #include <set>
 #include <cmath>
@@ -1752,9 +1754,18 @@
 }
 
 
-const char *SDNode::getOperationName() const {
+const char *SDNode::getOperationName(const SelectionDAG *G) const {
   switch (getOpcode()) {
-  default: return "<<Unknown>>";
+  default:
+    if (getOpcode() < ISD::BUILTIN_OP_END)
+      return "<<Unknown DAG Node>>";
+    else {
+      if (G)
+        if (const TargetInstrInfo *TII = G->getTarget().getInstrInfo())
+          return TII->getName(getOpcode()-ISD::BUILTIN_OP_END);
+      return "<<Unknown Target Node>>";
+    }
+   
   case ISD::PCMARKER:      return "PCMarker";
   case ISD::SRCVALUE:      return "SrcValue";
   case ISD::EntryToken:    return "EntryToken";
@@ -1883,7 +1894,8 @@
   }
 }
 
-void SDNode::dump() const {
+void SDNode::dump() const { dump(0); }
+void SDNode::dump(const SelectionDAG *G) const {
   std::cerr << (void*)this << ": ";
 
   for (unsigned i = 0, e = getNumValues(); i != e; ++i) {
@@ -1893,7 +1905,7 @@
     else
       std::cerr << MVT::getValueTypeString(getValueType(i));
   }
-  std::cerr << " = " << getOperationName();
+  std::cerr << " = " << getOperationName(G);
 
   std::cerr << " ";
   for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
@@ -1934,17 +1946,17 @@
   }
 }
 
-static void DumpNodes(SDNode *N, unsigned indent) {
+static void DumpNodes(SDNode *N, unsigned indent, const SelectionDAG *G) {
   for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
     if (N->getOperand(i).Val->hasOneUse())
-      DumpNodes(N->getOperand(i).Val, indent+2);
+      DumpNodes(N->getOperand(i).Val, indent+2, G);
     else
       std::cerr << "\n" << std::string(indent+2, ' ')
                 << (void*)N->getOperand(i).Val << ": <multiple use>";
 
 
   std::cerr << "\n" << std::string(indent, ' ');
-  N->dump();
+  N->dump(G);
 }
 
 void SelectionDAG::dump() const {
@@ -1954,10 +1966,10 @@
 
   for (unsigned i = 0, e = Nodes.size(); i != e; ++i) {
     if (!Nodes[i]->hasOneUse() && Nodes[i] != getRoot().Val)
-      DumpNodes(Nodes[i], 2);
+      DumpNodes(Nodes[i], 2, this);
   }
 
-  DumpNodes(getRoot().Val, 2);
+  DumpNodes(getRoot().Val, 2, this);
 
   std::cerr << "\n\n";
 }





From natebegeman at mac.com  Tue Aug 16 14:49:47 2005
From: natebegeman at mac.com (Nate Begeman)
Date: Tue, 16 Aug 2005 14:49:47 -0500
Subject: [llvm-commits] CVS: llvm/include/llvm/CodeGen/SelectionDAG.h
	SelectionDAGNodes.h 
Message-ID: <200508161949.OAA24669@zion.cs.uiuc.edu>



Changes in directory llvm/include/llvm/CodeGen:

SelectionDAG.h updated: 1.37 -> 1.38
SelectionDAGNodes.h updated: 1.49 -> 1.50
---
Log message:

Implement BR_CC and BRTWOWAY_CC.  This allows the removal of a rather nasty
fixme from the PowerPC backend.  Emit slightly better code for legalizing
select_cc.


---
Diffs of the changes:  (+27 -0)

 SelectionDAG.h      |   15 +++++++++++++++
 SelectionDAGNodes.h |   12 ++++++++++++
 2 files changed, 27 insertions(+)


Index: llvm/include/llvm/CodeGen/SelectionDAG.h
diff -u llvm/include/llvm/CodeGen/SelectionDAG.h:1.37 llvm/include/llvm/CodeGen/SelectionDAG.h:1.38
--- llvm/include/llvm/CodeGen/SelectionDAG.h:1.37	Tue Aug 16 13:16:24 2005
+++ llvm/include/llvm/CodeGen/SelectionDAG.h	Tue Aug 16 14:49:34 2005
@@ -193,6 +193,21 @@
     return getNode(ISD::SELECT_CC, VT, LHS, RHS, True, False,getCondCode(Cond));
   }
   
+  /// getBR2Way_CC - Helper function to make it easier to build BRTWOWAY_CC
+  /// nodes.
+  ///
+  SDOperand getBR2Way_CC(SDOperand Chain, SDOperand CCNode, SDOperand LHS, 
+                         SDOperand RHS, SDOperand True, SDOperand False) {
+    std::vector<SDOperand> Ops;
+    Ops.push_back(Chain);
+    Ops.push_back(CCNode);
+    Ops.push_back(LHS);
+    Ops.push_back(RHS);
+    Ops.push_back(True);
+    Ops.push_back(False);
+    return getNode(ISD::BRTWOWAY_CC, MVT::Other, Ops);
+  }
+
   /// getLoad - Loads are not normal binary operators: their result type is not
   /// determined by their operands, and they produce a value AND a token chain.
   ///


Index: llvm/include/llvm/CodeGen/SelectionDAGNodes.h
diff -u llvm/include/llvm/CodeGen/SelectionDAGNodes.h:1.49 llvm/include/llvm/CodeGen/SelectionDAGNodes.h:1.50
--- llvm/include/llvm/CodeGen/SelectionDAGNodes.h:1.49	Tue Aug 16 13:32:18 2005
+++ llvm/include/llvm/CodeGen/SelectionDAGNodes.h	Tue Aug 16 14:49:34 2005
@@ -233,6 +233,18 @@
     // operation to BRCOND/BR pairs when necessary.
     BRCONDTWOWAY,
 
+    // BR_CC - Conditional branch.  The behavior is like that of SELECT_CC, in
+    // that the condition is represented as condition code, and two nodes to
+    // compare, rather than as a combined SetCC node.  The operands in order are
+    // chain, cc, lhs, rhs, block to branch to if condition is true.
+    BR_CC,
+    
+    // BRTWOWAY_CC - Two-way conditional branch.  The operands in order are
+    // chain, cc, lhs, rhs, block to branch to if condition is true, block to
+    // branch to if condition is false.  Targets usually do not implement this,
+    // preferring to have legalize demote the operation to BRCOND/BR pairs.
+    BRTWOWAY_CC,
+    
     // RET - Return from function.  The first operand is the chain,
     // and any subsequent operands are the return values for the
     // function.  This operation can have variable number of operands.





From natebegeman at mac.com  Tue Aug 16 14:49:48 2005
From: natebegeman at mac.com (Nate Begeman)
Date: Tue, 16 Aug 2005 14:49:48 -0500
Subject: [llvm-commits] CVS: llvm/lib/Target/IA64/IA64ISelPattern.cpp 
Message-ID: <200508161949.OAA24681@zion.cs.uiuc.edu>



Changes in directory llvm/lib/Target/IA64:

IA64ISelPattern.cpp updated: 1.53 -> 1.54
---
Log message:

Implement BR_CC and BRTWOWAY_CC.  This allows the removal of a rather nasty
fixme from the PowerPC backend.  Emit slightly better code for legalizing
select_cc.


---
Diffs of the changes:  (+1 -0)

 IA64ISelPattern.cpp |    1 +
 1 files changed, 1 insertion(+)


Index: llvm/lib/Target/IA64/IA64ISelPattern.cpp
diff -u llvm/lib/Target/IA64/IA64ISelPattern.cpp:1.53 llvm/lib/Target/IA64/IA64ISelPattern.cpp:1.54
--- llvm/lib/Target/IA64/IA64ISelPattern.cpp:1.53	Wed Aug 10 07:38:57 2005
+++ llvm/lib/Target/IA64/IA64ISelPattern.cpp	Tue Aug 16 14:49:34 2005
@@ -57,6 +57,7 @@
       addRegisterClass(MVT::i1, IA64::PRRegisterClass);
 
       setOperationAction(ISD::BRCONDTWOWAY     , MVT::Other, Expand);
+      setOperationAction(ISD::BRTWOWAY_CC      , MVT::Other, Expand);
       setOperationAction(ISD::FP_ROUND_INREG   , MVT::f32  , Expand);
 
       setSetCCResultType(MVT::i1);





From natebegeman at mac.com  Tue Aug 16 14:49:48 2005
From: natebegeman at mac.com (Nate Begeman)
Date: Tue, 16 Aug 2005 14:49:48 -0500
Subject: [llvm-commits] CVS: llvm/lib/Target/PowerPC/PPC32ISelLowering.cpp
	PPC32ISelPattern.cpp 
Message-ID: <200508161949.OAA24695@zion.cs.uiuc.edu>



Changes in directory llvm/lib/Target/PowerPC:

PPC32ISelLowering.cpp updated: 1.1 -> 1.2
PPC32ISelPattern.cpp updated: 1.142 -> 1.143
---
Log message:

Implement BR_CC and BRTWOWAY_CC.  This allows the removal of a rather nasty
fixme from the PowerPC backend.  Emit slightly better code for legalizing
select_cc.


---
Diffs of the changes:  (+11 -18)

 PPC32ISelLowering.cpp |    4 ++++
 PPC32ISelPattern.cpp  |   25 +++++++------------------
 2 files changed, 11 insertions(+), 18 deletions(-)


Index: llvm/lib/Target/PowerPC/PPC32ISelLowering.cpp
diff -u llvm/lib/Target/PowerPC/PPC32ISelLowering.cpp:1.1 llvm/lib/Target/PowerPC/PPC32ISelLowering.cpp:1.2
--- llvm/lib/Target/PowerPC/PPC32ISelLowering.cpp:1.1	Tue Aug 16 12:14:42 2005
+++ llvm/lib/Target/PowerPC/PPC32ISelLowering.cpp	Tue Aug 16 14:49:35 2005
@@ -66,6 +66,10 @@
   setOperationAction(ISD::SELECT, MVT::i32, Expand);
   setOperationAction(ISD::SELECT, MVT::f32, Expand);
   setOperationAction(ISD::SELECT, MVT::f64, Expand);
+
+  // PowerPC does not have BRCOND* which requires SetCC
+  setOperationAction(ISD::BRCOND,       MVT::Other, Expand);
+  setOperationAction(ISD::BRCONDTWOWAY, MVT::Other, Expand);
   
   // PowerPC does not have FP_TO_UINT
   setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand);


Index: llvm/lib/Target/PowerPC/PPC32ISelPattern.cpp
diff -u llvm/lib/Target/PowerPC/PPC32ISelPattern.cpp:1.142 llvm/lib/Target/PowerPC/PPC32ISelPattern.cpp:1.143
--- llvm/lib/Target/PowerPC/PPC32ISelPattern.cpp:1.142	Tue Aug 16 12:14:42 2005
+++ llvm/lib/Target/PowerPC/PPC32ISelPattern.cpp	Tue Aug 16 14:49:35 2005
@@ -713,22 +713,11 @@
 void ISel::SelectBranchCC(SDOperand N)
 {
   MachineBasicBlock *Dest =
-    cast<BasicBlockSDNode>(N.getOperand(2))->getBasicBlock();
+    cast<BasicBlockSDNode>(N.getOperand(4))->getBasicBlock();
 
   Select(N.getOperand(0));  //chain
-  
-  // FIXME: Until we have Branch_CC and Branch_Twoway_CC, we're going to have to
-  // Fake it up by hand by checking to see if op 1 is a SetCC, or a boolean.
-  unsigned CCReg;
-  ISD::CondCode CC;
-  SDOperand Cond = N.getOperand(1);
-  if (Cond.getOpcode() == ISD::SETCC) {
-    CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
-    CCReg = SelectCC(Cond.getOperand(0), Cond.getOperand(1), CC);
-  } else {
-    CC = ISD::SETNE;
-    CCReg = SelectCC(Cond, ISelDAG->getConstant(0, Cond.getValueType()), CC);
-  }
+  ISD::CondCode CC = cast<CondCodeSDNode>(N.getOperand(1))->get();
+  unsigned CCReg = SelectCC(N.getOperand(2), N.getOperand(3), CC);
   unsigned Opc = getBCCForSetCC(CC);
 
   // Iterate to the next basic block
@@ -739,9 +728,9 @@
   // and build a PowerPC branch pseudo-op, suitable for long branch conversion
   // if necessary by the branch selection pass.  Otherwise, emit a standard
   // conditional branch.
-  if (N.getOpcode() == ISD::BRCONDTWOWAY) {
+  if (N.getOpcode() == ISD::BRTWOWAY_CC) {
     MachineBasicBlock *Fallthrough =
-      cast<BasicBlockSDNode>(N.getOperand(3))->getBasicBlock();
+      cast<BasicBlockSDNode>(N.getOperand(5))->getBasicBlock();
     if (Dest != It) {
       BuildMI(BB, PPC::COND_BRANCH, 4).addReg(CCReg).addImm(Opc)
         .addMBB(Dest).addMBB(Fallthrough);
@@ -1882,8 +1871,8 @@
     BuildMI(BB, PPC::B, 1).addMBB(Dest);
     return;
   }
-  case ISD::BRCOND:
-  case ISD::BRCONDTWOWAY:
+  case ISD::BR_CC:
+  case ISD::BRTWOWAY_CC:
     SelectBranchCC(N);
     return;
   case ISD::CopyToReg:





From natebegeman at mac.com  Tue Aug 16 14:49:48 2005
From: natebegeman at mac.com (Nate Begeman)
Date: Tue, 16 Aug 2005 14:49:48 -0500
Subject: [llvm-commits] CVS: llvm/lib/Target/SparcV8/SparcV8ISelPattern.cpp 
Message-ID: <200508161949.OAA24691@zion.cs.uiuc.edu>



Changes in directory llvm/lib/Target/SparcV8:

SparcV8ISelPattern.cpp updated: 1.5 -> 1.6
---
Log message:

Implement BR_CC and BRTWOWAY_CC.  This allows the removal of a rather nasty
fixme from the PowerPC backend.  Emit slightly better code for legalizing
select_cc.


---
Diffs of the changes:  (+1 -0)

 SparcV8ISelPattern.cpp |    1 +
 1 files changed, 1 insertion(+)


Index: llvm/lib/Target/SparcV8/SparcV8ISelPattern.cpp
diff -u llvm/lib/Target/SparcV8/SparcV8ISelPattern.cpp:1.5 llvm/lib/Target/SparcV8/SparcV8ISelPattern.cpp:1.6
--- llvm/lib/Target/SparcV8/SparcV8ISelPattern.cpp:1.5	Wed Jul 27 01:12:33 2005
+++ llvm/lib/Target/SparcV8/SparcV8ISelPattern.cpp	Tue Aug 16 14:49:35 2005
@@ -55,6 +55,7 @@
       addRegisterClass(MVT::f32, V8::FPRCRegisterClass);
 
       setOperationAction(ISD::BRCONDTWOWAY, MVT::Other, Expand);
+      setOperationAction(ISD::BRTWOWAY_CC,  MVT::Other, Expand);
       setOperationAction(ISD::EXTLOAD, MVT::i1,  Promote);
       setOperationAction(ISD::EXTLOAD, MVT::f32, Promote);
 





From natebegeman at mac.com  Tue Aug 16 14:49:48 2005
From: natebegeman at mac.com (Nate Begeman)
Date: Tue, 16 Aug 2005 14:49:48 -0500
Subject: [llvm-commits] CVS: llvm/lib/Target/X86/X86ISelPattern.cpp 
Message-ID: <200508161949.OAA24687@zion.cs.uiuc.edu>



Changes in directory llvm/lib/Target/X86:

X86ISelPattern.cpp updated: 1.168 -> 1.169
---
Log message:

Implement BR_CC and BRTWOWAY_CC.  This allows the removal of a rather nasty
fixme from the PowerPC backend.  Emit slightly better code for legalizing
select_cc.


---
Diffs of the changes:  (+1 -0)

 X86ISelPattern.cpp |    1 +
 1 files changed, 1 insertion(+)


Index: llvm/lib/Target/X86/X86ISelPattern.cpp
diff -u llvm/lib/Target/X86/X86ISelPattern.cpp:1.168 llvm/lib/Target/X86/X86ISelPattern.cpp:1.169
--- llvm/lib/Target/X86/X86ISelPattern.cpp:1.168	Sun Aug 14 13:37:02 2005
+++ llvm/lib/Target/X86/X86ISelPattern.cpp	Tue Aug 16 14:49:35 2005
@@ -152,6 +152,7 @@
       setOperationAction(ISD::FP_TO_SINT       , MVT::i16  , Promote);
 
       setOperationAction(ISD::BRCONDTWOWAY     , MVT::Other, Expand);
+      setOperationAction(ISD::BRTWOWAY_CC      , MVT::Other, Expand);
       setOperationAction(ISD::MEMMOVE          , MVT::Other, Expand);
       setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16  , Expand);
       setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1   , Expand);





From natebegeman at mac.com  Tue Aug 16 14:49:48 2005
From: natebegeman at mac.com (Nate Begeman)
Date: Tue, 16 Aug 2005 14:49:48 -0500
Subject: [llvm-commits] CVS: llvm/lib/Target/Alpha/AlphaISelPattern.cpp 
Message-ID: <200508161949.OAA24679@zion.cs.uiuc.edu>



Changes in directory llvm/lib/Target/Alpha:

AlphaISelPattern.cpp updated: 1.161 -> 1.162
---
Log message:

Implement BR_CC and BRTWOWAY_CC.  This allows the removal of a rather nasty
fixme from the PowerPC backend.  Emit slightly better code for legalizing
select_cc.


---
Diffs of the changes:  (+1 -0)

 AlphaISelPattern.cpp |    1 +
 1 files changed, 1 insertion(+)


Index: llvm/lib/Target/Alpha/AlphaISelPattern.cpp
diff -u llvm/lib/Target/Alpha/AlphaISelPattern.cpp:1.161 llvm/lib/Target/Alpha/AlphaISelPattern.cpp:1.162
--- llvm/lib/Target/Alpha/AlphaISelPattern.cpp:1.161	Mon Aug 15 09:31:37 2005
+++ llvm/lib/Target/Alpha/AlphaISelPattern.cpp	Tue Aug 16 14:49:34 2005
@@ -90,6 +90,7 @@
       addRegisterClass(MVT::f32, Alpha::FPRCRegisterClass);
 
       setOperationAction(ISD::BRCONDTWOWAY, MVT::Other, Expand);
+      setOperationAction(ISD::BRTWOWAY_CC,  MVT::Other, Expand);
 
       setOperationAction(ISD::EXTLOAD, MVT::i1,  Promote);
       setOperationAction(ISD::EXTLOAD, MVT::f32, Expand);





From natebegeman at mac.com  Tue Aug 16 14:49:48 2005
From: natebegeman at mac.com (Nate Begeman)
Date: Tue, 16 Aug 2005 14:49:48 -0500
Subject: [llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
	SelectionDAG.cpp 
Message-ID: <200508161949.OAA24675@zion.cs.uiuc.edu>



Changes in directory llvm/lib/CodeGen/SelectionDAG:

LegalizeDAG.cpp updated: 1.161 -> 1.162
SelectionDAG.cpp updated: 1.141 -> 1.142
---
Log message:

Implement BR_CC and BRTWOWAY_CC.  This allows the removal of a rather nasty
fixme from the PowerPC backend.  Emit slightly better code for legalizing
select_cc.


---
Diffs of the changes:  (+139 -12)

 LegalizeDAG.cpp  |  143 ++++++++++++++++++++++++++++++++++++++++++++++++++-----
 SelectionDAG.cpp |    8 ++-
 2 files changed, 139 insertions(+), 12 deletions(-)


Index: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.161 llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.162
--- llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.161	Tue Aug 16 13:17:10 2005
+++ llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp	Tue Aug 16 14:49:34 2005
@@ -594,7 +594,7 @@
 
   case ISD::BRCOND:
     Tmp1 = LegalizeOp(Node->getOperand(0));  // Legalize the chain.
-
+    
     switch (getTypeAction(Node->getOperand(1).getValueType())) {
     case Expand: assert(0 && "It's impossible to expand bools");
     case Legal:
@@ -604,10 +604,63 @@
       Tmp2 = PromoteOp(Node->getOperand(1));  // Promote the condition.
       break;
     }
-    // Basic block destination (Op#2) is always legal.
-    if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1))
-      Result = DAG.getNode(ISD::BRCOND, MVT::Other, Tmp1, Tmp2,
-                           Node->getOperand(2));
+      
+    switch (TLI.getOperationAction(ISD::BRCOND, MVT::Other)) {  
+    default: assert(0 && "This action is not supported yet!");
+    case TargetLowering::Expand:
+      // Expand brcond's setcc into its constituent parts and create a BR_CC
+      // Node.
+      if (Tmp2.getOpcode() == ISD::SETCC) {
+        Result = DAG.getNode(ISD::BR_CC, MVT::Other, Tmp1, Tmp2.getOperand(2),
+                             Tmp2.getOperand(0), Tmp2.getOperand(1),
+                             Node->getOperand(2));
+      } else {
+        Result = DAG.getNode(ISD::BR_CC, MVT::Other, Tmp1, 
+                             DAG.getCondCode(ISD::SETNE), Tmp2,
+                             DAG.getConstant(0, Tmp2.getValueType()),
+                             Node->getOperand(2));
+      }
+      break;
+    case TargetLowering::Legal:
+      // Basic block destination (Op#2) is always legal.
+      if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1))
+        Result = DAG.getNode(ISD::BRCOND, MVT::Other, Tmp1, Tmp2,
+                             Node->getOperand(2));
+        break;
+    }
+    break;
+  case ISD::BR_CC:
+    Tmp1 = LegalizeOp(Node->getOperand(0));  // Legalize the chain.
+    
+    if (getTypeAction(Node->getOperand(2).getValueType()) == Legal) {
+      Tmp2 = LegalizeOp(Node->getOperand(2));   // LHS
+      Tmp3 = LegalizeOp(Node->getOperand(3));   // RHS
+      if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(2) ||
+          Tmp3 != Node->getOperand(3)) {
+        Result = DAG.getNode(ISD::BR_CC, MVT::Other, Tmp1, Node->getOperand(1),
+                             Tmp2, Tmp3, Node->getOperand(4));
+      }
+      break;
+    } else {
+      Tmp2 = LegalizeOp(DAG.getNode(ISD::SETCC, TLI.getSetCCResultTy(),
+                                    Node->getOperand(2),  // LHS
+                                    Node->getOperand(3),  // RHS
+                                    Node->getOperand(1)));
+      // If we get a SETCC back from legalizing the SETCC node we just
+      // created, then use its LHS, RHS, and CC directly in creating a new
+      // node.  Otherwise, select between the true and false value based on
+      // comparing the result of the legalized with zero.
+      if (Tmp2.getOpcode() == ISD::SETCC) {
+        Result = DAG.getNode(ISD::BR_CC, MVT::Other, Tmp1, Tmp2.getOperand(2),
+                             Tmp2.getOperand(0), Tmp2.getOperand(1),
+                             Node->getOperand(4));
+      } else {
+        Result = DAG.getNode(ISD::BR_CC, MVT::Other, Tmp1, 
+                             DAG.getCondCode(ISD::SETNE),
+                             Tmp2, DAG.getConstant(0, Tmp2.getValueType()), 
+                             Node->getOperand(4));
+      }
+    }
     break;
   case ISD::BRCONDTWOWAY:
     Tmp1 = LegalizeOp(Node->getOperand(0));  // Legalize the chain.
@@ -636,13 +689,71 @@
       }
       break;
     case TargetLowering::Expand:
-      Result = DAG.getNode(ISD::BRCOND, MVT::Other, Tmp1, Tmp2,
+      // If BRTWOWAY_CC is legal for this target, then simply expand this node
+      // to that.  Otherwise, skip BRTWOWAY_CC and expand directly to a
+      // BRCOND/BR pair.
+      if (TLI.getOperationAction(ISD::BRTWOWAY_CC, MVT::Other) == 
+          TargetLowering::Legal) {
+        if (Tmp2.getOpcode() == ISD::SETCC) {
+          Result = DAG.getBR2Way_CC(Tmp1, Tmp2.getOperand(2),
+                                    Tmp2.getOperand(0), Tmp2.getOperand(1),
+                                    Node->getOperand(2), Node->getOperand(3));
+        } else {
+          Result = DAG.getBR2Way_CC(Tmp1, DAG.getCondCode(ISD::SETNE), Tmp2, 
+                                    DAG.getConstant(0, Tmp2.getValueType()),
+                                    Node->getOperand(2), Node->getOperand(3));
+        }
+      } else {
+        Result = DAG.getNode(ISD::BRCOND, MVT::Other, Tmp1, Tmp2,
                            Node->getOperand(2));
-      Result = DAG.getNode(ISD::BR, MVT::Other, Result, Node->getOperand(3));
+        Result = DAG.getNode(ISD::BR, MVT::Other, Result, Node->getOperand(3));
+      }
       break;
     }
     break;
-
+  case ISD::BRTWOWAY_CC:
+    Tmp1 = LegalizeOp(Node->getOperand(0));  // Legalize the chain.
+    if (getTypeAction(Node->getOperand(2).getValueType()) == Legal) {
+      Tmp2 = LegalizeOp(Node->getOperand(2));   // LHS
+      Tmp3 = LegalizeOp(Node->getOperand(3));   // RHS
+      if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(2) ||
+          Tmp3 != Node->getOperand(3)) {
+        Result = DAG.getBR2Way_CC(Tmp1, Node->getOperand(1), Tmp2, Tmp3,
+                                  Node->getOperand(4), Node->getOperand(5));
+      }
+      break;
+    } else {
+      Tmp2 = LegalizeOp(DAG.getNode(ISD::SETCC, TLI.getSetCCResultTy(),
+                                    Node->getOperand(2),  // LHS
+                                    Node->getOperand(3),  // RHS
+                                    Node->getOperand(1)));
+      // If this target does not support BRTWOWAY_CC, lower it to a BRCOND/BR
+      // pair.
+      switch (TLI.getOperationAction(ISD::BRTWOWAY_CC, MVT::Other)) {
+      default: assert(0 && "This action is not supported yet!");
+      case TargetLowering::Legal:
+        // If we get a SETCC back from legalizing the SETCC node we just
+        // created, then use its LHS, RHS, and CC directly in creating a new
+        // node.  Otherwise, select between the true and false value based on
+        // comparing the result of the legalized with zero.
+        if (Tmp2.getOpcode() == ISD::SETCC) {
+          Result = DAG.getBR2Way_CC(Tmp1, Tmp2.getOperand(2),
+                                    Tmp2.getOperand(0), Tmp2.getOperand(1),
+                                    Node->getOperand(4), Node->getOperand(5));
+        } else {
+          Result = DAG.getBR2Way_CC(Tmp1, DAG.getCondCode(ISD::SETNE), Tmp2, 
+                                    DAG.getConstant(0, Tmp2.getValueType()),
+                                    Node->getOperand(4), Node->getOperand(5));
+        }
+        break;
+      case TargetLowering::Expand: 
+        Result = DAG.getNode(ISD::BRCOND, MVT::Other, Tmp1, Tmp2,
+                             Node->getOperand(4));
+        Result = DAG.getNode(ISD::BR, MVT::Other, Result, Node->getOperand(5));
+        break;
+      }
+    }
+    break;
   case ISD::LOAD:
     Tmp1 = LegalizeOp(Node->getOperand(0));  // Legalize the chain.
     Tmp2 = LegalizeOp(Node->getOperand(1));  // Legalize the pointer.
@@ -967,9 +1078,19 @@
                                     Node->getOperand(0),  // LHS
                                     Node->getOperand(1),  // RHS
                                     Node->getOperand(4)));
-      Result = DAG.getSelectCC(Tmp1,
-                               DAG.getConstant(0, Tmp1.getValueType()), 
-                               Tmp3, Tmp4, ISD::SETNE);
+      // If we get a SETCC back from legalizing the SETCC node we just
+      // created, then use its LHS, RHS, and CC directly in creating a new
+      // node.  Otherwise, select between the true and false value based on
+      // comparing the result of the legalized with zero.
+      if (Tmp1.getOpcode() == ISD::SETCC) {
+        Result = DAG.getNode(ISD::SELECT_CC, Tmp3.getValueType(),
+                             Tmp1.getOperand(0), Tmp1.getOperand(1),
+                             Tmp3, Tmp4, Tmp1.getOperand(2));
+      } else {
+        Result = DAG.getSelectCC(Tmp1,
+                                 DAG.getConstant(0, Tmp1.getValueType()), 
+                                 Tmp3, Tmp4, ISD::SETNE);
+      }
     }
     break;
   case ISD::SETCC:


Index: llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp:1.141 llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp:1.142
--- llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp:1.141	Tue Aug 16 13:33:07 2005
+++ llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp	Tue Aug 16 14:49:34 2005
@@ -1602,7 +1602,11 @@
       else                 // Unconditional branch to false dest.
         return getNode(ISD::BR, MVT::Other, Ops[0], Ops[3]);
     break;
-
+  case ISD::BRTWOWAY_CC:
+    assert(Ops.size() == 6 && "BRTWOWAY_CC takes 6 operands!");
+    assert(Ops[2].getValueType() == Ops[3].getValueType() &&
+           "LHS and RHS of comparison must have same type!");
+    break;
   case ISD::TRUNCSTORE: {
     assert(Ops.size() == 5 && "TRUNCSTORE takes 5 operands!");
     MVT::ValueType EVT = cast<VTSDNode>(Ops[4])->getVT();
@@ -1833,6 +1837,8 @@
   case ISD::BR:      return "br";
   case ISD::BRCOND:  return "brcond";
   case ISD::BRCONDTWOWAY:  return "brcondtwoway";
+  case ISD::BR_CC:  return "br_cc";
+  case ISD::BRTWOWAY_CC:  return "brtwoway_cc";
   case ISD::RET:     return "ret";
   case ISD::CALL:    return "call";
   case ISD::TAILCALL:return "tailcall";





From lattner at cs.uiuc.edu  Tue Aug 16 16:54:52 2005
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Tue, 16 Aug 2005 16:54:52 -0500
Subject: [llvm-commits] CVS: llvm/include/llvm/CodeGen/SelectionDAG.h
	SelectionDAGNodes.h 
Message-ID: <200508162154.QAA15735@zion.cs.uiuc.edu>



Changes in directory llvm/include/llvm/CodeGen:

SelectionDAG.h updated: 1.38 -> 1.39
SelectionDAGNodes.h updated: 1.50 -> 1.51
---
Log message:

Eliminate the RegSDNode class, which 3 nodes (CopyFromReg/CopyToReg/ImplicitDef)
used to tack a register number onto the node.

Instead of doing this, make a new node, RegisterSDNode, which is a leaf 
containing a register number.  These three operations just become normal
DAG nodes now, instead of requiring special handling.

Note that with this change, it is no longer correct to make illegal 
CopyFromReg/CopyToReg nodes.  The legalizer will not touch them, and this
is bad, so don't do it. :)



---
Diffs of the changes:  (+26 -38)

 SelectionDAG.h      |   34 +++++++++++++++-------------------
 SelectionDAGNodes.h |   30 +++++++++++-------------------
 2 files changed, 26 insertions(+), 38 deletions(-)


Index: llvm/include/llvm/CodeGen/SelectionDAG.h
diff -u llvm/include/llvm/CodeGen/SelectionDAG.h:1.38 llvm/include/llvm/CodeGen/SelectionDAG.h:1.39
--- llvm/include/llvm/CodeGen/SelectionDAG.h:1.38	Tue Aug 16 14:49:34 2005
+++ llvm/include/llvm/CodeGen/SelectionDAG.h	Tue Aug 16 16:54:41 2005
@@ -101,30 +101,25 @@
   SDOperand getBasicBlock(MachineBasicBlock *MBB);
   SDOperand getExternalSymbol(const char *Sym, MVT::ValueType VT);
   SDOperand getValueType(MVT::ValueType);
+  SDOperand getRegister(unsigned Reg, MVT::ValueType VT);
 
-  SDOperand getCopyToReg(SDOperand Chain, SDOperand N, unsigned Reg) {
-    // Note: these are auto-CSE'd because the caller doesn't make requests that
-    // could cause duplicates to occur.
-    SDNode *NN = new RegSDNode(ISD::CopyToReg, Chain, N, Reg);
-    NN->setValueTypes(MVT::Other);
-    AllNodes.push_back(NN);
-    return SDOperand(NN, 0);
+  SDOperand getCopyToReg(SDOperand Chain, unsigned Reg, SDOperand N) {
+    return getNode(ISD::CopyToReg, MVT::Other, Chain,
+                   getRegister(Reg, N.getValueType()), N);
   }
 
-  SDOperand getCopyFromReg(unsigned Reg, MVT::ValueType VT, SDOperand Chain) {
-    // Note: These nodes are auto-CSE'd by the caller of this method.
-    SDNode *NN = new RegSDNode(ISD::CopyFromReg, Chain, Reg);
-    NN->setValueTypes(VT, MVT::Other);
-    AllNodes.push_back(NN);
-    return SDOperand(NN, 0);
+  SDOperand getCopyFromReg(SDOperand Chain, unsigned Reg, MVT::ValueType VT) {
+    std::vector<MVT::ValueType> ResultTys;
+    ResultTys.push_back(VT);
+    ResultTys.push_back(MVT::Other);
+    std::vector<SDOperand> Ops;
+    Ops.push_back(Chain);
+    Ops.push_back(getRegister(Reg, VT));
+    return getNode(ISD::CopyFromReg, ResultTys, Ops);
   }
 
-  SDOperand getImplicitDef(SDOperand Chain, unsigned Reg) {
-    // Note: These nodes are auto-CSE'd by the caller of this method.
-    SDNode *NN = new RegSDNode(ISD::ImplicitDef, Chain, Reg);
-    NN->setValueTypes(MVT::Other);
-    AllNodes.push_back(NN);
-    return SDOperand(NN, 0);
+  SDOperand getImplicitDef(SDOperand Chain, unsigned Reg, MVT::ValueType VT) {
+    return getNode(ISD::ImplicitDef, MVT::Other, Chain, getRegister(Reg, VT));
   }
 
   /// getCall - Note that this destroys the vector of RetVals passed in.
@@ -255,6 +250,7 @@
   std::map<std::pair<unsigned, std::pair<SDOperand, SDOperand> >,
            SDNode *> BinaryOps;
 
+  std::vector<RegisterSDNode*> RegNodes;
   std::vector<CondCodeSDNode*> CondCodeNodes;
 
   std::map<std::pair<SDOperand, std::pair<SDOperand, MVT::ValueType> >,


Index: llvm/include/llvm/CodeGen/SelectionDAGNodes.h
diff -u llvm/include/llvm/CodeGen/SelectionDAGNodes.h:1.50 llvm/include/llvm/CodeGen/SelectionDAGNodes.h:1.51
--- llvm/include/llvm/CodeGen/SelectionDAGNodes.h:1.50	Tue Aug 16 14:49:34 2005
+++ llvm/include/llvm/CodeGen/SelectionDAGNodes.h	Tue Aug 16 16:54:41 2005
@@ -55,12 +55,10 @@
 
     // Various leaf nodes.
     Constant, ConstantFP, GlobalAddress, FrameIndex, ConstantPool,
-    BasicBlock, ExternalSymbol, VALUETYPE, CONDCODE,
+    BasicBlock, ExternalSymbol, VALUETYPE, CONDCODE, Register,
 
-    // CopyToReg - This node has chain and child nodes, and an associated
-    // register number.  The instruction selector must guarantee that the value
-    // of the value node is available in the register stored in the RegSDNode
-    // object.
+    // CopyToReg - This node has three operands: a chain, a register number to
+    // set to this value, and a value.  
     CopyToReg,
 
     // CopyFromReg - This node indicates that the input value is a virtual or
@@ -69,10 +67,9 @@
     CopyFromReg,
 
     // ImplicitDef - This node indicates that the specified register is
-    // implicitly defined by some operation (e.g. its a live-in argument).  This
-    // register is indicated in the RegSDNode object.  The only operand to this
-    // is the token chain coming in, the only result is the token chain going
-    // out.
+    // implicitly defined by some operation (e.g. its a live-in argument).  The
+    // two operands to this are the token chain coming in and the register.
+    // The only result is the token chain going out.
     ImplicitDef,
 
     // UNDEF - An undefined node
@@ -830,24 +827,19 @@
 };
 
 
-class RegSDNode : public SDNode {
+class RegisterSDNode : public SDNode {
   unsigned Reg;
 protected:
   friend class SelectionDAG;
-  RegSDNode(unsigned Opc, SDOperand Chain, SDOperand Src, unsigned reg)
-    : SDNode(Opc, Chain, Src), Reg(reg) {
-  }
-  RegSDNode(unsigned Opc, SDOperand Chain, unsigned reg)
-    : SDNode(Opc, Chain), Reg(reg) {}
+  RegisterSDNode(unsigned reg, MVT::ValueType VT)
+    : SDNode(ISD::Register, VT), Reg(reg) {}
 public:
 
   unsigned getReg() const { return Reg; }
 
-  static bool classof(const RegSDNode *) { return true; }
+  static bool classof(const RegisterSDNode *) { return true; }
   static bool classof(const SDNode *N) {
-    return N->getOpcode() == ISD::CopyToReg ||
-           N->getOpcode() == ISD::CopyFromReg ||
-           N->getOpcode() == ISD::ImplicitDef;
+    return N->getOpcode() == ISD::Register;
   }
 };
 





From lattner at cs.uiuc.edu  Tue Aug 16 16:55:46 2005
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Tue, 16 Aug 2005 16:55:46 -0500
Subject: [llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
	SelectionDAG.cpp SelectionDAGISel.cpp SelectionDAGPrinter.cpp
Message-ID: <200508162155.QAA17046@zion.cs.uiuc.edu>



Changes in directory llvm/lib/CodeGen/SelectionDAG:

LegalizeDAG.cpp updated: 1.162 -> 1.163
SelectionDAG.cpp updated: 1.142 -> 1.143
SelectionDAGISel.cpp updated: 1.68 -> 1.69
SelectionDAGPrinter.cpp updated: 1.19 -> 1.20
---
Log message:

Eliminate the RegSDNode class, which 3 nodes (CopyFromReg/CopyToReg/ImplicitDef)
used to tack a register number onto the node.

Instead of doing this, make a new node, RegisterSDNode, which is a leaf 
containing a register number.  These three operations just become normal
DAG nodes now, instead of requiring special handling.

Note that with this change, it is no longer correct to make illegal 
CopyFromReg/CopyToReg nodes.  The legalizer will not touch them, and this
is bad, so don't do it. :)



---
Diffs of the changes:  (+82 -54)

 LegalizeDAG.cpp         |   63 ++++++++++++------------------------------------
 SelectionDAG.cpp        |   22 +++++++++++++++-
 SelectionDAGISel.cpp    |   47 ++++++++++++++++++++++++++++++++---
 SelectionDAGPrinter.cpp |    4 +--
 4 files changed, 82 insertions(+), 54 deletions(-)


Index: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.162 llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.163
--- llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.162	Tue Aug 16 14:49:34 2005
+++ llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp	Tue Aug 16 16:55:35 2005
@@ -405,8 +405,9 @@
   case ISD::CopyFromReg:
     Tmp1 = LegalizeOp(Node->getOperand(0));
     if (Tmp1 != Node->getOperand(0))
-      Result = DAG.getCopyFromReg(cast<RegSDNode>(Node)->getReg(),
-                                  Node->getValueType(0), Tmp1);
+      Result = DAG.getCopyFromReg(Tmp1, 
+                            cast<RegisterSDNode>(Node->getOperand(1))->getReg(),
+                                  Node->getValueType(0));
     else
       Result = Op.getValue(0);
 
@@ -418,7 +419,8 @@
   case ISD::ImplicitDef:
     Tmp1 = LegalizeOp(Node->getOperand(0));
     if (Tmp1 != Node->getOperand(0))
-      Result = DAG.getImplicitDef(Tmp1, cast<RegSDNode>(Node)->getReg());
+      Result = DAG.getNode(ISD::ImplicitDef, MVT::Other,
+                           Tmp1, Node->getOperand(1));
     break;
   case ISD::UNDEF: {
     MVT::ValueType VT = Op.getValueType();
@@ -844,29 +846,13 @@
   case ISD::CopyToReg:
     Tmp1 = LegalizeOp(Node->getOperand(0));  // Legalize the chain.
 
-    switch (getTypeAction(Node->getOperand(1).getValueType())) {
-    case Legal:
-      // Legalize the incoming value (must be legal).
-      Tmp2 = LegalizeOp(Node->getOperand(1));
-      if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1))
-        Result = DAG.getCopyToReg(Tmp1, Tmp2, cast<RegSDNode>(Node)->getReg());
-      break;
-    case Promote:
-      Tmp2 = PromoteOp(Node->getOperand(1));
-      Result = DAG.getCopyToReg(Tmp1, Tmp2, cast<RegSDNode>(Node)->getReg());
-      break;
-    case Expand:
-      SDOperand Lo, Hi;
-      ExpandOp(Node->getOperand(1), Lo, Hi);
-      unsigned Reg = cast<RegSDNode>(Node)->getReg();
-      Lo = DAG.getCopyToReg(Tmp1, Lo, Reg);
-      Hi = DAG.getCopyToReg(Tmp1, Hi, Reg+1);
-      // Note that the copytoreg nodes are independent of each other.
-      Result = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo, Hi);
-      assert(isTypeLegal(Result.getValueType()) &&
-             "Cannot expand multiple times yet (i64 -> i16)");
-      break;
-    }
+    assert(getTypeAction(Node->getOperand(2).getValueType()) == Legal &&
+           "Register type must be legal!");
+    // Legalize the incoming value (must be legal).
+    Tmp2 = LegalizeOp(Node->getOperand(2));
+    if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(2))
+      Result = DAG.getNode(ISD::CopyToReg, MVT::Other, Tmp1,
+                           Node->getOperand(1), Tmp2);
     break;
 
   case ISD::RET:
@@ -1913,6 +1899,8 @@
   NeedsAnotherIteration = true;
 
   switch (Node->getOpcode()) {
+  case ISD::CopyFromReg:
+    assert(0 && "CopyFromReg must be legal!");
   default:
     std::cerr << "NODE: "; Node->dump(); std::cerr << "\n";
     assert(0 && "Do not know how to promote this operator!");
@@ -1928,12 +1916,6 @@
     Result = DAG.getNode(ISD::FP_EXTEND, NVT, Op);
     assert(isa<ConstantFPSDNode>(Result) && "Didn't constant fold fp_extend?");
     break;
-  case ISD::CopyFromReg:
-    Result = DAG.getCopyFromReg(cast<RegSDNode>(Node)->getReg(), NVT,
-                                Node->getOperand(0));
-    // Remember that we legalized the chain.
-    AddLegalizedOperand(Op.getValue(1), Result.getValue(1));
-    break;
 
   case ISD::SETCC:
     assert(getTypeAction(TLI.getSetCCResultTy()) == Legal &&
@@ -2770,7 +2752,9 @@
   NeedsAnotherIteration = true;
 
   switch (Node->getOpcode()) {
-  default:
+   case ISD::CopyFromReg:
+      assert(0 && "CopyFromReg must be legal!");
+   default:
     std::cerr << "NODE: "; Node->dump(); std::cerr << "\n";
     assert(0 && "Do not know how to expand this operator!");
     abort();
@@ -2785,19 +2769,6 @@
     break;
   }
 
-  case ISD::CopyFromReg: {
-    unsigned Reg = cast<RegSDNode>(Node)->getReg();
-    // Aggregate register values are always in consequtive pairs.
-    Lo = DAG.getCopyFromReg(Reg, NVT, Node->getOperand(0));
-    Hi = DAG.getCopyFromReg(Reg+1, NVT, Lo.getValue(1));
-
-    // Remember that we legalized the chain.
-    AddLegalizedOperand(Op.getValue(1), Hi.getValue(1));
-
-    assert(isTypeLegal(NVT) && "Cannot expand this multiple times yet!");
-    break;
-  }
-
   case ISD::BUILD_PAIR:
     // Legalize both operands.  FIXME: in the future we should handle the case
     // where the two elements are not legal.


Index: llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp:1.142 llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp:1.143
--- llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp:1.142	Tue Aug 16 14:49:34 2005
+++ llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp	Tue Aug 16 16:55:35 2005
@@ -250,6 +250,9 @@
   case ISD::VALUETYPE:
     ValueTypeNodes[cast<VTSDNode>(N)->getVT()] = 0;
     break;
+  case ISD::Register:
+    RegNodes[cast<RegisterSDNode>(N)->getReg()] = 0;
+    break;
   case ISD::SRCVALUE: {
     SrcValueSDNode *SVN = cast<SrcValueSDNode>(N);
     ValueNodes.erase(std::make_pair(SVN->getValue(), SVN->getOffset()));
@@ -398,6 +401,20 @@
   return SDOperand(CondCodeNodes[Cond], 0);
 }
 
+SDOperand SelectionDAG::getRegister(unsigned Reg, MVT::ValueType VT) {
+  if (Reg >= RegNodes.size())
+    RegNodes.resize(Reg+1);
+  RegisterSDNode *&Result = RegNodes[Reg];
+  if (Result) {
+    assert(Result->getValueType(0) == VT &&
+           "Inconsistent value types for machine registers");
+  } else {
+    Result = new RegisterSDNode(Reg, VT);
+    AllNodes.push_back(Result);
+  }
+  return SDOperand(Result, 0);
+}
+
 SDOperand SelectionDAG::SimplifySetCC(MVT::ValueType VT, SDOperand N1,
                                       SDOperand N2, ISD::CondCode Cond) {
   // These setcc operations always fold.
@@ -1779,6 +1796,7 @@
   case ISD::GlobalAddress: return "GlobalAddress";
   case ISD::FrameIndex:    return "FrameIndex";
   case ISD::BasicBlock:    return "BasicBlock";
+  case ISD::Register:      return "Register";
   case ISD::ExternalSymbol: return "ExternalSymbol";
   case ISD::ConstantPool:  return "ConstantPoolIndex";
   case ISD::CopyToReg:     return "CopyToReg";
@@ -1939,8 +1957,8 @@
     if (LBB)
       std::cerr << LBB->getName() << " ";
     std::cerr << (const void*)BBDN->getBasicBlock() << ">";
-  } else if (const RegSDNode *C2V = dyn_cast<RegSDNode>(this)) {
-    std::cerr << "<reg #" << C2V->getReg() << ">";
+  } else if (const RegisterSDNode *C2V = dyn_cast<RegisterSDNode>(this)) {
+    std::cerr << " #" << C2V->getReg();
   } else if (const ExternalSymbolSDNode *ES =
              dyn_cast<ExternalSymbolSDNode>(this)) {
     std::cerr << "'" << ES->getSymbol() << "'";


Index: llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.68 llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.69
--- llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.68	Tue Aug  9 15:20:18 2005
+++ llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp	Tue Aug 16 16:55:35 2005
@@ -296,7 +296,27 @@
       FuncInfo.ValueMap.find(V);
     assert(VMI != FuncInfo.ValueMap.end() && "Value not in map!");
 
-    return N = DAG.getCopyFromReg(VMI->second, VT, DAG.getEntryNode());
+    unsigned InReg = VMI->second;
+   
+    // If this type is not legal, make it so now.
+    MVT::ValueType DestVT = TLI.getTypeToTransformTo(VT);
+    
+    N = DAG.getCopyFromReg(DAG.getEntryNode(), InReg, DestVT);
+    if (DestVT < VT) {
+      // Source must be expanded.  This input value is actually coming from the
+      // register pair VMI->second and VMI->second+1.
+      N = DAG.getNode(ISD::BUILD_PAIR, VT, N,
+                      DAG.getCopyFromReg(DAG.getEntryNode(), InReg+1, DestVT));
+    } else {
+      if (DestVT > VT) { // Promotion case
+        if (MVT::isFloatingPoint(VT))
+          N = DAG.getNode(ISD::FP_ROUND, VT, N);
+        else
+          N = DAG.getNode(ISD::TRUNCATE, VT, N);
+      }
+    }
+    
+    return N;
   }
 
   const SDOperand &setValue(const Value *V, SDOperand NewN) {
@@ -957,12 +977,31 @@
 
 SDOperand SelectionDAGISel::
 CopyValueToVirtualRegister(SelectionDAGLowering &SDL, Value *V, unsigned Reg) {
-  SelectionDAG &DAG = SDL.DAG;
   SDOperand Op = SDL.getValue(V);
   assert((Op.getOpcode() != ISD::CopyFromReg ||
-          cast<RegSDNode>(Op)->getReg() != Reg) &&
+          cast<RegisterSDNode>(Op.getOperand(1))->getReg() != Reg) &&
          "Copy from a reg to the same reg!");
-  return DAG.getCopyToReg(SDL.getRoot(), Op, Reg);
+  
+  // If this type is not legal, we must make sure to not create an invalid
+  // register use.
+  MVT::ValueType SrcVT = Op.getValueType();
+  MVT::ValueType DestVT = TLI.getTypeToTransformTo(SrcVT);
+  SelectionDAG &DAG = SDL.DAG;
+  if (SrcVT == DestVT) {
+    return DAG.getCopyToReg(SDL.getRoot(), Reg, Op);
+  } else if (SrcVT < DestVT) {
+    // The src value is promoted to the register.
+    Op = DAG.getNode(ISD::ZERO_EXTEND, DestVT, Op);
+    return DAG.getCopyToReg(SDL.getRoot(), Reg, Op);
+  } else  {
+    // The src value is expanded into multiple registers.
+    SDOperand Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, DestVT,
+                               Op, DAG.getConstant(0, MVT::i32));
+    SDOperand Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, DestVT,
+                               Op, DAG.getConstant(1, MVT::i32));
+    Op = DAG.getCopyToReg(SDL.getRoot(), Reg, Lo);
+    return DAG.getCopyToReg(Op, Reg+1, Hi);
+  }
 }
 
 /// IsOnlyUsedInOneBasicBlock - If the specified argument is only used in a


Index: llvm/lib/CodeGen/SelectionDAG/SelectionDAGPrinter.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/SelectionDAGPrinter.cpp:1.19 llvm/lib/CodeGen/SelectionDAG/SelectionDAGPrinter.cpp:1.20
--- llvm/lib/CodeGen/SelectionDAG/SelectionDAGPrinter.cpp:1.19	Tue Aug 16 13:31:23 2005
+++ llvm/lib/CodeGen/SelectionDAG/SelectionDAGPrinter.cpp	Tue Aug 16 16:55:35 2005
@@ -72,8 +72,8 @@
     if (LBB)
       Op += LBB->getName();
     //Op += " " + (const void*)BBDN->getBasicBlock();
-  } else if (const RegSDNode *C2V = dyn_cast<RegSDNode>(Node)) {
-    Op += " #" + utostr(C2V->getReg());
+  } else if (const RegisterSDNode *R = dyn_cast<RegisterSDNode>(Node)) {
+    Op += " #" + utostr(R->getReg());
   } else if (const ExternalSymbolSDNode *ES =
              dyn_cast<ExternalSymbolSDNode>(Node)) {
     Op += "'" + std::string(ES->getSymbol()) + "'";





From lattner at cs.uiuc.edu  Tue Aug 16 16:56:49 2005
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Tue, 16 Aug 2005 16:56:49 -0500
Subject: [llvm-commits] CVS: llvm/lib/Target/X86/X86ISelPattern.cpp 
Message-ID: <200508162156.QAA17150@zion.cs.uiuc.edu>



Changes in directory llvm/lib/Target/X86:

X86ISelPattern.cpp updated: 1.169 -> 1.170
---
Log message:

update the backends to work with the new CopyFromReg/CopyToReg/ImplicitDef nodes


---
Diffs of the changes:  (+26 -28)

 X86ISelPattern.cpp |   54 +++++++++++++++++++++++++----------------------------
 1 files changed, 26 insertions(+), 28 deletions(-)


Index: llvm/lib/Target/X86/X86ISelPattern.cpp
diff -u llvm/lib/Target/X86/X86ISelPattern.cpp:1.169 llvm/lib/Target/X86/X86ISelPattern.cpp:1.170
--- llvm/lib/Target/X86/X86ISelPattern.cpp:1.169	Tue Aug 16 14:49:35 2005
+++ llvm/lib/Target/X86/X86ISelPattern.cpp	Tue Aug 16 16:56:37 2005
@@ -429,8 +429,8 @@
 
     // Arguments go on the stack in reverse order, as specified by the ABI.
     unsigned ArgOffset = 0;
-    SDOperand StackPtr = DAG.getCopyFromReg(X86::ESP, MVT::i32,
-                                            DAG.getEntryNode());
+    SDOperand StackPtr = DAG.getCopyFromReg(DAG.getEntryNode(),
+                                            X86::ESP, MVT::i32);
     std::vector<SDOperand> Stores;
 
     for (unsigned i = 0, e = Args.size(); i != e; ++i) {
@@ -627,7 +627,7 @@
         if (!I->use_empty()) {
           unsigned VReg = AddLiveIn(MF, NumIntRegs ? X86::DL : X86::AL,
                                     X86::R8RegisterClass);
-          ArgValue = DAG.getCopyFromReg(VReg, MVT::i8, DAG.getRoot());
+          ArgValue = DAG.getCopyFromReg(DAG.getRoot(), VReg, MVT::i8);
           DAG.setRoot(ArgValue.getValue(1));
         }
         ++NumIntRegs;
@@ -641,7 +641,7 @@
         if (!I->use_empty()) {
           unsigned VReg = AddLiveIn(MF, NumIntRegs ? X86::DX : X86::AX,
                                     X86::R16RegisterClass);
-          ArgValue = DAG.getCopyFromReg(VReg, MVT::i16, DAG.getRoot());
+          ArgValue = DAG.getCopyFromReg(DAG.getRoot(), VReg, MVT::i16);
           DAG.setRoot(ArgValue.getValue(1));
         }
         ++NumIntRegs;
@@ -654,7 +654,7 @@
         if (!I->use_empty()) {
           unsigned VReg = AddLiveIn(MF,NumIntRegs ? X86::EDX : X86::EAX,
                                     X86::R32RegisterClass);
-          ArgValue = DAG.getCopyFromReg(VReg, MVT::i32, DAG.getRoot());
+          ArgValue = DAG.getCopyFromReg(DAG.getRoot(), VReg, MVT::i32);
           DAG.setRoot(ArgValue.getValue(1));
         }
         ++NumIntRegs;
@@ -668,8 +668,8 @@
           unsigned BotReg = AddLiveIn(MF, X86::EAX, X86::R32RegisterClass);
           unsigned TopReg = AddLiveIn(MF, X86::EDX, X86::R32RegisterClass);
 
-          SDOperand Low=DAG.getCopyFromReg(BotReg, MVT::i32, DAG.getRoot());
-          SDOperand Hi =DAG.getCopyFromReg(TopReg, MVT::i32, Low.getValue(1));
+          SDOperand Low = DAG.getCopyFromReg(DAG.getRoot(), BotReg, MVT::i32);
+          SDOperand Hi  = DAG.getCopyFromReg(Low.getValue(1), TopReg, MVT::i32);
           DAG.setRoot(Hi.getValue(1));
 
           ArgValue = DAG.getNode(ISD::BUILD_PAIR, MVT::i64, Low, Hi);
@@ -679,7 +679,7 @@
       } else if (NumIntRegs == 1) {
         if (!I->use_empty()) {
           unsigned BotReg = AddLiveIn(MF, X86::EDX, X86::R32RegisterClass);
-          SDOperand Low = DAG.getCopyFromReg(BotReg, MVT::i32, DAG.getRoot());
+          SDOperand Low = DAG.getCopyFromReg(DAG.getRoot(), BotReg, MVT::i32);
           DAG.setRoot(Low.getValue(1));
 
           // Load the high part from memory.
@@ -809,8 +809,8 @@
 
   // Arguments go on the stack in reverse order, as specified by the ABI.
   unsigned ArgOffset = 0;
-  SDOperand StackPtr = DAG.getCopyFromReg(X86::ESP, MVT::i32,
-                                          DAG.getEntryNode());
+  SDOperand StackPtr = DAG.getCopyFromReg(DAG.getEntryNode(),
+                                          X86::ESP, MVT::i32);
   NumIntRegs = 0;
   std::vector<SDOperand> Stores;
   std::vector<SDOperand> RegValuesToPass;
@@ -2249,11 +2249,10 @@
   SDOperand Op0, Op1;
 
   if (Node->getOpcode() == ISD::CopyFromReg) {
-    if (MRegisterInfo::isVirtualRegister(cast<RegSDNode>(Node)->getReg()) ||
-        cast<RegSDNode>(Node)->getReg() == X86::ESP) {
-      // Just use the specified register as our input.
-      return cast<RegSDNode>(Node)->getReg();
-    }
+    unsigned Reg = cast<RegisterSDNode>(Node->getOperand(1))->getReg();
+    // Just use the specified register as our input if we can.
+    if (MRegisterInfo::isVirtualRegister(Reg) || Reg == X86::ESP)
+      return Reg;
   }
 
   unsigned &Reg = ExprMap[N];
@@ -2310,20 +2309,18 @@
       Reg = Result = ExprMap[N.getValue(0)] =
         MakeReg(N.getValue(0).getValueType());
     }
+    Tmp1 = cast<RegisterSDNode>(Node->getOperand(1))->getReg();
     switch (Node->getValueType(0)) {
     default: assert(0 && "Cannot CopyFromReg this!");
     case MVT::i1:
     case MVT::i8:
-      BuildMI(BB, X86::MOV8rr, 1,
-              Result).addReg(cast<RegSDNode>(Node)->getReg());
+      BuildMI(BB, X86::MOV8rr, 1, Result).addReg(Tmp1);
       return Result;
     case MVT::i16:
-      BuildMI(BB, X86::MOV16rr, 1,
-              Result).addReg(cast<RegSDNode>(Node)->getReg());
+      BuildMI(BB, X86::MOV16rr, 1, Result).addReg(Tmp1);
       return Result;
     case MVT::i32:
-      BuildMI(BB, X86::MOV32rr, 1,
-              Result).addReg(cast<RegSDNode>(Node)->getReg());
+      BuildMI(BB, X86::MOV32rr, 1, Result).addReg(Tmp1);
       return Result;
     }
 
@@ -4012,13 +4009,14 @@
 
   if (OrigDest.getOpcode() == ISD::CopyFromReg) {
     OrigOffset = 0;
-    assert(cast<RegSDNode>(OrigDest)->getReg() == X86::ESP);
+    assert(cast<RegisterSDNode>(OrigDest.getOperand(1))->getReg() == X86::ESP);
   } else {
     // We expect only (ESP+C)
     assert(OrigDest.getOpcode() == ISD::ADD &&
            isa<ConstantSDNode>(OrigDest.getOperand(1)) &&
            OrigDest.getOperand(0).getOpcode() == ISD::CopyFromReg &&
-           cast<RegSDNode>(OrigDest.getOperand(0))->getReg() == X86::ESP);
+           cast<RegisterSDNode>(OrigDest.getOperand(0).getOperand(1))->getReg()
+                 == X86::ESP);
     OrigOffset = cast<ConstantSDNode>(OrigDest.getOperand(1))->getValue();
   }
 
@@ -4181,17 +4179,17 @@
     }
     return;
   case ISD::CopyToReg:
-    if (getRegPressure(N.getOperand(0)) > getRegPressure(N.getOperand(1))) {
+    if (getRegPressure(N.getOperand(0)) > getRegPressure(N.getOperand(2))) {
       Select(N.getOperand(0));
-      Tmp1 = SelectExpr(N.getOperand(1));
+      Tmp1 = SelectExpr(N.getOperand(2));
     } else {
-      Tmp1 = SelectExpr(N.getOperand(1));
+      Tmp1 = SelectExpr(N.getOperand(2));
       Select(N.getOperand(0));
     }
-    Tmp2 = cast<RegSDNode>(N)->getReg();
+    Tmp2 = cast<RegisterSDNode>(N.getOperand(1))->getReg();
 
     if (Tmp1 != Tmp2) {
-      switch (N.getOperand(1).getValueType()) {
+      switch (N.getOperand(2).getValueType()) {
       default: assert(0 && "Invalid type for operation!");
       case MVT::i1:
       case MVT::i8:  Opc = X86::MOV8rr; break;





From lattner at cs.uiuc.edu  Tue Aug 16 16:56:49 2005
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Tue, 16 Aug 2005 16:56:49 -0500
Subject: [llvm-commits] CVS: llvm/lib/Target/IA64/IA64ISelPattern.cpp 
Message-ID: <200508162156.QAA17154@zion.cs.uiuc.edu>



Changes in directory llvm/lib/Target/IA64:

IA64ISelPattern.cpp updated: 1.54 -> 1.55
---
Log message:

update the backends to work with the new CopyFromReg/CopyToReg/ImplicitDef nodes


---
Diffs of the changes:  (+12 -9)

 IA64ISelPattern.cpp |   21 ++++++++++++---------
 1 files changed, 12 insertions(+), 9 deletions(-)


Index: llvm/lib/Target/IA64/IA64ISelPattern.cpp
diff -u llvm/lib/Target/IA64/IA64ISelPattern.cpp:1.54 llvm/lib/Target/IA64/IA64ISelPattern.cpp:1.55
--- llvm/lib/Target/IA64/IA64ISelPattern.cpp:1.54	Tue Aug 16 14:49:34 2005
+++ llvm/lib/Target/IA64/IA64ISelPattern.cpp	Tue Aug 16 16:56:37 2005
@@ -201,8 +201,8 @@
             // FP args go into f8..f15 as needed: (hence the ++)
             argPreg[count] = args_FP[used_FPArgs++];
             argOpc[count] = IA64::FMOV;
-            argt = newroot = DAG.getCopyFromReg(argVreg[count],
-                getValueType(I->getType()), DAG.getRoot());
+            argt = newroot = DAG.getCopyFromReg(DAG.getRoot(), argVreg[count],
+                                                getValueType(I->getType()));
             break;
           case MVT::i1: // NOTE: as far as C abi stuff goes,
                         // bools are just boring old ints
@@ -217,7 +217,7 @@
             argPreg[count] = args_int[count];
             argOpc[count] = IA64::MOV;
             argt = newroot =
-              DAG.getCopyFromReg(argVreg[count], MVT::i64, DAG.getRoot());
+              DAG.getCopyFromReg(DAG.getRoot(), argVreg[count], MVT::i64);
             if ( getValueType(I->getType()) != MVT::i64)
               argt = DAG.getNode(ISD::TRUNCATE, getValueType(I->getType()),
                   newroot);
@@ -919,7 +919,7 @@
 
   if (Node->getOpcode() == ISD::CopyFromReg)
     // Just use the specified register as our input.
-    return dyn_cast<RegSDNode>(Node)->getReg();
+    return cast<RegisterSDNode>(Node->getOperand(1))->getReg();
 
   unsigned &Reg = ExprMap[N];
   if (Reg) return Reg;
@@ -2026,7 +2026,7 @@
       SDOperand Chain   = N.getOperand(0);
 
       Select(Chain);
-      unsigned r = dyn_cast<RegSDNode>(Node)->getReg();
+      unsigned r = cast<RegisterSDNode>(Node->getOperand(1))->getReg();
 
       if(N.getValueType() == MVT::i1) // if a bool, we use pseudocode
         BuildMI(BB, IA64::PCMPEQUNC, 3, Result)
@@ -2209,17 +2209,19 @@
 
   case ISD::CopyToReg: {
     Select(N.getOperand(0));
-    Tmp1 = SelectExpr(N.getOperand(1));
-    Tmp2 = cast<RegSDNode>(N)->getReg();
+    Tmp1 = SelectExpr(N.getOperand(2));
+    Tmp2 = cast<RegisterSDNode>(N.getOperand(1))->getReg();
 
     if (Tmp1 != Tmp2) {
-      if(N.getValueType() == MVT::i1) // if a bool, we use pseudocode
+      // if a bool, we use pseudocode
+      if (N.getOperand(2).getValueType() == MVT::i1)
         BuildMI(BB, IA64::PCMPEQUNC, 3, Tmp2)
           .addReg(IA64::r0).addReg(IA64::r0).addReg(Tmp1);
                                    // (Tmp1) Tmp2 = cmp.eq.unc(r0,r0)
       else
         BuildMI(BB, IA64::MOV, 1, Tmp2).addReg(Tmp1);
                       // XXX is this the right way 'round? ;)
+      // FIXME: WHAT ABOUT FLOATING POINT?
     }
     return;
   }
@@ -2288,7 +2290,8 @@
 
   case ISD::ImplicitDef: {
     Select(N.getOperand(0));
-    BuildMI(BB, IA64::IDEF, 0, cast<RegSDNode>(N)->getReg());
+    BuildMI(BB, IA64::IDEF, 0, 
+            cast<RegisterSDNode>(N.getOperand(1))->getReg());
     return;
   }
 





From lattner at cs.uiuc.edu  Tue Aug 16 16:56:49 2005
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Tue, 16 Aug 2005 16:56:49 -0500
Subject: [llvm-commits] CVS: llvm/lib/Target/Alpha/AlphaISelPattern.cpp 
Message-ID: <200508162156.QAA17156@zion.cs.uiuc.edu>



Changes in directory llvm/lib/Target/Alpha:

AlphaISelPattern.cpp updated: 1.162 -> 1.163
---
Log message:

update the backends to work with the new CopyFromReg/CopyToReg/ImplicitDef nodes


---
Diffs of the changes:  (+11 -10)

 AlphaISelPattern.cpp |   21 +++++++++++----------
 1 files changed, 11 insertions(+), 10 deletions(-)


Index: llvm/lib/Target/Alpha/AlphaISelPattern.cpp
diff -u llvm/lib/Target/Alpha/AlphaISelPattern.cpp:1.162 llvm/lib/Target/Alpha/AlphaISelPattern.cpp:1.163
--- llvm/lib/Target/Alpha/AlphaISelPattern.cpp:1.162	Tue Aug 16 14:49:34 2005
+++ llvm/lib/Target/Alpha/AlphaISelPattern.cpp	Tue Aug 16 16:56:37 2005
@@ -283,7 +283,7 @@
       case MVT::f64:
       case MVT::f32:
         args_float[count] = AddLiveIn(MF,args_float[count], getRegClassFor(VT));
-        argt = DAG.getCopyFromReg(args_float[count], VT, DAG.getRoot());
+        argt = DAG.getCopyFromReg(DAG.getRoot(), args_float[count], VT);
         break;
       case MVT::i1:
       case MVT::i8:
@@ -292,7 +292,7 @@
       case MVT::i64:
         args_int[count] = AddLiveIn(MF, args_int[count],
                                     getRegClassFor(MVT::i64));
-        argt = DAG.getCopyFromReg(args_int[count], VT, DAG.getRoot());
+        argt = DAG.getCopyFromReg(DAG.getRoot(), args_int[count], VT);
         if (VT != MVT::i64)
           argt = DAG.getNode(ISD::TRUNCATE, VT, argt);
         break;
@@ -319,7 +319,7 @@
     for (int i = 0; i < 6; ++i) {
       if (args_int[i] < 1024)
         args_int[i] = AddLiveIn(MF,args_int[i], getRegClassFor(MVT::i64));
-      SDOperand argt = DAG.getCopyFromReg(args_int[i], MVT::i64, DAG.getRoot());
+      SDOperand argt = DAG.getCopyFromReg(DAG.getRoot(), args_int[i], MVT::i64);
       int FI = MFI->CreateFixedObject(8, -8 * (6 - i));
       if (i == 0) VarArgsBase = FI;
       SDOperand SDFI = DAG.getFrameIndex(FI, MVT::i64);
@@ -328,7 +328,7 @@
 
       if (args_float[i] < 1024)
         args_float[i] = AddLiveIn(MF,args_float[i], getRegClassFor(MVT::f64));
-      argt = DAG.getCopyFromReg(args_float[i], MVT::f64, DAG.getRoot());
+      argt = DAG.getCopyFromReg(DAG.getRoot(), args_float[i], MVT::f64);
       FI = MFI->CreateFixedObject(8, - 8 * (12 - i));
       SDFI = DAG.getFrameIndex(FI, MVT::i64);
       LS.push_back(DAG.getNode(ISD::STORE, MVT::Other, DAG.getRoot(), argt,
@@ -1634,7 +1634,7 @@
       SDOperand Chain   = N.getOperand(0);
 
       Select(Chain);
-      unsigned r = cast<RegSDNode>(Node)->getReg();
+      unsigned r = cast<RegisterSDNode>(Node->getOperand(1))->getReg();
       //std::cerr << "CopyFromReg " << Result << " = " << r << "\n";
       if (MVT::isFloatingPoint(N.getValue(0).getValueType()))
         BuildMI(BB, Alpha::CPYS, 2, Result).addReg(r).addReg(r);
@@ -2199,7 +2199,8 @@
   case ISD::ImplicitDef:
     ++count_ins;
     Select(N.getOperand(0));
-    BuildMI(BB, Alpha::IDEF, 0, cast<RegSDNode>(N)->getReg());
+    BuildMI(BB, Alpha::IDEF, 0,
+            cast<RegisterSDNode>(N.getOperand(1))->getReg());
     return;
 
   case ISD::EntryToken: return;  // Noop
@@ -2216,12 +2217,12 @@
   case ISD::CopyToReg:
     ++count_outs;
     Select(N.getOperand(0));
-    Tmp1 = SelectExpr(N.getOperand(1));
-    Tmp2 = cast<RegSDNode>(N)->getReg();
+    Tmp1 = SelectExpr(N.getOperand(2));
+    Tmp2 = cast<RegisterSDNode>(N.getOperand(1))->getReg();
 
     if (Tmp1 != Tmp2) {
-      if (N.getOperand(1).getValueType() == MVT::f64 ||
-          N.getOperand(1).getValueType() == MVT::f32)
+      if (N.getOperand(2).getValueType() == MVT::f64 ||
+          N.getOperand(2).getValueType() == MVT::f32)
         BuildMI(BB, Alpha::CPYS, 2, Tmp2).addReg(Tmp1).addReg(Tmp1);
       else
         BuildMI(BB, Alpha::BIS, 2, Tmp2).addReg(Tmp1).addReg(Tmp1);





From lattner at cs.uiuc.edu  Tue Aug 16 16:58:26 2005
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Tue, 16 Aug 2005 16:58:26 -0500
Subject: [llvm-commits] CVS: llvm/lib/Target/PowerPC/PPC32ISelLowering.cpp
	PPC32ISelPattern.cpp 
Message-ID: <200508162158.QAA17466@zion.cs.uiuc.edu>



Changes in directory llvm/lib/Target/PowerPC:

PPC32ISelLowering.cpp updated: 1.2 -> 1.3
PPC32ISelPattern.cpp updated: 1.143 -> 1.144
---
Log message:

updates for changes in nodes


---
Diffs of the changes:  (+21 -19)

 PPC32ISelLowering.cpp |   18 +++++++++---------
 PPC32ISelPattern.cpp  |   22 ++++++++++++----------
 2 files changed, 21 insertions(+), 19 deletions(-)


Index: llvm/lib/Target/PowerPC/PPC32ISelLowering.cpp
diff -u llvm/lib/Target/PowerPC/PPC32ISelLowering.cpp:1.2 llvm/lib/Target/PowerPC/PPC32ISelLowering.cpp:1.3
--- llvm/lib/Target/PowerPC/PPC32ISelLowering.cpp:1.2	Tue Aug 16 14:49:35 2005
+++ llvm/lib/Target/PowerPC/PPC32ISelLowering.cpp	Tue Aug 16 16:58:15 2005
@@ -128,8 +128,8 @@
         if (!ArgLive) break;
           if (GPR_remaining > 0) {
             MF.addLiveIn(GPR[GPR_idx]);
-            argt = newroot = DAG.getCopyFromReg(GPR[GPR_idx], MVT::i32,
-                                                DAG.getRoot());
+            argt = newroot = DAG.getCopyFromReg(DAG.getRoot(),
+                                                GPR[GPR_idx], MVT::i32);
             if (ObjectVT != MVT::i32)
               argt = DAG.getNode(ISD::TRUNCATE, ObjectVT, newroot);
           } else {
@@ -141,14 +141,14 @@
           if (GPR_remaining > 0) {
             SDOperand argHi, argLo;
             MF.addLiveIn(GPR[GPR_idx]);
-            argHi = DAG.getCopyFromReg(GPR[GPR_idx], MVT::i32, DAG.getRoot());
+            argHi = DAG.getCopyFromReg(DAG.getRoot(), GPR[GPR_idx], MVT::i32);
             // If we have two or more remaining argument registers, then both halves
             // of the i64 can be sourced from there.  Otherwise, the lower half will
             // have to come off the stack.  This can happen when an i64 is preceded
             // by 28 bytes of arguments.
             if (GPR_remaining > 1) {
               MF.addLiveIn(GPR[GPR_idx+1]);
-              argLo = DAG.getCopyFromReg(GPR[GPR_idx+1], MVT::i32, argHi);
+              argLo = DAG.getCopyFromReg(argHi, GPR[GPR_idx+1], MVT::i32);
             } else {
               int FI = MFI->CreateFixedObject(4, ArgOffset+4);
               SDOperand FIN = DAG.getFrameIndex(FI, MVT::i32);
@@ -168,8 +168,8 @@
         if (!ArgLive) break;
           if (FPR_remaining > 0) {
             MF.addLiveIn(FPR[FPR_idx]);
-            argt = newroot = DAG.getCopyFromReg(FPR[FPR_idx], ObjectVT,
-                                                DAG.getRoot());
+            argt = newroot = DAG.getCopyFromReg(DAG.getRoot(), 
+                                                FPR[FPR_idx], ObjectVT);
             --FPR_remaining;
             ++FPR_idx;
           } else {
@@ -217,7 +217,7 @@
     std::vector<SDOperand> MemOps;
     for (; GPR_remaining > 0; --GPR_remaining, ++GPR_idx) {
       MF.addLiveIn(GPR[GPR_idx]);
-      SDOperand Val = DAG.getCopyFromReg(GPR[GPR_idx], MVT::i32, DAG.getRoot());
+      SDOperand Val = DAG.getCopyFromReg(DAG.getRoot(), GPR[GPR_idx], MVT::i32);
       SDOperand Store = DAG.getNode(ISD::STORE, MVT::Other, Val.getValue(1),
                                     Val, FIN, DAG.getSrcValue(NULL));
       MemOps.push_back(Store);
@@ -298,8 +298,8 @@
     // Set up a copy of the stack pointer for use loading and storing any
     // arguments that may not fit in the registers available for argument
     // passing.
-    SDOperand StackPtr = DAG.getCopyFromReg(PPC::R1, MVT::i32,
-                                            DAG.getEntryNode());
+    SDOperand StackPtr = DAG.getCopyFromReg(DAG.getEntryNode(),
+                                            PPC::R1, MVT::i32);
     
     // Figure out which arguments are going to go in registers, and which in
     // memory.  Also, if this is a vararg function, floating point operations


Index: llvm/lib/Target/PowerPC/PPC32ISelPattern.cpp
diff -u llvm/lib/Target/PowerPC/PPC32ISelPattern.cpp:1.143 llvm/lib/Target/PowerPC/PPC32ISelPattern.cpp:1.144
--- llvm/lib/Target/PowerPC/PPC32ISelPattern.cpp:1.143	Tue Aug 16 14:49:35 2005
+++ llvm/lib/Target/PowerPC/PPC32ISelPattern.cpp	Tue Aug 16 16:58:15 2005
@@ -808,11 +808,12 @@
   SDNode *Node = N.Val;
   MVT::ValueType DestType = N.getValueType();
 
-  if (Node->getOpcode() == ISD::CopyFromReg &&
-      (MRegisterInfo::isVirtualRegister(cast<RegSDNode>(Node)->getReg()) ||
-       cast<RegSDNode>(Node)->getReg() == PPC::R1))
+  if (Node->getOpcode() == ISD::CopyFromReg) {
+    unsigned Reg = cast<RegisterSDNode>(Node->getOperand(1))->getReg();
     // Just use the specified register as our input.
-    return cast<RegSDNode>(Node)->getReg();
+    if (MRegisterInfo::isVirtualRegister(Reg) || Reg == PPC::R1)
+      return Reg;
+  }
 
   unsigned &Reg = ExprMap[N];
   if (Reg) return Reg;
@@ -1085,7 +1086,7 @@
     DestType = N.getValue(0).getValueType();
     if (Result == 1)
       Result = ExprMap[N.getValue(0)] = MakeReg(DestType);
-    Tmp1 = dyn_cast<RegSDNode>(Node)->getReg();
+    Tmp1 = dyn_cast<RegisterSDNode>(Node->getOperand(1))->getReg();
     if (MVT::isInteger(DestType))
       BuildMI(BB, PPC::OR, 2, Result).addReg(Tmp1).addReg(Tmp1);
     else
@@ -1877,12 +1878,12 @@
     return;
   case ISD::CopyToReg:
     Select(N.getOperand(0));
-    Tmp1 = SelectExpr(N.getOperand(1));
-    Tmp2 = cast<RegSDNode>(N)->getReg();
+    Tmp1 = SelectExpr(N.getOperand(2));
+    Tmp2 = cast<RegisterSDNode>(N.getOperand(1))->getReg();
 
     if (Tmp1 != Tmp2) {
-      if (N.getOperand(1).getValueType() == MVT::f64 ||
-          N.getOperand(1).getValueType() == MVT::f32)
+      if (N.getOperand(2).getValueType() == MVT::f64 ||
+          N.getOperand(2).getValueType() == MVT::f32)
         BuildMI(BB, PPC::FMR, 1, Tmp2).addReg(Tmp1);
       else
         BuildMI(BB, PPC::OR, 2, Tmp2).addReg(Tmp1).addReg(Tmp1);
@@ -1890,7 +1891,8 @@
     return;
   case ISD::ImplicitDef:
     Select(N.getOperand(0));
-    BuildMI(BB, PPC::IMPLICIT_DEF, 0, cast<RegSDNode>(N)->getReg());
+    BuildMI(BB, PPC::IMPLICIT_DEF, 0,
+            cast<RegisterSDNode>(N.getOperand(1))->getReg());
     return;
   case ISD::RET:
     switch (N.getNumOperands()) {





From lattner at cs.uiuc.edu  Tue Aug 16 17:00:04 2005
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Tue, 16 Aug 2005 17:00:04 -0500
Subject: [llvm-commits] CVS: llvm/lib/Bytecode/Reader/Reader.h 
Message-ID: <200508162200.RAA17632@zion.cs.uiuc.edu>



Changes in directory llvm/lib/Bytecode/Reader:

Reader.h updated: 1.23 -> 1.24
---
Log message:

This is a dummy, it doesn't matter what the ValueType is


---
Diffs of the changes:  (+1 -1)

 Reader.h |    2 +-
 1 files changed, 1 insertion(+), 1 deletion(-)


Index: llvm/lib/Bytecode/Reader/Reader.h
diff -u llvm/lib/Bytecode/Reader/Reader.h:1.23 llvm/lib/Bytecode/Reader/Reader.h:1.24
--- llvm/lib/Bytecode/Reader/Reader.h:1.23	Fri May  6 17:35:09 2005
+++ llvm/lib/Bytecode/Reader/Reader.h	Tue Aug 16 16:59:52 2005
@@ -80,7 +80,7 @@
   class ValueList : public User {
     std::vector<Use> Uses;
   public:
-    ValueList() : User(Type::VoidTy, Value::ValueListVal, 0, 0) {}
+    ValueList() : User(Type::VoidTy, Value::ArgumentVal, 0, 0) {}
 
     // vector compatibility methods
     unsigned size() const { return getNumOperands(); }





From lattner at cs.uiuc.edu  Tue Aug 16 17:05:10 2005
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Tue, 16 Aug 2005 17:05:10 -0500
Subject: [llvm-commits] CVS: llvm/include/llvm/Value.h 
Message-ID: <200508162205.RAA21942@zion.cs.uiuc.edu>



Changes in directory llvm/include/llvm:

Value.h updated: 1.76 -> 1.77
---
Log message:

remove a dead enum value, making a comment above correct again


---
Diffs of the changes:  (+0 -1)

 Value.h |    1 -
 1 files changed, 1 deletion(-)


Index: llvm/include/llvm/Value.h
diff -u llvm/include/llvm/Value.h:1.76 llvm/include/llvm/Value.h:1.77
--- llvm/include/llvm/Value.h:1.76	Thu Apr 21 15:11:51 2005
+++ llvm/include/llvm/Value.h	Tue Aug 16 17:04:58 2005
@@ -148,7 +148,6 @@
     ConstantAggregateZeroVal, // This is an instance of ConstantAggregateNull
     SimpleConstantVal,        // This is some other type of Constant
     InstructionVal,           // This is an instance of Instruction
-    ValueListVal              // This is for bcreader, a special ValTy
   };
   unsigned getValueType() const {
     return SubclassID;





From natebegeman at mac.com  Tue Aug 16 19:20:21 2005
From: natebegeman at mac.com (Nate Begeman)
Date: Tue, 16 Aug 2005 19:20:21 -0500
Subject: [llvm-commits] CVS: llvm/lib/Target/PowerPC/PPC32ISelPattern.cpp 
Message-ID: <200508170020.TAA30606@zion.cs.uiuc.edu>



Changes in directory llvm/lib/Target/PowerPC:

PPC32ISelPattern.cpp updated: 1.144 -> 1.145
---
Log message:

Implement a couple improvements:
Remove dead code in ISD::Constant handling
Add support for add long, imm16

We now codegen 'long long foo(long long a) { return ++a; }'
as:
addic r4, r4, 1
addze r3, r3
blr

instead of:
li r2, 1
li r5, 0
addc r2, r4, r2
adde r3, r3, r5
blr


---
Diffs of the changes:  (+28 -12)

 PPC32ISelPattern.cpp |   40 ++++++++++++++++++++++++++++------------
 1 files changed, 28 insertions(+), 12 deletions(-)


Index: llvm/lib/Target/PowerPC/PPC32ISelPattern.cpp
diff -u llvm/lib/Target/PowerPC/PPC32ISelPattern.cpp:1.144 llvm/lib/Target/PowerPC/PPC32ISelPattern.cpp:1.145
--- llvm/lib/Target/PowerPC/PPC32ISelPattern.cpp:1.144	Tue Aug 16 16:58:15 2005
+++ llvm/lib/Target/PowerPC/PPC32ISelPattern.cpp	Tue Aug 16 19:20:08 2005
@@ -1436,16 +1436,36 @@
   case ISD::SUB_PARTS: {
     assert(N.getNumOperands() == 4 && N.getValueType() == MVT::i32 &&
            "Not an i64 add/sub!");
-    // Emit all of the operands.
-    std::vector<unsigned> InVals;
-    for (unsigned i = 0, e = N.getNumOperands(); i != e; ++i)
-      InVals.push_back(SelectExpr(N.getOperand(i)));
+    unsigned Tmp4 = 0;
+    bool ME = isIntImmediate(N.getOperand(3),Tmp3) && ((signed)Tmp3 == -1);
+    bool ZE = isIntImmediate(N.getOperand(3),Tmp3) && (Tmp3 == 0);
+    bool IM = isIntImmediate(N.getOperand(2),Tmp3) && ((signed)Tmp3 >= -32768 ||
+                                                       (signed)Tmp3 <   32768);
+    Tmp1 = SelectExpr(N.getOperand(0));
+    Tmp2 = SelectExpr(N.getOperand(1));
+    if (!IM || N.getOpcode() == ISD::SUB_PARTS)
+      Tmp3 = SelectExpr(N.getOperand(2));
+    if ((!ME && !ZE) || N.getOpcode() == ISD::SUB_PARTS)
+      Tmp4 = SelectExpr(N.getOperand(3));
+    
     if (N.getOpcode() == ISD::ADD_PARTS) {
-      BuildMI(BB, PPC::ADDC, 2, Result).addReg(InVals[0]).addReg(InVals[2]);
-      BuildMI(BB, PPC::ADDE, 2, Result+1).addReg(InVals[1]).addReg(InVals[3]);
+      // Codegen the low 32 bits of the add.  Interestingly, there is no shifted
+      // form of add immediate carrying.
+      if (IM)
+        BuildMI(BB, PPC::ADDIC, 2, Result).addReg(Tmp1).addSImm(Tmp3);
+      else
+        BuildMI(BB, PPC::ADDC, 2, Result).addReg(Tmp1).addReg(Tmp3);
+      // Codegen the high 32 bits, adding zero, minus one, or the full value
+      // along with the carry flag produced by addc/addic to tmp2.
+      if (ZE)
+        BuildMI(BB, PPC::ADDZE, 1, Result+1).addReg(Tmp2);
+      else if (ME)
+        BuildMI(BB, PPC::ADDME, 1, Result+1).addReg(Tmp2);
+      else
+        BuildMI(BB, PPC::ADDE, 2, Result+1).addReg(Tmp2).addReg(Tmp4);
     } else {
-      BuildMI(BB, PPC::SUBFC, 2, Result).addReg(InVals[2]).addReg(InVals[0]);
-      BuildMI(BB, PPC::SUBFE, 2, Result+1).addReg(InVals[3]).addReg(InVals[1]);
+      BuildMI(BB, PPC::SUBFC, 2, Result).addReg(Tmp3).addReg(Tmp1);
+      BuildMI(BB, PPC::SUBFE, 2, Result+1).addReg(Tmp4).addReg(Tmp2);
     }
     return Result+N.ResNo;
   }
@@ -1716,10 +1736,6 @@
   case ISD::Constant:
     switch (N.getValueType()) {
     default: assert(0 && "Cannot use constants of this type!");
-    case MVT::i1:
-      BuildMI(BB, PPC::LI, 1, Result)
-        .addSImm(!cast<ConstantSDNode>(N)->isNullValue());
-      break;
     case MVT::i32:
       {
         int v = (int)cast<ConstantSDNode>(N)->getSignExtended();





From lattner at cs.uiuc.edu  Tue Aug 16 19:33:42 2005
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Tue, 16 Aug 2005 19:33:42 -0500
Subject: [llvm-commits] CVS: llvm/include/llvm/CodeGen/SelectionDAG.h
	SelectionDAGNodes.h 
Message-ID: <200508170033.TAA30817@zion.cs.uiuc.edu>



Changes in directory llvm/include/llvm/CodeGen:

SelectionDAG.h updated: 1.39 -> 1.40
SelectionDAGNodes.h updated: 1.51 -> 1.52
---
Log message:

add some helper methods, and a new TargetConstant node, which is not 
subjected to folding.


---
Diffs of the changes:  (+22 -4)

 SelectionDAG.h      |   15 ++++++++++++++-
 SelectionDAGNodes.h |   11 ++++++++---
 2 files changed, 22 insertions(+), 4 deletions(-)


Index: llvm/include/llvm/CodeGen/SelectionDAG.h
diff -u llvm/include/llvm/CodeGen/SelectionDAG.h:1.39 llvm/include/llvm/CodeGen/SelectionDAG.h:1.40
--- llvm/include/llvm/CodeGen/SelectionDAG.h:1.39	Tue Aug 16 16:54:41 2005
+++ llvm/include/llvm/CodeGen/SelectionDAG.h	Tue Aug 16 19:33:30 2005
@@ -94,6 +94,7 @@
   void RemoveDeadNodes(SDNode *N = 0);
 
   SDOperand getConstant(uint64_t Val, MVT::ValueType VT);
+  SDOperand getTargetConstant(uint64_t Val, MVT::ValueType VT);
   SDOperand getConstantFP(double Val, MVT::ValueType VT);
   SDOperand getGlobalAddress(const GlobalValue *GV, MVT::ValueType VT);
   SDOperand getFrameIndex(int FI, MVT::ValueType VT);
@@ -226,7 +227,18 @@
   void SelectNodeTo(SDNode *N, MVT::ValueType VT, unsigned TargetOpc,
                     SDOperand Op1, SDOperand Op2, SDOperand Op3);
   
-  
+  SDOperand getTargetNode(unsigned Opcode, MVT::ValueType VT,
+                          SDOperand Op1) {
+    return getNode(ISD::BUILTIN_OP_END+Opcode, VT, Op1);
+  }
+  SDOperand getTargetNode(unsigned Opcode, MVT::ValueType VT,
+                          SDOperand Op1, SDOperand Op2) {
+    return getNode(ISD::BUILTIN_OP_END+Opcode, VT, Op1, Op2);
+  }
+  SDOperand getTargetNode(unsigned Opcode, MVT::ValueType VT,
+                          SDOperand Op1, SDOperand Op2, SDOperand Op3) {
+    return getNode(ISD::BUILTIN_OP_END+Opcode, VT, Op1, Op2, Op3);
+  }
   void dump() const;
 
 private:
@@ -258,6 +270,7 @@
 
   std::map<const GlobalValue*, SDNode*> GlobalValues;
   std::map<std::pair<uint64_t, MVT::ValueType>, SDNode*> Constants;
+  std::map<std::pair<uint64_t, MVT::ValueType>, SDNode*> TargetConstants;
   std::map<std::pair<uint64_t, MVT::ValueType>, SDNode*> ConstantFPs;
   std::map<int, SDNode*> FrameIndices;
   std::map<unsigned, SDNode*> ConstantPoolIndices;


Index: llvm/include/llvm/CodeGen/SelectionDAGNodes.h
diff -u llvm/include/llvm/CodeGen/SelectionDAGNodes.h:1.51 llvm/include/llvm/CodeGen/SelectionDAGNodes.h:1.52
--- llvm/include/llvm/CodeGen/SelectionDAGNodes.h:1.51	Tue Aug 16 16:54:41 2005
+++ llvm/include/llvm/CodeGen/SelectionDAGNodes.h	Tue Aug 16 19:33:30 2005
@@ -56,6 +56,10 @@
     // Various leaf nodes.
     Constant, ConstantFP, GlobalAddress, FrameIndex, ConstantPool,
     BasicBlock, ExternalSymbol, VALUETYPE, CONDCODE, Register,
+    
+    // TargetConstant - Like Constant, but the DAG does not do any folding or
+    // simplification of the constant.  This is used by the DAG->DAG selector.
+    TargetConstant,
 
     // CopyToReg - This node has three operands: a chain, a register number to
     // set to this value, and a value.  
@@ -681,8 +685,8 @@
   uint64_t Value;
 protected:
   friend class SelectionDAG;
-  ConstantSDNode(uint64_t val, MVT::ValueType VT)
-    : SDNode(ISD::Constant, VT), Value(val) {
+  ConstantSDNode(bool isTarget, uint64_t val, MVT::ValueType VT)
+    : SDNode(isTarget ? ISD::TargetConstant : ISD::Constant, VT), Value(val) {
   }
 public:
 
@@ -702,7 +706,8 @@
 
   static bool classof(const ConstantSDNode *) { return true; }
   static bool classof(const SDNode *N) {
-    return N->getOpcode() == ISD::Constant;
+    return N->getOpcode() == ISD::Constant ||
+           N->getOpcode() == ISD::TargetConstant;
   }
 };
 





From lattner at cs.uiuc.edu  Tue Aug 16 19:34:17 2005
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Tue, 16 Aug 2005 19:34:17 -0500
Subject: [llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp 
Message-ID: <200508170034.TAA30874@zion.cs.uiuc.edu>



Changes in directory llvm/lib/CodeGen/SelectionDAG:

SelectionDAG.cpp updated: 1.143 -> 1.144
---
Log message:

add a new TargetConstant node


---
Diffs of the changes:  (+19 -1)

 SelectionDAG.cpp |   20 +++++++++++++++++++-
 1 files changed, 19 insertions(+), 1 deletion(-)


Index: llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp:1.143 llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp:1.144
--- llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp:1.143	Tue Aug 16 16:55:35 2005
+++ llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp	Tue Aug 16 19:34:06 2005
@@ -218,6 +218,10 @@
     Constants.erase(std::make_pair(cast<ConstantSDNode>(N)->getValue(),
                                    N->getValueType(0)));
     break;
+  case ISD::TargetConstant:
+    TargetConstants.erase(std::make_pair(cast<ConstantSDNode>(N)->getValue(),
+                                         N->getValueType(0)));
+    break;
   case ISD::ConstantFP: {
     union {
       double DV;
@@ -309,7 +313,20 @@
 
   SDNode *&N = Constants[std::make_pair(Val, VT)];
   if (N) return SDOperand(N, 0);
-  N = new ConstantSDNode(Val, VT);
+  N = new ConstantSDNode(false, Val, VT);
+  AllNodes.push_back(N);
+  return SDOperand(N, 0);
+}
+
+SDOperand SelectionDAG::getTargetConstant(uint64_t Val, MVT::ValueType VT) {
+  assert(MVT::isInteger(VT) && "Cannot create FP integer constant!");
+  // Mask out any bits that are not valid for this constant.
+  if (VT != MVT::i64)
+    Val &= ((uint64_t)1 << MVT::getSizeInBits(VT)) - 1;
+  
+  SDNode *&N = TargetConstants[std::make_pair(Val, VT)];
+  if (N) return SDOperand(N, 0);
+  N = new ConstantSDNode(true, Val, VT);
   AllNodes.push_back(N);
   return SDOperand(N, 0);
 }
@@ -1792,6 +1809,7 @@
   case ISD::EntryToken:    return "EntryToken";
   case ISD::TokenFactor:   return "TokenFactor";
   case ISD::Constant:      return "Constant";
+  case ISD::TargetConstant: return "TargetConstant";
   case ISD::ConstantFP:    return "ConstantFP";
   case ISD::GlobalAddress: return "GlobalAddress";
   case ISD::FrameIndex:    return "FrameIndex";





From jlaskey at apple.com  Tue Aug 16 19:39:40 2005
From: jlaskey at apple.com (Jim Laskey)
Date: Tue, 16 Aug 2005 19:39:40 -0500
Subject: [llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp 
Message-ID: <200508170039.TAA30893@zion.cs.uiuc.edu>



Changes in directory llvm/lib/CodeGen/SelectionDAG:

LegalizeDAG.cpp updated: 1.163 -> 1.164
---
Log message:


Added generic code expansion for [signed|unsigned] i32 to [f32|f64] casts in the 
legalizer.  PowerPC now uses this expansion instead of ISel version.

Example:

// signed integer to double conversion
double f1(signed x) {
  return (double)x;
}

// unsigned integer to double conversion
double f2(unsigned x) {
  return (double)x;
}

// signed integer to float conversion
float f3(signed x) {
  return (float)x;
}

// unsigned integer to float conversion
float f4(unsigned x) {
  return (float)x;
}


Byte Code:

internal fastcc double %_Z2f1i(int %x) {
entry:
        %tmp.1 = cast int %x to double          ; <double> [#uses=1]
        ret double %tmp.1
}

internal fastcc double %_Z2f2j(uint %x) {
entry:
        %tmp.1 = cast uint %x to double         ; <double> [#uses=1]
        ret double %tmp.1
}

internal fastcc float %_Z2f3i(int %x) {
entry:
        %tmp.1 = cast int %x to float           ; <float> [#uses=1]
        ret float %tmp.1
}

internal fastcc float %_Z2f4j(uint %x) {
entry:
        %tmp.1 = cast uint %x to float          ; <float> [#uses=1]
        ret float %tmp.1
}

internal fastcc double %_Z2g1i(int %x) {
entry:
        %buffer = alloca [2 x uint]             ; <[2 x uint]*> [#uses=3]
        %tmp.0 = getelementptr [2 x uint]* %buffer, int 0, int 0                ; <uint*> [#uses=1]
        store uint 1127219200, uint* %tmp.0
        %tmp.2 = cast int %x to uint            ; <uint> [#uses=1]
        %tmp.3 = xor uint %tmp.2, 2147483648            ; <uint> [#uses=1]
        %tmp.5 = getelementptr [2 x uint]* %buffer, int 0, int 1                ; <uint*> [#uses=1]
        store uint %tmp.3, uint* %tmp.5
        %tmp.9 = cast [2 x uint]* %buffer to double*            ; <double*> [#uses=1]
        %tmp.10 = load double* %tmp.9           ; <double> [#uses=1]
        %tmp.13 = load double* cast (long* %signed_bias to double*)             ; <double> [#uses=1]
        %tmp.14 = sub double %tmp.10, %tmp.13           ; <double> [#uses=1]
        ret double %tmp.14
}

internal fastcc double %_Z2g2j(uint %x) {
entry:
        %buffer = alloca [2 x uint]             ; <[2 x uint]*> [#uses=3]
        %tmp.0 = getelementptr [2 x uint]* %buffer, int 0, int 0                ; <uint*> [#uses=1]
        store uint 1127219200, uint* %tmp.0
        %tmp.1 = getelementptr [2 x uint]* %buffer, int 0, int 1                ; <uint*> [#uses=1]
        store uint %x, uint* %tmp.1
        %tmp.4 = cast [2 x uint]* %buffer to double*            ; <double*> [#uses=1]
        %tmp.5 = load double* %tmp.4            ; <double> [#uses=1]
        %tmp.8 = load double* cast (long* %unsigned_bias to double*)            ; <double> [#uses=1]
        %tmp.9 = sub double %tmp.5, %tmp.8              ; <double> [#uses=1]
        ret double %tmp.9
}

internal fastcc float %_Z2g3i(int %x) {
entry:
        %buffer = alloca [2 x uint]             ; <[2 x uint]*> [#uses=3]
        %tmp.0 = getelementptr [2 x uint]* %buffer, int 0, int 0                ; <uint*> [#uses=1]
        store uint 1127219200, uint* %tmp.0
        %tmp.2 = cast int %x to uint            ; <uint> [#uses=1]
        %tmp.3 = xor uint %tmp.2, 2147483648            ; <uint> [#uses=1]
        %tmp.5 = getelementptr [2 x uint]* %buffer, int 0, int 1                ; <uint*> [#uses=1]
        store uint %tmp.3, uint* %tmp.5
        %tmp.9 = cast [2 x uint]* %buffer to double*            ; <double*> [#uses=1]
        %tmp.10 = load double* %tmp.9           ; <double> [#uses=1]
        %tmp.13 = load double* cast (long* %signed_bias to double*)             ; <double> [#uses=1]
        %tmp.14 = sub double %tmp.10, %tmp.13           ; <double> [#uses=1]
        %tmp.16 = cast double %tmp.14 to float          ; <float> [#uses=1]
        ret float %tmp.16
}

internal fastcc float %_Z2g4j(uint %x) {
entry:
        %buffer = alloca [2 x uint]             ; <[2 x uint]*> [#uses=3]
        %tmp.0 = getelementptr [2 x uint]* %buffer, int 0, int 0                ; <uint*> [#uses=1]
        store uint 1127219200, uint* %tmp.0
        %tmp.1 = getelementptr [2 x uint]* %buffer, int 0, int 1                ; <uint*> [#uses=1]
        store uint %x, uint* %tmp.1
        %tmp.4 = cast [2 x uint]* %buffer to double*            ; <double*> [#uses=1]
        %tmp.5 = load double* %tmp.4            ; <double> [#uses=1]
        %tmp.8 = load double* cast (long* %unsigned_bias to double*)            ; <double> [#uses=1]
        %tmp.9 = sub double %tmp.5, %tmp.8              ; <double> [#uses=1]
        %tmp.11 = cast double %tmp.9 to float           ; <float> [#uses=1]
        ret float %tmp.11
}


PowerPC Code:

        .machine ppc970


        .const
        .align  2
.CPIl1__Z2f1i_0:                                        ; float 0x4330000080000000
        .long   1501560836      ; float 4.5036e+15
        .text
        .align  2
        .globl  l1__Z2f1i
l1__Z2f1i:
.LBBl1__Z2f1i_0:        ; entry
        xoris r2, r3, 32768
        stw r2, -4(r1)
        lis r2, 17200
        stw r2, -8(r1)
        lfd f0, -8(r1)
        lis r2, ha16(.CPIl1__Z2f1i_0)
        lfs f1, lo16(.CPIl1__Z2f1i_0)(r2)
        fsub f1, f0, f1
        blr


        .const
        .align  2
.CPIl2__Z2f2j_0:                                        ; float 0x4330000000000000
        .long   1501560832      ; float 4.5036e+15
        .text
        .align  2
        .globl  l2__Z2f2j
l2__Z2f2j:
.LBBl2__Z2f2j_0:        ; entry
        stw r3, -4(r1)
        lis r2, 17200
        stw r2, -8(r1)
        lfd f0, -8(r1)
        lis r2, ha16(.CPIl2__Z2f2j_0)
        lfs f1, lo16(.CPIl2__Z2f2j_0)(r2)
        fsub f1, f0, f1
        blr


        .const
        .align  2
.CPIl3__Z2f3i_0:                                        ; float 0x4330000080000000
        .long   1501560836      ; float 4.5036e+15
        .text
        .align  2
        .globl  l3__Z2f3i
l3__Z2f3i:
.LBBl3__Z2f3i_0:        ; entry
        xoris r2, r3, 32768
        stw r2, -4(r1)
        lis r2, 17200
        stw r2, -8(r1)
        lfd f0, -8(r1)
        lis r2, ha16(.CPIl3__Z2f3i_0)
        lfs f1, lo16(.CPIl3__Z2f3i_0)(r2)
        fsub f0, f0, f1
        frsp f1, f0
        blr


        .const
        .align  2
.CPIl4__Z2f4j_0:                                        ; float 0x4330000000000000
        .long   1501560832      ; float 4.5036e+15
        .text
        .align  2
        .globl  l4__Z2f4j
l4__Z2f4j:
.LBBl4__Z2f4j_0:        ; entry
        stw r3, -4(r1)
        lis r2, 17200
        stw r2, -8(r1)
        lfd f0, -8(r1)
        lis r2, ha16(.CPIl4__Z2f4j_0)
        lfs f1, lo16(.CPIl4__Z2f4j_0)(r2)
        fsub f0, f0, f1
        frsp f1, f0
        blr




---
Diffs of the changes:  (+72 -11)

 LegalizeDAG.cpp |   83 ++++++++++++++++++++++++++++++++++++++++++++++++--------
 1 files changed, 72 insertions(+), 11 deletions(-)


Index: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.163 llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.164
--- llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.163	Tue Aug 16 16:55:35 2005
+++ llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp	Tue Aug 16 19:39:29 2005
@@ -126,7 +126,9 @@
   SDOperand ExpandIntToFP(bool isSigned, MVT::ValueType DestTy,
                           SDOperand Source);
 
-  SDOperand ExpandLegalUINT_TO_FP(SDOperand LegalOp, MVT::ValueType DestVT);
+  SDOperand ExpandLegalINT_TO_FP(bool isSigned,
+                                 SDOperand LegalOp,
+                                 MVT::ValueType DestVT);
   SDOperand PromoteLegalINT_TO_FP(SDOperand LegalOp, MVT::ValueType DestVT,
                                   bool isSigned);
   SDOperand PromoteLegalFP_TO_INT(SDOperand LegalOp, MVT::ValueType DestVT,
@@ -155,12 +157,71 @@
          "Too many value types for ValueTypeActions to hold!");
 }
 
-/// ExpandLegalUINT_TO_FP - This function is responsible for legalizing a
-/// UINT_TO_FP operation of the specified operand when the target requests that
+/// ExpandLegalINT_TO_FP - This function is responsible for legalizing a
+/// INT_TO_FP operation of the specified operand when the target requests that
 /// we expand it.  At this point, we know that the result and operand types are
 /// legal for the target.
-SDOperand SelectionDAGLegalize::ExpandLegalUINT_TO_FP(SDOperand Op0,
-                                                      MVT::ValueType DestVT) {
+SDOperand SelectionDAGLegalize::ExpandLegalINT_TO_FP(bool isSigned,
+                                                     SDOperand Op0,
+                                                     MVT::ValueType DestVT) {
+  if (Op0.getValueType() == MVT::i32) {
+    // simple 32-bit [signed|unsigned] integer to float/double expansion
+    
+    // get the stack frame index of a 8 byte buffer
+    MachineFunction &MF = DAG.getMachineFunction();
+    int SSFI = MF.getFrameInfo()->CreateStackObject(8, 8);
+    // get address of 8 byte buffer
+    SDOperand StackSlot = DAG.getFrameIndex(SSFI, TLI.getPointerTy());
+    // word offset constant for Hi/Lo address computation
+    SDOperand WordOff = DAG.getConstant(sizeof(int), TLI.getPointerTy());
+    // set up Hi and Lo (into buffer) address based on endian
+    SDOperand Hi, Lo;
+    if (TLI.isLittleEndian()) {
+      Hi = DAG.getNode(ISD::ADD, TLI.getPointerTy(), StackSlot, WordOff);
+      Lo = StackSlot;
+    } else {
+      Hi = StackSlot;
+      Lo = DAG.getNode(ISD::ADD, TLI.getPointerTy(), StackSlot, WordOff);
+    }
+    // if signed map to unsigned space
+    SDOperand Op0Mapped;
+    if (isSigned) {
+      // constant used to invert sign bit (signed to unsigned mapping)
+      SDOperand SignBit = DAG.getConstant(0x80000000u, MVT::i32);
+      Op0Mapped = DAG.getNode(ISD::XOR, MVT::i32, Op0, SignBit);
+    } else {
+      Op0Mapped = Op0;
+    }
+    // store the lo of the constructed double - based on integer input
+    SDOperand Store1 = DAG.getNode(ISD::STORE, MVT::Other, DAG.getEntryNode(),
+                                   Op0Mapped, Lo, DAG.getSrcValue(NULL));
+    // initial hi portion of constructed double
+    SDOperand InitialHi = DAG.getConstant(0x43300000u, MVT::i32);
+    // store the hi of the constructed double - biased exponent
+    SDOperand Store2 = DAG.getNode(ISD::STORE, MVT::Other, Store1,
+                                   InitialHi, Hi, DAG.getSrcValue(NULL));
+    // load the constructed double
+    SDOperand Load = DAG.getLoad(MVT::f64, Store2, StackSlot,
+                               DAG.getSrcValue(NULL));
+    // FP constant to bias correct the final result
+    SDOperand Bias = DAG.getConstantFP(isSigned ? 0x1.000008p52 : 0x1.000000p52,
+                                     MVT::f64);
+    // subtract the bias
+    SDOperand Sub = DAG.getNode(ISD::SUB, MVT::f64, Load, Bias);
+    // final result
+    SDOperand Result;
+    // handle final rounding
+    if (DestVT == MVT::f64) {
+      // do nothing
+      Result = Sub;
+    } else {
+     // if f32 then cast to f32
+      Result = DAG.getNode(ISD::FP_ROUND, MVT::f32, Sub);
+    }
+    NeedsAnotherIteration = true;
+    return Result;
+  }
+  assert(!isSigned && "Legalize cannot Expand SINT_TO_FP for i64 yet");
   SDOperand Tmp1 = DAG.getNode(ISD::SINT_TO_FP, DestVT, Op0);
 
   SDOperand SignSet = DAG.getSetCC(TLI.getSetCCResultTy(), Op0,
@@ -170,9 +231,9 @@
   SDOperand CstOffset = DAG.getNode(ISD::SELECT, Zero.getValueType(),
                                     SignSet, Four, Zero);
 
-  // If the sign bit of the integer is set, the large number will be treated as
-  // a negative number.  To counteract this, the dynamic code adds an offset
-  // depending on the data type.
+  // If the sign bit of the integer is set, the large number will be treated
+  // as a negative number.  To counteract this, the dynamic code adds an
+  // offset depending on the data type.
   uint64_t FF;
   switch (Op0.getValueType()) {
   default: assert(0 && "Unsupported integer type!");
@@ -1648,9 +1709,9 @@
                                      Node->getOperand(0).getValueType())) {
       default: assert(0 && "Unknown operation action!");
       case TargetLowering::Expand:
-        assert(!isSigned && "Legalize cannot Expand SINT_TO_FP yet");
-        Result = ExpandLegalUINT_TO_FP(LegalizeOp(Node->getOperand(0)),
-                                       Node->getValueType(0));
+        Result = ExpandLegalINT_TO_FP(isSigned,
+                                      LegalizeOp(Node->getOperand(0)),
+                                      Node->getValueType(0));
         AddLegalizedOperand(Op, Result);
         return Result;
       case TargetLowering::Promote:





From jlaskey at apple.com  Tue Aug 16 19:40:33 2005
From: jlaskey at apple.com (Jim Laskey)
Date: Tue, 16 Aug 2005 19:40:33 -0500
Subject: [llvm-commits] CVS: llvm/lib/Target/PowerPC/PPC32ISelLowering.cpp 
Message-ID: <200508170040.TAA30911@zion.cs.uiuc.edu>



Changes in directory llvm/lib/Target/PowerPC:

PPC32ISelLowering.cpp updated: 1.3 -> 1.4
---
Log message:

Make UINT_TO_FP and SINT_TO_FP use generic expansion.



---
Diffs of the changes:  (+4 -0)

 PPC32ISelLowering.cpp |    4 ++++
 1 files changed, 4 insertions(+)


Index: llvm/lib/Target/PowerPC/PPC32ISelLowering.cpp
diff -u llvm/lib/Target/PowerPC/PPC32ISelLowering.cpp:1.3 llvm/lib/Target/PowerPC/PPC32ISelLowering.cpp:1.4
--- llvm/lib/Target/PowerPC/PPC32ISelLowering.cpp:1.3	Tue Aug 16 16:58:15 2005
+++ llvm/lib/Target/PowerPC/PPC32ISelLowering.cpp	Tue Aug 16 19:40:22 2005
@@ -74,6 +74,10 @@
   // PowerPC does not have FP_TO_UINT
   setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand);
   
+  // PowerPC does not have [U|S]INT_TO_FP
+  setOperationAction(ISD::SINT_TO_FP, MVT::i32, Expand);
+  setOperationAction(ISD::UINT_TO_FP, MVT::i32, Expand);
+
   setSetCCResultContents(ZeroOrOneSetCCResult);
   addLegalFPImmediate(+0.0); // Necessary for FSEL
   addLegalFPImmediate(-0.0); //





From jlaskey at apple.com  Tue Aug 16 19:41:51 2005
From: jlaskey at apple.com (Jim Laskey)
Date: Tue, 16 Aug 2005 19:41:51 -0500
Subject: [llvm-commits] CVS: llvm/lib/Target/PowerPC/PPC32ISelPattern.cpp 
Message-ID: <200508170041.TAA30926@zion.cs.uiuc.edu>



Changes in directory llvm/lib/Target/PowerPC:

PPC32ISelPattern.cpp updated: 1.145 -> 1.146
---
Log message:

Remove ISel code generation for UINT_TO_FP and SINT_TO_FP.  Now asserts if
marked as legal.


---
Diffs of the changes:  (+2 -34)

 PPC32ISelPattern.cpp |   36 ++----------------------------------
 1 files changed, 2 insertions(+), 34 deletions(-)


Index: llvm/lib/Target/PowerPC/PPC32ISelPattern.cpp
diff -u llvm/lib/Target/PowerPC/PPC32ISelPattern.cpp:1.145 llvm/lib/Target/PowerPC/PPC32ISelPattern.cpp:1.146
--- llvm/lib/Target/PowerPC/PPC32ISelPattern.cpp:1.145	Tue Aug 16 19:20:08 2005
+++ llvm/lib/Target/PowerPC/PPC32ISelPattern.cpp	Tue Aug 16 19:41:40 2005
@@ -1816,42 +1816,10 @@
     return Result;
 
   case ISD::UINT_TO_FP:
-  case ISD::SINT_TO_FP: {
-    assert (N.getOperand(0).getValueType() == MVT::i32
-            && "int to float must operate on i32");
-    bool IsUnsigned = (ISD::UINT_TO_FP == opcode);
-    Tmp1 = SelectExpr(N.getOperand(0));  // Get the operand register
-    Tmp2 = MakeFPReg(); // temp reg to load the integer value into
-    Tmp3 = MakeIntReg(); // temp reg to hold the conversion constant
-
-    int FrameIdx = BB->getParent()->getFrameInfo()->CreateStackObject(8, 8);
-    MachineConstantPool *CP = BB->getParent()->getConstantPool();
-    Opc = DestType == MVT::f64 ? PPC::FSUB : PPC::FSUBS;
-
-    if (IsUnsigned) {
-      unsigned ConstF = getConstDouble(0x1.000000p52);
-      // Store the hi & low halves of the fp value, currently in int regs
-      BuildMI(BB, PPC::LIS, 1, Tmp3).addSImm(0x4330);
-      addFrameReference(BuildMI(BB, PPC::STW, 3).addReg(Tmp3), FrameIdx);
-      addFrameReference(BuildMI(BB, PPC::STW, 3).addReg(Tmp1), FrameIdx, 4);
-      addFrameReference(BuildMI(BB, PPC::LFD, 2, Tmp2), FrameIdx);
-      // Generate the return value with a subtract
-      BuildMI(BB, Opc, 2, Result).addReg(Tmp2).addReg(ConstF);
-    } else {
-      unsigned ConstF = getConstDouble(0x1.000008p52);
-      unsigned TmpL = MakeIntReg();
-      // Store the hi & low halves of the fp value, currently in int regs
-      BuildMI(BB, PPC::LIS, 1, Tmp3).addSImm(0x4330);
-      addFrameReference(BuildMI(BB, PPC::STW, 3).addReg(Tmp3), FrameIdx);
-      BuildMI(BB, PPC::XORIS, 2, TmpL).addReg(Tmp1).addImm(0x8000);
-      addFrameReference(BuildMI(BB, PPC::STW, 3).addReg(TmpL), FrameIdx, 4);
-      addFrameReference(BuildMI(BB, PPC::LFD, 2, Tmp2), FrameIdx);
-      // Generate the return value with a subtract
-      BuildMI(BB, Opc, 2, Result).addReg(Tmp2).addReg(ConstF);
-    }
+  case ISD::SINT_TO_FP:
+    assert (0 && "int to float implemented in legalizer");
     return Result;
   }
-  }
   return 0;
 }
 





From alenhar2 at cs.uiuc.edu  Tue Aug 16 19:47:35 2005
From: alenhar2 at cs.uiuc.edu (Andrew Lenharth)
Date: Tue, 16 Aug 2005 19:47:35 -0500
Subject: [llvm-commits] CVS: llvm/lib/Target/Alpha/AlphaISelPattern.cpp 
Message-ID: <200508170047.TAA30996@zion.cs.uiuc.edu>



Changes in directory llvm/lib/Target/Alpha:

AlphaISelPattern.cpp updated: 1.163 -> 1.164
---
Log message:

thinko.  Should fix s4addl.ll regression

---
Diffs of the changes:  (+2 -2)

 AlphaISelPattern.cpp |    4 ++--
 1 files changed, 2 insertions(+), 2 deletions(-)


Index: llvm/lib/Target/Alpha/AlphaISelPattern.cpp
diff -u llvm/lib/Target/Alpha/AlphaISelPattern.cpp:1.163 llvm/lib/Target/Alpha/AlphaISelPattern.cpp:1.164
--- llvm/lib/Target/Alpha/AlphaISelPattern.cpp:1.163	Tue Aug 16 16:56:37 2005
+++ llvm/lib/Target/Alpha/AlphaISelPattern.cpp	Tue Aug 16 19:47:24 2005
@@ -606,7 +606,7 @@
 // If so Imm will receive the 64 bit value.
 static bool isSIntImmediateBounded(SDOperand N, int64_t& Imm, 
                                    int64_t low, int64_t high) {
-  if (isSIntImmediate(N, Imm) && Imm <= high && Imm >= high)
+  if (isSIntImmediate(N, Imm) && Imm <= high && Imm >= low)
     return true;
   return false;
 }
@@ -624,7 +624,7 @@
 
 static bool isUIntImmediateBounded(SDOperand N, uint64_t& Imm, 
                                    uint64_t low, uint64_t high) {
-  if (isUIntImmediate(N, Imm) && Imm <= high && Imm >= high)
+  if (isUIntImmediate(N, Imm) && Imm <= high && Imm >= low)
     return true;
   return false;
 }





From jlaskey at apple.com  Tue Aug 16 20:14:49 2005
From: jlaskey at apple.com (Jim Laskey)
Date: Tue, 16 Aug 2005 20:14:49 -0500
Subject: [llvm-commits] CVS: llvm/lib/Target/PowerPC/PPC32ISelPattern.cpp 
Message-ID: <200508170114.UAA31199@zion.cs.uiuc.edu>



Changes in directory llvm/lib/Target/PowerPC:

PPC32ISelPattern.cpp updated: 1.146 -> 1.147
---
Log message:

Removed UINT_TO_FP and SINT_TO_FP from ISel outright.


---
Diffs of the changes:  (+0 -5)

 PPC32ISelPattern.cpp |    5 -----
 1 files changed, 5 deletions(-)


Index: llvm/lib/Target/PowerPC/PPC32ISelPattern.cpp
diff -u llvm/lib/Target/PowerPC/PPC32ISelPattern.cpp:1.146 llvm/lib/Target/PowerPC/PPC32ISelPattern.cpp:1.147
--- llvm/lib/Target/PowerPC/PPC32ISelPattern.cpp:1.146	Tue Aug 16 19:41:40 2005
+++ llvm/lib/Target/PowerPC/PPC32ISelPattern.cpp	Tue Aug 16 20:14:38 2005
@@ -1814,11 +1814,6 @@
     Tmp1 = SelectExpr(N.getOperand(0));
     BuildMI(BB, PPC::FMR, 1, Result).addReg(Tmp1);
     return Result;
-
-  case ISD::UINT_TO_FP:
-  case ISD::SINT_TO_FP:
-    assert (0 && "int to float implemented in legalizer");
-    return Result;
   }
   return 0;
 }





From lattner at cs.uiuc.edu  Tue Aug 16 20:25:25 2005
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Tue, 16 Aug 2005 20:25:25 -0500
Subject: [llvm-commits] CVS: llvm/lib/Target/PowerPC/PPC32ISelPattern.cpp 
Message-ID: <200508170125.UAA31497@zion.cs.uiuc.edu>



Changes in directory llvm/lib/Target/PowerPC:

PPC32ISelPattern.cpp updated: 1.147 -> 1.148
---
Log message:

Fix a few small typos I noticed when converting this over to the DAG->DAG 
selector.  Also, there is no difference between addSImm and addImm, so just
use addImm, folding some branches.


---
Diffs of the changes:  (+11 -12)

 PPC32ISelPattern.cpp |   23 +++++++++++------------
 1 files changed, 11 insertions(+), 12 deletions(-)


Index: llvm/lib/Target/PowerPC/PPC32ISelPattern.cpp
diff -u llvm/lib/Target/PowerPC/PPC32ISelPattern.cpp:1.147 llvm/lib/Target/PowerPC/PPC32ISelPattern.cpp:1.148
--- llvm/lib/Target/PowerPC/PPC32ISelPattern.cpp:1.147	Tue Aug 16 20:14:38 2005
+++ llvm/lib/Target/PowerPC/PPC32ISelPattern.cpp	Tue Aug 16 20:25:14 2005
@@ -36,14 +36,15 @@
 using namespace llvm;
 
 namespace {
-Statistic<>Recorded("ppc-codegen", "Number of recording ops emitted");
-Statistic<>FusedFP("ppc-codegen", "Number of fused fp operations");
-Statistic<>FrameOff("ppc-codegen", "Number of frame idx offsets collapsed");
+Statistic<> Recorded("ppc-codegen", "Number of recording ops emitted");
+Statistic<> FusedFP ("ppc-codegen", "Number of fused fp operations");
+Statistic<> FrameOff("ppc-codegen", "Number of frame idx offsets collapsed");
 
 //===--------------------------------------------------------------------===//
-/// ISel - PPC32 specific code to select PPC32 machine instructions for
-/// SelectionDAG operations.
+// ISel - PPC32 specific code to select PPC32 machine instructions for
+// SelectionDAG operations.
 //===--------------------------------------------------------------------===//
+
 class ISel : public SelectionDAGISel {
   PPC32TargetLowering PPC32Lowering;
   SelectionDAG *ISelDAG;  // Hack to support us having a dag->dag transform
@@ -764,7 +765,7 @@
   // exit if not a constant
   if (!CN) return false;
   // extract immediate
-  unsigned C = (unsigned)CN->getSignExtended();
+  unsigned C = (unsigned)CN->getValue();
   // negate if required (ISD::SUB)
   if (Negate) C = -C;
   // get the hi and lo portions of constant
@@ -784,17 +785,15 @@
   unsigned Opr0 = SelectExpr(N.getOperand(0));
   // is a lo instruction needed
   if (Lo) {
-    // generate instruction for hi portion
-    const MachineInstrBuilder &MIBLo = BuildMI(BB, OCLo, 2, Tmp).addReg(Opr0);
-    if (IsArithmetic) MIBLo.addSImm(Lo); else MIBLo.addImm(Lo);
+    // generate instruction for lo portion
+    BuildMI(BB, OCLo, 2, Tmp).addReg(Opr0).addImm(Lo);
     // need to switch out first operand for hi instruction
     Opr0 = Tmp;
   }
-  // is a ho instruction needed
+  // is a hi instruction needed
   if (Hi) {
     // generate instruction for hi portion
-    const MachineInstrBuilder &MIBHi = BuildMI(BB, OCHi, 2, Result).addReg(Opr0);
-    if (IsArithmetic) MIBHi.addSImm(Hi); else MIBHi.addImm(Hi);
+    BuildMI(BB, OCHi, 2, Result).addReg(Opr0).addImm(Hi);
   }
   return true;
 }





From lattner at cs.uiuc.edu  Tue Aug 16 20:54:12 2005
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Tue, 16 Aug 2005 20:54:12 -0500
Subject: [llvm-commits] CVS: llvm/include/llvm/CodeGen/SelectionDAGNodes.h 
Message-ID: <200508170154.UAA31713@zion.cs.uiuc.edu>



Changes in directory llvm/include/llvm/CodeGen:

SelectionDAGNodes.h updated: 1.52 -> 1.53
---
Log message:

make sure to remove a node from the use list of its operands when we replace
it.


---
Diffs of the changes:  (+8 -1)

 SelectionDAGNodes.h |    9 ++++++++-
 1 files changed, 8 insertions(+), 1 deletion(-)


Index: llvm/include/llvm/CodeGen/SelectionDAGNodes.h
diff -u llvm/include/llvm/CodeGen/SelectionDAGNodes.h:1.52 llvm/include/llvm/CodeGen/SelectionDAGNodes.h:1.53
--- llvm/include/llvm/CodeGen/SelectionDAGNodes.h:1.52	Tue Aug 16 19:33:30 2005
+++ llvm/include/llvm/CodeGen/SelectionDAGNodes.h	Tue Aug 16 20:54:00 2005
@@ -614,7 +614,14 @@
   void MorphNodeTo(unsigned Opc) {
     NodeType = Opc;
     Values.clear();
-    Operands.clear();
+    
+    // Clear the operands list, updating used nodes to remove this from their
+    // use list.
+    while (!Operands.empty()) {
+      SDNode *O = Operands.back().Val;
+      Operands.pop_back();
+      O->removeUser(this);
+    }
   }
   
   void setValueTypes(MVT::ValueType VT) {





From jeffc at jolt-lang.org  Tue Aug 16 20:58:08 2005
From: jeffc at jolt-lang.org (Jeff Cohen)
Date: Tue, 16 Aug 2005 18:58:08 -0700
Subject: [llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
Message-ID: <430299B0.7030907@jolt-lang.org>

VC++ does not accept 0x1.000008p52 as a legal number.  It complains 
about an invalid suffix.  This is a C99 feature, and VC++ (as of .NET 
2003) is not C99-compliant.



From brukman at cs.uiuc.edu  Tue Aug 16 21:39:07 2005
From: brukman at cs.uiuc.edu (Misha Brukman)
Date: Tue, 16 Aug 2005 21:39:07 -0500
Subject: [llvm-commits] CVS: llvm/Makefile.rules 
Message-ID: <200508170239.VAA01127@zion.cs.uiuc.edu>



Changes in directory llvm:

Makefile.rules updated: 1.318 -> 1.319
---
Log message:

Fix grammar


---
Diffs of the changes:  (+1 -1)

 Makefile.rules |    2 +-
 1 files changed, 1 insertion(+), 1 deletion(-)


Index: llvm/Makefile.rules
diff -u llvm/Makefile.rules:1.318 llvm/Makefile.rules:1.319
--- llvm/Makefile.rules:1.318	Sat Aug 13 00:09:50 2005
+++ llvm/Makefile.rules	Tue Aug 16 21:38:56 2005
@@ -625,7 +625,7 @@
 # (defined by the user's project) and "LLVM" libs (defined 
 # by the # LLVM project).
 #---------------------------------------------------------
-#some versions of gcc on alpha produce to many symbols, so use a .a file
+# Some versions of gcc on Alpha produce too many symbols, so use a .a file
 ifeq ($(ARCH),Alpha)
 USEDLIBS :=  $(subst LLVMCore, LLVMCore.a, $(USEDLIBS))
 LLVMLIBS := $(subst LLVMCore, LLVMCore.a, $(LLVMLIBS))





From lattner at cs.uiuc.edu  Wed Aug 17 01:06:36 2005
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Wed, 17 Aug 2005 01:06:36 -0500
Subject: [llvm-commits] 
	CVS: llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
Message-ID: <200508170606.BAA27252@zion.cs.uiuc.edu>



Changes in directory llvm/lib/CodeGen/SelectionDAG:

SelectionDAGISel.cpp updated: 1.69 -> 1.70
---
Log message:

Fix a regression on X86, where FP values can be promoted too.


---
Diffs of the changes:  (+4 -1)

 SelectionDAGISel.cpp |    5 ++++-
 1 files changed, 4 insertions(+), 1 deletion(-)


Index: llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.69 llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.70
--- llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.69	Tue Aug 16 16:55:35 2005
+++ llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp	Wed Aug 17 01:06:25 2005
@@ -991,7 +991,10 @@
     return DAG.getCopyToReg(SDL.getRoot(), Reg, Op);
   } else if (SrcVT < DestVT) {
     // The src value is promoted to the register.
-    Op = DAG.getNode(ISD::ZERO_EXTEND, DestVT, Op);
+    if (MVT::isFloatingPoint(SrcVT))
+      Op = DAG.getNode(ISD::FP_EXTEND, DestVT, Op);
+    else
+      Op = DAG.getNode(ISD::ZERO_EXTEND, DestVT, Op);
     return DAG.getCopyToReg(SDL.getRoot(), Reg, Op);
   } else  {
     // The src value is expanded into multiple registers.





From lattner at cs.uiuc.edu  Wed Aug 17 01:34:49 2005
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Wed, 17 Aug 2005 01:34:49 -0500
Subject: [llvm-commits] 
	CVS: llvm/include/llvm/Transforms/Utils/BasicBlockUtils.h
Message-ID: <200508170634.BAA01857@zion.cs.uiuc.edu>



Changes in directory llvm/include/llvm/Transforms/Utils:

BasicBlockUtils.h updated: 1.9 -> 1.10
---
Log message:

add a helper


---
Diffs of the changes:  (+7 -0)

 BasicBlockUtils.h |    7 +++++++
 1 files changed, 7 insertions(+)


Index: llvm/include/llvm/Transforms/Utils/BasicBlockUtils.h
diff -u llvm/include/llvm/Transforms/Utils/BasicBlockUtils.h:1.9 llvm/include/llvm/Transforms/Utils/BasicBlockUtils.h:1.10
--- llvm/include/llvm/Transforms/Utils/BasicBlockUtils.h:1.9	Thu Apr 21 15:59:05 2005
+++ llvm/include/llvm/Transforms/Utils/BasicBlockUtils.h	Wed Aug 17 01:34:37 2005
@@ -84,6 +84,13 @@
   return MadeChange;
 }
 
+inline bool SplitCriticalEdge(BasicBlock *Src, BasicBlock *Dst, Pass *P = 0) {
+  for (succ_iterator SI = succ_begin(Src); ; ++SI) {
+    assert(SI != succ_end(Src) && "Edge doesn't exist");
+    if (*SI == Dst)
+      return SplitCriticalEdge(Src, SI, P);
+  }
+}
 } // End llvm namespace
 
 #endif





From lattner at cs.uiuc.edu  Wed Aug 17 01:35:28 2005
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Wed, 17 Aug 2005 01:35:28 -0500
Subject: [llvm-commits] 
	CVS: llvm/lib/Transforms/Scalar/LoopStrengthReduce.cpp
Message-ID: <200508170635.BAA02514@zion.cs.uiuc.edu>



Changes in directory llvm/lib/Transforms/Scalar:

LoopStrengthReduce.cpp updated: 1.52 -> 1.53
---
Log message:

Use a new helper to split critical edges, making the code simpler.

Do not claim to not change the CFG.  We do change the cfg to split critical
edges.  This isn't causing us a problem now, but could likely do so in the 
future.


---
Diffs of the changes:  (+21 -18)

 LoopStrengthReduce.cpp |   39 +++++++++++++++++++++------------------
 1 files changed, 21 insertions(+), 18 deletions(-)


Index: llvm/lib/Transforms/Scalar/LoopStrengthReduce.cpp
diff -u llvm/lib/Transforms/Scalar/LoopStrengthReduce.cpp:1.52 llvm/lib/Transforms/Scalar/LoopStrengthReduce.cpp:1.53
--- llvm/lib/Transforms/Scalar/LoopStrengthReduce.cpp:1.52	Mon Aug 15 19:38:11 2005
+++ llvm/lib/Transforms/Scalar/LoopStrengthReduce.cpp	Wed Aug 17 01:35:16 2005
@@ -119,7 +119,15 @@
     }
 
     virtual void getAnalysisUsage(AnalysisUsage &AU) const {
-      AU.setPreservesCFG();
+      // We split critical edges, so we change the CFG.  However, we do update
+      // many analyses if they are around.
+      AU.addPreservedID(LoopSimplifyID);
+      AU.addPreserved<LoopInfo>();
+      AU.addPreserved<DominatorSet>();
+      AU.addPreserved<ImmediateDominators>();
+      AU.addPreserved<DominanceFrontier>();
+      AU.addPreserved<DominatorTree>();
+
       AU.addRequiredID(LoopSimplifyID);
       AU.addRequired<LoopInfo>();
       AU.addRequired<DominatorSet>();
@@ -440,25 +448,20 @@
       // code on all predecessor/successor paths.
       if (e != 1 &&
           PN->getIncomingBlock(i)->getTerminator()->getNumSuccessors() > 1) {
-        TerminatorInst *PredTI = PN->getIncomingBlock(i)->getTerminator();
-        for (unsigned Succ = 0; ; ++Succ) {
-          assert(Succ != PredTI->getNumSuccessors() &&"Didn't find successor?");
-          if (PredTI->getSuccessor(Succ) == PN->getParent()) {
-            // First step, split the critical edge.
-            SplitCriticalEdge(PredTI, Succ, P);
+
+        // First step, split the critical edge.
+        SplitCriticalEdge(PN->getIncomingBlock(i), PN->getParent(), P);
             
-            // Next step: move the basic block.  In particular, if the PHI node
-            // is outside of the loop, and PredTI is in the loop, we want to
-            // move the block to be immediately before the PHI block, not
-            // immediately after PredTI.
-            if (L->contains(PredTI->getParent()) &&
-                !L->contains(PN->getParent())) {
-              BasicBlock *NewBB = PN->getIncomingBlock(i);
-              NewBB->moveBefore(PN->getParent());
-            }
-            break;
-          }
+        // Next step: move the basic block.  In particular, if the PHI node
+        // is outside of the loop, and PredTI is in the loop, we want to
+        // move the block to be immediately before the PHI block, not
+        // immediately after PredTI.
+        if (L->contains(PN->getIncomingBlock(i)) &&
+            !L->contains(PN->getParent())) {
+          BasicBlock *NewBB = PN->getIncomingBlock(i);
+          NewBB->moveBefore(PN->getParent());
         }
+        break;
       }
 
       Value *&Code = InsertedCode[PN->getIncomingBlock(i)];





From lattner at cs.uiuc.edu  Wed Aug 17 01:37:55 2005
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Wed, 17 Aug 2005 01:37:55 -0500
Subject: [llvm-commits] 
	CVS: llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
Message-ID: <200508170637.BAA02850@zion.cs.uiuc.edu>



Changes in directory llvm/lib/CodeGen/SelectionDAG:

SelectionDAGISel.cpp updated: 1.70 -> 1.71
---
Log message:

Add a new beta option for critical edge splitting, to avoid a problem that
Nate noticed in yacr2 (and I know occurs in other places as well).

This is still rough, as the critical edge blocks are not intelligently placed
but is added to get some idea to see if this improves performance.



---
Diffs of the changes:  (+23 -0)

 SelectionDAGISel.cpp |   23 +++++++++++++++++++++++
 1 files changed, 23 insertions(+)


Index: llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.70 llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.71
--- llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.70	Wed Aug 17 01:06:25 2005
+++ llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp	Wed Aug 17 01:37:43 2005
@@ -29,12 +29,18 @@
 #include "llvm/Target/TargetInstrInfo.h"
 #include "llvm/Target/TargetLowering.h"
 #include "llvm/Target/TargetMachine.h"
+#include "llvm/Transforms/Utils/BasicBlockUtils.h"
 #include "llvm/Support/CommandLine.h"
 #include "llvm/Support/Debug.h"
 #include <map>
 #include <iostream>
 using namespace llvm;
 
+static cl::opt<bool>
+SplitPHICritEdges("split-phi-constant-crit-edges", cl::Hidden,
+         cl::desc("Split critical edges for PHI values that are constants"));
+
+
 #ifndef _NDEBUG
 static cl::opt<bool>
 ViewDAGs("view-isel-dags", cl::Hidden,
@@ -959,6 +965,10 @@
   return RegMap->createVirtualRegister(TLI.getRegClassFor(VT));
 }
 
+void SelectionDAGISel::getAnalysisUsage(AnalysisUsage &AU) const {
+  if (!SplitPHICritEdges)
+    AU.setPreservesAll();
+}
 
 
 bool SelectionDAGISel::runOnFunction(Function &Fn) {
@@ -966,6 +976,19 @@
   RegMap = MF.getSSARegMap();
   DEBUG(std::cerr << "\n\n\n=== " << Fn.getName() << "\n");
 
+  // First pass, split all critical edges for PHI nodes with incoming values
+  // that are constants, this way the load of the constant into a vreg will not
+  // be placed into MBBs that are used some other way.
+  if (SplitPHICritEdges)
+    for (Function::iterator BB = Fn.begin(), E = Fn.end(); BB != E; ++BB) {
+      PHINode *PN;
+      for (BasicBlock::iterator BBI = BB->begin();
+           (PN = dyn_cast<PHINode>(BBI)); ++BBI)
+        for (unsigned i = 0, e = PN->getNumIncomingValues(); i != e; ++i)
+          if (isa<Constant>(PN->getIncomingValue(i)))
+            SplitCriticalEdge(PN->getIncomingBlock(i), BB);
+    }
+
   FunctionLoweringInfo FuncInfo(TLI, Fn, MF);
 
   for (Function::iterator I = Fn.begin(), E = Fn.end(); I != E; ++I)





From lattner at cs.uiuc.edu  Wed Aug 17 01:38:16 2005
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Wed, 17 Aug 2005 01:38:16 -0500
Subject: [llvm-commits] CVS: llvm-test/Makefile.programs 
Message-ID: <200508170638.BAA02867@zion.cs.uiuc.edu>



Changes in directory llvm-test:

Makefile.programs updated: 1.162 -> 1.163
---
Log message:

Switch PPC and X86 to test -split-phi-constant-crit-edges tonight


---
Diffs of the changes:  (+3 -2)

 Makefile.programs |    5 +++--
 1 files changed, 3 insertions(+), 2 deletions(-)


Index: llvm-test/Makefile.programs
diff -u llvm-test/Makefile.programs:1.162 llvm-test/Makefile.programs:1.163
--- llvm-test/Makefile.programs:1.162	Mon Aug 15 18:48:22 2005
+++ llvm-test/Makefile.programs	Wed Aug 17 01:38:05 2005
@@ -187,14 +187,15 @@
 endif#DISABLE_DIFFS
 
 ifeq ($(ARCH),PowerPC)
-LLCBETAOPTION := 
+LLCBETAOPTION := -split-phi-constant-crit-edges
 endif
 ifeq ($(ARCH),Alpha)
 LLCBETAOPTION := -enable-alpha-FTOI -enable-lsr-for-alpha
 #-enable-alpha-intfpdiv
 endif
 ifeq ($(ARCH),x86)
-LLCBETAOPTION := -enable-x86-fastcc
+LLCBETAOPTION := -split-phi-constant-crit-edges
+#-enable-x86-fastcc
 endif
 
 # Given a version of the entire program linked together into a single unit of





From lattner at cs.uiuc.edu  Wed Aug 17 01:47:01 2005
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Wed, 17 Aug 2005 01:47:01 -0500
Subject: [llvm-commits] CVS: llvm/include/llvm/CodeGen/SelectionDAGISel.h 
Message-ID: <200508170647.BAA03002@zion.cs.uiuc.edu>



Changes in directory llvm/include/llvm/CodeGen:

SelectionDAGISel.h updated: 1.5 -> 1.6
---
Log message:

This was moved to the .cpp file


---
Diffs of the changes:  (+1 -3)

 SelectionDAGISel.h |    4 +---
 1 files changed, 1 insertion(+), 3 deletions(-)


Index: llvm/include/llvm/CodeGen/SelectionDAGISel.h
diff -u llvm/include/llvm/CodeGen/SelectionDAGISel.h:1.5 llvm/include/llvm/CodeGen/SelectionDAGISel.h:1.6
--- llvm/include/llvm/CodeGen/SelectionDAGISel.h:1.5	Fri May 13 02:23:03 2005
+++ llvm/include/llvm/CodeGen/SelectionDAGISel.h	Wed Aug 17 01:46:50 2005
@@ -40,9 +40,7 @@
 
   SelectionDAGISel(TargetLowering &tli) : TLI(tli) {}
 
-  virtual void getAnalysisUsage(AnalysisUsage &AU) const {
-    AU.setPreservesAll();
-  }
+  virtual void getAnalysisUsage(AnalysisUsage &AU) const;
 
   virtual bool runOnFunction(Function &Fn);
 





From jlaskey at apple.com  Wed Aug 17 04:45:11 2005
From: jlaskey at apple.com (Jim Laskey)
Date: Wed, 17 Aug 2005 04:45:11 -0500
Subject: [llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp 
Message-ID: <200508170945.EAA04982@zion.cs.uiuc.edu>



Changes in directory llvm/lib/CodeGen/SelectionDAG:

LegalizeDAG.cpp updated: 1.164 -> 1.165
---
Log message:

Change hex float constants for the sake of VC++.



---
Diffs of the changes:  (+4 -1)

 LegalizeDAG.cpp |    5 ++++-
 1 files changed, 4 insertions(+), 1 deletion(-)


Index: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.164 llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.165
--- llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.164	Tue Aug 16 19:39:29 2005
+++ llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp	Wed Aug 17 04:44:59 2005
@@ -204,7 +204,10 @@
     SDOperand Load = DAG.getLoad(MVT::f64, Store2, StackSlot,
                                DAG.getSrcValue(NULL));
     // FP constant to bias correct the final result
-    SDOperand Bias = DAG.getConstantFP(isSigned ? 0x1.000008p52 : 0x1.000000p52,
+    uint64_t   SignedBias = 0x4330000080000000ULL;
+    uint64_t UnsignedBias = 0x4330000000000000ULL;
+    SDOperand Bias = DAG.getConstantFP(isSigned ? *(double *)&SignedBias
+                                                : *(double *)&UnsignedBias,
                                      MVT::f64);
     // subtract the bias
     SDOperand Sub = DAG.getNode(ISD::SUB, MVT::f64, Load, Bias);





From lattner at cs.uiuc.edu  Wed Aug 17 12:08:36 2005
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Wed, 17 Aug 2005 12:08:36 -0500
Subject: [llvm-commits] CVS: llvm/lib/Target/Alpha/AlphaISelPattern.cpp 
Message-ID: <200508171708.MAA05866@zion.cs.uiuc.edu>



Changes in directory llvm/lib/Target/Alpha:

AlphaISelPattern.cpp updated: 1.164 -> 1.165
---
Log message:

Fix some bugs in the alpha backend, some of which I introduced yesterday,
and some that were preexisting.  All alpha regtests pass now.


---
Diffs of the changes:  (+3 -2)

 AlphaISelPattern.cpp |    5 +++--
 1 files changed, 3 insertions(+), 2 deletions(-)


Index: llvm/lib/Target/Alpha/AlphaISelPattern.cpp
diff -u llvm/lib/Target/Alpha/AlphaISelPattern.cpp:1.164 llvm/lib/Target/Alpha/AlphaISelPattern.cpp:1.165
--- llvm/lib/Target/Alpha/AlphaISelPattern.cpp:1.164	Tue Aug 16 19:47:24 2005
+++ llvm/lib/Target/Alpha/AlphaISelPattern.cpp	Wed Aug 17 12:08:24 2005
@@ -284,6 +284,7 @@
       case MVT::f32:
         args_float[count] = AddLiveIn(MF,args_float[count], getRegClassFor(VT));
         argt = DAG.getCopyFromReg(DAG.getRoot(), args_float[count], VT);
+        DAG.setRoot(argt.getValue(1));
         break;
       case MVT::i1:
       case MVT::i8:
@@ -292,12 +293,12 @@
       case MVT::i64:
         args_int[count] = AddLiveIn(MF, args_int[count],
                                     getRegClassFor(MVT::i64));
-        argt = DAG.getCopyFromReg(DAG.getRoot(), args_int[count], VT);
+        argt = DAG.getCopyFromReg(DAG.getRoot(), args_int[count], MVT::i64);
+        DAG.setRoot(argt.getValue(1));
         if (VT != MVT::i64)
           argt = DAG.getNode(ISD::TRUNCATE, VT, argt);
         break;
       }
-      DAG.setRoot(argt.getValue(1));
     } else { //more args
       // Create the frame index object for this incoming parameter...
       int FI = MFI->CreateFixedObject(8, 8 * (count - 6));





From jlaskey at apple.com  Wed Aug 17 12:28:00 2005
From: jlaskey at apple.com (Jim Laskey)
Date: Wed, 17 Aug 2005 12:28:00 -0500
Subject: [llvm-commits] CVS: llvm/include/llvm/Support/MathExtras.h 
Message-ID: <200508171728.MAA08704@zion.cs.uiuc.edu>



Changes in directory llvm/include/llvm/Support:

MathExtras.h updated: 1.23 -> 1.24
---
Log message:

Added support for converting raw bits to FP, and FP to raw bits.  The intent
is to avoid the distraction of the union declarations.



---
Diffs of the changes:  (+44 -0)

 MathExtras.h |   44 ++++++++++++++++++++++++++++++++++++++++++++
 1 files changed, 44 insertions(+)


Index: llvm/include/llvm/Support/MathExtras.h
diff -u llvm/include/llvm/Support/MathExtras.h:1.23 llvm/include/llvm/Support/MathExtras.h:1.24
--- llvm/include/llvm/Support/MathExtras.h:1.23	Wed Aug  3 15:53:19 2005
+++ llvm/include/llvm/Support/MathExtras.h	Wed Aug 17 12:27:47 2005
@@ -168,6 +168,50 @@
     return 63 - CountLeadingZeros_64(Value);
 }
 
+// BitsToDouble - This function takes a 64-bit integer and returns the bit
+// equivalent double.
+inline double BitsToDouble(uint64_t Bits) {
+  union {
+    uint64_t L;
+    double D;
+  } T;
+  T.L = Bits;
+  return T.D;
+}
+
+// BitsToFloat - This function takes a 32-bit integer and returns the bit
+// equivalent float.
+inline float BitsToFloat(unsigned Bits) {
+  union {
+    unsigned I;
+    float F;
+  } T;
+  T.I = Bits;
+  return T.F;
+}
+
+// DoubleToBits - This function takes a double and returns the bit
+// equivalent 64-bit integer.
+inline uint64_t DoubleToBits(double Double) {
+  union {
+    uint64_t L;
+    double D;
+  } T;
+  T.D = Double;
+  return T.L;
+}
+
+// FloatToBits - This function takes a float and returns the bit
+// equivalent 32-bit integer.
+inline unsigned FloatToBits(float Float) {
+  union {
+    unsigned I;
+    float F;
+  } T;
+  T.F = Float;
+  return T.I;
+}
+
 // Platform-independent wrappers for the C99 isnan() function.
 int IsNAN (float f);
 int IsNAN (double d);





From jlaskey at apple.com  Wed Aug 17 12:43:03 2005
From: jlaskey at apple.com (Jim Laskey)
Date: Wed, 17 Aug 2005 12:43:03 -0500
Subject: [llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp 
Message-ID: <200508171743.MAA09382@zion.cs.uiuc.edu>



Changes in directory llvm/lib/CodeGen/SelectionDAG:

LegalizeDAG.cpp updated: 1.165 -> 1.166
---
Log message:

Switched to using BitsToDouble for int_to_float to avoid aliasing problem.



---
Diffs of the changes:  (+4 -4)

 LegalizeDAG.cpp |    8 ++++----
 1 files changed, 4 insertions(+), 4 deletions(-)


Index: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.165 llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.166
--- llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.165	Wed Aug 17 04:44:59 2005
+++ llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp	Wed Aug 17 12:42:52 2005
@@ -15,6 +15,7 @@
 #include "llvm/CodeGen/MachineConstantPool.h"
 #include "llvm/CodeGen/MachineFunction.h"
 #include "llvm/CodeGen/MachineFrameInfo.h"
+#include "llvm/Support/MathExtras.h"
 #include "llvm/Target/TargetLowering.h"
 #include "llvm/Target/TargetData.h"
 #include "llvm/Target/TargetOptions.h"
@@ -204,10 +205,9 @@
     SDOperand Load = DAG.getLoad(MVT::f64, Store2, StackSlot,
                                DAG.getSrcValue(NULL));
     // FP constant to bias correct the final result
-    uint64_t   SignedBias = 0x4330000080000000ULL;
-    uint64_t UnsignedBias = 0x4330000000000000ULL;
-    SDOperand Bias = DAG.getConstantFP(isSigned ? *(double *)&SignedBias
-                                                : *(double *)&UnsignedBias,
+    SDOperand Bias = DAG.getConstantFP(isSigned ?
+                                            BitsToDouble(0x4330000080000000ULL)
+                                          : BitsToDouble(0x4330000000000000ULL),
                                      MVT::f64);
     // subtract the bias
     SDOperand Sub = DAG.getNode(ISD::SUB, MVT::f64, Load, Bias);





From lattner at cs.uiuc.edu  Wed Aug 17 13:58:52 2005
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Wed, 17 Aug 2005 13:58:52 -0500
Subject: [llvm-commits] CVS: llvm/include/llvm/CodeGen/SelectionDAGNodes.h 
Message-ID: <200508171858.NAA10003@zion.cs.uiuc.edu>



Changes in directory llvm/include/llvm/CodeGen:

SelectionDAGNodes.h updated: 1.53 -> 1.54
---
Log message:

Make removeUser more efficient, add a matching addUser.
Fix the setOperands methods I added to update use/def information correctly.


---
Diffs of the changes:  (+10 -2)

 SelectionDAGNodes.h |   12 ++++++++++--
 1 files changed, 10 insertions(+), 2 deletions(-)


Index: llvm/include/llvm/CodeGen/SelectionDAGNodes.h
diff -u llvm/include/llvm/CodeGen/SelectionDAGNodes.h:1.53 llvm/include/llvm/CodeGen/SelectionDAGNodes.h:1.54
--- llvm/include/llvm/CodeGen/SelectionDAGNodes.h:1.53	Tue Aug 16 20:54:00 2005
+++ llvm/include/llvm/CodeGen/SelectionDAGNodes.h	Wed Aug 17 13:58:38 2005
@@ -641,25 +641,33 @@
   void setOperands(SDOperand Op0) {
     Operands.reserve(1);
     Operands.push_back(Op0);
+    Op0.Val->Uses.push_back(this);
   }
   void setOperands(SDOperand Op0, SDOperand Op1) {
     Operands.reserve(2);
     Operands.push_back(Op0);
     Operands.push_back(Op1);
+    Op0.Val->Uses.push_back(this); Op1.Val->Uses.push_back(this);
   }
   void setOperands(SDOperand Op0, SDOperand Op1, SDOperand Op2) {
     Operands.reserve(3);
     Operands.push_back(Op0);
     Operands.push_back(Op1);
     Operands.push_back(Op2);
+    Op0.Val->Uses.push_back(this); Op1.Val->Uses.push_back(this);
+    Op2.Val->Uses.push_back(this);
+  }
+  void addUser(SDNode *User) {
+    Uses.push_back(User);
   }
   void removeUser(SDNode *User) {
     // Remove this user from the operand's use list.
     for (unsigned i = Uses.size(); ; --i) {
       assert(i != 0 && "Didn't find user!");
       if (Uses[i-1] == User) {
-        Uses.erase(Uses.begin()+i-1);
-        break;
+        Uses[i-1] = Uses.back();
+        Uses.pop_back();
+        return;
       }
     }
   }





From lattner at cs.uiuc.edu  Wed Aug 17 13:59:29 2005
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Wed, 17 Aug 2005 13:59:29 -0500
Subject: [llvm-commits] CVS: llvm/include/llvm/CodeGen/SelectionDAG.h 
Message-ID: <200508171859.NAA10062@zion.cs.uiuc.edu>



Changes in directory llvm/include/llvm/CodeGen:

SelectionDAG.h updated: 1.40 -> 1.41
---
Log message:

add ReplaceAllUsesWith, and a helper to implemented it


---
Diffs of the changes:  (+7 -0)

 SelectionDAG.h |    7 +++++++
 1 files changed, 7 insertions(+)


Index: llvm/include/llvm/CodeGen/SelectionDAG.h
diff -u llvm/include/llvm/CodeGen/SelectionDAG.h:1.40 llvm/include/llvm/CodeGen/SelectionDAG.h:1.41
--- llvm/include/llvm/CodeGen/SelectionDAG.h:1.40	Tue Aug 16 19:33:30 2005
+++ llvm/include/llvm/CodeGen/SelectionDAG.h	Wed Aug 17 13:59:17 2005
@@ -239,10 +239,17 @@
                           SDOperand Op1, SDOperand Op2, SDOperand Op3) {
     return getNode(ISD::BUILTIN_OP_END+Opcode, VT, Op1, Op2, Op3);
   }
+  
+  /// ReplaceAllUsesWith - Modify anything using 'From' to use 'To' instead.
+  /// This can cause recursive merging of nodes in the DAG.
+  ///
+  void ReplaceAllUsesWith(SDNode *From, SDNode *To);
+  
   void dump() const;
 
 private:
   void RemoveNodeFromCSEMaps(SDNode *N);
+  SDNode *AddNonLeafNodeToCSEMaps(SDNode *N);
   void DeleteNodeIfDead(SDNode *N, void *NodeSet);
   
   /// SimplifySetCC - Try to simplify a setcc built with the specified operands 





From lattner at cs.uiuc.edu  Wed Aug 17 14:00:31 2005
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Wed, 17 Aug 2005 14:00:31 -0500
Subject: [llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp 
Message-ID: <200508171900.OAA10150@zion.cs.uiuc.edu>



Changes in directory llvm/lib/CodeGen/SelectionDAG:

SelectionDAG.cpp updated: 1.144 -> 1.145
---
Log message:

Fix a bug in RemoveDeadNodes where it would crash when its "optional"
argument is not specified.

Implement ReplaceAllUsesWith.


---
Diffs of the changes:  (+77 -1)

 SelectionDAG.cpp |   78 ++++++++++++++++++++++++++++++++++++++++++++++++++++++-
 1 files changed, 77 insertions(+), 1 deletion(-)


Index: llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp:1.144 llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp:1.145
--- llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp:1.144	Tue Aug 16 19:34:06 2005
+++ llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp	Wed Aug 17 14:00:20 2005
@@ -152,7 +152,8 @@
   // to the root node, preventing it from being deleted.
   SDNode *DummyNode = new SDNode(ISD::EntryToken, getRoot());
 
-  DeleteNodeIfDead(N, &AllNodeSet);
+  // If we have a hint to start from, use it.
+  if (N) DeleteNodeIfDead(N, &AllNodeSet);
 
  Restart:
   unsigned NumNodes = AllNodeSet.size();
@@ -292,6 +293,51 @@
   }
 }
 
+/// AddNonLeafNodeToCSEMaps - Add the specified node back to the CSE maps.  It
+/// has been taken out and modified in some way.  If the specified node already
+/// exists in the CSE maps, do not modify the maps, but return the existing node
+/// instead.  If it doesn't exist, add it and return null.
+///
+SDNode *SelectionDAG::AddNonLeafNodeToCSEMaps(SDNode *N) {
+  assert(N->getNumOperands() && "This is a leaf node!");
+  if (N->getOpcode() == ISD::LOAD) {
+    SDNode *&L = Loads[std::make_pair(N->getOperand(1),
+                                      std::make_pair(N->getOperand(0),
+                                                     N->getValueType(0)))];
+    if (L) return L;
+    L = N;
+  } else if (N->getNumOperands() == 1) {
+    SDNode *&U = UnaryOps[std::make_pair(N->getOpcode(),
+                                         std::make_pair(N->getOperand(0),
+                                                        N->getValueType(0)))];
+    if (U) return U;
+    U = N;
+  } else if (N->getNumOperands() == 2) {
+    SDNode *&B = BinaryOps[std::make_pair(N->getOpcode(),
+                                          std::make_pair(N->getOperand(0),
+                                                         N->getOperand(1)))];
+    if (B) return B;
+    B = N;
+  } else if (N->getNumValues() == 1) {
+    std::vector<SDOperand> Ops(N->op_begin(), N->op_end());
+    SDNode *&ORN = OneResultNodes[std::make_pair(N->getOpcode(),
+                                  std::make_pair(N->getValueType(0), Ops))];
+    if (ORN) return ORN;
+    ORN = N;
+  } else {
+    // Remove the node from the ArbitraryNodes map.
+    std::vector<MVT::ValueType> RV(N->value_begin(), N->value_end());
+    std::vector<SDOperand>     Ops(N->op_begin(), N->op_end());
+    SDNode *&AN = ArbitraryNodes[std::make_pair(N->getOpcode(),
+                                                std::make_pair(RV, Ops))];
+    if (AN) return AN;
+    AN = N;
+  }
+  return 0;
+  
+}
+
+
 
 SelectionDAG::~SelectionDAG() {
   for (unsigned i = 0, e = AllNodes.size(); i != e; ++i)
@@ -1758,6 +1804,36 @@
   N->setOperands(Op1, Op2, Op3);
 }
 
+/// ReplaceAllUsesWith - Modify anything using 'From' to use 'To' instead.
+/// This can cause recursive merging of nodes in the DAG.
+///
+void SelectionDAG::ReplaceAllUsesWith(SDNode *From, SDNode *To) {
+  assert(From != To && "Cannot replace uses of with self");
+  while (!From->use_empty()) {
+    // Process users until they are all gone.
+    SDNode *U = *From->use_begin();
+    
+    // This node is about to morph, remove its old self from the CSE maps.
+    RemoveNodeFromCSEMaps(U);
+    
+    for (unsigned i = 0, e = U->getNumOperands(); i != e; ++i)
+      if (U->getOperand(i).Val == From) {
+        assert(From->getValueType(U->getOperand(i).ResNo) ==
+               To->getValueType(U->getOperand(i).ResNo));
+        From->removeUser(U);
+        U->Operands[i].Val = To;
+        To->addUser(U);
+      }
+        
+    // Now that we have modified U, add it back to the CSE maps.  If it already
+    // exists there, recursively merge the results together.
+    if (SDNode *Existing = AddNonLeafNodeToCSEMaps(U))
+      ReplaceAllUsesWith(U, Existing);
+      // U is now dead.
+  }
+}
+
+
 
 /// hasNUsesOfValue - Return true if there are exactly NUSES uses of the
 /// indicated value.  This method ignores uses of other values defined by this





From jlaskey at apple.com  Wed Aug 17 14:19:27 2005
From: jlaskey at apple.com (Jim Laskey)
Date: Wed, 17 Aug 2005 14:19:27 -0500
Subject: [llvm-commits] CVS: llvm/include/llvm/Constants.h 
Message-ID: <200508171919.OAA10624@zion.cs.uiuc.edu>



Changes in directory llvm/include/llvm:

Constants.h updated: 1.70 -> 1.71
---
Log message:

Culling out use of unions for converting FP to bits and vice versa.



---
Diffs of the changes:  (+3 -17)

 Constants.h |   20 +++-----------------
 1 files changed, 3 insertions(+), 17 deletions(-)


Index: llvm/include/llvm/Constants.h
diff -u llvm/include/llvm/Constants.h:1.70 llvm/include/llvm/Constants.h:1.71
--- llvm/include/llvm/Constants.h:1.70	Thu Apr 21 15:11:51 2005
+++ llvm/include/llvm/Constants.h	Wed Aug 17 14:19:16 2005
@@ -23,6 +23,7 @@
 #include "llvm/Constant.h"
 #include "llvm/Type.h"
 #include "llvm/Support/DataTypes.h"
+#include "llvm/Support/MathExtras.h"
 
 namespace llvm {
 
@@ -277,12 +278,7 @@
   /// getNullValue.  Don't depend on == for doubles to tell us it's zero, it
   /// considers -0.0 to be null as well as 0.0.  :(
   virtual bool isNullValue() const {
-    union {
-      double V;
-      uint64_t I;
-    } T;
-    T.V = Val;
-    return T.I == 0;
+    return DoubleToBits(Val) == 0;
   }
 
   /// isExactlyValue - We don't rely on operator== working on double values, as
@@ -290,17 +286,7 @@
   /// As such, this method can be used to do an exact bit-for-bit comparison of
   /// two floating point values.
   bool isExactlyValue(double V) const {
-    union {
-      double V;
-      uint64_t I;
-    } T1;
-    T1.V = Val;
-    union {
-      double V;
-      uint64_t I;
-    } T2;
-    T2.V = V;
-    return T1.I == T2.I;
+    return DoubleToBits(V) == DoubleToBits(Val);
   }
 
   /// Methods for support type inquiry through isa, cast, and dyn_cast:





From jlaskey at apple.com  Wed Aug 17 14:20:54 2005
From: jlaskey at apple.com (Jim Laskey)
Date: Wed, 17 Aug 2005 14:20:54 -0500
Subject: [llvm-commits] CVS: llvm/include/llvm/CodeGen/SelectionDAGNodes.h 
Message-ID: <200508171920.OAA10644@zion.cs.uiuc.edu>



Changes in directory llvm/include/llvm/CodeGen:

SelectionDAGNodes.h updated: 1.54 -> 1.55
---
Log message:

Culling out use of unions for converting FP to bits and vice versa.



---
Diffs of the changes:  (+2 -11)

 SelectionDAGNodes.h |   13 ++-----------
 1 files changed, 2 insertions(+), 11 deletions(-)


Index: llvm/include/llvm/CodeGen/SelectionDAGNodes.h
diff -u llvm/include/llvm/CodeGen/SelectionDAGNodes.h:1.54 llvm/include/llvm/CodeGen/SelectionDAGNodes.h:1.55
--- llvm/include/llvm/CodeGen/SelectionDAGNodes.h:1.54	Wed Aug 17 13:58:38 2005
+++ llvm/include/llvm/CodeGen/SelectionDAGNodes.h	Wed Aug 17 14:20:43 2005
@@ -25,6 +25,7 @@
 #include "llvm/ADT/GraphTraits.h"
 #include "llvm/ADT/iterator"
 #include "llvm/Support/DataTypes.h"
+#include "llvm/Support/MathExtras.h"
 #include <cassert>
 #include <vector>
 
@@ -742,17 +743,7 @@
   /// As such, this method can be used to do an exact bit-for-bit comparison of
   /// two floating point values.
   bool isExactlyValue(double V) const {
-    union {
-      double V;
-      uint64_t I;
-    } T1;
-    T1.V = Value;
-    union {
-      double V;
-      uint64_t I;
-    } T2;
-    T2.V = V;
-    return T1.I == T2.I;
+    return DoubleToBits(V) == DoubleToBits(Value);
   }
 
   static bool classof(const ConstantFPSDNode *) { return true; }





From jlaskey at apple.com  Wed Aug 17 14:22:16 2005
From: jlaskey at apple.com (Jim Laskey)
Date: Wed, 17 Aug 2005 14:22:16 -0500
Subject: [llvm-commits] CVS: llvm/lib/Bytecode/Reader/Reader.cpp 
Message-ID: <200508171922.OAA10657@zion.cs.uiuc.edu>



Changes in directory llvm/lib/Bytecode/Reader:

Reader.cpp updated: 1.165 -> 1.166
---
Log message:

Culling out use of unions for converting FP to bits and vice versa.




---
Diffs of the changes:  (+6 -15)

 Reader.cpp |   21 ++++++---------------
 1 files changed, 6 insertions(+), 15 deletions(-)


Index: llvm/lib/Bytecode/Reader/Reader.cpp
diff -u llvm/lib/Bytecode/Reader/Reader.cpp:1.165 llvm/lib/Bytecode/Reader/Reader.cpp:1.166
--- llvm/lib/Bytecode/Reader/Reader.cpp:1.165	Wed Jul 27 01:12:33 2005
+++ llvm/lib/Bytecode/Reader/Reader.cpp	Wed Aug 17 14:22:05 2005
@@ -27,6 +27,7 @@
 #include "llvm/Config/alloca.h"
 #include "llvm/Support/GetElementPtrTypeIterator.h"
 #include "llvm/Support/Compressor.h"
+#include "llvm/Support/MathExtras.h"
 #include "llvm/ADT/StringExtras.h"
 #include <sstream>
 #include <algorithm>
@@ -162,29 +163,19 @@
 inline void BytecodeReader::read_float(float& FloatVal) {
   /// FIXME: This isn't optimal, it has size problems on some platforms
   /// where FP is not IEEE.
-  union {
-    float f;
-    uint32_t i;
-  } FloatUnion;
-  FloatUnion.i = At[0] | (At[1] << 8) | (At[2] << 16) | (At[3] << 24);
+  FloatVal = BitsToFloat(At[0] | (At[1] << 8) | (At[2] << 16) | (At[3] << 24));
   At+=sizeof(uint32_t);
-  FloatVal = FloatUnion.f;
 }
 
 /// Read a double value in little-endian order
 inline void BytecodeReader::read_double(double& DoubleVal) {
   /// FIXME: This isn't optimal, it has size problems on some platforms
   /// where FP is not IEEE.
-  union {
-    double d;
-    uint64_t i;
-  } DoubleUnion;
-  DoubleUnion.i = (uint64_t(At[0]) <<  0) | (uint64_t(At[1]) << 8) |
-                  (uint64_t(At[2]) << 16) | (uint64_t(At[3]) << 24) |
-                  (uint64_t(At[4]) << 32) | (uint64_t(At[5]) << 40) |
-                  (uint64_t(At[6]) << 48) | (uint64_t(At[7]) << 56);
+  DoubleVal = BitsToDouble((uint64_t(At[0]) <<  0) | (uint64_t(At[1]) << 8) |
+                           (uint64_t(At[2]) << 16) | (uint64_t(At[3]) << 24) |
+                           (uint64_t(At[4]) << 32) | (uint64_t(At[5]) << 40) |
+                           (uint64_t(At[6]) << 48) | (uint64_t(At[7]) << 56));
   At+=sizeof(uint64_t);
-  DoubleVal = DoubleUnion.d;
 }
 
 /// Read a block header and obtain its type and size





From jlaskey at apple.com  Wed Aug 17 14:23:25 2005
From: jlaskey at apple.com (Jim Laskey)
Date: Wed, 17 Aug 2005 14:23:25 -0500
Subject: [llvm-commits] CVS: llvm/lib/Bytecode/Writer/Writer.cpp 
Message-ID: <200508171923.OAA10669@zion.cs.uiuc.edu>



Changes in directory llvm/lib/Bytecode/Writer:

Writer.cpp updated: 1.107 -> 1.108
---
Log message:

Culling out use of unions for converting FP to bits and vice versa.




---
Diffs of the changes:  (+15 -22)

 Writer.cpp |   37 +++++++++++++++----------------------
 1 files changed, 15 insertions(+), 22 deletions(-)


Index: llvm/lib/Bytecode/Writer/Writer.cpp
diff -u llvm/lib/Bytecode/Writer/Writer.cpp:1.107 llvm/lib/Bytecode/Writer/Writer.cpp:1.108
--- llvm/lib/Bytecode/Writer/Writer.cpp:1.107	Wed Jul 27 01:12:33 2005
+++ llvm/lib/Bytecode/Writer/Writer.cpp	Wed Aug 17 14:23:14 2005
@@ -27,6 +27,7 @@
 #include "llvm/SymbolTable.h"
 #include "llvm/Support/GetElementPtrTypeIterator.h"
 #include "llvm/Support/Compressor.h"
+#include "llvm/Support/MathExtras.h"
 #include "llvm/ADT/STLExtras.h"
 #include "llvm/ADT/Statistic.h"
 #include <cstring>
@@ -139,33 +140,25 @@
 inline void BytecodeWriter::output_float(float& FloatVal) {
   /// FIXME: This isn't optimal, it has size problems on some platforms
   /// where FP is not IEEE.
-  union {
-    float f;
-    uint32_t i;
-  } FloatUnion;
-  FloatUnion.f = FloatVal;
-  Out.push_back( static_cast<unsigned char>( (FloatUnion.i & 0xFF )));
-  Out.push_back( static_cast<unsigned char>( (FloatUnion.i >> 8) & 0xFF));
-  Out.push_back( static_cast<unsigned char>( (FloatUnion.i >> 16) & 0xFF));
-  Out.push_back( static_cast<unsigned char>( (FloatUnion.i >> 24) & 0xFF));
+  uint32_t i = FloatToBits(FloatVal);
+  Out.push_back( static_cast<unsigned char>( (i & 0xFF )));
+  Out.push_back( static_cast<unsigned char>( (i >> 8) & 0xFF));
+  Out.push_back( static_cast<unsigned char>( (i >> 16) & 0xFF));
+  Out.push_back( static_cast<unsigned char>( (i >> 24) & 0xFF));
 }
 
 inline void BytecodeWriter::output_double(double& DoubleVal) {
   /// FIXME: This isn't optimal, it has size problems on some platforms
   /// where FP is not IEEE.
-  union {
-    double d;
-    uint64_t i;
-  } DoubleUnion;
-  DoubleUnion.d = DoubleVal;
-  Out.push_back( static_cast<unsigned char>( (DoubleUnion.i & 0xFF )));
-  Out.push_back( static_cast<unsigned char>( (DoubleUnion.i >> 8) & 0xFF));
-  Out.push_back( static_cast<unsigned char>( (DoubleUnion.i >> 16) & 0xFF));
-  Out.push_back( static_cast<unsigned char>( (DoubleUnion.i >> 24) & 0xFF));
-  Out.push_back( static_cast<unsigned char>( (DoubleUnion.i >> 32) & 0xFF));
-  Out.push_back( static_cast<unsigned char>( (DoubleUnion.i >> 40) & 0xFF));
-  Out.push_back( static_cast<unsigned char>( (DoubleUnion.i >> 48) & 0xFF));
-  Out.push_back( static_cast<unsigned char>( (DoubleUnion.i >> 56) & 0xFF));
+  uint64_t i = DoubleToBits(DoubleVal);
+  Out.push_back( static_cast<unsigned char>( (i & 0xFF )));
+  Out.push_back( static_cast<unsigned char>( (i >> 8) & 0xFF));
+  Out.push_back( static_cast<unsigned char>( (i >> 16) & 0xFF));
+  Out.push_back( static_cast<unsigned char>( (i >> 24) & 0xFF));
+  Out.push_back( static_cast<unsigned char>( (i >> 32) & 0xFF));
+  Out.push_back( static_cast<unsigned char>( (i >> 40) & 0xFF));
+  Out.push_back( static_cast<unsigned char>( (i >> 48) & 0xFF));
+  Out.push_back( static_cast<unsigned char>( (i >> 56) & 0xFF));
 }
 
 inline BytecodeBlock::BytecodeBlock(unsigned ID, BytecodeWriter& w,





From jlaskey at apple.com  Wed Aug 17 14:24:51 2005
From: jlaskey at apple.com (Jim Laskey)
Date: Wed, 17 Aug 2005 14:24:51 -0500
Subject: [llvm-commits] CVS: llvm/lib/CodeGen/AsmPrinter.cpp 
Message-ID: <200508171924.OAA10698@zion.cs.uiuc.edu>



Changes in directory llvm/lib/CodeGen:

AsmPrinter.cpp updated: 1.19 -> 1.20
---
Log message:

Culling out use of unions for converting FP to bits and vice versa.




---
Diffs of the changes:  (+7 -18)

 AsmPrinter.cpp |   25 +++++++------------------
 1 files changed, 7 insertions(+), 18 deletions(-)


Index: llvm/lib/CodeGen/AsmPrinter.cpp
diff -u llvm/lib/CodeGen/AsmPrinter.cpp:1.19 llvm/lib/CodeGen/AsmPrinter.cpp:1.20
--- llvm/lib/CodeGen/AsmPrinter.cpp:1.19	Sun Aug  7 23:26:32 2005
+++ llvm/lib/CodeGen/AsmPrinter.cpp	Wed Aug 17 14:24:40 2005
@@ -15,6 +15,7 @@
 #include "llvm/Constants.h"
 #include "llvm/Instruction.h"
 #include "llvm/Support/Mangler.h"
+#include "llvm/Support/MathExtras.h"
 #include "llvm/Target/TargetMachine.h"
 using namespace llvm;
 
@@ -222,39 +223,27 @@
     // precision...
     double Val = CFP->getValue();
     if (CFP->getType() == Type::DoubleTy) {
-      union DU {                            // Abide by C TBAA rules
-        double FVal;
-        uint64_t UVal;
-      } U;
-      U.FVal = Val;
-
       if (Data64bitsDirective)
-        O << Data64bitsDirective << U.UVal << "\t" << CommentString
+        O << Data64bitsDirective << DoubleToBits(Val) << "\t" << CommentString
           << " double value: " << Val << "\n";
       else if (TD.isBigEndian()) {
-        O << Data32bitsDirective << unsigned(U.UVal >> 32)
+        O << Data32bitsDirective << unsigned(DoubleToBits(Val) >> 32)
           << "\t" << CommentString << " double most significant word "
           << Val << "\n";
-        O << Data32bitsDirective << unsigned(U.UVal)
+        O << Data32bitsDirective << unsigned(DoubleToBits(Val))
           << "\t" << CommentString << " double least significant word "
           << Val << "\n";
       } else {
-        O << Data32bitsDirective << unsigned(U.UVal)
+        O << Data32bitsDirective << unsigned(DoubleToBits(Val))
           << "\t" << CommentString << " double least significant word " << Val
           << "\n";
-        O << Data32bitsDirective << unsigned(U.UVal >> 32)
+        O << Data32bitsDirective << unsigned(DoubleToBits(Val) >> 32)
           << "\t" << CommentString << " double most significant word " << Val
           << "\n";
       }
       return;
     } else {
-      union FU {                            // Abide by C TBAA rules
-        float FVal;
-        int32_t UVal;
-      } U;
-      U.FVal = (float)Val;
-
-      O << Data32bitsDirective << U.UVal << "\t" << CommentString
+      O << Data32bitsDirective << FloatToBits(Val) << "\t" << CommentString
         << " float " << Val << "\n";
       return;
     }





From jlaskey at apple.com  Wed Aug 17 14:27:34 2005
From: jlaskey at apple.com (Jim Laskey)
Date: Wed, 17 Aug 2005 14:27:34 -0500
Subject: [llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp 
Message-ID: <200508171927.OAA10719@zion.cs.uiuc.edu>



Changes in directory llvm/lib/CodeGen/SelectionDAG:

LegalizeDAG.cpp updated: 1.166 -> 1.167
---
Log message:

Culling out use of unions for converting FP to bits and vice versa.




---
Diffs of the changes:  (+6 -12)

 LegalizeDAG.cpp |   18 ++++++------------
 1 files changed, 6 insertions(+), 12 deletions(-)


Index: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.166 llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.167
--- llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.166	Wed Aug 17 12:42:52 2005
+++ llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp	Wed Aug 17 14:27:23 2005
@@ -975,23 +975,17 @@
     // Turn 'store float 1.0, Ptr' -> 'store int 0x12345678, Ptr'
     if (ConstantFPSDNode *CFP =dyn_cast<ConstantFPSDNode>(Node->getOperand(1))){
       if (CFP->getValueType(0) == MVT::f32) {
-        union {
-          unsigned I;
-          float    F;
-        } V;
-        V.F = CFP->getValue();
         Result = DAG.getNode(ISD::STORE, MVT::Other, Tmp1,
-                             DAG.getConstant(V.I, MVT::i32), Tmp2,
+                             DAG.getConstant(FloatToBits(CFP->getValue()),
+                                             MVT::i32),
+                             Tmp2,
                              Node->getOperand(3));
       } else {
         assert(CFP->getValueType(0) == MVT::f64 && "Unknown FP type!");
-        union {
-          uint64_t I;
-          double   F;
-        } V;
-        V.F = CFP->getValue();
         Result = DAG.getNode(ISD::STORE, MVT::Other, Tmp1,
-                             DAG.getConstant(V.I, MVT::i64), Tmp2,
+                             DAG.getConstant(DoubleToBits(CFP->getValue()),
+                                             MVT::i64),
+                             Tmp2,
                              Node->getOperand(3));
       }
       Node = Result.Val;





From jlaskey at apple.com  Wed Aug 17 14:28:38 2005
From: jlaskey at apple.com (Jim Laskey)
Date: Wed, 17 Aug 2005 14:28:38 -0500
Subject: [llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp 
Message-ID: <200508171928.OAA10737@zion.cs.uiuc.edu>



Changes in directory llvm/lib/CodeGen/SelectionDAG:

SelectionDAG.cpp updated: 1.145 -> 1.146
---
Log message:

Culling out use of unions for converting FP to bits and vice versa.


 


---
Diffs of the changes:  (+3 -14)

 SelectionDAG.cpp |   17 +++--------------
 1 files changed, 3 insertions(+), 14 deletions(-)


Index: llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp:1.145 llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp:1.146
--- llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp:1.145	Wed Aug 17 14:00:20 2005
+++ llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp	Wed Aug 17 14:28:27 2005
@@ -224,12 +224,8 @@
                                          N->getValueType(0)));
     break;
   case ISD::ConstantFP: {
-    union {
-      double DV;
-      uint64_t IV;
-    };
-    DV = cast<ConstantFPSDNode>(N)->getValue();
-    ConstantFPs.erase(std::make_pair(IV, N->getValueType(0)));
+    uint64_t V = DoubleToBits(cast<ConstantFPSDNode>(N)->getValue());
+    ConstantFPs.erase(std::make_pair(V, N->getValueType(0)));
     break;
   }
   case ISD::CONDCODE:
@@ -385,14 +381,7 @@
   // Do the map lookup using the actual bit pattern for the floating point
   // value, so that we don't have problems with 0.0 comparing equal to -0.0, and
   // we don't have issues with SNANs.
-  union {
-    double DV;
-    uint64_t IV;
-  };
-
-  DV = Val;
-
-  SDNode *&N = ConstantFPs[std::make_pair(IV, VT)];
+  SDNode *&N = ConstantFPs[std::make_pair(DoubleToBits(Val), VT)];
   if (N) return SDOperand(N, 0);
   N = new ConstantFPSDNode(Val, VT);
   AllNodes.push_back(N);





From jlaskey at apple.com  Wed Aug 17 14:30:56 2005
From: jlaskey at apple.com (Jim Laskey)
Date: Wed, 17 Aug 2005 14:30:56 -0500
Subject: [llvm-commits] CVS: llvm/lib/Target/CBackend/Writer.cpp 
Message-ID: <200508171930.OAA10811@zion.cs.uiuc.edu>



Changes in directory llvm/lib/Target/CBackend:

Writer.cpp updated: 1.242 -> 1.243
---
Log message:

Culling out use of unions for converting FP to bits and vice versa.


 


---
Diffs of the changes:  (+5 -20)

 Writer.cpp |   25 +++++--------------------
 1 files changed, 5 insertions(+), 20 deletions(-)


Index: llvm/lib/Target/CBackend/Writer.cpp
diff -u llvm/lib/Target/CBackend/Writer.cpp:1.242 llvm/lib/Target/CBackend/Writer.cpp:1.243
--- llvm/lib/Target/CBackend/Writer.cpp:1.242	Thu Jul 14 14:41:16 2005
+++ llvm/lib/Target/CBackend/Writer.cpp	Wed Aug 17 14:30:44 2005
@@ -32,6 +32,7 @@
 #include "llvm/Support/GetElementPtrTypeIterator.h"
 #include "llvm/Support/InstVisitor.h"
 #include "llvm/Support/Mangler.h"
+#include "llvm/Support/MathExtras.h"
 #include "llvm/ADT/StringExtras.h"
 #include "llvm/ADT/STLExtras.h"
 #include "llvm/Support/MathExtras.h"
@@ -585,14 +586,10 @@
         const unsigned long SignalNaN = 0x7ff4UL;
 
         // We need to grab the first part of the FP #
-        union {
-          double   d;
-          uint64_t ll;
-        } DHex;
         char Buffer[100];
 
-        DHex.d = FPC->getValue();
-        sprintf(Buffer, "0x%llx", (unsigned long long)DHex.ll);
+        uint64_t ll = DoubleToBits(FPC->getValue());
+        sprintf(Buffer, "0x%llx", (unsigned long long)ll);
 
         std::string Num(&Buffer[0], &Buffer[6]);
         unsigned long Val = strtoul(Num.c_str(), 0, 16);
@@ -953,16 +950,6 @@
 
 /// Output all floating point constants that cannot be printed accurately...
 void CWriter::printFloatingPointConstants(Function &F) {
-  union {
-    double D;
-    uint64_t U;
-  } DBLUnion;
-
-  union {
-    float F;
-    unsigned U;
-  } FLTUnion;
-
   // Scan the module for floating point constants.  If any FP constant is used
   // in the function, we want to redirect it here so that we do not depend on
   // the precision of the printed form, unless the printed form preserves
@@ -979,14 +966,12 @@
         FPConstantMap[FPC] = FPCounter;  // Number the FP constants
 
         if (FPC->getType() == Type::DoubleTy) {
-          DBLUnion.D = Val;
           Out << "static const ConstantDoubleTy FPConstant" << FPCounter++
-              << " = 0x" << std::hex << DBLUnion.U << std::dec
+              << " = 0x" << std::hex << DoubleToBits(Val) << std::dec
               << "ULL;    /* " << Val << " */\n";
         } else if (FPC->getType() == Type::FloatTy) {
-          FLTUnion.F = Val;
           Out << "static const ConstantFloatTy FPConstant" << FPCounter++
-              << " = 0x" << std::hex << FLTUnion.U << std::dec
+              << " = 0x" << std::hex << FloatToBits(Val) << std::dec
               << "U;    /* " << Val << " */\n";
         } else
           assert(0 && "Unknown float type!");





From lattner at cs.uiuc.edu  Wed Aug 17 14:32:14 2005
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Wed, 17 Aug 2005 14:32:14 -0500
Subject: [llvm-commits] CVS: llvm/lib/Target/PowerPC/PowerPC.h 
Message-ID: <200508171932.OAA10899@zion.cs.uiuc.edu>



Changes in directory llvm/lib/Target/PowerPC:

PowerPC.h updated: 1.19 -> 1.20
---
Log message:

add prototype, remove dead proto


---
Diffs of the changes:  (+1 -1)

 PowerPC.h |    2 +-
 1 files changed, 1 insertion(+), 1 deletion(-)


Index: llvm/lib/Target/PowerPC/PowerPC.h
diff -u llvm/lib/Target/PowerPC/PowerPC.h:1.19 llvm/lib/Target/PowerPC/PowerPC.h:1.20
--- llvm/lib/Target/PowerPC/PowerPC.h:1.19	Fri Aug  5 17:05:03 2005
+++ llvm/lib/Target/PowerPC/PowerPC.h	Wed Aug 17 14:32:03 2005
@@ -29,7 +29,7 @@
 FunctionPass *createPPCBranchSelectionPass();
 FunctionPass *createPPC32ISelSimple(TargetMachine &TM);
 FunctionPass *createPPC32ISelPattern(TargetMachine &TM);
-FunctionPass *createPPC64ISelPattern(TargetMachine &TM);
+FunctionPass *createPPC32ISelDag(TargetMachine &TM);
 FunctionPass *createDarwinAsmPrinter(std::ostream &OS, TargetMachine &TM);
 FunctionPass *createAIXAsmPrinter(std::ostream &OS, TargetMachine &TM);
 





From jlaskey at apple.com  Wed Aug 17 14:33:06 2005
From: jlaskey at apple.com (Jim Laskey)
Date: Wed, 17 Aug 2005 14:33:06 -0500
Subject: [llvm-commits] CVS: llvm/lib/Target/SparcV8/SparcV8AsmPrinter.cpp 
Message-ID: <200508171933.OAA10974@zion.cs.uiuc.edu>



Changes in directory llvm/lib/Target/SparcV8:

SparcV8AsmPrinter.cpp updated: 1.33 -> 1.34
---
Log message:

Culling out use of unions for converting FP to bits and vice versa.


 
 


---
Diffs of the changes:  (+3 -13)

 SparcV8AsmPrinter.cpp |   16 +++-------------
 1 files changed, 3 insertions(+), 13 deletions(-)


Index: llvm/lib/Target/SparcV8/SparcV8AsmPrinter.cpp
diff -u llvm/lib/Target/SparcV8/SparcV8AsmPrinter.cpp:1.33 llvm/lib/Target/SparcV8/SparcV8AsmPrinter.cpp:1.34
--- llvm/lib/Target/SparcV8/SparcV8AsmPrinter.cpp:1.33	Fri Apr 22 13:06:01 2005
+++ llvm/lib/Target/SparcV8/SparcV8AsmPrinter.cpp	Wed Aug 17 14:32:54 2005
@@ -247,22 +247,12 @@
     switch (CFP->getType()->getTypeID()) {
     default: assert(0 && "Unknown floating point type!");
     case Type::FloatTyID: {
-      union FU {                            // Abide by C TBAA rules
-        float FVal;
-        unsigned UVal;
-      } U;
-      U.FVal = Val;
-      O << ".long\t" << U.UVal << "\t! float " << Val << "\n";
+      O << ".long\t" << FloatToBits(Val) << "\t! float " << Val << "\n";
       return;
     }
     case Type::DoubleTyID: {
-      union DU {                            // Abide by C TBAA rules
-        double FVal;
-        uint64_t UVal;
-      } U;
-      U.FVal = Val;
-      O << ".word\t0x" << std::hex << (U.UVal >> 32) << std::dec << "\t! double " << Val << "\n";
-      O << ".word\t0x" << std::hex << (U.UVal & 0xffffffffUL) << std::dec << "\t! double " << Val << "\n";
+      O << ".word\t0x" << std::hex << (DoubleToBits(Val) >> 32) << std::dec << "\t! double " << Val << "\n";
+      O << ".word\t0x" << std::hex << (DoubleToBits(Val) & 0xffffffffUL) << std::dec << "\t! double " << Val << "\n";
       return;
     }
     }





From lattner at cs.uiuc.edu  Wed Aug 17 14:33:14 2005
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Wed, 17 Aug 2005 14:33:14 -0500
Subject: [llvm-commits] CVS: llvm/lib/Target/PowerPC/PPC32ISelDAGToDAG.cpp 
Message-ID: <200508171933.OAA10985@zion.cs.uiuc.edu>



Changes in directory llvm/lib/Target/PowerPC:

PPC32ISelDAGToDAG.cpp added (r1.1)
---
Log message:

initial hack at a dag->dag instruction selector.  This is obviously woefully
incomplete, but it is a start.  It handles basic argument/retval stuff, immediates,
add and sub.


---
Diffs of the changes:  (+325 -0)

 PPC32ISelDAGToDAG.cpp |  325 ++++++++++++++++++++++++++++++++++++++++++++++++++
 1 files changed, 325 insertions(+)


Index: llvm/lib/Target/PowerPC/PPC32ISelDAGToDAG.cpp
diff -c /dev/null llvm/lib/Target/PowerPC/PPC32ISelDAGToDAG.cpp:1.1
*** /dev/null	Wed Aug 17 14:33:13 2005
--- llvm/lib/Target/PowerPC/PPC32ISelDAGToDAG.cpp	Wed Aug 17 14:33:03 2005
***************
*** 0 ****
--- 1,325 ----
+ //===-- PPC32ISelDAGToDAG.cpp - PPC32 pattern matching inst selector ------===//
+ //
+ //                     The LLVM Compiler Infrastructure
+ //
+ // This file was developed by Chris Lattner and is distributed under
+ // the University of Illinois Open Source License. See LICENSE.TXT for details.
+ //
+ //===----------------------------------------------------------------------===//
+ //
+ // This file defines a pattern matching instruction selector for 32 bit PowerPC,
+ // converting from a legalized dag to a PPC dag.
+ //
+ //===----------------------------------------------------------------------===//
+ 
+ #include "PowerPC.h"
+ #include "PPC32TargetMachine.h"
+ #include "PPC32ISelLowering.h"
+ #include "llvm/CodeGen/SelectionDAG.h"
+ #include "llvm/CodeGen/SelectionDAGISel.h"
+ #include "llvm/Target/TargetOptions.h"
+ #include "llvm/ADT/Statistic.h"
+ #include "llvm/Support/Debug.h"
+ #include "llvm/Support/MathExtras.h"
+ using namespace llvm;
+ 
+ namespace {
+   Statistic<> Recorded("ppc-codegen", "Number of recording ops emitted");
+   Statistic<> FusedFP ("ppc-codegen", "Number of fused fp operations");
+   Statistic<> FrameOff("ppc-codegen", "Number of frame idx offsets collapsed");
+     
+   //===--------------------------------------------------------------------===//
+   /// PPC32DAGToDAGISel - PPC32 specific code to select PPC32 machine
+   /// instructions for SelectionDAG operations.
+   ///
+   class PPC32DAGToDAGISel : public SelectionDAGISel {
+     PPC32TargetLowering PPC32Lowering;
+     
+     unsigned GlobalBaseReg;
+     bool GlobalBaseInitialized;
+   public:
+     PPC32DAGToDAGISel(TargetMachine &TM)
+       : SelectionDAGISel(PPC32Lowering), PPC32Lowering(TM) {}
+     
+     /// runOnFunction - Override this function in order to reset our
+     /// per-function variables.
+     virtual bool runOnFunction(Function &Fn) {
+       // Make sure we re-emit a set of the global base reg if necessary
+       GlobalBaseInitialized = false;
+       return SelectionDAGISel::runOnFunction(Fn);
+     }
+     
+     /// getI32Imm - Return a target constant with the specified value, of type
+     /// i32.
+     inline SDOperand getI32Imm(unsigned Imm) {
+       return CurDAG->getTargetConstant(Imm, MVT::i32);
+     }
+     
+     // Select - Convert the specified operand from a target-independent to a
+     // target-specific node if it hasn't already been changed.
+     SDOperand Select(SDOperand Op);
+     
+     SDNode *SelectIntImmediateExpr(SDOperand LHS, SDOperand RHS,
+                                    unsigned OCHi, unsigned OCLo,
+                                    bool IsArithmetic = false,
+                                    bool Negate = false);
+    
+     /// InstructionSelectBasicBlock - This callback is invoked by
+     /// SelectionDAGISel when it has created a SelectionDAG for us to codegen.
+     virtual void InstructionSelectBasicBlock(SelectionDAG &DAG) {
+       DEBUG(BB->dump());
+       // Codegen the basic block.
+       Select(DAG.getRoot());
+       DAG.RemoveDeadNodes();
+       DAG.viewGraph();
+     }
+  
+     virtual const char *getPassName() const {
+       return "PowerPC DAG->DAG Pattern Instruction Selection";
+     } 
+   };
+ }
+ 
+ // Immediate constant composers.
+ // Lo16 - grabs the lo 16 bits from a 32 bit constant.
+ // Hi16 - grabs the hi 16 bits from a 32 bit constant.
+ // HA16 - computes the hi bits required if the lo bits are add/subtracted in
+ // arithmethically.
+ static unsigned Lo16(unsigned x)  { return x & 0x0000FFFF; }
+ static unsigned Hi16(unsigned x)  { return Lo16(x >> 16); }
+ static unsigned HA16(unsigned x)  { return Hi16((signed)x - (signed short)x); }
+ 
+ // isIntImmediate - This method tests to see if a constant operand.
+ // If so Imm will receive the 32 bit value.
+ static bool isIntImmediate(SDOperand N, unsigned& Imm) {
+   if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N)) {
+     Imm = (unsigned)CN->getSignExtended();
+     return true;
+   }
+   return false;
+ }
+ 
+ // SelectIntImmediateExpr - Choose code for integer operations with an immediate
+ // operand.
+ SDNode *PPC32DAGToDAGISel::SelectIntImmediateExpr(SDOperand LHS, SDOperand RHS,
+                                                   unsigned OCHi, unsigned OCLo,
+                                                   bool IsArithmetic,
+                                                   bool Negate) {
+   // Check to make sure this is a constant.
+   ConstantSDNode *CN = dyn_cast<ConstantSDNode>(RHS);
+   // Exit if not a constant.
+   if (!CN) return 0;
+   // Extract immediate.
+   unsigned C = (unsigned)CN->getValue();
+   // Negate if required (ISD::SUB).
+   if (Negate) C = -C;
+   // Get the hi and lo portions of constant.
+   unsigned Hi = IsArithmetic ? HA16(C) : Hi16(C);
+   unsigned Lo = Lo16(C);
+ 
+   // If two instructions are needed and usage indicates it would be better to
+   // load immediate into a register, bail out.
+   if (Hi && Lo && CN->use_size() > 2) return false;
+ 
+   // Select the first operand.
+   SDOperand Opr0 = Select(LHS);
+ 
+   if (Lo)  // Add in the lo-part.
+     Opr0 = CurDAG->getTargetNode(OCLo, MVT::i32, Opr0, getI32Imm(Lo));
+   if (Hi)  // Add in the hi-part.
+     Opr0 = CurDAG->getTargetNode(OCHi, MVT::i32, Opr0, getI32Imm(Hi));
+   return Opr0.Val;
+ }
+ 
+ 
+ // Select - Convert the specified operand from a target-independent to a
+ // target-specific node if it hasn't already been changed.
+ SDOperand PPC32DAGToDAGISel::Select(SDOperand Op) {
+   SDNode *N = Op.Val;
+   if (N->getOpcode() >= ISD::BUILTIN_OP_END)
+     return Op;   // Already selected.
+   
+   switch (N->getOpcode()) {
+   default:
+     std::cerr << "Cannot yet select: ";
+     N->dump();
+     std::cerr << "\n";
+     abort();
+   case ISD::EntryToken:       // These leaves remain the same.
+   case ISD::UNDEF:
+     return Op;
+   case ISD::TokenFactor: {
+     SDOperand New;
+     if (N->getNumOperands() == 2) {
+       SDOperand Op0 = Select(N->getOperand(0));
+       SDOperand Op1 = Select(N->getOperand(1));
+       New = CurDAG->getNode(ISD::TokenFactor, MVT::Other, Op0, Op1);
+     } else {
+       std::vector<SDOperand> Ops;
+       for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
+         Ops.push_back(Select(N->getOperand(0)));
+       New = CurDAG->getNode(ISD::TokenFactor, MVT::Other, Ops);
+     }
+     
+     if (New.Val != N) {
+       CurDAG->ReplaceAllUsesWith(N, New.Val);
+       N = New.Val;
+     }
+     break;
+   }
+   case ISD::CopyFromReg: {
+     SDOperand Chain = Select(N->getOperand(0));
+     if (Chain == N->getOperand(0)) return Op; // No change
+     SDOperand New = CurDAG->getCopyFromReg(Chain,
+          cast<RegisterSDNode>(N->getOperand(1))->getReg(), N->getValueType(0));
+     return New.getValue(Op.ResNo);
+   }
+   case ISD::CopyToReg: {
+     SDOperand Chain = Select(N->getOperand(0));
+     SDOperand Reg = N->getOperand(1);
+     SDOperand Val = Select(N->getOperand(2));
+     if (Chain != N->getOperand(0) || Val != N->getOperand(2)) {
+       SDOperand New = CurDAG->getNode(ISD::CopyToReg, MVT::Other,
+                                       Chain, Reg, Val);
+       CurDAG->ReplaceAllUsesWith(N, New.Val);
+       N = New.Val;
+     }
+     break;    
+   }
+   case ISD::Constant: {
+     assert(N->getValueType(0) == MVT::i32);
+     unsigned v = (unsigned)cast<ConstantSDNode>(N)->getValue();
+     if ((unsigned)(short)v == v) {
+       CurDAG->SelectNodeTo(N, MVT::i32, PPC::LI, getI32Imm(v));
+       break;
+     } else {
+       SDOperand Top = CurDAG->getTargetNode(PPC::LIS, MVT::i32,
+                                             getI32Imm(unsigned(v) >> 16));
+       CurDAG->SelectNodeTo(N, MVT::i32, PPC::ORI, Top, getI32Imm(v & 0xFFFF));
+       break;
+     }
+   }
+ 
+   case ISD::ADD: {
+     MVT::ValueType Ty = N->getValueType(0);
+     if (Ty == MVT::i32) {
+       if (SDNode *I = SelectIntImmediateExpr(N->getOperand(0), N->getOperand(1),
+                                              PPC::ADDIS, PPC::ADDI, true)) {
+         CurDAG->ReplaceAllUsesWith(N, I);
+         N = I;
+       } else {
+         CurDAG->SelectNodeTo(N, Ty, PPC::ADD, Select(N->getOperand(0)),
+                              Select(N->getOperand(1)));
+       }
+       break;
+     }
+     
+     if (!NoExcessFPPrecision) {  // Match FMA ops
+       if (N->getOperand(0).getOpcode() == ISD::MUL &&
+           N->getOperand(0).Val->hasOneUse()) {
+         ++FusedFP; // Statistic
+         CurDAG->SelectNodeTo(N, Ty, Ty == MVT::f64 ? PPC::FMADD : PPC::FMADDS,
+                              Select(N->getOperand(0).getOperand(0)),
+                              Select(N->getOperand(0).getOperand(1)),
+                              Select(N->getOperand(1)));
+         break;
+       } else if (N->getOperand(1).getOpcode() == ISD::MUL &&
+                  N->getOperand(1).hasOneUse()) {
+         ++FusedFP; // Statistic
+         CurDAG->SelectNodeTo(N, Ty, Ty == MVT::f64 ? PPC::FMADD : PPC::FMADDS,
+                              Select(N->getOperand(1).getOperand(0)),
+                              Select(N->getOperand(1).getOperand(1)),
+                              Select(N->getOperand(0)));
+         break;
+       }
+     }
+     
+     CurDAG->SelectNodeTo(N, Ty, Ty == MVT::f64 ? PPC::FADD : PPC::FADDS,
+                          Select(N->getOperand(0)), Select(N->getOperand(1)));
+     break;
+   }
+   case ISD::SUB: {
+     MVT::ValueType Ty = N->getValueType(0);
+     if (Ty == MVT::i32) {
+       unsigned Imm;
+       if (isIntImmediate(N->getOperand(0), Imm) && isInt16(Imm)) {
+         CurDAG->SelectNodeTo(N, Ty, PPC::SUBFIC, Select(N->getOperand(1)),
+                              getI32Imm(Lo16(Imm)));
+         break;
+       }
+       if (SDNode *I = SelectIntImmediateExpr(N->getOperand(0), N->getOperand(1),
+                                           PPC::ADDIS, PPC::ADDI, true, true)) {
+         CurDAG->ReplaceAllUsesWith(N, I);
+         N = I;
+       } else {
+         CurDAG->SelectNodeTo(N, Ty, PPC::SUBF, Select(N->getOperand(1)),
+                              Select(N->getOperand(0)));
+       }
+       break;
+     }
+     
+     if (!NoExcessFPPrecision) {  // Match FMA ops
+       if (N->getOperand(0).getOpcode() == ISD::MUL &&
+           N->getOperand(0).Val->hasOneUse()) {
+         ++FusedFP; // Statistic
+         CurDAG->SelectNodeTo(N, Ty, Ty == MVT::f64 ? PPC::FMSUB : PPC::FMSUBS,
+                              Select(N->getOperand(0).getOperand(0)),
+                              Select(N->getOperand(0).getOperand(1)),
+                              Select(N->getOperand(1)));
+         break;
+       } else if (N->getOperand(1).getOpcode() == ISD::MUL &&
+                  N->getOperand(1).Val->hasOneUse()) {
+         ++FusedFP; // Statistic
+         CurDAG->SelectNodeTo(N, Ty, Ty == MVT::f64 ? PPC::FNMSUB : PPC::FNMSUBS,
+                              Select(N->getOperand(1).getOperand(0)),
+                              Select(N->getOperand(1).getOperand(1)),
+                              Select(N->getOperand(0)));
+         break;
+       }
+     }
+     CurDAG->SelectNodeTo(N, Ty, Ty == MVT::f64 ? PPC::FSUB : PPC::FSUBS,
+                          Select(N->getOperand(0)),
+                          Select(N->getOperand(1)));
+     break;
+   }    
+   case ISD::RET: {
+     SDOperand Chain = Select(N->getOperand(0));     // Token chain.
+ 
+     if (N->getNumOperands() > 1) {
+       SDOperand Val = Select(N->getOperand(1));
+       switch (N->getOperand(1).getValueType()) {
+       default: assert(0 && "Unknown return type!");
+       case MVT::f64:
+       case MVT::f32:
+         Chain = CurDAG->getCopyToReg(Chain, PPC::F1, Val);
+         break;
+       case MVT::i32:
+         Chain = CurDAG->getCopyToReg(Chain, PPC::R3, Val);
+         break;
+       }
+ 
+       if (N->getNumOperands() > 2) {
+         assert(N->getOperand(1).getValueType() == MVT::i32 &&
+                N->getOperand(2).getValueType() == MVT::i32 &&
+                N->getNumOperands() == 2 && "Unknown two-register ret value!");
+         Val = Select(N->getOperand(2));
+         Chain = CurDAG->getCopyToReg(Chain, PPC::R4, Val);
+       }
+     }
+ 
+     // Finally, select this to a blr (return) instruction.
+     CurDAG->SelectNodeTo(N, MVT::Other, PPC::BLR, Chain);
+     break;
+   }
+   }
+   return SDOperand(N, 0);
+ }
+ 
+ 
+ /// createPPC32ISelDag - This pass converts a legalized DAG into a 
+ /// PowerPC-specific DAG, ready for instruction scheduling.
+ ///
+ FunctionPass *llvm::createPPC32ISelDag(TargetMachine &TM) {
+   return new PPC32DAGToDAGISel(TM);
+ }
+ 





From lattner at cs.uiuc.edu  Wed Aug 17 14:33:41 2005
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Wed, 17 Aug 2005 14:33:41 -0500
Subject: [llvm-commits] 
	CVS: llvm/lib/Target/PowerPC/PowerPCTargetMachine.cpp
Message-ID: <200508171933.OAA11025@zion.cs.uiuc.edu>



Changes in directory llvm/lib/Target/PowerPC:

PowerPCTargetMachine.cpp updated: 1.63 -> 1.64
---
Log message:

add a beta option for turning on dag->dag isel


---
Diffs of the changes:  (+9 -3)

 PowerPCTargetMachine.cpp |   12 +++++++++---
 1 files changed, 9 insertions(+), 3 deletions(-)


Index: llvm/lib/Target/PowerPC/PowerPCTargetMachine.cpp
diff -u llvm/lib/Target/PowerPC/PowerPCTargetMachine.cpp:1.63 llvm/lib/Target/PowerPC/PowerPCTargetMachine.cpp:1.64
--- llvm/lib/Target/PowerPC/PowerPCTargetMachine.cpp:1.63	Mon Aug 15 18:47:04 2005
+++ llvm/lib/Target/PowerPC/PowerPCTargetMachine.cpp	Wed Aug 17 14:33:30 2005
@@ -30,8 +30,11 @@
 using namespace llvm;
 
 namespace {
-  const std::string PPC32ID = "PowerPC/32bit";
+  const char *PPC32ID = "PowerPC/32bit";
 
+  static cl::opt<bool> EnablePPCDAGDAG("enable-ppc-dag-isel", cl::Hidden,
+                            cl::desc("Enable DAG-to-DAG isel for PPC (beta)"));
+  
   // Register the targets
   RegisterTarget<PPC32TargetMachine>
   X("ppc32", "  PowerPC 32-bit");
@@ -81,8 +84,11 @@
   // Make sure that no unreachable blocks are instruction selected.
   PM.add(createUnreachableBlockEliminationPass());
 
-  // Default to pattern ISel
-  if (PatternISelTriState == 0) {
+  // Install an instruction selector.
+  if (EnablePPCDAGDAG) {
+    PM.add(createPPC32ISelDag(*this));
+    
+  } else if (PatternISelTriState == 0) {
     PM.add(createLowerConstantExpressionsPass());
     PM.add(createPPC32ISelSimple(*this));
   } else





From jlaskey at apple.com  Wed Aug 17 14:33:42 2005
From: jlaskey at apple.com (Jim Laskey)
Date: Wed, 17 Aug 2005 14:33:42 -0500
Subject: [llvm-commits] CVS: llvm/lib/VMCore/AsmWriter.cpp 
Message-ID: <200508171933.OAA11029@zion.cs.uiuc.edu>



Changes in directory llvm/lib/VMCore:

AsmWriter.cpp updated: 1.180 -> 1.181
---
Log message:

Culling out use of unions for converting FP to bits and vice versa.


 


---
Diffs of the changes:  (+2 -10)

 AsmWriter.cpp |   12 ++----------
 1 files changed, 2 insertions(+), 10 deletions(-)


Index: llvm/lib/VMCore/AsmWriter.cpp
diff -u llvm/lib/VMCore/AsmWriter.cpp:1.180 llvm/lib/VMCore/AsmWriter.cpp:1.181
--- llvm/lib/VMCore/AsmWriter.cpp:1.180	Sat Jun 18 13:34:52 2005
+++ llvm/lib/VMCore/AsmWriter.cpp	Wed Aug 17 14:33:31 2005
@@ -29,6 +29,7 @@
 #include "llvm/Support/CFG.h"
 #include "llvm/ADT/StringExtras.h"
 #include "llvm/ADT/STLExtras.h"
+#include "llvm/Support/MathExtras.h"
 #include <algorithm>
 using namespace llvm;
 
@@ -431,18 +432,9 @@
 
     // Otherwise we could not reparse it to exactly the same value, so we must
     // output the string in hexadecimal format!
-    //
-    // Behave nicely in the face of C TBAA rules... see:
-    // http://www.nullstone.com/htmls/category/aliastyp.htm
-    //
-    union {
-      double D;
-      uint64_t U;
-    } V;
-    V.D = CFP->getValue();
     assert(sizeof(double) == sizeof(uint64_t) &&
            "assuming that double is 64 bits!");
-    Out << "0x" << utohexstr(V.U);
+    Out << "0x" << utohexstr(DoubleToBits(CFP->getValue()));
 
   } else if (isa<ConstantAggregateZero>(CV)) {
     Out << "zeroinitializer";





From jlaskey at apple.com  Wed Aug 17 14:35:00 2005
From: jlaskey at apple.com (Jim Laskey)
Date: Wed, 17 Aug 2005 14:35:00 -0500
Subject: [llvm-commits] CVS: llvm/lib/VMCore/Constants.cpp 
Message-ID: <200508171935.OAA11059@zion.cs.uiuc.edu>



Changes in directory llvm/lib/VMCore:

Constants.cpp updated: 1.126 -> 1.127
---
Log message:

Culling out use of unions for converting FP to bits and vice versa.


 
 


---
Diffs of the changes:  (+5 -24)

 Constants.cpp |   29 +++++------------------------
 1 files changed, 5 insertions(+), 24 deletions(-)


Index: llvm/lib/VMCore/Constants.cpp
diff -u llvm/lib/VMCore/Constants.cpp:1.126 llvm/lib/VMCore/Constants.cpp:1.127
--- llvm/lib/VMCore/Constants.cpp:1.126	Thu Apr 21 18:46:51 2005
+++ llvm/lib/VMCore/Constants.cpp	Wed Aug 17 14:34:49 2005
@@ -19,6 +19,7 @@
 #include "llvm/SymbolTable.h"
 #include "llvm/Module.h"
 #include "llvm/ADT/StringExtras.h"
+#include "llvm/Support/MathExtras.h"
 #include <algorithm>
 #include <iostream>
 using namespace llvm;
@@ -796,24 +797,14 @@
   struct ConstantCreator<ConstantFP, Type, uint64_t> {
     static ConstantFP *create(const Type *Ty, uint64_t V) {
       assert(Ty == Type::DoubleTy);
-      union {
-        double F;
-        uint64_t I;
-      } T;
-      T.I = V;
-      return new ConstantFP(Ty, T.F);
+      return new ConstantFP(Ty, BitsToDouble(V));
     }
   };
   template<>
   struct ConstantCreator<ConstantFP, Type, uint32_t> {
     static ConstantFP *create(const Type *Ty, uint32_t V) {
       assert(Ty == Type::FloatTy);
-      union {
-        float F;
-        uint32_t I;
-      } T;
-      T.I = V;
-      return new ConstantFP(Ty, T.F);
+      return new ConstantFP(Ty, BitsToFloat(V));
     }
   };
 }
@@ -824,20 +815,10 @@
 ConstantFP *ConstantFP::get(const Type *Ty, double V) {
   if (Ty == Type::FloatTy) {
     // Force the value through memory to normalize it.
-    union {
-      float F;
-      uint32_t I;
-    } T;
-    T.F = (float)V;
-    return FloatConstants.getOrCreate(Ty, T.I);
+    return FloatConstants.getOrCreate(Ty, FloatToBits(V));
   } else {
     assert(Ty == Type::DoubleTy);
-    union {
-      double F;
-      uint64_t I;
-    } T;
-    T.F = V;
-    return DoubleConstants.getOrCreate(Ty, T.I);
+    return DoubleConstants.getOrCreate(Ty, DoubleToBits(V));
   }
 }
 





From jlaskey at apple.com  Wed Aug 17 15:04:45 2005
From: jlaskey at apple.com (Jim Laskey)
Date: Wed, 17 Aug 2005 15:04:45 -0500
Subject: [llvm-commits] CVS: llvm/lib/Target/SparcV8/SparcV8AsmPrinter.cpp 
Message-ID: <200508172004.PAA11494@zion.cs.uiuc.edu>



Changes in directory llvm/lib/Target/SparcV8:

SparcV8AsmPrinter.cpp updated: 1.34 -> 1.35
---
Log message:

Promote dependency for MathExtras.h out of Constants.h.



---
Diffs of the changes:  (+1 -0)

 SparcV8AsmPrinter.cpp |    1 +
 1 files changed, 1 insertion(+)


Index: llvm/lib/Target/SparcV8/SparcV8AsmPrinter.cpp
diff -u llvm/lib/Target/SparcV8/SparcV8AsmPrinter.cpp:1.34 llvm/lib/Target/SparcV8/SparcV8AsmPrinter.cpp:1.35
--- llvm/lib/Target/SparcV8/SparcV8AsmPrinter.cpp:1.34	Wed Aug 17 14:32:54 2005
+++ llvm/lib/Target/SparcV8/SparcV8AsmPrinter.cpp	Wed Aug 17 15:04:34 2005
@@ -26,6 +26,7 @@
 #include "llvm/ADT/Statistic.h"
 #include "llvm/ADT/StringExtras.h"
 #include "llvm/Support/CommandLine.h"
+#include "llvm/Support/MathExtras.h"
 #include <cctype>
 using namespace llvm;
 





From jlaskey at apple.com  Wed Aug 17 15:06:34 2005
From: jlaskey at apple.com (Jim Laskey)
Date: Wed, 17 Aug 2005 15:06:34 -0500
Subject: [llvm-commits] CVS: llvm/include/llvm/Constants.h 
Message-ID: <200508172006.PAA11530@zion.cs.uiuc.edu>



Changes in directory llvm/include/llvm:

Constants.h updated: 1.71 -> 1.72
---
Log message:

Move code dependency for MathExtras.h out of Constants.h.



---
Diffs of the changes:  (+2 -7)

 Constants.h |    9 ++-------
 1 files changed, 2 insertions(+), 7 deletions(-)


Index: llvm/include/llvm/Constants.h
diff -u llvm/include/llvm/Constants.h:1.71 llvm/include/llvm/Constants.h:1.72
--- llvm/include/llvm/Constants.h:1.71	Wed Aug 17 14:19:16 2005
+++ llvm/include/llvm/Constants.h	Wed Aug 17 15:06:22 2005
@@ -23,7 +23,6 @@
 #include "llvm/Constant.h"
 #include "llvm/Type.h"
 #include "llvm/Support/DataTypes.h"
-#include "llvm/Support/MathExtras.h"
 
 namespace llvm {
 
@@ -277,17 +276,13 @@
   /// isNullValue - Return true if this is the value that would be returned by
   /// getNullValue.  Don't depend on == for doubles to tell us it's zero, it
   /// considers -0.0 to be null as well as 0.0.  :(
-  virtual bool isNullValue() const {
-    return DoubleToBits(Val) == 0;
-  }
+  virtual bool isNullValue() const;
 
   /// isExactlyValue - We don't rely on operator== working on double values, as
   /// it returns true for things that are clearly not equal, like -0.0 and 0.0.
   /// As such, this method can be used to do an exact bit-for-bit comparison of
   /// two floating point values.
-  bool isExactlyValue(double V) const {
-    return DoubleToBits(V) == DoubleToBits(Val);
-  }
+  bool isExactlyValue(double V) const;
 
   /// Methods for support type inquiry through isa, cast, and dyn_cast:
   static inline bool classof(const ConstantFP *) { return true; }





From jlaskey at apple.com  Wed Aug 17 15:06:34 2005
From: jlaskey at apple.com (Jim Laskey)
Date: Wed, 17 Aug 2005 15:06:34 -0500
Subject: [llvm-commits] CVS: llvm/lib/VMCore/Constants.cpp 
Message-ID: <200508172006.PAA11534@zion.cs.uiuc.edu>



Changes in directory llvm/lib/VMCore:

Constants.cpp updated: 1.127 -> 1.128
---
Log message:

Move code dependency for MathExtras.h out of Constants.h.



---
Diffs of the changes:  (+9 -0)

 Constants.cpp |    9 +++++++++
 1 files changed, 9 insertions(+)


Index: llvm/lib/VMCore/Constants.cpp
diff -u llvm/lib/VMCore/Constants.cpp:1.127 llvm/lib/VMCore/Constants.cpp:1.128
--- llvm/lib/VMCore/Constants.cpp:1.127	Wed Aug 17 14:34:49 2005
+++ llvm/lib/VMCore/Constants.cpp	Wed Aug 17 15:06:22 2005
@@ -812,6 +812,15 @@
 static ValueMap<uint64_t, Type, ConstantFP> DoubleConstants;
 static ValueMap<uint32_t, Type, ConstantFP> FloatConstants;
 
+bool ConstantFP::isNullValue() const {
+  return DoubleToBits(Val) == 0;
+}
+
+bool ConstantFP::isExactlyValue(double V) const {
+  return DoubleToBits(V) == DoubleToBits(Val);
+}
+
+
 ConstantFP *ConstantFP::get(const Type *Ty, double V) {
   if (Ty == Type::FloatTy) {
     // Force the value through memory to normalize it.





From jlaskey at apple.com  Wed Aug 17 15:08:15 2005
From: jlaskey at apple.com (Jim Laskey)
Date: Wed, 17 Aug 2005 15:08:15 -0500
Subject: [llvm-commits] CVS: llvm/include/llvm/CodeGen/SelectionDAGNodes.h 
Message-ID: <200508172008.PAA11559@zion.cs.uiuc.edu>



Changes in directory llvm/include/llvm/CodeGen:

SelectionDAGNodes.h updated: 1.55 -> 1.56
---
Log message:

Move the code dependency for MathExtras.h from SelectionDAGNodes.h.

Added some class dividers in SelectionDAG.cpp.



---
Diffs of the changes:  (+1 -4)

 SelectionDAGNodes.h |    5 +----
 1 files changed, 1 insertion(+), 4 deletions(-)


Index: llvm/include/llvm/CodeGen/SelectionDAGNodes.h
diff -u llvm/include/llvm/CodeGen/SelectionDAGNodes.h:1.55 llvm/include/llvm/CodeGen/SelectionDAGNodes.h:1.56
--- llvm/include/llvm/CodeGen/SelectionDAGNodes.h:1.55	Wed Aug 17 14:20:43 2005
+++ llvm/include/llvm/CodeGen/SelectionDAGNodes.h	Wed Aug 17 15:08:02 2005
@@ -25,7 +25,6 @@
 #include "llvm/ADT/GraphTraits.h"
 #include "llvm/ADT/iterator"
 #include "llvm/Support/DataTypes.h"
-#include "llvm/Support/MathExtras.h"
 #include <cassert>
 #include <vector>
 
@@ -742,9 +741,7 @@
   /// it returns true for things that are clearly not equal, like -0.0 and 0.0.
   /// As such, this method can be used to do an exact bit-for-bit comparison of
   /// two floating point values.
-  bool isExactlyValue(double V) const {
-    return DoubleToBits(V) == DoubleToBits(Value);
-  }
+  bool isExactlyValue(double V) const;
 
   static bool classof(const ConstantFPSDNode *) { return true; }
   static bool classof(const SDNode *N) {





From jlaskey at apple.com  Wed Aug 17 15:08:15 2005
From: jlaskey at apple.com (Jim Laskey)
Date: Wed, 17 Aug 2005 15:08:15 -0500
Subject: [llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp 
Message-ID: <200508172008.PAA11558@zion.cs.uiuc.edu>



Changes in directory llvm/lib/CodeGen/SelectionDAG:

SelectionDAG.cpp updated: 1.146 -> 1.147
---
Log message:

Move the code dependency for MathExtras.h from SelectionDAGNodes.h.

Added some class dividers in SelectionDAG.cpp.



---
Diffs of the changes:  (+21 -1)

 SelectionDAG.cpp |   22 +++++++++++++++++++++-
 1 files changed, 21 insertions(+), 1 deletion(-)


Index: llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp:1.146 llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp:1.147
--- llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp:1.146	Wed Aug 17 14:28:27 2005
+++ llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp	Wed Aug 17 15:08:02 2005
@@ -57,6 +57,21 @@
   return false;
 }
 
+//===----------------------------------------------------------------------===//
+//                              ConstantFPSDNode Class
+//===----------------------------------------------------------------------===//
+
+/// isExactlyValue - We don't rely on operator== working on double values, as
+/// it returns true for things that are clearly not equal, like -0.0 and 0.0.
+/// As such, this method can be used to do an exact bit-for-bit comparison of
+/// two floating point values.
+bool ConstantFPSDNode::isExactlyValue(double V) const {
+  return DoubleToBits(V) == DoubleToBits(Value);
+}
+
+//===----------------------------------------------------------------------===//
+//                              ISD Class
+//===----------------------------------------------------------------------===//
 
 /// getSetCCSwappedOperands - Return the operation corresponding to (Y op X)
 /// when given the operation for (X op Y).
@@ -140,6 +155,9 @@
   return TLI.getTargetMachine();
 }
 
+//===----------------------------------------------------------------------===//
+//                              SelectionDAG Class
+//===----------------------------------------------------------------------===//
 
 /// RemoveDeadNodes - This method deletes all unreachable nodes in the
 /// SelectionDAG, including nodes (like loads) that have uses of their token
@@ -1822,7 +1840,9 @@
   }
 }
 
-
+//===----------------------------------------------------------------------===//
+//                              SDNode Class
+//===----------------------------------------------------------------------===//
 
 /// hasNUsesOfValue - Return true if there are exactly NUSES uses of the
 /// indicated value.  This method ignores uses of other values defined by this





From lattner at cs.uiuc.edu  Wed Aug 17 16:21:59 2005
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Wed, 17 Aug 2005 16:21:59 -0500
Subject: [llvm-commits] 
	CVS: llvm/test/Regression/Transforms/LoopStrengthReduce/2005-08-17-OutOfLoopVariant.ll
Message-ID: <200508172121.QAA28857@zion.cs.uiuc.edu>



Changes in directory llvm/test/Regression/Transforms/LoopStrengthReduce:

2005-08-17-OutOfLoopVariant.ll added (r1.1)
---
Log message:

new testcase distilled from mesa


---
Diffs of the changes:  (+18 -0)

 2005-08-17-OutOfLoopVariant.ll |   18 ++++++++++++++++++
 1 files changed, 18 insertions(+)


Index: llvm/test/Regression/Transforms/LoopStrengthReduce/2005-08-17-OutOfLoopVariant.ll
diff -c /dev/null llvm/test/Regression/Transforms/LoopStrengthReduce/2005-08-17-OutOfLoopVariant.ll:1.1
*** /dev/null	Wed Aug 17 16:21:57 2005
--- llvm/test/Regression/Transforms/LoopStrengthReduce/2005-08-17-OutOfLoopVariant.ll	Wed Aug 17 16:21:47 2005
***************
*** 0 ****
--- 1,18 ----
+ ; RUN: llvm-as < %s | opt -loop-reduce -disable-output
+ 
+ int %image_to_texture(uint %indvar454) {
+ loopentry.1.outer:
+ 	%j.2.1.ph = cast uint %indvar454 to int		; <int> [#uses=1]
+ 	br label %loopentry.1
+ 
+ loopentry.1:		; preds = %label.5, %loopentry.1.outer
+ 	%i.3 = phi int [ 0, %loopentry.1.outer ], [ %i.3.be, %loopentry.1 ]
+ 	%tmp.390 = load int* null		; <int> [#uses=1]
+ 	%tmp.392 = mul int %tmp.390, %j.2.1.ph		; <int> [#uses=1]
+ 	%tmp.394 = add int %tmp.392, %i.3		; <int> [#uses=1]
+ 	%i.3.be = add int %i.3, 1		; <int> [#uses=1]
+ 	br bool false, label %loopentry.1, label %label.6
+ 
+ label.6:		; preds = %no_exit.1
+ 	ret int %tmp.394
+ }





From lattner at cs.uiuc.edu  Wed Aug 17 16:22:52 2005
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Wed, 17 Aug 2005 16:22:52 -0500
Subject: [llvm-commits] 
	CVS: llvm/lib/Transforms/Scalar/LoopStrengthReduce.cpp
Message-ID: <200508172122.QAA28918@zion.cs.uiuc.edu>



Changes in directory llvm/lib/Transforms/Scalar:

LoopStrengthReduce.cpp updated: 1.53 -> 1.54
---
Log message:

Fix Transforms/LoopStrengthReduce/2005-08-17-OutOfLoopVariant.ll, a crash
on 177.mesa


---
Diffs of the changes:  (+4 -1)

 LoopStrengthReduce.cpp |    5 ++++-
 1 files changed, 4 insertions(+), 1 deletion(-)


Index: llvm/lib/Transforms/Scalar/LoopStrengthReduce.cpp
diff -u llvm/lib/Transforms/Scalar/LoopStrengthReduce.cpp:1.53 llvm/lib/Transforms/Scalar/LoopStrengthReduce.cpp:1.54
--- llvm/lib/Transforms/Scalar/LoopStrengthReduce.cpp:1.53	Wed Aug 17 01:35:16 2005
+++ llvm/lib/Transforms/Scalar/LoopStrengthReduce.cpp	Wed Aug 17 16:22:41 2005
@@ -744,7 +744,10 @@
     // value of the IV.  Do not put anything in the base, make sure it's all in
     // the immediate field to allow as much factoring as possible.
     if (!L->contains(UsersToProcess[i].Inst->getParent())) {
-      std::swap(UsersToProcess[i].Base, UsersToProcess[i].Imm);
+      UsersToProcess[i].Imm = SCEVAddExpr::get(UsersToProcess[i].Imm,
+                                               UsersToProcess[i].Base);
+      UsersToProcess[i].Base = 
+        SCEVUnknown::getIntegerSCEV(0, UsersToProcess[i].Base->getType());
     } else {
       
       // Addressing modes can be folded into loads and stores.  Be careful that





From reid at x10sys.com  Wed Aug 17 17:43:30 2005
From: reid at x10sys.com (Reid Spencer)
Date: Wed, 17 Aug 2005 15:43:30 -0700
Subject: [llvm-commits] CVS: llvm/include/llvm/Support/MathExtras.h
In-Reply-To: <200508171728.MAA08704@zion.cs.uiuc.edu>
References: <200508171728.MAA08704@zion.cs.uiuc.edu>
Message-ID: <1124318610.25996.11.camel@bashful.x10sys.com>

Jim,

Is this going to work okay on all platforms? (see below)

On Wed, 2005-08-17 at 12:28 -0500, Jim Laskey wrote:
> 
> Changes in directory llvm/include/llvm/Support:
> 
> MathExtras.h updated: 1.23 -> 1.24
> ---
> Log message:
> 
> Added support for converting raw bits to FP, and FP to raw bits.  The intent
> is to avoid the distraction of the union declarations.
> 
> 
> 
> ---
> Diffs of the changes:  (+44 -0)
> 
>  MathExtras.h |   44 ++++++++++++++++++++++++++++++++++++++++++++
>  1 files changed, 44 insertions(+)
> 
> 
> Index: llvm/include/llvm/Support/MathExtras.h
> diff -u llvm/include/llvm/Support/MathExtras.h:1.23 llvm/include/llvm/Support/MathExtras.h:1.24
> --- llvm/include/llvm/Support/MathExtras.h:1.23	Wed Aug  3 15:53:19 2005
> +++ llvm/include/llvm/Support/MathExtras.h	Wed Aug 17 12:27:47 2005
> @@ -168,6 +168,50 @@
>      return 63 - CountLeadingZeros_64(Value);
>  }
>  
> +// BitsToDouble - This function takes a 64-bit integer and returns the bit
> +// equivalent double.
> +inline double BitsToDouble(uint64_t Bits) {
> +  union {
> +    uint64_t L;
> +    double D;
> +  } T;
> +  T.L = Bits;
> +  return T.D;
> +}

This one should be fine because double and uint64_t are 64-bits on all
platforms we care about.

> +
> +// BitsToFloat - This function takes a 32-bit integer and returns the bit
> +// equivalent float.
> +inline float BitsToFloat(unsigned Bits) {
> +  union {
> +    unsigned I;
> +    float F;
> +  } T;
> +  T.I = Bits;
> +  return T.F;
> +}

This one I'm not so sure about. "unsigned" could be 32 or 64-bits
depending on the platform. float is probably 32-bits on all platforms we
care about. If unsigned is 64-bits and big-endian, we would get the
wrong value for the float as it would be effectively shifted into the
high order bits. Truncation could occur too.

Shouldn't this use uin32_t instead of "unsigned" ?


> +
> +// DoubleToBits - This function takes a double and returns the bit
> +// equivalent 64-bit integer.
> +inline uint64_t DoubleToBits(double Double) {
> +  union {
> +    uint64_t L;
> +    double D;
> +  } T;
> +  T.D = Double;
> +  return T.L;
> +}

This should be okay.

> +
> +// FloatToBits - This function takes a float and returns the bit
> +// equivalent 32-bit integer.
> +inline unsigned FloatToBits(float Float) {
> +  union {
> +    unsigned I;
> +    float F;
> +  } T;
> +  T.F = Float;
> +  return T.I;
> +}

This one suffers same problem as for BitsToFloat

Reid
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From sabre at nondot.org  Wed Aug 17 17:46:37 2005
From: sabre at nondot.org (Chris Lattner)
Date: Wed, 17 Aug 2005 17:46:37 -0500 (CDT)
Subject: [llvm-commits] CVS: llvm/include/llvm/Support/MathExtras.h
In-Reply-To: <1124318610.25996.11.camel@bashful.x10sys.com>
References: <200508171728.MAA08704@zion.cs.uiuc.edu>
	<1124318610.25996.11.camel@bashful.x10sys.com>
Message-ID: <Pine.LNX.4.61.0508171745070.3454@nondot.org>

On Wed, 17 Aug 2005, Reid Spencer wrote:
>> +// BitsToFloat - This function takes a 32-bit integer and returns the bit
>> +// equivalent float.
>> +inline float BitsToFloat(unsigned Bits) {
>> +  union {
>> +    unsigned I;
>> +    float F;
>> +  } T;
>> +  T.I = Bits;
>> +  return T.F;
>> +}
>
> This one I'm not so sure about. "unsigned" could be 32 or 64-bits
> depending on the platform. float is probably 32-bits on all platforms we
> care about. If unsigned is 64-bits and big-endian, we would get the
> wrong value for the float as it would be effectively shifted into the
> high order bits. Truncation could occur too.
>
> Shouldn't this use uin32_t instead of "unsigned" ?

He's not making things any worse than they were before, but I don't see 
any harm in changing it to uint32_t.  LLVM has many assumptions that 
int/unsigned are 32-bits.  Are you aware of any platform (that matters) 
where int is not 32-bits?

-Chris

>> +// DoubleToBits - This function takes a double and returns the bit
>> +// equivalent 64-bit integer.
>> +inline uint64_t DoubleToBits(double Double) {
>> +  union {
>> +    uint64_t L;
>> +    double D;
>> +  } T;
>> +  T.D = Double;
>> +  return T.L;
>> +}
>
> This should be okay.
>
>> +
>> +// FloatToBits - This function takes a float and returns the bit
>> +// equivalent 32-bit integer.
>> +inline unsigned FloatToBits(float Float) {
>> +  union {
>> +    unsigned I;
>> +    float F;
>> +  } T;
>> +  T.F = Float;
>> +  return T.I;
>> +}
>
> This one suffers same problem as for BitsToFloat
>
> Reid
>

-Chris

-- 
http://nondot.org/sabre/
http://llvm.org/



From reid at x10sys.com  Wed Aug 17 18:33:05 2005
From: reid at x10sys.com (Reid Spencer)
Date: Wed, 17 Aug 2005 16:33:05 -0700
Subject: [llvm-commits] CVS: llvm/include/llvm/Support/MathExtras.h
In-Reply-To: <Pine.LNX.4.61.0508171745070.3454@nondot.org>
References: <200508171728.MAA08704@zion.cs.uiuc.edu>
	<1124318610.25996.11.camel@bashful.x10sys.com>
	<Pine.LNX.4.61.0508171745070.3454@nondot.org>
Message-ID: <1124321585.25996.20.camel@bashful.x10sys.com>

On Wed, 2005-08-17 at 17:46 -0500, Chris Lattner wrote:
> On Wed, 17 Aug 2005, Reid Spencer wrote:
> >> +// BitsToFloat - This function takes a 32-bit integer and returns the bit
> >> +// equivalent float.
> >> +inline float BitsToFloat(unsigned Bits) {
> >> +  union {
> >> +    unsigned I;
> >> +    float F;
> >> +  } T;
> >> +  T.I = Bits;
> >> +  return T.F;
> >> +}
> >
> > This one I'm not so sure about. "unsigned" could be 32 or 64-bits
> > depending on the platform. float is probably 32-bits on all platforms we
> > care about. If unsigned is 64-bits and big-endian, we would get the
> > wrong value for the float as it would be effectively shifted into the
> > high order bits. Truncation could occur too.
> >
> > Shouldn't this use uin32_t instead of "unsigned" ?
> 
> He's not making things any worse than they were before, but I don't see 
> any harm in changing it to uint32_t.  

True, he's not, but I agree that changing it to uint32_t would both do
no harm and potentially avoid problems down the road.

> LLVM has many assumptions that 
> int/unsigned are 32-bits. 

In many of those cases, the range of possible values makes the size of
unsigned irrelevant. Not so in this case.

>  Are you aware of any platform (that matters) where int is not 32-bits?

It generally depends on the compiler in use since the standard
recommends a size but does not prohibit a compiler from specifying an
"implementation dependent" size. One of the reasons we don't get
problems in this area is because we use GCC nearly everywhere and its
sizes are consistent from platform to platform. HOWEVER, we are also
currently supporting aCC on HP-UX and the opportunity for supporting
other compilers in the future exists. Of particular not, I believe this
code will break on a 64-bit HP-UX machine compiled with aCC where "int"
is 64-bits

Reid
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From sabre at nondot.org  Wed Aug 17 18:35:43 2005
From: sabre at nondot.org (Chris Lattner)
Date: Wed, 17 Aug 2005 18:35:43 -0500 (CDT)
Subject: [llvm-commits] CVS: llvm/include/llvm/Support/MathExtras.h
In-Reply-To: <1124321585.25996.20.camel@bashful.x10sys.com>
References: <200508171728.MAA08704@zion.cs.uiuc.edu> 
	<1124318610.25996.11.camel@bashful.x10sys.com>
	<Pine.LNX.4.61.0508171745070.3454@nondot.org>
	<1124321585.25996.20.camel@bashful.x10sys.com>
Message-ID: <Pine.LNX.4.61.0508171834580.4306@nondot.org>

On Wed, 17 Aug 2005, Reid Spencer wrote:
> It generally depends on the compiler in use since the standard
> recommends a size but does not prohibit a compiler from specifying an
> "implementation dependent" size. One of the reasons we don't get
> problems in this area is because we use GCC nearly everywhere and its
> sizes are consistent from platform to platform. HOWEVER, we are also
> currently supporting aCC on HP-UX and the opportunity for supporting
> other compilers in the future exists. Of particular not, I believe this
> code will break on a 64-bit HP-UX machine compiled with aCC where "int"
> is 64-bits

No, this depends on the ABI, not the compiler.  I seriously doubt that int 
is 64-bits on HPUX.  Duraid, do you know?

-Chris

-- 
http://nondot.org/sabre/
http://llvm.org/



From natebegeman at mac.com  Wed Aug 17 18:45:06 2005
From: natebegeman at mac.com (Nate Begeman)
Date: Wed, 17 Aug 2005 18:45:06 -0500
Subject: [llvm-commits] CVS: llvm/include/llvm/CodeGen/SelectionDAGNodes.h 
Message-ID: <200508172345.SAA15499@zion.cs.uiuc.edu>



Changes in directory llvm/include/llvm/CodeGen:

SelectionDAGNodes.h updated: 1.56 -> 1.57
---
Log message:

Add two new methods isTargetOpcode() which returns true if the node type
is greater than the range of building selection dag node types, and
getTargetOpcode(), which returns the node opcode less the value of
isd::builtin_op_end, which specifies the end of the builtin types.


---
Diffs of the changes:  (+13 -0)

 SelectionDAGNodes.h |   13 +++++++++++++
 1 files changed, 13 insertions(+)


Index: llvm/include/llvm/CodeGen/SelectionDAGNodes.h
diff -u llvm/include/llvm/CodeGen/SelectionDAGNodes.h:1.56 llvm/include/llvm/CodeGen/SelectionDAGNodes.h:1.57
--- llvm/include/llvm/CodeGen/SelectionDAGNodes.h:1.56	Wed Aug 17 15:08:02 2005
+++ llvm/include/llvm/CodeGen/SelectionDAGNodes.h	Wed Aug 17 18:44:54 2005
@@ -428,6 +428,8 @@
   inline unsigned getNodeDepth() const;
   inline unsigned getNumOperands() const;
   inline const SDOperand &getOperand(unsigned i) const;
+  inline bool isTargetOpcode() const;
+  inline unsigned getTargetOpcode() const;
 
   /// hasOneUse - Return true if there is exactly one operation using this
   /// result value of the defining operator.
@@ -480,6 +482,11 @@
   //  Accessors
   //
   unsigned getOpcode()  const { return NodeType; }
+  bool isTargetOpcode() const { return NodeType >= ISD::BUILTIN_OP_END; }
+  unsigned getTargetOpcode() const {
+    assert(isTargetOpcode() && "Not a target opcode!");
+    return NodeType - ISD::BUILTIN_OP_END;
+  }
 
   size_t use_size() const { return Uses.size(); }
   bool use_empty() const { return Uses.empty(); }
@@ -691,6 +698,12 @@
 inline const SDOperand &SDOperand::getOperand(unsigned i) const {
   return Val->getOperand(i);
 }
+inline bool SDOperand::isTargetOpcode() const {
+  return Val->isTargetOpcode();
+}
+inline unsigned SDOperand::getTargetOpcode() const {
+  return Val->getTargetOpcode();
+}
 inline bool SDOperand::hasOneUse() const {
   return Val->hasNUsesOfValue(1, ResNo);
 }





From natebegeman at mac.com  Wed Aug 17 18:46:48 2005
From: natebegeman at mac.com (Nate Begeman)
Date: Wed, 17 Aug 2005 18:46:48 -0500
Subject: [llvm-commits] CVS: llvm/lib/Target/PowerPC/PPC32ISelDAGToDAG.cpp 
Message-ID: <200508172346.SAA15514@zion.cs.uiuc.edu>



Changes in directory llvm/lib/Target/PowerPC:

PPC32ISelDAGToDAG.cpp updated: 1.1 -> 1.2
---
Log message:

Teach the DAG->DAG ISel about FNEG, and how it can be used to invert 
several of the PowerPC opcodes that come in both negated and non-negated
forms.


---
Diffs of the changes:  (+29 -2)

 PPC32ISelDAGToDAG.cpp |   31 +++++++++++++++++++++++++++++--
 1 files changed, 29 insertions(+), 2 deletions(-)


Index: llvm/lib/Target/PowerPC/PPC32ISelDAGToDAG.cpp
diff -u llvm/lib/Target/PowerPC/PPC32ISelDAGToDAG.cpp:1.1 llvm/lib/Target/PowerPC/PPC32ISelDAGToDAG.cpp:1.2
--- llvm/lib/Target/PowerPC/PPC32ISelDAGToDAG.cpp:1.1	Wed Aug 17 14:33:03 2005
+++ llvm/lib/Target/PowerPC/PPC32ISelDAGToDAG.cpp	Wed Aug 17 18:46:35 2005
@@ -199,7 +199,6 @@
       break;
     }
   }
-
   case ISD::ADD: {
     MVT::ValueType Ty = N->getValueType(0);
     if (Ty == MVT::i32) {
@@ -281,7 +280,35 @@
                          Select(N->getOperand(0)),
                          Select(N->getOperand(1)));
     break;
-  }    
+  }
+  case ISD::FNEG: {
+    SDOperand Val = Select(N->getOperand(0));
+    MVT::ValueType Ty = N->getValueType(0);
+    if (Val.Val->hasOneUse()) {
+      unsigned Opc;
+      switch (Val.getTargetOpcode()) {
+      default:          Opc = 0;            break;
+      case PPC::FABS:   Opc = PPC::FNABS;   break;
+      case PPC::FMADD:  Opc = PPC::FNMADD;  break;
+      case PPC::FMADDS: Opc = PPC::FNMADDS; break;
+      case PPC::FMSUB:  Opc = PPC::FNMSUB;  break;
+      case PPC::FMSUBS: Opc = PPC::FNMSUBS; break;
+      }
+      // If we inverted the opcode, then emit the new instruction with the
+      // inverted opcode and the original instruction's operands.  Otherwise, 
+      // fall through and generate a fneg instruction.
+      if (Opc) {
+        if (PPC::FNABS == Opc)
+          CurDAG->SelectNodeTo(N, Ty, Opc, Val.getOperand(0));
+        else
+          CurDAG->SelectNodeTo(N, Ty, Opc, Val.getOperand(0),
+                               Val.getOperand(1), Val.getOperand(2));
+        break;
+      }
+    }
+    CurDAG->SelectNodeTo(N, Ty, PPC::FNEG, Val);
+    break;
+  }
   case ISD::RET: {
     SDOperand Chain = Select(N->getOperand(0));     // Token chain.
 





From jlaskey at apple.com  Wed Aug 17 18:54:24 2005
From: jlaskey at apple.com (Jim Laskey)
Date: Wed, 17 Aug 2005 18:54:24 -0500
Subject: [llvm-commits] CVS: llvm/include/llvm/Support/MathExtras.h 
Message-ID: <200508172354.SAA15551@zion.cs.uiuc.edu>



Changes in directory llvm/include/llvm/Support:

MathExtras.h updated: 1.24 -> 1.25
---
Log message:

include/llvm/Support/MathExtras.h

---
Diffs of the changes:  (+4 -4)

 MathExtras.h |    8 ++++----
 1 files changed, 4 insertions(+), 4 deletions(-)


Index: llvm/include/llvm/Support/MathExtras.h
diff -u llvm/include/llvm/Support/MathExtras.h:1.24 llvm/include/llvm/Support/MathExtras.h:1.25
--- llvm/include/llvm/Support/MathExtras.h:1.24	Wed Aug 17 12:27:47 2005
+++ llvm/include/llvm/Support/MathExtras.h	Wed Aug 17 18:54:12 2005
@@ -181,9 +181,9 @@
 
 // BitsToFloat - This function takes a 32-bit integer and returns the bit
 // equivalent float.
-inline float BitsToFloat(unsigned Bits) {
+inline float BitsToFloat(uint32_t Bits) {
   union {
-    unsigned I;
+    uint32_t I;
     float F;
   } T;
   T.I = Bits;
@@ -203,9 +203,9 @@
 
 // FloatToBits - This function takes a float and returns the bit
 // equivalent 32-bit integer.
-inline unsigned FloatToBits(float Float) {
+inline uint32_t FloatToBits(float Float) {
   union {
-    unsigned I;
+    uint32_t I;
     float F;
   } T;
   T.F = Float;





From jlaskey at apple.com  Wed Aug 17 18:54:24 2005
From: jlaskey at apple.com (Jim Laskey)
Date: Wed, 17 Aug 2005 18:54:24 -0500
Subject: [llvm-commits] CVS: llvm/Xcode/LLVM.xcodeproj/project.pbxproj 
Message-ID: <200508172354.SAA15555@zion.cs.uiuc.edu>



Changes in directory llvm/Xcode/LLVM.xcodeproj:

project.pbxproj updated: 1.1 -> 1.2
---
Log message:

include/llvm/Support/MathExtras.h

---
Diffs of the changes:  (+3 -57)

 project.pbxproj |   60 ++------------------------------------------------------
 1 files changed, 3 insertions(+), 57 deletions(-)


Index: llvm/Xcode/LLVM.xcodeproj/project.pbxproj
diff -u llvm/Xcode/LLVM.xcodeproj/project.pbxproj:1.1 llvm/Xcode/LLVM.xcodeproj/project.pbxproj:1.2
--- llvm/Xcode/LLVM.xcodeproj/project.pbxproj:1.1	Thu Aug 11 17:19:26 2005
+++ llvm/Xcode/LLVM.xcodeproj/project.pbxproj	Wed Aug 17 18:54:12 2005
@@ -238,7 +238,6 @@
 		DE66EEA508ABEE5E00323D32 /* AlphaInstrInfo.h */ = {isa = PBXFileReference; fileEncoding = 30; lastKnownFileType = sourcecode.c.h; path = AlphaInstrInfo.h; sourceTree = "<group>"; };
 		DE66EEA608ABEE5E00323D32 /* AlphaInstrInfo.td */ = {isa = PBXFileReference; fileEncoding = 30; lastKnownFileType = text; path = AlphaInstrInfo.td; sourceTree = "<group>"; };
 		DE66EEA708ABEE5E00323D32 /* AlphaISelPattern.cpp */ = {isa = PBXFileReference; fileEncoding = 30; lastKnownFileType = sourcecode.cpp.cpp; path = AlphaISelPattern.cpp; sourceTree = "<group>"; };
-		DE66EEA808ABEE5E00323D32 /* AlphaISelPattern.cpp.orig */ = {isa = PBXFileReference; fileEncoding = 30; lastKnownFileType = text; path = AlphaISelPattern.cpp.orig; sourceTree = "<group>"; };
 		DE66EEA908ABEE5E00323D32 /* AlphaJITInfo.cpp */ = {isa = PBXFileReference; fileEncoding = 30; lastKnownFileType = sourcecode.cpp.cpp; path = AlphaJITInfo.cpp; sourceTree = "<group>"; };
 		DE66EEAA08ABEE5E00323D32 /* AlphaJITInfo.h */ = {isa = PBXFileReference; fileEncoding = 30; lastKnownFileType = sourcecode.c.h; path = AlphaJITInfo.h; sourceTree = "<group>"; };
 		DE66EEAB08ABEE5E00323D32 /* AlphaRegisterInfo.cpp */ = {isa = PBXFileReference; fileEncoding = 30; lastKnownFileType = sourcecode.cpp.cpp; path = AlphaRegisterInfo.cpp; sourceTree = "<group>"; };
@@ -266,7 +265,6 @@
 		DE66EF0C08ABEE5E00323D32 /* IA64TargetMachine.h */ = {isa = PBXFileReference; fileEncoding = 30; lastKnownFileType = sourcecode.c.h; path = IA64TargetMachine.h; sourceTree = "<group>"; };
 		DE66EF0E08ABEE5E00323D32 /* README */ = {isa = PBXFileReference; fileEncoding = 30; lastKnownFileType = text; path = README; sourceTree = "<group>"; };
 		DE66EF1008ABEE5E00323D32 /* MRegisterInfo.cpp */ = {isa = PBXFileReference; fileEncoding = 30; lastKnownFileType = sourcecode.cpp.cpp; path = MRegisterInfo.cpp; sourceTree = "<group>"; };
-		DE66EF1208ABEE5E00323D32 /* .cvsignore */ = {isa = PBXFileReference; fileEncoding = 30; lastKnownFileType = text; path = .cvsignore; sourceTree = "<group>"; };
 		DE66EF3D08ABEE5F00323D32 /* LICENSE.TXT */ = {isa = PBXFileReference; fileEncoding = 30; lastKnownFileType = text; path = LICENSE.TXT; sourceTree = "<group>"; };
 		DE66EF3F08ABEE5F00323D32 /* PowerPC.h */ = {isa = PBXFileReference; fileEncoding = 30; lastKnownFileType = sourcecode.c.h; path = PowerPC.h; sourceTree = "<group>"; };
 		DE66EF4008ABEE5F00323D32 /* PowerPC.td */ = {isa = PBXFileReference; fileEncoding = 30; lastKnownFileType = text; path = PowerPC.td; sourceTree = "<group>"; };
@@ -297,17 +295,8 @@
 		DE66EF6008ABEE5F00323D32 /* PPC32Relocations.h */ = {isa = PBXFileReference; fileEncoding = 30; lastKnownFileType = sourcecode.c.h; path = PPC32Relocations.h; sourceTree = "<group>"; };
 		DE66EF6108ABEE5F00323D32 /* PPC32TargetMachine.h */ = {isa = PBXFileReference; fileEncoding = 30; lastKnownFileType = sourcecode.c.h; path = PPC32TargetMachine.h; sourceTree = "<group>"; };
 		DE66EF6208ABEE5F00323D32 /* PPC64.td */ = {isa = PBXFileReference; fileEncoding = 30; lastKnownFileType = text; path = PPC64.td; sourceTree = "<group>"; };
-		DE66EF6308ABEE5F00323D32 /* PPC64CodeEmitter.cpp */ = {isa = PBXFileReference; fileEncoding = 30; lastKnownFileType = sourcecode.cpp.cpp; path = PPC64CodeEmitter.cpp; sourceTree = "<group>"; };
-		DE66EF6708ABEE5F00323D32 /* PPC64InstrInfo.cpp */ = {isa = PBXFileReference; fileEncoding = 30; lastKnownFileType = sourcecode.cpp.cpp; path = PPC64InstrInfo.cpp; sourceTree = "<group>"; };
-		DE66EF6808ABEE5F00323D32 /* PPC64InstrInfo.h */ = {isa = PBXFileReference; fileEncoding = 30; lastKnownFileType = sourcecode.c.h; path = PPC64InstrInfo.h; sourceTree = "<group>"; };
-		DE66EF6908ABEE5F00323D32 /* PPC64ISelPattern.cpp */ = {isa = PBXFileReference; fileEncoding = 30; lastKnownFileType = sourcecode.cpp.cpp; path = PPC64ISelPattern.cpp; sourceTree = "<group>"; };
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@@ -340,7 +329,6 @@
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@@ -391,9 +379,6 @@
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@@ -438,7 +423,6 @@
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@@ -455,7 +439,6 @@
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@@ -551,7 +534,6 @@
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@@ -642,9 +624,7 @@
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@@ -673,7 +653,6 @@
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@@ -682,7 +661,6 @@
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@@ -783,7 +760,6 @@
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@@ -1305,7 +1278,6 @@
 				DE66EEA508ABEE5E00323D32 /* AlphaInstrInfo.h */,
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 				DE66EEAA08ABEE5E00323D32 /* AlphaJITInfo.h */,
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-				DE66EF6308ABEE5F00323D32 /* PPC64CodeEmitter.cpp */,
-				DE66EF6708ABEE5F00323D32 /* PPC64InstrInfo.cpp */,
-				DE66EF6808ABEE5F00323D32 /* PPC64InstrInfo.h */,
-				DE66EF6908ABEE5F00323D32 /* PPC64ISelPattern.cpp */,
-				DE66EF6A08ABEE5F00323D32 /* PPC64JITInfo.h */,
-				DE66EF6B08ABEE5F00323D32 /* PPC64RegisterInfo.cpp */,
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 				DE66EF6D08ABEE5F00323D32 /* PPC64RegisterInfo.td */,
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 			);
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 				DE66EFFA08ABEE6000323D32 /* DecomposeMultiDimRefs.cpp */,
 				DE66EFFB08ABEE6000323D32 /* EmitBytecodeToAssembly.cpp */,
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@@ -1464,9 +1425,6 @@
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@@ -1576,7 +1534,6 @@
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-				DE66F09408ABEE6000323D32 /* .cvsignore */,
 				DE66F0BC08ABEE6000323D32 /* X86.h */,
 				DE66F0BD08ABEE6000323D32 /* X86.td */,
 				DE66F0BE08ABEE6000323D32 /* X86AsmPrinter.cpp */,
@@ -1593,7 +1550,6 @@
 				DE66F0D008ABEE6100323D32 /* X86IntelAsmPrinter.cpp */,
 				DE66F0D108ABEE6100323D32 /* X86IntelAsmPrinter.h */,
 				DE66F0D208ABEE6100323D32 /* X86ISelPattern.cpp */,
-				DE66F0D308ABEE6100323D32 /* X86ISelPattern.cpp.orig */,
 				DE66F0D408ABEE6100323D32 /* X86ISelSimple.cpp */,
 				DE66F0D508ABEE6100323D32 /* X86JITInfo.cpp */,
 				DE66F0D608ABEE6100323D32 /* X86JITInfo.h */,
@@ -1793,7 +1749,6 @@
 		DE66F1EB08ABF03100323D32 /* ADT */ = {
 			isa = PBXGroup;
 			children = (
-				DE66F1EC08ABF03100323D32 /* .cvsignore */,
 				DE66F1ED08ABF03100323D32 /* BitSetVector.h */,
 				DE66F1EE08ABF03100323D32 /* DenseMap.h */,
 				DE66F1EF08ABF03100323D32 /* DepthFirstIterator.h */,
@@ -1923,9 +1878,7 @@
 		DE66F24C08ABF03100323D32 /* Config */ = {
 			isa = PBXGroup;
 			children = (
-				DE66F24D08ABF03100323D32 /* .cvsignore */,
 				DE66F24E08ABF03100323D32 /* alloca.h */,
-				DE66F24F08ABF03100323D32 /* config.h */,
 				DE66F25008ABF03100323D32 /* config.h.in */,
 			);
 			path = Config;
@@ -1956,7 +1909,6 @@
 		DE66F26E08ABF03200323D32 /* Support */ = {
 			isa = PBXGroup;
 			children = (
-				DE66F26F08ABF03200323D32 /* .cvsignore */,
 				DE66F27008ABF03200323D32 /* AIXDataTypesFix.h */,
 				DE66F27108ABF03200323D32 /* Annotation.h */,
 				DE66F27208ABF03200323D32 /* CallSite.h */,
@@ -1965,7 +1917,6 @@
 				DE66F27508ABF03200323D32 /* CommandLine.h */,
 				DE66F27608ABF03200323D32 /* Compressor.h */,
 				DE66F27708ABF03200323D32 /* ConstantRange.h */,
-				DE66F27808ABF03200323D32 /* DataTypes.h */,
 				DE66F27908ABF03200323D32 /* DataTypes.h.in */,
 				DE66F27A08ABF03200323D32 /* Debug.h */,
 				DE66F27B08ABF03200323D32 /* DOTGraphTraits.h */,
@@ -1986,7 +1937,6 @@
 				DE66F28A08ABF03200323D32 /* SlowOperationInformer.h */,
 				DE66F28B08ABF03200323D32 /* StableBasicBlockNumbering.h */,
 				DE66F28C08ABF03200323D32 /* SystemUtils.h */,
-				DE66F28D08ABF03200323D32 /* ThreadSupport.h */,
 				DE66F28E08ABF03200323D32 /* Timer.h */,
 				DE66F28F08ABF03200323D32 /* ToolRunner.h */,
 				DE66F29008ABF03200323D32 /* type_traits.h */,
@@ -2146,7 +2096,6 @@
 				DE66F36908ABF14500323D32 /* c */,
 				DE66F36A08ABF14500323D32 /* CompilerDriver.cpp */,
 				DE66F36B08ABF14500323D32 /* CompilerDriver.h */,
-				DE66F36C08ABF14500323D32 /* ConfigLexer.cpp */,
 				DE66F36D08ABF14500323D32 /* ConfigLexer.h */,
 				DE66F36E08ABF14500323D32 /* ConfigLexer.l */,
 				DE66F36F08ABF14500323D32 /* Configuration.cpp */,
@@ -2161,7 +2110,6 @@
 		DE66F38D08ABF35C00323D32 /* docs */ = {
 			isa = PBXGroup;
 			children = (
-				DE66F38E08ABF35C00323D32 /* .cvsignore */,
 				DE66F38F08ABF35C00323D32 /* AliasAnalysis.html */,
 				DE66F39008ABF35C00323D32 /* Bugpoint.html */,
 				DE66F39108ABF35C00323D32 /* BytecodeFormat.html */,
@@ -2172,7 +2120,6 @@
 				DE66F3B908ABF35D00323D32 /* CommandLine.html */,
 				DE66F3BA08ABF35D00323D32 /* CompilerDriver.html */,
 				DE66F3BB08ABF35D00323D32 /* CompilerWriterInfo.html */,
-				DE66F3BC08ABF35D00323D32 /* doxygen.cfg */,
 				DE66F3BD08ABF35D00323D32 /* doxygen.cfg.in */,
 				DE66F3BE08ABF35D00323D32 /* doxygen.css */,
 				DE66F3BF08ABF35D00323D32 /* doxygen.footer */,
@@ -2210,7 +2157,6 @@
 		DE66F39508ABF35C00323D32 /* CommandGuide */ = {
 			isa = PBXGroup;
 			children = (
-				DE66F39608ABF35C00323D32 /* .cvsignore */,
 				DE66F39708ABF35C00323D32 /* analyze.pod */,
 				DE66F39808ABF35C00323D32 /* bugpoint.pod */,
 				DE66F39908ABF35C00323D32 /* gccas.pod */,
@@ -2270,7 +2216,7 @@
 /* Begin PBXLegacyTarget section */
 		D28A88AD04BDD90700651E21 /* LLVM */ = {
 			isa = PBXLegacyTarget;
-			buildArgumentsString = "$(ACTION)";
+			buildArgumentsString = "-j 4 $(ACTION)";
 			buildConfigurationList = DE66EC4C08ABE78900323D32 /* Build configuration list for PBXLegacyTarget "LLVM" */;
 			buildPhases = (
 			);
@@ -2280,11 +2226,11 @@
 				PRODUCT_NAME = LLVM;
 			};
 			buildToolPath = /usr/bin/make;
-			buildWorkingDirectory = ..;
+			buildWorkingDirectory = /llvm/obj;
 			dependencies = (
 			);
 			name = LLVM;
-			passBuildSettingsInEnvironment = 1;
+			passBuildSettingsInEnvironment = 0;
 			productName = LLVM;
 		};
 /* End PBXLegacyTarget section */





From jlaskey at apple.com  Wed Aug 17 18:57:36 2005
From: jlaskey at apple.com (Jim Laskey)
Date: Wed, 17 Aug 2005 18:57:36 -0500
Subject: [llvm-commits] CVS: llvm/Xcode/LLVM.xcodeproj/project.pbxproj 
Message-ID: <200508172357.SAA15578@zion.cs.uiuc.edu>



Changes in directory llvm/Xcode/LLVM.xcodeproj:

project.pbxproj updated: 1.2 -> 1.3
---
Log message:

messed up

---
Diffs of the changes:  (+57 -3)

 project.pbxproj |   60 +++++++++++++++++++++++++++++++++++++++++++++++++++++---
 1 files changed, 57 insertions(+), 3 deletions(-)


Index: llvm/Xcode/LLVM.xcodeproj/project.pbxproj
diff -u llvm/Xcode/LLVM.xcodeproj/project.pbxproj:1.2 llvm/Xcode/LLVM.xcodeproj/project.pbxproj:1.3
--- llvm/Xcode/LLVM.xcodeproj/project.pbxproj:1.2	Wed Aug 17 18:54:12 2005
+++ llvm/Xcode/LLVM.xcodeproj/project.pbxproj	Wed Aug 17 18:57:24 2005
@@ -238,6 +238,7 @@
 		DE66EEA508ABEE5E00323D32 /* AlphaInstrInfo.h */ = {isa = PBXFileReference; fileEncoding = 30; lastKnownFileType = sourcecode.c.h; path = AlphaInstrInfo.h; sourceTree = "<group>"; };
 		DE66EEA608ABEE5E00323D32 /* AlphaInstrInfo.td */ = {isa = PBXFileReference; fileEncoding = 30; lastKnownFileType = text; path = AlphaInstrInfo.td; sourceTree = "<group>"; };
 		DE66EEA708ABEE5E00323D32 /* AlphaISelPattern.cpp */ = {isa = PBXFileReference; fileEncoding = 30; lastKnownFileType = sourcecode.cpp.cpp; path = AlphaISelPattern.cpp; sourceTree = "<group>"; };
+		DE66EEA808ABEE5E00323D32 /* AlphaISelPattern.cpp.orig */ = {isa = PBXFileReference; fileEncoding = 30; lastKnownFileType = text; path = AlphaISelPattern.cpp.orig; sourceTree = "<group>"; };
 		DE66EEA908ABEE5E00323D32 /* AlphaJITInfo.cpp */ = {isa = PBXFileReference; fileEncoding = 30; lastKnownFileType = sourcecode.cpp.cpp; path = AlphaJITInfo.cpp; sourceTree = "<group>"; };
 		DE66EEAA08ABEE5E00323D32 /* AlphaJITInfo.h */ = {isa = PBXFileReference; fileEncoding = 30; lastKnownFileType = sourcecode.c.h; path = AlphaJITInfo.h; sourceTree = "<group>"; };
 		DE66EEAB08ABEE5E00323D32 /* AlphaRegisterInfo.cpp */ = {isa = PBXFileReference; fileEncoding = 30; lastKnownFileType = sourcecode.cpp.cpp; path = AlphaRegisterInfo.cpp; sourceTree = "<group>"; };
@@ -265,6 +266,7 @@
 		DE66EF0C08ABEE5E00323D32 /* IA64TargetMachine.h */ = {isa = PBXFileReference; fileEncoding = 30; lastKnownFileType = sourcecode.c.h; path = IA64TargetMachine.h; sourceTree = "<group>"; };
 		DE66EF0E08ABEE5E00323D32 /* README */ = {isa = PBXFileReference; fileEncoding = 30; lastKnownFileType = text; path = README; sourceTree = "<group>"; };
 		DE66EF1008ABEE5E00323D32 /* MRegisterInfo.cpp */ = {isa = PBXFileReference; fileEncoding = 30; lastKnownFileType = sourcecode.cpp.cpp; path = MRegisterInfo.cpp; sourceTree = "<group>"; };
+		DE66EF1208ABEE5E00323D32 /* .cvsignore */ = {isa = PBXFileReference; fileEncoding = 30; lastKnownFileType = text; path = .cvsignore; sourceTree = "<group>"; };
 		DE66EF3D08ABEE5F00323D32 /* LICENSE.TXT */ = {isa = PBXFileReference; fileEncoding = 30; lastKnownFileType = text; path = LICENSE.TXT; sourceTree = "<group>"; };
 		DE66EF3F08ABEE5F00323D32 /* PowerPC.h */ = {isa = PBXFileReference; fileEncoding = 30; lastKnownFileType = sourcecode.c.h; path = PowerPC.h; sourceTree = "<group>"; };
 		DE66EF4008ABEE5F00323D32 /* PowerPC.td */ = {isa = PBXFileReference; fileEncoding = 30; lastKnownFileType = text; path = PowerPC.td; sourceTree = "<group>"; };
@@ -295,8 +297,17 @@
 		DE66EF6008ABEE5F00323D32 /* PPC32Relocations.h */ = {isa = PBXFileReference; fileEncoding = 30; lastKnownFileType = sourcecode.c.h; path = PPC32Relocations.h; sourceTree = "<group>"; };
 		DE66EF6108ABEE5F00323D32 /* PPC32TargetMachine.h */ = {isa = PBXFileReference; fileEncoding = 30; lastKnownFileType = sourcecode.c.h; path = PPC32TargetMachine.h; sourceTree = "<group>"; };
 		DE66EF6208ABEE5F00323D32 /* PPC64.td */ = {isa = PBXFileReference; fileEncoding = 30; lastKnownFileType = text; path = PPC64.td; sourceTree = "<group>"; };
+		DE66EF6308ABEE5F00323D32 /* PPC64CodeEmitter.cpp */ = {isa = PBXFileReference; fileEncoding = 30; lastKnownFileType = sourcecode.cpp.cpp; path = PPC64CodeEmitter.cpp; sourceTree = "<group>"; };
+		DE66EF6708ABEE5F00323D32 /* PPC64InstrInfo.cpp */ = {isa = PBXFileReference; fileEncoding = 30; lastKnownFileType = sourcecode.cpp.cpp; path = PPC64InstrInfo.cpp; sourceTree = "<group>"; };
+		DE66EF6808ABEE5F00323D32 /* PPC64InstrInfo.h */ = {isa = PBXFileReference; fileEncoding = 30; lastKnownFileType = sourcecode.c.h; path = PPC64InstrInfo.h; sourceTree = "<group>"; };
+		DE66EF6908ABEE5F00323D32 /* PPC64ISelPattern.cpp */ = {isa = PBXFileReference; fileEncoding = 30; lastKnownFileType = sourcecode.cpp.cpp; path = PPC64ISelPattern.cpp; sourceTree = "<group>"; };
+		DE66EF6A08ABEE5F00323D32 /* PPC64JITInfo.h */ = {isa = PBXFileReference; fileEncoding = 30; lastKnownFileType = sourcecode.c.h; path = PPC64JITInfo.h; sourceTree = "<group>"; };
+		DE66EF6B08ABEE5F00323D32 /* PPC64RegisterInfo.cpp */ = {isa = PBXFileReference; fileEncoding = 30; lastKnownFileType = sourcecode.cpp.cpp; path = PPC64RegisterInfo.cpp; sourceTree = "<group>"; };
+		DE66EF6C08ABEE5F00323D32 /* PPC64RegisterInfo.h */ = {isa = PBXFileReference; fileEncoding = 30; lastKnownFileType = sourcecode.c.h; path = PPC64RegisterInfo.h; sourceTree = "<group>"; };
 		DE66EF6D08ABEE5F00323D32 /* PPC64RegisterInfo.td */ = {isa = PBXFileReference; fileEncoding = 30; lastKnownFileType = text; path = PPC64RegisterInfo.td; sourceTree = "<group>"; };
+		DE66EF6E08ABEE5F00323D32 /* PPC64TargetMachine.h */ = {isa = PBXFileReference; fileEncoding = 30; lastKnownFileType = sourcecode.c.h; path = PPC64TargetMachine.h; sourceTree = "<group>"; };
 		DE66EF6F08ABEE5F00323D32 /* README.txt */ = {isa = PBXFileReference; fileEncoding = 30; lastKnownFileType = text; path = README.txt; sourceTree = "<group>"; };
+		DE66EF7108ABEE5F00323D32 /* .cvsignore */ = {isa = PBXFileReference; fileEncoding = 30; lastKnownFileType = text; path = .cvsignore; sourceTree = "<group>"; };
 		DE66EF8208ABEE5F00323D32 /* README.txt */ = {isa = PBXFileReference; fileEncoding = 30; lastKnownFileType = text; path = README.txt; sourceTree = "<group>"; };
 		DE66EF8308ABEE5F00323D32 /* Skeleton.h */ = {isa = PBXFileReference; fileEncoding = 30; lastKnownFileType = sourcecode.c.h; path = Skeleton.h; sourceTree = "<group>"; };
 		DE66EF8408ABEE5F00323D32 /* Skeleton.td */ = {isa = PBXFileReference; fileEncoding = 30; lastKnownFileType = text; path = Skeleton.td; sourceTree = "<group>"; };
@@ -329,6 +340,7 @@
 		DE66EFC608ABEE5F00323D32 /* SparcV8RegisterInfo.td */ = {isa = PBXFileReference; fileEncoding = 30; lastKnownFileType = text; path = SparcV8RegisterInfo.td; sourceTree = "<group>"; };
 		DE66EFC708ABEE5F00323D32 /* SparcV8TargetMachine.cpp */ = {isa = PBXFileReference; fileEncoding = 30; lastKnownFileType = sourcecode.cpp.cpp; path = SparcV8TargetMachine.cpp; sourceTree = "<group>"; };
 		DE66EFC808ABEE5F00323D32 /* SparcV8TargetMachine.h */ = {isa = PBXFileReference; fileEncoding = 30; lastKnownFileType = sourcecode.c.h; path = SparcV8TargetMachine.h; sourceTree = "<group>"; };
+		DE66EFCA08ABEE5F00323D32 /* .cvsignore */ = {isa = PBXFileReference; fileEncoding = 30; lastKnownFileType = text; path = .cvsignore; sourceTree = "<group>"; };
 		DE66EFFA08ABEE6000323D32 /* DecomposeMultiDimRefs.cpp */ = {isa = PBXFileReference; fileEncoding = 30; lastKnownFileType = sourcecode.cpp.cpp; path = DecomposeMultiDimRefs.cpp; sourceTree = "<group>"; };
 		DE66EFFB08ABEE6000323D32 /* EmitBytecodeToAssembly.cpp */ = {isa = PBXFileReference; fileEncoding = 30; lastKnownFileType = sourcecode.cpp.cpp; path = EmitBytecodeToAssembly.cpp; sourceTree = "<group>"; };
 		DE66F00708ABEE6000323D32 /* InstrScheduling.cpp */ = {isa = PBXFileReference; fileEncoding = 30; lastKnownFileType = sourcecode.cpp.cpp; path = InstrScheduling.cpp; sourceTree = "<group>"; };
@@ -379,6 +391,9 @@
 		DE66F06008ABEE6000323D32 /* RegClass.cpp */ = {isa = PBXFileReference; fileEncoding = 30; lastKnownFileType = sourcecode.cpp.cpp; path = RegClass.cpp; sourceTree = "<group>"; };
 		DE66F06108ABEE6000323D32 /* RegClass.h */ = {isa = PBXFileReference; fileEncoding = 30; lastKnownFileType = sourcecode.c.h; path = RegClass.h; sourceTree = "<group>"; };
 		DE66F06208ABEE6000323D32 /* SparcV9.burg.in */ = {isa = PBXFileReference; fileEncoding = 30; lastKnownFileType = text; path = SparcV9.burg.in; sourceTree = "<group>"; };
+		DE66F06308ABEE6000323D32 /* SparcV9.burg.in1 */ = {isa = PBXFileReference; fileEncoding = 30; lastKnownFileType = text; path = SparcV9.burg.in1; sourceTree = "<group>"; };
+		DE66F06408ABEE6000323D32 /* SparcV9.burm */ = {isa = PBXFileReference; fileEncoding = 30; lastKnownFileType = text; path = SparcV9.burm; sourceTree = "<group>"; };
+		DE66F06508ABEE6000323D32 /* SparcV9.burm.cpp */ = {isa = PBXFileReference; fileEncoding = 30; lastKnownFileType = sourcecode.cpp.cpp; path = SparcV9.burm.cpp; sourceTree = "<group>"; };
 		DE66F06608ABEE6000323D32 /* SparcV9.td */ = {isa = PBXFileReference; fileEncoding = 30; lastKnownFileType = text; path = SparcV9.td; sourceTree = "<group>"; };
 		DE66F06708ABEE6000323D32 /* SparcV9_F2.td */ = {isa = PBXFileReference; fileEncoding = 30; lastKnownFileType = text; path = SparcV9_F2.td; sourceTree = "<group>"; };
 		DE66F06808ABEE6000323D32 /* SparcV9_F3.td */ = {isa = PBXFileReference; fileEncoding = 30; lastKnownFileType = text; path = SparcV9_F3.td; sourceTree = "<group>"; };
@@ -423,6 +438,7 @@
 		DE66F09008ABEE6000323D32 /* TargetMachineRegistry.cpp */ = {isa = PBXFileReference; fileEncoding = 30; lastKnownFileType = sourcecode.cpp.cpp; path = TargetMachineRegistry.cpp; sourceTree = "<group>"; };
 		DE66F09108ABEE6000323D32 /* TargetSchedInfo.cpp */ = {isa = PBXFileReference; fileEncoding = 30; lastKnownFileType = sourcecode.cpp.cpp; path = TargetSchedInfo.cpp; sourceTree = "<group>"; };
 		DE66F09208ABEE6000323D32 /* TargetSubtarget.cpp */ = {isa = PBXFileReference; fileEncoding = 30; lastKnownFileType = sourcecode.cpp.cpp; path = TargetSubtarget.cpp; sourceTree = "<group>"; };
+		DE66F09408ABEE6000323D32 /* .cvsignore */ = {isa = PBXFileReference; fileEncoding = 30; lastKnownFileType = text; path = .cvsignore; sourceTree = "<group>"; };
 		DE66F0BC08ABEE6000323D32 /* X86.h */ = {isa = PBXFileReference; fileEncoding = 30; lastKnownFileType = sourcecode.c.h; path = X86.h; sourceTree = "<group>"; };
 		DE66F0BD08ABEE6000323D32 /* X86.td */ = {isa = PBXFileReference; fileEncoding = 30; lastKnownFileType = text; path = X86.td; sourceTree = "<group>"; };
 		DE66F0BE08ABEE6000323D32 /* X86AsmPrinter.cpp */ = {isa = PBXFileReference; fileEncoding = 30; lastKnownFileType = sourcecode.cpp.cpp; path = X86AsmPrinter.cpp; sourceTree = "<group>"; };
@@ -439,6 +455,7 @@
 		DE66F0D008ABEE6100323D32 /* X86IntelAsmPrinter.cpp */ = {isa = PBXFileReference; fileEncoding = 30; lastKnownFileType = sourcecode.cpp.cpp; path = X86IntelAsmPrinter.cpp; sourceTree = "<group>"; };
 		DE66F0D108ABEE6100323D32 /* X86IntelAsmPrinter.h */ = {isa = PBXFileReference; fileEncoding = 30; lastKnownFileType = sourcecode.c.h; path = X86IntelAsmPrinter.h; sourceTree = "<group>"; };
 		DE66F0D208ABEE6100323D32 /* X86ISelPattern.cpp */ = {isa = PBXFileReference; fileEncoding = 30; lastKnownFileType = sourcecode.cpp.cpp; path = X86ISelPattern.cpp; sourceTree = "<group>"; };
+		DE66F0D308ABEE6100323D32 /* X86ISelPattern.cpp.orig */ = {isa = PBXFileReference; fileEncoding = 30; lastKnownFileType = text; path = X86ISelPattern.cpp.orig; sourceTree = "<group>"; };
 		DE66F0D408ABEE6100323D32 /* X86ISelSimple.cpp */ = {isa = PBXFileReference; fileEncoding = 30; lastKnownFileType = sourcecode.cpp.cpp; path = X86ISelSimple.cpp; sourceTree = "<group>"; };
 		DE66F0D508ABEE6100323D32 /* X86JITInfo.cpp */ = {isa = PBXFileReference; fileEncoding = 30; lastKnownFileType = sourcecode.cpp.cpp; path = X86JITInfo.cpp; sourceTree = "<group>"; };
 		DE66F0D608ABEE6100323D32 /* X86JITInfo.h */ = {isa = PBXFileReference; fileEncoding = 30; lastKnownFileType = sourcecode.c.h; path = X86JITInfo.h; sourceTree = "<group>"; };
@@ -534,6 +551,7 @@
 		DE66F1E708ABEFB400323D32 /* ValueMapper.cpp */ = {isa = PBXFileReference; fileEncoding = 30; lastKnownFileType = sourcecode.cpp.cpp; path = ValueMapper.cpp; sourceTree = "<group>"; };
 		DE66F1E808ABEFB400323D32 /* ValueMapper.h */ = {isa = PBXFileReference; fileEncoding = 30; lastKnownFileType = sourcecode.c.h; path = ValueMapper.h; sourceTree = "<group>"; };
 		DE66F1EA08ABF03100323D32 /* AbstractTypeUser.h */ = {isa = PBXFileReference; fileEncoding = 30; lastKnownFileType = sourcecode.c.h; path = AbstractTypeUser.h; sourceTree = "<group>"; };
+		DE66F1EC08ABF03100323D32 /* .cvsignore */ = {isa = PBXFileReference; fileEncoding = 30; lastKnownFileType = text; path = .cvsignore; sourceTree = "<group>"; };
 		DE66F1ED08ABF03100323D32 /* BitSetVector.h */ = {isa = PBXFileReference; fileEncoding = 30; lastKnownFileType = sourcecode.c.h; path = BitSetVector.h; sourceTree = "<group>"; };
 		DE66F1EE08ABF03100323D32 /* DenseMap.h */ = {isa = PBXFileReference; fileEncoding = 30; lastKnownFileType = sourcecode.c.h; path = DenseMap.h; sourceTree = "<group>"; };
 		DE66F1EF08ABF03100323D32 /* DepthFirstIterator.h */ = {isa = PBXFileReference; fileEncoding = 30; lastKnownFileType = sourcecode.c.h; path = DepthFirstIterator.h; sourceTree = "<group>"; };
@@ -624,7 +642,9 @@
 		DE66F24908ABF03100323D32 /* SSARegMap.h */ = {isa = PBXFileReference; fileEncoding = 30; lastKnownFileType = sourcecode.c.h; path = SSARegMap.h; sourceTree = "<group>"; };
 		DE66F24A08ABF03100323D32 /* ValueSet.h */ = {isa = PBXFileReference; fileEncoding = 30; lastKnownFileType = sourcecode.c.h; path = ValueSet.h; sourceTree = "<group>"; };
 		DE66F24B08ABF03100323D32 /* ValueTypes.h */ = {isa = PBXFileReference; fileEncoding = 30; lastKnownFileType = sourcecode.c.h; path = ValueTypes.h; sourceTree = "<group>"; };
+		DE66F24D08ABF03100323D32 /* .cvsignore */ = {isa = PBXFileReference; fileEncoding = 30; lastKnownFileType = text; path = .cvsignore; sourceTree = "<group>"; };
 		DE66F24E08ABF03100323D32 /* alloca.h */ = {isa = PBXFileReference; fileEncoding = 30; lastKnownFileType = sourcecode.c.h; path = alloca.h; sourceTree = "<group>"; };
+		DE66F24F08ABF03100323D32 /* config.h */ = {isa = PBXFileReference; fileEncoding = 30; lastKnownFileType = sourcecode.c.h; path = config.h; sourceTree = "<group>"; };
 		DE66F25008ABF03100323D32 /* config.h.in */ = {isa = PBXFileReference; fileEncoding = 30; lastKnownFileType = text; path = config.h.in; sourceTree = "<group>"; };
 		DE66F25108ABF03100323D32 /* Constant.h */ = {isa = PBXFileReference; fileEncoding = 30; lastKnownFileType = sourcecode.c.h; path = Constant.h; sourceTree = "<group>"; };
 		DE66F25208ABF03100323D32 /* Constants.h */ = {isa = PBXFileReference; fileEncoding = 30; lastKnownFileType = sourcecode.c.h; path = Constants.h; sourceTree = "<group>"; };
@@ -653,6 +673,7 @@
 		DE66F26B08ABF03200323D32 /* PassAnalysisSupport.h */ = {isa = PBXFileReference; fileEncoding = 30; lastKnownFileType = sourcecode.c.h; path = PassAnalysisSupport.h; sourceTree = "<group>"; };
 		DE66F26C08ABF03200323D32 /* PassManager.h */ = {isa = PBXFileReference; fileEncoding = 30; lastKnownFileType = sourcecode.c.h; path = PassManager.h; sourceTree = "<group>"; };
 		DE66F26D08ABF03200323D32 /* PassSupport.h */ = {isa = PBXFileReference; fileEncoding = 30; lastKnownFileType = sourcecode.c.h; path = PassSupport.h; sourceTree = "<group>"; };
+		DE66F26F08ABF03200323D32 /* .cvsignore */ = {isa = PBXFileReference; fileEncoding = 30; lastKnownFileType = text; path = .cvsignore; sourceTree = "<group>"; };
 		DE66F27008ABF03200323D32 /* AIXDataTypesFix.h */ = {isa = PBXFileReference; fileEncoding = 30; lastKnownFileType = sourcecode.c.h; path = AIXDataTypesFix.h; sourceTree = "<group>"; };
 		DE66F27108ABF03200323D32 /* Annotation.h */ = {isa = PBXFileReference; fileEncoding = 30; lastKnownFileType = sourcecode.c.h; path = Annotation.h; sourceTree = "<group>"; };
 		DE66F27208ABF03200323D32 /* CallSite.h */ = {isa = PBXFileReference; fileEncoding = 30; lastKnownFileType = sourcecode.c.h; path = CallSite.h; sourceTree = "<group>"; };
@@ -661,6 +682,7 @@
 		DE66F27508ABF03200323D32 /* CommandLine.h */ = {isa = PBXFileReference; fileEncoding = 30; lastKnownFileType = sourcecode.c.h; path = CommandLine.h; sourceTree = "<group>"; };
 		DE66F27608ABF03200323D32 /* Compressor.h */ = {isa = PBXFileReference; fileEncoding = 30; lastKnownFileType = sourcecode.c.h; path = Compressor.h; sourceTree = "<group>"; };
 		DE66F27708ABF03200323D32 /* ConstantRange.h */ = {isa = PBXFileReference; fileEncoding = 30; lastKnownFileType = sourcecode.c.h; path = ConstantRange.h; sourceTree = "<group>"; };
+		DE66F27808ABF03200323D32 /* DataTypes.h */ = {isa = PBXFileReference; fileEncoding = 30; lastKnownFileType = sourcecode.c.h; path = DataTypes.h; sourceTree = "<group>"; };
 		DE66F27908ABF03200323D32 /* DataTypes.h.in */ = {isa = PBXFileReference; fileEncoding = 30; lastKnownFileType = text; path = DataTypes.h.in; sourceTree = "<group>"; };
 		DE66F27A08ABF03200323D32 /* Debug.h */ = {isa = PBXFileReference; fileEncoding = 30; lastKnownFileType = sourcecode.c.h; path = Debug.h; sourceTree = "<group>"; };
 		DE66F27B08ABF03200323D32 /* DOTGraphTraits.h */ = {isa = PBXFileReference; fileEncoding = 30; lastKnownFileType = sourcecode.c.h; path = DOTGraphTraits.h; sourceTree = "<group>"; };
@@ -681,6 +703,7 @@
 		DE66F28A08ABF03200323D32 /* SlowOperationInformer.h */ = {isa = PBXFileReference; fileEncoding = 30; lastKnownFileType = sourcecode.c.h; path = SlowOperationInformer.h; sourceTree = "<group>"; };
 		DE66F28B08ABF03200323D32 /* StableBasicBlockNumbering.h */ = {isa = PBXFileReference; fileEncoding = 30; lastKnownFileType = sourcecode.c.h; path = StableBasicBlockNumbering.h; sourceTree = "<group>"; };
 		DE66F28C08ABF03200323D32 /* SystemUtils.h */ = {isa = PBXFileReference; fileEncoding = 30; lastKnownFileType = sourcecode.c.h; path = SystemUtils.h; sourceTree = "<group>"; };
+		DE66F28D08ABF03200323D32 /* ThreadSupport.h */ = {isa = PBXFileReference; fileEncoding = 30; lastKnownFileType = sourcecode.c.h; path = ThreadSupport.h; sourceTree = "<group>"; };
 		DE66F28E08ABF03200323D32 /* Timer.h */ = {isa = PBXFileReference; fileEncoding = 30; lastKnownFileType = sourcecode.c.h; path = Timer.h; sourceTree = "<group>"; };
 		DE66F28F08ABF03200323D32 /* ToolRunner.h */ = {isa = PBXFileReference; fileEncoding = 30; lastKnownFileType = sourcecode.c.h; path = ToolRunner.h; sourceTree = "<group>"; };
 		DE66F29008ABF03200323D32 /* type_traits.h */ = {isa = PBXFileReference; fileEncoding = 30; lastKnownFileType = sourcecode.c.h; path = type_traits.h; sourceTree = "<group>"; };
@@ -760,6 +783,7 @@
 		DE66F36908ABF14500323D32 /* c */ = {isa = PBXFileReference; fileEncoding = 30; lastKnownFileType = text; path = c; sourceTree = "<group>"; };
 		DE66F36A08ABF14500323D32 /* CompilerDriver.cpp */ = {isa = PBXFileReference; fileEncoding = 30; lastKnownFileType = sourcecode.cpp.cpp; path = CompilerDriver.cpp; sourceTree = "<group>"; };
 		DE66F36B08ABF14500323D32 /* CompilerDriver.h */ = {isa = PBXFileReference; fileEncoding = 30; lastKnownFileType = sourcecode.c.h; path = CompilerDriver.h; sourceTree = "<group>"; };
+		DE66F36C08ABF14500323D32 /* ConfigLexer.cpp */ = {isa = PBXFileReference; fileEncoding = 30; lastKnownFileType = sourcecode.cpp.cpp; path = ConfigLexer.cpp; sourceTree = "<group>"; };
 		DE66F36D08ABF14500323D32 /* ConfigLexer.h */ = {isa = PBXFileReference; fileEncoding = 30; lastKnownFileType = sourcecode.c.h; path = ConfigLexer.h; sourceTree = "<group>"; };
 		DE66F36E08ABF14500323D32 /* ConfigLexer.l */ = {isa = PBXFileReference; fileEncoding = 30; lastKnownFileType = sourcecode.lex; path = ConfigLexer.l; sourceTree = "<group>"; };
 		DE66F36F08ABF14500323D32 /* Configuration.cpp */ = {isa = PBXFileReference; fileEncoding = 30; lastKnownFileType = sourcecode.cpp.cpp; path = Configuration.cpp; sourceTree = "<group>"; };
@@ -769,12 +793,14 @@
 		DE66F37E08ABF14500323D32 /* llvmc.cpp */ = {isa = PBXFileReference; fileEncoding = 30; lastKnownFileType = sourcecode.cpp.cpp; path = llvmc.cpp; sourceTree = "<group>"; };
 		DE66F38708ABF14500323D32 /* opt.cpp */ = {isa = PBXFileReference; fileEncoding = 30; lastKnownFileType = sourcecode.cpp.cpp; name = opt.cpp; path = opt/opt.cpp; sourceTree = "<group>"; };
 		DE66F38C08ABF35300323D32 /* CREDITS.TXT */ = {isa = PBXFileReference; fileEncoding = 30; lastKnownFileType = text; name = CREDITS.TXT; path = ../CREDITS.TXT; sourceTree = SOURCE_ROOT; };
+		DE66F38E08ABF35C00323D32 /* .cvsignore */ = {isa = PBXFileReference; fileEncoding = 30; lastKnownFileType = text; path = .cvsignore; sourceTree = "<group>"; };
 		DE66F38F08ABF35C00323D32 /* AliasAnalysis.html */ = {isa = PBXFileReference; fileEncoding = 30; lastKnownFileType = text.html; path = AliasAnalysis.html; sourceTree = "<group>"; };
 		DE66F39008ABF35C00323D32 /* Bugpoint.html */ = {isa = PBXFileReference; fileEncoding = 30; lastKnownFileType = text.html; path = Bugpoint.html; sourceTree = "<group>"; };
 		DE66F39108ABF35C00323D32 /* BytecodeFormat.html */ = {isa = PBXFileReference; fileEncoding = 30; lastKnownFileType = text.html; path = BytecodeFormat.html; sourceTree = "<group>"; };
 		DE66F39208ABF35C00323D32 /* CFEBuildInstrs.html */ = {isa = PBXFileReference; fileEncoding = 30; lastKnownFileType = text.html; path = CFEBuildInstrs.html; sourceTree = "<group>"; };
 		DE66F39308ABF35C00323D32 /* CodeGenerator.html */ = {isa = PBXFileReference; fileEncoding = 30; lastKnownFileType = text.html; path = CodeGenerator.html; sourceTree = "<group>"; };
 		DE66F39408ABF35C00323D32 /* CodingStandards.html */ = {isa = PBXFileReference; fileEncoding = 30; lastKnownFileType = text.html; path = CodingStandards.html; sourceTree = "<group>"; };
+		DE66F39608ABF35C00323D32 /* .cvsignore */ = {isa = PBXFileReference; fileEncoding = 30; lastKnownFileType = text; path = .cvsignore; sourceTree = "<group>"; };
 		DE66F39708ABF35C00323D32 /* analyze.pod */ = {isa = PBXFileReference; fileEncoding = 30; lastKnownFileType = text; path = analyze.pod; sourceTree = "<group>"; };
 		DE66F39808ABF35C00323D32 /* bugpoint.pod */ = {isa = PBXFileReference; fileEncoding = 30; lastKnownFileType = text; path = bugpoint.pod; sourceTree = "<group>"; };
 		DE66F39908ABF35C00323D32 /* gccas.pod */ = {isa = PBXFileReference; fileEncoding = 30; lastKnownFileType = text; path = gccas.pod; sourceTree = "<group>"; };
@@ -803,6 +829,7 @@
 		DE66F3B908ABF35D00323D32 /* CommandLine.html */ = {isa = PBXFileReference; fileEncoding = 30; lastKnownFileType = text.html; path = CommandLine.html; sourceTree = "<group>"; };
 		DE66F3BA08ABF35D00323D32 /* CompilerDriver.html */ = {isa = PBXFileReference; fileEncoding = 30; lastKnownFileType = text.html; path = CompilerDriver.html; sourceTree = "<group>"; };
 		DE66F3BB08ABF35D00323D32 /* CompilerWriterInfo.html */ = {isa = PBXFileReference; fileEncoding = 30; lastKnownFileType = text.html; path = CompilerWriterInfo.html; sourceTree = "<group>"; };
+		DE66F3BC08ABF35D00323D32 /* doxygen.cfg */ = {isa = PBXFileReference; fileEncoding = 30; lastKnownFileType = text; path = doxygen.cfg; sourceTree = "<group>"; };
 		DE66F3BD08ABF35D00323D32 /* doxygen.cfg.in */ = {isa = PBXFileReference; fileEncoding = 30; lastKnownFileType = text; path = doxygen.cfg.in; sourceTree = "<group>"; };
 		DE66F3BE08ABF35D00323D32 /* doxygen.css */ = {isa = PBXFileReference; fileEncoding = 30; lastKnownFileType = text; path = doxygen.css; sourceTree = "<group>"; };
 		DE66F3BF08ABF35D00323D32 /* doxygen.footer */ = {isa = PBXFileReference; fileEncoding = 30; lastKnownFileType = text; path = doxygen.footer; sourceTree = "<group>"; };
@@ -1278,6 +1305,7 @@
 				DE66EEA508ABEE5E00323D32 /* AlphaInstrInfo.h */,
 				DE66EEA608ABEE5E00323D32 /* AlphaInstrInfo.td */,
 				DE66EEA708ABEE5E00323D32 /* AlphaISelPattern.cpp */,
+				DE66EEA808ABEE5E00323D32 /* AlphaISelPattern.cpp.orig */,
 				DE66EEA908ABEE5E00323D32 /* AlphaJITInfo.cpp */,
 				DE66EEAA08ABEE5E00323D32 /* AlphaJITInfo.h */,
 				DE66EEAB08ABEE5E00323D32 /* AlphaRegisterInfo.cpp */,
@@ -1325,6 +1353,7 @@
 		DE66EF1108ABEE5E00323D32 /* PowerPC */ = {
 			isa = PBXGroup;
 			children = (
+				DE66EF1208ABEE5E00323D32 /* .cvsignore */,
 				DE66EF3D08ABEE5F00323D32 /* LICENSE.TXT */,
 				DE66EF3F08ABEE5F00323D32 /* PowerPC.h */,
 				DE66EF4008ABEE5F00323D32 /* PowerPC.td */,
@@ -1355,7 +1384,15 @@
 				DE66EF6008ABEE5F00323D32 /* PPC32Relocations.h */,
 				DE66EF6108ABEE5F00323D32 /* PPC32TargetMachine.h */,
 				DE66EF6208ABEE5F00323D32 /* PPC64.td */,
+				DE66EF6308ABEE5F00323D32 /* PPC64CodeEmitter.cpp */,
+				DE66EF6708ABEE5F00323D32 /* PPC64InstrInfo.cpp */,
+				DE66EF6808ABEE5F00323D32 /* PPC64InstrInfo.h */,
+				DE66EF6908ABEE5F00323D32 /* PPC64ISelPattern.cpp */,
+				DE66EF6A08ABEE5F00323D32 /* PPC64JITInfo.h */,
+				DE66EF6B08ABEE5F00323D32 /* PPC64RegisterInfo.cpp */,
+				DE66EF6C08ABEE5F00323D32 /* PPC64RegisterInfo.h */,
 				DE66EF6D08ABEE5F00323D32 /* PPC64RegisterInfo.td */,
+				DE66EF6E08ABEE5F00323D32 /* PPC64TargetMachine.h */,
 				DE66EF6F08ABEE5F00323D32 /* README.txt */,
 			);
 			path = PowerPC;
@@ -1364,6 +1401,7 @@
 		DE66EF7008ABEE5F00323D32 /* Skeleton */ = {
 			isa = PBXGroup;
 			children = (
+				DE66EF7108ABEE5F00323D32 /* .cvsignore */,
 				DE66EF8208ABEE5F00323D32 /* README.txt */,
 				DE66EF8308ABEE5F00323D32 /* Skeleton.h */,
 				DE66EF8408ABEE5F00323D32 /* Skeleton.td */,
@@ -1414,6 +1452,7 @@
 				DE66F00F08ABEE6000323D32 /* LiveVar */,
 				DE66F02608ABEE6000323D32 /* ModuloScheduling */,
 				DE66F04608ABEE6000323D32 /* RegAlloc */,
+				DE66EFCA08ABEE5F00323D32 /* .cvsignore */,
 				DE66EFFA08ABEE6000323D32 /* DecomposeMultiDimRefs.cpp */,
 				DE66EFFB08ABEE6000323D32 /* EmitBytecodeToAssembly.cpp */,
 				DE66F00E08ABEE6000323D32 /* InternalGlobalMapper.cpp */,
@@ -1425,6 +1464,9 @@
 				DE66F02408ABEE6000323D32 /* MappingInfo.cpp */,
 				DE66F02508ABEE6000323D32 /* MappingInfo.h */,
 				DE66F06208ABEE6000323D32 /* SparcV9.burg.in */,
+				DE66F06308ABEE6000323D32 /* SparcV9.burg.in1 */,
+				DE66F06408ABEE6000323D32 /* SparcV9.burm */,
+				DE66F06508ABEE6000323D32 /* SparcV9.burm.cpp */,
 				DE66F06608ABEE6000323D32 /* SparcV9.td */,
 				DE66F06708ABEE6000323D32 /* SparcV9_F2.td */,
 				DE66F06808ABEE6000323D32 /* SparcV9_F3.td */,
@@ -1534,6 +1576,7 @@
 		DE66F09308ABEE6000323D32 /* X86 */ = {
 			isa = PBXGroup;
 			children = (
+				DE66F09408ABEE6000323D32 /* .cvsignore */,
 				DE66F0BC08ABEE6000323D32 /* X86.h */,
 				DE66F0BD08ABEE6000323D32 /* X86.td */,
 				DE66F0BE08ABEE6000323D32 /* X86AsmPrinter.cpp */,
@@ -1550,6 +1593,7 @@
 				DE66F0D008ABEE6100323D32 /* X86IntelAsmPrinter.cpp */,
 				DE66F0D108ABEE6100323D32 /* X86IntelAsmPrinter.h */,
 				DE66F0D208ABEE6100323D32 /* X86ISelPattern.cpp */,
+				DE66F0D308ABEE6100323D32 /* X86ISelPattern.cpp.orig */,
 				DE66F0D408ABEE6100323D32 /* X86ISelSimple.cpp */,
 				DE66F0D508ABEE6100323D32 /* X86JITInfo.cpp */,
 				DE66F0D608ABEE6100323D32 /* X86JITInfo.h */,
@@ -1749,6 +1793,7 @@
 		DE66F1EB08ABF03100323D32 /* ADT */ = {
 			isa = PBXGroup;
 			children = (
+				DE66F1EC08ABF03100323D32 /* .cvsignore */,
 				DE66F1ED08ABF03100323D32 /* BitSetVector.h */,
 				DE66F1EE08ABF03100323D32 /* DenseMap.h */,
 				DE66F1EF08ABF03100323D32 /* DepthFirstIterator.h */,
@@ -1878,7 +1923,9 @@
 		DE66F24C08ABF03100323D32 /* Config */ = {
 			isa = PBXGroup;
 			children = (
+				DE66F24D08ABF03100323D32 /* .cvsignore */,
 				DE66F24E08ABF03100323D32 /* alloca.h */,
+				DE66F24F08ABF03100323D32 /* config.h */,
 				DE66F25008ABF03100323D32 /* config.h.in */,
 			);
 			path = Config;
@@ -1909,6 +1956,7 @@
 		DE66F26E08ABF03200323D32 /* Support */ = {
 			isa = PBXGroup;
 			children = (
+				DE66F26F08ABF03200323D32 /* .cvsignore */,
 				DE66F27008ABF03200323D32 /* AIXDataTypesFix.h */,
 				DE66F27108ABF03200323D32 /* Annotation.h */,
 				DE66F27208ABF03200323D32 /* CallSite.h */,
@@ -1917,6 +1965,7 @@
 				DE66F27508ABF03200323D32 /* CommandLine.h */,
 				DE66F27608ABF03200323D32 /* Compressor.h */,
 				DE66F27708ABF03200323D32 /* ConstantRange.h */,
+				DE66F27808ABF03200323D32 /* DataTypes.h */,
 				DE66F27908ABF03200323D32 /* DataTypes.h.in */,
 				DE66F27A08ABF03200323D32 /* Debug.h */,
 				DE66F27B08ABF03200323D32 /* DOTGraphTraits.h */,
@@ -1937,6 +1986,7 @@
 				DE66F28A08ABF03200323D32 /* SlowOperationInformer.h */,
 				DE66F28B08ABF03200323D32 /* StableBasicBlockNumbering.h */,
 				DE66F28C08ABF03200323D32 /* SystemUtils.h */,
+				DE66F28D08ABF03200323D32 /* ThreadSupport.h */,
 				DE66F28E08ABF03200323D32 /* Timer.h */,
 				DE66F28F08ABF03200323D32 /* ToolRunner.h */,
 				DE66F29008ABF03200323D32 /* type_traits.h */,
@@ -2096,6 +2146,7 @@
 				DE66F36908ABF14500323D32 /* c */,
 				DE66F36A08ABF14500323D32 /* CompilerDriver.cpp */,
 				DE66F36B08ABF14500323D32 /* CompilerDriver.h */,
+				DE66F36C08ABF14500323D32 /* ConfigLexer.cpp */,
 				DE66F36D08ABF14500323D32 /* ConfigLexer.h */,
 				DE66F36E08ABF14500323D32 /* ConfigLexer.l */,
 				DE66F36F08ABF14500323D32 /* Configuration.cpp */,
@@ -2110,6 +2161,7 @@
 		DE66F38D08ABF35C00323D32 /* docs */ = {
 			isa = PBXGroup;
 			children = (
+				DE66F38E08ABF35C00323D32 /* .cvsignore */,
 				DE66F38F08ABF35C00323D32 /* AliasAnalysis.html */,
 				DE66F39008ABF35C00323D32 /* Bugpoint.html */,
 				DE66F39108ABF35C00323D32 /* BytecodeFormat.html */,
@@ -2120,6 +2172,7 @@
 				DE66F3B908ABF35D00323D32 /* CommandLine.html */,
 				DE66F3BA08ABF35D00323D32 /* CompilerDriver.html */,
 				DE66F3BB08ABF35D00323D32 /* CompilerWriterInfo.html */,
+				DE66F3BC08ABF35D00323D32 /* doxygen.cfg */,
 				DE66F3BD08ABF35D00323D32 /* doxygen.cfg.in */,
 				DE66F3BE08ABF35D00323D32 /* doxygen.css */,
 				DE66F3BF08ABF35D00323D32 /* doxygen.footer */,
@@ -2157,6 +2210,7 @@
 		DE66F39508ABF35C00323D32 /* CommandGuide */ = {
 			isa = PBXGroup;
 			children = (
+				DE66F39608ABF35C00323D32 /* .cvsignore */,
 				DE66F39708ABF35C00323D32 /* analyze.pod */,
 				DE66F39808ABF35C00323D32 /* bugpoint.pod */,
 				DE66F39908ABF35C00323D32 /* gccas.pod */,
@@ -2216,7 +2270,7 @@
 /* Begin PBXLegacyTarget section */
 		D28A88AD04BDD90700651E21 /* LLVM */ = {
 			isa = PBXLegacyTarget;
-			buildArgumentsString = "-j 4 $(ACTION)";
+			buildArgumentsString = "$(ACTION)";
 			buildConfigurationList = DE66EC4C08ABE78900323D32 /* Build configuration list for PBXLegacyTarget "LLVM" */;
 			buildPhases = (
 			);
@@ -2226,11 +2280,11 @@
 				PRODUCT_NAME = LLVM;
 			};
 			buildToolPath = /usr/bin/make;
-			buildWorkingDirectory = /llvm/obj;
+			buildWorkingDirectory = ..;
 			dependencies = (
 			);
 			name = LLVM;
-			passBuildSettingsInEnvironment = 0;
+			passBuildSettingsInEnvironment = 1;
 			productName = LLVM;
 		};
 /* End PBXLegacyTarget section */





From jlaskey at apple.com  Wed Aug 17 19:00:31 2005
From: jlaskey at apple.com (Jim Laskey)
Date: Wed, 17 Aug 2005 21:00:31 -0300
Subject: [llvm-commits] CVS: llvm/Xcode/LLVM.xcodeproj/project.pbxproj
In-Reply-To: <200508172357.SAA15578@zion.cs.uiuc.edu>
References: <200508172357.SAA15578@zion.cs.uiuc.edu>
Message-ID: <01A8BCD6-77EC-4E85-8F9C-4CCC66B386F6@apple.com>

Old habits die hard.  This is a revert of the previous change to llvm/ 
Xcode/LLVM.xcodeproj.

-- Jim



On Aug 17, 2005, at 8:57 PM, Jim Laskey wrote:

>
>
> Changes in directory llvm/Xcode/LLVM.xcodeproj:
>
> project.pbxproj updated: 1.2 -> 1.3
> ---
> Log message:
>
> messed up
>
> ---
> Diffs of the changes:  (+57 -3)
>
>  project.pbxproj |   60 ++++++++++++++++++++++++++++++++++++++++++++ 
> +++++++++---
>  1 files changed, 57 insertions(+), 3 deletions(-)
>
>
> Index: llvm/Xcode/LLVM.xcodeproj/project.pbxproj
> diff -u llvm/Xcode/LLVM.xcodeproj/project.pbxproj:1.2 llvm/Xcode/ 
> LLVM.xcodeproj/project.pbxproj:1.3
> --- llvm/Xcode/LLVM.xcodeproj/project.pbxproj:1.2    Wed Aug 17  
> 18:54:12 2005
> +++ llvm/Xcode/LLVM.xcodeproj/project.pbxproj    Wed Aug 17  
> 18:57:24 2005
> @@ -238,6 +238,7 @@
>          DE66EEA508ABEE5E00323D32 /* AlphaInstrInfo.h */ = {isa =  
> PBXFileReference; fileEncoding = 30; lastKnownFileType =  
> sourcecode.c.h; path = AlphaInstrInfo.h; sourceTree = "<group>"; };
>          DE66EEA608ABEE5E00323D32 /* AlphaInstrInfo.td */ = {isa =  
> PBXFileReference; fileEncoding = 30; lastKnownFileType = text; path  
> = AlphaInstrInfo.td; sourceTree = "<group>"; };
>          DE66EEA708ABEE5E00323D32 /* AlphaISelPattern.cpp */ = {isa  
> = PBXFileReference; fileEncoding = 30; lastKnownFileType =  
> sourcecode.cpp.cpp; path = AlphaISelPattern.cpp; sourceTree =  
> "<group>"; };
> +        DE66EEA808ABEE5E00323D32 /* AlphaISelPattern.cpp.orig */ =  
> {isa = PBXFileReference; fileEncoding = 30; lastKnownFileType =  
> text; path = AlphaISelPattern.cpp.orig; sourceTree = "<group>"; };
>          DE66EEA908ABEE5E00323D32 /* AlphaJITInfo.cpp */ = {isa =  
> PBXFileReference; fileEncoding = 30; lastKnownFileType =  
> sourcecode.cpp.cpp; path = AlphaJITInfo.cpp; sourceTree =  
> "<group>"; };
>          DE66EEAA08ABEE5E00323D32 /* AlphaJITInfo.h */ = {isa =  
> PBXFileReference; fileEncoding = 30; lastKnownFileType =  
> sourcecode.c.h; path = AlphaJITInfo.h; sourceTree = "<group>"; };
>          DE66EEAB08ABEE5E00323D32 /* AlphaRegisterInfo.cpp */ =  
> {isa = PBXFileReference; fileEncoding = 30; lastKnownFileType =  
> sourcecode.cpp.cpp; path = AlphaRegisterInfo.cpp; sourceTree =  
> "<group>"; };
> @@ -265,6 +266,7 @@
>          DE66EF0C08ABEE5E00323D32 /* IA64TargetMachine.h */ = {isa  
> = PBXFileReference; fileEncoding = 30; lastKnownFileType =  
> sourcecode.c.h; path = IA64TargetMachine.h; sourceTree = "<group>"; };
>          DE66EF0E08ABEE5E00323D32 /* README */ = {isa =  
> PBXFileReference; fileEncoding = 30; lastKnownFileType = text; path  
> = README; sourceTree = "<group>"; };
>          DE66EF1008ABEE5E00323D32 /* MRegisterInfo.cpp */ = {isa =  
> PBXFileReference; fileEncoding = 30; lastKnownFileType =  
> sourcecode.cpp.cpp; path = MRegisterInfo.cpp; sourceTree =  
> "<group>"; };
> +        DE66EF1208ABEE5E00323D32 /* .cvsignore */ = {isa =  
> PBXFileReference; fileEncoding = 30; lastKnownFileType = text; path  
> = .cvsignore; sourceTree = "<group>"; };
>          DE66EF3D08ABEE5F00323D32 /* LICENSE.TXT */ = {isa =  
> PBXFileReference; fileEncoding = 30; lastKnownFileType = text; path  
> = LICENSE.TXT; sourceTree = "<group>"; };
>          DE66EF3F08ABEE5F00323D32 /* PowerPC.h */ = {isa =  
> PBXFileReference; fileEncoding = 30; lastKnownFileType =  
> sourcecode.c.h; path = PowerPC.h; sourceTree = "<group>"; };
>          DE66EF4008ABEE5F00323D32 /* PowerPC.td */ = {isa =  
> PBXFileReference; fileEncoding = 30; lastKnownFileType = text; path  
> = PowerPC.td; sourceTree = "<group>"; };
> @@ -295,8 +297,17 @@
>          DE66EF6008ABEE5F00323D32 /* PPC32Relocations.h */ = {isa =  
> PBXFileReference; fileEncoding = 30; lastKnownFileType =  
> sourcecode.c.h; path = PPC32Relocations.h; sourceTree = "<group>"; };
>          DE66EF6108ABEE5F00323D32 /* PPC32TargetMachine.h */ = {isa  
> = PBXFileReference; fileEncoding = 30; lastKnownFileType =  
> sourcecode.c.h; path = PPC32TargetMachine.h; sourceTree =  
> "<group>"; };
>          DE66EF6208ABEE5F00323D32 /* PPC64.td */ = {isa =  
> PBXFileReference; fileEncoding = 30; lastKnownFileType = text; path  
> = PPC64.td; sourceTree = "<group>"; };
> +        DE66EF6308ABEE5F00323D32 /* PPC64CodeEmitter.cpp */ = {isa  
> = PBXFileReference; fileEncoding = 30; lastKnownFileType =  
> sourcecode.cpp.cpp; path = PPC64CodeEmitter.cpp; sourceTree =  
> "<group>"; };
> +        DE66EF6708ABEE5F00323D32 /* PPC64InstrInfo.cpp */ = {isa =  
> PBXFileReference; fileEncoding = 30; lastKnownFileType =  
> sourcecode.cpp.cpp; path = PPC64InstrInfo.cpp; sourceTree =  
> "<group>"; };
> +        DE66EF6808ABEE5F00323D32 /* PPC64InstrInfo.h */ = {isa =  
> PBXFileReference; fileEncoding = 30; lastKnownFileType =  
> sourcecode.c.h; path = PPC64InstrInfo.h; sourceTree = "<group>"; };
> +        DE66EF6908ABEE5F00323D32 /* PPC64ISelPattern.cpp */ = {isa  
> = PBXFileReference; fileEncoding = 30; lastKnownFileType =  
> sourcecode.cpp.cpp; path = PPC64ISelPattern.cpp; sourceTree =  
> "<group>"; };
> +        DE66EF6A08ABEE5F00323D32 /* PPC64JITInfo.h */ = {isa =  
> PBXFileReference; fileEncoding = 30; lastKnownFileType =  
> sourcecode.c.h; path = PPC64JITInfo.h; sourceTree = "<group>"; };
> +        DE66EF6B08ABEE5F00323D32 /* PPC64RegisterInfo.cpp */ =  
> {isa = PBXFileReference; fileEncoding = 30; lastKnownFileType =  
> sourcecode.cpp.cpp; path = PPC64RegisterInfo.cpp; sourceTree =  
> "<group>"; };
> +        DE66EF6C08ABEE5F00323D32 /* PPC64RegisterInfo.h */ = {isa  
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>          DE66EF8208ABEE5F00323D32 /* README.txt */ = {isa =  
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>          DE66EFFA08ABEE6000323D32 /* DecomposeMultiDimRefs.cpp */ =  
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> @@ -379,6 +391,9 @@
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> = SparcV9.burg.in; sourceTree = "<group>"; };
> +        DE66F06308ABEE6000323D32 /* SparcV9.burg.in1 */ = {isa =  
> PBXFileReference; fileEncoding = 30; lastKnownFileType = text; path  
> = SparcV9.burg.in1; sourceTree = "<group>"; };
> +        DE66F06408ABEE6000323D32 /* SparcV9.burm */ = {isa =  
> PBXFileReference; fileEncoding = 30; lastKnownFileType = text; path  
> = SparcV9.burm; sourceTree = "<group>"; };
> +        DE66F06508ABEE6000323D32 /* SparcV9.burm.cpp */ = {isa =  
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>          DE66F06808ABEE6000323D32 /* SparcV9_F3.td */ = {isa =  
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>          DE66F09208ABEE6000323D32 /* TargetSubtarget.cpp */ = {isa  
> = PBXFileReference; fileEncoding = 30; lastKnownFileType =  
> sourcecode.cpp.cpp; path = TargetSubtarget.cpp; sourceTree =  
> "<group>"; };
> +        DE66F09408ABEE6000323D32 /* .cvsignore */ = {isa =  
> PBXFileReference; fileEncoding = 30; lastKnownFileType = text; path  
> = .cvsignore; sourceTree = "<group>"; };
>          DE66F0BC08ABEE6000323D32 /* X86.h */ = {isa =  
> PBXFileReference; fileEncoding = 30; lastKnownFileType =  
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>          DE66F0BD08ABEE6000323D32 /* X86.td */ = {isa =  
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>          DE66F0BE08ABEE6000323D32 /* X86AsmPrinter.cpp */ = {isa =  
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> sourcecode.cpp.cpp; path = X86AsmPrinter.cpp; sourceTree =  
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> @@ -439,6 +455,7 @@
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> PBXFileReference; fileEncoding = 30; lastKnownFileType =  
> sourcecode.cpp.cpp; path = X86ISelPattern.cpp; sourceTree =  
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> PBXFileReference; fileEncoding = 30; lastKnownFileType =  
> sourcecode.c.h; path = AbstractTypeUser.h; sourceTree = "<group>"; };
> +        DE66F1EC08ABF03100323D32 /* .cvsignore */ = {isa =  
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>          DE66F1ED08ABF03100323D32 /* BitSetVector.h */ = {isa =  
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>          DE66F1EE08ABF03100323D32 /* DenseMap.h */ = {isa =  
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>          DE66F1EF08ABF03100323D32 /* DepthFirstIterator.h */ = {isa  
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> sourcecode.c.h; path = DepthFirstIterator.h; sourceTree =  
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> @@ -624,7 +642,9 @@
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>          DE66F24B08ABF03100323D32 /* ValueTypes.h */ = {isa =  
> PBXFileReference; fileEncoding = 30; lastKnownFileType =  
> sourcecode.c.h; path = ValueTypes.h; sourceTree = "<group>"; };
> +        DE66F24D08ABF03100323D32 /* .cvsignore */ = {isa =  
> PBXFileReference; fileEncoding = 30; lastKnownFileType = text; path  
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>          DE66F24E08ABF03100323D32 /* alloca.h */ = {isa =  
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> sourcecode.c.h; path = alloca.h; sourceTree = "<group>"; };
> +        DE66F24F08ABF03100323D32 /* config.h */ = {isa =  
> PBXFileReference; fileEncoding = 30; lastKnownFileType =  
> sourcecode.c.h; path = config.h; sourceTree = "<group>"; };
>          DE66F25008ABF03100323D32 /* config.h.in */ = {isa =  
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> @@ -653,6 +673,7 @@
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> PBXFileReference; fileEncoding = 30; lastKnownFileType =  
> sourcecode.c.h; path = PassSupport.h; sourceTree = "<group>"; };
> +        DE66F26F08ABF03200323D32 /* .cvsignore */ = {isa =  
> PBXFileReference; fileEncoding = 30; lastKnownFileType = text; path  
> = .cvsignore; sourceTree = "<group>"; };
>          DE66F27008ABF03200323D32 /* AIXDataTypesFix.h */ = {isa =  
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>          DE66F27108ABF03200323D32 /* Annotation.h */ = {isa =  
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>          DE66F27208ABF03200323D32 /* CallSite.h */ = {isa =  
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> @@ -661,6 +682,7 @@
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>          DE66F27608ABF03200323D32 /* Compressor.h */ = {isa =  
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>          DE66F27708ABF03200323D32 /* ConstantRange.h */ = {isa =  
> PBXFileReference; fileEncoding = 30; lastKnownFileType =  
> sourcecode.c.h; path = ConstantRange.h; sourceTree = "<group>"; };
> +        DE66F27808ABF03200323D32 /* DataTypes.h */ = {isa =  
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>          DE66F27908ABF03200323D32 /* DataTypes.h.in */ = {isa =  
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>          DE66F27A08ABF03200323D32 /* Debug.h */ = {isa =  
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>          DE66F27B08ABF03200323D32 /* DOTGraphTraits.h */ = {isa =  
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> @@ -681,6 +703,7 @@
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>          DE66F28B08ABF03200323D32 /* StableBasicBlockNumbering.h */  
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> PBXFileReference; fileEncoding = 30; lastKnownFileType =  
> sourcecode.c.h; path = SystemUtils.h; sourceTree = "<group>"; };
> +        DE66F28D08ABF03200323D32 /* ThreadSupport.h */ = {isa =  
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>          DE66F36B08ABF14500323D32 /* CompilerDriver.h */ = {isa =  
> PBXFileReference; fileEncoding = 30; lastKnownFileType =  
> sourcecode.c.h; path = CompilerDriver.h; sourceTree = "<group>"; };
> +        DE66F36C08ABF14500323D32 /* ConfigLexer.cpp */ = {isa =  
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> sourcecode.cpp.cpp; path = ConfigLexer.cpp; sourceTree = "<group>"; };
>          DE66F36D08ABF14500323D32 /* ConfigLexer.h */ = {isa =  
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> @@ -769,12 +793,14 @@
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> PBXFileReference; fileEncoding = 30; lastKnownFileType = text; name  
> = CREDITS.TXT; path = ../CREDITS.TXT; sourceTree = SOURCE_ROOT; };
> +        DE66F38E08ABF35C00323D32 /* .cvsignore */ = {isa =  
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>          DE66F39408ABF35C00323D32 /* CodingStandards.html */ = {isa  
> = PBXFileReference; fileEncoding = 30; lastKnownFileType =  
> text.html; path = CodingStandards.html; sourceTree = "<group>"; };
> +        DE66F39608ABF35C00323D32 /* .cvsignore */ = {isa =  
> PBXFileReference; fileEncoding = 30; lastKnownFileType = text; path  
> = .cvsignore; sourceTree = "<group>"; };
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>          DE66F3BB08ABF35D00323D32 /* CompilerWriterInfo.html */ =  
> {isa = PBXFileReference; fileEncoding = 30; lastKnownFileType =  
> text.html; path = CompilerWriterInfo.html; sourceTree = "<group>"; };
> +        DE66F3BC08ABF35D00323D32 /* doxygen.cfg */ = {isa =  
> PBXFileReference; fileEncoding = 30; lastKnownFileType = text; path  
> = doxygen.cfg; sourceTree = "<group>"; };
>          DE66F3BD08ABF35D00323D32 /* doxygen.cfg.in */ = {isa =  
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>                  DE66EEA608ABEE5E00323D32 /* AlphaInstrInfo.td */,
>                  DE66EEA708ABEE5E00323D32 /* AlphaISelPattern.cpp */,
> +                DE66EEA808ABEE5E00323D32 /*  
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>                  DE66EEA908ABEE5E00323D32 /* AlphaJITInfo.cpp */,
>                  DE66EEAA08ABEE5E00323D32 /* AlphaJITInfo.h */,
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> @@ -1325,6 +1353,7 @@
>          DE66EF1108ABEE5E00323D32 /* PowerPC */ = {
>              isa = PBXGroup;
>              children = (
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>                  DE66EF3D08ABEE5F00323D32 /* LICENSE.TXT */,
>                  DE66EF3F08ABEE5F00323D32 /* PowerPC.h */,
>                  DE66EF4008ABEE5F00323D32 /* PowerPC.td */,
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>                  DE66EF6108ABEE5F00323D32 /* PPC32TargetMachine.h */,
>                  DE66EF6208ABEE5F00323D32 /* PPC64.td */,
> +                DE66EF6308ABEE5F00323D32 /* PPC64CodeEmitter.cpp */,
> +                DE66EF6708ABEE5F00323D32 /* PPC64InstrInfo.cpp */,
> +                DE66EF6808ABEE5F00323D32 /* PPC64InstrInfo.h */,
> +                DE66EF6908ABEE5F00323D32 /* PPC64ISelPattern.cpp */,
> +                DE66EF6A08ABEE5F00323D32 /* PPC64JITInfo.h */,
> +                DE66EF6B08ABEE5F00323D32 /* PPC64RegisterInfo.cpp */,
> +                DE66EF6C08ABEE5F00323D32 /* PPC64RegisterInfo.h */,
>                  DE66EF6D08ABEE5F00323D32 /* PPC64RegisterInfo.td */,
> +                DE66EF6E08ABEE5F00323D32 /* PPC64TargetMachine.h */,
>                  DE66EF6F08ABEE5F00323D32 /* README.txt */,
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>              path = PowerPC;
> @@ -1364,6 +1401,7 @@
>          DE66EF7008ABEE5F00323D32 /* Skeleton */ = {
>              isa = PBXGroup;
>              children = (
> +                DE66EF7108ABEE5F00323D32 /* .cvsignore */,
>                  DE66EF8208ABEE5F00323D32 /* README.txt */,
>                  DE66EF8308ABEE5F00323D32 /* Skeleton.h */,
>                  DE66EF8408ABEE5F00323D32 /* Skeleton.td */,
> @@ -1414,6 +1452,7 @@
>                  DE66F00F08ABEE6000323D32 /* LiveVar */,
>                  DE66F02608ABEE6000323D32 /* ModuloScheduling */,
>                  DE66F04608ABEE6000323D32 /* RegAlloc */,
> +                DE66EFCA08ABEE5F00323D32 /* .cvsignore */,
>                  DE66EFFA08ABEE6000323D32 /*  
> DecomposeMultiDimRefs.cpp */,
>                  DE66EFFB08ABEE6000323D32 /*  
> EmitBytecodeToAssembly.cpp */,
>                  DE66F00E08ABEE6000323D32 /*  
> InternalGlobalMapper.cpp */,
> @@ -1425,6 +1464,9 @@
>                  DE66F02408ABEE6000323D32 /* MappingInfo.cpp */,
>                  DE66F02508ABEE6000323D32 /* MappingInfo.h */,
>                  DE66F06208ABEE6000323D32 /* SparcV9.burg.in */,
> +                DE66F06308ABEE6000323D32 /* SparcV9.burg.in1 */,
> +                DE66F06408ABEE6000323D32 /* SparcV9.burm */,
> +                DE66F06508ABEE6000323D32 /* SparcV9.burm.cpp */,
>                  DE66F06608ABEE6000323D32 /* SparcV9.td */,
>                  DE66F06708ABEE6000323D32 /* SparcV9_F2.td */,
>                  DE66F06808ABEE6000323D32 /* SparcV9_F3.td */,
> @@ -1534,6 +1576,7 @@
>          DE66F09308ABEE6000323D32 /* X86 */ = {
>              isa = PBXGroup;
>              children = (
> +                DE66F09408ABEE6000323D32 /* .cvsignore */,
>                  DE66F0BC08ABEE6000323D32 /* X86.h */,
>                  DE66F0BD08ABEE6000323D32 /* X86.td */,
>                  DE66F0BE08ABEE6000323D32 /* X86AsmPrinter.cpp */,
> @@ -1550,6 +1593,7 @@
>                  DE66F0D008ABEE6100323D32 /* X86IntelAsmPrinter.cpp  
> */,
>                  DE66F0D108ABEE6100323D32 /* X86IntelAsmPrinter.h */,
>                  DE66F0D208ABEE6100323D32 /* X86ISelPattern.cpp */,
> +                DE66F0D308ABEE6100323D32 /*  
> X86ISelPattern.cpp.orig */,
>                  DE66F0D408ABEE6100323D32 /* X86ISelSimple.cpp */,
>                  DE66F0D508ABEE6100323D32 /* X86JITInfo.cpp */,
>                  DE66F0D608ABEE6100323D32 /* X86JITInfo.h */,
> @@ -1749,6 +1793,7 @@
>          DE66F1EB08ABF03100323D32 /* ADT */ = {
>              isa = PBXGroup;
>              children = (
> +                DE66F1EC08ABF03100323D32 /* .cvsignore */,
>                  DE66F1ED08ABF03100323D32 /* BitSetVector.h */,
>                  DE66F1EE08ABF03100323D32 /* DenseMap.h */,
>                  DE66F1EF08ABF03100323D32 /* DepthFirstIterator.h */,
> @@ -1878,7 +1923,9 @@
>          DE66F24C08ABF03100323D32 /* Config */ = {
>              isa = PBXGroup;
>              children = (
> +                DE66F24D08ABF03100323D32 /* .cvsignore */,
>                  DE66F24E08ABF03100323D32 /* alloca.h */,
> +                DE66F24F08ABF03100323D32 /* config.h */,
>                  DE66F25008ABF03100323D32 /* config.h.in */,
>              );
>              path = Config;
> @@ -1909,6 +1956,7 @@
>          DE66F26E08ABF03200323D32 /* Support */ = {
>              isa = PBXGroup;
>              children = (
> +                DE66F26F08ABF03200323D32 /* .cvsignore */,
>                  DE66F27008ABF03200323D32 /* AIXDataTypesFix.h */,
>                  DE66F27108ABF03200323D32 /* Annotation.h */,
>                  DE66F27208ABF03200323D32 /* CallSite.h */,
> @@ -1917,6 +1965,7 @@
>                  DE66F27508ABF03200323D32 /* CommandLine.h */,
>                  DE66F27608ABF03200323D32 /* Compressor.h */,
>                  DE66F27708ABF03200323D32 /* ConstantRange.h */,
> +                DE66F27808ABF03200323D32 /* DataTypes.h */,
>                  DE66F27908ABF03200323D32 /* DataTypes.h.in */,
>                  DE66F27A08ABF03200323D32 /* Debug.h */,
>                  DE66F27B08ABF03200323D32 /* DOTGraphTraits.h */,
> @@ -1937,6 +1986,7 @@
>                  DE66F28A08ABF03200323D32 /*  
> SlowOperationInformer.h */,
>                  DE66F28B08ABF03200323D32 /*  
> StableBasicBlockNumbering.h */,
>                  DE66F28C08ABF03200323D32 /* SystemUtils.h */,
> +                DE66F28D08ABF03200323D32 /* ThreadSupport.h */,
>                  DE66F28E08ABF03200323D32 /* Timer.h */,
>                  DE66F28F08ABF03200323D32 /* ToolRunner.h */,
>                  DE66F29008ABF03200323D32 /* type_traits.h */,
> @@ -2096,6 +2146,7 @@
>                  DE66F36908ABF14500323D32 /* c */,
>                  DE66F36A08ABF14500323D32 /* CompilerDriver.cpp */,
>                  DE66F36B08ABF14500323D32 /* CompilerDriver.h */,
> +                DE66F36C08ABF14500323D32 /* ConfigLexer.cpp */,
>                  DE66F36D08ABF14500323D32 /* ConfigLexer.h */,
>                  DE66F36E08ABF14500323D32 /* ConfigLexer.l */,
>                  DE66F36F08ABF14500323D32 /* Configuration.cpp */,
> @@ -2110,6 +2161,7 @@
>          DE66F38D08ABF35C00323D32 /* docs */ = {
>              isa = PBXGroup;
>              children = (
> +                DE66F38E08ABF35C00323D32 /* .cvsignore */,
>                  DE66F38F08ABF35C00323D32 /* AliasAnalysis.html */,
>                  DE66F39008ABF35C00323D32 /* Bugpoint.html */,
>                  DE66F39108ABF35C00323D32 /* BytecodeFormat.html */,
> @@ -2120,6 +2172,7 @@
>                  DE66F3B908ABF35D00323D32 /* CommandLine.html */,
>                  DE66F3BA08ABF35D00323D32 /* CompilerDriver.html */,
>                  DE66F3BB08ABF35D00323D32 /*  
> CompilerWriterInfo.html */,
> +                DE66F3BC08ABF35D00323D32 /* doxygen.cfg */,
>                  DE66F3BD08ABF35D00323D32 /* doxygen.cfg.in */,
>                  DE66F3BE08ABF35D00323D32 /* doxygen.css */,
>                  DE66F3BF08ABF35D00323D32 /* doxygen.footer */,
> @@ -2157,6 +2210,7 @@
>          DE66F39508ABF35C00323D32 /* CommandGuide */ = {
>              isa = PBXGroup;
>              children = (
> +                DE66F39608ABF35C00323D32 /* .cvsignore */,
>                  DE66F39708ABF35C00323D32 /* analyze.pod */,
>                  DE66F39808ABF35C00323D32 /* bugpoint.pod */,
>                  DE66F39908ABF35C00323D32 /* gccas.pod */,
> @@ -2216,7 +2270,7 @@
>  /* Begin PBXLegacyTarget section */
>          D28A88AD04BDD90700651E21 /* LLVM */ = {
>              isa = PBXLegacyTarget;
> -            buildArgumentsString = "-j 4 $(ACTION)";
> +            buildArgumentsString = "$(ACTION)";
>              buildConfigurationList = DE66EC4C08ABE78900323D32 /*  
> Build configuration list for PBXLegacyTarget "LLVM" */;
>              buildPhases = (
>              );
> @@ -2226,11 +2280,11 @@
>                  PRODUCT_NAME = LLVM;
>              };
>              buildToolPath = /usr/bin/make;
> -            buildWorkingDirectory = /llvm/obj;
> +            buildWorkingDirectory = ..;
>              dependencies = (
>              );
>              name = LLVM;
> -            passBuildSettingsInEnvironment = 0;
> +            passBuildSettingsInEnvironment = 1;
>              productName = LLVM;
>          };
>  /* End PBXLegacyTarget section */
>
>
>
> _______________________________________________
> llvm-commits mailing list
> llvm-commits at cs.uiuc.edu
> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
>



From jlaskey at apple.com  Wed Aug 17 19:15:26 2005
From: jlaskey at apple.com (Jim Laskey)
Date: Wed, 17 Aug 2005 19:15:26 -0500
Subject: [llvm-commits] CVS: llvm/lib/Target/PowerPC/PPC32ISelPattern.cpp 
Message-ID: <200508180015.TAA15712@zion.cs.uiuc.edu>



Changes in directory llvm/lib/Target/PowerPC:

PPC32ISelPattern.cpp updated: 1.148 -> 1.149
---
Log message:

Better version of isIntImmediate.



---
Diffs of the changes:  (+1 -1)

 PPC32ISelPattern.cpp |    2 +-
 1 files changed, 1 insertion(+), 1 deletion(-)


Index: llvm/lib/Target/PowerPC/PPC32ISelPattern.cpp
diff -u llvm/lib/Target/PowerPC/PPC32ISelPattern.cpp:1.148 llvm/lib/Target/PowerPC/PPC32ISelPattern.cpp:1.149
--- llvm/lib/Target/PowerPC/PPC32ISelPattern.cpp:1.148	Tue Aug 16 20:25:14 2005
+++ llvm/lib/Target/PowerPC/PPC32ISelPattern.cpp	Wed Aug 17 19:15:15 2005
@@ -177,7 +177,7 @@
   // test for constant
   if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N)) {
     // retrieve value
-    Imm = (unsigned)CN->getSignExtended();
+    Imm = (unsigned)CN->getValue();
     // passes muster
     return true;
   }





From natebegeman at mac.com  Wed Aug 17 19:21:53 2005
From: natebegeman at mac.com (Nate Begeman)
Date: Wed, 17 Aug 2005 19:21:53 -0500
Subject: [llvm-commits] CVS: llvm/lib/Target/PowerPC/PPC32ISelDAGToDAG.cpp 
Message-ID: <200508180021.TAA15738@zion.cs.uiuc.edu>



Changes in directory llvm/lib/Target/PowerPC:

PPC32ISelDAGToDAG.cpp updated: 1.2 -> 1.3
---
Log message:

Be fruitful and multiply!


---
Diffs of the changes:  (+29 -0)

 PPC32ISelDAGToDAG.cpp |   29 +++++++++++++++++++++++++++++
 1 files changed, 29 insertions(+)


Index: llvm/lib/Target/PowerPC/PPC32ISelDAGToDAG.cpp
diff -u llvm/lib/Target/PowerPC/PPC32ISelDAGToDAG.cpp:1.2 llvm/lib/Target/PowerPC/PPC32ISelDAGToDAG.cpp:1.3
--- llvm/lib/Target/PowerPC/PPC32ISelDAGToDAG.cpp:1.2	Wed Aug 17 18:46:35 2005
+++ llvm/lib/Target/PowerPC/PPC32ISelDAGToDAG.cpp	Wed Aug 17 19:21:41 2005
@@ -281,6 +281,35 @@
                          Select(N->getOperand(1)));
     break;
   }
+  case ISD::MUL: {
+    unsigned Imm, Opc;
+    if (isIntImmediate(N->getOperand(1), Imm) && isInt16(Imm)) {
+      CurDAG->SelectNodeTo(N, N->getValueType(0), PPC::MULLI, 
+                           Select(N->getOperand(0)), getI32Imm(Lo16(Imm)));
+      break;
+    } 
+    switch (N->getValueType(0)) {
+      default: assert(0 && "Unhandled multiply type!");
+      case MVT::i32: Opc = PPC::MULLW; break;
+      case MVT::f32: Opc = PPC::FMULS; break;
+      case MVT::f64: Opc = PPC::FMUL;  break;
+    }
+    CurDAG->SelectNodeTo(N, N->getValueType(0), Opc, Select(N->getOperand(0)), 
+                         Select(N->getOperand(1)));
+    break;
+  }
+  case ISD::MULHS: {
+    assert(N->getValueType(0) == MVT::i32);
+    CurDAG->SelectNodeTo(N, N->getValueType(0), PPC::MULHW, 
+                         Select(N->getOperand(0)), Select(N->getOperand(1)));
+    break;
+  }
+  case ISD::MULHU: {
+    assert(N->getValueType(0) == MVT::i32);
+    CurDAG->SelectNodeTo(N, N->getValueType(0), PPC::MULHWU, 
+                         Select(N->getOperand(0)), Select(N->getOperand(1)));
+    break;
+  }
   case ISD::FNEG: {
     SDOperand Val = Select(N->getOperand(0));
     MVT::ValueType Ty = N->getValueType(0);





From natebegeman at mac.com  Wed Aug 17 19:53:59 2005
From: natebegeman at mac.com (Nate Begeman)
Date: Wed, 17 Aug 2005 19:53:59 -0500
Subject: [llvm-commits] CVS: llvm/lib/Target/PowerPC/PPC32ISelDAGToDAG.cpp 
Message-ID: <200508180053.TAA15988@zion.cs.uiuc.edu>



Changes in directory llvm/lib/Target/PowerPC:

PPC32ISelDAGToDAG.cpp updated: 1.3 -> 1.4
---
Log message:

Add a couple more nodes that are easy to handle


---
Diffs of the changes:  (+11 -0)

 PPC32ISelDAGToDAG.cpp |   11 +++++++++++
 1 files changed, 11 insertions(+)


Index: llvm/lib/Target/PowerPC/PPC32ISelDAGToDAG.cpp
diff -u llvm/lib/Target/PowerPC/PPC32ISelDAGToDAG.cpp:1.3 llvm/lib/Target/PowerPC/PPC32ISelDAGToDAG.cpp:1.4
--- llvm/lib/Target/PowerPC/PPC32ISelDAGToDAG.cpp:1.3	Wed Aug 17 19:21:41 2005
+++ llvm/lib/Target/PowerPC/PPC32ISelDAGToDAG.cpp	Wed Aug 17 19:53:47 2005
@@ -310,6 +310,11 @@
                          Select(N->getOperand(0)), Select(N->getOperand(1)));
     break;
   }
+  case ISD::FABS: {
+    CurDAG->SelectNodeTo(N, N->getValueType(0), PPC::FABS, 
+                         Select(N->getOperand(0)));
+    break;
+  }
   case ISD::FNEG: {
     SDOperand Val = Select(N->getOperand(0));
     MVT::ValueType Ty = N->getValueType(0);
@@ -338,6 +343,12 @@
     CurDAG->SelectNodeTo(N, Ty, PPC::FNEG, Val);
     break;
   }
+  case ISD::FSQRT: {
+    MVT::ValueType Ty = N->getValueType(0);
+    CurDAG->SelectNodeTo(N, Ty, Ty == MVT::f64 ? PPC::FSQRT : PPC::FSQRTS,
+                         Select(N->getOperand(0)));
+    break;
+  }
   case ISD::RET: {
     SDOperand Chain = Select(N->getOperand(0));     // Token chain.
 





From natebegeman at mac.com  Wed Aug 17 22:04:30 2005
From: natebegeman at mac.com (Nate Begeman)
Date: Wed, 17 Aug 2005 22:04:30 -0500
Subject: [llvm-commits] CVS: llvm/lib/Target/PowerPC/PPC32ISelDAGToDAG.cpp 
Message-ID: <200508180304.WAA25404@zion.cs.uiuc.edu>



Changes in directory llvm/lib/Target/PowerPC:

PPC32ISelDAGToDAG.cpp updated: 1.4 -> 1.5
---
Log message:

Add a bunch more simple nodes.


---
Diffs of the changes:  (+36 -10)

 PPC32ISelDAGToDAG.cpp |   46 ++++++++++++++++++++++++++++++++++++----------
 1 files changed, 36 insertions(+), 10 deletions(-)


Index: llvm/lib/Target/PowerPC/PPC32ISelDAGToDAG.cpp
diff -u llvm/lib/Target/PowerPC/PPC32ISelDAGToDAG.cpp:1.4 llvm/lib/Target/PowerPC/PPC32ISelDAGToDAG.cpp:1.5
--- llvm/lib/Target/PowerPC/PPC32ISelDAGToDAG.cpp:1.4	Wed Aug 17 19:53:47 2005
+++ llvm/lib/Target/PowerPC/PPC32ISelDAGToDAG.cpp	Wed Aug 17 22:04:18 2005
@@ -199,6 +199,25 @@
       break;
     }
   }
+  case ISD::SIGN_EXTEND_INREG:
+    switch(cast<VTSDNode>(N->getOperand(1))->getVT()) {
+    default: assert(0 && "Illegal type in SIGN_EXTEND_INREG"); break;
+    case MVT::i16:
+      CurDAG->SelectNodeTo(N, MVT::i32, PPC::EXTSH, Select(N->getOperand(0)));
+      break;
+    case MVT::i8:
+      CurDAG->SelectNodeTo(N, MVT::i32, PPC::EXTSB, Select(N->getOperand(0)));
+      break;
+    case MVT::i1:
+      CurDAG->SelectNodeTo(N, MVT::i32, PPC::SUBFIC, Select(N->getOperand(0)),
+                           getI32Imm(0));
+      break;
+    }
+    break;
+  case ISD::CTLZ:
+    assert(N->getValueType(0) == MVT::i32);
+    CurDAG->SelectNodeTo(N, MVT::i32, PPC::CNTLZW, Select(N->getOperand(0)));
+    break;
   case ISD::ADD: {
     MVT::ValueType Ty = N->getValueType(0);
     if (Ty == MVT::i32) {
@@ -298,23 +317,30 @@
                          Select(N->getOperand(1)));
     break;
   }
-  case ISD::MULHS: {
+  case ISD::MULHS:
     assert(N->getValueType(0) == MVT::i32);
-    CurDAG->SelectNodeTo(N, N->getValueType(0), PPC::MULHW, 
-                         Select(N->getOperand(0)), Select(N->getOperand(1)));
+    CurDAG->SelectNodeTo(N, MVT::i32, PPC::MULHW, Select(N->getOperand(0)), 
+                         Select(N->getOperand(1)));
     break;
-  }
-  case ISD::MULHU: {
+  case ISD::MULHU:
     assert(N->getValueType(0) == MVT::i32);
-    CurDAG->SelectNodeTo(N, N->getValueType(0), PPC::MULHWU, 
-                         Select(N->getOperand(0)), Select(N->getOperand(1)));
+    CurDAG->SelectNodeTo(N, MVT::i32, PPC::MULHWU, Select(N->getOperand(0)),
+                         Select(N->getOperand(1)));
     break;
-  }
-  case ISD::FABS: {
+  case ISD::FABS:
     CurDAG->SelectNodeTo(N, N->getValueType(0), PPC::FABS, 
                          Select(N->getOperand(0)));
     break;
-  }
+  case ISD::FP_EXTEND:
+    assert(MVT::f64 == N->getValueType(0) && 
+           MVT::f32 == N->getOperand(0).getValueType() && "Illegal FP_EXTEND");
+    CurDAG->SelectNodeTo(N, MVT::f64, PPC::FMR, Select(N->getOperand(0)));
+    break;
+  case ISD::FP_ROUND:
+    assert(MVT::f32 == N->getValueType(0) && 
+           MVT::f64 == N->getOperand(0).getValueType() && "Illegal FP_ROUND");
+    CurDAG->SelectNodeTo(N, MVT::f32, PPC::FRSP, Select(N->getOperand(0)));
+    break;
   case ISD::FNEG: {
     SDOperand Val = Select(N->getOperand(0));
     MVT::ValueType Ty = N->getValueType(0);





From natebegeman at mac.com  Wed Aug 17 22:11:55 2005
From: natebegeman at mac.com (Nate Begeman)
Date: Wed, 17 Aug 2005 22:11:55 -0500
Subject: [llvm-commits] CVS: llvm/test/Regression/CodeGen/PowerPC/lha.ll 
Message-ID: <200508180311.WAA25440@zion.cs.uiuc.edu>



Changes in directory llvm/test/Regression/CodeGen/PowerPC:

lha.ll added (r1.1)
---
Log message:

Add a testcase for load short -> uint, which is currently emitted as a
zextload + sign_extend_inreg rather than a sextload.


---
Diffs of the changes:  (+9 -0)

 lha.ll |    9 +++++++++
 1 files changed, 9 insertions(+)


Index: llvm/test/Regression/CodeGen/PowerPC/lha.ll
diff -c /dev/null llvm/test/Regression/CodeGen/PowerPC/lha.ll:1.1
*** /dev/null	Wed Aug 17 22:11:54 2005
--- llvm/test/Regression/CodeGen/PowerPC/lha.ll	Wed Aug 17 22:11:44 2005
***************
*** 0 ****
--- 1,9 ----
+ ; RUN: llvm-as < %s | llc -march=ppc32 | grep lha
+ ; XFAIL: *
+ 
+ uint %test(short* %a) {
+ entry:
+     %tmp.1 = load short* %a
+     %tmp.2 = cast short %tmp.1 to uint
+     ret uint %tmp.2
+ }





From sabre at nondot.org  Wed Aug 17 22:25:55 2005
From: sabre at nondot.org (Chris Lattner)
Date: Wed, 17 Aug 2005 22:25:55 -0500 (CDT)
Subject: [llvm-commits] CVS: llvm/lib/Target/PowerPC/PPC32ISelDAGToDAG.cpp
In-Reply-To: <200508180304.WAA25404@zion.cs.uiuc.edu>
References: <200508180304.WAA25404@zion.cs.uiuc.edu>
Message-ID: <Pine.LNX.4.61.0508172223040.5365@nondot.org>

On Wed, 17 Aug 2005, Nate Begeman wrote:
> +  case ISD::SIGN_EXTEND_INREG:
> +    switch(cast<VTSDNode>(N->getOperand(1))->getVT()) {
> +    default: assert(0 && "Illegal type in SIGN_EXTEND_INREG"); break;
...
> +    case MVT::i1:
> +      CurDAG->SelectNodeTo(N, MVT::i32, PPC::SUBFIC, Select(N->getOperand(0)),
> +                           getI32Imm(0));
> +      break;

BTW, I don't think this is right.  This would miscompile in the case where 
the input has a value of "2", for example (returning 0-2).  It would 
probably be better to say that this is not legal so the legalizer turns 
it into shl/sar, unless there is a way to make this work trickily.

We haven't noticed this because SEXT_INREG from a bool is not really 
possible to generate yet.

-Chris

-- 
http://nondot.org/sabre/
http://llvm.org/



From lattner at cs.uiuc.edu  Wed Aug 17 22:31:13 2005
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Wed, 17 Aug 2005 22:31:13 -0500
Subject: [llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
	SelectionDAGPrinter.cpp 
Message-ID: <200508180331.WAA25886@zion.cs.uiuc.edu>



Changes in directory llvm/lib/CodeGen/SelectionDAG:

SelectionDAG.cpp updated: 1.147 -> 1.148
SelectionDAGPrinter.cpp updated: 1.20 -> 1.21
---
Log message:

Fix printing of VTSDNodes


---
Diffs of the changes:  (+5 -0)

 SelectionDAG.cpp        |    3 +++
 SelectionDAGPrinter.cpp |    2 ++
 2 files changed, 5 insertions(+)


Index: llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp:1.147 llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp:1.148
--- llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp:1.147	Wed Aug 17 15:08:02 2005
+++ llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp	Wed Aug 17 22:31:02 2005
@@ -1891,6 +1891,7 @@
    
   case ISD::PCMARKER:      return "PCMarker";
   case ISD::SRCVALUE:      return "SrcValue";
+  case ISD::VALUETYPE:     return "ValueType";
   case ISD::EntryToken:    return "EntryToken";
   case ISD::TokenFactor:   return "TokenFactor";
   case ISD::Constant:      return "Constant";
@@ -2070,6 +2071,8 @@
       std::cerr << "<" << M->getValue() << ":" << M->getOffset() << ">";
     else
       std::cerr << "<null:" << M->getOffset() << ">";
+  } else if (const VTSDNode *N = dyn_cast<VTSDNode>(this)) {
+    std::cerr << ":" << getValueTypeString(N->getVT());
   }
 }
 


Index: llvm/lib/CodeGen/SelectionDAG/SelectionDAGPrinter.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/SelectionDAGPrinter.cpp:1.20 llvm/lib/CodeGen/SelectionDAG/SelectionDAGPrinter.cpp:1.21
--- llvm/lib/CodeGen/SelectionDAG/SelectionDAGPrinter.cpp:1.20	Tue Aug 16 16:55:35 2005
+++ llvm/lib/CodeGen/SelectionDAG/SelectionDAGPrinter.cpp	Wed Aug 17 22:31:02 2005
@@ -82,6 +82,8 @@
       Op += "<" + M->getValue()->getName() + ":" + itostr(M->getOffset()) + ">";
     else
       Op += "<null:" + itostr(M->getOffset()) + ">";
+  } else if (const VTSDNode *N = dyn_cast<VTSDNode>(Node)) {
+    std::cerr << ":" << getValueTypeString(N->getVT());
   }
   return Op;
 }





From natebegeman at mac.com  Thu Aug 18 00:00:25 2005
From: natebegeman at mac.com (Nate Begeman)
Date: Thu, 18 Aug 2005 00:00:25 -0500
Subject: [llvm-commits] CVS: llvm/lib/Target/PowerPC/PPC32ISelDAGToDAG.cpp 
Message-ID: <200508180500.AAA26317@zion.cs.uiuc.edu>



Changes in directory llvm/lib/Target/PowerPC:

PPC32ISelDAGToDAG.cpp updated: 1.5 -> 1.6
---
Log message:

Implement XOR, remove a broken sign_extend_inreg case


---
Diffs of the changes:  (+63 -4)

 PPC32ISelDAGToDAG.cpp |   67 +++++++++++++++++++++++++++++++++++++++++++++++---
 1 files changed, 63 insertions(+), 4 deletions(-)


Index: llvm/lib/Target/PowerPC/PPC32ISelDAGToDAG.cpp
diff -u llvm/lib/Target/PowerPC/PPC32ISelDAGToDAG.cpp:1.5 llvm/lib/Target/PowerPC/PPC32ISelDAGToDAG.cpp:1.6
--- llvm/lib/Target/PowerPC/PPC32ISelDAGToDAG.cpp:1.5	Wed Aug 17 22:04:18 2005
+++ llvm/lib/Target/PowerPC/PPC32ISelDAGToDAG.cpp	Thu Aug 18 00:00:13 2005
@@ -80,6 +80,29 @@
   };
 }
 
+// isIntImmediate - This method tests to see if a constant operand.
+// If so Imm will receive the 32 bit value.
+static bool isIntImmediate(SDNode *N, unsigned& Imm) {
+  if (N->getOpcode() == ISD::Constant) {
+    Imm = cast<ConstantSDNode>(N)->getValue();
+    return true;
+  }
+  return false;
+}
+
+// isOpcWithIntImmediate - This method tests to see if the node is a specific
+// opcode and that it has a immediate integer right operand.
+// If so Imm will receive the 32 bit value.
+static bool isOpcWithIntImmediate(SDNode *N, unsigned Opc, unsigned& Imm) {
+  return N->getOpcode() == Opc && isIntImmediate(N->getOperand(1).Val, Imm);
+}
+
+// isOprNot - Returns true if the specified operand is an xor with immediate -1.
+static bool isOprNot(SDNode *N) {
+  unsigned Imm;
+  return isOpcWithIntImmediate(N, ISD::XOR, Imm) && (signed)Imm == -1;
+}
+
 // Immediate constant composers.
 // Lo16 - grabs the lo 16 bits from a 32 bit constant.
 // Hi16 - grabs the hi 16 bits from a 32 bit constant.
@@ -208,10 +231,6 @@
     case MVT::i8:
       CurDAG->SelectNodeTo(N, MVT::i32, PPC::EXTSB, Select(N->getOperand(0)));
       break;
-    case MVT::i1:
-      CurDAG->SelectNodeTo(N, MVT::i32, PPC::SUBFIC, Select(N->getOperand(0)),
-                           getI32Imm(0));
-      break;
     }
     break;
   case ISD::CTLZ:
@@ -327,6 +346,46 @@
     CurDAG->SelectNodeTo(N, MVT::i32, PPC::MULHWU, Select(N->getOperand(0)),
                          Select(N->getOperand(1)));
     break;
+  case ISD::XOR:
+    // Check whether or not this node is a logical 'not'.  This is represented
+    // by llvm as a xor with the constant value -1 (all bits set).  If this is a
+    // 'not', then fold 'or' into 'nor', and so forth for the supported ops.
+    if (isOprNot(N)) {
+      unsigned Opc;
+      switch(N->getOperand(0).getOpcode()) {
+      default:        Opc = 0;          break;
+      case ISD::OR:   Opc = PPC::NOR;   break;
+      case ISD::AND:  Opc = PPC::NAND;  break;
+      case ISD::XOR:  Opc = PPC::EQV;   break;
+      }
+      if (Opc)
+        CurDAG->SelectNodeTo(N, MVT::i32, Opc, 
+                             Select(N->getOperand(0).getOperand(0)),
+                             Select(N->getOperand(0).getOperand(1)));
+      else
+        CurDAG->SelectNodeTo(N, MVT::i32, PPC::NOR, Select(N->getOperand(0)),
+                             Select(N->getOperand(0)));
+      break;
+    }
+    // If this is a xor with an immediate other than -1, then codegen it as high
+    // and low 16 bit immediate xors.
+    if (SDNode *I = SelectIntImmediateExpr(N->getOperand(0), 
+                                           N->getOperand(1),
+                                           PPC::XORIS, PPC::XORI)) {
+      CurDAG->ReplaceAllUsesWith(N, I); 
+      N = I;
+      break;
+    }
+    // Finally, check for the case where we are being asked to select
+    // xor (not(a), b) which is equivalent to not(xor a, b), which is eqv
+    if (isOprNot(N->getOperand(0).Val))
+      CurDAG->SelectNodeTo(N, MVT::i32, PPC::EQV, 
+                           Select(N->getOperand(0).getOperand(0)),
+                           Select(N->getOperand(1)));
+    else
+      CurDAG->SelectNodeTo(N, MVT::i32, PPC::XOR, Select(N->getOperand(0)),
+                           Select(N->getOperand(1)));
+    break;
   case ISD::FABS:
     CurDAG->SelectNodeTo(N, N->getValueType(0), PPC::FABS, 
                          Select(N->getOperand(0)));





From natebegeman at mac.com  Thu Aug 18 00:45:02 2005
From: natebegeman at mac.com (Nate Begeman)
Date: Thu, 18 Aug 2005 00:45:02 -0500
Subject: [llvm-commits] CVS: llvm/lib/Target/PowerPC/PPC32ISelDAGToDAG.cpp 
Message-ID: <200508180545.AAA26515@zion.cs.uiuc.edu>



Changes in directory llvm/lib/Target/PowerPC:

PPC32ISelDAGToDAG.cpp updated: 1.6 -> 1.7
---
Log message:

Maintain consistency in negating things


---
Diffs of the changes:  (+8 -9)

 PPC32ISelDAGToDAG.cpp |   17 ++++++++---------
 1 files changed, 8 insertions(+), 9 deletions(-)


Index: llvm/lib/Target/PowerPC/PPC32ISelDAGToDAG.cpp
diff -u llvm/lib/Target/PowerPC/PPC32ISelDAGToDAG.cpp:1.6 llvm/lib/Target/PowerPC/PPC32ISelDAGToDAG.cpp:1.7
--- llvm/lib/Target/PowerPC/PPC32ISelDAGToDAG.cpp:1.6	Thu Aug 18 00:00:13 2005
+++ llvm/lib/Target/PowerPC/PPC32ISelDAGToDAG.cpp	Thu Aug 18 00:44:50 2005
@@ -352,19 +352,18 @@
     // 'not', then fold 'or' into 'nor', and so forth for the supported ops.
     if (isOprNot(N)) {
       unsigned Opc;
-      switch(N->getOperand(0).getOpcode()) {
+      SDOperand Val = Select(N->getOperand(0));
+      switch (Val.getTargetOpcode()) {
       default:        Opc = 0;          break;
-      case ISD::OR:   Opc = PPC::NOR;   break;
-      case ISD::AND:  Opc = PPC::NAND;  break;
-      case ISD::XOR:  Opc = PPC::EQV;   break;
+      case PPC::OR:   Opc = PPC::NOR;   break;
+      case PPC::AND:  Opc = PPC::NAND;  break;
+      case PPC::XOR:  Opc = PPC::EQV;   break;
       }
       if (Opc)
-        CurDAG->SelectNodeTo(N, MVT::i32, Opc, 
-                             Select(N->getOperand(0).getOperand(0)),
-                             Select(N->getOperand(0).getOperand(1)));
+        CurDAG->SelectNodeTo(N, MVT::i32, Opc, Val.getOperand(0),
+                             Val.getOperand(1));
       else
-        CurDAG->SelectNodeTo(N, MVT::i32, PPC::NOR, Select(N->getOperand(0)),
-                             Select(N->getOperand(0)));
+        CurDAG->SelectNodeTo(N, MVT::i32, PPC::NOR, Val, Val);
       break;
     }
     // If this is a xor with an immediate other than -1, then codegen it as high





From natebegeman at mac.com  Thu Aug 18 02:26:01 2005
From: natebegeman at mac.com (Nate Begeman)
Date: Thu, 18 Aug 2005 02:26:01 -0500
Subject: [llvm-commits] CVS: llvm/include/llvm/CodeGen/SelectionDAG.h
	SelectionDAGNodes.h 
Message-ID: <200508180726.CAA27017@zion.cs.uiuc.edu>



Changes in directory llvm/include/llvm/CodeGen:

SelectionDAG.h updated: 1.41 -> 1.42
SelectionDAGNodes.h updated: 1.57 -> 1.58
---
Log message:

Add support for target DAG nodes that take 4 operands, such as PowerPC's
rlwinm.


---
Diffs of the changes:  (+11 -0)

 SelectionDAG.h      |    2 ++
 SelectionDAGNodes.h |    9 +++++++++
 2 files changed, 11 insertions(+)


Index: llvm/include/llvm/CodeGen/SelectionDAG.h
diff -u llvm/include/llvm/CodeGen/SelectionDAG.h:1.41 llvm/include/llvm/CodeGen/SelectionDAG.h:1.42
--- llvm/include/llvm/CodeGen/SelectionDAG.h:1.41	Wed Aug 17 13:59:17 2005
+++ llvm/include/llvm/CodeGen/SelectionDAG.h	Thu Aug 18 02:25:46 2005
@@ -226,6 +226,8 @@
                     SDOperand Op1, SDOperand Op2);
   void SelectNodeTo(SDNode *N, MVT::ValueType VT, unsigned TargetOpc,
                     SDOperand Op1, SDOperand Op2, SDOperand Op3);
+  void SelectNodeTo(SDNode *N, MVT::ValueType VT, unsigned TargetOpc,
+                    SDOperand Op1, SDOperand Op2, SDOperand Op3, SDOperand Op4);
   
   SDOperand getTargetNode(unsigned Opcode, MVT::ValueType VT,
                           SDOperand Op1) {


Index: llvm/include/llvm/CodeGen/SelectionDAGNodes.h
diff -u llvm/include/llvm/CodeGen/SelectionDAGNodes.h:1.57 llvm/include/llvm/CodeGen/SelectionDAGNodes.h:1.58
--- llvm/include/llvm/CodeGen/SelectionDAGNodes.h:1.57	Wed Aug 17 18:44:54 2005
+++ llvm/include/llvm/CodeGen/SelectionDAGNodes.h	Thu Aug 18 02:25:46 2005
@@ -664,6 +664,15 @@
     Op0.Val->Uses.push_back(this); Op1.Val->Uses.push_back(this);
     Op2.Val->Uses.push_back(this);
   }
+  void setOperands(SDOperand Op0, SDOperand Op1, SDOperand Op2, SDOperand Op3) {
+    Operands.reserve(4);
+    Operands.push_back(Op0);
+    Operands.push_back(Op1);
+    Operands.push_back(Op2);
+    Operands.push_back(Op3);
+    Op0.Val->Uses.push_back(this); Op1.Val->Uses.push_back(this);
+    Op2.Val->Uses.push_back(this); Op3.Val->Uses.push_back(this);
+  }
   void addUser(SDNode *User) {
     Uses.push_back(User);
   }





From natebegeman at mac.com  Thu Aug 18 02:30:27 2005
From: natebegeman at mac.com (Nate Begeman)
Date: Thu, 18 Aug 2005 02:30:27 -0500
Subject: [llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp 
Message-ID: <200508180730.CAA27056@zion.cs.uiuc.edu>



Changes in directory llvm/lib/CodeGen/SelectionDAG:

SelectionDAG.cpp updated: 1.148 -> 1.149
---
Log message:

Add support for target DAG nodes that take 4 operands, such as PowerPC's
rlwinm.


---
Diffs of the changes:  (+8 -0)

 SelectionDAG.cpp |    8 ++++++++
 1 files changed, 8 insertions(+)


Index: llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp:1.148 llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp:1.149
--- llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp:1.148	Wed Aug 17 22:31:02 2005
+++ llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp	Thu Aug 18 02:30:15 2005
@@ -1810,6 +1810,14 @@
   N->setValueTypes(VT);
   N->setOperands(Op1, Op2, Op3);
 }
+void SelectionDAG::SelectNodeTo(SDNode *N, MVT::ValueType VT,
+                                unsigned TargetOpc, SDOperand Op1,
+                                SDOperand Op2, SDOperand Op3, SDOperand Op4) {
+  RemoveNodeFromCSEMaps(N);
+  N->MorphNodeTo(ISD::BUILTIN_OP_END+TargetOpc);
+  N->setValueTypes(VT);
+  N->setOperands(Op1, Op2, Op3, Op4);
+}
 
 /// ReplaceAllUsesWith - Modify anything using 'From' to use 'To' instead.
 /// This can cause recursive merging of nodes in the DAG.





From natebegeman at mac.com  Thu Aug 18 02:30:58 2005
From: natebegeman at mac.com (Nate Begeman)
Date: Thu, 18 Aug 2005 02:30:58 -0500
Subject: [llvm-commits] CVS: llvm/lib/Target/PowerPC/PPC32ISelDAGToDAG.cpp 
Message-ID: <200508180730.CAA27068@zion.cs.uiuc.edu>



Changes in directory llvm/lib/Target/PowerPC:

PPC32ISelDAGToDAG.cpp updated: 1.7 -> 1.8
---
Log message:

Add support for ISD::AND, and its various optimized forms.


---
Diffs of the changes:  (+105 -0)

 PPC32ISelDAGToDAG.cpp |  105 ++++++++++++++++++++++++++++++++++++++++++++++++++
 1 files changed, 105 insertions(+)


Index: llvm/lib/Target/PowerPC/PPC32ISelDAGToDAG.cpp
diff -u llvm/lib/Target/PowerPC/PPC32ISelDAGToDAG.cpp:1.7 llvm/lib/Target/PowerPC/PPC32ISelDAGToDAG.cpp:1.8
--- llvm/lib/Target/PowerPC/PPC32ISelDAGToDAG.cpp:1.7	Thu Aug 18 00:44:50 2005
+++ llvm/lib/Target/PowerPC/PPC32ISelDAGToDAG.cpp	Thu Aug 18 02:30:46 2005
@@ -90,6 +90,71 @@
   return false;
 }
 
+// isOprShiftImm - Returns true if the specified operand is a shift opcode with
+// a immediate shift count less than 32.
+static bool isOprShiftImm(SDNode *N, unsigned& Opc, unsigned& SH) {
+  Opc = N->getOpcode();
+  return (Opc == ISD::SHL || Opc == ISD::SRL || Opc == ISD::SRA) &&
+    isIntImmediate(N->getOperand(1).Val, SH) && SH < 32;
+}
+
+// isRunOfOnes - Returns true iff Val consists of one contiguous run of 1s with
+// any number of 0s on either side.  The 1s are allowed to wrap from LSB to
+// MSB, so 0x000FFF0, 0x0000FFFF, and 0xFF0000FF are all runs.  0x0F0F0000 is
+// not, since all 1s are not contiguous.
+static bool isRunOfOnes(unsigned Val, unsigned &MB, unsigned &ME) {
+  if (isShiftedMask_32(Val)) {
+    // look for the first non-zero bit
+    MB = CountLeadingZeros_32(Val);
+    // look for the first zero bit after the run of ones
+    ME = CountLeadingZeros_32((Val - 1) ^ Val);
+    return true;
+  } else if (isShiftedMask_32(Val = ~Val)) { // invert mask
+                                             // effectively look for the first zero bit
+    ME = CountLeadingZeros_32(Val) - 1;
+    // effectively look for the first one bit after the run of zeros
+    MB = CountLeadingZeros_32((Val - 1) ^ Val) + 1;
+    return true;
+  }
+  // no run present
+  return false;
+}
+
+// isRotateAndMask - Returns true if Mask and Shift can be folded in to a rotate
+// and mask opcode and mask operation.
+static bool isRotateAndMask(SDNode *N, unsigned Mask, bool IsShiftMask,
+                            unsigned &SH, unsigned &MB, unsigned &ME) {
+  unsigned Shift  = 32;
+  unsigned Indeterminant = ~0;  // bit mask marking indeterminant results
+  unsigned Opcode = N->getOpcode();
+  if (!isIntImmediate(N->getOperand(1).Val, Shift) || (Shift > 31))
+    return false;
+  
+  if (Opcode == ISD::SHL) {
+    // apply shift left to mask if it comes first
+    if (IsShiftMask) Mask = Mask << Shift;
+    // determine which bits are made indeterminant by shift
+    Indeterminant = ~(0xFFFFFFFFu << Shift);
+  } else if (Opcode == ISD::SRA || Opcode == ISD::SRL) { 
+    // apply shift right to mask if it comes first
+    if (IsShiftMask) Mask = Mask >> Shift;
+    // determine which bits are made indeterminant by shift
+    Indeterminant = ~(0xFFFFFFFFu >> Shift);
+    // adjust for the left rotate
+    Shift = 32 - Shift;
+  } else {
+    return false;
+  }
+  
+  // if the mask doesn't intersect any Indeterminant bits
+  if (Mask && !(Mask & Indeterminant)) {
+    SH = Shift;
+    // make sure the mask is still a mask (wrap arounds may not be)
+    return isRunOfOnes(Mask, MB, ME);
+  }
+  return false;
+}
+
 // isOpcWithIntImmediate - This method tests to see if the node is a specific
 // opcode and that it has a immediate integer right operand.
 // If so Imm will receive the 32 bit value.
@@ -346,6 +411,46 @@
     CurDAG->SelectNodeTo(N, MVT::i32, PPC::MULHWU, Select(N->getOperand(0)),
                          Select(N->getOperand(1)));
     break;
+  case ISD::AND: {
+    unsigned Imm, SH, MB, ME;
+    // If this is an and of a value rotated between 0 and 31 bits and then and'd
+    // with a mask, emit rlwinm
+    if (isIntImmediate(N->getOperand(1), Imm) && (isShiftedMask_32(Imm) ||
+                                                  isShiftedMask_32(~Imm))) {
+      SDOperand Val;
+      if (isRotateAndMask(N->getOperand(0).Val, Imm, false, SH, MB, ME)) {
+        Val = Select(N->getOperand(0).getOperand(0));
+      } else {
+        Val = Select(N->getOperand(0));
+        isRunOfOnes(Imm, MB, ME);
+        SH = 0;
+      }
+      CurDAG->SelectNodeTo(N, MVT::i32, PPC::RLWINM, Val, getI32Imm(SH),
+                           getI32Imm(MB), getI32Imm(ME));
+      break;
+    }
+    // If this is an and with an immediate that isn't a mask, then codegen it as
+    // high and low 16 bit immediate ands.
+    if (SDNode *I = SelectIntImmediateExpr(N->getOperand(0), 
+                                           N->getOperand(1),
+                                           PPC::ANDISo, PPC::ANDIo)) {
+      CurDAG->ReplaceAllUsesWith(N, I); 
+      N = I;
+      break;
+    }
+    // Finally, check for the case where we are being asked to select
+    // and (not(a), b) or and (a, not(b)) which can be selected as andc.
+    if (isOprNot(N->getOperand(0).Val))
+      CurDAG->SelectNodeTo(N, MVT::i32, PPC::ANDC, Select(N->getOperand(1)),
+                           Select(N->getOperand(0).getOperand(0)));
+    else if (isOprNot(N->getOperand(1).Val))
+      CurDAG->SelectNodeTo(N, MVT::i32, PPC::ANDC, Select(N->getOperand(0)),
+                           Select(N->getOperand(1).getOperand(0)));
+    else
+      CurDAG->SelectNodeTo(N, MVT::i32, PPC::AND, Select(N->getOperand(0)),
+                           Select(N->getOperand(1)));
+    break;
+  }
   case ISD::XOR:
     // Check whether or not this node is a logical 'not'.  This is represented
     // by llvm as a xor with the constant value -1 (all bits set).  If this is a





From jlaskey at apple.com  Thu Aug 18 03:56:57 2005
From: jlaskey at apple.com (Jim Laskey)
Date: Thu, 18 Aug 2005 05:56:57 -0300
Subject: [llvm-commits] CVS: llvm/lib/Target/PowerPC/PPC32ISelDAGToDAG.cpp
In-Reply-To: <200508180053.TAA15988@zion.cs.uiuc.edu>
References: <200508180053.TAA15988@zion.cs.uiuc.edu>
Message-ID: <C77708C7-B4BF-4FEB-9E39-073E316283CA@apple.com>

Is there a is implemented on target test for this somewhere?

Cheers,

-- Jim



On Aug 17, 2005, at 9:53 PM, Nate Begeman wrote:

> +  case ISD::FSQRT: {
> +    MVT::ValueType Ty = N->getValueType(0);
> +    CurDAG->SelectNodeTo(N, Ty, Ty == MVT::f64 ? PPC::FSQRT :  
> PPC::FSQRTS,
> +                         Select(N->getOperand(0)));
> +    break;
> +  }
>

-------------- next part --------------
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From sabre at nondot.org  Thu Aug 18 10:33:21 2005
From: sabre at nondot.org (Chris Lattner)
Date: Thu, 18 Aug 2005 10:33:21 -0500 (CDT)
Subject: [llvm-commits] CVS: llvm/lib/Target/PowerPC/PPC32ISelDAGToDAG.cpp
In-Reply-To: <C77708C7-B4BF-4FEB-9E39-073E316283CA@apple.com>
References: <200508180053.TAA15988@zion.cs.uiuc.edu>
	<C77708C7-B4BF-4FEB-9E39-073E316283CA@apple.com>
Message-ID: <Pine.LNX.4.61.0508181032250.5365@nondot.org>

On Thu, 18 Aug 2005, Jim Laskey wrote:
> Is there a is implemented on target test for this somewhere?

Yup, in PPC32ISelLowering.cpp, we have this:

   // If we're enabling GP optimizations, use hardware square root
   if (!TM.getSubtarget<PPCSubtarget>().isGigaProcessor()) {
     setOperationAction(ISD::FSQRT, MVT::f64, Expand);
     setOperationAction(ISD::FSQRT, MVT::f32, Expand);
   }

So the legalizer will take care of the processors that don't have it 
(expanding to a sqrt[f] call).

-Chris

>
> On Aug 17, 2005, at 9:53 PM, Nate Begeman wrote:
>
>> +  case ISD::FSQRT: {
>> +    MVT::ValueType Ty = N->getValueType(0);
>> +    CurDAG->SelectNodeTo(N, Ty, Ty == MVT::f64 ? PPC::FSQRT : PPC::FSQRTS,
>> +                         Select(N->getOperand(0)));
>> +    break;
>> +  }
>> 
>
>

-Chris

-- 
http://nondot.org/sabre/
http://llvm.org/



From jlaskey at apple.com  Thu Aug 18 10:51:14 2005
From: jlaskey at apple.com (Jim Laskey)
Date: Thu, 18 Aug 2005 12:51:14 -0300
Subject: [llvm-commits] CVS: llvm/lib/Target/PowerPC/PPC32ISelDAGToDAG.cpp
In-Reply-To: <Pine.LNX.4.61.0508181032250.5365@nondot.org>
References: <200508180053.TAA15988@zion.cs.uiuc.edu>
	<C77708C7-B4BF-4FEB-9E39-073E316283CA@apple.com>
	<Pine.LNX.4.61.0508181032250.5365@nondot.org>
Message-ID: <F934B34A-9F39-4F26-822C-F28994FB4597@apple.com>

It seems to be on by default.  I.E.  if I llc -march=ppc32 it gets  
generated.

-- Jim


On Aug 18, 2005, at 12:33 PM, Chris Lattner wrote:

> On Thu, 18 Aug 2005, Jim Laskey wrote:
>
>> Is there a is implemented on target test for this somewhere?
>>
>
> Yup, in PPC32ISelLowering.cpp, we have this:
>
>   // If we're enabling GP optimizations, use hardware square root
>   if (!TM.getSubtarget<PPCSubtarget>().isGigaProcessor()) {
>     setOperationAction(ISD::FSQRT, MVT::f64, Expand);
>     setOperationAction(ISD::FSQRT, MVT::f32, Expand);
>   }
>
> So the legalizer will take care of the processors that don't have  
> it (expanding to a sqrt[f] call).
>
> -Chris
>
>
>>
>> On Aug 17, 2005, at 9:53 PM, Nate Begeman wrote:
>>
>>
>>> +  case ISD::FSQRT: {
>>> +    MVT::ValueType Ty = N->getValueType(0);
>>> +    CurDAG->SelectNodeTo(N, Ty, Ty == MVT::f64 ? PPC::FSQRT :  
>>> PPC::FSQRTS,
>>> +                         Select(N->getOperand(0)));
>>> +    break;
>>> +  }
>>>
>>
>>
>>
>
> -Chris
>
> -- 
> http://nondot.org/sabre/
> http://llvm.org/
>



From jlaskey at apple.com  Thu Aug 18 10:52:42 2005
From: jlaskey at apple.com (Jim Laskey)
Date: Thu, 18 Aug 2005 10:52:42 -0500
Subject: [llvm-commits] CVS: llvm/lib/Target/PowerPC/PPC32ISelPattern.cpp 
Message-ID: <200508181552.KAA26903@zion.cs.uiuc.edu>



Changes in directory llvm/lib/Target/PowerPC:

PPC32ISelPattern.cpp updated: 1.149 -> 1.150
---
Log message:

Handle loading of 0x????0000 constants with a single instruction.



---
Diffs of the changes:  (+9 -5)

 PPC32ISelPattern.cpp |   14 +++++++++-----
 1 files changed, 9 insertions(+), 5 deletions(-)


Index: llvm/lib/Target/PowerPC/PPC32ISelPattern.cpp
diff -u llvm/lib/Target/PowerPC/PPC32ISelPattern.cpp:1.149 llvm/lib/Target/PowerPC/PPC32ISelPattern.cpp:1.150
--- llvm/lib/Target/PowerPC/PPC32ISelPattern.cpp:1.149	Wed Aug 17 19:15:15 2005
+++ llvm/lib/Target/PowerPC/PPC32ISelPattern.cpp	Thu Aug 18 10:52:30 2005
@@ -1738,12 +1738,16 @@
     case MVT::i32:
       {
         int v = (int)cast<ConstantSDNode>(N)->getSignExtended();
-        if (v < 32768 && v >= -32768) {
-          BuildMI(BB, PPC::LI, 1, Result).addSImm(v);
-        } else {
+        unsigned Hi = Hi16(v);
+        unsigned Lo = Lo16(v);
+        if (Hi && Lo) {
           Tmp1 = MakeIntReg();
-          BuildMI(BB, PPC::LIS, 1, Tmp1).addSImm(v >> 16);
-          BuildMI(BB, PPC::ORI, 2, Result).addReg(Tmp1).addImm(v & 0xFFFF);
+          BuildMI(BB, PPC::LIS, 1, Tmp1).addSImm(Hi);
+          BuildMI(BB, PPC::ORI, 2, Result).addReg(Tmp1).addImm(Lo);
+        } else if (Lo) {
+          BuildMI(BB, PPC::LI, 1, Result).addSImm(Lo);
+        } else {
+          BuildMI(BB, PPC::LIS, 1, Result).addSImm(Hi);
         }
       }
     }





From jlaskey at apple.com  Thu Aug 18 12:15:41 2005
From: jlaskey at apple.com (Jim Laskey)
Date: Thu, 18 Aug 2005 12:15:41 -0500
Subject: [llvm-commits] 
	CVS: llvm-test/MultiSource/Benchmarks/MallocBench/espresso/compl.c
	mincov.c opo.c 
Message-ID: <200508181715.MAA14346@zion.cs.uiuc.edu>



Changes in directory llvm-test/MultiSource/Benchmarks/MallocBench/espresso:

compl.c updated: 1.1 -> 1.2
mincov.c updated: 1.1 -> 1.2
opo.c updated: 1.1 -> 1.2
---
Log message:

Allow espresso to build under stricter C standards.



---
Diffs of the changes:  (+13 -13)

 compl.c  |   18 +++++++++---------
 mincov.c |    6 +++---
 opo.c    |    2 +-
 3 files changed, 13 insertions(+), 13 deletions(-)


Index: llvm-test/MultiSource/Benchmarks/MallocBench/espresso/compl.c
diff -u llvm-test/MultiSource/Benchmarks/MallocBench/espresso/compl.c:1.1 llvm-test/MultiSource/Benchmarks/MallocBench/espresso/compl.c:1.2
--- llvm-test/MultiSource/Benchmarks/MallocBench/espresso/compl.c:1.1	Tue Feb 17 12:13:39 2004
+++ llvm-test/MultiSource/Benchmarks/MallocBench/espresso/compl.c	Thu Aug 18 12:15:30 2005
@@ -22,15 +22,15 @@
 #define USE_COMPL_LIFT_ONSET_COMPLEX	2
 #define NO_LIFTING			3
 
-bool compl_special_cases();
-pcover compl_merge();
-void compl_d1merge();
-pcover compl_cube();
-void compl_lift();
-void compl_lift_onset();
-void compl_lift_onset_complex();
-bool simp_comp_special_cases();
-bool simplify_special_cases();
+static bool compl_special_cases();
+static pcover compl_merge();
+static void compl_d1merge();
+static pcover compl_cube();
+static void compl_lift();
+static void compl_lift_onset();
+static void compl_lift_onset_complex();
+static bool simp_comp_special_cases();
+static bool simplify_special_cases();
 
 
 /* complement -- compute the complement of T */


Index: llvm-test/MultiSource/Benchmarks/MallocBench/espresso/mincov.c
diff -u llvm-test/MultiSource/Benchmarks/MallocBench/espresso/mincov.c:1.1 llvm-test/MultiSource/Benchmarks/MallocBench/espresso/mincov.c:1.2
--- llvm-test/MultiSource/Benchmarks/MallocBench/espresso/mincov.c:1.1	Tue Feb 17 12:13:40 2004
+++ llvm-test/MultiSource/Benchmarks/MallocBench/espresso/mincov.c	Thu Aug 18 12:15:30 2005
@@ -7,9 +7,9 @@
 #define USE_GIMPEL
 #define USE_INDEP_SET
 
-extern int select_column();
-extern void select_essential();
-extern int verify_cover();
+static int select_column();
+static void select_essential();
+static int verify_cover();
 
 #define fail(why) {\
     (void) fprintf(stderr, "Fatal error: file %s, line %d\n%s\n",\


Index: llvm-test/MultiSource/Benchmarks/MallocBench/espresso/opo.c
diff -u llvm-test/MultiSource/Benchmarks/MallocBench/espresso/opo.c:1.1 llvm-test/MultiSource/Benchmarks/MallocBench/espresso/opo.c:1.2
--- llvm-test/MultiSource/Benchmarks/MallocBench/espresso/opo.c:1.1	Tue Feb 17 12:13:40 2004
+++ llvm-test/MultiSource/Benchmarks/MallocBench/espresso/opo.c	Thu Aug 18 12:15:30 2005
@@ -50,7 +50,7 @@
 static int opo_no_make_sparse;
 static int opo_repeated;
 static int opo_exact;
-void minimize();
+static void minimize();
 
 void phase_assignment(PLA, opo_strategy)
 pPLA PLA;





From jlaskey at apple.com  Thu Aug 18 12:16:34 2005
From: jlaskey at apple.com (Jim Laskey)
Date: Thu, 18 Aug 2005 12:16:34 -0500
Subject: [llvm-commits] 
	CVS: llvm-test/SingleSource/UnitTests/2005-07-17-INT-To-FP.c
Message-ID: <200508181716.MAA14411@zion.cs.uiuc.edu>



Changes in directory llvm-test/SingleSource/UnitTests:

2005-07-17-INT-To-FP.c updated: 1.1 -> 1.2
---
Log message:

Adding edge case tests for int to fp casting.



---
Diffs of the changes:  (+23 -0)

 2005-07-17-INT-To-FP.c |   23 +++++++++++++++++++++++
 1 files changed, 23 insertions(+)


Index: llvm-test/SingleSource/UnitTests/2005-07-17-INT-To-FP.c
diff -u llvm-test/SingleSource/UnitTests/2005-07-17-INT-To-FP.c:1.1 llvm-test/SingleSource/UnitTests/2005-07-17-INT-To-FP.c:1.2
--- llvm-test/SingleSource/UnitTests/2005-07-17-INT-To-FP.c:1.1	Sun Jul 17 23:29:50 2005
+++ llvm-test/SingleSource/UnitTests/2005-07-17-INT-To-FP.c	Thu Aug 18 12:16:22 2005
@@ -1,8 +1,24 @@
 // Test the various SINT-TO-FP and UINT-TO-FP conversions.
 #include <stdio.h>
 
+int tests[] = {
+  0x80000000,
+  -123456789,
+  -10,
+  -2,
+  -1,
+  0,
+  1,
+  2,
+  10,
+  123456789,
+  0x7FFFFFFF
+};
+
 int main() {
+
   unsigned i;
+  // byte boundary tests
   for (i = 0; i < 64; ++i) {
     printf("%d %f, %f, %f, %f\n", i,
            (double)(signed char)(i << 2),            // i8
@@ -16,4 +32,11 @@
            (double)(unsigned int)(i << 26),            // i32
            (double)(unsigned long long)((unsigned long long)i << 58ULL));  // i64
   }
+  // edge case tests
+  for (unsigned i = 0; i < (sizeof(tests) / sizeof(int)); i++) {
+    printf("%d %f %f %f %f\n", (double)(unsigned)tests[i],
+                               (double)(  signed)tests[i],
+                               (float) (unsigned)tests[i],
+                               (float) (  signed)tests[i]);
+  }
 }





From lattner at cs.uiuc.edu  Thu Aug 18 12:17:04 2005
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Thu, 18 Aug 2005 12:17:04 -0500
Subject: [llvm-commits] CVS: llvm/lib/Target/PowerPC/PPC32ISelPattern.cpp 
Message-ID: <200508181717.MAA14422@zion.cs.uiuc.edu>



Changes in directory llvm/lib/Target/PowerPC:

PPC32ISelPattern.cpp updated: 1.150 -> 1.151
---
Log message:

replace switch stmt with an assert, generate li 0 instead of lis 0 for 0,
to make the code follow people's expectations better.


---
Diffs of the changes:  (+15 -18)

 PPC32ISelPattern.cpp |   33 +++++++++++++++------------------
 1 files changed, 15 insertions(+), 18 deletions(-)


Index: llvm/lib/Target/PowerPC/PPC32ISelPattern.cpp
diff -u llvm/lib/Target/PowerPC/PPC32ISelPattern.cpp:1.150 llvm/lib/Target/PowerPC/PPC32ISelPattern.cpp:1.151
--- llvm/lib/Target/PowerPC/PPC32ISelPattern.cpp:1.150	Thu Aug 18 10:52:30 2005
+++ llvm/lib/Target/PowerPC/PPC32ISelPattern.cpp	Thu Aug 18 12:16:52 2005
@@ -1732,26 +1732,23 @@
     return Result;
   }
 
-  case ISD::Constant:
-    switch (N.getValueType()) {
-    default: assert(0 && "Cannot use constants of this type!");
-    case MVT::i32:
-      {
-        int v = (int)cast<ConstantSDNode>(N)->getSignExtended();
-        unsigned Hi = Hi16(v);
-        unsigned Lo = Lo16(v);
-        if (Hi && Lo) {
-          Tmp1 = MakeIntReg();
-          BuildMI(BB, PPC::LIS, 1, Tmp1).addSImm(Hi);
-          BuildMI(BB, PPC::ORI, 2, Result).addReg(Tmp1).addImm(Lo);
-        } else if (Lo) {
-          BuildMI(BB, PPC::LI, 1, Result).addSImm(Lo);
-        } else {
-          BuildMI(BB, PPC::LIS, 1, Result).addSImm(Hi);
-        }
-      }
+  case ISD::Constant: {
+    assert(N.getValueType() == MVT::i32 &&
+           "Only i32 constants are legal on this target!");
+    int v = (int)cast<ConstantSDNode>(N)->getValue();
+    unsigned Hi = Hi16(v);
+    unsigned Lo = Lo16(v);
+    if (Hi && Lo) {
+      Tmp1 = MakeIntReg();
+      BuildMI(BB, PPC::LIS, 1, Tmp1).addSImm(Hi);
+      BuildMI(BB, PPC::ORI, 2, Result).addReg(Tmp1).addImm(Lo);
+    } else if (Hi) {
+      BuildMI(BB, PPC::LIS, 1, Result).addSImm(Hi);
+    } else {
+      BuildMI(BB, PPC::LI, 1, Result).addSImm(Lo);
     }
     return Result;
+  }
 
   case ISD::ConstantFP: {
     ConstantFPSDNode *CN = cast<ConstantFPSDNode>(N);





From lattner at cs.uiuc.edu  Thu Aug 18 12:31:53 2005
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Thu, 18 Aug 2005 12:31:53 -0500
Subject: [llvm-commits] CVS: llvm-test/Makefile.programs 
Message-ID: <200508181731.MAA14514@zion.cs.uiuc.edu>



Changes in directory llvm-test:

Makefile.programs updated: 1.163 -> 1.164
---
Log message:

This flag goes away


---
Diffs of the changes:  (+2 -3)

 Makefile.programs |    5 ++---
 1 files changed, 2 insertions(+), 3 deletions(-)


Index: llvm-test/Makefile.programs
diff -u llvm-test/Makefile.programs:1.163 llvm-test/Makefile.programs:1.164
--- llvm-test/Makefile.programs:1.163	Wed Aug 17 01:38:05 2005
+++ llvm-test/Makefile.programs	Thu Aug 18 12:31:40 2005
@@ -187,15 +187,14 @@
 endif#DISABLE_DIFFS
 
 ifeq ($(ARCH),PowerPC)
-LLCBETAOPTION := -split-phi-constant-crit-edges
+LLCBETAOPTION := 
 endif
 ifeq ($(ARCH),Alpha)
 LLCBETAOPTION := -enable-alpha-FTOI -enable-lsr-for-alpha
 #-enable-alpha-intfpdiv
 endif
 ifeq ($(ARCH),x86)
-LLCBETAOPTION := -split-phi-constant-crit-edges
-#-enable-x86-fastcc
+LLCBETAOPTION := -enable-x86-fastcc
 endif
 
 # Given a version of the entire program linked together into a single unit of





From lattner at cs.uiuc.edu  Thu Aug 18 12:35:26 2005
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Thu, 18 Aug 2005 12:35:26 -0500
Subject: [llvm-commits] 
	CVS: llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
Message-ID: <200508181735.MAA14587@zion.cs.uiuc.edu>



Changes in directory llvm/lib/CodeGen/SelectionDAG:

SelectionDAGISel.cpp updated: 1.71 -> 1.72
---
Log message:

Enable critical edge splitting by default


---
Diffs of the changes:  (+10 -16)

 SelectionDAGISel.cpp |   26 ++++++++++----------------
 1 files changed, 10 insertions(+), 16 deletions(-)


Index: llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.71 llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.72
--- llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.71	Wed Aug 17 01:37:43 2005
+++ llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp	Thu Aug 18 12:35:14 2005
@@ -36,11 +36,6 @@
 #include <iostream>
 using namespace llvm;
 
-static cl::opt<bool>
-SplitPHICritEdges("split-phi-constant-crit-edges", cl::Hidden,
-         cl::desc("Split critical edges for PHI values that are constants"));
-
-
 #ifndef _NDEBUG
 static cl::opt<bool>
 ViewDAGs("view-isel-dags", cl::Hidden,
@@ -966,8 +961,8 @@
 }
 
 void SelectionDAGISel::getAnalysisUsage(AnalysisUsage &AU) const {
-  if (!SplitPHICritEdges)
-    AU.setPreservesAll();
+  // FIXME: we only modify the CFG to split critical edges.  This
+  // updates dom and loop info.
 }
 
 
@@ -979,15 +974,14 @@
   // First pass, split all critical edges for PHI nodes with incoming values
   // that are constants, this way the load of the constant into a vreg will not
   // be placed into MBBs that are used some other way.
-  if (SplitPHICritEdges)
-    for (Function::iterator BB = Fn.begin(), E = Fn.end(); BB != E; ++BB) {
-      PHINode *PN;
-      for (BasicBlock::iterator BBI = BB->begin();
-           (PN = dyn_cast<PHINode>(BBI)); ++BBI)
-        for (unsigned i = 0, e = PN->getNumIncomingValues(); i != e; ++i)
-          if (isa<Constant>(PN->getIncomingValue(i)))
-            SplitCriticalEdge(PN->getIncomingBlock(i), BB);
-    }
+  for (Function::iterator BB = Fn.begin(), E = Fn.end(); BB != E; ++BB) {
+    PHINode *PN;
+    for (BasicBlock::iterator BBI = BB->begin();
+         (PN = dyn_cast<PHINode>(BBI)); ++BBI)
+      for (unsigned i = 0, e = PN->getNumIncomingValues(); i != e; ++i)
+        if (isa<Constant>(PN->getIncomingValue(i)))
+          SplitCriticalEdge(PN->getIncomingBlock(i), BB);
+  }
 
   FunctionLoweringInfo FuncInfo(TLI, Fn, MF);
 





From natebegeman at mac.com  Thu Aug 18 13:01:50 2005
From: natebegeman at mac.com (Nate Begeman)
Date: Thu, 18 Aug 2005 13:01:50 -0500
Subject: [llvm-commits] CVS: llvm/lib/Target/PowerPC/PPC32ISelDAGToDAG.cpp
	PPC32ISelPattern.cpp 
Message-ID: <200508181801.NAA14729@zion.cs.uiuc.edu>



Changes in directory llvm/lib/Target/PowerPC:

PPC32ISelDAGToDAG.cpp updated: 1.8 -> 1.9
PPC32ISelPattern.cpp updated: 1.151 -> 1.152
---
Log message:

Improve ISD::Constant codegen.
Now for int foo() { return -1; } we generate:
_foo:
        li r3, -1
        blr

instead of
_foo:
        lis r2, -1
        ori r3, r2, 65535
        blr


---
Diffs of the changes:  (+12 -8)

 PPC32ISelDAGToDAG.cpp |   18 +++++++++++-------
 PPC32ISelPattern.cpp  |    2 +-
 2 files changed, 12 insertions(+), 8 deletions(-)


Index: llvm/lib/Target/PowerPC/PPC32ISelDAGToDAG.cpp
diff -u llvm/lib/Target/PowerPC/PPC32ISelDAGToDAG.cpp:1.8 llvm/lib/Target/PowerPC/PPC32ISelDAGToDAG.cpp:1.9
--- llvm/lib/Target/PowerPC/PPC32ISelDAGToDAG.cpp:1.8	Thu Aug 18 02:30:46 2005
+++ llvm/lib/Target/PowerPC/PPC32ISelDAGToDAG.cpp	Thu Aug 18 13:01:39 2005
@@ -277,15 +277,18 @@
   case ISD::Constant: {
     assert(N->getValueType(0) == MVT::i32);
     unsigned v = (unsigned)cast<ConstantSDNode>(N)->getValue();
-    if ((unsigned)(short)v == v) {
+    unsigned Hi = HA16(v);
+    unsigned Lo = Lo16(v);
+    if (Hi && Lo) {
+      SDOperand Top = CurDAG->getTargetNode(PPC::LIS, MVT::i32, 
+                                            getI32Imm(v >> 16));
+      CurDAG->SelectNodeTo(N, MVT::i32, PPC::ORI, Top, getI32Imm(v & 0xFFFF));
+    } else if (Lo) {
       CurDAG->SelectNodeTo(N, MVT::i32, PPC::LI, getI32Imm(v));
-      break;
     } else {
-      SDOperand Top = CurDAG->getTargetNode(PPC::LIS, MVT::i32,
-                                            getI32Imm(unsigned(v) >> 16));
-      CurDAG->SelectNodeTo(N, MVT::i32, PPC::ORI, Top, getI32Imm(v & 0xFFFF));
-      break;
+      CurDAG->SelectNodeTo(N, MVT::i32, PPC::LIS, getI32Imm(v >> 16));
     }
+    break;
   }
   case ISD::SIGN_EXTEND_INREG:
     switch(cast<VTSDNode>(N->getOperand(1))->getVT()) {
@@ -412,12 +415,13 @@
                          Select(N->getOperand(1)));
     break;
   case ISD::AND: {
-    unsigned Imm, SH, MB, ME;
+    unsigned Imm;
     // If this is an and of a value rotated between 0 and 31 bits and then and'd
     // with a mask, emit rlwinm
     if (isIntImmediate(N->getOperand(1), Imm) && (isShiftedMask_32(Imm) ||
                                                   isShiftedMask_32(~Imm))) {
       SDOperand Val;
+      unsigned SH, MB, ME;
       if (isRotateAndMask(N->getOperand(0).Val, Imm, false, SH, MB, ME)) {
         Val = Select(N->getOperand(0).getOperand(0));
       } else {


Index: llvm/lib/Target/PowerPC/PPC32ISelPattern.cpp
diff -u llvm/lib/Target/PowerPC/PPC32ISelPattern.cpp:1.151 llvm/lib/Target/PowerPC/PPC32ISelPattern.cpp:1.152
--- llvm/lib/Target/PowerPC/PPC32ISelPattern.cpp:1.151	Thu Aug 18 12:16:52 2005
+++ llvm/lib/Target/PowerPC/PPC32ISelPattern.cpp	Thu Aug 18 13:01:39 2005
@@ -1736,7 +1736,7 @@
     assert(N.getValueType() == MVT::i32 &&
            "Only i32 constants are legal on this target!");
     int v = (int)cast<ConstantSDNode>(N)->getValue();
-    unsigned Hi = Hi16(v);
+    unsigned Hi = HA16(v);
     unsigned Lo = Lo16(v);
     if (Hi && Lo) {
       Tmp1 = MakeIntReg();





From sabre at nondot.org  Thu Aug 18 13:04:41 2005
From: sabre at nondot.org (Chris Lattner)
Date: Thu, 18 Aug 2005 13:04:41 -0500 (CDT)
Subject: [llvm-commits] CVS: llvm/lib/Target/PowerPC/PPC32ISelDAGToDAG.cpp
	PPC32ISelPattern.cpp 
In-Reply-To: <200508181801.NAA14729@zion.cs.uiuc.edu>
References: <200508181801.NAA14729@zion.cs.uiuc.edu>
Message-ID: <Pine.LNX.4.61.0508181304250.19940@nondot.org>


I emailed Jim about this before, but won't this miscompile 65535 -> -1?

-Chris

On Thu, 18 Aug 2005, Nate Begeman wrote:

>
>
> Changes in directory llvm/lib/Target/PowerPC:
>
> PPC32ISelDAGToDAG.cpp updated: 1.8 -> 1.9
> PPC32ISelPattern.cpp updated: 1.151 -> 1.152
> ---
> Log message:
>
> Improve ISD::Constant codegen.
> Now for int foo() { return -1; } we generate:
> _foo:
>        li r3, -1
>        blr
>
> instead of
> _foo:
>        lis r2, -1
>        ori r3, r2, 65535
>        blr
>
>
> ---
> Diffs of the changes:  (+12 -8)
>
> PPC32ISelDAGToDAG.cpp |   18 +++++++++++-------
> PPC32ISelPattern.cpp  |    2 +-
> 2 files changed, 12 insertions(+), 8 deletions(-)
>
>
> Index: llvm/lib/Target/PowerPC/PPC32ISelDAGToDAG.cpp
> diff -u llvm/lib/Target/PowerPC/PPC32ISelDAGToDAG.cpp:1.8 llvm/lib/Target/PowerPC/PPC32ISelDAGToDAG.cpp:1.9
> --- llvm/lib/Target/PowerPC/PPC32ISelDAGToDAG.cpp:1.8	Thu Aug 18 02:30:46 2005
> +++ llvm/lib/Target/PowerPC/PPC32ISelDAGToDAG.cpp	Thu Aug 18 13:01:39 2005
> @@ -277,15 +277,18 @@
>   case ISD::Constant: {
>     assert(N->getValueType(0) == MVT::i32);
>     unsigned v = (unsigned)cast<ConstantSDNode>(N)->getValue();
> -    if ((unsigned)(short)v == v) {
> +    unsigned Hi = HA16(v);
> +    unsigned Lo = Lo16(v);
> +    if (Hi && Lo) {
> +      SDOperand Top = CurDAG->getTargetNode(PPC::LIS, MVT::i32,
> +                                            getI32Imm(v >> 16));
> +      CurDAG->SelectNodeTo(N, MVT::i32, PPC::ORI, Top, getI32Imm(v & 0xFFFF));
> +    } else if (Lo) {
>       CurDAG->SelectNodeTo(N, MVT::i32, PPC::LI, getI32Imm(v));
> -      break;
>     } else {
> -      SDOperand Top = CurDAG->getTargetNode(PPC::LIS, MVT::i32,
> -                                            getI32Imm(unsigned(v) >> 16));
> -      CurDAG->SelectNodeTo(N, MVT::i32, PPC::ORI, Top, getI32Imm(v & 0xFFFF));
> -      break;
> +      CurDAG->SelectNodeTo(N, MVT::i32, PPC::LIS, getI32Imm(v >> 16));
>     }
> +    break;
>   }
>   case ISD::SIGN_EXTEND_INREG:
>     switch(cast<VTSDNode>(N->getOperand(1))->getVT()) {
> @@ -412,12 +415,13 @@
>                          Select(N->getOperand(1)));
>     break;
>   case ISD::AND: {
> -    unsigned Imm, SH, MB, ME;
> +    unsigned Imm;
>     // If this is an and of a value rotated between 0 and 31 bits and then and'd
>     // with a mask, emit rlwinm
>     if (isIntImmediate(N->getOperand(1), Imm) && (isShiftedMask_32(Imm) ||
>                                                   isShiftedMask_32(~Imm))) {
>       SDOperand Val;
> +      unsigned SH, MB, ME;
>       if (isRotateAndMask(N->getOperand(0).Val, Imm, false, SH, MB, ME)) {
>         Val = Select(N->getOperand(0).getOperand(0));
>       } else {
>
>
> Index: llvm/lib/Target/PowerPC/PPC32ISelPattern.cpp
> diff -u llvm/lib/Target/PowerPC/PPC32ISelPattern.cpp:1.151 llvm/lib/Target/PowerPC/PPC32ISelPattern.cpp:1.152
> --- llvm/lib/Target/PowerPC/PPC32ISelPattern.cpp:1.151	Thu Aug 18 12:16:52 2005
> +++ llvm/lib/Target/PowerPC/PPC32ISelPattern.cpp	Thu Aug 18 13:01:39 2005
> @@ -1736,7 +1736,7 @@
>     assert(N.getValueType() == MVT::i32 &&
>            "Only i32 constants are legal on this target!");
>     int v = (int)cast<ConstantSDNode>(N)->getValue();
> -    unsigned Hi = Hi16(v);
> +    unsigned Hi = HA16(v);
>     unsigned Lo = Lo16(v);
>     if (Hi && Lo) {
>       Tmp1 = MakeIntReg();
>
>
>
> _______________________________________________
> llvm-commits mailing list
> llvm-commits at cs.uiuc.edu
> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
>

-Chris

-- 
http://nondot.org/sabre/
http://llvm.org/



From natebegeman at mac.com  Thu Aug 18 13:15:00 2005
From: natebegeman at mac.com (Nate Begeman)
Date: Thu, 18 Aug 2005 13:15:00 -0500
Subject: [llvm-commits] CVS: llvm/lib/Target/PowerPC/PPC32ISelPattern.cpp 
Message-ID: <200508181815.NAA20618@zion.cs.uiuc.edu>



Changes in directory llvm/lib/Target/PowerPC:

PPC32ISelPattern.cpp updated: 1.152 -> 1.153
---
Log message:

Fix int foo() { return 65535; } by using the top 16 bits of the constant
as the argument to LIS rather than the result of HA16(constant).

The DAG->DAG ISel was already doing the right thing.


---
Diffs of the changes:  (+3 -20)

 PPC32ISelPattern.cpp |   23 +++--------------------
 1 files changed, 3 insertions(+), 20 deletions(-)


Index: llvm/lib/Target/PowerPC/PPC32ISelPattern.cpp
diff -u llvm/lib/Target/PowerPC/PPC32ISelPattern.cpp:1.152 llvm/lib/Target/PowerPC/PPC32ISelPattern.cpp:1.153
--- llvm/lib/Target/PowerPC/PPC32ISelPattern.cpp:1.152	Thu Aug 18 13:01:39 2005
+++ llvm/lib/Target/PowerPC/PPC32ISelPattern.cpp	Thu Aug 18 13:14:49 2005
@@ -246,23 +246,6 @@
   return 0;
 }
 
-/// getCROpForOp - Return the condition register opcode (or inverted opcode)
-/// associated with the SelectionDAG opcode.
-static unsigned getCROpForSetCC(unsigned Opcode, bool Inv1, bool Inv2) {
-  switch (Opcode) {
-  default: assert(0 && "Unknown opcode!"); abort();
-  case ISD::AND:
-    if (Inv1 && Inv2) return PPC::CRNOR; // De Morgan's Law
-    if (!Inv1 && !Inv2) return PPC::CRAND;
-    if (Inv1 ^ Inv2) return PPC::CRANDC;
-  case ISD::OR:
-    if (Inv1 && Inv2) return PPC::CRNAND; // De Morgan's Law
-    if (!Inv1 && !Inv2) return PPC::CROR;
-    if (Inv1 ^ Inv2) return PPC::CRORC;
-  }
-  return 0;
-}
-
 /// getCRIdxForSetCC - Return the index of the condition register field
 /// associated with the SetCC condition, and whether or not the field is
 /// treated as inverted.  That is, lt = 0; ge = 0 inverted.
@@ -1735,15 +1718,15 @@
   case ISD::Constant: {
     assert(N.getValueType() == MVT::i32 &&
            "Only i32 constants are legal on this target!");
-    int v = (int)cast<ConstantSDNode>(N)->getValue();
+    unsigned v = (unsigned)cast<ConstantSDNode>(N)->getValue();
     unsigned Hi = HA16(v);
     unsigned Lo = Lo16(v);
     if (Hi && Lo) {
       Tmp1 = MakeIntReg();
-      BuildMI(BB, PPC::LIS, 1, Tmp1).addSImm(Hi);
+      BuildMI(BB, PPC::LIS, 1, Tmp1).addSImm(v >> 16);
       BuildMI(BB, PPC::ORI, 2, Result).addReg(Tmp1).addImm(Lo);
     } else if (Hi) {
-      BuildMI(BB, PPC::LIS, 1, Result).addSImm(Hi);
+      BuildMI(BB, PPC::LIS, 1, Result).addSImm(v >> 16);
     } else {
       BuildMI(BB, PPC::LI, 1, Result).addSImm(Lo);
     }





From sabre at nondot.org  Thu Aug 18 13:21:24 2005
From: sabre at nondot.org (Chris Lattner)
Date: Thu, 18 Aug 2005 13:21:24 -0500 (CDT)
Subject: [llvm-commits] CVS: llvm/lib/Target/PowerPC/PPC32ISelPattern.cpp
In-Reply-To: <200508181815.NAA20618@zion.cs.uiuc.edu>
References: <200508181815.NAA20618@zion.cs.uiuc.edu>
Message-ID: <Pine.LNX.4.61.0508181320490.19940@nondot.org>

On Thu, 18 Aug 2005, Nate Begeman wrote:
> Fix int foo() { return 65535; } by using the top 16 bits of the constant
> as the argument to LIS rather than the result of HA16(constant).
>
> The DAG->DAG ISel was already doing the right thing.

This still doesn't fix it, IIUC.  This will result in 65535 turning into 
"li 65535" -> "li -1".

No?

-Chris

> Diffs of the changes:  (+3 -20)
>
> PPC32ISelPattern.cpp |   23 +++--------------------
> 1 files changed, 3 insertions(+), 20 deletions(-)
>
>
> Index: llvm/lib/Target/PowerPC/PPC32ISelPattern.cpp
> diff -u llvm/lib/Target/PowerPC/PPC32ISelPattern.cpp:1.152 llvm/lib/Target/PowerPC/PPC32ISelPattern.cpp:1.153
> --- llvm/lib/Target/PowerPC/PPC32ISelPattern.cpp:1.152	Thu Aug 18 13:01:39 2005
> +++ llvm/lib/Target/PowerPC/PPC32ISelPattern.cpp	Thu Aug 18 13:14:49 2005
> @@ -246,23 +246,6 @@
>   return 0;
> }
>
> -/// getCROpForOp - Return the condition register opcode (or inverted opcode)
> -/// associated with the SelectionDAG opcode.
> -static unsigned getCROpForSetCC(unsigned Opcode, bool Inv1, bool Inv2) {
> -  switch (Opcode) {
> -  default: assert(0 && "Unknown opcode!"); abort();
> -  case ISD::AND:
> -    if (Inv1 && Inv2) return PPC::CRNOR; // De Morgan's Law
> -    if (!Inv1 && !Inv2) return PPC::CRAND;
> -    if (Inv1 ^ Inv2) return PPC::CRANDC;
> -  case ISD::OR:
> -    if (Inv1 && Inv2) return PPC::CRNAND; // De Morgan's Law
> -    if (!Inv1 && !Inv2) return PPC::CROR;
> -    if (Inv1 ^ Inv2) return PPC::CRORC;
> -  }
> -  return 0;
> -}
> -
> /// getCRIdxForSetCC - Return the index of the condition register field
> /// associated with the SetCC condition, and whether or not the field is
> /// treated as inverted.  That is, lt = 0; ge = 0 inverted.
> @@ -1735,15 +1718,15 @@
>   case ISD::Constant: {
>     assert(N.getValueType() == MVT::i32 &&
>            "Only i32 constants are legal on this target!");
> -    int v = (int)cast<ConstantSDNode>(N)->getValue();
> +    unsigned v = (unsigned)cast<ConstantSDNode>(N)->getValue();
>     unsigned Hi = HA16(v);
>     unsigned Lo = Lo16(v);
>     if (Hi && Lo) {
>       Tmp1 = MakeIntReg();
> -      BuildMI(BB, PPC::LIS, 1, Tmp1).addSImm(Hi);
> +      BuildMI(BB, PPC::LIS, 1, Tmp1).addSImm(v >> 16);
>       BuildMI(BB, PPC::ORI, 2, Result).addReg(Tmp1).addImm(Lo);
>     } else if (Hi) {
> -      BuildMI(BB, PPC::LIS, 1, Result).addSImm(Hi);
> +      BuildMI(BB, PPC::LIS, 1, Result).addSImm(v >> 16);
>     } else {
>       BuildMI(BB, PPC::LI, 1, Result).addSImm(Lo);
>     }
>
>
>
> _______________________________________________
> llvm-commits mailing list
> llvm-commits at cs.uiuc.edu
> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
>

-Chris

-- 
http://nondot.org/sabre/
http://llvm.org/



From sabre at nondot.org  Thu Aug 18 13:23:50 2005
From: sabre at nondot.org (Chris Lattner)
Date: Thu, 18 Aug 2005 13:23:50 -0500 (CDT)
Subject: [llvm-commits] CVS: llvm/lib/Target/PowerPC/PPC32ISelPattern.cpp
In-Reply-To: <Pine.LNX.4.61.0508181320490.19940@nondot.org>
References: <200508181815.NAA20618@zion.cs.uiuc.edu>
	<Pine.LNX.4.61.0508181320490.19940@nondot.org>
Message-ID: <Pine.LNX.4.61.0508181323310.19940@nondot.org>

On Thu, 18 Aug 2005, Chris Lattner wrote:
> On Thu, 18 Aug 2005, Nate Begeman wrote:
>> Fix int foo() { return 65535; } by using the top 16 bits of the 
>> constant
>> as the argument to LIS rather than the result of HA16(constant).
>> 
>> The DAG->DAG ISel was already doing the right thing.
>
> This still doesn't fix it, IIUC.  This will result in 65535 turning into 
> "li 65535" -> "li -1".

Oh I see.  It's using HA16 instead of Hi16, ok. :)

-Chris

>> Diffs of the changes:  (+3 -20)
>> 
>> PPC32ISelPattern.cpp |   23 +++--------------------
>> 1 files changed, 3 insertions(+), 20 deletions(-)
>> 
>> 
>> Index: llvm/lib/Target/PowerPC/PPC32ISelPattern.cpp
>> diff -u llvm/lib/Target/PowerPC/PPC32ISelPattern.cpp:1.152 
>> llvm/lib/Target/PowerPC/PPC32ISelPattern.cpp:1.153
>> --- llvm/lib/Target/PowerPC/PPC32ISelPattern.cpp:1.152	Thu Aug 
>> 18 13:01:39 2005
>> +++ llvm/lib/Target/PowerPC/PPC32ISelPattern.cpp	Thu Aug 18 
>> 13:14:49 2005
>> @@ -246,23 +246,6 @@
>>   return 0;
>> }
>> 
>> -/// getCROpForOp - Return the condition register opcode (or inverted 
>> opcode)
>> -/// associated with the SelectionDAG opcode.
>> -static unsigned getCROpForSetCC(unsigned Opcode, bool Inv1, bool Inv2) 
>> {
>> -  switch (Opcode) {
>> -  default: assert(0 && "Unknown opcode!"); abort();
>> -  case ISD::AND:
>> -    if (Inv1 && Inv2) return PPC::CRNOR; // De Morgan's Law
>> -    if (!Inv1 && !Inv2) return PPC::CRAND;
>> -    if (Inv1 ^ Inv2) return PPC::CRANDC;
>> -  case ISD::OR:
>> -    if (Inv1 && Inv2) return PPC::CRNAND; // De Morgan's Law
>> -    if (!Inv1 && !Inv2) return PPC::CROR;
>> -    if (Inv1 ^ Inv2) return PPC::CRORC;
>> -  }
>> -  return 0;
>> -}
>> -
>> /// getCRIdxForSetCC - Return the index of the condition register field
>> /// associated with the SetCC condition, and whether or not the field 
>> is
>> /// treated as inverted.  That is, lt = 0; ge = 0 inverted.
>> @@ -1735,15 +1718,15 @@
>>   case ISD::Constant: {
>>     assert(N.getValueType() == MVT::i32 &&
>>            "Only i32 constants are legal on this target!");
>> -    int v = (int)cast<ConstantSDNode>(N)->getValue();
>> +    unsigned v = (unsigned)cast<ConstantSDNode>(N)->getValue();
>>     unsigned Hi = HA16(v);
>>     unsigned Lo = Lo16(v);
>>     if (Hi && Lo) {
>>       Tmp1 = MakeIntReg();
>> -      BuildMI(BB, PPC::LIS, 1, Tmp1).addSImm(Hi);
>> +      BuildMI(BB, PPC::LIS, 1, Tmp1).addSImm(v >> 16);
>>       BuildMI(BB, PPC::ORI, 2, Result).addReg(Tmp1).addImm(Lo);
>>     } else if (Hi) {
>> -      BuildMI(BB, PPC::LIS, 1, Result).addSImm(Hi);
>> +      BuildMI(BB, PPC::LIS, 1, Result).addSImm(v >> 16);
>>     } else {
>>       BuildMI(BB, PPC::LI, 1, Result).addSImm(Lo);
>>     }
>> 
>> 
>> 
>> _______________________________________________
>> llvm-commits mailing list
>> llvm-commits at cs.uiuc.edu
>> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
>> 
>
> -Chris
>
>

-Chris

-- 
http://nondot.org/sabre/
http://llvm.org/



From lattner at cs.uiuc.edu  Thu Aug 18 13:34:12 2005
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Thu, 18 Aug 2005 13:34:12 -0500
Subject: [llvm-commits] CVS: llvm/lib/Target/PowerPC/PPC32ISelDAGToDAG.cpp 
Message-ID: <200508181834.NAA23319@zion.cs.uiuc.edu>



Changes in directory llvm/lib/Target/PowerPC:

PPC32ISelDAGToDAG.cpp updated: 1.9 -> 1.10
---
Log message:

remove some unused stuff


---
Diffs of the changes:  (+0 -10)

 PPC32ISelDAGToDAG.cpp |   10 ----------
 1 files changed, 10 deletions(-)


Index: llvm/lib/Target/PowerPC/PPC32ISelDAGToDAG.cpp
diff -u llvm/lib/Target/PowerPC/PPC32ISelDAGToDAG.cpp:1.9 llvm/lib/Target/PowerPC/PPC32ISelDAGToDAG.cpp:1.10
--- llvm/lib/Target/PowerPC/PPC32ISelDAGToDAG.cpp:1.9	Thu Aug 18 13:01:39 2005
+++ llvm/lib/Target/PowerPC/PPC32ISelDAGToDAG.cpp	Thu Aug 18 13:34:00 2005
@@ -35,20 +35,10 @@
   class PPC32DAGToDAGISel : public SelectionDAGISel {
     PPC32TargetLowering PPC32Lowering;
     
-    unsigned GlobalBaseReg;
-    bool GlobalBaseInitialized;
   public:
     PPC32DAGToDAGISel(TargetMachine &TM)
       : SelectionDAGISel(PPC32Lowering), PPC32Lowering(TM) {}
     
-    /// runOnFunction - Override this function in order to reset our
-    /// per-function variables.
-    virtual bool runOnFunction(Function &Fn) {
-      // Make sure we re-emit a set of the global base reg if necessary
-      GlobalBaseInitialized = false;
-      return SelectionDAGISel::runOnFunction(Fn);
-    }
-    
     /// getI32Imm - Return a target constant with the specified value, of type
     /// i32.
     inline SDOperand getI32Imm(unsigned Imm) {





From lattner at cs.uiuc.edu  Thu Aug 18 13:44:44 2005
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Thu, 18 Aug 2005 13:44:44 -0500
Subject: [llvm-commits] CVS: llvm/include/llvm/CodeGen/SelectionDAGISel.h 
Message-ID: <200508181844.NAA23454@zion.cs.uiuc.edu>



Changes in directory llvm/include/llvm/CodeGen:

SelectionDAGISel.h updated: 1.6 -> 1.7
---
Log message:

add a method


---
Diffs of the changes:  (+5 -0)

 SelectionDAGISel.h |    5 +++++
 1 files changed, 5 insertions(+)


Index: llvm/include/llvm/CodeGen/SelectionDAGISel.h
diff -u llvm/include/llvm/CodeGen/SelectionDAGISel.h:1.6 llvm/include/llvm/CodeGen/SelectionDAGISel.h:1.7
--- llvm/include/llvm/CodeGen/SelectionDAGISel.h:1.6	Wed Aug 17 01:46:50 2005
+++ llvm/include/llvm/CodeGen/SelectionDAGISel.h	Thu Aug 18 13:44:33 2005
@@ -49,6 +49,11 @@
   virtual void EmitFunctionEntryCode(Function &Fn, MachineFunction &MF) {}
   virtual void InstructionSelectBasicBlock(SelectionDAG &SD) = 0;
 
+protected:
+  /// Pick a safe ordering and emit instructions for each target node in the
+  /// graph.
+  void ScheduleAndEmitDAG(SelectionDAG &SD);
+  
 private:
   SDOperand CopyValueToVirtualRegister(SelectionDAGLowering &SDL,
                                        Value *V, unsigned Reg);





From lattner at cs.uiuc.edu  Thu Aug 18 13:45:36 2005
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Thu, 18 Aug 2005 13:45:36 -0500
Subject: [llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp 
Message-ID: <200508181845.NAA23549@zion.cs.uiuc.edu>



Changes in directory llvm/lib/CodeGen/SelectionDAG:

ScheduleDAG.cpp added (r1.1)
---
Log message:

new file, obviously just a stub


---
Diffs of the changes:  (+23 -0)

 ScheduleDAG.cpp |   23 +++++++++++++++++++++++
 1 files changed, 23 insertions(+)


Index: llvm/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp
diff -c /dev/null llvm/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp:1.1
*** /dev/null	Thu Aug 18 13:45:34 2005
--- llvm/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp	Thu Aug 18 13:45:24 2005
***************
*** 0 ****
--- 1,23 ----
+ //===-- ScheduleDAG.cpp - Implement a trivial DAG scheduler ---------------===//
+ //
+ //                     The LLVM Compiler Infrastructure
+ //
+ // This file was developed by Chris Lattner and is distributed under the
+ // University of Illinois Open Source License. See LICENSE.TXT for details.
+ //
+ //===----------------------------------------------------------------------===//
+ //
+ // This implements a simple code linearizer for DAGs.  This is not a very good
+ // way to emit code, but gets working code quickly.
+ //
+ //===----------------------------------------------------------------------===//
+ 
+ #define DEBUG_TYPE "sched"
+ #include "llvm/CodeGen/SelectionDAGISel.h"
+ using namespace llvm;
+ 
+ /// Pick a safe ordering and emit instructions for each target node in the
+ /// graph.
+ void SelectionDAGISel::ScheduleAndEmitDAG(SelectionDAG &SD) {
+   
+ }





From lattner at cs.uiuc.edu  Thu Aug 18 13:46:18 2005
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Thu, 18 Aug 2005 13:46:18 -0500
Subject: [llvm-commits] CVS: llvm/lib/Target/PowerPC/PPC32ISelDAGToDAG.cpp 
Message-ID: <200508181846.NAA23612@zion.cs.uiuc.edu>



Changes in directory llvm/lib/Target/PowerPC:

PPC32ISelDAGToDAG.cpp updated: 1.10 -> 1.11
---
Log message:

After selecting the instructions for a basic block, emit the instructions


---
Diffs of the changes:  (+5 -1)

 PPC32ISelDAGToDAG.cpp |    6 +++++-
 1 files changed, 5 insertions(+), 1 deletion(-)


Index: llvm/lib/Target/PowerPC/PPC32ISelDAGToDAG.cpp
diff -u llvm/lib/Target/PowerPC/PPC32ISelDAGToDAG.cpp:1.10 llvm/lib/Target/PowerPC/PPC32ISelDAGToDAG.cpp:1.11
--- llvm/lib/Target/PowerPC/PPC32ISelDAGToDAG.cpp:1.10	Thu Aug 18 13:34:00 2005
+++ llvm/lib/Target/PowerPC/PPC32ISelDAGToDAG.cpp	Thu Aug 18 13:46:06 2005
@@ -58,10 +58,14 @@
     /// SelectionDAGISel when it has created a SelectionDAG for us to codegen.
     virtual void InstructionSelectBasicBlock(SelectionDAG &DAG) {
       DEBUG(BB->dump());
-      // Codegen the basic block.
+      // Select target instructions for the DAG.
       Select(DAG.getRoot());
       DAG.RemoveDeadNodes();
+      
       DAG.viewGraph();
+
+      // Emit machine code to BB. 
+      ScheduleAndEmitDAG(DAG);
     }
  
     virtual const char *getPassName() const {





From jlaskey at apple.com  Thu Aug 18 13:58:34 2005
From: jlaskey at apple.com (Jim Laskey)
Date: Thu, 18 Aug 2005 13:58:34 -0500
Subject: [llvm-commits] CVS: llvm/lib/Target/PowerPC/PPC32ISelPattern.cpp 
Message-ID: <200508181858.NAA23765@zion.cs.uiuc.edu>



Changes in directory llvm/lib/Target/PowerPC:

PPC32ISelPattern.cpp updated: 1.153 -> 1.154
---
Log message:

More optimal solution for loading constants.



---
Diffs of the changes:  (+11 -9)

 PPC32ISelPattern.cpp |   20 +++++++++++---------
 1 files changed, 11 insertions(+), 9 deletions(-)


Index: llvm/lib/Target/PowerPC/PPC32ISelPattern.cpp
diff -u llvm/lib/Target/PowerPC/PPC32ISelPattern.cpp:1.153 llvm/lib/Target/PowerPC/PPC32ISelPattern.cpp:1.154
--- llvm/lib/Target/PowerPC/PPC32ISelPattern.cpp:1.153	Thu Aug 18 13:14:49 2005
+++ llvm/lib/Target/PowerPC/PPC32ISelPattern.cpp	Thu Aug 18 13:58:23 2005
@@ -1719,16 +1719,18 @@
     assert(N.getValueType() == MVT::i32 &&
            "Only i32 constants are legal on this target!");
     unsigned v = (unsigned)cast<ConstantSDNode>(N)->getValue();
-    unsigned Hi = HA16(v);
-    unsigned Lo = Lo16(v);
-    if (Hi && Lo) {
-      Tmp1 = MakeIntReg();
-      BuildMI(BB, PPC::LIS, 1, Tmp1).addSImm(v >> 16);
-      BuildMI(BB, PPC::ORI, 2, Result).addReg(Tmp1).addImm(Lo);
-    } else if (Hi) {
-      BuildMI(BB, PPC::LIS, 1, Result).addSImm(v >> 16);
+    if (isInt16(v)) {
+      BuildMI(BB, PPC::LI, 1, Result).addSImm(Lo16(v));
     } else {
-      BuildMI(BB, PPC::LI, 1, Result).addSImm(Lo);
+      unsigned Hi = Hi16(v);
+      unsigned Lo = Lo16(v);
+      if (Lo) {
+        Tmp1 = MakeIntReg();
+        BuildMI(BB, PPC::LIS, 1, Tmp1).addSImm(Hi);
+        BuildMI(BB, PPC::ORI, 2, Result).addReg(Tmp1).addImm(Lo);
+      } else {
+        BuildMI(BB, PPC::LIS, 1, Result).addSImm(Hi);
+      }
     }
     return Result;
   }





From jlaskey at apple.com  Thu Aug 18 14:32:58 2005
From: jlaskey at apple.com (Jim Laskey)
Date: Thu, 18 Aug 2005 14:32:58 -0500
Subject: [llvm-commits] 
	CVS: llvm/test/Regression/CodeGen/PowerPC/constants.ll
Message-ID: <200508181932.OAA24016@zion.cs.uiuc.edu>



Changes in directory llvm/test/Regression/CodeGen/PowerPC:

constants.ll added (r1.1)
---
Log message:

Add regression test to make sure that constants are generated optimally.



---
Diffs of the changes:  (+51 -0)

 constants.ll |   51 +++++++++++++++++++++++++++++++++++++++++++++++++++
 1 files changed, 51 insertions(+)


Index: llvm/test/Regression/CodeGen/PowerPC/constants.ll
diff -c /dev/null llvm/test/Regression/CodeGen/PowerPC/constants.ll:1.1
*** /dev/null	Thu Aug 18 14:32:56 2005
--- llvm/test/Regression/CodeGen/PowerPC/constants.ll	Thu Aug 18 14:32:46 2005
***************
*** 0 ****
--- 1,51 ----
+ ; All of these ands and shifts should be folded into constants's
+ ; RUN: llvm-as < constants.ll | llc -march=ppc32 | grep lis | wc -l | grep 5 &&
+ ; RUN: llvm-as < constants.ll | llc -march=ppc32 | grep ori | wc -l | grep 3 &&
+ ; RUN: llvm-as < constants.ll | llc -march=ppc32 | grep li | wc -l | grep 18
+ 
+ implementation   ; Functions:
+ 
+ int %_Z2f1v() {
+ entry:
+         ret int 1
+ }
+ 
+ int %_Z2f2v() {
+ entry:
+         ret int -1
+ }
+ 
+ int %_Z2f3v() {
+ entry:
+         ret int 0
+ }
+ 
+ int %_Z2f4v() {
+ entry:
+         ret int 32767
+ }
+ 
+ int %_Z2f5v() {
+ entry:
+         ret int 65535
+ }
+ 
+ int %_Z2f6v() {
+ entry:
+         ret int 65536
+ }
+ 
+ int %_Z2f7v() {
+ entry:
+         ret int 131071
+ }
+ 
+ int %_Z2f8v() {
+ entry:
+         ret int 2147483647
+ }
+ 
+ int %_Z2f9v() {
+ entry:
+         ret int -2147483648
+ }





From jlaskey at apple.com  Thu Aug 18 14:39:08 2005
From: jlaskey at apple.com (Jim Laskey)
Date: Thu, 18 Aug 2005 14:39:08 -0500
Subject: [llvm-commits] 
	CVS: llvm/test/Regression/CodeGen/PowerPC/constants.ll
Message-ID: <200508181939.OAA24148@zion.cs.uiuc.edu>



Changes in directory llvm/test/Regression/CodeGen/PowerPC:

constants.ll updated: 1.1 -> 1.2
---
Log message:

1. Fix comment.

2. Get an exact count of 'li ' instructions.


---
Diffs of the changes:  (+4 -4)

 constants.ll |    8 ++++----
 1 files changed, 4 insertions(+), 4 deletions(-)


Index: llvm/test/Regression/CodeGen/PowerPC/constants.ll
diff -u llvm/test/Regression/CodeGen/PowerPC/constants.ll:1.1 llvm/test/Regression/CodeGen/PowerPC/constants.ll:1.2
--- llvm/test/Regression/CodeGen/PowerPC/constants.ll:1.1	Thu Aug 18 14:32:46 2005
+++ llvm/test/Regression/CodeGen/PowerPC/constants.ll	Thu Aug 18 14:38:57 2005
@@ -1,7 +1,7 @@
-; All of these ands and shifts should be folded into constants's
-; RUN: llvm-as < constants.ll | llc -march=ppc32 | grep lis | wc -l | grep 5 &&
-; RUN: llvm-as < constants.ll | llc -march=ppc32 | grep ori | wc -l | grep 3 &&
-; RUN: llvm-as < constants.ll | llc -march=ppc32 | grep li | wc -l | grep 18
+; All of these routines should be perform optimal load of constants.
+; RUN: llvm-as < constants.ll | llc -march=ppc32 | grep lis   | wc -l | grep 5 &&
+; RUN: llvm-as < constants.ll | llc -march=ppc32 | grep ori   | wc -l | grep 3 &&
+; RUN: llvm-as < constants.ll | llc -march=ppc32 | grep 'li ' | wc -l | grep 4
 
 implementation   ; Functions:
 





From lattner at cs.uiuc.edu  Thu Aug 18 14:45:49 2005
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Thu, 18 Aug 2005 14:45:49 -0500
Subject: [llvm-commits] CVS: llvm/utils/TableGen/InstrInfoEmitter.cpp 
Message-ID: <200508181945.OAA24237@zion.cs.uiuc.edu>



Changes in directory llvm/utils/TableGen:

InstrInfoEmitter.cpp updated: 1.18 -> 1.19
---
Log message:

Fill in the numOperands field of the TargetInstrDescriptor struct from the
.td file.


---
Diffs of the changes:  (+1 -1)

 InstrInfoEmitter.cpp |    2 +-
 1 files changed, 1 insertion(+), 1 deletion(-)


Index: llvm/utils/TableGen/InstrInfoEmitter.cpp
diff -u llvm/utils/TableGen/InstrInfoEmitter.cpp:1.18 llvm/utils/TableGen/InstrInfoEmitter.cpp:1.19
--- llvm/utils/TableGen/InstrInfoEmitter.cpp:1.18	Thu Apr 21 19:00:35 2005
+++ llvm/utils/TableGen/InstrInfoEmitter.cpp	Thu Aug 18 14:45:37 2005
@@ -102,7 +102,7 @@
     OS << Inst.TheDef->getName();
   else
     OS << Inst.Name;
-  OS << "\",\t-1, -1, 0, false, 0, 0, 0, 0";
+  OS << "\",\t" << Inst.OperandList.size() << ", -1, 0, false, 0, 0, 0, 0";
 
   // Emit all of the target indepedent flags...
   if (Inst.isReturn)     OS << "|M_RET_FLAG";





From lattner at cs.uiuc.edu  Thu Aug 18 14:52:17 2005
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Thu, 18 Aug 2005 14:52:17 -0500
Subject: [llvm-commits] CVS: llvm/Xcode/LLVM.xcodeproj/project.pbxproj 
Message-ID: <200508181952.OAA24387@zion.cs.uiuc.edu>



Changes in directory llvm/Xcode/LLVM.xcodeproj:

project.pbxproj updated: 1.3 -> 1.4
---
Log message:

Add ScheduleDAG.cpp to the project


---
Diffs of the changes:  (+2 -0)

 project.pbxproj |    2 ++
 1 files changed, 2 insertions(+)


Index: llvm/Xcode/LLVM.xcodeproj/project.pbxproj
diff -u llvm/Xcode/LLVM.xcodeproj/project.pbxproj:1.3 llvm/Xcode/LLVM.xcodeproj/project.pbxproj:1.4
--- llvm/Xcode/LLVM.xcodeproj/project.pbxproj:1.3	Wed Aug 17 18:57:24 2005
+++ llvm/Xcode/LLVM.xcodeproj/project.pbxproj	Thu Aug 18 14:52:06 2005
@@ -868,6 +868,7 @@
 		DE66F41508ABF37000323D32 /* HowToUseJIT.cpp */ = {isa = PBXFileReference; fileEncoding = 30; lastKnownFileType = sourcecode.cpp.cpp; name = HowToUseJIT.cpp; path = HowToUseJIT/HowToUseJIT.cpp; sourceTree = "<group>"; };
 		DE66F41E08ABF37000323D32 /* ModuleMaker.cpp */ = {isa = PBXFileReference; fileEncoding = 30; lastKnownFileType = sourcecode.cpp.cpp; name = ModuleMaker.cpp; path = ModuleMaker/ModuleMaker.cpp; sourceTree = "<group>"; };
 		DE66F42608ABF37000323D32 /* ParallelJIT.cpp */ = {isa = PBXFileReference; fileEncoding = 30; lastKnownFileType = sourcecode.cpp.cpp; name = ParallelJIT.cpp; path = ParallelJIT/ParallelJIT.cpp; sourceTree = "<group>"; };
+		DE694D9F08B51E0C0039C106 /* ScheduleDAG.cpp */ = {isa = PBXFileReference; fileEncoding = 30; lastKnownFileType = sourcecode.cpp.cpp; path = ScheduleDAG.cpp; sourceTree = "<group>"; };
 /* End PBXFileReference section */
 
 /* Begin PBXGroup section */
@@ -1083,6 +1084,7 @@
 		DE66ED8308ABEC2B00323D32 /* SelectionDAG */ = {
 			isa = PBXGroup;
 			children = (
+				DE694D9F08B51E0C0039C106 /* ScheduleDAG.cpp */,
 				DE66ED9008ABEC2B00323D32 /* LegalizeDAG.cpp */,
 				DE66ED9208ABEC2B00323D32 /* SelectionDAG.cpp */,
 				DE66ED9308ABEC2B00323D32 /* SelectionDAGISel.cpp */,





From jlaskey at apple.com  Thu Aug 18 15:06:20 2005
From: jlaskey at apple.com (Jim Laskey)
Date: Thu, 18 Aug 2005 15:06:20 -0500
Subject: [llvm-commits] 
	CVS: llvm/test/Regression/CodeGen/PowerPC/constants.ll
Message-ID: <200508182006.PAA24510@zion.cs.uiuc.edu>



Changes in directory llvm/test/Regression/CodeGen/PowerPC:

constants.ll updated: 1.2 -> 1.3
---
Log message:

Unmangled names.



---
Diffs of the changes:  (+9 -9)

 constants.ll |   18 +++++++++---------
 1 files changed, 9 insertions(+), 9 deletions(-)


Index: llvm/test/Regression/CodeGen/PowerPC/constants.ll
diff -u llvm/test/Regression/CodeGen/PowerPC/constants.ll:1.2 llvm/test/Regression/CodeGen/PowerPC/constants.ll:1.3
--- llvm/test/Regression/CodeGen/PowerPC/constants.ll:1.2	Thu Aug 18 14:38:57 2005
+++ llvm/test/Regression/CodeGen/PowerPC/constants.ll	Thu Aug 18 15:06:09 2005
@@ -5,47 +5,47 @@
 
 implementation   ; Functions:
 
-int %_Z2f1v() {
+int %f1() {
 entry:
         ret int 1
 }
 
-int %_Z2f2v() {
+int %f2() {
 entry:
         ret int -1
 }
 
-int %_Z2f3v() {
+int %f3() {
 entry:
         ret int 0
 }
 
-int %_Z2f4v() {
+int %f4() {
 entry:
         ret int 32767
 }
 
-int %_Z2f5v() {
+int %f5() {
 entry:
         ret int 65535
 }
 
-int %_Z2f6v() {
+int %f6() {
 entry:
         ret int 65536
 }
 
-int %_Z2f7v() {
+int %f7() {
 entry:
         ret int 131071
 }
 
-int %_Z2f8v() {
+int %f8() {
 entry:
         ret int 2147483647
 }
 
-int %_Z2f9v() {
+int %f9() {
 entry:
         ret int -2147483648
 }





From lattner at cs.uiuc.edu  Thu Aug 18 15:08:10 2005
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Thu, 18 Aug 2005 15:08:10 -0500
Subject: [llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp 
Message-ID: <200508182008.PAA24603@zion.cs.uiuc.edu>



Changes in directory llvm/lib/CodeGen/SelectionDAG:

ScheduleDAG.cpp updated: 1.1 -> 1.2
---
Log message:

Implement the first chunk of a code emitter.  This is sophisticated enough to
codegen:

_empty:
.LBB_empty_0:   ; 
        blr

but can't do anything more (yet). :)



---
Diffs of the changes:  (+94 -1)

 ScheduleDAG.cpp |   95 +++++++++++++++++++++++++++++++++++++++++++++++++++++++-
 1 files changed, 94 insertions(+), 1 deletion(-)


Index: llvm/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp:1.1 llvm/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp:1.2
--- llvm/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp:1.1	Thu Aug 18 13:45:24 2005
+++ llvm/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp	Thu Aug 18 15:07:59 2005
@@ -14,10 +14,103 @@
 
 #define DEBUG_TYPE "sched"
 #include "llvm/CodeGen/SelectionDAGISel.h"
+#include "llvm/CodeGen/SelectionDAG.h"
+#include "llvm/Target/TargetMachine.h"
+#include "llvm/Target/TargetInstrInfo.h"
 using namespace llvm;
 
+namespace {
+  class SimpleSched {
+    SelectionDAG &DAG;
+    MachineBasicBlock *BB;
+    const TargetMachine &TM;
+    const TargetInstrInfo &TII;
+    
+    std::map<SDNode *, unsigned> EmittedOps;
+  public:
+    SimpleSched(SelectionDAG &D, MachineBasicBlock *bb)
+      : DAG(D), BB(bb), TM(D.getTarget()), TII(*TM.getInstrInfo()) {
+      assert(&TII && "Target doesn't provide instr info?");
+    }
+    
+    void Run() {
+      Emit(DAG.getRoot());
+    }
+    
+  private:
+    unsigned Emit(SDOperand Op);
+  };
+}
+
+unsigned SimpleSched::Emit(SDOperand Op) {
+  // Check to see if we have already emitted this.  If so, return the value
+  // already emitted.  Note that if a node has a single use it cannot be
+  // revisited, so don't bother putting it in the map.
+  unsigned *OpSlot;
+  if (Op.Val->hasOneUse()) {
+    OpSlot = 0;  // No reuse possible.
+  } else {
+    std::map<SDNode *, unsigned>::iterator OpI = EmittedOps.lower_bound(Op.Val);
+    if (OpI != EmittedOps.end() && OpI->first == Op.Val)
+      return OpI->second + Op.ResNo;
+    OpSlot = &EmittedOps.insert(OpI, std::make_pair(Op.Val, 0))->second;
+  }
+  
+  unsigned ResultReg = 0;
+  if (Op.isTargetOpcode()) {
+    unsigned Opc = Op.getTargetOpcode();
+    const TargetInstrDescriptor &II = TII.get(Opc);
+
+    // Target nodes have any register or immediate operands before any chain
+    // nodes.  Check that the DAG matches the TD files's expectation of #
+    // operands.
+    assert((unsigned(II.numOperands) == Op.getNumOperands() ||
+            // It could be some number of operands followed by a token chain.
+           (unsigned(II.numOperands)+1 == Op.getNumOperands() &&
+            Op.getOperand(II.numOperands).getValueType() == MVT::Other)) &&
+           "#operands for dag node doesn't match .td file!"); 
+
+    // Create the new machine instruction.
+    MachineInstr *MI = new MachineInstr(Opc, II.numOperands, true, true);
+    
+    // Add result register values for things that are defined by this
+    // instruction.
+    assert(Op.Val->getNumValues() == 1 &&
+           Op.getValue(0).getValueType() == MVT::Other &&
+           "Return values not implemented yet");
+    
+    // Emit all of the operands of this instruction, adding them to the
+    // instruction as appropriate.
+    for (unsigned i = 0, e = Op.getNumOperands(); i != e; ++i) {
+      if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(i))) {
+        MI->addZeroExtImm64Operand(C->getValue());
+      } else if (RegisterSDNode*R =dyn_cast<RegisterSDNode>(Op.getOperand(i))) {
+        MI->addRegOperand(R->getReg(), MachineOperand::Use);
+      } else {
+        unsigned R = Emit(Op.getOperand(i));
+        // Add an operand, unless this corresponds to a chain node.
+        if (Op.getOperand(i).getValueType() != MVT::Other)
+          MI->addRegOperand(R, MachineOperand::Use);
+      }
+    }
+
+    // Now that we have emitted all operands, emit this instruction itself.
+    BB->insert(BB->end(), MI);
+  } else {
+    switch (Op.getOpcode()) {
+    default: assert(0 &&
+                    "This target-independent node should have been selected!");
+    case ISD::EntryToken: break;
+    }
+  }
+  
+  if (OpSlot) *OpSlot = ResultReg;
+  return ResultReg+Op.ResNo;
+}
+
+
 /// Pick a safe ordering and emit instructions for each target node in the
 /// graph.
 void SelectionDAGISel::ScheduleAndEmitDAG(SelectionDAG &SD) {
-  
+  SimpleSched(SD, BB).Run();  
 }





From lattner at cs.uiuc.edu  Thu Aug 18 15:09:05 2005
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Thu, 18 Aug 2005 15:09:05 -0500
Subject: [llvm-commits] CVS: llvm/lib/Target/PowerPC/PPC32ISelDAGToDAG.cpp 
Message-ID: <200508182009.PAA24640@zion.cs.uiuc.edu>



Changes in directory llvm/lib/Target/PowerPC:

PPC32ISelDAGToDAG.cpp updated: 1.11 -> 1.12
---
Log message:

Move this to the emitter


---
Diffs of the changes:  (+0 -2)

 PPC32ISelDAGToDAG.cpp |    2 --
 1 files changed, 2 deletions(-)


Index: llvm/lib/Target/PowerPC/PPC32ISelDAGToDAG.cpp
diff -u llvm/lib/Target/PowerPC/PPC32ISelDAGToDAG.cpp:1.11 llvm/lib/Target/PowerPC/PPC32ISelDAGToDAG.cpp:1.12
--- llvm/lib/Target/PowerPC/PPC32ISelDAGToDAG.cpp:1.11	Thu Aug 18 13:46:06 2005
+++ llvm/lib/Target/PowerPC/PPC32ISelDAGToDAG.cpp	Thu Aug 18 15:08:53 2005
@@ -62,8 +62,6 @@
       Select(DAG.getRoot());
       DAG.RemoveDeadNodes();
       
-      DAG.viewGraph();
-
       // Emit machine code to BB. 
       ScheduleAndEmitDAG(DAG);
     }





From lattner at cs.uiuc.edu  Thu Aug 18 15:12:01 2005
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Thu, 18 Aug 2005 15:12:01 -0500
Subject: [llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp 
Message-ID: <200508182012.PAA24728@zion.cs.uiuc.edu>



Changes in directory llvm/lib/CodeGen/SelectionDAG:

ScheduleDAG.cpp updated: 1.2 -> 1.3
---
Log message:

add a new -view-sched-dags option to view dags as they are sent to the scheduler.


---
Diffs of the changes:  (+10 -0)

 ScheduleDAG.cpp |   10 ++++++++++
 1 files changed, 10 insertions(+)


Index: llvm/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp:1.2 llvm/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp:1.3
--- llvm/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp:1.2	Thu Aug 18 15:07:59 2005
+++ llvm/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp	Thu Aug 18 15:11:49 2005
@@ -17,8 +17,17 @@
 #include "llvm/CodeGen/SelectionDAG.h"
 #include "llvm/Target/TargetMachine.h"
 #include "llvm/Target/TargetInstrInfo.h"
+#include "llvm/Support/CommandLine.h"
 using namespace llvm;
 
+#ifndef _NDEBUG
+static cl::opt<bool>
+ViewDAGs("view-sched-dags", cl::Hidden,
+         cl::desc("Pop up a window to show sched dags as they are processed"));
+#else
+static const bool ViewDAGS = 0;
+#endif
+
 namespace {
   class SimpleSched {
     SelectionDAG &DAG;
@@ -112,5 +121,6 @@
 /// Pick a safe ordering and emit instructions for each target node in the
 /// graph.
 void SelectionDAGISel::ScheduleAndEmitDAG(SelectionDAG &SD) {
+  if (ViewDAGs) SD.viewGraph();
   SimpleSched(SD, BB).Run();  
 }





From lattner at cs.uiuc.edu  Thu Aug 18 16:36:58 2005
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Thu, 18 Aug 2005 16:36:58 -0500
Subject: [llvm-commits] CVS: llvm/utils/TableGen/InstrInfoEmitter.cpp
	InstrInfoEmitter.h 
Message-ID: <200508182136.QAA30520@zion.cs.uiuc.edu>



Changes in directory llvm/utils/TableGen:

InstrInfoEmitter.cpp updated: 1.19 -> 1.20
InstrInfoEmitter.h updated: 1.8 -> 1.9
---
Log message:

When emitting implicit use/def lists, only emit each unique list once.  Though
LLVM is able to merge identical static const globals, GCC isn't, and this caused
some bloat in the generated data.  This has a marginal effect on PPC, shrinking
the implicit sets from 10->4, but shrinks X86 from 179 to 23, a much bigger
reduction.

This should speed up the register allocator as well by reducing the dcache
footprint for this static data.



---
Diffs of the changes:  (+47 -20)

 InstrInfoEmitter.cpp |   59 +++++++++++++++++++++++++++++++++++----------------
 InstrInfoEmitter.h   |    8 +++++-
 2 files changed, 47 insertions(+), 20 deletions(-)


Index: llvm/utils/TableGen/InstrInfoEmitter.cpp
diff -u llvm/utils/TableGen/InstrInfoEmitter.cpp:1.19 llvm/utils/TableGen/InstrInfoEmitter.cpp:1.20
--- llvm/utils/TableGen/InstrInfoEmitter.cpp:1.19	Thu Aug 18 14:45:37 2005
+++ llvm/utils/TableGen/InstrInfoEmitter.cpp	Thu Aug 18 16:36:47 2005
@@ -46,14 +46,21 @@
   OS << "} // End llvm namespace \n";
 }
 
-void InstrInfoEmitter::printDefList(ListInit *LI, const std::string &Name,
-                                    std::ostream &OS) const {
-  OS << "static const unsigned " << Name << "[] = { ";
-  for (unsigned j = 0, e = LI->getSize(); j != e; ++j)
-    if (DefInit *DI = dynamic_cast<DefInit*>(LI->getElement(j)))
-      OS << getQualifiedName(DI->getDef()) << ", ";
+static std::vector<Record*> GetDefList(ListInit *LI, const std::string &Name) {
+  std::vector<Record*> Result;
+  for (unsigned i = 0, e = LI->getSize(); i != e; ++i)
+    if (DefInit *DI = dynamic_cast<DefInit*>(LI->getElement(i)))
+      Result.push_back(DI->getDef());
     else
       throw "Illegal value in '" + Name + "' list!";
+  return Result;
+}
+
+void InstrInfoEmitter::printDefList(const std::vector<Record*> &Uses,
+                                    unsigned Num, std::ostream &OS) const {
+  OS << "static const unsigned ImplicitList" << Num << "[] = { ";
+  for (unsigned i = 0, e = Uses.size(); i != e; ++i)
+    OS << getQualifiedName(Uses[i]) << ", ";
   OS << "0 };\n";
 }
 
@@ -69,34 +76,50 @@
   Record *PHI = InstrInfo->getValueAsDef("PHIInst");
 
   // Emit empty implicit uses and defs lists
-  OS << "static const unsigned EmptyImpUses[] = { 0 };\n"
-     << "static const unsigned EmptyImpDefs[] = { 0 };\n";
+  OS << "static const unsigned EmptyImpList[] = { 0 };\n";
 
-  // Emit all of the instruction's implicit uses and defs...
+  // Keep track of all of the def lists we have emitted already.
+  std::map<std::vector<Record*>, unsigned> EmittedLists;
+  std::map<ListInit*, unsigned> ListNumbers;
+  unsigned ListNumber = 0;
+ 
+  // Emit all of the instruction's implicit uses and defs.
   for (CodeGenTarget::inst_iterator II = Target.inst_begin(),
          E = Target.inst_end(); II != E; ++II) {
     Record *Inst = II->second.TheDef;
     ListInit *LI = Inst->getValueAsListInit("Uses");
-    if (LI->getSize()) printDefList(LI, Inst->getName()+"ImpUses", OS);
+    if (LI->getSize()) {
+      std::vector<Record*> Uses = GetDefList(LI, Inst->getName());
+      unsigned &IL = EmittedLists[Uses];
+      if (!IL) printDefList(Uses, IL = ++ListNumber, OS);
+      ListNumbers[LI] = IL;
+    }
     LI = Inst->getValueAsListInit("Defs");
-    if (LI->getSize()) printDefList(LI, Inst->getName()+"ImpDefs", OS);
+    if (LI->getSize()) {
+      std::vector<Record*> Uses = GetDefList(LI, Inst->getName());
+      unsigned &IL = EmittedLists[Uses];
+      if (!IL) printDefList(Uses, IL = ++ListNumber, OS);
+      ListNumbers[LI] = IL;
+    }
   }
 
   OS << "\nstatic const TargetInstrDescriptor " << TargetName
      << "Insts[] = {\n";
-  emitRecord(Target.getPHIInstruction(), 0, InstrInfo, OS);
+  emitRecord(Target.getPHIInstruction(), 0, InstrInfo, ListNumbers, OS);
 
   unsigned i = 0;
   for (CodeGenTarget::inst_iterator II = Target.inst_begin(),
          E = Target.inst_end(); II != E; ++II)
     if (II->second.TheDef != PHI)
-      emitRecord(II->second, ++i, InstrInfo, OS);
+      emitRecord(II->second, ++i, InstrInfo, ListNumbers, OS);
   OS << "};\n";
   OS << "} // End llvm namespace \n";
 }
 
 void InstrInfoEmitter::emitRecord(const CodeGenInstruction &Inst, unsigned Num,
-                                  Record *InstrInfo, std::ostream &OS) {
+                                  Record *InstrInfo,
+                                  std::map<ListInit*, unsigned> &ListNumbers,
+                                  std::ostream &OS) {
   OS << "  { \"";
   if (Inst.Name.empty())
     OS << Inst.TheDef->getName();
@@ -134,15 +157,15 @@
   // Emit the implicit uses and defs lists...
   LI = Inst.TheDef->getValueAsListInit("Uses");
   if (!LI->getSize())
-    OS << "EmptyImpUses, ";
+    OS << "EmptyImpList, ";
   else
-    OS << Inst.TheDef->getName() << "ImpUses, ";
+    OS << "ImplicitList" << ListNumbers[LI] << ", ";
 
   LI = Inst.TheDef->getValueAsListInit("Defs");
   if (!LI->getSize())
-    OS << "EmptyImpDefs ";
+    OS << "EmptyImpList ";
   else
-    OS << Inst.TheDef->getName() << "ImpDefs ";
+    OS << "ImplicitList" << ListNumbers[LI] << " ";
 
   OS << " },  // Inst #" << Num << " = " << Inst.TheDef->getName() << "\n";
 }


Index: llvm/utils/TableGen/InstrInfoEmitter.h
diff -u llvm/utils/TableGen/InstrInfoEmitter.h:1.8 llvm/utils/TableGen/InstrInfoEmitter.h:1.9
--- llvm/utils/TableGen/InstrInfoEmitter.h:1.8	Thu Apr 21 19:00:35 2005
+++ llvm/utils/TableGen/InstrInfoEmitter.h	Thu Aug 18 16:36:47 2005
@@ -16,6 +16,8 @@
 #define INSTRINFO_EMITTER_H
 
 #include "TableGenBackend.h"
+#include <vector>
+#include <map>
 
 namespace llvm {
 
@@ -35,10 +37,12 @@
   // runEnums - Print out enum values for all of the instructions.
   void runEnums(std::ostream &OS);
 private:
-  void printDefList(ListInit *LI, const std::string &Name,
+  void printDefList(const std::vector<Record*> &Uses, unsigned Num,
                     std::ostream &OS) const;
   void emitRecord(const CodeGenInstruction &Inst, unsigned Num,
-                  Record *InstrInfo, std::ostream &OS);
+                  Record *InstrInfo, 
+                  std::map<ListInit*, unsigned> &ListNumbers,
+                  std::ostream &OS);
   void emitShiftedValue(Record *R, StringInit *Val, IntInit *Shift,
                         std::ostream &OS);
 };





From lattner at cs.uiuc.edu  Thu Aug 18 17:12:43 2005
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Thu, 18 Aug 2005 17:12:43 -0500
Subject: [llvm-commits] CVS: llvm/utils/TableGen/InstrInfoEmitter.cpp 
Message-ID: <200508182212.RAA30848@zion.cs.uiuc.edu>



Changes in directory llvm/utils/TableGen:

InstrInfoEmitter.cpp updated: 1.20 -> 1.21
---
Log message:

revert this change, which causes breakage, temporarily


---
Diffs of the changes:  (+3 -1)

 InstrInfoEmitter.cpp |    4 +++-
 1 files changed, 3 insertions(+), 1 deletion(-)


Index: llvm/utils/TableGen/InstrInfoEmitter.cpp
diff -u llvm/utils/TableGen/InstrInfoEmitter.cpp:1.20 llvm/utils/TableGen/InstrInfoEmitter.cpp:1.21
--- llvm/utils/TableGen/InstrInfoEmitter.cpp:1.20	Thu Aug 18 16:36:47 2005
+++ llvm/utils/TableGen/InstrInfoEmitter.cpp	Thu Aug 18 17:12:31 2005
@@ -125,7 +125,9 @@
     OS << Inst.TheDef->getName();
   else
     OS << Inst.Name;
-  OS << "\",\t" << Inst.OperandList.size() << ", -1, 0, false, 0, 0, 0, 0";
+  OS << "\",\t" << -1
+     //Inst.OperandList.size()
+     << ", -1, 0, false, 0, 0, 0, 0";
 
   // Emit all of the target indepedent flags...
   if (Inst.isReturn)     OS << "|M_RET_FLAG";





From lattner at cs.uiuc.edu  Thu Aug 18 18:17:18 2005
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Thu, 18 Aug 2005 18:17:18 -0500
Subject: [llvm-commits] CVS: llvm/lib/Target/Target.td 
Message-ID: <200508182317.SAA31144@zion.cs.uiuc.edu>



Changes in directory llvm/lib/Target:

Target.td updated: 1.43 -> 1.44
---
Log message:

Add a new flag


---
Diffs of the changes:  (+4 -0)

 Target.td |    4 ++++
 1 files changed, 4 insertions(+)


Index: llvm/lib/Target/Target.td
diff -u llvm/lib/Target/Target.td:1.43 llvm/lib/Target/Target.td:1.44
--- llvm/lib/Target/Target.td:1.43	Sat Jan  1 20:27:48 2005
+++ llvm/lib/Target/Target.td	Thu Aug 18 18:17:07 2005
@@ -145,6 +145,10 @@
 ///     (ops R32:$dst, R32:$src) or something similar.
 def ops;
 
+/// variable_ops definition - Mark this instruction as taking a variable number
+/// of operands.
+def variable_ops;
+
 /// Operand Types - These provide the built-in operand types that may be used
 /// by a target.  Targets can optionally provide their own operand types as
 /// needed, though this should not be needed for RISC targets.





From lattner at cs.uiuc.edu  Thu Aug 18 18:25:02 2005
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Thu, 18 Aug 2005 18:25:02 -0500
Subject: [llvm-commits] CVS: llvm/lib/Target/PowerPC/PPC32ISelPattern.cpp
	PPC32ISelSimple.cpp PPC32RegisterInfo.cpp 
Message-ID: <200508182325.SAA31220@zion.cs.uiuc.edu>



Changes in directory llvm/lib/Target/PowerPC:

PPC32ISelPattern.cpp updated: 1.154 -> 1.155
PPC32ISelSimple.cpp updated: 1.144 -> 1.145
PPC32RegisterInfo.cpp updated: 1.16 -> 1.17
---
Log message:

MFLR doesn't take an operand, the LR register is implicit


---
Diffs of the changes:  (+3 -3)

 PPC32ISelPattern.cpp  |    2 +-
 PPC32ISelSimple.cpp   |    2 +-
 PPC32RegisterInfo.cpp |    2 +-
 3 files changed, 3 insertions(+), 3 deletions(-)


Index: llvm/lib/Target/PowerPC/PPC32ISelPattern.cpp
diff -u llvm/lib/Target/PowerPC/PPC32ISelPattern.cpp:1.154 llvm/lib/Target/PowerPC/PPC32ISelPattern.cpp:1.155
--- llvm/lib/Target/PowerPC/PPC32ISelPattern.cpp:1.154	Thu Aug 18 13:58:23 2005
+++ llvm/lib/Target/PowerPC/PPC32ISelPattern.cpp	Thu Aug 18 18:24:50 2005
@@ -437,7 +437,7 @@
     MachineBasicBlock::iterator MBBI = FirstMBB.begin();
     GlobalBaseReg = MakeIntReg();
     BuildMI(FirstMBB, MBBI, PPC::MovePCtoLR, 0, PPC::LR);
-    BuildMI(FirstMBB, MBBI, PPC::MFLR, 1, GlobalBaseReg).addReg(PPC::LR);
+    BuildMI(FirstMBB, MBBI, PPC::MFLR, 1, GlobalBaseReg);
     GlobalBaseInitialized = true;
   }
   return GlobalBaseReg;


Index: llvm/lib/Target/PowerPC/PPC32ISelSimple.cpp
diff -u llvm/lib/Target/PowerPC/PPC32ISelSimple.cpp:1.144 llvm/lib/Target/PowerPC/PPC32ISelSimple.cpp:1.145
--- llvm/lib/Target/PowerPC/PPC32ISelSimple.cpp:1.144	Tue Aug  2 14:25:03 2005
+++ llvm/lib/Target/PowerPC/PPC32ISelSimple.cpp	Thu Aug 18 18:24:50 2005
@@ -619,7 +619,7 @@
     MachineBasicBlock::iterator MBBI = FirstMBB.begin();
     GlobalBaseReg = makeAnotherReg(Type::IntTy);
     BuildMI(FirstMBB, MBBI, PPC::MovePCtoLR, 0, PPC::LR);
-    BuildMI(FirstMBB, MBBI, PPC::MFLR, 1, GlobalBaseReg).addReg(PPC::LR);
+    BuildMI(FirstMBB, MBBI, PPC::MFLR, 1, GlobalBaseReg);
     GlobalBaseInitialized = true;
   }
   return GlobalBaseReg;


Index: llvm/lib/Target/PowerPC/PPC32RegisterInfo.cpp
diff -u llvm/lib/Target/PowerPC/PPC32RegisterInfo.cpp:1.16 llvm/lib/Target/PowerPC/PPC32RegisterInfo.cpp:1.17
--- llvm/lib/Target/PowerPC/PPC32RegisterInfo.cpp:1.16	Thu Aug  4 15:49:48 2005
+++ llvm/lib/Target/PowerPC/PPC32RegisterInfo.cpp	Thu Aug 18 18:24:50 2005
@@ -83,7 +83,7 @@
   };
   unsigned OC = Opcode[getIdx(getClass(SrcReg))];
   if (SrcReg == PPC::LR) {
-    BuildMI(MBB, MI, PPC::MFLR, 1, PPC::R11).addReg(PPC::LR);
+    BuildMI(MBB, MI, PPC::MFLR, 1, PPC::R11);
     addFrameReference(BuildMI(MBB, MI, OC, 3).addReg(PPC::R11),FrameIdx);
   } else if (PPC32::CRRCRegisterClass == getClass(SrcReg)) {
     BuildMI(MBB, MI, PPC::MFCR, 0, PPC::R11);





From lattner at cs.uiuc.edu  Thu Aug 18 18:25:45 2005
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Thu, 18 Aug 2005 18:25:45 -0500
Subject: [llvm-commits] CVS: llvm/lib/Target/PowerPC/PowerPCInstrInfo.td 
Message-ID: <200508182325.SAA31255@zion.cs.uiuc.edu>



Changes in directory llvm/lib/Target/PowerPC:

PowerPCInstrInfo.td updated: 1.76 -> 1.77
---
Log message:

Fix operand numbers by marking variable arity nodes as such and by fixing
the operand lists of a few other nodes.


---
Diffs of the changes:  (+9 -8)

 PowerPCInstrInfo.td |   17 +++++++++--------
 1 files changed, 9 insertions(+), 8 deletions(-)


Index: llvm/lib/Target/PowerPC/PowerPCInstrInfo.td
diff -u llvm/lib/Target/PowerPC/PowerPCInstrInfo.td:1.76 llvm/lib/Target/PowerPC/PowerPCInstrInfo.td:1.77
--- llvm/lib/Target/PowerPC/PowerPCInstrInfo.td:1.76	Mon Aug  8 15:04:52 2005
+++ llvm/lib/Target/PowerPC/PowerPCInstrInfo.td	Thu Aug 18 18:25:33 2005
@@ -1,4 +1,3 @@
-
 //===- PowerPCInstrInfo.td - The PowerPC Instruction Set -----*- tablegen -*-=//
 // 
 //                     The LLVM Compiler Infrastructure
@@ -60,18 +59,19 @@
 }
 
 // Pseudo-instructions:
-def PHI : Pseudo<(ops), "; PHI">;
+def PHI : Pseudo<(ops variable_ops), "; PHI">;
 let isLoad = 1 in {
-def ADJCALLSTACKDOWN : Pseudo<(ops), "; ADJCALLSTACKDOWN">;
-def ADJCALLSTACKUP : Pseudo<(ops), "; ADJCALLSTACKUP">;
+def ADJCALLSTACKDOWN : Pseudo<(ops u16imm), "; ADJCALLSTACKDOWN">;
+def ADJCALLSTACKUP : Pseudo<(ops u16imm), "; ADJCALLSTACKUP">;
 }
-def IMPLICIT_DEF : Pseudo<(ops), "; IMPLICIT_DEF">;
+def IMPLICIT_DEF : Pseudo<(ops variable_ops), "; IMPLICIT_DEF">;
 
 let Defs = [LR] in
   def MovePCtoLR : Pseudo<(ops piclabel:$label), "bl $label">;
 
 let isBranch = 1, isTerminator = 1 in {
-  def COND_BRANCH : Pseudo<(ops), "; COND_BRANCH">;
+  def COND_BRANCH : Pseudo<(ops CRRC:$crS, u16imm, target:$true, target:$false),
+                           "; COND_BRANCH">;
   def B   : IForm<18, 0, 0, (ops target:$func), "b $func">;
 //def BA  : IForm<18, 1, 0, (ops target:$func), "ba $func">;
   def BL  : IForm<18, 0, 1, (ops target:$func), "bl $func">;
@@ -100,8 +100,9 @@
           LR,XER,CTR,
           CR0,CR1,CR5,CR6,CR7] in {
   // Convenient aliases for call instructions
-  def CALLpcrel : IForm<18, 0, 1, (ops target:$func), "bl $func">;
-  def CALLindirect : XLForm_2_ext<19, 528, 20, 0, 1, (ops), "bctrl">;
+  def CALLpcrel : IForm<18, 0, 1, (ops target:$func, variable_ops), "bl $func">;
+  def CALLindirect : XLForm_2_ext<19, 528, 20, 0, 1,
+                                  (ops variable_ops), "bctrl">;
 }
 
 // D-Form instructions.  Most instructions that perform an operation on a





From natebegeman at mac.com  Thu Aug 18 18:38:12 2005
From: natebegeman at mac.com (Nate Begeman)
Date: Thu, 18 Aug 2005 18:38:12 -0500
Subject: [llvm-commits] CVS: llvm/lib/Target/PowerPC/PPC32ISelDAGToDAG.cpp 
Message-ID: <200508182338.SAA31329@zion.cs.uiuc.edu>



Changes in directory llvm/lib/Target/PowerPC:

PPC32ISelDAGToDAG.cpp updated: 1.12 -> 1.13
---
Log message:

Add shifts.


---
Diffs of the changes:  (+45 -0)

 PPC32ISelDAGToDAG.cpp |   45 +++++++++++++++++++++++++++++++++++++++++++++
 1 files changed, 45 insertions(+)


Index: llvm/lib/Target/PowerPC/PPC32ISelDAGToDAG.cpp
diff -u llvm/lib/Target/PowerPC/PPC32ISelDAGToDAG.cpp:1.12 llvm/lib/Target/PowerPC/PPC32ISelDAGToDAG.cpp:1.13
--- llvm/lib/Target/PowerPC/PPC32ISelDAGToDAG.cpp:1.12	Thu Aug 18 15:08:53 2005
+++ llvm/lib/Target/PowerPC/PPC32ISelDAGToDAG.cpp	Thu Aug 18 18:38:00 2005
@@ -486,6 +486,51 @@
       CurDAG->SelectNodeTo(N, MVT::i32, PPC::XOR, Select(N->getOperand(0)),
                            Select(N->getOperand(1)));
     break;
+  case ISD::SHL: {
+    unsigned Imm, SH, MB, ME;
+    if (isOpcWithIntImmediate(N->getOperand(0).Val, ISD::AND, Imm) &&
+        isRotateAndMask(N, Imm, true, SH, MB, ME))
+      CurDAG->SelectNodeTo(N, MVT::i32, PPC::RLWINM, 
+                           Select(N->getOperand(0).getOperand(0)),
+                           getI32Imm(SH), getI32Imm(MB), getI32Imm(ME));
+    else if (isIntImmediate(N->getOperand(1), Imm))
+      CurDAG->SelectNodeTo(N, MVT::i32, PPC::RLWINM, Select(N->getOperand(0)),
+                           getI32Imm(Imm), getI32Imm(0), getI32Imm(31-Imm));
+    else
+      CurDAG->SelectNodeTo(N, MVT::i32, PPC::SLW, Select(N->getOperand(0)),
+                           Select(N->getOperand(1)));
+    break;
+  }
+  case ISD::SRL: {
+    unsigned Imm, SH, MB, ME;
+    if (isOpcWithIntImmediate(N->getOperand(0).Val, ISD::AND, Imm) &&
+        isRotateAndMask(N, Imm, true, SH, MB, ME))
+      CurDAG->SelectNodeTo(N, MVT::i32, PPC::RLWINM, 
+                           Select(N->getOperand(0).getOperand(0)),
+                           getI32Imm(SH), getI32Imm(MB), getI32Imm(ME));
+    else if (isIntImmediate(N->getOperand(1), Imm))
+      CurDAG->SelectNodeTo(N, MVT::i32, PPC::RLWINM, Select(N->getOperand(0)),
+                           getI32Imm(32-Imm), getI32Imm(Imm), getI32Imm(31));
+    else
+      CurDAG->SelectNodeTo(N, MVT::i32, PPC::SRW, Select(N->getOperand(0)),
+                           Select(N->getOperand(1)));
+    break;
+  }
+  case ISD::SRA: {
+    unsigned Imm, SH, MB, ME;
+    if (isOpcWithIntImmediate(N->getOperand(0).Val, ISD::AND, Imm) &&
+        isRotateAndMask(N, Imm, true, SH, MB, ME))
+      CurDAG->SelectNodeTo(N, MVT::i32, PPC::RLWINM, 
+                           Select(N->getOperand(0).getOperand(0)),
+                           getI32Imm(SH), getI32Imm(MB), getI32Imm(ME));
+    else if (isIntImmediate(N->getOperand(1), Imm))
+      CurDAG->SelectNodeTo(N, MVT::i32, PPC::SRAWI, Select(N->getOperand(0)), 
+                           getI32Imm(Imm));
+    else
+      CurDAG->SelectNodeTo(N, MVT::i32, PPC::SRAW, Select(N->getOperand(0)),
+                           Select(N->getOperand(1)));
+    break;
+  }
   case ISD::FABS:
     CurDAG->SelectNodeTo(N, N->getValueType(0), PPC::FABS, 
                          Select(N->getOperand(0)));





From lattner at cs.uiuc.edu  Thu Aug 18 18:38:53 2005
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Thu, 18 Aug 2005 18:38:53 -0500
Subject: [llvm-commits] CVS: llvm/utils/TableGen/CodeGenTarget.cpp
	CodeGenInstruction.h 
Message-ID: <200508182338.SAA31364@zion.cs.uiuc.edu>



Changes in directory llvm/utils/TableGen:

CodeGenTarget.cpp updated: 1.28 -> 1.29
CodeGenInstruction.h updated: 1.8 -> 1.9
---
Log message:

Figure out how many operands each instruction has, keep track of whether
or not it's variable.


---
Diffs of the changes:  (+12 -6)

 CodeGenInstruction.h |    7 +++++--
 CodeGenTarget.cpp    |   11 +++++++----
 2 files changed, 12 insertions(+), 6 deletions(-)


Index: llvm/utils/TableGen/CodeGenTarget.cpp
diff -u llvm/utils/TableGen/CodeGenTarget.cpp:1.28 llvm/utils/TableGen/CodeGenTarget.cpp:1.29
--- llvm/utils/TableGen/CodeGenTarget.cpp:1.28	Thu Apr 21 19:00:35 2005
+++ llvm/utils/TableGen/CodeGenTarget.cpp	Thu Aug 18 18:38:41 2005
@@ -237,7 +237,8 @@
   isCommutable = R->getValueAsBit("isCommutable");
   isTerminator = R->getValueAsBit("isTerminator");
   hasDelaySlot = R->getValueAsBit("hasDelaySlot");
-
+  hasVariableNumberOfOperands = false;
+  
   try {
     DagInit *DI = R->getValueAsDag("OperandList");
 
@@ -248,18 +249,20 @@
         MVT::ValueType Ty;
         std::string PrintMethod = "printOperand";
         unsigned NumOps = 1;
-        if (Rec->isSubClassOf("RegisterClass"))
+        if (Rec->isSubClassOf("RegisterClass")) {
           Ty = getValueType(Rec->getValueAsDef("RegType"));
-        else if (Rec->isSubClassOf("Operand")) {
+        } else if (Rec->isSubClassOf("Operand")) {
           Ty = getValueType(Rec->getValueAsDef("Type"));
           PrintMethod = Rec->getValueAsString("PrintMethod");
           NumOps = Rec->getValueAsInt("NumMIOperands");
+        } else if (Rec->getName() == "variable_ops") {
+          hasVariableNumberOfOperands = true;
         } else
           throw "Unknown operand class '" + Rec->getName() +
                 "' in instruction '" + R->getName() + "' instruction!";
 
         OperandList.push_back(OperandInfo(Rec, Ty, DI->getArgName(i),
-                                          PrintMethod, MIOperandNo));
+                                          PrintMethod, MIOperandNo, NumOps));
         MIOperandNo += NumOps;
       } else {
         throw "Illegal operand for the '" + R->getName() + "' instruction!";


Index: llvm/utils/TableGen/CodeGenInstruction.h
diff -u llvm/utils/TableGen/CodeGenInstruction.h:1.8 llvm/utils/TableGen/CodeGenInstruction.h:1.9
--- llvm/utils/TableGen/CodeGenInstruction.h:1.8	Thu Apr 21 19:00:35 2005
+++ llvm/utils/TableGen/CodeGenInstruction.h	Thu Aug 18 18:38:41 2005
@@ -56,10 +56,12 @@
       /// OperandList may not match the MachineInstr operand num.  Until it
       /// does, this contains the MI operand index of this operand.
       unsigned MIOperandNo;
+      unsigned MINumOperands;   // The number of operands.
 
       OperandInfo(Record *R, MVT::ValueType T, const std::string &N,
-                  const std::string &PMN, unsigned MION)
-        : Rec(R), Ty(T), Name(N), PrinterMethodName(PMN), MIOperandNo(MION) {}
+                  const std::string &PMN, unsigned MION, unsigned MINO)
+        : Rec(R), Ty(T), Name(N), PrinterMethodName(PMN), MIOperandNo(MION),
+          MINumOperands(MINO) {}
     };
 
     /// OperandList - The list of declared operands, along with their declared
@@ -78,6 +80,7 @@
     bool isCommutable;
     bool isTerminator;
     bool hasDelaySlot;
+    bool hasVariableNumberOfOperands;
 
     CodeGenInstruction(Record *R, const std::string &AsmStr);
 





From natebegeman at mac.com  Thu Aug 18 18:53:28 2005
From: natebegeman at mac.com (Nate Begeman)
Date: Thu, 18 Aug 2005 18:53:28 -0500
Subject: [llvm-commits] CVS: llvm/lib/Target/X86/X86.h X86TargetMachine.cpp
	X86ISelSimple.cpp 
Message-ID: <200508182353.SAA31519@zion.cs.uiuc.edu>



Changes in directory llvm/lib/Target/X86:

X86.h updated: 1.35 -> 1.36
X86TargetMachine.cpp updated: 1.84 -> 1.85
X86ISelSimple.cpp (r1.322) removed
---
Log message:

Remove the X86 and PowerPC Simple instruction selectors; their time has
passed.


---
Diffs of the changes:  (+4 -16)

 X86.h                |    6 ------
 X86TargetMachine.cpp |   14 ++++----------
 2 files changed, 4 insertions(+), 16 deletions(-)


Index: llvm/lib/Target/X86/X86.h
diff -u llvm/lib/Target/X86/X86.h:1.35 llvm/lib/Target/X86/X86.h:1.36
--- llvm/lib/Target/X86/X86.h:1.35	Mon Jul 11 00:17:48 2005
+++ llvm/lib/Target/X86/X86.h	Thu Aug 18 18:53:15 2005
@@ -32,12 +32,6 @@
 extern X86VectorEnum X86Vector;
 extern bool X86ScalarSSE;
 
-/// createX86SimpleInstructionSelector - This pass converts an LLVM function
-/// into a machine code representation in a very simple peep-hole fashion.  The
-/// generated code sucks but the implementation is nice and simple.
-///
-FunctionPass *createX86SimpleInstructionSelector(TargetMachine &TM);
-
 /// createX86PatternInstructionSelector - This pass converts an LLVM function
 /// into a machine code representation in a more aggressive way.
 ///


Index: llvm/lib/Target/X86/X86TargetMachine.cpp
diff -u llvm/lib/Target/X86/X86TargetMachine.cpp:1.84 llvm/lib/Target/X86/X86TargetMachine.cpp:1.85
--- llvm/lib/Target/X86/X86TargetMachine.cpp:1.84	Wed Jul 27 01:12:34 2005
+++ llvm/lib/Target/X86/X86TargetMachine.cpp	Thu Aug 18 18:53:15 2005
@@ -120,11 +120,8 @@
   // Make sure that no unreachable blocks are instruction selected.
   PM.add(createUnreachableBlockEliminationPass());
 
-  // Default to pattern ISel
-  if (PatternISelTriState == 0)
-    PM.add(createX86SimpleInstructionSelector(*this));
-  else
-    PM.add(createX86PatternInstructionSelector(*this));
+  // Install an instruction selector.
+  PM.add(createX86PatternInstructionSelector(*this));
 
   // Run optional SSA-based machine code optimizations next...
   if (!NoSSAPeephole)
@@ -191,11 +188,8 @@
   // Make sure that no unreachable blocks are instruction selected.
   PM.add(createUnreachableBlockEliminationPass());
 
-  // Default to pattern ISel
-  if (PatternISelTriState == 0)
-    PM.add(createX86SimpleInstructionSelector(TM));
-  else
-    PM.add(createX86PatternInstructionSelector(TM));
+  // Install an instruction selector.
+  PM.add(createX86PatternInstructionSelector(TM));
 
   // Run optional SSA-based machine code optimizations next...
   if (!NoSSAPeephole)





From natebegeman at mac.com  Thu Aug 18 18:53:28 2005
From: natebegeman at mac.com (Nate Begeman)
Date: Thu, 18 Aug 2005 18:53:28 -0500
Subject: [llvm-commits] CVS: llvm/include/llvm/Target/TargetOptions.h 
Message-ID: <200508182353.SAA31513@zion.cs.uiuc.edu>



Changes in directory llvm/include/llvm/Target:

TargetOptions.h updated: 1.5 -> 1.6
---
Log message:

Remove the X86 and PowerPC Simple instruction selectors; their time has
passed.


---
Diffs of the changes:  (+0 -7)

 TargetOptions.h |    7 -------
 1 files changed, 7 deletions(-)


Index: llvm/include/llvm/Target/TargetOptions.h
diff -u llvm/include/llvm/Target/TargetOptions.h:1.5 llvm/include/llvm/Target/TargetOptions.h:1.6
--- llvm/include/llvm/Target/TargetOptions.h:1.5	Fri Apr 29 23:09:37 2005
+++ llvm/include/llvm/Target/TargetOptions.h	Thu Aug 18 18:53:15 2005
@@ -34,13 +34,6 @@
   /// over the place.
   extern bool NoExcessFPPrecision;
 
-  /// PatternISelTriState - This flag is enabled when -pattern-isel=X is
-  /// specified on the command line.  The default value is 2, in which case the
-  /// target chooses what is best for it.  Setting X to 0 forces the use of
-  /// a simple ISel if available, while setting it to 1 forces the use of a
-  /// pattern ISel if available.
-  extern int PatternISelTriState;
-
   /// UnsafeFPMath - This flag is enabled when the
   /// -enable-unsafe-fp-math flag is specified on the command line.  When
   /// this flag is off (the default), the code generator is not allowed to





From natebegeman at mac.com  Thu Aug 18 18:53:28 2005
From: natebegeman at mac.com (Nate Begeman)
Date: Thu, 18 Aug 2005 18:53:28 -0500
Subject: [llvm-commits] CVS: llvm/lib/Target/PowerPC/PowerPC.h
	PowerPCTargetMachine.cpp PPC32ISelSimple.cpp 
Message-ID: <200508182353.SAA31529@zion.cs.uiuc.edu>



Changes in directory llvm/lib/Target/PowerPC:

PowerPC.h updated: 1.20 -> 1.21
PowerPCTargetMachine.cpp updated: 1.64 -> 1.65
PPC32ISelSimple.cpp (r1.145) removed
---
Log message:

Remove the X86 and PowerPC Simple instruction selectors; their time has
passed.


---
Diffs of the changes:  (+4 -14)

 PowerPC.h                |    1 -
 PowerPCTargetMachine.cpp |   17 ++++-------------
 2 files changed, 4 insertions(+), 14 deletions(-)


Index: llvm/lib/Target/PowerPC/PowerPC.h
diff -u llvm/lib/Target/PowerPC/PowerPC.h:1.20 llvm/lib/Target/PowerPC/PowerPC.h:1.21
--- llvm/lib/Target/PowerPC/PowerPC.h:1.20	Wed Aug 17 14:32:03 2005
+++ llvm/lib/Target/PowerPC/PowerPC.h	Thu Aug 18 18:53:15 2005
@@ -27,7 +27,6 @@
 };
 
 FunctionPass *createPPCBranchSelectionPass();
-FunctionPass *createPPC32ISelSimple(TargetMachine &TM);
 FunctionPass *createPPC32ISelPattern(TargetMachine &TM);
 FunctionPass *createPPC32ISelDag(TargetMachine &TM);
 FunctionPass *createDarwinAsmPrinter(std::ostream &OS, TargetMachine &TM);


Index: llvm/lib/Target/PowerPC/PowerPCTargetMachine.cpp
diff -u llvm/lib/Target/PowerPC/PowerPCTargetMachine.cpp:1.64 llvm/lib/Target/PowerPC/PowerPCTargetMachine.cpp:1.65
--- llvm/lib/Target/PowerPC/PowerPCTargetMachine.cpp:1.64	Wed Aug 17 14:33:30 2005
+++ llvm/lib/Target/PowerPC/PowerPCTargetMachine.cpp	Thu Aug 18 18:53:15 2005
@@ -85,13 +85,9 @@
   PM.add(createUnreachableBlockEliminationPass());
 
   // Install an instruction selector.
-  if (EnablePPCDAGDAG) {
+  if (EnablePPCDAGDAG)
     PM.add(createPPC32ISelDag(*this));
-    
-  } else if (PatternISelTriState == 0) {
-    PM.add(createLowerConstantExpressionsPass());
-    PM.add(createPPC32ISelSimple(*this));
-  } else
+  else
     PM.add(createPPC32ISelPattern(*this));
 
   if (PrintMachineCode)
@@ -143,13 +139,8 @@
   // Make sure that no unreachable blocks are instruction selected.
   PM.add(createUnreachableBlockEliminationPass());
 
-  // Default to pattern ISel
-  if (PatternISelTriState == 0) {
-    PM.add(createLowerConstantExpressionsPass());
-    PM.add(createPPC32ISelSimple(TM));
-  } else {
-    PM.add(createPPC32ISelPattern(TM));
-  }
+  // Install an instruction selector.
+  PM.add(createPPC32ISelPattern(TM));
 
   PM.add(createRegisterAllocator());
   PM.add(createPrologEpilogCodeInserter());





From natebegeman at mac.com  Thu Aug 18 18:53:28 2005
From: natebegeman at mac.com (Nate Begeman)
Date: Thu, 18 Aug 2005 18:53:28 -0500
Subject: [llvm-commits] CVS: llvm/lib/Target/TargetMachine.cpp 
Message-ID: <200508182353.SAA31523@zion.cs.uiuc.edu>



Changes in directory llvm/lib/Target:

TargetMachine.cpp updated: 1.40 -> 1.41
---
Log message:

Remove the X86 and PowerPC Simple instruction selectors; their time has
passed.


---
Diffs of the changes:  (+0 -5)

 TargetMachine.cpp |    5 -----
 1 files changed, 5 deletions(-)


Index: llvm/lib/Target/TargetMachine.cpp
diff -u llvm/lib/Target/TargetMachine.cpp:1.40 llvm/lib/Target/TargetMachine.cpp:1.41
--- llvm/lib/Target/TargetMachine.cpp:1.40	Wed Jul  6 13:59:03 2005
+++ llvm/lib/Target/TargetMachine.cpp	Thu Aug 18 18:53:15 2005
@@ -25,7 +25,6 @@
   bool PrintMachineCode;
   bool NoFramePointerElim;
   bool NoExcessFPPrecision;
-  int  PatternISelTriState;
   bool UnsafeFPMath;
   bool PICEnabled;
 };
@@ -44,10 +43,6 @@
                cl::desc("Disable optimizations that may increase FP precision"),
                cl::location(NoExcessFPPrecision),
                cl::init(false));
-  cl::opt<int, true> PatternISel("enable-pattern-isel",
-                    cl::desc("Turn the pattern ISel off(0), on(1), default(2)"),
-                    cl::location(PatternISelTriState),
-                    cl::init(2));
   cl::opt<bool, true>
   EnableUnsafeFPMath("enable-unsafe-fp-math",
                cl::desc("Enable optimizations that may decrease FP precision"),





From lattner at cs.uiuc.edu  Thu Aug 18 19:16:28 2005
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Thu, 18 Aug 2005 19:16:28 -0500
Subject: [llvm-commits] CVS: llvm/lib/Target/X86/X86ISelPattern.cpp 
Message-ID: <200508190016.TAA31741@zion.cs.uiuc.edu>



Changes in directory llvm/lib/Target/X86:

X86ISelPattern.cpp updated: 1.170 -> 1.171
---
Log message:

Stop adding bogus operands to variable shifts on X86.  These instructions
only take one operand.  The other comes implicitly in through CL.


---
Diffs of the changes:  (+2 -2)

 X86ISelPattern.cpp |    4 ++--
 1 files changed, 2 insertions(+), 2 deletions(-)


Index: llvm/lib/Target/X86/X86ISelPattern.cpp
diff -u llvm/lib/Target/X86/X86ISelPattern.cpp:1.170 llvm/lib/Target/X86/X86ISelPattern.cpp:1.171
--- llvm/lib/Target/X86/X86ISelPattern.cpp:1.170	Tue Aug 16 16:56:37 2005
+++ llvm/lib/Target/X86/X86ISelPattern.cpp	Thu Aug 18 19:16:17 2005
@@ -3223,7 +3223,7 @@
     case MVT::i32: Opc = X86::SHL32rCL; break;
     }
     BuildMI(BB, X86::MOV8rr, 1, X86::CL).addReg(Tmp2);
-    BuildMI(BB, Opc, 2, Result).addReg(Tmp1).addReg(Tmp2);
+    BuildMI(BB, Opc, 1, Result).addReg(Tmp1);
     return Result;
   case ISD::SRL:
     if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
@@ -3253,7 +3253,7 @@
     case MVT::i32: Opc = X86::SHR32rCL; break;
     }
     BuildMI(BB, X86::MOV8rr, 1, X86::CL).addReg(Tmp2);
-    BuildMI(BB, Opc, 2, Result).addReg(Tmp1).addReg(Tmp2);
+    BuildMI(BB, Opc, 1, Result).addReg(Tmp1);
     return Result;
   case ISD::SRA:
     if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N.getOperand(1))) {





From lattner at cs.uiuc.edu  Thu Aug 18 19:31:51 2005
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Thu, 18 Aug 2005 19:31:51 -0500
Subject: [llvm-commits] CVS: llvm/lib/Target/X86/X86ISelPattern.cpp 
Message-ID: <200508190031.TAA31874@zion.cs.uiuc.edu>



Changes in directory llvm/lib/Target/X86:

X86ISelPattern.cpp updated: 1.171 -> 1.172
---
Log message:

The variable SAR's only take one operand too


---
Diffs of the changes:  (+1 -1)

 X86ISelPattern.cpp |    2 +-
 1 files changed, 1 insertion(+), 1 deletion(-)


Index: llvm/lib/Target/X86/X86ISelPattern.cpp
diff -u llvm/lib/Target/X86/X86ISelPattern.cpp:1.171 llvm/lib/Target/X86/X86ISelPattern.cpp:1.172
--- llvm/lib/Target/X86/X86ISelPattern.cpp:1.171	Thu Aug 18 19:16:17 2005
+++ llvm/lib/Target/X86/X86ISelPattern.cpp	Thu Aug 18 19:31:37 2005
@@ -3283,7 +3283,7 @@
     case MVT::i32: Opc = X86::SAR32rCL; break;
     }
     BuildMI(BB, X86::MOV8rr, 1, X86::CL).addReg(Tmp2);
-    BuildMI(BB, Opc, 2, Result).addReg(Tmp1).addReg(Tmp2);
+    BuildMI(BB, Opc, 1, Result).addReg(Tmp1);
     return Result;
 
   case ISD::SETCC:





From natebegeman at mac.com  Thu Aug 18 19:38:30 2005
From: natebegeman at mac.com (Nate Begeman)
Date: Thu, 18 Aug 2005 19:38:30 -0500
Subject: [llvm-commits] CVS: llvm/lib/Target/PowerPC/PPC32ISelDAGToDAG.cpp 
Message-ID: <200508190038.TAA31981@zion.cs.uiuc.edu>



Changes in directory llvm/lib/Target/PowerPC:

PPC32ISelDAGToDAG.cpp updated: 1.13 -> 1.14
---
Log message:

ISD::OR, and it's accompanying SelectBitfieldInsert


---
Diffs of the changes:  (+136 -1)

 PPC32ISelDAGToDAG.cpp |  137 +++++++++++++++++++++++++++++++++++++++++++++++++-
 1 files changed, 136 insertions(+), 1 deletion(-)


Index: llvm/lib/Target/PowerPC/PPC32ISelDAGToDAG.cpp
diff -u llvm/lib/Target/PowerPC/PPC32ISelDAGToDAG.cpp:1.13 llvm/lib/Target/PowerPC/PPC32ISelDAGToDAG.cpp:1.14
--- llvm/lib/Target/PowerPC/PPC32ISelDAGToDAG.cpp:1.13	Thu Aug 18 18:38:00 2005
+++ llvm/lib/Target/PowerPC/PPC32ISelDAGToDAG.cpp	Thu Aug 18 19:38:14 2005
@@ -53,7 +53,8 @@
                                    unsigned OCHi, unsigned OCLo,
                                    bool IsArithmetic = false,
                                    bool Negate = false);
-   
+    SDNode *SelectBitfieldInsert(SDNode *N);
+
     /// InstructionSelectBasicBlock - This callback is invoked by
     /// SelectionDAGISel when it has created a SelectionDAG for us to codegen.
     virtual void InstructionSelectBasicBlock(SelectionDAG &DAG) {
@@ -179,6 +180,115 @@
   return false;
 }
 
+/// SelectBitfieldInsert - turn an or of two masked values into
+/// the rotate left word immediate then mask insert (rlwimi) instruction.
+/// Returns true on success, false if the caller still needs to select OR.
+///
+/// Patterns matched:
+/// 1. or shl, and   5. or and, and
+/// 2. or and, shl   6. or shl, shr
+/// 3. or shr, and   7. or shr, shl
+/// 4. or and, shr
+SDNode *PPC32DAGToDAGISel::SelectBitfieldInsert(SDNode *N) {
+  bool IsRotate = false;
+  unsigned TgtMask = 0xFFFFFFFF, InsMask = 0xFFFFFFFF, SH = 0;
+  unsigned Value;
+  
+  SDOperand Op0 = N->getOperand(0);
+  SDOperand Op1 = N->getOperand(1);
+  
+  unsigned Op0Opc = Op0.getOpcode();
+  unsigned Op1Opc = Op1.getOpcode();
+  
+  // Verify that we have the correct opcodes
+  if (ISD::SHL != Op0Opc && ISD::SRL != Op0Opc && ISD::AND != Op0Opc)
+    return false;
+  if (ISD::SHL != Op1Opc && ISD::SRL != Op1Opc && ISD::AND != Op1Opc)
+    return false;
+  
+  // Generate Mask value for Target
+  if (isIntImmediate(Op0.getOperand(1), Value)) {
+    switch(Op0Opc) {
+      case ISD::SHL: TgtMask <<= Value; break;
+      case ISD::SRL: TgtMask >>= Value; break;
+      case ISD::AND: TgtMask &= Value; break;
+    }
+  } else {
+    return 0;
+  }
+  
+  // Generate Mask value for Insert
+  if (isIntImmediate(Op1.getOperand(1), Value)) {
+    switch(Op1Opc) {
+      case ISD::SHL:
+        SH = Value;
+        InsMask <<= SH;
+        if (Op0Opc == ISD::SRL) IsRotate = true;
+          break;
+      case ISD::SRL:
+        SH = Value;
+        InsMask >>= SH;
+        SH = 32-SH;
+        if (Op0Opc == ISD::SHL) IsRotate = true;
+          break;
+      case ISD::AND:
+        InsMask &= Value;
+        break;
+    }
+  } else {
+    return 0;
+  }
+  
+  // If both of the inputs are ANDs and one of them has a logical shift by
+  // constant as its input, make that AND the inserted value so that we can
+  // combine the shift into the rotate part of the rlwimi instruction
+  bool IsAndWithShiftOp = false;
+  if (Op0Opc == ISD::AND && Op1Opc == ISD::AND) {
+    if (Op1.getOperand(0).getOpcode() == ISD::SHL ||
+        Op1.getOperand(0).getOpcode() == ISD::SRL) {
+      if (isIntImmediate(Op1.getOperand(0).getOperand(1), Value)) {
+        SH = Op1.getOperand(0).getOpcode() == ISD::SHL ? Value : 32 - Value;
+        IsAndWithShiftOp = true;
+      }
+    } else if (Op0.getOperand(0).getOpcode() == ISD::SHL ||
+               Op0.getOperand(0).getOpcode() == ISD::SRL) {
+      if (isIntImmediate(Op0.getOperand(0).getOperand(1), Value)) {
+        std::swap(Op0, Op1);
+        std::swap(TgtMask, InsMask);
+        SH = Op1.getOperand(0).getOpcode() == ISD::SHL ? Value : 32 - Value;
+        IsAndWithShiftOp = true;
+      }
+    }
+  }
+  
+  // Verify that the Target mask and Insert mask together form a full word mask
+  // and that the Insert mask is a run of set bits (which implies both are runs
+  // of set bits).  Given that, Select the arguments and generate the rlwimi
+  // instruction.
+  unsigned MB, ME;
+  if (((TgtMask & InsMask) == 0) && isRunOfOnes(InsMask, MB, ME)) {
+    bool fullMask = (TgtMask ^ InsMask) == 0xFFFFFFFF;
+    bool Op0IsAND = Op0Opc == ISD::AND;
+    // Check for rotlwi / rotrwi here, a special case of bitfield insert
+    // where both bitfield halves are sourced from the same value.
+    if (IsRotate && fullMask &&
+        N->getOperand(0).getOperand(0) == N->getOperand(1).getOperand(0)) {
+      Op0 = CurDAG->getTargetNode(PPC::RLWINM, MVT::i32,
+                                  Select(N->getOperand(0).getOperand(0)),
+                                  getI32Imm(SH), getI32Imm(0), getI32Imm(31));
+      return Op0.Val;
+    }
+    SDOperand Tmp1 = (Op0IsAND && fullMask) ? Select(Op0.getOperand(0))
+                                            : Select(Op0);
+    SDOperand Tmp2 = IsAndWithShiftOp ? Select(Op1.getOperand(0).getOperand(0)) 
+                                      : Select(Op1.getOperand(0));
+    Op0 = CurDAG->getTargetNode(PPC::RLWIMI, MVT::i32, Tmp1, Tmp2,
+                                getI32Imm(SH), getI32Imm(MB), getI32Imm(ME));
+    return Op0.Val;
+  }
+  return 0;
+}
+
 // SelectIntImmediateExpr - Choose code for integer operations with an immediate
 // operand.
 SDNode *PPC32DAGToDAGISel::SelectIntImmediateExpr(SDOperand LHS, SDOperand RHS,
@@ -447,6 +557,31 @@
                            Select(N->getOperand(1)));
     break;
   }
+  case ISD::OR:
+    if (SDNode *I = SelectBitfieldInsert(N)) {
+      CurDAG->ReplaceAllUsesWith(N, I);
+      N = I;
+      break;
+    }
+    if (SDNode *I = SelectIntImmediateExpr(N->getOperand(0), 
+                                           N->getOperand(1),
+                                           PPC::ORIS, PPC::ORI)) {
+      CurDAG->ReplaceAllUsesWith(N, I); 
+      N = I;
+      break;
+    }
+    // Finally, check for the case where we are being asked to select
+    // 'or (not(a), b)' or 'or (a, not(b))' which can be selected as orc.
+    if (isOprNot(N->getOperand(0).Val))
+      CurDAG->SelectNodeTo(N, MVT::i32, PPC::ORC, Select(N->getOperand(1)),
+                           Select(N->getOperand(0).getOperand(0)));
+    else if (isOprNot(N->getOperand(1).Val))
+      CurDAG->SelectNodeTo(N, MVT::i32, PPC::ORC, Select(N->getOperand(0)),
+                           Select(N->getOperand(1).getOperand(0)));
+    else
+      CurDAG->SelectNodeTo(N, MVT::i32, PPC::OR, Select(N->getOperand(0)),
+                           Select(N->getOperand(1)));
+    break;
   case ISD::XOR:
     // Check whether or not this node is a logical 'not'.  This is represented
     // by llvm as a xor with the constant value -1 (all bits set).  If this is a





From lattner at cs.uiuc.edu  Thu Aug 18 19:38:34 2005
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Thu, 18 Aug 2005 19:38:34 -0500
Subject: [llvm-commits] CVS: llvm/lib/Target/X86/X86InstrInfo.td 
Message-ID: <200508190038.TAA31989@zion.cs.uiuc.edu>



Changes in directory llvm/lib/Target/X86:

X86InstrInfo.td updated: 1.131 -> 1.132
---
Log message:

Give ADJCALLSTACKDOWN/UP the correct operands.
Give a whole bunch of other stuff variable operands, particularly FP.  The
FP stackifier is playing fast and loose with operands here, so we have to
mark them all as variable.  This will have to be fixed before we can dag->dag
the X86 backend.  The solution is for the pre-stackifier and post-stackifier
instructions to all be disjoint.


---
Diffs of the changes:  (+126 -57)

 X86InstrInfo.td |  183 ++++++++++++++++++++++++++++++++++++++------------------
 1 files changed, 126 insertions(+), 57 deletions(-)


Index: llvm/lib/Target/X86/X86InstrInfo.td
diff -u llvm/lib/Target/X86/X86InstrInfo.td:1.131 llvm/lib/Target/X86/X86InstrInfo.td:1.132
--- llvm/lib/Target/X86/X86InstrInfo.td:1.131	Wed Aug  3 18:26:28 2005
+++ llvm/lib/Target/X86/X86InstrInfo.td	Thu Aug 18 19:38:22 2005
@@ -142,13 +142,13 @@
 // Instruction list...
 //
 
-def PHI : I<0, Pseudo, (ops), "PHINODE">;        // PHI node.
+def PHI : I<0, Pseudo, (ops variable_ops), "PHINODE">;        // PHI node.
 def NOOP : I<0x90, RawFrm, (ops), "nop">; // nop
 
-def ADJCALLSTACKDOWN : I<0, Pseudo, (ops), "#ADJCALLSTACKDOWN">;
-def ADJCALLSTACKUP   : I<0, Pseudo, (ops), "#ADJCALLSTACKUP">;
-def IMPLICIT_USE     : I<0, Pseudo, (ops), "#IMPLICIT_USE">;
-def IMPLICIT_DEF     : I<0, Pseudo, (ops), "#IMPLICIT_DEF">;
+def ADJCALLSTACKDOWN : I<0, Pseudo, (ops i32imm), "#ADJCALLSTACKDOWN">;
+def ADJCALLSTACKUP   : I<0, Pseudo, (ops i32imm, i32imm), "#ADJCALLSTACKUP">;
+def IMPLICIT_USE     : I<0, Pseudo, (ops variable_ops), "#IMPLICIT_USE">;
+def IMPLICIT_DEF     : I<0, Pseudo, (ops variable_ops), "#IMPLICIT_DEF">;
 let isTerminator = 1 in
   let Defs = [FP0, FP1, FP2, FP3, FP4, FP5, FP6] in
     def FP_REG_KILL  : I<0, Pseudo, (ops), "#FP_REG_KILL">;
@@ -1582,18 +1582,22 @@
 // FADD reg, mem: Before stackification, these are represented by:
 // R1 = FADD* R2, [mem]
 def FADD32m  : FPI<0xD8, MRM0m, OneArgFPRW,    // ST(0) = ST(0) + [mem32real]
-                   (ops f32mem:$src), "fadd{s} $src">;
+                   (ops f32mem:$src, variable_ops),
+                   "fadd{s} $src">;
 def FADD64m  : FPI<0xDC, MRM0m, OneArgFPRW,    // ST(0) = ST(0) + [mem64real]
-                   (ops f64mem:$src), "fadd{l} $src">;
+                   (ops f64mem:$src, variable_ops),
+                   "fadd{l} $src">;
 //def FIADD16m : FPI<0xDE, MRM0m, OneArgFPRW>;    // ST(0) = ST(0) + [mem16int]
 //def FIADD32m : FPI<0xDA, MRM0m, OneArgFPRW>;    // ST(0) = ST(0) + [mem32int]
 
 // FMUL reg, mem: Before stackification, these are represented by:
 // R1 = FMUL* R2, [mem]
 def FMUL32m  : FPI<0xD8, MRM1m, OneArgFPRW,    // ST(0) = ST(0) * [mem32real]
-                   (ops f32mem:$src), "fmul{s} $src">;
+                   (ops f32mem:$src, variable_ops),
+                   "fmul{s} $src">;
 def FMUL64m  : FPI<0xDC, MRM1m, OneArgFPRW,    // ST(0) = ST(0) * [mem64real]
-                   (ops f64mem:$src), "fmul{l} $src">;
+                   (ops f64mem:$src, variable_ops),
+                   "fmul{l} $src">;
 // ST(0) = ST(0) * [mem16int]
 //def FIMUL16m : FPI16m<"fimul", 0xDE, MRM1m, OneArgFPRW>;
 // ST(0) = ST(0) * [mem32int]
@@ -1616,9 +1620,11 @@
 // Note that the order of operands does not reflect the operation being
 // performed.
 def FSUBR32m  : FPI<0xD8, MRM5m, OneArgFPRW,  // ST(0) = [mem32real] - ST(0)
-                    (ops f32mem:$src), "fsubr{s} $src">;
+                    (ops f32mem:$src, variable_ops),
+                    "fsubr{s} $src">;
 def FSUBR64m  : FPI<0xDC, MRM5m, OneArgFPRW,  // ST(0) = [mem64real] - ST(0)
-                    (ops f64mem:$src), "fsubr{l} $src">;
+                    (ops f64mem:$src, variable_ops),
+                    "fsubr{l} $src">;
 // ST(0) = [mem16int] - ST(0)
 //def FISUBR16m : FPI16m<"fisubr", 0xDE, MRM5m, OneArgFPRW>;
 // ST(0) = [mem32int] - ST(0)
@@ -1627,9 +1633,11 @@
 // FDIV reg, mem: Before stackification, these are represented by:
 // R1 = FDIV* R2, [mem]
 def FDIV32m  : FPI<0xD8, MRM6m, OneArgFPRW,    // ST(0) = ST(0) / [mem32real]
-                   (ops f32mem:$src), "fdiv{s} $src">;
+                   (ops f32mem:$src, variable_ops),
+                   "fdiv{s} $src">;
 def FDIV64m  : FPI<0xDC, MRM6m, OneArgFPRW,    // ST(0) = ST(0) / [mem64real]
-                   (ops f64mem:$src), "fdiv{l} $src">;
+                   (ops f64mem:$src, variable_ops),
+                   "fdiv{l} $src">;
 // ST(0) = ST(0) / [mem16int]
 //def FIDIV16m : FPI16m<"fidiv", 0xDE, MRM6m, OneArgFPRW>;
 // ST(0) = ST(0) / [mem32int]
@@ -1652,61 +1660,122 @@
 // Floating point cmovs...
 let isTwoAddress = 1, Uses = [ST0], Defs = [ST0] in {
   def FCMOVB  : FPI<0xC0, AddRegFrm, CondMovFP,
-                    (ops RST:$op), "fcmovb {$op, %ST(0)|%ST(0), $op}">, DA;
+                    (ops RST:$op, variable_ops),
+                    "fcmovb {$op, %ST(0)|%ST(0), $op}">, DA;
   def FCMOVBE : FPI<0xD0, AddRegFrm, CondMovFP,
-                    (ops RST:$op), "fcmovbe {$op, %ST(0)|%ST(0), $op}">, DA;
+                    (ops RST:$op, variable_ops),
+                    "fcmovbe {$op, %ST(0)|%ST(0), $op}">, DA;
   def FCMOVE  : FPI<0xC8, AddRegFrm, CondMovFP,
-                    (ops RST:$op), "fcmove {$op, %ST(0)|%ST(0), $op}">, DA;
+                    (ops RST:$op, variable_ops),
+                    "fcmove {$op, %ST(0)|%ST(0), $op}">, DA;
   def FCMOVP  : FPI<0xD8, AddRegFrm, CondMovFP,
-                    (ops RST:$op), "fcmovu  {$op, %ST(0)|%ST(0), $op}">, DA;
+                    (ops RST:$op, variable_ops),
+                    "fcmovu  {$op, %ST(0)|%ST(0), $op}">, DA;
   def FCMOVAE : FPI<0xC0, AddRegFrm, CondMovFP,
-                    (ops RST:$op), "fcmovae {$op, %ST(0)|%ST(0), $op}">, DB;
+                    (ops RST:$op, variable_ops),
+                    "fcmovae {$op, %ST(0)|%ST(0), $op}">, DB;
   def FCMOVA  : FPI<0xD0, AddRegFrm, CondMovFP,
-                    (ops RST:$op), "fcmova {$op, %ST(0)|%ST(0), $op}">, DB;
+                    (ops RST:$op, variable_ops),
+                    "fcmova {$op, %ST(0)|%ST(0), $op}">, DB;
   def FCMOVNE : FPI<0xC8, AddRegFrm, CondMovFP,
-                    (ops RST:$op), "fcmovne {$op, %ST(0)|%ST(0), $op}">, DB;
+                    (ops RST:$op, variable_ops),
+                    "fcmovne {$op, %ST(0)|%ST(0), $op}">, DB;
   def FCMOVNP : FPI<0xD8, AddRegFrm, CondMovFP,
-                    (ops RST:$op), "fcmovnu {$op, %ST(0)|%ST(0), $op}">, DB;
+                    (ops RST:$op, variable_ops),
+                    "fcmovnu {$op, %ST(0)|%ST(0), $op}">, DB;
 }
 
 // Floating point loads & stores...
-def FLDrr   : FPI<0xC0, AddRegFrm, NotFP, (ops    RST:$src), "fld $src">, D9;
-def FLD32m  : FPI<0xD9, MRM0m, ZeroArgFP, (ops f32mem:$src), "fld{s} $src">;
-def FLD64m  : FPI<0xDD, MRM0m, ZeroArgFP, (ops f64mem:$src), "fld{l} $src">;
-def FLD80m  : FPI<0xDB, MRM5m, ZeroArgFP, (ops f80mem:$src), "fld{t} $src">;
-def FILD16m : FPI<0xDF, MRM0m, ZeroArgFP, (ops i16mem:$src), "fild{s} $src">;
-def FILD32m : FPI<0xDB, MRM0m, ZeroArgFP, (ops i32mem:$src), "fild{l} $src">;
-def FILD64m : FPI<0xDF, MRM5m, ZeroArgFP, (ops i64mem:$src), "fild{ll} $src">;
-
-def FSTrr    : FPI<0xD0, AddRegFrm, NotFP, (ops RST:$op), "fst $op">, DD;
-def FSTPrr   : FPI<0xD8, AddRegFrm, NotFP, (ops RST:$op), "fstp $op">, DD;
-def FST32m   : FPI<0xD9, MRM2m, OneArgFP, (ops f32mem:$op), "fst{s} $op">;
-def FST64m   : FPI<0xDD, MRM2m, OneArgFP, (ops f64mem:$op), "fst{l} $op">;
-def FSTP32m  : FPI<0xD9, MRM3m, OneArgFP, (ops f32mem:$op), "fstp{s} $op">;
-def FSTP64m  : FPI<0xDD, MRM3m, OneArgFP, (ops f64mem:$op), "fstp{l} $op">;
-def FSTP80m  : FPI<0xDB, MRM7m, OneArgFP, (ops f80mem:$op), "fstp{t} $op">;
-
-def FIST16m  : FPI<0xDF, MRM2m , OneArgFP, (ops i16mem:$op), "fist{s} $op">;
-def FIST32m  : FPI<0xDB, MRM2m , OneArgFP, (ops i32mem:$op), "fist{l} $op">;
-def FISTP16m : FPI<0xDF, MRM3m , NotFP   , (ops i16mem:$op), "fistp{s} $op">;
-def FISTP32m : FPI<0xDB, MRM3m , NotFP   , (ops i32mem:$op), "fistp{l} $op">;
-def FISTP64m : FPI<0xDF, MRM7m , OneArgFP, (ops i64mem:$op), "fistp{ll} $op">;
+// FIXME: these are all marked variable_ops because they have an implicit 
+// destination.  Instructions like FILD* that are generated by the instruction
+//  selector (not the fp stackifier) need more accurate operand accounting.
+def FLDrr   : FPI<0xC0, AddRegFrm, NotFP,
+                  (ops RST:$src, variable_ops),
+                  "fld $src">, D9;
+def FLD32m  : FPI<0xD9, MRM0m, ZeroArgFP,
+                  (ops f32mem:$src, variable_ops),
+                  "fld{s} $src">;
+def FLD64m  : FPI<0xDD, MRM0m, ZeroArgFP,
+                  (ops f64mem:$src, variable_ops),
+                  "fld{l} $src">;
+def FLD80m  : FPI<0xDB, MRM5m, ZeroArgFP,
+                  (ops f80mem:$src, variable_ops),
+                  "fld{t} $src">;
+def FILD16m : FPI<0xDF, MRM0m, ZeroArgFP,
+                  (ops i16mem:$src, variable_ops),
+                  "fild{s} $src">;
+def FILD32m : FPI<0xDB, MRM0m, ZeroArgFP,
+                  (ops i32mem:$src, variable_ops),
+                  "fild{l} $src">;
+def FILD64m : FPI<0xDF, MRM5m, ZeroArgFP,
+                  (ops i64mem:$src, variable_ops),
+                  "fild{ll} $src">;
+
+def FSTrr    : FPI<0xD0, AddRegFrm, NotFP,
+                   (ops RST:$op, variable_ops),
+                   "fst $op">, DD;
+def FSTPrr   : FPI<0xD8, AddRegFrm, NotFP,
+                   (ops RST:$op, variable_ops),
+                   "fstp $op">, DD;
+def FST32m   : FPI<0xD9, MRM2m, OneArgFP,
+                   (ops f32mem:$op, variable_ops),
+                   "fst{s} $op">;
+def FST64m   : FPI<0xDD, MRM2m, OneArgFP,
+                   (ops f64mem:$op, variable_ops),
+                   "fst{l} $op">;
+def FSTP32m  : FPI<0xD9, MRM3m, OneArgFP,
+                   (ops f32mem:$op, variable_ops),
+                   "fstp{s} $op">;
+def FSTP64m  : FPI<0xDD, MRM3m, OneArgFP,
+                   (ops f64mem:$op, variable_ops),
+                   "fstp{l} $op">;
+def FSTP80m  : FPI<0xDB, MRM7m, OneArgFP,
+                   (ops f80mem:$op, variable_ops),
+                   "fstp{t} $op">;
+
+def FIST16m  : FPI<0xDF, MRM2m , OneArgFP,
+                   (ops i16mem:$op, variable_ops),
+                   "fist{s} $op">;
+def FIST32m  : FPI<0xDB, MRM2m , OneArgFP,
+                   (ops i32mem:$op, variable_ops),
+                   "fist{l} $op">;
+def FISTP16m : FPI<0xDF, MRM3m , NotFP   ,
+                   (ops i16mem:$op, variable_ops),
+                   "fistp{s} $op">;
+def FISTP32m : FPI<0xDB, MRM3m , NotFP   ,
+                   (ops i32mem:$op, variable_ops),
+                   "fistp{l} $op">;
+def FISTP64m : FPI<0xDF, MRM7m , OneArgFP,
+                   (ops i64mem:$op, variable_ops),
+                   "fistp{ll} $op">;
 
 def FXCH     : FPI<0xC8, AddRegFrm, NotFP,
                    (ops RST:$op), "fxch $op">, D9;      // fxch ST(i), ST(0)
 
 // Floating point constant loads...
-def FLD0 : FPI<0xEE, RawFrm, ZeroArgFP, (ops), "fldz">, D9;
-def FLD1 : FPI<0xE8, RawFrm, ZeroArgFP, (ops), "fld1">, D9;
+def FLD0 : FPI<0xEE, RawFrm, ZeroArgFP, (ops variable_ops), "fldz">, D9;
+def FLD1 : FPI<0xE8, RawFrm, ZeroArgFP, (ops variable_ops), "fld1">, D9;
 
 
 // Unary operations...
-def FCHS  : FPI<0xE0, RawFrm, OneArgFPRW, (ops), "fchs" >, D9; // f1 = fchs f2
-def FABS  : FPI<0xE1, RawFrm, OneArgFPRW, (ops), "fabs" >, D9; // f1 = fabs f2
-def FSQRT : FPI<0xFA, RawFrm, OneArgFPRW, (ops), "fsqrt">, D9; // fsqrt ST(0)
-def FSIN  : FPI<0xFE, RawFrm, OneArgFPRW, (ops), "fsin" >, D9; // fsin  ST(0)
-def FCOS  : FPI<0xFF, RawFrm, OneArgFPRW, (ops), "fcos" >, D9; // fcos  ST(0)
-def FTST  : FPI<0xE4, RawFrm, OneArgFP  , (ops), "ftst" >, D9; // ftst ST(0)
+def FCHS  : FPI<0xE0, RawFrm, OneArgFPRW,   // f1 = fchs f2
+                (ops variable_ops),
+                "fchs">, D9;
+def FABS  : FPI<0xE1, RawFrm, OneArgFPRW,   // f1 = fabs f2
+                (ops variable_ops),
+                "fabs">, D9;
+def FSQRT : FPI<0xFA, RawFrm, OneArgFPRW,   // fsqrt ST(0)
+                (ops variable_ops),
+                "fsqrt">, D9;
+def FSIN  : FPI<0xFE, RawFrm, OneArgFPRW,   // fsin  ST(0)
+                (ops variable_ops),
+                "fsin">, D9;
+def FCOS  : FPI<0xFF, RawFrm, OneArgFPRW,   // fcos  ST(0)
+                (ops variable_ops),
+                "fcos">, D9;
+def FTST  : FPI<0xE4, RawFrm, OneArgFP  ,   // ftst ST(0)
+                (ops variable_ops),
+                "ftst">, D9;
 
 // Binary arithmetic operations...
 class FPST0rInst<bits<8> o, dag ops, string asm>
@@ -1770,20 +1839,20 @@
 
 // Floating point compares
 def FUCOMr    : FPI<0xE0, AddRegFrm, CompareFP,   // FPSW = cmp ST(0) with ST(i)
-                    (ops RST:$reg),
+                    (ops RST:$reg, variable_ops),
                     "fucom $reg">, DD, Imp<[ST0],[]>;
-def FUCOMPr   : I<0xE8, AddRegFrm,
-                  (ops RST:$reg),           // FPSW = cmp ST(0) with ST(i), pop
+def FUCOMPr   : I<0xE8, AddRegFrm,           // FPSW = cmp ST(0) with ST(i), pop
+                  (ops RST:$reg, variable_ops),
                   "fucomp $reg">, DD, Imp<[ST0],[]>;
-def FUCOMPPr  : I<0xE9, RawFrm,
-                  (ops),                    // cmp ST(0) with ST(1), pop, pop
+def FUCOMPPr  : I<0xE9, RawFrm,                // cmp ST(0) with ST(1), pop, pop
+                  (ops variable_ops),
                   "fucompp">, DA, Imp<[ST0],[]>;
 
 def FUCOMIr  : FPI<0xE8, AddRegFrm, CompareFP,  // CC = cmp ST(0) with ST(i)
-                   (ops RST:$reg),
+                   (ops RST:$reg, variable_ops),
                    "fucomi {$reg, %ST(0)|%ST(0), $reg}">, DB, Imp<[ST0],[]>;
 def FUCOMIPr : I<0xE8, AddRegFrm,              // CC = cmp ST(0) with ST(i), pop
-                 (ops RST:$reg),
+                 (ops RST:$reg, variable_ops),
                  "fucomip {$reg, %ST(0)|%ST(0), $reg}">, DF, Imp<[ST0],[]>;
 
 





From lattner at cs.uiuc.edu  Thu Aug 18 19:41:40 2005
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Thu, 18 Aug 2005 19:41:40 -0500
Subject: [llvm-commits] CVS: llvm/lib/Target/X86/X86InstrInfo.td 
Message-ID: <200508190041.TAA32036@zion.cs.uiuc.edu>



Changes in directory llvm/lib/Target/X86:

X86InstrInfo.td updated: 1.132 -> 1.133
---
Log message:

add a few missing cases


---
Diffs of the changes:  (+8 -4)

 X86InstrInfo.td |   12 ++++++++----
 1 files changed, 8 insertions(+), 4 deletions(-)


Index: llvm/lib/Target/X86/X86InstrInfo.td
diff -u llvm/lib/Target/X86/X86InstrInfo.td:1.132 llvm/lib/Target/X86/X86InstrInfo.td:1.133
--- llvm/lib/Target/X86/X86InstrInfo.td:1.132	Thu Aug 18 19:38:22 2005
+++ llvm/lib/Target/X86/X86InstrInfo.td	Thu Aug 18 19:41:29 2005
@@ -1606,9 +1606,11 @@
 // FSUB reg, mem: Before stackification, these are represented by:
 // R1 = FSUB* R2, [mem]
 def FSUB32m  : FPI<0xD8, MRM4m, OneArgFPRW,    // ST(0) = ST(0) - [mem32real]
-                   (ops f32mem:$src), "fsub{s} $src">;
+                   (ops f32mem:$src, variable_ops),
+                   "fsub{s} $src">;
 def FSUB64m  : FPI<0xDC, MRM4m, OneArgFPRW,    // ST(0) = ST(0) - [mem64real]
-                   (ops f64mem:$src), "fsub{l} $src">;
+                   (ops f64mem:$src, variable_ops),
+                   "fsub{l} $src">;
 // ST(0) = ST(0) - [mem16int]
 //def FISUB16m : FPI16m<"fisub", 0xDE, MRM4m, OneArgFPRW>;
 // ST(0) = ST(0) - [mem32int]
@@ -1648,9 +1650,11 @@
 // Note that the order of operands does not reflect the operation being
 // performed.
 def FDIVR32m  : FPI<0xD8, MRM7m, OneArgFPRW,  // ST(0) = [mem32real] / ST(0)
-                    (ops f32mem:$src), "fdivr{s} $src">;
+                    (ops f32mem:$src, variable_ops),
+                    "fdivr{s} $src">;
 def FDIVR64m  : FPI<0xDC, MRM7m, OneArgFPRW,  // ST(0) = [mem64real] / ST(0)
-                    (ops f64mem:$src), "fdivr{l} $src">;
+                    (ops f64mem:$src, variable_ops),
+                    "fdivr{l} $src">;
 // ST(0) = [mem16int] / ST(0)
 //def FIDIVR16m : FPI16m<"fidivr", 0xDE, MRM7m, OneArgFPRW>;
 // ST(0) = [mem32int] / ST(0)





From lattner at cs.uiuc.edu  Thu Aug 18 19:47:54 2005
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Thu, 18 Aug 2005 19:47:54 -0500
Subject: [llvm-commits] CVS: llvm/lib/Target/IA64/IA64InstrInfo.td 
Message-ID: <200508190047.TAA32125@zion.cs.uiuc.edu>



Changes in directory llvm/lib/Target/IA64:

IA64InstrInfo.td updated: 1.13 -> 1.14
---
Log message:

Mark some instructions as variable_ops, and PSEUDO_ALLOC as taking a GPR.
I'm not convinced this is all of them,  but I can't do much testing, because
IA64 LLC crashes on big programs :(


---
Diffs of the changes:  (+8 -7)

 IA64InstrInfo.td |   15 ++++++++-------
 1 files changed, 8 insertions(+), 7 deletions(-)


Index: llvm/lib/Target/IA64/IA64InstrInfo.td
diff -u llvm/lib/Target/IA64/IA64InstrInfo.td:1.13 llvm/lib/Target/IA64/IA64InstrInfo.td:1.14
--- llvm/lib/Target/IA64/IA64InstrInfo.td:1.13	Wed May 11 00:16:09 2005
+++ llvm/lib/Target/IA64/IA64InstrInfo.td	Thu Aug 18 19:47:42 2005
@@ -36,13 +36,14 @@
 let PrintMethod = "printCallOperand" in
   def calltarget : Operand<i64>;
   
-def PHI : PseudoInstIA64<(ops), "PHI">;
-def IDEF : PseudoInstIA64<(ops), "// IDEF">;
-def IUSE : PseudoInstIA64<(ops), "// IUSE">;
-def WTF : PseudoInstIA64<(ops), "que??">;
-def ADJUSTCALLSTACKUP : PseudoInstIA64<(ops), "// ADJUSTCALLSTACKUP">;
-def ADJUSTCALLSTACKDOWN : PseudoInstIA64<(ops), "// ADJUSTCALLSTACKDOWN">;
-def PSEUDO_ALLOC : PseudoInstIA64<(ops), "// PSEUDO_ALLOC">;
+def PHI : PseudoInstIA64<(ops variable_ops), "PHI">;
+def IDEF : PseudoInstIA64<(ops variable_ops), "// IDEF">;
+def IUSE : PseudoInstIA64<(ops variable_ops), "// IUSE">;
+def ADJUSTCALLSTACKUP : PseudoInstIA64<(ops variable_ops),
+                                        "// ADJUSTCALLSTACKUP">;
+def ADJUSTCALLSTACKDOWN : PseudoInstIA64<(ops variable_ops),
+                                         "// ADJUSTCALLSTACKDOWN">;
+def PSEUDO_ALLOC : PseudoInstIA64<(ops GR), "// PSEUDO_ALLOC">;
 
 def ALLOC : AForm<0x03, 0x0b,
   (ops GR:$dst, i8imm:$inputs, i8imm:$locals, i8imm:$outputs, i8imm:$rotating),





From lattner at cs.uiuc.edu  Thu Aug 18 19:51:49 2005
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Thu, 18 Aug 2005 19:51:49 -0500
Subject: [llvm-commits] CVS: llvm/lib/Target/Alpha/AlphaInstrInfo.td 
Message-ID: <200508190051.TAA32213@zion.cs.uiuc.edu>



Changes in directory llvm/lib/Target/Alpha:

AlphaInstrInfo.td updated: 1.57 -> 1.58
---
Log message:

mark variable arity instructions as such.  Alpha wins the battle for 
cleanest backend in this metric :)


---
Diffs of the changes:  (+4 -4)

 AlphaInstrInfo.td |    8 ++++----
 1 files changed, 4 insertions(+), 4 deletions(-)


Index: llvm/lib/Target/Alpha/AlphaInstrInfo.td
diff -u llvm/lib/Target/Alpha/AlphaInstrInfo.td:1.57 llvm/lib/Target/Alpha/AlphaInstrInfo.td:1.58
--- llvm/lib/Target/Alpha/AlphaInstrInfo.td:1.57	Fri Aug 12 11:14:08 2005
+++ llvm/lib/Target/Alpha/AlphaInstrInfo.td	Thu Aug 18 19:51:37 2005
@@ -18,11 +18,11 @@
   // //#define GP    $29
   // //#define SP    $30
 
-def PHI : PseudoInstAlpha<(ops ), "#phi">;
+def PHI : PseudoInstAlpha<(ops variable_ops), "#phi">;
 def IDEF : PseudoInstAlpha<(ops GPRC:$RA), "#idef $RA">;
-def WTF : PseudoInstAlpha<(ops ), "#wtf">;
-def ADJUSTSTACKUP : PseudoInstAlpha<(ops ), "ADJUP">;
-def ADJUSTSTACKDOWN : PseudoInstAlpha<(ops ), "ADJDOWN">;
+def WTF : PseudoInstAlpha<(ops variable_ops), "#wtf">;
+def ADJUSTSTACKUP : PseudoInstAlpha<(ops variable_ops), "ADJUP">;
+def ADJUSTSTACKDOWN : PseudoInstAlpha<(ops variable_ops), "ADJDOWN">;
 def ALTENT : PseudoInstAlpha<(ops s64imm:$TARGET), "$TARGET:\n">;
 def PCLABEL : PseudoInstAlpha<(ops s64imm:$num), "PCMARKER_$num:\n">;
 def MEMLABEL : PseudoInstAlpha<(ops s64imm:$i, s64imm:$j, s64imm:$k, s64imm:$m),





From natebegeman at mac.com  Thu Aug 18 19:56:39 2005
From: natebegeman at mac.com (Nate Begeman)
Date: Thu, 18 Aug 2005 19:56:39 -0500
Subject: [llvm-commits] CVS: llvm/include/llvm/CodeGen/SelectionDAG.h 
Message-ID: <200508190056.TAA32401@zion.cs.uiuc.edu>



Changes in directory llvm/include/llvm/CodeGen:

SelectionDAG.h updated: 1.42 -> 1.43
---
Log message:

Add support for target nodes with more than 3 operands, required by ppc


---
Diffs of the changes:  (+10 -0)

 SelectionDAG.h |   10 ++++++++++
 1 files changed, 10 insertions(+)


Index: llvm/include/llvm/CodeGen/SelectionDAG.h
diff -u llvm/include/llvm/CodeGen/SelectionDAG.h:1.42 llvm/include/llvm/CodeGen/SelectionDAG.h:1.43
--- llvm/include/llvm/CodeGen/SelectionDAG.h:1.42	Thu Aug 18 02:25:46 2005
+++ llvm/include/llvm/CodeGen/SelectionDAG.h	Thu Aug 18 19:56:28 2005
@@ -241,6 +241,16 @@
                           SDOperand Op1, SDOperand Op2, SDOperand Op3) {
     return getNode(ISD::BUILTIN_OP_END+Opcode, VT, Op1, Op2, Op3);
   }
+  SDOperand getTargetNode(unsigned Opcode, MVT::ValueType VT,
+                          SDOperand Op1, SDOperand Op2, SDOperand Op3,
+                          SDOperand Op4) {
+    return getNode(ISD::BUILTIN_OP_END+Opcode, VT, Op1, Op2, Op3, Op4);
+  }
+  SDOperand getTargetNode(unsigned Opcode, MVT::ValueType VT,
+                          SDOperand Op1, SDOperand Op2, SDOperand Op3,
+                          SDOperand Op4, SDOperand Op5) {
+    return getNode(ISD::BUILTIN_OP_END+Opcode, VT, Op1, Op2, Op3, Op4, Op5);
+  }
   
   /// ReplaceAllUsesWith - Modify anything using 'From' to use 'To' instead.
   /// This can cause recursive merging of nodes in the DAG.





From lattner at cs.uiuc.edu  Thu Aug 18 20:00:01 2005
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Thu, 18 Aug 2005 20:00:01 -0500
Subject: [llvm-commits] CVS: llvm/utils/TableGen/InstrInfoEmitter.cpp 
Message-ID: <200508190100.UAA32511@zion.cs.uiuc.edu>



Changes in directory llvm/utils/TableGen:

InstrInfoEmitter.cpp updated: 1.21 -> 1.22
---
Log message:

now that all of the targets are clean w.r.t. the number of operands for each
instruction defined, actually emit this to the InstrInfoDescriptor, which
allows an assert in the machineinstrbuilder to do some checking for us,
and is required by the dag->dag emitter


---
Diffs of the changes:  (+11 -3)

 InstrInfoEmitter.cpp |   14 +++++++++++---
 1 files changed, 11 insertions(+), 3 deletions(-)


Index: llvm/utils/TableGen/InstrInfoEmitter.cpp
diff -u llvm/utils/TableGen/InstrInfoEmitter.cpp:1.21 llvm/utils/TableGen/InstrInfoEmitter.cpp:1.22
--- llvm/utils/TableGen/InstrInfoEmitter.cpp:1.21	Thu Aug 18 17:12:31 2005
+++ llvm/utils/TableGen/InstrInfoEmitter.cpp	Thu Aug 18 19:59:49 2005
@@ -120,14 +120,22 @@
                                   Record *InstrInfo,
                                   std::map<ListInit*, unsigned> &ListNumbers,
                                   std::ostream &OS) {
+  int NumOperands;
+  if (Inst.hasVariableNumberOfOperands)
+    NumOperands = -1;
+  else if (!Inst.OperandList.empty())
+    // Each logical operand can be multiple MI operands.
+    NumOperands = Inst.OperandList.back().MIOperandNo +
+                  Inst.OperandList.back().MINumOperands;
+  else
+    NumOperands = 0;
+  
   OS << "  { \"";
   if (Inst.Name.empty())
     OS << Inst.TheDef->getName();
   else
     OS << Inst.Name;
-  OS << "\",\t" << -1
-     //Inst.OperandList.size()
-     << ", -1, 0, false, 0, 0, 0, 0";
+  OS << "\",\t" << NumOperands << ", -1, 0, false, 0, 0, 0, 0";
 
   // Emit all of the target indepedent flags...
   if (Inst.isReturn)     OS << "|M_RET_FLAG";





From lattner at cs.uiuc.edu  Thu Aug 18 20:01:45 2005
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Thu, 18 Aug 2005 20:01:45 -0500
Subject: [llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp 
Message-ID: <200508190101.UAA32560@zion.cs.uiuc.edu>



Changes in directory llvm/lib/CodeGen/SelectionDAG:

ScheduleDAG.cpp updated: 1.3 -> 1.4
---
Log message:

Fix computation of # operands, add a temporary hack for CopyToReg


---
Diffs of the changes:  (+17 -6)

 ScheduleDAG.cpp |   23 +++++++++++++++++------
 1 files changed, 17 insertions(+), 6 deletions(-)


Index: llvm/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp:1.3 llvm/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp:1.4
--- llvm/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp:1.3	Thu Aug 18 15:11:49 2005
+++ llvm/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp	Thu Aug 18 20:01:34 2005
@@ -73,11 +73,16 @@
     // Target nodes have any register or immediate operands before any chain
     // nodes.  Check that the DAG matches the TD files's expectation of #
     // operands.
-    assert((unsigned(II.numOperands) == Op.getNumOperands() ||
-            // It could be some number of operands followed by a token chain.
-           (unsigned(II.numOperands)+1 == Op.getNumOperands() &&
-            Op.getOperand(II.numOperands).getValueType() == MVT::Other)) &&
+#ifndef _NDEBUG
+    unsigned Operands = Op.getNumOperands();
+    if (Operands && Op.getOperand(Operands-1).getValueType() == MVT::Other)
+      --Operands;
+    unsigned Results = Op.Val->getNumValues();
+    if (Results && Op.getOperand(Results-1).getValueType() == MVT::Other)
+      --Results;
+    assert(unsigned(II.numOperands) == Operands+Results &&
            "#operands for dag node doesn't match .td file!"); 
+#endif
 
     // Create the new machine instruction.
     MachineInstr *MI = new MachineInstr(Opc, II.numOperands, true, true);
@@ -107,9 +112,15 @@
     BB->insert(BB->end(), MI);
   } else {
     switch (Op.getOpcode()) {
-    default: assert(0 &&
-                    "This target-independent node should have been selected!");
+    default:
+      Op.Val->dump(); 
+      assert(0 && "This target-independent node should have been selected!");
     case ISD::EntryToken: break;
+    case ISD::CopyToReg: {
+      unsigned Val = Emit(Op.getOperand(2));
+      // FIXME: DO THE COPY NOW.
+      break;
+    }
     }
   }
   





From lattner at cs.uiuc.edu  Thu Aug 18 20:04:45 2005
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Thu, 18 Aug 2005 20:04:45 -0500
Subject: [llvm-commits] CVS: llvm/utils/TableGen/CodeEmitterGen.cpp 
Message-ID: <200508190104.UAA32614@zion.cs.uiuc.edu>



Changes in directory llvm/utils/TableGen:

CodeEmitterGen.cpp updated: 1.40 -> 1.41
---
Log message:

The code emitter generator only supports targets with 32-bit instruction
words.  There is no way for one of these targets to have a > 32-bit immediate!


---
Diffs of the changes:  (+1 -1)

 CodeEmitterGen.cpp |    2 +-
 1 files changed, 1 insertion(+), 1 deletion(-)


Index: llvm/utils/TableGen/CodeEmitterGen.cpp
diff -u llvm/utils/TableGen/CodeEmitterGen.cpp:1.40 llvm/utils/TableGen/CodeEmitterGen.cpp:1.41
--- llvm/utils/TableGen/CodeEmitterGen.cpp:1.40	Thu Apr 21 19:00:35 2005
+++ llvm/utils/TableGen/CodeEmitterGen.cpp	Thu Aug 18 20:04:33 2005
@@ -197,7 +197,7 @@
         // this is not an operand!!
         if (beginBitInInst != -1) {
           o << "      // op" << op << ": " << Vals[i].getName() << "\n"
-            << "      int64_t op" << op
+            << "      int op" << op
             <<" = getMachineOpValue(MI, MI.getOperand("<<op<<"));\n";
           //<< "   MachineOperand &op" << op <<" = MI.getOperand("<<op<<");\n";
           OpOrder[Vals[i].getName()] = op++;





From lattner at cs.uiuc.edu  Thu Aug 18 20:14:51 2005
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Thu, 18 Aug 2005 20:14:51 -0500
Subject: [llvm-commits] 
	CVS: llvm/test/Regression/CodeGen/X86/2005-01-17-CycleInDAG.ll
	fabs.ll regpressure.ll rotate.ll shift-double.llx 
Message-ID: <200508190114.UAA32724@zion.cs.uiuc.edu>



Changes in directory llvm/test/Regression/CodeGen/X86:

2005-01-17-CycleInDAG.ll updated: 1.1 -> 1.2
fabs.ll updated: 1.4 -> 1.5
regpressure.ll updated: 1.2 -> 1.3
rotate.ll updated: 1.2 -> 1.3
shift-double.llx updated: 1.5 -> 1.6
---
Log message:

remove dead flags


---
Diffs of the changes:  (+5 -5)

 2005-01-17-CycleInDAG.ll |    2 +-
 fabs.ll                  |    2 +-
 regpressure.ll           |    2 +-
 rotate.ll                |    2 +-
 shift-double.llx         |    2 +-
 5 files changed, 5 insertions(+), 5 deletions(-)


Index: llvm/test/Regression/CodeGen/X86/2005-01-17-CycleInDAG.ll
diff -u llvm/test/Regression/CodeGen/X86/2005-01-17-CycleInDAG.ll:1.1 llvm/test/Regression/CodeGen/X86/2005-01-17-CycleInDAG.ll:1.2
--- llvm/test/Regression/CodeGen/X86/2005-01-17-CycleInDAG.ll:1.1	Mon Jan 17 00:25:59 2005
+++ llvm/test/Regression/CodeGen/X86/2005-01-17-CycleInDAG.ll	Thu Aug 18 20:14:40 2005
@@ -3,7 +3,7 @@
 ; is invalid code (there is no correct way to order the instruction).  Check
 ; that we do not fold the load into the sub.
 
-; RUN: llvm-as < %s | llc -march=x86 -disable-pattern-isel=0 | not grep 'sub.*GLOBAL'
+; RUN: llvm-as < %s | llc -march=x86 | not grep 'sub.*GLOBAL'
 
 %GLOBAL = external global int
 


Index: llvm/test/Regression/CodeGen/X86/fabs.ll
diff -u llvm/test/Regression/CodeGen/X86/fabs.ll:1.4 llvm/test/Regression/CodeGen/X86/fabs.ll:1.5
--- llvm/test/Regression/CodeGen/X86/fabs.ll:1.4	Fri Apr 15 23:25:48 2005
+++ llvm/test/Regression/CodeGen/X86/fabs.ll	Thu Aug 18 20:14:40 2005
@@ -1,5 +1,5 @@
 ; Make sure this testcase codegens to the fabs instruction, not a call to fabsf
-; RUN: llvm-as < %s | llc -march=x86 -enable-pattern-isel=1 | grep 'fabs$' | wc -l | grep 2
+; RUN: llvm-as < %s | llc -march=x86 | grep 'fabs$' | wc -l | grep 2
 
 declare float %fabsf(float)
 


Index: llvm/test/Regression/CodeGen/X86/regpressure.ll
diff -u llvm/test/Regression/CodeGen/X86/regpressure.ll:1.2 llvm/test/Regression/CodeGen/X86/regpressure.ll:1.3
--- llvm/test/Regression/CodeGen/X86/regpressure.ll:1.2	Mon Jan 17 17:16:01 2005
+++ llvm/test/Regression/CodeGen/X86/regpressure.ll	Thu Aug 18 20:14:40 2005
@@ -1,7 +1,7 @@
 ;; Both functions in this testcase should codegen to the same function, and
 ;; neither of them should require spilling anything to the stack.
 
-; RUN: llvm-as < %s | llc -march=x86 -disable-pattern-isel=0 -stats  2>&1 | not grep 'Number of register spills'
+; RUN: llvm-as < %s | llc -march=x86 -stats  2>&1 | not grep 'Number of register spills'
 
 ;; This can be compiled to use three registers if the loads are not
 ;; folded into the multiplies, 2 registers otherwise.


Index: llvm/test/Regression/CodeGen/X86/rotate.ll
diff -u llvm/test/Regression/CodeGen/X86/rotate.ll:1.2 llvm/test/Regression/CodeGen/X86/rotate.ll:1.3
--- llvm/test/Regression/CodeGen/X86/rotate.ll:1.2	Fri Apr 15 23:25:48 2005
+++ llvm/test/Regression/CodeGen/X86/rotate.ll	Thu Aug 18 20:14:40 2005
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86 -x86-asm-syntax=intel -enable-pattern-isel=1 | grep ro[rl] | wc -l | grep 12
+; RUN: llvm-as < %s | llc -march=x86 -x86-asm-syntax=intel | grep ro[rl] | wc -l | grep 12
 
 uint %rotl32(uint %A, ubyte %Amt) {
 	%B = shl uint %A, ubyte %Amt


Index: llvm/test/Regression/CodeGen/X86/shift-double.llx
diff -u llvm/test/Regression/CodeGen/X86/shift-double.llx:1.5 llvm/test/Regression/CodeGen/X86/shift-double.llx:1.6
--- llvm/test/Regression/CodeGen/X86/shift-double.llx:1.5	Fri Apr 15 23:25:48 2005
+++ llvm/test/Regression/CodeGen/X86/shift-double.llx	Thu Aug 18 20:14:40 2005
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86 -x86-asm-syntax=intel -enable-pattern-isel=1 | grep sh[lr]d | wc -l | grep 5
+; RUN: llvm-as < %s | llc -march=x86 -x86-asm-syntax=intel grep sh[lr]d | wc -l | grep 5
 
 long %test1(long %X, ubyte %C) {
 	%Y = shl long %X, ubyte %C





From lattner at cs.uiuc.edu  Thu Aug 18 20:16:29 2005
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Thu, 18 Aug 2005 20:16:29 -0500
Subject: [llvm-commits] CVS: llvm/test/Regression/CodeGen/PowerPC/fnegsel.ll
	select_lt0.ll setcc_no_zext.ll 
Message-ID: <200508190116.UAA00313@zion.cs.uiuc.edu>



Changes in directory llvm/test/Regression/CodeGen/PowerPC:

fnegsel.ll updated: 1.2 -> 1.3
select_lt0.ll updated: 1.1 -> 1.2
setcc_no_zext.ll updated: 1.1 -> 1.2
---
Log message:

remove dead options


---
Diffs of the changes:  (+3 -3)

 fnegsel.ll       |    2 +-
 select_lt0.ll    |    2 +-
 setcc_no_zext.ll |    2 +-
 3 files changed, 3 insertions(+), 3 deletions(-)


Index: llvm/test/Regression/CodeGen/PowerPC/fnegsel.ll
diff -u llvm/test/Regression/CodeGen/PowerPC/fnegsel.ll:1.2 llvm/test/Regression/CodeGen/PowerPC/fnegsel.ll:1.3
--- llvm/test/Regression/CodeGen/PowerPC/fnegsel.ll:1.2	Sun Apr 10 15:45:35 2005
+++ llvm/test/Regression/CodeGen/PowerPC/fnegsel.ll	Thu Aug 18 20:16:18 2005
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=ppc32 -enable-ppc-pattern-isel | not grep fneg
+; RUN: llvm-as < %s | llc -march=ppc32 | not grep fneg
 
 double %test_FNEG_sel(double %A, double %B, double %C) {
     %D = sub double -0.0, %A


Index: llvm/test/Regression/CodeGen/PowerPC/select_lt0.ll
diff -u llvm/test/Regression/CodeGen/PowerPC/select_lt0.ll:1.1 llvm/test/Regression/CodeGen/PowerPC/select_lt0.ll:1.2
--- llvm/test/Regression/CodeGen/PowerPC/select_lt0.ll:1.1	Wed Apr 13 16:45:13 2005
+++ llvm/test/Regression/CodeGen/PowerPC/select_lt0.ll	Thu Aug 18 20:16:18 2005
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=ppc32 -enable-ppc-pattern-isel | not grep cmp
+; RUN: llvm-as < %s | llc -march=ppc32 | not grep cmp
 
 int %seli32_1(int %a) {
 entry:


Index: llvm/test/Regression/CodeGen/PowerPC/setcc_no_zext.ll
diff -u llvm/test/Regression/CodeGen/PowerPC/setcc_no_zext.ll:1.1 llvm/test/Regression/CodeGen/PowerPC/setcc_no_zext.ll:1.2
--- llvm/test/Regression/CodeGen/PowerPC/setcc_no_zext.ll:1.1	Wed Apr 13 16:45:13 2005
+++ llvm/test/Regression/CodeGen/PowerPC/setcc_no_zext.ll	Thu Aug 18 20:16:18 2005
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=ppc32 -enable-ppc-pattern-isel | not grep rlwinm
+; RUN: llvm-as < %s | llc -march=ppc32 | not grep rlwinm
 
 int %setcc_one_or_zero(int* %a) {
 entry:





From lattner at cs.uiuc.edu  Thu Aug 18 20:17:30 2005
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Thu, 18 Aug 2005 20:17:30 -0500
Subject: [llvm-commits] 
	CVS: llvm/test/Regression/CodeGen/Generic/shift-folding.ll
Message-ID: <200508190117.UAA00352@zion.cs.uiuc.edu>



Changes in directory llvm/test/Regression/CodeGen/Generic:

shift-folding.ll updated: 1.1 -> 1.2
---
Log message:

remove dead args


---
Diffs of the changes:  (+1 -1)

 shift-folding.ll |    2 +-
 1 files changed, 1 insertion(+), 1 deletion(-)


Index: llvm/test/Regression/CodeGen/Generic/shift-folding.ll
diff -u llvm/test/Regression/CodeGen/Generic/shift-folding.ll:1.1 llvm/test/Regression/CodeGen/Generic/shift-folding.ll:1.2
--- llvm/test/Regression/CodeGen/Generic/shift-folding.ll:1.1	Mon May  9 12:09:31 2005
+++ llvm/test/Regression/CodeGen/Generic/shift-folding.ll	Thu Aug 18 20:17:18 2005
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86 -enable-pattern-isel=1 | grep 's[ah][rl]l' | wc -l | grep 1
+; RUN: llvm-as < %s | llc -march=x86 | grep 's[ah][rl]l' | wc -l | grep 1
 
 int* %test1(int *%P, uint %X) {
 	%Y = shr uint %X, ubyte 2





From natebegeman at mac.com  Thu Aug 18 22:42:43 2005
From: natebegeman at mac.com (Nate Begeman)
Date: Thu, 18 Aug 2005 22:42:43 -0500
Subject: [llvm-commits] CVS: llvm/lib/Target/PowerPC/PPC32ISelPattern.cpp 
Message-ID: <200508190342.WAA01102@zion.cs.uiuc.edu>



Changes in directory llvm/lib/Target/PowerPC:

PPC32ISelPattern.cpp updated: 1.155 -> 1.156
---
Log message:

Fix a bug where we were passing the wrong number of arguments to an
instruction.


---
Diffs of the changes:  (+4 -1)

 PPC32ISelPattern.cpp |    5 ++++-
 1 files changed, 4 insertions(+), 1 deletion(-)


Index: llvm/lib/Target/PowerPC/PPC32ISelPattern.cpp
diff -u llvm/lib/Target/PowerPC/PPC32ISelPattern.cpp:1.155 llvm/lib/Target/PowerPC/PPC32ISelPattern.cpp:1.156
--- llvm/lib/Target/PowerPC/PPC32ISelPattern.cpp:1.155	Thu Aug 18 18:24:50 2005
+++ llvm/lib/Target/PowerPC/PPC32ISelPattern.cpp	Thu Aug 18 22:42:28 2005
@@ -469,7 +469,10 @@
   BuildMI(BB, PPC::MCRF, 1, PPC::CR7).addReg(CCReg);
   bool GPOpt =
     TLI.getTargetMachine().getSubtarget<PPCSubtarget>().isGigaProcessor();
-  BuildMI(BB, GPOpt ? PPC::MFOCRF : PPC::MFCR, 1, IntCR).addReg(PPC::CR7);
+  if (GPOpt)
+    BuildMI(BB, PPC::MFOCRF, 1, IntCR).addReg(PPC::CR7);
+  else
+    BuildMI(BB, PPC::MFCR, 0, IntCR);
   if (Inv) {
     unsigned Tmp1 = MakeIntReg();
     BuildMI(BB, PPC::RLWINM, 4, Tmp1).addReg(IntCR).addImm(32-(3-Idx))





From jeffc at jolt-lang.org  Thu Aug 18 23:40:00 2005
From: jeffc at jolt-lang.org (Jeff Cohen)
Date: Thu, 18 Aug 2005 23:40:00 -0500
Subject: [llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp 
Message-ID: <200508190440.XAA01400@zion.cs.uiuc.edu>



Changes in directory llvm/lib/CodeGen/SelectionDAG:

SelectionDAG.cpp updated: 1.149 -> 1.150
---
Log message:

Fix VC++ precedence warning.

---
Diffs of the changes:  (+1 -1)

 SelectionDAG.cpp |    2 +-
 1 files changed, 1 insertion(+), 1 deletion(-)


Index: llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp:1.149 llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp:1.150
--- llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp:1.149	Thu Aug 18 02:30:15 2005
+++ llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp	Thu Aug 18 23:39:48 2005
@@ -1171,7 +1171,7 @@
       if (Opcode == ISD::SRA) {
         // If the sign bit is known to be zero, switch this to a SRL.
         if (MaskedValueIsZero(N1,
-                              1ULL << MVT::getSizeInBits(N1.getValueType())-1,
+                              1ULL << (MVT::getSizeInBits(N1.getValueType())-1),
                               TLI))
           return getNode(ISD::SRL, N1.getValueType(), N1, N2);
       } else {





From lattner at cs.uiuc.edu  Fri Aug 19 01:16:16 2005
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Fri, 19 Aug 2005 01:16:16 -0500
Subject: [llvm-commits] CVS: llvm/utils/TableGen/CodeGenTarget.cpp 
Message-ID: <200508190616.BAA02128@zion.cs.uiuc.edu>



Changes in directory llvm/utils/TableGen:

CodeGenTarget.cpp updated: 1.29 -> 1.30
---
Log message:

Fix a problem jeffc noticed


---
Diffs of the changes:  (+1 -0)

 CodeGenTarget.cpp |    1 +
 1 files changed, 1 insertion(+)


Index: llvm/utils/TableGen/CodeGenTarget.cpp
diff -u llvm/utils/TableGen/CodeGenTarget.cpp:1.29 llvm/utils/TableGen/CodeGenTarget.cpp:1.30
--- llvm/utils/TableGen/CodeGenTarget.cpp:1.29	Thu Aug 18 18:38:41 2005
+++ llvm/utils/TableGen/CodeGenTarget.cpp	Fri Aug 19 01:16:04 2005
@@ -257,6 +257,7 @@
           NumOps = Rec->getValueAsInt("NumMIOperands");
         } else if (Rec->getName() == "variable_ops") {
           hasVariableNumberOfOperands = true;
+          continue;
         } else
           throw "Unknown operand class '" + Rec->getName() +
                 "' in instruction '" + R->getName() + "' instruction!";





From duraid at octopus.com.au  Fri Aug 19 08:26:01 2005
From: duraid at octopus.com.au (Duraid Madina)
Date: Fri, 19 Aug 2005 08:26:01 -0500
Subject: [llvm-commits] CVS: llvm/lib/Target/IA64/IA64ISelPattern.cpp 
Message-ID: <200508191326.IAA02335@zion.cs.uiuc.edu>



Changes in directory llvm/lib/Target/IA64:

IA64ISelPattern.cpp updated: 1.55 -> 1.56
---
Log message:

a bugfix (up top) and a quick repair job: disable generation of dep.z
(which died about a week ago) so we're back to load-(2^n-1)-then-AND
sequences. slow, but things should now be Almost Completely Working,
modulo those pesky alignment/ABI issues.



---
Diffs of the changes:  (+3 -3)

 IA64ISelPattern.cpp |    6 +++---
 1 files changed, 3 insertions(+), 3 deletions(-)


Index: llvm/lib/Target/IA64/IA64ISelPattern.cpp
diff -u llvm/lib/Target/IA64/IA64ISelPattern.cpp:1.55 llvm/lib/Target/IA64/IA64ISelPattern.cpp:1.56
--- llvm/lib/Target/IA64/IA64ISelPattern.cpp:1.55	Tue Aug 16 16:56:37 2005
+++ llvm/lib/Target/IA64/IA64ISelPattern.cpp	Fri Aug 19 08:25:50 2005
@@ -1220,7 +1220,7 @@
     case MVT::i16: depositPos=0; depositLen=16; break;
     case MVT::i32: depositPos=0; depositLen=32; break;
     }
-    BuildMI(BB, IA64::DEPZ, 1, Result).addReg(Tmp1)
+    BuildMI(BB, IA64::DEPZ, 3, Result).addReg(Tmp1)
       .addImm(depositPos).addImm(depositLen);
     return Result;
   }
@@ -1439,7 +1439,7 @@
     case MVT::i32:
     case MVT::i64: {
       Tmp1 = SelectExpr(N.getOperand(0));
-      switch (ponderIntegerAndWith(N.getOperand(1), Tmp3)) {
+/* FIXME     switch (ponderIntegerAndWith(N.getOperand(1), Tmp3)) {
         case 1: // ANDing a constant that is 2^n-1 for some n
           switch (Tmp3) {
             case 8:  // if AND 0x00000000000000FF, be quaint and use zxt1
@@ -1457,7 +1457,7 @@
               break;
           }
           return Result; // early exit
-      } // fallthrough and emit a simple AND:
+  FIXME } */ // fallthrough and emit a simple AND:
       Tmp2 = SelectExpr(N.getOperand(1));
       BuildMI(BB, IA64::AND, 2, Result).addReg(Tmp1).addReg(Tmp2);
     }





From jeffc at jolt-lang.org  Fri Aug 19 08:51:33 2005
From: jeffc at jolt-lang.org (Jeff Cohen)
Date: Fri, 19 Aug 2005 08:51:33 -0500
Subject: [llvm-commits] CVS: llvm/win32/x86/x86.vcproj 
Message-ID: <200508191351.IAA02451@zion.cs.uiuc.edu>



Changes in directory llvm/win32/x86:

x86.vcproj updated: 1.13 -> 1.14
---
Log message:

Update Visual Studio projects for removed file.

---
Diffs of the changes:  (+0 -3)

 x86.vcproj |    3 ---
 1 files changed, 3 deletions(-)


Index: llvm/win32/x86/x86.vcproj
diff -u llvm/win32/x86/x86.vcproj:1.13 llvm/win32/x86/x86.vcproj:1.14
--- llvm/win32/x86/x86.vcproj:1.13	Mon Jul 11 22:00:20 2005
+++ llvm/win32/x86/x86.vcproj	Fri Aug 19 08:51:22 2005
@@ -167,9 +167,6 @@
 				RelativePath="..\..\lib\Target\X86\X86ISelPattern.cpp">
 			</File>
 			<File
-				RelativePath="..\..\lib\Target\X86\X86ISelSimple.cpp">
-			</File>
-			<File
 				RelativePath="..\..\lib\Target\X86\X86JITInfo.cpp">
 			</File>
 			<File





From lattner at cs.uiuc.edu  Fri Aug 19 11:09:01 2005
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Fri, 19 Aug 2005 11:09:01 -0500
Subject: [llvm-commits] 
	CVS: llvm-test/SingleSource/UnitTests/2005-07-17-INT-To-FP.c
Message-ID: <200508191609.LAA03182@zion.cs.uiuc.edu>



Changes in directory llvm-test/SingleSource/UnitTests:

2005-07-17-INT-To-FP.c updated: 1.2 -> 1.3
---
Log message:

Make this compile


---
Diffs of the changes:  (+1 -1)

 2005-07-17-INT-To-FP.c |    2 +-
 1 files changed, 1 insertion(+), 1 deletion(-)


Index: llvm-test/SingleSource/UnitTests/2005-07-17-INT-To-FP.c
diff -u llvm-test/SingleSource/UnitTests/2005-07-17-INT-To-FP.c:1.2 llvm-test/SingleSource/UnitTests/2005-07-17-INT-To-FP.c:1.3
--- llvm-test/SingleSource/UnitTests/2005-07-17-INT-To-FP.c:1.2	Thu Aug 18 12:16:22 2005
+++ llvm-test/SingleSource/UnitTests/2005-07-17-INT-To-FP.c	Fri Aug 19 11:08:50 2005
@@ -33,7 +33,7 @@
            (double)(unsigned long long)((unsigned long long)i << 58ULL));  // i64
   }
   // edge case tests
-  for (unsigned i = 0; i < (sizeof(tests) / sizeof(int)); i++) {
+  for (i = 0; i < (sizeof(tests) / sizeof(int)); i++) {
     printf("%d %f %f %f %f\n", (double)(unsigned)tests[i],
                                (double)(  signed)tests[i],
                                (float) (unsigned)tests[i],





From jeffc at jolt-lang.org  Fri Aug 19 11:19:32 2005
From: jeffc at jolt-lang.org (Jeff Cohen)
Date: Fri, 19 Aug 2005 11:19:32 -0500
Subject: [llvm-commits] CVS: llvm/lib/CodeGen/ELFWriter.cpp 
Message-ID: <200508191619.LAA06854@zion.cs.uiuc.edu>



Changes in directory llvm/lib/CodeGen:

ELFWriter.cpp updated: 1.14 -> 1.15
---
Log message:

Fix VC++ constant truncation warning.

---
Diffs of the changes:  (+2 -2)

 ELFWriter.cpp |    4 ++--
 1 files changed, 2 insertions(+), 2 deletions(-)


Index: llvm/lib/CodeGen/ELFWriter.cpp
diff -u llvm/lib/CodeGen/ELFWriter.cpp:1.14 llvm/lib/CodeGen/ELFWriter.cpp:1.15
--- llvm/lib/CodeGen/ELFWriter.cpp:1.14	Thu Jul 28 13:13:59 2005
+++ llvm/lib/CodeGen/ELFWriter.cpp	Fri Aug 19 11:19:21 2005
@@ -499,7 +499,7 @@
     if (S.Align)
       for (size_t NewFileOff = (FileOff+S.Align-1) & ~(S.Align-1);
            FileOff != NewFileOff; ++FileOff)
-        O.put(0xAB);
+        O.put((char)0xAB);
     O.write((char*)&S.SectionData[0], S.SectionData.size());
     FileOff += S.SectionData.size();
 
@@ -520,7 +520,7 @@
   // Align output for the section table.
   for (size_t NewFileOff = (FileOff+TableAlign-1) & ~(TableAlign-1);
        FileOff != NewFileOff; ++FileOff)
-    O.put(0xAB);
+    O.put((char)0xAB);
 
   // Emit the section table itself.
   O.write((char*)&Table[0], Table.size());





From lattner at cs.uiuc.edu  Fri Aug 19 11:56:37 2005
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Fri, 19 Aug 2005 11:56:37 -0500
Subject: [llvm-commits] CVS: llvm/include/llvm/Target/TargetInstrInfo.h 
Message-ID: <200508191656.LAA07114@zion.cs.uiuc.edu>



Changes in directory llvm/include/llvm/Target:

TargetInstrInfo.h updated: 1.77 -> 1.78
---
Log message:

Add a new field to TargetInstrDescriptor for tracking information about
operands.


---
Diffs of the changes:  (+15 -0)

 TargetInstrInfo.h |   15 +++++++++++++++
 1 files changed, 15 insertions(+)


Index: llvm/include/llvm/Target/TargetInstrInfo.h
diff -u llvm/include/llvm/Target/TargetInstrInfo.h:1.77 llvm/include/llvm/Target/TargetInstrInfo.h:1.78
--- llvm/include/llvm/Target/TargetInstrInfo.h:1.77	Thu Apr 21 22:46:24 2005
+++ llvm/include/llvm/Target/TargetInstrInfo.h	Fri Aug 19 11:56:26 2005
@@ -29,6 +29,7 @@
 class Constant;
 class Function;
 class MachineCodeForInstruction;
+class TargetRegisterClass;
 
 //---------------------------------------------------------------------------
 // Data types used to define information about a single machine instruction
@@ -72,6 +73,19 @@
 // before control flow occurs.
 const unsigned M_TERMINATOR_FLAG       = 1 << 12;
 
+/// TargetOperandInfo - This holds information about one operand of a machine
+/// instruction, indicating the register class for register operands, etc.
+///
+class TargetOperandInfo {
+public:
+  /// RegClass - This specifies the register class of the operand if the
+  /// operand is a register.  If not, this contains null.
+  const TargetRegisterClass *RegClass;
+  
+  /// Currently no other information.
+};
+
+
 class TargetInstrDescriptor {
 public:
   const char *    Name;          // Assembly language mnemonic for the opcode.
@@ -87,6 +101,7 @@
   unsigned        TSFlags;       // Target Specific Flag values
   const unsigned *ImplicitUses;  // Registers implicitly read by this instr
   const unsigned *ImplicitDefs;  // Registers implicitly defined by this instr
+  const TargetOperandInfo *OpInfo; // 'numOperands' entries about operands.
 };
 
 





From lattner at cs.uiuc.edu  Fri Aug 19 11:57:07 2005
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Fri, 19 Aug 2005 11:57:07 -0500
Subject: [llvm-commits] 
	CVS: llvm/lib/Target/SparcV9/SparcV9TargetMachine.cpp
Message-ID: <200508191657.LAA07172@zion.cs.uiuc.edu>



Changes in directory llvm/lib/Target/SparcV9:

SparcV9TargetMachine.cpp updated: 1.140 -> 1.141
---
Log message:

Sparcv9 gets no operand info


---
Diffs of the changes:  (+1 -1)

 SparcV9TargetMachine.cpp |    2 +-
 1 files changed, 1 insertion(+), 1 deletion(-)


Index: llvm/lib/Target/SparcV9/SparcV9TargetMachine.cpp
diff -u llvm/lib/Target/SparcV9/SparcV9TargetMachine.cpp:1.140 llvm/lib/Target/SparcV9/SparcV9TargetMachine.cpp:1.141
--- llvm/lib/Target/SparcV9/SparcV9TargetMachine.cpp:1.140	Wed Jul 27 00:53:43 2005
+++ llvm/lib/Target/SparcV9/SparcV9TargetMachine.cpp	Fri Aug 19 11:56:56 2005
@@ -39,7 +39,7 @@
           NUMDELAYSLOTS, LATENCY, SCHEDCLASS, INSTFLAGS)             \
   { OPCODESTRING, NUMOPERANDS, RESULTPOS, MAXIMM, IMMSE,             \
           NUMDELAYSLOTS, LATENCY, SCHEDCLASS, INSTFLAGS, 0,          \
-          ImplicitRegUseList, ImplicitRegUseList },
+          ImplicitRegUseList, ImplicitRegUseList, 0 },
 #include "SparcV9Instr.def"
 };
 





From lattner at cs.uiuc.edu  Fri Aug 19 11:57:39 2005
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Fri, 19 Aug 2005 11:57:39 -0500
Subject: [llvm-commits] CVS: llvm/utils/TableGen/CodeGenInstruction.h
	InstrInfoEmitter.cpp 
Message-ID: <200508191657.LAA07234@zion.cs.uiuc.edu>



Changes in directory llvm/utils/TableGen:

CodeGenInstruction.h updated: 1.9 -> 1.10
InstrInfoEmitter.cpp updated: 1.22 -> 1.23
---
Log message:

For now, just emit empty operand info structures.


---
Diffs of the changes:  (+24 -2)

 CodeGenInstruction.h |    1 +
 InstrInfoEmitter.cpp |   25 +++++++++++++++++++++++--
 2 files changed, 24 insertions(+), 2 deletions(-)


Index: llvm/utils/TableGen/CodeGenInstruction.h
diff -u llvm/utils/TableGen/CodeGenInstruction.h:1.9 llvm/utils/TableGen/CodeGenInstruction.h:1.10
--- llvm/utils/TableGen/CodeGenInstruction.h:1.9	Thu Aug 18 18:38:41 2005
+++ llvm/utils/TableGen/CodeGenInstruction.h	Fri Aug 19 11:57:28 2005
@@ -35,6 +35,7 @@
     /// operand list for a tablegen instruction.
     struct OperandInfo {
       /// Rec - The definition this operand is declared as.
+      ///
       Record *Rec;
 
       /// Ty - The MachineValueType of the operand.


Index: llvm/utils/TableGen/InstrInfoEmitter.cpp
diff -u llvm/utils/TableGen/InstrInfoEmitter.cpp:1.22 llvm/utils/TableGen/InstrInfoEmitter.cpp:1.23
--- llvm/utils/TableGen/InstrInfoEmitter.cpp:1.22	Thu Aug 18 19:59:49 2005
+++ llvm/utils/TableGen/InstrInfoEmitter.cpp	Fri Aug 19 11:57:28 2005
@@ -103,6 +103,21 @@
     }
   }
 
+  // Emit all of the operand info records.
+  OS << "\n";
+  for (CodeGenTarget::inst_iterator II = Target.inst_begin(),
+       E = Target.inst_end(); II != E; ++II) {
+    const CodeGenInstruction &Inst = II->second;
+    if (!Inst.hasVariableNumberOfOperands) {
+      OS << "static const TargetOperandInfo " << Inst.TheDef->getName()
+         << "_Operands[] = {";
+      // FIXME: Emit operand info.
+      OS << "};\n";
+    }
+  }
+  
+  // Emit all of the TargetInstrDescriptor records.
+  //
   OS << "\nstatic const TargetInstrDescriptor " << TargetName
      << "Insts[] = {\n";
   emitRecord(Target.getPHIInstruction(), 0, InstrInfo, ListNumbers, OS);
@@ -173,10 +188,16 @@
 
   LI = Inst.TheDef->getValueAsListInit("Defs");
   if (!LI->getSize())
-    OS << "EmptyImpList ";
+    OS << "EmptyImpList, ";
   else
-    OS << "ImplicitList" << ListNumbers[LI] << " ";
+    OS << "ImplicitList" << ListNumbers[LI] << ", ";
 
+  // Emit the operand info.
+  if (NumOperands == -1)
+    OS << "0 ";
+  else
+    OS << Inst.TheDef->getName() << "_Operands ";
+  
   OS << " },  // Inst #" << Num << " = " << Inst.TheDef->getName() << "\n";
 }
 





From lattner at cs.uiuc.edu  Fri Aug 19 12:58:23 2005
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Fri, 19 Aug 2005 12:58:23 -0500
Subject: [llvm-commits] CVS: llvm/utils/TableGen/Record.cpp Record.h 
Message-ID: <200508191758.MAA07686@zion.cs.uiuc.edu>



Changes in directory llvm/utils/TableGen:

Record.cpp updated: 1.43 -> 1.44
Record.h updated: 1.49 -> 1.50
---
Log message:

Add a setName method to Record.


---
Diffs of the changes:  (+26 -0)

 Record.cpp |   12 ++++++++++++
 Record.h   |   14 ++++++++++++++
 2 files changed, 26 insertions(+)


Index: llvm/utils/TableGen/Record.cpp
diff -u llvm/utils/TableGen/Record.cpp:1.43 llvm/utils/TableGen/Record.cpp:1.44
--- llvm/utils/TableGen/Record.cpp:1.43	Thu Apr 21 23:13:13 2005
+++ llvm/utils/TableGen/Record.cpp	Fri Aug 19 12:58:11 2005
@@ -589,6 +589,18 @@
   if (PrintSem) OS << ";\n";
 }
 
+void Record::setName(const std::string &Name) {
+  if (Records.getDef(getName()) == this) {
+    Records.removeDef(getName());
+    this->Name = Name;
+    Records.addDef(this);
+  } else {
+    Records.removeClass(getName());
+    this->Name = Name;
+    Records.addClass(this);
+  }
+}
+
 /// resolveReferencesTo - If anything in this record refers to RV, replace the
 /// reference to RV with the RHS of RV.  If RV is null, we resolve all possible
 /// references.


Index: llvm/utils/TableGen/Record.h
diff -u llvm/utils/TableGen/Record.h:1.49 llvm/utils/TableGen/Record.h:1.50
--- llvm/utils/TableGen/Record.h:1.49	Thu Apr 21 23:13:13 2005
+++ llvm/utils/TableGen/Record.h	Fri Aug 19 12:58:11 2005
@@ -898,6 +898,7 @@
   ~Record() {}
 
   const std::string &getName() const { return Name; }
+  void setName(const std::string &Name);  // Also updates RecordKeeper.
   const std::vector<std::string> &getTemplateArgs() const {
     return TemplateArgs;
   }
@@ -1058,6 +1059,19 @@
     Defs.insert(std::make_pair(R->getName(), R));
   }
 
+  /// removeClass - Remove, but do not delete, the specified record.
+  ///
+  void removeClass(const std::string &Name) {
+    assert(Classes.count(Name) && "Class does not exist!");
+    Classes.erase(Name);
+  }
+  /// removeDef - Remove, but do not delete, the specified record.
+  ///
+  void removeDef(const std::string &Name) {
+    assert(Defs.count(Name) && "Def does not exist!");
+    Defs.erase(Name);
+  }
+  
   //===--------------------------------------------------------------------===//
   // High-level helper methods, useful for tablegen backends...
 





From lattner at cs.uiuc.edu  Fri Aug 19 12:59:00 2005
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Fri, 19 Aug 2005 12:59:00 -0500
Subject: [llvm-commits] CVS: llvm/utils/TableGen/Record.h 
Message-ID: <200508191759.MAA07770@zion.cs.uiuc.edu>



Changes in directory llvm/utils/TableGen:

Record.h updated: 1.50 -> 1.51
---
Log message:

add a setName method to record


---
Diffs of the changes:  (+1 -1)

 Record.h |    2 +-
 1 files changed, 1 insertion(+), 1 deletion(-)


Index: llvm/utils/TableGen/Record.h
diff -u llvm/utils/TableGen/Record.h:1.50 llvm/utils/TableGen/Record.h:1.51
--- llvm/utils/TableGen/Record.h:1.50	Fri Aug 19 12:58:11 2005
+++ llvm/utils/TableGen/Record.h	Fri Aug 19 12:58:49 2005
@@ -888,7 +888,7 @@
 }
 
 class Record {
-  const std::string Name;
+  std::string Name;
   std::vector<std::string> TemplateArgs;
   std::vector<RecordVal> Values;
   std::vector<Record*> SuperClasses;





From lattner at cs.uiuc.edu  Fri Aug 19 13:30:51 2005
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Fri, 19 Aug 2005 13:30:51 -0500
Subject: [llvm-commits] CVS: llvm/lib/Target/PowerPC/PPC32RegisterInfo.cpp
	PPC32RegisterInfo.h 
Message-ID: <200508191830.NAA08038@zion.cs.uiuc.edu>



Changes in directory llvm/lib/Target/PowerPC:

PPC32RegisterInfo.cpp updated: 1.17 -> 1.18
PPC32RegisterInfo.h updated: 1.2 -> 1.3
---
Log message:

Now that the simple isels are dead, so is this.


---
Diffs of the changes:  (+0 -21)

 PPC32RegisterInfo.cpp |   20 --------------------
 PPC32RegisterInfo.h   |    1 -
 2 files changed, 21 deletions(-)


Index: llvm/lib/Target/PowerPC/PPC32RegisterInfo.cpp
diff -u llvm/lib/Target/PowerPC/PPC32RegisterInfo.cpp:1.17 llvm/lib/Target/PowerPC/PPC32RegisterInfo.cpp:1.18
--- llvm/lib/Target/PowerPC/PPC32RegisterInfo.cpp:1.17	Thu Aug 18 18:24:50 2005
+++ llvm/lib/Target/PowerPC/PPC32RegisterInfo.cpp	Fri Aug 19 13:30:39 2005
@@ -305,23 +305,3 @@
 
 #include "PPC32GenRegisterInfo.inc"
 
-const TargetRegisterClass*
-PPC32RegisterInfo::getRegClassForType(const Type* Ty) const {
-  switch (Ty->getTypeID()) {
-    default:              assert(0 && "Invalid type to getClass!");
-    case Type::LongTyID:
-    case Type::ULongTyID: assert(0 && "Long values can't fit in registers!");
-    case Type::BoolTyID:
-    case Type::SByteTyID:
-    case Type::UByteTyID:
-    case Type::ShortTyID:
-    case Type::UShortTyID:
-    case Type::IntTyID:
-    case Type::UIntTyID:
-    case Type::PointerTyID: return &GPRCInstance;
-
-    case Type::FloatTyID:
-    case Type::DoubleTyID: return &FPRCInstance;
-  }
-}
-


Index: llvm/lib/Target/PowerPC/PPC32RegisterInfo.h
diff -u llvm/lib/Target/PowerPC/PPC32RegisterInfo.h:1.2 llvm/lib/Target/PowerPC/PPC32RegisterInfo.h:1.3
--- llvm/lib/Target/PowerPC/PPC32RegisterInfo.h:1.2	Thu Apr 21 18:20:02 2005
+++ llvm/lib/Target/PowerPC/PPC32RegisterInfo.h	Fri Aug 19 13:30:39 2005
@@ -26,7 +26,6 @@
   std::map<unsigned, unsigned> ImmToIdxMap;
 public:
   PPC32RegisterInfo();
-  const TargetRegisterClass* getRegClassForType(const Type* Ty) const;
 
   /// Code Generation virtual methods...
   void storeRegToStackSlot(MachineBasicBlock &MBB,





From lattner at cs.uiuc.edu  Fri Aug 19 13:32:15 2005
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Fri, 19 Aug 2005 13:32:15 -0500
Subject: [llvm-commits] CVS: llvm/lib/Target/X86/X86RegisterInfo.h
	X86RegisterInfo.cpp 
Message-ID: <200508191832.NAA08097@zion.cs.uiuc.edu>



Changes in directory llvm/lib/Target/X86:

X86RegisterInfo.h updated: 1.29 -> 1.30
X86RegisterInfo.cpp updated: 1.107 -> 1.108
---
Log message:

The simple isel being gone makes this dead!


---
Diffs of the changes:  (+0 -20)

 X86RegisterInfo.cpp |   19 -------------------
 X86RegisterInfo.h   |    1 -
 2 files changed, 20 deletions(-)


Index: llvm/lib/Target/X86/X86RegisterInfo.h
diff -u llvm/lib/Target/X86/X86RegisterInfo.h:1.29 llvm/lib/Target/X86/X86RegisterInfo.h:1.30
--- llvm/lib/Target/X86/X86RegisterInfo.h:1.29	Thu Apr 21 18:38:14 2005
+++ llvm/lib/Target/X86/X86RegisterInfo.h	Fri Aug 19 13:32:03 2005
@@ -24,7 +24,6 @@
 
 struct X86RegisterInfo : public X86GenRegisterInfo {
   X86RegisterInfo();
-  const TargetRegisterClass* getRegClassForType(const Type* Ty) const;
 
   /// Code Generation virtual methods...
   void storeRegToStackSlot(MachineBasicBlock &MBB,


Index: llvm/lib/Target/X86/X86RegisterInfo.cpp
diff -u llvm/lib/Target/X86/X86RegisterInfo.cpp:1.107 llvm/lib/Target/X86/X86RegisterInfo.cpp:1.108
--- llvm/lib/Target/X86/X86RegisterInfo.cpp:1.107	Wed Jul 27 01:12:34 2005
+++ llvm/lib/Target/X86/X86RegisterInfo.cpp	Fri Aug 19 13:32:03 2005
@@ -572,22 +572,3 @@
 
 #include "X86GenRegisterInfo.inc"
 
-const TargetRegisterClass*
-X86RegisterInfo::getRegClassForType(const Type* Ty) const {
-  switch (Ty->getTypeID()) {
-  case Type::LongTyID:
-  case Type::ULongTyID: assert(0 && "Long values can't fit in registers!");
-  default:              assert(0 && "Invalid type to getClass!");
-  case Type::BoolTyID:
-  case Type::SByteTyID:
-  case Type::UByteTyID:   return &R8Instance;
-  case Type::ShortTyID:
-  case Type::UShortTyID:  return &R16Instance;
-  case Type::IntTyID:
-  case Type::UIntTyID:
-  case Type::PointerTyID: return &R32Instance;
-
-  case Type::FloatTyID:
-  case Type::DoubleTyID: return &RFPInstance;
-  }
-}





From lattner at cs.uiuc.edu  Fri Aug 19 13:33:38 2005
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Fri, 19 Aug 2005 13:33:38 -0500
Subject: [llvm-commits] CVS: llvm/lib/Target/Alpha/AlphaRegisterInfo.h
	AlphaRegisterInfo.cpp 
Message-ID: <200508191833.NAA08157@zion.cs.uiuc.edu>



Changes in directory llvm/lib/Target/Alpha:

AlphaRegisterInfo.h updated: 1.4 -> 1.5
AlphaRegisterInfo.cpp updated: 1.25 -> 1.26
---
Log message:

This code has always been dead for alpha


---
Diffs of the changes:  (+0 -21)

 AlphaRegisterInfo.cpp |   20 --------------------
 AlphaRegisterInfo.h   |    1 -
 2 files changed, 21 deletions(-)


Index: llvm/lib/Target/Alpha/AlphaRegisterInfo.h
diff -u llvm/lib/Target/Alpha/AlphaRegisterInfo.h:1.4 llvm/lib/Target/Alpha/AlphaRegisterInfo.h:1.5
--- llvm/lib/Target/Alpha/AlphaRegisterInfo.h:1.4	Thu Apr 21 18:10:23 2005
+++ llvm/lib/Target/Alpha/AlphaRegisterInfo.h	Fri Aug 19 13:33:26 2005
@@ -23,7 +23,6 @@
 
 struct AlphaRegisterInfo : public AlphaGenRegisterInfo {
   AlphaRegisterInfo();
-  const TargetRegisterClass* getRegClassForType(const Type* Ty) const;
 
   /// Code Generation virtual methods...
   void storeRegToStackSlot(MachineBasicBlock &MBB,


Index: llvm/lib/Target/Alpha/AlphaRegisterInfo.cpp
diff -u llvm/lib/Target/Alpha/AlphaRegisterInfo.cpp:1.25 llvm/lib/Target/Alpha/AlphaRegisterInfo.cpp:1.26
--- llvm/lib/Target/Alpha/AlphaRegisterInfo.cpp:1.25	Fri Jul 22 15:52:16 2005
+++ llvm/lib/Target/Alpha/AlphaRegisterInfo.cpp	Fri Aug 19 13:33:26 2005
@@ -333,26 +333,6 @@
 
 #include "AlphaGenRegisterInfo.inc"
 
-const TargetRegisterClass*
-AlphaRegisterInfo::getRegClassForType(const Type* Ty) const {
-  switch (Ty->getTypeID()) {
-    default:              assert(0 && "Invalid type to getClass!");
-    case Type::BoolTyID:
-    case Type::SByteTyID:
-    case Type::UByteTyID:
-    case Type::ShortTyID:
-    case Type::UShortTyID:
-    case Type::IntTyID:
-    case Type::UIntTyID:
-    case Type::PointerTyID:
-    case Type::LongTyID:
-    case Type::ULongTyID:  return &GPRCInstance;
-
-  case Type::FloatTyID:
-  case Type::DoubleTyID: return &FPRCInstance;
-  }
-}
-
 std::string AlphaRegisterInfo::getPrettyName(unsigned reg)
 {
   std::string s(RegisterDescriptors[reg].Name);





From lattner at cs.uiuc.edu  Fri Aug 19 13:34:48 2005
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Fri, 19 Aug 2005 13:34:48 -0500
Subject: [llvm-commits] CVS: llvm/lib/Target/IA64/IA64RegisterInfo.h
	IA64RegisterInfo.cpp 
Message-ID: <200508191834.NAA08225@zion.cs.uiuc.edu>



Changes in directory llvm/lib/Target/IA64:

IA64RegisterInfo.h updated: 1.2 -> 1.3
IA64RegisterInfo.cpp updated: 1.5 -> 1.6
---
Log message:

This code has always been dead on itanium


---
Diffs of the changes:  (+0 -22)

 IA64RegisterInfo.cpp |   21 ---------------------
 IA64RegisterInfo.h   |    1 -
 2 files changed, 22 deletions(-)


Index: llvm/lib/Target/IA64/IA64RegisterInfo.h
diff -u llvm/lib/Target/IA64/IA64RegisterInfo.h:1.2 llvm/lib/Target/IA64/IA64RegisterInfo.h:1.3
--- llvm/lib/Target/IA64/IA64RegisterInfo.h:1.2	Thu Apr 21 18:13:11 2005
+++ llvm/lib/Target/IA64/IA64RegisterInfo.h	Fri Aug 19 13:34:37 2005
@@ -23,7 +23,6 @@
 
 struct IA64RegisterInfo : public IA64GenRegisterInfo {
   IA64RegisterInfo();
-  const TargetRegisterClass* getRegClassForType(const Type* Ty) const;
 
   /// Code Generation virtual methods...
   void storeRegToStackSlot(MachineBasicBlock &MBB,


Index: llvm/lib/Target/IA64/IA64RegisterInfo.cpp
diff -u llvm/lib/Target/IA64/IA64RegisterInfo.cpp:1.5 llvm/lib/Target/IA64/IA64RegisterInfo.cpp:1.6
--- llvm/lib/Target/IA64/IA64RegisterInfo.cpp:1.5	Fri Apr 22 12:54:15 2005
+++ llvm/lib/Target/IA64/IA64RegisterInfo.cpp	Fri Aug 19 13:34:37 2005
@@ -339,24 +339,3 @@
 
 #include "IA64GenRegisterInfo.inc"
 
-const TargetRegisterClass*
-IA64RegisterInfo::getRegClassForType(const Type* Ty) const {
-  switch (Ty->getTypeID()) {
-  default:              assert(0 && "Invalid type to getClass!");
-  case Type::LongTyID:
-  case Type::ULongTyID:
-  case Type::BoolTyID:
-  case Type::SByteTyID:
-  case Type::UByteTyID:
-  case Type::ShortTyID:
-  case Type::UShortTyID:
-  case Type::IntTyID:
-  case Type::UIntTyID:
-  case Type::PointerTyID: return &GRInstance;
-
-  case Type::FloatTyID:
-  case Type::DoubleTyID: return &FPInstance;
-  }
-}
-
-





From lattner at cs.uiuc.edu  Fri Aug 19 13:35:52 2005
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Fri, 19 Aug 2005 13:35:52 -0500
Subject: [llvm-commits] CVS: llvm/lib/Target/Skeleton/SkeletonRegisterInfo.h
	SkeletonRegisterInfo.cpp 
Message-ID: <200508191835.NAA08287@zion.cs.uiuc.edu>



Changes in directory llvm/lib/Target/Skeleton:

SkeletonRegisterInfo.h updated: 1.6 -> 1.7
SkeletonRegisterInfo.cpp updated: 1.5 -> 1.6
---
Log message:

The skeleton target has never had an isel


---
Diffs of the changes:  (+0 -21)

 SkeletonRegisterInfo.cpp |   20 --------------------
 SkeletonRegisterInfo.h   |    1 -
 2 files changed, 21 deletions(-)


Index: llvm/lib/Target/Skeleton/SkeletonRegisterInfo.h
diff -u llvm/lib/Target/Skeleton/SkeletonRegisterInfo.h:1.6 llvm/lib/Target/Skeleton/SkeletonRegisterInfo.h:1.7
--- llvm/lib/Target/Skeleton/SkeletonRegisterInfo.h:1.6	Thu Apr 21 18:20:35 2005
+++ llvm/lib/Target/Skeleton/SkeletonRegisterInfo.h	Fri Aug 19 13:35:41 2005
@@ -21,7 +21,6 @@
 
   struct SkeletonRegisterInfo : public SkeletonGenRegisterInfo {
     SkeletonRegisterInfo();
-    const TargetRegisterClass* getRegClassForType(const Type* Ty) const;
 
     void storeRegToStackSlot(MachineBasicBlock &MBB,
                              MachineBasicBlock::iterator MBBI,


Index: llvm/lib/Target/Skeleton/SkeletonRegisterInfo.cpp
diff -u llvm/lib/Target/Skeleton/SkeletonRegisterInfo.cpp:1.5 llvm/lib/Target/Skeleton/SkeletonRegisterInfo.cpp:1.6
--- llvm/lib/Target/Skeleton/SkeletonRegisterInfo.cpp:1.5	Thu Apr 21 18:20:35 2005
+++ llvm/lib/Target/Skeleton/SkeletonRegisterInfo.cpp	Fri Aug 19 13:35:41 2005
@@ -67,23 +67,3 @@
 
 #include "SkeletonGenRegisterInfo.inc"
 
-const TargetRegisterClass*
-SkeletonRegisterInfo::getRegClassForType(const Type* Ty) const {
-  switch (Ty->getTypeID()) {
-  case Type::LongTyID:
-  case Type::ULongTyID: assert(0 && "Long values can't fit in registers!");
-  default:              assert(0 && "Invalid type to getClass!");
-  case Type::BoolTyID:
-  case Type::SByteTyID:
-  case Type::UByteTyID:
-  case Type::ShortTyID:
-  case Type::UShortTyID:
-  case Type::IntTyID:
-  case Type::UIntTyID:
-  case Type::PointerTyID: return &GPRCInstance;
-
-  case Type::FloatTyID:
-  case Type::DoubleTyID: return &FPRCInstance;
-  }
-}
-





From lattner at cs.uiuc.edu  Fri Aug 19 13:45:31 2005
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Fri, 19 Aug 2005 13:45:31 -0500
Subject: [llvm-commits] CVS: llvm/utils/TableGen/CodeGenRegisters.h
	CodeGenTarget.cpp 
Message-ID: <200508191845.NAA08477@zion.cs.uiuc.edu>



Changes in directory llvm/utils/TableGen:

CodeGenRegisters.h updated: 1.5 -> 1.6
CodeGenTarget.cpp updated: 1.30 -> 1.31
---
Log message:

Read the namespace field from register classes


---
Diffs of the changes:  (+8 -0)

 CodeGenRegisters.h |    1 +
 CodeGenTarget.cpp  |    7 +++++++
 2 files changed, 8 insertions(+)


Index: llvm/utils/TableGen/CodeGenRegisters.h
diff -u llvm/utils/TableGen/CodeGenRegisters.h:1.5 llvm/utils/TableGen/CodeGenRegisters.h:1.6
--- llvm/utils/TableGen/CodeGenRegisters.h:1.5	Thu Apr 21 19:00:35 2005
+++ llvm/utils/TableGen/CodeGenRegisters.h	Fri Aug 19 13:45:20 2005
@@ -32,6 +32,7 @@
 
   struct CodeGenRegisterClass {
     Record *TheDef;
+    std::string Namespace;
     std::vector<Record*> Elements;
     unsigned SpillSize;
     unsigned SpillAlignment;


Index: llvm/utils/TableGen/CodeGenTarget.cpp
diff -u llvm/utils/TableGen/CodeGenTarget.cpp:1.30 llvm/utils/TableGen/CodeGenTarget.cpp:1.31
--- llvm/utils/TableGen/CodeGenTarget.cpp:1.30	Fri Aug 19 01:16:04 2005
+++ llvm/utils/TableGen/CodeGenTarget.cpp	Fri Aug 19 13:45:20 2005
@@ -143,6 +143,13 @@
 }
 
 CodeGenRegisterClass::CodeGenRegisterClass(Record *R) : TheDef(R) {
+  // Rename anonymous register classes.
+  if (R->getName().size() > 9 && R->getName()[9] == '.') {
+    static unsigned AnonCounter = 0;
+    R->setName("AnonRegClass_"+utostr(AnonCounter++));
+  } 
+  
+  Namespace = R->getValueAsString("Namespace");
   SpillSize = R->getValueAsInt("Size");
   SpillAlignment = R->getValueAsInt("Alignment");
 





From lattner at cs.uiuc.edu  Fri Aug 19 13:46:38 2005
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Fri, 19 Aug 2005 13:46:38 -0500
Subject: [llvm-commits] CVS: llvm/utils/TableGen/InstrInfoEmitter.cpp
	InstrInfoEmitter.h 
Message-ID: <200508191846.NAA08536@zion.cs.uiuc.edu>



Changes in directory llvm/utils/TableGen:

InstrInfoEmitter.cpp updated: 1.23 -> 1.24
InstrInfoEmitter.h updated: 1.9 -> 1.10
---
Log message:

Emit real operand info for instructions.  This currently works but is bad
in one way: the generated tables require dynamic initialization for the
register classes.  This will be fixed in a future patch.


---
Diffs of the changes:  (+45 -10)

 InstrInfoEmitter.cpp |   54 +++++++++++++++++++++++++++++++++++++++++----------
 InstrInfoEmitter.h   |    1 
 2 files changed, 45 insertions(+), 10 deletions(-)


Index: llvm/utils/TableGen/InstrInfoEmitter.cpp
diff -u llvm/utils/TableGen/InstrInfoEmitter.cpp:1.23 llvm/utils/TableGen/InstrInfoEmitter.cpp:1.24
--- llvm/utils/TableGen/InstrInfoEmitter.cpp:1.23	Fri Aug 19 11:57:28 2005
+++ llvm/utils/TableGen/InstrInfoEmitter.cpp	Fri Aug 19 13:46:26 2005
@@ -64,6 +64,24 @@
   OS << "0 };\n";
 }
 
+static std::vector<Record*> GetOperandInfo(const CodeGenInstruction &Inst) {
+  std::vector<Record*> Result;
+  if (Inst.hasVariableNumberOfOperands)
+    return Result;  // No info for variable operand instrs.
+
+  for (unsigned i = 0, e = Inst.OperandList.size(); i != e; ++i) {
+    if (Inst.OperandList[i].Rec->isSubClassOf("RegisterClass"))
+      Result.push_back(Inst.OperandList[i].Rec);
+    else {
+      // This might be a multiple operand thing.
+      // FIXME: Targets like X86 have registers in their multi-operand operands.
+      for (unsigned j = 0, e = Inst.OperandList[i].MINumOperands; j != e; ++j)
+        Result.push_back(0);
+    }
+  }
+  return Result;
+}
+
 
 // run - Emit the main instruction description records for the target...
 void InstrInfoEmitter::run(std::ostream &OS) {
@@ -103,15 +121,27 @@
     }
   }
 
+  std::map<std::vector<Record*>, unsigned> OperandInfosEmitted;
+  unsigned OperandListNum = 0;
+  OperandInfosEmitted[std::vector<Record*>()] = ++OperandListNum;
+  
   // Emit all of the operand info records.
   OS << "\n";
   for (CodeGenTarget::inst_iterator II = Target.inst_begin(),
        E = Target.inst_end(); II != E; ++II) {
-    const CodeGenInstruction &Inst = II->second;
-    if (!Inst.hasVariableNumberOfOperands) {
-      OS << "static const TargetOperandInfo " << Inst.TheDef->getName()
-         << "_Operands[] = {";
-      // FIXME: Emit operand info.
+    std::vector<Record*> OperandInfo = GetOperandInfo(II->second);
+    unsigned &N = OperandInfosEmitted[OperandInfo];
+    if (N == 0) {
+      N = ++OperandListNum;
+      OS << "static const TargetOperandInfo OperandInfo" << N << "[] = { ";
+      for (unsigned i = 0, e = OperandInfo.size(); i != e; ++i) {
+        if (Record *RC = OperandInfo[i]) {
+          // FIXME: BAD: REQUIRES RUNTIME INIT
+          OS << "{ " << getQualifiedName(RC) << "RegisterClass }, ";
+        } else {
+          OS << "{ 0 }, ";
+        }
+      }
       OS << "};\n";
     }
   }
@@ -120,13 +150,15 @@
   //
   OS << "\nstatic const TargetInstrDescriptor " << TargetName
      << "Insts[] = {\n";
-  emitRecord(Target.getPHIInstruction(), 0, InstrInfo, ListNumbers, OS);
+  emitRecord(Target.getPHIInstruction(), 0, InstrInfo, ListNumbers,
+             OperandInfosEmitted, OS);
 
   unsigned i = 0;
   for (CodeGenTarget::inst_iterator II = Target.inst_begin(),
          E = Target.inst_end(); II != E; ++II)
     if (II->second.TheDef != PHI)
-      emitRecord(II->second, ++i, InstrInfo, ListNumbers, OS);
+      emitRecord(II->second, ++i, InstrInfo, ListNumbers,
+                 OperandInfosEmitted, OS);
   OS << "};\n";
   OS << "} // End llvm namespace \n";
 }
@@ -134,6 +166,7 @@
 void InstrInfoEmitter::emitRecord(const CodeGenInstruction &Inst, unsigned Num,
                                   Record *InstrInfo,
                                   std::map<ListInit*, unsigned> &ListNumbers,
+                               std::map<std::vector<Record*>, unsigned> &OpInfo,
                                   std::ostream &OS) {
   int NumOperands;
   if (Inst.hasVariableNumberOfOperands)
@@ -193,10 +226,11 @@
     OS << "ImplicitList" << ListNumbers[LI] << ", ";
 
   // Emit the operand info.
-  if (NumOperands == -1)
-    OS << "0 ";
+  std::vector<Record*> OperandInfo = GetOperandInfo(Inst);
+  if (OperandInfo.empty())
+    OS << "0";
   else
-    OS << Inst.TheDef->getName() << "_Operands ";
+    OS << "OperandInfo" << OpInfo[OperandInfo];
   
   OS << " },  // Inst #" << Num << " = " << Inst.TheDef->getName() << "\n";
 }


Index: llvm/utils/TableGen/InstrInfoEmitter.h
diff -u llvm/utils/TableGen/InstrInfoEmitter.h:1.9 llvm/utils/TableGen/InstrInfoEmitter.h:1.10
--- llvm/utils/TableGen/InstrInfoEmitter.h:1.9	Thu Aug 18 16:36:47 2005
+++ llvm/utils/TableGen/InstrInfoEmitter.h	Fri Aug 19 13:46:26 2005
@@ -42,6 +42,7 @@
   void emitRecord(const CodeGenInstruction &Inst, unsigned Num,
                   Record *InstrInfo, 
                   std::map<ListInit*, unsigned> &ListNumbers,
+                  std::map<std::vector<Record*>, unsigned> &OpInfo,
                   std::ostream &OS);
   void emitShiftedValue(Record *R, StringInit *Val, IntInit *Shift,
                         std::ostream &OS);





From lattner at cs.uiuc.edu  Fri Aug 19 13:48:11 2005
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Fri, 19 Aug 2005 13:48:11 -0500
Subject: [llvm-commits] CVS: llvm/utils/TableGen/RegisterInfoEmitter.cpp 
Message-ID: <200508191848.NAA08571@zion.cs.uiuc.edu>



Changes in directory llvm/utils/TableGen:

RegisterInfoEmitter.cpp updated: 1.27 -> 1.28
---
Log message:

Refactor to use Target.getRegisterClasses consistently, which provides
anonymous regclass definition renaming.

Change the generated code to emit register classes as properly namespace
qualified entities like everything else.

expose the actual class definition as an object, though this isn't quite
usable yet.



---
Diffs of the changes:  (+40 -30)

 RegisterInfoEmitter.cpp |   70 +++++++++++++++++++++++++++---------------------
 1 files changed, 40 insertions(+), 30 deletions(-)


Index: llvm/utils/TableGen/RegisterInfoEmitter.cpp
diff -u llvm/utils/TableGen/RegisterInfoEmitter.cpp:1.27 llvm/utils/TableGen/RegisterInfoEmitter.cpp:1.28
--- llvm/utils/TableGen/RegisterInfoEmitter.cpp:1.27	Thu Apr 21 19:00:35 2005
+++ llvm/utils/TableGen/RegisterInfoEmitter.cpp	Fri Aug 19 13:47:59 2005
@@ -61,16 +61,18 @@
      << "  const unsigned* getCalleeSaveRegs() const;\n"
      << "};\n\n";
 
-  std::vector<Record*> RegisterClasses =
-    Records.getAllDerivedDefinitions("RegisterClass");
+  const std::vector<CodeGenRegisterClass> &RegisterClasses =
+    Target.getRegisterClasses();
 
-  OS << "namespace " << TargetName << " { // Register classes\n";
-  for (unsigned i = 0, e = RegisterClasses.size(); i != e; ++i) {
-    const std::string &Name = RegisterClasses[i]->getName();
-    if (Name.size() < 9 || Name[9] != '.')       // Ignore anonymous classes
-      OS << "  extern TargetRegisterClass *" << Name << "RegisterClass;\n";
+  if (!RegisterClasses.empty()) {
+    OS << "namespace " << RegisterClasses[0].Namespace
+       << " { // Register classes\n";
+    for (unsigned i = 0, e = RegisterClasses.size(); i != e; ++i) {
+      const std::string &Name = RegisterClasses[i].getName();
+      OS << "  extern TargetRegisterClass * const "<< Name <<"RegisterClass;\n";
+    }
+    OS << "} // end of namespace " << TargetName << "\n\n";
   }
-  OS << "} // end of namespace " << TargetName << "\n\n";
   OS << "} // End llvm namespace \n";
 }
 
@@ -90,7 +92,6 @@
     Target.getRegisterClasses();
 
   std::set<Record*> RegistersFound;
-  std::vector<std::string> RegClassNames;
 
   // Loop over all of the register classes... emitting each one.
   OS << "namespace {     // Register classes...\n";
@@ -102,15 +103,10 @@
   for (unsigned rc = 0, e = RegisterClasses.size(); rc != e; ++rc) {
     const CodeGenRegisterClass &RC = RegisterClasses[rc];
 
-    std::string Name = RC.getName();
-    if (Name.size() > 9 && Name[9] == '.') {
-      static unsigned AnonCounter = 0;
-      Name = "AnonRegClass_"+utostr(AnonCounter++);
-    }
-
-    RegClassNames.push_back(Name);
-
-    // Emit the register list now...
+    // Give the register class a legal C name if it's anonymous.
+    std::string Name = RC.TheDef->getName();
+  
+    // Emit the register list now.
     OS << "  // " << Name << " Register Class...\n  const unsigned " << Name
        << "[] = {\n    ";
     for (unsigned i = 0, e = RC.Elements.size(); i != e; ++i) {
@@ -130,12 +126,25 @@
        << "    " << Name << "Class() : TargetRegisterClass("
        << RC.SpillSize/8 << ", " << RC.SpillAlignment/8 << ", " << Name << ", "
        << Name << " + " << RC.Elements.size() << ") {}\n"
-       << RC.MethodDefinitions << "  } " << Name << "Instance;\n\n";
+       << RC.MethodDefinitions << "  };\n\n";
+  }
+  OS << "}  // end anonymous namespace\n\n";
+  
+  // Now that all of the structs have been emitted, emit the instances.
+  if (!RegisterClasses.empty()) {
+    OS << "namespace " << RegisterClasses[0].Namespace
+       << " {   // Register class instances\n";
+    for (unsigned i = 0, e = RegisterClasses.size(); i != e; ++i)
+      OS << "  " << RegisterClasses[i].getName()  << "Class\t"
+         << RegisterClasses[i].getName() << "RegClassInstance;\n";
+    OS << "}\n";
   }
 
+  OS << "\nnamespace {\n";
   OS << "  const TargetRegisterClass* const RegisterClasses[] = {\n";
-  for (unsigned i = 0, e = RegClassNames.size(); i != e; ++i)
-    OS << "    &" << RegClassNames[i] << "Instance,\n";
+  for (unsigned i = 0, e = RegisterClasses.size(); i != e; ++i)
+    OS << "    &" << getQualifiedName(RegisterClasses[i].TheDef)
+       << "RegClassInstance,\n";
   OS << "  };\n";
 
   // Emit register class aliases...
@@ -228,15 +237,16 @@
   OS << "  };\n";      // End of register descriptors...
   OS << "}\n\n";       // End of anonymous namespace...
 
-  OS << "namespace " << Target.getName() << " { // Register classes\n";
-  for (unsigned i = 0, e = RegisterClasses.size(); i != e; ++i) {
-    const std::string &Name = RegisterClasses[i].getName();
-    if (Name.size() < 9 || Name[9] != '.')    // Ignore anonymous classes
-      OS << "  TargetRegisterClass *" << Name << "RegisterClass = &"
-         << Name << "Instance;\n";
+  if (!RegisterClasses.empty()) {
+    OS << "namespace " << RegisterClasses[0].Namespace
+       << " { // Register classes\n";
+    for (unsigned i = 0, e = RegisterClasses.size(); i != e; ++i) {
+      OS << "  TargetRegisterClass * const " << RegisterClasses[i].getName()
+         << "RegisterClass = &" << getQualifiedName(RegisterClasses[i].TheDef)
+         << "RegClassInstance;\n";
+    }
+    OS << "} // end of namespace " << RegisterClasses[0].Namespace << "\n\n";
   }
-  OS << "} // end of namespace " << Target.getName() << "\n\n";
-
 
 
   std::string ClassName = Target.getName() + "GenRegisterInfo";
@@ -245,7 +255,7 @@
   OS << ClassName << "::" << ClassName
      << "(int CallFrameSetupOpcode, int CallFrameDestroyOpcode)\n"
      << "  : MRegisterInfo(RegisterDescriptors, " << Registers.size()+1
-     << ", RegisterClasses, RegisterClasses+" << RegClassNames.size() << ",\n "
+     << ", RegisterClasses, RegisterClasses+" << RegisterClasses.size() <<",\n "
      << "                 CallFrameSetupOpcode, CallFrameDestroyOpcode) {}\n\n";
 
   // Emit the getCalleeSaveRegs method...





From lattner at cs.uiuc.edu  Fri Aug 19 13:48:59 2005
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Fri, 19 Aug 2005 13:48:59 -0500
Subject: [llvm-commits] CVS: llvm/lib/Target/Target.td 
Message-ID: <200508191848.NAA08628@zion.cs.uiuc.edu>



Changes in directory llvm/lib/Target:

Target.td updated: 1.44 -> 1.45
---
Log message:

Require that targets specify a namespace for their register classes.


---
Diffs of the changes:  (+4 -1)

 Target.td |    5 ++++-
 1 files changed, 4 insertions(+), 1 deletion(-)


Index: llvm/lib/Target/Target.td
diff -u llvm/lib/Target/Target.td:1.44 llvm/lib/Target/Target.td:1.45
--- llvm/lib/Target/Target.td:1.44	Thu Aug 18 18:17:07 2005
+++ llvm/lib/Target/Target.td	Fri Aug 19 13:48:48 2005
@@ -79,7 +79,10 @@
 // register classes.  This also defines the default allocation order of
 // registers by register allocators.
 //
-class RegisterClass<ValueType regType, int alignment, list<Register> regList> {
+class RegisterClass<string namespace, ValueType regType, int alignment,
+                    list<Register> regList> {
+  string Namespace = namespace;
+
   // RegType - Specify the ValueType of the registers in this register class.
   // Note that all registers in a register class must have the same ValueType.
   //





From lattner at cs.uiuc.edu  Fri Aug 19 13:49:34 2005
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Fri, 19 Aug 2005 13:49:34 -0500
Subject: [llvm-commits] CVS: llvm/lib/Target/SparcV8/SparcV8RegisterInfo.td 
Message-ID: <200508191849.NAA08685@zion.cs.uiuc.edu>



Changes in directory llvm/lib/Target/SparcV8:

SparcV8RegisterInfo.td updated: 1.20 -> 1.21
---
Log message:

put reg classes in namespaces


---
Diffs of the changes:  (+3 -3)

 SparcV8RegisterInfo.td |    6 +++---
 1 files changed, 3 insertions(+), 3 deletions(-)


Index: llvm/lib/Target/SparcV8/SparcV8RegisterInfo.td
diff -u llvm/lib/Target/SparcV8/SparcV8RegisterInfo.td:1.20 llvm/lib/Target/SparcV8/SparcV8RegisterInfo.td:1.21
--- llvm/lib/Target/SparcV8/SparcV8RegisterInfo.td:1.20	Thu Dec  9 22:46:30 2004
+++ llvm/lib/Target/SparcV8/SparcV8RegisterInfo.td	Fri Aug 19 13:49:22 2005
@@ -84,7 +84,7 @@
 // FIXME: the register order should be defined in terms of the preferred
 // allocation order...
 //
-def IntRegs : RegisterClass<i32, 32, [L0, L1, L2, L3, L4, L5, L6, L7,
+def IntRegs : RegisterClass<"V8", i32, 32, [L0, L1, L2, L3, L4, L5, L6, L7,
                                      I0, I1, I2, I3, I4, I5,
                                      G1,
                                      O0, O1, O2, O3, O4, O5, O7,
@@ -104,9 +104,9 @@
   }];
 }
 
-def FPRegs : RegisterClass<f32, 32, [F0, F1, F2, F3, F4, F5, F6, F7, F8,
+def FPRegs : RegisterClass<"V8", f32, 32, [F0, F1, F2, F3, F4, F5, F6, F7, F8,
   F9, F10, F11, F12, F13, F14, F15, F16, F17, F18, F19, F20, F21, F22,
   F23, F24, F25, F26, F27, F28, F29, F30, F31]>;
 
-def DFPRegs : RegisterClass<f64, 64, [D0, D1, D2, D3, D4, D5, D6, D7,
+def DFPRegs : RegisterClass<"V8", f64, 64, [D0, D1, D2, D3, D4, D5, D6, D7,
   D8, D9, D10, D11, D12, D13, D14, D15]>;





From lattner at cs.uiuc.edu  Fri Aug 19 13:50:22 2005
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Fri, 19 Aug 2005 13:50:22 -0500
Subject: [llvm-commits] CVS: llvm/lib/Target/SparcV8/SparcV8RegisterInfo.cpp
Message-ID: <200508191850.NAA08726@zion.cs.uiuc.edu>



Changes in directory llvm/lib/Target/SparcV8:

SparcV8RegisterInfo.cpp updated: 1.25 -> 1.26
---
Log message:

Fix code that assumes the register info will be dumped into a target
namespace instead of the reg class namespace.  Update getRegClassForType()
to use modified names due to tblgen change.


---
Diffs of the changes:  (+18 -18)

 SparcV8RegisterInfo.cpp |   36 ++++++++++++++++++------------------
 1 files changed, 18 insertions(+), 18 deletions(-)


Index: llvm/lib/Target/SparcV8/SparcV8RegisterInfo.cpp
diff -u llvm/lib/Target/SparcV8/SparcV8RegisterInfo.cpp:1.25 llvm/lib/Target/SparcV8/SparcV8RegisterInfo.cpp:1.26
--- llvm/lib/Target/SparcV8/SparcV8RegisterInfo.cpp:1.25	Thu Apr 21 18:21:30 2005
+++ llvm/lib/Target/SparcV8/SparcV8RegisterInfo.cpp	Fri Aug 19 13:50:11 2005
@@ -26,12 +26,12 @@
                            V8::ADJCALLSTACKUP) {}
 
 static const TargetRegisterClass *getClass(unsigned SrcReg) {
-  if (SparcV8::IntRegsRegisterClass->contains(SrcReg))
-    return SparcV8::IntRegsRegisterClass;
-  else if (SparcV8::FPRegsRegisterClass->contains(SrcReg))
-    return SparcV8::FPRegsRegisterClass;
-  else if (SparcV8::DFPRegsRegisterClass->contains(SrcReg))
-    return SparcV8::DFPRegsRegisterClass;
+  if (V8::IntRegsRegisterClass->contains(SrcReg))
+    return V8::IntRegsRegisterClass;
+  else if (V8::FPRegsRegisterClass->contains(SrcReg))
+    return V8::FPRegsRegisterClass;
+  else if (V8::DFPRegsRegisterClass->contains(SrcReg))
+    return V8::DFPRegsRegisterClass;
   else {
     std::cerr << "Error: register of unknown class found: " << SrcReg << "\n";
     abort ();
@@ -44,13 +44,13 @@
   const TargetRegisterClass *RC = getClass(SrcReg);
 
   // On the order of operands here: think "[FrameIdx + 0] = SrcReg".
-  if (RC == SparcV8::IntRegsRegisterClass)
+  if (RC == V8::IntRegsRegisterClass)
     BuildMI (MBB, I, V8::ST, 3).addFrameIndex (FrameIdx).addSImm (0)
       .addReg (SrcReg);
-  else if (RC == SparcV8::FPRegsRegisterClass)
+  else if (RC == V8::FPRegsRegisterClass)
     BuildMI (MBB, I, V8::STFri, 3).addFrameIndex (FrameIdx).addSImm (0)
       .addReg (SrcReg);
-  else if (RC == SparcV8::DFPRegsRegisterClass)
+  else if (RC == V8::DFPRegsRegisterClass)
     BuildMI (MBB, I, V8::STDFri, 3).addFrameIndex (FrameIdx).addSImm (0)
       .addReg (SrcReg);
   else
@@ -61,12 +61,12 @@
 loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
                      unsigned DestReg, int FrameIdx) const {
   const TargetRegisterClass *RC = getClass(DestReg);
-  if (RC == SparcV8::IntRegsRegisterClass)
+  if (RC == V8::IntRegsRegisterClass)
     BuildMI (MBB, I, V8::LD, 2, DestReg).addFrameIndex (FrameIdx).addSImm (0);
-  else if (RC == SparcV8::FPRegsRegisterClass)
+  else if (RC == V8::FPRegsRegisterClass)
     BuildMI (MBB, I, V8::LDFri, 2, DestReg).addFrameIndex (FrameIdx)
       .addSImm (0);
-  else if (RC == SparcV8::DFPRegsRegisterClass)
+  else if (RC == V8::DFPRegsRegisterClass)
     BuildMI (MBB, I, V8::LDDFri, 2, DestReg).addFrameIndex (FrameIdx)
       .addSImm (0);
   else
@@ -77,11 +77,11 @@
                                        MachineBasicBlock::iterator I,
                                        unsigned DestReg, unsigned SrcReg,
                                        const TargetRegisterClass *RC) const {
-  if (RC == SparcV8::IntRegsRegisterClass)
+  if (RC == V8::IntRegsRegisterClass)
     BuildMI (MBB, I, V8::ORrr, 2, DestReg).addReg (V8::G0).addReg (SrcReg);
-  else if (RC == SparcV8::FPRegsRegisterClass)
+  else if (RC == V8::FPRegsRegisterClass)
     BuildMI (MBB, I, V8::FMOVS, 1, DestReg).addReg (SrcReg);
-  else if (RC == SparcV8::DFPRegsRegisterClass)
+  else if (RC == V8::DFPRegsRegisterClass)
     BuildMI (MBB, I, V8::FpMOVD, 1, DestReg).addReg (SrcReg);
   else
     assert (0 && "Can't copy this register");
@@ -158,8 +158,8 @@
 const TargetRegisterClass*
 SparcV8RegisterInfo::getRegClassForType(const Type* Ty) const {
   switch (Ty->getTypeID()) {
-  case Type::FloatTyID:  return &FPRegsInstance;
-  case Type::DoubleTyID: return &DFPRegsInstance;
+  case Type::FloatTyID:  return V8::FPRegsRegisterClass;
+  case Type::DoubleTyID: return V8::DFPRegsRegisterClass;
   case Type::LongTyID:
   case Type::ULongTyID:  assert(0 && "Long values do not fit in registers!");
   default:               assert(0 && "Invalid type to getClass!");
@@ -170,7 +170,7 @@
   case Type::UShortTyID:
   case Type::IntTyID:
   case Type::UIntTyID:
-  case Type::PointerTyID: return &IntRegsInstance;
+  case Type::PointerTyID: return V8::IntRegsRegisterClass;
   }
 }
 





From lattner at cs.uiuc.edu  Fri Aug 19 13:50:58 2005
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Fri, 19 Aug 2005 13:50:58 -0500
Subject: [llvm-commits] CVS: llvm/lib/Target/IA64/IA64RegisterInfo.td 
Message-ID: <200508191850.NAA08788@zion.cs.uiuc.edu>



Changes in directory llvm/lib/Target/IA64:

IA64RegisterInfo.td updated: 1.6 -> 1.7
---
Log message:

Put register classes in namespaces


---
Diffs of the changes:  (+3 -3)

 IA64RegisterInfo.td |    6 +++---
 1 files changed, 3 insertions(+), 3 deletions(-)


Index: llvm/lib/Target/IA64/IA64RegisterInfo.td
diff -u llvm/lib/Target/IA64/IA64RegisterInfo.td:1.6 llvm/lib/Target/IA64/IA64RegisterInfo.td:1.7
--- llvm/lib/Target/IA64/IA64RegisterInfo.td:1.6	Tue Apr 12 13:42:59 2005
+++ llvm/lib/Target/IA64/IA64RegisterInfo.td	Fri Aug 19 13:50:46 2005
@@ -233,7 +233,7 @@
 // FIXME/XXX  we also reserve r22 for calculating addresses
 // in IA64RegisterInfo.cpp
 
-def GR : RegisterClass<i64, 64, 
+def GR : RegisterClass<"IA64", i64, 64, 
        [
        
 //FIXME!: for readability, we don't want the out registers to be the first
@@ -279,7 +279,7 @@
 
 // these are the scratch (+stacked) FP registers
 // ZERO (F0) and ONE (F1) are not here
-def FP : RegisterClass<f64, 64, 
+def FP : RegisterClass<"IA64", f64, 64, 
        [F6, F7, 
 	F8, F9, F10, F11, F12, F13, F14, F15, 
 	F32, F33, F34, F35, F36, F37, F38, F39, 
@@ -296,7 +296,7 @@
 	F120, F121, F122, F123, F124, F125, F126, F127]>;
 
 // these are the predicate registers, p0 (1/TRUE) is not here
-def PR : RegisterClass<i1, 64, 
+def PR : RegisterClass<"IA64", i1, 64, 
 
 // for now, let's be wimps and only have the scratch predicate regs
  [p6, p7, p8, p9, p10, p11, p12, p13, p14, p15]> {





From lattner at cs.uiuc.edu  Fri Aug 19 13:50:58 2005
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Fri, 19 Aug 2005 13:50:58 -0500
Subject: [llvm-commits] CVS: llvm/lib/Target/Alpha/AlphaRegisterInfo.td 
Message-ID: <200508191850.NAA08792@zion.cs.uiuc.edu>



Changes in directory llvm/lib/Target/Alpha:

AlphaRegisterInfo.td updated: 1.11 -> 1.12
---
Log message:

Put register classes in namespaces


---
Diffs of the changes:  (+2 -2)

 AlphaRegisterInfo.td |    4 ++--
 1 files changed, 2 insertions(+), 2 deletions(-)


Index: llvm/lib/Target/Alpha/AlphaRegisterInfo.td
diff -u llvm/lib/Target/Alpha/AlphaRegisterInfo.td:1.11 llvm/lib/Target/Alpha/AlphaRegisterInfo.td:1.12
--- llvm/lib/Target/Alpha/AlphaRegisterInfo.td:1.11	Tue Jun 28 19:31:08 2005
+++ llvm/lib/Target/Alpha/AlphaRegisterInfo.td	Fri Aug 19 13:50:46 2005
@@ -79,7 +79,7 @@
 
 /// Register classes
 // Don't allocate 15, 28, 30, 31
-def GPRC : RegisterClass<i64, 64,
+def GPRC : RegisterClass<"Alpha", i64, 64,
      // Volatile
      [R0, R1, R2, R3, R4, R5, R6, R7, R8, R16, R17, R18, R19, R20, R21, R22,
       R23, R24, R25, 
@@ -93,7 +93,7 @@
 
 // Don't allocate 15, 29, 30, 31
 // Allocation volatiles only for now
-def FPRC : RegisterClass<f64, 64, [F0, F1, 
+def FPRC : RegisterClass<"Alpha", f64, 64, [F0, F1, 
         F10, F11, F12, F13, F14, F15, F16, F17, F18, F19,
         F20, F21, F22, F23, F24, F25, F26, F27, F28, F29, F30,
         // Saved:





From lattner at cs.uiuc.edu  Fri Aug 19 13:52:09 2005
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Fri, 19 Aug 2005 13:52:09 -0500
Subject: [llvm-commits] CVS: llvm/lib/Target/X86/X86RegisterInfo.td 
Message-ID: <200508191852.NAA08909@zion.cs.uiuc.edu>



Changes in directory llvm/lib/Target/X86:

X86RegisterInfo.td updated: 1.19 -> 1.20
---
Log message:

Put register classes into namespaces


---
Diffs of the changes:  (+8 -7)

 X86RegisterInfo.td |   15 ++++++++-------
 1 files changed, 8 insertions(+), 7 deletions(-)


Index: llvm/lib/Target/X86/X86RegisterInfo.td
diff -u llvm/lib/Target/X86/X86RegisterInfo.td:1.19 llvm/lib/Target/X86/X86RegisterInfo.td:1.20
--- llvm/lib/Target/X86/X86RegisterInfo.td:1.19	Wed Jul  6 13:59:04 2005
+++ llvm/lib/Target/X86/X86RegisterInfo.td	Fri Aug 19 13:51:57 2005
@@ -72,9 +72,9 @@
 // dependences between upper and lower parts of the register.  BL and BH are
 // last because they are call clobbered. Both Athlon and P4 chips suffer this
 // issue.
-def R8  : RegisterClass<i8,  8, [AL, CL, DL, AH, CH, DH, BL, BH]>;
+def R8  : RegisterClass<"X86", i8,  8, [AL, CL, DL, AH, CH, DH, BL, BH]>;
 
-def R16 : RegisterClass<i16, 16, [AX, CX, DX, SI, DI, BX, BP, SP]> {
+def R16 : RegisterClass<"X86", i16, 16, [AX, CX, DX, SI, DI, BX, BP, SP]> {
   let Methods = [{
     iterator allocation_order_end(MachineFunction &MF) const {
       if (hasFP(MF))     // Does the function dedicate EBP to being a frame ptr?
@@ -85,7 +85,7 @@
   }];
 }
 
-def R32 : RegisterClass<i32, 32, [EAX, ECX, EDX, ESI, EDI, EBX, EBP, ESP]> {
+def R32 : RegisterClass<"X86", i32, 32, [EAX, ECX, EDX, ESI, EDI, EBX, EBP, ESP]> {
   let Methods = [{
     iterator allocation_order_end(MachineFunction &MF) const {
       if (hasFP(MF))     // Does the function dedicate EBP to being a frame ptr?
@@ -99,8 +99,8 @@
 // FIXME: These registers can contain both integer and fp values.  We should
 // figure out the right way to deal with that.  For now, since they'll be used
 // for scalar FP, they are being declared f64
-def RXMM : RegisterClass<f64, 32, [XMM0, XMM1, XMM2, XMM3, 
-                                   XMM4, XMM5, XMM6, XMM7]>;
+def RXMM : RegisterClass<"X86", f64, 32,
+                         [XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7]>;
 
 // FIXME: This sets up the floating point register files as though they are f64
 // values, though they really are f80 values.  This will cause us to spill
@@ -108,12 +108,13 @@
 // faster on common hardware.  In reality, this should be controlled by a
 // command line option or something.
 
-def RFP : RegisterClass<f64, 32, [FP0, FP1, FP2, FP3, FP4, FP5, FP6]>;
+def RFP : RegisterClass<"X86", f64, 32, [FP0, FP1, FP2, FP3, FP4, FP5, FP6]>;
 
 // Floating point stack registers (these are not allocatable by the
 // register allocator - the floating point stackifier is responsible
 // for transforming FPn allocations to STn registers)
-def RST : RegisterClass<f64, 32, [ST0, ST1, ST2, ST3, ST4, ST5, ST6, ST7]> {
+def RST : RegisterClass<"X86", f64, 32,
+                        [ST0, ST1, ST2, ST3, ST4, ST5, ST6, ST7]> {
   let Methods = [{
     iterator allocation_order_end(MachineFunction &MF) const {
       return begin();





From lattner at cs.uiuc.edu  Fri Aug 19 13:52:09 2005
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Fri, 19 Aug 2005 13:52:09 -0500
Subject: [llvm-commits] CVS: llvm/lib/Target/SparcV9/SparcV9RegisterInfo.td 
Message-ID: <200508191852.NAA08913@zion.cs.uiuc.edu>



Changes in directory llvm/lib/Target/SparcV9:

SparcV9RegisterInfo.td updated: 1.4 -> 1.5
---
Log message:

Put register classes into namespaces


---
Diffs of the changes:  (+1 -1)

 SparcV9RegisterInfo.td |    2 +-
 1 files changed, 1 insertion(+), 1 deletion(-)


Index: llvm/lib/Target/SparcV9/SparcV9RegisterInfo.td
diff -u llvm/lib/Target/SparcV9/SparcV9RegisterInfo.td:1.4 llvm/lib/Target/SparcV9/SparcV9RegisterInfo.td:1.5
--- llvm/lib/Target/SparcV9/SparcV9RegisterInfo.td:1.4	Mon Sep 13 23:16:49 2004
+++ llvm/lib/Target/SparcV9/SparcV9RegisterInfo.td	Fri Aug 19 13:51:57 2005
@@ -43,7 +43,7 @@
 // FIXME: the register order should be defined in terms of the preferred
 // allocation order...
 //
-def IntRegs : RegisterClass<i64, 64, [G0, G1, G2, G3, G4, G5, G6, G7,
+def IntRegs : RegisterClass<"V9", i64, 64, [G0, G1, G2, G3, G4, G5, G6, G7,
                                      O0, O1, O2, O3, O4, O5, O6, O7,
                                      L0, L1, L2, L3, L4, L5, L6, L7,
                                      I0, I1, I2, I3, I4, I5, I6, I7]>;





From lattner at cs.uiuc.edu  Fri Aug 19 13:53:06 2005
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Fri, 19 Aug 2005 13:53:06 -0500
Subject: [llvm-commits] CVS: llvm/lib/Target/PowerPC/PPC32RegisterInfo.td
	PPC64RegisterInfo.td 
Message-ID: <200508191853.NAA09044@zion.cs.uiuc.edu>



Changes in directory llvm/lib/Target/PowerPC:

PPC32RegisterInfo.td updated: 1.5 -> 1.6
PPC64RegisterInfo.td updated: 1.4 -> 1.5
---
Log message:

Put reg classes into namespaces


---
Diffs of the changes:  (+6 -6)

 PPC32RegisterInfo.td |    6 +++---
 PPC64RegisterInfo.td |    6 +++---
 2 files changed, 6 insertions(+), 6 deletions(-)


Index: llvm/lib/Target/PowerPC/PPC32RegisterInfo.td
diff -u llvm/lib/Target/PowerPC/PPC32RegisterInfo.td:1.5 llvm/lib/Target/PowerPC/PPC32RegisterInfo.td:1.6
--- llvm/lib/Target/PowerPC/PPC32RegisterInfo.td:1.5	Thu Aug  4 15:49:48 2005
+++ llvm/lib/Target/PowerPC/PPC32RegisterInfo.td	Fri Aug 19 13:52:55 2005
@@ -15,7 +15,7 @@
 /// Register classes
 // Allocate volatiles first
 // then nonvolatiles in reverse order since stmw/lmw save from rN to r31
-def GPRC : RegisterClass<i32, 32,
+def GPRC : RegisterClass<"PPC32", i32, 32,
      [R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12,
       R30, R29, R28, R27, R26, R25, R24, R23, R22, R21, R20, R19, R18, R17,
       R16, R15, R14, R13, R31, R0, R1, LR]>
@@ -33,8 +33,8 @@
   }];
 }
 
-def FPRC : RegisterClass<f64, 64, [F0, F1, F2, F3, F4, F5, F6, F7,
+def FPRC : RegisterClass<"PPC32", f64, 64, [F0, F1, F2, F3, F4, F5, F6, F7,
   F8, F9, F10, F11, F12, F13, F14, F15, F16, F17, F18, F19, F20, F21,
   F22, F23, F24, F25, F26, F27, F28, F29, F30, F31]>;
 
-def CRRC : RegisterClass<i32, 32, [CR0, CR1, CR5, CR6, CR7, CR2, CR3, CR4]>;
+def CRRC : RegisterClass<"PPC32", i32, 32, [CR0, CR1, CR5, CR6, CR7, CR2, CR3, CR4]>;


Index: llvm/lib/Target/PowerPC/PPC64RegisterInfo.td
diff -u llvm/lib/Target/PowerPC/PPC64RegisterInfo.td:1.4 llvm/lib/Target/PowerPC/PPC64RegisterInfo.td:1.5
--- llvm/lib/Target/PowerPC/PPC64RegisterInfo.td:1.4	Thu Aug  4 15:49:48 2005
+++ llvm/lib/Target/PowerPC/PPC64RegisterInfo.td	Fri Aug 19 13:52:55 2005
@@ -15,7 +15,7 @@
 /// Register classes
 // Allocate volatiles first
 // then nonvolatiles in reverse order since stmw/lmw save from rN to r31
-def GPRC : RegisterClass<i64, 64,
+def GPRC : RegisterClass<"PPC64", i64, 64,
      [R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12,
       R30, R29, R28, R27, R26, R25, R24, R23, R22, R21, R20, R19, R18, R17,
       R16, R15, R14, R13, R31, R0, R1, LR]>
@@ -33,8 +33,8 @@
   }];
 }
 
-def FPRC : RegisterClass<f64, 64, [F0, F1, F2, F3, F4, F5, F6, F7,
+def FPRC : RegisterClass<"PPC64", f64, 64, [F0, F1, F2, F3, F4, F5, F6, F7,
   F8, F9, F10, F11, F12, F13, F14, F15, F16, F17, F18, F19, F20, F21,
   F22, F23, F24, F25, F26, F27, F28, F29, F30, F31]>;
 
-def CRRC : RegisterClass<i32, 32, [CR0, CR1, CR2, CR3, CR4, CR5, CR6, CR7]>;
+def CRRC : RegisterClass<"PPC64", i32, 32, [CR0, CR1, CR2, CR3, CR4, CR5, CR6, CR7]>;





From lattner at cs.uiuc.edu  Fri Aug 19 13:53:54 2005
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Fri, 19 Aug 2005 13:53:54 -0500
Subject: [llvm-commits] 
	CVS: llvm/lib/Target/Skeleton/SkeletonRegisterInfo.td
Message-ID: <200508191853.NAA09102@zion.cs.uiuc.edu>



Changes in directory llvm/lib/Target/Skeleton:

SkeletonRegisterInfo.td updated: 1.3 -> 1.4
---
Log message:

put reg classes into namespace


---
Diffs of the changes:  (+2 -2)

 SkeletonRegisterInfo.td |    4 ++--
 1 files changed, 2 insertions(+), 2 deletions(-)


Index: llvm/lib/Target/Skeleton/SkeletonRegisterInfo.td
diff -u llvm/lib/Target/Skeleton/SkeletonRegisterInfo.td:1.3 llvm/lib/Target/Skeleton/SkeletonRegisterInfo.td:1.4
--- llvm/lib/Target/Skeleton/SkeletonRegisterInfo.td:1.3	Mon Sep 13 23:16:43 2004
+++ llvm/lib/Target/Skeleton/SkeletonRegisterInfo.td	Fri Aug 19 13:53:43 2005
@@ -96,10 +96,10 @@
 
 /// Register classes: one for floats and another for non-floats.
 ///
-def GPRC : RegisterClass<i32, 32, [R0, R1, R2, R3, R4, R5, R6, R7,
+def GPRC : RegisterClass<"Skeleton", i32, 32, [R0, R1, R2, R3, R4, R5, R6, R7,
   R8, R9, R10, R11, R12, R13, R14, R15, R16, R17, R18, R19, R20, R21,
   R22, R23, R24, R25, R26, R27, R28, R29, R30, R31]>;
-def FPRC : RegisterClass<f64, 64, [F0, F1, F2, F3, F4, F5, F6, F7,
+def FPRC : RegisterClass<"Skeleton", f64, 64, [F0, F1, F2, F3, F4, F5, F6, F7,
   F8, F9, F10, F11, F12, F13, F14, F15, F16, F17, F18, F19, F20, F21,
   F22, F23, F24, F25, F26, F27, F28, F29, F30, F31]>;
 





From lattner at cs.uiuc.edu  Fri Aug 19 14:13:03 2005
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Fri, 19 Aug 2005 14:13:03 -0500
Subject: [llvm-commits] CVS: llvm/utils/TableGen/CodeGenRegisters.h
	CodeGenTarget.cpp RegisterInfoEmitter.cpp 
Message-ID: <200508191913.OAA09455@zion.cs.uiuc.edu>



Changes in directory llvm/utils/TableGen:

CodeGenRegisters.h updated: 1.6 -> 1.7
CodeGenTarget.cpp updated: 1.31 -> 1.32
RegisterInfoEmitter.cpp updated: 1.28 -> 1.29
---
Log message:

Split register class "Methods" into MethodProtos and MethodBodies


---
Diffs of the changes:  (+13 -6)

 CodeGenRegisters.h      |    2 +-
 CodeGenTarget.cpp       |   14 ++++++++++----
 RegisterInfoEmitter.cpp |    3 ++-
 3 files changed, 13 insertions(+), 6 deletions(-)


Index: llvm/utils/TableGen/CodeGenRegisters.h
diff -u llvm/utils/TableGen/CodeGenRegisters.h:1.6 llvm/utils/TableGen/CodeGenRegisters.h:1.7
--- llvm/utils/TableGen/CodeGenRegisters.h:1.6	Fri Aug 19 13:45:20 2005
+++ llvm/utils/TableGen/CodeGenRegisters.h	Fri Aug 19 14:12:51 2005
@@ -36,7 +36,7 @@
     std::vector<Record*> Elements;
     unsigned SpillSize;
     unsigned SpillAlignment;
-    std::string MethodDefinitions;
+    std::string MethodProtos, MethodBodies;
 
     const std::string &getName() const;
 


Index: llvm/utils/TableGen/CodeGenTarget.cpp
diff -u llvm/utils/TableGen/CodeGenTarget.cpp:1.31 llvm/utils/TableGen/CodeGenTarget.cpp:1.32
--- llvm/utils/TableGen/CodeGenTarget.cpp:1.31	Fri Aug 19 13:45:20 2005
+++ llvm/utils/TableGen/CodeGenTarget.cpp	Fri Aug 19 14:12:51 2005
@@ -153,12 +153,18 @@
   SpillSize = R->getValueAsInt("Size");
   SpillAlignment = R->getValueAsInt("Alignment");
 
-  if (CodeInit *CI = dynamic_cast<CodeInit*>(R->getValueInit("Methods")))
-    MethodDefinitions = CI->getValue();
+  if (CodeInit *CI = dynamic_cast<CodeInit*>(R->getValueInit("MethodBodies")))
+    MethodBodies = CI->getValue();
   else
-    throw "Expected 'code' fragment for 'Methods' value in register class '"+
-          getName() + "'!";
+    throw "Expected 'code' fragment for 'MethodBodies' value in register "
+          "class '" + getName() + "'!";
 
+  if (CodeInit *CI = dynamic_cast<CodeInit*>(R->getValueInit("MethodProtos")))
+    MethodProtos = CI->getValue();
+  else
+    throw "Expected 'code' fragment for 'MethodProtos' value in register "
+      "class '" + getName() + "'!";
+  
   ListInit *RegList = R->getValueAsListInit("MemberList");
   for (unsigned i = 0, e = RegList->getSize(); i != e; ++i) {
     DefInit *RegDef = dynamic_cast<DefInit*>(RegList->getElement(i));


Index: llvm/utils/TableGen/RegisterInfoEmitter.cpp
diff -u llvm/utils/TableGen/RegisterInfoEmitter.cpp:1.28 llvm/utils/TableGen/RegisterInfoEmitter.cpp:1.29
--- llvm/utils/TableGen/RegisterInfoEmitter.cpp:1.28	Fri Aug 19 13:47:59 2005
+++ llvm/utils/TableGen/RegisterInfoEmitter.cpp	Fri Aug 19 14:12:51 2005
@@ -126,7 +126,8 @@
        << "    " << Name << "Class() : TargetRegisterClass("
        << RC.SpillSize/8 << ", " << RC.SpillAlignment/8 << ", " << Name << ", "
        << Name << " + " << RC.Elements.size() << ") {}\n"
-       << RC.MethodDefinitions << "  };\n\n";
+       << RC.MethodProtos << "  };\n";
+    OS << RC.MethodBodies << "\n";
   }
   OS << "}  // end anonymous namespace\n\n";
   





From lattner at cs.uiuc.edu  Fri Aug 19 14:13:33 2005
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Fri, 19 Aug 2005 14:13:33 -0500
Subject: [llvm-commits] CVS: llvm/lib/Target/X86/X86RegisterInfo.td 
Message-ID: <200508191913.OAA09515@zion.cs.uiuc.edu>



Changes in directory llvm/lib/Target/X86:

X86RegisterInfo.td updated: 1.20 -> 1.21
---
Log message:

Split RegisterClass 'Methods' into MethodProtos and MethodBodies


---
Diffs of the changes:  (+18 -6)

 X86RegisterInfo.td |   24 ++++++++++++++++++------
 1 files changed, 18 insertions(+), 6 deletions(-)


Index: llvm/lib/Target/X86/X86RegisterInfo.td
diff -u llvm/lib/Target/X86/X86RegisterInfo.td:1.20 llvm/lib/Target/X86/X86RegisterInfo.td:1.21
--- llvm/lib/Target/X86/X86RegisterInfo.td:1.20	Fri Aug 19 13:51:57 2005
+++ llvm/lib/Target/X86/X86RegisterInfo.td	Fri Aug 19 14:13:20 2005
@@ -75,8 +75,12 @@
 def R8  : RegisterClass<"X86", i8,  8, [AL, CL, DL, AH, CH, DH, BL, BH]>;
 
 def R16 : RegisterClass<"X86", i16, 16, [AX, CX, DX, SI, DI, BX, BP, SP]> {
-  let Methods = [{
-    iterator allocation_order_end(MachineFunction &MF) const {
+  let MethodProtos = [{
+    iterator allocation_order_end(MachineFunction &MF) const;
+  }];
+  let MethodBodies = [{
+    R16Class::iterator
+    R16Class::allocation_order_end(MachineFunction &MF) const {
       if (hasFP(MF))     // Does the function dedicate EBP to being a frame ptr?
         return end()-2;  // If so, don't allocate SP or BP
       else
@@ -86,8 +90,12 @@
 }
 
 def R32 : RegisterClass<"X86", i32, 32, [EAX, ECX, EDX, ESI, EDI, EBX, EBP, ESP]> {
-  let Methods = [{
-    iterator allocation_order_end(MachineFunction &MF) const {
+  let MethodProtos = [{
+    iterator allocation_order_end(MachineFunction &MF) const;
+  }];
+  let MethodBodies = [{
+    R32Class::iterator
+    R32Class::allocation_order_end(MachineFunction &MF) const {
       if (hasFP(MF))     // Does the function dedicate EBP to being a frame ptr?
         return end()-2;  // If so, don't allocate ESP or EBP
       else
@@ -115,8 +123,12 @@
 // for transforming FPn allocations to STn registers)
 def RST : RegisterClass<"X86", f64, 32,
                         [ST0, ST1, ST2, ST3, ST4, ST5, ST6, ST7]> {
-  let Methods = [{
-    iterator allocation_order_end(MachineFunction &MF) const {
+    let MethodProtos = [{
+    iterator allocation_order_end(MachineFunction &MF) const;
+  }];
+  let MethodBodies = [{
+    RSTClass::iterator
+    RSTClass::allocation_order_end(MachineFunction &MF) const {
       return begin();
     }
   }];





From lattner at cs.uiuc.edu  Fri Aug 19 14:13:33 2005
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Fri, 19 Aug 2005 14:13:33 -0500
Subject: [llvm-commits] CVS: llvm/lib/Target/PowerPC/PPC32RegisterInfo.td
	PPC64RegisterInfo.td 
Message-ID: <200508191913.OAA09521@zion.cs.uiuc.edu>



Changes in directory llvm/lib/Target/PowerPC:

PPC32RegisterInfo.td updated: 1.6 -> 1.7
PPC64RegisterInfo.td updated: 1.5 -> 1.6
---
Log message:

Split RegisterClass 'Methods' into MethodProtos and MethodBodies


---
Diffs of the changes:  (+18 -6)

 PPC32RegisterInfo.td |   12 +++++++++---
 PPC64RegisterInfo.td |   12 +++++++++---
 2 files changed, 18 insertions(+), 6 deletions(-)


Index: llvm/lib/Target/PowerPC/PPC32RegisterInfo.td
diff -u llvm/lib/Target/PowerPC/PPC32RegisterInfo.td:1.6 llvm/lib/Target/PowerPC/PPC32RegisterInfo.td:1.7
--- llvm/lib/Target/PowerPC/PPC32RegisterInfo.td:1.6	Fri Aug 19 13:52:55 2005
+++ llvm/lib/Target/PowerPC/PPC32RegisterInfo.td	Fri Aug 19 14:13:20 2005
@@ -20,11 +20,17 @@
       R30, R29, R28, R27, R26, R25, R24, R23, R22, R21, R20, R19, R18, R17,
       R16, R15, R14, R13, R31, R0, R1, LR]>
 {
-  let Methods = [{
-    iterator allocation_order_begin(MachineFunction &MF) const {
+  let MethodProtos = [{
+    iterator allocation_order_begin(MachineFunction &MF) const;
+    iterator allocation_order_end(MachineFunction &MF) const;
+  }];
+  let MethodBodies = [{
+    GPRCClass::iterator
+    GPRCClass::allocation_order_begin(MachineFunction &MF) const {
       return begin() + ((TargetAIX == PPCTarget) ? 1 : 0);
     }
-    iterator allocation_order_end(MachineFunction &MF) const {
+    GPRCClass::iterator
+    GPRCClass::allocation_order_end(MachineFunction &MF) const {
       if (hasFP(MF))
         return end()-4;
       else


Index: llvm/lib/Target/PowerPC/PPC64RegisterInfo.td
diff -u llvm/lib/Target/PowerPC/PPC64RegisterInfo.td:1.5 llvm/lib/Target/PowerPC/PPC64RegisterInfo.td:1.6
--- llvm/lib/Target/PowerPC/PPC64RegisterInfo.td:1.5	Fri Aug 19 13:52:55 2005
+++ llvm/lib/Target/PowerPC/PPC64RegisterInfo.td	Fri Aug 19 14:13:20 2005
@@ -20,11 +20,17 @@
       R30, R29, R28, R27, R26, R25, R24, R23, R22, R21, R20, R19, R18, R17,
       R16, R15, R14, R13, R31, R0, R1, LR]>
 {
-  let Methods = [{
-    iterator allocation_order_begin(MachineFunction &MF) const {
+  let MethodProtos = [{
+    iterator allocation_order_begin(MachineFunction &MF) const;
+    iterator allocation_order_end(MachineFunction &MF) const;
+  }];
+  let MethodBodies = [{
+    GPRCClass::iterator
+    GPRCClass::allocation_order_begin(MachineFunction &MF) const {
       return begin() + ((TargetAIX == PPCTarget) ? 1 : 0);
     }
-    iterator allocation_order_end(MachineFunction &MF) const {
+    GPRCClass::iterator
+    GPRCClass::allocation_order_end(MachineFunction &MF) const {
       if (hasFP(MF))
         return end()-4;
       else





From lattner at cs.uiuc.edu  Fri Aug 19 14:13:34 2005
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Fri, 19 Aug 2005 14:13:34 -0500
Subject: [llvm-commits] CVS: llvm/lib/Target/IA64/IA64RegisterInfo.td 
Message-ID: <200508191913.OAA09525@zion.cs.uiuc.edu>



Changes in directory llvm/lib/Target/IA64:

IA64RegisterInfo.td updated: 1.7 -> 1.8
---
Log message:

Split RegisterClass 'Methods' into MethodProtos and MethodBodies


---
Diffs of the changes:  (+9 -4)

 IA64RegisterInfo.td |   13 +++++++++----
 1 files changed, 9 insertions(+), 4 deletions(-)


Index: llvm/lib/Target/IA64/IA64RegisterInfo.td
diff -u llvm/lib/Target/IA64/IA64RegisterInfo.td:1.7 llvm/lib/Target/IA64/IA64RegisterInfo.td:1.8
--- llvm/lib/Target/IA64/IA64RegisterInfo.td:1.7	Fri Aug 19 13:50:46 2005
+++ llvm/lib/Target/IA64/IA64RegisterInfo.td	Fri Aug 19 14:13:20 2005
@@ -257,14 +257,19 @@
         r120, r121, r122, r123, r124, r125, r126, r127,
 	r0, r1, r2, r12, r13, r15, r22]> // the last 15 are special (look down)
   {
-    let Methods = [{
-
-      iterator allocation_order_begin(MachineFunction &MF) const {
+    let MethodProtos = [{
+    iterator allocation_order_begin(MachineFunction &MF) const;
+    iterator allocation_order_end(MachineFunction &MF) const;
+  }];
+  let MethodBodies = [{
+    GRClass::iterator
+    GRClass::allocation_order_begin(MachineFunction &MF) const {
 	// hide registers appropriately:
 	return begin()+(8-(MF.getInfo<IA64FunctionInfo>()->outRegsUsed));
       }
 
-      iterator allocation_order_end(MachineFunction &MF) const {
+      GRClass::iterator
+      GRClass::allocation_order_end(MachineFunction &MF) const {
 	int numReservedRegs=7; // the 7 special registers r0,r1,r2,r12,r13 etc
 
 	// we also can't allocate registers for use as locals if they're





From lattner at cs.uiuc.edu  Fri Aug 19 14:13:34 2005
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Fri, 19 Aug 2005 14:13:34 -0500
Subject: [llvm-commits] CVS: llvm/lib/Target/SparcV8/SparcV8RegisterInfo.td 
Message-ID: <200508191913.OAA09527@zion.cs.uiuc.edu>



Changes in directory llvm/lib/Target/SparcV8:

SparcV8RegisterInfo.td updated: 1.21 -> 1.22
---
Log message:

Split RegisterClass 'Methods' into MethodProtos and MethodBodies


---
Diffs of the changes:  (+7 -2)

 SparcV8RegisterInfo.td |    9 +++++++--
 1 files changed, 7 insertions(+), 2 deletions(-)


Index: llvm/lib/Target/SparcV8/SparcV8RegisterInfo.td
diff -u llvm/lib/Target/SparcV8/SparcV8RegisterInfo.td:1.21 llvm/lib/Target/SparcV8/SparcV8RegisterInfo.td:1.22
--- llvm/lib/Target/SparcV8/SparcV8RegisterInfo.td:1.21	Fri Aug 19 13:49:22 2005
+++ llvm/lib/Target/SparcV8/SparcV8RegisterInfo.td	Fri Aug 19 14:13:20 2005
@@ -97,8 +97,13 @@
                                      G0, // constant zero
                                      G5, G6, G7 // reserved for kernel
                                      ]> {
-  let Methods = [{
-    iterator allocation_order_end(MachineFunction &MF) const {
+  let MethodProtos = [{
+    iterator allocation_order_end(MachineFunction &MF) const;
+  }];
+  let MethodBodies = [{
+    IntRegsClass::iterator
+    IntRegsClass::allocation_order_end(MachineFunction &MF) const {
+      // FIXME: These special regs should be taken out of the regclass!
       return end()-10;  // Don't allocate special registers
     }
   }];





From lattner at cs.uiuc.edu  Fri Aug 19 14:13:34 2005
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Fri, 19 Aug 2005 14:13:34 -0500
Subject: [llvm-commits] CVS: llvm/lib/Target/Target.td 
Message-ID: <200508191913.OAA09533@zion.cs.uiuc.edu>



Changes in directory llvm/lib/Target:

Target.td updated: 1.45 -> 1.46
---
Log message:

Split RegisterClass 'Methods' into MethodProtos and MethodBodies


---
Diffs of the changes:  (+5 -3)

 Target.td |    8 +++++---
 1 files changed, 5 insertions(+), 3 deletions(-)


Index: llvm/lib/Target/Target.td
diff -u llvm/lib/Target/Target.td:1.45 llvm/lib/Target/Target.td:1.46
--- llvm/lib/Target/Target.td:1.45	Fri Aug 19 13:48:48 2005
+++ llvm/lib/Target/Target.td	Fri Aug 19 14:13:20 2005
@@ -100,9 +100,11 @@
   //
   list<Register> MemberList = regList;
 
-  // Methods - This member can be used to insert arbitrary code into a generated
-  // register class.   The normal usage of this is to overload virtual methods.
-  code Methods = [{}];
+  // MethodProtos/MethodBodies - These members can be used to insert arbitrary
+  // code into a generated register class.   The normal usage of this is to 
+  // overload virtual methods.
+  code MethodProtos = [{}];
+  code MethodBodies = [{}];
 }
 
 





From lattner at cs.uiuc.edu  Fri Aug 19 15:23:54 2005
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Fri, 19 Aug 2005 15:23:54 -0500
Subject: [llvm-commits] CVS: llvm/utils/TableGen/RegisterInfoEmitter.cpp 
Message-ID: <200508192023.PAA09838@zion.cs.uiuc.edu>



Changes in directory llvm/utils/TableGen:

RegisterInfoEmitter.cpp updated: 1.29 -> 1.30
---
Log message:

Expose the derived register classes to the public header, allowing them
to be accessed.


---
Diffs of the changes:  (+23 -22)

 RegisterInfoEmitter.cpp |   45 +++++++++++++++++++++++----------------------
 1 files changed, 23 insertions(+), 22 deletions(-)


Index: llvm/utils/TableGen/RegisterInfoEmitter.cpp
diff -u llvm/utils/TableGen/RegisterInfoEmitter.cpp:1.29 llvm/utils/TableGen/RegisterInfoEmitter.cpp:1.30
--- llvm/utils/TableGen/RegisterInfoEmitter.cpp:1.29	Fri Aug 19 14:12:51 2005
+++ llvm/utils/TableGen/RegisterInfoEmitter.cpp	Fri Aug 19 15:23:42 2005
@@ -69,7 +69,17 @@
        << " { // Register classes\n";
     for (unsigned i = 0, e = RegisterClasses.size(); i != e; ++i) {
       const std::string &Name = RegisterClasses[i].getName();
-      OS << "  extern TargetRegisterClass * const "<< Name <<"RegisterClass;\n";
+
+      // Output the register class definition.
+      OS << "  struct " << Name << "Class : public TargetRegisterClass {\n"
+         << "    " << Name << "Class();\n"
+         << RegisterClasses[i].MethodProtos << "  };\n";
+
+      // Output the extern for the instance.
+      OS << "  extern " << Name << "Class\t" << Name << "RegClass;\n";
+      // Output the extern for the pointer to the instance (should remove).
+      OS << "  static TargetRegisterClass * const "<< Name <<"RegisterClass = &"
+         << Name << "RegClass;\n";
     }
     OS << "} // end of namespace " << TargetName << "\n\n";
   }
@@ -121,13 +131,6 @@
       RegClassesBelongedTo.insert(std::make_pair(Reg, &RC));
     }
     OS << "\n  };\n\n";
-
-    OS << "  struct " << Name << "Class : public TargetRegisterClass {\n"
-       << "    " << Name << "Class() : TargetRegisterClass("
-       << RC.SpillSize/8 << ", " << RC.SpillAlignment/8 << ", " << Name << ", "
-       << Name << " + " << RC.Elements.size() << ") {}\n"
-       << RC.MethodProtos << "  };\n";
-    OS << RC.MethodBodies << "\n";
   }
   OS << "}  // end anonymous namespace\n\n";
   
@@ -137,7 +140,17 @@
        << " {   // Register class instances\n";
     for (unsigned i = 0, e = RegisterClasses.size(); i != e; ++i)
       OS << "  " << RegisterClasses[i].getName()  << "Class\t"
-         << RegisterClasses[i].getName() << "RegClassInstance;\n";
+         << RegisterClasses[i].getName() << "RegClass;\n";
+    
+    for (unsigned i = 0, e = RegisterClasses.size(); i != e; ++i) {
+      const CodeGenRegisterClass &RC = RegisterClasses[i];
+      OS << RC.MethodBodies << "\n";
+      OS << RC.getName() << "Class::" << RC.getName()
+        << "Class()  : TargetRegisterClass(" << RC.SpillSize/8 << ", "
+        << RC.SpillAlignment/8 << ", " << RC.getName() << ", "
+        << RC.getName() << " + " << RC.Elements.size() << ") {}\n";
+    }
+  
     OS << "}\n";
   }
 
@@ -145,7 +158,7 @@
   OS << "  const TargetRegisterClass* const RegisterClasses[] = {\n";
   for (unsigned i = 0, e = RegisterClasses.size(); i != e; ++i)
     OS << "    &" << getQualifiedName(RegisterClasses[i].TheDef)
-       << "RegClassInstance,\n";
+       << "RegClass,\n";
   OS << "  };\n";
 
   // Emit register class aliases...
@@ -238,18 +251,6 @@
   OS << "  };\n";      // End of register descriptors...
   OS << "}\n\n";       // End of anonymous namespace...
 
-  if (!RegisterClasses.empty()) {
-    OS << "namespace " << RegisterClasses[0].Namespace
-       << " { // Register classes\n";
-    for (unsigned i = 0, e = RegisterClasses.size(); i != e; ++i) {
-      OS << "  TargetRegisterClass * const " << RegisterClasses[i].getName()
-         << "RegisterClass = &" << getQualifiedName(RegisterClasses[i].TheDef)
-         << "RegClassInstance;\n";
-    }
-    OS << "} // end of namespace " << RegisterClasses[0].Namespace << "\n\n";
-  }
-
-
   std::string ClassName = Target.getName() + "GenRegisterInfo";
 
   // Emit the constructor of the class...





From lattner at cs.uiuc.edu  Fri Aug 19 15:29:26 2005
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Fri, 19 Aug 2005 15:29:26 -0500
Subject: [llvm-commits] CVS: llvm/utils/TableGen/InstrInfoEmitter.cpp 
Message-ID: <200508192029.PAA09912@zion.cs.uiuc.edu>



Changes in directory llvm/utils/TableGen:

InstrInfoEmitter.cpp updated: 1.24 -> 1.25
---
Log message:


Emit this:

static const TargetOperandInfo OperandInfo6[] = { { &PPC32::CRRCRegClass }, { 0 }, };

instead of this:

static const TargetOperandInfo OperandInfo6[] = { { PPC32::CRRCRegisterClass }, { 0 }, }; 

For operand information, which does not require dynamic (startup-time) 
initialization.



---
Diffs of the changes:  (+1 -2)

 InstrInfoEmitter.cpp |    3 +--
 1 files changed, 1 insertion(+), 2 deletions(-)


Index: llvm/utils/TableGen/InstrInfoEmitter.cpp
diff -u llvm/utils/TableGen/InstrInfoEmitter.cpp:1.24 llvm/utils/TableGen/InstrInfoEmitter.cpp:1.25
--- llvm/utils/TableGen/InstrInfoEmitter.cpp:1.24	Fri Aug 19 13:46:26 2005
+++ llvm/utils/TableGen/InstrInfoEmitter.cpp	Fri Aug 19 15:29:14 2005
@@ -136,8 +136,7 @@
       OS << "static const TargetOperandInfo OperandInfo" << N << "[] = { ";
       for (unsigned i = 0, e = OperandInfo.size(); i != e; ++i) {
         if (Record *RC = OperandInfo[i]) {
-          // FIXME: BAD: REQUIRES RUNTIME INIT
-          OS << "{ " << getQualifiedName(RC) << "RegisterClass }, ";
+          OS << "{ &" << getQualifiedName(RC) << "RegClass }, ";
         } else {
           OS << "{ 0 }, ";
         }





From lattner at cs.uiuc.edu  Fri Aug 19 15:45:54 2005
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Fri, 19 Aug 2005 15:45:54 -0500
Subject: [llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp 
Message-ID: <200508192045.PAA10056@zion.cs.uiuc.edu>



Changes in directory llvm/lib/CodeGen/SelectionDAG:

ScheduleDAG.cpp updated: 1.4 -> 1.5
---
Log message:

Now that we have operand info for machine instructions, use it to create
temporary registers for things that define a register.  This allows dag->dag
isel to compile this:

int %test() { ret int 65535 }

into:

_test:
        lis r2, 0
        ori r2, r2, 65535
        blr

Next up, getting CopyFromReg to work, allowing arguments and cross-bb values.



---
Diffs of the changes:  (+21 -8)

 ScheduleDAG.cpp |   29 +++++++++++++++++++++--------
 1 files changed, 21 insertions(+), 8 deletions(-)


Index: llvm/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp:1.4 llvm/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp:1.5
--- llvm/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp:1.4	Thu Aug 18 20:01:34 2005
+++ llvm/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp	Fri Aug 19 15:45:43 2005
@@ -13,8 +13,10 @@
 //===----------------------------------------------------------------------===//
 
 #define DEBUG_TYPE "sched"
+#include "llvm/CodeGen/MachineFunction.h"
 #include "llvm/CodeGen/SelectionDAGISel.h"
 #include "llvm/CodeGen/SelectionDAG.h"
+#include "llvm/CodeGen/SSARegMap.h"
 #include "llvm/Target/TargetMachine.h"
 #include "llvm/Target/TargetInstrInfo.h"
 #include "llvm/Support/CommandLine.h"
@@ -34,11 +36,13 @@
     MachineBasicBlock *BB;
     const TargetMachine &TM;
     const TargetInstrInfo &TII;
+    SSARegMap *RegMap;
     
     std::map<SDNode *, unsigned> EmittedOps;
   public:
     SimpleSched(SelectionDAG &D, MachineBasicBlock *bb)
-      : DAG(D), BB(bb), TM(D.getTarget()), TII(*TM.getInstrInfo()) {
+      : DAG(D), BB(bb), TM(D.getTarget()), TII(*TM.getInstrInfo()),
+        RegMap(BB->getParent()->getSSARegMap()) {
       assert(&TII && "Target doesn't provide instr info?");
     }
     
@@ -73,14 +77,14 @@
     // Target nodes have any register or immediate operands before any chain
     // nodes.  Check that the DAG matches the TD files's expectation of #
     // operands.
+    unsigned NumResults = Op.Val->getNumValues();
+    if (NumResults && Op.getOperand(NumResults-1).getValueType() == MVT::Other)
+      --NumResults;
 #ifndef _NDEBUG
     unsigned Operands = Op.getNumOperands();
     if (Operands && Op.getOperand(Operands-1).getValueType() == MVT::Other)
       --Operands;
-    unsigned Results = Op.Val->getNumValues();
-    if (Results && Op.getOperand(Results-1).getValueType() == MVT::Other)
-      --Results;
-    assert(unsigned(II.numOperands) == Operands+Results &&
+    assert(unsigned(II.numOperands) == Operands+NumResults &&
            "#operands for dag node doesn't match .td file!"); 
 #endif
 
@@ -89,9 +93,18 @@
     
     // Add result register values for things that are defined by this
     // instruction.
-    assert(Op.Val->getNumValues() == 1 &&
-           Op.getValue(0).getValueType() == MVT::Other &&
-           "Return values not implemented yet");
+    if (NumResults) {
+      // Create the result registers for this node and add the result regs to
+      // the machine instruction.
+      const TargetOperandInfo *OpInfo = II.OpInfo;
+      ResultReg = RegMap->createVirtualRegister(OpInfo[0].RegClass);
+      MI->addRegOperand(ResultReg, MachineOperand::Def);
+      for (unsigned i = 1; i != NumResults; ++i) {
+        assert(OpInfo[i].RegClass && "Isn't a register operand!");
+        MI->addRegOperand(RegMap->createVirtualRegister(OpInfo[0].RegClass),
+                          MachineOperand::Def);
+      }
+    }
     
     // Emit all of the operands of this instruction, adding them to the
     // instruction as appropriate.





From lattner at cs.uiuc.edu  Fri Aug 19 15:51:04 2005
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Fri, 19 Aug 2005 15:51:04 -0500
Subject: [llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp 
Message-ID: <200508192051.PAA10132@zion.cs.uiuc.edu>



Changes in directory llvm/lib/CodeGen/SelectionDAG:

ScheduleDAG.cpp updated: 1.5 -> 1.6
---
Log message:

Before implementing copyfromreg, we'll implement copytoreg correctly.
This gets us this for the previous testcase:

_test:
        lis r2, 0
        ori r3, r2, 65535
        blr

Note that we actually write to r3 (the return reg) correctly now :)



---
Diffs of the changes:  (+6 -2)

 ScheduleDAG.cpp |    8 ++++++--
 1 files changed, 6 insertions(+), 2 deletions(-)


Index: llvm/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp:1.5 llvm/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp:1.6
--- llvm/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp:1.5	Fri Aug 19 15:45:43 2005
+++ llvm/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp	Fri Aug 19 15:50:53 2005
@@ -36,14 +36,16 @@
     MachineBasicBlock *BB;
     const TargetMachine &TM;
     const TargetInstrInfo &TII;
+    const MRegisterInfo &MRI;
     SSARegMap *RegMap;
     
     std::map<SDNode *, unsigned> EmittedOps;
   public:
     SimpleSched(SelectionDAG &D, MachineBasicBlock *bb)
       : DAG(D), BB(bb), TM(D.getTarget()), TII(*TM.getInstrInfo()),
-        RegMap(BB->getParent()->getSSARegMap()) {
+        MRI(*TM.getRegisterInfo()), RegMap(BB->getParent()->getSSARegMap()) {
       assert(&TII && "Target doesn't provide instr info?");
+      assert(&MRI && "Target doesn't provide register info?");
     }
     
     void Run() {
@@ -131,7 +133,9 @@
     case ISD::EntryToken: break;
     case ISD::CopyToReg: {
       unsigned Val = Emit(Op.getOperand(2));
-      // FIXME: DO THE COPY NOW.
+      MRI.copyRegToReg(*BB, BB->end(),
+                       cast<RegisterSDNode>(Op.getOperand(1))->getReg(), Val,
+                       RegMap->getRegClass(Val));
       break;
     }
     }





From lattner at cs.uiuc.edu  Fri Aug 19 16:21:28 2005
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Fri, 19 Aug 2005 16:21:28 -0500
Subject: [llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
	SelectionDAGPrinter.cpp 
Message-ID: <200508192121.QAA10350@zion.cs.uiuc.edu>



Changes in directory llvm/lib/CodeGen/SelectionDAG:

SelectionDAG.cpp updated: 1.150 -> 1.151
SelectionDAGPrinter.cpp updated: 1.21 -> 1.22
---
Log message:

Print physreg register nodes with target names (e.g. F1) instead of numbers


---
Diffs of the changes:  (+12 -2)

 SelectionDAG.cpp        |    6 +++++-
 SelectionDAGPrinter.cpp |    8 +++++++-
 2 files changed, 12 insertions(+), 2 deletions(-)


Index: llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp:1.150 llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp:1.151
--- llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp:1.150	Thu Aug 18 23:39:48 2005
+++ llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp	Fri Aug 19 16:21:15 2005
@@ -2070,7 +2070,11 @@
       std::cerr << LBB->getName() << " ";
     std::cerr << (const void*)BBDN->getBasicBlock() << ">";
   } else if (const RegisterSDNode *C2V = dyn_cast<RegisterSDNode>(this)) {
-    std::cerr << " #" << C2V->getReg();
+    if (G && MRegisterInfo::isPhysicalRegister(R->getReg())) {
+      std::cerr << " " <<G->getTarget().getRegisterInfo()->getName(R->getReg());
+    } else {
+      std::cerr << " #" << R->getReg();
+    }
   } else if (const ExternalSymbolSDNode *ES =
              dyn_cast<ExternalSymbolSDNode>(this)) {
     std::cerr << "'" << ES->getSymbol() << "'";


Index: llvm/lib/CodeGen/SelectionDAG/SelectionDAGPrinter.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/SelectionDAGPrinter.cpp:1.21 llvm/lib/CodeGen/SelectionDAG/SelectionDAGPrinter.cpp:1.22
--- llvm/lib/CodeGen/SelectionDAG/SelectionDAGPrinter.cpp:1.21	Wed Aug 17 22:31:02 2005
+++ llvm/lib/CodeGen/SelectionDAG/SelectionDAGPrinter.cpp	Fri Aug 19 16:21:16 2005
@@ -13,6 +13,8 @@
 
 #include "llvm/CodeGen/SelectionDAG.h"
 #include "llvm/CodeGen/MachineFunction.h"
+#include "llvm/Target/MRegisterInfo.h"
+#include "llvm/Target/TargetMachine.h"
 #include "llvm/Function.h"
 #include "llvm/Support/GraphWriter.h"
 #include "llvm/ADT/StringExtras.h"
@@ -73,7 +75,11 @@
       Op += LBB->getName();
     //Op += " " + (const void*)BBDN->getBasicBlock();
   } else if (const RegisterSDNode *R = dyn_cast<RegisterSDNode>(Node)) {
-    Op += " #" + utostr(R->getReg());
+    if (G && MRegisterInfo::isPhysicalRegister(R->getReg())) {
+      Op = Op + " " + G->getTarget().getRegisterInfo()->getName(R->getReg());
+    } else {
+      Op += " #" + utostr(R->getReg());
+    }
   } else if (const ExternalSymbolSDNode *ES =
              dyn_cast<ExternalSymbolSDNode>(Node)) {
     Op += "'" + std::string(ES->getSymbol()) + "'";





From lattner at cs.uiuc.edu  Fri Aug 19 16:33:48 2005
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Fri, 19 Aug 2005 16:33:48 -0500
Subject: [llvm-commits] CVS: llvm/lib/Target/PowerPC/PPC32ISelDAGToDAG.cpp 
Message-ID: <200508192133.QAA10488@zion.cs.uiuc.edu>



Changes in directory llvm/lib/Target/PowerPC:

PPC32ISelDAGToDAG.cpp updated: 1.14 -> 1.15
---
Log message:

Fix a typeo, no wonder all tokenfactor edges were the same!


---
Diffs of the changes:  (+1 -1)

 PPC32ISelDAGToDAG.cpp |    2 +-
 1 files changed, 1 insertion(+), 1 deletion(-)


Index: llvm/lib/Target/PowerPC/PPC32ISelDAGToDAG.cpp
diff -u llvm/lib/Target/PowerPC/PPC32ISelDAGToDAG.cpp:1.14 llvm/lib/Target/PowerPC/PPC32ISelDAGToDAG.cpp:1.15
--- llvm/lib/Target/PowerPC/PPC32ISelDAGToDAG.cpp:1.14	Thu Aug 18 19:38:14 2005
+++ llvm/lib/Target/PowerPC/PPC32ISelDAGToDAG.cpp	Fri Aug 19 16:33:02 2005
@@ -347,7 +347,7 @@
     } else {
       std::vector<SDOperand> Ops;
       for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
-        Ops.push_back(Select(N->getOperand(0)));
+        Ops.push_back(Select(N->getOperand(i)));
       New = CurDAG->getNode(ISD::TokenFactor, MVT::Other, Ops);
     }
     





From lattner at cs.uiuc.edu  Fri Aug 19 16:34:25 2005
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Fri, 19 Aug 2005 16:34:25 -0500
Subject: [llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp 
Message-ID: <200508192134.QAA10523@zion.cs.uiuc.edu>



Changes in directory llvm/lib/CodeGen/SelectionDAG:

SelectionDAG.cpp updated: 1.151 -> 1.152
---
Log message:

Fix a bug in previous commit


---
Diffs of the changes:  (+2 -1)

 SelectionDAG.cpp |    3 ++-
 1 files changed, 2 insertions(+), 1 deletion(-)


Index: llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp:1.151 llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp:1.152
--- llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp:1.151	Fri Aug 19 16:21:15 2005
+++ llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp	Fri Aug 19 16:34:13 2005
@@ -17,6 +17,7 @@
 #include "llvm/Assembly/Writer.h"
 #include "llvm/CodeGen/MachineBasicBlock.h"
 #include "llvm/Support/MathExtras.h"
+#include "llvm/Target/MRegisterInfo.h"
 #include "llvm/Target/TargetLowering.h"
 #include "llvm/Target/TargetInstrInfo.h"
 #include "llvm/Target/TargetMachine.h"
@@ -2069,7 +2070,7 @@
     if (LBB)
       std::cerr << LBB->getName() << " ";
     std::cerr << (const void*)BBDN->getBasicBlock() << ">";
-  } else if (const RegisterSDNode *C2V = dyn_cast<RegisterSDNode>(this)) {
+  } else if (const RegisterSDNode *R = dyn_cast<RegisterSDNode>(this)) {
     if (G && MRegisterInfo::isPhysicalRegister(R->getReg())) {
       std::cerr << " " <<G->getTarget().getRegisterInfo()->getName(R->getReg());
     } else {





From lattner at cs.uiuc.edu  Fri Aug 19 16:44:05 2005
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Fri, 19 Aug 2005 16:44:05 -0500
Subject: [llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp 
Message-ID: <200508192144.QAA10609@zion.cs.uiuc.edu>



Changes in directory llvm/lib/CodeGen/SelectionDAG:

ScheduleDAG.cpp updated: 1.6 -> 1.7
---
Log message:

Implement CopyFromReg, TokenFactor, and fix a bug in CopyToReg.  This allows
us to compile stuff like this:

double %test(double %A, double %B, double %C, double %E) {
        %F = mul double %A, %A
        %G = add double %F, %B
        %H = sub double -0.0, %G
        %I = mul double %H, %C
        %J = add double %I, %E
        ret double %J
}

to:

_test:
        fnmadd f0, f1, f1, f2
        fmadd f1, f0, f3, f4
        blr

woot!



---
Diffs of the changes:  (+30 -0)

 ScheduleDAG.cpp |   30 ++++++++++++++++++++++++++++++
 1 files changed, 30 insertions(+)


Index: llvm/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp:1.6 llvm/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp:1.7
--- llvm/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp:1.6	Fri Aug 19 15:50:53 2005
+++ llvm/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp	Fri Aug 19 16:43:53 2005
@@ -131,13 +131,43 @@
       Op.Val->dump(); 
       assert(0 && "This target-independent node should have been selected!");
     case ISD::EntryToken: break;
+    case ISD::TokenFactor:
+      for (unsigned i = 0, e = Op.getNumOperands(); i != e; ++i)
+        Emit(Op.getOperand(i));
+      break;
     case ISD::CopyToReg: {
+      Emit(Op.getOperand(0));   // Emit the chain.
       unsigned Val = Emit(Op.getOperand(2));
       MRI.copyRegToReg(*BB, BB->end(),
                        cast<RegisterSDNode>(Op.getOperand(1))->getReg(), Val,
                        RegMap->getRegClass(Val));
       break;
     }
+    case ISD::CopyFromReg: {
+      Emit(Op.getOperand(0));   // Emit the chain.
+      unsigned SrcReg = cast<RegisterSDNode>(Op.getOperand(1))->getReg();
+      
+      // Figure out the register class to create for the destreg.
+      const TargetRegisterClass *TRC;
+      if (MRegisterInfo::isVirtualRegister(SrcReg)) {
+        TRC = RegMap->getRegClass(SrcReg);
+      } else {
+        // FIXME: we don't know what register class to generate this for.  Do
+        // a brute force search and pick the first match. :(
+        for (MRegisterInfo::regclass_iterator I = MRI.regclass_begin(),
+               E = MRI.regclass_end(); I != E; ++I)
+          if ((*I)->contains(SrcReg)) {
+            TRC = *I;
+            break;
+          }
+        assert(TRC && "Couldn't find register class for reg copy!");
+      }
+      
+      // Create the reg, emit the copy.
+      ResultReg = RegMap->createVirtualRegister(TRC);
+      MRI.copyRegToReg(*BB, BB->end(), ResultReg, SrcReg, TRC);
+      break;
+    }
     }
   }
   





From lattner at cs.uiuc.edu  Fri Aug 19 17:31:16 2005
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Fri, 19 Aug 2005 17:31:16 -0500
Subject: [llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp 
Message-ID: <200508192231.RAA10848@zion.cs.uiuc.edu>



Changes in directory llvm/lib/CodeGen/SelectionDAG:

SelectionDAG.cpp updated: 1.152 -> 1.153
---
Log message:

Add support for TargetGlobalAddress nodes


---
Diffs of the changes:  (+14 -1)

 SelectionDAG.cpp |   15 ++++++++++++++-
 1 files changed, 14 insertions(+), 1 deletion(-)


Index: llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp:1.152 llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp:1.153
--- llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp:1.152	Fri Aug 19 16:34:13 2005
+++ llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp	Fri Aug 19 17:31:04 2005
@@ -255,6 +255,9 @@
   case ISD::GlobalAddress:
     GlobalValues.erase(cast<GlobalAddressSDNode>(N)->getGlobal());
     break;
+  case ISD::TargetGlobalAddress:
+    TargetGlobalValues.erase(cast<GlobalAddressSDNode>(N)->getGlobal());
+    break;
   case ISD::FrameIndex:
     FrameIndices.erase(cast<FrameIndexSDNode>(N)->getIndex());
     break;
@@ -413,7 +416,16 @@
                                          MVT::ValueType VT) {
   SDNode *&N = GlobalValues[GV];
   if (N) return SDOperand(N, 0);
-  N = new GlobalAddressSDNode(GV,VT);
+  N = new GlobalAddressSDNode(false, GV, VT);
+  AllNodes.push_back(N);
+  return SDOperand(N, 0);
+}
+
+SDOperand SelectionDAG::getTargetGlobalAddress(const GlobalValue *GV,
+                                               MVT::ValueType VT) {
+  SDNode *&N = TargetGlobalValues[GV];
+  if (N) return SDOperand(N, 0);
+  N = new GlobalAddressSDNode(true, GV, VT);
   AllNodes.push_back(N);
   return SDOperand(N, 0);
 }
@@ -1907,6 +1919,7 @@
   case ISD::TargetConstant: return "TargetConstant";
   case ISD::ConstantFP:    return "ConstantFP";
   case ISD::GlobalAddress: return "GlobalAddress";
+  case ISD::TargetGlobalAddress: return "TargetGlobalAddress";
   case ISD::FrameIndex:    return "FrameIndex";
   case ISD::BasicBlock:    return "BasicBlock";
   case ISD::Register:      return "Register";





From lattner at cs.uiuc.edu  Fri Aug 19 17:31:45 2005
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Fri, 19 Aug 2005 17:31:45 -0500
Subject: [llvm-commits] CVS: llvm/include/llvm/CodeGen/SelectionDAG.h
	SelectionDAGNodes.h 
Message-ID: <200508192231.RAA10910@zion.cs.uiuc.edu>



Changes in directory llvm/include/llvm/CodeGen:

SelectionDAG.h updated: 1.43 -> 1.44
SelectionDAGNodes.h updated: 1.58 -> 1.59
---
Log message:

ADd support for TargetGlobalAddress nodes


---
Diffs of the changes:  (+11 -3)

 SelectionDAG.h      |    2 ++
 SelectionDAGNodes.h |   12 +++++++++---
 2 files changed, 11 insertions(+), 3 deletions(-)


Index: llvm/include/llvm/CodeGen/SelectionDAG.h
diff -u llvm/include/llvm/CodeGen/SelectionDAG.h:1.43 llvm/include/llvm/CodeGen/SelectionDAG.h:1.44
--- llvm/include/llvm/CodeGen/SelectionDAG.h:1.43	Thu Aug 18 19:56:28 2005
+++ llvm/include/llvm/CodeGen/SelectionDAG.h	Fri Aug 19 17:31:34 2005
@@ -97,6 +97,7 @@
   SDOperand getTargetConstant(uint64_t Val, MVT::ValueType VT);
   SDOperand getConstantFP(double Val, MVT::ValueType VT);
   SDOperand getGlobalAddress(const GlobalValue *GV, MVT::ValueType VT);
+  SDOperand getTargetGlobalAddress(const GlobalValue *GV, MVT::ValueType VT);
   SDOperand getFrameIndex(int FI, MVT::ValueType VT);
   SDOperand getConstantPool(unsigned CPIdx, MVT::ValueType VT);
   SDOperand getBasicBlock(MachineBasicBlock *MBB);
@@ -288,6 +289,7 @@
            SDNode *> Loads;
 
   std::map<const GlobalValue*, SDNode*> GlobalValues;
+  std::map<const GlobalValue*, SDNode*> TargetGlobalValues;
   std::map<std::pair<uint64_t, MVT::ValueType>, SDNode*> Constants;
   std::map<std::pair<uint64_t, MVT::ValueType>, SDNode*> TargetConstants;
   std::map<std::pair<uint64_t, MVT::ValueType>, SDNode*> ConstantFPs;


Index: llvm/include/llvm/CodeGen/SelectionDAGNodes.h
diff -u llvm/include/llvm/CodeGen/SelectionDAGNodes.h:1.58 llvm/include/llvm/CodeGen/SelectionDAGNodes.h:1.59
--- llvm/include/llvm/CodeGen/SelectionDAGNodes.h:1.58	Thu Aug 18 02:25:46 2005
+++ llvm/include/llvm/CodeGen/SelectionDAGNodes.h	Fri Aug 19 17:31:34 2005
@@ -60,6 +60,11 @@
     // TargetConstant - Like Constant, but the DAG does not do any folding or
     // simplification of the constant.  This is used by the DAG->DAG selector.
     TargetConstant,
+    
+    // TargetGlobalAddress - Like GlobalAddress, but the DAG does no folding or
+    // anything else with this node, and this is valid in the target-specific
+    // dag, turning into a GlobalAddress operand.
+    TargetGlobalAddress,
 
     // CopyToReg - This node has three operands: a chain, a register number to
     // set to this value, and a value.  
@@ -775,8 +780,8 @@
   GlobalValue *TheGlobal;
 protected:
   friend class SelectionDAG;
-  GlobalAddressSDNode(const GlobalValue *GA, MVT::ValueType VT)
-    : SDNode(ISD::GlobalAddress, VT) {
+  GlobalAddressSDNode(bool isTarget, const GlobalValue *GA, MVT::ValueType VT)
+    : SDNode(isTarget ? ISD::TargetGlobalAddress : ISD::GlobalAddress, VT) {
     TheGlobal = const_cast<GlobalValue*>(GA);
   }
 public:
@@ -785,7 +790,8 @@
 
   static bool classof(const GlobalAddressSDNode *) { return true; }
   static bool classof(const SDNode *N) {
-    return N->getOpcode() == ISD::GlobalAddress;
+    return N->getOpcode() == ISD::GlobalAddress ||
+           N->getOpcode() == ISD::TargetGlobalAddress;
   }
 };
 





From lattner at cs.uiuc.edu  Fri Aug 19 17:38:36 2005
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Fri, 19 Aug 2005 17:38:36 -0500
Subject: [llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp 
Message-ID: <200508192238.RAA11083@zion.cs.uiuc.edu>



Changes in directory llvm/lib/CodeGen/SelectionDAG:

ScheduleDAG.cpp updated: 1.7 -> 1.8
---
Log message:

Add support for global address nodes


---
Diffs of the changes:  (+3 -0)

 ScheduleDAG.cpp |    3 +++
 1 files changed, 3 insertions(+)


Index: llvm/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp:1.7 llvm/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp:1.8
--- llvm/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp:1.7	Fri Aug 19 16:43:53 2005
+++ llvm/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp	Fri Aug 19 17:38:24 2005
@@ -115,6 +115,9 @@
         MI->addZeroExtImm64Operand(C->getValue());
       } else if (RegisterSDNode*R =dyn_cast<RegisterSDNode>(Op.getOperand(i))) {
         MI->addRegOperand(R->getReg(), MachineOperand::Use);
+      } else if (GlobalAddressSDNode *TGA =
+                       dyn_cast<GlobalAddressSDNode>(Op.getOperand(i))) {
+        MI->addGlobalAddressOperand(TGA->getGlobal(), false, 0);
       } else {
         unsigned R = Emit(Op.getOperand(i));
         // Add an operand, unless this corresponds to a chain node.





From lattner at cs.uiuc.edu  Fri Aug 19 17:39:05 2005
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Fri, 19 Aug 2005 17:39:05 -0500
Subject: [llvm-commits] CVS: llvm/lib/Target/PowerPC/PPC32ISelDAGToDAG.cpp 
Message-ID: <200508192239.RAA11116@zion.cs.uiuc.edu>



Changes in directory llvm/lib/Target/PowerPC:

PPC32ISelDAGToDAG.cpp updated: 1.15 -> 1.16
---
Log message:

add support for global address, including PIC support.
This REALLY should be lowered by the legalizer!



---
Diffs of the changes:  (+48 -1)

 PPC32ISelDAGToDAG.cpp |   49 ++++++++++++++++++++++++++++++++++++++++++++++++-
 1 files changed, 48 insertions(+), 1 deletion(-)


Index: llvm/lib/Target/PowerPC/PPC32ISelDAGToDAG.cpp
diff -u llvm/lib/Target/PowerPC/PPC32ISelDAGToDAG.cpp:1.15 llvm/lib/Target/PowerPC/PPC32ISelDAGToDAG.cpp:1.16
--- llvm/lib/Target/PowerPC/PPC32ISelDAGToDAG.cpp:1.15	Fri Aug 19 16:33:02 2005
+++ llvm/lib/Target/PowerPC/PPC32ISelDAGToDAG.cpp	Fri Aug 19 17:38:53 2005
@@ -15,10 +15,14 @@
 #include "PowerPC.h"
 #include "PPC32TargetMachine.h"
 #include "PPC32ISelLowering.h"
+#include "llvm/CodeGen/MachineInstrBuilder.h"
+#include "llvm/CodeGen/MachineFunction.h"
+#include "llvm/CodeGen/SSARegMap.h"
 #include "llvm/CodeGen/SelectionDAG.h"
 #include "llvm/CodeGen/SelectionDAGISel.h"
 #include "llvm/Target/TargetOptions.h"
 #include "llvm/ADT/Statistic.h"
+#include "llvm/GlobalValue.h"
 #include "llvm/Support/Debug.h"
 #include "llvm/Support/MathExtras.h"
 using namespace llvm;
@@ -34,16 +38,26 @@
   ///
   class PPC32DAGToDAGISel : public SelectionDAGISel {
     PPC32TargetLowering PPC32Lowering;
-    
+    unsigned GlobalBaseReg;
   public:
     PPC32DAGToDAGISel(TargetMachine &TM)
       : SelectionDAGISel(PPC32Lowering), PPC32Lowering(TM) {}
     
+    virtual bool runOnFunction(Function &Fn) {
+      // Make sure we re-emit a set of the global base reg if necessary
+      GlobalBaseReg = 0;
+      return SelectionDAGISel::runOnFunction(Fn);
+    }
+   
     /// getI32Imm - Return a target constant with the specified value, of type
     /// i32.
     inline SDOperand getI32Imm(unsigned Imm) {
       return CurDAG->getTargetConstant(Imm, MVT::i32);
     }
+
+    /// getGlobalBaseReg - insert code into the entry mbb to materialize the PIC
+    /// base register.  Return the virtual register that holds this value.
+    unsigned getGlobalBaseReg();
     
     // Select - Convert the specified operand from a target-independent to a
     // target-specific node if it hasn't already been changed.
@@ -73,6 +87,23 @@
   };
 }
 
+/// getGlobalBaseReg - Output the instructions required to put the
+/// base address to use for accessing globals into a register.
+///
+unsigned PPC32DAGToDAGISel::getGlobalBaseReg() {
+  if (!GlobalBaseReg) {
+    // Insert the set of GlobalBaseReg into the first MBB of the function
+    MachineBasicBlock &FirstMBB = BB->getParent()->front();
+    MachineBasicBlock::iterator MBBI = FirstMBB.begin();
+    SSARegMap *RegMap = BB->getParent()->getSSARegMap();
+    GlobalBaseReg = RegMap->createVirtualRegister(PPC32::GPRCRegisterClass);
+    BuildMI(FirstMBB, MBBI, PPC::MovePCtoLR, 0, PPC::LR);
+    BuildMI(FirstMBB, MBBI, PPC::MFLR, 1, GlobalBaseReg);
+  }
+  return GlobalBaseReg;
+}
+
+
 // isIntImmediate - This method tests to see if a constant operand.
 // If so Imm will receive the 32 bit value.
 static bool isIntImmediate(SDNode *N, unsigned& Imm) {
@@ -392,6 +423,22 @@
     }
     break;
   }
+  case ISD::GlobalAddress: {
+    GlobalValue *GV = cast<GlobalAddressSDNode>(N)->getGlobal();
+    SDOperand Tmp;
+    SDOperand GA = CurDAG->getTargetGlobalAddress(GV, MVT::i32);
+    if (PICEnabled) {
+      SDOperand PICBaseReg = CurDAG->getRegister(getGlobalBaseReg(), MVT::i32);
+      Tmp = CurDAG->getTargetNode(PPC::ADDIS, MVT::i32, PICBaseReg, GA);
+    } else {
+      Tmp = CurDAG->getTargetNode(PPC::LIS, MVT::i32, GA);
+    }
+    if (GV->hasWeakLinkage() || GV->isExternal())
+      CurDAG->SelectNodeTo(N, MVT::i32, PPC::LWZ, GA, Tmp);
+    else
+      CurDAG->SelectNodeTo(N, MVT::i32, PPC::LA, Tmp, GA);
+    break;
+  }
   case ISD::SIGN_EXTEND_INREG:
     switch(cast<VTSDNode>(N->getOperand(1))->getVT()) {
     default: assert(0 && "Illegal type in SIGN_EXTEND_INREG"); break;





From jlaskey at apple.com  Sat Aug 20 06:05:35 2005
From: jlaskey at apple.com (Jim Laskey)
Date: Sat, 20 Aug 2005 06:05:35 -0500
Subject: [llvm-commits] CVS: llvm/lib/Target/IA64/IA64ISelPattern.cpp 
Message-ID: <200508201105.GAA12649@zion.cs.uiuc.edu>



Changes in directory llvm/lib/Target/IA64:

IA64ISelPattern.cpp updated: 1.56 -> 1.57
---
Log message:

Repair an out by one error for IA64.



---
Diffs of the changes:  (+1 -1)

 IA64ISelPattern.cpp |    2 +-
 1 files changed, 1 insertion(+), 1 deletion(-)


Index: llvm/lib/Target/IA64/IA64ISelPattern.cpp
diff -u llvm/lib/Target/IA64/IA64ISelPattern.cpp:1.56 llvm/lib/Target/IA64/IA64ISelPattern.cpp:1.57
--- llvm/lib/Target/IA64/IA64ISelPattern.cpp:1.56	Fri Aug 19 08:25:50 2005
+++ llvm/lib/Target/IA64/IA64ISelPattern.cpp	Sat Aug 20 06:05:23 2005
@@ -875,7 +875,7 @@
   int64_t v = (int64_t)cast<ConstantSDNode>(N)->getSignExtended();
 
   if (isMask_64(v)) { // if ANDing with ((2^n)-1) for some n
-    Imm = Log2_64(v);
+    Imm = Log2_64(v) + 1;
     return 1; // say so
   }
 





From lattner at cs.uiuc.edu  Sat Aug 20 13:07:41 2005
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Sat, 20 Aug 2005 13:07:41 -0500
Subject: [llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp 
Message-ID: <200508201807.NAA28817@zion.cs.uiuc.edu>



Changes in directory llvm/lib/CodeGen/SelectionDAG:

ScheduleDAG.cpp updated: 1.8 -> 1.9
---
Log message:

fix bogus warning


---
Diffs of the changes:  (+1 -1)

 ScheduleDAG.cpp |    2 +-
 1 files changed, 1 insertion(+), 1 deletion(-)


Index: llvm/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp:1.8 llvm/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp:1.9
--- llvm/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp:1.8	Fri Aug 19 17:38:24 2005
+++ llvm/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp	Sat Aug 20 13:07:27 2005
@@ -151,7 +151,7 @@
       unsigned SrcReg = cast<RegisterSDNode>(Op.getOperand(1))->getReg();
       
       // Figure out the register class to create for the destreg.
-      const TargetRegisterClass *TRC;
+      const TargetRegisterClass *TRC = 0;
       if (MRegisterInfo::isVirtualRegister(SrcReg)) {
         TRC = RegMap->getRegClass(SrcReg);
       } else {





From duraid at octopus.com.au  Sun Aug 21 10:44:05 2005
From: duraid at octopus.com.au (Duraid Madina)
Date: Sun, 21 Aug 2005 10:44:05 -0500
Subject: [llvm-commits] CVS: llvm/lib/Target/IA64/IA64ISelPattern.cpp 
Message-ID: <200508211544.KAA06469@zion.cs.uiuc.edu>



Changes in directory llvm/lib/Target/IA64:

IA64ISelPattern.cpp updated: 1.57 -> 1.58
---
Log message:

reenable collapse of loadimm+AND -> dep.z (thanks guys)



---
Diffs of the changes:  (+6 -5)

 IA64ISelPattern.cpp |   11 ++++++-----
 1 files changed, 6 insertions(+), 5 deletions(-)


Index: llvm/lib/Target/IA64/IA64ISelPattern.cpp
diff -u llvm/lib/Target/IA64/IA64ISelPattern.cpp:1.57 llvm/lib/Target/IA64/IA64ISelPattern.cpp:1.58
--- llvm/lib/Target/IA64/IA64ISelPattern.cpp:1.57	Sat Aug 20 06:05:23 2005
+++ llvm/lib/Target/IA64/IA64ISelPattern.cpp	Sun Aug 21 10:43:53 2005
@@ -1439,7 +1439,7 @@
     case MVT::i32:
     case MVT::i64: {
       Tmp1 = SelectExpr(N.getOperand(0));
-/* FIXME     switch (ponderIntegerAndWith(N.getOperand(1), Tmp3)) {
+      switch (ponderIntegerAndWith(N.getOperand(1), Tmp3)) {
         case 1: // ANDing a constant that is 2^n-1 for some n
           switch (Tmp3) {
             case 8:  // if AND 0x00000000000000FF, be quaint and use zxt1
@@ -1452,12 +1452,13 @@
               BuildMI(BB, IA64::ZXT4, 1, Result).addReg(Tmp1);
               break;
             default: // otherwise, use dep.z to paste zeros
-              BuildMI(BB, IA64::DEPZ, 3, Result).addReg(Tmp1)
+            // FIXME: assert the dep.z is in bounds
+	      BuildMI(BB, IA64::DEPZ, 3, Result).addReg(Tmp1)
                 .addImm(0).addImm(Tmp3);
               break;
-          }
-          return Result; // early exit
-  FIXME } */ // fallthrough and emit a simple AND:
+	  }
+	  return Result; // early exit
+      } // fallthrough and emit a simple AND:
       Tmp2 = SelectExpr(N.getOperand(1));
       BuildMI(BB, IA64::AND, 2, Result).addReg(Tmp1).addReg(Tmp2);
     }





From lattner at cs.uiuc.edu  Sun Aug 21 11:37:48 2005
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Sun, 21 Aug 2005 11:37:48 -0500
Subject: [llvm-commits] 
	CVS: llvm/test/Regression/CodeGen/X86/shift-double.llx
Message-ID: <200508211637.LAA06748@zion.cs.uiuc.edu>



Changes in directory llvm/test/Regression/CodeGen/X86:

shift-double.llx updated: 1.6 -> 1.7
---
Log message:

Fix a bug in the RUN line


---
Diffs of the changes:  (+1 -1)

 shift-double.llx |    2 +-
 1 files changed, 1 insertion(+), 1 deletion(-)


Index: llvm/test/Regression/CodeGen/X86/shift-double.llx
diff -u llvm/test/Regression/CodeGen/X86/shift-double.llx:1.6 llvm/test/Regression/CodeGen/X86/shift-double.llx:1.7
--- llvm/test/Regression/CodeGen/X86/shift-double.llx:1.6	Thu Aug 18 20:14:40 2005
+++ llvm/test/Regression/CodeGen/X86/shift-double.llx	Sun Aug 21 11:37:36 2005
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86 -x86-asm-syntax=intel grep sh[lr]d | wc -l | grep 5
+; RUN: llvm-as < %s | llc -march=x86 -x86-asm-syntax=intel | grep sh[lr]d | wc -l | grep 5
 
 long %test1(long %X, ubyte %C) {
 	%Y = shl long %X, ubyte %C





From lattner at cs.uiuc.edu  Sun Aug 21 12:41:23 2005
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Sun, 21 Aug 2005 12:41:23 -0500
Subject: [llvm-commits] CVS: llvm/lib/Target/PowerPC/PPC32ISelPattern.cpp 
Message-ID: <200508211741.MAA07351@zion.cs.uiuc.edu>



Changes in directory llvm/lib/Target/PowerPC:

PPC32ISelPattern.cpp updated: 1.156 -> 1.157
---
Log message:

If the false value for a select_cc is really simple (has no inputs), evaluate
it in the block.  This codegens:

int %test(bool %c) {
        %retval = select bool %c, int 17, int 1 
        ret int %retval
}

as:

_test:
        rlwinm r2, r3, 0, 31, 31
        li r2, 17
        cmpwi cr0, r3, 0
        bne .LBB_test_2 ; 
.LBB_test_1:    ; 
        li r2, 1
.LBB_test_2:    ; 
        or r3, r2, r2
        blr

instead of:

_test:
        rlwinm r2, r3, 0, 31, 31
        li r2, 17
        li r4, 1
        cmpwi cr0, r3, 0
        bne .LBB_test_2 ; 
.LBB_test_1:    ; 
        or r2, r4, r4
.LBB_test_2:    ; 
        or r3, r2, r2
        blr

... which is one fewer instruction.  The savings are more significant for 
global address and constantfp nodes.



---
Diffs of the changes:  (+16 -1)

 PPC32ISelPattern.cpp |   17 ++++++++++++++++-
 1 files changed, 16 insertions(+), 1 deletion(-)


Index: llvm/lib/Target/PowerPC/PPC32ISelPattern.cpp
diff -u llvm/lib/Target/PowerPC/PPC32ISelPattern.cpp:1.156 llvm/lib/Target/PowerPC/PPC32ISelPattern.cpp:1.157
--- llvm/lib/Target/PowerPC/PPC32ISelPattern.cpp:1.156	Thu Aug 18 22:42:28 2005
+++ llvm/lib/Target/PowerPC/PPC32ISelPattern.cpp	Sun Aug 21 12:41:11 2005
@@ -1675,7 +1675,16 @@
     // selecting it in the fallthrough basic block rather than here, which
     // increases register pressure.
     unsigned TrueValue = SelectExpr(N.getOperand(2));
-    unsigned FalseValue = SelectExpr(N.getOperand(3));
+    unsigned FalseValue;
+
+    // If the false value is simple enough, evaluate it inline in the false
+    // block.
+    if (isa<ConstantSDNode>(N.getOperand(3)) ||
+        isa<ConstantFPSDNode>(N.getOperand(3)) ||
+        isa<GlobalAddressSDNode>(N.getOperand(3)))
+      FalseValue = 0;
+    else
+      FalseValue = SelectExpr(N.getOperand(3));
     unsigned CCReg = SelectCC(N.getOperand(0), N.getOperand(1), CC);
     Opc = getBCCForSetCC(CC);
     
@@ -1706,6 +1715,12 @@
     //   %FalseValue = ...
     //   # fallthrough to sinkMBB
     BB = copy0MBB;
+
+    // If the false value is simple enough, evaluate it here, to avoid it being
+    // evaluated on the true edge.
+    if (FalseValue == 0)
+      FalseValue = SelectExpr(N.getOperand(3));
+
     // Update machine-CFG edges
     BB->addSuccessor(sinkMBB);
 





From lattner at cs.uiuc.edu  Sun Aug 21 13:03:21 2005
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Sun, 21 Aug 2005 13:03:21 -0500
Subject: [llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp 
Message-ID: <200508211803.NAA08218@zion.cs.uiuc.edu>



Changes in directory llvm/lib/CodeGen/SelectionDAG:

LegalizeDAG.cpp updated: 1.167 -> 1.168
---
Log message:

When legalizing brcond ->brcc or select -> selectcc, make sure to truncate
the old condition to a one bit value.  The incoming value must have been
promoted, and the top bits are undefined.  This causes us to generate:

_test:
        rlwinm r2, r3, 0, 31, 31
        li r3, 17
        cmpwi cr0, r2, 0
        bne .LBB_test_2 ; 
.LBB_test_1:    ; 
        li r3, 1
.LBB_test_2:    ; 
        blr

instead of:

_test:
        rlwinm r2, r3, 0, 31, 31
        li r2, 17
        cmpwi cr0, r3, 0
        bne .LBB_test_2 ; 
.LBB_test_1:    ; 
        li r2, 1
.LBB_test_2:    ; 
        or r3, r2, r2
        blr

for:

int %test(bool %c) {
        %retval = select bool %c, int 17, int 1 
        ret int %retval
}



---
Diffs of the changes:  (+7 -0)

 LegalizeDAG.cpp |    7 +++++++
 1 files changed, 7 insertions(+)


Index: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.167 llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.168
--- llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.167	Wed Aug 17 14:27:23 2005
+++ llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp	Sun Aug 21 13:03:09 2005
@@ -681,6 +681,10 @@
                              Tmp2.getOperand(0), Tmp2.getOperand(1),
                              Node->getOperand(2));
       } else {
+        // Make sure the condition is either zero or one.  It may have been
+        // promoted from something else.
+        Tmp2 = DAG.getZeroExtendInReg(Tmp2, MVT::i1);
+        
         Result = DAG.getNode(ISD::BR_CC, MVT::Other, Tmp1, 
                              DAG.getCondCode(ISD::SETNE), Tmp2,
                              DAG.getConstant(0, Tmp2.getValueType()),
@@ -1072,6 +1076,9 @@
                               Tmp2, Tmp3,
                               cast<CondCodeSDNode>(Tmp1.getOperand(2))->get());
       } else {
+        // Make sure the condition is either zero or one.  It may have been
+        // promoted from something else.
+        Tmp1 = DAG.getZeroExtendInReg(Tmp1, MVT::i1);
         Result = DAG.getSelectCC(Tmp1, 
                                  DAG.getConstant(0, Tmp1.getValueType()),
                                  Tmp2, Tmp3, ISD::SETNE);





From lattner at cs.uiuc.edu  Sun Aug 21 13:49:40 2005
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Sun, 21 Aug 2005 13:49:40 -0500
Subject: [llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp 
Message-ID: <200508211849.NAA10606@zion.cs.uiuc.edu>



Changes in directory llvm/lib/CodeGen/SelectionDAG:

ScheduleDAG.cpp updated: 1.9 -> 1.10
---
Log message:

Add support for basic blocks, fix a bug in result # computation


---
Diffs of the changes:  (+7 -2)

 ScheduleDAG.cpp |    9 +++++++--
 1 files changed, 7 insertions(+), 2 deletions(-)


Index: llvm/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp:1.9 llvm/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp:1.10
--- llvm/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp:1.9	Sat Aug 20 13:07:27 2005
+++ llvm/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp	Sun Aug 21 13:49:29 2005
@@ -80,7 +80,7 @@
     // nodes.  Check that the DAG matches the TD files's expectation of #
     // operands.
     unsigned NumResults = Op.Val->getNumValues();
-    if (NumResults && Op.getOperand(NumResults-1).getValueType() == MVT::Other)
+    if (NumResults && Op.Val->getValueType(NumResults-1) == MVT::Other)
       --NumResults;
 #ifndef _NDEBUG
     unsigned Operands = Op.getNumOperands();
@@ -118,6 +118,9 @@
       } else if (GlobalAddressSDNode *TGA =
                        dyn_cast<GlobalAddressSDNode>(Op.getOperand(i))) {
         MI->addGlobalAddressOperand(TGA->getGlobal(), false, 0);
+      } else if (BasicBlockSDNode *BB =
+                       dyn_cast<BasicBlockSDNode>(Op.getOperand(i))) {
+        MI->addMachineBasicBlockOperand(BB->getBasicBlock());
       } else {
         unsigned R = Emit(Op.getOperand(i));
         // Add an operand, unless this corresponds to a chain node.
@@ -133,7 +136,9 @@
     default:
       Op.Val->dump(); 
       assert(0 && "This target-independent node should have been selected!");
-    case ISD::EntryToken: break;
+    case ISD::EntryToken:
+    case ISD::BasicBlock:
+      break;
     case ISD::TokenFactor:
       for (unsigned i = 0, e = Op.getNumOperands(); i != e; ++i)
         Emit(Op.getOperand(i));





From lattner at cs.uiuc.edu  Sun Aug 21 13:49:45 2005
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Sun, 21 Aug 2005 13:49:45 -0500
Subject: [llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp 
Message-ID: <200508211849.NAA10616@zion.cs.uiuc.edu>



Changes in directory llvm/lib/CodeGen/SelectionDAG:

SelectionDAG.cpp updated: 1.153 -> 1.154
---
Log message:

add a method


---
Diffs of the changes:  (+9 -0)

 SelectionDAG.cpp |    9 +++++++++
 1 files changed, 9 insertions(+)


Index: llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp:1.153 llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp:1.154
--- llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp:1.153	Fri Aug 19 17:31:04 2005
+++ llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp	Sun Aug 21 13:49:33 2005
@@ -1831,6 +1831,15 @@
   N->setValueTypes(VT);
   N->setOperands(Op1, Op2, Op3, Op4);
 }
+void SelectionDAG::SelectNodeTo(SDNode *N, MVT::ValueType VT,
+                                unsigned TargetOpc, SDOperand Op1,
+                                SDOperand Op2, SDOperand Op3, SDOperand Op4,
+                                SDOperand Op5) {
+  RemoveNodeFromCSEMaps(N);
+  N->MorphNodeTo(ISD::BUILTIN_OP_END+TargetOpc);
+  N->setValueTypes(VT);
+  N->setOperands(Op1, Op2, Op3, Op4, Op5);
+}
 
 /// ReplaceAllUsesWith - Modify anything using 'From' to use 'To' instead.
 /// This can cause recursive merging of nodes in the DAG.





From lattner at cs.uiuc.edu  Sun Aug 21 13:50:10 2005
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Sun, 21 Aug 2005 13:50:10 -0500
Subject: [llvm-commits] CVS: llvm/include/llvm/CodeGen/SelectionDAG.h
	SelectionDAGNodes.h 
Message-ID: <200508211850.NAA10637@zion.cs.uiuc.edu>



Changes in directory llvm/include/llvm/CodeGen:

SelectionDAG.h updated: 1.44 -> 1.45
SelectionDAGNodes.h updated: 1.59 -> 1.60
---
Log message:

Add 5-operand version of SelectNodeTo


---
Diffs of the changes:  (+15 -0)

 SelectionDAG.h      |    3 +++
 SelectionDAGNodes.h |   12 ++++++++++++
 2 files changed, 15 insertions(+)


Index: llvm/include/llvm/CodeGen/SelectionDAG.h
diff -u llvm/include/llvm/CodeGen/SelectionDAG.h:1.44 llvm/include/llvm/CodeGen/SelectionDAG.h:1.45
--- llvm/include/llvm/CodeGen/SelectionDAG.h:1.44	Fri Aug 19 17:31:34 2005
+++ llvm/include/llvm/CodeGen/SelectionDAG.h	Sun Aug 21 13:49:58 2005
@@ -229,6 +229,9 @@
                     SDOperand Op1, SDOperand Op2, SDOperand Op3);
   void SelectNodeTo(SDNode *N, MVT::ValueType VT, unsigned TargetOpc,
                     SDOperand Op1, SDOperand Op2, SDOperand Op3, SDOperand Op4);
+  void SelectNodeTo(SDNode *N, MVT::ValueType VT, unsigned TargetOpc,
+                    SDOperand Op1, SDOperand Op2, SDOperand Op3, SDOperand Op4,
+                    SDOperand Op5);
   
   SDOperand getTargetNode(unsigned Opcode, MVT::ValueType VT,
                           SDOperand Op1) {


Index: llvm/include/llvm/CodeGen/SelectionDAGNodes.h
diff -u llvm/include/llvm/CodeGen/SelectionDAGNodes.h:1.59 llvm/include/llvm/CodeGen/SelectionDAGNodes.h:1.60
--- llvm/include/llvm/CodeGen/SelectionDAGNodes.h:1.59	Fri Aug 19 17:31:34 2005
+++ llvm/include/llvm/CodeGen/SelectionDAGNodes.h	Sun Aug 21 13:49:58 2005
@@ -678,6 +678,18 @@
     Op0.Val->Uses.push_back(this); Op1.Val->Uses.push_back(this);
     Op2.Val->Uses.push_back(this); Op3.Val->Uses.push_back(this);
   }
+  void setOperands(SDOperand Op0, SDOperand Op1, SDOperand Op2, SDOperand Op3,
+                   SDOperand Op4) {
+    Operands.reserve(5);
+    Operands.push_back(Op0);
+    Operands.push_back(Op1);
+    Operands.push_back(Op2);
+    Operands.push_back(Op3);
+    Operands.push_back(Op4);
+    Op0.Val->Uses.push_back(this); Op1.Val->Uses.push_back(this);
+    Op2.Val->Uses.push_back(this); Op3.Val->Uses.push_back(this);
+    Op4.Val->Uses.push_back(this);
+  }
   void addUser(SDNode *User) {
     Uses.push_back(User);
   }





From lattner at cs.uiuc.edu  Sun Aug 21 13:50:49 2005
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Sun, 21 Aug 2005 13:50:49 -0500
Subject: [llvm-commits] CVS: llvm/lib/Target/PowerPC/PPC32ISelDAGToDAG.cpp 
Message-ID: <200508211850.NAA10649@zion.cs.uiuc.edu>



Changes in directory llvm/lib/Target/PowerPC:

PPC32ISelDAGToDAG.cpp updated: 1.16 -> 1.17
---
Log message:

Implement selection for branches.  




---
Diffs of the changes:  (+83 -0)

 PPC32ISelDAGToDAG.cpp |   83 ++++++++++++++++++++++++++++++++++++++++++++++++++
 1 files changed, 83 insertions(+)


Index: llvm/lib/Target/PowerPC/PPC32ISelDAGToDAG.cpp
diff -u llvm/lib/Target/PowerPC/PPC32ISelDAGToDAG.cpp:1.16 llvm/lib/Target/PowerPC/PPC32ISelDAGToDAG.cpp:1.17
--- llvm/lib/Target/PowerPC/PPC32ISelDAGToDAG.cpp:1.16	Fri Aug 19 17:38:53 2005
+++ llvm/lib/Target/PowerPC/PPC32ISelDAGToDAG.cpp	Sun Aug 21 13:50:37 2005
@@ -69,6 +69,10 @@
                                    bool Negate = false);
     SDNode *SelectBitfieldInsert(SDNode *N);
 
+    /// SelectCC - Select a comparison of the specified values with the
+    /// specified condition code, returning the CR# of the expression.
+    SDOperand SelectCC(SDOperand LHS, SDOperand RHS, ISD::CondCode CC);
+
     /// InstructionSelectBasicBlock - This callback is invoked by
     /// SelectionDAGISel when it has created a SelectionDAG for us to codegen.
     virtual void InstructionSelectBasicBlock(SelectionDAG &DAG) {
@@ -353,6 +357,47 @@
 }
 
 
+/// SelectCC - Select a comparison of the specified values with the specified
+/// condition code, returning the CR# of the expression.
+SDOperand PPC32DAGToDAGISel::SelectCC(SDOperand LHS, SDOperand RHS,
+                                      ISD::CondCode CC) {
+  // Always select the LHS.
+  LHS = Select(LHS);
+
+  // Use U to determine whether the SETCC immediate range is signed or not.
+  if (MVT::isInteger(LHS.getValueType())) {
+    bool U = ISD::isUnsignedIntSetCC(CC);
+    unsigned Imm;
+    if (isIntImmediate(RHS, Imm) && 
+        ((U && isUInt16(Imm)) || (!U && isInt16(Imm))))
+      return CurDAG->getTargetNode(U ? PPC::CMPLWI : PPC::CMPWI, MVT::i32,
+                                   LHS, getI32Imm(Lo16(Imm)));
+    return CurDAG->getTargetNode(U ? PPC::CMPLW : PPC::CMPW, MVT::i32,
+                                 LHS, Select(RHS));
+  } else {
+    return CurDAG->getTargetNode(PPC::FCMPU, MVT::i32, LHS, Select(RHS));
+  }
+}
+
+/// getBCCForSetCC - Returns the PowerPC condition branch mnemonic corresponding
+/// to Condition.
+static unsigned getBCCForSetCC(ISD::CondCode CC) {
+  switch (CC) {
+  default: assert(0 && "Unknown condition!"); abort();
+  case ISD::SETEQ:  return PPC::BEQ;
+  case ISD::SETNE:  return PPC::BNE;
+  case ISD::SETULT:
+  case ISD::SETLT:  return PPC::BLT;
+  case ISD::SETULE:
+  case ISD::SETLE:  return PPC::BLE;
+  case ISD::SETUGT:
+  case ISD::SETGT:  return PPC::BGT;
+  case ISD::SETUGE:
+  case ISD::SETGE:  return PPC::BGE;
+  }
+  return 0;
+}
+
 // Select - Convert the specified operand from a target-independent to a
 // target-specific node if it hasn't already been changed.
 SDOperand PPC32DAGToDAGISel::Select(SDOperand Op) {
@@ -790,6 +835,44 @@
     CurDAG->SelectNodeTo(N, MVT::Other, PPC::BLR, Chain);
     break;
   }
+
+  case ISD::BR_CC:
+  case ISD::BRTWOWAY_CC: {
+    SDOperand Chain = Select(N->getOperand(0));
+    MachineBasicBlock *Dest =
+      cast<BasicBlockSDNode>(N->getOperand(4))->getBasicBlock();
+    ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(1))->get();
+    SDOperand CondCode = SelectCC(N->getOperand(2), N->getOperand(3), CC);
+    unsigned Opc = getBCCForSetCC(CC);
+
+    // If this is a two way branch, then grab the fallthrough basic block
+    // argument and build a PowerPC branch pseudo-op, suitable for long branch
+    // conversion if necessary by the branch selection pass.  Otherwise, emit a
+    // standard conditional branch.
+    if (N->getOpcode() == ISD::BRTWOWAY_CC) {
+      MachineBasicBlock *Fallthrough =
+        cast<BasicBlockSDNode>(N->getOperand(5))->getBasicBlock();
+      SDOperand CB = CurDAG->getTargetNode(PPC::COND_BRANCH, MVT::Other,
+                                           CondCode, getI32Imm(Opc),
+                                           N->getOperand(4), N->getOperand(5),
+                                           Chain);
+      CurDAG->SelectNodeTo(N, MVT::Other, PPC::B, N->getOperand(5), CB);
+    } else {
+      // Iterate to the next basic block
+      ilist<MachineBasicBlock>::iterator It = BB;
+      ++It;
+
+      // If the fallthrough path is off the end of the function, which would be
+      // undefined behavior, set it to be the same as the current block because
+      // we have nothing better to set it to, and leaving it alone will cause
+      // the PowerPC Branch Selection pass to crash.
+      if (It == BB->getParent()->end()) It = Dest;
+      CurDAG->SelectNodeTo(N, MVT::Other, PPC::COND_BRANCH, CondCode,
+                           getI32Imm(Opc), N->getOperand(4),
+                           CurDAG->getBasicBlock(It), Chain);
+    }
+    break;
+  }
   }
   return SDOperand(N, 0);
 }





From lattner at cs.uiuc.edu  Sun Aug 21 14:03:39 2005
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Sun, 21 Aug 2005 14:03:39 -0500
Subject: [llvm-commits] CVS: llvm/lib/Target/PowerPC/PPC32ISelPattern.cpp 
Message-ID: <200508211903.OAA11100@zion.cs.uiuc.edu>



Changes in directory llvm/lib/Target/PowerPC:

PPC32ISelPattern.cpp updated: 1.157 -> 1.158
---
Log message:

Simplify the logic for BRTWOWAY_CC handling.  The isel code already
simplifies BRTWOWAY into BR if one of the results is a fall-through.
Unless I'm missing something, there is no reason to duplicate this
in the target-specific code.


---
Diffs of the changes:  (+7 -16)

 PPC32ISelPattern.cpp |   23 +++++++----------------
 1 files changed, 7 insertions(+), 16 deletions(-)


Index: llvm/lib/Target/PowerPC/PPC32ISelPattern.cpp
diff -u llvm/lib/Target/PowerPC/PPC32ISelPattern.cpp:1.157 llvm/lib/Target/PowerPC/PPC32ISelPattern.cpp:1.158
--- llvm/lib/Target/PowerPC/PPC32ISelPattern.cpp:1.157	Sun Aug 21 12:41:11 2005
+++ llvm/lib/Target/PowerPC/PPC32ISelPattern.cpp	Sun Aug 21 14:03:28 2005
@@ -707,10 +707,6 @@
   unsigned CCReg = SelectCC(N.getOperand(2), N.getOperand(3), CC);
   unsigned Opc = getBCCForSetCC(CC);
 
-  // Iterate to the next basic block
-  ilist<MachineBasicBlock>::iterator It = BB;
-  ++It;
-
   // If this is a two way branch, then grab the fallthrough basic block argument
   // and build a PowerPC branch pseudo-op, suitable for long branch conversion
   // if necessary by the branch selection pass.  Otherwise, emit a standard
@@ -718,19 +714,14 @@
   if (N.getOpcode() == ISD::BRTWOWAY_CC) {
     MachineBasicBlock *Fallthrough =
       cast<BasicBlockSDNode>(N.getOperand(5))->getBasicBlock();
-    if (Dest != It) {
-      BuildMI(BB, PPC::COND_BRANCH, 4).addReg(CCReg).addImm(Opc)
-        .addMBB(Dest).addMBB(Fallthrough);
-      if (Fallthrough != It)
-        BuildMI(BB, PPC::B, 1).addMBB(Fallthrough);
-    } else {
-      if (Fallthrough != It) {
-        Opc = PPC32InstrInfo::invertPPCBranchOpcode(Opc);
-        BuildMI(BB, PPC::COND_BRANCH, 4).addReg(CCReg).addImm(Opc)
-          .addMBB(Fallthrough).addMBB(Dest);
-      }
-    }
+    BuildMI(BB, PPC::COND_BRANCH, 4).addReg(CCReg).addImm(Opc)
+      .addMBB(Dest).addMBB(Fallthrough);
+    BuildMI(BB, PPC::B, 1).addMBB(Fallthrough);
   } else {
+    // Iterate to the next basic block
+    ilist<MachineBasicBlock>::iterator It = BB;
+    ++It;
+
     // If the fallthrough path is off the end of the function, which would be
     // undefined behavior, set it to be the same as the current block because
     // we have nothing better to set it to, and leaving it alone will cause the





From lattner at cs.uiuc.edu  Sun Aug 21 14:09:44 2005
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Sun, 21 Aug 2005 14:09:44 -0500
Subject: [llvm-commits] CVS: llvm/lib/Target/PowerPC/PowerPCAsmPrinter.cpp 
Message-ID: <200508211909.OAA11803@zion.cs.uiuc.edu>



Changes in directory llvm/lib/Target/PowerPC:

PowerPCAsmPrinter.cpp updated: 1.86 -> 1.87
---
Log message:

Don't print out the MBB label for the entry mbb


---
Diffs of the changes:  (+6 -2)

 PowerPCAsmPrinter.cpp |    8 ++++++--
 1 files changed, 6 insertions(+), 2 deletions(-)


Index: llvm/lib/Target/PowerPC/PowerPCAsmPrinter.cpp
diff -u llvm/lib/Target/PowerPC/PowerPCAsmPrinter.cpp:1.86 llvm/lib/Target/PowerPC/PowerPCAsmPrinter.cpp:1.87
--- llvm/lib/Target/PowerPC/PowerPCAsmPrinter.cpp:1.86	Fri Aug  5 17:05:03 2005
+++ llvm/lib/Target/PowerPC/PowerPCAsmPrinter.cpp	Sun Aug 21 14:09:33 2005
@@ -400,8 +400,12 @@
   for (MachineFunction::const_iterator I = MF.begin(), E = MF.end();
        I != E; ++I) {
     // Print a label for the basic block.
-    O << ".LBB" << CurrentFnName << "_" << I->getNumber() << ":\t"
-      << CommentString << " " << I->getBasicBlock()->getName() << "\n";
+    if (I != MF.begin()) {
+      O << ".LBB" << CurrentFnName << "_" << I->getNumber() << ":\t";
+      if (!I->getBasicBlock()->getName().empty())
+        O << CommentString << " " << I->getBasicBlock()->getName();
+      O << "\n";
+    }
     for (MachineBasicBlock::const_iterator II = I->begin(), E = I->end();
          II != E; ++II) {
       // Print the assembly for the instruction.





From lattner at cs.uiuc.edu  Sun Aug 21 14:49:04 2005
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Sun, 21 Aug 2005 14:49:04 -0500
Subject: [llvm-commits] CVS: llvm/include/llvm/CodeGen/SelectionDAG.h 
Message-ID: <200508211949.OAA12845@zion.cs.uiuc.edu>



Changes in directory llvm/include/llvm/CodeGen:

SelectionDAG.h updated: 1.45 -> 1.46
---
Log message:

ADd a method


---
Diffs of the changes:  (+2 -0)

 SelectionDAG.h |    2 ++
 1 files changed, 2 insertions(+)


Index: llvm/include/llvm/CodeGen/SelectionDAG.h
diff -u llvm/include/llvm/CodeGen/SelectionDAG.h:1.45 llvm/include/llvm/CodeGen/SelectionDAG.h:1.46
--- llvm/include/llvm/CodeGen/SelectionDAG.h:1.45	Sun Aug 21 13:49:58 2005
+++ llvm/include/llvm/CodeGen/SelectionDAG.h	Sun Aug 21 14:48:53 2005
@@ -232,6 +232,8 @@
   void SelectNodeTo(SDNode *N, MVT::ValueType VT, unsigned TargetOpc,
                     SDOperand Op1, SDOperand Op2, SDOperand Op3, SDOperand Op4,
                     SDOperand Op5);
+  void SelectNodeTo(SDNode *N, MVT::ValueType VT1, MVT::ValueType VT2,
+                    unsigned TargetOpc, SDOperand Op1, SDOperand Op2);
   
   SDOperand getTargetNode(unsigned Opcode, MVT::ValueType VT,
                           SDOperand Op1) {





From lattner at cs.uiuc.edu  Sun Aug 21 14:49:10 2005
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Sun, 21 Aug 2005 14:49:10 -0500
Subject: [llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp 
Message-ID: <200508211949.OAA12852@zion.cs.uiuc.edu>



Changes in directory llvm/lib/CodeGen/SelectionDAG:

SelectionDAG.cpp updated: 1.154 -> 1.155
---
Log message:

add a method


---
Diffs of the changes:  (+9 -0)

 SelectionDAG.cpp |    9 +++++++++
 1 files changed, 9 insertions(+)


Index: llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp:1.154 llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp:1.155
--- llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp:1.154	Sun Aug 21 13:49:33 2005
+++ llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp	Sun Aug 21 14:48:59 2005
@@ -1815,6 +1815,15 @@
   N->setValueTypes(VT);
   N->setOperands(Op1, Op2);
 }
+void SelectionDAG::SelectNodeTo(SDNode *N,
+                                MVT::ValueType VT1, MVT::ValueType VT2,
+                                unsigned TargetOpc, SDOperand Op1,
+                                SDOperand Op2) {
+  RemoveNodeFromCSEMaps(N);
+  N->MorphNodeTo(ISD::BUILTIN_OP_END+TargetOpc);
+  N->setValueTypes(VT1, VT2);
+  N->setOperands(Op1, Op2);
+}
 void SelectionDAG::SelectNodeTo(SDNode *N, MVT::ValueType VT,
                                 unsigned TargetOpc, SDOperand Op1,
                                 SDOperand Op2, SDOperand Op3) {





From lattner at cs.uiuc.edu  Sun Aug 21 14:56:16 2005
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Sun, 21 Aug 2005 14:56:16 -0500
Subject: [llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp 
Message-ID: <200508211956.OAA13870@zion.cs.uiuc.edu>



Changes in directory llvm/lib/CodeGen/SelectionDAG:

ScheduleDAG.cpp updated: 1.10 -> 1.11
---
Log message:

Add support for frame index nodes


---
Diffs of the changes:  (+4 -3)

 ScheduleDAG.cpp |    7 ++++---
 1 files changed, 4 insertions(+), 3 deletions(-)


Index: llvm/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp:1.10 llvm/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp:1.11
--- llvm/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp:1.10	Sun Aug 21 13:49:29 2005
+++ llvm/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp	Sun Aug 21 14:56:04 2005
@@ -121,6 +121,9 @@
       } else if (BasicBlockSDNode *BB =
                        dyn_cast<BasicBlockSDNode>(Op.getOperand(i))) {
         MI->addMachineBasicBlockOperand(BB->getBasicBlock());
+      } else if (FrameIndexSDNode *FI =
+                       dyn_cast<FrameIndexSDNode>(Op.getOperand(i))) {
+        MI->addFrameIndexOperand(FI->getIndex());
       } else {
         unsigned R = Emit(Op.getOperand(i));
         // Add an operand, unless this corresponds to a chain node.
@@ -136,9 +139,7 @@
     default:
       Op.Val->dump(); 
       assert(0 && "This target-independent node should have been selected!");
-    case ISD::EntryToken:
-    case ISD::BasicBlock:
-      break;
+    case ISD::EntryToken: break;
     case ISD::TokenFactor:
       for (unsigned i = 0, e = Op.getNumOperands(); i != e; ++i)
         Emit(Op.getOperand(i));





From lattner at cs.uiuc.edu  Sun Aug 21 17:30:41 2005
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Sun, 21 Aug 2005 17:30:41 -0500
Subject: [llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp 
Message-ID: <200508212230.RAA16273@zion.cs.uiuc.edu>



Changes in directory llvm/lib/CodeGen/SelectionDAG:

SelectionDAG.cpp updated: 1.155 -> 1.156
---
Log message:

add anew method


---
Diffs of the changes:  (+10 -0)

 SelectionDAG.cpp |   10 ++++++++++
 1 files changed, 10 insertions(+)


Index: llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp:1.155 llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp:1.156
--- llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp:1.155	Sun Aug 21 14:48:59 2005
+++ llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp	Sun Aug 21 17:30:30 2005
@@ -1832,6 +1832,16 @@
   N->setValueTypes(VT);
   N->setOperands(Op1, Op2, Op3);
 }
+void SelectionDAG::SelectNodeTo(SDNode *N, MVT::ValueType VT1,
+                                MVT::ValueType VT2,
+                                unsigned TargetOpc, SDOperand Op1,
+                                SDOperand Op2, SDOperand Op3) {
+  RemoveNodeFromCSEMaps(N);
+  N->MorphNodeTo(ISD::BUILTIN_OP_END+TargetOpc);
+  N->setValueTypes(VT1, VT2);
+  N->setOperands(Op1, Op2, Op3);
+}
+
 void SelectionDAG::SelectNodeTo(SDNode *N, MVT::ValueType VT,
                                 unsigned TargetOpc, SDOperand Op1,
                                 SDOperand Op2, SDOperand Op3, SDOperand Op4) {





From lattner at cs.uiuc.edu  Sun Aug 21 17:30:53 2005
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Sun, 21 Aug 2005 17:30:53 -0500
Subject: [llvm-commits] CVS: llvm/include/llvm/CodeGen/SelectionDAG.h 
Message-ID: <200508212230.RAA16283@zion.cs.uiuc.edu>



Changes in directory llvm/include/llvm/CodeGen:

SelectionDAG.h updated: 1.46 -> 1.47
---
Log message:

add a method


---
Diffs of the changes:  (+3 -0)

 SelectionDAG.h |    3 +++
 1 files changed, 3 insertions(+)


Index: llvm/include/llvm/CodeGen/SelectionDAG.h
diff -u llvm/include/llvm/CodeGen/SelectionDAG.h:1.46 llvm/include/llvm/CodeGen/SelectionDAG.h:1.47
--- llvm/include/llvm/CodeGen/SelectionDAG.h:1.46	Sun Aug 21 14:48:53 2005
+++ llvm/include/llvm/CodeGen/SelectionDAG.h	Sun Aug 21 17:30:42 2005
@@ -234,6 +234,9 @@
                     SDOperand Op5);
   void SelectNodeTo(SDNode *N, MVT::ValueType VT1, MVT::ValueType VT2,
                     unsigned TargetOpc, SDOperand Op1, SDOperand Op2);
+  void SelectNodeTo(SDNode *N, MVT::ValueType VT1, MVT::ValueType VT2,
+                    unsigned TargetOpc, SDOperand Op1, SDOperand Op2,
+                    SDOperand Op3);
   
   SDOperand getTargetNode(unsigned Opcode, MVT::ValueType VT,
                           SDOperand Op1) {





From lattner at cs.uiuc.edu  Sun Aug 21 17:31:20 2005
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Sun, 21 Aug 2005 17:31:20 -0500
Subject: [llvm-commits] CVS: llvm/lib/Target/PowerPC/PPC32ISelDAGToDAG.cpp 
Message-ID: <200508212231.RAA16296@zion.cs.uiuc.edu>



Changes in directory llvm/lib/Target/PowerPC:

PPC32ISelDAGToDAG.cpp updated: 1.17 -> 1.18
---
Log message:

Implement most of load support.  There is still a bug though.


---
Diffs of the changes:  (+96 -8)

 PPC32ISelDAGToDAG.cpp |  104 ++++++++++++++++++++++++++++++++++++++++++++++----
 1 files changed, 96 insertions(+), 8 deletions(-)


Index: llvm/lib/Target/PowerPC/PPC32ISelDAGToDAG.cpp
diff -u llvm/lib/Target/PowerPC/PPC32ISelDAGToDAG.cpp:1.17 llvm/lib/Target/PowerPC/PPC32ISelDAGToDAG.cpp:1.18
--- llvm/lib/Target/PowerPC/PPC32ISelDAGToDAG.cpp:1.17	Sun Aug 21 13:50:37 2005
+++ llvm/lib/Target/PowerPC/PPC32ISelDAGToDAG.cpp	Sun Aug 21 17:31:09 2005
@@ -57,7 +57,7 @@
 
     /// getGlobalBaseReg - insert code into the entry mbb to materialize the PIC
     /// base register.  Return the virtual register that holds this value.
-    unsigned getGlobalBaseReg();
+    SDOperand getGlobalBaseReg();
     
     // Select - Convert the specified operand from a target-independent to a
     // target-specific node if it hasn't already been changed.
@@ -73,6 +73,11 @@
     /// specified condition code, returning the CR# of the expression.
     SDOperand SelectCC(SDOperand LHS, SDOperand RHS, ISD::CondCode CC);
 
+    /// SelectAddr - Given the specified address, return the two operands for a
+    /// load/store instruction, and return true if it should be an indexed [r+r]
+    /// operation.
+    bool SelectAddr(SDOperand Addr, SDOperand &Op1, SDOperand &Op2);
+
     /// InstructionSelectBasicBlock - This callback is invoked by
     /// SelectionDAGISel when it has created a SelectionDAG for us to codegen.
     virtual void InstructionSelectBasicBlock(SelectionDAG &DAG) {
@@ -94,7 +99,7 @@
 /// getGlobalBaseReg - Output the instructions required to put the
 /// base address to use for accessing globals into a register.
 ///
-unsigned PPC32DAGToDAGISel::getGlobalBaseReg() {
+SDOperand PPC32DAGToDAGISel::getGlobalBaseReg() {
   if (!GlobalBaseReg) {
     // Insert the set of GlobalBaseReg into the first MBB of the function
     MachineBasicBlock &FirstMBB = BB->getParent()->front();
@@ -104,7 +109,7 @@
     BuildMI(FirstMBB, MBBI, PPC::MovePCtoLR, 0, PPC::LR);
     BuildMI(FirstMBB, MBBI, PPC::MFLR, 1, GlobalBaseReg);
   }
-  return GlobalBaseReg;
+  return CurDAG->getRegister(GlobalBaseReg, MVT::i32);
 }
 
 
@@ -356,6 +361,58 @@
   return Opr0.Val;
 }
 
+/// SelectAddr - Given the specified address, return the two operands for a
+/// load/store instruction, and return true if it should be an indexed [r+r]
+/// operation.
+bool PPC32DAGToDAGISel::SelectAddr(SDOperand Addr, SDOperand &Op1,
+                                   SDOperand &Op2) {
+  unsigned imm = 0;
+  if (Addr.getOpcode() == ISD::ADD) {
+    if (isIntImmediate(Addr.getOperand(1), imm) && isInt16(imm)) {
+      Op1 = getI32Imm(Lo16(imm));
+      if (isa<FrameIndexSDNode>(Addr.getOperand(0))) {
+        ++FrameOff;
+        Op2 = Addr.getOperand(0);
+      } else {
+        Op2 = Select(Addr.getOperand(0));
+      }
+      return false;
+    } else {
+      Op1 = Select(Addr.getOperand(0));
+      Op2 = Select(Addr.getOperand(1));
+      return true;   // [r+r]
+    }
+  }
+
+  // Now check if we're dealing with a global, and whether or not we should emit
+  // an optimized load or store for statics.
+  if (GlobalAddressSDNode *GN = dyn_cast<GlobalAddressSDNode>(Addr)) {
+    GlobalValue *GV = GN->getGlobal();
+    if (!GV->hasWeakLinkage() && !GV->isExternal()) {
+      Op1 = CurDAG->getTargetGlobalAddress(GV, MVT::i32);
+      if (PICEnabled)
+        Op2 = CurDAG->getTargetNode(PPC::ADDIS, MVT::i32, getGlobalBaseReg(),
+                                    Op1);
+      else
+        Op2 = CurDAG->getTargetNode(PPC::LIS, MVT::i32, Op1);
+      return false;
+    }
+  } else if (isa<FrameIndexSDNode>(Addr)) {
+    Op1 = getI32Imm(0);
+    Op2 = Addr;
+    return false;
+  } else if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(Addr)) {
+    Op1 = Addr;
+    if (PICEnabled)
+      Op2 = CurDAG->getTargetNode(PPC::ADDIS, MVT::i32, getGlobalBaseReg(),Op1);
+    else
+      Op2 = CurDAG->getTargetNode(PPC::LIS, MVT::i32, Op1);
+    return false;
+  }
+  Op1 = getI32Imm(0);
+  Op2 = Select(Addr);
+  return false;
+}
 
 /// SelectCC - Select a comparison of the specified values with the specified
 /// condition code, returning the CR# of the expression.
@@ -398,6 +455,7 @@
   return 0;
 }
 
+
 // Select - Convert the specified operand from a target-independent to a
 // target-specific node if it hasn't already been changed.
 SDOperand PPC32DAGToDAGISel::Select(SDOperand Op) {
@@ -472,12 +530,11 @@
     GlobalValue *GV = cast<GlobalAddressSDNode>(N)->getGlobal();
     SDOperand Tmp;
     SDOperand GA = CurDAG->getTargetGlobalAddress(GV, MVT::i32);
-    if (PICEnabled) {
-      SDOperand PICBaseReg = CurDAG->getRegister(getGlobalBaseReg(), MVT::i32);
-      Tmp = CurDAG->getTargetNode(PPC::ADDIS, MVT::i32, PICBaseReg, GA);
-    } else {
+    if (PICEnabled)
+      Tmp = CurDAG->getTargetNode(PPC::ADDIS, MVT::i32, getGlobalBaseReg(), GA);
+    else
       Tmp = CurDAG->getTargetNode(PPC::LIS, MVT::i32, GA);
-    }
+
     if (GV->hasWeakLinkage() || GV->isExternal())
       CurDAG->SelectNodeTo(N, MVT::i32, PPC::LWZ, GA, Tmp);
     else
@@ -806,6 +863,37 @@
                          Select(N->getOperand(0)));
     break;
   }
+  case ISD::LOAD:
+  case ISD::EXTLOAD:
+  case ISD::ZEXTLOAD:
+  case ISD::SEXTLOAD: {
+    SDOperand Op1, Op2;
+    bool isIdx = SelectAddr(N->getOperand(1), Op1, Op2);
+
+    MVT::ValueType TypeBeingLoaded = (N->getOpcode() == ISD::LOAD) ?
+      N->getValueType(0) : cast<VTSDNode>(N->getOperand(3))->getVT();
+    unsigned Opc;
+    switch (TypeBeingLoaded) {
+    default: N->dump(); assert(0 && "Cannot load this type!");
+    case MVT::i1:
+    case MVT::i8:  Opc = isIdx ? PPC::LBZX : PPC::LBZ; break;
+    case MVT::i16:
+      if (N->getOpcode() == ISD::SEXTLOAD) { // SEXT load?
+        Opc = isIdx ? PPC::LHAX : PPC::LHA;
+      } else {
+        Opc = isIdx ? PPC::LHZX : PPC::LHZ;
+      }
+      break;
+    case MVT::i32: Opc = isIdx ? PPC::LWZX : PPC::LWZ; break;
+    case MVT::f32: Opc = isIdx ? PPC::LFSX : PPC::LFS; break;
+    case MVT::f64: Opc = isIdx ? PPC::LFDX : PPC::LFD; break;
+    }
+
+    CurDAG->SelectNodeTo(N, N->getValueType(0), MVT::Other, Opc,
+                         Op1, Op2, Select(N->getOperand(0)));
+    break;
+  }
+
   case ISD::RET: {
     SDOperand Chain = Select(N->getOperand(0));     // Token chain.
 





From lattner at cs.uiuc.edu  Sun Aug 21 19:47:39 2005
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Sun, 21 Aug 2005 19:47:39 -0500
Subject: [llvm-commits] CVS: llvm/lib/Target/PowerPC/PPC32ISelPattern.cpp 
Message-ID: <200508220047.TAA17100@zion.cs.uiuc.edu>



Changes in directory llvm/lib/Target/PowerPC:

PPC32ISelPattern.cpp updated: 1.158 -> 1.159
---
Log message:

Make sure expressions only have one use before emitting them into a place that is conditionally executed


---
Diffs of the changes:  (+4 -3)

 PPC32ISelPattern.cpp |    7 ++++---
 1 files changed, 4 insertions(+), 3 deletions(-)


Index: llvm/lib/Target/PowerPC/PPC32ISelPattern.cpp
diff -u llvm/lib/Target/PowerPC/PPC32ISelPattern.cpp:1.158 llvm/lib/Target/PowerPC/PPC32ISelPattern.cpp:1.159
--- llvm/lib/Target/PowerPC/PPC32ISelPattern.cpp:1.158	Sun Aug 21 14:03:28 2005
+++ llvm/lib/Target/PowerPC/PPC32ISelPattern.cpp	Sun Aug 21 19:47:28 2005
@@ -1670,9 +1670,10 @@
 
     // If the false value is simple enough, evaluate it inline in the false
     // block.
-    if (isa<ConstantSDNode>(N.getOperand(3)) ||
-        isa<ConstantFPSDNode>(N.getOperand(3)) ||
-        isa<GlobalAddressSDNode>(N.getOperand(3)))
+    if (N.getOperand(3).Val->hasOneUse() &&
+        (isa<ConstantSDNode>(N.getOperand(3)) ||
+         isa<ConstantFPSDNode>(N.getOperand(3)) ||
+         isa<GlobalAddressSDNode>(N.getOperand(3))))
       FalseValue = 0;
     else
       FalseValue = SelectExpr(N.getOperand(3));





From lattner at cs.uiuc.edu  Sun Aug 21 19:59:25 2005
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Sun, 21 Aug 2005 19:59:25 -0500
Subject: [llvm-commits] CVS: llvm/lib/Target/PowerPC/PPC32ISelDAGToDAG.cpp 
Message-ID: <200508220059.TAA17521@zion.cs.uiuc.edu>



Changes in directory llvm/lib/Target/PowerPC:

PPC32ISelDAGToDAG.cpp updated: 1.18 -> 1.19
---
Log message:

Fix compilation of:
float %test2(float* %P) {
        %Q = load float* %P
        %R = add float %Q, %Q
        ret float %R
}

By returning the right result.



---
Diffs of the changes:  (+1 -1)

 PPC32ISelDAGToDAG.cpp |    2 +-
 1 files changed, 1 insertion(+), 1 deletion(-)


Index: llvm/lib/Target/PowerPC/PPC32ISelDAGToDAG.cpp
diff -u llvm/lib/Target/PowerPC/PPC32ISelDAGToDAG.cpp:1.18 llvm/lib/Target/PowerPC/PPC32ISelDAGToDAG.cpp:1.19
--- llvm/lib/Target/PowerPC/PPC32ISelDAGToDAG.cpp:1.18	Sun Aug 21 17:31:09 2005
+++ llvm/lib/Target/PowerPC/PPC32ISelDAGToDAG.cpp	Sun Aug 21 19:59:14 2005
@@ -962,7 +962,7 @@
     break;
   }
   }
-  return SDOperand(N, 0);
+  return SDOperand(N, Op.ResNo);
 }
 
 





From lattner at cs.uiuc.edu  Sun Aug 21 20:04:43 2005
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Sun, 21 Aug 2005 20:04:43 -0500
Subject: [llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp 
Message-ID: <200508220104.UAA17948@zion.cs.uiuc.edu>



Changes in directory llvm/lib/CodeGen/SelectionDAG:

ScheduleDAG.cpp updated: 1.11 -> 1.12
---
Log message:

Add a fast-path for register values.  Add support for constant pool entries,
allowing us to compile this:

float %test2(float* %P) {
        %Q = load float* %P
        %R = add float %Q, 10.1
        ret float %R
}

to this:

_test2:
        lfs r2, 0(r3)
        lis r3, ha16(.CPI_test2_0)
        lfs r3, lo16(.CPI_test2_0)(r3)
        fadds f1, r2, r3
        blr



---
Diffs of the changes:  (+13 -1)

 ScheduleDAG.cpp |   14 +++++++++++++-
 1 files changed, 13 insertions(+), 1 deletion(-)


Index: llvm/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp:1.11 llvm/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp:1.12
--- llvm/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp:1.11	Sun Aug 21 14:56:04 2005
+++ llvm/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp	Sun Aug 21 20:04:32 2005
@@ -111,7 +111,16 @@
     // Emit all of the operands of this instruction, adding them to the
     // instruction as appropriate.
     for (unsigned i = 0, e = Op.getNumOperands(); i != e; ++i) {
-      if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(i))) {
+      if (Op.getOperand(i).isTargetOpcode()) {
+        // Note that this case is redundant with the final else block, but we
+        // include it because it is the most common and it makes the logic
+        // simpler here.
+        unsigned R = Emit(Op.getOperand(i));
+        // Add an operand, unless this corresponds to a chain node.
+        if (Op.getOperand(i).getValueType() != MVT::Other)
+          MI->addRegOperand(R, MachineOperand::Use);
+      } else if (ConstantSDNode *C =
+                                   dyn_cast<ConstantSDNode>(Op.getOperand(i))) {
         MI->addZeroExtImm64Operand(C->getValue());
       } else if (RegisterSDNode*R =dyn_cast<RegisterSDNode>(Op.getOperand(i))) {
         MI->addRegOperand(R->getReg(), MachineOperand::Use);
@@ -124,6 +133,9 @@
       } else if (FrameIndexSDNode *FI =
                        dyn_cast<FrameIndexSDNode>(Op.getOperand(i))) {
         MI->addFrameIndexOperand(FI->getIndex());
+      } else if (ConstantPoolSDNode *CP = 
+                    dyn_cast<ConstantPoolSDNode>(Op.getOperand(i))) {
+        MI->addConstantPoolIndexOperand(CP->getIndex());
       } else {
         unsigned R = Emit(Op.getOperand(i));
         // Add an operand, unless this corresponds to a chain node.





From lattner at cs.uiuc.edu  Sun Aug 21 20:28:10 2005
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Sun, 21 Aug 2005 20:28:10 -0500
Subject: [llvm-commits] CVS: llvm/lib/Target/PowerPC/PPC32ISelDAGToDAG.cpp 
Message-ID: <200508220128.UAA18426@zion.cs.uiuc.edu>



Changes in directory llvm/lib/Target/PowerPC:

PPC32ISelDAGToDAG.cpp updated: 1.19 -> 1.20
---
Log message:

Implement stores.


---
Diffs of the changes:  (+26 -0)

 PPC32ISelDAGToDAG.cpp |   26 ++++++++++++++++++++++++++
 1 files changed, 26 insertions(+)


Index: llvm/lib/Target/PowerPC/PPC32ISelDAGToDAG.cpp
diff -u llvm/lib/Target/PowerPC/PPC32ISelDAGToDAG.cpp:1.19 llvm/lib/Target/PowerPC/PPC32ISelDAGToDAG.cpp:1.20
--- llvm/lib/Target/PowerPC/PPC32ISelDAGToDAG.cpp:1.19	Sun Aug 21 19:59:14 2005
+++ llvm/lib/Target/PowerPC/PPC32ISelDAGToDAG.cpp	Sun Aug 21 20:27:59 2005
@@ -894,6 +894,32 @@
     break;
   }
 
+  case ISD::TRUNCSTORE:
+  case ISD::STORE: {
+    SDOperand AddrOp1, AddrOp2;
+    bool isIdx = SelectAddr(N->getOperand(2), AddrOp1, AddrOp2);
+
+    unsigned Opc;
+    if (N->getOpcode() == ISD::STORE) {
+      switch (N->getOperand(1).getValueType()) {
+      default: assert(0 && "unknown Type in store");
+      case MVT::i32: Opc = isIdx ? PPC::STWX  : PPC::STW; break;
+      case MVT::f64: Opc = isIdx ? PPC::STFDX : PPC::STFD; break;
+      case MVT::f32: Opc = isIdx ? PPC::STFSX : PPC::STFS; break;
+      }
+    } else { //ISD::TRUNCSTORE
+      switch(cast<VTSDNode>(N->getOperand(4))->getVT()) {
+      default: assert(0 && "unknown Type in store");
+      case MVT::i1:
+      case MVT::i8:  Opc = isIdx ? PPC::STBX : PPC::STB; break;
+      case MVT::i16: Opc = isIdx ? PPC::STHX : PPC::STH; break;
+      }
+    }
+
+    CurDAG->SelectNodeTo(N, MVT::Other, Opc, Select(N->getOperand(1)),
+                         AddrOp1, AddrOp2, Select(N->getOperand(0)));
+    break;
+  }
   case ISD::RET: {
     SDOperand Chain = Select(N->getOperand(0));     // Token chain.