From jeffc at jolt-lang.org  Mon Nov 28 00:46:09 2005
From: jeffc at jolt-lang.org (Jeff Cohen)
Date: Mon, 28 Nov 2005 00:46:09 -0600
Subject: [llvm-commits] 
	CVS: llvm/lib/Transforms/Instrumentation/RSProfiling.cpp
Message-ID: <200511280646.AAA15818@zion.cs.uiuc.edu>



Changes in directory llvm/lib/Transforms/Instrumentation:

RSProfiling.cpp updated: 1.1 -> 1.2
---
Log message:

Fix VC++ warning.

---
Diffs of the changes:  (+1 -0)

 RSProfiling.cpp |    1 +
 1 files changed, 1 insertion(+)


Index: llvm/lib/Transforms/Instrumentation/RSProfiling.cpp
diff -u llvm/lib/Transforms/Instrumentation/RSProfiling.cpp:1.1 llvm/lib/Transforms/Instrumentation/RSProfiling.cpp:1.2
--- llvm/lib/Transforms/Instrumentation/RSProfiling.cpp:1.1	Sun Nov 27 18:58:09 2005
+++ llvm/lib/Transforms/Instrumentation/RSProfiling.cpp	Mon Nov 28 00:45:57 2005
@@ -445,6 +445,7 @@
     return v;
   }
   assert(0 && "Value not handled");
+  return 0;
 }
 
 void ProfilerRS::Duplicate(Function& F, RSProfilers& LI)





From jeffc at jolt-lang.org  Mon Nov 28 00:46:48 2005
From: jeffc at jolt-lang.org (Jeff Cohen)
Date: Mon, 28 Nov 2005 00:46:48 -0600
Subject: [llvm-commits] CVS: llvm/win32/Transforms/Transforms.vcproj 
Message-ID: <200511280646.AAA15834@zion.cs.uiuc.edu>



Changes in directory llvm/win32/Transforms:

Transforms.vcproj updated: 1.17 -> 1.18
---
Log message:

Teach Visual Studio about new files.

---
Diffs of the changes:  (+6 -0)

 Transforms.vcproj |    6 ++++++
 1 files changed, 6 insertions(+)


Index: llvm/win32/Transforms/Transforms.vcproj
diff -u llvm/win32/Transforms/Transforms.vcproj:1.17 llvm/win32/Transforms/Transforms.vcproj:1.18
--- llvm/win32/Transforms/Transforms.vcproj:1.17	Thu Nov 10 19:34:02 2005
+++ llvm/win32/Transforms/Transforms.vcproj	Mon Nov 28 00:46:36 2005
@@ -137,6 +137,12 @@
 					RelativePath="..\..\lib\Transforms\Instrumentation\ProfilingUtils.h">
 				</File>
 				<File
+					RelativePath="..\..\lib\Transforms\Instrumentation\RSProfiling.cpp">
+				</File>
+				<File
+					RelativePath="..\..\lib\Transforms\Instrumentation\RSProfiling.h">
+				</File>
+				<File
 					RelativePath="..\..\lib\Transforms\Instrumentation\TraceBasicBlocks.cpp">
 				</File>
 				<File





From criswell at cs.uiuc.edu  Mon Nov 28 09:49:40 2005
From: criswell at cs.uiuc.edu (John Criswell)
Date: Mon, 28 Nov 2005 09:49:40 -0600
Subject: [llvm-commits] CVS: llvm/runtime/GCCLibraries/libc/remove.c 
Message-ID: <200511281549.JAA16208@choi.cs.uiuc.edu>



Changes in directory llvm/runtime/GCCLibraries/libc:

remove.c added (r1.1)
---
Log message:

Add the remove() function from the C library.


---
Diffs of the changes:  (+46 -0)

 remove.c |   46 ++++++++++++++++++++++++++++++++++++++++++++++
 1 files changed, 46 insertions(+)


Index: llvm/runtime/GCCLibraries/libc/remove.c
diff -c /dev/null llvm/runtime/GCCLibraries/libc/remove.c:1.1
*** /dev/null	Mon Nov 28 09:49:26 2005
--- llvm/runtime/GCCLibraries/libc/remove.c	Mon Nov 28 09:49:15 2005
***************
*** 0 ****
--- 1,46 ----
+ //===-- remove.c - The remove function for the LLVM libc Library --*- C -*-===//
+ // 
+ // A lot of this code is ripped gratuitously from glibc and libiberty.
+ //
+ //===----------------------------------------------------------------------===//
+ 
+ /* ANSI C `remove' function to delete a file or directory.  POSIX.1 version.
+    Copyright (C) 1995,96,97,2002 Free Software Foundation, Inc.
+    This file is part of the GNU C Library.
+ 
+    The GNU C Library is free software; you can redistribute it and/or
+    modify it under the terms of the GNU Lesser General Public
+    License as published by the Free Software Foundation; either
+    version 2.1 of the License, or (at your option) any later version.
+ 
+    The GNU C Library is distributed in the hope that it will be useful,
+    but WITHOUT ANY WARRANTY; without even the implied warranty of
+    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+    Lesser General Public License for more details.
+ 
+    You should have received a copy of the GNU Lesser General Public
+    License along with the GNU C Library; if not, write to the Free
+    Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA
+    02111-1307 USA.  */
+ 
+ #include <errno.h>
+ #include <stdio.h>
+ #include <unistd.h>
+ 
+ int
+ remove (const char * file)
+ {
+   int save;
+ 
+   save = errno;
+   if (rmdir (file) == 0)
+     return 0;
+   else if (errno == ENOTDIR && unlink (file) == 0)
+     {
+       errno = (save);
+       return 0;
+     }
+ 
+   return -1;
+ }
+ 





From alenhar2 at cs.uiuc.edu  Mon Nov 28 12:00:48 2005
From: alenhar2 at cs.uiuc.edu (Andrew Lenharth)
Date: Mon, 28 Nov 2005 12:00:48 -0600
Subject: [llvm-commits] CVS: llvm/include/llvm/Transforms/RSProfiling.h
	LinkAllPasses.h Instrumentation.h 
Message-ID: <200511281800.MAA30939@apoc.cs.uiuc.edu>



Changes in directory llvm/include/llvm/Transforms:

RSProfiling.h added (r1.1)
LinkAllPasses.h updated: 1.26 -> 1.27
Instrumentation.h updated: 1.9 -> 1.10
---
Log message:

Added documented rsprofiler interface.  Also remove new profiler passes, the
old ones have been updated to implement the interface.


---
Diffs of the changes:  (+30 -4)

 Instrumentation.h |    2 --
 LinkAllPasses.h   |    2 --
 RSProfiling.h     |   30 ++++++++++++++++++++++++++++++
 3 files changed, 30 insertions(+), 4 deletions(-)


Index: llvm/include/llvm/Transforms/RSProfiling.h
diff -c /dev/null llvm/include/llvm/Transforms/RSProfiling.h:1.1
*** /dev/null	Mon Nov 28 12:00:38 2005
--- llvm/include/llvm/Transforms/RSProfiling.h	Mon Nov 28 12:00:28 2005
***************
*** 0 ****
--- 1,30 ----
+ //===- RSProfiling.cpp - Various profiling using random sampling ----------===//
+ //
+ //                      The LLVM Compiler Infrastructure
+ //
+ // This file was developed by the LLVM research group and is distributed under
+ // the University of Illinois Open Source License. See LICENSE.TXT for details.
+ //
+ //===----------------------------------------------------------------------===//
+ //
+ // This file defines the abstract interface that a profiler must implement to
+ // support the random profiling transform.
+ //
+ //===----------------------------------------------------------------------===//
+ 
+ namespace llvm {
+   //===--------------------------------------------------------------------===//
+   /// RSProfilers - The basic Random Sampling Profiler Interface  Any profiler 
+   /// that implements this interface can be transformed by the random sampling
+   /// pass to be sample based rather than always on.
+   ///
+   /// The only exposed function can be queried to find out if an instruction
+   /// was original or if it was inserted by the profiler.  Implementations of
+   /// this interface are expected to chain to other implementations, such that
+   /// multiple profilers can be support simultaniously.
+   struct RSProfilers : public ModulePass {
+     /// isProfiling - This method returns true if the value passed it was 
+     /// inserted by the profiler.
+     virtual bool isProfiling(Value* v) = 0;
+   };
+ };


Index: llvm/include/llvm/Transforms/LinkAllPasses.h
diff -u llvm/include/llvm/Transforms/LinkAllPasses.h:1.26 llvm/include/llvm/Transforms/LinkAllPasses.h:1.27
--- llvm/include/llvm/Transforms/LinkAllPasses.h:1.26	Sun Nov 27 18:58:09 2005
+++ llvm/include/llvm/Transforms/LinkAllPasses.h	Mon Nov 28 12:00:28 2005
@@ -106,8 +106,6 @@
       (void) llvm::createTraceValuesPassForFunction();
       (void) llvm::createUnifyFunctionExitNodesPass();
       (void) llvm::createCondPropagationPass();
-      (void) llvm::createBlockProfilerRSPass();
-      (void) llvm::createFunctionProfilerRSPass();
       (void) llvm::createNullProfilerRSPass();
       (void) llvm::createRSProfilingPass();
 


Index: llvm/include/llvm/Transforms/Instrumentation.h
diff -u llvm/include/llvm/Transforms/Instrumentation.h:1.9 llvm/include/llvm/Transforms/Instrumentation.h:1.10
--- llvm/include/llvm/Transforms/Instrumentation.h:1.9	Sun Nov 27 18:58:09 2005
+++ llvm/include/llvm/Transforms/Instrumentation.h	Mon Nov 28 12:00:28 2005
@@ -44,8 +44,6 @@
 FunctionPass *createProfilePathsPass();
 
 // Random Sampling Profiling Framework
-ModulePass* createBlockProfilerRSPass();
-ModulePass* createFunctionProfilerRSPass();
 ModulePass* createNullProfilerRSPass();
 FunctionPass* createRSProfilingPass();
 





From alenhar2 at cs.uiuc.edu  Mon Nov 28 12:00:53 2005
From: alenhar2 at cs.uiuc.edu (Andrew Lenharth)
Date: Mon, 28 Nov 2005 12:00:53 -0600
Subject: [llvm-commits] 
	CVS: llvm/lib/Transforms/Instrumentation/RSProfiling.h
	RSProfiling.cpp BlockProfiling.cpp 
Message-ID: <200511281800.MAA30947@apoc.cs.uiuc.edu>



Changes in directory llvm/lib/Transforms/Instrumentation:

RSProfiling.h updated: 1.1 -> 1.2
RSProfiling.cpp updated: 1.2 -> 1.3
BlockProfiling.cpp updated: 1.13 -> 1.14
---
Log message:

Added documented rsprofiler interface.  Also remove new profiler passes, the
old ones have been updated to implement the interface.



---
Diffs of the changes:  (+63 -135)

 BlockProfiling.cpp |    8 +-
 RSProfiling.cpp    |  173 ++++++++++++++---------------------------------------
 RSProfiling.h      |   17 ++---
 3 files changed, 63 insertions(+), 135 deletions(-)


Index: llvm/lib/Transforms/Instrumentation/RSProfiling.h
diff -u llvm/lib/Transforms/Instrumentation/RSProfiling.h:1.1 llvm/lib/Transforms/Instrumentation/RSProfiling.h:1.2
--- llvm/lib/Transforms/Instrumentation/RSProfiling.h:1.1	Sun Nov 27 18:58:09 2005
+++ llvm/lib/Transforms/Instrumentation/RSProfiling.h	Mon Nov 28 12:00:38 2005
@@ -1,4 +1,4 @@
-//===- RSProfiling.cpp - Various profiling using random sampling ----------===//
+//===- RSProfiling.h - Various profiling using random sampling ----------===//
 //
 //                      The LLVM Compiler Infrastructure
 //
@@ -10,18 +10,19 @@
 // See notes in RSProfiling.cpp
 //
 //===----------------------------------------------------------------------===//
+#include "llvm/Transforms/RSProfiling.h"
 
 namespace llvm {
-  // By default, we provide some convienence stuff to clients, so they 
-  // can just store the instructions they create to do profiling.
-  // also, handle all chaining issues.
-  // a client is free to overwrite these, as long as it implements the
-  // chaining itself.
-  struct RSProfilers : public ModulePass {
+  /// RSProfilers_std - a simple support class for profilers that handles most
+  /// of the work of chaining and tracking inserted code.
+  struct RSProfilers_std : public RSProfilers {
     std::set<Value*> profcode;
+    // Lookup up values in profcode
     virtual bool isProfiling(Value* v);
-    virtual ~RSProfilers() {}
+    // handles required chaining
     virtual void getAnalysisUsage(AnalysisUsage &AU) const;
+    // places counter updates in basic blocks and recordes added instructions in
+    // profcode
     void IncrementCounterInBlock(BasicBlock *BB, unsigned CounterNum,
                                  GlobalValue *CounterArray);
   };


Index: llvm/lib/Transforms/Instrumentation/RSProfiling.cpp
diff -u llvm/lib/Transforms/Instrumentation/RSProfiling.cpp:1.2 llvm/lib/Transforms/Instrumentation/RSProfiling.cpp:1.3
--- llvm/lib/Transforms/Instrumentation/RSProfiling.cpp:1.2	Mon Nov 28 00:45:57 2005
+++ llvm/lib/Transforms/Instrumentation/RSProfiling.cpp	Mon Nov 28 12:00:38 2005
@@ -10,7 +10,9 @@
 // These passes implement a random sampling based profiling.  Different methods
 // of choosing when to sample are supported, as well as different types of
 // profiling.  This is done as two passes.  The first is a sequence of profiling
-// passes which insert profiling into the program, and remember what they inserted.
+// passes which insert profiling into the program, and remember what they 
+// inserted.
+//
 // The second stage duplicates all instructions in a function, ignoring the 
 // profiling code, then connects the two versions togeather at the entry and at
 // backedges.  At each connection point a choice is made as to whether to jump
@@ -31,9 +33,7 @@
 //===----------------------------------------------------------------------===//
 
 #include "llvm/Pass.h"
-#include "llvm/Function.h"
 #include "llvm/Module.h"
-#include "llvm/BasicBlock.h"
 #include "llvm/Instructions.h"
 #include "llvm/Constants.h"
 #include "llvm/DerivedTypes.h"
@@ -43,7 +43,7 @@
 #include "llvm/Support/CommandLine.h"
 #include "llvm/Support/Debug.h"
 #include "llvm/Transforms/Instrumentation.h"
-#include "ProfilingUtils.h"
+//#include "ProfilingUtils.h"
 #include "RSProfiling.h"
 
 #include <set>
@@ -65,19 +65,11 @@
       cl::desc("How to randomly choose to profile:"),
       cl::values(
                  clEnumValN(GBV, "global", "global counter"),
-                 clEnumValN(GBVO, "ra_global", "register allocated global counter"),
+                 clEnumValN(GBVO, "ra_global", 
+			    "register allocated global counter"),
                  clEnumValN(HOSTCC, "rdcc", "cycle counter"),
                  clEnumValEnd));
   
-
-  class FunctionProfilerRS : public RSProfilers {
-    bool runOnModule(Module &M);
-  };
-
-  class BlockProfilerRS : public RSProfilers {
-    bool runOnModule(Module &M);
-  };
-
   class NullProfilerRS : public RSProfilers {
   public:
     bool isProfiling(Value* v) {
@@ -93,15 +85,8 @@
 
   static RegisterAnalysisGroup<RSProfilers> A("Profiling passes");
   static RegisterOpt<NullProfilerRS> NP("insert-null-profiling-rs",
-                                          "Measure profiling framework overhead");
+					"Measure profiling framework overhead");
   static RegisterAnalysisGroup<RSProfilers, NullProfilerRS, true> NPT;
-  static RegisterOpt<BlockProfilerRS> BBP("insert-block-profiling-rs",
-                                          "Add block count instrumentation");
-  static RegisterAnalysisGroup<RSProfilers, BlockProfilerRS> BBPT;
-  static RegisterOpt<FunctionProfilerRS> FP("insert-function-profiling-rs",
-                                          "Add function count instrumentation");
-  static RegisterAnalysisGroup<RSProfilers, FunctionProfilerRS> FPT;
-
 
   //Something that chooses how to sample
   class Chooser {
@@ -160,7 +145,7 @@
   };
 
   RegisterOpt<ProfilerRS> X("insert-rs-profiling-framework",
-                                "Insert random sampling instrumentation  framework");
+			   "Insert random sampling instrumentation  framework");
 };
 
 //Local utilities
@@ -203,17 +188,18 @@
   //decrement counter
   LoadInst* l = new LoadInst(Counter, "counter", t);
   
-  SetCondInst* s = new SetCondInst(Instruction::SetEQ, l, ConstantUInt::get(T, 0), 
+  SetCondInst* s = new SetCondInst(Instruction::SetEQ, l, 
+				   ConstantUInt::get(T, 0), 
                                    "countercc", t);
-  Value* nv = BinaryOperator::create(Instruction::Sub, l,
-                                     ConstantInt::get(T, 1),
+  Value* nv = BinaryOperator::createSub(l, ConstantInt::get(T, 1),
                                      "counternew", t);
   new StoreInst(nv, Counter, t);
   t->setCondition(s);
   
   //reset counter
   BasicBlock* oldnext = t->getSuccessor(0);
-  BasicBlock* resetblock = new BasicBlock("reset", oldnext->getParent(), oldnext);
+  BasicBlock* resetblock = new BasicBlock("reset", oldnext->getParent(), 
+					  oldnext);
   TerminatorInst* t2 = new BranchInst(oldnext, resetblock);
   t->setSuccessor(0, resetblock);
   new StoreInst(ResetValue, Counter, t2);
@@ -274,17 +260,18 @@
   //decrement counter
   LoadInst* l = new LoadInst(AI, "counter", t);
   
-  SetCondInst* s = new SetCondInst(Instruction::SetEQ, l, ConstantUInt::get(T, 0), 
+  SetCondInst* s = new SetCondInst(Instruction::SetEQ, l, 
+				   ConstantUInt::get(T, 0), 
                                    "countercc", t);
-  Value* nv = BinaryOperator::create(Instruction::Sub, l,
-                                     ConstantInt::get(T, 1),
+  Value* nv = BinaryOperator::createSub(l, ConstantInt::get(T, 1),
                                      "counternew", t);
   new StoreInst(nv, AI, t);
   t->setCondition(s);
   
   //reset counter
   BasicBlock* oldnext = t->getSuccessor(0);
-  BasicBlock* resetblock = new BasicBlock("reset", oldnext->getParent(), oldnext);
+  BasicBlock* resetblock = new BasicBlock("reset", oldnext->getParent(), 
+					  oldnext);
   TerminatorInst* t2 = new BranchInst(oldnext, resetblock);
   t->setSuccessor(0, resetblock);
   new StoreInst(ResetValue, AI, t2);
@@ -304,9 +291,12 @@
   BranchInst* t = cast<BranchInst>(bb->getTerminator());
   
   CallInst* c = new CallInst(F, "rdcc", t);
-  BinaryOperator* b = BinaryOperator::create(Instruction::And, c, ConstantUInt::get(Type::ULongTy, rm), "mrdcc", t);
+  BinaryOperator* b = 
+    BinaryOperator::createAnd(c, ConstantUInt::get(Type::ULongTy, rm),
+			      "mrdcc", t);
   
-  SetCondInst* s = new SetCondInst(Instruction::SetEQ, b, ConstantUInt::get(Type::ULongTy, 0), 
+  SetCondInst* s = new SetCondInst(Instruction::SetEQ, b, 
+				   ConstantUInt::get(Type::ULongTy, 0), 
                                    "mrdccc", t);
   t->setCondition(s);
 }
@@ -314,7 +304,7 @@
 ///////////////////////////////////////
 // Profiling:
 ///////////////////////////////////////
-bool RSProfilers::isProfiling(Value* v) {
+bool RSProfilers_std::isProfiling(Value* v) {
   if (profcode.find(v) != profcode.end())
     return true;
   //else
@@ -322,7 +312,7 @@
   return LI.isProfiling(v);
 }
 
-void RSProfilers::IncrementCounterInBlock(BasicBlock *BB, unsigned CounterNum,
+void RSProfilers_std::IncrementCounterInBlock(BasicBlock *BB, unsigned CounterNum,
                                           GlobalValue *CounterArray) {
   // Insert the increment after any alloca or PHI instructions...
   BasicBlock::iterator InsertPos = BB->begin();
@@ -338,77 +328,18 @@
   // Load, increment and store the value back.
   Value *OldVal = new LoadInst(ElementPtr, "OldCounter", InsertPos);
   profcode.insert(OldVal);
-  Value *NewVal = BinaryOperator::create(Instruction::Add, OldVal,
-                                         ConstantInt::get(Type::UIntTy, 1),
-                                         "NewCounter", InsertPos);
+  Value *NewVal = BinaryOperator::createAdd(OldVal,
+					    ConstantInt::get(Type::UIntTy, 1),
+					    "NewCounter", InsertPos);
   profcode.insert(NewVal);
   profcode.insert(new StoreInst(NewVal, ElementPtr, InsertPos));
 }
 
-void RSProfilers::getAnalysisUsage(AnalysisUsage &AU) const {
+void RSProfilers_std::getAnalysisUsage(AnalysisUsage &AU) const {
   //grab any outstanding profiler, or get the null one
   AU.addRequired<RSProfilers>();
 }
 
-bool FunctionProfilerRS::runOnModule(Module &M) {
-  Function *Main = M.getMainFunction();
-  if (Main == 0) {
-    std::cerr << "WARNING: cannot insert function profiling into a module"
-              << " with no main function!\n";
-    return false;  // No main, no instrumentation!
-  }
-  
-  unsigned NumFunctions = 0;
-  for (Module::iterator I = M.begin(), E = M.end(); I != E; ++I)
-    if (!I->isExternal())
-      ++NumFunctions;
-  
-  const Type *ATy = ArrayType::get(Type::UIntTy, NumFunctions);
-  GlobalVariable *Counters =
-    new GlobalVariable(ATy, false, GlobalValue::InternalLinkage,
-                       Constant::getNullValue(ATy), "FuncProfCounters", &M);
-  
-  // Instrument all of the functions...
-  unsigned i = 0;
-  for (Module::iterator I = M.begin(), E = M.end(); I != E; ++I)
-    if (!I->isExternal())
-      // Insert counter at the start of the function
-      IncrementCounterInBlock(I->begin(), i++, Counters);
-  
-  // Add the initialization call to main.
-  InsertProfilingInitCall(Main, "llvm_start_func_profiling", Counters);
-  return true;
-}
-
-bool BlockProfilerRS::runOnModule(Module &M) {
-  Function *Main = M.getMainFunction();
-  if (Main == 0) {
-    std::cerr << "WARNING: cannot insert block profiling into a module"
-              << " with no main function!\n";
-    return false;  // No main, no instrumentation!
-  }
-  
-  unsigned NumBlocks = 0;
-  for (Module::iterator I = M.begin(), E = M.end(); I != E; ++I)
-    NumBlocks += I->size();
-  
-  const Type *ATy = ArrayType::get(Type::UIntTy, NumBlocks);
-  GlobalVariable *Counters =
-    new GlobalVariable(ATy, false, GlobalValue::InternalLinkage,
-                       Constant::getNullValue(ATy), "BlockProfCounters", &M);
-  
-  // Instrument all of the blocks...
-  unsigned i = 0;
-  for (Module::iterator I = M.begin(), E = M.end(); I != E; ++I)
-    for (Function::iterator BB = I->begin(), E = I->end(); BB != E; ++BB)
-      // Insert counter at the start of the block
-      IncrementCounterInBlock(BB, i++, Counters);
-  
-  // Add the initialization call to main.
-  InsertProfilingInitCall(Main, "llvm_start_block_profiling", Counters);
-  return true;
-}
-
 ///////////////////////////////////////
 // RS Framework
 ///////////////////////////////////////
@@ -421,7 +352,8 @@
     if (bb == &bb->getParent()->getEntryBlock())
       TransCache[bb] = bb; //don't translate entry block
     else
-      TransCache[bb] = new BasicBlock("dup_" + bb->getName(), bb->getParent(), NULL);
+      TransCache[bb] = new BasicBlock("dup_" + bb->getName(), bb->getParent(), 
+				      NULL);
     return TransCache[bb];
   } else if (Instruction* i = dyn_cast<Instruction>(v)) {
     //we have already translated this
@@ -510,13 +442,14 @@
   //a:
   BasicBlock* bbC = new BasicBlock("choice", &F, src->getNext() );
   //ChoicePoints.insert(bbC);
-  BasicBlock* bbCp = new BasicBlock("choice", &F, cast<BasicBlock>(Translate(src))->getNext() );
+  BasicBlock* bbCp = 
+    new BasicBlock("choice", &F, cast<BasicBlock>(Translate(src))->getNext() );
   ChoicePoints.insert(bbCp);
   
   //b:
-  //new BranchInst(dst, cast<BasicBlock>(Translate(dst)), ConstantBool::get(true), bbC);
   new BranchInst(cast<BasicBlock>(Translate(dst)), bbC);
-  new BranchInst(dst, cast<BasicBlock>(Translate(dst)), ConstantBool::get(true), bbCp);
+  new BranchInst(dst, cast<BasicBlock>(Translate(dst)), 
+		 ConstantBool::get(true), bbCp);
   //c:
   {
     TerminatorInst* iB = src->getTerminator();
@@ -537,7 +470,8 @@
   //thus collapse those edges int the Phi
   CollapsePhi(dst, bbC);
   //f:
-  ReplacePhiPred(cast<BasicBlock>(Translate(dst)),cast<BasicBlock>(Translate(src)),bbCp);
+  ReplacePhiPred(cast<BasicBlock>(Translate(dst)),
+		 cast<BasicBlock>(Translate(src)),bbCp);
   CollapsePhi(cast<BasicBlock>(Translate(dst)), bbCp);
   //g:
   for(BasicBlock::iterator ib = dst->begin(), ie = dst->end(); ib != ie;
@@ -546,7 +480,8 @@
       for(unsigned x = 0; x < phi->getNumIncomingValues(); ++x)
         if(bbC == phi->getIncomingBlock(x)) {
           phi->addIncoming(Translate(phi->getIncomingValue(x)), bbCp);
-          cast<PHINode>(Translate(phi))->addIncoming(phi->getIncomingValue(x), bbC);
+          cast<PHINode>(Translate(phi))->addIncoming(phi->getIncomingValue(x), 
+						     bbC);
         }
       phi->removeIncomingValue(bbC);
     }
@@ -558,23 +493,19 @@
     RSProfilers& LI = getAnalysis<RSProfilers>();
     
     getBackEdges(F, BackEdges);
-    DEBUG(
-          for (std::set<std::pair<BasicBlock*, BasicBlock*> >::iterator ii = BackEdges.begin();
-               ii != BackEdges.end(); ++ii)
-            std::cerr << ii->first->getName() << " -> " << ii->second->getName() << "\n";
-          );
     Duplicate(F, LI);
     //assume that stuff worked.  now connect the duplicated basic blocks 
     //with the originals in such a way as to preserve ssa.  yuk!
-    for (std::set<std::pair<BasicBlock*, BasicBlock*> >::iterator ib = BackEdges.begin(),
-           ie = BackEdges.end(); ib != ie; ++ib)
+    for (std::set<std::pair<BasicBlock*, BasicBlock*> >::iterator 
+	   ib = BackEdges.begin(), ie = BackEdges.end(); ib != ie; ++ib)
       ProcessBackEdge(ib->first, ib->second, F);
     
-    //oh, and add the edge from the reg2mem created entry node to the duplicated second node
+    //oh, and add the edge from the reg2mem created entry node to the 
+    //duplicated second node
     TerminatorInst* T = F.getEntryBlock().getTerminator();
     ReplaceInstWithInst(T, new BranchInst(T->getSuccessor(0),
-                                          cast<BasicBlock>(Translate(T->getSuccessor(0))),
-                                          ConstantBool::get(true)));
+			       cast<BasicBlock>(Translate(T->getSuccessor(0))),
+					  ConstantBool::get(true)));
     
     //do whatever is needed now that the function is duplicated
     c->PrepFunction(&F);
@@ -582,8 +513,8 @@
     //add entry node to choice points
     ChoicePoints.insert(&F.getEntryBlock());
     
-    for (std::set<BasicBlock*>::iterator ii = ChoicePoints.begin(), ie = ChoicePoints.end();
-         ii != ie; ++ii)
+    for (std::set<BasicBlock*>::iterator 
+	   ii = ChoicePoints.begin(), ie = ChoicePoints.end(); ii != ie; ++ii)
       c->ProcessChoicePoint(*ii);
     
     ChoicePoints.clear();
@@ -636,7 +567,7 @@
       std::map<BasicBlock*, Value*> counter;
       for(unsigned i = 0; i < phi->getNumIncomingValues(); ) {
         if (counter[phi->getIncomingBlock(i)]) {
-          assert (phi->getIncomingValue(i) == counter[phi->getIncomingBlock(i)]);
+          assert(phi->getIncomingValue(i) == counter[phi->getIncomingBlock(i)]);
           phi->removeIncomingValue(i, false);
         } else {
           counter[phi->getIncomingBlock(i)] = phi->getIncomingValue(i);
@@ -686,14 +617,6 @@
 
 
 //Creation functions
-ModulePass* llvm::createBlockProfilerRSPass() {
-  return new BlockProfilerRS();
-}
-
-ModulePass* llvm::createFunctionProfilerRSPass() {
-  return new FunctionProfilerRS();
-}
-
 ModulePass* llvm::createNullProfilerRSPass() {
   return new NullProfilerRS();
 }


Index: llvm/lib/Transforms/Instrumentation/BlockProfiling.cpp
diff -u llvm/lib/Transforms/Instrumentation/BlockProfiling.cpp:1.13 llvm/lib/Transforms/Instrumentation/BlockProfiling.cpp:1.14
--- llvm/lib/Transforms/Instrumentation/BlockProfiling.cpp:1.13	Thu Apr 21 18:40:46 2005
+++ llvm/lib/Transforms/Instrumentation/BlockProfiling.cpp	Mon Nov 28 12:00:38 2005
@@ -24,18 +24,21 @@
 #include "llvm/Module.h"
 #include "llvm/Pass.h"
 #include "llvm/Transforms/Instrumentation.h"
+#include "RSProfiling.h"
 #include "ProfilingUtils.h"
 #include <iostream>
 
 using namespace llvm;
 
 namespace {
-  class FunctionProfiler : public ModulePass {
+  class FunctionProfiler : public RSProfilers_std {
     bool runOnModule(Module &M);
   };
 
   RegisterOpt<FunctionProfiler> X("insert-function-profiling",
                                "Insert instrumentation for function profiling");
+  RegisterAnalysisGroup<RSProfilers, FunctionProfiler> XG;
+
 }
 
 ModulePass *llvm::createFunctionProfilerPass() {
@@ -74,12 +77,13 @@
 
 
 namespace {
-  class BlockProfiler : public ModulePass {
+  class BlockProfiler : public RSProfilers_std {
     bool runOnModule(Module &M);
   };
 
   RegisterOpt<BlockProfiler> Y("insert-block-profiling",
                                "Insert instrumentation for block profiling");
+  RegisterAnalysisGroup<RSProfilers, BlockProfiler> YG;
 }
 
 ModulePass *llvm::createBlockProfilerPass() { return new BlockProfiler(); }





From alenhar2 at cs.uiuc.edu  Mon Nov 28 12:11:19 2005
From: alenhar2 at cs.uiuc.edu (Andrew Lenharth)
Date: Mon, 28 Nov 2005 12:11:19 -0600
Subject: [llvm-commits] 
	CVS: llvm/lib/Transforms/Instrumentation/RSProfiling.cpp
Message-ID: <200511281811.MAA30962@apoc.cs.uiuc.edu>



Changes in directory llvm/lib/Transforms/Instrumentation:

RSProfiling.cpp updated: 1.3 -> 1.4
---
Log message:

a few more comments on the interfaces and functions

---
Diffs of the changes:  (+20 -3)

 RSProfiling.cpp |   23 ++++++++++++++++++++---
 1 files changed, 20 insertions(+), 3 deletions(-)


Index: llvm/lib/Transforms/Instrumentation/RSProfiling.cpp
diff -u llvm/lib/Transforms/Instrumentation/RSProfiling.cpp:1.3 llvm/lib/Transforms/Instrumentation/RSProfiling.cpp:1.4
--- llvm/lib/Transforms/Instrumentation/RSProfiling.cpp:1.3	Mon Nov 28 12:00:38 2005
+++ llvm/lib/Transforms/Instrumentation/RSProfiling.cpp	Mon Nov 28 12:10:59 2005
@@ -70,6 +70,9 @@
                  clEnumValN(HOSTCC, "rdcc", "cycle counter"),
                  clEnumValEnd));
   
+  /// NullProfilerRS - The basic profiler that does nothing.  It is the default
+  /// profiler and thus terminates RSProfiler chains.  It is useful for 
+  /// measuring framework overhead
   class NullProfilerRS : public RSProfilers {
   public:
     bool isProfiling(Value* v) {
@@ -88,15 +91,21 @@
 					"Measure profiling framework overhead");
   static RegisterAnalysisGroup<RSProfilers, NullProfilerRS, true> NPT;
 
-  //Something that chooses how to sample
+  /// Chooser - Something that chooses when to make a sample of the profiled code
   class Chooser {
   public:
+    /// ProcessChoicePoint - is called for each basic block inserted to choose 
+    /// between normal and sample code
     virtual void ProcessChoicePoint(BasicBlock*) = 0;
+    /// PrepFunction - is called once per function before other work is done.
+    /// This gives the opertunity to insert new allocas and such.
     virtual void PrepFunction(Function*) = 0;
     virtual ~Chooser() {}
   };
 
   //Things that implement sampling policies
+  //A global value that is read-mod-stored to choose when to sample.
+  //A sample is taken when the global counter hits 0
   class GlobalRandomCounter : public Chooser {
     GlobalVariable* Counter;
     Value* ResetValue;
@@ -108,6 +117,7 @@
     virtual void ProcessChoicePoint(BasicBlock* bb);
   };
 
+  //Same is GRC, but allow register allocation of the global counter
   class GlobalRandomCounterOpt : public Chooser {
     GlobalVariable* Counter;
     Value* ResetValue;
@@ -120,6 +130,8 @@
     virtual void ProcessChoicePoint(BasicBlock* bb);
   };
 
+  //Use the cycle counter intrinsic as a source of pseudo randomness when
+  //deciding when to sample.
   class CycleCounter : public Chooser {
     uint64_t rm;
     Function* F;
@@ -130,14 +142,18 @@
     virtual void ProcessChoicePoint(BasicBlock* bb);
   };
 
-
+  /// ProfilerRS - Insert the random sampling framework
   struct ProfilerRS : public FunctionPass {
     std::map<Value*, Value*> TransCache;
     std::set<BasicBlock*> ChoicePoints;
     Chooser* c;
 
+    //Translate and duplicate values for the new profile free version of stuff
     Value* Translate(Value* v);
+    //Duplicate an entire function (with out profiling)
     void Duplicate(Function& F, RSProfilers& LI);
+    //Called once for each backedge, handle the insertion of choice points and
+    //the interconection of the two versions of the code
     void ProcessBackEdge(BasicBlock* src, BasicBlock* dst, Function& F);
     bool runOnFunction(Function& F);
     bool doInitialization(Module &M);
@@ -224,7 +240,8 @@
   LoadInst* l = new LoadInst(Counter, "counterload", AI->getNext());
   new StoreInst(l, AI, l->getNext());
   
-  //modify all functions and return values
+  //modify all functions and return values to restore the local variable to/from
+  //the global variable
   for(Function::iterator fib = F->begin(), fie = F->end();
       fib != fie; ++fib)
     for(BasicBlock::iterator bib = fib->begin(), bie = fib->end();





From lattner at cs.uiuc.edu  Mon Nov 28 15:47:12 2005
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Mon, 28 Nov 2005 15:47:12 -0600
Subject: [llvm-commits] CVS: llvm-www/releases/download.html index.html 
Message-ID: <200511282147.PAA25221@zion.cs.uiuc.edu>



Changes in directory llvm-www/releases:

download.html updated: 1.24 -> 1.25
index.html updated: 1.25 -> 1.26
---
Log message:

eliminate the LLVM registration page.


---
Diffs of the changes:  (+27 -37)

 download.html |   23 ++++++++---------------
 index.html    |   41 +++++++++++++++++++----------------------
 2 files changed, 27 insertions(+), 37 deletions(-)


Index: llvm-www/releases/download.html
diff -u llvm-www/releases/download.html:1.24 llvm-www/releases/download.html:1.25
--- llvm-www/releases/download.html:1.24	Tue Nov  8 14:11:31 2005
+++ llvm-www/releases/download.html	Mon Nov 28 15:46:59 2005
@@ -11,15 +11,8 @@
 
 <div class="rel_container">
 
-<div class="rel_intro">
-If you signed up for the LLVM Announcements list, you should receive a
-confirmation email.  If you didn't, you can  
-<a href="http://lists.cs.uiuc.edu/mailman/listinfo/llvm-announce">subscribe to
-llvm-announce</a> directly.
-</div>
-
 <table class="rel_section">
-<tr><td>CVS Access</td></tr>
+<tr><td><a name="cvs">CVS Access</a></td></tr>
 </table>
 
 <div class="rel_boxtext">
@@ -37,7 +30,7 @@
 </div>
 
 <table class="rel_section">
-<tr><td>Download LLVM 1.6</td></tr>
+<tr><td><a name="1.6">Download LLVM 1.6</a></td></tr>
 </table>
 
 <div class="rel_boxtext">
@@ -66,7 +59,7 @@
 
 
 <table class="rel_section">
-<tr><td>Download LLVM 1.5</td></tr>
+<tr><td><a name="1.5">Download LLVM 1.5</a></td></tr>
 </table>
 
 <div class="rel_boxtext">
@@ -96,7 +89,7 @@
 
 
 <table class="rel_section">
-<tr><td>Download LLVM 1.4</td></tr>
+<tr><td><a name="1.4">Download LLVM 1.4</a></td></tr>
 </table>
 
 <div class="rel_boxtext">
@@ -125,7 +118,7 @@
 
 
 <table class="rel_section">
-<tr><td>Download LLVM 1.3</td></tr>
+<tr><td><a name="1.3">Download LLVM 1.3</a></td></tr>
 </table>
 
 <div class="rel_boxtext">
@@ -159,7 +152,7 @@
 </div>
 
 <table class="rel_section">
-<tr><td>Download LLVM 1.2</td></tr>
+<tr><td><a name="1.2">Download LLVM 1.2</a></td></tr>
 </table>
 
 <div class="rel_boxtext">
@@ -186,7 +179,7 @@
 </div>
 
 <table class="rel_section">
-<tr><td>Download LLVM 1.1</td></tr>
+<tr><td><a name="1.1">Download LLVM 1.1</a></td></tr>
 </table>
 
 <div class="rel_boxtext">
@@ -216,7 +209,7 @@
 </div>
 
 <table class="rel_section">
-<tr><td>Download LLVM 1.0</td></tr>
+<tr><td><a name="1.0">Download LLVM 1.0</a></td></tr>
 </table>
 
 <div class="rel_boxtext">


Index: llvm-www/releases/index.html
diff -u llvm-www/releases/index.html:1.25 llvm-www/releases/index.html:1.26
--- llvm-www/releases/index.html:1.25	Tue Nov  8 14:11:31 2005
+++ llvm-www/releases/index.html	Mon Nov 28 15:46:59 2005
@@ -6,24 +6,11 @@
 <body>
 
 <div class="rel_title">
-  LLVM Public Release
+  LLVM Download Page
 </div>
 
 <div class="rel_container">
 
-<div class="rel_intro">
-
-<p>We are pleased to announce the public release of the LLVM Compiler
-Infrastructure.</p>
-
-<p>LLVM is a new infrastructure designed for compile-time, link-time, runtime,
-and "idle-time" optimization of programs from arbitrary programming languages.
-LLVM is written in C++ and has been developed since 2000 A.D. at the University
-of Illinois.  It currently supports compilation of C and C++ programs, using
-front-ends derived from GCC 3.4.</p>
-
-</div>
-
 <div class="rel_section">License</div>
 
 <div class="rel_boxtext">
@@ -35,33 +22,43 @@
 
 </div>
 
+<div class="rel_section">Mailing list</div>
+
+<div class="rel_boxtext">
+If you are interested in LLVM, we strongly encourage you to sign up for the
+<a href="http://lists.cs.uiuc.edu/mailman/listinfo/llvm-announce">
+LLVM announcements mailing list</a>.  This list is an extremely low volume
+list (less than one email per month) that is a good way to keep track of the
+high-level happenings in the LLVM community.
+</div>
+
 <div class="rel_section">Download</div>
 
 <div class="rel_boxtext">
 
 <ul>
-<li>Always - <a href="register.html">Anonymous CVS access</a>; <a
+<li>Always - <a href="download.html#cvs">Anonymous CVS access</a>; <a
 href="../docs/ReleaseNotes.html">release notes</a>.</li>
 
-<li>08 Nov 2005 - 1.6 release <a href="register.html">download</a>; <a
+<li>08 Nov 2005 - 1.6 release <a href="download.html#1.6">download</a>; <a
 href="1.6/docs/ReleaseNotes.html">release notes</a>.</li>
 
-<li>18 May 2005 - 1.5 release <a href="register.html">download</a>; <a
+<li>18 May 2005 - 1.5 release <a href="download.html#1.5">download</a>; <a
 href="1.5/docs/ReleaseNotes.html">release notes</a>.</li>
 
-<li>09 Dec 2004 - 1.4 release <a href="register.html">download</a>; <a
+<li>09 Dec 2004 - 1.4 release <a href="download.html#1.4">download</a>; <a
 href="1.4/docs/ReleaseNotes.html">release notes</a>.</li>
 
-<li>13 Aug 2004 - 1.3 release <a href="register.html">download</a>; <a
+<li>13 Aug 2004 - 1.3 release <a href="download.html#1.3">download</a>; <a
 href="1.3/docs/ReleaseNotes.html">release notes</a>.</li>
 
-<li>19 Mar 2004 - 1.2 release <a href="register.html">download</a>; <a
+<li>19 Mar 2004 - 1.2 release <a href="download.html#1.2">download</a>; <a
 href="1.2/docs/ReleaseNotes.html">release notes</a>.</li>
 
-<li>17 Dec 2003 - 1.1 release <a href="register.html">download</a>; <a
+<li>17 Dec 2003 - 1.1 release <a href="download.html#1.1">download</a>; <a
 href="1.1/docs/ReleaseNotes.html">release notes</a>.</li>
 
-<li>24 Oct 2003 - 1.0 release <a href="register.html">download</a>; <a
+<li>24 Oct 2003 - 1.0 release <a href="download.html#1.0">download</a>; <a
 href="1.0/docs/ReleaseNotes.html">release notes</a>.</li>
 </ul>
 





From lattner at cs.uiuc.edu  Mon Nov 28 15:48:38 2005
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Mon, 28 Nov 2005 15:48:38 -0600
Subject: [llvm-commits] CVS: llvm-www/releases/checkreg.cgi quickreg.cgi
	register.cgi testregister.cgi testregister.html 
Message-ID: <200511282148.PAA25300@zion.cs.uiuc.edu>



Changes in directory llvm-www/releases:

checkreg.cgi (r1.4) removed
quickreg.cgi (r1.1) removed
register.cgi (r1.22) removed
testregister.cgi (r1.23) removed
testregister.html (r1.2) removed
---
Log message:

good bye registration CGI scripts, you have served us well.


---
Diffs of the changes:  (+0 -0)

 0 files changed





From lattner at cs.uiuc.edu  Mon Nov 28 15:49:51 2005
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Mon, 28 Nov 2005 15:49:51 -0600
Subject: [llvm-commits] CVS: llvm-www/releases/register.html 
Message-ID: <200511282149.PAA25380@zion.cs.uiuc.edu>



Changes in directory llvm-www/releases:

register.html (r1.9) removed
---
Log message:

this page is also dead


---
Diffs of the changes:  (+0 -0)

 0 files changed





From lattner at cs.uiuc.edu  Mon Nov 28 16:42:26 2005
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Mon, 28 Nov 2005 16:42:26 -0600
Subject: [llvm-commits] CVS: llvm/lib/Target/Target.td 
Message-ID: <200511282242.QAA25777@zion.cs.uiuc.edu>



Changes in directory llvm/lib/Target:

Target.td updated: 1.58 -> 1.59
---
Log message:

fix a typo :)


---
Diffs of the changes:  (+1 -1)

 Target.td |    2 +-
 1 files changed, 1 insertion(+), 1 deletion(-)


Index: llvm/lib/Target/Target.td
diff -u llvm/lib/Target/Target.td:1.58 llvm/lib/Target/Target.td:1.59
--- llvm/lib/Target/Target.td:1.58	Sat Nov 19 01:00:10 2005
+++ llvm/lib/Target/Target.td	Mon Nov 28 16:42:15 2005
@@ -31,7 +31,7 @@
 def i16    : ValueType<16 ,  3>;   // 16-bit integer value
 def i32    : ValueType<32 ,  4>;   // 32-bit integer value
 def i64    : ValueType<64 ,  5>;   // 64-bit integer value
-def i128   : ValueType<128,  5>;   // 128-bit integer value
+def i128   : ValueType<128,  6>;   // 128-bit integer value
 def f32    : ValueType<32 ,  7>;   // 32-bit floating point value
 def f64    : ValueType<64 ,  8>;   // 64-bit floating point value
 def f80    : ValueType<80 ,  9>;   // 80-bit floating point value





From criswell at cs.uiuc.edu  Mon Nov 28 17:26:02 2005
From: criswell at cs.uiuc.edu (John Criswell)
Date: Mon, 28 Nov 2005 17:26:02 -0600
Subject: [llvm-commits] CVS: llvm/docs/WritingAnLLVMPass.html 
Message-ID: <200511282326.RAA15267@choi.cs.uiuc.edu>



Changes in directory llvm/docs:

WritingAnLLVMPass.html updated: 1.41 -> 1.42
---
Log message:

Fixed a punctuation error.


---
Diffs of the changes:  (+2 -2)

 WritingAnLLVMPass.html |    4 ++--
 1 files changed, 2 insertions(+), 2 deletions(-)


Index: llvm/docs/WritingAnLLVMPass.html
diff -u llvm/docs/WritingAnLLVMPass.html:1.41 llvm/docs/WritingAnLLVMPass.html:1.42
--- llvm/docs/WritingAnLLVMPass.html:1.41	Fri Jul 15 14:25:12 2005
+++ llvm/docs/WritingAnLLVMPass.html	Mon Nov 28 17:25:41 2005
@@ -1217,7 +1217,7 @@
 <div class="doc_text">
 <p>The <a
 href="http://llvm.cs.uiuc.edu/doxygen/Statistic_8h-source.html"><tt>Statistic</tt></a>
-class, is designed to be an easy way to expose various success
+class is designed to be an easy way to expose various success
 metrics from passes.  These statistics are printed at the end of a
 run, when the -stats command line option is enabled on the command
 line. See the <a href="http://llvm.org/docs/ProgrammersManual.html#Statistic">Statistics section</a> in the Programmer's Manual for details. 
@@ -1593,7 +1593,7 @@
 
   <a href="mailto:sabre at nondot.org">Chris Lattner</a><br>
   <a href="http://llvm.cs.uiuc.edu">The LLVM Compiler Infrastructure</a><br>
-  Last modified: $Date: 2005/07/15 19:25:12 $
+  Last modified: $Date: 2005/11/28 23:25:41 $
 </address>
 
 </body>





From lattner at cs.uiuc.edu  Mon Nov 28 18:24:20 2005
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Mon, 28 Nov 2005 18:24:20 -0600
Subject: [llvm-commits] CVS: llvm/lib/Target/Target.td 
Message-ID: <200511290024.SAA26579@zion.cs.uiuc.edu>



Changes in directory llvm/lib/Target:

Target.td updated: 1.59 -> 1.60
---
Log message:

revert my change for the time being, which broke the build


---
Diffs of the changes:  (+1 -1)

 Target.td |    2 +-
 1 files changed, 1 insertion(+), 1 deletion(-)


Index: llvm/lib/Target/Target.td
diff -u llvm/lib/Target/Target.td:1.59 llvm/lib/Target/Target.td:1.60
--- llvm/lib/Target/Target.td:1.59	Mon Nov 28 16:42:15 2005
+++ llvm/lib/Target/Target.td	Mon Nov 28 18:24:08 2005
@@ -31,7 +31,7 @@
 def i16    : ValueType<16 ,  3>;   // 16-bit integer value
 def i32    : ValueType<32 ,  4>;   // 32-bit integer value
 def i64    : ValueType<64 ,  5>;   // 64-bit integer value
-def i128   : ValueType<128,  6>;   // 128-bit integer value
+def i128   : ValueType<128,  5>;   // 128-bit integer value
 def f32    : ValueType<32 ,  7>;   // 32-bit floating point value
 def f64    : ValueType<64 ,  8>;   // 64-bit floating point value
 def f80    : ValueType<80 ,  9>;   // 80-bit floating point value





From lattner at cs.uiuc.edu  Mon Nov 28 18:41:52 2005
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Mon, 28 Nov 2005 18:41:52 -0600
Subject: [llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCRegisterInfo.td 
Message-ID: <200511290041.SAA26688@zion.cs.uiuc.edu>



Changes in directory llvm/lib/Target/PowerPC:

PPCRegisterInfo.td updated: 1.22 -> 1.23
---
Log message:

don't say this is i128, because it isn't yet.  Hopefully nate will change
this to be something sane, but in the mean time it is unused, so safe to 
make something bogus.


---
Diffs of the changes:  (+1 -1)

 PPCRegisterInfo.td |    2 +-
 1 files changed, 1 insertion(+), 1 deletion(-)


Index: llvm/lib/Target/PowerPC/PPCRegisterInfo.td
diff -u llvm/lib/Target/PowerPC/PPCRegisterInfo.td:1.22 llvm/lib/Target/PowerPC/PPCRegisterInfo.td:1.23
--- llvm/lib/Target/PowerPC/PPCRegisterInfo.td:1.22	Sat Nov 26 16:39:34 2005
+++ llvm/lib/Target/PowerPC/PPCRegisterInfo.td	Mon Nov 28 18:41:40 2005
@@ -192,7 +192,7 @@
   F8, F9, F10, F11, F12, F13, F14, F15, F16, F17, F18, F19, F20, F21,
   F22, F23, F24, F25, F26, F27, F28, F29, F30, F31]>;
 
-def VRRC : RegisterClass<"PPC", i128, 128, [V0, V1, V2, V3, V4, V5, V6, V7, V8,
+def VRRC : RegisterClass<"PPC", f64/*FIXME*/, 128, [V0, V1, V2, V3, V4, V5, V6, V7, V8,
   V9, V10, V11, V12, V13, V14, V15, V16, V17, V18, V19, V20, V21, V22, V23,
   V24, V25, V26, V27, V28, V29, V30, V31]>;
 





From lattner at cs.uiuc.edu  Mon Nov 28 18:42:43 2005
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Mon, 28 Nov 2005 18:42:43 -0600
Subject: [llvm-commits] CVS: llvm/lib/Target/Target.td 
Message-ID: <200511290042.SAA26769@zion.cs.uiuc.edu>



Changes in directory llvm/lib/Target:

Target.td updated: 1.60 -> 1.61
---
Log message:

refix typo


---
Diffs of the changes:  (+1 -1)

 Target.td |    2 +-
 1 files changed, 1 insertion(+), 1 deletion(-)


Index: llvm/lib/Target/Target.td
diff -u llvm/lib/Target/Target.td:1.60 llvm/lib/Target/Target.td:1.61
--- llvm/lib/Target/Target.td:1.60	Mon Nov 28 18:24:08 2005
+++ llvm/lib/Target/Target.td	Mon Nov 28 18:42:30 2005
@@ -31,7 +31,7 @@
 def i16    : ValueType<16 ,  3>;   // 16-bit integer value
 def i32    : ValueType<32 ,  4>;   // 32-bit integer value
 def i64    : ValueType<64 ,  5>;   // 64-bit integer value
-def i128   : ValueType<128,  5>;   // 128-bit integer value
+def i128   : ValueType<128,  6>;   // 128-bit integer value
 def f32    : ValueType<32 ,  7>;   // 32-bit floating point value
 def f64    : ValueType<64 ,  8>;   // 64-bit floating point value
 def f80    : ValueType<80 ,  9>;   // 80-bit floating point value





From lattner at cs.uiuc.edu  Mon Nov 28 18:57:19 2005
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Mon, 28 Nov 2005 18:57:19 -0600
Subject: [llvm-commits] CVS: llvm/CREDITS.TXT 
Message-ID: <200511290057.SAA26867@zion.cs.uiuc.edu>



Changes in directory llvm:

CREDITS.TXT updated: 1.42 -> 1.43
---
Log message:

add Evan and Jim. Please edit your entries as desired.


---
Diffs of the changes:  (+8 -0)

 CREDITS.TXT |    8 ++++++++
 1 files changed, 8 insertions(+)


Index: llvm/CREDITS.TXT
diff -u llvm/CREDITS.TXT:1.42 llvm/CREDITS.TXT:1.43
--- llvm/CREDITS.TXT:1.42	Tue Aug  2 17:10:21 2005
+++ llvm/CREDITS.TXT	Mon Nov 28 18:57:06 2005
@@ -34,6 +34,10 @@
 E: ccarter at uiuc.edu
 D: Fixes to the Reassociation pass, various improvement patches
 
+N: Evan Cheng
+E: evan.cheng at apple.com
+D: X86 backend improvements
+
 N: Jeff Cohen
 E: jeffc at jolt-lang.org
 W: http://jolt-lang.org
@@ -69,6 +73,10 @@
 E: kowshik at uiuc.edu
 D: Author of the original C backend
 
+N: Jim Laskey
+E: jlaskey at apple.com
+D: Improvements to the PPC backend, instruction scheduling
+
 N: Chris Lattner
 E: sabre at nondot.org
 W: http://nondot.org/~sabre/





From lattner at cs.uiuc.edu  Mon Nov 28 19:07:04 2005
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Mon, 28 Nov 2005 19:07:04 -0600
Subject: [llvm-commits] 
	CVS: llvm/test/Regression/Transforms/Mem2Reg/2005-11-28-Crash.ll
Message-ID: <200511290107.TAA27271@zion.cs.uiuc.edu>



Changes in directory llvm/test/Regression/Transforms/Mem2Reg:

2005-11-28-Crash.ll added (r1.1)
---
Log message:

new testcase for pr670: http://llvm.cs.uiuc.edu/PR670 


---
Diffs of the changes:  (+88 -0)

 2005-11-28-Crash.ll |   88 ++++++++++++++++++++++++++++++++++++++++++++++++++++
 1 files changed, 88 insertions(+)


Index: llvm/test/Regression/Transforms/Mem2Reg/2005-11-28-Crash.ll
diff -c /dev/null llvm/test/Regression/Transforms/Mem2Reg/2005-11-28-Crash.ll:1.1
*** /dev/null	Mon Nov 28 19:07:01 2005
--- llvm/test/Regression/Transforms/Mem2Reg/2005-11-28-Crash.ll	Mon Nov 28 19:06:51 2005
***************
*** 0 ****
--- 1,88 ----
+ ; RUN: llvm-as < %s | opt -mem2reg -disable-output
+ ; PR670
+ 
+ void %printk(int, ...) {
+ entry:
+ 	%flags = alloca uint		; <uint*> [#uses=2]
+ 	br bool false, label %then.0, label %endif.0
+ 
+ then.0:		; preds = %entry
+ 	br label %endif.0
+ 
+ endif.0:		; preds = %then.0, %entry
+ 	store uint 0, uint* %flags
+ 	br label %loopentry
+ 
+ loopentry:		; preds = %endif.3, %endif.0
+ 	br bool false, label %no_exit, label %loopexit
+ 
+ no_exit:		; preds = %loopentry
+ 	br bool false, label %then.1, label %endif.1
+ 
+ then.1:		; preds = %no_exit
+ 	br bool false, label %shortcirc_done.0, label %shortcirc_next.0
+ 
+ shortcirc_next.0:		; preds = %then.1
+ 	br label %shortcirc_done.0
+ 
+ shortcirc_done.0:		; preds = %shortcirc_next.0, %then.1
+ 	br bool false, label %shortcirc_done.1, label %shortcirc_next.1
+ 
+ shortcirc_next.1:		; preds = %shortcirc_done.0
+ 	br label %shortcirc_done.1
+ 
+ shortcirc_done.1:		; preds = %shortcirc_next.1, %shortcirc_done.0
+ 	br bool false, label %shortcirc_done.2, label %shortcirc_next.2
+ 
+ shortcirc_next.2:		; preds = %shortcirc_done.1
+ 	br label %shortcirc_done.2
+ 
+ shortcirc_done.2:		; preds = %shortcirc_next.2, %shortcirc_done.1
+ 	br bool false, label %then.2, label %endif.2
+ 
+ then.2:		; preds = %shortcirc_done.2
+ 	br label %endif.2
+ 
+ endif.2:		; preds = %then.2, %shortcirc_done.2
+ 	br label %endif.1
+ 
+ endif.1:		; preds = %endif.2, %no_exit
+ 	br bool false, label %then.3, label %endif.3
+ 
+ then.3:		; preds = %endif.1
+ 	br label %endif.3
+ 
+ endif.3:		; preds = %then.3, %endif.1
+ 	br label %loopentry
+ 
+ loopexit:		; preds = %loopentry
+ 	br label %endif.4
+ 
+ then.4:		; No predecessors!
+ 	%tmp.61 = load uint* %flags		; <uint> [#uses=0]
+ 	br label %out
+ 
+ dead_block_after_goto:		; No predecessors!
+ 	br label %endif.4
+ 
+ endif.4:		; preds = %dead_block_after_goto, %loopexit
+ 	br bool false, label %then.5, label %else
+ 
+ then.5:		; preds = %endif.4
+ 	br label %endif.5
+ 
+ else:		; preds = %endif.4
+ 	br label %endif.5
+ 
+ endif.5:		; preds = %else, %then.5
+ 	br label %out
+ 
+ out:		; preds = %endif.5, %then.4
+ 	br label %return
+ 
+ after_ret:		; No predecessors!
+ 	br label %return
+ 
+ return:		; preds = %after_ret, %out
+ 	ret void
+ }





From lattner at cs.uiuc.edu  Mon Nov 28 19:07:24 2005
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Mon, 28 Nov 2005 19:07:24 -0600
Subject: [llvm-commits] CVS: llvm/include/llvm/Analysis/Dominators.h 
Message-ID: <200511290107.TAA27306@zion.cs.uiuc.edu>



Changes in directory llvm/include/llvm/Analysis:

Dominators.h updated: 1.50 -> 1.51
---
Log message:

Fix PR670: http://llvm.cs.uiuc.edu/PR670  and test/Regression/Transforms/Mem2Reg/2005-11-28-Crash.ll


---
Diffs of the changes:  (+1 -0)

 Dominators.h |    1 +
 1 files changed, 1 insertion(+)


Index: llvm/include/llvm/Analysis/Dominators.h
diff -u llvm/include/llvm/Analysis/Dominators.h:1.50 llvm/include/llvm/Analysis/Dominators.h:1.51
--- llvm/include/llvm/Analysis/Dominators.h:1.50	Fri Nov 18 01:27:33 2005
+++ llvm/include/llvm/Analysis/Dominators.h	Mon Nov 28 19:07:12 2005
@@ -311,6 +311,7 @@
     ///
     bool properlyDominates(const Node *N) const {
       const Node *IDom;
+      if (this == 0 || N == 0) return false;
       while ((IDom = N->getIDom()) != 0 && IDom != this)
         N = IDom;   // Walk up the tree
       return IDom != 0;





From lattner at cs.uiuc.edu  Mon Nov 28 19:35:02 2005
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Mon, 28 Nov 2005 19:35:02 -0600
Subject: [llvm-commits] CVS: llvm/docs/Lexicon.html 
Message-ID: <200511290135.TAA27540@zion.cs.uiuc.edu>



Changes in directory llvm/docs:

Lexicon.html updated: 1.11 -> 1.12
---
Log message:

Add "SCC" to the lexicon.  Patch provided by Marco Matthies, thanks!


---
Diffs of the changes:  (+5 -2)

 Lexicon.html |    7 +++++--
 1 files changed, 5 insertions(+), 2 deletions(-)


Index: llvm/docs/Lexicon.html
diff -u llvm/docs/Lexicon.html:1.11 llvm/docs/Lexicon.html:1.12
--- llvm/docs/Lexicon.html:1.11	Fri May 13 15:18:49 2005
+++ llvm/docs/Lexicon.html	Mon Nov 28 19:34:50 2005
@@ -53,6 +53,7 @@
     </tr>
     <tr><th colspan="8"><b>- <a href="#S">S</a> -</b></th></tr>
     <tr>
+      <td><a href="#SCC">SCC</a></td>
       <td><a href="#SCCP">SCCP</a></td>
       <td><a href="#SSA">SSA</a></td>
     </tr>
@@ -150,8 +151,10 @@
 <div class="doc_subsection"><a name="S">- S -</a></div>
 <div class="doc_text">
   <dl>
+    <dt><a name="SCC"><b>SCC</b></a></dt>
+    <dd>Strongly Connected Component</dd>
     <dt><a name="SCCP"><b>SCCP</b></a></dt>
-    <dd>Sparse Conditional Constant Propagation
+    <dd>Sparse Conditional Constant Propagation</dd>
     <dt><a name="SSA"><b>SSA</b></a></dt>
     <dd>Static Single Assignment</dd>
   </dl>
@@ -164,7 +167,7 @@
  src="http://www.w3.org/Icons/valid-html401" alt="Valid HTML 4.01!"></a><a
  href="http://llvm.cs.uiuc.edu/">The LLVM Team</a><br>
 <a href="http://llvm.cs.uiuc.edu">The LLVM Compiler Infrastructure</a><br>
-Last modified: $Date: 2005/05/13 20:18:49 $
+Last modified: $Date: 2005/11/29 01:34:50 $
 </address>
 <!-- vim: sw=2
 -->





From evan.cheng at apple.com  Mon Nov 28 22:59:58 2005
From: evan.cheng at apple.com (Evan Cheng)
Date: Mon, 28 Nov 2005 22:59:58 -0600
Subject: [llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCISelPattern.cpp 
Message-ID: <200511290459.WAA28720@zion.cs.uiuc.edu>



Changes in directory llvm/lib/Target/PowerPC:

PPCISelPattern.cpp updated: 1.192 -> 1.193
---
Log message:

Fixed a comment bug:
createPPCPatternInstructionSelector -> createPPCISelPattern


---
Diffs of the changes:  (+1 -1)

 PPCISelPattern.cpp |    2 +-
 1 files changed, 1 insertion(+), 1 deletion(-)


Index: llvm/lib/Target/PowerPC/PPCISelPattern.cpp
diff -u llvm/lib/Target/PowerPC/PPCISelPattern.cpp:1.192 llvm/lib/Target/PowerPC/PPCISelPattern.cpp:1.193
--- llvm/lib/Target/PowerPC/PPCISelPattern.cpp:1.192	Tue Nov 15 18:48:01 2005
+++ llvm/lib/Target/PowerPC/PPCISelPattern.cpp	Mon Nov 28 22:59:46 2005
@@ -1713,7 +1713,7 @@
 }
 
 
-/// createPPCPatternInstructionSelector - This pass converts an LLVM function
+/// createPPCISelPattern - This pass converts an LLVM function
 /// into a machine code representation using pattern matching and a machine
 /// description file.
 ///





From natebegeman at mac.com  Mon Nov 28 23:45:44 2005
From: natebegeman at mac.com (Nate Begeman)
Date: Mon, 28 Nov 2005 23:45:44 -0600
Subject: [llvm-commits] CVS: llvm/include/llvm/CodeGen/ValueTypes.h 
Message-ID: <200511290545.XAA29087@zion.cs.uiuc.edu>



Changes in directory llvm/include/llvm/CodeGen:

ValueTypes.h updated: 1.13 -> 1.14
---
Log message:

Add the majority of the vector machien value types we expect to support,
and make a few changes to the legalization machinery to support more than
16 types.


---
Diffs of the changes:  (+21 -3)

 ValueTypes.h |   24 +++++++++++++++++++++---
 1 files changed, 21 insertions(+), 3 deletions(-)


Index: llvm/include/llvm/CodeGen/ValueTypes.h
diff -u llvm/include/llvm/CodeGen/ValueTypes.h:1.13 llvm/include/llvm/CodeGen/ValueTypes.h:1.14
--- llvm/include/llvm/CodeGen/ValueTypes.h:1.13	Thu Nov 17 15:44:42 2005
+++ llvm/include/llvm/CodeGen/ValueTypes.h	Mon Nov 28 23:45:28 2005
@@ -48,14 +48,26 @@
                             // be refined into a target vector type, or
                             // scalarized.
 
+                            // These are 128 bit vectors of varying packed types
+    v16i8          =  14,   // 16 x i8
+    v8i16          =  15,   //  8 x i16
+    v4i32          =  16,   //  4 x i32
+    v2i64          =  17,   //  2 x i64
+
+    v4f32          =  18,   //  4 x f32
+    v2f64          =  19,   //  2 x f64
+
     LAST_VALUETYPE,         // This always remains at the end of the list.
   };
 
   static inline bool isInteger(ValueType VT) {
-    return VT >= i1 && VT <= i128;
+    return (VT >= i1 && VT <= i128) || (VT >= v16i8 && VT <= v2i64);
   }
   static inline bool isFloatingPoint(ValueType VT) {
-    return VT >= f32 && VT <= f128;
+    return (VT >= f32 && VT <= f128) || (VT >= v4f32 && VT <= v2f64);
+  }
+  static inline bool isVector(ValueType VT) {
+    return (VT >= v16i8 && VT <= v2f64);
   }
 
   static inline unsigned getSizeInBits(ValueType VT) {
@@ -70,7 +82,13 @@
     case MVT::i64 : return 64;
     case MVT::f80 : return 80;
     case MVT::f128:
-    case MVT::i128: return 128;
+    case MVT::i128: 
+    case MVT::v16i8:
+    case MVT::v8i16:
+    case MVT::v4i32:
+    case MVT::v2i64:
+    case MVT::v4f32:
+    case MVT::v2f64: return 128;
     }
   }
 





From natebegeman at mac.com  Mon Nov 28 23:45:44 2005
From: natebegeman at mac.com (Nate Begeman)
Date: Mon, 28 Nov 2005 23:45:44 -0600
Subject: [llvm-commits] CVS: llvm/include/llvm/Target/TargetLowering.h 
Message-ID: <200511290545.XAA29094@zion.cs.uiuc.edu>



Changes in directory llvm/include/llvm/Target:

TargetLowering.h updated: 1.28 -> 1.29
---
Log message:

Add the majority of the vector machien value types we expect to support,
and make a few changes to the legalization machinery to support more than
16 types.


---
Diffs of the changes:  (+2 -2)

 TargetLowering.h |    4 ++--
 1 files changed, 2 insertions(+), 2 deletions(-)


Index: llvm/include/llvm/Target/TargetLowering.h
diff -u llvm/include/llvm/Target/TargetLowering.h:1.28 llvm/include/llvm/Target/TargetLowering.h:1.29
--- llvm/include/llvm/Target/TargetLowering.h:1.28	Thu Nov 17 15:44:42 2005
+++ llvm/include/llvm/Target/TargetLowering.h	Mon Nov 28 23:45:28 2005
@@ -123,7 +123,7 @@
   LegalizeAction getTypeAction(MVT::ValueType VT) const {
     return (LegalizeAction)((ValueTypeActions >> (2*VT)) & 3);
   }
-  unsigned getValueTypeActions() const { return ValueTypeActions; }
+  unsigned long long getValueTypeActions() const { return ValueTypeActions; }
 
   /// getTypeToTransformTo - For types supported by the target, this is an
   /// identity function.  For types that must be promoted to larger types, this
@@ -441,7 +441,7 @@
   /// ValueTypeActions - This is a bitvector that contains two bits for each
   /// value type, where the two bits correspond to the LegalizeAction enum.
   /// This can be queried with "getTypeAction(VT)".
-  unsigned ValueTypeActions;
+  unsigned long long ValueTypeActions;
 
   /// TransformToType - For any value types we are promoting or expanding, this
   /// contains the value type that we are changing to.  For Expanded types, this





From natebegeman at mac.com  Mon Nov 28 23:45:44 2005
From: natebegeman at mac.com (Nate Begeman)
Date: Mon, 28 Nov 2005 23:45:44 -0600
Subject: [llvm-commits] CVS: llvm/lib/Target/Target.td TargetLowering.cpp 
Message-ID: <200511290545.XAA29090@zion.cs.uiuc.edu>



Changes in directory llvm/lib/Target:

Target.td updated: 1.61 -> 1.62
TargetLowering.cpp updated: 1.14 -> 1.15
---
Log message:

Add the majority of the vector machien value types we expect to support,
and make a few changes to the legalization machinery to support more than
16 types.


---
Diffs of the changes:  (+10 -4)

 Target.td          |    8 +++++++-
 TargetLowering.cpp |    6 +++---
 2 files changed, 10 insertions(+), 4 deletions(-)


Index: llvm/lib/Target/Target.td
diff -u llvm/lib/Target/Target.td:1.61 llvm/lib/Target/Target.td:1.62
--- llvm/lib/Target/Target.td:1.61	Mon Nov 28 18:42:30 2005
+++ llvm/lib/Target/Target.td	Mon Nov 28 23:45:29 2005
@@ -38,7 +38,13 @@
 def f128   : ValueType<128, 10>;   // 128-bit floating point value
 def FlagVT : ValueType<0  , 11>;   // Condition code or machine flag
 def isVoid : ValueType<0  , 12>;   // Produces no value
-def Vector : ValueType<0  , 13>;   // Abstract vector type
+def Vector : ValueType<0  , 13>;   // Abstract vector value
+def v16i8  : ValueType<128, 14>;   // 16 x i8  vector value
+def v8i16  : ValueType<128, 15>;   //  8 x i16 vector value
+def v4i32  : ValueType<128, 16>;   //  4 x i32 vector value
+def v2i64  : ValueType<128, 17>;   //  2 x i64 vector value
+def v4f32  : ValueType<128, 18>;   //  4 x f32 vector value
+def v2f64  : ValueType<128, 19>;   //  2 x f64 vector value
 
 //===----------------------------------------------------------------------===//
 // Register file description - These classes are used to fill in the target


Index: llvm/lib/Target/TargetLowering.cpp
diff -u llvm/lib/Target/TargetLowering.cpp:1.14 llvm/lib/Target/TargetLowering.cpp:1.15
--- llvm/lib/Target/TargetLowering.cpp:1.14	Mon Nov 21 19:29:36 2005
+++ llvm/lib/Target/TargetLowering.cpp	Mon Nov 28 23:45:29 2005
@@ -42,8 +42,8 @@
                                TargetLowering::LegalizeAction Action,
                                TargetLowering &TLI,
                                MVT::ValueType *TransformToType,
-                               unsigned &ValueTypeActions) {
-  ValueTypeActions |= Action << (VT*2);
+                               unsigned long long &ValueTypeActions) {
+  ValueTypeActions |= (unsigned long long)Action << (VT*2);
   if (Action == TargetLowering::Promote) {
     MVT::ValueType PromoteTo;
     if (VT == MVT::f32)
@@ -75,7 +75,7 @@
 /// computeRegisterProperties - Once all of the register classes are added,
 /// this allows us to compute derived properties we expose.
 void TargetLowering::computeRegisterProperties() {
-  assert(MVT::LAST_VALUETYPE <= 16 &&
+  assert(MVT::LAST_VALUETYPE <= 32 &&
          "Too many value types for ValueTypeActions to hold!");
 
   // Everything defaults to one.





From natebegeman at mac.com  Mon Nov 28 23:45:44 2005
From: natebegeman at mac.com (Nate Begeman)
Date: Mon, 28 Nov 2005 23:45:44 -0600
Subject: [llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCRegisterInfo.td 
Message-ID: <200511290545.XAA29093@zion.cs.uiuc.edu>



Changes in directory llvm/lib/Target/PowerPC:

PPCRegisterInfo.td updated: 1.23 -> 1.24
---
Log message:

Add the majority of the vector machien value types we expect to support,
and make a few changes to the legalization machinery to support more than
16 types.


---
Diffs of the changes:  (+1 -1)

 PPCRegisterInfo.td |    2 +-
 1 files changed, 1 insertion(+), 1 deletion(-)


Index: llvm/lib/Target/PowerPC/PPCRegisterInfo.td
diff -u llvm/lib/Target/PowerPC/PPCRegisterInfo.td:1.23 llvm/lib/Target/PowerPC/PPCRegisterInfo.td:1.24
--- llvm/lib/Target/PowerPC/PPCRegisterInfo.td:1.23	Mon Nov 28 18:41:40 2005
+++ llvm/lib/Target/PowerPC/PPCRegisterInfo.td	Mon Nov 28 23:45:29 2005
@@ -192,7 +192,7 @@
   F8, F9, F10, F11, F12, F13, F14, F15, F16, F17, F18, F19, F20, F21,
   F22, F23, F24, F25, F26, F27, F28, F29, F30, F31]>;
 
-def VRRC : RegisterClass<"PPC", f64/*FIXME*/, 128, [V0, V1, V2, V3, V4, V5, V6, V7, V8,
+def VRRC : RegisterClass<"PPC", v4f32, 128, [V0, V1, V2, V3, V4, V5, V6, V7, V8,
   V9, V10, V11, V12, V13, V14, V15, V16, V17, V18, V19, V20, V21, V22, V23,
   V24, V25, V26, V27, V28, V29, V30, V31]>;
 





From natebegeman at mac.com  Mon Nov 28 23:45:44 2005
From: natebegeman at mac.com (Nate Begeman)
Date: Mon, 28 Nov 2005 23:45:44 -0600
Subject: [llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp 
Message-ID: <200511290545.XAA29096@zion.cs.uiuc.edu>



Changes in directory llvm/lib/CodeGen/SelectionDAG:

LegalizeDAG.cpp updated: 1.215 -> 1.216
---
Log message:

Add the majority of the vector machien value types we expect to support,
and make a few changes to the legalization machinery to support more than
16 types.


---
Diffs of the changes:  (+2 -2)

 LegalizeDAG.cpp |    4 ++--
 1 files changed, 2 insertions(+), 2 deletions(-)


Index: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.215 llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.216
--- llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.215	Tue Nov 22 12:16:00 2005
+++ llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp	Mon Nov 28 23:45:29 2005
@@ -52,7 +52,7 @@
   /// ValueTypeActions - This is a bitvector that contains two bits for each
   /// value type, where the two bits correspond to the LegalizeAction enum.
   /// This can be queried with "getTypeAction(VT)".
-  unsigned ValueTypeActions;
+  unsigned long long ValueTypeActions;
 
   /// NeedsAnotherIteration - This is set when we expand a large integer
   /// operation into smaller integer operations, but the smaller operations are
@@ -161,7 +161,7 @@
 SelectionDAGLegalize::SelectionDAGLegalize(SelectionDAG &dag)
   : TLI(dag.getTargetLoweringInfo()), DAG(dag),
     ValueTypeActions(TLI.getValueTypeActions()) {
-  assert(MVT::LAST_VALUETYPE <= 16 &&
+  assert(MVT::LAST_VALUETYPE <= 32 &&
          "Too many value types for ValueTypeActions to hold!");
 }
 





From natebegeman at mac.com  Mon Nov 28 23:45:44 2005
From: natebegeman at mac.com (Nate Begeman)
Date: Mon, 28 Nov 2005 23:45:44 -0600
Subject: [llvm-commits] CVS: llvm/lib/CodeGen/ValueTypes.cpp 
Message-ID: <200511290545.XAA29108@zion.cs.uiuc.edu>



Changes in directory llvm/lib/CodeGen:

ValueTypes.cpp updated: 1.5 -> 1.6
---
Log message:

Add the majority of the vector machien value types we expect to support,
and make a few changes to the legalization machinery to support more than
16 types.


---
Diffs of the changes:  (+6 -0)

 ValueTypes.cpp |    6 ++++++
 1 files changed, 6 insertions(+)


Index: llvm/lib/CodeGen/ValueTypes.cpp
diff -u llvm/lib/CodeGen/ValueTypes.cpp:1.5 llvm/lib/CodeGen/ValueTypes.cpp:1.6
--- llvm/lib/CodeGen/ValueTypes.cpp:1.5	Fri Nov 18 18:36:38 2005
+++ llvm/lib/CodeGen/ValueTypes.cpp	Mon Nov 28 23:45:28 2005
@@ -34,6 +34,12 @@
   case MVT::Other: return "ch";
   case MVT::Flag:  return "flag";
   case MVT::Vector:return "vec";
+  case MVT::v16i8: return "v16i8";
+  case MVT::v8i16: return "v8i16";
+  case MVT::v4i32: return "v4i32";
+  case MVT::v2i64: return "v2i64";
+  case MVT::v4f32: return "v4f32";
+  case MVT::v2f64: return "v2f64";
   }
 }
 





From lattner at cs.uiuc.edu  Tue Nov 29 00:15:51 2005
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Tue, 29 Nov 2005 00:15:51 -0600
Subject: [llvm-commits] CVS: llvm/include/llvm/CodeGen/SelectionDAG.h
	SelectionDAGNodes.h 
Message-ID: <200511290615.AAA29325@zion.cs.uiuc.edu>



Changes in directory llvm/include/llvm/CodeGen:

SelectionDAG.h updated: 1.70 -> 1.71
SelectionDAGNodes.h updated: 1.78 -> 1.79
---
Log message:

Add support for a new STRING and LOCATION node for line number support, patch 
contributed by Daniel Berlin, with a few cleanups here and there by me.


---
Diffs of the changes:  (+24 -1)

 SelectionDAG.h      |    2 ++
 SelectionDAGNodes.h |   23 ++++++++++++++++++++++-
 2 files changed, 24 insertions(+), 1 deletion(-)


Index: llvm/include/llvm/CodeGen/SelectionDAG.h
diff -u llvm/include/llvm/CodeGen/SelectionDAG.h:1.70 llvm/include/llvm/CodeGen/SelectionDAG.h:1.71
--- llvm/include/llvm/CodeGen/SelectionDAG.h:1.70	Fri Nov 18 19:42:10 2005
+++ llvm/include/llvm/CodeGen/SelectionDAG.h	Tue Nov 29 00:15:39 2005
@@ -105,6 +105,7 @@
   /// argument, it is used as the seed for node deletion.
   void RemoveDeadNodes(SDNode *N = 0);
 
+  SDOperand getString(const std::string &Val);
   SDOperand getConstant(uint64_t Val, MVT::ValueType VT);
   SDOperand getTargetConstant(uint64_t Val, MVT::ValueType VT);
   SDOperand getConstantFP(double Val, MVT::ValueType VT);
@@ -406,6 +407,7 @@
   std::vector<SDNode*> ValueTypeNodes;
   std::map<std::string, SDNode*> ExternalSymbols;
   std::map<std::string, SDNode*> TargetExternalSymbols;
+  std::map<std::string, StringSDNode*> StringNodes;
   std::map<std::pair<unsigned,
                      std::pair<MVT::ValueType, std::vector<SDOperand> > >,
            SDNode*> OneResultNodes;


Index: llvm/include/llvm/CodeGen/SelectionDAGNodes.h
diff -u llvm/include/llvm/CodeGen/SelectionDAGNodes.h:1.78 llvm/include/llvm/CodeGen/SelectionDAGNodes.h:1.79
--- llvm/include/llvm/CodeGen/SelectionDAGNodes.h:1.78	Tue Nov 22 12:15:59 2005
+++ llvm/include/llvm/CodeGen/SelectionDAGNodes.h	Tue Nov 29 00:15:39 2005
@@ -63,7 +63,8 @@
     AssertSext, AssertZext,
 
     // Various leaf nodes.
-    Constant, ConstantFP, GlobalAddress, FrameIndex, ConstantPool,
+    Constant, ConstantFP, STRING,
+    GlobalAddress, FrameIndex, ConstantPool,
     BasicBlock, ExternalSymbol, VALUETYPE, CONDCODE, Register,
     
     // TargetConstant - Like Constant, but the DAG does not do any folding or
@@ -341,6 +342,12 @@
     // HANDLENODE node - Used as a handle for various purposes.
     HANDLENODE,
 
+    // LOCATION - This node is used to represent a source location for debug
+    // info.  It takes token chain as input, then a line number, then a column
+    // number, then a filename, then a working dir.  It produces a token chain
+    // as output.
+    LOCATION,
+    
     // BUILTIN_OP_END - This must be the last enum value in this list.
     BUILTIN_OP_END,
   };
@@ -846,6 +853,20 @@
   SDOperand getValue() const { return getOperand(0); }
 };
 
+class StringSDNode : public SDNode {
+  std::string Value;
+protected:
+  friend class SelectionDAG;
+  StringSDNode(const std::string &val)
+    : SDNode(ISD::STRING, MVT::Other), Value(val) {
+  }
+public:
+  const std::string &getValue() const { return Value; }
+  static bool classof(const StringSDNode *) { return true; }
+  static bool classof(const SDNode *N) {
+    return N->getOpcode() == ISD::STRING;
+  }
+};  
 
 class ConstantSDNode : public SDNode {
   uint64_t Value;





From lattner at cs.uiuc.edu  Tue Nov 29 00:16:34 2005
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Tue, 29 Nov 2005 00:16:34 -0600
Subject: [llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCISelLowering.cpp 
Message-ID: <200511290616.AAA29373@zion.cs.uiuc.edu>



Changes in directory llvm/lib/Target/PowerPC:

PPCISelLowering.cpp updated: 1.45 -> 1.46
---
Log message:

No targets support line number info yet.



---
Diffs of the changes:  (+3 -0)

 PPCISelLowering.cpp |    3 +++
 1 files changed, 3 insertions(+)


Index: llvm/lib/Target/PowerPC/PPCISelLowering.cpp
diff -u llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.45 llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.46
--- llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.45	Thu Nov 17 12:55:48 2005
+++ llvm/lib/Target/PowerPC/PPCISelLowering.cpp	Tue Nov 29 00:16:21 2005
@@ -90,6 +90,9 @@
 
   // PowerPC does not have truncstore for i1.
   setOperationAction(ISD::TRUNCSTORE, MVT::i1, Promote);
+
+  // PowerPC doesn't have line number support yet.
+  setOperationAction(ISD::LOCATION, MVT::Other, Expand);
   
   // We want to legalize GlobalAddress into the appropriate instructions to
   // materialize the address.





From lattner at cs.uiuc.edu  Tue Nov 29 00:16:35 2005
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Tue, 29 Nov 2005 00:16:35 -0600
Subject: [llvm-commits] CVS: llvm/lib/Target/Alpha/AlphaISelLowering.cpp 
Message-ID: <200511290616.AAA29377@zion.cs.uiuc.edu>



Changes in directory llvm/lib/Target/Alpha:

AlphaISelLowering.cpp updated: 1.8 -> 1.9
---
Log message:

No targets support line number info yet.



---
Diffs of the changes:  (+3 -0)

 AlphaISelLowering.cpp |    3 +++
 1 files changed, 3 insertions(+)


Index: llvm/lib/Target/Alpha/AlphaISelLowering.cpp
diff -u llvm/lib/Target/Alpha/AlphaISelLowering.cpp:1.8 llvm/lib/Target/Alpha/AlphaISelLowering.cpp:1.9
--- llvm/lib/Target/Alpha/AlphaISelLowering.cpp:1.8	Wed Nov  9 13:17:08 2005
+++ llvm/lib/Target/Alpha/AlphaISelLowering.cpp	Tue Nov 29 00:16:21 2005
@@ -97,6 +97,9 @@
 
   //Doesn't work yet
   setOperationAction(ISD::SETCC, MVT::f32,   Promote);
+
+  // We don't have line number support yet.
+  setOperationAction(ISD::LOCATION, MVT::Other, Expand);
   
   computeRegisterProperties();
   





From lattner at cs.uiuc.edu  Tue Nov 29 00:16:35 2005
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Tue, 29 Nov 2005 00:16:35 -0600
Subject: [llvm-commits] CVS: llvm/lib/Target/X86/X86ISelLowering.cpp 
Message-ID: <200511290616.AAA29383@zion.cs.uiuc.edu>



Changes in directory llvm/lib/Target/X86:

X86ISelLowering.cpp updated: 1.4 -> 1.5
---
Log message:

No targets support line number info yet.



---
Diffs of the changes:  (+3 -0)

 X86ISelLowering.cpp |    3 +++
 1 files changed, 3 insertions(+)


Index: llvm/lib/Target/X86/X86ISelLowering.cpp
diff -u llvm/lib/Target/X86/X86ISelLowering.cpp:1.4 llvm/lib/Target/X86/X86ISelLowering.cpp:1.5
--- llvm/lib/Target/X86/X86ISelLowering.cpp:1.4	Sun Nov 20 16:57:19 2005
+++ llvm/lib/Target/X86/X86ISelLowering.cpp	Tue Nov 29 00:16:21 2005
@@ -116,6 +116,9 @@
   setOperationAction(ISD::SELECT           , MVT::i1   , Promote);
   setOperationAction(ISD::SELECT           , MVT::i8   , Promote);
 
+  // We don't have line number support yet.
+  setOperationAction(ISD::LOCATION, MVT::Other, Expand);
+
   if (X86ScalarSSE) {
     // Set up the FP register classes.
     addRegisterClass(MVT::f32, X86::V4F4RegisterClass);





From lattner at cs.uiuc.edu  Tue Nov 29 00:16:35 2005
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Tue, 29 Nov 2005 00:16:35 -0600
Subject: [llvm-commits] CVS: llvm/lib/Target/IA64/IA64ISelLowering.cpp 
Message-ID: <200511290616.AAA29381@zion.cs.uiuc.edu>



Changes in directory llvm/lib/Target/IA64:

IA64ISelLowering.cpp updated: 1.3 -> 1.4
---
Log message:

No targets support line number info yet.



---
Diffs of the changes:  (+3 -0)

 IA64ISelLowering.cpp |    3 +++
 1 files changed, 3 insertions(+)


Index: llvm/lib/Target/IA64/IA64ISelLowering.cpp
diff -u llvm/lib/Target/IA64/IA64ISelLowering.cpp:1.3 llvm/lib/Target/IA64/IA64ISelLowering.cpp:1.4
--- llvm/lib/Target/IA64/IA64ISelLowering.cpp:1.3	Fri Nov  4 04:01:11 2005
+++ llvm/lib/Target/IA64/IA64ISelLowering.cpp	Tue Nov 29 00:16:21 2005
@@ -72,6 +72,9 @@
       setOperationAction(ISD::FCOS , MVT::f32, Expand);
       setOperationAction(ISD::FSQRT, MVT::f32, Expand);
 
+      // We don't have line number support yet.
+      setOperationAction(ISD::LOCATION, MVT::Other, Expand);
+
       //IA64 has these, but they are not implemented
       setOperationAction(ISD::CTTZ , MVT::i64  , Expand);
       setOperationAction(ISD::CTLZ , MVT::i64  , Expand);





From natebegeman at mac.com  Tue Nov 29 00:19:50 2005
From: natebegeman at mac.com (Nate Begeman)
Date: Tue, 29 Nov 2005 00:19:50 -0600
Subject: [llvm-commits] CVS: llvm/utils/TableGen/CodeGenTarget.cpp 
Message-ID: <200511290619.AAA29452@zion.cs.uiuc.edu>



Changes in directory llvm/utils/TableGen:

CodeGenTarget.cpp updated: 1.43 -> 1.44
---
Log message:

Add the new vector types to tablegen


---
Diffs of the changes:  (+12 -0)

 CodeGenTarget.cpp |   12 ++++++++++++
 1 files changed, 12 insertions(+)


Index: llvm/utils/TableGen/CodeGenTarget.cpp
diff -u llvm/utils/TableGen/CodeGenTarget.cpp:1.43 llvm/utils/TableGen/CodeGenTarget.cpp:1.44
--- llvm/utils/TableGen/CodeGenTarget.cpp:1.43	Sat Nov 19 01:48:33 2005
+++ llvm/utils/TableGen/CodeGenTarget.cpp	Tue Nov 29 00:19:38 2005
@@ -46,6 +46,12 @@
   case MVT::f80:   return "f80";
   case MVT::f128:  return "f128";
   case MVT::isVoid:return "void";
+  case MVT::v16i8: return "v16i8";
+  case MVT::v8i16: return "v8i16";
+  case MVT::v4i32: return "v4i32";
+  case MVT::v2i64: return "v2i64";
+  case MVT::v4f32: return "v4f32";
+  case MVT::v2f64: return "v2f64";
   default: assert(0 && "ILLEGAL VALUE TYPE!"); return "";
   }
 }
@@ -64,6 +70,12 @@
   case MVT::f80:   return "f80";
   case MVT::f128:  return "f128";
   case MVT::isVoid:return "isVoid";
+  case MVT::v16i8: return "v16i8";
+  case MVT::v8i16: return "v8i16";
+  case MVT::v4i32: return "v4i32";
+  case MVT::v2i64: return "v2i64";
+  case MVT::v4f32: return "v4f32";
+  case MVT::v2f64: return "v2f64";
   default: assert(0 && "ILLEGAL VALUE TYPE!"); return "";
   }
 }





From lattner at cs.uiuc.edu  Tue Nov 29 00:21:18 2005
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Tue, 29 Nov 2005 00:21:18 -0600
Subject: [llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
	SelectionDAG.cpp SelectionDAGISel.cpp SelectionDAGPrinter.cpp
Message-ID: <200511290621.AAA29525@zion.cs.uiuc.edu>



Changes in directory llvm/lib/CodeGen/SelectionDAG:

LegalizeDAG.cpp updated: 1.216 -> 1.217
SelectionDAG.cpp updated: 1.215 -> 1.216
SelectionDAGISel.cpp updated: 1.105 -> 1.106
SelectionDAGPrinter.cpp updated: 1.28 -> 1.29
---
Log message:

Add support for a new STRING and LOCATION node for line number support, patch 
contributed by Daniel Berlin, with a few cleanups here and there by me.



---
Diffs of the changes:  (+113 -2)

 LegalizeDAG.cpp         |   27 ++++++++++++++++++
 SelectionDAG.cpp        |   16 +++++++++++
 SelectionDAGISel.cpp    |   69 ++++++++++++++++++++++++++++++++++++++++++++++--
 SelectionDAGPrinter.cpp |    3 ++
 4 files changed, 113 insertions(+), 2 deletions(-)


Index: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.216 llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.217
--- llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.216	Mon Nov 28 23:45:29 2005
+++ llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp	Tue Nov 29 00:21:05 2005
@@ -540,6 +540,7 @@
   case ISD::CONDCODE:
   case ISD::VALUETYPE:
   case ISD::SRCVALUE:
+  case ISD::STRING:
     switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
     default: assert(0 && "This action is not supported yet!");
     case TargetLowering::Custom: {
@@ -601,6 +602,32 @@
     }
     break;
   }
+
+  case ISD::LOCATION:
+    assert(Node->getNumOperands() == 5 && "Invalid LOCATION node!");
+    Tmp1 = LegalizeOp(Node->getOperand(0));  // Legalize the input chain.
+    
+    switch (TLI.getOperationAction(ISD::LOCATION, MVT::Other)) {
+    case TargetLowering::Promote:
+    default: assert(0 && "This action is not supported yet!");
+    case TargetLowering::Expand:
+      // If the target doesn't support line numbers, ignore this node.
+      Result = Tmp1;
+      break;
+    case TargetLowering::Legal:
+      if (Tmp1 != Node->getOperand(0)) {
+        std::vector<SDOperand> Ops;
+        Ops.push_back(Tmp1);
+        Ops.push_back(Node->getOperand(1));  // line # must be legal.
+        Ops.push_back(Node->getOperand(2));  // col # must be legal.
+        Ops.push_back(Node->getOperand(3));  // filename must be legal.
+        Ops.push_back(Node->getOperand(4));  // working dir # must be legal.
+        Result = DAG.getNode(ISD::LOCATION, MVT::Other, Ops);
+      }
+      break;
+    }
+    break;
+
   case ISD::Constant:
     // We know we don't need to expand constants here, constants only have one
     // value and we check that it is fine above.


Index: llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp:1.215 llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp:1.216
--- llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp:1.215	Tue Nov 22 12:16:00 2005
+++ llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp	Tue Nov 29 00:21:05 2005
@@ -274,6 +274,9 @@
     Erased = ConstantFPs.erase(std::make_pair(V, N->getValueType(0)));
     break;
   }
+  case ISD::STRING:
+    Erased = StringNodes.erase(cast<StringSDNode>(N)->getValue());
+    break;
   case ISD::CONDCODE:
     assert(CondCodeNodes[cast<CondCodeSDNode>(N)->get()] &&
            "Cond code doesn't exist!");
@@ -448,6 +451,15 @@
   return SDOperand(N, 0);
 }
 
+SDOperand SelectionDAG::getString(const std::string &Val) {
+  StringSDNode *&N = StringNodes[Val];
+  if (!N) {
+    N = new StringSDNode(Val);
+    AllNodes.push_back(N);
+  }
+  return SDOperand(N, 0);
+}
+
 SDOperand SelectionDAG::getTargetConstant(uint64_t Val, MVT::ValueType VT) {
   assert(MVT::isInteger(VT) && "Cannot create FP integer constant!");
   // Mask out any bits that are not valid for this constant.
@@ -1670,6 +1682,7 @@
   case ISD::READCYCLECOUNTER: return "ReadCycleCounter";
   case ISD::SRCVALUE:      return "SrcValue";
   case ISD::VALUETYPE:     return "ValueType";
+  case ISD::STRING:        return "String";
   case ISD::EntryToken:    return "EntryToken";
   case ISD::TokenFactor:   return "TokenFactor";
   case ISD::AssertSext:    return "AssertSext";
@@ -1787,6 +1800,9 @@
   case ISD::READIO: return "readio";
   case ISD::WRITEIO: return "writeio";
 
+  // Debug info
+  case ISD::LOCATION: return "location";
+
   case ISD::CONDCODE:
     switch (cast<CondCodeSDNode>(this)->get()) {
     default: assert(0 && "Unknown setcc condition!");


Index: llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.105 llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.106
--- llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.105	Tue Nov 22 12:16:00 2005
+++ llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp	Tue Nov 29 00:21:05 2005
@@ -17,6 +17,7 @@
 #include "llvm/Constants.h"
 #include "llvm/DerivedTypes.h"
 #include "llvm/Function.h"
+#include "llvm/GlobalVariable.h"
 #include "llvm/Instructions.h"
 #include "llvm/Intrinsics.h"
 #include "llvm/CodeGen/IntrinsicLowering.h"
@@ -719,6 +720,44 @@
   CurMBB->getParent()->getFrameInfo()->CreateVariableSizedObject();
 }
 
+/// getStringValue - Turn an LLVM constant pointer that eventually points to a
+/// global into a string value.  Return an empty string if we can't do it.
+///
+static std::string getStringValue(Value *V, unsigned Offset = 0) {
+  if (GlobalVariable *GV = dyn_cast<GlobalVariable>(V)) {
+    if (GV->hasInitializer() && isa<ConstantArray>(GV->getInitializer())) {
+      ConstantArray *Init = cast<ConstantArray>(GV->getInitializer());
+      if (Init->isString()) {
+        std::string Result = Init->getAsString();
+        if (Offset < Result.size()) {
+          // If we are pointing INTO The string, erase the beginning...
+          Result.erase(Result.begin(), Result.begin()+Offset);
+
+          // Take off the null terminator, and any string fragments after it.
+          std::string::size_type NullPos = Result.find_first_of((char)0);
+          if (NullPos != std::string::npos)
+            Result.erase(Result.begin()+NullPos, Result.end());
+          return Result;
+        }
+      }
+    }
+  } else if (Constant *C = dyn_cast<Constant>(V)) {
+    if (GlobalValue *GV = dyn_cast<GlobalValue>(C))
+      return getStringValue(GV, Offset);
+    else if (ConstantExpr *CE = dyn_cast<ConstantExpr>(C)) {
+      if (CE->getOpcode() == Instruction::GetElementPtr) {
+        // Turn a gep into the specified offset.
+        if (CE->getNumOperands() == 3 &&
+            cast<Constant>(CE->getOperand(1))->isNullValue() &&
+            isa<ConstantInt>(CE->getOperand(2))) {
+          return getStringValue(CE->getOperand(0),
+                   Offset+cast<ConstantInt>(CE->getOperand(2))->getRawValue());
+        }
+      }
+    }
+  }
+  return "";
+}
 
 void SelectionDAGLowering::visitLoad(LoadInst &I) {
   SDOperand Ptr = getValue(I.getOperand(0));
@@ -813,11 +852,37 @@
     return 0;
     
   case Intrinsic::dbg_stoppoint:
+    {
     if (TLI.getTargetMachine().getIntrinsicLowering().EmitDebugFunctions())
       return "llvm_debugger_stop";
-    if (I.getType() != Type::VoidTy)
-      setValue(&I, DAG.getNode(ISD::UNDEF, TLI.getValueType(I.getType())));
+    
+    std::string fname = "<unknown>";
+    std::vector<SDOperand> Ops;
+
+    // Pull the filename out of the the compilation unit.
+    const GlobalVariable *cunit = dyn_cast<GlobalVariable>(I.getOperand(4));
+    if (cunit && cunit->hasInitializer()) {
+      ConstantStruct *CS = dyn_cast<ConstantStruct>(cunit->getInitializer());
+      if (CS->getNumOperands() > 0) {
+          std::string dirname = getStringValue(CS->getOperand(4));
+          fname = dirname + "/" + getStringValue(CS->getOperand(3));
+        }
+      }
+    // Input Chain
+    Ops.push_back(getRoot());
+    
+    // line number
+    Ops.push_back(getValue(I.getOperand(2)));
+   
+    // column
+    Ops.push_back(getValue(I.getOperand(3)));
+
+    // filename
+    Ops.push_back(DAG.getString(fname));
+    Ops.push_back(DAG.getString(""));
+    DAG.setRoot(DAG.getNode(ISD::LOCATION, MVT::Other, Ops));
     return 0;
+  }
   case Intrinsic::dbg_region_start:
     if (TLI.getTargetMachine().getIntrinsicLowering().EmitDebugFunctions())
       return "llvm_dbg_region_start";


Index: llvm/lib/CodeGen/SelectionDAG/SelectionDAGPrinter.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/SelectionDAGPrinter.cpp:1.28 llvm/lib/CodeGen/SelectionDAG/SelectionDAGPrinter.cpp:1.29
--- llvm/lib/CodeGen/SelectionDAG/SelectionDAGPrinter.cpp:1.28	Sat Nov 19 21:45:52 2005
+++ llvm/lib/CodeGen/SelectionDAG/SelectionDAGPrinter.cpp	Tue Nov 29 00:21:05 2005
@@ -98,7 +98,10 @@
       Op += "<null:" + itostr(M->getOffset()) + ">";
   } else if (const VTSDNode *N = dyn_cast<VTSDNode>(Node)) {
     Op = Op + " VT=" + getValueTypeString(N->getVT());
+  } else if (const StringSDNode *N = dyn_cast<StringSDNode>(Node)) {
+    Op = Op + "\"" + N->getValue() + "\"";
   }
+  
   return Op;
 }
 





From natebegeman at mac.com  Tue Nov 29 02:04:56 2005
From: natebegeman at mac.com (Nate Begeman)
Date: Tue, 29 Nov 2005 02:04:56 -0600
Subject: [llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCInstrFormats.td
	PPCInstrInfo.td 
Message-ID: <200511290804.CAA29990@zion.cs.uiuc.edu>



Changes in directory llvm/lib/Target/PowerPC:

PPCInstrFormats.td updated: 1.57 -> 1.58
PPCInstrInfo.td updated: 1.145 -> 1.146
---
Log message:

Add the remainder of the AltiVec 4 x float instructions.  Further
enhancements will be necessary to teach the code generator that since
there is no fmul, it will have to do vmaddfp, adding +0.0.


---
Diffs of the changes:  (+61 -14)

 PPCInstrFormats.td |   14 ++++++++++++
 PPCInstrInfo.td    |   61 ++++++++++++++++++++++++++++++++++++++++-------------
 2 files changed, 61 insertions(+), 14 deletions(-)


Index: llvm/lib/Target/PowerPC/PPCInstrFormats.td
diff -u llvm/lib/Target/PowerPC/PPCInstrFormats.td:1.57 llvm/lib/Target/PowerPC/PPCInstrFormats.td:1.58
--- llvm/lib/Target/PowerPC/PPCInstrFormats.td:1.57	Sat Nov 26 16:39:34 2005
+++ llvm/lib/Target/PowerPC/PPCInstrFormats.td	Tue Nov 29 02:04:45 2005
@@ -582,6 +582,20 @@
   let Inst{21-31} = xo;
 }
 
+class VXForm_2<bits<11> xo, dag OL, string asmstr,
+               InstrItinClass itin, list<dag> pattern>
+    : I<4, OL, asmstr, itin> {
+  bits<5> VD;
+  bits<5> VB;
+  
+  let Pattern = pattern;
+  
+  let Inst{6-10}  = VD;
+  let Inst{11-15} = 0;
+  let Inst{16-20} = VB;
+  let Inst{21-31} = xo;
+}
+
 // E-4 VXR-Form
 class VXRForm_1<bits<10> xo, bit rc, dag OL, string asmstr,
                InstrItinClass itin, list<dag> pattern>


Index: llvm/lib/Target/PowerPC/PPCInstrInfo.td
diff -u llvm/lib/Target/PowerPC/PPCInstrInfo.td:1.145 llvm/lib/Target/PowerPC/PPCInstrInfo.td:1.146
--- llvm/lib/Target/PowerPC/PPCInstrInfo.td:1.145	Sat Nov 26 16:39:34 2005
+++ llvm/lib/Target/PowerPC/PPCInstrInfo.td	Tue Nov 29 02:04:45 2005
@@ -767,32 +767,65 @@
                       []>, isPPC64;
 
 // VA-Form instructions.  3-input AltiVec ops.
-def VMADDFP: VAForm_1<46, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB, VRRC:$vC),
-                      "vmaddfp $vD, $vA, $vB, $vC", VecFP,
-                      []>;
+def VMADDFP : VAForm_1<46, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB, VRRC:$vC),
+                       "vmaddfp $vD, $vA, $vC, $vB", VecFP,
+                       [(set VRRC:$vD, (fadd (fmul VRRC:$vA, VRRC:$vC),
+                                             VRRC:$vB))]>;
+def VNMSUBFP: VAForm_1<47, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB, VRRC:$vC),
+                      "vnmsubfp $vD, $vA, $vC, $vB", VecFP,
+                      [(set VRRC:$vD, (fneg (fsub (fmul VRRC:$vA, 
+                                                        VRRC:$vC),
+                                                  VRRC:$vB)))]>;
 
 // VX-Form instructions.  AltiVec arithmetic ops.
 def VADDFP : VXForm_1<10, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
                       "vaddfp $vD, $vA, $vB", VecFP,
-                      []>;
-def VADDUWM: VXForm_1<128, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
-                      "vadduwm $vD, $vA, $vB", VecGeneral,
-                      []>;
-def VAND   : VXForm_1<1028, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
-                      "vand $vD, $vA, $vB", VecGeneral,
-                      []>;
+                      [(set VRRC:$vD, (fadd VRRC:$vA, VRRC:$vB))]>;
 def VCFSX  : VXForm_1<842, (ops VRRC:$vD, u5imm:$UIMM, VRRC:$vB),
                       "vcfsx $vD, $vB, $UIMM", VecFP,
                       []>;
 def VCFUX  : VXForm_1<778, (ops VRRC:$vD, u5imm:$UIMM, VRRC:$vB),
                       "vcfux $vD, $vB, $UIMM", VecFP,
                       []>;
-def VOR    : VXForm_1<1156, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
-                      "vor $vD, $vA, $vB", VecGeneral,
+def VCTSXS : VXForm_1<970, (ops VRRC:$vD, u5imm:$UIMM, VRRC:$vB),
+                      "vctsxs $vD, $vB, $UIMM", VecFP,
                       []>;
-def VXOR   : VXForm_1<1220, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
-                      "vxor $vD, $vA, $vB", VecGeneral,
+def VCTUXS : VXForm_1<906, (ops VRRC:$vD, u5imm:$UIMM, VRRC:$vB),
+                      "vctuxs $vD, $vB, $UIMM", VecFP,
                       []>;
+def VEXPTEFP : VXForm_2<394, (ops VRRC:$vD, VRRC:$vB),
+                        "vexptefp $vD, $vB", VecFP,
+                        []>;
+def VLOGEFP  : VXForm_2<458, (ops VRRC:$vD, VRRC:$vB),
+                        "vlogefp $vD, $vB", VecFP,
+                        []>;
+def VMAXFP : VXForm_1<1034, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
+                      "vmaxfp $vD, $vA, $vB", VecFP,
+                      []>;
+def VMINFP : VXForm_1<1098, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
+                      "vminfp $vD, $vA, $vB", VecFP,
+                      []>;
+def VREFP  : VXForm_2<266, (ops VRRC:$vD, VRRC:$vB),
+                      "vrefp $vD, $vB", VecFP,
+                      []>;
+def VRFIM  : VXForm_2<714, (ops VRRC:$vD, VRRC:$vB),
+                      "vrfim $vD, $vB", VecFP,
+                      []>;
+def VRFIN  : VXForm_2<522, (ops VRRC:$vD, VRRC:$vB),
+                      "vrfin $vD, $vB", VecFP,
+                      []>;
+def VRFIP  : VXForm_2<650, (ops VRRC:$vD, VRRC:$vB),
+                      "vrfip $vD, $vB", VecFP,
+                      []>;
+def VRFIZ  : VXForm_2<586, (ops VRRC:$vD, VRRC:$vB),
+                      "vrfiz $vD, $vB", VecFP,
+                      []>;
+def VRSQRTEFP : VXForm_2<330, (ops VRRC:$vD, VRRC:$vB),
+                         "vrsqrtefp $vD, $vB", VecFP,
+                         []>;
+def VSUBFP : VXForm_1<74, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
+                      "vsubfp $vD, $vA, $vB", VecFP,
+                      [(set VRRC:$vD, (fsub VRRC:$vA, VRRC:$vB))]>;
 
 //===----------------------------------------------------------------------===//
 // PowerPC Instruction Patterns





From natebegeman at mac.com  Tue Nov 29 02:17:31 2005
From: natebegeman at mac.com (Nate Begeman)
Date: Tue, 29 Nov 2005 02:17:31 -0600
Subject: [llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCISelLowering.cpp 
Message-ID: <200511290817.CAA30194@zion.cs.uiuc.edu>



Changes in directory llvm/lib/Target/PowerPC:

PPCISelLowering.cpp updated: 1.46 -> 1.47
---
Log message:

Hook up one type, v4f32, to the VR RegisterClass for now.


---
Diffs of the changes:  (+6 -0)

 PPCISelLowering.cpp |    6 ++++++
 1 files changed, 6 insertions(+)


Index: llvm/lib/Target/PowerPC/PPCISelLowering.cpp
diff -u llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.46 llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.47
--- llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.46	Tue Nov 29 00:16:21 2005
+++ llvm/lib/Target/PowerPC/PPCISelLowering.cpp	Tue Nov 29 02:17:20 2005
@@ -121,6 +121,12 @@
     setOperationAction(ISD::SRA, MVT::i64, Custom);
   }
   
+  if (TM.getSubtarget<PPCSubtarget>().hasAltivec()) {
+    // FIXME: AltiVec supports a wide variety of packed types.  For now, we're
+    // bringing up support with just v4f32.
+    addRegisterClass(MVT::v4f32, PPC::VRRCRegisterClass);
+  }
+  
   setSetCCResultContents(ZeroOrOneSetCCResult);
   
   computeRegisterProperties();





From alenhar2 at cs.uiuc.edu  Tue Nov 29 09:51:32 2005
From: alenhar2 at cs.uiuc.edu (Andrew Lenharth)
Date: Tue, 29 Nov 2005 09:51:32 -0600
Subject: [llvm-commits] vector types
In-Reply-To: <200511290616.jAT6GrIp006021@dcs-maillist.cs.uiuc.edu>
References: <200511290616.jAT6GrIp006021@dcs-maillist.cs.uiuc.edu>
Message-ID: <1133279492.32542.6.camel@apoc.cs.uiuc.edu>

> Add the majority of the vector machien value types we expect to support,
> and make a few changes to the legalization machinery to support more than
> 16 types.

Just in case anyone cares, the relevant vector types for alpha are:

v8i8, v4i16, and maybe v2i32 (only one unpack operation produces this
and one pack operations consumes it).  Of course all the operations that
exist are (s|u)(min|max), packing, unpacking, and comparison.  Not that
I am too worried about support. 

Andrew

> 
> 
> ---
> Diffs of the changes:  (+21 -3)
> 
>  ValueTypes.h |   24 +++++++++++++++++++++---
>  1 files changed, 21 insertions(+), 3 deletions(-)
> 
> 
> Index: llvm/include/llvm/CodeGen/ValueTypes.h
> diff -u llvm/include/llvm/CodeGen/ValueTypes.h:1.13 llvm/include/llvm/CodeGen/ValueTypes.h:1.14
> --- llvm/include/llvm/CodeGen/ValueTypes.h:1.13	Thu Nov 17 15:44:42 2005
> +++ llvm/include/llvm/CodeGen/ValueTypes.h	Mon Nov 28 23:45:28 2005
> @@ -48,14 +48,26 @@
>                              // be refined into a target vector type, or
>                              // scalarized.
>  
> +                            // These are 128 bit vectors of varying packed types
> +    v16i8          =  14,   // 16 x i8
> +    v8i16          =  15,   //  8 x i16
> +    v4i32          =  16,   //  4 x i32
> +    v2i64          =  17,   //  2 x i64
> +
> +    v4f32          =  18,   //  4 x f32
> +    v2f64          =  19,   //  2 x f64
> +
>      LAST_VALUETYPE,         // This always remains at the end of the list.
>    };
>  
>    static inline bool isInteger(ValueType VT) {
> -    return VT >= i1 && VT <= i128;
> +    return (VT >= i1 && VT <= i128) || (VT >= v16i8 && VT <= v2i64);
>    }
>    static inline bool isFloatingPoint(ValueType VT) {
> -    return VT >= f32 && VT <= f128;
> +    return (VT >= f32 && VT <= f128) || (VT >= v4f32 && VT <= v2f64);
> +  }
> +  static inline bool isVector(ValueType VT) {
> +    return (VT >= v16i8 && VT <= v2f64);
>    }
>  
>    static inline unsigned getSizeInBits(ValueType VT) {
> @@ -70,7 +82,13 @@
>      case MVT::i64 : return 64;
>      case MVT::f80 : return 80;
>      case MVT::f128:
> -    case MVT::i128: return 128;
> +    case MVT::i128: 
> +    case MVT::v16i8:
> +    case MVT::v8i16:
> +    case MVT::v4i32:
> +    case MVT::v2i64:
> +    case MVT::v4f32:
> +    case MVT::v2f64: return 128;
>      }
>    }




From sabre at nondot.org  Tue Nov 29 10:36:19 2005
From: sabre at nondot.org (Chris Lattner)
Date: Tue, 29 Nov 2005 10:36:19 -0600 (CST)
Subject: [llvm-commits] vector types
In-Reply-To: <1133279492.32542.6.camel@apoc.cs.uiuc.edu>
References: <200511290616.jAT6GrIp006021@dcs-maillist.cs.uiuc.edu>
	<1133279492.32542.6.camel@apoc.cs.uiuc.edu>
Message-ID: <Pine.LNX.4.61.0511291035210.846@nondot.org>

On Tue, 29 Nov 2005, Andrew Lenharth wrote:
>> Add the majority of the vector machien value types we expect to support,
>> and make a few changes to the legalization machinery to support more than
>> 16 types.
>
> Just in case anyone cares, the relevant vector types for alpha are:
>
> v8i8, v4i16, and maybe v2i32 (only one unpack operation produces this
> and one pack operations consumes it).  Of course all the operations that
> exist are (s|u)(min|max), packing, unpacking, and comparison.  Not that
> I am too worried about support.

Ok, sounds good.  We figured that the list could be expanded on demand. :) 
MMX also has several other supported types that aren't on the list, so we 
would add those if we ever decided to add support.

-Chris

>> ---
>> Diffs of the changes:  (+21 -3)
>>
>>  ValueTypes.h |   24 +++++++++++++++++++++---
>>  1 files changed, 21 insertions(+), 3 deletions(-)
>>
>>
>> Index: llvm/include/llvm/CodeGen/ValueTypes.h
>> diff -u llvm/include/llvm/CodeGen/ValueTypes.h:1.13 llvm/include/llvm/CodeGen/ValueTypes.h:1.14
>> --- llvm/include/llvm/CodeGen/ValueTypes.h:1.13	Thu Nov 17 15:44:42 2005
>> +++ llvm/include/llvm/CodeGen/ValueTypes.h	Mon Nov 28 23:45:28 2005
>> @@ -48,14 +48,26 @@
>>                              // be refined into a target vector type, or
>>                              // scalarized.
>>
>> +                            // These are 128 bit vectors of varying packed types
>> +    v16i8          =  14,   // 16 x i8
>> +    v8i16          =  15,   //  8 x i16
>> +    v4i32          =  16,   //  4 x i32
>> +    v2i64          =  17,   //  2 x i64
>> +
>> +    v4f32          =  18,   //  4 x f32
>> +    v2f64          =  19,   //  2 x f64
>> +
>>      LAST_VALUETYPE,         // This always remains at the end of the list.
>>    };
>>
>>    static inline bool isInteger(ValueType VT) {
>> -    return VT >= i1 && VT <= i128;
>> +    return (VT >= i1 && VT <= i128) || (VT >= v16i8 && VT <= v2i64);
>>    }
>>    static inline bool isFloatingPoint(ValueType VT) {
>> -    return VT >= f32 && VT <= f128;
>> +    return (VT >= f32 && VT <= f128) || (VT >= v4f32 && VT <= v2f64);
>> +  }
>> +  static inline bool isVector(ValueType VT) {
>> +    return (VT >= v16i8 && VT <= v2f64);
>>    }
>>
>>    static inline unsigned getSizeInBits(ValueType VT) {
>> @@ -70,7 +82,13 @@
>>      case MVT::i64 : return 64;
>>      case MVT::f80 : return 80;
>>      case MVT::f128:
>> -    case MVT::i128: return 128;
>> +    case MVT::i128:
>> +    case MVT::v16i8:
>> +    case MVT::v8i16:
>> +    case MVT::v4i32:
>> +    case MVT::v2i64:
>> +    case MVT::v4f32:
>> +    case MVT::v2f64: return 128;
>>      }
>>    }
>
>
> _______________________________________________
> llvm-commits mailing list
> llvm-commits at cs.uiuc.edu
> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
>

-Chris

-- 
http://nondot.org/sabre/
http://llvm.org/



From lattner at cs.uiuc.edu  Tue Nov 29 12:19:41 2005
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Tue, 29 Nov 2005 12:19:41 -0600
Subject: [llvm-commits] 
	CVS: llvm-test/SingleSource/UnitTests/2005-11-29-LongSwitch.c
Message-ID: <200511291819.MAA08793@zion.cs.uiuc.edu>



Changes in directory llvm-test/SingleSource/UnitTests:

2005-11-29-LongSwitch.c added (r1.1)
---
Log message:

new testcase corresponding to PR671: http://llvm.cs.uiuc.edu/PR671 


---
Diffs of the changes:  (+19 -0)

 2005-11-29-LongSwitch.c |   19 +++++++++++++++++++
 1 files changed, 19 insertions(+)


Index: llvm-test/SingleSource/UnitTests/2005-11-29-LongSwitch.c
diff -c /dev/null llvm-test/SingleSource/UnitTests/2005-11-29-LongSwitch.c:1.1
*** /dev/null	Tue Nov 29 12:19:31 2005
--- llvm-test/SingleSource/UnitTests/2005-11-29-LongSwitch.c	Tue Nov 29 12:19:21 2005
***************
*** 0 ****
--- 1,19 ----
+ // PR671
+ 
+ #include <stdio.h>
+ 
+ int foo(long long v) {
+     switch (v) {
+     case 0:
+         return 1;
+     case -1:
+         return 2;
+     }
+     return 0;
+ }
+ 
+ int main() {
+     int r = foo(4294967295LL);
+     printf("foo = %d\n", r);
+     return r;
+ }





From lattner at cs.uiuc.edu  Tue Nov 29 12:25:16 2005
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Tue, 29 Nov 2005 12:25:16 -0600
Subject: [llvm-commits] CVS: llvm-gcc/gcc/llvm-expand.c
	llvm-representation.c llvm-representation.h 
Message-ID: <200511291825.MAA08895@zion.cs.uiuc.edu>



Changes in directory llvm-gcc/gcc:

llvm-expand.c updated: 1.117 -> 1.118
llvm-representation.c updated: 1.20 -> 1.21
llvm-representation.h updated: 1.19 -> 1.20
---
Log message:

Allow switch statements on long-long values to be correctly handled.  This
fixes PR671: http://llvm.cs.uiuc.edu/PR671  and llvm-test/SingleSource/UnitTests/2005-11-29-LongSwitch.c


---
Diffs of the changes:  (+25 -11)

 llvm-expand.c         |   23 ++++++++++++++---------
 llvm-representation.c |   11 ++++++++++-
 llvm-representation.h |    2 +-
 3 files changed, 25 insertions(+), 11 deletions(-)


Index: llvm-gcc/gcc/llvm-expand.c
diff -u llvm-gcc/gcc/llvm-expand.c:1.117 llvm-gcc/gcc/llvm-expand.c:1.118
--- llvm-gcc/gcc/llvm-expand.c:1.117	Wed Sep 28 02:16:59 2005
+++ llvm-gcc/gcc/llvm-expand.c	Tue Nov 29 12:25:04 2005
@@ -2022,8 +2022,8 @@
     add_scope_stack(Fn, &Fn->ExpandInfo->InnermostCaseScope, CASE_NESTING);
   llvm_instruction *SI = llvm_instruction_new(VoidTy, "", O_Switch, 2);
   llvm_value *Val = llvm_expand_expr(Fn, expr, 0);
-
-  SI->Operands[0] = cast_if_type_not_equal(Fn, Val, UIntTy);
+  assert(llvm_type_is_integral(Val->Ty) && "Not an integer switch expr!");
+  SI->Operands[0] = Val;
 
   append_inst(Fn, SI);
   thiscase->x.switchblock.SwitchInst = SI;
@@ -2083,6 +2083,15 @@
   pop_and_free_scope_stack(Fn, &Fn->ExpandInfo->InnermostCaseScope);
 }
 
+static unsigned long long getIntCstAsLongLong(tree V) {
+  unsigned HOST_WIDE_INT HI = (unsigned HOST_WIDE_INT)TREE_INT_CST_HIGH(V);
+  unsigned HOST_WIDE_INT LO = (unsigned HOST_WIDE_INT)TREE_INT_CST_LOW(V);
+  if (sizeof(LO) == 8) return LO;
+  
+  assert(sizeof(LO) == 4 && "64 and 32 bit HOST_WIDE_INT's supported!");
+  return ((long long)(unsigned)HI << 32) | (long long)(unsigned)LO;
+}
+
 /* Add a case label to the current switch statement.  This could be a range of
    case values to insert.  Handle them as appropriate.
  */
@@ -2091,7 +2100,7 @@
   llvm_nesting *thiscase = Fn->ExpandInfo->InnermostCaseScope;
   llvm_instruction *SwitchInst;
   llvm_basicblock *Block = getLabelDeclBlock(label);
-  int Low, High;
+  long long Low, High;
 
   assert(thiscase && "Case label not in case statement!");
   SwitchInst = thiscase->x.switchblock.SwitchInst;
@@ -2111,12 +2120,8 @@
     }
   }
 
-  if ((TREE_INT_CST_HIGH(low) != 0 || TREE_INT_CST_HIGH(high) != 0) &&
-      (TREE_INT_CST_HIGH(low) != -1 || TREE_INT_CST_HIGH(high) != -1))
-    LLVM_TODO_TREE(label); /* Cannot handle case values this large! */
-
-  Low = (int)TREE_INT_CST_LOW(low);
-  High = (int)TREE_INT_CST_LOW(high);
+  Low = getIntCstAsLongLong(low);
+  High = getIntCstAsLongLong(high);
 
   for (; Low != High+1; ++Low) {
     llvm_switch_case *NewCase = xmalloc(sizeof(llvm_switch_case));


Index: llvm-gcc/gcc/llvm-representation.c
diff -u llvm-gcc/gcc/llvm-representation.c:1.20 llvm-gcc/gcc/llvm-representation.c:1.21
--- llvm-gcc/gcc/llvm-representation.c:1.20	Sat Sep 24 03:33:56 2005
+++ llvm-gcc/gcc/llvm-representation.c	Tue Nov 29 12:25:04 2005
@@ -708,7 +708,16 @@
     fprintf(F, " [");
 
     for (; C; C = C->Next) {
-      fprintf(F, "\n\t\tuint %u, ", C->Value);
+      switch (Operand->Ty->ID) {
+      case UByteTyID:  fprintf(F, "\n\t\tubyte %u, ", (unsigned char)C->Value); break;
+      case SByteTyID:  fprintf(F, "\n\t\tsbyte %d, ", (signed char)C->Value); break;
+      case UShortTyID: fprintf(F, "\n\t\tushort %u, ", (unsigned short)C->Value); break;
+      case ShortTyID:  fprintf(F, "\n\t\tshort %d, ", (signed short)C->Value); break;
+      case UIntTyID:   fprintf(F, "\n\t\tuint %u, ", (unsigned)C->Value); break;
+      case IntTyID:    fprintf(F, "\n\t\tint %d, ", (signed)C->Value); break;
+      case ULongTyID:  fprintf(F, "\n\t\tulong %llu, ", C->Value); break;
+      case LongTyID:   fprintf(F, "\n\t\tlong %lld, ", C->Value); break;
+      }
       llvm_value_print_operand(D2V(C->Dest), 1, F);
     }
     fprintf(F, "\n\t]");


Index: llvm-gcc/gcc/llvm-representation.h
diff -u llvm-gcc/gcc/llvm-representation.h:1.19 llvm-gcc/gcc/llvm-representation.h:1.20
--- llvm-gcc/gcc/llvm-representation.h:1.19	Thu Jul 28 13:50:28 2005
+++ llvm-gcc/gcc/llvm-representation.h	Tue Nov 29 12:25:04 2005
@@ -154,7 +154,7 @@
 
 typedef struct llvm_switch_case {
   struct llvm_switch_case *Next;
-  unsigned Value;
+  unsigned long long Value;
   struct llvm_basicblock *Dest;
 } llvm_switch_case;
 





From evan.cheng at apple.com  Tue Nov 29 12:45:10 2005
From: evan.cheng at apple.com (Evan Cheng)
Date: Tue, 29 Nov 2005 12:45:10 -0600
Subject: [llvm-commits] CVS: llvm/utils/TableGen/DAGISelEmitter.cpp 
Message-ID: <200511291845.MAA09568@zion.cs.uiuc.edu>



Changes in directory llvm/utils/TableGen:

DAGISelEmitter.cpp updated: 1.76 -> 1.77
---
Log message:

Better error message when unrecognized opcode is seen.


---
Diffs of the changes:  (+6 -1)

 DAGISelEmitter.cpp |    7 ++++++-
 1 files changed, 6 insertions(+), 1 deletion(-)


Index: llvm/utils/TableGen/DAGISelEmitter.cpp
diff -u llvm/utils/TableGen/DAGISelEmitter.cpp:1.76 llvm/utils/TableGen/DAGISelEmitter.cpp:1.77
--- llvm/utils/TableGen/DAGISelEmitter.cpp:1.76	Thu Nov 17 11:43:52 2005
+++ llvm/utils/TableGen/DAGISelEmitter.cpp	Tue Nov 29 12:44:58 2005
@@ -1952,7 +1952,12 @@
              dynamic_cast<IntInit*>(PatternsToMatch[i].first->getLeafValue())) {
         PatternsByOpcode[getSDNodeNamed("imm")].push_back(&PatternsToMatch[i]);
       } else {
-        assert(0 && "Unknown leaf value");
+        std::cerr << "Unrecognized opcode '";
+        PatternsToMatch[i].first->dump();
+        std::cerr << "' on tree pattern '";
+        std::cerr << PatternsToMatch[i].second->getOperator()->getName();
+        std::cerr << "'!\n";
+        exit(1);
       }
     }
   





From evan.cheng at apple.com  Tue Nov 29 13:39:05 2005
From: evan.cheng at apple.com (Evan Cheng)
Date: Tue, 29 Nov 2005 13:39:05 -0600
Subject: [llvm-commits] CVS: llvm/lib/Target/X86/X86InstrInfo.td 
Message-ID: <200511291939.NAA10279@zion.cs.uiuc.edu>



Changes in directory llvm/lib/Target/X86:

X86InstrInfo.td updated: 1.141 -> 1.142
---
Log message:

Add more X86 ISel patterns.


---
Diffs of the changes:  (+464 -408)

 X86InstrInfo.td |  872 +++++++++++++++++++++++++++++---------------------------
 1 files changed, 464 insertions(+), 408 deletions(-)


Index: llvm/lib/Target/X86/X86InstrInfo.td
diff -u llvm/lib/Target/X86/X86InstrInfo.td:1.141 llvm/lib/Target/X86/X86InstrInfo.td:1.142
--- llvm/lib/Target/X86/X86InstrInfo.td:1.141	Sun Nov 20 16:13:18 2005
+++ llvm/lib/Target/X86/X86InstrInfo.td	Tue Nov 29 13:38:52 2005
@@ -145,8 +145,10 @@
 //===----------------------------------------------------------------------===//
 // Instruction templates...
 
-class I<bits<8> o, Format f, dag ops, string asm>
-  : X86Inst<o, f, NoImm, ops, asm>;
+class I<bits<8> o, Format f, dag ops, string asm, list<dag> pattern>
+  : X86Inst<o, f, NoImm, ops, asm> {
+  let Pattern = pattern;
+}
 class Ii8 <bits<8> o, Format f, dag ops, string asm, list<dag> pattern>
   : X86Inst<o, f, Imm8 , ops, asm> {
   let Pattern = pattern;
@@ -164,17 +166,17 @@
 // Instruction list...
 //
 
-def PHI : I<0, Pseudo, (ops variable_ops), "PHINODE">;        // PHI node.
-def NOOP : I<0x90, RawFrm, (ops), "nop">; // nop
+def PHI : I<0, Pseudo, (ops variable_ops), "PHINODE", []>;        // PHI node.
+def NOOP : I<0x90, RawFrm, (ops), "nop", []>; // nop
 
-def ADJCALLSTACKDOWN : I<0, Pseudo, (ops i32imm:$amt), "#ADJCALLSTACKDOWN">;
+def ADJCALLSTACKDOWN : I<0, Pseudo, (ops i32imm:$amt), "#ADJCALLSTACKDOWN", []>;
 def ADJCALLSTACKUP   : I<0, Pseudo, (ops i32imm:$amt1, i32imm:$amt2),
-                         "#ADJCALLSTACKUP">;
-def IMPLICIT_USE     : I<0, Pseudo, (ops variable_ops), "#IMPLICIT_USE">;
-def IMPLICIT_DEF     : I<0, Pseudo, (ops variable_ops), "#IMPLICIT_DEF">;
+                         "#ADJCALLSTACKUP", []>;
+def IMPLICIT_USE     : I<0, Pseudo, (ops variable_ops), "#IMPLICIT_USE", []>;
+def IMPLICIT_DEF     : I<0, Pseudo, (ops variable_ops), "#IMPLICIT_DEF", []>;
 let isTerminator = 1 in
   let Defs = [FP0, FP1, FP2, FP3, FP4, FP5, FP6] in
-    def FP_REG_KILL  : I<0, Pseudo, (ops), "#FP_REG_KILL">;
+    def FP_REG_KILL  : I<0, Pseudo, (ops), "#FP_REG_KILL", []>;
 
 //===----------------------------------------------------------------------===//
 //  Control Flow Instructions...
@@ -182,13 +184,14 @@
 
 // Return instructions.
 let isTerminator = 1, isReturn = 1, isBarrier = 1 in
-  def RET : I<0xC3, RawFrm, (ops), "ret">;
+  def RET : I<0xC3, RawFrm, (ops), "ret", []>;
 let isTerminator = 1, isReturn = 1, isBarrier = 1 in
   def RETI : Ii16<0xC2, RawFrm, (ops i16imm:$amt), "ret $amt", []>;
 
 // All branches are RawFrm, Void, Branch, and Terminators
 let isBranch = 1, isTerminator = 1 in
-  class IBr<bits<8> opcode, dag ops, string asm> : I<opcode, RawFrm, ops, asm>;
+  class IBr<bits<8> opcode, dag ops, string asm> :
+        I<opcode, RawFrm, ops, asm, []>;
 
 let isBarrier = 1 in
   def JMP : IBr<0xE9, (ops i32imm:$dst), "jmp $dst">;
@@ -215,18 +218,19 @@
   // All calls clobber the non-callee saved registers...
   let Defs = [EAX, ECX, EDX, FP0, FP1, FP2, FP3, FP4, FP5, FP6, ST0,
               XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7] in {
-    def CALLpcrel32 : I<0xE8, RawFrm, (ops calltarget:$dst), "call $dst">;
-    def CALL32r     : I<0xFF, MRM2r, (ops R32:$dst), "call {*}$dst">;
-    def CALL32m     : I<0xFF, MRM2m, (ops i32mem:$dst), "call {*}$dst">;
+    def CALLpcrel32 : I<0xE8, RawFrm, (ops calltarget:$dst), "call $dst", []>;
+    def CALL32r     : I<0xFF, MRM2r, (ops R32:$dst), "call {*}$dst", []>;
+    def CALL32m     : I<0xFF, MRM2m, (ops i32mem:$dst), "call {*}$dst", []>;
   }
 
 // Tail call stuff.
 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in
   def TAILJMPd : IBr<0xE9, (ops calltarget:$dst), "jmp $dst  # TAIL CALL">;
 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in
-  def TAILJMPr : I<0xFF, MRM4r, (ops R32:$dst), "jmp {*}$dst  # TAIL CALL">;
+  def TAILJMPr : I<0xFF, MRM4r, (ops R32:$dst), "jmp {*}$dst  # TAIL CALL", []>;
 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in
-  def TAILJMPm : I<0xFF, MRM4m, (ops i32mem:$dst), "jmp {*}$dst  # TAIL CALL">;
+  def TAILJMPm : I<0xFF, MRM4m, (ops i32mem:$dst),
+                   "jmp {*}$dst  # TAIL CALL", []>;
 
 // ADJSTACKPTRri - This is a standard ADD32ri instruction, identical in every
 // way, except that it is marked as being a terminator.  This causes the epilog
@@ -241,63 +245,63 @@
 //  Miscellaneous Instructions...
 //
 def LEAVE    : I<0xC9, RawFrm,
-                 (ops), "leave">, Imp<[EBP,ESP],[EBP,ESP]>;
+                 (ops), "leave", []>, Imp<[EBP,ESP],[EBP,ESP]>;
 def POP32r   : I<0x58, AddRegFrm,
-                 (ops R32:$reg), "pop{l} $reg">, Imp<[ESP],[ESP]>;
+                 (ops R32:$reg), "pop{l} $reg", []>, Imp<[ESP],[ESP]>;
 
 let isTwoAddress = 1 in                               // R32 = bswap R32
   def BSWAP32r : I<0xC8, AddRegFrm,
-                   (ops R32:$dst, R32:$src), "bswap{l} $dst">, TB;
+                   (ops R32:$dst, R32:$src), "bswap{l} $dst", []>, TB;
 
 def XCHG8rr  : I<0x86, MRMDestReg,                    // xchg R8, R8
                  (ops R8:$src1, R8:$src2),
-                 "xchg{b} {$src2|$src1}, {$src1|$src2}">;
+                 "xchg{b} {$src2|$src1}, {$src1|$src2}", []>;
 def XCHG16rr : I<0x87, MRMDestReg,                    // xchg R16, R16
                  (ops R16:$src1, R16:$src2),
-                 "xchg{w} {$src2|$src1}, {$src1|$src2}">, OpSize;
+                 "xchg{w} {$src2|$src1}, {$src1|$src2}", []>, OpSize;
 def XCHG32rr : I<0x87, MRMDestReg,                    // xchg R32, R32
                  (ops R32:$src1, R32:$src2),
-                 "xchg{l} {$src2|$src1}, {$src1|$src2}">;
+                 "xchg{l} {$src2|$src1}, {$src1|$src2}", []>;
 
 def XCHG8mr  : I<0x86, MRMDestMem,
                  (ops i8mem:$src1, R8:$src2),
-                 "xchg{b} {$src2|$src1}, {$src1|$src2}">;
+                 "xchg{b} {$src2|$src1}, {$src1|$src2}", []>;
 def XCHG16mr : I<0x87, MRMDestMem,
                  (ops i16mem:$src1, R16:$src2),
-                 "xchg{w} {$src2|$src1}, {$src1|$src2}">, OpSize;
+                 "xchg{w} {$src2|$src1}, {$src1|$src2}", []>, OpSize;
 def XCHG32mr : I<0x87, MRMDestMem,
                  (ops i32mem:$src1, R32:$src2),
-                 "xchg{l} {$src2|$src1}, {$src1|$src2}">;
+                 "xchg{l} {$src2|$src1}, {$src1|$src2}", []>;
 def XCHG8rm  : I<0x86, MRMSrcMem,
                  (ops R8:$src1, i8mem:$src2),
-                 "xchg{b} {$src2|$src1}, {$src1|$src2}">;
+                 "xchg{b} {$src2|$src1}, {$src1|$src2}", []>;
 def XCHG16rm : I<0x87, MRMSrcMem,
                  (ops R16:$src1, i16mem:$src2),
-                 "xchg{w} {$src2|$src1}, {$src1|$src2}">, OpSize;
+                 "xchg{w} {$src2|$src1}, {$src1|$src2}", []>, OpSize;
 def XCHG32rm : I<0x87, MRMSrcMem,
                  (ops R32:$src1, i32mem:$src2),
-                 "xchg{l} {$src2|$src1}, {$src1|$src2}">;
+                 "xchg{l} {$src2|$src1}, {$src1|$src2}", []>;
 
 def LEA16r   : I<0x8D, MRMSrcMem,
                  (ops R16:$dst, i32mem:$src),
-                 "lea{w} {$src|$dst}, {$dst|$src}">, OpSize;
+                 "lea{w} {$src|$dst}, {$dst|$src}", []>, OpSize;
 def LEA32r   : I<0x8D, MRMSrcMem,
                  (ops R32:$dst, i32mem:$src),
-                 "lea{l} {$src|$dst}, {$dst|$src}">;
+                 "lea{l} {$src|$dst}, {$dst|$src}", []>;
 
 
-def REP_MOVSB : I<0xA4, RawFrm, (ops), "{rep;movsb|rep movsb}">,
+def REP_MOVSB : I<0xA4, RawFrm, (ops), "{rep;movsb|rep movsb}", []>,
                 Imp<[ECX,EDI,ESI], [ECX,EDI,ESI]>, REP;
-def REP_MOVSW : I<0xA5, RawFrm, (ops), "{rep;movsw|rep movsw}">,
+def REP_MOVSW : I<0xA5, RawFrm, (ops), "{rep;movsw|rep movsw}", []>,
                 Imp<[ECX,EDI,ESI], [ECX,EDI,ESI]>, REP, OpSize;
-def REP_MOVSD : I<0xA5, RawFrm, (ops), "{rep;movsd|rep movsd}">,
+def REP_MOVSD : I<0xA5, RawFrm, (ops), "{rep;movsd|rep movsd}", []>,
                 Imp<[ECX,EDI,ESI], [ECX,EDI,ESI]>, REP;
 
-def REP_STOSB : I<0xAA, RawFrm, (ops), "{rep;stosb|rep stosb}">,
+def REP_STOSB : I<0xAA, RawFrm, (ops), "{rep;stosb|rep stosb}", []>,
                 Imp<[AL,ECX,EDI], [ECX,EDI]>, REP;
-def REP_STOSW : I<0xAB, RawFrm, (ops), "{rep;stosw|rep stosw}">,
+def REP_STOSW : I<0xAB, RawFrm, (ops), "{rep;stosw|rep stosw}", []>,
                 Imp<[AX,ECX,EDI], [ECX,EDI]>, REP, OpSize;
-def REP_STOSD : I<0xAB, RawFrm, (ops), "{rep;stosl|rep stosd}">,
+def REP_STOSD : I<0xAB, RawFrm, (ops), "{rep;stosl|rep stosd}", []>,
                 Imp<[EAX,ECX,EDI], [ECX,EDI]>, REP;
 
 
@@ -305,11 +309,11 @@
 //  Input/Output Instructions...
 //
 def IN8rr  : I<0xEC, RawFrm, (ops),
-               "in{b} {%dx, %al|%AL, %DX}">,  Imp<[DX], [AL]>;
+               "in{b} {%dx, %al|%AL, %DX}", []>,  Imp<[DX], [AL]>;
 def IN16rr : I<0xED, RawFrm, (ops),
-               "in{w} {%dx, %ax|%AX, %DX}">,  Imp<[DX], [AX]>, OpSize;
+               "in{w} {%dx, %ax|%AX, %DX}", []>,  Imp<[DX], [AX]>, OpSize;
 def IN32rr : I<0xED, RawFrm, (ops),
-               "in{l} {%dx, %eax|%EAX, %DX}">, Imp<[DX],[EAX]>;
+               "in{l} {%dx, %eax|%EAX, %DX}", []>, Imp<[DX],[EAX]>;
 
 def IN8ri  : Ii16<0xE4, RawFrm, (ops i16imm:$port),
                   "in{b} {$port, %al|%AL, $port}", []>,  Imp<[], [AL]>;
@@ -319,11 +323,11 @@
                   "in{l} {$port, %eax|%EAX, $port}", []>, Imp<[],[EAX]>;
 
 def OUT8rr  : I<0xEE, RawFrm, (ops),
-                "out{b} {%al, %dx|%DX, %AL}">,  Imp<[DX,  AL], []>;
+                "out{b} {%al, %dx|%DX, %AL}", []>,  Imp<[DX,  AL], []>;
 def OUT16rr : I<0xEF, RawFrm, (ops),
-                "out{w} {%ax, %dx|%DX, %AX}">,  Imp<[DX,  AX], []>, OpSize;
+                "out{w} {%ax, %dx|%DX, %AX}", []>,  Imp<[DX,  AX], []>, OpSize;
 def OUT32rr : I<0xEF, RawFrm, (ops),
-                "out{l} {%eax, %dx|%DX, %EAX}">, Imp<[DX, EAX], []>;
+                "out{l} {%eax, %dx|%DX, %EAX}", []>, Imp<[DX, EAX], []>;
 
 def OUT8ir  : Ii16<0xE6, RawFrm, (ops i16imm:$port),
                    "out{b} {%al, $port|$port, %AL}", []>, Imp<[AL], []>;
@@ -336,11 +340,11 @@
 //  Move Instructions...
 //
 def MOV8rr  : I<0x88, MRMDestReg, (ops R8 :$dst, R8 :$src),
-                "mov{b} {$src, $dst|$dst, $src}">;
+                "mov{b} {$src, $dst|$dst, $src}", []>;
 def MOV16rr : I<0x89, MRMDestReg, (ops R16:$dst, R16:$src),
-                "mov{w} {$src, $dst|$dst, $src}">, OpSize;
+                "mov{w} {$src, $dst|$dst, $src}", []>, OpSize;
 def MOV32rr : I<0x89, MRMDestReg, (ops R32:$dst, R32:$src),
-                "mov{l} {$src, $dst|$dst, $src}">;
+                "mov{l} {$src, $dst|$dst, $src}", []>;
 def MOV8ri  : Ii8 <0xB0, AddRegFrm, (ops R8 :$dst, i8imm :$src),
                    "mov{b} {$src, $dst|$dst, $src}",
                    [(set R8:$dst, imm:$src)]>;
@@ -358,85 +362,88 @@
                    "mov{l} {$src, $dst|$dst, $src}", []>;
 
 def MOV8rm  : I<0x8A, MRMSrcMem, (ops R8 :$dst, i8mem :$src),
-                "mov{b} {$src, $dst|$dst, $src}">;
+                "mov{b} {$src, $dst|$dst, $src}", []>;
 def MOV16rm : I<0x8B, MRMSrcMem, (ops R16:$dst, i16mem:$src),
-                "mov{w} {$src, $dst|$dst, $src}">, OpSize;
+                "mov{w} {$src, $dst|$dst, $src}", []>, OpSize;
 def MOV32rm : I<0x8B, MRMSrcMem, (ops R32:$dst, i32mem:$src),
-                "mov{l} {$src, $dst|$dst, $src}">;
+                "mov{l} {$src, $dst|$dst, $src}", []>;
 
 def MOV8mr  : I<0x88, MRMDestMem, (ops i8mem :$dst, R8 :$src),
-                "mov{b} {$src, $dst|$dst, $src}">;
+                "mov{b} {$src, $dst|$dst, $src}", []>;
 def MOV16mr : I<0x89, MRMDestMem, (ops i16mem:$dst, R16:$src),
-                "mov{w} {$src, $dst|$dst, $src}">, OpSize;
+                "mov{w} {$src, $dst|$dst, $src}", []>, OpSize;
 def MOV32mr : I<0x89, MRMDestMem, (ops i32mem:$dst, R32:$src),
-                "mov{l} {$src, $dst|$dst, $src}">;
+                "mov{l} {$src, $dst|$dst, $src}", []>;
                 
 //===----------------------------------------------------------------------===//
 //  Fixed-Register Multiplication and Division Instructions...
 //
 
 // Extra precision multiplication
-def MUL8r  : I<0xF6, MRM4r, (ops R8:$src), "mul{b} $src">,
+def MUL8r  : I<0xF6, MRM4r, (ops R8:$src), "mul{b} $src", []>,
              Imp<[AL],[AX]>;               // AL,AH = AL*R8
-def MUL16r : I<0xF7, MRM4r, (ops R16:$src), "mul{w} $src">,
+def MUL16r : I<0xF7, MRM4r, (ops R16:$src), "mul{w} $src", []>,
              Imp<[AX],[AX,DX]>, OpSize;    // AX,DX = AX*R16
-def MUL32r : I<0xF7, MRM4r, (ops R32:$src), "mul{l} $src">,
+def MUL32r : I<0xF7, MRM4r, (ops R32:$src), "mul{l} $src", []>,
              Imp<[EAX],[EAX,EDX]>;         // EAX,EDX = EAX*R32
 def MUL8m  : I<0xF6, MRM4m, (ops i8mem :$src),
-               "mul{b} $src">, Imp<[AL],[AX]>;            // AL,AH = AL*[mem8]
+               "mul{b} $src", []>, Imp<[AL],[AX]>;          // AL,AH = AL*[mem8]
 def MUL16m : I<0xF7, MRM4m, (ops i16mem:$src),
-               "mul{w} $src">, Imp<[AX],[AX,DX]>, OpSize; // AX,DX = AX*[mem16]
+               "mul{w} $src", []>, Imp<[AX],[AX,DX]>,
+               OpSize; // AX,DX = AX*[mem16]
 def MUL32m : I<0xF7, MRM4m, (ops i32mem:$src),
-               "mul{l} $src">, Imp<[EAX],[EAX,EDX]>;   // EAX,EDX = EAX*[mem32]
+               "mul{l} $src", []>, Imp<[EAX],[EAX,EDX]>;// EAX,EDX = EAX*[mem32]
 
-def IMUL8r  : I<0xF6, MRM5r, (ops R8:$src), "imul{b} $src">,
+def IMUL8r  : I<0xF6, MRM5r, (ops R8:$src), "imul{b} $src", []>,
               Imp<[AL],[AX]>;               // AL,AH = AL*R8
-def IMUL16r : I<0xF7, MRM5r, (ops R16:$src), "imul{w} $src">,
+def IMUL16r : I<0xF7, MRM5r, (ops R16:$src), "imul{w} $src", []>,
               Imp<[AX],[AX,DX]>, OpSize;    // AX,DX = AX*R16
-def IMUL32r : I<0xF7, MRM5r, (ops R32:$src), "imul{l} $src">,
+def IMUL32r : I<0xF7, MRM5r, (ops R32:$src), "imul{l} $src", []>,
               Imp<[EAX],[EAX,EDX]>;         // EAX,EDX = EAX*R32
 def IMUL8m  : I<0xF6, MRM5m, (ops i8mem :$src),
-                "imul{b} $src">, Imp<[AL],[AX]>;           // AL,AH = AL*[mem8]
+                "imul{b} $src", []>, Imp<[AL],[AX]>;        // AL,AH = AL*[mem8]
 def IMUL16m : I<0xF7, MRM5m, (ops i16mem:$src),
-                "imul{w} $src">, Imp<[AX],[AX,DX]>, OpSize;// AX,DX = AX*[mem16]
+                "imul{w} $src", []>, Imp<[AX],[AX,DX]>,
+                OpSize; // AX,DX = AX*[mem16]
 def IMUL32m : I<0xF7, MRM5m, (ops i32mem:$src),
-                "imul{l} $src">, Imp<[EAX],[EAX,EDX]>;  // EAX,EDX = EAX*[mem32]
+                "imul{l} $src", []>,
+                Imp<[EAX],[EAX,EDX]>;  // EAX,EDX = EAX*[mem32]
 
 // unsigned division/remainder
 def DIV8r  : I<0xF6, MRM6r, (ops R8:$src),          // AX/r8 = AL,AH
-               "div{b} $src">, Imp<[AX],[AX]>;
+               "div{b} $src", []>, Imp<[AX],[AX]>;
 def DIV16r : I<0xF7, MRM6r, (ops R16:$src),         // DX:AX/r16 = AX,DX
-               "div{w} $src">, Imp<[AX,DX],[AX,DX]>, OpSize;
+               "div{w} $src", []>, Imp<[AX,DX],[AX,DX]>, OpSize;
 def DIV32r : I<0xF7, MRM6r, (ops R32:$src),         // EDX:EAX/r32 = EAX,EDX
-               "div{l} $src">, Imp<[EAX,EDX],[EAX,EDX]>;
+               "div{l} $src", []>, Imp<[EAX,EDX],[EAX,EDX]>;
 def DIV8m  : I<0xF6, MRM6m, (ops i8mem:$src),       // AX/[mem8] = AL,AH
-               "div{b} $src">, Imp<[AX],[AX]>;
+               "div{b} $src", []>, Imp<[AX],[AX]>;
 def DIV16m : I<0xF7, MRM6m, (ops i16mem:$src),      // DX:AX/[mem16] = AX,DX
-               "div{w} $src">, Imp<[AX,DX],[AX,DX]>, OpSize;
+               "div{w} $src", []>, Imp<[AX,DX],[AX,DX]>, OpSize;
 def DIV32m : I<0xF7, MRM6m, (ops i32mem:$src),      // EDX:EAX/[mem32] = EAX,EDX
-               "div{l} $src">, Imp<[EAX,EDX],[EAX,EDX]>;
+               "div{l} $src", []>, Imp<[EAX,EDX],[EAX,EDX]>;
 
 // Signed division/remainder.
 def IDIV8r : I<0xF6, MRM7r, (ops R8:$src),          // AX/r8 = AL,AH
-               "idiv{b} $src">, Imp<[AX],[AX]>;
+               "idiv{b} $src", []>, Imp<[AX],[AX]>;
 def IDIV16r: I<0xF7, MRM7r, (ops R16:$src),         // DX:AX/r16 = AX,DX
-               "idiv{w} $src">, Imp<[AX,DX],[AX,DX]>, OpSize;
+               "idiv{w} $src", []>, Imp<[AX,DX],[AX,DX]>, OpSize;
 def IDIV32r: I<0xF7, MRM7r, (ops R32:$src),         // EDX:EAX/r32 = EAX,EDX
-               "idiv{l} $src">, Imp<[EAX,EDX],[EAX,EDX]>;
+               "idiv{l} $src", []>, Imp<[EAX,EDX],[EAX,EDX]>;
 def IDIV8m : I<0xF6, MRM7m, (ops i8mem:$src),      // AX/[mem8] = AL,AH
-               "idiv{b} $src">, Imp<[AX],[AX]>;
+               "idiv{b} $src", []>, Imp<[AX],[AX]>;
 def IDIV16m: I<0xF7, MRM7m, (ops i16mem:$src),     // DX:AX/[mem16] = AX,DX
-               "idiv{w} $src">, Imp<[AX,DX],[AX,DX]>, OpSize;
+               "idiv{w} $src", []>, Imp<[AX,DX],[AX,DX]>, OpSize;
 def IDIV32m: I<0xF7, MRM7m, (ops i32mem:$src),     // EDX:EAX/[mem32] = EAX,EDX
-               "idiv{l} $src">, Imp<[EAX,EDX],[EAX,EDX]>;
+               "idiv{l} $src", []>, Imp<[EAX,EDX],[EAX,EDX]>;
 
 // Sign-extenders for division.
 def CBW : I<0x98, RawFrm, (ops),
-            "{cbtw|cbw}">, Imp<[AL],[AH]>;   // AX = signext(AL)
+            "{cbtw|cbw}", []>, Imp<[AL],[AH]>;   // AX = signext(AL)
 def CWD : I<0x99, RawFrm, (ops),
-            "{cwtd|cwd}">, Imp<[AX],[DX]>;   // DX:AX = signext(AX)
+            "{cwtd|cwd}", []>, Imp<[AX],[DX]>;   // DX:AX = signext(AX)
 def CDQ : I<0x99, RawFrm, (ops),
-            "{cltd|cdq}">, Imp<[EAX],[EDX]>; // EDX:EAX = signext(EAX)
+            "{cltd|cdq}", []>, Imp<[EAX],[EDX]>; // EDX:EAX = signext(EAX)
           
 
 //===----------------------------------------------------------------------===//
@@ -447,252 +454,265 @@
 // Conditional moves
 def CMOVB16rr : I<0x42, MRMSrcReg,       // if <u, R16 = R16
                   (ops R16:$dst, R16:$src1, R16:$src2),
-                  "cmovb {$src2, $dst|$dst, $src2}">, TB, OpSize;
+                  "cmovb {$src2, $dst|$dst, $src2}", []>, TB, OpSize;
 def CMOVB16rm : I<0x42, MRMSrcMem,       // if <u, R16 = [mem16]
                   (ops R16:$dst, R16:$src1, i16mem:$src2),
-                  "cmovb {$src2, $dst|$dst, $src2}">, TB, OpSize;
+                  "cmovb {$src2, $dst|$dst, $src2}", []>, TB, OpSize;
 def CMOVB32rr : I<0x42, MRMSrcReg,       // if <u, R32 = R32
                   (ops R32:$dst, R32:$src1, R32:$src2),
-                  "cmovb {$src2, $dst|$dst, $src2}">, TB;
+                  "cmovb {$src2, $dst|$dst, $src2}", []>, TB;
 def CMOVB32rm : I<0x42, MRMSrcMem,       // if <u, R32 = [mem32]
                   (ops R32:$dst, R32:$src1, i32mem:$src2),
-                  "cmovb {$src2, $dst|$dst, $src2}">, TB;
+                  "cmovb {$src2, $dst|$dst, $src2}", []>, TB;
 
 def CMOVAE16rr: I<0x43, MRMSrcReg,       // if >=u, R16 = R16
                   (ops R16:$dst, R16:$src1, R16:$src2),
-                  "cmovae {$src2, $dst|$dst, $src2}">, TB, OpSize;
+                  "cmovae {$src2, $dst|$dst, $src2}", []>, TB, OpSize;
 def CMOVAE16rm: I<0x43, MRMSrcMem,       // if >=u, R16 = [mem16]
                   (ops R16:$dst, R16:$src1, i16mem:$src2),
-                  "cmovae {$src2, $dst|$dst, $src2}">, TB, OpSize;
+                  "cmovae {$src2, $dst|$dst, $src2}", []>, TB, OpSize;
 def CMOVAE32rr: I<0x43, MRMSrcReg,       // if >=u, R32 = R32
                   (ops R32:$dst, R32:$src1, R32:$src2),
-                  "cmovae {$src2, $dst|$dst, $src2}">, TB;
+                  "cmovae {$src2, $dst|$dst, $src2}", []>, TB;
 def CMOVAE32rm: I<0x43, MRMSrcMem,       // if >=u, R32 = [mem32]
                   (ops R32:$dst, R32:$src1, i32mem:$src2),
-                  "cmovae {$src2, $dst|$dst, $src2}">, TB;
+                  "cmovae {$src2, $dst|$dst, $src2}", []>, TB;
 
 def CMOVE16rr : I<0x44, MRMSrcReg,       // if ==, R16 = R16
                   (ops R16:$dst, R16:$src1, R16:$src2),
-                  "cmove {$src2, $dst|$dst, $src2}">, TB, OpSize;
+                  "cmove {$src2, $dst|$dst, $src2}", []>, TB, OpSize;
 def CMOVE16rm : I<0x44, MRMSrcMem,       // if ==, R16 = [mem16]
                   (ops R16:$dst, R16:$src1, i16mem:$src2),
-                  "cmove {$src2, $dst|$dst, $src2}">, TB, OpSize;
+                  "cmove {$src2, $dst|$dst, $src2}", []>, TB, OpSize;
 def CMOVE32rr : I<0x44, MRMSrcReg,       // if ==, R32 = R32
                   (ops R32:$dst, R32:$src1, R32:$src2),
-                  "cmove {$src2, $dst|$dst, $src2}">, TB;
+                  "cmove {$src2, $dst|$dst, $src2}", []>, TB;
 def CMOVE32rm : I<0x44, MRMSrcMem,       // if ==, R32 = [mem32]
                   (ops R32:$dst, R32:$src1, i32mem:$src2),
-                  "cmove {$src2, $dst|$dst, $src2}">, TB;
+                  "cmove {$src2, $dst|$dst, $src2}", []>, TB;
 
 def CMOVNE16rr: I<0x45, MRMSrcReg,       // if !=, R16 = R16
                   (ops R16:$dst, R16:$src1, R16:$src2),
-                  "cmovne {$src2, $dst|$dst, $src2}">, TB, OpSize;
+                  "cmovne {$src2, $dst|$dst, $src2}", []>, TB, OpSize;
 def CMOVNE16rm: I<0x45, MRMSrcMem,       // if !=, R16 = [mem16]
                   (ops R16:$dst, R16:$src1, i16mem:$src2),
-                  "cmovne {$src2, $dst|$dst, $src2}">, TB, OpSize;
+                  "cmovne {$src2, $dst|$dst, $src2}", []>, TB, OpSize;
 def CMOVNE32rr: I<0x45, MRMSrcReg,       // if !=, R32 = R32
                   (ops R32:$dst, R32:$src1, R32:$src2),
-                  "cmovne {$src2, $dst|$dst, $src2}">, TB;
+                  "cmovne {$src2, $dst|$dst, $src2}", []>, TB;
 def CMOVNE32rm: I<0x45, MRMSrcMem,       // if !=, R32 = [mem32]
                   (ops R32:$dst, R32:$src1, i32mem:$src2),
-                  "cmovne {$src2, $dst|$dst, $src2}">, TB;
+                  "cmovne {$src2, $dst|$dst, $src2}", []>, TB;
 
 def CMOVBE16rr: I<0x46, MRMSrcReg,       // if <=u, R16 = R16
                   (ops R16:$dst, R16:$src1, R16:$src2),
-                  "cmovbe {$src2, $dst|$dst, $src2}">, TB, OpSize;
+                  "cmovbe {$src2, $dst|$dst, $src2}", []>, TB, OpSize;
 def CMOVBE16rm: I<0x46, MRMSrcMem,       // if <=u, R16 = [mem16]
                   (ops R16:$dst, R16:$src1, i16mem:$src2),
-                  "cmovbe {$src2, $dst|$dst, $src2}">, TB, OpSize;
+                  "cmovbe {$src2, $dst|$dst, $src2}", []>, TB, OpSize;
 def CMOVBE32rr: I<0x46, MRMSrcReg,       // if <=u, R32 = R32
                   (ops R32:$dst, R32:$src1, R32:$src2),
-                  "cmovbe {$src2, $dst|$dst, $src2}">, TB;
+                  "cmovbe {$src2, $dst|$dst, $src2}", []>, TB;
 def CMOVBE32rm: I<0x46, MRMSrcMem,       // if <=u, R32 = [mem32]
                   (ops R32:$dst, R32:$src1, i32mem:$src2),
-                  "cmovbe {$src2, $dst|$dst, $src2}">, TB;
+                  "cmovbe {$src2, $dst|$dst, $src2}", []>, TB;
 
 def CMOVA16rr : I<0x47, MRMSrcReg,       // if >u, R16 = R16
                   (ops R16:$dst, R16:$src1, R16:$src2),
-                  "cmova {$src2, $dst|$dst, $src2}">, TB, OpSize;
+                  "cmova {$src2, $dst|$dst, $src2}", []>, TB, OpSize;
 def CMOVA16rm : I<0x47, MRMSrcMem,       // if >u, R16 = [mem16]
                   (ops R16:$dst, R16:$src1, i16mem:$src2),
-                  "cmova {$src2, $dst|$dst, $src2}">, TB, OpSize;
+                  "cmova {$src2, $dst|$dst, $src2}", []>, TB, OpSize;
 def CMOVA32rr : I<0x47, MRMSrcReg,       // if >u, R32 = R32
                   (ops R32:$dst, R32:$src1, R32:$src2),
-                  "cmova {$src2, $dst|$dst, $src2}">, TB;
+                  "cmova {$src2, $dst|$dst, $src2}", []>, TB;
 def CMOVA32rm : I<0x47, MRMSrcMem,       // if >u, R32 = [mem32]
                   (ops R32:$dst, R32:$src1, i32mem:$src2),
-                  "cmova {$src2, $dst|$dst, $src2}">, TB;
+                  "cmova {$src2, $dst|$dst, $src2}", []>, TB;
 
 def CMOVS16rr : I<0x48, MRMSrcReg,       // if signed, R16 = R16
                   (ops R16:$dst, R16:$src1, R16:$src2),
-                  "cmovs {$src2, $dst|$dst, $src2}">, TB, OpSize;
+                  "cmovs {$src2, $dst|$dst, $src2}", []>, TB, OpSize;
 def CMOVS16rm : I<0x48, MRMSrcMem,       // if signed, R16 = [mem16]
                   (ops R16:$dst, R16:$src1, i16mem:$src2),
-                  "cmovs {$src2, $dst|$dst, $src2}">, TB, OpSize;
+                  "cmovs {$src2, $dst|$dst, $src2}", []>, TB, OpSize;
 def CMOVS32rr : I<0x48, MRMSrcReg,       // if signed, R32 = R32
                   (ops R32:$dst, R32:$src1, R32:$src2),
-                  "cmovs {$src2, $dst|$dst, $src2}">, TB;
+                  "cmovs {$src2, $dst|$dst, $src2}", []>, TB;
 def CMOVS32rm : I<0x48, MRMSrcMem,       // if signed, R32 = [mem32]
                   (ops R32:$dst, R32:$src1, i32mem:$src2),
-                  "cmovs {$src2, $dst|$dst, $src2}">, TB;
+                  "cmovs {$src2, $dst|$dst, $src2}", []>, TB;
 
 def CMOVNS16rr: I<0x49, MRMSrcReg,       // if !signed, R16 = R16
                   (ops R16:$dst, R16:$src1, R16:$src2),
-                  "cmovns {$src2, $dst|$dst, $src2}">, TB, OpSize;
+                  "cmovns {$src2, $dst|$dst, $src2}", []>, TB, OpSize;
 def CMOVNS16rm: I<0x49, MRMSrcMem,       // if !signed, R16 = [mem16]
                   (ops R16:$dst, R16:$src1, i16mem:$src2),
-                  "cmovns {$src2, $dst|$dst, $src2}">, TB, OpSize;
+                  "cmovns {$src2, $dst|$dst, $src2}", []>, TB, OpSize;
 def CMOVNS32rr: I<0x49, MRMSrcReg,       // if !signed, R32 = R32
                   (ops R32:$dst, R32:$src1, R32:$src2),
-                  "cmovns {$src2, $dst|$dst, $src2}">, TB;
+                  "cmovns {$src2, $dst|$dst, $src2}", []>, TB;
 def CMOVNS32rm: I<0x49, MRMSrcMem,       // if !signed, R32 = [mem32]
                   (ops R32:$dst, R32:$src1, i32mem:$src2),
-                  "cmovns {$src2, $dst|$dst, $src2}">, TB;
+                  "cmovns {$src2, $dst|$dst, $src2}", []>, TB;
 
 def CMOVP16rr : I<0x4A, MRMSrcReg,       // if parity, R16 = R16
                   (ops R16:$dst, R16:$src1, R16:$src2),
-                  "cmovp {$src2, $dst|$dst, $src2}">, TB, OpSize;
+                  "cmovp {$src2, $dst|$dst, $src2}", []>, TB, OpSize;
 def CMOVP16rm : I<0x4A, MRMSrcMem,       // if parity, R16 = [mem16]
                   (ops R16:$dst, R16:$src1, i16mem:$src2),
-                  "cmovp {$src2, $dst|$dst, $src2}">, TB, OpSize;
+                  "cmovp {$src2, $dst|$dst, $src2}", []>, TB, OpSize;
 def CMOVP32rr : I<0x4A, MRMSrcReg,       // if parity, R32 = R32
                   (ops R32:$dst, R32:$src1, R32:$src2),
-                  "cmovp {$src2, $dst|$dst, $src2}">, TB;
+                  "cmovp {$src2, $dst|$dst, $src2}", []>, TB;
 def CMOVP32rm : I<0x4A, MRMSrcMem,       // if parity, R32 = [mem32]
                   (ops R32:$dst, R32:$src1, i32mem:$src2),
-                  "cmovp {$src2, $dst|$dst, $src2}">, TB;
+                  "cmovp {$src2, $dst|$dst, $src2}", []>, TB;
 
  
 def CMOVNP16rr : I<0x4B, MRMSrcReg,       // if !parity, R16 = R16
                   (ops R16:$dst, R16:$src1, R16:$src2),
-                  "cmovnp {$src2, $dst|$dst, $src2}">, TB, OpSize;
+                  "cmovnp {$src2, $dst|$dst, $src2}", []>, TB, OpSize;
 def CMOVNP16rm : I<0x4B, MRMSrcMem,       // if !parity, R16 = [mem16]
                   (ops R16:$dst, R16:$src1, i16mem:$src2),
-                  "cmovnp {$src2, $dst|$dst, $src2}">, TB, OpSize;
+                  "cmovnp {$src2, $dst|$dst, $src2}", []>, TB, OpSize;
 def CMOVNP32rr : I<0x4B, MRMSrcReg,       // if !parity, R32 = R32
                   (ops R32:$dst, R32:$src1, R32:$src2),
-                  "cmovnp {$src2, $dst|$dst, $src2}">, TB;
+                  "cmovnp {$src2, $dst|$dst, $src2}", []>, TB;
 def CMOVNP32rm : I<0x4B, MRMSrcMem,       // if !parity, R32 = [mem32]
                   (ops R32:$dst, R32:$src1, i32mem:$src2),
-                  "cmovnp {$src2, $dst|$dst, $src2}">, TB;
+                  "cmovnp {$src2, $dst|$dst, $src2}", []>, TB;
 
 
 def CMOVL16rr : I<0x4C, MRMSrcReg,       // if <s, R16 = R16
                   (ops R16:$dst, R16:$src1, R16:$src2),
-                  "cmovl {$src2, $dst|$dst, $src2}">, TB, OpSize;
+                  "cmovl {$src2, $dst|$dst, $src2}", []>, TB, OpSize;
 def CMOVL16rm : I<0x4C, MRMSrcMem,       // if <s, R16 = [mem16]
                   (ops R16:$dst, R16:$src1, i16mem:$src2),
-                  "cmovl {$src2, $dst|$dst, $src2}">, TB, OpSize;
+                  "cmovl {$src2, $dst|$dst, $src2}", []>, TB, OpSize;
 def CMOVL32rr : I<0x4C, MRMSrcReg,       // if <s, R32 = R32
                   (ops R32:$dst, R32:$src1, R32:$src2),
-                  "cmovl {$src2, $dst|$dst, $src2}">, TB;
+                  "cmovl {$src2, $dst|$dst, $src2}", []>, TB;
 def CMOVL32rm : I<0x4C, MRMSrcMem,       // if <s, R32 = [mem32]
                   (ops R32:$dst, R32:$src1, i32mem:$src2),
-                  "cmovl {$src2, $dst|$dst, $src2}">, TB;
+                  "cmovl {$src2, $dst|$dst, $src2}", []>, TB;
 
 def CMOVGE16rr: I<0x4D, MRMSrcReg,       // if >=s, R16 = R16
                   (ops R16:$dst, R16:$src1, R16:$src2),
-                  "cmovge {$src2, $dst|$dst, $src2}">, TB, OpSize;
+                  "cmovge {$src2, $dst|$dst, $src2}", []>, TB, OpSize;
 def CMOVGE16rm: I<0x4D, MRMSrcMem,       // if >=s, R16 = [mem16]
                   (ops R16:$dst, R16:$src1, i16mem:$src2),
-                  "cmovge {$src2, $dst|$dst, $src2}">, TB, OpSize;
+                  "cmovge {$src2, $dst|$dst, $src2}", []>, TB, OpSize;
 def CMOVGE32rr: I<0x4D, MRMSrcReg,       // if >=s, R32 = R32
                   (ops R32:$dst, R32:$src1, R32:$src2),
-                  "cmovge {$src2, $dst|$dst, $src2}">, TB;
+                  "cmovge {$src2, $dst|$dst, $src2}", []>, TB;
 def CMOVGE32rm: I<0x4D, MRMSrcMem,       // if >=s, R32 = [mem32]
                   (ops R32:$dst, R32:$src1, i32mem:$src2),
-                  "cmovge {$src2, $dst|$dst, $src2}">, TB;
+                  "cmovge {$src2, $dst|$dst, $src2}", []>, TB;
 
 def CMOVLE16rr: I<0x4E, MRMSrcReg,       // if <=s, R16 = R16
                   (ops R16:$dst, R16:$src1, R16:$src2),
-                  "cmovle {$src2, $dst|$dst, $src2}">, TB, OpSize;
+                  "cmovle {$src2, $dst|$dst, $src2}", []>, TB, OpSize;
 def CMOVLE16rm: I<0x4E, MRMSrcMem,       // if <=s, R16 = [mem16]
                   (ops R16:$dst, R16:$src1, i16mem:$src2),
-                  "cmovle {$src2, $dst|$dst, $src2}">, TB, OpSize;
+                  "cmovle {$src2, $dst|$dst, $src2}", []>, TB, OpSize;
 def CMOVLE32rr: I<0x4E, MRMSrcReg,       // if <=s, R32 = R32
                   (ops R32:$dst, R32:$src1, R32:$src2),
-                  "cmovle {$src2, $dst|$dst, $src2}">, TB;
+                  "cmovle {$src2, $dst|$dst, $src2}", []>, TB;
 def CMOVLE32rm: I<0x4E, MRMSrcMem,       // if <=s, R32 = [mem32]
                   (ops R32:$dst, R32:$src1, i32mem:$src2),
-                  "cmovle {$src2, $dst|$dst, $src2}">, TB;
+                  "cmovle {$src2, $dst|$dst, $src2}", []>, TB;
 
 def CMOVG16rr : I<0x4F, MRMSrcReg,       // if >s, R16 = R16
                   (ops R16:$dst, R16:$src1, R16:$src2),
-                  "cmovg {$src2, $dst|$dst, $src2}">, TB, OpSize;
+                  "cmovg {$src2, $dst|$dst, $src2}", []>, TB, OpSize;
 def CMOVG16rm : I<0x4F, MRMSrcMem,       // if >s, R16 = [mem16]
                   (ops R16:$dst, R16:$src1, i16mem:$src2),
-                  "cmovg {$src2, $dst|$dst, $src2}">, TB, OpSize;
+                  "cmovg {$src2, $dst|$dst, $src2}", []>, TB, OpSize;
 def CMOVG32rr : I<0x4F, MRMSrcReg,       // if >s, R32 = R32
                   (ops R32:$dst, R32:$src1, R32:$src2),
-                  "cmovg {$src2, $dst|$dst, $src2}">, TB;
+                  "cmovg {$src2, $dst|$dst, $src2}", []>, TB;
 def CMOVG32rm : I<0x4F, MRMSrcMem,       // if >s, R32 = [mem32]
                   (ops R32:$dst, R32:$src1, i32mem:$src2),
-                  "cmovg {$src2, $dst|$dst, $src2}">, TB;
+                  "cmovg {$src2, $dst|$dst, $src2}", []>, TB;
 
 // unary instructions
-def NEG8r  : I<0xF6, MRM3r, (ops R8 :$dst, R8 :$src), "neg{b} $dst">;
-def NEG16r : I<0xF7, MRM3r, (ops R16:$dst, R16:$src), "neg{w} $dst">, OpSize;
-def NEG32r : I<0xF7, MRM3r, (ops R32:$dst, R32:$src), "neg{l} $dst">;
+def NEG8r  : I<0xF6, MRM3r, (ops R8 :$dst, R8 :$src), "neg{b} $dst",
+               [(set R8:$dst, (ineg R8:$src))]>;
+def NEG16r : I<0xF7, MRM3r, (ops R16:$dst, R16:$src), "neg{w} $dst",
+               [(set R16:$dst, (ineg R16:$src))]>, OpSize;
+def NEG32r : I<0xF7, MRM3r, (ops R32:$dst, R32:$src), "neg{l} $dst",
+               [(set R32:$dst, (ineg R32:$src))]>;
 let isTwoAddress = 0 in {
-  def NEG8m  : I<0xF6, MRM3m, (ops i8mem :$dst), "neg{b} $dst">;
-  def NEG16m : I<0xF7, MRM3m, (ops i16mem:$dst), "neg{w} $dst">, OpSize;
-  def NEG32m : I<0xF7, MRM3m, (ops i32mem:$dst), "neg{l} $dst">;
+  def NEG8m  : I<0xF6, MRM3m, (ops i8mem :$dst), "neg{b} $dst", []>;
+  def NEG16m : I<0xF7, MRM3m, (ops i16mem:$dst), "neg{w} $dst", []>, OpSize;
+  def NEG32m : I<0xF7, MRM3m, (ops i32mem:$dst), "neg{l} $dst", []>;
 }
 
-def NOT8r  : I<0xF6, MRM2r, (ops R8 :$dst, R8 :$src), "not{b} $dst">;
-def NOT16r : I<0xF7, MRM2r, (ops R16:$dst, R16:$src), "not{w} $dst">, OpSize;
-def NOT32r : I<0xF7, MRM2r, (ops R32:$dst, R32:$src), "not{l} $dst">;
+def NOT8r  : I<0xF6, MRM2r, (ops R8 :$dst, R8 :$src), "not{b} $dst",
+               [(set R8:$dst, (not R8:$src))]>;
+def NOT16r : I<0xF7, MRM2r, (ops R16:$dst, R16:$src), "not{w} $dst",
+               [(set R16:$dst, (not R16:$src))]>, OpSize;
+def NOT32r : I<0xF7, MRM2r, (ops R32:$dst, R32:$src), "not{l} $dst",
+               [(set R32:$dst, (not R32:$src))]>;
 let isTwoAddress = 0 in {
-  def NOT8m  : I<0xF6, MRM2m, (ops i8mem :$dst), "not{b} $dst">;
-  def NOT16m : I<0xF7, MRM2m, (ops i16mem:$dst), "not{w} $dst">, OpSize;
-  def NOT32m : I<0xF7, MRM2m, (ops i32mem:$dst), "not{l} $dst">;
+  def NOT8m  : I<0xF6, MRM2m, (ops i8mem :$dst), "not{b} $dst", []>;
+  def NOT16m : I<0xF7, MRM2m, (ops i16mem:$dst), "not{w} $dst", []>, OpSize;
+  def NOT32m : I<0xF7, MRM2m, (ops i32mem:$dst), "not{l} $dst", []>;
 }
 
-def INC8r  : I<0xFE, MRM0r, (ops R8 :$dst, R8 :$src), "inc{b} $dst">;
+def INC8r  : I<0xFE, MRM0r, (ops R8 :$dst, R8 :$src), "inc{b} $dst",
+               [(set R8:$dst, (add R8:$src, 1))]>;
 let isConvertibleToThreeAddress = 1 in {   // Can transform into LEA.
-def INC16r : I<0xFF, MRM0r, (ops R16:$dst, R16:$src), "inc{w} $dst">, OpSize;
-def INC32r : I<0xFF, MRM0r, (ops R32:$dst, R32:$src), "inc{l} $dst">;
+def INC16r : I<0xFF, MRM0r, (ops R16:$dst, R16:$src), "inc{w} $dst",
+               [(set R16:$dst, (add R16:$src, 1))]>, OpSize;
+def INC32r : I<0xFF, MRM0r, (ops R32:$dst, R32:$src), "inc{l} $dst",
+               [(set R32:$dst, (add R32:$src, 1))]>;
 }
 let isTwoAddress = 0 in {
-  def INC8m  : I<0xFE, MRM0m, (ops i8mem :$dst), "inc{b} $dst">;
-  def INC16m : I<0xFF, MRM0m, (ops i16mem:$dst), "inc{w} $dst">, OpSize;
-  def INC32m : I<0xFF, MRM0m, (ops i32mem:$dst), "inc{l} $dst">;
+  def INC8m  : I<0xFE, MRM0m, (ops i8mem :$dst), "inc{b} $dst", []>;
+  def INC16m : I<0xFF, MRM0m, (ops i16mem:$dst), "inc{w} $dst", []>, OpSize;
+  def INC32m : I<0xFF, MRM0m, (ops i32mem:$dst), "inc{l} $dst", []>;
 }
 
-def DEC8r  : I<0xFE, MRM1r, (ops R8 :$dst, R8 :$src), "dec{b} $dst">;
+def DEC8r  : I<0xFE, MRM1r, (ops R8 :$dst, R8 :$src), "dec{b} $dst", []>;
 let isConvertibleToThreeAddress = 1 in {   // Can transform into LEA.
-def DEC16r : I<0xFF, MRM1r, (ops R16:$dst, R16:$src), "dec{w} $dst">, OpSize;
-def DEC32r : I<0xFF, MRM1r, (ops R32:$dst, R32:$src), "dec{l} $dst">;
+def DEC16r : I<0xFF, MRM1r, (ops R16:$dst, R16:$src), "dec{w} $dst", []>,
+             OpSize;
+def DEC32r : I<0xFF, MRM1r, (ops R32:$dst, R32:$src), "dec{l} $dst", []>;
 }
 
 let isTwoAddress = 0 in {
-  def DEC8m  : I<0xFE, MRM1m, (ops i8mem :$dst), "dec{b} $dst">;
-  def DEC16m : I<0xFF, MRM1m, (ops i16mem:$dst), "dec{w} $dst">, OpSize;
-  def DEC32m : I<0xFF, MRM1m, (ops i32mem:$dst), "dec{l} $dst">;
+  def DEC8m  : I<0xFE, MRM1m, (ops i8mem :$dst), "dec{b} $dst", []>;
+  def DEC16m : I<0xFF, MRM1m, (ops i16mem:$dst), "dec{w} $dst", []>, OpSize;
+  def DEC32m : I<0xFF, MRM1m, (ops i32mem:$dst), "dec{l} $dst", []>;
 }
 
 // Logical operators...
 let isCommutable = 1 in {   // X = AND Y, Z   --> X = AND Z, Y
 def AND8rr   : I<0x20, MRMDestReg,
                 (ops R8 :$dst, R8 :$src1, R8 :$src2),
-                "and{b} {$src2, $dst|$dst, $src2}">;
+                "and{b} {$src2, $dst|$dst, $src2}",
+                [(set R8:$dst, (and R8:$src1, R8:$src2))]>;
 def AND16rr  : I<0x21, MRMDestReg,
                  (ops R16:$dst, R16:$src1, R16:$src2),
-                 "and{w} {$src2, $dst|$dst, $src2}">, OpSize;
+                 "and{w} {$src2, $dst|$dst, $src2}",
+                 [(set R16:$dst, (and R16:$src1, R16:$src2))]>, OpSize;
 def AND32rr  : I<0x21, MRMDestReg, 
                  (ops R32:$dst, R32:$src1, R32:$src2),
-                 "and{l} {$src2, $dst|$dst, $src2}">;
+                 "and{l} {$src2, $dst|$dst, $src2}",
+                 [(set R32:$dst, (and R32:$src1, R32:$src2))]>;
 }
 
 def AND8rm   : I<0x22, MRMSrcMem, 
                  (ops R8 :$dst, R8 :$src1, i8mem :$src2),
-                 "and{b} {$src2, $dst|$dst, $src2}">;
+                 "and{b} {$src2, $dst|$dst, $src2}",[]>;
 def AND16rm  : I<0x23, MRMSrcMem, 
                  (ops R16:$dst, R16:$src1, i16mem:$src2),
-                 "and{w} {$src2, $dst|$dst, $src2}">, OpSize;
+                 "and{w} {$src2, $dst|$dst, $src2}", []>, OpSize;
 def AND32rm  : I<0x23, MRMSrcMem,
                  (ops R32:$dst, R32:$src1, i32mem:$src2),
-                 "and{l} {$src2, $dst|$dst, $src2}">;
+                 "and{l} {$src2, $dst|$dst, $src2}", []>;
 
 def AND8ri   : Ii8<0x80, MRM4r, 
                    (ops R8 :$dst, R8 :$src1, i8imm :$src2),
@@ -718,13 +738,13 @@
 let isTwoAddress = 0 in {
   def AND8mr   : I<0x20, MRMDestMem,
                    (ops i8mem :$dst, R8 :$src),
-                   "and{b} {$src, $dst|$dst, $src}">;
+                   "and{b} {$src, $dst|$dst, $src}", []>;
   def AND16mr  : I<0x21, MRMDestMem,
                    (ops i16mem:$dst, R16:$src),
-                   "and{w} {$src, $dst|$dst, $src}">, OpSize;
+                   "and{w} {$src, $dst|$dst, $src}", []>, OpSize;
   def AND32mr  : I<0x21, MRMDestMem,
                    (ops i32mem:$dst, R32:$src),
-                   "and{l} {$src, $dst|$dst, $src}">;
+                   "and{l} {$src, $dst|$dst, $src}", []>;
   def AND8mi   : Ii8<0x80, MRM4m,
                      (ops i8mem :$dst, i8imm :$src),
                      "and{b} {$src, $dst|$dst, $src}", []>;
@@ -745,18 +765,21 @@
 
 let isCommutable = 1 in {   // X = OR Y, Z   --> X = OR Z, Y
 def OR8rr    : I<0x08, MRMDestReg, (ops R8 :$dst, R8 :$src1, R8 :$src2),
-                 "or{b} {$src2, $dst|$dst, $src2}">;
+                 "or{b} {$src2, $dst|$dst, $src2}",
+                 [(set R8:$dst, (or R8:$src1, R8:$src2))]>;
 def OR16rr   : I<0x09, MRMDestReg, (ops R16:$dst, R16:$src1, R16:$src2),
-                 "or{w} {$src2, $dst|$dst, $src2}">, OpSize;
+                 "or{w} {$src2, $dst|$dst, $src2}",
+                 [(set R16:$dst, (or R16:$src1, R16:$src2))]>, OpSize;
 def OR32rr   : I<0x09, MRMDestReg, (ops R32:$dst, R32:$src1, R32:$src2),
-                 "or{l} {$src2, $dst|$dst, $src2}">;
+                 "or{l} {$src2, $dst|$dst, $src2}",
+                 [(set R32:$dst, (or R32:$src1, R32:$src2))]>;
 }
 def OR8rm    : I<0x0A, MRMSrcMem , (ops R8 :$dst, R8 :$src1, i8mem :$src2),
-                 "or{b} {$src2, $dst|$dst, $src2}">;
+                 "or{b} {$src2, $dst|$dst, $src2}", []>;
 def OR16rm   : I<0x0B, MRMSrcMem , (ops R16:$dst, R16:$src1, i16mem:$src2),
-                 "or{w} {$src2, $dst|$dst, $src2}">, OpSize;
+                 "or{w} {$src2, $dst|$dst, $src2}", []>, OpSize;
 def OR32rm   : I<0x0B, MRMSrcMem , (ops R32:$dst, R32:$src1, i32mem:$src2),
-                 "or{l} {$src2, $dst|$dst, $src2}">;
+                 "or{l} {$src2, $dst|$dst, $src2}", []>;
 
 def OR8ri    : Ii8 <0x80, MRM1r, (ops R8 :$dst, R8 :$src1, i8imm:$src2),
                     "or{b} {$src2, $dst|$dst, $src2}",
@@ -776,11 +799,11 @@
                    [(set R32:$dst, (or R32:$src1, immSExt8:$src2))]>;
 let isTwoAddress = 0 in {
   def OR8mr  : I<0x08, MRMDestMem, (ops i8mem:$dst, R8:$src),
-                 "or{b} {$src, $dst|$dst, $src}">;
+                 "or{b} {$src, $dst|$dst, $src}", []>;
   def OR16mr : I<0x09, MRMDestMem, (ops i16mem:$dst, R16:$src),
-                 "or{w} {$src, $dst|$dst, $src}">, OpSize;
+                 "or{w} {$src, $dst|$dst, $src}", []>, OpSize;
   def OR32mr : I<0x09, MRMDestMem, (ops i32mem:$dst, R32:$src),
-                 "or{l} {$src, $dst|$dst, $src}">;
+                 "or{l} {$src, $dst|$dst, $src}", []>;
   def OR8mi    : Ii8<0x80, MRM1m, (ops i8mem :$dst, i8imm:$src),
                  "or{b} {$src, $dst|$dst, $src}", []>;
   def OR16mi   : Ii16<0x81, MRM1m, (ops i16mem:$dst, i16imm:$src),
@@ -797,24 +820,27 @@
 let isCommutable = 1 in {   // X = XOR Y, Z   --> X = XOR Z, Y
 def XOR8rr   : I<0x30, MRMDestReg,
                  (ops R8 :$dst, R8 :$src1, R8 :$src2),
-                 "xor{b} {$src2, $dst|$dst, $src2}">;
+                 "xor{b} {$src2, $dst|$dst, $src2}",
+                 [(set R8:$dst, (xor R8:$src1, R8:$src2))]>;
 def XOR16rr  : I<0x31, MRMDestReg, 
                  (ops R16:$dst, R16:$src1, R16:$src2), 
-                 "xor{w} {$src2, $dst|$dst, $src2}">, OpSize;
+                 "xor{w} {$src2, $dst|$dst, $src2}",
+                 [(set R16:$dst, (xor R16:$src1, R16:$src2))]>, OpSize;
 def XOR32rr  : I<0x31, MRMDestReg, 
                  (ops R32:$dst, R32:$src1, R32:$src2), 
-                 "xor{l} {$src2, $dst|$dst, $src2}">;
+                 "xor{l} {$src2, $dst|$dst, $src2}",
+                 [(set R32:$dst, (xor R32:$src1, R32:$src2))]>;
 }
 
 def XOR8rm   : I<0x32, MRMSrcMem , 
                  (ops R8 :$dst, R8:$src1, i8mem :$src2), 
-                 "xor{b} {$src2, $dst|$dst, $src2}">;
+                 "xor{b} {$src2, $dst|$dst, $src2}", []>;
 def XOR16rm  : I<0x33, MRMSrcMem , 
                  (ops R16:$dst, R8:$src1, i16mem:$src2), 
-                 "xor{w} {$src2, $dst|$dst, $src2}">, OpSize;
+                 "xor{w} {$src2, $dst|$dst, $src2}", []>, OpSize;
 def XOR32rm  : I<0x33, MRMSrcMem , 
                  (ops R32:$dst, R8:$src1, i32mem:$src2), 
-                 "xor{l} {$src2, $dst|$dst, $src2}">;
+                 "xor{l} {$src2, $dst|$dst, $src2}", []>;
 
 def XOR8ri   : Ii8<0x80, MRM6r, 
                    (ops R8:$dst, R8:$src1, i8imm:$src2), 
@@ -839,13 +865,13 @@
 let isTwoAddress = 0 in {
   def XOR8mr   : I<0x30, MRMDestMem,
                    (ops i8mem :$dst, R8 :$src),
-                   "xor{b} {$src, $dst|$dst, $src}">;
+                   "xor{b} {$src, $dst|$dst, $src}", []>;
   def XOR16mr  : I<0x31, MRMDestMem,
                    (ops i16mem:$dst, R16:$src),
-                   "xor{w} {$src, $dst|$dst, $src}">, OpSize;
+                   "xor{w} {$src, $dst|$dst, $src}", []>, OpSize;
   def XOR32mr  : I<0x31, MRMDestMem,
                    (ops i32mem:$dst, R32:$src),
-                   "xor{l} {$src, $dst|$dst, $src}">;
+                   "xor{l} {$src, $dst|$dst, $src}", []>;
   def XOR8mi   : Ii8<0x80, MRM6m,
                      (ops i8mem :$dst, i8imm :$src),
                      "xor{b} {$src, $dst|$dst, $src}", []>;
@@ -866,11 +892,11 @@
 // Shift instructions
 // FIXME: provide shorter instructions when imm8 == 1
 def SHL8rCL  : I<0xD2, MRM4r, (ops R8 :$dst, R8 :$src),
-                 "shl{b} {%cl, $dst|$dst, %CL}">, Imp<[CL],[]>;
+                 "shl{b} {%cl, $dst|$dst, %CL}", []>, Imp<[CL],[]>;
 def SHL16rCL : I<0xD3, MRM4r, (ops R16:$dst, R16:$src),
-                 "shl{w} {%cl, $dst|$dst, %CL}">, Imp<[CL],[]>, OpSize;
+                 "shl{w} {%cl, $dst|$dst, %CL}", []>, Imp<[CL],[]>, OpSize;
 def SHL32rCL : I<0xD3, MRM4r, (ops R32:$dst, R32:$src),
-                 "shl{l} {%cl, $dst|$dst, %CL}">, Imp<[CL],[]>;
+                 "shl{l} {%cl, $dst|$dst, %CL}", []>, Imp<[CL],[]>;
 
 def SHL8ri   : Ii8<0xC0, MRM4r, (ops R8 :$dst, R8 :$src1, i8imm:$src2),
                    "shl{b} {$src2, $dst|$dst, $src2}",
@@ -886,25 +912,25 @@
 
 let isTwoAddress = 0 in {
   def SHL8mCL  : I<0xD2, MRM4m, (ops i8mem :$dst),
-                   "shl{b} {%cl, $dst|$dst, %CL}">, Imp<[CL],[]>;
+                   "shl{b} {%cl, $dst|$dst, %CL}", []>, Imp<[CL],[]>;
   def SHL16mCL : I<0xD3, MRM4m, (ops i16mem:$dst),
-                   "shl{w} {%cl, $dst|$dst, %CL}">, Imp<[CL],[]>, OpSize;
+                   "shl{w} {%cl, $dst|$dst, %CL}", []>, Imp<[CL],[]>, OpSize;
   def SHL32mCL : I<0xD3, MRM4m, (ops i32mem:$dst),
-                   "shl{l} {%cl, $dst|$dst, %CL}">, Imp<[CL],[]>;
+                   "shl{l} {%cl, $dst|$dst, %CL}", []>, Imp<[CL],[]>;
   def SHL8mi   : Ii8<0xC0, MRM4m, (ops i8mem :$dst, i8imm:$src),
-                     "shl{b} {$src, $dst|$dst, $src}", []>;
+                     "shl{b} {$src, $dst|$dst, $src}, []", []>;
   def SHL16mi  : Ii8<0xC1, MRM4m, (ops i16mem:$dst, i8imm:$src),
-                     "shl{w} {$src, $dst|$dst, $src}", []>, OpSize;
+                     "shl{w} {$src, $dst|$dst, $src}, []", []>, OpSize;
   def SHL32mi  : Ii8<0xC1, MRM4m, (ops i32mem:$dst, i8imm:$src),
-                     "shl{l} {$src, $dst|$dst, $src}", []>;
+                     "shl{l} {$src, $dst|$dst, $src}, []", []>;
 }
 
 def SHR8rCL  : I<0xD2, MRM5r, (ops R8 :$dst, R8 :$src),
-                 "shr{b} {%cl, $dst|$dst, %CL}">, Imp<[CL],[]>;
+                 "shr{b} {%cl, $dst|$dst, %CL}", []>, Imp<[CL],[]>;
 def SHR16rCL : I<0xD3, MRM5r, (ops R16:$dst, R16:$src),
-                 "shr{w} {%cl, $dst|$dst, %CL}">, Imp<[CL],[]>, OpSize;
+                 "shr{w} {%cl, $dst|$dst, %CL}", []>, Imp<[CL],[]>, OpSize;
 def SHR32rCL : I<0xD3, MRM5r, (ops R32:$dst, R32:$src),
-                 "shr{l} {%cl, $dst|$dst, %CL}">, Imp<[CL],[]>;
+                 "shr{l} {%cl, $dst|$dst, %CL}", []>, Imp<[CL],[]>;
 
 def SHR8ri   : Ii8<0xC0, MRM5r, (ops R8:$dst, R8:$src1, i8imm:$src2),
                    "shr{b} {$src2, $dst|$dst, $src2}",
@@ -918,11 +944,11 @@
 
 let isTwoAddress = 0 in {
   def SHR8mCL  : I<0xD2, MRM5m, (ops i8mem :$dst),
-                   "shr{b} {%cl, $dst|$dst, %CL}">, Imp<[CL],[]>;
+                   "shr{b} {%cl, $dst|$dst, %CL}", []>, Imp<[CL],[]>;
   def SHR16mCL : I<0xD3, MRM5m, (ops i16mem:$dst),
-                   "shr{w} {%cl, $dst|$dst, %CL}">, Imp<[CL],[]>, OpSize;
+                   "shr{w} {%cl, $dst|$dst, %CL}", []>, Imp<[CL],[]>, OpSize;
   def SHR32mCL : I<0xD3, MRM5m, (ops i32mem:$dst),
-                   "shr{l} {%cl, $dst|$dst, %CL}">, Imp<[CL],[]>;
+                   "shr{l} {%cl, $dst|$dst, %CL}", []>, Imp<[CL],[]>;
   def SHR8mi   : Ii8<0xC0, MRM5m, (ops i8mem :$dst, i8imm:$src),
                      "shr{b} {$src, $dst|$dst, $src}", []>;
   def SHR16mi  : Ii8<0xC1, MRM5m, (ops i16mem:$dst, i8imm:$src),
@@ -932,11 +958,11 @@
 }
 
 def SAR8rCL  : I<0xD2, MRM7r, (ops R8 :$dst, R8 :$src),
-                 "sar{b} {%cl, $dst|$dst, %CL}">, Imp<[CL],[]>;
+                 "sar{b} {%cl, $dst|$dst, %CL}", []>, Imp<[CL],[]>;
 def SAR16rCL : I<0xD3, MRM7r, (ops R16:$dst, R16:$src),
-                 "sar{w} {%cl, $dst|$dst, %CL}">, Imp<[CL],[]>, OpSize;
+                 "sar{w} {%cl, $dst|$dst, %CL}", []>, Imp<[CL],[]>, OpSize;
 def SAR32rCL : I<0xD3, MRM7r, (ops R32:$dst, R32:$src),
-                 "sar{l} {%cl, $dst|$dst, %CL}">, Imp<[CL],[]>;
+                 "sar{l} {%cl, $dst|$dst, %CL}", []>, Imp<[CL],[]>;
 
 def SAR8ri   : Ii8<0xC0, MRM7r, (ops R8 :$dst, R8 :$src1, i8imm:$src2),
                    "sar{b} {$src2, $dst|$dst, $src2}",
@@ -949,11 +975,11 @@
                    [(set R32:$dst, (sra R32:$src1, immSExt8:$src2))]>;
 let isTwoAddress = 0 in {
   def SAR8mCL  : I<0xD2, MRM7m, (ops i8mem :$dst),
-                   "sar{b} {%cl, $dst|$dst, %CL}">, Imp<[CL],[]>;
+                   "sar{b} {%cl, $dst|$dst, %CL}", []>, Imp<[CL],[]>;
   def SAR16mCL : I<0xD3, MRM7m, (ops i16mem:$dst),
-                   "sar{w} {%cl, $dst|$dst, %CL}">, Imp<[CL],[]>, OpSize;
+                   "sar{w} {%cl, $dst|$dst, %CL}", []>, Imp<[CL],[]>, OpSize;
   def SAR32mCL : I<0xD3, MRM7m, (ops i32mem:$dst), 
-                   "sar{l} {%cl, $dst|$dst, %CL}">, Imp<[CL],[]>;
+                   "sar{l} {%cl, $dst|$dst, %CL}", []>, Imp<[CL],[]>;
   def SAR8mi   : Ii8<0xC0, MRM7m, (ops i8mem :$dst, i8imm:$src),
                      "sar{b} {$src, $dst|$dst, $src}", []>;
   def SAR16mi  : Ii8<0xC1, MRM7m, (ops i16mem:$dst, i8imm:$src),
@@ -965,11 +991,11 @@
 // Rotate instructions
 // FIXME: provide shorter instructions when imm8 == 1
 def ROL8rCL  : I<0xD2, MRM0r, (ops R8 :$dst, R8 :$src),
-                 "rol{b} {%cl, $dst|$dst, %CL}">, Imp<[CL],[]>;
+                 "rol{b} {%cl, $dst|$dst, %CL}", []>, Imp<[CL],[]>;
 def ROL16rCL : I<0xD3, MRM0r, (ops R16:$dst, R16:$src),
-                 "rol{w} {%cl, $dst|$dst, %CL}">, Imp<[CL],[]>, OpSize;
+                 "rol{w} {%cl, $dst|$dst, %CL}", []>, Imp<[CL],[]>, OpSize;
 def ROL32rCL : I<0xD3, MRM0r, (ops R32:$dst, R32:$src),
-                 "rol{l} {%cl, $dst|$dst, %CL}">, Imp<[CL],[]>;
+                 "rol{l} {%cl, $dst|$dst, %CL}", []>, Imp<[CL],[]>;
 
 def ROL8ri   : Ii8<0xC0, MRM0r, (ops R8 :$dst, R8 :$src1, i8imm:$src2),
                    "rol{b} {$src2, $dst|$dst, $src2}", []>;
@@ -980,11 +1006,11 @@
 
 let isTwoAddress = 0 in {
   def ROL8mCL  : I<0xD2, MRM0m, (ops i8mem :$dst),
-                   "rol{b} {%cl, $dst|$dst, %CL}">, Imp<[CL],[]>;
+                   "rol{b} {%cl, $dst|$dst, %CL}", []>, Imp<[CL],[]>;
   def ROL16mCL : I<0xD3, MRM0m, (ops i16mem:$dst),
-                   "rol{w} {%cl, $dst|$dst, %CL}">, Imp<[CL],[]>, OpSize;
+                   "rol{w} {%cl, $dst|$dst, %CL}", []>, Imp<[CL],[]>, OpSize;
   def ROL32mCL : I<0xD3, MRM0m, (ops i32mem:$dst),
-                   "rol{l} {%cl, $dst|$dst, %CL}">, Imp<[CL],[]>;
+                   "rol{l} {%cl, $dst|$dst, %CL}", []>, Imp<[CL],[]>;
   def ROL8mi   : Ii8<0xC0, MRM0m, (ops i8mem :$dst, i8imm:$src),
                      "rol{b} {$src, $dst|$dst, $src}", []>;
   def ROL16mi  : Ii8<0xC1, MRM0m, (ops i16mem:$dst, i8imm:$src),
@@ -994,11 +1020,11 @@
 }
 
 def ROR8rCL  : I<0xD2, MRM1r, (ops R8 :$dst, R8 :$src),
-                 "ror{b} {%cl, $dst|$dst, %CL}">, Imp<[CL],[]>;
+                 "ror{b} {%cl, $dst|$dst, %CL}", []>, Imp<[CL],[]>;
 def ROR16rCL : I<0xD3, MRM1r, (ops R16:$dst, R16:$src),
-                 "ror{w} {%cl, $dst|$dst, %CL}">, Imp<[CL],[]>, OpSize;
+                 "ror{w} {%cl, $dst|$dst, %CL}", []>, Imp<[CL],[]>, OpSize;
 def ROR32rCL : I<0xD3, MRM1r, (ops R32:$dst, R32:$src),
-                 "ror{l} {%cl, $dst|$dst, %CL}">, Imp<[CL],[]>;
+                 "ror{l} {%cl, $dst|$dst, %CL}", []>, Imp<[CL],[]>;
 
 def ROR8ri   : Ii8<0xC0, MRM1r, (ops R8 :$dst, R8 :$src1, i8imm:$src2),
                    "ror{b} {$src2, $dst|$dst, $src2}", []>;
@@ -1008,11 +1034,11 @@
                    "ror{l} {$src2, $dst|$dst, $src2}", []>;
 let isTwoAddress = 0 in {
   def ROR8mCL  : I<0xD2, MRM1m, (ops i8mem :$dst),
-                   "ror{b} {%cl, $dst|$dst, %CL}">, Imp<[CL],[]>;
+                   "ror{b} {%cl, $dst|$dst, %CL}", []>, Imp<[CL],[]>;
   def ROR16mCL : I<0xD3, MRM1m, (ops i16mem:$dst),
-                   "ror{w} {%cl, $dst|$dst, %CL}">, Imp<[CL],[]>, OpSize;
+                   "ror{w} {%cl, $dst|$dst, %CL}", []>, Imp<[CL],[]>, OpSize;
   def ROR32mCL : I<0xD3, MRM1m, (ops i32mem:$dst), 
-                   "ror{l} {%cl, $dst|$dst, %CL}">, Imp<[CL],[]>;
+                   "ror{l} {%cl, $dst|$dst, %CL}", []>, Imp<[CL],[]>;
   def ROR8mi   : Ii8<0xC0, MRM1m, (ops i8mem :$dst, i8imm:$src),
                      "ror{b} {$src, $dst|$dst, $src}", []>;
   def ROR16mi  : Ii8<0xC1, MRM1m, (ops i16mem:$dst, i8imm:$src),
@@ -1026,16 +1052,16 @@
 // Double shift instructions (generalizations of rotate)
 
 def SHLD32rrCL : I<0xA5, MRMDestReg, (ops R32:$dst, R32:$src1, R32:$src2),
-                   "shld{l} {%cl, $src2, $dst|$dst, $src2, %CL}">,
+                   "shld{l} {%cl, $src2, $dst|$dst, $src2, %CL}", []>,
                    Imp<[CL],[]>, TB;
 def SHRD32rrCL : I<0xAD, MRMDestReg, (ops R32:$dst, R32:$src1, R32:$src2),
-                   "shrd{l} {%cl, $src2, $dst|$dst, $src2, %CL}">,
+                   "shrd{l} {%cl, $src2, $dst|$dst, $src2, %CL}", []>,
                    Imp<[CL],[]>, TB;
 def SHLD16rrCL : I<0xA5, MRMDestReg, (ops R16:$dst, R16:$src1, R16:$src2),
-                   "shld{w} {%cl, $src2, $dst|$dst, $src2, %CL}">,
+                   "shld{w} {%cl, $src2, $dst|$dst, $src2, %CL}", []>,
                    Imp<[CL],[]>, TB, OpSize;
 def SHRD16rrCL : I<0xAD, MRMDestReg, (ops R16:$dst, R16:$src1, R16:$src2),
-                   "shrd{w} {%cl, $src2, $dst|$dst, $src2, %CL}">,
+                   "shrd{w} {%cl, $src2, $dst|$dst, $src2, %CL}", []>,
                    Imp<[CL],[]>, TB, OpSize;
 
 let isCommutable = 1 in {  // These instructions commute to each other.
@@ -1057,10 +1083,10 @@
 
 let isTwoAddress = 0 in {
   def SHLD32mrCL : I<0xA5, MRMDestMem, (ops i32mem:$dst, R32:$src2),
-                     "shld{l} {%cl, $src2, $dst|$dst, $src2, %CL}">,
+                     "shld{l} {%cl, $src2, $dst|$dst, $src2, %CL}", []>,
                      Imp<[CL],[]>, TB;
   def SHRD32mrCL : I<0xAD, MRMDestMem, (ops i32mem:$dst, R32:$src2),
-                    "shrd{l} {%cl, $src2, $dst|$dst, $src2, %CL}">,
+                    "shrd{l} {%cl, $src2, $dst|$dst, $src2, %CL}", []>,
                     Imp<[CL],[]>, TB;
   def SHLD32mri8 : Ii8<0xA4, MRMDestMem,
                       (ops i32mem:$dst, R32:$src2, i8imm:$src3),
@@ -1072,10 +1098,10 @@
                        TB;
 
   def SHLD16mrCL : I<0xA5, MRMDestMem, (ops i16mem:$dst, R16:$src2),
-                     "shld{w} {%cl, $src2, $dst|$dst, $src2, %CL}">,
+                     "shld{w} {%cl, $src2, $dst|$dst, $src2, %CL}", []>,
                      Imp<[CL],[]>, TB, OpSize;
   def SHRD16mrCL : I<0xAD, MRMDestMem, (ops i16mem:$dst, R16:$src2),
-                    "shrd{w} {%cl, $src2, $dst|$dst, $src2, %CL}">,
+                    "shrd{w} {%cl, $src2, $dst|$dst, $src2, %CL}", []>,
                     Imp<[CL],[]>, TB, OpSize;
   def SHLD16mri8 : Ii8<0xA4, MRMDestMem,
                       (ops i16mem:$dst, R16:$src2, i8imm:$src3),
@@ -1091,20 +1117,23 @@
 // Arithmetic.
 let isCommutable = 1 in {   // X = ADD Y, Z   --> X = ADD Z, Y
 def ADD8rr   : I<0x00, MRMDestReg, (ops R8 :$dst, R8 :$src1, R8 :$src2),
-                 "add{b} {$src2, $dst|$dst, $src2}">;
+                 "add{b} {$src2, $dst|$dst, $src2}",
+                 [(set R8:$dst, (add R8:$src1, R8:$src2))]>;
 let isConvertibleToThreeAddress = 1 in {   // Can transform into LEA.
 def ADD16rr  : I<0x01, MRMDestReg, (ops R16:$dst, R16:$src1, R16:$src2),
-                 "add{w} {$src2, $dst|$dst, $src2}">, OpSize;
+                 "add{w} {$src2, $dst|$dst, $src2}",
+                 [(set R16:$dst, (add R16:$src1, R16:$src2))]>, OpSize;
 def ADD32rr  : I<0x01, MRMDestReg, (ops R32:$dst, R32:$src1, R32:$src2),
-                 "add{l} {$src2, $dst|$dst, $src2}">;
+                 "add{l} {$src2, $dst|$dst, $src2}",
+                 [(set R32:$dst, (add R32:$src1, R32:$src2))]>;
 } // end isConvertibleToThreeAddress
 } // end isCommutable
 def ADD8rm   : I<0x02, MRMSrcMem, (ops R8 :$dst, R8 :$src1, i8mem :$src2),
-                 "add{b} {$src2, $dst|$dst, $src2}">;
+                 "add{b} {$src2, $dst|$dst, $src2}", []>;
 def ADD16rm  : I<0x03, MRMSrcMem, (ops R16:$dst, R16:$src1, i16mem:$src2),
-                 "add{w} {$src2, $dst|$dst, $src2}">, OpSize;
+                 "add{w} {$src2, $dst|$dst, $src2}", []>, OpSize;
 def ADD32rm  : I<0x03, MRMSrcMem, (ops R32:$dst, R32:$src1, i32mem:$src2),
-                 "add{l} {$src2, $dst|$dst, $src2}">;
+                 "add{l} {$src2, $dst|$dst, $src2}", []>;
 
 def ADD8ri   : Ii8<0x80, MRM0r, (ops R8:$dst, R8:$src1, i8imm:$src2),
                    "add{b} {$src2, $dst|$dst, $src2}",
@@ -1129,11 +1158,11 @@
 
 let isTwoAddress = 0 in {
   def ADD8mr   : I<0x00, MRMDestMem, (ops i8mem :$dst, R8 :$src2),
-                   "add{b} {$src2, $dst|$dst, $src2}">;
+                   "add{b} {$src2, $dst|$dst, $src2}", []>;
   def ADD16mr  : I<0x01, MRMDestMem, (ops i16mem:$dst, R16:$src2),
-                   "add{w} {$src2, $dst|$dst, $src2}">, OpSize;
+                   "add{w} {$src2, $dst|$dst, $src2}", []>, OpSize;
   def ADD32mr  : I<0x01, MRMDestMem, (ops i32mem:$dst, R32:$src2),
-                   "add{l} {$src2, $dst|$dst, $src2}">;
+                   "add{l} {$src2, $dst|$dst, $src2}", []>;
   def ADD8mi   : Ii8<0x80, MRM0m, (ops i8mem :$dst, i8imm :$src2),
                      "add{b} {$src2, $dst|$dst, $src2}", []>;
   def ADD16mi  : Ii16<0x81, MRM0m, (ops i16mem:$dst, i16imm:$src2),
@@ -1148,10 +1177,10 @@
 
 let isCommutable = 1 in {  // X = ADC Y, Z --> X = ADC Z, Y
 def ADC32rr  : I<0x11, MRMDestReg, (ops R32:$dst, R32:$src1, R32:$src2),
-                 "adc{l} {$src2, $dst|$dst, $src2}">;
+                 "adc{l} {$src2, $dst|$dst, $src2}", []>;
 }
 def ADC32rm  : I<0x13, MRMSrcMem , (ops R32:$dst, R32:$src1, i32mem:$src2),
-                 "adc{l} {$src2, $dst|$dst, $src2}">;
+                 "adc{l} {$src2, $dst|$dst, $src2}", []>;
 def ADC32ri  : Ii32<0x81, MRM2r, (ops R32:$dst, R32:$src1, i32imm:$src2),
                     "adc{l} {$src2, $dst|$dst, $src2}", []>;
 def ADC32ri8 : Ii8<0x83, MRM2r, (ops R32:$dst, R32:$src1, i8imm:$src2),
@@ -1159,7 +1188,7 @@
 
 let isTwoAddress = 0 in {
   def ADC32mr  : I<0x11, MRMDestMem, (ops i32mem:$dst, R32:$src2),
-                   "adc{l} {$src2, $dst|$dst, $src2}">;
+                   "adc{l} {$src2, $dst|$dst, $src2}", []>;
   def ADC32mi  : Ii32<0x81, MRM2m, (ops i32mem:$dst, i32imm:$src2),
                       "adc{l} {$src2, $dst|$dst, $src2}", []>;
   def ADC32mi8 : Ii8<0x83, MRM2m, (ops i32mem:$dst, i8imm :$src2),
@@ -1167,17 +1196,20 @@
 }
 
 def SUB8rr   : I<0x28, MRMDestReg, (ops R8 :$dst, R8 :$src1, R8 :$src2),
-                 "sub{b} {$src2, $dst|$dst, $src2}">;
+                 "sub{b} {$src2, $dst|$dst, $src2}",
+                 [(set R8:$dst, (sub R8:$src1, R8:$src2))]>;
 def SUB16rr  : I<0x29, MRMDestReg, (ops R16:$dst, R16:$src1, R16:$src2),
-                 "sub{w} {$src2, $dst|$dst, $src2}">, OpSize;
+                 "sub{w} {$src2, $dst|$dst, $src2}",
+                 [(set R16:$dst, (sub R16:$src1, R16:$src2))]>, OpSize;
 def SUB32rr  : I<0x29, MRMDestReg, (ops R32:$dst, R32:$src1, R32:$src2),
-                 "sub{l} {$src2, $dst|$dst, $src2}">;
+                 "sub{l} {$src2, $dst|$dst, $src2}",
+                 [(set R32:$dst, (sub R32:$src1, R32:$src2))]>;
 def SUB8rm   : I<0x2A, MRMSrcMem, (ops R8 :$dst, R8 :$src1, i8mem :$src2),
-                 "sub{b} {$src2, $dst|$dst, $src2}">;
+                 "sub{b} {$src2, $dst|$dst, $src2}", []>;
 def SUB16rm  : I<0x2B, MRMSrcMem, (ops R16:$dst, R16:$src1, i16mem:$src2),
-                 "sub{w} {$src2, $dst|$dst, $src2}">, OpSize;
+                 "sub{w} {$src2, $dst|$dst, $src2}", []>, OpSize;
 def SUB32rm  : I<0x2B, MRMSrcMem, (ops R32:$dst, R32:$src1, i32mem:$src2),
-                 "sub{l} {$src2, $dst|$dst, $src2}">;
+                 "sub{l} {$src2, $dst|$dst, $src2}", []>;
 
 def SUB8ri   : Ii8 <0x80, MRM5r, (ops R8:$dst, R8:$src1, i8imm:$src2),
                     "sub{b} {$src2, $dst|$dst, $src2}",
@@ -1196,11 +1228,11 @@
                    [(set R32:$dst, (sub R32:$src1, immSExt8:$src2))]>;
 let isTwoAddress = 0 in {
   def SUB8mr   : I<0x28, MRMDestMem, (ops i8mem :$dst, R8 :$src2),
-                   "sub{b} {$src2, $dst|$dst, $src2}">;
+                   "sub{b} {$src2, $dst|$dst, $src2}", []>;
   def SUB16mr  : I<0x29, MRMDestMem, (ops i16mem:$dst, R16:$src2),
-                   "sub{w} {$src2, $dst|$dst, $src2}">, OpSize;
+                   "sub{w} {$src2, $dst|$dst, $src2}", []>, OpSize;
   def SUB32mr  : I<0x29, MRMDestMem, (ops i32mem:$dst, R32:$src2), 
-                   "sub{l} {$src2, $dst|$dst, $src2}">;
+                   "sub{l} {$src2, $dst|$dst, $src2}", []>;
   def SUB8mi   : Ii8<0x80, MRM5m, (ops i8mem :$dst, i8imm:$src2), 
                      "sub{b} {$src2, $dst|$dst, $src2}", []>;
   def SUB16mi  : Ii16<0x81, MRM5m, (ops i16mem:$dst, i16imm:$src2), 
@@ -1214,11 +1246,11 @@
 }
 
 def SBB32rr    : I<0x19, MRMDestReg, (ops R32:$dst, R32:$src1, R32:$src2),
-                  "sbb{l} {$src2, $dst|$dst, $src2}">;
+                  "sbb{l} {$src2, $dst|$dst, $src2}", []>;
 
 let isTwoAddress = 0 in {
   def SBB32mr  : I<0x19, MRMDestMem, (ops i32mem:$dst, R32:$src2), 
-                   "sbb{l} {$src2, $dst|$dst, $src2}">;
+                   "sbb{l} {$src2, $dst|$dst, $src2}", []>;
   def SBB8mi  : Ii32<0x80, MRM3m, (ops i8mem:$dst, i8imm:$src2), 
                       "sbb{b} {$src2, $dst|$dst, $src2}", []>;
   def SBB16mi  : Ii32<0x81, MRM3m, (ops i16mem:$dst, i16imm:$src2), 
@@ -1236,7 +1268,7 @@
                     "sbb{w} {$src2, $dst|$dst, $src2}", []>, OpSize;
 
 def SBB32rm  : I<0x1B, MRMSrcMem, (ops R32:$dst, R32:$src1, i32mem:$src2),
-                    "sbb{l} {$src2, $dst|$dst, $src2}">;
+                    "sbb{l} {$src2, $dst|$dst, $src2}", []>;
 def SBB32ri  : Ii32<0x81, MRM3r, (ops R32:$dst, R32:$src1, i32imm:$src2),
                     "sbb{l} {$src2, $dst|$dst, $src2}", []>;
 
@@ -1247,14 +1279,16 @@
 
 let isCommutable = 1 in {  // X = IMUL Y, Z --> X = IMUL Z, Y
 def IMUL16rr : I<0xAF, MRMSrcReg, (ops R16:$dst, R16:$src1, R16:$src2),
-                 "imul{w} {$src2, $dst|$dst, $src2}">, TB, OpSize;
+                 "imul{w} {$src2, $dst|$dst, $src2}",
+                 [(set R16:$dst, (mul R16:$src1, R16:$src2))]>, TB, OpSize;
 def IMUL32rr : I<0xAF, MRMSrcReg, (ops R32:$dst, R32:$src1, R32:$src2),
-                 "imul{l} {$src2, $dst|$dst, $src2}">, TB;
+                 "imul{l} {$src2, $dst|$dst, $src2}",
+                 [(set R32:$dst, (mul R32:$src1, R32:$src2))]>, TB;
 }
 def IMUL16rm : I<0xAF, MRMSrcMem, (ops R16:$dst, R16:$src1, i16mem:$src2),
-                 "imul{w} {$src2, $dst|$dst, $src2}">, TB, OpSize;
+                 "imul{w} {$src2, $dst|$dst, $src2}", []>, TB, OpSize;
 def IMUL32rm : I<0xAF, MRMSrcMem, (ops R32:$dst, R32:$src1, i32mem:$src2),
-                 "imul{l} {$src2, $dst|$dst, $src2}">, TB;
+                 "imul{l} {$src2, $dst|$dst, $src2}", []>, TB;
 
 } // end Two Address instructions
 
@@ -1295,24 +1329,24 @@
 //
 let isCommutable = 1 in {   // TEST X, Y   --> TEST Y, X
 def TEST8rr  : I<0x84, MRMDestReg, (ops R8:$src1, R8:$src2),
-                 "test{b} {$src2, $src1|$src1, $src2}">;
+                 "test{b} {$src2, $src1|$src1, $src2}", []>;
 def TEST16rr : I<0x85, MRMDestReg, (ops R16:$src1, R16:$src2),
-                 "test{w} {$src2, $src1|$src1, $src2}">, OpSize;
+                 "test{w} {$src2, $src1|$src1, $src2}", []>, OpSize;
 def TEST32rr : I<0x85, MRMDestReg, (ops R32:$src1, R32:$src2),
-                 "test{l} {$src2, $src1|$src1, $src2}">;
+                 "test{l} {$src2, $src1|$src1, $src2}", []>;
 }
 def TEST8mr  : I<0x84, MRMDestMem, (ops i8mem :$src1, R8 :$src2),
-                 "test{b} {$src2, $src1|$src1, $src2}">;
+                 "test{b} {$src2, $src1|$src1, $src2}", []>;
 def TEST16mr : I<0x85, MRMDestMem, (ops i16mem:$src1, R16:$src2),
-                 "test{w} {$src2, $src1|$src1, $src2}">, OpSize;
+                 "test{w} {$src2, $src1|$src1, $src2}", []>, OpSize;
 def TEST32mr : I<0x85, MRMDestMem, (ops i32mem:$src1, R32:$src2),
-                 "test{l} {$src2, $src1|$src1, $src2}">;
+                 "test{l} {$src2, $src1|$src1, $src2}", []>;
 def TEST8rm  : I<0x84, MRMSrcMem, (ops R8 :$src1, i8mem :$src2),
-                 "test{b} {$src2, $src1|$src1, $src2}">;
+                 "test{b} {$src2, $src1|$src1, $src2}", []>;
 def TEST16rm : I<0x85, MRMSrcMem, (ops R16:$src1, i16mem:$src2),
-                 "test{w} {$src2, $src1|$src1, $src2}">, OpSize;
+                 "test{w} {$src2, $src1|$src1, $src2}", []>, OpSize;
 def TEST32rm : I<0x85, MRMSrcMem, (ops R32:$src1, i32mem:$src2),
-                 "test{l} {$src2, $src1|$src1, $src2}">;
+                 "test{l} {$src2, $src1|$src1, $src2}", []>;
 
 def TEST8ri  : Ii8 <0xF6, MRM0r,                     // flags = R8  & imm8
                     (ops R8:$src1, i8imm:$src2),
@@ -1336,94 +1370,94 @@
 
 
 // Condition code ops, incl. set if equal/not equal/...
-def SAHF     : I<0x9E, RawFrm, (ops), "sahf">, Imp<[AH],[]>;  // flags = AH
-def LAHF     : I<0x9F, RawFrm, (ops), "lahf">, Imp<[],[AH]>;  // AH = flags
+def SAHF     : I<0x9E, RawFrm, (ops), "sahf", []>, Imp<[AH],[]>;  // flags = AH
+def LAHF     : I<0x9F, RawFrm, (ops), "lahf", []>, Imp<[],[AH]>;  // AH = flags
 
 def SETBr    : I<0x92, MRM0r,
-                 (ops R8   :$dst), "setb $dst">, TB;    // R8 = <  unsign
+                 (ops R8   :$dst), "setb $dst", []>, TB;    // R8 = <  unsign
 def SETBm    : I<0x92, MRM0m,
-                 (ops i8mem:$dst), "setb $dst">, TB;    // [mem8] = <  unsign
+                 (ops i8mem:$dst), "setb $dst", []>, TB;    // [mem8] = <  unsign
 def SETAEr   : I<0x93, MRM0r, 
-                 (ops R8   :$dst), "setae $dst">, TB;   // R8 = >= unsign
+                 (ops R8   :$dst), "setae $dst", []>, TB;   // R8 = >= unsign
 def SETAEm   : I<0x93, MRM0m, 
-                 (ops i8mem:$dst), "setae $dst">, TB;   // [mem8] = >= unsign
+                 (ops i8mem:$dst), "setae $dst", []>, TB;   // [mem8] = >= unsign
 def SETEr    : I<0x94, MRM0r, 
-                 (ops R8   :$dst), "sete $dst">, TB;    // R8 = ==
+                 (ops R8   :$dst), "sete $dst", []>, TB;    // R8 = ==
 def SETEm    : I<0x94, MRM0m, 
-                 (ops i8mem:$dst), "sete $dst">, TB;    // [mem8] = ==
+                 (ops i8mem:$dst), "sete $dst", []>, TB;    // [mem8] = ==
 def SETNEr   : I<0x95, MRM0r, 
-                 (ops R8   :$dst), "setne $dst">, TB;   // R8 = !=
+                 (ops R8   :$dst), "setne $dst", []>, TB;   // R8 = !=
 def SETNEm   : I<0x95, MRM0m, 
-                 (ops i8mem:$dst), "setne $dst">, TB;   // [mem8] = !=
+                 (ops i8mem:$dst), "setne $dst", []>, TB;   // [mem8] = !=
 def SETBEr   : I<0x96, MRM0r, 
-                 (ops R8   :$dst), "setbe $dst">, TB;   // R8 = <= unsign
+                 (ops R8   :$dst), "setbe $dst", []>, TB;   // R8 = <= unsign
 def SETBEm   : I<0x96, MRM0m, 
-                 (ops i8mem:$dst), "setbe $dst">, TB;   // [mem8] = <= unsign
+                 (ops i8mem:$dst), "setbe $dst", []>, TB;   // [mem8] = <= unsign
 def SETAr    : I<0x97, MRM0r, 
-                 (ops R8   :$dst), "seta $dst">, TB;    // R8 = >  signed
+                 (ops R8   :$dst), "seta $dst", []>, TB;    // R8 = >  signed
 def SETAm    : I<0x97, MRM0m, 
-                 (ops i8mem:$dst), "seta $dst">, TB;    // [mem8] = >  signed
+                 (ops i8mem:$dst), "seta $dst", []>, TB;    // [mem8] = >  signed
 def SETSr    : I<0x98, MRM0r, 
-                 (ops R8   :$dst), "sets $dst">, TB;    // R8 = <sign bit>
+                 (ops R8   :$dst), "sets $dst", []>, TB;    // R8 = <sign bit>
 def SETSm    : I<0x98, MRM0m, 
-                 (ops i8mem:$dst), "sets $dst">, TB;    // [mem8] = <sign bit>
+                 (ops i8mem:$dst), "sets $dst", []>, TB;    // [mem8] = <sign bit>
 def SETNSr   : I<0x99, MRM0r, 
-                 (ops R8   :$dst), "setns $dst">, TB;   // R8 = !<sign bit>
+                 (ops R8   :$dst), "setns $dst", []>, TB;   // R8 = !<sign bit>
 def SETNSm   : I<0x99, MRM0m, 
-                 (ops i8mem:$dst), "setns $dst">, TB;   // [mem8] = !<sign bit>
+                 (ops i8mem:$dst), "setns $dst", []>, TB;   // [mem8] = !<sign bit>
 def SETPr    : I<0x9A, MRM0r, 
-                 (ops R8   :$dst), "setp $dst">, TB;    // R8 = parity
+                 (ops R8   :$dst), "setp $dst", []>, TB;    // R8 = parity
 def SETPm    : I<0x9A, MRM0m, 
-                 (ops i8mem:$dst), "setp $dst">, TB;    // [mem8] = parity
+                 (ops i8mem:$dst), "setp $dst", []>, TB;    // [mem8] = parity
 def SETNPr   : I<0x9B, MRM0r, 
-                 (ops R8   :$dst), "setnp $dst">, TB;   // R8 = not parity
+                 (ops R8   :$dst), "setnp $dst", []>, TB;   // R8 = not parity
 def SETNPm   : I<0x9B, MRM0m, 
-                 (ops i8mem:$dst), "setnp $dst">, TB;   // [mem8] = not parity
+                 (ops i8mem:$dst), "setnp $dst", []>, TB;   // [mem8] = not parity
 def SETLr    : I<0x9C, MRM0r, 
-                 (ops R8   :$dst), "setl $dst">, TB;    // R8 = <  signed
+                 (ops R8   :$dst), "setl $dst", []>, TB;    // R8 = <  signed
 def SETLm    : I<0x9C, MRM0m, 
-                 (ops i8mem:$dst), "setl $dst">, TB;    // [mem8] = <  signed
+                 (ops i8mem:$dst), "setl $dst", []>, TB;    // [mem8] = <  signed
 def SETGEr   : I<0x9D, MRM0r, 
-                 (ops R8   :$dst), "setge $dst">, TB;   // R8 = >= signed
+                 (ops R8   :$dst), "setge $dst", []>, TB;   // R8 = >= signed
 def SETGEm   : I<0x9D, MRM0m, 
-                 (ops i8mem:$dst), "setge $dst">, TB;   // [mem8] = >= signed
+                 (ops i8mem:$dst), "setge $dst", []>, TB;   // [mem8] = >= signed
 def SETLEr   : I<0x9E, MRM0r, 
-                 (ops R8   :$dst), "setle $dst">, TB;   // R8 = <= signed
+                 (ops R8   :$dst), "setle $dst", []>, TB;   // R8 = <= signed
 def SETLEm   : I<0x9E, MRM0m, 
-                 (ops i8mem:$dst), "setle $dst">, TB;   // [mem8] = <= signed
+                 (ops i8mem:$dst), "setle $dst", []>, TB;   // [mem8] = <= signed
 def SETGr    : I<0x9F, MRM0r, 
-                 (ops R8   :$dst), "setg $dst">, TB;    // R8 = <  signed
+                 (ops R8   :$dst), "setg $dst", []>, TB;    // R8 = <  signed
 def SETGm    : I<0x9F, MRM0m, 
-                 (ops i8mem:$dst), "setg $dst">, TB;    // [mem8] = <  signed
+                 (ops i8mem:$dst), "setg $dst", []>, TB;    // [mem8] = <  signed
 
 // Integer comparisons
 def CMP8rr  : I<0x38, MRMDestReg,
                 (ops R8 :$src1, R8 :$src2),
-                "cmp{b} {$src2, $src1|$src1, $src2}">;
+                "cmp{b} {$src2, $src1|$src1, $src2}", []>;
 def CMP16rr : I<0x39, MRMDestReg,
                 (ops R16:$src1, R16:$src2),
-                "cmp{w} {$src2, $src1|$src1, $src2}">, OpSize;
+                "cmp{w} {$src2, $src1|$src1, $src2}", []>, OpSize;
 def CMP32rr : I<0x39, MRMDestReg,
                 (ops R32:$src1, R32:$src2),
-                "cmp{l} {$src2, $src1|$src1, $src2}">;
+                "cmp{l} {$src2, $src1|$src1, $src2}", []>;
 def CMP8mr  : I<0x38, MRMDestMem,
                 (ops i8mem :$src1, R8 :$src2),
-                "cmp{b} {$src2, $src1|$src1, $src2}">;
+                "cmp{b} {$src2, $src1|$src1, $src2}", []>;
 def CMP16mr : I<0x39, MRMDestMem,
                 (ops i16mem:$src1, R16:$src2),
-                "cmp{w} {$src2, $src1|$src1, $src2}">, OpSize;
+                "cmp{w} {$src2, $src1|$src1, $src2}", []>, OpSize;
 def CMP32mr : I<0x39, MRMDestMem,
                 (ops i32mem:$src1, R32:$src2),
-                "cmp{l} {$src2, $src1|$src1, $src2}">;
+                "cmp{l} {$src2, $src1|$src1, $src2}", []>;
 def CMP8rm  : I<0x3A, MRMSrcMem,
                 (ops R8 :$src1, i8mem :$src2),
-                "cmp{b} {$src2, $src1|$src1, $src2}">;
+                "cmp{b} {$src2, $src1|$src1, $src2}", []>;
 def CMP16rm : I<0x3B, MRMSrcMem,
                 (ops R16:$src1, i16mem:$src2),
-                "cmp{w} {$src2, $src1|$src1, $src2}">, OpSize;
+                "cmp{w} {$src2, $src1|$src1, $src2}", []>, OpSize;
 def CMP32rm : I<0x3B, MRMSrcMem,
                 (ops R32:$src1, i32mem:$src2),
-                "cmp{l} {$src2, $src1|$src1, $src2}">;
+                "cmp{l} {$src2, $src1|$src1, $src2}", []>;
 def CMP8ri  : Ii8<0x80, MRM7r,
                   (ops R16:$src1, i8imm:$src2),
                   "cmp{b} {$src2, $src1|$src1, $src2}", []>;
@@ -1445,171 +1479,193 @@
 
 // Sign/Zero extenders
 def MOVSX16rr8 : I<0xBE, MRMSrcReg, (ops R16:$dst, R8 :$src),
-                   "movs{bw|x} {$src, $dst|$dst, $src}">, TB, OpSize;
+                   "movs{bw|x} {$src, $dst|$dst, $src}",
+                   [(set R16:$dst, (sext R8:$src))]>, TB, OpSize;
 def MOVSX16rm8 : I<0xBE, MRMSrcMem, (ops R16:$dst, i8mem :$src),
-                   "movs{bw|x} {$src, $dst|$dst, $src}">, TB, OpSize;
+                   "movs{bw|x} {$src, $dst|$dst, $src}", []>, TB, OpSize;
 def MOVSX32rr8 : I<0xBE, MRMSrcReg, (ops R32:$dst, R8 :$src),
-                   "movs{bl|x} {$src, $dst|$dst, $src}">, TB;
+                   "movs{bl|x} {$src, $dst|$dst, $src}",
+                   [(set R32:$dst, (sext R8:$src))]>, TB;
 def MOVSX32rm8 : I<0xBE, MRMSrcMem, (ops R32:$dst, i8mem :$src),
-                   "movs{bl|x} {$src, $dst|$dst, $src}">, TB;
+                   "movs{bl|x} {$src, $dst|$dst, $src}", []>, TB;
 def MOVSX32rr16: I<0xBF, MRMSrcReg, (ops R32:$dst, R16:$src),
-                   "movs{wl|x} {$src, $dst|$dst, $src}">, TB;
+                   "movs{wl|x} {$src, $dst|$dst, $src}",
+                   [(set R32:$dst, (sext R16:$src))]>, TB;
 def MOVSX32rm16: I<0xBF, MRMSrcMem, (ops R32:$dst, i16mem:$src),
-                   "movs{wl|x} {$src, $dst|$dst, $src}">, TB;
+                   "movs{wl|x} {$src, $dst|$dst, $src}", []>, TB;
 
 def MOVZX16rr8 : I<0xB6, MRMSrcReg, (ops R16:$dst, R8 :$src),
-                   "movz{bw|x} {$src, $dst|$dst, $src}">, TB, OpSize;
+                   "movz{bw|x} {$src, $dst|$dst, $src}",
+                   [(set R16:$dst, (zext R8:$src))]>, TB, OpSize;
 def MOVZX16rm8 : I<0xB6, MRMSrcMem, (ops R16:$dst, i8mem :$src),
-                   "movz{bw|x} {$src, $dst|$dst, $src}">, TB, OpSize;
+                   "movz{bw|x} {$src, $dst|$dst, $src}", []>, TB, OpSize;
 def MOVZX32rr8 : I<0xB6, MRMSrcReg, (ops R32:$dst, R8 :$src),
-                   "movz{bl|x} {$src, $dst|$dst, $src}">, TB;
+                   "movz{bl|x} {$src, $dst|$dst, $src}",
+                   [(set R32:$dst, (zext R8:$src))]>, TB;
 def MOVZX32rm8 : I<0xB6, MRMSrcMem, (ops R32:$dst, i8mem :$src),
-                   "movz{bl|x} {$src, $dst|$dst, $src}">, TB;
+                   "movz{bl|x} {$src, $dst|$dst, $src}", []>, TB;
 def MOVZX32rr16: I<0xB7, MRMSrcReg, (ops R32:$dst, R16:$src),
-                   "movz{wl|x} {$src, $dst|$dst, $src}">, TB;
+                   "movz{wl|x} {$src, $dst|$dst, $src}",
+                   [(set R32:$dst, (zext R16:$src))]>, TB;
 def MOVZX32rm16: I<0xB7, MRMSrcMem, (ops R32:$dst, i16mem:$src),
-                   "movz{wl|x} {$src, $dst|$dst, $src}">, TB;
+                   "movz{wl|x} {$src, $dst|$dst, $src}", []>, TB;
 
 //===----------------------------------------------------------------------===//
 // XMM Floating point support (requires SSE2)
 //===----------------------------------------------------------------------===//
 
 def MOVSSrr : I<0x10, MRMSrcReg, (ops V4F4:$dst, V4F4:$src),
-                "movss {$src, $dst|$dst, $src}">, XS;
+                "movss {$src, $dst|$dst, $src}", []>, XS;
 def MOVSSrm : I<0x10, MRMSrcMem, (ops V4F4:$dst, f32mem:$src),
-                "movss {$src, $dst|$dst, $src}">, XS;
+                "movss {$src, $dst|$dst, $src}", []>, XS;
 def MOVSSmr : I<0x11, MRMDestMem, (ops f32mem:$dst, V4F4:$src),
-                "movss {$src, $dst|$dst, $src}">, XS;
+                "movss {$src, $dst|$dst, $src}", []>, XS;
 def MOVSDrr : I<0x10, MRMSrcReg, (ops V2F8:$dst, V2F8:$src),
-                "movsd {$src, $dst|$dst, $src}">, XD;
+                "movsd {$src, $dst|$dst, $src}", []>, XD;
 def MOVSDrm : I<0x10, MRMSrcMem, (ops V2F8:$dst, f64mem:$src),
-                "movsd {$src, $dst|$dst, $src}">, XD;
+                "movsd {$src, $dst|$dst, $src}", []>, XD;
 def MOVSDmr : I<0x11, MRMDestMem, (ops f64mem:$dst, V2F8:$src),
-                "movsd {$src, $dst|$dst, $src}">, XD;
+                "movsd {$src, $dst|$dst, $src}", []>, XD;
 
 def CVTTSD2SIrr: I<0x2C, MRMSrcReg, (ops R32:$dst, V2F8:$src),
-                "cvttsd2si {$src, $dst|$dst, $src}">, XD;
+                "cvttsd2si {$src, $dst|$dst, $src}",
+                [(set R32:$dst, (fp_to_sint V2F8:$src))]>, XD;
 def CVTTSD2SIrm: I<0x2C, MRMSrcMem, (ops R32:$dst, f64mem:$src),
-                "cvttsd2si {$src, $dst|$dst, $src}">, XD;
+                "cvttsd2si {$src, $dst|$dst, $src}", []>, XD;
 def CVTTSS2SIrr: I<0x2C, MRMSrcReg, (ops R32:$dst, V4F4:$src),
-                "cvttss2si {$src, $dst|$dst, $src}">, XS;
+                "cvttss2si {$src, $dst|$dst, $src}",
+                [(set R32:$dst, (fp_to_sint V4F4:$src))]>, XS;
 def CVTTSS2SIrm: I<0x2C, MRMSrcMem, (ops R32:$dst, f32mem:$src),
-                "cvttss2si {$src, $dst|$dst, $src}">, XS;
+                "cvttss2si {$src, $dst|$dst, $src}", []>, XS;
 def CVTSD2SSrr: I<0x5A, MRMSrcReg, (ops V4F4:$dst, V2F8:$src),
-                "cvtsd2ss {$src, $dst|$dst, $src}">, XS;
+                "cvtsd2ss {$src, $dst|$dst, $src}",
+                [(set V4F4:$dst, (fround V2F8:$src))]>, XS;
 def CVTSD2SSrm: I<0x5A, MRMSrcMem, (ops V4F4:$dst, f64mem:$src), 
-                "cvtsd2ss {$src, $dst|$dst, $src}">, XS;
+                "cvtsd2ss {$src, $dst|$dst, $src}", []>, XS;
 def CVTSS2SDrr: I<0x5A, MRMSrcReg, (ops V2F8:$dst, V4F4:$src),
-                "cvtss2sd {$src, $dst|$dst, $src}">, XD;
+                "cvtss2sd {$src, $dst|$dst, $src}",
+                [(set V2F8:$dst, (fextend V4F4:$src))]>, XD;
 def CVTSS2SDrm: I<0x5A, MRMSrcMem, (ops V2F8:$dst, f32mem:$src),
-                "cvtss2sd {$src, $dst|$dst, $src}">, XD;
+                "cvtss2sd {$src, $dst|$dst, $src}", []>, XD;
 def CVTSI2SSrr: I<0x2A, MRMSrcReg, (ops V4F4:$dst, R32:$src),
-                "cvtsi2ss {$src, $dst|$dst, $src}">, XS;
+                "cvtsi2ss {$src, $dst|$dst, $src}",
+                [(set V4F4:$dst, (sint_to_fp R32:$src))]>, XS;
 def CVTSI2SSrm: I<0x2A, MRMSrcMem, (ops V4F4:$dst, i32mem:$src),
-                "cvtsi2ss {$src, $dst|$dst, $src}">, XS;
+                "cvtsi2ss {$src, $dst|$dst, $src}", []>, XS;
 def CVTSI2SDrr: I<0x2A, MRMSrcReg, (ops V2F8:$dst, R32:$src),
-                "cvtsi2sd {$src, $dst|$dst, $src}">, XD;
+                "cvtsi2sd {$src, $dst|$dst, $src}",
+                [(set V2F8:$dst, (sint_to_fp R32:$src))]>, XD;
 def CVTSI2SDrm: I<0x2A, MRMSrcMem, (ops V2F8:$dst, i32mem:$src),
-                "cvtsi2sd {$src, $dst|$dst, $src}">, XD;
+                "cvtsi2sd {$src, $dst|$dst, $src}", []>, XD;
 
 def SQRTSSrm : I<0x51, MRMSrcMem, (ops V4F4:$dst, f32mem:$src),
-                "subss {$src, $dst|$dst, $src}">, XS;
+                "sqrtss {$src, $dst|$dst, $src}", []>, XS;
 def SQRTSSrr : I<0x51, MRMSrcReg, (ops V4F4:$dst, V4F4:$src),
-                "subss {$src, $dst|$dst, $src}">, XS;
+                "sqrtss {$src, $dst|$dst, $src}",
+                [(set V4F4:$dst, (fsqrt V4F4:$src))]>, XS;
 def SQRTSDrm : I<0x51, MRMSrcMem, (ops V2F8:$dst, f64mem:$src),
-                "subsd {$src, $dst|$dst, $src}">, XD;
+                "sqrtsd {$src, $dst|$dst, $src}", []>, XD;
 def SQRTSDrr : I<0x51, MRMSrcReg, (ops V2F8:$dst, V2F8:$src),
-                "subsd {$src, $dst|$dst, $src}">, XD;
+                "sqrtsd {$src, $dst|$dst, $src}",
+                [(set V2F8:$dst, (fsqrt V2F8:$src))]>, XD;
 
 def UCOMISDrr: I<0x2E, MRMSrcReg, (ops V2F8:$dst, V2F8:$src),
-                "ucomisd {$src, $dst|$dst, $src}">, TB, OpSize;
+                "ucomisd {$src, $dst|$dst, $src}", []>, TB, OpSize;
 def UCOMISDrm: I<0x2E, MRMSrcMem, (ops V2F8:$dst, f64mem:$src),
-                "ucomisd {$src, $dst|$dst, $src}">, TB, OpSize;
+                "ucomisd {$src, $dst|$dst, $src}", []>, TB, OpSize;
 def UCOMISSrr: I<0x2E, MRMSrcReg, (ops V4F4:$dst, V4F4:$src),
-                "ucomiss {$src, $dst|$dst, $src}">, TB;
+                "ucomiss {$src, $dst|$dst, $src}", []>, TB;
 def UCOMISSrm: I<0x2E, MRMSrcMem, (ops V4F4:$dst, f32mem:$src),
-                "ucomiss {$src, $dst|$dst, $src}">, TB;
+                "ucomiss {$src, $dst|$dst, $src}", []>, TB;
 
-// Pseudo-instructions that map to fld0 to xorps/xorpd for sse.
+// Pseudo-instructions that map fld0 to xorps/xorpd for sse.
 // FIXME: remove when we can teach regalloc that xor reg, reg is ok.
 def FLD0SS : I<0x57, MRMSrcReg, (ops V4F4:$dst),
-                "xorps $dst, $dst">, TB;
+                "xorps $dst, $dst", []>, TB;
 def FLD0SD : I<0x57, MRMSrcReg, (ops V2F8:$dst),
-                "xorpd $dst, $dst">, TB, OpSize;
+                "xorpd $dst, $dst", []>, TB, OpSize;
 
 let isTwoAddress = 1 in {
 let isCommutable = 1 in {
-def ADDSSrr : I<0x58, MRMSrcReg, (ops V4F4:$dst, V4F4:$src1, V4F4:$src),
-                "addss {$src, $dst|$dst, $src}">, XS;
-def ADDSDrr : I<0x58, MRMSrcReg, (ops V2F8:$dst, V2F8:$src1, V2F8:$src),
-                "addsd {$src, $dst|$dst, $src}">, XD;
-def ANDPSrr : I<0x54, MRMSrcReg, (ops V4F4:$dst, V4F4:$src1, V4F4:$src),
-                "andps {$src, $dst|$dst, $src}">, TB;
-def ANDPDrr : I<0x54, MRMSrcReg, (ops V2F8:$dst, V2F8:$src1, V2F8:$src),
-                "andpd {$src, $dst|$dst, $src}">, TB, OpSize;
-def MULSSrr : I<0x59, MRMSrcReg, (ops V4F4:$dst, V4F4:$src1, V4F4:$src),
-                "mulss {$src, $dst|$dst, $src}">, XS;
-def MULSDrr : I<0x59, MRMSrcReg, (ops V2F8:$dst, V2F8:$src1, V2F8:$src),
-                "mulsd {$src, $dst|$dst, $src}">, XD;
-def ORPSrr : I<0x56, MRMSrcReg, (ops V4F4:$dst, V4F4:$src1, V4F4:$src),
-                "orps {$src, $dst|$dst, $src}">, TB;
-def ORPDrr : I<0x56, MRMSrcReg, (ops V2F8:$dst, V2F8:$src1, V2F8:$src),
-                "orpd {$src, $dst|$dst, $src}">, TB, OpSize;
-def XORPSrr : I<0x57, MRMSrcReg, (ops V4F4:$dst, V4F4:$src1, V4F4:$src),
-                "xorps {$src, $dst|$dst, $src}">, TB;
-def XORPDrr : I<0x57, MRMSrcReg, (ops V2F8:$dst, V2F8:$src1, V2F8:$src),
-                "xorpd {$src, $dst|$dst, $src}">, TB, OpSize;
-}
-def ANDNPSrr : I<0x55, MRMSrcReg, (ops V4F4:$dst, V4F4:$src1, V4F4:$src),
-                "andnps {$src, $dst|$dst, $src}">, TB;
-def ANDNPDrr : I<0x55, MRMSrcReg, (ops V2F8:$dst, V2F8:$src1, V2F8:$src),
-                "andnpd {$src, $dst|$dst, $src}">, TB, OpSize;
-def ADDSSrm : I<0x58, MRMSrcMem, (ops V4F4:$dst, V4F4:$src1, f32mem:$src),
-                "addss {$src, $dst|$dst, $src}">, XS;
-def ADDSDrm : I<0x58, MRMSrcMem, (ops V2F8:$dst, V2F8:$src1, f64mem:$src),
-                "addsd {$src, $dst|$dst, $src}">, XD;
-def MULSSrm : I<0x59, MRMSrcMem, (ops V4F4:$dst, V4F4:$src1, f32mem:$src),
-                "mulss {$src, $dst|$dst, $src}">, XS;
-def MULSDrm : I<0x59, MRMSrcMem, (ops V2F8:$dst, V2F8:$src1, f64mem:$src),
-                "mulsd {$src, $dst|$dst, $src}">, XD;
-
-def DIVSSrm : I<0x5E, MRMSrcMem, (ops V4F4:$dst, V4F4:$src1, f32mem:$src),
-                "divss {$src, $dst|$dst, $src}">, XS;
-def DIVSSrr : I<0x5E, MRMSrcReg, (ops V4F4:$dst, V4F4:$src1, V4F4:$src),
-                "divss {$src, $dst|$dst, $src}">, XS;
-def DIVSDrm : I<0x5E, MRMSrcMem, (ops V2F8:$dst, V2F8:$src1, f64mem:$src),
-                "divsd {$src, $dst|$dst, $src}">, XD;
-def DIVSDrr : I<0x5E, MRMSrcReg, (ops V2F8:$dst, V2F8:$src1, V2F8:$src),
-                "divsd {$src, $dst|$dst, $src}">, XD;
-
-def SUBSSrm : I<0x5C, MRMSrcMem, (ops V4F4:$dst, V4F4:$src1, f32mem:$src),
-                "subss {$src, $dst|$dst, $src}">, XS;
-def SUBSSrr : I<0x5C, MRMSrcReg, (ops V4F4:$dst, V4F4:$src1, V4F4:$src),
-                "subss {$src, $dst|$dst, $src}">, XS;
-def SUBSDrm : I<0x5C, MRMSrcMem, (ops V2F8:$dst, V2F8:$src1, f64mem:$src),
-                "subsd {$src, $dst|$dst, $src}">, XD;
-def SUBSDrr : I<0x5C, MRMSrcReg, (ops V2F8:$dst, V2F8:$src1, V2F8:$src),
-                "subsd {$src, $dst|$dst, $src}">, XD;
+def ADDSSrr : I<0x58, MRMSrcReg, (ops V4F4:$dst, V4F4:$src1, V4F4:$src2),
+                "addss {$src2, $dst|$dst, $src2}",
+                [(set V4F4:$dst, (fadd V4F4:$src1, V4F4:$src2))]>, XS;
+def ADDSDrr : I<0x58, MRMSrcReg, (ops V2F8:$dst, V2F8:$src1, V2F8:$src2),
+                "addsd {$src2, $dst|$dst, $src2}",
+                [(set V2F8:$dst, (fadd V2F8:$src1, V2F8:$src2))]>, XD;
+def ANDPSrr : I<0x54, MRMSrcReg, (ops V4F4:$dst, V4F4:$src1, V4F4:$src2),
+                "andps {$src2, $dst|$dst, $src2}", []>, TB;
+def ANDPDrr : I<0x54, MRMSrcReg, (ops V2F8:$dst, V2F8:$src1, V2F8:$src2),
+                "andpd {$src2, $dst|$dst, $src2}", []>, TB, OpSize;
+def MULSSrr : I<0x59, MRMSrcReg, (ops V4F4:$dst, V4F4:$src1, V4F4:$src2),
+                "mulss {$src2, $dst|$dst, $src2}",
+                [(set V4F4:$dst, (fmul V4F4:$src1, V4F4:$src2))]>, XS;
+def MULSDrr : I<0x59, MRMSrcReg, (ops V2F8:$dst, V2F8:$src1, V2F8:$src2),
+                "mulsd {$src2, $dst|$dst, $src2}",
+                [(set V2F8:$dst, (fmul V2F8:$src1, V2F8:$src2))]>, XD;
+def ORPSrr : I<0x56, MRMSrcReg, (ops V4F4:$dst, V4F4:$src1, V4F4:$src2),
+                "orps {$src2, $dst|$dst, $src2}", []>, TB;
+def ORPDrr : I<0x56, MRMSrcReg, (ops V2F8:$dst, V2F8:$src1, V2F8:$src2),
+                "orpd {$src2, $dst|$dst, $src2}", []>, TB, OpSize;
+def XORPSrr : I<0x57, MRMSrcReg, (ops V4F4:$dst, V4F4:$src1, V4F4:$src2),
+                "xorps {$src2, $dst|$dst, $src2}", []>, TB;
+def XORPDrr : I<0x57, MRMSrcReg, (ops V2F8:$dst, V2F8:$src1, V2F8:$src2),
+                "xorpd {$src2, $dst|$dst, $src2}", []>, TB, OpSize;
+}
+def ANDNPSrr : I<0x55, MRMSrcReg, (ops V4F4:$dst, V4F4:$src1, V4F4:$src2),
+                "andnps {$src2, $dst|$dst, $src2}", []>, TB;
+def ANDNPDrr : I<0x55, MRMSrcReg, (ops V2F8:$dst, V2F8:$src1, V2F8:$src2),
+                "andnpd {$src2, $dst|$dst, $src2}", []>, TB, OpSize;
+def ADDSSrm : I<0x58, MRMSrcMem, (ops V4F4:$dst, V4F4:$src1, f32mem:$src2),
+                "addss {$src2, $dst|$dst, $src2}", []>, XS;
+def ADDSDrm : I<0x58, MRMSrcMem, (ops V2F8:$dst, V2F8:$src1, f64mem:$src2),
+                "addsd {$src2, $dst|$dst, $src2}", []>, XD;
+def MULSSrm : I<0x59, MRMSrcMem, (ops V4F4:$dst, V4F4:$src1, f32mem:$src2),
+                "mulss {$src2, $dst|$dst, $src2}", []>, XS;
+def MULSDrm : I<0x59, MRMSrcMem, (ops V2F8:$dst, V2F8:$src1, f64mem:$src2),
+                "mulsd {$src2, $dst|$dst, $src2}", []>, XD;
+
+def DIVSSrm : I<0x5E, MRMSrcMem, (ops V4F4:$dst, V4F4:$src1, f32mem:$src2),
+                "divss {$src2, $dst|$dst, $src2}", []>, XS;
+def DIVSSrr : I<0x5E, MRMSrcReg, (ops V4F4:$dst, V4F4:$src1, V4F4:$src2),
+                "divss {$src2, $dst|$dst, $src2}",
+                [(set V4F4:$dst, (fdiv V4F4:$src1, V4F4:$src2))]>, XS;
+def DIVSDrm : I<0x5E, MRMSrcMem, (ops V2F8:$dst, V2F8:$src1, f64mem:$src2),
+                "divsd {$src2, $dst|$dst, $src2}", []>, XD;
+def DIVSDrr : I<0x5E, MRMSrcReg, (ops V2F8:$dst, V2F8:$src1, V2F8:$src2),
+                "divsd {$src2, $dst|$dst, $src2}",
+                [(set V2F8:$dst, (fdiv V2F8:$src1, V2F8:$src2))]>, XD;
+
+def SUBSSrm : I<0x5C, MRMSrcMem, (ops V4F4:$dst, V4F4:$src1, f32mem:$src2),
+                "subss {$src2, $dst|$dst, $src2}", []>, XS;
+def SUBSSrr : I<0x5C, MRMSrcReg, (ops V4F4:$dst, V4F4:$src1, V4F4:$src2),
+                "subss {$src2, $dst|$dst, $src2}",
+                [(set V4F4:$dst, (fsub V4F4:$src1, V4F4:$src2))]>, XS;
+def SUBSDrm : I<0x5C, MRMSrcMem, (ops V2F8:$dst, V2F8:$src1, f64mem:$src2),
+                "subsd {$src2, $dst|$dst, $src2}", []>, XD;
+def SUBSDrr : I<0x5C, MRMSrcReg, (ops V2F8:$dst, V2F8:$src1, V2F8:$src2),
+                "subsd {$src2, $dst|$dst, $src2}",
+                [(set V2F8:$dst, (fsub V2F8:$src1, V2F8:$src2))]>, XD;
 
 def CMPSSrr : I<0xC2, MRMSrcReg, 
                 (ops V4F4:$dst, V4F4:$src1, V4F4:$src, SSECC:$cc),
-                "cmp${cc}ss {$src, $dst|$dst, $src}">, XS;
+                "cmp${cc}ss {$src, $dst|$dst, $src}", []>, XS;
 def CMPSSrm : I<0xC2, MRMSrcMem, 
                 (ops V4F4:$dst, V4F4:$src1, f32mem:$src, SSECC:$cc),
-                "cmp${cc}ss {$src, $dst|$dst, $src}">, XS;
+                "cmp${cc}ss {$src, $dst|$dst, $src}", []>, XS;
 def CMPSDrr : I<0xC2, MRMSrcReg, 
                 (ops V2F8:$dst, V2F8:$src1, V2F8:$src, SSECC:$cc),
-                "cmp${cc}sd {$src, $dst|$dst, $src}">, XD;
+                "cmp${cc}sd {$src, $dst|$dst, $src}", []>, XD;
 def CMPSDrm : I<0xC2, MRMSrcMem, 
                 (ops V2F8:$dst, V2F8:$src1, f64mem:$src, SSECC:$cc),
-                "cmp${cc}sd {$src, $dst|$dst, $src}">, XD;
+                "cmp${cc}sd {$src, $dst|$dst, $src}", []>, XD;
 }
 
 //===----------------------------------------------------------------------===//
 // Miscellaneous Instructions
 //===----------------------------------------------------------------------===//
 
-def RDTSC : I<0x31, RawFrm, (ops), "rdtsc">, TB, Imp<[],[EAX,EDX]>;
+def RDTSC : I<0x31, RawFrm, (ops), "rdtsc", []>, TB, Imp<[],[EAX,EDX]>;
 
 
 //===----------------------------------------------------------------------===//
@@ -1849,16 +1905,16 @@
 
 // Binary arithmetic operations...
 class FPST0rInst<bits<8> o, dag ops, string asm>
-  : I<o, AddRegFrm, ops, asm>, D8 {
+  : I<o, AddRegFrm, ops, asm, []>, D8 {
   list<Register> Uses = [ST0];
   list<Register> Defs = [ST0];
 }
 class FPrST0Inst<bits<8> o, dag ops, string asm>
-  : I<o, AddRegFrm, ops, asm>, DC {
+  : I<o, AddRegFrm, ops, asm, []>, DC {
   list<Register> Uses = [ST0];
 }
 class FPrST0PInst<bits<8> o, dag ops, string asm>
-  : I<o, AddRegFrm, ops, asm>, DE {
+  : I<o, AddRegFrm, ops, asm, []>, DE {
   list<Register> Uses = [ST0];
 }
 
@@ -1913,24 +1969,24 @@
                     "fucom $reg">, DD, Imp<[ST0],[]>;
 def FUCOMPr   : I<0xE8, AddRegFrm,           // FPSW = cmp ST(0) with ST(i), pop
                   (ops RST:$reg, variable_ops),
-                  "fucomp $reg">, DD, Imp<[ST0],[]>;
+                  "fucomp $reg", []>, DD, Imp<[ST0],[]>;
 def FUCOMPPr  : I<0xE9, RawFrm,                // cmp ST(0) with ST(1), pop, pop
                   (ops variable_ops),
-                  "fucompp">, DA, Imp<[ST0],[]>;
+                  "fucompp", []>, DA, Imp<[ST0],[]>;
 
 def FUCOMIr  : FPI<0xE8, AddRegFrm, CompareFP,  // CC = cmp ST(0) with ST(i)
                    (ops RST:$reg, variable_ops),
                    "fucomi {$reg, %ST(0)|%ST(0), $reg}">, DB, Imp<[ST0],[]>;
 def FUCOMIPr : I<0xE8, AddRegFrm,              // CC = cmp ST(0) with ST(i), pop
                  (ops RST:$reg, variable_ops),
-                 "fucomip {$reg, %ST(0)|%ST(0), $reg}">, DF, Imp<[ST0],[]>;
+                 "fucomip {$reg, %ST(0)|%ST(0), $reg}", []>, DF, Imp<[ST0],[]>;
 
 
 // Floating point flag ops
 def FNSTSW8r  : I<0xE0, RawFrm,                  // AX = fp flags
-                  (ops), "fnstsw">, DF, Imp<[],[AX]>;
+                  (ops), "fnstsw", []>, DF, Imp<[],[AX]>;
 
 def FNSTCW16m : I<0xD9, MRM7m,                   // [mem16] = X87 control world
-                  (ops i16mem:$dst), "fnstcw $dst">;
+                  (ops i16mem:$dst), "fnstcw $dst", []>;
 def FLDCW16m  : I<0xD9, MRM5m,                   // X87 control world = [mem16]
-                  (ops i16mem:$dst), "fldcw $dst">;
+                  (ops i16mem:$dst), "fldcw $dst", []>;





From natebegeman at mac.com  Tue Nov 29 16:43:02 2005
From: natebegeman at mac.com (Nate Begeman)
Date: Tue, 29 Nov 2005 16:43:02 -0600
Subject: [llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCInstrFormats.td
	PPCInstrInfo.td 
Message-ID: <200511292243.QAA19611@zion.cs.uiuc.edu>



Changes in directory llvm/lib/Target/PowerPC:

PPCInstrFormats.td updated: 1.58 -> 1.59
PPCInstrInfo.td updated: 1.146 -> 1.147
---
Log message:

Represent the encoding of the SPR instructions as they actually are, so
that we can use the correct SPR numbers in the InstrInfo.td file.  This is
necessary to support VRsave.


---
Diffs of the changes:  (+18 -8)

 PPCInstrFormats.td |   12 ++++++++++--
 PPCInstrInfo.td    |   14 ++++++++------
 2 files changed, 18 insertions(+), 8 deletions(-)


Index: llvm/lib/Target/PowerPC/PPCInstrFormats.td
diff -u llvm/lib/Target/PowerPC/PPCInstrFormats.td:1.58 llvm/lib/Target/PowerPC/PPCInstrFormats.td:1.59
--- llvm/lib/Target/PowerPC/PPCInstrFormats.td:1.58	Tue Nov 29 02:04:45 2005
+++ llvm/lib/Target/PowerPC/PPCInstrFormats.td	Tue Nov 29 16:42:50 2005
@@ -361,7 +361,16 @@
   bits<10> SPR;
 
   let Inst{6-10}  = RT;
-  let Inst{11-20} = SPR;
+  let Inst{11}    = SPR{4};
+  let Inst{12}    = SPR{3};
+  let Inst{13}    = SPR{2};
+  let Inst{14}    = SPR{1};
+  let Inst{15}    = SPR{0};
+  let Inst{16}    = SPR{9};
+  let Inst{17}    = SPR{8};
+  let Inst{18}    = SPR{7};
+  let Inst{19}    = SPR{6};
+  let Inst{20}    = SPR{5};
   let Inst{21-30} = xo;
   let Inst{31}    = 0;
 }
@@ -411,7 +420,6 @@
   let Inst{31}    = 0;
 }
 
-
 class XFXForm_7<bits<6> opcode, bits<10> xo, dag OL, string asmstr,
                 InstrItinClass itin>
   : XFXForm_1<opcode, xo, OL, asmstr, itin>;


Index: llvm/lib/Target/PowerPC/PPCInstrInfo.td
diff -u llvm/lib/Target/PowerPC/PPCInstrInfo.td:1.146 llvm/lib/Target/PowerPC/PPCInstrInfo.td:1.147
--- llvm/lib/Target/PowerPC/PPCInstrInfo.td:1.146	Tue Nov 29 02:04:45 2005
+++ llvm/lib/Target/PowerPC/PPCInstrInfo.td	Tue Nov 29 16:42:50 2005
@@ -560,15 +560,17 @@
 // Note that although LR should be listed as `8' and CTR as `9' in the SPR
 // field, the manual lists the groups of bits as [5-9] = 0, [0-4] = 8 or 9
 // which means the SPR value needs to be multiplied by a factor of 32.
-def MFCTR : XFXForm_1_ext<31, 339, 288, (ops GPRC:$rT), "mfctr $rT", SprMFSPR>;
-def MFLR  : XFXForm_1_ext<31, 339, 256, (ops GPRC:$rT), "mflr $rT", SprMFSPR>;
+def MFCTR : XFXForm_1_ext<31, 339, 9, (ops GPRC:$rT), "mfctr $rT", SprMFSPR>;
+def MFLR  : XFXForm_1_ext<31, 339, 8, (ops GPRC:$rT), "mflr $rT",  SprMFSPR>;
 def MFCR  : XFXForm_3<31, 19, (ops GPRC:$rT), "mfcr $rT", SprMFCR>;
 def MTCRF : XFXForm_5<31, 144, (ops crbitm:$FXM, GPRC:$rS),
                       "mtcrf $FXM, $rS", BrMCRX>;
-def MFOCRF : XFXForm_5a<31, 19, (ops GPRC:$rT, crbitm:$FXM),
-                        "mfcr $rT, $FXM", SprMFCR>;
-def MTCTR : XFXForm_7_ext<31, 467, 288, (ops GPRC:$rS), "mtctr $rS", SprMTSPR>;
-def MTLR  : XFXForm_7_ext<31, 467, 256, (ops GPRC:$rS), "mtlr $rS", SprMTSPR>;
+def MFOCRF: XFXForm_5a<31, 19, (ops GPRC:$rT, crbitm:$FXM),
+                       "mfcr $rT, $FXM", SprMFCR>;
+def MTCTR : XFXForm_7_ext<31, 467, 9, (ops GPRC:$rS), "mtctr $rS", SprMTSPR>;
+def MTLR  : XFXForm_7_ext<31, 467, 8, (ops GPRC:$rS), "mtlr $rS", SprMTSPR>;
+def MTSPR : XFXForm_7<31, 467, (ops GPRC:$rS, u16imm:$UIMM), "mtspr $UIMM, $rS",
+                      SprMTSPR>;
 
 // XS-Form instructions.  Just 'sradi'
 //





From evan.cheng at apple.com  Tue Nov 29 19:59:11 2005
From: evan.cheng at apple.com (Evan Cheng)
Date: Tue, 29 Nov 2005 19:59:11 -0600
Subject: [llvm-commits] CVS: llvm/lib/Target/X86/X86IntelAsmPrinter.cpp 
Message-ID: <200511300159.TAA21809@zion.cs.uiuc.edu>



Changes in directory llvm/lib/Target/X86:

X86IntelAsmPrinter.cpp updated: 1.11 -> 1.12
---
Log message:

Fixed a minor bug: - -offset != offset iff offset == MININT


---
Diffs of the changes:  (+1 -1)

 X86IntelAsmPrinter.cpp |    2 +-
 1 files changed, 1 insertion(+), 1 deletion(-)


Index: llvm/lib/Target/X86/X86IntelAsmPrinter.cpp
diff -u llvm/lib/Target/X86/X86IntelAsmPrinter.cpp:1.11 llvm/lib/Target/X86/X86IntelAsmPrinter.cpp:1.12
--- llvm/lib/Target/X86/X86IntelAsmPrinter.cpp:1.11	Mon Nov 21 17:06:54 2005
+++ llvm/lib/Target/X86/X86IntelAsmPrinter.cpp	Tue Nov 29 19:59:00 2005
@@ -117,7 +117,7 @@
     if (Offset > 0)
       O << " + " << Offset;
     else if (Offset < 0)
-      O << " - " << -Offset;
+      O << Offset;
     return;
   }
   case MachineOperand::MO_ExternalSymbol:





From evan.cheng at apple.com  Tue Nov 29 20:04:24 2005
From: evan.cheng at apple.com (Evan Cheng)
Date: Tue, 29 Nov 2005 20:04:24 -0600
Subject: [llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp
	SelectionDAG.cpp SelectionDAGPrinter.cpp 
Message-ID: <200511300204.UAA21884@zion.cs.uiuc.edu>



Changes in directory llvm/lib/CodeGen/SelectionDAG:

ScheduleDAG.cpp updated: 1.45 -> 1.46
SelectionDAG.cpp updated: 1.216 -> 1.217
SelectionDAGPrinter.cpp updated: 1.29 -> 1.30
---
Log message:

Added an index field to GlobalAddressSDNode so it can represent X+12, etc.


---
Diffs of the changes:  (+23 -3)

 ScheduleDAG.cpp         |    2 +-
 SelectionDAG.cpp        |   19 +++++++++++++++++--
 SelectionDAGPrinter.cpp |    5 +++++
 3 files changed, 23 insertions(+), 3 deletions(-)


Index: llvm/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp:1.45 llvm/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp:1.46
--- llvm/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp:1.45	Wed Nov  9 17:47:37 2005
+++ llvm/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp	Tue Nov 29 20:04:11 2005
@@ -1123,7 +1123,7 @@
         MI->addRegOperand(R->getReg(), MachineOperand::Use);
       } else if (GlobalAddressSDNode *TGA =
                        dyn_cast<GlobalAddressSDNode>(Node->getOperand(i))) {
-        MI->addGlobalAddressOperand(TGA->getGlobal(), false, 0);
+        MI->addGlobalAddressOperand(TGA->getGlobal(), false, TGA->getOffset());
       } else if (BasicBlockSDNode *BB =
                        dyn_cast<BasicBlockSDNode>(Node->getOperand(i))) {
         MI->addMachineBasicBlockOperand(BB->getBasicBlock());


Index: llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp:1.216 llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp:1.217
--- llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp:1.216	Tue Nov 29 00:21:05 2005
+++ llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp	Tue Nov 29 20:04:11 2005
@@ -500,10 +500,10 @@
 }
 
 SDOperand SelectionDAG::getTargetGlobalAddress(const GlobalValue *GV,
-                                               MVT::ValueType VT) {
+                                               MVT::ValueType VT, int offset) {
   SDNode *&N = TargetGlobalValues[GV];
   if (N) return SDOperand(N, 0);
-  N = new GlobalAddressSDNode(true, GV, VT);
+  N = new GlobalAddressSDNode(true, GV, VT, offset);
   AllNodes.push_back(N);
   return SDOperand(N, 0);
 }
@@ -1457,6 +1457,16 @@
   N->setOperands(Op1, Op2, Op3, Op4, Op5);
 }
 
+void SelectionDAG::SelectNodeTo(SDNode *N, unsigned TargetOpc,
+                                MVT::ValueType VT, SDOperand Op1,
+                                SDOperand Op2, SDOperand Op3, SDOperand Op4,
+                                SDOperand Op5, SDOperand Op6) {
+  RemoveNodeFromCSEMaps(N);
+  N->MorphNodeTo(ISD::BUILTIN_OP_END+TargetOpc);
+  N->setValueTypes(VT);
+  N->setOperands(Op1, Op2, Op3, Op4, Op5, Op6);
+}
+
 void SelectionDAG::SelectNodeTo(SDNode *N, unsigned TargetOpc, 
                                 MVT::ValueType VT1, MVT::ValueType VT2,
                                 SDOperand Op1, SDOperand Op2) {
@@ -1859,8 +1869,13 @@
     std::cerr << "<" << CSDN->getValue() << ">";
   } else if (const GlobalAddressSDNode *GADN =
              dyn_cast<GlobalAddressSDNode>(this)) {
+    int offset = GADN->getOffset();
     std::cerr << "<";
     WriteAsOperand(std::cerr, GADN->getGlobal()) << ">";
+    if (offset > 0)
+      std::cerr << " + " << offset;
+    else
+      std::cerr << " " << offset;
   } else if (const FrameIndexSDNode *FIDN = dyn_cast<FrameIndexSDNode>(this)) {
     std::cerr << "<" << FIDN->getIndex() << ">";
   } else if (const ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(this)){


Index: llvm/lib/CodeGen/SelectionDAG/SelectionDAGPrinter.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/SelectionDAGPrinter.cpp:1.29 llvm/lib/CodeGen/SelectionDAG/SelectionDAGPrinter.cpp:1.30
--- llvm/lib/CodeGen/SelectionDAG/SelectionDAGPrinter.cpp:1.29	Tue Nov 29 00:21:05 2005
+++ llvm/lib/CodeGen/SelectionDAG/SelectionDAGPrinter.cpp	Tue Nov 29 20:04:11 2005
@@ -70,7 +70,12 @@
     Op += ": " + ftostr(CSDN->getValue());
   } else if (const GlobalAddressSDNode *GADN =
              dyn_cast<GlobalAddressSDNode>(Node)) {
+    int offset = GADN->getOffset();
     Op += ": " + GADN->getGlobal()->getName();
+    if (offset > 0)
+      Op += "+" + itostr(offset);
+    else
+      Op += itostr(offset);
   } else if (const FrameIndexSDNode *FIDN = dyn_cast<FrameIndexSDNode>(Node)) {
     Op += " " + itostr(FIDN->getIndex());
   } else if (const ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(Node)){





From evan.cheng at apple.com  Tue Nov 29 20:04:24 2005
From: evan.cheng at apple.com (Evan Cheng)
Date: Tue, 29 Nov 2005 20:04:24 -0600
Subject: [llvm-commits] CVS: llvm/include/llvm/CodeGen/SelectionDAG.h
	SelectionDAGNodes.h 
Message-ID: <200511300204.UAA21880@zion.cs.uiuc.edu>



Changes in directory llvm/include/llvm/CodeGen:

SelectionDAG.h updated: 1.71 -> 1.72
SelectionDAGNodes.h updated: 1.79 -> 1.80
---
Log message:

Added an index field to GlobalAddressSDNode so it can represent X+12, etc.


---
Diffs of the changes:  (+25 -2)

 SelectionDAG.h      |    6 +++++-
 SelectionDAGNodes.h |   21 ++++++++++++++++++++-
 2 files changed, 25 insertions(+), 2 deletions(-)


Index: llvm/include/llvm/CodeGen/SelectionDAG.h
diff -u llvm/include/llvm/CodeGen/SelectionDAG.h:1.71 llvm/include/llvm/CodeGen/SelectionDAG.h:1.72
--- llvm/include/llvm/CodeGen/SelectionDAG.h:1.71	Tue Nov 29 00:15:39 2005
+++ llvm/include/llvm/CodeGen/SelectionDAG.h	Tue Nov 29 20:04:11 2005
@@ -110,7 +110,8 @@
   SDOperand getTargetConstant(uint64_t Val, MVT::ValueType VT);
   SDOperand getConstantFP(double Val, MVT::ValueType VT);
   SDOperand getGlobalAddress(const GlobalValue *GV, MVT::ValueType VT);
-  SDOperand getTargetGlobalAddress(const GlobalValue *GV, MVT::ValueType VT);
+  SDOperand getTargetGlobalAddress(const GlobalValue *GV, MVT::ValueType VT,
+                                   int offset=0);
   SDOperand getFrameIndex(int FI, MVT::ValueType VT);
   SDOperand getTargetFrameIndex(int FI, MVT::ValueType VT);
   SDOperand getConstantPool(Constant *C, MVT::ValueType VT);
@@ -283,6 +284,9 @@
   void SelectNodeTo(SDNode *N, unsigned TargetOpc, MVT::ValueType VT, 
                     SDOperand Op1, SDOperand Op2, SDOperand Op3, SDOperand Op4,
                     SDOperand Op5);
+  void SelectNodeTo(SDNode *N, unsigned TargetOpc, MVT::ValueType VT, 
+                    SDOperand Op1, SDOperand Op2, SDOperand Op3, SDOperand Op4,
+                    SDOperand Op5, SDOperand Op6);
   void SelectNodeTo(SDNode *N, unsigned TargetOpc, MVT::ValueType VT1, 
                     MVT::ValueType VT2, SDOperand Op1, SDOperand Op2);
   void SelectNodeTo(SDNode *N, unsigned TargetOpc, MVT::ValueType VT1,


Index: llvm/include/llvm/CodeGen/SelectionDAGNodes.h
diff -u llvm/include/llvm/CodeGen/SelectionDAGNodes.h:1.79 llvm/include/llvm/CodeGen/SelectionDAGNodes.h:1.80
--- llvm/include/llvm/CodeGen/SelectionDAGNodes.h:1.79	Tue Nov 29 00:15:39 2005
+++ llvm/include/llvm/CodeGen/SelectionDAGNodes.h	Tue Nov 29 20:04:11 2005
@@ -795,6 +795,21 @@
     Op2.Val->Uses.push_back(this); Op3.Val->Uses.push_back(this);
     Op4.Val->Uses.push_back(this);
   }
+  void setOperands(SDOperand Op0, SDOperand Op1, SDOperand Op2, SDOperand Op3,
+                   SDOperand Op4, SDOperand Op5) {
+    assert(NumOperands == 0 && "Should not have operands yet!");
+    OperandList = new SDOperand[6];
+    OperandList[0] = Op0;
+    OperandList[1] = Op1;
+    OperandList[2] = Op2;
+    OperandList[3] = Op3;
+    OperandList[4] = Op4;
+    OperandList[5] = Op5;
+    NumOperands = 6;
+    Op0.Val->Uses.push_back(this); Op1.Val->Uses.push_back(this);
+    Op2.Val->Uses.push_back(this); Op3.Val->Uses.push_back(this);
+    Op4.Val->Uses.push_back(this); Op5.Val->Uses.push_back(this);
+  }
   void addUser(SDNode *User) {
     Uses.push_back(User);
   }
@@ -923,15 +938,19 @@
 
 class GlobalAddressSDNode : public SDNode {
   GlobalValue *TheGlobal;
+  int offset;
 protected:
   friend class SelectionDAG;
-  GlobalAddressSDNode(bool isTarget, const GlobalValue *GA, MVT::ValueType VT)
+  GlobalAddressSDNode(bool isTarget, const GlobalValue *GA, MVT::ValueType VT,
+                      int o=0)
     : SDNode(isTarget ? ISD::TargetGlobalAddress : ISD::GlobalAddress, VT) {
     TheGlobal = const_cast<GlobalValue*>(GA);
+    offset = o;
   }
 public:
 
   GlobalValue *getGlobal() const { return TheGlobal; }
+  int getOffset() const { return offset; }
 
   static bool classof(const GlobalAddressSDNode *) { return true; }
   static bool classof(const SDNode *N) {





From evan.cheng at apple.com  Tue Nov 29 20:49:33 2005
From: evan.cheng at apple.com (Evan Cheng)
Date: Tue, 29 Nov 2005 20:49:33 -0600
Subject: [llvm-commits] CVS: llvm/include/llvm/CodeGen/SelectionDAG.h 
Message-ID: <200511300249.UAA22037@zion.cs.uiuc.edu>



Changes in directory llvm/include/llvm/CodeGen:

SelectionDAG.h updated: 1.72 -> 1.73
---
Log message:

Fixed a bug introduced by my last commit: TargetGlobalValues should key on
GlobalValue * and index pair. Update getGlobalAddress() for symmetry.


---
Diffs of the changes:  (+5 -4)

 SelectionDAG.h |    9 +++++----
 1 files changed, 5 insertions(+), 4 deletions(-)


Index: llvm/include/llvm/CodeGen/SelectionDAG.h
diff -u llvm/include/llvm/CodeGen/SelectionDAG.h:1.72 llvm/include/llvm/CodeGen/SelectionDAG.h:1.73
--- llvm/include/llvm/CodeGen/SelectionDAG.h:1.72	Tue Nov 29 20:04:11 2005
+++ llvm/include/llvm/CodeGen/SelectionDAG.h	Tue Nov 29 20:49:21 2005
@@ -109,9 +109,10 @@
   SDOperand getConstant(uint64_t Val, MVT::ValueType VT);
   SDOperand getTargetConstant(uint64_t Val, MVT::ValueType VT);
   SDOperand getConstantFP(double Val, MVT::ValueType VT);
-  SDOperand getGlobalAddress(const GlobalValue *GV, MVT::ValueType VT);
+  SDOperand getGlobalAddress(const GlobalValue *GV, MVT::ValueType VT,
+                             int offset = 0);
   SDOperand getTargetGlobalAddress(const GlobalValue *GV, MVT::ValueType VT,
-                                   int offset=0);
+                                   int offset = 0);
   SDOperand getFrameIndex(int FI, MVT::ValueType VT);
   SDOperand getTargetFrameIndex(int FI, MVT::ValueType VT);
   SDOperand getConstantPool(Constant *C, MVT::ValueType VT);
@@ -399,8 +400,8 @@
   std::map<std::pair<SDOperand, std::pair<SDOperand, MVT::ValueType> >,
            SDNode *> Loads;
 
-  std::map<const GlobalValue*, SDNode*> GlobalValues;
-  std::map<const GlobalValue*, SDNode*> TargetGlobalValues;
+  std::map<std::pair<const GlobalValue*, int>, SDNode*> GlobalValues;
+  std::map<std::pair<const GlobalValue*, int>, SDNode*> TargetGlobalValues;
   std::map<std::pair<uint64_t, MVT::ValueType>, SDNode*> Constants;
   std::map<std::pair<uint64_t, MVT::ValueType>, SDNode*> TargetConstants;
   std::map<std::pair<uint64_t, MVT::ValueType>, SDNode*> ConstantFPs;





From evan.cheng at apple.com  Tue Nov 29 20:49:34 2005
From: evan.cheng at apple.com (Evan Cheng)
Date: Tue, 29 Nov 2005 20:49:34 -0600
Subject: [llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp 
Message-ID: <200511300249.UAA22041@zion.cs.uiuc.edu>



Changes in directory llvm/lib/CodeGen/SelectionDAG:

SelectionDAG.cpp updated: 1.217 -> 1.218
---
Log message:

Fixed a bug introduced by my last commit: TargetGlobalValues should key on
GlobalValue * and index pair. Update getGlobalAddress() for symmetry.


---
Diffs of the changes:  (+13 -7)

 SelectionDAG.cpp |   20 +++++++++++++-------
 1 files changed, 13 insertions(+), 7 deletions(-)


Index: llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp:1.217 llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp:1.218
--- llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp:1.217	Tue Nov 29 20:04:11 2005
+++ llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp	Tue Nov 29 20:49:21 2005
@@ -283,12 +283,18 @@
     Erased = CondCodeNodes[cast<CondCodeSDNode>(N)->get()] != 0;
     CondCodeNodes[cast<CondCodeSDNode>(N)->get()] = 0;
     break;
-  case ISD::GlobalAddress:
-    Erased = GlobalValues.erase(cast<GlobalAddressSDNode>(N)->getGlobal());
+  case ISD::GlobalAddress: {
+    GlobalAddressSDNode *GN = cast<GlobalAddressSDNode>(N);
+    Erased = GlobalValues.erase(std::make_pair(GN->getGlobal(),
+                                               GN->getOffset()));
     break;
-  case ISD::TargetGlobalAddress:
-    Erased =TargetGlobalValues.erase(cast<GlobalAddressSDNode>(N)->getGlobal());
+  }
+  case ISD::TargetGlobalAddress: {
+    GlobalAddressSDNode *GN = cast<GlobalAddressSDNode>(N);
+    Erased =TargetGlobalValues.erase(std::make_pair(GN->getGlobal(),
+                                                    GN->getOffset()));
     break;
+  }
   case ISD::FrameIndex:
     Erased = FrameIndices.erase(cast<FrameIndexSDNode>(N)->getIndex());
     break;
@@ -491,8 +497,8 @@
 
 
 SDOperand SelectionDAG::getGlobalAddress(const GlobalValue *GV,
-                                         MVT::ValueType VT) {
-  SDNode *&N = GlobalValues[GV];
+                                         MVT::ValueType VT, int offset) {
+  SDNode *&N = GlobalValues[std::make_pair(GV, offset)];
   if (N) return SDOperand(N, 0);
   N = new GlobalAddressSDNode(false, GV, VT);
   AllNodes.push_back(N);
@@ -501,7 +507,7 @@
 
 SDOperand SelectionDAG::getTargetGlobalAddress(const GlobalValue *GV,
                                                MVT::ValueType VT, int offset) {
-  SDNode *&N = TargetGlobalValues[GV];
+  SDNode *&N = TargetGlobalValues[std::make_pair(GV, offset)];
   if (N) return SDOperand(N, 0);
   N = new GlobalAddressSDNode(true, GV, VT, offset);
   AllNodes.push_back(N);





From evan.cheng at apple.com  Tue Nov 29 20:51:32 2005
From: evan.cheng at apple.com (Evan Cheng)
Date: Tue, 29 Nov 2005 20:51:32 -0600
Subject: [llvm-commits] CVS: llvm/lib/Target/X86/X86ISelDAGToDAG.cpp 
Message-ID: <200511300251.UAA22069@zion.cs.uiuc.edu>



Changes in directory llvm/lib/Target/X86:

X86ISelDAGToDAG.cpp updated: 1.3 -> 1.4
---
Log message:

Added support to STORE and shifts to DAG to DAG isel.


---
Diffs of the changes:  (+88 -8)

 X86ISelDAGToDAG.cpp |   96 +++++++++++++++++++++++++++++++++++++++++++++++-----
 1 files changed, 88 insertions(+), 8 deletions(-)


Index: llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
diff -u llvm/lib/Target/X86/X86ISelDAGToDAG.cpp:1.3 llvm/lib/Target/X86/X86ISelDAGToDAG.cpp:1.4
--- llvm/lib/Target/X86/X86ISelDAGToDAG.cpp:1.3	Fri Nov 18 20:11:08 2005
+++ llvm/lib/Target/X86/X86ISelDAGToDAG.cpp	Tue Nov 29 20:51:20 2005
@@ -49,7 +49,7 @@
     GlobalValue *GV;
 
     X86ISelAddressMode()
-      : BaseType(RegBase), Scale(1), IndexReg(), Disp(), GV(0) {
+      : BaseType(RegBase), Scale(1), IndexReg(), Disp(0), GV(0) {
     }
   };
 }
@@ -267,7 +267,7 @@
 
 SDOperand X86DAGToDAGISel::Select(SDOperand Op) {
   SDNode *N = Op.Val;
-  MVT::ValueType OpVT = Op.getValueType();
+  MVT::ValueType OpVT = N->getValueType(0);
   unsigned Opc;
 
   if (N->getOpcode() >= ISD::BUILTIN_OP_END)
@@ -275,9 +275,13 @@
   
   switch (N->getOpcode()) {
     default: break;
+
     case ISD::SHL:
+    case ISD::SRL:
+    case ISD::SRA:
       if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N->getOperand(1))) {
-        if (CN->getValue() == 1) {   // X = SHL Y, 1  -> X = ADD Y, Y
+        if (N->getOpcode() == ISD::SHL && CN->getValue() == 1) {
+          // X = SHL Y, 1  -> X = ADD Y, Y
           switch (OpVT) {
             default: assert(0 && "Cannot shift this type!");
             case MVT::i8:  Opc = X86::ADD8rr; break;
@@ -288,7 +292,37 @@
           CurDAG->SelectNodeTo(N, Opc, MVT::i32, Tmp0, Tmp0);
           return SDOperand(N, 0);
         }
+      } else {
+        static const unsigned SHLTab[] = {
+          X86::SHL8rCL, X86::SHL16rCL, X86::SHL32rCL
+        };
+        static const unsigned SRLTab[] = {
+          X86::SHR8rCL, X86::SHR16rCL, X86::SHR32rCL
+        };
+        static const unsigned SRATab[] = {
+          X86::SAR8rCL, X86::SAR16rCL, X86::SAR32rCL
+        };
+
+        switch (OpVT) {
+          default: assert(0 && "Cannot shift this type!");
+          case MVT::i1:
+          case MVT::i8:  Opc = 0; break;
+          case MVT::i16: Opc = 1; break;
+          case MVT::i32: Opc = 2; break;
+        }
+
+        switch (N->getOpcode()) {
+          default: assert(0 && "Unreachable!");
+          case ISD::SHL: Opc = SHLTab[Opc]; break;
+          case ISD::SRL: Opc = SRLTab[Opc]; break;
+          case ISD::SRA: Opc = SRATab[Opc]; break;
+        }
+
+        SDOperand Tmp0 = Select(N->getOperand(0));
+        CurDAG->SelectNodeTo(N, Opc, MVT::i32, Tmp0);
+        return SDOperand(N, 0);
       }
+      break;
 
     case ISD::RET: {
       SDOperand Chain = Select(N->getOperand(0));     // Token chain.
@@ -326,7 +360,7 @@
     }
 
     case ISD::LOAD: {
-      switch (N->getValueType(0)) {
+      switch (OpVT) {
         default: assert(0 && "Cannot load this type!");
         case MVT::i1:
         case MVT::i8:  Opc = X86::MOV8rm; break;
@@ -342,23 +376,69 @@
         // ???
         assert(0 && "Can't handle load from constant pool!");
       } else {
-        SDOperand Chain = Select(N->getOperand(0));     // Token chain.
         X86ISelAddressMode AM;
+        SDOperand Chain = Select(N->getOperand(0));     // Token chain.
+
         SelectAddress(N->getOperand(1), AM);
         SDOperand Scale = getI8Imm (AM.Scale);
-        SDOperand Disp  = AM.GV ? CurDAG->getTargetGlobalAddress(AM.GV, MVT::i32)
+        SDOperand Disp  = AM.GV
+          ? CurDAG->getTargetGlobalAddress(AM.GV, MVT::i32, AM.Disp)
           : getI32Imm(AM.Disp);
         if (AM.BaseType == X86ISelAddressMode::RegBase) {
-          CurDAG->SelectNodeTo(N, Opc, N->getValueType(0), MVT::Other,
+          CurDAG->SelectNodeTo(N, Opc, OpVT, MVT::Other,
                                AM.Base.Reg, Scale, AM.IndexReg, Disp, Chain);
         } else {
           SDOperand Base = CurDAG->getFrameIndex(AM.Base.FrameIndex, MVT::i32);
-          CurDAG->SelectNodeTo(N, Opc, N->getValueType(0), MVT::Other,
+          CurDAG->SelectNodeTo(N, Opc, OpVT, MVT::Other,
                                Base, Scale, AM.IndexReg, Disp, Chain);
         }
       }
       return SDOperand(N, Op.ResNo);
     }
+
+    case ISD::STORE: {
+      SDOperand Chain = Select(N->getOperand(0));     // Token chain.
+      SDOperand Tmp1 = Select(N->getOperand(1));
+      X86ISelAddressMode AM;
+      SelectAddress(N->getOperand(2), AM);
+
+      Opc = 0;
+      if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N->getOperand(1))) {
+        switch (CN->getValueType(0)) {
+          default: assert(0 && "Invalid type for operation!");
+          case MVT::i1:
+          case MVT::i8:  Opc = X86::MOV8mi;  break;
+          case MVT::i16: Opc = X86::MOV16mi; break;
+          case MVT::i32: Opc = X86::MOV32mi; break;
+        }
+      }
+
+      if (!Opc) {
+        switch (N->getOperand(1).getValueType()) {
+          default: assert(0 && "Cannot store this type!");
+          case MVT::i1:
+          case MVT::i8:  Opc = X86::MOV8mr;  break;
+          case MVT::i16: Opc = X86::MOV16mr; break;
+          case MVT::i32: Opc = X86::MOV32mr; break;
+          case MVT::f32: Opc = X86::MOVSSmr; break;
+          case MVT::f64: Opc = X86::FST64m;  break;
+        }
+      }
+
+      SDOperand Scale = getI8Imm (AM.Scale);
+      SDOperand Disp  = AM.GV
+        ? CurDAG->getTargetGlobalAddress(AM.GV, MVT::i32, AM.Disp)
+        : getI32Imm(AM.Disp);
+      if (AM.BaseType == X86ISelAddressMode::RegBase) {
+        CurDAG->SelectNodeTo(N, Opc, MVT::Other,
+                             AM.Base.Reg, Scale, AM.IndexReg, Disp, Tmp1,
+                             Chain);
+      } else {
+        SDOperand Base = CurDAG->getFrameIndex(AM.Base.FrameIndex, MVT::i32);
+        CurDAG->SelectNodeTo(N, Opc, MVT::Other,
+                             Base, Scale, AM.IndexReg, Disp, Tmp1, Chain);
+      }
+    }
   }
 
   return SelectCode(Op);





From lattner at cs.uiuc.edu  Tue Nov 29 23:11:30 2005
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Tue, 29 Nov 2005 23:11:30 -0600
Subject: [llvm-commits] CVS: llvm/lib/Target/X86/X86InstrInfo.td 
Message-ID: <200511300511.XAA25142@zion.cs.uiuc.edu>



Changes in directory llvm/lib/Target/X86:

X86InstrInfo.td updated: 1.142 -> 1.143
---
Log message:

Fix a bug in a recent patch that broke shifts


---
Diffs of the changes:  (+3 -3)

 X86InstrInfo.td |    6 +++---
 1 files changed, 3 insertions(+), 3 deletions(-)


Index: llvm/lib/Target/X86/X86InstrInfo.td
diff -u llvm/lib/Target/X86/X86InstrInfo.td:1.142 llvm/lib/Target/X86/X86InstrInfo.td:1.143
--- llvm/lib/Target/X86/X86InstrInfo.td:1.142	Tue Nov 29 13:38:52 2005
+++ llvm/lib/Target/X86/X86InstrInfo.td	Tue Nov 29 23:11:18 2005
@@ -918,11 +918,11 @@
   def SHL32mCL : I<0xD3, MRM4m, (ops i32mem:$dst),
                    "shl{l} {%cl, $dst|$dst, %CL}", []>, Imp<[CL],[]>;
   def SHL8mi   : Ii8<0xC0, MRM4m, (ops i8mem :$dst, i8imm:$src),
-                     "shl{b} {$src, $dst|$dst, $src}, []", []>;
+                     "shl{b} {$src, $dst|$dst, $src}", []>;
   def SHL16mi  : Ii8<0xC1, MRM4m, (ops i16mem:$dst, i8imm:$src),
-                     "shl{w} {$src, $dst|$dst, $src}, []", []>, OpSize;
+                     "shl{w} {$src, $dst|$dst, $src}", []>, OpSize;
   def SHL32mi  : Ii8<0xC1, MRM4m, (ops i32mem:$dst, i8imm:$src),
-                     "shl{l} {$src, $dst|$dst, $src}, []", []>;
+                     "shl{l} {$src, $dst|$dst, $src}", []>;
 }
 
 def SHR8rCL  : I<0xD2, MRM5r, (ops R8 :$dst, R8 :$src),





From reid at x10sys.com  Tue Nov 29 23:21:23 2005
From: reid at x10sys.com (Reid Spencer)
Date: Tue, 29 Nov 2005 23:21:23 -0600
Subject: [llvm-commits] 
	CVS: llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
Message-ID: <200511300521.XAA25547@zion.cs.uiuc.edu>



Changes in directory llvm/lib/CodeGen/SelectionDAG:

SelectionDAGISel.cpp updated: 1.106 -> 1.107
---
Log message:

Fix a problem with llvm-ranlib that (on some platforms) caused the archive
file to become corrupted due to interactions between mmap'd memory segments
and file descriptors closing. The problem is completely avoiding by using
a third temporary file.

Patch provided by Evan Jones


---
Diffs of the changes:  (+30 -0)

 SelectionDAGISel.cpp |   30 ++++++++++++++++++++++++++++++
 1 files changed, 30 insertions(+)


Index: llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.106 llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.107
--- llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.106	Tue Nov 29 00:21:05 2005
+++ llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp	Tue Nov 29 23:21:10 2005
@@ -1161,6 +1161,36 @@
 }
 
 void SelectionDAGLowering::visitMemIntrinsic(CallInst &I, unsigned Op) {
+#if 0
+  // If the size of the cpy/move/set is constant (known)
+  if (ConstantUInt* op3 = dyn_cast<ConstantUInt>(I.getOperand(3))) {
+    uint64_t size = op3->getValue();
+    switch (Op) {
+      case ISD::MEMSET: 
+        if (size <= TLI.getMaxStoresPerMemSet()) {
+          if (ConstantUInt* op4 = dyn_cast<ConstantUInt>(I.getOperand(4))) {
+        uint64_t TySize = TLI.getTargetData().getTypeSize(Ty);
+            uint64_t align = op4.getValue();
+            while (size > align) {
+              size -=align;
+            }
+  Value *SrcV = I.getOperand(0);
+  SDOperand Src = getValue(SrcV);
+  SDOperand Ptr = getValue(I.getOperand(1));
+  DAG.setRoot(DAG.getNode(ISD::STORE, MVT::Other, getRoot(), Src, Ptr,
+                          DAG.getSrcValue(I.getOperand(1))));
+          }
+          break;
+        }
+        break; // don't do this optimization, use a normal memset
+      case ISD::MEMMOVE: 
+      case ISD::MEMCPY:
+        break; // FIXME: not implemented yet
+    }
+  }
+#endif
+
+  // Non-optimized version
   std::vector<SDOperand> Ops;
   Ops.push_back(getRoot());
   Ops.push_back(getValue(I.getOperand(1)));





From reid at x10sys.com  Tue Nov 29 23:21:23 2005
From: reid at x10sys.com (Reid Spencer)
Date: Tue, 29 Nov 2005 23:21:23 -0600
Subject: [llvm-commits] CVS: llvm/lib/Bytecode/Archive/Archive.cpp
	ArchiveWriter.cpp 
Message-ID: <200511300521.XAA25543@zion.cs.uiuc.edu>



Changes in directory llvm/lib/Bytecode/Archive:

Archive.cpp updated: 1.9 -> 1.10
ArchiveWriter.cpp updated: 1.20 -> 1.21
---
Log message:

Fix a problem with llvm-ranlib that (on some platforms) caused the archive
file to become corrupted due to interactions between mmap'd memory segments
and file descriptors closing. The problem is completely avoiding by using
a third temporary file.

Patch provided by Evan Jones


---
Diffs of the changes:  (+72 -36)

 Archive.cpp       |   24 ++++++++++++++-
 ArchiveWriter.cpp |   84 ++++++++++++++++++++++++++++++++----------------------
 2 files changed, 72 insertions(+), 36 deletions(-)


Index: llvm/lib/Bytecode/Archive/Archive.cpp
diff -u llvm/lib/Bytecode/Archive/Archive.cpp:1.9 llvm/lib/Bytecode/Archive/Archive.cpp:1.10
--- llvm/lib/Bytecode/Archive/Archive.cpp:1.9	Thu May  5 17:32:02 2005
+++ llvm/lib/Bytecode/Archive/Archive.cpp	Tue Nov 29 23:21:10 2005
@@ -140,13 +140,28 @@
   }
 }
 
-// Archive destructor - just clean up memory
-Archive::~Archive() {
+void Archive::cleanUpMemory() {
   // Shutdown the file mapping
   if (mapfile) {
     mapfile->close();
     delete mapfile;
+    
+    mapfile = 0;
+    base = 0;
   }
+  
+  // Forget the entire symbol table
+  symTab.clear();
+  symTabSize = 0;
+  
+  firstFileOffset = 0;
+  
+  // Free the foreign symbol table member
+  if (foreignST) {
+    delete foreignST;
+    foreignST = 0;
+  }
+  
   // Delete any ModuleProviders and ArchiveMember's we've allocated as a result
   // of symbol table searches.
   for (ModuleMap::iterator I=modules.begin(), E=modules.end(); I != E; ++I ) {
@@ -155,3 +170,8 @@
   }
 }
 
+// Archive destructor - just clean up memory
+Archive::~Archive() {
+  cleanUpMemory();
+}
+


Index: llvm/lib/Bytecode/Archive/ArchiveWriter.cpp
diff -u llvm/lib/Bytecode/Archive/ArchiveWriter.cpp:1.20 llvm/lib/Bytecode/Archive/ArchiveWriter.cpp:1.21
--- llvm/lib/Bytecode/Archive/ArchiveWriter.cpp:1.20	Thu Jul  7 22:08:58 2005
+++ llvm/lib/Bytecode/Archive/ArchiveWriter.cpp	Tue Nov 29 23:21:10 2005
@@ -421,42 +421,58 @@
       sys::MappedFile arch(TmpArchive);
       const char* base = (const char*) arch.map();
 
-      // Open the final file to write and check it.
-      std::ofstream FinalFile(archPath.c_str(), io_mode);
-      if ( !FinalFile.is_open() || FinalFile.bad() ) {
-        throw std::string("Error opening archive file: ") + archPath.toString();
+      // Open another temporary file in order to avoid invalidating the mmapped data
+      sys::Path FinalFilePath = archPath;
+      FinalFilePath.createTemporaryFileOnDisk();
+      sys::RemoveFileOnSignal(FinalFilePath);
+      try {
+          
+  
+        std::ofstream FinalFile(FinalFilePath.c_str(), io_mode);
+        if ( !FinalFile.is_open() || FinalFile.bad() ) {
+          throw std::string("Error opening archive file: ") + FinalFilePath.toString();
+        }
+  
+        // Write the file magic number
+        FinalFile << ARFILE_MAGIC;
+  
+        // If there is a foreign symbol table, put it into the file now. Most
+        // ar(1) implementations require the symbol table to be first but llvm-ar
+        // can deal with it being after a foreign symbol table. This ensures
+        // compatibility with other ar(1) implementations as well as allowing the
+        // archive to store both native .o and LLVM .bc files, both indexed.
+        if (foreignST) {
+          writeMember(*foreignST, FinalFile, false, false, false);
+        }
+  
+        // Put out the LLVM symbol table now.
+        writeSymbolTable(FinalFile);
+  
+        // Copy the temporary file contents being sure to skip the file's magic
+        // number.
+        FinalFile.write(base + sizeof(ARFILE_MAGIC)-1,
+          arch.size()-sizeof(ARFILE_MAGIC)+1);
+  
+        // Close up shop
+        FinalFile.close();
+        arch.close();
+        
+        // Move the final file over top of TmpArchive
+        FinalFilePath.renamePathOnDisk(TmpArchive);
+      } catch (...) {
+        // Make sure we clean up.
+        if (FinalFilePath.exists())
+          FinalFilePath.eraseFromDisk();
+        throw;
       }
-
-      // Write the file magic number
-      FinalFile << ARFILE_MAGIC;
-
-      // If there is a foreign symbol table, put it into the file now. Most
-      // ar(1) implementations require the symbol table to be first but llvm-ar
-      // can deal with it being after a foreign symbol table. This ensures
-      // compatibility with other ar(1) implementations as well as allowing the
-      // archive to store both native .o and LLVM .bc files, both indexed.
-      if (foreignST) {
-        writeMember(*foreignST, FinalFile, false, false, false);
-      }
-
-      // Put out the LLVM symbol table now.
-      writeSymbolTable(FinalFile);
-
-      // Copy the temporary file contents being sure to skip the file's magic
-      // number.
-      FinalFile.write(base + sizeof(ARFILE_MAGIC)-1,
-        arch.size()-sizeof(ARFILE_MAGIC)+1);
-
-      // Close up shop
-      FinalFile.close();
-      arch.close();
-      TmpArchive.eraseFromDisk();
-
-    } else {
-      // We don't have to insert the symbol table, so just renaming the temp
-      // file to the correct name will suffice.
-      TmpArchive.renamePathOnDisk(archPath);
     }
+    
+    // Before we replace the actual archive, we need to forget all the
+    // members, since they point to data in that old archive. We need to do
+    // we cannot replace an open file on Windows.
+    cleanUpMemory();
+    
+    TmpArchive.renamePathOnDisk(archPath);
   } catch (...) {
     // Make sure we clean up.
     if (TmpArchive.exists())





From reid at x10sys.com  Tue Nov 29 23:21:24 2005
From: reid at x10sys.com (Reid Spencer)
Date: Tue, 29 Nov 2005 23:21:24 -0600
Subject: [llvm-commits] CVS: llvm/include/llvm/Bytecode/Archive.h 
Message-ID: <200511300521.XAA25552@zion.cs.uiuc.edu>



Changes in directory llvm/include/llvm/Bytecode:

Archive.h updated: 1.11 -> 1.12
---
Log message:

Fix a problem with llvm-ranlib that (on some platforms) caused the archive
file to become corrupted due to interactions between mmap'd memory segments
and file descriptors closing. The problem is completely avoiding by using
a third temporary file.

Patch provided by Evan Jones


---
Diffs of the changes:  (+3 -0)

 Archive.h |    3 +++
 1 files changed, 3 insertions(+)


Index: llvm/include/llvm/Bytecode/Archive.h
diff -u llvm/include/llvm/Bytecode/Archive.h:1.11 llvm/include/llvm/Bytecode/Archive.h:1.12
--- llvm/include/llvm/Bytecode/Archive.h:1.11	Thu Apr 21 15:34:13 2005
+++ llvm/include/llvm/Bytecode/Archive.h	Tue Nov 29 23:21:10 2005
@@ -489,6 +489,9 @@
     bool fillHeader(const ArchiveMember&mbr,
                     ArchiveMemberHeader& hdr,int sz, bool TruncateNames) const;
 
+    /// @brief Frees all the members and unmaps the archive file.
+    void Archive::cleanUpMemory();
+
     /// This type is used to keep track of bytecode modules loaded from the
     /// symbol table. It maps the file offset to a pair that consists of the
     /// associated ArchiveMember and the ModuleProvider.





From lattner at cs.uiuc.edu  Tue Nov 29 23:26:15 2005
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Tue, 29 Nov 2005 23:26:15 -0600
Subject: [llvm-commits] CVS: llvm/include/llvm/Bytecode/Archive.h 
Message-ID: <200511300526.XAA27700@zion.cs.uiuc.edu>



Changes in directory llvm/include/llvm/Bytecode:

Archive.h updated: 1.12 -> 1.13
---
Log message:

minor cleanup


---
Diffs of the changes:  (+1 -1)

 Archive.h |    2 +-
 1 files changed, 1 insertion(+), 1 deletion(-)


Index: llvm/include/llvm/Bytecode/Archive.h
diff -u llvm/include/llvm/Bytecode/Archive.h:1.12 llvm/include/llvm/Bytecode/Archive.h:1.13
--- llvm/include/llvm/Bytecode/Archive.h:1.12	Tue Nov 29 23:21:10 2005
+++ llvm/include/llvm/Bytecode/Archive.h	Tue Nov 29 23:26:03 2005
@@ -490,7 +490,7 @@
                     ArchiveMemberHeader& hdr,int sz, bool TruncateNames) const;
 
     /// @brief Frees all the members and unmaps the archive file.
-    void Archive::cleanUpMemory();
+    void cleanUpMemory();
 
     /// This type is used to keep track of bytecode modules loaded from the
     /// symbol table. It maps the file offset to a pair that consists of the





From lattner at cs.uiuc.edu  Wed Nov 30 00:31:40 2005
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Wed, 30 Nov 2005 00:31:40 -0600
Subject: [llvm-commits] CVS: llvm/docs/Makefile 
Message-ID: <200511300631.AAA20691@zion.cs.uiuc.edu>



Changes in directory llvm/docs:

Makefile updated: 1.10 -> 1.11
---
Log message:

copy the doxygen tarball into the HTML directory after building it



---
Diffs of the changes:  (+1 -0)

 Makefile |    1 +
 1 files changed, 1 insertion(+)


Index: llvm/docs/Makefile
diff -u llvm/docs/Makefile:1.10 llvm/docs/Makefile:1.11
--- llvm/docs/Makefile:1.10	Mon May 16 13:29:13 2005
+++ llvm/docs/Makefile	Wed Nov 30 00:31:28 2005
@@ -63,6 +63,7 @@
 	$(Verb) $(RM) -rf $@ $(PROJ_OBJ_DIR)/doxygen.tar
 	$(Verb) $(TAR) cf $(PROJ_OBJ_DIR)/doxygen.tar doxygen
 	$(Verb) $(GZIP) $(PROJ_OBJ_DIR)/doxygen.tar
+	$(Verb) $(CP) $(PROJ_OBJ_DIR)/doxygen.tar.gz $(PROJ_OBJ_DIR)/doxygen/html/
 
 userloc: $(LLVM_SRC_ROOT)/docs/userloc.html
 





From lattner at cs.uiuc.edu  Wed Nov 30 00:35:46 2005
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Wed, 30 Nov 2005 00:35:46 -0600
Subject: [llvm-commits] CVS: llvm/docs/index.html 
Message-ID: <200511300635.AAA26042@zion.cs.uiuc.edu>



Changes in directory llvm/docs:

index.html updated: 1.47 -> 1.48
---
Log message:

Add a link to the doxygen tarball


---
Diffs of the changes:  (+5 -2)

 index.html |    7 +++++--
 1 files changed, 5 insertions(+), 2 deletions(-)


Index: llvm/docs/index.html
diff -u llvm/docs/index.html:1.47 llvm/docs/index.html:1.48
--- llvm/docs/index.html:1.47	Sun Apr 24 12:46:56 2005
+++ llvm/docs/index.html	Wed Nov 30 00:35:34 2005
@@ -148,7 +148,10 @@
 
 <li><a href="http://llvm.cs.uiuc.edu/doxygen/">Doxygen generated 
 documentation</a> (<a
-href="http://llvm.cs.uiuc.edu/doxygen/inherits.html">classes</a>)</li>
+href="http://llvm.cs.uiuc.edu/doxygen/inherits.html">classes</a>)
+
+(<a href="http://llvm.cs.uiuc.edu/doxygen/doxygen.tar.gz">tarball</a>)
+</li>
 
 <li><a href="http://llvm.cs.uiuc.edu/cvsweb/cvsweb.cgi/llvm">CVSWeb CVS Tree 
 Browser</a></li>
@@ -242,6 +245,6 @@
   src="http://www.w3.org/Icons/valid-html401" alt="Valid HTML 4.01!"></a>
 
   <a href="http://llvm.cs.uiuc.edu">LLVM Compiler Infrastructure</a><br>
-  Last modified: $Date: 2005/04/24 17:46:56 $
+  Last modified: $Date: 2005/11/30 06:35:34 $
 </address>
 





From alenhar2 at cs.uiuc.edu  Wed Nov 30 00:43:15 2005
From: alenhar2 at cs.uiuc.edu (Andrew Lenharth)
Date: Wed, 30 Nov 2005 00:43:15 -0600
Subject: [llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp 
Message-ID: <200511300643.AAA31721@zion.cs.uiuc.edu>



Changes in directory llvm/lib/CodeGen/SelectionDAG:

LegalizeDAG.cpp updated: 1.217 -> 1.218
---
Log message:

add support for custom lowering SINT_TO_FP

---
Diffs of the changes:  (+13 -0)

 LegalizeDAG.cpp |   13 +++++++++++++
 1 files changed, 13 insertions(+)


Index: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.217 llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.218
--- llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.217	Tue Nov 29 00:21:05 2005
+++ llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp	Wed Nov 30 00:43:03 2005
@@ -1956,6 +1956,19 @@
         return Result;
       case TargetLowering::Legal:
         break;
+      case TargetLowering::Custom: {
+        Tmp1 = LegalizeOp(Node->getOperand(0));
+        SDOperand Tmp =
+          DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1);
+        Tmp = TLI.LowerOperation(Tmp, DAG);
+        if (Tmp.Val) {
+          AddLegalizedOperand(Op, Tmp);
+          NeedsAnotherIteration = true;
+          return Tmp;
+        } else {
+          assert(0 && "Target Must Lower this");
+        }
+      }
       }
 
       Tmp1 = LegalizeOp(Node->getOperand(0));





From alenhar2 at cs.uiuc.edu  Wed Nov 30 01:14:38 2005
From: alenhar2 at cs.uiuc.edu (Andrew Lenharth)
Date: Wed, 30 Nov 2005 01:14:38 -0600
Subject: [llvm-commits] CVS: llvm-test/Makefile.programs 
Message-ID: <200511300714.BAA08086@zion.cs.uiuc.edu>



Changes in directory llvm-test:

Makefile.programs updated: 1.179 -> 1.180
---
Log message:

Why not.  Performance sucks, but correctness sucks more, so sounds just right for beta.  Maybe I will be surprised.

---
Diffs of the changes:  (+2 -2)

 Makefile.programs |    4 ++--
 1 files changed, 2 insertions(+), 2 deletions(-)


Index: llvm-test/Makefile.programs
diff -u llvm-test/Makefile.programs:1.179 llvm-test/Makefile.programs:1.180
--- llvm-test/Makefile.programs:1.179	Sat Nov 12 13:21:05 2005
+++ llvm-test/Makefile.programs	Wed Nov 30 01:14:26 2005
@@ -190,8 +190,8 @@
 LLCBETAOPTION := -sched=simple
 endif
 ifeq ($(ARCH),Alpha)
-LLCBETAOPTION := -enable-alpha-intfpdiv
-# -enable-alpha-FTOI
+LLCBETAOPTION := -enable-dag-isel-for-alpha
+# -enable-alpha-FTOI -enable-alpha-intfpdiv
 endif
 ifeq ($(ARCH),IA64)
 LLCBETAOPTION := -enable-ia64-dag-isel 





From alenhar2 at cs.uiuc.edu  Wed Nov 30 01:20:09 2005
From: alenhar2 at cs.uiuc.edu (Andrew Lenharth)
Date: Wed, 30 Nov 2005 01:20:09 -0600
Subject: [llvm-commits] CVS: llvm/lib/Target/Alpha/AlphaISelDAGToDAG.cpp
	AlphaISelLowering.cpp AlphaISelLowering.h
	AlphaISelPattern.cpp AlphaInstrFormats.td AlphaInstrInfo.td
	AlphaRegisterInfo.td 
Message-ID: <200511300720.BAA08305@zion.cs.uiuc.edu>



Changes in directory llvm/lib/Target/Alpha:

AlphaISelDAGToDAG.cpp updated: 1.6 -> 1.7
AlphaISelLowering.cpp updated: 1.9 -> 1.10
AlphaISelLowering.h updated: 1.3 -> 1.4
AlphaISelPattern.cpp updated: 1.188 -> 1.189
AlphaInstrFormats.td updated: 1.14 -> 1.15
AlphaInstrInfo.td updated: 1.73 -> 1.74
AlphaRegisterInfo.td updated: 1.13 -> 1.14
---
Log message:

All sorts of stuff.

Getting in on the custom lowering thing, yay
evilness with fp setcc, yuck
trivial int select, hmmm
in memory args for functions, yay
DIV and REM, always handy.  They should be custom lowered though.

Lots more stuff compiles now (go go single source!).  Of course, none of it
probably works, but that is what the nightly tester can find out :)



---
Diffs of the changes:  (+203 -32)

 AlphaISelDAGToDAG.cpp |   90 ++++++++++++++++++++++++++++++++++++++++++++++++--
 AlphaISelLowering.cpp |   35 ++++++++++++++++++-
 AlphaISelLowering.h   |   10 +++++
 AlphaISelPattern.cpp  |   22 ++++++------
 AlphaInstrFormats.td  |   10 +++++
 AlphaInstrInfo.td     |   62 +++++++++++++++++++++++++++-------
 AlphaRegisterInfo.td  |    6 +--
 7 files changed, 203 insertions(+), 32 deletions(-)


Index: llvm/lib/Target/Alpha/AlphaISelDAGToDAG.cpp
diff -u llvm/lib/Target/Alpha/AlphaISelDAGToDAG.cpp:1.6 llvm/lib/Target/Alpha/AlphaISelDAGToDAG.cpp:1.7
--- llvm/lib/Target/Alpha/AlphaISelDAGToDAG.cpp:1.6	Mon Nov 21 22:20:06 2005
+++ llvm/lib/Target/Alpha/AlphaISelDAGToDAG.cpp	Wed Nov 30 01:19:56 2005
@@ -16,6 +16,7 @@
 #include "AlphaTargetMachine.h"
 #include "AlphaISelLowering.h"
 #include "llvm/CodeGen/MachineInstrBuilder.h"
+#include "llvm/CodeGen/MachineFrameInfo.h"
 #include "llvm/CodeGen/MachineFunction.h"
 #include "llvm/CodeGen/SSARegMap.h"
 #include "llvm/CodeGen/SelectionDAG.h"
@@ -278,6 +279,7 @@
       CurDAG->SelectNodeTo(N, Alpha::LDAr, MVT::i64, CPI, Tmp);
       return SDOperand(N, 0);
     }
+    break;
   }
   case ISD::ConstantFP:
     if (ConstantFPSDNode *CN = dyn_cast<ConstantFPSDNode>(N)) {
@@ -296,7 +298,76 @@
       } else {
         abort();
       }
+      break;
     }
+  case ISD::SDIV:
+  case ISD::UDIV:
+  case ISD::UREM:
+  case ISD::SREM:
+    if (MVT::isInteger(N->getValueType(0))) {
+      const char* opstr = 0;
+      switch(N->getOpcode()) {
+      case ISD::UREM: opstr = "__remqu"; break;
+      case ISD::SREM: opstr = "__remq";  break;
+      case ISD::UDIV: opstr = "__divqu"; break;
+      case ISD::SDIV: opstr = "__divq";  break;
+      }
+      SDOperand Tmp1 = Select(N->getOperand(0)),
+        Tmp2 = Select(N->getOperand(1)),
+        Addr = CurDAG->getExternalSymbol(opstr, AlphaLowering.getPointerTy());
+      SDOperand Tmp3 = Select(Addr);
+      SDOperand Chain = CurDAG->getCopyToReg(CurDAG->getRoot(), Alpha::R24, 
+                                             Tmp1, SDOperand());
+      Chain = CurDAG->getCopyToReg(CurDAG->getRoot(), Alpha::R25, 
+                                   Tmp2, Chain.getValue(1));
+      Chain = CurDAG->getCopyToReg(CurDAG->getRoot(), Alpha::R27, 
+                                   Tmp3, Chain.getValue(1));
+      Chain = CurDAG->getTargetNode(Alpha::JSRs, MVT::i64, MVT::Flag,
+                                    CurDAG->getRegister(Alpha::R27, MVT::i64),
+                                    getI64Imm(0));
+      return CurDAG->getCopyFromReg(Chain.getValue(1), Alpha::R27, MVT::i64, 
+                                    Chain.getValue(1));
+    }
+    break;
+
+  case ISD::SETCC:
+    if (MVT::isFloatingPoint(N->getOperand(0).Val->getValueType(0))) {
+      unsigned Opc = Alpha::WTF;
+      ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(2))->get();
+      bool rev = false;
+      switch(CC) {
+      default: N->dump(); assert(0 && "Unknown FP comparison!");
+      case ISD::SETEQ: Opc = Alpha::CMPTEQ; break;
+      case ISD::SETLT: Opc = Alpha::CMPTLT; break;
+      case ISD::SETLE: Opc = Alpha::CMPTLE; break;
+      case ISD::SETGT: Opc = Alpha::CMPTLT; rev = true; break;
+      case ISD::SETGE: Opc = Alpha::CMPTLE; rev = true; break;
+        //case ISD::SETNE: Opc = Alpha::CMPTEQ; inv = true; break;
+      };
+      SDOperand tmp1 = Select(N->getOperand(0)),
+        tmp2 = Select(N->getOperand(1));
+      SDOperand cmp = CurDAG->getTargetNode(Opc, MVT::f64, 
+                                            rev?tmp2:tmp1,
+                                            rev?tmp1:tmp2);
+      SDOperand LD;
+      if (AlphaLowering.hasITOF()) {
+        LD = CurDAG->getNode(AlphaISD::FTOIT_, MVT::i64, cmp);
+      } else {
+        int FrameIdx =
+          CurDAG->getMachineFunction().getFrameInfo()->CreateStackObject(8, 8);
+        SDOperand FI = CurDAG->getFrameIndex(FrameIdx, MVT::i64);
+        SDOperand ST = CurDAG->getTargetNode(Alpha::STT, MVT::Other, 
+                                             cmp, FI, CurDAG->getRegister(Alpha::R31, MVT::i64));
+        LD = CurDAG->getTargetNode(Alpha::LDQ, MVT::i64, FI, 
+                                   CurDAG->getRegister(Alpha::R31, MVT::i64),
+                                   ST);
+      }
+      SDOperand FP = CurDAG->getTargetNode(Alpha::CMPULT, MVT::i64, 
+                                           CurDAG->getRegister(Alpha::R31, MVT::i64),
+                                           LD);
+      return FP;
+    }
+    break;
   }
   
   return SelectCode(Op);
@@ -328,13 +399,26 @@
    for (int i = 0; i < std::min(6, count); ++i) {
      if (MVT::isInteger(TypeOperands[i])) {
        Chain = CurDAG->getCopyToReg(Chain, args_int[i], CallOperands[i]);
-     } else if (TypeOperands[i] == MVT::f64 || TypeOperands[i] == MVT::f64) {
+     } else if (TypeOperands[i] == MVT::f32 || TypeOperands[i] == MVT::f64) {
        Chain = CurDAG->getCopyToReg(Chain, args_float[i], CallOperands[i]);
      } else
        assert(0 && "Unknown operand"); 
    }
-
-   assert(CallOperands.size() <= 6 && "Too big a call");
+   for (int i = 6; i < count; ++i) {
+     unsigned Opc = Alpha::WTF;
+     if (MVT::isInteger(TypeOperands[i])) {
+       Opc = Alpha::STQ;
+     } else if (TypeOperands[i] == MVT::f32) {
+       Opc = Alpha::STS;
+     } else if (TypeOperands[i] == MVT::f64) {
+       Opc = Alpha::STT;
+     } else
+       assert(0 && "Unknown operand"); 
+     Chain = CurDAG->getTargetNode(Opc, MVT::Other, CallOperands[i], 
+                                   getI64Imm((i - 6) * 8), 
+                                   CurDAG->getRegister(Alpha::R30, MVT::i64),
+                                   Chain);
+   }
 
    Chain = CurDAG->getCopyToReg(Chain, Alpha::R27, Addr);
    // Finally, once everything is in registers to pass to the call, emit the


Index: llvm/lib/Target/Alpha/AlphaISelLowering.cpp
diff -u llvm/lib/Target/Alpha/AlphaISelLowering.cpp:1.9 llvm/lib/Target/Alpha/AlphaISelLowering.cpp:1.10
--- llvm/lib/Target/Alpha/AlphaISelLowering.cpp:1.9	Tue Nov 29 00:16:21 2005
+++ llvm/lib/Target/Alpha/AlphaISelLowering.cpp	Wed Nov 30 01:19:56 2005
@@ -72,6 +72,7 @@
   setOperationAction(ISD::FREM, MVT::f64, Expand);
   
   setOperationAction(ISD::UINT_TO_FP, MVT::i64, Expand);
+  setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom);
   
   if (!TM.getSubtarget<AlphaSubtarget>().hasCT()) {
     setOperationAction(ISD::CTPOP    , MVT::i64  , Expand);
@@ -101,10 +102,12 @@
   // We don't have line number support yet.
   setOperationAction(ISD::LOCATION, MVT::Other, Expand);
   
-  computeRegisterProperties();
-  
   addLegalFPImmediate(+0.0); //F31
   addLegalFPImmediate(-0.0); //-F31
+
+  computeRegisterProperties();
+
+  useITOF = TM.getSubtarget<AlphaSubtarget>().hasF2I();
 }
 
 
@@ -385,3 +388,31 @@
 }
 
 
+/// LowerOperation - Provide custom lowering hooks for some operations.
+///
+SDOperand AlphaTargetLowering::LowerOperation(SDOperand Op, SelectionDAG &DAG) {
+  switch (Op.getOpcode()) {
+  default: assert(0 && "Wasn't expecting to be able to lower this!"); 
+  case ISD::SINT_TO_FP: {
+    assert(MVT::i64 == Op.getOperand(0).getValueType() && 
+           "Unhandled SINT_TO_FP type in custom expander!");
+    SDOperand LD;
+    bool isDouble = MVT::f64 == Op.getValueType();
+    if (useITOF) {
+      LD = DAG.getNode(AlphaISD::ITOFT_, MVT::f64, Op.getOperand(0));
+    } else {
+      int FrameIdx =
+        DAG.getMachineFunction().getFrameInfo()->CreateStackObject(8, 8);
+      SDOperand FI = DAG.getFrameIndex(FrameIdx, MVT::i64);
+      SDOperand ST = DAG.getNode(ISD::STORE, MVT::Other, DAG.getEntryNode(),
+                                 Op.getOperand(0), FI, DAG.getSrcValue(0));
+      LD = DAG.getLoad(MVT::f64, ST, FI, DAG.getSrcValue(0));
+      }
+    SDOperand FP = DAG.getNode(isDouble?AlphaISD::CVTQT_:AlphaISD::CVTQS_,
+                               isDouble?MVT::f64:MVT::f32, LD);
+    return FP;
+  }
+  }
+  return SDOperand();
+}
+


Index: llvm/lib/Target/Alpha/AlphaISelLowering.h
diff -u llvm/lib/Target/Alpha/AlphaISelLowering.h:1.3 llvm/lib/Target/Alpha/AlphaISelLowering.h:1.4
--- llvm/lib/Target/Alpha/AlphaISelLowering.h:1.3	Sat Oct 22 17:06:58 2005
+++ llvm/lib/Target/Alpha/AlphaISelLowering.h	Wed Nov 30 01:19:56 2005
@@ -25,6 +25,8 @@
     enum NodeType {
       // Start the numbering where the builting ops and target ops leave off.
       FIRST_NUMBER = ISD::BUILTIN_OP_END+Alpha::INSTRUCTION_LIST_END,
+      //These corrospond to the identical Instruction
+      ITOFT_, FTOIT_, CVTQT_, CVTQS_,
     };
   }
 
@@ -33,9 +35,14 @@
     int VarArgsBase;    // What is the base FrameIndex
     unsigned GP; //GOT vreg
     unsigned RA; //Return Address
+    bool useITOF;
   public:
     AlphaTargetLowering(TargetMachine &TM);
-
+    
+    /// LowerOperation - Provide custom lowering hooks for some operations.
+    ///
+    virtual SDOperand LowerOperation(SDOperand Op, SelectionDAG &DAG);
+    
     /// LowerArguments - This hook must be implemented to indicate how we should
     /// lower the arguments for the specified function, into the specified DAG.
     virtual std::vector<SDOperand>
@@ -61,6 +68,7 @@
     void restoreRA(MachineBasicBlock* BB);
     unsigned getVRegGP() { return GP; }
     unsigned getVRegRA() { return RA; }
+    bool hasITOF() { return useITOF; }
   };
 }
 


Index: llvm/lib/Target/Alpha/AlphaISelPattern.cpp
diff -u llvm/lib/Target/Alpha/AlphaISelPattern.cpp:1.188 llvm/lib/Target/Alpha/AlphaISelPattern.cpp:1.189
--- llvm/lib/Target/Alpha/AlphaISelPattern.cpp:1.188	Tue Nov 22 14:59:00 2005
+++ llvm/lib/Target/Alpha/AlphaISelPattern.cpp	Wed Nov 30 01:19:56 2005
@@ -1559,17 +1559,17 @@
     }
     return Result;
 
-  case ISD::SINT_TO_FP:
-    {
-      assert (N.getOperand(0).getValueType() == MVT::i64
-              && "only quads can be loaded from");
-      Tmp1 = SelectExpr(N.getOperand(0));  // Get the operand register
-      Tmp2 = MakeReg(MVT::f64);
-      MoveInt2FP(Tmp1, Tmp2, true);
-      Opc = DestType == MVT::f64 ? Alpha::CVTQT : Alpha::CVTQS;
-      BuildMI(BB, Opc, 1, Result).addReg(Tmp2);
-      return Result;
-    }
+  case AlphaISD::CVTQT_:
+    BuildMI(BB, Alpha::CVTQT, 1, Result).addReg(SelectExpr(N.getOperand(0)));
+    return Result;
+
+  case AlphaISD::CVTQS_:
+    BuildMI(BB, Alpha::CVTQS, 1, Result).addReg(SelectExpr(N.getOperand(0)));
+    return Result;
+
+  case AlphaISD::ITOFT_:
+    BuildMI(BB, Alpha::ITOFT, 1, Result).addReg(SelectExpr(N.getOperand(0)));
+    return Result;
 
   case ISD::AssertSext:
   case ISD::AssertZext:


Index: llvm/lib/Target/Alpha/AlphaInstrFormats.td
diff -u llvm/lib/Target/Alpha/AlphaInstrFormats.td:1.14 llvm/lib/Target/Alpha/AlphaInstrFormats.td:1.15
--- llvm/lib/Target/Alpha/AlphaInstrFormats.td:1.14	Mon Nov 21 22:20:06 2005
+++ llvm/lib/Target/Alpha/AlphaInstrFormats.td	Wed Nov 30 01:19:56 2005
@@ -40,6 +40,16 @@
 }
 
 //3.3.1
+class MFormAlt<bits<6> opcode, string asmstr> 
+        : InstAlphaAlt<opcode, asmstr> {
+  bits<5> Ra;
+  bits<16> disp;
+  bits<5> Rb;
+
+  let Inst{25-21} = Ra;
+  let Inst{20-16} = Rb;
+  let Inst{15-0} = disp;
+}
 class MForm<bits<6> opcode, string asmstr> 
         : InstAlpha<opcode, (ops GPRC:$RA, s16imm:$DISP, GPRC:$RB), asmstr> {
   bits<5> Ra;


Index: llvm/lib/Target/Alpha/AlphaInstrInfo.td
diff -u llvm/lib/Target/Alpha/AlphaInstrInfo.td:1.73 llvm/lib/Target/Alpha/AlphaInstrInfo.td:1.74
--- llvm/lib/Target/Alpha/AlphaInstrInfo.td:1.73	Mon Nov 21 22:20:06 2005
+++ llvm/lib/Target/Alpha/AlphaInstrInfo.td	Wed Nov 30 01:19:56 2005
@@ -13,6 +13,20 @@
 include "AlphaInstrFormats.td"
 
 //********************
+//Custom DAG Nodes
+//********************
+
+def SDTFPUnaryOpUnC  : SDTypeProfile<1, 1, [
+  SDTCisFP<1>, SDTCisFP<0>
+]>;
+
+def Alpha_itoft : SDNode<"AlphaISD::ITOFT_", SDTIntToFPOp, []>;
+def Alpha_ftoit : SDNode<"AlphaISD::FTOIT_", SDTFPToIntOp, []>;
+def Alpha_cvtqt : SDNode<"AlphaISD::CVTQT_", SDTFPUnaryOpUnC, []>;
+def Alpha_cvtqs : SDNode<"AlphaISD::CVTQS_", SDTFPUnaryOpUnC, []>;
+
+
+//********************
 //Paterns for matching
 //********************
 
@@ -143,6 +157,10 @@
 def CMOVNE   : OForm4<  0x11, 0x26, "cmovne $RCOND,$RSRC,$RDEST">; //CMOVE if RCOND != zero
 def CMOVNEi  : OForm4L< 0x11, 0x26, "cmovne $RCOND,$L,$RDEST">; //CMOVE if RCOND != zero
 
+//FIXME: fold setcc with select
+def : Pat<(select GPRC:$which, GPRC:$src1, GPRC:$src2),
+      (CMOVEQ GPRC:$src1, GPRC:$src2, GPRC:$which)>;
+
 //conditional moves, fp
 let OperandList = (ops F8RC:$RDEST, F8RC:$RSRC2, F8RC:$RSRC, F8RC:$RCOND),
     isTwoAddress = 1 in {
@@ -409,12 +427,16 @@
 def LDWU : MForm<0x0C, "ldwu $RA,$DISP($RB)">; //Load zero-extended word
 
 //Stores, float
-def STS : MForm<0x26, "sts $RA,$DISP($RB)">; //Store S_floating
-def STT : MForm<0x27, "stt $RA,$DISP($RB)">; //Store T_floating
+let OperandList = (ops F4RC:$RA, s16imm:$DISP, GPRC:$RB) in
+def STS : MFormAlt<0x26, "sts $RA,$DISP($RB)">; //Store S_floating
+let OperandList = (ops F8RC:$RA, s16imm:$DISP, GPRC:$RB) in
+def STT : MFormAlt<0x27, "stt $RA,$DISP($RB)">; //Store T_floating
 
 //Loads, float
-def LDS : MForm<0x22, "lds $RA,$DISP($RB)">; //Load S_floating
-def LDT : MForm<0x23, "ldt $RA,$DISP($RB)">; //Load T_floating
+let OperandList = (ops F4RC:$RA, s16imm:$DISP, GPRC:$RB) in
+def LDS : MFormAlt<0x22, "lds $RA,$DISP($RB)">; //Load S_floating
+let OperandList = (ops F8RC:$RA, s16imm:$DISP, GPRC:$RB) in
+def LDT : MFormAlt<0x23, "ldt $RA,$DISP($RB)">; //Load T_floating
 
 //Load address
 def LDA : MForm<0x08,  "lda $RA,$DISP($RB)">;  //Load address
@@ -428,8 +450,10 @@
 def LDWUr : MForm<0x0C, "ldwu $RA,$DISP($RB)\t\t!gprellow">; //Load zero-extended word
 
 //Loads, float, Rellocated Low form
-def LDSr : MForm<0x22, "lds $RA,$DISP($RB)\t\t!gprellow">; //Load S_floating
-def LDTr : MForm<0x23, "ldt $RA,$DISP($RB)\t\t!gprellow">; //Load T_floating
+let OperandList = (ops F4RC:$RA, s16imm:$DISP, GPRC:$RB) in
+def LDSr : MFormAlt<0x22, "lds $RA,$DISP($RB)\t\t!gprellow">; //Load S_floating
+let OperandList = (ops F8RC:$RA, s16imm:$DISP, GPRC:$RB) in
+def LDTr : MFormAlt<0x23, "ldt $RA,$DISP($RB)\t\t!gprellow">; //Load T_floating
 
 //Load address, rellocated low and high form
 def LDAr : MForm<0x08,  "lda $RA,$DISP($RB)\t\t!gprellow">;  //Load address
@@ -450,8 +474,10 @@
 def STQr : MForm<0x2D, "stq $RA,$DISP($RB)\t\t!gprellow">; //Store quadword
 
 //Stores, float
-def STSr : MForm<0x26, "sts $RA,$DISP($RB)\t\t!gprellow">; //Store S_floating
-def STTr : MForm<0x27, "stt $RA,$DISP($RB)\t\t!gprellow">; //Store T_floating
+let OperandList = (ops F4RC:$RA, s16imm:$DISP, GPRC:$RB) in
+def STSr : MFormAlt<0x26, "sts $RA,$DISP($RB)\t\t!gprellow">; //Store S_floating
+let OperandList = (ops F8RC:$RA, s16imm:$DISP, GPRC:$RB) in
+def STTr : MFormAlt<0x27, "stt $RA,$DISP($RB)\t\t!gprellow">; //Store T_floating
 
 
 //Branches, int
@@ -533,17 +559,21 @@
 let OperandList = (ops GPRC:$RC, F4RC:$RA), Fb = 31 in 
 def FTOIS : FPForm<0x1C, 0x078, "ftois $RA,$RC",[]>; //Floating to integer move, S_floating
 let OperandList = (ops GPRC:$RC, F8RC:$RA), Fb = 31 in 
-def FTOIT : FPForm<0x1C, 0x070, "ftoit $RA,$RC",[]>; //Floating to integer move, T_floating
+def FTOIT : FPForm<0x1C, 0x070, "ftoit $RA,$RC",
+        [(set GPRC:$RC, (Alpha_ftoit F8RC:$RA))]>; //Floating to integer move
 let OperandList = (ops F4RC:$RC, GPRC:$RA), Fb = 31 in 
 def ITOFS : FPForm<0x14, 0x004, "itofs $RA,$RC",[]>; //Integer to floating move, S_floating
 let OperandList = (ops F8RC:$RC, GPRC:$RA), Fb = 31 in 
-def ITOFT : FPForm<0x14, 0x024, "itoft $RA,$RC",[]>; //Integer to floating move, T_floating
+def ITOFT : FPForm<0x14, 0x024, "itoft $RA,$RC",
+        [(set F8RC:$RC, (Alpha_itoft GPRC:$RA))]>; //Integer to floating move
 
 
 let OperandList = (ops F4RC:$RC, F8RC:$RB), Fa = 31 in 
-def CVTQS : FPForm<0x16, 0x7BC, "cvtqs/sui $RB,$RC",[]>; //Convert quadword to S_floating
+def CVTQS : FPForm<0x16, 0x7BC, "cvtqs/sui $RB,$RC",
+        [(set F4RC:$RC, (Alpha_cvtqs F8RC:$RB))]>;
 let OperandList = (ops F8RC:$RC, F8RC:$RB), Fa = 31 in 
-def CVTQT : FPForm<0x16, 0x7BE, "cvtqt/sui $RB,$RC",[]>; //Convert quadword to T_floating
+def CVTQT : FPForm<0x16, 0x7BE, "cvtqt/sui $RB,$RC",
+        [(set F8RC:$RC, (Alpha_cvtqt F8RC:$RB))]>;
 let OperandList = (ops F8RC:$RC, F8RC:$RB), Fa = 31 in 
 def CVTTQ : FPForm<0x16, 0x52F, "cvttq/svc $RB,$RC",[]>; //Convert T_floating to quadword
 let OperandList = (ops F8RC:$RC, F4RC:$RB), Fa = 31 in 
@@ -648,3 +678,11 @@
 def : Pat<(select GPRC:$which, GPRC:$src1, GPRC:$src2),
           (CMOVEQ GPRC:$src1, GPRC:$src2, GPRC:$which)>; //may be CMOVNE
 
+def : Pat<(fabs F8RC:$RB),
+          (CPYST F31, F8RC:$RB)>;
+def : Pat<(fabs F4RC:$RB),
+          (CPYSS F31, F4RC:$RB)>;
+def : Pat<(fneg F8RC:$RB),
+          (CPYSNT F8RC:$RB, F8RC:$RB)>;
+def : Pat<(fneg F4RC:$RB),
+          (CPYSNS F4RC:$RB, F4RC:$RB)>;


Index: llvm/lib/Target/Alpha/AlphaRegisterInfo.td
diff -u llvm/lib/Target/Alpha/AlphaRegisterInfo.td:1.13 llvm/lib/Target/Alpha/AlphaRegisterInfo.td:1.14
--- llvm/lib/Target/Alpha/AlphaRegisterInfo.td:1.13	Wed Nov  9 13:17:08 2005
+++ llvm/lib/Target/Alpha/AlphaRegisterInfo.td	Wed Nov 30 01:19:56 2005
@@ -78,7 +78,6 @@
   // $28 is undefined after any and all calls
 
 /// Register classes
-// Don't allocate 15, 28, 30, 31
 def GPRC : RegisterClass<"Alpha", i64, 64,
      // Volatile
      [R0, R1, R2, R3, R4, R5, R6, R7, R8, R16, R17, R18, R19, R20, R21, R22,
@@ -89,7 +88,8 @@
      R29, //global offset table address
      // Non-volatile
      R9, R10, R11, R12, R13, R14,
-     R31 ]> //zero
+// Don't allocate 15, 30, 31
+     R15, R30, R31 ]> //zero
 {
   let MethodProtos = [{
     iterator allocation_order_end(MachineFunction &MF) const;
@@ -97,7 +97,7 @@
   let MethodBodies = [{
     GPRCClass::iterator
     GPRCClass::allocation_order_end(MachineFunction &MF) const {
-        return end()-1;
+        return end()-3;
     }
   }];
 }





From natebegeman at mac.com  Wed Nov 30 02:22:41 2005
From: natebegeman at mac.com (Nate Begeman)
Date: Wed, 30 Nov 2005 02:22:41 -0600
Subject: [llvm-commits] 
	CVS: llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
Message-ID: <200511300822.CAA15122@zion.cs.uiuc.edu>



Changes in directory llvm/lib/CodeGen/SelectionDAG:

SelectionDAGISel.cpp updated: 1.107 -> 1.108
---
Log message:

First chunk of actually generating vector code for packed types.  These
changes allow us to generate the following code:

_foo:
        li r2, 0
        lvx v0, r2, r3
        vaddfp v0, v0, v0
        stvx v0, r2, r3
        blr

for this llvm:

void %foo(<4 x float>* %a) {
entry:
        %tmp1 = load <4 x float>* %a
        %tmp2 = add <4 x float> %tmp1, %tmp1
        store <4 x float> %tmp2, <4 x float>* %a
        ret void
}


---
Diffs of the changes:  (+12 -2)

 SelectionDAGISel.cpp |   14 ++++++++++++--
 1 files changed, 12 insertions(+), 2 deletions(-)


Index: llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.107 llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.108
--- llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.107	Tue Nov 29 23:21:10 2005
+++ llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp	Wed Nov 30 02:22:07 2005
@@ -520,12 +520,19 @@
     const PackedType *PTy = cast<PackedType>(Ty);
     unsigned NumElements = PTy->getNumElements();
     MVT::ValueType PVT = TLI.getValueType(PTy->getElementType());
+    MVT::ValueType TVT = MVT::getVectorType(PVT, NumElements);
     
     // Immediately scalarize packed types containing only one element, so that
-    // the Legalize pass does not have to deal with them.
+    // the Legalize pass does not have to deal with them.  Similarly, if the
+    // abstract vector is going to turn into one that the target natively
+    // supports, generate that type now so that Legalize doesn't have to deal
+    // with that either.  These steps ensure that Legalize only has to handle
+    // vector types in its Expand case.
+    unsigned Opc = MVT::isFloatingPoint(PVT) ? FPOp : IntOp;
     if (NumElements == 1) {
-      unsigned Opc = MVT::isFloatingPoint(PVT) ? FPOp : IntOp;
       setValue(&I, DAG.getNode(Opc, PVT, Op1, Op2));
+    } else if (TVT != MVT::Other && TLI.isTypeLegal(TVT)) {
+      setValue(&I, DAG.getNode(Opc, TVT, Op1, Op2));
     } else {
       SDOperand Num = DAG.getConstant(NumElements, MVT::i32);
       SDOperand Typ = DAG.getValueType(PVT);
@@ -777,11 +784,14 @@
     const PackedType *PTy = cast<PackedType>(Ty);
     unsigned NumElements = PTy->getNumElements();
     MVT::ValueType PVT = TLI.getValueType(PTy->getElementType());
+    MVT::ValueType TVT = MVT::getVectorType(PVT, NumElements);
     
     // Immediately scalarize packed types containing only one element, so that
     // the Legalize pass does not have to deal with them.
     if (NumElements == 1) {
       L = DAG.getLoad(PVT, Root, Ptr, DAG.getSrcValue(I.getOperand(0)));
+    } else if (TVT != MVT::Other && TLI.isTypeLegal(TVT)) {
+      L = DAG.getLoad(TVT, Root, Ptr, DAG.getSrcValue(I.getOperand(0)));
     } else {
       L = DAG.getVecLoad(NumElements, PVT, Root, Ptr, 
                          DAG.getSrcValue(I.getOperand(0)));





From natebegeman at mac.com  Wed Nov 30 02:22:41 2005
From: natebegeman at mac.com (Nate Begeman)
Date: Wed, 30 Nov 2005 02:22:41 -0600
Subject: [llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp 
Message-ID: <200511300822.CAA15120@zion.cs.uiuc.edu>



Changes in directory llvm/lib/Target/PowerPC:

PPCISelDAGToDAG.cpp updated: 1.130 -> 1.131
---
Log message:

First chunk of actually generating vector code for packed types.  These
changes allow us to generate the following code:

_foo:
        li r2, 0
        lvx v0, r2, r3
        vaddfp v0, v0, v0
        stvx v0, r2, r3
        blr

for this llvm:

void %foo(<4 x float>* %a) {
entry:
        %tmp1 = load <4 x float>* %a
        %tmp2 = add <4 x float> %tmp1, %tmp1
        store <4 x float> %tmp2, <4 x float>* %a
        ret void
}


---
Diffs of the changes:  (+51 -11)

 PPCISelDAGToDAG.cpp |   62 ++++++++++++++++++++++++++++++++++++++++++----------
 1 files changed, 51 insertions(+), 11 deletions(-)


Index: llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
diff -u llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp:1.130 llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp:1.131
--- llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp:1.130	Thu Nov 17 12:26:56 2005
+++ llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp	Wed Nov 30 02:22:07 2005
@@ -73,6 +73,11 @@
     /// load/store instruction, and return true if it should be an indexed [r+r]
     /// operation.
     bool SelectAddr(SDOperand Addr, SDOperand &Op1, SDOperand &Op2);
+    
+    /// SelectAddrIndexed - Given the specified addressed, force it to be
+    /// represented as an indexed [r+r] operation, rather than possibly
+    /// returning [r+imm] as SelectAddr may.
+    void SelectAddrIndexed(SDOperand Addr, SDOperand &Op1, SDOperand &Op2);
 
     SDOperand BuildSDIVSequence(SDNode *N);
     SDOperand BuildUDIVSequence(SDNode *N);
@@ -428,7 +433,7 @@
     }
   }
 
- if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(Addr)) {
+  if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(Addr)) {
     Op1 = getI32Imm(0);
     Op2 = CurDAG->getTargetFrameIndex(FI->getIndex(), MVT::i32);
     return false;
@@ -445,6 +450,26 @@
   return false;
 }
 
+/// SelectAddrIndexed - Given the specified addressed, force it to be
+/// represented as an indexed [r+r] operation, rather than possibly
+/// returning [r+imm] as SelectAddr may.
+void PPCDAGToDAGISel::SelectAddrIndexed(SDOperand Addr, SDOperand &Op1, 
+                                        SDOperand &Op2) {
+  if (Addr.getOpcode() == ISD::ADD) {
+    Op1 = Select(Addr.getOperand(0));
+    Op2 = Select(Addr.getOperand(1));
+    return;
+  }
+  
+  if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(Addr)) {
+    Op1 = CurDAG->getTargetNode(PPC::LI, MVT::i32, getI32Imm(0));
+    Op2 = CurDAG->getTargetFrameIndex(FI->getIndex(), MVT::i32);
+    return;
+  }
+  Op1 = CurDAG->getTargetNode(PPC::LI, MVT::i32, getI32Imm(0));
+  Op2 = Select(Addr);
+}
+
 /// SelectCC - Select a comparison of the specified values with the specified
 /// condition code, returning the CR# of the expression.
 SDOperand PPCDAGToDAGISel::SelectCC(SDOperand LHS, SDOperand RHS,
@@ -916,9 +941,8 @@
       }
     }
     
-    CurDAG->SelectNodeTo(N, Ty == MVT::f64 ? PPC::FADD : PPC::FADDS, Ty,
-                         Select(N->getOperand(0)), Select(N->getOperand(1)));
-    return SDOperand(N, 0);
+    // Other cases are autogenerated.
+    break;
   }
   case ISD::FSUB: {
     MVT::ValueType Ty = N->getValueType(0);
@@ -942,10 +966,9 @@
         return SDOperand(N, 0);
       }
     }
-    CurDAG->SelectNodeTo(N, Ty == MVT::f64 ? PPC::FSUB : PPC::FSUBS, Ty,
-                         Select(N->getOperand(0)),
-                         Select(N->getOperand(1)));
-    return SDOperand(N, 0);
+
+    // Other cases are autogenerated.
+    break;
   }
   case ISD::SDIV: {
     // FIXME: since this depends on the setting of the carry flag from the srawi
@@ -1074,10 +1097,17 @@
   case ISD::ZEXTLOAD:
   case ISD::SEXTLOAD: {
     SDOperand Op1, Op2;
-    bool isIdx = SelectAddr(N->getOperand(1), Op1, Op2);
-
+    // If this is a vector load, then force this to be indexed addressing, since
+    // altivec does not have immediate offsets for loads.
+    bool isIdx = true;
+    if (N->getOpcode() == ISD::LOAD && MVT::isVector(N->getValueType(0))) { 
+      SelectAddrIndexed(N->getOperand(1), Op1, Op2);
+    } else {
+      isIdx = SelectAddr(N->getOperand(1), Op1, Op2);
+    }
     MVT::ValueType TypeBeingLoaded = (N->getOpcode() == ISD::LOAD) ?
       N->getValueType(0) : cast<VTSDNode>(N->getOperand(3))->getVT();
+
     unsigned Opc;
     switch (TypeBeingLoaded) {
     default: N->dump(); assert(0 && "Cannot load this type!");
@@ -1093,6 +1123,7 @@
     case MVT::i32: Opc = isIdx ? PPC::LWZX : PPC::LWZ; break;
     case MVT::f32: Opc = isIdx ? PPC::LFSX : PPC::LFS; break;
     case MVT::f64: Opc = isIdx ? PPC::LFDX : PPC::LFD; break;
+    case MVT::v4f32: Opc = PPC::LVX; break;
     }
 
     // If this is an f32 -> f64 load, emit the f32 load, then use an 'extending
@@ -1119,7 +1150,15 @@
   case ISD::TRUNCSTORE:
   case ISD::STORE: {
     SDOperand AddrOp1, AddrOp2;
-    bool isIdx = SelectAddr(N->getOperand(2), AddrOp1, AddrOp2);
+    // If this is a vector store, then force this to be indexed addressing,
+    // since altivec does not have immediate offsets for stores.
+    bool isIdx = true;
+    if (N->getOpcode() == ISD::STORE && 
+        MVT::isVector(N->getOperand(1).getValueType())) {
+      SelectAddrIndexed(N->getOperand(2), AddrOp1, AddrOp2);
+    } else {
+      isIdx = SelectAddr(N->getOperand(2), AddrOp1, AddrOp2);
+    }
 
     unsigned Opc;
     if (N->getOpcode() == ISD::STORE) {
@@ -1128,6 +1167,7 @@
       case MVT::i32: Opc = isIdx ? PPC::STWX  : PPC::STW; break;
       case MVT::f64: Opc = isIdx ? PPC::STFDX : PPC::STFD; break;
       case MVT::f32: Opc = isIdx ? PPC::STFSX : PPC::STFS; break;
+      case MVT::v4f32: Opc = PPC::STVX;
       }
     } else { //ISD::TRUNCSTORE
       switch(cast<VTSDNode>(N->getOperand(4))->getVT()) {





From natebegeman at mac.com  Wed Nov 30 02:22:41 2005
From: natebegeman at mac.com (Nate Begeman)
Date: Wed, 30 Nov 2005 02:22:41 -0600
Subject: [llvm-commits] CVS: llvm/include/llvm/CodeGen/ValueTypes.h 
Message-ID: <200511300822.CAA15121@zion.cs.uiuc.edu>



Changes in directory llvm/include/llvm/CodeGen:

ValueTypes.h updated: 1.14 -> 1.15
---
Log message:

First chunk of actually generating vector code for packed types.  These
changes allow us to generate the following code:

_foo:
        li r2, 0
        lvx v0, r2, r3
        vaddfp v0, v0, v0
        stvx v0, r2, r3
        blr

for this llvm:

void %foo(<4 x float>* %a) {
entry:
        %tmp1 = load <4 x float>* %a
        %tmp2 = add <4 x float> %tmp1, %tmp1
        store <4 x float> %tmp2, <4 x float>* %a
        ret void
}


---
Diffs of the changes:  (+17 -4)

 ValueTypes.h |   21 +++++++++++++++++----
 1 files changed, 17 insertions(+), 4 deletions(-)


Index: llvm/include/llvm/CodeGen/ValueTypes.h
diff -u llvm/include/llvm/CodeGen/ValueTypes.h:1.14 llvm/include/llvm/CodeGen/ValueTypes.h:1.15
--- llvm/include/llvm/CodeGen/ValueTypes.h:1.14	Mon Nov 28 23:45:28 2005
+++ llvm/include/llvm/CodeGen/ValueTypes.h	Wed Nov 30 02:22:02 2005
@@ -45,10 +45,8 @@
     isVoid         =  12,   // This has no value
     
     Vector         =  13,   // This is an abstract vector type, which will
-                            // be refined into a target vector type, or
-                            // scalarized.
-
-                            // These are 128 bit vectors of varying packed types
+                            // be expanded into a target vector type, or scalars
+                            // if no matching vector type is available.
     v16i8          =  14,   // 16 x i8
     v8i16          =  15,   //  8 x i16
     v4i32          =  16,   //  4 x i32
@@ -70,6 +68,21 @@
     return (VT >= v16i8 && VT <= v2f64);
   }
 
+  /// getVectorType - Returns the ValueType that represents a vector NumElements
+  /// in length, where each element is of type VT.  If there is no ValueType
+  /// that represents this vector, a ValueType of Other is returned.
+  ///
+  static inline ValueType getVectorType(ValueType VT, unsigned NumElements) {
+    switch (VT) {
+    default: 
+      break;
+    case MVT::f32:
+      if (NumElements == 4) return MVT::v4f32;
+      break;
+    }
+    return MVT::Other;
+  }
+  
   static inline unsigned getSizeInBits(ValueType VT) {
     switch (VT) {
     default: assert(0 && "ValueType has no known size!");





From alenhar2 at cs.uiuc.edu  Wed Nov 30 10:10:48 2005
From: alenhar2 at cs.uiuc.edu (Andrew Lenharth)
Date: Wed, 30 Nov 2005 10:10:48 -0600
Subject: [llvm-commits] CVS: llvm/lib/Target/Alpha/AlphaISelDAGToDAG.cpp
	AlphaISelLowering.cpp AlphaISelLowering.h
	AlphaISelPattern.cpp AlphaInstrInfo.td 
Message-ID: <200511301610.KAA28430@zion.cs.uiuc.edu>



Changes in directory llvm/lib/Target/Alpha:

AlphaISelDAGToDAG.cpp updated: 1.7 -> 1.8
AlphaISelLowering.cpp updated: 1.10 -> 1.11
AlphaISelLowering.h updated: 1.4 -> 1.5
AlphaISelPattern.cpp updated: 1.189 -> 1.190
AlphaInstrInfo.td updated: 1.74 -> 1.75
---
Log message:

FPSelect and more custom lowering

---
Diffs of the changes:  (+69 -25)

 AlphaISelDAGToDAG.cpp |   29 ++++++++++++++++++++++++++++-
 AlphaISelLowering.cpp |   27 +++++++++++++++++++++++++--
 AlphaISelLowering.h   |    2 +-
 AlphaISelPattern.cpp  |   28 ++++++++--------------------
 AlphaInstrInfo.td     |    8 +++++++-
 5 files changed, 69 insertions(+), 25 deletions(-)


Index: llvm/lib/Target/Alpha/AlphaISelDAGToDAG.cpp
diff -u llvm/lib/Target/Alpha/AlphaISelDAGToDAG.cpp:1.7 llvm/lib/Target/Alpha/AlphaISelDAGToDAG.cpp:1.8
--- llvm/lib/Target/Alpha/AlphaISelDAGToDAG.cpp:1.7	Wed Nov 30 01:19:56 2005
+++ llvm/lib/Target/Alpha/AlphaISelDAGToDAG.cpp	Wed Nov 30 10:10:29 2005
@@ -368,8 +368,35 @@
       return FP;
     }
     break;
+
+  case ISD::SELECT:
+    if (MVT::isFloatingPoint(N->getValueType(0))) {
+      //move int to fp
+      SDOperand LD,
+        cond = Select(N->getOperand(0)),
+        TV = Select(N->getOperand(1)),
+        FV = Select(N->getOperand(2));
+      
+      if (AlphaLowering.hasITOF()) {
+        LD = CurDAG->getNode(AlphaISD::ITOFT_, MVT::f64, cond);
+      } else {
+        int FrameIdx =
+          CurDAG->getMachineFunction().getFrameInfo()->CreateStackObject(8, 8);
+        SDOperand FI = CurDAG->getFrameIndex(FrameIdx, MVT::i64);
+        SDOperand ST = CurDAG->getTargetNode(Alpha::STQ, MVT::Other, 
+                                             cond, FI, CurDAG->getRegister(Alpha::R31, MVT::i64));
+        LD = CurDAG->getTargetNode(Alpha::LDT, MVT::f64, FI, 
+                                   CurDAG->getRegister(Alpha::R31, MVT::i64),
+                                   ST);
+      }
+      SDOperand FP = CurDAG->getTargetNode(Alpha::FCMOVEQ, MVT::f64, TV, FV, LD);
+      return FP;
+    }
+    break;
+
+
   }
-  
+
   return SelectCode(Op);
 }
 


Index: llvm/lib/Target/Alpha/AlphaISelLowering.cpp
diff -u llvm/lib/Target/Alpha/AlphaISelLowering.cpp:1.10 llvm/lib/Target/Alpha/AlphaISelLowering.cpp:1.11
--- llvm/lib/Target/Alpha/AlphaISelLowering.cpp:1.10	Wed Nov 30 01:19:56 2005
+++ llvm/lib/Target/Alpha/AlphaISelLowering.cpp	Wed Nov 30 10:10:29 2005
@@ -73,7 +73,9 @@
   
   setOperationAction(ISD::UINT_TO_FP, MVT::i64, Expand);
   setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom);
-  
+  setOperationAction(ISD::FP_TO_UINT, MVT::i64, Expand);
+  setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom);
+
   if (!TM.getSubtarget<AlphaSubtarget>().hasCT()) {
     setOperationAction(ISD::CTPOP    , MVT::i64  , Expand);
     setOperationAction(ISD::CTTZ     , MVT::i64  , Expand);
@@ -412,7 +414,28 @@
                                isDouble?MVT::f64:MVT::f32, LD);
     return FP;
   }
+  case ISD::FP_TO_SINT: {
+    bool isDouble = MVT::f64 == Op.getOperand(0).getValueType();
+    SDOperand src = Op.getOperand(0);
+
+    if (!isDouble) //Promote
+      src = DAG.getNode(ISD::FP_EXTEND, MVT::f64, src);
+    
+    src = DAG.getNode(AlphaISD::CVTTQ_, MVT::f64, src);
+
+    if (useITOF) {
+      return DAG.getNode(AlphaISD::FTOIT_, MVT::i64, src);
+    } else {
+      int FrameIdx =
+        DAG.getMachineFunction().getFrameInfo()->CreateStackObject(8, 8);
+      SDOperand FI = DAG.getFrameIndex(FrameIdx, MVT::i64);
+      SDOperand ST = DAG.getNode(ISD::STORE, MVT::Other, DAG.getEntryNode(),
+                                 src, FI, DAG.getSrcValue(0));
+      return DAG.getLoad(MVT::i64, ST, FI, DAG.getSrcValue(0));
+      }
+  }
+
   }
+
   return SDOperand();
 }
-


Index: llvm/lib/Target/Alpha/AlphaISelLowering.h
diff -u llvm/lib/Target/Alpha/AlphaISelLowering.h:1.4 llvm/lib/Target/Alpha/AlphaISelLowering.h:1.5
--- llvm/lib/Target/Alpha/AlphaISelLowering.h:1.4	Wed Nov 30 01:19:56 2005
+++ llvm/lib/Target/Alpha/AlphaISelLowering.h	Wed Nov 30 10:10:29 2005
@@ -26,7 +26,7 @@
       // Start the numbering where the builting ops and target ops leave off.
       FIRST_NUMBER = ISD::BUILTIN_OP_END+Alpha::INSTRUCTION_LIST_END,
       //These corrospond to the identical Instruction
-      ITOFT_, FTOIT_, CVTQT_, CVTQS_,
+      ITOFT_, FTOIT_, CVTQT_, CVTQS_, CVTTQ_,
     };
   }
 


Index: llvm/lib/Target/Alpha/AlphaISelPattern.cpp
diff -u llvm/lib/Target/Alpha/AlphaISelPattern.cpp:1.189 llvm/lib/Target/Alpha/AlphaISelPattern.cpp:1.190
--- llvm/lib/Target/Alpha/AlphaISelPattern.cpp:1.189	Wed Nov 30 01:19:56 2005
+++ llvm/lib/Target/Alpha/AlphaISelPattern.cpp	Wed Nov 30 10:10:29 2005
@@ -1297,26 +1297,6 @@
     return Result;
   }
 
-  case ISD::FP_TO_UINT:
-  case ISD::FP_TO_SINT:
-    {
-      assert (DestType == MVT::i64 && "only quads can be loaded to");
-      MVT::ValueType SrcType = N.getOperand(0).getValueType();
-      assert (SrcType == MVT::f32 || SrcType == MVT::f64);
-      Tmp1 = SelectExpr(N.getOperand(0));  // Get the operand register
-      if (SrcType == MVT::f32)
-        {
-          Tmp2 = MakeReg(MVT::f64);
-          BuildMI(BB, Alpha::CVTST, 1, Tmp2).addReg(Tmp1);
-          Tmp1 = Tmp2;
-        }
-      Tmp2 = MakeReg(MVT::f64);
-      BuildMI(BB, Alpha::CVTTQ, 1, Tmp2).addReg(Tmp1);
-      MoveFP2Int(Tmp2, Result, true);
-
-      return Result;
-    }
-
   case ISD::SELECT:
     if (isFP) {
       //Tmp1 = SelectExpr(N.getOperand(0)); //Cond
@@ -1567,10 +1547,18 @@
     BuildMI(BB, Alpha::CVTQS, 1, Result).addReg(SelectExpr(N.getOperand(0)));
     return Result;
 
+  case AlphaISD::CVTTQ_:
+    BuildMI(BB, Alpha::CVTTQ, 1, Result).addReg(SelectExpr(N.getOperand(0)));
+    return Result;
+
   case AlphaISD::ITOFT_:
     BuildMI(BB, Alpha::ITOFT, 1, Result).addReg(SelectExpr(N.getOperand(0)));
     return Result;
 
+  case AlphaISD::FTOIT_:
+    BuildMI(BB, Alpha::FTOIT, 1, Result).addReg(SelectExpr(N.getOperand(0)));
+    return Result;
+
   case ISD::AssertSext:
   case ISD::AssertZext:
     return SelectExpr(N.getOperand(0));


Index: llvm/lib/Target/Alpha/AlphaInstrInfo.td
diff -u llvm/lib/Target/Alpha/AlphaInstrInfo.td:1.74 llvm/lib/Target/Alpha/AlphaInstrInfo.td:1.75
--- llvm/lib/Target/Alpha/AlphaInstrInfo.td:1.74	Wed Nov 30 01:19:56 2005
+++ llvm/lib/Target/Alpha/AlphaInstrInfo.td	Wed Nov 30 10:10:29 2005
@@ -24,6 +24,7 @@
 def Alpha_ftoit : SDNode<"AlphaISD::FTOIT_", SDTFPToIntOp, []>;
 def Alpha_cvtqt : SDNode<"AlphaISD::CVTQT_", SDTFPUnaryOpUnC, []>;
 def Alpha_cvtqs : SDNode<"AlphaISD::CVTQS_", SDTFPUnaryOpUnC, []>;
+def Alpha_cvttq : SDNode<"AlphaISD::CVTTQ_", SDTFPUnaryOp, []>;
 
 
 //********************
@@ -575,7 +576,8 @@
 def CVTQT : FPForm<0x16, 0x7BE, "cvtqt/sui $RB,$RC",
         [(set F8RC:$RC, (Alpha_cvtqt F8RC:$RB))]>;
 let OperandList = (ops F8RC:$RC, F8RC:$RB), Fa = 31 in 
-def CVTTQ : FPForm<0x16, 0x52F, "cvttq/svc $RB,$RC",[]>; //Convert T_floating to quadword
+def CVTTQ : FPForm<0x16, 0x52F, "cvttq/svc $RB,$RC",
+        [(set F8RC:$RC, (Alpha_cvttq F8RC:$RB))]>;
 let OperandList = (ops F8RC:$RC, F4RC:$RB), Fa = 31 in 
 def CVTST : FPForm<0x16, 0x6AC, "cvtst/s $RB,$RC",
                    [(set F8RC:$RC, (fextend F4RC:$RB))]>;
@@ -686,3 +688,7 @@
           (CPYSNT F8RC:$RB, F8RC:$RB)>;
 def : Pat<(fneg F4RC:$RB),
           (CPYSNS F4RC:$RB, F4RC:$RB)>;
+//Yes, signed multiply high is ugly
+def : Pat<(mulhs GPRC:$RA, GPRC:$RB),
+          (SUBQ (UMULH GPRC:$RA, GPRC:$RB), (ADDQ (CMOVGE GPRC:$RB, R31, GPRC:$RA), 
+                                                 (CMOVGE GPRC:$RA, R31, GPRC:$RB)))>;





From alenhar2 at cs.uiuc.edu  Wed Nov 30 11:11:32 2005
From: alenhar2 at cs.uiuc.edu (Andrew Lenharth)
Date: Wed, 30 Nov 2005 11:11:32 -0600
Subject: [llvm-commits] CVS: llvm/lib/Target/Alpha/AlphaISelDAGToDAG.cpp
	AlphaISelLowering.cpp AlphaISelPattern.cpp AlphaInstrInfo.td 
Message-ID: <200511301711.LAA28872@zion.cs.uiuc.edu>



Changes in directory llvm/lib/Target/Alpha:

AlphaISelDAGToDAG.cpp updated: 1.8 -> 1.9
AlphaISelLowering.cpp updated: 1.11 -> 1.12
AlphaISelPattern.cpp updated: 1.190 -> 1.191
AlphaInstrInfo.td updated: 1.75 -> 1.76
---
Log message:

Make typesafe that which isn't: FCMOVxx

---
Diffs of the changes:  (+52 -26)

 AlphaISelDAGToDAG.cpp |   12 +++++++++---
 AlphaISelLowering.cpp |    3 +--
 AlphaISelPattern.cpp  |   32 +++++++++++++++++++++-----------
 AlphaInstrInfo.td     |   31 +++++++++++++++++++++----------
 4 files changed, 52 insertions(+), 26 deletions(-)


Index: llvm/lib/Target/Alpha/AlphaISelDAGToDAG.cpp
diff -u llvm/lib/Target/Alpha/AlphaISelDAGToDAG.cpp:1.8 llvm/lib/Target/Alpha/AlphaISelDAGToDAG.cpp:1.9
--- llvm/lib/Target/Alpha/AlphaISelDAGToDAG.cpp:1.8	Wed Nov 30 10:10:29 2005
+++ llvm/lib/Target/Alpha/AlphaISelDAGToDAG.cpp	Wed Nov 30 11:11:20 2005
@@ -335,6 +335,7 @@
       unsigned Opc = Alpha::WTF;
       ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(2))->get();
       bool rev = false;
+      bool isNE = false;
       switch(CC) {
       default: N->dump(); assert(0 && "Unknown FP comparison!");
       case ISD::SETEQ: Opc = Alpha::CMPTEQ; break;
@@ -342,13 +343,17 @@
       case ISD::SETLE: Opc = Alpha::CMPTLE; break;
       case ISD::SETGT: Opc = Alpha::CMPTLT; rev = true; break;
       case ISD::SETGE: Opc = Alpha::CMPTLE; rev = true; break;
-        //case ISD::SETNE: Opc = Alpha::CMPTEQ; inv = true; break;
+      case ISD::SETNE: Opc = Alpha::CMPTEQ; isNE = true; break;
       };
       SDOperand tmp1 = Select(N->getOperand(0)),
         tmp2 = Select(N->getOperand(1));
       SDOperand cmp = CurDAG->getTargetNode(Opc, MVT::f64, 
                                             rev?tmp2:tmp1,
                                             rev?tmp1:tmp2);
+      if (isNE) 
+        cmp = CurDAG->getTargetNode(Alpha::CMPTEQ, MVT::f64, cmp, 
+                                    CurDAG->getRegister(Alpha::F31, MVT::f64));
+      
       SDOperand LD;
       if (AlphaLowering.hasITOF()) {
         LD = CurDAG->getNode(AlphaISD::FTOIT_, MVT::i64, cmp);
@@ -372,6 +377,7 @@
   case ISD::SELECT:
     if (MVT::isFloatingPoint(N->getValueType(0))) {
       //move int to fp
+      bool isDouble = N->getValueType(0) == MVT::f64;
       SDOperand LD,
         cond = Select(N->getOperand(0)),
         TV = Select(N->getOperand(1)),
@@ -389,12 +395,12 @@
                                    CurDAG->getRegister(Alpha::R31, MVT::i64),
                                    ST);
       }
-      SDOperand FP = CurDAG->getTargetNode(Alpha::FCMOVEQ, MVT::f64, TV, FV, LD);
+      SDOperand FP = CurDAG->getTargetNode(isDouble?Alpha::FCMOVEQT:Alpha::FCMOVEQS,
+                                           MVT::f64, TV, FV, LD);
       return FP;
     }
     break;
 
-
   }
 
   return SelectCode(Op);


Index: llvm/lib/Target/Alpha/AlphaISelLowering.cpp
diff -u llvm/lib/Target/Alpha/AlphaISelLowering.cpp:1.11 llvm/lib/Target/Alpha/AlphaISelLowering.cpp:1.12
--- llvm/lib/Target/Alpha/AlphaISelLowering.cpp:1.11	Wed Nov 30 10:10:29 2005
+++ llvm/lib/Target/Alpha/AlphaISelLowering.cpp	Wed Nov 30 11:11:20 2005
@@ -98,8 +98,7 @@
   setOperationAction(ISD::FCOS , MVT::f32, Expand);
   setOperationAction(ISD::FSQRT, MVT::f32, Expand);
 
-  //Doesn't work yet
-  setOperationAction(ISD::SETCC, MVT::f32,   Promote);
+  setOperationAction(ISD::SETCC, MVT::f32, Promote);
 
   // We don't have line number support yet.
   setOperationAction(ISD::LOCATION, MVT::Other, Expand);


Index: llvm/lib/Target/Alpha/AlphaISelPattern.cpp
diff -u llvm/lib/Target/Alpha/AlphaISelPattern.cpp:1.190 llvm/lib/Target/Alpha/AlphaISelPattern.cpp:1.191
--- llvm/lib/Target/Alpha/AlphaISelPattern.cpp:1.190	Wed Nov 30 10:10:29 2005
+++ llvm/lib/Target/Alpha/AlphaISelPattern.cpp	Wed Nov 30 11:11:20 2005
@@ -1317,7 +1317,7 @@
 
         bool invTest = false;
         unsigned Tmp3;
-
+        bool isD = CC.getOperand(0).getValueType() == MVT::f64;
         ConstantFPSDNode *CN;
         if ((CN = dyn_cast<ConstantFPSDNode>(CC.getOperand(1)))
             && (CN->isExactlyValue(+0.0) || CN->isExactlyValue(-0.0)))
@@ -1332,21 +1332,31 @@
         {
           unsigned Tmp1 = SelectExpr(CC.getOperand(0));
           unsigned Tmp2 = SelectExpr(CC.getOperand(1));
-          bool isD = CC.getOperand(0).getValueType() == MVT::f64;
           Tmp3 = MakeReg(isD ? MVT::f64 : MVT::f32);
           BuildMI(BB, isD ? Alpha::SUBT : Alpha::SUBS, 2, Tmp3)
             .addReg(Tmp1).addReg(Tmp2);
         }
 
-        switch (cast<CondCodeSDNode>(CC.getOperand(2))->get()) {
-        default: CC.Val->dump(); assert(0 && "Unknown FP comparison!");
-        case ISD::SETEQ: Opc = invTest ? Alpha::FCMOVNE : Alpha::FCMOVEQ; break;
-        case ISD::SETLT: Opc = invTest ? Alpha::FCMOVGT : Alpha::FCMOVLT; break;
-        case ISD::SETLE: Opc = invTest ? Alpha::FCMOVGE : Alpha::FCMOVLE; break;
-        case ISD::SETGT: Opc = invTest ? Alpha::FCMOVLT : Alpha::FCMOVGT; break;
-        case ISD::SETGE: Opc = invTest ? Alpha::FCMOVLE : Alpha::FCMOVGE; break;
-        case ISD::SETNE: Opc = invTest ? Alpha::FCMOVEQ : Alpha::FCMOVNE; break;
-        }
+        if(isD)
+          switch (cast<CondCodeSDNode>(CC.getOperand(2))->get()) {
+          default: CC.Val->dump(); assert(0 && "Unknown FP comparison!");
+          case ISD::SETEQ: Opc = invTest ? Alpha::FCMOVNET : Alpha::FCMOVEQT; break;
+          case ISD::SETLT: Opc = invTest ? Alpha::FCMOVGTT : Alpha::FCMOVLTT; break;
+          case ISD::SETLE: Opc = invTest ? Alpha::FCMOVGET : Alpha::FCMOVLET; break;
+          case ISD::SETGT: Opc = invTest ? Alpha::FCMOVLTT : Alpha::FCMOVGTT; break;
+          case ISD::SETGE: Opc = invTest ? Alpha::FCMOVLET : Alpha::FCMOVGET; break;
+          case ISD::SETNE: Opc = invTest ? Alpha::FCMOVEQT : Alpha::FCMOVNET; break;
+          }
+        else
+          switch (cast<CondCodeSDNode>(CC.getOperand(2))->get()) {
+          default: CC.Val->dump(); assert(0 && "Unknown FP comparison!");
+          case ISD::SETEQ: Opc = invTest ? Alpha::FCMOVNES : Alpha::FCMOVEQS; break;
+          case ISD::SETLT: Opc = invTest ? Alpha::FCMOVGTS : Alpha::FCMOVLTS; break;
+          case ISD::SETLE: Opc = invTest ? Alpha::FCMOVGES : Alpha::FCMOVLES; break;
+          case ISD::SETGT: Opc = invTest ? Alpha::FCMOVLTS : Alpha::FCMOVGTS; break;
+          case ISD::SETGE: Opc = invTest ? Alpha::FCMOVLES : Alpha::FCMOVGES; break;
+          case ISD::SETNE: Opc = invTest ? Alpha::FCMOVEQS : Alpha::FCMOVNES; break;
+          }
         BuildMI(BB, Opc, 3, Result).addReg(FV).addReg(TV).addReg(Tmp3);
         return Result;
       }


Index: llvm/lib/Target/Alpha/AlphaInstrInfo.td
diff -u llvm/lib/Target/Alpha/AlphaInstrInfo.td:1.75 llvm/lib/Target/Alpha/AlphaInstrInfo.td:1.76
--- llvm/lib/Target/Alpha/AlphaInstrInfo.td:1.75	Wed Nov 30 10:10:29 2005
+++ llvm/lib/Target/Alpha/AlphaInstrInfo.td	Wed Nov 30 11:11:20 2005
@@ -162,16 +162,6 @@
 def : Pat<(select GPRC:$which, GPRC:$src1, GPRC:$src2),
       (CMOVEQ GPRC:$src1, GPRC:$src2, GPRC:$which)>;
 
-//conditional moves, fp
-let OperandList = (ops F8RC:$RDEST, F8RC:$RSRC2, F8RC:$RSRC, F8RC:$RCOND),
-    isTwoAddress = 1 in {
-def FCMOVEQ : FPForm<0x17, 0x02A, "fcmoveq $RCOND,$RSRC,$RDEST",[]>; //FCMOVE if = zero
-def FCMOVGE : FPForm<0x17, 0x02D, "fcmovge $RCOND,$RSRC,$RDEST",[]>; //FCMOVE if >= zero
-def FCMOVGT : FPForm<0x17, 0x02F, "fcmovgt $RCOND,$RSRC,$RDEST",[]>; //FCMOVE if > zero
-def FCMOVLE : FPForm<0x17, 0x02E, "fcmovle $RCOND,$RSRC,$RDEST",[]>; //FCMOVE if <= zero
-def FCMOVLT : FPForm<0x17, 0x02C, "fcmovlt $RCOND,$RSRC,$RDEST",[]>; // FCMOVE if < zero
-def FCMOVNE : FPForm<0x17, 0x02B, "fcmovne $RCOND,$RSRC,$RDEST",[]>; //FCMOVE if != zero
-}
 
 def ADDL     : OForm< 0x10, 0x00, "addl $RA,$RB,$RC",
                       [(set GPRC:$RC, (intop (add GPRC:$RA, GPRC:$RB)))]>;
@@ -555,6 +545,27 @@
 }
 //TODO: Add lots more FP patterns
 
+//conditional moves, floats
+let OperandList = (ops F4RC:$RDEST, F4RC:$RSRC2, F4RC:$RSRC, F8RC:$RCOND),
+    isTwoAddress = 1 in {
+def FCMOVEQS : FPForm<0x17, 0x02A, "fcmoveq $RCOND,$RSRC,$RDEST",[]>; //FCMOVE if = zero
+def FCMOVGES : FPForm<0x17, 0x02D, "fcmovge $RCOND,$RSRC,$RDEST",[]>; //FCMOVE if >= zero
+def FCMOVGTS : FPForm<0x17, 0x02F, "fcmovgt $RCOND,$RSRC,$RDEST",[]>; //FCMOVE if > zero
+def FCMOVLES : FPForm<0x17, 0x02E, "fcmovle $RCOND,$RSRC,$RDEST",[]>; //FCMOVE if <= zero
+def FCMOVLTS : FPForm<0x17, 0x02C, "fcmovlt $RCOND,$RSRC,$RDEST",[]>; // FCMOVE if < zero
+def FCMOVNES : FPForm<0x17, 0x02B, "fcmovne $RCOND,$RSRC,$RDEST",[]>; //FCMOVE if != zero
+}
+//conditional moves, doubles
+let OperandList = (ops F8RC:$RDEST, F8RC:$RSRC2, F8RC:$RSRC, F8RC:$RCOND),
+    isTwoAddress = 1 in {
+def FCMOVEQT : FPForm<0x17, 0x02A, "fcmoveq $RCOND,$RSRC,$RDEST",[]>; //FCMOVE if = zero
+def FCMOVGET : FPForm<0x17, 0x02D, "fcmovge $RCOND,$RSRC,$RDEST",[]>; //FCMOVE if >= zero
+def FCMOVGTT : FPForm<0x17, 0x02F, "fcmovgt $RCOND,$RSRC,$RDEST",[]>; //FCMOVE if > zero
+def FCMOVLET : FPForm<0x17, 0x02E, "fcmovle $RCOND,$RSRC,$RDEST",[]>; //FCMOVE if <= zero
+def FCMOVLTT : FPForm<0x17, 0x02C, "fcmovlt $RCOND,$RSRC,$RDEST",[]>; // FCMOVE if < zero
+def FCMOVNET : FPForm<0x17, 0x02B, "fcmovne $RCOND,$RSRC,$RDEST",[]>; //FCMOVE if != zero
+}
+
 
 
 let OperandList = (ops GPRC:$RC, F4RC:$RA), Fb = 31 in 





From alenhar2 at cs.uiuc.edu  Wed Nov 30 11:12:38 2005
From: alenhar2 at cs.uiuc.edu (Andrew Lenharth)
Date: Wed, 30 Nov 2005 11:12:38 -0600
Subject: [llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp 
Message-ID: <200511301712.LAA28900@zion.cs.uiuc.edu>



Changes in directory llvm/lib/CodeGen/SelectionDAG:

LegalizeDAG.cpp updated: 1.218 -> 1.219
---
Log message:

At long last, you can say that f32 isn't supported for setcc

---
Diffs of the changes:  (+28 -1)

 LegalizeDAG.cpp |   29 ++++++++++++++++++++++++++++-
 1 files changed, 28 insertions(+), 1 deletion(-)


Index: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.218 llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.219
--- llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.218	Wed Nov 30 00:43:03 2005
+++ llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp	Wed Nov 30 11:12:26 2005
@@ -1438,10 +1438,37 @@
     default: 
       assert(0 && "Cannot handle this action for SETCC yet!");
       break;
-    case TargetLowering::Promote:
+    case TargetLowering::Promote: {
+      // First step, figure out the appropriate operation to use.
+      // Allow SETCC to not be supported for all legal data types
+      // Mostly this targets FP
+      MVT::ValueType NewInTy = Node->getOperand(0).getValueType();
+      MVT::ValueType OldVT = NewInTy;
+
+      // Scan for the appropriate larger type to use.
+      while (1) {
+        NewInTy = (MVT::ValueType)(NewInTy+1);
+
+        assert(MVT::isInteger(NewInTy) == MVT::isInteger(OldVT) &&
+               "Fell off of the edge of the integer world");
+        assert(MVT::isFloatingPoint(NewInTy) == MVT::isFloatingPoint(OldVT) &&
+               "Fell off of the edge of the floating point world");
+          
+        // If the target supports SETCC of this type, use it.
+        if (TLI.getOperationAction(ISD::SETCC, NewInTy) == TargetLowering::Legal)
+          break;
+      }
+      if (MVT::isInteger(NewInTy))
+        assert(0 && "Cannot promote Legal Integer SETCC yet");
+      else {
+        Tmp1 = DAG.getNode(ISD::FP_EXTEND, NewInTy, Tmp1);
+        Tmp2 = DAG.getNode(ISD::FP_EXTEND, NewInTy, Tmp2);
+      }
+      
       Result = DAG.getNode(ISD::SETCC, Node->getValueType(0), Tmp1, Tmp2,
                            Node->getOperand(2));
       break;
+    }
     case TargetLowering::Legal:
       if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1))
         Result = DAG.getNode(ISD::SETCC, Node->getValueType(0), Tmp1, Tmp2,





From alenhar2 at cs.uiuc.edu  Wed Nov 30 11:14:23 2005
From: alenhar2 at cs.uiuc.edu (Andrew Lenharth)
Date: Wed, 30 Nov 2005 11:14:23 -0600
Subject: [llvm-commits] CVS: llvm/lib/Target/Alpha/AlphaISelPattern.cpp 
Message-ID: <200511301714.LAA28931@zion.cs.uiuc.edu>



Changes in directory llvm/lib/Target/Alpha:

AlphaISelPattern.cpp updated: 1.191 -> 1.192
---
Log message:

remove redundant code

---
Diffs of the changes:  (+2 -14)

 AlphaISelPattern.cpp |   16 ++--------------
 1 files changed, 2 insertions(+), 14 deletions(-)


Index: llvm/lib/Target/Alpha/AlphaISelPattern.cpp
diff -u llvm/lib/Target/Alpha/AlphaISelPattern.cpp:1.191 llvm/lib/Target/Alpha/AlphaISelPattern.cpp:1.192
--- llvm/lib/Target/Alpha/AlphaISelPattern.cpp:1.191	Wed Nov 30 11:11:20 2005
+++ llvm/lib/Target/Alpha/AlphaISelPattern.cpp	Wed Nov 30 11:14:11 2005
@@ -365,21 +365,9 @@
 
   //Can only compare doubles, and dag won't promote for me
   if (SetCC->getOperand(0).getValueType() == MVT::f32)
-    {
-      //assert(0 && "Setcc On float?\n");
-      std::cerr << "Setcc on float!\n";
-      Tmp3 = MakeReg(MVT::f64);
-      BuildMI(BB, Alpha::CVTST, 1, Tmp3).addReg(Tmp1);
-      Tmp1 = Tmp3;
-    }
+      assert(0 && "Setcc On float?\n");
   if (SetCC->getOperand(1).getValueType() == MVT::f32)
-    {
-      //assert (0 && "Setcc On float?\n");
-      std::cerr << "Setcc on float!\n";
-      Tmp3 = MakeReg(MVT::f64);
-      BuildMI(BB, Alpha::CVTST, 1, Tmp3).addReg(Tmp2);
-      Tmp2 = Tmp3;
-    }
+    assert (0 && "Setcc On float?\n");
 
   if (rev) std::swap(Tmp1, Tmp2);
   //do the comparison





From lattner at cs.uiuc.edu  Wed Nov 30 12:21:04 2005
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Wed, 30 Nov 2005 12:21:04 -0600
Subject: [llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp 
Message-ID: <200511301821.MAA29744@zion.cs.uiuc.edu>



Changes in directory llvm/lib/CodeGen/SelectionDAG:

SelectionDAG.cpp updated: 1.218 -> 1.219
---
Log message:

CALLSEQ_START/END nodes don't get memoized, do not add them in when 
replaceAllUses'ing.



---
Diffs of the changes:  (+4 -0)

 SelectionDAG.cpp |    4 ++++
 1 files changed, 4 insertions(+)


Index: llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp:1.218 llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp:1.219
--- llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp:1.218	Tue Nov 29 20:49:21 2005
+++ llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp	Wed Nov 30 12:20:52 2005
@@ -387,6 +387,10 @@
 ///
 SDNode *SelectionDAG::AddNonLeafNodeToCSEMaps(SDNode *N) {
   assert(N->getNumOperands() && "This is a leaf node!");
+  if (N->getOpcode() == ISD::CALLSEQ_START || 
+      N->getOpcode() == ISD::CALLSEQ_END)
+    return 0;
+  
   if (N->getOpcode() == ISD::LOAD) {
     SDNode *&L = Loads[std::make_pair(N->getOperand(1),
                                       std::make_pair(N->getOperand(0),





From natebegeman at mac.com  Wed Nov 30 12:37:26 2005
From: natebegeman at mac.com (Nate Begeman)
Date: Wed, 30 Nov 2005 12:37:26 -0600
Subject: [llvm-commits] CVS: llvm/utils/TableGen/Record.cpp 
Message-ID: <200511301837.MAA29832@zion.cs.uiuc.edu>



Changes in directory llvm/utils/TableGen:

Record.cpp updated: 1.47 -> 1.48
---
Log message:

Fix some copy and paste typos.


---
Diffs of the changes:  (+2 -2)

 Record.cpp |    4 ++--
 1 files changed, 2 insertions(+), 2 deletions(-)


Index: llvm/utils/TableGen/Record.cpp
diff -u llvm/utils/TableGen/Record.cpp:1.47 llvm/utils/TableGen/Record.cpp:1.48
--- llvm/utils/TableGen/Record.cpp:1.47	Fri Oct 28 17:49:02 2005
+++ llvm/utils/TableGen/Record.cpp	Wed Nov 30 12:37:14 2005
@@ -741,7 +741,7 @@
   if (IntInit *II = dynamic_cast<IntInit*>(R->getValue()))
     return II->getValue();
   throw "Record `" + getName() + "', field `" + FieldName +
-        "' does not have a list initializer!";
+        "' does not have an int initializer!";
 }
 
 /// getValueAsDef - This method looks up the specified field and returns its
@@ -757,7 +757,7 @@
   if (DefInit *DI = dynamic_cast<DefInit*>(R->getValue()))
     return DI->getDef();
   throw "Record `" + getName() + "', field `" + FieldName +
-        "' does not have a list initializer!";
+        "' does not have a def initializer!";
 }
 
 /// getValueAsBit - This method looks up the specified field and returns its





From natebegeman at mac.com  Wed Nov 30 12:54:48 2005
From: natebegeman at mac.com (Nate Begeman)
Date: Wed, 30 Nov 2005 12:54:48 -0600
Subject: [llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp 
Message-ID: <200511301854.MAA29978@zion.cs.uiuc.edu>



Changes in directory llvm/lib/Target/PowerPC:

PPCAsmPrinter.cpp updated: 1.121 -> 1.122
---
Log message:

No longer track value types for asm printer operands, and remove them as
an argument to every operand printing function.  Requires some slight
tweaks to x86, the only user.


---
Diffs of the changes:  (+17 -30)

 PPCAsmPrinter.cpp |   47 +++++++++++++++++------------------------------
 1 files changed, 17 insertions(+), 30 deletions(-)


Index: llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp
diff -u llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp:1.121 llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp:1.122
--- llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp:1.121	Mon Nov 21 02:26:15 2005
+++ llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp	Wed Nov 30 12:54:35 2005
@@ -27,7 +27,6 @@
 #include "llvm/CodeGen/AsmPrinter.h"
 #include "llvm/CodeGen/MachineFunctionPass.h"
 #include "llvm/CodeGen/MachineInstr.h"
-#include "llvm/CodeGen/ValueTypes.h"
 #include "llvm/Support/Mangler.h"
 #include "llvm/Support/MathExtras.h"
 #include "llvm/Support/CommandLine.h"
@@ -81,7 +80,7 @@
     void printMachineInstruction(const MachineInstr *MI);
     void printOp(const MachineOperand &MO);
 
-    void printOperand(const MachineInstr *MI, unsigned OpNo, MVT::ValueType VT){
+    void printOperand(const MachineInstr *MI, unsigned OpNo){
       const MachineOperand &MO = MI->getOperand(OpNo);
       if (MO.getType() == MachineOperand::MO_MachineRegister) {
         assert(MRegisterInfo::isPhysicalRegister(MO.getReg())&&"Not physreg??");
@@ -93,32 +92,26 @@
       }
     }
 
-    void printU5ImmOperand(const MachineInstr *MI, unsigned OpNo,
-                            MVT::ValueType VT) {
+    void printU5ImmOperand(const MachineInstr *MI, unsigned OpNo) {
       unsigned char value = MI->getOperand(OpNo).getImmedValue();
       assert(value <= 31 && "Invalid u5imm argument!");
       O << (unsigned int)value;
     }
-    void printU6ImmOperand(const MachineInstr *MI, unsigned OpNo,
-                            MVT::ValueType VT) {
+    void printU6ImmOperand(const MachineInstr *MI, unsigned OpNo) {
       unsigned char value = MI->getOperand(OpNo).getImmedValue();
       assert(value <= 63 && "Invalid u6imm argument!");
       O << (unsigned int)value;
     }
-    void printS16ImmOperand(const MachineInstr *MI, unsigned OpNo,
-                            MVT::ValueType VT) {
+    void printS16ImmOperand(const MachineInstr *MI, unsigned OpNo) {
       O << (short)MI->getOperand(OpNo).getImmedValue();
     }
-    void printU16ImmOperand(const MachineInstr *MI, unsigned OpNo,
-                            MVT::ValueType VT) {
+    void printU16ImmOperand(const MachineInstr *MI, unsigned OpNo) {
       O << (unsigned short)MI->getOperand(OpNo).getImmedValue();
     }
-    void printS16X4ImmOperand(const MachineInstr *MI, unsigned OpNo,
-                              MVT::ValueType VT) {
+    void printS16X4ImmOperand(const MachineInstr *MI, unsigned OpNo) {
       O << (short)MI->getOperand(OpNo).getImmedValue()*4;
     }
-    void printBranchOperand(const MachineInstr *MI, unsigned OpNo,
-                            MVT::ValueType VT) {
+    void printBranchOperand(const MachineInstr *MI, unsigned OpNo) {
       // Branches can take an immediate operand.  This is used by the branch
       // selection pass to print $+8, an eight byte displacement from the PC.
       if (MI->getOperand(OpNo).isImmediate()) {
@@ -127,8 +120,7 @@
         printOp(MI->getOperand(OpNo));
       }
     }
-    void printCallOperand(const MachineInstr *MI, unsigned OpNo,
-                          MVT::ValueType VT) {
+    void printCallOperand(const MachineInstr *MI, unsigned OpNo) {
       const MachineOperand &MO = MI->getOperand(OpNo);
       if (!PPCGenerateStaticCode) {
         if (MO.getType() == MachineOperand::MO_ExternalSymbol) {
@@ -149,20 +141,17 @@
       
       printOp(MI->getOperand(OpNo));
     }
-    void printAbsAddrOperand(const MachineInstr *MI, unsigned OpNo,
-                             MVT::ValueType VT) {
+    void printAbsAddrOperand(const MachineInstr *MI, unsigned OpNo) {
      O << (int)MI->getOperand(OpNo).getImmedValue()*4;
     }
-    void printPICLabel(const MachineInstr *MI, unsigned OpNo,
-                       MVT::ValueType VT) {
+    void printPICLabel(const MachineInstr *MI, unsigned OpNo) {
       // FIXME: should probably be converted to cout.width and cout.fill
       O << "\"L0000" << getFunctionNumber() << "$pb\"\n";
       O << "\"L0000" << getFunctionNumber() << "$pb\":";
     }
-    void printSymbolHi(const MachineInstr *MI, unsigned OpNo,
-                       MVT::ValueType VT) {
+    void printSymbolHi(const MachineInstr *MI, unsigned OpNo) {
       if (MI->getOperand(OpNo).isImmediate()) {
-        printS16ImmOperand(MI, OpNo, VT);
+        printS16ImmOperand(MI, OpNo);
       } else {
         O << "ha16(";
         printOp(MI->getOperand(OpNo));
@@ -172,10 +161,9 @@
           O << ')';
       }
     }
-    void printSymbolLo(const MachineInstr *MI, unsigned OpNo,
-                       MVT::ValueType VT) {
+    void printSymbolLo(const MachineInstr *MI, unsigned OpNo) {
       if (MI->getOperand(OpNo).isImmediate()) {
-        printS16ImmOperand(MI, OpNo, VT);
+        printS16ImmOperand(MI, OpNo);
       } else {
         O << "lo16(";
         printOp(MI->getOperand(OpNo));
@@ -185,8 +173,7 @@
           O << ')';
       }
     }
-    void printcrbitm(const MachineInstr *MI, unsigned OpNo,
-                       MVT::ValueType VT) {
+    void printcrbitm(const MachineInstr *MI, unsigned OpNo) {
       unsigned CCReg = MI->getOperand(OpNo).getReg();
       unsigned RegNo = enumRegToMachineReg(CCReg);
       O << (0x80 >> RegNo);
@@ -356,9 +343,9 @@
       SH = 32-SH;
     }
     if (FoundMnemonic) {
-      printOperand(MI, 0, MVT::i64);
+      printOperand(MI, 0);
       O << ", ";
-      printOperand(MI, 1, MVT::i64);
+      printOperand(MI, 1);
       O << ", " << (unsigned int)SH << "\n";
       return;
     }





From natebegeman at mac.com  Wed Nov 30 12:54:48 2005
From: natebegeman at mac.com (Nate Begeman)
Date: Wed, 30 Nov 2005 12:54:48 -0600
Subject: [llvm-commits] CVS: llvm/lib/Target/IA64/IA64AsmPrinter.cpp 
Message-ID: <200511301854.MAA29982@zion.cs.uiuc.edu>



Changes in directory llvm/lib/Target/IA64:

IA64AsmPrinter.cpp updated: 1.20 -> 1.21
---
Log message:

No longer track value types for asm printer operands, and remove them as
an argument to every operand printing function.  Requires some slight
tweaks to x86, the only user.


---
Diffs of the changes:  (+8 -16)

 IA64AsmPrinter.cpp |   24 ++++++++----------------
 1 files changed, 8 insertions(+), 16 deletions(-)


Index: llvm/lib/Target/IA64/IA64AsmPrinter.cpp
diff -u llvm/lib/Target/IA64/IA64AsmPrinter.cpp:1.20 llvm/lib/Target/IA64/IA64AsmPrinter.cpp:1.21
--- llvm/lib/Target/IA64/IA64AsmPrinter.cpp:1.20	Mon Nov 21 02:40:17 2005
+++ llvm/lib/Target/IA64/IA64AsmPrinter.cpp	Wed Nov 30 12:54:35 2005
@@ -23,7 +23,6 @@
 #include "llvm/Assembly/Writer.h"
 #include "llvm/CodeGen/AsmPrinter.h"
 #include "llvm/CodeGen/MachineFunctionPass.h"
-#include "llvm/CodeGen/ValueTypes.h"
 #include "llvm/Target/TargetMachine.h"
 #include "llvm/Support/Mangler.h"
 #include "llvm/ADT/Statistic.h"
@@ -65,7 +64,7 @@
     bool printInstruction(const MachineInstr *MI);
 
     // This method is used by the tablegen'erated instruction printer.
-    void printOperand(const MachineInstr *MI, unsigned OpNo, MVT::ValueType VT){
+    void printOperand(const MachineInstr *MI, unsigned OpNo){
       const MachineOperand &MO = MI->getOperand(OpNo);
       if (MO.getType() == MachineOperand::MO_MachineRegister) {
         assert(MRegisterInfo::isPhysicalRegister(MO.getReg())&&"Not physref??");
@@ -76,30 +75,25 @@
       }
     }
 
-    void printS8ImmOperand(const MachineInstr *MI, unsigned OpNo,
-                            MVT::ValueType VT) {
+    void printS8ImmOperand(const MachineInstr *MI, unsigned OpNo) {
       int val=(unsigned int)MI->getOperand(OpNo).getImmedValue();
       if(val>=128) val=val-256; // if negative, flip sign
       O << val;
     }
-    void printS14ImmOperand(const MachineInstr *MI, unsigned OpNo,
-                            MVT::ValueType VT) {
+    void printS14ImmOperand(const MachineInstr *MI, unsigned OpNo) {
       int val=(unsigned int)MI->getOperand(OpNo).getImmedValue();
       if(val>=8192) val=val-16384; // if negative, flip sign
       O << val;
     }
-    void printS22ImmOperand(const MachineInstr *MI, unsigned OpNo,
-                            MVT::ValueType VT) {
+    void printS22ImmOperand(const MachineInstr *MI, unsigned OpNo) {
       int val=(unsigned int)MI->getOperand(OpNo).getImmedValue();
       if(val>=2097152) val=val-4194304; // if negative, flip sign
       O << val;
     }
-    void printU64ImmOperand(const MachineInstr *MI, unsigned OpNo,
-                            MVT::ValueType VT) {
+    void printU64ImmOperand(const MachineInstr *MI, unsigned OpNo) {
       O << (uint64_t)MI->getOperand(OpNo).getImmedValue();
     }
-    void printS64ImmOperand(const MachineInstr *MI, unsigned OpNo,
-                            MVT::ValueType VT) {
+    void printS64ImmOperand(const MachineInstr *MI, unsigned OpNo) {
 // XXX : nasty hack to avoid GPREL22 "relocation truncated to fit" linker
 // errors - instead of add rX = @gprel(CPI<whatever>), r1;; we now
 // emit movl rX = @gprel(CPI<whatever);;
@@ -116,13 +110,11 @@
       }
     }
 
-    void printGlobalOperand(const MachineInstr *MI, unsigned OpNo,
-                          MVT::ValueType VT) {
+    void printGlobalOperand(const MachineInstr *MI, unsigned OpNo) {
       printOp(MI->getOperand(OpNo), false); // this is NOT a br.call instruction
     }
 
-    void printCallOperand(const MachineInstr *MI, unsigned OpNo,
-                          MVT::ValueType VT) {
+    void printCallOperand(const MachineInstr *MI, unsigned OpNo) {
       printOp(MI->getOperand(OpNo), true); // this is a br.call instruction
     }
 





From natebegeman at mac.com  Wed Nov 30 12:54:49 2005
From: natebegeman at mac.com (Nate Begeman)
Date: Wed, 30 Nov 2005 12:54:49 -0600
Subject: [llvm-commits] CVS: llvm/utils/TableGen/AsmWriterEmitter.cpp 
Message-ID: <200511301854.MAA30002@zion.cs.uiuc.edu>



Changes in directory llvm/utils/TableGen:

AsmWriterEmitter.cpp updated: 1.22 -> 1.23
---
Log message:

No longer track value types for asm printer operands, and remove them as
an argument to every operand printing function.  Requires some slight
tweaks to x86, the only user.


---
Diffs of the changes:  (+6 -12)

 AsmWriterEmitter.cpp |   18 ++++++------------
 1 files changed, 6 insertions(+), 12 deletions(-)


Index: llvm/utils/TableGen/AsmWriterEmitter.cpp
diff -u llvm/utils/TableGen/AsmWriterEmitter.cpp:1.22 llvm/utils/TableGen/AsmWriterEmitter.cpp:1.23
--- llvm/utils/TableGen/AsmWriterEmitter.cpp:1.22	Wed Jul 27 01:12:35 2005
+++ llvm/utils/TableGen/AsmWriterEmitter.cpp	Wed Nov 30 12:54:35 2005
@@ -38,21 +38,16 @@
     /// machine instruction.
     unsigned MIOpNo;
 
-    /// OpVT - For isMachineInstrOperand, this is the value type for the
-    /// operand.
-    MVT::ValueType OpVT;
-
     AsmWriterOperand(const std::string &LitStr)
-      : OperandType(isLiteralTextOperand),  Str(LitStr) {}
+      : OperandType(isLiteralTextOperand), Str(LitStr) {}
 
-    AsmWriterOperand(const std::string &Printer, unsigned OpNo,
-                     MVT::ValueType VT) : OperandType(isMachineInstrOperand),
-                                          Str(Printer), MIOpNo(OpNo), OpVT(VT){}
+    AsmWriterOperand(const std::string &Printer, unsigned OpNo) 
+      : OperandType(isMachineInstrOperand), Str(Printer), MIOpNo(OpNo) {}
 
     bool operator!=(const AsmWriterOperand &Other) const {
       if (OperandType != Other.OperandType || Str != Other.Str) return true;
       if (OperandType == isMachineInstrOperand)
-        return MIOpNo != Other.MIOpNo || OpVT != Other.OpVT;
+        return MIOpNo != Other.MIOpNo;
       return false;
     }
     bool operator==(const AsmWriterOperand &Other) const {
@@ -90,7 +85,7 @@
   if (OperandType == isLiteralTextOperand)
     OS << "O << \"" << Str << "\"; ";
   else
-    OS << Str << "(MI, " << MIOpNo << ", MVT::" << getEnumName(OpVT) << "); ";
+    OS << Str << "(MI, " << MIOpNo << "); ";
 }
 
 
@@ -204,8 +199,7 @@
         --MIOp;
       }
 
-      Operands.push_back(AsmWriterOperand(OpInfo.PrinterMethodName,
-                                          MIOp, OpInfo.Ty));
+      Operands.push_back(AsmWriterOperand(OpInfo.PrinterMethodName, MIOp));
       LastEmitted = VarEnd;
     }
   }





From natebegeman at mac.com  Wed Nov 30 12:54:49 2005
From: natebegeman at mac.com (Nate Begeman)
Date: Wed, 30 Nov 2005 12:54:49 -0600
Subject: [llvm-commits] CVS: llvm/lib/Target/Alpha/AlphaAsmPrinter.cpp 
Message-ID: <200511301854.MAA29998@zion.cs.uiuc.edu>



Changes in directory llvm/lib/Target/Alpha:

AlphaAsmPrinter.cpp updated: 1.26 -> 1.27
---
Log message:

No longer track value types for asm printer operands, and remove them as
an argument to every operand printing function.  Requires some slight
tweaks to x86, the only user.


---
Diffs of the changes:  (+2 -3)

 AlphaAsmPrinter.cpp |    5 ++---
 1 files changed, 2 insertions(+), 3 deletions(-)


Index: llvm/lib/Target/Alpha/AlphaAsmPrinter.cpp
diff -u llvm/lib/Target/Alpha/AlphaAsmPrinter.cpp:1.26 llvm/lib/Target/Alpha/AlphaAsmPrinter.cpp:1.27
--- llvm/lib/Target/Alpha/AlphaAsmPrinter.cpp:1.26	Mon Nov 21 02:29:17 2005
+++ llvm/lib/Target/Alpha/AlphaAsmPrinter.cpp	Wed Nov 30 12:54:34 2005
@@ -18,7 +18,6 @@
 #include "llvm/Module.h"
 #include "llvm/Type.h"
 #include "llvm/Assembly/Writer.h"
-#include "llvm/CodeGen/ValueTypes.h"
 #include "llvm/CodeGen/AsmPrinter.h"
 #include "llvm/Target/TargetMachine.h"
 #include "llvm/Support/Mangler.h"
@@ -54,7 +53,7 @@
     }
     bool printInstruction(const MachineInstr *MI);
     void printOp(const MachineOperand &MO, bool IsCallOp = false);
-    void printOperand(const MachineInstr *MI, int opNum, MVT::ValueType VT);
+    void printOperand(const MachineInstr *MI, int opNum);
     void printBaseOffsetPair (const MachineInstr *MI, int i, bool brackets=true);
     void printMachineInstruction(const MachineInstr *MI);
     bool runOnMachineFunction(MachineFunction &F);
@@ -75,7 +74,7 @@
 
 #include "AlphaGenAsmWriter.inc"
 
-void AlphaAsmPrinter::printOperand(const MachineInstr *MI, int opNum, MVT::ValueType VT)
+void AlphaAsmPrinter::printOperand(const MachineInstr *MI, int opNum)
 {
   const MachineOperand &MO = MI->getOperand(opNum);
   if (MO.getType() == MachineOperand::MO_MachineRegister) {





From natebegeman at mac.com  Wed Nov 30 12:54:49 2005
From: natebegeman at mac.com (Nate Begeman)
Date: Wed, 30 Nov 2005 12:54:49 -0600
Subject: [llvm-commits] CVS: llvm/lib/Target/X86/X86ATTAsmPrinter.cpp
	X86ATTAsmPrinter.h X86InstrInfo.td X86IntelAsmPrinter.cpp
	X86IntelAsmPrinter.h 
Message-ID: <200511301854.MAA29994@zion.cs.uiuc.edu>



Changes in directory llvm/lib/Target/X86:

X86ATTAsmPrinter.cpp updated: 1.16 -> 1.17
X86ATTAsmPrinter.h updated: 1.2 -> 1.3
X86InstrInfo.td updated: 1.143 -> 1.144
X86IntelAsmPrinter.cpp updated: 1.12 -> 1.13
X86IntelAsmPrinter.h updated: 1.2 -> 1.3
---
Log message:

No longer track value types for asm printer operands, and remove them as
an argument to every operand printing function.  Requires some slight
tweaks to x86, the only user.


---
Diffs of the changes:  (+65 -40)

 X86ATTAsmPrinter.cpp   |    3 +--
 X86ATTAsmPrinter.h     |   32 +++++++++++++++++++++++---------
 X86InstrInfo.td        |   22 +++++++++++-----------
 X86IntelAsmPrinter.cpp |    3 +--
 X86IntelAsmPrinter.h   |   45 +++++++++++++++++++++++++++++----------------
 5 files changed, 65 insertions(+), 40 deletions(-)


Index: llvm/lib/Target/X86/X86ATTAsmPrinter.cpp
diff -u llvm/lib/Target/X86/X86ATTAsmPrinter.cpp:1.16 llvm/lib/Target/X86/X86ATTAsmPrinter.cpp:1.17
--- llvm/lib/Target/X86/X86ATTAsmPrinter.cpp:1.16	Mon Nov 21 17:06:54 2005
+++ llvm/lib/Target/X86/X86ATTAsmPrinter.cpp	Wed Nov 30 12:54:35 2005
@@ -145,8 +145,7 @@
   }
 }
 
-void X86ATTAsmPrinter::printSSECC(const MachineInstr *MI, unsigned Op,
-                                  MVT::ValueType VT) {
+void X86ATTAsmPrinter::printSSECC(const MachineInstr *MI, unsigned Op) {
   unsigned char value = MI->getOperand(Op).getImmedValue();
   assert(value <= 7 && "Invalid ssecc argument!");
   switch (value) {


Index: llvm/lib/Target/X86/X86ATTAsmPrinter.h
diff -u llvm/lib/Target/X86/X86ATTAsmPrinter.h:1.2 llvm/lib/Target/X86/X86ATTAsmPrinter.h:1.3
--- llvm/lib/Target/X86/X86ATTAsmPrinter.h:1.2	Thu Jul 14 17:52:25 2005
+++ llvm/lib/Target/X86/X86ATTAsmPrinter.h	Wed Nov 30 12:54:35 2005
@@ -35,23 +35,37 @@
   bool printInstruction(const MachineInstr *MI);
 
   // This method is used by the tablegen'erated instruction printer.
-  void printOperand(const MachineInstr *MI, unsigned OpNo, MVT::ValueType VT){
+  void printOperand(const MachineInstr *MI, unsigned OpNo){
     printOp(MI->getOperand(OpNo));
   }
-
-  void printCallOperand(const MachineInstr *MI, unsigned OpNo,
-                        MVT::ValueType VT) {
+  void printCallOperand(const MachineInstr *MI, unsigned OpNo) {
     printOp(MI->getOperand(OpNo), true); // Don't print '$' prefix.
   }
-
-  void printMemoryOperand(const MachineInstr *MI, unsigned OpNo,
-                          MVT::ValueType VT) {
+  void printi8mem(const MachineInstr *MI, unsigned OpNo) {
     printMemReference(MI, OpNo);
   }
-
+  void printi16mem(const MachineInstr *MI, unsigned OpNo) {
+    printMemReference(MI, OpNo);
+  }
+  void printi32mem(const MachineInstr *MI, unsigned OpNo) {
+    printMemReference(MI, OpNo);
+  }
+  void printi64mem(const MachineInstr *MI, unsigned OpNo) {
+    printMemReference(MI, OpNo);
+  }
+  void printf32mem(const MachineInstr *MI, unsigned OpNo) {
+    printMemReference(MI, OpNo);
+  }
+  void printf64mem(const MachineInstr *MI, unsigned OpNo) {
+    printMemReference(MI, OpNo);
+  }
+  void printf80mem(const MachineInstr *MI, unsigned OpNo) {
+    printMemReference(MI, OpNo);
+  }
+  
   void printMachineInstruction(const MachineInstr *MI);
   void printOp(const MachineOperand &MO, bool isCallOperand = false);
-  void printSSECC(const MachineInstr *MI, unsigned Op, MVT::ValueType VT);
+  void printSSECC(const MachineInstr *MI, unsigned Op);
   void printMemReference(const MachineInstr *MI, unsigned Op);
   bool runOnMachineFunction(MachineFunction &F);
 };


Index: llvm/lib/Target/X86/X86InstrInfo.td
diff -u llvm/lib/Target/X86/X86InstrInfo.td:1.143 llvm/lib/Target/X86/X86InstrInfo.td:1.144
--- llvm/lib/Target/X86/X86InstrInfo.td:1.143	Tue Nov 29 23:11:18 2005
+++ llvm/lib/Target/X86/X86InstrInfo.td	Wed Nov 30 12:54:35 2005
@@ -15,24 +15,24 @@
 
 // *mem - Operand definitions for the funky X86 addressing mode operands.
 //
-
-class X86MemOperand<ValueType Ty> : Operand<Ty> {
-  let PrintMethod = "printMemoryOperand";
+class X86MemOperand<ValueType Ty, string printMethod> : Operand<Ty> {
+  let PrintMethod = printMethod;
   let NumMIOperands = 4;
   let MIOperandInfo = (ops R32, i8imm, R32, i32imm);
 }
+
+def i8mem   : X86MemOperand<i8,  "printi8mem">;
+def i16mem  : X86MemOperand<i16, "printi16mem">;
+def i32mem  : X86MemOperand<i32, "printi32mem">;
+def i64mem  : X86MemOperand<i64, "printi64mem">;
+def f32mem  : X86MemOperand<f32, "printf32mem">;
+def f64mem  : X86MemOperand<f64, "printf64mem">;
+def f80mem  : X86MemOperand<f80, "printf80mem">;
+
 def SSECC : Operand<i8> {
   let PrintMethod = "printSSECC";
 }
 
-def i8mem  : X86MemOperand<i8>;
-def i16mem : X86MemOperand<i16>;
-def i32mem : X86MemOperand<i32>;
-def i64mem : X86MemOperand<i64>;
-def f32mem : X86MemOperand<f32>;
-def f64mem : X86MemOperand<f64>;
-def f80mem : X86MemOperand<f80>;
-
 // A couple of more descriptive operand definitions.
 // 16-bits but only 8 bits are significant.
 def i16i8imm  : Operand<i16>;


Index: llvm/lib/Target/X86/X86IntelAsmPrinter.cpp
diff -u llvm/lib/Target/X86/X86IntelAsmPrinter.cpp:1.12 llvm/lib/Target/X86/X86IntelAsmPrinter.cpp:1.13
--- llvm/lib/Target/X86/X86IntelAsmPrinter.cpp:1.12	Tue Nov 29 19:59:00 2005
+++ llvm/lib/Target/X86/X86IntelAsmPrinter.cpp	Wed Nov 30 12:54:35 2005
@@ -59,8 +59,7 @@
   return false;
 }
 
-void X86IntelAsmPrinter::printSSECC(const MachineInstr *MI, unsigned Op,
-                                  MVT::ValueType VT) {
+void X86IntelAsmPrinter::printSSECC(const MachineInstr *MI, unsigned Op) {
   unsigned char value = MI->getOperand(Op).getImmedValue();
   assert(value <= 7 && "Invalid ssecc argument!");
   switch (value) {


Index: llvm/lib/Target/X86/X86IntelAsmPrinter.h
diff -u llvm/lib/Target/X86/X86IntelAsmPrinter.h:1.2 llvm/lib/Target/X86/X86IntelAsmPrinter.h:1.3
--- llvm/lib/Target/X86/X86IntelAsmPrinter.h:1.2	Thu Jul 14 17:52:25 2005
+++ llvm/lib/Target/X86/X86IntelAsmPrinter.h	Wed Nov 30 12:54:35 2005
@@ -37,7 +37,7 @@
   bool printInstruction(const MachineInstr *MI);
 
   // This method is used by the tablegen'erated instruction printer.
-  void printOperand(const MachineInstr *MI, unsigned OpNo, MVT::ValueType VT){
+  void printOperand(const MachineInstr *MI, unsigned OpNo){
     const MachineOperand &MO = MI->getOperand(OpNo);
     if (MO.getType() == MachineOperand::MO_MachineRegister) {
       assert(MRegisterInfo::isPhysicalRegister(MO.getReg())&&"Not physref??");
@@ -48,29 +48,42 @@
     }
   }
 
-  void printCallOperand(const MachineInstr *MI, unsigned OpNo,
-                        MVT::ValueType VT) {
+  void printCallOperand(const MachineInstr *MI, unsigned OpNo) {
     printOp(MI->getOperand(OpNo), true); // Don't print "OFFSET".
   }
 
-  void printMemoryOperand(const MachineInstr *MI, unsigned OpNo,
-                          MVT::ValueType VT) {
-    switch (VT) {
-    default: assert(0 && "Unknown arg size!");
-    case MVT::i8:   O << "BYTE PTR "; break;
-    case MVT::i16:  O << "WORD PTR "; break;
-    case MVT::i32:
-    case MVT::f32:  O << "DWORD PTR "; break;
-    case MVT::i64:
-    case MVT::f64:  O << "QWORD PTR "; break;
-    case MVT::f80:  O << "XWORD PTR "; break;
-    }
+  void printi8mem(const MachineInstr *MI, unsigned OpNo) {
+    O << "BYTE PTR ";
+    printMemReference(MI, OpNo);
+  }
+  void printi16mem(const MachineInstr *MI, unsigned OpNo) {
+    O << "WORD PTR ";
+    printMemReference(MI, OpNo);
+  }
+  void printi32mem(const MachineInstr *MI, unsigned OpNo) {
+    O << "WORD PTR ";
+    printMemReference(MI, OpNo);
+  }
+  void printi64mem(const MachineInstr *MI, unsigned OpNo) {
+    O << "DWORD PTR ";
+    printMemReference(MI, OpNo);
+  }
+  void printf32mem(const MachineInstr *MI, unsigned OpNo) {
+    O << "DWORD PTR ";
+    printMemReference(MI, OpNo);
+  }
+  void printf64mem(const MachineInstr *MI, unsigned OpNo) {
+    O << "QWORD PTR ";
+    printMemReference(MI, OpNo);
+  }
+  void printf80mem(const MachineInstr *MI, unsigned OpNo) {
+    O << "XWORD PTR ";
     printMemReference(MI, OpNo);
   }
 
   void printMachineInstruction(const MachineInstr *MI);
   void printOp(const MachineOperand &MO, bool elideOffsetKeyword = false);
-  void printSSECC(const MachineInstr *MI, unsigned Op, MVT::ValueType VT);
+  void printSSECC(const MachineInstr *MI, unsigned Op);
   void printMemReference(const MachineInstr *MI, unsigned Op);
   bool runOnMachineFunction(MachineFunction &F);
   bool doInitialization(Module &M);





From natebegeman at mac.com  Wed Nov 30 12:57:50 2005
From: natebegeman at mac.com (Nate Begeman)
Date: Wed, 30 Nov 2005 12:57:50 -0600
Subject: [llvm-commits] CVS: llvm/lib/Target/X86/X86IntelAsmPrinter.h 
Message-ID: <200511301857.MAA30023@zion.cs.uiuc.edu>



Changes in directory llvm/lib/Target/X86:

X86IntelAsmPrinter.h updated: 1.3 -> 1.4
---
Log message:

Fix a typo in my latest change


---
Diffs of the changes:  (+2 -2)

 X86IntelAsmPrinter.h |    4 ++--
 1 files changed, 2 insertions(+), 2 deletions(-)


Index: llvm/lib/Target/X86/X86IntelAsmPrinter.h
diff -u llvm/lib/Target/X86/X86IntelAsmPrinter.h:1.3 llvm/lib/Target/X86/X86IntelAsmPrinter.h:1.4
--- llvm/lib/Target/X86/X86IntelAsmPrinter.h:1.3	Wed Nov 30 12:54:35 2005
+++ llvm/lib/Target/X86/X86IntelAsmPrinter.h	Wed Nov 30 12:57:39 2005
@@ -61,11 +61,11 @@
     printMemReference(MI, OpNo);
   }
   void printi32mem(const MachineInstr *MI, unsigned OpNo) {
-    O << "WORD PTR ";
+    O << "DWORD PTR ";
     printMemReference(MI, OpNo);
   }
   void printi64mem(const MachineInstr *MI, unsigned OpNo) {
-    O << "DWORD PTR ";
+    O << "QWORD PTR ";
     printMemReference(MI, OpNo);
   }
   void printf32mem(const MachineInstr *MI, unsigned OpNo) {





From lattner at cs.uiuc.edu  Wed Nov 30 13:31:34 2005
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Wed, 30 Nov 2005 13:31:34 -0600
Subject: [llvm-commits] CVS: llvm/include/llvm/Analysis/AliasSetTracker.h 
Message-ID: <200511301931.NAA30353@zion.cs.uiuc.edu>



Changes in directory llvm/include/llvm/Analysis:

AliasSetTracker.h updated: 1.25 -> 1.26
---
Log message:

Add a simple clear() method


---
Diffs of the changes:  (+5 -0)

 AliasSetTracker.h |    5 +++++
 1 files changed, 5 insertions(+)


Index: llvm/include/llvm/Analysis/AliasSetTracker.h
diff -u llvm/include/llvm/Analysis/AliasSetTracker.h:1.25 llvm/include/llvm/Analysis/AliasSetTracker.h:1.26
--- llvm/include/llvm/Analysis/AliasSetTracker.h:1.25	Thu Apr 21 15:16:31 2005
+++ llvm/include/llvm/Analysis/AliasSetTracker.h	Wed Nov 30 13:31:23 2005
@@ -290,6 +290,11 @@
   bool remove(InvokeInst *II) { return remove(CallSite(II)); }
   bool remove(Instruction *I);
   void remove(AliasSet &AS);
+  
+  void clear() {
+    PointerMap.clear();
+    AliasSets.clear();
+  }
 
   /// getAliasSets - Return the alias sets that are active.
   ///





From lattner at cs.uiuc.edu  Wed Nov 30 13:37:19 2005
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Wed, 30 Nov 2005 13:37:19 -0600
Subject: [llvm-commits] 
	CVS: llvm/test/Regression/Transforms/DeadStoreElimination/2005-11-30-vaarg.ll
Message-ID: <200511301937.NAA30503@zion.cs.uiuc.edu>



Changes in directory llvm/test/Regression/Transforms/DeadStoreElimination:

2005-11-30-vaarg.ll added (r1.1)
---
Log message:

new testcase dse is miscompiling


---
Diffs of the changes:  (+9 -0)

 2005-11-30-vaarg.ll |    9 +++++++++
 1 files changed, 9 insertions(+)


Index: llvm/test/Regression/Transforms/DeadStoreElimination/2005-11-30-vaarg.ll
diff -c /dev/null llvm/test/Regression/Transforms/DeadStoreElimination/2005-11-30-vaarg.ll:1.1
*** /dev/null	Wed Nov 30 13:37:18 2005
--- llvm/test/Regression/Transforms/DeadStoreElimination/2005-11-30-vaarg.ll	Wed Nov 30 13:37:08 2005
***************
*** 0 ****
--- 1,9 ----
+ ; RUN: llvm-as < %s | opt -dse | llvm-dis | grep store
+ 
+ double %foo(sbyte* %X) {
+         %X_addr = alloca sbyte*
+         store sbyte* %X, sbyte** %X_addr  ;; not a dead store.
+         %tmp.0 = va_arg sbyte** %X_addr, double
+         ret double %tmp.0
+ }
+ 





From lattner at cs.uiuc.edu  Wed Nov 30 13:38:34 2005
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Wed, 30 Nov 2005 13:38:34 -0600
Subject: [llvm-commits] 
	CVS: llvm/lib/Transforms/Scalar/DeadStoreElimination.cpp
Message-ID: <200511301938.NAA30524@zion.cs.uiuc.edu>



Changes in directory llvm/lib/Transforms/Scalar:

DeadStoreElimination.cpp updated: 1.12 -> 1.13
---
Log message:

Fix a bug where we didn't realize that vaarg reads memory.  This fixes
Transforms/DeadStoreElimination/2005-11-30-vaarg.ll


---
Diffs of the changes:  (+7 -0)

 DeadStoreElimination.cpp |    7 +++++++
 1 files changed, 7 insertions(+)


Index: llvm/lib/Transforms/Scalar/DeadStoreElimination.cpp
diff -u llvm/lib/Transforms/Scalar/DeadStoreElimination.cpp:1.12 llvm/lib/Transforms/Scalar/DeadStoreElimination.cpp:1.13
--- llvm/lib/Transforms/Scalar/DeadStoreElimination.cpp:1.12	Thu Apr 21 18:45:12 2005
+++ llvm/lib/Transforms/Scalar/DeadStoreElimination.cpp	Wed Nov 30 13:38:22 2005
@@ -96,6 +96,13 @@
     }
 
     if (!isa<StoreInst>(I) || cast<StoreInst>(I)->isVolatile()) {
+      // If this is a vaarg instruction, it reads its operand.  We don't model
+      // it correctly, so just conservatively remove all entries.
+      if (isa<VAArgInst>(I)) {
+        KillLocs.clear();
+        continue;
+      }      
+      
       // If this is a non-store instruction, it makes everything referenced no
       // longer killed.  Remove anything aliased from the alias set tracker.
       KillLocs.remove(I);





From lattner at cs.uiuc.edu  Wed Nov 30 14:40:39 2005
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Wed, 30 Nov 2005 14:40:39 -0600
Subject: [llvm-commits] 
	CVS: llvm/test/Regression/CodeGen/PowerPC/2005-11-30-vastart-crash.ll
Message-ID: <200511302040.OAA31058@zion.cs.uiuc.edu>



Changes in directory llvm/test/Regression/CodeGen/PowerPC:

2005-11-30-vastart-crash.ll added (r1.1)
---
Log message:

Test that crashes the ppc backend.


---
Diffs of the changes:  (+17 -0)

 2005-11-30-vastart-crash.ll |   17 +++++++++++++++++
 1 files changed, 17 insertions(+)


Index: llvm/test/Regression/CodeGen/PowerPC/2005-11-30-vastart-crash.ll
diff -c /dev/null llvm/test/Regression/CodeGen/PowerPC/2005-11-30-vastart-crash.ll:1.1
*** /dev/null	Wed Nov 30 14:40:38 2005
--- llvm/test/Regression/CodeGen/PowerPC/2005-11-30-vastart-crash.ll	Wed Nov 30 14:40:28 2005
***************
*** 0 ****
--- 1,17 ----
+ ; RUN: llvm-as < %s | llc
+ target endian = big
+ target pointersize = 32
+ target triple = "powerpc-apple-darwin8.2.0"
+ implementation   ; Functions:
+ 
+ void %bar(int %G, int %E, int %F, int %A, int %B, int %C, int %D, sbyte* %fmt, ...) {
+ 	%ap = alloca sbyte*		; <sbyte**> [#uses=2]
+ 	call void %llvm.va_start( sbyte** %ap )
+ 	%tmp.1 = load sbyte** %ap		; <sbyte*> [#uses=1]
+ 	%tmp.0 = call double %foo( sbyte* %tmp.1 )		; <double> [#uses=0]
+ 	ret void
+ }
+ 
+ declare void %llvm.va_start(sbyte**)
+ 
+ declare double %foo(sbyte*)





From lattner at cs.uiuc.edu  Wed Nov 30 14:41:06 2005
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Wed, 30 Nov 2005 14:41:06 -0600
Subject: [llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCISelLowering.cpp 
Message-ID: <200511302041.OAA31113@zion.cs.uiuc.edu>



Changes in directory llvm/lib/Target/PowerPC:

PPCISelLowering.cpp updated: 1.47 -> 1.48
---
Log message:

Fix Regression/CodeGen/PowerPC/2005-11-30-vastart-crash.ll


---
Diffs of the changes:  (+6 -2)

 PPCISelLowering.cpp |    8 ++++++--
 1 files changed, 6 insertions(+), 2 deletions(-)


Index: llvm/lib/Target/PowerPC/PPCISelLowering.cpp
diff -u llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.47 llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.48
--- llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.47	Tue Nov 29 02:17:20 2005
+++ llvm/lib/Target/PowerPC/PPCISelLowering.cpp	Wed Nov 30 14:40:54 2005
@@ -434,7 +434,8 @@
         needsLoad = true;
       }
       break;
-    case MVT::i64: ObjSize = 8;
+    case MVT::i64:
+      ObjSize = 8;
       if (!ArgLive) break;
       if (GPR_remaining > 0) {
         SDOperand argHi, argLo;
@@ -530,7 +531,10 @@
       SDOperand PtrOff = DAG.getConstant(4, getPointerTy());
       FIN = DAG.getNode(ISD::ADD, MVT::i32, FIN, PtrOff);
     }
-    DAG.setRoot(DAG.getNode(ISD::TokenFactor, MVT::Other, MemOps));
+    if (!MemOps.empty()) {
+      MemOps.push_back(DAG.getRoot());
+      DAG.setRoot(DAG.getNode(ISD::TokenFactor, MVT::Other, MemOps));
+    }
   }
   
   // Finally, inform the code generator which regs we return values in.





From lattner at cs.uiuc.edu  Wed Nov 30 16:44:49 2005
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Wed, 30 Nov 2005 16:44:49 -0600
Subject: [llvm-commits] CVS: llvm/include/llvm/CodeGen/SelectionDAG.h 
Message-ID: <200511302244.QAA02653@zion.cs.uiuc.edu>



Changes in directory llvm/include/llvm/CodeGen:

SelectionDAG.h updated: 1.73 -> 1.74
---
Log message:

Make SelectNodeTo return N


---
Diffs of the changes:  (+30 -28)

 SelectionDAG.h |   58 +++++++++++++++++++++++++++++----------------------------
 1 files changed, 30 insertions(+), 28 deletions(-)


Index: llvm/include/llvm/CodeGen/SelectionDAG.h
diff -u llvm/include/llvm/CodeGen/SelectionDAG.h:1.73 llvm/include/llvm/CodeGen/SelectionDAG.h:1.74
--- llvm/include/llvm/CodeGen/SelectionDAG.h:1.73	Tue Nov 29 20:49:21 2005
+++ llvm/include/llvm/CodeGen/SelectionDAG.h	Wed Nov 30 16:44:37 2005
@@ -20,7 +20,7 @@
 
 #include <map>
 #include <list>
-#include <string> // FIXME remove eventually, turning map into const char* map.
+#include <string>
 
 namespace llvm {
   class TargetLowering;
@@ -272,33 +272,35 @@
   /// SelectNodeTo - These are used for target selectors to *mutate* the
   /// specified node to have the specified return type, Target opcode, and
   /// operands.  Note that target opcodes are stored as
-  /// ISD::BUILTIN_OP_END+TargetOpcode in the node opcode field.
-  void SelectNodeTo(SDNode *N, unsigned TargetOpc, MVT::ValueType VT);
-  void SelectNodeTo(SDNode *N, unsigned TargetOpc, MVT::ValueType VT, 
-                    SDOperand Op1);
-  void SelectNodeTo(SDNode *N, unsigned TargetOpc, MVT::ValueType VT, 
-                    SDOperand Op1, SDOperand Op2);
-  void SelectNodeTo(SDNode *N, unsigned TargetOpc, MVT::ValueType VT, 
-                    SDOperand Op1, SDOperand Op2, SDOperand Op3);
-  void SelectNodeTo(SDNode *N, unsigned TargetOpc, MVT::ValueType VT, 
-                    SDOperand Op1, SDOperand Op2, SDOperand Op3, SDOperand Op4);
-  void SelectNodeTo(SDNode *N, unsigned TargetOpc, MVT::ValueType VT, 
-                    SDOperand Op1, SDOperand Op2, SDOperand Op3, SDOperand Op4,
-                    SDOperand Op5);
-  void SelectNodeTo(SDNode *N, unsigned TargetOpc, MVT::ValueType VT, 
-                    SDOperand Op1, SDOperand Op2, SDOperand Op3, SDOperand Op4,
-                    SDOperand Op5, SDOperand Op6);
-  void SelectNodeTo(SDNode *N, unsigned TargetOpc, MVT::ValueType VT1, 
-                    MVT::ValueType VT2, SDOperand Op1, SDOperand Op2);
-  void SelectNodeTo(SDNode *N, unsigned TargetOpc, MVT::ValueType VT1,
-                    MVT::ValueType VT2, SDOperand Op1, SDOperand Op2,
-                    SDOperand Op3);
-  void SelectNodeTo(SDNode *N, unsigned TargetOpc, MVT::ValueType VT1,
-                    MVT::ValueType VT2, SDOperand Op1, SDOperand Op2,
-                    SDOperand Op3, SDOperand Op4);
-  void SelectNodeTo(SDNode *N, unsigned TargetOpc, MVT::ValueType VT1,
-                    MVT::ValueType VT2, SDOperand Op1, SDOperand Op2,
-                    SDOperand Op3, SDOperand Op4, SDOperand Op5);
+  /// ISD::BUILTIN_OP_END+TargetOpcode in the node opcode field.  The 0th value
+  /// of the resultant node is returned.
+  SDOperand SelectNodeTo(SDNode *N, unsigned TargetOpc, MVT::ValueType VT);
+  SDOperand SelectNodeTo(SDNode *N, unsigned TargetOpc, MVT::ValueType VT, 
+                         SDOperand Op1);
+  SDOperand SelectNodeTo(SDNode *N, unsigned TargetOpc, MVT::ValueType VT, 
+                         SDOperand Op1, SDOperand Op2);
+  SDOperand SelectNodeTo(SDNode *N, unsigned TargetOpc, MVT::ValueType VT, 
+                         SDOperand Op1, SDOperand Op2, SDOperand Op3);
+  SDOperand SelectNodeTo(SDNode *N, unsigned TargetOpc, MVT::ValueType VT, 
+                         SDOperand Op1, SDOperand Op2, SDOperand Op3, 
+                         SDOperand Op4);
+  SDOperand SelectNodeTo(SDNode *N, unsigned TargetOpc, MVT::ValueType VT, 
+                         SDOperand Op1, SDOperand Op2, SDOperand Op3,
+                         SDOperand Op4, SDOperand Op5);
+  SDOperand SelectNodeTo(SDNode *N, unsigned TargetOpc, MVT::ValueType VT, 
+                         SDOperand Op1, SDOperand Op2, SDOperand Op3, 
+                         SDOperand Op4, SDOperand Op5, SDOperand Op6);
+  SDOperand SelectNodeTo(SDNode *N, unsigned TargetOpc, MVT::ValueType VT1, 
+                         MVT::ValueType VT2, SDOperand Op1, SDOperand Op2);
+  SDOperand SelectNodeTo(SDNode *N, unsigned TargetOpc, MVT::ValueType VT1,
+                         MVT::ValueType VT2, SDOperand Op1, SDOperand Op2,
+                         SDOperand Op3);
+  SDOperand SelectNodeTo(SDNode *N, unsigned TargetOpc, MVT::ValueType VT1,
+                         MVT::ValueType VT2, SDOperand Op1, SDOperand Op2,
+                         SDOperand Op3, SDOperand Op4);
+  SDOperand SelectNodeTo(SDNode *N, unsigned TargetOpc, MVT::ValueType VT1,
+                         MVT::ValueType VT2, SDOperand Op1, SDOperand Op2,
+                         SDOperand Op3, SDOperand Op4, SDOperand Op5);
 
   SDOperand getTargetNode(unsigned Opcode, MVT::ValueType VT) {
     return getNode(ISD::BUILTIN_OP_END+Opcode, VT);





From lattner at cs.uiuc.edu  Wed Nov 30 16:45:26 2005
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Wed, 30 Nov 2005 16:45:26 -0600
Subject: [llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp 
Message-ID: <200511302245.QAA03257@zion.cs.uiuc.edu>



Changes in directory llvm/lib/CodeGen/SelectionDAG:

SelectionDAG.cpp updated: 1.219 -> 1.220
---
Log message:

Make SelectNodeTo return N


---
Diffs of the changes:  (+49 -35)

 SelectionDAG.cpp |   84 ++++++++++++++++++++++++++++++++-----------------------
 1 files changed, 49 insertions(+), 35 deletions(-)


Index: llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp:1.219 llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp:1.220
--- llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp:1.219	Wed Nov 30 12:20:52 2005
+++ llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp	Wed Nov 30 16:45:14 2005
@@ -1415,104 +1415,118 @@
 /// specified node to have the specified return type, Target opcode, and
 /// operands.  Note that target opcodes are stored as
 /// ISD::BUILTIN_OP_END+TargetOpcode in the node opcode field.
-void SelectionDAG::SelectNodeTo(SDNode *N, unsigned TargetOpc,
-                                MVT::ValueType VT) {
+SDOperand SelectionDAG::SelectNodeTo(SDNode *N, unsigned TargetOpc,
+                                     MVT::ValueType VT) {
   RemoveNodeFromCSEMaps(N);
   N->MorphNodeTo(ISD::BUILTIN_OP_END+TargetOpc);
   N->setValueTypes(VT);
+  return SDOperand(N, 0);
 }
 
-void SelectionDAG::SelectNodeTo(SDNode *N, unsigned TargetOpc,
-                                MVT::ValueType VT, SDOperand Op1) {
+SDOperand SelectionDAG::SelectNodeTo(SDNode *N, unsigned TargetOpc,
+                                     MVT::ValueType VT, SDOperand Op1) {
   RemoveNodeFromCSEMaps(N);
   N->MorphNodeTo(ISD::BUILTIN_OP_END+TargetOpc);
   N->setValueTypes(VT);
   N->setOperands(Op1);
+  return SDOperand(N, 0);
 }
 
-void SelectionDAG::SelectNodeTo(SDNode *N, unsigned TargetOpc,
-                                MVT::ValueType VT, SDOperand Op1,
-                                SDOperand Op2) {
+SDOperand SelectionDAG::SelectNodeTo(SDNode *N, unsigned TargetOpc,
+                                     MVT::ValueType VT, SDOperand Op1,
+                                     SDOperand Op2) {
   RemoveNodeFromCSEMaps(N);
   N->MorphNodeTo(ISD::BUILTIN_OP_END+TargetOpc);
   N->setValueTypes(VT);
   N->setOperands(Op1, Op2);
+  return SDOperand(N, 0);
 }
 
-void SelectionDAG::SelectNodeTo(SDNode *N, unsigned TargetOpc,
-                                MVT::ValueType VT, SDOperand Op1,
-                                SDOperand Op2, SDOperand Op3) {
+SDOperand SelectionDAG::SelectNodeTo(SDNode *N, unsigned TargetOpc,
+                                     MVT::ValueType VT, SDOperand Op1,
+                                     SDOperand Op2, SDOperand Op3) {
   RemoveNodeFromCSEMaps(N);
   N->MorphNodeTo(ISD::BUILTIN_OP_END+TargetOpc);
   N->setValueTypes(VT);
   N->setOperands(Op1, Op2, Op3);
+  return SDOperand(N, 0);
 }
 
-void SelectionDAG::SelectNodeTo(SDNode *N, unsigned TargetOpc,
-                                MVT::ValueType VT, SDOperand Op1,
-                                SDOperand Op2, SDOperand Op3, SDOperand Op4) {
+SDOperand SelectionDAG::SelectNodeTo(SDNode *N, unsigned TargetOpc,
+                                     MVT::ValueType VT, SDOperand Op1,
+                                     SDOperand Op2, SDOperand Op3,
+                                     SDOperand Op4) {
   RemoveNodeFromCSEMaps(N);
   N->MorphNodeTo(ISD::BUILTIN_OP_END+TargetOpc);
   N->setValueTypes(VT);
   N->setOperands(Op1, Op2, Op3, Op4);
+  return SDOperand(N, 0);
 }
 
-void SelectionDAG::SelectNodeTo(SDNode *N, unsigned TargetOpc,
-                                MVT::ValueType VT, SDOperand Op1,
-                                SDOperand Op2, SDOperand Op3, SDOperand Op4,
-                                SDOperand Op5) {
+SDOperand SelectionDAG::SelectNodeTo(SDNode *N, unsigned TargetOpc,
+                                     MVT::ValueType VT, SDOperand Op1,
+                                     SDOperand Op2, SDOperand Op3,SDOperand Op4,
+                                     SDOperand Op5) {
   RemoveNodeFromCSEMaps(N);
   N->MorphNodeTo(ISD::BUILTIN_OP_END+TargetOpc);
   N->setValueTypes(VT);
   N->setOperands(Op1, Op2, Op3, Op4, Op5);
+  return SDOperand(N, 0);
 }
 
-void SelectionDAG::SelectNodeTo(SDNode *N, unsigned TargetOpc,
-                                MVT::ValueType VT, SDOperand Op1,
-                                SDOperand Op2, SDOperand Op3, SDOperand Op4,
-                                SDOperand Op5, SDOperand Op6) {
+SDOperand SelectionDAG::SelectNodeTo(SDNode *N, unsigned TargetOpc,
+                                     MVT::ValueType VT, SDOperand Op1,
+                                     SDOperand Op2, SDOperand Op3,SDOperand Op4,
+                                     SDOperand Op5, SDOperand Op6) {
   RemoveNodeFromCSEMaps(N);
   N->MorphNodeTo(ISD::BUILTIN_OP_END+TargetOpc);
   N->setValueTypes(VT);
   N->setOperands(Op1, Op2, Op3, Op4, Op5, Op6);
+  return SDOperand(N, 0);
 }
 
-void SelectionDAG::SelectNodeTo(SDNode *N, unsigned TargetOpc, 
-                                MVT::ValueType VT1, MVT::ValueType VT2,
-                                SDOperand Op1, SDOperand Op2) {
+SDOperand SelectionDAG::SelectNodeTo(SDNode *N, unsigned TargetOpc, 
+                                     MVT::ValueType VT1, MVT::ValueType VT2,
+                                     SDOperand Op1, SDOperand Op2) {
   RemoveNodeFromCSEMaps(N);
   N->MorphNodeTo(ISD::BUILTIN_OP_END+TargetOpc);
   setNodeValueTypes(N, VT1, VT2);
   N->setOperands(Op1, Op2);
+  return SDOperand(N, 0);
 }
 
-void SelectionDAG::SelectNodeTo(SDNode *N, unsigned TargetOpc,
-                                MVT::ValueType VT1, MVT::ValueType VT2,
-                                SDOperand Op1, SDOperand Op2, SDOperand Op3) {
+SDOperand SelectionDAG::SelectNodeTo(SDNode *N, unsigned TargetOpc,
+                                     MVT::ValueType VT1, MVT::ValueType VT2,
+                                     SDOperand Op1, SDOperand Op2, 
+                                     SDOperand Op3) {
   RemoveNodeFromCSEMaps(N);
   N->MorphNodeTo(ISD::BUILTIN_OP_END+TargetOpc);
   setNodeValueTypes(N, VT1, VT2);
   N->setOperands(Op1, Op2, Op3);
+  return SDOperand(N, 0);
 }
 
-void SelectionDAG::SelectNodeTo(SDNode *N, unsigned TargetOpc,
-                                MVT::ValueType VT1, MVT::ValueType VT2,
-                                SDOperand Op1, SDOperand Op2,
-                                SDOperand Op3, SDOperand Op4) {
+SDOperand SelectionDAG::SelectNodeTo(SDNode *N, unsigned TargetOpc,
+                                     MVT::ValueType VT1, MVT::ValueType VT2,
+                                     SDOperand Op1, SDOperand Op2,
+                                     SDOperand Op3, SDOperand Op4) {
   RemoveNodeFromCSEMaps(N);
   N->MorphNodeTo(ISD::BUILTIN_OP_END+TargetOpc);
   setNodeValueTypes(N, VT1, VT2);
   N->setOperands(Op1, Op2, Op3, Op4);
+  return SDOperand(N, 0);
 }
 
-void SelectionDAG::SelectNodeTo(SDNode *N, unsigned TargetOpc,
-                                MVT::ValueType VT1, MVT::ValueType VT2,
-                                SDOperand Op1, SDOperand Op2,
-                                SDOperand Op3, SDOperand Op4, SDOperand Op5) {
+SDOperand SelectionDAG::SelectNodeTo(SDNode *N, unsigned TargetOpc,
+                                     MVT::ValueType VT1, MVT::ValueType VT2,
+                                     SDOperand Op1, SDOperand Op2,
+                                     SDOperand Op3, SDOperand Op4, 
+                                     SDOperand Op5) {
   RemoveNodeFromCSEMaps(N);
   N->MorphNodeTo(ISD::BUILTIN_OP_END+TargetOpc);
   setNodeValueTypes(N, VT1, VT2);
   N->setOperands(Op1, Op2, Op3, Op4, Op5);
+  return SDOperand(N, 0);
 }
 
 // ReplaceAllUsesWith - Modify anything using 'From' to use 'To' instead.





From lattner at cs.uiuc.edu  Wed Nov 30 16:53:17 2005
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Wed, 30 Nov 2005 16:53:17 -0600
Subject: [llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp 
Message-ID: <200511302253.QAA10751@zion.cs.uiuc.edu>



Changes in directory llvm/lib/Target/PowerPC:

PPCISelDAGToDAG.cpp updated: 1.131 -> 1.132
---
Log message:

SelectNodeTo now returns N.  Use it instead of return N directly.


---
Diffs of the changes:  (+81 -108)

 PPCISelDAGToDAG.cpp |  189 ++++++++++++++++++++++------------------------------
 1 files changed, 81 insertions(+), 108 deletions(-)


Index: llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
diff -u llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp:1.131 llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp:1.132
--- llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp:1.131	Wed Nov 30 02:22:07 2005
+++ llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp	Wed Nov 30 16:53:06 2005
@@ -661,25 +661,22 @@
       default: break;
       case ISD::SETEQ:
         Op = CurDAG->getTargetNode(PPC::CNTLZW, MVT::i32, Op);
-        CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Op, getI32Imm(27),
-                             getI32Imm(5), getI32Imm(31));
-        return SDOperand(N, 0);
+        return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Op, getI32Imm(27),
+                                    getI32Imm(5), getI32Imm(31));
       case ISD::SETNE: {
         SDOperand AD = CurDAG->getTargetNode(PPC::ADDIC, MVT::i32, MVT::Flag,
                                              Op, getI32Imm(~0U));
-        CurDAG->SelectNodeTo(N, PPC::SUBFE, MVT::i32, AD, Op, AD.getValue(1));
-        return SDOperand(N, 0);
+        return CurDAG->SelectNodeTo(N, PPC::SUBFE, MVT::i32, AD, Op, 
+                                    AD.getValue(1));
       }
       case ISD::SETLT:
-        CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Op, getI32Imm(1),
-                             getI32Imm(31), getI32Imm(31));
-        return SDOperand(N, 0);
+        return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Op, getI32Imm(1),
+                                    getI32Imm(31), getI32Imm(31));
       case ISD::SETGT: {
         SDOperand T = CurDAG->getTargetNode(PPC::NEG, MVT::i32, Op);
         T = CurDAG->getTargetNode(PPC::ANDC, MVT::i32, T, Op);;
-        CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, T, getI32Imm(1),
-                             getI32Imm(31), getI32Imm(31));
-        return SDOperand(N, 0);
+        return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, T, getI32Imm(1),
+                                    getI32Imm(31), getI32Imm(31));
       }
       }
     } else if (Imm == ~0U) {        // setcc op, -1
@@ -689,31 +686,28 @@
       case ISD::SETEQ:
         Op = CurDAG->getTargetNode(PPC::ADDIC, MVT::i32, MVT::Flag,
                                    Op, getI32Imm(1));
-        CurDAG->SelectNodeTo(N, PPC::ADDZE, MVT::i32, 
-                             CurDAG->getTargetNode(PPC::LI, MVT::i32,
-                                                   getI32Imm(0)),
-                             Op.getValue(1));
-        return SDOperand(N, 0);
+        return CurDAG->SelectNodeTo(N, PPC::ADDZE, MVT::i32, 
+                                    CurDAG->getTargetNode(PPC::LI, MVT::i32,
+                                                          getI32Imm(0)),
+                                    Op.getValue(1));
       case ISD::SETNE: {
         Op = CurDAG->getTargetNode(PPC::NOR, MVT::i32, Op, Op);
         SDOperand AD = CurDAG->getTargetNode(PPC::ADDIC, MVT::i32, MVT::Flag,
                                              Op, getI32Imm(~0U));
-        CurDAG->SelectNodeTo(N, PPC::SUBFE, MVT::i32, AD, Op, AD.getValue(1));
-        return SDOperand(N, 0);
+        return CurDAG->SelectNodeTo(N, PPC::SUBFE, MVT::i32, AD, Op, 
+                                    AD.getValue(1));
       }
       case ISD::SETLT: {
         SDOperand AD = CurDAG->getTargetNode(PPC::ADDI, MVT::i32, Op,
                                              getI32Imm(1));
         SDOperand AN = CurDAG->getTargetNode(PPC::AND, MVT::i32, AD, Op);
-        CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, AN, getI32Imm(1),
-                             getI32Imm(31), getI32Imm(31));
-        return SDOperand(N, 0);
+        return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, AN, getI32Imm(1),
+                                    getI32Imm(31), getI32Imm(31));
       }
       case ISD::SETGT:
         Op = CurDAG->getTargetNode(PPC::RLWINM, MVT::i32, Op, getI32Imm(1),
                                    getI32Imm(31), getI32Imm(31));
-        CurDAG->SelectNodeTo(N, PPC::XORI, MVT::i32, Op, getI32Imm(1));
-        return SDOperand(N, 0);
+        return CurDAG->SelectNodeTo(N, PPC::XORI, MVT::i32, Op, getI32Imm(1));
       }
     }
   }
@@ -741,18 +735,16 @@
     IntCR = CurDAG->getTargetNode(PPC::MFCR, MVT::i32, CCReg);
   
   if (!Inv) {
-    CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, IntCR,
-                         getI32Imm((32-(3-Idx)) & 31),
-                                   getI32Imm(31), getI32Imm(31));
+    return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, IntCR,
+                                getI32Imm((32-(3-Idx)) & 31),
+                                getI32Imm(31), getI32Imm(31));
   } else {
     SDOperand Tmp =
     CurDAG->getTargetNode(PPC::RLWINM, MVT::i32, IntCR,
                           getI32Imm((32-(3-Idx)) & 31),
                           getI32Imm(31),getI32Imm(31));
-    CurDAG->SelectNodeTo(N, PPC::XORI, MVT::i32, Tmp, getI32Imm(1));
+    return CurDAG->SelectNodeTo(N, PPC::XORI, MVT::i32, Tmp, getI32Imm(1));
   }
-  
-  return SDOperand(N, 0);
 }
 
 /// isCallCompatibleAddress - Return true if the specified 32-bit value is
@@ -896,12 +888,10 @@
     
   case ISD::FrameIndex: {
     int FI = cast<FrameIndexSDNode>(N)->getIndex();
-    if (N->hasOneUse()) {
-      CurDAG->SelectNodeTo(N, PPC::ADDI, MVT::i32,
-                           CurDAG->getTargetFrameIndex(FI, MVT::i32),
-                           getI32Imm(0));
-      return SDOperand(N, 0);
-    }
+    if (N->hasOneUse())
+      return CurDAG->SelectNodeTo(N, PPC::ADDI, MVT::i32,
+                                  CurDAG->getTargetFrameIndex(FI, MVT::i32),
+                                  getI32Imm(0));
     return CurDAG->getTargetNode(PPC::ADDI, MVT::i32,
                                  CurDAG->getTargetFrameIndex(FI, MVT::i32),
                                  getI32Imm(0));
@@ -913,10 +903,8 @@
       Tmp = CurDAG->getTargetNode(PPC::ADDIS, MVT::i32, getGlobalBaseReg(),CPI);
     else
       Tmp = CurDAG->getTargetNode(PPC::LIS, MVT::i32, CPI);
-    if (N->hasOneUse()) {
-      CurDAG->SelectNodeTo(N, PPC::LA, MVT::i32, Tmp, CPI);
-      return SDOperand(N, 0);
-    }
+    if (N->hasOneUse())
+      return CurDAG->SelectNodeTo(N, PPC::LA, MVT::i32, Tmp, CPI);
     return CurDAG->getTargetNode(PPC::LA, MVT::i32, Tmp, CPI);
   }
   case ISD::FADD: {
@@ -925,19 +913,17 @@
       if (N->getOperand(0).getOpcode() == ISD::FMUL &&
           N->getOperand(0).Val->hasOneUse()) {
         ++FusedFP; // Statistic
-        CurDAG->SelectNodeTo(N, Ty == MVT::f64 ? PPC::FMADD : PPC::FMADDS, Ty,
-                             Select(N->getOperand(0).getOperand(0)),
-                             Select(N->getOperand(0).getOperand(1)),
-                             Select(N->getOperand(1)));
-        return SDOperand(N, 0);
+        return CurDAG->SelectNodeTo(N, Ty == MVT::f64 ? PPC::FMADD :PPC::FMADDS,
+                                    Ty, Select(N->getOperand(0).getOperand(0)),
+                                    Select(N->getOperand(0).getOperand(1)),
+                                    Select(N->getOperand(1)));
       } else if (N->getOperand(1).getOpcode() == ISD::FMUL &&
                  N->getOperand(1).hasOneUse()) {
         ++FusedFP; // Statistic
-        CurDAG->SelectNodeTo(N, Ty == MVT::f64 ? PPC::FMADD : PPC::FMADDS, Ty,
-                             Select(N->getOperand(1).getOperand(0)),
-                             Select(N->getOperand(1).getOperand(1)),
-                             Select(N->getOperand(0)));
-        return SDOperand(N, 0);
+        return CurDAG->SelectNodeTo(N, Ty == MVT::f64 ? PPC::FMADD :PPC::FMADDS,
+                                    Ty, Select(N->getOperand(1).getOperand(0)),
+                                    Select(N->getOperand(1).getOperand(1)),
+                                    Select(N->getOperand(0)));
       }
     }
     
@@ -951,19 +937,17 @@
       if (N->getOperand(0).getOpcode() == ISD::FMUL &&
           N->getOperand(0).Val->hasOneUse()) {
         ++FusedFP; // Statistic
-        CurDAG->SelectNodeTo(N, Ty == MVT::f64 ? PPC::FMSUB : PPC::FMSUBS, Ty,
-                             Select(N->getOperand(0).getOperand(0)),
-                             Select(N->getOperand(0).getOperand(1)),
-                             Select(N->getOperand(1)));
-        return SDOperand(N, 0);
+        return CurDAG->SelectNodeTo(N, Ty == MVT::f64 ? PPC::FMSUB:PPC::FMSUBS,
+                                    Ty, Select(N->getOperand(0).getOperand(0)),
+                                    Select(N->getOperand(0).getOperand(1)),
+                                    Select(N->getOperand(1)));
       } else if (N->getOperand(1).getOpcode() == ISD::FMUL &&
                  N->getOperand(1).Val->hasOneUse()) {
         ++FusedFP; // Statistic
-        CurDAG->SelectNodeTo(N, Ty == MVT::f64 ? PPC::FNMSUB : PPC::FNMSUBS, Ty,
-                             Select(N->getOperand(1).getOperand(0)),
-                             Select(N->getOperand(1).getOperand(1)),
-                             Select(N->getOperand(0)));
-        return SDOperand(N, 0);
+        return CurDAG->SelectNodeTo(N, Ty == MVT::f64 ?PPC::FNMSUB:PPC::FNMSUBS, 
+                                    Ty, Select(N->getOperand(1).getOperand(0)),
+                                    Select(N->getOperand(1).getOperand(1)),
+                                    Select(N->getOperand(0)));
       }
     }
 
@@ -983,9 +967,8 @@
           CurDAG->getTargetNode(PPC::SRAWI, MVT::i32, MVT::Flag,
                                 Select(N->getOperand(0)),
                                 getI32Imm(Log2_32(Imm)));
-        CurDAG->SelectNodeTo(N, PPC::ADDZE, MVT::i32, 
-                             Op.getValue(0), Op.getValue(1));
-        return SDOperand(N, 0);
+        return CurDAG->SelectNodeTo(N, PPC::ADDZE, MVT::i32, 
+                                    Op.getValue(0), Op.getValue(1));
       } else if ((signed)Imm < 0 && isPowerOf2_32(-Imm)) {
         SDOperand Op =
           CurDAG->getTargetNode(PPC::SRAWI, MVT::i32, MVT::Flag,
@@ -994,8 +977,7 @@
         SDOperand PT =
           CurDAG->getTargetNode(PPC::ADDZE, MVT::i32, Op.getValue(0),
                                 Op.getValue(1));
-        CurDAG->SelectNodeTo(N, PPC::NEG, MVT::i32, PT);
-        return SDOperand(N, 0);
+        return CurDAG->SelectNodeTo(N, PPC::NEG, MVT::i32, PT);
       }
     }
     
@@ -1020,9 +1002,8 @@
         isRunOfOnes(Imm, MB, ME);
         SH = 0;
       }
-      CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Val, getI32Imm(SH),
-                           getI32Imm(MB), getI32Imm(ME));
-      return SDOperand(N, 0);
+      return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Val, getI32Imm(SH),
+                                  getI32Imm(MB), getI32Imm(ME));
     }
     
     // Other cases are autogenerated.
@@ -1038,10 +1019,9 @@
     unsigned Imm, SH, MB, ME;
     if (isOpcWithIntImmediate(N->getOperand(0).Val, ISD::AND, Imm) &&
         isRotateAndMask(N, Imm, true, SH, MB, ME)) {
-      CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, 
-                           Select(N->getOperand(0).getOperand(0)),
-                           getI32Imm(SH), getI32Imm(MB), getI32Imm(ME));
-      return SDOperand(N, 0);
+      return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, 
+                                  Select(N->getOperand(0).getOperand(0)),
+                                  getI32Imm(SH), getI32Imm(MB), getI32Imm(ME));
     }
     
     // Other cases are autogenerated.
@@ -1051,10 +1031,10 @@
     unsigned Imm, SH, MB, ME;
     if (isOpcWithIntImmediate(N->getOperand(0).Val, ISD::AND, Imm) &&
         isRotateAndMask(N, Imm, true, SH, MB, ME)) { 
-      CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, 
-                           Select(N->getOperand(0).getOperand(0)),
-                           getI32Imm(SH & 0x1F), getI32Imm(MB), getI32Imm(ME));
-      return SDOperand(N, 0);
+      return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, 
+                                  Select(N->getOperand(0).getOperand(0)),
+                                  getI32Imm(SH & 0x1F), getI32Imm(MB),
+                                  getI32Imm(ME));
     }
     
     // Other cases are autogenerated.
@@ -1079,18 +1059,16 @@
       // fall through and generate a fneg instruction.
       if (Opc) {
         if (Opc == PPC::FNABSS || Opc == PPC::FNABSD)
-          CurDAG->SelectNodeTo(N, Opc, Ty, Val.getOperand(0));
+          return CurDAG->SelectNodeTo(N, Opc, Ty, Val.getOperand(0));
         else
-          CurDAG->SelectNodeTo(N, Opc, Ty, Val.getOperand(0),
-                               Val.getOperand(1), Val.getOperand(2));
-        return SDOperand(N, 0);
+          return CurDAG->SelectNodeTo(N, Opc, Ty, Val.getOperand(0),
+                                      Val.getOperand(1), Val.getOperand(2));
       }
     }
     if (Ty == MVT::f32)
-      CurDAG->SelectNodeTo(N, PPC::FNEGS, MVT::f32, Val);
+      return CurDAG->SelectNodeTo(N, PPC::FNEGS, MVT::f32, Val);
     else
-      CurDAG->SelectNodeTo(N, PPC::FNEGD, MVT::f64, Val);
-    return SDOperand(N, 0);
+      return CurDAG->SelectNodeTo(N, PPC::FNEGD, MVT::f64, Val);
   }
   case ISD::LOAD:
   case ISD::EXTLOAD:
@@ -1129,9 +1107,9 @@
     // If this is an f32 -> f64 load, emit the f32 load, then use an 'extending
     // copy'.
     if (TypeBeingLoaded != MVT::f32 || N->getOpcode() == ISD::LOAD) {
-        CurDAG->SelectNodeTo(N, Opc, N->getValueType(0), MVT::Other,
-                             Op1, Op2, Select(N->getOperand(0)));
-      return SDOperand(N, Op.ResNo);
+      return CurDAG->SelectNodeTo(N, Opc, N->getValueType(0), MVT::Other,
+                                  Op1, Op2, Select(N->getOperand(0))).
+                    getValue(Op.ResNo);
     } else {
       std::vector<SDOperand> Ops;
       Ops.push_back(Op1);
@@ -1177,9 +1155,8 @@
       }
     }
     
-    CurDAG->SelectNodeTo(N, Opc, MVT::Other, Select(N->getOperand(1)),
-                         AddrOp1, AddrOp2, Select(N->getOperand(0)));
-    return SDOperand(N, 0);
+    return CurDAG->SelectNodeTo(N, Opc, MVT::Other, Select(N->getOperand(1)),
+                                AddrOp1, AddrOp2, Select(N->getOperand(0)));
   }
     
   case ISD::SELECT_CC: {
@@ -1195,9 +1172,8 @@
             SDOperand Tmp =
               CurDAG->getTargetNode(PPC::ADDIC, MVT::i32, MVT::Flag,
                                     LHS, getI32Imm(~0U));
-            CurDAG->SelectNodeTo(N, PPC::SUBFE, MVT::i32, Tmp, LHS,
-                                 Tmp.getValue(1));
-            return SDOperand(N, 0);
+            return CurDAG->SelectNodeTo(N, PPC::SUBFE, MVT::i32, Tmp, LHS,
+                                        Tmp.getValue(1));
           }
 
     SDOperand CCReg = SelectCC(N->getOperand(0), N->getOperand(1), CC);
@@ -1211,10 +1187,10 @@
       SelectCCOp = PPC::SELECT_CC_F4;
     else
       SelectCCOp = PPC::SELECT_CC_F8;
-    CurDAG->SelectNodeTo(N, SelectCCOp, N->getValueType(0), CCReg,
-                         Select(N->getOperand(2)), Select(N->getOperand(3)),
-                         getI32Imm(BROpc));
-    return SDOperand(N, 0);
+    return CurDAG->SelectNodeTo(N, SelectCCOp, N->getValueType(0), CCReg,
+                                Select(N->getOperand(2)), 
+                                Select(N->getOperand(3)),
+                                getI32Imm(BROpc));
   }
     
   case ISD::CALLSEQ_START:
@@ -1222,9 +1198,8 @@
     unsigned Amt = cast<ConstantSDNode>(N->getOperand(1))->getValue();
     unsigned Opc = N->getOpcode() == ISD::CALLSEQ_START ?
                        PPC::ADJCALLSTACKDOWN : PPC::ADJCALLSTACKUP;
-    CurDAG->SelectNodeTo(N, Opc, MVT::Other,
-                         getI32Imm(Amt), Select(N->getOperand(0)));
-    return SDOperand(N, 0);
+    return CurDAG->SelectNodeTo(N, Opc, MVT::Other,
+                                getI32Imm(Amt), Select(N->getOperand(0)));
   }
   case ISD::RET: {
     SDOperand Chain = Select(N->getOperand(0));     // Token chain.
@@ -1246,13 +1221,11 @@
     }
 
     // Finally, select this to a blr (return) instruction.
-    CurDAG->SelectNodeTo(N, PPC::BLR, MVT::Other, Chain);
-    return SDOperand(N, 0);
+    return CurDAG->SelectNodeTo(N, PPC::BLR, MVT::Other, Chain);
   }
   case ISD::BR:
-    CurDAG->SelectNodeTo(N, PPC::B, MVT::Other, N->getOperand(1),
-                         Select(N->getOperand(0)));
-    return SDOperand(N, 0);
+    return CurDAG->SelectNodeTo(N, PPC::B, MVT::Other, N->getOperand(1),
+                                Select(N->getOperand(0)));
   case ISD::BR_CC:
   case ISD::BRTWOWAY_CC: {
     SDOperand Chain = Select(N->getOperand(0));
@@ -1284,7 +1257,7 @@
                                            CondCode, getI32Imm(Opc),
                                            CondTrueBlock, CondFalseBlock,
                                            Chain);
-      CurDAG->SelectNodeTo(N, PPC::B, MVT::Other, CondFalseBlock, CB);
+      return CurDAG->SelectNodeTo(N, PPC::B, MVT::Other, CondFalseBlock, CB);
     } else {
       // Iterate to the next basic block
       ilist<MachineBasicBlock>::iterator It = BB;
@@ -1295,11 +1268,11 @@
       // we have nothing better to set it to, and leaving it alone will cause
       // the PowerPC Branch Selection pass to crash.
       if (It == BB->getParent()->end()) It = Dest;
-      CurDAG->SelectNodeTo(N, PPC::COND_BRANCH, MVT::Other, CondCode,
-                           getI32Imm(getBCCForSetCC(CC)), N->getOperand(4),
-                           CurDAG->getBasicBlock(It), Chain);
+      return CurDAG->SelectNodeTo(N, PPC::COND_BRANCH, MVT::Other, CondCode,
+                                  getI32Imm(getBCCForSetCC(CC)), 
+                                  N->getOperand(4), CurDAG->getBasicBlock(It), 
+                                  Chain);
     }
-    return SDOperand(N, 0);
   }
   }
   





From lattner at cs.uiuc.edu  Wed Nov 30 16:59:30 2005
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Wed, 30 Nov 2005 16:59:30 -0600
Subject: [llvm-commits] CVS: llvm/lib/Target/X86/X86ISelDAGToDAG.cpp 
Message-ID: <200511302259.QAA11196@zion.cs.uiuc.edu>



Changes in directory llvm/lib/Target/X86:

X86ISelDAGToDAG.cpp updated: 1.4 -> 1.5
---
Log message:

SelectNodeTo now returns its result, we must pay attention to it.


---
Diffs of the changes:  (+18 -20)

 X86ISelDAGToDAG.cpp |   38 ++++++++++++++++++--------------------
 1 files changed, 18 insertions(+), 20 deletions(-)


Index: llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
diff -u llvm/lib/Target/X86/X86ISelDAGToDAG.cpp:1.4 llvm/lib/Target/X86/X86ISelDAGToDAG.cpp:1.5
--- llvm/lib/Target/X86/X86ISelDAGToDAG.cpp:1.4	Tue Nov 29 20:51:20 2005
+++ llvm/lib/Target/X86/X86ISelDAGToDAG.cpp	Wed Nov 30 16:59:19 2005
@@ -289,8 +289,7 @@
             case MVT::i32: Opc = X86::ADD32rr; break;
           }
           SDOperand Tmp0 = Select(N->getOperand(0));
-          CurDAG->SelectNodeTo(N, Opc, MVT::i32, Tmp0, Tmp0);
-          return SDOperand(N, 0);
+          return CurDAG->SelectNodeTo(N, Opc, MVT::i32, Tmp0, Tmp0);
         }
       } else {
         static const unsigned SHLTab[] = {
@@ -319,8 +318,7 @@
         }
 
         SDOperand Tmp0 = Select(N->getOperand(0));
-        CurDAG->SelectNodeTo(N, Opc, MVT::i32, Tmp0);
-        return SDOperand(N, 0);
+        return CurDAG->SelectNodeTo(N, Opc, MVT::i32, Tmp0);
       }
       break;
 
@@ -350,13 +348,11 @@
           break;
       }
       if (X86Lowering.getBytesToPopOnReturn() == 0)
-        CurDAG->SelectNodeTo(N, X86::RET, MVT::Other, Chain);
+        return CurDAG->SelectNodeTo(N, X86::RET, MVT::Other, Chain);
       else
-        CurDAG->SelectNodeTo(N, X86::RET, MVT::Other,
-                             getI16Imm(X86Lowering.getBytesToPopOnReturn()),
-                             Chain);
-
-      return SDOperand(N, 0);
+        return CurDAG->SelectNodeTo(N, X86::RET, MVT::Other,
+                              getI16Imm(X86Lowering.getBytesToPopOnReturn()),
+                                    Chain);
     }
 
     case ISD::LOAD: {
@@ -385,15 +381,17 @@
           ? CurDAG->getTargetGlobalAddress(AM.GV, MVT::i32, AM.Disp)
           : getI32Imm(AM.Disp);
         if (AM.BaseType == X86ISelAddressMode::RegBase) {
-          CurDAG->SelectNodeTo(N, Opc, OpVT, MVT::Other,
-                               AM.Base.Reg, Scale, AM.IndexReg, Disp, Chain);
+          return CurDAG->SelectNodeTo(N, Opc, OpVT, MVT::Other,
+                                      AM.Base.Reg, Scale, AM.IndexReg, Disp, 
+                                      Chain)
+            .getValue(Op.ResNo);
         } else {
           SDOperand Base = CurDAG->getFrameIndex(AM.Base.FrameIndex, MVT::i32);
-          CurDAG->SelectNodeTo(N, Opc, OpVT, MVT::Other,
-                               Base, Scale, AM.IndexReg, Disp, Chain);
+          return CurDAG->SelectNodeTo(N, Opc, OpVT, MVT::Other,
+                                      Base, Scale, AM.IndexReg, Disp, Chain)
+            .getValue(Op.ResNo);
         }
       }
-      return SDOperand(N, Op.ResNo);
     }
 
     case ISD::STORE: {
@@ -430,13 +428,13 @@
         ? CurDAG->getTargetGlobalAddress(AM.GV, MVT::i32, AM.Disp)
         : getI32Imm(AM.Disp);
       if (AM.BaseType == X86ISelAddressMode::RegBase) {
-        CurDAG->SelectNodeTo(N, Opc, MVT::Other,
-                             AM.Base.Reg, Scale, AM.IndexReg, Disp, Tmp1,
-                             Chain);
+        return CurDAG->SelectNodeTo(N, Opc, MVT::Other,
+                                    AM.Base.Reg, Scale, AM.IndexReg, Disp, Tmp1,
+                                    Chain);
       } else {
         SDOperand Base = CurDAG->getFrameIndex(AM.Base.FrameIndex, MVT::i32);
-        CurDAG->SelectNodeTo(N, Opc, MVT::Other,
-                             Base, Scale, AM.IndexReg, Disp, Tmp1, Chain);
+        return CurDAG->SelectNodeTo(N, Opc, MVT::Other,
+                                  Base, Scale, AM.IndexReg, Disp, Tmp1, Chain);
       }
     }
   }





From lattner at cs.uiuc.edu  Wed Nov 30 17:02:21 2005
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Wed, 30 Nov 2005 17:02:21 -0600
Subject: [llvm-commits] CVS: llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp 
Message-ID: <200511302302.RAA11331@zion.cs.uiuc.edu>



Changes in directory llvm/lib/Target/IA64:

IA64ISelDAGToDAG.cpp updated: 1.12 -> 1.13
---
Log message:

Pay attn to the node returned by SelectNodeTo


---
Diffs of the changes:  (+28 -37)

 IA64ISelDAGToDAG.cpp |   65 +++++++++++++++++++++------------------------------
 1 files changed, 28 insertions(+), 37 deletions(-)


Index: llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp
diff -u llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp:1.12 llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp:1.13
--- llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp:1.12	Fri Nov 25 01:49:25 2005
+++ llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp	Wed Nov 30 17:02:08 2005
@@ -580,11 +580,9 @@
 
   case ISD::FrameIndex: { // TODO: reduce creepyness
     int FI = cast<FrameIndexSDNode>(N)->getIndex();
-    if (N->hasOneUse()) {
-      CurDAG->SelectNodeTo(N, IA64::MOV, MVT::i64,
-                           CurDAG->getTargetFrameIndex(FI, MVT::i64));
-      return SDOperand(N, 0);
-    }
+    if (N->hasOneUse())
+      return CurDAG->SelectNodeTo(N, IA64::MOV, MVT::i64,
+                                  CurDAG->getTargetFrameIndex(FI, MVT::i64));
     return CurDAG->getTargetNode(IA64::MOV, MVT::i64,
                                 CurDAG->getTargetFrameIndex(FI, MVT::i64));
   }
@@ -617,11 +615,11 @@
     default: N->dump(); assert(0 && "Cannot load this type!");
     case MVT::i1: { // this is a bool
       Opc = IA64::LD1; // first we load a byte, then compare for != 0
-      CurDAG->SelectNodeTo(N, IA64::CMPNE, MVT::i1, MVT::Other, 
-	CurDAG->getTargetNode(Opc, MVT::i64, Address),
-	CurDAG->getRegister(IA64::r0, MVT::i64), Chain);
-      return SDOperand(N, Op.ResNo); // XXX: early exit
-      }
+      return CurDAG->SelectNodeTo(N, IA64::CMPNE, MVT::i1, MVT::Other, 
+                                  CurDAG->getTargetNode(Opc, MVT::i64, Address),
+                                  CurDAG->getRegister(IA64::r0, MVT::i64), 
+                                  Chain).getValue(Op.ResNo);
+    }
     case MVT::i8:  Opc = IA64::LD1; break;
     case MVT::i16: Opc = IA64::LD2; break;
     case MVT::i32: Opc = IA64::LD4; break;
@@ -631,10 +629,9 @@
     case MVT::f64: Opc = IA64::LDF8; break;
     }
 
-    CurDAG->SelectNodeTo(N, Opc, N->getValueType(0), MVT::Other,
-                             Address, Chain); // TODO: comment this
-    
-    return SDOperand(N, Op.ResNo);
+    // TODO: comment this
+    return CurDAG->SelectNodeTo(N, Opc, N->getValueType(0), MVT::Other,
+                                Address, Chain).getValue(Op.ResNo);
   }
   
   case ISD::TRUNCSTORE:
@@ -648,14 +645,13 @@
       default: assert(0 && "unknown type in store");
       case MVT::i1: { // this is a bool
         Opc = IA64::ST1; // we store either 0 or 1 as a byte 
-        CurDAG->SelectNodeTo(N, Opc, MVT::Other, Address,
-	    CurDAG->getTargetNode(IA64::PADDS, MVT::i64,
-	      CurDAG->getRegister(IA64::r0, MVT::i64),
-	      CurDAG->getConstant(1, MVT::i64),
-	      Select(N->getOperand(1))),
-	    Chain);
-        return SDOperand(N, 0); // XXX: early exit
-        }
+        SDOperand Tmp = 
+          CurDAG->getTargetNode(IA64::PADDS, MVT::i64,
+                                CurDAG->getRegister(IA64::r0, MVT::i64),
+                                CurDAG->getConstant(1, MVT::i64),
+                                Select(N->getOperand(1)));
+        return CurDAG->SelectNodeTo(N, Opc, MVT::Other, Address, Tmp, Chain);
+      }
       case MVT::i64: Opc = IA64::ST8;  break;
       case MVT::f64: Opc = IA64::STF8; break;
       }
@@ -669,9 +665,8 @@
       }
     }
     
-    CurDAG->SelectNodeTo(N, Opc, MVT::Other, Select(N->getOperand(2)),
-                         Select(N->getOperand(1)), Chain);
-    return SDOperand(N, 0);
+    return CurDAG->SelectNodeTo(N, Opc, MVT::Other, Select(N->getOperand(2)),
+                                Select(N->getOperand(1)), Chain);
   }
 
   case ISD::BRCOND: {
@@ -680,8 +675,8 @@
     MachineBasicBlock *Dest =
       cast<BasicBlockSDNode>(N->getOperand(2))->getBasicBlock();
     //FIXME - we do NOT need long branches all the time
-    CurDAG->SelectNodeTo(N, IA64::BRLCOND_NOTCALL, MVT::Other, CC, CurDAG->getBasicBlock(Dest), Chain);
-    return SDOperand(N, 0);
+    return CurDAG->SelectNodeTo(N, IA64::BRLCOND_NOTCALL, MVT::Other, CC, 
+                                CurDAG->getBasicBlock(Dest), Chain);
   }
 
   case ISD::CALLSEQ_START:
@@ -689,9 +684,8 @@
     int64_t Amt = cast<ConstantSDNode>(N->getOperand(1))->getValue();
     unsigned Opc = N->getOpcode() == ISD::CALLSEQ_START ?
                        IA64::ADJUSTCALLSTACKDOWN : IA64::ADJUSTCALLSTACKUP;
-    CurDAG->SelectNodeTo(N, Opc, MVT::Other,
-                         getI64Imm(Amt), Select(N->getOperand(0)));
-    return SDOperand(N, 0);
+    return CurDAG->SelectNodeTo(N, Opc, MVT::Other,
+                                getI64Imm(Amt), Select(N->getOperand(0)));
   }
 
   case ISD::RET: {
@@ -735,20 +729,17 @@
     Chain = AR_PFSVal.getValue(1);
     Chain = CurDAG->getCopyToReg(Chain, IA64::AR_PFS, AR_PFSVal);
 
-    CurDAG->SelectNodeTo(N, IA64::RET, MVT::Other, Chain); // and then just emit a 'ret' instruction
-    
+    // and then just emit a 'ret' instruction
     // before returning, restore the ar.pfs register (set by the 'alloc' up top)
     // BuildMI(BB, IA64::MOV, 1).addReg(IA64::AR_PFS).addReg(IA64Lowering.VirtGPR);
     //
-    return SDOperand(N, 0);
+    return CurDAG->SelectNodeTo(N, IA64::RET, MVT::Other, Chain);
   }
   
   case ISD::BR:
 		 // FIXME: we don't need long branches all the time!
-    CurDAG->SelectNodeTo(N, IA64::BRL_NOTCALL, MVT::Other, N->getOperand(1),
-                         Select(N->getOperand(0)));
-    return SDOperand(N, 0);
-  
+    return CurDAG->SelectNodeTo(N, IA64::BRL_NOTCALL, MVT::Other, 
+                                N->getOperand(1), Select(N->getOperand(0)));
   }
   
   return SelectCode(Op);





From lattner at cs.uiuc.edu  Wed Nov 30 17:04:50 2005
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Wed, 30 Nov 2005 17:04:50 -0600
Subject: [llvm-commits] CVS: llvm/lib/Target/Alpha/AlphaISelDAGToDAG.cpp 
Message-ID: <200511302304.RAA11408@zion.cs.uiuc.edu>



Changes in directory llvm/lib/Target/Alpha:

AlphaISelDAGToDAG.cpp updated: 1.9 -> 1.10
---
Log message:

SelectNodeTo now returns its result, we must pay attention to it.



---
Diffs of the changes:  (+29 -40)

 AlphaISelDAGToDAG.cpp |   69 +++++++++++++++++++++-----------------------------
 1 files changed, 29 insertions(+), 40 deletions(-)


Index: llvm/lib/Target/Alpha/AlphaISelDAGToDAG.cpp
diff -u llvm/lib/Target/Alpha/AlphaISelDAGToDAG.cpp:1.9 llvm/lib/Target/Alpha/AlphaISelDAGToDAG.cpp:1.10
--- llvm/lib/Target/Alpha/AlphaISelDAGToDAG.cpp:1.9	Wed Nov 30 11:11:20 2005
+++ llvm/lib/Target/Alpha/AlphaISelDAGToDAG.cpp	Wed Nov 30 17:04:38 2005
@@ -148,8 +148,8 @@
     SDOperand CC = Select(N->getOperand(1));
     MachineBasicBlock *Dest =
       cast<BasicBlockSDNode>(N->getOperand(2))->getBasicBlock();
-    CurDAG->SelectNodeTo(N, Alpha::BNE, MVT::Other, CC, CurDAG->getBasicBlock(Dest), Chain);
-    return SDOperand(N, 0);
+    return CurDAG->SelectNodeTo(N, Alpha::BNE, MVT::Other, CC, 
+                                CurDAG->getBasicBlock(Dest), Chain);
   }
   case ISD::LOAD:
   case ISD::EXTLOAD:
@@ -178,9 +178,9 @@
           assert(opcode != ISD::SEXTLOAD && "Not zext"); break;
       }
 
-    CurDAG->SelectNodeTo(N, Opc, N->getValueType(0), MVT::Other,
-                         getI64Imm(0), Address, Chain);
-    return SDOperand(N, Op.ResNo);
+    return CurDAG->SelectNodeTo(N, Opc, N->getValueType(0), MVT::Other,
+                                getI64Imm(0), Address, 
+                                Chain).getValue(Op.ResNo);
   }
   case ISD::STORE:
   case ISD::TRUNCSTORE: {
@@ -205,51 +205,44 @@
       default: assert(0 && "Bad truncstore!");
       };
     }
-    CurDAG->SelectNodeTo(N, Opc, MVT::Other, Value, getI64Imm(0), Address, 
-                         Chain);
-    return SDOperand(N, 0);
+    return CurDAG->SelectNodeTo(N, Opc, MVT::Other, Value, getI64Imm(0),
+                                Address, Chain);
   }
 
-  case ISD::BR: {
-    CurDAG->SelectNodeTo(N, Alpha::BR_DAG, MVT::Other, N->getOperand(1),
-                         Select(N->getOperand(0)));
-    return SDOperand(N, 0);
-  }
+  case ISD::BR:
+    return CurDAG->SelectNodeTo(N, Alpha::BR_DAG, MVT::Other, N->getOperand(1),
+                                Select(N->getOperand(0)));
 
   case ISD::FrameIndex: {
     int FI = cast<FrameIndexSDNode>(N)->getIndex();
-    CurDAG->SelectNodeTo(N, Alpha::LDA, MVT::i64,
-                         CurDAG->getTargetFrameIndex(FI, MVT::i32),
-                         getI64Imm(0));
-    return SDOperand(N, 0);
+    return CurDAG->SelectNodeTo(N, Alpha::LDA, MVT::i64,
+                                CurDAG->getTargetFrameIndex(FI, MVT::i32),
+                                getI64Imm(0));
   }
   case ISD::ConstantPool: {
     Constant *C = cast<ConstantPoolSDNode>(N)->get();
     SDOperand Tmp, CPI = CurDAG->getTargetConstantPool(C, MVT::i64);
     Tmp = CurDAG->getTargetNode(Alpha::LDAHr, MVT::i64, CPI, getGlobalBaseReg());
-    CurDAG->SelectNodeTo(N, Alpha::LDAr, MVT::i64, CPI, Tmp);
-    return SDOperand(N, 0);
+    return CurDAG->SelectNodeTo(N, Alpha::LDAr, MVT::i64, CPI, Tmp);
   }
   case ISD::GlobalAddress: {
     GlobalValue *GV = cast<GlobalAddressSDNode>(N)->getGlobal();
     SDOperand GA = CurDAG->getTargetGlobalAddress(GV, MVT::i64);
-    CurDAG->SelectNodeTo(N, Alpha::LDQl, MVT::i64, GA, getGlobalBaseReg());
-    return SDOperand(N, 0);
+    return CurDAG->SelectNodeTo(N, Alpha::LDQl, MVT::i64, GA, 
+                                getGlobalBaseReg());
   }
   case ISD::ExternalSymbol:
-    CurDAG->SelectNodeTo(N, Alpha::LDQl, MVT::i64, 
-                         CurDAG->getTargetExternalSymbol(cast<ExternalSymbolSDNode>(N)->getSymbol(), MVT::i64),
-                         CurDAG->getRegister(AlphaLowering.getVRegGP(), MVT::i64));
-    return SDOperand(N, 0);
+    return CurDAG->SelectNodeTo(N, Alpha::LDQl, MVT::i64, 
+                                CurDAG->getTargetExternalSymbol(cast<ExternalSymbolSDNode>(N)->getSymbol(), MVT::i64),
+                                CurDAG->getRegister(AlphaLowering.getVRegGP(), MVT::i64));
 
   case ISD::CALLSEQ_START:
   case ISD::CALLSEQ_END: {
     unsigned Amt = cast<ConstantSDNode>(N->getOperand(1))->getValue();
     unsigned Opc = N->getOpcode() == ISD::CALLSEQ_START ?
                        Alpha::ADJUSTSTACKDOWN : Alpha::ADJUSTSTACKUP;
-    CurDAG->SelectNodeTo(N, Opc, MVT::Other,
-                         getI64Imm(Amt), Select(N->getOperand(0)));
-    return SDOperand(N, 0);
+    return CurDAG->SelectNodeTo(N, Opc, MVT::Other,
+                                getI64Imm(Amt), Select(N->getOperand(0)));
   }
   case ISD::RET: {
     SDOperand Chain = Select(N->getOperand(0));     // Token chain.
@@ -264,8 +257,7 @@
 
     // FIXME: add restoring of the RA to R26 to the chain
     // Finally, select this to a ret instruction.
-    CurDAG->SelectNodeTo(N, Alpha::RETDAG, MVT::Other, Chain);
-    return SDOperand(N, 0);
+    return CurDAG->SelectNodeTo(N, Alpha::RETDAG, MVT::Other, Chain);
   }
   case ISD::Constant: {
     int64_t val = (int64_t)cast<ConstantSDNode>(N)->getValue();
@@ -276,8 +268,7 @@
         ConstantUInt::get(Type::getPrimitiveType(Type::ULongTyID) , val);
       SDOperand Tmp, CPI = CurDAG->getTargetConstantPool(C, MVT::i64);
       Tmp = CurDAG->getTargetNode(Alpha::LDAHr, MVT::i64, CPI, getGlobalBaseReg());
-      CurDAG->SelectNodeTo(N, Alpha::LDAr, MVT::i64, CPI, Tmp);
-      return SDOperand(N, 0);
+      return CurDAG->SelectNodeTo(N, Alpha::LDAr, MVT::i64, CPI, Tmp);
     }
     break;
   }
@@ -286,15 +277,13 @@
       bool isDouble = N->getValueType(0) == MVT::f64;
       MVT::ValueType T = isDouble ? MVT::f64 : MVT::f32;
       if (CN->isExactlyValue(+0.0)) {
-        CurDAG->SelectNodeTo(N, isDouble ? Alpha::CPYST : Alpha::CPYSS, T,
-                             CurDAG->getRegister(Alpha::F31, T),
-                             CurDAG->getRegister(Alpha::F31, T));
-        return SDOperand(N, 0);
+        return CurDAG->SelectNodeTo(N, isDouble ? Alpha::CPYST : Alpha::CPYSS,
+                                    T, CurDAG->getRegister(Alpha::F31, T),
+                                    CurDAG->getRegister(Alpha::F31, T));
       } else if ( CN->isExactlyValue(-0.0)) {
-        CurDAG->SelectNodeTo(N, isDouble ? Alpha::CPYSNT : Alpha::CPYSNS, T,
-                             CurDAG->getRegister(Alpha::F31, T),
-                             CurDAG->getRegister(Alpha::F31, T));
-        return SDOperand(N, 0);
+        return CurDAG->SelectNodeTo(N, isDouble ? Alpha::CPYSNT : Alpha::CPYSNS,
+                                    T, CurDAG->getRegister(Alpha::F31, T),
+                                    CurDAG->getRegister(Alpha::F31, T));
       } else {
         abort();
       }





From lattner at cs.uiuc.edu  Wed Nov 30 17:08:58 2005
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Wed, 30 Nov 2005 17:08:58 -0600
Subject: [llvm-commits] CVS: llvm/utils/TableGen/DAGISelEmitter.cpp 
Message-ID: <200511302308.RAA11495@zion.cs.uiuc.edu>



Changes in directory llvm/utils/TableGen:

DAGISelEmitter.cpp updated: 1.77 -> 1.78
---
Log message:

Make the code generated by tblgen return the result of SelectNodeTo, to
permit future changes.


---
Diffs of the changes:  (+1 -2)

 DAGISelEmitter.cpp |    3 +--
 1 files changed, 1 insertion(+), 2 deletions(-)


Index: llvm/utils/TableGen/DAGISelEmitter.cpp
diff -u llvm/utils/TableGen/DAGISelEmitter.cpp:1.77 llvm/utils/TableGen/DAGISelEmitter.cpp:1.78
--- llvm/utils/TableGen/DAGISelEmitter.cpp:1.77	Tue Nov 29 12:44:58 2005
+++ llvm/utils/TableGen/DAGISelEmitter.cpp	Wed Nov 30 17:08:45 2005
@@ -1733,13 +1733,12 @@
       // If this instruction is the root, and if there is only one use of it,
       // use SelectNodeTo instead of getTargetNode to avoid an allocation.
       OS << "      if (N.Val->hasOneUse()) {\n";
-      OS << "        CurDAG->SelectNodeTo(N.Val, "
+      OS << "        return CurDAG->SelectNodeTo(N.Val, "
          << II.Namespace << "::" << II.TheDef->getName() << ", MVT::"
          << getEnumName(N->getType());
       for (unsigned i = 0, e = Ops.size(); i != e; ++i)
         OS << ", Tmp" << Ops[i];
       OS << ");\n";
-      OS << "        return N;\n";
       OS << "      } else {\n";
       OS << "        return CodeGenMap[N] = CurDAG->getTargetNode("
       << II.Namespace << "::" << II.TheDef->getName() << ", MVT::"





From natebegeman at mac.com  Wed Nov 30 17:58:29 2005
From: natebegeman at mac.com (Nate Begeman)
Date: Wed, 30 Nov 2005 17:58:29 -0600
Subject: [llvm-commits] CVS: llvm/utils/TableGen/CodeGenInstruction.h 
Message-ID: <200511302358.RAA21133@zion.cs.uiuc.edu>



Changes in directory llvm/utils/TableGen:

CodeGenInstruction.h updated: 1.13 -> 1.14
---
Log message:

fit into 80 columns


---
Diffs of the changes:  (+2 -2)

 CodeGenInstruction.h |    4 ++--
 1 files changed, 2 insertions(+), 2 deletions(-)


Index: llvm/utils/TableGen/CodeGenInstruction.h
diff -u llvm/utils/TableGen/CodeGenInstruction.h:1.13 llvm/utils/TableGen/CodeGenInstruction.h:1.14
--- llvm/utils/TableGen/CodeGenInstruction.h:1.13	Sat Nov 19 01:05:57 2005
+++ llvm/utils/TableGen/CodeGenInstruction.h	Wed Nov 30 17:58:18 2005
@@ -60,8 +60,8 @@
       unsigned MIOperandNo;
       unsigned MINumOperands;   // The number of operands.
 
-      /// MIOperandInfo - Default MI operand type. Note an operand may be made up
-      /// of multiple MI operands.
+      /// MIOperandInfo - Default MI operand type. Note an operand may be made
+      /// up of multiple MI operands.
       DagInit *MIOperandInfo;
 
       OperandInfo(Record *R, MVT::ValueType T, const std::string &N,





From natebegeman at mac.com  Wed Nov 30 18:06:25 2005
From: natebegeman at mac.com (Nate Begeman)
Date: Wed, 30 Nov 2005 18:06:25 -0600
Subject: [llvm-commits] CVS: llvm/utils/TableGen/CodeGenTarget.h
	DAGISelEmitter.cpp DAGISelEmitter.h 
Message-ID: <200512010006.SAA21259@zion.cs.uiuc.edu>



Changes in directory llvm/utils/TableGen:

CodeGenTarget.h updated: 1.19 -> 1.20
DAGISelEmitter.cpp updated: 1.78 -> 1.79
DAGISelEmitter.h updated: 1.36 -> 1.37
---
Log message:

Stop checking the ValueType of the CodeGenInstruction.  Instead, use the
ValueType from the RegisterClass or Operands.  This step is necessary to
allow RegisterClasses to have multiple ValueTypes.


---
Diffs of the changes:  (+62 -28)

 CodeGenTarget.h    |    9 ++++++++
 DAGISelEmitter.cpp |   55 ++++++++++++++++++++++++++++++++++++++---------------
 DAGISelEmitter.h   |   26 ++++++++++++-------------
 3 files changed, 62 insertions(+), 28 deletions(-)


Index: llvm/utils/TableGen/CodeGenTarget.h
diff -u llvm/utils/TableGen/CodeGenTarget.h:1.19 llvm/utils/TableGen/CodeGenTarget.h:1.20
--- llvm/utils/TableGen/CodeGenTarget.h:1.19	Wed Sep 14 13:02:53 2005
+++ llvm/utils/TableGen/CodeGenTarget.h	Wed Nov 30 18:06:14 2005
@@ -81,6 +81,15 @@
     if (RegisterClasses.empty()) ReadRegisterClasses();
     return RegisterClasses;
   }
+  
+  const CodeGenRegisterClass &getRegisterClass(Record *R) const {
+    const std::vector<CodeGenRegisterClass> &RC = getRegisterClasses();
+    for (unsigned i = 0, e = RC.size(); i != e; ++i)
+      if (RC[i].TheDef == R)
+        return RC[i];
+    assert(0 && "Didn't find the register class");
+    abort();
+  }
 
   const std::vector<MVT::ValueType> &getLegalValueTypes() const {
     if (LegalValueTypes.empty()) ReadLegalValueTypes();


Index: llvm/utils/TableGen/DAGISelEmitter.cpp
diff -u llvm/utils/TableGen/DAGISelEmitter.cpp:1.78 llvm/utils/TableGen/DAGISelEmitter.cpp:1.79
--- llvm/utils/TableGen/DAGISelEmitter.cpp:1.78	Wed Nov 30 17:08:45 2005
+++ llvm/utils/TableGen/DAGISelEmitter.cpp	Wed Nov 30 18:06:14 2005
@@ -531,14 +531,34 @@
     
     assert(Inst.getNumResults() == 1 && "Only supports one result instrs!");
     // Apply the result type to the node
-    bool MadeChange = UpdateNodeType(Inst.getResultType(0), TP);
+    Record *ResultNode = Inst.getResult(0);
+    assert(ResultNode->isSubClassOf("RegisterClass") &&
+           "Operands should be register classes!");
+
+    const CodeGenRegisterClass &RC = 
+      TP.getDAGISelEmitter().getTargetInfo().getRegisterClass(ResultNode);
+    
+    bool MadeChange = UpdateNodeType(RC.VT, TP);
 
     if (getNumChildren() != Inst.getNumOperands())
       TP.error("Instruction '" + getOperator()->getName() + " expects " +
                utostr(Inst.getNumOperands()) + " operands, not " +
                utostr(getNumChildren()) + " operands!");
     for (unsigned i = 0, e = getNumChildren(); i != e; ++i) {
-      MadeChange |= getChild(i)->UpdateNodeType(Inst.getOperandType(i), TP);
+      Record *OperandNode = Inst.getOperand(i);
+      MVT::ValueType VT;
+      if (OperandNode->isSubClassOf("RegisterClass")) {
+        const CodeGenRegisterClass &RC = 
+          TP.getDAGISelEmitter().getTargetInfo().getRegisterClass(OperandNode);
+        VT = RC.VT;
+      } else if (OperandNode->isSubClassOf("Operand")) {
+        VT = getValueType(OperandNode->getValueAsDef("Type"));
+      } else {
+        assert(0 && "Unknown operand type!");
+        abort();
+      }
+      
+      MadeChange |= getChild(i)->UpdateNodeType(VT, TP);
       MadeChange |= getChild(i)->ApplyTypeConstraints(TP, NotRegisters);
     }
     return MadeChange;
@@ -1021,8 +1041,8 @@
     // instruction for its operand list.  We have to assume that there is one
     // result, as we have no detailed info.
     if (!LI || LI->getSize() == 0) {
-      std::vector<MVT::ValueType> ResultTypes;
-      std::vector<MVT::ValueType> OperandTypes;
+      std::vector<Record*> Results;
+      std::vector<Record*> Operands;
       
       CodeGenInstruction &InstInfo =Target.getInstruction(Instrs[i]->getName());
       
@@ -1031,15 +1051,15 @@
         continue;
       
       // Assume the first operand is the result.
-      ResultTypes.push_back(InstInfo.OperandList[0].Ty);
+      Results.push_back(InstInfo.OperandList[0].Rec);
       
       // The rest are inputs.
       for (unsigned j = 1, e = InstInfo.OperandList.size(); j != e; ++j)
-        OperandTypes.push_back(InstInfo.OperandList[j].Ty);
+        Operands.push_back(InstInfo.OperandList[j].Rec);
       
       // Create and insert the instruction.
       Instructions.insert(std::make_pair(Instrs[i], 
-                            DAGInstruction(0, ResultTypes, OperandTypes)));
+                            DAGInstruction(0, Results, Operands)));
       continue;  // no pattern.
     }
     
@@ -1086,7 +1106,7 @@
     CodeGenInstruction &CGI = Target.getInstruction(Instrs[i]->getName());
 
     // Check that all of the results occur first in the list.
-    std::vector<MVT::ValueType> ResultTypes;
+    std::vector<Record*> Results;
     for (unsigned i = 0; i != NumResults; ++i) {
       if (i == CGI.OperandList.size())
         I->error("'" + InstResults.begin()->first +
@@ -1103,7 +1123,7 @@
         I->error("Operand $" + OpName + " class mismatch!");
       
       // Remember the return type.
-      ResultTypes.push_back(CGI.OperandList[i].Ty);
+      Results.push_back(CGI.OperandList[i].Rec);
       
       // Okay, this one checks out.
       InstResults.erase(OpName);
@@ -1114,7 +1134,7 @@
     std::map<std::string, TreePatternNode*> InstInputsCheck(InstInputs);
 
     std::vector<TreePatternNode*> ResultNodeOperands;
-    std::vector<MVT::ValueType> OperandTypes;
+    std::vector<Record*> Operands;
     for (unsigned i = NumResults, e = CGI.OperandList.size(); i != e; ++i) {
       const std::string &OpName = CGI.OperandList[i].Name;
       if (OpName.empty())
@@ -1125,10 +1145,15 @@
                  " does not appear in the instruction pattern");
       TreePatternNode *InVal = InstInputsCheck[OpName];
       InstInputsCheck.erase(OpName);   // It occurred, remove from map.
-      if (CGI.OperandList[i].Ty != InVal->getExtType())
-        I->error("Operand $" + OpName +
-                 "'s type disagrees between the operand and pattern");
-      OperandTypes.push_back(InVal->getType());
+      
+      if (InVal->isLeaf() &&
+          dynamic_cast<DefInit*>(InVal->getLeafValue())) {
+        Record *InRec = static_cast<DefInit*>(InVal->getLeafValue())->getDef();
+        if (CGI.OperandList[i].Rec != InRec)
+          I->error("Operand $" + OpName +
+                 "'s register class disagrees between the operand and pattern");
+      }
+      Operands.push_back(CGI.OperandList[i].Rec);
       
       // Construct the result for the dest-pattern operand list.
       TreePatternNode *OpNode = InVal->clone();
@@ -1155,7 +1180,7 @@
       new TreePatternNode(I->getRecord(), ResultNodeOperands);
 
     // Create and insert the instruction.
-    DAGInstruction TheInst(I, ResultTypes, OperandTypes);
+    DAGInstruction TheInst(I, Results, Operands);
     Instructions.insert(std::make_pair(I->getRecord(), TheInst));
 
     // Use a temporary tree pattern to infer all types and make sure that the


Index: llvm/utils/TableGen/DAGISelEmitter.h
diff -u llvm/utils/TableGen/DAGISelEmitter.h:1.36 llvm/utils/TableGen/DAGISelEmitter.h:1.37
--- llvm/utils/TableGen/DAGISelEmitter.h:1.36	Wed Nov  2 00:49:14 2005
+++ llvm/utils/TableGen/DAGISelEmitter.h	Wed Nov 30 18:06:14 2005
@@ -326,30 +326,30 @@
     TreePattern *Pattern;
     unsigned NumResults;
     unsigned NumOperands;
-    std::vector<MVT::ValueType> ResultTypes;
-    std::vector<MVT::ValueType> OperandTypes;
+    std::vector<Record*> Results;
+    std::vector<Record*> Operands;
     TreePatternNode *ResultPattern;
   public:
     DAGInstruction(TreePattern *TP,
-                   const std::vector<MVT::ValueType> &resultTypes,
-                   const std::vector<MVT::ValueType> &operandTypes)
-      : Pattern(TP), ResultTypes(resultTypes), OperandTypes(operandTypes), 
+                   const std::vector<Record*> &results,
+                   const std::vector<Record*> &operands)
+      : Pattern(TP), Results(results), Operands(operands), 
         ResultPattern(0) {}
 
     TreePattern *getPattern() const { return Pattern; }
-    unsigned getNumResults() const { return ResultTypes.size(); }
-    unsigned getNumOperands() const { return OperandTypes.size(); }
+    unsigned getNumResults() const { return Results.size(); }
+    unsigned getNumOperands() const { return Operands.size(); }
     
     void setResultPattern(TreePatternNode *R) { ResultPattern = R; }
     
-    MVT::ValueType getResultType(unsigned RN) const {
-      assert(RN < ResultTypes.size());
-      return ResultTypes[RN];
+    Record *getResult(unsigned RN) const {
+      assert(RN < Results.size());
+      return Results[RN];
     }
     
-    MVT::ValueType getOperandType(unsigned ON) const {
-      assert(ON < OperandTypes.size());
-      return OperandTypes[ON];
+    Record *getOperand(unsigned ON) const {
+      assert(ON < Operands.size());
+      return Operands[ON];
     }
     TreePatternNode *getResultPattern() const { return ResultPattern; }
   };





From natebegeman at mac.com  Wed Nov 30 18:12:16 2005
From: natebegeman at mac.com (Nate Begeman)
Date: Wed, 30 Nov 2005 18:12:16 -0600
Subject: [llvm-commits] CVS: llvm/utils/TableGen/CodeGenInstruction.h
	CodeGenTarget.cpp 
Message-ID: <200512010012.SAA21905@zion.cs.uiuc.edu>



Changes in directory llvm/utils/TableGen:

CodeGenInstruction.h updated: 1.14 -> 1.15
CodeGenTarget.cpp updated: 1.44 -> 1.45
---
Log message:

Nuke CodeGenInstruction's ValueType member, it is no longer used.


---
Diffs of the changes:  (+7 -18)

 CodeGenInstruction.h |   12 +++---------
 CodeGenTarget.cpp    |   13 ++++---------
 2 files changed, 7 insertions(+), 18 deletions(-)


Index: llvm/utils/TableGen/CodeGenInstruction.h
diff -u llvm/utils/TableGen/CodeGenInstruction.h:1.14 llvm/utils/TableGen/CodeGenInstruction.h:1.15
--- llvm/utils/TableGen/CodeGenInstruction.h:1.14	Wed Nov 30 17:58:18 2005
+++ llvm/utils/TableGen/CodeGenInstruction.h	Wed Nov 30 18:12:04 2005
@@ -39,10 +39,6 @@
       ///
       Record *Rec;
 
-      /// Ty - The MachineValueType of the operand.
-      ///
-      MVT::ValueType Ty;
-
       /// Name - If this operand was assigned a symbolic name, this is it,
       /// otherwise, it's empty.
       std::string Name;
@@ -64,11 +60,9 @@
       /// up of multiple MI operands.
       DagInit *MIOperandInfo;
 
-      OperandInfo(Record *R, MVT::ValueType T, const std::string &N,
-                  const std::string &PMN, unsigned MION, unsigned MINO,
-                  DagInit *MIOI)
-
-        : Rec(R), Ty(T), Name(N), PrinterMethodName(PMN), MIOperandNo(MION),
+      OperandInfo(Record *R, const std::string &N, const std::string &PMN, 
+                  unsigned MION, unsigned MINO, DagInit *MIOI)
+        : Rec(R), Name(N), PrinterMethodName(PMN), MIOperandNo(MION),
           MINumOperands(MINO), MIOperandInfo(MIOI) {}
     };
 


Index: llvm/utils/TableGen/CodeGenTarget.cpp
diff -u llvm/utils/TableGen/CodeGenTarget.cpp:1.44 llvm/utils/TableGen/CodeGenTarget.cpp:1.45
--- llvm/utils/TableGen/CodeGenTarget.cpp:1.44	Tue Nov 29 00:19:38 2005
+++ llvm/utils/TableGen/CodeGenTarget.cpp	Wed Nov 30 18:12:04 2005
@@ -276,21 +276,17 @@
       throw "Illegal operand for the '" + R->getName() + "' instruction!";
 
     Record *Rec = Arg->getDef();
-    MVT::ValueType Ty;
     std::string PrintMethod = "printOperand";
     unsigned NumOps = 1;
     DagInit *MIOpInfo = 0;
-    if (Rec->isSubClassOf("RegisterClass")) {
-      Ty = getValueType(Rec->getValueAsDef("RegType"));
-    } else if (Rec->isSubClassOf("Operand")) {
-      Ty = getValueType(Rec->getValueAsDef("Type"));
+    if (Rec->isSubClassOf("Operand")) {
       PrintMethod = Rec->getValueAsString("PrintMethod");
       NumOps = Rec->getValueAsInt("NumMIOperands");
       MIOpInfo = Rec->getValueAsDag("MIOperandInfo");
     } else if (Rec->getName() == "variable_ops") {
       hasVariableNumberOfOperands = true;
       continue;
-    } else
+    } else if (!Rec->isSubClassOf("RegisterClass"))
       throw "Unknown operand class '" + Rec->getName() +
             "' in instruction '" + R->getName() + "' instruction!";
 
@@ -302,9 +298,8 @@
       throw "In instruction '" + R->getName() + "', operand #" + utostr(i) +
         " has the same name as a previous operand!";
     
-    OperandList.push_back(OperandInfo(Rec, Ty, DI->getArgName(i),
-                                      PrintMethod, MIOperandNo, NumOps,
-                                      MIOpInfo));
+    OperandList.push_back(OperandInfo(Rec, DI->getArgName(i), PrintMethod, 
+                                      MIOperandNo, NumOps, MIOpInfo));
     MIOperandNo += NumOps;
   }
 }





From evan.cheng at apple.com  Wed Nov 30 18:18:57 2005
From: evan.cheng at apple.com (Evan Cheng)
Date: Wed, 30 Nov 2005 18:18:57 -0600
Subject: [llvm-commits] CVS: llvm/include/llvm/CodeGen/SelectionDAG.h 
Message-ID: <200512010018.SAA22479@zion.cs.uiuc.edu>



Changes in directory llvm/include/llvm/CodeGen:

SelectionDAG.h updated: 1.74 -> 1.75
---
Log message:

Teach tblgen to accept register source operands in patterns, e.g.

def SHL8rCL  : I<0xD2, MRM4r, (ops R8 :$dst, R8 :$src),
                 "shl{b} {%cl, $dst|$dst, %CL}",
                 [(set R8:$dst, (shl R8:$src, CL))]>, Imp<[CL],[]>;

This generates a CopyToReg operand and added its 2nd result to the shl as
a flag operand.


---
Diffs of the changes:  (+14 -0)

 SelectionDAG.h |   14 ++++++++++++++
 1 files changed, 14 insertions(+)


Index: llvm/include/llvm/CodeGen/SelectionDAG.h
diff -u llvm/include/llvm/CodeGen/SelectionDAG.h:1.74 llvm/include/llvm/CodeGen/SelectionDAG.h:1.75
--- llvm/include/llvm/CodeGen/SelectionDAG.h:1.74	Wed Nov 30 16:44:37 2005
+++ llvm/include/llvm/CodeGen/SelectionDAG.h	Wed Nov 30 18:18:45 2005
@@ -143,6 +143,20 @@
     if (Flag.Val) Ops.push_back(Flag);
     return getNode(ISD::CopyToReg, VTs, Ops);
   }
+
+  // Similar to last getCopyToReg() except parameter Reg is a SDOperand
+  SDOperand getCopyToReg(SDOperand Chain, SDOperand Reg, SDOperand N,
+                         SDOperand Flag) {
+    std::vector<MVT::ValueType> VTs;
+    VTs.push_back(MVT::Other);
+    VTs.push_back(MVT::Flag);
+    std::vector<SDOperand> Ops;
+    Ops.push_back(Chain);
+    Ops.push_back(Reg);
+    Ops.push_back(N);
+    if (Flag.Val) Ops.push_back(Flag);
+    return getNode(ISD::CopyToReg, VTs, Ops);
+  }
   
   SDOperand getCopyFromReg(SDOperand Chain, unsigned Reg, MVT::ValueType VT) {
     std::vector<MVT::ValueType> ResultTys;





From evan.cheng at apple.com  Wed Nov 30 18:18:57 2005
From: evan.cheng at apple.com (Evan Cheng)
Date: Wed, 30 Nov 2005 18:18:57 -0600
Subject: [llvm-commits] CVS: llvm/utils/TableGen/DAGISelEmitter.cpp
	DAGISelEmitter.h 
Message-ID: <200512010018.SAA22485@zion.cs.uiuc.edu>



Changes in directory llvm/utils/TableGen:

DAGISelEmitter.cpp updated: 1.79 -> 1.80
DAGISelEmitter.h updated: 1.37 -> 1.38
---
Log message:

Teach tblgen to accept register source operands in patterns, e.g.

def SHL8rCL  : I<0xD2, MRM4r, (ops R8 :$dst, R8 :$src),
                 "shl{b} {%cl, $dst|$dst, %CL}",
                 [(set R8:$dst, (shl R8:$src, CL))]>, Imp<[CL],[]>;

This generates a CopyToReg operand and added its 2nd result to the shl as
a flag operand.


---
Diffs of the changes:  (+69 -8)

 DAGISelEmitter.cpp |   72 +++++++++++++++++++++++++++++++++++++++++++++++------
 DAGISelEmitter.h   |    5 ++-
 2 files changed, 69 insertions(+), 8 deletions(-)


Index: llvm/utils/TableGen/DAGISelEmitter.cpp
diff -u llvm/utils/TableGen/DAGISelEmitter.cpp:1.79 llvm/utils/TableGen/DAGISelEmitter.cpp:1.80
--- llvm/utils/TableGen/DAGISelEmitter.cpp:1.79	Wed Nov 30 18:06:14 2005
+++ llvm/utils/TableGen/DAGISelEmitter.cpp	Wed Nov 30 18:18:45 2005
@@ -1574,7 +1574,7 @@
 /// matches, and the SDNode for the result has the RootName specified name.
 void DAGISelEmitter::EmitMatchForPattern(TreePatternNode *N,
                                          const std::string &RootName,
-                                     std::map<std::string,std::string> &VarMap,
+                                         std::map<std::string,std::string> &VarMap,
                                          unsigned PatternNo, std::ostream &OS) {
   if (N->isLeaf()) {
     if (IntInit *II = dynamic_cast<IntInit*>(N->getLeafValue())) {
@@ -1637,7 +1637,8 @@
       // Handle leaves of various types.
       if (DefInit *DI = dynamic_cast<DefInit*>(Child->getLeafValue())) {
         Record *LeafRec = DI->getDef();
-        if (LeafRec->isSubClassOf("RegisterClass")) {
+        if (LeafRec->isSubClassOf("RegisterClass") ||
+            LeafRec->isSubClassOf("Register")) {
           // Handle register references.  Nothing to do here.
         } else if (LeafRec->isSubClassOf("ValueType")) {
           // Make sure this is the specified value type.
@@ -1671,12 +1672,60 @@
        << ".Val)) goto P" << PatternNo << "Fail;\n";
 }
 
+/// getRegisterValueType - Look up and return ValueType of specified record
+static MVT::ValueType getRegisterValueType(Record *R, const CodeGenTarget &T) {
+  const std::vector<CodeGenRegisterClass> &RegisterClasses =
+    T.getRegisterClasses();
+
+  for (unsigned i = 0, e = RegisterClasses.size(); i != e; ++i) {
+    const CodeGenRegisterClass &RC = RegisterClasses[i];
+    for (unsigned ei = 0, ee = RC.Elements.size(); ei != ee; ++ei) {
+      if (R == RC.Elements[ei]) {
+        return RC.VT;
+      }
+    }
+  }
+
+  return MVT::Other;
+}
+
+
+/// EmitCopyToRegsForPattern - Emit the flag operands for the DAG that will be
+/// built in CodeGenPatternResult.
+void DAGISelEmitter::EmitCopyToRegsForPattern(TreePatternNode *N,
+                                              const std::string &RootName,
+                                              std::ostream &OS, bool &InFlag) {
+  const CodeGenTarget &T = getTargetInfo();
+  for (unsigned i = 0, e = N->getNumChildren(); i != e; ++i) {
+    TreePatternNode *Child = N->getChild(i);
+    if (!Child->isLeaf()) {
+      EmitCopyToRegsForPattern(Child, RootName + utostr(i), OS, InFlag);
+    } else {
+      if (DefInit *DI = dynamic_cast<DefInit*>(Child->getLeafValue())) {
+        Record *RR = DI->getDef();
+        if (RR->isSubClassOf("Register")) {
+          MVT::ValueType RVT = getRegisterValueType(RR, T);
+          if (!InFlag) {
+            OS << "      SDOperand InFlag;  // Null incoming flag value.\n";
+            InFlag = true;
+          }
+          OS << "      InFlag = CurDAG->getCopyToReg(CurDAG->getEntryNode()"
+             << ", CurDAG->getRegister(" << getQualifiedName(RR)
+             << ", MVT::" << getEnumName(RVT) << ")"
+             << ", " << RootName << i << ", InFlag).getValue(1);\n";
+
+        }
+      }
+    }
+  }
+}
+
 /// CodeGenPatternResult - Emit the action for a pattern.  Now that it has
 /// matched, we actually have to build a DAG!
 unsigned DAGISelEmitter::
 CodeGenPatternResult(TreePatternNode *N, unsigned &Ctr,
                      std::map<std::string,std::string> &VariableMap, 
-                     std::ostream &OS, bool isRoot) {
+                     std::ostream &OS, bool InFlag, bool isRoot) {
   // This is something selected from the pattern we matched.
   if (!N->getName().empty()) {
     assert(!isRoot && "Root of pattern cannot be a leaf!");
@@ -1742,7 +1791,8 @@
     // Emit all of the operands.
     std::vector<unsigned> Ops;
     for (unsigned i = 0, e = N->getNumChildren(); i != e; ++i)
-      Ops.push_back(CodeGenPatternResult(N->getChild(i), Ctr, VariableMap, OS));
+      Ops.push_back(CodeGenPatternResult(N->getChild(i),
+                                         Ctr, VariableMap, OS, InFlag));
 
     CodeGenInstruction &II = Target.getInstruction(Op->getName());
     unsigned ResNo = Ctr++;
@@ -1763,6 +1813,8 @@
          << getEnumName(N->getType());
       for (unsigned i = 0, e = Ops.size(); i != e; ++i)
         OS << ", Tmp" << Ops[i];
+      if (InFlag)
+        OS << ", InFlag";
       OS << ");\n";
       OS << "      } else {\n";
       OS << "        return CodeGenMap[N] = CurDAG->getTargetNode("
@@ -1770,13 +1822,16 @@
       << getEnumName(N->getType());
       for (unsigned i = 0, e = Ops.size(); i != e; ++i)
         OS << ", Tmp" << Ops[i];
+      if (InFlag)
+        OS << ", InFlag";
       OS << ");\n";
       OS << "      }\n";
     }
     return ResNo;
   } else if (Op->isSubClassOf("SDNodeXForm")) {
     assert(N->getNumChildren() == 1 && "node xform should have one child!");
-    unsigned OpVal = CodeGenPatternResult(N->getChild(0), Ctr, VariableMap, OS);
+    unsigned OpVal = CodeGenPatternResult(N->getChild(0),
+                                          Ctr, VariableMap, OS, InFlag);
     
     unsigned ResNo = Ctr++;
     OS << "      SDOperand Tmp" << ResNo << " = Transform_" << Op->getName()
@@ -1886,10 +1941,13 @@
     // an unresolved type to add a check for, this returns true and we iterate,
     // otherwise we are done.
   } while (InsertOneTypeCheck(Pat, Pattern.first, "N", PatternNo, OS));
+
+  bool InFlag = false;
+  EmitCopyToRegsForPattern(Pattern.first, "N", OS, InFlag);
   
   unsigned TmpNo = 0;
-  CodeGenPatternResult(Pattern.second, TmpNo,
-                       VariableMap, OS, true /*the root*/);
+  CodeGenPatternResult(Pattern.second,
+                       TmpNo, VariableMap, OS, InFlag, true /*the root*/);
   delete Pat;
   
   OS << "    }\n  P" << PatternNo << "Fail:\n";


Index: llvm/utils/TableGen/DAGISelEmitter.h
diff -u llvm/utils/TableGen/DAGISelEmitter.h:1.37 llvm/utils/TableGen/DAGISelEmitter.h:1.38
--- llvm/utils/TableGen/DAGISelEmitter.h:1.37	Wed Nov 30 18:06:14 2005
+++ llvm/utils/TableGen/DAGISelEmitter.h	Wed Nov 30 18:18:45 2005
@@ -418,9 +418,12 @@
   void EmitMatchForPattern(TreePatternNode *N, const std::string &RootName,
                            std::map<std::string,std::string> &VarMap,
                            unsigned PatternNo, std::ostream &OS);
+  void EmitCopyToRegsForPattern(TreePatternNode *N, const std::string &RootName,
+                                std::ostream &OS, bool &InFlag);
   unsigned CodeGenPatternResult(TreePatternNode *N, unsigned &Ctr,
                                 std::map<std::string,std::string> &VariableMap, 
-                                std::ostream &OS, bool isRoot = false);      
+                                std::ostream &OS, bool InFlag,
+                                bool isRoot = false);
   void EmitCodeForPattern(PatternToMatch &Pattern, std::ostream &OS);
   void EmitInstructionSelector(std::ostream &OS);
 };





From evan.cheng at apple.com  Wed Nov 30 18:42:02 2005
From: evan.cheng at apple.com (Evan Cheng)
Date: Wed, 30 Nov 2005 18:42:02 -0600
Subject: [llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp 
Message-ID: <200512010042.SAA22863@zion.cs.uiuc.edu>



Changes in directory llvm/lib/Target/PowerPC:

PPCISelDAGToDAG.cpp updated: 1.132 -> 1.133
---
Log message:

Use a getCopyToReg() variant to generate a flaggy CopyToReg node.


---
Diffs of the changes:  (+2 -8)

 PPCISelDAGToDAG.cpp |   10 ++--------
 1 files changed, 2 insertions(+), 8 deletions(-)


Index: llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
diff -u llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp:1.132 llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp:1.133
--- llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp:1.132	Wed Nov 30 16:53:06 2005
+++ llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp	Wed Nov 30 18:41:50 2005
@@ -720,14 +720,8 @@
   // Force the ccreg into CR7.
   SDOperand CR7Reg = CurDAG->getRegister(PPC::CR7, MVT::i32);
   
-  std::vector<MVT::ValueType> VTs;
-  VTs.push_back(MVT::Other);
-  VTs.push_back(MVT::Flag);    // NONSTANDARD CopyToReg node: defines a flag
-  std::vector<SDOperand> Ops;
-  Ops.push_back(CurDAG->getEntryNode());
-  Ops.push_back(CR7Reg);
-  Ops.push_back(CCReg);
-  CCReg = CurDAG->getNode(ISD::CopyToReg, VTs, Ops).getValue(1);
+  SDOperand InFlag;  // Null incoming flag value.
+  CCReg = CurDAG->getCopyToReg(CurDAG->getEntryNode(), CR7Reg, CCReg, InFlag);
   
   if (TLI.getTargetMachine().getSubtarget<PPCSubtarget>().isGigaProcessor())
     IntCR = CurDAG->getTargetNode(PPC::MFOCRF, MVT::i32, CR7Reg, CCReg);





From evan.cheng at apple.com  Wed Nov 30 18:44:06 2005
From: evan.cheng at apple.com (Evan Cheng)
Date: Wed, 30 Nov 2005 18:44:06 -0600
Subject: [llvm-commits] CVS: llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
	X86InstrInfo.td 
Message-ID: <200512010044.SAA24139@zion.cs.uiuc.edu>



Changes in directory llvm/lib/Target/X86:

X86ISelDAGToDAG.cpp updated: 1.5 -> 1.6
X86InstrInfo.td updated: 1.144 -> 1.145
---
Log message:

Proper support for shifts with register shift value.


---
Diffs of the changes:  (+24 -44)

 X86ISelDAGToDAG.cpp |   41 ++++++-----------------------------------
 X86InstrInfo.td     |   27 ++++++++++++++++++---------
 2 files changed, 24 insertions(+), 44 deletions(-)


Index: llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
diff -u llvm/lib/Target/X86/X86ISelDAGToDAG.cpp:1.5 llvm/lib/Target/X86/X86ISelDAGToDAG.cpp:1.6
--- llvm/lib/Target/X86/X86ISelDAGToDAG.cpp:1.5	Wed Nov 30 16:59:19 2005
+++ llvm/lib/Target/X86/X86ISelDAGToDAG.cpp	Wed Nov 30 18:43:55 2005
@@ -134,10 +134,11 @@
 void X86DAGToDAGISel::SelectAddress(SDOperand N, X86ISelAddressMode &AM) {
   MatchAddress(N, AM);
 
-  if (AM.BaseType == X86ISelAddressMode::RegBase && !AM.Base.Reg.Val) {
-    AM.Base.Reg = CurDAG->getRegister(0, MVT::i32);
-  } else {
-    AM.Base.Reg = Select(AM.Base.Reg);
+  if (AM.BaseType == X86ISelAddressMode::RegBase) {
+    if (AM.Base.Reg.Val)
+      AM.Base.Reg = Select(AM.Base.Reg);
+    else
+      AM.Base.Reg = CurDAG->getRegister(0, MVT::i32);
   }
   if (!AM.IndexReg.Val) {
     AM.IndexReg = CurDAG->getRegister(0, MVT::i32);
@@ -277,10 +278,8 @@
     default: break;
 
     case ISD::SHL:
-    case ISD::SRL:
-    case ISD::SRA:
       if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N->getOperand(1))) {
-        if (N->getOpcode() == ISD::SHL && CN->getValue() == 1) {
+        if (CN->getValue() == 1) {
           // X = SHL Y, 1  -> X = ADD Y, Y
           switch (OpVT) {
             default: assert(0 && "Cannot shift this type!");
@@ -291,34 +290,6 @@
           SDOperand Tmp0 = Select(N->getOperand(0));
           return CurDAG->SelectNodeTo(N, Opc, MVT::i32, Tmp0, Tmp0);
         }
-      } else {
-        static const unsigned SHLTab[] = {
-          X86::SHL8rCL, X86::SHL16rCL, X86::SHL32rCL
-        };
-        static const unsigned SRLTab[] = {
-          X86::SHR8rCL, X86::SHR16rCL, X86::SHR32rCL
-        };
-        static const unsigned SRATab[] = {
-          X86::SAR8rCL, X86::SAR16rCL, X86::SAR32rCL
-        };
-
-        switch (OpVT) {
-          default: assert(0 && "Cannot shift this type!");
-          case MVT::i1:
-          case MVT::i8:  Opc = 0; break;
-          case MVT::i16: Opc = 1; break;
-          case MVT::i32: Opc = 2; break;
-        }
-
-        switch (N->getOpcode()) {
-          default: assert(0 && "Unreachable!");
-          case ISD::SHL: Opc = SHLTab[Opc]; break;
-          case ISD::SRL: Opc = SRLTab[Opc]; break;
-          case ISD::SRA: Opc = SRATab[Opc]; break;
-        }
-
-        SDOperand Tmp0 = Select(N->getOperand(0));
-        return CurDAG->SelectNodeTo(N, Opc, MVT::i32, Tmp0);
       }
       break;
 


Index: llvm/lib/Target/X86/X86InstrInfo.td
diff -u llvm/lib/Target/X86/X86InstrInfo.td:1.144 llvm/lib/Target/X86/X86InstrInfo.td:1.145
--- llvm/lib/Target/X86/X86InstrInfo.td:1.144	Wed Nov 30 12:54:35 2005
+++ llvm/lib/Target/X86/X86InstrInfo.td	Wed Nov 30 18:43:55 2005
@@ -892,11 +892,14 @@
 // Shift instructions
 // FIXME: provide shorter instructions when imm8 == 1
 def SHL8rCL  : I<0xD2, MRM4r, (ops R8 :$dst, R8 :$src),
-                 "shl{b} {%cl, $dst|$dst, %CL}", []>, Imp<[CL],[]>;
+                 "shl{b} {%cl, $dst|$dst, %CL}",
+                 [(set R8:$dst, (shl R8:$src, CL))]>, Imp<[CL],[]>;
 def SHL16rCL : I<0xD3, MRM4r, (ops R16:$dst, R16:$src),
-                 "shl{w} {%cl, $dst|$dst, %CL}", []>, Imp<[CL],[]>, OpSize;
+                 "shl{w} {%cl, $dst|$dst, %CL}",
+                 [(set R16:$dst, (shl R16:$src, CL))]>, Imp<[CL],[]>, OpSize;
 def SHL32rCL : I<0xD3, MRM4r, (ops R32:$dst, R32:$src),
-                 "shl{l} {%cl, $dst|$dst, %CL}", []>, Imp<[CL],[]>;
+                 "shl{l} {%cl, $dst|$dst, %CL}",
+                 [(set R32:$dst, (shl R32:$src, CL))]>, Imp<[CL],[]>;
 
 def SHL8ri   : Ii8<0xC0, MRM4r, (ops R8 :$dst, R8 :$src1, i8imm:$src2),
                    "shl{b} {$src2, $dst|$dst, $src2}",
@@ -926,11 +929,14 @@
 }
 
 def SHR8rCL  : I<0xD2, MRM5r, (ops R8 :$dst, R8 :$src),
-                 "shr{b} {%cl, $dst|$dst, %CL}", []>, Imp<[CL],[]>;
+                 "shr{b} {%cl, $dst|$dst, %CL}",
+                 [(set R8:$dst, (srl R8:$src, CL))]>, Imp<[CL],[]>;
 def SHR16rCL : I<0xD3, MRM5r, (ops R16:$dst, R16:$src),
-                 "shr{w} {%cl, $dst|$dst, %CL}", []>, Imp<[CL],[]>, OpSize;
+                 "shr{w} {%cl, $dst|$dst, %CL}",
+                 [(set R16:$dst, (srl R16:$src, CL))]>, Imp<[CL],[]>, OpSize;
 def SHR32rCL : I<0xD3, MRM5r, (ops R32:$dst, R32:$src),
-                 "shr{l} {%cl, $dst|$dst, %CL}", []>, Imp<[CL],[]>;
+                 "shr{l} {%cl, $dst|$dst, %CL}",
+                 [(set R32:$dst, (srl R32:$src, CL))]>, Imp<[CL],[]>;
 
 def SHR8ri   : Ii8<0xC0, MRM5r, (ops R8:$dst, R8:$src1, i8imm:$src2),
                    "shr{b} {$src2, $dst|$dst, $src2}",
@@ -958,11 +964,14 @@
 }
 
 def SAR8rCL  : I<0xD2, MRM7r, (ops R8 :$dst, R8 :$src),
-                 "sar{b} {%cl, $dst|$dst, %CL}", []>, Imp<[CL],[]>;
+                 "sar{b} {%cl, $dst|$dst, %CL}",
+                 [(set R8:$dst, (sra R8:$src, CL))]>, Imp<[CL],[]>;
 def SAR16rCL : I<0xD3, MRM7r, (ops R16:$dst, R16:$src),
-                 "sar{w} {%cl, $dst|$dst, %CL}", []>, Imp<[CL],[]>, OpSize;
+                 "sar{w} {%cl, $dst|$dst, %CL}",
+                 [(set R16:$dst, (sra R16:$src, CL))]>, Imp<[CL],[]>, OpSize;
 def SAR32rCL : I<0xD3, MRM7r, (ops R32:$dst, R32:$src),
-                 "sar{l} {%cl, $dst|$dst, %CL}", []>, Imp<[CL],[]>;
+                 "sar{l} {%cl, $dst|$dst, %CL}",
+                 [(set R32:$dst, (sra R32:$src, CL))]>, Imp<[CL],[]>;
 
 def SAR8ri   : Ii8<0xC0, MRM7r, (ops R8 :$dst, R8 :$src1, i8imm:$src2),
                    "sar{b} {$src2, $dst|$dst, $src2}",





From alenhar2 at cs.uiuc.edu  Wed Nov 30 19:53:21 2005
From: alenhar2 at cs.uiuc.edu (Andrew Lenharth)
Date: Wed, 30 Nov 2005 19:53:21 -0600
Subject: [llvm-commits] CVS: llvm/lib/Target/Alpha/AlphaISelDAGToDAG.cpp 
Message-ID: <200512010153.TAA28540@zion.cs.uiuc.edu>



Changes in directory llvm/lib/Target/Alpha:

AlphaISelDAGToDAG.cpp updated: 1.10 -> 1.11
---
Log message:

Flags where I think I need them, quick, before the nightly tester starts

---
Diffs of the changes:  (+42 -23)

 AlphaISelDAGToDAG.cpp |   65 ++++++++++++++++++++++++++++++++------------------
 1 files changed, 42 insertions(+), 23 deletions(-)


Index: llvm/lib/Target/Alpha/AlphaISelDAGToDAG.cpp
diff -u llvm/lib/Target/Alpha/AlphaISelDAGToDAG.cpp:1.10 llvm/lib/Target/Alpha/AlphaISelDAGToDAG.cpp:1.11
--- llvm/lib/Target/Alpha/AlphaISelDAGToDAG.cpp:1.10	Wed Nov 30 17:04:38 2005
+++ llvm/lib/Target/Alpha/AlphaISelDAGToDAG.cpp	Wed Nov 30 19:53:10 2005
@@ -70,6 +70,7 @@
     
 private:
     SDOperand getGlobalBaseReg();
+    SDOperand getRASaveReg();
     SDOperand SelectCALL(SDOperand Op);
 
   };
@@ -79,7 +80,17 @@
 /// GOT address into a register.
 ///
 SDOperand AlphaDAGToDAGISel::getGlobalBaseReg() {
-  return CurDAG->getRegister(AlphaLowering.getVRegGP(), MVT::i64);
+  return CurDAG->getCopyFromReg(CurDAG->getEntryNode(), 
+                                AlphaLowering.getVRegGP(), 
+                                MVT::i64);
+}
+
+/// getRASaveReg - Grab the return address
+///
+SDOperand AlphaDAGToDAGISel::getRASaveReg() {
+  return CurDAG->getCopyFromReg(CurDAG->getEntryNode(),
+                                AlphaLowering.getVRegRA(), 
+                                MVT::i64);
 }
 
 /// InstructionSelectBasicBlock - This callback is invoked by
@@ -234,7 +245,7 @@
   case ISD::ExternalSymbol:
     return CurDAG->SelectNodeTo(N, Alpha::LDQl, MVT::i64, 
                                 CurDAG->getTargetExternalSymbol(cast<ExternalSymbolSDNode>(N)->getSymbol(), MVT::i64),
-                                CurDAG->getRegister(AlphaLowering.getVRegGP(), MVT::i64));
+                                getGlobalBaseReg());
 
   case ISD::CALLSEQ_START:
   case ISD::CALLSEQ_END: {
@@ -246,18 +257,20 @@
   }
   case ISD::RET: {
     SDOperand Chain = Select(N->getOperand(0));     // Token chain.
+    SDOperand InFlag;
 
     if (N->getNumOperands() == 2) {
       SDOperand Val = Select(N->getOperand(1));
       if (N->getOperand(1).getValueType() == MVT::i64) {
-        Chain = CurDAG->getCopyToReg(Chain, Alpha::R0, Val);
+        Chain = CurDAG->getCopyToReg(Chain, Alpha::R0, Val, InFlag);
+        InFlag = Chain.getValue(1);
       }
     }
-    //BuildMI(BB, Alpha::RET, 2, Alpha::R31).addReg(Alpha::R26).addImm(1);
-
-    // FIXME: add restoring of the RA to R26 to the chain
+    Chain = CurDAG->getCopyToReg(Chain, Alpha::R26, getRASaveReg(), InFlag);
+    InFlag = Chain.getValue(1);
+    
     // Finally, select this to a ret instruction.
-    return CurDAG->SelectNodeTo(N, Alpha::RETDAG, MVT::Other, Chain);
+    return CurDAG->SelectNodeTo(N, Alpha::RETDAG, MVT::Other, Chain, InFlag);
   }
   case ISD::Constant: {
     int64_t val = (int64_t)cast<ConstantSDNode>(N)->getValue();
@@ -401,8 +414,8 @@
   SDNode *N = Op.Val;
   SDOperand Chain = Select(N->getOperand(0));
   SDOperand Addr = Select(N->getOperand(1));
+  SDOperand InFlag;  // Null incoming flag value.
 
-//   unsigned CallOpcode;
    std::vector<SDOperand> CallOperands;
    std::vector<MVT::ValueType> TypeOperands;
   
@@ -418,14 +431,6 @@
    static const unsigned args_float[] = {Alpha::F16, Alpha::F17, Alpha::F18,
                                          Alpha::F19, Alpha::F20, Alpha::F21};
    
-   for (int i = 0; i < std::min(6, count); ++i) {
-     if (MVT::isInteger(TypeOperands[i])) {
-       Chain = CurDAG->getCopyToReg(Chain, args_int[i], CallOperands[i]);
-     } else if (TypeOperands[i] == MVT::f32 || TypeOperands[i] == MVT::f64) {
-       Chain = CurDAG->getCopyToReg(Chain, args_float[i], CallOperands[i]);
-     } else
-       assert(0 && "Unknown operand"); 
-   }
    for (int i = 6; i < count; ++i) {
      unsigned Opc = Alpha::WTF;
      if (MVT::isInteger(TypeOperands[i])) {
@@ -438,30 +443,44 @@
        assert(0 && "Unknown operand"); 
      Chain = CurDAG->getTargetNode(Opc, MVT::Other, CallOperands[i], 
                                    getI64Imm((i - 6) * 8), 
-                                   CurDAG->getRegister(Alpha::R30, MVT::i64),
+                                   CurDAG->getCopyFromReg(Chain, Alpha::R30, MVT::i64),
                                    Chain);
    }
+   for (int i = 0; i < std::min(6, count); ++i) {
+     if (MVT::isInteger(TypeOperands[i])) {
+       Chain = CurDAG->getCopyToReg(Chain, args_int[i], CallOperands[i], InFlag);
+       InFlag = Chain.getValue(1);
+     } else if (TypeOperands[i] == MVT::f32 || TypeOperands[i] == MVT::f64) {
+       Chain = CurDAG->getCopyToReg(Chain, args_float[i], CallOperands[i], InFlag);
+       InFlag = Chain.getValue(1);
+     } else
+       assert(0 && "Unknown operand"); 
+   }
+
 
-   Chain = CurDAG->getCopyToReg(Chain, Alpha::R27, Addr);
+   Chain = CurDAG->getCopyToReg(Chain, Alpha::R27, Addr, InFlag);
+   InFlag = Chain.getValue(1);
    // Finally, once everything is in registers to pass to the call, emit the
    // call itself.
-   Chain = CurDAG->getTargetNode(Alpha::JSRDAG, MVT::Other, Chain );
-  
+   Chain = CurDAG->getTargetNode(Alpha::JSRDAG, MVT::Other, MVT::Flag, 
+                                 Chain, InFlag );
+   InFlag = Chain.getValue(1);
+
    std::vector<SDOperand> CallResults;
   
    switch (N->getValueType(0)) {
    default: assert(0 && "Unexpected ret value!");
      case MVT::Other: break;
    case MVT::i64:
-     Chain = CurDAG->getCopyFromReg(Chain, Alpha::R0, MVT::i64).getValue(1);
+     Chain = CurDAG->getCopyFromReg(Chain, Alpha::R0, MVT::i64, InFlag).getValue(1);
      CallResults.push_back(Chain.getValue(0));
      break;
    case MVT::f32:
-     Chain = CurDAG->getCopyFromReg(Chain, Alpha::F0, MVT::f32).getValue(1);
+     Chain = CurDAG->getCopyFromReg(Chain, Alpha::F0, MVT::f32, InFlag).getValue(1);
      CallResults.push_back(Chain.getValue(0));
      break;
    case MVT::f64:
-     Chain = CurDAG->getCopyFromReg(Chain, Alpha::F0, MVT::f64).getValue(1);
+     Chain = CurDAG->getCopyFromReg(Chain, Alpha::F0, MVT::f64, InFlag).getValue(1);
      CallResults.push_back(Chain.getValue(0));
      break;
    }





From lattner at cs.uiuc.edu  Wed Nov 30 21:50:30 2005
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Wed, 30 Nov 2005 21:50:30 -0600
Subject: [llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp 
Message-ID: <200512010350.VAA13092@zion.cs.uiuc.edu>



Changes in directory llvm/lib/Target/PowerPC:

PPCISelDAGToDAG.cpp updated: 1.133 -> 1.134
---
Log message:

Fix a regression caused by a patch earlier today


---
Diffs of the changes:  (+2 -1)

 PPCISelDAGToDAG.cpp |    3 ++-
 1 files changed, 2 insertions(+), 1 deletion(-)


Index: llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
diff -u llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp:1.133 llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp:1.134
--- llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp:1.133	Wed Nov 30 18:41:50 2005
+++ llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp	Wed Nov 30 21:50:19 2005
@@ -721,7 +721,8 @@
   SDOperand CR7Reg = CurDAG->getRegister(PPC::CR7, MVT::i32);
   
   SDOperand InFlag;  // Null incoming flag value.
-  CCReg = CurDAG->getCopyToReg(CurDAG->getEntryNode(), CR7Reg, CCReg, InFlag);
+  CCReg = CurDAG->getCopyToReg(CurDAG->getEntryNode(), CR7Reg, CCReg, 
+                               InFlag).getValue(1);
   
   if (TLI.getTargetMachine().getSubtarget<PPCSubtarget>().isGigaProcessor())
     IntCR = CurDAG->getTargetNode(PPC::MFOCRF, MVT::i32, CR7Reg, CCReg);





From natebegeman at mac.com  Wed Nov 30 22:48:38 2005
From: natebegeman at mac.com (Nate Begeman)
Date: Wed, 30 Nov 2005 22:48:38 -0600
Subject: [llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCRegisterInfo.td 
Message-ID: <200512010448.WAA13437@zion.cs.uiuc.edu>



Changes in directory llvm/lib/Target/PowerPC:

PPCRegisterInfo.td updated: 1.24 -> 1.25
---
Log message:

Cosmetic change, better reflects actual values


---
Diffs of the changes:  (+5 -6)

 PPCRegisterInfo.td |   11 +++++------
 1 files changed, 5 insertions(+), 6 deletions(-)


Index: llvm/lib/Target/PowerPC/PPCRegisterInfo.td
diff -u llvm/lib/Target/PowerPC/PPCRegisterInfo.td:1.24 llvm/lib/Target/PowerPC/PPCRegisterInfo.td:1.25
--- llvm/lib/Target/PowerPC/PPCRegisterInfo.td:1.24	Mon Nov 28 23:45:29 2005
+++ llvm/lib/Target/PowerPC/PPCRegisterInfo.td	Wed Nov 30 22:48:26 2005
@@ -28,8 +28,8 @@
 }
 
 // SPR - One of the 32-bit special-purpose registers
-class SPR<bits<5> num, string n> : PPCReg<n> {
-  field bits<5> Num = num;
+class SPR<bits<10> num, string n> : PPCReg<n> {
+  field bits<10> Num = num;
 }
 
 // FPR - One of the 32 64-bit floating-point registers
@@ -126,12 +126,11 @@
 def CR6 : CR<6, "cr6">; def CR7 : CR<7, "cr7">;
 
 // Link register
-// FIXME: encode actual spr numbers here
-def LR  : SPR<2,   "lr">;
+def LR  : SPR<8, "lr">;
 // Count register
-def CTR : SPR<3, "ctr">;
+def CTR : SPR<9, "ctr">;
 // VRsave register
-def VRSAVE: SPR<4, "VRsave">;
+def VRSAVE: SPR<256, "VRsave">;
 
 /// Register classes
 // Allocate volatiles first





From natebegeman at mac.com  Wed Nov 30 22:51:22 2005
From: natebegeman at mac.com (Nate Begeman)
Date: Wed, 30 Nov 2005 22:51:22 -0600
Subject: [llvm-commits] CVS: llvm/lib/Target/Target.td 
Message-ID: <200512010451.WAA13515@zion.cs.uiuc.edu>



Changes in directory llvm/lib/Target:

Target.td updated: 1.62 -> 1.63
---
Log message:

Support multiple ValueTypes per RegisterClass, needed for upcoming vector
work.  This change has no effect on generated code.


---
Diffs of the changes:  (+6 -3)

 Target.td |    9 ++++++---
 1 files changed, 6 insertions(+), 3 deletions(-)


Index: llvm/lib/Target/Target.td
diff -u llvm/lib/Target/Target.td:1.62 llvm/lib/Target/Target.td:1.63
--- llvm/lib/Target/Target.td:1.62	Mon Nov 28 23:45:29 2005
+++ llvm/lib/Target/Target.td	Wed Nov 30 22:51:06 2005
@@ -90,19 +90,22 @@
 // register classes.  This also defines the default allocation order of
 // registers by register allocators.
 //
-class RegisterClass<string namespace, ValueType regType, int alignment,
+class RegisterClass<string namespace, list<ValueType> regTypes, int alignment,
                     list<Register> regList> {
   string Namespace = namespace;
 
   // RegType - Specify the ValueType of the registers in this register class.
   // Note that all registers in a register class must have the same ValueType.
   //
-  ValueType RegType = regType;
+  list<ValueType> RegTypes = regTypes;
+
+  // Size - Specify the spill size in bits of the registers.  A default value of
+  // zero lets tablgen pick an appropriate size.
+  int Size = 0;
 
   // Alignment - Specify the alignment required of the registers when they are
   // stored or loaded to memory.
   //
-  int Size = RegType.Size;
   int Alignment = alignment;
 
   // MemberList - Specify which registers are in this class.  If the





From natebegeman at mac.com  Wed Nov 30 22:51:23 2005
From: natebegeman at mac.com (Nate Begeman)
Date: Wed, 30 Nov 2005 22:51:23 -0600
Subject: [llvm-commits] CVS: llvm/lib/Target/SparcV8/SparcV8RegisterInfo.td 
Message-ID: <200512010451.WAA13519@zion.cs.uiuc.edu>



Changes in directory llvm/lib/Target/SparcV8:

SparcV8RegisterInfo.td updated: 1.22 -> 1.23
---
Log message:

Support multiple ValueTypes per RegisterClass, needed for upcoming vector
work.  This change has no effect on generated code.


---
Diffs of the changes:  (+3 -3)

 SparcV8RegisterInfo.td |    6 +++---
 1 files changed, 3 insertions(+), 3 deletions(-)


Index: llvm/lib/Target/SparcV8/SparcV8RegisterInfo.td
diff -u llvm/lib/Target/SparcV8/SparcV8RegisterInfo.td:1.22 llvm/lib/Target/SparcV8/SparcV8RegisterInfo.td:1.23
--- llvm/lib/Target/SparcV8/SparcV8RegisterInfo.td:1.22	Fri Aug 19 14:13:20 2005
+++ llvm/lib/Target/SparcV8/SparcV8RegisterInfo.td	Wed Nov 30 22:51:06 2005
@@ -84,7 +84,7 @@
 // FIXME: the register order should be defined in terms of the preferred
 // allocation order...
 //
-def IntRegs : RegisterClass<"V8", i32, 32, [L0, L1, L2, L3, L4, L5, L6, L7,
+def IntRegs : RegisterClass<"V8", [i32], 32, [L0, L1, L2, L3, L4, L5, L6, L7,
                                      I0, I1, I2, I3, I4, I5,
                                      G1,
                                      O0, O1, O2, O3, O4, O5, O7,
@@ -109,9 +109,9 @@
   }];
 }
 
-def FPRegs : RegisterClass<"V8", f32, 32, [F0, F1, F2, F3, F4, F5, F6, F7, F8,
+def FPRegs : RegisterClass<"V8", [f32], 32, [F0, F1, F2, F3, F4, F5, F6, F7, F8,
   F9, F10, F11, F12, F13, F14, F15, F16, F17, F18, F19, F20, F21, F22,
   F23, F24, F25, F26, F27, F28, F29, F30, F31]>;
 
-def DFPRegs : RegisterClass<"V8", f64, 64, [D0, D1, D2, D3, D4, D5, D6, D7,
+def DFPRegs : RegisterClass<"V8", [f64], 64, [D0, D1, D2, D3, D4, D5, D6, D7,
   D8, D9, D10, D11, D12, D13, D14, D15]>;





From natebegeman at mac.com  Wed Nov 30 22:51:24 2005
From: natebegeman at mac.com (Nate Begeman)
Date: Wed, 30 Nov 2005 22:51:24 -0600
Subject: [llvm-commits] CVS: llvm/lib/Target/IA64/IA64RegisterInfo.td 
Message-ID: <200512010451.WAA13526@zion.cs.uiuc.edu>



Changes in directory llvm/lib/Target/IA64:

IA64RegisterInfo.td updated: 1.10 -> 1.11
---
Log message:

Support multiple ValueTypes per RegisterClass, needed for upcoming vector
work.  This change has no effect on generated code.


---
Diffs of the changes:  (+3 -3)

 IA64RegisterInfo.td |    6 +++---
 1 files changed, 3 insertions(+), 3 deletions(-)


Index: llvm/lib/Target/IA64/IA64RegisterInfo.td
diff -u llvm/lib/Target/IA64/IA64RegisterInfo.td:1.10 llvm/lib/Target/IA64/IA64RegisterInfo.td:1.11
--- llvm/lib/Target/IA64/IA64RegisterInfo.td:1.10	Wed Nov  2 01:30:39 2005
+++ llvm/lib/Target/IA64/IA64RegisterInfo.td	Wed Nov 30 22:51:06 2005
@@ -232,7 +232,7 @@
 // FIXME/XXX  we also reserve r22 for calculating addresses
 // in IA64RegisterInfo.cpp
 
-def GR : RegisterClass<"IA64", i64, 64, 
+def GR : RegisterClass<"IA64", [i64], 64, 
        [
        
 //FIXME!: for readability, we don't want the out registers to be the first
@@ -282,7 +282,7 @@
 
 
 // these are the scratch (+stacked) FP registers
-def FP : RegisterClass<"IA64", f64, 64, 
+def FP : RegisterClass<"IA64", [f64], 64, 
        [F6, F7, 
 	F8, F9, F10, F11, F12, F13, F14, F15, 
 	F32, F33, F34, F35, F36, F37, F38, F39, 
@@ -317,7 +317,7 @@
 }
 
 // these are the predicate registers, p0 (1/TRUE) is not here
-def PR : RegisterClass<"IA64", i1, 64, 
+def PR : RegisterClass<"IA64", [i1], 64, 
 
 // for now, let's be wimps and only have the scratch predicate regs
  [p6, p7, p8, p9, p10, p11, p12, p13, p14, p15]> {





From natebegeman at mac.com  Wed Nov 30 22:51:24 2005
From: natebegeman at mac.com (Nate Begeman)
Date: Wed, 30 Nov 2005 22:51:24 -0600
Subject: [llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp 
Message-ID: <200512010451.WAA13527@zion.cs.uiuc.edu>



Changes in directory llvm/lib/CodeGen/SelectionDAG:

ScheduleDAG.cpp updated: 1.46 -> 1.47
---
Log message:

Support multiple ValueTypes per RegisterClass, needed for upcoming vector
work.  This change has no effect on generated code.


---
Diffs of the changes:  (+1 -1)

 ScheduleDAG.cpp |    2 +-
 1 files changed, 1 insertion(+), 1 deletion(-)


Index: llvm/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp:1.46 llvm/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp:1.47
--- llvm/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp:1.46	Tue Nov 29 20:04:11 2005
+++ llvm/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp	Wed Nov 30 22:51:06 2005
@@ -1208,7 +1208,7 @@
         // Pick the register class of the right type that contains this physreg.
         for (MRegisterInfo::regclass_iterator I = MRI.regclass_begin(),
              E = MRI.regclass_end(); I != E; ++I)
-          if ((*I)->getType() == Node->getValueType(0) &&
+          if ((*I)->hasType(Node->getValueType(0)) &&
               (*I)->contains(SrcReg)) {
             TRC = *I;
             break;





From natebegeman at mac.com  Wed Nov 30 22:51:24 2005
From: natebegeman at mac.com (Nate Begeman)
Date: Wed, 30 Nov 2005 22:51:24 -0600
Subject: [llvm-commits] 
	CVS: llvm/lib/Target/Skeleton/SkeletonRegisterInfo.td
Message-ID: <200512010451.WAA13531@zion.cs.uiuc.edu>



Changes in directory llvm/lib/Target/Skeleton:

SkeletonRegisterInfo.td updated: 1.5 -> 1.6
---
Log message:

Support multiple ValueTypes per RegisterClass, needed for upcoming vector
work.  This change has no effect on generated code.


---
Diffs of the changes:  (+2 -2)

 SkeletonRegisterInfo.td |    4 ++--
 1 files changed, 2 insertions(+), 2 deletions(-)


Index: llvm/lib/Target/Skeleton/SkeletonRegisterInfo.td
diff -u llvm/lib/Target/Skeleton/SkeletonRegisterInfo.td:1.5 llvm/lib/Target/Skeleton/SkeletonRegisterInfo.td:1.6
--- llvm/lib/Target/Skeleton/SkeletonRegisterInfo.td:1.5	Fri Sep 30 01:43:58 2005
+++ llvm/lib/Target/Skeleton/SkeletonRegisterInfo.td	Wed Nov 30 22:51:06 2005
@@ -89,10 +89,10 @@
 
 /// Register classes: one for floats and another for non-floats.
 ///
-def GPRC : RegisterClass<"Skeleton", i32, 32, [R0, R1, R2, R3, R4, R5, R6, R7,
+def GPRC : RegisterClass<"Skeleton", [i32], 32, [R0, R1, R2, R3, R4, R5, R6, R7,
   R8, R9, R10, R11, R12, R13, R14, R15, R16, R17, R18, R19, R20, R21,
   R22, R23, R24, R25, R26, R27, R28, R29, R30, R31]>;
-def FPRC : RegisterClass<"Skeleton", f64, 64, [F0, F1, F2, F3, F4, F5, F6, F7,
+def FPRC : RegisterClass<"Skeleton", [f64], 64, [F0, F1, F2, F3, F4, F5, F6, F7,
   F8, F9, F10, F11, F12, F13, F14, F15, F16, F17, F18, F19, F20, F21,
   F22, F23, F24, F25, F26, F27, F28, F29, F30, F31]>;
 





From natebegeman at mac.com  Wed Nov 30 22:51:24 2005
From: natebegeman at mac.com (Nate Begeman)
Date: Wed, 30 Nov 2005 22:51:24 -0600
Subject: [llvm-commits] CVS: llvm/include/llvm/Target/MRegisterInfo.h 
Message-ID: <200512010451.WAA13523@zion.cs.uiuc.edu>



Changes in directory llvm/include/llvm/Target:

MRegisterInfo.h updated: 1.65 -> 1.66
---
Log message:

Support multiple ValueTypes per RegisterClass, needed for upcoming vector
work.  This change has no effect on generated code.


---
Diffs of the changes:  (+13 -7)

 MRegisterInfo.h |   20 +++++++++++++-------
 1 files changed, 13 insertions(+), 7 deletions(-)


Index: llvm/include/llvm/Target/MRegisterInfo.h
diff -u llvm/include/llvm/Target/MRegisterInfo.h:1.65 llvm/include/llvm/Target/MRegisterInfo.h:1.66
--- llvm/include/llvm/Target/MRegisterInfo.h:1.65	Sun Oct  2 22:32:39 2005
+++ llvm/include/llvm/Target/MRegisterInfo.h	Wed Nov 30 22:51:06 2005
@@ -45,18 +45,15 @@
   typedef const unsigned* const_iterator;
 
 private:
-  const MVT::ValueType VT;
+  const MVT::ValueType* VTs;
   const unsigned RegSize, Alignment;    // Size & Alignment of register in bytes
   const iterator RegsBegin, RegsEnd;
 public:
-  TargetRegisterClass(MVT::ValueType vt, unsigned RS, unsigned Al, iterator RB, iterator RE)
-    : VT(vt), RegSize(RS), Alignment(Al), RegsBegin(RB), RegsEnd(RE) {}
+  TargetRegisterClass(const MVT::ValueType *vts, unsigned RS, unsigned Al,
+                      iterator RB, iterator RE)
+    : VTs(vts), RegSize(RS), Alignment(Al), RegsBegin(RB), RegsEnd(RE) {}
   virtual ~TargetRegisterClass() {}     // Allow subclasses
 
-  /// getType - Return the declared value type for this register class.
-  ///
-  MVT::ValueType getType() const { return VT; }
-  
   // begin/end - Return all of the registers in this class.
   iterator       begin() const { return RegsBegin; }
   iterator         end() const { return RegsEnd; }
@@ -78,6 +75,15 @@
     return false;
   }
 
+  /// hasType - return true if this TargetRegisterClass has the ValueType vt.
+  ///
+  bool hasType(MVT::ValueType vt) const {
+    for(int i = 0; VTs[i] != MVT::Other; ++i)
+      if (VTs[i] == vt)
+        return true;
+    return false;
+  }
+  
   /// allocation_order_begin/end - These methods define a range of registers
   /// which specify the registers in this class that are valid to register
   /// allocate, and the preferred order to allocate them in.  For example,





From natebegeman at mac.com  Wed Nov 30 22:51:24 2005
From: natebegeman at mac.com (Nate Begeman)
Date: Wed, 30 Nov 2005 22:51:24 -0600
Subject: [llvm-commits] CVS: llvm/lib/Target/X86/X86RegisterInfo.td 
Message-ID: <200512010451.WAA13549@zion.cs.uiuc.edu>



Changes in directory llvm/lib/Target/X86:

X86RegisterInfo.td updated: 1.22 -> 1.23
---
Log message:

Support multiple ValueTypes per RegisterClass, needed for upcoming vector
work.  This change has no effect on generated code.


---
Diffs of the changes:  (+8 -7)

 X86RegisterInfo.td |   15 ++++++++-------
 1 files changed, 8 insertions(+), 7 deletions(-)


Index: llvm/lib/Target/X86/X86RegisterInfo.td
diff -u llvm/lib/Target/X86/X86RegisterInfo.td:1.22 llvm/lib/Target/X86/X86RegisterInfo.td:1.23
--- llvm/lib/Target/X86/X86RegisterInfo.td:1.22	Fri Oct 14 17:06:00 2005
+++ llvm/lib/Target/X86/X86RegisterInfo.td	Wed Nov 30 22:51:06 2005
@@ -72,9 +72,9 @@
 // dependences between upper and lower parts of the register.  BL and BH are
 // last because they are call clobbered. Both Athlon and P4 chips suffer this
 // issue.
-def R8  : RegisterClass<"X86", i8,  8, [AL, CL, DL, AH, CH, DH, BL, BH]>;
+def R8  : RegisterClass<"X86", [i8],  8, [AL, CL, DL, AH, CH, DH, BL, BH]>;
 
-def R16 : RegisterClass<"X86", i16, 16, [AX, CX, DX, SI, DI, BX, BP, SP]> {
+def R16 : RegisterClass<"X86", [i16], 16, [AX, CX, DX, SI, DI, BX, BP, SP]> {
   let MethodProtos = [{
     iterator allocation_order_end(MachineFunction &MF) const;
   }];
@@ -89,7 +89,8 @@
   }];
 }
 
-def R32 : RegisterClass<"X86", i32, 32, [EAX, ECX, EDX, ESI, EDI, EBX, EBP, ESP]> {
+def R32 : RegisterClass<"X86", [i32], 32, 
+                        [EAX, ECX, EDX, ESI, EDI, EBX, EBP, ESP]> {
   let MethodProtos = [{
     iterator allocation_order_end(MachineFunction &MF) const;
   }];
@@ -106,9 +107,9 @@
 
 // V4F4, the 4 x f32 class, and V2F8, the 2 x f64 class, which we will use for
 // Scalar SSE2 floating point support.
-def V4F4 : RegisterClass<"X86", f32, 32,
+def V4F4 : RegisterClass<"X86", [f32], 32,
                          [XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7]>;
-def V2F8 : RegisterClass<"X86", f64, 64,
+def V2F8 : RegisterClass<"X86", [f64], 64,
                          [XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7]>;
 
 // FIXME: This sets up the floating point register files as though they are f64
@@ -117,12 +118,12 @@
 // faster on common hardware.  In reality, this should be controlled by a
 // command line option or something.
 
-def RFP : RegisterClass<"X86", f64, 32, [FP0, FP1, FP2, FP3, FP4, FP5, FP6]>;
+def RFP : RegisterClass<"X86", [f64], 32, [FP0, FP1, FP2, FP3, FP4, FP5, FP6]>;
 
 // Floating point stack registers (these are not allocatable by the
 // register allocator - the floating point stackifier is responsible
 // for transforming FPn allocations to STn registers)
-def RST : RegisterClass<"X86", f64, 32,
+def RST : RegisterClass<"X86", [f64], 32,
                         [ST0, ST1, ST2, ST3, ST4, ST5, ST6, ST7]> {
     let MethodProtos = [{
     iterator allocation_order_end(MachineFunction &MF) const;





From natebegeman at mac.com  Wed Nov 30 22:51:24 2005
From: natebegeman at mac.com (Nate Begeman)
Date: Wed, 30 Nov 2005 22:51:24 -0600
Subject: [llvm-commits] CVS: llvm/utils/TableGen/CodeGenRegisters.h
	CodeGenTarget.cpp DAGISelEmitter.cpp RegisterInfoEmitter.cpp 
Message-ID: <200512010451.WAA13563@zion.cs.uiuc.edu>



Changes in directory llvm/utils/TableGen:

CodeGenRegisters.h updated: 1.8 -> 1.9
CodeGenTarget.cpp updated: 1.45 -> 1.46
DAGISelEmitter.cpp updated: 1.80 -> 1.81
RegisterInfoEmitter.cpp updated: 1.37 -> 1.38
---
Log message:

Support multiple ValueTypes per RegisterClass, needed for upcoming vector
work.  This change has no effect on generated code.


---
Diffs of the changes:  (+57 -17)

 CodeGenRegisters.h      |    9 ++++++++-
 CodeGenTarget.cpp       |   28 ++++++++++++++++++++--------
 DAGISelEmitter.cpp      |   16 ++++++++++------
 RegisterInfoEmitter.cpp |   21 +++++++++++++++++++--
 4 files changed, 57 insertions(+), 17 deletions(-)


Index: llvm/utils/TableGen/CodeGenRegisters.h
diff -u llvm/utils/TableGen/CodeGenRegisters.h:1.8 llvm/utils/TableGen/CodeGenRegisters.h:1.9
--- llvm/utils/TableGen/CodeGenRegisters.h:1.8	Thu Sep  8 16:43:21 2005
+++ llvm/utils/TableGen/CodeGenRegisters.h	Wed Nov 30 22:51:06 2005
@@ -35,13 +35,20 @@
     Record *TheDef;
     std::string Namespace;
     std::vector<Record*> Elements;
+    std::vector<MVT::ValueType> VTs;
     unsigned SpillSize;
     unsigned SpillAlignment;
-    MVT::ValueType VT;
     std::string MethodProtos, MethodBodies;
 
     const std::string &getName() const;
 
+    const MVT::ValueType getValueTypeNum(unsigned VTNum) const {
+      if (VTNum < VTs.size())
+        return VTs[VTNum];
+      assert(0 && "VTNum greater than number of ValueTypes in RegClass!");
+      abort();
+    }
+
     CodeGenRegisterClass(Record *R);
   };
 }


Index: llvm/utils/TableGen/CodeGenTarget.cpp
diff -u llvm/utils/TableGen/CodeGenTarget.cpp:1.45 llvm/utils/TableGen/CodeGenTarget.cpp:1.46
--- llvm/utils/TableGen/CodeGenTarget.cpp:1.45	Wed Nov 30 18:12:04 2005
+++ llvm/utils/TableGen/CodeGenTarget.cpp	Wed Nov 30 22:51:06 2005
@@ -154,13 +154,15 @@
     R->setName("AnonRegClass_"+utostr(AnonCounter++));
   } 
   
-  Namespace = R->getValueAsString("Namespace");
-  SpillSize = R->getValueAsInt("Size");
-  SpillAlignment = R->getValueAsInt("Alignment");
-  VT = getValueType(R->getValueAsDef("RegType"));
-
-  MethodBodies = R->getValueAsCode("MethodBodies");
-  MethodProtos = R->getValueAsCode("MethodProtos");
+  std::vector<Record*> TypeList = R->getValueAsListOfDefs("RegTypes");
+  for (unsigned i = 0, e = TypeList.size(); i != e; ++i) {
+    Record *Type = TypeList[i];
+    if (!Type->isSubClassOf("ValueType"))
+      throw "RegTypes list member '" + Type->getName() +
+        "' does not derive from the ValueType class!";
+    VTs.push_back(getValueType(Type));
+  }
+  assert(!VTs.empty() && "RegisterClass must contain at least one ValueType!");
   
   std::vector<Record*> RegList = R->getValueAsListOfDefs("MemberList");
   for (unsigned i = 0, e = RegList.size(); i != e; ++i) {
@@ -170,6 +172,15 @@
             "' does not derive from the Register class!";
     Elements.push_back(Reg);
   }
+  
+  // Allow targets to override the size in bits of the RegisterClass.
+  unsigned Size = R->getValueAsInt("Size");
+
+  Namespace = R->getValueAsString("Namespace");
+  SpillSize = Size ? Size : MVT::getSizeInBits(VTs[0]);
+  SpillAlignment = R->getValueAsInt("Alignment");
+  MethodBodies = R->getValueAsCode("MethodBodies");
+  MethodProtos = R->getValueAsCode("MethodProtos");
 }
 
 const std::string &CodeGenRegisterClass::getName() const {
@@ -179,7 +190,8 @@
 void CodeGenTarget::ReadLegalValueTypes() const {
   const std::vector<CodeGenRegisterClass> &RCs = getRegisterClasses();
   for (unsigned i = 0, e = RCs.size(); i != e; ++i)
-    LegalValueTypes.push_back(RCs[i].VT);
+    for (unsigned ri = 0, re = RCs[i].VTs.size(); ri != re; ++ri)
+      LegalValueTypes.push_back(RCs[i].VTs[ri]);
   
   // Remove duplicates.
   std::sort(LegalValueTypes.begin(), LegalValueTypes.end());


Index: llvm/utils/TableGen/DAGISelEmitter.cpp
diff -u llvm/utils/TableGen/DAGISelEmitter.cpp:1.80 llvm/utils/TableGen/DAGISelEmitter.cpp:1.81
--- llvm/utils/TableGen/DAGISelEmitter.cpp:1.80	Wed Nov 30 18:18:45 2005
+++ llvm/utils/TableGen/DAGISelEmitter.cpp	Wed Nov 30 22:51:06 2005
@@ -455,7 +455,9 @@
   // Check to see if this is a register or a register class...
   if (R->isSubClassOf("RegisterClass")) {
     if (NotRegisters) return MVT::isUnknown;
-    return getValueType(R->getValueAsDef("RegType"));
+    const CodeGenRegisterClass &RC = 
+      TP.getDAGISelEmitter().getTargetInfo().getRegisterClass(R);
+    return RC.getValueTypeNum(0);
   } else if (R->isSubClassOf("PatFrag")) {
     // Pattern fragment types will be resolved when they are inlined.
     return MVT::isUnknown;
@@ -537,8 +539,9 @@
 
     const CodeGenRegisterClass &RC = 
       TP.getDAGISelEmitter().getTargetInfo().getRegisterClass(ResultNode);
-    
-    bool MadeChange = UpdateNodeType(RC.VT, TP);
+
+    // Get the first ValueType in the RegClass, it's as good as any.
+    bool MadeChange = UpdateNodeType(RC.getValueTypeNum(0), TP);
 
     if (getNumChildren() != Inst.getNumOperands())
       TP.error("Instruction '" + getOperator()->getName() + " expects " +
@@ -550,7 +553,7 @@
       if (OperandNode->isSubClassOf("RegisterClass")) {
         const CodeGenRegisterClass &RC = 
           TP.getDAGISelEmitter().getTargetInfo().getRegisterClass(OperandNode);
-        VT = RC.VT;
+        VT = RC.getValueTypeNum(0);
       } else if (OperandNode->isSubClassOf("Operand")) {
         VT = getValueType(OperandNode->getValueAsDef("Type"));
       } else {
@@ -1672,7 +1675,8 @@
        << ".Val)) goto P" << PatternNo << "Fail;\n";
 }
 
-/// getRegisterValueType - Look up and return ValueType of specified record
+/// getRegisterValueType - Look up and return the first ValueType of specified 
+/// RegisterClass record
 static MVT::ValueType getRegisterValueType(Record *R, const CodeGenTarget &T) {
   const std::vector<CodeGenRegisterClass> &RegisterClasses =
     T.getRegisterClasses();
@@ -1681,7 +1685,7 @@
     const CodeGenRegisterClass &RC = RegisterClasses[i];
     for (unsigned ei = 0, ee = RC.Elements.size(); ei != ee; ++ei) {
       if (R == RC.Elements[ei]) {
-        return RC.VT;
+        return RC.getValueTypeNum(0);
       }
     }
   }


Index: llvm/utils/TableGen/RegisterInfoEmitter.cpp
diff -u llvm/utils/TableGen/RegisterInfoEmitter.cpp:1.37 llvm/utils/TableGen/RegisterInfoEmitter.cpp:1.38
--- llvm/utils/TableGen/RegisterInfoEmitter.cpp:1.37	Fri Oct 28 17:59:53 2005
+++ llvm/utils/TableGen/RegisterInfoEmitter.cpp	Wed Nov 30 22:51:06 2005
@@ -109,6 +109,7 @@
   // belongs to.
   std::multimap<Record*, const CodeGenRegisterClass*> RegClassesBelongedTo;
 
+  // Emit the register enum value arrays for each RegisterClass
   for (unsigned rc = 0, e = RegisterClasses.size(); rc != e; ++rc) {
     const CodeGenRegisterClass &RC = RegisterClasses[rc];
 
@@ -127,6 +128,22 @@
     }
     OS << "\n  };\n\n";
   }
+  
+  // Emit the ValueType arrays for each RegisterClass
+  for (unsigned rc = 0, e = RegisterClasses.size(); rc != e; ++rc) {
+    const CodeGenRegisterClass &RC = RegisterClasses[rc];
+    
+    // Give the register class a legal C name if it's anonymous.
+    std::string Name = RC.TheDef->getName() + "VTs";
+    
+    // Emit the register list now.
+    OS << "  // " << Name 
+      << " Register Class Value Types...\n  const MVT::ValueType " << Name
+      << "[] = {\n    ";
+    for (unsigned i = 0, e = RC.VTs.size(); i != e; ++i)
+      OS << "MVT::" << RC.VTs[i] << ", ";
+    OS << "MVT::Other\n  };\n\n";
+  }
   OS << "}  // end anonymous namespace\n\n";
   
   // Now that all of the structs have been emitted, emit the instances.
@@ -140,8 +157,8 @@
     for (unsigned i = 0, e = RegisterClasses.size(); i != e; ++i) {
       const CodeGenRegisterClass &RC = RegisterClasses[i];
       OS << RC.MethodBodies << "\n";
-      OS << RC.getName() << "Class::" << RC.getName()
-         << "Class()  : TargetRegisterClass(MVT::" << getEnumName(RC.VT) << ","
+      OS << RC.getName() << "Class::" << RC.getName() 
+         << "Class()  : TargetRegisterClass(" << RC.getName() + "VTs" << ", "
          << RC.SpillSize/8 << ", "
          << RC.SpillAlignment/8 << ", " << RC.getName() << ", "
          << RC.getName() << " + " << RC.Elements.size() << ") {}\n";





From natebegeman at mac.com  Wed Nov 30 22:51:24 2005
From: natebegeman at mac.com (Nate Begeman)
Date: Wed, 30 Nov 2005 22:51:24 -0600
Subject: [llvm-commits] CVS: llvm/lib/Target/SparcV9/SparcV9RegisterInfo.cpp
	SparcV9RegisterInfo.td 
Message-ID: <200512010451.WAA13541@zion.cs.uiuc.edu>



Changes in directory llvm/lib/Target/SparcV9:

SparcV9RegisterInfo.cpp updated: 1.9 -> 1.10
SparcV9RegisterInfo.td updated: 1.5 -> 1.6
---
Log message:

Support multiple ValueTypes per RegisterClass, needed for upcoming vector
work.  This change has no effect on generated code.


---
Diffs of the changes:  (+12 -6)

 SparcV9RegisterInfo.cpp |   16 +++++++++++-----
 SparcV9RegisterInfo.td  |    2 +-
 2 files changed, 12 insertions(+), 6 deletions(-)


Index: llvm/lib/Target/SparcV9/SparcV9RegisterInfo.cpp
diff -u llvm/lib/Target/SparcV9/SparcV9RegisterInfo.cpp:1.9 llvm/lib/Target/SparcV9/SparcV9RegisterInfo.cpp:1.10
--- llvm/lib/Target/SparcV9/SparcV9RegisterInfo.cpp:1.9	Sun Oct  2 01:23:51 2005
+++ llvm/lib/Target/SparcV9/SparcV9RegisterInfo.cpp	Wed Nov 30 22:51:06 2005
@@ -27,6 +27,7 @@
 
 #include "SparcV9RegisterInfo.h"
 #include "llvm/CodeGen/MachineFunction.h"
+#include "llvm/CodeGen/ValueTypes.h"
 using namespace llvm;
 
 namespace llvm {
@@ -42,8 +43,9 @@
     SparcV9::g2, SparcV9::g3, SparcV9::g4, SparcV9::g5, SparcV9::g6,
     SparcV9::g7, SparcV9::o6
   };
+  const MVT::ValueType IRVTs[] = { MVT::i64, MVT::Other };
   struct IRClass : public TargetRegisterClass {
-    IRClass() : TargetRegisterClass(MVT::i64, 8, 8, IR, IR + 32) {}
+    IRClass() : TargetRegisterClass(IRVTs, 8, 8, IR, IR + 32) {}
   } IRInstance;
 
 
@@ -66,12 +68,13 @@
     SparcV9::f58, SparcV9::f59, SparcV9::f60, SparcV9::f61,
     SparcV9::f62, SparcV9::f63
   };
+  const MVT::ValueType FRVTs[] = { MVT::f32, MVT::Other };
   // FIXME: The size is correct for the first 32 registers. The
   // latter 32 do not all really exist; you can only access every other
   // one (32, 34, ...), and they must contain double-fp or quad-fp
   // values... see below about the aliasing problems.
   struct FRClass : public TargetRegisterClass {
-    FRClass() : TargetRegisterClass(MVT::f32, 4, 8, FR, FR + 64) {}
+    FRClass() : TargetRegisterClass(FRVTs, 4, 8, FR, FR + 64) {}
   } FRInstance;
 
 
@@ -79,8 +82,9 @@
   const unsigned ICCR[] = {
     SparcV9::xcc, SparcV9::icc, SparcV9::ccr
   };
+  const MVT::ValueType ICCRVTs[] = { MVT::i1, MVT::Other };
   struct ICCRClass : public TargetRegisterClass {
-    ICCRClass() : TargetRegisterClass(MVT::i1, 1, 8, ICCR, ICCR + 3) {}
+    ICCRClass() : TargetRegisterClass(ICCRVTs, 1, 8, ICCR, ICCR + 3) {}
   } ICCRInstance;
 
 
@@ -88,8 +92,9 @@
   const unsigned FCCR[] = {
     SparcV9::fcc0, SparcV9::fcc1, SparcV9::fcc2, SparcV9::fcc3
   };
+  const MVT::ValueType FCCRVTs[] = { MVT::i1, MVT::Other };
   struct FCCRClass : public TargetRegisterClass {
-    FCCRClass() : TargetRegisterClass(MVT::i1, 1, 8, FCCR, FCCR + 4) {}
+    FCCRClass() : TargetRegisterClass(FCCRVTs, 1, 8, FCCR, FCCR + 4) {}
   } FCCRInstance;
 
 
@@ -97,8 +102,9 @@
   const unsigned SR[] = {
     SparcV9::fsr
   };
+  const MVT::ValueType SRVTs[] = { MVT::i64, MVT::Other };
   struct SRClass : public TargetRegisterClass {
-    SRClass() : TargetRegisterClass(MVT::i64, 8, 8, SR, SR + 1) {}
+    SRClass() : TargetRegisterClass(SRVTs, 8, 8, SR, SR + 1) {}
   } SRInstance;
 
 


Index: llvm/lib/Target/SparcV9/SparcV9RegisterInfo.td
diff -u llvm/lib/Target/SparcV9/SparcV9RegisterInfo.td:1.5 llvm/lib/Target/SparcV9/SparcV9RegisterInfo.td:1.6
--- llvm/lib/Target/SparcV9/SparcV9RegisterInfo.td:1.5	Fri Aug 19 13:51:57 2005
+++ llvm/lib/Target/SparcV9/SparcV9RegisterInfo.td	Wed Nov 30 22:51:06 2005
@@ -43,7 +43,7 @@
 // FIXME: the register order should be defined in terms of the preferred
 // allocation order...
 //
-def IntRegs : RegisterClass<"V9", i64, 64, [G0, G1, G2, G3, G4, G5, G6, G7,
+def IntRegs : RegisterClass<"V9", [i64], 64, [G0, G1, G2, G3, G4, G5, G6, G7,
                                      O0, O1, O2, O3, O4, O5, O6, O7,
                                      L0, L1, L2, L3, L4, L5, L6, L7,
                                      I0, I1, I2, I3, I4, I5, I6, I7]>;





From natebegeman at mac.com  Wed Nov 30 22:51:24 2005
From: natebegeman at mac.com (Nate Begeman)
Date: Wed, 30 Nov 2005 22:51:24 -0600
Subject: [llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCRegisterInfo.td 
Message-ID: <200512010451.WAA13547@zion.cs.uiuc.edu>



Changes in directory llvm/lib/Target/PowerPC:

PPCRegisterInfo.td updated: 1.25 -> 1.26
---
Log message:

Support multiple ValueTypes per RegisterClass, needed for upcoming vector
work.  This change has no effect on generated code.


---
Diffs of the changes:  (+8 -7)

 PPCRegisterInfo.td |   15 ++++++++-------
 1 files changed, 8 insertions(+), 7 deletions(-)


Index: llvm/lib/Target/PowerPC/PPCRegisterInfo.td
diff -u llvm/lib/Target/PowerPC/PPCRegisterInfo.td:1.25 llvm/lib/Target/PowerPC/PPCRegisterInfo.td:1.26
--- llvm/lib/Target/PowerPC/PPCRegisterInfo.td:1.25	Wed Nov 30 22:48:26 2005
+++ llvm/lib/Target/PowerPC/PPCRegisterInfo.td	Wed Nov 30 22:51:06 2005
@@ -135,7 +135,7 @@
 /// Register classes
 // Allocate volatiles first
 // then nonvolatiles in reverse order since stmw/lmw save from rN to r31
-def GPRC : RegisterClass<"PPC", i32, 32,
+def GPRC : RegisterClass<"PPC", [i32], 32,
      [R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12,
       R30, R29, R28, R27, R26, R25, R24, R23, R22, R21, R20, R19, R18, R17,
       R16, R15, R14, R13, R31, R0, R1, LR]>
@@ -158,7 +158,7 @@
     }
   }];
 }
-def G8RC : RegisterClass<"PPC", i64, 64,
+def G8RC : RegisterClass<"PPC", [i64], 64,
      [X2, X3, X4, X5, X6, X7, X8, X9, X10, X11, X12,
       X30, X29, X28, X27, X26, X25, X24, X23, X22, X21, X20, X19, X18, X17,
       X16, X15, X14, X13, X31, X0, X1]>
@@ -184,15 +184,16 @@
 
 
 
-def F8RC : RegisterClass<"PPC", f64, 64, [F0, F1, F2, F3, F4, F5, F6, F7,
+def F8RC : RegisterClass<"PPC", [f64], 64, [F0, F1, F2, F3, F4, F5, F6, F7,
   F8, F9, F10, F11, F12, F13, F14, F15, F16, F17, F18, F19, F20, F21,
   F22, F23, F24, F25, F26, F27, F28, F29, F30, F31]>;
-def F4RC : RegisterClass<"PPC", f32, 32, [F0, F1, F2, F3, F4, F5, F6, F7,
+def F4RC : RegisterClass<"PPC", [f32], 32, [F0, F1, F2, F3, F4, F5, F6, F7,
   F8, F9, F10, F11, F12, F13, F14, F15, F16, F17, F18, F19, F20, F21,
   F22, F23, F24, F25, F26, F27, F28, F29, F30, F31]>;
 
-def VRRC : RegisterClass<"PPC", v4f32, 128, [V0, V1, V2, V3, V4, V5, V6, V7, V8,
-  V9, V10, V11, V12, V13, V14, V15, V16, V17, V18, V19, V20, V21, V22, V23,
+def VRRC : RegisterClass<"PPC", [v4f32], 128, [V0, V1, V2, V3, V4, V5, V6, V7, 
+  V8, V9, V10, V11, V12, V13, V14, V15, V16, V17, V18, V19, V20, V21, V22, V23,
   V24, V25, V26, V27, V28, V29, V30, V31]>;
 
-def CRRC : RegisterClass<"PPC", i32, 32, [CR0, CR1, CR5, CR6, CR7, CR2, CR3, CR4]>;
+def CRRC : RegisterClass<"PPC", [i32], 32, [CR0, CR1, CR5, CR6, CR7, CR2, 
+  CR3, CR4]>;





From natebegeman at mac.com  Wed Nov 30 22:51:24 2005
From: natebegeman at mac.com (Nate Begeman)
Date: Wed, 30 Nov 2005 22:51:24 -0600
Subject: [llvm-commits] CVS: llvm/lib/Target/Alpha/AlphaRegisterInfo.td 
Message-ID: <200512010451.WAA13534@zion.cs.uiuc.edu>



Changes in directory llvm/lib/Target/Alpha:

AlphaRegisterInfo.td updated: 1.14 -> 1.15
---
Log message:

Support multiple ValueTypes per RegisterClass, needed for upcoming vector
work.  This change has no effect on generated code.


---
Diffs of the changes:  (+3 -3)

 AlphaRegisterInfo.td |    6 +++---
 1 files changed, 3 insertions(+), 3 deletions(-)


Index: llvm/lib/Target/Alpha/AlphaRegisterInfo.td
diff -u llvm/lib/Target/Alpha/AlphaRegisterInfo.td:1.14 llvm/lib/Target/Alpha/AlphaRegisterInfo.td:1.15
--- llvm/lib/Target/Alpha/AlphaRegisterInfo.td:1.14	Wed Nov 30 01:19:56 2005
+++ llvm/lib/Target/Alpha/AlphaRegisterInfo.td	Wed Nov 30 22:51:06 2005
@@ -78,7 +78,7 @@
   // $28 is undefined after any and all calls
 
 /// Register classes
-def GPRC : RegisterClass<"Alpha", i64, 64,
+def GPRC : RegisterClass<"Alpha", [i64], 64,
      // Volatile
      [R0, R1, R2, R3, R4, R5, R6, R7, R8, R16, R17, R18, R19, R20, R21, R22,
       R23, R24, R25, R28, 
@@ -102,7 +102,7 @@
   }];
 }
 
-def F4RC : RegisterClass<"Alpha", f32, 64, [F0, F1, 
+def F4RC : RegisterClass<"Alpha", [f32], 64, [F0, F1, 
         F10, F11, F12, F13, F14, F15, F16, F17, F18, F19,
         F20, F21, F22, F23, F24, F25, F26, F27, F28, F29, F30,
         // Saved:
@@ -120,7 +120,7 @@
   }];
 }
 
-def F8RC : RegisterClass<"Alpha", f64, 64, [F0, F1, 
+def F8RC : RegisterClass<"Alpha", [f64], 64, [F0, F1, 
         F10, F11, F12, F13, F14, F15, F16, F17, F18, F19,
         F20, F21, F22, F23, F24, F25, F26, F27, F28, F29, F30,
         // Saved:





From alenhar2 at cs.uiuc.edu  Thu Dec  1 11:49:15 2005
From: alenhar2 at cs.uiuc.edu (Andrew Lenharth)
Date: Thu, 1 Dec 2005 11:49:15 -0600
Subject: [llvm-commits] CVS: llvm/lib/Target/Alpha/AlphaISelPattern.cpp 
Message-ID: <200512011749.LAA12884@apoc.cs.uiuc.edu>



Changes in directory llvm/lib/Target/Alpha:

AlphaISelPattern.cpp updated: 1.192 -> 1.193
---
Log message:

major think-o

---
Diffs of the changes:  (+10 -5)

 AlphaISelPattern.cpp |   15 ++++++++++-----
 1 files changed, 10 insertions(+), 5 deletions(-)


Index: llvm/lib/Target/Alpha/AlphaISelPattern.cpp
diff -u llvm/lib/Target/Alpha/AlphaISelPattern.cpp:1.192 llvm/lib/Target/Alpha/AlphaISelPattern.cpp:1.193
--- llvm/lib/Target/Alpha/AlphaISelPattern.cpp:1.192	Wed Nov 30 11:14:11 2005
+++ llvm/lib/Target/Alpha/AlphaISelPattern.cpp	Thu Dec  1 11:48:51 2005
@@ -1538,23 +1538,28 @@
     return Result;
 
   case AlphaISD::CVTQT_:
-    BuildMI(BB, Alpha::CVTQT, 1, Result).addReg(SelectExpr(N.getOperand(0)));
+    Tmp1 = SelectExpr(N.getOperand(0));
+    BuildMI(BB, Alpha::CVTQT, 1, Result).addReg(Tmp1);
     return Result;
 
   case AlphaISD::CVTQS_:
-    BuildMI(BB, Alpha::CVTQS, 1, Result).addReg(SelectExpr(N.getOperand(0)));
+    Tmp1 = SelectExpr(N.getOperand(0));
+    BuildMI(BB, Alpha::CVTQS, 1, Result).addReg(Tmp1);
     return Result;
 
   case AlphaISD::CVTTQ_:
-    BuildMI(BB, Alpha::CVTTQ, 1, Result).addReg(SelectExpr(N.getOperand(0)));
+    Tmp1 = SelectExpr(N.getOperand(0));
+    BuildMI(BB, Alpha::CVTTQ, 1, Result).addReg(Tmp1);
     return Result;
 
   case AlphaISD::ITOFT_:
-    BuildMI(BB, Alpha::ITOFT, 1, Result).addReg(SelectExpr(N.getOperand(0)));
+    Tmp1 = SelectExpr(N.getOperand(0));
+    BuildMI(BB, Alpha::ITOFT, 1, Result).addReg(Tmp1);
     return Result;
 
   case AlphaISD::FTOIT_:
-    BuildMI(BB, Alpha::FTOIT, 1, Result).addReg(SelectExpr(N.getOperand(0)));
+    Tmp1 = SelectExpr(N.getOperand(0));
+    BuildMI(BB, Alpha::FTOIT, 1, Result).addReg(Tmp1);
     return Result;
 
   case ISD::AssertSext:





From lattner at cs.uiuc.edu  Thu Dec  1 12:01:09 2005
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Thu, 1 Dec 2005 12:01:09 -0600
Subject: [llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp 
Message-ID: <200512011801.MAA18558@zion.cs.uiuc.edu>



Changes in directory llvm/lib/CodeGen/SelectionDAG:

SelectionDAG.cpp updated: 1.220 -> 1.221
---
Log message:

This is a bugfix for SelectNodeTo.  In certain situations, we could be
selecting a node and use a mix of getTargetNode() and SelectNodeTo.  Because
SelectNodeTo didn't check the CSE maps for a preexisting node and didn't insert
its result into the CSE maps, we would sometimes miss a CSE opportunity.

This is extremely rare, but worth fixing for completeness.



---
Diffs of the changes:  (+110 -0)

 SelectionDAG.cpp |  110 +++++++++++++++++++++++++++++++++++++++++++++++++++++++
 1 files changed, 110 insertions(+)


Index: llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp:1.220 llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp:1.221
--- llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp:1.220	Wed Nov 30 16:45:14 2005
+++ llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp	Thu Dec  1 12:00:57 2005
@@ -1415,40 +1415,74 @@
 /// specified node to have the specified return type, Target opcode, and
 /// operands.  Note that target opcodes are stored as
 /// ISD::BUILTIN_OP_END+TargetOpcode in the node opcode field.
+///
+/// Note that SelectNodeTo returns the resultant node.  If there is already a
+/// node of the specified opcode and operands, it returns that node instead of
+/// the current one.
 SDOperand SelectionDAG::SelectNodeTo(SDNode *N, unsigned TargetOpc,
                                      MVT::ValueType VT) {
+  // If an identical node already exists, use it.
+  SDNode *&ON = NullaryOps[std::make_pair(ISD::BUILTIN_OP_END+TargetOpc, VT)];
+  if (ON) return SDOperand(ON, 0);
+  
   RemoveNodeFromCSEMaps(N);
+  
   N->MorphNodeTo(ISD::BUILTIN_OP_END+TargetOpc);
   N->setValueTypes(VT);
+
+  ON = N;   // Memoize the new node.
   return SDOperand(N, 0);
 }
 
 SDOperand SelectionDAG::SelectNodeTo(SDNode *N, unsigned TargetOpc,
                                      MVT::ValueType VT, SDOperand Op1) {
+  // If an identical node already exists, use it.
+  SDNode *&ON = UnaryOps[std::make_pair(ISD::BUILTIN_OP_END+TargetOpc,
+                                        std::make_pair(Op1, VT))];
+  if (ON) return SDOperand(ON, 0);
+  
   RemoveNodeFromCSEMaps(N);
   N->MorphNodeTo(ISD::BUILTIN_OP_END+TargetOpc);
   N->setValueTypes(VT);
   N->setOperands(Op1);
+  
+  ON = N;   // Memoize the new node.
   return SDOperand(N, 0);
 }
 
 SDOperand SelectionDAG::SelectNodeTo(SDNode *N, unsigned TargetOpc,
                                      MVT::ValueType VT, SDOperand Op1,
                                      SDOperand Op2) {
+  // If an identical node already exists, use it.
+  SDNode *&ON = BinaryOps[std::make_pair(ISD::BUILTIN_OP_END+TargetOpc,
+                                         std::make_pair(Op1, Op2))];
+  if (ON) return SDOperand(ON, 0);
+  
   RemoveNodeFromCSEMaps(N);
   N->MorphNodeTo(ISD::BUILTIN_OP_END+TargetOpc);
   N->setValueTypes(VT);
   N->setOperands(Op1, Op2);
+  
+  ON = N;   // Memoize the new node.
   return SDOperand(N, 0);
 }
 
 SDOperand SelectionDAG::SelectNodeTo(SDNode *N, unsigned TargetOpc,
                                      MVT::ValueType VT, SDOperand Op1,
                                      SDOperand Op2, SDOperand Op3) {
+  // If an identical node already exists, use it.
+  std::vector<SDOperand> OpList;
+  OpList.push_back(Op1); OpList.push_back(Op2); OpList.push_back(Op3);
+  SDNode *&ON = OneResultNodes[std::make_pair(ISD::BUILTIN_OP_END+TargetOpc,
+                                              std::make_pair(VT, OpList))];
+  if (ON) return SDOperand(ON, 0);
+  
   RemoveNodeFromCSEMaps(N);
   N->MorphNodeTo(ISD::BUILTIN_OP_END+TargetOpc);
   N->setValueTypes(VT);
   N->setOperands(Op1, Op2, Op3);
+
+  ON = N;   // Memoize the new node.
   return SDOperand(N, 0);
 }
 
@@ -1456,10 +1490,20 @@
                                      MVT::ValueType VT, SDOperand Op1,
                                      SDOperand Op2, SDOperand Op3,
                                      SDOperand Op4) {
+  // If an identical node already exists, use it.
+  std::vector<SDOperand> OpList;
+  OpList.push_back(Op1); OpList.push_back(Op2); OpList.push_back(Op3);
+  OpList.push_back(Op4);
+  SDNode *&ON = OneResultNodes[std::make_pair(ISD::BUILTIN_OP_END+TargetOpc,
+                                              std::make_pair(VT, OpList))];
+  if (ON) return SDOperand(ON, 0);
+  
   RemoveNodeFromCSEMaps(N);
   N->MorphNodeTo(ISD::BUILTIN_OP_END+TargetOpc);
   N->setValueTypes(VT);
   N->setOperands(Op1, Op2, Op3, Op4);
+
+  ON = N;   // Memoize the new node.
   return SDOperand(N, 0);
 }
 
@@ -1467,10 +1511,20 @@
                                      MVT::ValueType VT, SDOperand Op1,
                                      SDOperand Op2, SDOperand Op3,SDOperand Op4,
                                      SDOperand Op5) {
+  // If an identical node already exists, use it.
+  std::vector<SDOperand> OpList;
+  OpList.push_back(Op1); OpList.push_back(Op2); OpList.push_back(Op3);
+  OpList.push_back(Op4); OpList.push_back(Op5);
+  SDNode *&ON = OneResultNodes[std::make_pair(ISD::BUILTIN_OP_END+TargetOpc,
+                                              std::make_pair(VT, OpList))];
+  if (ON) return SDOperand(ON, 0);
+  
   RemoveNodeFromCSEMaps(N);
   N->MorphNodeTo(ISD::BUILTIN_OP_END+TargetOpc);
   N->setValueTypes(VT);
   N->setOperands(Op1, Op2, Op3, Op4, Op5);
+  
+  ON = N;   // Memoize the new node.
   return SDOperand(N, 0);
 }
 
@@ -1478,20 +1532,41 @@
                                      MVT::ValueType VT, SDOperand Op1,
                                      SDOperand Op2, SDOperand Op3,SDOperand Op4,
                                      SDOperand Op5, SDOperand Op6) {
+  // If an identical node already exists, use it.
+  std::vector<SDOperand> OpList;
+  OpList.push_back(Op1); OpList.push_back(Op2); OpList.push_back(Op3);
+  OpList.push_back(Op4); OpList.push_back(Op5); OpList.push_back(Op6);
+  SDNode *&ON = OneResultNodes[std::make_pair(ISD::BUILTIN_OP_END+TargetOpc,
+                                              std::make_pair(VT, OpList))];
+  if (ON) return SDOperand(ON, 0);
+
   RemoveNodeFromCSEMaps(N);
   N->MorphNodeTo(ISD::BUILTIN_OP_END+TargetOpc);
   N->setValueTypes(VT);
   N->setOperands(Op1, Op2, Op3, Op4, Op5, Op6);
+  
+  ON = N;   // Memoize the new node.
   return SDOperand(N, 0);
 }
 
 SDOperand SelectionDAG::SelectNodeTo(SDNode *N, unsigned TargetOpc, 
                                      MVT::ValueType VT1, MVT::ValueType VT2,
                                      SDOperand Op1, SDOperand Op2) {
+  // If an identical node already exists, use it.
+  std::vector<SDOperand> OpList;
+  OpList.push_back(Op1); OpList.push_back(Op2); 
+  std::vector<MVT::ValueType> VTList;
+  VTList.push_back(VT1); VTList.push_back(VT2);
+  SDNode *&ON = ArbitraryNodes[std::make_pair(ISD::BUILTIN_OP_END+TargetOpc,
+                                              std::make_pair(VTList, OpList))];
+  if (ON) return SDOperand(ON, 0);
+
   RemoveNodeFromCSEMaps(N);
   N->MorphNodeTo(ISD::BUILTIN_OP_END+TargetOpc);
   setNodeValueTypes(N, VT1, VT2);
   N->setOperands(Op1, Op2);
+  
+  ON = N;   // Memoize the new node.
   return SDOperand(N, 0);
 }
 
@@ -1499,10 +1574,21 @@
                                      MVT::ValueType VT1, MVT::ValueType VT2,
                                      SDOperand Op1, SDOperand Op2, 
                                      SDOperand Op3) {
+  // If an identical node already exists, use it.
+  std::vector<SDOperand> OpList;
+  OpList.push_back(Op1); OpList.push_back(Op2); OpList.push_back(Op3);
+  std::vector<MVT::ValueType> VTList;
+  VTList.push_back(VT1); VTList.push_back(VT2);
+  SDNode *&ON = ArbitraryNodes[std::make_pair(ISD::BUILTIN_OP_END+TargetOpc,
+                                              std::make_pair(VTList, OpList))];
+  if (ON) return SDOperand(ON, 0);
+
   RemoveNodeFromCSEMaps(N);
   N->MorphNodeTo(ISD::BUILTIN_OP_END+TargetOpc);
   setNodeValueTypes(N, VT1, VT2);
   N->setOperands(Op1, Op2, Op3);
+  
+  ON = N;   // Memoize the new node.
   return SDOperand(N, 0);
 }
 
@@ -1510,10 +1596,22 @@
                                      MVT::ValueType VT1, MVT::ValueType VT2,
                                      SDOperand Op1, SDOperand Op2,
                                      SDOperand Op3, SDOperand Op4) {
+  // If an identical node already exists, use it.
+  std::vector<SDOperand> OpList;
+  OpList.push_back(Op1); OpList.push_back(Op2); OpList.push_back(Op3);
+  OpList.push_back(Op4);
+  std::vector<MVT::ValueType> VTList;
+  VTList.push_back(VT1); VTList.push_back(VT2);
+  SDNode *&ON = ArbitraryNodes[std::make_pair(ISD::BUILTIN_OP_END+TargetOpc,
+                                              std::make_pair(VTList, OpList))];
+  if (ON) return SDOperand(ON, 0);
+
   RemoveNodeFromCSEMaps(N);
   N->MorphNodeTo(ISD::BUILTIN_OP_END+TargetOpc);
   setNodeValueTypes(N, VT1, VT2);
   N->setOperands(Op1, Op2, Op3, Op4);
+
+  ON = N;   // Memoize the new node.
   return SDOperand(N, 0);
 }
 
@@ -1522,10 +1620,22 @@
                                      SDOperand Op1, SDOperand Op2,
                                      SDOperand Op3, SDOperand Op4, 
                                      SDOperand Op5) {
+  // If an identical node already exists, use it.
+  std::vector<SDOperand> OpList;
+  OpList.push_back(Op1); OpList.push_back(Op2); OpList.push_back(Op3);
+  OpList.push_back(Op4); OpList.push_back(Op5);
+  std::vector<MVT::ValueType> VTList;
+  VTList.push_back(VT1); VTList.push_back(VT2);
+  SDNode *&ON = ArbitraryNodes[std::make_pair(ISD::BUILTIN_OP_END+TargetOpc,
+                                              std::make_pair(VTList, OpList))];
+  if (ON) return SDOperand(ON, 0);
+
   RemoveNodeFromCSEMaps(N);
   N->MorphNodeTo(ISD::BUILTIN_OP_END+TargetOpc);
   setNodeValueTypes(N, VT1, VT2);
   N->setOperands(Op1, Op2, Op3, Op4, Op5);
+  
+  ON = N;   // Memoize the new node.
   return SDOperand(N, 0);
 }
 





From lattner at cs.uiuc.edu  Thu Dec  1 12:09:34 2005
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Thu, 1 Dec 2005 12:09:34 -0600
Subject: [llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp 
Message-ID: <200512011809.MAA18706@zion.cs.uiuc.edu>



Changes in directory llvm/lib/Target/PowerPC:

PPCISelDAGToDAG.cpp updated: 1.134 -> 1.135
---
Log message:

Make sure these get added into the codegenmap when appropriate


---
Diffs of the changes:  (+5 -4)

 PPCISelDAGToDAG.cpp |    9 +++++----
 1 files changed, 5 insertions(+), 4 deletions(-)


Index: llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
diff -u llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp:1.134 llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp:1.135
--- llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp:1.134	Wed Nov 30 21:50:19 2005
+++ llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp	Thu Dec  1 12:09:22 2005
@@ -887,9 +887,10 @@
       return CurDAG->SelectNodeTo(N, PPC::ADDI, MVT::i32,
                                   CurDAG->getTargetFrameIndex(FI, MVT::i32),
                                   getI32Imm(0));
-    return CurDAG->getTargetNode(PPC::ADDI, MVT::i32,
-                                 CurDAG->getTargetFrameIndex(FI, MVT::i32),
-                                 getI32Imm(0));
+    return CodeGenMap[Op] = 
+      CurDAG->getTargetNode(PPC::ADDI, MVT::i32,
+                            CurDAG->getTargetFrameIndex(FI, MVT::i32),
+                            getI32Imm(0));
   }
   case ISD::ConstantPool: {
     Constant *C = cast<ConstantPoolSDNode>(N)->get();
@@ -900,7 +901,7 @@
       Tmp = CurDAG->getTargetNode(PPC::LIS, MVT::i32, CPI);
     if (N->hasOneUse())
       return CurDAG->SelectNodeTo(N, PPC::LA, MVT::i32, Tmp, CPI);
-    return CurDAG->getTargetNode(PPC::LA, MVT::i32, Tmp, CPI);
+    return CodeGenMap[Op] = CurDAG->getTargetNode(PPC::LA, MVT::i32, Tmp, CPI);
   }
   case ISD::FADD: {
     MVT::ValueType Ty = N->getValueType(0);





From lattner at cs.uiuc.edu  Thu Dec  1 12:20:05 2005
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Thu, 1 Dec 2005 12:20:05 -0600
Subject: [llvm-commits] CVS: llvm/lib/Target/IA64/IA64ISelPattern.cpp 
Message-ID: <200512011820.MAA19092@zion.cs.uiuc.edu>



Changes in directory llvm/lib/Target/IA64:

IA64ISelPattern.cpp updated: 1.68 -> 1.69
---
Log message:

IA64 doesn't support the LOCATION node, and for some reason the ISelPattern
stuff isn't using ISelLowering.cpp


---
Diffs of the changes:  (+3 -0)

 IA64ISelPattern.cpp |    3 +++
 1 files changed, 3 insertions(+)


Index: llvm/lib/Target/IA64/IA64ISelPattern.cpp
diff -u llvm/lib/Target/IA64/IA64ISelPattern.cpp:1.68 llvm/lib/Target/IA64/IA64ISelPattern.cpp:1.69
--- llvm/lib/Target/IA64/IA64ISelPattern.cpp:1.68	Fri Oct 28 12:46:36 2005
+++ llvm/lib/Target/IA64/IA64ISelPattern.cpp	Thu Dec  1 12:19:53 2005
@@ -100,6 +100,9 @@
       setOperationAction(ISD::MULHS , MVT::i64  , Expand);
       setOperationAction(ISD::MULHU , MVT::i64  , Expand);
 
+      // We don't have line number support yet.
+      setOperationAction(ISD::LOCATION, MVT::Other, Expand);
+
       computeRegisterProperties();
 
       addLegalFPImmediate(+0.0);





From lattner at cs.uiuc.edu  Thu Dec  1 12:21:47 2005
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Thu, 1 Dec 2005 12:21:47 -0600
Subject: [llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp 
Message-ID: <200512011821.MAA19177@zion.cs.uiuc.edu>



Changes in directory llvm/lib/CodeGen/SelectionDAG:

LegalizeDAG.cpp updated: 1.219 -> 1.220
---
Log message:

Promote line and column number information for our friendly 64-bit targets.


---
Diffs of the changes:  (+10 -3)

 LegalizeDAG.cpp |   13 ++++++++++---
 1 files changed, 10 insertions(+), 3 deletions(-)


Index: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.219 llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.220
--- llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.219	Wed Nov 30 11:12:26 2005
+++ llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp	Thu Dec  1 12:21:35 2005
@@ -615,11 +615,18 @@
       Result = Tmp1;
       break;
     case TargetLowering::Legal:
-      if (Tmp1 != Node->getOperand(0)) {
+      if (Tmp1 != Node->getOperand(0) ||
+          getTypeAction(Node->getOperand(1).getValueType()) == Promote) {
         std::vector<SDOperand> Ops;
         Ops.push_back(Tmp1);
-        Ops.push_back(Node->getOperand(1));  // line # must be legal.
-        Ops.push_back(Node->getOperand(2));  // col # must be legal.
+        if (getTypeAction(Node->getOperand(1).getValueType()) == Legal) {
+          Ops.push_back(Node->getOperand(1));  // line # must be legal.
+          Ops.push_back(Node->getOperand(2));  // col # must be legal.
+        } else {
+          // Otherwise promote them.
+          Ops.push_back(PromoteOp(Node->getOperand(1)));
+          Ops.push_back(PromoteOp(Node->getOperand(2)));
+        }
         Ops.push_back(Node->getOperand(3));  // filename must be legal.
         Ops.push_back(Node->getOperand(4));  // working dir # must be legal.
         Result = DAG.getNode(ISD::LOCATION, MVT::Other, Ops);





From lattner at cs.uiuc.edu  Thu Dec  1 16:48:35 2005
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Thu, 1 Dec 2005 16:48:35 -0600
Subject: [llvm-commits] CVS: llvm/tools/lli/lli.cpp 
Message-ID: <200512012248.QAA12725@zion.cs.uiuc.edu>



Changes in directory llvm/tools/lli:

lli.cpp updated: 1.50 -> 1.51
---
Log message:

If a module has a main, but it is defined externally, refuse to run it.

Attempting to run it will find lli's main, which isn't the desired effect.


---
Diffs of the changes:  (+1 -1)

 lli.cpp |    2 +-
 1 files changed, 1 insertion(+), 1 deletion(-)


Index: llvm/tools/lli/lli.cpp
diff -u llvm/tools/lli/lli.cpp:1.50 llvm/tools/lli/lli.cpp:1.51
--- llvm/tools/lli/lli.cpp:1.50	Sat Oct 22 23:37:20 2005
+++ llvm/tools/lli/lli.cpp	Thu Dec  1 16:48:23 2005
@@ -85,7 +85,7 @@
     // EnvVars to determine envp.
     //
     Function *Fn = MP->getModule()->getMainFunction();
-    if (!Fn) {
+    if (!Fn || Fn->isExternal()) {
       std::cerr << "'main' function not found in module.\n";
       return -1;
     }





From lattner at cs.uiuc.edu  Thu Dec  1 17:14:20 2005
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Thu, 1 Dec 2005 17:14:20 -0600
Subject: [llvm-commits] 
	CVS: llvm/test/Regression/CodeGen/PowerPC/2005-12-01-Crash.ll
Message-ID: <200512012314.RAA12875@zion.cs.uiuc.edu>



Changes in directory llvm/test/Regression/CodeGen/PowerPC:

2005-12-01-Crash.ll added (r1.1)
---
Log message:

New testcase that crashes llc


---
Diffs of the changes:  (+23 -0)

 2005-12-01-Crash.ll |   23 +++++++++++++++++++++++
 1 files changed, 23 insertions(+)


Index: llvm/test/Regression/CodeGen/PowerPC/2005-12-01-Crash.ll
diff -c /dev/null llvm/test/Regression/CodeGen/PowerPC/2005-12-01-Crash.ll:1.1
*** /dev/null	Thu Dec  1 17:14:19 2005
--- llvm/test/Regression/CodeGen/PowerPC/2005-12-01-Crash.ll	Thu Dec  1 17:14:09 2005
***************
*** 0 ****
--- 1,23 ----
+ ; RUN: llvm-as < %s | llc
+ 
+ %str = external global [36 x sbyte]		; <[36 x sbyte]*> [#uses=0]
+ %str = external global [29 x sbyte]		; <[29 x sbyte]*> [#uses=0]
+ %str1 = external global [29 x sbyte]		; <[29 x sbyte]*> [#uses=0]
+ %str2 = external global [29 x sbyte]		; <[29 x sbyte]*> [#uses=1]
+ %str = external global [2 x sbyte]		; <[2 x sbyte]*> [#uses=0]
+ %str3 = external global [2 x sbyte]		; <[2 x sbyte]*> [#uses=0]
+ %str4 = external global [2 x sbyte]		; <[2 x sbyte]*> [#uses=0]
+ %str5 = external global [2 x sbyte]		; <[2 x sbyte]*> [#uses=0]
+ 
+ implementation   ; Functions:
+ 
+ void %printArgsNoRet(int %a1, float %a2, sbyte %a3, double %a4, sbyte* %a5, int %a6, float %a7, sbyte %a8, double %a9, sbyte* %a10, int %a11, float %a12, sbyte %a13, double %a14, sbyte* %a15) {
+ entry:
+ 	%tmp17 = cast sbyte %a13 to int		; <int> [#uses=1]
+ 	%tmp23 = call int (sbyte*, ...)* %printf( sbyte* getelementptr ([29 x sbyte]* %str2, int 0, uint 0), int %a11, double 0.000000e+00, int %tmp17, double %a14, int 0 )		; <int> [#uses=0]
+ 	ret void
+ }
+ 
+ declare int %printf(sbyte*, ...)
+ 
+ declare int %main(int, sbyte**)





From lattner at cs.uiuc.edu  Thu Dec  1 17:15:01 2005
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Thu, 1 Dec 2005 17:15:01 -0600
Subject: [llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp 
Message-ID: <200512012315.RAA12939@zion.cs.uiuc.edu>



Changes in directory llvm/lib/CodeGen/SelectionDAG:

SelectionDAG.cpp updated: 1.221 -> 1.222
---
Log message:

Don't remove two operand, two result nodes from the binary ops map.  These
should come from the arbitrary ops map.

This fixes Regression/CodeGen/PowerPC/2005-12-01-Crash.ll


---
Diffs of the changes:  (+40 -37)

 SelectionDAG.cpp |   77 ++++++++++++++++++++++++++++---------------------------
 1 files changed, 40 insertions(+), 37 deletions(-)


Index: llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp:1.221 llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp:1.222
--- llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp:1.221	Thu Dec  1 12:00:57 2005
+++ llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp	Thu Dec  1 17:14:50 2005
@@ -388,43 +388,46 @@
 SDNode *SelectionDAG::AddNonLeafNodeToCSEMaps(SDNode *N) {
   assert(N->getNumOperands() && "This is a leaf node!");
   if (N->getOpcode() == ISD::CALLSEQ_START || 
-      N->getOpcode() == ISD::CALLSEQ_END)
-    return 0;
-  
-  if (N->getOpcode() == ISD::LOAD) {
-    SDNode *&L = Loads[std::make_pair(N->getOperand(1),
-                                      std::make_pair(N->getOperand(0),
-                                                     N->getValueType(0)))];
-    if (L) return L;
-    L = N;
-  } else if (N->getOpcode() == ISD::HANDLENODE) {
-    return 0;  // never add it.
-  } else if (N->getNumOperands() == 1) {
-    SDNode *&U = UnaryOps[std::make_pair(N->getOpcode(),
-                                         std::make_pair(N->getOperand(0),
-                                                        N->getValueType(0)))];
-    if (U) return U;
-    U = N;
-  } else if (N->getNumOperands() == 2) {
-    SDNode *&B = BinaryOps[std::make_pair(N->getOpcode(),
-                                          std::make_pair(N->getOperand(0),
-                                                         N->getOperand(1)))];
-    if (B) return B;
-    B = N;
-  } else if (N->getNumValues() == 1) {
-    std::vector<SDOperand> Ops(N->op_begin(), N->op_end());
-    SDNode *&ORN = OneResultNodes[std::make_pair(N->getOpcode(),
-                                  std::make_pair(N->getValueType(0), Ops))];
-    if (ORN) return ORN;
-    ORN = N;
-  } else {
-    // Remove the node from the ArbitraryNodes map.
-    std::vector<MVT::ValueType> RV(N->value_begin(), N->value_end());
-    std::vector<SDOperand>     Ops(N->op_begin(), N->op_end());
-    SDNode *&AN = ArbitraryNodes[std::make_pair(N->getOpcode(),
-                                                std::make_pair(RV, Ops))];
-    if (AN) return AN;
-    AN = N;
+      N->getOpcode() == ISD::CALLSEQ_END ||
+      N->getOpcode() == ISD::HANDLENODE)
+    return 0;    // Never add these nodes.
+  
+  if (N->getNumValues() == 1) {
+    if (N->getNumOperands() == 1) {
+      SDNode *&U = UnaryOps[std::make_pair(N->getOpcode(),
+                                           std::make_pair(N->getOperand(0),
+                                                          N->getValueType(0)))];
+      if (U) return U;
+      U = N;
+    } else if (N->getNumOperands() == 2) {
+      SDNode *&B = BinaryOps[std::make_pair(N->getOpcode(),
+                                            std::make_pair(N->getOperand(0),
+                                                           N->getOperand(1)))];
+      if (B) return B;
+      B = N;
+    } else {
+      std::vector<SDOperand> Ops(N->op_begin(), N->op_end());
+      SDNode *&ORN = OneResultNodes[std::make_pair(N->getOpcode(),
+                                                   std::make_pair(N->getValueType(0), Ops))];
+      if (ORN) return ORN;
+      ORN = N;
+    }
+  } else {  
+    if (N->getOpcode() == ISD::LOAD) {
+      SDNode *&L = Loads[std::make_pair(N->getOperand(1),
+                                        std::make_pair(N->getOperand(0),
+                                                       N->getValueType(0)))];
+      if (L) return L;
+      L = N;
+    } else {
+      // Remove the node from the ArbitraryNodes map.
+      std::vector<MVT::ValueType> RV(N->value_begin(), N->value_end());
+      std::vector<SDOperand>     Ops(N->op_begin(), N->op_end());
+      SDNode *&AN = ArbitraryNodes[std::make_pair(N->getOpcode(),
+                                                  std::make_pair(RV, Ops))];
+      if (AN) return AN;
+      AN = N;
+    }
   }
   return 0;
 }





From lattner at cs.uiuc.edu  Thu Dec  1 18:11:31 2005
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Thu, 1 Dec 2005 18:11:31 -0600
Subject: [llvm-commits] CVS: llvm/lib/Target/X86/README.txt 
Message-ID: <200512020011.SAA25579@zion.cs.uiuc.edu>



Changes in directory llvm/lib/Target/X86:

README.txt updated: 1.17 -> 1.18
---
Log message:

add a note


---
Diffs of the changes:  (+6 -0)

 README.txt |    6 ++++++
 1 files changed, 6 insertions(+)


Index: llvm/lib/Target/X86/README.txt
diff -u llvm/lib/Target/X86/README.txt:1.17 llvm/lib/Target/X86/README.txt:1.18
--- llvm/lib/Target/X86/README.txt:1.17	Sun Nov 27 22:52:39 2005
+++ llvm/lib/Target/X86/README.txt	Thu Dec  1 18:11:20 2005
@@ -12,6 +12,12 @@
 by using the EAX result from the mul.  We should add a similar node for
 DIVREM.
 
+another case is:
+
+long long test(int X, int Y) { return (long long)X*Y; }
+
+... which should only be one imul instruction.
+
 //===---------------------------------------------------------------------===//
 
 This should be one DIV/IDIV instruction, not a libcall:





From alenhar2 at cs.uiuc.edu  Thu Dec  1 22:56:35 2005
From: alenhar2 at cs.uiuc.edu (Andrew Lenharth)
Date: Thu, 1 Dec 2005 22:56:35 -0600
Subject: [llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp 
Message-ID: <200512020456.WAA28799@zion.cs.uiuc.edu>



Changes in directory llvm/lib/CodeGen/SelectionDAG:

LegalizeDAG.cpp updated: 1.220 -> 1.221
---
Log message:

cycle counter fix

---
Diffs of the changes:  (+6 -0)

 LegalizeDAG.cpp |    6 ++++++
 1 files changed, 6 insertions(+)


Index: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.220 llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.221
--- llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.220	Thu Dec  1 12:21:35 2005
+++ llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp	Thu Dec  1 22:56:24 2005
@@ -1193,6 +1193,12 @@
     Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain
     if (Tmp1 != Node->getOperand(0))
       Result = DAG.getNode(ISD::READCYCLECOUNTER, MVT::i64, Tmp1);
+
+    // Since rdcc produce two values, make sure to remember that we legalized
+    // both of them.
+    AddLegalizedOperand(SDOperand(Node, 0), Result);
+    AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1));
+    return Result.getValue(Op.ResNo);
     break;
 
   case ISD::TRUNCSTORE:





From alenhar2 at cs.uiuc.edu  Fri Dec  2 00:08:20 2005
From: alenhar2 at cs.uiuc.edu (Andrew Lenharth)
Date: Fri, 2 Dec 2005 00:08:20 -0600
Subject: [llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp 
Message-ID: <200512020608.AAA29030@zion.cs.uiuc.edu>



Changes in directory llvm/lib/CodeGen/SelectionDAG:

LegalizeDAG.cpp updated: 1.221 -> 1.222
---
Log message:

bah, must generate all results

---
Diffs of the changes:  (+8 -2)

 LegalizeDAG.cpp |   10 ++++++++--
 1 files changed, 8 insertions(+), 2 deletions(-)


Index: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.221 llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.222
--- llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.221	Thu Dec  1 22:56:24 2005
+++ llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp	Fri Dec  2 00:08:08 2005
@@ -1191,8 +1191,14 @@
     break;
   case ISD::READCYCLECOUNTER:
     Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain
-    if (Tmp1 != Node->getOperand(0))
-      Result = DAG.getNode(ISD::READCYCLECOUNTER, MVT::i64, Tmp1);
+    if (Tmp1 != Node->getOperand(0)) {
+      std::vector<MVT::ValueType> rtypes;
+      std::vector<SDOperand> rvals;
+      rtypes.push_back(MVT::i64);
+      rtypes.push_back(MVT::Other);
+      rvals.push_back(Tmp1);
+      Result = DAG.getNode(ISD::READCYCLECOUNTER, rtypes, rvals);
+    }
 
     // Since rdcc produce two values, make sure to remember that we legalized
     // both of them.





From lattner at cs.uiuc.edu  Fri Dec  2 13:00:34 2005
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Fri, 2 Dec 2005 13:00:34 -0600
Subject: [llvm-commits] CVS: llvm/tools/lli/lli.cpp 
Message-ID: <200512021900.NAA29835@zion.cs.uiuc.edu>



Changes in directory llvm/tools/lli:

lli.cpp updated: 1.51 -> 1.52
---
Log message:

Revert my previous patch which broke due to lazy streaming of functions
from .bc files.


---
Diffs of the changes:  (+1 -1)

 lli.cpp |    2 +-
 1 files changed, 1 insertion(+), 1 deletion(-)


Index: llvm/tools/lli/lli.cpp
diff -u llvm/tools/lli/lli.cpp:1.51 llvm/tools/lli/lli.cpp:1.52
--- llvm/tools/lli/lli.cpp:1.51	Thu Dec  1 16:48:23 2005
+++ llvm/tools/lli/lli.cpp	Fri Dec  2 13:00:22 2005
@@ -85,7 +85,7 @@
     // EnvVars to determine envp.
     //
     Function *Fn = MP->getModule()->getMainFunction();
-    if (!Fn || Fn->isExternal()) {
+    if (!Fn) {
       std::cerr << "'main' function not found in module.\n";
       return -1;
     }





From alenhar2 at cs.uiuc.edu  Fri Dec  2 13:16:29 2005
From: alenhar2 at cs.uiuc.edu (Andrew Lenharth)
Date: Fri, 2 Dec 2005 13:16:29 -0600
Subject: [llvm-commits] CVS: llvm-test/External/SPEC/CINT95/Makefile 
Message-ID: <200512021916.NAA29987@zion.cs.uiuc.edu>



Changes in directory llvm-test/External/SPEC/CINT95:

Makefile updated: 1.7 -> 1.8
---
Log message:

134.perl is causing major problems for sabi, so I am filtering it out on alpha until it can be tracked down

---
Diffs of the changes:  (+8 -0)

 Makefile |    8 ++++++++
 1 files changed, 8 insertions(+)


Index: llvm-test/External/SPEC/CINT95/Makefile
diff -u llvm-test/External/SPEC/CINT95/Makefile:1.7 llvm-test/External/SPEC/CINT95/Makefile:1.8
--- llvm-test/External/SPEC/CINT95/Makefile:1.7	Mon Sep  6 23:18:02 2004
+++ llvm-test/External/SPEC/CINT95/Makefile	Fri Dec  2 13:16:17 2005
@@ -10,4 +10,12 @@
   147.vortex
 
 # Get the $(ARCH) setting
+include ${LEVEL}/Makefile.config
+
+ifeq ($(ARCH), Alpha)
+PARALLEL_DIRS := $(filter-out 134.perl, $(PARALLEL_DIRS))
+endif
+
+# Include the standard makefiles
 include ${LEVEL}/External/Makefile.external
+





From lattner at cs.uiuc.edu  Sat Dec  3 01:14:59 2005
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Sat, 3 Dec 2005 01:14:59 -0600
Subject: [llvm-commits] 
	CVS: llvm/test/Regression/ExecutionEngine/2005-12-02-TailCallBug.ll
Message-ID: <200512030714.BAA15011@zion.cs.uiuc.edu>



Changes in directory llvm/test/Regression/ExecutionEngine:

2005-12-02-TailCallBug.ll added (r1.1)
---
Log message:

new testcase for PR672: http://llvm.cs.uiuc.edu/PR672 


---
Diffs of the changes:  (+22 -0)

 2005-12-02-TailCallBug.ll |   22 ++++++++++++++++++++++
 1 files changed, 22 insertions(+)


Index: llvm/test/Regression/ExecutionEngine/2005-12-02-TailCallBug.ll
diff -c /dev/null llvm/test/Regression/ExecutionEngine/2005-12-02-TailCallBug.ll:1.1
*** /dev/null	Sat Dec  3 01:14:57 2005
--- llvm/test/Regression/ExecutionEngine/2005-12-02-TailCallBug.ll	Sat Dec  3 01:14:47 2005
***************
*** 0 ****
--- 1,22 ----
+ ; RUN: llvm-as %s | lli
+ 
+ ; PR672
+ 
+ int %main(){ 
+  %f   = cast int (int, int*, int)* %check_tail to int*
+  %res = tail call fastcc int %check_tail( int 10, int* %f,int 10)
+  ret int %res
+ }
+ fastcc int %check_tail(int %x, int* %f, int %g) {
+ 	%tmp1 = setgt int %x, 0
+ 	br bool %tmp1, label %if-then, label %if-else
+ 
+ if-then:
+ 	%fun_ptr = cast int* %f to int(int, int*, int)*	
+ 	%arg1    = add int %x, -1		
+ 	%res = tail call fastcc int %fun_ptr( int %arg1, int * %f, int %g)
+ 	ret int %res
+ 
+ if-else:
+         ret int %x
+ }





From lattner at cs.uiuc.edu  Sat Dec  3 01:16:07 2005
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Sat, 3 Dec 2005 01:16:07 -0600
Subject: [llvm-commits] CVS: llvm/lib/Target/X86/X86ISelPattern.cpp 
Message-ID: <200512030716.BAA15028@zion.cs.uiuc.edu>



Changes in directory llvm/lib/Target/X86:

X86ISelPattern.cpp updated: 1.186 -> 1.187
---
Log message:

Fix test/Regression/ExecutionEngine/2005-12-02-TailCallBug.ll and PR672: http://llvm.cs.uiuc.edu/PR672 .

This also fixes 177.mesa, the only program that fails with --enable-x86-fastcc
turned on.  Given a clean nightly tester run, we should be able to turn it
on by default!


---
Diffs of the changes:  (+14 -0)

 X86ISelPattern.cpp |   14 ++++++++++++++
 1 files changed, 14 insertions(+)


Index: llvm/lib/Target/X86/X86ISelPattern.cpp
diff -u llvm/lib/Target/X86/X86ISelPattern.cpp:1.186 llvm/lib/Target/X86/X86ISelPattern.cpp:1.187
--- llvm/lib/Target/X86/X86ISelPattern.cpp:1.186	Sun Nov 20 15:41:10 2005
+++ llvm/lib/Target/X86/X86ISelPattern.cpp	Sat Dec  3 01:15:55 2005
@@ -3067,6 +3067,20 @@
 
   // TODO: handle jmp [mem]
   if (!isDirect) {
+    // We do not want the register allocator to allocate CalleeReg to a callee 
+    // saved register, as these will be restored before the JMP.  To prevent
+    // this, emit explicit clobbers of callee saved regs here.  A better way to
+    // solve this would be to specify that the register constraints of TAILJMPr
+    // only allow registers that are not callee saved, but we currently can't
+    // express that.  This forces all four of these regs to be saved and 
+    // reloaded for all functions with an indirect tail call.
+    // TODO: Improve this!
+    BuildMI(BB, X86::IMPLICIT_DEF, 4)
+       .addReg(X86::ESI, MachineOperand::Def)
+       .addReg(X86::EDI, MachineOperand::Def)
+       .addReg(X86::EBX, MachineOperand::Def)
+       .addReg(X86::EBP, MachineOperand::Def);
+    
     BuildMI(BB, X86::TAILJMPr, 1).addReg(CalleeReg);
   } else if (GlobalAddressSDNode *GASD = dyn_cast<GlobalAddressSDNode>(Callee)){
     BuildMI(BB, X86::TAILJMPd, 1).addGlobalAddress(GASD->getGlobal(), true);





From lattner at cs.uiuc.edu  Sat Dec  3 11:21:16 2005
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Sat, 3 Dec 2005 11:21:16 -0600
Subject: [llvm-commits] 
	CVS: llvm/test/Regression/ExecutionEngine/2005-12-02-TailCallBug.ll
Message-ID: <200512031721.LAA20621@zion.cs.uiuc.edu>



Changes in directory llvm/test/Regression/ExecutionEngine:

2005-12-02-TailCallBug.ll updated: 1.1 -> 1.2
---
Log message:

Fix a bug in the testcase


---
Diffs of the changes:  (+1 -1)

 2005-12-02-TailCallBug.ll |    2 +-
 1 files changed, 1 insertion(+), 1 deletion(-)


Index: llvm/test/Regression/ExecutionEngine/2005-12-02-TailCallBug.ll
diff -u llvm/test/Regression/ExecutionEngine/2005-12-02-TailCallBug.ll:1.1 llvm/test/Regression/ExecutionEngine/2005-12-02-TailCallBug.ll:1.2
--- llvm/test/Regression/ExecutionEngine/2005-12-02-TailCallBug.ll:1.1	Sat Dec  3 01:14:47 2005
+++ llvm/test/Regression/ExecutionEngine/2005-12-02-TailCallBug.ll	Sat Dec  3 11:20:57 2005
@@ -1,4 +1,4 @@
-; RUN: llvm-as %s | lli
+; RUN: llvm-as < %s | lli
 
 ; PR672
 





From lattner at cs.uiuc.edu  Sat Dec  3 12:25:43 2005
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Sat, 3 Dec 2005 12:25:43 -0600
Subject: [llvm-commits] 
	CVS: llvm/test/Regression/Transforms/SimplifyCFG/2005-12-03-IncorrectPHIFold.ll
Message-ID: <200512031825.MAA31387@zion.cs.uiuc.edu>



Changes in directory llvm/test/Regression/Transforms/SimplifyCFG:

2005-12-03-IncorrectPHIFold.ll added (r1.1)
---
Log message:

new testcase, miscompiled by simplifycfg.  This has been distilled from Ptrdist/bc


---
Diffs of the changes:  (+138 -0)

 2005-12-03-IncorrectPHIFold.ll |  138 +++++++++++++++++++++++++++++++++++++++++
 1 files changed, 138 insertions(+)


Index: llvm/test/Regression/Transforms/SimplifyCFG/2005-12-03-IncorrectPHIFold.ll
diff -c /dev/null llvm/test/Regression/Transforms/SimplifyCFG/2005-12-03-IncorrectPHIFold.ll:1.1
*** /dev/null	Sat Dec  3 12:25:42 2005
--- llvm/test/Regression/Transforms/SimplifyCFG/2005-12-03-IncorrectPHIFold.ll	Sat Dec  3 12:25:32 2005
***************
*** 0 ****
--- 1,138 ----
+ ; Make sure this doesn't turn into an infinite loop
+ 
+ ; RUN: llvm-as < %s | opt -simplifycfg -constprop -simplifycfg | llvm-dis | grep bb86
+ 
+ 	%struct.anon = type { uint, int, int, int, [1024 x sbyte] }
+ %_zero_ = external global %struct.anon*		; <%struct.anon**> [#uses=2]
+ %_one_ = external global %struct.anon*		; <%struct.anon**> [#uses=4]
+ %str = internal constant [4 x sbyte] c"%d\0A\00"		; <[4 x sbyte]*> [#uses=1]
+ 
+ implementation   ; Functions:
+ 
+ 
+ declare int %bc_compare(%struct.anon*, %struct.anon*)
+ 
+ declare void %free_num(%struct.anon**)
+ 
+ declare %struct.anon* %copy_num(%struct.anon*)
+ 
+ declare void %init_num(%struct.anon**)
+ 
+ declare %struct.anon* %new_num(int, int)
+ 
+ declare void %int2num(%struct.anon**, int)
+ 
+ declare void %bc_multiply(%struct.anon*, %struct.anon*, %struct.anon**, int)
+ 
+ declare void %bc_raise(%struct.anon*, %struct.anon*, %struct.anon**, int)
+ 
+ declare int %bc_divide(%struct.anon*, %struct.anon*, %struct.anon**, int)
+ 
+ declare void %bc_add(%struct.anon*, %struct.anon*, %struct.anon**)
+ 
+ declare int %_do_compare(%struct.anon*, %struct.anon*, int, int)
+ 
+ declare int %printf(sbyte*, ...)
+ 
+ int %bc_sqrt(%struct.anon** %num, int %scale) {
+ entry:
+ 	%guess = alloca %struct.anon*		; <%struct.anon**> [#uses=15]
+ 	%guess1 = alloca %struct.anon*		; <%struct.anon**> [#uses=12]
+ 	%point5 = alloca %struct.anon*		; <%struct.anon**> [#uses=4]
+ 	%tmp = load %struct.anon** %num		; <%struct.anon*> [#uses=1]
+ 	%tmp1 = load %struct.anon** %_zero_		; <%struct.anon*> [#uses=1]
+ 	%tmp = call int %bc_compare( %struct.anon* %tmp, %struct.anon* %tmp1 )		; <int> [#uses=2]
+ 	%tmp = setlt int %tmp, 0		; <bool> [#uses=1]
+ 	br bool %tmp, label %cond_true, label %cond_false
+ 
+ cond_true:		; preds = %entry
+ 	ret int 0
+ 
+ cond_false:		; preds = %entry
+ 	%tmp5 = seteq int %tmp, 0		; <bool> [#uses=1]
+ 	br bool %tmp5, label %cond_true6, label %cond_next13
+ 
+ cond_true6:		; preds = %cond_false
+ 	call void %free_num( %struct.anon** %num )
+ 	%tmp8 = load %struct.anon** %_zero_		; <%struct.anon*> [#uses=1]
+ 	%tmp9 = call %struct.anon* %copy_num( %struct.anon* %tmp8 )		; <%struct.anon*> [#uses=1]
+ 	store %struct.anon* %tmp9, %struct.anon** %num
+ 	ret int 1
+ 
+ cond_next13:		; preds = %cond_false
+ 	%tmp15 = load %struct.anon** %num		; <%struct.anon*> [#uses=1]
+ 	%tmp16 = load %struct.anon** %_one_		; <%struct.anon*> [#uses=1]
+ 	%tmp17 = call int %bc_compare( %struct.anon* %tmp15, %struct.anon* %tmp16 )		; <int> [#uses=2]
+ 	%tmp19 = seteq int %tmp17, 0		; <bool> [#uses=1]
+ 	br bool %tmp19, label %cond_true20, label %cond_next27
+ 
+ cond_true20:		; preds = %cond_next13
+ 	call void %free_num( %struct.anon** %num )
+ 	%tmp22 = load %struct.anon** %_one_		; <%struct.anon*> [#uses=1]
+ 	%tmp23 = call %struct.anon* %copy_num( %struct.anon* %tmp22 )		; <%struct.anon*> [#uses=1]
+ 	store %struct.anon* %tmp23, %struct.anon** %num
+ 	ret int 1
+ 
+ cond_next27:		; preds = %cond_next13
+ 	%tmp29 = load %struct.anon** %num		; <%struct.anon*> [#uses=1]
+ 	%tmp30 = getelementptr %struct.anon* %tmp29, int 0, uint 2		; <int*> [#uses=1]
+ 	%tmp31 = load int* %tmp30		; <int> [#uses=2]
+ 	%tmp33 = setge int %tmp31, %scale		; <bool> [#uses=1]
+ 	%max = select bool %tmp33, int %tmp31, int %scale		; <int> [#uses=4]
+ 	%tmp35 = add int %max, 2		; <int> [#uses=2]
+ 	call void %init_num( %struct.anon** %guess )
+ 	call void %init_num( %struct.anon** %guess1 )
+ 	%tmp36 = call %struct.anon* %new_num( int 1, int 1 )		; <%struct.anon*> [#uses=2]
+ 	store %struct.anon* %tmp36, %struct.anon** %point5
+ 	%tmp = getelementptr %struct.anon* %tmp36, int 0, uint 4, int 1		; <sbyte*> [#uses=1]
+ 	store sbyte 5, sbyte* %tmp
+ 	%tmp39 = setlt int %tmp17, 0		; <bool> [#uses=1]
+ 	br bool %tmp39, label %cond_true40, label %cond_false43
+ 
+ cond_true40:		; preds = %cond_next27
+ 	%tmp41 = load %struct.anon** %_one_		; <%struct.anon*> [#uses=1]
+ 	%tmp42 = call %struct.anon* %copy_num( %struct.anon* %tmp41 )		; <%struct.anon*> [#uses=1]
+ 	store %struct.anon* %tmp42, %struct.anon** %guess
+ 	br label %bb80.outer
+ 
+ cond_false43:		; preds = %cond_next27
+ 	call void %int2num( %struct.anon** %guess, int 10 )
+ 	%tmp45 = load %struct.anon** %num		; <%struct.anon*> [#uses=1]
+ 	%tmp46 = getelementptr %struct.anon* %tmp45, int 0, uint 1		; <int*> [#uses=1]
+ 	%tmp47 = load int* %tmp46		; <int> [#uses=1]
+ 	call void %int2num( %struct.anon** %guess1, int %tmp47 )
+ 	%tmp48 = load %struct.anon** %guess1		; <%struct.anon*> [#uses=1]
+ 	%tmp49 = load %struct.anon** %point5		; <%struct.anon*> [#uses=1]
+ 	call void %bc_multiply( %struct.anon* %tmp48, %struct.anon* %tmp49, %struct.anon** %guess1, int %max )
+ 	%tmp51 = load %struct.anon** %guess1		; <%struct.anon*> [#uses=1]
+ 	%tmp52 = getelementptr %struct.anon* %tmp51, int 0, uint 2		; <int*> [#uses=1]
+ 	store int 0, int* %tmp52
+ 	%tmp53 = load %struct.anon** %guess		; <%struct.anon*> [#uses=1]
+ 	%tmp54 = load %struct.anon** %guess1		; <%struct.anon*> [#uses=1]
+ 	call void %bc_raise( %struct.anon* %tmp53, %struct.anon* %tmp54, %struct.anon** %guess, int %max )
+ 	br label %bb80.outer
+ 
+ bb80.outer:		; preds = %cond_true77, %cond_next56
+ 	%done.1.ph = phi int [ 1, %cond_true83 ], [0, %cond_true40], [0, %cond_false43]		; <int> [#uses=1]
+ 	br label %bb80
+ 
+ bb80:		; preds = %bb80.outer, %cond_true83
+ 	%tmp82 = seteq int %done.1.ph, 0		; <bool> [#uses=1]
+ 	br bool %tmp82, label %cond_true83, label %bb86
+ 
+ cond_true83:		; preds = %bb80
+ 	%tmp71 = call int %_do_compare( %struct.anon* null, %struct.anon* null, int 0, int 1 )		; <int> [#uses=2]
+ 	%tmp76 = seteq int %tmp71, 0		; <bool> [#uses=1]
+ 	br bool %tmp76, label %bb80.outer, label %bb80
+ 
+ bb86:		; preds = %bb80
+ 	call void %free_num( %struct.anon** %num )
+ 	%tmp88 = load %struct.anon** %guess		; <%struct.anon*> [#uses=1]
+ 	%tmp89 = load %struct.anon** %_one_		; <%struct.anon*> [#uses=1]
+ 	%tmp92 = call int %bc_divide( %struct.anon* %tmp88, %struct.anon* %tmp89, %struct.anon** %num, int %max )		; <int> [#uses=0]
+ 	call void %free_num( %struct.anon** %guess )
+ 	call void %free_num( %struct.anon** %guess1 )
+ 	call void %free_num( %struct.anon** %point5 )
+ 	ret int 1
+ }
+ 





From lattner at cs.uiuc.edu  Sat Dec  3 12:26:10 2005
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Sat, 3 Dec 2005 12:26:10 -0600
Subject: [llvm-commits] CVS: llvm/lib/Transforms/Utils/SimplifyCFG.cpp 
Message-ID: <200512031826.MAA31422@zion.cs.uiuc.edu>



Changes in directory llvm/lib/Transforms/Utils:

SimplifyCFG.cpp updated: 1.92 -> 1.93
---
Log message:

Fix SimplifyCFG/2005-12-03-IncorrectPHIFold.ll


---
Diffs of the changes:  (+14 -8)

 SimplifyCFG.cpp |   22 ++++++++++++++--------
 1 files changed, 14 insertions(+), 8 deletions(-)


Index: llvm/lib/Transforms/Utils/SimplifyCFG.cpp
diff -u llvm/lib/Transforms/Utils/SimplifyCFG.cpp:1.92 llvm/lib/Transforms/Utils/SimplifyCFG.cpp:1.93
--- llvm/lib/Transforms/Utils/SimplifyCFG.cpp:1.92	Mon Oct  3 18:43:43 2005
+++ llvm/lib/Transforms/Utils/SimplifyCFG.cpp	Sat Dec  3 12:25:58 2005
@@ -82,7 +82,7 @@
   //
   if (isa<PHINode>(Succ->front())) {
     std::set<BasicBlock*> BBPreds(pred_begin(BB), pred_end(BB));
-    for (pred_iterator PI = pred_begin(Succ), PE = pred_end(Succ);\
+    for (pred_iterator PI = pred_begin(Succ), PE = pred_end(Succ);
          PI != PE; ++PI)
       if (std::find(BBPreds.begin(), BBPreds.end(), *PI) != BBPreds.end()) {
         // Loop over all of the PHI nodes checking to see if there are
@@ -115,19 +115,25 @@
     }
   if (IsSafe) return true;
   
-  // If the PHI nodes in BB are only used by instructions in Succ, we are ok.
-  IsSafe = true;
+  // If the PHI nodes in BB are only used by instructions in Succ, we are ok if
+  // BB and Succ have no common predecessors.
   for (BasicBlock::iterator I = BB->begin(); isa<PHINode>(I) && IsSafe; ++I) {
     PHINode *PN = cast<PHINode>(I);
     for (Value::use_iterator UI = PN->use_begin(), E = PN->use_end(); UI != E;
          ++UI)
-      if (cast<Instruction>(*UI)->getParent() != Succ) {
-        IsSafe = false;
-        break;
-      }
+      if (cast<Instruction>(*UI)->getParent() != Succ)
+        return false;
   }
   
-  return IsSafe;
+  // Scan the predecessor sets of BB and Succ, making sure there are no common
+  // predecessors.  Common predecessors would cause us to build a phi node with
+  // differing incoming values, which is not legal.
+  std::set<BasicBlock*> BBPreds(pred_begin(BB), pred_end(BB));
+  for (pred_iterator PI = pred_begin(Succ), E = pred_end(Succ); PI != E; ++PI)
+    if (BBPreds.count(*PI))
+      return false;
+    
+  return true;
 }
 
 /// TryToSimplifyUncondBranchFromEmptyBlock - BB contains an unconditional





From lattner at cs.uiuc.edu  Sat Dec  3 12:26:53 2005
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Sat, 3 Dec 2005 12:26:53 -0600
Subject: [llvm-commits] 
	CVS: llvm/test/Regression/Transforms/SimplifyCFG/PhiEliminate.ll
Message-ID: <200512031826.MAA31483@zion.cs.uiuc.edu>



Changes in directory llvm/test/Regression/Transforms/SimplifyCFG:

PhiEliminate.ll updated: 1.4 -> 1.5
---
Log message:

expand testcase, which has been in my tree for a while now


---
Diffs of the changes:  (+29 -1)

 PhiEliminate.ll |   30 +++++++++++++++++++++++++++++-
 1 files changed, 29 insertions(+), 1 deletion(-)


Index: llvm/test/Regression/Transforms/SimplifyCFG/PhiEliminate.ll
diff -u llvm/test/Regression/Transforms/SimplifyCFG/PhiEliminate.ll:1.4 llvm/test/Regression/Transforms/SimplifyCFG/PhiEliminate.ll:1.5
--- llvm/test/Regression/Transforms/SimplifyCFG/PhiEliminate.ll:1.4	Tue Mar 30 13:45:39 2004
+++ llvm/test/Regression/Transforms/SimplifyCFG/PhiEliminate.ll	Sat Dec  3 12:26:41 2005
@@ -9,6 +9,35 @@
 declare void %use(bool)
 declare void %use(int)
 
+
+void %test2(bool %c, bool %d, int %V, int %V2) {
+	br bool %d, label %X, label %F
+X:
+	br bool %c, label %T, label %F
+T:
+	br label %F
+F:
+	%B1 = phi bool [true, %0], [false, %T], [false, %X]
+	%B2 = phi bool [true, %T], [false, %0], [false, %X]
+	%I1 = phi int  [1, %T], [0, %0], [2, %X]
+	%I2 = phi int  [1, %0], [0, %T], [3, %X]
+	%I3 = phi int  [17, %T], [0, %0], [4, %X]
+	%I4 = phi int  [17, %T], [5, %0], [44, %X]
+	%I5 = phi int  [%V, %T], [0, %0], [%V, %X]
+	%I6 = phi int  [%V, %0], [0, %T], [%V, %X]
+	%I7 = phi int  [%V, %0], [%V2, %T], [%V2, %X]
+	call void %use(bool %B1)
+	call void %use(bool %B2)
+	call void %use(int  %I1)
+	call void %use(int  %I2)
+	call void %use(int  %I3)
+	call void %use(int  %I4)
+	call void %use(int  %I5)
+	call void %use(int  %I6)
+	call void %use(int  %I7)
+	ret void
+}
+
 void %test(bool %c, int %V, int %V2) {
 	br bool %c, label %T, label %F
 T:
@@ -34,4 +63,3 @@
 	call void %use(int  %I7)
 	ret void
 }
-





From lattner at cs.uiuc.edu  Sat Dec  3 12:51:00 2005
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Sat, 3 Dec 2005 12:51:00 -0600
Subject: [llvm-commits] 
	CVS: llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
Message-ID: <200512031851.MAA07854@zion.cs.uiuc.edu>



Changes in directory llvm/lib/CodeGen/SelectionDAG:

SelectionDAGISel.cpp updated: 1.108 -> 1.109
---
Log message:

dbg.stoppoint returns a value, don't forget to init it


---
Diffs of the changes:  (+1 -0)

 SelectionDAGISel.cpp |    1 +
 1 files changed, 1 insertion(+)


Index: llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.108 llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.109
--- llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.108	Wed Nov 30 02:22:07 2005
+++ llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp	Sat Dec  3 12:50:48 2005
@@ -891,6 +891,7 @@
     Ops.push_back(DAG.getString(fname));
     Ops.push_back(DAG.getString(""));
     DAG.setRoot(DAG.getNode(ISD::LOCATION, MVT::Other, Ops));
+    setValue(&I, DAG.getNode(ISD::UNDEF, TLI.getValueType(I.getType())));
     return 0;
   }
   case Intrinsic::dbg_region_start:





From lattner at cs.uiuc.edu  Sun Dec  4 00:03:36 2005
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Sun, 4 Dec 2005 00:03:36 -0600
Subject: [llvm-commits] 
	CVS: llvm/test/Regression/CodeGen/X86/2005-12-03-IndirectTailCall.ll
Message-ID: <200512040603.AAA11203@zion.cs.uiuc.edu>



Changes in directory llvm/test/Regression/CodeGen/X86:

2005-12-03-IndirectTailCall.ll added (r1.1)
---
Log message:

new testcase, for PR672: http://llvm.cs.uiuc.edu/PR672 


---
Diffs of the changes:  (+24 -0)

 2005-12-03-IndirectTailCall.ll |   24 ++++++++++++++++++++++++
 1 files changed, 24 insertions(+)


Index: llvm/test/Regression/CodeGen/X86/2005-12-03-IndirectTailCall.ll
diff -c /dev/null llvm/test/Regression/CodeGen/X86/2005-12-03-IndirectTailCall.ll:1.1
*** /dev/null	Sun Dec  4 00:03:35 2005
--- llvm/test/Regression/CodeGen/X86/2005-12-03-IndirectTailCall.ll	Sun Dec  4 00:03:25 2005
***************
*** 0 ****
--- 1,24 ----
+ ; RUN: llvm-as < %s | llc -march=x86 -enable-x86-fastcc | grep 'jmp \*%ecx'
+ declare int %putchar(int)
+ 
+ int %main(){ 
+  %f   = cast int (int, int*, int)* %check_tail to int*
+  %res = tail call fastcc int %check_tail( int 10, int* %f,int 10)
+  ret int %res
+ }
+ 
+ fastcc int %check_tail(int %x, int* %f, int %g) {
+         %tmp1 = setgt int %x, 0
+         br bool %tmp1, label %if-then, label %if-else
+ 
+ if-then:
+         %fun_ptr = cast int* %f to int(int, int*, int)* 
+         %arg1    = add int %x, -1
+         call int %putchar(int 90)       
+         %res = tail call fastcc int %fun_ptr( int %arg1, int * %f, int %g)
+         ret int %res
+ 
+ if-else:
+         ret int %x
+ }
+ 





From lattner at cs.uiuc.edu  Sun Dec  4 00:04:02 2005
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Sun, 4 Dec 2005 00:04:02 -0600
Subject: [llvm-commits] CVS: llvm/lib/Target/X86/X86ISelPattern.cpp 
Message-ID: <200512040604.AAA11239@zion.cs.uiuc.edu>



Changes in directory llvm/lib/Target/X86:

X86ISelPattern.cpp updated: 1.187 -> 1.188
---
Log message:

Fix PR672: http://llvm.cs.uiuc.edu/PR672  another way which should be more robust


---
Diffs of the changes:  (+14 -16)

 X86ISelPattern.cpp |   30 ++++++++++++++----------------
 1 files changed, 14 insertions(+), 16 deletions(-)


Index: llvm/lib/Target/X86/X86ISelPattern.cpp
diff -u llvm/lib/Target/X86/X86ISelPattern.cpp:1.187 llvm/lib/Target/X86/X86ISelPattern.cpp:1.188
--- llvm/lib/Target/X86/X86ISelPattern.cpp:1.187	Sat Dec  3 01:15:55 2005
+++ llvm/lib/Target/X86/X86ISelPattern.cpp	Sun Dec  4 00:03:50 2005
@@ -3014,7 +3014,10 @@
   bool isDirect = isa<GlobalAddressSDNode>(Callee) ||
                   isa<ExternalSymbolSDNode>(Callee);
   unsigned CalleeReg = 0;
-  if (!isDirect) CalleeReg = SelectExpr(Callee);
+  if (!isDirect) {
+    // If this is not a direct tail call, evaluate the callee's address.
+    CalleeReg = SelectExpr(Callee);
+  }
 
   unsigned RegOp1 = 0;
   unsigned RegOp2 = 0;
@@ -3059,6 +3062,15 @@
         break;
       }
   }
+  
+  // If this is not a direct tail call, put the callee's address into ECX.
+  // The address has to be evaluated into a non-callee save register that is
+  // not used for arguments.  This means either ECX, as EAX and EDX may be
+  // used for argument passing.  We do this here to make sure that the
+  // expressions for arguments and callee are all evaluated before the copies
+  // into physical registers.
+  if (!isDirect)
+    BuildMI(BB, X86::MOV32rr, 1, X86::ECX).addReg(CalleeReg);
 
   // Adjust ESP.
   if (ESPOffset)
@@ -3067,21 +3079,7 @@
 
   // TODO: handle jmp [mem]
   if (!isDirect) {
-    // We do not want the register allocator to allocate CalleeReg to a callee 
-    // saved register, as these will be restored before the JMP.  To prevent
-    // this, emit explicit clobbers of callee saved regs here.  A better way to
-    // solve this would be to specify that the register constraints of TAILJMPr
-    // only allow registers that are not callee saved, but we currently can't
-    // express that.  This forces all four of these regs to be saved and 
-    // reloaded for all functions with an indirect tail call.
-    // TODO: Improve this!
-    BuildMI(BB, X86::IMPLICIT_DEF, 4)
-       .addReg(X86::ESI, MachineOperand::Def)
-       .addReg(X86::EDI, MachineOperand::Def)
-       .addReg(X86::EBX, MachineOperand::Def)
-       .addReg(X86::EBP, MachineOperand::Def);
-    
-    BuildMI(BB, X86::TAILJMPr, 1).addReg(CalleeReg);
+    BuildMI(BB, X86::TAILJMPr, 1).addReg(X86::ECX);
   } else if (GlobalAddressSDNode *GASD = dyn_cast<GlobalAddressSDNode>(Callee)){
     BuildMI(BB, X86::TAILJMPd, 1).addGlobalAddress(GASD->getGlobal(), true);
   } else {





From evan.cheng at apple.com  Sun Dec  4 02:13:28 2005
From: evan.cheng at apple.com (Evan Cheng)
Date: Sun, 4 Dec 2005 02:13:28 -0600
Subject: [llvm-commits] CVS: llvm/lib/Target/Target.td TargetSelectionDAG.td
Message-ID: <200512040813.CAA14374@zion.cs.uiuc.edu>



Changes in directory llvm/lib/Target:

Target.td updated: 1.63 -> 1.64
TargetSelectionDAG.td updated: 1.10 -> 1.11
---
Log message:

* Added instruction property hasCtrlDep for those which r/w control-flow
  chains.
* Added DAG node property SDNPHasChain for nodes which r/w control-flow
  chains.
* Renamed SDTVT to SDTOther.
* Added several new SDTypeProfiles for BR, BRCOND, RET, and WRITEPORT.
* Added SDNode definitions for BR, BRCOND, RET, and WRITEPORT.


---
Diffs of the changes:  (+27 -3)

 Target.td             |    1 +
 TargetSelectionDAG.td |   29 ++++++++++++++++++++++++++---
 2 files changed, 27 insertions(+), 3 deletions(-)


Index: llvm/lib/Target/Target.td
diff -u llvm/lib/Target/Target.td:1.63 llvm/lib/Target/Target.td:1.64
--- llvm/lib/Target/Target.td:1.63	Wed Nov 30 22:51:06 2005
+++ llvm/lib/Target/Target.td	Sun Dec  4 02:13:17 2005
@@ -163,6 +163,7 @@
   bit isTerminator = 0;     // Is this part of the terminator for a basic block?
   bit hasDelaySlot = 0;     // Does this instruction have an delay slot?
   bit usesCustomDAGSchedInserter = 0; // Pseudo instr needing special help.
+  bit hasCtrlDep   = 0;     // Does this instruction r/w ctrl-flow chains?
   
   InstrItinClass Itinerary; // Execution steps used for scheduling. 
 }


Index: llvm/lib/Target/TargetSelectionDAG.td
diff -u llvm/lib/Target/TargetSelectionDAG.td:1.10 llvm/lib/Target/TargetSelectionDAG.td:1.11
--- llvm/lib/Target/TargetSelectionDAG.td:1.10	Thu Nov 17 01:20:15 2005
+++ llvm/lib/Target/TargetSelectionDAG.td	Sun Dec  4 02:13:17 2005
@@ -68,7 +68,7 @@
 
 // Builtin profiles.
 def SDTImm    : SDTypeProfile<1, 0, [SDTCisInt<0>]>;      // for 'imm'.
-def SDTVT     : SDTypeProfile<1, 0, [SDTCisVT<0, OtherVT>]>; // for 'vt'.
+def SDTOther  : SDTypeProfile<1, 0, [SDTCisVT<0, OtherVT>]>; // for 'vt'.
 def SDTUNDEF  : SDTypeProfile<1, 0, []>; // for 'undef'.
 def SDTIntBinOp : SDTypeProfile<1, 2, [   // add, and, or, xor, udiv, etc.
   SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisInt<0>
@@ -113,6 +113,21 @@
   SDTCisInt<1>, SDTCisSameAs<0, 2>, SDTCisSameAs<2, 3>
 ]>;
 
+def SDTBr : SDTypeProfile<0, 1, [ // br
+  SDTCisVT<0, OtherVT>
+]>;
+
+def SDTBrCond : SDTypeProfile<0, 2, [ // brcond
+  SDTCisInt<0>, SDTCisVT<1, OtherVT>
+]>;
+
+def SDTRet : SDTypeProfile<0, 0, [ // ret
+]>;
+
+def SDTWritePort : SDTypeProfile<0, 2, [ // writeport
+  SDTCisInt<0>, SDTCisInt<1>
+]>;
+
 //===----------------------------------------------------------------------===//
 // Selection DAG Node Properties.
 //
@@ -121,6 +136,7 @@
 class SDNodeProperty;
 def SDNPCommutative : SDNodeProperty;   // X op Y == Y op X
 def SDNPAssociative : SDNodeProperty;   // (X op Y) op Z == X op (Y op Z)
+def SDNPHasChain    : SDNodeProperty;   // R/W chain operand and result
 
 //===----------------------------------------------------------------------===//
 // Selection DAG Node definitions.
@@ -137,8 +153,9 @@
 def node;
 
 def imm        : SDNode<"ISD::Constant"  , SDTImm     , [], "ConstantSDNode">;
-def vt         : SDNode<"ISD::VALUETYPE" , SDTVT      , [], "VTSDNode">;
-def cond       : SDNode<"ISD::CONDCODE"  , SDTVT      , [], "CondCodeSDNode">;
+def vt         : SDNode<"ISD::VALUETYPE" , SDTOther   , [], "VTSDNode">;
+def bb         : SDNode<"ISD::BasicBlock", SDTOther   , [], "BasicBlockSDNode">;
+def cond       : SDNode<"ISD::CONDCODE"  , SDTOther   , [], "CondCodeSDNode">;
 def undef      : SDNode<"ISD::UNDEF"     , SDTUNDEF   , []>;
 def globaladdr : SDNode<"ISD::GlobalAddress", SDTImm, [],
                         "GlobalAddressSDNode">;
@@ -194,6 +211,12 @@
 def setcc      : SDNode<"ISD::SETCC"      , SDTSetCC>;
 def select     : SDNode<"ISD::SELECT"     , SDTSelect>;
 
+def br         : SDNode<"ISD::BR"         , SDTBr,     [SDNPHasChain]>;
+def brcond     : SDNode<"ISD::BRCOND"     , SDTBrCond, [SDNPHasChain]>;
+def ret        : SDNode<"ISD::RET"        , SDTRet,    [SDNPHasChain]>;
+
+def writeport  : SDNode<"ISD::WRITEPORT"  , SDTWritePort, [SDNPHasChain]>;
+
 //===----------------------------------------------------------------------===//
 // Selection DAG Condition Codes
 





From evan.cheng at apple.com  Sun Dec  4 02:18:28 2005
From: evan.cheng at apple.com (Evan Cheng)
Date: Sun, 4 Dec 2005 02:18:28 -0600
Subject: [llvm-commits] CVS: llvm/utils/TableGen/CodeGenInstruction.h
	CodeGenTarget.cpp DAGISelEmitter.cpp DAGISelEmitter.h 
Message-ID: <200512040818.CAA16425@zion.cs.uiuc.edu>



Changes in directory llvm/utils/TableGen:

CodeGenInstruction.h updated: 1.15 -> 1.16
CodeGenTarget.cpp updated: 1.46 -> 1.47
DAGISelEmitter.cpp updated: 1.81 -> 1.82
DAGISelEmitter.h updated: 1.38 -> 1.39
---
Log message:

* Commit the fix (by Chris) for a tblgen type inferencing bug.
* Enhanced tblgen to handle instructions which have chain operand and writes a
chain result.
* Enhanced tblgen to handle instructions which produces no results. Part of
the change is a temporary hack which relies on instruction property (e.g.
isReturn, isBranch). The proper fix would be to change the .td syntax to
separate results dag from ops dag.


---
Diffs of the changes:  (+198 -71)

 CodeGenInstruction.h |    1 
 CodeGenTarget.cpp    |    1 
 DAGISelEmitter.cpp   |  257 +++++++++++++++++++++++++++++++++++++--------------
 DAGISelEmitter.h     |   10 -
 4 files changed, 198 insertions(+), 71 deletions(-)


Index: llvm/utils/TableGen/CodeGenInstruction.h
diff -u llvm/utils/TableGen/CodeGenInstruction.h:1.15 llvm/utils/TableGen/CodeGenInstruction.h:1.16
--- llvm/utils/TableGen/CodeGenInstruction.h:1.15	Wed Nov 30 18:12:04 2005
+++ llvm/utils/TableGen/CodeGenInstruction.h	Sun Dec  4 02:18:16 2005
@@ -84,6 +84,7 @@
     bool hasDelaySlot;
     bool usesCustomDAGSchedInserter;
     bool hasVariableNumberOfOperands;
+    bool hasCtrlDep;
 
     CodeGenInstruction(Record *R, const std::string &AsmStr);
 


Index: llvm/utils/TableGen/CodeGenTarget.cpp
diff -u llvm/utils/TableGen/CodeGenTarget.cpp:1.46 llvm/utils/TableGen/CodeGenTarget.cpp:1.47
--- llvm/utils/TableGen/CodeGenTarget.cpp:1.46	Wed Nov 30 22:51:06 2005
+++ llvm/utils/TableGen/CodeGenTarget.cpp	Sun Dec  4 02:18:16 2005
@@ -268,6 +268,7 @@
   isTerminator = R->getValueAsBit("isTerminator");
   hasDelaySlot = R->getValueAsBit("hasDelaySlot");
   usesCustomDAGSchedInserter = R->getValueAsBit("usesCustomDAGSchedInserter");
+  hasCtrlDep   = R->getValueAsBit("hasCtrlDep");
   hasVariableNumberOfOperands = false;
   
   DagInit *DI;


Index: llvm/utils/TableGen/DAGISelEmitter.cpp
diff -u llvm/utils/TableGen/DAGISelEmitter.cpp:1.81 llvm/utils/TableGen/DAGISelEmitter.cpp:1.82
--- llvm/utils/TableGen/DAGISelEmitter.cpp:1.81	Wed Nov 30 22:51:06 2005
+++ llvm/utils/TableGen/DAGISelEmitter.cpp	Sun Dec  4 02:18:16 2005
@@ -84,7 +84,8 @@
 TreePatternNode *SDTypeConstraint::getOperandNum(unsigned OpNo,
                                                  TreePatternNode *N,
                                                  unsigned NumResults) const {
-  assert(NumResults == 1 && "We only work with single result nodes so far!");
+  assert(NumResults <= 1 &&
+         "We only work with nodes with zero or one result so far!");
   
   if (OpNo < NumResults)
     return N;  // FIXME: need value #
@@ -100,7 +101,8 @@
                                            const SDNodeInfo &NodeInfo,
                                            TreePattern &TP) const {
   unsigned NumResults = NodeInfo.getNumResults();
-  assert(NumResults == 1 && "We only work with single result nodes so far!");
+  assert(NumResults <= 1 &&
+         "We only work with nodes with zero or one result so far!");
   
   // Check that the number of operands is sane.
   if (NodeInfo.getNumOperands() >= 0) {
@@ -234,6 +236,8 @@
       Properties |= 1 << SDNPCommutative;
     } else if (PropList[i]->getName() == "SDNPAssociative") {
       Properties |= 1 << SDNPAssociative;
+    } else if (PropList[i]->getName() == "SDNPHasChain") {
+      Properties |= 1 << SDNPHasChain;
     } else {
       std::cerr << "Unknown SD Node property '" << PropList[i]->getName()
                 << "' on node '" << R->getName() << "'!\n";
@@ -440,6 +444,7 @@
   }
   
   FragTree->setName(getName());
+  FragTree->UpdateNodeType(getExtType(), TP);
   
   // Get a new copy of this fragment to stitch into here.
   //delete this;    // FIXME: implement refcounting!
@@ -526,22 +531,33 @@
     bool MadeChange = NI.ApplyTypeConstraints(this, TP);
     for (unsigned i = 0, e = getNumChildren(); i != e; ++i)
       MadeChange |= getChild(i)->ApplyTypeConstraints(TP, NotRegisters);
+    // Branch, etc. do not produce results and top-level forms in instr pattern
+    // must have void types.
+    if (NI.getNumResults() == 0)
+      MadeChange |= UpdateNodeType(MVT::isVoid, TP);
     return MadeChange;  
   } else if (getOperator()->isSubClassOf("Instruction")) {
     const DAGInstruction &Inst =
       TP.getDAGISelEmitter().getInstruction(getOperator());
+    bool MadeChange = false;
+    unsigned NumResults = Inst.getNumResults();
     
-    assert(Inst.getNumResults() == 1 && "Only supports one result instrs!");
+    assert(NumResults <= 1 &&
+           "Only supports zero or one result instrs!");
     // Apply the result type to the node
-    Record *ResultNode = Inst.getResult(0);
-    assert(ResultNode->isSubClassOf("RegisterClass") &&
-           "Operands should be register classes!");
+    if (NumResults == 0) {
+      MadeChange = UpdateNodeType(MVT::isVoid, TP);
+    } else {
+      Record *ResultNode = Inst.getResult(0);
+      assert(ResultNode->isSubClassOf("RegisterClass") &&
+             "Operands should be register classes!");
 
-    const CodeGenRegisterClass &RC = 
-      TP.getDAGISelEmitter().getTargetInfo().getRegisterClass(ResultNode);
+      const CodeGenRegisterClass &RC = 
+        TP.getDAGISelEmitter().getTargetInfo().getRegisterClass(ResultNode);
 
-    // Get the first ValueType in the RegClass, it's as good as any.
-    bool MadeChange = UpdateNodeType(RC.getValueTypeNum(0), TP);
+      // Get the first ValueType in the RegClass, it's as good as any.
+      MadeChange = UpdateNodeType(RC.getValueTypeNum(0), TP);
+    }
 
     if (getNumChildren() != Inst.getNumOperands())
       TP.error("Instruction '" + getOperator()->getName() + " expects " +
@@ -655,8 +671,7 @@
         Dag->setArg(0, new DagInit(R,
                                 std::vector<std::pair<Init*, std::string> >()));
         return ParseTreePattern(Dag);
-      }   
-      
+      }
       New = new TreePatternNode(DI);
     } else if (DagInit *DI = dynamic_cast<DagInit*>(Arg)) {
       New = ParseTreePattern(DI);
@@ -1052,13 +1067,21 @@
       // Doesn't even define a result?
       if (InstInfo.OperandList.size() == 0)
         continue;
+
+      // FIXME: temporary hack...
+      if (InstInfo.isReturn || InstInfo.isBranch || InstInfo.isCall ||
+          InstInfo.isStore) {
+        // These produce no results
+        for (unsigned j = 0, e = InstInfo.OperandList.size(); j != e; ++j)
+          Operands.push_back(InstInfo.OperandList[j].Rec);
+      } else {
+        // Assume the first operand is the result.
+        Results.push_back(InstInfo.OperandList[0].Rec);
       
-      // Assume the first operand is the result.
-      Results.push_back(InstInfo.OperandList[0].Rec);
-      
-      // The rest are inputs.
-      for (unsigned j = 1, e = InstInfo.OperandList.size(); j != e; ++j)
-        Operands.push_back(InstInfo.OperandList[j].Rec);
+        // The rest are inputs.
+        for (unsigned j = 1, e = InstInfo.OperandList.size(); j != e; ++j)
+          Operands.push_back(InstInfo.OperandList[j].Rec);
+      }
       
       // Create and insert the instruction.
       Instructions.insert(std::make_pair(Instrs[i], 
@@ -1088,11 +1111,9 @@
     // fill in the InstResults map.
     for (unsigned j = 0, e = I->getNumTrees(); j != e; ++j) {
       TreePatternNode *Pat = I->getTree(j);
-      if (Pat->getExtType() != MVT::isVoid) {
-        I->dump();
+      if (Pat->getExtType() != MVT::isVoid)
         I->error("Top-level forms in instruction pattern should have"
                  " void types");
-      }
 
       // Find inputs and outputs, and verify the structure of the uses/defs.
       FindPatternInputsAndOutputs(I, Pat, InstInputs, InstResults);
@@ -1201,7 +1222,8 @@
   // If we can, convert the instructions to be patterns that are matched!
   for (std::map<Record*, DAGInstruction>::iterator II = Instructions.begin(),
        E = Instructions.end(); II != E; ++II) {
-    TreePattern *I = II->second.getPattern();
+    DAGInstruction &TheInst = II->second;
+    TreePattern *I = TheInst.getPattern();
     if (I == 0) continue;  // No pattern.
     
     if (I->getNumTrees() != 1) {
@@ -1209,19 +1231,24 @@
       continue;
     }
     TreePatternNode *Pattern = I->getTree(0);
-    if (Pattern->getOperator()->getName() != "set")
-      continue;  // Not a set (store or something?)
-    
-    if (Pattern->getNumChildren() != 2)
-      continue;  // Not a set of a single value (not handled so far)
+    TreePatternNode *SrcPattern;
+    if (TheInst.getNumResults() == 0) {
+      SrcPattern = Pattern;
+    } else {
+      if (Pattern->getOperator()->getName() != "set")
+        continue;  // Not a set (store or something?)
     
-    TreePatternNode *SrcPattern = Pattern->getChild(1)->clone();
+      if (Pattern->getNumChildren() != 2)
+        continue;  // Not a set of a single value (not handled so far)
+
+      SrcPattern = Pattern->getChild(1)->clone();    
+    }
     
     std::string Reason;
     if (!SrcPattern->canPatternMatch(Reason, *this))
       I->error("Instruction can never match: " + Reason);
     
-    TreePatternNode *DstPattern = II->second.getResultPattern();
+    TreePatternNode *DstPattern = TheInst.getResultPattern();
     PatternsToMatch.push_back(std::make_pair(SrcPattern, DstPattern));
   }
 }
@@ -1527,8 +1554,8 @@
 /// pattern.
 static unsigned getPatternSize(TreePatternNode *P) {
   assert(isExtIntegerVT(P->getExtType()) || 
-         isExtFloatingPointVT(P->getExtType()) &&
-         "Not a valid pattern node to size!");
+         isExtFloatingPointVT(P->getExtType()) ||
+         P->getExtType() == MVT::isVoid && "Not a valid pattern node to size!");
   unsigned Size = 1;  // The node itself.
   
   // Count children in the count if they are also nodes.
@@ -1572,13 +1599,24 @@
   }
 };
 
+/// nodeHasChain - return true if TreePatternNode has the property
+/// 'hasChain', meaning it reads a ctrl-flow chain operand and writes
+/// a chain result.
+static bool nodeHasChain(TreePatternNode *N, DAGISelEmitter &ISE)
+{
+  if (N->isLeaf()) return false;
+
+  const SDNodeInfo &NodeInfo = ISE.getSDNodeInfo(N->getOperator());
+  return NodeInfo.hasProperty(SDNodeInfo::SDNPHasChain);
+}
+
 /// EmitMatchForPattern - Emit a matcher for N, going to the label for PatternNo
 /// if the match fails.  At this point, we already know that the opcode for N
 /// matches, and the SDNode for the result has the RootName specified name.
 void DAGISelEmitter::EmitMatchForPattern(TreePatternNode *N,
                                          const std::string &RootName,
                                          std::map<std::string,std::string> &VarMap,
-                                         unsigned PatternNo, std::ostream &OS) {
+                                         unsigned PatternNo,std::ostream &OS) {
   if (N->isLeaf()) {
     if (IntInit *II = dynamic_cast<IntInit*>(N->getLeafValue())) {
       OS << "      if (cast<ConstantSDNode>(" << RootName
@@ -1606,32 +1644,35 @@
       return;
     }
   }
-  
+
+
   // Emit code to load the child nodes and match their contents recursively.
-  for (unsigned i = 0, e = N->getNumChildren(); i != e; ++i) {
-    OS << "      SDOperand " << RootName << i <<" = " << RootName
-       << ".getOperand(" << i << ");\n";
+  unsigned OpNo = (unsigned) nodeHasChain(N, *this);
+  for (unsigned i = 0, e = N->getNumChildren(); i != e; ++i, ++OpNo) {
+    OS << "      SDOperand " << RootName << OpNo <<" = " << RootName
+       << ".getOperand(" << OpNo << ");\n";
     TreePatternNode *Child = N->getChild(i);
     
     if (!Child->isLeaf()) {
       // If it's not a leaf, recursively match.
       const SDNodeInfo &CInfo = getSDNodeInfo(Child->getOperator());
-      OS << "      if (" << RootName << i << ".getOpcode() != "
+      OS << "      if (" << RootName << OpNo << ".getOpcode() != "
          << CInfo.getEnumName() << ") goto P" << PatternNo << "Fail;\n";
-      EmitMatchForPattern(Child, RootName + utostr(i), VarMap, PatternNo, OS);
+      EmitMatchForPattern(Child, RootName + utostr(OpNo), VarMap, PatternNo,
+                          OS);
     } else {
       // If this child has a name associated with it, capture it in VarMap.  If
       // we already saw this in the pattern, emit code to verify dagness.
       if (!Child->getName().empty()) {
         std::string &VarMapEntry = VarMap[Child->getName()];
         if (VarMapEntry.empty()) {
-          VarMapEntry = RootName + utostr(i);
+          VarMapEntry = RootName + utostr(OpNo);
         } else {
           // If we get here, this is a second reference to a specific name.  Since
           // we already have checked that the first reference is valid, we don't
           // have to recursively match it, just check that it's the same as the
           // previously named thing.
-          OS << "      if (" << VarMapEntry << " != " << RootName << i
+          OS << "      if (" << VarMapEntry << " != " << RootName << OpNo
           << ") goto P" << PatternNo << "Fail;\n";
           continue;
         }
@@ -1645,12 +1686,12 @@
           // Handle register references.  Nothing to do here.
         } else if (LeafRec->isSubClassOf("ValueType")) {
           // Make sure this is the specified value type.
-          OS << "      if (cast<VTSDNode>(" << RootName << i << ")->getVT() != "
+          OS << "      if (cast<VTSDNode>(" << RootName << OpNo << ")->getVT() != "
           << "MVT::" << LeafRec->getName() << ") goto P" << PatternNo
           << "Fail;\n";
         } else if (LeafRec->isSubClassOf("CondCode")) {
           // Make sure this is the specified cond code.
-          OS << "      if (cast<CondCodeSDNode>(" << RootName << i
+          OS << "      if (cast<CondCodeSDNode>(" << RootName << OpNo
              << ")->get() != " << "ISD::" << LeafRec->getName()
              << ") goto P" << PatternNo << "Fail;\n";
         } else {
@@ -1658,8 +1699,8 @@
           assert(0 && "Unknown leaf type!");
         }
       } else if (IntInit *II = dynamic_cast<IntInit*>(Child->getLeafValue())) {
-        OS << "      if (!isa<ConstantSDNode>(" << RootName << i << ") ||\n"
-           << "          cast<ConstantSDNode>(" << RootName << i
+        OS << "      if (!isa<ConstantSDNode>(" << RootName << OpNo << ") ||\n"
+           << "          cast<ConstantSDNode>(" << RootName << OpNo
            << ")->getSignExtended() != " << II->getValue() << ")\n"
            << "        goto P" << PatternNo << "Fail;\n";
       } else {
@@ -1668,7 +1709,7 @@
       }
     }
   }
-  
+
   // If there is a node predicate for this, emit the call.
   if (!N->getPredicateFn().empty())
     OS << "      if (!" << N->getPredicateFn() << "(" << RootName
@@ -1694,30 +1735,69 @@
 }
 
 
+/// EmitLeadChainForPattern - Emit the flag operands for the DAG that will be
+/// built in CodeGenPatternResult.
+void DAGISelEmitter::EmitLeadChainForPattern(TreePatternNode *N,
+                                             const std::string &RootName,
+                                             std::ostream &OS,
+                                             bool &HasChain) {
+  if (!N->isLeaf()) {
+    Record *Op = N->getOperator();
+    if (Op->isSubClassOf("Instruction")) {
+      bool HasCtrlDep = Op->getValueAsBit("hasCtrlDep");
+      unsigned OpNo = (unsigned) HasCtrlDep;
+      for (unsigned i = 0, e = N->getNumChildren(); i != e; ++i)
+        EmitLeadChainForPattern(N->getChild(i), RootName + utostr(OpNo),
+                                 OS, HasChain);
+
+      if (!HasChain && HasCtrlDep) {
+        OS << "      SDOperand Chain = Select("
+           << RootName << ".getOperand(0));\n";
+        HasChain = true;
+      }
+    }
+  }
+}
+
 /// EmitCopyToRegsForPattern - Emit the flag operands for the DAG that will be
 /// built in CodeGenPatternResult.
 void DAGISelEmitter::EmitCopyToRegsForPattern(TreePatternNode *N,
                                               const std::string &RootName,
-                                              std::ostream &OS, bool &InFlag) {
+                                              std::ostream &OS,
+                                              bool &HasChain, bool &InFlag) {
   const CodeGenTarget &T = getTargetInfo();
-  for (unsigned i = 0, e = N->getNumChildren(); i != e; ++i) {
+  unsigned OpNo = (unsigned) nodeHasChain(N, *this);
+  for (unsigned i = 0, e = N->getNumChildren(); i != e; ++i, ++OpNo) {
     TreePatternNode *Child = N->getChild(i);
     if (!Child->isLeaf()) {
-      EmitCopyToRegsForPattern(Child, RootName + utostr(i), OS, InFlag);
+      EmitCopyToRegsForPattern(Child, RootName + utostr(OpNo), OS, HasChain,
+                               InFlag);
     } else {
       if (DefInit *DI = dynamic_cast<DefInit*>(Child->getLeafValue())) {
         Record *RR = DI->getDef();
         if (RR->isSubClassOf("Register")) {
           MVT::ValueType RVT = getRegisterValueType(RR, T);
           if (!InFlag) {
-            OS << "      SDOperand InFlag;  // Null incoming flag value.\n";
+            OS << "      SDOperand InFlag;\n";
             InFlag = true;
           }
-          OS << "      InFlag = CurDAG->getCopyToReg(CurDAG->getEntryNode()"
-             << ", CurDAG->getRegister(" << getQualifiedName(RR)
-             << ", MVT::" << getEnumName(RVT) << ")"
-             << ", " << RootName << i << ", InFlag).getValue(1);\n";
-
+          if (HasChain) {
+            OS << "      SDOperand " << RootName << "CR" << i << ";\n";
+            OS << "      " << RootName << "CR" << i
+               << "  = CurDAG->getCopyToReg(Chain, CurDAG->getRegister("
+               << getQualifiedName(RR) << ", MVT::" << getEnumName(RVT) << ")"
+               << ", Select(" << RootName << OpNo << "), InFlag);\n";
+            OS << "      Chain  = " << RootName << "CR" << i
+               << ".getValue(0);\n";
+            OS << "      InFlag = " << RootName << "CR" << i
+               << ".getValue(1);\n";
+          } else {
+            OS << "      InFlag = CurDAG->getCopyToReg(CurDAG->getEntryNode()"
+               << ", CurDAG->getRegister(" << getQualifiedName(RR)
+               << ", MVT::" << getEnumName(RVT) << ")"
+               << ", Select(" << RootName << OpNo
+               << "), InFlag).getValue(1);\n";
+          }
         }
       }
     }
@@ -1729,7 +1809,8 @@
 unsigned DAGISelEmitter::
 CodeGenPatternResult(TreePatternNode *N, unsigned &Ctr,
                      std::map<std::string,std::string> &VariableMap, 
-                     std::ostream &OS, bool InFlag, bool isRoot) {
+                     std::ostream &OS, bool &HasChain, bool InFlag,
+                     bool isRoot) {
   // This is something selected from the pattern we matched.
   if (!N->getName().empty()) {
     assert(!isRoot && "Root of pattern cannot be a leaf!");
@@ -1792,22 +1873,61 @@
 
   Record *Op = N->getOperator();
   if (Op->isSubClassOf("Instruction")) {
+    bool HasCtrlDep = Op->getValueAsBit("hasCtrlDep");
+
     // Emit all of the operands.
     std::vector<unsigned> Ops;
     for (unsigned i = 0, e = N->getNumChildren(); i != e; ++i)
-      Ops.push_back(CodeGenPatternResult(N->getChild(i),
-                                         Ctr, VariableMap, OS, InFlag));
+      Ops.push_back(CodeGenPatternResult(N->getChild(i), Ctr,
+                                         VariableMap, OS, HasChain, InFlag));
 
     CodeGenInstruction &II = Target.getInstruction(Op->getName());
     unsigned ResNo = Ctr++;
+
+    const DAGInstruction &Inst = getInstruction(Op);
+    unsigned NumResults = Inst.getNumResults();
     
     if (!isRoot) {
       OS << "      SDOperand Tmp" << ResNo << " = CurDAG->getTargetNode("
          << II.Namespace << "::" << II.TheDef->getName() << ", MVT::"
          << getEnumName(N->getType());
+      unsigned LastOp = 0;
+      for (unsigned i = 0, e = Ops.size(); i != e; ++i) {
+        LastOp = Ops[i];
+        OS << ", Tmp" << LastOp;
+      }
+      OS << ");\n";
+      if (HasCtrlDep) {
+        // Must have at least one result
+        OS << "      Chain = Tmp" << LastOp << ".getValue("
+           << NumResults << ");\n";
+      }
+    } else if (HasCtrlDep) {
+      if (NumResults > 0) 
+        OS << "      SDOperand Result = ";
+      else
+        OS << "      Chain = CodeGenMap[N] = ";
+      OS << "CurDAG->getTargetNode("
+         << II.Namespace << "::" << II.TheDef->getName();
+      if (NumResults > 0) 
+        OS << ", MVT::" << getEnumName(N->getType()); // TODO: multiple results?
+      OS << ", MVT::Other";
       for (unsigned i = 0, e = Ops.size(); i != e; ++i)
         OS << ", Tmp" << Ops[i];
+      OS << ", Chain";
+      if (InFlag)
+        OS << ", InFlag";
       OS << ");\n";
+      if (NumResults > 0) {
+        OS << "      CodeGenMap[N.getValue(0)] = Result;\n";
+        OS << "      CodeGenMap[N.getValue(" << NumResults
+           << ")] = Result.getValue(" << NumResults << ");\n";
+        OS << "      Chain = CodeGenMap[N].getValue(" << NumResults << ");\n";
+      }
+      if (NumResults == 0)
+        OS << "      return Chain;\n";
+      else
+        OS << "      return (N.ResNo) ? Chain : CodeGenMap[N];\n";
     } else {
       // If this instruction is the root, and if there is only one use of it,
       // use SelectNodeTo instead of getTargetNode to avoid an allocation.
@@ -1822,8 +1942,8 @@
       OS << ");\n";
       OS << "      } else {\n";
       OS << "        return CodeGenMap[N] = CurDAG->getTargetNode("
-      << II.Namespace << "::" << II.TheDef->getName() << ", MVT::"
-      << getEnumName(N->getType());
+         << II.Namespace << "::" << II.TheDef->getName() << ", MVT::"
+         << getEnumName(N->getType());
       for (unsigned i = 0, e = Ops.size(); i != e; ++i)
         OS << ", Tmp" << Ops[i];
       if (InFlag)
@@ -1834,8 +1954,8 @@
     return ResNo;
   } else if (Op->isSubClassOf("SDNodeXForm")) {
     assert(N->getNumChildren() == 1 && "node xform should have one child!");
-    unsigned OpVal = CodeGenPatternResult(N->getChild(0),
-                                          Ctr, VariableMap, OS, InFlag);
+    unsigned OpVal = CodeGenPatternResult(N->getChild(0), Ctr,
+                                          VariableMap, OS, HasChain, InFlag);
     
     unsigned ResNo = Ctr++;
     OS << "      SDOperand Tmp" << ResNo << " = Transform_" << Op->getName()
@@ -1866,6 +1986,7 @@
 /// 'Pat' may be missing types.  If we find an unresolved type to add a check
 /// for, this returns true otherwise false if Pat has all types.
 static bool InsertOneTypeCheck(TreePatternNode *Pat, TreePatternNode *Other,
+                               DAGISelEmitter &ISE,
                                const std::string &Prefix, unsigned PatternNo,
                                std::ostream &OS) {
   // Did we find one?
@@ -1879,9 +2000,10 @@
     return false;
   }
   
-  for (unsigned i = 0, e = Pat->getNumChildren(); i != e; ++i)
+  unsigned OpNo = (unsigned) nodeHasChain(Pat, ISE);
+  for (unsigned i = 0, e = Pat->getNumChildren(); i != e; ++i, ++OpNo)
     if (InsertOneTypeCheck(Pat->getChild(i), Other->getChild(i),
-                           Prefix + utostr(i), PatternNo, OS))
+                           ISE, Prefix + utostr(OpNo), PatternNo, OS))
       return true;
   return false;
 }
@@ -1944,14 +2066,17 @@
     // Insert a check for an unresolved type and add it to the tree.  If we find
     // an unresolved type to add a check for, this returns true and we iterate,
     // otherwise we are done.
-  } while (InsertOneTypeCheck(Pat, Pattern.first, "N", PatternNo, OS));
+  } while (InsertOneTypeCheck(Pat, Pattern.first, *this, "N", PatternNo, OS));
+
+  bool HasChain = false;
+  EmitLeadChainForPattern(Pattern.second, "N", OS, HasChain);
 
   bool InFlag = false;
-  EmitCopyToRegsForPattern(Pattern.first, "N", OS, InFlag);
+  EmitCopyToRegsForPattern(Pattern.first, "N", OS, HasChain, InFlag);
   
   unsigned TmpNo = 0;
   CodeGenPatternResult(Pattern.second,
-                       TmpNo, VariableMap, OS, InFlag, true /*the root*/);
+                       TmpNo, VariableMap, OS, HasChain, InFlag, true /*the root*/);
   delete Pat;
   
   OS << "    }\n  P" << PatternNo << "Fail:\n";


Index: llvm/utils/TableGen/DAGISelEmitter.h
diff -u llvm/utils/TableGen/DAGISelEmitter.h:1.38 llvm/utils/TableGen/DAGISelEmitter.h:1.39
--- llvm/utils/TableGen/DAGISelEmitter.h:1.38	Wed Nov 30 18:18:45 2005
+++ llvm/utils/TableGen/DAGISelEmitter.h	Sun Dec  4 02:18:16 2005
@@ -101,7 +101,7 @@
     }
     
     // SelectionDAG node properties.
-    enum SDNP { SDNPCommutative, SDNPAssociative };
+    enum SDNP { SDNPCommutative, SDNPAssociative, SDNPHasChain };
 
     /// hasProperty - Return true if this node has the specified property.
     ///
@@ -324,8 +324,6 @@
 
   class DAGInstruction {
     TreePattern *Pattern;
-    unsigned NumResults;
-    unsigned NumOperands;
     std::vector<Record*> Results;
     std::vector<Record*> Operands;
     TreePatternNode *ResultPattern;
@@ -418,11 +416,13 @@
   void EmitMatchForPattern(TreePatternNode *N, const std::string &RootName,
                            std::map<std::string,std::string> &VarMap,
                            unsigned PatternNo, std::ostream &OS);
+  void EmitLeadChainForPattern(TreePatternNode *N, const std::string &RootName,
+                               std::ostream &OS, bool &HasChain);
   void EmitCopyToRegsForPattern(TreePatternNode *N, const std::string &RootName,
-                                std::ostream &OS, bool &InFlag);
+                                std::ostream &OS, bool &HasChain, bool &InFlag);
   unsigned CodeGenPatternResult(TreePatternNode *N, unsigned &Ctr,
                                 std::map<std::string,std::string> &VariableMap, 
-                                std::ostream &OS, bool InFlag,
+                                std::ostream &OS, bool &HasChain, bool InFlag,
                                 bool isRoot = false);
   void EmitCodeForPattern(PatternToMatch &Pattern, std::ostream &OS);
   void EmitInstructionSelector(std::ostream &OS);





From evan.cheng at apple.com  Sun Dec  4 02:19:54 2005
From: evan.cheng at apple.com (Evan Cheng)
Date: Sun, 4 Dec 2005 02:19:54 -0600
Subject: [llvm-commits] CVS: llvm/lib/Target/X86/X86InstrInfo.td 
Message-ID: <200512040819.CAA17078@zion.cs.uiuc.edu>



Changes in directory llvm/lib/Target/X86:

X86InstrInfo.td updated: 1.145 -> 1.146
---
Log message:

Added isel patterns for RET, JMP, and WRITEPORT.


---
Diffs of the changes:  (+53 -39)

 X86InstrInfo.td |   92 ++++++++++++++++++++++++++++++++------------------------
 1 files changed, 53 insertions(+), 39 deletions(-)


Index: llvm/lib/Target/X86/X86InstrInfo.td
diff -u llvm/lib/Target/X86/X86InstrInfo.td:1.145 llvm/lib/Target/X86/X86InstrInfo.td:1.146
--- llvm/lib/Target/X86/X86InstrInfo.td:1.145	Wed Nov 30 18:43:55 2005
+++ llvm/lib/Target/X86/X86InstrInfo.td	Sun Dec  4 02:19:43 2005
@@ -43,6 +43,9 @@
 let PrintMethod = "printCallOperand" in
   def calltarget : Operand<i32>;
 
+// Branch targets have OtherVT type.
+def brtarget : Operand<OtherVT>;
+
 // Format specifies the encoding used by the instruction.  This is part of the
 // ad-hoc solution used to emit machine instruction encodings by our machine
 // code emitter.
@@ -183,33 +186,33 @@
 //
 
 // Return instructions.
-let isTerminator = 1, isReturn = 1, isBarrier = 1 in
-  def RET : I<0xC3, RawFrm, (ops), "ret", []>;
-let isTerminator = 1, isReturn = 1, isBarrier = 1 in
+let isTerminator = 1, isReturn = 1, isBarrier = 1, hasCtrlDep=1 in
+  def RET : I<0xC3, RawFrm, (ops), "ret", [(ret)]>;
+let isTerminator = 1, isReturn = 1, isBarrier = 1, hasCtrlDep=1 in
   def RETI : Ii16<0xC2, RawFrm, (ops i16imm:$amt), "ret $amt", []>;
 
 // All branches are RawFrm, Void, Branch, and Terminators
-let isBranch = 1, isTerminator = 1 in
-  class IBr<bits<8> opcode, dag ops, string asm> :
-        I<opcode, RawFrm, ops, asm, []>;
+let isBranch = 1, isTerminator = 1, hasCtrlDep = 1 in
+  class IBr<bits<8> opcode, dag ops, string asm, list<dag> pattern> :
+        I<opcode, RawFrm, ops, asm, pattern>;
 
 let isBarrier = 1 in
-  def JMP : IBr<0xE9, (ops i32imm:$dst), "jmp $dst">;
-def JB  : IBr<0x82, (ops i32imm:$dst), "jb $dst">, TB;
-def JAE : IBr<0x83, (ops i32imm:$dst), "jae $dst">, TB;
-def JE  : IBr<0x84, (ops i32imm:$dst), "je $dst">, TB;
-def JNE : IBr<0x85, (ops i32imm:$dst), "jne $dst">, TB;
-def JBE : IBr<0x86, (ops i32imm:$dst), "jbe $dst">, TB;
-def JA  : IBr<0x87, (ops i32imm:$dst), "ja $dst">, TB;
-def JS  : IBr<0x88, (ops i32imm:$dst), "js $dst">, TB;
-def JNS : IBr<0x89, (ops i32imm:$dst), "jns $dst">, TB;
-def JP  : IBr<0x8A, (ops i32imm:$dst), "jp $dst">, TB;
-def JNP : IBr<0x8B, (ops i32imm:$dst), "jnp $dst">, TB;
-def JL  : IBr<0x8C, (ops i32imm:$dst), "jl $dst">, TB;
-def JGE : IBr<0x8D, (ops i32imm:$dst), "jge $dst">, TB;
-def JLE : IBr<0x8E, (ops i32imm:$dst), "jle $dst">, TB;
-def JG  : IBr<0x8F, (ops i32imm:$dst), "jg $dst">, TB;
-
+  def JMP : IBr<0xE9, (ops brtarget:$dst), "jmp $dst", [(br bb:$dst)]>;
+def JB  : IBr<0x82, (ops brtarget:$dst), "jb $dst",
+              []>, TB;
+def JAE : IBr<0x83, (ops brtarget:$dst), "jae $dst", []>, TB;
+def JE  : IBr<0x84, (ops brtarget:$dst), "je $dst", []>, TB;
+def JNE : IBr<0x85, (ops brtarget:$dst), "jne $dst", []>, TB;
+def JBE : IBr<0x86, (ops brtarget:$dst), "jbe $dst", []>, TB;
+def JA  : IBr<0x87, (ops brtarget:$dst), "ja $dst", []>, TB;
+def JS  : IBr<0x88, (ops brtarget:$dst), "js $dst", []>, TB;
+def JNS : IBr<0x89, (ops brtarget:$dst), "jns $dst", []>, TB;
+def JP  : IBr<0x8A, (ops brtarget:$dst), "jp $dst", []>, TB;
+def JNP : IBr<0x8B, (ops brtarget:$dst), "jnp $dst", []>, TB;
+def JL  : IBr<0x8C, (ops brtarget:$dst), "jl $dst", []>, TB;
+def JGE : IBr<0x8D, (ops brtarget:$dst), "jge $dst", []>, TB;
+def JLE : IBr<0x8E, (ops brtarget:$dst), "jle $dst", []>, TB;
+def JG  : IBr<0x8F, (ops brtarget:$dst), "jg $dst", []>, TB;
 
 //===----------------------------------------------------------------------===//
 //  Call Instructions...
@@ -225,7 +228,7 @@
 
 // Tail call stuff.
 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in
-  def TAILJMPd : IBr<0xE9, (ops calltarget:$dst), "jmp $dst  # TAIL CALL">;
+  def TAILJMPd : IBr<0xE9, (ops calltarget:$dst), "jmp $dst  # TAIL CALL", []>;
 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in
   def TAILJMPr : I<0xFF, MRM4r, (ops R32:$dst), "jmp {*}$dst  # TAIL CALL", []>;
 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in
@@ -315,26 +318,37 @@
 def IN32rr : I<0xED, RawFrm, (ops),
                "in{l} {%dx, %eax|%EAX, %DX}", []>, Imp<[DX],[EAX]>;
 
-def IN8ri  : Ii16<0xE4, RawFrm, (ops i16imm:$port),
+def IN8ri  : Ii8<0xE4, RawFrm, (ops i8imm:$port),
                   "in{b} {$port, %al|%AL, $port}", []>,  Imp<[], [AL]>;
-def IN16ri : Ii16<0xE5, RawFrm, (ops i16imm:$port),
+def IN16ri : Ii8<0xE5, RawFrm, (ops i8imm:$port),
                   "in{w} {$port, %ax|%AX, $port}", []>,  Imp<[], [AX]>, OpSize;
-def IN32ri : Ii16<0xE5, RawFrm, (ops i16imm:$port),
+def IN32ri : Ii8<0xE5, RawFrm, (ops i8imm:$port),
                   "in{l} {$port, %eax|%EAX, $port}", []>, Imp<[],[EAX]>;
 
-def OUT8rr  : I<0xEE, RawFrm, (ops),
-                "out{b} {%al, %dx|%DX, %AL}", []>,  Imp<[DX,  AL], []>;
-def OUT16rr : I<0xEF, RawFrm, (ops),
-                "out{w} {%ax, %dx|%DX, %AX}", []>,  Imp<[DX,  AX], []>, OpSize;
-def OUT32rr : I<0xEF, RawFrm, (ops),
-                "out{l} {%eax, %dx|%DX, %EAX}", []>, Imp<[DX, EAX], []>;
-
-def OUT8ir  : Ii16<0xE6, RawFrm, (ops i16imm:$port),
-                   "out{b} {%al, $port|$port, %AL}", []>, Imp<[AL], []>;
-def OUT16ir : Ii16<0xE7, RawFrm, (ops i16imm:$port),
-                   "out{w} {%ax, $port|$port, %AX}", []>, Imp<[AX], []>, OpSize;
-def OUT32ir : Ii16<0xE7, RawFrm, (ops i16imm:$port),
-                   "out{l} {%eax, $port|$port, %EAX}", []>, Imp<[EAX], []>;
+let hasCtrlDep=1 in {
+  def OUT8rr  : I<0xEE, RawFrm, (ops),
+                  "out{b} {%al, %dx|%DX, %AL}",
+                  [(writeport (i8 AL), (i16 DX))]>,  Imp<[DX,  AL], []>;
+  def OUT16rr : I<0xEF, RawFrm, (ops),
+                  "out{w} {%ax, %dx|%DX, %AX}",
+                  [(writeport (i16 AX), (i16 DX))]>,  Imp<[DX,  AX], []>, OpSize;
+  def OUT32rr : I<0xEF, RawFrm, (ops),
+                  "out{l} {%eax, %dx|%DX, %EAX}",
+                  [(writeport (i32 EAX), (i16 DX))]>, Imp<[DX, EAX], []>;
+
+  def OUT8ir  : Ii8<0xE6, RawFrm, (ops i8imm:$port),
+                     "out{b} {%al, $port|$port, %AL}",
+                     [(writeport (i8 AL), (i8 imm:$port))]>,
+                     Imp<[AL], []>;
+  def OUT16ir : Ii8<0xE7, RawFrm, (ops i8imm:$port),
+                     "out{w} {%ax, $port|$port, %AX}",
+                     [(writeport (i16 AX), (i8 imm:$port))]>,
+                     Imp<[AX], []>, OpSize;
+  def OUT32ir : Ii8<0xE7, RawFrm, (ops i8imm:$port),
+                     "out{l} {%eax, $port|$port, %EAX}",
+                     [(writeport (i32 EAX), (i8 imm:$port))]>,
+                     Imp<[EAX], []>;
+}
 
 //===----------------------------------------------------------------------===//
 //  Move Instructions...





From lattner at cs.uiuc.edu  Sun Dec  4 12:43:05 2005
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Sun, 4 Dec 2005 12:43:05 -0600
Subject: [llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCInstrFormats.td
	PPCInstrInfo.td 
Message-ID: <200512041843.MAA29473@zion.cs.uiuc.edu>



Changes in directory llvm/lib/Target/PowerPC:

PPCInstrFormats.td updated: 1.59 -> 1.60
PPCInstrInfo.td updated: 1.147 -> 1.148
---
Log message:

Define BR in the .td file now that Evan made tblgen smarter.


---
Diffs of the changes:  (+10 -5)

 PPCInstrFormats.td |    3 ++-
 PPCInstrInfo.td    |   12 ++++++++----
 2 files changed, 10 insertions(+), 5 deletions(-)


Index: llvm/lib/Target/PowerPC/PPCInstrFormats.td
diff -u llvm/lib/Target/PowerPC/PPCInstrFormats.td:1.59 llvm/lib/Target/PowerPC/PPCInstrFormats.td:1.60
--- llvm/lib/Target/PowerPC/PPCInstrFormats.td:1.59	Tue Nov 29 16:42:50 2005
+++ llvm/lib/Target/PowerPC/PPCInstrFormats.td	Sun Dec  4 12:42:54 2005
@@ -31,8 +31,9 @@
 
 // 1.7.1 I-Form
 class IForm<bits<6> opcode, bit aa, bit lk, dag OL, string asmstr,
-            InstrItinClass itin>
+            InstrItinClass itin, list<dag> pattern>
          : I<opcode, OL, asmstr, itin> {
+  let Pattern = pattern;
   bits<24> LI;
 
   let Inst{6-29}  = LI;


Index: llvm/lib/Target/PowerPC/PPCInstrInfo.td
diff -u llvm/lib/Target/PowerPC/PPCInstrInfo.td:1.147 llvm/lib/Target/PowerPC/PPCInstrInfo.td:1.148
--- llvm/lib/Target/PowerPC/PPCInstrInfo.td:1.147	Tue Nov 29 16:42:50 2005
+++ llvm/lib/Target/PowerPC/PPCInstrInfo.td	Sun Dec  4 12:42:54 2005
@@ -128,7 +128,7 @@
 def s16immX4  : Operand<i32> {   // Multiply imm by 4 before printing.
   let PrintMethod = "printS16X4ImmOperand";
 }
-def target : Operand<i32> {
+def target : Operand<OtherVT> {
   let PrintMethod = "printBranchOperand";
 }
 def calltarget : Operand<i32> {
@@ -194,7 +194,9 @@
   def COND_BRANCH : Pseudo<(ops CRRC:$crS, u16imm:$opc,
                                 target:$true, target:$false),
                            "; COND_BRANCH", []>;
-  def B   : IForm<18, 0, 0, (ops target:$func), "b $func", BrB>;
+  def B   : IForm<18, 0, 0, (ops target:$dst),
+                  "b $dst", BrB,
+                  [(br bb:$dst)]>;
 
   // FIXME: 4*CR# needs to be added to the BI field!
   // This will only work for CR0 as it stands now
@@ -223,8 +225,10 @@
           LR,CTR,
           CR0,CR1,CR5,CR6,CR7] in {
   // Convenient aliases for call instructions
-  def BL  : IForm<18, 0, 1, (ops calltarget:$func, variable_ops), "bl $func", BrB>;
-  def BLA : IForm<18, 1, 1, (ops aaddr:$func, variable_ops), "bla $func", BrB>;
+  def BL  : IForm<18, 0, 1, (ops calltarget:$func, variable_ops), 
+                            "bl $func", BrB, []>;
+  def BLA : IForm<18, 1, 1, (ops aaddr:$func, variable_ops),
+                            "bla $func", BrB, []>;
   def BCTRL : XLForm_2_ext<19, 528, 20, 0, 1, (ops variable_ops), "bctrl", BrB>;
 }
 





From lattner at cs.uiuc.edu  Sun Dec  4 12:48:13 2005
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Sun, 4 Dec 2005 12:48:13 -0600
Subject: [llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCInstrInfo.td
	PPCISelDAGToDAG.cpp 
Message-ID: <200512041848.MAA29567@zion.cs.uiuc.edu>



Changes in directory llvm/lib/Target/PowerPC:

PPCInstrInfo.td updated: 1.148 -> 1.149
PPCISelDAGToDAG.cpp updated: 1.135 -> 1.136
---
Log message:

Finish moving uncond br over to .td file, remove from .cpp file.



---
Diffs of the changes:  (+2 -4)

 PPCISelDAGToDAG.cpp |    4 +---
 PPCInstrInfo.td     |    2 +-
 2 files changed, 2 insertions(+), 4 deletions(-)


Index: llvm/lib/Target/PowerPC/PPCInstrInfo.td
diff -u llvm/lib/Target/PowerPC/PPCInstrInfo.td:1.148 llvm/lib/Target/PowerPC/PPCInstrInfo.td:1.149
--- llvm/lib/Target/PowerPC/PPCInstrInfo.td:1.148	Sun Dec  4 12:42:54 2005
+++ llvm/lib/Target/PowerPC/PPCInstrInfo.td	Sun Dec  4 12:48:01 2005
@@ -190,7 +190,7 @@
 let Defs = [LR] in
   def MovePCtoLR : Pseudo<(ops piclabel:$label), "bl $label", []>;
 
-let isBranch = 1, isTerminator = 1 in {
+let isBranch = 1, isTerminator = 1, hasCtrlDep = 1 in {
   def COND_BRANCH : Pseudo<(ops CRRC:$crS, u16imm:$opc,
                                 target:$true, target:$false),
                            "; COND_BRANCH", []>;


Index: llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
diff -u llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp:1.135 llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp:1.136
--- llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp:1.135	Thu Dec  1 12:09:22 2005
+++ llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp	Sun Dec  4 12:48:01 2005
@@ -873,6 +873,7 @@
   
   switch (N->getOpcode()) {
   default: break;
+  case ISD::BasicBlock:         return CodeGenMap[Op] = Op;
   case ISD::DYNAMIC_STACKALLOC: return SelectDYNAMIC_STACKALLOC(Op);
   case ISD::ADD_PARTS:          return SelectADD_PARTS(Op);
   case ISD::SUB_PARTS:          return SelectSUB_PARTS(Op);
@@ -1219,9 +1220,6 @@
     // Finally, select this to a blr (return) instruction.
     return CurDAG->SelectNodeTo(N, PPC::BLR, MVT::Other, Chain);
   }
-  case ISD::BR:
-    return CurDAG->SelectNodeTo(N, PPC::B, MVT::Other, N->getOperand(1),
-                                Select(N->getOperand(0)));
   case ISD::BR_CC:
   case ISD::BRTWOWAY_CC: {
     SDOperand Chain = Select(N->getOperand(0));





From lattner at cs.uiuc.edu  Sun Dec  4 13:02:11 2005
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Sun, 4 Dec 2005 13:02:11 -0600
Subject: [llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCInstrInfo.td
	PPCISelDAGToDAG.cpp 
Message-ID: <200512041902.NAA30230@zion.cs.uiuc.edu>



Changes in directory llvm/lib/Target/PowerPC:

PPCInstrInfo.td updated: 1.149 -> 1.150
PPCISelDAGToDAG.cpp updated: 1.136 -> 1.137
---
Log message:

Autogen matching code for ADJCALLSTACK[UP|DOWN], thanks to Evan's tblgen
improvements.


---
Diffs of the changes:  (+12 -11)

 PPCISelDAGToDAG.cpp |    8 --------
 PPCInstrInfo.td     |   15 ++++++++++++---
 2 files changed, 12 insertions(+), 11 deletions(-)


Index: llvm/lib/Target/PowerPC/PPCInstrInfo.td
diff -u llvm/lib/Target/PowerPC/PPCInstrInfo.td:1.149 llvm/lib/Target/PowerPC/PPCInstrInfo.td:1.150
--- llvm/lib/Target/PowerPC/PPCInstrInfo.td:1.149	Sun Dec  4 12:48:01 2005
+++ llvm/lib/Target/PowerPC/PPCInstrInfo.td	Sun Dec  4 13:01:59 2005
@@ -30,6 +30,11 @@
 def PPChi     : SDNode<"PPCISD::Hi", SDTIntBinOp, []>;
 def PPClo     : SDNode<"PPCISD::Lo", SDTIntBinOp, []>;
 
+// These are target-independent nodes, but have target-specific formats.
+def SDT_PPCCallSeq : SDTypeProfile<0, 1, [ SDTCisVT<0, i32> ]>;
+def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_PPCCallSeq,[SDNPHasChain]>;
+def callseq_end   : SDNode<"ISD::CALLSEQ_END",   SDT_PPCCallSeq,[SDNPHasChain]>;
+
 //===----------------------------------------------------------------------===//
 // PowerPC specific transformation functions and pattern fragments.
 //
@@ -158,9 +163,13 @@
 // Pseudo-instructions:
 def PHI : Pseudo<(ops variable_ops), "; PHI", []>;
 
-let isLoad = 1 in {
-def ADJCALLSTACKDOWN : Pseudo<(ops u16imm:$amt), "; ADJCALLSTACKDOWN", []>;
-def ADJCALLSTACKUP : Pseudo<(ops u16imm:$amt), "; ADJCALLSTACKUP", []>;
+let isLoad = 1, hasCtrlDep = 1 in {
+def ADJCALLSTACKDOWN : Pseudo<(ops u16imm:$amt),
+                              "; ADJCALLSTACKDOWN",
+                              [(callseq_start imm:$amt)]>;
+def ADJCALLSTACKUP   : Pseudo<(ops u16imm:$amt),
+                              "; ADJCALLSTACKUP",
+                              [(callseq_end imm:$amt)]>;
 }
 def IMPLICIT_DEF_GPR : Pseudo<(ops GPRC:$rD), "; $rD = IMPLICIT_DEF_GPRC",
                               [(set GPRC:$rD, (undef))]>;


Index: llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
diff -u llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp:1.136 llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp:1.137
--- llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp:1.136	Sun Dec  4 12:48:01 2005
+++ llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp	Sun Dec  4 13:01:59 2005
@@ -1190,14 +1190,6 @@
                                 getI32Imm(BROpc));
   }
     
-  case ISD::CALLSEQ_START:
-  case ISD::CALLSEQ_END: {
-    unsigned Amt = cast<ConstantSDNode>(N->getOperand(1))->getValue();
-    unsigned Opc = N->getOpcode() == ISD::CALLSEQ_START ?
-                       PPC::ADJCALLSTACKDOWN : PPC::ADJCALLSTACKUP;
-    return CurDAG->SelectNodeTo(N, Opc, MVT::Other,
-                                getI32Imm(Amt), Select(N->getOperand(0)));
-  }
   case ISD::RET: {
     SDOperand Chain = Select(N->getOperand(0));     // Token chain.
 





From lattner at cs.uiuc.edu  Sun Dec  4 13:04:50 2005
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Sun, 4 Dec 2005 13:04:50 -0600
Subject: [llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp 
Message-ID: <200512041904.NAA30370@zion.cs.uiuc.edu>



Changes in directory llvm/lib/Target/PowerPC:

PPCISelDAGToDAG.cpp updated: 1.137 -> 1.138
---
Log message:

The basic fneg cases are already autogen'd


---
Diffs of the changes:  (+2 -4)

 PPCISelDAGToDAG.cpp |    6 ++----
 1 files changed, 2 insertions(+), 4 deletions(-)


Index: llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
diff -u llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp:1.137 llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp:1.138
--- llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp:1.137	Sun Dec  4 13:01:59 2005
+++ llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp	Sun Dec  4 13:04:38 2005
@@ -1062,10 +1062,8 @@
                                       Val.getOperand(1), Val.getOperand(2));
       }
     }
-    if (Ty == MVT::f32)
-      return CurDAG->SelectNodeTo(N, PPC::FNEGS, MVT::f32, Val);
-    else
-      return CurDAG->SelectNodeTo(N, PPC::FNEGD, MVT::f64, Val);
+    // Other cases are autogenerated.
+    break;
   }
   case ISD::LOAD:
   case ISD::EXTLOAD:





From lattner at cs.uiuc.edu  Sun Dec  4 18:49:02 2005
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Sun, 4 Dec 2005 18:49:02 -0600
Subject: [llvm-commits] CVS: llvm/utils/TableGen/DAGISelEmitter.cpp 
Message-ID: <200512050049.SAA00951@zion.cs.uiuc.edu>



Changes in directory llvm/utils/TableGen:

DAGISelEmitter.cpp updated: 1.82 -> 1.83
---
Log message:

Generate code to silence bogus GCC warnings.


---
Diffs of the changes:  (+1 -1)

 DAGISelEmitter.cpp |    2 +-
 1 files changed, 1 insertion(+), 1 deletion(-)


Index: llvm/utils/TableGen/DAGISelEmitter.cpp
diff -u llvm/utils/TableGen/DAGISelEmitter.cpp:1.82 llvm/utils/TableGen/DAGISelEmitter.cpp:1.83
--- llvm/utils/TableGen/DAGISelEmitter.cpp:1.82	Sun Dec  4 02:18:16 2005
+++ llvm/utils/TableGen/DAGISelEmitter.cpp	Sun Dec  4 18:48:51 2005
@@ -1778,7 +1778,7 @@
         if (RR->isSubClassOf("Register")) {
           MVT::ValueType RVT = getRegisterValueType(RR, T);
           if (!InFlag) {
-            OS << "      SDOperand InFlag;\n";
+            OS << "      SDOperand InFlag = SDOperand(0,0);\n";
             InFlag = true;
           }
           if (HasChain) {





From lattner at cs.uiuc.edu  Sun Dec  4 20:34:17 2005
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Sun, 4 Dec 2005 20:34:17 -0600
Subject: [llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCInstrInfo.td 
Message-ID: <200512050234.UAA01417@zion.cs.uiuc.edu>



Changes in directory llvm/lib/Target/PowerPC:

PPCInstrInfo.td updated: 1.150 -> 1.151
---
Log message:

Add some explicit type casts so that tblgen knows the type of the shift
amount, which is not necessarily the same as the type being shifted.


---
Diffs of the changes:  (+5 -5)

 PPCInstrInfo.td |   10 +++++-----
 1 files changed, 5 insertions(+), 5 deletions(-)


Index: llvm/lib/Target/PowerPC/PPCInstrInfo.td
diff -u llvm/lib/Target/PowerPC/PPCInstrInfo.td:1.150 llvm/lib/Target/PowerPC/PPCInstrInfo.td:1.151
--- llvm/lib/Target/PowerPC/PPCInstrInfo.td:1.150	Sun Dec  4 13:01:59 2005
+++ llvm/lib/Target/PowerPC/PPCInstrInfo.td	Sun Dec  4 20:34:05 2005
@@ -467,7 +467,7 @@
 }
 def SRAWI : XForm_10<31, 824, (ops GPRC:$rA, GPRC:$rS, u5imm:$SH), 
                      "srawi $rA, $rS, $SH", IntShift,
-                     [(set GPRC:$rA, (sra GPRC:$rS, imm:$SH))]>;
+                     [(set GPRC:$rA, (sra GPRC:$rS, (i32 imm:$SH)))]>;
 def CNTLZW : XForm_11<31,  26, (ops GPRC:$rA, GPRC:$rS),
                       "cntlzw $rA, $rS", IntGeneral,
                       [(set GPRC:$rA, (ctlz GPRC:$rS))]>;
@@ -875,14 +875,14 @@
           (OR8To4 G8RC:$in, G8RC:$in)>;
 
 // SHL
-def : Pat<(shl GPRC:$in, imm:$imm),
+def : Pat<(shl GPRC:$in, (i32 imm:$imm)),
           (RLWINM GPRC:$in, imm:$imm, 0, (SHL32 imm:$imm))>;
-def : Pat<(shl G8RC:$in, imm:$imm),
+def : Pat<(shl G8RC:$in, (i64 imm:$imm)),
           (RLDICR G8RC:$in, imm:$imm, (SHL64 imm:$imm))>;
 // SRL
-def : Pat<(srl GPRC:$in, imm:$imm),
+def : Pat<(srl GPRC:$in, (i32 imm:$imm)),
           (RLWINM GPRC:$in, (SRL32 imm:$imm), imm:$imm, 31)>;
-def : Pat<(srl G8RC:$in, imm:$imm),
+def : Pat<(srl G8RC:$in, (i64 imm:$imm)),
           (RLDICL G8RC:$in, (SRL64 imm:$imm), imm:$imm)>;
 
 // Hi and Lo for Darwin Global Addresses.





From lattner at cs.uiuc.edu  Sun Dec  4 20:34:41 2005
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Sun, 4 Dec 2005 20:34:41 -0600
Subject: [llvm-commits] CVS: llvm/lib/Target/IA64/IA64InstrInfo.td 
Message-ID: <200512050234.UAA01476@zion.cs.uiuc.edu>



Changes in directory llvm/lib/Target/IA64:

IA64InstrInfo.td updated: 1.29 -> 1.30
---
Log message:

Add some explicit type casts so that tblgen knows the type of the shiftamount, which is not necessarily the same as the type being shifted.


---
Diffs of the changes:  (+6 -6)

 IA64InstrInfo.td |   12 ++++++------
 1 files changed, 6 insertions(+), 6 deletions(-)


Index: llvm/lib/Target/IA64/IA64InstrInfo.td
diff -u llvm/lib/Target/IA64/IA64InstrInfo.td:1.29 llvm/lib/Target/IA64/IA64InstrInfo.td:1.30
--- llvm/lib/Target/IA64/IA64InstrInfo.td:1.29	Sun Nov 13 19:17:30 2005
+++ llvm/lib/Target/IA64/IA64InstrInfo.td	Sun Dec  4 20:34:29 2005
@@ -156,31 +156,31 @@
 def MIX1L : AForm_DAG<0x03, 0x0b, (ops GR:$dst, GR:$src1, GR:$src2),
           "mix1.l $dst = $src1, $src2;;",
 	  [(set GR:$dst, (or (and GR:$src1, isMIX1Lable),
-	                     (and (srl GR:$src2, 8), isMIX1Lable)))]>;
+	                     (and (srl GR:$src2, (i64 8)), isMIX1Lable)))]>;
 
 def MIX2L : AForm_DAG<0x03, 0x0b, (ops GR:$dst, GR:$src1, GR:$src2),
           "mix2.l $dst = $src1, $src2;;",
 	  [(set GR:$dst, (or (and GR:$src1, isMIX2Lable),
-	                     (and (srl GR:$src2, 16), isMIX2Lable)))]>;
+	                     (and (srl GR:$src2, (i64 16)), isMIX2Lable)))]>;
 
 def MIX4L : AForm_DAG<0x03, 0x0b, (ops GR:$dst, GR:$src1, GR:$src2),
           "mix4.l $dst = $src1, $src2;;",
 	  [(set GR:$dst, (or (and GR:$src1, isMIX4Lable),
-	                     (and (srl GR:$src2, 32), isMIX4Lable)))]>;
+	                     (and (srl GR:$src2, (i64 32)), isMIX4Lable)))]>;
 
 def MIX1R : AForm_DAG<0x03, 0x0b, (ops GR:$dst, GR:$src1, GR:$src2),
           "mix1.r $dst = $src1, $src2;;",
-	  [(set GR:$dst, (or (and (shl GR:$src1, 8), isMIX1Rable),
+	  [(set GR:$dst, (or (and (shl GR:$src1, (i64 8)), isMIX1Rable),
 	                     (and GR:$src2, isMIX1Rable)))]>;
 
 def MIX2R : AForm_DAG<0x03, 0x0b, (ops GR:$dst, GR:$src1, GR:$src2),
           "mix2.r $dst = $src1, $src2;;",
-	  [(set GR:$dst, (or (and (shl GR:$src1, 16), isMIX2Rable),
+	  [(set GR:$dst, (or (and (shl GR:$src1, (i64 16)), isMIX2Rable),
 	                     (and GR:$src2, isMIX2Rable)))]>;
 
 def MIX4R : AForm_DAG<0x03, 0x0b, (ops GR:$dst, GR:$src1, GR:$src2),
           "mix4.r $dst = $src1, $src2;;",
-	  [(set GR:$dst, (or (and (shl GR:$src1, 32), isMIX4Rable),
+	  [(set GR:$dst, (or (and (shl GR:$src1, (i64 32)), isMIX4Rable),
 	                     (and GR:$src2, isMIX4Rable)))]>;
 
 def GETFSIGD : AForm_DAG<0x03, 0x0b, (ops GR:$dst, FP:$src),





From lattner at cs.uiuc.edu  Sun Dec  4 20:35:20 2005
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Sun, 4 Dec 2005 20:35:20 -0600
Subject: [llvm-commits] CVS: llvm/utils/TableGen/CodeGenRegisters.h
	CodeGenTarget.h 
Message-ID: <200512050235.UAA01575@zion.cs.uiuc.edu>



Changes in directory llvm/utils/TableGen:

CodeGenRegisters.h updated: 1.9 -> 1.10
CodeGenTarget.h updated: 1.20 -> 1.21
---
Log message:

Add some methods


---
Diffs of the changes:  (+22 -1)

 CodeGenRegisters.h |    2 ++
 CodeGenTarget.h    |   21 ++++++++++++++++++++-
 2 files changed, 22 insertions(+), 1 deletion(-)


Index: llvm/utils/TableGen/CodeGenRegisters.h
diff -u llvm/utils/TableGen/CodeGenRegisters.h:1.9 llvm/utils/TableGen/CodeGenRegisters.h:1.10
--- llvm/utils/TableGen/CodeGenRegisters.h:1.9	Wed Nov 30 22:51:06 2005
+++ llvm/utils/TableGen/CodeGenRegisters.h	Sun Dec  4 20:35:08 2005
@@ -42,6 +42,8 @@
 
     const std::string &getName() const;
 
+    unsigned getNumValueTypes() const { return VTs.size(); }
+    
     const MVT::ValueType getValueTypeNum(unsigned VTNum) const {
       if (VTNum < VTs.size())
         return VTs[VTNum];


Index: llvm/utils/TableGen/CodeGenTarget.h
diff -u llvm/utils/TableGen/CodeGenTarget.h:1.20 llvm/utils/TableGen/CodeGenTarget.h:1.21
--- llvm/utils/TableGen/CodeGenTarget.h:1.20	Wed Nov 30 18:06:14 2005
+++ llvm/utils/TableGen/CodeGenTarget.h	Sun Dec  4 20:35:08 2005
@@ -90,7 +90,26 @@
     assert(0 && "Didn't find the register class");
     abort();
   }
-
+  
+  /// getRegisterClassForRegister - Find the register class that contains the
+  /// specified physical register.  If there register exists in multiple
+  /// register classes or is not in a register class, return null.
+  const CodeGenRegisterClass *getRegisterClassForRegister(Record *R) const {
+    const std::vector<CodeGenRegisterClass> &RCs = getRegisterClasses();
+    const CodeGenRegisterClass *FoundRC = 0;
+    for (unsigned i = 0, e = RCs.size(); i != e; ++i) {
+      const CodeGenRegisterClass &RC = RegisterClasses[i];
+      for (unsigned ei = 0, ee = RC.Elements.size(); ei != ee; ++ei) {
+        if (R == RC.Elements[ei]) {
+          if (FoundRC) return 0;  // In multiple RC's
+          FoundRC = &RC;
+          break;
+        }
+      }
+    }
+    return FoundRC;
+  }
+  
   const std::vector<MVT::ValueType> &getLegalValueTypes() const {
     if (LegalValueTypes.empty()) ReadLegalValueTypes();
     return LegalValueTypes;





From lattner at cs.uiuc.edu  Sun Dec  4 20:36:49 2005
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Sun, 4 Dec 2005 20:36:49 -0600
Subject: [llvm-commits] CVS: llvm/utils/TableGen/DAGISelEmitter.cpp 
Message-ID: <200512050236.UAA01687@zion.cs.uiuc.edu>



Changes in directory llvm/utils/TableGen:

DAGISelEmitter.cpp updated: 1.83 -> 1.84
---
Log message:

Implement PR673: http://llvm.cs.uiuc.edu/PR673 : for explicit register references, use type information
if available


---
Diffs of the changes:  (+8 -15)

 DAGISelEmitter.cpp |   23 ++++++++---------------
 1 files changed, 8 insertions(+), 15 deletions(-)


Index: llvm/utils/TableGen/DAGISelEmitter.cpp
diff -u llvm/utils/TableGen/DAGISelEmitter.cpp:1.83 llvm/utils/TableGen/DAGISelEmitter.cpp:1.84
--- llvm/utils/TableGen/DAGISelEmitter.cpp:1.83	Sun Dec  4 18:48:51 2005
+++ llvm/utils/TableGen/DAGISelEmitter.cpp	Sun Dec  4 20:36:37 2005
@@ -467,9 +467,12 @@
     // Pattern fragment types will be resolved when they are inlined.
     return MVT::isUnknown;
   } else if (R->isSubClassOf("Register")) {
-    //const CodeGenTarget &T = TP.getDAGISelEmitter().getTargetInfo();
-    // TODO: if a register appears in exactly one regclass, we could use that
-    // type info.
+    // If the register appears in exactly one regclass, and the regclass has one
+    // value type, use it as the known type.
+    const CodeGenTarget &T = TP.getDAGISelEmitter().getTargetInfo();
+    if (const CodeGenRegisterClass *RC = T.getRegisterClassForRegister(R))
+      if (RC->getNumValueTypes() == 1)
+        return RC->getValueTypeNum(0);
     return MVT::isUnknown;
   } else if (R->isSubClassOf("ValueType") || R->isSubClassOf("CondCode")) {
     // Using a VTSDNode or CondCodeSDNode.
@@ -1719,18 +1722,8 @@
 /// getRegisterValueType - Look up and return the first ValueType of specified 
 /// RegisterClass record
 static MVT::ValueType getRegisterValueType(Record *R, const CodeGenTarget &T) {
-  const std::vector<CodeGenRegisterClass> &RegisterClasses =
-    T.getRegisterClasses();
-
-  for (unsigned i = 0, e = RegisterClasses.size(); i != e; ++i) {
-    const CodeGenRegisterClass &RC = RegisterClasses[i];
-    for (unsigned ei = 0, ee = RC.Elements.size(); ei != ee; ++ei) {
-      if (R == RC.Elements[ei]) {
-        return RC.getValueTypeNum(0);
-      }
-    }
-  }
-
+  if (const CodeGenRegisterClass *RC = T.getRegisterClassForRegister(R))
+    return RC->getValueTypeNum(0);
   return MVT::Other;
 }
 





From lattner at cs.uiuc.edu  Sun Dec  4 20:37:38 2005
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Sun, 4 Dec 2005 20:37:38 -0600
Subject: [llvm-commits] CVS: llvm/lib/Target/TargetSelectionDAG.td 
Message-ID: <200512050237.UAA01720@zion.cs.uiuc.edu>



Changes in directory llvm/lib/Target:

TargetSelectionDAG.td updated: 1.11 -> 1.12
---
Log message:

On some targets (e.g. X86), shift amounts are not the same as the value 
being shifted.  Don't assume they are.


---
Diffs of the changes:  (+6 -3)

 TargetSelectionDAG.td |    9 ++++++---
 1 files changed, 6 insertions(+), 3 deletions(-)


Index: llvm/lib/Target/TargetSelectionDAG.td
diff -u llvm/lib/Target/TargetSelectionDAG.td:1.11 llvm/lib/Target/TargetSelectionDAG.td:1.12
--- llvm/lib/Target/TargetSelectionDAG.td:1.11	Sun Dec  4 02:13:17 2005
+++ llvm/lib/Target/TargetSelectionDAG.td	Sun Dec  4 20:37:26 2005
@@ -73,6 +73,9 @@
 def SDTIntBinOp : SDTypeProfile<1, 2, [   // add, and, or, xor, udiv, etc.
   SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisInt<0>
 ]>;
+def SDTIntShiftOp : SDTypeProfile<1, 2, [   // shl, sra, srl
+  SDTCisSameAs<0, 1>, SDTCisInt<0>, SDTCisInt<2>
+]>;
 def SDTFPBinOp : SDTypeProfile<1, 2, [      // fadd, fmul, etc.
   SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisFP<0>
 ]>;
@@ -172,9 +175,9 @@
 def udiv       : SDNode<"ISD::UDIV"      , SDTIntBinOp>;
 def srem       : SDNode<"ISD::SREM"      , SDTIntBinOp>;
 def urem       : SDNode<"ISD::UREM"      , SDTIntBinOp>;
-def srl        : SDNode<"ISD::SRL"       , SDTIntBinOp>;
-def sra        : SDNode<"ISD::SRA"       , SDTIntBinOp>;
-def shl        : SDNode<"ISD::SHL"       , SDTIntBinOp>;
+def srl        : SDNode<"ISD::SRL"       , SDTIntShiftOp>;
+def sra        : SDNode<"ISD::SRA"       , SDTIntShiftOp>;
+def shl        : SDNode<"ISD::SHL"       , SDTIntShiftOp>;
 def and        : SDNode<"ISD::AND"       , SDTIntBinOp,
                         [SDNPCommutative, SDNPAssociative]>;
 def or         : SDNode<"ISD::OR"        , SDTIntBinOp,





From lattner at cs.uiuc.edu  Sun Dec  4 20:40:37 2005
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Sun, 4 Dec 2005 20:40:37 -0600
Subject: [llvm-commits] CVS: llvm/lib/Target/X86/X86InstrInfo.td 
Message-ID: <200512050240.UAA01766@zion.cs.uiuc.edu>



Changes in directory llvm/lib/Target/X86:

X86InstrInfo.td updated: 1.146 -> 1.147
---
Log message:

Several things:
1. Remove redundant type casts now that PR673: http://llvm.cs.uiuc.edu/PR673  is implemented.
2. Implement the OUT*ir instructions correctly.  The port number really
   *is* a 16-bit value, but the patterns should only match if the number
   is 0-255.  Update the patterns so they now match.
3. Fix patterns for shifts to reflect that the shift amount is always an
   i8, not an i16 as they were believed to be before.  This previous fib
   stopped working when we started knowing that CL has type i8.
4. Change use of i16i8imm in SH*ri patterns to all be imm.



---
Diffs of the changes:  (+32 -24)

 X86InstrInfo.td |   56 ++++++++++++++++++++++++++++++++------------------------
 1 files changed, 32 insertions(+), 24 deletions(-)


Index: llvm/lib/Target/X86/X86InstrInfo.td
diff -u llvm/lib/Target/X86/X86InstrInfo.td:1.146 llvm/lib/Target/X86/X86InstrInfo.td:1.147
--- llvm/lib/Target/X86/X86InstrInfo.td:1.146	Sun Dec  4 02:19:43 2005
+++ llvm/lib/Target/X86/X86InstrInfo.td	Sun Dec  4 20:40:25 2005
@@ -145,6 +145,13 @@
   return (int)N->getValue() == (signed char)N->getValue();
 }]>;
 
+def immZExt8  : PatLeaf<(imm), [{
+  // immZExt8 predicate - True if the immediate fits in a 8-bit zero extended
+  // field.
+  return (unsigned)N->getValue() == (unsigned char)N->getValue();
+}]>;
+
+
 //===----------------------------------------------------------------------===//
 // Instruction templates...
 
@@ -328,25 +335,25 @@
 let hasCtrlDep=1 in {
   def OUT8rr  : I<0xEE, RawFrm, (ops),
                   "out{b} {%al, %dx|%DX, %AL}",
-                  [(writeport (i8 AL), (i16 DX))]>,  Imp<[DX,  AL], []>;
+                  [(writeport AL, DX)]>,  Imp<[DX,  AL], []>;
   def OUT16rr : I<0xEF, RawFrm, (ops),
                   "out{w} {%ax, %dx|%DX, %AX}",
-                  [(writeport (i16 AX), (i16 DX))]>,  Imp<[DX,  AX], []>, OpSize;
+                  [(writeport AX, DX)]>,  Imp<[DX,  AX], []>, OpSize;
   def OUT32rr : I<0xEF, RawFrm, (ops),
                   "out{l} {%eax, %dx|%DX, %EAX}",
-                  [(writeport (i32 EAX), (i16 DX))]>, Imp<[DX, EAX], []>;
+                  [(writeport EAX, DX)]>, Imp<[DX, EAX], []>;
 
-  def OUT8ir  : Ii8<0xE6, RawFrm, (ops i8imm:$port),
+  def OUT8ir  : Ii8<0xE6, RawFrm, (ops i16i8imm:$port),
                      "out{b} {%al, $port|$port, %AL}",
-                     [(writeport (i8 AL), (i8 imm:$port))]>,
+                     [(writeport AL, (i16 immZExt8:$port))]>,
                      Imp<[AL], []>;
-  def OUT16ir : Ii8<0xE7, RawFrm, (ops i8imm:$port),
+  def OUT16ir : Ii8<0xE7, RawFrm, (ops i16i8imm:$port),
                      "out{w} {%ax, $port|$port, %AX}",
-                     [(writeport (i16 AX), (i8 imm:$port))]>,
+                     [(writeport AX, (i16 immZExt8:$port))]>,
                      Imp<[AX], []>, OpSize;
-  def OUT32ir : Ii8<0xE7, RawFrm, (ops i8imm:$port),
+  def OUT32ir : Ii8<0xE7, RawFrm, (ops i16i8imm:$port),
                      "out{l} {%eax, $port|$port, %EAX}",
-                     [(writeport (i32 EAX), (i8 imm:$port))]>,
+                     [(writeport EAX, (i16 immZExt8:$port))]>,
                      Imp<[EAX], []>;
 }
 
@@ -917,14 +924,14 @@
 
 def SHL8ri   : Ii8<0xC0, MRM4r, (ops R8 :$dst, R8 :$src1, i8imm:$src2),
                    "shl{b} {$src2, $dst|$dst, $src2}",
-                   [(set R8:$dst, (shl R8:$src1, imm:$src2))]>;
+                   [(set R8:$dst, (shl R8:$src1, (i8 imm:$src2)))]>;
 let isConvertibleToThreeAddress = 1 in {   // Can transform into LEA.
-def SHL16ri  : Ii8<0xC1, MRM4r, (ops R16:$dst, R16:$src1, i16i8imm:$src2),
+def SHL16ri  : Ii8<0xC1, MRM4r, (ops R16:$dst, R16:$src1, i8imm:$src2),
                    "shl{w} {$src2, $dst|$dst, $src2}",
-                   [(set R16:$dst, (shl R16:$src1, immSExt8:$src2))]>, OpSize;
-def SHL32ri  : Ii8<0xC1, MRM4r, (ops R32:$dst, R32:$src1, i32i8imm:$src2),
+                   [(set R16:$dst, (shl R16:$src1, (i8 imm:$src2)))]>, OpSize;
+def SHL32ri  : Ii8<0xC1, MRM4r, (ops R32:$dst, R32:$src1, i8imm:$src2),
                    "shl{l} {$src2, $dst|$dst, $src2}",
-                   [(set R32:$dst, (shl R32:$src1, immSExt8:$src2))]>;
+                   [(set R32:$dst, (shl R32:$src1, (i8 imm:$src2)))]>;
 }
 
 let isTwoAddress = 0 in {
@@ -954,13 +961,13 @@
 
 def SHR8ri   : Ii8<0xC0, MRM5r, (ops R8:$dst, R8:$src1, i8imm:$src2),
                    "shr{b} {$src2, $dst|$dst, $src2}",
-                   [(set R8:$dst, (srl R8:$src1, imm:$src2))]>;
-def SHR16ri  : Ii8<0xC1, MRM5r, (ops R16:$dst, R16:$src1, i16i8imm:$src2),
+                   [(set R8:$dst, (srl R8:$src1, (i8 imm:$src2)))]>;
+def SHR16ri  : Ii8<0xC1, MRM5r, (ops R16:$dst, R16:$src1, i8imm:$src2),
                    "shr{w} {$src2, $dst|$dst, $src2}",
-                   [(set R16:$dst, (srl R16:$src1, immSExt8:$src2))]>, OpSize;
-def SHR32ri  : Ii8<0xC1, MRM5r, (ops R32:$dst, R32:$src1, i32i8imm:$src2),
+                   [(set R16:$dst, (srl R16:$src1, (i8 imm:$src2)))]>, OpSize;
+def SHR32ri  : Ii8<0xC1, MRM5r, (ops R32:$dst, R32:$src1, i8imm:$src2),
                    "shr{l} {$src2, $dst|$dst, $src2}",
-                   [(set R32:$dst, (srl R32:$src1, immSExt8:$src2))]>;
+                   [(set R32:$dst, (srl R32:$src1, (i8 imm:$src2)))]>;
 
 let isTwoAddress = 0 in {
   def SHR8mCL  : I<0xD2, MRM5m, (ops i8mem :$dst),
@@ -989,13 +996,14 @@
 
 def SAR8ri   : Ii8<0xC0, MRM7r, (ops R8 :$dst, R8 :$src1, i8imm:$src2),
                    "sar{b} {$src2, $dst|$dst, $src2}",
-                   [(set R8:$dst, (sra R8:$src1, imm:$src2))]>;
-def SAR16ri  : Ii8<0xC1, MRM7r, (ops R16:$dst, R16:$src1, i16i8imm:$src2),
+                   [(set R8:$dst, (sra R8:$src1, (i8 imm:$src2)))]>;
+def SAR16ri  : Ii8<0xC1, MRM7r, (ops R16:$dst, R16:$src1, i8imm:$src2),
                    "sar{w} {$src2, $dst|$dst, $src2}",
-                   [(set R16:$dst, (sra R16:$src1, immSExt8:$src2))]>, OpSize;
-def SAR32ri  : Ii8<0xC1, MRM7r, (ops R32:$dst, R32:$src1, i32i8imm:$src2),
+                   [(set R16:$dst, (sra R16:$src1, (i8 imm:$src2)))]>,
+                   OpSize;
+def SAR32ri  : Ii8<0xC1, MRM7r, (ops R32:$dst, R32:$src1, i8imm:$src2),
                    "sar{l} {$src2, $dst|$dst, $src2}",
-                   [(set R32:$dst, (sra R32:$src1, immSExt8:$src2))]>;
+                   [(set R32:$dst, (sra R32:$src1, (i8 imm:$src2)))]>;
 let isTwoAddress = 0 in {
   def SAR8mCL  : I<0xD2, MRM7m, (ops i8mem :$dst),
                    "sar{b} {%cl, $dst|$dst, %CL}", []>, Imp<[CL],[]>;





From lattner at cs.uiuc.edu  Sun Dec  4 21:22:58 2005
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Sun, 4 Dec 2005 21:22:58 -0600
Subject: [llvm-commits] 
	CVS: llvm/test/Regression/CFrontend/2005-12-04-DeclarationLineNumbers.c
Message-ID: <200512050322.VAA02176@zion.cs.uiuc.edu>



Changes in directory llvm/test/Regression/CFrontend:

2005-12-04-DeclarationLineNumbers.c added (r1.1)
---
Log message:

testcase for PR664: http://llvm.cs.uiuc.edu/PR664 


---
Diffs of the changes:  (+20 -0)

 2005-12-04-DeclarationLineNumbers.c |   20 ++++++++++++++++++++
 1 files changed, 20 insertions(+)


Index: llvm/test/Regression/CFrontend/2005-12-04-DeclarationLineNumbers.c
diff -c /dev/null llvm/test/Regression/CFrontend/2005-12-04-DeclarationLineNumbers.c:1.1
*** /dev/null	Sun Dec  4 21:22:56 2005
--- llvm/test/Regression/CFrontend/2005-12-04-DeclarationLineNumbers.c	Sun Dec  4 21:22:46 2005
***************
*** 0 ****
--- 1,20 ----
+ // RUN: %llvmgcc %s -S -g -o - | grep 'llvm.dbg.stoppoint.*uint 14'
+ // PR664: ensure that line #'s are emitted for declarations
+ short test(short br_data_0,
+ short br_data_1,
+ short br_data_2,
+ short br_data_3,
+ short br_data_4,
+ short br_data_5,
+ short br_data_6,
+ short br_data_7) {
+ 
+ short sm07 = br_data_0 + br_data_7;
+ short sm16 = br_data_1 + br_data_6;
+ short sm25 = br_data_2 + br_data_5;
+ short sm34 = br_data_3 + br_data_4;
+ short s0734 = sm07 + sm34;
+ short s1625 = sm16 + sm25;
+ 
+ return s0734 + s1625;
+ }





From lattner at cs.uiuc.edu  Sun Dec  4 21:24:33 2005
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Sun, 4 Dec 2005 21:24:33 -0600
Subject: [llvm-commits] CVS: llvm-gcc/gcc/llvm-expand.c 
Message-ID: <200512050324.VAA02454@zion.cs.uiuc.edu>



Changes in directory llvm-gcc/gcc:

llvm-expand.c updated: 1.118 -> 1.119
---
Log message:

Fix PR664: http://llvm.cs.uiuc.edu/PR664  by emitting line numbers for declarations.



---
Diffs of the changes:  (+11 -9)

 llvm-expand.c |   20 +++++++++++---------
 1 files changed, 11 insertions(+), 9 deletions(-)


Index: llvm-gcc/gcc/llvm-expand.c
diff -u llvm-gcc/gcc/llvm-expand.c:1.118 llvm-gcc/gcc/llvm-expand.c:1.119
--- llvm-gcc/gcc/llvm-expand.c:1.118	Tue Nov 29 12:25:04 2005
+++ llvm-gcc/gcc/llvm-expand.c	Sun Dec  4 21:24:21 2005
@@ -2731,14 +2731,14 @@
     int saved_stmts_are_full_exprs_p = stmts_are_full_exprs_p ();
     prep_stmt (t);
   
-    if(debug_info_level > DINFO_LEVEL_NONE){
-      if(TREE_CODE(t) == COMPOUND_STMT){
-	/* skip compound statements - we handle their components. 
-	   Avoids emitting multiple stop points for a single line. */
-      }else if (TREE_CODE(t) == DECL_STMT){
-	llvm_emit_dbg_declare(Fn, t); /* FIXME: does nothing */
-      }else{
-	llvm_emit_dbg_stoppoint(Fn, STMT_LINENO(t), 0);
+    if (debug_info_level > DINFO_LEVEL_NONE) {
+      if (TREE_CODE(t) == COMPOUND_STMT) {
+        /* skip compound statements - we handle their components. 
+          Avoids emitting multiple stop points for a single line. */
+      } else if (TREE_CODE(t) == DECL_STMT) {
+        llvm_emit_dbg_declare(Fn, t); /* FIXME: does nothing */
+      } else {
+        llvm_emit_dbg_stoppoint(Fn, STMT_LINENO(t), 0);
       }
     }
 
@@ -8251,7 +8251,9 @@
 
 
 /* Emit intrinsics to mark variable declarations */
-static void llvm_emit_dbg_declare(llvm_function * Fn, tree t){
+static void llvm_emit_dbg_declare(llvm_function * Fn, tree t) {
+  llvm_emit_dbg_stoppoint(Fn, STMT_LINENO(t), 0);
+
   /* FIXME: need to actually do this.  
 
   See llvm_emit_dbg_stoppoint for an example of how to create a new





From lattner at cs.uiuc.edu  Sun Dec  4 22:48:23 2005
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Sun, 4 Dec 2005 22:48:23 -0600
Subject: [llvm-commits] 
	CVS: llvm/test/Regression/CFrontend/2005-12-04-AttributeUsed.c
Message-ID: <200512050448.WAA03110@zion.cs.uiuc.edu>



Changes in directory llvm/test/Regression/CFrontend:

2005-12-04-AttributeUsed.c added (r1.1)
---
Log message:

New testcase for PR660: http://llvm.cs.uiuc.edu/PR660 


---
Diffs of the changes:  (+8 -0)

 2005-12-04-AttributeUsed.c |    8 ++++++++
 1 files changed, 8 insertions(+)


Index: llvm/test/Regression/CFrontend/2005-12-04-AttributeUsed.c
diff -c /dev/null llvm/test/Regression/CFrontend/2005-12-04-AttributeUsed.c:1.1
*** /dev/null	Sun Dec  4 22:48:22 2005
--- llvm/test/Regression/CFrontend/2005-12-04-AttributeUsed.c	Sun Dec  4 22:48:12 2005
***************
*** 0 ****
--- 1,8 ----
+ // RUN: %llvmgcc %s -S -o - | llvm-as | llvm-dis | grep llvm.used | grep foo | grep X
+ 
+ int X __attribute__((used));
+ int Y;
+ 
+ void foo() __attribute__((used));
+ 
+ void foo() {}





From lattner at cs.uiuc.edu  Sun Dec  4 22:49:33 2005
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Sun, 4 Dec 2005 22:49:33 -0600
Subject: [llvm-commits] CVS: llvm-gcc/gcc/llvm-expand.c
	llvm-representation.c llvm-representation.h 
Message-ID: <200512050449.WAA03172@zion.cs.uiuc.edu>



Changes in directory llvm-gcc/gcc:

llvm-expand.c updated: 1.119 -> 1.120
llvm-representation.c updated: 1.21 -> 1.22
llvm-representation.h updated: 1.20 -> 1.21
---
Log message:

Implement support for attribute "used", implementing PR660: http://llvm.cs.uiuc.edu/PR660  and
implementing test/Regression/CFrontend/2005-12-04-AttributeUsed.c.



---
Diffs of the changes:  (+66 -1)

 llvm-expand.c         |    9 ++++++++
 llvm-representation.c |   56 +++++++++++++++++++++++++++++++++++++++++++++++++-
 llvm-representation.h |    2 +
 3 files changed, 66 insertions(+), 1 deletion(-)


Index: llvm-gcc/gcc/llvm-expand.c
diff -u llvm-gcc/gcc/llvm-expand.c:1.119 llvm-gcc/gcc/llvm-expand.c:1.120
--- llvm-gcc/gcc/llvm-expand.c:1.119	Sun Dec  4 21:24:21 2005
+++ llvm-gcc/gcc/llvm-expand.c	Sun Dec  4 22:49:21 2005
@@ -7271,6 +7271,10 @@
     return Fn;
   }
 
+  /* If this was marked 'used', add it to the 'used' list.  */
+  if (lookup_attribute ("used", DECL_ATTRIBUTES (subr)))
+    Fn->AttributeUsed = 1;
+  
   /* If there is already a body for this function, it's a wierd error.  The only
    * case we allow is if the old function was linkonce.
    */
@@ -7776,6 +7780,11 @@
       G->Init = V2C(llvm_constant_get_null(BaseTy));
     }
   }
+    
+  /* If this was marked 'used', add it to the 'used' list.  */
+  if (lookup_attribute ("used", DECL_ATTRIBUTES (decl)))
+    G->AttributeUsed = 1;
+    
 
   TREE_ASM_WRITTEN(decl) = 1;
   if (EMIT_CODE_INCREMENTALLY) llvm_global_print(G, llvm_out_file);


Index: llvm-gcc/gcc/llvm-representation.c
diff -u llvm-gcc/gcc/llvm-representation.c:1.21 llvm-gcc/gcc/llvm-representation.c:1.22
--- llvm-gcc/gcc/llvm-representation.c:1.21	Tue Nov 29 12:25:04 2005
+++ llvm-gcc/gcc/llvm-representation.c	Sun Dec  4 22:49:21 2005
@@ -24,6 +24,7 @@
 #include "hashtab.h"
 #include <assert.h>
 #include <string.h>
+#include <ctype.h>
 
 /* The one true program we are compiling */
 llvm_program TheProgram;
@@ -1055,6 +1056,8 @@
 
 /* Print the specified program to the output file */
 void llvm_program_print(FILE *F) {
+  unsigned NumAttributeUsed;
+  
   llvm_type_print_all_named(F);
 
   /* Output global ctors and dtors if there are any */
@@ -1081,7 +1084,58 @@
       fprintf(F, "\n    ]\n\n");
     }
   }
-
+  
+  /* Output the llvm.used array if there are any attribute(used) globals */
+  NumAttributeUsed = 0;
+  
+  {  /* Count globals that are attribute used */
+  llvm_global *I;
+  for (I = llvm_ilist_begin(TheProgram.Globals);
+       I != llvm_ilist_end(TheProgram.Globals);
+       I = I->Next)
+    if (I->AttributeUsed) ++NumAttributeUsed;
+  }
+  {  /* Count functions that are attribute used */
+    llvm_function *I;
+    for (I = llvm_ilist_begin(TheProgram.Functions);
+         I != llvm_ilist_end(TheProgram.Functions);
+         I = I->Next)
+      if (I->AttributeUsed) ++NumAttributeUsed;
+  }
+
+  if (NumAttributeUsed) {
+    llvm_global *G;
+    llvm_function *Fn;
+    fprintf(F, "; Attribute used list\n");
+    fprintf(F,"%%llvm.used = appending global [%d x sbyte*]"
+            " [\n", NumAttributeUsed);
+    NumAttributeUsed = 0;
+    for (G = llvm_ilist_begin(TheProgram.Globals);
+         G != llvm_ilist_end(TheProgram.Globals);
+         G = G->Next) {
+      if (G->AttributeUsed) {
+        if (NumAttributeUsed++)
+          fprintf(F, ",\n");
+        fprintf(F, "\tsbyte* cast (");
+        llvm_value_print_operand(G2V(G), 1, F);
+        fprintf(F, " to sbyte*)");
+      }
+    }
+    for (Fn = llvm_ilist_begin(TheProgram.Functions);
+         Fn != llvm_ilist_end(TheProgram.Functions);
+         Fn = Fn->Next) {
+      if (Fn->AttributeUsed) {
+        if (NumAttributeUsed++)
+          fprintf(F, ",\n");
+        fprintf(F, "\tsbyte* cast (");
+        llvm_value_print_operand(G2V(Fn), 1, F);
+          fprintf(F, " to sbyte*)");
+      }
+    }
+    fprintf(F, "\n    ]\n\n");
+  }
+  
+  
   /* Output the rest of the global variables... */
   llvm_ilist_foreach1(llvm_global, TheProgram.Globals, llvm_global_print, F);
 


Index: llvm-gcc/gcc/llvm-representation.h
diff -u llvm-gcc/gcc/llvm-representation.h:1.20 llvm-gcc/gcc/llvm-representation.h:1.21
--- llvm-gcc/gcc/llvm-representation.h:1.20	Tue Nov 29 12:25:04 2005
+++ llvm-gcc/gcc/llvm-representation.h	Sun Dec  4 22:49:21 2005
@@ -287,6 +287,7 @@
 
   ENUM_BITFIELD (llvm_linkage) Linkage : 4;
   int MarkedNameUsed : 1;
+  int AttributeUsed : 1;       /* Function is attribute(used) */
   char *PrettyFunctionName;
 } llvm_function;
 
@@ -307,6 +308,7 @@
   llvm_ilist_node(struct llvm_global, Globals); /* Part of Global list */
   llvm_constant *Init;                  /* Initializer or null for external */
   int isConstant : 1;                   /* Is the global immutable? */
+  int AttributeUsed : 1;                /* Global is attribute(used) */
 
   ENUM_BITFIELD (llvm_linkage) Linkage : 4;
   int  MarkedNameUsed : 1;





From lattner at cs.uiuc.edu  Sun Dec  4 23:07:50 2005
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Sun, 4 Dec 2005 23:07:50 -0600
Subject: [llvm-commits] CVS: llvm/lib/Transforms/IPO/Internalize.cpp 
Message-ID: <200512050507.XAA03511@zion.cs.uiuc.edu>



Changes in directory llvm/lib/Transforms/IPO:

Internalize.cpp updated: 1.26 -> 1.27
---
Log message:

Wrap a long line, never internalize llvm.used.


---
Diffs of the changes:  (+6 -2)

 Internalize.cpp |    8 ++++++--
 1 files changed, 6 insertions(+), 2 deletions(-)


Index: llvm/lib/Transforms/IPO/Internalize.cpp
diff -u llvm/lib/Transforms/IPO/Internalize.cpp:1.26 llvm/lib/Transforms/IPO/Internalize.cpp:1.27
--- llvm/lib/Transforms/IPO/Internalize.cpp:1.26	Tue Oct 18 01:29:22 2005
+++ llvm/lib/Transforms/IPO/Internalize.cpp	Sun Dec  4 23:07:38 2005
@@ -99,9 +99,13 @@
         }
 
       // Mark all global variables with initializers as internal as well...
-      for (Module::global_iterator I = M.global_begin(), E = M.global_end(); I != E; ++I)
+      for (Module::global_iterator I = M.global_begin(), E = M.global_end();
+           I != E; ++I)
         if (!I->isExternal() && !I->hasInternalLinkage() &&
-            !ExternalNames.count(I->getName())) {
+            !ExternalNames.count(I->getName()) &&
+            // *never* internalize the llvm.used symbol, used to implement
+            // attribute((used)).
+            I->getName() != "llvm.used") {
           // Special case handling of the global ctor and dtor list.  When we
           // internalize it, we mark it constant, which allows elimination of
           // the list if it's empty.





From lattner at cs.uiuc.edu  Sun Dec  4 23:23:18 2005
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Sun, 4 Dec 2005 23:23:18 -0600
Subject: [llvm-commits] CVS: llvm/docs/ReleaseNotes.html 
Message-ID: <200512050523.XAA03638@zion.cs.uiuc.edu>



Changes in directory llvm/docs:

ReleaseNotes.html updated: 1.343 -> 1.344
---
Log message:

attribute((used)) is now supported


---
Diffs of the changes:  (+4 -4)

 ReleaseNotes.html |    8 ++++----
 1 files changed, 4 insertions(+), 4 deletions(-)


Index: llvm/docs/ReleaseNotes.html
diff -u llvm/docs/ReleaseNotes.html:1.343 llvm/docs/ReleaseNotes.html:1.344
--- llvm/docs/ReleaseNotes.html:1.343	Tue Nov  8 15:29:17 2005
+++ llvm/docs/ReleaseNotes.html	Sun Dec  4 23:23:06 2005
@@ -254,14 +254,14 @@
 
       <b>Supported:</b> <tt>format</tt>, <tt>format_arg</tt>, <tt>non_null</tt>,
       <tt>noreturn</tt>, <tt>constructor</tt>, <tt>destructor</tt>,
-      <tt>unused</tt>,
+      <tt>unused</tt>, <tt>used</tt>,
       <tt>deprecated</tt>, <tt>warn_unused_result</tt>, <tt>weak</tt><br>
 
       <b>Ignored:</b> <tt>noinline</tt>,
       <tt>always_inline</tt>, <tt>pure</tt>, <tt>const</tt>, <tt>nothrow</tt>,
       <tt>malloc</tt>, <tt>no_instrument_function</tt>, <tt>cdecl</tt><br>
 
-      <b>Unsupported:</b> <tt>used</tt>, <tt>section</tt>, <tt>alias</tt>,
+      <b>Unsupported:</b> <tt>section</tt>, <tt>alias</tt>,
       <tt>visibility</tt>, <tt>regparm</tt>, <tt>stdcall</tt>,
       <tt>fastcall</tt>, all other target specific attributes</li>
    
@@ -269,7 +269,7 @@
       Specifying attributes of variables.<br>
       <b>Supported:</b> <tt>cleanup</tt>, <tt>common</tt>, <tt>nocommon</tt>,
                         <tt>deprecated</tt>, <tt>transparent_union</tt>,
-                        <tt>unused</tt>, <tt>weak</tt><br>
+                        <tt>unused</tt>, <tt>used</tt>, <tt>weak</tt><br>
 
       <b>Unsupported:</b> <tt>aligned</tt>, <tt>mode</tt>, <tt>packed</tt>,
                         <tt>section</tt>, <tt>shared</tt>, <tt>tls_model</tt>,
@@ -556,7 +556,7 @@
   src="http://www.w3.org/Icons/valid-html401" alt="Valid HTML 4.01!" /></a>
 
   <a href="http://llvm.org/">The LLVM Compiler Infrastructure</a><br>
-  Last modified: $Date: 2005/11/08 21:29:17 $
+  Last modified: $Date: 2005/12/05 05:23:06 $
 </address>
 
 </body>





From lattner at cs.uiuc.edu  Sun Dec  4 23:30:34 2005
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Sun, 4 Dec 2005 23:30:34 -0600
Subject: [llvm-commits] CVS: llvm/include/llvm/Module.h 
Message-ID: <200512050530.XAA05685@zion.cs.uiuc.edu>



Changes in directory llvm/include/llvm:

Module.h updated: 1.64 -> 1.65
---
Log message:

Add a flag to Module::getGlobalVariable to allow it to return vars with
internal linkage.

Patch provided by Evan Jones, thanks!



---
Diffs of the changes:  (+7 -6)

 Module.h |   13 +++++++------
 1 files changed, 7 insertions(+), 6 deletions(-)


Index: llvm/include/llvm/Module.h
diff -u llvm/include/llvm/Module.h:1.64 llvm/include/llvm/Module.h:1.65
--- llvm/include/llvm/Module.h:1.64	Tue Oct 25 12:58:00 2005
+++ llvm/include/llvm/Module.h	Sun Dec  4 23:30:21 2005
@@ -137,13 +137,14 @@
   //
 
   /// getGlobalVariable - Look up the specified global variable in the module
-  /// symbol table.  If it does not exist, return null.  Note that this only
-  /// returns a global variable if it does not have internal linkage.  The type
-  /// argument should be the underlying type of the global, i.e., it should not
-  /// have the top-level PointerType, which represents the address of the
-  /// global.
+  /// symbol table.  If it does not exist, return null.  The type argument
+  /// should be the underlying type of the global, i.e., it should not have
+  /// the top-level PointerType, which represents the address of the global.
+  /// If AllowInternal is set to true, this function will return types that
+  /// have InternalLinkage. By default, these types are not returned.
   ///
-  GlobalVariable *getGlobalVariable(const std::string &Name, const Type *Ty);
+  GlobalVariable *getGlobalVariable(const std::string &Name, const Type *Ty,
+                                    bool AllowInternal = false);
 
 
   //===--------------------------------------------------------------------===//





From lattner at cs.uiuc.edu  Sun Dec  4 23:30:34 2005
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Sun, 4 Dec 2005 23:30:34 -0600
Subject: [llvm-commits] CVS: llvm/lib/VMCore/Module.cpp 
Message-ID: <200512050530.XAA05689@zion.cs.uiuc.edu>



Changes in directory llvm/lib/VMCore:

Module.cpp updated: 1.61 -> 1.62
---
Log message:

Add a flag to Module::getGlobalVariable to allow it to return vars with
internal linkage.

Patch provided by Evan Jones, thanks!



---
Diffs of the changes:  (+7 -7)

 Module.cpp |   14 +++++++-------
 1 files changed, 7 insertions(+), 7 deletions(-)


Index: llvm/lib/VMCore/Module.cpp
diff -u llvm/lib/VMCore/Module.cpp:1.61 llvm/lib/VMCore/Module.cpp:1.62
--- llvm/lib/VMCore/Module.cpp:1.61	Thu Apr 21 18:46:51 2005
+++ llvm/lib/VMCore/Module.cpp	Sun Dec  4 23:30:21 2005
@@ -206,17 +206,17 @@
 //
 
 /// getGlobalVariable - Look up the specified global variable in the module
-/// symbol table.  If it does not exist, return null.  Note that this only
-/// returns a global variable if it does not have internal linkage.  The type
-/// argument should be the underlying type of the global, ie, it should not
-/// have the top-level PointerType, which represents the address of the
-/// global.
+/// symbol table.  If it does not exist, return null.  The type argument
+/// should be the underlying type of the global, i.e., it should not have
+/// the top-level PointerType, which represents the address of the global.
+/// If AllowInternal is set to true, this function will return types that
+/// have InternalLinkage. By default, these types are not returned.
 ///
 GlobalVariable *Module::getGlobalVariable(const std::string &Name,
-                                          const Type *Ty) {
+                                          const Type *Ty, bool AllowInternal) {
   if (Value *V = getSymbolTable().lookup(PointerType::get(Ty), Name)) {
     GlobalVariable *Result = cast<GlobalVariable>(V);
-    if (!Result->hasInternalLinkage())
+    if (AllowInternal || !Result->hasInternalLinkage())
       return Result;
   }
   return 0;