See Also @@ -639,7 +654,7 @@ Chris Lattner
LLVM Compiler Infrastructure
- Last modified: $Date: 2004/12/04 00:32:12 $ + Last modified: $Date: 2006/01/01 21:59:22 $ From alenhar2 at cs.uiuc.edu Sun Jan 1 16:14:05 2006 From: alenhar2 at cs.uiuc.edu (Andrew Lenharth) Date: Sun, 1 Jan 2006 16:14:05 -0600 Subject: [llvm-commits] CVS: llvm/lib/Target/Alpha/AlphaRegisterInfo.cpp Message-ID: <200601012214.QAA01976@zion.cs.uiuc.edu> Changes in directory llvm/lib/Target/Alpha: AlphaRegisterInfo.cpp updated: 1.30 -> 1.31 --- Log message: clean this function up some --- Diffs of the changes: (+26 -37) AlphaRegisterInfo.cpp | 63 ++++++++++++++++++++------------------------------ 1 files changed, 26 insertions(+), 37 deletions(-) Index: llvm/lib/Target/Alpha/AlphaRegisterInfo.cpp diff -u llvm/lib/Target/Alpha/AlphaRegisterInfo.cpp:1.30 llvm/lib/Target/Alpha/AlphaRegisterInfo.cpp:1.31 --- llvm/lib/Target/Alpha/AlphaRegisterInfo.cpp:1.30 Wed Nov 9 13:17:08 2005 +++ llvm/lib/Target/Alpha/AlphaRegisterInfo.cpp Sun Jan 1 16:13:54 2006 @@ -126,43 +126,32 @@ MachineInstr *AlphaRegisterInfo::foldMemoryOperand(MachineInstr *MI, unsigned OpNum, int FrameIndex) const { - // Make sure this is a reg-reg copy. - unsigned Opc = MI->getOpcode(); - - if ((Opc == Alpha::BIS && - MI->getOperand(1).getReg() == MI->getOperand(2).getReg())) { - if (OpNum == 0) { // move -> store - unsigned InReg = MI->getOperand(1).getReg(); - return BuildMI(Alpha::STQ, 3).addReg(InReg).addFrameIndex(FrameIndex) - .addReg(Alpha::F31); - } else { // load -> move - unsigned OutReg = MI->getOperand(0).getReg(); - return BuildMI(Alpha::LDQ, 2, OutReg).addFrameIndex(FrameIndex) - .addReg(Alpha::F31); - } - } else if ((Opc == Alpha::CPYSS && - MI->getOperand(1).getReg() == MI->getOperand(2).getReg())) { - if (OpNum == 0) { // move -> store - unsigned InReg = MI->getOperand(1).getReg(); - return BuildMI(Alpha::STS, 3).addReg(InReg).addFrameIndex(FrameIndex) - .addReg(Alpha::F31); - } else { // load -> move - unsigned OutReg = MI->getOperand(0).getReg(); - return BuildMI(Alpha::LDS, 2, OutReg).addFrameIndex(FrameIndex) - .addReg(Alpha::F31); - } - } else if ((Opc == Alpha::CPYST && - MI->getOperand(1).getReg() == MI->getOperand(2).getReg())) { - if (OpNum == 0) { // move -> store - unsigned InReg = MI->getOperand(1).getReg(); - return BuildMI(Alpha::STT, 3).addReg(InReg).addFrameIndex(FrameIndex) - .addReg(Alpha::F31); - } else { // load -> move - unsigned OutReg = MI->getOperand(0).getReg(); - return BuildMI(Alpha::LDT, 2, OutReg).addFrameIndex(FrameIndex) - .addReg(Alpha::F31); - } - } + // Make sure this is a reg-reg copy. + unsigned Opc = MI->getOpcode(); + + switch(Opc) { + default: + break; + case Alpha::BIS: + case Alpha::CPYSS: + case Alpha::CPYST: + if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg()) { + if (OpNum == 0) { // move -> store + unsigned InReg = MI->getOperand(1).getReg(); + Opc = (Opc == Alpha::BIS) ? Alpha::STQ : + ((Opc == Alpha::CPYSS) ? Alpha::STS : Alpha::STT); + return BuildMI(Opc, 3).addReg(InReg).addFrameIndex(FrameIndex) + .addReg(Alpha::F31); + } else { // load -> move + unsigned OutReg = MI->getOperand(0).getReg(); + Opc = (Opc == Alpha::BIS) ? Alpha::LDQ : + ((Opc == Alpha::CPYSS) ? Alpha::LDS : Alpha::LDT); + return BuildMI(Opc, 2, OutReg).addFrameIndex(FrameIndex) + .addReg(Alpha::F31); + } + } + break; + } return 0; } From alenhar2 at cs.uiuc.edu Sun Jan 1 16:14:42 2006 From: alenhar2 at cs.uiuc.edu (Andrew Lenharth) Date: Sun, 1 Jan 2006 16:14:42 -0600 Subject: [llvm-commits] CVS: llvm/test/Regression/CodeGen/Alpha/zapnot2.ll Message-ID: <200601012214.QAA01990@zion.cs.uiuc.edu> Changes in directory llvm/test/Regression/CodeGen/Alpha: zapnot2.ll updated: 1.2 -> 1.3 --- Log message: Change this regression so andi is not a valid codegen of it --- Diffs of the changes: (+1 -1) zapnot2.ll | 2 +- 1 files changed, 1 insertion(+), 1 deletion(-) Index: llvm/test/Regression/CodeGen/Alpha/zapnot2.ll diff -u llvm/test/Regression/CodeGen/Alpha/zapnot2.ll:1.2 llvm/test/Regression/CodeGen/Alpha/zapnot2.ll:1.3 --- llvm/test/Regression/CodeGen/Alpha/zapnot2.ll:1.2 Fri May 13 10:42:07 2005 +++ llvm/test/Regression/CodeGen/Alpha/zapnot2.ll Sun Jan 1 16:14:31 2006 @@ -5,6 +5,6 @@ long %bar(long %x) { entry: - %tmp.1 = and long %x, 255 ; [#uses=1] + %tmp.1 = and long %x, 16711935 ; [#uses=1] ret long %tmp.1 } From alenhar2 at cs.uiuc.edu Sun Jan 1 16:16:26 2006 From: alenhar2 at cs.uiuc.edu (Andrew Lenharth) Date: Sun, 1 Jan 2006 16:16:26 -0600 Subject: [llvm-commits] CVS: llvm/lib/Target/Alpha/AlphaISelDAGToDAG.cpp AlphaInstrFormats.td AlphaInstrInfo.td Message-ID: <200601012216.QAA02029@zion.cs.uiuc.edu> Changes in directory llvm/lib/Target/Alpha: AlphaISelDAGToDAG.cpp updated: 1.24 -> 1.25 AlphaInstrFormats.td updated: 1.21 -> 1.22 AlphaInstrInfo.td updated: 1.96 -> 1.97 --- Log message: Move brcond over and fix some imm patterns. This may be the last change before changing the default alpha isel. --- Diffs of the changes: (+166 -160) AlphaISelDAGToDAG.cpp | 85 +++++++++--------- AlphaInstrFormats.td | 17 +++ AlphaInstrInfo.td | 224 ++++++++++++++++++++++++-------------------------- 3 files changed, 166 insertions(+), 160 deletions(-) Index: llvm/lib/Target/Alpha/AlphaISelDAGToDAG.cpp diff -u llvm/lib/Target/Alpha/AlphaISelDAGToDAG.cpp:1.24 llvm/lib/Target/Alpha/AlphaISelDAGToDAG.cpp:1.25 --- llvm/lib/Target/Alpha/AlphaISelDAGToDAG.cpp:1.24 Thu Dec 29 20:30:02 2005 +++ llvm/lib/Target/Alpha/AlphaISelDAGToDAG.cpp Sun Jan 1 16:16:14 2006 @@ -41,7 +41,46 @@ static const int64_t IMM_LOW = -32768; static const int64_t IMM_HIGH = 32767; static const int64_t IMM_MULT = 65536; - + static const int64_t IMM_FULLHIGH = IMM_HIGH + IMM_HIGH * IMM_MULT; + static const int64_t IMM_FULLLOW = IMM_LOW + IMM_LOW * IMM_MULT; + + static int64_t get_ldah16(int64_t x) { + int64_t y = x / IMM_MULT; + if (x % IMM_MULT > IMM_HIGH) + ++y; + return y; + } + + static int64_t get_lda16(int64_t x) { + return x - get_ldah16(x) * IMM_MULT; + } + + static uint64_t get_zapImm(uint64_t x) { + unsigned int build = 0; + for(int i = 0; i < 8; ++i) + { + if ((x & 0x00FF) == 0x00FF) + build |= 1 << i; + else if ((x & 0x00FF) != 0) + { build = 0; break; } + x >>= 8; + } + return x; + } + + static bool isFPZ(SDOperand N) { + ConstantFPSDNode *CN = dyn_cast(N); + return (CN && (CN->isExactlyValue(+0.0) || CN->isExactlyValue(-0.0))); + } + static bool isFPZn(SDOperand N) { + ConstantFPSDNode *CN = dyn_cast(N); + return (CN && CN->isExactlyValue(-0.0)); + } + static bool isFPZp(SDOperand N) { + ConstantFPSDNode *CN = dyn_cast(N); + return (CN && CN->isExactlyValue(+0.0)); + } + public: AlphaDAGToDAGISel(TargetMachine &TM) : SelectionDAGISel(AlphaLowering), AlphaLowering(TM) @@ -154,46 +193,6 @@ CodeGenMap[Op.getValue(1)] = Result.getValue(1); return SDOperand(Result.Val, Op.ResNo); } - case ISD::BRCOND: { - if (N->getOperand(1).getOpcode() == ISD::SETCC && - MVT::isFloatingPoint(N->getOperand(1).getOperand(0).getValueType())) { - SDOperand Chain = Select(N->getOperand(0)); - SDOperand CC1 = Select(N->getOperand(1).getOperand(0)); - SDOperand CC2 = Select(N->getOperand(1).getOperand(1)); - ISD::CondCode cCode= cast(N->getOperand(1).getOperand(2))->get(); - - bool rev = false; - bool isNE = false; - unsigned Opc = Alpha::WTF; - switch(cCode) { - default: N->dump(); assert(0 && "Unknown FP comparison!"); - case ISD::SETEQ: Opc = Alpha::CMPTEQ; break; - case ISD::SETLT: Opc = Alpha::CMPTLT; break; - case ISD::SETLE: Opc = Alpha::CMPTLE; break; - case ISD::SETGT: Opc = Alpha::CMPTLT; rev = true; break; - case ISD::SETGE: Opc = Alpha::CMPTLE; rev = true; break; - case ISD::SETNE: Opc = Alpha::CMPTEQ; isNE = true; break; - }; - SDOperand cmp = CurDAG->getTargetNode(Opc, MVT::f64, - rev?CC2:CC1, - rev?CC1:CC2); - - MachineBasicBlock *Dest = - cast(N->getOperand(2))->getBasicBlock(); - if(isNE) - return CurDAG->SelectNodeTo(N, Alpha::FBEQ, MVT::Other, cmp, - CurDAG->getBasicBlock(Dest), Chain); - else - return CurDAG->SelectNodeTo(N, Alpha::FBNE, MVT::Other, cmp, - CurDAG->getBasicBlock(Dest), Chain); - } - SDOperand Chain = Select(N->getOperand(0)); - SDOperand CC = Select(N->getOperand(1)); - MachineBasicBlock *Dest = - cast(N->getOperand(2))->getBasicBlock(); - return CurDAG->SelectNodeTo(N, Alpha::BNE, MVT::Other, CC, - CurDAG->getBasicBlock(Dest), Chain); - } case ISD::FrameIndex: { int FI = cast(N)->getIndex(); @@ -248,8 +247,8 @@ val >= IMM_LOW + IMM_LOW * IMM_MULT) break; //(LDAH (LDA)) if ((uval >> 32) == 0 && //empty upper bits - val32 <= IMM_HIGH + IMM_HIGH * IMM_MULT && - val32 >= IMM_LOW + IMM_LOW * IMM_MULT) + val32 <= IMM_HIGH + IMM_HIGH * IMM_MULT) + // val32 >= IMM_LOW + IMM_LOW * IMM_MULT) //always true break; //(zext (LDAH (LDA))) //Else use the constant pool MachineConstantPool *CP = BB->getParent()->getConstantPool(); Index: llvm/lib/Target/Alpha/AlphaInstrFormats.td diff -u llvm/lib/Target/Alpha/AlphaInstrFormats.td:1.21 llvm/lib/Target/Alpha/AlphaInstrFormats.td:1.22 --- llvm/lib/Target/Alpha/AlphaInstrFormats.td:1.21 Sun Dec 25 11:36:48 2005 +++ llvm/lib/Target/Alpha/AlphaInstrFormats.td Sun Jan 1 16:16:14 2006 @@ -107,10 +107,23 @@ let Inst{25-21} = Ra; let Inst{20-0} = disp; } +let isBranch = 1, isTerminator = 1 in +class BFormDG opcode, string asmstr, list pattern> + : InstAlpha { + let Pattern = pattern; + + bits<5> Ra; + bits<21> disp; + + let Inst{25-21} = Ra; + let Inst{20-0} = disp; +} let isBranch = 1, isTerminator = 1 in -class FBForm opcode, string asmstr> - : InstAlpha { +class FBForm opcode, string asmstr, list pattern> + : InstAlpha { + let Pattern = pattern; + bits<5> Ra; bits<21> disp; Index: llvm/lib/Target/Alpha/AlphaInstrInfo.td diff -u llvm/lib/Target/Alpha/AlphaInstrInfo.td:1.96 llvm/lib/Target/Alpha/AlphaInstrInfo.td:1.97 --- llvm/lib/Target/Alpha/AlphaInstrInfo.td:1.96 Thu Dec 29 20:30:02 2005 +++ llvm/lib/Target/Alpha/AlphaInstrInfo.td Sun Jan 1 16:16:14 2006 @@ -34,72 +34,56 @@ def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_AlphaCallSeq,[SDNPHasChain]>; def callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_AlphaCallSeq,[SDNPHasChain]>; +def SDTFPLeaf : SDTypeProfile<1, 0, [SDTCisFP<0>]>; // for 'fpimm'. +def fpimm : SDNode<"ISD::ConstantFP" , SDTFPLeaf , [], "ConstantFPSDNode">; //******************** //Paterns for matching //******************** -def invX : SDNodeXFormgetValue()); }]>; -def immUExt8 : PatLeaf<(imm), [{ - // immUExt8 predicate - True if the immediate fits in a 8-bit zero extended - // field. Used by instructions like 'addi'. +def negX : SDNodeXFormgetValue() + 1); +}]>; +def SExt32 : SDNodeXFormgetValue() << 32) >> 32); +}]>; +def SExt16 : SDNodeXFormgetValue() << 48) >> 48); +}]>; +def LL16 : SDNodeXFormgetValue())); +}]>; +def LH16 : SDNodeXFormgetValue())); +}]>; +def iZAPX : SDNodeXFormgetValue())); +}]>; + +def immUExt8 : PatLeaf<(imm), [{ //imm fits in 8 bit zero extended field return (uint64_t)N->getValue() == (uint8_t)N->getValue(); }]>; -def immUExt8inv : PatLeaf<(imm), [{ - // immUExt8inv predicate - True if the inverted immediate fits in a 8-bit zero extended - // field. Used by instructions like 'ornoti'. +def immUExt8inv : PatLeaf<(imm), [{ //inverted imm fits in 8 bit zero extended field return (uint64_t)~N->getValue() == (uint8_t)~N->getValue(); }], invX>; -def immSExt16 : PatLeaf<(imm), [{ - // immSExt16 predicate - True if the immediate fits in a 16-bit sign extended - // field. Used by instructions like 'lda'. - return (int64_t)N->getValue() == (int16_t)N->getValue(); -}]>; - -def SExtInt : SDNodeXFormgetValue() << 32) >> 32); +def immUExt8neg : PatLeaf<(imm), [{ //negated imm fits in 8 bit zero extended field + return ((uint64_t)~N->getValue() + 1) == (uint8_t)((uint64_t)~N->getValue() + 1); +}], negX>; +def immSExt16 : PatLeaf<(imm), [{ //imm fits in 16 bit sign extended field + return ((int64_t)N->getValue() << 48) >> 48 == (int64_t)N->getValue(); }]>; - -def immSExt16int : PatLeaf<(imm), [{ - // immSExt16 predicate - True if the immediate fits in a 16-bit sign extended - // field. Used by instructions like 'lda'. - int64_t val = (int64_t)N->getValue(); - uint32_t uval32 = (uint32_t)val; - int32_t val32 = (int32_t)val; - return (int64_t)uval32 == val && val32 == (int16_t)val32; -}], SExtInt>; - - -def iZAPX : SDNodeXFormgetValue(); - unsigned int build = 0; - for(int i = 0; i < 8; ++i) - { - if ((UImm & 0x00FF) == 0x00FF) - build |= 1 << i; - else if ((UImm & 0x00FF) != 0) - { build = 0; break; } - UImm >>= 8; - } - return getI64Imm(build); -}]>; -def immZAP : PatLeaf<(imm), [{ - // immZAP predicate - True if the immediate fits is suitable for use in a - // ZAP instruction - uint64_t UImm = (uint64_t)N->getValue(); - unsigned int build = 0; - for(int i = 0; i < 8; ++i) - { - if ((UImm & 0x00FF) == 0x00FF) - build |= 1 << i; - else if ((UImm & 0x00FF) != 0) - { build = 0; break; } - UImm >>= 8; - } +def immSExt16int : PatLeaf<(imm), [{ //(int)imm fits in a 16 bit sign extended field + return ((int64_t)N->getValue() << 48) >> 48 == ((int64_t)N->getValue() << 32) >> 32; +}], SExt16>; +def immZAP : PatLeaf<(imm), [{ //imm is good for zapi + uint64_t build = get_zapImm((uint64_t)N->getValue()); return build != 0; }], iZAPX>; +def immFPZ : PatLeaf<(fpimm), [{ //the only fpconstant nodes are +/- 0.0 + return true; +}]>; def intop : PatFrag<(ops node:$op), (sext_inreg node:$op, i32)>; def add4 : PatFrag<(ops node:$op1, node:$op2), @@ -111,11 +95,8 @@ def sub8 : PatFrag<(ops node:$op1, node:$op2), (sub (shl node:$op1, 3), node:$op2)>; - // //#define FP $15 - // //#define RA $26 - // //#define PV $27 - // //#define GP $29 - // //#define SP $30 + +//Pseudo ops for selection def PHI : PseudoInstAlpha<(ops variable_ops), "#phi", []>; @@ -127,6 +108,7 @@ [(set F8RC:$RA, (undef))]>; def WTF : PseudoInstAlpha<(ops variable_ops), "#wtf", []>; + let isLoad = 1, hasCtrlDep = 1 in { def ADJUSTSTACKUP : PseudoInstAlpha<(ops s64imm:$amt), "; ADJUP $amt", [(callseq_start imm:$amt)]>; @@ -138,12 +120,7 @@ def MEMLABEL : PseudoInstAlpha<(ops s64imm:$i, s64imm:$j, s64imm:$k, s64imm:$m), "LSMARKER$$$i$$$j$$$k$$$m:\n",[]>; -//***************** -//These are shortcuts, the assembler expands them -//***************** -//AT = R28 -//T0-T7 = R1 - R8 -//T8-T11 = R22-R25 + //An even better improvement on the Int = SetCC(FP): SelectCC! //These are evil because they hide control flow in a MBB @@ -322,11 +299,11 @@ def S8SUBL : OForm< 0x10, 0x1B, "s8subl $RA,$RB,$RC", [(set GPRC:$RC, (intop (sub8 GPRC:$RA, GPRC:$RB)))]>; def S8SUBLi : OFormL<0x10, 0x1B, "s8subl $RA,$L,$RC", - [(set GPRC:$RC, (intop (sub8 GPRC:$RA, immUExt8:$L)))]>; + [(set GPRC:$RC, (intop (add8 GPRC:$RA, immUExt8neg:$L)))]>; def S8SUBQ : OForm< 0x10, 0x3B, "s8subq $RA,$RB,$RC", [(set GPRC:$RC, (sub8 GPRC:$RA, GPRC:$RB))]>; def S8SUBQi : OFormL<0x10, 0x3B, "s8subq $RA,$L,$RC", - [(set GPRC:$RC, (sub8 GPRC:$RA, immUExt8:$L))]>; + [(set GPRC:$RC, (add8 GPRC:$RA, immUExt8neg:$L))]>; def SEXTB : OForm2<0x1C, 0x00, "sextb $RB,$RC", [(set GPRC:$RC, (sext_inreg GPRC:$RB, i8))]>; def SEXTW : OForm2<0x1C, 0x01, "sextw $RB,$RC", @@ -346,11 +323,11 @@ def SUBL : OForm< 0x10, 0x09, "subl $RA,$RB,$RC", [(set GPRC:$RC, (intop (sub GPRC:$RA, GPRC:$RB)))]>; def SUBLi : OFormL<0x10, 0x09, "subl $RA,$L,$RC", - [(set GPRC:$RC, (intop (sub GPRC:$RA, immUExt8:$L)))]>; + [(set GPRC:$RC, (intop (add GPRC:$RA, immUExt8neg:$L)))]>; def SUBQ : OForm< 0x10, 0x29, "subq $RA,$RB,$RC", [(set GPRC:$RC, (sub GPRC:$RA, GPRC:$RB))]>; def SUBQi : OFormL<0x10, 0x29, "subq $RA,$L,$RC", - [(set GPRC:$RC, (sub GPRC:$RA, immUExt8:$L))]>; + [(set GPRC:$RC, (add GPRC:$RA, immUExt8neg:$L))]>; def UMULH : OForm< 0x13, 0x30, "umulh $RA,$RB,$RC", [(set GPRC:$RC, (mulhu GPRC:$RA, GPRC:$RB))]>; def UMULHi : OFormL<0x13, 0x30, "umulh $RA,$L,$RC", @@ -449,10 +426,6 @@ def JSR_COROUTINE : MbrForm< 0x1A, 0x03, (ops GPRC:$RD, GPRC:$RS, s14imm:$DISP), "jsr_coroutine $RD,($RS),$DISP">; //Jump to subroutine return -let Ra = 31 in -def BR : BFormD<0x30, "br $$31,$DISP", [(br bb:$DISP)]>; - - let OperandList = (ops GPRC:$RA, s64imm:$DISP, GPRC:$RB) in { def LDQ : MForm<0x29, 0, 1, "ldq $RA,$DISP($RB)", [(set GPRC:$RA, (load (add GPRC:$RB, immSExt16:$DISP)))]>; @@ -594,24 +567,6 @@ def : Pat<(Alpha_rellit texternalsym:$ext, GPRC:$RB), (LDQl texternalsym:$ext, GPRC:$RB)>; -//Branches, int -def BEQ : BForm<0x39, "beq $RA,$DISP">; //Branch if = zero -def BGE : BForm<0x3E, "bge $RA,$DISP">; //Branch if >= zero -def BGT : BForm<0x3F, "bgt $RA,$DISP">; //Branch if > zero -def BLBC : BForm<0x38, "blbc $RA,$DISP">; //Branch if low bit clear -def BLBS : BForm<0x3C, "blbs $RA,$DISP">; //Branch if low bit set -def BLE : BForm<0x3B, "ble $RA,$DISP">; //Branch if <= zero -def BLT : BForm<0x3A, "blt $RA,$DISP">; //Branch if < zero -def BNE : BForm<0x3D, "bne $RA,$DISP">; //Branch if != zero - -//Branches, float -def FBEQ : FBForm<0x31, "fbeq $RA,$DISP">; //Floating branch if = zero -def FBGE : FBForm<0x36, "fbge $RA,$DISP">; //Floating branch if >= zero -def FBGT : FBForm<0x37, "fbgt $RA,$DISP">; //Floating branch if > zero -def FBLE : FBForm<0x33, "fble $RA,$DISP">; //Floating branch if <= zero -def FBLT : FBForm<0x32, "fblt $RA,$DISP">; //Floating branch if < zero -def FBNE : FBForm<0x35, "fbne $RA,$DISP">; //Floating branch if != zero - def RPCC : MfcForm<0x18, 0xC000, "rpcc $RA">; //Read process cycle counter //Basic Floating point ops @@ -747,6 +702,63 @@ def CVTTS : FPForm<0x16, 0x7AC, "cvtts/sui $RB,$RC", [(set F4RC:$RC, (fround F8RC:$RB))]>; + +///////////////////////////////////////////////////////// +//Branching +///////////////////////////////////////////////////////// +let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, noResults = 1 in { +let Ra = 31 in +def BR : BFormD<0x30, "br $$31,$DISP", [(br bb:$DISP)]>; + +//Branches, int +def BEQ : BFormDG<0x39, "beq $RA,$DISP", + [(brcond (seteq GPRC:$RA, 0), bb:$DISP)]>; +def BGE : BFormDG<0x3E, "bge $RA,$DISP", + [(brcond (setge GPRC:$RA, 0), bb:$DISP)]>; +def BGT : BFormDG<0x3F, "bgt $RA,$DISP", + [(brcond (setgt GPRC:$RA, 0), bb:$DISP)]>; +def BLBC : BFormDG<0x38, "blbc $RA,$DISP", []>; //TODO: Low bit clear +def BLBS : BFormDG<0x3C, "blbs $RA,$DISP", + [(brcond (seteq GPRC:$RA, 1), bb:$DISP)]>; +def BLE : BFormDG<0x3B, "ble $RA,$DISP", + [(brcond (setle GPRC:$RA, 0), bb:$DISP)]>; +def BLT : BFormDG<0x3A, "blt $RA,$DISP", + [(brcond (setlt GPRC:$RA, 0), bb:$DISP)]>; +def BNE : BFormDG<0x3D, "bne $RA,$DISP", + [(brcond (setne GPRC:$RA, 0), bb:$DISP)]>; + +//Branches, float +def FBEQ : FBForm<0x31, "fbeq $RA,$DISP", + [(brcond (seteq F8RC:$RA, immFPZ), bb:$DISP)]>; +def FBGE : FBForm<0x36, "fbge $RA,$DISP", + [(brcond (setge F8RC:$RA, immFPZ), bb:$DISP)]>; +def FBGT : FBForm<0x37, "fbgt $RA,$DISP", + [(brcond (setgt F8RC:$RA, immFPZ), bb:$DISP)]>; +def FBLE : FBForm<0x33, "fble $RA,$DISP", + [(brcond (setle F8RC:$RA, immFPZ), bb:$DISP)]>; +def FBLT : FBForm<0x32, "fblt $RA,$DISP", + [(brcond (setlt F8RC:$RA, immFPZ), bb:$DISP)]>; +def FBNE : FBForm<0x35, "fbne $RA,$DISP", + [(brcond (setne F8RC:$RA, immFPZ), bb:$DISP)]>; +} + +def : Pat<(brcond (and GPRC:$RA, 1), bb:$DISP), (BLBS GPRC:$RA, bb:$DISP)>; +def : Pat<(brcond GPRC:$RA, bb:$DISP), (BNE GPRC:$RA, bb:$DISP)>; +def : Pat<(brcond (seteq F8RC:$RA, F8RC:$RB), bb:$DISP), + (FBNE (CMPTEQ F8RC:$RA, F8RC:$RB), bb:$DISP)>; +def : Pat<(brcond (setlt F8RC:$RA, F8RC:$RB), bb:$DISP), + (FBNE (CMPTLT F8RC:$RA, F8RC:$RB), bb:$DISP)>; +def : Pat<(brcond (setle F8RC:$RA, F8RC:$RB), bb:$DISP), + (FBNE (CMPTLE F8RC:$RA, F8RC:$RB), bb:$DISP)>; +def : Pat<(brcond (setgt F8RC:$RA, F8RC:$RB), bb:$DISP), + (FBNE (CMPTLT F8RC:$RB, F8RC:$RA), bb:$DISP)>; +def : Pat<(brcond (setge F8RC:$RA, F8RC:$RB), bb:$DISP), + (FBNE (CMPTLE F8RC:$RB, F8RC:$RA), bb:$DISP)>; +def : Pat<(brcond (setne F8RC:$RA, F8RC:$RB), bb:$DISP), + (FBEQ (CMPTEQ F8RC:$RA, F8RC:$RB), bb:$DISP)>; + +//End Branches + //S_floating : IEEE Single //T_floating : IEEE Double @@ -794,34 +806,16 @@ def immConst2Part : PatLeaf<(imm), [{ //true if imm fits in a LDAH LDA pair int64_t val = (int64_t)N->getValue(); - return (val <= (int64_t)IMM_HIGH +(int64_t)IMM_HIGH* (int64_t)IMM_MULT & - val >= (int64_t)IMM_LOW + (int64_t)IMM_LOW * (int64_t)IMM_MULT); + return (val <= IMM_FULLHIGH && val >= IMM_FULLLOW); }]>; def immConst2PartInt : PatLeaf<(imm), [{ //true if imm fits in a LDAH LDA pair with zeroext uint64_t uval = N->getValue(); int32_t val32 = (int32_t)uval; return ((uval >> 32) == 0 && //empty upper bits - val32 <= IMM_HIGH + IMM_HIGH * IMM_MULT && - val32 >= IMM_LOW + IMM_LOW * IMM_MULT); -}], SExtInt>; - -//TODO: factor this out -def LL16 : SDNodeXFormgetValue(); - int64_t y = l / IMM_MULT; - if (l % IMM_MULT > IMM_HIGH) - ++y; - return getI64Imm(l - y * IMM_MULT); -}]>; -//TODO: factor this out -def LH16 : SDNodeXFormgetValue(); - int64_t y = l / IMM_MULT; - if (l % IMM_MULT > IMM_HIGH) - ++y; - return getI64Imm(y); -}]>; + val32 <= IMM_FULLHIGH); +// val32 >= IMM_FULLLOW + IMM_LOW * IMM_MULT); //Always True +}], SExt32>; def : Pat<(i64 immConst2Part:$imm), (LDA (LL16 immConst2Part:$imm), (LDAH (LH16 immConst2Part:$imm), R31))>; @@ -830,10 +824,10 @@ (LDA immSExt16:$imm, R31)>; def : Pat<(i64 immSExt16int:$imm), - (ZAPNOTi (LDA (SExtInt immSExt16int:$imm), R31), 15)>; + (ZAPNOTi (LDA (SExt16 immSExt16int:$imm), R31), 15)>; def : Pat<(i64 immConst2PartInt:$imm), - (ZAPNOTi (LDA (LL16 (SExtInt immConst2PartInt:$imm)), - (LDAH (LH16 (SExtInt immConst2PartInt:$imm)), R31)), 15)>; + (ZAPNOTi (LDA (LL16 (SExt16 immConst2PartInt:$imm)), + (LDAH (LH16 (SExt16 immConst2PartInt:$imm)), R31)), 15)>; //TODO: I want to just define these like this! From alenhar2 at cs.uiuc.edu Sun Jan 1 16:16:55 2006 From: alenhar2 at cs.uiuc.edu (Andrew Lenharth) Date: Sun, 1 Jan 2006 16:16:55 -0600 Subject: [llvm-commits] CVS: llvm/lib/Target/TargetSelectionDAG.td Message-ID: <200601012216.QAA02050@zion.cs.uiuc.edu> Changes in directory llvm/lib/Target: TargetSelectionDAG.td updated: 1.37 -> 1.38 --- Log message: Add support for brcond --- Diffs of the changes: (+5 -0) TargetSelectionDAG.td | 5 +++++ 1 files changed, 5 insertions(+) Index: llvm/lib/Target/TargetSelectionDAG.td diff -u llvm/lib/Target/TargetSelectionDAG.td:1.37 llvm/lib/Target/TargetSelectionDAG.td:1.38 --- llvm/lib/Target/TargetSelectionDAG.td:1.37 Sat Dec 24 17:36:59 2005 +++ llvm/lib/Target/TargetSelectionDAG.td Sun Jan 1 16:16:43 2006 @@ -131,6 +131,10 @@ SDTCisVT<0, OtherVT> ]>; +def SDTBrcond : SDTypeProfile<0, 2, [ // brcond + SDTCisInt<0>, SDTCisVT<1, OtherVT> +]>; + def SDTRet : SDTypeProfile<0, 0, []>; // ret def SDTReadPort : SDTypeProfile<1, 1, [ // readport @@ -260,6 +264,7 @@ def select : SDNode<"ISD::SELECT" , SDTSelect>; def selectcc : SDNode<"ISD::SELECT_CC" , SDTSelectCC>; +def brcond : SDNode<"ISD::BRCOND" , SDTBrcond, [SDNPHasChain]>; def br : SDNode<"ISD::BR" , SDTBr, [SDNPHasChain]>; def ret : SDNode<"ISD::RET" , SDTRet, [SDNPHasChain]>; From lattner at cs.uiuc.edu Sun Jan 1 16:20:43 2006 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Sun, 1 Jan 2006 16:20:43 -0600 Subject: [llvm-commits] CVS: llvm/lib/Target/Alpha/AlphaJITInfo.cpp Message-ID: <200601012220.QAA02467@zion.cs.uiuc.edu> Changes in directory llvm/lib/Target/Alpha: AlphaJITInfo.cpp updated: 1.7 -> 1.8 --- Log message: Remove a 'using namespace std'. --- Diffs of the changes: (+4 -5) AlphaJITInfo.cpp | 9 ++++----- 1 files changed, 4 insertions(+), 5 deletions(-) Index: llvm/lib/Target/Alpha/AlphaJITInfo.cpp diff -u llvm/lib/Target/Alpha/AlphaJITInfo.cpp:1.7 llvm/lib/Target/Alpha/AlphaJITInfo.cpp:1.8 --- llvm/lib/Target/Alpha/AlphaJITInfo.cpp:1.7 Thu Aug 4 10:32:36 2005 +++ llvm/lib/Target/Alpha/AlphaJITInfo.cpp Sun Jan 1 16:20:31 2006 @@ -20,7 +20,6 @@ #include #include #include -using namespace std; using namespace llvm; #define BUILD_OFormatI(Op, RA, LIT, FUN, RC) \ @@ -240,7 +239,7 @@ //because gpdist are paired and relative to the pc of the first inst, //we need to have some state - static map, void*> gpdistmap; + static std::map, void*> gpdistmap; for (unsigned i = 0; i != NumRelocs; ++i, ++MR) { unsigned *RelocPos = (unsigned*)Function + MR->getMachineCodeOffset()/4; @@ -276,13 +275,13 @@ idx = getUpper16(idx); DEBUG(std::cerr << "LDAH: " << idx << "\n"); //add the relocation to the map - gpdistmap[make_pair(Function, MR->getConstantVal())] = RelocPos; + gpdistmap[std::make_pair(Function, MR->getConstantVal())] = RelocPos; break; case 0x08: //LDA - assert(gpdistmap[make_pair(Function, MR->getConstantVal())] && + assert(gpdistmap[std::make_pair(Function, MR->getConstantVal())] && "LDAg without seeing LDAHg"); idx = &GOTBase[GOToffset * 8] - - (unsigned char*)gpdistmap[make_pair(Function, MR->getConstantVal())]; + (unsigned char*)gpdistmap[std::make_pair(Function, MR->getConstantVal())]; idx = getLower16(idx); DEBUG(std::cerr << "LDA: " << idx << "\n"); break;