-Unfortunately, the process of extending the code generator to support a new node
-is not extremely well documented. As such, it is often helpful to look at other
-intrinsics (e.g. llvm.ctpop) to see how they are recognized and turned
-into a node by SelectionDAGISel.cpp, legalized by
-LegalizeDAG.cpp, then finally emitted by the various code generators.
-
+
+
+
+
As with intrinsics, adding a new SelectionDAG node to LLVM is much easier
+than adding a new instruction. New nodes are often added to help represent
+instructions common to many targets. These nodes often map to an LLVM
+instruction (add, sub) or intrinsic (byteswap, population count). In other
+cases, new nodes have been added to allow many targets to perform a common task
+(converting between floating point and integer representation) or capture more
+complicated behavior in a single node (rotate).
+
+
+- include/llvm/CodeGen/SelectionDAGNodes.h:
+ Add an enum value for the new SelectionDAG node.
+- lib/CodeGen/SelectionDAG/SelectionDAG.cpp:
+ Add code to print the node to getOperationName. If your new node
+ can be evaluated at compile time when given constant arguments (such as an
+ add of a constant with another constant), find the getNode method
+ that takes the appropriate number of arguments, and add a case for your node
+ to the switch statement that performs constant folding for nodes that take
+ the same number of arguments as your new node.
+- lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:
+ Add code to legalize,
+ promote, and expand the node as necessary. At a minimum, you will need
+ to add a case statement for your node in LegalizeOp which calls
+ LegalizeOp on the node's operands, and returns a new node if any of the
+ operands changed as a result of being legalized. It is likely that not all
+ targets supported by the SelectionDAG framework will natively support the
+ new node. In this case, you must also add code in your node's case
+ statement in LegalizeOp to Expand your node into simpler, legal
+ operations. The case for ISD::UREM for expanding a remainder into a
+ multiply and a subtract is a good example.
+- lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:
+ If targets may support the new node being added only at certain sizes, you
+ will also need to add code to your node's case statement in
+ LegalizeOp to Promote your node's operands to a larger size, and
+ perform the correct operation. You will also need to add code to
+ PromoteOp to do this as well. For a good example, see ISD::BSWAP,
+ which promotes its operand to a wider size, performs the byteswap, and then
+ shifts the correct bytes right to emulate the narrower byteswap in the
+ wider type.
+- lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:
+ Add a case for your node in ExpandOp to teach the legalizer how to
+ perform the action represented by the new node on a value that has been
+ split into high and low halves. This case will be used to support your
+ node with a 64 bit operand on a 32 bit target.
+- lib/CodeGen/SelectionDAG/DAGCombiner.cpp:
+ If your node can be combined with itself, or other existing nodes in a
+ peephole-like fashion, add a visit function for it, and call that function
+ from . There are several good examples for simple combines you
+ can do; visitFABS and visitSRL are good starting places.
+
+- lib/Target/PowerPC/PPCISelLowering.cpp:
+ Each target has an implementation of the TargetLowering class,
+ usually in its own file (although some targets include it in the same
+ file as the DAGToDAGISel). The default behavior for a target is to
+ assume that your new node is legal for all types that are legal for
+ that target. If this target does not natively support your node, then
+ tell the target to either Promote it (if it is supported at a larger
+ type) or Expand it. This will cause the code you wrote in
+ LegalizeOp above to decompose your new node into other legal
+ nodes for this target.
+- lib/Target/TargetSelectionDAG.td:
+ Most current targets supported by LLVM generate code using the DAGToDAG
+ method, where SelectionDAG nodes are pattern matched to target-specific
+ nodes, which represent individual instructions. In order for the targets
+ to match an instruction to your new node, you must add a def for that node
+ to the list in this file, with the appropriate type constraints. Look at
+ add, bswap, and fadd for examples.
+- lib/Target/PowerPC/PPCInstrInfo.td:
+ Each target has a tablegen file that describes the target's instruction
+ set. For targets that use the DAGToDAG instruction selection framework,
+ add a pattern for your new node that uses one or more target nodes.
+ Documentation for this is a bit sparse right now, but there are several
+ decent examples. See the patterns for rotl in
+ PPCInstrInfo.td.
+- TODO: document complex patterns.
+- llvm/test/Regression/CodeGen/*: Add test cases for your new node
+ to the test suite. llvm/test/Regression/CodeGen/X86/bswap.ll is
+ a good example.
+