From lattner at cs.uiuc.edu Mon Mar 13 00:08:50 2006 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Mon, 13 Mar 2006 00:08:50 -0600 Subject: [llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp Message-ID: <200603130608.AAA13955@zion.cs.uiuc.edu> Changes in directory llvm/lib/CodeGen/SelectionDAG: LegalizeDAG.cpp updated: 1.313 -> 1.314 --- Log message: For targets with FABS/FNEG support, lower copysign to an integer load, a select and FABS/FNEG. This speeds up a trivial (aka stupid) copysign benchmark I wrote from 6.73s to 2.64s, woo. --- Diffs of the changes: (+25 -2) LegalizeDAG.cpp | 27 +++++++++++++++++++++++++-- 1 files changed, 25 insertions(+), 2 deletions(-) Index: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp diff -u llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.313 llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.314 --- llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.313 Tue Mar 7 22:39:05 2006 +++ llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp Mon Mar 13 00:08:38 2006 @@ -1795,10 +1795,33 @@ case TargetLowering::Custom: Tmp1 = TLI.LowerOperation(Result, DAG); if (Tmp1.Val) Result = Tmp1; - break; + break; case TargetLowering::Legal: break; case TargetLowering::Expand: - // Floating point mod -> fmod libcall. + // If this target supports fabs/fneg natively, do this efficiently. + if (TLI.isOperationLegal(ISD::FABS, Tmp1.getValueType()) && + TLI.isOperationLegal(ISD::FNEG, Tmp1.getValueType())) { + // Get the sign bit of the RHS. + MVT::ValueType IVT = + Tmp2.getValueType() == MVT::f32 ? MVT::i32 : MVT::i64; + SDOperand SignBit = DAG.getNode(ISD::BIT_CONVERT, IVT, Tmp2); + SignBit = DAG.getSetCC(TLI.getSetCCResultTy(), + SignBit, DAG.getConstant(0, IVT), ISD::SETLT); + // Get the absolute value of the result. + SDOperand AbsVal = DAG.getNode(ISD::FABS, Tmp1.getValueType(), Tmp1); + // Select between the nabs and abs value based on the sign bit of + // the input. + Result = DAG.getNode(ISD::SELECT, AbsVal.getValueType(), SignBit, + DAG.getNode(ISD::FNEG, AbsVal.getValueType(), + AbsVal), + AbsVal); + Result = LegalizeOp(Result); + break; + } + + // Otherwise, do bitwise ops! + + // copysign -> copysignf/copysign libcall. const char *FnName; if (Node->getValueType(0) == MVT::f32) { FnName = "copysignf"; From lattner at cs.uiuc.edu Mon Mar 13 00:26:38 2006 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Mon, 13 Mar 2006 00:26:38 -0600 Subject: [llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Message-ID: <200603130626.AAA14039@zion.cs.uiuc.edu> Changes in directory llvm/lib/CodeGen/SelectionDAG: DAGCombiner.cpp updated: 1.123 -> 1.124 --- Log message: add a couple of missing folds --- Diffs of the changes: (+12 -0) DAGCombiner.cpp | 12 ++++++++++++ 1 files changed, 12 insertions(+) Index: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp diff -u llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.123 llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.124 --- llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.123 Sun Mar 5 13:53:55 2006 +++ llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Mon Mar 13 00:26:26 2006 @@ -2102,6 +2102,18 @@ // fold (fp_round c1fp) -> c1fp if (N0CFP) return DAG.getNode(ISD::FP_ROUND, VT, N0); + + // fold (fp_round (fp_extend x)) -> x + if (N0.getOpcode() == ISD::FP_EXTEND && VT == N0.getOperand(0).getValueType()) + return N0.getOperand(0); + + // fold (fp_round (copysign X, Y)) -> (copysign (fp_round X), Y) + if (N0.getOpcode() == ISD::FCOPYSIGN && N0.Val->hasOneUse()) { + SDOperand Tmp = DAG.getNode(ISD::FP_ROUND, VT, N0.getOperand(0)); + AddToWorkList(Tmp.Val); + return DAG.getNode(ISD::FCOPYSIGN, VT, Tmp, N0.getOperand(1)); + } + return SDOperand(); } From lattner at cs.uiuc.edu Mon Mar 13 00:42:28 2006 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Mon, 13 Mar 2006 00:42:28 -0600 Subject: [llvm-commits] CVS: llvm/lib/Target/TargetLowering.cpp Message-ID: <200603130642.AAA14126@zion.cs.uiuc.edu> Changes in directory llvm/lib/Target: TargetLowering.cpp updated: 1.44 -> 1.45 --- Log message: I can't convince myself that this is safe, remove the recursive call. --- Diffs of the changes: (+2 -18) TargetLowering.cpp | 20 ++------------------ 1 files changed, 2 insertions(+), 18 deletions(-) Index: llvm/lib/Target/TargetLowering.cpp diff -u llvm/lib/Target/TargetLowering.cpp:1.44 llvm/lib/Target/TargetLowering.cpp:1.45 --- llvm/lib/Target/TargetLowering.cpp:1.44 Sun Mar 5 13:52:57 2006 +++ llvm/lib/Target/TargetLowering.cpp Mon Mar 13 00:42:16 2006 @@ -565,23 +565,6 @@ break; } case ISD::ADD: - if (ConstantSDNode *AA = dyn_cast(Op.getOperand(1))) { - if (SimplifyDemandedBits(Op.getOperand(0), DemandedMask, KnownZero, - KnownOne, TLO, Depth+1)) - return true; - // Compute the KnownOne/KnownZero masks for the constant, so we can set - // KnownZero appropriately if we're adding a constant that has all low - // bits cleared. - ComputeMaskedBits(Op.getOperand(1), - MVT::getIntVTBitMask(Op.getValueType()), - KnownZero2, KnownOne2, Depth+1); - - uint64_t KnownZeroOut = std::min(CountTrailingZeros_64(~KnownZero), - CountTrailingZeros_64(~KnownZero2)); - KnownZero = (1ULL << KnownZeroOut) - 1; - KnownOne = 0; - } - break; case ISD::SUB: // Just use ComputeMaskedBits to compute output bits, there are no // simplifications that can be done here, and sub always demands all input @@ -843,7 +826,8 @@ assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); // Output known-0 bits are known if clear or set in both the low clear bits - // common to both LHS & RHS; + // common to both LHS & RHS. For example, 8+(X<<3) is known to have the + // low 3 bits clear. uint64_t KnownZeroOut = std::min(CountTrailingZeros_64(~KnownZero), CountTrailingZeros_64(~KnownZero2)); From lattner at cs.uiuc.edu Mon Mar 13 00:50:59 2006 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Mon, 13 Mar 2006 00:50:59 -0600 Subject: [llvm-commits] CVS: llvm/test/Regression/CodeGen/PowerPC/and_add.ll Message-ID: <200603130650.AAA14284@zion.cs.uiuc.edu> Changes in directory llvm/test/Regression/CodeGen/PowerPC: and_add.ll added (r1.1) --- Log message: new testcase --- Diffs of the changes: (+11 -0) and_add.ll | 11 +++++++++++ 1 files changed, 11 insertions(+) Index: llvm/test/Regression/CodeGen/PowerPC/and_add.ll diff -c /dev/null llvm/test/Regression/CodeGen/PowerPC/and_add.ll:1.1 *** /dev/null Mon Mar 13 00:50:57 2006 --- llvm/test/Regression/CodeGen/PowerPC/and_add.ll Mon Mar 13 00:50:47 2006 *************** *** 0 **** --- 1,11 ---- + ; RUN: llvm-as < %s | llc -march=ppc32 | grep slwi && + ; RUN: llvm-as < %s | llc -march=ppc32 | not grep addi && + ; RUN: llvm-as < %s | llc -march=ppc32 | not grep rlwinm + + int %test(int %A) { + %B = mul int %A, 8 ;; shift + %C = add int %B, 7 ;; dead, no demanded bits. + %D = and int %C, -8 ;; dead once add is gone. + ret int %D + } + From lattner at cs.uiuc.edu Mon Mar 13 00:51:42 2006 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Mon, 13 Mar 2006 00:51:42 -0600 Subject: [llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Message-ID: <200603130651.AAA14294@zion.cs.uiuc.edu> Changes in directory llvm/lib/CodeGen/SelectionDAG: DAGCombiner.cpp updated: 1.124 -> 1.125 --- Log message: Fold X+Y -> X|Y when safe. This implements: Regression/CodeGen/PowerPC/and_add.ll a case that occurs with dynamic allocas of constant size. --- Diffs of the changes: (+19 -1) DAGCombiner.cpp | 20 +++++++++++++++++++- 1 files changed, 19 insertions(+), 1 deletion(-) Index: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp diff -u llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.124 llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.125 --- llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.124 Mon Mar 13 00:26:26 2006 +++ llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Mon Mar 13 00:51:27 2006 @@ -714,9 +714,27 @@ // fold (A+(B-A)) -> B if (N1.getOpcode() == ISD::SUB && N0 == N1.getOperand(1)) return N1.getOperand(0); - // + if (!MVT::isVector(VT) && SimplifyDemandedBits(SDOperand(N, 0))) return SDOperand(); + + // fold (a+b) -> (a|b) iff a and b share no bits. + if (MVT::isInteger(VT) && !MVT::isVector(VT)) { + uint64_t LHSZero, LHSOne; + uint64_t RHSZero, RHSOne; + uint64_t Mask = MVT::getIntVTBitMask(VT); + TLI.ComputeMaskedBits(N0, Mask, LHSZero, LHSOne); + if (LHSZero) { + TLI.ComputeMaskedBits(N1, Mask, RHSZero, RHSOne); + + // If all possibly-set bits on the LHS are clear on the RHS, return an OR. + // If all possibly-set bits on the RHS are clear on the LHS, return an OR. + if ((RHSZero & (~LHSZero & Mask)) == (~LHSZero & Mask) || + (LHSZero & (~RHSZero & Mask)) == (~RHSZero & Mask)) + return DAG.getNode(ISD::OR, VT, N0, N1); + } + } + return SDOperand(); } From lattner at cs.uiuc.edu Mon Mar 13 00:52:34 2006 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Mon, 13 Mar 2006 00:52:34 -0600 Subject: [llvm-commits] CVS: llvm/lib/Target/README.txt Message-ID: <200603130652.AAA14354@zion.cs.uiuc.edu> Changes in directory llvm/lib/Target: README.txt updated: 1.17 -> 1.18 --- Log message: remove two implemented items --- Diffs of the changes: (+0 -22) README.txt | 22 ---------------------- 1 files changed, 22 deletions(-) Index: llvm/lib/Target/README.txt diff -u llvm/lib/Target/README.txt:1.17 llvm/lib/Target/README.txt:1.18 --- llvm/lib/Target/README.txt:1.17 Sat Mar 11 14:20:40 2006 +++ llvm/lib/Target/README.txt Mon Mar 13 00:52:22 2006 @@ -56,20 +56,6 @@ //===---------------------------------------------------------------------===// -DAG combine this into mul A, 8: - -int %test(int %A) { - %B = mul int %A, 8 ;; shift - %C = add int %B, 7 ;; dead, no demanded bits. - %D = and int %C, -8 ;; dead once add is gone. - ret int %D -} - -This sort of thing occurs in the alloca lowering code and other places that -are generating alignment of an already aligned value. - -//===---------------------------------------------------------------------===// - Turn this into a signed shift right in instcombine: int f(unsigned x) { @@ -81,14 +67,6 @@ //===---------------------------------------------------------------------===// -We should reassociate: -int f(int a, int b){ return a * a + 2 * a * b + b * b; } -into: -int f(int a, int b) { return a * (a + 2 * b) + b * b; } -to eliminate a multiply. - -//===---------------------------------------------------------------------===// - On targets with expensive 64-bit multiply, we could LSR this: for (i = ...; ++i) { From jlaskey at apple.com Mon Mar 13 07:07:56 2006 From: jlaskey at apple.com (Jim Laskey) Date: Mon, 13 Mar 2006 07:07:56 -0600 Subject: [llvm-commits] CVS: llvm/lib/Target/CBackend/Writer.cpp Message-ID: <200603131307.HAA15666@zion.cs.uiuc.edu> Changes in directory llvm/lib/Target/CBackend: Writer.cpp updated: 1.255 -> 1.256 --- Log message: Handle the removal of the debug chain. --- Diffs of the changes: (+2 -2) Writer.cpp | 4 ++-- 1 files changed, 2 insertions(+), 2 deletions(-) Index: llvm/lib/Target/CBackend/Writer.cpp diff -u llvm/lib/Target/CBackend/Writer.cpp:1.255 llvm/lib/Target/CBackend/Writer.cpp:1.256 --- llvm/lib/Target/CBackend/Writer.cpp:1.255 Wed Mar 8 13:31:15 2006 +++ llvm/lib/Target/CBackend/Writer.cpp Mon Mar 13 07:07:37 2006 @@ -1691,8 +1691,8 @@ case Intrinsic::dbg_stoppoint: { // If we use writeOperand directly we get a "u" suffix which is rejected // by gcc. - ConstantUInt *SI = cast(I.getOperand(2)); - GlobalVariable *GV = cast(I.getOperand(4)); + ConstantUInt *SI = cast(I.getOperand(1)); + GlobalVariable *GV = cast(I.getOperand(3)); ConstantStruct *CS = cast(GV->getInitializer()); std::string FileName = CS->getOperand(4)->getStringValue(); std::string Directory = CS->getOperand(5)->getStringValue(); From jlaskey at apple.com Mon Mar 13 07:07:56 2006 From: jlaskey at apple.com (Jim Laskey) Date: Mon, 13 Mar 2006 07:07:56 -0600 Subject: [llvm-commits] CVS: llvm/lib/CodeGen/IntrinsicLowering.cpp Message-ID: <200603131307.HAA15664@zion.cs.uiuc.edu> Changes in directory llvm/lib/CodeGen: IntrinsicLowering.cpp updated: 1.41 -> 1.42 --- Log message: Handle the removal of the debug chain. --- Diffs of the changes: (+0 -2) IntrinsicLowering.cpp | 2 -- 1 files changed, 2 deletions(-) Index: llvm/lib/CodeGen/IntrinsicLowering.cpp diff -u llvm/lib/CodeGen/IntrinsicLowering.cpp:1.41 llvm/lib/CodeGen/IntrinsicLowering.cpp:1.42 --- llvm/lib/CodeGen/IntrinsicLowering.cpp:1.41 Thu Mar 9 14:02:42 2006 +++ llvm/lib/CodeGen/IntrinsicLowering.cpp Mon Mar 13 07:07:37 2006 @@ -403,8 +403,6 @@ case Intrinsic::dbg_region_start: case Intrinsic::dbg_region_end: case Intrinsic::dbg_func_start: - if (CI->getType() != Type::VoidTy) - CI->replaceAllUsesWith(Constant::getNullValue(CI->getType())); break; // Simply strip out debugging intrinsics case Intrinsic::memcpy_i32: From jlaskey at apple.com Mon Mar 13 07:07:56 2006 From: jlaskey at apple.com (Jim Laskey) Date: Mon, 13 Mar 2006 07:07:56 -0600 Subject: [llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp Message-ID: <200603131307.HAA15674@zion.cs.uiuc.edu> Changes in directory llvm/lib/CodeGen/SelectionDAG: SelectionDAGISel.cpp updated: 1.187 -> 1.188 --- Log message: Handle the removal of the debug chain. --- Diffs of the changes: (+4 -4) SelectionDAGISel.cpp | 8 ++++---- 1 files changed, 4 insertions(+), 4 deletions(-) Index: llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp diff -u llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.187 llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.188 --- llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.187 Fri Mar 10 17:52:03 2006 +++ llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp Mon Mar 13 07:07:37 2006 @@ -966,19 +966,19 @@ case Intrinsic::dbg_stoppoint: { MachineDebugInfo *DebugInfo = DAG.getMachineDebugInfo(); - if (DebugInfo && DebugInfo->Verify(I.getOperand(4))) { + if (DebugInfo && DebugInfo->Verify(I.getOperand(3))) { std::vector Ops; // Input Chain Ops.push_back(getRoot()); // line number - Ops.push_back(getValue(I.getOperand(2))); + Ops.push_back(getValue(I.getOperand(1))); // column - Ops.push_back(getValue(I.getOperand(3))); + Ops.push_back(getValue(I.getOperand(2))); - DebugInfoDesc *DD = DebugInfo->getDescFor(I.getOperand(4)); + DebugInfoDesc *DD = DebugInfo->getDescFor(I.getOperand(3)); assert(DD && "Not a debug information descriptor"); CompileUnitDesc *CompileUnit = dyn_cast(DD); assert(CompileUnit && "Not a compile unit"); From jlaskey at apple.com Mon Mar 13 07:07:56 2006 From: jlaskey at apple.com (Jim Laskey) Date: Mon, 13 Mar 2006 07:07:56 -0600 Subject: [llvm-commits] CVS: llvm/lib/VMCore/AutoUpgrade.cpp Message-ID: <200603131307.HAA15682@zion.cs.uiuc.edu> Changes in directory llvm/lib/VMCore: AutoUpgrade.cpp updated: 1.11 -> 1.12 --- Log message: Handle the removal of the debug chain. --- Diffs of the changes: (+99 -47) AutoUpgrade.cpp | 146 +++++++++++++++++++++++++++++++++++++------------------- 1 files changed, 99 insertions(+), 47 deletions(-) Index: llvm/lib/VMCore/AutoUpgrade.cpp diff -u llvm/lib/VMCore/AutoUpgrade.cpp:1.11 llvm/lib/VMCore/AutoUpgrade.cpp:1.12 --- llvm/lib/VMCore/AutoUpgrade.cpp:1.11 Thu Mar 9 12:42:10 2006 +++ llvm/lib/VMCore/AutoUpgrade.cpp Mon Mar 13 07:07:37 2006 @@ -12,6 +12,7 @@ //===----------------------------------------------------------------------===// #include "llvm/Assembly/AutoUpgrade.h" +#include "llvm/Constants.h" #include "llvm/DerivedTypes.h" #include "llvm/Function.h" #include "llvm/Module.h" @@ -73,6 +74,31 @@ if (Name == "llvm.ctpop" || Name == "llvm.ctlz" || Name == "llvm.cttz") return getUpgradedUnaryFn(F); break; + case 'd': + if (Name == "llvm.dbg.stoppoint") { + if (F->getReturnType() != Type::VoidTy) { + return M->getOrInsertFunction(Name, Type::VoidTy, + Type::UIntTy, + Type::UIntTy, + F->getFunctionType()->getParamType(3), + NULL); + } + } else if (Name == "llvm.dbg.func.start") { + if (F->getReturnType() != Type::VoidTy) { + return M->getOrInsertFunction(Name, Type::VoidTy, + F->getFunctionType()->getParamType(0), + NULL); + } + } else if (Name == "llvm.dbg.region.start") { + if (F->getReturnType() != Type::VoidTy) { + return M->getOrInsertFunction(Name, Type::VoidTy, NULL); + } + } else if (Name == "llvm.dbg.region.end") { + if (F->getReturnType() != Type::VoidTy) { + return M->getOrInsertFunction(Name, Type::VoidTy, NULL); + } + } + break; case 'i': if (Name == "llvm.isunordered" && F->arg_begin() != F->arg_end()) { if (F->arg_begin()->getType() == Type::FloatTy) @@ -106,6 +132,29 @@ return 0; } +// Occasionally upgraded function call site arguments need to be permutated to +// some new order. The result of getArgumentPermutation is an array of size +// F->getFunctionType()getNumParams() indicating the new operand order. A value +// of zero in the array indicates replacing with UndefValue for the arg type. +// NULL is returned if there is no permutation. It's assumed that the function +// name is in the form "llvm.?????" +static unsigned *getArgumentPermutation(Function* F) { + // Get the Function's name. + const std::string& Name = F->getName(); + switch (Name[5]) { + case 'd': + if (Name == "llvm.dbg.stoppoint") { + static unsigned Permutation[] = { 2, 3, 4 }; + assert(F->getFunctionType()->getNumParams() == + (sizeof(Permutation) / sizeof(unsigned)) && + "Permutation is wrong length"); + return Permutation; + } + break; + } + return NULL; +} + // UpgradeIntrinsicFunction - Convert overloaded intrinsic function names to // their non-overloaded variants by appending the appropriate suffix based on // the argument types. @@ -157,72 +206,75 @@ return result; } -// UpgradeIntrinsicCall - In the BC reader, change a call to some intrinsic to -// be a called to the specified intrinsic. We expect the callees to have the -// same number of arguments, but their types may be different. +// UpgradeIntrinsicCall - In the BC reader, change a call to an intrinsic to be +// a call to an upgraded intrinsic. We may have to permute the order or promote +// some arguments with a cast. void llvm::UpgradeIntrinsicCall(CallInst *CI, Function *NewFn) { Function *F = CI->getCalledFunction(); const FunctionType *NewFnTy = NewFn->getFunctionType(); std::vector Oprnds; - for (unsigned i = 1, e = CI->getNumOperands(); i != e; ++i) { - Value *V = CI->getOperand(i); - if (V->getType() != NewFnTy->getParamType(i-1)) - V = new CastInst(V, NewFnTy->getParamType(i-1), V->getName(), CI); - Oprnds.push_back(V); + + unsigned *Permutation = getArgumentPermutation(NewFn); + unsigned N = NewFnTy->getNumParams(); + + if (Permutation) { + for (unsigned i = 0; i != N; ++i) { + unsigned p = Permutation[i]; + + if (p) { + Value *V = CI->getOperand(p); + if (V->getType() != NewFnTy->getParamType(i)) + V = new CastInst(V, NewFnTy->getParamType(i), V->getName(), CI); + Oprnds.push_back(V); + } else + Oprnds.push_back(UndefValue::get(NewFnTy->getParamType(i))); + } + } else { + assert(N == (CI->getNumOperands() - 1) && + "Upgraded function needs permutation"); + for (unsigned i = 0; i != N; ++i) { + Value *V = CI->getOperand(i + 1); + if (V->getType() != NewFnTy->getParamType(i)) + V = new CastInst(V, NewFnTy->getParamType(i), V->getName(), CI); + Oprnds.push_back(V); + } } - CallInst *NewCI = new CallInst(NewFn, Oprnds, CI->getName(), CI); + + bool NewIsVoid = NewFn->getReturnType() == Type::VoidTy; + + CallInst *NewCI = new CallInst(NewFn, Oprnds, + NewIsVoid ? "" : CI->getName(), + CI); NewCI->setTailCall(CI->isTailCall()); NewCI->setCallingConv(CI->getCallingConv()); if (!CI->use_empty()) { - Instruction *RetVal = NewCI; - if (F->getReturnType() != NewFn->getReturnType()) { - RetVal = new CastInst(NewCI, NewFn->getReturnType(), - NewCI->getName(), CI); - NewCI->moveBefore(RetVal); + if (NewIsVoid) { + CI->replaceAllUsesWith(UndefValue::get(CI->getType())); + } else { + Instruction *RetVal = NewCI; + + if (F->getReturnType() != NewFn->getReturnType()) { + RetVal = new CastInst(NewCI, NewFn->getReturnType(), + NewCI->getName(), CI); + NewCI->moveBefore(RetVal); + } + + CI->replaceAllUsesWith(RetVal); } - CI->replaceAllUsesWith(RetVal); } CI->eraseFromParent(); } bool llvm::UpgradeCallsToIntrinsic(Function* F) { - if (Function* newF = UpgradeIntrinsicFunction(F)) { + if (Function* NewFn = UpgradeIntrinsicFunction(F)) { for (Value::use_iterator UI = F->use_begin(), UE = F->use_end(); UI != UE; ) { - if (CallInst* CI = dyn_cast(*UI++)) { - std::vector Oprnds; - User::op_iterator OI = CI->op_begin(); - ++OI; - for (User::op_iterator OE = CI->op_end(); OI != OE; ++OI) { - const Type* opTy = OI->get()->getType(); - if (opTy->isSigned()) { - Oprnds.push_back( - new CastInst(OI->get(),opTy->getUnsignedVersion(), - "autoupgrade_cast",CI)); - } else { - Oprnds.push_back(*OI); - } - } - CallInst* newCI = new CallInst(newF, Oprnds, - CI->hasName() ? "autoupcall" : "", CI); - newCI->setTailCall(CI->isTailCall()); - newCI->setCallingConv(CI->getCallingConv()); - if (CI->use_empty()) { - // noop - } else if (CI->getType() != newCI->getType()) { - CastInst *final = new CastInst(newCI, CI->getType(), - "autoupgrade_uncast", newCI); - newCI->moveBefore(final); - CI->replaceAllUsesWith(final); - } else { - CI->replaceAllUsesWith(newCI); - } - CI->eraseFromParent(); - } + if (CallInst* CI = dyn_cast(*UI++)) + UpgradeIntrinsicCall(CI, NewFn); } - if (newF != F) + if (NewFn != F) F->eraseFromParent(); return true; } From jlaskey at apple.com Mon Mar 13 07:07:56 2006 From: jlaskey at apple.com (Jim Laskey) Date: Mon, 13 Mar 2006 07:07:56 -0600 Subject: [llvm-commits] CVS: llvm/include/llvm/Intrinsics.td Message-ID: <200603131307.HAA15676@zion.cs.uiuc.edu> Changes in directory llvm/include/llvm: Intrinsics.td updated: 1.5 -> 1.6 --- Log message: Handle the removal of the debug chain. --- Diffs of the changes: (+4 -4) Intrinsics.td | 8 ++++---- 1 files changed, 4 insertions(+), 4 deletions(-) Index: llvm/include/llvm/Intrinsics.td diff -u llvm/include/llvm/Intrinsics.td:1.5 llvm/include/llvm/Intrinsics.td:1.6 --- llvm/include/llvm/Intrinsics.td:1.5 Sat Mar 11 18:04:28 2006 +++ llvm/include/llvm/Intrinsics.td Mon Mar 13 07:07:37 2006 @@ -181,11 +181,11 @@ //===------------------------ Debugger Intrinsics -------------------------===// // -def int_dbg_stoppoint : Intrinsic<[llvm_anchor_ty, llvm_anchor_ty, +def int_dbg_stoppoint : Intrinsic<[llvm_void_ty, llvm_uint_ty, llvm_uint_ty, llvm_descriptor_ty]>; -def int_dbg_region_start : Intrinsic<[llvm_anchor_ty, llvm_anchor_ty]>; -def int_dbg_region_end : Intrinsic<[llvm_anchor_ty, llvm_anchor_ty]>; -def int_dbg_func_start : Intrinsic<[llvm_anchor_ty, llvm_descriptor_ty]>; +def int_dbg_region_start : Intrinsic<[llvm_void_ty]>; +def int_dbg_region_end : Intrinsic<[llvm_void_ty]>; +def int_dbg_func_start : Intrinsic<[llvm_void_ty, llvm_descriptor_ty]>; // dbg_declare, // Declare a local object From jlaskey at apple.com Mon Mar 13 07:07:56 2006 From: jlaskey at apple.com (Jim Laskey) Date: Mon, 13 Mar 2006 07:07:56 -0600 Subject: [llvm-commits] CVS: llvm/lib/Debugger/ProgramInfo.cpp Message-ID: <200603131307.HAA15672@zion.cs.uiuc.edu> Changes in directory llvm/lib/Debugger: ProgramInfo.cpp updated: 1.13 -> 1.14 --- Log message: Handle the removal of the debug chain. --- Diffs of the changes: (+3 -3) ProgramInfo.cpp | 6 +++--- 1 files changed, 3 insertions(+), 3 deletions(-) Index: llvm/lib/Debugger/ProgramInfo.cpp diff -u llvm/lib/Debugger/ProgramInfo.cpp:1.13 llvm/lib/Debugger/ProgramInfo.cpp:1.14 --- llvm/lib/Debugger/ProgramInfo.cpp:1.13 Wed Mar 8 12:11:07 2006 +++ llvm/lib/Debugger/ProgramInfo.cpp Mon Mar 13 07:07:37 2006 @@ -63,11 +63,11 @@ if (F->getIntrinsicID() == Intrinsic::dbg_stoppoint) { unsigned CurLineNo = ~0, CurColNo = ~0; const GlobalVariable *CurDesc = 0; - if (const ConstantInt *C = dyn_cast(CI->getOperand(2))) + if (const ConstantInt *C = dyn_cast(CI->getOperand(1))) CurLineNo = C->getRawValue(); - if (const ConstantInt *C = dyn_cast(CI->getOperand(3))) + if (const ConstantInt *C = dyn_cast(CI->getOperand(2))) CurColNo = C->getRawValue(); - const Value *Op = CI->getOperand(4); + const Value *Op = CI->getOperand(3); if ((CurDesc = dyn_cast(Op)) && (LineNo < LastLineNo || From jlaskey at apple.com Mon Mar 13 07:07:56 2006 From: jlaskey at apple.com (Jim Laskey) Date: Mon, 13 Mar 2006 07:07:56 -0600 Subject: [llvm-commits] CVS: llvm/lib/Transforms/IPO/StripSymbols.cpp Message-ID: <200603131307.HAA15688@zion.cs.uiuc.edu> Changes in directory llvm/lib/Transforms/IPO: StripSymbols.cpp updated: 1.5 -> 1.6 --- Log message: Handle the removal of the debug chain. --- Diffs of the changes: (+1 -1) StripSymbols.cpp | 2 +- 1 files changed, 1 insertion(+), 1 deletion(-) Index: llvm/lib/Transforms/IPO/StripSymbols.cpp diff -u llvm/lib/Transforms/IPO/StripSymbols.cpp:1.5 llvm/lib/Transforms/IPO/StripSymbols.cpp:1.6 --- llvm/lib/Transforms/IPO/StripSymbols.cpp:1.5 Thu Mar 9 00:09:41 2006 +++ llvm/lib/Transforms/IPO/StripSymbols.cpp Mon Mar 13 07:07:37 2006 @@ -116,7 +116,7 @@ Value *RV = UndefValue::get(StopPoint->getFunctionType()->getReturnType()); while (!StopPoint->use_empty()) { CallInst *CI = cast(StopPoint->use_back()); - Value *Arg = CI->getOperand(4); + Value *Arg = CI->getOperand(3); CI->replaceAllUsesWith(RV); CI->eraseFromParent(); if (Arg->use_empty()) From jlaskey at apple.com Mon Mar 13 07:07:56 2006 From: jlaskey at apple.com (Jim Laskey) Date: Mon, 13 Mar 2006 07:07:56 -0600 Subject: [llvm-commits] CVS: llvm/lib/Bytecode/Reader/Reader.cpp Message-ID: <200603131307.HAA15680@zion.cs.uiuc.edu> Changes in directory llvm/lib/Bytecode/Reader: Reader.cpp updated: 1.189 -> 1.190 --- Log message: Handle the removal of the debug chain. --- Diffs of the changes: (+2 -2) Reader.cpp | 4 ++-- 1 files changed, 2 insertions(+), 2 deletions(-) Index: llvm/lib/Bytecode/Reader/Reader.cpp diff -u llvm/lib/Bytecode/Reader/Reader.cpp:1.189 llvm/lib/Bytecode/Reader/Reader.cpp:1.190 --- llvm/lib/Bytecode/Reader/Reader.cpp:1.189 Thu Mar 2 17:59:12 2006 +++ llvm/lib/Bytecode/Reader/Reader.cpp Mon Mar 13 07:07:37 2006 @@ -1861,8 +1861,8 @@ if (!upgradedFunctions.empty()) { for (Function::iterator BI = F->begin(), BE = F->end(); BI != BE; ++BI) for (BasicBlock::iterator II = BI->begin(), IE = BI->end(); - II != IE; ++II) - if (CallInst* CI = dyn_cast(II)) { + II != IE;) + if (CallInst* CI = dyn_cast(II++)) { std::map::iterator FI = upgradedFunctions.find(CI->getCalledFunction()); if (FI != upgradedFunctions.end()) From reid at x10sys.com Mon Mar 13 11:57:42 2006 From: reid at x10sys.com (Reid Spencer) Date: Mon, 13 Mar 2006 11:57:42 -0600 Subject: [llvm-commits] CVS: llvm/lib/VMCore/Makefile Message-ID: <200603131757.LAA29683@zion.cs.uiuc.edu> Changes in directory llvm/lib/VMCore: Makefile updated: 1.10 -> 1.11 --- Log message: Bring makefile back into compliance with standard by using $(Echo) instead of @echo --- Diffs of the changes: (+1 -1) Makefile | 2 +- 1 files changed, 1 insertion(+), 1 deletion(-) Index: llvm/lib/VMCore/Makefile diff -u llvm/lib/VMCore/Makefile:1.10 llvm/lib/VMCore/Makefile:1.11 --- llvm/lib/VMCore/Makefile:1.10 Thu Mar 9 14:29:41 2006 +++ llvm/lib/VMCore/Makefile Mon Mar 13 11:57:31 2006 @@ -19,6 +19,6 @@ include $(LEVEL)/Makefile.common $(LEVEL)/include/llvm/Intrinsics.gen: $(LEVEL)/include/llvm/Intrinsics.td $(TBLGEN) - @echo Building Intrinsics.gen from Intrinsics.td + $(Echo) Building Intrinsics.gen from Intrinsics.td $(Verb) $(TableGen) $< -o $@ -gen-intrinsic From lattner at cs.uiuc.edu Mon Mar 13 12:37:42 2006 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Mon, 13 Mar 2006 12:37:42 -0600 Subject: [llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Message-ID: <200603131837.MAA30034@zion.cs.uiuc.edu> Changes in directory llvm/lib/CodeGen/SelectionDAG: DAGCombiner.cpp updated: 1.125 -> 1.126 --- Log message: make sure dead token factor nodes are removed by the dag combiner. --- Diffs of the changes: (+1 -0) DAGCombiner.cpp | 1 + 1 files changed, 1 insertion(+) Index: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp diff -u llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.125 llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.126 --- llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.125 Mon Mar 13 00:51:27 2006 +++ llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Mon Mar 13 12:37:30 2006 @@ -665,6 +665,7 @@ for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) { SDOperand Op = N->getOperand(i); if (Op.getOpcode() == ISD::TokenFactor && Op.hasOneUse()) { + AddToWorkList(Op.Val); // Remove dead node. Changed = true; for (unsigned j = 0, e = Op.getNumOperands(); j != e; ++j) Ops.push_back(Op.getOperand(j)); From llvm at cs.uiuc.edu Mon Mar 13 15:22:55 2006 From: llvm at cs.uiuc.edu (LLVM) Date: Mon, 13 Mar 2006 15:22:55 -0600 Subject: [llvm-commits] CVS: llvm/runtime/GCCLibraries/libc/memory.c Message-ID: <200603132122.PAA31070@zion.cs.uiuc.edu> Changes in directory llvm/runtime/GCCLibraries/libc: memory.c (r1.5) removed --- Log message: Optimizing to calloc() to malloc() + memset() can be bad on some platforms. --- Diffs of the changes: (+0 -0) 0 files changed From lattner at cs.uiuc.edu Mon Mar 13 15:52:22 2006 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Mon, 13 Mar 2006 15:52:22 -0600 Subject: [llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp PPCInstrInfo.td PPCRegisterInfo.cpp PPCRegisterInfo.td Message-ID: <200603132152.PAA31255@zion.cs.uiuc.edu> Changes in directory llvm/lib/Target/PowerPC: PPCISelDAGToDAG.cpp updated: 1.164 -> 1.165 PPCInstrInfo.td updated: 1.181 -> 1.182 PPCRegisterInfo.cpp updated: 1.43 -> 1.44 PPCRegisterInfo.td updated: 1.29 -> 1.30 --- Log message: For functions that use vector registers, save VRSAVE, mark used registers, and update it on entry to each function, then restore it on exit. This compiles: void func(vfloat *a, vfloat *b, vfloat *c) { *a = *b * *c + *c; } to this: _func: mfspr r2, 256 oris r6, r2, 49152 mtspr 256: http://llvm.cs.uiuc.edu/PR256 , r6 lvx v0, 0, r5 lvx v1, 0, r4 vmaddfp v0, v1, v0, v0 stvx v0, 0, r3 mtspr 256: http://llvm.cs.uiuc.edu/PR256 , r2 blr GCC produces this (which has additional stack accesses): _func: mfspr r0,256 stw r0,-4(r1) oris r0,r0,0xc000 mtspr 256: http://llvm.cs.uiuc.edu/PR256 ,r0 lvx v0,0,r5 lvx v1,0,r4 lwz r12,-4(r1) vmaddfp v0,v0,v1,v0 stvx v0,0,r3 mtspr 256: http://llvm.cs.uiuc.edu/PR256 ,r12 blr --- Diffs of the changes: (+130 -10) PPCISelDAGToDAG.cpp | 59 +++++++++++++++++++++++++++++++++++++++++++++++++++- PPCInstrInfo.td | 26 ++++++++++++++++------ PPCRegisterInfo.cpp | 51 ++++++++++++++++++++++++++++++++++++++++++++ PPCRegisterInfo.td | 4 +-- 4 files changed, 130 insertions(+), 10 deletions(-) Index: llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp diff -u llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp:1.164 llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp:1.165 --- llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp:1.164 Sun Mar 12 03:13:49 2006 +++ llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp Mon Mar 13 15:52:10 2006 @@ -196,8 +196,65 @@ CodeGenMap.clear(); DAG.RemoveDeadNodes(); - // Emit machine code to BB. + // Emit machine code to BB. ScheduleAndEmitDAG(DAG); + + // Check to see if this function uses vector registers, which means we have to + // save and restore the VRSAVE register and update it with the regs we use. + // + // In this case, there will be virtual registers of vector type type created + // by the scheduler. Detect them now. + SSARegMap *RegMap = DAG.getMachineFunction().getSSARegMap(); + bool HasVectorVReg = false; + for (unsigned i = MRegisterInfo::FirstVirtualRegister, + e = RegMap->getLastVirtReg(); i != e; ++i) + if (RegMap->getRegClass(i) == &PPC::VRRCRegClass) { + HasVectorVReg = true; + break; + } + + // If we have a vector register, we want to emit code into the entry and exit + // blocks to save and restore the VRSAVE register. We do this here (instead + // of marking all vector instructions as clobbering VRSAVE) for two reasons: + // + // 1. This (trivially) reduces the load on the register allocator, by not + // having to represent the live range of the VRSAVE register. + // 2. This (more significantly) allows us to create a temporary virtual + // register to hold the saved VRSAVE value, allowing this temporary to be + // register allocated, instead of forcing it to be spilled to the stack. + if (HasVectorVReg) { + // Create two vregs - one to hold the VRSAVE register that is live-in to the + // function and one for the value after having bits or'd into it. + unsigned InVRSAVE = RegMap->createVirtualRegister(&PPC::GPRCRegClass); + unsigned UpdatedVRSAVE = RegMap->createVirtualRegister(&PPC::GPRCRegClass); + + MachineFunction &MF = DAG.getMachineFunction(); + MachineBasicBlock &EntryBB = *MF.begin(); + // Emit the following code into the entry block: + // InVRSAVE = MFVRSAVE + // UpdatedVRSAVE = UPDATE_VRSAVE InVRSAVE + // MTVRSAVE UpdatedVRSAVE + MachineBasicBlock::iterator IP = EntryBB.begin(); // Insert Point + BuildMI(EntryBB, IP, PPC::MFVRSAVE, 0, InVRSAVE); + BuildMI(EntryBB, IP, PPC::UPDATE_VRSAVE, 1, UpdatedVRSAVE).addReg(InVRSAVE); + BuildMI(EntryBB, IP, PPC::MTVRSAVE, 1).addReg(UpdatedVRSAVE); + + // Find all return blocks, outputting a restore in each epilog. + const TargetInstrInfo &TII = *DAG.getTarget().getInstrInfo(); + for (MachineFunction::iterator BB = MF.begin(), E = MF.end(); BB != E; ++BB) + if (!BB->empty() && TII.isReturn(BB->back().getOpcode())) { + IP = BB->end(); --IP; + + // Skip over all terminator instructions, which are part of the return + // sequence. + MachineBasicBlock::iterator I2 = IP; + while (I2 != BB->begin() && TII.isTerminatorInstr((--I2)->getOpcode())) + IP = I2; + + // Emit: MTVRSAVE InVRSave + BuildMI(*BB, IP, PPC::MTVRSAVE, 1).addReg(InVRSAVE); + } + } } /// getGlobalBaseReg - Output the instructions required to put the Index: llvm/lib/Target/PowerPC/PPCInstrInfo.td diff -u llvm/lib/Target/PowerPC/PPCInstrInfo.td:1.181 llvm/lib/Target/PowerPC/PPCInstrInfo.td:1.182 --- llvm/lib/Target/PowerPC/PPCInstrInfo.td:1.181 Sun Mar 12 23:15:10 2006 +++ llvm/lib/Target/PowerPC/PPCInstrInfo.td Mon Mar 13 15:52:10 2006 @@ -210,6 +210,9 @@ def ADJCALLSTACKUP : Pseudo<(ops u16imm:$amt), "; ADJCALLSTACKUP", [(callseq_end imm:$amt)]>; + +def UPDATE_VRSAVE : Pseudo<(ops GPRC:$rD, GPRC:$rS), + "UPDATE_VRSAVE $rD, $rS", []>; } def IMPLICIT_DEF_GPR : Pseudo<(ops GPRC:$rD), "; $rD = IMPLICIT_DEF_GPRC", [(set GPRC:$rD, (undef))]>; @@ -694,8 +697,24 @@ // def MFCTR : XFXForm_1_ext<31, 339, 9, (ops GPRC:$rT), "mfctr $rT", SprMFSPR>, PPC970_DGroup_First, PPC970_Unit_FXU; +def MTCTR : XFXForm_7_ext<31, 467, 9, (ops GPRC:$rS), "mtctr $rS", SprMTSPR>, + PPC970_DGroup_First, PPC970_Unit_FXU; + +def MTLR : XFXForm_7_ext<31, 467, 8, (ops GPRC:$rS), "mtlr $rS", SprMTSPR>, + PPC970_DGroup_First, PPC970_Unit_FXU; def MFLR : XFXForm_1_ext<31, 339, 8, (ops GPRC:$rT), "mflr $rT", SprMFSPR>, PPC970_DGroup_First, PPC970_Unit_FXU; + +// Move to/from VRSAVE: despite being a SPR, the VRSAVE register is renamed like +// a GPR on the PPC970. As such, copies in and out have the same performance +// characteristics as an OR instruction. +def MTVRSAVE : XFXForm_7_ext<31, 467, 256, (ops GPRC:$rS), + "mtspr 256, $rS", IntGeneral>, + PPC970_Unit_FXU; +def MFVRSAVE : XFXForm_1_ext<31, 339, 256, (ops GPRC:$rT), + "mfspr $rT, 256", IntGeneral>, + PPC970_Unit_FXU; + def MFCR : XFXForm_3<31, 19, (ops GPRC:$rT), "mfcr $rT", SprMFCR>, PPC970_MicroCode, PPC970_Unit_CRU; def MTCRF : XFXForm_5<31, 144, (ops crbitm:$FXM, GPRC:$rS), @@ -704,13 +723,6 @@ def MFOCRF: XFXForm_5a<31, 19, (ops GPRC:$rT, crbitm:$FXM), "mfcr $rT, $FXM", SprMFCR>, PPC970_DGroup_First, PPC970_Unit_CRU; -def MTCTR : XFXForm_7_ext<31, 467, 9, (ops GPRC:$rS), "mtctr $rS", SprMTSPR>, - PPC970_DGroup_First, PPC970_Unit_FXU; -def MTLR : XFXForm_7_ext<31, 467, 8, (ops GPRC:$rS), "mtlr $rS", SprMTSPR>, - PPC970_DGroup_First, PPC970_Unit_FXU; -def MTSPR : XFXForm_7<31, 467, (ops GPRC:$rS, u16imm:$UIMM), "mtspr $UIMM, $rS", - SprMTSPR>, - PPC970_DGroup_Single, PPC970_Unit_FXU; // XS-Form instructions. Just 'sradi' // Index: llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp diff -u llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp:1.43 llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp:1.44 --- llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp:1.43 Thu Feb 2 14:12:32 2006 +++ llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp Mon Mar 13 15:52:10 2006 @@ -266,12 +266,63 @@ } } +// HandleVRSaveUpdate - MI is the UPDATE_VRSAVE instruction introduced by the +// instruction selector. Based on the vector registers that have been used, +// transform this into the appropriate ORI instruction. +static void HandleVRSaveUpdate(MachineInstr *MI, const bool *UsedRegs) { + unsigned UsedRegMask = 0; +#define HANDLEREG(N) if (UsedRegs[PPC::V##N]) UsedRegMask |= 1 << (31-N) + HANDLEREG( 0); HANDLEREG( 1); HANDLEREG( 2); HANDLEREG( 3); + HANDLEREG( 4); HANDLEREG( 5); HANDLEREG( 6); HANDLEREG( 7); + HANDLEREG( 8); HANDLEREG( 9); HANDLEREG(10); HANDLEREG(11); + HANDLEREG(12); HANDLEREG(13); HANDLEREG(14); HANDLEREG(15); + HANDLEREG(16); HANDLEREG(17); HANDLEREG(18); HANDLEREG(19); + HANDLEREG(20); HANDLEREG(21); HANDLEREG(22); HANDLEREG(23); + HANDLEREG(24); HANDLEREG(25); HANDLEREG(26); HANDLEREG(27); + HANDLEREG(28); HANDLEREG(29); HANDLEREG(30); HANDLEREG(31); +#undef HANDLEREG + unsigned SrcReg = MI->getOperand(1).getReg(); + unsigned DstReg = MI->getOperand(0).getReg(); + // If no registers are used, turn this into a copy. + if (UsedRegMask == 0) { + if (SrcReg != DstReg) + BuildMI(*MI->getParent(), MI, PPC::OR4, 2, DstReg) + .addReg(SrcReg).addReg(SrcReg); + } else if ((UsedRegMask & 0xFFFF) == UsedRegMask) { + BuildMI(*MI->getParent(), MI, PPC::ORI, 2, DstReg) + .addReg(SrcReg).addImm(UsedRegMask); + } else if ((UsedRegMask & 0xFFFF0000) == UsedRegMask) { + BuildMI(*MI->getParent(), MI, PPC::ORIS, 2, DstReg) + .addReg(SrcReg).addImm(UsedRegMask >> 16); + } else { + BuildMI(*MI->getParent(), MI, PPC::ORIS, 2, DstReg) + .addReg(SrcReg).addImm(UsedRegMask >> 16); + BuildMI(*MI->getParent(), MI, PPC::ORI, 2, DstReg) + .addReg(DstReg).addImm(UsedRegMask & 0xFFFF); + } + + // Remove the old UPDATE_VRSAVE instruction. + MI->getParent()->erase(MI); +} + void PPCRegisterInfo::emitPrologue(MachineFunction &MF) const { MachineBasicBlock &MBB = MF.front(); // Prolog goes in entry BB MachineBasicBlock::iterator MBBI = MBB.begin(); MachineFrameInfo *MFI = MF.getFrameInfo(); + // Scan the first few instructions of the prolog, looking for an UPDATE_VRSAVE + // instruction. If we find it, process it. + for (unsigned i = 0; MBBI != MBB.end() && i < 5; ++i, ++MBBI) { + if (MBBI->getOpcode() == PPC::UPDATE_VRSAVE) { + HandleVRSaveUpdate(MBBI, MF.getUsedPhysregs()); + break; + } + } + + // Move MBBI back to the beginning of the function. + MBBI = MBB.begin(); + // Get the number of bytes to allocate from the FrameInfo unsigned NumBytes = MFI->getStackSize(); Index: llvm/lib/Target/PowerPC/PPCRegisterInfo.td diff -u llvm/lib/Target/PowerPC/PPCRegisterInfo.td:1.29 llvm/lib/Target/PowerPC/PPCRegisterInfo.td:1.30 --- llvm/lib/Target/PowerPC/PPCRegisterInfo.td:1.29 Wed Dec 21 20:26:21 2005 +++ llvm/lib/Target/PowerPC/PPCRegisterInfo.td Mon Mar 13 15:52:10 2006 @@ -152,9 +152,9 @@ GPRCClass::iterator GPRCClass::allocation_order_end(MachineFunction &MF) const { if (hasFP(MF)) - return end()-4; + return end()-4; // don't allocate R31, R0, R1, LR else - return end()-3; + return end()-3; // don't allocate R0, R1, LR } }]; } From lattner at cs.uiuc.edu Mon Mar 13 16:38:44 2006 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Mon, 13 Mar 2006 16:38:44 -0600 Subject: [llvm-commits] CVS: llvm/include/llvm/Intrinsics.td Message-ID: <200603132238.QAA31579@zion.cs.uiuc.edu> Changes in directory llvm/include/llvm: Intrinsics.td updated: 1.6 -> 1.7 --- Log message: Add a first ppc altivec intrinsic. Add packed type support. --- Diffs of the changes: (+30 -0) Intrinsics.td | 30 ++++++++++++++++++++++++++++++ 1 files changed, 30 insertions(+) Index: llvm/include/llvm/Intrinsics.td diff -u llvm/include/llvm/Intrinsics.td:1.6 llvm/include/llvm/Intrinsics.td:1.7 --- llvm/include/llvm/Intrinsics.td:1.6 Mon Mar 13 07:07:37 2006 +++ llvm/include/llvm/Intrinsics.td Mon Mar 13 16:38:32 2006 @@ -54,6 +54,11 @@ string TypeVal = typeval; } +class LLVMPackedType : LLVMType<"Type::PackedTyID">{ + int NumElts = numelts; + LLVMType ElTy = elty; +} + def llvm_void_ty : LLVMType<"Type::VoidTyID">; def llvm_bool_ty : LLVMType<"Type::BoolTyID">; def llvm_sbyte_ty : LLVMType<"Type::SByteTyID">; @@ -71,6 +76,10 @@ def llvm_anchor_ty : LLVMType<"Type::PointerTyID">; // {}* def llvm_descriptor_ty : LLVMType<"Type::PointerTyID">; // global* +def llvm_v4i32_ty : LLVMPackedType<4, llvm_int_ty>; // 4 x int +def llvm_v4f32_ty : LLVMPackedType<4, llvm_float_ty>; // 4 x float +def llvm_v2f64_ty : LLVMPackedType<4, llvm_float_ty>; // 2 x double + //===----------------------------------------------------------------------===// // Intrinsic Definitions. //===----------------------------------------------------------------------===// @@ -88,10 +97,18 @@ list properties = [], string name = ""> { string LLVMName = name; + string GCCBuiltinName = ""; list Types = types; list Properties = properties; } +/// GCCBuiltin - If this intrinsic exactly corresponds to a GCC builtin, this +/// specifies the name of the builtin. This provides automatic CBE and CFE +/// support. +class GCCBuiltin { + string GCCBuiltinName = name; +} + //===--------------- Variable Argument Handling Intrinsics ----------------===// // @@ -189,3 +206,16 @@ def int_dbg_func_start : Intrinsic<[llvm_void_ty, llvm_descriptor_ty]>; // dbg_declare, // Declare a local object + + +//===----------------------------------------------------------------------===// +// Target-specific intrinsics +//===----------------------------------------------------------------------===// + +//===----------------------------------------------------------------------===// +// PowerPC Intrinsics + +def int_ppc_altivec_lvx : Intrinsic<[llvm_v4i32_ty, llvm_int_ty, llvm_ptr_ty], + [IntrReadMem]>, + GCCBuiltin<"__builtin_altivec_lvx">; + From lattner at cs.uiuc.edu Mon Mar 13 16:39:08 2006 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Mon, 13 Mar 2006 16:39:08 -0600 Subject: [llvm-commits] CVS: llvm/utils/TableGen/CodeGenIntrinsics.h IntrinsicEmitter.cpp Message-ID: <200603132239.QAA31594@zion.cs.uiuc.edu> Changes in directory llvm/utils/TableGen: CodeGenIntrinsics.h updated: 1.3 -> 1.4 IntrinsicEmitter.cpp updated: 1.6 -> 1.7 --- Log message: Verify that packed type operands have the right size and base type. --- Diffs of the changes: (+28 -6) CodeGenIntrinsics.h | 4 ++++ IntrinsicEmitter.cpp | 30 ++++++++++++++++++++++++------ 2 files changed, 28 insertions(+), 6 deletions(-) Index: llvm/utils/TableGen/CodeGenIntrinsics.h diff -u llvm/utils/TableGen/CodeGenIntrinsics.h:1.3 llvm/utils/TableGen/CodeGenIntrinsics.h:1.4 --- llvm/utils/TableGen/CodeGenIntrinsics.h:1.3 Thu Mar 9 16:05:04 2006 +++ llvm/utils/TableGen/CodeGenIntrinsics.h Mon Mar 13 16:38:57 2006 @@ -30,6 +30,10 @@ /// of the arguments. These are things like Type::UIntTyID. std::vector ArgTypes; + /// ArgTypeDefs - The records for each argument type. + /// + std::vector ArgTypeDefs; + // Memory mod/ref behavior of this intrinsic. enum { NoMem, ReadArgMem, ReadMem, WriteArgMem, WriteMem Index: llvm/utils/TableGen/IntrinsicEmitter.cpp diff -u llvm/utils/TableGen/IntrinsicEmitter.cpp:1.6 llvm/utils/TableGen/IntrinsicEmitter.cpp:1.7 --- llvm/utils/TableGen/IntrinsicEmitter.cpp:1.6 Fri Mar 10 18:20:47 2006 +++ llvm/utils/TableGen/IntrinsicEmitter.cpp Mon Mar 13 16:38:57 2006 @@ -13,6 +13,7 @@ #include "IntrinsicEmitter.h" #include "Record.h" +#include "llvm/ADT/StringExtras.h" using namespace llvm; //===----------------------------------------------------------------------===// @@ -52,6 +53,7 @@ Record *TyEl = DI->getDef(); assert(TyEl->isSubClassOf("LLVMType") && "Expected a type!"); ArgTypes.push_back(TyEl->getValueAsString("TypeVal")); + ArgTypeDefs.push_back(TyEl); } if (ArgTypes.size() == 0) throw "Intrinsic '"+DefName+"' needs at least a type for the ret value!"; @@ -151,6 +153,25 @@ OS << "#endif\n\n"; } +static void EmitTypeVerify(std::ostream &OS, const std::string &Val, + Record *ArgType) { + OS << " Assert1(" << Val << "->getTypeID() == " + << ArgType->getValueAsString("TypeVal") << ",\n" + << " \"Illegal intrinsic type!\", IF);\n"; + + // If this is a packed type, check that the subtype and size are correct. + if (ArgType->isSubClassOf("LLVMPackedType")) { + Record *SubType = ArgType->getValueAsDef("ElTy"); + OS << " Assert1(cast(" << Val + << ")->getElementType()->getTypeID() == " + << SubType->getValueAsString("TypeVal") << ",\n" + << " \"Illegal intrinsic type!\", IF);\n"; + OS << " Assert1(cast(" << Val << ")->getNumElements() == " + << ArgType->getValueAsInt("NumElts") << ",\n" + << " \"Illegal intrinsic type!\", IF);\n"; + } +} + void IntrinsicEmitter::EmitVerifier(const std::vector &Ints, std::ostream &OS) { OS << "// Verifier::visitIntrinsicFunctionCall code.\n"; @@ -163,13 +184,10 @@ OS << " Assert1(FTy->getNumParams() == " << Ints[i].ArgTypes.size()-1 << ",\n" << " \"Illegal # arguments for intrinsic function!\", IF);\n"; - OS << " Assert1(FTy->getReturnType()->getTypeID() == " - << Ints[i].ArgTypes[0] << ",\n" - << " \"Illegal result type!\", IF);\n"; + EmitTypeVerify(OS, "FTy->getReturnType()", Ints[i].ArgTypeDefs[0]); for (unsigned j = 1; j != Ints[i].ArgTypes.size(); ++j) - OS << " Assert1(FTy->getParamType(" << j-1 << ")->getTypeID() == " - << Ints[i].ArgTypes[j] << ",\n" - << " \"Illegal argument type!\", IF);\n"; + EmitTypeVerify(OS, "FTy->getParamType(" + utostr(j-1) + ")", + Ints[i].ArgTypeDefs[j]); OS << " break;\n"; } OS << " }\n"; From lattner at cs.uiuc.edu Mon Mar 13 17:08:56 2006 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Mon, 13 Mar 2006 17:08:56 -0600 Subject: [llvm-commits] CVS: llvm/utils/TableGen/CodeGenIntrinsics.h IntrinsicEmitter.cpp IntrinsicEmitter.h Message-ID: <200603132308.RAA31995@zion.cs.uiuc.edu> Changes in directory llvm/utils/TableGen: CodeGenIntrinsics.h updated: 1.4 -> 1.5 IntrinsicEmitter.cpp updated: 1.7 -> 1.8 IntrinsicEmitter.h updated: 1.5 -> 1.6 --- Log message: emit a mapping from LLVM intrinsic -> GCC builtins. --- Diffs of the changes: (+30 -8) CodeGenIntrinsics.h | 3 ++- IntrinsicEmitter.cpp | 33 ++++++++++++++++++++++++++------- IntrinsicEmitter.h | 2 ++ 3 files changed, 30 insertions(+), 8 deletions(-) Index: llvm/utils/TableGen/CodeGenIntrinsics.h diff -u llvm/utils/TableGen/CodeGenIntrinsics.h:1.4 llvm/utils/TableGen/CodeGenIntrinsics.h:1.5 --- llvm/utils/TableGen/CodeGenIntrinsics.h:1.4 Mon Mar 13 16:38:57 2006 +++ llvm/utils/TableGen/CodeGenIntrinsics.h Mon Mar 13 17:08:44 2006 @@ -25,7 +25,8 @@ Record *TheDef; // The actual record defining this instruction. std::string Name; // The name of the LLVM function "llvm.bswap.i32" std::string EnumName; // The name of the enum "bswap_i32" - + std::string GCCBuiltinName;// Name of the corresponding GCC builtin, or "". + /// ArgTypes - The type primitive enum value for the return value and all /// of the arguments. These are things like Type::UIntTyID. std::vector ArgTypes; Index: llvm/utils/TableGen/IntrinsicEmitter.cpp diff -u llvm/utils/TableGen/IntrinsicEmitter.cpp:1.7 llvm/utils/TableGen/IntrinsicEmitter.cpp:1.8 --- llvm/utils/TableGen/IntrinsicEmitter.cpp:1.7 Mon Mar 13 16:38:57 2006 +++ llvm/utils/TableGen/IntrinsicEmitter.cpp Mon Mar 13 17:08:44 2006 @@ -33,6 +33,7 @@ std::string(DefName.begin(), DefName.begin()+4) != "int_") throw "Intrinsic '" + DefName + "' does not start with 'int_'!"; EnumName = std::string(DefName.begin()+4, DefName.end()); + GCCBuiltinName = R->getValueAsString("GCCBuiltinName"); Name = R->getValueAsString("LLVMName"); if (Name == "") { @@ -105,6 +106,9 @@ // Emit side effect info for each function. EmitSideEffectInfo(Ints, OS); + + // Emit a list of intrinsics with corresponding GCC builtins. + EmitGCCBuiltinList(Ints, OS); } void IntrinsicEmitter::EmitEnumInfo(const std::vector &Ints, @@ -221,16 +225,31 @@ OS << " default: break;\n"; for (unsigned i = 0, e = Ints.size(); i != e; ++i) { switch (Ints[i].ModRef) { - default: break; - case CodeGenIntrinsic::NoMem: - case CodeGenIntrinsic::ReadArgMem: - case CodeGenIntrinsic::ReadMem: - OS << " case Intrinsic::" << Ints[i].EnumName << ":\n"; - break; + default: break; + case CodeGenIntrinsic::NoMem: + case CodeGenIntrinsic::ReadArgMem: + case CodeGenIntrinsic::ReadMem: + OS << " case Intrinsic::" << Ints[i].EnumName << ":\n"; + break; } } OS << " return true; // These intrinsics have no side effects.\n"; OS << " }\n"; OS << "#endif\n\n"; - } + +void IntrinsicEmitter:: +EmitGCCBuiltinList(const std::vector &Ints, std::ostream &OS){ + OS << "// Get the GCC builtin that corresponds to an LLVM intrinsic.\n"; + OS << "#ifdef GET_GCC_BUILTIN_NAME\n"; + OS << " switch (F->getIntrinsicID()) {\n"; + OS << " default: BuiltinName = \"\"; break;\n"; + for (unsigned i = 0, e = Ints.size(); i != e; ++i) { + if (!Ints[i].GCCBuiltinName.empty()) { + OS << " case Intrinsic::" << Ints[i].EnumName << ": BuiltinName = \"" + << Ints[i].GCCBuiltinName << "\"; break;\n"; + } + } + OS << " }\n"; + OS << "#endif\n\n"; +} \ No newline at end of file Index: llvm/utils/TableGen/IntrinsicEmitter.h diff -u llvm/utils/TableGen/IntrinsicEmitter.h:1.5 llvm/utils/TableGen/IntrinsicEmitter.h:1.6 --- llvm/utils/TableGen/IntrinsicEmitter.h:1.5 Thu Mar 9 16:37:52 2006 +++ llvm/utils/TableGen/IntrinsicEmitter.h Mon Mar 13 17:08:44 2006 @@ -37,6 +37,8 @@ std::ostream &OS); void EmitSideEffectInfo(const std::vector &Ints, std::ostream &OS); + void EmitGCCBuiltinList(const std::vector &Ints, + std::ostream &OS); }; } // End llvm namespace From lattner at cs.uiuc.edu Mon Mar 13 17:09:17 2006 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Mon, 13 Mar 2006 17:09:17 -0600 Subject: [llvm-commits] CVS: llvm/lib/Target/CBackend/Writer.cpp Message-ID: <200603132309.RAA32028@zion.cs.uiuc.edu> Changes in directory llvm/lib/Target/CBackend: Writer.cpp updated: 1.256 -> 1.257 --- Log message: Handle builtins that directly correspond to GCC builtins. --- Diffs of the changes: (+25 -2) Writer.cpp | 27 +++++++++++++++++++++++++-- 1 files changed, 25 insertions(+), 2 deletions(-) Index: llvm/lib/Target/CBackend/Writer.cpp diff -u llvm/lib/Target/CBackend/Writer.cpp:1.256 llvm/lib/Target/CBackend/Writer.cpp:1.257 --- llvm/lib/Target/CBackend/Writer.cpp:1.256 Mon Mar 13 07:07:37 2006 +++ llvm/lib/Target/CBackend/Writer.cpp Mon Mar 13 17:09:05 2006 @@ -1602,6 +1602,15 @@ // We directly implement these intrinsics break; default: + // If this is an intrinsic that directly corresponds to a GCC + // builtin, we handle it. + const char *BuiltinName = ""; +#define GET_GCC_BUILTIN_NAME +#include "llvm/Intrinsics.gen" +#undef GET_GCC_BUILTIN_NAME + // If we handle it, don't lower it. + if (BuiltinName[0]) break; + // All other intrinsic calls we must lower. Instruction *Before = 0; if (CI != &BB->front()) @@ -1613,17 +1622,32 @@ } else { I = BB->begin(); } + break; } } void CWriter::visitCallInst(CallInst &I) { + bool WroteCallee = false; + // Handle intrinsic function calls first... if (Function *F = I.getCalledFunction()) if (Intrinsic::ID ID = (Intrinsic::ID)F->getIntrinsicID()) { switch (ID) { - default: assert(0 && "Unknown LLVM intrinsic!"); + default: { + // If this is an intrinsic that directly corresponds to a GCC + // builtin, we emit it here. + const char *BuiltinName = ""; +#define GET_GCC_BUILTIN_NAME +#include "llvm/Intrinsics.gen" +#undef GET_GCC_BUILTIN_NAME + assert(BuiltinName[0] && "Unknown LLVM intrinsic!"); + + Out << BuiltinName; + WroteCallee = true; + break; + } case Intrinsic::vastart: Out << "0; "; @@ -1720,7 +1744,6 @@ // in the common case, we handle casts where the number of arguments passed // match exactly. // - bool WroteCallee = false; if (I.isTailCall()) Out << " /*tail*/ "; if (ConstantExpr *CE = dyn_cast(Callee)) if (CE->getOpcode() == Instruction::Cast) From evan.cheng at apple.com Mon Mar 13 17:14:34 2006 From: evan.cheng at apple.com (Evan Cheng) Date: Mon, 13 Mar 2006 17:14:34 -0600 Subject: [llvm-commits] CVS: llvm/lib/Transforms/Scalar/LoopStrengthReduce.cpp Message-ID: <200603132314.RAA32113@zion.cs.uiuc.edu> Changes in directory llvm/lib/Transforms/Scalar: LoopStrengthReduce.cpp updated: 1.75 -> 1.76 --- Log message: Added target lowering hooks which LSR consults to make more intelligent transformation decisions. --- Diffs of the changes: (+33 -25) LoopStrengthReduce.cpp | 58 +++++++++++++++++++++++++++---------------------- 1 files changed, 33 insertions(+), 25 deletions(-) Index: llvm/lib/Transforms/Scalar/LoopStrengthReduce.cpp diff -u llvm/lib/Transforms/Scalar/LoopStrengthReduce.cpp:1.75 llvm/lib/Transforms/Scalar/LoopStrengthReduce.cpp:1.76 --- llvm/lib/Transforms/Scalar/LoopStrengthReduce.cpp:1.75 Sat Feb 4 03:52:43 2006 +++ llvm/lib/Transforms/Scalar/LoopStrengthReduce.cpp Mon Mar 13 17:14:23 2006 @@ -31,6 +31,7 @@ #include "llvm/Target/TargetData.h" #include "llvm/ADT/Statistic.h" #include "llvm/Support/Debug.h" +#include "llvm/Target/TargetLowering.h" #include #include #include @@ -105,9 +106,14 @@ /// DeadInsts - Keep track of instructions we may have made dead, so that /// we can remove them after we are done working. std::set DeadInsts; + + /// TLI - Keep a pointer of a TargetLowering to consult for determining + /// transformation profitability. + const TargetLowering *TLI; + public: - LoopStrengthReduce(unsigned MTAMS = 1) - : MaxTargetAMSize(MTAMS) { + LoopStrengthReduce(unsigned MTAMS = 1, const TargetLowering *tli = NULL) + : MaxTargetAMSize(MTAMS), TLI(tli) { } virtual bool runOnFunction(Function &) { @@ -162,8 +168,9 @@ "Loop Strength Reduction"); } -FunctionPass *llvm::createLoopStrengthReducePass(unsigned MaxTargetAMSize) { - return new LoopStrengthReduce(MaxTargetAMSize); +FunctionPass *llvm::createLoopStrengthReducePass(unsigned MaxTargetAMSize, + const TargetLowering *TLI) { + return new LoopStrengthReduce(MaxTargetAMSize, TLI); } /// getCastedVersionOf - Return the specified value casted to uintptr_t. @@ -574,25 +581,25 @@ /// isTargetConstant - Return true if the following can be referenced by the /// immediate field of a target instruction. -static bool isTargetConstant(const SCEVHandle &V) { - - // FIXME: Look at the target to decide if &GV is a legal constant immediate. +static bool isTargetConstant(const SCEVHandle &V, const TargetLowering *TLI) { if (SCEVConstant *SC = dyn_cast(V)) { - // PPC allows a sign-extended 16-bit immediate field. int64_t V = SC->getValue()->getSExtValue(); - if (V > -(1 << 16) && V < (1 << 16)-1) - return true; - return false; + if (TLI) + return TLI->isLegalAddressImmediate(V); + else + // Defaults to PPC. PPC allows a sign-extended 16-bit immediate field. + return (V > -(1 << 16) && V < (1 << 16)-1); } - return false; // ENABLE this for x86 - if (SCEVUnknown *SU = dyn_cast(V)) if (ConstantExpr *CE = dyn_cast(SU->getValue())) - if (CE->getOpcode() == Instruction::Cast) - if (isa(CE->getOperand(0))) - // FIXME: should check to see that the dest is uintptr_t! + if (CE->getOpcode() == Instruction::Cast) { + Constant *Op0 = CE->getOperand(0); + if (isa(Op0) && + TLI && + TLI->isLegalAddressImmediate(cast(Op0))) return true; + } return false; } @@ -638,7 +645,8 @@ /// MoveImmediateValues - Look at Val, and pull out any additions of constants /// that can fit into the immediate field of instructions in the target. /// Accumulate these immediate values into the Imm value. -static void MoveImmediateValues(SCEVHandle &Val, SCEVHandle &Imm, +static void MoveImmediateValues(const TargetLowering *TLI, + SCEVHandle &Val, SCEVHandle &Imm, bool isAddress, Loop *L) { if (SCEVAddExpr *SAE = dyn_cast(Val)) { std::vector NewOps; @@ -646,7 +654,7 @@ for (unsigned i = 0; i != SAE->getNumOperands(); ++i) { SCEVHandle NewOp = SAE->getOperand(i); - MoveImmediateValues(NewOp, Imm, isAddress, L); + MoveImmediateValues(TLI, NewOp, Imm, isAddress, L); if (!NewOp->isLoopInvariant(L)) { // If this is a loop-variant expression, it must stay in the immediate @@ -665,7 +673,7 @@ } else if (SCEVAddRecExpr *SARE = dyn_cast(Val)) { // Try to pull immediates out of the start value of nested addrec's. SCEVHandle Start = SARE->getStart(); - MoveImmediateValues(Start, Imm, isAddress, L); + MoveImmediateValues(TLI, Start, Imm, isAddress, L); if (Start != SARE->getStart()) { std::vector Ops(SARE->op_begin(), SARE->op_end()); @@ -675,12 +683,12 @@ return; } else if (SCEVMulExpr *SME = dyn_cast(Val)) { // Transform "8 * (4 + v)" -> "32 + 8*V" if "32" fits in the immed field. - if (isAddress && isTargetConstant(SME->getOperand(0)) && + if (isAddress && isTargetConstant(SME->getOperand(0), TLI) && SME->getNumOperands() == 2 && SME->isLoopInvariant(L)) { SCEVHandle SubImm = SCEVUnknown::getIntegerSCEV(0, Val->getType()); SCEVHandle NewOp = SME->getOperand(1); - MoveImmediateValues(NewOp, SubImm, isAddress, L); + MoveImmediateValues(TLI, NewOp, SubImm, isAddress, L); // If we extracted something out of the subexpressions, see if we can // simplify this! @@ -688,7 +696,7 @@ // Scale SubImm up by "8". If the result is a target constant, we are // good. SubImm = SCEVMulExpr::get(SubImm, SME->getOperand(0)); - if (isTargetConstant(SubImm)) { + if (isTargetConstant(SubImm, TLI)) { // Accumulate the immediate. Imm = SCEVAddExpr::get(Imm, SubImm); @@ -702,7 +710,7 @@ // Loop-variant expressions must stay in the immediate field of the // expression. - if ((isAddress && isTargetConstant(Val)) || + if ((isAddress && isTargetConstant(Val, TLI)) || !Val->isLoopInvariant(L)) { Imm = SCEVAddExpr::get(Imm, Val); Val = SCEVUnknown::getIntegerSCEV(0, Val->getType()); @@ -879,7 +887,7 @@ if (SI->getOperand(1) == UsersToProcess[i].OperandValToReplace) isAddress = true; - MoveImmediateValues(UsersToProcess[i].Base, UsersToProcess[i].Imm, + MoveImmediateValues(TLI, UsersToProcess[i].Base, UsersToProcess[i].Imm, isAddress, L); } } @@ -941,7 +949,7 @@ // this by forcing a noop cast to be inserted into the preheader in this // case. if (Constant *C = dyn_cast(BaseV)) - if (!C->isNullValue() && !isTargetConstant(Base)) { + if (!C->isNullValue() && !isTargetConstant(Base, TLI)) { // We want this constant emitted into the preheader! BaseV = new CastInst(BaseV, BaseV->getType(), "preheaderinsert", PreInsertPt); From evan.cheng at apple.com Mon Mar 13 17:14:35 2006 From: evan.cheng at apple.com (Evan Cheng) Date: Mon, 13 Mar 2006 17:14:35 -0600 Subject: [llvm-commits] CVS: llvm/include/llvm/Transforms/Scalar.h Message-ID: <200603132314.RAA32117@zion.cs.uiuc.edu> Changes in directory llvm/include/llvm/Transforms: Scalar.h updated: 1.60 -> 1.61 --- Log message: Added target lowering hooks which LSR consults to make more intelligent transformation decisions. --- Diffs of the changes: (+8 -2) Scalar.h | 10 ++++++++-- 1 files changed, 8 insertions(+), 2 deletions(-) Index: llvm/include/llvm/Transforms/Scalar.h diff -u llvm/include/llvm/Transforms/Scalar.h:1.60 llvm/include/llvm/Transforms/Scalar.h:1.61 --- llvm/include/llvm/Transforms/Scalar.h:1.60 Tue Nov 22 16:14:23 2005 +++ llvm/include/llvm/Transforms/Scalar.h Mon Mar 13 17:14:23 2006 @@ -15,6 +15,8 @@ #ifndef LLVM_TRANSFORMS_SCALAR_H #define LLVM_TRANSFORMS_SCALAR_H +#include + namespace llvm { class ModulePass; @@ -22,6 +24,7 @@ class GetElementPtrInst; class PassInfo; class TerminatorInst; +class TargetLowering; //===----------------------------------------------------------------------===// // @@ -132,9 +135,12 @@ // a loop's canonical induction variable as one of their indices. The // MaxTargetAMSize is the largest element size that the target architecture // can handle in its addressing modes. Power of two multipliers less than or -// equal to this value are not reduced. +// equal to this value are not reduced. It also takes an optional second +// parameter used to consult the target machine whether certain transformations +// are profitable. // -FunctionPass *createLoopStrengthReducePass(unsigned MaxTargetAMSize = 1); +FunctionPass *createLoopStrengthReducePass(unsigned MaxTargetAMSize = 1, + const TargetLowering *TLI = NULL); //===----------------------------------------------------------------------===// // From evan.cheng at apple.com Mon Mar 13 17:15:38 2006 From: evan.cheng at apple.com (Evan Cheng) Date: Mon, 13 Mar 2006 17:15:38 -0600 Subject: [llvm-commits] CVS: llvm/include/llvm/Target/TargetLowering.h Message-ID: <200603132315.RAA32137@zion.cs.uiuc.edu> Changes in directory llvm/include/llvm/Target: TargetLowering.h updated: 1.59 -> 1.60 --- Log message: Add LSR hooks. --- Diffs of the changes: (+10 -1) TargetLowering.h | 11 ++++++++++- 1 files changed, 10 insertions(+), 1 deletion(-) Index: llvm/include/llvm/Target/TargetLowering.h diff -u llvm/include/llvm/Target/TargetLowering.h:1.59 llvm/include/llvm/Target/TargetLowering.h:1.60 --- llvm/include/llvm/Target/TargetLowering.h:1.59 Sun Mar 5 17:49:19 2006 +++ llvm/include/llvm/Target/TargetLowering.h Mon Mar 13 17:15:27 2006 @@ -349,7 +349,7 @@ uint64_t &KnownZero, uint64_t &KnownOne, unsigned Depth = 0) const; - + struct DAGCombinerInfo { void *DC; // The DAG Combiner object. bool BeforeLegalize; @@ -560,6 +560,15 @@ virtual bool isOperandValidForConstraint(SDOperand Op, char ConstraintLetter); //===--------------------------------------------------------------------===// + // Loop Strength Reduction hooks + // + + /// isLegalAddressImmediate - Return true if the integer value or GlobalValue + /// can be used as the offset of the target addressing mode. + virtual bool isLegalAddressImmediate(int64_t V) const; + virtual bool isLegalAddressImmediate(GlobalValue *GV) const; + + //===--------------------------------------------------------------------===// // Scheduler hooks // From evan.cheng at apple.com Mon Mar 13 17:16:43 2006 From: evan.cheng at apple.com (Evan Cheng) Date: Mon, 13 Mar 2006 17:16:43 -0600 Subject: [llvm-commits] CVS: llvm/lib/Target/TargetLowering.cpp Message-ID: <200603132316.RAA32157@zion.cs.uiuc.edu> Changes in directory llvm/lib/Target: TargetLowering.cpp updated: 1.45 -> 1.46 --- Log message: Add LSR hooks. --- Diffs of the changes: (+13 -0) TargetLowering.cpp | 13 +++++++++++++ 1 files changed, 13 insertions(+) Index: llvm/lib/Target/TargetLowering.cpp diff -u llvm/lib/Target/TargetLowering.cpp:1.45 llvm/lib/Target/TargetLowering.cpp:1.46 --- llvm/lib/Target/TargetLowering.cpp:1.45 Mon Mar 13 00:42:16 2006 +++ llvm/lib/Target/TargetLowering.cpp Mon Mar 13 17:16:31 2006 @@ -976,3 +976,16 @@ return std::pair(0, 0); } + +//===----------------------------------------------------------------------===// +// Loop Strength Reduction hooks +//===----------------------------------------------------------------------===// + +/// isLegalAddressImmediate - Return true if the integer value or +/// GlobalValue can be used as the offset of the target addressing mode. +bool TargetLowering::isLegalAddressImmediate(int64_t V) const { + return false; +} +bool TargetLowering::isLegalAddressImmediate(GlobalValue *GV) const { + return false; +} From evan.cheng at apple.com Mon Mar 13 17:17:54 2006 From: evan.cheng at apple.com (Evan Cheng) Date: Mon, 13 Mar 2006 17:17:54 -0600 Subject: [llvm-commits] CVS: llvm/include/llvm/Target/TargetMachine.h Message-ID: <200603132317.RAA32215@zion.cs.uiuc.edu> Changes in directory llvm/include/llvm/Target: TargetMachine.h updated: 1.60 -> 1.61 --- Log message: Added getTargetLowering() - returns DAG lowering info. --- Diffs of the changes: (+3 -0) TargetMachine.h | 3 +++ 1 files changed, 3 insertions(+) Index: llvm/include/llvm/Target/TargetMachine.h diff -u llvm/include/llvm/Target/TargetMachine.h:1.60 llvm/include/llvm/Target/TargetMachine.h:1.61 --- llvm/include/llvm/Target/TargetMachine.h:1.60 Wed Feb 22 14:19:42 2006 +++ llvm/include/llvm/Target/TargetMachine.h Mon Mar 13 17:17:42 2006 @@ -24,6 +24,7 @@ class TargetInstrInfo; class TargetInstrDescriptor; class TargetJITInfo; +class TargetLowering; class TargetSchedInfo; class SparcV9RegInfo; class TargetFrameInfo; @@ -108,9 +109,11 @@ // -- Instruction opcode and operand information // -- Pipelines and scheduling information // -- Stack frame information + // -- Selection DAG lowering information // virtual const TargetInstrInfo *getInstrInfo() const { return 0; } virtual const TargetFrameInfo *getFrameInfo() const { return 0; } + virtual TargetLowering *getTargetLowering() const { return 0; } const TargetData &getTargetData() const { return DataLayout; } /// getSubtarget - This method returns a pointer to the specified type of From evan.cheng at apple.com Mon Mar 13 17:18:28 2006 From: evan.cheng at apple.com (Evan Cheng) Date: Mon, 13 Mar 2006 17:18:28 -0600 Subject: [llvm-commits] CVS: llvm/lib/Target/X86/X86ISelLowering.cpp Message-ID: <200603132318.RAA32230@zion.cs.uiuc.edu> Changes in directory llvm/lib/Target/X86: X86ISelLowering.cpp updated: 1.104 -> 1.105 --- Log message: Add LSR hooks. --- Diffs of the changes: (+35 -4) X86ISelLowering.cpp | 39 +++++++++++++++++++++++++++++++++++---- 1 files changed, 35 insertions(+), 4 deletions(-) Index: llvm/lib/Target/X86/X86ISelLowering.cpp diff -u llvm/lib/Target/X86/X86ISelLowering.cpp:1.104 llvm/lib/Target/X86/X86ISelLowering.cpp:1.105 --- llvm/lib/Target/X86/X86ISelLowering.cpp:1.104 Tue Mar 7 17:29:39 2006 +++ llvm/lib/Target/X86/X86ISelLowering.cpp Mon Mar 13 17:18:16 2006 @@ -19,6 +19,8 @@ #include "llvm/CallingConv.h" #include "llvm/Constants.h" #include "llvm/Function.h" +#include "llvm/ADT/VectorExtras.h" +#include "llvm/Analysis/ScalarEvolutionExpressions.h" #include "llvm/CodeGen/MachineFrameInfo.h" #include "llvm/CodeGen/MachineFunction.h" #include "llvm/CodeGen/MachineInstrBuilder.h" @@ -26,7 +28,6 @@ #include "llvm/CodeGen/SSARegMap.h" #include "llvm/Support/MathExtras.h" #include "llvm/Target/TargetOptions.h" -#include "llvm/ADT/VectorExtras.h" using namespace llvm; // FIXME: temporary. @@ -1317,6 +1318,16 @@ // X86 Custom Lowering Hooks //===----------------------------------------------------------------------===// +/// DarwinGVRequiresExtraLoad - true if accessing the GV requires an extra +/// load. For Darwin, external and weak symbols are indirect, loading the value +/// at address GV rather then the value of GV itself. This means that the +/// GlobalAddress must be in the base or index register of the address, not the +/// GV offset field. +static bool DarwinGVRequiresExtraLoad(GlobalValue *GV) { + return (GV->hasWeakLinkage() || GV->hasLinkOnceLinkage() || + (GV->isExternal() && !GV->hasNotBeenReadFromBytecode())); +} + /// LowerOperation - Provide custom lowering hooks for some operations. /// SDOperand X86TargetLowering::LowerOperation(SDOperand Op, SelectionDAG &DAG) { @@ -1986,12 +1997,11 @@ DAG.getNode(X86ISD::GlobalBaseReg, getPointerTy()), Result); // For Darwin, external and weak symbols are indirect, so we want to load - // the value at address GV, not the value of GV itself. This means that + // the value at address GV, not the value of GV itself. This means that // the GlobalAddress must be in the base or index register of the address, // not the GV offset field. if (getTargetMachine().getRelocationModel() != Reloc::Static && - (GV->hasWeakLinkage() || GV->hasLinkOnceLinkage() || - (GV->isExternal() && !GV->hasNotBeenReadFromBytecode()))) + DarwinGVRequiresExtraLoad(GV)) Result = DAG.getLoad(MVT::i32, DAG.getEntryNode(), Result, DAG.getSrcValue(NULL)); } @@ -2179,3 +2189,24 @@ return std::vector(); } + +/// isLegalAddressImmediate - Return true if the integer value or +/// GlobalValue can be used as the offset of the target addressing mode. +bool X86TargetLowering::isLegalAddressImmediate(int64_t V) const { + // X86 allows a sign-extended 32-bit immediate field. + return (V > -(1LL << 32) && V < (1LL << 32)-1); +} + +bool X86TargetLowering::isLegalAddressImmediate(GlobalValue *GV) const { + if (getTargetMachine(). + getSubtarget().isTargetDarwin()) { + Reloc::Model RModel = getTargetMachine().getRelocationModel(); + if (RModel == Reloc::Static) + return true; + else if (RModel == Reloc::DynamicNoPIC) + return DarwinGVRequiresExtraLoad(GV); + else + return false; + } else + return true; +} From evan.cheng at apple.com Mon Mar 13 17:19:22 2006 From: evan.cheng at apple.com (Evan Cheng) Date: Mon, 13 Mar 2006 17:19:22 -0600 Subject: [llvm-commits] CVS: llvm/lib/Target/README.txt Message-ID: <200603132319.RAA32246@zion.cs.uiuc.edu> Changes in directory llvm/lib/Target: README.txt updated: 1.18 -> 1.19 --- Log message: Update --- Diffs of the changes: (+3 -0) README.txt | 3 +++ 1 files changed, 3 insertions(+) Index: llvm/lib/Target/README.txt diff -u llvm/lib/Target/README.txt:1.18 llvm/lib/Target/README.txt:1.19 --- llvm/lib/Target/README.txt:1.18 Mon Mar 13 00:52:22 2006 +++ llvm/lib/Target/README.txt Mon Mar 13 17:19:10 2006 @@ -54,6 +54,9 @@ Number 1 is the preferred solution. +This has been "fixed" by a TableGen hack. But that is a short term workaround +which will be removed once the proper fix is made. + //===---------------------------------------------------------------------===// Turn this into a signed shift right in instcombine: From evan.cheng at apple.com Mon Mar 13 17:20:51 2006 From: evan.cheng at apple.com (Evan Cheng) Date: Mon, 13 Mar 2006 17:20:51 -0600 Subject: [llvm-commits] CVS: llvm/lib/Target/PowerPC/PPC.h PPCAsmPrinter.cpp PPCISelDAGToDAG.cpp PPCISelLowering.cpp PPCISelLowering.h PPCJITInfo.h PPCTargetMachine.cpp PPCTargetMachine.h Message-ID: <200603132320.RAA32301@zion.cs.uiuc.edu> Changes in directory llvm/lib/Target/PowerPC: PPC.h updated: 1.27 -> 1.28 PPCAsmPrinter.cpp updated: 1.157 -> 1.158 PPCISelDAGToDAG.cpp updated: 1.165 -> 1.166 PPCISelLowering.cpp updated: 1.95 -> 1.96 PPCISelLowering.h updated: 1.25 -> 1.26 PPCJITInfo.h updated: 1.8 -> 1.9 PPCTargetMachine.cpp updated: 1.81 -> 1.82 PPCTargetMachine.h updated: 1.16 -> 1.17 --- Log message: Added getTargetLowering() to TargetMachine. Refactored targets to support this. --- Diffs of the changes: (+30 -13) PPC.h | 8 ++++---- PPCAsmPrinter.cpp | 5 +++-- PPCISelDAGToDAG.cpp | 7 ++++--- PPCISelLowering.cpp | 8 ++++++++ PPCISelLowering.h | 4 ++++ PPCJITInfo.h | 6 +++--- PPCTargetMachine.cpp | 2 +- PPCTargetMachine.h | 3 +++ 8 files changed, 30 insertions(+), 13 deletions(-) Index: llvm/lib/Target/PowerPC/PPC.h diff -u llvm/lib/Target/PowerPC/PPC.h:1.27 llvm/lib/Target/PowerPC/PPC.h:1.28 --- llvm/lib/Target/PowerPC/PPC.h:1.27 Wed Feb 22 14:19:42 2006 +++ llvm/lib/Target/PowerPC/PPC.h Mon Mar 13 17:20:37 2006 @@ -20,16 +20,16 @@ namespace llvm { class FunctionPass; -class TargetMachine; +class PPCTargetMachine; enum PPCTargetEnum { TargetDefault, TargetAIX, TargetDarwin }; FunctionPass *createPPCBranchSelectionPass(); -FunctionPass *createPPCISelDag(TargetMachine &TM); -FunctionPass *createDarwinAsmPrinter(std::ostream &OS, TargetMachine &TM); -FunctionPass *createAIXAsmPrinter(std::ostream &OS, TargetMachine &TM); +FunctionPass *createPPCISelDag(PPCTargetMachine &TM); +FunctionPass *createDarwinAsmPrinter(std::ostream &OS, PPCTargetMachine &TM); +FunctionPass *createAIXAsmPrinter(std::ostream &OS, PPCTargetMachine &TM); extern PPCTargetEnum PPCTarget; } // end namespace llvm; Index: llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp diff -u llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp:1.157 llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp:1.158 --- llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp:1.157 Tue Mar 7 16:00:35 2006 +++ llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp Mon Mar 13 17:20:37 2006 @@ -307,7 +307,8 @@ /// code for a MachineFunction to the given output stream, in a format that the /// Darwin assembler can deal with. /// -FunctionPass *llvm::createDarwinAsmPrinter(std::ostream &o, TargetMachine &tm) { +FunctionPass *llvm::createDarwinAsmPrinter(std::ostream &o, + PPCTargetMachine &tm) { return new DarwinAsmPrinter(o, tm); } @@ -315,7 +316,7 @@ /// for a MachineFunction to the given output stream, in a format that the /// AIX 5L assembler can deal with. /// -FunctionPass *llvm::createAIXAsmPrinter(std::ostream &o, TargetMachine &tm) { +FunctionPass *llvm::createAIXAsmPrinter(std::ostream &o, PPCTargetMachine &tm) { return new AIXAsmPrinter(o, tm); } Index: llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp diff -u llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp:1.165 llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp:1.166 --- llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp:1.165 Mon Mar 13 15:52:10 2006 +++ llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp Mon Mar 13 17:20:37 2006 @@ -42,8 +42,9 @@ PPCTargetLowering PPCLowering; unsigned GlobalBaseReg; public: - PPCDAGToDAGISel(TargetMachine &TM) - : SelectionDAGISel(PPCLowering), PPCLowering(TM) {} + PPCDAGToDAGISel(PPCTargetMachine &TM) + : SelectionDAGISel(PPCLowering), + PPCLowering(*TM.getTargetLowering()){} virtual bool runOnFunction(Function &Fn) { // Make sure we re-emit a set of the global base reg if necessary @@ -1140,7 +1141,7 @@ /// createPPCISelDag - This pass converts a legalized DAG into a /// PowerPC-specific DAG, ready for instruction scheduling. /// -FunctionPass *llvm::createPPCISelDag(TargetMachine &TM) { +FunctionPass *llvm::createPPCISelDag(PPCTargetMachine &TM) { return new PPCDAGToDAGISel(TM); } Index: llvm/lib/Target/PowerPC/PPCISelLowering.cpp diff -u llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.95 llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.96 --- llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.95 Sat Mar 4 23:08:37 2006 +++ llvm/lib/Target/PowerPC/PPCISelLowering.cpp Mon Mar 13 17:20:37 2006 @@ -14,6 +14,7 @@ #include "PPCISelLowering.h" #include "PPCTargetMachine.h" #include "llvm/ADT/VectorExtras.h" +#include "llvm/Analysis/ScalarEvolutionExpressions.h" #include "llvm/CodeGen/MachineFrameInfo.h" #include "llvm/CodeGen/MachineFunction.h" #include "llvm/CodeGen/MachineInstrBuilder.h" @@ -1174,3 +1175,10 @@ // Handle standard constraint letters. return TargetLowering::isOperandValidForConstraint(Op, Letter); } + +/// isLegalAddressImmediate - Return true if the integer value can be used +/// as the offset of the target addressing mode. +bool PPCTargetLowering::isLegalAddressImmediate(int64_t V) const { + // PPC allows a sign-extended 16-bit immediate field. + return (V > -(1 << 16) && V < (1 << 16)-1); +} Index: llvm/lib/Target/PowerPC/PPCISelLowering.h diff -u llvm/lib/Target/PowerPC/PPCISelLowering.h:1.25 llvm/lib/Target/PowerPC/PPCISelLowering.h:1.26 --- llvm/lib/Target/PowerPC/PPCISelLowering.h:1.25 Tue Feb 28 23:50:56 2006 +++ llvm/lib/Target/PowerPC/PPCISelLowering.h Mon Mar 13 17:20:37 2006 @@ -109,6 +109,10 @@ getRegClassForInlineAsmConstraint(const std::string &Constraint, MVT::ValueType VT) const; bool isOperandValidForConstraint(SDOperand Op, char ConstraintLetter); + + /// isLegalAddressImmediate - Return true if the integer value can be used + /// as the offset of the target addressing mode. + virtual bool isLegalAddressImmediate(int64_t V) const; }; } Index: llvm/lib/Target/PowerPC/PPCJITInfo.h diff -u llvm/lib/Target/PowerPC/PPCJITInfo.h:1.8 llvm/lib/Target/PowerPC/PPCJITInfo.h:1.9 --- llvm/lib/Target/PowerPC/PPCJITInfo.h:1.8 Sun Oct 16 00:39:50 2005 +++ llvm/lib/Target/PowerPC/PPCJITInfo.h Mon Mar 13 17:20:37 2006 @@ -17,13 +17,13 @@ #include "llvm/Target/TargetJITInfo.h" namespace llvm { - class TargetMachine; + class PPCTargetMachine; class PPCJITInfo : public TargetJITInfo { protected: - TargetMachine &TM; + PPCTargetMachine &TM; public: - PPCJITInfo(TargetMachine &tm) : TM(tm) {useGOT = 0;} + PPCJITInfo(PPCTargetMachine &tm) : TM(tm) {useGOT = 0;} /// addPassesToJITCompile - Add passes to the specified pass manager to /// implement a fast dynamic compiler for this target. Return true if this Index: llvm/lib/Target/PowerPC/PPCTargetMachine.cpp diff -u llvm/lib/Target/PowerPC/PPCTargetMachine.cpp:1.81 llvm/lib/Target/PowerPC/PPCTargetMachine.cpp:1.82 --- llvm/lib/Target/PowerPC/PPCTargetMachine.cpp:1.81 Thu Feb 23 16:18:07 2006 +++ llvm/lib/Target/PowerPC/PPCTargetMachine.cpp Mon Mar 13 17:20:37 2006 @@ -62,7 +62,7 @@ const std::string &FS) : TargetMachine("PowerPC", IL, false, 4, 4, 4, 4, 4, 4, 2, 1, 1), Subtarget(M, FS), FrameInfo(*this, false), JITInfo(*this), - InstrItins(Subtarget.getInstrItineraryData()) { + TLInfo(*this), InstrItins(Subtarget.getInstrItineraryData()) { if (TargetDefault == PPCTarget) { if (Subtarget.isAIX()) PPCTarget = TargetAIX; if (Subtarget.isDarwin()) PPCTarget = TargetDarwin; Index: llvm/lib/Target/PowerPC/PPCTargetMachine.h diff -u llvm/lib/Target/PowerPC/PPCTargetMachine.h:1.16 llvm/lib/Target/PowerPC/PPCTargetMachine.h:1.17 --- llvm/lib/Target/PowerPC/PPCTargetMachine.h:1.16 Mon Nov 7 20:12:47 2005 +++ llvm/lib/Target/PowerPC/PPCTargetMachine.h Mon Mar 13 17:20:37 2006 @@ -18,6 +18,7 @@ #include "PPCSubtarget.h" #include "PPCJITInfo.h" #include "PPCInstrInfo.h" +#include "PPCISelLowering.h" #include "llvm/Target/TargetMachine.h" namespace llvm { @@ -31,6 +32,7 @@ PPCSubtarget Subtarget; PPCFrameInfo FrameInfo; PPCJITInfo JITInfo; + PPCTargetLowering TLInfo; InstrItineraryData InstrItins; public: PPCTargetMachine(const Module &M, IntrinsicLowering *IL, @@ -40,6 +42,7 @@ virtual const TargetFrameInfo *getFrameInfo() const { return &FrameInfo; } virtual TargetJITInfo *getJITInfo() { return &JITInfo; } virtual const TargetSubtarget *getSubtargetImpl() const{ return &Subtarget; } + virtual PPCTargetLowering *getTargetLowering() { return &TLInfo; } virtual const MRegisterInfo *getRegisterInfo() const { return &InstrInfo.getRegisterInfo(); } From evan.cheng at apple.com Mon Mar 13 17:20:51 2006 From: evan.cheng at apple.com (Evan Cheng) Date: Mon, 13 Mar 2006 17:20:51 -0600 Subject: [llvm-commits] CVS: llvm/lib/Target/X86/X86.h X86ATTAsmPrinter.cpp X86ATTAsmPrinter.h X86AsmPrinter.cpp X86AsmPrinter.h X86ELFWriter.cpp X86ISelDAGToDAG.cpp X86ISelLowering.h X86IntelAsmPrinter.cpp X86IntelAsmPrinter.h X86JITInfo.h X86TargetMachine.cpp X86TargetMachine.h Message-ID: <200603132320.RAA32343@zion.cs.uiuc.edu> Changes in directory llvm/lib/Target/X86: X86.h updated: 1.44 -> 1.45 X86ATTAsmPrinter.cpp updated: 1.30 -> 1.31 X86ATTAsmPrinter.h updated: 1.9 -> 1.10 X86AsmPrinter.cpp updated: 1.170 -> 1.171 X86AsmPrinter.h updated: 1.13 -> 1.14 X86ELFWriter.cpp updated: 1.2 -> 1.3 X86ISelDAGToDAG.cpp updated: 1.55 -> 1.56 X86ISelLowering.h updated: 1.32 -> 1.33 X86IntelAsmPrinter.cpp updated: 1.23 -> 1.24 X86IntelAsmPrinter.h updated: 1.10 -> 1.11 X86JITInfo.h updated: 1.7 -> 1.8 X86TargetMachine.cpp updated: 1.106 -> 1.107 X86TargetMachine.h updated: 1.31 -> 1.32 --- Log message: Added getTargetLowering() to TargetMachine. Refactored targets to support this. --- Diffs of the changes: (+45 -37) X86.h | 8 ++++---- X86ATTAsmPrinter.cpp | 1 - X86ATTAsmPrinter.h | 4 +--- X86AsmPrinter.cpp | 10 +++++----- X86AsmPrinter.h | 5 ++--- X86ELFWriter.cpp | 6 +++--- X86ISelDAGToDAG.cpp | 10 ++++++---- X86ISelLowering.h | 6 ++++++ X86IntelAsmPrinter.cpp | 1 - X86IntelAsmPrinter.h | 5 +---- X86JITInfo.h | 6 +++--- X86TargetMachine.cpp | 8 ++++++-- X86TargetMachine.h | 12 ++++++++---- 13 files changed, 45 insertions(+), 37 deletions(-) Index: llvm/lib/Target/X86/X86.h diff -u llvm/lib/Target/X86/X86.h:1.44 llvm/lib/Target/X86/X86.h:1.45 --- llvm/lib/Target/X86/X86.h:1.44 Thu Feb 16 18:03:04 2006 +++ llvm/lib/Target/X86/X86.h Mon Mar 13 17:20:37 2006 @@ -19,7 +19,7 @@ namespace llvm { -class TargetMachine; +class X86TargetMachine; class PassManager; class FunctionPass; class IntrinsicLowering; @@ -28,7 +28,7 @@ /// createX86ISelDag - This pass converts a legalized DAG into a /// X86-specific DAG, ready for instruction scheduling. /// -FunctionPass *createX86ISelDag(TargetMachine &TM); +FunctionPass *createX86ISelDag(X86TargetMachine &TM); /// createX86FloatingPointStackifierPass - This function returns a pass which /// converts floating point register references and pseudo instructions into @@ -40,7 +40,7 @@ /// assembly code for a MachineFunction to the given output stream, /// using the given target machine description. /// -FunctionPass *createX86CodePrinterPass(std::ostream &o, TargetMachine &tm); +FunctionPass *createX86CodePrinterPass(std::ostream &o, X86TargetMachine &tm); /// createX86CodeEmitterPass - Return a pass that emits the collected X86 code /// to the specified MCE object. @@ -50,7 +50,7 @@ /// code as an ELF object file. /// void addX86ELFObjectWriterPass(PassManager &FPM, - std::ostream &o, TargetMachine &tm); + std::ostream &o, X86TargetMachine &tm); /// createX86EmitCodeToMemory - Returns a pass that converts a register /// allocated function into raw machine code in a dynamically Index: llvm/lib/Target/X86/X86ATTAsmPrinter.cpp diff -u llvm/lib/Target/X86/X86ATTAsmPrinter.cpp:1.30 llvm/lib/Target/X86/X86ATTAsmPrinter.cpp:1.31 --- llvm/lib/Target/X86/X86ATTAsmPrinter.cpp:1.30 Mon Mar 6 20:23:26 2006 +++ llvm/lib/Target/X86/X86ATTAsmPrinter.cpp Mon Mar 13 17:20:37 2006 @@ -21,7 +21,6 @@ #include "llvm/Target/TargetOptions.h" #include using namespace llvm; -using namespace x86; /// runOnMachineFunction - This uses the printMachineInstruction() /// method to print assembly for each instruction. Index: llvm/lib/Target/X86/X86ATTAsmPrinter.h diff -u llvm/lib/Target/X86/X86ATTAsmPrinter.h:1.9 llvm/lib/Target/X86/X86ATTAsmPrinter.h:1.10 --- llvm/lib/Target/X86/X86ATTAsmPrinter.h:1.9 Mon Mar 6 20:02:57 2006 +++ llvm/lib/Target/X86/X86ATTAsmPrinter.h Mon Mar 13 17:20:37 2006 @@ -18,10 +18,9 @@ #include "llvm/CodeGen/ValueTypes.h" namespace llvm { -namespace x86 { struct X86ATTAsmPrinter : public X86SharedAsmPrinter { - X86ATTAsmPrinter(std::ostream &O, TargetMachine &TM) + X86ATTAsmPrinter(std::ostream &O, X86TargetMachine &TM) : X86SharedAsmPrinter(O, TM) { } virtual const char *getPassName() const { @@ -69,7 +68,6 @@ bool runOnMachineFunction(MachineFunction &F); }; -} // end namespace x86 } // end namespace llvm #endif Index: llvm/lib/Target/X86/X86AsmPrinter.cpp diff -u llvm/lib/Target/X86/X86AsmPrinter.cpp:1.170 llvm/lib/Target/X86/X86AsmPrinter.cpp:1.171 --- llvm/lib/Target/X86/X86AsmPrinter.cpp:1.170 Tue Mar 7 16:00:35 2006 +++ llvm/lib/Target/X86/X86AsmPrinter.cpp Mon Mar 13 17:20:37 2006 @@ -14,10 +14,10 @@ // //===----------------------------------------------------------------------===// +#include "X86AsmPrinter.h" #include "X86ATTAsmPrinter.h" #include "X86IntelAsmPrinter.h" #include "X86Subtarget.h" -#include "X86.h" #include "llvm/Constants.h" #include "llvm/Module.h" #include "llvm/Type.h" @@ -25,10 +25,9 @@ #include "llvm/Support/Mangler.h" #include "llvm/Support/CommandLine.h" using namespace llvm; -using namespace x86; -Statistic<> llvm::x86::EmittedInsts("asm-printer", - "Number of machine instrs printed"); +Statistic<> llvm::EmittedInsts("asm-printer", + "Number of machine instrs printed"); enum AsmWriterFlavorTy { att, intel }; cl::opt @@ -210,7 +209,8 @@ /// for a MachineFunction to the given output stream, using the given target /// machine description. /// -FunctionPass *llvm::createX86CodePrinterPass(std::ostream &o,TargetMachine &tm){ +FunctionPass *llvm::createX86CodePrinterPass(std::ostream &o, + X86TargetMachine &tm){ switch (AsmWriterFlavor) { default: assert(0 && "Unknown asm flavor!"); Index: llvm/lib/Target/X86/X86AsmPrinter.h diff -u llvm/lib/Target/X86/X86AsmPrinter.h:1.13 llvm/lib/Target/X86/X86AsmPrinter.h:1.14 --- llvm/lib/Target/X86/X86AsmPrinter.h:1.13 Mon Mar 6 20:23:26 2006 +++ llvm/lib/Target/X86/X86AsmPrinter.h Mon Mar 13 17:20:37 2006 @@ -17,6 +17,7 @@ #define X86ASMPRINTER_H #include "X86.h" +#include "X86TargetMachine.h" #include "llvm/CodeGen/AsmPrinter.h" #include "llvm/CodeGen/DwarfWriter.h" #include "llvm/CodeGen/MachineDebugInfo.h" @@ -25,7 +26,6 @@ namespace llvm { -namespace x86 { extern Statistic<> EmittedInsts; @@ -56,7 +56,7 @@ struct X86SharedAsmPrinter : public AsmPrinter { X86DwarfWriter DW; - X86SharedAsmPrinter(std::ostream &O, TargetMachine &TM) + X86SharedAsmPrinter(std::ostream &O, X86TargetMachine &TM) : AsmPrinter(O, TM), DW(O, this), forDarwin(false) { } bool doInitialization(Module &M); @@ -90,7 +90,6 @@ } }; -} // end namespace x86 } // end namespace llvm #endif Index: llvm/lib/Target/X86/X86ELFWriter.cpp diff -u llvm/lib/Target/X86/X86ELFWriter.cpp:1.2 llvm/lib/Target/X86/X86ELFWriter.cpp:1.3 --- llvm/lib/Target/X86/X86ELFWriter.cpp:1.2 Mon Jul 11 00:17:48 2005 +++ llvm/lib/Target/X86/X86ELFWriter.cpp Mon Mar 13 17:20:37 2006 @@ -13,15 +13,15 @@ //===----------------------------------------------------------------------===// #include "X86.h" +#include "X86TargetMachine.h" #include "llvm/PassManager.h" #include "llvm/CodeGen/ELFWriter.h" -#include "llvm/Target/TargetMachine.h" using namespace llvm; namespace { class X86ELFWriter : public ELFWriter { public: - X86ELFWriter(std::ostream &O, TargetMachine &TM) : ELFWriter(O, TM) { + X86ELFWriter(std::ostream &O, X86TargetMachine &TM) : ELFWriter(O, TM) { e_machine = 3; // EM_386 } }; @@ -31,7 +31,7 @@ /// as an ELF object file. /// void llvm::addX86ELFObjectWriterPass(PassManager &FPM, - std::ostream &O, TargetMachine &TM) { + std::ostream &O, X86TargetMachine &TM) { X86ELFWriter *EW = new X86ELFWriter(O, TM); FPM.add(EW); FPM.add(createX86CodeEmitterPass(EW->getMachineCodeEmitter())); Index: llvm/lib/Target/X86/X86ISelDAGToDAG.cpp diff -u llvm/lib/Target/X86/X86ISelDAGToDAG.cpp:1.55 llvm/lib/Target/X86/X86ISelDAGToDAG.cpp:1.56 --- llvm/lib/Target/X86/X86ISelDAGToDAG.cpp:1.55 Tue Feb 28 15:13:57 2006 +++ llvm/lib/Target/X86/X86ISelDAGToDAG.cpp Mon Mar 13 17:20:37 2006 @@ -15,9 +15,10 @@ #define DEBUG_TYPE "isel" #include "X86.h" #include "X86InstrBuilder.h" +#include "X86ISelLowering.h" #include "X86RegisterInfo.h" #include "X86Subtarget.h" -#include "X86ISelLowering.h" +#include "X86TargetMachine.h" #include "llvm/GlobalValue.h" #include "llvm/Instructions.h" #include "llvm/Support/CFG.h" @@ -90,8 +91,9 @@ unsigned GlobalBaseReg; public: - X86DAGToDAGISel(TargetMachine &TM) - : SelectionDAGISel(X86Lowering), X86Lowering(TM) { + X86DAGToDAGISel(X86TargetMachine &TM) + : SelectionDAGISel(X86Lowering), + X86Lowering(*TM.getTargetLowering()) { Subtarget = &TM.getSubtarget(); } @@ -842,6 +844,6 @@ /// createX86ISelDag - This pass converts a legalized DAG into a /// X86-specific DAG, ready for instruction scheduling. /// -FunctionPass *llvm::createX86ISelDag(TargetMachine &TM) { +FunctionPass *llvm::createX86ISelDag(X86TargetMachine &TM) { return new X86DAGToDAGISel(TM); } Index: llvm/lib/Target/X86/X86ISelLowering.h diff -u llvm/lib/Target/X86/X86ISelLowering.h:1.32 llvm/lib/Target/X86/X86ISelLowering.h:1.33 --- llvm/lib/Target/X86/X86ISelLowering.h:1.32 Thu Feb 23 14:41:18 2006 +++ llvm/lib/Target/X86/X86ISelLowering.h Mon Mar 13 17:20:37 2006 @@ -230,6 +230,12 @@ std::vector getRegClassForInlineAsmConstraint(const std::string &Constraint, MVT::ValueType VT) const; + + /// isLegalAddressImmediate - Return true if the integer value or + /// GlobalValue can be used as the offset of the target addressing mode. + virtual bool isLegalAddressImmediate(int64_t V) const; + virtual bool isLegalAddressImmediate(GlobalValue *GV) const; + private: // C Calling Convention implementation. std::vector LowerCCCArguments(Function &F, SelectionDAG &DAG); Index: llvm/lib/Target/X86/X86IntelAsmPrinter.cpp diff -u llvm/lib/Target/X86/X86IntelAsmPrinter.cpp:1.23 llvm/lib/Target/X86/X86IntelAsmPrinter.cpp:1.24 --- llvm/lib/Target/X86/X86IntelAsmPrinter.cpp:1.23 Mon Mar 6 20:23:26 2006 +++ llvm/lib/Target/X86/X86IntelAsmPrinter.cpp Mon Mar 13 17:20:37 2006 @@ -20,7 +20,6 @@ #include "llvm/Support/Mangler.h" #include "llvm/Target/TargetOptions.h" using namespace llvm; -using namespace x86; /// runOnMachineFunction - This uses the printMachineInstruction() /// method to print assembly for each instruction. Index: llvm/lib/Target/X86/X86IntelAsmPrinter.h diff -u llvm/lib/Target/X86/X86IntelAsmPrinter.h:1.10 llvm/lib/Target/X86/X86IntelAsmPrinter.h:1.11 --- llvm/lib/Target/X86/X86IntelAsmPrinter.h:1.10 Mon Mar 6 20:02:57 2006 +++ llvm/lib/Target/X86/X86IntelAsmPrinter.h Mon Mar 13 17:20:37 2006 @@ -16,14 +16,12 @@ #include "X86AsmPrinter.h" #include "llvm/CodeGen/ValueTypes.h" -#include "llvm/Target/TargetMachine.h" #include "llvm/Target/MRegisterInfo.h" namespace llvm { -namespace x86 { struct X86IntelAsmPrinter : public X86SharedAsmPrinter { - X86IntelAsmPrinter(std::ostream &O, TargetMachine &TM) + X86IntelAsmPrinter(std::ostream &O, X86TargetMachine &TM) : X86SharedAsmPrinter(O, TM) { } virtual const char *getPassName() const { @@ -91,7 +89,6 @@ bool doInitialization(Module &M); }; -} // end namespace x86 } // end namespace llvm #endif Index: llvm/lib/Target/X86/X86JITInfo.h diff -u llvm/lib/Target/X86/X86JITInfo.h:1.7 llvm/lib/Target/X86/X86JITInfo.h:1.8 --- llvm/lib/Target/X86/X86JITInfo.h:1.7 Fri Jul 29 18:32:02 2005 +++ llvm/lib/Target/X86/X86JITInfo.h Mon Mar 13 17:20:37 2006 @@ -17,13 +17,13 @@ #include "llvm/Target/TargetJITInfo.h" namespace llvm { - class TargetMachine; + class X86TargetMachine; class IntrinsicLowering; class X86JITInfo : public TargetJITInfo { - TargetMachine &TM; + X86TargetMachine &TM; public: - X86JITInfo(TargetMachine &tm) : TM(tm) {useGOT = 0;} + X86JITInfo(X86TargetMachine &tm) : TM(tm) {useGOT = 0;} /// addPassesToJITCompile - Add passes to the specified pass manager to /// implement a fast dynamic compiler for this target. Return true if this Index: llvm/lib/Target/X86/X86TargetMachine.cpp diff -u llvm/lib/Target/X86/X86TargetMachine.cpp:1.106 llvm/lib/Target/X86/X86TargetMachine.cpp:1.107 --- llvm/lib/Target/X86/X86TargetMachine.cpp:1.106 Thu Mar 9 15:51:28 2006 +++ llvm/lib/Target/X86/X86TargetMachine.cpp Mon Mar 13 17:20:37 2006 @@ -79,7 +79,7 @@ Subtarget(M, FS), FrameInfo(TargetFrameInfo::StackGrowsDown, Subtarget.getStackAlignment(), -4), - JITInfo(*this) { + JITInfo(*this), TLInfo(*this) { if (getRelocationModel() == Reloc::Default) if (Subtarget.isTargetDarwin()) setRelocationModel(Reloc::DynamicNoPIC); @@ -97,7 +97,7 @@ FileType != TargetMachine::ObjectFile) return true; // Run loop strength reduction before anything else. - if (EnableX86LSR) PM.add(createLoopStrengthReducePass()); + if (EnableX86LSR) PM.add(createLoopStrengthReducePass(1, &TLInfo)); // FIXME: Implement efficient support for garbage collection intrinsics. PM.add(createLowerGCPass()); @@ -164,6 +164,10 @@ // The JIT should use static relocation model. TM.setRelocationModel(Reloc::Static); + // Run loop strength reduction before anything else. + if (EnableX86LSR) + PM.add(createLoopStrengthReducePass(1, TM.getTargetLowering())); + // FIXME: Implement efficient support for garbage collection intrinsics. PM.add(createLowerGCPass()); Index: llvm/lib/Target/X86/X86TargetMachine.h diff -u llvm/lib/Target/X86/X86TargetMachine.h:1.31 llvm/lib/Target/X86/X86TargetMachine.h:1.32 --- llvm/lib/Target/X86/X86TargetMachine.h:1.31 Mon Nov 7 20:11:51 2005 +++ llvm/lib/Target/X86/X86TargetMachine.h Mon Mar 13 17:20:37 2006 @@ -17,18 +17,21 @@ #include "llvm/Target/TargetMachine.h" #include "llvm/Target/TargetFrameInfo.h" #include "llvm/PassManager.h" +#include "X86.h" #include "X86InstrInfo.h" #include "X86JITInfo.h" #include "X86Subtarget.h" +#include "X86ISelLowering.h" namespace llvm { class IntrinsicLowering; class X86TargetMachine : public TargetMachine { - X86InstrInfo InstrInfo; - X86Subtarget Subtarget; - TargetFrameInfo FrameInfo; - X86JITInfo JITInfo; + X86InstrInfo InstrInfo; + X86Subtarget Subtarget; + TargetFrameInfo FrameInfo; + X86JITInfo JITInfo; + X86TargetLowering TLInfo; public: X86TargetMachine(const Module &M, IntrinsicLowering *IL, const std::string &FS); @@ -37,6 +40,7 @@ virtual const TargetFrameInfo *getFrameInfo() const { return &FrameInfo; } virtual TargetJITInfo *getJITInfo() { return &JITInfo; } virtual const TargetSubtarget *getSubtargetImpl() const{ return &Subtarget; } + virtual X86TargetLowering *getTargetLowering() { return &TLInfo; } virtual const MRegisterInfo *getRegisterInfo() const { return &InstrInfo.getRegisterInfo(); } From evan.cheng at apple.com Mon Mar 13 17:20:51 2006 From: evan.cheng at apple.com (Evan Cheng) Date: Mon, 13 Mar 2006 17:20:51 -0600 Subject: [llvm-commits] CVS: llvm/lib/Target/IA64/IA64.h IA64AsmPrinter.cpp IA64Bundling.cpp IA64ISelDAGToDAG.cpp IA64TargetMachine.cpp IA64TargetMachine.h Message-ID: <200603132320.RAA32323@zion.cs.uiuc.edu> Changes in directory llvm/lib/Target/IA64: IA64.h updated: 1.4 -> 1.5 IA64AsmPrinter.cpp updated: 1.24 -> 1.25 IA64Bundling.cpp updated: 1.2 -> 1.3 IA64ISelDAGToDAG.cpp updated: 1.37 -> 1.38 IA64TargetMachine.cpp updated: 1.11 -> 1.12 IA64TargetMachine.h updated: 1.5 -> 1.6 --- Log message: Added getTargetLowering() to TargetMachine. Refactored targets to support this. --- Diffs of the changes: (+22 -16) IA64.h | 8 ++++---- IA64AsmPrinter.cpp | 3 ++- IA64Bundling.cpp | 6 +++--- IA64ISelDAGToDAG.cpp | 7 ++++--- IA64TargetMachine.cpp | 3 ++- IA64TargetMachine.h | 11 +++++++---- 6 files changed, 22 insertions(+), 16 deletions(-) Index: llvm/lib/Target/IA64/IA64.h diff -u llvm/lib/Target/IA64/IA64.h:1.4 llvm/lib/Target/IA64/IA64.h:1.5 --- llvm/lib/Target/IA64/IA64.h:1.4 Tue Jan 24 20:23:38 2006 +++ llvm/lib/Target/IA64/IA64.h Mon Mar 13 17:20:37 2006 @@ -18,26 +18,26 @@ namespace llvm { -class TargetMachine; +class IA64TargetMachine; class FunctionPass; class IntrinsicLowering; /// createIA64DAGToDAGInstructionSelector - This pass converts an LLVM /// function into IA64 machine code in a sane, DAG->DAG transform. /// -FunctionPass *createIA64DAGToDAGInstructionSelector(TargetMachine &TM); +FunctionPass *createIA64DAGToDAGInstructionSelector(IA64TargetMachine &TM); /// createIA64BundlingPass - This pass adds stop bits and bundles /// instructions. /// -FunctionPass *createIA64BundlingPass(TargetMachine &TM); +FunctionPass *createIA64BundlingPass(IA64TargetMachine &TM); /// createIA64CodePrinterPass - Returns a pass that prints the IA64 /// assembly code for a MachineFunction to the given output stream, /// using the given target machine description. This should work /// regardless of whether the function is in SSA form. /// -FunctionPass *createIA64CodePrinterPass(std::ostream &o,TargetMachine &tm); +FunctionPass *createIA64CodePrinterPass(std::ostream &o, IA64TargetMachine &tm); } // End llvm namespace Index: llvm/lib/Target/IA64/IA64AsmPrinter.cpp diff -u llvm/lib/Target/IA64/IA64AsmPrinter.cpp:1.24 llvm/lib/Target/IA64/IA64AsmPrinter.cpp:1.25 --- llvm/lib/Target/IA64/IA64AsmPrinter.cpp:1.24 Thu Mar 9 00:14:35 2006 +++ llvm/lib/Target/IA64/IA64AsmPrinter.cpp Mon Mar 13 17:20:37 2006 @@ -374,7 +374,8 @@ /// assembly code for a MachineFunction to the given output stream, using /// the given target machine description. /// -FunctionPass *llvm::createIA64CodePrinterPass(std::ostream &o,TargetMachine &tm){ +FunctionPass *llvm::createIA64CodePrinterPass(std::ostream &o, + IA64TargetMachine &tm) { return new IA64AsmPrinter(o, tm); } Index: llvm/lib/Target/IA64/IA64Bundling.cpp diff -u llvm/lib/Target/IA64/IA64Bundling.cpp:1.2 llvm/lib/Target/IA64/IA64Bundling.cpp:1.3 --- llvm/lib/Target/IA64/IA64Bundling.cpp:1.2 Thu Jan 26 03:08:31 2006 +++ llvm/lib/Target/IA64/IA64Bundling.cpp Mon Mar 13 17:20:37 2006 @@ -37,9 +37,9 @@ /// Target machine description which we query for reg. names, data /// layout, etc. /// - TargetMachine &TM; + IA64TargetMachine &TM; - IA64BundlingPass(TargetMachine &tm) : TM(tm) { } + IA64BundlingPass(IA64TargetMachine &tm) : TM(tm) { } virtual const char *getPassName() const { return "IA64 (Itanium) Bundling Pass"; @@ -64,7 +64,7 @@ /// createIA64BundlingPass - Returns a pass that adds STOP (;;) instructions /// and arranges the result into bundles. /// -FunctionPass *llvm::createIA64BundlingPass(TargetMachine &tm) { +FunctionPass *llvm::createIA64BundlingPass(IA64TargetMachine &tm) { return new IA64BundlingPass(tm); } Index: llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp diff -u llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp:1.37 llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp:1.38 --- llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp:1.37 Sat Feb 11 01:33:17 2006 +++ llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp Mon Mar 13 17:20:37 2006 @@ -42,8 +42,8 @@ IA64TargetLowering IA64Lowering; unsigned GlobalBaseReg; public: - IA64DAGToDAGISel(TargetMachine &TM) - : SelectionDAGISel(IA64Lowering), IA64Lowering(TM) {} + IA64DAGToDAGISel(IA64TargetMachine &TM) + : SelectionDAGISel(IA64Lowering), IA64Lowering(*TM.getTargetLowering()) {} virtual bool runOnFunction(Function &Fn) { // Make sure we re-emit a set of the global base reg if necessary @@ -621,7 +621,8 @@ /// createIA64DAGToDAGInstructionSelector - This pass converts a legalized DAG /// into an IA64-specific DAG, ready for instruction scheduling. /// -FunctionPass *llvm::createIA64DAGToDAGInstructionSelector(TargetMachine &TM) { +FunctionPass +*llvm::createIA64DAGToDAGInstructionSelector(IA64TargetMachine &TM) { return new IA64DAGToDAGISel(TM); } Index: llvm/lib/Target/IA64/IA64TargetMachine.cpp diff -u llvm/lib/Target/IA64/IA64TargetMachine.cpp:1.11 llvm/lib/Target/IA64/IA64TargetMachine.cpp:1.12 --- llvm/lib/Target/IA64/IA64TargetMachine.cpp:1.11 Tue Jan 24 20:23:38 2006 +++ llvm/lib/Target/IA64/IA64TargetMachine.cpp Mon Mar 13 17:20:37 2006 @@ -79,7 +79,8 @@ IA64TargetMachine::IA64TargetMachine(const Module &M, IntrinsicLowering *IL, const std::string &FS) : TargetMachine("IA64", IL, true), - FrameInfo(TargetFrameInfo::StackGrowsDown, 16, 0) { // FIXME? check this stuff + FrameInfo(TargetFrameInfo::StackGrowsDown, 16, 0), + TLInfo(*this) { // FIXME? check this stuff } // addPassesToEmitFile - We currently use all of the same passes as the JIT Index: llvm/lib/Target/IA64/IA64TargetMachine.h diff -u llvm/lib/Target/IA64/IA64TargetMachine.h:1.5 llvm/lib/Target/IA64/IA64TargetMachine.h:1.6 --- llvm/lib/Target/IA64/IA64TargetMachine.h:1.5 Mon Nov 7 20:11:51 2005 +++ llvm/lib/Target/IA64/IA64TargetMachine.h Mon Mar 13 17:20:37 2006 @@ -18,20 +18,23 @@ #include "llvm/Target/TargetFrameInfo.h" #include "llvm/PassManager.h" #include "IA64InstrInfo.h" +#include "IA64ISelLowering.h" namespace llvm { class IntrinsicLowering; class IA64TargetMachine : public TargetMachine { - IA64InstrInfo InstrInfo; - TargetFrameInfo FrameInfo; + IA64InstrInfo InstrInfo; + TargetFrameInfo FrameInfo; //IA64JITInfo JITInfo; + IA64TargetLowering TLInfo; public: IA64TargetMachine(const Module &M, IntrinsicLowering *IL, const std::string &FS); - virtual const IA64InstrInfo *getInstrInfo() const { return &InstrInfo; } - virtual const TargetFrameInfo *getFrameInfo() const { return &FrameInfo; } + virtual const IA64InstrInfo *getInstrInfo() const { return &InstrInfo; } + virtual const TargetFrameInfo *getFrameInfo() const { return &FrameInfo; } + virtual IA64TargetLowering *getTargetLowering() { return &TLInfo; } virtual const MRegisterInfo *getRegisterInfo() const { return &InstrInfo.getRegisterInfo(); } From evan.cheng at apple.com Mon Mar 13 17:57:03 2006 From: evan.cheng at apple.com (Evan Cheng) Date: Mon, 13 Mar 2006 17:57:03 -0600 Subject: [llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCTargetMachine.cpp Message-ID: <200603132357.RAA32683@zion.cs.uiuc.edu> Changes in directory llvm/lib/Target/PowerPC: PPCTargetMachine.cpp updated: 1.82 -> 1.83 --- Log message: PPC LSR pass should use target lowering hooks. --- Diffs of the changes: (+2 -2) PPCTargetMachine.cpp | 4 ++-- 1 files changed, 2 insertions(+), 2 deletions(-) Index: llvm/lib/Target/PowerPC/PPCTargetMachine.cpp diff -u llvm/lib/Target/PowerPC/PPCTargetMachine.cpp:1.82 llvm/lib/Target/PowerPC/PPCTargetMachine.cpp:1.83 --- llvm/lib/Target/PowerPC/PPCTargetMachine.cpp:1.82 Mon Mar 13 17:20:37 2006 +++ llvm/lib/Target/PowerPC/PPCTargetMachine.cpp Mon Mar 13 17:56:51 2006 @@ -84,7 +84,7 @@ if (FileType != TargetMachine::AssemblyFile) return true; // Run loop strength reduction before anything else. - if (!Fast) PM.add(createLoopStrengthReducePass()); + if (!Fast) PM.add(createLoopStrengthReducePass(1, &TLInfo)); // FIXME: Implement efficient support for garbage collection intrinsics. PM.add(createLowerGCPass()); @@ -138,7 +138,7 @@ TM.setRelocationModel(Reloc::DynamicNoPIC); // Run loop strength reduction before anything else. - PM.add(createLoopStrengthReducePass()); + PM.add(createLoopStrengthReducePass(1, TM.getTargetLowering())); // FIXME: Implement efficient support for garbage collection intrinsics. PM.add(createLowerGCPass()); From jlaskey at apple.com Mon Mar 13 19:53:22 2006 From: jlaskey at apple.com (Jim Laskey) Date: Mon, 13 Mar 2006 19:53:22 -0600 Subject: [llvm-commits] CVS: llvm/test/Regression/CodeGen/Generic/DebugStuff.ll Message-ID: <200603140153.TAA01172@zion.cs.uiuc.edu> Changes in directory llvm/test/Regression/CodeGen/Generic: DebugStuff.ll updated: 1.4 -> 1.5 --- Log message: Remove the use of llvm.dbg.declare. --- Diffs of the changes: (+3 -6) DebugStuff.ll | 9 +++------ 1 files changed, 3 insertions(+), 6 deletions(-) Index: llvm/test/Regression/CodeGen/Generic/DebugStuff.ll diff -u llvm/test/Regression/CodeGen/Generic/DebugStuff.ll:1.4 llvm/test/Regression/CodeGen/Generic/DebugStuff.ll:1.5 --- llvm/test/Regression/CodeGen/Generic/DebugStuff.ll:1.4 Wed Feb 15 11:20:59 2006 +++ llvm/test/Regression/CodeGen/Generic/DebugStuff.ll Mon Mar 13 19:53:11 2006 @@ -12,7 +12,6 @@ declare {}* %llvm.dbg.func.start(%lldb.global*) declare {}* %llvm.dbg.region.start({}*) declare {}* %llvm.dbg.region.end({}*) -declare {}* %llvm.dbg.declare({}*, ...) ;; Global object anchors %llvm.dbg.translation_units = linkonce global {} {} @@ -90,16 +89,14 @@ %t = alloca int %.1 = call {}* %llvm.dbg.func.start(%lldb.global* %d.foo) %.2 = call {}* %llvm.dbg.stoppoint({}* %.1, uint 5, uint 2, %lldb.compile_unit* %d.compile_unit) - - %.3 = call {}*({}*, ...)* %llvm.dbg.declare({}* %.2, %lldb.local* %d.t, int* %t) %tmp.0 = load int* %q store int %tmp.0, int* %t - %.4 = call {}* %llvm.dbg.stoppoint({}* %.3, uint 6, uint 2, %lldb.compile_unit* %d.compile_unit) + %.3 = call {}* %llvm.dbg.stoppoint({}* %.2, uint 6, uint 2, %lldb.compile_unit* %d.compile_unit) %tmp.01 = load int* %t %tmp.1 = add int %tmp.01, 1 store int %tmp.1, int* %q - %.5 = call {}* %llvm.dbg.stoppoint({}* %.4, uint 7, uint 1, %lldb.compile_unit* %d.compile_unit) - call {}* %llvm.dbg.region.end({}* %.5) + %.4 = call {}* %llvm.dbg.stoppoint({}* %.3, uint 7, uint 1, %lldb.compile_unit* %d.compile_unit) + call {}* %llvm.dbg.region.end({}* %.4) ret void } From jlaskey at apple.com Mon Mar 13 20:00:47 2006 From: jlaskey at apple.com (Jim Laskey) Date: Mon, 13 Mar 2006 20:00:47 -0600 Subject: [llvm-commits] CVS: llvm/lib/VMCore/AutoUpgrade.cpp Message-ID: <200603140200.UAA01246@zion.cs.uiuc.edu> Changes in directory llvm/lib/VMCore: AutoUpgrade.cpp updated: 1.12 -> 1.13 --- Log message: 1. Handle removal of all arguments for a morphed intrinsic. 2. Remove the declaration of llvm.dbg.declare. --- Diffs of the changes: (+4 -1) AutoUpgrade.cpp | 5 ++++- 1 files changed, 4 insertions(+), 1 deletion(-) Index: llvm/lib/VMCore/AutoUpgrade.cpp diff -u llvm/lib/VMCore/AutoUpgrade.cpp:1.12 llvm/lib/VMCore/AutoUpgrade.cpp:1.13 --- llvm/lib/VMCore/AutoUpgrade.cpp:1.12 Mon Mar 13 07:07:37 2006 +++ llvm/lib/VMCore/AutoUpgrade.cpp Mon Mar 13 20:00:35 2006 @@ -97,6 +97,9 @@ if (F->getReturnType() != Type::VoidTy) { return M->getOrInsertFunction(Name, Type::VoidTy, NULL); } + } else if (Name == "llvm.dbg.declare") { + F->setName(""); + return NULL; } break; case 'i': @@ -230,7 +233,7 @@ } else Oprnds.push_back(UndefValue::get(NewFnTy->getParamType(i))); } - } else { + } else if (N) { assert(N == (CI->getNumOperands() - 1) && "Upgraded function needs permutation"); for (unsigned i = 0; i != N; ++i) { From reid at x10sys.com Mon Mar 13 23:39:51 2006 From: reid at x10sys.com (Reid Spencer) Date: Mon, 13 Mar 2006 23:39:51 -0600 Subject: [llvm-commits] CVS: llvm/docs/AliasAnalysis.html Bugpoint.html BytecodeFormat.html CFEBuildInstrs.html CodeGenerator.html CodingStandards.html CommandLine.html CompilerDriver.html CompilerWriterInfo.html ExtendingLLVM.html FAQ.html GarbageCollection.html GettingStarted.html GettingStartedVS.html HowToSubmitABug.html LLVMVsTheWorld.html LangRef.html Lexicon.html MakefileGuide.html ProgrammersManual.html Projects.html SourceLevelDebugging.html Stacker.html SystemLibrary.html TableGenFundamentals.html TestingGuide.html UsingLibraries.html WritingAnLLVMBackend.html WritingAnLLVMPass.html index.html Message-ID: <200603140539.XAA02536@zion.cs.uiuc.edu> Changes in directory llvm/docs: AliasAnalysis.html updated: 1.26 -> 1.27 Bugpoint.html updated: 1.5 -> 1.6 BytecodeFormat.html updated: 1.50 -> 1.51 CFEBuildInstrs.html updated: 1.55 -> 1.56 CodeGenerator.html updated: 1.28 -> 1.29 CodingStandards.html updated: 1.26 -> 1.27 CommandLine.html updated: 1.39 -> 1.40 CompilerDriver.html updated: 1.11 -> 1.12 CompilerWriterInfo.html updated: 1.8 -> 1.9 ExtendingLLVM.html updated: 1.25 -> 1.26 FAQ.html updated: 1.30 -> 1.31 GarbageCollection.html updated: 1.7 -> 1.8 GettingStarted.html updated: 1.125 -> 1.126 GettingStartedVS.html updated: 1.5 -> 1.6 HowToSubmitABug.html updated: 1.25 -> 1.26 LLVMVsTheWorld.html updated: 1.8 -> 1.9 LangRef.html updated: 1.138 -> 1.139 Lexicon.html updated: 1.13 -> 1.14 MakefileGuide.html updated: 1.27 -> 1.28 ProgrammersManual.html updated: 1.89 -> 1.90 Projects.html updated: 1.19 -> 1.20 SourceLevelDebugging.html updated: 1.11 -> 1.12 Stacker.html updated: 1.19 -> 1.20 SystemLibrary.html updated: 1.9 -> 1.10 TableGenFundamentals.html updated: 1.14 -> 1.15 TestingGuide.html updated: 1.27 -> 1.28 UsingLibraries.html updated: 1.18 -> 1.19 WritingAnLLVMBackend.html updated: 1.9 -> 1.10 WritingAnLLVMPass.html updated: 1.43 -> 1.44 index.html updated: 1.50 -> 1.51 --- Log message: Changes docs for llvm.cs.uiuc.edu -> llvm.org --- Diffs of the changes: (+124 -124) AliasAnalysis.html | 8 ++--- Bugpoint.html | 4 +- BytecodeFormat.html | 8 ++--- CFEBuildInstrs.html | 7 ++-- CodeGenerator.html | 4 +- CodingStandards.html | 4 +- CommandLine.html | 4 +- CompilerDriver.html | 4 +- CompilerWriterInfo.html | 4 +- ExtendingLLVM.html | 4 +- FAQ.html | 8 ++--- GarbageCollection.html | 4 +- GettingStarted.html | 14 ++++----- GettingStartedVS.html | 10 +++--- HowToSubmitABug.html | 6 +-- LLVMVsTheWorld.html | 6 +-- LangRef.html | 4 +- Lexicon.html | 6 +-- MakefileGuide.html | 4 +- ProgrammersManual.html | 6 +-- Projects.html | 4 +- SourceLevelDebugging.html | 4 +- Stacker.html | 4 +- SystemLibrary.html | 6 +-- TableGenFundamentals.html | 4 +- TestingGuide.html | 10 +++--- UsingLibraries.html | 4 +- WritingAnLLVMBackend.html | 4 +- WritingAnLLVMPass.html | 70 +++++++++++++++++++++++----------------------- index.html | 18 +++++------ 30 files changed, 124 insertions(+), 123 deletions(-) Index: llvm/docs/AliasAnalysis.html diff -u llvm/docs/AliasAnalysis.html:1.26 llvm/docs/AliasAnalysis.html:1.27 --- llvm/docs/AliasAnalysis.html:1.26 Tue Jan 3 00:04:48 2006 +++ llvm/docs/AliasAnalysis.html Mon Mar 13 23:39:39 2006 @@ -75,7 +75,7 @@ same object, or are known to never point to the same object.

The LLVM AliasAnalysis +href="http://llvm.org/doxygen/classllvm_1_1AliasAnalysis.html">AliasAnalysis class is the primary interface used by clients and implementations of alias analyses in the LLVM system. This class is the common interface between clients of alias analysis information and the implementations providing it, and is @@ -102,7 +102,7 @@

The AliasAnalysis +href="http://llvm.org/doxygen/classllvm_1_1AliasAnalysis.html">AliasAnalysis class defines the interface that the various alias analysis implementations should support. This class exports two important enums: AliasResult and ModRefResult which represent the result of an alias query or a @@ -951,8 +951,8 @@ src="http://www.w3.org/Icons/valid-html401" alt="Valid HTML 4.01!"> Chris Lattner
- LLVM Compiler Infrastructure
- Last modified: $Date: 2006/01/03 06:04:48 $ + LLVM Compiler Infrastructure
+ Last modified: $Date: 2006/03/14 05:39:39 $ Index: llvm/docs/Bugpoint.html diff -u llvm/docs/Bugpoint.html:1.5 llvm/docs/Bugpoint.html:1.6 --- llvm/docs/Bugpoint.html:1.5 Thu Dec 9 14:26:20 2004 +++ llvm/docs/Bugpoint.html Mon Mar 13 23:39:39 2006 @@ -230,8 +230,8 @@ src="http://www.w3.org/Icons/valid-html401" alt="Valid HTML 4.01!"> Chris Lattner
- LLVM Compiler Infrastructure
- Last modified: $Date: 2004/12/09 20:26:20 $ + LLVM Compiler Infrastructure
+ Last modified: $Date: 2006/03/14 05:39:39 $ Index: llvm/docs/BytecodeFormat.html diff -u llvm/docs/BytecodeFormat.html:1.50 llvm/docs/BytecodeFormat.html:1.51 --- llvm/docs/BytecodeFormat.html:1.50 Wed Jan 25 17:31:53 2006 +++ llvm/docs/BytecodeFormat.html Mon Mar 13 23:39:39 2006 @@ -747,7 +747,7 @@

Note that we plan to eventually expand the target description capabilities -of bytecode files to target +of bytecode files to target triples.

@@ -1553,7 +1553,7 @@

Instructions encode an opcode that identifies the kind of instruction. Opcodes are an enumerated integer value. The specific values used depend on the version of LLVM you're using. The opcode values are defined in the - + include/llvm/Instruction.def file. You should check there for the most recent definitions. The table below provides the opcodes defined as of the writing of this document. The table associates each opcode mnemonic with @@ -2147,8 +2147,8 @@ src="http://www.w3.org/Icons/valid-html401" alt="Valid HTML 4.01!"> Reid Spencer and Chris Lattner
-The LLVM Compiler Infrastructure
-Last modified: $Date: 2006/01/25 23:31:53 $ +The LLVM Compiler Infrastructure
+Last modified: $Date: 2006/03/14 05:39:39 $ Index: llvm/docs/CFEBuildInstrs.html diff -u llvm/docs/CFEBuildInstrs.html:1.55 llvm/docs/CFEBuildInstrs.html:1.56 --- llvm/docs/CFEBuildInstrs.html:1.55 Sun Feb 5 00:44:17 2006 +++ llvm/docs/CFEBuildInstrs.html Mon Mar 13 23:39:39 2006 @@ -184,7 +184,7 @@ shown below. Also, note that Solaris has trouble with various wide (multibyte) character functions from C as referenced from C++, so we typically configure with ---disable-c-mbchar (cf. Bug 206). +--disable-c-mbchar (cf. Bug 206). 

@@ -312,7 +312,7 @@
 
     University of Illinois at Urbana-Champaign
 
-    http://llvm.cs.uiuc.edu
+    http://llvm.org
 
 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
@@ -356,8 +356,8 @@
   src="http://www.w3.org/Icons/valid-html401" alt="Valid HTML 4.01!">
 
   Brian Gaeke

-  LLVM Compiler Infrastructure

-  Last modified: $Date: 2006/02/05 06:44:17 $
+  LLVM Compiler Infrastructure

+  Last modified: $Date: 2006/03/14 05:39:39 $
 
 
 


Index: llvm/docs/CodeGenerator.html
diff -u llvm/docs/CodeGenerator.html:1.28 llvm/docs/CodeGenerator.html:1.29
--- llvm/docs/CodeGenerator.html:1.28	Mon Oct 24 11:54:55 2005
+++ llvm/docs/CodeGenerator.html	Mon Mar 13 23:39:39 2006
@@ -1296,8 +1296,8 @@
   src="http://www.w3.org/Icons/valid-html401" alt="Valid HTML 4.01!" />
 
   Chris Lattner

-  The LLVM Compiler Infrastructure

-  Last modified: $Date: 2005/10/24 16:54:55 $
+  The LLVM Compiler Infrastructure

+  Last modified: $Date: 2006/03/14 05:39:39 $
 
 
 


Index: llvm/docs/CodingStandards.html
diff -u llvm/docs/CodingStandards.html:1.26 llvm/docs/CodingStandards.html:1.27
--- llvm/docs/CodingStandards.html:1.26	Sun Jan  1 15:59:22 2006
+++ llvm/docs/CodingStandards.html	Mon Mar 13 23:39:39 2006
@@ -653,8 +653,8 @@
   src="http://www.w3.org/Icons/valid-html401" alt="Valid HTML 4.01!">
 
   Chris Lattner

-  LLVM Compiler Infrastructure

-  Last modified: $Date: 2006/01/01 21:59:22 $
+  LLVM Compiler Infrastructure

+  Last modified: $Date: 2006/03/14 05:39:39 $
 
 
 


Index: llvm/docs/CommandLine.html
diff -u llvm/docs/CommandLine.html:1.39 llvm/docs/CommandLine.html:1.40
--- llvm/docs/CommandLine.html:1.39	Mon Nov 14 13:32:05 2005
+++ llvm/docs/CommandLine.html	Mon Mar 13 23:39:39 2006
@@ -1899,8 +1899,8 @@
   src="http://www.w3.org/Icons/valid-html401" alt="Valid HTML 4.01!">
 
   Chris Lattner

-  LLVM Compiler Infrastructure

-  Last modified: $Date: 2005/11/14 19:32:05 $
+  LLVM Compiler Infrastructure

+  Last modified: $Date: 2006/03/14 05:39:39 $
 
 
 


Index: llvm/docs/CompilerDriver.html
diff -u llvm/docs/CompilerDriver.html:1.11 llvm/docs/CompilerDriver.html:1.12
--- llvm/docs/CompilerDriver.html:1.11	Sun Nov 21 08:58:11 2004
+++ llvm/docs/CompilerDriver.html	Mon Mar 13 23:39:39 2006
@@ -814,8 +814,8 @@
  href="http://validator.w3.org/check/referer">Valid HTML 4.01!Reid Spencer

-The LLVM Compiler Infrastructure

-Last modified: $Date: 2004/11/21 14:58:11 $
+The LLVM Compiler Infrastructure

+Last modified: $Date: 2006/03/14 05:39:39 $
 
 


Index: llvm/docs/CompilerWriterInfo.html
diff -u llvm/docs/CompilerWriterInfo.html:1.8 llvm/docs/CompilerWriterInfo.html:1.9
--- llvm/docs/CompilerWriterInfo.html:1.8	Wed May 18 14:43:24 2005
+++ llvm/docs/CompilerWriterInfo.html	Mon Mar 13 23:39:39 2006
@@ -252,8 +252,8 @@
   src="http://www.w3.org/Icons/valid-html401" alt="Valid HTML 4.01!">
 
   Misha Brukman

-  LLVM Compiler Infrastructure

-  Last modified: $Date: 2005/05/18 19:43:24 $
+  LLVM Compiler Infrastructure

+  Last modified: $Date: 2006/03/14 05:39:39 $
 
 
 


Index: llvm/docs/ExtendingLLVM.html
diff -u llvm/docs/ExtendingLLVM.html:1.25 llvm/docs/ExtendingLLVM.html:1.26
--- llvm/docs/ExtendingLLVM.html:1.25	Thu Mar  9 16:38:42 2006
+++ llvm/docs/ExtendingLLVM.html	Mon Mar 13 23:39:39 2006
@@ -388,9 +388,9 @@
   Valid HTML 4.01!
 
-  The LLVM Compiler Infrastructure
+  The LLVM Compiler Infrastructure
   

-  Last modified: $Date: 2006/03/09 22:38:42 $
+  Last modified: $Date: 2006/03/14 05:39:39 $
 
 
 


Index: llvm/docs/FAQ.html
diff -u llvm/docs/FAQ.html:1.30 llvm/docs/FAQ.html:1.31
--- llvm/docs/FAQ.html:1.30	Mon Apr 25 15:36:56 2005
+++ llvm/docs/FAQ.html	Mon Mar 13 23:39:39 2006
@@ -89,7 +89,7 @@
 
 
 

-  
Written by The LLVM Team

+  
Written by The LLVM Team

 

 
 
@@ -129,7 +129,7 @@
 

 
Yes.  The modified source distribution must retain the copyright notice and
 follow the three bulletted conditions listed in the LLVM license.

+href="http://llvm.org/releases/1.3/LICENSE.TXT">LLVM license.

 

 
 

@@ -573,8 +573,8 @@
   Valid HTML 4.01!
 
-  LLVM Compiler Infrastructure

-  Last modified: $Date: 2005/04/25 20:36:56 $
+  LLVM Compiler Infrastructure

+  Last modified: $Date: 2006/03/14 05:39:39 $
 
 
 


Index: llvm/docs/GarbageCollection.html
diff -u llvm/docs/GarbageCollection.html:1.7 llvm/docs/GarbageCollection.html:1.8
--- llvm/docs/GarbageCollection.html:1.7	Thu Jul 22 00:49:38 2004
+++ llvm/docs/GarbageCollection.html	Mon Mar 13 23:39:39 2006
@@ -525,8 +525,8 @@
   src="http://www.w3.org/Icons/valid-html401" alt="Valid HTML 4.01!">
 
   Chris Lattner

-  LLVM Compiler Infrastructure

-  Last modified: $Date: 2004/07/22 05:49:38 $
+  LLVM Compiler Infrastructure

+  Last modified: $Date: 2006/03/14 05:39:39 $
 
 
 


Index: llvm/docs/GettingStarted.html
diff -u llvm/docs/GettingStarted.html:1.125 llvm/docs/GettingStarted.html:1.126
--- llvm/docs/GettingStarted.html:1.125	Wed Jan  4 00:51:22 2006
+++ llvm/docs/GettingStarted.html	Mon Mar 13 23:39:39 2006
@@ -1080,7 +1080,7 @@
 
 
One useful source of information about the LLVM source base is the LLVM doxygen documentation available at http://llvm.cs.uiuc.edu/doxygen/.
+href="http://llvm.org/doxygen/">http://llvm.org/doxygen/.
 The following is a brief introduction to code layout:

 
 

@@ -1407,7 +1407,7 @@
   NightlyTestTemplate.html 
These files are used in a
   cron script to generate nightly status reports of the functionality of
   tools, and the results can be seen by following the appropriate link on
-  the LLVM homepage.

+  the LLVM homepage.

 
   
TableGen/ 
The TableGen directory contains
   the tool used to generate register descriptions, instruction set
@@ -1526,9 +1526,9 @@
 out:

 
 
 
@@ -1545,8 +1545,8 @@
 
   Chris Lattner

   Reid Spencer

-  The LLVM Compiler Infrastructure

-  Last modified: $Date: 2006/01/04 06:51:22 $
+  The LLVM Compiler Infrastructure

+  Last modified: $Date: 2006/03/14 05:39:39 $
 
 
 


Index: llvm/docs/GettingStartedVS.html
diff -u llvm/docs/GettingStartedVS.html:1.5 llvm/docs/GettingStartedVS.html:1.6
--- llvm/docs/GettingStartedVS.html:1.5	Sun Oct 30 15:00:24 2005
+++ llvm/docs/GettingStartedVS.html	Mon Mar 13 23:39:39 2006
@@ -328,9 +328,9 @@
 out:

 
 
 
@@ -346,8 +346,8 @@
   src="http://www.w3.org/Icons/valid-html401" alt="Valid HTML 4.01!" />
 
   Jeff Cohen

-  The LLVM Compiler Infrastructure

-  Last modified: $Date: 2005/10/30 21:00:24 $
+  The LLVM Compiler Infrastructure

+  Last modified: $Date: 2006/03/14 05:39:39 $
 
 
 


Index: llvm/docs/HowToSubmitABug.html
diff -u llvm/docs/HowToSubmitABug.html:1.25 llvm/docs/HowToSubmitABug.html:1.26
--- llvm/docs/HowToSubmitABug.html:1.25	Wed Feb  8 11:01:37 2006
+++ llvm/docs/HowToSubmitABug.html	Mon Mar 13 23:39:39 2006
@@ -57,7 +57,7 @@
 more easily.

 
 
Once you have a reduced test-case, go to the LLVM Bug Tracking
+href="http://llvm.org/bugs/enter_bug.cgi">the LLVM Bug Tracking
 System, select the category in which the bug falls, and fill out the form
 with the necessary details.  The bug description should contain the following
 information:

@@ -350,9 +350,9 @@
   src="http://www.w3.org/Icons/valid-html401" alt="Valid HTML 4.01!" />
 
   Chris Lattner

-  The LLVM Compiler Infrastructure
+  The LLVM Compiler Infrastructure
   

-  Last modified: $Date: 2006/02/08 17:01:37 $
+  Last modified: $Date: 2006/03/14 05:39:39 $
 
 
 


Index: llvm/docs/LLVMVsTheWorld.html
diff -u llvm/docs/LLVMVsTheWorld.html:1.8 llvm/docs/LLVMVsTheWorld.html:1.9
--- llvm/docs/LLVMVsTheWorld.html:1.8	Sun May 23 16:07:26 2004
+++ llvm/docs/LLVMVsTheWorld.html	Mon Mar 13 23:39:39 2006
@@ -61,7 +61,7 @@
 strong SSA-based optimization at compile-time, link-time, run-time, and
 off-line, and multiple platform backends with Just-in-Time and ahead-of-time
 compilation frameworks. (See our document on Lifelong
+href="http://llvm.org/pubs/2004-01-30-CGO-LLVM.html">Lifelong
 Code Optimization for more.)

 
 
GCC: Many relatively mature platform backends support assembly-language code
@@ -171,9 +171,9 @@
 

 

   
Brian R. Gaeke

-  The LLVM Compiler Infrastructure
+  The LLVM Compiler Infrastructure
   

-  Last modified: $Date: 2004/05/23 21:07:26 $
+  Last modified: $Date: 2006/03/14 05:39:39 $
 

 
 


Index: llvm/docs/LangRef.html
diff -u llvm/docs/LangRef.html:1.138 llvm/docs/LangRef.html:1.139
--- llvm/docs/LangRef.html:1.138	Fri Mar  3 18:02:10 2006
+++ llvm/docs/LangRef.html	Mon Mar 13 23:39:39 2006
@@ -3693,8 +3693,8 @@
   src="http://www.w3.org/Icons/valid-html401" alt="Valid HTML 4.01!" />
 
   Chris Lattner

-  The LLVM Compiler Infrastructure

-  Last modified: $Date: 2006/03/04 00:02:10 $
+  The LLVM Compiler Infrastructure

+  Last modified: $Date: 2006/03/14 05:39:39 $
 
 
 


Index: llvm/docs/Lexicon.html
diff -u llvm/docs/Lexicon.html:1.13 llvm/docs/Lexicon.html:1.14
--- llvm/docs/Lexicon.html:1.13	Wed Feb  8 10:59:49 2006
+++ llvm/docs/Lexicon.html	Mon Mar 13 23:39:39 2006
@@ -168,9 +168,9 @@
  src="http://jigsaw.w3.org/css-validator/images/vcss" alt="Valid CSS!">Valid HTML 4.01!The LLVM Team

-The LLVM Compiler Infrastructure

-Last modified: $Date: 2006/02/08 16:59:49 $
+ href="http://llvm.org/">The LLVM Team

+The LLVM Compiler Infrastructure

+Last modified: $Date: 2006/03/14 05:39:39 $
 
 


Index: llvm/docs/MakefileGuide.html
diff -u llvm/docs/MakefileGuide.html:1.27 llvm/docs/MakefileGuide.html:1.28
--- llvm/docs/MakefileGuide.html:1.27	Fri Jan 27 16:06:01 2006
+++ llvm/docs/MakefileGuide.html	Mon Mar 13 23:39:39 2006
@@ -990,8 +990,8 @@
   src="http://www.w3.org/Icons/valid-html401" alt="Valid HTML 4.01!" />
 
   Reid Spencer

-  The LLVM Compiler Infrastructure

-  Last modified: $Date: 2006/01/27 22:06:01 $
+  The LLVM Compiler Infrastructure

+  Last modified: $Date: 2006/03/14 05:39:39 $
 
 
 


Index: llvm/docs/ProgrammersManual.html
diff -u llvm/docs/ProgrammersManual.html:1.89 llvm/docs/ProgrammersManual.html:1.90
--- llvm/docs/ProgrammersManual.html:1.89	Sun Nov 27 20:30:22 2005
+++ llvm/docs/ProgrammersManual.html	Mon Mar 13 23:39:39 2006
@@ -739,7 +739,7 @@
 most-specific common base class is Instruction, which includes lots of
 less closely-related things. For these cases, LLVM provides a handy wrapper
 class called CallSite.
+href="http://llvm.org/doxygen/classllvm_1_1CallSite.html">CallSite.
 It is essentially a wrapper around an Instruction pointer, with some
 methods that provide functionality common to CallInsts and
 InvokeInsts.

@@ -2276,8 +2276,8 @@
 
   Dinakar Dhurjati and
   Chris Lattner

-  The LLVM Compiler Infrastructure

-  Last modified: $Date: 2005/11/28 02:30:22 $
+  The LLVM Compiler Infrastructure

+  Last modified: $Date: 2006/03/14 05:39:39 $
 
 
 


Index: llvm/docs/Projects.html
diff -u llvm/docs/Projects.html:1.19 llvm/docs/Projects.html:1.20
--- llvm/docs/Projects.html:1.19	Mon Oct 24 11:43:08 2005
+++ llvm/docs/Projects.html	Mon Mar 13 23:39:39 2006
@@ -451,9 +451,9 @@
   src="http://www.w3.org/Icons/valid-html401" alt="Valid HTML 4.01!" />
 
   John Criswell

-  The LLVM Compiler Infrastructure
+  The LLVM Compiler Infrastructure
   

-  Last modified: $Date: 2005/10/24 16:43:08 $
+  Last modified: $Date: 2006/03/14 05:39:39 $
 
 
 


Index: llvm/docs/SourceLevelDebugging.html
diff -u llvm/docs/SourceLevelDebugging.html:1.11 llvm/docs/SourceLevelDebugging.html:1.12
--- llvm/docs/SourceLevelDebugging.html:1.11	Thu Dec  9 14:27:37 2004
+++ llvm/docs/SourceLevelDebugging.html	Mon Mar 13 23:39:39 2006
@@ -1109,8 +1109,8 @@
   src="http://www.w3.org/Icons/valid-html401" alt="Valid HTML 4.01!">
 
   Chris Lattner

-  LLVM Compiler Infrastructure

-  Last modified: $Date: 2004/12/09 20:27:37 $
+  LLVM Compiler Infrastructure

+  Last modified: $Date: 2006/03/14 05:39:39 $
 
 
 


Index: llvm/docs/Stacker.html
diff -u llvm/docs/Stacker.html:1.19 llvm/docs/Stacker.html:1.20
--- llvm/docs/Stacker.html:1.19	Wed May  4 10:43:40 2005
+++ llvm/docs/Stacker.html	Mon Mar 13 23:39:39 2006
@@ -1404,8 +1404,8 @@
   src="http://www.w3.org/Icons/valid-html401" alt="Valid HTML 4.01!">
 
   Reid Spencer

-  LLVM Compiler Infrastructure

-  Last modified: $Date: 2005/05/04 15:43:40 $
+  LLVM Compiler Infrastructure

+  Last modified: $Date: 2006/03/14 05:39:39 $
 
 
 


Index: llvm/docs/SystemLibrary.html
diff -u llvm/docs/SystemLibrary.html:1.9 llvm/docs/SystemLibrary.html:1.10
--- llvm/docs/SystemLibrary.html:1.9	Wed Jan  5 12:21:39 2005
+++ llvm/docs/SystemLibrary.html	Mon Mar 13 23:39:39 2006
@@ -323,7 +323,7 @@
 
 
Bug 351

 

-  
See bug 351
+  
See bug 351
   for further details on the progress of this work

 

 
@@ -337,8 +337,8 @@
   src="http://www.w3.org/Icons/valid-html401" alt="Valid HTML 4.01!">
 
   Reid Spencer

-  LLVM Compiler Infrastructure

-  Last modified: $Date: 2005/01/05 18:21:39 $
+  LLVM Compiler Infrastructure

+  Last modified: $Date: 2006/03/14 05:39:39 $
 
 
 


Index: llvm/docs/TableGenFundamentals.html
diff -u llvm/docs/TableGenFundamentals.html:1.14 llvm/docs/TableGenFundamentals.html:1.15
--- llvm/docs/TableGenFundamentals.html:1.14	Mon Oct 24 11:54:55 2005
+++ llvm/docs/TableGenFundamentals.html	Mon Mar 13 23:39:39 2006
@@ -559,8 +559,8 @@
   src="http://www.w3.org/Icons/valid-html401" alt="Valid HTML 4.01!" />
 
   Chris Lattner

-  LLVM Compiler Infrastructure

-  Last modified: $Date: 2005/10/24 16:54:55 $
+  LLVM Compiler Infrastructure

+  Last modified: $Date: 2006/03/14 05:39:39 $
 
 
 


Index: llvm/docs/TestingGuide.html
diff -u llvm/docs/TestingGuide.html:1.27 llvm/docs/TestingGuide.html:1.28
--- llvm/docs/TestingGuide.html:1.27	Fri May 13 15:25:49 2005
+++ llvm/docs/TestingGuide.html	Mon Mar 13 23:39:39 2006
@@ -416,7 +416,7 @@
 
    
   
  1. cd into the llvm/projects directory
    2. 
   
  2. check out the llvm-test module with:
    
-  cvs -d :pserver:anon at llvm.cs.uiuc.edu:/var/cvs/llvm co -PR llvm-test
     
+  cvs -d :pserver:anon at llvm.org:/var/cvs/llvm co -PR llvm-test
     
   This will get the test suite into llvm/projects/llvm-test
    3. 
   
  3. configure the test suite. You can do this one of two ways:
   
      
@@ -468,7 +468,7 @@
 
      
 
 
      
-The LLVM Nightly Testers
+The LLVM Nightly Testers
 automatically check out an LLVM tree, build it, run the "nightly" 
 program test (described above), run  all of the feature and regression tests, 
 and then delete the checked out tree.  This tester is designed to ensure that 
@@ -492,7 +492,7 @@
 
       #!/bin/bash
 BASE=/proj/work/llvm/nightlytest
-export CVSROOT=:pserver:anon at llvm.cs.uiuc.edu:/var/cvs/llvm
+export CVSROOT=:pserver:anon at llvm.org:/var/cvs/llvm
 export BUILDDIR=$BASE/build 
 export WEBDIR=$BASE/testresults 
 export LLVMGCCDIR=/proj/work/llvm/cfrontend/install
@@ -521,8 +521,8 @@
   src="http://www.w3.org/Icons/valid-html401" alt="Valid HTML 4.01!" />
 
   John T. Criswell, Reid Spencer, and Tanya Lattner
      
-  The LLVM Compiler Infrastructure
      
-  Last modified: $Date: 2005/05/13 20:25:49 $
+  The LLVM Compiler Infrastructure
      
+  Last modified: $Date: 2006/03/14 05:39:39 $
 
 
 


Index: llvm/docs/UsingLibraries.html
diff -u llvm/docs/UsingLibraries.html:1.18 llvm/docs/UsingLibraries.html:1.19
--- llvm/docs/UsingLibraries.html:1.18	Sun Feb  5 00:40:12 2006
+++ llvm/docs/UsingLibraries.html	Mon Mar 13 23:39:39 2006
@@ -496,8 +496,8 @@
     src="http://www.w3.org/Icons/valid-html401" alt="Valid HTML 4.01!" />
   Reid Spencer
 
-The LLVM Compiler Infrastructure 
-
      Last modified: $Date: 2006/02/05 06:40:12 $ 
      
+The LLVM Compiler Infrastructure 
+
      Last modified: $Date: 2006/03/14 05:39:39 $ 
 
 
 
@@ -36,7 +36,7 @@
 
 
 
@@ -249,7 +249,7 @@
   Valid HTML 4.01!
 
-  LLVM Compiler Infrastructure
      
-  Last modified: $Date: 2006/02/23 16:18:29 $
+  LLVM Compiler Infrastructure
      
+  Last modified: $Date: 2006/03/14 05:39:39 $
 
 





From reid at x10sys.com  Mon Mar 13 23:42:19 2006
From: reid at x10sys.com (Reid Spencer)
Date: Mon, 13 Mar 2006 23:42:19 -0600
Subject: [llvm-commits] CVS: llvm/docs/CommandGuide/analyze.pod bugpoint.pod
	gccas.pod gccld.pod index.html llc.pod lli.pod llvm-ar.pod
	llvm-as.pod llvm-bcanalyzer.pod llvm-db.pod llvm-dis.pod
	llvm-extract.pod llvm-ld.pod llvm-link.pod llvm-nm.pod
	llvm-prof.pod llvm-ranlib.pod llvmc.pod llvmgcc.pod
	llvmgxx.pod opt.pod stkrc.pod 
Message-ID: <200603140542.XAA02851@zion.cs.uiuc.edu>



Changes in directory llvm/docs/CommandGuide:

analyze.pod updated: 1.2 -> 1.3
bugpoint.pod updated: 1.5 -> 1.6
gccas.pod updated: 1.4 -> 1.5
gccld.pod updated: 1.4 -> 1.5
index.html updated: 1.24 -> 1.25
llc.pod updated: 1.11 -> 1.12
lli.pod updated: 1.4 -> 1.5
llvm-ar.pod updated: 1.9 -> 1.10
llvm-as.pod updated: 1.4 -> 1.5
llvm-bcanalyzer.pod updated: 1.6 -> 1.7
llvm-db.pod updated: 1.3 -> 1.4
llvm-dis.pod updated: 1.3 -> 1.4
llvm-extract.pod updated: 1.4 -> 1.5
llvm-ld.pod updated: 1.3 -> 1.4
llvm-link.pod updated: 1.4 -> 1.5
llvm-nm.pod updated: 1.2 -> 1.3
llvm-prof.pod updated: 1.4 -> 1.5
llvm-ranlib.pod updated: 1.4 -> 1.5
llvmc.pod updated: 1.10 -> 1.11
llvmgcc.pod updated: 1.6 -> 1.7
llvmgxx.pod updated: 1.6 -> 1.7
opt.pod updated: 1.2 -> 1.3
stkrc.pod updated: 1.2 -> 1.3
---
Log message:

Change docs for llvm.cs.uiuc.edu -> llvm.org


---
Diffs of the changes:  (+28 -28)

 analyze.pod         |    2 +-
 bugpoint.pod        |    2 +-
 gccas.pod           |    2 +-
 gccld.pod           |    2 +-
 index.html          |    4 ++--
 llc.pod             |    2 +-
 lli.pod             |    2 +-
 llvm-ar.pod         |    2 +-
 llvm-as.pod         |    2 +-
 llvm-bcanalyzer.pod |    4 ++--
 llvm-db.pod         |    4 ++--
 llvm-dis.pod        |    2 +-
 llvm-extract.pod    |    2 +-
 llvm-ld.pod         |    2 +-
 llvm-link.pod       |    2 +-
 llvm-nm.pod         |    2 +-
 llvm-prof.pod       |    2 +-
 llvm-ranlib.pod     |    2 +-
 llvmc.pod           |    2 +-
 llvmgcc.pod         |    2 +-
 llvmgxx.pod         |    2 +-
 opt.pod             |    2 +-
 stkrc.pod           |    6 +++---
 23 files changed, 28 insertions(+), 28 deletions(-)


Index: llvm/docs/CommandGuide/analyze.pod
diff -u llvm/docs/CommandGuide/analyze.pod:1.2 llvm/docs/CommandGuide/analyze.pod:1.3
--- llvm/docs/CommandGuide/analyze.pod:1.2	Fri Jul  2 11:06:19 2004
+++ llvm/docs/CommandGuide/analyze.pod	Mon Mar 13 23:42:07 2006
@@ -70,6 +70,6 @@
 
 =head1 AUTHORS
 
-Maintained by the LLVM Team (L).
+Maintained by the LLVM Team (L).
 
 =cut


Index: llvm/docs/CommandGuide/bugpoint.pod
diff -u llvm/docs/CommandGuide/bugpoint.pod:1.5 llvm/docs/CommandGuide/bugpoint.pod:1.6
--- llvm/docs/CommandGuide/bugpoint.pod:1.5	Thu Dec  9 14:28:42 2004
+++ llvm/docs/CommandGuide/bugpoint.pod	Mon Mar 13 23:42:07 2006
@@ -113,6 +113,6 @@
 
 =head1 AUTHOR
 
-Maintained by the LLVM Team (L).
+Maintained by the LLVM Team (L).
 
 =cut


Index: llvm/docs/CommandGuide/gccas.pod
diff -u llvm/docs/CommandGuide/gccas.pod:1.4 llvm/docs/CommandGuide/gccas.pod:1.5
--- llvm/docs/CommandGuide/gccas.pod:1.4	Fri Jul  2 11:06:19 2004
+++ llvm/docs/CommandGuide/gccas.pod	Mon Mar 13 23:42:07 2006
@@ -71,6 +71,6 @@
 
 =head1 AUTHORS
 
-Maintained by the LLVM Team (L).
+Maintained by the LLVM Team (L).
 
 =cut


Index: llvm/docs/CommandGuide/gccld.pod
diff -u llvm/docs/CommandGuide/gccld.pod:1.4 llvm/docs/CommandGuide/gccld.pod:1.5
--- llvm/docs/CommandGuide/gccld.pod:1.4	Fri May 13 15:14:06 2005
+++ llvm/docs/CommandGuide/gccld.pod	Mon Mar 13 23:42:07 2006
@@ -170,6 +170,6 @@
 
 =head1 AUTHORS
 
-Maintained by the LLVM Team (L).
+Maintained by the LLVM Team (L).
 
 =cut


Index: llvm/docs/CommandGuide/index.html
diff -u llvm/docs/CommandGuide/index.html:1.24 llvm/docs/CommandGuide/index.html:1.25
--- llvm/docs/CommandGuide/index.html:1.24	Sun Apr 24 12:46:58 2005
+++ llvm/docs/CommandGuide/index.html	Mon Mar 13 23:42:07 2006
@@ -139,8 +139,8 @@
   Valid HTML 4.01!
 
-  LLVM Compiler Infrastructure
      
-  Last modified: $Date: 2005/04/24 17:46:58 $
+  LLVM Compiler Infrastructure
      
+  Last modified: $Date: 2006/03/14 05:42:07 $
 
 
 


Index: llvm/docs/CommandGuide/llc.pod
diff -u llvm/docs/CommandGuide/llc.pod:1.11 llvm/docs/CommandGuide/llc.pod:1.12
--- llvm/docs/CommandGuide/llc.pod:1.11	Thu Dec 15 23:19:35 2005
+++ llvm/docs/CommandGuide/llc.pod	Mon Mar 13 23:42:07 2006
@@ -186,6 +186,6 @@
 
 =head1 AUTHORS
 
-Maintained by the LLVM Team (L).
+Maintained by the LLVM Team (L).
 
 =cut


Index: llvm/docs/CommandGuide/lli.pod
diff -u llvm/docs/CommandGuide/lli.pod:1.4 llvm/docs/CommandGuide/lli.pod:1.5
--- llvm/docs/CommandGuide/lli.pod:1.4	Thu Dec 15 23:19:35 2005
+++ llvm/docs/CommandGuide/lli.pod	Mon Mar 13 23:42:07 2006
@@ -92,6 +92,6 @@
 
 =head1 AUTHOR
 
-Maintained by the LLVM Team (L).
+Maintained by the LLVM Team (L).
 
 =cut


Index: llvm/docs/CommandGuide/llvm-ar.pod
diff -u llvm/docs/CommandGuide/llvm-ar.pod:1.9 llvm/docs/CommandGuide/llvm-ar.pod:1.10
--- llvm/docs/CommandGuide/llvm-ar.pod:1.9	Fri Dec 10 09:48:15 2004
+++ llvm/docs/CommandGuide/llvm-ar.pod	Mon Mar 13 23:42:07 2006
@@ -401,6 +401,6 @@
 
 =head1 AUTHORS
 
-Maintained by the LLVM Team (L).
+Maintained by the LLVM Team (L).
 
 =cut


Index: llvm/docs/CommandGuide/llvm-as.pod
diff -u llvm/docs/CommandGuide/llvm-as.pod:1.4 llvm/docs/CommandGuide/llvm-as.pod:1.5
--- llvm/docs/CommandGuide/llvm-as.pod:1.4	Fri May 13 15:04:33 2005
+++ llvm/docs/CommandGuide/llvm-as.pod	Mon Mar 13 23:42:07 2006
@@ -72,6 +72,6 @@
 
 =head1 AUTHORS
 
-Maintained by the LLVM Team (L).
+Maintained by the LLVM Team (L).
 
 =cut


Index: llvm/docs/CommandGuide/llvm-bcanalyzer.pod
diff -u llvm/docs/CommandGuide/llvm-bcanalyzer.pod:1.6 llvm/docs/CommandGuide/llvm-bcanalyzer.pod:1.7
--- llvm/docs/CommandGuide/llvm-bcanalyzer.pod:1.6	Sat Dec 11 01:16:54 2004
+++ llvm/docs/CommandGuide/llvm-bcanalyzer.pod	Mon Mar 13 23:42:07 2006
@@ -306,10 +306,10 @@
 
 =head1 SEE ALSO
 
-L, L
+L, L
 
 =head1 AUTHORS
 
-Maintained by the LLVM Team (L).
+Maintained by the LLVM Team (L).
 
 =cut


Index: llvm/docs/CommandGuide/llvm-db.pod
diff -u llvm/docs/CommandGuide/llvm-db.pod:1.3 llvm/docs/CommandGuide/llvm-db.pod:1.4
--- llvm/docs/CommandGuide/llvm-db.pod:1.3	Fri Jul  2 11:06:19 2004
+++ llvm/docs/CommandGuide/llvm-db.pod	Mon Mar 13 23:42:07 2006
@@ -7,10 +7,10 @@
 =head1 SYNOPSIS
 
 Details coming soon. Please see 
-L in the meantime.
+L in the meantime.
 
 =head1 AUTHORS
 
-Maintained by the LLVM Team (L).
+Maintained by the LLVM Team (L).
 
 =cut


Index: llvm/docs/CommandGuide/llvm-dis.pod
diff -u llvm/docs/CommandGuide/llvm-dis.pod:1.3 llvm/docs/CommandGuide/llvm-dis.pod:1.4
--- llvm/docs/CommandGuide/llvm-dis.pod:1.3	Fri May 13 15:04:33 2005
+++ llvm/docs/CommandGuide/llvm-dis.pod	Mon Mar 13 23:42:07 2006
@@ -55,6 +55,6 @@
 
 =head1 AUTHORS
 
-Maintained by the LLVM Team (L).
+Maintained by the LLVM Team (L).
 
 =cut


Index: llvm/docs/CommandGuide/llvm-extract.pod
diff -u llvm/docs/CommandGuide/llvm-extract.pod:1.4 llvm/docs/CommandGuide/llvm-extract.pod:1.5
--- llvm/docs/CommandGuide/llvm-extract.pod:1.4	Fri May 13 15:03:17 2005
+++ llvm/docs/CommandGuide/llvm-extract.pod	Mon Mar 13 23:42:07 2006
@@ -58,6 +58,6 @@
 
 =head1 AUTHORS
 
-Maintained by the LLVM Team (L).
+Maintained by the LLVM Team (L).
 
 =cut


Index: llvm/docs/CommandGuide/llvm-ld.pod
diff -u llvm/docs/CommandGuide/llvm-ld.pod:1.3 llvm/docs/CommandGuide/llvm-ld.pod:1.4
--- llvm/docs/CommandGuide/llvm-ld.pod:1.3	Tue Dec 20 23:13:06 2005
+++ llvm/docs/CommandGuide/llvm-ld.pod	Mon Mar 13 23:42:07 2006
@@ -181,6 +181,6 @@
 
 =head1 AUTHORS
 
-Maintained by the LLVM Team (L).
+Maintained by the LLVM Team (L).
 
 =cut


Index: llvm/docs/CommandGuide/llvm-link.pod
diff -u llvm/docs/CommandGuide/llvm-link.pod:1.4 llvm/docs/CommandGuide/llvm-link.pod:1.5
--- llvm/docs/CommandGuide/llvm-link.pod:1.4	Mon Nov 15 14:36:39 2004
+++ llvm/docs/CommandGuide/llvm-link.pod	Mon Mar 13 23:42:07 2006
@@ -69,6 +69,6 @@
 
 =head1 AUTHORS
 
-Maintained by the LLVM Team (L).
+Maintained by the LLVM Team (L).
 
 =cut


Index: llvm/docs/CommandGuide/llvm-nm.pod
diff -u llvm/docs/CommandGuide/llvm-nm.pod:1.2 llvm/docs/CommandGuide/llvm-nm.pod:1.3
--- llvm/docs/CommandGuide/llvm-nm.pod:1.2	Fri Jul  2 11:06:19 2004
+++ llvm/docs/CommandGuide/llvm-nm.pod	Mon Mar 13 23:42:07 2006
@@ -117,6 +117,6 @@
 
 =head1 AUTHOR
 
-Maintained by the LLVM Team (L).
+Maintained by the LLVM Team (L).
 
 =cut


Index: llvm/docs/CommandGuide/llvm-prof.pod
diff -u llvm/docs/CommandGuide/llvm-prof.pod:1.4 llvm/docs/CommandGuide/llvm-prof.pod:1.5
--- llvm/docs/CommandGuide/llvm-prof.pod:1.4	Mon Nov 15 14:30:19 2004
+++ llvm/docs/CommandGuide/llvm-prof.pod	Mon Mar 13 23:42:07 2006
@@ -52,6 +52,6 @@
 
 =head1 AUTHOR
 
-B is maintained by the LLVM Team (L).
+B is maintained by the LLVM Team (L).
 
 =cut


Index: llvm/docs/CommandGuide/llvm-ranlib.pod
diff -u llvm/docs/CommandGuide/llvm-ranlib.pod:1.4 llvm/docs/CommandGuide/llvm-ranlib.pod:1.5
--- llvm/docs/CommandGuide/llvm-ranlib.pod:1.4	Fri May 13 15:08:34 2005
+++ llvm/docs/CommandGuide/llvm-ranlib.pod	Mon Mar 13 23:42:07 2006
@@ -47,6 +47,6 @@
 
 =head1 AUTHORS
 
-Maintained by the LLVM Team (L).
+Maintained by the LLVM Team (L).
 
 =cut


Index: llvm/docs/CommandGuide/llvmc.pod
diff -u llvm/docs/CommandGuide/llvmc.pod:1.10 llvm/docs/CommandGuide/llvmc.pod:1.11
--- llvm/docs/CommandGuide/llvmc.pod:1.10	Wed Jul 20 16:06:37 2005
+++ llvm/docs/CommandGuide/llvmc.pod	Mon Mar 13 23:42:07 2006
@@ -400,6 +400,6 @@
 
 =head1 AUTHORS
 
-Maintained by the LLVM Team (L).
+Maintained by the LLVM Team (L).
 
 =cut


Index: llvm/docs/CommandGuide/llvmgcc.pod
diff -u llvm/docs/CommandGuide/llvmgcc.pod:1.6 llvm/docs/CommandGuide/llvmgcc.pod:1.7
--- llvm/docs/CommandGuide/llvmgcc.pod:1.6	Fri May 13 15:10:13 2005
+++ llvm/docs/CommandGuide/llvmgcc.pod	Mon Mar 13 23:42:07 2006
@@ -89,7 +89,7 @@
 
 =head1 AUTHORS
 
-Maintained by the LLVM Team (L).
+Maintained by the LLVM Team (L).
 
 =cut
 


Index: llvm/docs/CommandGuide/llvmgxx.pod
diff -u llvm/docs/CommandGuide/llvmgxx.pod:1.6 llvm/docs/CommandGuide/llvmgxx.pod:1.7
--- llvm/docs/CommandGuide/llvmgxx.pod:1.6	Fri May 13 15:10:13 2005
+++ llvm/docs/CommandGuide/llvmgxx.pod	Mon Mar 13 23:42:07 2006
@@ -89,7 +89,7 @@
 
 =head1 AUTHORS
 
-Maintained by the LLVM Team (L).
+Maintained by the LLVM Team (L).
 
 =cut
 


Index: llvm/docs/CommandGuide/opt.pod
diff -u llvm/docs/CommandGuide/opt.pod:1.2 llvm/docs/CommandGuide/opt.pod:1.3
--- llvm/docs/CommandGuide/opt.pod:1.2	Fri Jul  2 11:06:19 2004
+++ llvm/docs/CommandGuide/opt.pod	Mon Mar 13 23:42:07 2006
@@ -92,6 +92,6 @@
 
 =head1 AUTHORS
 
-Maintained by the LLVM Team (L).
+Maintained by the LLVM Team (L).
 
 =cut


Index: llvm/docs/CommandGuide/stkrc.pod
diff -u llvm/docs/CommandGuide/stkrc.pod:1.2 llvm/docs/CommandGuide/stkrc.pod:1.3
--- llvm/docs/CommandGuide/stkrc.pod:1.2	Sat Jul 10 18:41:08 2004
+++ llvm/docs/CommandGuide/stkrc.pod	Mon Mar 13 23:42:07 2006
@@ -13,7 +13,7 @@
 The B command is the compiler for the Stacker language. Stacker is a
 simple stack based, Forth-like language that was written as a demonstration
 language for LLVM. For details on the language, please see
-L . The B compiler is fairly 
+L . The B compiler is fairly 
 minimal. It compiles to bytecode only and doesn't perform any optimizations.
 The output of stkrc (a bytecode file) can be piped through other LLVM tools
 for optimization and linking.
@@ -87,10 +87,10 @@
 
 =head1 SEE ALSO
 
-L, L
+L, L
 
 =head1 AUTHORS
 
-Maintained by the LLVM Team (L).
+Maintained by the LLVM Team (L).
 
 =cut





From reid at x10sys.com  Mon Mar 13 23:55:07 2006
From: reid at x10sys.com (Reid Spencer)
Date: Mon, 13 Mar 2006 23:55:07 -0600
Subject: [llvm-commits] CVS: llvm/lib/System/README.txt 
Message-ID: <200603140555.XAA02945@zion.cs.uiuc.edu>



Changes in directory llvm/lib/System:

README.txt updated: 1.5 -> 1.6
---
Log message:

Convert llvm.cs.uiuc.edu -> llvm.org


---
Diffs of the changes:  (+1 -1)

 README.txt |    2 +-
 1 files changed, 1 insertion(+), 1 deletion(-)


Index: llvm/lib/System/README.txt
diff -u llvm/lib/System/README.txt:1.5 llvm/lib/System/README.txt:1.6
--- llvm/lib/System/README.txt:1.5	Sat Nov  6 18:58:20 2004
+++ llvm/lib/System/README.txt	Mon Mar 13 23:54:51 2006
@@ -15,7 +15,7 @@
 Complete documentation for the library can be found in the file:
   llvm/docs/SystemLibrary.html 
 or at this URL:
-  http://llvm.cs.uiuc.edu/docs/SystemLibrary.html
+  http://llvm.org/docs/SystemLibrary.html
 
 While we recommend that you read the more detailed documentation, for the 
 impatient, here's a high level summary of the library's requirements.





From reid at x10sys.com  Mon Mar 13 23:55:08 2006
From: reid at x10sys.com (Reid Spencer)
Date: Mon, 13 Mar 2006 23:55:08 -0600
Subject: [llvm-commits] CVS: llvm/utils/NightlyTestTemplate.html 
Message-ID: <200603140555.XAA02949@zion.cs.uiuc.edu>



Changes in directory llvm/utils:

NightlyTestTemplate.html updated: 1.43 -> 1.44
---
Log message:

Convert llvm.cs.uiuc.edu -> llvm.org


---
Diffs of the changes:  (+2 -2)

 NightlyTestTemplate.html |    4 ++--
 1 files changed, 2 insertions(+), 2 deletions(-)


Index: llvm/utils/NightlyTestTemplate.html
diff -u llvm/utils/NightlyTestTemplate.html:1.43 llvm/utils/NightlyTestTemplate.html:1.44
--- llvm/utils/NightlyTestTemplate.html:1.43	Sat Jan 28 13:44:48 2006
+++ llvm/utils/NightlyTestTemplate.html	Mon Mar 13 23:54:52 2006
@@ -29,8 +29,8 @@
 
      
 
 Back to:
      
-Test Results
      
-LLVM Page
      
+Test Results
      
+LLVM Page
      
 
 
 





From reid at x10sys.com  Mon Mar 13 23:55:08 2006
From: reid at x10sys.com (Reid Spencer)
Date: Mon, 13 Mar 2006 23:55:08 -0600
Subject: [llvm-commits] CVS: llvm-test/LICENSE.TXT 
Message-ID: <200603140555.XAA02967@zion.cs.uiuc.edu>



Changes in directory llvm-test:

LICENSE.TXT updated: 1.12 -> 1.13
---
Log message:

Convert llvm.cs.uiuc.edu -> llvm.org


---
Diffs of the changes:  (+1 -1)

 LICENSE.TXT |    2 +-
 1 files changed, 1 insertion(+), 1 deletion(-)


Index: llvm-test/LICENSE.TXT
diff -u llvm-test/LICENSE.TXT:1.12 llvm-test/LICENSE.TXT:1.13
--- llvm-test/LICENSE.TXT:1.12	Tue Feb 14 00:12:20 2006
+++ llvm-test/LICENSE.TXT	Mon Mar 13 23:54:51 2006
@@ -13,7 +13,7 @@
 
     University of Illinois at Urbana-Champaign
 
-    http://llvm.cs.uiuc.edu
+    http://llvm.org/
 
 Permission is hereby granted, free of charge, to any person obtaining a copy of
 this software and associated documentation files (the "Software"), to deal with





From reid at x10sys.com  Mon Mar 13 23:55:08 2006
From: reid at x10sys.com (Reid Spencer)
Date: Mon, 13 Mar 2006 23:55:08 -0600
Subject: [llvm-commits] CVS: llvm/utils/emacs/llvm-mode.el tablegen-mode.el 
Message-ID: <200603140555.XAA02956@zion.cs.uiuc.edu>



Changes in directory llvm/utils/emacs:

llvm-mode.el updated: 1.17 -> 1.18
tablegen-mode.el updated: 1.1 -> 1.2
---
Log message:

Convert llvm.cs.uiuc.edu -> llvm.org


---
Diffs of the changes:  (+2 -2)

 llvm-mode.el     |    2 +-
 tablegen-mode.el |    2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)


Index: llvm/utils/emacs/llvm-mode.el
diff -u llvm/utils/emacs/llvm-mode.el:1.17 llvm/utils/emacs/llvm-mode.el:1.18
--- llvm/utils/emacs/llvm-mode.el:1.17	Fri May 13 15:40:51 2005
+++ llvm/utils/emacs/llvm-mode.el	Mon Mar 13 23:54:52 2006
@@ -1,4 +1,4 @@
-;; Maintainer:  The LLVM team, http://llvm.cs.uiuc.edu/
+;; Maintainer:  The LLVM team, http://llvm.org/
 ;; Description: Major mode for the LLVM assembler language.
 ;; Updated:     2003-06-02
 


Index: llvm/utils/emacs/tablegen-mode.el
diff -u llvm/utils/emacs/tablegen-mode.el:1.1 llvm/utils/emacs/tablegen-mode.el:1.2
--- llvm/utils/emacs/tablegen-mode.el:1.1	Mon Aug 11 14:10:02 2003
+++ llvm/utils/emacs/tablegen-mode.el	Mon Mar 13 23:54:52 2006
@@ -1,4 +1,4 @@
-;; Maintainer:  The LLVM team, http://llvm.cs.uiuc.edu/
+;; Maintainer:  The LLVM team, http://llvm.org/
 ;; Description: Major mode for TableGen description files (part of LLVM project)
 ;; Updated:     2003-08-11
 





From reid at x10sys.com  Mon Mar 13 23:55:08 2006
From: reid at x10sys.com (Reid Spencer)
Date: Mon, 13 Mar 2006 23:55:08 -0600
Subject: [llvm-commits] CVS: llvm/tools/bugpoint/bugpoint.cpp 
Message-ID: <200603140555.XAA02973@zion.cs.uiuc.edu>



Changes in directory llvm/tools/bugpoint:

bugpoint.cpp updated: 1.27 -> 1.28
---
Log message:

Convert llvm.cs.uiuc.edu -> llvm.org


---
Diffs of the changes:  (+1 -1)

 bugpoint.cpp |    2 +-
 1 files changed, 1 insertion(+), 1 deletion(-)


Index: llvm/tools/bugpoint/bugpoint.cpp
diff -u llvm/tools/bugpoint/bugpoint.cpp:1.27 llvm/tools/bugpoint/bugpoint.cpp:1.28
--- llvm/tools/bugpoint/bugpoint.cpp:1.27	Thu Dec 22 14:02:55 2005
+++ llvm/tools/bugpoint/bugpoint.cpp	Mon Mar 13 23:54:51 2006
@@ -51,7 +51,7 @@
 int main(int argc, char **argv) {
   cl::ParseCommandLineOptions(argc, argv,
                               " LLVM automatic testcase reducer. See\nhttp://"
-                              "llvm.cs.uiuc.edu/docs/CommandGuide/bugpoint.html"
+                              "llvm.org/docs/CommandGuide/bugpoint.html"
                               " for more information.\n");
   sys::PrintStackTraceOnErrorSignal();
   sys::SetInterruptFunction(BugpointInterruptFunction);





From reid at x10sys.com  Mon Mar 13 23:55:08 2006
From: reid at x10sys.com (Reid Spencer)
Date: Mon, 13 Mar 2006 23:55:08 -0600
Subject: [llvm-commits] CVS: llvm/utils/vim/llvm.vim tablegen.vim 
Message-ID: <200603140555.XAA02961@zion.cs.uiuc.edu>



Changes in directory llvm/utils/vim:

llvm.vim updated: 1.15 -> 1.16
tablegen.vim updated: 1.3 -> 1.4
---
Log message:

Convert llvm.cs.uiuc.edu -> llvm.org


---
Diffs of the changes:  (+2 -2)

 llvm.vim     |    2 +-
 tablegen.vim |    2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)


Index: llvm/utils/vim/llvm.vim
diff -u llvm/utils/vim/llvm.vim:1.15 llvm/utils/vim/llvm.vim:1.16
--- llvm/utils/vim/llvm.vim:1.15	Fri May 13 15:40:52 2005
+++ llvm/utils/vim/llvm.vim	Mon Mar 13 23:54:52 2006
@@ -1,6 +1,6 @@
 " Vim syntax file
 " Language:   llvm
-" Maintainer: The LLVM team, http://llvm.cs.uiuc.edu/
+" Maintainer: The LLVM team, http://llvm.org/
 " Updated:    2003-06-02
 
 if version < 600


Index: llvm/utils/vim/tablegen.vim
diff -u llvm/utils/vim/tablegen.vim:1.3 llvm/utils/vim/tablegen.vim:1.4
--- llvm/utils/vim/tablegen.vim:1.3	Mon Aug 11 14:14:20 2003
+++ llvm/utils/vim/tablegen.vim	Mon Mar 13 23:54:52 2006
@@ -1,6 +1,6 @@
 " Vim syntax file
 " Language:   TableGen
-" Maintainer: The LLVM team, http://llvm.cs.uiuc.edu/
+" Maintainer: The LLVM team, http://llvm.org/
 " Updated:    2003-08-11
 
 if version < 600





From reid at x10sys.com  Mon Mar 13 23:55:08 2006
From: reid at x10sys.com (Reid Spencer)
Date: Mon, 13 Mar 2006 23:55:08 -0600
Subject: [llvm-commits] CVS: llvm/lib/ExecutionEngine/JIT/Intercept.cpp 
Message-ID: <200603140555.XAA02963@zion.cs.uiuc.edu>



Changes in directory llvm/lib/ExecutionEngine/JIT:

Intercept.cpp updated: 1.24 -> 1.25
---
Log message:

Convert llvm.cs.uiuc.edu -> llvm.org


---
Diffs of the changes:  (+1 -1)

 Intercept.cpp |    2 +-
 1 files changed, 1 insertion(+), 1 deletion(-)


Index: llvm/lib/ExecutionEngine/JIT/Intercept.cpp
diff -u llvm/lib/ExecutionEngine/JIT/Intercept.cpp:1.24 llvm/lib/ExecutionEngine/JIT/Intercept.cpp:1.25
--- llvm/lib/ExecutionEngine/JIT/Intercept.cpp:1.24	Thu Apr 21 17:45:04 2005
+++ llvm/lib/ExecutionEngine/JIT/Intercept.cpp	Mon Mar 13 23:54:51 2006
@@ -46,7 +46,7 @@
 // strategy of making these functions work differently when inlined vs. when
 // not inlined, and hiding their real definitions in a separate archive file
 // that the dynamic linker can't see. For more info, search for
-// 'libc_nonshared.a' on Google, or read http://llvm.cs.uiuc.edu/PR274.
+// 'libc_nonshared.a' on Google, or read http://llvm.org/PR274.
 #if defined(__linux__)
 #if defined(HAVE_SYS_STAT_H)
 #include 





From reid at x10sys.com  Tue Mar 14 00:00:04 2006
From: reid at x10sys.com (Reid Spencer)
Date: Tue, 14 Mar 2006 00:00:04 -0600
Subject: [llvm-commits] CVS: llvm/utils/TableGen/IntrinsicEmitter.cpp 
Message-ID: <200603140600.AAA03072@zion.cs.uiuc.edu>



Changes in directory llvm/utils/TableGen:

IntrinsicEmitter.cpp updated: 1.8 -> 1.9
---
Log message:

Add a newline at the end to avoid gcc warnings.


---
Diffs of the changes:  (+1 -1)

 IntrinsicEmitter.cpp |    2 +-
 1 files changed, 1 insertion(+), 1 deletion(-)


Index: llvm/utils/TableGen/IntrinsicEmitter.cpp
diff -u llvm/utils/TableGen/IntrinsicEmitter.cpp:1.8 llvm/utils/TableGen/IntrinsicEmitter.cpp:1.9
--- llvm/utils/TableGen/IntrinsicEmitter.cpp:1.8	Mon Mar 13 17:08:44 2006
+++ llvm/utils/TableGen/IntrinsicEmitter.cpp	Mon Mar 13 23:59:52 2006
@@ -252,4 +252,4 @@
   }
   OS << "  }\n";
   OS << "#endif\n\n";
-}
\ No newline at end of file
+}





From reid at x10sys.com  Tue Mar 14 00:05:18 2006
From: reid at x10sys.com (Reid Spencer)
Date: Tue, 14 Mar 2006 00:05:18 -0600
Subject: [llvm-commits] CVS: llvm/utils/emacs/emacs.el 
Message-ID: <200603140605.AAA03106@zion.cs.uiuc.edu>



Changes in directory llvm/utils/emacs:

emacs.el updated: 1.1 -> 1.2
---
Log message:

Change llvm.cs.uiuc.edu -> llvm.org


---
Diffs of the changes:  (+1 -1)

 emacs.el |    2 +-
 1 files changed, 1 insertion(+), 1 deletion(-)


Index: llvm/utils/emacs/emacs.el
diff -u llvm/utils/emacs/emacs.el:1.1 llvm/utils/emacs/emacs.el:1.2
--- llvm/utils/emacs/emacs.el:1.1	Sun Apr 24 12:09:19 2005
+++ llvm/utils/emacs/emacs.el	Tue Mar 14 00:05:05 2006
@@ -1,5 +1,5 @@
 ;; LLVM coding style guidelines in emacs
-;; Maintainer: LLVM Team, http://llvm.cs.uiuc.edu
+;; Maintainer: LLVM Team, http://llvm.org/
 ;; Modified:   2005-04-24
 
 ;; Max 80 cols per line, indent by two spaces, no tabs.





From reid at x10sys.com  Tue Mar 14 00:05:19 2006
From: reid at x10sys.com (Reid Spencer)
Date: Tue, 14 Mar 2006 00:05:19 -0600
Subject: [llvm-commits] 
	CVS: llvm-test/MultiSource/Benchmarks/MallocBench/gs/cframe_.h
Message-ID: <200603140605.AAA03110@zion.cs.uiuc.edu>



Changes in directory llvm-test/MultiSource/Benchmarks/MallocBench/gs:

cframe_.h updated: 1.1 -> 1.2
---
Log message:

Change llvm.cs.uiuc.edu -> llvm.org


---
Diffs of the changes:  (+1 -1)

 cframe_.h |    2 +-
 1 files changed, 1 insertion(+), 1 deletion(-)


Index: llvm-test/MultiSource/Benchmarks/MallocBench/gs/cframe_.h
diff -u llvm-test/MultiSource/Benchmarks/MallocBench/gs/cframe_.h:1.1 llvm-test/MultiSource/Benchmarks/MallocBench/gs/cframe_.h:1.2
--- llvm-test/MultiSource/Benchmarks/MallocBench/gs/cframe_.h:1.1	Wed Feb 18 13:58:29 2004
+++ llvm-test/MultiSource/Benchmarks/MallocBench/gs/cframe_.h	Tue Mar 14 00:05:05 2006
@@ -1,5 +1,5 @@
 /*
- * LLVM - http://llvm.cs.uiuc.edu
+ * LLVM - http://llvm.org/
  *
  * Changes:
  *  1) 2/18/2004





From reid at x10sys.com  Tue Mar 14 00:08:17 2006
From: reid at x10sys.com (Reid Spencer)
Date: Tue, 14 Mar 2006 00:08:17 -0600
Subject: [llvm-commits] CVS: llvm/utils/llvmgrep llvmdo 
Message-ID: <200603140608.AAA03127@zion.cs.uiuc.edu>



Changes in directory llvm/utils:

llvmgrep updated: 1.8 -> 1.9
llvmdo updated: 1.10 -> 1.11
---
Log message:

Allow a sequence of digits at the end of the directory name when trying to
determine the top directory. This allows the tool to find the correct top
directory when you have something like:

   /x/llvm
   /x/llvm2
   /x/llvm3

Previously the scripts would always find /x/llvm even if you were in the
llvm2 or llvm3 directory because the pattern didn't allow the digits at 
the end of the path.


---
Diffs of the changes:  (+3 -2)

 llvmdo   |    2 +-
 llvmgrep |    3 ++-
 2 files changed, 3 insertions(+), 2 deletions(-)


Index: llvm/utils/llvmgrep
diff -u llvm/utils/llvmgrep:1.8 llvm/utils/llvmgrep:1.9
--- llvm/utils/llvmgrep:1.8	Thu Oct  7 11:03:21 2004
+++ llvm/utils/llvmgrep	Tue Mar 14 00:08:05 2006
@@ -18,7 +18,8 @@
 # details.
 ##===----------------------------------------------------------------------===##
 
-TOPDIR=`pwd | sed -e 's#\(.*/llvm\).*#\1#'`
+TOPDIR=`pwd | sed -e 's#\(.*/llvm[0-9]*\).*#\1#'`
+echo $TOPDIR
 if test -d "$TOPDIR" ; then
   cd $TOPDIR
   case `uname -s` in


Index: llvm/utils/llvmdo
diff -u llvm/utils/llvmdo:1.10 llvm/utils/llvmdo:1.11
--- llvm/utils/llvmdo:1.10	Thu Jan 19 16:01:51 2006
+++ llvm/utils/llvmdo	Tue Mar 14 00:08:05 2006
@@ -43,7 +43,7 @@
   exit 1
 fi
 shift;
-TOPDIR=`pwd | sed -e 's#\(.*/llvm\).*#\1#'`
+TOPDIR=`pwd | sed -e 's#\(.*/llvm[0-9]*\).*#\1#'`
 if test -d "$TOPDIR" ; then
   cd $TOPDIR
   case `uname -s` in





From lattner at cs.uiuc.edu  Tue Mar 14 00:54:44 2006
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Tue, 14 Mar 2006 00:54:44 -0600
Subject: [llvm-commits] 
	CVS: llvm/test/Regression/Transforms/Reassociate/shift-factor.ll
Message-ID: <200603140654.AAA03541@zion.cs.uiuc.edu>



Changes in directory llvm/test/Regression/Transforms/Reassociate:

shift-factor.ll added (r1.1)
---
Log message:

Test that we can reassociate (x<<1)+(y<<1) -> (X+Y)<<1.


---
Diffs of the changes:  (+11 -0)

 shift-factor.ll |   11 +++++++++++
 1 files changed, 11 insertions(+)


Index: llvm/test/Regression/Transforms/Reassociate/shift-factor.ll
diff -c /dev/null llvm/test/Regression/Transforms/Reassociate/shift-factor.ll:1.1
*** /dev/null	Tue Mar 14 00:54:42 2006
--- llvm/test/Regression/Transforms/Reassociate/shift-factor.ll	Tue Mar 14 00:54:32 2006
***************
*** 0 ****
--- 1,11 ----
+ ; There should be exactly one shift and one add left.
+ ; RUN: llvm-as < %s | opt -reassociate -instcombine | llvm-dis | grep shl | wc -l | grep 1 &&
+ ; RUN: llvm-as < %s | opt -reassociate -instcombine | llvm-dis | grep add | wc -l | grep 1
+ 
+ int %test(int %X, int %Y) {
+         %tmp.2 = shl int %X, ubyte 1            ;  [#uses=1]
+         %tmp.6 = shl int %Y, ubyte 1            ;  [#uses=1]
+         %tmp.4 = add int %tmp.6, %tmp.2         ;  [#uses=1]
+         ret int %tmp.4
+ }
+ 





From lattner at cs.uiuc.edu  Tue Mar 14 00:55:30 2006
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Tue, 14 Mar 2006 00:55:30 -0600
Subject: [llvm-commits] CVS: llvm/lib/Transforms/Scalar/Reassociate.cpp 
Message-ID: <200603140655.AAA03575@zion.cs.uiuc.edu>



Changes in directory llvm/lib/Transforms/Scalar:

Reassociate.cpp updated: 1.57 -> 1.58
---
Log message:

Promote shifts by a constant to multiplies so that we can reassociate 
(x<<1)+(y<<1) -> (X+Y)<<1.  This implements 
Transforms/Reassociate/shift-factor.ll


---
Diffs of the changes:  (+17 -13)

 Reassociate.cpp |   30 +++++++++++++++++-------------
 1 files changed, 17 insertions(+), 13 deletions(-)


Index: llvm/lib/Transforms/Scalar/Reassociate.cpp
diff -u llvm/lib/Transforms/Scalar/Reassociate.cpp:1.57 llvm/lib/Transforms/Scalar/Reassociate.cpp:1.58
--- llvm/lib/Transforms/Scalar/Reassociate.cpp:1.57	Sat Mar  4 03:31:13 2006
+++ llvm/lib/Transforms/Scalar/Reassociate.cpp	Tue Mar 14 00:55:18 2006
@@ -410,19 +410,23 @@
 /// by one, change this into a multiply by a constant to assist with further
 /// reassociation.
 static Instruction *ConvertShiftToMul(Instruction *Shl) {
-  if (!isReassociableOp(Shl->getOperand(0), Instruction::Mul) &&
-      !(Shl->hasOneUse() && isReassociableOp(Shl->use_back(),Instruction::Mul)))
-    return 0;
-
-  Constant *MulCst = ConstantInt::get(Shl->getType(), 1);
-  MulCst = ConstantExpr::getShl(MulCst, cast(Shl->getOperand(1)));
-
-  std::string Name = Shl->getName();  Shl->setName("");
-  Instruction *Mul = BinaryOperator::createMul(Shl->getOperand(0), MulCst,
-                                               Name, Shl);
-  Shl->replaceAllUsesWith(Mul);
-  Shl->eraseFromParent();
-  return Mul;
+  // If an operand of this shift is a reassociable multiply, or if the shift
+  // is used by a reassociable multiply or add, turn into a multiply.
+  if (isReassociableOp(Shl->getOperand(0), Instruction::Mul) ||
+      (Shl->hasOneUse() && 
+       (isReassociableOp(Shl->use_back(), Instruction::Mul) ||
+        isReassociableOp(Shl->use_back(), Instruction::Add)))) {
+    Constant *MulCst = ConstantInt::get(Shl->getType(), 1);
+    MulCst = ConstantExpr::getShl(MulCst, cast(Shl->getOperand(1)));
+    
+    std::string Name = Shl->getName();  Shl->setName("");
+    Instruction *Mul = BinaryOperator::createMul(Shl->getOperand(0), MulCst,
+                                                 Name, Shl);
+    Shl->replaceAllUsesWith(Mul);
+    Shl->eraseFromParent();
+    return Mul;
+  }
+  return 0;
 }
 
 // Scan backwards and forwards among values with the same rank as element i to





From lattner at cs.uiuc.edu  Tue Mar 14 00:57:46 2006
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Tue, 14 Mar 2006 00:57:46 -0600
Subject: [llvm-commits] CVS: llvm/lib/Target/README.txt 
Message-ID: <200603140657.AAA03710@zion.cs.uiuc.edu>



Changes in directory llvm/lib/Target:

README.txt updated: 1.19 -> 1.20
---
Log message:

transformation implemented


---
Diffs of the changes:  (+0 -10)

 README.txt |   10 ----------
 1 files changed, 10 deletions(-)


Index: llvm/lib/Target/README.txt
diff -u llvm/lib/Target/README.txt:1.19 llvm/lib/Target/README.txt:1.20
--- llvm/lib/Target/README.txt:1.19	Mon Mar 13 17:19:10 2006
+++ llvm/lib/Target/README.txt	Tue Mar 14 00:57:34 2006
@@ -88,16 +88,6 @@
 
 //===---------------------------------------------------------------------===//
 
-Reassociate is missing this:
-
-int test(int X, int Y) {
- return (X+X+Y+Y);  // (X+Y) << 1;
-}
-
-it needs to turn the shifts into multiplies to get it.
-
-//===---------------------------------------------------------------------===//
-
 Reassociate should turn: X*X*X*X -> t=(X*X) (t*t) to eliminate a multiply.
 
 //===---------------------------------------------------------------------===//





From lattner at cs.uiuc.edu  Tue Mar 14 01:11:23 2006
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Tue, 14 Mar 2006 01:11:23 -0600
Subject: [llvm-commits] CVS: llvm/lib/Transforms/Scalar/Reassociate.cpp 
Message-ID: <200603140711.BAA03933@zion.cs.uiuc.edu>



Changes in directory llvm/lib/Transforms/Scalar:

Reassociate.cpp updated: 1.58 -> 1.59
---
Log message:

extract some code into a method, no functionality change


---
Diffs of the changes:  (+56 -50)

 Reassociate.cpp |  106 +++++++++++++++++++++++++++++---------------------------
 1 files changed, 56 insertions(+), 50 deletions(-)


Index: llvm/lib/Transforms/Scalar/Reassociate.cpp
diff -u llvm/lib/Transforms/Scalar/Reassociate.cpp:1.58 llvm/lib/Transforms/Scalar/Reassociate.cpp:1.59
--- llvm/lib/Transforms/Scalar/Reassociate.cpp:1.58	Tue Mar 14 00:55:18 2006
+++ llvm/lib/Transforms/Scalar/Reassociate.cpp	Tue Mar 14 01:11:11 2006
@@ -78,6 +78,7 @@
   private:
     void BuildRankMap(Function &F);
     unsigned getRank(Value *V);
+    void ReassociateExpression(BinaryOperator *I);
     void RewriteExprTree(BinaryOperator *I, unsigned Idx,
                          std::vector &Ops);
     Value *OptimizeExpression(BinaryOperator *I, std::vector &Ops);
@@ -752,57 +753,62 @@
         cast(I->use_back())->getOpcode() == Instruction::Sub)
       continue;
 
-    // First, walk the expression tree, linearizing the tree, collecting
-    std::vector Ops;
-    LinearizeExprTree(I, Ops);
-
-    DEBUG(std::cerr << "RAIn:\t"; PrintOps(I, Ops);
-          std::cerr << "\n");
-
-    // Now that we have linearized the tree to a list and have gathered all of
-    // the operands and their ranks, sort the operands by their rank.  Use a
-    // stable_sort so that values with equal ranks will have their relative
-    // positions maintained (and so the compiler is deterministic).  Note that
-    // this sorts so that the highest ranking values end up at the beginning of
-    // the vector.
-    std::stable_sort(Ops.begin(), Ops.end());
-
-    // OptimizeExpression - Now that we have the expression tree in a convenient
-    // sorted form, optimize it globally if possible.
-    if (Value *V = OptimizeExpression(I, Ops)) {
-      // This expression tree simplified to something that isn't a tree,
-      // eliminate it.
-      DEBUG(std::cerr << "Reassoc to scalar: " << *V << "\n");
-      I->replaceAllUsesWith(V);
-      RemoveDeadBinaryOp(I);
-      continue;
-    }
-
-    // We want to sink immediates as deeply as possible except in the case where
-    // this is a multiply tree used only by an add, and the immediate is a -1.
-    // In this case we reassociate to put the negation on the outside so that we
-    // can fold the negation into the add: (-X)*Y + Z -> Z-X*Y
-    if (I->getOpcode() == Instruction::Mul && I->hasOneUse() &&
-        cast(I->use_back())->getOpcode() == Instruction::Add &&
-        isa(Ops.back().Op) &&
-        cast(Ops.back().Op)->isAllOnesValue()) {
-      Ops.insert(Ops.begin(), Ops.back());
-      Ops.pop_back();
-    }
-
-    DEBUG(std::cerr << "RAOut:\t"; PrintOps(I, Ops);
-          std::cerr << "\n");
+    ReassociateExpression(I);
+  }
+}
 
-    if (Ops.size() == 1) {
-      // This expression tree simplified to something that isn't a tree,
-      // eliminate it.
-      I->replaceAllUsesWith(Ops[0].Op);
-      RemoveDeadBinaryOp(I);
-    } else {
-      // Now that we ordered and optimized the expressions, splat them back into
-      // the expression tree, removing any unneeded nodes.
-      RewriteExprTree(I, 0, Ops);
-    }
+void Reassociate::ReassociateExpression(BinaryOperator *I) {
+  
+  // First, walk the expression tree, linearizing the tree, collecting
+  std::vector Ops;
+  LinearizeExprTree(I, Ops);
+  
+  DEBUG(std::cerr << "RAIn:\t"; PrintOps(I, Ops);
+        std::cerr << "\n");
+  
+  // Now that we have linearized the tree to a list and have gathered all of
+  // the operands and their ranks, sort the operands by their rank.  Use a
+  // stable_sort so that values with equal ranks will have their relative
+  // positions maintained (and so the compiler is deterministic).  Note that
+  // this sorts so that the highest ranking values end up at the beginning of
+  // the vector.
+  std::stable_sort(Ops.begin(), Ops.end());
+  
+  // OptimizeExpression - Now that we have the expression tree in a convenient
+  // sorted form, optimize it globally if possible.
+  if (Value *V = OptimizeExpression(I, Ops)) {
+    // This expression tree simplified to something that isn't a tree,
+    // eliminate it.
+    DEBUG(std::cerr << "Reassoc to scalar: " << *V << "\n");
+    I->replaceAllUsesWith(V);
+    RemoveDeadBinaryOp(I);
+    return;
+  }
+  
+  // We want to sink immediates as deeply as possible except in the case where
+  // this is a multiply tree used only by an add, and the immediate is a -1.
+  // In this case we reassociate to put the negation on the outside so that we
+  // can fold the negation into the add: (-X)*Y + Z -> Z-X*Y
+  if (I->getOpcode() == Instruction::Mul && I->hasOneUse() &&
+      cast(I->use_back())->getOpcode() == Instruction::Add &&
+      isa(Ops.back().Op) &&
+      cast(Ops.back().Op)->isAllOnesValue()) {
+    Ops.insert(Ops.begin(), Ops.back());
+    Ops.pop_back();
+  }
+  
+  DEBUG(std::cerr << "RAOut:\t"; PrintOps(I, Ops);
+        std::cerr << "\n");
+  
+  if (Ops.size() == 1) {
+    // This expression tree simplified to something that isn't a tree,
+    // eliminate it.
+    I->replaceAllUsesWith(Ops[0].Op);
+    RemoveDeadBinaryOp(I);
+  } else {
+    // Now that we ordered and optimized the expressions, splat them back into
+    // the expression tree, removing any unneeded nodes.
+    RewriteExprTree(I, 0, Ops);
   }
 }
 





From lattner at cs.uiuc.edu  Tue Mar 14 02:13:21 2006
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Tue, 14 Mar 2006 02:13:21 -0600
Subject: [llvm-commits] 
	CVS: llvm/test/Regression/Transforms/Reassociate/mul-factor3.ll
	mulfactor2.ll 
Message-ID: <200603140813.CAA06235@zion.cs.uiuc.edu>



Changes in directory llvm/test/Regression/Transforms/Reassociate:

mul-factor3.ll added (r1.1)
mulfactor2.ll updated: 1.1 -> 1.2
---
Log message:

new testcase from a FIXME in the code


---
Diffs of the changes:  (+16 -2)

 mul-factor3.ll |   14 ++++++++++++++
 mulfactor2.ll  |    4 ++--
 2 files changed, 16 insertions(+), 2 deletions(-)


Index: llvm/test/Regression/Transforms/Reassociate/mul-factor3.ll
diff -c /dev/null llvm/test/Regression/Transforms/Reassociate/mul-factor3.ll:1.1
*** /dev/null	Tue Mar 14 02:13:19 2006
--- llvm/test/Regression/Transforms/Reassociate/mul-factor3.ll	Tue Mar 14 02:13:09 2006
***************
*** 0 ****
--- 1,14 ----
+ ; This should be one add and two multiplies.
+ 
+ ; RUN: llvm-as < %s | opt -reassociate -instcombine | llvm-dis | grep mul | wc -l | grep 2 &&
+ ; RUN: llvm-as < %s | opt -reassociate -instcombine | llvm-dis | grep add | wc -l | grep 1
+ 
+ int %test(int %A, int %B, int %C) {
+ 	%aa = mul int %A, %A
+ 	%aab = mul int %aa, %B
+ 
+ 	%ac = mul int %A, %C
+ 	%aac = mul int %ac, %A
+ 	%r = add int %aab, %aac
+ 	ret int %r
+ }


Index: llvm/test/Regression/Transforms/Reassociate/mulfactor2.ll
diff -u llvm/test/Regression/Transforms/Reassociate/mulfactor2.ll:1.1 llvm/test/Regression/Transforms/Reassociate/mulfactor2.ll:1.2
--- llvm/test/Regression/Transforms/Reassociate/mulfactor2.ll:1.1	Sat Mar  4 03:35:02 2006
+++ llvm/test/Regression/Transforms/Reassociate/mulfactor2.ll	Tue Mar 14 02:13:09 2006
@@ -1,7 +1,7 @@
 ; This should turn into one multiply and one add.
 
-; RUN: llvm-as < mulfactor2.ll | opt -instcombine -reassociate -instcombine | llvm-dis | grep mul | wc -l | grep 1 &&
-; RUN: llvm-as < mulfactor2.ll | opt -instcombine -reassociate -instcombine | llvm-dis | grep add | wc -l | grep 1
+; RUN: llvm-as < %s | opt -instcombine -reassociate -instcombine | llvm-dis | grep mul | wc -l | grep 1 &&
+; RUN: llvm-as < %s | opt -instcombine -reassociate -instcombine | llvm-dis | grep add | wc -l | grep 1
 int %main(int %t) {
         %tmp.3 = mul int %t, 12         ;  [#uses=1]
         %tmp.4 = add int %tmp.3, 5              ;  [#uses=1]





From lattner at cs.uiuc.edu  Tue Mar 14 10:04:41 2006
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Tue, 14 Mar 2006 10:04:41 -0600
Subject: [llvm-commits] CVS: llvm/lib/Transforms/Scalar/Reassociate.cpp 
Message-ID: <200603141604.KAA18329@zion.cs.uiuc.edu>



Changes in directory llvm/lib/Transforms/Scalar:

Reassociate.cpp updated: 1.59 -> 1.60
---
Log message:

Implement a FIXME, recusively reassociating 
A*A*B + A*A*C   -->   A*(A*B+A*C)   -->   A*(A*(B+C))

This implements Reassociate/mul-factor3.ll



---
Diffs of the changes:  (+65 -26)

 Reassociate.cpp |   91 ++++++++++++++++++++++++++++++++++++++++----------------
 1 files changed, 65 insertions(+), 26 deletions(-)


Index: llvm/lib/Transforms/Scalar/Reassociate.cpp
diff -u llvm/lib/Transforms/Scalar/Reassociate.cpp:1.59 llvm/lib/Transforms/Scalar/Reassociate.cpp:1.60
--- llvm/lib/Transforms/Scalar/Reassociate.cpp:1.59	Tue Mar 14 01:11:11 2006
+++ llvm/lib/Transforms/Scalar/Reassociate.cpp	Tue Mar 14 10:04:29 2006
@@ -79,8 +79,8 @@
     void BuildRankMap(Function &F);
     unsigned getRank(Value *V);
     void ReassociateExpression(BinaryOperator *I);
-    void RewriteExprTree(BinaryOperator *I, unsigned Idx,
-                         std::vector &Ops);
+    void RewriteExprTree(BinaryOperator *I, std::vector &Ops,
+                         unsigned Idx = 0);
     Value *OptimizeExpression(BinaryOperator *I, std::vector &Ops);
     void LinearizeExprTree(BinaryOperator *I, std::vector &Ops);
     void LinearizeExpr(BinaryOperator *I);
@@ -174,7 +174,7 @@
 /// isReassociableOp - Return true if V is an instruction of the specified
 /// opcode and if it only has one use.
 static BinaryOperator *isReassociableOp(Value *V, unsigned Opcode) {
-  if (V->hasOneUse() && isa(V) &&
+  if ((V->hasOneUse() || V->use_empty()) && isa(V) &&
       cast(V)->getOpcode() == Opcode)
     return cast(V);
   return 0;
@@ -234,6 +234,10 @@
 /// form of the the expression (((a+b)+c)+d), and collects information about the
 /// rank of the non-tree operands.
 ///
+/// NOTE: These intentionally destroys the expression tree operands (turning
+/// them into undef values) to reduce #uses of the values.  This means that the
+/// caller MUST use something like RewriteExprTree to put the values back in.
+///
 void Reassociate::LinearizeExprTree(BinaryOperator *I,
                                     std::vector &Ops) {
   Value *LHS = I->getOperand(0), *RHS = I->getOperand(1);
@@ -262,6 +266,10 @@
       // such, just remember these operands and their rank.
       Ops.push_back(ValueEntry(getRank(LHS), LHS));
       Ops.push_back(ValueEntry(getRank(RHS), RHS));
+      
+      // Clear the leaves out.
+      I->setOperand(0, UndefValue::get(I->getType()));
+      I->setOperand(1, UndefValue::get(I->getType()));
       return;
     } else {
       // Turn X+(Y+Z) -> (Y+Z)+X
@@ -293,13 +301,17 @@
 
   // Remember the RHS operand and its rank.
   Ops.push_back(ValueEntry(getRank(RHS), RHS));
+  
+  // Clear the RHS leaf out.
+  I->setOperand(1, UndefValue::get(I->getType()));
 }
 
 // RewriteExprTree - Now that the operands for this expression tree are
 // linearized and optimized, emit them in-order.  This function is written to be
 // tail recursive.
-void Reassociate::RewriteExprTree(BinaryOperator *I, unsigned i,
-                                  std::vector &Ops) {
+void Reassociate::RewriteExprTree(BinaryOperator *I,
+                                  std::vector &Ops,
+                                  unsigned i) {
   if (i+2 == Ops.size()) {
     if (I->getOperand(0) != Ops[i].Op ||
         I->getOperand(1) != Ops[i+1].Op) {
@@ -334,7 +346,7 @@
   // Compactify the tree instructions together with each other to guarantee
   // that the expression tree is dominated by all of Ops.
   LHS->moveBefore(I);
-  RewriteExprTree(LHS, i+1, Ops);
+  RewriteExprTree(LHS, Ops, i+1);
 }
 
 
@@ -474,14 +486,36 @@
       Factors.erase(Factors.begin()+i);
       break;
     }
-  if (!FoundFactor) return 0;
+  if (!FoundFactor) {
+    // Make sure to restore the operands to the expression tree.
+    RewriteExprTree(BO, Factors);
+    return 0;
+  }
   
   if (Factors.size() == 1) return Factors[0].Op;
   
-  RewriteExprTree(BO, 0, Factors);
+  RewriteExprTree(BO, Factors);
   return BO;
 }
 
+/// FindSingleUseMultiplyFactors - If V is a single-use multiply, recursively
+/// add its operands as factors, otherwise add V to the list of factors.
+static void FindSingleUseMultiplyFactors(Value *V,
+                                         std::vector &Factors) {
+  BinaryOperator *BO;
+  if ((!V->hasOneUse() && !V->use_empty()) ||
+      !(BO = dyn_cast(V)) ||
+      BO->getOpcode() != Instruction::Mul) {
+    Factors.push_back(V);
+    return;
+  }
+  
+  // Otherwise, add the LHS and RHS to the list of factors.
+  FindSingleUseMultiplyFactors(BO->getOperand(1), Factors);
+  FindSingleUseMultiplyFactors(BO->getOperand(0), Factors);
+}
+
+
 
 Value *Reassociate::OptimizeExpression(BinaryOperator *I,
                                        std::vector &Ops) {
@@ -627,26 +661,26 @@
     if (!I->getType()->isFloatingPoint()) {
       for (unsigned i = 0, e = Ops.size(); i != e; ++i) {
         if (BinaryOperator *BOp = dyn_cast(Ops[i].Op))
-          if (BOp->getOpcode() == Instruction::Mul && BOp->hasOneUse()) {
+          if (BOp->getOpcode() == Instruction::Mul && BOp->use_empty()) {
             // Compute all of the factors of this added value.
-            std::vector Factors;
-            LinearizeExprTree(BOp, Factors);
+            std::vector Factors;
+            FindSingleUseMultiplyFactors(BOp, Factors);
             assert(Factors.size() > 1 && "Bad linearize!");
             
             // Add one to FactorOccurrences for each unique factor in this op.
             if (Factors.size() == 2) {
-              unsigned Occ = ++FactorOccurrences[Factors[0].Op];
-              if (Occ > MaxOcc) { MaxOcc = Occ; MaxOccVal = Factors[0].Op; }
-              if (Factors[0].Op != Factors[1].Op) {   // Don't double count A*A.
-                Occ = ++FactorOccurrences[Factors[1].Op];
-                if (Occ > MaxOcc) { MaxOcc = Occ; MaxOccVal = Factors[1].Op; }
+              unsigned Occ = ++FactorOccurrences[Factors[0]];
+              if (Occ > MaxOcc) { MaxOcc = Occ; MaxOccVal = Factors[0]; }
+              if (Factors[0] != Factors[1]) {   // Don't double count A*A.
+                Occ = ++FactorOccurrences[Factors[1]];
+                if (Occ > MaxOcc) { MaxOcc = Occ; MaxOccVal = Factors[1]; }
               }
             } else {
               std::set Duplicates;
               for (unsigned i = 0, e = Factors.size(); i != e; ++i)
-                if (Duplicates.insert(Factors[i].Op).second) {
-                  unsigned Occ = ++FactorOccurrences[Factors[i].Op];
-                  if (Occ > MaxOcc) { MaxOcc = Occ; MaxOccVal = Factors[i].Op; }
+                if (Duplicates.insert(Factors[i]).second) {
+                  unsigned Occ = ++FactorOccurrences[Factors[i]];
+                  if (Occ > MaxOcc) { MaxOcc = Occ; MaxOccVal = Factors[i]; }
                 }
             }
           }
@@ -675,21 +709,26 @@
       // No need for extra uses anymore.
       delete DummyInst;
 
+      unsigned NumAddedValues = NewMulOps.size();
       Value *V = EmitAddTreeOfValues(I, NewMulOps);
-      // FIXME: Must optimize V now, to handle this case:
-      // A*A*B + A*A*C -> A*(A*B+A*C)   -> A*(A*(B+C))
-      V = BinaryOperator::createMul(V, MaxOccVal, "tmp", I);
+      Value *V2 = BinaryOperator::createMul(V, MaxOccVal, "tmp", I);
 
+      // Now that we have inserted V and its sole use, optimize it. This allows
+      // us to handle cases that require multiple factoring steps, such as this:
+      // A*A*B + A*A*C   -->   A*(A*B+A*C)   -->   A*(A*(B+C))
+      if (NumAddedValues > 1)
+        ReassociateExpression(cast(V));
+      
       ++NumFactor;
       
       if (Ops.size() == 0)
-        return V;
+        return V2;
 
       // Add the new value to the list of things being added.
-      Ops.insert(Ops.begin(), ValueEntry(getRank(V), V));
+      Ops.insert(Ops.begin(), ValueEntry(getRank(V2), V2));
       
       // Rewrite the tree so that there is now a use of V.
-      RewriteExprTree(I, 0, Ops);
+      RewriteExprTree(I, Ops);
       return OptimizeExpression(I, Ops);
     }
     break;
@@ -808,7 +847,7 @@
   } else {
     // Now that we ordered and optimized the expressions, splat them back into
     // the expression tree, removing any unneeded nodes.
-    RewriteExprTree(I, 0, Ops);
+    RewriteExprTree(I, Ops);
   }
 }
 





From lattner at cs.uiuc.edu  Tue Mar 14 11:57:01 2006
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Tue, 14 Mar 2006 11:57:01 -0600
Subject: [llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp 
Message-ID: <200603141757.LAA18954@zion.cs.uiuc.edu>



Changes in directory llvm/lib/Target/PowerPC:

PPCISelDAGToDAG.cpp updated: 1.166 -> 1.167
---
Log message:

Fix an off by one error that caused PPC LLC failures last night.


---
Diffs of the changes:  (+1 -1)

 PPCISelDAGToDAG.cpp |    2 +-
 1 files changed, 1 insertion(+), 1 deletion(-)


Index: llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
diff -u llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp:1.166 llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp:1.167
--- llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp:1.166	Mon Mar 13 17:20:37 2006
+++ llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp	Tue Mar 14 11:56:49 2006
@@ -208,7 +208,7 @@
   SSARegMap *RegMap = DAG.getMachineFunction().getSSARegMap();
   bool HasVectorVReg = false;
   for (unsigned i = MRegisterInfo::FirstVirtualRegister, 
-       e = RegMap->getLastVirtReg(); i != e; ++i)
+       e = RegMap->getLastVirtReg()+1; i != e; ++i)
     if (RegMap->getRegClass(i) == &PPC::VRRCRegClass) {
       HasVectorVReg = true;
       break;





From jlaskey at apple.com  Tue Mar 14 12:08:58 2006
From: jlaskey at apple.com (Jim Laskey)
Date: Tue, 14 Mar 2006 12:08:58 -0600
Subject: [llvm-commits] CVS: llvm/docs/SourceLevelDebugging.html 
Message-ID: <200603141808.MAA19074@zion.cs.uiuc.edu>



Changes in directory llvm/docs:

SourceLevelDebugging.html updated: 1.12 -> 1.13
---
Log message:

Bring debugging information up to date.


---
Diffs of the changes:  (+1171 -641)

 SourceLevelDebugging.html | 1812 +++++++++++++++++++++++++++++-----------------
 1 files changed, 1171 insertions(+), 641 deletions(-)


Index: llvm/docs/SourceLevelDebugging.html
diff -u llvm/docs/SourceLevelDebugging.html:1.12 llvm/docs/SourceLevelDebugging.html:1.13
--- llvm/docs/SourceLevelDebugging.html:1.12	Mon Mar 13 23:39:39 2006
+++ llvm/docs/SourceLevelDebugging.html	Tue Mar 14 12:08:46 2006
@@ -17,46 +17,41 @@
   
        
     
      1. Philosophy behind LLVM debugging information
        2. 
     
      2. Debugging optimized code
        3. 
-    
      3. Future work
        4. 
   
      
-  
    1. Using the llvm-db tool
-  
        
-    
      1. Limitations of llvm-db
        2. 
-    
      2. A sample llvm-db session
        3. 
-    
      3. Starting the debugger
        4. 
-    
      4. Commands recognized by the debugger
        5. 
-  
      2. 
-
-  
    2. Architecture of the LLVM debugger
-  
        
-    
      1. The Debugger and InferiorProcess classes
        2. 
-    
      2. The RuntimeInfo, ProgramInfo, and SourceLanguage classes
        3. 
-    
      3. The llvm-db tool
        4. 
-    
      4. Short-term TODO list
        5. 
-  
      3. 
-
   
    3. Debugging information format
   
        
-    
      1. Anchors for global objects
        2. 
-    
      2. Representing stopping points in the source program
        3. 
-    
      3. Object lifetimes and scoping
        4. 
-    
      4. Object descriptor formats
+    
      5. Debug information descriptors
     
        6. 
+    
      6. Debugger intrinsic functions
+      
        7. 
-    
      7. Debugger intrinsic functions
        8. 
-    
      8. Values for debugger tags
        9. 
+    
      9. Representing stopping points in the
+                                           source program
        10. 
   
      4. 
   
    4. C/C++ front-end specific debug information
   
        
-    
      1. Program Scope Entries
-    
        2. 
-    
      2. Data objects (program variables)
        3. 
+    
      3. C/C++ source file information
        4. 
+    
      4. C/C++ global variable information
        5. 
+    
      5. C/C++ function information
        6. 
+    
      6. C/C++ basic types
        7. 
+    
      7. C/C++ derived types
        8. 
+    
      8. C/C++ struct/union types
        9. 
+    
      9. C/C++ enumeration types
        10. 
   
      5. 
 
 
@@ -67,7 +62,8 @@
 
 
 
      
-  
      Written by Chris Lattner
      
+  
      Written by Chris Lattner
+            and Jim Laskey
      
 
      
 
 
@@ -78,15 +74,10 @@
 
      
 
 
      This document is the central repository for all information pertaining to
-debug information in LLVM.  It describes the user
-interface for the llvm-db tool, which provides a 
-powerful source-level debugger
-to users of LLVM-based compilers.  It then describes the various components that make up the debugger and the
-libraries which future clients may use.  Finally, it describes the actual format that the LLVM debug information takes,
-which is useful for those interested in creating front-ends or dealing directly
-with the information.
      
+debug information in LLVM.  It describes the actual format
+that the LLVM debug information takes, which is useful for those interested
+in creating front-ends or dealing directly with the information.  Further, this
+document provides specifc examples of what debug information for C/C++.
      
 
 
      
 
@@ -133,15 +124,13 @@
 currently uses working draft 7 of the Dwarf 3 standard).
      
 
-
      When a program is debugged, the debugger interacts with the user and turns
-the stored debug information into source-language specific information.  As
-such, the debugger must be aware of the source-language, and is thus tied to a
-specific language of family of languages.  The LLVM
-debugger is designed to be modular in its support for source-languages.
      
+
      When a program is being debugged, a debugger interacts with the user and
+turns the stored debug information into source-language specific information. 
+As such, the debugger must be aware of the source-language, and is thus tied to
+a specific language of family of languages.
      
 
 
 
-
 
 
      
   Debugging optimized code
@@ -195,508 +184,531 @@
 
 
      
 
-
-
      
-  Future work
+
+
      
+  Debugging information format
 
      
+
 
 
      
-
      There are several important extensions that could be eventually added to the
-LLVM debugger.  The most important extension would be to upgrade the LLVM code
-generators to support debugging information.  This would also allow, for
-example, the X86 code generator to emit native objects that contain debugging
-information consumable by traditional source-level debuggers like GDB or
-DBX.
      
 
-
      Additionally, LLVM optimizations can be upgraded to incrementally update the
-debugging information, new commands can be added to the
-debugger, and thread support could be added to the debugger.
      
+
      LLVM debugging information has been carefully designed to make it possible
+for the optimizer to optimize the program and debugging information without
+necessarily having to know anything about debugging information.  In particular,
+the global constant merging pass automatically eliminates duplicated debugging
+information (often caused by header files), the global dead code elimination
+pass automatically deletes debugging information for a function if it decides to
+delete the function, and the linker eliminates debug information when it merges
+linkonce functions.
      
 
-
      The "SourceLanguage" modules provided by llvm-db could be
-substantially improved to provide good support for C++ language features like
-namespaces and scoping rules.
      
+
      To do this, most of the debugging information (descriptors for types,
+variables, functions, source files, etc) is inserted by the language front-end
+in the form of LLVM global variables.  These LLVM global variables are no
+different from any other global variables, except that they have a web of LLVM
+intrinsic functions that point to them.  If the last references to a particular
+piece of debugging information are deleted (for example, by the
+-globaldce pass), the extraneous debug information will automatically
+become dead and be removed by the optimizer.
      
+
+
      Debug information is designed to be agnostic about the target debugger and
+debugging information representation (e.g. DWARF/Stabs/etc).  It uses a generic
+machine debug information pass to decode the information that represents
+variables, types, functions, namespaces, etc: this allows for arbitrary
+source-language semantics and type-systems to be used, as long as there is a
+module written for the target debugger to interpret the information. In
+addition, debug global variables are declared in the "llvm.metadata"
+section.  All values declared in this section are stripped away after target
+debug information is constructed and before the program object is emitted.
      
 
-
      After working with the debugger for a while, perhaps the nicest improvement
-would be to add some sort of line editor, such as GNU readline (but one that is
-compatible with the LLVM license).
      
+
      To provide basic functionality, the LLVM debugger does have to make some
+assumptions about the source-level language being debugged, though it keeps
+these to a minimum.  The only common features that the LLVM debugger assumes
+exist are source files, and program objects.  These abstract objects are
+used by the debugger to form stack traces, show information about local
+variables, etc.
      
 
-
      For someone so inclined, it should be straight-forward to write different
-front-ends for the LLVM debugger, as the LLVM debugging engine is cleanly
-separated from the llvm-db front-end.  A new LLVM GUI debugger or IDE
-would be nice.
      
+
      This section of the documentation first describes the representation aspects
+common to any source-language.  The next section
+describes the data layout conventions used by the C and C++ front-ends.
      
 
 
      
 
-
-
      
-  Using the llvm-db tool
+
+
      
+  Debug information descriptors
 
      
-
 
 
      
+
      In consideration of the complexity and volume of debug information, LLVM
+provides a specification for well formed debug global variables.  The constant
+value of each of these globals is one of a limited set of structures, known as
+debug descriptors.
      
+
+
      Consumers of LLVM debug information expect the descriptors for program
+objects to start in a canonical format, but the descriptors can include
+additional information appended at the end that is source-language specific. 
+All LLVM debugging information is versioned, allowing backwards compatibility in
+the case that the core structures need to change in some way.  Also, all
+debugging information objects start with a tag to indicate what type of object
+it is.  The source-language is allowed to define its own objects, by using
+unreserved tag numbers.
      
+
+
      The fields of debug descriptors used internally by LLVM (MachineDebugInfo)
+are restricted to only the simple data types int, uint,
+bool, float, double, sbyte* and  { }*
+.  References to arbitrary values are handled using a  { }*  and a
+cast to  { }*  expression; typically references to other field
+descriptors, arrays of descriptors or global variables.
      
+
+
      +  %llvm.dbg.object.type = type {
+    uint,   ;; A tag
+    ...
+  }
+
      
 
-
      The llvm-db tool provides a GDB-like interface for source-level
-debugging of programs.  This tool provides many standard commands for inspecting
-and modifying the program as it executes, loading new programs, single stepping,
-placing breakpoints, etc.  This section describes how to use the debugger.
      
-
-
      llvm-db has been designed to be as similar to GDB in its user
-interface as possible.  This should make it extremely easy to learn
-llvm-db if you already know GDB.  In general, llvm-db
-provides the subset of GDB commands that are applicable to LLVM debugging users.
-If there is a command missing that make a reasonable amount of sense within the
-limitations of llvm-db, please report it as
-a bug or, better yet, submit a patch to add it.
      
+
      The first field of a descriptor is always an uint containing a tag
+value identifying the content of the descriptor. The remaining fields are
+specific to the descriptor.  The values of tags are loosely bound to the tag
+values of Dwarf information entries.  However, that does not restrict the use of
+the information supplied to Dwarf targets.
      
+
+
      The details of the various descriptors follow.
      
 
 
      
 
 
-
      
-  Limitations of llvm-db
+
      
+  Anchor descriptors
 
      
 
 
      
 
-
      llvm-db is designed to be modular and easy to extend.  This
-extensibility was key to getting the debugger up-and-running quickly, because we
-can start with simple-but-unsophisicated implementations of various components.
-Because of this, it is currently missing many features, though they should be
-easy to add over time (patches welcomed!).  The biggest inherent limitations of
-llvm-db are currently due to extremely simple debugger backend (implemented in
-"lib/Debugger/UnixLocalInferiorProcess.cpp") which is designed to work without
-any cooperation from the code generators.  Because it is so simple, it suffers
-from the following inherent limitations:
      
+
      +  %llvm.dbg.anchor.type = type {
+    uint,   ;; Tag = 0
+    uint    ;; Tag of descriptors grouped by the anchor
+  }
+
      
 
-
        
+
        One important aspect of the LLVM debug representation is that it allows the
+LLVM debugger to efficiently index all of the global objects without having the
+scan the program.  To do this, all of the global objects use "anchor"
+descriptors with designated names.  All of the global objects of a particular
+type (e.g., compile units) contain a pointer to the anchor.  This pointer allows
+the debugger to use def-use chains to find all global objects of that type.
        
 
-
      • Running a program in llvm-db is a bit slower than running it with
-lli (i.e., in the JIT).
        • 
+
        The following names are recognized as anchors by LLVM:
        
 
-
      • Inspection of the target hardware is not supported.  This means that you
-cannot, for example, print the contents of X86 registers.
        • 
+
        +  %llvm.dbg.compile_units       = linkonce constant %llvm.dbg.anchor.type  { uint 0, uint 17 } ;; DW_TAG_compile_unit
+  %llvm.dbg.global_variables    = linkonce constant %llvm.dbg.anchor.type  { uint 0, uint 52 } ;; DW_TAG_variable
+  %llvm.dbg.subprograms         = linkonce constant %llvm.dbg.anchor.type  { uint 0, uint 46 } ;; DW_TAG_subprogram
+
        
 
-
      • Inspection of LLVM code is not supported.  This means that you cannot print
-the contents of arbitrary LLVM values, or use commands such as stepi.
-This also means that you cannot debug code without debug information.
        • 
-
-
      • Portions of the debugger run in the same address space as the program being
-debugged.  This means that memory corruption by the program could trample on
-portions of the debugger.
        • 
+
        Using anchors in this way (where the compile unit descriptor points to the
+anchors, as opposed to having a list of compile unit descriptors) allows for the
+standard dead global elimination and merging passes to automatically remove
+unused debugging information.  If the globals were kept track of through lists,
+there would always be an object pointing to the descriptors, thus would never be
+deleted.
        
 
-
      • Attaching to existing processes and core files is not currently
-supported.
        • 
+
      
 
-
+
+
      
+  Compile unit descriptors
+
      
 
-
      That said, the debugger is still quite useful, and all of these limitations
-can be eliminated by integrating support for the debugger into the code
-generators, and writing a new InferiorProcess
-subclass to use it.  See the future work section for ideas
-of how to extend the LLVM debugger despite these limitations.
      
+
      
 
-
      
+
      +  %llvm.dbg.compile_unit.type = type {
+    uint,   ;; Tag = 17 (DW_TAG_compile_unit)
+    {  }*,  ;; Compile unit anchor = cast = (%llvm.dbg.anchor.type* %llvm.dbg.compile_units to {  }*)
+    uint,   ;; LLVM debug version number = 1
+    uint,   ;; Dwarf language identifier (ex. DW_LANG_C89) 
+    sbyte*, ;; Source file name
+    sbyte*, ;; Source file directory (includes trailing slash)
+    sbyte*  ;; Producer (ex. "4.0.1 LLVM (LLVM research group)")
+  }
+
      
 
+
      These descriptors contain the version number for the debug info (currently
+1), a source language ID for the file (we use the Dwarf 3.0 ID numbers, such as
+DW_LANG_C89, DW_LANG_C_plus_plus, DW_LANG_Cobol74,
+etc), three strings describing the filename, working directory of the compiler,
+and an identifier string for the compiler that produced it.
      
+
+
       Compile unit descriptors provide the root context for objects declared in a
+specific source file.  Global variables and top level functions would be defined
+using this context.  Compile unit descriptors also provide context for source
+line correspondence.
        
+
+
      
 
 
-
      
-  A sample llvm-db session
+
      
+  Global variable descriptors
 
      
 
 
      
 
-
      TODO: this is obviously lame, when more is implemented, this can be much
-better.
      
-
 
      -$ llvm-db funccall
-llvm-db: The LLVM source-level debugger
-Loading program... successfully loaded 'funccall.bc'!
-(llvm-db) create
-Starting program: funccall.bc
-main at funccall.c:9:2
-9 ->            q = 0;
-(llvm-db) list main
-4       void foo() {
-5               int t = q;
-6               q = t + 1;
-7       }
-8       int main() {
-9 ->            q = 0;
-10              foo();
-11              q = q - 1;
-12
-13              return q;
-(llvm-db) list
-14      }
-(llvm-db) step
-10 ->           foo();
-(llvm-db) s
-foo at funccall.c:5:2
-5 ->            int t = q;
-(llvm-db) bt
-#0 ->   0x85ffba0 in foo at funccall.c:5:2
-#1      0x85ffd98 in main at funccall.c:10:2
-(llvm-db) finish
-main at funccall.c:11:2
-11 ->           q = q - 1;
-(llvm-db) s
-13 ->           return q;
-(llvm-db) s
-The program stopped with exit code 0
-(llvm-db) quit
-$
+  %llvm.dbg.global_variable.type = type {
+    uint,   ;; Tag = 52 (DW_TAG_variable)
+    {  }*,  ;; Global variable anchor = cast (%llvm.dbg.anchor.type* %llvm.dbg.global_variables to {  }*),  
+    {  }*,  ;; Reference to compile unit
+    sbyte*, ;; Name
+    {  }*,  ;; Reference to type descriptor
+    bool,   ;; True if the global is local to compile unit (static)
+    bool,   ;; True if the global is defined in the compile unit (not extern)
+    {  }*,  ;; Reference to the global variable
+    uint    ;; Line number in compile unit where variable is defined
+  }
 
      
 
+
      These descriptors provide debug information about globals variables.  The
+provide details such as name, type and where the variable is defined.
      
+
+
      
+
+
+
      
+  Subprogram descriptors
 
      
 
+
      
+
+
      +  %llvm.dbg.subprogram.type = type {
+    uint,   ;; Tag = 46 (DW_TAG_subprogram)
+    {  }*,  ;; Subprogram anchor = cast (%llvm.dbg.anchor.type* %llvm.dbg.subprograms to {  }*),  
+    {  }*,  ;; Reference to compile unit
+    sbyte*, ;; Name
+    {  }*,  ;; Reference to type descriptor
+    bool,   ;; True if the global is local to compile unit (static)
+    bool    ;; True if the global is defined in the compile unit (not extern)
+    TODO - MORE TO COME
+  }
+
+
      
+
+
      These descriptors provide debug information about functions, methods and
+subprograms.  The provide details such as name, return and argument types and
+where the subprogram is defined.
      
 
+
      
 
 
-
      
-  Starting the debugger
+
      
+  Basic type descriptors
 
      
 
 
      
 
-
      There are three ways to start up the llvm-db debugger:
      
+
      +  %llvm.dbg.basictype.type = type {
+    uint,   ;; Tag = 36 (DW_TAG_base_type)
+    {  }*,  ;; Reference to context (typically a compile unit)
+    sbyte*, ;; Name (may be "" for anonymous types)
+    {  }*,  ;; Reference to compile unit where defined (may be NULL)
+    int,    ;; Line number where defined (may be 0)
+    uint,   ;; Size in bits
+    uint,   ;; Alignment in bits
+    uint,   ;; Offset in bits
+    uint    ;; Dwarf type encoding
+  }
+
      
 
-
      When run with no options, just llvm-db, the debugger starts up
-without a program loaded at all.  You must use the file command to load a program, and the set args or run
-commands to specify the arguments for the program.
      
+
      These descriptors define primitive types used in the code. Example int, bool
+and float.  The context provides the scope of the type, which is usually the top
+level.  Since basic types are not usually user defined the compile unit and line
+number can be left as NULL and 0.  The size, alignment and offset are expressed
+in bits and can be 64 bit values.  The alignment is used to round the offset
+when embedded in a composite type
+(example to keep float doubles on 64 bit boundaries.) The offset is the bit
+offset if embedded in a composite
+type.
      
 
-
      If you start the debugger with one argument, as llvm-db
-<program>, the debugger will start up and load in the specified
-program.  You can then optionally specify arguments to the program with the set args or run
-commands.
      
+
      The type encoding provides the details of the type.  The values are typically
+one of the following;
      
 
-
      The third way to start the program is with the --args option.  This
-option allows you to specify the program to load and the arguments to start out
-with.   Example use: llvm-db --args ls /home
      
+
      +  DW_ATE_address = 1
+  DW_ATE_boolean = 2
+  DW_ATE_float = 4
+  DW_ATE_signed = 5
+  DW_ATE_signed_char = 6
+  DW_ATE_unsigned = 7
+  DW_ATE_unsigned_char = 8
+
      
 
 
      
 
 
-
      
-  Commands recognized by the debugger
+
      
+  Derived type descriptors
 
      
 
 
      
 
-
      FIXME: this needs work obviously.  See the GDB documentation for
-information about what these do, or try 'help [command]' within
-llvm-db to get information.
      
+
      +  %llvm.dbg.derivedtype.type = type {
+    uint,   ;; Tag (see below)
+    {  }*,  ;; Reference to context
+    sbyte*, ;; Name (may be "" for anonymous types)
+    {  }*,  ;; Reference to compile unit where defined (may be NULL)
+    int,    ;; Line number where defined (may be 0)
+    uint,   ;; Size in bits
+    uint,   ;; Alignment in bits
+    uint,   ;; Offset in bits
+    {  }*   ;; Reference to type derived from
+  }
+
      
 
-
      
-
      General usage:
      
-
        
-
      • help [command]
        • 
-
      • quit
        • 
-
      • file [program]
        • 
-
      
+
      These descriptors are used to define types derived from other types.  The
+value of the tag varies depending on the meaning.  The following are possible
+tag values;
      
 
-
      Program inspection and interaction:
      
-
        
-
      • create (start the program, stopping it ASAP in main)
        • 
-
      • kill
        • 
-
      • run [args]
        • 
-
      • step [num]
        • 
-
      • next [num]
        • 
-
      • cont
        • 
-
      • finish
        • 
-
-
      • list [start[, end]]
        • 
-
      • info source
        • 
-
      • info sources
        • 
-
      • info functions
        • 
-
      
+
      +  DW_TAG_member = 13
+  DW_TAG_pointer_type = 15
+  DW_TAG_reference_type = 16
+  DW_TAG_typedef = 22
+  DW_TAG_const_type = 38
+  DW_TAG_volatile_type = 53
+  DW_TAG_restrict_type = 55
+
      
 
-
      Call stack inspection:
      
-
        
-
      • backtrace
        • 
-
      • up [n]
        • 
-
      • down [n]
        • 
-
      • frame [n]
        • 
-
      
+
       DW_TAG_member is used to define a member of a composite type.  The type of the member is the
+derived type.
      
+
+
      DW_TAG_typedef is used to
+provide a name for the derived type.
      
+
+
      DW_TAG_pointer_type,
+DW_TAG_reference_type, DW_TAG_const_type,
+DW_TAG_volatile_type and DW_TAG_restrict_type are used to
+qualify the derived type. 
      
+
+
      Derived type location can be determined
+from the compile unit and line number.  The size, alignment and offset are
+expressed in bits and can be 64 bit values.  The alignment is used to round the
+offset when embedded in a composite type
+(example to keep float doubles on 64 bit boundaries.) The offset is the bit
+offset if embedded in a composite
+type.
      
+
+
      Note that the void * type is expressed as a
+llvm.dbg.derivedtype.type with tag of DW_TAG_pointer_type and
+NULL derived type.
      
 
+
      
 
-
      Debugger inspection and interaction:
      
-
        
-
      • info target
        • 
-
      • show prompt
        • 
-
      • set prompt
        • 
-
      • show listsize
        • 
-
      • set listsize
        • 
-
      • show language
        • 
-
      • set language
        • 
-
      • show args
        • 
-
      • set args [args]
        • 
-
      
+
+
      
+  Composite type descriptors
+
      
 
-
      TODO:
      
-
        
-
      • info frame
        • 
-
      • break
        • 
-
      • print
        • 
-
      • ptype
        • 
-
-
      • info types
        • 
-
      • info variables
        • 
-
      • info program
        • 
-
-
      • info args
        • 
-
      • info locals
        • 
-
      • info catch
        • 
-
      • ... many others
        • 
-
      
+
      
+
+
      +  %llvm.dbg.compositetype.type = type {
+    uint,   ;; Tag (see below)
+    {  }*,  ;; Reference to context
+    sbyte*, ;; Name (may be "" for anonymous types)
+    {  }*,  ;; Reference to compile unit where defined (may be NULL)
+    int,    ;; Line number where defined (may be 0)
+    uint,   ;; Size in bits
+    uint,   ;; Alignment in bits
+    uint,   ;; Offset in bits
+    {  }*   ;; Reference to array of member descriptors
+  }
+
      
+
+
      These descriptors are used to define types that are composed of 0 or more
+elements.  The value of the tag varies depending on the meaning.  The following
+are possible tag values;
      
+
+
      +  DW_TAG_array_type = 1
+  DW_TAG_enumeration_type = 4
+  DW_TAG_structure_type = 19
+  DW_TAG_union_type = 23
+
      
+
+
      The members of array types (tag = DW_TAG_array_type) are subrange descriptors, each representing the range of
+subscripts at that level of indexing.
      
+
+
      The members of enumeration types (tag = DW_TAG_enumeration_type) are
+enumerator descriptors, each representing the
+definition of enumeration value
+for the set.
      
+
+
      The members of structure (tag = DW_TAG_structure_type) or union (tag
+= DW_TAG_union_type) types are any one of the basic, derived
+or composite type descriptors, each
+representing a field member of the structure or union.
      
+
+
      Composite type location can be
+determined from the compile unit and line number.  The size, alignment and
+offset are expressed in bits and can be 64 bit values.  The alignment is used to
+round the offset when embedded in a composite
+type (as an example, to keep float doubles on 64 bit boundaries.) The offset
+is the bit offset if embedded in a composite
+type.
      
 
 
      
 
-
-
      
-  Architecture of the LLVM debugger
+
+
      
+  Subrange descriptors
 
      
-
 
 
      
-
      The LLVM debugger is built out of three distinct layers of software.  These
-layers provide clients with different interface options depending on what pieces
-of they want to implement themselves, and it also promotes code modularity and
-good design.  The three layers are the Debugger
-interface, the "info" interfaces, and the llvm-db tool itself.
      
+
+
      +  %llvm.dbg.subrange.type = type {
+    uint,   ;; Tag = 33 (DW_TAG_subrange_type)
+    uint,   ;; Low value
+    uint    ;; High value
+  }
+
      
+
+
      These descriptors are used to define ranges of array subscripts for an array
+composite type.  The low value defines the
+lower bounds typically zero for C/C++.  The high value is the upper bounds. 
+Values are 64 bit.  High - low + 1 is the size of the array.  If
+low == high the array will be unbounded.
      
+
 
      
 
 
-
      
-  The Debugger and InferiorProcess classes
+
      
+  Enumerator descriptors
 
      
 
 
      
-
      The Debugger class (defined in the include/llvm/Debugger/ directory)
-is a low-level class which is used to maintain information about the loaded
-program, as well as start and stop the program running as necessary.  This class
-does not provide any high-level analysis or control over the program, only
-exposing simple interfaces like load/unloadProgram,
-create/killProgram, step/next/finish/contProgram, and
-low-level methods for installing breakpoints.
      
-
-
      
-The Debugger class is itself a wrapper around the lowest-level InferiorProcess
-class.  This class is used to represent an instance of the program running under
-debugger control.  The InferiorProcess class can be implemented in different
-ways for different targets and execution scenarios (e.g., remote debugging).
-The InferiorProcess class exposes a small and simple collection of interfaces
-which are useful for inspecting the current state of the program (such as
-collecting stack trace information, reading the memory image of the process,
-etc).  The interfaces in this class are designed to be as low-level and simple
-as possible, to make it easy to create new instances of the class.
-
      
-
-
      
-The Debugger class exposes the currently active instance of InferiorProcess
-through the Debugger::getRunningProcess method, which returns a
-const reference to the class.  This means that clients of the Debugger
-class can only inspect the running instance of the program directly.  To
-change the executing process in some way, they must use the interces exposed by
-the Debugger class.
-
      
+
+
      +  %llvm.dbg.enumerator.type = type {
+    uint,   ;; Tag = 40 (DW_TAG_enumerator)
+    sbyte*, ;; Name
+    uint    ;; Value
+  }
+
      
+
+
      These descriptors are used to define members of an enumeration composite type, it associates the name to the
+value.
      
+
 
      
 
 
 
      
-  The RuntimeInfo, ProgramInfo, and SourceLanguage classes
+  Debugger intrinsic functions
 
      
 
 
      
-
      
-The next-highest level of debugger abstraction is provided through the
-ProgramInfo, RuntimeInfo, SourceLanguage and related classes (also defined in
-the include/llvm/Debugger/ directory).  These classes efficiently
-decode the debugging information and low-level interfaces exposed by
-InferiorProcess into a higher-level representation, suitable for analysis by the
-debugger.
-
      
-
-
      
-The ProgramInfo class exposes a variety of different kinds of information about
-the program objects in the source-level-language.  The SourceFileInfo class
-represents a source-file in the program (e.g. a .cpp or .h file).  The
-SourceFileInfo class captures information such as which SourceLanguage was used
-to compile the file, where the debugger can get access to the actual file text
-(which is lazily loaded on demand), etc.  The SourceFunctionInfo class
-represents a... FIXME: finish.  The ProgramInfo class provides interfaces
-to lazily find and decode the information needed to create the Source*Info
-classes requested by the debugger.
-
      
-
-
      
-The RuntimeInfo class exposes information about the currently executed program,
-by decoding information from the InferiorProcess and ProgramInfo classes.  It
-provides a StackFrame class which provides an easy-to-use interface for
-inspecting the current and suspended stack frames in the program.
-
      
-
-
      
-The SourceLanguage class is an abstract interface used by the debugger to
-perform all source-language-specific tasks.  For example, this interface is used
-by the ProgramInfo class to decode language-specific types and functions and by
-the debugger front-end (such as llvm-db to
-evaluate source-langauge expressions typed into the debugger.  This class uses
-the RuntimeInfo & ProgramInfo classes to get information about the current
-execution context and the loaded program, respectively.
-
      
+
+
      LLVM uses several intrinsic functions (name prefixed with "llvm.dbg") to
+provide debug information at various points in generated code.
      
 
 
      
 
 
-
      
-  The llvm-db tool
+
      
+  llvm.dbg.stoppoint
 
      
 
 
      
-
      
-The llvm-db is designed to be a debugger providing an interface as similar to GDB as reasonable, but no more so than that.
-Because the Debugger and info classes implement all of the heavy lifting and
-analysis, llvm-db (which lives in llvm/tools/llvm-db) consists
-mainly of of code to interact with the user and parse commands.  The CLIDebugger
-constructor registers all of the builtin commands for the debugger, and each
-command is implemented as a CLIDebugger::[name]Command method.
-
      
-
      
+
      +  void %llvm.dbg.stoppoint( uint, uint, %llvm.dbg.compile_unit* )
+
      
 
+
      This intrinsic is used to provide correspondence between the source file and
+the generated code.  The first argument is the line number (base 1), second
+argument si the column number (0 if unknown) and the third argument the source
+compile unit.  Code following a call to this intrinsic will have been defined in
+close proximity of the line, column and file.  This information holds until the
+next call to lvm.dbg.stoppoint.
      
+
+
      
 
 
-
      
-  Short-term TODO list
+
      
+  llvm.dbg.func.start
 
      
 
 
      
+
      +  void %llvm.dbg.func.start( %llvm.dbg.subprogram.type* )
+
      
 
-
      
-FIXME: this section will eventually go away.  These are notes to myself of
-things that should be implemented, but haven't yet.
-
      
-
-
      
-Breakpoints: Support is already implemented in the 'InferiorProcess'
-class, though it hasn't been tested yet.  To finish breakpoint support, we need
-to implement breakCommand (which should reuse the linespec parser from the list
-command), and handle the fact that 'break foo' or 'break file.c:53' may insert
-multiple breakpoints.  Also, if you say 'break file.c:53' and there is no
-stoppoint on line 53, the breakpoint should go on the next available line.  My
-idea was to have the Debugger class provide a "Breakpoint" class which
-encapsulated this messiness, giving the debugger front-end a simple interface.
-The debugger front-end would have to map the really complex semantics of
-temporary breakpoints and 'conditional' breakpoints onto this intermediate
-level. Also, breakpoints should survive as much as possible across program
-reloads.
-
      
-
-
      
-UnixLocalInferiorProcess.cpp speedup: There is no reason for the debugged
-process to code gen the globals corresponding to debug information.  The
-IntrinsicLowering object could instead change descriptors into constant expr
-casts of the constant address of the LLVM objects for the descriptors.  This
-would also allow us to eliminate the mapping back and forth between physical
-addresses that must be done.
      
-
-
      
-Process deaths: The InferiorProcessDead exception should be extended to
-know "how" a process died, i.e., it was killed by a signal.  This is easy to
-collect in the UnixLocalInferiorProcess, we just need to represent it.
      
+
      This intrinsic is used to link the debug information in %llvm.dbg.subprogram to the function. It also
+defines the beginning of the function's declarative region (scope.)  The
+intrinsic should be called early in the function after the all the alloca
+instructions.
      
 
 
      
 
-
-
      
-  Debugging information format
+
+
      
+  llvm.dbg.region.start
 
      
-
 
 
      
+
      +  void %llvm.dbg.region.start()
+
      
 
-
      LLVM debugging information has been carefully designed to make it possible
-for the optimizer to optimize the program and debugging information without
-necessarily having to know anything about debugging information.  In particular,
-the global constant merging pass automatically eliminates duplicated debugging
-information (often caused by header files), the global dead code elimination
-pass automatically deletes debugging information for a function if it decides to
-delete the function, and the linker eliminates debug information when it merges
-linkonce functions.
      
+
      This intrinsic is used to define the beginning of a declarative scope (ex.
+block) for local language elements.  It should be paired off with a closing
+%llvm.dbg.region.end.
      
 
-
      To do this, most of the debugging information (descriptors for types,
-variables, functions, source files, etc) is inserted by the language front-end
-in the form of LLVM global variables.  These LLVM global variables are no
-different from any other global variables, except that they have a web of LLVM
-intrinsic functions that point to them.  If the last references to a particular
-piece of debugging information are deleted (for example, by the
--globaldce pass), the extraneous debug information will automatically
-become dead and be removed by the optimizer.
      
+
      
 
-
      The debugger is designed to be agnostic about the contents of most of the
-debugging information.  It uses a source-language-specific
-module to decode the information that represents variables, types,
-functions, namespaces, etc: this allows for arbitrary source-language semantics
-and type-systems to be used, as long as there is a module written for the
-debugger to interpret the information.
      
+
+
      
+  llvm.dbg.region.end
+
      
 
-
      To provide basic functionality, the LLVM debugger does have to make some
-assumptions about the source-level language being debugged, though it keeps
-these to a minimum.  The only common features that the LLVM debugger assumes
-exist are source files, and program objects.  These abstract objects are
-used by the debugger to form stack traces, show information about local
-variables, etc.
      
+
      
+
      +  void %llvm.dbg.region.end()
+
      
 
-
      This section of the documentation first describes the representation aspects
-common to any source-language.  The next section
-describes the data layout conventions used by the C and C++ front-ends.
      
+
      This intrinsic is used to define the end of a declarative scope (ex. block)
+for local language elements.  It should be paired off with an opening %llvm.dbg.region.start or %llvm.dbg.func.start.
      
 
 
      
 
 
-
      
-  Anchors for global objects
+
      
+  llvm.dbg.declare
 
      
 
 
      
-
      One important aspect of the LLVM debug representation is that it allows the
-LLVM debugger to efficiently index all of the global objects without having the
-scan the program.  To do this, all of the global objects use "anchor" globals of
-type "{}", with designated names.  These anchor objects obviously do
-not contain any content or meaning by themselves, but all of the global objects
-of a particular type (e.g., source file descriptors) contain a pointer to the
-anchor.  This pointer allows the debugger to use def-use chains to find all
-global objects of that type.
      
-
-
      So far, the following names are recognized as anchors by the LLVM
-debugger:
      
-
 
      -  %llvm.dbg.translation_units = linkonce global {} {}
-  %llvm.dbg.globals         = linkonce global {} {}
+  void %llvm.dbg.declare( {} *, ... )
 
      
 
-
      Using anchors in this way (where the source file descriptor points to the
-anchors, as opposed to having a list of source file descriptors) allows for the
-standard dead global elimination and merging passes to automatically remove
-unused debugging information.  If the globals were kept track of through lists,
-there would always be an object pointing to the descriptors, thus would never be
-deleted.
      
+
      This intrinsic provides information about a local element (ex. variable.) 
+TODO - details.
      
 
 
      
 
 
 
      
-  
+  
      Representing stopping points in the source program
   
 
      
@@ -706,13 +718,14 @@
 
      LLVM debugger "stop points" are a key part of the debugging representation
 that allows the LLVM to maintain simple semantics for debugging optimized code.  The basic idea is that the
-front-end inserts calls to the %llvm.dbg.stoppoint intrinsic function
-at every point in the program where the debugger should be able to inspect the
-program (these correspond to places the debugger stops when you "step"
-through it).  The front-end can choose to place these as fine-grained as it
-would like (for example, before every subexpression evaluated), but it is
-recommended to only put them after every source statement that includes
-executable code.
      
+front-end inserts calls to the %llvm.dbg.stoppoint intrinsic
+function at every point in the program where the debugger should be able to
+inspect the program (these correspond to places the debugger stops when you
+"step" through it).  The front-end can choose to place these as
+fine-grained as it would like (for example, before every subexpression
+evaluated), but it is recommended to only put them after every source statement
+that includes executable code.
      
 
 
      Using calls to this intrinsic function to demark legal points for the
 debugger to inspect the program automatically disables any optimizations that
@@ -724,12 +737,6 @@
 optimization of subexpressions, code duplication transformations, or basic-block
 reordering transformations.
      
 
-
      An important aspect of the calls to the %llvm.dbg.stoppoint
-intrinsic is that the function-local debugging information is woven together
-with use-def chains.  This makes it easy for the debugger to, for example,
-locate the 'next' stop point.  For a concrete example of stop points, see the
-example in the next section.
      
-
 
      
 
 
@@ -764,54 +771,67 @@
 9.  }
-

Compiled to LLVM, this function would be represented like this (FIXME: CHECK -AND UPDATE THIS):

+

Compiled to LLVM, this function would be represented like this:

 void %foo() {
+entry:
     %X = alloca int
     %Y = alloca int
     %Z = alloca int
-    %D1 = call {}* %llvm.dbg.func.start(%lldb.global* %d.foo)
-    %D2 = call {}* %llvm.dbg.stoppoint({}* %D1, uint 2, uint 2, %lldb.compile_unit* %file)
-
-    %D3 = call {}* %llvm.dbg.DEFINEVARIABLE({}* %D2, ...)
+    
+    ...
+    
+    call void %llvm.dbg.func.start( %llvm.dbg.subprogram.type* %llvm.dbg.subprogram )
+    
+    call void %llvm.dbg.stoppoint( uint 2, uint 2, %llvm.dbg.compile_unit* %llvm.dbg.compile_unit )
+    
+    call void %llvm.dbg.declare({}* %X, ...)
+    call void %llvm.dbg.declare({}* %Y, ...)
+    
     ;; Evaluate expression on line 2, assigning to X.
-    %D4 = call {}* %llvm.dbg.stoppoint({}* %D3, uint 3, uint 2, %lldb.compile_unit* %file)
-
-    %D5 = call {}* %llvm.dbg.DEFINEVARIABLE({}* %D4, ...)
+    
+    call void %llvm.dbg.stoppoint( uint 3, uint 2, %llvm.dbg.compile_unit* %llvm.dbg.compile_unit )
+    
     ;; Evaluate expression on line 3, assigning to Y.
-    %D6 = call {}* %llvm.dbg.stoppoint({}* %D5, uint 5, uint 4, %lldb.compile_unit* %file)
-
-    %D7 = call {}* %llvm.region.start({}* %D6)
-    %D8 = call {}* %llvm.dbg.DEFINEVARIABLE({}* %D7, ...)
+    
+    call void %llvm.region.start()
+    call void %llvm.dbg.stoppoint( uint 5, uint 4, %llvm.dbg.compile_unit* %llvm.dbg.compile_unit )
+    call void %llvm.dbg.declare({}* %X, ...)
+    
     ;; Evaluate expression on line 5, assigning to Z.
-    %D9 = call {}* %llvm.dbg.stoppoint({}* %D8, uint 6, uint 4, %lldb.compile_unit* %file)
-
-    ;; Code for line 6.
-    %D10 = call {}* %llvm.region.end({}* %D9)
-    %D11 = call {}* %llvm.dbg.stoppoint({}* %D10, uint 8, uint 2, %lldb.compile_unit* %file)
-
-    ;; Code for line 8.
-    %D12 = call {}* %llvm.region.end({}* %D11)
+    
+    call void %llvm.dbg.stoppoint( uint 7, uint 2, %llvm.dbg.compile_unit* %llvm.dbg.compile_unit )
+    call void %llvm.region.end()
+    
+    call void %llvm.dbg.stoppoint( uint 9, uint 2, %llvm.dbg.compile_unit* %llvm.dbg.compile_unit )
+    
+    call void %llvm.region.end()
+    
     ret void
 }

This example illustrates a few important details about the LLVM debugging -information. In particular, it shows how the various intrinsics used are woven -together with def-use and use-def chains, similar to how anchors are used with globals. This allows -the debugger to analyze the relationship between statements, variable -definitions, and the code used to implement the function.

- -

In this example, two explicit regions are defined, one with the definition of the %D1 variable and one with the -definition of %D7. In the case of -%D1, the debug information indicates that the function whose descriptor is specified as an argument to the -intrinsic. This defines a new stack frame whose lifetime ends when the region -is ended by the %D12 call.

+information. In particular, it shows how the various intrinsics are applied +together to allow a debugger to analyze the relationship between statements, +variable definitions, and the code used to implement the function.

+ +

The first intrinsic %llvm.dbg.func.start provides +a link with the subprogram descriptor +containing the details of this function. This call also defines the beginning +of the function region, bounded by the %llvm.region.end at the end of +the function. This region is used to bracket the lifetime of variables declared +within. For a function, this outer region defines a new stack frame whose +lifetime ends when the region is ended.

+ +

It is possible to define inner regions for short term variables by using the +%llvm.region.start and %llvm.region.end to bound a +region. The inner region in this example would be for the block containing the +declaration of Z.

Using regions to represent the boundaries of source-level functions allow LLVM interprocedural optimizations to arbitrarily modify LLVM functions without @@ -824,280 +844,790 @@ inlined function from the debugger).

Once the function has been defined, the stopping point corresponding to line #2 of -the function is encountered. At this point in the function, no local -variables are live. As lines 2 and 3 of the example are executed, their -variable definitions are automatically introduced into the program, without the +href="#format_common_stoppoint">stopping point corresponding to +line #2 (column #2) of the function is encountered. At this point in the +function, no local variables are live. As lines 2 and 3 of the example +are executed, their variable definitions are introduced into the program using +%llvm.dbg.declare, without the need to specify a new region. These variables do not require new regions to be introduced because they go out of scope at the same point in the program: line 9.

In contrast, the Z variable goes out of scope at a different time, -on line 7. For this reason, it is defined within the -%D7 region, which kills the availability of Z before the -code for line 8 is executed. In this way, regions can support arbitrary -source-language scoping rules, as long as they can only be nested (ie, one scope -cannot partially overlap with a part of another scope).

+on line 7. For this reason, it is defined within the inner region, which kills +the availability of Z before the code for line 8 is executed. In this +way, regions can support arbitrary source-language scoping rules, as long as +they can only be nested (ie, one scope cannot partially overlap with a part of +another scope).

It is worth noting that this scoping mechanism is used to control scoping of all declarations, not just variable declarations. For example, the scope of a -C++ using declaration is controlled with this, and the llvm-db C++ -support routines could use this to change how name lookup is performed (though -this is not implemented yet).

+C++ using declaration is controlled with this couldchange how name lookup is +performed.

+ + + + + + +
+ C/C++ front-end specific debug information +
+ + +
+ +

The C and C++ front-ends represent information about the program in a format +that is effectively identical to Dwarf 3.0 in terms of +information content. This allows code generators to trivially support native +debuggers by generating standard dwarf information, and contains enough +information for non-dwarf targets to translate it as needed.

+ +

This section describes the forms used to represent C and C++ programs. Other +languages could pattern themselves after this (which itself is tuned to +representing programs in the same way that Dwarf 3 does), or they could choose +to provide completely different forms if they don't fit into the Dwarf model. +As support for debugging information gets added to the various LLVM +source-language front-ends, the information used should be documented here.

+ +

The following sections provide examples of various C/C++ constructs and the +debug information that would best describe those constructs.

- Object descriptor formats + C/C++ source file information
-

The LLVM debugger expects the descriptors for program objects to start in a -canonical format, but the descriptors can include additional information -appended at the end that is source-language specific. All LLVM debugging -information is versioned, allowing backwards compatibility in the case that the -core structures need to change in some way. Also, all debugging information -objects start with a tag to indicate what type -of object it is. The source-language is allows to define its own objects, by -using unreserved tag numbers.

-

The lowest-level descriptor are those describing the files containing the program source -code, as most other descriptors (sometimes indirectly) refer to them. -

+

Given the source files "MySource.cpp" and "MyHeader.h" located in the +directory "/Users/mine/sources", the following code;

+ +
+#include "MyHeader.h"
+
+int main(int argc, char *argv[]) {
+  return 0;
+}
+
+ +

a C/C++ front-end would generate the following descriptors;

+ +
+...
+;;
+;; Define types used.  In this case we need one for compile unit anchors and one
+;; for compile units.
+;;
+%llvm.dbg.anchor.type = type { uint, uint }
+%llvm.dbg.compile_unit.type = type { uint, {  }*, uint, uint, sbyte*, sbyte*, sbyte* }
+...
+;;
+;; Define the anchor for compile units.  Note that the second field of the
+;; anchor is 17, which is the same as the tag for compile units
+;; (17 = DW_TAG_compile_unit.)
+;;
+%llvm.dbg.compile_units = linkonce constant %llvm.dbg.anchor.type { uint 0, uint 17 }, section "llvm.metadata"
+
+;;
+;; Define the compile unit for the source file "/Users/mine/sources/MySource.cpp".
+;;
+%llvm.dbg.compile_unit1 = internal constant %llvm.dbg.compile_unit.type {
+    uint 17, 
+    {  }* cast (%llvm.dbg.anchor.type* %llvm.dbg.compile_units to {  }*), 
+    uint 1, 
+    uint 1, 
+    sbyte* getelementptr ([13 x sbyte]* %str1, int 0, int 0), 
+    sbyte* getelementptr ([21 x sbyte]* %str2, int 0, int 0), 
+    sbyte* getelementptr ([33 x sbyte]* %str3, int 0, int 0) }, section "llvm.metadata"
+    
+;;
+;; Define the compile unit for the header file "/Users/mine/sources/MyHeader.h".
+;;
+%llvm.dbg.compile_unit2 = internal constant %llvm.dbg.compile_unit.type {
+    uint 17, 
+    {  }* cast (%llvm.dbg.anchor.type* %llvm.dbg.compile_units to {  }*), 
+    uint 1, 
+    uint 1, 
+    sbyte* getelementptr ([11 x sbyte]* %str4, int 0, int 0), 
+    sbyte* getelementptr ([21 x sbyte]* %str2, int 0, int 0), 
+    sbyte* getelementptr ([33 x sbyte]* %str3, int 0, int 0) }, section "llvm.metadata"
+
+;;
+;; Define each of the strings used in the compile units.
+;;
+%str1 = internal constant [13 x sbyte] c"MySource.cpp\00", section "llvm.metadata";
+%str2 = internal constant [21 x sbyte] c"/Users/mine/sources/\00", section "llvm.metadata";
+%str3 = internal constant [33 x sbyte] c"4.0.1 LLVM (LLVM research group)\00", section "llvm.metadata";
+%str4 = internal constant [11 x sbyte] c"MyHeader.h\00", section "llvm.metadata";
+...
+
+
+ +
+ C/C++ global variable information +
- +
+ C/C++ function information
-

-Source file descriptors are patterned after the Dwarf "compile_unit" object. -The descriptor currently is defined to have at least the following LLVM -type entries:

+ +

Given a function declared as follows;

-%lldb.compile_unit = type {
-       uint,                 ;; Tag: LLVM_COMPILE_UNIT
-       ushort,               ;; LLVM debug version number
-       ushort,               ;; Dwarf language identifier
-       sbyte*,               ;; Filename
-       sbyte*,               ;; Working directory when compiled
-       sbyte*                ;; Producer of the debug information
+int main(int argc, char *argv[]) {
+  return 0;
 }
-

-These descriptors contain the version number for the debug info, a source -language ID for the file (we use the Dwarf 3.0 ID numbers, such as -DW_LANG_C89, DW_LANG_C_plus_plus, DW_LANG_Cobol74, -etc), three strings describing the filename, working directory of the compiler, -and an identifier string for the compiler that produced it. Note that actual -compile_unit declarations must also include an anchor to llvm.dbg.translation_units, -but it is not specified where the anchor is to be located. Here is an example -descriptor: -

- -

-%arraytest_source_file = internal constant %lldb.compile_unit {
-    uint 17,                                                      ; Tag value
-    ushort 0,                                                     ; Version #0
-    ushort 1,                                                     ; DW_LANG_C89
-    sbyte* getelementptr ([12 x sbyte]* %.str_1, long 0, long 0), ; filename
-    sbyte* getelementptr ([12 x sbyte]* %.str_2, long 0, long 0), ; working dir
-    sbyte* getelementptr ([12 x sbyte]* %.str_3, long 0, long 0), ; producer
-    {}* %llvm.dbg.translation_units                               ; Anchor
+
a C/C++ front-end would generate the following descriptors;

+
+
+;;
+;; Define types used. One for subprogram anchors, one for the subprogram
+;; descriptor, one for the global's basic type and one for the subprogram's
+;; compile unit.
+;;
+%llvm.dbg.subprogram.type = type { uint, {  }*, {  }*, sbyte*, {  }*, bool, bool }
+%llvm.dbg.anchor.type = type { uint, uint }
+%llvm.dbg.compile_unit.type = ...
+	
+;;
+;; Define the anchor for subprograms.  Note that the second field of the
+;; anchor is 46, which is the same as the tag for subprograms
+;; (46 = DW_TAG_subprogram.)
+;;
+%llvm.dbg.subprograms = linkonce constant %llvm.dbg.anchor.type { uint 0, uint 46 }, section "llvm.metadata"
+
+;;
+;; Define the descriptor for the subprogram.  TODO - more details.
+;;
+%llvm.dbg.subprogram = internal constant %llvm.dbg.subprogram.type {
+    uint 46, 
+    {  }* cast (%llvm.dbg.anchor.type* %llvm.dbg.subprograms to {  }*), 
+    {  }* cast (%llvm.dbg.compile_unit.type* %llvm.dbg.compile_unit to {  }*), 
+    sbyte* getelementptr ([5 x sbyte]* %str1, int 0, int 0), 
+    {  }* null, 
+    bool false, 
+    bool true }, section "llvm.metadata"
+
+;;
+;; Define the name of the subprogram.
+;;
+%str1 = internal constant [5 x sbyte] c"main\00", section "llvm.metadata"
+
+;;
+;; Define the subprogram itself.
+;;
+int %main(int %argc, sbyte** %argv) {
+...
 }
-%.str_1 = internal constant [12 x sbyte] c"arraytest.c\00"
-%.str_2 = internal constant [12 x sbyte] c"/home/sabre\00"
-%.str_3 = internal constant [12 x sbyte] c"llvmgcc 3.4\00"
-

+
-

-Note that the LLVM constant merging pass should eliminate duplicate copies of -the strings that get emitted to each translation unit, such as the producer. -

+
+ +
+ C/C++ basic types
+
+ +

The following are the basic type descriptors for C/C++ core types;

+ +
- +
- Representation of program objects + bool
-

-The LLVM debugger needs to know about some source-language program objects, in -order to build stack traces, print information about local variables, and other -related activities. The LLVM debugger differentiates between three different -types of program objects: subprograms (functions, messages, methods, etc), -variables (locals and globals), and others. Because source-languages have -widely varying forms of these objects, the LLVM debugger expects only a few -fields in the descriptor for each object: -

-%lldb.object = type {
-       uint,                  ;; A tag
-       any*,                  ;; The context for the object
-       sbyte*                 ;; The object 'name'
-}
+%llvm.dbg.basictype = internal constant %llvm.dbg.basictype.type {
+    uint 36, 
+    {  }* cast (%llvm.dbg.compile_unit.type* %llvm.dbg.compile_unit to {  }*), 
+    sbyte* getelementptr ([5 x sbyte]* %str1, int 0, int 0), 
+    {  }* null, 
+    int 0, 
+    uint 32, 
+    uint 32, 
+    uint 0, 
+    uint 2 }, section "llvm.metadata"
+%str1 = internal constant [5 x sbyte] c"bool\00", section "llvm.metadata"
-

The first field contains a tag for the descriptor. The second field contains -either a pointer to the descriptor for the containing source file, or it contains a pointer to -another program object whose context pointer eventually reaches a source file. -Through this context pointer, the -LLVM debugger can establish the debug version number of the object.

- -

The third field contains a string that the debugger can use to identify the -object if it does not contain explicit support for the source-language in use -(ie, the 'unknown' source language handler uses this string). This should be -some sort of unmangled string that corresponds to the object, but it is a -quality of implementation issue what exactly it contains (it is legal, though -not useful, for all of these strings to be null).

- -

Note again that descriptors can be extended to include -source-language-specific information in addition to the fields required by the -LLVM debugger. See the section on the C/C++ -front-end for more information. Also remember that global objects -(functions, selectors, global variables, etc) must contain an anchor to the llvm.dbg.globals -variable.

- -
- Program object contexts +
+ char
+ 
-Allow source-language specific contexts, use to identify namespaces etc
-Must end up in a source file descriptor.
-Debugger core ignores all unknown context objects.
+%llvm.dbg.basictype = internal constant %llvm.dbg.basictype.type {
+    uint 36, 
+    {  }* cast (%llvm.dbg.compile_unit.type* %llvm.dbg.compile_unit to {  }*), 
+    sbyte* getelementptr ([5 x sbyte]* %str1, int 0, int 0), 
+    {  }* null, 
+    int 0, 
+    uint 8, 
+    uint 8, 
+    uint 0, 
+    uint 6 }, section "llvm.metadata"
+%str1 = internal constant [5 x sbyte] c"char\00", section "llvm.metadata"
+
-
- Debugger intrinsic functions +
+ unsigned char
-
-Define each intrinsics, as an extension of the language reference manual.
 
-llvm.dbg.stoppoint
-llvm.dbg.region.start
-llvm.dbg.region.end
-llvm.dbg.function.start
-llvm.dbg.declare
+
+%llvm.dbg.basictype = internal constant %llvm.dbg.basictype.type {
+    uint 36, 
+    {  }* cast (%llvm.dbg.compile_unit.type* %llvm.dbg.compile_unit to {  }*), 
+    sbyte* getelementptr ([14 x sbyte]* %str1, int 0, int 0), 
+    {  }* null, 
+    int 0, 
+    uint 8, 
+    uint 8, 
+    uint 0, 
+    uint 8 }, section "llvm.metadata"
+%str1 = internal constant [14 x sbyte] c"unsigned char\00", section "llvm.metadata"
 

+
-
- Values for debugger tags +
+ short
-

Happen to be the same value as the similarly named Dwarf-3 tags, this may -change in the future.

+
+%llvm.dbg.basictype = internal constant %llvm.dbg.basictype.type {
+    uint 36, 
+    {  }* cast (%llvm.dbg.compile_unit.type* %llvm.dbg.compile_unit to {  }*), 
+    sbyte* getelementptr ([10 x sbyte]* %str1, int 0, int 0), 
+    {  }* null, 
+    int 0, 
+    uint 16, 
+    uint 16, 
+    uint 0, 
+    uint 5 }, section "llvm.metadata"
+%str1 = internal constant [10 x sbyte] c"short int\00", section "llvm.metadata"
+
+ +
+ + +
+ unsigned short +
+ +
-  LLVM_COMPILE_UNIT     : 17
-  LLVM_SUBPROGRAM       : 46
-  LLVM_VARIABLE         : 52
-
+%llvm.dbg.basictype = internal constant %llvm.dbg.basictype.type {
+    uint 36, 
+    {  }* cast (%llvm.dbg.compile_unit.type* %llvm.dbg.compile_unit to {  }*), 
+    sbyte* getelementptr ([19 x sbyte]* %str1, int 0, int 0), 
+    {  }* null, 
+    int 0, 
+    uint 16, 
+    uint 16, 
+    uint 0, 
+    uint 7 }, section "llvm.metadata"
+%str1 = internal constant [19 x sbyte] c"short unsigned int\00", section "llvm.metadata"
+
+ +
+ int +
+
+ +
+%llvm.dbg.basictype = internal constant %llvm.dbg.basictype.type {
+    uint 36, 
+    {  }* cast (%llvm.dbg.compile_unit.type* %llvm.dbg.compile_unit to {  }*), 
+    sbyte* getelementptr ([4 x sbyte]* %str1, int 0, int 0), 
+    {  }* null, 
+    int 0, 
+    uint 32, 
+    uint 32, 
+    uint 0, 
+    uint 5 }, section "llvm.metadata"
+%str1 = internal constant [4 x sbyte] c"int\00", section "llvm.metadata"
+
- -
- C/C++ front-end specific debug information
- + + +
+ unsigned int +
-

The C and C++ front-ends represent information about the program in a format -that is effectively identical to Dwarf 3.0 in terms of -information content. This allows code generators to trivially support native -debuggers by generating standard dwarf information, and contains enough -information for non-dwarf targets to translate it as needed.

+
+%llvm.dbg.basictype = internal constant %llvm.dbg.basictype.type {
+    uint 36, 
+    {  }* cast (%llvm.dbg.compile_unit.type* %llvm.dbg.compile_unit to {  }*), 
+    sbyte* getelementptr ([13 x sbyte]* %str1, int 0, int 0), 
+    {  }* null, 
+    int 0, 
+    uint 32, 
+    uint 32, 
+    uint 0, 
+    uint 7 }, section "llvm.metadata"
+%str1 = internal constant [13 x sbyte] c"unsigned int\00", section "llvm.metadata"
+
-

The basic debug information required by the debugger is (intentionally) -designed to be as minimal as possible. This basic information is so minimal -that it is unlikely that any source-language could be adequately -described by it. Because of this, the debugger format was designed for -extension to support source-language-specific information. The extended -descriptors are read and interpreted by the language-specific modules in the debugger if there is -support available, otherwise it is ignored.

+
-

This section describes the extensions used to represent C and C++ programs. -Other languages could pattern themselves after this (which itself is tuned to -representing programs in the same way that Dwarf 3 does), or they could choose -to provide completely different extensions if they don't fit into the Dwarf -model. As support for debugging information gets added to the various LLVM -source-language front-ends, the information used should be documented here.

+ +
+ long long +
+ +
+ +
+%llvm.dbg.basictype = internal constant %llvm.dbg.basictype.type {
+    uint 36, 
+    {  }* cast (%llvm.dbg.compile_unit.type* %llvm.dbg.compile_unit to {  }*), 
+    sbyte* getelementptr ([14 x sbyte]* %str1, int 0, int 0), 
+    {  }* null, 
+    int 0, 
+    uint 64, 
+    uint 64, 
+    uint 0, 
+    uint 5 }, section "llvm.metadata"
+%str1 = internal constant [14 x sbyte] c"long long int\00", section "llvm.metadata"
+
-
- Program Scope Entries +
+ unsigned long long
-

TODO

+ +
+%llvm.dbg.basictype = internal constant %llvm.dbg.basictype.type {
+    uint 36, 
+    {  }* cast (%llvm.dbg.compile_unit.type* %llvm.dbg.compile_unit to {  }*), 
+    sbyte* getelementptr ([23 x sbyte]* %str1, int 0, int 0), 
+    {  }* null, 
+    int 0, 
+    uint 64, 
+    uint 64, 
+    uint 0, 
+    uint 7 }, section "llvm.metadata"
+%str1 = internal constant [23 x sbyte] c"long long unsigned int\00", section "llvm.metadata"
+
+
- +
- Compilation unit entries + float
-

-Translation units do not add any information over the standard source file representation already -expected by the debugger. As such, it uses descriptors of the type specified, -with a trailing anchor. -

+ +
+%llvm.dbg.basictype = internal constant %llvm.dbg.basictype.type {
+    uint 36, 
+    {  }* cast (%llvm.dbg.compile_unit.type* %llvm.dbg.compile_unit to {  }*), 
+    sbyte* getelementptr ([6 x sbyte]* %str1, int 0, int 0), 
+    {  }* null, 
+    int 0, 
+    uint 32, 
+    uint 32, 
+    uint 0, 
+    uint 4 }, section "llvm.metadata"
+%str1 = internal constant [6 x sbyte] c"float\00", section "llvm.metadata"
+
+
- +
- Module, namespace, and importing entries + double
-

TODO

+ +
+%llvm.dbg.basictype = internal constant %llvm.dbg.basictype.type {
+    uint 36, 
+    {  }* cast (%llvm.dbg.compile_unit.type* %llvm.dbg.compile_unit to {  }*), 
+    sbyte* getelementptr ([7 x sbyte]* %str1, int 0, int 0), 
+    {  }* null, 
+    int 0, 
+    uint 64, 
+    uint 64, 
+    uint 0, 
+    uint 4 }, section "llvm.metadata"
+%str1 = internal constant [7 x sbyte] c"double\00", section "llvm.metadata"
+
+
- Data objects (program variables) + C/C++ derived types
-

TODO

+ +

Given the following as an example of C/C++ derived type;

+ +
+typedef const int *IntPtr;
+
+ +

a C/C++ front-end would generate the following descriptors;

+ +
+;;
+;; Define the typedef "IntPtr".
+;;
+%llvm.dbg.derivedtype1 = internal constant %llvm.dbg.derivedtype.type {
+    uint 22, 
+    {  }* cast (%llvm.dbg.compile_unit.type* %llvm.dbg.compile_unit to {  }*), 
+    sbyte* getelementptr ([7 x sbyte]* %str1, int 0, int 0), 
+    {  }* cast (%llvm.dbg.compile_unit.type* %llvm.dbg.compile_unit to {  }*), 
+    int 1, 
+    uint 0, 
+    uint 0, 
+    uint 0, 
+    {  }* cast (%llvm.dbg.derivedtype.type* %llvm.dbg.derivedtype2 to {  }*) }, section "llvm.metadata"
+%str1 = internal constant [7 x sbyte] c"IntPtr\00", section "llvm.metadata"
+
+;;
+;; Define the pointer type.
+;;
+%llvm.dbg.derivedtype2 = internal constant %llvm.dbg.derivedtype.type {
+    uint 15, 
+    {  }* cast (%llvm.dbg.compile_unit.type* %llvm.dbg.compile_unit to {  }*), 
+    sbyte* getelementptr ([1 x sbyte]* %str2, int 0, int 0), 
+    {  }* null, 
+    int 0, 
+    uint 32, 
+    uint 32, 
+    uint 0, 
+    {  }* cast (%llvm.dbg.derivedtype.type* %llvm.dbg.derivedtype3 to {  }*) }, section "llvm.metadata"
+%str2 = internal constant [1 x sbyte] zeroinitializer, section "llvm.metadata"
+
+;;
+;; Define the const type.
+;;
+%llvm.dbg.derivedtype3 = internal constant %llvm.dbg.derivedtype.type {
+    uint 38, 
+    {  }* cast (%llvm.dbg.compile_unit.type* %llvm.dbg.compile_unit to {  }*), 
+    sbyte* getelementptr ([1 x sbyte]* %str2, int 0, int 0), 
+    {  }* null, 
+    int 0, 
+    uint 0, 
+    uint 0, 
+    uint 0, 
+    {  }* cast (%llvm.dbg.basictype.type* %llvm.dbg.basictype1 to {  }*) }, section "llvm.metadata"	
+
+;;
+;; Define the int type.
+;;
+%llvm.dbg.basictype1 = internal constant %llvm.dbg.basictype.type {
+    uint 36, 
+    {  }* cast (%llvm.dbg.compile_unit.type* %llvm.dbg.compile_unit to {  }*), 
+    sbyte* getelementptr ([4 x sbyte]* %str4, int 0, int 0), 
+    {  }* null, 
+    int 0, 
+    uint 32, 
+    uint 32, 
+    uint 0, 
+    uint 5 }, section "llvm.metadata"
+%str4 = internal constant [4 x sbyte] c"int\00", section "llvm.metadata"
+
+ +
+ + +
+ C/C++ struct/union types
+
+ +

Given the following as an example of C/C++ struct type;

+ +
+struct Color {
+  unsigned Red;
+  unsigned Green;
+  unsigned Blue;
+};
+
+ +

a C/C++ front-end would generate the following descriptors;

+ +
+;;
+;; Define basic type for unsigned int.
+;;
+%llvm.dbg.basictype = internal constant %llvm.dbg.basictype.type {
+    uint 36, 
+    {  }* cast (%llvm.dbg.compile_unit.type* %llvm.dbg.compile_unit to {  }*), 
+    sbyte* getelementptr ([13 x sbyte]* %str1, int 0, int 0), 
+    {  }* null, 
+    int 0, 
+    uint 32, 
+    uint 32, 
+    uint 0, 
+    uint 7 }, section "llvm.metadata"
+%str1 = internal constant [13 x sbyte] c"unsigned int\00", section "llvm.metadata"
+
+;;
+;; Define composite type for struct Color.
+;;
+%llvm.dbg.compositetype = internal constant %llvm.dbg.compositetype.type {
+    uint 19, 
+    {  }* cast (%llvm.dbg.compile_unit.type* %llvm.dbg.compile_unit to {  }*), 
+    sbyte* getelementptr ([6 x sbyte]* %str2, int 0, int 0), 
+    {  }* cast (%llvm.dbg.compile_unit.type* %llvm.dbg.compile_unit to {  }*), 
+    int 1, 
+    uint 96, 
+    uint 32, 
+    uint 0, 
+    {  }* null, 
+    {  }* cast ([3 x {  }*]* %llvm.dbg.array to {  }*) }, section "llvm.metadata"
+%str2 = internal constant [6 x sbyte] c"Color\00", section "llvm.metadata"
+
+;;
+;; Define the Red field.
+;;
+%llvm.dbg.derivedtype1 = internal constant %llvm.dbg.derivedtype.type {
+    uint 13, 
+    {  }* null, 
+    sbyte* getelementptr ([4 x sbyte]* %str3, int 0, int 0), 
+    {  }* cast (%llvm.dbg.compile_unit.type* %llvm.dbg.compile_unit to {  }*), 
+    int 2, 
+    uint 32, 
+    uint 32, 
+    uint 0, 
+    {  }* cast (%llvm.dbg.basictype.type* %llvm.dbg.basictype to {  }*) }, section "llvm.metadata"
+%str3 = internal constant [4 x sbyte] c"Red\00", section "llvm.metadata"
+
+;;
+;; Define the Green field.
+;;
+%llvm.dbg.derivedtype2 = internal constant %llvm.dbg.derivedtype.type {
+    uint 13, 
+    {  }* null, 
+    sbyte* getelementptr ([6 x sbyte]* %str4, int 0, int 0), 
+    {  }* cast (%llvm.dbg.compile_unit.type* %llvm.dbg.compile_unit to {  }*), 
+    int 3, 
+    uint 32, 
+    uint 32, 
+    uint 32, 
+    {  }* cast (%llvm.dbg.basictype.type* %llvm.dbg.basictype to {  }*) }, section "llvm.metadata"
+%str4 = internal constant [6 x sbyte] c"Green\00", section "llvm.metadata"
+
+;;
+;; Define the Blue field.
+;;
+%llvm.dbg.derivedtype3 = internal constant %llvm.dbg.derivedtype.type {
+    uint 13, 
+    {  }* null, 
+    sbyte* getelementptr ([5 x sbyte]* %str5, int 0, int 0), 
+    {  }* cast (%llvm.dbg.compile_unit.type* %llvm.dbg.compile_unit to {  }*), 
+    int 4, 
+    uint 32, 
+    uint 32, 
+    uint 64, 
+    {  }* cast (%llvm.dbg.basictype.type* %llvm.dbg.basictype to {  }*) }, section "llvm.metadata"
+%str5 = internal constant [5 x sbyte] c"Blue\00", section "llvm.metadata"
+
+;;
+;; Define the array of fields used by the composite type Color.
+;;
+%llvm.dbg.array = internal constant [3 x {  }*] [
+      {  }* cast (%llvm.dbg.derivedtype.type* %llvm.dbg.derivedtype1 to {  }*),
+      {  }* cast (%llvm.dbg.derivedtype.type* %llvm.dbg.derivedtype2 to {  }*),
+      {  }* cast (%llvm.dbg.derivedtype.type* %llvm.dbg.derivedtype3 to {  }*) ], section "llvm.metadata"
+
+ +
+ + +
+ C/C++ enumeration types +
+ +
+ +

Given the following as an example of C/C++ enumeration type;

+ +
+enum Trees {
+  Spruce = 100,
+  Oak = 200,
+  Maple = 300
+};
+
+ +

a C/C++ front-end would generate the following descriptors;

+ +
+;;
+;; Define composite type for enum Trees
+;;
+%llvm.dbg.compositetype = internal constant %llvm.dbg.compositetype.type {
+    uint 4, 
+    {  }* cast (%llvm.dbg.compile_unit.type* %llvm.dbg.compile_unit to {  }*), 
+    sbyte* getelementptr ([6 x sbyte]* %str1, int 0, int 0), 
+    {  }* cast (%llvm.dbg.compile_unit.type* %llvm.dbg.compile_unit to {  }*), 
+    int 1, 
+    uint 32, 
+    uint 32, 
+    uint 0, 
+    {  }* null, 
+    {  }* cast ([3 x {  }*]* %llvm.dbg.array to {  }*) }, section "llvm.metadata"
+%str1 = internal constant [6 x sbyte] c"Trees\00", section "llvm.metadata"
+
+;;
+;; Define Spruce enumerator.
+;;
+%llvm.dbg.enumerator1 = internal constant %llvm.dbg.enumerator.type {
+    uint 40, 
+    sbyte* getelementptr ([7 x sbyte]* %str2, int 0, int 0), 
+    int 100 }, section "llvm.metadata"
+%str2 = internal constant [7 x sbyte] c"Spruce\00", section "llvm.metadata"
+
+;;
+;; Define Oak enumerator.
+;;
+%llvm.dbg.enumerator2 = internal constant %llvm.dbg.enumerator.type {
+    uint 40, 
+    sbyte* getelementptr ([4 x sbyte]* %str3, int 0, int 0), 
+    int 200 }, section "llvm.metadata"
+%str3 = internal constant [4 x sbyte] c"Oak\00", section "llvm.metadata"
+
+;;
+;; Define Maple enumerator.
+;;
+%llvm.dbg.enumerator3 = internal constant %llvm.dbg.enumerator.type {
+    uint 40, 
+    sbyte* getelementptr ([6 x sbyte]* %str4, int 0, int 0), 
+    int 300 }, section "llvm.metadata"
+%str4 = internal constant [6 x sbyte] c"Maple\00", section "llvm.metadata"
+
+;;
+;; Define the array of enumerators used by composite type Trees.
+;;
+%llvm.dbg.array = internal constant [3 x {  }*] [
+  {  }* cast (%llvm.dbg.enumerator.type* %llvm.dbg.enumerator1 to {  }*),
+  {  }* cast (%llvm.dbg.enumerator.type* %llvm.dbg.enumerator2 to {  }*),
+  {  }* cast (%llvm.dbg.enumerator.type* %llvm.dbg.enumerator3 to {  }*) ], section "llvm.metadata"
+
+ +
@@ -1110,7 +1640,7 @@ Chris Lattner
LLVM Compiler Infrastructure
- Last modified: $Date: 2006/03/14 05:39:39 $ + Last modified: $Date: 2006/03/14 18:08:46 $ From jlaskey at apple.com Tue Mar 14 12:38:09 2006 From: jlaskey at apple.com (Jim Laskey) Date: Tue, 14 Mar 2006 12:38:09 -0600 Subject: [llvm-commits] CVS: llvm/lib/CodeGen/MachineDebugInfo.cpp Message-ID: <200603141838.MAA19184@zion.cs.uiuc.edu> Changes in directory llvm/lib/CodeGen: MachineDebugInfo.cpp updated: 1.30 -> 1.31 --- Log message: 1. Use null for serialized empty strings. 2. Allow for user defined debug descriptors. 3. Allow for user augmented fields on debug descriptors. --- Diffs of the changes: (+17 -9) MachineDebugInfo.cpp | 26 +++++++++++++++++--------- 1 files changed, 17 insertions(+), 9 deletions(-) Index: llvm/lib/CodeGen/MachineDebugInfo.cpp diff -u llvm/lib/CodeGen/MachineDebugInfo.cpp:1.30 llvm/lib/CodeGen/MachineDebugInfo.cpp:1.31 --- llvm/lib/CodeGen/MachineDebugInfo.cpp:1.30 Thu Mar 9 11:48:46 2006 +++ llvm/lib/CodeGen/MachineDebugInfo.cpp Tue Mar 14 12:37:57 2006 @@ -270,7 +270,11 @@ Elements.push_back(ConstantBool::get(Field)); } virtual void Apply(std::string &Field) { - Elements.push_back(SR.getString(Field)); + if (Field.empty()) { + Elements.push_back(NULL); + } else { + Elements.push_back(SR.getString(Field)); + } } virtual void Apply(DebugInfoDesc *&Field) { GlobalVariable *GV = NULL; @@ -417,7 +421,7 @@ } virtual void Apply(std::string &Field) { Constant *C = CI->getOperand(I++); - IsValid = IsValid && isStringValue(C); + IsValid = IsValid && (!C || isStringValue(C)); } virtual void Apply(DebugInfoDesc *&Field) { // FIXME - Prepare the correct descriptor. @@ -1086,11 +1090,13 @@ // Create an empty instance of the correct sort. Slot = DebugInfoDesc::DescFactory(Tag); - assert(Slot && "Unknown Tag"); - // Deserialize the fields. - DIDeserializeVisitor DRAM(*this, GV); - DRAM.ApplyToFields(Slot); + // If not a user defined descriptor. + if (Slot) { + // Deserialize the fields. + DIDeserializeVisitor DRAM(*this, GV); + DRAM.ApplyToFields(Slot); + } return Slot; } @@ -1238,7 +1244,9 @@ // Construct an empty DebugInfoDesc. DebugInfoDesc *DD = DebugInfoDesc::DescFactory(Tag); - if (!DD) return false; + + // Allow for user defined descriptors. + if (!DD) return true; // Get the initializer constant. ConstantStruct *CI = cast(GV->getInitializer()); @@ -1255,8 +1263,8 @@ Slot = CTAM.getCount(); } - // Field count must equal operand count. - if (Slot != N) { + // Field count must be at most equal operand count. + if (Slot > N) { delete DD; return false; } From jlaskey at apple.com Tue Mar 14 12:51:02 2006 From: jlaskey at apple.com (Jim Laskey) Date: Tue, 14 Mar 2006 12:51:02 -0600 Subject: [llvm-commits] CVS: llvm/docs/SourceLevelDebugging.html Message-ID: <200603141851.MAA19286@zion.cs.uiuc.edu> Changes in directory llvm/docs: SourceLevelDebugging.html updated: 1.13 -> 1.14 --- Log message: Reflect the fact that empty strings can be expressed as null. --- Diffs of the changes: (+5 -6) SourceLevelDebugging.html | 11 +++++------ 1 files changed, 5 insertions(+), 6 deletions(-) Index: llvm/docs/SourceLevelDebugging.html diff -u llvm/docs/SourceLevelDebugging.html:1.13 llvm/docs/SourceLevelDebugging.html:1.14 --- llvm/docs/SourceLevelDebugging.html:1.13 Tue Mar 14 12:08:46 2006 +++ llvm/docs/SourceLevelDebugging.html Tue Mar 14 12:50:50 2006 @@ -1407,14 +1407,13 @@ %llvm.dbg.derivedtype2 = internal constant %llvm.dbg.derivedtype.type { uint 15, { }* cast (%llvm.dbg.compile_unit.type* %llvm.dbg.compile_unit to { }*), - sbyte* getelementptr ([1 x sbyte]* %str2, int 0, int 0), + sbyte* null, { }* null, int 0, uint 32, uint 32, uint 0, { }* cast (%llvm.dbg.derivedtype.type* %llvm.dbg.derivedtype3 to { }*) }, section "llvm.metadata" -%str2 = internal constant [1 x sbyte] zeroinitializer, section "llvm.metadata" ;; ;; Define the const type. @@ -1422,7 +1421,7 @@ %llvm.dbg.derivedtype3 = internal constant %llvm.dbg.derivedtype.type { uint 38, { }* cast (%llvm.dbg.compile_unit.type* %llvm.dbg.compile_unit to { }*), - sbyte* getelementptr ([1 x sbyte]* %str2, int 0, int 0), + sbyte* null, { }* null, int 0, uint 0, @@ -1436,14 +1435,14 @@ %llvm.dbg.basictype1 = internal constant %llvm.dbg.basictype.type { uint 36, { }* cast (%llvm.dbg.compile_unit.type* %llvm.dbg.compile_unit to { }*), - sbyte* getelementptr ([4 x sbyte]* %str4, int 0, int 0), + sbyte* getelementptr ([4 x sbyte]* %str2, int 0, int 0), { }* null, int 0, uint 32, uint 32, uint 0, uint 5 }, section "llvm.metadata" -%str4 = internal constant [4 x sbyte] c"int\00", section "llvm.metadata" +%str2 = internal constant [4 x sbyte] c"int\00", section "llvm.metadata"
@@ -1640,7 +1639,7 @@ Chris Lattner
LLVM Compiler Infrastructure
- Last modified: $Date: 2006/03/14 18:08:46 $ + Last modified: $Date: 2006/03/14 18:50:50 $ From lattner at cs.uiuc.edu Tue Mar 14 13:31:36 2006 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Tue, 14 Mar 2006 13:31:36 -0600 Subject: [llvm-commits] CVS: llvm/lib/Target/README.txt Message-ID: <200603141931.NAA19504@zion.cs.uiuc.edu> Changes in directory llvm/lib/Target: README.txt updated: 1.20 -> 1.21 --- Log message: add a note --- Diffs of the changes: (+8 -0) README.txt | 8 ++++++++ 1 files changed, 8 insertions(+) Index: llvm/lib/Target/README.txt diff -u llvm/lib/Target/README.txt:1.20 llvm/lib/Target/README.txt:1.21 --- llvm/lib/Target/README.txt:1.20 Tue Mar 14 00:57:34 2006 +++ llvm/lib/Target/README.txt Tue Mar 14 13:31:24 2006 @@ -113,3 +113,11 @@ //===---------------------------------------------------------------------===// +This code: +int rot(unsigned char b) { int a = ((b>>1) ^ (b<<7)) & 0xff; return a; } + +Can be improved in two ways: + +1. The instcombiner should eliminate the type conversions. +2. The X86 backend should turn this into a rotate by one bit. + From lattner at cs.uiuc.edu Tue Mar 14 13:41:57 2006 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Tue, 14 Mar 2006 13:41:57 -0600 Subject: [llvm-commits] CVS: llvm/lib/VMCore/Dominators.cpp Message-ID: <200603141941.NAA19594@zion.cs.uiuc.edu> Changes in directory llvm/lib/VMCore: Dominators.cpp updated: 1.68 -> 1.69 --- Log message: Fix an et-forest memory leak. Patch by Daniel Berlin. --- Diffs of the changes: (+1 -0) Dominators.cpp | 1 + 1 files changed, 1 insertion(+) Index: llvm/lib/VMCore/Dominators.cpp diff -u llvm/lib/VMCore/Dominators.cpp:1.68 llvm/lib/VMCore/Dominators.cpp:1.69 --- llvm/lib/VMCore/Dominators.cpp:1.68 Sat Jan 14 14:55:09 2006 +++ llvm/lib/VMCore/Dominators.cpp Tue Mar 14 13:41:45 2006 @@ -682,6 +682,7 @@ rightmost->MinOccurrence = NewFatherOcc->MinOccurrence; } + delete ParentOcc; ParentOcc = NewFatherOcc; // Update *our* tree From lattner at cs.uiuc.edu Tue Mar 14 13:50:08 2006 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Tue, 14 Mar 2006 13:50:08 -0600 Subject: [llvm-commits] CVS: llvm/lib/VMCore/AutoUpgrade.cpp Message-ID: <200603141950.NAA19669@zion.cs.uiuc.edu> Changes in directory llvm/lib/VMCore: AutoUpgrade.cpp updated: 1.13 -> 1.14 --- Log message: Bugfix, unbreaking CodeGen/PowerPC/cttz.ll --- Diffs of the changes: (+1 -1) AutoUpgrade.cpp | 2 +- 1 files changed, 1 insertion(+), 1 deletion(-) Index: llvm/lib/VMCore/AutoUpgrade.cpp diff -u llvm/lib/VMCore/AutoUpgrade.cpp:1.13 llvm/lib/VMCore/AutoUpgrade.cpp:1.14 --- llvm/lib/VMCore/AutoUpgrade.cpp:1.13 Mon Mar 13 20:00:35 2006 +++ llvm/lib/VMCore/AutoUpgrade.cpp Tue Mar 14 13:49:57 2006 @@ -259,7 +259,7 @@ Instruction *RetVal = NewCI; if (F->getReturnType() != NewFn->getReturnType()) { - RetVal = new CastInst(NewCI, NewFn->getReturnType(), + RetVal = new CastInst(NewCI, F->getReturnType(), NewCI->getName(), CI); NewCI->moveBefore(RetVal); } From lattner at cs.uiuc.edu Tue Mar 14 14:00:32 2006 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Tue, 14 Mar 2006 14:00:32 -0600 Subject: [llvm-commits] CVS: llvm/include/llvm/Intrinsics.td Message-ID: <200603142000.OAA19757@zion.cs.uiuc.edu> Changes in directory llvm/include/llvm: Intrinsics.td updated: 1.7 -> 1.8 --- Log message: Fix the gcread/gcwrite intrinsic specifications, fixing CodeGen/Generic/GC/alloc_loop.ll --- Diffs of the changes: (+5 -5) Intrinsics.td | 10 +++++----- 1 files changed, 5 insertions(+), 5 deletions(-) Index: llvm/include/llvm/Intrinsics.td diff -u llvm/include/llvm/Intrinsics.td:1.7 llvm/include/llvm/Intrinsics.td:1.8 --- llvm/include/llvm/Intrinsics.td:1.7 Mon Mar 13 16:38:32 2006 +++ llvm/include/llvm/Intrinsics.td Tue Mar 14 14:00:20 2006 @@ -73,12 +73,11 @@ def llvm_double_ty : LLVMType<"Type::DoubleTyID">; def llvm_ptr_ty : LLVMType<"Type::PointerTyID">; // sbyte* def llvm_ptrptr_ty : LLVMType<"Type::PointerTyID">; // sbyte** -def llvm_anchor_ty : LLVMType<"Type::PointerTyID">; // {}* def llvm_descriptor_ty : LLVMType<"Type::PointerTyID">; // global* def llvm_v4i32_ty : LLVMPackedType<4, llvm_int_ty>; // 4 x int def llvm_v4f32_ty : LLVMPackedType<4, llvm_float_ty>; // 4 x float -def llvm_v2f64_ty : LLVMPackedType<4, llvm_float_ty>; // 2 x double +def llvm_v2f64_ty : LLVMPackedType<4, llvm_double_ty>; // 2 x double //===----------------------------------------------------------------------===// // Intrinsic Definitions. @@ -121,9 +120,10 @@ //===------------------- Garbage Collection Intrinsics --------------------===// // def int_gcroot : Intrinsic<[llvm_void_ty, llvm_ptrptr_ty, llvm_ptr_ty]>; -def int_gcread : Intrinsic<[llvm_ptr_ty, llvm_ptrptr_ty], [InstrReadArgMem]>; -def int_gcwrite : Intrinsic<[llvm_void_ty, llvm_ptr_ty, llvm_ptrptr_ty], - [InstrWriteArgMem]>; +def int_gcread : Intrinsic<[llvm_ptr_ty, llvm_ptr_ty, llvm_ptrptr_ty], + [InstrReadArgMem]>; +def int_gcwrite : Intrinsic<[llvm_void_ty, llvm_ptr_ty, llvm_ptr_ty, + llvm_ptrptr_ty], [InstrWriteArgMem]>; //===--------------------- Code Generator Intrinsics ----------------------===// // From lattner at cs.uiuc.edu Tue Mar 14 14:03:03 2006 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Tue, 14 Mar 2006 14:03:03 -0600 Subject: [llvm-commits] CVS: llvm/docs/LangRef.html Message-ID: <200603142003.OAA19809@zion.cs.uiuc.edu> Changes in directory llvm/docs: LangRef.html updated: 1.139 -> 1.140 --- Log message: Update this to match the documentation in the GC doc and to match actual practice. --- Diffs of the changes: (+11 -7) LangRef.html | 18 +++++++++++------- 1 files changed, 11 insertions(+), 7 deletions(-) Index: llvm/docs/LangRef.html diff -u llvm/docs/LangRef.html:1.139 llvm/docs/LangRef.html:1.140 --- llvm/docs/LangRef.html:1.139 Mon Mar 13 23:39:39 2006 +++ llvm/docs/LangRef.html Tue Mar 14 14:02:51 2006 @@ -2917,7 +2917,7 @@
Syntax:
-  declare sbyte* %llvm.gcread(sbyte** %Ptr)
+  declare sbyte* %llvm.gcread(sbyte* %ObjPtr, sbyte** %Ptr)
Overview:
@@ -2928,8 +2928,10 @@
Arguments:
-

The argument is the address to read from, which should be an address -allocated from the garbage collector.

+

The second argument is the address to read from, which should be an address +allocated from the garbage collector. The first object is a pointer to the +start of the referenced object, if needed by the language runtime (otherwise +null).

Semantics:
@@ -2950,7 +2952,7 @@
Syntax:
-  declare void %llvm.gcwrite(sbyte* %P1, sbyte** %P2)
+  declare void %llvm.gcwrite(sbyte* %P1, sbyte* %Obj, sbyte** %P2)
Overview:
@@ -2961,8 +2963,10 @@
Arguments:
-

The first argument is the reference to store, and the second is the heap -location to store to.

+

The first argument is the reference to store, the second is the start of the +object to store it to, and the third is the address of the field of Obj to +store to. If the runtime does not require a pointer to the object, Obj may be +null.

Semantics:
@@ -3694,7 +3698,7 @@ Chris Lattner
The LLVM Compiler Infrastructure
- Last modified: $Date: 2006/03/14 05:39:39 $ + Last modified: $Date: 2006/03/14 20:02:51 $ From bocchino at persephone.cs.uiuc.edu Tue Mar 14 14:55:51 2006 From: bocchino at persephone.cs.uiuc.edu (Robert L. Bocchino Jr.) Date: Tue, 14 Mar 2006 14:55:51 -0600 (CST) Subject: [llvm-commits] CVS: llvm/docs/LangRef.html Message-ID: <20060314205551.71A7220E88E6@persephone.cs.uiuc.edu> Changes in directory llvm/docs: LangRef.html updated: 1.140 -> 1.141 --- Log message: Split the 'vset' instruction into two instructions, 'vsetint' and 'vsetfp', to reflect the fact that the semantics are different for integer and fp values. --- Diffs of the changes: (+74 -39) LangRef.html | 113 ++++++++++++++++++++++++++++++++++++++--------------------- 1 files changed, 74 insertions(+), 39 deletions(-) Index: llvm/docs/LangRef.html diff -u llvm/docs/LangRef.html:1.140 llvm/docs/LangRef.html:1.141 --- llvm/docs/LangRef.html:1.140 Tue Mar 14 14:02:51 2006 +++ llvm/docs/LangRef.html Tue Mar 14 14:55:28 2006 @@ -106,7 +106,8 @@
  • 'phi' Instruction
  • 'cast .. to' Instruction
  • 'select' Instruction
    • -
  • 'vset' Instruction
    • +
  • 'vsetint' Instruction
    • +
  • 'vsetfp' Instruction
  • 'vselect' Instruction
  • 'extractelement' Instruction
  • 'insertelement' Instruction
    • @@ -2331,56 +2332,50 @@
    -
    'vset' +
    'vsetint' Instruction
    Syntax:
    -
    <result> = vset <op>, <n x <ty>> <var1>, <var2>   ; yields <n x bool>
+
    <result> = vsetint <op>, <n x <ty>> <var1>, <var2>   ; yields <n x bool>
 
    
 
 
    Overview:
    
 
-
    The 'vset' instruction returns a vector of boolean
-values representing, at each position, the result of the comparison
-between the values at that position in the two operands.
    
+
    The 'vsetint' instruction takes two integer vectors and
+returns a vector of boolean values representing, at each position, the
+result of the comparison between the values at that position in the
+two operands.
    
 
 
    Arguments:
    
 
-
    The arguments to a 'vset' instruction are a comparison
+
    The arguments to a 'vsetint' instruction are a comparison
 operation and two value arguments.  The value arguments must be of packed type, and they must have identical types.
-For value arguments of integral element type, the operation argument
-must be one of eq, ne, lt, gt,
-le, ge, ult, ugt, ule,
-uge, true, and false.  For value arguments
-of floating point element type, the operation argument must be one of
-eq, ne, lt, gt, le,
-ge, oeq, one, olt, ogt,
-ole, oge, ueq, une, ult,
-ugt, ule, uge, o, u,
-true, and false.  The result is a packed
-bool value with the same length as each operand.
    
+href="#t_integral">integral packed type,
+and they must have identical types.  The operation argument must be
+one of eq, ne, slt, sgt,
+sle, sge, ult, ugt, ule,
+uge, true, and false.  The result is a
+packed bool value with the same length as each operand.
    
 
 
    Semantics:
    
 
-
    The following table shows the semantics of 'vset' for
-integral value arguments.  For each position of the result, the
-comparison is done on the corresponding positions of the two value
-arguments.  Note that the signedness of the comparison depends on the
-comparison opcode and not on the signedness of the value
-operands.  E.g., vset lt <4 x unsigned> %x, %y does an
-elementwise signed comparison of %x and
-%y.
    
+
    The following table shows the semantics of 'vsetint'.  For
+each position of the result, the comparison is done on the
+corresponding positions of the two value arguments.  Note that the
+signedness of the comparison depends on the comparison opcode and
+not on the signedness of the value operands.  E.g., vsetint
+slt <4 x unsigned> %x, %y does an elementwise signed
+comparison of %x and %y.
    
 
 
-    
-    
-    
-    
+    
+    
+    
+    
@@ -2390,7 +2385,47 @@
   
    
   
     
    OperationResult is true iffComparison is
    
     
    eqvar1 == var2--
    
     
    nevar1 != var2--
    ltvar1 < var2signed
    gtvar1 > var2signed
    levar1 <= var2signed
    gevar1 >= var2signed
    sltvar1 < var2signed
    sgtvar1 > var2signed
    slevar1 <= var2signed
    sgevar1 >= var2signed
    
     
    ultvar1 < var2unsigned
    
     
    ugtvar1 > var2unsigned
    
     
    ulevar1 <= var2unsigned
    
 
    
 
-
    The following table shows the semantics of 'vset' for
+
    Example:
    
+
      <result> = vsetint eq <2 x int> <int 0, int 1>, <int 1, int 0>      ; yields {<2 x bool>}:result = false, false
+  <result> = vsetint ne <2 x int> <int 0, int 1>, <int 1, int 0>      ; yields {<2 x bool>}:result = true, true
+  <result> = vsetint slt <2 x int> <int 0, int 1>, <int 1, int 0>      ; yields {<2 x bool>}:result = true, false
+  <result> = vsetint sgt <2 x int> <int 0, int 1>, <int 1, int 0>      ; yields {<2 x bool>}:result = false, true
+  <result> = vsetint sle <2 x int> <int 0, int 1>, <int 1, int 0>      ; yields {<2 x bool>}:result = true, false
+  <result> = vsetint sge <2 x int> <int 0, int 1>, <int 1, int 0>      ; yields {<2 x bool>}:result = false, true
+
    
+
    + + +
    'vsetfp' +Instruction
    +
    +
    Syntax:
    +
    <result> = vsetfp <op>, <n x <ty>> <var1>, <var2>   ; yields <n x bool>
+
    + +
    Overview:
    + +

    The 'vsetfp' instruction takes two floating point vector +arguments and returns a vector of boolean values representing, at each +position, the result of the comparison between the values at that +position in the two operands.

    + +
    Arguments:
    + +

    The arguments to a 'vsetfp' instruction are a comparison +operation and two value arguments. The value arguments must be of floating point packed +type, and they must have identical types. The operation argument must +be one of eq, ne, lt, gt, +le, ge, oeq, one, olt, +ogt, ole, oge, ueq, une, +ult, ugt, ule, uge, o, +u, true, and false. The result is a packed +bool value with the same length as each operand.

    + +
    Semantics:
    + +

    The following table shows the semantics of 'vsetfp' for floating point types. If either operand is a floating point Not a Number (NaN) value, the operation is unordered, and the value in the first column below is produced at that position. Otherwise, the @@ -2426,12 +2461,12 @@

    Example:
    -
      <result> = vset eq <2 x int> <int 0, int 1>, <int 1, int 0>      ; yields {<2 x bool>}:result = false, false
-  <result> = vset ne <2 x int> <int 0, int 1>, <int 1, int 0>      ; yields {<2 x bool>}:result = true, true
-  <result> = vset lt <2 x int> <int 0, int 1>, <int 1, int 0>      ; yields {<2 x bool>}:result = true, false
-  <result> = vset gt <2 x int> <int 0, int 1>, <int 1, int 0>      ; yields {<2 x bool>}:result = false, true
-  <result> = vset le <2 x int> <int 0, int 1>, <int 1, int 0>      ; yields {<2 x bool>}:result = true, false
-  <result> = vset ge <2 x int> <int 0, int 1>, <int 1, int 0>      ; yields {<2 x bool>}:result = false, true
+
      <result> = vsetfp eq <2 x float> <float 0, float 1>, <float 1, float 0>      ; yields {<2 x bool>}:result = false, false
+  <result> = vsetfp ne <2 x float> <float 0, float 1>, <float 1, float 0>      ; yields {<2 x bool>}:result = true, true
+  <result> = vsetfp lt <2 x float> <float 0, float 1>, <float 1, float 0>      ; yields {<2 x bool>}:result = true, false
+  <result> = vsetfp gt <2 x float> <float 0, float 1>, <float 1, float 0>      ; yields {<2 x bool>}:result = false, true
+  <result> = vsetfp le <2 x float> <float 0, float 1>, <float 1, float 0>      ; yields {<2 x bool>}:result = true, false
+  <result> = vsetfp ge <2 x float> <float 0, float 1>, <float 1, float 0>      ; yields {<2 x bool>}:result = false, true
    @@ -3698,7 +3733,7 @@ Chris Lattner
    The LLVM Compiler Infrastructure
    - Last modified: $Date: 2006/03/14 20:02:51 $ + Last modified: $Date: 2006/03/14 20:55:28 $ From bocchino at persephone.cs.uiuc.edu Tue Mar 14 17:23:20 2006 From: bocchino at persephone.cs.uiuc.edu (Robert L. Bocchino Jr.) Date: Tue, 14 Mar 2006 17:23:20 -0600 (CST) Subject: [llvm-commits] CVS: llvm/docs/LangRef.html Message-ID: <20060314232320.31EA820E95E7@persephone.cs.uiuc.edu> Changes in directory llvm/docs: LangRef.html updated: 1.141 -> 1.142 --- Log message: Fixed a typo in the vsetfp examples. --- Diffs of the changes: (+7 -7) LangRef.html | 14 +++++++------- 1 files changed, 7 insertions(+), 7 deletions(-) Index: llvm/docs/LangRef.html diff -u llvm/docs/LangRef.html:1.141 llvm/docs/LangRef.html:1.142 --- llvm/docs/LangRef.html:1.141 Tue Mar 14 14:55:28 2006 +++ llvm/docs/LangRef.html Tue Mar 14 17:22:57 2006 @@ -2461,12 +2461,12 @@
    Example:
    -
      <result> = vsetfp eq <2 x float> <float 0, float 1>, <float 1, float 0>      ; yields {<2 x bool>}:result = false, false
-  <result> = vsetfp ne <2 x float> <float 0, float 1>, <float 1, float 0>      ; yields {<2 x bool>}:result = true, true
-  <result> = vsetfp lt <2 x float> <float 0, float 1>, <float 1, float 0>      ; yields {<2 x bool>}:result = true, false
-  <result> = vsetfp gt <2 x float> <float 0, float 1>, <float 1, float 0>      ; yields {<2 x bool>}:result = false, true
-  <result> = vsetfp le <2 x float> <float 0, float 1>, <float 1, float 0>      ; yields {<2 x bool>}:result = true, false
-  <result> = vsetfp ge <2 x float> <float 0, float 1>, <float 1, float 0>      ; yields {<2 x bool>}:result = false, true
+
      <result> = vsetfp eq <2 x float> <float 0.0, float 1.0>, <float 1.0, float 0.0>      ; yields {<2 x bool>}:result = false, false
+  <result> = vsetfp ne <2 x float> <float 0.0, float 1.0>, <float 1.0, float 0.0>      ; yields {<2 x bool>}:result = true, true
+  <result> = vsetfp lt <2 x float> <float 0.0, float 1.0>, <float 1.0, float 0.0>      ; yields {<2 x bool>}:result = true, false
+  <result> = vsetfp gt <2 x float> <float 0.0, float 1.0>, <float 1.0, float 0.0>      ; yields {<2 x bool>}:result = false, true
+  <result> = vsetfp le <2 x float> <float 0.0, float 1.0>, <float 1.0, float 0.0>      ; yields {<2 x bool>}:result = true, false
+  <result> = vsetfp ge <2 x float> <float 0.0, float 1.0>, <float 1.0, float 0.0>      ; yields {<2 x bool>}:result = false, true
    @@ -3733,7 +3733,7 @@ Chris Lattner
    The LLVM Compiler Infrastructure
    - Last modified: $Date: 2006/03/14 20:55:28 $ + Last modified: $Date: 2006/03/14 23:22:57 $ From lattner at cs.uiuc.edu Tue Mar 14 19:32:47 2006 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Tue, 14 Mar 2006 19:32:47 -0600 Subject: [llvm-commits] CVS: llvm/include/llvm/Intrinsics.td Message-ID: <200603150132.TAA21826@zion.cs.uiuc.edu> Changes in directory llvm/include/llvm: Intrinsics.td updated: 1.8 -> 1.9 --- Log message: Set TargetPrefix on target-specific intrinsics. That way, in theory, different targets could have different implemenations of a __builtin_foo gcc intrinsic. --- Diffs of the changes: (+7 -7) Intrinsics.td | 14 +++++++------- 1 files changed, 7 insertions(+), 7 deletions(-) Index: llvm/include/llvm/Intrinsics.td diff -u llvm/include/llvm/Intrinsics.td:1.8 llvm/include/llvm/Intrinsics.td:1.9 --- llvm/include/llvm/Intrinsics.td:1.8 Tue Mar 14 14:00:20 2006 +++ llvm/include/llvm/Intrinsics.td Tue Mar 14 19:32:36 2006 @@ -97,6 +97,7 @@ string name = ""> { string LLVMName = name; string GCCBuiltinName = ""; + string TargetPrefix = ""; // Set to a prefix for target-specific intrinsics. list Types = types; list Properties = properties; } @@ -204,8 +205,6 @@ def int_dbg_region_start : Intrinsic<[llvm_void_ty]>; def int_dbg_region_end : Intrinsic<[llvm_void_ty]>; def int_dbg_func_start : Intrinsic<[llvm_void_ty, llvm_descriptor_ty]>; -// dbg_declare, // Declare a local object - //===----------------------------------------------------------------------===// @@ -214,8 +213,9 @@ //===----------------------------------------------------------------------===// // PowerPC Intrinsics - -def int_ppc_altivec_lvx : Intrinsic<[llvm_v4i32_ty, llvm_int_ty, llvm_ptr_ty], - [IntrReadMem]>, - GCCBuiltin<"__builtin_altivec_lvx">; - +// +let TargetPrefix = "ppc" in { // All intrinsics start with "llvm.ppc.". + def int_ppc_altivec_lvx : Intrinsic<[llvm_v4i32_ty, llvm_int_ty, llvm_ptr_ty], + [IntrReadMem]>, + GCCBuiltin<"__builtin_altivec_lvx">; +} From lattner at cs.uiuc.edu Tue Mar 14 19:33:38 2006 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Tue, 14 Mar 2006 19:33:38 -0600 Subject: [llvm-commits] CVS: llvm/utils/TableGen/CodeGenIntrinsics.h IntrinsicEmitter.cpp IntrinsicEmitter.h Message-ID: <200603150133.TAA21892@zion.cs.uiuc.edu> Changes in directory llvm/utils/TableGen: CodeGenIntrinsics.h updated: 1.5 -> 1.6 IntrinsicEmitter.cpp updated: 1.9 -> 1.10 IntrinsicEmitter.h updated: 1.6 -> 1.7 --- Log message: Autogenerate code to map from GCC builtin to LLVM intrinsic. --- Diffs of the changes: (+59 -1) CodeGenIntrinsics.h | 1 IntrinsicEmitter.cpp | 57 ++++++++++++++++++++++++++++++++++++++++++++++++++- IntrinsicEmitter.h | 2 + 3 files changed, 59 insertions(+), 1 deletion(-) Index: llvm/utils/TableGen/CodeGenIntrinsics.h diff -u llvm/utils/TableGen/CodeGenIntrinsics.h:1.5 llvm/utils/TableGen/CodeGenIntrinsics.h:1.6 --- llvm/utils/TableGen/CodeGenIntrinsics.h:1.5 Mon Mar 13 17:08:44 2006 +++ llvm/utils/TableGen/CodeGenIntrinsics.h Tue Mar 14 19:33:26 2006 @@ -26,6 +26,7 @@ std::string Name; // The name of the LLVM function "llvm.bswap.i32" std::string EnumName; // The name of the enum "bswap_i32" std::string GCCBuiltinName;// Name of the corresponding GCC builtin, or "". + std::string TargetPrefix; // Target prefix, e.g. "ppc" for t-s intrinsics. /// ArgTypes - The type primitive enum value for the return value and all /// of the arguments. These are things like Type::UIntTyID. Index: llvm/utils/TableGen/IntrinsicEmitter.cpp diff -u llvm/utils/TableGen/IntrinsicEmitter.cpp:1.9 llvm/utils/TableGen/IntrinsicEmitter.cpp:1.10 --- llvm/utils/TableGen/IntrinsicEmitter.cpp:1.9 Mon Mar 13 23:59:52 2006 +++ llvm/utils/TableGen/IntrinsicEmitter.cpp Tue Mar 14 19:33:26 2006 @@ -34,7 +34,7 @@ throw "Intrinsic '" + DefName + "' does not start with 'int_'!"; EnumName = std::string(DefName.begin()+4, DefName.end()); GCCBuiltinName = R->getValueAsString("GCCBuiltinName"); - + TargetPrefix = R->getValueAsString("TargetPrefix"); Name = R->getValueAsString("LLVMName"); if (Name == "") { // If an explicit name isn't specified, derive one from the DefName. @@ -44,6 +44,21 @@ Name += '.'; else Name += EnumName[i]; + } else { + // Verify it starts with "llvm.". + if (Name.size() <= 5 || + std::string(Name.begin(), Name.begin()+5) != "llvm.") + throw "Intrinsic '" + DefName + "'s name does not start with 'llvm.'!"; + } + + // If TargetPrefix is specified, make sure that Name starts with + // "llvm..". + if (!TargetPrefix.empty()) { + if (Name.size() < 6+TargetPrefix.size() || + std::string(Name.begin()+5, Name.begin()+6+TargetPrefix.size()) + != (TargetPrefix+".")) + throw "Intrinsic '" + DefName + "' does not start with 'llvm." + + TargetPrefix + ".'!"; } // Parse the list of argument types. @@ -109,6 +124,9 @@ // Emit a list of intrinsics with corresponding GCC builtins. EmitGCCBuiltinList(Ints, OS); + + // Emit code to translate GCC builtins into LLVM intrinsics. + EmitIntrinsicToGCCBuiltinMap(Ints, OS); } void IntrinsicEmitter::EmitEnumInfo(const std::vector &Ints, @@ -253,3 +271,40 @@ OS << " }\n"; OS << "#endif\n\n"; } + +void IntrinsicEmitter:: +EmitIntrinsicToGCCBuiltinMap(const std::vector &Ints, + std::ostream &OS) { + typedef std::map, std::string> BIMTy; + BIMTy BuiltinMap; + for (unsigned i = 0, e = Ints.size(); i != e; ++i) { + if (!Ints[i].GCCBuiltinName.empty()) { + std::pair Key(Ints[i].GCCBuiltinName, + Ints[i].TargetPrefix); + if (!BuiltinMap.insert(std::make_pair(Key, Ints[i].EnumName)).second) + throw "Intrinsic '" + Ints[i].TheDef->getName() + + "': duplicate GCC builtin name!"; + } + } + + OS << "// Get the LLVM intrinsic that corresponds to a GCC builtin.\n"; + OS << "// This is used by the C front-end. The GCC builtin name is passed\n"; + OS << "// in as BuiltinName, and a target prefix (e.g. 'ppc') is passed\n"; + OS << "// in as TargetPrefix. The result is assigned to 'IntrinsicID'.\n"; + OS << "#ifdef GET_LLVM_INTRINSIC_FOR_GCC_BUILTIN\n"; + OS << " if (0);\n"; + // Note: this could emit significantly better code if we cared. + for (BIMTy::iterator I = BuiltinMap.begin(), E = BuiltinMap.end();I != E;++I){ + OS << " else if ("; + if (!I->first.second.empty()) { + // Emit this as a strcmp, so it can be constant folded by the FE. + OS << "!strcmp(TargetPrefix, \"" << I->first.second << "\") &&\n" + << " "; + } + OS << "!strcmp(BuiltinName, \"" << I->first.first << "\"))\n"; + OS << " IntrinsicID = Intrinsic::" << I->second << "\";\n"; + } + OS << " else\n"; + OS << " IntrinsicID = Intrinsic::not_intrinsic;\n"; + OS << "#endif\n\n"; +} Index: llvm/utils/TableGen/IntrinsicEmitter.h diff -u llvm/utils/TableGen/IntrinsicEmitter.h:1.6 llvm/utils/TableGen/IntrinsicEmitter.h:1.7 --- llvm/utils/TableGen/IntrinsicEmitter.h:1.6 Mon Mar 13 17:08:44 2006 +++ llvm/utils/TableGen/IntrinsicEmitter.h Tue Mar 14 19:33:26 2006 @@ -39,6 +39,8 @@ std::ostream &OS); void EmitGCCBuiltinList(const std::vector &Ints, std::ostream &OS); + void EmitIntrinsicToGCCBuiltinMap(const std::vector &Ints, + std::ostream &OS); }; } // End llvm namespace From lattner at cs.uiuc.edu Tue Mar 14 19:55:33 2006 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Tue, 14 Mar 2006 19:55:33 -0600 Subject: [llvm-commits] CVS: llvm/utils/TableGen/IntrinsicEmitter.cpp IntrinsicEmitter.h Message-ID: <200603150155.TAA22157@zion.cs.uiuc.edu> Changes in directory llvm/utils/TableGen: IntrinsicEmitter.cpp updated: 1.10 -> 1.11 IntrinsicEmitter.h updated: 1.7 -> 1.8 --- Log message: Autogenerate a table of intrinsic names, so we can map from intrinsic ID to LLVM intrinsic function name. --- Diffs of the changes: (+22 -4) IntrinsicEmitter.cpp | 24 ++++++++++++++++++++---- IntrinsicEmitter.h | 2 ++ 2 files changed, 22 insertions(+), 4 deletions(-) Index: llvm/utils/TableGen/IntrinsicEmitter.cpp diff -u llvm/utils/TableGen/IntrinsicEmitter.cpp:1.10 llvm/utils/TableGen/IntrinsicEmitter.cpp:1.11 --- llvm/utils/TableGen/IntrinsicEmitter.cpp:1.10 Tue Mar 14 19:33:26 2006 +++ llvm/utils/TableGen/IntrinsicEmitter.cpp Tue Mar 14 19:55:21 2006 @@ -109,10 +109,13 @@ // Emit the enum information. EmitEnumInfo(Ints, OS); + + // Emit the intrinsic ID -> name table. + EmitIntrinsicToNameTable(Ints, OS); // Emit the function name recognizer. EmitFnNameRecognizer(Ints, OS); - + // Emit the intrinsic verifier. EmitVerifier(Ints, OS); @@ -158,9 +161,6 @@ char LastChar = 0; for (std::map::iterator I = IntMapping.begin(), E = IntMapping.end(); I != E; ++I) { - assert(I->first.size() > 5 && std::string(I->first.begin(), - I->first.begin()+5) == "llvm." && - "Invalid intrinsic name!"); if (I->first[5] != LastChar) { LastChar = I->first[5]; OS << " case '" << LastChar << "':\n"; @@ -175,6 +175,22 @@ OS << "#endif\n\n"; } +void IntrinsicEmitter:: +EmitIntrinsicToNameTable(const std::vector &Ints, + std::ostream &OS) { + std::vector Names; + for (unsigned i = 0, e = Ints.size(); i != e; ++i) + Names.push_back(Ints[i].Name); + std::sort(Names.begin(), Names.end()); + + OS << "// Intrinsic ID to name table\n"; + OS << "#ifdef GET_INTRINSIC_NAME_TABLE\n"; + OS << " // Note that entry #0 is the invalid intrinsic!\n"; + for (unsigned i = 0, e = Names.size(); i != e; ++i) + OS << " \"" << Names[i] << "\",\n"; + OS << "#endif\n\n"; +} + static void EmitTypeVerify(std::ostream &OS, const std::string &Val, Record *ArgType) { OS << " Assert1(" << Val << "->getTypeID() == " Index: llvm/utils/TableGen/IntrinsicEmitter.h diff -u llvm/utils/TableGen/IntrinsicEmitter.h:1.7 llvm/utils/TableGen/IntrinsicEmitter.h:1.8 --- llvm/utils/TableGen/IntrinsicEmitter.h:1.7 Tue Mar 14 19:33:26 2006 +++ llvm/utils/TableGen/IntrinsicEmitter.h Tue Mar 14 19:55:21 2006 @@ -31,6 +31,8 @@ void EmitFnNameRecognizer(const std::vector &Ints, std::ostream &OS); + void EmitIntrinsicToNameTable(const std::vector &Ints, + std::ostream &OS); void EmitVerifier(const std::vector &Ints, std::ostream &OS); void EmitModRefInfo(const std::vector &Ints, From lattner at cs.uiuc.edu Tue Mar 14 20:05:50 2006 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Tue, 14 Mar 2006 20:05:50 -0600 Subject: [llvm-commits] CVS: llvm/utils/TableGen/IntrinsicEmitter.cpp Message-ID: <200603150205.UAA22315@zion.cs.uiuc.edu> Changes in directory llvm/utils/TableGen: IntrinsicEmitter.cpp updated: 1.11 -> 1.12 --- Log message: remove typo --- Diffs of the changes: (+1 -1) IntrinsicEmitter.cpp | 2 +- 1 files changed, 1 insertion(+), 1 deletion(-) Index: llvm/utils/TableGen/IntrinsicEmitter.cpp diff -u llvm/utils/TableGen/IntrinsicEmitter.cpp:1.11 llvm/utils/TableGen/IntrinsicEmitter.cpp:1.12 --- llvm/utils/TableGen/IntrinsicEmitter.cpp:1.11 Tue Mar 14 19:55:21 2006 +++ llvm/utils/TableGen/IntrinsicEmitter.cpp Tue Mar 14 20:05:38 2006 @@ -318,7 +318,7 @@ << " "; } OS << "!strcmp(BuiltinName, \"" << I->first.first << "\"))\n"; - OS << " IntrinsicID = Intrinsic::" << I->second << "\";\n"; + OS << " IntrinsicID = Intrinsic::" << I->second << ";\n"; } OS << " else\n"; OS << " IntrinsicID = Intrinsic::not_intrinsic;\n"; From jeffc at jolt-lang.org Tue Mar 14 20:51:17 2006 From: jeffc at jolt-lang.org (Jeff Cohen) Date: Tue, 14 Mar 2006 20:51:17 -0600 Subject: [llvm-commits] CVS: llvm/utils/TableGen/IntrinsicEmitter.cpp Message-ID: <200603150251.UAA22418@zion.cs.uiuc.edu> Changes in directory llvm/utils/TableGen: IntrinsicEmitter.cpp updated: 1.12 -> 1.13 --- Log message: Fix VC++ build error. --- Diffs of the changes: (+1 -0) IntrinsicEmitter.cpp | 1 + 1 files changed, 1 insertion(+) Index: llvm/utils/TableGen/IntrinsicEmitter.cpp diff -u llvm/utils/TableGen/IntrinsicEmitter.cpp:1.12 llvm/utils/TableGen/IntrinsicEmitter.cpp:1.13 --- llvm/utils/TableGen/IntrinsicEmitter.cpp:1.12 Tue Mar 14 20:05:38 2006 +++ llvm/utils/TableGen/IntrinsicEmitter.cpp Tue Mar 14 20:51:05 2006 @@ -14,6 +14,7 @@ #include "IntrinsicEmitter.h" #include "Record.h" #include "llvm/ADT/StringExtras.h" +#include using namespace llvm; //===----------------------------------------------------------------------===// From alenhar2 at cs.uiuc.edu Tue Mar 14 21:44:11 2006 From: alenhar2 at cs.uiuc.edu (Andrew Lenharth) Date: Tue, 14 Mar 2006 21:44:11 -0600 Subject: [llvm-commits] CVS: llvm/lib/Analysis/DataStructure/Local.cpp Message-ID: <200603150344.VAA22549@zion.cs.uiuc.edu> Changes in directory llvm/lib/Analysis/DataStructure: Local.cpp updated: 1.140 -> 1.141 --- Log message: improve mem intrinsics and add a few things povray uses --- Diffs of the changes: (+30 -3) Local.cpp | 33 ++++++++++++++++++++++++++++++--- 1 files changed, 30 insertions(+), 3 deletions(-) Index: llvm/lib/Analysis/DataStructure/Local.cpp diff -u llvm/lib/Analysis/DataStructure/Local.cpp:1.140 llvm/lib/Analysis/DataStructure/Local.cpp:1.141 --- llvm/lib/Analysis/DataStructure/Local.cpp:1.140 Thu Mar 2 18:00:25 2006 +++ llvm/lib/Analysis/DataStructure/Local.cpp Tue Mar 14 21:43:59 2006 @@ -545,10 +545,18 @@ return; case Intrinsic::vaend: return; // noop - case Intrinsic::memmove_i32: case Intrinsic::memcpy_i32: - case Intrinsic::memmove_i64: case Intrinsic::memcpy_i64: { + //write first location + if (DSNode *N = getValueDest(**CS.arg_begin()).getNode()) + N->setHeapNodeMarker()->setModifiedMarker(); + //and read second pointer + if (DSNode *N = getValueDest(**(CS.arg_begin() + 1)).getNode()) + N->setReadMarker(); + return; + } + case Intrinsic::memmove_i32: + case Intrinsic::memmove_i64: { // Merge the first & second arguments, and mark the memory read and // modified. DSNodeHandle RetNH = getValueDest(**CS.arg_begin()); @@ -676,7 +684,6 @@ Link.mergeWith(getValueDest(**CS.arg_begin())); } } - return; } else if (F->getName() == "fopen" || F->getName() == "fdopen" || F->getName() == "freopen") { @@ -981,6 +988,26 @@ N->mergeTypeInfo(Type::DoubleTy, H.getOffset()); } return; + } else if (F->getName() == "qsort") { + CallSite::arg_iterator AI = CS.arg_begin(); + if (DSNode *N = getValueDest(**AI).getNode()) + N->setModifiedMarker(); + //How do you mark a function pointer as being called? Assume it is a read + AI += 3; + if (DSNode *N = getValueDest(**AI).getNode()) + N->setReadMarker(); + return; + } else if (F->getName() == "strcat" || F->getName() == "strncat") { + //This might be making unsafe assumptions about usage + //Merge return and first arg + DSNodeHandle RetNH = getValueDest(*CS.getInstruction()); + RetNH.mergeWith(getValueDest(**CS.arg_begin())); + if (DSNode *N = RetNH.getNode()) + N->setHeapNodeMarker()->setModifiedMarker()->setReadMarker(); + //and read second pointer + if (DSNode *N = getValueDest(**(CS.arg_begin() + 1)).getNode()) + N->setReadMarker(); + return; } else { // Unknown function, warn if it returns a pointer type or takes a // pointer argument. From alenhar2 at cs.uiuc.edu Tue Mar 14 22:04:33 2006 From: alenhar2 at cs.uiuc.edu (Andrew Lenharth) Date: Tue, 14 Mar 2006 22:04:33 -0600 Subject: [llvm-commits] CVS: llvm/lib/Analysis/DataStructure/DataStructure.cpp Message-ID: <200603150404.WAA22656@zion.cs.uiuc.edu> Changes in directory llvm/lib/Analysis/DataStructure: DataStructure.cpp updated: 1.241 -> 1.242 --- Log message: Handle one offset with growth case seen in povray. Namely, if we have an offset, and the offset lands at a field boundary in the old type, construct a new type, copying the fields masked by the offset from the old type, and unify with that. --- Diffs of the changes: (+39 -10) DataStructure.cpp | 49 +++++++++++++++++++++++++++++++++++++++---------- 1 files changed, 39 insertions(+), 10 deletions(-) Index: llvm/lib/Analysis/DataStructure/DataStructure.cpp diff -u llvm/lib/Analysis/DataStructure/DataStructure.cpp:1.241 llvm/lib/Analysis/DataStructure/DataStructure.cpp:1.242 --- llvm/lib/Analysis/DataStructure/DataStructure.cpp:1.241 Sun Jan 22 17:19:18 2006 +++ llvm/lib/Analysis/DataStructure/DataStructure.cpp Tue Mar 14 22:04:21 2006 @@ -492,13 +492,51 @@ return true; } - if (Offset) { // We could handle this case, but we don't for now... + // If this node would have to have an unreasonable number of fields, just + // collapse it. This can occur for fortran common blocks, which have stupid + // things like { [100000000 x double], [1000000 x double] }. + unsigned NumFields = (NewTySize+Offset+DS::PointerSize-1) >> DS::PointerShift; + if (NumFields > 256) { + foldNodeCompletely(); + return true; + } + + if (Offset) { + //handle some common cases: + // Ty: struct { t1, t2, t3, t4, ..., tn} + // NewTy: struct { offset, stuff...} + // try merge with NewTy: struct {t1, t2, stuff...} if offset lands exactly on a field in Ty + if (isa(NewTy) && isa(Ty)) { + DEBUG(std::cerr << "Ty: " << *Ty << "\nNewTy: " << *NewTy << "@" << Offset << "\n"); + unsigned O = 0; + const StructType *STy = cast(Ty); + const StructLayout &SL = *TD.getStructLayout(STy); + unsigned i = SL.getElementContainingOffset(Offset); + //Either we hit it exactly or give up + if (SL.MemberOffsets[i] != Offset) { + if (FoldIfIncompatible) foldNodeCompletely(); + return true; + } + std::vector nt; + for (unsigned x = 0; x < i; ++x) + nt.push_back(STy->getElementType(x)); + STy = cast(NewTy); + nt.insert(nt.end(), STy->element_begin(), STy->element_end()); + //and merge + STy = StructType::get(nt); + DEBUG(std::cerr << "Trying with: " << *STy << "\n"); + return mergeTypeInfo(STy, 0); + } + std::cerr << "UNIMP: Trying to merge a growth type into " << "offset != 0: Collapsing!\n"; + abort(); if (FoldIfIncompatible) foldNodeCompletely(); return true; + } + // Okay, the situation is nice and simple, we are trying to merge a type in // at offset 0 that is bigger than our current type. Implement this by // switching to the new type and then merge in the smaller one, which should @@ -506,15 +544,6 @@ // ok, it will collapse the node as appropriate. // - // If this node would have to have an unreasonable number of fields, just - // collapse it. This can occur for fortran common blocks, which have stupid - // things like { [100000000 x double], [1000000 x double] }. - unsigned NumFields = (NewTySize+DS::PointerSize-1) >> DS::PointerShift; - if (NumFields > 256) { - foldNodeCompletely(); - return true; - } - const Type *OldTy = Ty; Ty = NewTy; NodeType &= ~Array; From natebegeman at mac.com Tue Mar 14 23:25:17 2006 From: natebegeman at mac.com (Nate Begeman) Date: Tue, 14 Mar 2006 23:25:17 -0600 Subject: [llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCInstrInfo.td Message-ID: <200603150525.XAA23040@zion.cs.uiuc.edu> Changes in directory llvm/lib/Target/PowerPC: PPCInstrInfo.td updated: 1.182 -> 1.183 --- Log message: Update scheduling info for vrsave instruction --- Diffs of the changes: (+2 -2) PPCInstrInfo.td | 4 ++-- 1 files changed, 2 insertions(+), 2 deletions(-) Index: llvm/lib/Target/PowerPC/PPCInstrInfo.td diff -u llvm/lib/Target/PowerPC/PPCInstrInfo.td:1.182 llvm/lib/Target/PowerPC/PPCInstrInfo.td:1.183 --- llvm/lib/Target/PowerPC/PPCInstrInfo.td:1.182 Mon Mar 13 15:52:10 2006 +++ llvm/lib/Target/PowerPC/PPCInstrInfo.td Tue Mar 14 23:25:05 2006 @@ -710,10 +710,10 @@ // characteristics as an OR instruction. def MTVRSAVE : XFXForm_7_ext<31, 467, 256, (ops GPRC:$rS), "mtspr 256, $rS", IntGeneral>, - PPC970_Unit_FXU; + PPC970_DGroup_Single, PPC970_Unit_FXU; def MFVRSAVE : XFXForm_1_ext<31, 339, 256, (ops GPRC:$rT), "mfspr $rT, 256", IntGeneral>, - PPC970_Unit_FXU; + PPC970_DGroup_First, PPC970_Unit_FXU; def MFCR : XFXForm_3<31, 19, (ops GPRC:$rT), "mfcr $rT", SprMFCR>, PPC970_MicroCode, PPC970_Unit_CRU; From alenhar2 at cs.uiuc.edu Tue Mar 14 23:43:53 2006 From: alenhar2 at cs.uiuc.edu (Andrew Lenharth) Date: Tue, 14 Mar 2006 23:43:53 -0600 Subject: [llvm-commits] CVS: llvm/lib/Analysis/DataStructure/DataStructure.cpp Message-ID: <200603150543.XAA23316@zion.cs.uiuc.edu> Changes in directory llvm/lib/Analysis/DataStructure: DataStructure.cpp updated: 1.242 -> 1.243 --- Log message: allow field sensitivity to be a tunable parameter --- Diffs of the changes: (+6 -2) DataStructure.cpp | 8 ++++++-- 1 files changed, 6 insertions(+), 2 deletions(-) Index: llvm/lib/Analysis/DataStructure/DataStructure.cpp diff -u llvm/lib/Analysis/DataStructure/DataStructure.cpp:1.242 llvm/lib/Analysis/DataStructure/DataStructure.cpp:1.243 --- llvm/lib/Analysis/DataStructure/DataStructure.cpp:1.242 Tue Mar 14 22:04:21 2006 +++ llvm/lib/Analysis/DataStructure/DataStructure.cpp Tue Mar 14 23:43:41 2006 @@ -39,6 +39,10 @@ Statistic<> NumDNE ("dsa", "Number of nodes removed by reachability"); Statistic<> NumTrivialDNE ("dsa", "Number of nodes trivially removed"); Statistic<> NumTrivialGlobalDNE("dsa", "Number of globals trivially removed"); + static cl::opt + DSAFieldLimit("dsa-field-limit", cl::Hidden, + cl::desc("Number of fields to track before collapsing a node"), + cl::init(256)); }; #if 0 @@ -468,7 +472,7 @@ // collapse it. This can occur for fortran common blocks, which have stupid // things like { [100000000 x double], [1000000 x double] }. unsigned NumFields = (NewTySize+DS::PointerSize-1) >> DS::PointerShift; - if (NumFields > 256) { + if (NumFields > DSAFieldLimit) { foldNodeCompletely(); return true; } @@ -496,7 +500,7 @@ // collapse it. This can occur for fortran common blocks, which have stupid // things like { [100000000 x double], [1000000 x double] }. unsigned NumFields = (NewTySize+Offset+DS::PointerSize-1) >> DS::PointerShift; - if (NumFields > 256) { + if (NumFields > DSAFieldLimit) { foldNodeCompletely(); return true; } From evan.cheng at apple.com Wed Mar 15 12:05:25 2006 From: evan.cheng at apple.com (Evan Cheng) Date: Wed, 15 Mar 2006 12:05:25 -0600 Subject: [llvm-commits] CVS: llvm/test/Regression/CodeGen/X86/fabs.ll fp-immediate-shorten.ll negatize_zero.ll Message-ID: <200603151805.MAA06282@zion.cs.uiuc.edu> Changes in directory llvm/test/Regression/CodeGen/X86: fabs.ll updated: 1.6 -> 1.7 fp-immediate-shorten.ll updated: 1.2 -> 1.3 negatize_zero.ll updated: 1.2 -> 1.3 --- Log message: Also requires -mattr=-sse3 --- Diffs of the changes: (+3 -3) fabs.ll | 2 +- fp-immediate-shorten.ll | 2 +- negatize_zero.ll | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) Index: llvm/test/Regression/CodeGen/X86/fabs.ll diff -u llvm/test/Regression/CodeGen/X86/fabs.ll:1.6 llvm/test/Regression/CodeGen/X86/fabs.ll:1.7 --- llvm/test/Regression/CodeGen/X86/fabs.ll:1.6 Fri Jan 27 15:14:23 2006 +++ llvm/test/Regression/CodeGen/X86/fabs.ll Wed Mar 15 12:05:13 2006 @@ -1,5 +1,5 @@ ; Make sure this testcase codegens to the fabs instruction, not a call to fabsf -; RUN: llvm-as < %s | llc -march=x86 -mattr=-sse2 | grep 'fabs$' | wc -l | grep 2 +; RUN: llvm-as < %s | llc -march=x86 -mattr=-sse2,-sse3 | grep 'fabs$' | wc -l | grep 2 declare float %fabsf(float) Index: llvm/test/Regression/CodeGen/X86/fp-immediate-shorten.ll diff -u llvm/test/Regression/CodeGen/X86/fp-immediate-shorten.ll:1.2 llvm/test/Regression/CodeGen/X86/fp-immediate-shorten.ll:1.3 --- llvm/test/Regression/CodeGen/X86/fp-immediate-shorten.ll:1.2 Fri Jan 27 15:14:23 2006 +++ llvm/test/Regression/CodeGen/X86/fp-immediate-shorten.ll Wed Mar 15 12:05:13 2006 @@ -1,5 +1,5 @@ ;; Test that this FP immediate is stored in the constant pool as a float. -; RUN: llvm-as < %s | llc -march=x86 -mattr=-sse2 | grep '.long.1123418112' +; RUN: llvm-as < %s | llc -march=x86 -mattr=-sse2,-sse3 | grep '.long.1123418112' double %D() { ret double 123.0 } Index: llvm/test/Regression/CodeGen/X86/negatize_zero.ll diff -u llvm/test/Regression/CodeGen/X86/negatize_zero.ll:1.2 llvm/test/Regression/CodeGen/X86/negatize_zero.ll:1.3 --- llvm/test/Regression/CodeGen/X86/negatize_zero.ll:1.2 Fri Jan 27 15:14:23 2006 +++ llvm/test/Regression/CodeGen/X86/negatize_zero.ll Wed Mar 15 12:05:13 2006 @@ -1,4 +1,4 @@ -; RUN: llvm-as < %s | llc -march=x86 -mattr=-sse2 | grep fchs +; RUN: llvm-as < %s | llc -march=x86 -mattr=-sse2,-sse3 | grep fchs double %T() { From alenhar2 at cs.uiuc.edu Wed Mar 15 12:32:30 2006 From: alenhar2 at cs.uiuc.edu (Andrew Lenharth) Date: Wed, 15 Mar 2006 12:32:30 -0600 Subject: [llvm-commits] CVS: llvm/lib/Analysis/DataStructure/Local.cpp Message-ID: <200603151832.MAA22611@zion.cs.uiuc.edu> Changes in directory llvm/lib/Analysis/DataStructure: Local.cpp updated: 1.141 -> 1.142 --- Log message: remove qsort for now --- Diffs of the changes: (+0 -9) Local.cpp | 9 --------- 1 files changed, 9 deletions(-) Index: llvm/lib/Analysis/DataStructure/Local.cpp diff -u llvm/lib/Analysis/DataStructure/Local.cpp:1.141 llvm/lib/Analysis/DataStructure/Local.cpp:1.142 --- llvm/lib/Analysis/DataStructure/Local.cpp:1.141 Tue Mar 14 21:43:59 2006 +++ llvm/lib/Analysis/DataStructure/Local.cpp Wed Mar 15 12:32:18 2006 @@ -988,15 +988,6 @@ N->mergeTypeInfo(Type::DoubleTy, H.getOffset()); } return; - } else if (F->getName() == "qsort") { - CallSite::arg_iterator AI = CS.arg_begin(); - if (DSNode *N = getValueDest(**AI).getNode()) - N->setModifiedMarker(); - //How do you mark a function pointer as being called? Assume it is a read - AI += 3; - if (DSNode *N = getValueDest(**AI).getNode()) - N->setReadMarker(); - return; } else if (F->getName() == "strcat" || F->getName() == "strncat") { //This might be making unsafe assumptions about usage //Merge return and first arg From alenhar2 at cs.uiuc.edu Wed Mar 15 13:03:06 2006 From: alenhar2 at cs.uiuc.edu (Andrew Lenharth) Date: Wed, 15 Mar 2006 13:03:06 -0600 Subject: [llvm-commits] CVS: llvm/test/Regression/Analysis/DSGraph/2004-02-13-memcpy.ll Message-ID: <200603151903.NAA23840@zion.cs.uiuc.edu> Changes in directory llvm/test/Regression/Analysis/DSGraph: 2004-02-13-memcpy.ll updated: 1.2 -> 1.3 --- Log message: better check --- Diffs of the changes: (+15 -3) 2004-02-13-memcpy.ll | 18 +++++++++++++++--- 1 files changed, 15 insertions(+), 3 deletions(-) Index: llvm/test/Regression/Analysis/DSGraph/2004-02-13-memcpy.ll diff -u llvm/test/Regression/Analysis/DSGraph/2004-02-13-memcpy.ll:1.2 llvm/test/Regression/Analysis/DSGraph/2004-02-13-memcpy.ll:1.3 --- llvm/test/Regression/Analysis/DSGraph/2004-02-13-memcpy.ll:1.2 Fri Feb 13 10:09:37 2004 +++ llvm/test/Regression/Analysis/DSGraph/2004-02-13-memcpy.ll Wed Mar 15 13:02:54 2006 @@ -1,6 +1,8 @@ -; RUN: analyze %s -datastructure-gc -dsgc-check-flags=X:SMR +; RUN: analyze %s -datastructure-gc -dsgc-check-flags=Xn:SMR +; RUN: analyze %s -datastructure-gc -dsgc-check-flags=X:SM -declare void %llvm.memcpy(sbyte*, sbyte*, uint, uint) +declare void %llvm.memcpy.i32(sbyte*, sbyte*, uint, uint) +declare void %llvm.memmove.i32(sbyte*, sbyte*, uint, uint) void %test() { %X = alloca int @@ -8,6 +10,16 @@ %x = cast int* %X to sbyte* %y = cast int* %Y to sbyte* store int 4, int* %X - call void %llvm.memcpy(sbyte* %x, sbyte* %y, uint 4, uint 4) + call void %llvm.memcpy.i32(sbyte* %x, sbyte* %y, uint 4, uint 4) + ret void +} + +void %test2() { + %Xn = alloca int + %Yn = alloca int + %xn = cast int* %Xn to sbyte* + %yn = cast int* %Yn to sbyte* + store int 4, int* %Xn + call void %llvm.memmove.i32(sbyte* %xn, sbyte* %yn, uint 4, uint 4) ret void } From alenhar2 at cs.uiuc.edu Wed Mar 15 13:03:28 2006 From: alenhar2 at cs.uiuc.edu (Andrew Lenharth) Date: Wed, 15 Mar 2006 13:03:28 -0600 Subject: [llvm-commits] CVS: llvm/lib/Analysis/DataStructure/Local.cpp Message-ID: <200603151903.NAA23865@zion.cs.uiuc.edu> Changes in directory llvm/lib/Analysis/DataStructure: Local.cpp updated: 1.142 -> 1.143 --- Log message: no heap is happening here --- Diffs of the changes: (+1 -1) Local.cpp | 2 +- 1 files changed, 1 insertion(+), 1 deletion(-) Index: llvm/lib/Analysis/DataStructure/Local.cpp diff -u llvm/lib/Analysis/DataStructure/Local.cpp:1.142 llvm/lib/Analysis/DataStructure/Local.cpp:1.143 --- llvm/lib/Analysis/DataStructure/Local.cpp:1.142 Wed Mar 15 12:32:18 2006 +++ llvm/lib/Analysis/DataStructure/Local.cpp Wed Mar 15 13:03:16 2006 @@ -549,7 +549,7 @@ case Intrinsic::memcpy_i64: { //write first location if (DSNode *N = getValueDest(**CS.arg_begin()).getNode()) - N->setHeapNodeMarker()->setModifiedMarker(); + N->setModifiedMarker(); //and read second pointer if (DSNode *N = getValueDest(**(CS.arg_begin() + 1)).getNode()) N->setReadMarker(); From jlaskey at apple.com Wed Mar 15 13:10:10 2006 From: jlaskey at apple.com (Jim Laskey) Date: Wed, 15 Mar 2006 13:10:10 -0600 Subject: [llvm-commits] CVS: llvm/include/llvm/CodeGen/MachineDebugInfo.h Message-ID: <200603151910.NAA23912@zion.cs.uiuc.edu> Changes in directory llvm/include/llvm/CodeGen: MachineDebugInfo.h updated: 1.29 -> 1.30 --- Log message: Expand subprogram and added block descriptor. --- Diffs of the changes: (+49 -11) MachineDebugInfo.h | 60 +++++++++++++++++++++++++++++++++++++++++++---------- 1 files changed, 49 insertions(+), 11 deletions(-) Index: llvm/include/llvm/CodeGen/MachineDebugInfo.h diff -u llvm/include/llvm/CodeGen/MachineDebugInfo.h:1.29 llvm/include/llvm/CodeGen/MachineDebugInfo.h:1.30 --- llvm/include/llvm/CodeGen/MachineDebugInfo.h:1.29 Thu Mar 9 11:30:53 2006 +++ llvm/include/llvm/CodeGen/MachineDebugInfo.h Wed Mar 15 13:09:58 2006 @@ -55,7 +55,7 @@ // Debug info constants. enum { - LLVMDebugVersion = 1 // Current version of debug information. + LLVMDebugVersion = 2 // Current version of debug information. }; //===----------------------------------------------------------------------===// @@ -274,8 +274,8 @@ private: DebugInfoDesc *Context; // Context debug descriptor. std::string Name; // Type name (may be empty.) - CompileUnitDesc *File; // Declared compile unit (may be NULL.) - int Line; // Declared line# (may be zero.) + CompileUnitDesc *File; // Defined compile unit (may be NULL.) + unsigned Line; // Defined line# (may be zero.) uint64_t Size; // Type bit size (may be zero.) uint64_t Align; // Type bit alignment (may be zero.) uint64_t Offset; // Type bit offset (may be zero.) @@ -287,14 +287,14 @@ DebugInfoDesc *getContext() const { return Context; } const std::string &getName() const { return Name; } CompileUnitDesc *getFile() const { return File; } - int getLine() const { return Line; } + unsigned getLine() const { return Line; } uint64_t getSize() const { return Size; } uint64_t getAlign() const { return Align; } uint64_t getOffset() const { return Offset; } void setContext(DebugInfoDesc *C) { Context = C; } void setName(const std::string &N) { Name = N; } void setFile(CompileUnitDesc *U) { File = U; } - void setLine(int L) { Line = L; } + void setLine(unsigned L) { Line = L; } void setSize(uint64_t S) { Size = S; } void setAlign(uint64_t A) { Align = A; } void setOffset(uint64_t O) { Offset = O; } @@ -504,6 +504,8 @@ private: DebugInfoDesc *Context; // Context debug descriptor. std::string Name; // Global name. + CompileUnitDesc *File; // Defined compile unit (may be NULL.) + unsigned Line; // Defined line# (may be zero.) TypeDesc *TyDesc; // Type debug descriptor. bool IsStatic; // Is the global a static. bool IsDefinition; // Is the global defined in context. @@ -515,11 +517,15 @@ // Accessors DebugInfoDesc *getContext() const { return Context; } const std::string &getName() const { return Name; } + CompileUnitDesc *getFile() const { return File; } + unsigned getLine() const { return Line; } TypeDesc *getTypeDesc() const { return TyDesc; } bool isStatic() const { return IsStatic; } bool isDefinition() const { return IsDefinition; } void setContext(DebugInfoDesc *C) { Context = C; } void setName(const std::string &N) { Name = N; } + void setFile(CompileUnitDesc *U) { File = U; } + void setLine(unsigned L) { Line = L; } void setTypeDesc(TypeDesc *T) { TyDesc = T; } void setIsStatic(bool IS) { IsStatic = IS; } void setIsDefinition(bool ID) { IsDefinition = ID; } @@ -535,16 +541,13 @@ class GlobalVariableDesc : public GlobalDesc { private: GlobalVariable *Global; // llvm global. - unsigned Line; // Source line number. public: GlobalVariableDesc(); // Accessors. GlobalVariable *getGlobalVariable() const { return Global; } - unsigned getLine() const { return Line; } void setGlobalVariable(GlobalVariable *GV) { Global = GV; } - void setLine(unsigned L) { Line = L; } // Implement isa/cast/dyncast. static bool classof(const GlobalVariableDesc *) { return true; } @@ -577,19 +580,20 @@ /// subprogram/function. class SubprogramDesc : public GlobalDesc { private: - // FIXME - Other attributes + std::vector Elements;// Information about args, variables + // and blocks. public: SubprogramDesc(); // Accessors - // FIXME - Other getters/setters. + std::vector &getElements() { return Elements; } // Implement isa/cast/dyncast. static bool classof(const SubprogramDesc *) { return true; } static bool classof(const DebugInfoDesc *D); - /// ApplyToFields - Target the visitor to the fields of the SubprogramDesc. + /// ApplyToFields - Target the visitor to the fields of the SubprogramDesc. /// virtual void ApplyToFields(DIVisitor *Visitor); @@ -612,6 +616,40 @@ }; //===----------------------------------------------------------------------===// +/// BlockDesc - This descriptor groups variables and blocks nested in a block. +/// +class BlockDesc : public DebugInfoDesc { +private: + std::vector Elements;// Information about nested variables + // and blocks. +public: + BlockDesc(); + + // Accessors + std::vector &getElements() { return Elements; } + + // Implement isa/cast/dyncast. + static bool classof(const BlockDesc *) { return true; } + static bool classof(const DebugInfoDesc *D); + + /// ApplyToFields - Target the visitor to the fields of the BlockDesc. + /// + virtual void ApplyToFields(DIVisitor *Visitor); + + /// getDescString - Return a string used to compose global names and labels. + /// + virtual const char *getDescString() const; + + /// getTypeString - Return a string used to label this descriptor's type. + /// + virtual const char *getTypeString() const; + +#ifndef NDEBUG + virtual void dump(); +#endif +}; + +//===----------------------------------------------------------------------===// /// DIDeserializer - This class is responsible for casting GlobalVariables /// into DebugInfoDesc objects. class DIDeserializer { From jlaskey at apple.com Wed Mar 15 13:10:11 2006 From: jlaskey at apple.com (Jim Laskey) Date: Wed, 15 Mar 2006 13:10:11 -0600 Subject: [llvm-commits] CVS: llvm/lib/CodeGen/DwarfWriter.cpp MachineDebugInfo.cpp Message-ID: <200603151910.NAA23918@zion.cs.uiuc.edu> Changes in directory llvm/lib/CodeGen: DwarfWriter.cpp updated: 1.47 -> 1.48 MachineDebugInfo.cpp updated: 1.31 -> 1.32 --- Log message: Expand subprogram and added block descriptor. --- Diffs of the changes: (+79 -29) DwarfWriter.cpp | 14 +++---- MachineDebugInfo.cpp | 94 +++++++++++++++++++++++++++++++++++++++------------ 2 files changed, 79 insertions(+), 29 deletions(-) Index: llvm/lib/CodeGen/DwarfWriter.cpp diff -u llvm/lib/CodeGen/DwarfWriter.cpp:1.47 llvm/lib/CodeGen/DwarfWriter.cpp:1.48 --- llvm/lib/CodeGen/DwarfWriter.cpp:1.47 Thu Mar 9 11:48:46 2006 +++ llvm/lib/CodeGen/DwarfWriter.cpp Wed Mar 15 13:09:58 2006 @@ -1518,19 +1518,19 @@ // Gather the details (simplify add attribute code.) const std::string &Name = SPD->getName(); - unsigned FileID = Unit->getID(); - // FIXME - faking the line for the time being. - unsigned Line = 1; - - // FIXME - faking the type for the time being. - DIE *Type = NewBasicType(Unit->getDie(), Type::IntTy); + CompileUnitDesc *FileDesc = static_cast(SPD->getFile()); + CompileUnit *File = FindCompileUnit(FileDesc); + unsigned FileID = File->getID(); + DIE *Type = NewBasicType(Unit->getDie(), Type::IntTy); + unsigned Line = SPD->getLine(); + unsigned IsExternal = SPD->isStatic() ? 0 : 1; DIE *SubprogramDie = new DIE(DW_TAG_subprogram); SubprogramDie->AddString (DW_AT_name, DW_FORM_string, Name); SubprogramDie->AddUInt (DW_AT_decl_file, 0, FileID); SubprogramDie->AddUInt (DW_AT_decl_line, 0, Line); SubprogramDie->AddDIEntry (DW_AT_type, DW_FORM_ref4, Type); - SubprogramDie->AddUInt (DW_AT_external, DW_FORM_flag, 1); + SubprogramDie->AddUInt (DW_AT_external, DW_FORM_flag, IsExternal); // Add to map. Slot = SubprogramDie; Index: llvm/lib/CodeGen/MachineDebugInfo.cpp diff -u llvm/lib/CodeGen/MachineDebugInfo.cpp:1.31 llvm/lib/CodeGen/MachineDebugInfo.cpp:1.32 --- llvm/lib/CodeGen/MachineDebugInfo.cpp:1.31 Tue Mar 14 12:37:57 2006 +++ llvm/lib/CodeGen/MachineDebugInfo.cpp Wed Mar 15 13:09:58 2006 @@ -270,16 +270,12 @@ Elements.push_back(ConstantBool::get(Field)); } virtual void Apply(std::string &Field) { - if (Field.empty()) { - Elements.push_back(NULL); - } else { Elements.push_back(SR.getString(Field)); - } } virtual void Apply(DebugInfoDesc *&Field) { GlobalVariable *GV = NULL; - // If non-NULL the convert to global. + // If non-NULL then convert to global. if (Field) GV = SR.Serialize(Field); // FIXME - At some point should use specific type. @@ -473,19 +469,21 @@ case DW_TAG_compile_unit: return new CompileUnitDesc(); case DW_TAG_variable: return new GlobalVariableDesc(); case DW_TAG_subprogram: return new SubprogramDesc(); + case DW_TAG_lexical_block: return new BlockDesc(); case DW_TAG_base_type: return new BasicTypeDesc(); case DW_TAG_typedef: - case DW_TAG_pointer_type: + case DW_TAG_pointer_type: case DW_TAG_reference_type: case DW_TAG_const_type: - case DW_TAG_volatile_type: - case DW_TAG_restrict_type: return new DerivedTypeDesc(Tag); + case DW_TAG_volatile_type: + case DW_TAG_restrict_type: + case DW_TAG_formal_parameter: + case DW_TAG_member: return new DerivedTypeDesc(Tag); case DW_TAG_array_type: case DW_TAG_structure_type: case DW_TAG_union_type: case DW_TAG_enumeration_type: return new CompositeTypeDesc(Tag); case DW_TAG_subrange_type: return new SubrangeDesc(); - case DW_TAG_member: return new DerivedTypeDesc(DW_TAG_member); case DW_TAG_enumerator: return new EnumeratorDesc(); default: break; } @@ -761,6 +759,7 @@ case DW_TAG_const_type: case DW_TAG_volatile_type: case DW_TAG_restrict_type: + case DW_TAG_formal_parameter: case DW_TAG_member: return true; default: break; @@ -948,6 +947,8 @@ : AnchoredDesc(T) , Context(0) , Name("") +, File(NULL) +, Line(0) , TyDesc(NULL) , IsStatic(false) , IsDefinition(false) @@ -960,6 +961,8 @@ Visitor->Apply(Context); Visitor->Apply(Name); + Visitor->Apply((DebugInfoDesc *&)File); + Visitor->Apply(Line); Visitor->Apply((DebugInfoDesc *&)TyDesc); Visitor->Apply(IsStatic); Visitor->Apply(IsDefinition); @@ -983,7 +986,6 @@ GlobalDesc::ApplyToFields(Visitor); Visitor->Apply(Global); - Visitor->Apply(Line); } /// getDescString - Return a string used to compose global names and labels. @@ -1011,11 +1013,12 @@ << "Tag(" << getTag() << "), " << "Anchor(" << getAnchor() << "), " << "Name(\"" << getName() << "\"), " + << "File(" << getFile() << ")," + << "Line(" << getLine() << ")," << "Type(\"" << getTypeDesc() << "\"), " << "IsStatic(" << (isStatic() ? "true" : "false") << "), " << "IsDefinition(" << (isDefinition() ? "true" : "false") << "), " - << "Global(" << Global << "), " - << "Line(" << Line << ")\n"; + << "Global(" << Global << ")\n"; } #endif @@ -1034,6 +1037,8 @@ /// SubprogramDesc. void SubprogramDesc::ApplyToFields(DIVisitor *Visitor) { GlobalDesc::ApplyToFields(Visitor); + + Visitor->Apply(Elements); } /// getDescString - Return a string used to compose global names and labels. @@ -1061,6 +1066,8 @@ << "Tag(" << getTag() << "), " << "Anchor(" << getAnchor() << "), " << "Name(\"" << getName() << "\"), " + << "File(" << getFile() << ")," + << "Line(" << getLine() << ")," << "Type(\"" << getTypeDesc() << "\"), " << "IsStatic(" << (isStatic() ? "true" : "false") << "), " << "IsDefinition(" << (isDefinition() ? "true" : "false") << ")\n"; @@ -1069,6 +1076,44 @@ //===----------------------------------------------------------------------===// +BlockDesc::BlockDesc() +: DebugInfoDesc(DW_TAG_lexical_block) +{} + +// Implement isa/cast/dyncast. +bool BlockDesc::classof(const DebugInfoDesc *D) { + return D->getTag() == DW_TAG_lexical_block; +} + +/// ApplyToFields - Target the visitor to the fields of the BlockDesc. +/// +void BlockDesc::ApplyToFields(DIVisitor *Visitor) { + DebugInfoDesc::ApplyToFields(Visitor); + + Visitor->Apply(Elements); +} + +/// getDescString - Return a string used to compose global names and labels. +/// +const char *BlockDesc::getDescString() const { + return "llvm.dbg.block"; +} + +/// getTypeString - Return a string used to label this descriptors type. +/// +const char *BlockDesc::getTypeString() const { + return "llvm.dbg.block.type"; +} + +#ifndef NDEBUG +void BlockDesc::dump() { + std::cerr << getDescString() << " " + << "Tag(" << getTag() << ")\n"; +} +#endif + +//===----------------------------------------------------------------------===// + DebugInfoDesc *DIDeserializer::Deserialize(Value *V) { return Deserialize(getGlobalVariable(V)); } @@ -1159,17 +1204,22 @@ Constant *DISerializer::getString(const std::string &String) { // Check string cache for previous edition. Constant *&Slot = StringCache[String]; - // return Constant if previously defined. + // Return Constant if previously defined. if (Slot) return Slot; - // Construct string as an llvm constant. - Constant *ConstStr = ConstantArray::get(String); - // Otherwise create and return a new string global. - GlobalVariable *StrGV = new GlobalVariable(ConstStr->getType(), true, - GlobalVariable::InternalLinkage, - ConstStr, "str", M); - StrGV->setSection("llvm.metadata"); - // Convert to generic string pointer. - Slot = ConstantExpr::getCast(StrGV, getStrPtrType()); + // If empty string then use a sbyte* null instead. + if (String.empty()) { + Slot = ConstantPointerNull::get(getStrPtrType()); + } else { + // Construct string as an llvm constant. + Constant *ConstStr = ConstantArray::get(String); + // Otherwise create and return a new string global. + GlobalVariable *StrGV = new GlobalVariable(ConstStr->getType(), true, + GlobalVariable::InternalLinkage, + ConstStr, "str", M); + StrGV->setSection("llvm.metadata"); + // Convert to generic string pointer. + Slot = ConstantExpr::getCast(StrGV, getStrPtrType()); + } return Slot; } From jlaskey at apple.com Wed Mar 15 13:11:04 2006 From: jlaskey at apple.com (Jim Laskey) Date: Wed, 15 Mar 2006 13:11:04 -0600 Subject: [llvm-commits] CVS: llvm/docs/SourceLevelDebugging.html Message-ID: <200603151911.NAA23964@zion.cs.uiuc.edu> Changes in directory llvm/docs: SourceLevelDebugging.html updated: 1.14 -> 1.15 --- Log message: Update doc to reflect changes in subprogram and block descriptors. --- Diffs of the changes: (+56 -24) SourceLevelDebugging.html | 80 ++++++++++++++++++++++++++++++++-------------- 1 files changed, 56 insertions(+), 24 deletions(-) Index: llvm/docs/SourceLevelDebugging.html diff -u llvm/docs/SourceLevelDebugging.html:1.14 llvm/docs/SourceLevelDebugging.html:1.15 --- llvm/docs/SourceLevelDebugging.html:1.14 Tue Mar 14 12:50:50 2006 +++ llvm/docs/SourceLevelDebugging.html Wed Mar 15 13:10:52 2006 @@ -26,6 +26,7 @@
  • Compile unit descriptors
  • Global variable descriptors
  • Subprogram descriptors
    • +
  • Block descriptors
  • Basic type descriptors
  • Derived type descriptors
  • Composite type descriptors
    • @@ -126,7 +127,7 @@

    When a program is being debugged, a debugger interacts with the user and turns the stored debug information into source-language specific information. -As such, the debugger must be aware of the source-language, and is thus tied to +As such, a debugger must be aware of the source-language, and is thus tied to a specific language of family of languages.

    @@ -175,7 +176,7 @@

    Basically, the debug information allows you to compile a program with "-O0 -g" and get full debug information, allowing you to arbitrarily -modify the program as it executes from the debugger. Compiling a program with +modify the program as it executes from a debugger. Compiling a program with "-O3 -g" gives you full debug information that is always available and accurate for reading (e.g., you get accurate stack traces despite tail call elimination and inlining), but you might lose the ability to modify the program @@ -225,7 +226,7 @@ these to a minimum. The only common features that the LLVM debugger assumes exist are source files, and program objects. These abstract objects are -used by the debugger to form stack traces, show information about local +used by a debugger to form stack traces, show information about local variables, etc.

    This section of the documentation first describes the representation aspects @@ -297,7 +298,7 @@ scan the program. To do this, all of the global objects use "anchor" descriptors with designated names. All of the global objects of a particular type (e.g., compile units) contain a pointer to the anchor. This pointer allows -the debugger to use def-use chains to find all global objects of that type.

    +a debugger to use def-use chains to find all global objects of that type.

    The following names are recognized as anchors by LLVM:

    @@ -327,7 +328,7 @@ %llvm.dbg.compile_unit.type = type { uint, ;; Tag = 17 (DW_TAG_compile_unit) { }*, ;; Compile unit anchor = cast = (%llvm.dbg.anchor.type* %llvm.dbg.compile_units to { }*) - uint, ;; LLVM debug version number = 1 + uint, ;; LLVM debug version number = 2 uint, ;; Dwarf language identifier (ex. DW_LANG_C89) sbyte*, ;; Source file name sbyte*, ;; Source file directory (includes trailing slash) @@ -336,7 +337,7 @@

    These descriptors contain the version number for the debug info (currently -1), a source language ID for the file (we use the Dwarf 3.0 ID numbers, such as +2), a source language ID for the file (we use the Dwarf 3.0 ID numbers, such as DW_LANG_C89, DW_LANG_C_plus_plus, DW_LANG_Cobol74, etc), three strings describing the filename, working directory of the compiler, and an identifier string for the compiler that produced it.

    @@ -359,13 +360,14 @@ %llvm.dbg.global_variable.type = type { uint, ;; Tag = 52 (DW_TAG_variable) { }*, ;; Global variable anchor = cast (%llvm.dbg.anchor.type* %llvm.dbg.global_variables to { }*), - { }*, ;; Reference to compile unit + { }*, ;; Reference to context descriptor sbyte*, ;; Name + { }*, ;; Reference to compile unit where defined + int, ;; Line number where defined { }*, ;; Reference to type descriptor bool, ;; True if the global is local to compile unit (static) bool, ;; True if the global is defined in the compile unit (not extern) - { }*, ;; Reference to the global variable - uint ;; Line number in compile unit where variable is defined + { }* ;; Reference to the global variable } @@ -385,20 +387,43 @@ %llvm.dbg.subprogram.type = type { uint, ;; Tag = 46 (DW_TAG_subprogram) { }*, ;; Subprogram anchor = cast (%llvm.dbg.anchor.type* %llvm.dbg.subprograms to { }*), - { }*, ;; Reference to compile unit + { }*, ;; Reference to context descriptor sbyte*, ;; Name + { }*, ;; Reference to compile unit where defined + int, ;; Line number where defined { }*, ;; Reference to type descriptor bool, ;; True if the global is local to compile unit (static) - bool ;; True if the global is defined in the compile unit (not extern) - TODO - MORE TO COME + bool, ;; True if the global is defined in the compile unit (not extern) + { }* ;; Reference to array of member descriptors } -

    These descriptors provide debug information about functions, methods and subprograms. The provide details such as name, return and argument types and where the subprogram is defined.

    +

    The array of member descriptors is used to define arguments local variables +and nested blocks.

    + +
    + +
    + Block descriptors +
    + +
    + +
    +  %llvm.dbg.block = type {
+    uint,   ;; Tag = 13 (DW_TAG_lexical_block)
+    {  }*   ;; Reference to array of member descriptors
+  }
+
    + +

    These descriptors provide debug information about nested blocks within a +subprogram. The array of member descriptors is used to define local variables +and deeper nested blocks.

    +
    @@ -473,6 +498,7 @@ tag values;

    +  DW_TAG_formal_parameter = 5
   DW_TAG_member = 13
   DW_TAG_pointer_type = 15
   DW_TAG_reference_type = 16
@@ -483,8 +509,10 @@

    DW_TAG_member is used to define a member of a composite type. The type of the member is the -derived type.

    +href="#format_composite_type">composite type or subprogram. The type of the member is the derived type. DW_TAG_formal_parameter +is used to define a member which is a formal argument of a subprogram.

    DW_TAG_typedef is used to provide a name for the derived type.

    @@ -720,8 +748,8 @@ href="#debugopt">debugging optimized code. The basic idea is that the front-end inserts calls to the %llvm.dbg.stoppoint intrinsic -function at every point in the program where the debugger should be able to -inspect the program (these correspond to places the debugger stops when you +function at every point in the program where a debugger should be able to +inspect the program (these correspond to places a debugger stops when you "step" through it). The front-end can choose to place these as fine-grained as it would like (for example, before every subexpression evaluated), but it is recommended to only put them after every source statement @@ -841,7 +869,7 @@ drawn between LLVM functions and their source-level counterparts (note however, that if the inliner inlines all instances of a non-strong-linkage function into its caller that it will not be possible for the user to manually invoke the -inlined function from the debugger).

    +inlined function from a debugger).

    Once the function has been defined, the stopping point corresponding to @@ -990,7 +1018,7 @@ ;; compile unit. ;; %llvm.dbg.anchor.type = type { uint, uint } -%llvm.dbg.global_variable.type = type { uint, { }*, { }*, sbyte*, { }*, bool, bool, { }*, uint } +%llvm.dbg.global_variable.type = type { uint, { }*, { }*, sbyte*, { }*, uint, { }*, bool, bool, { }*, uint } %llvm.dbg.basictype.type = type { uint, { }*, sbyte*, { }*, int, uint, uint, uint, uint } %llvm.dbg.compile_unit.type = ... ... @@ -1015,11 +1043,12 @@ { }* cast (%llvm.dbg.anchor.type* %llvm.dbg.global_variables to { }*), { }* cast (%llvm.dbg.compile_unit.type* %llvm.dbg.compile_unit to { }*), sbyte* getelementptr ([9 x sbyte]* %str1, int 0, int 0), + { }* cast (%llvm.dbg.compile_unit.type* %llvm.dbg.compile_unit to { }*), + uint 1, { }* cast (%llvm.dbg.basictype.type* %llvm.dbg.basictype to { }*), bool false, bool true, - { }* cast (int* %MyGlobal to { }*), - uint 1 }, section "llvm.metadata" + { }* cast (int* %MyGlobal to { }*) }, section "llvm.metadata" ;; ;; Define the basic type of 32 bit signed integer. Note that since int is an @@ -1068,7 +1097,7 @@ ;; descriptor, one for the global's basic type and one for the subprogram's ;; compile unit. ;; -%llvm.dbg.subprogram.type = type { uint, { }*, { }*, sbyte*, { }*, bool, bool } +%llvm.dbg.subprogram.type = type { uint, { }*, { }*, sbyte*, { }*, bool, bool, { }* } %llvm.dbg.anchor.type = type { uint, uint } %llvm.dbg.compile_unit.type = ... @@ -1087,9 +1116,12 @@ { }* cast (%llvm.dbg.anchor.type* %llvm.dbg.subprograms to { }*), { }* cast (%llvm.dbg.compile_unit.type* %llvm.dbg.compile_unit to { }*), sbyte* getelementptr ([5 x sbyte]* %str1, int 0, int 0), + { }* cast (%llvm.dbg.compile_unit.type* %llvm.dbg.compile_unit to { }*), + uint 1, { }* null, bool false, - bool true }, section "llvm.metadata" + bool true, + null }, section "llvm.metadata" ;; ;; Define the name of the subprogram. @@ -1639,7 +1671,7 @@ Chris Lattner
    LLVM Compiler Infrastructure
    - Last modified: $Date: 2006/03/14 18:50:50 $ + Last modified: $Date: 2006/03/15 19:10:52 $ From lattner at cs.uiuc.edu Wed Mar 15 13:15:38 2006 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Wed, 15 Mar 2006 13:15:38 -0600 Subject: [llvm-commits] CVS: llvm/utils/TableGen/IntrinsicEmitter.cpp Message-ID: <200603151915.NAA24086@zion.cs.uiuc.edu> Changes in directory llvm/utils/TableGen: IntrinsicEmitter.cpp updated: 1.13 -> 1.14 --- Log message: allow the GCCBuiltinName field to be optional --- Diffs of the changes: (+2 -1) IntrinsicEmitter.cpp | 3 ++- 1 files changed, 2 insertions(+), 1 deletion(-) Index: llvm/utils/TableGen/IntrinsicEmitter.cpp diff -u llvm/utils/TableGen/IntrinsicEmitter.cpp:1.13 llvm/utils/TableGen/IntrinsicEmitter.cpp:1.14 --- llvm/utils/TableGen/IntrinsicEmitter.cpp:1.13 Tue Mar 14 20:51:05 2006 +++ llvm/utils/TableGen/IntrinsicEmitter.cpp Wed Mar 15 13:15:26 2006 @@ -34,7 +34,8 @@ std::string(DefName.begin(), DefName.begin()+4) != "int_") throw "Intrinsic '" + DefName + "' does not start with 'int_'!"; EnumName = std::string(DefName.begin()+4, DefName.end()); - GCCBuiltinName = R->getValueAsString("GCCBuiltinName"); + if (R->getValue("GCCBuiltinName")) // Ignore a missing GCCBuiltinName field. + GCCBuiltinName = R->getValueAsString("GCCBuiltinName"); TargetPrefix = R->getValueAsString("TargetPrefix"); Name = R->getValueAsString("LLVMName"); if (Name == "") { From lattner at cs.uiuc.edu Wed Mar 15 13:22:53 2006 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Wed, 15 Mar 2006 13:22:53 -0600 Subject: [llvm-commits] CVS: llvm/lib/Transforms/IPO/StripSymbols.cpp Message-ID: <200603151922.NAA24213@zion.cs.uiuc.edu> Changes in directory llvm/lib/Transforms/IPO: StripSymbols.cpp updated: 1.6 -> 1.7 --- Log message: Teach the strip pass to strip type names in addition to value names. This is fallout from the type/value split in the symtab long long ago :) --- Diffs of the changes: (+5 -0) StripSymbols.cpp | 5 +++++ 1 files changed, 5 insertions(+) Index: llvm/lib/Transforms/IPO/StripSymbols.cpp diff -u llvm/lib/Transforms/IPO/StripSymbols.cpp:1.6 llvm/lib/Transforms/IPO/StripSymbols.cpp:1.7 --- llvm/lib/Transforms/IPO/StripSymbols.cpp:1.6 Mon Mar 13 07:07:37 2006 +++ llvm/lib/Transforms/IPO/StripSymbols.cpp Wed Mar 15 13:22:41 2006 @@ -84,6 +84,11 @@ I->setName(""); // Internal symbols can't participate in linkage I->getSymbolTable().strip(); } + + // Remove all names from types. + SymbolTable &SymTab = M.getSymbolTable(); + while (SymTab.type_begin() != SymTab.type_end()) + SymTab.remove(SymTab.type_begin()); } // Strip debug info in the module if it exists. To do this, we remove From lattner at cs.uiuc.edu Wed Mar 15 13:23:52 2006 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Wed, 15 Mar 2006 13:23:52 -0600 Subject: [llvm-commits] CVS: llvm/include/llvm/Intrinsics.td Message-ID: <200603151923.NAA24283@zion.cs.uiuc.edu> Changes in directory llvm/include/llvm: Intrinsics.td updated: 1.9 -> 1.10 --- Log message: minor changes so that GCC builtin can be specified before the Intrinsic info, add some more PPC intrinsics. --- Diffs of the changes: (+14 -4) Intrinsics.td | 18 ++++++++++++++---- 1 files changed, 14 insertions(+), 4 deletions(-) Index: llvm/include/llvm/Intrinsics.td diff -u llvm/include/llvm/Intrinsics.td:1.9 llvm/include/llvm/Intrinsics.td:1.10 --- llvm/include/llvm/Intrinsics.td:1.9 Tue Mar 14 19:32:36 2006 +++ llvm/include/llvm/Intrinsics.td Wed Mar 15 13:23:40 2006 @@ -96,7 +96,6 @@ list properties = [], string name = ""> { string LLVMName = name; - string GCCBuiltinName = ""; string TargetPrefix = ""; // Set to a prefix for target-specific intrinsics. list Types = types; list Properties = properties; @@ -215,7 +214,18 @@ // PowerPC Intrinsics // let TargetPrefix = "ppc" in { // All intrinsics start with "llvm.ppc.". - def int_ppc_altivec_lvx : Intrinsic<[llvm_v4i32_ty, llvm_int_ty, llvm_ptr_ty], - [IntrReadMem]>, - GCCBuiltin<"__builtin_altivec_lvx">; + def int_ppc_altivec_lvx : GCCBuiltin<"__builtin_altivec_lvx">, + Intrinsic<[llvm_v4i32_ty, llvm_int_ty, llvm_ptr_ty], + [IntrReadMem]>; + def int_ppc_altivec_stvx : GCCBuiltin<"__builtin_altivec_stvx">, + Intrinsic<[llvm_void_ty, llvm_v4i32_ty, llvm_int_ty, llvm_ptr_ty], + [IntrWriteMem]>; + + def int_ppc_altivec_vmaddfp : GCCBuiltin<"__builtin_altivec_vmaddfp">, + Intrinsic<[llvm_v4f32_ty, llvm_v4f32_ty, + llvm_v4f32_ty, llvm_v4f32_ty], [InstrNoMem]>; + def int_ppc_altivec_vadduwm : GCCBuiltin<"__builtin_altivec_vadduwm">, + Intrinsic<[llvm_v4i32_ty, llvm_v4i32_ty, llvm_v4i32_ty], + [InstrNoMem]>; + } From lattner at cs.uiuc.edu Wed Mar 15 16:19:30 2006 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Wed, 15 Mar 2006 16:19:30 -0600 Subject: [llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp Message-ID: <200603152219.QAA26186@zion.cs.uiuc.edu> Changes in directory llvm/lib/CodeGen/SelectionDAG: LegalizeDAG.cpp updated: 1.314 -> 1.315 --- Log message: Add a note, this code should be moved to the dag combiner. --- Diffs of the changes: (+1 -0) LegalizeDAG.cpp | 1 + 1 files changed, 1 insertion(+) Index: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp diff -u llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.314 llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.315 --- llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.314 Mon Mar 13 00:08:38 2006 +++ llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp Wed Mar 15 16:19:18 2006 @@ -1260,6 +1260,7 @@ // Turn 'store float 1.0, Ptr' -> 'store int 0x12345678, Ptr' // FIXME: We shouldn't do this for TargetConstantFP's. + // FIXME: move this to the DAG Combiner! if (ConstantFPSDNode *CFP =dyn_cast(Node->getOperand(1))){ if (CFP->getValueType(0) == MVT::f32) { Tmp3 = DAG.getConstant(FloatToBits(CFP->getValue()), MVT::i32); From lattner at cs.uiuc.edu Wed Mar 15 16:19:58 2006 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Wed, 15 Mar 2006 16:19:58 -0600 Subject: [llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp SelectionDAGISel.cpp Message-ID: <200603152219.QAA26223@zion.cs.uiuc.edu> Changes in directory llvm/lib/CodeGen/SelectionDAG: SelectionDAG.cpp updated: 1.269 -> 1.270 SelectionDAGISel.cpp updated: 1.188 -> 1.189 --- Log message: add support for vector->vector casts --- Diffs of the changes: (+79 -35) SelectionDAG.cpp | 4 - SelectionDAGISel.cpp | 110 +++++++++++++++++++++++++++++++++++---------------- 2 files changed, 79 insertions(+), 35 deletions(-) Index: llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp diff -u llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp:1.269 llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp:1.270 --- llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp:1.269 Sun Mar 5 17:57:58 2006 +++ llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp Wed Mar 15 16:19:46 2006 @@ -1086,8 +1086,8 @@ break; case ISD::BIT_CONVERT: // Basic sanity checking. - assert(MVT::getSizeInBits(VT)==MVT::getSizeInBits(Operand.getValueType()) && - "Cannot BIT_CONVERT between two different types!"); + assert(MVT::getSizeInBits(VT) == MVT::getSizeInBits(Operand.getValueType()) + && "Cannot BIT_CONVERT between two different types!"); if (VT == Operand.getValueType()) return Operand; // noop conversion. if (OpOpcode == ISD::BIT_CONVERT) // bitconv(bitconv(x)) -> bitconv(x) return getNode(ISD::BIT_CONVERT, VT, Operand.getOperand(0)); Index: llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp diff -u llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.188 llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.189 --- llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.188 Mon Mar 13 07:07:37 2006 +++ llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp Wed Mar 15 16:19:46 2006 @@ -362,6 +362,9 @@ void setCurrentBasicBlock(MachineBasicBlock *MBB) { CurMBB = MBB; } + SDOperand getLoadFrom(const Type *Ty, SDOperand Ptr, + SDOperand SrcValue, SDOperand Root, + bool isVolatile); SDOperand getIntPtrConstant(uint64_t Val) { return DAG.getConstant(Val, TLI.getPointerTy()); @@ -726,42 +729,78 @@ void SelectionDAGLowering::visitCast(User &I) { SDOperand N = getValue(I.getOperand(0)); - MVT::ValueType SrcTy = TLI.getValueType(I.getOperand(0)->getType()); - MVT::ValueType DestTy = TLI.getValueType(I.getType()); + MVT::ValueType SrcVT = TLI.getValueType(I.getOperand(0)->getType()); + MVT::ValueType DestVT = TLI.getValueType(I.getType()); - if (N.getValueType() == DestTy) { + if (N.getValueType() == DestVT) { setValue(&I, N); // noop cast. - } else if (DestTy == MVT::i1) { + } else if (DestVT == MVT::i1) { // Cast to bool is a comparison against zero, not truncation to zero. - SDOperand Zero = isInteger(SrcTy) ? DAG.getConstant(0, N.getValueType()) : + SDOperand Zero = isInteger(SrcVT) ? DAG.getConstant(0, N.getValueType()) : DAG.getConstantFP(0.0, N.getValueType()); setValue(&I, DAG.getSetCC(MVT::i1, N, Zero, ISD::SETNE)); - } else if (isInteger(SrcTy)) { - if (isInteger(DestTy)) { // Int -> Int cast - if (DestTy < SrcTy) // Truncating cast? - setValue(&I, DAG.getNode(ISD::TRUNCATE, DestTy, N)); + } else if (isInteger(SrcVT)) { + if (isInteger(DestVT)) { // Int -> Int cast + if (DestVT < SrcVT) // Truncating cast? + setValue(&I, DAG.getNode(ISD::TRUNCATE, DestVT, N)); else if (I.getOperand(0)->getType()->isSigned()) - setValue(&I, DAG.getNode(ISD::SIGN_EXTEND, DestTy, N)); + setValue(&I, DAG.getNode(ISD::SIGN_EXTEND, DestVT, N)); else - setValue(&I, DAG.getNode(ISD::ZERO_EXTEND, DestTy, N)); + setValue(&I, DAG.getNode(ISD::ZERO_EXTEND, DestVT, N)); } else { // Int -> FP cast if (I.getOperand(0)->getType()->isSigned()) - setValue(&I, DAG.getNode(ISD::SINT_TO_FP, DestTy, N)); + setValue(&I, DAG.getNode(ISD::SINT_TO_FP, DestVT, N)); else - setValue(&I, DAG.getNode(ISD::UINT_TO_FP, DestTy, N)); + setValue(&I, DAG.getNode(ISD::UINT_TO_FP, DestVT, N)); } - } else { - assert(isFloatingPoint(SrcTy) && "Unknown value type!"); - if (isFloatingPoint(DestTy)) { // FP -> FP cast - if (DestTy < SrcTy) // Rounding cast? - setValue(&I, DAG.getNode(ISD::FP_ROUND, DestTy, N)); + } else if (isFloatingPoint(SrcVT)) { + if (isFloatingPoint(DestVT)) { // FP -> FP cast + if (DestVT < SrcVT) // Rounding cast? + setValue(&I, DAG.getNode(ISD::FP_ROUND, DestVT, N)); else - setValue(&I, DAG.getNode(ISD::FP_EXTEND, DestTy, N)); + setValue(&I, DAG.getNode(ISD::FP_EXTEND, DestVT, N)); } else { // FP -> Int cast. if (I.getType()->isSigned()) - setValue(&I, DAG.getNode(ISD::FP_TO_SINT, DestTy, N)); + setValue(&I, DAG.getNode(ISD::FP_TO_SINT, DestVT, N)); else - setValue(&I, DAG.getNode(ISD::FP_TO_UINT, DestTy, N)); + setValue(&I, DAG.getNode(ISD::FP_TO_UINT, DestVT, N)); + } + } else { + const PackedType *SrcTy = cast(I.getOperand(0)->getType()); + const PackedType *DstTy = cast(I.getType()); + + unsigned SrcNumElements = SrcTy->getNumElements(); + MVT::ValueType SrcPVT = TLI.getValueType(SrcTy->getElementType()); + MVT::ValueType SrcTVT = MVT::getVectorType(SrcPVT, SrcNumElements); + + unsigned DstNumElements = DstTy->getNumElements(); + MVT::ValueType DstPVT = TLI.getValueType(DstTy->getElementType()); + MVT::ValueType DstTVT = MVT::getVectorType(DstPVT, DstNumElements); + + // If the input and output type are legal, convert this to a bit convert of + // the SrcTVT/DstTVT types. + if (SrcTVT != MVT::Other && DstTVT != MVT::Other && + TLI.isTypeLegal(SrcTVT) && TLI.isTypeLegal(DstTVT)) { + assert(N.getValueType() == SrcTVT); + setValue(&I, DAG.getNode(ISD::BIT_CONVERT, DstTVT, N)); + } else { + // Otherwise, convert this directly into a store/load. + // FIXME: add a VBIT_CONVERT node that we could use to automatically turn + // 8xFloat -> 8xInt casts into two 4xFloat -> 4xInt casts. + // Create the stack frame object. + uint64_t ByteSize = TD.getTypeSize(SrcTy); + assert(ByteSize == TD.getTypeSize(DstTy) && "Not a bit_convert!"); + MachineFrameInfo *FrameInfo = DAG.getMachineFunction().getFrameInfo(); + int FrameIdx = FrameInfo->CreateStackObject(ByteSize, ByteSize); + SDOperand FIPtr = DAG.getFrameIndex(FrameIdx, TLI.getPointerTy()); + + // Emit a store to the stack slot. + SDOperand Store = DAG.getNode(ISD::STORE, MVT::Other, DAG.getEntryNode(), + N, FIPtr, DAG.getSrcValue(NULL)); + // Result is a load from the stack slot. + SDOperand Val = + getLoadFrom(DstTy, FIPtr, DAG.getSrcValue(NULL), Store, false); + setValue(&I, Val); } } } @@ -893,8 +932,14 @@ // Do not serialize non-volatile loads against each other. Root = DAG.getRoot(); } - - const Type *Ty = I.getType(); + + setValue(&I, getLoadFrom(I.getType(), Ptr, DAG.getSrcValue(I.getOperand(0)), + Root, I.isVolatile())); +} + +SDOperand SelectionDAGLowering::getLoadFrom(const Type *Ty, SDOperand Ptr, + SDOperand SrcValue, SDOperand Root, + bool isVolatile) { SDOperand L; if (const PackedType *PTy = dyn_cast(Ty)) { @@ -905,24 +950,23 @@ // Immediately scalarize packed types containing only one element, so that // the Legalize pass does not have to deal with them. if (NumElements == 1) { - L = DAG.getLoad(PVT, Root, Ptr, DAG.getSrcValue(I.getOperand(0))); - } else if (TVT != MVT::Other && - TLI.isTypeLegal(TVT) && TLI.isOperationLegal(ISD::LOAD, TVT)) { - L = DAG.getLoad(TVT, Root, Ptr, DAG.getSrcValue(I.getOperand(0))); + L = DAG.getLoad(PVT, Root, Ptr, SrcValue); + } else if (TVT != MVT::Other && TLI.isTypeLegal(TVT) && + TLI.isOperationLegal(ISD::LOAD, TVT)) { + L = DAG.getLoad(TVT, Root, Ptr, SrcValue); } else { - L = DAG.getVecLoad(NumElements, PVT, Root, Ptr, - DAG.getSrcValue(I.getOperand(0))); + L = DAG.getVecLoad(NumElements, PVT, Root, Ptr, SrcValue); } } else { - L = DAG.getLoad(TLI.getValueType(Ty), Root, Ptr, - DAG.getSrcValue(I.getOperand(0))); + L = DAG.getLoad(TLI.getValueType(Ty), Root, Ptr, SrcValue); } - setValue(&I, L); - if (I.isVolatile()) + if (isVolatile) DAG.setRoot(L.getValue(1)); else PendingLoads.push_back(L.getValue(1)); + + return L; } From lattner at cs.uiuc.edu Wed Mar 15 19:30:04 2006 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Wed, 15 Mar 2006 19:30:04 -0600 Subject: [llvm-commits] CVS: llvm/lib/Target/TargetSelectionDAG.td Message-ID: <200603160130.TAA27237@zion.cs.uiuc.edu> Changes in directory llvm/lib/Target: TargetSelectionDAG.td updated: 1.51 -> 1.52 --- Log message: add support for the bitconvert node --- Diffs of the changes: (+3 -0) TargetSelectionDAG.td | 3 +++ 1 files changed, 3 insertions(+) Index: llvm/lib/Target/TargetSelectionDAG.td diff -u llvm/lib/Target/TargetSelectionDAG.td:1.51 llvm/lib/Target/TargetSelectionDAG.td:1.52 --- llvm/lib/Target/TargetSelectionDAG.td:1.51 Thu Mar 9 11:47:22 2006 +++ llvm/lib/Target/TargetSelectionDAG.td Wed Mar 15 19:29:53 2006 @@ -74,6 +74,8 @@ def SDTPtrLeaf: SDTypeProfile<1, 0, [SDTCisPtrTy<0>]>; // for '&g'. def SDTOther : SDTypeProfile<1, 0, [SDTCisVT<0, OtherVT>]>; // for 'vt'. def SDTUNDEF : SDTypeProfile<1, 0, []>; // for 'undef'. +def SDTUnaryOp : SDTypeProfile<1, 1, []>; // bitconvert + def SDTIntBinOp : SDTypeProfile<1, 2, [ // add, and, or, xor, udiv, etc. SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisInt<0> ]>; @@ -251,6 +253,7 @@ def zext : SDNode<"ISD::ZERO_EXTEND", SDTIntExtendOp>; def anyext : SDNode<"ISD::ANY_EXTEND" , SDTIntExtendOp>; def trunc : SDNode<"ISD::TRUNCATE" , SDTIntTruncOp>; +def bitconvert : SDNode<"ISD::BIT_CONVERT", SDTUnaryOp>; def fadd : SDNode<"ISD::FADD" , SDTFPBinOp, [SDNPCommutative]>; def fsub : SDNode<"ISD::FSUB" , SDTFPBinOp>; From reid at x10sys.com Wed Mar 15 21:06:10 2006 From: reid at x10sys.com (Reid Spencer) Date: Wed, 15 Mar 2006 21:06:10 -0600 Subject: [llvm-commits] CVS: llvm/test/Regression/C++Frontend/2006-03-06-C++RecurseCrash.cpp Message-ID: <200603160306.VAA27676@zion.cs.uiuc.edu> Changes in directory llvm/test/Regression/C++Frontend: 2006-03-06-C++RecurseCrash.cpp updated: 1.1 -> 1.2 --- Log message: Add a RUN: line so this test doesn't fail. --- Diffs of the changes: (+1 -1) 2006-03-06-C++RecurseCrash.cpp | 2 +- 1 files changed, 1 insertion(+), 1 deletion(-) Index: llvm/test/Regression/C++Frontend/2006-03-06-C++RecurseCrash.cpp diff -u llvm/test/Regression/C++Frontend/2006-03-06-C++RecurseCrash.cpp:1.1 llvm/test/Regression/C++Frontend/2006-03-06-C++RecurseCrash.cpp:1.2 --- llvm/test/Regression/C++Frontend/2006-03-06-C++RecurseCrash.cpp:1.1 Mon Mar 6 17:52:37 2006 +++ llvm/test/Regression/C++Frontend/2006-03-06-C++RecurseCrash.cpp Wed Mar 15 21:05:57 2006 @@ -1,4 +1,4 @@ -// %llvmgcc %s -S -o - +// RUN: %llvmgcc %s -S -o - namespace std { class exception { }; From lattner at cs.uiuc.edu Thu Mar 16 10:15:11 2006 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Thu, 16 Mar 2006 10:15:11 -0600 Subject: [llvm-commits] CVS: llvm/docs/Projects.html Message-ID: <200603161615.KAA11159@zion.cs.uiuc.edu> Changes in directory llvm/docs: Projects.html updated: 1.20 -> 1.21 --- Log message: Fix a typo Eric van Riet Paap noticed --- Diffs of the changes: (+2 -2) Projects.html | 4 ++-- 1 files changed, 2 insertions(+), 2 deletions(-) Index: llvm/docs/Projects.html diff -u llvm/docs/Projects.html:1.20 llvm/docs/Projects.html:1.21 --- llvm/docs/Projects.html:1.20 Mon Mar 13 23:39:39 2006 +++ llvm/docs/Projects.html Thu Mar 16 10:14:59 2006 @@ -100,7 +100,7 @@

    • AC_INIT. Place the name of your project, its version number and a contact email address for your project as the arguments to this macro
      • -
    • AC_CONFIG_AUC_DIR. If your project isn't in the +
    • AC_CONFIG_AUX_DIR. If your project isn't in the llvm/projects directory then you might need to adjust this so that it specifies a relative path to the llvm/autoconf directory.
    • LLVM_CONFIG_PROJECT. Just leave this alone.
      • @@ -453,7 +453,7 @@ John Criswell
      The LLVM Compiler Infrastructure
      - Last modified: $Date: 2006/03/14 05:39:39 $ + Last modified: $Date: 2006/03/16 16:14:59 $ From jlaskey at apple.com Thu Mar 16 12:15:23 2006 From: jlaskey at apple.com (Jim Laskey) Date: Thu, 16 Mar 2006 12:15:23 -0600 Subject: [llvm-commits] CVS: llvm/include/llvm/IntrinsicInst.h Message-ID: <200603161815.MAA12255@zion.cs.uiuc.edu> Changes in directory llvm/include/llvm: IntrinsicInst.h updated: 1.11 -> 1.12 --- Log message: Typo. --- Diffs of the changes: (+1 -1) IntrinsicInst.h | 2 +- 1 files changed, 1 insertion(+), 1 deletion(-) Index: llvm/include/llvm/IntrinsicInst.h diff -u llvm/include/llvm/IntrinsicInst.h:1.11 llvm/include/llvm/IntrinsicInst.h:1.12 --- llvm/include/llvm/IntrinsicInst.h:1.11 Thu Mar 9 14:01:20 2006 +++ llvm/include/llvm/IntrinsicInst.h Thu Mar 16 12:15:12 2006 @@ -1,4 +1,4 @@ -//===-- llvm/InstrinsicInst.h - Intrinsic Instruction Wrappers --*- C++ -*-===// +//===-- llvm/IntrinsicInst.h - Intrinsic Instruction Wrappers ---*- C++ -*-===// // // The LLVM Compiler Infrastructure // From lattner at cs.uiuc.edu Thu Mar 16 12:25:35 2006 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Thu, 16 Mar 2006 12:25:35 -0600 Subject: [llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp Message-ID: <200603161825.MAA12338@zion.cs.uiuc.edu> Changes in directory llvm/lib/Target/PowerPC: PPCISelDAGToDAG.cpp updated: 1.167 -> 1.168 --- Log message: Save/restore VRSAVE once per function, not once per block. --- Diffs of the changes: (+52 -39) PPCISelDAGToDAG.cpp | 91 +++++++++++++++++++++++++++++----------------------- 1 files changed, 52 insertions(+), 39 deletions(-) Index: llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp diff -u llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp:1.167 llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp:1.168 --- llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp:1.167 Tue Mar 14 11:56:49 2006 +++ llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp Thu Mar 16 12:25:23 2006 @@ -39,17 +39,21 @@ /// instructions for SelectionDAG operations. /// class PPCDAGToDAGISel : public SelectionDAGISel { + PPCTargetMachine &TM; PPCTargetLowering PPCLowering; unsigned GlobalBaseReg; public: - PPCDAGToDAGISel(PPCTargetMachine &TM) - : SelectionDAGISel(PPCLowering), - PPCLowering(*TM.getTargetLowering()){} + PPCDAGToDAGISel(PPCTargetMachine &tm) + : SelectionDAGISel(PPCLowering), TM(tm), + PPCLowering(*TM.getTargetLowering()) {} virtual bool runOnFunction(Function &Fn) { // Make sure we re-emit a set of the global base reg if necessary GlobalBaseReg = 0; - return SelectionDAGISel::runOnFunction(Fn); + SelectionDAGISel::runOnFunction(Fn); + + InsertVRSaveCode(Fn); + return true; } /// getI32Imm - Return a target constant with the specified value, of type @@ -121,6 +125,8 @@ /// SelectionDAGISel when it has created a SelectionDAG for us to codegen. virtual void InstructionSelectBasicBlock(SelectionDAG &DAG); + void InsertVRSaveCode(Function &Fn); + virtual const char *getPassName() const { return "PowerPC DAG->DAG Pattern Instruction Selection"; } @@ -199,13 +205,19 @@ // Emit machine code to BB. ScheduleAndEmitDAG(DAG); - +} + +/// InsertVRSaveCode - Once the entire function has been instruction selected, +/// all virtual registers are created and all machine instructions are built, +/// check to see if we need to save/restore VRSAVE. If so, do it. +void PPCDAGToDAGISel::InsertVRSaveCode(Function &F) { // Check to see if this function uses vector registers, which means we have to // save and restore the VRSAVE register and update it with the regs we use. // // In this case, there will be virtual registers of vector type type created // by the scheduler. Detect them now. - SSARegMap *RegMap = DAG.getMachineFunction().getSSARegMap(); + MachineFunction &Fn = MachineFunction::get(&F); + SSARegMap *RegMap = Fn.getSSARegMap(); bool HasVectorVReg = false; for (unsigned i = MRegisterInfo::FirstVirtualRegister, e = RegMap->getLastVirtReg()+1; i != e; ++i) @@ -213,7 +225,8 @@ HasVectorVReg = true; break; } - + if (!HasVectorVReg) return; // nothing to do. + // If we have a vector register, we want to emit code into the entry and exit // blocks to save and restore the VRSAVE register. We do this here (instead // of marking all vector instructions as clobbering VRSAVE) for two reasons: @@ -223,41 +236,41 @@ // 2. This (more significantly) allows us to create a temporary virtual // register to hold the saved VRSAVE value, allowing this temporary to be // register allocated, instead of forcing it to be spilled to the stack. - if (HasVectorVReg) { - // Create two vregs - one to hold the VRSAVE register that is live-in to the - // function and one for the value after having bits or'd into it. - unsigned InVRSAVE = RegMap->createVirtualRegister(&PPC::GPRCRegClass); - unsigned UpdatedVRSAVE = RegMap->createVirtualRegister(&PPC::GPRCRegClass); - - MachineFunction &MF = DAG.getMachineFunction(); - MachineBasicBlock &EntryBB = *MF.begin(); - // Emit the following code into the entry block: - // InVRSAVE = MFVRSAVE - // UpdatedVRSAVE = UPDATE_VRSAVE InVRSAVE - // MTVRSAVE UpdatedVRSAVE - MachineBasicBlock::iterator IP = EntryBB.begin(); // Insert Point - BuildMI(EntryBB, IP, PPC::MFVRSAVE, 0, InVRSAVE); - BuildMI(EntryBB, IP, PPC::UPDATE_VRSAVE, 1, UpdatedVRSAVE).addReg(InVRSAVE); - BuildMI(EntryBB, IP, PPC::MTVRSAVE, 1).addReg(UpdatedVRSAVE); - - // Find all return blocks, outputting a restore in each epilog. - const TargetInstrInfo &TII = *DAG.getTarget().getInstrInfo(); - for (MachineFunction::iterator BB = MF.begin(), E = MF.end(); BB != E; ++BB) - if (!BB->empty() && TII.isReturn(BB->back().getOpcode())) { - IP = BB->end(); --IP; - - // Skip over all terminator instructions, which are part of the return - // sequence. - MachineBasicBlock::iterator I2 = IP; - while (I2 != BB->begin() && TII.isTerminatorInstr((--I2)->getOpcode())) - IP = I2; - - // Emit: MTVRSAVE InVRSave - BuildMI(*BB, IP, PPC::MTVRSAVE, 1).addReg(InVRSAVE); - } + + // Create two vregs - one to hold the VRSAVE register that is live-in to the + // function and one for the value after having bits or'd into it. + unsigned InVRSAVE = RegMap->createVirtualRegister(&PPC::GPRCRegClass); + unsigned UpdatedVRSAVE = RegMap->createVirtualRegister(&PPC::GPRCRegClass); + + MachineBasicBlock &EntryBB = *Fn.begin(); + // Emit the following code into the entry block: + // InVRSAVE = MFVRSAVE + // UpdatedVRSAVE = UPDATE_VRSAVE InVRSAVE + // MTVRSAVE UpdatedVRSAVE + MachineBasicBlock::iterator IP = EntryBB.begin(); // Insert Point + BuildMI(EntryBB, IP, PPC::MFVRSAVE, 0, InVRSAVE); + BuildMI(EntryBB, IP, PPC::UPDATE_VRSAVE, 1, UpdatedVRSAVE).addReg(InVRSAVE); + BuildMI(EntryBB, IP, PPC::MTVRSAVE, 1).addReg(UpdatedVRSAVE); + + // Find all return blocks, outputting a restore in each epilog. + const TargetInstrInfo &TII = *TM.getInstrInfo(); + for (MachineFunction::iterator BB = Fn.begin(), E = Fn.end(); BB != E; ++BB) { + if (!BB->empty() && TII.isReturn(BB->back().getOpcode())) { + IP = BB->end(); --IP; + + // Skip over all terminator instructions, which are part of the return + // sequence. + MachineBasicBlock::iterator I2 = IP; + while (I2 != BB->begin() && TII.isTerminatorInstr((--I2)->getOpcode())) + IP = I2; + + // Emit: MTVRSAVE InVRSave + BuildMI(*BB, IP, PPC::MTVRSAVE, 1).addReg(InVRSAVE); + } } } + /// getGlobalBaseReg - Output the instructions required to put the /// base address to use for accessing globals into a register. /// From lattner at cs.uiuc.edu Thu Mar 16 12:48:03 2006 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Thu, 16 Mar 2006 12:48:03 -0600 Subject: [llvm-commits] CVS: llvm/test/Regression/CFrontend/2006-03-16-VectorCtor.c Message-ID: <200603161848.MAA12483@zion.cs.uiuc.edu> Changes in directory llvm/test/Regression/CFrontend: 2006-03-16-VectorCtor.c added (r1.1) --- Log message: New testcase, the new CFE compiles this into insertelement instructions, the old one crashes. --- Diffs of the changes: (+11 -0) 2006-03-16-VectorCtor.c | 11 +++++++++++ 1 files changed, 11 insertions(+) Index: llvm/test/Regression/CFrontend/2006-03-16-VectorCtor.c diff -c /dev/null llvm/test/Regression/CFrontend/2006-03-16-VectorCtor.c:1.1 *** /dev/null Thu Mar 16 12:48:01 2006 --- llvm/test/Regression/CFrontend/2006-03-16-VectorCtor.c Thu Mar 16 12:47:51 2006 *************** *** 0 **** --- 1,11 ---- + // Passes with the new CFE. + // RUN: %llvmgcc %s -S -o - + // XFAIL: * + + typedef int v4si __attribute__ ((__vector_size__ (16))); + void test(v4si *P, v4si *Q, float X) { + *P = (v4si){ X, X, X, X } * *Q; + } + + v4si G = (v4si){ 0.1, 1.2, 4.2, 17.2 }; + From natebegeman at mac.com Thu Mar 16 12:50:56 2006 From: natebegeman at mac.com (Nate Begeman) Date: Thu, 16 Mar 2006 12:50:56 -0600 Subject: [llvm-commits] CVS: llvm/lib/Target/PowerPC/README.txt Message-ID: <200603161850.MAA12509@zion.cs.uiuc.edu> Changes in directory llvm/lib/Target/PowerPC: README.txt updated: 1.70 -> 1.71 --- Log message: Another case we could do better on. --- Diffs of the changes: (+11 -0) README.txt | 11 +++++++++++ 1 files changed, 11 insertions(+) Index: llvm/lib/Target/PowerPC/README.txt diff -u llvm/lib/Target/PowerPC/README.txt:1.70 llvm/lib/Target/PowerPC/README.txt:1.71 --- llvm/lib/Target/PowerPC/README.txt:1.70 Tue Mar 7 18:25:47 2006 +++ llvm/lib/Target/PowerPC/README.txt Thu Mar 16 12:50:44 2006 @@ -507,3 +507,14 @@ ===-------------------------------------------------------------------------=== +int foo(int N, int ***W, int **TK, int X) { + int t, i; + + for (t = 0; t < N; ++t) + for (i = 0; i < 4; ++i) + W[t / X][i][t % X] = TK[i][t]; + + return 5; +} + +We generate relatively atrocious code for this loop compared to gcc. \ No newline at end of file From lattner at cs.uiuc.edu Thu Mar 16 13:02:32 2006 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Thu, 16 Mar 2006 13:02:32 -0600 Subject: [llvm-commits] CVS: llvm-www/Features.html OpenProjects.html Oversight.html header.incl Message-ID: <200603161902.NAA12642@zion.cs.uiuc.edu> Changes in directory llvm-www: Features.html updated: 1.15 -> 1.16 OpenProjects.html updated: 1.11 -> 1.12 Oversight.html updated: 1.4 -> 1.5 header.incl updated: 1.44 -> 1.45 --- Log message: llvm.cs -> llvm.org --- Diffs of the changes: (+0 -0) 0 files changed From lattner at cs.uiuc.edu Thu Mar 16 13:42:56 2006 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Thu, 16 Mar 2006 13:42:56 -0600 Subject: [llvm-commits] CVS: llvm/include/llvm/CodeGen/ValueTypes.h Message-ID: <200603161942.NAA12928@zion.cs.uiuc.edu> Changes in directory llvm/include/llvm/CodeGen: ValueTypes.h updated: 1.21 -> 1.22 --- Log message: Add markers for the first and last vector value type. --- Diffs of the changes: (+6 -2) ValueTypes.h | 8 ++++++-- 1 files changed, 6 insertions(+), 2 deletions(-) Index: llvm/include/llvm/CodeGen/ValueTypes.h diff -u llvm/include/llvm/CodeGen/ValueTypes.h:1.21 llvm/include/llvm/CodeGen/ValueTypes.h:1.22 --- llvm/include/llvm/CodeGen/ValueTypes.h:1.21 Thu Mar 2 19:55:49 2006 +++ llvm/include/llvm/CodeGen/ValueTypes.h Thu Mar 16 13:42:44 2006 @@ -48,6 +48,7 @@ Vector = 13, // This is an abstract vector type, which will // be expanded into a target vector type, or scalars // if no matching vector type is available. + v8i8 = 14, // 8 x i8 v4i16 = 15, // 4 x i16 v2i32 = 16, // 2 x i32 @@ -59,8 +60,10 @@ v2f32 = 21, // 2 x f32 v4f32 = 22, // 4 x f32 v2f64 = 23, // 2 x f64 + FIRST_VECTOR_VALUETYPE = v8i8, + LAST_VECTOR_VALUETYPE = v2f64, - LAST_VALUETYPE // This always remains at the end of the list. + LAST_VALUETYPE = 24 // This always remains at the end of the list. }; static inline bool isInteger(ValueType VT) { @@ -70,7 +73,8 @@ return (VT >= f32 && VT <= f128) || (VT >= v4f32 && VT <= v2f64); } static inline bool isVector(ValueType VT) { - return (VT >= v8i8 && VT <= v2f64); + return (VT >= FIRST_VECTOR_VALUETYPE && + VT <= LAST_VECTOR_VALUETYPE); } /// getVectorType - Returns the ValueType that represents a vector NumElements From lattner at cs.uiuc.edu Thu Mar 16 13:50:14 2006 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Thu, 16 Mar 2006 13:50:14 -0600 Subject: [llvm-commits] CVS: llvm/lib/Target/TargetLowering.cpp Message-ID: <200603161950.NAA13039@zion.cs.uiuc.edu> Changes in directory llvm/lib/Target: TargetLowering.cpp updated: 1.46 -> 1.47 --- Log message: set TransformToType correctly for vector types. --- Diffs of the changes: (+8 -0) TargetLowering.cpp | 8 ++++++++ 1 files changed, 8 insertions(+) Index: llvm/lib/Target/TargetLowering.cpp diff -u llvm/lib/Target/TargetLowering.cpp:1.46 llvm/lib/Target/TargetLowering.cpp:1.47 --- llvm/lib/Target/TargetLowering.cpp:1.46 Mon Mar 13 17:16:31 2006 +++ llvm/lib/Target/TargetLowering.cpp Thu Mar 16 13:50:01 2006 @@ -124,6 +124,14 @@ // Set MVT::Vector to always be Expanded SetValueTypeAction(MVT::Vector, Expand, *this, TransformToType, ValueTypeActions); + + // Loop over all of the legal vector value types, specifying an identity type + // transformation. + for (unsigned i = MVT::FIRST_VECTOR_VALUETYPE; + i != MVT::LAST_VECTOR_VALUETYPE; ++i) { + if (isTypeLegal((MVT::ValueType)i)) + TransformToType[i] = (MVT::ValueType)i; + } assert(isTypeLegal(MVT::f64) && "Target does not support FP?"); TransformToType[MVT::f64] = MVT::f64; From lattner at cs.uiuc.edu Thu Mar 16 13:51:30 2006 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Thu, 16 Mar 2006 13:51:30 -0600 Subject: [llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp Message-ID: <200603161951.NAA13100@zion.cs.uiuc.edu> Changes in directory llvm/lib/CodeGen/SelectionDAG: SelectionDAGISel.cpp updated: 1.189 -> 1.190 --- Log message: Teach CreateRegForValue how to handle vector types. --- Diffs of the changes: (+53 -23) SelectionDAGISel.cpp | 76 +++++++++++++++++++++++++++++++++++---------------- 1 files changed, 53 insertions(+), 23 deletions(-) Index: llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp diff -u llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.189 llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.190 --- llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.189 Wed Mar 15 16:19:46 2006 +++ llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp Thu Mar 16 13:51:18 2006 @@ -171,28 +171,8 @@ return RegMap->createVirtualRegister(TLI.getRegClassFor(VT)); } - unsigned CreateRegForValue(const Value *V) { - MVT::ValueType VT = TLI.getValueType(V->getType()); - // The common case is that we will only create one register for this - // value. If we have that case, create and return the virtual register. - unsigned NV = TLI.getNumElements(VT); - if (NV == 1) { - // If we are promoting this value, pick the next largest supported type. - return MakeReg(TLI.getTypeToTransformTo(VT)); - } - - // If this value is represented with multiple target registers, make sure - // to create enough consecutive registers of the right (smaller) type. - unsigned NT = VT-1; // Find the type to use. - while (TLI.getNumElements((MVT::ValueType)NT) != 1) - --NT; - - unsigned R = MakeReg((MVT::ValueType)NT); - for (unsigned i = 1; i != NV; ++i) - MakeReg((MVT::ValueType)NT); - return R; - } - + unsigned CreateRegForValue(const Value *V); + unsigned InitializeRegForValue(const Value *V) { unsigned &R = ValueMap[V]; assert(R == 0 && "Already initialized this value register!"); @@ -290,7 +270,57 @@ } } - +/// CreateRegForValue - Allocate the appropriate number of virtual registers of +/// the correctly promoted or expanded types. Assign these registers +/// consecutive vreg numbers and return the first assigned number. +unsigned FunctionLoweringInfo::CreateRegForValue(const Value *V) { + MVT::ValueType VT = TLI.getValueType(V->getType()); + + // The number of multiples of registers that we need, to, e.g., split up + // a <2 x int64> -> 4 x i32 registers. + unsigned NumVectorRegs = 1; + + // If this is a packed type, figure out what type it will decompose into + // and how many of the elements it will use. + if (VT == MVT::Vector) { + const PackedType *PTy = cast(V->getType()); + unsigned NumElts = PTy->getNumElements(); + MVT::ValueType EltTy = TLI.getValueType(PTy->getElementType()); + + // Divide the input until we get to a supported size. This will always + // end with a scalar if the target doesn't support vectors. + while (NumElts > 1 && !TLI.isTypeLegal(getVectorType(EltTy, NumElts))) { + NumElts >>= 1; + NumVectorRegs <<= 1; + } + VT = getVectorType(EltTy, NumElts); + } + + // The common case is that we will only create one register for this + // value. If we have that case, create and return the virtual register. + unsigned NV = TLI.getNumElements(VT); + if (NV == 1) { + // If we are promoting this value, pick the next largest supported type. + MVT::ValueType PromotedType = TLI.getTypeToTransformTo(VT); + unsigned Reg = MakeReg(PromotedType); + // If this is a vector of supported or promoted types (e.g. 4 x i16), + // create all of the registers. + for (unsigned i = 1; i != NumVectorRegs; ++i) + MakeReg(PromotedType); + return Reg; + } + + // If this value is represented with multiple target registers, make sure + // to create enough consecutive registers of the right (smaller) type. + unsigned NT = VT-1; // Find the type to use. + while (TLI.getNumElements((MVT::ValueType)NT) != 1) + --NT; + + unsigned R = MakeReg((MVT::ValueType)NT); + for (unsigned i = 1; i != NV*NumVectorRegs; ++i) + MakeReg((MVT::ValueType)NT); + return R; +} //===----------------------------------------------------------------------===// /// SelectionDAGLowering - This is the common target-independent lowering From lattner at cs.uiuc.edu Thu Mar 16 13:58:02 2006 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Thu, 16 Mar 2006 13:58:02 -0600 Subject: [llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp Message-ID: <200603161958.NAA13244@zion.cs.uiuc.edu> Changes in directory llvm/lib/CodeGen/SelectionDAG: SelectionDAGISel.cpp updated: 1.190 -> 1.191 --- Log message: Add support for CopyFromReg from vector values. Note: this doesn't support illegal vector types yet! --- Diffs of the changes: (+119 -104) SelectionDAGISel.cpp | 223 +++++++++++++++++++++++++++------------------------ 1 files changed, 119 insertions(+), 104 deletions(-) Index: llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp diff -u llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.190 llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.191 --- llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.190 Thu Mar 16 13:51:18 2006 +++ llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp Thu Mar 16 13:57:50 2006 @@ -400,110 +400,7 @@ return DAG.getConstant(Val, TLI.getPointerTy()); } - SDOperand getValue(const Value *V) { - SDOperand &N = NodeMap[V]; - if (N.Val) return N; - - const Type *VTy = V->getType(); - MVT::ValueType VT = TLI.getValueType(VTy); - if (Constant *C = const_cast(dyn_cast(V))) - if (ConstantExpr *CE = dyn_cast(C)) { - visit(CE->getOpcode(), *CE); - assert(N.Val && "visit didn't populate the ValueMap!"); - return N; - } else if (GlobalValue *GV = dyn_cast(C)) { - return N = DAG.getGlobalAddress(GV, VT); - } else if (isa(C)) { - return N = DAG.getConstant(0, TLI.getPointerTy()); - } else if (isa(C)) { - return N = DAG.getNode(ISD::UNDEF, VT); - } else if (ConstantFP *CFP = dyn_cast(C)) { - return N = DAG.getConstantFP(CFP->getValue(), VT); - } else if (const PackedType *PTy = dyn_cast(VTy)) { - unsigned NumElements = PTy->getNumElements(); - MVT::ValueType PVT = TLI.getValueType(PTy->getElementType()); - MVT::ValueType TVT = MVT::getVectorType(PVT, NumElements); - - // Now that we know the number and type of the elements, push a - // Constant or ConstantFP node onto the ops list for each element of - // the packed constant. - std::vector Ops; - if (ConstantPacked *CP = dyn_cast(C)) { - if (MVT::isFloatingPoint(PVT)) { - for (unsigned i = 0; i != NumElements; ++i) { - const ConstantFP *El = cast(CP->getOperand(i)); - Ops.push_back(DAG.getConstantFP(El->getValue(), PVT)); - } - } else { - for (unsigned i = 0; i != NumElements; ++i) { - const ConstantIntegral *El = - cast(CP->getOperand(i)); - Ops.push_back(DAG.getConstant(El->getRawValue(), PVT)); - } - } - } else { - assert(isa(C) && "Unknown packed constant!"); - SDOperand Op; - if (MVT::isFloatingPoint(PVT)) - Op = DAG.getConstantFP(0, PVT); - else - Op = DAG.getConstant(0, PVT); - Ops.assign(NumElements, Op); - } - - // Handle the case where we have a 1-element vector, in which - // case we want to immediately turn it into a scalar constant. - if (Ops.size() == 1) { - return N = Ops[0]; - } else if (TVT != MVT::Other && TLI.isTypeLegal(TVT)) { - return N = DAG.getNode(ISD::ConstantVec, TVT, Ops); - } else { - // If the packed type isn't legal, then create a ConstantVec node with - // generic Vector type instead. - SDOperand Num = DAG.getConstant(NumElements, MVT::i32); - SDOperand Typ = DAG.getValueType(PVT); - Ops.insert(Ops.begin(), Typ); - Ops.insert(Ops.begin(), Num); - return N = DAG.getNode(ISD::VConstant, MVT::Vector, Ops); - } - } else { - // Canonicalize all constant ints to be unsigned. - return N = DAG.getConstant(cast(C)->getRawValue(),VT); - } - - if (const AllocaInst *AI = dyn_cast(V)) { - std::map::iterator SI = - FuncInfo.StaticAllocaMap.find(AI); - if (SI != FuncInfo.StaticAllocaMap.end()) - return DAG.getFrameIndex(SI->second, TLI.getPointerTy()); - } - - std::map::const_iterator VMI = - FuncInfo.ValueMap.find(V); - assert(VMI != FuncInfo.ValueMap.end() && "Value not in map!"); - - unsigned InReg = VMI->second; - - // If this type is not legal, make it so now. - MVT::ValueType DestVT = TLI.getTypeToTransformTo(VT); - - N = DAG.getCopyFromReg(DAG.getEntryNode(), InReg, DestVT); - if (DestVT < VT) { - // Source must be expanded. This input value is actually coming from the - // register pair VMI->second and VMI->second+1. - N = DAG.getNode(ISD::BUILD_PAIR, VT, N, - DAG.getCopyFromReg(DAG.getEntryNode(), InReg+1, DestVT)); - } else { - if (DestVT > VT) { // Promotion case - if (MVT::isFloatingPoint(VT)) - N = DAG.getNode(ISD::FP_ROUND, VT, N); - else - N = DAG.getNode(ISD::TRUNCATE, VT, N); - } - } - - return N; - } + SDOperand getValue(const Value *V); const SDOperand &setValue(const Value *V, SDOperand NewN) { SDOperand &N = NodeMap[V]; @@ -599,6 +496,124 @@ }; } // end namespace llvm +SDOperand SelectionDAGLowering::getValue(const Value *V) { + SDOperand &N = NodeMap[V]; + if (N.Val) return N; + + const Type *VTy = V->getType(); + MVT::ValueType VT = TLI.getValueType(VTy); + if (Constant *C = const_cast(dyn_cast(V))) { + if (ConstantExpr *CE = dyn_cast(C)) { + visit(CE->getOpcode(), *CE); + assert(N.Val && "visit didn't populate the ValueMap!"); + return N; + } else if (GlobalValue *GV = dyn_cast(C)) { + return N = DAG.getGlobalAddress(GV, VT); + } else if (isa(C)) { + return N = DAG.getConstant(0, TLI.getPointerTy()); + } else if (isa(C)) { + return N = DAG.getNode(ISD::UNDEF, VT); + } else if (ConstantFP *CFP = dyn_cast(C)) { + return N = DAG.getConstantFP(CFP->getValue(), VT); + } else if (const PackedType *PTy = dyn_cast(VTy)) { + unsigned NumElements = PTy->getNumElements(); + MVT::ValueType PVT = TLI.getValueType(PTy->getElementType()); + MVT::ValueType TVT = MVT::getVectorType(PVT, NumElements); + + // Now that we know the number and type of the elements, push a + // Constant or ConstantFP node onto the ops list for each element of + // the packed constant. + std::vector Ops; + if (ConstantPacked *CP = dyn_cast(C)) { + if (MVT::isFloatingPoint(PVT)) { + for (unsigned i = 0; i != NumElements; ++i) { + const ConstantFP *El = cast(CP->getOperand(i)); + Ops.push_back(DAG.getConstantFP(El->getValue(), PVT)); + } + } else { + for (unsigned i = 0; i != NumElements; ++i) { + const ConstantIntegral *El = + cast(CP->getOperand(i)); + Ops.push_back(DAG.getConstant(El->getRawValue(), PVT)); + } + } + } else { + assert(isa(C) && "Unknown packed constant!"); + SDOperand Op; + if (MVT::isFloatingPoint(PVT)) + Op = DAG.getConstantFP(0, PVT); + else + Op = DAG.getConstant(0, PVT); + Ops.assign(NumElements, Op); + } + + // Handle the case where we have a 1-element vector, in which + // case we want to immediately turn it into a scalar constant. + if (Ops.size() == 1) { + return N = Ops[0]; + } else if (TVT != MVT::Other && TLI.isTypeLegal(TVT)) { + return N = DAG.getNode(ISD::ConstantVec, TVT, Ops); + } else { + // If the packed type isn't legal, then create a ConstantVec node with + // generic Vector type instead. + SDOperand Num = DAG.getConstant(NumElements, MVT::i32); + SDOperand Typ = DAG.getValueType(PVT); + Ops.insert(Ops.begin(), Typ); + Ops.insert(Ops.begin(), Num); + return N = DAG.getNode(ISD::VConstant, MVT::Vector, Ops); + } + } else { + // Canonicalize all constant ints to be unsigned. + return N = DAG.getConstant(cast(C)->getRawValue(),VT); + } + } + + if (const AllocaInst *AI = dyn_cast(V)) { + std::map::iterator SI = + FuncInfo.StaticAllocaMap.find(AI); + if (SI != FuncInfo.StaticAllocaMap.end()) + return DAG.getFrameIndex(SI->second, TLI.getPointerTy()); + } + + std::map::const_iterator VMI = + FuncInfo.ValueMap.find(V); + assert(VMI != FuncInfo.ValueMap.end() && "Value not in map!"); + + unsigned InReg = VMI->second; + + // If this type is not legal, make it so now. + if (VT == MVT::Vector) { + // FIXME: We only handle legal vectors right now. We need a VBUILD_VECTOR + const PackedType *PTy = cast(VTy); + unsigned NumElements = PTy->getNumElements(); + MVT::ValueType PVT = TLI.getValueType(PTy->getElementType()); + MVT::ValueType TVT = MVT::getVectorType(PVT, NumElements); + assert(TLI.isTypeLegal(TVT) && + "FIXME: Cannot handle illegal vector types here yet!"); + VT = TVT; + } + + MVT::ValueType DestVT = TLI.getTypeToTransformTo(VT); + + N = DAG.getCopyFromReg(DAG.getEntryNode(), InReg, DestVT); + if (DestVT < VT) { + // Source must be expanded. This input value is actually coming from the + // register pair VMI->second and VMI->second+1. + N = DAG.getNode(ISD::BUILD_PAIR, VT, N, + DAG.getCopyFromReg(DAG.getEntryNode(), InReg+1, DestVT)); + } else { + if (DestVT > VT) { // Promotion case + if (MVT::isFloatingPoint(VT)) + N = DAG.getNode(ISD::FP_ROUND, VT, N); + else + N = DAG.getNode(ISD::TRUNCATE, VT, N); + } + } + + return N; +} + + void SelectionDAGLowering::visitRet(ReturnInst &I) { if (I.getNumOperands() == 0) { DAG.setRoot(DAG.getNode(ISD::RET, MVT::Other, getRoot())); From lattner at cs.uiuc.edu Thu Mar 16 14:04:09 2006 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Thu, 16 Mar 2006 14:04:09 -0600 Subject: [llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCInstrInfo.cpp PPCInstrInfo.td PPCRegisterInfo.cpp Message-ID: <200603162004.OAA13493@zion.cs.uiuc.edu> Changes in directory llvm/lib/Target/PowerPC: PPCInstrInfo.cpp updated: 1.17 -> 1.18 PPCInstrInfo.td updated: 1.183 -> 1.184 PPCRegisterInfo.cpp updated: 1.44 -> 1.45 --- Log message: Add support for copying registers. still needed: spilling and reloading them --- Diffs of the changes: (+7 -1) PPCInstrInfo.cpp | 2 +- PPCInstrInfo.td | 4 ++++ PPCRegisterInfo.cpp | 2 ++ 3 files changed, 7 insertions(+), 1 deletion(-) Index: llvm/lib/Target/PowerPC/PPCInstrInfo.cpp diff -u llvm/lib/Target/PowerPC/PPCInstrInfo.cpp:1.17 llvm/lib/Target/PowerPC/PPCInstrInfo.cpp:1.18 --- llvm/lib/Target/PowerPC/PPCInstrInfo.cpp:1.17 Sun Mar 5 17:49:55 2006 +++ llvm/lib/Target/PowerPC/PPCInstrInfo.cpp Thu Mar 16 14:03:58 2006 @@ -25,7 +25,7 @@ unsigned& sourceReg, unsigned& destReg) const { MachineOpCode oc = MI.getOpcode(); - if (oc == PPC::OR4 || oc == PPC::OR8 || + if (oc == PPC::OR4 || oc == PPC::OR8 || oc == PPC::VOR || oc == PPC::OR4To8 || oc == PPC::OR8To4) { // or r1, r2, r2 assert(MI.getNumOperands() == 3 && MI.getOperand(0).isRegister() && Index: llvm/lib/Target/PowerPC/PPCInstrInfo.td diff -u llvm/lib/Target/PowerPC/PPCInstrInfo.td:1.183 llvm/lib/Target/PowerPC/PPCInstrInfo.td:1.184 --- llvm/lib/Target/PowerPC/PPCInstrInfo.td:1.183 Tue Mar 14 23:25:05 2006 +++ llvm/lib/Target/PowerPC/PPCInstrInfo.td Thu Mar 16 14:03:58 2006 @@ -1009,6 +1009,9 @@ def VSUBFP : VXForm_1<74, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB), "vsubfp $vD, $vA, $vB", VecFP, [(set VRRC:$vD, (fsub VRRC:$vA, VRRC:$vB))]>; +def VOR : VXForm_1<1156, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB), + "vor $vD, $vA, $vB", VecFP, + []>; def VXOR : VXForm_1<1220, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB), "vxor $vD, $vA, $vB", VecFP, []>; @@ -1151,6 +1154,7 @@ def : Pat<(store (v4i32 VRRC:$rS), xoaddr:$dst), (STVX (v4i32 VRRC:$rS), xoaddr:$dst)>; + // Same as above, but using a temporary. FIXME: implement temporaries :) /* def : Pattern<(xor GPRC:$in, imm:$imm), Index: llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp diff -u llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp:1.44 llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp:1.45 --- llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp:1.44 Mon Mar 13 15:52:10 2006 +++ llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp Thu Mar 16 14:03:58 2006 @@ -110,6 +110,8 @@ BuildMI(MBB, MI, PPC::FMRD, 1, DestReg).addReg(SrcReg); } else if (RC == PPC::CRRCRegisterClass) { BuildMI(MBB, MI, PPC::MCRF, 1, DestReg).addReg(SrcReg); + } else if (RC == PPC::VRRCRegisterClass) { + BuildMI(MBB, MI, PPC::VOR, 2, DestReg).addReg(SrcReg).addReg(SrcReg); } else { std::cerr << "Attempt to copy register that is not GPR or FPR"; abort(); From lattner at cs.uiuc.edu Thu Mar 16 15:31:57 2006 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Thu, 16 Mar 2006 15:31:57 -0600 Subject: [llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp Message-ID: <200603162131.PAA14505@zion.cs.uiuc.edu> Changes in directory llvm/lib/Target/PowerPC: PPCRegisterInfo.cpp updated: 1.45 -> 1.46 --- Log message: in functions that use a lot of callee saved regs, this can be more than 5 instructions away. --- Diffs of the changes: (+1 -1) PPCRegisterInfo.cpp | 2 +- 1 files changed, 1 insertion(+), 1 deletion(-) Index: llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp diff -u llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp:1.45 llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp:1.46 --- llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp:1.45 Thu Mar 16 14:03:58 2006 +++ llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp Thu Mar 16 15:31:45 2006 @@ -315,7 +315,7 @@ // Scan the first few instructions of the prolog, looking for an UPDATE_VRSAVE // instruction. If we find it, process it. - for (unsigned i = 0; MBBI != MBB.end() && i < 5; ++i, ++MBBI) { + for (unsigned i = 0; MBBI != MBB.end(); ++i, ++MBBI) { if (MBBI->getOpcode() == PPC::UPDATE_VRSAVE) { HandleVRSaveUpdate(MBBI, MF.getUsedPhysregs()); break; From evan.cheng at apple.com Thu Mar 16 15:47:55 2006 From: evan.cheng at apple.com (Evan Cheng) Date: Thu, 16 Mar 2006 15:47:55 -0600 Subject: [llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCTargetMachine.cpp Message-ID: <200603162147.PAA14649@zion.cs.uiuc.edu> Changes in directory llvm/lib/Target/PowerPC: PPCTargetMachine.cpp updated: 1.83 -> 1.84 --- Log message: Added a way for TargetLowering to specify what values can be used as the scale component of the target addressing mode. --- Diffs of the changes: (+2 -2) PPCTargetMachine.cpp | 4 ++-- 1 files changed, 2 insertions(+), 2 deletions(-) Index: llvm/lib/Target/PowerPC/PPCTargetMachine.cpp diff -u llvm/lib/Target/PowerPC/PPCTargetMachine.cpp:1.83 llvm/lib/Target/PowerPC/PPCTargetMachine.cpp:1.84 --- llvm/lib/Target/PowerPC/PPCTargetMachine.cpp:1.83 Mon Mar 13 17:56:51 2006 +++ llvm/lib/Target/PowerPC/PPCTargetMachine.cpp Thu Mar 16 15:47:42 2006 @@ -84,7 +84,7 @@ if (FileType != TargetMachine::AssemblyFile) return true; // Run loop strength reduction before anything else. - if (!Fast) PM.add(createLoopStrengthReducePass(1, &TLInfo)); + if (!Fast) PM.add(createLoopStrengthReducePass(&TLInfo)); // FIXME: Implement efficient support for garbage collection intrinsics. PM.add(createLowerGCPass()); @@ -138,7 +138,7 @@ TM.setRelocationModel(Reloc::DynamicNoPIC); // Run loop strength reduction before anything else. - PM.add(createLoopStrengthReducePass(1, TM.getTargetLowering())); + PM.add(createLoopStrengthReducePass(TM.getTargetLowering())); // FIXME: Implement efficient support for garbage collection intrinsics. PM.add(createLowerGCPass()); From evan.cheng at apple.com Thu Mar 16 15:47:56 2006 From: evan.cheng at apple.com (Evan Cheng) Date: Thu, 16 Mar 2006 15:47:56 -0600 Subject: [llvm-commits] CVS: llvm/lib/Target/X86/X86ISelLowering.cpp X86TargetMachine.cpp Message-ID: <200603162147.PAA14655@zion.cs.uiuc.edu> Changes in directory llvm/lib/Target/X86: X86ISelLowering.cpp updated: 1.105 -> 1.106 X86TargetMachine.cpp updated: 1.107 -> 1.108 --- Log message: Added a way for TargetLowering to specify what values can be used as the scale component of the target addressing mode. --- Diffs of the changes: (+12 -2) X86ISelLowering.cpp | 10 ++++++++++ X86TargetMachine.cpp | 4 ++-- 2 files changed, 12 insertions(+), 2 deletions(-) Index: llvm/lib/Target/X86/X86ISelLowering.cpp diff -u llvm/lib/Target/X86/X86ISelLowering.cpp:1.105 llvm/lib/Target/X86/X86ISelLowering.cpp:1.106 --- llvm/lib/Target/X86/X86ISelLowering.cpp:1.105 Mon Mar 13 17:18:16 2006 +++ llvm/lib/Target/X86/X86ISelLowering.cpp Thu Mar 16 15:47:42 2006 @@ -49,6 +49,16 @@ setSchedulingPreference(SchedulingForRegPressure); setShiftAmountFlavor(Mask); // shl X, 32 == shl X, 0 setStackPointerRegisterToSaveRestore(X86::ESP); + + // Add legal addressing mode scale values. + addLegalAddressScale(8); + addLegalAddressScale(4); + addLegalAddressScale(2); + // Enter the ones which require both scale + index last. These are more + // expensive. + addLegalAddressScale(9); + addLegalAddressScale(5); + addLegalAddressScale(3); // Set up the register classes. addRegisterClass(MVT::i8, X86::R8RegisterClass); Index: llvm/lib/Target/X86/X86TargetMachine.cpp diff -u llvm/lib/Target/X86/X86TargetMachine.cpp:1.107 llvm/lib/Target/X86/X86TargetMachine.cpp:1.108 --- llvm/lib/Target/X86/X86TargetMachine.cpp:1.107 Mon Mar 13 17:20:37 2006 +++ llvm/lib/Target/X86/X86TargetMachine.cpp Thu Mar 16 15:47:42 2006 @@ -97,7 +97,7 @@ FileType != TargetMachine::ObjectFile) return true; // Run loop strength reduction before anything else. - if (EnableX86LSR) PM.add(createLoopStrengthReducePass(1, &TLInfo)); + if (EnableX86LSR) PM.add(createLoopStrengthReducePass(&TLInfo)); // FIXME: Implement efficient support for garbage collection intrinsics. PM.add(createLowerGCPass()); @@ -166,7 +166,7 @@ // Run loop strength reduction before anything else. if (EnableX86LSR) - PM.add(createLoopStrengthReducePass(1, TM.getTargetLowering())); + PM.add(createLoopStrengthReducePass(TM.getTargetLowering())); // FIXME: Implement efficient support for garbage collection intrinsics. PM.add(createLowerGCPass()); From evan.cheng at apple.com Thu Mar 16 15:47:56 2006 From: evan.cheng at apple.com (Evan Cheng) Date: Thu, 16 Mar 2006 15:47:56 -0600 Subject: [llvm-commits] CVS: llvm/include/llvm/Target/TargetLowering.h Message-ID: <200603162147.PAA14659@zion.cs.uiuc.edu> Changes in directory llvm/include/llvm/Target: TargetLowering.h updated: 1.60 -> 1.61 --- Log message: Added a way for TargetLowering to specify what values can be used as the scale component of the target addressing mode. --- Diffs of the changes: (+28 -9) TargetLowering.h | 37 ++++++++++++++++++++++++++++--------- 1 files changed, 28 insertions(+), 9 deletions(-) Index: llvm/include/llvm/Target/TargetLowering.h diff -u llvm/include/llvm/Target/TargetLowering.h:1.60 llvm/include/llvm/Target/TargetLowering.h:1.61 --- llvm/include/llvm/Target/TargetLowering.h:1.60 Mon Mar 13 17:15:27 2006 +++ llvm/include/llvm/Target/TargetLowering.h Thu Mar 16 15:47:42 2006 @@ -560,15 +560,6 @@ virtual bool isOperandValidForConstraint(SDOperand Op, char ConstraintLetter); //===--------------------------------------------------------------------===// - // Loop Strength Reduction hooks - // - - /// isLegalAddressImmediate - Return true if the integer value or GlobalValue - /// can be used as the offset of the target addressing mode. - virtual bool isLegalAddressImmediate(int64_t V) const; - virtual bool isLegalAddressImmediate(GlobalValue *GV) const; - - //===--------------------------------------------------------------------===// // Scheduler hooks // @@ -580,6 +571,34 @@ virtual MachineBasicBlock *InsertAtEndOfBasicBlock(MachineInstr *MI, MachineBasicBlock *MBB); + //===--------------------------------------------------------------------===// + // Loop Strength Reduction hooks + // + + /// isLegalAddressImmediate - Return true if the integer value or GlobalValue + /// can be used as the offset of the target addressing mode. + virtual bool isLegalAddressImmediate(int64_t V) const; + virtual bool isLegalAddressImmediate(GlobalValue *GV) const; + + typedef std::vector::const_iterator legal_am_scale_iterator; + legal_am_scale_iterator legal_am_scale_begin() const { + return LegalAddressScales.begin(); + } + legal_am_scale_iterator legal_am_scale_end() const { + return LegalAddressScales.end(); + } + +protected: + /// addLegalAddressScale - Add a integer (> 1) value which can be used as + /// scale in the target addressing mode. Note: the ordering matters so the + /// least efficient ones should be entered first. + void addLegalAddressScale(unsigned Scale) { + LegalAddressScales.push_back(Scale); + } + +private: + std::vector LegalAddressScales; + private: TargetMachine &TM; const TargetData &TD; From evan.cheng at apple.com Thu Mar 16 15:53:17 2006 From: evan.cheng at apple.com (Evan Cheng) Date: Thu, 16 Mar 2006 15:53:17 -0600 Subject: [llvm-commits] CVS: llvm/lib/Transforms/Scalar/LoopStrengthReduce.cpp Message-ID: <200603162153.PAA14697@zion.cs.uiuc.edu> Changes in directory llvm/lib/Transforms/Scalar: LoopStrengthReduce.cpp updated: 1.76 -> 1.77 --- Log message: For each loop, keep track of all the IV expressions inserted indexed by stride. For a set of uses of the IV of a stride which is a multiple of another stride, do not insert a new IV expression. Rather, reuse the previous IV and rewrite the uses as uses of IV expression multiplied by the factor. e.g. x = 0 ...; x ++ y = 0 ...; y += 4 then use of y can be rewritten as use of 4*x for x86. --- Diffs of the changes: (+119 -40) LoopStrengthReduce.cpp | 159 ++++++++++++++++++++++++++++++++++++------------- 1 files changed, 119 insertions(+), 40 deletions(-) Index: llvm/lib/Transforms/Scalar/LoopStrengthReduce.cpp diff -u llvm/lib/Transforms/Scalar/LoopStrengthReduce.cpp:1.76 llvm/lib/Transforms/Scalar/LoopStrengthReduce.cpp:1.77 --- llvm/lib/Transforms/Scalar/LoopStrengthReduce.cpp:1.76 Mon Mar 13 17:14:23 2006 +++ llvm/lib/Transforms/Scalar/LoopStrengthReduce.cpp Thu Mar 16 15:53:05 2006 @@ -76,6 +76,27 @@ } }; + /// IVInfo - This structure keeps track of one IV expression inserted during + /// StrengthReduceStridedIVUsers. It contains the base value, as well as the + /// PHI node and increment value created for rewrite. + struct IVExpr { + SCEVHandle Base; + PHINode *PHI; + Value *IncV; + + IVExpr(const SCEVHandle &base, PHINode *phi, Value *incv) + : Base(base), PHI(phi), IncV(incv) {} + }; + + /// IVsOfOneStride - This structure keeps track of all IV expression inserted + /// during StrengthReduceStridedIVUsers for a particular stride of the IV. + struct IVsOfOneStride { + std::vector IVs; + + void addIV(const SCEVHandle &Base, PHINode *PHI, Value *IncV) { + IVs.push_back(IVExpr(Base, PHI, IncV)); + } + }; class LoopStrengthReduce : public FunctionPass { LoopInfo *LI; @@ -85,14 +106,14 @@ const Type *UIntPtrTy; bool Changed; - /// MaxTargetAMSize - This is the maximum power-of-two scale value that the - /// target can handle for free with its addressing modes. - unsigned MaxTargetAMSize; - /// IVUsesByStride - Keep track of all uses of induction variables that we /// are interested in. The key of the map is the stride of the access. std::map IVUsesByStride; + /// IVsByStride - Keep track of all IVs that have been inserted for a + /// particular stride. + std::map IVsByStride; + /// StrideOrder - An ordering of the keys in IVUsesByStride that is stable: /// We use this to iterate over the IVUsesByStride collection without being /// dependent on random ordering of pointers in the process. @@ -112,8 +133,8 @@ const TargetLowering *TLI; public: - LoopStrengthReduce(unsigned MTAMS = 1, const TargetLowering *tli = NULL) - : MaxTargetAMSize(MTAMS), TLI(tli) { + LoopStrengthReduce(const TargetLowering *tli = NULL) + : TLI(tli) { } virtual bool runOnFunction(Function &) { @@ -168,9 +189,8 @@ "Loop Strength Reduction"); } -FunctionPass *llvm::createLoopStrengthReducePass(unsigned MaxTargetAMSize, - const TargetLowering *TLI) { - return new LoopStrengthReduce(MaxTargetAMSize, TLI); +FunctionPass *llvm::createLoopStrengthReducePass(const TargetLowering *TLI) { + return new LoopStrengthReduce(TLI); } /// getCastedVersionOf - Return the specified value casted to uintptr_t. @@ -829,6 +849,14 @@ return Result; } +/// isZero - returns true if the scalar evolution expression is zero. +/// +static bool isZero(SCEVHandle &V) { + if (SCEVConstant *SC = dyn_cast(V)) + return SC->getValue()->getRawValue() == 0; + return false; +} + /// StrengthReduceStridedIVUsers - Strength reduce all of the users of a single /// stride of IV. All of the users may have different starting values, and this @@ -863,7 +891,8 @@ // for the strides (e.g. if we have "A+C+B" and "A+B+D" as our bases, find // "A+B"), emit it to the preheader, then remove the expression from the // UsersToProcess base values. - SCEVHandle CommonExprs = RemoveCommonExpressionsFromUseBases(UsersToProcess); + SCEVHandle CommonExprs = + RemoveCommonExpressionsFromUseBases(UsersToProcess); // Next, figure out what we can represent in the immediate fields of // instructions. If we can represent anything there, move it to the imm @@ -891,12 +920,12 @@ isAddress, L); } } - + // Now that we know what we need to do, insert the PHI node itself. // DEBUG(std::cerr << "INSERTING IV of STRIDE " << *Stride << " and BASE " << *CommonExprs << " :\n"); - + SCEVExpander Rewriter(*SE, *LI); SCEVExpander PreheaderRewriter(*SE, *LI); @@ -905,33 +934,68 @@ Instruction *PhiInsertBefore = L->getHeader()->begin(); BasicBlock *LatchBlock = L->getLoopLatch(); - - // Create a new Phi for this base, and stick it in the loop header. - const Type *ReplacedTy = CommonExprs->getType(); - PHINode *NewPHI = new PHINode(ReplacedTy, "iv.", PhiInsertBefore); - ++NumInserted; - - // Insert the stride into the preheader. - Value *StrideV = PreheaderRewriter.expandCodeFor(Stride, PreInsertPt, - ReplacedTy); - if (!isa(StrideV)) ++NumVariable; + unsigned RewriteFactor = 1; + PHINode *NewPHI = NULL; + Value *IncV = NULL; + // FIXME: Only handle base == 0 for now. + if (TLI && isZero(CommonExprs)) { + if (SCEVConstant *SC = dyn_cast(Stride)) { + unsigned SInt = SC->getValue()->getRawValue(); + for (TargetLowering::legal_am_scale_iterator + I = TLI->legal_am_scale_begin(), E = TLI->legal_am_scale_end(); + I != E; ++I) { + unsigned Scale = *I; + if ((SInt % Scale) != 0) + continue; + std::map::iterator SI = + IVsByStride.find(SCEVUnknown::getIntegerSCEV(SInt/Scale, Type::UIntTy)); + if (SI == IVsByStride.end()) + continue; + for (std::vector::iterator II = SI->second.IVs.begin(), + IE = SI->second.IVs.end(); II != IE; ++II) + if (isZero(II->Base)) { + RewriteFactor = Scale; + NewPHI = II->PHI; + IncV = II->IncV; + break; + } + if (RewriteFactor != 1) + break; + } + } + } + + const Type *ReplacedTy = CommonExprs->getType(); + if (RewriteFactor == 1) { + // Create a new Phi for this base, and stick it in the loop header. + NewPHI = new PHINode(ReplacedTy, "iv.", PhiInsertBefore); + ++NumInserted; + + // Insert the stride into the preheader. + Value *StrideV = PreheaderRewriter.expandCodeFor(Stride, PreInsertPt, + ReplacedTy); + if (!isa(StrideV)) ++NumVariable; + + + // Emit the initial base value into the loop preheader, and add it to the + // Phi node. + Value *PHIBaseV = PreheaderRewriter.expandCodeFor(CommonExprs, PreInsertPt, + ReplacedTy); + NewPHI->addIncoming(PHIBaseV, Preheader); + + // Emit the increment of the base value before the terminator of the loop + // latch block, and add it to the Phi node. + SCEVHandle IncExp = SCEVAddExpr::get(SCEVUnknown::get(NewPHI), + SCEVUnknown::get(StrideV)); + + IncV = Rewriter.expandCodeFor(IncExp, LatchBlock->getTerminator(), + ReplacedTy); + IncV->setName(NewPHI->getName()+".inc"); + NewPHI->addIncoming(IncV, LatchBlock); - // Emit the initial base value into the loop preheader, and add it to the - // Phi node. - Value *PHIBaseV = PreheaderRewriter.expandCodeFor(CommonExprs, PreInsertPt, - ReplacedTy); - NewPHI->addIncoming(PHIBaseV, Preheader); - - // Emit the increment of the base value before the terminator of the loop - // latch block, and add it to the Phi node. - SCEVHandle IncExp = SCEVAddExpr::get(SCEVUnknown::get(NewPHI), - SCEVUnknown::get(StrideV)); - - Value *IncV = Rewriter.expandCodeFor(IncExp, LatchBlock->getTerminator(), - ReplacedTy); - IncV->setName(NewPHI->getName()+".inc"); - NewPHI->addIncoming(IncV, LatchBlock); + IVsByStride[Stride].addIV(CommonExprs, NewPHI, IncV); + } // Sort by the base value, so that all IVs with identical bases are next to // each other. @@ -977,13 +1041,20 @@ // Clear the SCEVExpander's expression map so that we are guaranteed // to have the code emitted where we expect it. Rewriter.clear(); - + + // If we are reusing the iv, then it must be multiplied by a constant + // factor take advantage of addressing mode scale component. + if (RewriteFactor != 1) + RewriteExpr = + SCEVMulExpr::get(SCEVUnknown::getIntegerSCEV(RewriteFactor, + RewriteExpr->getType()), RewriteExpr); + // Now that we know what we need to do, insert code before User for the // immediate and any loop-variant expressions. if (!isa(BaseV) || !cast(BaseV)->isNullValue()) // Add BaseV to the PHI value if needed. RewriteExpr = SCEVAddExpr::get(RewriteExpr, SCEVUnknown::get(BaseV)); - + User.RewriteInstructionToUseNewBase(RewriteExpr, Rewriter, L, this); // Mark old value we replaced as possibly dead, so that it is elminated @@ -1119,7 +1190,15 @@ // If we only have one stride, we can more aggressively eliminate some things. bool HasOneStride = IVUsesByStride.size() == 1; - + +#ifndef NDEBUG + DEBUG(std::cerr << "\nLSR on "); + DEBUG(L->dump()); +#endif + + // IVsByStride keeps IVs for one particular loop. + IVsByStride.clear(); + // Note: this processes each stride/type pair individually. All users passed // into StrengthReduceStridedIVUsers have the same type AND stride. Also, // node that we iterate over IVUsesByStride indirectly by using StrideOrder. From evan.cheng at apple.com Thu Mar 16 15:53:18 2006 From: evan.cheng at apple.com (Evan Cheng) Date: Thu, 16 Mar 2006 15:53:18 -0600 Subject: [llvm-commits] CVS: llvm/include/llvm/Transforms/Scalar.h Message-ID: <200603162153.PAA14701@zion.cs.uiuc.edu> Changes in directory llvm/include/llvm/Transforms: Scalar.h updated: 1.61 -> 1.62 --- Log message: For each loop, keep track of all the IV expressions inserted indexed by stride. For a set of uses of the IV of a stride which is a multiple of another stride, do not insert a new IV expression. Rather, reuse the previous IV and rewrite the uses as uses of IV expression multiplied by the factor. e.g. x = 0 ...; x ++ y = 0 ...; y += 4 then use of y can be rewritten as use of 4*x for x86. --- Diffs of the changes: (+4 -8) Scalar.h | 12 ++++-------- 1 files changed, 4 insertions(+), 8 deletions(-) Index: llvm/include/llvm/Transforms/Scalar.h diff -u llvm/include/llvm/Transforms/Scalar.h:1.61 llvm/include/llvm/Transforms/Scalar.h:1.62 --- llvm/include/llvm/Transforms/Scalar.h:1.61 Mon Mar 13 17:14:23 2006 +++ llvm/include/llvm/Transforms/Scalar.h Thu Mar 16 15:53:05 2006 @@ -132,15 +132,11 @@ //===----------------------------------------------------------------------===// // // LoopStrengthReduce - This pass is strength reduces GEP instructions that use -// a loop's canonical induction variable as one of their indices. The -// MaxTargetAMSize is the largest element size that the target architecture -// can handle in its addressing modes. Power of two multipliers less than or -// equal to this value are not reduced. It also takes an optional second -// parameter used to consult the target machine whether certain transformations -// are profitable. +// a loop's canonical induction variable as one of their indices. It takes an +// optional parameter used to consult the target machine whether certain +// transformations are profitable. // -FunctionPass *createLoopStrengthReducePass(unsigned MaxTargetAMSize = 1, - const TargetLowering *TLI = NULL); +FunctionPass *createLoopStrengthReducePass(const TargetLowering *TLI = NULL); //===----------------------------------------------------------------------===// // From evan.cheng at apple.com Thu Mar 16 16:03:00 2006 From: evan.cheng at apple.com (Evan Cheng) Date: Thu, 16 Mar 2006 16:03:00 -0600 Subject: [llvm-commits] CVS: llvm/lib/Target/X86/X86ISelLowering.cpp Message-ID: <200603162203.QAA14809@zion.cs.uiuc.edu> Changes in directory llvm/lib/Target/X86: X86ISelLowering.cpp updated: 1.106 -> 1.107 --- Log message: Bug fix: condition inverted. --- Diffs of the changes: (+1 -1) X86ISelLowering.cpp | 2 +- 1 files changed, 1 insertion(+), 1 deletion(-) Index: llvm/lib/Target/X86/X86ISelLowering.cpp diff -u llvm/lib/Target/X86/X86ISelLowering.cpp:1.106 llvm/lib/Target/X86/X86ISelLowering.cpp:1.107 --- llvm/lib/Target/X86/X86ISelLowering.cpp:1.106 Thu Mar 16 15:47:42 2006 +++ llvm/lib/Target/X86/X86ISelLowering.cpp Thu Mar 16 16:02:48 2006 @@ -2214,7 +2214,7 @@ if (RModel == Reloc::Static) return true; else if (RModel == Reloc::DynamicNoPIC) - return DarwinGVRequiresExtraLoad(GV); + return !DarwinGVRequiresExtraLoad(GV); else return false; } else From lattner at cs.uiuc.edu Thu Mar 16 16:07:18 2006 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Thu, 16 Mar 2006 16:07:18 -0600 Subject: [llvm-commits] CVS: llvm/lib/Target/PowerPC/PPC.td Message-ID: <200603162207.QAA14880@zion.cs.uiuc.edu> Changes in directory llvm/lib/Target/PowerPC: PPC.td updated: 1.14 -> 1.15 --- Log message: add callee saved vector regs --- Diffs of the changes: (+2 -1) PPC.td | 3 ++- 1 files changed, 2 insertions(+), 1 deletion(-) Index: llvm/lib/Target/PowerPC/PPC.td diff -u llvm/lib/Target/PowerPC/PPC.td:1.14 llvm/lib/Target/PowerPC/PPC.td:1.15 --- llvm/lib/Target/PowerPC/PPC.td:1.14 Sun Mar 12 23:15:10 2006 +++ llvm/lib/Target/PowerPC/PPC.td Thu Mar 16 16:07:06 2006 @@ -93,5 +93,6 @@ let CalleeSavedRegisters = [R1, R13, R14, R15, R16, R17, R18, R19, R20, R21, R22, R23, R24, R25, R26, R27, R28, R29, R30, R31, F14, F15, F16, F17, F18, F19, F20, F21, F22, F23, F24, F25, F26, F27, F28, F29, - F30, F31, CR2, CR3, CR4, LR]; + F30, F31, CR2, CR3, CR4, V20, V21, V22, V23, V24, V25, V26, V27, V28, + V29, V30, V31, LR]; } From lattner at cs.uiuc.edu Thu Mar 16 16:24:14 2006 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Thu, 16 Mar 2006 16:24:14 -0600 Subject: [llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCInstrInfo.cpp PPCRegisterInfo.cpp Message-ID: <200603162224.QAA15117@zion.cs.uiuc.edu> Changes in directory llvm/lib/Target/PowerPC: PPCInstrInfo.cpp updated: 1.18 -> 1.19 PPCRegisterInfo.cpp updated: 1.46 -> 1.47 --- Log message: teach the ppc backend how to spill/reload vector regs --- Diffs of the changes: (+21 -1) PPCInstrInfo.cpp | 2 +- PPCRegisterInfo.cpp | 20 ++++++++++++++++++++ 2 files changed, 21 insertions(+), 1 deletion(-) Index: llvm/lib/Target/PowerPC/PPCInstrInfo.cpp diff -u llvm/lib/Target/PowerPC/PPCInstrInfo.cpp:1.18 llvm/lib/Target/PowerPC/PPCInstrInfo.cpp:1.19 --- llvm/lib/Target/PowerPC/PPCInstrInfo.cpp:1.18 Thu Mar 16 14:03:58 2006 +++ llvm/lib/Target/PowerPC/PPCInstrInfo.cpp Thu Mar 16 16:24:02 2006 @@ -80,7 +80,7 @@ } unsigned PPCInstrInfo::isLoadFromStackSlot(MachineInstr *MI, - int &FrameIndex) const { + int &FrameIndex) const { switch (MI->getOpcode()) { default: break; case PPC::LD: Index: llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp diff -u llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp:1.46 llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp:1.47 --- llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp:1.46 Thu Mar 16 15:31:45 2006 +++ llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp Thu Mar 16 16:24:02 2006 @@ -50,6 +50,9 @@ unsigned SrcReg, int FrameIdx, const TargetRegisterClass *RC) const { if (SrcReg == PPC::LR) { + // FIXME: this spills LR immediately to memory in one step. To do this, we + // use R11, which we know cannot be used in the prolog/epilog. This is a + // hack. BuildMI(MBB, MI, PPC::MFLR, 1, PPC::R11); addFrameReference(BuildMI(MBB, MI, PPC::STW, 3).addReg(PPC::R11), FrameIdx); } else if (RC == PPC::CRRCRegisterClass) { @@ -63,6 +66,15 @@ addFrameReference(BuildMI(MBB, MI, PPC::STFD, 3).addReg(SrcReg),FrameIdx); } else if (RC == PPC::F4RCRegisterClass) { addFrameReference(BuildMI(MBB, MI, PPC::STFS, 3).addReg(SrcReg),FrameIdx); + } else if (RC == PPC::VRRCRegisterClass) { + // We don't have indexed addressing for vector loads. Emit: + // R11 = ADDI FI# + // Dest = LVX R0, R11 + // + // FIXME: We use R0 here, because it isn't available for RA. + addFrameReference(BuildMI(MBB, MI, PPC::ADDI, 1, PPC::R0), FrameIdx, 0, 0); + BuildMI(MBB, MI, PPC::STVX, 3) + .addReg(SrcReg).addReg(PPC::R0).addReg(PPC::R0); } else { assert(0 && "Unknown regclass!"); abort(); @@ -88,6 +100,14 @@ addFrameReference(BuildMI(MBB, MI, PPC::LFD, 2, DestReg), FrameIdx); } else if (RC == PPC::F4RCRegisterClass) { addFrameReference(BuildMI(MBB, MI, PPC::LFS, 2, DestReg), FrameIdx); + } else if (RC == PPC::VRRCRegisterClass) { + // We don't have indexed addressing for vector loads. Emit: + // R11 = ADDI FI# + // Dest = LVX R0, R11 + // + // FIXME: We use R0 here, because it isn't available for RA. + addFrameReference(BuildMI(MBB, MI, PPC::ADDI, 1, PPC::R0), FrameIdx, 0, 0); + BuildMI(MBB, MI, PPC::LVX, 2, DestReg).addReg(PPC::R0).addReg(PPC::R0); } else { assert(0 && "Unknown regclass!"); abort(); From lattner at cs.uiuc.edu Thu Mar 16 16:26:07 2006 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Thu, 16 Mar 2006 16:26:07 -0600 Subject: [llvm-commits] CVS: llvm/lib/Target/PowerPC/README.txt Message-ID: <200603162226.QAA15245@zion.cs.uiuc.edu> Changes in directory llvm/lib/Target/PowerPC: README.txt updated: 1.71 -> 1.72 --- Log message: add a note --- Diffs of the changes: (+8 -1) README.txt | 9 ++++++++- 1 files changed, 8 insertions(+), 1 deletion(-) Index: llvm/lib/Target/PowerPC/README.txt diff -u llvm/lib/Target/PowerPC/README.txt:1.71 llvm/lib/Target/PowerPC/README.txt:1.72 --- llvm/lib/Target/PowerPC/README.txt:1.71 Thu Mar 16 12:50:44 2006 +++ llvm/lib/Target/PowerPC/README.txt Thu Mar 16 16:25:55 2006 @@ -507,6 +507,10 @@ ===-------------------------------------------------------------------------=== +Implement PPCInstrInfo::isLoadFromStackSlot/isStoreToStackSlot for vector +registers, to generate better spill code. + +===-------------------------------------------------------------------------=== int foo(int N, int ***W, int **TK, int X) { int t, i; @@ -517,4 +521,7 @@ return 5; } -We generate relatively atrocious code for this loop compared to gcc. \ No newline at end of file +We generate relatively atrocious code for this loop compared to gcc. + + + From lattner at cs.uiuc.edu Thu Mar 16 16:36:11 2006 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Thu, 16 Mar 2006 16:36:11 -0600 Subject: [llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCInstrInfo.td Message-ID: <200603162236.QAA15441@zion.cs.uiuc.edu> Changes in directory llvm/lib/Target/PowerPC: PPCInstrInfo.td updated: 1.184 -> 1.185 --- Log message: Strangely, calls clobber call-clobbered vector regs. Whodathoughtit? --- Diffs of the changes: (+1 -0) PPCInstrInfo.td | 1 + 1 files changed, 1 insertion(+) Index: llvm/lib/Target/PowerPC/PPCInstrInfo.td diff -u llvm/lib/Target/PowerPC/PPCInstrInfo.td:1.184 llvm/lib/Target/PowerPC/PPCInstrInfo.td:1.185 --- llvm/lib/Target/PowerPC/PPCInstrInfo.td:1.184 Thu Mar 16 14:03:58 2006 +++ llvm/lib/Target/PowerPC/PPCInstrInfo.td Thu Mar 16 16:35:59 2006 @@ -276,6 +276,7 @@ // All calls clobber the non-callee saved registers... Defs = [R0,R2,R3,R4,R5,R6,R7,R8,R9,R10,R11,R12, F0,F1,F2,F3,F4,F5,F6,F7,F8,F9,F10,F11,F12,F13, + V0,V1,V2,V3,V4,V5,V6,V7,V8,V9,V10,V11,V12,V13,V14,V15,V16,V17,V18,V19, LR,CTR, CR0,CR1,CR5,CR6,CR7] in { // Convenient aliases for call instructions From natebegeman at mac.com Thu Mar 16 16:38:00 2006 From: natebegeman at mac.com (Nate Begeman) Date: Thu, 16 Mar 2006 16:38:00 -0600 Subject: [llvm-commits] CVS: llvm/lib/Target/PowerPC/README.txt Message-ID: <200603162238.QAA15458@zion.cs.uiuc.edu> Changes in directory llvm/lib/Target/PowerPC: README.txt updated: 1.72 -> 1.73 --- Log message: Notes on how to kill the eeevil brtwoway, and make ppc branch selector more target independant, generate better code, and be less conservative. --- Diffs of the changes: (+28 -0) README.txt | 28 ++++++++++++++++++++++++++++ 1 files changed, 28 insertions(+) Index: llvm/lib/Target/PowerPC/README.txt diff -u llvm/lib/Target/PowerPC/README.txt:1.72 llvm/lib/Target/PowerPC/README.txt:1.73 --- llvm/lib/Target/PowerPC/README.txt:1.72 Thu Mar 16 16:25:55 2006 +++ llvm/lib/Target/PowerPC/README.txt Thu Mar 16 16:37:48 2006 @@ -18,6 +18,34 @@ This occurs in SPASS. +The power of diet coke came up with a solution to this today: + +We know the only two cases that can happen here are either: +a) we have a conditional branch followed by a fallthrough to the next BB +b) we have a conditional branch followed by an unconditional branch + +We also invented the BRTWOWAY node to model (b). + +Currently, these are modeled by the PPC_BRCOND node which is a 12-byte pseudo +that codegens to + bccinv false +true: + b truebb +false: + b falsebb + +However, realizing that for (a), we can bccinv directly to the fallthrough +block, and for (b) we will already have another unconditional branch after +the conditional branch (see SPASS case above), then we know that we don't need +BRTWOWAY at all, and can just codegen PPC_BRCOND as + +bccinv +8 +b truebb + +This will also allow us to selectively not run the ppc branch selector, by just +selecting PPC_BRCOND pseudo directly to the correct conditional branch +instruction for small functions. + ===-------------------------------------------------------------------------=== * Codegen this: From evan.cheng at apple.com Thu Mar 16 16:44:34 2006 From: evan.cheng at apple.com (Evan Cheng) Date: Thu, 16 Mar 2006 16:44:34 -0600 Subject: [llvm-commits] CVS: llvm/lib/Target/X86/README.txt Message-ID: <200603162244.QAA15502@zion.cs.uiuc.edu> Changes in directory llvm/lib/Target/X86: README.txt updated: 1.65 -> 1.66 --- Log message: A new entry. --- Diffs of the changes: (+45 -0) README.txt | 45 +++++++++++++++++++++++++++++++++++++++++++++ 1 files changed, 45 insertions(+) Index: llvm/lib/Target/X86/README.txt diff -u llvm/lib/Target/X86/README.txt:1.65 llvm/lib/Target/X86/README.txt:1.66 --- llvm/lib/Target/X86/README.txt:1.65 Wed Mar 8 19:39:46 2006 +++ llvm/lib/Target/X86/README.txt Thu Mar 16 16:44:22 2006 @@ -584,3 +584,48 @@ //===---------------------------------------------------------------------===// +%X = weak global int 0 + +void %foo(int %N) { + %N = cast int %N to uint + %tmp.24 = setgt int %N, 0 + br bool %tmp.24, label %no_exit, label %return + +no_exit: + %indvar = phi uint [ 0, %entry ], [ %indvar.next, %no_exit ] + %i.0.0 = cast uint %indvar to int + volatile store int %i.0.0, int* %X + %indvar.next = add uint %indvar, 1 + %exitcond = seteq uint %indvar.next, %N + br bool %exitcond, label %return, label %no_exit + +return: + ret void +} + +compiles into: + + .text + .align 4 + .globl _foo +_foo: + movl 4(%esp), %eax + cmpl $1, %eax + jl LBB_foo_4 # return +LBB_foo_1: # no_exit.preheader + xorl %ecx, %ecx +LBB_foo_2: # no_exit + movl L_X$non_lazy_ptr, %edx + movl %ecx, (%edx) + incl %ecx + cmpl %eax, %ecx + jne LBB_foo_2 # no_exit +LBB_foo_3: # return.loopexit +LBB_foo_4: # return + ret + +We should hoist "movl L_X$non_lazy_ptr, %edx" out of the loop after +remateralization is implemented. This can be accomplished with 1) a target +dependent LICM pass or 2) makeing SelectDAG represent the whole function. + +//===---------------------------------------------------------------------===// From lattner at cs.uiuc.edu Thu Mar 16 17:05:31 2006 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Thu, 16 Mar 2006 17:05:31 -0600 Subject: [llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp Message-ID: <200603162305.RAA15724@zion.cs.uiuc.edu> Changes in directory llvm/lib/CodeGen/SelectionDAG: SelectionDAGISel.cpp updated: 1.191 -> 1.192 --- Log message: Fix a problem fully scalarizing values. --- Diffs of the changes: (+4 -1) SelectionDAGISel.cpp | 5 ++++- 1 files changed, 4 insertions(+), 1 deletion(-) Index: llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp diff -u llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.191 llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.192 --- llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.191 Thu Mar 16 13:57:50 2006 +++ llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp Thu Mar 16 17:05:19 2006 @@ -293,7 +293,10 @@ NumElts >>= 1; NumVectorRegs <<= 1; } - VT = getVectorType(EltTy, NumElts); + if (NumElts == 1) + VT = EltTy; + else + VT = getVectorType(EltTy, NumElts); } // The common case is that we will only create one register for this From lattner at cs.uiuc.edu Thu Mar 16 17:16:29 2006 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Thu, 16 Mar 2006 17:16:29 -0600 Subject: [llvm-commits] CVS: llvm/tools/bugpoint/CrashDebugger.cpp Message-ID: <200603162316.RAA15867@zion.cs.uiuc.edu> Changes in directory llvm/tools/bugpoint: CrashDebugger.cpp updated: 1.46 -> 1.47 --- Log message: add an assert to get a slightly better msg about this problem --- Diffs of the changes: (+3 -0) CrashDebugger.cpp | 3 +++ 1 files changed, 3 insertions(+) Index: llvm/tools/bugpoint/CrashDebugger.cpp diff -u llvm/tools/bugpoint/CrashDebugger.cpp:1.46 llvm/tools/bugpoint/CrashDebugger.cpp:1.47 --- llvm/tools/bugpoint/CrashDebugger.cpp:1.46 Sun Mar 5 16:21:36 2006 +++ llvm/tools/bugpoint/CrashDebugger.cpp Thu Mar 16 17:16:17 2006 @@ -128,6 +128,9 @@ // Convert list to set for fast lookup... std::set Functions; for (unsigned i = 0, e = Funcs.size(); i != e; ++i) { + // FIXME: bugpoint should add names to all stripped symbols. + assert(!Funcs[i]->getName().empty() && + "Bugpoint doesn't work on stripped modules yet PR718!"); Function *CMF = M->getFunction(Funcs[i]->getName(), Funcs[i]->getFunctionType()); assert(CMF && "Function not in module?!"); From lattner at cs.uiuc.edu Thu Mar 16 17:52:20 2006 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Thu, 16 Mar 2006 17:52:20 -0600 Subject: [llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp Message-ID: <200603162352.RAA16181@zion.cs.uiuc.edu> Changes in directory llvm/lib/Target/PowerPC: PPCRegisterInfo.cpp updated: 1.47 -> 1.48 --- Log message: remove dead variable --- Diffs of the changes: (+0 -2) PPCRegisterInfo.cpp | 2 -- 1 files changed, 2 deletions(-) Index: llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp diff -u llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp:1.47 llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp:1.48 --- llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp:1.47 Thu Mar 16 16:24:02 2006 +++ llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp Thu Mar 16 17:52:08 2006 @@ -118,8 +118,6 @@ MachineBasicBlock::iterator MI, unsigned DestReg, unsigned SrcReg, const TargetRegisterClass *RC) const { - MachineInstr *I; - if (RC == PPC::GPRCRegisterClass) { BuildMI(MBB, MI, PPC::OR4, 2, DestReg).addReg(SrcReg).addReg(SrcReg); } else if (RC == PPC::G8RCRegisterClass) { From natebegeman at mac.com Thu Mar 16 19:40:48 2006 From: natebegeman at mac.com (Nate Begeman) Date: Thu, 16 Mar 2006 19:40:48 -0600 Subject: [llvm-commits] CVS: llvm/lib/Target/README.txt Message-ID: <200603170140.TAA16908@zion.cs.uiuc.edu> Changes in directory llvm/lib/Target: README.txt updated: 1.21 -> 1.22 --- Log message: Remove BRTWOWAY* Make the PPC backend not dependent on BRTWOWAY_CC and make the branch selector smarter about the code it generates, fixing a case in the readme. --- Diffs of the changes: (+5 -1) README.txt | 6 +++++- 1 files changed, 5 insertions(+), 1 deletion(-) Index: llvm/lib/Target/README.txt diff -u llvm/lib/Target/README.txt:1.21 llvm/lib/Target/README.txt:1.22 --- llvm/lib/Target/README.txt:1.21 Tue Mar 14 13:31:24 2006 +++ llvm/lib/Target/README.txt Thu Mar 16 19:40:33 2006 @@ -17,7 +17,11 @@ a bunch of loads from m. It would be better to avoid the memcpy and just do loads from the static array. -===-------------------------------------------------------------------------=== +//===---------------------------------------------------------------------===// + +Make the PPC branch selector target independant + +//===---------------------------------------------------------------------===// Get the C front-end to expand hypot(x,y) -> llvm.sqrt(x*x+y*y) when errno and precision don't matter (ffastmath). Misc/mandel will like this. :) From natebegeman at mac.com Thu Mar 16 19:40:50 2006 From: natebegeman at mac.com (Nate Begeman) Date: Thu, 16 Mar 2006 19:40:50 -0600 Subject: [llvm-commits] CVS: llvm/lib/Target/IA64/IA64ISelLowering.cpp Message-ID: <200603170140.TAA16915@zion.cs.uiuc.edu> Changes in directory llvm/lib/Target/IA64: IA64ISelLowering.cpp updated: 1.35 -> 1.36 --- Log message: Remove BRTWOWAY* Make the PPC backend not dependent on BRTWOWAY_CC and make the branch selector smarter about the code it generates, fixing a case in the readme. --- Diffs of the changes: (+0 -2) IA64ISelLowering.cpp | 2 -- 1 files changed, 2 deletions(-) Index: llvm/lib/Target/IA64/IA64ISelLowering.cpp diff -u llvm/lib/Target/IA64/IA64ISelLowering.cpp:1.35 llvm/lib/Target/IA64/IA64ISelLowering.cpp:1.36 --- llvm/lib/Target/IA64/IA64ISelLowering.cpp:1.35 Sat Mar 4 23:08:37 2006 +++ llvm/lib/Target/IA64/IA64ISelLowering.cpp Thu Mar 16 19:40:33 2006 @@ -36,8 +36,6 @@ addRegisterClass(MVT::i1, IA64::PRRegisterClass); setOperationAction(ISD::BR_CC , MVT::Other, Expand); - setOperationAction(ISD::BRCONDTWOWAY , MVT::Other, Expand); - setOperationAction(ISD::BRTWOWAY_CC , MVT::Other, Expand); setOperationAction(ISD::FP_ROUND_INREG , MVT::f32 , Expand); // ia64 uses SELECT not SELECT_CC From natebegeman at mac.com Thu Mar 16 19:40:50 2006 From: natebegeman at mac.com (Nate Begeman) Date: Thu, 16 Mar 2006 19:40:50 -0600 Subject: [llvm-commits] CVS: llvm/lib/Target/X86/X86ISelLowering.cpp Message-ID: <200603170140.TAA16917@zion.cs.uiuc.edu> Changes in directory llvm/lib/Target/X86: X86ISelLowering.cpp updated: 1.107 -> 1.108 --- Log message: Remove BRTWOWAY* Make the PPC backend not dependent on BRTWOWAY_CC and make the branch selector smarter about the code it generates, fixing a case in the readme. --- Diffs of the changes: (+0 -2) X86ISelLowering.cpp | 2 -- 1 files changed, 2 deletions(-) Index: llvm/lib/Target/X86/X86ISelLowering.cpp diff -u llvm/lib/Target/X86/X86ISelLowering.cpp:1.107 llvm/lib/Target/X86/X86ISelLowering.cpp:1.108 --- llvm/lib/Target/X86/X86ISelLowering.cpp:1.107 Thu Mar 16 16:02:48 2006 +++ llvm/lib/Target/X86/X86ISelLowering.cpp Thu Mar 16 19:40:33 2006 @@ -125,8 +125,6 @@ setOperationAction(ISD::BIT_CONVERT , MVT::i32 , Expand); setOperationAction(ISD::BRCOND , MVT::Other, Custom); - setOperationAction(ISD::BRCONDTWOWAY , MVT::Other, Expand); - setOperationAction(ISD::BRTWOWAY_CC , MVT::Other, Expand); setOperationAction(ISD::BR_CC , MVT::Other, Expand); setOperationAction(ISD::SELECT_CC , MVT::Other, Expand); setOperationAction(ISD::MEMMOVE , MVT::Other, Expand); From natebegeman at mac.com Thu Mar 16 19:40:50 2006 From: natebegeman at mac.com (Nate Begeman) Date: Thu, 16 Mar 2006 19:40:50 -0600 Subject: [llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCBranchSelector.cpp PPCISelDAGToDAG.cpp PPCISelLowering.cpp PPCInstrInfo.td README.txt Message-ID: <200603170140.TAA16931@zion.cs.uiuc.edu> Changes in directory llvm/lib/Target/PowerPC: PPCBranchSelector.cpp updated: 1.21 -> 1.22 PPCISelDAGToDAG.cpp updated: 1.168 -> 1.169 PPCISelLowering.cpp updated: 1.96 -> 1.97 PPCInstrInfo.td updated: 1.185 -> 1.186 README.txt updated: 1.73 -> 1.74 --- Log message: Remove BRTWOWAY* Make the PPC backend not dependent on BRTWOWAY_CC and make the branch selector smarter about the code it generates, fixing a case in the readme. --- Diffs of the changes: (+11 -80) PPCBranchSelector.cpp | 8 ++------ PPCISelDAGToDAG.cpp | 38 ++++---------------------------------- PPCISelLowering.cpp | 5 ++--- PPCInstrInfo.td | 3 +-- README.txt | 37 ++----------------------------------- 5 files changed, 11 insertions(+), 80 deletions(-) Index: llvm/lib/Target/PowerPC/PPCBranchSelector.cpp diff -u llvm/lib/Target/PowerPC/PPCBranchSelector.cpp:1.21 llvm/lib/Target/PowerPC/PPCBranchSelector.cpp:1.22 --- llvm/lib/Target/PowerPC/PPCBranchSelector.cpp:1.21 Wed Feb 8 13:33:26 2006 +++ llvm/lib/Target/PowerPC/PPCBranchSelector.cpp Thu Mar 16 19:40:33 2006 @@ -48,10 +48,10 @@ static unsigned getNumBytesForInstruction(MachineInstr *MI) { switch (MI->getOpcode()) { case PPC::COND_BRANCH: - // while this will be 4 most of the time, if we emit 12 it is just a + // while this will be 4 most of the time, if we emit 8 it is just a // minor pessimization that saves us from having to worry about // keeping the offsets up to date later when we emit long branch glue. - return 12; + return 8; case PPC::IMPLICIT_DEF_GPR: // no asm emitted case PPC::IMPLICIT_DEF_F4: // no asm emitted case PPC::IMPLICIT_DEF_F8: // no asm emitted @@ -102,7 +102,6 @@ // long branch: // bInverseCC $PC+8 // b .L_TARGET_MBB - // b .L_FALLTHROUGH_MBB for (MachineFunction::iterator MFI = Fn.begin(), E = Fn.end(); MFI != E; ++MFI) { MachineBasicBlock *MBB = MFI; @@ -123,8 +122,6 @@ // 3. fallthrough MBB MachineBasicBlock *trueMBB = MBBI->getOperand(2).getMachineBasicBlock(); - MachineBasicBlock *falseMBB = - MBBI->getOperand(3).getMachineBasicBlock(); int Displacement = OffsetMap[trueMBB] - ByteCount; unsigned Opcode = MBBI->getOperand(1).getImmedValue(); @@ -136,7 +133,6 @@ } else { BuildMI(*MBB, MBBJ, Inverted, 2).addReg(CRReg).addSImm(8); BuildMI(*MBB, MBBJ, PPC::B, 1).addMBB(trueMBB); - BuildMI(*MBB, MBBJ, PPC::B, 1).addMBB(falseMBB); } // Erase the psuedo COND_BRANCH instruction, and then back up the Index: llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp diff -u llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp:1.168 llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp:1.169 --- llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp:1.168 Thu Mar 16 12:25:23 2006 +++ llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp Thu Mar 16 19:40:33 2006 @@ -1105,44 +1105,14 @@ N2, N3, getI32Imm(BROpc)); return; } - case ISD::BR_CC: - case ISD::BRTWOWAY_CC: { + case ISD::BR_CC: { SDOperand Chain; Select(Chain, N->getOperand(0)); - MachineBasicBlock *Dest = - cast(N->getOperand(4))->getBasicBlock(); ISD::CondCode CC = cast(N->getOperand(1))->get(); SDOperand CondCode = SelectCC(N->getOperand(2), N->getOperand(3), CC); - - // If this is a two way branch, then grab the fallthrough basic block - // argument and build a PowerPC branch pseudo-op, suitable for long branch - // conversion if necessary by the branch selection pass. Otherwise, emit a - // standard conditional branch. - if (N->getOpcode() == ISD::BRTWOWAY_CC) { - SDOperand CondTrueBlock = N->getOperand(4); - SDOperand CondFalseBlock = N->getOperand(5); - unsigned Opc = getBCCForSetCC(CC); - SDOperand CB = - SDOperand(CurDAG->getTargetNode(PPC::COND_BRANCH, MVT::Other, - CondCode, getI32Imm(Opc), - CondTrueBlock, CondFalseBlock, - Chain), 0); - Result = CurDAG->SelectNodeTo(N, PPC::B, MVT::Other, CondFalseBlock, CB); - } else { - // Iterate to the next basic block - ilist::iterator It = BB; - ++It; - - // If the fallthrough path is off the end of the function, which would be - // undefined behavior, set it to be the same as the current block because - // we have nothing better to set it to, and leaving it alone will cause - // the PowerPC Branch Selection pass to crash. - if (It == BB->getParent()->end()) It = Dest; - Result = CurDAG->SelectNodeTo(N, PPC::COND_BRANCH, MVT::Other, CondCode, - getI32Imm(getBCCForSetCC(CC)), - N->getOperand(4), CurDAG->getBasicBlock(It), - Chain); - } + Result = CurDAG->SelectNodeTo(N, PPC::COND_BRANCH, MVT::Other, + CondCode, getI32Imm(getBCCForSetCC(CC)), + N->getOperand(4), Chain); return; } } Index: llvm/lib/Target/PowerPC/PPCISelLowering.cpp diff -u llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.96 llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.97 --- llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.96 Mon Mar 13 17:20:37 2006 +++ llvm/lib/Target/PowerPC/PPCISelLowering.cpp Thu Mar 16 19:40:33 2006 @@ -94,9 +94,8 @@ // PowerPC wants to optimize integer setcc a bit setOperationAction(ISD::SETCC, MVT::i32, Custom); - // PowerPC does not have BRCOND* which requires SetCC - setOperationAction(ISD::BRCOND, MVT::Other, Expand); - setOperationAction(ISD::BRCONDTWOWAY, MVT::Other, Expand); + // PowerPC does not have BRCOND which requires SetCC + setOperationAction(ISD::BRCOND, MVT::Other, Expand); // PowerPC turns FP_TO_SINT into FCTIWZ and some load/stores. setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom); Index: llvm/lib/Target/PowerPC/PPCInstrInfo.td diff -u llvm/lib/Target/PowerPC/PPCInstrInfo.td:1.185 llvm/lib/Target/PowerPC/PPCInstrInfo.td:1.186 --- llvm/lib/Target/PowerPC/PPCInstrInfo.td:1.185 Thu Mar 16 16:35:59 2006 +++ llvm/lib/Target/PowerPC/PPCInstrInfo.td Thu Mar 16 19:40:33 2006 @@ -245,8 +245,7 @@ let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, noResults = 1, PPC970_Unit = 7 in { - def COND_BRANCH : Pseudo<(ops CRRC:$crS, u16imm:$opc, - target:$true, target:$false), + def COND_BRANCH : Pseudo<(ops CRRC:$crS, u16imm:$opc, target:$true), "; COND_BRANCH", []>; def B : IForm<18, 0, 0, (ops target:$dst), "b $dst", BrB, Index: llvm/lib/Target/PowerPC/README.txt diff -u llvm/lib/Target/PowerPC/README.txt:1.73 llvm/lib/Target/PowerPC/README.txt:1.74 --- llvm/lib/Target/PowerPC/README.txt:1.73 Thu Mar 16 16:37:48 2006 +++ llvm/lib/Target/PowerPC/README.txt Thu Mar 16 19:40:33 2006 @@ -10,41 +10,8 @@ ===-------------------------------------------------------------------------=== -Should hint to the branch select pass that it doesn't need to print the second -unconditional branch, so we don't end up with things like: - b .LBBl42__2E_expand_function_8_674 ; loopentry.24 - b .LBBl42__2E_expand_function_8_42 ; NewDefault - b .LBBl42__2E_expand_function_8_42 ; NewDefault - -This occurs in SPASS. - -The power of diet coke came up with a solution to this today: - -We know the only two cases that can happen here are either: -a) we have a conditional branch followed by a fallthrough to the next BB -b) we have a conditional branch followed by an unconditional branch - -We also invented the BRTWOWAY node to model (b). - -Currently, these are modeled by the PPC_BRCOND node which is a 12-byte pseudo -that codegens to - bccinv false -true: - b truebb -false: - b falsebb - -However, realizing that for (a), we can bccinv directly to the fallthrough -block, and for (b) we will already have another unconditional branch after -the conditional branch (see SPASS case above), then we know that we don't need -BRTWOWAY at all, and can just codegen PPC_BRCOND as - -bccinv +8 -b truebb - -This will also allow us to selectively not run the ppc branch selector, by just -selecting PPC_BRCOND pseudo directly to the correct conditional branch -instruction for small functions. +Teach the .td file to pattern match PPC::BR_COND to appropriate bc variant, so +we don't have to always run the branch selector for small functions. ===-------------------------------------------------------------------------=== From natebegeman at mac.com Thu Mar 16 19:40:50 2006 From: natebegeman at mac.com (Nate Begeman) Date: Thu, 16 Mar 2006 19:40:50 -0600 Subject: [llvm-commits] CVS: llvm/include/llvm/CodeGen/SelectionDAGNodes.h Message-ID: <200603170140.TAA16935@zion.cs.uiuc.edu> Changes in directory llvm/include/llvm/CodeGen: SelectionDAGNodes.h updated: 1.110 -> 1.111 --- Log message: Remove BRTWOWAY* Make the PPC backend not dependent on BRTWOWAY_CC and make the branch selector smarter about the code it generates, fixing a case in the readme. --- Diffs of the changes: (+0 -13) SelectionDAGNodes.h | 13 ------------- 1 files changed, 13 deletions(-) Index: llvm/include/llvm/CodeGen/SelectionDAGNodes.h diff -u llvm/include/llvm/CodeGen/SelectionDAGNodes.h:1.110 llvm/include/llvm/CodeGen/SelectionDAGNodes.h:1.111 --- llvm/include/llvm/CodeGen/SelectionDAGNodes.h:1.110 Sat Mar 4 23:06:40 2006 +++ llvm/include/llvm/CodeGen/SelectionDAGNodes.h Thu Mar 16 19:40:33 2006 @@ -302,25 +302,12 @@ // to if the condition is true. BRCOND, - // BRCONDTWOWAY - Two-way conditional branch. The first operand is the - // chain, the second is the condition, the third is the block to branch to - // if true, and the forth is the block to branch to if false. Targets - // usually do not implement this, preferring to have legalize demote the - // operation to BRCOND/BR pairs when necessary. - BRCONDTWOWAY, - // BR_CC - Conditional branch. The behavior is like that of SELECT_CC, in // that the condition is represented as condition code, and two nodes to // compare, rather than as a combined SetCC node. The operands in order are // chain, cc, lhs, rhs, block to branch to if condition is true. BR_CC, - // BRTWOWAY_CC - Two-way conditional branch. The operands in order are - // chain, cc, lhs, rhs, block to branch to if condition is true, block to - // branch to if condition is false. Targets usually do not implement this, - // preferring to have legalize demote the operation to BRCOND/BR pairs. - BRTWOWAY_CC, - // RET - Return from function. The first operand is the chain, // and any subsequent operands are the return values for the // function. This operation can have variable number of operands. From natebegeman at mac.com Thu Mar 16 19:40:50 2006 From: natebegeman at mac.com (Nate Begeman) Date: Thu, 16 Mar 2006 19:40:50 -0600 Subject: [llvm-commits] CVS: llvm/lib/Target/Sparc/SparcISelDAGToDAG.cpp Message-ID: <200603170140.TAA16939@zion.cs.uiuc.edu> Changes in directory llvm/lib/Target/Sparc: SparcISelDAGToDAG.cpp updated: 1.88 -> 1.89 --- Log message: Remove BRTWOWAY* Make the PPC backend not dependent on BRTWOWAY_CC and make the branch selector smarter about the code it generates, fixing a case in the readme. --- Diffs of the changes: (+0 -2) SparcISelDAGToDAG.cpp | 2 -- 1 files changed, 2 deletions(-) Index: llvm/lib/Target/Sparc/SparcISelDAGToDAG.cpp diff -u llvm/lib/Target/Sparc/SparcISelDAGToDAG.cpp:1.88 llvm/lib/Target/Sparc/SparcISelDAGToDAG.cpp:1.89 --- llvm/lib/Target/Sparc/SparcISelDAGToDAG.cpp:1.88 Sat Mar 4 23:08:37 2006 +++ llvm/lib/Target/Sparc/SparcISelDAGToDAG.cpp Thu Mar 16 19:40:33 2006 @@ -166,8 +166,6 @@ // Sparc doesn't have BRCOND either, it has BR_CC. setOperationAction(ISD::BRCOND, MVT::Other, Expand); - setOperationAction(ISD::BRCONDTWOWAY, MVT::Other, Expand); - setOperationAction(ISD::BRTWOWAY_CC, MVT::Other, Expand); setOperationAction(ISD::BR_CC, MVT::i32, Custom); setOperationAction(ISD::BR_CC, MVT::f32, Custom); setOperationAction(ISD::BR_CC, MVT::f64, Custom); From natebegeman at mac.com Thu Mar 16 19:40:51 2006 From: natebegeman at mac.com (Nate Begeman) Date: Thu, 16 Mar 2006 19:40:51 -0600 Subject: [llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp LegalizeDAG.cpp SelectionDAG.cpp SelectionDAGISel.cpp Message-ID: <200603170140.TAA16951@zion.cs.uiuc.edu> Changes in directory llvm/lib/CodeGen/SelectionDAG: DAGCombiner.cpp updated: 1.126 -> 1.127 LegalizeDAG.cpp updated: 1.315 -> 1.316 SelectionDAG.cpp updated: 1.270 -> 1.271 SelectionDAGISel.cpp updated: 1.192 -> 1.193 --- Log message: Remove BRTWOWAY* Make the PPC backend not dependent on BRTWOWAY_CC and make the branch selector smarter about the code it generates, fixing a case in the readme. --- Diffs of the changes: (+5 -181) DAGCombiner.cpp | 68 ------------------------------------ LegalizeDAG.cpp | 94 --------------------------------------------------- SelectionDAG.cpp | 16 -------- SelectionDAGISel.cpp | 8 ++-- 4 files changed, 5 insertions(+), 181 deletions(-) Index: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp diff -u llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.126 llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.127 --- llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.126 Mon Mar 13 12:37:30 2006 +++ llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Thu Mar 16 19:40:33 2006 @@ -206,9 +206,7 @@ SDOperand visitFNEG(SDNode *N); SDOperand visitFABS(SDNode *N); SDOperand visitBRCOND(SDNode *N); - SDOperand visitBRCONDTWOWAY(SDNode *N); SDOperand visitBR_CC(SDNode *N); - SDOperand visitBRTWOWAY_CC(SDNode *N); SDOperand visitLOAD(SDNode *N); SDOperand visitSTORE(SDNode *N); @@ -639,9 +637,7 @@ case ISD::FNEG: return visitFNEG(N); case ISD::FABS: return visitFABS(N); case ISD::BRCOND: return visitBRCOND(N); - case ISD::BRCONDTWOWAY: return visitBRCONDTWOWAY(N); case ISD::BR_CC: return visitBR_CC(N); - case ISD::BRTWOWAY_CC: return visitBRTWOWAY_CC(N); case ISD::LOAD: return visitLOAD(N); case ISD::STORE: return visitSTORE(N); } @@ -2219,35 +2215,6 @@ return SDOperand(); } -SDOperand DAGCombiner::visitBRCONDTWOWAY(SDNode *N) { - SDOperand Chain = N->getOperand(0); - SDOperand N1 = N->getOperand(1); - SDOperand N2 = N->getOperand(2); - SDOperand N3 = N->getOperand(3); - ConstantSDNode *N1C = dyn_cast(N1); - - // unconditional branch to true mbb - if (N1C && N1C->getValue() == 1) - return DAG.getNode(ISD::BR, MVT::Other, Chain, N2); - // unconditional branch to false mbb - if (N1C && N1C->isNullValue()) - return DAG.getNode(ISD::BR, MVT::Other, Chain, N3); - // fold a brcondtwoway with a setcc condition into a BRTWOWAY_CC node if - // BRTWOWAY_CC is legal on the target. - if (N1.getOpcode() == ISD::SETCC && - TLI.isOperationLegal(ISD::BRTWOWAY_CC, MVT::Other)) { - std::vector Ops; - Ops.push_back(Chain); - Ops.push_back(N1.getOperand(2)); - Ops.push_back(N1.getOperand(0)); - Ops.push_back(N1.getOperand(1)); - Ops.push_back(N2); - Ops.push_back(N3); - return DAG.getNode(ISD::BRTWOWAY_CC, MVT::Other, Ops); - } - return SDOperand(); -} - // Operand List for BR_CC: Chain, CondCC, CondLHS, CondRHS, DestBB. // SDOperand DAGCombiner::visitBR_CC(SDNode *N) { @@ -2273,41 +2240,6 @@ return SDOperand(); } -SDOperand DAGCombiner::visitBRTWOWAY_CC(SDNode *N) { - SDOperand Chain = N->getOperand(0); - SDOperand CCN = N->getOperand(1); - SDOperand LHS = N->getOperand(2); - SDOperand RHS = N->getOperand(3); - SDOperand N4 = N->getOperand(4); - SDOperand N5 = N->getOperand(5); - - SDOperand SCC = SimplifySetCC(TLI.getSetCCResultTy(), LHS, RHS, - cast(CCN)->get(), false); - ConstantSDNode *SCCC = dyn_cast_or_null(SCC.Val); - - // fold select_cc lhs, rhs, x, x, cc -> x - if (N4 == N5) - return DAG.getNode(ISD::BR, MVT::Other, Chain, N4); - // fold select_cc true, x, y -> x - if (SCCC && SCCC->getValue()) - return DAG.getNode(ISD::BR, MVT::Other, Chain, N4); - // fold select_cc false, x, y -> y - if (SCCC && SCCC->isNullValue()) - return DAG.getNode(ISD::BR, MVT::Other, Chain, N5); - // fold to a simpler setcc - if (SCC.Val && SCC.getOpcode() == ISD::SETCC) { - std::vector Ops; - Ops.push_back(Chain); - Ops.push_back(SCC.getOperand(2)); - Ops.push_back(SCC.getOperand(0)); - Ops.push_back(SCC.getOperand(1)); - Ops.push_back(N4); - Ops.push_back(N5); - return DAG.getNode(ISD::BRTWOWAY_CC, MVT::Other, Ops); - } - return SDOperand(); -} - SDOperand DAGCombiner::visitLOAD(SDNode *N) { SDOperand Chain = N->getOperand(0); SDOperand Ptr = N->getOperand(1); Index: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp diff -u llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.315 llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.316 --- llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.315 Wed Mar 15 16:19:18 2006 +++ llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp Thu Mar 16 19:40:33 2006 @@ -945,100 +945,6 @@ break; } break; - case ISD::BRCONDTWOWAY: - Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. - switch (getTypeAction(Node->getOperand(1).getValueType())) { - case Expand: assert(0 && "It's impossible to expand bools"); - case Legal: - Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the condition. - break; - case Promote: - Tmp2 = PromoteOp(Node->getOperand(1)); // Promote the condition. - break; - } - - // If this target does not support BRCONDTWOWAY, lower it to a BRCOND/BR - // pair. - switch (TLI.getOperationAction(ISD::BRCONDTWOWAY, MVT::Other)) { - case TargetLowering::Promote: - default: assert(0 && "This action is not supported yet!"); - case TargetLowering::Legal: - Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2), - Node->getOperand(3)); - break; - case TargetLowering::Expand: - // If BRTWOWAY_CC is legal for this target, then simply expand this node - // to that. Otherwise, skip BRTWOWAY_CC and expand directly to a - // BRCOND/BR pair. - if (TLI.isOperationLegal(ISD::BRTWOWAY_CC, MVT::Other)) { - if (Tmp2.getOpcode() == ISD::SETCC) { - Tmp3 = Tmp2.getOperand(0); - Tmp4 = Tmp2.getOperand(1); - Tmp2 = Tmp2.getOperand(2); - } else { - Tmp3 = Tmp2; - Tmp4 = DAG.getConstant(0, Tmp2.getValueType()); - Tmp2 = DAG.getCondCode(ISD::SETNE); - } - std::vector Ops; - Ops.push_back(Tmp1); - Ops.push_back(Tmp2); - Ops.push_back(Tmp3); - Ops.push_back(Tmp4); - Ops.push_back(Node->getOperand(2)); - Ops.push_back(Node->getOperand(3)); - Result = DAG.getNode(ISD::BRTWOWAY_CC, MVT::Other, Ops); - } else { - Result = DAG.getNode(ISD::BRCOND, MVT::Other, Tmp1, Tmp2, - Node->getOperand(2)); - Result = DAG.getNode(ISD::BR, MVT::Other, Result, Node->getOperand(3)); - } - break; - } - break; - case ISD::BRTWOWAY_CC: { - Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. - // Ensure that libcalls are emitted before a branch. - Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END); - Tmp1 = LegalizeOp(Tmp1); - LastCALLSEQ_END = DAG.getEntryNode(); - - Tmp2 = Node->getOperand(2); // LHS - Tmp3 = Node->getOperand(3); // RHS - Tmp4 = Node->getOperand(1); // CC - - LegalizeSetCCOperands(Tmp2, Tmp3, Tmp4); - - // If we didn't get both a LHS and RHS back from LegalizeSetCCOperands, - // the LHS is a legal SETCC itself. In this case, we need to compare - // the result against zero to select between true and false values. - if (Tmp3.Val == 0) { - Tmp3 = DAG.getConstant(0, Tmp2.getValueType()); - Tmp4 = DAG.getCondCode(ISD::SETNE); - } - std::vector Ops; - Ops.push_back(Tmp1); - Ops.push_back(Tmp4); - Ops.push_back(Tmp2); - Ops.push_back(Tmp3); - Ops.push_back(Node->getOperand(4)); - Ops.push_back(Node->getOperand(5)); - Result = DAG.UpdateNodeOperands(Result, Ops); - - // Everything is legal, see if we should expand this op or something. - switch (TLI.getOperationAction(ISD::BRTWOWAY_CC, MVT::Other)) { - default: assert(0 && "This action is not supported yet!"); - case TargetLowering::Legal: break; - case TargetLowering::Expand: - Result = DAG.getNode(ISD::BRCOND, MVT::Other, Tmp1, - DAG.getNode(ISD::SETCC, TLI.getSetCCResultTy(), Tmp2, - Tmp3, Tmp4), - Result.getOperand(4)); - Result = DAG.getNode(ISD::BR, MVT::Other, Result, Result.getOperand(5)); - break; - } - break; - } case ISD::LOAD: { Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer. Index: llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp diff -u llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp:1.270 llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp:1.271 --- llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp:1.270 Wed Mar 15 16:19:46 2006 +++ llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp Thu Mar 16 19:40:33 2006 @@ -1486,18 +1486,6 @@ ConstantSDNode *N1C = dyn_cast(Ops[1].Val); switch (Opcode) { default: break; - case ISD::BRCONDTWOWAY: - if (N1C) - if (N1C->getValue()) // Unconditional branch to true dest. - return getNode(ISD::BR, MVT::Other, Ops[0], Ops[2]); - else // Unconditional branch to false dest. - return getNode(ISD::BR, MVT::Other, Ops[0], Ops[3]); - break; - case ISD::BRTWOWAY_CC: - assert(Ops.size() == 6 && "BRTWOWAY_CC takes 6 operands!"); - assert(Ops[2].getValueType() == Ops[3].getValueType() && - "LHS and RHS of comparison must have same type!"); - break; case ISD::TRUNCSTORE: { assert(Ops.size() == 5 && "TRUNCSTORE takes 5 operands!"); MVT::ValueType EVT = cast(Ops[4])->getVT(); @@ -2692,9 +2680,7 @@ // Control flow instructions case ISD::BR: return "br"; case ISD::BRCOND: return "brcond"; - case ISD::BRCONDTWOWAY: return "brcondtwoway"; - case ISD::BR_CC: return "br_cc"; - case ISD::BRTWOWAY_CC: return "brtwoway_cc"; + case ISD::BR_CC: return "br_cc"; case ISD::RET: return "ret"; case ISD::CALLSEQ_START: return "callseq_start"; case ISD::CALLSEQ_END: return "callseq_end"; Index: llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp diff -u llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.192 llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.193 --- llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.192 Thu Mar 16 17:05:19 2006 +++ llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp Thu Mar 16 19:40:33 2006 @@ -691,10 +691,10 @@ SDOperand True = DAG.getConstant(1, Cond.getValueType()); Cond = DAG.getNode(ISD::XOR, Cond.getValueType(), Cond, True); } - Ops.push_back(Cond); - Ops.push_back(DAG.getBasicBlock(Succ0MBB)); - Ops.push_back(DAG.getBasicBlock(Succ1MBB)); - DAG.setRoot(DAG.getNode(ISD::BRCONDTWOWAY, MVT::Other, Ops)); + SDOperand True = DAG.getNode(ISD::BRCOND, MVT::Other, getRoot(), Cond, + DAG.getBasicBlock(Succ0MBB)); + DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, True, + DAG.getBasicBlock(Succ1MBB))); } } } From natebegeman at mac.com Thu Mar 16 19:40:51 2006 From: natebegeman at mac.com (Nate Begeman) Date: Thu, 16 Mar 2006 19:40:51 -0600 Subject: [llvm-commits] CVS: llvm/lib/Target/Alpha/AlphaISelLowering.cpp Message-ID: <200603170140.TAA16949@zion.cs.uiuc.edu> Changes in directory llvm/lib/Target/Alpha: AlphaISelLowering.cpp updated: 1.40 -> 1.41 --- Log message: Remove BRTWOWAY* Make the PPC backend not dependent on BRTWOWAY_CC and make the branch selector smarter about the code it generates, fixing a case in the readme. --- Diffs of the changes: (+0 -2) AlphaISelLowering.cpp | 2 -- 1 files changed, 2 deletions(-) Index: llvm/lib/Target/Alpha/AlphaISelLowering.cpp diff -u llvm/lib/Target/Alpha/AlphaISelLowering.cpp:1.40 llvm/lib/Target/Alpha/AlphaISelLowering.cpp:1.41 --- llvm/lib/Target/Alpha/AlphaISelLowering.cpp:1.40 Thu Mar 9 08:58:25 2006 +++ llvm/lib/Target/Alpha/AlphaISelLowering.cpp Thu Mar 16 19:40:33 2006 @@ -48,8 +48,6 @@ addRegisterClass(MVT::f64, Alpha::F8RCRegisterClass); addRegisterClass(MVT::f32, Alpha::F4RCRegisterClass); - setOperationAction(ISD::BRCONDTWOWAY, MVT::Other, Expand); - setOperationAction(ISD::BRTWOWAY_CC, MVT::Other, Expand); setOperationAction(ISD::BR_CC, MVT::Other, Expand); setOperationAction(ISD::SELECT_CC, MVT::Other, Expand); From evan.cheng at apple.com Thu Mar 16 20:24:16 2006 From: evan.cheng at apple.com (Evan Cheng) Date: Thu, 16 Mar 2006 20:24:16 -0600 Subject: [llvm-commits] CVS: llvm/lib/Target/X86/X86InstrInfo.td Message-ID: <200603170224.UAA17335@zion.cs.uiuc.edu> Changes in directory llvm/lib/Target/X86: X86InstrInfo.td updated: 1.253 -> 1.254 --- Log message: - Nuke 16-bit SBB instructions. We'll never use them. - Nuke a bogus comment. --- Diffs of the changes: (+0 -21) X86InstrInfo.td | 21 --------------------- 1 files changed, 21 deletions(-) Index: llvm/lib/Target/X86/X86InstrInfo.td diff -u llvm/lib/Target/X86/X86InstrInfo.td:1.253 llvm/lib/Target/X86/X86InstrInfo.td:1.254 --- llvm/lib/Target/X86/X86InstrInfo.td:1.253 Tue Mar 7 17:34:23 2006 +++ llvm/lib/Target/X86/X86InstrInfo.td Thu Mar 16 20:24:04 2006 @@ -1784,7 +1784,6 @@ [(set R32:$dst, (add R32:$src1, imm:$src2))]>; } -// FIXME: move ADD16ri8 above ADD16ri to optimize for space. def ADD16ri8 : Ii8<0x83, MRM0r, (ops R16:$dst, R16:$src1, i16i8imm:$src2), "add{w} {$src2, $dst|$dst, $src2}", [(set R16:$dst, (add R16:$src1, i16immSExt8:$src2))]>, @@ -1926,39 +1925,19 @@ def SBB8mi : Ii32<0x80, MRM3m, (ops i8mem:$dst, i8imm:$src2), "sbb{b} {$src2, $dst|$dst, $src2}", [(store (sube (loadi8 addr:$dst), imm:$src2), addr:$dst)]>; - def SBB16mi : Ii32<0x81, MRM3m, (ops i16mem:$dst, i16imm:$src2), - "sbb{w} {$src2, $dst|$dst, $src2}", - [(store (sube (loadi16 addr:$dst), imm:$src2), addr:$dst)]>, - OpSize; def SBB32mi : Ii32<0x81, MRM3m, (ops i32mem:$dst, i32imm:$src2), "sbb{l} {$src2, $dst|$dst, $src2}", [(store (sube (loadi32 addr:$dst), imm:$src2), addr:$dst)]>; - def SBB16mi8 : Ii8<0x83, MRM3m, (ops i16mem:$dst, i16i8imm :$src2), - "sbb{w} {$src2, $dst|$dst, $src2}", - [(store (sube (load addr:$dst), i16immSExt8:$src2), addr:$dst)]>, - OpSize; def SBB32mi8 : Ii8<0x83, MRM3m, (ops i32mem:$dst, i32i8imm :$src2), "sbb{l} {$src2, $dst|$dst, $src2}", [(store (sube (load addr:$dst), i32immSExt8:$src2), addr:$dst)]>; } -def SBB8ri : Ii8<0x80, MRM3r, (ops R8:$dst, R8:$src1, i8imm:$src2), - "sbb{b} {$src2, $dst|$dst, $src2}", - [(set R8:$dst, (sube R8:$src1, imm:$src2))]>; -def SBB16ri : Ii16<0x81, MRM3r, (ops R16:$dst, R16:$src1, i16imm:$src2), - "sbb{w} {$src2, $dst|$dst, $src2}", - [(set R16:$dst, (sube R16:$src1, imm:$src2))]>, OpSize; - def SBB32rm : I<0x1B, MRMSrcMem, (ops R32:$dst, R32:$src1, i32mem:$src2), "sbb{l} {$src2, $dst|$dst, $src2}", [(set R32:$dst, (sube R32:$src1, (load addr:$src2)))]>; def SBB32ri : Ii32<0x81, MRM3r, (ops R32:$dst, R32:$src1, i32imm:$src2), "sbb{l} {$src2, $dst|$dst, $src2}", [(set R32:$dst, (sube R32:$src1, imm:$src2))]>; - -def SBB16ri8 : Ii8<0x83, MRM3r, (ops R16:$dst, R16:$src1, i16i8imm:$src2), - "sbb{w} {$src2, $dst|$dst, $src2}", - [(set R16:$dst, (sube R16:$src1, i16immSExt8:$src2))]>, - OpSize; def SBB32ri8 : Ii8<0x83, MRM3r, (ops R32:$dst, R32:$src1, i32i8imm:$src2), "sbb{l} {$src2, $dst|$dst, $src2}", [(set R32:$dst, (sube R32:$src1, i32immSExt8:$src2))]>; From evan.cheng at apple.com Thu Mar 16 20:25:13 2006 From: evan.cheng at apple.com (Evan Cheng) Date: Thu, 16 Mar 2006 20:25:13 -0600 Subject: [llvm-commits] CVS: llvm/lib/Target/X86/X86RegisterInfo.cpp Message-ID: <200603170225.UAA17353@zion.cs.uiuc.edu> Changes in directory llvm/lib/Target/X86: X86RegisterInfo.cpp updated: 1.127 -> 1.128 --- Log message: Add some missing entries to X86RegisterInfo::foldMemoryOperand(). e.g. ADD32ri8. --- Diffs of the changes: (+18 -6) X86RegisterInfo.cpp | 24 ++++++++++++++++++------ 1 files changed, 18 insertions(+), 6 deletions(-) Index: llvm/lib/Target/X86/X86RegisterInfo.cpp diff -u llvm/lib/Target/X86/X86RegisterInfo.cpp:1.127 llvm/lib/Target/X86/X86RegisterInfo.cpp:1.128 --- llvm/lib/Target/X86/X86RegisterInfo.cpp:1.127 Fri Feb 24 19:37:02 2006 +++ llvm/lib/Target/X86/X86RegisterInfo.cpp Thu Mar 16 20:25:01 2006 @@ -221,39 +221,49 @@ case X86::ADD8rr: return MakeMRInst(X86::ADD8mr , FrameIndex, MI); case X86::ADD16rr: return MakeMRInst(X86::ADD16mr, FrameIndex, MI); case X86::ADD32rr: return MakeMRInst(X86::ADD32mr, FrameIndex, MI); - case X86::ADC32rr: return MakeMRInst(X86::ADC32mr, FrameIndex, MI); - case X86::ADC32ri: return MakeMIInst(X86::ADC32mi, FrameIndex, MI); case X86::ADD8ri: return MakeMIInst(X86::ADD8mi , FrameIndex, MI); case X86::ADD16ri: return MakeMIInst(X86::ADD16mi, FrameIndex, MI); case X86::ADD32ri: return MakeMIInst(X86::ADD32mi, FrameIndex, MI); + case X86::ADD16ri8: return MakeMIInst(X86::ADD16mi8,FrameIndex, MI); + case X86::ADD32ri8: return MakeMIInst(X86::ADD32mi8,FrameIndex, MI); + case X86::ADC32rr: return MakeMRInst(X86::ADC32mr, FrameIndex, MI); + case X86::ADC32ri: return MakeMIInst(X86::ADC32mi, FrameIndex, MI); + case X86::ADC32ri8: return MakeMIInst(X86::ADC32mi8,FrameIndex, MI); case X86::SUB8rr: return MakeMRInst(X86::SUB8mr , FrameIndex, MI); case X86::SUB16rr: return MakeMRInst(X86::SUB16mr, FrameIndex, MI); case X86::SUB32rr: return MakeMRInst(X86::SUB32mr, FrameIndex, MI); - case X86::SBB32rr: return MakeMRInst(X86::SBB32mr, FrameIndex, MI); - case X86::SBB8ri: return MakeMIInst(X86::SBB8mi, FrameIndex, MI); - case X86::SBB16ri: return MakeMIInst(X86::SBB16mi, FrameIndex, MI); - case X86::SBB32ri: return MakeMIInst(X86::SBB32mi, FrameIndex, MI); case X86::SUB8ri: return MakeMIInst(X86::SUB8mi , FrameIndex, MI); case X86::SUB16ri: return MakeMIInst(X86::SUB16mi, FrameIndex, MI); case X86::SUB32ri: return MakeMIInst(X86::SUB32mi, FrameIndex, MI); + case X86::SUB16ri8: return MakeMIInst(X86::SUB16mi8,FrameIndex, MI); + case X86::SUB32ri8: return MakeMIInst(X86::SUB32mi8,FrameIndex, MI); + case X86::SBB32rr: return MakeMRInst(X86::SBB32mr, FrameIndex, MI); + case X86::SBB32ri: return MakeMIInst(X86::SBB32mi, FrameIndex, MI); + case X86::SBB32ri8: return MakeMIInst(X86::SBB32mi8,FrameIndex, MI); case X86::AND8rr: return MakeMRInst(X86::AND8mr , FrameIndex, MI); case X86::AND16rr: return MakeMRInst(X86::AND16mr, FrameIndex, MI); case X86::AND32rr: return MakeMRInst(X86::AND32mr, FrameIndex, MI); case X86::AND8ri: return MakeMIInst(X86::AND8mi , FrameIndex, MI); case X86::AND16ri: return MakeMIInst(X86::AND16mi, FrameIndex, MI); case X86::AND32ri: return MakeMIInst(X86::AND32mi, FrameIndex, MI); + case X86::AND16ri8: return MakeMIInst(X86::AND16mi8,FrameIndex, MI); + case X86::AND32ri8: return MakeMIInst(X86::AND32mi8,FrameIndex, MI); case X86::OR8rr: return MakeMRInst(X86::OR8mr , FrameIndex, MI); case X86::OR16rr: return MakeMRInst(X86::OR16mr, FrameIndex, MI); case X86::OR32rr: return MakeMRInst(X86::OR32mr, FrameIndex, MI); case X86::OR8ri: return MakeMIInst(X86::OR8mi , FrameIndex, MI); case X86::OR16ri: return MakeMIInst(X86::OR16mi, FrameIndex, MI); case X86::OR32ri: return MakeMIInst(X86::OR32mi, FrameIndex, MI); + case X86::OR16ri8: return MakeMIInst(X86::OR16mi8, FrameIndex, MI); + case X86::OR32ri8: return MakeMIInst(X86::OR32mi8, FrameIndex, MI); case X86::XOR8rr: return MakeMRInst(X86::XOR8mr , FrameIndex, MI); case X86::XOR16rr: return MakeMRInst(X86::XOR16mr, FrameIndex, MI); case X86::XOR32rr: return MakeMRInst(X86::XOR32mr, FrameIndex, MI); case X86::XOR8ri: return MakeMIInst(X86::XOR8mi , FrameIndex, MI); case X86::XOR16ri: return MakeMIInst(X86::XOR16mi, FrameIndex, MI); case X86::XOR32ri: return MakeMIInst(X86::XOR32mi, FrameIndex, MI); + case X86::XOR16ri8: return MakeMIInst(X86::XOR16mi8,FrameIndex, MI); + case X86::XOR32ri8: return MakeMIInst(X86::XOR32mi8,FrameIndex, MI); case X86::SHL8rCL: return MakeMInst( X86::SHL8mCL ,FrameIndex, MI); case X86::SHL16rCL: return MakeMInst( X86::SHL16mCL,FrameIndex, MI); case X86::SHL32rCL: return MakeMInst( X86::SHL32mCL,FrameIndex, MI); @@ -392,6 +402,8 @@ case X86::IMUL32rr: return MakeRMInst(X86::IMUL32rm,FrameIndex, MI); case X86::IMUL16rri: return MakeRMIInst(X86::IMUL16rmi, FrameIndex, MI); case X86::IMUL32rri: return MakeRMIInst(X86::IMUL32rmi, FrameIndex, MI); + case X86::IMUL16rri8:return MakeRMIInst(X86::IMUL16rmi8, FrameIndex, MI); + case X86::IMUL32rri8:return MakeRMIInst(X86::IMUL32rmi8, FrameIndex, MI); case X86::CMP8rr: return MakeRMInst(X86::CMP8rm , FrameIndex, MI); case X86::CMP16rr: return MakeRMInst(X86::CMP16rm, FrameIndex, MI); case X86::CMP32rr: return MakeRMInst(X86::CMP32rm, FrameIndex, MI); From evan.cheng at apple.com Thu Mar 16 20:36:34 2006 From: evan.cheng at apple.com (Evan Cheng) Date: Thu, 16 Mar 2006 20:36:34 -0600 Subject: [llvm-commits] CVS: llvm/lib/Target/X86/X86RegisterInfo.cpp Message-ID: <200603170236.UAA17393@zion.cs.uiuc.edu> Changes in directory llvm/lib/Target/X86: X86RegisterInfo.cpp updated: 1.128 -> 1.129 --- Log message: Also fold MOV8r0, MOV16r0, MOV32r0 + store to MOV8mi, MOV16mi, and MOV32mi. --- Diffs of the changes: (+9 -0) X86RegisterInfo.cpp | 9 +++++++++ 1 files changed, 9 insertions(+) Index: llvm/lib/Target/X86/X86RegisterInfo.cpp diff -u llvm/lib/Target/X86/X86RegisterInfo.cpp:1.128 llvm/lib/Target/X86/X86RegisterInfo.cpp:1.129 --- llvm/lib/Target/X86/X86RegisterInfo.cpp:1.128 Thu Mar 16 20:25:01 2006 +++ llvm/lib/Target/X86/X86RegisterInfo.cpp Thu Mar 16 20:36:22 2006 @@ -160,6 +160,11 @@ return 0; } +static MachineInstr *MakeM0Inst(unsigned Opcode, unsigned FrameIndex, + MachineInstr *MI) { + return addFrameReference(BuildMI(Opcode, 5), FrameIndex).addZImm(0); +} + static MachineInstr *MakeRMInst(unsigned Opcode, unsigned FrameIndex, MachineInstr *MI) { const MachineOperand& op = MI->getOperand(0); @@ -328,6 +333,10 @@ case X86::CMP8ri: return MakeMIInst(X86::CMP8mi , FrameIndex, MI); case X86::CMP16ri: return MakeMIInst(X86::CMP16mi, FrameIndex, MI); case X86::CMP32ri: return MakeMIInst(X86::CMP32mi, FrameIndex, MI); + // Alias instructions + case X86::MOV8r0: return MakeM0Inst(X86::MOV8mi, FrameIndex, MI); + case X86::MOV16r0: return MakeM0Inst(X86::MOV16mi, FrameIndex, MI); + case X86::MOV32r0: return MakeM0Inst(X86::MOV32mi, FrameIndex, MI); // Alias scalar SSE instructions case X86::FsMOVAPSrr: return MakeMRInst(X86::MOVSSmr, FrameIndex, MI); case X86::FsMOVAPDrr: return MakeMRInst(X86::MOVSDmr, FrameIndex, MI); From lattner at cs.uiuc.edu Thu Mar 16 23:10:32 2006 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Thu, 16 Mar 2006 23:10:32 -0600 Subject: [llvm-commits] CVS: llvm/lib/Target/X86/X86ISelLowering.cpp Message-ID: <200603170510.XAA18109@zion.cs.uiuc.edu> Changes in directory llvm/lib/Target/X86: X86ISelLowering.cpp updated: 1.108 -> 1.109 --- Log message: Parameterize the number of integer arguments to pass in registers --- Diffs of the changes: (+27 -17) X86ISelLowering.cpp | 44 +++++++++++++++++++++++++++----------------- 1 files changed, 27 insertions(+), 17 deletions(-) Index: llvm/lib/Target/X86/X86ISelLowering.cpp diff -u llvm/lib/Target/X86/X86ISelLowering.cpp:1.108 llvm/lib/Target/X86/X86ISelLowering.cpp:1.109 --- llvm/lib/Target/X86/X86ISelLowering.cpp:1.108 Thu Mar 16 19:40:33 2006 +++ llvm/lib/Target/X86/X86ISelLowering.cpp Thu Mar 16 23:10:20 2006 @@ -639,6 +639,13 @@ return VReg; } +enum { + // FASTCC_NUM_INT_ARGS_INREGS - This is the max number of integer arguments + // to pass in registers. 0 is none, 1 is is "use EAX", 2 is "use EAX and + // EDX". Anything more is illegal. + FASTCC_NUM_INT_ARGS_INREGS = 2 +}; + std::vector X86TargetLowering::LowerFastCCArguments(Function &F, SelectionDAG &DAG) { @@ -660,7 +667,7 @@ // 0 (neither EAX or EDX used), 1 (EAX is used) or 2 (EAX and EDX are both // used). unsigned NumIntRegs = 0; - + for (Function::arg_iterator I = F.arg_begin(), E = F.arg_end(); I != E; ++I) { MVT::ValueType ObjectVT = getValueType(I->getType()); unsigned ArgIncrement = 4; @@ -671,7 +678,7 @@ default: assert(0 && "Unhandled argument type!"); case MVT::i1: case MVT::i8: - if (NumIntRegs < 2) { + if (NumIntRegs < FASTCC_NUM_INT_ARGS_INREGS) { if (!I->use_empty()) { unsigned VReg = AddLiveIn(MF, NumIntRegs ? X86::DL : X86::AL, X86::R8RegisterClass); @@ -688,7 +695,7 @@ ObjSize = 1; break; case MVT::i16: - if (NumIntRegs < 2) { + if (NumIntRegs < FASTCC_NUM_INT_ARGS_INREGS) { if (!I->use_empty()) { unsigned VReg = AddLiveIn(MF, NumIntRegs ? X86::DX : X86::AX, X86::R16RegisterClass); @@ -701,9 +708,9 @@ ObjSize = 2; break; case MVT::i32: - if (NumIntRegs < 2) { + if (NumIntRegs < FASTCC_NUM_INT_ARGS_INREGS) { if (!I->use_empty()) { - unsigned VReg = AddLiveIn(MF,NumIntRegs ? X86::EDX : X86::EAX, + unsigned VReg = AddLiveIn(MF, NumIntRegs ? X86::EDX : X86::EAX, X86::R32RegisterClass); ArgValue = DAG.getCopyFromReg(DAG.getRoot(), VReg, MVT::i32); DAG.setRoot(ArgValue.getValue(1)); @@ -714,7 +721,7 @@ ObjSize = 4; break; case MVT::i64: - if (NumIntRegs == 0) { + if (NumIntRegs+2 <= FASTCC_NUM_INT_ARGS_INREGS) { if (!I->use_empty()) { unsigned BotReg = AddLiveIn(MF, X86::EAX, X86::R32RegisterClass); unsigned TopReg = AddLiveIn(MF, X86::EDX, X86::R32RegisterClass); @@ -725,9 +732,9 @@ ArgValue = DAG.getNode(ISD::BUILD_PAIR, MVT::i64, Low, Hi); } - NumIntRegs = 2; + NumIntRegs += 2; break; - } else if (NumIntRegs == 1) { + } else if (NumIntRegs+1 <= FASTCC_NUM_INT_ARGS_INREGS) { if (!I->use_empty()) { unsigned BotReg = AddLiveIn(MF, X86::EDX, X86::R32RegisterClass); SDOperand Low = DAG.getCopyFromReg(DAG.getRoot(), BotReg, MVT::i32); @@ -742,7 +749,7 @@ ArgValue = DAG.getNode(ISD::BUILD_PAIR, MVT::i64, Low, Hi); } ArgOffset += 4; - NumIntRegs = 2; + NumIntRegs = FASTCC_NUM_INT_ARGS_INREGS; break; } ObjSize = ArgIncrement = 8; @@ -826,7 +833,7 @@ case MVT::i8: case MVT::i16: case MVT::i32: - if (NumIntRegs < 2) { + if (NumIntRegs < FASTCC_NUM_INT_ARGS_INREGS) { ++NumIntRegs; break; } @@ -835,11 +842,11 @@ NumBytes += 4; break; case MVT::i64: - if (NumIntRegs == 0) { - NumIntRegs = 2; + if (NumIntRegs+2 <= FASTCC_NUM_INT_ARGS_INREGS) { + NumIntRegs += 2; break; - } else if (NumIntRegs == 1) { - NumIntRegs = 2; + } else if (NumIntRegs+1 <= FASTCC_NUM_INT_ARGS_INREGS) { + NumIntRegs = FASTCC_NUM_INT_ARGS_INREGS; NumBytes += 4; break; } @@ -872,7 +879,7 @@ case MVT::i8: case MVT::i16: case MVT::i32: - if (NumIntRegs < 2) { + if (NumIntRegs < FASTCC_NUM_INT_ARGS_INREGS) { RegValuesToPass.push_back(Args[i].first); ++NumIntRegs; break; @@ -888,14 +895,17 @@ break; } case MVT::i64: - if (NumIntRegs < 2) { // Can pass part of it in regs? + // Can pass (at least) part of it in regs? + if (NumIntRegs < FASTCC_NUM_INT_ARGS_INREGS) { SDOperand Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Args[i].first, DAG.getConstant(1, MVT::i32)); SDOperand Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Args[i].first, DAG.getConstant(0, MVT::i32)); RegValuesToPass.push_back(Lo); ++NumIntRegs; - if (NumIntRegs < 2) { // Pass both parts in regs? + + // Pass both parts in regs? + if (NumIntRegs < FASTCC_NUM_INT_ARGS_INREGS) { RegValuesToPass.push_back(Hi); ++NumIntRegs; } else { From reid at x10sys.com Fri Mar 17 00:27:58 2006 From: reid at x10sys.com (Reid Spencer) Date: Fri, 17 Mar 2006 00:27:58 -0600 Subject: [llvm-commits] CVS: llvm/lib/VMCore/Makefile Message-ID: <200603170627.AAA18439@zion.cs.uiuc.edu> Changes in directory llvm/lib/VMCore: Makefile updated: 1.11 -> 1.12 --- Log message: Two fixes: 1. Allow building of Intrinsics.gen to work for srcdir != objdir 2. Add a rule for installation of Intrinsics.gen. --- Diffs of the changes: (+5 -1) Makefile | 6 +++++- 1 files changed, 5 insertions(+), 1 deletion(-) Index: llvm/lib/VMCore/Makefile diff -u llvm/lib/VMCore/Makefile:1.11 llvm/lib/VMCore/Makefile:1.12 --- llvm/lib/VMCore/Makefile:1.11 Mon Mar 13 11:57:31 2006 +++ llvm/lib/VMCore/Makefile Fri Mar 17 00:27:06 2006 @@ -18,7 +18,11 @@ include $(LEVEL)/Makefile.common -$(LEVEL)/include/llvm/Intrinsics.gen: $(LEVEL)/include/llvm/Intrinsics.td $(TBLGEN) +GENFILE:=$(PROJ_SRC_ROOT)/include/llvm/Intrinsics.gen + +$(GENFILE): $(PROJ_SRC_ROOT)/include/llvm/Intrinsics.td $(TBLGEN) $(Echo) Building Intrinsics.gen from Intrinsics.td $(Verb) $(TableGen) $< -o $@ -gen-intrinsic +install-local:: $(GENFILE) + $(DataInstall) $(GENFILE) $(PROJ_includedir)/llvm/Intrinsics.gen From lattner at cs.uiuc.edu Fri Mar 17 00:55:20 2006 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Fri, 17 Mar 2006 00:55:20 -0600 Subject: [llvm-commits] CVS: llvm-test/GenerateReport.pl Message-ID: <200603170655.AAA18560@zion.cs.uiuc.edu> Changes in directory llvm-test: GenerateReport.pl updated: 1.27 -> 1.28 --- Log message: Add the ability for reports to request custom hilighting of columns to make it easier to browse reports :) --- Diffs of the changes: (+38 -13) GenerateReport.pl | 51 ++++++++++++++++++++++++++++++++++++++------------- 1 files changed, 38 insertions(+), 13 deletions(-) Index: llvm-test/GenerateReport.pl diff -u llvm-test/GenerateReport.pl:1.27 llvm-test/GenerateReport.pl:1.28 --- llvm-test/GenerateReport.pl:1.27 Wed Apr 27 15:12:30 2005 +++ llvm-test/GenerateReport.pl Fri Mar 17 00:54:41 2006 @@ -96,6 +96,11 @@ open(REPORTDESC, $ReportFN) or die "Couldn't open report description '$ReportFN'!"; +# HilightColumns - Filled in by the report if desired in HTML mode. This +# contains a column number if the HTML version of the output should highlight a +# cell in green/red if it is gt/lt 1.0 by a significant margin. +my %HilightColumns; + my @LatexColumns; # Filled in by report if it supports Latex mode my %LatexColumnFormat; # Filled in by report if supports latex mode my @Graphs; # Filled in by the report if supports graph mode @@ -201,27 +206,47 @@ if ($HTML) { sub printCell { my $Str = shift; + my $ColNo = shift; + my $IsWhite = shift; + my $Attrs = ""; if ($Str eq '|') { - print ""; + $Attrs = " bgcolor='black' width='1'"; + $Str = ""; } else { - #print "
      $Str
      \n"; - print "$Str\n"; - }; ""; - } - sub printLine { -# print "\n"; + # If the user requested that we highlight this column, check to see what + # number it is. If it is > 1.05, we color it green, < 0.95 we use red. + # If it's not a number, ignore it. + if ($HilightColumns{$ColNo}) { + if ($Str =~ m/^([0-9]+).?[0-9.]*$/) { + if ($Str <= 0.85) { + $Attrs = " bgcolor='#FF7070'"; + } elsif ($Str <= 0.95) { + $Attrs = " bgcolor='#FFAAAA'"; + } elsif ($Str >= 1.15) { + $Attrs = " bgcolor='#80FF80'"; + } elsif ($Str >= 1.05) { + $Attrs = " bgcolor='#CCFFCC'"; + } + } + + if (!$IsWhite && $Attrs eq "") { + # If it's not already white, make it white now. + $Attrs = " bgcolor=white"; + } + } + }; + print "$Str"; + ""; } print "\n"; print "\n"; map { - #print ""; $_ = "
      $_
      " - if $_ ne "|"; printCell $_ + if $_ ne "|"; + printCell($_, -1) } @Header; - #print ""; print "\n"; - #print "" x (2*@Header+1); print "\n"; my $RowCount = 0; foreach $Row (@Values) { @@ -229,8 +254,8 @@ $IsWhite = ++$RowCount <= 2; print "\n"; $RowCount = 0 if ($RowCount > 3); - map { printLine($IsWhite); printCell $_ } @$Row; - printLine($IsWhite); + my $ColCount = 0; + map { printCell($_, $ColCount++, $IsWhite); } @$Row; print "\n\n"; } print "\n
      \n"; From lattner at cs.uiuc.edu Fri Mar 17 01:06:46 2006 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Fri, 17 Mar 2006 01:06:46 -0600 Subject: [llvm-commits] CVS: llvm-test/TEST.nightly.report Message-ID: <200603170706.BAA18728@zion.cs.uiuc.edu> Changes in directory llvm-test: TEST.nightly.report updated: 1.38 -> 1.39 --- Log message: Add a new LLC/LLCBETA column, to make it easier to track LLC BETA hilight the ratio columns with red/green to make it easy to tell at a glance if we're winning or losing. --- Diffs of the changes: (+24 -7) TEST.nightly.report | 31 ++++++++++++++++++++++++------- 1 files changed, 24 insertions(+), 7 deletions(-) Index: llvm-test/TEST.nightly.report diff -u llvm-test/TEST.nightly.report:1.38 llvm-test/TEST.nightly.report:1.39 --- llvm-test/TEST.nightly.report:1.38 Wed Nov 2 10:15:15 2005 +++ llvm-test/TEST.nightly.report Fri Mar 17 01:06:34 2006 @@ -22,8 +22,8 @@ sub GCCCBERatio { my ($Cols, $Col) = @_; - my $GCC = $Cols->[$Col-5]; - my $CBE = $Cols->[$Col-4]; + my $GCC = $Cols->[$Col-6]; + my $CBE = $Cols->[$Col-5]; return "n/a" if ($GCC eq "*" or $CBE eq "*"); return sprintf("%3.2f", $GCC/$CBE) if ($GCC >= 0.1 and $CBE >= 0.1); return "-"; @@ -31,8 +31,8 @@ sub GCCLLCRatio { my ($Cols, $Col) = @_; - my $GCC = $Cols->[$Col-6]; - my $LLC = $Cols->[$Col-4]; + my $GCC = $Cols->[$Col-7]; + my $LLC = $Cols->[$Col-5]; return "n/a" if ($GCC eq "*" or $LLC eq "*"); return sprintf("%3.2f", $GCC/$LLC) if ($GCC >= 0.1 and $LLC >= 0.1); return "-"; @@ -40,13 +40,28 @@ sub GCCLLC_BETARatio { my ($Cols, $Col) = @_; - my $GCC = $Cols->[$Col-7]; - my $LLC_BETA = $Cols->[$Col-4]; + my $GCC = $Cols->[$Col-8]; + my $LLC_BETA = $Cols->[$Col-5]; return "n/a" if ($GCC eq "*" or $LLC_BETA eq "*"); return sprintf("%3.2f", $GCC/$LLC_BETA) if ($GCC >= 0.1 and $LLC_BETA >= 0.1); return "-"; } +sub LLCLLC_BETARatio { # LLC/LLC-BETA + my ($Cols, $Col) = @_; + my $LLC = $Cols->[$Col-7]; + my $LLC_BETA = $Cols->[$Col-6]; + return "n/a" if ($LLC eq "*" or $LLC_BETA eq "*"); + return sprintf("%3.2f", $LLC/$LLC_BETA) if ($LLC >= 0.1 and $LLC_BETA >= 0.1); + return "-"; +} + +# highlight the RATIO columns with green/red. +$HilightColumns{14} = 1; +$HilightColumns{15} = 1; +$HilightColumns{16} = 1; +$HilightColumns{17} = 1; + # These are the columns for the report. The first entry is the header for the # column, the second is the regex to use to match the value. Empty list create # separators, and closures may be put in for custom processing. @@ -66,7 +81,9 @@ ["LLC" , 'TEST-RESULT-llc-time: program\s*([.0-9m:]+)', \&FormatTime], ["LLC-BETA" , 'TEST-RESULT-llc-beta-time: program\s*([.0-9m:]+)',\&FormatTime], ["JIT" , 'TEST-RESULT-jit-time: program\s*([.0-9m:]+)', \&FormatTime], + [], ["GCC/
      CBE" , \&GCCCBERatio], ["GCC/
      LLC" , \&GCCLLCRatio], - ["GCC/
      LLC-BETA" , \&GCCLLC_BETARatio] + ["GCC/
      LLC-BETA" , \&GCCLLC_BETARatio], + ["LLC/
      LLC-BETA" , \&LLCLLC_BETARatio] ); From reid at x10sys.com Fri Mar 17 01:39:56 2006 From: reid at x10sys.com (Reid Spencer) Date: Fri, 17 Mar 2006 01:39:56 -0600 Subject: [llvm-commits] CVS: llvm/lib/VMCore/Makefile Message-ID: <200603170739.BAA18855@zion.cs.uiuc.edu> Changes in directory llvm/lib/VMCore: Makefile updated: 1.12 -> 1.13 --- Log message: Fix use of LEVEL. --- Diffs of the changes: (+1 -1) Makefile | 2 +- 1 files changed, 1 insertion(+), 1 deletion(-) Index: llvm/lib/VMCore/Makefile diff -u llvm/lib/VMCore/Makefile:1.12 llvm/lib/VMCore/Makefile:1.13 --- llvm/lib/VMCore/Makefile:1.12 Fri Mar 17 00:27:06 2006 +++ llvm/lib/VMCore/Makefile Fri Mar 17 01:39:44 2006 @@ -9,7 +9,7 @@ LEVEL = ../.. LIBRARYNAME = LLVMCore -BUILT_SOURCES = $(LEVEL)/include/llvm/Intrinsics.gen +BUILT_SOURCES = $(PROJ_SRC_ROOT)/include/llvm/Intrinsics.gen include $(LEVEL)/Makefile.config ifeq ($(ARCH),Alpha) From reid at x10sys.com Fri Mar 17 02:04:56 2006 From: reid at x10sys.com (Reid Spencer) Date: Fri, 17 Mar 2006 02:04:56 -0600 Subject: [llvm-commits] CVS: llvm/docs/Projects.html Message-ID: <200603170804.CAA19023@zion.cs.uiuc.edu> Changes in directory llvm/docs: Projects.html updated: 1.21 -> 1.22 --- Log message: Fix a typo. --- Diffs of the changes: (+2 -2) Projects.html | 4 ++-- 1 files changed, 2 insertions(+), 2 deletions(-) Index: llvm/docs/Projects.html diff -u llvm/docs/Projects.html:1.21 llvm/docs/Projects.html:1.22 --- llvm/docs/Projects.html:1.21 Thu Mar 16 10:14:59 2006 +++ llvm/docs/Projects.html Fri Mar 17 02:04:25 2006 @@ -105,7 +105,7 @@ it specifies a relative path to the llvm/autoconf directory.
    • LLVM_CONFIG_PROJECT. Just leave this alone.
    • AC_CONFIG_SRCDIR. Specify a path to a file name that identifies - your project; or just leave it at Makefile.config.in
      • + your project; or just leave it at Makefile.common.in
    • AC_CONFIG_FILES. Do not change.
    • AC_CONFIG_MAKEFILE. Use one of these macros for each Makefile that your project uses. This macro arranges for your makefiles to be copied @@ -453,7 +453,7 @@ John Criswell
      The LLVM Compiler Infrastructure
      - Last modified: $Date: 2006/03/16 16:14:59 $ + Last modified: $Date: 2006/03/17 08:04:25 $ From lattner at cs.uiuc.edu Fri Mar 17 11:28:00 2006 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Fri, 17 Mar 2006 11:28:00 -0600 Subject: [llvm-commits] CVS: llvm/lib/Target/X86/X86ISelLowering.cpp Message-ID: <200603171728.LAA01698@zion.cs.uiuc.edu> Changes in directory llvm/lib/Target/X86: X86ISelLowering.cpp updated: 1.109 -> 1.110 --- Log message: Disable x86 fastcc from passing args in registers --- Diffs of the changes: (+18 -6) X86ISelLowering.cpp | 24 ++++++++++++++++++------ 1 files changed, 18 insertions(+), 6 deletions(-) Index: llvm/lib/Target/X86/X86ISelLowering.cpp diff -u llvm/lib/Target/X86/X86ISelLowering.cpp:1.109 llvm/lib/Target/X86/X86ISelLowering.cpp:1.110 --- llvm/lib/Target/X86/X86ISelLowering.cpp:1.109 Thu Mar 16 23:10:20 2006 +++ llvm/lib/Target/X86/X86ISelLowering.cpp Fri Mar 17 11:27:47 2006 @@ -639,12 +639,24 @@ return VReg; } -enum { - // FASTCC_NUM_INT_ARGS_INREGS - This is the max number of integer arguments - // to pass in registers. 0 is none, 1 is is "use EAX", 2 is "use EAX and - // EDX". Anything more is illegal. - FASTCC_NUM_INT_ARGS_INREGS = 2 -}; +// FASTCC_NUM_INT_ARGS_INREGS - This is the max number of integer arguments +// to pass in registers. 0 is none, 1 is is "use EAX", 2 is "use EAX and +// EDX". Anything more is illegal. +// +// FIXME: The linscan register allocator currently has problem with +// coallescing. At the time of this writing, whenever it decides to coallesce +// a physreg with a virtreg, this increases the size of the physreg's live +// range, and the live range cannot ever be reduced. This causes problems if +// too many physregs are coalleced with virtregs, which can cause the register +// allocator to wedge itself. +// +// This code triggers this problem more often if we pass args in registers, +// so disable it until this is fixed. +// +// NOTE: this isn't marked const, so that GCC doesn't emit annoying warnings +// about code being dead. +// +static unsigned FASTCC_NUM_INT_ARGS_INREGS = 0; std::vector From reid at x10sys.com Fri Mar 17 11:43:13 2006 From: reid at x10sys.com (Reid Spencer) Date: Fri, 17 Mar 2006 11:43:13 -0600 Subject: [llvm-commits] CVS: llvm/utils/NightlyTest.pl Message-ID: <200603171743.LAA01824@zion.cs.uiuc.edu> Changes in directory llvm/utils: NightlyTest.pl updated: 1.104 -> 1.105 --- Log message: Use the tag instead of 
       tag to get code/file/warning lists to
wrap but also still be in a fixed-width font.


---
Diffs of the changes:  (+1 -1)

 NightlyTest.pl |    2 +-
 1 files changed, 1 insertion(+), 1 deletion(-)


Index: llvm/utils/NightlyTest.pl
diff -u llvm/utils/NightlyTest.pl:1.104 llvm/utils/NightlyTest.pl:1.105
--- llvm/utils/NightlyTest.pl:1.104	Wed Feb  8 03:08:06 2006
+++ llvm/utils/NightlyTest.pl	Fri Mar 17 11:43:01 2006
@@ -151,7 +151,7 @@
 
 sub AddPreTag {  # Add pre tags around nonempty list, or convert to "none"
   $_ = shift;
-  if (length) { return "
        $_
      "; } else { "none
      "; }
+  if (length) { return "
        $_
      "; } else { "none
      "; }
 }
 
 sub ChangeDir { # directory, logical name





From lattner at cs.uiuc.edu  Fri Mar 17 12:01:29 2006
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Fri, 17 Mar 2006 12:01:29 -0600
Subject: [llvm-commits] 
	CVS: llvm/test/Regression/CFrontend/2006-03-17-KnRMismatch.c
Message-ID: <200603171801.MAA01990@zion.cs.uiuc.edu>



Changes in directory llvm/test/Regression/CFrontend:

2006-03-17-KnRMismatch.c added (r1.1)
---
Log message:

new testcase that broke the new f.e.


---
Diffs of the changes:  (+8 -0)

 2006-03-17-KnRMismatch.c |    8 ++++++++
 1 files changed, 8 insertions(+)


Index: llvm/test/Regression/CFrontend/2006-03-17-KnRMismatch.c
diff -c /dev/null llvm/test/Regression/CFrontend/2006-03-17-KnRMismatch.c:1.1
*** /dev/null	Fri Mar 17 12:01:27 2006
--- llvm/test/Regression/CFrontend/2006-03-17-KnRMismatch.c	Fri Mar 17 12:01:17 2006
***************
*** 0 ****
--- 1,8 ----
+ // RUN: %llvmgcc %s -S -o -
+ 
+ void regnode(int op);
+ 
+ void regnode(op)
+ char op;
+ {
+ }





From evan.cheng at apple.com  Fri Mar 17 13:46:06 2006
From: evan.cheng at apple.com (Evan Cheng)
Date: Fri, 17 Mar 2006 13:46:06 -0600
Subject: [llvm-commits] 
	CVS: llvm/test/Regression/CodeGen/X86/loop-strength-reduce.ll
Message-ID: <200603171946.NAA03169@zion.cs.uiuc.edu>



Changes in directory llvm/test/Regression/CodeGen/X86:

loop-strength-reduce.ll added (r1.1)
---
Log message:

Add a lsr common loop invariant hoisting test case

---
Diffs of the changes:  (+28 -0)

 loop-strength-reduce.ll |   28 ++++++++++++++++++++++++++++
 1 files changed, 28 insertions(+)


Index: llvm/test/Regression/CodeGen/X86/loop-strength-reduce.ll
diff -c /dev/null llvm/test/Regression/CodeGen/X86/loop-strength-reduce.ll:1.1
*** /dev/null	Fri Mar 17 13:46:04 2006
--- llvm/test/Regression/CodeGen/X86/loop-strength-reduce.ll	Fri Mar 17 13:45:54 2006
***************
*** 0 ****
--- 1,28 ----
+ ; RUN: llvm-as < %s | llc -march=x86 -enable-x86-lsr | grep 'A(' | wc -l | grep 1
+ ;
+ ; Make sure the common loop invariant _A(reg) is hoisted up to preheader.
+ 
+ %A = internal global [16 x [16 x int]] zeroinitializer, align 32
+ 
+ void %test(int %row, int %N) {
+ entry:
+ 	%N = cast int %N to uint
+ 	%tmp5 = setgt int %N, 0
+ 	br bool %tmp5, label %cond_true, label %return
+ 
+ cond_true:
+ 	%indvar = phi uint [ 0, %entry ], [ %indvar.next, %cond_true ]
+ 	%i.0.0 = cast uint %indvar to int
+ 	%tmp2 = add int %i.0.0, 1
+ 	%tmp = getelementptr [16 x [16 x int]]* %A, int 0, int %row, int %tmp2
+ 	store int 4, int* %tmp
+ 	%tmp5 = add int %i.0.0, 2
+ 	%tmp7 = getelementptr [16 x [16 x int]]* %A, int 0, int %row, int %tmp5
+ 	store int 5, int* %tmp7
+ 	%indvar.next = add uint %indvar, 1
+ 	%exitcond = seteq uint %indvar.next, %N
+ 	br bool %exitcond, label %return, label %cond_true
+ 
+ return:
+ 	ret void
+ }





From evan.cheng at apple.com  Fri Mar 17 13:52:35 2006
From: evan.cheng at apple.com (Evan Cheng)
Date: Fri, 17 Mar 2006 13:52:35 -0600
Subject: [llvm-commits] 
	CVS: llvm/lib/Transforms/Scalar/LoopStrengthReduce.cpp
Message-ID: <200603171952.NAA03258@zion.cs.uiuc.edu>



Changes in directory llvm/lib/Transforms/Scalar:

LoopStrengthReduce.cpp updated: 1.77 -> 1.78
---
Log message:

Allow users of iv / stride to be rewritten with expression that is a multiply
of a smaller stride even if they have a common loop invariant expression part.


---
Diffs of the changes:  (+83 -41)

 LoopStrengthReduce.cpp |  124 ++++++++++++++++++++++++++++++++-----------------
 1 files changed, 83 insertions(+), 41 deletions(-)


Index: llvm/lib/Transforms/Scalar/LoopStrengthReduce.cpp
diff -u llvm/lib/Transforms/Scalar/LoopStrengthReduce.cpp:1.77 llvm/lib/Transforms/Scalar/LoopStrengthReduce.cpp:1.78
--- llvm/lib/Transforms/Scalar/LoopStrengthReduce.cpp:1.77	Thu Mar 16 15:53:05 2006
+++ llvm/lib/Transforms/Scalar/LoopStrengthReduce.cpp	Fri Mar 17 13:52:23 2006
@@ -180,6 +180,8 @@
 
     void OptimizeIndvars(Loop *L);
 
+    unsigned CheckForIVReuse(const SCEVHandle &Stride, IVExpr &IV);
+
     void StrengthReduceStridedIVUsers(const SCEVHandle &Stride,
                                       IVUsersOfOneStride &Uses,
                                       Loop *L, bool isOnlyStride);
@@ -858,6 +860,44 @@
 }
 
 
+/// CheckForIVReuse - Returns the multiple if the stride is the multiple
+/// of a previous stride and it is a legal value for the target addressing
+/// mode scale component. This allows the users of this stride to be rewritten
+/// as prev iv * factor. It returns 1 if no reuse is possible.
+unsigned LoopStrengthReduce::CheckForIVReuse(const SCEVHandle &Stride,
+                                             IVExpr &IV) {
+  if (!TLI)
+    return 1;
+
+  if (SCEVConstant *SC = dyn_cast(Stride)) {
+    unsigned SInt = SC->getValue()->getRawValue();
+    if (SInt == 1)
+      return 1;
+
+    for (TargetLowering::legal_am_scale_iterator
+           I = TLI->legal_am_scale_begin(), E = TLI->legal_am_scale_end();
+         I != E; ++I) {
+      unsigned Scale = *I;
+      if (SInt >= Scale && (SInt % Scale) != 0)
+        continue;
+      std::map::iterator SI =
+        IVsByStride.find(SCEVUnknown::getIntegerSCEV(SInt/Scale, Type::UIntTy));
+      if (SI == IVsByStride.end())
+        continue;
+      for (std::vector::iterator II = SI->second.IVs.begin(),
+             IE = SI->second.IVs.end(); II != IE; ++II)
+        // FIXME: Only handle base == 0 for now.
+        if (isZero(II->Base)) {
+          IV = *II;
+          return Scale;
+        }
+    }
+  }
+
+  return 1;
+}
+
+
 /// StrengthReduceStridedIVUsers - Strength reduce all of the users of a single
 /// stride of IV.  All of the users may have different starting values, and this
 /// may not be the only stride (we know it is if isOnlyStride is true).
@@ -883,7 +923,19 @@
     assert(UsersToProcess.back().Base->isLoopInvariant(L) &&
            "Base value is not loop invariant!");
   }
-  
+
+  // Check if it is possible to reuse a IV with stride that is factor of this
+  // stride. And the multiple is a number that can be encoded in the scale
+  // field of the target addressing mode.
+  PHINode *NewPHI = NULL;
+  Value   *IncV   = NULL;
+  IVExpr   ReuseIV(Stride, NULL, NULL);
+  unsigned RewriteFactor = CheckForIVReuse(Stride, ReuseIV);
+  if (RewriteFactor > 1) {
+    NewPHI = ReuseIV.PHI;
+    IncV   = ReuseIV.IncV;
+  }
+
   // We now have a whole bunch of uses of like-strided induction variables, but
   // they might all have different bases.  We want to emit one PHI node for this
   // stride which we fold as many common expressions (between the IVs) into as
@@ -935,55 +987,26 @@
   
   BasicBlock *LatchBlock = L->getLoopLatch();
 
-  unsigned RewriteFactor = 1;
-  PHINode *NewPHI = NULL;
-  Value   *IncV   = NULL;
-  // FIXME: Only handle base == 0 for now.
-  if (TLI && isZero(CommonExprs)) {
-    if (SCEVConstant *SC = dyn_cast(Stride)) {
-      unsigned SInt = SC->getValue()->getRawValue();
-      for (TargetLowering::legal_am_scale_iterator
-             I = TLI->legal_am_scale_begin(), E = TLI->legal_am_scale_end();
-           I != E; ++I) {
-        unsigned Scale = *I;
-        if ((SInt % Scale) != 0)
-          continue;
-        std::map::iterator SI =
-        IVsByStride.find(SCEVUnknown::getIntegerSCEV(SInt/Scale, Type::UIntTy));
-        if (SI == IVsByStride.end())
-          continue;
-        for (std::vector::iterator II = SI->second.IVs.begin(),
-               IE = SI->second.IVs.end(); II != IE; ++II)
-          if (isZero(II->Base)) {
-            RewriteFactor = Scale;
-            NewPHI = II->PHI;
-            IncV   = II->IncV;
-            break;
-          }
-        if (RewriteFactor != 1)
-          break;
-      }
-    }
-  }
-
   const Type *ReplacedTy = CommonExprs->getType();
+
+  // Emit the initial base value into the loop preheader.
+  Value *CommonBaseV
+    = PreheaderRewriter.expandCodeFor(CommonExprs, PreInsertPt,
+                                      ReplacedTy);
+
   if (RewriteFactor == 1) {
     // Create a new Phi for this base, and stick it in the loop header.
     NewPHI = new PHINode(ReplacedTy, "iv.", PhiInsertBefore);
     ++NumInserted;
   
+    // Add common base to the new Phi node.
+    NewPHI->addIncoming(CommonBaseV, Preheader);
+
     // Insert the stride into the preheader.
     Value *StrideV = PreheaderRewriter.expandCodeFor(Stride, PreInsertPt,
                                                      ReplacedTy);
     if (!isa(StrideV)) ++NumVariable;
 
-
-    // Emit the initial base value into the loop preheader, and add it to the
-    // Phi node.
-    Value *PHIBaseV = PreheaderRewriter.expandCodeFor(CommonExprs, PreInsertPt,
-                                                      ReplacedTy);
-    NewPHI->addIncoming(PHIBaseV, Preheader);
-  
     // Emit the increment of the base value before the terminator of the loop
     // latch block, and add it to the Phi node.
     SCEVHandle IncExp = SCEVAddExpr::get(SCEVUnknown::get(NewPHI),
@@ -994,7 +1017,16 @@
     IncV->setName(NewPHI->getName()+".inc");
     NewPHI->addIncoming(IncV, LatchBlock);
 
+    // Remember this in case a later stride is multiple of this.
     IVsByStride[Stride].addIV(CommonExprs, NewPHI, IncV);
+  } else {
+    Constant *C = dyn_cast(CommonBaseV);
+    if (!C ||
+        (!C->isNullValue() &&
+         !isTargetConstant(SCEVUnknown::get(CommonBaseV), TLI)))
+      // We want the common base emitted into the preheader!
+      CommonBaseV = new CastInst(CommonBaseV, CommonBaseV->getType(),
+                                 "commonbase", PreInsertPt);
   }
 
   // Sort by the base value, so that all IVs with identical bases are next to
@@ -1044,10 +1076,20 @@
 
       // If we are reusing the iv, then it must be multiplied by a constant
       // factor take advantage of addressing mode scale component.
-      if (RewriteFactor != 1)
+      if (RewriteFactor != 1) {
         RewriteExpr =
           SCEVMulExpr::get(SCEVUnknown::getIntegerSCEV(RewriteFactor,
-                                          RewriteExpr->getType()), RewriteExpr);
+                                                       RewriteExpr->getType()),
+                           RewriteExpr);
+
+        // The common base is emitted in the loop preheader. But since we
+        // are reusing an IV, it has not been used to initialize the PHI node.
+        // Add it to the expression used to rewrite the uses.
+        if (!isa(CommonBaseV) ||
+            !cast(CommonBaseV)->isNullValue())
+          RewriteExpr = SCEVAddExpr::get(RewriteExpr,
+                                         SCEVUnknown::get(CommonBaseV));
+      }
 
       // Now that we know what we need to do, insert code before User for the
       // immediate and any loop-variant expressions.





From lattner at cs.uiuc.edu  Fri Mar 17 13:53:53 2006
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Fri, 17 Mar 2006 13:53:53 -0600
Subject: [llvm-commits] CVS: llvm/include/llvm/CodeGen/SelectionDAGNodes.h 
Message-ID: <200603171953.NAA03326@zion.cs.uiuc.edu>



Changes in directory llvm/include/llvm/CodeGen:

SelectionDAGNodes.h updated: 1.111 -> 1.112
---
Log message:

add a couple of enum values


---
Diffs of the changes:  (+12 -1)

 SelectionDAGNodes.h |   13 ++++++++++++-
 1 files changed, 12 insertions(+), 1 deletion(-)


Index: llvm/include/llvm/CodeGen/SelectionDAGNodes.h
diff -u llvm/include/llvm/CodeGen/SelectionDAGNodes.h:1.111 llvm/include/llvm/CodeGen/SelectionDAGNodes.h:1.112
--- llvm/include/llvm/CodeGen/SelectionDAGNodes.h:1.111	Thu Mar 16 19:40:33 2006
+++ llvm/include/llvm/CodeGen/SelectionDAGNodes.h	Fri Mar 17 13:53:41 2006
@@ -146,7 +146,12 @@
     // are both floating point.  X and the result must have the same type.
     // FCOPYSIGN(f32, f64) is allowed.
     FCOPYSIGN,
+
+    /// INSERT_VECTOR_ELT(VECTOR, VAL, IDX) - Returns VECTOR (a legal packed
+    /// type) with the element at IDX replaced with VAL.
+    INSERT_VECTOR_ELT,
     
+    // BINOP(LHS, RHS,  COUNT,TYPE)
     // Simple abstract vector operators.  Unlike the integer and floating point
     // binary operators, these nodes also take two additional operands:
     // a constant element count, and a value type node indicating the type of
@@ -156,6 +161,12 @@
     VADD, VSUB, VMUL, VSDIV, VUDIV,
     VAND, VOR, VXOR,
 
+    /// VINSERT_VECTOR_ELT(VECTOR, VAL, IDX,  COUNT,TYPE) - Given a vector
+    /// VECTOR, an element ELEMENT, and a (potentially variable) index IDX,
+    /// return an vector with the specified element of VECTOR replaced with VAL.
+    /// COUNT and TYPE specify the type of vector, as is standard for V* nodes.
+    VINSERT_VECTOR_ELT,
+    
     // MULHU/MULHS - Multiply high - Multiply two integers of type iN, producing
     // an unsigned/signed value of type i[2*n], then return the top part.
     MULHU, MULHS,
@@ -168,7 +179,7 @@
     // Counting operators
     CTTZ, CTLZ, CTPOP,
 
-    // Select
+    // Select(COND, TRUEVAL, FALSEVAL)
     SELECT, 
     
     // Select with condition operator - This selects between a true value and 





From lattner at cs.uiuc.edu  Fri Mar 17 13:54:11 2006
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Fri, 17 Mar 2006 13:54:11 -0600
Subject: [llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp 
Message-ID: <200603171954.NAA03359@zion.cs.uiuc.edu>



Changes in directory llvm/lib/CodeGen/SelectionDAG:

SelectionDAG.cpp updated: 1.271 -> 1.272
---
Log message:

add a couple enum values


---
Diffs of the changes:  (+3 -1)

 SelectionDAG.cpp |    4 +++-
 1 files changed, 3 insertions(+), 1 deletion(-)


Index: llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp:1.271 llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp:1.272
--- llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp:1.271	Thu Mar 16 19:40:33 2006
+++ llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp	Fri Mar 17 13:53:59 2006
@@ -2649,10 +2649,12 @@
   case ISD::VADD:   return "vadd";
   case ISD::VSUB:   return "vsub";
   case ISD::VMUL:   return "vmul";
-    
+
   case ISD::SETCC:       return "setcc";
   case ISD::SELECT:      return "select";
   case ISD::SELECT_CC:   return "select_cc";
+  case ISD::INSERT_VECTOR_ELT: return "insert_vector_elt";
+  case ISD::VINSERT_VECTOR_ELT: return "vinsert_vector_elt";
   case ISD::ADDC:        return "addc";
   case ISD::ADDE:        return "adde";
   case ISD::SUBC:        return "subc";





From evan.cheng at apple.com  Fri Mar 17 13:56:04 2006
From: evan.cheng at apple.com (Evan Cheng)
Date: Fri, 17 Mar 2006 13:56:04 -0600
Subject: [llvm-commits] CVS: llvm/lib/Target/X86/X86InstrFPStack.td
	X86InstrInfo.td X86InstrSSE.td 
Message-ID: <200603171956.NAA03393@zion.cs.uiuc.edu>



Changes in directory llvm/lib/Target/X86:

X86InstrFPStack.td updated: 1.3 -> 1.4
X86InstrInfo.td updated: 1.254 -> 1.255
X86InstrSSE.td updated: 1.5 -> 1.6
---
Log message:

Move some pattern fragments to the right files.


---
Diffs of the changes:  (+37 -27)

 X86InstrFPStack.td |   26 ++++++++++++++++++++++++++
 X86InstrInfo.td    |   28 +---------------------------
 X86InstrSSE.td     |   10 ++++++++++
 3 files changed, 37 insertions(+), 27 deletions(-)


Index: llvm/lib/Target/X86/X86InstrFPStack.td
diff -u llvm/lib/Target/X86/X86InstrFPStack.td:1.3 llvm/lib/Target/X86/X86InstrFPStack.td:1.4
--- llvm/lib/Target/X86/X86InstrFPStack.td:1.3	Tue Feb 21 14:00:20 2006
+++ llvm/lib/Target/X86/X86InstrFPStack.td	Fri Mar 17 13:55:52 2006
@@ -13,6 +13,32 @@
 //
 //===----------------------------------------------------------------------===//
 
+//===----------------------------------------------------------------------===//
+// FPStack pattern fragments
+//===----------------------------------------------------------------------===//
+
+def fp32imm0 : PatLeaf<(f32 fpimm), [{
+  return N->isExactlyValue(+0.0);
+}]>;
+
+def fp64imm0 : PatLeaf<(f64 fpimm), [{
+  return N->isExactlyValue(+0.0);
+}]>;
+
+def fp64immneg0 : PatLeaf<(f64 fpimm), [{
+  return N->isExactlyValue(-0.0);
+}]>;
+
+def fp64imm1 : PatLeaf<(f64 fpimm), [{
+  return N->isExactlyValue(+1.0);
+}]>;
+
+def fp64immneg1 : PatLeaf<(f64 fpimm), [{
+  return N->isExactlyValue(-1.0);
+}]>;
+
+def extloadf64f32  : PatFrag<(ops node:$ptr), (f64 (extload node:$ptr, f32))>;
+
 // Some 'special' instructions
 let usesCustomDAGSchedInserter = 1 in {  // Expanded by the scheduler.
   def FP_TO_INT16_IN_MEM : I<0, Pseudo,


Index: llvm/lib/Target/X86/X86InstrInfo.td
diff -u llvm/lib/Target/X86/X86InstrInfo.td:1.254 llvm/lib/Target/X86/X86InstrInfo.td:1.255
--- llvm/lib/Target/X86/X86InstrInfo.td:1.254	Thu Mar 16 20:24:04 2006
+++ llvm/lib/Target/X86/X86InstrInfo.td	Fri Mar 17 13:55:52 2006
@@ -319,36 +319,14 @@
   return (unsigned)N->getValue() == (unsigned char)N->getValue();
 }]>;
 
-def fp32imm0 : PatLeaf<(f32 fpimm), [{
-  return N->isExactlyValue(+0.0);
-}]>;
-
-def fp64imm0 : PatLeaf<(f64 fpimm), [{
-  return N->isExactlyValue(+0.0);
-}]>;
-
-def fp64immneg0 : PatLeaf<(f64 fpimm), [{
-  return N->isExactlyValue(-0.0);
-}]>;
-
-def fp64imm1 : PatLeaf<(f64 fpimm), [{
-  return N->isExactlyValue(+1.0);
-}]>;
-
-def fp64immneg1 : PatLeaf<(f64 fpimm), [{
-  return N->isExactlyValue(-1.0);
-}]>;
-
 // Helper fragments for loads.
 def loadi8  : PatFrag<(ops node:$ptr), (i8  (load node:$ptr))>;
 def loadi16 : PatFrag<(ops node:$ptr), (i16 (load node:$ptr))>;
 def loadi32 : PatFrag<(ops node:$ptr), (i32 (load node:$ptr))>;
+
 def loadf32 : PatFrag<(ops node:$ptr), (f32 (load node:$ptr))>;
 def loadf64 : PatFrag<(ops node:$ptr), (f64 (load node:$ptr))>;
 
-def X86loadv4f32 : PatFrag<(ops node:$ptr), (v4f32 (load node:$ptr))>;
-def X86loadv2f64 : PatFrag<(ops node:$ptr), (v2f64 (load node:$ptr))>;
-
 def sextloadi16i1  : PatFrag<(ops node:$ptr), (i16 (sextload node:$ptr, i1))>;
 def sextloadi32i1  : PatFrag<(ops node:$ptr), (i32 (sextload node:$ptr, i1))>;
 def sextloadi16i8  : PatFrag<(ops node:$ptr), (i16 (sextload node:$ptr, i8))>;
@@ -363,10 +341,6 @@
 def zextloadi32i16 : PatFrag<(ops node:$ptr), (i32 (zextload node:$ptr, i16))>;
 
 def extloadi8i1    : PatFrag<(ops node:$ptr), (i8  (extload node:$ptr, i1))>;
-def extloadf64f32  : PatFrag<(ops node:$ptr), (f64 (extload node:$ptr, f32))>;
-
-def X86loadpf32    : PatFrag<(ops node:$ptr), (f32   (X86loadp node:$ptr))>;
-def X86loadpf64    : PatFrag<(ops node:$ptr), (f64   (X86loadp node:$ptr))>;
 
 //===----------------------------------------------------------------------===//
 // Instruction templates...


Index: llvm/lib/Target/X86/X86InstrSSE.td
diff -u llvm/lib/Target/X86/X86InstrSSE.td:1.5 llvm/lib/Target/X86/X86InstrSSE.td:1.6
--- llvm/lib/Target/X86/X86InstrSSE.td:1.5	Tue Feb 21 20:26:30 2006
+++ llvm/lib/Target/X86/X86InstrSSE.td	Fri Mar 17 13:55:52 2006
@@ -14,6 +14,16 @@
 //===----------------------------------------------------------------------===//
 
 //===----------------------------------------------------------------------===//
+// SSE pattern fragments
+//===----------------------------------------------------------------------===//
+
+def X86loadpf32  : PatFrag<(ops node:$ptr), (f32   (X86loadp node:$ptr))>;
+def X86loadpf64  : PatFrag<(ops node:$ptr), (f64   (X86loadp node:$ptr))>;
+
+def X86loadv4f32 : PatFrag<(ops node:$ptr), (v4f32 (load node:$ptr))>;
+def X86loadv2f64 : PatFrag<(ops node:$ptr), (v2f64 (load node:$ptr))>;
+
+//===----------------------------------------------------------------------===//
 // SSE scalar FP Instructions
 //===----------------------------------------------------------------------===//
 





From lattner at cs.uiuc.edu  Fri Mar 17 14:04:52 2006
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Fri, 17 Mar 2006 14:04:52 -0600
Subject: [llvm-commits] CVS: llvm/test/Regression/CodeGen/Generic/vector.ll 
Message-ID: <200603172004.OAA03532@zion.cs.uiuc.edu>



Changes in directory llvm/test/Regression/CodeGen/Generic:

vector.ll added (r1.1)
---
Log message:

new testcase


---
Diffs of the changes:  (+41 -0)

 vector.ll |   41 +++++++++++++++++++++++++++++++++++++++++
 1 files changed, 41 insertions(+)


Index: llvm/test/Regression/CodeGen/Generic/vector.ll
diff -c /dev/null llvm/test/Regression/CodeGen/Generic/vector.ll:1.1
*** /dev/null	Fri Mar 17 14:04:50 2006
--- llvm/test/Regression/CodeGen/Generic/vector.ll	Fri Mar 17 14:04:40 2006
***************
*** 0 ****
--- 1,41 ----
+ ; RUN: llvm-as < %s | llc
+ ; Test that vectors are scalarized/lowered correctly.
+ 
+ %f1 = type <1 x float>
+ %f2 = type <2 x float>
+ %f4 = type <4 x float>
+ %f8 = type <8 x float>
+ 
+ implementation
+ 
+ void %test_f1(%f1 *%P, %f1* %Q, %f1 *%S) {
+   %p = load %f1 *%P
+   %q = load %f1* %Q
+   %R = add %f1 %p, %q
+   store %f1 %R, %f1 *%S
+   ret void
+ }
+ 
+ void %test_f2(%f2 *%P, %f2* %Q, %f2 *%S) {
+   %p = load %f2* %P
+   %q = load %f2* %Q
+   %R = add %f2 %p, %q
+   store %f2 %R, %f2 *%S
+   ret void
+ }
+ 
+ void %test_f4(%f4 *%P, %f4* %Q, %f4 *%S) {
+   %p = load %f4* %P
+   %q = load %f4* %Q
+   %R = add %f4 %p, %q
+   store %f4 %R, %f4 *%S
+   ret void
+ }
+ 
+ void %test_f8(%f8 *%P, %f8* %Q, %f8 *%S) {
+   %p = load %f8* %P
+   %q = load %f8* %Q
+   %R = add %f8 %p, %q
+   store %f8 %R, %f8 *%S
+   ret void
+ }





From evan.cheng at apple.com  Fri Mar 17 14:31:53 2006
From: evan.cheng at apple.com (Evan Cheng)
Date: Fri, 17 Mar 2006 14:31:53 -0600
Subject: [llvm-commits] CVS: llvm/lib/Target/X86/X86ISelLowering.cpp 
Message-ID: <200603172031.OAA03776@zion.cs.uiuc.edu>



Changes in directory llvm/lib/Target/X86:

X86ISelLowering.cpp updated: 1.110 -> 1.111
---
Log message:

Darwin should use _setjmp/_longjmp instead of setjmp/longjmp.


---
Diffs of the changes:  (+4 -0)

 X86ISelLowering.cpp |    4 ++++
 1 files changed, 4 insertions(+)


Index: llvm/lib/Target/X86/X86ISelLowering.cpp
diff -u llvm/lib/Target/X86/X86ISelLowering.cpp:1.110 llvm/lib/Target/X86/X86ISelLowering.cpp:1.111
--- llvm/lib/Target/X86/X86ISelLowering.cpp:1.110	Fri Mar 17 11:27:47 2006
+++ llvm/lib/Target/X86/X86ISelLowering.cpp	Fri Mar 17 14:31:41 2006
@@ -50,6 +50,10 @@
   setShiftAmountFlavor(Mask);   // shl X, 32 == shl X, 0
   setStackPointerRegisterToSaveRestore(X86::ESP);
 
+  if (!TM.getSubtarget().isTargetDarwin())
+    // Darwin should use _setjmp/_longjmp instead of setjmp/longjmp.
+    setUseUnderscoreSetJmpLongJmp(true);
+    
   // Add legal addressing mode scale values.
   addLegalAddressScale(8);
   addLegalAddressScale(4);





From natebegeman at mac.com  Fri Mar 17 16:39:57 2006
From: natebegeman at mac.com (Nate Begeman)
Date: Fri, 17 Mar 2006 16:39:57 -0600
Subject: [llvm-commits] CVS: llvm/test/Regression/CodeGen/PowerPC/neg.ll 
Message-ID: <200603172239.QAA04583@zion.cs.uiuc.edu>



Changes in directory llvm/test/Regression/CodeGen/PowerPC:

neg.ll added (r1.1)
---
Log message:

Add a missing testcase


---
Diffs of the changes:  (+6 -0)

 neg.ll |    6 ++++++
 1 files changed, 6 insertions(+)


Index: llvm/test/Regression/CodeGen/PowerPC/neg.ll
diff -c /dev/null llvm/test/Regression/CodeGen/PowerPC/neg.ll:1.1
*** /dev/null	Fri Mar 17 16:39:55 2006
--- llvm/test/Regression/CodeGen/PowerPC/neg.ll	Fri Mar 17 16:39:45 2006
***************
*** 0 ****
--- 1,6 ----
+ ; RUN: llvm-as < %s | llc -march=ppc32 | grep neg
+ 
+ int %test(int %X) {
+     %Y = sub int 0, %X
+ 	ret int %Y
+ }





From natebegeman at mac.com  Fri Mar 17 16:41:49 2006
From: natebegeman at mac.com (Nate Begeman)
Date: Fri, 17 Mar 2006 16:41:49 -0600
Subject: [llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCInstrInfo.td 
Message-ID: <200603172241.QAA04614@zion.cs.uiuc.edu>



Changes in directory llvm/lib/Target/PowerPC:

PPCInstrInfo.td updated: 1.186 -> 1.187
---
Log message:

Fix subfic to match subc by default instead of sub so that it is correctly
cost-modeled as producing a flag.  This fixes the test I just added for neg


---
Diffs of the changes:  (+2 -2)

 PPCInstrInfo.td |    4 ++--
 1 files changed, 2 insertions(+), 2 deletions(-)


Index: llvm/lib/Target/PowerPC/PPCInstrInfo.td
diff -u llvm/lib/Target/PowerPC/PPCInstrInfo.td:1.186 llvm/lib/Target/PowerPC/PPCInstrInfo.td:1.187
--- llvm/lib/Target/PowerPC/PPCInstrInfo.td:1.186	Thu Mar 16 19:40:33 2006
+++ llvm/lib/Target/PowerPC/PPCInstrInfo.td	Fri Mar 17 16:41:37 2006
@@ -334,7 +334,7 @@
                      [(set GPRC:$rD, (mul GPRC:$rA, immSExt16:$imm))]>;
 def SUBFIC : DForm_2< 8, (ops GPRC:$rD, GPRC:$rA, s16imm:$imm),
                      "subfic $rD, $rA, $imm", IntGeneral,
-                     [(set GPRC:$rD, (sub immSExt16:$imm, GPRC:$rA))]>;
+                     [(set GPRC:$rD, (subc immSExt16:$imm, GPRC:$rA))]>;
 def LI  : DForm_2_r0<14, (ops GPRC:$rD, symbolLo:$imm),
                      "li $rD, $imm", IntGeneral,
                      [(set GPRC:$rD, immSExt16:$imm)]>;
@@ -1058,7 +1058,7 @@
 def : Pat<(xor GPRC:$in, imm:$imm),
           (XORIS (XORI GPRC:$in, (LO16 imm:$imm)), (HI16 imm:$imm))>;
 // SUBFIC
-def : Pat<(subc immSExt16:$imm, GPRC:$in),
+def : Pat<(sub  immSExt16:$imm, GPRC:$in),
           (SUBFIC GPRC:$in, imm:$imm)>;
 
 // Return void support.





From lattner at cs.uiuc.edu  Fri Mar 17 18:40:49 2006
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Fri, 17 Mar 2006 18:40:49 -0600
Subject: [llvm-commits] CVS: llvm/utils/TableGen/CodeEmitterGen.cpp 
Message-ID: <200603180040.SAA05459@zion.cs.uiuc.edu>



Changes in directory llvm/utils/TableGen:

CodeEmitterGen.cpp updated: 1.43 -> 1.44
---
Log message:

Fix miscodegen of V_SET0 in PPC.


---
Diffs of the changes:  (+4 -0)

 CodeEmitterGen.cpp |    4 ++++
 1 files changed, 4 insertions(+)


Index: llvm/utils/TableGen/CodeEmitterGen.cpp
diff -u llvm/utils/TableGen/CodeEmitterGen.cpp:1.43 llvm/utils/TableGen/CodeEmitterGen.cpp:1.44
--- llvm/utils/TableGen/CodeEmitterGen.cpp:1.43	Thu Jan 26 19:39:38 2006
+++ llvm/utils/TableGen/CodeEmitterGen.cpp	Fri Mar 17 18:40:36 2006
@@ -112,6 +112,10 @@
         NewBI->setBit(middle, BI->getBit(middle));
       }
       BI = NewBI;
+      
+      // Update the bits in reversed order so that emitInstrOpBits will get the
+      // correct endianness.
+      R->getValue("Inst")->setValue(NewBI);
     }
 
     unsigned Value = 0;





From evan.cheng at apple.com  Fri Mar 17 18:45:01 2006
From: evan.cheng at apple.com (Evan Cheng)
Date: Fri, 17 Mar 2006 18:45:01 -0600
Subject: [llvm-commits] 
	CVS: llvm/lib/Transforms/Scalar/LoopStrengthReduce.cpp
Message-ID: <200603180045.SAA05488@zion.cs.uiuc.edu>



Changes in directory llvm/lib/Transforms/Scalar:

LoopStrengthReduce.cpp updated: 1.78 -> 1.79
---
Log message:

Sort StrideOrder so we can process the smallest strides first. This allows
for more IV reuses.


---
Diffs of the changes:  (+27 -0)

 LoopStrengthReduce.cpp |   27 +++++++++++++++++++++++++++
 1 files changed, 27 insertions(+)


Index: llvm/lib/Transforms/Scalar/LoopStrengthReduce.cpp
diff -u llvm/lib/Transforms/Scalar/LoopStrengthReduce.cpp:1.78 llvm/lib/Transforms/Scalar/LoopStrengthReduce.cpp:1.79
--- llvm/lib/Transforms/Scalar/LoopStrengthReduce.cpp:1.78	Fri Mar 17 13:52:23 2006
+++ llvm/lib/Transforms/Scalar/LoopStrengthReduce.cpp	Fri Mar 17 18:44:49 2006
@@ -1199,6 +1199,30 @@
   CondUse->isUseOfPostIncrementedValue = true;
 }
 
+namespace {
+  // Constant strides come first which in turns are sorted by their absolute
+  // values. If absolute values are the same, then positive strides comes first.
+  // e.g.
+  // 4, -1, X, 1, 2 ==> 1, -1, 2, 4, X
+  struct StrideCompare {
+    bool operator()(const SCEVHandle &LHS, const SCEVHandle &RHS) {
+      SCEVConstant *LHSC = dyn_cast(LHS);
+      SCEVConstant *RHSC = dyn_cast(RHS);
+      if (LHSC && RHSC) {
+        int64_t  LV = LHSC->getValue()->getSExtValue();
+        int64_t  RV = RHSC->getValue()->getSExtValue();
+        uint64_t ALV = (LV < 0) ? -LV : LV;
+        uint64_t ARV = (RV < 0) ? -RV : RV;
+        if (ALV == ARV)
+          return LV > RV;
+        else
+          return ALV < ARV;
+      } else
+        return (LHSC && !RHSC);
+    }
+  };
+}
+
 void LoopStrengthReduce::runOnLoop(Loop *L) {
   // First step, transform all loops nesting inside of this loop.
   for (LoopInfo::iterator I = L->begin(), E = L->end(); I != E; ++I)
@@ -1241,6 +1265,9 @@
   // IVsByStride keeps IVs for one particular loop.
   IVsByStride.clear();
 
+  // Sort the StrideOrder so we process larger strides first.
+  std::stable_sort(StrideOrder.begin(), StrideOrder.end(), StrideCompare());
+
   // Note: this processes each stride/type pair individually.  All users passed
   // into StrengthReduceStridedIVUsers have the same type AND stride.  Also,
   // node that we iterate over IVUsesByStride indirectly by using StrideOrder.





From evan.cheng at apple.com  Fri Mar 17 19:23:32 2006
From: evan.cheng at apple.com (Evan Cheng)
Date: Fri, 17 Mar 2006 19:23:32 -0600
Subject: [llvm-commits] CVS: llvm/lib/Target/X86/X86InstrFPStack.td
	X86InstrInfo.td X86InstrSSE.td X86RegisterInfo.cpp 
Message-ID: <200603180123.TAA05724@zion.cs.uiuc.edu>



Changes in directory llvm/lib/Target/X86:

X86InstrFPStack.td updated: 1.4 -> 1.5
X86InstrInfo.td updated: 1.255 -> 1.256
X86InstrSSE.td updated: 1.6 -> 1.7
X86RegisterInfo.cpp updated: 1.129 -> 1.130
---
Log message:

Use the generic vector register classes VR64 / VR128 rather than V4F32,
V8I16, etc.


---
Diffs of the changes:  (+247 -233)

 X86InstrFPStack.td  |   33 ++++
 X86InstrInfo.td     |   39 -----
 X86InstrSSE.td      |  396 +++++++++++++++++++++++++++-------------------------
 X86RegisterInfo.cpp |   12 -
 4 files changed, 247 insertions(+), 233 deletions(-)


Index: llvm/lib/Target/X86/X86InstrFPStack.td
diff -u llvm/lib/Target/X86/X86InstrFPStack.td:1.4 llvm/lib/Target/X86/X86InstrFPStack.td:1.5
--- llvm/lib/Target/X86/X86InstrFPStack.td:1.4	Fri Mar 17 13:55:52 2006
+++ llvm/lib/Target/X86/X86InstrFPStack.td	Fri Mar 17 19:23:20 2006
@@ -14,6 +14,39 @@
 //===----------------------------------------------------------------------===//
 
 //===----------------------------------------------------------------------===//
+// FPStack specific DAG Nodes.
+//===----------------------------------------------------------------------===//
+
+def SDTX86FpGet   : SDTypeProfile<1, 0, [SDTCisVT<0, f64>]>;
+def SDTX86FpSet   : SDTypeProfile<0, 1, [SDTCisFP<0>]>;
+def SDTX86Fld     : SDTypeProfile<1, 2, [SDTCisVT<0, f64>,
+                                         SDTCisPtrTy<1>, SDTCisVT<2, OtherVT>]>;
+def SDTX86Fst     : SDTypeProfile<0, 3, [SDTCisFP<0>,
+                                         SDTCisPtrTy<1>, SDTCisVT<2, OtherVT>]>;
+def SDTX86Fild    : SDTypeProfile<1, 2, [SDTCisVT<0, f64>, SDTCisPtrTy<1>,
+                                         SDTCisVT<2, OtherVT>]>;
+def SDTX86FpToIMem: SDTypeProfile<0, 2, [SDTCisFP<0>, SDTCisPtrTy<1>]>;
+
+def X86fpget   : SDNode<"X86ISD::FP_GET_RESULT", SDTX86FpGet,
+                        [SDNPHasChain, SDNPInFlag, SDNPOutFlag]>;
+def X86fpset   : SDNode<"X86ISD::FP_SET_RESULT", SDTX86FpSet,
+                        [SDNPHasChain, SDNPOutFlag]>;
+def X86fld     : SDNode<"X86ISD::FLD",      SDTX86Fld,
+                        [SDNPHasChain]>;
+def X86fst     : SDNode<"X86ISD::FST",      SDTX86Fst,
+                        [SDNPHasChain, SDNPInFlag]>;
+def X86fild    : SDNode<"X86ISD::FILD",     SDTX86Fild,
+                        [SDNPHasChain]>;
+def X86fildflag: SDNode<"X86ISD::FILD_FLAG",SDTX86Fild,
+                        [SDNPHasChain, SDNPOutFlag]>;
+def X86fp_to_i16mem : SDNode<"X86ISD::FP_TO_INT16_IN_MEM", SDTX86FpToIMem,
+                        [SDNPHasChain]>;
+def X86fp_to_i32mem : SDNode<"X86ISD::FP_TO_INT32_IN_MEM", SDTX86FpToIMem,
+                        [SDNPHasChain]>;
+def X86fp_to_i64mem : SDNode<"X86ISD::FP_TO_INT64_IN_MEM", SDTX86FpToIMem,
+                        [SDNPHasChain]>;
+
+//===----------------------------------------------------------------------===//
 // FPStack pattern fragments
 //===----------------------------------------------------------------------===//
 


Index: llvm/lib/Target/X86/X86InstrInfo.td
diff -u llvm/lib/Target/X86/X86InstrInfo.td:1.255 llvm/lib/Target/X86/X86InstrInfo.td:1.256
--- llvm/lib/Target/X86/X86InstrInfo.td:1.255	Fri Mar 17 13:55:52 2006
+++ llvm/lib/Target/X86/X86InstrInfo.td	Fri Mar 17 19:23:20 2006
@@ -41,17 +41,6 @@
 
 def SDT_X86Call   : SDTypeProfile<0, 1, [SDTCisVT<0, i32>]>;
 
-def SDTX86FpGet   : SDTypeProfile<1, 0, [SDTCisVT<0, f64>]>;
-def SDTX86FpSet   : SDTypeProfile<0, 1, [SDTCisFP<0>]>;
-
-def SDTX86Fld     : SDTypeProfile<1, 2, [SDTCisVT<0, f64>,
-                                         SDTCisPtrTy<1>, SDTCisVT<2, OtherVT>]>;
-def SDTX86Fst     : SDTypeProfile<0, 3, [SDTCisFP<0>,
-                                         SDTCisPtrTy<1>, SDTCisVT<2, OtherVT>]>;
-def SDTX86Fild    : SDTypeProfile<1, 2, [SDTCisVT<0, f64>, SDTCisPtrTy<1>,
-                                         SDTCisVT<2, OtherVT>]>;
-def SDTX86FpToIMem: SDTypeProfile<0, 2, [SDTCisFP<0>, SDTCisPtrTy<1>]>;
-
 def SDTX86RepStr  : SDTypeProfile<0, 1, [SDTCisVT<0, OtherVT>]>;
 
 def SDTX86RdTsc   : SDTypeProfile<0, 0, []>;
@@ -61,11 +50,6 @@
 def X86shld    : SDNode<"X86ISD::SHLD",     SDTIntShiftDOp>;
 def X86shrd    : SDNode<"X86ISD::SHRD",     SDTIntShiftDOp>;
 
-def X86fand    : SDNode<"X86ISD::FAND",     SDTFPBinOp,
-                        [SDNPCommutative, SDNPAssociative]>;
-def X86fxor    : SDNode<"X86ISD::FXOR",     SDTFPBinOp,
-                        [SDNPCommutative, SDNPAssociative]>;
-
 def X86cmp     : SDNode<"X86ISD::CMP" ,     SDTX86CmpTest,
                         [SDNPOutFlag]>;
 def X86test    : SDNode<"X86ISD::TEST",     SDTX86CmpTest,
@@ -91,26 +75,6 @@
 def X86call    : SDNode<"X86ISD::CALL",     SDT_X86Call,
                         [SDNPHasChain, SDNPOutFlag, SDNPOptInFlag]>;
 
-def X86fpget   : SDNode<"X86ISD::FP_GET_RESULT", SDTX86FpGet,
-                        [SDNPHasChain, SDNPInFlag, SDNPOutFlag]>;
-def X86fpset   : SDNode<"X86ISD::FP_SET_RESULT", SDTX86FpSet,
-                        [SDNPHasChain, SDNPOutFlag]>;
-
-def X86fld     : SDNode<"X86ISD::FLD",      SDTX86Fld,
-                        [SDNPHasChain]>;
-def X86fst     : SDNode<"X86ISD::FST",      SDTX86Fst,
-                        [SDNPHasChain, SDNPInFlag]>;
-def X86fild    : SDNode<"X86ISD::FILD",     SDTX86Fild,
-                        [SDNPHasChain]>;
-def X86fildflag: SDNode<"X86ISD::FILD_FLAG",SDTX86Fild,
-                        [SDNPHasChain, SDNPOutFlag]>;
-def X86fp_to_i16mem : SDNode<"X86ISD::FP_TO_INT16_IN_MEM", SDTX86FpToIMem,
-                        [SDNPHasChain]>;
-def X86fp_to_i32mem : SDNode<"X86ISD::FP_TO_INT32_IN_MEM", SDTX86FpToIMem,
-                        [SDNPHasChain]>;
-def X86fp_to_i64mem : SDNode<"X86ISD::FP_TO_INT64_IN_MEM", SDTX86FpToIMem,
-                        [SDNPHasChain]>;
-
 def X86rep_stos: SDNode<"X86ISD::REP_STOS", SDTX86RepStr,
                         [SDNPHasChain, SDNPInFlag, SDNPOutFlag]>;
 def X86rep_movs: SDNode<"X86ISD::REP_MOVS", SDTX86RepStr,
@@ -119,9 +83,6 @@
 def X86rdtsc   : SDNode<"X86ISD::RDTSC_DAG",SDTX86RdTsc,
                         [SDNPHasChain, SDNPOutFlag]>;
 
-def X86loadp   : SDNode<"X86ISD::LOAD_PACK", SDTLoad, 
-                        [SDNPHasChain]>;
-
 def X86Wrapper : SDNode<"X86ISD::Wrapper",  SDTX86Wrapper>;
 
 //===----------------------------------------------------------------------===//


Index: llvm/lib/Target/X86/X86InstrSSE.td
diff -u llvm/lib/Target/X86/X86InstrSSE.td:1.6 llvm/lib/Target/X86/X86InstrSSE.td:1.7
--- llvm/lib/Target/X86/X86InstrSSE.td:1.6	Fri Mar 17 13:55:52 2006
+++ llvm/lib/Target/X86/X86InstrSSE.td	Fri Mar 17 19:23:20 2006
@@ -14,14 +14,25 @@
 //===----------------------------------------------------------------------===//
 
 //===----------------------------------------------------------------------===//
+// SSE specific DAG Nodes.
+//===----------------------------------------------------------------------===//
+
+def X86loadp   : SDNode<"X86ISD::LOAD_PACK", SDTLoad, 
+                        [SDNPHasChain]>;
+def X86fand    : SDNode<"X86ISD::FAND",     SDTFPBinOp,
+                        [SDNPCommutative, SDNPAssociative]>;
+def X86fxor    : SDNode<"X86ISD::FXOR",     SDTFPBinOp,
+                        [SDNPCommutative, SDNPAssociative]>;
+
+//===----------------------------------------------------------------------===//
 // SSE pattern fragments
 //===----------------------------------------------------------------------===//
 
 def X86loadpf32  : PatFrag<(ops node:$ptr), (f32   (X86loadp node:$ptr))>;
 def X86loadpf64  : PatFrag<(ops node:$ptr), (f64   (X86loadp node:$ptr))>;
 
-def X86loadv4f32 : PatFrag<(ops node:$ptr), (v4f32 (load node:$ptr))>;
-def X86loadv2f64 : PatFrag<(ops node:$ptr), (v2f64 (load node:$ptr))>;
+def loadv4f32    : PatFrag<(ops node:$ptr), (v4f32 (load node:$ptr))>;
+def loadv2f64    : PatFrag<(ops node:$ptr), (v2f64 (load node:$ptr))>;
 
 //===----------------------------------------------------------------------===//
 // SSE scalar FP Instructions
@@ -331,329 +342,344 @@
 //===----------------------------------------------------------------------===//
 
 // Move Instructions
-def MOVAPSrr : PSI<0x28, MRMSrcReg, (ops V4F32:$dst, V4F32:$src),
+def MOVAPSrr : PSI<0x28, MRMSrcReg, (ops VR128:$dst, VR128:$src),
                    "movaps {$src, $dst|$dst, $src}", []>;
-def MOVAPSrm : PSI<0x28, MRMSrcMem, (ops V4F32:$dst, f128mem:$src),
+def MOVAPSrm : PSI<0x28, MRMSrcMem, (ops VR128:$dst, f128mem:$src),
                    "movaps {$src, $dst|$dst, $src}",
-                   [(set V4F32:$dst, (X86loadv4f32 addr:$src))]>;
-def MOVAPDrr : PDI<0x28, MRMSrcReg, (ops V2F64:$dst, V2F64:$src),
+                   [(set VR128:$dst, (loadv4f32 addr:$src))]>;
+def MOVAPDrr : PDI<0x28, MRMSrcReg, (ops VR128:$dst, VR128:$src),
                    "movapd {$src, $dst|$dst, $src}", []>;
-def MOVAPDrm : PDI<0x28, MRMSrcMem, (ops V2F64:$dst, f128mem:$src),
+def MOVAPDrm : PDI<0x28, MRMSrcMem, (ops VR128:$dst, f128mem:$src),
                    "movapd {$src, $dst|$dst, $src}",
-                   [(set V2F64:$dst, (X86loadv2f64 addr:$src))]>;
+                   [(set VR128:$dst, (loadv2f64 addr:$src))]>;
 
-def MOVAPSmr : PSI<0x29, MRMDestMem, (ops f128mem:$dst, V4F32:$src),
+def MOVAPSmr : PSI<0x29, MRMDestMem, (ops f128mem:$dst, VR128:$src),
                    "movaps {$src, $dst|$dst, $src}",
-                   [(store V4F32:$src, addr:$dst)]>;
-def MOVAPDmr : PDI<0x29, MRMDestMem, (ops f128mem:$dst, V2F64:$src),
+                   [(store (v4f32 VR128:$src), addr:$dst)]>;
+def MOVAPDmr : PDI<0x29, MRMDestMem, (ops f128mem:$dst, VR128:$src),
                    "movapd {$src, $dst|$dst, $src}",
-                   [(store V2F64:$src, addr:$dst)]>;
+                   [(store (v2f64 VR128:$src), addr:$dst)]>;
 
-def MOVUPSrr : PSI<0x10, MRMSrcReg, (ops V4F32:$dst, V4F32:$src),
+def MOVUPSrr : PSI<0x10, MRMSrcReg, (ops VR128:$dst, VR128:$src),
                    "movups {$src, $dst|$dst, $src}", []>;
-def MOVUPSrm : PSI<0x10, MRMSrcMem, (ops V4F32:$dst, f128mem:$src),
+def MOVUPSrm : PSI<0x10, MRMSrcMem, (ops VR128:$dst, f128mem:$src),
                    "movups {$src, $dst|$dst, $src}", []>;
-def MOVUPSmr : PSI<0x11, MRMDestMem, (ops f128mem:$dst, V4F32:$src),
+def MOVUPSmr : PSI<0x11, MRMDestMem, (ops f128mem:$dst, VR128:$src),
                    "movups {$src, $dst|$dst, $src}", []>;
-def MOVUPDrr : PDI<0x10, MRMSrcReg, (ops V2F64:$dst, V2F64:$src),
+def MOVUPDrr : PDI<0x10, MRMSrcReg, (ops VR128:$dst, VR128:$src),
                    "movupd {$src, $dst|$dst, $src}", []>;
-def MOVUPDrm : PDI<0x10, MRMSrcMem, (ops V2F64:$dst, f128mem:$src),
+def MOVUPDrm : PDI<0x10, MRMSrcMem, (ops VR128:$dst, f128mem:$src),
                    "movupd {$src, $dst|$dst, $src}", []>;
-def MOVUPDmr : PDI<0x11, MRMDestMem, (ops f128mem:$dst, V2F64:$src),
+def MOVUPDmr : PDI<0x11, MRMDestMem, (ops f128mem:$dst, VR128:$src),
                    "movupd {$src, $dst|$dst, $src}", []>;
 
-def MOVLPSrm : PSI<0x12, MRMSrcMem, (ops V4F32:$dst, f64mem:$src),
+def MOVLPSrm : PSI<0x12, MRMSrcMem, (ops VR128:$dst, f64mem:$src),
                    "movlps {$src, $dst|$dst, $src}", []>;
-def MOVLPSmr : PSI<0x13, MRMDestMem, (ops f64mem:$dst, V4F32:$src),
+def MOVLPSmr : PSI<0x13, MRMDestMem, (ops f64mem:$dst, VR128:$src),
                    "movlps {$src, $dst|$dst, $src}", []>;
-def MOVLPDrm : PDI<0x12, MRMSrcMem, (ops V2F64:$dst, f64mem:$src),
+def MOVLPDrm : PDI<0x12, MRMSrcMem, (ops VR128:$dst, f64mem:$src),
                    "movlpd {$src, $dst|$dst, $src}", []>;
-def MOVLPDmr : PDI<0x13, MRMDestMem, (ops f64mem:$dst, V2F64:$src),
+def MOVLPDmr : PDI<0x13, MRMDestMem, (ops f64mem:$dst, VR128:$src),
                    "movlpd {$src, $dst|$dst, $src}", []>;
 
-def MOVHPSrm : PSI<0x16, MRMSrcMem, (ops V4F32:$dst, f64mem:$src),
+def MOVHPSrm : PSI<0x16, MRMSrcMem, (ops VR128:$dst, f64mem:$src),
                    "movhps {$src, $dst|$dst, $src}", []>;
-def MOVHPSmr : PSI<0x17, MRMDestMem, (ops f64mem:$dst, V4F32:$src),
+def MOVHPSmr : PSI<0x17, MRMDestMem, (ops f64mem:$dst, VR128:$src),
                    "movhps {$src, $dst|$dst, $src}", []>;
-def MOVHPDrm : PDI<0x16, MRMSrcMem, (ops V2F64:$dst, f64mem:$src),
+def MOVHPDrm : PDI<0x16, MRMSrcMem, (ops VR128:$dst, f64mem:$src),
                    "movhpd {$src, $dst|$dst, $src}", []>;
-def MOVHPDmr : PDI<0x17, MRMDestMem, (ops f64mem:$dst, V2F64:$src),
+def MOVHPDmr : PDI<0x17, MRMDestMem, (ops f64mem:$dst, VR128:$src),
                    "movhpd {$src, $dst|$dst, $src}", []>;
 
-def MOVLHPSrr : PSI<0x16, MRMSrcReg, (ops V4F32:$dst, V4F32:$src),
+def MOVLHPSrr : PSI<0x16, MRMSrcReg, (ops VR128:$dst, VR128:$src),
                     "movlhps {$src, $dst|$dst, $src}", []>;
-def MOVHLPSrr : PSI<0x12, MRMSrcReg, (ops V4F32:$dst, V4F32:$src),
+def MOVHLPSrr : PSI<0x12, MRMSrcReg, (ops VR128:$dst, VR128:$src),
                     "movlhps {$src, $dst|$dst, $src}", []>;
 
-def MOVMSKPSrr : PSI<0x50, MRMSrcReg, (ops R32:$dst, V4F32:$src),
+def MOVMSKPSrr : PSI<0x50, MRMSrcReg, (ops R32:$dst, VR128:$src),
                      "movmskps {$src, $dst|$dst, $src}", []>;
-def MOVMSKPDrr : PSI<0x50, MRMSrcReg, (ops R32:$dst, V2F64:$src),
+def MOVMSKPDrr : PSI<0x50, MRMSrcReg, (ops R32:$dst, VR128:$src),
                      "movmskpd {$src, $dst|$dst, $src}", []>;
 
 // Conversion instructions
-def CVTPI2PSrr : PSI<0x2A, MRMSrcReg, (ops V4F32:$dst, V2I32:$src),
+def CVTPI2PSrr : PSI<0x2A, MRMSrcReg, (ops VR128:$dst, VR64:$src),
                      "cvtpi2ps {$src, $dst|$dst, $src}", []>;
-def CVTPI2PSrm : PSI<0x2A, MRMSrcMem, (ops V4F32:$dst, i64mem:$src),
+def CVTPI2PSrm : PSI<0x2A, MRMSrcMem, (ops VR128:$dst, i64mem:$src),
                      "cvtpi2ps {$src, $dst|$dst, $src}", []>;
-def CVTPI2PDrr : PDI<0x2A, MRMSrcReg, (ops V2F64:$dst, V2I32:$src),
+def CVTPI2PDrr : PDI<0x2A, MRMSrcReg, (ops VR128:$dst, VR64:$src),
                      "cvtpi2pd {$src, $dst|$dst, $src}", []>;
-def CVTPI2PDrm : PDI<0x2A, MRMSrcMem, (ops V2F64:$dst, i64mem:$src),
+def CVTPI2PDrm : PDI<0x2A, MRMSrcMem, (ops VR128:$dst, i64mem:$src),
                      "cvtpi2pd {$src, $dst|$dst, $src}", []>;
 
 // SSE2 instructions without OpSize prefix
-def CVTDQ2PSrr : I<0x5B, MRMSrcReg, (ops V4F32:$dst, V4I32:$src),
+def CVTDQ2PSrr : I<0x5B, MRMSrcReg, (ops VR128:$dst, VR128:$src),
                    "cvtdq2ps {$src, $dst|$dst, $src}", []>, TB,
                  Requires<[HasSSE2]>;
-def CVTDQ2PSrm : I<0x5B, MRMSrcMem, (ops V4F32:$dst, i128mem:$src),
+def CVTDQ2PSrm : I<0x5B, MRMSrcMem, (ops VR128:$dst, i128mem:$src),
                    "cvtdq2ps {$src, $dst|$dst, $src}", []>, TB,
                  Requires<[HasSSE2]>;
 
 // SSE2 instructions with XS prefix
-def CVTDQ2PDrr : I<0xE6, MRMSrcReg, (ops V2F64:$dst, V2I32:$src),
+def CVTDQ2PDrr : I<0xE6, MRMSrcReg, (ops VR128:$dst, VR64:$src),
                    "cvtdq2pd {$src, $dst|$dst, $src}", []>,
                  XS, Requires<[HasSSE2]>;
-def CVTDQ2PDrm : I<0xE6, MRMSrcMem, (ops V4F32:$dst, i64mem:$src),
+def CVTDQ2PDrm : I<0xE6, MRMSrcMem, (ops VR128:$dst, i64mem:$src),
                    "cvtdq2pd {$src, $dst|$dst, $src}", []>,
                  XS, Requires<[HasSSE2]>;
 
-def CVTPS2PIrr : PSI<0x2D, MRMSrcReg, (ops V2I32:$dst, V4F32:$src),
+def CVTPS2PIrr : PSI<0x2D, MRMSrcReg, (ops VR64:$dst, VR128:$src),
                     "cvtps2pi {$src, $dst|$dst, $src}", []>;
-def CVTPS2PIrm : PSI<0x2D, MRMSrcMem, (ops V2I32:$dst, f64mem:$src),
+def CVTPS2PIrm : PSI<0x2D, MRMSrcMem, (ops VR64:$dst, f64mem:$src),
                     "cvtps2pi {$src, $dst|$dst, $src}", []>;
-def CVTPD2PIrr : PDI<0x2D, MRMSrcReg, (ops V2I32:$dst, V2F64:$src),
+def CVTPD2PIrr : PDI<0x2D, MRMSrcReg, (ops VR64:$dst, VR128:$src),
                     "cvtpd2pi {$src, $dst|$dst, $src}", []>;
-def CVTPD2PIrm : PDI<0x2D, MRMSrcMem, (ops V2I32:$dst, f128mem:$src),
+def CVTPD2PIrm : PDI<0x2D, MRMSrcMem, (ops VR64:$dst, f128mem:$src),
                     "cvtpd2pi {$src, $dst|$dst, $src}", []>;
 
-def CVTPS2DQrr : PDI<0x5B, MRMSrcReg, (ops V4I32:$dst, V4F32:$src),
+def CVTPS2DQrr : PDI<0x5B, MRMSrcReg, (ops VR128:$dst, VR128:$src),
                      "cvtps2dq {$src, $dst|$dst, $src}", []>;
-def CVTPS2DQrm : PDI<0x5B, MRMSrcMem, (ops V4I32:$dst, f128mem:$src),
+def CVTPS2DQrm : PDI<0x5B, MRMSrcMem, (ops VR128:$dst, f128mem:$src),
                      "cvtps2dq {$src, $dst|$dst, $src}", []>;
 // SSE2 packed instructions with XD prefix
-def CVTPD2DQrr : SDI<0xE6, MRMSrcReg, (ops V4I32:$dst, V2F64:$src),
+def CVTPD2DQrr : SDI<0xE6, MRMSrcReg, (ops VR128:$dst, VR128:$src),
                      "cvtpd2dq {$src, $dst|$dst, $src}", []>;
-def CVTPD2DQrm : SDI<0xE6, MRMSrcMem, (ops V4I32:$dst, f128mem:$src),
+def CVTPD2DQrm : SDI<0xE6, MRMSrcMem, (ops VR128:$dst, f128mem:$src),
                      "cvtpd2dq {$src, $dst|$dst, $src}", []>;
 
 // SSE2 instructions without OpSize prefix
-def CVTPS2PDrr : I<0x5A, MRMSrcReg, (ops V4I32:$dst, V2F64:$src),
+def CVTPS2PDrr : I<0x5A, MRMSrcReg, (ops VR128:$dst, VR128:$src),
                    "cvtps2pd {$src, $dst|$dst, $src}", []>, TB,
                  Requires<[HasSSE2]>;
-def CVTPS2PDrm : I<0x5A, MRMSrcReg, (ops V4I32:$dst, f64mem:$src),
+def CVTPS2PDrm : I<0x5A, MRMSrcReg, (ops VR128:$dst, f64mem:$src),
                    "cvtps2pd {$src, $dst|$dst, $src}", []>, TB,
                  Requires<[HasSSE2]>;
 
-def CVTPD2PSrr : PDI<0x5A, MRMSrcReg, (ops V4F32:$dst, V2F64:$src),
+def CVTPD2PSrr : PDI<0x5A, MRMSrcReg, (ops VR128:$dst, VR128:$src),
                      "cvtpd2ps {$src, $dst|$dst, $src}", []>;
-def CVTPD2PSrm : PDI<0x5A, MRMSrcReg, (ops V4F32:$dst, f128mem:$src),
+def CVTPD2PSrm : PDI<0x5A, MRMSrcReg, (ops VR128:$dst, f128mem:$src),
                      "cvtpd2ps {$src, $dst|$dst, $src}", []>;
 
 // Arithmetic
 let isTwoAddress = 1 in {
 let isCommutable = 1 in {
-def ADDPSrr : PSI<0x58, MRMSrcReg, (ops V4F32:$dst, V4F32:$src1, V4F32:$src2),
+def ADDPSrr : PSI<0x58, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
                   "addps {$src2, $dst|$dst, $src2}",
-                  [(set V4F32:$dst, (fadd V4F32:$src1, V4F32:$src2))]>;
-def ADDPDrr : PDI<0x58, MRMSrcReg, (ops V2F64:$dst, V2F64:$src1, V2F64:$src2),
+                  [(set VR128:$dst, (v4f32 (fadd VR128:$src1, VR128:$src2)))]>;
+def ADDPDrr : PDI<0x58, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
                   "addpd {$src2, $dst|$dst, $src2}",
-                  [(set V2F64:$dst, (fadd V2F64:$src1, V2F64:$src2))]>;
-def MULPSrr : PSI<0x59, MRMSrcReg, (ops V4F32:$dst, V4F32:$src1, V4F32:$src2),
+                  [(set VR128:$dst, (v2f64 (fadd VR128:$src1, VR128:$src2)))]>;
+def MULPSrr : PSI<0x59, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
                   "mulps {$src2, $dst|$dst, $src2}",
-                  [(set V4F32:$dst, (fmul V4F32:$src1, V4F32:$src2))]>;
-def MULPDrr : PDI<0x59, MRMSrcReg, (ops V2F64:$dst, V2F64:$src1, V2F64:$src2),
+                  [(set VR128:$dst, (v4f32 (fmul VR128:$src1, VR128:$src2)))]>;
+def MULPDrr : PDI<0x59, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
                   "mulpd {$src2, $dst|$dst, $src2}",
-                  [(set V2F64:$dst, (fmul V2F64:$src1, V2F64:$src2))]>;
+                  [(set VR128:$dst, (v2f64 (fmul VR128:$src1, VR128:$src2)))]>;
 }
 
-def ADDPSrm : PSI<0x58, MRMSrcMem, (ops V4F32:$dst, V4F32:$src1, f128mem:$src2),
+def ADDPSrm : PSI<0x58, MRMSrcMem, (ops VR128:$dst, VR128:$src1, f128mem:$src2),
                   "addps {$src2, $dst|$dst, $src2}",
-                  [(set V4F32:$dst, (fadd V4F32:$src1,
-                                    (X86loadv4f32 addr:$src2)))]>;
-def ADDPDrm : PDI<0x58, MRMSrcMem, (ops V2F64:$dst, V2F64:$src1, f128mem:$src2),
+                  [(set VR128:$dst, (v4f32 (fadd VR128:$src1,
+                                            (load addr:$src2))))]>;
+def ADDPDrm : PDI<0x58, MRMSrcMem, (ops VR128:$dst, VR128:$src1, f128mem:$src2),
                   "addpd {$src2, $dst|$dst, $src2}",
-                  [(set V2F64:$dst, (fadd V2F64:$src1,
-                                    (X86loadv2f64 addr:$src2)))]>;
-def MULPSrm : PSI<0x59, MRMSrcMem, (ops V4F32:$dst, V4F32:$src1, f128mem:$src2),
+                  [(set VR128:$dst, (v2f64 (fadd VR128:$src1,
+                                            (load addr:$src2))))]>;
+def MULPSrm : PSI<0x59, MRMSrcMem, (ops VR128:$dst, VR128:$src1, f128mem:$src2),
                   "mulps {$src2, $dst|$dst, $src2}",
-                  [(set V4F32:$dst, (fmul V4F32:$src1,
-                                    (X86loadv4f32 addr:$src2)))]>;
-def MULPDrm : PDI<0x59, MRMSrcMem, (ops V2F64:$dst, V2F64:$src1, f128mem:$src2),
+                  [(set VR128:$dst, (v4f32 (fmul VR128:$src1,
+                                            (load addr:$src2))))]>;
+def MULPDrm : PDI<0x59, MRMSrcMem, (ops VR128:$dst, VR128:$src1, f128mem:$src2),
                   "mulpd {$src2, $dst|$dst, $src2}",
-                  [(set V2F64:$dst, (fmul V2F64:$src1,
-                                    (X86loadv2f64 addr:$src2)))]>;
+                  [(set VR128:$dst, (v2f64 (fmul VR128:$src1,
+                                            (load addr:$src2))))]>;
 
-def DIVPSrr : PSI<0x5E, MRMSrcReg, (ops V4F32:$dst, V4F32:$src1, V4F32:$src2),
-                "divps {$src2, $dst|$dst, $src2}",
-                [(set V4F32:$dst, (fdiv V4F32:$src1, V4F32:$src2))]>;
-def DIVPSrm : PSI<0x5E, MRMSrcMem, (ops V4F32:$dst, V4F32:$src1, f128mem:$src2),
-                "divps {$src2, $dst|$dst, $src2}",
-                [(set V4F32:$dst, (fdiv V4F32:$src1,
-                                  (X86loadv4f32 addr:$src2)))]>;
-def DIVPDrr : PDI<0x5E, MRMSrcReg, (ops V2F64:$dst, V2F64:$src1, V2F64:$src2),
+def DIVPSrr : PSI<0x5E, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
+                  "divps {$src2, $dst|$dst, $src2}",
+                  [(set VR128:$dst, (v4f32 (fdiv VR128:$src1, VR128:$src2)))]>;
+def DIVPSrm : PSI<0x5E, MRMSrcMem, (ops VR128:$dst, VR128:$src1, f128mem:$src2),
+                  "divps {$src2, $dst|$dst, $src2}",
+                  [(set VR128:$dst, (v4f32 (fdiv VR128:$src1,
+                                            (load addr:$src2))))]>;
+def DIVPDrr : PDI<0x5E, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
                 "divpd {$src2, $dst|$dst, $src2}",
-                [(set V2F64:$dst, (fdiv V2F64:$src1, V2F64:$src2))]>;
-def DIVPDrm : PDI<0x5E, MRMSrcMem, (ops V2F64:$dst, V2F64:$src1, f128mem:$src2),
+                  [(set VR128:$dst, (v2f64 (fdiv VR128:$src1, VR128:$src2)))]>;
+def DIVPDrm : PDI<0x5E, MRMSrcMem, (ops VR128:$dst, VR128:$src1, f128mem:$src2),
                 "divpd {$src2, $dst|$dst, $src2}",
-                [(set V2F64:$dst, (fdiv V2F64:$src1,
-                                  (X86loadv2f64 addr:$src2)))]>;
+                  [(set VR128:$dst, (v2f64 (fdiv VR128:$src1,
+                                            (load addr:$src2))))]>;
 
-def SUBPSrr : PSI<0x5C, MRMSrcReg, (ops V4F32:$dst, V4F32:$src1, V4F32:$src2),
-                "subps {$src2, $dst|$dst, $src2}",
-                [(set V4F32:$dst, (fsub V4F32:$src1, V4F32:$src2))]>;
-def SUBPSrm : PSI<0x5C, MRMSrcMem, (ops V4F32:$dst, V4F32:$src1, f128mem:$src2),
-                "subps {$src2, $dst|$dst, $src2}",
-                [(set V4F32:$dst, (fsub V4F32:$src1,
-                                  (X86loadv4f32 addr:$src2)))]>;
-def SUBPDrr : PDI<0x5C, MRMSrcReg, (ops V2F64:$dst, V2F64:$src1, V2F64:$src2),
-                "subpd {$src2, $dst|$dst, $src2}",
-                [(set V2F64:$dst, (fsub V2F64:$src1, V2F64:$src2))]>;
-def SUBPDrm : PDI<0x5C, MRMSrcMem, (ops V2F64:$dst, V2F64:$src1, f128mem:$src2),
-                "subpd {$src2, $dst|$dst, $src2}",
-                [(set V2F64:$dst, (fsub V2F64:$src1,
-                                  (X86loadv2f64 addr:$src2)))]>;
-}
-
-def SQRTPSrr : PSI<0x51, MRMSrcReg, (ops V4F32:$dst, V4F32:$src),
-                 "sqrtps {$src, $dst|$dst, $src}",
-                 [(set V4F32:$dst, (fsqrt V4F32:$src))]>;
-def SQRTPSrm : PSI<0x51, MRMSrcMem, (ops V4F32:$dst, f128mem:$src),
-                 "sqrtps {$src, $dst|$dst, $src}",
-                 [(set V4F32:$dst, (fsqrt (X86loadv4f32 addr:$src)))]>;
-def SQRTPDrr : PDI<0x51, MRMSrcReg, (ops V2F64:$dst, V2F64:$src),
-                 "sqrtpd {$src, $dst|$dst, $src}",
-                 [(set V2F64:$dst, (fsqrt V2F64:$src))]>;
-def SQRTPDrm : PDI<0x51, MRMSrcMem, (ops V2F64:$dst, f128mem:$src),
-                 "sqrtpd {$src, $dst|$dst, $src}",
-                 [(set V2F64:$dst, (fsqrt (X86loadv2f64 addr:$src)))]>;
-
-def RSQRTPSrr : PSI<0x52, MRMSrcReg, (ops V4F32:$dst, V4F32:$src),
-                 "rsqrtps {$src, $dst|$dst, $src}", []>;
-def RSQRTPSrm : PSI<0x52, MRMSrcMem, (ops V4F32:$dst, f128mem:$src),
-                 "rsqrtps {$src, $dst|$dst, $src}", []>;
-def RCPPSrr : PSI<0x53, MRMSrcReg, (ops V4F32:$dst, V4F32:$src),
+def SUBPSrr : PSI<0x5C, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
+                  "subps {$src2, $dst|$dst, $src2}",
+                  [(set VR128:$dst, (v4f32 (fsub VR128:$src1, VR128:$src2)))]>;
+def SUBPSrm : PSI<0x5C, MRMSrcMem, (ops VR128:$dst, VR128:$src1, f128mem:$src2),
+                  "subps {$src2, $dst|$dst, $src2}",
+                  [(set VR128:$dst, (v4f32 (fsub VR128:$src1,
+                                            (load addr:$src2))))]>;
+def SUBPDrr : PDI<0x5C, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
+                  "subpd {$src2, $dst|$dst, $src2}",
+                  [(set VR128:$dst, (fsub VR128:$src1, VR128:$src2))]>;
+def SUBPDrm : PDI<0x5C, MRMSrcMem, (ops VR128:$dst, VR128:$src1, f128mem:$src2),
+                  "subpd {$src2, $dst|$dst, $src2}",
+                  [(set VR128:$dst, (fsub VR128:$src1,
+                                     (load addr:$src2)))]>;
+}
+
+def SQRTPSrr : PSI<0x51, MRMSrcReg, (ops VR128:$dst, VR128:$src),
+                   "sqrtps {$src, $dst|$dst, $src}",
+                   [(set VR128:$dst, (v4f32 (fsqrt VR128:$src)))]>;
+def SQRTPSrm : PSI<0x51, MRMSrcMem, (ops VR128:$dst, f128mem:$src),
+                   "sqrtps {$src, $dst|$dst, $src}",
+                   [(set VR128:$dst, (v4f32 (fsqrt (load addr:$src))))]>;
+def SQRTPDrr : PDI<0x51, MRMSrcReg, (ops VR128:$dst, VR128:$src),
+                   "sqrtpd {$src, $dst|$dst, $src}",
+                   [(set VR128:$dst, (v2f64 (fsqrt VR128:$src)))]>;
+def SQRTPDrm : PDI<0x51, MRMSrcMem, (ops VR128:$dst, f128mem:$src),
+                   "sqrtpd {$src, $dst|$dst, $src}",
+                   [(set VR128:$dst, (v2f64 (fsqrt (load addr:$src))))]>;
+
+def RSQRTPSrr : PSI<0x52, MRMSrcReg, (ops VR128:$dst, VR128:$src),
+                    "rsqrtps {$src, $dst|$dst, $src}", []>;
+def RSQRTPSrm : PSI<0x52, MRMSrcMem, (ops VR128:$dst, f128mem:$src),
+                    "rsqrtps {$src, $dst|$dst, $src}", []>;
+def RCPPSrr : PSI<0x53, MRMSrcReg, (ops VR128:$dst, VR128:$src),
                   "rcpps {$src, $dst|$dst, $src}", []>;
-def RCPPSrm : PSI<0x53, MRMSrcMem, (ops V4F32:$dst, f128mem:$src),
+def RCPPSrm : PSI<0x53, MRMSrcMem, (ops VR128:$dst, f128mem:$src),
                   "rcpps {$src, $dst|$dst, $src}", []>;
 
-def MAXPSrr : PSI<0x5F, MRMSrcReg, (ops V4F32:$dst, V4F32:$src),
+def MAXPSrr : PSI<0x5F, MRMSrcReg, (ops VR128:$dst, VR128:$src),
                   "maxps {$src, $dst|$dst, $src}", []>;
-def MAXPSrm : PSI<0x5F, MRMSrcMem, (ops V4F32:$dst, f128mem:$src),
+def MAXPSrm : PSI<0x5F, MRMSrcMem, (ops VR128:$dst, f128mem:$src),
                   "maxps {$src, $dst|$dst, $src}", []>;
-def MAXPDrr : PDI<0x5F, MRMSrcReg, (ops V2F64:$dst, V2F64:$src),
+def MAXPDrr : PDI<0x5F, MRMSrcReg, (ops VR128:$dst, VR128:$src),
                   "maxpd {$src, $dst|$dst, $src}", []>;
-def MAXPDrm : PDI<0x5F, MRMSrcMem, (ops V2F64:$dst, f128mem:$src),
+def MAXPDrm : PDI<0x5F, MRMSrcMem, (ops VR128:$dst, f128mem:$src),
                   "maxpd {$src, $dst|$dst, $src}", []>;
-def MINPSrr : PSI<0x5D, MRMSrcReg, (ops V4F32:$dst, V4F32:$src),
+def MINPSrr : PSI<0x5D, MRMSrcReg, (ops VR128:$dst, VR128:$src),
                   "minps {$src, $dst|$dst, $src}", []>;
-def MINPSrm : PSI<0x5D, MRMSrcMem, (ops V4F32:$dst, f128mem:$src),
+def MINPSrm : PSI<0x5D, MRMSrcMem, (ops VR128:$dst, f128mem:$src),
                   "minps {$src, $dst|$dst, $src}", []>;
-def MINPDrr : PDI<0x5D, MRMSrcReg, (ops V2F64:$dst, V2F64:$src),
+def MINPDrr : PDI<0x5D, MRMSrcReg, (ops VR128:$dst, VR128:$src),
                   "minpd {$src, $dst|$dst, $src}", []>;
-def MINPDrm : PDI<0x5D, MRMSrcMem, (ops V2F64:$dst, f128mem:$src),
+def MINPDrm : PDI<0x5D, MRMSrcMem, (ops VR128:$dst, f128mem:$src),
                   "minpd {$src, $dst|$dst, $src}", []>;
 
 // Logical
 let isTwoAddress = 1 in {
 let isCommutable = 1 in {
-def ANDPSrr : PSI<0x54, MRMSrcReg, (ops V4F32:$dst, V4F32:$src1, V4F32:$src2),
-                "andps {$src2, $dst|$dst, $src2}",
-                [(set V4F32:$dst, (X86fand V4F32:$src1, V4F32:$src2))]>;
-def ANDPDrr : PDI<0x54, MRMSrcReg, (ops V2F64:$dst, V2F64:$src1, V2F64:$src2),
-                "andpd {$src2, $dst|$dst, $src2}",
-                [(set V2F64:$dst, (X86fand V2F64:$src1, V2F64:$src2))]>;
-def ORPSrr  : PSI<0x56, MRMSrcReg, (ops V4F32:$dst, V4F32:$src1, V4F32:$src2),
-                "orps {$src2, $dst|$dst, $src2}", []>;
-def ORPDrr  : PDI<0x56, MRMSrcReg, (ops V2F64:$dst, V2F64:$src1, V2F64:$src2),
-                "orpd {$src2, $dst|$dst, $src2}", []>;
-def XORPSrr : PSI<0x57, MRMSrcReg, (ops V4F32:$dst, V4F32:$src1, V4F32:$src2),
-                "xorps {$src2, $dst|$dst, $src2}",
-                [(set V4F32:$dst, (X86fxor V4F32:$src1, V4F32:$src2))]>;
-def XORPDrr : PDI<0x57, MRMSrcReg, (ops V2F64:$dst, V2F64:$src1, V2F64:$src2),
-                "xorpd {$src2, $dst|$dst, $src2}",
-                [(set V2F64:$dst, (X86fxor V2F64:$src1, V2F64:$src2))]>;
-}
-def ANDPSrm : PSI<0x54, MRMSrcMem, (ops V4F32:$dst, V4F32:$src1, f128mem:$src2),
-                "andps {$src2, $dst|$dst, $src2}",
-                [(set V4F32:$dst, (X86fand V4F32:$src1,
-                                  (X86loadv4f32 addr:$src2)))]>;
-def ANDPDrm : PDI<0x54, MRMSrcMem, (ops V2F64:$dst, V2F64:$src1, f128mem:$src2),
+def ANDPSrr : PSI<0x54, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
+                  "andps {$src2, $dst|$dst, $src2}",
+                  [(set VR128:$dst, (v4i32 (and VR128:$src1, VR128:$src2)))]>;
+def ANDPDrr : PDI<0x54, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
                 "andpd {$src2, $dst|$dst, $src2}",
-                [(set V2F64:$dst, (X86fand V2F64:$src1,
-                                  (X86loadv2f64 addr:$src2)))]>;
-def ORPSrm  : PSI<0x56, MRMSrcMem, (ops V4F32:$dst, V4F32:$src1, f128mem:$src2),
-                "orps {$src2, $dst|$dst, $src2}", []>;
-def ORPDrm  : PDI<0x56, MRMSrcMem, (ops V2F64:$dst, V2F64:$src1, f128mem:$src2),
-                "orpd {$src2, $dst|$dst, $src2}", []>;
-def XORPSrm : PSI<0x57, MRMSrcMem, (ops V4F32:$dst, V4F32:$src1, f128mem:$src2),
-                "xorps {$src2, $dst|$dst, $src2}",
-                [(set V4F32:$dst, (X86fxor V4F32:$src1,
-                                  (X86loadv4f32 addr:$src2)))]>;
-def XORPDrm : PDI<0x57, MRMSrcMem, (ops V2F64:$dst, V2F64:$src1, f128mem:$src2),
-                "xorpd {$src2, $dst|$dst, $src2}",
-                [(set V2F64:$dst, (X86fxor V2F64:$src1,
-                                  (X86loadv2f64 addr:$src2)))]>;
-def ANDNPSrr : PSI<0x55, MRMSrcReg, (ops V4F32:$dst, V4F32:$src1, V4F32:$src2),
-                "andnps {$src2, $dst|$dst, $src2}", []>;
-def ANDNPSrm : PSI<0x55, MRMSrcMem, (ops V4F32:$dst, V4F32:$src1, f128mem:$src2),
-                "andnps {$src2, $dst|$dst, $src2}", []>;
-def ANDNPDrr : PDI<0x55, MRMSrcReg, (ops V2F64:$dst, V2F64:$src1, V2F64:$src2),
-                "andnpd {$src2, $dst|$dst, $src2}", []>;
-def ANDNPDrm : PDI<0x55, MRMSrcMem, (ops V2F64:$dst, V2F64:$src1, f128mem:$src2),
-                "andnpd {$src2, $dst|$dst, $src2}", []>;
+                  [(set VR128:$dst, (v2i64 (and VR128:$src1, VR128:$src2)))]>;
+def ORPSrr  : PSI<0x56, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
+                  "orps {$src2, $dst|$dst, $src2}",
+                  [(set VR128:$dst, (v4i32 (or VR128:$src1, VR128:$src2)))]>;
+def ORPDrr  : PDI<0x56, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
+                  "orpd {$src2, $dst|$dst, $src2}",
+                  [(set VR128:$dst, (v2i64 (or VR128:$src1, VR128:$src2)))]>;
+def XORPSrr : PSI<0x57, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
+                  "xorps {$src2, $dst|$dst, $src2}",
+                  [(set VR128:$dst, (v4i32 (xor VR128:$src1, VR128:$src2)))]>;
+def XORPDrr : PDI<0x57, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
+                  "xorpd {$src2, $dst|$dst, $src2}",
+                  [(set VR128:$dst, (v2i64 (xor VR128:$src1, VR128:$src2)))]>;
+}
+def ANDPSrm : PSI<0x54, MRMSrcMem, (ops VR128:$dst, VR128:$src1, f128mem:$src2),
+                  "andps {$src2, $dst|$dst, $src2}",
+                  [(set VR128:$dst, (v4i32 (and VR128:$src1,
+                                            (load addr:$src2))))]>;
+def ANDPDrm : PDI<0x54, MRMSrcMem, (ops VR128:$dst, VR128:$src1, f128mem:$src2),
+                  "andpd {$src2, $dst|$dst, $src2}",
+                  [(set VR128:$dst, (v2i64 (and VR128:$src1,
+                                            (load addr:$src2))))]>;
+def ORPSrm  : PSI<0x56, MRMSrcMem, (ops VR128:$dst, VR128:$src1, f128mem:$src2),
+                  "orps {$src2, $dst|$dst, $src2}",
+                  [(set VR128:$dst, (v4i32 (or VR128:$src1,
+                                            (load addr:$src2))))]>;
+def ORPDrm  : PDI<0x56, MRMSrcMem, (ops VR128:$dst, VR128:$src1, f128mem:$src2),
+                "orpd {$src2, $dst|$dst, $src2}",
+                  [(set VR128:$dst, (v2i64 (or VR128:$src1,
+                                            (load addr:$src2))))]>;
+def XORPSrm : PSI<0x57, MRMSrcMem, (ops VR128:$dst, VR128:$src1, f128mem:$src2),
+                  "xorps {$src2, $dst|$dst, $src2}",
+                  [(set VR128:$dst, (v4i32 (xor VR128:$src1,
+                                            (load addr:$src2))))]>;
+def XORPDrm : PDI<0x57, MRMSrcMem, (ops VR128:$dst, VR128:$src1, f128mem:$src2),
+                  "xorpd {$src2, $dst|$dst, $src2}",
+                  [(set VR128:$dst, (v2i64 (xor VR128:$src1,
+                                            (load addr:$src2))))]>;
+def ANDNPSrr : PSI<0x55, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
+                  "andnps {$src2, $dst|$dst, $src2}",
+                  [(set VR128:$dst, (v4i32 (and (not VR128:$src1),
+                                            VR128:$src2)))]>;
+def ANDNPSrm : PSI<0x55, MRMSrcMem, (ops VR128:$dst, VR128:$src1, f128mem:$src2),
+                  "andnps {$src2, $dst|$dst, $src2}",
+                  [(set VR128:$dst, (v4i32 (and (not VR128:$src1),
+                                            (load addr:$src2))))]>;
+def ANDNPDrr : PDI<0x55, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
+                  "andnpd {$src2, $dst|$dst, $src2}",
+                  [(set VR128:$dst, (v2i64 (and (not VR128:$src1),
+                                            VR128:$src2)))]>;
+
+def ANDNPDrm : PDI<0x55, MRMSrcMem, (ops VR128:$dst, VR128:$src1, f128mem:$src2),
+                  "andnpd {$src2, $dst|$dst, $src2}",
+                  [(set VR128:$dst, (v2i64 (and VR128:$src1,
+                                            (load addr:$src2))))]>;
 }
 
 let isTwoAddress = 1 in {
 def CMPPSrr : PSI<0xC2, MRMSrcReg, 
-                (ops V4F32:$dst, V4F32:$src1, V4F32:$src, SSECC:$cc),
+                (ops VR128:$dst, VR128:$src1, VR128:$src, SSECC:$cc),
                 "cmp${cc}ps {$src, $dst|$dst, $src}", []>;
 def CMPPSrm : PSI<0xC2, MRMSrcMem, 
-                (ops V4F32:$dst, V4F32:$src1, f128mem:$src, SSECC:$cc),
+                (ops VR128:$dst, VR128:$src1, f128mem:$src, SSECC:$cc),
                 "cmp${cc}ps {$src, $dst|$dst, $src}", []>;
 def CMPPDrr : PDI<0xC2, MRMSrcReg, 
-                (ops V2F64:$dst, V2F64:$src1, V2F64:$src, SSECC:$cc),
+                (ops VR128:$dst, VR128:$src1, VR128:$src, SSECC:$cc),
                 "cmp${cc}pd {$src, $dst|$dst, $src}", []>;
 def CMPPDrm : PDI<0xC2, MRMSrcMem, 
-                (ops V2F64:$dst, V2F64:$src1, f128mem:$src, SSECC:$cc),
+                (ops VR128:$dst, VR128:$src1, f128mem:$src, SSECC:$cc),
                 "cmp${cc}pd {$src, $dst|$dst, $src}", []>;
 }
 
 // Shuffle and unpack instructions
 def SHUFPSrr : PSI<0xC6, MRMSrcReg, 
-                   (ops V4F32:$dst, V4F32:$src1, V4F32:$src2, i8imm:$src3),
+                   (ops VR128:$dst, VR128:$src1, VR128:$src2, i8imm:$src3),
                    "shufps {$src3, $src2, $dst|$dst, $src2, $src3}", []>;
 def SHUFPSrm : PSI<0xC6, MRMSrcMem, 
-                   (ops V4F32:$dst, V4F32:$src1, f128mem:$src2, i8imm:$src3),
+                   (ops VR128:$dst, VR128:$src1, f128mem:$src2, i8imm:$src3),
                    "shufps {$src3, $src2, $dst|$dst, $src2, $src3}", []>;
 def SHUFPDrr : PDI<0xC6, MRMSrcReg, 
-                   (ops V2F64:$dst, V2F64:$src1, V2F64:$src2, i8imm:$src3),
+                   (ops VR128:$dst, VR128:$src1, VR128:$src2, i8imm:$src3),
                    "shufpd {$src3, $src2, $dst|$dst, $src2, $src3}", []>;
 def SHUFPDrm : PDI<0xC6, MRMSrcMem, 
-                   (ops V2F64:$dst, V2F64:$src1, f128mem:$src2, i8imm:$src3),
+                   (ops VR128:$dst, VR128:$src1, f128mem:$src2, i8imm:$src3),
                    "shufpd {$src3, $src2, $dst|$dst, $src2, $src3}", []>;
 
 def UNPCKHPSrr : PSI<0x15, MRMSrcReg, 
-                    (ops V4F32:$dst, V4F32:$src1, V4F32:$src2),
+                    (ops VR128:$dst, VR128:$src1, VR128:$src2),
                     "unpckhps {$src2, $dst|$dst, $src2}", []>;
 def UNPCKHPSrm : PSI<0x15, MRMSrcMem, 
-                    (ops V4F32:$dst, V4F32:$src1, f128mem:$src2),
+                    (ops VR128:$dst, VR128:$src1, f128mem:$src2),
                     "unpckhps {$src2, $dst|$dst, $src2}", []>;
 def UNPCKHPDrr : PDI<0x15, MRMSrcReg, 
-                    (ops V2F64:$dst, V2F64:$src1, V2F64:$src2),
+                    (ops VR128:$dst, VR128:$src1, VR128:$src2),
                     "unpckhpd {$src2, $dst|$dst, $src2}", []>;
 def UNPCKHPDrm : PDI<0x15, MRMSrcMem, 
-                    (ops V2F64:$dst, V2F64:$src1, f128mem:$src2),
+                    (ops VR128:$dst, VR128:$src1, f128mem:$src2),
                     "unpckhpd {$src2, $dst|$dst, $src2}", []>;
 def UNPCKLPSrr : PSI<0x14, MRMSrcReg, 
-                    (ops V4F32:$dst, V4F32:$src1, V4F32:$src2),
+                    (ops VR128:$dst, VR128:$src1, VR128:$src2),
                     "unpcklps {$src2, $dst|$dst, $src2}", []>;
 def UNPCKLPSrm : PSI<0x14, MRMSrcMem, 
-                    (ops V4F32:$dst, V4F32:$src1, f128mem:$src2),
+                    (ops VR128:$dst, VR128:$src1, f128mem:$src2),
                     "unpcklps {$src2, $dst|$dst, $src2}", []>;
 def UNPCKLPDrr : PDI<0x14, MRMSrcReg, 
-                    (ops V2F64:$dst, V2F64:$src1, V2F64:$src2),
+                    (ops VR128:$dst, VR128:$src1, VR128:$src2),
                     "unpcklpd {$src2, $dst|$dst, $src2}", []>;
 def UNPCKLPDrm : PDI<0x14, MRMSrcMem, 
-                    (ops V2F64:$dst, V2F64:$src1, f128mem:$src2),
+                    (ops VR128:$dst, VR128:$src1, f128mem:$src2),
                     "unpcklpd {$src2, $dst|$dst, $src2}", []>;
 
 //===----------------------------------------------------------------------===//


Index: llvm/lib/Target/X86/X86RegisterInfo.cpp
diff -u llvm/lib/Target/X86/X86RegisterInfo.cpp:1.129 llvm/lib/Target/X86/X86RegisterInfo.cpp:1.130
--- llvm/lib/Target/X86/X86RegisterInfo.cpp:1.129	Thu Mar 16 20:36:22 2006
+++ llvm/lib/Target/X86/X86RegisterInfo.cpp	Fri Mar 17 19:23:20 2006
@@ -61,9 +61,7 @@
     Opc = X86::MOVSSmr;
   } else if (RC == &X86::FR64RegClass) {
     Opc = X86::MOVSDmr;
-  } else if (RC == &X86::V4F32RegClass) {
-    Opc = X86::MOVAPSmr;
-  } else if (RC == &X86::V2F64RegClass) {
+  } else if (RC == &X86::VR128RegClass) {
     Opc = X86::MOVAPDmr;
   } else {
     assert(0 && "Unknown regclass");
@@ -89,9 +87,7 @@
     Opc = X86::MOVSSrm;
   } else if (RC == &X86::FR64RegClass) {
     Opc = X86::MOVSDrm;
-  } else if (RC == &X86::V4F32RegClass) {
-    Opc = X86::MOVAPSrm;
-  } else if (RC == &X86::V2F64RegClass) {
+  } else if (RC == &X86::VR128RegClass) {
     Opc = X86::MOVAPDrm;
   } else {
     assert(0 && "Unknown regclass");
@@ -117,9 +113,7 @@
     Opc = X86::FsMOVAPSrr;
   } else if (RC == &X86::FR64RegClass) {
     Opc = X86::FsMOVAPDrr;
-  } else if (RC == &X86::V4F32RegClass) {
-    Opc = X86::MOVAPSrr;
-  } else if (RC == &X86::V2F64RegClass) {
+  } else if (RC == &X86::VR128RegClass) {
     Opc = X86::MOVAPDrr;
   } else {
     assert(0 && "Unknown regclass");





From lattner at cs.uiuc.edu  Fri Mar 17 19:43:40 2006
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Fri, 17 Mar 2006 19:43:40 -0600
Subject: [llvm-commits] CVS: llvm/include/llvm/CodeGen/SelectionDAGNodes.h 
Message-ID: <200603180143.TAA05879@zion.cs.uiuc.edu>



Changes in directory llvm/include/llvm/CodeGen:

SelectionDAGNodes.h updated: 1.112 -> 1.113
---
Log message:

Update comments.


---
Diffs of the changes:  (+5 -4)

 SelectionDAGNodes.h |    9 +++++----
 1 files changed, 5 insertions(+), 4 deletions(-)


Index: llvm/include/llvm/CodeGen/SelectionDAGNodes.h
diff -u llvm/include/llvm/CodeGen/SelectionDAGNodes.h:1.112 llvm/include/llvm/CodeGen/SelectionDAGNodes.h:1.113
--- llvm/include/llvm/CodeGen/SelectionDAGNodes.h:1.112	Fri Mar 17 13:53:41 2006
+++ llvm/include/llvm/CodeGen/SelectionDAGNodes.h	Fri Mar 17 19:43:28 2006
@@ -85,9 +85,10 @@
     TargetConstantPool,
     TargetExternalSymbol,
 
-    // Abstract version of ConstantVec with abstract Vector type. The first node
-    // is a constant element count, the second is a value type indicating the
-    // type of the elements.
+    // Abstract version of ConstantVec with abstract Vector type. The first N-2
+    // operands are the constants to initialize the vector, the N-2nd operand
+    // is a constant element count, and that last operand is the value type
+    // indicating the type of the elements.
     VConstant,
 
     // CopyToReg - This node has three operands: a chain, a register number to
@@ -157,7 +158,7 @@
     // a constant element count, and a value type node indicating the type of
     // the elements.  The order is count, type, op0, op1.  All vector opcodes,
     // including VLOAD and VConstant must currently have count and type as
-    // their 1st and 2nd arguments.
+    // their last two operands.
     VADD, VSUB, VMUL, VSDIV, VUDIV,
     VAND, VOR, VXOR,
 





From lattner at cs.uiuc.edu  Fri Mar 17 19:44:56 2006
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Fri, 17 Mar 2006 19:44:56 -0600
Subject: [llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
	SelectionDAG.cpp SelectionDAGISel.cpp 
Message-ID: <200603180144.TAA05920@zion.cs.uiuc.edu>



Changes in directory llvm/lib/CodeGen/SelectionDAG:

LegalizeDAG.cpp updated: 1.316 -> 1.317
SelectionDAG.cpp updated: 1.272 -> 1.273
SelectionDAGISel.cpp updated: 1.193 -> 1.194
---
Log message:

Change the structure of lowering vector stuff.  Note: This breaks some 
things.


---
Diffs of the changes:  (+318 -214)

 LegalizeDAG.cpp      |  429 +++++++++++++++++++++++++++++++--------------------
 SelectionDAG.cpp     |    4 
 SelectionDAGISel.cpp |   99 +++++------
 3 files changed, 318 insertions(+), 214 deletions(-)


Index: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.316 llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.317
--- llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.316	Thu Mar 16 19:40:33 2006
+++ llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp	Fri Mar 17 19:44:44 2006
@@ -74,12 +74,21 @@
   /// us to avoid promoting the same thing more than once.
   std::map PromotedNodes;
 
-  /// ExpandedNodes - For nodes that need to be expanded, and which have more
-  /// than one use, this map indicates which which operands are the expanded
-  /// version of the input.  This allows us to avoid expanding the same node
-  /// more than once.
+  /// ExpandedNodes - For nodes that need to be expanded this map indicates
+  /// which which operands are the expanded version of the input.  This allows
+  /// us to avoid expanding the same node more than once.
   std::map > ExpandedNodes;
 
+  /// SplitNodes - For vector nodes that need to be split, this map indicates
+  /// which which operands are the split version of the input.  This allows us
+  /// to avoid splitting the same node more than once.
+  std::map > SplitNodes;
+  
+  /// PackedNodes - For nodes that need to be packed from MVT::Vector types to
+  /// concrete packed types, this contains the mapping of ones we have already
+  /// processed to the result.
+  std::map PackedNodes;
+  
   void AddLegalizedOperand(SDOperand From, SDOperand To) {
     LegalizedNodes.insert(std::make_pair(From, To));
     // If someone requests legalization of the new node, return itself.
@@ -113,11 +122,40 @@
   void LegalizeDAG();
 
 private:
-
+  /// HandleOp - Legalize, Promote, Expand or Pack the specified operand as
+  /// appropriate for its type.
+  void HandleOp(SDOperand Op);
+    
+  /// LegalizeOp - We know that the specified value has a legal type.
+  /// Recursively ensure that the operands have legal types, then return the
+  /// result.
   SDOperand LegalizeOp(SDOperand O);
-  void ExpandOp(SDOperand O, SDOperand &Lo, SDOperand &Hi);
+  
+  /// PromoteOp - Given an operation that produces a value in an invalid type,
+  /// promote it to compute the value into a larger type.  The produced value
+  /// will have the correct bits for the low portion of the register, but no
+  /// guarantee is made about the top bits: it may be zero, sign-extended, or
+  /// garbage.
   SDOperand PromoteOp(SDOperand O);
 
+  /// ExpandOp - Expand the specified SDOperand into its two component pieces
+  /// Lo&Hi.  Note that the Op MUST be an expanded type.  As a result of this,
+  /// the LegalizeNodes map is filled in for any results that are not expanded,
+  /// the ExpandedNodes map is filled in for any results that are expanded, and
+  /// the Lo/Hi values are returned.   This applies to integer types and Vector
+  /// types.
+  void ExpandOp(SDOperand O, SDOperand &Lo, SDOperand &Hi);
+
+  /// SplitVectorOp - Given an operand of MVT::Vector type, break it down into
+  /// two smaller values of MVT::Vector type.
+  void SplitVectorOp(SDOperand O, SDOperand &Lo, SDOperand &Hi);
+  
+  /// PackVectorOp - Given an operand of MVT::Vector type, convert it into the
+  /// equivalent operation that returns a packed value (e.g. MVT::V4F32).  When
+  /// this is called, we know that PackedVT is the right type for the result and
+  /// we know that this type is legal for the target.
+  SDOperand PackVectorOp(SDOperand O, MVT::ValueType PackedVT);
+  
   bool LegalizeAllNodesNotLeadingTo(SDNode *N, SDNode *Dest);
 
   void LegalizeSetCCOperands(SDOperand &LHS, SDOperand &RHS, SDOperand &CC);
@@ -149,6 +187,8 @@
 };
 }
 
+/// getScalarizedOpcode - Return the scalar opcode that corresponds to the
+/// specified vector opcode.
 static unsigned getScalarizedOpcode(unsigned VecOp, MVT::ValueType VT) {
   switch (VecOp) {
   default: assert(0 && "Don't know how to scalarize this opcode!");
@@ -220,23 +260,8 @@
          "Error: DAG is cyclic!");
   Visited.clear();
   
-  for (unsigned i = 0, e = Order.size(); i != e; ++i) {
-    SDNode *N = Order[i];
-    switch (getTypeAction(N->getValueType(0))) {
-    default: assert(0 && "Bad type action!");
-    case Legal:
-      LegalizeOp(SDOperand(N, 0));
-      break;
-    case Promote:
-      PromoteOp(SDOperand(N, 0));
-      break;
-    case Expand: {
-      SDOperand X, Y;
-      ExpandOp(SDOperand(N, 0), X, Y);
-      break;
-    }
-    }
-  }
+  for (unsigned i = 0, e = Order.size(); i != e; ++i)
+    HandleOp(SDOperand(Order[i], 0));
 
   // Finally, it's possible the root changed.  Get the new root.
   SDOperand OldRoot = DAG.getRoot();
@@ -246,6 +271,8 @@
   ExpandedNodes.clear();
   LegalizedNodes.clear();
   PromotedNodes.clear();
+  SplitNodes.clear();
+  PackedNodes.clear();
 
   // Remove dead nodes now.
   DAG.RemoveDeadNodes(OldRoot.Val);
@@ -350,8 +377,47 @@
   return false;
 }
 
+/// HandleOp - Legalize, Promote, Expand or Pack the specified operand as
+/// appropriate for its type.
+void SelectionDAGLegalize::HandleOp(SDOperand Op) {
+  switch (getTypeAction(Op.getValueType())) {
+  default: assert(0 && "Bad type action!");
+  case Legal:   LegalizeOp(Op); break;
+  case Promote: PromoteOp(Op);  break;
+  case Expand:
+    if (Op.getValueType() != MVT::Vector) {
+      SDOperand X, Y;
+      ExpandOp(Op, X, Y);
+    } else {
+      SDNode *N = Op.Val;
+      unsigned NumOps = N->getNumOperands();
+      unsigned NumElements =
+        cast(N->getOperand(NumOps-2))->getValue();
+      MVT::ValueType EVT = cast(N->getOperand(NumOps-1))->getVT();
+      MVT::ValueType PackedVT = getVectorType(EVT, NumElements);
+      if (PackedVT != MVT::Other && TLI.isTypeLegal(PackedVT)) {
+        // In the common case, this is a legal vector type, convert it to the
+        // packed operation and type now.
+        PackVectorOp(Op, PackedVT);
+      } else if (NumElements == 1) {
+        // Otherwise, if this is a single element vector, convert it to a
+        // scalar operation.
+        PackVectorOp(Op, EVT);
+      } else {
+        // Otherwise, this is a multiple element vector that isn't supported.
+        // Split it in half and legalize both parts.
+        SDOperand X, Y;
+        ExpandOp(Op, X, Y);
+      }
+    }
+    break;
+  }
+}
 
 
+/// LegalizeOp - We know that the specified value has a legal type.
+/// Recursively ensure that the operands have legal types, then return the
+/// result.
 SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) {
   assert(isTypeLegal(Op.getValueType()) &&
          "Caller should expand or promote operands that are not legal!");
@@ -361,19 +427,10 @@
   // register on this target, make sure to expand or promote them.
   if (Node->getNumValues() > 1) {
     for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i)
-      switch (getTypeAction(Node->getValueType(i))) {
-      case Legal: break;  // Nothing to do.
-      case Expand: {
-        SDOperand T1, T2;
-        ExpandOp(Op.getValue(i), T1, T2);
-        assert(LegalizedNodes.count(Op) &&
-               "Expansion didn't add legal operands!");
-        return LegalizedNodes[Op];
-      }
-      case Promote:
-        PromoteOp(Op.getValue(i));
+      if (getTypeAction(Node->getValueType(i)) != Legal) {
+        HandleOp(Op.getValue(i));
         assert(LegalizedNodes.count(Op) &&
-               "Promotion didn't add legal operands!");
+               "Handling didn't add legal operands!");
         return LegalizedNodes[Op];
       }
   }
@@ -1205,25 +1262,47 @@
       break;
 
     case Expand:
+      unsigned IncrementSize = 0;
       SDOperand Lo, Hi;
-      ExpandOp(Node->getOperand(1), Lo, Hi);
-
-      if (!TLI.isLittleEndian())
-        std::swap(Lo, Hi);
-
-      Lo = DAG.getNode(ISD::STORE, MVT::Other, Tmp1, Lo, Tmp2,
-                       Node->getOperand(3));
+      
       // If this is a vector type, then we have to calculate the increment as
       // the product of the element size in bytes, and the number of elements
       // in the high half of the vector.
-      unsigned IncrementSize;
-      if (MVT::Vector == Hi.getValueType()) {
-        unsigned NumElems = cast(Hi.getOperand(0))->getValue();
-        MVT::ValueType EVT = cast(Hi.getOperand(1))->getVT();
-        IncrementSize = NumElems * MVT::getSizeInBits(EVT)/8;
+      if (Node->getOperand(1).getValueType() == MVT::Vector) {
+        SDNode *InVal = Node->getOperand(1).Val;
+        unsigned NumElems =
+          cast(*(InVal->op_end()-2))->getValue();
+        MVT::ValueType EVT = cast(*(InVal->op_end()-1))->getVT();
+
+        // Figure out if there is a Packed type corresponding to this Vector
+        // type.  If so, convert to the packed type.
+        MVT::ValueType TVT = MVT::getVectorType(EVT, NumElems);
+        if (TVT != MVT::Other && TLI.isTypeLegal(TVT)) {
+          // Turn this into a normal store of the packed type.
+          Tmp3 = PackVectorOp(Node->getOperand(1), TVT);
+          Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp3, Tmp2, 
+                                          Node->getOperand(3));
+          break;
+        } else if (NumElems == 1) {
+          // Turn this into a normal store of the scalar type.
+          Tmp3 = PackVectorOp(Node->getOperand(1), EVT);
+          Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp3, Tmp2, 
+                                          Node->getOperand(3));
+          break;
+        } else {
+          SplitVectorOp(Node->getOperand(1), Lo, Hi);
+          IncrementSize = NumElems/2 * MVT::getSizeInBits(EVT)/8;
+        }
       } else {
+        ExpandOp(Node->getOperand(1), Lo, Hi);
         IncrementSize = MVT::getSizeInBits(Hi.getValueType())/8;
       }
+
+      if (!TLI.isLittleEndian())
+        std::swap(Lo, Hi);
+
+      Lo = DAG.getNode(ISD::STORE, MVT::Other, Tmp1, Lo, Tmp2,
+                       Node->getOperand(3));
       Tmp2 = DAG.getNode(ISD::ADD, Tmp2.getValueType(), Tmp2,
                          getIntPtrConstant(IncrementSize));
       assert(isTypeLegal(Tmp2.getValueType()) &&
@@ -1757,7 +1836,6 @@
     AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0));
     AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1));
     return Result;
-    break;
 
   case ISD::ADDE:
   case ISD::SUBE:
@@ -1770,7 +1848,6 @@
     AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0));
     AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1));
     return Result;
-    break;
     
   case ISD::BUILD_PAIR: {
     MVT::ValueType PairTy = Node->getValueType(0);
@@ -3444,43 +3521,6 @@
     Hi = DAG.getConstant(Cst >> MVT::getSizeInBits(NVT), NVT);
     break;
   }
-  case ISD::VConstant: {
-    unsigned NumElements =
-      cast(Node->getOperand(0))->getValue() / 2;
-    MVT::ValueType EVT = cast(Node->getOperand(1))->getVT();
-    MVT::ValueType TVT = (NumElements > 1)
-                         ? getVectorType(EVT, NumElements) : EVT;
-    // If type of bisected vector is legal, turn it into a ConstantVec (which
-    // will be lowered to a ConstantPool or something else). Otherwise, bisect
-    // the VConstant, and return each half as a new VConstant.
-    unsigned Opc = ISD::ConstantVec;
-    std::vector LoOps, HiOps;
-    if (!(TVT != MVT::Other &&
-          (!MVT::isVector(TVT) || TLI.isTypeLegal(TVT)))) {
-      Opc = ISD::VConstant;
-      TVT = MVT::Vector;
-      SDOperand Num = DAG.getConstant(NumElements, MVT::i32);
-      SDOperand Typ = DAG.getValueType(EVT);
-      HiOps.push_back(Num);
-      HiOps.push_back(Typ);
-      LoOps.push_back(Num);
-      LoOps.push_back(Typ);
-    }
-
-    if (NumElements == 1) {
-      Hi = Node->getOperand(2);
-      Lo = Node->getOperand(3);
-    } else {
-      for (unsigned I = 0, E = NumElements; I < E; ++I) {
-        HiOps.push_back(Node->getOperand(I+2));
-        LoOps.push_back(Node->getOperand(I+2+NumElements));
-      }
-      Hi = DAG.getNode(Opc, TVT, HiOps);
-      Lo = DAG.getNode(Opc, TVT, LoOps);
-    }
-    break;
-  }
-
   case ISD::BUILD_PAIR:
     // Return the operands.
     Lo = Node->getOperand(0);
@@ -3580,80 +3620,6 @@
       std::swap(Lo, Hi);
     break;
   }
-  case ISD::VLOAD: {
-    SDOperand Ch = Node->getOperand(2);   // Legalize the chain.
-    SDOperand Ptr = Node->getOperand(3);  // Legalize the pointer.
-    unsigned NumElements =cast(Node->getOperand(0))->getValue();
-    MVT::ValueType EVT = cast(Node->getOperand(1))->getVT();
-    MVT::ValueType TVT = (NumElements/2 > 1)
-      ? getVectorType(EVT, NumElements/2) : EVT;
-    
-    // If type of split vector is legal, turn into a pair of scalar or
-    // packed loads.
-    if (TVT != MVT::Other &&
-        (!MVT::isVector(TVT) ||
-         (TLI.isTypeLegal(TVT) && TLI.isOperationLegal(ISD::LOAD, TVT)))) {
-      Lo = DAG.getLoad(TVT, Ch, Ptr, Node->getOperand(4));
-      // Increment the pointer to the other half.
-      unsigned IncrementSize = MVT::getSizeInBits(TVT)/8;
-      Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr,
-                        getIntPtrConstant(IncrementSize));
-      // FIXME: This creates a bogus srcvalue!
-      Hi = DAG.getLoad(TVT, Ch, Ptr, Node->getOperand(4));
-    } else {
-      NumElements /= 2; // Split the vector in half
-      Lo = DAG.getVecLoad(NumElements, EVT, Ch, Ptr, Node->getOperand(4));
-      unsigned IncrementSize = NumElements * MVT::getSizeInBits(EVT)/8;
-      Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr,
-                        getIntPtrConstant(IncrementSize));
-      // FIXME: This creates a bogus srcvalue!
-      Hi = DAG.getVecLoad(NumElements, EVT, Ch, Ptr, Node->getOperand(4));
-    }
-    
-    // Build a factor node to remember that this load is independent of the
-    // other one.
-    SDOperand TF = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1),
-                               Hi.getValue(1));
-    
-    // Remember that we legalized the chain.
-    AddLegalizedOperand(Op.getValue(1), LegalizeOp(TF));
-    if (!TLI.isLittleEndian())
-      std::swap(Lo, Hi);
-    break;
-  }
-  case ISD::VADD:
-  case ISD::VSUB:
-  case ISD::VMUL:
-  case ISD::VSDIV:
-  case ISD::VUDIV:
-  case ISD::VAND:
-  case ISD::VOR:
-  case ISD::VXOR: {
-    unsigned NumElements =cast(Node->getOperand(0))->getValue();
-    MVT::ValueType EVT = cast(Node->getOperand(1))->getVT();
-    MVT::ValueType TVT = (NumElements/2 > 1)
-                         ? getVectorType(EVT, NumElements/2) : EVT;
-    SDOperand LL, LH, RL, RH;
-    
-    ExpandOp(Node->getOperand(2), LL, LH);
-    ExpandOp(Node->getOperand(3), RL, RH);
-
-    // If type of split vector is legal, turn into a pair of scalar / packed
-    // ADD, SUB, or MUL.
-    unsigned Opc = getScalarizedOpcode(Node->getOpcode(), EVT);
-    if (TVT != MVT::Other &&
-        (!MVT::isVector(TVT) ||
-         (TLI.isTypeLegal(TVT) && TLI.isOperationLegal(Opc, TVT)))) {
-      Lo = DAG.getNode(Opc, TVT, LL, RL);
-      Hi = DAG.getNode(Opc, TVT, LH, RH);
-    } else {
-      SDOperand Num = DAG.getConstant(NumElements/2, MVT::i32);
-      SDOperand Typ = DAG.getValueType(EVT);
-      Lo = DAG.getNode(Node->getOpcode(), MVT::Vector, Num, Typ, LL, RL);
-      Hi = DAG.getNode(Node->getOpcode(), MVT::Vector, Num, Typ, LH, RH);
-    }
-    break;
-  }
   case ISD::AND:
   case ISD::OR:
   case ISD::XOR: {   // Simple logical operators -> two trivial pieces.
@@ -4018,6 +3984,149 @@
   assert(isNew && "Value already expanded?!?");
 }
 
+/// SplitVectorOp - Given an operand of MVT::Vector type, break it down into
+/// two smaller values of MVT::Vector type.
+void SelectionDAGLegalize::SplitVectorOp(SDOperand Op, SDOperand &Lo,
+                                         SDOperand &Hi) {
+  assert(Op.getValueType() == MVT::Vector && "Cannot split non-vector type!");
+  SDNode *Node = Op.Val;
+  unsigned NumElements = cast(*(Node->op_end()-2))->getValue();
+  assert(NumElements > 1 && "Cannot split a single element vector!");
+  unsigned NewNumElts = NumElements/2;
+  SDOperand NewNumEltsNode = DAG.getConstant(NewNumElts, MVT::i32);
+  SDOperand TypeNode = *(Node->op_end()-1);
+  
+  // See if we already split it.
+  std::map >::iterator I
+    = SplitNodes.find(Op);
+  if (I != SplitNodes.end()) {
+    Lo = I->second.first;
+    Hi = I->second.second;
+    return;
+  }
+  
+  switch (Node->getOpcode()) {
+  case ISD::VConstant: {
+    std::vector LoOps(Node->op_begin(), Node->op_begin()+NewNumElts);
+    LoOps.push_back(NewNumEltsNode);
+    LoOps.push_back(TypeNode);
+    Lo = DAG.getNode(ISD::VConstant, MVT::Vector, LoOps);
+
+    std::vector HiOps(Node->op_begin()+NewNumElts, Node->op_end()-2);
+    HiOps.push_back(NewNumEltsNode);
+    HiOps.push_back(TypeNode);
+    Hi = DAG.getNode(ISD::VConstant, MVT::Vector, HiOps);
+    break;
+  }
+  case ISD::VADD:
+  case ISD::VSUB:
+  case ISD::VMUL:
+  case ISD::VSDIV:
+  case ISD::VUDIV:
+  case ISD::VAND:
+  case ISD::VOR:
+  case ISD::VXOR: {
+    SDOperand LL, LH, RL, RH;
+    SplitVectorOp(Node->getOperand(0), LL, LH);
+    SplitVectorOp(Node->getOperand(1), RL, RH);
+    
+    Lo = DAG.getNode(Node->getOpcode(), MVT::Vector, LL, RL,
+                     NewNumEltsNode, TypeNode);
+    Hi = DAG.getNode(Node->getOpcode(), MVT::Vector, LH, RH,
+                     NewNumEltsNode, TypeNode);
+    break;
+  }
+  case ISD::VLOAD: {
+    SDOperand Ch = Node->getOperand(0);   // Legalize the chain.
+    SDOperand Ptr = Node->getOperand(1);  // Legalize the pointer.
+    MVT::ValueType EVT = cast(TypeNode)->getVT();
+    
+    Lo = DAG.getVecLoad(NewNumElts, EVT, Ch, Ptr, Node->getOperand(2));
+    unsigned IncrementSize = NewNumElts * MVT::getSizeInBits(EVT)/8;
+    Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr,
+                      getIntPtrConstant(IncrementSize));
+    // FIXME: This creates a bogus srcvalue!
+    Hi = DAG.getVecLoad(NewNumElts, EVT, Ch, Ptr, Node->getOperand(2));
+    
+    // Build a factor node to remember that this load is independent of the
+    // other one.
+    SDOperand TF = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1),
+                               Hi.getValue(1));
+    
+    // Remember that we legalized the chain.
+    AddLegalizedOperand(Op.getValue(1), LegalizeOp(TF));
+    if (!TLI.isLittleEndian())
+      std::swap(Lo, Hi);
+    break;
+  }
+  }
+      
+  // Remember in a map if the values will be reused later.
+  bool isNew =
+    SplitNodes.insert(std::make_pair(Op, std::make_pair(Lo, Hi))).second;
+  assert(isNew && "Value already expanded?!?");
+}
+
+
+/// PackVectorOp - Given an operand of MVT::Vector type, convert it into the
+/// equivalent operation that returns a scalar (e.g. F32) or packed value
+/// (e.g. MVT::V4F32).  When this is called, we know that PackedVT is the right
+/// type for the result.
+SDOperand SelectionDAGLegalize::PackVectorOp(SDOperand Op, 
+                                             MVT::ValueType NewVT) {
+  assert(Op.getValueType() == MVT::Vector && "Bad PackVectorOp invocation!");
+  SDNode *Node = Op.Val;
+  
+  // See if we already packed it.
+  std::map::iterator I = PackedNodes.find(Op);
+  if (I != PackedNodes.end()) return I->second;
+  
+  SDOperand Result;
+  switch (Node->getOpcode()) {
+  default: assert(0 && "Unknown vector operation!");
+  case ISD::VADD:
+  case ISD::VSUB:
+  case ISD::VMUL:
+  case ISD::VSDIV:
+  case ISD::VUDIV:
+  case ISD::VAND:
+  case ISD::VOR:
+  case ISD::VXOR:
+    Result = DAG.getNode(getScalarizedOpcode(Node->getOpcode(), NewVT),
+                         NewVT, 
+                         PackVectorOp(Node->getOperand(0), NewVT),
+                         PackVectorOp(Node->getOperand(1), NewVT));
+    break;
+  case ISD::VLOAD: {
+    SDOperand Ch = LegalizeOp(Node->getOperand(2));   // Legalize the chain.
+    SDOperand Ptr = LegalizeOp(Node->getOperand(3));  // Legalize the pointer.
+    
+    Result = DAG.getLoad(NewVT, Ch, Ptr, Node->getOperand(4));
+    
+    // Remember that we legalized the chain.
+    AddLegalizedOperand(Op.getValue(1), LegalizeOp(Result.getValue(1)));
+    break;
+  }
+  case ISD::VConstant:
+    if (!MVT::isVector(NewVT)) {
+      Result = Node->getOperand(0);
+    } else {
+      // If type of bisected vector is legal, turn it into a ConstantVec (which
+      // will be lowered to a ConstantPool or something else). Otherwise, bisect
+      // the VConstant, and return each half as a new VConstant.
+      std::vector Ops(Node->op_begin(), Node->op_end()-2);
+      Result = DAG.getNode(ISD::ConstantVec, NewVT, Ops);
+    }
+    break;
+  }
+
+  if (TLI.isTypeLegal(NewVT))
+    Result = LegalizeOp(Result);
+  bool isNew = PackedNodes.insert(std::make_pair(Op, Result)).second;
+  assert(isNew && "Value already packed?");
+  return Result;
+}
+
 
 // SelectionDAG::Legalize - This is the entry point for the file.
 //


Index: llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp:1.272 llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp:1.273
--- llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp:1.272	Fri Mar 17 13:53:59 2006
+++ llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp	Fri Mar 17 19:44:44 2006
@@ -1422,11 +1422,11 @@
   if (N) return SDOperand(N, 0);
   std::vector Ops;
   Ops.reserve(5);
-  Ops.push_back(getConstant(Count, MVT::i32));
-  Ops.push_back(getValueType(EVT));
   Ops.push_back(Chain);
   Ops.push_back(Ptr);
   Ops.push_back(SV);
+  Ops.push_back(getConstant(Count, MVT::i32));
+  Ops.push_back(getValueType(EVT));
   std::vector VTs;
   VTs.reserve(2);
   VTs.push_back(MVT::Vector); VTs.push_back(MVT::Other);  // Add token chain.


Index: llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.193 llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.194
--- llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.193	Thu Mar 16 19:40:33 2006
+++ llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp	Fri Mar 17 19:44:44 2006
@@ -423,8 +423,6 @@
   void visitUnreachable(UnreachableInst &I) { /* noop */ }
 
   // These all get lowered before this pass.
-  void visitExtractElement(ExtractElementInst &I) { assert(0 && "TODO"); }
-  void visitInsertElement(InsertElementInst &I) { assert(0 && "TODO"); }
   void visitSwitch(SwitchInst &I) { assert(0 && "TODO"); }
   void visitInvoke(InvokeInst &I) { assert(0 && "TODO"); }
   void visitUnwind(UnwindInst &I) { assert(0 && "TODO"); }
@@ -465,6 +463,9 @@
   void visitSetLT(User &I) { visitSetCC(I, ISD::SETLT, ISD::SETULT); }
   void visitSetGT(User &I) { visitSetCC(I, ISD::SETGT, ISD::SETUGT); }
 
+  void visitExtractElement(ExtractElementInst &I) { assert(0 && "TODO"); }
+  void visitInsertElement(InsertElementInst &I);
+
   void visitGetElementPtr(User &I);
   void visitCast(User &I);
   void visitSelect(User &I);
@@ -550,21 +551,12 @@
         Ops.assign(NumElements, Op);
       }
       
-      // Handle the case where we have a 1-element vector, in which
-      // case we want to immediately turn it into a scalar constant.
-      if (Ops.size() == 1) {
-        return N = Ops[0];
-      } else if (TVT != MVT::Other && TLI.isTypeLegal(TVT)) {
-        return N = DAG.getNode(ISD::ConstantVec, TVT, Ops);
-      } else {
-        // If the packed type isn't legal, then create a ConstantVec node with
-        // generic Vector type instead.
-        SDOperand Num = DAG.getConstant(NumElements, MVT::i32);
-        SDOperand Typ = DAG.getValueType(PVT);
-        Ops.insert(Ops.begin(), Typ);
-        Ops.insert(Ops.begin(), Num);
-        return N = DAG.getNode(ISD::VConstant, MVT::Vector, Ops);
-      }
+      // Create a ConstantVec node with generic Vector type.
+      SDOperand Num = DAG.getConstant(NumElements, MVT::i32);
+      SDOperand Typ = DAG.getValueType(PVT);
+      Ops.push_back(Num);
+      Ops.push_back(Typ);
+      return N = DAG.getNode(ISD::VConstant, MVT::Vector, Ops);
     } else {
       // Canonicalize all constant ints to be unsigned.
       return N = DAG.getConstant(cast(C)->getRawValue(),VT);
@@ -724,27 +716,9 @@
     setValue(&I, DAG.getNode(FPOp, Op1.getValueType(), Op1, Op2));
   } else {
     const PackedType *PTy = cast(Ty);
-    unsigned NumElements = PTy->getNumElements();
-    MVT::ValueType PVT = TLI.getValueType(PTy->getElementType());
-    MVT::ValueType TVT = MVT::getVectorType(PVT, NumElements);
-    
-    // Immediately scalarize packed types containing only one element, so that
-    // the Legalize pass does not have to deal with them.  Similarly, if the
-    // abstract vector is going to turn into one that the target natively
-    // supports, generate that type now so that Legalize doesn't have to deal
-    // with that either.  These steps ensure that Legalize only has to handle
-    // vector types in its Expand case.
-    unsigned Opc = MVT::isFloatingPoint(PVT) ? FPOp : IntOp;
-    if (NumElements == 1) {
-      setValue(&I, DAG.getNode(Opc, PVT, Op1, Op2));
-    } else if (TVT != MVT::Other &&
-               TLI.isTypeLegal(TVT) && TLI.isOperationLegal(Opc, TVT)) {
-      setValue(&I, DAG.getNode(Opc, TVT, Op1, Op2));
-    } else {
-      SDOperand Num = DAG.getConstant(NumElements, MVT::i32);
-      SDOperand Typ = DAG.getValueType(PVT);
-      setValue(&I, DAG.getNode(VecOp, MVT::Vector, Num, Typ, Op1, Op2));
-    }
+    SDOperand Num = DAG.getConstant(PTy->getNumElements(), MVT::i32);
+    SDOperand Typ = DAG.getValueType(TLI.getValueType(PTy->getElementType()));
+    setValue(&I, DAG.getNode(VecOp, MVT::Vector, Op1, Op2, Num, Typ));
   }
 }
 
@@ -814,6 +788,8 @@
         setValue(&I, DAG.getNode(ISD::FP_TO_UINT, DestVT, N));
     }
   } else {
+    assert(0 && "Cannot bitconvert vectors yet!");
+#if 0
     const PackedType *SrcTy = cast(I.getOperand(0)->getType());
     const PackedType *DstTy = cast(I.getType());
     
@@ -850,9 +826,41 @@
         getLoadFrom(DstTy, FIPtr, DAG.getSrcValue(NULL), Store, false);
       setValue(&I, Val);
     }
+#endif
   }
 }
 
+void SelectionDAGLowering::visitInsertElement(InsertElementInst &I) {
+  const PackedType *Ty = cast(I.getType());
+  unsigned NumElements = Ty->getNumElements();
+  MVT::ValueType PVT = TLI.getValueType(Ty->getElementType());
+  MVT::ValueType TVT = MVT::getVectorType(PVT, NumElements);
+
+  SDOperand InVec = getValue(I.getOperand(0));
+  SDOperand InVal = getValue(I.getOperand(1));
+  SDOperand InIdx = DAG.getNode(ISD::ZERO_EXTEND, TLI.getPointerTy(),
+                                getValue(I.getOperand(2)));
+
+  // Immediately scalarize packed types containing only one element, so that
+  // the Legalize pass does not have to deal with them.  Similarly, if the
+  // abstract vector is going to turn into one that the target natively
+  // supports, generate that type now so that Legalize doesn't have to deal
+  // with that either.  These steps ensure that Legalize only has to handle
+  // vector types in its Expand case.
+  if (NumElements == 1) {
+    setValue(&I, InVal);   // Must be insertelt(Vec, InVal, 0) -> InVal
+  } else if (TVT != MVT::Other && TLI.isTypeLegal(TVT) && 
+             TLI.isOperationLegal(ISD::INSERT_VECTOR_ELT, TVT)) {
+    setValue(&I, DAG.getNode(ISD::INSERT_VECTOR_ELT, TVT, InVec, InVal, InIdx));
+  } else {
+    SDOperand Num = DAG.getConstant(NumElements, MVT::i32);
+    SDOperand Typ = DAG.getValueType(PVT);
+    setValue(&I, DAG.getNode(ISD::VINSERT_VECTOR_ELT, MVT::Vector,
+                             InVec, InVal, InIdx, Num, Typ));
+  }
+}
+
+
 void SelectionDAGLowering::visitGetElementPtr(User &I) {
   SDOperand N = getValue(I.getOperand(0));
   const Type *Ty = I.getOperand(0)->getType();
@@ -989,22 +997,9 @@
                                             SDOperand SrcValue, SDOperand Root,
                                             bool isVolatile) {
   SDOperand L;
-  
   if (const PackedType *PTy = dyn_cast(Ty)) {
-    unsigned NumElements = PTy->getNumElements();
     MVT::ValueType PVT = TLI.getValueType(PTy->getElementType());
-    MVT::ValueType TVT = MVT::getVectorType(PVT, NumElements);
-    
-    // Immediately scalarize packed types containing only one element, so that
-    // the Legalize pass does not have to deal with them.
-    if (NumElements == 1) {
-      L = DAG.getLoad(PVT, Root, Ptr, SrcValue);
-    } else if (TVT != MVT::Other && TLI.isTypeLegal(TVT) &&
-               TLI.isOperationLegal(ISD::LOAD, TVT)) {
-      L = DAG.getLoad(TVT, Root, Ptr, SrcValue);
-    } else {
-      L = DAG.getVecLoad(NumElements, PVT, Root, Ptr, SrcValue);
-    }
+    L = DAG.getVecLoad(PTy->getNumElements(), PVT, Root, Ptr, SrcValue);
   } else {
     L = DAG.getLoad(TLI.getValueType(Ty), Root, Ptr, SrcValue);
   }





From evan.cheng at apple.com  Sat Mar 18 02:03:24 2006
From: evan.cheng at apple.com (Evan Cheng)
Date: Sat, 18 Mar 2006 02:03:24 -0600
Subject: [llvm-commits] 
	CVS: llvm/lib/Transforms/Scalar/LoopStrengthReduce.cpp
Message-ID: <200603180803.CAA07409@zion.cs.uiuc.edu>



Changes in directory llvm/lib/Transforms/Scalar:

LoopStrengthReduce.cpp updated: 1.79 -> 1.80
---
Log message:

- Fixed a bogus if condition.
- Added more debugging info.
- Allow reuse of IV of negative stride. e.g. -4 stride == 2 * iv of -2 stride.


---
Diffs of the changes:  (+25 -19)

 LoopStrengthReduce.cpp |   44 +++++++++++++++++++++++++-------------------
 1 files changed, 25 insertions(+), 19 deletions(-)


Index: llvm/lib/Transforms/Scalar/LoopStrengthReduce.cpp
diff -u llvm/lib/Transforms/Scalar/LoopStrengthReduce.cpp:1.79 llvm/lib/Transforms/Scalar/LoopStrengthReduce.cpp:1.80
--- llvm/lib/Transforms/Scalar/LoopStrengthReduce.cpp:1.79	Fri Mar 17 18:44:49 2006
+++ llvm/lib/Transforms/Scalar/LoopStrengthReduce.cpp	Sat Mar 18 02:03:12 2006
@@ -77,15 +77,20 @@
   };
 
   /// IVInfo - This structure keeps track of one IV expression inserted during
-  /// StrengthReduceStridedIVUsers. It contains the base value, as well as the
-  /// PHI node and increment value created for rewrite.
+  /// StrengthReduceStridedIVUsers. It contains the stride, the common base, as
+  /// well as the PHI node and increment value created for rewrite.
   struct IVExpr {
+    SCEVHandle  Stride;
     SCEVHandle  Base;
     PHINode    *PHI;
     Value      *IncV;
 
-    IVExpr(const SCEVHandle &base, PHINode *phi, Value *incv)
-      : Base(base), PHI(phi), IncV(incv) {}
+    IVExpr()
+      : Stride(SCEVUnknown::getIntegerSCEV(0, Type::UIntTy)),
+        Base  (SCEVUnknown::getIntegerSCEV(0, Type::UIntTy)) {}
+    IVExpr(const SCEVHandle &stride, const SCEVHandle &base, PHINode *phi,
+           Value *incv)
+      : Stride(stride), Base(base), PHI(phi), IncV(incv) {}
   };
 
   /// IVsOfOneStride - This structure keeps track of all IV expression inserted
@@ -93,8 +98,9 @@
   struct IVsOfOneStride {
     std::vector IVs;
 
-    void addIV(const SCEVHandle &Base, PHINode *PHI, Value *IncV) {
-      IVs.push_back(IVExpr(Base, PHI, IncV));
+    void addIV(const SCEVHandle &Stride, const SCEVHandle &Base, PHINode *PHI,
+               Value *IncV) {
+      IVs.push_back(IVExpr(Stride, Base, PHI, IncV));
     }
   };
 
@@ -863,22 +869,20 @@
 /// CheckForIVReuse - Returns the multiple if the stride is the multiple
 /// of a previous stride and it is a legal value for the target addressing
 /// mode scale component. This allows the users of this stride to be rewritten
-/// as prev iv * factor. It returns 1 if no reuse is possible.
+/// as prev iv * factor. It returns 0 if no reuse is possible.
 unsigned LoopStrengthReduce::CheckForIVReuse(const SCEVHandle &Stride,
                                              IVExpr &IV) {
-  if (!TLI)
-    return 1;
+  if (!TLI) return 0;
 
   if (SCEVConstant *SC = dyn_cast(Stride)) {
-    unsigned SInt = SC->getValue()->getRawValue();
-    if (SInt == 1)
-      return 1;
+    int64_t SInt = SC->getValue()->getSExtValue();
+    if (SInt == 1) return 0;
 
     for (TargetLowering::legal_am_scale_iterator
            I = TLI->legal_am_scale_begin(), E = TLI->legal_am_scale_end();
          I != E; ++I) {
       unsigned Scale = *I;
-      if (SInt >= Scale && (SInt % Scale) != 0)
+      if (abs(SInt) < Scale || (SInt % Scale) != 0)
         continue;
       std::map::iterator SI =
         IVsByStride.find(SCEVUnknown::getIntegerSCEV(SInt/Scale, Type::UIntTy));
@@ -894,7 +898,7 @@
     }
   }
 
-  return 1;
+  return 0;
 }
 
 
@@ -929,9 +933,11 @@
   // field of the target addressing mode.
   PHINode *NewPHI = NULL;
   Value   *IncV   = NULL;
-  IVExpr   ReuseIV(Stride, NULL, NULL);
+  IVExpr   ReuseIV;
   unsigned RewriteFactor = CheckForIVReuse(Stride, ReuseIV);
-  if (RewriteFactor > 1) {
+  if (RewriteFactor != 0) {
+    DEBUG(std::cerr << "BASED ON IV of STRIDE " << *ReuseIV.Stride
+          << " and BASE " << *ReuseIV.Base << " :\n");
     NewPHI = ReuseIV.PHI;
     IncV   = ReuseIV.IncV;
   }
@@ -994,7 +1000,7 @@
     = PreheaderRewriter.expandCodeFor(CommonExprs, PreInsertPt,
                                       ReplacedTy);
 
-  if (RewriteFactor == 1) {
+  if (RewriteFactor == 0) {
     // Create a new Phi for this base, and stick it in the loop header.
     NewPHI = new PHINode(ReplacedTy, "iv.", PhiInsertBefore);
     ++NumInserted;
@@ -1018,7 +1024,7 @@
     NewPHI->addIncoming(IncV, LatchBlock);
 
     // Remember this in case a later stride is multiple of this.
-    IVsByStride[Stride].addIV(CommonExprs, NewPHI, IncV);
+    IVsByStride[Stride].addIV(Stride, CommonExprs, NewPHI, IncV);
   } else {
     Constant *C = dyn_cast(CommonBaseV);
     if (!C ||
@@ -1076,7 +1082,7 @@
 
       // If we are reusing the iv, then it must be multiplied by a constant
       // factor take advantage of addressing mode scale component.
-      if (RewriteFactor != 1) {
+      if (RewriteFactor != 0) {
         RewriteExpr =
           SCEVMulExpr::get(SCEVUnknown::getIntegerSCEV(RewriteFactor,
                                                        RewriteExpr->getType()),





From lattner at cs.uiuc.edu  Sat Mar 18 17:49:06 2006
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Sat, 18 Mar 2006 17:49:06 -0600
Subject: [llvm-commits] 
	CVS: llvm/test/Regression/CodeGen/X86/fast-cc-callee-pops.ll
	fast-cc-pass-in-regs.ll 
Message-ID: <200603182349.RAA24358@zion.cs.uiuc.edu>



Changes in directory llvm/test/Regression/CodeGen/X86:

fast-cc-callee-pops.ll updated: 1.1 -> 1.2
fast-cc-pass-in-regs.ll updated: 1.3 -> 1.4
---
Log message:

update testcases for x86 fastcc changes.


---
Diffs of the changes:  (+4 -2)

 fast-cc-callee-pops.ll  |    2 +-
 fast-cc-pass-in-regs.ll |    4 +++-
 2 files changed, 4 insertions(+), 2 deletions(-)


Index: llvm/test/Regression/CodeGen/X86/fast-cc-callee-pops.ll
diff -u llvm/test/Regression/CodeGen/X86/fast-cc-callee-pops.ll:1.1 llvm/test/Regression/CodeGen/X86/fast-cc-callee-pops.ll:1.2
--- llvm/test/Regression/CodeGen/X86/fast-cc-callee-pops.ll:1.1	Fri May 13 17:15:26 2005
+++ llvm/test/Regression/CodeGen/X86/fast-cc-callee-pops.ll	Sat Mar 18 17:48:54 2006
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86 -x86-asm-syntax=intel -enable-x86-fastcc  | grep 'ret 20'
+; RUN: llvm-as < %s | llc -march=x86 -x86-asm-syntax=intel -enable-x86-fastcc  | grep 'ret 28'
 
 ; Check that a fastcc function pops its stack variables before returning.
 


Index: llvm/test/Regression/CodeGen/X86/fast-cc-pass-in-regs.ll
diff -u llvm/test/Regression/CodeGen/X86/fast-cc-pass-in-regs.ll:1.3 llvm/test/Regression/CodeGen/X86/fast-cc-pass-in-regs.ll:1.4
--- llvm/test/Regression/CodeGen/X86/fast-cc-pass-in-regs.ll:1.3	Fri May 13 11:20:59 2005
+++ llvm/test/Regression/CodeGen/X86/fast-cc-pass-in-regs.ll	Sat Mar 18 17:48:54 2006
@@ -1,7 +1,9 @@
 ; RUN: llvm-as < %s | llc -march=x86 -x86-asm-syntax=intel -enable-x86-fastcc  | grep 'mov %EDX, 1'
-
 ; check that fastcc is passing stuff in regs.
 
+; Argument reg passing is disabled due to regalloc issues.  FIXME!
+; XFAIL: *
+
 declare fastcc long %callee(long)
 
 long %caller() {





From lattner at cs.uiuc.edu  Sat Mar 18 18:08:01 2006
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Sat, 18 Mar 2006 18:08:01 -0600
Subject: [llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp 
Message-ID: <200603190008.SAA24487@zion.cs.uiuc.edu>



Changes in directory llvm/lib/CodeGen/SelectionDAG:

LegalizeDAG.cpp updated: 1.317 -> 1.318
---
Log message:

Fix the remaining bugs in the vector expansion rework I commited yesterday.
This fixes CodeGen/Generic/vector.ll


---
Diffs of the changes:  (+5 -4)

 LegalizeDAG.cpp |    9 +++++----
 1 files changed, 5 insertions(+), 4 deletions(-)


Index: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.317 llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.318
--- llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.317	Fri Mar 17 19:44:44 2006
+++ llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp	Sat Mar 18 18:07:49 2006
@@ -407,7 +407,7 @@
         // Otherwise, this is a multiple element vector that isn't supported.
         // Split it in half and legalize both parts.
         SDOperand X, Y;
-        ExpandOp(Op, X, Y);
+        SplitVectorOp(Op, X, Y);
       }
     }
     break;
@@ -4006,6 +4006,7 @@
   }
   
   switch (Node->getOpcode()) {
+  default: assert(0 && "Unknown vector operation!");
   case ISD::VConstant: {
     std::vector LoOps(Node->op_begin(), Node->op_begin()+NewNumElts);
     LoOps.push_back(NewNumEltsNode);
@@ -4098,10 +4099,10 @@
                          PackVectorOp(Node->getOperand(1), NewVT));
     break;
   case ISD::VLOAD: {
-    SDOperand Ch = LegalizeOp(Node->getOperand(2));   // Legalize the chain.
-    SDOperand Ptr = LegalizeOp(Node->getOperand(3));  // Legalize the pointer.
+    SDOperand Ch = LegalizeOp(Node->getOperand(0));   // Legalize the chain.
+    SDOperand Ptr = LegalizeOp(Node->getOperand(1));  // Legalize the pointer.
     
-    Result = DAG.getLoad(NewVT, Ch, Ptr, Node->getOperand(4));
+    Result = DAG.getLoad(NewVT, Ch, Ptr, Node->getOperand(2));
     
     // Remember that we legalized the chain.
     AddLegalizedOperand(Op.getValue(1), LegalizeOp(Result.getValue(1)));





From lattner at cs.uiuc.edu  Sat Mar 18 18:20:15 2006
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Sat, 18 Mar 2006 18:20:15 -0600
Subject: [llvm-commits] CVS: llvm/test/Regression/CodeGen/Generic/vector.ll 
Message-ID: <200603190020.SAA24630@zion.cs.uiuc.edu>



Changes in directory llvm/test/Regression/CodeGen/Generic:

vector.ll updated: 1.1 -> 1.2
---
Log message:

Add three new testcases


---
Diffs of the changes:  (+25 -0)

 vector.ll |   25 +++++++++++++++++++++++++
 1 files changed, 25 insertions(+)


Index: llvm/test/Regression/CodeGen/Generic/vector.ll
diff -u llvm/test/Regression/CodeGen/Generic/vector.ll:1.1 llvm/test/Regression/CodeGen/Generic/vector.ll:1.2
--- llvm/test/Regression/CodeGen/Generic/vector.ll:1.1	Fri Mar 17 14:04:40 2006
+++ llvm/test/Regression/CodeGen/Generic/vector.ll	Sat Mar 18 18:20:03 2006
@@ -8,6 +8,8 @@
 
 implementation
 
+;;; TEST HANDLING OF VARIOUS VECTOR SIZES
+
 void %test_f1(%f1 *%P, %f1* %Q, %f1 *%S) {
   %p = load %f1 *%P
   %q = load %f1* %Q
@@ -39,3 +41,26 @@
   store %f8 %R, %f8 *%S
   ret void
 }
+
+;;; TEST VECTOR CONSTRUCTS
+
+void %test_cst(%f4 *%P, %f4 *%S) {
+  %p = load %f4* %P
+  %R = add %f4 %p, 
+  store %f4 %R, %f4 *%S
+  ret void
+}
+
+void %test_zero(%f4 *%P, %f4 *%S) {
+  %p = load %f4* %P
+  %R = add %f4 %p, zeroinitializer
+  store %f4 %R, %f4 *%S
+  ret void
+}
+
+void %test_undef(%f4 *%P, %f4 *%S) {
+  %p = load %f4* %P
+  %R = add %f4 %p, undef
+  store %f4 %R, %f4 *%S
+  ret void
+}





From lattner at cs.uiuc.edu  Sat Mar 18 18:20:33 2006
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Sat, 18 Mar 2006 18:20:33 -0600
Subject: [llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
	SelectionDAGISel.cpp 
Message-ID: <200603190020.SAA24645@zion.cs.uiuc.edu>



Changes in directory llvm/lib/CodeGen/SelectionDAG:

LegalizeDAG.cpp updated: 1.318 -> 1.319
SelectionDAGISel.cpp updated: 1.194 -> 1.195
---
Log message:

implement vector.ll:test_undef


---
Diffs of the changes:  (+24 -9)

 LegalizeDAG.cpp      |    8 ++++++--
 SelectionDAGISel.cpp |   25 ++++++++++++++++++-------
 2 files changed, 24 insertions(+), 9 deletions(-)


Index: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.318 llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.319
--- llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.318	Sat Mar 18 18:07:49 2006
+++ llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp	Sat Mar 18 18:20:20 2006
@@ -730,12 +730,16 @@
       std::vector CV;
       if (MVT::isFloatingPoint(VT)) {
         for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) {
-          double V = cast(Node->getOperand(i))->getValue();
+          double V = 0;
+          if (Node->getOperand(i).getOpcode() != ISD::UNDEF)
+            V = cast(Node->getOperand(i))->getValue();
           CV.push_back(ConstantFP::get(OpNTy, V));
         }
       } else {
         for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) {
-          uint64_t V = cast(Node->getOperand(i))->getValue();
+          uint64_t V = 0;
+          if (Node->getOperand(i).getOpcode() != ISD::UNDEF)
+            V = cast(Node->getOperand(i))->getValue();
           CV.push_back(ConstantUInt::get(OpNTy, V));
         }
       }


Index: llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.194 llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.195
--- llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.194	Fri Mar 17 19:44:44 2006
+++ llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp	Sat Mar 18 18:20:20 2006
@@ -516,13 +516,26 @@
     } else if (isa(C)) {
       return N = DAG.getConstant(0, TLI.getPointerTy());
     } else if (isa(C)) {
-      return N = DAG.getNode(ISD::UNDEF, VT);
+      if (!isa(VTy))
+        return N = DAG.getNode(ISD::UNDEF, VT);
+
+      // Create a VConstant of undef nodes.
+      const PackedType *PTy = cast(VTy);
+      unsigned NumElements = PTy->getNumElements();
+      MVT::ValueType PVT = TLI.getValueType(PTy->getElementType());
+
+      std::vector Ops;
+      Ops.assign(NumElements, DAG.getNode(ISD::UNDEF, PVT));
+      
+      // Create a VConstant node with generic Vector type.
+      Ops.push_back(DAG.getConstant(NumElements, MVT::i32));
+      Ops.push_back(DAG.getValueType(PVT));
+      return N = DAG.getNode(ISD::VConstant, MVT::Vector, Ops);
     } else if (ConstantFP *CFP = dyn_cast(C)) {
       return N = DAG.getConstantFP(CFP->getValue(), VT);
     } else if (const PackedType *PTy = dyn_cast(VTy)) {
       unsigned NumElements = PTy->getNumElements();
       MVT::ValueType PVT = TLI.getValueType(PTy->getElementType());
-      MVT::ValueType TVT = MVT::getVectorType(PVT, NumElements);
       
       // Now that we know the number and type of the elements, push a
       // Constant or ConstantFP node onto the ops list for each element of
@@ -551,11 +564,9 @@
         Ops.assign(NumElements, Op);
       }
       
-      // Create a ConstantVec node with generic Vector type.
-      SDOperand Num = DAG.getConstant(NumElements, MVT::i32);
-      SDOperand Typ = DAG.getValueType(PVT);
-      Ops.push_back(Num);
-      Ops.push_back(Typ);
+      // Create a VConstant node with generic Vector type.
+      Ops.push_back(DAG.getConstant(NumElements, MVT::i32));
+      Ops.push_back(DAG.getValueType(PVT));
       return N = DAG.getNode(ISD::VConstant, MVT::Vector, Ops);
     } else {
       // Canonicalize all constant ints to be unsigned.





From lattner at cs.uiuc.edu  Sat Mar 18 18:52:37 2006
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Sat, 18 Mar 2006 18:52:37 -0600
Subject: [llvm-commits] CVS: llvm/include/llvm/CodeGen/SelectionDAGNodes.h 
Message-ID: <200603190052.SAA25028@zion.cs.uiuc.edu>



Changes in directory llvm/include/llvm/CodeGen:

SelectionDAGNodes.h updated: 1.113 -> 1.114
---
Log message:

Rename ConstantVec -> BUILD_VECTOR and VConstant -> VBUILD_VECTOR.  Allow
*BUILD_VECTOR to take variable inputs.


---
Diffs of the changes:  (+23 -24)

 SelectionDAGNodes.h |   47 +++++++++++++++++++++++------------------------
 1 files changed, 23 insertions(+), 24 deletions(-)


Index: llvm/include/llvm/CodeGen/SelectionDAGNodes.h
diff -u llvm/include/llvm/CodeGen/SelectionDAGNodes.h:1.113 llvm/include/llvm/CodeGen/SelectionDAGNodes.h:1.114
--- llvm/include/llvm/CodeGen/SelectionDAGNodes.h:1.113	Fri Mar 17 19:43:28 2006
+++ llvm/include/llvm/CodeGen/SelectionDAGNodes.h	Sat Mar 18 18:52:25 2006
@@ -67,15 +67,10 @@
     Constant, ConstantFP,
     GlobalAddress, FrameIndex, ConstantPool, ExternalSymbol,
 
-    // ConstantVec works like Constant or ConstantFP, except that it is not a
-    // leaf node.  All operands are either Constant or ConstantFP nodes.
-    ConstantVec,
-    
     // TargetConstant* - Like Constant*, but the DAG does not do any folding or
     // simplification of the constant.
     TargetConstant,
     TargetConstantFP,
-    TargetConstantVec, 
     
     // TargetGlobalAddress - Like GlobalAddress, but the DAG does no folding or
     // anything else with this node, and this is valid in the target-specific
@@ -85,12 +80,6 @@
     TargetConstantPool,
     TargetExternalSymbol,
 
-    // Abstract version of ConstantVec with abstract Vector type. The first N-2
-    // operands are the constants to initialize the vector, the N-2nd operand
-    // is a constant element count, and that last operand is the value type
-    // indicating the type of the elements.
-    VConstant,
-
     // CopyToReg - This node has three operands: a chain, a register number to
     // set to this value, and a value.  
     CopyToReg,
@@ -148,26 +137,36 @@
     // FCOPYSIGN(f32, f64) is allowed.
     FCOPYSIGN,
 
-    /// INSERT_VECTOR_ELT(VECTOR, VAL, IDX) - Returns VECTOR (a legal packed
-    /// type) with the element at IDX replaced with VAL.
-    INSERT_VECTOR_ELT,
+    /// VBUILD_VECTOR(ELT1, ELT2, ELT3, ELT4,...,  COUNT,TYPE) - Return a vector
+    /// with the specified, possibly variable, elements.  The number of elements
+    /// is required to be a power of two.
+    VBUILD_VECTOR,
+
+    /// BUILD_VECTOR(ELT1, ELT2, ELT3, ELT4,...) - Return a vector
+    /// with the specified, possibly variable, elements.  The number of elements
+    /// is required to be a power of two.
+    BUILD_VECTOR,
     
-    // BINOP(LHS, RHS,  COUNT,TYPE)
-    // Simple abstract vector operators.  Unlike the integer and floating point
-    // binary operators, these nodes also take two additional operands:
-    // a constant element count, and a value type node indicating the type of
-    // the elements.  The order is count, type, op0, op1.  All vector opcodes,
-    // including VLOAD and VConstant must currently have count and type as
-    // their last two operands.
-    VADD, VSUB, VMUL, VSDIV, VUDIV,
-    VAND, VOR, VXOR,
-
     /// VINSERT_VECTOR_ELT(VECTOR, VAL, IDX,  COUNT,TYPE) - Given a vector
     /// VECTOR, an element ELEMENT, and a (potentially variable) index IDX,
     /// return an vector with the specified element of VECTOR replaced with VAL.
     /// COUNT and TYPE specify the type of vector, as is standard for V* nodes.
     VINSERT_VECTOR_ELT,
     
+    /// INSERT_VECTOR_ELT(VECTOR, VAL, IDX) - Returns VECTOR (a legal packed
+    /// type) with the element at IDX replaced with VAL.
+    INSERT_VECTOR_ELT,
+    
+    /// BINOP(LHS, RHS,  COUNT,TYPE)
+    /// Simple abstract vector operators.  Unlike the integer and floating point
+    /// binary operators, these nodes also take two additional operands:
+    /// a constant element count, and a value type node indicating the type of
+    /// the elements.  The order is count, type, op0, op1.  All vector opcodes,
+    /// including VLOAD and VConstant must currently have count and type as
+    /// their last two operands.
+    VADD, VSUB, VMUL, VSDIV, VUDIV,
+    VAND, VOR, VXOR,
+
     // MULHU/MULHS - Multiply high - Multiply two integers of type iN, producing
     // an unsigned/signed value of type i[2*n], then return the top part.
     MULHU, MULHS,





From lattner at cs.uiuc.edu  Sat Mar 18 18:53:10 2006
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Sat, 18 Mar 2006 18:53:10 -0600
Subject: [llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
	SelectionDAG.cpp SelectionDAGISel.cpp 
Message-ID: <200603190053.SAA25067@zion.cs.uiuc.edu>



Changes in directory llvm/lib/CodeGen/SelectionDAG:

LegalizeDAG.cpp updated: 1.319 -> 1.320
SelectionDAG.cpp updated: 1.273 -> 1.274
SelectionDAGISel.cpp updated: 1.195 -> 1.196
---
Log message:

Rename ConstantVec -> BUILD_VECTOR and VConstant -> VBUILD_VECTOR.  Allow*BUILD_VECTOR to take variable inputs.


---
Diffs of the changes:  (+71 -57)

 LegalizeDAG.cpp      |  115 ++++++++++++++++++++++++++++-----------------------
 SelectionDAG.cpp     |    5 --
 SelectionDAGISel.cpp |    8 +--
 3 files changed, 71 insertions(+), 57 deletions(-)


Index: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.319 llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.320
--- llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.319	Sat Mar 18 18:20:20 2006
+++ llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp	Sat Mar 18 18:52:58 2006
@@ -452,7 +452,6 @@
   case ISD::TargetFrameIndex:
   case ISD::TargetConstant:
   case ISD::TargetConstantFP:
-  case ISD::TargetConstantVec:
   case ISD::TargetConstantPool:
   case ISD::TargetGlobalAddress:
   case ISD::TargetExternalSymbol:
@@ -709,47 +708,6 @@
     }
     break;
   }
-  case ISD::ConstantVec:
-    switch (TLI.getOperationAction(ISD::ConstantVec, Node->getValueType(0))) {
-    default: assert(0 && "This action is not supported yet!");
-    case TargetLowering::Custom:
-      Tmp3 = TLI.LowerOperation(Result, DAG);
-      if (Tmp3.Val) {
-        Result = Tmp3;
-        break;
-      }
-      // FALLTHROUGH
-    case TargetLowering::Expand:
-      // We assume that vector constants are not legal, and will be immediately
-      // spilled to the constant pool.
-      //
-      // Create a ConstantPacked, and put it in the constant pool.
-      MVT::ValueType VT = Node->getValueType(0);
-      const Type *OpNTy = 
-        MVT::getTypeForValueType(Node->getOperand(0).getValueType());
-      std::vector CV;
-      if (MVT::isFloatingPoint(VT)) {
-        for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) {
-          double V = 0;
-          if (Node->getOperand(i).getOpcode() != ISD::UNDEF)
-            V = cast(Node->getOperand(i))->getValue();
-          CV.push_back(ConstantFP::get(OpNTy, V));
-        }
-      } else {
-        for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) {
-          uint64_t V = 0;
-          if (Node->getOperand(i).getOpcode() != ISD::UNDEF)
-            V = cast(Node->getOperand(i))->getValue();
-          CV.push_back(ConstantUInt::get(OpNTy, V));
-        }
-      }
-      Constant *CP = ConstantPacked::get(CV);
-      SDOperand CPIdx = DAG.getConstantPool(CP, TLI.getPointerTy());
-      Result = DAG.getLoad(VT, DAG.getEntryNode(), CPIdx,
-                           DAG.getSrcValue(NULL));
-      break;
-    }
-    break;
   case ISD::TokenFactor:
     if (Node->getNumOperands() == 2) {
       Tmp1 = LegalizeOp(Node->getOperand(0));
@@ -769,6 +727,64 @@
     }
     break;
 
+  case ISD::BUILD_VECTOR:
+    switch (TLI.getOperationAction(ISD::BUILD_VECTOR, Node->getValueType(0))) {
+      default: assert(0 && "This action is not supported yet!");
+      case TargetLowering::Custom:
+        Tmp3 = TLI.LowerOperation(Result, DAG);
+        if (Tmp3.Val) {
+          Result = Tmp3;
+          break;
+        }
+          // FALLTHROUGH
+        case TargetLowering::Expand: {
+          // We assume that built vectors are not legal, and will be immediately
+          // spilled to memory.  If the values are all constants, turn this into a
+          // load from the constant pool.
+          bool isConstant = true;
+          for (SDNode::op_iterator I = Node->op_begin(), E = Node->op_end();
+               I != E; ++I) {
+            if (!isa(I) && !isa(I) &&
+                I->getOpcode() != ISD::UNDEF) {
+              isConstant = false;
+              break;
+            }
+          }
+          
+          // Create a ConstantPacked, and put it in the constant pool.
+          if (isConstant) {
+            MVT::ValueType VT = Node->getValueType(0);
+            const Type *OpNTy = 
+              MVT::getTypeForValueType(Node->getOperand(0).getValueType());
+            std::vector CV;
+            for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) {
+              if (ConstantFPSDNode *V = 
+                    dyn_cast(Node->getOperand(i))) {
+                CV.push_back(ConstantFP::get(OpNTy, V->getValue()));
+              } else if (ConstantSDNode *V = 
+                             dyn_cast(Node->getOperand(i))) {
+                CV.push_back(ConstantUInt::get(OpNTy, V->getValue()));
+              } else {
+                assert(Node->getOperand(i).getOpcode() == ISD::UNDEF);
+                CV.push_back(UndefValue::get(OpNTy));
+              }
+            }
+            Constant *CP = ConstantPacked::get(CV);
+            SDOperand CPIdx = DAG.getConstantPool(CP, TLI.getPointerTy());
+            Result = DAG.getLoad(VT, DAG.getEntryNode(), CPIdx,
+                                 DAG.getSrcValue(NULL));
+            break;
+          }
+          
+          // Otherwise, this isn't a constant entry.  Allocate a sufficiently
+          // aligned object on the stack, store each element into it, then load
+          // the result as a vector.
+          assert(0 && "Cannot lower variable BUILD_VECTOR yet!");
+          abort();
+          break;
+        }
+      }
+      break;
   case ISD::CALLSEQ_START: {
     SDNode *CallEnd = FindCallEndFromCallStart(Node);
     
@@ -4011,16 +4027,16 @@
   
   switch (Node->getOpcode()) {
   default: assert(0 && "Unknown vector operation!");
-  case ISD::VConstant: {
+  case ISD::VBUILD_VECTOR: {
     std::vector LoOps(Node->op_begin(), Node->op_begin()+NewNumElts);
     LoOps.push_back(NewNumEltsNode);
     LoOps.push_back(TypeNode);
-    Lo = DAG.getNode(ISD::VConstant, MVT::Vector, LoOps);
+    Lo = DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector, LoOps);
 
     std::vector HiOps(Node->op_begin()+NewNumElts, Node->op_end()-2);
     HiOps.push_back(NewNumEltsNode);
     HiOps.push_back(TypeNode);
-    Hi = DAG.getNode(ISD::VConstant, MVT::Vector, HiOps);
+    Hi = DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector, HiOps);
     break;
   }
   case ISD::VADD:
@@ -4112,15 +4128,14 @@
     AddLegalizedOperand(Op.getValue(1), LegalizeOp(Result.getValue(1)));
     break;
   }
-  case ISD::VConstant:
+  case ISD::VBUILD_VECTOR:
     if (!MVT::isVector(NewVT)) {
+      // Returning a scalar?
       Result = Node->getOperand(0);
     } else {
-      // If type of bisected vector is legal, turn it into a ConstantVec (which
-      // will be lowered to a ConstantPool or something else). Otherwise, bisect
-      // the VConstant, and return each half as a new VConstant.
+      // Returning a BUILD_VECTOR?
       std::vector Ops(Node->op_begin(), Node->op_end()-2);
-      Result = DAG.getNode(ISD::ConstantVec, NewVT, Ops);
+      Result = DAG.getNode(ISD::BUILD_VECTOR, NewVT, Ops);
     }
     break;
   }


Index: llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp:1.273 llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp:1.274
--- llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp:1.273	Fri Mar 17 19:44:44 2006
+++ llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp	Sat Mar 18 18:52:58 2006
@@ -2598,15 +2598,14 @@
   case ISD::ConstantPool:  return "ConstantPool";
   case ISD::ExternalSymbol: return "ExternalSymbol";
 
-  case ISD::ConstantVec:   return "ConstantVec";
+  case ISD::BUILD_VECTOR:   return "BUILD_VECTOR";
   case ISD::TargetConstant: return "TargetConstant";
   case ISD::TargetConstantFP:return "TargetConstantFP";
-  case ISD::TargetConstantVec:return "TargetConstantVec";
   case ISD::TargetGlobalAddress: return "TargetGlobalAddress";
   case ISD::TargetFrameIndex: return "TargetFrameIndex";
   case ISD::TargetConstantPool:  return "TargetConstantPool";
   case ISD::TargetExternalSymbol: return "TargetExternalSymbol";
-  case ISD::VConstant:     return "VConstant";
+  case ISD::VBUILD_VECTOR: return "VBUILD_VECTOR";
 
   case ISD::CopyToReg:     return "CopyToReg";
   case ISD::CopyFromReg:   return "CopyFromReg";


Index: llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.195 llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.196
--- llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.195	Sat Mar 18 18:20:20 2006
+++ llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp	Sat Mar 18 18:52:58 2006
@@ -519,7 +519,7 @@
       if (!isa(VTy))
         return N = DAG.getNode(ISD::UNDEF, VT);
 
-      // Create a VConstant of undef nodes.
+      // Create a VBUILD_VECTOR of undef nodes.
       const PackedType *PTy = cast(VTy);
       unsigned NumElements = PTy->getNumElements();
       MVT::ValueType PVT = TLI.getValueType(PTy->getElementType());
@@ -530,7 +530,7 @@
       // Create a VConstant node with generic Vector type.
       Ops.push_back(DAG.getConstant(NumElements, MVT::i32));
       Ops.push_back(DAG.getValueType(PVT));
-      return N = DAG.getNode(ISD::VConstant, MVT::Vector, Ops);
+      return N = DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector, Ops);
     } else if (ConstantFP *CFP = dyn_cast(C)) {
       return N = DAG.getConstantFP(CFP->getValue(), VT);
     } else if (const PackedType *PTy = dyn_cast(VTy)) {
@@ -564,10 +564,10 @@
         Ops.assign(NumElements, Op);
       }
       
-      // Create a VConstant node with generic Vector type.
+      // Create a VBUILD_VECTOR node with generic Vector type.
       Ops.push_back(DAG.getConstant(NumElements, MVT::i32));
       Ops.push_back(DAG.getValueType(PVT));
-      return N = DAG.getNode(ISD::VConstant, MVT::Vector, Ops);
+      return N = DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector, Ops);
     } else {
       // Canonicalize all constant ints to be unsigned.
       return N = DAG.getConstant(cast(C)->getRawValue(),VT);





From lattner at cs.uiuc.edu  Sat Mar 18 19:13:41 2006
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Sat, 18 Mar 2006 19:13:41 -0600
Subject: [llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCISelLowering.cpp 
Message-ID: <200603190113.TAA25194@zion.cs.uiuc.edu>



Changes in directory llvm/lib/Target/PowerPC:

PPCISelLowering.cpp updated: 1.97 -> 1.98
---
Log message:

rename these nodes


---
Diffs of the changes:  (+3 -3)

 PPCISelLowering.cpp |    6 +++---
 1 files changed, 3 insertions(+), 3 deletions(-)


Index: llvm/lib/Target/PowerPC/PPCISelLowering.cpp
diff -u llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.97 llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.98
--- llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.97	Thu Mar 16 19:40:33 2006
+++ llvm/lib/Target/PowerPC/PPCISelLowering.cpp	Sat Mar 18 19:13:28 2006
@@ -179,10 +179,10 @@
     setOperationAction(ISD::LOAD       , MVT::v4f32, Legal);
     setOperationAction(ISD::ADD        , MVT::v4i32, Legal);
     setOperationAction(ISD::LOAD       , MVT::v4i32, Legal);
-    // FIXME: We don't support any ConstantVec's yet.  We should custom expand
+    // FIXME: We don't support any BUILD_VECTOR's yet.  We should custom expand
     // the ones we do!
-    setOperationAction(ISD::ConstantVec, MVT::v4f32, Expand);
-    setOperationAction(ISD::ConstantVec, MVT::v4i32, Expand);
+    setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Expand);
+    setOperationAction(ISD::BUILD_VECTOR, MVT::v4i32, Expand);
   }
   
   setSetCCResultContents(ZeroOrOneSetCCResult);





From lattner at cs.uiuc.edu  Sat Mar 18 19:13:41 2006
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Sat, 18 Mar 2006 19:13:41 -0600
Subject: [llvm-commits] CVS: llvm/lib/Target/X86/X86ISelLowering.cpp 
Message-ID: <200603190113.TAA25198@zion.cs.uiuc.edu>



Changes in directory llvm/lib/Target/X86:

X86ISelLowering.cpp updated: 1.111 -> 1.112
---
Log message:

rename these nodes


---
Diffs of the changes:  (+9 -9)

 X86ISelLowering.cpp |   18 +++++++++---------
 1 files changed, 9 insertions(+), 9 deletions(-)


Index: llvm/lib/Target/X86/X86ISelLowering.cpp
diff -u llvm/lib/Target/X86/X86ISelLowering.cpp:1.111 llvm/lib/Target/X86/X86ISelLowering.cpp:1.112
--- llvm/lib/Target/X86/X86ISelLowering.cpp:1.111	Fri Mar 17 14:31:41 2006
+++ llvm/lib/Target/X86/X86ISelLowering.cpp	Sat Mar 18 19:13:28 2006
@@ -263,9 +263,9 @@
     addRegisterClass(MVT::v2i32, X86::VR64RegisterClass);
 
     // FIXME: add MMX packed arithmetics
-    setOperationAction(ISD::ConstantVec, MVT::v8i8,  Expand);
-    setOperationAction(ISD::ConstantVec, MVT::v4i16, Expand);
-    setOperationAction(ISD::ConstantVec, MVT::v2i32, Expand);
+    setOperationAction(ISD::BUILD_VECTOR, MVT::v8i8,  Expand);
+    setOperationAction(ISD::BUILD_VECTOR, MVT::v4i16, Expand);
+    setOperationAction(ISD::BUILD_VECTOR, MVT::v2i32, Expand);
   }
 
   if (TM.getSubtarget().hasSSE1()) {
@@ -275,7 +275,7 @@
     setOperationAction(ISD::SUB        , MVT::v4f32, Legal);
     setOperationAction(ISD::MUL        , MVT::v4f32, Legal);
     setOperationAction(ISD::LOAD       , MVT::v4f32, Legal);
-    setOperationAction(ISD::ConstantVec, MVT::v4f32, Expand);
+    setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Expand);
   }
 
   if (TM.getSubtarget().hasSSE2()) {
@@ -290,11 +290,11 @@
     setOperationAction(ISD::SUB        , MVT::v2f64, Legal);
     setOperationAction(ISD::MUL        , MVT::v2f64, Legal);
     setOperationAction(ISD::LOAD       , MVT::v2f64, Legal);
-    setOperationAction(ISD::ConstantVec, MVT::v2f64, Expand);
-    setOperationAction(ISD::ConstantVec, MVT::v16i8, Expand);
-    setOperationAction(ISD::ConstantVec, MVT::v8i16, Expand);
-    setOperationAction(ISD::ConstantVec, MVT::v4i32, Expand);
-    setOperationAction(ISD::ConstantVec, MVT::v2i64, Expand);
+    setOperationAction(ISD::BUILD_VECTOR, MVT::v2f64, Expand);
+    setOperationAction(ISD::BUILD_VECTOR, MVT::v16i8, Expand);
+    setOperationAction(ISD::BUILD_VECTOR, MVT::v8i16, Expand);
+    setOperationAction(ISD::BUILD_VECTOR, MVT::v4i32, Expand);
+    setOperationAction(ISD::BUILD_VECTOR, MVT::v2i64, Expand);
   }
 
   computeRegisterProperties();





From lattner at cs.uiuc.edu  Sat Mar 18 19:17:32 2006
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Sat, 18 Mar 2006 19:17:32 -0600
Subject: [llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
	SelectionDAGISel.cpp 
Message-ID: <200603190117.TAA25268@zion.cs.uiuc.edu>



Changes in directory llvm/lib/CodeGen/SelectionDAG:

LegalizeDAG.cpp updated: 1.320 -> 1.321
SelectionDAGISel.cpp updated: 1.196 -> 1.197
---
Log message:

implement basic support for INSERT_VECTOR_ELT.


---
Diffs of the changes:  (+97 -73)

 LegalizeDAG.cpp      |  144 ++++++++++++++++++++++++++++++++-------------------
 SelectionDAGISel.cpp |   26 +--------
 2 files changed, 97 insertions(+), 73 deletions(-)


Index: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.320 llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.321
--- llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.320	Sat Mar 18 18:52:58 2006
+++ llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp	Sat Mar 18 19:17:20 2006
@@ -729,62 +729,92 @@
 
   case ISD::BUILD_VECTOR:
     switch (TLI.getOperationAction(ISD::BUILD_VECTOR, Node->getValueType(0))) {
-      default: assert(0 && "This action is not supported yet!");
-      case TargetLowering::Custom:
-        Tmp3 = TLI.LowerOperation(Result, DAG);
-        if (Tmp3.Val) {
-          Result = Tmp3;
+    default: assert(0 && "This action is not supported yet!");
+    case TargetLowering::Custom:
+      Tmp3 = TLI.LowerOperation(Result, DAG);
+      if (Tmp3.Val) {
+        Result = Tmp3;
+        break;
+      }
+      // FALLTHROUGH
+    case TargetLowering::Expand: {
+      // We assume that built vectors are not legal, and will be immediately
+      // spilled to memory.  If the values are all constants, turn this into a
+      // load from the constant pool.
+      bool isConstant = true;
+      for (SDNode::op_iterator I = Node->op_begin(), E = Node->op_end();
+           I != E; ++I) {
+        if (!isa(I) && !isa(I) &&
+            I->getOpcode() != ISD::UNDEF) {
+          isConstant = false;
           break;
         }
-          // FALLTHROUGH
-        case TargetLowering::Expand: {
-          // We assume that built vectors are not legal, and will be immediately
-          // spilled to memory.  If the values are all constants, turn this into a
-          // load from the constant pool.
-          bool isConstant = true;
-          for (SDNode::op_iterator I = Node->op_begin(), E = Node->op_end();
-               I != E; ++I) {
-            if (!isa(I) && !isa(I) &&
-                I->getOpcode() != ISD::UNDEF) {
-              isConstant = false;
-              break;
-            }
-          }
-          
-          // Create a ConstantPacked, and put it in the constant pool.
-          if (isConstant) {
-            MVT::ValueType VT = Node->getValueType(0);
-            const Type *OpNTy = 
-              MVT::getTypeForValueType(Node->getOperand(0).getValueType());
-            std::vector CV;
-            for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) {
-              if (ConstantFPSDNode *V = 
-                    dyn_cast(Node->getOperand(i))) {
-                CV.push_back(ConstantFP::get(OpNTy, V->getValue()));
-              } else if (ConstantSDNode *V = 
-                             dyn_cast(Node->getOperand(i))) {
-                CV.push_back(ConstantUInt::get(OpNTy, V->getValue()));
-              } else {
-                assert(Node->getOperand(i).getOpcode() == ISD::UNDEF);
-                CV.push_back(UndefValue::get(OpNTy));
-              }
-            }
-            Constant *CP = ConstantPacked::get(CV);
-            SDOperand CPIdx = DAG.getConstantPool(CP, TLI.getPointerTy());
-            Result = DAG.getLoad(VT, DAG.getEntryNode(), CPIdx,
-                                 DAG.getSrcValue(NULL));
-            break;
+      }
+      
+      // Create a ConstantPacked, and put it in the constant pool.
+      if (isConstant) {
+        MVT::ValueType VT = Node->getValueType(0);
+        const Type *OpNTy = 
+          MVT::getTypeForValueType(Node->getOperand(0).getValueType());
+        std::vector CV;
+        for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) {
+          if (ConstantFPSDNode *V = 
+                dyn_cast(Node->getOperand(i))) {
+            CV.push_back(ConstantFP::get(OpNTy, V->getValue()));
+          } else if (ConstantSDNode *V = 
+                         dyn_cast(Node->getOperand(i))) {
+            CV.push_back(ConstantUInt::get(OpNTy, V->getValue()));
+          } else {
+            assert(Node->getOperand(i).getOpcode() == ISD::UNDEF);
+            CV.push_back(UndefValue::get(OpNTy));
           }
-          
-          // Otherwise, this isn't a constant entry.  Allocate a sufficiently
-          // aligned object on the stack, store each element into it, then load
-          // the result as a vector.
-          assert(0 && "Cannot lower variable BUILD_VECTOR yet!");
-          abort();
-          break;
         }
+        Constant *CP = ConstantPacked::get(CV);
+        SDOperand CPIdx = DAG.getConstantPool(CP, TLI.getPointerTy());
+        Result = DAG.getLoad(VT, DAG.getEntryNode(), CPIdx,
+                             DAG.getSrcValue(NULL));
+        break;
+      }
+      
+      // Otherwise, this isn't a constant entry.  Allocate a sufficiently
+      // aligned object on the stack, store each element into it, then load
+      // the result as a vector.
+      assert(0 && "Cannot lower variable BUILD_VECTOR yet!");
+      abort();
+      break;
+    }
+    }
+    break;
+  case ISD::INSERT_VECTOR_ELT:
+    Tmp1 = LegalizeOp(Node->getOperand(0));  // InVec
+    Tmp2 = LegalizeOp(Node->getOperand(1));  // InVal
+    Tmp3 = LegalizeOp(Node->getOperand(2));  // InEltNo
+    Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
+    
+    switch (TLI.getOperationAction(ISD::INSERT_VECTOR_ELT,
+                                   Node->getValueType(0))) {
+    default: assert(0 && "This action is not supported yet!");
+    case TargetLowering::Legal:
+      break;
+    case TargetLowering::Custom:
+      Tmp3 = TLI.LowerOperation(Result, DAG);
+      if (Tmp3.Val) {
+        Result = Tmp3;
+        break;
       }
+      // FALLTHROUGH
+    case TargetLowering::Expand: {
+      // If the target doesn't support this, we have to spill the input vector
+      // to a temporary stack slot, update the element, then reload it.  This is
+      // badness.  We could also load the value into a vector register (either
+      // with a "move to register" or "extload into register" instruction, then
+      // permute it into place, if the idx is a constant and if the idx is
+      // supported by the target.
+      assert(0 && "INSERT_VECTOR_ELT expand not supported yet!");
       break;
+    }
+    }
+    break;
   case ISD::CALLSEQ_START: {
     SDNode *CallEnd = FindCallEndFromCallStart(Node);
     
@@ -4104,7 +4134,9 @@
   
   SDOperand Result;
   switch (Node->getOpcode()) {
-  default: assert(0 && "Unknown vector operation!");
+  default: 
+    Node->dump(); std::cerr << "\n";
+    assert(0 && "Unknown vector operation in PackVectorOp!");
   case ISD::VADD:
   case ISD::VSUB:
   case ISD::VMUL:
@@ -4138,6 +4170,16 @@
       Result = DAG.getNode(ISD::BUILD_VECTOR, NewVT, Ops);
     }
     break;
+  case ISD::VINSERT_VECTOR_ELT:
+    if (!MVT::isVector(NewVT)) {
+      // Returning a scalar?  Must be the inserted element.
+      Result = Node->getOperand(1);
+    } else {
+      Result = DAG.getNode(ISD::INSERT_VECTOR_ELT, NewVT,
+                           PackVectorOp(Node->getOperand(0), NewVT),
+                           Node->getOperand(1), Node->getOperand(2));
+    }
+    break;
   }
 
   if (TLI.isTypeLegal(NewVT))


Index: llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.196 llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.197
--- llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.196	Sat Mar 18 18:52:58 2006
+++ llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp	Sat Mar 18 19:17:20 2006
@@ -842,33 +842,15 @@
 }
 
 void SelectionDAGLowering::visitInsertElement(InsertElementInst &I) {
-  const PackedType *Ty = cast(I.getType());
-  unsigned NumElements = Ty->getNumElements();
-  MVT::ValueType PVT = TLI.getValueType(Ty->getElementType());
-  MVT::ValueType TVT = MVT::getVectorType(PVT, NumElements);
-
   SDOperand InVec = getValue(I.getOperand(0));
   SDOperand InVal = getValue(I.getOperand(1));
   SDOperand InIdx = DAG.getNode(ISD::ZERO_EXTEND, TLI.getPointerTy(),
                                 getValue(I.getOperand(2)));
 
-  // Immediately scalarize packed types containing only one element, so that
-  // the Legalize pass does not have to deal with them.  Similarly, if the
-  // abstract vector is going to turn into one that the target natively
-  // supports, generate that type now so that Legalize doesn't have to deal
-  // with that either.  These steps ensure that Legalize only has to handle
-  // vector types in its Expand case.
-  if (NumElements == 1) {
-    setValue(&I, InVal);   // Must be insertelt(Vec, InVal, 0) -> InVal
-  } else if (TVT != MVT::Other && TLI.isTypeLegal(TVT) && 
-             TLI.isOperationLegal(ISD::INSERT_VECTOR_ELT, TVT)) {
-    setValue(&I, DAG.getNode(ISD::INSERT_VECTOR_ELT, TVT, InVec, InVal, InIdx));
-  } else {
-    SDOperand Num = DAG.getConstant(NumElements, MVT::i32);
-    SDOperand Typ = DAG.getValueType(PVT);
-    setValue(&I, DAG.getNode(ISD::VINSERT_VECTOR_ELT, MVT::Vector,
-                             InVec, InVal, InIdx, Num, Typ));
-  }
+  SDOperand Num = *(InVec.Val->op_end()-2);
+  SDOperand Typ = *(InVec.Val->op_end()-1);
+  setValue(&I, DAG.getNode(ISD::VINSERT_VECTOR_ELT, MVT::Vector,
+                           InVec, InVal, InIdx, Num, Typ));
 }
 
 





From lattner at cs.uiuc.edu  Sat Mar 18 19:27:15 2006
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Sat, 18 Mar 2006 19:27:15 -0600
Subject: [llvm-commits] CVS: llvm/test/Regression/CodeGen/Generic/vector.ll 
Message-ID: <200603190127.TAA25381@zion.cs.uiuc.edu>



Changes in directory llvm/test/Regression/CodeGen/Generic:

vector.ll updated: 1.2 -> 1.3
---
Log message:

add two new insert_element tests


---
Diffs of the changes:  (+12 -0)

 vector.ll |   12 ++++++++++++
 1 files changed, 12 insertions(+)


Index: llvm/test/Regression/CodeGen/Generic/vector.ll
diff -u llvm/test/Regression/CodeGen/Generic/vector.ll:1.2 llvm/test/Regression/CodeGen/Generic/vector.ll:1.3
--- llvm/test/Regression/CodeGen/Generic/vector.ll:1.2	Sat Mar 18 18:20:03 2006
+++ llvm/test/Regression/CodeGen/Generic/vector.ll	Sat Mar 18 19:27:04 2006
@@ -64,3 +64,15 @@
   store %f4 %R, %f4 *%S
   ret void
 }
+
+void %test_constant_insert(%f4 *%S) {
+  %R = insertelement %f4 zeroinitializer, float 10.0, uint 0
+  store %f4 %R, %f4 *%S
+  ret void
+}
+
+void %test_variable_buildvector(float %F, %f4 *%S) {
+  %R = insertelement %f4 zeroinitializer, float %F, uint 0
+  store %f4 %R, %f4 *%S
+  ret void
+}





From lattner at cs.uiuc.edu  Sat Mar 18 19:28:09 2006
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Sat, 18 Mar 2006 19:28:09 -0600
Subject: [llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp 
Message-ID: <200603190128.TAA25420@zion.cs.uiuc.edu>



Changes in directory llvm/lib/CodeGen/SelectionDAG:

DAGCombiner.cpp updated: 1.127 -> 1.128
---
Log message:

fold insertelement(buildvector) -> buildvector if the inserted element # is
a constant.  This implements test_constant_insert in CodeGen/Generic/vector.ll



---
Diffs of the changes:  (+42 -0)

 DAGCombiner.cpp |   42 ++++++++++++++++++++++++++++++++++++++++++
 1 files changed, 42 insertions(+)


Index: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.127 llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.128
--- llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.127	Thu Mar 16 19:40:33 2006
+++ llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp	Sat Mar 18 19:27:56 2006
@@ -209,6 +209,8 @@
     SDOperand visitBR_CC(SDNode *N);
     SDOperand visitLOAD(SDNode *N);
     SDOperand visitSTORE(SDNode *N);
+    SDOperand visitINSERT_VECTOR_ELT(SDNode *N);
+    SDOperand visitVINSERT_VECTOR_ELT(SDNode *N);
 
     SDOperand ReassociateOps(unsigned Opc, SDOperand LHS, SDOperand RHS);
     
@@ -640,6 +642,8 @@
   case ISD::BR_CC:              return visitBR_CC(N);
   case ISD::LOAD:               return visitLOAD(N);
   case ISD::STORE:              return visitSTORE(N);
+  case ISD::INSERT_VECTOR_ELT:  return visitINSERT_VECTOR_ELT(N);
+  case ISD::VINSERT_VECTOR_ELT: return visitVINSERT_VECTOR_ELT(N);
   }
   return SDOperand();
 }
@@ -2290,6 +2294,44 @@
   return SDOperand();
 }
 
+SDOperand DAGCombiner::visitINSERT_VECTOR_ELT(SDNode *N) {
+  SDOperand InVec = N->getOperand(0);
+  SDOperand InVal = N->getOperand(1);
+  SDOperand EltNo = N->getOperand(2);
+  
+  // If the invec is a BUILD_VECTOR and if EltNo is a constant, build a new
+  // vector with the inserted element.
+  if (InVec.getOpcode() == ISD::BUILD_VECTOR && isa(EltNo)) {
+    unsigned Elt = cast(EltNo)->getValue();
+    std::vector Ops(InVec.Val->op_begin(), InVec.Val->op_end());
+    if (Elt < Ops.size())
+      Ops[Elt] = InVal;
+    return DAG.getNode(ISD::BUILD_VECTOR, InVec.getValueType(), Ops);
+  }
+  
+  return SDOperand();
+}
+
+SDOperand DAGCombiner::visitVINSERT_VECTOR_ELT(SDNode *N) {
+  SDOperand InVec = N->getOperand(0);
+  SDOperand InVal = N->getOperand(1);
+  SDOperand EltNo = N->getOperand(2);
+  SDOperand NumElts = N->getOperand(3);
+  SDOperand EltType = N->getOperand(4);
+  
+  // If the invec is a VBUILD_VECTOR and if EltNo is a constant, build a new
+  // vector with the inserted element.
+  if (InVec.getOpcode() == ISD::VBUILD_VECTOR && isa(EltNo)) {
+    unsigned Elt = cast(EltNo)->getValue();
+    std::vector Ops(InVec.Val->op_begin(), InVec.Val->op_end());
+    if (Elt < Ops.size()-2)
+      Ops[Elt] = InVal;
+    return DAG.getNode(ISD::VBUILD_VECTOR, InVec.getValueType(), Ops);
+  }
+  
+  return SDOperand();
+}
+
 SDOperand DAGCombiner::SimplifySelect(SDOperand N0, SDOperand N1, SDOperand N2){
   assert(N0.getOpcode() ==ISD::SETCC && "First argument must be a SetCC node!");
   





From lattner at cs.uiuc.edu  Sat Mar 18 22:19:08 2006
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Sat, 18 Mar 2006 22:19:08 -0600
Subject: [llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp 
Message-ID: <200603190419.WAA26099@zion.cs.uiuc.edu>



Changes in directory llvm/lib/CodeGen/SelectionDAG:

LegalizeDAG.cpp updated: 1.321 -> 1.322
---
Log message:

Implement expand of BUILD_VECTOR containing variable elements.
This implements CodeGen/Generic/vector.ll:test_variable_buildvector


---
Diffs of the changes:  (+32 -2)

 LegalizeDAG.cpp |   34 ++++++++++++++++++++++++++++++++--
 1 files changed, 32 insertions(+), 2 deletions(-)


Index: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.321 llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.322
--- llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.321	Sat Mar 18 19:17:20 2006
+++ llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp	Sat Mar 18 22:18:56 2006
@@ -779,8 +779,38 @@
       // Otherwise, this isn't a constant entry.  Allocate a sufficiently
       // aligned object on the stack, store each element into it, then load
       // the result as a vector.
-      assert(0 && "Cannot lower variable BUILD_VECTOR yet!");
-      abort();
+      MVT::ValueType VT = Node->getValueType(0);
+      // Create the stack frame object.
+      MachineFrameInfo *FrameInfo = DAG.getMachineFunction().getFrameInfo();
+      unsigned ByteSize = MVT::getSizeInBits(VT)/8;
+      int FrameIdx = FrameInfo->CreateStackObject(ByteSize, ByteSize);
+      SDOperand FIPtr = DAG.getFrameIndex(FrameIdx, TLI.getPointerTy());
+      
+      // Emit a store of each element to the stack slot.
+      std::vector Stores;
+      bool isLittleEndian = TLI.isLittleEndian();
+      unsigned TypeByteSize = 
+        MVT::getSizeInBits(Node->getOperand(0).getValueType())/8;
+      unsigned VectorSize = MVT::getSizeInBits(VT)/8;
+      // Store (in the right endianness) the elements to memory.
+      for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) {
+        unsigned Offset;
+        if (isLittleEndian) 
+          Offset = TypeByteSize*i;
+        else
+          Offset = TypeByteSize*(e-i-1);
+
+        SDOperand Idx = DAG.getConstant(Offset, FIPtr.getValueType());
+        Idx = DAG.getNode(ISD::ADD, FIPtr.getValueType(), FIPtr, Idx);
+
+        Stores.push_back(DAG.getNode(ISD::STORE, MVT::Other, DAG.getEntryNode(),
+                                     Node->getOperand(i), Idx, 
+                                     DAG.getSrcValue(NULL)));
+      }
+      SDOperand StoreChain = DAG.getNode(ISD::TokenFactor, MVT::Other, Stores);
+      
+      // Result is a load from the stack slot.
+      Result = DAG.getLoad(VT, StoreChain, FIPtr, DAG.getSrcValue(0));
       break;
     }
     }





From lattner at cs.uiuc.edu  Sat Mar 18 22:33:49 2006
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Sat, 18 Mar 2006 22:33:49 -0600
Subject: [llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCInstrInfo.td 
Message-ID: <200603190433.WAA26328@zion.cs.uiuc.edu>



Changes in directory llvm/lib/Target/PowerPC:

PPCInstrInfo.td updated: 1.187 -> 1.188
---
Log message:

we don't use lmw/stmw.  When we want them they are easy enough to add


---
Diffs of the changes:  (+0 -6)

 PPCInstrInfo.td |    6 ------
 1 files changed, 6 deletions(-)


Index: llvm/lib/Target/PowerPC/PPCInstrInfo.td
diff -u llvm/lib/Target/PowerPC/PPCInstrInfo.td:1.187 llvm/lib/Target/PowerPC/PPCInstrInfo.td:1.188
--- llvm/lib/Target/PowerPC/PPCInstrInfo.td:1.187	Fri Mar 17 16:41:37 2006
+++ llvm/lib/Target/PowerPC/PPCInstrInfo.td	Sat Mar 18 22:33:37 2006
@@ -301,9 +301,6 @@
 def LHZ : DForm_1<40, (ops GPRC:$rD, memri:$src),
                   "lhz $rD, $src", LdStGeneral,
                   [(set GPRC:$rD, (zextload iaddr:$src, i16))]>;
-def LMW : DForm_1<46, (ops GPRC:$rD, s16imm:$disp, GPRC:$rA),
-                  "lmw $rD, $disp($rA)", LdStLMW,
-                  []>;
 def LWZ : DForm_1<32, (ops GPRC:$rD, memri:$src),
                   "lwz $rD, $src", LdStGeneral,
                   [(set GPRC:$rD, (load iaddr:$src))]>;
@@ -343,9 +340,6 @@
                      [(set GPRC:$rD, imm16Shifted:$imm)]>;
 }
 let isStore = 1, noResults = 1, PPC970_Unit = 2 in {
-def STMW : DForm_3<47, (ops GPRC:$rS, s16imm:$disp, GPRC:$rA),
-                   "stmw $rS, $disp($rA)", LdStLMW,
-                   []>;
 def STB  : DForm_3<38, (ops GPRC:$rS, memri:$src),
                    "stb $rS, $src", LdStGeneral,
                    [(truncstore GPRC:$rS, iaddr:$src, i8)]>;





From lattner at cs.uiuc.edu  Sat Mar 18 22:45:23 2006
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Sat, 18 Mar 2006 22:45:23 -0600
Subject: [llvm-commits] CVS: llvm/test/Regression/CodeGen/Generic/vector.ll 
Message-ID: <200603190445.WAA26487@zion.cs.uiuc.edu>



Changes in directory llvm/test/Regression/CodeGen/Generic:

vector.ll updated: 1.3 -> 1.4
---
Log message:

add another testcase, explicitly check stuff works with G5 and G3 codegen on
PPC.


---
Diffs of the changes:  (+17 -1)

 vector.ll |   18 +++++++++++++++++-
 1 files changed, 17 insertions(+), 1 deletion(-)


Index: llvm/test/Regression/CodeGen/Generic/vector.ll
diff -u llvm/test/Regression/CodeGen/Generic/vector.ll:1.3 llvm/test/Regression/CodeGen/Generic/vector.ll:1.4
--- llvm/test/Regression/CodeGen/Generic/vector.ll:1.3	Sat Mar 18 19:27:04 2006
+++ llvm/test/Regression/CodeGen/Generic/vector.ll	Sat Mar 18 22:45:11 2006
@@ -1,5 +1,7 @@
-; RUN: llvm-as < %s | llc
 ; Test that vectors are scalarized/lowered correctly.
+; RUN: llvm-as < %s | llc && 
+; RUN: llvm-as < %s | llc -march=ppc32 -mcpu=g5 &&
+; RUN: llvm-as < %s | llc -march=ppc32 -mcpu=g3
 
 %f1 = type <1 x float>
 %f2 = type <2 x float>
@@ -76,3 +78,17 @@
   store %f4 %R, %f4 *%S
   ret void
 }
+
+;;; TEST IMPORTANT IDIOMS
+
+void %splat(%f4* %P, %f4* %Q, float %X) {
+        %tmp = insertelement %f4 undef, float %X, uint 0
+        %tmp2 = insertelement %f4 %tmp, float %X, uint 1
+        %tmp4 = insertelement %f4 %tmp2, float %X, uint 2
+        %tmp6 = insertelement %f4 %tmp4, float %X, uint 3
+	%q = load %f4* %Q
+	%R = add %f4 %q, %tmp6
+        store %f4 %R, %f4* %P
+        ret void
+}
+





From lattner at cs.uiuc.edu  Sat Mar 18 23:26:57 2006
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Sat, 18 Mar 2006 23:26:57 -0600
Subject: [llvm-commits] CVS: llvm/include/llvm/CodeGen/SelectionDAGNodes.h
	ValueTypes.h 
Message-ID: <200603190526.XAA26682@zion.cs.uiuc.edu>



Changes in directory llvm/include/llvm/CodeGen:

SelectionDAGNodes.h updated: 1.114 -> 1.115
ValueTypes.h updated: 1.22 -> 1.23
---
Log message:

improve comments, add a new MVT::getVectorBaseType method.


---
Diffs of the changes:  (+71 -40)

 SelectionDAGNodes.h |   14 ++++---
 ValueTypes.h        |   97 +++++++++++++++++++++++++++++++++-------------------
 2 files changed, 71 insertions(+), 40 deletions(-)


Index: llvm/include/llvm/CodeGen/SelectionDAGNodes.h
diff -u llvm/include/llvm/CodeGen/SelectionDAGNodes.h:1.114 llvm/include/llvm/CodeGen/SelectionDAGNodes.h:1.115
--- llvm/include/llvm/CodeGen/SelectionDAGNodes.h:1.114	Sat Mar 18 18:52:25 2006
+++ llvm/include/llvm/CodeGen/SelectionDAGNodes.h	Sat Mar 18 23:26:45 2006
@@ -166,7 +166,12 @@
     /// their last two operands.
     VADD, VSUB, VMUL, VSDIV, VUDIV,
     VAND, VOR, VXOR,
-
+    
+    /// SCALAR_TO_VECTOR(VAL) - This represents the operation of loading a
+    /// scalar value into the low element of the resultant vector type.  The top
+    /// elements of the vector are undefined.
+    SCALAR_TO_VECTOR,
+    
     // MULHU/MULHS - Multiply high - Multiply two integers of type iN, producing
     // an unsigned/signed value of type i[2*n], then return the top part.
     MULHU, MULHS,
@@ -281,10 +286,9 @@
     //          integer result type.
     // ZEXTLOAD loads the integer operand and zero extends it to a larger
     //          integer result type.
-    // EXTLOAD  is used for two things: floating point extending loads, and
-    //          integer extending loads where it doesn't matter what the high
-    //          bits are set to.  The code generator is allowed to codegen this
-    //          into whichever operation is more efficient.
+    // EXTLOAD  is used for three things: floating point extending loads, 
+    //          integer extending loads [the top bits are undefined], and vector
+    //          extending loads [load into low elt].
     EXTLOAD, SEXTLOAD, ZEXTLOAD,
 
     // TRUNCSTORE - This operators truncates (for integer) or rounds (for FP) a


Index: llvm/include/llvm/CodeGen/ValueTypes.h
diff -u llvm/include/llvm/CodeGen/ValueTypes.h:1.22 llvm/include/llvm/CodeGen/ValueTypes.h:1.23
--- llvm/include/llvm/CodeGen/ValueTypes.h:1.22	Thu Mar 16 13:42:44 2006
+++ llvm/include/llvm/CodeGen/ValueTypes.h	Sat Mar 18 23:26:45 2006
@@ -66,20 +66,55 @@
     LAST_VALUETYPE =  24    // This always remains at the end of the list.
   };
 
+  /// MVT::isInteger - Return true if this is a simple integer, or a packed
+  /// vector integer type.
   static inline bool isInteger(ValueType VT) {
     return (VT >= i1 && VT <= i128) || (VT >= v8i8 && VT <= v2i64);
   }
+
+  /// MVT::isFloatingPoint - Return true if this is a simple FP, or a packed
+  /// vector FP type.
   static inline bool isFloatingPoint(ValueType VT) {
     return (VT >= f32 && VT <= f128) || (VT >= v4f32 && VT <= v2f64);
   }
+  
+  /// MVT::isVector - Return true if this is a packed vector type (i.e. not 
+  /// MVT::Vector).
   static inline bool isVector(ValueType VT) {
-    return (VT >= FIRST_VECTOR_VALUETYPE &&
-            VT <= LAST_VECTOR_VALUETYPE);
+    return VT >= FIRST_VECTOR_VALUETYPE && VT <= LAST_VECTOR_VALUETYPE;
   }
   
-  /// getVectorType - Returns the ValueType that represents a vector NumElements
-  /// in length, where each element is of type VT.  If there is no ValueType
-  /// that represents this vector, a ValueType of Other is returned.
+  /// MVT::getSizeInBits - Return the size of the specified value type in bits.
+  ///
+  static inline unsigned getSizeInBits(ValueType VT) {
+    switch (VT) {
+    default: assert(0 && "ValueType has no known size!");
+    case MVT::i1  :  return 1;
+    case MVT::i8  :  return 8;
+    case MVT::i16 :  return 16;
+    case MVT::f32 :
+    case MVT::i32 :  return 32;
+    case MVT::f64 :
+    case MVT::i64 :
+    case MVT::v8i8:
+    case MVT::v4i16:
+    case MVT::v2i32: 
+    case MVT::v2f32: return 64;
+    case MVT::f80 :  return 80;
+    case MVT::f128:
+    case MVT::i128: 
+    case MVT::v16i8:
+    case MVT::v8i16:
+    case MVT::v4i32:
+    case MVT::v2i64:
+    case MVT::v4f32:
+    case MVT::v2f64: return 128;
+    }
+  }
+  
+  /// MVT::getVectorType - Returns the ValueType that represents a vector
+  /// NumElements in length, where each element is of type VT.  If there is no
+  /// ValueType that represents this vector, a ValueType of Other is returned.
   ///
   static inline ValueType getVectorType(ValueType VT, unsigned NumElements) {
     switch (VT) {
@@ -88,19 +123,19 @@
     case MVT::i8:
       if (NumElements == 8)  return MVT::v8i8;
       if (NumElements == 16) return MVT::v16i8;
-      break;
+        break;
     case MVT::i16:
       if (NumElements == 4)  return MVT::v4i16;
       if (NumElements == 8)  return MVT::v8i16;
-      break;
+        break;
     case MVT::i32:
       if (NumElements == 2)  return MVT::v2i32;
       if (NumElements == 4)  return MVT::v4i32;
-      break;
+        break;
     case MVT::f32:
       if (NumElements == 2)  return MVT::v2f32;
       if (NumElements == 4)  return MVT::v4f32;
-      break;
+        break;
     case MVT::f64:
       if (NumElements == 2)  return MVT::v2f64;
       break;
@@ -108,40 +143,32 @@
     return MVT::Other;
   }
   
-  static inline unsigned getSizeInBits(ValueType VT) {
+  /// MVT::getVectorBaseType - Given a packed vector type, return the type of
+  /// each element.
+  static inline ValueType getVectorBaseType(ValueType VT) {
     switch (VT) {
-    default: assert(0 && "ValueType has no known size!");
-    case MVT::i1  :  return 1;
-    case MVT::i8  :  return 8;
-    case MVT::i16 :  return 16;
-    case MVT::f32 :
-    case MVT::i32 :  return 32;
-    case MVT::f64 :
-    case MVT::i64 :
-    case MVT::v8i8:
-    case MVT::v4i16:
-    case MVT::v2i32: 
-    case MVT::v2f32: return 64;
-    case MVT::f80 :  return 80;
-    case MVT::f128:
-    case MVT::i128: 
-    case MVT::v16i8:
-    case MVT::v8i16:
-    case MVT::v4i32:
-    case MVT::v2i64:
-    case MVT::v4f32:
-    case MVT::v2f64: return 128;
+    default: assert(0 && "Invalid vector type!");
+    case v8i8 :
+    case v16i8: return i8;
+    case v4i16:
+    case v8i16: return i16; 
+    case v2i32:
+    case v4i32: return i32;
+    case v2i64: return i64;
+    case v2f32:
+    case v4f32: return f32;
+    case v2f64: return f64;
     }
   }
   
-  /// getIntVTBitMask - Return an integer with 1's every place there are bits
-  /// in the specified integer value type.
+  /// MVT::getIntVTBitMask - Return an integer with 1's every place there are
+  /// bits in the specified integer value type.
   static inline uint64_t getIntVTBitMask(ValueType VT) {
     assert(isInteger(VT) && !isVector(VT) && "Only applies to int scalars!");
     return ~0ULL >> (64-getSizeInBits(VT));
   }
-  /// getIntVTSignBit - Return an integer with a 1 in the position of the sign
-  /// bit for the specified integer value type.
+  /// MVT::getIntVTSignBit - Return an integer with a 1 in the position of the
+  /// sign bit for the specified integer value type.
   static inline uint64_t getIntVTSignBit(ValueType VT) {
     assert(isInteger(VT) && !isVector(VT) && "Only applies to int scalars!");
     return 1ULL << (getSizeInBits(VT)-1);





From lattner at cs.uiuc.edu  Sat Mar 18 23:33:42 2006
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Sat, 18 Mar 2006 23:33:42 -0600
Subject: [llvm-commits] CVS: llvm/lib/Target/PowerPC/README.txt 
Message-ID: <200603190533.XAA26731@zion.cs.uiuc.edu>



Changes in directory llvm/lib/Target/PowerPC:

README.txt updated: 1.74 -> 1.75
---
Log message:

notes


---
Diffs of the changes:  (+16 -0)

 README.txt |   16 ++++++++++++++++
 1 files changed, 16 insertions(+)


Index: llvm/lib/Target/PowerPC/README.txt
diff -u llvm/lib/Target/PowerPC/README.txt:1.74 llvm/lib/Target/PowerPC/README.txt:1.75
--- llvm/lib/Target/PowerPC/README.txt:1.74	Thu Mar 16 19:40:33 2006
+++ llvm/lib/Target/PowerPC/README.txt	Sat Mar 18 23:33:30 2006
@@ -506,6 +506,7 @@
 registers, to generate better spill code.
 
 ===-------------------------------------------------------------------------===
+
 int foo(int N, int ***W, int **TK, int X) {
   int t, i;
   
@@ -518,5 +519,20 @@
 
 We generate relatively atrocious code for this loop compared to gcc.
 
+===-------------------------------------------------------------------------===
+
+Altivec support.  The first should be a single lvx from the constant pool, the
+second should be a xor/stvx:
 
+void foo(void) {
+  int x[8] __attribute__((aligned(128))) = { 1, 1, 1, 1, 1, 1, 1, 1 };
+  bar (x);
+}
+
+#include 
+void foo(void) {
+  int x[8] __attribute__((aligned(128)));
+  memset (x, 0, sizeof (x));
+  bar (x);
+}
 





From lattner at cs.uiuc.edu  Sat Mar 18 23:43:13 2006
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Sat, 18 Mar 2006 23:43:13 -0600
Subject: [llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCInstrInfo.td 
Message-ID: <200603190543.XAA26818@zion.cs.uiuc.edu>



Changes in directory llvm/lib/Target/PowerPC:

PPCInstrInfo.td updated: 1.188 -> 1.189
---
Log message:

minor fixes


---
Diffs of the changes:  (+2 -2)

 PPCInstrInfo.td |    4 ++--
 1 files changed, 2 insertions(+), 2 deletions(-)


Index: llvm/lib/Target/PowerPC/PPCInstrInfo.td
diff -u llvm/lib/Target/PowerPC/PPCInstrInfo.td:1.188 llvm/lib/Target/PowerPC/PPCInstrInfo.td:1.189
--- llvm/lib/Target/PowerPC/PPCInstrInfo.td:1.188	Sat Mar 18 22:33:37 2006
+++ llvm/lib/Target/PowerPC/PPCInstrInfo.td	Sat Mar 18 23:43:01 2006
@@ -216,9 +216,9 @@
 }
 def IMPLICIT_DEF_GPR : Pseudo<(ops GPRC:$rD), "; $rD = IMPLICIT_DEF_GPRC",
                               [(set GPRC:$rD, (undef))]>;
-def IMPLICIT_DEF_F8  : Pseudo<(ops F8RC:$rD), "; %rD = IMPLICIT_DEF_F8",
+def IMPLICIT_DEF_F8  : Pseudo<(ops F8RC:$rD), "; $rD = IMPLICIT_DEF_F8",
                               [(set F8RC:$rD, (undef))]>;
-def IMPLICIT_DEF_F4  : Pseudo<(ops F4RC:$rD), "; %rD = IMPLICIT_DEF_F4",
+def IMPLICIT_DEF_F4  : Pseudo<(ops F4RC:$rD), "; $rD = IMPLICIT_DEF_F4",
                               [(set F4RC:$rD, (undef))]>;
 
 // SELECT_CC_* - Used to implement the SELECT_CC DAG operation.  Expanded by the





From lattner at cs.uiuc.edu  Sat Mar 18 23:46:16 2006
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Sat, 18 Mar 2006 23:46:16 -0600
Subject: [llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp 
Message-ID: <200603190546.XAA26885@zion.cs.uiuc.edu>



Changes in directory llvm/lib/CodeGen/SelectionDAG:

LegalizeDAG.cpp updated: 1.322 -> 1.323
---
Log message:

Don't bother storing undef elements of BUILD_VECTOR's


---
Diffs of the changes:  (+9 -1)

 LegalizeDAG.cpp |   10 +++++++++-
 1 files changed, 9 insertions(+), 1 deletion(-)


Index: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.322 llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.323
--- llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.322	Sat Mar 18 22:18:56 2006
+++ llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp	Sat Mar 18 23:46:04 2006
@@ -794,6 +794,9 @@
       unsigned VectorSize = MVT::getSizeInBits(VT)/8;
       // Store (in the right endianness) the elements to memory.
       for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) {
+        // Ignore undef elements.
+        if (Node->getOperand(i).getOpcode() == ISD::UNDEF) continue;
+        
         unsigned Offset;
         if (isLittleEndian) 
           Offset = TypeByteSize*i;
@@ -807,7 +810,12 @@
                                      Node->getOperand(i), Idx, 
                                      DAG.getSrcValue(NULL)));
       }
-      SDOperand StoreChain = DAG.getNode(ISD::TokenFactor, MVT::Other, Stores);
+      
+      SDOperand StoreChain;
+      if (!Stores.empty())    // Not all undef elements?
+        StoreChain = DAG.getNode(ISD::TokenFactor, MVT::Other, Stores);
+      else
+        StoreChain = DAG.getEntryNode();
       
       // Result is a load from the stack slot.
       Result = DAG.getLoad(VT, StoreChain, FIPtr, DAG.getSrcValue(0));





From lattner at cs.uiuc.edu  Sat Mar 18 23:47:03 2006
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Sat, 18 Mar 2006 23:47:03 -0600
Subject: [llvm-commits] CVS: llvm/test/Regression/CodeGen/Generic/vector.ll 
Message-ID: <200603190547.XAA26940@zion.cs.uiuc.edu>



Changes in directory llvm/test/Regression/CodeGen/Generic:

vector.ll updated: 1.4 -> 1.5
---
Log message:

add a new testcase.  This insertelement should be a noop on SSE.


---
Diffs of the changes:  (+6 -0)

 vector.ll |    6 ++++++
 1 files changed, 6 insertions(+)


Index: llvm/test/Regression/CodeGen/Generic/vector.ll
diff -u llvm/test/Regression/CodeGen/Generic/vector.ll:1.4 llvm/test/Regression/CodeGen/Generic/vector.ll:1.5
--- llvm/test/Regression/CodeGen/Generic/vector.ll:1.4	Sat Mar 18 22:45:11 2006
+++ llvm/test/Regression/CodeGen/Generic/vector.ll	Sat Mar 18 23:46:51 2006
@@ -79,6 +79,12 @@
   ret void
 }
 
+void %test_scalar_to_vector(float %F, %f4 *%S) {
+  %R = insertelement %f4 undef, float %F, uint 0   ;; R = scalar_to_vector F
+  store %f4 %R, %f4 *%S
+  ret void
+}
+
 ;;; TEST IMPORTANT IDIOMS
 
 void %splat(%f4* %P, %f4* %Q, float %X) {





From evan.cheng at apple.com  Sun Mar 19 00:08:24 2006
From: evan.cheng at apple.com (Evan Cheng)
Date: Sun, 19 Mar 2006 00:08:24 -0600
Subject: [llvm-commits] CVS: llvm/lib/Target/X86/README.txt 
Message-ID: <200603190608.AAA27026@zion.cs.uiuc.edu>



Changes in directory llvm/lib/Target/X86:

README.txt updated: 1.66 -> 1.67
---
Log message:

Remember which tests are hurt by LSR.

---
Diffs of the changes:  (+4 -0)

 README.txt |    4 ++++
 1 files changed, 4 insertions(+)


Index: llvm/lib/Target/X86/README.txt
diff -u llvm/lib/Target/X86/README.txt:1.66 llvm/lib/Target/X86/README.txt:1.67
--- llvm/lib/Target/X86/README.txt:1.66	Thu Mar 16 16:44:22 2006
+++ llvm/lib/Target/X86/README.txt	Sun Mar 19 00:08:11 2006
@@ -629,3 +629,7 @@
 dependent LICM pass or 2) makeing SelectDAG represent the whole function. 
 
 //===---------------------------------------------------------------------===//
+
+The following tests perform worse with LSR:
+
+lambda, siod, optimizer-eval, ackermann, hash2, nestedloop, strcat, and Treesor.





From evan.cheng at apple.com  Sun Mar 19 00:09:01 2006
From: evan.cheng at apple.com (Evan Cheng)
Date: Sun, 19 Mar 2006 00:09:01 -0600
Subject: [llvm-commits] CVS: llvm/lib/Target/X86/X86TargetMachine.cpp 
Message-ID: <200603190609.AAA27043@zion.cs.uiuc.edu>



Changes in directory llvm/lib/Target/X86:

X86TargetMachine.cpp updated: 1.108 -> 1.109
---
Log message:

Turning on LSR by default

---
Diffs of the changes:  (+2 -6)

 X86TargetMachine.cpp |    8 ++------
 1 files changed, 2 insertions(+), 6 deletions(-)


Index: llvm/lib/Target/X86/X86TargetMachine.cpp
diff -u llvm/lib/Target/X86/X86TargetMachine.cpp:1.108 llvm/lib/Target/X86/X86TargetMachine.cpp:1.109
--- llvm/lib/Target/X86/X86TargetMachine.cpp:1.108	Thu Mar 16 15:47:42 2006
+++ llvm/lib/Target/X86/X86TargetMachine.cpp	Sun Mar 19 00:08:49 2006
@@ -38,9 +38,6 @@
                               cl::desc("Disable the X86 asm printer, for use "
                                        "when profiling the code generator."));
 
-  cl::opt EnableX86LSR("enable-x86-lsr", cl::Hidden,
-                              cl::desc("Enable the X86 loop strength reduction "
-                                       "pass."));
   // Register the target.
   RegisterTarget X("x86", "  IA-32 (Pentium and above)");
 }
@@ -97,7 +94,7 @@
       FileType != TargetMachine::ObjectFile) return true;
 
   // Run loop strength reduction before anything else.
-  if (EnableX86LSR) PM.add(createLoopStrengthReducePass(&TLInfo));
+  PM.add(createLoopStrengthReducePass(&TLInfo));
 
   // FIXME: Implement efficient support for garbage collection intrinsics.
   PM.add(createLowerGCPass());
@@ -165,8 +162,7 @@
   TM.setRelocationModel(Reloc::Static);
 
   // Run loop strength reduction before anything else.
-  if (EnableX86LSR)
-    PM.add(createLoopStrengthReducePass(TM.getTargetLowering()));
+  PM.add(createLoopStrengthReducePass(TM.getTargetLowering()));
 
   // FIXME: Implement efficient support for garbage collection intrinsics.
   PM.add(createLowerGCPass());





From evan.cheng at apple.com  Sun Mar 19 00:09:36 2006
From: evan.cheng at apple.com (Evan Cheng)
Date: Sun, 19 Mar 2006 00:09:36 -0600
Subject: [llvm-commits] CVS: llvm/lib/Target/README.txt 
Message-ID: <200603190609.AAA27058@zion.cs.uiuc.edu>



Changes in directory llvm/lib/Target:

README.txt updated: 1.22 -> 1.23
---
Log message:

Remind us of exit value substitution

---
Diffs of the changes:  (+3 -0)

 README.txt |    3 +++
 1 files changed, 3 insertions(+)


Index: llvm/lib/Target/README.txt
diff -u llvm/lib/Target/README.txt:1.22 llvm/lib/Target/README.txt:1.23
--- llvm/lib/Target/README.txt:1.22	Thu Mar 16 19:40:33 2006
+++ llvm/lib/Target/README.txt	Sun Mar 19 00:09:23 2006
@@ -125,3 +125,6 @@
 1. The instcombiner should eliminate the type conversions.
 2. The X86 backend should turn this into a rotate by one bit.
 
+//===---------------------------------------------------------------------===//
+
+Add LSR exit value substitution. It'll probably be a win for Ackermann, etc.





From lattner at cs.uiuc.edu  Sun Mar 19 00:10:21 2006
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Sun, 19 Mar 2006 00:10:21 -0600
Subject: [llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCInstrInfo.td 
Message-ID: <200603190610.AAA27123@zion.cs.uiuc.edu>



Changes in directory llvm/lib/Target/PowerPC:

PPCInstrInfo.td updated: 1.189 -> 1.190
---
Log message:

add support for vector undef


---
Diffs of the changes:  (+4 -0)

 PPCInstrInfo.td |    4 ++++
 1 files changed, 4 insertions(+)


Index: llvm/lib/Target/PowerPC/PPCInstrInfo.td
diff -u llvm/lib/Target/PowerPC/PPCInstrInfo.td:1.189 llvm/lib/Target/PowerPC/PPCInstrInfo.td:1.190
--- llvm/lib/Target/PowerPC/PPCInstrInfo.td:1.189	Sat Mar 18 23:43:01 2006
+++ llvm/lib/Target/PowerPC/PPCInstrInfo.td	Sun Mar 19 00:10:09 2006
@@ -220,6 +220,8 @@
                               [(set F8RC:$rD, (undef))]>;
 def IMPLICIT_DEF_F4  : Pseudo<(ops F4RC:$rD), "; $rD = IMPLICIT_DEF_F4",
                               [(set F4RC:$rD, (undef))]>;
+def IMPLICIT_DEF_VRRC : Pseudo<(ops VRRC:$rD), "; $rD = IMPLICIT_DEF_VRRC",
+                               [(set VRRC:$rD, (v4f32 (undef)))]>;
 
 // SELECT_CC_* - Used to implement the SELECT_CC DAG operation.  Expanded by the
 // scheduler into a branch sequence.
@@ -1148,6 +1150,8 @@
 def : Pat<(store (v4i32 VRRC:$rS), xoaddr:$dst),
           (STVX (v4i32 VRRC:$rS), xoaddr:$dst)>;
 
+def : Pat<(v4i32 (undef)), (v4i32 (IMPLICIT_DEF_VRRC))>;
+
 
 // Same as above, but using a temporary. FIXME: implement temporaries :)
 /*





From evan.cheng at apple.com  Sun Mar 19 00:11:21 2006
From: evan.cheng at apple.com (Evan Cheng)
Date: Sun, 19 Mar 2006 00:11:21 -0600
Subject: [llvm-commits] CVS: llvm-test/Makefile.programs 
Message-ID: <200603190611.AAA27138@zion.cs.uiuc.edu>



Changes in directory llvm-test:

Makefile.programs updated: 1.200 -> 1.201
---
Log message:

Switch x86 llc-beta back to -enable-x86-fastcc now that LSR is on by default

---
Diffs of the changes:  (+1 -1)

 Makefile.programs |    2 +-
 1 files changed, 1 insertion(+), 1 deletion(-)


Index: llvm-test/Makefile.programs
diff -u llvm-test/Makefile.programs:1.200 llvm-test/Makefile.programs:1.201
--- llvm-test/Makefile.programs:1.200	Thu Mar  9 20:18:30 2006
+++ llvm-test/Makefile.programs	Sun Mar 19 00:11:09 2006
@@ -197,7 +197,7 @@
 LLCBETAOPTION := -sched=simple 
 endif
 ifeq ($(ARCH),x86)
-LLCBETAOPTION := -enable-x86-lsr
+LLCBETAOPTION := -enable-x86-fastcc
 endif
 ifeq ($(ARCH),Sparc)
 LLCBETAOPTION := -enable-sparc-v9-insts





From lattner at cs.uiuc.edu  Sun Mar 19 00:17:31 2006
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Sun, 19 Mar 2006 00:17:31 -0600
Subject: [llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCISelLowering.cpp 
Message-ID: <200603190617.AAA27230@zion.cs.uiuc.edu>



Changes in directory llvm/lib/Target/PowerPC:

PPCISelLowering.cpp updated: 1.98 -> 1.99
---
Log message:

PPC doesn't have SCALAR_TO_VECTOR


---
Diffs of the changes:  (+3 -0)

 PPCISelLowering.cpp |    3 +++
 1 files changed, 3 insertions(+)


Index: llvm/lib/Target/PowerPC/PPCISelLowering.cpp
diff -u llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.98 llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.99
--- llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.98	Sat Mar 18 19:13:28 2006
+++ llvm/lib/Target/PowerPC/PPCISelLowering.cpp	Sun Mar 19 00:17:19 2006
@@ -183,6 +183,9 @@
     // the ones we do!
     setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Expand);
     setOperationAction(ISD::BUILD_VECTOR, MVT::v4i32, Expand);
+    
+    setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4f32, Expand);
+    setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i32, Expand);
   }
   
   setSetCCResultContents(ZeroOrOneSetCCResult);





From lattner at cs.uiuc.edu  Sun Mar 19 00:31:34 2006
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Sun, 19 Mar 2006 00:31:34 -0600
Subject: [llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
	SelectionDAG.cpp 
Message-ID: <200603190631.AAA27374@zion.cs.uiuc.edu>



Changes in directory llvm/lib/CodeGen/SelectionDAG:

LegalizeDAG.cpp updated: 1.323 -> 1.324
SelectionDAG.cpp updated: 1.274 -> 1.275
---
Log message:

Add SCALAR_TO_VECTOR support


---
Diffs of the changes:  (+154 -90)

 LegalizeDAG.cpp  |  227 +++++++++++++++++++++++++++++++++----------------------
 SelectionDAG.cpp |   17 +++-
 2 files changed, 154 insertions(+), 90 deletions(-)


Index: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.323 llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.324
--- llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.323	Sat Mar 18 23:46:04 2006
+++ llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp	Sun Mar 19 00:31:19 2006
@@ -160,12 +160,15 @@
 
   void LegalizeSetCCOperands(SDOperand &LHS, SDOperand &RHS, SDOperand &CC);
     
+  SDOperand CreateStackTemporary(MVT::ValueType VT);
+
   SDOperand ExpandLibCall(const char *Name, SDNode *Node,
                           SDOperand &Hi);
   SDOperand ExpandIntToFP(bool isSigned, MVT::ValueType DestTy,
                           SDOperand Source);
 
   SDOperand ExpandBIT_CONVERT(MVT::ValueType DestVT, SDOperand SrcOp);
+  SDOperand ExpandBUILD_VECTOR(SDNode *Node);
   SDOperand ExpandLegalINT_TO_FP(bool isSigned,
                                  SDOperand LegalOp,
                                  MVT::ValueType DestVT);
@@ -737,91 +740,10 @@
         break;
       }
       // FALLTHROUGH
-    case TargetLowering::Expand: {
-      // We assume that built vectors are not legal, and will be immediately
-      // spilled to memory.  If the values are all constants, turn this into a
-      // load from the constant pool.
-      bool isConstant = true;
-      for (SDNode::op_iterator I = Node->op_begin(), E = Node->op_end();
-           I != E; ++I) {
-        if (!isa(I) && !isa(I) &&
-            I->getOpcode() != ISD::UNDEF) {
-          isConstant = false;
-          break;
-        }
-      }
-      
-      // Create a ConstantPacked, and put it in the constant pool.
-      if (isConstant) {
-        MVT::ValueType VT = Node->getValueType(0);
-        const Type *OpNTy = 
-          MVT::getTypeForValueType(Node->getOperand(0).getValueType());
-        std::vector CV;
-        for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) {
-          if (ConstantFPSDNode *V = 
-                dyn_cast(Node->getOperand(i))) {
-            CV.push_back(ConstantFP::get(OpNTy, V->getValue()));
-          } else if (ConstantSDNode *V = 
-                         dyn_cast(Node->getOperand(i))) {
-            CV.push_back(ConstantUInt::get(OpNTy, V->getValue()));
-          } else {
-            assert(Node->getOperand(i).getOpcode() == ISD::UNDEF);
-            CV.push_back(UndefValue::get(OpNTy));
-          }
-        }
-        Constant *CP = ConstantPacked::get(CV);
-        SDOperand CPIdx = DAG.getConstantPool(CP, TLI.getPointerTy());
-        Result = DAG.getLoad(VT, DAG.getEntryNode(), CPIdx,
-                             DAG.getSrcValue(NULL));
-        break;
-      }
-      
-      // Otherwise, this isn't a constant entry.  Allocate a sufficiently
-      // aligned object on the stack, store each element into it, then load
-      // the result as a vector.
-      MVT::ValueType VT = Node->getValueType(0);
-      // Create the stack frame object.
-      MachineFrameInfo *FrameInfo = DAG.getMachineFunction().getFrameInfo();
-      unsigned ByteSize = MVT::getSizeInBits(VT)/8;
-      int FrameIdx = FrameInfo->CreateStackObject(ByteSize, ByteSize);
-      SDOperand FIPtr = DAG.getFrameIndex(FrameIdx, TLI.getPointerTy());
-      
-      // Emit a store of each element to the stack slot.
-      std::vector Stores;
-      bool isLittleEndian = TLI.isLittleEndian();
-      unsigned TypeByteSize = 
-        MVT::getSizeInBits(Node->getOperand(0).getValueType())/8;
-      unsigned VectorSize = MVT::getSizeInBits(VT)/8;
-      // Store (in the right endianness) the elements to memory.
-      for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) {
-        // Ignore undef elements.
-        if (Node->getOperand(i).getOpcode() == ISD::UNDEF) continue;
-        
-        unsigned Offset;
-        if (isLittleEndian) 
-          Offset = TypeByteSize*i;
-        else
-          Offset = TypeByteSize*(e-i-1);
-
-        SDOperand Idx = DAG.getConstant(Offset, FIPtr.getValueType());
-        Idx = DAG.getNode(ISD::ADD, FIPtr.getValueType(), FIPtr, Idx);
-
-        Stores.push_back(DAG.getNode(ISD::STORE, MVT::Other, DAG.getEntryNode(),
-                                     Node->getOperand(i), Idx, 
-                                     DAG.getSrcValue(NULL)));
-      }
-      
-      SDOperand StoreChain;
-      if (!Stores.empty())    // Not all undef elements?
-        StoreChain = DAG.getNode(ISD::TokenFactor, MVT::Other, Stores);
-      else
-        StoreChain = DAG.getEntryNode();
-      
-      // Result is a load from the stack slot.
-      Result = DAG.getLoad(VT, StoreChain, FIPtr, DAG.getSrcValue(0));
+    case TargetLowering::Expand:
+      Result = ExpandBUILD_VECTOR(Result.Val);
       break;
     }
-    }
     break;
   case ISD::INSERT_VECTOR_ELT:
     Tmp1 = LegalizeOp(Node->getOperand(0));  // InVec
@@ -853,6 +775,29 @@
     }
     }
     break;
+  case ISD::SCALAR_TO_VECTOR:
+    Tmp1 = LegalizeOp(Node->getOperand(0));  // InVal
+    Result = DAG.UpdateNodeOperands(Result, Tmp1);
+    switch (TLI.getOperationAction(ISD::SCALAR_TO_VECTOR,
+                                   Node->getValueType(0))) {
+    default: assert(0 && "This action is not supported yet!");
+    case TargetLowering::Legal:
+      break;
+    case TargetLowering::Expand: {
+      // If the target doesn't support this, store the value to a temporary
+      // stack slot, then EXTLOAD the vector back out.
+      SDOperand StackPtr = 
+        CreateStackTemporary(Node->getOperand(0).getValueType());
+      SDOperand Ch = DAG.getNode(ISD::STORE, MVT::Other, DAG.getEntryNode(),
+                                 Node->getOperand(0), StackPtr,
+                                 DAG.getSrcValue(NULL));
+      Result = DAG.getExtLoad(ISD::EXTLOAD, Node->getValueType(0), Ch, StackPtr,
+                              DAG.getSrcValue(NULL),
+                              Node->getOperand(0).getValueType());
+      break;
+    }
+    }
+    break;
   case ISD::CALLSEQ_START: {
     SDNode *CallEnd = FindCallEndFromCallStart(Node);
     
@@ -3005,10 +2950,7 @@
 SDOperand SelectionDAGLegalize::ExpandBIT_CONVERT(MVT::ValueType DestVT, 
                                                   SDOperand SrcOp) {
   // Create the stack frame object.
-  MachineFrameInfo *FrameInfo = DAG.getMachineFunction().getFrameInfo();
-  unsigned ByteSize = MVT::getSizeInBits(DestVT)/8;
-  int FrameIdx = FrameInfo->CreateStackObject(ByteSize, ByteSize);
-  SDOperand FIPtr = DAG.getFrameIndex(FrameIdx, TLI.getPointerTy());
+  SDOperand FIPtr = CreateStackTemporary(DestVT);
   
   // Emit a store to the stack slot.
   SDOperand Store = DAG.getNode(ISD::STORE, MVT::Other, DAG.getEntryNode(),
@@ -3017,6 +2959,117 @@
   return DAG.getLoad(DestVT, Store, FIPtr, DAG.getSrcValue(0));
 }
 
+/// ExpandBUILD_VECTOR - Expand a BUILD_VECTOR node on targets that don't
+/// support the operation, but do support the resultant packed vector type.
+SDOperand SelectionDAGLegalize::ExpandBUILD_VECTOR(SDNode *Node) {
+  
+  // If the only non-undef value is the low element, turn this into a 
+  // SCALAR_TO_VECTOR node.
+  bool isOnlyLowElement = true;
+  for (SDNode::op_iterator I = Node->op_begin()+1, E = Node->op_end();
+       I != E; ++I) {
+    if (I->getOpcode() != ISD::UNDEF) {
+      isOnlyLowElement = false;
+      break;
+    }
+  }
+  
+  if (isOnlyLowElement) {
+    // If the low element is an undef too, then this whole things is an undef.
+    if (Node->getOperand(0).getOpcode() == ISD::UNDEF)
+      return DAG.getNode(ISD::UNDEF, Node->getValueType(0));
+    // Otherwise, turn this into a scalar_to_vector node.
+    return DAG.getNode(ISD::SCALAR_TO_VECTOR, Node->getValueType(0),
+                       Node->getOperand(0));
+  }
+  
+  // If the elements are all constants, turn this into a load from the constant
+  // pool.
+  bool isConstant = true;
+  for (SDNode::op_iterator I = Node->op_begin(), E = Node->op_end();
+       I != E; ++I) {
+    if (!isa(I) && !isa(I) &&
+        I->getOpcode() != ISD::UNDEF) {
+      isConstant = false;
+      break;
+    }
+  }
+  
+  // Create a ConstantPacked, and put it in the constant pool.
+  if (isConstant) {
+    MVT::ValueType VT = Node->getValueType(0);
+    const Type *OpNTy = 
+      MVT::getTypeForValueType(Node->getOperand(0).getValueType());
+    std::vector CV;
+    for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) {
+      if (ConstantFPSDNode *V = 
+          dyn_cast(Node->getOperand(i))) {
+        CV.push_back(ConstantFP::get(OpNTy, V->getValue()));
+      } else if (ConstantSDNode *V = 
+                 dyn_cast(Node->getOperand(i))) {
+        CV.push_back(ConstantUInt::get(OpNTy, V->getValue()));
+      } else {
+        assert(Node->getOperand(i).getOpcode() == ISD::UNDEF);
+        CV.push_back(UndefValue::get(OpNTy));
+      }
+    }
+    Constant *CP = ConstantPacked::get(CV);
+    SDOperand CPIdx = DAG.getConstantPool(CP, TLI.getPointerTy());
+    return DAG.getLoad(VT, DAG.getEntryNode(), CPIdx,
+                       DAG.getSrcValue(NULL));
+  }
+  
+  // Otherwise, we can't handle this case efficiently.  Allocate a sufficiently
+  // aligned object on the stack, store each element into it, then load
+  // the result as a vector.
+  MVT::ValueType VT = Node->getValueType(0);
+  // Create the stack frame object.
+  SDOperand FIPtr = CreateStackTemporary(VT);
+  
+  // Emit a store of each element to the stack slot.
+  std::vector Stores;
+  bool isLittleEndian = TLI.isLittleEndian();
+  unsigned TypeByteSize = 
+    MVT::getSizeInBits(Node->getOperand(0).getValueType())/8;
+  unsigned VectorSize = MVT::getSizeInBits(VT)/8;
+  // Store (in the right endianness) the elements to memory.
+  for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) {
+    // Ignore undef elements.
+    if (Node->getOperand(i).getOpcode() == ISD::UNDEF) continue;
+    
+    unsigned Offset;
+    if (isLittleEndian) 
+      Offset = TypeByteSize*i;
+    else
+      Offset = TypeByteSize*(e-i-1);
+    
+    SDOperand Idx = DAG.getConstant(Offset, FIPtr.getValueType());
+    Idx = DAG.getNode(ISD::ADD, FIPtr.getValueType(), FIPtr, Idx);
+    
+    Stores.push_back(DAG.getNode(ISD::STORE, MVT::Other, DAG.getEntryNode(),
+                                 Node->getOperand(i), Idx, 
+                                 DAG.getSrcValue(NULL)));
+  }
+  
+  SDOperand StoreChain;
+  if (!Stores.empty())    // Not all undef elements?
+    StoreChain = DAG.getNode(ISD::TokenFactor, MVT::Other, Stores);
+  else
+    StoreChain = DAG.getEntryNode();
+  
+  // Result is a load from the stack slot.
+  return DAG.getLoad(VT, StoreChain, FIPtr, DAG.getSrcValue(0));
+}
+
+/// CreateStackTemporary - Create a stack temporary, suitable for holding the
+/// specified value type.
+SDOperand SelectionDAGLegalize::CreateStackTemporary(MVT::ValueType VT) {
+  MachineFrameInfo *FrameInfo = DAG.getMachineFunction().getFrameInfo();
+  unsigned ByteSize = MVT::getSizeInBits(VT)/8;
+  int FrameIdx = FrameInfo->CreateStackObject(ByteSize, ByteSize);
+  return DAG.getFrameIndex(FrameIdx, TLI.getPointerTy());
+}
+
 void SelectionDAGLegalize::ExpandShiftParts(unsigned NodeOp,
                                             SDOperand Op, SDOperand Amt,
                                             SDOperand &Lo, SDOperand &Hi) {


Index: llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp:1.274 llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp:1.275
--- llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp:1.274	Sat Mar 18 18:52:58 2006
+++ llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp	Sun Mar 19 00:31:19 2006
@@ -1092,6 +1092,11 @@
     if (OpOpcode == ISD::BIT_CONVERT)  // bitconv(bitconv(x)) -> bitconv(x)
       return getNode(ISD::BIT_CONVERT, VT, Operand.getOperand(0));
     break;
+  case ISD::SCALAR_TO_VECTOR:
+    assert(MVT::isVector(VT) && !MVT::isVector(Operand.getValueType()) &&
+           MVT::getVectorBaseType(VT) == Operand.getValueType() &&
+           "Illegal SCALAR_TO_VECTOR node!");
+    break;
   case ISD::FNEG:
     if (OpOpcode == ISD::FSUB)   // -(X-Y) -> (Y-X)
       return getNode(ISD::FSUB, VT, Operand.Val->getOperand(1),
@@ -1555,10 +1560,15 @@
     // normal load.
     if (ResultTys[0] == EVT)
       return getLoad(ResultTys[0], Ops[0], Ops[1], Ops[2]);
-    assert(EVT < ResultTys[0] &&
-           "Should only be an extending load, not truncating!");
+    if (MVT::isVector(ResultTys[0])) {
+      assert(EVT == MVT::getVectorBaseType(ResultTys[0]) &&
+             "Invalid vector extload!");
+    } else {
+      assert(EVT < ResultTys[0] &&
+             "Should only be an extending load, not truncating!");
+    }
     assert((Opcode == ISD::EXTLOAD || MVT::isInteger(ResultTys[0])) &&
-           "Cannot sign/zero extend a FP load!");
+           "Cannot sign/zero extend a FP/Vector load!");
     assert(MVT::isInteger(ResultTys[0]) == MVT::isInteger(EVT) &&
            "Cannot convert from FP to Int or Int -> FP!");
     break;
@@ -2654,6 +2664,7 @@
   case ISD::SELECT_CC:   return "select_cc";
   case ISD::INSERT_VECTOR_ELT: return "insert_vector_elt";
   case ISD::VINSERT_VECTOR_ELT: return "vinsert_vector_elt";
+  case ISD::SCALAR_TO_VECTOR:   return "scalar_to_vector";
   case ISD::ADDC:        return "addc";
   case ISD::ADDE:        return "adde";
   case ISD::SUBC:        return "subc";





From lattner at cs.uiuc.edu  Sun Mar 19 00:47:33 2006
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Sun, 19 Mar 2006 00:47:33 -0600
Subject: [llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp 
Message-ID: <200603190647.AAA27546@zion.cs.uiuc.edu>



Changes in directory llvm/lib/CodeGen/SelectionDAG:

LegalizeDAG.cpp updated: 1.324 -> 1.325
---
Log message:

Allow SCALAR_TO_VECTOR to be custom lowered.


---
Diffs of the changes:  (+9 -0)

 LegalizeDAG.cpp |    9 +++++++++
 1 files changed, 9 insertions(+)


Index: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.324 llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.325
--- llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.324	Sun Mar 19 00:31:19 2006
+++ llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp	Sun Mar 19 00:47:21 2006
@@ -783,9 +783,18 @@
     default: assert(0 && "This action is not supported yet!");
     case TargetLowering::Legal:
       break;
+    case TargetLowering::Custom:
+      Tmp3 = TLI.LowerOperation(Result, DAG);
+      if (Tmp3.Val) {
+        Result = Tmp3;
+        break;
+      }
+      // FALLTHROUGH
     case TargetLowering::Expand: {
       // If the target doesn't support this, store the value to a temporary
       // stack slot, then EXTLOAD the vector back out.
+      // TODO: If a target doesn't support this, create a stack slot for the
+      // whole vector, then store into it, then load the whole vector.
       SDOperand StackPtr = 
         CreateStackTemporary(Node->getOperand(0).getValueType());
       SDOperand Ch = DAG.getNode(ISD::STORE, MVT::Other, DAG.getEntryNode(),





From lattner at cs.uiuc.edu  Sun Mar 19 00:56:04 2006
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Sun, 19 Mar 2006 00:56:04 -0600
Subject: [llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCISelLowering.cpp
	PPCISelLowering.h PPCInstrInfo.td 
Message-ID: <200603190656.AAA27628@zion.cs.uiuc.edu>



Changes in directory llvm/lib/Target/PowerPC:

PPCISelLowering.cpp updated: 1.99 -> 1.100
PPCISelLowering.h updated: 1.26 -> 1.27
PPCInstrInfo.td updated: 1.190 -> 1.191
---
Log message:

Custom lower SCALAR_TO_VECTOR into lve*x.


---
Diffs of the changes:  (+37 -9)

 PPCISelLowering.cpp |   20 ++++++++++++++++++--
 PPCISelLowering.h   |    8 ++++++++
 PPCInstrInfo.td     |   18 +++++++++++-------
 3 files changed, 37 insertions(+), 9 deletions(-)


Index: llvm/lib/Target/PowerPC/PPCISelLowering.cpp
diff -u llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.99 llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.100
--- llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.99	Sun Mar 19 00:17:19 2006
+++ llvm/lib/Target/PowerPC/PPCISelLowering.cpp	Sun Mar 19 00:55:52 2006
@@ -184,8 +184,8 @@
     setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Expand);
     setOperationAction(ISD::BUILD_VECTOR, MVT::v4i32, Expand);
     
-    setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4f32, Expand);
-    setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i32, Expand);
+    setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4f32, Custom);
+    setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i32, Custom);
   }
   
   setSetCCResultContents(ZeroOrOneSetCCResult);
@@ -208,6 +208,7 @@
   case PPCISD::STFIWX:        return "PPCISD::STFIWX";
   case PPCISD::VMADDFP:       return "PPCISD::VMADDFP";
   case PPCISD::VNMSUBFP:      return "PPCISD::VNMSUBFP";
+  case PPCISD::LVE_X:         return "PPCISD::LVE_X";
   case PPCISD::Hi:            return "PPCISD::Hi";
   case PPCISD::Lo:            return "PPCISD::Lo";
   case PPCISD::GlobalBaseReg: return "PPCISD::GlobalBaseReg";
@@ -550,6 +551,21 @@
     }
     return DAG.getNode(PPCISD::RET_FLAG, MVT::Other, Copy, Copy.getValue(1));
   }
+  case ISD::SCALAR_TO_VECTOR: {
+    // Create a stack slot that is 16-byte aligned.
+    MachineFrameInfo *FrameInfo = DAG.getMachineFunction().getFrameInfo();
+    int FrameIdx = FrameInfo->CreateStackObject(16, 16);
+    SDOperand FIdx = DAG.getFrameIndex(FrameIdx, MVT::i32);
+    
+    // Store the input value into Value#0 of the stack slot.
+    unsigned InSize = MVT::getSizeInBits(Op.getOperand(0).getValueType())/8;
+    FIdx = DAG.getNode(ISD::ADD, MVT::i32, FIdx,
+                       DAG.getConstant(16-InSize, MVT::i32));
+    SDOperand Store = DAG.getNode(ISD::STORE, MVT::Other, DAG.getEntryNode(),
+                                  Op.getOperand(0), FIdx,DAG.getSrcValue(NULL));
+    return DAG.getNode(PPCISD::LVE_X, Op.getValueType(), Store, FIdx, 
+                       DAG.getSrcValue(NULL));
+  }
   }
   return SDOperand();
 }


Index: llvm/lib/Target/PowerPC/PPCISelLowering.h
diff -u llvm/lib/Target/PowerPC/PPCISelLowering.h:1.26 llvm/lib/Target/PowerPC/PPCISelLowering.h:1.27
--- llvm/lib/Target/PowerPC/PPCISelLowering.h:1.26	Mon Mar 13 17:20:37 2006
+++ llvm/lib/Target/PowerPC/PPCISelLowering.h	Sun Mar 19 00:55:52 2006
@@ -48,6 +48,14 @@
       // three v4f32 operands and producing a v4f32 result.
       VMADDFP, VNMSUBFP,
       
+      /// LVE_X - The PPC LVE*X instructions.  The size of the element loaded is
+      /// the size of the element type of the vector result.  The element loaded
+      /// depends on the alignment of the input pointer.
+      ///
+      /// The first operand is a token chain, the second is the address to load
+      /// the third is the SRCVALUE node.
+      LVE_X,
+      
       /// Hi/Lo - These represent the high and low 16-bit parts of a global
       /// address respectively.  These nodes have two operands, the first of
       /// which must be a TargetGlobalAddress, and the second of which must be a


Index: llvm/lib/Target/PowerPC/PPCInstrInfo.td
diff -u llvm/lib/Target/PowerPC/PPCInstrInfo.td:1.190 llvm/lib/Target/PowerPC/PPCInstrInfo.td:1.191
--- llvm/lib/Target/PowerPC/PPCInstrInfo.td:1.190	Sun Mar 19 00:10:09 2006
+++ llvm/lib/Target/PowerPC/PPCInstrInfo.td	Sun Mar 19 00:55:52 2006
@@ -45,6 +45,8 @@
 def PPCvmaddfp  : SDNode<"PPCISD::VMADDFP", SDTFPTernaryOp, []>;
 def PPCvnmsubfp : SDNode<"PPCISD::VNMSUBFP", SDTFPTernaryOp, []>;
 
+def PPClve_x    : SDNode<"PPCISD::LVE_X", SDTLoad, [SDNPHasChain]>;
+
 // These nodes represent the 32-bit PPC shifts that operate on 6-bit shift
 // amounts.  These nodes are generated by the multi-precision shift code.
 def PPCsrl        : SDNode<"PPCISD::SRL"       , SDT_PPCShiftOp>;
@@ -451,15 +453,15 @@
 def LDX  : XForm_1<31,  21, (ops G8RC:$rD, memrr:$src),
                    "ldx $rD, $src", LdStLD,
                    [(set G8RC:$rD, (load xaddr:$src))]>, isPPC64;
-def LVEBX: XForm_1<31,   7, (ops VRRC:$vD,  GPRC:$base, GPRC:$rA),
-                   "lvebx $vD, $base, $rA", LdStGeneral,
-                   []>;
-def LVEHX: XForm_1<31,  39, (ops VRRC:$vD,  GPRC:$base, GPRC:$rA),
-                   "lvehx $vD, $base, $rA", LdStGeneral,
+def LVEBX: XForm_1<31,   7, (ops VRRC:$vD, memrr:$src),
+                   "lvebx $vD, $src", LdStGeneral,
                    []>;
-def LVEWX: XForm_1<31,  71, (ops VRRC:$vD,  GPRC:$base, GPRC:$rA),
-                   "lvewx $vD, $base, $rA", LdStGeneral,
+def LVEHX: XForm_1<31,  39, (ops VRRC:$vD,  memrr:$src),
+                   "lvehx $vD, $src", LdStGeneral,
                    []>;
+def LVEWX: XForm_1<31,  71, (ops VRRC:$vD,  memrr:$src),
+                   "lvewx $vD, $src", LdStGeneral,
+                   [(set VRRC:$vD, (v4f32 (PPClve_x xoaddr:$src)))]>;
 def LVX  : XForm_1<31, 103, (ops VRRC:$vD,  memrr:$src),
                    "lvx $vD, $src", LdStGeneral,
                    [(set VRRC:$vD, (v4f32 (load xoaddr:$src)))]>;
@@ -1149,6 +1151,8 @@
           (v4i32 (LVX xoaddr:$src))>;
 def : Pat<(store (v4i32 VRRC:$rS), xoaddr:$dst),
           (STVX (v4i32 VRRC:$rS), xoaddr:$dst)>;
+def : Pat<(v4i32 (PPClve_x xoaddr:$src)),
+          (v4i32 (LVEWX xoaddr:$src))>;
 
 def : Pat<(v4i32 (undef)), (v4i32 (IMPLICIT_DEF_VRRC))>;
 





From evan.cheng at apple.com  Sun Mar 19 01:57:46 2006
From: evan.cheng at apple.com (Evan Cheng)
Date: Sun, 19 Mar 2006 01:57:46 -0600
Subject: [llvm-commits] CVS: llvm/utils/TableGen/CodeGenTarget.cpp 
Message-ID: <200603190757.BAA27890@zion.cs.uiuc.edu>



Changes in directory llvm/utils/TableGen:

CodeGenTarget.cpp updated: 1.56 -> 1.57
---
Log message:

getEnumName() missed v8i8, v4i16, and v2i32 types

---
Diffs of the changes:  (+3 -0)

 CodeGenTarget.cpp |    3 +++
 1 files changed, 3 insertions(+)


Index: llvm/utils/TableGen/CodeGenTarget.cpp
diff -u llvm/utils/TableGen/CodeGenTarget.cpp:1.56 llvm/utils/TableGen/CodeGenTarget.cpp:1.57
--- llvm/utils/TableGen/CodeGenTarget.cpp:1.56	Tue Feb 28 19:10:52 2006
+++ llvm/utils/TableGen/CodeGenTarget.cpp	Sun Mar 19 01:57:34 2006
@@ -76,6 +76,9 @@
   case MVT::f128:  return "f128";
   case MVT::Flag:  return "Flag";
   case MVT::isVoid:return "isVoid";
+  case MVT::v8i8:  return "v8i8";
+  case MVT::v4i16: return "v4i16";
+  case MVT::v2i32: return "v2i32";
   case MVT::v16i8: return "v16i8";
   case MVT::v8i16: return "v8i16";
   case MVT::v4i32: return "v4i32";





From evan.cheng at apple.com  Sun Mar 19 03:39:07 2006
From: evan.cheng at apple.com (Evan Cheng)
Date: Sun, 19 Mar 2006 03:39:07 -0600
Subject: [llvm-commits] CVS: llvm/lib/Target/X86/X86InstrSSE.td 
Message-ID: <200603190939.DAA28182@zion.cs.uiuc.edu>



Changes in directory llvm/lib/Target/X86:

X86InstrSSE.td updated: 1.7 -> 1.8
---
Log message:

Vector undef's

---
Diffs of the changes:  (+21 -0)

 X86InstrSSE.td |   21 +++++++++++++++++++++
 1 files changed, 21 insertions(+)


Index: llvm/lib/Target/X86/X86InstrSSE.td
diff -u llvm/lib/Target/X86/X86InstrSSE.td:1.7 llvm/lib/Target/X86/X86InstrSSE.td:1.8
--- llvm/lib/Target/X86/X86InstrSSE.td:1.7	Fri Mar 17 19:23:20 2006
+++ llvm/lib/Target/X86/X86InstrSSE.td	Sun Mar 19 03:38:54 2006
@@ -341,6 +341,14 @@
 // SSE packed FP Instructions
 //===----------------------------------------------------------------------===//
 
+// Some 'special' instructions
+def IMPLICIT_DEF_VR128 : I<0, Pseudo, (ops VR128:$dst),
+                           "#IMPLICIT_DEF $dst",
+                           [(set VR128:$dst, (v4f32 (undef)))]>,
+                         Requires<[HasSSE1]>;
+
+def : Pat<(v2f64 (undef)), (IMPLICIT_DEF_VR128)>, Requires<[HasSSE2]>;
+
 // Move Instructions
 def MOVAPSrr : PSI<0x28, MRMSrcReg, (ops VR128:$dst, VR128:$src),
                    "movaps {$src, $dst|$dst, $src}", []>;
@@ -686,6 +694,19 @@
 // SSE integer instructions
 //===----------------------------------------------------------------------===//
 
+// Some 'special' instructions
+def IMPLICIT_DEF_VR64 : I<0, Pseudo, (ops VR64:$dst),
+                          "#IMPLICIT_DEF $dst",
+                          [(set VR64:$dst, (v8i8 (undef)))]>,
+                        Requires<[HasMMX]>;
+
+def : Pat<(v4i16 (undef)), (IMPLICIT_DEF_VR64)>,  Requires<[HasMMX]>;
+def : Pat<(v2i32 (undef)), (IMPLICIT_DEF_VR64)>,  Requires<[HasMMX]>;
+def : Pat<(v16i8 (undef)), (IMPLICIT_DEF_VR128)>, Requires<[HasSSE2]>;
+def : Pat<(v8i16 (undef)), (IMPLICIT_DEF_VR128)>, Requires<[HasSSE2]>;
+def : Pat<(v4i32 (undef)), (IMPLICIT_DEF_VR128)>, Requires<[HasSSE2]>;
+def : Pat<(v2i64 (undef)), (IMPLICIT_DEF_VR128)>, Requires<[HasSSE2]>;
+
 // Move Instructions
 def MOVD128rr : PDI<0x6E, MRMSrcReg, (ops VR128:$dst, R32:$src),
                   "movd {$src, $dst|$dst, $src}", []>;





From lattner at cs.uiuc.edu  Sun Mar 19 13:36:55 2006
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Sun, 19 Mar 2006 13:36:55 -0600
Subject: [llvm-commits] 
	CVS: llvm/test/Regression/Transforms/CorrelatedExprs/switch.ll
Message-ID: <200603191936.NAA02025@zion.cs.uiuc.edu>



Changes in directory llvm/test/Regression/Transforms/CorrelatedExprs:

switch.ll added (r1.1)
---
Log message:

new testcase, contributed by Eric Kidd.


---
Diffs of the changes:  (+20 -0)

 switch.ll |   20 ++++++++++++++++++++
 1 files changed, 20 insertions(+)


Index: llvm/test/Regression/Transforms/CorrelatedExprs/switch.ll
diff -c /dev/null llvm/test/Regression/Transforms/CorrelatedExprs/switch.ll:1.1
*** /dev/null	Sun Mar 19 13:36:42 2006
--- llvm/test/Regression/Transforms/CorrelatedExprs/switch.ll	Sun Mar 19 13:36:32 2006
***************
*** 0 ****
--- 1,20 ----
+ ; RUN: llvm-as < %s | opt -cee -constprop -instcombine -dce | llvm-dis | not grep 'REMOVE'
+ 
+ int %test_case_values_should_propagate(int %A) {
+     switch int %A, label %D [
+         int 40, label %C1
+         int 41, label %C2
+         int 42, label %C3
+     ]
+ C1:
+     %REMOVE1 = add int %A, 2     ; Should be 42.
+     ret int %REMOVE1
+ C2:
+     %REMOVE2 = add int %A, 3     ; Should be 44.
+     ret int %REMOVE2
+ C3:
+     %REMOVE3 = add int %A, 4     ; Should be 46.
+     ret int %REMOVE3
+ D:
+     ret int 10
+ }





From lattner at cs.uiuc.edu  Sun Mar 19 13:37:36 2006
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Sun, 19 Mar 2006 13:37:36 -0600
Subject: [llvm-commits] CVS: llvm/lib/Transforms/Scalar/CorrelatedExprs.cpp 
Message-ID: <200603191937.NAA02067@zion.cs.uiuc.edu>



Changes in directory llvm/lib/Transforms/Scalar:

CorrelatedExprs.cpp updated: 1.32 -> 1.33
---
Log message:

Teach cee to propagate through switch statements.  This implements
Transforms/CorrelatedExprs/switch.ll

Patch contributed by Eric Kidd!


---
Diffs of the changes:  (+21 -1)

 CorrelatedExprs.cpp |   22 +++++++++++++++++++++-
 1 files changed, 21 insertions(+), 1 deletion(-)


Index: llvm/lib/Transforms/Scalar/CorrelatedExprs.cpp
diff -u llvm/lib/Transforms/Scalar/CorrelatedExprs.cpp:1.32 llvm/lib/Transforms/Scalar/CorrelatedExprs.cpp:1.33
--- llvm/lib/Transforms/Scalar/CorrelatedExprs.cpp:1.32	Thu Jan 26 14:41:32 2006
+++ llvm/lib/Transforms/Scalar/CorrelatedExprs.cpp	Sun Mar 19 13:37:24 2006
@@ -267,6 +267,7 @@
                              const std::vector &RegionExitBlocks);
 
     void PropagateBranchInfo(BranchInst *BI);
+    void PropagateSwitchInfo(SwitchInst *SI);
     void PropagateEquality(Value *Op0, Value *Op1, RegionInfo &RI);
     void PropagateRelation(Instruction::BinaryOps Opcode, Value *Op0,
                            Value *Op1, RegionInfo &RI);
@@ -360,9 +361,12 @@
   // Now that all of our successors have information if they deserve it,
   // propagate any information our terminator instruction finds to our
   // successors.
-  if (BranchInst *BI = dyn_cast(TI))
+  if (BranchInst *BI = dyn_cast(TI)) {
     if (BI->isConditional())
       PropagateBranchInfo(BI);
+  } else if (SwitchInst *SI = dyn_cast(TI)) {
+    PropagateSwitchInfo(SI);
+  }
 
   // If this is a branch to a block outside our region that simply performs
   // another conditional branch, one whose outcome is known inside of this
@@ -794,6 +798,22 @@
 }
 
 
+// PropagateSwitchInfo - We need to propagate the value tested by the
+// switch statement through each case block.
+//
+void CEE::PropagateSwitchInfo(SwitchInst *SI) {
+  // Propagate information down each of our non-default case labels.  We
+  // don't yet propagate information down the default label, because a
+  // potentially large number of inequality constraints provide less
+  // benefit per unit work than a single equality constraint.
+  //
+  Value *cond = SI->getCondition();
+  for (unsigned i = 1; i < SI->getNumSuccessors(); ++i)
+    PropagateEquality(cond, SI->getSuccessorValue(i),
+                      getRegionInfo(SI->getSuccessor(i)));
+}
+
+
 // PropagateEquality - If we discover that two values are equal to each other in
 // a specified region, propagate this knowledge recursively.
 //





From llvm at cs.uiuc.edu  Sun Mar 19 15:40:27 2006
From: llvm at cs.uiuc.edu (LLVM)
Date: Sun, 19 Mar 2006 15:40:27 -0600
Subject: [llvm-commits] CVS: llvm/utils/llvm-config/
Message-ID: <200603192140.PAA02879@zion.cs.uiuc.edu>



Changes in directory llvm/utils/llvm-config:

---
Log message:

Directory /var/cvs/llvm/llvm/utils/llvm-config added to the repository


---
Diffs of the changes:  (+0 -0)

 0 files changed





From reid at x10sys.com  Sun Mar 19 16:08:14 2006
From: reid at x10sys.com (Reid Spencer)
Date: Sun, 19 Mar 2006 16:08:14 -0600
Subject: [llvm-commits] CVS: llvm/utils/GenLibDeps.pl 
Message-ID: <200603192208.QAA03245@zion.cs.uiuc.edu>



Changes in directory llvm/utils:

GenLibDeps.pl updated: 1.3 -> 1.4
---
Log message:

Add a -flat option for generating the library dependencies in a flat 
format with one library per line, similar to a makefile dependency list.


---
Diffs of the changes:  (+31 -5)

 GenLibDeps.pl |   36 +++++++++++++++++++++++++++++++-----
 1 files changed, 31 insertions(+), 5 deletions(-)


Index: llvm/utils/GenLibDeps.pl
diff -u llvm/utils/GenLibDeps.pl:1.3 llvm/utils/GenLibDeps.pl:1.4
--- llvm/utils/GenLibDeps.pl:1.3	Wed Jan  5 11:29:29 2005
+++ llvm/utils/GenLibDeps.pl	Sun Mar 19 16:08:01 2006
@@ -9,6 +9,16 @@
 # Syntax:   GenLibDeps.pl 
 #
 
+# Parse arguments... 
+while (scalar(@ARGV) and ($_ = $ARGV[0], /^[-+]/)) {
+  shift;
+  last if /^--$/;  # Stop processing arguments on --
+
+  # List command line options here...
+  if (/^-flat$/)     { $FLAT = 1; next; }
+  print "Unknown option: $_ : ignoring!\n";
+}
+
 # Give first option a name.
 my $Directory = $ARGV[0];
 
@@ -58,7 +68,11 @@
   my $lib = $_[0];
   my $lib_ns = $lib;
   $lib_ns =~ s/(.*)\.[oa]/$1/;
-  print "  
      $lib
        \n";
+  if ($FLAT) {
+    print "$lib:";
+  } else {
+    print "  
        $lib
          \n";
+  }
   open UNDEFS, 
     "nm -u $Directory/$lib | grep ' U ' | sed -e 's/         U //' | sort | uniq |";
   open DEPENDS,
@@ -80,7 +94,11 @@
   open DF, ") {
     chomp;
-    print "    
        • $_
          • \n";
+    if ($FLAT) {
+      print " $_";
+    } else {
+      print "    
        • $_
          • \n";
+    }
     $suffix = substr($_,length($_)-1,1);
     $_ =~ s/(.*)\.[oa]/$1/;
     if ($suffix eq "a") {
@@ -90,7 +108,11 @@
     }
   }
   close DF;
-  print "  
        \n";
+  if ($FLAT) {
+    print "\n";
+  } else {
+    print "  
      \n";
+  }
 }
 
 # Make sure we flush on write. This is slower but correct based on the way we
@@ -98,7 +120,9 @@
 $| = 1;
 
 # Print the definition list tag
-print "
      \n";
+if (!$FLAT) {
+  print "
      \n";
+}
 
 open DOT, "| $DotPath -Tgif > libdeps.gif";
 
@@ -125,4 +149,6 @@
 close DOT;
 
 # Print end tag of definition list element
-print "
      \n";
+if (!$FLAT) {
+  print "
      \n";
+}





From lattner at cs.uiuc.edu  Sun Mar 19 16:08:20 2006
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Sun, 19 Mar 2006 16:08:20 -0600
Subject: [llvm-commits] CVS: llvm/lib/Target/PowerPC/README.txt 
Message-ID: <200603192208.QAA03252@zion.cs.uiuc.edu>



Changes in directory llvm/lib/Target/PowerPC:

README.txt updated: 1.75 -> 1.76
---
Log message:

Add a note about the MUL -> FMADD vector bug.


---
Diffs of the changes:  (+10 -0)

 README.txt |   10 ++++++++++
 1 files changed, 10 insertions(+)


Index: llvm/lib/Target/PowerPC/README.txt
diff -u llvm/lib/Target/PowerPC/README.txt:1.75 llvm/lib/Target/PowerPC/README.txt:1.76
--- llvm/lib/Target/PowerPC/README.txt:1.75	Sat Mar 18 23:33:30 2006
+++ llvm/lib/Target/PowerPC/README.txt	Sun Mar 19 16:08:08 2006
@@ -536,3 +536,13 @@
   bar (x);
 }
 
+===-------------------------------------------------------------------------===
+
+Altivec: Codegen'ing MUL with vector FMADD should add -0.0, not 0.0:
+http://gcc.gnu.org/bugzilla/show_bug.cgi?id=8763
+
+We need to codegen -0.0 vector efficiently (no constant pool load).
+
+When -ffast-math is on, we can use 0.0.
+
+===-------------------------------------------------------------------------===





From reid at x10sys.com  Sun Mar 19 16:11:05 2006
From: reid at x10sys.com (Reid Spencer)
Date: Sun, 19 Mar 2006 16:11:05 -0600
Subject: [llvm-commits] CVS: llvm/utils/llvm-config/Makefile 
Message-ID: <200603192211.QAA03306@zion.cs.uiuc.edu>



Changes in directory llvm/utils/llvm-config:

Makefile added (r1.1)
---
Log message:

First cut at the Makefile for llvm-config. This initial version just provides
the rule for building the LibDeps.txt file using GenLibDeps.pl. This needs
to be done from time to time manually in order to keep LibDeps.txt up to 
date. 


---
Diffs of the changes:  (+16 -0)

 Makefile |   16 ++++++++++++++++
 1 files changed, 16 insertions(+)


Index: llvm/utils/llvm-config/Makefile
diff -c /dev/null llvm/utils/llvm-config/Makefile:1.1
*** /dev/null	Sun Mar 19 16:11:04 2006
--- llvm/utils/llvm-config/Makefile	Sun Mar 19 16:10:53 2006
***************
*** 0 ****
--- 1,16 ----
+ ##===- utils/llvm-config/Makefile --------------------------*- Makefile -*-===##
+ # 
+ #                     The LLVM Compiler Infrastructure
+ #
+ # This file was developed by Reid Spencer and Eric Kidd and is distributed under
+ # the University of Illinois Open Source License. See LICENSE.TXT for details.
+ # 
+ ##===----------------------------------------------------------------------===##
+ 
+ LEVEL = ../..
+ 
+ 
+ include $(LEVEL)/Makefile.common
+ 
+ LibDeps.txt: $(LEVEL)/utils/GenLibDeps.pl $(LibDir)
+ 	$(LEVEL)/utils/GenLibDeps.pl -flat $(LibDir) | sort > LibDeps.txt





From reid at x10sys.com  Sun Mar 19 16:12:42 2006
From: reid at x10sys.com (Reid Spencer)
Date: Sun, 19 Mar 2006 16:12:42 -0600
Subject: [llvm-commits] CVS: llvm/utils/llvm-config/LibDeps.txt 
Message-ID: <200603192212.QAA03336@zion.cs.uiuc.edu>



Changes in directory llvm/utils/llvm-config:

LibDeps.txt added (r1.1)
---
Log message:

The library dependency file in flat format. This file is generated by the
makefile using the utils/GenLibDeps.pl script with the -flat option. It
records the dependencies between libraries in such a way that the 
llvm-config script can easily read it (in makefile dependency format).


---
Diffs of the changes:  (+35 -0)

 LibDeps.txt |   35 +++++++++++++++++++++++++++++++++++
 1 files changed, 35 insertions(+)


Index: llvm/utils/llvm-config/LibDeps.txt
diff -c /dev/null llvm/utils/llvm-config/LibDeps.txt:1.1
*** /dev/null	Sun Mar 19 16:12:40 2006
--- llvm/utils/llvm-config/LibDeps.txt	Sun Mar 19 16:12:30 2006
***************
*** 0 ****
--- 1,35 ----
+ libLLVMAnalysis.a: libLLVMSupport.a libLLVMTarget.a LLVMCore.o
+ libLLVMArchive.a: libLLVMSupport.a libLLVMSystem.a LLVMBCReader.o LLVMCore.o
+ libLLVMInstrumentation.a: libLLVMScalarOpts.a libLLVMSupport.a libLLVMTransformUtils.a LLVMCore.o
+ libLLVMipa.a: libLLVMAnalysis.a libLLVMSupport.a LLVMCore.o
+ libLLVMipo.a: libLLVMAnalysis.a libLLVMipa.a libLLVMSupport.a libLLVMTarget.a libLLVMTransformUtils.a LLVMCore.o
+ libLLVMLinker.a: libLLVMArchive.a libLLVMSystem.a LLVMBCReader.o LLVMCore.o
+ libLLVMScalarOpts.a: libLLVMAnalysis.a libLLVMSupport.a libLLVMTarget.a libLLVMTransformUtils.a LLVMCore.o
+ libLLVMSupport.a: libLLVMSystem.a LLVMbzip2.o
+ libLLVMSystem.a:
+ libLLVMTarget.a: libLLVMSupport.a LLVMCodeGen.o LLVMCore.o LLVMSelectionDAG.o
+ libLLVMTransforms.a: libLLVMSupport.a libLLVMTarget.a libLLVMTransformUtils.a LLVMCore.o
+ libLLVMTransformUtils.a: libLLVMAnalysis.a libLLVMipa.a libLLVMSupport.a LLVMCore.o
+ LLVMAlpha.o: libLLVMScalarOpts.a libLLVMSupport.a libLLVMTarget.a LLVMCodeGen.o LLVMCore.o LLVMSelectionDAG.o
+ LLVMAsmParser.o: LLVMCore.o
+ LLVMBCReader.o: libLLVMSupport.a libLLVMSystem.a LLVMCore.o
+ LLVMBCWriter.o: libLLVMSupport.a LLVMCore.o
+ LLVMbzip2.o:
+ LLVMCBackend.o: libLLVMAnalysis.a libLLVMipa.a libLLVMScalarOpts.a libLLVMSupport.a libLLVMTarget.a LLVMCore.o
+ LLVMCodeGen.o: libLLVMAnalysis.a libLLVMSupport.a libLLVMTarget.a LLVMCore.o
+ LLVMCore.o: libLLVMSupport.a
+ LLVMDataStructure.o: libLLVMAnalysis.a libLLVMSupport.a libLLVMTarget.a LLVMCore.o
+ LLVMDebugger.o: libLLVMSupport.a libLLVMSystem.a LLVMBCReader.o LLVMCore.o
+ LLVMExecutionEngine.o: libLLVMSupport.a libLLVMSystem.a libLLVMTarget.a LLVMCore.o LLVMInterpreter.o LLVMJIT.o
+ LLVMIA64.o: libLLVMScalarOpts.a libLLVMSupport.a libLLVMTarget.a LLVMCodeGen.o LLVMCore.o LLVMSelectionDAG.o
+ LLVMInterpreter.o: libLLVMSupport.a libLLVMSystem.a libLLVMTarget.a LLVMCore.o LLVMExecutionEngine.o
+ LLVMJIT.o: libLLVMSupport.a libLLVMSystem.a libLLVMTarget.a LLVMCore.o LLVMExecutionEngine.o
+ LLVMPowerPC.o: libLLVMScalarOpts.a libLLVMSupport.a libLLVMTarget.a LLVMCodeGen.o LLVMCore.o LLVMSelectionDAG.o
+ LLVMSelectionDAG.o: libLLVMSupport.a libLLVMSystem.a libLLVMTarget.a libLLVMTransformUtils.a LLVMCodeGen.o LLVMCore.o
+ LLVMSparc.o: libLLVMScalarOpts.a libLLVMSupport.a libLLVMTarget.a LLVMCodeGen.o LLVMCore.o LLVMSelectionDAG.o
+ LLVMSparcV9InstrSched.o: libLLVMSupport.a LLVMCodeGen.o LLVMCore.o LLVMSparcV9LiveVar.o LLVMSparcV9.o
+ LLVMSparcV9LiveVar.o: libLLVMSupport.a LLVMCodeGen.o LLVMCore.o
+ LLVMSparcV9ModuloSched.o: libLLVMAnalysis.a libLLVMSupport.a libLLVMTarget.a LLVMCodeGen.o LLVMCore.o LLVMSparcV9.o
+ LLVMSparcV9.o: libLLVMScalarOpts.a libLLVMSupport.a libLLVMTarget.a LLVMBCWriter.o LLVMCodeGen.o LLVMCore.o LLVMSparcV9InstrSched.o LLVMSparcV9ModuloSched.o LLVMSparcV9RegAlloc.o
+ LLVMSparcV9RegAlloc.o: libLLVMAnalysis.a libLLVMSupport.a LLVMCodeGen.o LLVMCore.o LLVMSparcV9LiveVar.o LLVMSparcV9.o
+ LLVMX86.o: libLLVMScalarOpts.a libLLVMSupport.a libLLVMTarget.a LLVMCodeGen.o LLVMCore.o LLVMSelectionDAG.o





From lattner at cs.uiuc.edu  Sun Mar 19 16:27:53 2006
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Sun, 19 Mar 2006 16:27:53 -0600
Subject: [llvm-commits] CVS: llvm/lib/Target/X86/README.txt 
Message-ID: <200603192227.QAA03508@zion.cs.uiuc.edu>



Changes in directory llvm/lib/Target/X86:

README.txt updated: 1.67 -> 1.68
---
Log message:

add a note with a testcase


---
Diffs of the changes:  (+11 -0)

 README.txt |   11 +++++++++++
 1 files changed, 11 insertions(+)


Index: llvm/lib/Target/X86/README.txt
diff -u llvm/lib/Target/X86/README.txt:1.67 llvm/lib/Target/X86/README.txt:1.68
--- llvm/lib/Target/X86/README.txt:1.67	Sun Mar 19 00:08:11 2006
+++ llvm/lib/Target/X86/README.txt	Sun Mar 19 16:27:41 2006
@@ -633,3 +633,14 @@
 The following tests perform worse with LSR:
 
 lambda, siod, optimizer-eval, ackermann, hash2, nestedloop, strcat, and Treesor.
+
+//===---------------------------------------------------------------------===//
+
+Should generate min/max for stuff like:
+
+void minf(float a, float b, float *X) {
+  *X = a <= b ? a : b;
+}
+
+//===---------------------------------------------------------------------===//
+





From lattner at cs.uiuc.edu  Sun Mar 19 17:41:44 2006
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Sun, 19 Mar 2006 17:41:44 -0600
Subject: [llvm-commits] CVS: llvm/include/llvm/CodeGen/ValueTypes.h 
Message-ID: <200603192341.RAA04258@zion.cs.uiuc.edu>



Changes in directory llvm/include/llvm/CodeGen:

ValueTypes.h updated: 1.23 -> 1.24
---
Log message:

Add a helper method



---
Diffs of the changes:  (+18 -0)

 ValueTypes.h |   18 ++++++++++++++++++
 1 files changed, 18 insertions(+)


Index: llvm/include/llvm/CodeGen/ValueTypes.h
diff -u llvm/include/llvm/CodeGen/ValueTypes.h:1.23 llvm/include/llvm/CodeGen/ValueTypes.h:1.24
--- llvm/include/llvm/CodeGen/ValueTypes.h:1.23	Sat Mar 18 23:26:45 2006
+++ llvm/include/llvm/CodeGen/ValueTypes.h	Sun Mar 19 17:41:32 2006
@@ -161,6 +161,24 @@
     }
   }
   
+  /// MVT::getVectorNumElements - Given a packed vector type, return the number
+  /// of elements it contains.
+  static inline unsigned getVectorNumElements(ValueType VT) {
+    switch (VT) {
+      default: assert(0 && "Invalid vector type!");
+      case v16i8: return 16;
+      case v8i8 :
+      case v8i16: return 8;
+      case v4i16:
+      case v4i32: 
+      case v4f32: return 4;
+      case v2i32:
+      case v2i64:
+      case v2f32:
+      case v2f64: return 2;
+    }
+  }
+  
   /// MVT::getIntVTBitMask - Return an integer with 1's every place there are
   /// bits in the specified integer value type.
   static inline uint64_t getIntVTBitMask(ValueType VT) {





From lattner at cs.uiuc.edu  Sun Mar 19 17:43:03 2006
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Sun, 19 Mar 2006 17:43:03 -0600
Subject: [llvm-commits] CVS: llvm/include/llvm/CodeGen/SelectionDAGNodes.h 
Message-ID: <200603192343.RAA04310@zion.cs.uiuc.edu>



Changes in directory llvm/include/llvm/CodeGen:

SelectionDAGNodes.h updated: 1.115 -> 1.116
---
Log message:

add a node


---
Diffs of the changes:  (+9 -0)

 SelectionDAGNodes.h |    9 +++++++++
 1 files changed, 9 insertions(+)


Index: llvm/include/llvm/CodeGen/SelectionDAGNodes.h
diff -u llvm/include/llvm/CodeGen/SelectionDAGNodes.h:1.115 llvm/include/llvm/CodeGen/SelectionDAGNodes.h:1.116
--- llvm/include/llvm/CodeGen/SelectionDAGNodes.h:1.115	Sat Mar 18 23:26:45 2006
+++ llvm/include/llvm/CodeGen/SelectionDAGNodes.h	Sun Mar 19 17:42:51 2006
@@ -157,6 +157,15 @@
     /// type) with the element at IDX replaced with VAL.
     INSERT_VECTOR_ELT,
     
+    /// VECTOR_SHUFFLE(VEC1, VEC2, SHUFFLEVEC) - Returns a vector, of the same
+    /// type as VEC1/VEC2.  SHUFFLEVEC is a BUILD_VECTOR of constant int values
+    /// (regardless of whether its datatype is legal or not) that indicate
+    /// which value each result element will get.  The elements of VEC1/VEC2 are
+    /// enumerated in order.  This is quite similar to the Altivec 'vperm'
+    /// instruction, except that the indices must be constants and are in terms
+    /// of the element size of VEC1/VEC2, not in terms of bytes.
+    VECTOR_SHUFFLE,
+    
     /// BINOP(LHS, RHS,  COUNT,TYPE)
     /// Simple abstract vector operators.  Unlike the integer and floating point
     /// binary operators, these nodes also take two additional operands:





From lattner at cs.uiuc.edu  Sun Mar 19 17:56:16 2006
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Sun, 19 Mar 2006 17:56:16 -0600
Subject: [llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp 
Message-ID: <200603192356.RAA04464@zion.cs.uiuc.edu>



Changes in directory llvm/lib/CodeGen/SelectionDAG:

SelectionDAG.cpp updated: 1.275 -> 1.276
---
Log message:

Add very basic support for VECTOR_SHUFFLE


---
Diffs of the changes:  (+9 -1)

 SelectionDAG.cpp |   10 +++++++++-
 1 files changed, 9 insertions(+), 1 deletion(-)


Index: llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp:1.275 llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp:1.276
--- llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp:1.275	Sun Mar 19 00:31:19 2006
+++ llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp	Sun Mar 19 17:56:04 2006
@@ -1360,6 +1360,13 @@
       else
         return N1;         // Never-taken branch
     break;
+  case ISD::VECTOR_SHUFFLE:
+    assert(VT == N1.getValueType() && VT == N2.getValueType() &&
+           MVT::isVector(VT) && MVT::isVector(N3.getValueType()) &&
+           N3.getOpcode() == ISD::BUILD_VECTOR &&
+           MVT::getVectorNumElements(VT) == N3.getNumOperands() &&
+           "Illegal VECTOR_SHUFFLE node!");
+    break;
   }
 
   std::vector Ops;
@@ -2615,7 +2622,6 @@
   case ISD::TargetFrameIndex: return "TargetFrameIndex";
   case ISD::TargetConstantPool:  return "TargetConstantPool";
   case ISD::TargetExternalSymbol: return "TargetExternalSymbol";
-  case ISD::VBUILD_VECTOR: return "VBUILD_VECTOR";
 
   case ISD::CopyToReg:     return "CopyToReg";
   case ISD::CopyFromReg:   return "CopyFromReg";
@@ -2665,6 +2671,8 @@
   case ISD::INSERT_VECTOR_ELT: return "insert_vector_elt";
   case ISD::VINSERT_VECTOR_ELT: return "vinsert_vector_elt";
   case ISD::SCALAR_TO_VECTOR:   return "scalar_to_vector";
+  case ISD::VBUILD_VECTOR: return "vbuild_vector";
+  case ISD::VECTOR_SHUFFLE: return "vector_shuffle";
   case ISD::ADDC:        return "addc";
   case ISD::ADDE:        return "adde";
   case ISD::SUBC:        return "subc";





From lattner at cs.uiuc.edu  Sun Mar 19 18:20:42 2006
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Sun, 19 Mar 2006 18:20:42 -0600
Subject: [llvm-commits] CVS: llvm/include/llvm/CodeGen/ValueTypes.h 
Message-ID: <200603200020.SAA04683@zion.cs.uiuc.edu>



Changes in directory llvm/include/llvm/CodeGen:

ValueTypes.h updated: 1.24 -> 1.25
---
Log message:

Add another helper


---
Diffs of the changes:  (+13 -0)

 ValueTypes.h |   13 +++++++++++++
 1 files changed, 13 insertions(+)


Index: llvm/include/llvm/CodeGen/ValueTypes.h
diff -u llvm/include/llvm/CodeGen/ValueTypes.h:1.24 llvm/include/llvm/CodeGen/ValueTypes.h:1.25
--- llvm/include/llvm/CodeGen/ValueTypes.h:1.24	Sun Mar 19 17:41:32 2006
+++ llvm/include/llvm/CodeGen/ValueTypes.h	Sun Mar 19 18:20:30 2006
@@ -179,6 +179,19 @@
     }
   }
   
+  /// MVT::getIntVectorWithNumElements - Return any integer vector type that has
+  /// the specified number of elements.
+  static inline ValueType getIntVectorWithNumElements(unsigned NumElts) {
+    switch (NumElts) {
+    default: assert(0 && "Invalid vector type!");
+    case  2: return v2i32;
+    case  4: return v4i16;
+    case  8: return v8i8;
+    case 16: return v16i8;
+    }
+  }
+  
+  
   /// MVT::getIntVTBitMask - Return an integer with 1's every place there are
   /// bits in the specified integer value type.
   static inline uint64_t getIntVTBitMask(ValueType VT) {





From lattner at cs.uiuc.edu  Sun Mar 19 18:56:04 2006
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Sun, 19 Mar 2006 18:56:04 -0600
Subject: [llvm-commits] CVS: llvm/include/llvm/Target/TargetLowering.h 
Message-ID: <200603200056.SAA04846@zion.cs.uiuc.edu>



Changes in directory llvm/include/llvm/Target:

TargetLowering.h updated: 1.61 -> 1.62
---
Log message:

Add some helper methods


---
Diffs of the changes:  (+17 -0)

 TargetLowering.h |   17 +++++++++++++++++
 1 files changed, 17 insertions(+)


Index: llvm/include/llvm/Target/TargetLowering.h
diff -u llvm/include/llvm/Target/TargetLowering.h:1.61 llvm/include/llvm/Target/TargetLowering.h:1.62
--- llvm/include/llvm/Target/TargetLowering.h:1.61	Thu Mar 16 15:47:42 2006
+++ llvm/include/llvm/Target/TargetLowering.h	Sun Mar 19 18:55:52 2006
@@ -195,6 +195,15 @@
     return getOperationAction(Op, VT) == Legal ||
            getOperationAction(Op, VT) == Custom;
   }
+  
+  
+  /// isVectorShuffleLegal - Return true if a vector shuffle is legal with the
+  /// specified mask and type.  Targets can specify exactly which masks they
+  /// support and the code generator is tasked with not creating illegal masks.
+  bool isShuffleLegal(MVT::ValueType VT, SDOperand Mask) const {
+    return isOperationLegal(ISD::VECTOR_SHUFFLE, VT) && 
+           isShuffleMaskLegal(Mask);
+  }
 
   /// getTypeToPromoteTo - If the action for this operation is to promote, this
   /// method returns the ValueType to promote to.
@@ -476,6 +485,14 @@
     TargetDAGCombineArray[NT >> 3] |= 1 << (NT&7);
   }
   
+  /// isShuffleMaskLegal - Targets can use this to indicate that they only
+  /// support *some* VECTOR_SHUFFLE operations, those with specific masks.
+  /// By default, if a target supports the VECTOR_SHUFFLE node, all mask values
+  /// are assumed to be legal.
+  virtual bool isShuffleMaskLegal(SDOperand Mask) const {
+    return true;
+  }
+  
 public:
 
   //===--------------------------------------------------------------------===//





From lattner at cs.uiuc.edu  Sun Mar 19 19:01:09 2006
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Sun, 19 Mar 2006 19:01:09 -0600
Subject: [llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCInstrInfo.td 
Message-ID: <200603200101.TAA04944@zion.cs.uiuc.edu>



Changes in directory llvm/lib/Target/PowerPC:

PPCInstrInfo.td updated: 1.191 -> 1.192
---
Log message:

add the vperm instruction


---
Diffs of the changes:  (+4 -0)

 PPCInstrInfo.td |    4 ++++
 1 files changed, 4 insertions(+)


Index: llvm/lib/Target/PowerPC/PPCInstrInfo.td
diff -u llvm/lib/Target/PowerPC/PPCInstrInfo.td:1.191 llvm/lib/Target/PowerPC/PPCInstrInfo.td:1.192
--- llvm/lib/Target/PowerPC/PPCInstrInfo.td:1.191	Sun Mar 19 00:55:52 2006
+++ llvm/lib/Target/PowerPC/PPCInstrInfo.td	Sun Mar 19 19:00:56 2006
@@ -955,6 +955,10 @@
                                                   VRRC:$vB)))]>,
                        Requires<[FPContractions]>;
 
+def VPERM   : VAForm_1<43, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB, VRRC:$vC),
+                       "vperm $vD, $vA, $vC, $vB", VecFP, []>;
+
+
 // VX-Form instructions.  AltiVec arithmetic ops.
 def VADDFP : VXForm_1<10, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
                       "vaddfp $vD, $vA, $vB", VecFP,





From lattner at cs.uiuc.edu  Sun Mar 19 19:51:58 2006
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Sun, 19 Mar 2006 19:51:58 -0600
Subject: [llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp 
Message-ID: <200603200151.TAA05244@zion.cs.uiuc.edu>



Changes in directory llvm/lib/CodeGen/SelectionDAG:

ScheduleDAG.cpp updated: 1.79 -> 1.80
---
Log message:

TargetData doesn't know the alignment of vectors :(


---
Diffs of the changes:  (+8 -1)

 ScheduleDAG.cpp |    9 ++++++++-
 1 files changed, 8 insertions(+), 1 deletion(-)


Index: llvm/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp:1.79 llvm/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp:1.80
--- llvm/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp:1.79	Fri Mar 10 01:42:02 2006
+++ llvm/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp	Sun Mar 19 19:51:46 2006
@@ -20,6 +20,7 @@
 #include "llvm/Target/TargetMachine.h"
 #include "llvm/Target/TargetInstrInfo.h"
 #include "llvm/Target/TargetLowering.h"
+#include "llvm/Support/MathExtras.h"
 using namespace llvm;
 
 
@@ -124,9 +125,15 @@
     if (Align == 0) {
       if (CP->get()->getType() == Type::DoubleTy)
         Align = 3;  // always 8-byte align doubles.
-      else
+      else {
         Align = TM.getTargetData()
           .getTypeAlignmentShift(CP->get()->getType());
+        if (Align == 0) {
+          // Alignment of packed types.  FIXME!
+          Align = TM.getTargetData().getTypeSize(CP->get()->getType());
+          Align = Log2_64(Align);
+        }
+      }
     }
     
     unsigned Idx = ConstPool->getConstantPoolIndex(CP->get(), Align);





From lattner at cs.uiuc.edu  Sun Mar 19 19:52:41 2006
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Sun, 19 Mar 2006 19:52:41 -0600
Subject: [llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp 
Message-ID: <200603200152.TAA05305@zion.cs.uiuc.edu>



Changes in directory llvm/lib/CodeGen/SelectionDAG:

LegalizeDAG.cpp updated: 1.325 -> 1.326
---
Log message:

If a target supports splatting with SHUFFLE_VECTOR, lower to it from BUILD_VECTOR(x,x,x,x)


---
Diffs of the changes:  (+41 -4)

 LegalizeDAG.cpp |   45 +++++++++++++++++++++++++++++++++++++++++----
 1 files changed, 41 insertions(+), 4 deletions(-)


Index: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.325 llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.326
--- llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.325	Sun Mar 19 00:47:21 2006
+++ llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp	Sun Mar 19 19:52:29 2006
@@ -807,6 +807,21 @@
     }
     }
     break;
+  case ISD::VECTOR_SHUFFLE:
+    assert(TLI.isShuffleLegal(Result.getValueType(), Node->getOperand(2)) &&
+           "vector shuffle should not be created if not legal!");
+    Tmp1 = LegalizeOp(Node->getOperand(0));   // Legalize the input vectors,
+    Tmp2 = LegalizeOp(Node->getOperand(1));   // but not the shuffle mask.
+    Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
+
+    // Allow targets to custom lower the SHUFFLEs they support.
+    if (TLI.getOperationAction(ISD::VECTOR_SHUFFLE, Result.getValueType())
+        == TargetLowering::Custom) {
+      Tmp1 = TLI.LowerOperation(Result, DAG);
+      if (Tmp1.Val) Result = Tmp1;
+    }
+    break;
+    
   case ISD::CALLSEQ_START: {
     SDNode *CallEnd = FindCallEndFromCallStart(Node);
     
@@ -2973,14 +2988,15 @@
 SDOperand SelectionDAGLegalize::ExpandBUILD_VECTOR(SDNode *Node) {
   
   // If the only non-undef value is the low element, turn this into a 
-  // SCALAR_TO_VECTOR node.
+  // SCALAR_TO_VECTOR node.  If this is { X, X, X, X }, determine X.
   bool isOnlyLowElement = true;
+  SDOperand SplatValue = Node->getOperand(0);
   for (SDNode::op_iterator I = Node->op_begin()+1, E = Node->op_end();
        I != E; ++I) {
-    if (I->getOpcode() != ISD::UNDEF) {
+    if (I->getOpcode() != ISD::UNDEF)
       isOnlyLowElement = false;
-      break;
-    }
+    if (SplatValue != *I)
+      SplatValue = SDOperand(0,0);
   }
   
   if (isOnlyLowElement) {
@@ -2992,6 +3008,27 @@
                        Node->getOperand(0));
   }
   
+  if (SplatValue.Val) {   // Splat of one value?
+    // Build the shuffle constant vector: <0, 0, 0, 0>
+    MVT::ValueType MaskVT = 
+      MVT::getIntVectorWithNumElements(Node->getNumOperands());
+    SDOperand Zero = DAG.getConstant(0, MVT::getVectorBaseType(MaskVT));
+    std::vector ZeroVec(Node->getNumOperands(), Zero);
+    SDOperand SplatMask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT, ZeroVec);
+
+    // If the target supports VECTOR_SHUFFLE and this shuffle mask, use it.
+    if (TLI.isShuffleLegal(Node->getValueType(0), SplatMask)) {
+      // Get the splatted value into the low element of a vector register.
+      SDOperand LowValVec = 
+        DAG.getNode(ISD::SCALAR_TO_VECTOR, Node->getValueType(0), SplatValue);
+    
+      // Return shuffle(LowValVec, undef, <0,0,0,0>)
+      return DAG.getNode(ISD::VECTOR_SHUFFLE, Node->getValueType(0), LowValVec,
+                         DAG.getNode(ISD::UNDEF, Node->getValueType(0)),
+                         SplatMask);
+    }
+  }
+  
   // If the elements are all constants, turn this into a load from the constant
   // pool.
   bool isConstant = true;





From lattner at cs.uiuc.edu  Sun Mar 19 19:53:14 2006
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Sun, 19 Mar 2006 19:53:14 -0600
Subject: [llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCRegisterInfo.td 
Message-ID: <200603200153.TAA05360@zion.cs.uiuc.edu>



Changes in directory llvm/lib/Target/PowerPC:

PPCRegisterInfo.td updated: 1.30 -> 1.31
---
Log message:

Claim to have v16i8 for perm masks



---
Diffs of the changes:  (+2 -1)

 PPCRegisterInfo.td |    3 ++-
 1 files changed, 2 insertions(+), 1 deletion(-)


Index: llvm/lib/Target/PowerPC/PPCRegisterInfo.td
diff -u llvm/lib/Target/PowerPC/PPCRegisterInfo.td:1.30 llvm/lib/Target/PowerPC/PPCRegisterInfo.td:1.31
--- llvm/lib/Target/PowerPC/PPCRegisterInfo.td:1.30	Mon Mar 13 15:52:10 2006
+++ llvm/lib/Target/PowerPC/PPCRegisterInfo.td	Sun Mar 19 19:53:02 2006
@@ -191,7 +191,8 @@
   F8, F9, F10, F11, F12, F13, F14, F15, F16, F17, F18, F19, F20, F21,
   F22, F23, F24, F25, F26, F27, F28, F29, F30, F31]>;
 
-def VRRC : RegisterClass<"PPC", [v4f32,v4i32], 128, [V0, V1, V2, V3, V4, V5,
+def VRRC : RegisterClass<"PPC", [v16i8,v4f32,v4i32], 128,
+ [V0, V1, V2, V3, V4, V5,
   V6, V7, V8, V9, V10, V11, V12, V13, V14, V15, V16, V17, V18, V19, V20, V21,
   V22, V23, V24, V25, V26, V27, V28, V29, V30, V31]>;
 





From lattner at cs.uiuc.edu  Sun Mar 19 19:54:05 2006
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Sun, 19 Mar 2006 19:54:05 -0600
Subject: [llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCISelLowering.cpp
	PPCISelLowering.h PPCInstrInfo.td 
Message-ID: <200603200154.TAA05397@zion.cs.uiuc.edu>



Changes in directory llvm/lib/Target/PowerPC:

PPCISelLowering.cpp updated: 1.100 -> 1.101
PPCISelLowering.h updated: 1.27 -> 1.28
PPCInstrInfo.td updated: 1.192 -> 1.193
---
Log message:

Custom lower arbitrary VECTOR_SHUFFLE's to VPERM.
TODO: leave specific ones as VECTOR_SHUFFLE's and turn them into specialized
operations like vsplt*


---
Diffs of the changes:  (+60 -15)

 PPCISelLowering.cpp |   46 +++++++++++++++++++++++++++++++++++++++++-----
 PPCISelLowering.h   |    4 ++++
 PPCInstrInfo.td     |   25 +++++++++++++++----------
 3 files changed, 60 insertions(+), 15 deletions(-)


Index: llvm/lib/Target/PowerPC/PPCISelLowering.cpp
diff -u llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.100 llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.101
--- llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.100	Sun Mar 19 00:55:52 2006
+++ llvm/lib/Target/PowerPC/PPCISelLowering.cpp	Sun Mar 19 19:53:53 2006
@@ -167,6 +167,11 @@
     setOperationAction(ISD::SUB , (MVT::ValueType)VT, Expand);
     setOperationAction(ISD::MUL , (MVT::ValueType)VT, Expand);
     setOperationAction(ISD::LOAD, (MVT::ValueType)VT, Expand);
+    setOperationAction(ISD::VECTOR_SHUFFLE, (MVT::ValueType)VT, Expand);
+    
+    // FIXME: We don't support any BUILD_VECTOR's yet.  We should custom expand
+    // the ones we do, like splat(0.0) and splat(-0.0).
+    setOperationAction(ISD::BUILD_VECTOR, (MVT::ValueType)VT, Expand);
   }
 
   if (TM.getSubtarget().hasAltivec()) {
@@ -179,11 +184,11 @@
     setOperationAction(ISD::LOAD       , MVT::v4f32, Legal);
     setOperationAction(ISD::ADD        , MVT::v4i32, Legal);
     setOperationAction(ISD::LOAD       , MVT::v4i32, Legal);
-    // FIXME: We don't support any BUILD_VECTOR's yet.  We should custom expand
-    // the ones we do!
-    setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Expand);
-    setOperationAction(ISD::BUILD_VECTOR, MVT::v4i32, Expand);
-    
+    setOperationAction(ISD::LOAD       , MVT::v16i8, Legal);
+
+    setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4i32, Custom);
+    setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4f32, Custom);
+
     setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4f32, Custom);
     setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i32, Custom);
   }
@@ -209,6 +214,7 @@
   case PPCISD::VMADDFP:       return "PPCISD::VMADDFP";
   case PPCISD::VNMSUBFP:      return "PPCISD::VNMSUBFP";
   case PPCISD::LVE_X:         return "PPCISD::LVE_X";
+  case PPCISD::VPERM:         return "PPCISD::VPERM";
   case PPCISD::Hi:            return "PPCISD::Hi";
   case PPCISD::Lo:            return "PPCISD::Lo";
   case PPCISD::GlobalBaseReg: return "PPCISD::GlobalBaseReg";
@@ -566,6 +572,36 @@
     return DAG.getNode(PPCISD::LVE_X, Op.getValueType(), Store, FIdx, 
                        DAG.getSrcValue(NULL));
   }
+  case ISD::VECTOR_SHUFFLE: {
+    // FIXME: Cases that are handled by instructions that take permute
+    // immediates (such as vsplt*) shouldn't be lowered here!  Also handle cases
+    // that are cheaper to do as multiple such instructions than as a constant
+    // pool load/vperm pair.
+    
+    // Lower this to a VPERM(V1, V2, V3) expression, where V3 is a constant
+    // vector that will get spilled to the constant pool.
+    SDOperand V1 = Op.getOperand(0);
+    SDOperand V2 = Op.getOperand(1);
+    if (V2.getOpcode() == ISD::UNDEF) V2 = V1;
+    SDOperand PermMask = Op.getOperand(2);
+    
+    // The SHUFFLE_VECTOR mask is almost exactly what we want for vperm, except
+    // that it is in input element units, not in bytes.  Convert now.
+    MVT::ValueType EltVT = MVT::getVectorBaseType(V1.getValueType());
+    unsigned BytesPerElement = MVT::getSizeInBits(EltVT)/8;
+    
+    std::vector ResultMask;
+    for (unsigned i = 0, e = PermMask.getNumOperands(); i != e; ++i) {
+      unsigned SrcElt =cast(PermMask.getOperand(i))->getValue();
+      
+      for (unsigned j = 0; j != BytesPerElement; ++j)
+        ResultMask.push_back(DAG.getConstant(SrcElt*BytesPerElement+j,
+                                             MVT::i8));
+    }
+    
+    SDOperand VPermMask =DAG.getNode(ISD::BUILD_VECTOR, MVT::v16i8, ResultMask);
+    return DAG.getNode(PPCISD::VPERM, V1.getValueType(), V1, V2, VPermMask);
+  }
   }
   return SDOperand();
 }


Index: llvm/lib/Target/PowerPC/PPCISelLowering.h
diff -u llvm/lib/Target/PowerPC/PPCISelLowering.h:1.27 llvm/lib/Target/PowerPC/PPCISelLowering.h:1.28
--- llvm/lib/Target/PowerPC/PPCISelLowering.h:1.27	Sun Mar 19 00:55:52 2006
+++ llvm/lib/Target/PowerPC/PPCISelLowering.h	Sun Mar 19 19:53:53 2006
@@ -56,6 +56,10 @@
       /// the third is the SRCVALUE node.
       LVE_X,
       
+      /// VPERM - The PPC VPERM Instruction.
+      ///
+      VPERM,
+      
       /// Hi/Lo - These represent the high and low 16-bit parts of a global
       /// address respectively.  These nodes have two operands, the first of
       /// which must be a TargetGlobalAddress, and the second of which must be a


Index: llvm/lib/Target/PowerPC/PPCInstrInfo.td
diff -u llvm/lib/Target/PowerPC/PPCInstrInfo.td:1.192 llvm/lib/Target/PowerPC/PPCInstrInfo.td:1.193
--- llvm/lib/Target/PowerPC/PPCInstrInfo.td:1.192	Sun Mar 19 19:00:56 2006
+++ llvm/lib/Target/PowerPC/PPCInstrInfo.td	Sun Mar 19 19:53:53 2006
@@ -26,6 +26,10 @@
 def SDT_PPCCallSeq : SDTypeProfile<0, 1, [ SDTCisVT<0, i32> ]>;
 def SDT_PPCRetFlag : SDTypeProfile<0, 0, []>;
 
+def SDT_PPCvperm   : SDTypeProfile<1, 3, [
+  SDTCisVT<3, v16i8>, SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>
+]>;
+
 //===----------------------------------------------------------------------===//
 // PowerPC specific DAG Nodes.
 //
@@ -46,6 +50,7 @@
 def PPCvnmsubfp : SDNode<"PPCISD::VNMSUBFP", SDTFPTernaryOp, []>;
 
 def PPClve_x    : SDNode<"PPCISD::LVE_X", SDTLoad, [SDNPHasChain]>;
+def PPCvperm    : SDNode<"PPCISD::VPERM", SDT_PPCvperm, []>;
 
 // These nodes represent the 32-bit PPC shifts that operate on 6-bit shift
 // amounts.  These nodes are generated by the multi-precision shift code.
@@ -118,15 +123,6 @@
   return ((unsigned)N->getValue() & 0xFFFF0000U) == (unsigned)N->getValue();
 }], HI16>;
 
-/*
-// Example of a legalize expander: Only for PPC64.
-def : Expander<(set i64:$dst, (fp_to_sint f64:$src)),
-               [(set f64:$tmp , (FCTIDZ f64:$src)),
-                (set i32:$tmpFI, (CreateNewFrameIndex 8, 8)),
-                (store f64:$tmp, i32:$tmpFI),
-                (set i64:$dst, (load i32:$tmpFI))],
-                Subtarget_PPC64>;
-*/
 
 //===----------------------------------------------------------------------===//
 // PowerPC Flag Definitions.
@@ -956,7 +952,9 @@
                        Requires<[FPContractions]>;
 
 def VPERM   : VAForm_1<43, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB, VRRC:$vC),
-                       "vperm $vD, $vA, $vC, $vB", VecFP, []>;
+                       "vperm $vD, $vA, $vC, $vB", VecFP,
+                       [(set VRRC:$vD,
+                             (PPCvperm (v4f32 VRRC:$vA), VRRC:$vB, VRRC:$vC))]>;
 
 
 // VX-Form instructions.  AltiVec arithmetic ops.
@@ -1153,6 +1151,13 @@
 
 def : Pat<(v4i32 (load xoaddr:$src)),
           (v4i32 (LVX xoaddr:$src))>;
+def : Pat<(v16i8 (load xoaddr:$src)),
+          (v16i8 (LVX xoaddr:$src))>;
+
+
+def : Pat<(PPCvperm (v4i32 VRRC:$vA), VRRC:$vB, VRRC:$vC),
+          (v4i32 (VPERM VRRC:$vA, VRRC:$vB, VRRC:$vC))>;
+
 def : Pat<(store (v4i32 VRRC:$rS), xoaddr:$dst),
           (STVX (v4i32 VRRC:$rS), xoaddr:$dst)>;
 def : Pat<(v4i32 (PPClve_x xoaddr:$src)),





From lattner at cs.uiuc.edu  Sun Mar 19 22:47:44 2006
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Sun, 19 Mar 2006 22:47:44 -0600
Subject: [llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCInstrInfo.td 
Message-ID: <200603200447.WAA06341@zion.cs.uiuc.edu>



Changes in directory llvm/lib/Target/PowerPC:

PPCInstrInfo.td updated: 1.193 -> 1.194
---
Log message:

add vsplat instructions, fix sched description for vperm


---
Diffs of the changes:  (+11 -1)

 PPCInstrInfo.td |   12 +++++++++++-
 1 files changed, 11 insertions(+), 1 deletion(-)


Index: llvm/lib/Target/PowerPC/PPCInstrInfo.td
diff -u llvm/lib/Target/PowerPC/PPCInstrInfo.td:1.193 llvm/lib/Target/PowerPC/PPCInstrInfo.td:1.194
--- llvm/lib/Target/PowerPC/PPCInstrInfo.td:1.193	Sun Mar 19 19:53:53 2006
+++ llvm/lib/Target/PowerPC/PPCInstrInfo.td	Sun Mar 19 22:47:33 2006
@@ -952,7 +952,7 @@
                        Requires<[FPContractions]>;
 
 def VPERM   : VAForm_1<43, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB, VRRC:$vC),
-                       "vperm $vD, $vA, $vC, $vB", VecFP,
+                       "vperm $vD, $vA, $vC, $vB", VecPerm,
                        [(set VRRC:$vD,
                              (PPCvperm (v4f32 VRRC:$vA), VRRC:$vB, VRRC:$vC))]>;
 
@@ -1015,6 +1015,16 @@
 def VXOR : VXForm_1<1220, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
                       "vxor $vD, $vA, $vB", VecFP,
                       []>;
+
+def VSPLTB : VFForm_1<524, (ops VRRC:$vD, u5imm:$UIMM, VRRC:$vB),
+                      "vspltb $vD, $vB, $UIMM", VecPerm,
+                      []>;
+def VSPLTH : VFForm_1<588, (ops VRRC:$vD, u5imm:$UIMM, VRRC:$vB),
+                      "vsplth $vD, $vB, $UIMM", VecPerm,
+                      []>;
+def VSPLTW : VFForm_1<652, (ops VRRC:$vD, u5imm:$UIMM, VRRC:$vB),
+                      "vspltw $vD, $vB, $UIMM", VecPerm,
+                      []>;
                       
 // VX-Form Pseudo Instructions
 





From lattner at cs.uiuc.edu  Sun Mar 19 23:06:07 2006
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Sun, 19 Mar 2006 23:06:07 -0600
Subject: [llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCInstrInfo.td 
Message-ID: <200603200506.XAA06482@zion.cs.uiuc.edu>



Changes in directory llvm/lib/Target/PowerPC:

PPCInstrInfo.td updated: 1.194 -> 1.195
---
Log message:

fix typo


---
Diffs of the changes:  (+3 -3)

 PPCInstrInfo.td |    6 +++---
 1 files changed, 3 insertions(+), 3 deletions(-)


Index: llvm/lib/Target/PowerPC/PPCInstrInfo.td
diff -u llvm/lib/Target/PowerPC/PPCInstrInfo.td:1.194 llvm/lib/Target/PowerPC/PPCInstrInfo.td:1.195
--- llvm/lib/Target/PowerPC/PPCInstrInfo.td:1.194	Sun Mar 19 22:47:33 2006
+++ llvm/lib/Target/PowerPC/PPCInstrInfo.td	Sun Mar 19 23:05:55 2006
@@ -1016,13 +1016,13 @@
                       "vxor $vD, $vA, $vB", VecFP,
                       []>;
 
-def VSPLTB : VFForm_1<524, (ops VRRC:$vD, u5imm:$UIMM, VRRC:$vB),
+def VSPLTB : VXForm_1<524, (ops VRRC:$vD, u5imm:$UIMM, VRRC:$vB),
                       "vspltb $vD, $vB, $UIMM", VecPerm,
                       []>;
-def VSPLTH : VFForm_1<588, (ops VRRC:$vD, u5imm:$UIMM, VRRC:$vB),
+def VSPLTH : VXForm_1<588, (ops VRRC:$vD, u5imm:$UIMM, VRRC:$vB),
                       "vsplth $vD, $vB, $UIMM", VecPerm,
                       []>;
-def VSPLTW : VFForm_1<652, (ops VRRC:$vD, u5imm:$UIMM, VRRC:$vB),
+def VSPLTW : VXForm_1<652, (ops VRRC:$vD, u5imm:$UIMM, VRRC:$vB),
                       "vspltw $vD, $vB, $UIMM", VecPerm,
                       []>;
                       





From lattner at cs.uiuc.edu  Sun Mar 19 23:39:59 2006
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Sun, 19 Mar 2006 23:39:59 -0600
Subject: [llvm-commits] CVS: llvm/utils/TableGen/DAGISelEmitter.cpp
	DAGISelEmitter.h 
Message-ID: <200603200539.XAA06666@zion.cs.uiuc.edu>



Changes in directory llvm/utils/TableGen:

DAGISelEmitter.cpp updated: 1.176 -> 1.177
DAGISelEmitter.h updated: 1.57 -> 1.58
---
Log message:

Add a new SDTCisIntVectorOfSameSize type constraint


---
Diffs of the changes:  (+23 -3)

 DAGISelEmitter.cpp |   21 +++++++++++++++++++--
 DAGISelEmitter.h   |    5 ++++-
 2 files changed, 23 insertions(+), 3 deletions(-)


Index: llvm/utils/TableGen/DAGISelEmitter.cpp
diff -u llvm/utils/TableGen/DAGISelEmitter.cpp:1.176 llvm/utils/TableGen/DAGISelEmitter.cpp:1.177
--- llvm/utils/TableGen/DAGISelEmitter.cpp:1.176	Thu Mar  9 02:19:11 2006
+++ llvm/utils/TableGen/DAGISelEmitter.cpp	Sun Mar 19 23:39:47 2006
@@ -63,14 +63,14 @@
 
 /// isExtIntegerVT - Return true if the specified extended value type vector
 /// contains isInt or an integer value type.
-static bool isExtIntegerInVTs(std::vector EVTs) {
+static bool isExtIntegerInVTs(const std::vector &EVTs) {
   assert(!EVTs.empty() && "Cannot check for integer in empty ExtVT list!");
   return EVTs[0] == MVT::isInt || !(FilterEVTs(EVTs, MVT::isInteger).empty());
 }
 
 /// isExtFloatingPointVT - Return true if the specified extended value type 
 /// vector contains isFP or a FP value type.
-static bool isExtFloatingPointInVTs(std::vector EVTs) {
+static bool isExtFloatingPointInVTs(const std::vector &EVTs) {
   assert(!EVTs.empty() && "Cannot check for integer in empty ExtVT list!");
   return EVTs[0] == MVT::isFP ||
          !(FilterEVTs(EVTs, MVT::isFloatingPoint).empty());
@@ -103,6 +103,10 @@
     ConstraintType = SDTCisOpSmallerThanOp;
     x.SDTCisOpSmallerThanOp_Info.BigOperandNum = 
       R->getValueAsInt("BigOperandNum");
+  } else if (R->isSubClassOf("SDTCisIntVectorOfSameSize")) {
+    ConstraintType = SDTCisIntVectorOfSameSize;
+    x.SDTCisIntVectorOfSameSize_Info.OtherOperandNum =
+      R->getValueAsInt("OtherOpNum");
   } else {
     std::cerr << "Unrecognized SDTypeConstraint '" << R->getName() << "'!\n";
     exit(1);
@@ -259,6 +263,19 @@
     }    
     return MadeChange;
   }
+  case SDTCisIntVectorOfSameSize: {
+    TreePatternNode *OtherOperand =
+      getOperandNum(x.SDTCisIntVectorOfSameSize_Info.OtherOperandNum,
+                    N, NumResults);
+    if (OtherOperand->hasTypeSet()) {
+      if (!MVT::isVector(OtherOperand->getTypeNum(0)))
+        TP.error(N->getOperator()->getName() + " VT operand must be a vector!");
+      MVT::ValueType IVT = OtherOperand->getTypeNum(0);
+      IVT = MVT::getIntVectorWithNumElements(MVT::getVectorNumElements(IVT));
+      return NodeToApply->UpdateNodeType(IVT, TP);
+    }
+    return false;
+  }
   }  
   return false;
 }


Index: llvm/utils/TableGen/DAGISelEmitter.h
diff -u llvm/utils/TableGen/DAGISelEmitter.h:1.57 llvm/utils/TableGen/DAGISelEmitter.h:1.58
--- llvm/utils/TableGen/DAGISelEmitter.h:1.57	Thu Feb  9 01:16:09 2006
+++ llvm/utils/TableGen/DAGISelEmitter.h	Sun Mar 19 23:39:48 2006
@@ -47,7 +47,7 @@
     unsigned OperandNo;   // The operand # this constraint applies to.
     enum { 
       SDTCisVT, SDTCisPtrTy, SDTCisInt, SDTCisFP, SDTCisSameAs, 
-      SDTCisVTSmallerThanOp, SDTCisOpSmallerThanOp
+      SDTCisVTSmallerThanOp, SDTCisOpSmallerThanOp, SDTCisIntVectorOfSameSize
     } ConstraintType;
     
     union {   // The discriminated union.
@@ -63,6 +63,9 @@
       struct {
         unsigned BigOperandNum;
       } SDTCisOpSmallerThanOp_Info;
+      struct {
+        unsigned OtherOperandNum;
+      } SDTCisIntVectorOfSameSize_Info;
     } x;
 
     /// ApplyTypeConstraint - Given a node in a pattern, apply this type





From lattner at cs.uiuc.edu  Sun Mar 19 23:40:57 2006
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Sun, 19 Mar 2006 23:40:57 -0600
Subject: [llvm-commits] CVS: llvm/lib/Target/TargetSelectionDAG.td 
Message-ID: <200603200540.XAA06726@zion.cs.uiuc.edu>



Changes in directory llvm/lib/Target:

TargetSelectionDAG.td updated: 1.52 -> 1.53
---
Log message:

add vector_shuffle


---
Diffs of the changes:  (+16 -0)

 TargetSelectionDAG.td |   16 ++++++++++++++++
 1 files changed, 16 insertions(+)


Index: llvm/lib/Target/TargetSelectionDAG.td
diff -u llvm/lib/Target/TargetSelectionDAG.td:1.52 llvm/lib/Target/TargetSelectionDAG.td:1.53
--- llvm/lib/Target/TargetSelectionDAG.td:1.52	Wed Mar 15 19:29:53 2006
+++ llvm/lib/Target/TargetSelectionDAG.td	Sun Mar 19 23:40:45 2006
@@ -51,6 +51,15 @@
   int BigOperandNum = BigOp;
 }
 
+/// SDTCisIntVectorOfSameSize - This indicates that ThisOp and OtherOp are
+/// packed vector types, and that ThisOp is the result of 
+/// MVT::getIntVectorWithNumElements with the number of elements that ThisOp
+/// has.
+class SDTCisIntVectorOfSameSize
+  : SDTypeConstraint {
+  int OtherOpNum = OtherOp;
+}
+
 //===----------------------------------------------------------------------===//
 // Selection DAG Type Profile definitions.
 //
@@ -161,6 +170,10 @@
   SDTCisPtrTy<1>, SDTCisVT<2, OtherVT>, SDTCisVT<3, OtherVT>
 ]>;
 
+def SDTVecShuffle : SDTypeProfile<1, 3, [
+  SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>, SDTCisIntVectorOfSameSize<3, 0>
+]>;
+
 //===----------------------------------------------------------------------===//
 // Selection DAG Node Properties.
 //
@@ -293,6 +306,9 @@
 def extld      : SDNode<"ISD::EXTLOAD"    , SDTExtLoad,    [SDNPHasChain]>;
 def truncst    : SDNode<"ISD::TRUNCSTORE" , SDTTruncStore, [SDNPHasChain]>;
 
+def vector_shuffle : SDNode<"ISD::VECTOR_SHUFFLE", SDTVecShuffle, []>;
+
+
 //===----------------------------------------------------------------------===//
 // Selection DAG Condition Codes