From evan.cheng at apple.com Mon Mar 20 00:04:21 2006 From: evan.cheng at apple.com (Evan Cheng) Date: Mon, 20 Mar 2006 00:04:21 -0600 Subject: [llvm-commits] CVS: llvm/utils/TableGen/DAGISelEmitter.cpp DAGISelEmitter.h Message-ID: <200603200604.AAA06889@zion.cs.uiuc.edu> Changes in directory llvm/utils/TableGen: DAGISelEmitter.cpp updated: 1.177 -> 1.178 DAGISelEmitter.h updated: 1.58 -> 1.59 --- Log message: Copy matching pattern's output type info to instruction result pattern. The instruction patterns do not contain enough information to resolve the exact type of the destination if it of a generic vector type. --- Diffs of the changes: (+14 -6) DAGISelEmitter.cpp | 17 ++++++++++++----- DAGISelEmitter.h | 3 ++- 2 files changed, 14 insertions(+), 6 deletions(-) Index: llvm/utils/TableGen/DAGISelEmitter.cpp diff -u llvm/utils/TableGen/DAGISelEmitter.cpp:1.177 llvm/utils/TableGen/DAGISelEmitter.cpp:1.178 --- llvm/utils/TableGen/DAGISelEmitter.cpp:1.177 Sun Mar 19 23:39:47 2006 +++ llvm/utils/TableGen/DAGISelEmitter.cpp Mon Mar 20 00:04:09 2006 @@ -1105,7 +1105,7 @@ void DAGISelEmitter:: FindPatternInputsAndOutputs(TreePattern *I, TreePatternNode *Pat, std::map &InstInputs, - std::map &InstResults, + std::map &InstResults, std::vector &InstImpInputs, std::vector &InstImpResults) { if (Pat->isLeaf()) { @@ -1159,7 +1159,7 @@ I->error("set destination must have a name!"); if (InstResults.count(Dest->getName())) I->error("cannot set '" + Dest->getName() +"' multiple times"); - InstResults[Dest->getName()] = Val->getDef(); + InstResults[Dest->getName()] = Dest; } else if (Val->getDef()->isSubClassOf("Register")) { InstImpResults.push_back(Val->getDef()); } else { @@ -1235,7 +1235,7 @@ // InstResults - Keep track of all the virtual registers that are 'set' // in the instruction, including what reg class they are. - std::map InstResults; + std::map InstResults; std::vector InstImpInputs; std::vector InstImpResults; @@ -1265,6 +1265,7 @@ // Check that all of the results occur first in the list. std::vector Results; + TreePatternNode *Res0Node = NULL; for (unsigned i = 0; i != NumResults; ++i) { if (i == CGI.OperandList.size()) I->error("'" + InstResults.begin()->first + @@ -1272,7 +1273,10 @@ const std::string &OpName = CGI.OperandList[i].Name; // Check that it exists in InstResults. - Record *R = InstResults[OpName]; + TreePatternNode *RNode = InstResults[OpName]; + if (i == 0) + Res0Node = RNode; + Record *R = dynamic_cast(RNode->getLeafValue())->getDef(); if (R == 0) I->error("Operand $" + OpName + " should be a set destination: all " "outputs must occur before inputs in operand list!"); @@ -1337,6 +1341,9 @@ TreePatternNode *ResultPattern = new TreePatternNode(I->getRecord(), ResultNodeOperands); + // Copy fully inferred output node type to instruction result pattern. + if (NumResults > 0) + ResultPattern->setTypes(Res0Node->getExtTypes()); // Create and insert the instruction. DAGInstruction TheInst(I, Results, Operands, InstImpResults, InstImpInputs); @@ -1407,7 +1414,7 @@ // Validate that the input pattern is correct. { std::map InstInputs; - std::map InstResults; + std::map InstResults; std::vector InstImpInputs; std::vector InstImpResults; FindPatternInputsAndOutputs(Pattern, Pattern->getOnlyTree(), Index: llvm/utils/TableGen/DAGISelEmitter.h diff -u llvm/utils/TableGen/DAGISelEmitter.h:1.58 llvm/utils/TableGen/DAGISelEmitter.h:1.59 --- llvm/utils/TableGen/DAGISelEmitter.h:1.58 Sun Mar 19 23:39:48 2006 +++ llvm/utils/TableGen/DAGISelEmitter.h Mon Mar 20 00:04:09 2006 @@ -469,7 +469,8 @@ void FindPatternInputsAndOutputs(TreePattern *I, TreePatternNode *Pat, std::map &InstInputs, - std::map &InstResults, + std::map &InstResults, std::vector &InstImpInputs, std::vector &InstImpResults); void GenerateCodeForPattern(PatternToMatch &Pattern, From evan.cheng at apple.com Mon Mar 20 00:05:04 2006 From: evan.cheng at apple.com (Evan Cheng) Date: Mon, 20 Mar 2006 00:05:04 -0600 Subject: [llvm-commits] CVS: llvm/lib/Target/X86/X86InstrMMX.td X86InstrSSE.td Message-ID: <200603200605.AAA06917@zion.cs.uiuc.edu> Changes in directory llvm/lib/Target/X86: X86InstrMMX.td updated: 1.2 -> 1.3 X86InstrSSE.td updated: 1.8 -> 1.9 --- Log message: Move a few things around. --- Diffs of the changes: (+14 -13) X86InstrMMX.td | 10 ++++++++++ X86InstrSSE.td | 17 ++++------------- 2 files changed, 14 insertions(+), 13 deletions(-) Index: llvm/lib/Target/X86/X86InstrMMX.td diff -u llvm/lib/Target/X86/X86InstrMMX.td:1.2 llvm/lib/Target/X86/X86InstrMMX.td:1.3 --- llvm/lib/Target/X86/X86InstrMMX.td:1.2 Tue Feb 21 14:00:20 2006 +++ llvm/lib/Target/X86/X86InstrMMX.td Mon Mar 20 00:04:52 2006 @@ -13,6 +13,15 @@ // //===----------------------------------------------------------------------===// +// Some 'special' instructions +def IMPLICIT_DEF_VR64 : I<0, Pseudo, (ops VR64:$dst), + "#IMPLICIT_DEF $dst", + [(set VR64:$dst, (v8i8 (undef)))]>, + Requires<[HasMMX]>; + +def : Pat<(v4i16 (undef)), (IMPLICIT_DEF_VR64)>, Requires<[HasMMX]>; +def : Pat<(v2i32 (undef)), (IMPLICIT_DEF_VR64)>, Requires<[HasMMX]>; + // Move Instructions def MOVD64rr : I<0x6E, MRMSrcReg, (ops VR64:$dst, R32:$src), "movd {$src, $dst|$dst, $src}", []>, TB, @@ -33,3 +42,4 @@ def MOVQ64mr : I<0x7F, MRMDestMem, (ops i64mem:$dst, VR64:$src), "movq {$src, $dst|$dst, $src}", []>, TB, Requires<[HasMMX]>; + Index: llvm/lib/Target/X86/X86InstrSSE.td diff -u llvm/lib/Target/X86/X86InstrSSE.td:1.8 llvm/lib/Target/X86/X86InstrSSE.td:1.9 --- llvm/lib/Target/X86/X86InstrSSE.td:1.8 Sun Mar 19 03:38:54 2006 +++ llvm/lib/Target/X86/X86InstrSSE.td Mon Mar 20 00:04:52 2006 @@ -348,6 +348,10 @@ Requires<[HasSSE1]>; def : Pat<(v2f64 (undef)), (IMPLICIT_DEF_VR128)>, Requires<[HasSSE2]>; +def : Pat<(v16i8 (undef)), (IMPLICIT_DEF_VR128)>, Requires<[HasSSE2]>; +def : Pat<(v8i16 (undef)), (IMPLICIT_DEF_VR128)>, Requires<[HasSSE2]>; +def : Pat<(v4i32 (undef)), (IMPLICIT_DEF_VR128)>, Requires<[HasSSE2]>; +def : Pat<(v2i64 (undef)), (IMPLICIT_DEF_VR128)>, Requires<[HasSSE2]>; // Move Instructions def MOVAPSrr : PSI<0x28, MRMSrcReg, (ops VR128:$dst, VR128:$src), @@ -694,19 +698,6 @@ // SSE integer instructions //===----------------------------------------------------------------------===// -// Some 'special' instructions -def IMPLICIT_DEF_VR64 : I<0, Pseudo, (ops VR64:$dst), - "#IMPLICIT_DEF $dst", - [(set VR64:$dst, (v8i8 (undef)))]>, - Requires<[HasMMX]>; - -def : Pat<(v4i16 (undef)), (IMPLICIT_DEF_VR64)>, Requires<[HasMMX]>; -def : Pat<(v2i32 (undef)), (IMPLICIT_DEF_VR64)>, Requires<[HasMMX]>; -def : Pat<(v16i8 (undef)), (IMPLICIT_DEF_VR128)>, Requires<[HasSSE2]>; -def : Pat<(v8i16 (undef)), (IMPLICIT_DEF_VR128)>, Requires<[HasSSE2]>; -def : Pat<(v4i32 (undef)), (IMPLICIT_DEF_VR128)>, Requires<[HasSSE2]>; -def : Pat<(v2i64 (undef)), (IMPLICIT_DEF_VR128)>, Requires<[HasSSE2]>; - // Move Instructions def MOVD128rr : PDI<0x6E, MRMSrcReg, (ops VR128:$dst, R32:$src), "movd {$src, $dst|$dst, $src}", []>; From lattner at cs.uiuc.edu Mon Mar 20 00:15:57 2006 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Mon, 20 Mar 2006 00:15:57 -0600 Subject: [llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCISelLowering.h PPCInstrInfo.td Message-ID: <200603200615.AAA07020@zion.cs.uiuc.edu> Changes in directory llvm/lib/Target/PowerPC: PPCISelLowering.h updated: 1.28 -> 1.29 PPCInstrInfo.td updated: 1.195 -> 1.196 --- Log message: Check in some intermediate code that adds a skeleton for matching vsplt* instructions --- Diffs of the changes: (+28 -4) PPCISelLowering.h | 14 +++++++++++++- PPCInstrInfo.td | 18 +++++++++++++++--- 2 files changed, 28 insertions(+), 4 deletions(-) Index: llvm/lib/Target/PowerPC/PPCISelLowering.h diff -u llvm/lib/Target/PowerPC/PPCISelLowering.h:1.28 llvm/lib/Target/PowerPC/PPCISelLowering.h:1.29 --- llvm/lib/Target/PowerPC/PPCISelLowering.h:1.28 Sun Mar 19 19:53:53 2006 +++ llvm/lib/Target/PowerPC/PPCISelLowering.h Mon Mar 20 00:15:45 2006 @@ -82,7 +82,19 @@ /// Return with a flag operand, matched by 'blr' RET_FLAG, }; - } + } + + /// Define some predicates that are used for node matching. + namespace PPC { + /// isSplatShuffleMask - Return true if the specified VECTOR_SHUFFLE operand + /// specifies a splat of a single element that is suitable for input to + /// VSPLTB/VSPLTH/VSPLTW. + bool isSplatShuffleMask(SDNode *N) { return false; } // FIXME: + + /// getVSPLTImmediate - Return the appropriate VSPLT* immediate to splat the + /// specified isSplatShuffleMask VECTOR_SHUFFLE mask. + unsigned getVSPLTImmediate(SDNode *N) { return 0; } // FIXME: + } class PPCTargetLowering : public TargetLowering { int VarArgsFrameIndex; // FrameIndex for start of varargs area. Index: llvm/lib/Target/PowerPC/PPCInstrInfo.td diff -u llvm/lib/Target/PowerPC/PPCInstrInfo.td:1.195 llvm/lib/Target/PowerPC/PPCInstrInfo.td:1.196 --- llvm/lib/Target/PowerPC/PPCInstrInfo.td:1.195 Sun Mar 19 23:05:55 2006 +++ llvm/lib/Target/PowerPC/PPCInstrInfo.td Mon Mar 20 00:15:45 2006 @@ -123,6 +123,14 @@ return ((unsigned)N->getValue() & 0xFFFF0000U) == (unsigned)N->getValue(); }], HI16>; +// VSPLT_get_imm xform function: convert vector_shuffle mask to VSPLT* imm. +def VSPLT_get_imm : SDNodeXForm; + +def VSPLT_shuffle_mask : PatLeaf<(build_vector), [{ + return PPC::isSplatShuffleMask(N); +}], VSPLT_get_imm>; //===----------------------------------------------------------------------===// // PowerPC Flag Definitions. @@ -937,6 +945,7 @@ []>, isPPC64; } + let PPC970_Unit = 5 in { // VALU Operations. // VA-Form instructions. 3-input AltiVec ops. def VMADDFP : VAForm_1<46, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB, VRRC:$vC), @@ -1022,9 +1031,11 @@ def VSPLTH : VXForm_1<588, (ops VRRC:$vD, u5imm:$UIMM, VRRC:$vB), "vsplth $vD, $vB, $UIMM", VecPerm, []>; -def VSPLTW : VXForm_1<652, (ops VRRC:$vD, u5imm:$UIMM, VRRC:$vB), - "vspltw $vD, $vB, $UIMM", VecPerm, - []>; + +//def VSPLTW : VXForm_1<652, (ops VRRC:$vD, u5imm:$UIMM, VRRC:$vB), +// "vspltw $vD, $vB, $UIMM", VecPerm, +// [(set VRRC:$vD, (vector_shuffle (v4f32 VRRC:$vB), (undef), +// VSPLT_shuffle_mask:$UIMM))]>; // VX-Form Pseudo Instructions @@ -1033,6 +1044,7 @@ []>; } + //===----------------------------------------------------------------------===// // DWARF Pseudo Instructions // From lattner at cs.uiuc.edu Mon Mar 20 00:18:13 2006 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Mon, 20 Mar 2006 00:18:13 -0600 Subject: [llvm-commits] CVS: llvm/lib/Target/TargetSelectionDAG.td Message-ID: <200603200618.AAA07090@zion.cs.uiuc.edu> Changes in directory llvm/lib/Target: TargetSelectionDAG.td updated: 1.53 -> 1.54 --- Log message: Add a build_vector node --- Diffs of the changes: (+1 -1) TargetSelectionDAG.td | 2 +- 1 files changed, 1 insertion(+), 1 deletion(-) Index: llvm/lib/Target/TargetSelectionDAG.td diff -u llvm/lib/Target/TargetSelectionDAG.td:1.53 llvm/lib/Target/TargetSelectionDAG.td:1.54 --- llvm/lib/Target/TargetSelectionDAG.td:1.53 Sun Mar 19 23:40:45 2006 +++ llvm/lib/Target/TargetSelectionDAG.td Mon Mar 20 00:18:01 2006 @@ -307,7 +307,7 @@ def truncst : SDNode<"ISD::TRUNCSTORE" , SDTTruncStore, [SDNPHasChain]>; def vector_shuffle : SDNode<"ISD::VECTOR_SHUFFLE", SDTVecShuffle, []>; - +def build_vector : SDNode<"ISD::BUILD_VECTOR", SDTypeProfile<1, 0, []>, []>; //===----------------------------------------------------------------------===// // Selection DAG Condition Codes From lattner at cs.uiuc.edu Mon Mar 20 00:18:13 2006 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Mon, 20 Mar 2006 00:18:13 -0600 Subject: [llvm-commits] CVS: llvm/lib/Target/X86/X86ISelLowering.cpp Message-ID: <200603200618.AAA07094@zion.cs.uiuc.edu> Changes in directory llvm/lib/Target/X86: X86ISelLowering.cpp updated: 1.112 -> 1.113 --- Log message: Add a build_vector node --- Diffs of the changes: (+1 -0) X86ISelLowering.cpp | 1 + 1 files changed, 1 insertion(+) Index: llvm/lib/Target/X86/X86ISelLowering.cpp diff -u llvm/lib/Target/X86/X86ISelLowering.cpp:1.112 llvm/lib/Target/X86/X86ISelLowering.cpp:1.113 --- llvm/lib/Target/X86/X86ISelLowering.cpp:1.112 Sat Mar 18 19:13:28 2006 +++ llvm/lib/Target/X86/X86ISelLowering.cpp Mon Mar 20 00:18:01 2006 @@ -255,6 +255,7 @@ setOperationAction(ISD::SUB , (MVT::ValueType)VT, Expand); setOperationAction(ISD::MUL , (MVT::ValueType)VT, Expand); setOperationAction(ISD::LOAD, (MVT::ValueType)VT, Expand); + setOperationAction(ISD::VECTOR_SHUFFLE, (MVT::ValueType)VT, Expand); } if (TM.getSubtarget().hasMMX()) { From lattner at cs.uiuc.edu Mon Mar 20 00:33:13 2006 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Mon, 20 Mar 2006 00:33:13 -0600 Subject: [llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCISelLowering.cpp PPCISelLowering.h Message-ID: <200603200633.AAA07171@zion.cs.uiuc.edu> Changes in directory llvm/lib/Target/PowerPC: PPCISelLowering.cpp updated: 1.101 -> 1.102 PPCISelLowering.h updated: 1.29 -> 1.30 --- Log message: fix duplicate definition errors --- Diffs of the changes: (+20 -2) PPCISelLowering.cpp | 18 ++++++++++++++++++ PPCISelLowering.h | 4 ++-- 2 files changed, 20 insertions(+), 2 deletions(-) Index: llvm/lib/Target/PowerPC/PPCISelLowering.cpp diff -u llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.101 llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.102 --- llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.101 Sun Mar 19 19:53:53 2006 +++ llvm/lib/Target/PowerPC/PPCISelLowering.cpp Mon Mar 20 00:33:01 2006 @@ -239,6 +239,24 @@ return false; } + +/// isSplatShuffleMask - Return true if the specified VECTOR_SHUFFLE operand +/// specifies a splat of a single element that is suitable for input to +/// VSPLTB/VSPLTH/VSPLTW. +bool PPC::isSplatShuffleMask(SDNode *N) { + assert(N->getOpcode() == ISD::BUILD_VECTOR); + return false; +} + +/// getVSPLTImmediate - Return the appropriate VSPLT* immediate to splat the +/// specified isSplatShuffleMask VECTOR_SHUFFLE mask. +unsigned PPC::getVSPLTImmediate(SDNode *N) { + assert(isSplatShuffleMask(N)); + return 0; +} + + + /// LowerOperation - Provide custom lowering hooks for some operations. /// SDOperand PPCTargetLowering::LowerOperation(SDOperand Op, SelectionDAG &DAG) { Index: llvm/lib/Target/PowerPC/PPCISelLowering.h diff -u llvm/lib/Target/PowerPC/PPCISelLowering.h:1.29 llvm/lib/Target/PowerPC/PPCISelLowering.h:1.30 --- llvm/lib/Target/PowerPC/PPCISelLowering.h:1.29 Mon Mar 20 00:15:45 2006 +++ llvm/lib/Target/PowerPC/PPCISelLowering.h Mon Mar 20 00:33:01 2006 @@ -89,11 +89,11 @@ /// isSplatShuffleMask - Return true if the specified VECTOR_SHUFFLE operand /// specifies a splat of a single element that is suitable for input to /// VSPLTB/VSPLTH/VSPLTW. - bool isSplatShuffleMask(SDNode *N) { return false; } // FIXME: + bool isSplatShuffleMask(SDNode *N); /// getVSPLTImmediate - Return the appropriate VSPLT* immediate to splat the /// specified isSplatShuffleMask VECTOR_SHUFFLE mask. - unsigned getVSPLTImmediate(SDNode *N) { return 0; } // FIXME: + unsigned getVSPLTImmediate(SDNode *N); } class PPCTargetLowering : public TargetLowering { From lattner at cs.uiuc.edu Mon Mar 20 00:37:56 2006 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Mon, 20 Mar 2006 00:37:56 -0600 Subject: [llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCISelLowering.cpp Message-ID: <200603200637.AAA07237@zion.cs.uiuc.edu> Changes in directory llvm/lib/Target/PowerPC: PPCISelLowering.cpp updated: 1.102 -> 1.103 --- Log message: Implement PPC::isSplatShuffleMask and PPC::getVSPLTImmediate. --- Diffs of the changes: (+13 -2) PPCISelLowering.cpp | 15 +++++++++++++-- 1 files changed, 13 insertions(+), 2 deletions(-) Index: llvm/lib/Target/PowerPC/PPCISelLowering.cpp diff -u llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.102 llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.103 --- llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.102 Mon Mar 20 00:33:01 2006 +++ llvm/lib/Target/PowerPC/PPCISelLowering.cpp Mon Mar 20 00:37:44 2006 @@ -245,14 +245,25 @@ /// VSPLTB/VSPLTH/VSPLTW. bool PPC::isSplatShuffleMask(SDNode *N) { assert(N->getOpcode() == ISD::BUILD_VECTOR); - return false; + // This is a splat operation if each element of the permute is the same, and + // if the value doesn't reference the second vector. + SDOperand Elt = N->getOperand(0); + assert(isa(Elt) && "Invalid VECTOR_SHUFFLE mask!"); + for (unsigned i = 1, e = N->getNumOperands(); i != e; ++i) { + assert(isa(N->getOperand(i)) && + "Invalid VECTOR_SHUFFLE mask!"); + if (N->getOperand(i) != Elt) return false; + } + + // Make sure it is a splat of the first vector operand. + return cast(Elt)->getValue() < N->getNumOperands(); } /// getVSPLTImmediate - Return the appropriate VSPLT* immediate to splat the /// specified isSplatShuffleMask VECTOR_SHUFFLE mask. unsigned PPC::getVSPLTImmediate(SDNode *N) { assert(isSplatShuffleMask(N)); - return 0; + return cast(N)->getValue(); } From lattner at cs.uiuc.edu Mon Mar 20 00:51:22 2006 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Mon, 20 Mar 2006 00:51:22 -0600 Subject: [llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp PPCISelLowering.cpp PPCInstrInfo.td Message-ID: <200603200651.AAA07327@zion.cs.uiuc.edu> Changes in directory llvm/lib/Target/PowerPC: PPCISelDAGToDAG.cpp updated: 1.169 -> 1.170 PPCISelLowering.cpp updated: 1.103 -> 1.104 PPCInstrInfo.td updated: 1.196 -> 1.197 --- Log message: Add support for generating vspltw, instead of a vperm instruction with a constant pool load. This generates significantly nicer code for splats. When tblgen gets bugfixed, we can remove the custom selection code. --- Diffs of the changes: (+41 -13) PPCISelDAGToDAG.cpp | 16 ++++++++++++++++ PPCISelLowering.cpp | 28 +++++++++++++++++++--------- PPCInstrInfo.td | 10 ++++++---- 3 files changed, 41 insertions(+), 13 deletions(-) Index: llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp diff -u llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp:1.169 llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp:1.170 --- llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp:1.169 Thu Mar 16 19:40:33 2006 +++ llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp Mon Mar 20 00:51:10 2006 @@ -927,6 +927,22 @@ switch (N->getOpcode()) { default: break; + case ISD::VECTOR_SHUFFLE: + // FIXME: This should be autogenerated from the .td file, it is here for now + // due to bugs in tblgen. + if (Op.getOperand(1).getOpcode() == ISD::UNDEF && + (Op.getValueType() == MVT::v4f32 || Op.getValueType() == MVT::v4i32) && + PPC::isSplatShuffleMask(Op.getOperand(2).Val)) { + SDOperand N0; + Select(N0, N->getOperand(0)); + + Result = CodeGenMap[Op] = + SDOperand(CurDAG->getTargetNode(PPC::VSPLTW, MVT::v4f32, + getI32Imm(PPC::getVSPLTImmediate(Op.getOperand(2).Val)), + N0), 0); + return; + } + assert(0 && "ILLEGAL VECTOR_SHUFFLE!"); case ISD::SETCC: Result = SelectSETCC(Op); return; Index: llvm/lib/Target/PowerPC/PPCISelLowering.cpp diff -u llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.103 llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.104 --- llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.103 Mon Mar 20 00:37:44 2006 +++ llvm/lib/Target/PowerPC/PPCISelLowering.cpp Mon Mar 20 00:51:10 2006 @@ -245,6 +245,12 @@ /// VSPLTB/VSPLTH/VSPLTW. bool PPC::isSplatShuffleMask(SDNode *N) { assert(N->getOpcode() == ISD::BUILD_VECTOR); + + // We can only splat 8-bit, 16-bit, and 32-bit quantities. + if (N->getNumOperands() != 4 && N->getNumOperands() != 8 && + N->getNumOperands() != 16) + return false; + // This is a splat operation if each element of the permute is the same, and // if the value doesn't reference the second vector. SDOperand Elt = N->getOperand(0); @@ -263,11 +269,10 @@ /// specified isSplatShuffleMask VECTOR_SHUFFLE mask. unsigned PPC::getVSPLTImmediate(SDNode *N) { assert(isSplatShuffleMask(N)); - return cast(N)->getValue(); + return cast(N->getOperand(0))->getValue(); } - /// LowerOperation - Provide custom lowering hooks for some operations. /// SDOperand PPCTargetLowering::LowerOperation(SDOperand Op, SelectionDAG &DAG) { @@ -602,17 +607,22 @@ DAG.getSrcValue(NULL)); } case ISD::VECTOR_SHUFFLE: { - // FIXME: Cases that are handled by instructions that take permute - // immediates (such as vsplt*) shouldn't be lowered here! Also handle cases - // that are cheaper to do as multiple such instructions than as a constant - // pool load/vperm pair. + SDOperand V1 = Op.getOperand(0); + SDOperand V2 = Op.getOperand(1); + SDOperand PermMask = Op.getOperand(2); + + // Cases that are handled by instructions that take permute immediates + // (such as vsplt*) should be left as VECTOR_SHUFFLE nodes so they can be + // selected by the instruction selector. + if (PPC::isSplatShuffleMask(PermMask.Val) && V2.getOpcode() == ISD::UNDEF) + break; + + // TODO: Handle more cases, and also handle cases that are cheaper to do as + // multiple such instructions than as a constant pool load/vperm pair. // Lower this to a VPERM(V1, V2, V3) expression, where V3 is a constant // vector that will get spilled to the constant pool. - SDOperand V1 = Op.getOperand(0); - SDOperand V2 = Op.getOperand(1); if (V2.getOpcode() == ISD::UNDEF) V2 = V1; - SDOperand PermMask = Op.getOperand(2); // The SHUFFLE_VECTOR mask is almost exactly what we want for vperm, except // that it is in input element units, not in bytes. Convert now. Index: llvm/lib/Target/PowerPC/PPCInstrInfo.td diff -u llvm/lib/Target/PowerPC/PPCInstrInfo.td:1.196 llvm/lib/Target/PowerPC/PPCInstrInfo.td:1.197 --- llvm/lib/Target/PowerPC/PPCInstrInfo.td:1.196 Mon Mar 20 00:15:45 2006 +++ llvm/lib/Target/PowerPC/PPCInstrInfo.td Mon Mar 20 00:51:10 2006 @@ -1032,10 +1032,12 @@ "vsplth $vD, $vB, $UIMM", VecPerm, []>; -//def VSPLTW : VXForm_1<652, (ops VRRC:$vD, u5imm:$UIMM, VRRC:$vB), -// "vspltw $vD, $vB, $UIMM", VecPerm, -// [(set VRRC:$vD, (vector_shuffle (v4f32 VRRC:$vB), (undef), -// VSPLT_shuffle_mask:$UIMM))]>; +def VSPLTW : VXForm_1<652, (ops VRRC:$vD, u5imm:$UIMM, VRRC:$vB), + "vspltw $vD, $vB, $UIMM", VecPerm, + [/* + (set VRRC:$vD, (vector_shuffle (v4f32 VRRC:$vB), (undef), + VSPLT_shuffle_mask:$UIMM))*/]>; + // FIXME: ALSO ADD SUPPORT FOR v4i32! // VX-Form Pseudo Instructions From evan.cheng at apple.com Mon Mar 20 02:09:30 2006 From: evan.cheng at apple.com (Evan Cheng) Date: Mon, 20 Mar 2006 02:09:30 -0600 Subject: [llvm-commits] CVS: llvm/utils/TableGen/DAGISelEmitter.cpp Message-ID: <200603200809.CAA08615@zion.cs.uiuc.edu> Changes in directory llvm/utils/TableGen: DAGISelEmitter.cpp updated: 1.178 -> 1.179 --- Log message: It should be ok for a xform output type to be different from input type. --- Diffs of the changes: (+17 -5) DAGISelEmitter.cpp | 22 +++++++++++++++++----- 1 files changed, 17 insertions(+), 5 deletions(-) Index: llvm/utils/TableGen/DAGISelEmitter.cpp diff -u llvm/utils/TableGen/DAGISelEmitter.cpp:1.178 llvm/utils/TableGen/DAGISelEmitter.cpp:1.179 --- llvm/utils/TableGen/DAGISelEmitter.cpp:1.178 Mon Mar 20 00:04:09 2006 +++ llvm/utils/TableGen/DAGISelEmitter.cpp Mon Mar 20 02:09:17 2006 @@ -694,14 +694,26 @@ } else { assert(getOperator()->isSubClassOf("SDNodeXForm") && "Unknown node type!"); - // Node transforms always take one operand, and take and return the same - // type. + // Node transforms always take one operand. if (getNumChildren() != 1) TP.error("Node transform '" + getOperator()->getName() + "' requires one operand!"); - bool MadeChange = UpdateNodeType(getChild(0)->getExtTypes(), TP); - MadeChange |= getChild(0)->UpdateNodeType(getExtTypes(), TP); - return MadeChange; + unsigned char ExtType0 = getExtTypeNum(0); + unsigned char ChildExtType0 = getChild(0)->getExtTypeNum(0); + if (ExtType0 == MVT::isInt || + ExtType0 == MVT::isFP || + ExtType0 == MVT::isUnknown || + ChildExtType0 == MVT::isInt || + ChildExtType0 == MVT::isFP || + ChildExtType0 == MVT::isUnknown) { + // If either the output or input of the xform does not have exact + // type info. We assume they must be the same. Otherwise, it is perfectly + // legal to transform from one type to a completely different type. + bool MadeChange = UpdateNodeType(getChild(0)->getExtTypes(), TP); + MadeChange |= getChild(0)->UpdateNodeType(getExtTypes(), TP); + return MadeChange; + } + return false; } } From evan.cheng at apple.com Mon Mar 20 02:14:30 2006 From: evan.cheng at apple.com (Evan Cheng) Date: Mon, 20 Mar 2006 02:14:30 -0600 Subject: [llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp PPCInstrInfo.td Message-ID: <200603200814.CAA10316@zion.cs.uiuc.edu> Changes in directory llvm/lib/Target/PowerPC: PPCISelDAGToDAG.cpp updated: 1.170 -> 1.171 PPCInstrInfo.td updated: 1.197 -> 1.198 --- Log message: Use tblgen'd VECTOR_SHUFFLE selection code. --- Diffs of the changes: (+2 -19) PPCISelDAGToDAG.cpp | 16 ---------------- PPCInstrInfo.td | 5 ++--- 2 files changed, 2 insertions(+), 19 deletions(-) Index: llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp diff -u llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp:1.170 llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp:1.171 --- llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp:1.170 Mon Mar 20 00:51:10 2006 +++ llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp Mon Mar 20 02:14:16 2006 @@ -927,22 +927,6 @@ switch (N->getOpcode()) { default: break; - case ISD::VECTOR_SHUFFLE: - // FIXME: This should be autogenerated from the .td file, it is here for now - // due to bugs in tblgen. - if (Op.getOperand(1).getOpcode() == ISD::UNDEF && - (Op.getValueType() == MVT::v4f32 || Op.getValueType() == MVT::v4i32) && - PPC::isSplatShuffleMask(Op.getOperand(2).Val)) { - SDOperand N0; - Select(N0, N->getOperand(0)); - - Result = CodeGenMap[Op] = - SDOperand(CurDAG->getTargetNode(PPC::VSPLTW, MVT::v4f32, - getI32Imm(PPC::getVSPLTImmediate(Op.getOperand(2).Val)), - N0), 0); - return; - } - assert(0 && "ILLEGAL VECTOR_SHUFFLE!"); case ISD::SETCC: Result = SelectSETCC(Op); return; Index: llvm/lib/Target/PowerPC/PPCInstrInfo.td diff -u llvm/lib/Target/PowerPC/PPCInstrInfo.td:1.197 llvm/lib/Target/PowerPC/PPCInstrInfo.td:1.198 --- llvm/lib/Target/PowerPC/PPCInstrInfo.td:1.197 Mon Mar 20 00:51:10 2006 +++ llvm/lib/Target/PowerPC/PPCInstrInfo.td Mon Mar 20 02:14:16 2006 @@ -1034,9 +1034,8 @@ def VSPLTW : VXForm_1<652, (ops VRRC:$vD, u5imm:$UIMM, VRRC:$vB), "vspltw $vD, $vB, $UIMM", VecPerm, - [/* - (set VRRC:$vD, (vector_shuffle (v4f32 VRRC:$vB), (undef), - VSPLT_shuffle_mask:$UIMM))*/]>; + [(set VRRC:$vD, (vector_shuffle (v4f32 VRRC:$vB), (undef), + VSPLT_shuffle_mask:$UIMM))]>; // FIXME: ALSO ADD SUPPORT FOR v4i32! // VX-Form Pseudo Instructions From lattner at cs.uiuc.edu Mon Mar 20 11:53:01 2006 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Mon, 20 Mar 2006 11:53:01 -0600 Subject: [llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCInstrInfo.td Message-ID: <200603201753.LAA03504@zion.cs.uiuc.edu> Changes in directory llvm/lib/Target/PowerPC: PPCInstrInfo.td updated: 1.198 -> 1.199 --- Log message: Fix the pattern for VADDUWM, add i32 splat --- Diffs of the changes: (+4 -1) PPCInstrInfo.td | 5 ++++- 1 files changed, 4 insertions(+), 1 deletion(-) Index: llvm/lib/Target/PowerPC/PPCInstrInfo.td diff -u llvm/lib/Target/PowerPC/PPCInstrInfo.td:1.198 llvm/lib/Target/PowerPC/PPCInstrInfo.td:1.199 --- llvm/lib/Target/PowerPC/PPCInstrInfo.td:1.198 Mon Mar 20 02:14:16 2006 +++ llvm/lib/Target/PowerPC/PPCInstrInfo.td Mon Mar 20 11:51:58 2006 @@ -972,7 +972,7 @@ [(set VRRC:$vD, (fadd VRRC:$vA, VRRC:$vB))]>; def VADDUWM : VXForm_1<128, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB), "vadduwm $vD, $vA, $vB", VecGeneral, - [(set VRRC:$vD, (add VRRC:$vA, VRRC:$vB))]>; + [(set VRRC:$vD, (add (v4i32 VRRC:$vA), VRRC:$vB))]>; def VCFSX : VXForm_1<842, (ops VRRC:$vD, u5imm:$UIMM, VRRC:$vB), "vcfsx $vD, $vB, $UIMM", VecFP, []>; @@ -1178,6 +1178,9 @@ (v16i8 (LVX xoaddr:$src))>; +def : Pat<(vector_shuffle (v4i32 VRRC:$vB), (undef), VSPLT_shuffle_mask:$UIMM), + (v4i32 (VSPLTW VSPLT_shuffle_mask:$UIMM, VRRC:$vB))>; + def : Pat<(PPCvperm (v4i32 VRRC:$vA), VRRC:$vB, VRRC:$vC), (v4i32 (VPERM VRRC:$vA, VRRC:$vB, VRRC:$vC))>; From lattner at cs.uiuc.edu Mon Mar 20 11:55:35 2006 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Mon, 20 Mar 2006 11:55:35 -0600 Subject: [llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp Message-ID: <200603201755.LAA03647@zion.cs.uiuc.edu> Changes in directory llvm/lib/Target/PowerPC: PPCISelDAGToDAG.cpp updated: 1.171 -> 1.172 --- Log message: reenable this hack, the tblgen version isn't quite ready --- Diffs of the changes: (+16 -0) PPCISelDAGToDAG.cpp | 16 ++++++++++++++++ 1 files changed, 16 insertions(+) Index: llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp diff -u llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp:1.171 llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp:1.172 --- llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp:1.171 Mon Mar 20 02:14:16 2006 +++ llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp Mon Mar 20 11:54:43 2006 @@ -927,6 +927,22 @@ switch (N->getOpcode()) { default: break; + case ISD::VECTOR_SHUFFLE: + // FIXME: This should be autogenerated from the .td file, it is here for now + // due to bugs in tblgen. + if (Op.getOperand(1).getOpcode() == ISD::UNDEF && + (Op.getValueType() == MVT::v4f32 || Op.getValueType() == MVT::v4i32) && + PPC::isSplatShuffleMask(Op.getOperand(2).Val)) { + SDOperand N0; + Select(N0, N->getOperand(0)); + Result = CodeGenMap[Op] = + SDOperand(CurDAG->getTargetNode(PPC::VSPLTW, MVT::v4f32, + getI32Imm(PPC::getVSPLTImmediate(Op.getOperand(2).Val)), + N0), 0); + return; + } + assert(0 && "ILLEGAL VECTOR_SHUFFLE!"); + case ISD::SETCC: Result = SelectSETCC(Op); return; From evan.cheng at apple.com Mon Mar 20 12:26:23 2006 From: evan.cheng at apple.com (Evan Cheng) Date: Mon, 20 Mar 2006 12:26:23 -0600 Subject: [llvm-commits] CVS: llvm/test/Regression/CodeGen/X86/loop-strength-reduce.ll Message-ID: <200603201826.MAA03926@zion.cs.uiuc.edu> Changes in directory llvm/test/Regression/CodeGen/X86: loop-strength-reduce.ll updated: 1.1 -> 1.2 --- Log message: Option -enable-x86-lsr has been removed --- Diffs of the changes: (+1 -1) loop-strength-reduce.ll | 2 +- 1 files changed, 1 insertion(+), 1 deletion(-) Index: llvm/test/Regression/CodeGen/X86/loop-strength-reduce.ll diff -u llvm/test/Regression/CodeGen/X86/loop-strength-reduce.ll:1.1 llvm/test/Regression/CodeGen/X86/loop-strength-reduce.ll:1.2 --- llvm/test/Regression/CodeGen/X86/loop-strength-reduce.ll:1.1 Fri Mar 17 13:45:54 2006 +++ llvm/test/Regression/CodeGen/X86/loop-strength-reduce.ll Mon Mar 20 12:26:11 2006 @@ -1,4 +1,4 @@ -; RUN: llvm-as < %s | llc -march=x86 -enable-x86-lsr | grep 'A(' | wc -l | grep 1 +; RUN: llvm-as < %s | llc -march=x86 | grep 'A(' | wc -l | grep 1 ; ; Make sure the common loop invariant _A(reg) is hoisted up to preheader. From lattner at cs.uiuc.edu Mon Mar 20 12:27:03 2006 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Mon, 20 Mar 2006 12:27:03 -0600 Subject: [llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCISelLowering.cpp PPCInstrInfo.td Message-ID: <200603201827.MAA04003@zion.cs.uiuc.edu> Changes in directory llvm/lib/Target/PowerPC: PPCISelLowering.cpp updated: 1.104 -> 1.105 PPCInstrInfo.td updated: 1.199 -> 1.200 --- Log message: Fix a couple of bugs in permute/splat generate, thanks to Nate for actually figuring these out! :) --- Diffs of the changes: (+1 -3) PPCISelLowering.cpp | 2 -- PPCInstrInfo.td | 2 +- 2 files changed, 1 insertion(+), 3 deletions(-) Index: llvm/lib/Target/PowerPC/PPCISelLowering.cpp diff -u llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.104 llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.105 --- llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.104 Mon Mar 20 00:51:10 2006 +++ llvm/lib/Target/PowerPC/PPCISelLowering.cpp Mon Mar 20 12:26:51 2006 @@ -599,8 +599,6 @@ // Store the input value into Value#0 of the stack slot. unsigned InSize = MVT::getSizeInBits(Op.getOperand(0).getValueType())/8; - FIdx = DAG.getNode(ISD::ADD, MVT::i32, FIdx, - DAG.getConstant(16-InSize, MVT::i32)); SDOperand Store = DAG.getNode(ISD::STORE, MVT::Other, DAG.getEntryNode(), Op.getOperand(0), FIdx,DAG.getSrcValue(NULL)); return DAG.getNode(PPCISD::LVE_X, Op.getValueType(), Store, FIdx, Index: llvm/lib/Target/PowerPC/PPCInstrInfo.td diff -u llvm/lib/Target/PowerPC/PPCInstrInfo.td:1.199 llvm/lib/Target/PowerPC/PPCInstrInfo.td:1.200 --- llvm/lib/Target/PowerPC/PPCInstrInfo.td:1.199 Mon Mar 20 11:51:58 2006 +++ llvm/lib/Target/PowerPC/PPCInstrInfo.td Mon Mar 20 12:26:51 2006 @@ -961,7 +961,7 @@ Requires<[FPContractions]>; def VPERM : VAForm_1<43, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB, VRRC:$vC), - "vperm $vD, $vA, $vC, $vB", VecPerm, + "vperm $vD, $vA, $vB, $vC", VecPerm, [(set VRRC:$vD, (PPCvperm (v4f32 VRRC:$vA), VRRC:$vB, VRRC:$vC))]>; From natebegeman at mac.com Mon Mar 20 13:33:39 2006 From: natebegeman at mac.com (Nate Begeman) Date: Mon, 20 Mar 2006 13:33:39 -0600 Subject: [llvm-commits] CVS: llvm/include/llvm/Analysis/PostDominators.h Dominators.h Message-ID: <200603201933.NAA04361@zion.cs.uiuc.edu> Changes in directory llvm/include/llvm/Analysis: PostDominators.h updated: 1.11 -> 1.12 Dominators.h updated: 1.53 -> 1.54 --- Log message: Move some common data structures between dom and pdom into the base class --- Diffs of the changes: (+16 -32) Dominators.h | 32 ++++++++++++++++---------------- PostDominators.h | 16 ---------------- 2 files changed, 16 insertions(+), 32 deletions(-) Index: llvm/include/llvm/Analysis/PostDominators.h diff -u llvm/include/llvm/Analysis/PostDominators.h:1.11 llvm/include/llvm/Analysis/PostDominators.h:1.12 --- llvm/include/llvm/Analysis/PostDominators.h:1.11 Fri Mar 10 20:20:46 2006 +++ llvm/include/llvm/Analysis/PostDominators.h Mon Mar 20 13:32:48 2006 @@ -32,22 +32,6 @@ } private: - struct InfoRec { - unsigned Semi; - unsigned Size; - BasicBlock *Label, *Parent, *Child, *Ancestor; - - std::vector Bucket; - - InfoRec() : Semi(0), Size(0), Label(0), Parent(0), Child(0), Ancestor(0){} - }; - - // Vertex - Map the DFS number to the BasicBlock* - std::vector Vertex; - - // Info - Collection of information used during the computation of idoms. - std::map Info; - unsigned DFSPass(BasicBlock *V, InfoRec &VInfo, unsigned N); void Compress(BasicBlock *V, InfoRec &VInfo); BasicBlock *Eval(BasicBlock *v); Index: llvm/include/llvm/Analysis/Dominators.h diff -u llvm/include/llvm/Analysis/Dominators.h:1.53 llvm/include/llvm/Analysis/Dominators.h:1.54 --- llvm/include/llvm/Analysis/Dominators.h:1.53 Sat Jan 14 14:55:08 2006 +++ llvm/include/llvm/Analysis/Dominators.h Mon Mar 20 13:32:48 2006 @@ -66,7 +66,23 @@ /// class ImmediateDominatorsBase : public DominatorBase { protected: + struct InfoRec { + unsigned Semi; + unsigned Size; + BasicBlock *Label, *Parent, *Child, *Ancestor; + + std::vector Bucket; + + InfoRec() : Semi(0), Size(0), Label(0), Parent(0), Child(0), Ancestor(0){} + }; + std::map IDoms; + + // Vertex - Map the DFS number to the BasicBlock* + std::vector Vertex; + + // Info - Collection of information used during the computation of idoms. + std::map Info; public: ImmediateDominatorsBase(bool isPostDom) : DominatorBase(isPostDom) {} @@ -139,22 +155,6 @@ } private: - struct InfoRec { - unsigned Semi; - unsigned Size; - BasicBlock *Label, *Parent, *Child, *Ancestor; - - std::vector Bucket; - - InfoRec() : Semi(0), Size(0), Label(0), Parent(0), Child(0), Ancestor(0){} - }; - - // Vertex - Map the DFS number to the BasicBlock* - std::vector Vertex; - - // Info - Collection of information used during the computation of idoms. - std::map Info; - unsigned DFSPass(BasicBlock *V, InfoRec &VInfo, unsigned N); void Compress(BasicBlock *V, InfoRec &VInfo); BasicBlock *Eval(BasicBlock *v); From lattner at cs.uiuc.edu Mon Mar 20 16:37:17 2006 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Mon, 20 Mar 2006 16:37:17 -0600 Subject: [llvm-commits] CVS: llvm/test/Regression/CodeGen/PowerPC/load-constant-addr.ll Message-ID: <200603202237.QAA06845@zion.cs.uiuc.edu> Changes in directory llvm/test/Regression/CodeGen/PowerPC: load-constant-addr.ll added (r1.1) --- Log message: new testcase --- Diffs of the changes: (+9 -0) load-constant-addr.ll | 9 +++++++++ 1 files changed, 9 insertions(+) Index: llvm/test/Regression/CodeGen/PowerPC/load-constant-addr.ll diff -c /dev/null llvm/test/Regression/CodeGen/PowerPC/load-constant-addr.ll:1.1 *** /dev/null Mon Mar 20 16:37:15 2006 --- llvm/test/Regression/CodeGen/PowerPC/load-constant-addr.ll Mon Mar 20 16:37:05 2006 *************** *** 0 **** --- 1,9 ---- + ; Should fold the ori into the lfs. + ; RUN: llvm-as < %s | llc -march=ppc32 | grep lfs && + ; RUN: llvm-as < %s | llc -march=ppc32 | not grep ori + + float %test() { + %tmp.i = load float* cast (uint 186018016 to float*) + ret float %tmp.i + } + From lattner at cs.uiuc.edu Mon Mar 20 16:37:35 2006 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Mon, 20 Mar 2006 16:37:35 -0600 Subject: [llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCISelLowering.cpp Message-ID: <200603202237.QAA06880@zion.cs.uiuc.edu> Changes in directory llvm/lib/Target/PowerPC: PPCISelLowering.cpp updated: 1.105 -> 1.106 --- Log message: remove dead variable --- Diffs of the changes: (+1 -1) PPCISelLowering.cpp | 2 +- 1 files changed, 1 insertion(+), 1 deletion(-) Index: llvm/lib/Target/PowerPC/PPCISelLowering.cpp diff -u llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.105 llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.106 --- llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.105 Mon Mar 20 12:26:51 2006 +++ llvm/lib/Target/PowerPC/PPCISelLowering.cpp Mon Mar 20 16:37:23 2006 @@ -598,9 +598,9 @@ SDOperand FIdx = DAG.getFrameIndex(FrameIdx, MVT::i32); // Store the input value into Value#0 of the stack slot. - unsigned InSize = MVT::getSizeInBits(Op.getOperand(0).getValueType())/8; SDOperand Store = DAG.getNode(ISD::STORE, MVT::Other, DAG.getEntryNode(), Op.getOperand(0), FIdx,DAG.getSrcValue(NULL)); + // LVE_X it out. return DAG.getNode(PPCISD::LVE_X, Op.getValueType(), Store, FIdx, DAG.getSrcValue(NULL)); } From lattner at cs.uiuc.edu Mon Mar 20 16:38:34 2006 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Mon, 20 Mar 2006 16:38:34 -0600 Subject: [llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp Message-ID: <200603202238.QAA06921@zion.cs.uiuc.edu> Changes in directory llvm/lib/Target/PowerPC: PPCISelDAGToDAG.cpp updated: 1.172 -> 1.173 --- Log message: Handle constant addresses more efficiently, folding the low bits into the disp field of the load/store if possible. This compiles CodeGen/PowerPC/load-constant-addr.ll to: _test: lis r2, 2838 lfs f1, 26848(r2) blr instead of: _test: lis r2, 2838 ori r2, r2, 26848 lfs f1, 0(r2) blr --- Diffs of the changes: (+17 -0) PPCISelDAGToDAG.cpp | 17 +++++++++++++++++ 1 files changed, 17 insertions(+) Index: llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp diff -u llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp:1.172 llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp:1.173 --- llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp:1.172 Mon Mar 20 11:54:43 2006 +++ llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp Mon Mar 20 16:38:22 2006 @@ -535,7 +535,24 @@ return true; } } + } else if (ConstantSDNode *CN = dyn_cast(N)) { + // Loading from a constant address. + int Addr = (int)CN->getValue(); + + // If this address fits entirely in a 16-bit sext immediate field, codegen + // this as "d, 0" + if (Addr == (short)Addr) { + Disp = getI32Imm(Addr); + Base = CurDAG->getRegister(PPC::R0, MVT::i32); + return true; + } + + // Otherwise, break this down into an LIS + disp. + Disp = getI32Imm((short)Addr); + Base = CurDAG->getConstant(Addr - (signed short)Addr, MVT::i32); + return true; } + Disp = getI32Imm(0); if (FrameIndexSDNode *FI = dyn_cast(N)) Base = CurDAG->getTargetFrameIndex(FI->getIndex(), MVT::i32); From evan.cheng at apple.com Mon Mar 20 16:53:18 2006 From: evan.cheng at apple.com (Evan Cheng) Date: Mon, 20 Mar 2006 16:53:18 -0600 Subject: [llvm-commits] CVS: llvm/utils/TableGen/DAGISelEmitter.cpp Message-ID: <200603202253.QAA07078@zion.cs.uiuc.edu> Changes in directory llvm/utils/TableGen: DAGISelEmitter.cpp updated: 1.179 -> 1.180 --- Log message: The node wrapped in PatLeaf<> should be treated as a leaf even if it isn't one, i.e. don't select it. --- Diffs of the changes: (+11 -4) DAGISelEmitter.cpp | 15 +++++++++++---- 1 files changed, 11 insertions(+), 4 deletions(-) Index: llvm/utils/TableGen/DAGISelEmitter.cpp diff -u llvm/utils/TableGen/DAGISelEmitter.cpp:1.179 llvm/utils/TableGen/DAGISelEmitter.cpp:1.180 --- llvm/utils/TableGen/DAGISelEmitter.cpp:1.179 Mon Mar 20 02:09:17 2006 +++ llvm/utils/TableGen/DAGISelEmitter.cpp Mon Mar 20 16:53:06 2006 @@ -2175,7 +2175,7 @@ /// EmitResultCode - Emit the action for a pattern. Now that it has matched /// we actually have to build a DAG! std::pair - EmitResultCode(TreePatternNode *N, bool isRoot = false) { + EmitResultCode(TreePatternNode *N, bool LikeLeaf = false, bool isRoot = false) { // This is something selected from the pattern we matched. if (!N->getName().empty()) { assert(!isRoot && "Root of pattern cannot be a leaf!"); @@ -2257,7 +2257,12 @@ TmpNo = ResNo + NumRes; } else { emitDecl("Tmp" + utostr(ResNo)); - emitCode("Select(Tmp" + utostr(ResNo) + ", " + Val + ");"); + // This node, probably wrapped in a SDNodeXForms, behaves like a leaf + // node even if it isn't one. Don't select it. + if (LikeLeaf) + emitCode("Tmp" + utostr(ResNo) + " = " + Val + ";"); + else + emitCode("Select(Tmp" + utostr(ResNo) + ", " + Val + ");"); } // Add Tmp to VariableMap, so that we don't multiply select this // value if used multiple times by this pattern result. @@ -2552,7 +2557,9 @@ return std::make_pair(1, ResNo); } else if (Op->isSubClassOf("SDNodeXForm")) { assert(N->getNumChildren() == 1 && "node xform should have one child!"); - unsigned OpVal = EmitResultCode(N->getChild(0)).second; + // PatLeaf node - the operand may or may not be a leaf node. But it should + // behave like one. + unsigned OpVal = EmitResultCode(N->getChild(0), true).second; unsigned ResNo = TmpNo++; emitDecl("Tmp" + utostr(ResNo)); emitCode("Tmp" + utostr(ResNo) + " = Transform_" + Op->getName() @@ -2748,7 +2755,7 @@ // otherwise we are done. } while (Emitter.InsertOneTypeCheck(Pat, Pattern.getSrcPattern(), "N")); - Emitter.EmitResultCode(Pattern.getDstPattern(), true /*the root*/); + Emitter.EmitResultCode(Pattern.getDstPattern(), false, true /*the root*/); delete Pat; } From evan.cheng at apple.com Mon Mar 20 18:31:11 2006 From: evan.cheng at apple.com (Evan Cheng) Date: Mon, 20 Mar 2006 18:31:11 -0600 Subject: [llvm-commits] CVS: llvm/lib/Target/X86/X86RegisterInfo.td Message-ID: <200603210031.SAA08045@zion.cs.uiuc.edu> Changes in directory llvm/lib/Target/X86: X86RegisterInfo.td updated: 1.30 -> 1.31 --- Log message: Junk unused vector register classes. --- Diffs of the changes: (+0 -25) X86RegisterInfo.td | 25 ------------------------- 1 files changed, 25 deletions(-) Index: llvm/lib/Target/X86/X86RegisterInfo.td diff -u llvm/lib/Target/X86/X86RegisterInfo.td:1.30 llvm/lib/Target/X86/X86RegisterInfo.td:1.31 --- llvm/lib/Target/X86/X86RegisterInfo.td:1.30 Mon Feb 20 19:38:21 2006 +++ llvm/lib/Target/X86/X86RegisterInfo.td Mon Mar 20 18:30:59 2006 @@ -139,31 +139,6 @@ }]; } -// Vector integer registers: V8I8, the 8 x i8 class, V4I16, the 4 x i16 class, -// V2I32, the 2 x i32 class, V16I8, the 16 x i8 class, V8I16, the 8 x i16 class, -// V4I32, the 4 x i32 class, and V2I64, the 2 x i64 class. -def V8I8 : RegisterClass<"X86", [v8i8], 64, - [MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7]>; -def V4I16 : RegisterClass<"X86", [v4i16], 64, - [MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7]>; -def V2I32 : RegisterClass<"X86", [v2i32], 64, - [MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7]>; -def V16I8 : RegisterClass<"X86", [v16i8], 128, - [XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7]>; -def V8I16 : RegisterClass<"X86", [v8i16], 128, - [XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7]>; -def V4I32 : RegisterClass<"X86", [v4i32], 128, - [XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7]>; -def V2I64 : RegisterClass<"X86", [v2i64], 128, - [XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7]>; - -// Vector floating point registers: V4F4, the 4 x f32 class, and V2F8, -// the 2 x f64 class. -def V4F32 : RegisterClass<"X86", [v4f32], 128, - [XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7]>; -def V2F64 : RegisterClass<"X86", [v2f64], 128, - [XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7]>; - // Generic vector registers: VR64 and VR128. def VR64 : RegisterClass<"X86", [v8i8, v4i16, v2i32], 64, [MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7]>; From evan.cheng at apple.com Mon Mar 20 18:33:47 2006 From: evan.cheng at apple.com (Evan Cheng) Date: Mon, 20 Mar 2006 18:33:47 -0600 Subject: [llvm-commits] CVS: llvm/lib/Target/X86/X86InstrMMX.td X86InstrSSE.td Message-ID: <200603210033.SAA08078@zion.cs.uiuc.edu> Changes in directory llvm/lib/Target/X86: X86InstrMMX.td updated: 1.3 -> 1.4 X86InstrSSE.td updated: 1.9 -> 1.10 --- Log message: x86 ISD::SCALAR_TO_VECTOR support. --- Diffs of the changes: (+54 -0) X86InstrMMX.td | 18 ++++++++++++++++++ X86InstrSSE.td | 36 ++++++++++++++++++++++++++++++++++++ 2 files changed, 54 insertions(+) Index: llvm/lib/Target/X86/X86InstrMMX.td diff -u llvm/lib/Target/X86/X86InstrMMX.td:1.3 llvm/lib/Target/X86/X86InstrMMX.td:1.4 --- llvm/lib/Target/X86/X86InstrMMX.td:1.3 Mon Mar 20 00:04:52 2006 +++ llvm/lib/Target/X86/X86InstrMMX.td Mon Mar 20 18:33:35 2006 @@ -22,6 +22,24 @@ def : Pat<(v4i16 (undef)), (IMPLICIT_DEF_VR64)>, Requires<[HasMMX]>; def : Pat<(v2i32 (undef)), (IMPLICIT_DEF_VR64)>, Requires<[HasMMX]>; +def SCALAR_TO_VECTOR_V8I8 : I<0, Pseudo, (ops VR64:$dst, R8:$src), + "#SCALAR_TO_VECTOR $src", + [(set VR64:$dst, + (v8i8 (scalar_to_vector R8:$src)))]>, + Requires<[HasMMX]>; + +def SCALAR_TO_VECTOR_V4I16 : I<0, Pseudo, (ops VR64:$dst, R16:$src), + "#SCALAR_TO_VECTOR $src", + [(set VR64:$dst, + (v4i16 (scalar_to_vector R16:$src)))]>, + Requires<[HasMMX]>; + +def SCALAR_TO_VECTOR_V2I32 : I<0, Pseudo, (ops VR64:$dst, R32:$src), + "#SCALAR_TO_VECTOR $src", + [(set VR64:$dst, + (v2i32 (scalar_to_vector R32:$src)))]>, + Requires<[HasMMX]>; + // Move Instructions def MOVD64rr : I<0x6E, MRMSrcReg, (ops VR64:$dst, R32:$src), "movd {$src, $dst|$dst, $src}", []>, TB, Index: llvm/lib/Target/X86/X86InstrSSE.td diff -u llvm/lib/Target/X86/X86InstrSSE.td:1.9 llvm/lib/Target/X86/X86InstrSSE.td:1.10 --- llvm/lib/Target/X86/X86InstrSSE.td:1.9 Mon Mar 20 00:04:52 2006 +++ llvm/lib/Target/X86/X86InstrSSE.td Mon Mar 20 18:33:35 2006 @@ -353,6 +353,42 @@ def : Pat<(v4i32 (undef)), (IMPLICIT_DEF_VR128)>, Requires<[HasSSE2]>; def : Pat<(v2i64 (undef)), (IMPLICIT_DEF_VR128)>, Requires<[HasSSE2]>; +def SCALAR_TO_VECTOR_V4F32 : I<0, Pseudo, (ops VR128:$dst, FR32:$src), + "#SCALAR_TO_VECTOR $src", + [(set VR128:$dst, + (v4f32 (scalar_to_vector FR32:$src)))]>, + Requires<[HasSSE1]>; + +def SCALAR_TO_VECTOR_V2F64 : I<0, Pseudo, (ops VR128:$dst, FR64:$src), + "#SCALAR_TO_VECTOR $src", + [(set VR128:$dst, + (v2f64 (scalar_to_vector FR64:$src)))]>, + Requires<[HasSSE2]>; + +def SCALAR_TO_VECTOR_V16I8 : I<0, Pseudo, (ops VR128:$dst, R8:$src), + "#SCALAR_TO_VECTOR $src", + [(set VR128:$dst, + (v16i8 (scalar_to_vector R8:$src)))]>, + Requires<[HasSSE2]>; + +def SCALAR_TO_VECTOR_V8I16 : I<0, Pseudo, (ops VR128:$dst, R16:$src), + "#SCALAR_TO_VECTOR $src", + [(set VR128:$dst, + (v8i16 (scalar_to_vector R16:$src)))]>, + Requires<[HasSSE2]>; + +def SCALAR_TO_VECTOR_V4I32 : I<0, Pseudo, (ops VR128:$dst, R32:$src), + "#SCALAR_TO_VECTOR $src", + [(set VR128:$dst, + (v4i32 (scalar_to_vector R32:$src)))]>, + Requires<[HasSSE2]>; + +def SCALAR_TO_VECTOR_V2I64 : I<0, Pseudo, (ops VR128:$dst, VR64:$src), + "#SCALAR_TO_VECTOR $src", + [(set VR128:$dst, + (v2i64 (scalar_to_vector VR64:$src)))]>, + Requires<[HasSSE2]>; + // Move Instructions def MOVAPSrr : PSI<0x28, MRMSrcReg, (ops VR128:$dst, VR128:$src), "movaps {$src, $dst|$dst, $src}", []>; From evan.cheng at apple.com Mon Mar 20 18:33:47 2006 From: evan.cheng at apple.com (Evan Cheng) Date: Mon, 20 Mar 2006 18:33:47 -0600 Subject: [llvm-commits] CVS: llvm/lib/Target/TargetSelectionDAG.td Message-ID: <200603210033.SAA08082@zion.cs.uiuc.edu> Changes in directory llvm/lib/Target: TargetSelectionDAG.td updated: 1.54 -> 1.55 --- Log message: x86 ISD::SCALAR_TO_VECTOR support. --- Diffs of the changes: (+2 -0) TargetSelectionDAG.td | 2 ++ 1 files changed, 2 insertions(+) Index: llvm/lib/Target/TargetSelectionDAG.td diff -u llvm/lib/Target/TargetSelectionDAG.td:1.54 llvm/lib/Target/TargetSelectionDAG.td:1.55 --- llvm/lib/Target/TargetSelectionDAG.td:1.54 Mon Mar 20 00:18:01 2006 +++ llvm/lib/Target/TargetSelectionDAG.td Mon Mar 20 18:33:35 2006 @@ -308,6 +308,8 @@ def vector_shuffle : SDNode<"ISD::VECTOR_SHUFFLE", SDTVecShuffle, []>; def build_vector : SDNode<"ISD::BUILD_VECTOR", SDTypeProfile<1, 0, []>, []>; +def scalar_to_vector : SDNode<"ISD::SCALAR_TO_VECTOR", SDTypeProfile<1, 1, []>, + []>; //===----------------------------------------------------------------------===// // Selection DAG Condition Codes From lattner at cs.uiuc.edu Mon Mar 20 18:47:20 2006 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Mon, 20 Mar 2006 18:47:20 -0600 Subject: [llvm-commits] CVS: llvm/lib/Target/PowerPC/README.txt Message-ID: <200603210047.SAA08174@zion.cs.uiuc.edu> Changes in directory llvm/lib/Target/PowerPC: README.txt updated: 1.76 -> 1.77 --- Log message: minor note --- Diffs of the changes: (+3 -0) README.txt | 3 +++ 1 files changed, 3 insertions(+) Index: llvm/lib/Target/PowerPC/README.txt diff -u llvm/lib/Target/PowerPC/README.txt:1.76 llvm/lib/Target/PowerPC/README.txt:1.77 --- llvm/lib/Target/PowerPC/README.txt:1.76 Sun Mar 19 16:08:08 2006 +++ llvm/lib/Target/PowerPC/README.txt Mon Mar 20 18:47:09 2006 @@ -519,6 +519,9 @@ We generate relatively atrocious code for this loop compared to gcc. +We could also strength reduce the rem and the div: +http://www.lcs.mit.edu/pubs/pdf/MIT-LCS-TM-600.pdf + ===-------------------------------------------------------------------------=== Altivec support. The first should be a single lvx from the constant pool, the From lattner at cs.uiuc.edu Mon Mar 20 18:51:50 2006 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Mon, 20 Mar 2006 18:51:50 -0600 Subject: [llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCInstrInfo.td Message-ID: <200603210051.SAA08249@zion.cs.uiuc.edu> Changes in directory llvm/lib/Target/PowerPC: PPCInstrInfo.td updated: 1.200 -> 1.201 --- Log message: When codegen'ing vector MUL using VFMADD, *add* the 0, don't *mul* the 0. --- Diffs of the changes: (+1 -1) PPCInstrInfo.td | 2 +- 1 files changed, 1 insertion(+), 1 deletion(-) Index: llvm/lib/Target/PowerPC/PPCInstrInfo.td diff -u llvm/lib/Target/PowerPC/PPCInstrInfo.td:1.200 llvm/lib/Target/PowerPC/PPCInstrInfo.td:1.201 --- llvm/lib/Target/PowerPC/PPCInstrInfo.td:1.200 Mon Mar 20 12:26:51 2006 +++ llvm/lib/Target/PowerPC/PPCInstrInfo.td Mon Mar 20 18:51:38 2006 @@ -1123,7 +1123,7 @@ (ADDIS GPRC:$in, tconstpool:$g)>; def : Pat<(fmul VRRC:$vA, VRRC:$vB), - (VMADDFP VRRC:$vA, (V_SET0), VRRC:$vB)>; + (VMADDFP VRRC:$vA, VRRC:$vB, (V_SET0))>; // Fused negative multiply subtract, alternate pattern def : Pat<(fsub F8RC:$B, (fmul F8RC:$A, F8RC:$C)), From lattner at cs.uiuc.edu Mon Mar 20 19:06:53 2006 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Mon, 20 Mar 2006 19:06:53 -0600 Subject: [llvm-commits] CVS: llvm/Makefile.rules Message-ID: <200603210106.TAA08477@zion.cs.uiuc.edu> Changes in directory llvm: Makefile.rules updated: 1.351 -> 1.352 --- Log message: Enable assertions to be enabled in release builds by building with make ENABLE_OPTIMIZED=1 ENABLE_ASSERTIONS=1 --- Diffs of the changes: (+21 -11) Makefile.rules | 32 +++++++++++++++++++++----------- 1 files changed, 21 insertions(+), 11 deletions(-) Index: llvm/Makefile.rules diff -u llvm/Makefile.rules:1.351 llvm/Makefile.rules:1.352 --- llvm/Makefile.rules:1.351 Fri Mar 10 15:01:34 2006 +++ llvm/Makefile.rules Mon Mar 20 19:06:41 2006 @@ -198,12 +198,11 @@ # Variables derived from configuration we are building #-------------------------------------------------------------------- - ifdef ENABLE_PROFILING BuildMode := Profile - CXX.Flags := -O3 -DNDEBUG -felide-constructors -finline-functions -pg - C.Flags := -O3 -DNDEBUG -pg - LD.Flags := -O3 -DNDEBUG -pg + CXX.Flags := -O3 -felide-constructors -finline-functions -pg + C.Flags := -O3 -pg + LD.Flags := -O3 -pg else ifdef ENABLE_OPTIMIZED BuildMode := Release @@ -211,19 +210,30 @@ ifneq ($(OS),FreeBSD) OmitFramePointer := -fomit-frame-pointer endif - CXX.Flags := -O3 -DNDEBUG -finline-functions -felide-constructors \ - $(OmitFramePointer) - C.Flags := -O3 -DNDEBUG $(OmitFramePointer) - LD.Flags := -O3 -DNDEBUG + CXX.Flags := -O3 -finline-functions -felide-constructors $(OmitFramePointer) + C.Flags := -O3 $(OmitFramePointer) + LD.Flags := -O3 else BuildMode := Debug - CXX.Flags := -g -D_DEBUG - C.Flags := -g -D_DEBUG - LD.Flags := -g -D_DEBUG + CXX.Flags := -g + C.Flags := -g + LD.Flags := -g KEEP_SYMBOLS := 1 + # Assertions default to ON for debug builds. + ENABLE_ASSERTIONS := 1 endif endif +# If this is a debug build or if ENABLE_ASSERTIONS=1 is specified on the make +# command line, enable assertions. +ifdef ENABLE_ASSERTIONS + CXX.Flags += -D_DEBUG + C.Flags += -D_DEBUG +else + CXX.Flags += -DNDEBUG + C.Flags += -DNDEBUG +endif + CXX.Flags += $(CXXFLAGS) C.Flags += $(CFLAGS) CPP.Flags += $(CPPFLAGS) From lattner at cs.uiuc.edu Mon Mar 20 19:11:08 2006 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Mon, 20 Mar 2006 19:11:08 -0600 Subject: [llvm-commits] CVS: llvm/docs/GettingStarted.html MakefileGuide.html Message-ID: <200603210111.TAA08535@zion.cs.uiuc.edu> Changes in directory llvm/docs: GettingStarted.html updated: 1.126 -> 1.127 MakefileGuide.html updated: 1.28 -> 1.29 --- Log message: Document ENABLE_ASSERTIONS=1 --- Diffs of the changes: (+11 -2) GettingStarted.html | 7 ++++++- MakefileGuide.html | 6 +++++- 2 files changed, 11 insertions(+), 2 deletions(-) Index: llvm/docs/GettingStarted.html diff -u llvm/docs/GettingStarted.html:1.126 llvm/docs/GettingStarted.html:1.127 --- llvm/docs/GettingStarted.html:1.126 Mon Mar 13 23:39:39 2006 +++ llvm/docs/GettingStarted.html Mon Mar 20 19:10:57 2006 @@ -955,6 +955,11 @@ Perform a Release (Optimized) build.

+

gmake ENABLE_OPTIMIZED=1 ENABLE_ASSERTIONS=1 +
+ Perform a Release (Optimized) build with assertions enabled. +

+

gmake ENABLE_PROFILING=1
Perform a Profiling build. @@ -1546,7 +1551,7 @@ Chris Lattner
Reid Spencer
The LLVM Compiler Infrastructure
- Last modified: $Date: 2006/03/14 05:39:39 $ + Last modified: $Date: 2006/03/21 01:10:57 $ Index: llvm/docs/MakefileGuide.html diff -u llvm/docs/MakefileGuide.html:1.28 llvm/docs/MakefileGuide.html:1.29 --- llvm/docs/MakefileGuide.html:1.28 Mon Mar 13 23:39:39 2006 +++ llvm/docs/MakefileGuide.html Mon Mar 20 19:10:57 2006 @@ -632,6 +632,10 @@ to the compilers and linkers to ensure that profile data can be collected from the tools built. Use the gprof tool to analyze the output from the profiled tools (gmon.out).
+
ENABLE_ASSERTIONS
+
If set to any value, causes the build to enable assertions, even if + building a release or profile build. This is slower than a release build but + far faster than a debug build.
EXPERIMENTAL_DIRS
Specify a set of directories that should be built, but if they fail, it should not cause the build to fail. Note that this should only be used @@ -991,7 +995,7 @@ Reid Spencer
The LLVM Compiler Infrastructure
- Last modified: $Date: 2006/03/14 05:39:39 $ + Last modified: $Date: 2006/03/21 01:10:57 $ From reid at x10sys.com Mon Mar 20 19:21:51 2006 From: reid at x10sys.com (Reid Spencer) Date: Mon, 20 Mar 2006 19:21:51 -0600 Subject: [llvm-commits] CVS: llvm/utils/NightlyTestTemplate.html NightlyTest.pl Message-ID: <200603210121.TAA08630@zion.cs.uiuc.edu> Changes in directory llvm/utils: NightlyTestTemplate.html updated: 1.44 -> 1.45 NightlyTest.pl updated: 1.105 -> 1.106 --- Log message: Cause the various warnings list to be generated via a
    list with text enclosed in . This ensures that (a) the text is in a fixed width font (to indicated generated text) and (b) the text wraps without causing the page width to be extended. The main result of this is that the report will wrap to conform to the window size in which it is displayed instead of having a very wide length if a warning message is long. --- Diffs of the changes: (+25 -9) NightlyTest.pl | 24 ++++++++++++++++++++---- NightlyTestTemplate.html | 10 +++++----- 2 files changed, 25 insertions(+), 9 deletions(-) Index: llvm/utils/NightlyTestTemplate.html diff -u llvm/utils/NightlyTestTemplate.html:1.44 llvm/utils/NightlyTestTemplate.html:1.45 --- llvm/utils/NightlyTestTemplate.html:1.44 Mon Mar 13 23:54:52 2006 +++ llvm/utils/NightlyTestTemplate.html Mon Mar 20 19:21:39 2006 @@ -77,7 +77,7 @@

Warnings during the build:

-

$WarningsList

+$WarningsList

@@ -95,10 +95,10 @@

Changes to Warnings:

-
    -
  • Warnings Added: $WarningsAdded -
  • Warnings Removed: $WarningsRemoved -

+

Warnings Added:

+$WarningsAdded +

Warnings Removed:

+$WarningsRemoved

Changes in the test suite:

    Index: llvm/utils/NightlyTest.pl diff -u llvm/utils/NightlyTest.pl:1.105 llvm/utils/NightlyTest.pl:1.106 --- llvm/utils/NightlyTest.pl:1.105 Fri Mar 17 11:43:01 2006 +++ llvm/utils/NightlyTest.pl Mon Mar 20 19:21:39 2006 @@ -151,7 +151,21 @@ sub AddPreTag { # Add pre tags around nonempty list, or convert to "none" $_ = shift; - if (length) { return "
      $_
    "; } else { "none
    "; } + if (length) { return "
    $_
    "; } else { "none
    "; } +} + +sub ArrayToList { # Add
  • tags around nonempty list or convert to "none" + my $result = ""; + if (scalar @_) { + $result = "
      "; + foreach $item (@_) { + $result .= "
    • $item
      • "; + } + $result .= "
    "; + } else { + $result = "

    none

    "; + } + return $result; } sub ChangeDir { # directory, logical name @@ -528,7 +542,7 @@ } } my $WarningsFile = join "\n", @Warnings; -my $WarningsList = AddPreTag $WarningsFile; +my $WarningsList = ArrayToList @Warnings; $WarningsFile =~ s/:[0-9]+:/::/g; # Emit the warnings file, so we can diff... @@ -539,8 +553,10 @@ print "ADDED WARNINGS:\n$WarningsAdded\n\n" if (length $WarningsAdded); print "REMOVED WARNINGS:\n$WarningsRemoved\n\n" if (length $WarningsRemoved); -$WarningsAdded = AddPreTag $WarningsAdded; -$WarningsRemoved = AddPreTag $WarningsRemoved; +my @TmpWarningsAdded = split "\n", $WarningsAdded; +my @TmpWarningsRemoved = split "\n", $WarningsRemoved; +$WarningsAdded = ArrayToList @TmpWarningsAdded; +$WarningsRemoved = ArrayToList @TmpWarningsRemoved; # # Get some statistics about CVS commits over the current day... From lattner at cs.uiuc.edu Tue Mar 21 00:37:52 2006 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Tue, 21 Mar 2006 00:37:52 -0600 Subject: [llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp Message-ID: <200603210637.AAA10637@zion.cs.uiuc.edu> Changes in directory llvm/lib/Target/PowerPC: PPCISelDAGToDAG.cpp updated: 1.173 -> 1.174 --- Log message: With Evan's latest tblgen patch, this code is obsolete, thanks Evan! --- Diffs of the changes: (+0 -16) PPCISelDAGToDAG.cpp | 16 ---------------- 1 files changed, 16 deletions(-) Index: llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp diff -u llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp:1.173 llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp:1.174 --- llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp:1.173 Mon Mar 20 16:38:22 2006 +++ llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp Tue Mar 21 00:37:40 2006 @@ -944,22 +944,6 @@ switch (N->getOpcode()) { default: break; - case ISD::VECTOR_SHUFFLE: - // FIXME: This should be autogenerated from the .td file, it is here for now - // due to bugs in tblgen. - if (Op.getOperand(1).getOpcode() == ISD::UNDEF && - (Op.getValueType() == MVT::v4f32 || Op.getValueType() == MVT::v4i32) && - PPC::isSplatShuffleMask(Op.getOperand(2).Val)) { - SDOperand N0; - Select(N0, N->getOperand(0)); - Result = CodeGenMap[Op] = - SDOperand(CurDAG->getTargetNode(PPC::VSPLTW, MVT::v4f32, - getI32Imm(PPC::getVSPLTImmediate(Op.getOperand(2).Val)), - N0), 0); - return; - } - assert(0 && "ILLEGAL VECTOR_SHUFFLE!"); - case ISD::SETCC: Result = SelectSETCC(Op); return; From lattner at cs.uiuc.edu Tue Mar 21 00:43:10 2006 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Tue, 21 Mar 2006 00:43:10 -0600 Subject: [llvm-commits] CVS: llvm/utils/TableGen/DAGISelEmitter.cpp Message-ID: <200603210643.AAA10708@zion.cs.uiuc.edu> Changes in directory llvm/utils/TableGen: DAGISelEmitter.cpp updated: 1.180 -> 1.181 --- Log message: minor code simplification --- Diffs of the changes: (+5 -11) DAGISelEmitter.cpp | 16 +++++----------- 1 files changed, 5 insertions(+), 11 deletions(-) Index: llvm/utils/TableGen/DAGISelEmitter.cpp diff -u llvm/utils/TableGen/DAGISelEmitter.cpp:1.180 llvm/utils/TableGen/DAGISelEmitter.cpp:1.181 --- llvm/utils/TableGen/DAGISelEmitter.cpp:1.180 Mon Mar 20 16:53:06 2006 +++ llvm/utils/TableGen/DAGISelEmitter.cpp Tue Mar 21 00:42:58 2006 @@ -698,17 +698,11 @@ if (getNumChildren() != 1) TP.error("Node transform '" + getOperator()->getName() + "' requires one operand!"); - unsigned char ExtType0 = getExtTypeNum(0); - unsigned char ChildExtType0 = getChild(0)->getExtTypeNum(0); - if (ExtType0 == MVT::isInt || - ExtType0 == MVT::isFP || - ExtType0 == MVT::isUnknown || - ChildExtType0 == MVT::isInt || - ChildExtType0 == MVT::isFP || - ChildExtType0 == MVT::isUnknown) { - // If either the output or input of the xform does not have exact - // type info. We assume they must be the same. Otherwise, it is perfectly - // legal to transform from one type to a completely different type. + + // If either the output or input of the xform does not have exact + // type info. We assume they must be the same. Otherwise, it is perfectly + // legal to transform from one type to a completely different type. + if (!hasTypeSet() || !getChild(0)->hasTypeSet()) { bool MadeChange = UpdateNodeType(getChild(0)->getExtTypes(), TP); MadeChange |= getChild(0)->UpdateNodeType(getExtTypes(), TP); return MadeChange; From evan.cheng at apple.com Tue Mar 21 01:09:47 2006 From: evan.cheng at apple.com (Evan Cheng) Date: Tue, 21 Mar 2006 01:09:47 -0600 Subject: [llvm-commits] CVS: llvm/lib/Target/X86/X86InstrInfo.cpp X86InstrMMX.td X86InstrSSE.td Message-ID: <200603210709.BAA10828@zion.cs.uiuc.edu> Changes in directory llvm/lib/Target/X86: X86InstrInfo.cpp updated: 1.45 -> 1.46 X86InstrMMX.td updated: 1.4 -> 1.5 X86InstrSSE.td updated: 1.10 -> 1.11 --- Log message: - Remove scalar to vector pseudo ops. They are just wrong. - Handle FR32 to VR128:v4f32 and FR64 to VR128:v2f64 with aliases of MOVAPS and MOVAPD. Mark them as move instructions and *hope* they will be deleted. --- Diffs of the changes: (+17 -56) X86InstrInfo.cpp | 3 ++- X86InstrMMX.td | 19 ------------------- X86InstrSSE.td | 51 +++++++++++++++------------------------------------ 3 files changed, 17 insertions(+), 56 deletions(-) Index: llvm/lib/Target/X86/X86InstrInfo.cpp diff -u llvm/lib/Target/X86/X86InstrInfo.cpp:1.45 llvm/lib/Target/X86/X86InstrInfo.cpp:1.46 --- llvm/lib/Target/X86/X86InstrInfo.cpp:1.45 Thu Feb 16 16:45:16 2006 +++ llvm/lib/Target/X86/X86InstrInfo.cpp Tue Mar 21 01:09:35 2006 @@ -30,7 +30,8 @@ if (oc == X86::MOV8rr || oc == X86::MOV16rr || oc == X86::MOV32rr || oc == X86::FpMOV || oc == X86::MOVSSrr || oc == X86::MOVSDrr || oc == X86::FsMOVAPSrr || oc == X86::FsMOVAPDrr || - oc == X86::MOVAPSrr || oc == X86::MOVAPDrr) { + oc == X86::MOVAPSrr || oc == X86::MOVAPDrr || + oc == X86::FR32ToV4F32 || oc == X86::FR64ToV2F64) { assert(MI.getNumOperands() == 2 && MI.getOperand(0).isRegister() && MI.getOperand(1).isRegister() && Index: llvm/lib/Target/X86/X86InstrMMX.td diff -u llvm/lib/Target/X86/X86InstrMMX.td:1.4 llvm/lib/Target/X86/X86InstrMMX.td:1.5 --- llvm/lib/Target/X86/X86InstrMMX.td:1.4 Mon Mar 20 18:33:35 2006 +++ llvm/lib/Target/X86/X86InstrMMX.td Tue Mar 21 01:09:35 2006 @@ -22,24 +22,6 @@ def : Pat<(v4i16 (undef)), (IMPLICIT_DEF_VR64)>, Requires<[HasMMX]>; def : Pat<(v2i32 (undef)), (IMPLICIT_DEF_VR64)>, Requires<[HasMMX]>; -def SCALAR_TO_VECTOR_V8I8 : I<0, Pseudo, (ops VR64:$dst, R8:$src), - "#SCALAR_TO_VECTOR $src", - [(set VR64:$dst, - (v8i8 (scalar_to_vector R8:$src)))]>, - Requires<[HasMMX]>; - -def SCALAR_TO_VECTOR_V4I16 : I<0, Pseudo, (ops VR64:$dst, R16:$src), - "#SCALAR_TO_VECTOR $src", - [(set VR64:$dst, - (v4i16 (scalar_to_vector R16:$src)))]>, - Requires<[HasMMX]>; - -def SCALAR_TO_VECTOR_V2I32 : I<0, Pseudo, (ops VR64:$dst, R32:$src), - "#SCALAR_TO_VECTOR $src", - [(set VR64:$dst, - (v2i32 (scalar_to_vector R32:$src)))]>, - Requires<[HasMMX]>; - // Move Instructions def MOVD64rr : I<0x6E, MRMSrcReg, (ops VR64:$dst, R32:$src), "movd {$src, $dst|$dst, $src}", []>, TB, @@ -60,4 +42,3 @@ def MOVQ64mr : I<0x7F, MRMDestMem, (ops i64mem:$dst, VR64:$src), "movq {$src, $dst|$dst, $src}", []>, TB, Requires<[HasMMX]>; - Index: llvm/lib/Target/X86/X86InstrSSE.td diff -u llvm/lib/Target/X86/X86InstrSSE.td:1.10 llvm/lib/Target/X86/X86InstrSSE.td:1.11 --- llvm/lib/Target/X86/X86InstrSSE.td:1.10 Mon Mar 20 18:33:35 2006 +++ llvm/lib/Target/X86/X86InstrSSE.td Tue Mar 21 01:09:35 2006 @@ -353,42 +353,6 @@ def : Pat<(v4i32 (undef)), (IMPLICIT_DEF_VR128)>, Requires<[HasSSE2]>; def : Pat<(v2i64 (undef)), (IMPLICIT_DEF_VR128)>, Requires<[HasSSE2]>; -def SCALAR_TO_VECTOR_V4F32 : I<0, Pseudo, (ops VR128:$dst, FR32:$src), - "#SCALAR_TO_VECTOR $src", - [(set VR128:$dst, - (v4f32 (scalar_to_vector FR32:$src)))]>, - Requires<[HasSSE1]>; - -def SCALAR_TO_VECTOR_V2F64 : I<0, Pseudo, (ops VR128:$dst, FR64:$src), - "#SCALAR_TO_VECTOR $src", - [(set VR128:$dst, - (v2f64 (scalar_to_vector FR64:$src)))]>, - Requires<[HasSSE2]>; - -def SCALAR_TO_VECTOR_V16I8 : I<0, Pseudo, (ops VR128:$dst, R8:$src), - "#SCALAR_TO_VECTOR $src", - [(set VR128:$dst, - (v16i8 (scalar_to_vector R8:$src)))]>, - Requires<[HasSSE2]>; - -def SCALAR_TO_VECTOR_V8I16 : I<0, Pseudo, (ops VR128:$dst, R16:$src), - "#SCALAR_TO_VECTOR $src", - [(set VR128:$dst, - (v8i16 (scalar_to_vector R16:$src)))]>, - Requires<[HasSSE2]>; - -def SCALAR_TO_VECTOR_V4I32 : I<0, Pseudo, (ops VR128:$dst, R32:$src), - "#SCALAR_TO_VECTOR $src", - [(set VR128:$dst, - (v4i32 (scalar_to_vector R32:$src)))]>, - Requires<[HasSSE2]>; - -def SCALAR_TO_VECTOR_V2I64 : I<0, Pseudo, (ops VR128:$dst, VR64:$src), - "#SCALAR_TO_VECTOR $src", - [(set VR128:$dst, - (v2i64 (scalar_to_vector VR64:$src)))]>, - Requires<[HasSSE2]>; - // Move Instructions def MOVAPSrr : PSI<0x28, MRMSrcReg, (ops VR128:$dst, VR128:$src), "movaps {$src, $dst|$dst, $src}", []>; @@ -752,3 +716,18 @@ def MOVQ128mr : PDI<0xD6, MRMSrcMem, (ops i64mem:$dst, VR128:$src), "movq {$src, $dst|$dst, $src}", []>; + + +//===----------------------------------------------------------------------===// +// Alias Instructions +//===----------------------------------------------------------------------===// + +def FR32ToV4F32 : PSI<0x28, MRMSrcReg, (ops VR128:$dst, FR32:$src), + "movaps {$src, $dst|$dst, $src}", + [(set VR128:$dst, + (v4f32 (scalar_to_vector FR32:$src)))]>; + +def FR64ToV2F64 : PDI<0x28, MRMSrcReg, (ops VR128:$dst, FR64:$src), + "movapd {$src, $dst|$dst, $src}", + [(set VR128:$dst, + (v2f64 (scalar_to_vector FR64:$src)))]>; From evan.cheng at apple.com Tue Mar 21 01:13:08 2006 From: evan.cheng at apple.com (Evan Cheng) Date: Tue, 21 Mar 2006 01:13:08 -0600 Subject: [llvm-commits] CVS: llvm/lib/Target/X86/README.txt Message-ID: <200603210713.BAA10860@zion.cs.uiuc.edu> Changes in directory llvm/lib/Target/X86: README.txt updated: 1.68 -> 1.69 --- Log message: Add a note about x86 register coallescing --- Diffs of the changes: (+2 -0) README.txt | 2 ++ 1 files changed, 2 insertions(+) Index: llvm/lib/Target/X86/README.txt diff -u llvm/lib/Target/X86/README.txt:1.68 llvm/lib/Target/X86/README.txt:1.69 --- llvm/lib/Target/X86/README.txt:1.68 Sun Mar 19 16:27:41 2006 +++ llvm/lib/Target/X86/README.txt Tue Mar 21 01:12:57 2006 @@ -644,3 +644,5 @@ //===---------------------------------------------------------------------===// +Teach the coallescer to coales vregs of different register classes. e.g. FR32 / +FR64 to VR128. From evan.cheng at apple.com Tue Mar 21 01:18:38 2006 From: evan.cheng at apple.com (Evan Cheng) Date: Tue, 21 Mar 2006 01:18:38 -0600 Subject: [llvm-commits] CVS: llvm/lib/Target/X86/README.txt Message-ID: <200603210718.BAA10881@zion.cs.uiuc.edu> Changes in directory llvm/lib/Target/X86: README.txt updated: 1.69 -> 1.70 --- Log message: Combine 2 entries --- Diffs of the changes: (+6 -8) README.txt | 14 ++++++-------- 1 files changed, 6 insertions(+), 8 deletions(-) Index: llvm/lib/Target/X86/README.txt diff -u llvm/lib/Target/X86/README.txt:1.69 llvm/lib/Target/X86/README.txt:1.70 --- llvm/lib/Target/X86/README.txt:1.69 Tue Mar 21 01:12:57 2006 +++ llvm/lib/Target/X86/README.txt Tue Mar 21 01:18:26 2006 @@ -485,6 +485,12 @@ //===---------------------------------------------------------------------===// +Should generate min/max for stuff like: + +void minf(float a, float b, float *X) { + *X = a <= b ? a : b; +} + Make use of floating point min / max instructions. Perhaps introduce ISD::FMIN and ISD::FMAX node types? @@ -636,13 +642,5 @@ //===---------------------------------------------------------------------===// -Should generate min/max for stuff like: - -void minf(float a, float b, float *X) { - *X = a <= b ? a : b; -} - -//===---------------------------------------------------------------------===// - Teach the coallescer to coales vregs of different register classes. e.g. FR32 / FR64 to VR128. From lattner at cs.uiuc.edu Tue Mar 21 11:21:25 2006 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Tue, 21 Mar 2006 11:21:25 -0600 Subject: [llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp Message-ID: <200603211721.LAA25460@zion.cs.uiuc.edu> Changes in directory llvm/lib/Target/PowerPC: PPCAsmPrinter.cpp updated: 1.158 -> 1.159 --- Log message: Print absolute memory references like this: lwz r2, 8(0) instead of this: lwz r2, 8(r0) This fixes the llc/llc-beta failures on PPC last night. --- Diffs of the changes: (+5 -1) PPCAsmPrinter.cpp | 6 +++++- 1 files changed, 5 insertions(+), 1 deletion(-) Index: llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp diff -u llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp:1.158 llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp:1.159 --- llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp:1.158 Mon Mar 13 17:20:37 2006 +++ llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp Tue Mar 21 11:21:13 2006 @@ -194,7 +194,11 @@ void printMemRegImm(const MachineInstr *MI, unsigned OpNo) { printSymbolLo(MI, OpNo); O << '('; - printOperand(MI, OpNo+1); + if (MI->getOperand(OpNo+1).isRegister() && + MI->getOperand(OpNo+1).getReg() == PPC::R0) + O << "0"; + else + printOperand(MI, OpNo+1); O << ')'; } void printMemRegReg(const MachineInstr *MI, unsigned OpNo) { From lattner at cs.uiuc.edu Tue Mar 21 12:27:39 2006 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Tue, 21 Mar 2006 12:27:39 -0600 Subject: [llvm-commits] CVS: llvm/test/Regression/CodeGen/Generic/vector.ll Message-ID: <200603211827.MAA26481@zion.cs.uiuc.edu> Changes in directory llvm/test/Regression/CodeGen/Generic: vector.ll updated: 1.5 -> 1.6 --- Log message: Add an integer splat test --- Diffs of the changes: (+19 -0) vector.ll | 19 +++++++++++++++++++ 1 files changed, 19 insertions(+) Index: llvm/test/Regression/CodeGen/Generic/vector.ll diff -u llvm/test/Regression/CodeGen/Generic/vector.ll:1.5 llvm/test/Regression/CodeGen/Generic/vector.ll:1.6 --- llvm/test/Regression/CodeGen/Generic/vector.ll:1.5 Sat Mar 18 23:46:51 2006 +++ llvm/test/Regression/CodeGen/Generic/vector.ll Tue Mar 21 12:27:27 2006 @@ -6,6 +6,7 @@ %f1 = type <1 x float> %f2 = type <2 x float> %f4 = type <4 x float> +%i4 = type <4 x int> %f8 = type <8 x float> implementation @@ -44,6 +45,13 @@ ret void } +void %test_fmul(%f8 *%P, %f8* %Q, %f8 *%S) { + %p = load %f8* %P + %q = load %f8* %Q + %R = mul %f8 %p, %q + store %f8 %R, %f8 *%S + ret void +} ;;; TEST VECTOR CONSTRUCTS void %test_cst(%f4 *%P, %f4 *%S) { @@ -98,3 +106,14 @@ ret void } +void %splat_i4(%i4* %P, %i4* %Q, int %X) { + %tmp = insertelement %i4 undef, int %X, uint 0 + %tmp2 = insertelement %i4 %tmp, int %X, uint 1 + %tmp4 = insertelement %i4 %tmp2, int %X, uint 2 + %tmp6 = insertelement %i4 %tmp4, int %X, uint 3 + %q = load %i4* %Q + %R = add %i4 %q, %tmp6 + store %i4 %R, %i4* %P + ret void +} + From natebegeman at mac.com Tue Mar 21 12:58:31 2006 From: natebegeman at mac.com (Nate Begeman) Date: Tue, 21 Mar 2006 12:58:31 -0600 Subject: [llvm-commits] CVS: llvm/lib/Target/PowerPC/README.txt Message-ID: <200603211858.MAA27446@zion.cs.uiuc.edu> Changes in directory llvm/lib/Target/PowerPC: README.txt updated: 1.77 -> 1.78 --- Log message: Update readme --- Diffs of the changes: (+34 -0) README.txt | 34 ++++++++++++++++++++++++++++++++++ 1 files changed, 34 insertions(+) Index: llvm/lib/Target/PowerPC/README.txt diff -u llvm/lib/Target/PowerPC/README.txt:1.77 llvm/lib/Target/PowerPC/README.txt:1.78 --- llvm/lib/Target/PowerPC/README.txt:1.77 Mon Mar 20 18:47:09 2006 +++ llvm/lib/Target/PowerPC/README.txt Tue Mar 21 12:58:20 2006 @@ -549,3 +549,37 @@ When -ffast-math is on, we can use 0.0. ===-------------------------------------------------------------------------=== + +float foo(float X) { return (int)(X); } + +Currently produces + +_foo: + lis r2, ha16(LCPI1_0) + lis r3, 17200 + fctiwz f0, f1 + stfd f0, -8(r1) + lwz r4, -4(r1) + xoris r4, r4, 32768 + stw r4, -12(r1) + stw r3, -16(r1) + lfs f0, lo16(LCPI1_0)(r2) + lfd f1, -16(r1) + fsub f0, f1, f0 + frsp f1, f0 + blr + +When we have ppc64 working properly, it could produce the nicer code: + +_foo: + fctiwz f0, f1 + stfd f0, -8(r1) + lwz r4, -4(r1) + extsh r4, r4 + std r4, -16(r1) + lfd f1, -16(r1) + fcfid f0, f0 + frsp f0, f0 + blr + +Note: this would speed up SingleSource/Misc/pi by about 30% From lattner at cs.uiuc.edu Tue Mar 21 13:20:49 2006 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Tue, 21 Mar 2006 13:20:49 -0600 Subject: [llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp SelectionDAG.cpp SelectionDAGISel.cpp Message-ID: <200603211920.NAA27818@zion.cs.uiuc.edu> Changes in directory llvm/lib/CodeGen/SelectionDAG: LegalizeDAG.cpp updated: 1.326 -> 1.327 SelectionDAG.cpp updated: 1.276 -> 1.277 SelectionDAGISel.cpp updated: 1.197 -> 1.198 --- Log message: Add a hacky workaround for crashes due to vectors live across blocks. Note that this code won't work for vectors that aren't legal on the target. Improvements coming. --- Diffs of the changes: (+31 -1) LegalizeDAG.cpp | 3 +++ SelectionDAG.cpp | 3 ++- SelectionDAGISel.cpp | 26 ++++++++++++++++++++++++++ 3 files changed, 31 insertions(+), 1 deletion(-) Index: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp diff -u llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.326 llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.327 --- llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.326 Sun Mar 19 19:52:29 2006 +++ llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp Tue Mar 21 13:20:37 2006 @@ -4262,6 +4262,9 @@ /// type for the result. SDOperand SelectionDAGLegalize::PackVectorOp(SDOperand Op, MVT::ValueType NewVT) { + // FIXME: THIS IS A TEMPORARY HACK + if (Op.getValueType() == NewVT) return Op; + assert(Op.getValueType() == MVT::Vector && "Bad PackVectorOp invocation!"); SDNode *Node = Op.Val; Index: llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp diff -u llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp:1.276 llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp:1.277 --- llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp:1.276 Sun Mar 19 17:56:04 2006 +++ llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp Tue Mar 21 13:20:37 2006 @@ -1086,7 +1086,8 @@ break; case ISD::BIT_CONVERT: // Basic sanity checking. - assert(MVT::getSizeInBits(VT) == MVT::getSizeInBits(Operand.getValueType()) + assert((Operand.getValueType() == MVT::Vector || // FIXME: This is a hack. + MVT::getSizeInBits(VT) == MVT::getSizeInBits(Operand.getValueType())) && "Cannot BIT_CONVERT between two different types!"); if (VT == Operand.getValueType()) return Operand; // noop conversion. if (OpOpcode == ISD::BIT_CONVERT) // bitconv(bitconv(x)) -> bitconv(x) Index: llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp diff -u llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.197 llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.198 --- llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.197 Sat Mar 18 19:17:20 2006 +++ llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp Tue Mar 21 13:20:37 2006 @@ -2285,6 +2285,32 @@ SelectionDAG &DAG = SDL.DAG; if (SrcVT == DestVT) { return DAG.getCopyToReg(SDL.getRoot(), Reg, Op); + } else if (SrcVT == MVT::Vector) { + // FIXME: THIS DOES NOT SUPPORT PROMOTED/EXPANDED ELEMENTS! + + // Figure out the right, legal destination reg to copy into. + const PackedType *PTy = cast(V->getType()); + unsigned NumElts = PTy->getNumElements(); + MVT::ValueType EltTy = TLI.getValueType(PTy->getElementType()); + + unsigned NumVectorRegs = 1; + + // Divide the input until we get to a supported size. This will always + // end with a scalar if the target doesn't support vectors. + while (NumElts > 1 && !TLI.isTypeLegal(getVectorType(EltTy, NumElts))) { + NumElts >>= 1; + NumVectorRegs <<= 1; + } + + MVT::ValueType VT; + if (NumElts == 1) + VT = EltTy; + else + VT = getVectorType(EltTy, NumElts); + + // FIXME: THIS ASSUMES THAT THE INPUT VECTOR WILL BE LEGAL! + Op = DAG.getNode(ISD::BIT_CONVERT, VT, Op); + return DAG.getCopyToReg(SDL.getRoot(), Reg, Op); } else if (SrcVT < DestVT) { // The src value is promoted to the register. if (MVT::isFloatingPoint(SrcVT)) From lattner at cs.uiuc.edu Tue Mar 21 14:19:49 2006 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Tue, 21 Mar 2006 14:19:49 -0600 Subject: [llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCCodeEmitter.cpp Message-ID: <200603212019.OAA28392@zion.cs.uiuc.edu> Changes in directory llvm/lib/Target/PowerPC: PPCCodeEmitter.cpp updated: 1.48 -> 1.49 --- Log message: Don't emit pseudo instructions! --- Diffs of the changes: (+1 -0) PPCCodeEmitter.cpp | 1 + 1 files changed, 1 insertion(+) Index: llvm/lib/Target/PowerPC/PPCCodeEmitter.cpp diff -u llvm/lib/Target/PowerPC/PPCCodeEmitter.cpp:1.48 llvm/lib/Target/PowerPC/PPCCodeEmitter.cpp:1.49 --- llvm/lib/Target/PowerPC/PPCCodeEmitter.cpp:1.48 Fri Mar 10 14:19:50 2006 +++ llvm/lib/Target/PowerPC/PPCCodeEmitter.cpp Tue Mar 21 14:19:37 2006 @@ -132,6 +132,7 @@ case PPC::IMPLICIT_DEF_GPR: case PPC::IMPLICIT_DEF_F8: case PPC::IMPLICIT_DEF_F4: + case PPC::IMPLICIT_DEF_VRRC: break; // pseudo opcode, no side effects case PPC::MovePCtoLR: assert(0 && "CodeEmitter does not support MovePCtoLR instruction"); From lattner at cs.uiuc.edu Tue Mar 21 14:43:20 2006 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Tue, 21 Mar 2006 14:43:20 -0600 Subject: [llvm-commits] CVS: llvm/include/llvm/CodeGen/SelectionDAGNodes.h Message-ID: <200603212043.OAA29379@zion.cs.uiuc.edu> Changes in directory llvm/include/llvm/CodeGen: SelectionDAGNodes.h updated: 1.116 -> 1.117 --- Log message: add some nodes for extractelement --- Diffs of the changes: (+10 -0) SelectionDAGNodes.h | 10 ++++++++++ 1 files changed, 10 insertions(+) Index: llvm/include/llvm/CodeGen/SelectionDAGNodes.h diff -u llvm/include/llvm/CodeGen/SelectionDAGNodes.h:1.116 llvm/include/llvm/CodeGen/SelectionDAGNodes.h:1.117 --- llvm/include/llvm/CodeGen/SelectionDAGNodes.h:1.116 Sun Mar 19 17:42:51 2006 +++ llvm/include/llvm/CodeGen/SelectionDAGNodes.h Tue Mar 21 14:43:08 2006 @@ -156,6 +156,16 @@ /// INSERT_VECTOR_ELT(VECTOR, VAL, IDX) - Returns VECTOR (a legal packed /// type) with the element at IDX replaced with VAL. INSERT_VECTOR_ELT, + + /// VEXTRACT_VECTOR_ELT(VECTOR, IDX) - Returns a single element from VECTOR + /// (an MVT::Vector value) identified by the (potentially variable) element + /// number IDX. + VEXTRACT_VECTOR_ELT, + + /// EXTRACT_VECTOR_ELT(VECTOR, IDX) - Returns a single element from VECTOR + /// (a legal packed type vector) identified by the (potentially variable) + /// element number IDX. + EXTRACT_VECTOR_ELT, /// VECTOR_SHUFFLE(VEC1, VEC2, SHUFFLEVEC) - Returns a vector, of the same /// type as VEC1/VEC2. SHUFFLEVEC is a BUILD_VECTOR of constant int values From lattner at cs.uiuc.edu Tue Mar 21 14:44:23 2006 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Tue, 21 Mar 2006 14:44:23 -0600 Subject: [llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp SelectionDAG.cpp SelectionDAGISel.cpp Message-ID: <200603212044.OAA29456@zion.cs.uiuc.edu> Changes in directory llvm/lib/CodeGen/SelectionDAG: LegalizeDAG.cpp updated: 1.327 -> 1.328 SelectionDAG.cpp updated: 1.277 -> 1.278 SelectionDAGISel.cpp updated: 1.198 -> 1.199 --- Log message: add some trivial support for extractelement. --- Diffs of the changes: (+62 -2) LegalizeDAG.cpp | 52 ++++++++++++++++++++++++++++++++++++++++++++++++++- SelectionDAG.cpp | 2 + SelectionDAGISel.cpp | 10 ++++++++- 3 files changed, 62 insertions(+), 2 deletions(-) Index: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp diff -u llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.327 llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.328 --- llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.327 Tue Mar 21 13:20:37 2006 +++ llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp Tue Mar 21 14:44:12 2006 @@ -821,6 +821,56 @@ if (Tmp1.Val) Result = Tmp1; } break; + + case ISD::EXTRACT_VECTOR_ELT: + Tmp1 = LegalizeOp(Node->getOperand(0)); + Tmp2 = LegalizeOp(Node->getOperand(1)); + Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2); + // FIXME: LOWER. + break; + + case ISD::VEXTRACT_VECTOR_ELT: + // We know that operand #0 is the Vec vector. If the index is a constant + // or if the invec is a supported hardware type, we can use it. Otherwise, + // lower to a store then an indexed load. + Tmp1 = Node->getOperand(0); + Tmp2 = LegalizeOp(Node->getOperand(1)); + + SDNode *InVal = Tmp1.Val; + unsigned NumElems = cast(*(InVal->op_end()-2))->getValue(); + MVT::ValueType EVT = cast(*(InVal->op_end()-1))->getVT(); + + // Figure out if there is a Packed type corresponding to this Vector + // type. If so, convert to the packed type. + MVT::ValueType TVT = MVT::getVectorType(EVT, NumElems); + if (TVT != MVT::Other && TLI.isTypeLegal(TVT)) { + // Turn this into a packed extract_vector_elt operation. + Tmp1 = PackVectorOp(Tmp1, TVT); + Result = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, Node->getValueType(0), + Tmp1, Tmp2); + break; + } else if (NumElems == 1) { + // This must be an access of the only element. + Result = PackVectorOp(Tmp1, EVT); + break; + } else if (ConstantSDNode *CIdx = dyn_cast(Tmp2)) { + SDOperand Lo, Hi; + SplitVectorOp(Tmp1, Lo, Hi); + if (CIdx->getValue() < NumElems/2) { + Tmp1 = Lo; + } else { + Tmp1 = Hi; + Tmp2 = DAG.getConstant(CIdx->getValue() - NumElems/2, + Tmp2.getValueType()); + } + + // It's now an extract from the appropriate high or low part. + Result = LegalizeOp(DAG.UpdateNodeOperands(Result, Tmp1, Tmp2)); + } else { + // FIXME: IMPLEMENT STORE/LOAD lowering. + assert(0 && "unimp!"); + } + break; case ISD::CALLSEQ_START: { SDNode *CallEnd = FindCallEndFromCallStart(Node); @@ -4264,7 +4314,7 @@ MVT::ValueType NewVT) { // FIXME: THIS IS A TEMPORARY HACK if (Op.getValueType() == NewVT) return Op; - + assert(Op.getValueType() == MVT::Vector && "Bad PackVectorOp invocation!"); SDNode *Node = Op.Val; Index: llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp diff -u llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp:1.277 llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp:1.278 --- llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp:1.277 Tue Mar 21 13:20:37 2006 +++ llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp Tue Mar 21 14:44:12 2006 @@ -2671,6 +2671,8 @@ case ISD::SELECT_CC: return "select_cc"; case ISD::INSERT_VECTOR_ELT: return "insert_vector_elt"; case ISD::VINSERT_VECTOR_ELT: return "vinsert_vector_elt"; + case ISD::EXTRACT_VECTOR_ELT: return "extract_vector_elt"; + case ISD::VEXTRACT_VECTOR_ELT: return "vextract_vector_elt"; case ISD::SCALAR_TO_VECTOR: return "scalar_to_vector"; case ISD::VBUILD_VECTOR: return "vbuild_vector"; case ISD::VECTOR_SHUFFLE: return "vector_shuffle"; Index: llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp diff -u llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.198 llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.199 --- llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.198 Tue Mar 21 13:20:37 2006 +++ llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp Tue Mar 21 14:44:12 2006 @@ -463,7 +463,7 @@ void visitSetLT(User &I) { visitSetCC(I, ISD::SETLT, ISD::SETULT); } void visitSetGT(User &I) { visitSetCC(I, ISD::SETGT, ISD::SETUGT); } - void visitExtractElement(ExtractElementInst &I) { assert(0 && "TODO"); } + void visitExtractElement(ExtractElementInst &I); void visitInsertElement(InsertElementInst &I); void visitGetElementPtr(User &I); @@ -853,6 +853,14 @@ InVec, InVal, InIdx, Num, Typ)); } +void SelectionDAGLowering::visitExtractElement(ExtractElementInst &I) { + SDOperand InVec = getValue(I.getOperand(0)); + SDOperand InIdx = DAG.getNode(ISD::ZERO_EXTEND, TLI.getPointerTy(), + getValue(I.getOperand(1))); + SDOperand Typ = *(InVec.Val->op_end()-1); + setValue(&I, DAG.getNode(ISD::VEXTRACT_VECTOR_ELT, + TLI.getValueType(I.getType()), InVec, InIdx)); +} void SelectionDAGLowering::visitGetElementPtr(User &I) { SDOperand N = getValue(I.getOperand(0)); From evan.cheng at apple.com Tue Mar 21 14:44:29 2006 From: evan.cheng at apple.com (Evan Cheng) Date: Tue, 21 Mar 2006 14:44:29 -0600 Subject: [llvm-commits] CVS: llvm/utils/TableGen/DAGISelEmitter.cpp Message-ID: <200603212044.OAA29463@zion.cs.uiuc.edu> Changes in directory llvm/utils/TableGen: DAGISelEmitter.cpp updated: 1.181 -> 1.182 --- Log message: Don't forget to promote xform function to an explicit node for def : Pat<> patterns. --- Diffs of the changes: (+20 -1) DAGISelEmitter.cpp | 21 ++++++++++++++++++++- 1 files changed, 20 insertions(+), 1 deletion(-) Index: llvm/utils/TableGen/DAGISelEmitter.cpp diff -u llvm/utils/TableGen/DAGISelEmitter.cpp:1.181 llvm/utils/TableGen/DAGISelEmitter.cpp:1.182 --- llvm/utils/TableGen/DAGISelEmitter.cpp:1.181 Tue Mar 21 00:42:58 2006 +++ llvm/utils/TableGen/DAGISelEmitter.cpp Tue Mar 21 14:44:17 2006 @@ -1446,6 +1446,25 @@ Result->error("Cannot handle instructions producing instructions " "with temporaries yet!"); + // Promote the xform function to be an explicit node if set. + std::vector ResultNodeOperands; + TreePatternNode *DstPattern = Result->getOnlyTree(); + for (unsigned ii = 0, ee = DstPattern->getNumChildren(); ii != ee; ++ii) { + TreePatternNode *OpNode = DstPattern->getChild(ii); + if (Record *Xform = OpNode->getTransformFn()) { + OpNode->setTransformFn(0); + std::vector Children; + Children.push_back(OpNode); + OpNode = new TreePatternNode(Xform, Children); + } + ResultNodeOperands.push_back(OpNode); + } + DstPattern = new TreePatternNode(Result->getOnlyTree()->getOperator(), + ResultNodeOperands); + DstPattern->setTypes(Result->getOnlyTree()->getExtTypes()); + TreePattern Temp(Result->getRecord(), DstPattern, false, *this); + Temp.InferAllTypes(); + std::string Reason; if (!Pattern->getOnlyTree()->canPatternMatch(Reason, *this)) Pattern->error("Pattern can never match: " + Reason); @@ -1453,7 +1472,7 @@ PatternsToMatch. push_back(PatternToMatch(Patterns[i]->getValueAsListInit("Predicates"), Pattern->getOnlyTree(), - Result->getOnlyTree())); + Temp.getOnlyTree())); } } From lattner at cs.uiuc.edu Tue Mar 21 14:51:18 2006 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Tue, 21 Mar 2006 14:51:18 -0600 Subject: [llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCISelLowering.cpp Message-ID: <200603212051.OAA29589@zion.cs.uiuc.edu> Changes in directory llvm/lib/Target/PowerPC: PPCISelLowering.cpp updated: 1.106 -> 1.107 --- Log message: These targets don't support EXTRACT_VECTOR_ELT, though, in time, X86 will. --- Diffs of the changes: (+1 -0) PPCISelLowering.cpp | 1 + 1 files changed, 1 insertion(+) Index: llvm/lib/Target/PowerPC/PPCISelLowering.cpp diff -u llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.106 llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.107 --- llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.106 Mon Mar 20 16:37:23 2006 +++ llvm/lib/Target/PowerPC/PPCISelLowering.cpp Tue Mar 21 14:51:05 2006 @@ -168,6 +168,7 @@ setOperationAction(ISD::MUL , (MVT::ValueType)VT, Expand); setOperationAction(ISD::LOAD, (MVT::ValueType)VT, Expand); setOperationAction(ISD::VECTOR_SHUFFLE, (MVT::ValueType)VT, Expand); + setOperationAction(ISD::EXTRACT_VECTOR_ELT, (MVT::ValueType)VT, Expand); // FIXME: We don't support any BUILD_VECTOR's yet. We should custom expand // the ones we do, like splat(0.0) and splat(-0.0). From lattner at cs.uiuc.edu Tue Mar 21 14:51:18 2006 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Tue, 21 Mar 2006 14:51:18 -0600 Subject: [llvm-commits] CVS: llvm/lib/Target/X86/X86ISelLowering.cpp Message-ID: <200603212051.OAA29593@zion.cs.uiuc.edu> Changes in directory llvm/lib/Target/X86: X86ISelLowering.cpp updated: 1.113 -> 1.114 --- Log message: These targets don't support EXTRACT_VECTOR_ELT, though, in time, X86 will. --- Diffs of the changes: (+1 -0) X86ISelLowering.cpp | 1 + 1 files changed, 1 insertion(+) Index: llvm/lib/Target/X86/X86ISelLowering.cpp diff -u llvm/lib/Target/X86/X86ISelLowering.cpp:1.113 llvm/lib/Target/X86/X86ISelLowering.cpp:1.114 --- llvm/lib/Target/X86/X86ISelLowering.cpp:1.113 Mon Mar 20 00:18:01 2006 +++ llvm/lib/Target/X86/X86ISelLowering.cpp Tue Mar 21 14:51:05 2006 @@ -256,6 +256,7 @@ setOperationAction(ISD::MUL , (MVT::ValueType)VT, Expand); setOperationAction(ISD::LOAD, (MVT::ValueType)VT, Expand); setOperationAction(ISD::VECTOR_SHUFFLE, (MVT::ValueType)VT, Expand); + setOperationAction(ISD::EXTRACT_VECTOR_ELT, (MVT::ValueType)VT, Expand); } if (TM.getSubtarget().hasMMX()) { From lattner at cs.uiuc.edu Tue Mar 21 15:02:15 2006 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Tue, 21 Mar 2006 15:02:15 -0600 Subject: [llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp Message-ID: <200603212102.PAA29987@zion.cs.uiuc.edu> Changes in directory llvm/lib/CodeGen/SelectionDAG: LegalizeDAG.cpp updated: 1.328 -> 1.329 --- Log message: add expand support for extractelement --- Diffs of the changes: (+31 -1) LegalizeDAG.cpp | 32 +++++++++++++++++++++++++++++++- 1 files changed, 31 insertions(+), 1 deletion(-) Index: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp diff -u llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.328 llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.329 --- llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.328 Tue Mar 21 14:44:12 2006 +++ llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp Tue Mar 21 15:02:03 2006 @@ -826,7 +826,37 @@ Tmp1 = LegalizeOp(Node->getOperand(0)); Tmp2 = LegalizeOp(Node->getOperand(1)); Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2); - // FIXME: LOWER. + + switch (TLI.getOperationAction(ISD::EXTRACT_VECTOR_ELT, + Tmp1.getValueType())) { + default: assert(0 && "This action is not supported yet!"); + case TargetLowering::Legal: + break; + case TargetLowering::Custom: + Tmp3 = TLI.LowerOperation(Result, DAG); + if (Tmp3.Val) { + Result = Tmp3; + break; + } + // FALLTHROUGH + case TargetLowering::Expand: { + // If the target doesn't support this, store the value to a temporary + // stack slot, then LOAD the scalar element back out. + SDOperand StackPtr = CreateStackTemporary(Tmp1.getValueType()); + SDOperand Ch = DAG.getNode(ISD::STORE, MVT::Other, DAG.getEntryNode(), + Tmp1, StackPtr, DAG.getSrcValue(NULL)); + + // Add the offset to the index. + unsigned EltSize = MVT::getSizeInBits(Result.getValueType())/8; + Tmp2 = DAG.getNode(ISD::MUL, Tmp2.getValueType(), Tmp2, + DAG.getConstant(EltSize, Tmp2.getValueType())); + StackPtr = DAG.getNode(ISD::ADD, Tmp2.getValueType(), Tmp2, StackPtr); + + Result = DAG.getLoad(Result.getValueType(), Ch, StackPtr, + DAG.getSrcValue(NULL)); + break; + } + } break; case ISD::VEXTRACT_VECTOR_ELT: From evan.cheng at apple.com Tue Mar 21 17:01:33 2006 From: evan.cheng at apple.com (Evan Cheng) Date: Tue, 21 Mar 2006 17:01:33 -0600 Subject: [llvm-commits] CVS: llvm/lib/Target/X86/X86ISelLowering.cpp X86ISelLowering.h X86InstrMMX.td X86InstrSSE.td Message-ID: <200603212301.RAA30861@zion.cs.uiuc.edu> Changes in directory llvm/lib/Target/X86: X86ISelLowering.cpp updated: 1.114 -> 1.115 X86ISelLowering.h updated: 1.33 -> 1.34 X86InstrMMX.td updated: 1.5 -> 1.6 X86InstrSSE.td updated: 1.11 -> 1.12 --- Log message: - Use movaps to store 128-bit vector integers. - Each scalar to vector v8i16 and v16i8 is a any_extend followed by a movd. --- Diffs of the changes: (+71 -34) X86ISelLowering.cpp | 41 ++++++++++++++++++++++---------------- X86ISelLowering.h | 4 +++ X86InstrMMX.td | 4 ++- X86InstrSSE.td | 56 +++++++++++++++++++++++++++++++++++++--------------- 4 files changed, 71 insertions(+), 34 deletions(-) Index: llvm/lib/Target/X86/X86ISelLowering.cpp diff -u llvm/lib/Target/X86/X86ISelLowering.cpp:1.114 llvm/lib/Target/X86/X86ISelLowering.cpp:1.115 --- llvm/lib/Target/X86/X86ISelLowering.cpp:1.114 Tue Mar 21 14:51:05 2006 +++ llvm/lib/Target/X86/X86ISelLowering.cpp Tue Mar 21 17:01:21 2006 @@ -265,19 +265,19 @@ addRegisterClass(MVT::v2i32, X86::VR64RegisterClass); // FIXME: add MMX packed arithmetics - setOperationAction(ISD::BUILD_VECTOR, MVT::v8i8, Expand); - setOperationAction(ISD::BUILD_VECTOR, MVT::v4i16, Expand); - setOperationAction(ISD::BUILD_VECTOR, MVT::v2i32, Expand); + setOperationAction(ISD::BUILD_VECTOR, MVT::v8i8, Expand); + setOperationAction(ISD::BUILD_VECTOR, MVT::v4i16, Expand); + setOperationAction(ISD::BUILD_VECTOR, MVT::v2i32, Expand); } if (TM.getSubtarget().hasSSE1()) { addRegisterClass(MVT::v4f32, X86::VR128RegisterClass); - setOperationAction(ISD::ADD , MVT::v4f32, Legal); - setOperationAction(ISD::SUB , MVT::v4f32, Legal); - setOperationAction(ISD::MUL , MVT::v4f32, Legal); - setOperationAction(ISD::LOAD , MVT::v4f32, Legal); - setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Expand); + setOperationAction(ISD::ADD, MVT::v4f32, Legal); + setOperationAction(ISD::SUB, MVT::v4f32, Legal); + setOperationAction(ISD::MUL, MVT::v4f32, Legal); + setOperationAction(ISD::LOAD, MVT::v4f32, Legal); + setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Expand); } if (TM.getSubtarget().hasSSE2()) { @@ -288,15 +288,17 @@ addRegisterClass(MVT::v2i64, X86::VR128RegisterClass); - setOperationAction(ISD::ADD , MVT::v2f64, Legal); - setOperationAction(ISD::SUB , MVT::v2f64, Legal); - setOperationAction(ISD::MUL , MVT::v2f64, Legal); - setOperationAction(ISD::LOAD , MVT::v2f64, Legal); - setOperationAction(ISD::BUILD_VECTOR, MVT::v2f64, Expand); - setOperationAction(ISD::BUILD_VECTOR, MVT::v16i8, Expand); - setOperationAction(ISD::BUILD_VECTOR, MVT::v8i16, Expand); - setOperationAction(ISD::BUILD_VECTOR, MVT::v4i32, Expand); - setOperationAction(ISD::BUILD_VECTOR, MVT::v2i64, Expand); + setOperationAction(ISD::ADD, MVT::v2f64, Legal); + setOperationAction(ISD::SUB, MVT::v2f64, Legal); + setOperationAction(ISD::MUL, MVT::v2f64, Legal); + setOperationAction(ISD::LOAD, MVT::v2f64, Legal); + setOperationAction(ISD::BUILD_VECTOR, MVT::v2f64, Expand); + setOperationAction(ISD::BUILD_VECTOR, MVT::v16i8, Expand); + setOperationAction(ISD::BUILD_VECTOR, MVT::v8i16, Expand); + setOperationAction(ISD::BUILD_VECTOR, MVT::v4i32, Expand); + setOperationAction(ISD::BUILD_VECTOR, MVT::v2i64, Expand); + setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v16i8, Custom); + setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i16, Custom); } computeRegisterProperties(); @@ -2135,6 +2137,10 @@ Copy, DAG.getConstant(getBytesToPopOnReturn(), MVT::i16), Copy.getValue(1)); } + case ISD::SCALAR_TO_VECTOR: { + SDOperand AnyExt = DAG.getNode(ISD::ANY_EXTEND, MVT::i32, Op.getOperand(0)); + return DAG.getNode(X86ISD::SCALAR_TO_VECTOR, Op.getValueType(), AnyExt); + } } } @@ -2168,6 +2174,7 @@ case X86ISD::LOAD_PACK: return "X86ISD::LOAD_PACK"; case X86ISD::GlobalBaseReg: return "X86ISD::GlobalBaseReg"; case X86ISD::Wrapper: return "X86ISD::Wrapper"; + case X86ISD::SCALAR_TO_VECTOR: return "X86ISD::SCALAR_TO_VECTOR"; } } Index: llvm/lib/Target/X86/X86ISelLowering.h diff -u llvm/lib/Target/X86/X86ISelLowering.h:1.33 llvm/lib/Target/X86/X86ISelLowering.h:1.34 --- llvm/lib/Target/X86/X86ISelLowering.h:1.33 Mon Mar 13 17:20:37 2006 +++ llvm/lib/Target/X86/X86ISelLowering.h Tue Mar 21 17:01:21 2006 @@ -145,6 +145,10 @@ /// TCPWrapper - A wrapper node for TargetConstantPool, /// TargetExternalSymbol, and TargetGlobalAddress. Wrapper, + + /// SCALAR_TO_VECTOR - X86 version of SCALAR_TO_VECTOR. The destination base + /// type does not have to match the operand type. + SCALAR_TO_VECTOR, }; // X86 specific condition code. These correspond to X86_*_COND in Index: llvm/lib/Target/X86/X86InstrMMX.td diff -u llvm/lib/Target/X86/X86InstrMMX.td:1.5 llvm/lib/Target/X86/X86InstrMMX.td:1.6 --- llvm/lib/Target/X86/X86InstrMMX.td:1.5 Tue Mar 21 01:09:35 2006 +++ llvm/lib/Target/X86/X86InstrMMX.td Tue Mar 21 17:01:21 2006 @@ -24,7 +24,9 @@ // Move Instructions def MOVD64rr : I<0x6E, MRMSrcReg, (ops VR64:$dst, R32:$src), - "movd {$src, $dst|$dst, $src}", []>, TB, + "movd {$src, $dst|$dst, $src}", + [(set VR64:$dst, + (v2i32 (scalar_to_vector R32:$src)))]>, TB, Requires<[HasMMX]>; def MOVD64rm : I<0x6E, MRMSrcMem, (ops VR64:$dst, i32mem:$src), "movd {$src, $dst|$dst, $src}", []>, TB, Index: llvm/lib/Target/X86/X86InstrSSE.td diff -u llvm/lib/Target/X86/X86InstrSSE.td:1.11 llvm/lib/Target/X86/X86InstrSSE.td:1.12 --- llvm/lib/Target/X86/X86InstrSSE.td:1.11 Tue Mar 21 01:09:35 2006 +++ llvm/lib/Target/X86/X86InstrSSE.td Tue Mar 21 17:01:21 2006 @@ -17,12 +17,14 @@ // SSE specific DAG Nodes. //===----------------------------------------------------------------------===// -def X86loadp : SDNode<"X86ISD::LOAD_PACK", SDTLoad, - [SDNPHasChain]>; -def X86fand : SDNode<"X86ISD::FAND", SDTFPBinOp, - [SDNPCommutative, SDNPAssociative]>; -def X86fxor : SDNode<"X86ISD::FXOR", SDTFPBinOp, - [SDNPCommutative, SDNPAssociative]>; +def X86loadp : SDNode<"X86ISD::LOAD_PACK", SDTLoad, + [SDNPHasChain]>; +def X86fand : SDNode<"X86ISD::FAND", SDTFPBinOp, + [SDNPCommutative, SDNPAssociative]>; +def X86fxor : SDNode<"X86ISD::FXOR", SDTFPBinOp, + [SDNPCommutative, SDNPAssociative]>; +def X86s2vec : SDNode<"X86ISD::SCALAR_TO_VECTOR", + SDTypeProfile<1, 1, []>, []>; //===----------------------------------------------------------------------===// // SSE pattern fragments @@ -347,12 +349,6 @@ [(set VR128:$dst, (v4f32 (undef)))]>, Requires<[HasSSE1]>; -def : Pat<(v2f64 (undef)), (IMPLICIT_DEF_VR128)>, Requires<[HasSSE2]>; -def : Pat<(v16i8 (undef)), (IMPLICIT_DEF_VR128)>, Requires<[HasSSE2]>; -def : Pat<(v8i16 (undef)), (IMPLICIT_DEF_VR128)>, Requires<[HasSSE2]>; -def : Pat<(v4i32 (undef)), (IMPLICIT_DEF_VR128)>, Requires<[HasSSE2]>; -def : Pat<(v2i64 (undef)), (IMPLICIT_DEF_VR128)>, Requires<[HasSSE2]>; - // Move Instructions def MOVAPSrr : PSI<0x28, MRMSrcReg, (ops VR128:$dst, VR128:$src), "movaps {$src, $dst|$dst, $src}", []>; @@ -700,7 +696,9 @@ // Move Instructions def MOVD128rr : PDI<0x6E, MRMSrcReg, (ops VR128:$dst, R32:$src), - "movd {$src, $dst|$dst, $src}", []>; + "movd {$src, $dst|$dst, $src}", + [(set VR128:$dst, + (v4i32 (scalar_to_vector R32:$src)))]>; def MOVD128rm : PDI<0x6E, MRMSrcMem, (ops VR128:$dst, i32mem:$src), "movd {$src, $dst|$dst, $src}", []>; def MOVD128mr : PDI<0x7E, MRMDestMem, (ops i32mem:$dst, VR128:$src), @@ -708,11 +706,12 @@ // SSE2 instructions with XS prefix def MOVQ128rr : I<0x7E, MRMSrcReg, (ops VR128:$dst, VR64:$src), - "movq {$src, $dst|$dst, $src}", []>, XS, + "movq {$src, $dst|$dst, $src}", + [(set VR128:$dst, + (v2i64 (scalar_to_vector VR64:$src)))]>, XS, Requires<[HasSSE2]>; def MOVQ128rm : I<0x7E, MRMSrcMem, (ops VR128:$dst, i64mem:$src), - "movq {$src, $dst|$dst, $src}", []>, XS, - Requires<[HasSSE2]>; + "movq {$src, $dst|$dst, $src}", []>, XS; def MOVQ128mr : PDI<0xD6, MRMSrcMem, (ops i64mem:$dst, VR128:$src), "movq {$src, $dst|$dst, $src}", []>; @@ -731,3 +730,28 @@ "movapd {$src, $dst|$dst, $src}", [(set VR128:$dst, (v2f64 (scalar_to_vector FR64:$src)))]>; + +//===----------------------------------------------------------------------===// +// Non-Instruction Patterns +//===----------------------------------------------------------------------===// + +// 128-bit vector undef's. +def : Pat<(v2f64 (undef)), (IMPLICIT_DEF_VR128)>, Requires<[HasSSE2]>; +def : Pat<(v16i8 (undef)), (IMPLICIT_DEF_VR128)>, Requires<[HasSSE2]>; +def : Pat<(v8i16 (undef)), (IMPLICIT_DEF_VR128)>, Requires<[HasSSE2]>; +def : Pat<(v4i32 (undef)), (IMPLICIT_DEF_VR128)>, Requires<[HasSSE2]>; +def : Pat<(v2i64 (undef)), (IMPLICIT_DEF_VR128)>, Requires<[HasSSE2]>; + +// Store 128-bit integer vector values. +def : Pat<(store (v16i8 VR128:$src), addr:$dst), (MOVAPSmr addr:$dst, VR128:$src)>; +def : Pat<(store (v8i16 VR128:$src), addr:$dst), (MOVAPSmr addr:$dst, VR128:$src)>; +def : Pat<(store (v4i32 VR128:$src), addr:$dst), (MOVAPSmr addr:$dst, VR128:$src)>; +def : Pat<(store (v2i64 VR128:$src), addr:$dst), (MOVAPSmr addr:$dst, VR128:$src)>; + +// Scalar to v8i16 / v16i8. The source may be a R32, but only the lower 8 or +// 16-bits matter. +def : Pat<(v8i16 (X86s2vec R32:$src)), (MOVD128rr R32:$src)>, + Requires<[HasSSE2]>; +def : Pat<(v16i8 (X86s2vec R32:$src)), (MOVD128rr R32:$src)>, + Requires<[HasSSE2]>; + From evan.cheng at apple.com Tue Mar 21 17:04:35 2006 From: evan.cheng at apple.com (Evan Cheng) Date: Tue, 21 Mar 2006 17:04:35 -0600 Subject: [llvm-commits] CVS: llvm/lib/Target/X86/X86InstrMMX.td Message-ID: <200603212304.RAA30898@zion.cs.uiuc.edu> Changes in directory llvm/lib/Target/X86: X86InstrMMX.td updated: 1.6 -> 1.7 --- Log message: Didn't mean to check this in. No MMX support yet. --- Diffs of the changes: (+1 -3) X86InstrMMX.td | 4 +--- 1 files changed, 1 insertion(+), 3 deletions(-) Index: llvm/lib/Target/X86/X86InstrMMX.td diff -u llvm/lib/Target/X86/X86InstrMMX.td:1.6 llvm/lib/Target/X86/X86InstrMMX.td:1.7 --- llvm/lib/Target/X86/X86InstrMMX.td:1.6 Tue Mar 21 17:01:21 2006 +++ llvm/lib/Target/X86/X86InstrMMX.td Tue Mar 21 17:04:23 2006 @@ -24,9 +24,7 @@ // Move Instructions def MOVD64rr : I<0x6E, MRMSrcReg, (ops VR64:$dst, R32:$src), - "movd {$src, $dst|$dst, $src}", - [(set VR64:$dst, - (v2i32 (scalar_to_vector R32:$src)))]>, TB, + "movd {$src, $dst|$dst, $src}", []>, TB, Requires<[HasMMX]>; def MOVD64rm : I<0x6E, MRMSrcMem, (ops VR64:$dst, i32mem:$src), "movd {$src, $dst|$dst, $src}", []>, TB, From lattner at cs.uiuc.edu Tue Mar 21 18:12:49 2006 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Tue, 21 Mar 2006 18:12:49 -0600 Subject: [llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp Message-ID: <200603220012.SAA31487@zion.cs.uiuc.edu> Changes in directory llvm/lib/CodeGen/SelectionDAG: LegalizeDAG.cpp updated: 1.329 -> 1.330 --- Log message: Enclose some variables in a scope to avoid error with some gcc versions --- Diffs of the changes: (+3 -2) LegalizeDAG.cpp | 5 +++-- 1 files changed, 3 insertions(+), 2 deletions(-) Index: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp diff -u llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.329 llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.330 --- llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.329 Tue Mar 21 15:02:03 2006 +++ llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp Tue Mar 21 18:12:37 2006 @@ -859,7 +859,7 @@ } break; - case ISD::VEXTRACT_VECTOR_ELT: + case ISD::VEXTRACT_VECTOR_ELT: { // We know that operand #0 is the Vec vector. If the index is a constant // or if the invec is a supported hardware type, we can use it. Otherwise, // lower to a store then an indexed load. @@ -897,10 +897,11 @@ // It's now an extract from the appropriate high or low part. Result = LegalizeOp(DAG.UpdateNodeOperands(Result, Tmp1, Tmp2)); } else { - // FIXME: IMPLEMENT STORE/LOAD lowering. + // FIXME: IMPLEMENT STORE/LOAD lowering. Need alignment of stack slot!! assert(0 && "unimp!"); } break; + } case ISD::CALLSEQ_START: { SDNode *CallEnd = FindCallEndFromCallStart(Node); From lattner at cs.uiuc.edu Tue Mar 21 19:44:48 2006 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Tue, 21 Mar 2006 19:44:48 -0600 Subject: [llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCInstrFormats.td PPCInstrInfo.td Message-ID: <200603220144.TAA32202@zion.cs.uiuc.edu> Changes in directory llvm/lib/Target/PowerPC: PPCInstrFormats.td updated: 1.66 -> 1.67 PPCInstrInfo.td updated: 1.201 -> 1.202 --- Log message: Fix the JIT encoding of the VAForm_1 instructions, including vmaddfp --- Diffs of the changes: (+8 -9) PPCInstrFormats.td | 2 +- PPCInstrInfo.td | 15 +++++++-------- 2 files changed, 8 insertions(+), 9 deletions(-) Index: llvm/lib/Target/PowerPC/PPCInstrFormats.td diff -u llvm/lib/Target/PowerPC/PPCInstrFormats.td:1.66 llvm/lib/Target/PowerPC/PPCInstrFormats.td:1.67 --- llvm/lib/Target/PowerPC/PPCInstrFormats.td:1.66 Sun Mar 12 23:15:10 2006 +++ llvm/lib/Target/PowerPC/PPCInstrFormats.td Tue Mar 21 19:44:36 2006 @@ -595,8 +595,8 @@ : I<4, OL, asmstr, itin> { bits<5> VD; bits<5> VA; - bits<5> VB; bits<5> VC; + bits<5> VB; let Pattern = pattern; Index: llvm/lib/Target/PowerPC/PPCInstrInfo.td diff -u llvm/lib/Target/PowerPC/PPCInstrInfo.td:1.201 llvm/lib/Target/PowerPC/PPCInstrInfo.td:1.202 --- llvm/lib/Target/PowerPC/PPCInstrInfo.td:1.201 Mon Mar 20 18:51:38 2006 +++ llvm/lib/Target/PowerPC/PPCInstrInfo.td Tue Mar 21 19:44:36 2006 @@ -948,22 +948,21 @@ let PPC970_Unit = 5 in { // VALU Operations. // VA-Form instructions. 3-input AltiVec ops. -def VMADDFP : VAForm_1<46, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB, VRRC:$vC), +def VMADDFP : VAForm_1<46, (ops VRRC:$vD, VRRC:$vA, VRRC:$vC, VRRC:$vB), "vmaddfp $vD, $vA, $vC, $vB", VecFP, [(set VRRC:$vD, (fadd (fmul VRRC:$vA, VRRC:$vC), VRRC:$vB))]>, Requires<[FPContractions]>; -def VNMSUBFP: VAForm_1<47, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB, VRRC:$vC), +def VNMSUBFP: VAForm_1<47, (ops VRRC:$vD, VRRC:$vA, VRRC:$vC, VRRC:$vB), "vnmsubfp $vD, $vA, $vC, $vB", VecFP, - [(set VRRC:$vD, (fneg (fsub (fmul VRRC:$vA, - VRRC:$vC), - VRRC:$vB)))]>, + [(set VRRC:$vD, (fneg (fsub (fmul VRRC:$vA, VRRC:$vC), + VRRC:$vB)))]>, Requires<[FPContractions]>; -def VPERM : VAForm_1<43, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB, VRRC:$vC), - "vperm $vD, $vA, $vB, $vC", VecPerm, +def VPERM : VAForm_1<43, (ops VRRC:$vD, VRRC:$vA, VRRC:$vC, VRRC:$vB), + "vperm $vD, $vA, $vC, $vB", VecPerm, [(set VRRC:$vD, - (PPCvperm (v4f32 VRRC:$vA), VRRC:$vB, VRRC:$vC))]>; + (PPCvperm (v4f32 VRRC:$vA), VRRC:$vC, VRRC:$vB))]>; // VX-Form instructions. AltiVec arithmetic ops. From lattner at cs.uiuc.edu Tue Mar 21 19:46:09 2006 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Tue, 21 Mar 2006 19:46:09 -0600 Subject: [llvm-commits] CVS: llvm-test/SingleSource/UnitTests/Vector/ Message-ID: <200603220146.TAA32243@zion.cs.uiuc.edu> Changes in directory llvm-test/SingleSource/UnitTests/Vector: --- Log message: Directory /var/cvs/llvm/llvm-test/SingleSource/UnitTests/Vector added to the repository --- Diffs of the changes: (+0 -0) 0 files changed From lattner at cs.uiuc.edu Tue Mar 21 19:47:06 2006 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Tue, 21 Mar 2006 19:47:06 -0600 Subject: [llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp Message-ID: <200603220147.TAA32309@zion.cs.uiuc.edu> Changes in directory llvm/lib/CodeGen/SelectionDAG: LegalizeDAG.cpp updated: 1.330 -> 1.331 --- Log message: Endianness does not affect the order of vector fields. This fixes SingleSource/UnitTests/Vector/build.c --- Diffs of the changes: (+1 -6) LegalizeDAG.cpp | 7 +------ 1 files changed, 1 insertion(+), 6 deletions(-) Index: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp diff -u llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.330 llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.331 --- llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.330 Tue Mar 21 18:12:37 2006 +++ llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp Tue Mar 21 19:46:54 2006 @@ -3155,7 +3155,6 @@ // Emit a store of each element to the stack slot. std::vector Stores; - bool isLittleEndian = TLI.isLittleEndian(); unsigned TypeByteSize = MVT::getSizeInBits(Node->getOperand(0).getValueType())/8; unsigned VectorSize = MVT::getSizeInBits(VT)/8; @@ -3164,11 +3163,7 @@ // Ignore undef elements. if (Node->getOperand(i).getOpcode() == ISD::UNDEF) continue; - unsigned Offset; - if (isLittleEndian) - Offset = TypeByteSize*i; - else - Offset = TypeByteSize*(e-i-1); + unsigned Offset = TypeByteSize*i; SDOperand Idx = DAG.getConstant(Offset, FIPtr.getValueType()); Idx = DAG.getNode(ISD::ADD, FIPtr.getValueType(), FIPtr, Idx); From lattner at cs.uiuc.edu Tue Mar 21 19:48:47 2006 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Tue, 21 Mar 2006 19:48:47 -0600 Subject: [llvm-commits] CVS: llvm-test/SingleSource/UnitTests/Vector/build.c helpers.h simple.c Message-ID: <200603220148.TAA32381@zion.cs.uiuc.edu> Changes in directory llvm-test/SingleSource/UnitTests/Vector: build.c added (r1.1) helpers.h added (r1.1) simple.c added (r1.1) --- Log message: add some trivial testcases. --- Diffs of the changes: (+39 -0) build.c | 14 ++++++++++++++ helpers.h | 10 ++++++++++ simple.c | 15 +++++++++++++++ 3 files changed, 39 insertions(+) Index: llvm-test/SingleSource/UnitTests/Vector/build.c diff -c /dev/null llvm-test/SingleSource/UnitTests/Vector/build.c:1.1 *** /dev/null Tue Mar 21 19:48:45 2006 --- llvm-test/SingleSource/UnitTests/Vector/build.c Tue Mar 21 19:48:35 2006 *************** *** 0 **** --- 1,14 ---- + #include "helpers.h" + + int main(int argc, char **Argv) { + float X = 1.234; + if (argc == 1123) X = 2.38213; + FV A; + A.V = (v4sf){ X, X, X, X }; // splat + A.V = A.V * A.V; + printFV(&A); + A.V = (v4sf){ X, X, 0, 0 }; + A.V = A.V+A.V; + printFV(&A); + } + Index: llvm-test/SingleSource/UnitTests/Vector/helpers.h diff -c /dev/null llvm-test/SingleSource/UnitTests/Vector/helpers.h:1.1 *** /dev/null Tue Mar 21 19:48:47 2006 --- llvm-test/SingleSource/UnitTests/Vector/helpers.h Tue Mar 21 19:48:35 2006 *************** *** 0 **** --- 1,10 ---- + typedef float v4sf __attribute__ ((__vector_size__ (16))); + + typedef union { + v4sf V; + float A[4]; + } FV; + + static void printFV(FV *F) { + printf("%f %f %f %f\n", F->A[0], F->A[1], F->A[2], F->A[3]); + } Index: llvm-test/SingleSource/UnitTests/Vector/simple.c diff -c /dev/null llvm-test/SingleSource/UnitTests/Vector/simple.c:1.1 *** /dev/null Tue Mar 21 19:48:47 2006 --- llvm-test/SingleSource/UnitTests/Vector/simple.c Tue Mar 21 19:48:35 2006 *************** *** 0 **** --- 1,15 ---- + + #include "helpers.h" + + int main(int argc, char **Argv) { + float X = 1.234; + if (argc == 1123) X = 2.38213; + FV A; + A.V = (v4sf){ X, X, X, X }; // splat + A.V = A.V * A.V; + printFV(&A); + A.V = (v4sf){ X, X, 0, 0 }; + A.V = A.V+A.V; + printFV(&A); + } + From lattner at cs.uiuc.edu Tue Mar 21 20:00:34 2006 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Tue, 21 Mar 2006 20:00:34 -0600 Subject: [llvm-commits] CVS: llvm-test/SingleSource/UnitTests/Vector/sumarray.c helpers.h Message-ID: <200603220200.UAA32518@zion.cs.uiuc.edu> Changes in directory llvm-test/SingleSource/UnitTests/Vector: sumarray.c added (r1.1) helpers.h updated: 1.1 -> 1.2 --- Log message: Simple vector sum example --- Diffs of the changes: (+24 -0) helpers.h | 2 ++ sumarray.c | 22 ++++++++++++++++++++++ 2 files changed, 24 insertions(+) Index: llvm-test/SingleSource/UnitTests/Vector/sumarray.c diff -c /dev/null llvm-test/SingleSource/UnitTests/Vector/sumarray.c:1.1 *** /dev/null Tue Mar 21 20:00:32 2006 --- llvm-test/SingleSource/UnitTests/Vector/sumarray.c Tue Mar 21 20:00:22 2006 *************** *** 0 **** --- 1,22 ---- + #include "helpers.h" + + union Array { + v4sf Vectors[100]; + float Floats [400]; + }; + + union Array TheArray; + + void main() { + int i; + v4sf sum = { 0, 0, 0, 0}; + FV sumFV; + for (i = 0; i < 400; ++i) + TheArray.Floats[i] = i*12.345F; + + for (i = 0; i < 100; ++i) + sum += TheArray.Vectors[i]; + + sumFV.V = sum; + printFV(&sumFV); + } Index: llvm-test/SingleSource/UnitTests/Vector/helpers.h diff -u llvm-test/SingleSource/UnitTests/Vector/helpers.h:1.1 llvm-test/SingleSource/UnitTests/Vector/helpers.h:1.2 --- llvm-test/SingleSource/UnitTests/Vector/helpers.h:1.1 Tue Mar 21 19:48:35 2006 +++ llvm-test/SingleSource/UnitTests/Vector/helpers.h Tue Mar 21 20:00:22 2006 @@ -1,3 +1,5 @@ +#include + typedef float v4sf __attribute__ ((__vector_size__ (16))); typedef union { From evan.cheng at apple.com Tue Mar 21 20:52:45 2006 From: evan.cheng at apple.com (Evan Cheng) Date: Tue, 21 Mar 2006 20:52:45 -0600 Subject: [llvm-commits] CVS: llvm/lib/Target/X86/X86CodeEmitter.cpp Message-ID: <200603220252.UAA00368@zion.cs.uiuc.edu> Changes in directory llvm/lib/Target/X86: X86CodeEmitter.cpp updated: 1.92 -> 1.93 --- Log message: Add a couple more pseudo instructions. --- Diffs of the changes: (+2 -0) X86CodeEmitter.cpp | 2 ++ 1 files changed, 2 insertions(+) Index: llvm/lib/Target/X86/X86CodeEmitter.cpp diff -u llvm/lib/Target/X86/X86CodeEmitter.cpp:1.92 llvm/lib/Target/X86/X86CodeEmitter.cpp:1.93 --- llvm/lib/Target/X86/X86CodeEmitter.cpp:1.92 Sun Feb 26 03:12:34 2006 +++ llvm/lib/Target/X86/X86CodeEmitter.cpp Tue Mar 21 20:52:03 2006 @@ -398,6 +398,8 @@ case X86::IMPLICIT_DEF_R32: case X86::IMPLICIT_DEF_FR32: case X86::IMPLICIT_DEF_FR64: + case X86::IMPLICIT_DEF_VR64: + case X86::IMPLICIT_DEF_VR128: case X86::FP_REG_KILL: break; } From evan.cheng at apple.com Tue Mar 21 20:53:12 2006 From: evan.cheng at apple.com (Evan Cheng) Date: Tue, 21 Mar 2006 20:53:12 -0600 Subject: [llvm-commits] CVS: llvm/lib/Target/X86/X86ISelLowering.cpp X86ISelLowering.h X86InstrSSE.td Message-ID: <200603220253.UAA00387@zion.cs.uiuc.edu> Changes in directory llvm/lib/Target/X86: X86ISelLowering.cpp updated: 1.115 -> 1.116 X86ISelLowering.h updated: 1.34 -> 1.35 X86InstrSSE.td updated: 1.12 -> 1.13 --- Log message: Some splat and shuffle support. --- Diffs of the changes: (+157 -8) X86ISelLowering.cpp | 85 ++++++++++++++++++++++++++++++++++++++++++++++++++++ X86ISelLowering.h | 18 +++++++++++ X86InstrSSE.td | 62 +++++++++++++++++++++++++++++++++---- 3 files changed, 157 insertions(+), 8 deletions(-) Index: llvm/lib/Target/X86/X86ISelLowering.cpp diff -u llvm/lib/Target/X86/X86ISelLowering.cpp:1.115 llvm/lib/Target/X86/X86ISelLowering.cpp:1.116 --- llvm/lib/Target/X86/X86ISelLowering.cpp:1.115 Tue Mar 21 17:01:21 2006 +++ llvm/lib/Target/X86/X86ISelLowering.cpp Tue Mar 21 20:53:00 2006 @@ -278,6 +278,7 @@ setOperationAction(ISD::MUL, MVT::v4f32, Legal); setOperationAction(ISD::LOAD, MVT::v4f32, Legal); setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Expand); + setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4f32, Custom); } if (TM.getSubtarget().hasSSE2()) { @@ -299,6 +300,7 @@ setOperationAction(ISD::BUILD_VECTOR, MVT::v2i64, Expand); setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v16i8, Custom); setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i16, Custom); + setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2f64, Custom); } computeRegisterProperties(); @@ -1366,6 +1368,66 @@ (GV->isExternal() && !GV->hasNotBeenReadFromBytecode())); } +/// isPSHUFDMask - Return true if the specified VECTOR_SHUFFLE operand +/// specifies a shuffle of elements that is suitable for input to PSHUFD. +bool X86::isPSHUFDMask(SDNode *N) { + assert(N->getOpcode() == ISD::BUILD_VECTOR); + + if (N->getNumOperands() != 4) + return false; + + // This is a splat operation if each element of the permute is the same, and + // if the value doesn't reference the second vector. + SDOperand Elt = N->getOperand(0); + assert(isa(Elt) && "Invalid VECTOR_SHUFFLE mask!"); + for (unsigned i = 1, e = N->getNumOperands(); i != e; ++i) { + assert(isa(N->getOperand(i)) && + "Invalid VECTOR_SHUFFLE mask!"); + if (cast(N->getOperand(i))->getValue() >= 4) return false; + } + + return true; +} + +/// isSplatMask - Return true if the specified VECTOR_SHUFFLE operand specifies +/// a splat of a single element. +bool X86::isSplatMask(SDNode *N) { + assert(N->getOpcode() == ISD::BUILD_VECTOR); + + // We can only splat 64-bit, and 32-bit quantities. + if (N->getNumOperands() != 4 && N->getNumOperands() != 2) + return false; + + // This is a splat operation if each element of the permute is the same, and + // if the value doesn't reference the second vector. + SDOperand Elt = N->getOperand(0); + assert(isa(Elt) && "Invalid VECTOR_SHUFFLE mask!"); + for (unsigned i = 1, e = N->getNumOperands(); i != e; ++i) { + assert(isa(N->getOperand(i)) && + "Invalid VECTOR_SHUFFLE mask!"); + if (N->getOperand(i) != Elt) return false; + } + + // Make sure it is a splat of the first vector operand. + return cast(Elt)->getValue() < N->getNumOperands(); +} + +/// getShuffleImmediate - Return the appropriate immediate to shuffle +/// the specified isShuffleMask VECTOR_SHUFFLE mask. +unsigned X86::getShuffleImmediate(SDNode *N) { + unsigned NumOperands = N->getNumOperands(); + unsigned Shift = (NumOperands == 4) ? 2 : 1; + unsigned Mask = 0; + unsigned i = NumOperands - 1; + do { + Mask |= cast(N->getOperand(i))->getValue(); + Mask <<= Shift; + --i; + } while (i != 0); + + return Mask; +} + /// LowerOperation - Provide custom lowering hooks for some operations. /// SDOperand X86TargetLowering::LowerOperation(SDOperand Op, SelectionDAG &DAG) { @@ -2141,6 +2203,28 @@ SDOperand AnyExt = DAG.getNode(ISD::ANY_EXTEND, MVT::i32, Op.getOperand(0)); return DAG.getNode(X86ISD::SCALAR_TO_VECTOR, Op.getValueType(), AnyExt); } + case ISD::VECTOR_SHUFFLE: { + SDOperand V1 = Op.getOperand(0); + SDOperand V2 = Op.getOperand(1); + SDOperand PermMask = Op.getOperand(2); + MVT::ValueType VT = Op.getValueType(); + + if (V2.getOpcode() == ISD::UNDEF) { + // Handle splat cases. + if (X86::isSplatMask(PermMask.Val)) { + if (VT == MVT::v2f64 || VT == MVT::v2i64) + // Use unpcklpd + return DAG.getNode(X86ISD::UNPCKLP, VT, V1, V1); + // Leave the VECTOR_SHUFFLE alone. It matches SHUFP*. + break; + } else if (VT == MVT::v4f32 && X86::isPSHUFDMask(PermMask.Val)) + // Leave the VECTOR_SHUFFLE alone. It matches PSHUFD. + break; + } + + // TODO. + assert(0); + } } } @@ -2175,6 +2259,7 @@ case X86ISD::GlobalBaseReg: return "X86ISD::GlobalBaseReg"; case X86ISD::Wrapper: return "X86ISD::Wrapper"; case X86ISD::SCALAR_TO_VECTOR: return "X86ISD::SCALAR_TO_VECTOR"; + case X86ISD::UNPCKLP: return "X86ISD::UNPCKLP"; } } Index: llvm/lib/Target/X86/X86ISelLowering.h diff -u llvm/lib/Target/X86/X86ISelLowering.h:1.34 llvm/lib/Target/X86/X86ISelLowering.h:1.35 --- llvm/lib/Target/X86/X86ISelLowering.h:1.34 Tue Mar 21 17:01:21 2006 +++ llvm/lib/Target/X86/X86ISelLowering.h Tue Mar 21 20:53:00 2006 @@ -149,6 +149,9 @@ /// SCALAR_TO_VECTOR - X86 version of SCALAR_TO_VECTOR. The destination base /// type does not have to match the operand type. SCALAR_TO_VECTOR, + + /// UNPCKLP - X86 unpack and interleave low instructions. + UNPCKLP, }; // X86 specific condition code. These correspond to X86_*_COND in @@ -174,6 +177,21 @@ }; } + /// Define some predicates that are used for node matching. + namespace X86 { + /// isPSHUFDMask - Return true if the specified VECTOR_SHUFFLE operand + /// specifies a shuffle of elements that is suitable for input to PSHUFD. + bool isPSHUFDMask(SDNode *N); + + /// isSplatMask - Return true if the specified VECTOR_SHUFFLE operand + /// specifies a splat of a single element. + bool isSplatMask(SDNode *N); + + /// getShuffleImmediate - Return the appropriate immediate to shuffle + /// the specified isShuffleMask VECTOR_SHUFFLE mask. + unsigned getShuffleImmediate(SDNode *N); + } + //===----------------------------------------------------------------------===// // X86TargetLowering - X86 Implementation of the TargetLowering interface class X86TargetLowering : public TargetLowering { Index: llvm/lib/Target/X86/X86InstrSSE.td diff -u llvm/lib/Target/X86/X86InstrSSE.td:1.12 llvm/lib/Target/X86/X86InstrSSE.td:1.13 --- llvm/lib/Target/X86/X86InstrSSE.td:1.12 Tue Mar 21 17:01:21 2006 +++ llvm/lib/Target/X86/X86InstrSSE.td Tue Mar 21 20:53:00 2006 @@ -17,14 +17,19 @@ // SSE specific DAG Nodes. //===----------------------------------------------------------------------===// -def X86loadp : SDNode<"X86ISD::LOAD_PACK", SDTLoad, - [SDNPHasChain]>; -def X86fand : SDNode<"X86ISD::FAND", SDTFPBinOp, - [SDNPCommutative, SDNPAssociative]>; -def X86fxor : SDNode<"X86ISD::FXOR", SDTFPBinOp, - [SDNPCommutative, SDNPAssociative]>; -def X86s2vec : SDNode<"X86ISD::SCALAR_TO_VECTOR", - SDTypeProfile<1, 1, []>, []>; +def SDTX86Unpcklp : SDTypeProfile<1, 2, + [SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>]>; + +def X86loadp : SDNode<"X86ISD::LOAD_PACK", SDTLoad, + [SDNPHasChain]>; +def X86fand : SDNode<"X86ISD::FAND", SDTFPBinOp, + [SDNPCommutative, SDNPAssociative]>; +def X86fxor : SDNode<"X86ISD::FXOR", SDTFPBinOp, + [SDNPCommutative, SDNPAssociative]>; +def X86s2vec : SDNode<"X86ISD::SCALAR_TO_VECTOR", + SDTypeProfile<1, 1, []>, []>; +def X86unpcklp : SDNode<"X86ISD::UNPCKLP", + SDTX86Unpcklp, []>; //===----------------------------------------------------------------------===// // SSE pattern fragments @@ -36,6 +41,20 @@ def loadv4f32 : PatFrag<(ops node:$ptr), (v4f32 (load node:$ptr))>; def loadv2f64 : PatFrag<(ops node:$ptr), (v2f64 (load node:$ptr))>; +// SHUFFLE_get_imm xform function: convert vector_shuffle mask to PSHUF*, +// SHUF* etc. imm. +def SHUFFLE_get_imm : SDNodeXForm; + +def SHUFFLE_splat_mask : PatLeaf<(build_vector), [{ + return X86::isSplatMask(N); +}], SHUFFLE_get_imm>; + +def PSHUFD_shuffle_mask : PatLeaf<(build_vector), [{ + return X86::isPSHUFDMask(N); +}], SHUFFLE_get_imm>; + //===----------------------------------------------------------------------===// // SSE scalar FP Instructions //===----------------------------------------------------------------------===// @@ -652,6 +671,21 @@ } // Shuffle and unpack instructions +def PSHUFWrr : PSI<0x70, AddRegFrm, + (ops VR64:$dst, VR64:$src1, i8imm:$src2), + "pshufw {$src2, $src1, $dst|$dst, $src1, $src2}", []>; +def PSHUFWrm : PSI<0x70, MRMSrcMem, + (ops VR64:$dst, i64mem:$src1, i8imm:$src2), + "pshufw {$src2, $src1, $dst|$dst, $src1, $src2}", []>; +def PSHUFDrr : PDI<0x70, AddRegFrm, + (ops VR128:$dst, VR128:$src1, i8imm:$src2), + "pshufd {$src2, $src1, $dst|$dst, $src1, $src2}", + [(set VR128:$dst, (vector_shuffle (v4f32 VR128:$src1), (undef), + PSHUFD_shuffle_mask:$src2))]>; +def PSHUFDrm : PDI<0x70, MRMSrcMem, + (ops VR128:$dst, i128mem:$src1, i8imm:$src2), + "pshufd {$src2, $src1, $dst|$dst, $src1, $src2}", []>; + def SHUFPSrr : PSI<0xC6, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2, i8imm:$src3), "shufps {$src3, $src2, $dst|$dst, $src2, $src3}", []>; @@ -755,3 +789,15 @@ def : Pat<(v16i8 (X86s2vec R32:$src)), (MOVD128rr R32:$src)>, Requires<[HasSSE2]>; + +// Splat v4f32 / v4i32 +def : Pat<(vector_shuffle (v4f32 VR128:$src), (undef), SHUFFLE_splat_mask:$sm), + (v4f32 (SHUFPSrr VR128:$src, VR128:$src, SHUFFLE_splat_mask:$sm))>; +def : Pat<(vector_shuffle (v4i32 VR128:$src), (undef), SHUFFLE_splat_mask:$sm), + (v4i32 (SHUFPSrr VR128:$src, VR128:$src, SHUFFLE_splat_mask:$sm))>; + +// Splat v2f64 / v2i64 +def : Pat<(X86unpcklp (v2f64 VR128:$src1), VR128:$src2), + (v2f64 (UNPCKLPDrr VR128:$src1, VR128:$src2))>; +def : Pat<(X86unpcklp (v2i64 VR128:$src1), VR128:$src2), + (v2i64 (UNPCKLPDrr VR128:$src1, VR128:$src2))>; From lattner at cs.uiuc.edu Tue Mar 21 22:18:46 2006 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Tue, 21 Mar 2006 22:18:46 -0600 Subject: [llvm-commits] CVS: llvm/lib/Target/X86/X86ISelLowering.cpp Message-ID: <200603220418.WAA01119@zion.cs.uiuc.edu> Changes in directory llvm/lib/Target/X86: X86ISelLowering.cpp updated: 1.116 -> 1.117 --- Log message: fix a warning --- Diffs of the changes: (+4 -3) X86ISelLowering.cpp | 7 ++++--- 1 files changed, 4 insertions(+), 3 deletions(-) Index: llvm/lib/Target/X86/X86ISelLowering.cpp diff -u llvm/lib/Target/X86/X86ISelLowering.cpp:1.116 llvm/lib/Target/X86/X86ISelLowering.cpp:1.117 --- llvm/lib/Target/X86/X86ISelLowering.cpp:1.116 Tue Mar 21 20:53:00 2006 +++ llvm/lib/Target/X86/X86ISelLowering.cpp Tue Mar 21 22:18:34 2006 @@ -2216,14 +2216,15 @@ // Use unpcklpd return DAG.getNode(X86ISD::UNPCKLP, VT, V1, V1); // Leave the VECTOR_SHUFFLE alone. It matches SHUFP*. - break; + return SDOperand(); } else if (VT == MVT::v4f32 && X86::isPSHUFDMask(PermMask.Val)) // Leave the VECTOR_SHUFFLE alone. It matches PSHUFD. - break; + return SDOperand(); } // TODO. - assert(0); + assert(0 && "TODO"); + abort(); } } } From lattner at cs.uiuc.edu Tue Mar 21 23:26:15 2006 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Tue, 21 Mar 2006 23:26:15 -0600 Subject: [llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp PPCAsmPrinter.cpp Message-ID: <200603220526.XAA01441@zion.cs.uiuc.edu> Changes in directory llvm/lib/Target/PowerPC: PPCISelDAGToDAG.cpp updated: 1.174 -> 1.175 PPCAsmPrinter.cpp updated: 1.159 -> 1.160 --- Log message: Add support for "ri" addressing modes where the immediate is a 14-bit field which is shifted left two bits before use. Instructions like STD use this addressing mode. --- Diffs of the changes: (+95 -0) PPCAsmPrinter.cpp | 14 ++++++++ PPCISelDAGToDAG.cpp | 81 ++++++++++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 95 insertions(+) Index: llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp diff -u llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp:1.174 llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp:1.175 --- llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp:1.174 Tue Mar 21 00:37:40 2006 +++ llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp Tue Mar 21 23:26:03 2006 @@ -89,6 +89,11 @@ /// represented as an indexed [r+r] operation. bool SelectAddrIdxOnly(SDOperand N, SDOperand &Base, SDOperand &Index); + /// SelectAddrImmShift - Returns true if the address N can be represented by + /// a base register plus a signed 14-bit displacement [r+imm*4]. Suitable + /// for use by STD and friends. + bool SelectAddrImmShift(SDOperand N, SDOperand &Disp, SDOperand &Base); + /// SelectInlineAsmMemoryOperand - Implement addressing mode selection for /// inline asm expressions. virtual bool SelectInlineAsmMemoryOperand(const SDOperand &Op, @@ -619,6 +624,82 @@ return true; } +/// SelectAddrImmShift - Returns true if the address N can be represented by +/// a base register plus a signed 14-bit displacement [r+imm*4]. Suitable +/// for use by STD and friends. +bool PPCDAGToDAGISel::SelectAddrImmShift(SDOperand N, SDOperand &Disp, + SDOperand &Base) { + // If this can be more profitably realized as r+r, fail. + if (SelectAddrIdx(N, Disp, Base)) + return false; + + if (N.getOpcode() == ISD::ADD) { + unsigned imm = 0; + if (isIntImmediate(N.getOperand(1), imm) && isInt16(imm) && + (imm & 3) == 0) { + Disp = getI32Imm((imm & 0xFFFF) >> 2); + if (FrameIndexSDNode *FI = dyn_cast(N.getOperand(0))) { + Base = CurDAG->getTargetFrameIndex(FI->getIndex(), MVT::i32); + } else { + Base = N.getOperand(0); + } + return true; // [r+i] + } else if (N.getOperand(1).getOpcode() == PPCISD::Lo) { + // Match LOAD (ADD (X, Lo(G))). + assert(!cast(N.getOperand(1).getOperand(1))->getValue() + && "Cannot handle constant offsets yet!"); + Disp = N.getOperand(1).getOperand(0); // The global address. + assert(Disp.getOpcode() == ISD::TargetGlobalAddress || + Disp.getOpcode() == ISD::TargetConstantPool); + Base = N.getOperand(0); + return true; // [&g+r] + } + } else if (N.getOpcode() == ISD::OR) { + unsigned imm = 0; + if (isIntImmediate(N.getOperand(1), imm) && isInt16(imm) && + (imm & 3) == 0) { + // If this is an or of disjoint bitfields, we can codegen this as an add + // (for better address arithmetic) if the LHS and RHS of the OR are + // provably disjoint. + uint64_t LHSKnownZero, LHSKnownOne; + PPCLowering.ComputeMaskedBits(N.getOperand(0), ~0U, + LHSKnownZero, LHSKnownOne); + if ((LHSKnownZero|~imm) == ~0U) { + // If all of the bits are known zero on the LHS or RHS, the add won't + // carry. + Base = N.getOperand(0); + Disp = getI32Imm((imm & 0xFFFF) >> 2); + return true; + } + } + } else if (ConstantSDNode *CN = dyn_cast(N)) { + // Loading from a constant address. + int Addr = (int)CN->getValue(); + if ((Addr & 3) == 0) { + // If this address fits entirely in a 16-bit sext immediate field, codegen + // this as "d, 0" + if (Addr == (short)Addr) { + Disp = getI32Imm(Addr >> 2); + Base = CurDAG->getRegister(PPC::R0, MVT::i32); + return true; + } + + // Otherwise, break this down into an LIS + disp. + Disp = getI32Imm((short)Addr >> 2); + Base = CurDAG->getConstant(Addr - (signed short)Addr, MVT::i32); + return true; + } + } + + Disp = getI32Imm(0); + if (FrameIndexSDNode *FI = dyn_cast(N)) + Base = CurDAG->getTargetFrameIndex(FI->getIndex(), MVT::i32); + else + Base = N; + return true; // [r+0] +} + + /// SelectCC - Select a comparison of the specified values with the specified /// condition code, returning the CR# of the expression. SDOperand PPCDAGToDAGISel::SelectCC(SDOperand LHS, SDOperand RHS, Index: llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp diff -u llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp:1.159 llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp:1.160 --- llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp:1.159 Tue Mar 21 11:21:13 2006 +++ llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp Tue Mar 21 23:26:03 2006 @@ -201,6 +201,20 @@ printOperand(MI, OpNo+1); O << ')'; } + void printMemRegImmShifted(const MachineInstr *MI, unsigned OpNo) { + if (MI->getOperand(OpNo).isImmediate()) + printS16X4ImmOperand(MI, OpNo); + else + printSymbolLo(MI, OpNo); + O << '('; + if (MI->getOperand(OpNo+1).isRegister() && + MI->getOperand(OpNo+1).getReg() == PPC::R0) + O << "0"; + else + printOperand(MI, OpNo+1); + O << ')'; + } + void printMemRegReg(const MachineInstr *MI, unsigned OpNo) { // When used as the base register, r0 reads constant zero rather than // the value contained in the register. For this reason, the darwin From lattner at cs.uiuc.edu Tue Mar 21 23:30:45 2006 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Tue, 21 Mar 2006 23:30:45 -0600 Subject: [llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCHazardRecognizers.cpp PPCISelLowering.cpp PPCISelLowering.h PPCInstrInfo.td PPCRegisterInfo.cpp Message-ID: <200603220530.XAA01545@zion.cs.uiuc.edu> Changes in directory llvm/lib/Target/PowerPC: PPCHazardRecognizers.cpp updated: 1.11 -> 1.12 PPCISelLowering.cpp updated: 1.107 -> 1.108 PPCISelLowering.h updated: 1.30 -> 1.31 PPCInstrInfo.td updated: 1.202 -> 1.203 PPCRegisterInfo.cpp updated: 1.48 -> 1.49 --- Log message: When possible, custom lower 32-bit SINT_TO_FP to this: _foo2: extsw r2, r3 std r2, -8(r1) lfd f0, -8(r1) fcfid f0, f0 frsp f1, f0 blr instead of this: _foo2: lis r2, ha16(LCPI2_0) lis r4, 17200 xoris r3, r3, 32768 stw r3, -4(r1) stw r4, -8(r1) lfs f0, lo16(LCPI2_0)(r2) lfd f1, -8(r1) fsub f0, f1, f0 frsp f1, f0 blr This speeds up Misc/pi from 2.44s->2.09s with LLC and from 3.01->2.18s with llcbeta (16.7% and 38.1% respectively). --- Diffs of the changes: (+92 -32) PPCHazardRecognizers.cpp | 3 + PPCISelLowering.cpp | 86 ++++++++++++++++++++++++++++++++--------------- PPCISelLowering.h | 7 +++ PPCInstrInfo.td | 26 ++++++++++++-- PPCRegisterInfo.cpp | 2 - 5 files changed, 92 insertions(+), 32 deletions(-) Index: llvm/lib/Target/PowerPC/PPCHazardRecognizers.cpp diff -u llvm/lib/Target/PowerPC/PPCHazardRecognizers.cpp:1.11 llvm/lib/Target/PowerPC/PPCHazardRecognizers.cpp:1.12 --- llvm/lib/Target/PowerPC/PPCHazardRecognizers.cpp:1.11 Sun Mar 12 23:23:59 2006 +++ llvm/lib/Target/PowerPC/PPCHazardRecognizers.cpp Tue Mar 21 23:30:33 2006 @@ -245,8 +245,9 @@ case PPC::STFIWX: ThisStoreSize = 4; break; + case PPC::STD_32: + case PPC::STDX_32: case PPC::STD: - case PPC::STDU: case PPC::STFD: case PPC::STFDX: case PPC::STDX: Index: llvm/lib/Target/PowerPC/PPCISelLowering.cpp diff -u llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.107 llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.108 --- llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.107 Tue Mar 21 14:51:05 2006 +++ llvm/lib/Target/PowerPC/PPCISelLowering.cpp Tue Mar 21 23:30:33 2006 @@ -140,6 +140,7 @@ // They also have instructions for converting between i64 and fp. setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom); setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom); + setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom); // To take advantage of the above i64 FP_TO_SINT, promote i32 FP_TO_UINT setOperationAction(ISD::FP_TO_UINT, MVT::i32, Promote); } else { @@ -222,6 +223,8 @@ case PPCISD::SRL: return "PPCISD::SRL"; case PPCISD::SRA: return "PPCISD::SRA"; case PPCISD::SHL: return "PPCISD::SHL"; + case PPCISD::EXTSW_32: return "PPCISD::EXTSW_32"; + case PPCISD::STD_32: return "PPCISD::STD_32"; case PPCISD::CALL: return "PPCISD::CALL"; case PPCISD::RET_FLAG: return "PPCISD::RET_FLAG"; } @@ -302,15 +305,41 @@ Bits = DAG.getNode(ISD::TRUNCATE, MVT::i32, Bits); return Bits; } - case ISD::SINT_TO_FP: { - assert(MVT::i64 == Op.getOperand(0).getValueType() && - "Unhandled SINT_TO_FP type in custom expander!"); - SDOperand Bits = DAG.getNode(ISD::BIT_CONVERT, MVT::f64, Op.getOperand(0)); - SDOperand FP = DAG.getNode(PPCISD::FCFID, MVT::f64, Bits); - if (MVT::f32 == Op.getValueType()) - FP = DAG.getNode(ISD::FP_ROUND, MVT::f32, FP); - return FP; - } + case ISD::SINT_TO_FP: + if (Op.getOperand(0).getValueType() == MVT::i64) { + SDOperand Bits = DAG.getNode(ISD::BIT_CONVERT, MVT::f64, Op.getOperand(0)); + SDOperand FP = DAG.getNode(PPCISD::FCFID, MVT::f64, Bits); + if (Op.getValueType() == MVT::f32) + FP = DAG.getNode(ISD::FP_ROUND, MVT::f32, FP); + return FP; + } else { + assert(Op.getOperand(0).getValueType() == MVT::i32 && + "Unhandled SINT_TO_FP type in custom expander!"); + // Since we only generate this in 64-bit mode, we can take advantage of + // 64-bit registers. In particular, sign extend the input value into the + // 64-bit register with extsw, store the WHOLE 64-bit value into the stack + // then lfd it and fcfid it. + MachineFrameInfo *FrameInfo = DAG.getMachineFunction().getFrameInfo(); + int FrameIdx = FrameInfo->CreateStackObject(8, 8); + SDOperand FIdx = DAG.getFrameIndex(FrameIdx, MVT::i32); + + SDOperand Ext64 = DAG.getNode(PPCISD::EXTSW_32, MVT::i32, + Op.getOperand(0)); + + // STD the extended value into the stack slot. + SDOperand Store = DAG.getNode(PPCISD::STD_32, MVT::Other, + DAG.getEntryNode(), Ext64, FIdx, + DAG.getSrcValue(NULL)); + // Load the value as a double. + SDOperand Ld = DAG.getLoad(MVT::f64, Store, FIdx, DAG.getSrcValue(NULL)); + + // FCFID it and return it. + SDOperand FP = DAG.getNode(PPCISD::FCFID, MVT::f64, Ld); + if (Op.getValueType() == MVT::f32) + FP = DAG.getNode(ISD::FP_ROUND, MVT::f32, FP); + return FP; + } + case ISD::SELECT_CC: { // Turn FP only select_cc's into fsel instructions. if (!MVT::isFloatingPoint(Op.getOperand(0).getValueType()) || @@ -1106,27 +1135,30 @@ default: break; case ISD::SINT_TO_FP: if (TM.getSubtarget().is64Bit()) { - // Turn (sint_to_fp (fp_to_sint X)) -> fctidz/fcfid without load/stores. - // We allow the src/dst to be either f32/f64, but force the intermediate - // type to be i64. - if (N->getOperand(0).getOpcode() == ISD::FP_TO_SINT && - N->getOperand(0).getValueType() == MVT::i64) { - - SDOperand Val = N->getOperand(0).getOperand(0); - if (Val.getValueType() == MVT::f32) { - Val = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Val); + if (N->getOperand(0).getOpcode() == ISD::FP_TO_SINT) { + // Turn (sint_to_fp (fp_to_sint X)) -> fctidz/fcfid without load/stores. + // We allow the src/dst to be either f32/f64, but the intermediate + // type must be i64. + if (N->getOperand(0).getValueType() == MVT::i64) { + SDOperand Val = N->getOperand(0).getOperand(0); + if (Val.getValueType() == MVT::f32) { + Val = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Val); + DCI.AddToWorklist(Val.Val); + } + + Val = DAG.getNode(PPCISD::FCTIDZ, MVT::f64, Val); DCI.AddToWorklist(Val.Val); - } - - Val = DAG.getNode(PPCISD::FCTIDZ, MVT::f64, Val); - DCI.AddToWorklist(Val.Val); - Val = DAG.getNode(PPCISD::FCFID, MVT::f64, Val); - DCI.AddToWorklist(Val.Val); - if (N->getValueType(0) == MVT::f32) { - Val = DAG.getNode(ISD::FP_ROUND, MVT::f32, Val); + Val = DAG.getNode(PPCISD::FCFID, MVT::f64, Val); DCI.AddToWorklist(Val.Val); + if (N->getValueType(0) == MVT::f32) { + Val = DAG.getNode(ISD::FP_ROUND, MVT::f32, Val); + DCI.AddToWorklist(Val.Val); + } + return Val; + } else if (N->getOperand(0).getValueType() == MVT::i32) { + // If the intermediate type is i32, we can avoid the load/store here + // too. } - return Val; } } break; Index: llvm/lib/Target/PowerPC/PPCISelLowering.h diff -u llvm/lib/Target/PowerPC/PPCISelLowering.h:1.30 llvm/lib/Target/PowerPC/PPCISelLowering.h:1.31 --- llvm/lib/Target/PowerPC/PPCISelLowering.h:1.30 Mon Mar 20 00:33:01 2006 +++ llvm/lib/Target/PowerPC/PPCISelLowering.h Tue Mar 21 23:30:33 2006 @@ -75,7 +75,14 @@ /// shift amounts. These nodes are generated by the multi-precision shift /// code. SRL, SRA, SHL, + + /// EXTSW_32 - This is the EXTSW instruction for use with "32-bit" + /// registers. + EXTSW_32, + /// STD_32 - This is the STD instruction for use with "32-bit" registers. + STD_32, + /// CALL - A function call. CALL, Index: llvm/lib/Target/PowerPC/PPCInstrInfo.td diff -u llvm/lib/Target/PowerPC/PPCInstrInfo.td:1.202 llvm/lib/Target/PowerPC/PPCInstrInfo.td:1.203 --- llvm/lib/Target/PowerPC/PPCInstrInfo.td:1.202 Tue Mar 21 19:44:36 2006 +++ llvm/lib/Target/PowerPC/PPCInstrInfo.td Tue Mar 21 23:30:33 2006 @@ -58,6 +58,9 @@ def PPCsra : SDNode<"PPCISD::SRA" , SDT_PPCShiftOp>; def PPCshl : SDNode<"PPCISD::SHL" , SDT_PPCShiftOp>; +def PPCextsw_32 : SDNode<"PPCISD::EXTSW_32" , SDTIntUnaryOp>; +def PPCstd_32 : SDNode<"PPCISD::STD_32" , SDTStore, [SDNPHasChain]>; + // These are target-independent nodes, but have target-specific formats. def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_PPCCallSeq,[SDNPHasChain]>; def callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_PPCCallSeq,[SDNPHasChain]>; @@ -194,11 +197,17 @@ let NumMIOperands = 2; let MIOperandInfo = (ops GPRC, GPRC); } +def memrix : Operand { // memri where the imm is shifted 2 bits. + let PrintMethod = "printMemRegImmShifted"; + let NumMIOperands = 2; + let MIOperandInfo = (ops i32imm, GPRC); +} // Define PowerPC specific addressing mode. def iaddr : ComplexPattern; def xaddr : ComplexPattern; def xoaddr : ComplexPattern; +def ixaddr : ComplexPattern; // "std" //===----------------------------------------------------------------------===// // PowerPC Instruction Predicate Definitions. @@ -428,9 +437,15 @@ def STD : DSForm_2<62, 0, (ops GPRC:$rT, s16immX4:$DS, GPRC:$rA), "std $rT, $DS($rA)", LdStSTD, []>, isPPC64; -def STDU : DSForm_2<62, 1, (ops GPRC:$rT, s16immX4:$DS, GPRC:$rA), - "stdu $rT, $DS($rA)", LdStSTD, - []>, isPPC64; + +// STD_32/STDX_32 - Just like STD/STDX, but uses a '32-bit' input register. +def STD_32 : DSForm_2<62, 0, (ops GPRC:$rT, memrix:$dst), + "std $rT, $dst", LdStSTD, + [(PPCstd_32 GPRC:$rT, ixaddr:$dst)]>, isPPC64; +def STDX_32 : XForm_8<31, 149, (ops GPRC:$rT, memrr:$dst), + "stdx $rT, $dst", LdStSTD, + [(PPCstd_32 GPRC:$rT, xaddr:$dst)]>, isPPC64, + PPC970_DGroup_Cracked; } // X-Form instructions. Most instructions that perform an operation on a @@ -586,6 +601,11 @@ def EXTSW : XForm_11<31, 986, (ops G8RC:$rA, G8RC:$rS), "extsw $rA, $rS", IntGeneral, [(set G8RC:$rA, (sext_inreg G8RC:$rS, i32))]>, isPPC64; +/// EXTSW_32 - Just like EXTSW, but works on '32-bit' registers. +def EXTSW_32 : XForm_11<31, 986, (ops GPRC:$rA, GPRC:$rS), + "extsw $rA, $rS", IntGeneral, + [(set GPRC:$rA, (PPCextsw_32 GPRC:$rS))]>, isPPC64; + def CMP : XForm_16<31, 0, (ops CRRC:$crD, i1imm:$long, GPRC:$rA, GPRC:$rB), "cmp $crD, $long, $rA, $rB", IntCompare>; def CMPL : XForm_16<31, 32, (ops CRRC:$crD, i1imm:$long, GPRC:$rA, GPRC:$rB), Index: llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp diff -u llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp:1.48 llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp:1.49 --- llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp:1.48 Thu Mar 16 17:52:08 2006 +++ llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp Tue Mar 21 23:30:33 2006 @@ -276,7 +276,7 @@ case PPC::LWA: case PPC::LD: case PPC::STD: - case PPC::STDU: + case PPC::STD_32: assert((Offset & 3) == 0 && "Invalid frame offset!"); Offset >>= 2; // The actual encoded value has the low two bits zero. break; From lattner at cs.uiuc.edu Tue Mar 21 23:33:35 2006 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Tue, 21 Mar 2006 23:33:35 -0600 Subject: [llvm-commits] CVS: llvm/lib/Target/PowerPC/README.txt Message-ID: <200603220533.XAA01613@zion.cs.uiuc.edu> Changes in directory llvm/lib/Target/PowerPC: README.txt updated: 1.78 -> 1.79 --- Log message: This has been implemented. Tweak it into another note --- Diffs of the changes: (+9 -23) README.txt | 32 +++++++++----------------------- 1 files changed, 9 insertions(+), 23 deletions(-) Index: llvm/lib/Target/PowerPC/README.txt diff -u llvm/lib/Target/PowerPC/README.txt:1.78 llvm/lib/Target/PowerPC/README.txt:1.79 --- llvm/lib/Target/PowerPC/README.txt:1.78 Tue Mar 21 12:58:20 2006 +++ llvm/lib/Target/PowerPC/README.txt Tue Mar 21 23:33:23 2006 @@ -552,34 +552,20 @@ float foo(float X) { return (int)(X); } -Currently produces +Currently produces: _foo: - lis r2, ha16(LCPI1_0) - lis r3, 17200 fctiwz f0, f1 stfd f0, -8(r1) - lwz r4, -4(r1) - xoris r4, r4, 32768 - stw r4, -12(r1) - stw r3, -16(r1) - lfs f0, lo16(LCPI1_0)(r2) - lfd f1, -16(r1) - fsub f0, f1, f0 + lwz r2, -4(r1) + extsw r2, r2 + std r2, -16(r1) + lfd f0, -16(r1) + fcfid f0, f0 frsp f1, f0 blr -When we have ppc64 working properly, it could produce the nicer code: - -_foo: - fctiwz f0, f1 - stfd f0, -8(r1) - lwz r4, -4(r1) - extsh r4, r4 - std r4, -16(r1) - lfd f1, -16(r1) - fcfid f0, f0 - frsp f0, f0 - blr +We could use a target dag combine to turn the lwz/extsw into an lwa when the +lwz has a single use. Since LWA is cracked anyway, this would be a codesize +win only. -Note: this would speed up SingleSource/Misc/pi by about 30% From lattner at cs.uiuc.edu Wed Mar 22 00:07:29 2006 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Wed, 22 Mar 2006 00:07:29 -0600 Subject: [llvm-commits] CVS: llvm/include/llvm/ExecutionEngine/ExecutionEngine.h Message-ID: <200603220607.AAA01829@zion.cs.uiuc.edu> Changes in directory llvm/include/llvm/ExecutionEngine: ExecutionEngine.h updated: 1.34 -> 1.35 --- Log message: wrap lines to 80 columns. Add static JITCtor/InterpCtor fields --- Diffs of the changes: (+15 -5) ExecutionEngine.h | 20 +++++++++++++++----- 1 files changed, 15 insertions(+), 5 deletions(-) Index: llvm/include/llvm/ExecutionEngine/ExecutionEngine.h diff -u llvm/include/llvm/ExecutionEngine/ExecutionEngine.h:1.34 llvm/include/llvm/ExecutionEngine/ExecutionEngine.h:1.35 --- llvm/include/llvm/ExecutionEngine/ExecutionEngine.h:1.34 Wed Mar 8 12:42:33 2006 +++ llvm/include/llvm/ExecutionEngine/ExecutionEngine.h Wed Mar 22 00:06:37 2006 @@ -48,11 +48,13 @@ std::map GlobalAddressReverseMap; public: - std::map& getGlobalAddressMap(const MutexGuard& locked) { + std::map & + getGlobalAddressMap(const MutexGuard &locked) { return GlobalAddressMap; } - std::map& getGlobalAddressReverseMap(const MutexGuard& locked) { + std::map & + getGlobalAddressReverseMap(const MutexGuard& locked) { return GlobalAddressReverseMap; } }; @@ -71,9 +73,16 @@ TD = &td; } + // To avoid having libexecutionengine depend on the JIT and interpreter + // libraries, the JIT and Interpreter set these functions to ctor pointers + // at startup time if they are linked in. + typedef ExecutionEngine *(*EECtorFn)(ModuleProvider*, IntrinsicLowering*); + static EECtorFn JITCtor, InterpCtor; + public: - /// lock - This lock is protects the ExecutionEngine, JIT, JITResolver and JITEmitter classes. - /// It must be held while changing the internal state of any of those classes. + /// lock - This lock is protects the ExecutionEngine, JIT, JITResolver and + /// JITEmitter classes. It must be held while changing the internal state of + /// any of those classes. sys::Mutex lock; // Used to make this class and subclasses thread-safe ExecutionEngine(ModuleProvider *P); @@ -156,7 +165,8 @@ void *getPointerToGlobalIfAvailable(const GlobalValue *GV) { MutexGuard locked(lock); - std::map::iterator I = state.getGlobalAddressMap(locked).find(GV); + std::map::iterator I = + state.getGlobalAddressMap(locked).find(GV); return I != state.getGlobalAddressMap(locked).end() ? I->second : 0; } From lattner at cs.uiuc.edu Wed Mar 22 00:08:03 2006 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Wed, 22 Mar 2006 00:08:03 -0600 Subject: [llvm-commits] CVS: llvm/lib/ExecutionEngine/ExecutionEngine.cpp Message-ID: <200603220608.AAA01893@zion.cs.uiuc.edu> Changes in directory llvm/lib/ExecutionEngine: ExecutionEngine.cpp updated: 1.75 -> 1.76 --- Log message: Eliminate the dependency of ExecutionEngine on the JIT/Interpreter libraries. Now you can build a tool with just the JIT or just the interpreter. --- Diffs of the changes: (+8 -18) ExecutionEngine.cpp | 26 ++++++++------------------ 1 files changed, 8 insertions(+), 18 deletions(-) Index: llvm/lib/ExecutionEngine/ExecutionEngine.cpp diff -u llvm/lib/ExecutionEngine/ExecutionEngine.cpp:1.75 llvm/lib/ExecutionEngine/ExecutionEngine.cpp:1.76 --- llvm/lib/ExecutionEngine/ExecutionEngine.cpp:1.75 Wed Mar 8 12:42:46 2006 +++ llvm/lib/ExecutionEngine/ExecutionEngine.cpp Wed Mar 22 00:07:50 2006 @@ -13,8 +13,6 @@ //===----------------------------------------------------------------------===// #define DEBUG_TYPE "jit" -#include "Interpreter/Interpreter.h" -#include "JIT/JIT.h" #include "llvm/Constants.h" #include "llvm/DerivedTypes.h" #include "llvm/Module.h" @@ -26,6 +24,7 @@ #include "llvm/Support/Debug.h" #include "llvm/System/DynamicLibrary.h" #include "llvm/Target/TargetData.h" +#include using namespace llvm; namespace { @@ -33,6 +32,9 @@ Statistic<> NumGlobals ("lli", "Number of global vars initialized"); } +ExecutionEngine::EECtorFn ExecutionEngine::JITCtor = 0; +ExecutionEngine::EECtorFn ExecutionEngine::InterpCtor = 0; + ExecutionEngine::ExecutionEngine(ModuleProvider *P) : CurMod(*P->getModule()), MP(P) { assert(P && "ModuleProvider is null?"); @@ -163,24 +165,12 @@ ExecutionEngine *EE = 0; // Unless the interpreter was explicitly selected, try making a JIT. - if (!ForceInterpreter) - EE = JIT::create(MP, IL); + if (!ForceInterpreter && JITCtor) + EE = JITCtor(MP, IL); // If we can't make a JIT, make an interpreter instead. - if (EE == 0) { - try { - Module *M = MP->materializeModule(); - try { - EE = Interpreter::create(M, IL); - } catch (...) { - std::cerr << "Error creating the interpreter!\n"; - } - } catch (std::string& errmsg) { - std::cerr << "Error reading the bytecode file: " << errmsg << "\n"; - } catch (...) { - std::cerr << "Error reading the bytecode file!\n"; - } - } + if (EE == 0 && InterpCtor) + EE = InterpCtor(MP, IL); if (EE == 0) delete IL; From lattner at cs.uiuc.edu Wed Mar 22 00:08:03 2006 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Wed, 22 Mar 2006 00:08:03 -0600 Subject: [llvm-commits] CVS: llvm/lib/ExecutionEngine/Interpreter/Interpreter.cpp Interpreter.h Message-ID: <200603220608.AAA01899@zion.cs.uiuc.edu> Changes in directory llvm/lib/ExecutionEngine/Interpreter: Interpreter.cpp updated: 1.26 -> 1.27 Interpreter.h updated: 1.72 -> 1.73 --- Log message: Eliminate the dependency of ExecutionEngine on the JIT/Interpreter libraries. Now you can build a tool with just the JIT or just the interpreter. --- Diffs of the changes: (+19 -2) Interpreter.cpp | 15 ++++++++++++++- Interpreter.h | 6 +++++- 2 files changed, 19 insertions(+), 2 deletions(-) Index: llvm/lib/ExecutionEngine/Interpreter/Interpreter.cpp diff -u llvm/lib/ExecutionEngine/Interpreter/Interpreter.cpp:1.26 llvm/lib/ExecutionEngine/Interpreter/Interpreter.cpp:1.27 --- llvm/lib/ExecutionEngine/Interpreter/Interpreter.cpp:1.26 Mon Feb 6 23:29:44 2006 +++ llvm/lib/ExecutionEngine/Interpreter/Interpreter.cpp Wed Mar 22 00:07:50 2006 @@ -17,11 +17,24 @@ #include "llvm/CodeGen/IntrinsicLowering.h" #include "llvm/DerivedTypes.h" #include "llvm/Module.h" +#include "llvm/ModuleProvider.h" using namespace llvm; +static struct RegisterInterp { + RegisterInterp() { Interpreter::Register(); } +} InterpRegistrator; + /// create - Create a new interpreter object. This can never fail. /// -ExecutionEngine *Interpreter::create(Module *M, IntrinsicLowering *IL) { +ExecutionEngine *Interpreter::create(ModuleProvider *MP, + IntrinsicLowering *IL) { + Module *M; + try { + M = MP->materializeModule(); + } catch (...) { + return 0; // error materializing the module. + } + bool isLittleEndian = false; switch (M->getEndianness()) { case Module::LittleEndian: isLittleEndian = true; break; Index: llvm/lib/ExecutionEngine/Interpreter/Interpreter.h diff -u llvm/lib/ExecutionEngine/Interpreter/Interpreter.h:1.72 llvm/lib/ExecutionEngine/Interpreter/Interpreter.h:1.73 --- llvm/lib/ExecutionEngine/Interpreter/Interpreter.h:1.72 Mon Feb 6 23:29:44 2006 +++ llvm/lib/ExecutionEngine/Interpreter/Interpreter.h Wed Mar 22 00:07:50 2006 @@ -102,11 +102,15 @@ /// void runAtExitHandlers(); + static void Register() { + InterpCtor = create; + } + /// create - Create an interpreter ExecutionEngine. This can never fail. The /// specified IntrinsicLowering implementation will be deleted when the /// Interpreter execution engine is destroyed. /// - static ExecutionEngine *create(Module *M, IntrinsicLowering *IL); + static ExecutionEngine *create(ModuleProvider *M, IntrinsicLowering *IL); /// run - Start execution with the specified function and arguments. /// From lattner at cs.uiuc.edu Wed Mar 22 00:08:04 2006 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Wed, 22 Mar 2006 00:08:04 -0600 Subject: [llvm-commits] CVS: llvm/lib/ExecutionEngine/JIT/JIT.cpp JIT.h Message-ID: <200603220608.AAA01905@zion.cs.uiuc.edu> Changes in directory llvm/lib/ExecutionEngine/JIT: JIT.cpp updated: 1.59 -> 1.60 JIT.h updated: 1.27 -> 1.28 --- Log message: Eliminate the dependency of ExecutionEngine on the JIT/Interpreter libraries. Now you can build a tool with just the JIT or just the interpreter. --- Diffs of the changes: (+8 -1) JIT.cpp | 5 ++++- JIT.h | 4 ++++ 2 files changed, 8 insertions(+), 1 deletion(-) Index: llvm/lib/ExecutionEngine/JIT/JIT.cpp diff -u llvm/lib/ExecutionEngine/JIT/JIT.cpp:1.59 llvm/lib/ExecutionEngine/JIT/JIT.cpp:1.60 --- llvm/lib/ExecutionEngine/JIT/JIT.cpp:1.59 Sat Jan 7 00:12:07 2006 +++ llvm/lib/ExecutionEngine/JIT/JIT.cpp Wed Mar 22 00:07:50 2006 @@ -26,9 +26,12 @@ #include "llvm/Target/TargetMachine.h" #include "llvm/Target/TargetJITInfo.h" #include - using namespace llvm; +static struct RegisterJIT { + RegisterJIT() { JIT::Register(); } +} JITRegistrator; + JIT::JIT(ModuleProvider *MP, TargetMachine &tm, TargetJITInfo &tji) : ExecutionEngine(MP), TM(tm), TJI(tji), state(MP) { setTargetData(TM.getTargetData()); Index: llvm/lib/ExecutionEngine/JIT/JIT.h diff -u llvm/lib/ExecutionEngine/JIT/JIT.h:1.27 llvm/lib/ExecutionEngine/JIT/JIT.h:1.28 --- llvm/lib/ExecutionEngine/JIT/JIT.h:1.27 Tue Jul 12 10:51:55 2005 +++ llvm/lib/ExecutionEngine/JIT/JIT.h Wed Mar 22 00:07:50 2006 @@ -60,6 +60,10 @@ public: ~JIT(); + static void Register() { + JITCtor = create; + } + /// getJITInfo - Return the target JIT information structure. /// TargetJITInfo &getJITInfo() const { return TJI; } From lattner at cs.uiuc.edu Wed Mar 22 00:13:33 2006 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Wed, 22 Mar 2006 00:13:33 -0600 Subject: [llvm-commits] CVS: llvm-test/SingleSource/UnitTests/Vector/Makefile Message-ID: <200603220613.AAA01975@zion.cs.uiuc.edu> Changes in directory llvm-test/SingleSource/UnitTests/Vector: Makefile added (r1.1) --- Log message: I forgot to check this in earlier --- Diffs of the changes: (+7 -0) Makefile | 7 +++++++ 1 files changed, 7 insertions(+) Index: llvm-test/SingleSource/UnitTests/Vector/Makefile diff -c /dev/null llvm-test/SingleSource/UnitTests/Vector/Makefile:1.1 *** /dev/null Wed Mar 22 00:13:31 2006 --- llvm-test/SingleSource/UnitTests/Vector/Makefile Wed Mar 22 00:13:21 2006 *************** *** 0 **** --- 1,7 ---- + # SingleSource/UnitTests/Vector/Makefile + + DIRS = + LEVEL = ../../.. + include $(LEVEL)/SingleSource/Makefile.singlesrc + + From lattner at cs.uiuc.edu Wed Mar 22 00:14:22 2006 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Wed, 22 Mar 2006 00:14:22 -0600 Subject: [llvm-commits] CVS: llvm-test/SingleSource/UnitTests/Makefile Message-ID: <200603220614.AAA02013@zion.cs.uiuc.edu> Changes in directory llvm-test/SingleSource/UnitTests: Makefile updated: 1.5 -> 1.6 --- Log message: Recurse into the Vector dir --- Diffs of the changes: (+1 -1) Makefile | 2 +- 1 files changed, 1 insertion(+), 1 deletion(-) Index: llvm-test/SingleSource/UnitTests/Makefile diff -u llvm-test/SingleSource/UnitTests/Makefile:1.5 llvm-test/SingleSource/UnitTests/Makefile:1.6 --- llvm-test/SingleSource/UnitTests/Makefile:1.5 Sun Sep 5 02:56:52 2004 +++ llvm-test/SingleSource/UnitTests/Makefile Wed Mar 22 00:14:10 2006 @@ -1,6 +1,6 @@ # SingleSource/UnitTests/Makefile -DIRS = SetjmpLongjmp +DIRS = Vector SetjmpLongjmp LEVEL = ../.. include $(LEVEL)/SingleSource/Makefile.singlesrc From evan.cheng at apple.com Wed Mar 22 01:10:40 2006 From: evan.cheng at apple.com (Evan Cheng) Date: Wed, 22 Mar 2006 01:10:40 -0600 Subject: [llvm-commits] CVS: llvm/lib/Target/X86/X86InstrSSE.td Message-ID: <200603220710.BAA02185@zion.cs.uiuc.edu> Changes in directory llvm/lib/Target/X86: X86InstrSSE.td updated: 1.13 -> 1.14 --- Log message: Fix PSHUF* and SHUF* jit code emission problems --- Diffs of the changes: (+35 -25) X86InstrSSE.td | 60 +++++++++++++++++++++++++++++++++------------------------ 1 files changed, 35 insertions(+), 25 deletions(-) Index: llvm/lib/Target/X86/X86InstrSSE.td diff -u llvm/lib/Target/X86/X86InstrSSE.td:1.13 llvm/lib/Target/X86/X86InstrSSE.td:1.14 --- llvm/lib/Target/X86/X86InstrSSE.td:1.13 Tue Mar 21 20:53:00 2006 +++ llvm/lib/Target/X86/X86InstrSSE.td Wed Mar 22 01:10:28 2006 @@ -64,6 +64,8 @@ // SDI - SSE2 instructions with XD prefix. // PSI - SSE1 instructions with TB prefix. // PDI - SSE2 instructions with TB and OpSize prefixes. +// PSIi8 - SSE1 instructions with ImmT == Imm8 and TB prefix. +// PDIi8 - SSE2 instructions with ImmT == Imm8 and TB and OpSize prefixes. class SSI o, Format F, dag ops, string asm, list pattern> : I, XS, Requires<[HasSSE1]>; class SDI o, Format F, dag ops, string asm, list pattern> @@ -72,6 +74,14 @@ : I, TB, Requires<[HasSSE1]>; class PDI o, Format F, dag ops, string asm, list pattern> : I, TB, OpSize, Requires<[HasSSE2]>; +class PSIi8 o, Format F, dag ops, string asm, list pattern> + : X86Inst, TB, Requires<[HasSSE1]> { + let Pattern = pattern; +} +class PDIi8 o, Format F, dag ops, string asm, list pattern> + : X86Inst, TB, OpSize, Requires<[HasSSE2]> { + let Pattern = pattern; +} // Some 'special' instructions def IMPLICIT_DEF_FR32 : I<0, Pseudo, (ops FR32:$dst), @@ -671,33 +681,33 @@ } // Shuffle and unpack instructions -def PSHUFWrr : PSI<0x70, AddRegFrm, - (ops VR64:$dst, VR64:$src1, i8imm:$src2), - "pshufw {$src2, $src1, $dst|$dst, $src1, $src2}", []>; -def PSHUFWrm : PSI<0x70, MRMSrcMem, - (ops VR64:$dst, i64mem:$src1, i8imm:$src2), - "pshufw {$src2, $src1, $dst|$dst, $src1, $src2}", []>; -def PSHUFDrr : PDI<0x70, AddRegFrm, - (ops VR128:$dst, VR128:$src1, i8imm:$src2), - "pshufd {$src2, $src1, $dst|$dst, $src1, $src2}", +def PSHUFWrr : PSIi8<0x70, MRMDestReg, + (ops VR64:$dst, VR64:$src1, i8imm:$src2), + "pshufw {$src2, $src1, $dst|$dst, $src1, $src2}", []>; +def PSHUFWrm : PSIi8<0x70, MRMSrcMem, + (ops VR64:$dst, i64mem:$src1, i8imm:$src2), + "pshufw {$src2, $src1, $dst|$dst, $src1, $src2}", []>; +def PSHUFDrr : PDIi8<0x70, MRMDestReg, + (ops VR128:$dst, VR128:$src1, i8imm:$src2), + "pshufd {$src2, $src1, $dst|$dst, $src1, $src2}", [(set VR128:$dst, (vector_shuffle (v4f32 VR128:$src1), (undef), PSHUFD_shuffle_mask:$src2))]>; -def PSHUFDrm : PDI<0x70, MRMSrcMem, - (ops VR128:$dst, i128mem:$src1, i8imm:$src2), - "pshufd {$src2, $src1, $dst|$dst, $src1, $src2}", []>; - -def SHUFPSrr : PSI<0xC6, MRMSrcReg, - (ops VR128:$dst, VR128:$src1, VR128:$src2, i8imm:$src3), - "shufps {$src3, $src2, $dst|$dst, $src2, $src3}", []>; -def SHUFPSrm : PSI<0xC6, MRMSrcMem, - (ops VR128:$dst, VR128:$src1, f128mem:$src2, i8imm:$src3), - "shufps {$src3, $src2, $dst|$dst, $src2, $src3}", []>; -def SHUFPDrr : PDI<0xC6, MRMSrcReg, - (ops VR128:$dst, VR128:$src1, VR128:$src2, i8imm:$src3), - "shufpd {$src3, $src2, $dst|$dst, $src2, $src3}", []>; -def SHUFPDrm : PDI<0xC6, MRMSrcMem, - (ops VR128:$dst, VR128:$src1, f128mem:$src2, i8imm:$src3), - "shufpd {$src3, $src2, $dst|$dst, $src2, $src3}", []>; +def PSHUFDrm : PDIi8<0x70, MRMSrcMem, + (ops VR128:$dst, i128mem:$src1, i8imm:$src2), + "pshufd {$src2, $src1, $dst|$dst, $src1, $src2}", []>; + +def SHUFPSrr : PSIi8<0xC6, MRMSrcReg, + (ops VR128:$dst, VR128:$src1, VR128:$src2, i8imm:$src3), + "shufps {$src3, $src2, $dst|$dst, $src2, $src3}", []>; +def SHUFPSrm : PSIi8<0xC6, MRMSrcMem, + (ops VR128:$dst, VR128:$src1, f128mem:$src2, i8imm:$src3), + "shufps {$src3, $src2, $dst|$dst, $src2, $src3}", []>; +def SHUFPDrr : PDIi8<0xC6, MRMSrcReg, + (ops VR128:$dst, VR128:$src1, VR128:$src2, i8imm:$src3), + "shufpd {$src3, $src2, $dst|$dst, $src2, $src3}", []>; +def SHUFPDrm : PDIi8<0xC6, MRMSrcMem, + (ops VR128:$dst, VR128:$src1, f128mem:$src2, i8imm:$src3), + "shufpd {$src3, $src2, $dst|$dst, $src2, $src3}", []>; def UNPCKHPSrr : PSI<0x15, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2), From lattner at cs.uiuc.edu Wed Mar 22 01:33:58 2006 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Wed, 22 Mar 2006 01:33:58 -0600 Subject: [llvm-commits] CVS: llvm/lib/Target/README.txt Message-ID: <200603220733.BAA02297@zion.cs.uiuc.edu> Changes in directory llvm/lib/Target: README.txt updated: 1.23 -> 1.24 --- Log message: add a note --- Diffs of the changes: (+10 -0) README.txt | 10 ++++++++++ 1 files changed, 10 insertions(+) Index: llvm/lib/Target/README.txt diff -u llvm/lib/Target/README.txt:1.23 llvm/lib/Target/README.txt:1.24 --- llvm/lib/Target/README.txt:1.23 Sun Mar 19 00:09:23 2006 +++ llvm/lib/Target/README.txt Wed Mar 22 01:33:46 2006 @@ -128,3 +128,13 @@ //===---------------------------------------------------------------------===// Add LSR exit value substitution. It'll probably be a win for Ackermann, etc. + +//===---------------------------------------------------------------------===// + +It would be nice to revert this patch: +http://lists.cs.uiuc.edu/pipermail/llvm-commits/Week-of-Mon-20060213/031986.html + +And teach the dag combiner enough to simplify the code expanded before +legalize. It seems plausible that this knowledge would let it simplify other +stuff too. + From evan.cheng at apple.com Wed Mar 22 02:01:33 2006 From: evan.cheng at apple.com (Evan Cheng) Date: Wed, 22 Mar 2006 02:01:33 -0600 Subject: [llvm-commits] CVS: llvm/lib/Target/X86/X86ISelLowering.cpp X86ISelLowering.h X86InstrSSE.td Message-ID: <200603220801.CAA02438@zion.cs.uiuc.edu> Changes in directory llvm/lib/Target/X86: X86ISelLowering.cpp updated: 1.117 -> 1.118 X86ISelLowering.h updated: 1.35 -> 1.36 X86InstrSSE.td updated: 1.14 -> 1.15 --- Log message: - VECTOR_SHUFFLE of v4i32 / v4f32 with undef second vector always matches PSHUFD. We can make permutes entries which point to the undef pointing anything we want. - Change some names to appease Chris. --- Diffs of the changes: (+55 -45) X86ISelLowering.cpp | 52 +++++++++++++++++++++++++++------------------------- X86ISelLowering.h | 15 ++++++++------- X86InstrSSE.td | 33 ++++++++++++++++++++------------- 3 files changed, 55 insertions(+), 45 deletions(-) Index: llvm/lib/Target/X86/X86ISelLowering.cpp diff -u llvm/lib/Target/X86/X86ISelLowering.cpp:1.117 llvm/lib/Target/X86/X86ISelLowering.cpp:1.118 --- llvm/lib/Target/X86/X86ISelLowering.cpp:1.117 Tue Mar 21 22:18:34 2006 +++ llvm/lib/Target/X86/X86ISelLowering.cpp Wed Mar 22 02:01:21 2006 @@ -1368,27 +1368,6 @@ (GV->isExternal() && !GV->hasNotBeenReadFromBytecode())); } -/// isPSHUFDMask - Return true if the specified VECTOR_SHUFFLE operand -/// specifies a shuffle of elements that is suitable for input to PSHUFD. -bool X86::isPSHUFDMask(SDNode *N) { - assert(N->getOpcode() == ISD::BUILD_VECTOR); - - if (N->getNumOperands() != 4) - return false; - - // This is a splat operation if each element of the permute is the same, and - // if the value doesn't reference the second vector. - SDOperand Elt = N->getOperand(0); - assert(isa(Elt) && "Invalid VECTOR_SHUFFLE mask!"); - for (unsigned i = 1, e = N->getNumOperands(); i != e; ++i) { - assert(isa(N->getOperand(i)) && - "Invalid VECTOR_SHUFFLE mask!"); - if (cast(N->getOperand(i))->getValue() >= 4) return false; - } - - return true; -} - /// isSplatMask - Return true if the specified VECTOR_SHUFFLE operand specifies /// a splat of a single element. bool X86::isSplatMask(SDNode *N) { @@ -1412,9 +1391,10 @@ return cast(Elt)->getValue() < N->getNumOperands(); } -/// getShuffleImmediate - Return the appropriate immediate to shuffle -/// the specified isShuffleMask VECTOR_SHUFFLE mask. -unsigned X86::getShuffleImmediate(SDNode *N) { +/// getShuffleSHUFImmediate - Return the appropriate immediate to shuffle +/// the specified isShuffleMask VECTOR_SHUFFLE mask with PSHUF* and SHUFP* +/// instructions. +unsigned X86::getShuffleSHUFImmediate(SDNode *N) { unsigned NumOperands = N->getNumOperands(); unsigned Shift = (NumOperands == 4) ? 2 : 1; unsigned Mask = 0; @@ -1428,6 +1408,28 @@ return Mask; } +/// getShufflePSHUFDImmediate - Return the appropriate immediate to shuffle +/// the specified isShuffleMask VECTOR_SHUFFLE mask with PSHUFD instruction. +unsigned X86::getShufflePSHUFDImmediate(SDNode *N) { + unsigned NumOperands = N->getNumOperands(); + unsigned Mask = 0; + + assert(NumOperands == 4 && "Expect v4f32 / v4i32 vector operand"); + + unsigned i = NumOperands - 1; + do { + uint64_t Val = cast(N->getOperand(i))->getValue(); + // Second vector operand must be undef. We can have it point to anything + // we want. + if (Val >= NumOperands) Val = 0; + Mask |= Val; + Mask <<= 2; + --i; + } while (i != 0); + + return Mask; +} + /// LowerOperation - Provide custom lowering hooks for some operations. /// SDOperand X86TargetLowering::LowerOperation(SDOperand Op, SelectionDAG &DAG) { @@ -2217,7 +2219,7 @@ return DAG.getNode(X86ISD::UNPCKLP, VT, V1, V1); // Leave the VECTOR_SHUFFLE alone. It matches SHUFP*. return SDOperand(); - } else if (VT == MVT::v4f32 && X86::isPSHUFDMask(PermMask.Val)) + } else if (VT == MVT::v4f32) // Leave the VECTOR_SHUFFLE alone. It matches PSHUFD. return SDOperand(); } Index: llvm/lib/Target/X86/X86ISelLowering.h diff -u llvm/lib/Target/X86/X86ISelLowering.h:1.35 llvm/lib/Target/X86/X86ISelLowering.h:1.36 --- llvm/lib/Target/X86/X86ISelLowering.h:1.35 Tue Mar 21 20:53:00 2006 +++ llvm/lib/Target/X86/X86ISelLowering.h Wed Mar 22 02:01:21 2006 @@ -179,17 +179,18 @@ /// Define some predicates that are used for node matching. namespace X86 { - /// isPSHUFDMask - Return true if the specified VECTOR_SHUFFLE operand - /// specifies a shuffle of elements that is suitable for input to PSHUFD. - bool isPSHUFDMask(SDNode *N); - /// isSplatMask - Return true if the specified VECTOR_SHUFFLE operand /// specifies a splat of a single element. bool isSplatMask(SDNode *N); - /// getShuffleImmediate - Return the appropriate immediate to shuffle - /// the specified isShuffleMask VECTOR_SHUFFLE mask. - unsigned getShuffleImmediate(SDNode *N); + /// getShuffleSHUFImmediate - Return the appropriate immediate to shuffle + /// the specified isShuffleMask VECTOR_SHUFFLE mask with PSHUF* and SHUFP* + /// instructions. + unsigned getShuffleSHUFImmediate(SDNode *N); + + /// getShufflePSHUFDImmediate - Return the appropriate immediate to shuffle + /// the specified isShuffleMask VECTOR_SHUFFLE mask with PSHUFD instruction. + unsigned getShufflePSHUFDImmediate(SDNode *N); } //===----------------------------------------------------------------------===// Index: llvm/lib/Target/X86/X86InstrSSE.td diff -u llvm/lib/Target/X86/X86InstrSSE.td:1.14 llvm/lib/Target/X86/X86InstrSSE.td:1.15 --- llvm/lib/Target/X86/X86InstrSSE.td:1.14 Wed Mar 22 01:10:28 2006 +++ llvm/lib/Target/X86/X86InstrSSE.td Wed Mar 22 02:01:21 2006 @@ -41,19 +41,21 @@ def loadv4f32 : PatFrag<(ops node:$ptr), (v4f32 (load node:$ptr))>; def loadv2f64 : PatFrag<(ops node:$ptr), (v2f64 (load node:$ptr))>; -// SHUFFLE_get_imm xform function: convert vector_shuffle mask to PSHUF*, -// SHUF* etc. imm. -def SHUFFLE_get_imm : SDNodeXForm; -def SHUFFLE_splat_mask : PatLeaf<(build_vector), [{ +def SHUFFLE_get_pshufd_imm : SDNodeXForm; + +def SHUFP_splat_mask : PatLeaf<(build_vector), [{ return X86::isSplatMask(N); -}], SHUFFLE_get_imm>; +}], SHUFFLE_get_shuf_imm>; -def PSHUFD_shuffle_mask : PatLeaf<(build_vector), [{ - return X86::isPSHUFDMask(N); -}], SHUFFLE_get_imm>; +def PSHUFD_shuffle_mask : PatLeaf<(build_vector), [{}], SHUFFLE_get_pshufd_imm>; //===----------------------------------------------------------------------===// // SSE scalar FP Instructions @@ -801,13 +803,18 @@ // Splat v4f32 / v4i32 -def : Pat<(vector_shuffle (v4f32 VR128:$src), (undef), SHUFFLE_splat_mask:$sm), - (v4f32 (SHUFPSrr VR128:$src, VR128:$src, SHUFFLE_splat_mask:$sm))>; -def : Pat<(vector_shuffle (v4i32 VR128:$src), (undef), SHUFFLE_splat_mask:$sm), - (v4i32 (SHUFPSrr VR128:$src, VR128:$src, SHUFFLE_splat_mask:$sm))>; +def : Pat<(vector_shuffle (v4f32 VR128:$src), (undef), SHUFP_splat_mask:$sm), + (v4f32 (SHUFPSrr VR128:$src, VR128:$src, SHUFP_splat_mask:$sm))>; +def : Pat<(vector_shuffle (v4i32 VR128:$src), (undef), SHUFP_splat_mask:$sm), + (v4i32 (SHUFPSrr VR128:$src, VR128:$src, SHUFP_splat_mask:$sm))>; // Splat v2f64 / v2i64 def : Pat<(X86unpcklp (v2f64 VR128:$src1), VR128:$src2), (v2f64 (UNPCKLPDrr VR128:$src1, VR128:$src2))>; def : Pat<(X86unpcklp (v2i64 VR128:$src1), VR128:$src2), (v2i64 (UNPCKLPDrr VR128:$src1, VR128:$src2))>; + +// Shuffle v4i32, undef +def : Pat<(vector_shuffle (v4i32 VR128:$src1), (undef), + PSHUFD_shuffle_mask:$src2), + (v4i32 (PSHUFDrr VR128:$src1, PSHUFD_shuffle_mask:$src2))>; From reid at x10sys.com Wed Mar 22 10:00:19 2006 From: reid at x10sys.com (Reid Spencer) Date: Wed, 22 Mar 2006 10:00:19 -0600 Subject: [llvm-commits] CVS: llvm/Makefile.rules configure Message-ID: <200603221600.KAA16619@zion.cs.uiuc.edu> Changes in directory llvm: Makefile.rules updated: 1.352 -> 1.353 configure updated: 1.213 -> 1.214 --- Log message: These changes are necessary to support the new llvm-config tool. llvm-config is a handy tool for users of LLVM who want to be able to quickly get information about LLVM's configuration. It is intended to be used in the command line of other tools. Documentation will be forthcoming in a subsequent patch. --- Diffs of the changes: (+53 -43) Makefile.rules | 34 ++++++++++++++++++------------- configure | 62 ++++++++++++++++++++++++++++++--------------------------- 2 files changed, 53 insertions(+), 43 deletions(-) Index: llvm/Makefile.rules diff -u llvm/Makefile.rules:1.352 llvm/Makefile.rules:1.353 --- llvm/Makefile.rules:1.352 Mon Mar 20 19:06:41 2006 +++ llvm/Makefile.rules Wed Mar 22 09:59:55 2006 @@ -234,17 +234,17 @@ C.Flags += -DNDEBUG endif -CXX.Flags += $(CXXFLAGS) -C.Flags += $(CFLAGS) -CPP.Flags += $(CPPFLAGS) -LD.Flags += $(LDFLAGS) -AR.Flags := cru +CXX.Flags += $(CXXFLAGS) +C.Flags += $(CFLAGS) +CPP.BaseFlags += $(CPPFLAGS) +LD.Flags += $(LDFLAGS) +AR.Flags := cru LibTool.Flags := --tag=CXX #Make Floating point ieee complient on alpha ifeq ($(ARCH),Alpha) - CXX.Flags += -mieee - CPP.Flags += -mieee + CXX.Flags += -mieee + CPP.BaseFlags += -mieee endif #-------------------------------------------------------------------- @@ -360,13 +360,15 @@ CompileCommonOpts := -D_REENTRANT -D_HPUX_SOURCE endif -LD.Flags += -L$(LibDir) -L$(LLVMLibDir) -CPP.Flags += -I$(PROJ_OBJ_DIR) -I$(PROJ_SRC_DIR) \ - -I$(PROJ_OBJ_ROOT)/include \ - -I$(PROJ_SRC_ROOT)/include \ - -I$(LLVM_OBJ_ROOT)/include \ - -I$(LLVM_SRC_ROOT)/include \ - -D_GNU_SOURCE -D__STDC_LIMIT_MACROS +LD.Flags += -L$(LibDir) -L$(LLVMLibDir) +CPP.BaseFlags += -D_GNU_SOURCE -D__STDC_LIMIT_MACROS +# All -I flags should go here, so that they don't confuse llvm-config. +CPP.Flags += -I$(PROJ_OBJ_DIR) -I$(PROJ_SRC_DIR) \ + -I$(PROJ_OBJ_ROOT)/include \ + -I$(PROJ_SRC_ROOT)/include \ + -I$(LLVM_OBJ_ROOT)/include \ + -I$(LLVM_SRC_ROOT)/include \ + $(CPP.BaseFlags) Compile.C = $(CC) $(CPP.Flags) $(CompileCommonOpts) -c $(C.Flags) LTCompile.C = $(LIBTOOL) $(LibTool.Flags) --mode=compile $(Compile.C) @@ -386,6 +388,7 @@ LTInstall = $(LIBTOOL) $(LibTool.Flags) --mode=install $(INSTALL) \ $(Install.Flags) ProgInstall = $(INSTALL) $(Install.StripFlag) -m 0755 +ScriptInstall = $(INSTALL) -m 0755 DataInstall = $(INSTALL) -m 0644 Burg = $(BURG) -I $(PROJ_SRC_DIR) TableGen = $(TBLGEN) -I $(PROJ_SRC_DIR) -I$(PROJ_SRC_ROOT)/include @@ -635,6 +638,9 @@ ifeq ($(ARCH),Alpha) USEDLIBS := $(subst LLVMCore, LLVMCore.a, $(USEDLIBS)) LLVMLIBS := $(subst LLVMCore, LLVMCore.a, $(LLVMLIBS)) +CORE_IS_ARCHIVE := 1 +else +CORE_IS_ARCHIVE := 0 endif ProjLibsOptions := $(patsubst %.a.o, -l%, $(addsuffix .o, $(USEDLIBS))) Index: llvm/configure diff -u llvm/configure:1.213 llvm/configure:1.214 --- llvm/configure:1.213 Sun Feb 26 23:39:00 2006 +++ llvm/configure Wed Mar 22 09:59:55 2006 @@ -8376,7 +8376,7 @@ lt_dlunknown=0; lt_dlno_uscore=1; lt_dlneed_uscore=2 lt_status=$lt_dlunknown cat > conftest.$ac_ext < conftest.$ac_ext + echo '#line 10370 "configure"' > conftest.$ac_ext if { (eval echo "$as_me:$LINENO: \"$ac_compile\"") >&5 (eval $ac_compile) 2>&5 ac_status=$? @@ -10852,7 +10852,7 @@ # Provide some information about the compiler. -echo "$as_me:10856:" \ +echo "$as_me:10855:" \ "checking for Fortran 77 compiler version" >&5 ac_compiler=`set X $ac_compile; echo $2` { (eval echo "$as_me:$LINENO: \"$ac_compiler --version &5\"") >&5 @@ -11909,11 +11909,11 @@ -e 's:.*FLAGS}? :&$lt_compiler_flag :; t' \ -e 's: [^ ]*conftest\.: $lt_compiler_flag&:; t' \ -e 's:$: $lt_compiler_flag:'` - (eval echo "\"\$as_me:11913: $lt_compile\"" >&5) + (eval echo "\"\$as_me:11912: $lt_compile\"" >&5) (eval "$lt_compile" 2>conftest.err) ac_status=$? cat conftest.err >&5 - echo "$as_me:11917: \$? = $ac_status" >&5 + echo "$as_me:11916: \$? = $ac_status" >&5 if (exit $ac_status) && test -s "$ac_outfile"; then # The compiler can only warn and ignore the option if not recognized # So say no if there are warnings @@ -12152,11 +12152,11 @@ -e 's:.*FLAGS}? :&$lt_compiler_flag :; t' \ -e 's: [^ ]*conftest\.: $lt_compiler_flag&:; t' \ -e 's:$: $lt_compiler_flag:'` - (eval echo "\"\$as_me:12156: $lt_compile\"" >&5) + (eval echo "\"\$as_me:12155: $lt_compile\"" >&5) (eval "$lt_compile" 2>conftest.err) ac_status=$? cat conftest.err >&5 - echo "$as_me:12160: \$? = $ac_status" >&5 + echo "$as_me:12159: \$? = $ac_status" >&5 if (exit $ac_status) && test -s "$ac_outfile"; then # The compiler can only warn and ignore the option if not recognized # So say no if there are warnings @@ -12212,11 +12212,11 @@ -e 's:.*FLAGS}? :&$lt_compiler_flag :; t' \ -e 's: [^ ]*conftest\.: $lt_compiler_flag&:; t' \ -e 's:$: $lt_compiler_flag:'` - (eval echo "\"\$as_me:12216: $lt_compile\"" >&5) + (eval echo "\"\$as_me:12215: $lt_compile\"" >&5) (eval "$lt_compile" 2>out/conftest.err) ac_status=$? cat out/conftest.err >&5 - echo "$as_me:12220: \$? = $ac_status" >&5 + echo "$as_me:12219: \$? = $ac_status" >&5 if (exit $ac_status) && test -s out/conftest2.$ac_objext then # The compiler can only warn and ignore the option if not recognized @@ -14397,7 +14397,7 @@ lt_dlunknown=0; lt_dlno_uscore=1; lt_dlneed_uscore=2 lt_status=$lt_dlunknown cat > conftest.$ac_ext < conftest.$ac_ext <&5) + (eval echo "\"\$as_me:16691: $lt_compile\"" >&5) (eval "$lt_compile" 2>conftest.err) ac_status=$? cat conftest.err >&5 - echo "$as_me:16696: \$? = $ac_status" >&5 + echo "$as_me:16695: \$? = $ac_status" >&5 if (exit $ac_status) && test -s "$ac_outfile"; then # The compiler can only warn and ignore the option if not recognized # So say no if there are warnings @@ -16748,11 +16748,11 @@ -e 's:.*FLAGS}? :&$lt_compiler_flag :; t' \ -e 's: [^ ]*conftest\.: $lt_compiler_flag&:; t' \ -e 's:$: $lt_compiler_flag:'` - (eval echo "\"\$as_me:16752: $lt_compile\"" >&5) + (eval echo "\"\$as_me:16751: $lt_compile\"" >&5) (eval "$lt_compile" 2>out/conftest.err) ac_status=$? cat out/conftest.err >&5 - echo "$as_me:16756: \$? = $ac_status" >&5 + echo "$as_me:16755: \$? = $ac_status" >&5 if (exit $ac_status) && test -s out/conftest2.$ac_objext then # The compiler can only warn and ignore the option if not recognized @@ -18109,7 +18109,7 @@ lt_dlunknown=0; lt_dlno_uscore=1; lt_dlneed_uscore=2 lt_status=$lt_dlunknown cat > conftest.$ac_ext < conftest.$ac_ext <&5) + (eval echo "\"\$as_me:19047: $lt_compile\"" >&5) (eval "$lt_compile" 2>conftest.err) ac_status=$? cat conftest.err >&5 - echo "$as_me:19052: \$? = $ac_status" >&5 + echo "$as_me:19051: \$? = $ac_status" >&5 if (exit $ac_status) && test -s "$ac_outfile"; then # The compiler can only warn and ignore the option if not recognized # So say no if there are warnings @@ -19104,11 +19104,11 @@ -e 's:.*FLAGS}? :&$lt_compiler_flag :; t' \ -e 's: [^ ]*conftest\.: $lt_compiler_flag&:; t' \ -e 's:$: $lt_compiler_flag:'` - (eval echo "\"\$as_me:19108: $lt_compile\"" >&5) + (eval echo "\"\$as_me:19107: $lt_compile\"" >&5) (eval "$lt_compile" 2>out/conftest.err) ac_status=$? cat out/conftest.err >&5 - echo "$as_me:19112: \$? = $ac_status" >&5 + echo "$as_me:19111: \$? = $ac_status" >&5 if (exit $ac_status) && test -s out/conftest2.$ac_objext then # The compiler can only warn and ignore the option if not recognized @@ -21143,11 +21143,11 @@ -e 's:.*FLAGS}? :&$lt_compiler_flag :; t' \ -e 's: [^ ]*conftest\.: $lt_compiler_flag&:; t' \ -e 's:$: $lt_compiler_flag:'` - (eval echo "\"\$as_me:21147: $lt_compile\"" >&5) + (eval echo "\"\$as_me:21146: $lt_compile\"" >&5) (eval "$lt_compile" 2>conftest.err) ac_status=$? cat conftest.err >&5 - echo "$as_me:21151: \$? = $ac_status" >&5 + echo "$as_me:21150: \$? = $ac_status" >&5 if (exit $ac_status) && test -s "$ac_outfile"; then # The compiler can only warn and ignore the option if not recognized # So say no if there are warnings @@ -21386,11 +21386,11 @@ -e 's:.*FLAGS}? :&$lt_compiler_flag :; t' \ -e 's: [^ ]*conftest\.: $lt_compiler_flag&:; t' \ -e 's:$: $lt_compiler_flag:'` - (eval echo "\"\$as_me:21390: $lt_compile\"" >&5) + (eval echo "\"\$as_me:21389: $lt_compile\"" >&5) (eval "$lt_compile" 2>conftest.err) ac_status=$? cat conftest.err >&5 - echo "$as_me:21394: \$? = $ac_status" >&5 + echo "$as_me:21393: \$? = $ac_status" >&5 if (exit $ac_status) && test -s "$ac_outfile"; then # The compiler can only warn and ignore the option if not recognized # So say no if there are warnings @@ -21446,11 +21446,11 @@ -e 's:.*FLAGS}? :&$lt_compiler_flag :; t' \ -e 's: [^ ]*conftest\.: $lt_compiler_flag&:; t' \ -e 's:$: $lt_compiler_flag:'` - (eval echo "\"\$as_me:21450: $lt_compile\"" >&5) + (eval echo "\"\$as_me:21449: $lt_compile\"" >&5) (eval "$lt_compile" 2>out/conftest.err) ac_status=$? cat out/conftest.err >&5 - echo "$as_me:21454: \$? = $ac_status" >&5 + echo "$as_me:21453: \$? = $ac_status" >&5 if (exit $ac_status) && test -s out/conftest2.$ac_objext then # The compiler can only warn and ignore the option if not recognized @@ -23631,7 +23631,7 @@ lt_dlunknown=0; lt_dlno_uscore=1; lt_dlneed_uscore=2 lt_status=$lt_dlunknown cat > conftest.$ac_ext < conftest.$ac_ext < Changes in directory llvm/utils/llvm-config: find-cycles.pl added (r1.1) llvm-config.in.in added (r1.1) Makefile updated: 1.1 -> 1.2 --- Log message: These changes are necessary to support the new llvm-config tool. llvm-config is a handy tool for users of LLVM who want to be able to quickly get information about LLVM's configuration. It is intended to be used in the command line of other tools. Documentation will be forthcoming in a subsequent patch. --- Diffs of the changes: (+569 -1) Makefile | 44 ++++++ find-cycles.pl | 162 ++++++++++++++++++++++++ llvm-config.in.in | 364 ++++++++++++++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 569 insertions(+), 1 deletion(-) Index: llvm/utils/llvm-config/find-cycles.pl diff -c /dev/null llvm/utils/llvm-config/find-cycles.pl:1.1 *** /dev/null Wed Mar 22 10:00:06 2006 --- llvm/utils/llvm-config/find-cycles.pl Wed Mar 22 09:59:55 2006 *************** *** 0 **** --- 1,162 ---- + #!/usr/bin/perl + # + # Program: find-cycles.pl + # + # Synopsis: Given a list of possibly cyclic dependencies, merge all the + # cycles. This makes it possible to topologically sort the + # dependencies between different parts of LLVM. + # + # Syntax: find-cycles.pl < LibDeps.txt > FinalLibDeps.txt + # + # Input: cycmem1: cycmem2 dep1 dep2 + # cycmem2: cycmem1 dep3 dep4 + # boring: dep4 + # + # Output: cycmem1 cycmem2: dep1 dep2 dep3 dep4 + # boring: dep4 + # + # This file was written by Eric Kidd, and is placed into the public domain. + # + + use strict; + use warnings; + + my %DEPS; + my @CYCLES; + sub find_all_cycles; + + # Read our dependency information. + while (<>) { + chomp; + my ($module, $dependency_str) = /^([^:]*): ?(.*)$/; + die "Malformed data: $_" unless defined $dependency_str; + my @dependencies = split(/ /, $dependency_str); + $DEPS{$module} = \@dependencies; + } + + # Partition our raw dependencies into sets of cyclically-connected nodes. + find_all_cycles(); + + # Print out the finished cycles, with their dependencies. + my @output; + foreach my $cycle (@CYCLES) { + my @modules = sort keys %{$cycle}; + + # Merge the dependencies of all modules in this cycle. + my %dependencies; + foreach my $module (@modules) { + @dependencies{@{$DEPS{$module}}} = 1; + } + + # Prune the known cyclic dependencies. + foreach my $module (@modules) { + delete $dependencies{$module}; + } + + # Warn about possible linker problems. + my @archives = grep(/\.a$/, @modules); + if (@archives > 1) { + print STDERR "find-cycles.pl: Circular dependency between *.a files:\n"; + print STDERR "find-cycles.pl: ", join(' ', @archives), "\n"; + print STDERR "find-cycles.pl: Some linkers may have problems.\n"; + push @modules, @archives; # WORKAROUND: Duplicate *.a files. Ick. + } + + # Add to our output. (@modules is already as sorted as we need it to be.) + push @output, (join(' ', @modules) . ': ' . + join(' ', sort keys %dependencies) . "\n"); + } + print sort @output; + + + #========================================================================== + # Depedency Cycle Support + #========================================================================== + # For now, we have cycles in our dependency graph. Ideally, each cycle + # would be collapsed down to a single *.a file, saving us all this work. + # + # To understand this code, you'll need a working knowledge of Perl 5, + # and possibly some quality time with 'man perlref'. + + my %SEEN; + my %CYCLES; + sub find_cycles ($@); + sub found_cycles ($@); + + sub find_all_cycles { + # Find all multi-item cycles. + my @modules = sort keys %DEPS; + foreach my $module (@modules) { find_cycles($module); } + + # Build fake one-item "cycles" for the remaining modules, so we can + # treat them uniformly. + foreach my $module (@modules) { + unless (defined $CYCLES{$module}) { + my %cycle = ($module, 1); + $CYCLES{$module} = \%cycle; + } + } + + # Find all our unique cycles. We have to do this the hard way because + # we apparently can't store hash references as hash keys without making + # 'strict refs' sad. + my %seen; + foreach my $cycle (values %CYCLES) { + unless ($seen{$cycle}) { + $seen{$cycle} = 1; + push @CYCLES, $cycle; + } + } + } + + # Walk through our graph depth-first (keeping a trail in @path), and report + # any cycles we find. + sub find_cycles ($@) { + my ($module, @path) = @_; + if (str_in_list($module, @path)) { + found_cycle($module, @path); + } else { + return if defined $SEEN{$module}; + $SEEN{$module} = 1; + foreach my $dep (@{$DEPS{$module}}) { + find_cycles($dep, @path, $module); + } + } + } + + # Give a cycle, attempt to merge it with pre-existing cycle data. + sub found_cycle ($@) { + my ($module, @path) = @_; + + # Pop any modules which aren't part of our cycle. + while ($path[0] ne $module) { shift @path; } + #print join("->", @path, $module) . "\n"; + + # Collect the modules in our cycle into a hash. + my %cycle; + foreach my $item (@path) { + $cycle{$item} = 1; + if (defined $CYCLES{$item}) { + # Looks like we intersect with an existing cycle, so merge + # all those in, too. + foreach my $old_item (keys %{$CYCLES{$item}}) { + $cycle{$old_item} = 1; + } + } + } + + # Update our global cycle table. + my $cycle_ref = \%cycle; + foreach my $item (keys %cycle) { + $CYCLES{$item} = $cycle_ref; + } + #print join(":", sort keys %cycle) . "\n"; + } + + sub str_in_list ($@) { + my ($str, @list) = @_; + foreach my $item (@list) { + return 1 if ($item eq $str); + } + return 0; + } Index: llvm/utils/llvm-config/llvm-config.in.in diff -c /dev/null llvm/utils/llvm-config/llvm-config.in.in:1.1 *** /dev/null Wed Mar 22 10:00:19 2006 --- llvm/utils/llvm-config/llvm-config.in.in Wed Mar 22 09:59:55 2006 *************** *** 0 **** --- 1,364 ---- + #!/usr/bin/perl + # + # Program: llvm-config + # + # Synopsis: Prints out compiler options needed to build against an installed + # copy of LLVM. + # + # Syntax: lllvm-config OPTIONS... [COMPONENTS...] + # + # This file was written by Eric Kidd, and is placed into the public domain. + # + + use strict; + use warnings; + + #---- begin autoconf values ---- + my $VERSION = q{@PACKAGE_VERSION@}; + my $PREFIX = q{@LLVM_PREFIX@}; + my $BINDIR = q{@LLVM_BINDIR@}; + my $INCLUDEDIR = q{@LLVM_INCLUDEDIR@}; + my $LIBDIR = q{@LLVM_LIBDIR@}; + my $ARCH = lc(q{@ARCH@}); + my @TARGETS_BUILT = map { lc($_) } qw{@TARGETS_TO_BUILD@}; + #---- end autoconf values ---- + + #---- begin Makefile values ---- + my $CXXFLAGS = q{@LLVM_CXXFLAGS@}; + my $LDFLAGS = q{@LLVM_LDFLAGS@}; + my $CORE_IS_ARCHIVE = q{@CORE_IS_ARCHIVE@}; + #---- end Makefile values ---- + + sub usage; + sub fix_library_names (@); + sub expand_dependecies (@); + sub name_map_entries; + + # Parse our command-line arguments. + usage if @ARGV == 0; + my @components; + my $has_opt = 0; + my $want_libs = 0; + my $want_libnames = 0; + my $want_components = 0; + foreach my $arg (@ARGV) { + if ($arg =~ /^-/) { + if ($arg eq "--version") { + $has_opt = 1; print "$VERSION\n"; + } elsif ($arg eq "--prefix") { + $has_opt = 1; print "$PREFIX\n"; + } elsif ($arg eq "--bindir") { + $has_opt = 1; print "$BINDIR\n"; + } elsif ($arg eq "--includedir") { + $has_opt = 1; print "$INCLUDEDIR\n"; + } elsif ($arg eq "--libdir") { + $has_opt = 1; print "$LIBDIR\n"; + } elsif ($arg eq "--cxxflags") { + $has_opt = 1; print "-I$INCLUDEDIR $CXXFLAGS\n"; + } elsif ($arg eq "--ldflags") { + $has_opt = 1; print "-L$LIBDIR $LDFLAGS\n"; + } elsif ($arg eq "--libs") { + $has_opt = 1; $want_libs = 1; + } elsif ($arg eq "--libnames") { + $has_opt = 1; $want_libnames = 1; + } elsif ($arg eq "--components") { + $has_opt = 1; print join(' ', name_map_entries), "\n"; + } elsif ($arg eq "--targets-built") { + $has_opt = 1; print join(' ', @TARGETS_BUILT), "\n"; + } else { + usage(); + } + } else { + push @components, $arg; + } + } + + # If no options were specified, fail. + usage unless $has_opt; + + # If no components were specified, default to 'all'. + if (@components == 0) { + push @components, 'all'; + } + + # Handle any arguments which require building our dependency graph. + if ($want_libs || $want_libnames) { + my @libs = expand_dependecies(@components); + if ($want_libs) { + print join(' ', fix_library_names(@libs)), "\n"; + } + if ($want_libnames) { + print join(' ', @libs), "\n"; + } + } + + exit 0; + + #========================================================================== + # Support Routines + #========================================================================== + + sub usage { + print STDERR <<__EOD__; + Usage: llvm-config