From lattner at cs.uiuc.edu  Mon Mar 27 00:45:38 2006
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Mon, 27 Mar 2006 00:45:38 -0600
Subject: [llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp 
Message-ID: <200603270645.AAA11392@zion.cs.uiuc.edu>



Changes in directory llvm/lib/CodeGen/SelectionDAG:

SelectionDAG.cpp updated: 1.284 -> 1.285
---
Log message:

Instead of printing "INTRINSIC" on intrinsic node, print the intrinsic name.


---
Diffs of the changes:  (+5 -1)

 SelectionDAG.cpp |    6 +++++-
 1 files changed, 5 insertions(+), 1 deletion(-)


Index: llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp:1.284 llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp:1.285
--- llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp:1.284	Sun Mar 26 03:50:58 2006
+++ llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp	Mon Mar 27 00:45:25 2006
@@ -14,6 +14,7 @@
 #include "llvm/CodeGen/SelectionDAG.h"
 #include "llvm/Constants.h"
 #include "llvm/GlobalValue.h"
+#include "llvm/Intrinsics.h"
 #include "llvm/Assembly/Writer.h"
 #include "llvm/CodeGen/MachineBasicBlock.h"
 #include "llvm/Support/MathExtras.h"
@@ -2665,7 +2666,10 @@
   case ISD::FrameIndex:    return "FrameIndex";
   case ISD::ConstantPool:  return "ConstantPool";
   case ISD::ExternalSymbol: return "ExternalSymbol";
-  case ISD::INTRINSIC:     return "INTRINSIC";
+  case ISD::INTRINSIC:
+    bool hasChain = getOperand(0).getValueType() == MVT::Other;
+    unsigned IID = cast<ConstantSDNode>(getOperand(hasChain))->getValue();
+    return Intrinsic::getName((Intrinsic::ID)IID);
 
   case ISD::BUILD_VECTOR:   return "BUILD_VECTOR";
   case ISD::TargetConstant: return "TargetConstant";





From evan.cheng at apple.com  Mon Mar 27 00:59:00 2006
From: evan.cheng at apple.com (Evan Cheng)
Date: Mon, 27 Mar 2006 00:59:00 -0600
Subject: [llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp 
Message-ID: <200603270659.AAA11485@zion.cs.uiuc.edu>



Changes in directory llvm/lib/CodeGen/SelectionDAG:

SelectionDAG.cpp updated: 1.285 -> 1.286
---
Log message:

Change isBuildVectorAllOnesInteger to isBuildVectorAllOnes. Also check for
floating point cases.


---
Diffs of the changes:  (+39 -24)

 SelectionDAG.cpp |   63 ++++++++++++++++++++++++++++++++++---------------------
 1 files changed, 39 insertions(+), 24 deletions(-)


Index: llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp:1.285 llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp:1.286
--- llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp:1.285	Mon Mar 27 00:45:25 2006
+++ llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp	Mon Mar 27 00:58:47 2006
@@ -70,11 +70,10 @@
 //                              ISD Namespace
 //===----------------------------------------------------------------------===//
 
-/// isBuildVectorAllOnesInteger - Return true if the specified node is a
+/// isBuildVectorAllOnes - Return true if the specified node is a
 /// BUILD_VECTOR where all of the elements are ~0 or undef.
-bool ISD::isBuildVectorAllOnesInteger(const SDNode *N) {
-  if (N->getOpcode() != ISD::BUILD_VECTOR ||
-      !MVT::isInteger(N->getOperand(0).getValueType())) return false;
+bool ISD::isBuildVectorAllOnes(const SDNode *N) {
+  if (N->getOpcode() != ISD::BUILD_VECTOR) return false;
   
   unsigned i = 0, e = N->getNumOperands();
   
@@ -88,8 +87,13 @@
   // Do not accept build_vectors that aren't all constants or which have non-~0
   // elements.
   SDOperand NotZero = N->getOperand(i);
-  if (!isa<ConstantSDNode>(NotZero) ||
-      !cast<ConstantSDNode>(NotZero)->isAllOnesValue())
+  if (isa<ConstantSDNode>(NotZero)) {
+    if (!cast<ConstantSDNode>(NotZero)->isAllOnesValue())
+      return false;
+  } else if (isa<ConstantFPSDNode>(NotZero)) {
+    if (!cast<ConstantFPSDNode>(NotZero)->isExactlyValue(-1))
+      return false;
+  } else
     return false;
   
   // Okay, we have at least one ~0 value, check to see if the rest match or are
@@ -106,24 +110,35 @@
 /// BUILD_VECTOR where all of the elements are 0 or undef.
 bool ISD::isBuildVectorAllZeros(const SDNode *N) {
   if (N->getOpcode() != ISD::BUILD_VECTOR) return false;
-
-  bool AllUndef = true;
-  for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
-    SDOperand Elt = N->getOperand(i);
-    if (Elt.getOpcode() != ISD::UNDEF) {
-      AllUndef = false;
-      if (isa<ConstantSDNode>(Elt)) {
-        if (!cast<ConstantSDNode>(Elt)->isNullValue())
-          return false;
-      } else if (isa<ConstantFPSDNode>(Elt)) {
-        if (!cast<ConstantFPSDNode>(Elt)->isExactlyValue(0.0))
-          return false;
-      } else
-        return false;
-    }
-  }
-
-  return !AllUndef;
+  
+  unsigned i = 0, e = N->getNumOperands();
+  
+  // Skip over all of the undef values.
+  while (i != e && N->getOperand(i).getOpcode() == ISD::UNDEF)
+    ++i;
+  
+  // Do not accept an all-undef vector.
+  if (i == e) return false;
+  
+  // Do not accept build_vectors that aren't all constants or which have non-~0
+  // elements.
+  SDOperand Zero = N->getOperand(i);
+  if (isa<ConstantSDNode>(Zero)) {
+    if (!cast<ConstantSDNode>(Zero)->isNullValue())
+      return false;
+  } else if (isa<ConstantFPSDNode>(Zero)) {
+    if (!cast<ConstantFPSDNode>(Zero)->isExactlyValue(0.0))
+      return false;
+  } else
+    return false;
+  
+  // Okay, we have at least one ~0 value, check to see if the rest match or are
+  // undefs.
+  for (++i; i != e; ++i)
+    if (N->getOperand(i) != Zero &&
+        N->getOperand(i).getOpcode() != ISD::UNDEF)
+      return false;
+  return true;
 }
 
 /// getSetCCSwappedOperands - Return the operation corresponding to (Y op X)





From evan.cheng at apple.com  Mon Mar 27 00:59:00 2006
From: evan.cheng at apple.com (Evan Cheng)
Date: Mon, 27 Mar 2006 00:59:00 -0600
Subject: [llvm-commits] CVS: llvm/include/llvm/CodeGen/SelectionDAGNodes.h 
Message-ID: <200603270659.AAA11489@zion.cs.uiuc.edu>



Changes in directory llvm/include/llvm/CodeGen:

SelectionDAGNodes.h updated: 1.122 -> 1.123
---
Log message:

Change isBuildVectorAllOnesInteger to isBuildVectorAllOnes. Also check for
floating point cases.


---
Diffs of the changes:  (+2 -2)

 SelectionDAGNodes.h |    4 ++--
 1 files changed, 2 insertions(+), 2 deletions(-)


Index: llvm/include/llvm/CodeGen/SelectionDAGNodes.h
diff -u llvm/include/llvm/CodeGen/SelectionDAGNodes.h:1.122 llvm/include/llvm/CodeGen/SelectionDAGNodes.h:1.123
--- llvm/include/llvm/CodeGen/SelectionDAGNodes.h:1.122	Sun Mar 26 03:50:58 2006
+++ llvm/include/llvm/CodeGen/SelectionDAGNodes.h	Mon Mar 27 00:58:47 2006
@@ -455,9 +455,9 @@
 
   /// Node predicates
 
-  /// isBuildVectorAllOnesInteger - Return true if the specified node is a
+  /// isBuildVectorAllOnes - Return true if the specified node is a
   /// BUILD_VECTOR where all of the elements are ~0 or undef.
-  bool isBuildVectorAllOnesInteger(const SDNode *N);
+  bool isBuildVectorAllOnes(const SDNode *N);
 
   /// isBuildVectorAllZeros - Return true if the specified node is a
   /// BUILD_VECTOR where all of the elements are 0 or undef.





From evan.cheng at apple.com  Mon Mar 27 00:59:45 2006
From: evan.cheng at apple.com (Evan Cheng)
Date: Mon, 27 Mar 2006 00:59:45 -0600
Subject: [llvm-commits] CVS: llvm/lib/Target/TargetSelectionDAG.td 
Message-ID: <200603270659.AAA11509@zion.cs.uiuc.edu>



Changes in directory llvm/lib/Target:

TargetSelectionDAG.td updated: 1.60 -> 1.61
---
Log message:

Changed isBuildVectorAllOnesInteger to isBuildVectorAllOnes.


---
Diffs of the changes:  (+1 -1)

 TargetSelectionDAG.td |    2 +-
 1 files changed, 1 insertion(+), 1 deletion(-)


Index: llvm/lib/Target/TargetSelectionDAG.td
diff -u llvm/lib/Target/TargetSelectionDAG.td:1.60 llvm/lib/Target/TargetSelectionDAG.td:1.61
--- llvm/lib/Target/TargetSelectionDAG.td:1.60	Sun Mar 26 03:51:39 2006
+++ llvm/lib/Target/TargetSelectionDAG.td	Mon Mar 27 00:59:32 2006
@@ -384,7 +384,7 @@
 
 def immAllOnes : PatLeaf<(imm), [{ return N->isAllOnesValue(); }]>;
 def immAllOnesV: PatLeaf<(build_vector), [{
-  return ISD::isBuildVectorAllOnesInteger(N);
+  return ISD::isBuildVectorAllOnes(N);
 }]>;
 def immAllZerosV: PatLeaf<(build_vector), [{
   return ISD::isBuildVectorAllZeros(N);





From evan.cheng at apple.com  Mon Mar 27 01:00:29 2006
From: evan.cheng at apple.com (Evan Cheng)
Date: Mon, 27 Mar 2006 01:00:29 -0600
Subject: [llvm-commits] CVS: llvm/lib/Target/X86/X86ISelLowering.cpp
	X86InstrSSE.td 
Message-ID: <200603270700.BAA11557@zion.cs.uiuc.edu>



Changes in directory llvm/lib/Target/X86:

X86ISelLowering.cpp updated: 1.134 -> 1.135
X86InstrSSE.td updated: 1.32 -> 1.33
---
Log message:

Use pcmpeq to generate vector of all ones.


---
Diffs of the changes:  (+15 -0)

 X86ISelLowering.cpp |    4 ++++
 X86InstrSSE.td      |   11 +++++++++++
 2 files changed, 15 insertions(+)


Index: llvm/lib/Target/X86/X86ISelLowering.cpp
diff -u llvm/lib/Target/X86/X86ISelLowering.cpp:1.134 llvm/lib/Target/X86/X86ISelLowering.cpp:1.135
--- llvm/lib/Target/X86/X86ISelLowering.cpp:1.134	Sun Mar 26 19:32:24 2006
+++ llvm/lib/Target/X86/X86ISelLowering.cpp	Mon Mar 27 01:00:16 2006
@@ -2364,6 +2364,10 @@
     abort();
   }
   case ISD::BUILD_VECTOR: {
+    // All one's are handled with pcmpeqd.
+    if (ISD::isBuildVectorAllOnes(Op.Val))
+      return Op;
+
     std::set<SDOperand> Values;
     SDOperand Elt0 = Op.getOperand(0);
     Values.insert(Elt0);


Index: llvm/lib/Target/X86/X86InstrSSE.td
diff -u llvm/lib/Target/X86/X86InstrSSE.td:1.32 llvm/lib/Target/X86/X86InstrSSE.td:1.33
--- llvm/lib/Target/X86/X86InstrSSE.td:1.32	Sun Mar 26 03:53:12 2006
+++ llvm/lib/Target/X86/X86InstrSSE.td	Mon Mar 27 01:00:16 2006
@@ -1008,6 +1008,10 @@
                     "xorpd $dst, $dst",
                     [(set VR128:$dst, (v2f64 immAllZerosV))]>;
 
+def V_SETALLONES : PDI<0x76, MRMInitReg, (ops VR128:$dst),
+                       "pcmpeqd $dst, $dst",
+                       [(set VR128:$dst, (v2f64 immAllOnesV))]>;
+
 // Scalar to 128-bit vector with zero extension.
 // Three operand (but two address) aliases.
 let isTwoAddress = 1 in {
@@ -1051,6 +1055,13 @@
 def : Pat<(v8i16 immAllZerosV), (v8i16 (V_SET0_PI))>, Requires<[HasSSE2]>;
 def : Pat<(v4i32 immAllZerosV), (v4i32 (V_SET0_PI))>, Requires<[HasSSE2]>;
 
+// 128-bit vector all one's.
+def : Pat<(v16i8 immAllOnesV), (v16i8 (V_SETALLONES))>, Requires<[HasSSE2]>;
+def : Pat<(v8i16 immAllOnesV), (v8i16 (V_SETALLONES))>, Requires<[HasSSE2]>;
+def : Pat<(v4i32 immAllOnesV), (v4i32 (V_SETALLONES))>, Requires<[HasSSE2]>;
+def : Pat<(v2i64 immAllOnesV), (v2i64 (V_SETALLONES))>, Requires<[HasSSE2]>;
+def : Pat<(v4f32 immAllOnesV), (v4f32 (V_SETALLONES))>, Requires<[HasSSE1]>;
+
 // Load 128-bit integer vector values.
 def : Pat<(v16i8 (load addr:$src)), (MOVDQArm addr:$src)>,
       Requires<[HasSSE2]>;





From lattner at cs.uiuc.edu  Mon Mar 27 01:04:29 2006
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Mon, 27 Mar 2006 01:04:29 -0600
Subject: [llvm-commits] CVS: llvm/lib/Target/PowerPC/README_ALTIVEC.txt
	README.txt 
Message-ID: <200603270704.BAA11639@zion.cs.uiuc.edu>



Changes in directory llvm/lib/Target/PowerPC:

README_ALTIVEC.txt added (r1.1)
README.txt updated: 1.82 -> 1.83
---
Log message:

Split out altivec notes into their own README



---
Diffs of the changes:  (+56 -52)

 README.txt         |   54 +----------------------------------------------------
 README_ALTIVEC.txt |   54 +++++++++++++++++++++++++++++++++++++++++++++++++++++
 2 files changed, 56 insertions(+), 52 deletions(-)


Index: llvm/lib/Target/PowerPC/README_ALTIVEC.txt
diff -c /dev/null llvm/lib/Target/PowerPC/README_ALTIVEC.txt:1.1
*** /dev/null	Mon Mar 27 01:04:27 2006
--- llvm/lib/Target/PowerPC/README_ALTIVEC.txt	Mon Mar 27 01:04:16 2006
***************
*** 0 ****
--- 1,54 ----
+ //===- README_ALTIVEC.txt - Notes for improving Altivec code gen ----------===//
+ 
+ Implement TargetConstantVec, and set up PPC to custom lower ConstantVec into
+ TargetConstantVec's if it's one of the many forms that are algorithmically
+ computable using the spiffy altivec instructions.
+ 
+ //===----------------------------------------------------------------------===//
+ 
+ Implement PPCInstrInfo::isLoadFromStackSlot/isStoreToStackSlot for vector
+ registers, to generate better spill code.
+ 
+ //===----------------------------------------------------------------------===//
+ 
+ Altivec support.  The first should be a single lvx from the constant pool, the
+ second should be a xor/stvx:
+ 
+ void foo(void) {
+   int x[8] __attribute__((aligned(128))) = { 1, 1, 1, 1, 1, 1, 1, 1 };
+   bar (x);
+ }
+ 
+ #include <string.h>
+ void foo(void) {
+   int x[8] __attribute__((aligned(128)));
+   memset (x, 0, sizeof (x));
+   bar (x);
+ }
+ 
+ //===----------------------------------------------------------------------===//
+ 
+ Altivec: Codegen'ing MUL with vector FMADD should add -0.0, not 0.0:
+ http://gcc.gnu.org/bugzilla/show_bug.cgi?id=8763
+ 
+ We need to codegen -0.0 vector efficiently (no constant pool load).
+ 
+ When -ffast-math is on, we can use 0.0.
+ 
+ //===----------------------------------------------------------------------===//
+ 
+   Consider this:
+   v4f32 Vector;
+   v4f32 Vector2 = { Vector.X, Vector.X, Vector.X, Vector.X };
+ 
+ Since we know that "Vector" is 16-byte aligned and we know the element offset 
+ of ".X", we should change the load into a lve*x instruction, instead of doing
+ a load/store/lve*x sequence.
+ 
+ //===----------------------------------------------------------------------===//
+ 
+ There are a wide range of vector constants we can generate with combinations of
+ altivec instructions.  For example, GCC does: t=vsplti*, r = t+t.
+ 
+ //===----------------------------------------------------------------------===//
+ 


Index: llvm/lib/Target/PowerPC/README.txt
diff -u llvm/lib/Target/PowerPC/README.txt:1.82 llvm/lib/Target/PowerPC/README.txt:1.83
--- llvm/lib/Target/PowerPC/README.txt:1.82	Sat Mar 25 00:47:10 2006
+++ llvm/lib/Target/PowerPC/README.txt	Mon Mar 27 01:04:16 2006
@@ -1,3 +1,5 @@
+//===- README.txt - Notes for improving PowerPC-specific code gen ---------===//
+
 TODO:
 * gpr0 allocation
 * implement do-loop -> bdnz transform
@@ -309,12 +311,6 @@
 
 ===-------------------------------------------------------------------------===
 
-Implement TargetConstantVec, and set up PPC to custom lower ConstantVec into
-TargetConstantVec's if it's one of the many forms that are algorithmically
-computable using the spiffy altivec instructions.
-
-===-------------------------------------------------------------------------===
-
 Compile this:
 
 int foo(int a) {
@@ -502,11 +498,6 @@
 
 ===-------------------------------------------------------------------------===
 
-Implement PPCInstrInfo::isLoadFromStackSlot/isStoreToStackSlot for vector
-registers, to generate better spill code.
-
-===-------------------------------------------------------------------------===
-
 int foo(int N, int ***W, int **TK, int X) {
   int t, i;
   
@@ -524,32 +515,6 @@
 
 ===-------------------------------------------------------------------------===
 
-Altivec support.  The first should be a single lvx from the constant pool, the
-second should be a xor/stvx:
-
-void foo(void) {
-  int x[8] __attribute__((aligned(128))) = { 1, 1, 1, 1, 1, 1, 1, 1 };
-  bar (x);
-}
-
-#include <string.h>
-void foo(void) {
-  int x[8] __attribute__((aligned(128)));
-  memset (x, 0, sizeof (x));
-  bar (x);
-}
-
-===-------------------------------------------------------------------------===
-
-Altivec: Codegen'ing MUL with vector FMADD should add -0.0, not 0.0:
-http://gcc.gnu.org/bugzilla/show_bug.cgi?id=8763
-
-We need to codegen -0.0 vector efficiently (no constant pool load).
-
-When -ffast-math is on, we can use 0.0.
-
-===-------------------------------------------------------------------------===
-
 float foo(float X) { return (int)(X); }
 
 Currently produces:
@@ -571,16 +536,6 @@
 
 ===-------------------------------------------------------------------------===
 
-  Consider this:
-  v4f32 Vector;
-  v4f32 Vector2 = { Vector.X, Vector.X, Vector.X, Vector.X };
-
-Since we know that "Vector" is 16-byte aligned and we know the element offset 
-of ".X", we should change the load into a lve*x instruction, instead of doing
-a load/store/lve*x sequence.
-
-===-------------------------------------------------------------------------===
-
 We generate ugly code for this:
 
 void func(unsigned int *ret, float dx, float dy, float dz, float dw) {
@@ -596,8 +551,3 @@
 
 ===-------------------------------------------------------------------------===
 
-There are a wide range of vector constants we can generate with combinations of
-altivec instructions.  For example, GCC does: t=vsplti*, r = t+t.
-
-===-------------------------------------------------------------------------===
-





From evan.cheng at apple.com  Mon Mar 27 01:26:30 2006
From: evan.cheng at apple.com (Evan Cheng)
Date: Mon, 27 Mar 2006 01:26:30 -0600
Subject: [llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp 
Message-ID: <200603270726.BAA11774@zion.cs.uiuc.edu>



Changes in directory llvm/lib/CodeGen/SelectionDAG:

SelectionDAG.cpp updated: 1.286 -> 1.287
---
Log message:

Incorrect check for FP all one's

---
Diffs of the changes:  (+2 -1)

 SelectionDAG.cpp |    3 ++-
 1 files changed, 2 insertions(+), 1 deletion(-)


Index: llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp:1.286 llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp:1.287
--- llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp:1.286	Mon Mar 27 00:58:47 2006
+++ llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp	Mon Mar 27 01:26:17 2006
@@ -91,7 +91,8 @@
     if (!cast<ConstantSDNode>(NotZero)->isAllOnesValue())
       return false;
   } else if (isa<ConstantFPSDNode>(NotZero)) {
-    if (!cast<ConstantFPSDNode>(NotZero)->isExactlyValue(-1))
+    if (DoubleToBits(cast<ConstantFPSDNode>(NotZero)->getValue()) ==
+        (0ULL - 1))
       return false;
   } else
     return false;





From lattner at cs.uiuc.edu  Mon Mar 27 01:41:13 2006
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Mon, 27 Mar 2006 01:41:13 -0600
Subject: [llvm-commits] CVS: llvm/lib/Target/PowerPC/README_ALTIVEC.txt 
Message-ID: <200603270741.BAA11972@zion.cs.uiuc.edu>



Changes in directory llvm/lib/Target/PowerPC:

README_ALTIVEC.txt updated: 1.1 -> 1.2
---
Log message:

Add a bunch of notes from my journey thus far.


---
Diffs of the changes:  (+103 -9)

 README_ALTIVEC.txt |  112 ++++++++++++++++++++++++++++++++++++++++++++++++-----
 1 files changed, 103 insertions(+), 9 deletions(-)


Index: llvm/lib/Target/PowerPC/README_ALTIVEC.txt
diff -u llvm/lib/Target/PowerPC/README_ALTIVEC.txt:1.1 llvm/lib/Target/PowerPC/README_ALTIVEC.txt:1.2
--- llvm/lib/Target/PowerPC/README_ALTIVEC.txt:1.1	Mon Mar 27 01:04:16 2006
+++ llvm/lib/Target/PowerPC/README_ALTIVEC.txt	Mon Mar 27 01:41:00 2006
@@ -1,11 +1,5 @@
 //===- README_ALTIVEC.txt - Notes for improving Altivec code gen ----------===//
 
-Implement TargetConstantVec, and set up PPC to custom lower ConstantVec into
-TargetConstantVec's if it's one of the many forms that are algorithmically
-computable using the spiffy altivec instructions.
-
-//===----------------------------------------------------------------------===//
-
 Implement PPCInstrInfo::isLoadFromStackSlot/isStoreToStackSlot for vector
 registers, to generate better spill code.
 
@@ -31,8 +25,6 @@
 Altivec: Codegen'ing MUL with vector FMADD should add -0.0, not 0.0:
 http://gcc.gnu.org/bugzilla/show_bug.cgi?id=8763
 
-We need to codegen -0.0 vector efficiently (no constant pool load).
-
 When -ffast-math is on, we can use 0.0.
 
 //===----------------------------------------------------------------------===//
@@ -48,7 +40,109 @@
 //===----------------------------------------------------------------------===//
 
 There are a wide range of vector constants we can generate with combinations of
-altivec instructions.  For example, GCC does: t=vsplti*, r = t+t.
+altivec instructions.  Examples
+ GCC does: "t=vsplti*, r = t+t"  for constants it can't generate with one vsplti
+
+ -0.0 (sign bit):  vspltisw v0,-1 / vslw v0,v0,v0
+
+//===----------------------------------------------------------------------===//
+
+Missing intrinsics:
+
+ds*
+lve*
+lvs*
+lvx*
+mf*
+st*
+vavg*
+vexptefp
+vlogefp
+vmax*
+vmhaddshs/vmhraddshs
+vmin*
+vmladduhm
+vmr*
+vmsum*
+vmul*
+vperm
+vpk*
+vr*
+vsel (some aliases only accessible using builtins)
+vsl* (except vsldoi)
+vsr*
+vsum*
+vup*
+
+//===----------------------------------------------------------------------===//
+
+FABS/FNEG can be codegen'd with the appropriate and/xor of -0.0.
+
+//===----------------------------------------------------------------------===//
+
+For functions that use altivec AND have calls, we are VRSAVE'ing all call
+clobbered regs.
+
+//===----------------------------------------------------------------------===//
+
+VSPLTW and friends are expanded by the FE into insert/extract element ops.  Make
+sure that the dag combiner puts them back together in the appropriate 
+vector_shuffle node and that this gets pattern matched appropriately.
+
+//===----------------------------------------------------------------------===//
+
+Implement passing/returning vectors by value.
+
+//===----------------------------------------------------------------------===//
+
+GCC apparently tries to codegen { C1, C2, Variable, C3 } as a constant pool load
+of C1/C2/C3, then a load and vperm of Variable.
+
+//===----------------------------------------------------------------------===//
+
+We currently codegen SCALAR_TO_VECTOR as a store of the scalar to a 16-byte
+aligned stack slot, followed by a lve*x/vperm.  We should probably just store it
+to a scalar stack slot, then use lvsl/vperm to load it.  If the value is already
+in memory, this is a huge win.
+
+//===----------------------------------------------------------------------===//
+
+Do not generate the MFCR/RLWINM sequence for predicate compares when the
+predicate compare is used immediately by a branch.  Just branch on the right
+cond code on CR6.
+
+//===----------------------------------------------------------------------===//
+
+SROA should turn "vector unions" into the appropriate insert/extract element
+instructions.
+ 
+//===----------------------------------------------------------------------===//
+
+We need an LLVM 'shuffle' instruction, that corresponds to the VECTOR_SHUFFLE
+node.
+
+//===----------------------------------------------------------------------===//
+
+We need a way to teach tblgen that some operands of an intrinsic are required to
+be constants.  The verifier should enforce this constraint.
 
 //===----------------------------------------------------------------------===//
 
+We should instcombine the lvx/stvx intrinsics into loads/stores if we know that
+the loaded address is 16-byte aligned.
+
+//===----------------------------------------------------------------------===//
+
+Instead of writting a pattern for type-agnostic operations (e.g. gen-zero, load,
+store, and, ...) in every supported type, make legalize do the work.  We should
+have a canonical type that we want operations changed to (e.g. v4i32 for
+build_vector) and legalize should change non-identical types to thse.  This is
+similar to what it does for operations that are only supported in some types,
+e.g. x86 cmov (not supported on bytes).
+
+This would fix two problems:
+1. Writing patterns multiple times.
+2. Identical operations in different types are not getting CSE'd (e.g. 
+   { 0U, 0U, 0U, 0U } and {0.0, 0.0, 0.0, 0.0}.
+
+





From evan.cheng at apple.com  Mon Mar 27 02:10:39 2006
From: evan.cheng at apple.com (Evan Cheng)
Date: Mon, 27 Mar 2006 02:10:39 -0600
Subject: [llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp 
Message-ID: <200603270810.CAA13143@zion.cs.uiuc.edu>



Changes in directory llvm/lib/CodeGen/SelectionDAG:

SelectionDAG.cpp updated: 1.287 -> 1.288
---
Log message:

Try again

---
Diffs of the changes:  (+10 -3)

 SelectionDAG.cpp |   13 ++++++++++---
 1 files changed, 10 insertions(+), 3 deletions(-)


Index: llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp:1.287 llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp:1.288
--- llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp:1.287	Mon Mar 27 01:26:17 2006
+++ llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp	Mon Mar 27 02:10:26 2006
@@ -91,9 +91,16 @@
     if (!cast<ConstantSDNode>(NotZero)->isAllOnesValue())
       return false;
   } else if (isa<ConstantFPSDNode>(NotZero)) {
-    if (DoubleToBits(cast<ConstantFPSDNode>(NotZero)->getValue()) ==
-        (0ULL - 1))
-      return false;
+    MVT::ValueType VT = NotZero.getValueType();
+    if (VT== MVT::f64) {
+      if (DoubleToBits(cast<ConstantFPSDNode>(NotZero)->getValue()) !=
+          (uint64_t)-1)
+        return false;
+    } else {
+      if (FloatToBits(cast<ConstantFPSDNode>(NotZero)->getValue()) !=
+          (uint32_t)-1)
+        return false;
+    }
   } else
     return false;
   





From evan.cheng at apple.com  Mon Mar 27 02:23:25 2006
From: evan.cheng at apple.com (Evan Cheng)
Date: Mon, 27 Mar 2006 02:23:25 -0600
Subject: [llvm-commits] CVS: llvm/include/llvm/IntrinsicsX86.td 
Message-ID: <200603270823.CAA16404@zion.cs.uiuc.edu>



Changes in directory llvm/include/llvm:

IntrinsicsX86.td updated: 1.1 -> 1.2
---
Log message:

Intrinsics naming convention change.

---
Diffs of the changes:  (+69 -65)

 IntrinsicsX86.td |  134 ++++++++++++++++++++++++++++---------------------------
 1 files changed, 69 insertions(+), 65 deletions(-)


Index: llvm/include/llvm/IntrinsicsX86.td
diff -u llvm/include/llvm/IntrinsicsX86.td:1.1 llvm/include/llvm/IntrinsicsX86.td:1.2
--- llvm/include/llvm/IntrinsicsX86.td:1.1	Sat Mar 25 20:37:19 2006
+++ llvm/include/llvm/IntrinsicsX86.td	Mon Mar 27 02:23:12 2006
@@ -17,186 +17,186 @@
 
 // Arithmetic ops
 let TargetPrefix = "x86" in {  // All intrinsics start with "llvm.x86.".
-  def int_x86_sse_addss : GCCBuiltin<"__builtin_ia32_addss">,
+  def int_x86_sse_add_ss : GCCBuiltin<"__builtin_ia32_addss">,
               Intrinsic<[llvm_float_ty, llvm_float_ty,
                          llvm_float_ty], [InstrNoMem]>;
-  def int_x86_sse_addps : GCCBuiltin<"__builtin_ia32_addps">,
+  def int_x86_sse_add_ps : GCCBuiltin<"__builtin_ia32_addps">,
               Intrinsic<[llvm_v4f32_ty, llvm_v4f32_ty,
                          llvm_v4f32_ty], [InstrNoMem]>;
-  def int_x86_sse_subss : GCCBuiltin<"__builtin_ia32_subss">,
+  def int_x86_sse_sub_ss : GCCBuiltin<"__builtin_ia32_subss">,
               Intrinsic<[llvm_float_ty, llvm_float_ty,
                          llvm_float_ty], [InstrNoMem]>;
-  def int_x86_sse_subps : GCCBuiltin<"__builtin_ia32_subps">,
+  def int_x86_sse_sub_ps : GCCBuiltin<"__builtin_ia32_subps">,
               Intrinsic<[llvm_v4f32_ty, llvm_v4f32_ty,
                          llvm_v4f32_ty], [InstrNoMem]>;
-  def int_x86_sse_mulss : GCCBuiltin<"__builtin_ia32_mulss">,
+  def int_x86_sse_mul_ss : GCCBuiltin<"__builtin_ia32_mulss">,
               Intrinsic<[llvm_float_ty, llvm_float_ty,
                          llvm_float_ty], [InstrNoMem]>;
-  def int_x86_sse_mulps : GCCBuiltin<"__builtin_ia32_mulps">,
+  def int_x86_sse_mul_ps : GCCBuiltin<"__builtin_ia32_mulps">,
               Intrinsic<[llvm_v4f32_ty, llvm_v4f32_ty,
                          llvm_v4f32_ty], [InstrNoMem]>;
-  def int_x86_sse_divss : GCCBuiltin<"__builtin_ia32_divss">,
+  def int_x86_sse_div_ss : GCCBuiltin<"__builtin_ia32_divss">,
               Intrinsic<[llvm_float_ty, llvm_float_ty,
                          llvm_float_ty], [InstrNoMem]>;
-  def int_x86_sse_divps : GCCBuiltin<"__builtin_ia32_divps">,
+  def int_x86_sse_div_ps : GCCBuiltin<"__builtin_ia32_divps">,
               Intrinsic<[llvm_v4f32_ty, llvm_v4f32_ty,
                          llvm_v4f32_ty], [InstrNoMem]>;
-  def int_x86_sse_sqrtss : GCCBuiltin<"__builtin_ia32_sqrtss">,
+  def int_x86_sse_sqrt_ss : GCCBuiltin<"__builtin_ia32_sqrtss">,
               Intrinsic<[llvm_float_ty, llvm_float_ty,
                          llvm_float_ty], [InstrNoMem]>;
-  def int_x86_sse_sqrtps : GCCBuiltin<"__builtin_ia32_sqrtps">,
+  def int_x86_sse_sqrt_ps : GCCBuiltin<"__builtin_ia32_sqrtps">,
               Intrinsic<[llvm_v4f32_ty, llvm_v4f32_ty,
                          llvm_v4f32_ty], [InstrNoMem]>;
-  def int_x86_sse_rcpss : GCCBuiltin<"__builtin_ia32_rcpss">,
+  def int_x86_sse_rcp_ss : GCCBuiltin<"__builtin_ia32_rcpss">,
               Intrinsic<[llvm_float_ty, llvm_float_ty,
                          llvm_float_ty], [InstrNoMem]>;
-  def int_x86_sse_rcpps : GCCBuiltin<"__builtin_ia32_rcpps">,
+  def int_x86_sse_rcp_ps : GCCBuiltin<"__builtin_ia32_rcpps">,
               Intrinsic<[llvm_v4f32_ty, llvm_v4f32_ty,
                          llvm_v4f32_ty], [InstrNoMem]>;
-  def int_x86_sse_rsqrtss : GCCBuiltin<"__builtin_ia32_rsqrtss">,
+  def int_x86_sse_rsqrt_ss : GCCBuiltin<"__builtin_ia32_rsqrtss">,
               Intrinsic<[llvm_float_ty, llvm_float_ty,
                          llvm_float_ty], [InstrNoMem]>;
-  def int_x86_sse_rsqrtps : GCCBuiltin<"__builtin_ia32_rsqrtps">,
+  def int_x86_sse_rsqrt_ps : GCCBuiltin<"__builtin_ia32_rsqrtps">,
               Intrinsic<[llvm_v4f32_ty, llvm_v4f32_ty,
                          llvm_v4f32_ty], [InstrNoMem]>;
-  def int_x86_sse_minss : GCCBuiltin<"__builtin_ia32_minss">,
+  def int_x86_sse_min_ss : GCCBuiltin<"__builtin_ia32_minss">,
               Intrinsic<[llvm_float_ty, llvm_float_ty,
                          llvm_float_ty], [InstrNoMem]>;
-  def int_x86_sse_minps : GCCBuiltin<"__builtin_ia32_minps">,
+  def int_x86_sse_min_ps : GCCBuiltin<"__builtin_ia32_minps">,
               Intrinsic<[llvm_v4f32_ty, llvm_v4f32_ty,
                          llvm_v4f32_ty], [InstrNoMem]>;
-  def int_x86_sse_maxss : GCCBuiltin<"__builtin_ia32_maxss">,
+  def int_x86_sse_max_ss : GCCBuiltin<"__builtin_ia32_maxss">,
               Intrinsic<[llvm_float_ty, llvm_float_ty,
                          llvm_float_ty], [InstrNoMem]>;
-  def int_x86_sse_maxps : GCCBuiltin<"__builtin_ia32_maxps">,
+  def int_x86_sse_max_ps : GCCBuiltin<"__builtin_ia32_maxps">,
               Intrinsic<[llvm_v4f32_ty, llvm_v4f32_ty,
                          llvm_v4f32_ty], [InstrNoMem]>;
 }
 
 // Logical ops
 let TargetPrefix = "x86" in {  // All intrinsics start with "llvm.x86.".
-  def int_x86_sse_andps : GCCBuiltin<"__builtin_ia32_andps">,
+  def int_x86_sse_and_ps : GCCBuiltin<"__builtin_ia32_andps">,
               Intrinsic<[llvm_v4f32_ty, llvm_v4f32_ty,
                          llvm_v4f32_ty], [InstrNoMem]>;
-  def int_x86_sse_andnotps : GCCBuiltin<"__builtin_ia32_andnotps">,
+  def int_x86_sse_andnot_ps : GCCBuiltin<"__builtin_ia32_andnotps">,
               Intrinsic<[llvm_v4f32_ty, llvm_v4f32_ty,
                          llvm_v4f32_ty], [InstrNoMem]>;
-  def int_x86_sse_orps : GCCBuiltin<"__builtin_ia32_orps">,
+  def int_x86_sse_or_ps : GCCBuiltin<"__builtin_ia32_orps">,
               Intrinsic<[llvm_v4f32_ty, llvm_v4f32_ty,
                          llvm_v4f32_ty], [InstrNoMem]>;
-  def int_x86_sse_xorps : GCCBuiltin<"__builtin_ia32_xorps">,
+  def int_x86_sse_xor_ps : GCCBuiltin<"__builtin_ia32_xorps">,
               Intrinsic<[llvm_v4f32_ty, llvm_v4f32_ty,
                          llvm_v4f32_ty], [InstrNoMem]>;
 }
 
 // Comparison ops
 let TargetPrefix = "x86" in {  // All intrinsics start with "llvm.x86.".
-  def int_x86_sse_cmpeqss : GCCBuiltin<"__builtin_ia32_cmpeqss">,
+  def int_x86_sse_cmpeq_ss : GCCBuiltin<"__builtin_ia32_cmpeqss">,
               Intrinsic<[llvm_float_ty, llvm_float_ty,
                          llvm_v4f32_ty], [InstrNoMem]>;
-  def int_x86_sse_cmpeqps : GCCBuiltin<"__builtin_ia32_cmpeqps">,
+  def int_x86_sse_cmpeq_ps : GCCBuiltin<"__builtin_ia32_cmpeqps">,
               Intrinsic<[llvm_v4f32_ty, llvm_v4f32_ty,
                          llvm_v4f32_ty], [InstrNoMem]>;
-  def int_x86_sse_cmpltss : GCCBuiltin<"__builtin_ia32_cmpltss">,
+  def int_x86_sse_cmplt_ss : GCCBuiltin<"__builtin_ia32_cmpltss">,
               Intrinsic<[llvm_float_ty, llvm_float_ty,
                          llvm_float_ty], [InstrNoMem]>;
-  def int_x86_sse_cmpltps : GCCBuiltin<"__builtin_ia32_cmpltps">,
+  def int_x86_sse_cmplt_ps : GCCBuiltin<"__builtin_ia32_cmpltps">,
               Intrinsic<[llvm_v4f32_ty, llvm_v4f32_ty,
                          llvm_v4f32_ty], [InstrNoMem]>;
-  def int_x86_sse_cmpless : GCCBuiltin<"__builtin_ia32_cmpless">,
+  def int_x86_sse_cmple_ss : GCCBuiltin<"__builtin_ia32_cmpless">,
               Intrinsic<[llvm_float_ty, llvm_float_ty,
                          llvm_float_ty], [InstrNoMem]>;
-  def int_x86_sse_cmpleps : GCCBuiltin<"__builtin_ia32_cmpleps">,
+  def int_x86_sse_cmple_ps : GCCBuiltin<"__builtin_ia32_cmpleps">,
               Intrinsic<[llvm_v4f32_ty, llvm_v4f32_ty,
                          llvm_v4f32_ty], [InstrNoMem]>;
-  def int_x86_sse_cmpgtss : GCCBuiltin<"__builtin_ia32_cmpgtss">,
+  def int_x86_sse_cmpgt_ss : GCCBuiltin<"__builtin_ia32_cmpgtss">,
               Intrinsic<[llvm_float_ty, llvm_float_ty,
                          llvm_float_ty], [InstrNoMem]>;
-  def int_x86_sse_cmpgtps : GCCBuiltin<"__builtin_ia32_cmpgtps">,
+  def int_x86_sse_cmpgt_ps : GCCBuiltin<"__builtin_ia32_cmpgtps">,
               Intrinsic<[llvm_v4f32_ty, llvm_v4f32_ty,
                          llvm_v4f32_ty], [InstrNoMem]>;
-  def int_x86_sse_cmpgess : GCCBuiltin<"__builtin_ia32_cmpgess">,
+  def int_x86_sse_cmpge_ss : GCCBuiltin<"__builtin_ia32_cmpgess">,
               Intrinsic<[llvm_float_ty, llvm_float_ty,
                          llvm_float_ty], [InstrNoMem]>;
-  def int_x86_sse_cmpgeps : GCCBuiltin<"__builtin_ia32_cmpgeps">,
+  def int_x86_sse_cmpge_ps : GCCBuiltin<"__builtin_ia32_cmpgeps">,
               Intrinsic<[llvm_v4f32_ty, llvm_v4f32_ty,
                          llvm_v4f32_ty], [InstrNoMem]>;
-  def int_x86_sse_cmpneqss : GCCBuiltin<"__builtin_ia32_cmpneqss">,
+  def int_x86_sse_cmpneq_ss : GCCBuiltin<"__builtin_ia32_cmpneqss">,
               Intrinsic<[llvm_float_ty, llvm_float_ty,
                          llvm_float_ty], [InstrNoMem]>;
-  def int_x86_sse_cmpneqps : GCCBuiltin<"__builtin_ia32_cmpneqps">,
+  def int_x86_sse_cmpneq_ps : GCCBuiltin<"__builtin_ia32_cmpneqps">,
               Intrinsic<[llvm_v4f32_ty, llvm_v4f32_ty,
                          llvm_v4f32_ty], [InstrNoMem]>;
-  def int_x86_sse_cmpnltss : GCCBuiltin<"__builtin_ia32_cmpnltss">,
+  def int_x86_sse_cmpnlt_ss : GCCBuiltin<"__builtin_ia32_cmpnltss">,
               Intrinsic<[llvm_float_ty, llvm_float_ty,
                          llvm_float_ty], [InstrNoMem]>;
-  def int_x86_sse_cmpnltps : GCCBuiltin<"__builtin_ia32_cmpnltps">,
+  def int_x86_sse_cmpnlt_ps : GCCBuiltin<"__builtin_ia32_cmpnltps">,
               Intrinsic<[llvm_v4f32_ty, llvm_v4f32_ty,
                          llvm_v4f32_ty], [InstrNoMem]>;
-  def int_x86_sse_cmpnless : GCCBuiltin<"__builtin_ia32_cmpnless">,
+  def int_x86_sse_cmpnle_ss : GCCBuiltin<"__builtin_ia32_cmpnless">,
               Intrinsic<[llvm_float_ty, llvm_float_ty,
                          llvm_float_ty], [InstrNoMem]>;
-  def int_x86_sse_cmpnleps : GCCBuiltin<"__builtin_ia32_cmpnleps">,
+  def int_x86_sse_cmpnle_ps : GCCBuiltin<"__builtin_ia32_cmpnleps">,
               Intrinsic<[llvm_v4f32_ty, llvm_v4f32_ty,
                          llvm_v4f32_ty], [InstrNoMem]>;
-  def int_x86_sse_cmpngtss : GCCBuiltin<"__builtin_ia32_cmpngtss">,
+  def int_x86_sse_cmpngt_ss : GCCBuiltin<"__builtin_ia32_cmpngtss">,
               Intrinsic<[llvm_float_ty, llvm_float_ty,
                          llvm_float_ty], [InstrNoMem]>;
-  def int_x86_sse_cmpngtps : GCCBuiltin<"__builtin_ia32_cmpngtps">,
+  def int_x86_sse_cmpngt_ps : GCCBuiltin<"__builtin_ia32_cmpngtps">,
               Intrinsic<[llvm_v4f32_ty, llvm_v4f32_ty,
                          llvm_v4f32_ty], [InstrNoMem]>;
-  def int_x86_sse_cmpngess : GCCBuiltin<"__builtin_ia32_cmpngess">,
+  def int_x86_sse_cmpnge_ss : GCCBuiltin<"__builtin_ia32_cmpngess">,
               Intrinsic<[llvm_float_ty, llvm_float_ty,
                          llvm_float_ty], [InstrNoMem]>;
-  def int_x86_sse_cmpngeps : GCCBuiltin<"__builtin_ia32_cmpngeps">,
+  def int_x86_sse_cmpnge_ps : GCCBuiltin<"__builtin_ia32_cmpngeps">,
               Intrinsic<[llvm_v4f32_ty, llvm_v4f32_ty,
                          llvm_v4f32_ty], [InstrNoMem]>;
-  def int_x86_sse_cmpordss : GCCBuiltin<"__builtin_ia32_cmpordss">,
+  def int_x86_sse_cmpord_ss : GCCBuiltin<"__builtin_ia32_cmpordss">,
               Intrinsic<[llvm_float_ty, llvm_float_ty,
                          llvm_float_ty], [InstrNoMem]>;
-  def int_x86_sse_cmpordps : GCCBuiltin<"__builtin_ia32_cmpordps">,
+  def int_x86_sse_cmpord_ps : GCCBuiltin<"__builtin_ia32_cmpordps">,
               Intrinsic<[llvm_v4f32_ty, llvm_v4f32_ty,
                          llvm_v4f32_ty], [InstrNoMem]>;
-  def int_x86_sse_cmpunordss : GCCBuiltin<"__builtin_ia32_cmpunordss">,
+  def int_x86_sse_cmpunord_ss : GCCBuiltin<"__builtin_ia32_cmpunordss">,
               Intrinsic<[llvm_float_ty, llvm_float_ty,
                          llvm_float_ty], [InstrNoMem]>;
-  def int_x86_sse_cmpunordps : GCCBuiltin<"__builtin_ia32_cmpunordps">,
+  def int_x86_sse_cmpunord_ps : GCCBuiltin<"__builtin_ia32_cmpunordps">,
               Intrinsic<[llvm_v4f32_ty, llvm_v4f32_ty,
                          llvm_v4f32_ty], [InstrNoMem]>;
-  def int_x86_sse_comieqss : GCCBuiltin<"__builtin_ia32_comieq">,
+  def int_x86_sse_comieq_ss : GCCBuiltin<"__builtin_ia32_comieq">,
               Intrinsic<[llvm_int_ty, llvm_float_ty,
                          llvm_float_ty], [InstrNoMem]>;
-  def int_x86_sse_comiltss : GCCBuiltin<"__builtin_ia32_comilt">,
+  def int_x86_sse_comilt_ss : GCCBuiltin<"__builtin_ia32_comilt">,
               Intrinsic<[llvm_int_ty, llvm_float_ty,
                          llvm_float_ty], [InstrNoMem]>;
-  def int_x86_sse_comiless : GCCBuiltin<"__Builtin_ia32_comile">,
+  def int_x86_sse_comile_ss : GCCBuiltin<"__Builtin_ia32_comile">,
               Intrinsic<[llvm_int_ty, llvm_float_ty,
                          llvm_float_ty], [InstrNoMem]>;
-  def int_x86_sse_comigtss : GCCBuiltin<"__builtin_ia32_comigt">,
+  def int_x86_sse_comigt_ss : GCCBuiltin<"__builtin_ia32_comigt">,
               Intrinsic<[llvm_int_ty, llvm_float_ty,
                          llvm_float_ty], [InstrNoMem]>;
-  def int_x86_sse_comigess : GCCBuiltin<"__builtin_ia32_comige">,
+  def int_x86_sse_comige_ss : GCCBuiltin<"__builtin_ia32_comige">,
               Intrinsic<[llvm_int_ty, llvm_float_ty,
                          llvm_float_ty], [InstrNoMem]>;
-  def int_x86_sse_comineqss : GCCBuiltin<"__builtin_ia32_comineq">,
+  def int_x86_sse_comineq_ss : GCCBuiltin<"__builtin_ia32_comineq">,
               Intrinsic<[llvm_int_ty, llvm_float_ty,
                          llvm_float_ty], [InstrNoMem]>;
-  def int_x86_sse_ucomieqss : GCCBuiltin<"__builtin_ia32_ucomieq">,
+  def int_x86_sse_ucomieq_ss : GCCBuiltin<"__builtin_ia32_ucomieq">,
               Intrinsic<[llvm_int_ty, llvm_float_ty,
                          llvm_float_ty], [InstrNoMem]>;
-  def int_x86_sse_ucomiltss : GCCBuiltin<"__builtin_ia32_ucomilt">,
+  def int_x86_sse_ucomilt_ss : GCCBuiltin<"__builtin_ia32_ucomilt">,
               Intrinsic<[llvm_int_ty, llvm_float_ty,
                          llvm_float_ty], [InstrNoMem]>;
-  def int_x86_sse_ucomiless : GCCBuiltin<"__Builtin_ia32_ucomile">,
+  def int_x86_sse_ucomile_ss : GCCBuiltin<"__Builtin_ia32_ucomile">,
               Intrinsic<[llvm_int_ty, llvm_float_ty,
                          llvm_float_ty], [InstrNoMem]>;
-  def int_x86_sse_ucomigtss : GCCBuiltin<"__builtin_ia32_ucomigt">,
+  def int_x86_sse_ucomigt_ss : GCCBuiltin<"__builtin_ia32_ucomigt">,
               Intrinsic<[llvm_int_ty, llvm_float_ty,
                          llvm_float_ty], [InstrNoMem]>;
-  def int_x86_sse_ucomigess : GCCBuiltin<"__builtin_ia32_ucomige">,
+  def int_x86_sse_ucomige_ss : GCCBuiltin<"__builtin_ia32_ucomige">,
               Intrinsic<[llvm_int_ty, llvm_float_ty,
                          llvm_float_ty], [InstrNoMem]>;
-  def int_x86_sse_ucomineqss : GCCBuiltin<"__builtin_ia32_ucomineq">,
+  def int_x86_sse_ucomineq_ss : GCCBuiltin<"__builtin_ia32_ucomineq">,
               Intrinsic<[llvm_int_ty, llvm_float_ty,
                          llvm_float_ty], [InstrNoMem]>;
 }
@@ -220,21 +220,21 @@
 
 // SIMD load ops
 let TargetPrefix = "x86" in {  // All intrinsics start with "llvm.x86.".
-  def int_x86_sse_loadhps : GCCBuiltin<"__builtin_ia32_loadhps">,
+  def int_x86_sse_loadh_ps : GCCBuiltin<"__builtin_ia32_loadhps">,
               Intrinsic<[llvm_v4f32_ty, llvm_ptr_ty], [IntrReadMem]>;
-  def int_x86_sse_loadlps : GCCBuiltin<"__builtin_ia32_loadlps">,
+  def int_x86_sse_loadl_ps : GCCBuiltin<"__builtin_ia32_loadlps">,
               Intrinsic<[llvm_v4f32_ty, llvm_ptr_ty], [IntrReadMem]>;
-  def int_x86_sse_loadups : GCCBuiltin<"__builtin_ia32_loadups">,
+  def int_x86_sse_loadu_ps : GCCBuiltin<"__builtin_ia32_loadups">,
               Intrinsic<[llvm_v4f32_ty, llvm_ptr_ty], [IntrReadMem]>;
 }
 
 // SIMD store ops
 let TargetPrefix = "x86" in {  // All intrinsics start with "llvm.x86.".
-  def int_x86_sse_storehps : GCCBuiltin<"__builtin_ia32_storehps">,
+  def int_x86_sse_storeh_ps : GCCBuiltin<"__builtin_ia32_storehps">,
               Intrinsic<[llvm_ptr_ty, llvm_v4f32_ty], [IntrWriteMem]>;
-  def int_x86_sse_storelps : GCCBuiltin<"__builtin_ia32_storelps">,
+  def int_x86_sse_storel_ps : GCCBuiltin<"__builtin_ia32_storelps">,
               Intrinsic<[llvm_ptr_ty, llvm_v4f32_ty], [IntrWriteMem]>;
-  def int_x86_sse_storeups : GCCBuiltin<"__builtin_ia32_storeups">,
+  def int_x86_sse_storeu_ps : GCCBuiltin<"__builtin_ia32_storeups">,
               Intrinsic<[llvm_ptr_ty, llvm_v4f32_ty], [IntrWriteMem]>;
 }
 
@@ -248,7 +248,11 @@
               Intrinsic<[llvm_ptr_ty, llvm_v4f32_ty], [IntrWriteMem]>;
   def int_x86_sse_sfence : GCCBuiltin<"__builtin_ia32_sfence">,
               Intrinsic<[llvm_void_ty], [IntrWriteMem]>;
-  def int_x86_sse_movmskps : GCCBuiltin<"__builtin_ia32_movmskps">,
+}
+
+// Misc.
+let TargetPrefix = "x86" in {  // All intrinsics start with "llvm.x86.".
+  def int_x86_sse_movmsk_ps : GCCBuiltin<"__builtin_ia32_movmskps">,
               Intrinsic<[llvm_int_ty, llvm_v4f32_ty], [InstrNoMem]>;
   def int_x86_sse_ldmxcsr : GCCBuiltin<"__builtin_ia32_ldmxcsr">,
               Intrinsic<[llvm_void_ty, llvm_ptr_ty], [IntrWriteMem]>;





From lattner at cs.uiuc.edu  Mon Mar 27 10:11:13 2006
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Mon, 27 Mar 2006 10:11:13 -0600
Subject: [llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp 
Message-ID: <200603271611.KAA13679@zion.cs.uiuc.edu>



Changes in directory llvm/lib/CodeGen/SelectionDAG:

SelectionDAG.cpp updated: 1.288 -> 1.289
---
Log message:

Unbreak the build on non-apple compilers :-(


---
Diffs of the changes:  (+2 -1)

 SelectionDAG.cpp |    3 ++-
 1 files changed, 2 insertions(+), 1 deletion(-)


Index: llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp:1.288 llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp:1.289
--- llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp:1.288	Mon Mar 27 02:10:26 2006
+++ llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp	Mon Mar 27 10:10:59 2006
@@ -2689,10 +2689,11 @@
   case ISD::FrameIndex:    return "FrameIndex";
   case ISD::ConstantPool:  return "ConstantPool";
   case ISD::ExternalSymbol: return "ExternalSymbol";
-  case ISD::INTRINSIC:
+  case ISD::INTRINSIC: {
     bool hasChain = getOperand(0).getValueType() == MVT::Other;
     unsigned IID = cast<ConstantSDNode>(getOperand(hasChain))->getValue();
     return Intrinsic::getName((Intrinsic::ID)IID);
+  }
 
   case ISD::BUILD_VECTOR:   return "BUILD_VECTOR";
   case ISD::TargetConstant: return "TargetConstant";





From lattner at cs.uiuc.edu  Mon Mar 27 10:52:58 2006
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Mon, 27 Mar 2006 10:52:58 -0600
Subject: [llvm-commits] CVS: llvm/lib/Target/X86/X86InstrSSE.td 
Message-ID: <200603271652.KAA02934@zion.cs.uiuc.edu>



Changes in directory llvm/lib/Target/X86:

X86InstrSSE.td updated: 1.33 -> 1.34
---
Log message:

unbreak the build


---
Diffs of the changes:  (+1 -1)

 X86InstrSSE.td |    2 +-
 1 files changed, 1 insertion(+), 1 deletion(-)


Index: llvm/lib/Target/X86/X86InstrSSE.td
diff -u llvm/lib/Target/X86/X86InstrSSE.td:1.33 llvm/lib/Target/X86/X86InstrSSE.td:1.34
--- llvm/lib/Target/X86/X86InstrSSE.td:1.33	Mon Mar 27 01:00:16 2006
+++ llvm/lib/Target/X86/X86InstrSSE.td	Mon Mar 27 10:52:45 2006
@@ -493,7 +493,7 @@
 
 def MOVMSKPSrr : PSI<0x50, MRMSrcReg, (ops R32:$dst, VR128:$src),
                      "movmskps {$src, $dst|$dst, $src}",
-                     [(set R32:$dst, (int_x86_sse_movmskps VR128:$src))]>;
+                     [(set R32:$dst, (int_x86_sse_movmsk_ps VR128:$src))]>;
 def MOVMSKPDrr : PSI<0x50, MRMSrcReg, (ops R32:$dst, VR128:$src),
                      "movmskpd {$src, $dst|$dst, $src}",
                      [(set R32:$dst, (int_x86_sse2_movmskpd VR128:$src))]>;





From jlaskey at apple.com  Mon Mar 27 12:41:18 2006
From: jlaskey at apple.com (Jim Laskey)
Date: Mon, 27 Mar 2006 12:41:18 -0600
Subject: [llvm-commits] CVS: llvm/docs/TestingGuide.html 
Message-ID: <200603271841.MAA03545@zion.cs.uiuc.edu>



Changes in directory llvm/docs:

TestingGuide.html updated: 1.28 -> 1.29
---
Log message:

Add note for Mac OS X developers.


---
Diffs of the changes:  (+4 -1)

 TestingGuide.html |    5 ++++-
 1 files changed, 4 insertions(+), 1 deletion(-)


Index: llvm/docs/TestingGuide.html
diff -u llvm/docs/TestingGuide.html:1.28 llvm/docs/TestingGuide.html:1.29
--- llvm/docs/TestingGuide.html:1.28	Mon Mar 13 23:39:39 2006
+++ llvm/docs/TestingGuide.html	Mon Mar 27 12:41:06 2006
@@ -88,6 +88,9 @@
 filenames themselves on the <tt>configure</tt> line.</li>
 </ul></dd>
 </dl>
+
+<p>Mac OS X developers can simplify installation of Expect and tcl by using
+fink.  <tt>fink install expect</tt> will install both.</p>
 </div>
 
 <!--=========================================================================-->
@@ -522,7 +525,7 @@
 
   John T. Criswell, Reid Spencer, and Tanya Lattner<br>
   <a href="http://llvm.org">The LLVM Compiler Infrastructure</a><br/>
-  Last modified: $Date: 2006/03/14 05:39:39 $
+  Last modified: $Date: 2006/03/27 18:41:06 $
 </address>
 </body>
 </html>





From jlaskey at apple.com  Mon Mar 27 13:09:57 2006
From: jlaskey at apple.com (Jim Laskey)
Date: Mon, 27 Mar 2006 13:09:57 -0600
Subject: [llvm-commits] CVS: llvm/docs/TestingGuide.html 
Message-ID: <200603271909.NAA05461@zion.cs.uiuc.edu>



Changes in directory llvm/docs:

TestingGuide.html updated: 1.29 -> 1.30
---
Log message:

Adding other platforms.


---
Diffs of the changes:  (+5 -2)

 TestingGuide.html |    7 +++++--
 1 files changed, 5 insertions(+), 2 deletions(-)


Index: llvm/docs/TestingGuide.html
diff -u llvm/docs/TestingGuide.html:1.29 llvm/docs/TestingGuide.html:1.30
--- llvm/docs/TestingGuide.html:1.29	Mon Mar 27 12:41:06 2006
+++ llvm/docs/TestingGuide.html	Mon Mar 27 13:09:44 2006
@@ -90,7 +90,10 @@
 </dl>
 
 <p>Mac OS X developers can simplify installation of Expect and tcl by using
-fink.  <tt>fink install expect</tt> will install both.</p>
+fink.  <tt>fink install expect</tt> will install both. Alternatively, users not
+using Mac OS X an use <tt>sudo port install expect</tt> to install Expect and
+tcl.</p>
+
 </div>
 
 <!--=========================================================================-->
@@ -525,7 +528,7 @@
 
   John T. Criswell, Reid Spencer, and Tanya Lattner<br>
   <a href="http://llvm.org">The LLVM Compiler Infrastructure</a><br/>
-  Last modified: $Date: 2006/03/27 18:41:06 $
+  Last modified: $Date: 2006/03/27 19:09:44 $
 </address>
 </body>
 </html>





From jlaskey at apple.com  Mon Mar 27 13:33:48 2006
From: jlaskey at apple.com (Jim Laskey)
Date: Mon, 27 Mar 2006 13:33:48 -0600
Subject: [llvm-commits] CVS: llvm/docs/TestingGuide.html 
Message-ID: <200603271933.NAA12226@zion.cs.uiuc.edu>



Changes in directory llvm/docs:

TestingGuide.html updated: 1.30 -> 1.31
---
Log message:

Clarity.


---
Diffs of the changes:  (+5 -5)

 TestingGuide.html |   10 +++++-----
 1 files changed, 5 insertions(+), 5 deletions(-)


Index: llvm/docs/TestingGuide.html
diff -u llvm/docs/TestingGuide.html:1.30 llvm/docs/TestingGuide.html:1.31
--- llvm/docs/TestingGuide.html:1.30	Mon Mar 27 13:09:44 2006
+++ llvm/docs/TestingGuide.html	Mon Mar 27 13:33:35 2006
@@ -89,10 +89,10 @@
 </ul></dd>
 </dl>
 
-<p>Mac OS X developers can simplify installation of Expect and tcl by using
-fink.  <tt>fink install expect</tt> will install both. Alternatively, users not
-using Mac OS X an use <tt>sudo port install expect</tt> to install Expect and
-tcl.</p>
+<p>Darwin (Mac OS X) developers can simplify the installation of Expect and tcl
+by using fink.  <tt>fink install expect</tt> will install both. Alternatively,
+users not using Darwin an use <tt>sudo port install expect</tt> to install
+Expect and tcl.</p>
 
 </div>
 
@@ -528,7 +528,7 @@
 
   John T. Criswell, Reid Spencer, and Tanya Lattner<br>
   <a href="http://llvm.org">The LLVM Compiler Infrastructure</a><br/>
-  Last modified: $Date: 2006/03/27 19:09:44 $
+  Last modified: $Date: 2006/03/27 19:33:35 $
 </address>
 </body>
 </html>





From jlaskey at apple.com  Mon Mar 27 13:43:20 2006
From: jlaskey at apple.com (Jim Laskey)
Date: Mon, 27 Mar 2006 13:43:20 -0600
Subject: [llvm-commits] CVS: llvm/docs/TestingGuide.html 
Message-ID: <200603271943.NAA16576@zion.cs.uiuc.edu>



Changes in directory llvm/docs:

TestingGuide.html updated: 1.31 -> 1.32
---
Log message:

Typo.


---
Diffs of the changes:  (+2 -2)

 TestingGuide.html |    4 ++--
 1 files changed, 2 insertions(+), 2 deletions(-)


Index: llvm/docs/TestingGuide.html
diff -u llvm/docs/TestingGuide.html:1.31 llvm/docs/TestingGuide.html:1.32
--- llvm/docs/TestingGuide.html:1.31	Mon Mar 27 13:33:35 2006
+++ llvm/docs/TestingGuide.html	Mon Mar 27 13:43:08 2006
@@ -91,7 +91,7 @@
 
 <p>Darwin (Mac OS X) developers can simplify the installation of Expect and tcl
 by using fink.  <tt>fink install expect</tt> will install both. Alternatively,
-users not using Darwin an use <tt>sudo port install expect</tt> to install
+users not using Darwin can use <tt>sudo port install expect</tt> to install
 Expect and tcl.</p>
 
 </div>
@@ -528,7 +528,7 @@
 
   John T. Criswell, Reid Spencer, and Tanya Lattner<br>
   <a href="http://llvm.org">The LLVM Compiler Infrastructure</a><br/>
-  Last modified: $Date: 2006/03/27 19:33:35 $
+  Last modified: $Date: 2006/03/27 19:43:08 $
 </address>
 </body>
 </html>





From jlaskey at apple.com  Mon Mar 27 13:46:51 2006
From: jlaskey at apple.com (Jim Laskey)
Date: Mon, 27 Mar 2006 13:46:51 -0600
Subject: [llvm-commits] CVS: llvm/docs/TestingGuide.html 
Message-ID: <200603271946.NAA18483@zion.cs.uiuc.edu>



Changes in directory llvm/docs:

TestingGuide.html updated: 1.32 -> 1.33
---
Log message:

Misunderstanding.


---
Diffs of the changes:  (+3 -3)

 TestingGuide.html |    6 +++---
 1 files changed, 3 insertions(+), 3 deletions(-)


Index: llvm/docs/TestingGuide.html
diff -u llvm/docs/TestingGuide.html:1.32 llvm/docs/TestingGuide.html:1.33
--- llvm/docs/TestingGuide.html:1.32	Mon Mar 27 13:43:08 2006
+++ llvm/docs/TestingGuide.html	Mon Mar 27 13:46:38 2006
@@ -91,8 +91,8 @@
 
 <p>Darwin (Mac OS X) developers can simplify the installation of Expect and tcl
 by using fink.  <tt>fink install expect</tt> will install both. Alternatively,
-users not using Darwin can use <tt>sudo port install expect</tt> to install
-Expect and tcl.</p>
+Darwinports users can use <tt>sudo port install expect</tt> to install Expect
+and tcl.</p>
 
 </div>
 
@@ -528,7 +528,7 @@
 
   John T. Criswell, Reid Spencer, and Tanya Lattner<br>
   <a href="http://llvm.org">The LLVM Compiler Infrastructure</a><br/>
-  Last modified: $Date: 2006/03/27 19:43:08 $
+  Last modified: $Date: 2006/03/27 19:46:38 $
 </address>
 </body>
 </html>





From jlaskey at apple.com  Mon Mar 27 14:19:01 2006
From: jlaskey at apple.com (Jim Laskey)
Date: Mon, 27 Mar 2006 14:19:01 -0600
Subject: [llvm-commits] CVS: llvm/lib/Target/Alpha/AlphaRegisterInfo.cpp 
Message-ID: <200603272019.OAA25018@zion.cs.uiuc.edu>



Changes in directory llvm/lib/Target/Alpha:

AlphaRegisterInfo.cpp updated: 1.37 -> 1.38
---
Log message:

Translate llvm target registers to dwarf register numbers properly.


---
Diffs of the changes:  (+1 -1)

 AlphaRegisterInfo.cpp |    2 +-
 1 files changed, 1 insertion(+), 1 deletion(-)


Index: llvm/lib/Target/Alpha/AlphaRegisterInfo.cpp
diff -u llvm/lib/Target/Alpha/AlphaRegisterInfo.cpp:1.37 llvm/lib/Target/Alpha/AlphaRegisterInfo.cpp:1.38
--- llvm/lib/Target/Alpha/AlphaRegisterInfo.cpp:1.37	Thu Mar 23 12:12:57 2006
+++ llvm/lib/Target/Alpha/AlphaRegisterInfo.cpp	Mon Mar 27 14:18:45 2006
@@ -362,7 +362,7 @@
   
   // FIXME - Needs to handle register variables.
   // FIXME - Faking that llvm number is same as gcc numbering.
-  ML.set((FP ? Alpha::R15 : Alpha::R30) - Alpha::R0,
+  ML.set(getDwarfRegNum(FP ? Alpha::R15 : Alpha::R30),
          MFI->getObjectOffset(Index) + MFI->getStackSize());
 }
 





From jlaskey at apple.com  Mon Mar 27 14:19:01 2006
From: jlaskey at apple.com (Jim Laskey)
Date: Mon, 27 Mar 2006 14:19:01 -0600
Subject: [llvm-commits] CVS: llvm/lib/Target/X86/X86RegisterInfo.cpp 
Message-ID: <200603272019.OAA25026@zion.cs.uiuc.edu>



Changes in directory llvm/lib/Target/X86:

X86RegisterInfo.cpp updated: 1.131 -> 1.132
---
Log message:

Translate llvm target registers to dwarf register numbers properly.


---
Diffs of the changes:  (+1 -1)

 X86RegisterInfo.cpp |    2 +-
 1 files changed, 1 insertion(+), 1 deletion(-)


Index: llvm/lib/Target/X86/X86RegisterInfo.cpp
diff -u llvm/lib/Target/X86/X86RegisterInfo.cpp:1.131 llvm/lib/Target/X86/X86RegisterInfo.cpp:1.132
--- llvm/lib/Target/X86/X86RegisterInfo.cpp:1.131	Thu Mar 23 12:12:57 2006
+++ llvm/lib/Target/X86/X86RegisterInfo.cpp	Mon Mar 27 14:18:45 2006
@@ -693,7 +693,7 @@
   
   // FIXME - Needs to handle register variables.
   // FIXME - Hardcoding gcc numbering.
-  ML.set(FP ? 6 : 7,
+  ML.set(getDwarfRegNum(FP ? X86::EBP : X86::ESP),
          MFI->getObjectOffset(Index) + MFI->getStackSize());
 }
 





From jlaskey at apple.com  Mon Mar 27 14:19:01 2006
From: jlaskey at apple.com (Jim Laskey)
Date: Mon, 27 Mar 2006 14:19:01 -0600
Subject: [llvm-commits] CVS: llvm/lib/Target/IA64/IA64RegisterInfo.cpp 
Message-ID: <200603272019.OAA25036@zion.cs.uiuc.edu>



Changes in directory llvm/lib/Target/IA64:

IA64RegisterInfo.cpp updated: 1.14 -> 1.15
---
Log message:

Translate llvm target registers to dwarf register numbers properly.


---
Diffs of the changes:  (+1 -1)

 IA64RegisterInfo.cpp |    2 +-
 1 files changed, 1 insertion(+), 1 deletion(-)


Index: llvm/lib/Target/IA64/IA64RegisterInfo.cpp
diff -u llvm/lib/Target/IA64/IA64RegisterInfo.cpp:1.14 llvm/lib/Target/IA64/IA64RegisterInfo.cpp:1.15
--- llvm/lib/Target/IA64/IA64RegisterInfo.cpp:1.14	Thu Mar 23 12:12:57 2006
+++ llvm/lib/Target/IA64/IA64RegisterInfo.cpp	Mon Mar 27 14:18:45 2006
@@ -337,7 +337,7 @@
   
   // FIXME - Needs to handle register variables.
   // FIXME - Faking that llvm number is same as gcc numbering.
-  ML.set((FP ? IA64::r5 : IA64::r12) - IA64::r0,
+  ML.set(getDwarfRegNum(FP ? IA64::r5 : IA64::r12),
          MFI->getObjectOffset(Index) + MFI->getStackSize());
 }
 





From jlaskey at apple.com  Mon Mar 27 14:19:02 2006
From: jlaskey at apple.com (Jim Laskey)
Date: Mon, 27 Mar 2006 14:19:02 -0600
Subject: [llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp 
Message-ID: <200603272019.OAA25055@zion.cs.uiuc.edu>



Changes in directory llvm/lib/Target/PowerPC:

PPCRegisterInfo.cpp updated: 1.50 -> 1.51
---
Log message:

Translate llvm target registers to dwarf register numbers properly.


---
Diffs of the changes:  (+1 -1)

 PPCRegisterInfo.cpp |    2 +-
 1 files changed, 1 insertion(+), 1 deletion(-)


Index: llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
diff -u llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp:1.50 llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp:1.51
--- llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp:1.50	Thu Mar 23 12:12:57 2006
+++ llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp	Mon Mar 27 14:18:45 2006
@@ -454,7 +454,7 @@
   
   // FIXME - Needs to handle register variables.
   // FIXME - Faking that llvm number is same as gcc numbering.
-  ML.set((FP ? PPC::R31 : PPC::R1) - PPC::R0,
+  ML.set(getDwarfRegNum(FP ? PPC::R31 : PPC::R1),
          MFI->getObjectOffset(Index) + MFI->getStackSize());
 }
 





From jlaskey at apple.com  Mon Mar 27 14:19:01 2006
From: jlaskey at apple.com (Jim Laskey)
Date: Mon, 27 Mar 2006 14:19:01 -0600
Subject: [llvm-commits] CVS: llvm/lib/Target/Sparc/SparcRegisterInfo.cpp 
Message-ID: <200603272019.OAA25032@zion.cs.uiuc.edu>



Changes in directory llvm/lib/Target/Sparc:

SparcRegisterInfo.cpp updated: 1.38 -> 1.39
---
Log message:

Translate llvm target registers to dwarf register numbers properly.


---
Diffs of the changes:  (+1 -1)

 SparcRegisterInfo.cpp |    2 +-
 1 files changed, 1 insertion(+), 1 deletion(-)


Index: llvm/lib/Target/Sparc/SparcRegisterInfo.cpp
diff -u llvm/lib/Target/Sparc/SparcRegisterInfo.cpp:1.38 llvm/lib/Target/Sparc/SparcRegisterInfo.cpp:1.39
--- llvm/lib/Target/Sparc/SparcRegisterInfo.cpp:1.38	Thu Mar 23 12:12:57 2006
+++ llvm/lib/Target/Sparc/SparcRegisterInfo.cpp	Mon Mar 27 14:18:45 2006
@@ -207,7 +207,7 @@
   
   // FIXME - Needs to handle register variables.
   // FIXME - Faking that llvm number is same as gcc numbering.
-  ML.set(SP::G1 - SP::G0,
+  ML.set(getDwarfRegNum(SP::G1),
          MFI->getObjectOffset(Index) + MFI->getStackSize());
 }
 





From lattner at cs.uiuc.edu  Mon Mar 27 14:28:42 2006
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Mon, 27 Mar 2006 14:28:42 -0600
Subject: [llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp 
Message-ID: <200603272028.OAA26683@zion.cs.uiuc.edu>



Changes in directory llvm/lib/CodeGen/SelectionDAG:

LegalizeDAG.cpp updated: 1.339 -> 1.340
---
Log message:

Fix legalization of intrinsics with chain and result values


---
Diffs of the changes:  (+13 -2)

 LegalizeDAG.cpp |   15 +++++++++++++--
 1 files changed, 13 insertions(+), 2 deletions(-)


Index: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.339 llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.340
--- llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.339	Sun Mar 26 03:12:51 2006
+++ llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp	Mon Mar 27 14:28:29 2006
@@ -564,8 +564,19 @@
         TargetLowering::Custom) {
       Tmp3 = TLI.LowerOperation(Result, DAG);
       if (Tmp3.Val) Result = Tmp3;
-    }      
-    break;
+    }
+
+    if (Result.Val->getNumValues() == 1) break;
+
+    // Must have return value and chain result.
+    assert(Result.Val->getNumValues() == 2 &&
+           "Cannot return more than two values!");
+
+    // Since loads produce two values, make sure to remember that we 
+    // legalized both of them.
+    AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0));
+    AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1));
+    return Result.getValue(Op.ResNo);
   }    
 
   case ISD::LOCATION:





From lattner at cs.uiuc.edu  Mon Mar 27 15:36:15 2006
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Mon, 27 Mar 2006 15:36:15 -0600
Subject: [llvm-commits] 
	CVS: llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
Message-ID: <200603272136.PAA02175@zion.cs.uiuc.edu>



Changes in directory llvm/lib/CodeGen/SelectionDAG:

SelectionDAGISel.cpp updated: 1.207 -> 1.208
---
Log message:

Disable dbg_declare, it currently breaks the CFE build


---
Diffs of the changes:  (+1 -0)

 SelectionDAGISel.cpp |    1 +
 1 files changed, 1 insertion(+)


Index: llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.207 llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.208
--- llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.207	Sun Mar 26 19:32:24 2006
+++ llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp	Mon Mar 27 15:36:03 2006
@@ -1382,6 +1382,7 @@
     return 0;
   }
   case Intrinsic::dbg_declare: {
+    return 0;
     MachineDebugInfo *DebugInfo = DAG.getMachineDebugInfo();
     DbgDeclareInst &DI = cast<DbgDeclareInst>(I);
     if (DebugInfo && DebugInfo->Verify(DI.getVariable())) {





From lattner at cs.uiuc.edu  Mon Mar 27 16:05:47 2006
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Mon, 27 Mar 2006 16:05:47 -0600
Subject: [llvm-commits] CVS: llvm/include/llvm/IntrinsicsPowerPC.td 
Message-ID: <200603272205.QAA06324@zion.cs.uiuc.edu>



Changes in directory llvm/include/llvm:

IntrinsicsPowerPC.td updated: 1.2 -> 1.3
---
Log message:

add some more intrinsics.


---
Diffs of the changes:  (+109 -21)

 IntrinsicsPowerPC.td |  130 ++++++++++++++++++++++++++++++++++++++++++---------
 1 files changed, 109 insertions(+), 21 deletions(-)


Index: llvm/include/llvm/IntrinsicsPowerPC.td
diff -u llvm/include/llvm/IntrinsicsPowerPC.td:1.2 llvm/include/llvm/IntrinsicsPowerPC.td:1.3
--- llvm/include/llvm/IntrinsicsPowerPC.td:1.2	Sun Mar 26 01:50:25 2006
+++ llvm/include/llvm/IntrinsicsPowerPC.td	Mon Mar 27 16:05:34 2006
@@ -12,32 +12,36 @@
 //===----------------------------------------------------------------------===//
 
 let TargetPrefix = "ppc" in {  // All intrinsics start with "llvm.ppc.".
+  // Loads.
   def int_ppc_altivec_lvx : GCCBuiltin<"__builtin_altivec_lvx">,
               Intrinsic<[llvm_v4i32_ty, llvm_int_ty, llvm_ptr_ty],
                         [IntrReadMem]>;
+  def int_ppc_altivec_lvebx : GCCBuiltin<"__builtin_altivec_lvebx">,
+              Intrinsic<[llvm_v16i8_ty, llvm_int_ty, llvm_ptr_ty],
+                        [IntrReadMem]>;
+  def int_ppc_altivec_lvehx : GCCBuiltin<"__builtin_altivec_lvehx">,
+              Intrinsic<[llvm_v8i16_ty, llvm_int_ty, llvm_ptr_ty],
+                        [IntrReadMem]>;
+  def int_ppc_altivec_lvewx : GCCBuiltin<"__builtin_altivec_lvewx">,
+              Intrinsic<[llvm_v4i32_ty, llvm_int_ty, llvm_ptr_ty],
+                        [IntrReadMem]>;
+
+  // Stores.
   def int_ppc_altivec_stvx : GCCBuiltin<"__builtin_altivec_stvx">,
               Intrinsic<[llvm_void_ty, llvm_v4i32_ty, llvm_int_ty, llvm_ptr_ty],
                         [IntrWriteMem]>;
-                            
-  def int_ppc_altivec_vmaddfp : GCCBuiltin<"__builtin_altivec_vmaddfp">,
-              Intrinsic<[llvm_v4f32_ty, llvm_v4f32_ty,
-                         llvm_v4f32_ty, llvm_v4f32_ty], [InstrNoMem]>;
-  def int_ppc_altivec_vnmsubfp : GCCBuiltin<"__builtin_altivec_vnmsubfp">,
-              Intrinsic<[llvm_v4f32_ty, llvm_v4f32_ty,
-                         llvm_v4f32_ty, llvm_v4f32_ty], [InstrNoMem]>;
-
-  def int_ppc_altivec_vaddcuw : GCCBuiltin<"__builtin_altivec_vaddcuw">,
-              Intrinsic<[llvm_v4i32_ty, llvm_v4i32_ty, llvm_v4i32_ty],
-                        [InstrNoMem]>;
-  def int_ppc_altivec_vsubcuw : GCCBuiltin<"__builtin_altivec_vsubcuw">,
-              Intrinsic<[llvm_v4i32_ty, llvm_v4i32_ty, llvm_v4i32_ty],
-                        [InstrNoMem]>;
-  def int_ppc_altivec_vsel : GCCBuiltin<"__builtin_altivec_vsel_4si">,
-              Intrinsic<[llvm_v4i32_ty, llvm_v4i32_ty, 
-                         llvm_v4i32_ty, llvm_v4i32_ty], [InstrNoMem]>;
-  def int_ppc_altivec_vsldoi : GCCBuiltin<"__builtin_altivec_vsldoi_4si">,
-              Intrinsic<[llvm_v4i32_ty, llvm_v4i32_ty, 
-                         llvm_v4i32_ty, llvm_int_ty], [InstrNoMem]>;
+  def int_ppc_altivec_stvxl : GCCBuiltin<"__builtin_altivec_stvxl">,
+              Intrinsic<[llvm_void_ty, llvm_v4i32_ty, llvm_int_ty, llvm_ptr_ty],
+                        [IntrWriteMem]>;
+  def int_ppc_altivec_stevbx : GCCBuiltin<"__builtin_altivec_stevbx">,
+              Intrinsic<[llvm_void_ty, llvm_v16i8_ty, llvm_int_ty, llvm_ptr_ty],
+                        [IntrWriteMem]>;
+  def int_ppc_altivec_stevhx : GCCBuiltin<"__builtin_altivec_stevhx">,
+              Intrinsic<[llvm_void_ty, llvm_v8i16_ty, llvm_int_ty, llvm_ptr_ty],
+                        [IntrWriteMem]>;
+  def int_ppc_altivec_stevwx : GCCBuiltin<"__builtin_altivec_stevwx">,
+              Intrinsic<[llvm_void_ty, llvm_v4i32_ty, llvm_int_ty, llvm_ptr_ty],
+                        [IntrWriteMem]>;
 
   // Comparisons setting a vector.
   def int_ppc_altivec_vcmpbfp : GCCBuiltin<"__builtin_altivec_vcmpbfp">,
@@ -147,6 +151,13 @@
               Intrinsic<[llvm_v4i32_ty, llvm_v4i32_ty, llvm_v4i32_ty],
                         [InstrNoMem]>;
 
+  def int_ppc_altivec_vmaddfp : GCCBuiltin<"__builtin_altivec_vmaddfp">,
+              Intrinsic<[llvm_v4f32_ty, llvm_v4f32_ty,
+                         llvm_v4f32_ty, llvm_v4f32_ty], [InstrNoMem]>;
+  def int_ppc_altivec_vaddcuw : GCCBuiltin<"__builtin_altivec_vaddcuw">,
+              Intrinsic<[llvm_v4i32_ty, llvm_v4i32_ty, llvm_v4i32_ty],
+                        [InstrNoMem]>;
+
   def int_ppc_altivec_vsububs : GCCBuiltin<"__builtin_altivec_vsububs">,
               Intrinsic<[llvm_v16i8_ty, llvm_v16i8_ty, llvm_v16i8_ty],
                         [InstrNoMem]>;
@@ -166,7 +177,31 @@
               Intrinsic<[llvm_v4i32_ty, llvm_v4i32_ty, llvm_v4i32_ty],
                         [InstrNoMem]>;
 
-                        
+  def int_ppc_altivec_vnmsubfp : GCCBuiltin<"__builtin_altivec_vnmsubfp">,
+              Intrinsic<[llvm_v4f32_ty, llvm_v4f32_ty,
+                         llvm_v4f32_ty, llvm_v4f32_ty], [InstrNoMem]>;
+  def int_ppc_altivec_vsubcuw : GCCBuiltin<"__builtin_altivec_vsubcuw">,
+              Intrinsic<[llvm_v4i32_ty, llvm_v4i32_ty, llvm_v4i32_ty],
+                        [InstrNoMem]>;
+
+  // Vector Sum Instructions.
+  def int_ppc_altivec_vsumsws : GCCBuiltin<"__builtin_altivec_vsumsws">,
+            Intrinsic<[llvm_v4i32_ty, llvm_v4i32_ty, llvm_v4i32_ty],
+                      [InstrNoMem]>;
+  def int_ppc_altivec_vsum2sws : GCCBuiltin<"__builtin_altivec_vsum2sws">,
+            Intrinsic<[llvm_v4i32_ty, llvm_v4i32_ty, llvm_v4i32_ty],
+                      [InstrNoMem]>;
+  def int_ppc_altivec_vsum4sbs : GCCBuiltin<"__builtin_altivec_vsum4sbs">,
+            Intrinsic<[llvm_v4i32_ty, llvm_v16i8_ty, llvm_v4i32_ty],
+                      [InstrNoMem]>;
+  def int_ppc_altivec_vsum4shs : GCCBuiltin<"__builtin_altivec_vsum4shs">,
+            Intrinsic<[llvm_v4i32_ty, llvm_v8i16_ty, llvm_v4i32_ty],
+                      [InstrNoMem]>;
+  def int_ppc_altivec_vsum4ubs : GCCBuiltin<"__builtin_altivec_vsum4ubs">,
+            Intrinsic<[llvm_v4i32_ty, llvm_v16i8_ty, llvm_v4i32_ty],
+                      [InstrNoMem]>;
+
+
   // FP to integer conversion.
   def int_ppc_altivec_vcfsx : GCCBuiltin<"__builtin_altivec_vcfsx">,
               Intrinsic<[llvm_v4f32_ty, llvm_v4i32_ty, llvm_int_ty],
@@ -175,6 +210,59 @@
               Intrinsic<[llvm_v4f32_ty, llvm_v4i32_ty, llvm_int_ty],
                         [InstrNoMem]>;
 
+  // Left Shifts.
+  def int_ppc_altivec_vsldoi : GCCBuiltin<"__builtin_altivec_vsldoi_4si">,
+              Intrinsic<[llvm_v4i32_ty, llvm_v4i32_ty, 
+                         llvm_v4i32_ty, llvm_int_ty], [InstrNoMem]>;
+  def int_ppc_altivec_vslo : GCCBuiltin<"__builtin_altivec_vslo">,
+              Intrinsic<[llvm_v4i32_ty, llvm_v4i32_ty, llvm_v4i32_ty],
+                        [InstrNoMem]>;
+
+  def int_ppc_altivec_vslb : GCCBuiltin<"__builtin_altivec_vslb">,
+              Intrinsic<[llvm_v16i8_ty, llvm_v16i8_ty, llvm_v16i8_ty],
+                        [InstrNoMem]>;
+  def int_ppc_altivec_vslh : GCCBuiltin<"__builtin_altivec_vslh">,
+              Intrinsic<[llvm_v8i16_ty, llvm_v8i16_ty, llvm_v8i16_ty],
+                        [InstrNoMem]>;
+  def int_ppc_altivec_vslw : GCCBuiltin<"__builtin_altivec_vslw">,
+              Intrinsic<[llvm_v4i32_ty, llvm_v4i32_ty, llvm_v4i32_ty],
+                        [InstrNoMem]>;
+
+  // Right Shifts.
+  def int_ppc_altivec_vsr : GCCBuiltin<"__builtin_altivec_vsr">,
+              Intrinsic<[llvm_v4i32_ty, llvm_v4i32_ty, llvm_v4i32_ty],
+                        [InstrNoMem]>;
+  def int_ppc_altivec_vsro : GCCBuiltin<"__builtin_altivec_vsro">,
+              Intrinsic<[llvm_v4i32_ty, llvm_v4i32_ty, llvm_v4i32_ty],
+                        [InstrNoMem]>;
+
+  def int_ppc_altivec_vsrb : GCCBuiltin<"__builtin_altivec_vsrb">,
+              Intrinsic<[llvm_v16i8_ty, llvm_v16i8_ty, llvm_v16i8_ty],
+                        [InstrNoMem]>;
+  def int_ppc_altivec_vsrh : GCCBuiltin<"__builtin_altivec_vsrh">,
+              Intrinsic<[llvm_v8i16_ty, llvm_v8i16_ty, llvm_v8i16_ty],
+                        [InstrNoMem]>;
+  def int_ppc_altivec_vsrw : GCCBuiltin<"__builtin_altivec_vsrw">,
+              Intrinsic<[llvm_v4i32_ty, llvm_v4i32_ty, llvm_v4i32_ty],
+                        [InstrNoMem]>;
+  def int_ppc_altivec_vsrab : GCCBuiltin<"__builtin_altivec_vsrab">,
+              Intrinsic<[llvm_v16i8_ty, llvm_v16i8_ty, llvm_v16i8_ty],
+                        [InstrNoMem]>;
+  def int_ppc_altivec_vsrah : GCCBuiltin<"__builtin_altivec_vsrah">,
+              Intrinsic<[llvm_v8i16_ty, llvm_v8i16_ty, llvm_v8i16_ty],
+                        [InstrNoMem]>;
+  def int_ppc_altivec_vsraw : GCCBuiltin<"__builtin_altivec_vsraw">,
+              Intrinsic<[llvm_v4i32_ty, llvm_v4i32_ty, llvm_v4i32_ty],
+                        [InstrNoMem]>;
+
+
+  // Miscellaneous.
+  def int_ppc_altivec_vsel : GCCBuiltin<"__builtin_altivec_vsel_4si">,
+              Intrinsic<[llvm_v4i32_ty, llvm_v4i32_ty, 
+                         llvm_v4i32_ty, llvm_v4i32_ty], [InstrNoMem]>;
+
+  def int_ppc_altivec_vrefp : GCCBuiltin<"__builtin_altivec_vrefp">,
+              Intrinsic<[llvm_v4f32_ty, llvm_v4f32_ty], [InstrNoMem]>;
   def int_ppc_altivec_vrsqrtefp : GCCBuiltin<"__builtin_altivec_vrsqrtefp">,
               Intrinsic<[llvm_v4f32_ty, llvm_v4f32_ty], [InstrNoMem]>;
   





From lattner at cs.uiuc.edu  Mon Mar 27 16:07:25 2006
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Mon, 27 Mar 2006 16:07:25 -0600
Subject: [llvm-commits] CVS: llvm/include/llvm/IntrinsicsPowerPC.td 
Message-ID: <200603272207.QAA06768@zion.cs.uiuc.edu>



Changes in directory llvm/include/llvm:

IntrinsicsPowerPC.td updated: 1.3 -> 1.4
---
Log message:

fix spelling :(


---
Diffs of the changes:  (+3 -3)

 IntrinsicsPowerPC.td |    6 +++---
 1 files changed, 3 insertions(+), 3 deletions(-)


Index: llvm/include/llvm/IntrinsicsPowerPC.td
diff -u llvm/include/llvm/IntrinsicsPowerPC.td:1.3 llvm/include/llvm/IntrinsicsPowerPC.td:1.4
--- llvm/include/llvm/IntrinsicsPowerPC.td:1.3	Mon Mar 27 16:05:34 2006
+++ llvm/include/llvm/IntrinsicsPowerPC.td	Mon Mar 27 16:07:12 2006
@@ -33,13 +33,13 @@
   def int_ppc_altivec_stvxl : GCCBuiltin<"__builtin_altivec_stvxl">,
               Intrinsic<[llvm_void_ty, llvm_v4i32_ty, llvm_int_ty, llvm_ptr_ty],
                         [IntrWriteMem]>;
-  def int_ppc_altivec_stevbx : GCCBuiltin<"__builtin_altivec_stevbx">,
+  def int_ppc_altivec_stvebx : GCCBuiltin<"__builtin_altivec_stvebx">,
               Intrinsic<[llvm_void_ty, llvm_v16i8_ty, llvm_int_ty, llvm_ptr_ty],
                         [IntrWriteMem]>;
-  def int_ppc_altivec_stevhx : GCCBuiltin<"__builtin_altivec_stevhx">,
+  def int_ppc_altivec_stvehx : GCCBuiltin<"__builtin_altivec_stvehx">,
               Intrinsic<[llvm_void_ty, llvm_v8i16_ty, llvm_int_ty, llvm_ptr_ty],
                         [IntrWriteMem]>;
-  def int_ppc_altivec_stevwx : GCCBuiltin<"__builtin_altivec_stevwx">,
+  def int_ppc_altivec_stvewx : GCCBuiltin<"__builtin_altivec_stvewx">,
               Intrinsic<[llvm_void_ty, llvm_v4i32_ty, llvm_int_ty, llvm_ptr_ty],
                         [IntrWriteMem]>;
 





From lattner at cs.uiuc.edu  Mon Mar 27 16:21:31 2006
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Mon, 27 Mar 2006 16:21:31 -0600
Subject: [llvm-commits] CVS: llvm/utils/TableGen/DAGISelEmitter.cpp 
Message-ID: <200603272221.QAA07619@zion.cs.uiuc.edu>



Changes in directory llvm/utils/TableGen:

DAGISelEmitter.cpp updated: 1.188 -> 1.189
---
Log message:

Print error messages like this:
tblgen: In STVEBX: Intrinsic 'llvm.ppc.altivec.stvebx' expects 3 operands, not 2 operands!

instead of like this:
tblgen: In STVEBX: Intrinsic 'intrinsic_void expects 3 operands, not 2 operands!



---
Diffs of the changes:  (+1 -1)

 DAGISelEmitter.cpp |    2 +-
 1 files changed, 1 insertion(+), 1 deletion(-)


Index: llvm/utils/TableGen/DAGISelEmitter.cpp
diff -u llvm/utils/TableGen/DAGISelEmitter.cpp:1.188 llvm/utils/TableGen/DAGISelEmitter.cpp:1.189
--- llvm/utils/TableGen/DAGISelEmitter.cpp:1.188	Sat Mar 25 16:12:44 2006
+++ llvm/utils/TableGen/DAGISelEmitter.cpp	Mon Mar 27 16:21:18 2006
@@ -649,7 +649,7 @@
     MadeChange = UpdateNodeType(Int.ArgVTs[0], TP);
     
     if (getNumChildren() != Int.ArgVTs.size())
-      TP.error("Intrinsic '" + getOperator()->getName() + " expects " +
+      TP.error("Intrinsic '" + Int.Name + "' expects " +
                utostr(Int.ArgVTs.size()-1) + " operands, not " +
                utostr(getNumChildren()-1) + " operands!");
 





From lattner at cs.uiuc.edu  Mon Mar 27 16:38:52 2006
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Mon, 27 Mar 2006 16:38:52 -0600
Subject: [llvm-commits] CVS: llvm/include/llvm/IntrinsicsPowerPC.td 
Message-ID: <200603272238.QAA10432@zion.cs.uiuc.edu>



Changes in directory llvm/include/llvm:

IntrinsicsPowerPC.td updated: 1.4 -> 1.5
---
Log message:

Divirge from the GCC specification of the load/store intrinsics: only take
one pointer operand, instead of a pointer and an offset.  The FE will lower
to this canonicalized form.


---
Diffs of the changes:  (+9 -13)

 IntrinsicsPowerPC.td |   22 +++++++++-------------
 1 files changed, 9 insertions(+), 13 deletions(-)


Index: llvm/include/llvm/IntrinsicsPowerPC.td
diff -u llvm/include/llvm/IntrinsicsPowerPC.td:1.4 llvm/include/llvm/IntrinsicsPowerPC.td:1.5
--- llvm/include/llvm/IntrinsicsPowerPC.td:1.4	Mon Mar 27 16:07:12 2006
+++ llvm/include/llvm/IntrinsicsPowerPC.td	Mon Mar 27 16:38:39 2006
@@ -14,33 +14,29 @@
 let TargetPrefix = "ppc" in {  // All intrinsics start with "llvm.ppc.".
   // Loads.
   def int_ppc_altivec_lvx : GCCBuiltin<"__builtin_altivec_lvx">,
-              Intrinsic<[llvm_v4i32_ty, llvm_int_ty, llvm_ptr_ty],
-                        [IntrReadMem]>;
+              Intrinsic<[llvm_v4i32_ty, llvm_ptr_ty], [IntrReadMem]>;
   def int_ppc_altivec_lvebx : GCCBuiltin<"__builtin_altivec_lvebx">,
-              Intrinsic<[llvm_v16i8_ty, llvm_int_ty, llvm_ptr_ty],
-                        [IntrReadMem]>;
+              Intrinsic<[llvm_v16i8_ty, llvm_ptr_ty], [IntrReadMem]>;
   def int_ppc_altivec_lvehx : GCCBuiltin<"__builtin_altivec_lvehx">,
-              Intrinsic<[llvm_v8i16_ty, llvm_int_ty, llvm_ptr_ty],
-                        [IntrReadMem]>;
+              Intrinsic<[llvm_v8i16_ty, llvm_ptr_ty], [IntrReadMem]>;
   def int_ppc_altivec_lvewx : GCCBuiltin<"__builtin_altivec_lvewx">,
-              Intrinsic<[llvm_v4i32_ty, llvm_int_ty, llvm_ptr_ty],
-                        [IntrReadMem]>;
+              Intrinsic<[llvm_v4i32_ty, llvm_ptr_ty], [IntrReadMem]>;
 
   // Stores.
   def int_ppc_altivec_stvx : GCCBuiltin<"__builtin_altivec_stvx">,
-              Intrinsic<[llvm_void_ty, llvm_v4i32_ty, llvm_int_ty, llvm_ptr_ty],
+              Intrinsic<[llvm_void_ty, llvm_v4i32_ty, llvm_ptr_ty],
                         [IntrWriteMem]>;
   def int_ppc_altivec_stvxl : GCCBuiltin<"__builtin_altivec_stvxl">,
-              Intrinsic<[llvm_void_ty, llvm_v4i32_ty, llvm_int_ty, llvm_ptr_ty],
+              Intrinsic<[llvm_void_ty, llvm_v4i32_ty, llvm_ptr_ty],
                         [IntrWriteMem]>;
   def int_ppc_altivec_stvebx : GCCBuiltin<"__builtin_altivec_stvebx">,
-              Intrinsic<[llvm_void_ty, llvm_v16i8_ty, llvm_int_ty, llvm_ptr_ty],
+              Intrinsic<[llvm_void_ty, llvm_v16i8_ty, llvm_ptr_ty],
                         [IntrWriteMem]>;
   def int_ppc_altivec_stvehx : GCCBuiltin<"__builtin_altivec_stvehx">,
-              Intrinsic<[llvm_void_ty, llvm_v8i16_ty, llvm_int_ty, llvm_ptr_ty],
+              Intrinsic<[llvm_void_ty, llvm_v8i16_ty, llvm_ptr_ty],
                         [IntrWriteMem]>;
   def int_ppc_altivec_stvewx : GCCBuiltin<"__builtin_altivec_stvewx">,
-              Intrinsic<[llvm_void_ty, llvm_v4i32_ty, llvm_int_ty, llvm_ptr_ty],
+              Intrinsic<[llvm_void_ty, llvm_v4i32_ty, llvm_ptr_ty],
                         [IntrWriteMem]>;
 
   // Comparisons setting a vector.





From lattner at cs.uiuc.edu  Mon Mar 27 16:48:12 2006
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Mon, 27 Mar 2006 16:48:12 -0600
Subject: [llvm-commits] CVS: llvm/include/llvm/CodeGen/ValueTypes.h
	ValueTypes.td 
Message-ID: <200603272248.QAA10834@zion.cs.uiuc.edu>



Changes in directory llvm/include/llvm/CodeGen:

ValueTypes.h updated: 1.25 -> 1.26
ValueTypes.td updated: 1.1 -> 1.2
---
Log message:

add a new iPTR ValueType for tblgen use


---
Diffs of the changes:  (+9 -1)

 ValueTypes.h  |    6 +++++-
 ValueTypes.td |    4 ++++
 2 files changed, 9 insertions(+), 1 deletion(-)


Index: llvm/include/llvm/CodeGen/ValueTypes.h
diff -u llvm/include/llvm/CodeGen/ValueTypes.h:1.25 llvm/include/llvm/CodeGen/ValueTypes.h:1.26
--- llvm/include/llvm/CodeGen/ValueTypes.h:1.25	Sun Mar 19 18:20:30 2006
+++ llvm/include/llvm/CodeGen/ValueTypes.h	Mon Mar 27 16:48:00 2006
@@ -63,7 +63,11 @@
     FIRST_VECTOR_VALUETYPE = v8i8,
     LAST_VECTOR_VALUETYPE  = v2f64,
 
-    LAST_VALUETYPE =  24    // This always remains at the end of the list.
+    LAST_VALUETYPE =  24,   // This always remains at the end of the list.
+
+    // iPTR - An int value the size of the pointer of the current
+    // target.  This should only be used internal to tblgen!
+    iPTR           = 255
   };
 
   /// MVT::isInteger - Return true if this is a simple integer, or a packed


Index: llvm/include/llvm/CodeGen/ValueTypes.td
diff -u llvm/include/llvm/CodeGen/ValueTypes.td:1.1 llvm/include/llvm/CodeGen/ValueTypes.td:1.2
--- llvm/include/llvm/CodeGen/ValueTypes.td:1.1	Thu Mar  2 19:54:11 2006
+++ llvm/include/llvm/CodeGen/ValueTypes.td	Mon Mar 27 16:48:00 2006
@@ -43,3 +43,7 @@
 def v2f32  : ValueType<64,  21>;   //  2 x f32 vector value
 def v4f32  : ValueType<128, 22>;   //  4 x f32 vector value
 def v2f64  : ValueType<128, 23>;   //  2 x f64 vector value
+
+
+// Pseudo valuetype mapped to the current pointer size.
+def iPTR   : ValueType<0  , 255>;





From lattner at cs.uiuc.edu  Mon Mar 27 16:48:30 2006
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Mon, 27 Mar 2006 16:48:30 -0600
Subject: [llvm-commits] CVS: llvm/utils/TableGen/CodeGenIntrinsics.h
	CodeGenTarget.cpp CodeGenTarget.h 
Message-ID: <200603272248.QAA10850@zion.cs.uiuc.edu>



Changes in directory llvm/utils/TableGen:

CodeGenIntrinsics.h updated: 1.7 -> 1.8
CodeGenTarget.cpp updated: 1.59 -> 1.60
CodeGenTarget.h updated: 1.24 -> 1.25
---
Log message:

Add support for decoding iPTR to the right pointer type.


---
Diffs of the changes:  (+19 -7)

 CodeGenIntrinsics.h |    3 ++-
 CodeGenTarget.cpp   |   20 +++++++++++++++-----
 CodeGenTarget.h     |    3 ++-
 3 files changed, 19 insertions(+), 7 deletions(-)


Index: llvm/utils/TableGen/CodeGenIntrinsics.h
diff -u llvm/utils/TableGen/CodeGenIntrinsics.h:1.7 llvm/utils/TableGen/CodeGenIntrinsics.h:1.8
--- llvm/utils/TableGen/CodeGenIntrinsics.h:1.7	Fri Mar 24 13:49:31 2006
+++ llvm/utils/TableGen/CodeGenIntrinsics.h	Mon Mar 27 16:48:18 2006
@@ -21,6 +21,7 @@
 namespace llvm {
   class Record;
   class RecordKeeper;
+  class CodeGenTarget;
 
   struct CodeGenIntrinsic {
     Record *TheDef;            // The actual record defining this instruction.
@@ -45,7 +46,7 @@
       NoMem, ReadArgMem, ReadMem, WriteArgMem, WriteMem
     } ModRef;
 
-    CodeGenIntrinsic(Record *R);
+    CodeGenIntrinsic(Record *R, CodeGenTarget &CGT);
   };
 
   /// LoadIntrinsics - Read all of the intrinsics defined in the specified


Index: llvm/utils/TableGen/CodeGenTarget.cpp
diff -u llvm/utils/TableGen/CodeGenTarget.cpp:1.59 llvm/utils/TableGen/CodeGenTarget.cpp:1.60
--- llvm/utils/TableGen/CodeGenTarget.cpp:1.59	Fri Mar 24 14:25:01 2006
+++ llvm/utils/TableGen/CodeGenTarget.cpp	Mon Mar 27 16:48:18 2006
@@ -29,8 +29,13 @@
 
 /// getValueType - Return the MCV::ValueType that the specified TableGen record
 /// corresponds to.
-MVT::ValueType llvm::getValueType(Record *Rec) {
-  return (MVT::ValueType)Rec->getValueAsInt("Value");
+MVT::ValueType llvm::getValueType(Record *Rec, const CodeGenTarget *CGT) {
+  MVT::ValueType VT = (MVT::ValueType)Rec->getValueAsInt("Value");
+  if (VT == MVT::iPTR) {
+    assert(CGT && "Use a pointer type in a place that isn't supported yet!");
+    VT = CGT->getPointerType();
+  }
+  return VT;
 }
 
 std::string llvm::getName(MVT::ValueType T) {
@@ -355,10 +360,15 @@
 
 std::vector<CodeGenIntrinsic> llvm::LoadIntrinsics(const RecordKeeper &RC) {
   std::vector<Record*> I = RC.getAllDerivedDefinitions("Intrinsic");
-  return std::vector<CodeGenIntrinsic>(I.begin(), I.end());
+  
+  std::vector<CodeGenIntrinsic> Result;
+  CodeGenTarget CGT;
+  for (unsigned i = 0, e = I.size(); i != e; ++i)
+    Result.push_back(CodeGenIntrinsic(I[i], CGT));
+  return Result;
 }
 
-CodeGenIntrinsic::CodeGenIntrinsic(Record *R) {
+CodeGenIntrinsic::CodeGenIntrinsic(Record *R, CodeGenTarget &CGT) {
   TheDef = R;
   std::string DefName = R->getName();
   ModRef = WriteMem;
@@ -405,7 +415,7 @@
     assert(TyEl->isSubClassOf("LLVMType") && "Expected a type!");
     ArgTypes.push_back(TyEl->getValueAsString("TypeVal"));
     
-    ArgVTs.push_back(getValueType(TyEl->getValueAsDef("VT")));
+    ArgVTs.push_back(getValueType(TyEl->getValueAsDef("VT"), &CGT));
     ArgTypeDefs.push_back(TyEl);
   }
   if (ArgTypes.size() == 0)


Index: llvm/utils/TableGen/CodeGenTarget.h
diff -u llvm/utils/TableGen/CodeGenTarget.h:1.24 llvm/utils/TableGen/CodeGenTarget.h:1.25
--- llvm/utils/TableGen/CodeGenTarget.h:1.24	Thu Jan 26 19:45:06 2006
+++ llvm/utils/TableGen/CodeGenTarget.h	Mon Mar 27 16:48:18 2006
@@ -27,10 +27,11 @@
 class Record;
 class RecordKeeper;
 struct CodeGenRegister;
+class CodeGenTarget;
 
 /// getValueType - Return the MVT::ValueType that the specified TableGen record
 /// corresponds to.
-MVT::ValueType getValueType(Record *Rec);
+MVT::ValueType getValueType(Record *Rec, const CodeGenTarget *CGT = 0);
 
 std::ostream &operator<<(std::ostream &OS, MVT::ValueType T);
 std::string getName(MVT::ValueType T);





From lattner at cs.uiuc.edu  Mon Mar 27 16:49:19 2006
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Mon, 27 Mar 2006 16:49:19 -0600
Subject: [llvm-commits] CVS: llvm/include/llvm/Use.h 
Message-ID: <200603272249.QAA10913@zion.cs.uiuc.edu>



Changes in directory llvm/include/llvm:

Use.h updated: 1.12 -> 1.13
---
Log message:

Add some missing template specializations for autodereferencing User.


---
Diffs of the changes:  (+25 -1)

 Use.h |   26 +++++++++++++++++++++++++-
 1 files changed, 25 insertions(+), 1 deletion(-)


Index: llvm/include/llvm/Use.h
diff -u llvm/include/llvm/Use.h:1.12 llvm/include/llvm/Use.h:1.13
--- llvm/include/llvm/Use.h:1.12	Thu Apr 21 15:11:51 2005
+++ llvm/include/llvm/Use.h	Mon Mar 27 16:49:07 2006
@@ -132,7 +132,7 @@
   }
 
   // Retrieve a reference to the current SCC
-   UserTy *operator*() const {
+  UserTy *operator*() const {
     assert(U && "Cannot increment end iterator!");
     return U->getUser();
   }
@@ -142,6 +142,30 @@
   Use &getUse() const { return *U; }
 };
 
+
+template<> struct simplify_type<value_use_iterator<User> > {
+  typedef User* SimpleType;
+  
+  static SimpleType getSimplifiedValue(const value_use_iterator<User> &Val) {
+    return *Val;
+  }
+};
+
+template<> struct simplify_type<const value_use_iterator<User> >
+ : public simplify_type<value_use_iterator<User> > {};
+
+template<> struct simplify_type<value_use_iterator<const User> > {
+  typedef const User* SimpleType;
+  
+  static SimpleType getSimplifiedValue(const 
+                                       value_use_iterator<const User> &Val) {
+    return *Val;
+  }
+};
+
+template<> struct simplify_type<const value_use_iterator<const User> >
+  : public simplify_type<value_use_iterator<const User> > {};
+
 } // End llvm namespace
 
 #endif





From lattner at cs.uiuc.edu  Mon Mar 27 16:49:58 2006
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Mon, 27 Mar 2006 16:49:58 -0600
Subject: [llvm-commits] CVS: llvm/include/llvm/Intrinsics.td 
Message-ID: <200603272249.QAA10951@zion.cs.uiuc.edu>



Changes in directory llvm/include/llvm:

Intrinsics.td updated: 1.28 -> 1.29
---
Log message:

Add support for intrinsics with pointer arguments in target .td files.


---
Diffs of the changes:  (+3 -3)

 Intrinsics.td |    6 +++---
 1 files changed, 3 insertions(+), 3 deletions(-)


Index: llvm/include/llvm/Intrinsics.td
diff -u llvm/include/llvm/Intrinsics.td:1.28 llvm/include/llvm/Intrinsics.td:1.29
--- llvm/include/llvm/Intrinsics.td:1.28	Sat Mar 25 20:37:19 2006
+++ llvm/include/llvm/Intrinsics.td	Mon Mar 27 16:49:46 2006
@@ -75,9 +75,9 @@
 def llvm_ulong_ty      : LLVMType<i64, "Type::ULongTyID">;
 def llvm_float_ty      : LLVMType<f32, "Type::FloatTyID">;
 def llvm_double_ty     : LLVMType<f64, "Type::DoubleTyID">;
-def llvm_ptr_ty        : LLVMType<OtherVT, "Type::PointerTyID">;     // sbyte*
-def llvm_ptrptr_ty     : LLVMType<OtherVT, "Type::PointerTyID">;     // sbyte**
-def llvm_descriptor_ty : LLVMType<OtherVT, "Type::PointerTyID">;     // global*
+def llvm_ptr_ty        : LLVMType<iPTR, "Type::PointerTyID">;     // sbyte*
+def llvm_ptrptr_ty     : LLVMType<iPTR, "Type::PointerTyID">;     // sbyte**
+def llvm_descriptor_ty : LLVMType<iPTR, "Type::PointerTyID">;     // global*
 
 def llvm_v16i8_ty      : LLVMPackedType<v16i8,16, llvm_sbyte_ty>;  // 16 x sbyte
 def llvm_v8i16_ty      : LLVMPackedType<v8i16, 8, llvm_short_ty>;  // 8 x short





From jlaskey at apple.com  Mon Mar 27 17:30:30 2006
From: jlaskey at apple.com (Jim Laskey)
Date: Mon, 27 Mar 2006 17:30:30 -0600
Subject: [llvm-commits] CVS: llvm/include/llvm/IntrinsicInst.h 
Message-ID: <200603272330.RAA11156@zion.cs.uiuc.edu>



Changes in directory llvm/include/llvm:

IntrinsicInst.h updated: 1.14 -> 1.15
---
Log message:

Should not remove casts from variable's alloca.


---
Diffs of the changes:  (+1 -1)

 IntrinsicInst.h |    2 +-
 1 files changed, 1 insertion(+), 1 deletion(-)


Index: llvm/include/llvm/IntrinsicInst.h
diff -u llvm/include/llvm/IntrinsicInst.h:1.14 llvm/include/llvm/IntrinsicInst.h:1.15
--- llvm/include/llvm/IntrinsicInst.h:1.14	Fri Mar 24 03:50:26 2006
+++ llvm/include/llvm/IntrinsicInst.h	Mon Mar 27 17:30:18 2006
@@ -163,7 +163,7 @@
   /// DbgDeclareInst - This represents the llvm.dbg.declare instruction.
   ///
   struct DbgDeclareInst : public DbgInfoIntrinsic {
-    Value *getAddress()  const { return StripCast(getOperand(1)); }
+    Value *getAddress()  const { return getOperand(1); }
     Value *getVariable() const { return StripCast(getOperand(2)); }
 
     // Methods for support type inquiry through isa, cast, and dyn_cast:





From jlaskey at apple.com  Mon Mar 27 17:31:22 2006
From: jlaskey at apple.com (Jim Laskey)
Date: Mon, 27 Mar 2006 17:31:22 -0600
Subject: [llvm-commits] 
	CVS: llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
Message-ID: <200603272331.RAA11168@zion.cs.uiuc.edu>



Changes in directory llvm/lib/CodeGen/SelectionDAG:

SelectionDAGISel.cpp updated: 1.208 -> 1.209
---
Log message:

Reactivate llvm.dbg.declare.


---
Diffs of the changes:  (+0 -1)

 SelectionDAGISel.cpp |    1 -
 1 files changed, 1 deletion(-)


Index: llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.208 llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.209
--- llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.208	Mon Mar 27 15:36:03 2006
+++ llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp	Mon Mar 27 17:31:10 2006
@@ -1382,7 +1382,6 @@
     return 0;
   }
   case Intrinsic::dbg_declare: {
-    return 0;
     MachineDebugInfo *DebugInfo = DAG.getMachineDebugInfo();
     DbgDeclareInst &DI = cast<DbgDeclareInst>(I);
     if (DebugInfo && DebugInfo->Verify(DI.getVariable())) {





From alenhar2 at cs.uiuc.edu  Mon Mar 27 17:39:00 2006
From: alenhar2 at cs.uiuc.edu (Andrew Lenharth)
Date: Mon, 27 Mar 2006 17:39:00 -0600
Subject: [llvm-commits] 
	CVS: llvm/test/Regression/Analysis/DSGraph/2006-03-27-LinkedCollapsed.ll
Message-ID: <200603272339.RAA11223@zion.cs.uiuc.edu>



Changes in directory llvm/test/Regression/Analysis/DSGraph:

2006-03-27-LinkedCollapsed.ll added (r1.1)
---
Log message:

Adding links to a node collapsed during type merging crashes.



---
Diffs of the changes:  (+26 -0)

 2006-03-27-LinkedCollapsed.ll |   26 ++++++++++++++++++++++++++
 1 files changed, 26 insertions(+)


Index: llvm/test/Regression/Analysis/DSGraph/2006-03-27-LinkedCollapsed.ll
diff -c /dev/null llvm/test/Regression/Analysis/DSGraph/2006-03-27-LinkedCollapsed.ll:1.1
*** /dev/null	Mon Mar 27 17:38:58 2006
--- llvm/test/Regression/Analysis/DSGraph/2006-03-27-LinkedCollapsed.ll	Mon Mar 27 17:38:48 2006
***************
*** 0 ****
--- 1,26 ----
+ ; RUN: llvm-as < %s | analyze -datastructure
+ 
+ target endian = little
+ target pointersize = 32
+ target triple = "i686-pc-linux-gnu"
+ deplibs = [ "c", "crtend", "stdc++" ]
+ 	%struct.Blend_Map_Entry = type { float, ubyte, { [2 x double], [4 x ubyte] } }
+ 	%struct.Blend_Map_Struct = type { short, short, short, int, %struct.Blend_Map_Entry* }
+ 	%struct.Image_Colour_Struct = type { ushort, ushort, ushort, ushort, ushort }
+ 	%struct.Image_Struct = type { int, int, int, int, int, short, short, [3 x double], float, float, int, int, short, %struct.Image_Colour_Struct*, { ubyte** } }
+ 	%struct.Pattern_Struct = type { ushort, ushort, ushort, int, float, float, float, %struct.Warps_Struct*, %struct.Pattern_Struct*, %struct.Blend_Map_Struct*, { [3 x double], [4 x ubyte] } }
+ 	%struct.Tnormal_Struct = type { ushort, ushort, ushort, int, float, float, float, %struct.Warps_Struct*, %struct.Pattern_Struct*, %struct.Blend_Map_Struct*, { [3 x double], [4 x ubyte] }, float }
+ 	%struct.Warps_Struct = type { ushort, %struct.Warps_Struct* }
+ 
+ implementation   ; Functions:
+ 
+ declare fastcc %struct.Image_Struct* %Parse_Image()
+ 
+ fastcc void %Parse_Bump_Map(%struct.Tnormal_Struct* %Tnormal) {
+ entry:
+ 	%tmp.0 = tail call fastcc %struct.Image_Struct* %Parse_Image( )		; <%struct.Image_Struct*> [#uses=1]
+ 	%tmp.28 = getelementptr %struct.Tnormal_Struct* %Tnormal, int 0, uint 10		; <{ [3 x double], [4 x ubyte] }*> [#uses=1]
+ 	%tmp.32 = cast { [3 x double], [4 x ubyte] }* %tmp.28 to %struct.Image_Struct**		; <%struct.Image_Struct**> [#uses=1]
+ 	store %struct.Image_Struct* %tmp.0, %struct.Image_Struct** %tmp.32
+ 	ret void
+ }





From alenhar2 at cs.uiuc.edu  Mon Mar 27 17:40:10 2006
From: alenhar2 at cs.uiuc.edu (Andrew Lenharth)
Date: Mon, 27 Mar 2006 17:40:10 -0600
Subject: [llvm-commits] 
	CVS: llvm/lib/Analysis/DataStructure/DataStructure.cpp
Message-ID: <200603272340.RAA11255@zion.cs.uiuc.edu>



Changes in directory llvm/lib/Analysis/DataStructure:

DataStructure.cpp updated: 1.243 -> 1.244
---
Log message:

If adding a link to a collapsed, node, ignore offset.
Fixes 2006-03-27-LinkedCollapsed.ll



---
Diffs of the changes:  (+3 -0)

 DataStructure.cpp |    3 +++
 1 files changed, 3 insertions(+)


Index: llvm/lib/Analysis/DataStructure/DataStructure.cpp
diff -u llvm/lib/Analysis/DataStructure/DataStructure.cpp:1.243 llvm/lib/Analysis/DataStructure/DataStructure.cpp:1.244
--- llvm/lib/Analysis/DataStructure/DataStructure.cpp:1.243	Tue Mar 14 23:43:41 2006
+++ llvm/lib/Analysis/DataStructure/DataStructure.cpp	Mon Mar 27 17:39:58 2006
@@ -701,6 +701,9 @@
 void DSNode::addEdgeTo(unsigned Offset, const DSNodeHandle &NH) {
   if (NH.isNull()) return;       // Nothing to do
 
+  if (isNodeCompletelyFolded())
+    Offset = 0;
+
   DSNodeHandle &ExistingEdge = getLink(Offset);
   if (!ExistingEdge.isNull()) {
     // Merge the two nodes...





From lattner at cs.uiuc.edu  Mon Mar 27 18:03:04 2006
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Mon, 27 Mar 2006 18:03:04 -0600
Subject: [llvm-commits] CVS: llvm/include/llvm/Intrinsics.td 
Message-ID: <200603280003.SAA11466@zion.cs.uiuc.edu>



Changes in directory llvm/include/llvm:

Intrinsics.td updated: 1.29 -> 1.30
---
Log message:

revert this, it breaks things


---
Diffs of the changes:  (+3 -3)

 Intrinsics.td |    6 +++---
 1 files changed, 3 insertions(+), 3 deletions(-)


Index: llvm/include/llvm/Intrinsics.td
diff -u llvm/include/llvm/Intrinsics.td:1.29 llvm/include/llvm/Intrinsics.td:1.30
--- llvm/include/llvm/Intrinsics.td:1.29	Mon Mar 27 16:49:46 2006
+++ llvm/include/llvm/Intrinsics.td	Mon Mar 27 18:02:52 2006
@@ -75,9 +75,9 @@
 def llvm_ulong_ty      : LLVMType<i64, "Type::ULongTyID">;
 def llvm_float_ty      : LLVMType<f32, "Type::FloatTyID">;
 def llvm_double_ty     : LLVMType<f64, "Type::DoubleTyID">;
-def llvm_ptr_ty        : LLVMType<iPTR, "Type::PointerTyID">;     // sbyte*
-def llvm_ptrptr_ty     : LLVMType<iPTR, "Type::PointerTyID">;     // sbyte**
-def llvm_descriptor_ty : LLVMType<iPTR, "Type::PointerTyID">;     // global*
+def llvm_ptr_ty        : LLVMType<OtherVT, "Type::PointerTyID">;     // sbyte*
+def llvm_ptrptr_ty     : LLVMType<OtherVT, "Type::PointerTyID">;     // sbyte**
+def llvm_descriptor_ty : LLVMType<OtherVT, "Type::PointerTyID">;     // global*
 
 def llvm_v16i8_ty      : LLVMPackedType<v16i8,16, llvm_sbyte_ty>;  // 16 x sbyte
 def llvm_v8i16_ty      : LLVMPackedType<v8i16, 8, llvm_short_ty>;  // 8 x short





From lattner at cs.uiuc.edu  Mon Mar 27 18:03:20 2006
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Mon, 27 Mar 2006 18:03:20 -0600
Subject: [llvm-commits] CVS: llvm/utils/TableGen/CodeGenIntrinsics.h
	CodeGenTarget.cpp 
Message-ID: <200603280003.SAA11478@zion.cs.uiuc.edu>



Changes in directory llvm/utils/TableGen:

CodeGenIntrinsics.h updated: 1.8 -> 1.9
CodeGenTarget.cpp updated: 1.60 -> 1.61
---
Log message:

revert this, it breaks things.


---
Diffs of the changes:  (+4 -5)

 CodeGenIntrinsics.h |    2 +-
 CodeGenTarget.cpp   |    7 +++----
 2 files changed, 4 insertions(+), 5 deletions(-)


Index: llvm/utils/TableGen/CodeGenIntrinsics.h
diff -u llvm/utils/TableGen/CodeGenIntrinsics.h:1.8 llvm/utils/TableGen/CodeGenIntrinsics.h:1.9
--- llvm/utils/TableGen/CodeGenIntrinsics.h:1.8	Mon Mar 27 16:48:18 2006
+++ llvm/utils/TableGen/CodeGenIntrinsics.h	Mon Mar 27 18:03:08 2006
@@ -46,7 +46,7 @@
       NoMem, ReadArgMem, ReadMem, WriteArgMem, WriteMem
     } ModRef;
 
-    CodeGenIntrinsic(Record *R, CodeGenTarget &CGT);
+    CodeGenIntrinsic(Record *R, CodeGenTarget *CGT);
   };
 
   /// LoadIntrinsics - Read all of the intrinsics defined in the specified


Index: llvm/utils/TableGen/CodeGenTarget.cpp
diff -u llvm/utils/TableGen/CodeGenTarget.cpp:1.60 llvm/utils/TableGen/CodeGenTarget.cpp:1.61
--- llvm/utils/TableGen/CodeGenTarget.cpp:1.60	Mon Mar 27 16:48:18 2006
+++ llvm/utils/TableGen/CodeGenTarget.cpp	Mon Mar 27 18:03:08 2006
@@ -362,13 +362,12 @@
   std::vector<Record*> I = RC.getAllDerivedDefinitions("Intrinsic");
   
   std::vector<CodeGenIntrinsic> Result;
-  CodeGenTarget CGT;
   for (unsigned i = 0, e = I.size(); i != e; ++i)
-    Result.push_back(CodeGenIntrinsic(I[i], CGT));
+    Result.push_back(CodeGenIntrinsic(I[i], 0));
   return Result;
 }
 
-CodeGenIntrinsic::CodeGenIntrinsic(Record *R, CodeGenTarget &CGT) {
+CodeGenIntrinsic::CodeGenIntrinsic(Record *R, CodeGenTarget *CGT) {
   TheDef = R;
   std::string DefName = R->getName();
   ModRef = WriteMem;
@@ -415,7 +414,7 @@
     assert(TyEl->isSubClassOf("LLVMType") && "Expected a type!");
     ArgTypes.push_back(TyEl->getValueAsString("TypeVal"));
     
-    ArgVTs.push_back(getValueType(TyEl->getValueAsDef("VT"), &CGT));
+    ArgVTs.push_back(getValueType(TyEl->getValueAsDef("VT"), 0));
     ArgTypeDefs.push_back(TyEl);
   }
   if (ArgTypes.size() == 0)





From lattner at cs.uiuc.edu  Mon Mar 27 18:15:12 2006
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Mon, 27 Mar 2006 18:15:12 -0600
Subject: [llvm-commits] CVS: llvm/utils/TableGen/CodeGenIntrinsics.h
	CodeGenTarget.cpp 
Message-ID: <200603280015.SAA11564@zion.cs.uiuc.edu>



Changes in directory llvm/utils/TableGen:

CodeGenIntrinsics.h updated: 1.9 -> 1.10
CodeGenTarget.cpp updated: 1.61 -> 1.62
---
Log message:

Only compute intrinsic valuetypes when in a target .td file.


---
Diffs of the changes:  (+16 -3)

 CodeGenIntrinsics.h |    5 ++++-
 CodeGenTarget.cpp   |   14 ++++++++++++--
 2 files changed, 16 insertions(+), 3 deletions(-)


Index: llvm/utils/TableGen/CodeGenIntrinsics.h
diff -u llvm/utils/TableGen/CodeGenIntrinsics.h:1.9 llvm/utils/TableGen/CodeGenIntrinsics.h:1.10
--- llvm/utils/TableGen/CodeGenIntrinsics.h:1.9	Mon Mar 27 18:03:08 2006
+++ llvm/utils/TableGen/CodeGenIntrinsics.h	Mon Mar 27 18:15:00 2006
@@ -34,7 +34,10 @@
     /// of the arguments.  These are things like Type::UIntTyID.
     std::vector<std::string> ArgTypes;
     
-    /// ArgVTs - The MVT::ValueType for each argument type.
+    /// ArgVTs - The MVT::ValueType for each argument type.  Note that this list
+    /// is only populated when in the context of a target .td file.  When
+    /// building Intrinsics.td, this isn't available, because we don't know the
+    /// target pointer size.
     std::vector<MVT::ValueType> ArgVTs;
     
     /// ArgTypeDefs - The records for each argument type.


Index: llvm/utils/TableGen/CodeGenTarget.cpp
diff -u llvm/utils/TableGen/CodeGenTarget.cpp:1.61 llvm/utils/TableGen/CodeGenTarget.cpp:1.62
--- llvm/utils/TableGen/CodeGenTarget.cpp:1.61	Mon Mar 27 18:03:08 2006
+++ llvm/utils/TableGen/CodeGenTarget.cpp	Mon Mar 27 18:15:00 2006
@@ -362,8 +362,17 @@
   std::vector<Record*> I = RC.getAllDerivedDefinitions("Intrinsic");
   
   std::vector<CodeGenIntrinsic> Result;
+
+  // If we are in the context of a target .td file, get the target info so that
+  // we can decode the current intptr_t.
+  CodeGenTarget *CGT = 0;
+  if (Records.getClass("Target") &&
+      Records.getAllDerivedDefinitions("Target").size() == 1)
+    CGT = new CodeGenTarget();
+  
   for (unsigned i = 0, e = I.size(); i != e; ++i)
-    Result.push_back(CodeGenIntrinsic(I[i], 0));
+    Result.push_back(CodeGenIntrinsic(I[i], CGT));
+  delete CGT;
   return Result;
 }
 
@@ -414,7 +423,8 @@
     assert(TyEl->isSubClassOf("LLVMType") && "Expected a type!");
     ArgTypes.push_back(TyEl->getValueAsString("TypeVal"));
     
-    ArgVTs.push_back(getValueType(TyEl->getValueAsDef("VT"), 0));
+    if (CGT)
+      ArgVTs.push_back(getValueType(TyEl->getValueAsDef("VT"), CGT));
     ArgTypeDefs.push_back(TyEl);
   }
   if (ArgTypes.size() == 0)





From lattner at cs.uiuc.edu  Mon Mar 27 18:15:56 2006
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Mon, 27 Mar 2006 18:15:56 -0600
Subject: [llvm-commits] CVS: llvm/include/llvm/Intrinsics.td 
Message-ID: <200603280015.SAA11627@zion.cs.uiuc.edu>



Changes in directory llvm/include/llvm:

Intrinsics.td updated: 1.30 -> 1.31
---
Log message:

Reenable pointer intrinsics.


---
Diffs of the changes:  (+3 -3)

 Intrinsics.td |    6 +++---
 1 files changed, 3 insertions(+), 3 deletions(-)


Index: llvm/include/llvm/Intrinsics.td
diff -u llvm/include/llvm/Intrinsics.td:1.30 llvm/include/llvm/Intrinsics.td:1.31
--- llvm/include/llvm/Intrinsics.td:1.30	Mon Mar 27 18:02:52 2006
+++ llvm/include/llvm/Intrinsics.td	Mon Mar 27 18:15:44 2006
@@ -75,9 +75,9 @@
 def llvm_ulong_ty      : LLVMType<i64, "Type::ULongTyID">;
 def llvm_float_ty      : LLVMType<f32, "Type::FloatTyID">;
 def llvm_double_ty     : LLVMType<f64, "Type::DoubleTyID">;
-def llvm_ptr_ty        : LLVMType<OtherVT, "Type::PointerTyID">;     // sbyte*
-def llvm_ptrptr_ty     : LLVMType<OtherVT, "Type::PointerTyID">;     // sbyte**
-def llvm_descriptor_ty : LLVMType<OtherVT, "Type::PointerTyID">;     // global*
+def llvm_ptr_ty        : LLVMType<iPTR, "Type::PointerTyID">;     // sbyte*
+def llvm_ptrptr_ty     : LLVMType<iPTR, "Type::PointerTyID">;     // sbyte**
+def llvm_descriptor_ty : LLVMType<iPTR, "Type::PointerTyID">;     // global*
 
 def llvm_v16i8_ty      : LLVMPackedType<v16i8,16, llvm_sbyte_ty>;  // 16 x sbyte
 def llvm_v8i16_ty      : LLVMPackedType<v8i16, 8, llvm_short_ty>;  // 8 x short





From lattner at cs.uiuc.edu  Mon Mar 27 18:39:18 2006
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Mon, 27 Mar 2006 18:39:18 -0600
Subject: [llvm-commits] CVS: llvm/include/llvm/CodeGen/SelectionDAGNodes.h 
Message-ID: <200603280039.SAA11766@zion.cs.uiuc.edu>



Changes in directory llvm/include/llvm/CodeGen:

SelectionDAGNodes.h updated: 1.123 -> 1.124
---
Log message:

Tblgen doesn't like multiple SDNode<> definitions that map to the same
enum value.  Split them into separate enums.


---
Diffs of the changes:  (+22 -8)

 SelectionDAGNodes.h |   30 ++++++++++++++++++++++--------
 1 files changed, 22 insertions(+), 8 deletions(-)


Index: llvm/include/llvm/CodeGen/SelectionDAGNodes.h
diff -u llvm/include/llvm/CodeGen/SelectionDAGNodes.h:1.123 llvm/include/llvm/CodeGen/SelectionDAGNodes.h:1.124
--- llvm/include/llvm/CodeGen/SelectionDAGNodes.h:1.123	Mon Mar 27 00:58:47 2006
+++ llvm/include/llvm/CodeGen/SelectionDAGNodes.h	Mon Mar 27 18:39:06 2006
@@ -80,14 +80,28 @@
     TargetConstantPool,
     TargetExternalSymbol,
     
-    /// RESULT{,OUTCHAIN} = INTRINSIC({INCHAIN,} INTRINSICID, arg1, arg2, ...)
-    /// This node represents a target intrinsic function.  If the intrinsic
-    /// has side effects, the first operand is a chain pointer and the result
-    /// includes an output chain.  After this input is the ID number of the 
-    /// intrinsic, from the llvm::intrinsic namespace.  The operands to the 
-    /// intrinsic follow.
-    INTRINSIC,
-
+    /// RESULT = INTRINSIC_WO_CHAIN(INTRINSICID, arg1, arg2, ...)
+    /// This node represents a target intrinsic function with no side effects.
+    /// The first operand is the ID number of the intrinsic from the
+    /// llvm::Intrinsic namespace.  The operands to the intrinsic follow.  The
+    /// node has returns the result of the intrinsic.
+    INTRINSIC_WO_CHAIN,
+    
+    /// RESULT,OUTCHAIN = INTRINSIC_W_CHAIN(INCHAIN, INTRINSICID, arg1, ...)
+    /// This node represents a target intrinsic function with side effects that
+    /// returns a result.  The first operand is a chain pointer.  The second is
+    /// the ID number of the intrinsic from the llvm::Intrinsic namespace.  The
+    /// operands to the intrinsic follow.  The node has two results, the result
+    /// of the intrinsic and an output chain.
+    INTRINSIC_W_CHAIN,
+
+    /// OUTCHAIN = INTRINSIC_VOID(INCHAIN, INTRINSICID, arg1, arg2, ...)
+    /// This node represents a target intrinsic function with side effects that
+    /// does not return a result.  The first operand is a chain pointer.  The
+    /// second is the ID number of the intrinsic from the llvm::Intrinsic
+    /// namespace.  The operands to the intrinsic follow.
+    INTRINSIC_VOID,
+    
     // CopyToReg - This node has three operands: a chain, a register number to
     // set to this value, and a value.  
     CopyToReg,





From evan.cheng at apple.com  Mon Mar 27 18:40:10 2006
From: evan.cheng at apple.com (Evan Cheng)
Date: Mon, 27 Mar 2006 18:40:10 -0600
Subject: [llvm-commits] CVS: llvm/lib/Target/X86/X86ISelLowering.cpp
	X86ISelLowering.h X86InstrSSE.td 
Message-ID: <200603280040.SAA11893@zion.cs.uiuc.edu>



Changes in directory llvm/lib/Target/X86:

X86ISelLowering.cpp updated: 1.135 -> 1.136
X86ISelLowering.h updated: 1.44 -> 1.45
X86InstrSSE.td updated: 1.34 -> 1.35
---
Log message:

Model unpack lower and interleave as vector_shuffle so we can lower the
intrinsics as such.


---
Diffs of the changes:  (+88 -33)

 X86ISelLowering.cpp |   53 +++++++++++++++++++++++++++++++++++++++------
 X86ISelLowering.h   |    8 +++---
 X86InstrSSE.td      |   60 ++++++++++++++++++++++++++++++++--------------------
 3 files changed, 88 insertions(+), 33 deletions(-)


Index: llvm/lib/Target/X86/X86ISelLowering.cpp
diff -u llvm/lib/Target/X86/X86ISelLowering.cpp:1.135 llvm/lib/Target/X86/X86ISelLowering.cpp:1.136
--- llvm/lib/Target/X86/X86ISelLowering.cpp:1.135	Mon Mar 27 01:00:16 2006
+++ llvm/lib/Target/X86/X86ISelLowering.cpp	Mon Mar 27 18:39:58 2006
@@ -303,14 +303,18 @@
     setOperationAction(ISD::LOAD,             MVT::v8i16, Legal);
     setOperationAction(ISD::LOAD,             MVT::v4i32, Legal);
     setOperationAction(ISD::LOAD,             MVT::v2i64, Legal);
+    setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v16i8, Custom);
+    setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i16, Custom);
     setOperationAction(ISD::BUILD_VECTOR,     MVT::v2f64, Custom);
     setOperationAction(ISD::BUILD_VECTOR,     MVT::v16i8, Custom);
     setOperationAction(ISD::BUILD_VECTOR,     MVT::v8i16, Custom);
     setOperationAction(ISD::BUILD_VECTOR,     MVT::v4i32, Custom);
     setOperationAction(ISD::BUILD_VECTOR,     MVT::v2i64, Custom);
-    setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v16i8, Custom);
-    setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i16, Custom);
     setOperationAction(ISD::VECTOR_SHUFFLE,   MVT::v2f64, Custom);
+    setOperationAction(ISD::VECTOR_SHUFFLE,   MVT::v16i8, Custom);
+    setOperationAction(ISD::VECTOR_SHUFFLE,   MVT::v8i16, Custom);
+    setOperationAction(ISD::VECTOR_SHUFFLE,   MVT::v4i32, Custom);
+    setOperationAction(ISD::VECTOR_SHUFFLE,   MVT::v2i64, Custom);
   }
 
   computeRegisterProperties();
@@ -1499,6 +1503,29 @@
           cast<ConstantSDNode>(Bit1)->getValue() == 3);
 }
 
+/// isUNPCKLMask - Return true if the specified VECTOR_SHUFFLE operand
+/// specifies a shuffle of elements that is suitable for input to UNPCKL.
+bool X86::isUNPCKLMask(SDNode *N) {
+  assert(N->getOpcode() == ISD::BUILD_VECTOR);
+
+  unsigned NumElems = N->getNumOperands();
+  if (NumElems != 2 && NumElems != 4 && NumElems != 8 && NumElems != 16)
+    return false;
+
+  for (unsigned i = 0, j = 0; i != NumElems; i += 2, ++j) {
+    SDOperand BitI  = N->getOperand(i);
+    SDOperand BitI1 = N->getOperand(i+1);
+    assert(isa<ConstantSDNode>(BitI) && isa<ConstantSDNode>(BitI1) &&
+           "Invalid VECTOR_SHUFFLE mask!");
+    if (cast<ConstantSDNode>(BitI)->getValue()  != j)
+      return false;
+    if (cast<ConstantSDNode>(BitI1)->getValue() != j + NumElems)
+      return false;
+  }
+
+  return true;
+}
+
 /// isSplatMask - Return true if the specified VECTOR_SHUFFLE operand specifies
 /// a splat of a single element.
 bool X86::isSplatMask(SDNode *N) {
@@ -2321,6 +2348,9 @@
     MVT::ValueType VT = Op.getValueType();
     unsigned NumElems = PermMask.getNumOperands();
 
+    // All v2f64 cases are handled.
+    if (NumElems == 2) return SDOperand();
+
     // Handle splat cases.
     if (X86::isSplatMask(PermMask.Val)) {
       if (V2.getOpcode() == ISD::UNDEF)
@@ -2332,8 +2362,8 @@
         return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1,
                            DAG.getNode(ISD::UNDEF, V1.getValueType()),
                            PermMask);
-    } else if (NumElems == 2) {
-      // All v2f64 cases are handled.
+    } else if (X86::isUNPCKLMask(PermMask.Val)) {
+      // Leave the VECTOR_SHUFFLE alone. It matches {P}UNPCKL*.
       return SDOperand();
     } else if (X86::isPSHUFDMask(PermMask.Val)) {
       if (V2.getOpcode() == ISD::UNDEF)
@@ -2404,13 +2434,22 @@
       //         : unpcklps 1, 3 ==> Y: <?, ?, 3, 1>
       //   Step 2: unpcklps X, Y ==>    <3, 2, 1, 0>
       MVT::ValueType VT = Op.getValueType();
+      MVT::ValueType MaskVT = MVT::getIntVectorWithNumElements(NumElems);
+      MVT::ValueType BaseVT = MVT::getVectorBaseType(MaskVT);
+      std::vector<SDOperand> MaskVec;
+      for (unsigned i = 0, e = NumElems/2; i != e; ++i) {
+        MaskVec.push_back(DAG.getConstant(i,            BaseVT));
+        MaskVec.push_back(DAG.getConstant(i + NumElems, BaseVT));
+      }
+      SDOperand PermMask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT, MaskVec);
       std::vector<SDOperand> V(NumElems);
       for (unsigned i = 0; i < NumElems; ++i)
         V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, VT, Op.getOperand(i));
       NumElems >>= 1;
       while (NumElems != 0) {
         for (unsigned i = 0; i < NumElems; ++i)
-          V[i] = DAG.getNode(X86ISD::UNPCKL, VT, V[i], V[i + NumElems]);
+          V[i] = DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V[i], V[i + NumElems],
+                             PermMask);
         NumElems >>= 1;
       }
       return V[0];
@@ -2453,7 +2492,6 @@
   case X86ISD::Wrapper:            return "X86ISD::Wrapper";
   case X86ISD::S2VEC:              return "X86ISD::S2VEC";
   case X86ISD::ZEXT_S2VEC:         return "X86ISD::ZEXT_S2VEC";
-  case X86ISD::UNPCKL:             return "X86ISD::UNPCKL";
   }
 }
 
@@ -2543,5 +2581,6 @@
   return (Mask.Val->getNumOperands() == 2 ||
           X86::isSplatMask(Mask.Val) ||
           X86::isPSHUFDMask(Mask.Val) ||
-          X86::isSHUFPMask(Mask.Val));
+          X86::isSHUFPMask(Mask.Val) ||
+          X86::isUNPCKLMask(Mask.Val));
 }


Index: llvm/lib/Target/X86/X86ISelLowering.h
diff -u llvm/lib/Target/X86/X86ISelLowering.h:1.44 llvm/lib/Target/X86/X86ISelLowering.h:1.45
--- llvm/lib/Target/X86/X86ISelLowering.h:1.44	Sun Mar 26 03:53:12 2006
+++ llvm/lib/Target/X86/X86ISelLowering.h	Mon Mar 27 18:39:58 2006
@@ -153,10 +153,6 @@
       /// ZEXT_S2VEC - SCALAR_TO_VECTOR with zero extension. The destination base
       /// does not have to match the operand type.
       ZEXT_S2VEC,
-
-      /// UNPCKL - Unpack and interleave low. This corresponds to X86::UNPCKLPS,
-      /// X86::PUNPCKL*.
-      UNPCKL,
     };
 
     // X86 specific condition code. These correspond to X86_*_COND in
@@ -205,6 +201,10 @@
    /// specifies a shuffle of elements that is suitable for input to UNPCKHPD.
    bool isUNPCKHPDMask(SDNode *N);
 
+   /// isUNPCKLMask - Return true if the specified VECTOR_SHUFFLE operand
+   /// specifies a shuffle of elements that is suitable for input to UNPCKL.
+   bool isUNPCKLMask(SDNode *N);
+
    /// isSplatMask - Return true if the specified VECTOR_SHUFFLE operand
    /// specifies a splat of a single element.
    bool isSplatMask(SDNode *N);


Index: llvm/lib/Target/X86/X86InstrSSE.td
diff -u llvm/lib/Target/X86/X86InstrSSE.td:1.34 llvm/lib/Target/X86/X86InstrSSE.td:1.35
--- llvm/lib/Target/X86/X86InstrSSE.td:1.34	Mon Mar 27 10:52:45 2006
+++ llvm/lib/Target/X86/X86InstrSSE.td	Mon Mar 27 18:39:58 2006
@@ -30,8 +30,6 @@
 
 def SDTUnpckl : SDTypeProfile<1, 2,
                               [SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>]>;
-def X86unpckl  : SDNode<"X86ISD::UNPCKL", SDTUnpckl,
-                        []>;
 
 //===----------------------------------------------------------------------===//
 // SSE pattern fragments
@@ -77,6 +75,10 @@
   return X86::isUNPCKHPDMask(N);
 }], SHUFFLE_get_shuf_imm>;
 
+def UNPCKL_shuffle_mask : PatLeaf<(build_vector), [{
+  return X86::isUNPCKLMask(N);
+}]>;
+
 // Only use PSHUF if it is not a splat.
 def PSHUFD_shuffle_mask : PatLeaf<(build_vector), [{
   return !X86::isSplatMask(N) && X86::isPSHUFDMask(N);
@@ -756,14 +758,17 @@
 
 let isTwoAddress = 1 in {
 def SHUFPSrr : PSIi8<0xC6, MRMSrcReg, 
-                     (ops VR128:$dst, VR128:$src1, VR128:$src2, i8imm:$src3),
+                     (ops VR128:$dst, VR128:$src1, VR128:$src2, i32i8imm:$src3),
                      "shufps {$src3, $src2, $dst|$dst, $src2, $src3}",
                     [(set VR128:$dst, (vector_shuffle
                                        (v4f32 VR128:$src1), (v4f32 VR128:$src2),
                                        SHUFP_shuffle_mask:$src3))]>;
 def SHUFPSrm : PSIi8<0xC6, MRMSrcMem, 
-                     (ops VR128:$dst, VR128:$src1, f128mem:$src2, i8imm:$src3),
-                     "shufps {$src3, $src2, $dst|$dst, $src2, $src3}", []>;
+                   (ops VR128:$dst, VR128:$src1, f128mem:$src2, i32i8imm:$src3),
+                     "shufps {$src3, $src2, $dst|$dst, $src2, $src3}",
+                    [(set VR128:$dst, (vector_shuffle
+                                       (v4f32 VR128:$src1), (load addr:$src2),
+                                       SHUFP_shuffle_mask:$src3))]>;
 def SHUFPDrr : PDIi8<0xC6, MRMSrcReg, 
                      (ops VR128:$dst, VR128:$src1, VR128:$src2, i8imm:$src3),
                      "shufpd {$src3, $src2, $dst|$dst, $src2, $src3}",
@@ -772,7 +777,10 @@
                                        SHUFP_shuffle_mask:$src3))]>;
 def SHUFPDrm : PDIi8<0xC6, MRMSrcMem, 
                      (ops VR128:$dst, VR128:$src1, f128mem:$src2, i8imm:$src3),
-                     "shufpd {$src3, $src2, $dst|$dst, $src2, $src3}", []>;
+                     "shufpd {$src3, $src2, $dst|$dst, $src2, $src3}",
+                    [(set VR128:$dst, (vector_shuffle
+                                       (v2f64 VR128:$src1), (load addr:$src2),
+                                       SHUFP_shuffle_mask:$src3))]>;
 
 def UNPCKHPSrr : PSI<0x15, MRMSrcReg, 
                     (ops VR128:$dst, VR128:$src1, VR128:$src2),
@@ -789,13 +797,15 @@
 def UNPCKLPSrr : PSI<0x14, MRMSrcReg, 
                     (ops VR128:$dst, VR128:$src1, VR128:$src2),
                     "unpcklps {$src2, $dst|$dst, $src2}",
-                    [(set VR128:$dst, (v4f32 (X86unpckl VR128:$src1,
-                                              VR128:$src2)))]>;
+                    [(set VR128:$dst,
+                      (v4f32 (vector_shuffle VR128:$src1, VR128:$src2,
+                              UNPCKL_shuffle_mask)))]>;
 def UNPCKLPSrm : PSI<0x14, MRMSrcMem, 
                     (ops VR128:$dst, VR128:$src1, f128mem:$src2),
                     "unpcklps {$src2, $dst|$dst, $src2}",
-                    [(set VR128:$dst, (v4f32 (X86unpckl VR128:$src1,
-                                              (load addr:$src2))))]>;
+                    [(set VR128:$dst,
+                      (v4f32 (vector_shuffle VR128:$src1, (load addr:$src2),
+                              UNPCKL_shuffle_mask)))]>;
 def UNPCKLPDrr : PDI<0x14, MRMSrcReg, 
                     (ops VR128:$dst, VR128:$src1, VR128:$src2),
                     "unpcklpd {$src2, $dst|$dst, $src2}", []>;
@@ -895,33 +905,39 @@
 def PUNPCKLBWrr : PDI<0x60, MRMSrcReg, 
                       (ops VR128:$dst, VR128:$src1, VR128:$src2),
                       "punpcklbw {$src2, $dst|$dst, $src2}",
-                      [(set VR128:$dst, (v16i8 (X86unpckl VR128:$src1,
-                                                VR128:$src2)))]>;
+                      [(set VR128:$dst,
+                        (v16i8 (vector_shuffle VR128:$src1, VR128:$src2,
+                                UNPCKL_shuffle_mask)))]>;
 def PUNPCKLBWrm : PDI<0x60, MRMSrcMem, 
                       (ops VR128:$dst, VR128:$src1, i128mem:$src2),
                       "punpcklbw {$src2, $dst|$dst, $src2}",
-                      [(set VR128:$dst, (v16i8 (X86unpckl VR128:$src1,
-                                                (load addr:$src2))))]>;
+                      [(set VR128:$dst,
+                        (v16i8 (vector_shuffle VR128:$src1, (load addr:$src2),
+                                UNPCKL_shuffle_mask)))]>;
 def PUNPCKLWDrr : PDI<0x61, MRMSrcReg, 
                       (ops VR128:$dst, VR128:$src1, VR128:$src2),
                       "punpcklwd {$src2, $dst|$dst, $src2}",
-                      [(set VR128:$dst, (v8i16 (X86unpckl VR128:$src1,
-                                                VR128:$src2)))]>;
+                      [(set VR128:$dst,
+                        (v8i16 (vector_shuffle VR128:$src1, VR128:$src2,
+                                UNPCKL_shuffle_mask)))]>;
 def PUNPCKLWDrm : PDI<0x61, MRMSrcMem, 
                       (ops VR128:$dst, VR128:$src1, i128mem:$src2),
                       "punpcklwd {$src2, $dst|$dst, $src2}",
-                      [(set VR128:$dst, (v8i16 (X86unpckl VR128:$src1,
-                                                (load addr:$src2))))]>;
+                      [(set VR128:$dst,
+                        (v8i16 (vector_shuffle VR128:$src1, (load addr:$src2),
+                                UNPCKL_shuffle_mask)))]>;
 def PUNPCKLDQrr : PDI<0x62, MRMSrcReg, 
                       (ops VR128:$dst, VR128:$src1, VR128:$src2),
                       "punpckldq {$src2, $dst|$dst, $src2}",
-                      [(set VR128:$dst, (v4i32 (X86unpckl VR128:$src1,
-                                                VR128:$src2)))]>;
+                      [(set VR128:$dst,
+                        (v4i32 (vector_shuffle VR128:$src1, VR128:$src2,
+                                UNPCKL_shuffle_mask)))]>;
 def PUNPCKLDQrm : PDI<0x62, MRMSrcMem, 
                       (ops VR128:$dst, VR128:$src1, i128mem:$src2),
                       "punpckldq {$src2, $dst|$dst, $src2}",
-                      [(set VR128:$dst, (v4i32 (X86unpckl VR128:$src1,
-                                                (load addr:$src2))))]>;
+                      [(set VR128:$dst,
+                        (v4i32 (vector_shuffle VR128:$src1, (load addr:$src2),
+                                UNPCKL_shuffle_mask)))]>;
 def PUNPCKLQDQrr : PDI<0x6C, MRMSrcReg, 
                        (ops VR128:$dst, VR128:$src1, VR128:$src2),
                        "punpcklqdq {$src2, $dst|$dst, $src2}", []>;





From lattner at cs.uiuc.edu  Mon Mar 27 18:40:21 2006
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Mon, 27 Mar 2006 18:40:21 -0600
Subject: [llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
	SelectionDAG.cpp SelectionDAGISel.cpp 
Message-ID: <200603280040.SAA11904@zion.cs.uiuc.edu>



Changes in directory llvm/lib/CodeGen/SelectionDAG:

LegalizeDAG.cpp updated: 1.340 -> 1.341
SelectionDAG.cpp updated: 1.289 -> 1.290
SelectionDAGISel.cpp updated: 1.209 -> 1.210
---
Log message:

Tblgen doesn't like multiple SDNode<> definitions that map to the sameenum value.  Split them into separate enums.


---
Diffs of the changes:  (+19 -7)

 LegalizeDAG.cpp      |    6 ++++--
 SelectionDAG.cpp     |   10 +++++++---
 SelectionDAGISel.cpp |   10 ++++++++--
 3 files changed, 19 insertions(+), 7 deletions(-)


Index: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.340 llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.341
--- llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.340	Mon Mar 27 14:28:29 2006
+++ llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp	Mon Mar 27 18:40:09 2006
@@ -553,14 +553,16 @@
     break;
   }
     
-  case ISD::INTRINSIC: {
+  case ISD::INTRINSIC_W_CHAIN:
+  case ISD::INTRINSIC_WO_CHAIN:
+  case ISD::INTRINSIC_VOID: {
     std::vector<SDOperand> Ops;
     for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i)
       Ops.push_back(LegalizeOp(Node->getOperand(i)));
     Result = DAG.UpdateNodeOperands(Result, Ops);
     
     // Allow the target to custom lower its intrinsics if it wants to.
-    if (TLI.getOperationAction(ISD::INTRINSIC, MVT::Other) == 
+    if (TLI.getOperationAction(Node->getOpcode(), MVT::Other) == 
         TargetLowering::Custom) {
       Tmp3 = TLI.LowerOperation(Result, DAG);
       if (Tmp3.Val) Result = Tmp3;


Index: llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp:1.289 llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp:1.290
--- llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp:1.289	Mon Mar 27 10:10:59 2006
+++ llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp	Mon Mar 27 18:40:09 2006
@@ -2689,9 +2689,13 @@
   case ISD::FrameIndex:    return "FrameIndex";
   case ISD::ConstantPool:  return "ConstantPool";
   case ISD::ExternalSymbol: return "ExternalSymbol";
-  case ISD::INTRINSIC: {
-    bool hasChain = getOperand(0).getValueType() == MVT::Other;
-    unsigned IID = cast<ConstantSDNode>(getOperand(hasChain))->getValue();
+  case ISD::INTRINSIC_WO_CHAIN: {
+    unsigned IID = cast<ConstantSDNode>(getOperand(0))->getValue();
+    return Intrinsic::getName((Intrinsic::ID)IID);
+  }
+  case ISD::INTRINSIC_VOID:
+  case ISD::INTRINSIC_W_CHAIN: {
+    unsigned IID = cast<ConstantSDNode>(getOperand(1))->getValue();
     return Intrinsic::getName((Intrinsic::ID)IID);
   }
 


Index: llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.209 llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.210
--- llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.209	Mon Mar 27 17:31:10 2006
+++ llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp	Mon Mar 27 18:40:09 2006
@@ -1261,8 +1261,14 @@
     VTs.push_back(MVT::Other);
 
   // Create the node.
-  SDOperand Result = DAG.getNode(ISD::INTRINSIC, VTs, Ops);
-  
+  SDOperand Result;
+  if (!HasChain)
+    Result = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, VTs, Ops);
+  else if (I.getType() != Type::VoidTy)
+    Result = DAG.getNode(ISD::INTRINSIC_W_CHAIN, VTs, Ops);
+  else
+    Result = DAG.getNode(ISD::INTRINSIC_VOID, VTs, Ops);
+
   if (HasChain)
     DAG.setRoot(Result.getValue(Result.Val->getNumValues()-1));
   if (I.getType() != Type::VoidTy) {





From lattner at cs.uiuc.edu  Mon Mar 27 18:40:46 2006
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Mon, 27 Mar 2006 18:40:46 -0600
Subject: [llvm-commits] CVS: llvm/lib/Target/TargetSelectionDAG.td 
Message-ID: <200603280040.SAA11944@zion.cs.uiuc.edu>



Changes in directory llvm/lib/Target:

TargetSelectionDAG.td updated: 1.61 -> 1.62
---
Log message:

Tblgen doesn't like multiple SDNode<> definitions that map to the sameenum value.  Split them into separate enums.


---
Diffs of the changes:  (+3 -3)

 TargetSelectionDAG.td |    6 +++---
 1 files changed, 3 insertions(+), 3 deletions(-)


Index: llvm/lib/Target/TargetSelectionDAG.td
diff -u llvm/lib/Target/TargetSelectionDAG.td:1.61 llvm/lib/Target/TargetSelectionDAG.td:1.62
--- llvm/lib/Target/TargetSelectionDAG.td:1.61	Mon Mar 27 00:59:32 2006
+++ llvm/lib/Target/TargetSelectionDAG.td	Mon Mar 27 18:40:33 2006
@@ -313,13 +313,13 @@
 
 // Nodes for intrinsics, you should use the intrinsic itself and let tblgen use
 // these internally.  Don't reference these directly.
-def intrinsic_void : SDNode<"ISD::INTRINSIC", 
+def intrinsic_void : SDNode<"ISD::INTRINSIC_VOID", 
                             SDTypeProfile<0, -1, [SDTCisPtrTy<0>]>,
                             [SDNPHasChain]>;
-def intrinsic_w_chain : SDNode<"ISD::INTRINSIC", 
+def intrinsic_w_chain : SDNode<"ISD::INTRINSIC_W_CHAIN", 
                                SDTypeProfile<1, -1, [SDTCisPtrTy<1>]>,
                                [SDNPHasChain]>;
-def intrinsic_wo_chain : SDNode<"ISD::INTRINSIC", 
+def intrinsic_wo_chain : SDNode<"ISD::INTRINSIC_WO_CHAIN", 
                                 SDTypeProfile<1, -1, [SDTCisPtrTy<1>]>, []>;
 
 





From lattner at cs.uiuc.edu  Mon Mar 27 18:40:46 2006
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Mon, 27 Mar 2006 18:40:46 -0600
Subject: [llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCISelLowering.cpp
	PPCInstrAltivec.td 
Message-ID: <200603280040.SAA11950@zion.cs.uiuc.edu>



Changes in directory llvm/lib/Target/PowerPC:

PPCISelLowering.cpp updated: 1.115 -> 1.116
PPCInstrAltivec.td updated: 1.13 -> 1.14
---
Log message:

Tblgen doesn't like multiple SDNode<> definitions that map to the sameenum value.  Split them into separate enums.


---
Diffs of the changes:  (+11 -11)

 PPCISelLowering.cpp |    4 ++--
 PPCInstrAltivec.td  |   18 +++++++++---------
 2 files changed, 11 insertions(+), 11 deletions(-)


Index: llvm/lib/Target/PowerPC/PPCISelLowering.cpp
diff -u llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.115 llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.116
--- llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.115	Sun Mar 26 19:32:24 2006
+++ llvm/lib/Target/PowerPC/PPCISelLowering.cpp	Mon Mar 27 18:40:33 2006
@@ -138,7 +138,7 @@
   setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32  , Expand);
   
   // We want to custom lower some of our intrinsics.
-  setOperationAction(ISD::INTRINSIC         , MVT::Other, Custom);
+  setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
   
   if (TM.getSubtarget<PPCSubtarget>().is64Bit()) {
     // They also have instructions for converting between i64 and fp.
@@ -752,7 +752,7 @@
     SDOperand VPermMask =DAG.getNode(ISD::BUILD_VECTOR, MVT::v16i8, ResultMask);
     return DAG.getNode(PPCISD::VPERM, V1.getValueType(), V1, V2, VPermMask);
   }
-  case ISD::INTRINSIC: {
+  case ISD::INTRINSIC_WO_CHAIN: {
     bool HasChain = Op.getOperand(0).getValueType() == MVT::Other;
     unsigned IntNo=cast<ConstantSDNode>(Op.getOperand(HasChain))->getValue();
     


Index: llvm/lib/Target/PowerPC/PPCInstrAltivec.td
diff -u llvm/lib/Target/PowerPC/PPCInstrAltivec.td:1.13 llvm/lib/Target/PowerPC/PPCInstrAltivec.td:1.14
--- llvm/lib/Target/PowerPC/PPCInstrAltivec.td:1.13	Sun Mar 26 21:34:17 2006
+++ llvm/lib/Target/PowerPC/PPCInstrAltivec.td	Mon Mar 27 18:40:33 2006
@@ -89,15 +89,15 @@
                    []>, PPC970_Unit_LSU;
 
 let isStore = 1, noResults = 1, PPC970_Unit = 2 in {   // Stores.
-def STVEBX: XForm_8<31, 135, (ops VRRC:$rS, GPRC:$rA, GPRC:$rB),
-                   "stvebx $rS, $rA, $rB", LdStGeneral,
-                   []>;
-def STVEHX: XForm_8<31, 167, (ops VRRC:$rS, GPRC:$rA, GPRC:$rB),
-                   "stvehx $rS, $rA, $rB", LdStGeneral,
-                   []>;
-def STVEWX: XForm_8<31, 199, (ops VRRC:$rS, GPRC:$rA, GPRC:$rB),
-                   "stvewx $rS, $rA, $rB", LdStGeneral,
-                   []>;
+def STVEBX: XForm_8<31, 135, (ops VRRC:$rS, memrr:$dst),
+                   "stvebx $rS, $dst", LdStGeneral,
+                   [(int_ppc_altivec_stvebx VRRC:$rS, xoaddr:$dst)]>;
+def STVEHX: XForm_8<31, 167, (ops VRRC:$rS, memrr:$dst),
+                   "stvehx $rS, $dst", LdStGeneral,
+                   [(int_ppc_altivec_stvehx VRRC:$rS, xoaddr:$dst)]>;
+def STVEWX: XForm_8<31, 199, (ops VRRC:$rS, memrr:$dst),
+                   "stvewx $rS, $dst", LdStGeneral,
+                   [(int_ppc_altivec_stvewx VRRC:$rS, xoaddr:$dst)]>;
 def STVX  : XForm_8<31, 231, (ops VRRC:$rS, memrr:$dst),
                    "stvx $rS, $dst", LdStGeneral,
                    [(store (v4f32 VRRC:$rS), xoaddr:$dst)]>;





From lattner at cs.uiuc.edu  Mon Mar 27 18:41:45 2006
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Mon, 27 Mar 2006 18:41:45 -0600
Subject: [llvm-commits] CVS: llvm/utils/TableGen/DAGISelEmitter.cpp 
Message-ID: <200603280041.SAA12014@zion.cs.uiuc.edu>



Changes in directory llvm/utils/TableGen:

DAGISelEmitter.cpp updated: 1.189 -> 1.190
---
Log message:

Tblgen doesn't like multiple SDNode<> definitions that map to the sameenum value.  Split them into separate enums.

Also, don't emit dynamic checks when we can compute them statically


---
Diffs of the changes:  (+17 -13)

 DAGISelEmitter.cpp |   30 +++++++++++++++++-------------
 1 files changed, 17 insertions(+), 13 deletions(-)


Index: llvm/utils/TableGen/DAGISelEmitter.cpp
diff -u llvm/utils/TableGen/DAGISelEmitter.cpp:1.189 llvm/utils/TableGen/DAGISelEmitter.cpp:1.190
--- llvm/utils/TableGen/DAGISelEmitter.cpp:1.189	Mon Mar 27 16:21:18 2006
+++ llvm/utils/TableGen/DAGISelEmitter.cpp	Mon Mar 27 18:41:33 2006
@@ -3115,19 +3115,21 @@
     
     // If the last pattern has predicates (which could fail) emit code to catch
     // the case where nothing handles a pattern.
-    if (mightNotMatch)
-      OS << "  std::cerr << \"Cannot yet select: \";\n"
-         << "  if (N.getOpcode() != ISD::INTRINSIC) {\n"
-         << "    N.Val->dump(CurDAG);\n"
-         << "  } else {\n"
-         << "    unsigned iid = cast<ConstantSDNode>(N.getOperand("
-                 "N.getOperand(0).getValueType() == MVT::Other))->getValue();\n"
-         << "    std::cerr << \"intrinsic %\"<< "
-                       "Intrinsic::getName((Intrinsic::ID)iid);\n"
-         << "  }\n"
-         << "  std::cerr << '\\n';\n"
+    if (mightNotMatch) {
+      OS << "  std::cerr << \"Cannot yet select: \";\n";
+      if (OpcodeInfo.getEnumName() != "ISD::INTRINSIC_W_CHAIN" &&
+          OpcodeInfo.getEnumName() != "ISD::INTRINSIC_WO_CHAIN" &&
+          OpcodeInfo.getEnumName() != "ISD::INTRINSIC_VOID") {
+        OS << "  N.Val->dump(CurDAG);\n";
+      } else {
+        OS << "  unsigned iid = cast<ConstantSDNode>(N.getOperand("
+               "N.getOperand(0).getValueType() == MVT::Other))->getValue();\n"
+           << "  std::cerr << \"intrinsic %\"<< "
+                         "Intrinsic::getName((Intrinsic::ID)iid);\n";
+      }
+      OS << "  std::cerr << '\\n';\n"
          << "  abort();\n";
-
+    }
     OS << "}\n\n";
   }
   
@@ -3285,7 +3287,9 @@
 
   OS << "  } // end of big switch.\n\n"
      << "  std::cerr << \"Cannot yet select: \";\n"
-     << "  if (N.getOpcode() != ISD::INTRINSIC) {\n"
+     << "  if (N.getOpcode() != ISD::INTRINSIC_W_CHAIN &&\n"
+     << "      N.getOpcode() != ISD::INTRINSIC_WO_CHAIN &&\n"
+     << "      N.getOpcode() != ISD::INTRINSIC_VOID) {\n"
      << "    N.Val->dump(CurDAG);\n"
      << "  } else {\n"
      << "    unsigned iid = cast<ConstantSDNode>(N.getOperand("





From jlaskey at apple.com  Mon Mar 27 19:30:30 2006
From: jlaskey at apple.com (Jim Laskey)
Date: Mon, 27 Mar 2006 19:30:30 -0600
Subject: [llvm-commits] CVS: llvm/lib/CodeGen/MachineDebugInfo.cpp 
Message-ID: <200603280130.TAA12232@zion.cs.uiuc.edu>



Changes in directory llvm/lib/CodeGen:

MachineDebugInfo.cpp updated: 1.35 -> 1.36
---
Log message:

More bulletproofing of DebugInfoDesc verify.


---
Diffs of the changes:  (+1 -1)

 MachineDebugInfo.cpp |    2 +-
 1 files changed, 1 insertion(+), 1 deletion(-)


Index: llvm/lib/CodeGen/MachineDebugInfo.cpp
diff -u llvm/lib/CodeGen/MachineDebugInfo.cpp:1.35 llvm/lib/CodeGen/MachineDebugInfo.cpp:1.36
--- llvm/lib/CodeGen/MachineDebugInfo.cpp:1.35	Sun Mar 26 19:51:47 2006
+++ llvm/lib/CodeGen/MachineDebugInfo.cpp	Mon Mar 27 19:30:18 2006
@@ -1323,7 +1323,7 @@
 /// Verify - Return true if the GlobalVariable appears to be a valid
 /// serialization of a DebugInfoDesc.
 bool DIVerifier::Verify(Value *V) {
-  return Verify(getGlobalVariable(V));
+  return !V || Verify(getGlobalVariable(V));
 }
 bool DIVerifier::Verify(GlobalVariable *GV) {
   // NULLs are valid.





From jlaskey at apple.com  Mon Mar 27 19:34:26 2006
From: jlaskey at apple.com (Jim Laskey)
Date: Mon, 27 Mar 2006 19:34:26 -0600
Subject: [llvm-commits] 
	CVS: llvm/test/Regression/CodeGen/Generic/2006-03-27-DebugInfoNULLDeclare.ll
Message-ID: <200603280134.TAA12292@zion.cs.uiuc.edu>



Changes in directory llvm/test/Regression/CodeGen/Generic:

2006-03-27-DebugInfoNULLDeclare.ll added (r1.1)
---
Log message:

Regression test for the handling of nulls as arguments to debug intrinsics.


---
Diffs of the changes:  (+10 -0)

 2006-03-27-DebugInfoNULLDeclare.ll |   10 ++++++++++
 1 files changed, 10 insertions(+)


Index: llvm/test/Regression/CodeGen/Generic/2006-03-27-DebugInfoNULLDeclare.ll
diff -c /dev/null llvm/test/Regression/CodeGen/Generic/2006-03-27-DebugInfoNULLDeclare.ll:1.1
*** /dev/null	Mon Mar 27 19:34:24 2006
--- llvm/test/Regression/CodeGen/Generic/2006-03-27-DebugInfoNULLDeclare.ll	Mon Mar 27 19:34:14 2006
***************
*** 0 ****
--- 1,10 ----
+ ; RUN: llvm-as < %s | llc
+ 
+ implementation   ; Functions:
+ 
+ declare void %llvm.dbg.declare({  }*, {  }*)
+ 
+ void %foo() {
+ 	call void %llvm.dbg.declare( {  }* null, {  }* null ) 
+ 	ret void
+ }





From lattner at cs.uiuc.edu  Mon Mar 27 19:43:36 2006
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Mon, 27 Mar 2006 19:43:36 -0600
Subject: [llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCISelLowering.cpp
	PPCISelLowering.h PPCInstrAltivec.td PPCInstrInfo.td 
Message-ID: <200603280143.TAA12389@zion.cs.uiuc.edu>



Changes in directory llvm/lib/Target/PowerPC:

PPCISelLowering.cpp updated: 1.116 -> 1.117
PPCISelLowering.h updated: 1.35 -> 1.36
PPCInstrAltivec.td updated: 1.14 -> 1.15
PPCInstrInfo.td updated: 1.212 -> 1.213
---
Log message:

Use normal lvx for scalar_to_vector instead of lve*x.  They do the exact
same thing and we have a dag node for the former.


---
Diffs of the changes:  (+5 -20)

 PPCISelLowering.cpp |    6 ++----
 PPCISelLowering.h   |    8 --------
 PPCInstrAltivec.td  |   10 +++-------
 PPCInstrInfo.td     |    1 -
 4 files changed, 5 insertions(+), 20 deletions(-)


Index: llvm/lib/Target/PowerPC/PPCISelLowering.cpp
diff -u llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.116 llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.117
--- llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.116	Mon Mar 27 18:40:33 2006
+++ llvm/lib/Target/PowerPC/PPCISelLowering.cpp	Mon Mar 27 19:43:22 2006
@@ -222,7 +222,6 @@
   case PPCISD::STFIWX:        return "PPCISD::STFIWX";
   case PPCISD::VMADDFP:       return "PPCISD::VMADDFP";
   case PPCISD::VNMSUBFP:      return "PPCISD::VNMSUBFP";
-  case PPCISD::LVE_X:         return "PPCISD::LVE_X";
   case PPCISD::VPERM:         return "PPCISD::VPERM";
   case PPCISD::Hi:            return "PPCISD::Hi";
   case PPCISD::Lo:            return "PPCISD::Lo";
@@ -697,9 +696,8 @@
     // Store the input value into Value#0 of the stack slot.
     SDOperand Store = DAG.getNode(ISD::STORE, MVT::Other, DAG.getEntryNode(),
                                   Op.getOperand(0), FIdx,DAG.getSrcValue(NULL));
-    // LVE_X it out.
-    return DAG.getNode(PPCISD::LVE_X, Op.getValueType(), Store, FIdx, 
-                       DAG.getSrcValue(NULL));
+    // Load it out.
+    return DAG.getLoad(Op.getValueType(), Store, FIdx, DAG.getSrcValue(NULL));
   }
   case ISD::BUILD_VECTOR:
     // If this is a case we can't handle, return null and let the default


Index: llvm/lib/Target/PowerPC/PPCISelLowering.h
diff -u llvm/lib/Target/PowerPC/PPCISelLowering.h:1.35 llvm/lib/Target/PowerPC/PPCISelLowering.h:1.36
--- llvm/lib/Target/PowerPC/PPCISelLowering.h:1.35	Sun Mar 26 04:06:40 2006
+++ llvm/lib/Target/PowerPC/PPCISelLowering.h	Mon Mar 27 19:43:22 2006
@@ -48,14 +48,6 @@
       // three v4f32 operands and producing a v4f32 result.
       VMADDFP, VNMSUBFP,
       
-      /// LVE_X - The PPC LVE*X instructions.  The size of the element loaded is
-      /// the size of the element type of the vector result.  The element loaded
-      /// depends on the alignment of the input pointer.
-      ///
-      /// The first operand is a token chain, the second is the address to load
-      /// the third is the SRCVALUE node.
-      LVE_X,
-      
       /// VPERM - The PPC VPERM Instruction.
       ///
       VPERM,


Index: llvm/lib/Target/PowerPC/PPCInstrAltivec.td
diff -u llvm/lib/Target/PowerPC/PPCInstrAltivec.td:1.14 llvm/lib/Target/PowerPC/PPCInstrAltivec.td:1.15
--- llvm/lib/Target/PowerPC/PPCInstrAltivec.td:1.14	Mon Mar 27 18:40:33 2006
+++ llvm/lib/Target/PowerPC/PPCInstrAltivec.td	Mon Mar 27 19:43:22 2006
@@ -69,13 +69,13 @@
 let isLoad = 1, PPC970_Unit = 2 in {  // Loads.
 def LVEBX: XForm_1<31,   7, (ops VRRC:$vD, memrr:$src),
                    "lvebx $vD, $src", LdStGeneral,
-                   [(set VRRC:$vD, (v16i8 (PPClve_x xoaddr:$src)))]>;
+                   []>;
 def LVEHX: XForm_1<31,  39, (ops VRRC:$vD, memrr:$src),
                    "lvehx $vD, $src", LdStGeneral,
-                   [(set VRRC:$vD, (v8i16 (PPClve_x xoaddr:$src)))]>;
+                   []>;
 def LVEWX: XForm_1<31,  71, (ops VRRC:$vD, memrr:$src),
                    "lvewx $vD, $src", LdStGeneral,
-                   [(set VRRC:$vD, (v4f32 (PPClve_x xoaddr:$src)))]>;
+                   []>;
 def LVX  : XForm_1<31, 103, (ops VRRC:$vD, memrr:$src),
                    "lvx $vD, $src", LdStGeneral,
                    [(set VRRC:$vD, (v4f32 (load xoaddr:$src)))]>;
@@ -511,7 +511,3 @@
 def : Pat<(PPCvperm (v4i32 VRRC:$vA), VRRC:$vB, VRRC:$vC),
           (v4i32 (VPERM VRRC:$vA, VRRC:$vB, VRRC:$vC))>;
 
-def : Pat<(v4i32 (PPClve_x xoaddr:$src)),
-          (v4i32 (LVEWX xoaddr:$src))>;
-
-


Index: llvm/lib/Target/PowerPC/PPCInstrInfo.td
diff -u llvm/lib/Target/PowerPC/PPCInstrInfo.td:1.212 llvm/lib/Target/PowerPC/PPCInstrInfo.td:1.213
--- llvm/lib/Target/PowerPC/PPCInstrInfo.td:1.212	Sun Mar 26 04:06:40 2006
+++ llvm/lib/Target/PowerPC/PPCInstrInfo.td	Mon Mar 27 19:43:22 2006
@@ -53,7 +53,6 @@
 def PPCvmaddfp  : SDNode<"PPCISD::VMADDFP", SDTFPTernaryOp, []>;
 def PPCvnmsubfp : SDNode<"PPCISD::VNMSUBFP", SDTFPTernaryOp, []>;
 
-def PPClve_x    : SDNode<"PPCISD::LVE_X", SDTLoad, [SDNPHasChain]>;
 def PPCvperm    : SDNode<"PPCISD::VPERM", SDT_PPCvperm, []>;
 
 // These nodes represent the 32-bit PPC shifts that operate on 6-bit shift





From lattner at cs.uiuc.edu  Mon Mar 27 19:49:39 2006
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Mon, 27 Mar 2006 19:49:39 -0600
Subject: [llvm-commits] CVS: llvm/include/llvm/IntrinsicsPowerPC.td 
Message-ID: <200603280149.TAA12460@zion.cs.uiuc.edu>



Changes in directory llvm/include/llvm:

IntrinsicsPowerPC.td updated: 1.5 -> 1.6
---
Log message:

Add lvxl


---
Diffs of the changes:  (+2 -0)

 IntrinsicsPowerPC.td |    2 ++
 1 files changed, 2 insertions(+)


Index: llvm/include/llvm/IntrinsicsPowerPC.td
diff -u llvm/include/llvm/IntrinsicsPowerPC.td:1.5 llvm/include/llvm/IntrinsicsPowerPC.td:1.6
--- llvm/include/llvm/IntrinsicsPowerPC.td:1.5	Mon Mar 27 16:38:39 2006
+++ llvm/include/llvm/IntrinsicsPowerPC.td	Mon Mar 27 19:49:27 2006
@@ -15,6 +15,8 @@
   // Loads.
   def int_ppc_altivec_lvx : GCCBuiltin<"__builtin_altivec_lvx">,
               Intrinsic<[llvm_v4i32_ty, llvm_ptr_ty], [IntrReadMem]>;
+  def int_ppc_altivec_lvxl : GCCBuiltin<"__builtin_altivec_lvxl">,
+              Intrinsic<[llvm_v4i32_ty, llvm_ptr_ty], [IntrReadMem]>;
   def int_ppc_altivec_lvebx : GCCBuiltin<"__builtin_altivec_lvebx">,
               Intrinsic<[llvm_v16i8_ty, llvm_ptr_ty], [IntrReadMem]>;
   def int_ppc_altivec_lvehx : GCCBuiltin<"__builtin_altivec_lvehx">,





From evan.cheng at apple.com  Mon Mar 27 19:59:29 2006
From: evan.cheng at apple.com (Evan Cheng)
Date: Mon, 27 Mar 2006 19:59:29 -0600
Subject: [llvm-commits] CVS: llvm/include/llvm/CodeGen/ValueTypes.h 
Message-ID: <200603280159.TAA12528@zion.cs.uiuc.edu>



Changes in directory llvm/include/llvm/CodeGen:

ValueTypes.h updated: 1.26 -> 1.27
---
Log message:

getVectorTyppe(MVT::i64, 2) ==> MVT::v2i64.


---
Diffs of the changes:  (+3 -0)

 ValueTypes.h |    3 +++
 1 files changed, 3 insertions(+)


Index: llvm/include/llvm/CodeGen/ValueTypes.h
diff -u llvm/include/llvm/CodeGen/ValueTypes.h:1.26 llvm/include/llvm/CodeGen/ValueTypes.h:1.27
--- llvm/include/llvm/CodeGen/ValueTypes.h:1.26	Mon Mar 27 16:48:00 2006
+++ llvm/include/llvm/CodeGen/ValueTypes.h	Mon Mar 27 19:59:17 2006
@@ -136,6 +136,9 @@
       if (NumElements == 2)  return MVT::v2i32;
       if (NumElements == 4)  return MVT::v4i32;
         break;
+    case MVT::i64:
+      if (NumElements == 2)  return MVT::v2i64;
+      break;
     case MVT::f32:
       if (NumElements == 2)  return MVT::v2f32;
       if (NumElements == 4)  return MVT::v4f32;





From lattner at cs.uiuc.edu  Mon Mar 27 20:29:00 2006
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Mon, 27 Mar 2006 20:29:00 -0600
Subject: [llvm-commits] CVS: llvm/include/llvm/IntrinsicsPowerPC.td 
Message-ID: <200603280229.UAA12759@zion.cs.uiuc.edu>



Changes in directory llvm/include/llvm:

IntrinsicsPowerPC.td updated: 1.6 -> 1.7
---
Log message:

Add some more intrinsics: rotates, fp rounds, and random other fp instructions.


---
Diffs of the changes:  (+23 -1)

 IntrinsicsPowerPC.td |   24 +++++++++++++++++++++++-
 1 files changed, 23 insertions(+), 1 deletion(-)


Index: llvm/include/llvm/IntrinsicsPowerPC.td
diff -u llvm/include/llvm/IntrinsicsPowerPC.td:1.6 llvm/include/llvm/IntrinsicsPowerPC.td:1.7
--- llvm/include/llvm/IntrinsicsPowerPC.td:1.6	Mon Mar 27 19:49:27 2006
+++ llvm/include/llvm/IntrinsicsPowerPC.td	Mon Mar 27 20:28:48 2006
@@ -208,6 +208,15 @@
               Intrinsic<[llvm_v4f32_ty, llvm_v4i32_ty, llvm_int_ty],
                         [InstrNoMem]>;
 
+  def int_ppc_altivec_vrfim : GCCBuiltin<"__builtin_altivec_vrfim">,
+              Intrinsic<[llvm_v4f32_ty, llvm_v4f32_ty], [InstrNoMem]>;
+  def int_ppc_altivec_vrfin : GCCBuiltin<"__builtin_altivec_vrfin">,
+              Intrinsic<[llvm_v4f32_ty, llvm_v4f32_ty], [InstrNoMem]>;
+  def int_ppc_altivec_vrfip : GCCBuiltin<"__builtin_altivec_vrfip">,
+              Intrinsic<[llvm_v4f32_ty, llvm_v4f32_ty], [InstrNoMem]>;
+  def int_ppc_altivec_vrfiz : GCCBuiltin<"__builtin_altivec_vrfiz">,
+              Intrinsic<[llvm_v4f32_ty, llvm_v4f32_ty], [InstrNoMem]>;
+
   // Left Shifts.
   def int_ppc_altivec_vsldoi : GCCBuiltin<"__builtin_altivec_vsldoi_4si">,
               Intrinsic<[llvm_v4i32_ty, llvm_v4i32_ty, 
@@ -253,16 +262,29 @@
               Intrinsic<[llvm_v4i32_ty, llvm_v4i32_ty, llvm_v4i32_ty],
                         [InstrNoMem]>;
 
+  // Rotates.
+  def int_ppc_altivec_vrlb : GCCBuiltin<"__builtin_altivec_vrlb">,
+              Intrinsic<[llvm_v16i8_ty, llvm_v16i8_ty, llvm_v16i8_ty],
+                        [InstrNoMem]>;
+  def int_ppc_altivec_vrlh : GCCBuiltin<"__builtin_altivec_vrlh">,
+              Intrinsic<[llvm_v8i16_ty, llvm_v8i16_ty, llvm_v8i16_ty],
+                        [InstrNoMem]>;
+  def int_ppc_altivec_vrlw : GCCBuiltin<"__builtin_altivec_vrlw">,
+              Intrinsic<[llvm_v4i32_ty, llvm_v4i32_ty, llvm_v4i32_ty],
+                        [InstrNoMem]>;
 
   // Miscellaneous.
   def int_ppc_altivec_vsel : GCCBuiltin<"__builtin_altivec_vsel_4si">,
               Intrinsic<[llvm_v4i32_ty, llvm_v4i32_ty, 
                          llvm_v4i32_ty, llvm_v4i32_ty], [InstrNoMem]>;
 
+  def int_ppc_altivec_vexptefp : GCCBuiltin<"__builtin_altivec_vexptefp">,
+              Intrinsic<[llvm_v4f32_ty, llvm_v4f32_ty], [InstrNoMem]>;
+  def int_ppc_altivec_vlogefp : GCCBuiltin<"__builtin_altivec_vlogefp">,
+              Intrinsic<[llvm_v4f32_ty, llvm_v4f32_ty], [InstrNoMem]>;
   def int_ppc_altivec_vrefp : GCCBuiltin<"__builtin_altivec_vrefp">,
               Intrinsic<[llvm_v4f32_ty, llvm_v4f32_ty], [InstrNoMem]>;
   def int_ppc_altivec_vrsqrtefp : GCCBuiltin<"__builtin_altivec_vrsqrtefp">,
               Intrinsic<[llvm_v4f32_ty, llvm_v4f32_ty], [InstrNoMem]>;
-  
 }
 





From lattner at cs.uiuc.edu  Mon Mar 27 20:29:49 2006
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Mon, 27 Mar 2006 20:29:49 -0600
Subject: [llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCInstrAltivec.td
	README_ALTIVEC.txt 
Message-ID: <200603280229.UAA12818@zion.cs.uiuc.edu>



Changes in directory llvm/lib/Target/PowerPC:

PPCInstrAltivec.td updated: 1.15 -> 1.16
README_ALTIVEC.txt updated: 1.2 -> 1.3
---
Log message:

implement a bunch more intrinsics.


---
Diffs of the changes:  (+108 -23)

 PPCInstrAltivec.td |  120 +++++++++++++++++++++++++++++++++++++++++++++++------
 README_ALTIVEC.txt |   11 ----
 2 files changed, 108 insertions(+), 23 deletions(-)


Index: llvm/lib/Target/PowerPC/PPCInstrAltivec.td
diff -u llvm/lib/Target/PowerPC/PPCInstrAltivec.td:1.15 llvm/lib/Target/PowerPC/PPCInstrAltivec.td:1.16
--- llvm/lib/Target/PowerPC/PPCInstrAltivec.td:1.15	Mon Mar 27 19:43:22 2006
+++ llvm/lib/Target/PowerPC/PPCInstrAltivec.td	Mon Mar 27 20:29:37 2006
@@ -69,16 +69,19 @@
 let isLoad = 1, PPC970_Unit = 2 in {  // Loads.
 def LVEBX: XForm_1<31,   7, (ops VRRC:$vD, memrr:$src),
                    "lvebx $vD, $src", LdStGeneral,
-                   []>;
+                   [(set VRRC:$vD, (int_ppc_altivec_lvebx xoaddr:$src))]>;
 def LVEHX: XForm_1<31,  39, (ops VRRC:$vD, memrr:$src),
                    "lvehx $vD, $src", LdStGeneral,
-                   []>;
+                   [(set VRRC:$vD, (int_ppc_altivec_lvehx xoaddr:$src))]>;
 def LVEWX: XForm_1<31,  71, (ops VRRC:$vD, memrr:$src),
                    "lvewx $vD, $src", LdStGeneral,
-                   []>;
+                   [(set VRRC:$vD, (int_ppc_altivec_lvewx xoaddr:$src))]>;
 def LVX  : XForm_1<31, 103, (ops VRRC:$vD, memrr:$src),
                    "lvx $vD, $src", LdStGeneral,
-                   [(set VRRC:$vD, (v4f32 (load xoaddr:$src)))]>;
+                   [(set VRRC:$vD, (int_ppc_altivec_lvx xoaddr:$src))]>;
+def LVXL : XForm_1<31, 359, (ops VRRC:$vD, memrr:$src),
+                   "lvxl $vD, $src", LdStGeneral,
+                   [(set VRRC:$vD, (int_ppc_altivec_lvxl xoaddr:$src))]>;
 }
 
 def LVSL : XForm_1<31,   6, (ops VRRC:$vD,  GPRC:$base, GPRC:$rA),
@@ -100,7 +103,10 @@
                    [(int_ppc_altivec_stvewx VRRC:$rS, xoaddr:$dst)]>;
 def STVX  : XForm_8<31, 231, (ops VRRC:$rS, memrr:$dst),
                    "stvx $rS, $dst", LdStGeneral,
-                   [(store (v4f32 VRRC:$rS), xoaddr:$dst)]>;
+                   [(int_ppc_altivec_stvx VRRC:$rS, xoaddr:$dst)]>;
+def STVXL : XForm_8<31, 487, (ops VRRC:$rS, memrr:$dst),
+                   "stvxl $rS, $dst", LdStGeneral,
+                   [(int_ppc_altivec_stvxl VRRC:$rS, xoaddr:$dst)]>;
 }
 
 let PPC970_Unit = 5 in {  // VALU Operations.
@@ -197,10 +203,10 @@
                       []>;
 def VEXPTEFP : VXForm_2<394, (ops VRRC:$vD, VRRC:$vB),
                         "vexptefp $vD, $vB", VecFP,
-                        []>;
+                        [(set VRRC:$vD, (int_ppc_altivec_vexptefp VRRC:$vB))]>;
 def VLOGEFP  : VXForm_2<458, (ops VRRC:$vD, VRRC:$vB),
                         "vlogefp $vD, $vB", VecFP,
-                        []>;
+                        [(set VRRC:$vD, (int_ppc_altivec_vlogefp VRRC:$vB))]>;
 def VMAXFP : VXForm_1<1034, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
                       "vmaxfp $vD, $vA, $vB", VecFP,
                       []>;
@@ -209,19 +215,19 @@
                       []>;
 def VREFP  : VXForm_2<266, (ops VRRC:$vD, VRRC:$vB),
                       "vrefp $vD, $vB", VecFP,
-                      []>;
+                      [(set VRRC:$vD, (int_ppc_altivec_vrefp VRRC:$vB))]>;
 def VRFIM  : VXForm_2<714, (ops VRRC:$vD, VRRC:$vB),
                       "vrfim $vD, $vB", VecFP,
-                      []>;
+                      [(set VRRC:$vD, (int_ppc_altivec_vrfim VRRC:$vB))]>;
 def VRFIN  : VXForm_2<522, (ops VRRC:$vD, VRRC:$vB),
                       "vrfin $vD, $vB", VecFP,
-                      []>;
+                      [(set VRRC:$vD, (int_ppc_altivec_vrfin VRRC:$vB))]>;
 def VRFIP  : VXForm_2<650, (ops VRRC:$vD, VRRC:$vB),
                       "vrfip $vD, $vB", VecFP,
-                      []>;
+                      [(set VRRC:$vD, (int_ppc_altivec_vrfip VRRC:$vB))]>;
 def VRFIZ  : VXForm_2<586, (ops VRRC:$vD, VRRC:$vB),
                       "vrfiz $vD, $vB", VecFP,
-                      []>;
+                      [(set VRRC:$vD, (int_ppc_altivec_vrfiz VRRC:$vB))]>;
 def VRSQRTEFP : VXForm_2<330, (ops VRRC:$vD, VRRC:$vB),
                          "vrsqrtefp $vD, $vB", VecFP,
                          [(set VRRC:$vD,(int_ppc_altivec_vrsqrtefp VRRC:$vB))]>;
@@ -268,7 +274,28 @@
                        "vsubuws $vD, $vA, $vB", VecFP,
                        [(set VRRC:$vD,
                              (int_ppc_altivec_vsubuws VRRC:$vA, VRRC:$vB))]>;
-                      
+
+def VSUMSWS : VXForm_1<1928, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
+                       "vsumsws $vD, $vA, $vB", VecFP,
+                       [(set VRRC:$vD,
+                             (int_ppc_altivec_vsumsws VRRC:$vA, VRRC:$vB))]>;
+def VSUM2SWS: VXForm_1<1672, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
+                       "vsum2sws $vD, $vA, $vB", VecFP,
+                       [(set VRRC:$vD,
+                             (int_ppc_altivec_vsum2sws VRRC:$vA, VRRC:$vB))]>;
+def VSUM4SBS: VXForm_1<1672, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
+                       "vsum4sbs $vD, $vA, $vB", VecFP,
+                       [(set VRRC:$vD,
+                             (int_ppc_altivec_vsum4sbs VRRC:$vA, VRRC:$vB))]>;
+def VSUM4SHS: VXForm_1<1608, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
+                       "vsum4shs $vD, $vA, $vB", VecFP,
+                       [(set VRRC:$vD,
+                             (int_ppc_altivec_vsum4shs VRRC:$vA, VRRC:$vB))]>;
+def VSUM4UBS: VXForm_1<1544, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
+                       "vsum4ubs $vD, $vA, $vB", VecFP,
+                       [(set VRRC:$vD,
+                             (int_ppc_altivec_vsum4ubs VRRC:$vA, VRRC:$vB))]>;
+
 def VNOR : VXForm_1<1284, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
                     "vnor $vD, $vA, $vB", VecFP,
                     [(set VRRC:$vD, (vnot (or (v4i32 VRRC:$vA), VRRC:$vB)))]>;
@@ -279,6 +306,36 @@
                       "vxor $vD, $vA, $vB", VecFP,
                       [(set VRRC:$vD, (xor (v4i32 VRRC:$vA), VRRC:$vB))]>;
 
+def VRLB   : VXForm_1<4, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
+                      "vrlb $vD, $vA, $vB", VecFP,
+                      [(set VRRC:$vD,
+                             (int_ppc_altivec_vrlb VRRC:$vA, VRRC:$vB))]>;
+def VRLH   : VXForm_1<68, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
+                      "vrlh $vD, $vA, $vB", VecFP,
+                      [(set VRRC:$vD,
+                             (int_ppc_altivec_vrlh VRRC:$vA, VRRC:$vB))]>;
+def VRLW   : VXForm_1<132, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
+                      "vrlw $vD, $vA, $vB", VecFP,
+                      [(set VRRC:$vD,
+                             (int_ppc_altivec_vrlw VRRC:$vA, VRRC:$vB))]>;
+
+def VSLO   : VXForm_1<1036, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
+                      "vslo $vD, $vA, $vB", VecFP,
+                      [(set VRRC:$vD,
+                             (int_ppc_altivec_vslo VRRC:$vA, VRRC:$vB))]>;
+def VSLB   : VXForm_1<260, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
+                      "vslb $vD, $vA, $vB", VecFP,
+                      [(set VRRC:$vD,
+                             (int_ppc_altivec_vslb VRRC:$vA, VRRC:$vB))]>;
+def VSLH   : VXForm_1<324, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
+                      "vslh $vD, $vA, $vB", VecFP,
+                      [(set VRRC:$vD,
+                             (int_ppc_altivec_vslh VRRC:$vA, VRRC:$vB))]>;
+def VSLW   : VXForm_1<388, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
+                      "vslw $vD, $vA, $vB", VecFP,
+                      [(set VRRC:$vD,
+                             (int_ppc_altivec_vslw VRRC:$vA, VRRC:$vB))]>;
+
 def VSPLTB : VXForm_1<524, (ops VRRC:$vD, u5imm:$UIMM, VRRC:$vB),
                       "vspltb $vD, $vB, $UIMM", VecPerm,
                       []>;
@@ -290,6 +347,40 @@
                       [(set VRRC:$vD, (vector_shuffle (v4f32 VRRC:$vB), (undef),
                                       VSPLT_shuffle_mask:$UIMM))]>;
 
+def VSR    : VXForm_1<708, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
+                      "vsr $vD, $vA, $vB", VecFP,
+                      [(set VRRC:$vD,
+                             (int_ppc_altivec_vsr VRRC:$vA, VRRC:$vB))]>;
+def VSRO   : VXForm_1<1100, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
+                      "vsro $vD, $vA, $vB", VecFP,
+                      [(set VRRC:$vD,
+                             (int_ppc_altivec_vsro VRRC:$vA, VRRC:$vB))]>;
+def VSRAB  : VXForm_1<772, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
+                      "vsrab $vD, $vA, $vB", VecFP,
+                      [(set VRRC:$vD,
+                             (int_ppc_altivec_vsrab VRRC:$vA, VRRC:$vB))]>;
+def VSRAH  : VXForm_1<836, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
+                      "vsrah $vD, $vA, $vB", VecFP,
+                      [(set VRRC:$vD,
+                             (int_ppc_altivec_vsrah VRRC:$vA, VRRC:$vB))]>;
+def VSRAW  : VXForm_1<900, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
+                      "vsraw $vD, $vA, $vB", VecFP,
+                      [(set VRRC:$vD,
+                             (int_ppc_altivec_vsraw VRRC:$vA, VRRC:$vB))]>;
+def VSRB   : VXForm_1<516, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
+                      "vsrb $vD, $vA, $vB", VecFP,
+                      [(set VRRC:$vD,
+                             (int_ppc_altivec_vsrb VRRC:$vA, VRRC:$vB))]>;
+def VSRH   : VXForm_1<580, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
+                      "vsrh $vD, $vA, $vB", VecFP,
+                      [(set VRRC:$vD,
+                             (int_ppc_altivec_vsrh VRRC:$vA, VRRC:$vB))]>;
+def VSRW   : VXForm_1<644, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
+                      "vsrw $vD, $vA, $vB", VecFP,
+                      [(set VRRC:$vD,
+                             (int_ppc_altivec_vsrw VRRC:$vA, VRRC:$vB))]>;
+
+
 def VSPLTISB : VXForm_3<780, (ops VRRC:$vD, s5imm:$SIMM),
                        "vspltisb $vD, $SIMM", VecPerm,
                        [(set VRRC:$vD, (v4f32 vecspltisb:$SIMM))]>;
@@ -436,6 +527,7 @@
 def : Pat<(v16i8 (load xoaddr:$src)), (v16i8 (LVX xoaddr:$src))>;
 def : Pat<(v8i16 (load xoaddr:$src)), (v8i16 (LVX xoaddr:$src))>;
 def : Pat<(v4i32 (load xoaddr:$src)), (v4i32 (LVX xoaddr:$src))>;
+def : Pat<(v4f32 (load xoaddr:$src)), (v4f32 (LVX xoaddr:$src))>;
 
 // Stores.
 def : Pat<(store (v16i8 VRRC:$rS), xoaddr:$dst),
@@ -444,6 +536,8 @@
           (STVX (v8i16 VRRC:$rS), xoaddr:$dst)>;
 def : Pat<(store (v4i32 VRRC:$rS), xoaddr:$dst),
           (STVX (v4i32 VRRC:$rS), xoaddr:$dst)>;
+def : Pat<(store (v4f32 VRRC:$rS), xoaddr:$dst),
+          (STVX (v4f32 VRRC:$rS), xoaddr:$dst)>;
 
 // Bit conversions.
 def : Pat<(v16i8 (bitconvert (v8i16 VRRC:$src))), (v16i8 VRRC:$src)>;


Index: llvm/lib/Target/PowerPC/README_ALTIVEC.txt
diff -u llvm/lib/Target/PowerPC/README_ALTIVEC.txt:1.2 llvm/lib/Target/PowerPC/README_ALTIVEC.txt:1.3
--- llvm/lib/Target/PowerPC/README_ALTIVEC.txt:1.2	Mon Mar 27 01:41:00 2006
+++ llvm/lib/Target/PowerPC/README_ALTIVEC.txt	Mon Mar 27 20:29:37 2006
@@ -50,14 +50,9 @@
 Missing intrinsics:
 
 ds*
-lve*
-lvs*
-lvx*
+lvsl/lvsr
 mf*
-st*
 vavg*
-vexptefp
-vlogefp
 vmax*
 vmhaddshs/vmhraddshs
 vmin*
@@ -67,11 +62,7 @@
 vmul*
 vperm
 vpk*
-vr*
 vsel (some aliases only accessible using builtins)
-vsl* (except vsldoi)
-vsr*
-vsum*
 vup*
 
 //===----------------------------------------------------------------------===//





From evan.cheng at apple.com  Mon Mar 27 20:43:38 2006
From: evan.cheng at apple.com (Evan Cheng)
Date: Mon, 27 Mar 2006 20:43:38 -0600
Subject: [llvm-commits] CVS: llvm/lib/Target/X86/X86ISelLowering.cpp
	X86ISelLowering.h X86InstrSSE.td 
Message-ID: <200603280243.UAA12878@zion.cs.uiuc.edu>



Changes in directory llvm/lib/Target/X86:

X86ISelLowering.cpp updated: 1.136 -> 1.137
X86ISelLowering.h updated: 1.45 -> 1.46
X86InstrSSE.td updated: 1.35 -> 1.36
---
Log message:

- Clean up / consoladate various shuffle masks.
- Some misc. bug fixes.
- Use MOVHPDrm to load from m64 to upper half of a XMM register.


---
Diffs of the changes:  (+124 -96)

 X86ISelLowering.cpp |   58 ++++++++------------
 X86ISelLowering.h   |   13 +---
 X86InstrSSE.td      |  149 +++++++++++++++++++++++++++++++++-------------------
 3 files changed, 124 insertions(+), 96 deletions(-)


Index: llvm/lib/Target/X86/X86ISelLowering.cpp
diff -u llvm/lib/Target/X86/X86ISelLowering.cpp:1.136 llvm/lib/Target/X86/X86ISelLowering.cpp:1.137
--- llvm/lib/Target/X86/X86ISelLowering.cpp:1.136	Mon Mar 27 18:39:58 2006
+++ llvm/lib/Target/X86/X86ISelLowering.cpp	Mon Mar 27 20:43:26 2006
@@ -1451,24 +1451,6 @@
   return true;
 }
 
-/// isMOVLHPSorUNPCKLPDMask - Return true if the specified VECTOR_SHUFFLE
-/// operand specifies a shuffle of elements that is suitable for input to
-/// MOVLHPS or UNPCKLPD.
-bool X86::isMOVLHPSorUNPCKLPDMask(SDNode *N) {
-  assert(N->getOpcode() == ISD::BUILD_VECTOR);
-
-  if (N->getNumOperands() != 2)
-    return false;
-
-  // Expect bit 0 == 0, bit1 == 2
-  SDOperand Bit0 = N->getOperand(0);
-  SDOperand Bit1 = N->getOperand(1);
-  assert(isa<ConstantSDNode>(Bit0) && isa<ConstantSDNode>(Bit1) &&
-         "Invalid VECTOR_SHUFFLE mask!");
-  return (cast<ConstantSDNode>(Bit0)->getValue() == 0 && 
-          cast<ConstantSDNode>(Bit1)->getValue() == 2);
-}
-
 /// isMOVHLPSMask - Return true if the specified VECTOR_SHUFFLE operand
 /// specifies a shuffle of elements that is suitable for input to MOVHLPS.
 bool X86::isMOVHLPSMask(SDNode *N) {
@@ -1477,7 +1459,7 @@
   if (N->getNumOperands() != 2)
     return false;
 
-  // Expect bit 0 == 0, bit1 == 3
+  // Expect bit 0 == 1, bit1 == 1
   SDOperand Bit0 = N->getOperand(0);
   SDOperand Bit1 = N->getOperand(1);
   assert(isa<ConstantSDNode>(Bit0) && isa<ConstantSDNode>(Bit1) &&
@@ -1486,26 +1468,32 @@
           cast<ConstantSDNode>(Bit1)->getValue() == 3);
 }
 
-/// isUNPCKHPDMask - Return true if the specified VECTOR_SHUFFLE operand
-/// specifies a shuffle of elements that is suitable for input to UNPCKHPD.
-bool X86::isUNPCKHPDMask(SDNode *N) {
+/// isUNPCKLMask - Return true if the specified VECTOR_SHUFFLE operand
+/// specifies a shuffle of elements that is suitable for input to UNPCKL.
+bool X86::isUNPCKLMask(SDNode *N) {
   assert(N->getOpcode() == ISD::BUILD_VECTOR);
 
-  if (N->getNumOperands() != 2)
+  unsigned NumElems = N->getNumOperands();
+  if (NumElems != 2 && NumElems != 4 && NumElems != 8 && NumElems != 16)
     return false;
 
-  // Expect bit 0 == 1, bit1 == 3
-  SDOperand Bit0 = N->getOperand(0);
-  SDOperand Bit1 = N->getOperand(1);
-  assert(isa<ConstantSDNode>(Bit0) && isa<ConstantSDNode>(Bit1) &&
-         "Invalid VECTOR_SHUFFLE mask!");
-  return (cast<ConstantSDNode>(Bit0)->getValue() == 1 && 
-          cast<ConstantSDNode>(Bit1)->getValue() == 3);
+  for (unsigned i = 0, j = 0; i != NumElems; i += 2, ++j) {
+    SDOperand BitI  = N->getOperand(i);
+    SDOperand BitI1 = N->getOperand(i+1);
+    assert(isa<ConstantSDNode>(BitI) && isa<ConstantSDNode>(BitI1) &&
+           "Invalid VECTOR_SHUFFLE mask!");
+    if (cast<ConstantSDNode>(BitI)->getValue()  != j)
+      return false;
+    if (cast<ConstantSDNode>(BitI1)->getValue() != j + NumElems)
+      return false;
+  }
+
+  return true;
 }
 
-/// isUNPCKLMask - Return true if the specified VECTOR_SHUFFLE operand
-/// specifies a shuffle of elements that is suitable for input to UNPCKL.
-bool X86::isUNPCKLMask(SDNode *N) {
+/// isUNPCKHMask - Return true if the specified VECTOR_SHUFFLE operand
+/// specifies a shuffle of elements that is suitable for input to UNPCKH.
+bool X86::isUNPCKHMask(SDNode *N) {
   assert(N->getOpcode() == ISD::BUILD_VECTOR);
 
   unsigned NumElems = N->getNumOperands();
@@ -1517,9 +1505,9 @@
     SDOperand BitI1 = N->getOperand(i+1);
     assert(isa<ConstantSDNode>(BitI) && isa<ConstantSDNode>(BitI1) &&
            "Invalid VECTOR_SHUFFLE mask!");
-    if (cast<ConstantSDNode>(BitI)->getValue()  != j)
+    if (cast<ConstantSDNode>(BitI)->getValue()  != j + NumElems/2)
       return false;
-    if (cast<ConstantSDNode>(BitI1)->getValue() != j + NumElems)
+    if (cast<ConstantSDNode>(BitI1)->getValue() != j + NumElems/2 + NumElems)
       return false;
   }
 


Index: llvm/lib/Target/X86/X86ISelLowering.h
diff -u llvm/lib/Target/X86/X86ISelLowering.h:1.45 llvm/lib/Target/X86/X86ISelLowering.h:1.46
--- llvm/lib/Target/X86/X86ISelLowering.h:1.45	Mon Mar 27 18:39:58 2006
+++ llvm/lib/Target/X86/X86ISelLowering.h	Mon Mar 27 20:43:26 2006
@@ -188,23 +188,18 @@
    /// specifies a shuffle of elements that is suitable for input to SHUFP*.
    bool isSHUFPMask(SDNode *N);
 
-   /// isMOVLHPSorUNPCKLPDMask - Return true if the specified VECTOR_SHUFFLE
-   /// operand specifies a shuffle of elements that is suitable for input to
-   /// MOVLHPS or UNPCKLPD.
-   bool isMOVLHPSorUNPCKLPDMask(SDNode *N);
-
    /// isMOVHLPSMask - Return true if the specified VECTOR_SHUFFLE operand
    /// specifies a shuffle of elements that is suitable for input to MOVHLPS.
    bool isMOVHLPSMask(SDNode *N);
 
-   /// isUNPCKHPDMask - Return true if the specified VECTOR_SHUFFLE operand
-   /// specifies a shuffle of elements that is suitable for input to UNPCKHPD.
-   bool isUNPCKHPDMask(SDNode *N);
-
    /// isUNPCKLMask - Return true if the specified VECTOR_SHUFFLE operand
    /// specifies a shuffle of elements that is suitable for input to UNPCKL.
    bool isUNPCKLMask(SDNode *N);
 
+   /// isUNPCKHMask - Return true if the specified VECTOR_SHUFFLE operand
+   /// specifies a shuffle of elements that is suitable for input to UNPCKH.
+   bool isUNPCKHMask(SDNode *N);
+
    /// isSplatMask - Return true if the specified VECTOR_SHUFFLE operand
    /// specifies a splat of a single element.
    bool isSplatMask(SDNode *N);


Index: llvm/lib/Target/X86/X86InstrSSE.td
diff -u llvm/lib/Target/X86/X86InstrSSE.td:1.35 llvm/lib/Target/X86/X86InstrSSE.td:1.36
--- llvm/lib/Target/X86/X86InstrSSE.td:1.35	Mon Mar 27 18:39:58 2006
+++ llvm/lib/Target/X86/X86InstrSSE.td	Mon Mar 27 20:43:26 2006
@@ -63,22 +63,18 @@
   return X86::isSplatMask(N);
 }]>;
 
-def MOVLHPSorUNPCKLPD_shuffle_mask : PatLeaf<(build_vector), [{
-  return X86::isMOVLHPSorUNPCKLPDMask(N);
-}], SHUFFLE_get_shuf_imm>;
-
 def MOVHLPS_shuffle_mask : PatLeaf<(build_vector), [{
   return X86::isMOVHLPSMask(N);
-}], SHUFFLE_get_shuf_imm>;
-
-def UNPCKHPD_shuffle_mask : PatLeaf<(build_vector), [{
-  return X86::isUNPCKHPDMask(N);
-}], SHUFFLE_get_shuf_imm>;
+}]>;
 
 def UNPCKL_shuffle_mask : PatLeaf<(build_vector), [{
   return X86::isUNPCKLMask(N);
 }]>;
 
+def UNPCKH_shuffle_mask : PatLeaf<(build_vector), [{
+  return X86::isUNPCKHMask(N);
+}]>;
+
 // Only use PSHUF if it is not a splat.
 def PSHUFD_shuffle_mask : PatLeaf<(build_vector), [{
   return !X86::isSplatMask(N) && X86::isPSHUFDMask(N);
@@ -172,7 +168,7 @@
 def MOVSD128rm : SDI<0x10, MRMSrcMem, (ops VR128:$dst, f64mem:$src),
                      "movsd {$src, $dst|$dst, $src}",
                      [(set VR128:$dst, 
-                       (v4f32 (scalar_to_vector (loadf64 addr:$src))))]>;
+                       (v2f64 (scalar_to_vector (loadf64 addr:$src))))]>;
 
 
 // Conversion instructions
@@ -476,21 +472,34 @@
 def MOVLPDmr : PDI<0x13, MRMDestMem, (ops f64mem:$dst, VR128:$src),
                    "movlpd {$src, $dst|$dst, $src}", []>;
 
-def MOVHPSrm : PSI<0x16, MRMSrcMem, (ops VR128:$dst, f64mem:$src),
-                   "movhps {$src, $dst|$dst, $src}", []>;
+let isTwoAddress = 1 in {
+def MOVHPSrm : PSI<0x16, MRMSrcMem, (ops VR128:$dst, VR128:$src1, f64mem:$src2),
+                   "movhps {$src2, $dst|$dst, $src2}", []>;
+def MOVHPDrm : PDI<0x16, MRMSrcMem, (ops VR128:$dst, VR128:$src1, f64mem:$src2),
+                   "movhpd {$src2, $dst|$dst, $src2}",
+                   [(set VR128:$dst, 
+                     (v2f64 (vector_shuffle VR128:$src1,
+                             (scalar_to_vector (loadf64 addr:$src2)),
+                             UNPCKL_shuffle_mask)))]>;
+}
+
 def MOVHPSmr : PSI<0x17, MRMDestMem, (ops f64mem:$dst, VR128:$src),
                    "movhps {$src, $dst|$dst, $src}", []>;
-def MOVHPDrm : PDI<0x16, MRMSrcMem, (ops VR128:$dst, f64mem:$src),
-                   "movhpd {$src, $dst|$dst, $src}", []>;
 def MOVHPDmr : PDI<0x17, MRMDestMem, (ops f64mem:$dst, VR128:$src),
                    "movhpd {$src, $dst|$dst, $src}", []>;
 
 let isTwoAddress = 1 in {
 def MOVLHPSrr : PSI<0x16, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
-                    "movlhps {$src2, $dst|$dst, $src2}", []>;
+                    "movlhps {$src2, $dst|$dst, $src2}",
+                    [(set VR128:$dst,
+                      (v2f64 (vector_shuffle VR128:$src1, VR128:$src2,
+                              UNPCKL_shuffle_mask)))]>;
 
 def MOVHLPSrr : PSI<0x12, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
-                    "movlhps {$src2, $dst|$dst, $src2}", []>;
+                    "movlhps {$src2, $dst|$dst, $src2}",
+                    [(set VR128:$dst,
+                      (v2f64 (vector_shuffle VR128:$src1, VR128:$src2,
+                              MOVHLPS_shuffle_mask)))]>;
 }
 
 def MOVMSKPSrr : PSI<0x50, MRMSrcReg, (ops R32:$dst, VR128:$src),
@@ -784,16 +793,29 @@
 
 def UNPCKHPSrr : PSI<0x15, MRMSrcReg, 
                     (ops VR128:$dst, VR128:$src1, VR128:$src2),
-                    "unpckhps {$src2, $dst|$dst, $src2}", []>;
+                    "unpckhps {$src2, $dst|$dst, $src2}",
+                    [(set VR128:$dst,
+                      (v4f32 (vector_shuffle VR128:$src1, VR128:$src2,
+                              UNPCKH_shuffle_mask)))]>;
 def UNPCKHPSrm : PSI<0x15, MRMSrcMem, 
                     (ops VR128:$dst, VR128:$src1, f128mem:$src2),
-                    "unpckhps {$src2, $dst|$dst, $src2}", []>;
+                    "unpckhps {$src2, $dst|$dst, $src2}",
+                    [(set VR128:$dst,
+                      (v4f32 (vector_shuffle VR128:$src1, (load addr:$src2),
+                              UNPCKH_shuffle_mask)))]>;
 def UNPCKHPDrr : PDI<0x15, MRMSrcReg, 
                     (ops VR128:$dst, VR128:$src1, VR128:$src2),
-                    "unpckhpd {$src2, $dst|$dst, $src2}", []>;
+                    "unpckhpd {$src2, $dst|$dst, $src2}",
+                    [(set VR128:$dst,
+                      (v2f64 (vector_shuffle VR128:$src1, VR128:$src2,
+                              UNPCKH_shuffle_mask)))]>;
 def UNPCKHPDrm : PDI<0x15, MRMSrcMem, 
                     (ops VR128:$dst, VR128:$src1, f128mem:$src2),
-                    "unpckhpd {$src2, $dst|$dst, $src2}", []>;
+                    "unpckhpd {$src2, $dst|$dst, $src2}",
+                    [(set VR128:$dst,
+                      (v2f64 (vector_shuffle VR128:$src1, (load addr:$src2),
+                              UNPCKH_shuffle_mask)))]>;
+
 def UNPCKLPSrr : PSI<0x14, MRMSrcReg, 
                     (ops VR128:$dst, VR128:$src1, VR128:$src2),
                     "unpcklps {$src2, $dst|$dst, $src2}",
@@ -808,10 +830,16 @@
                               UNPCKL_shuffle_mask)))]>;
 def UNPCKLPDrr : PDI<0x14, MRMSrcReg, 
                     (ops VR128:$dst, VR128:$src1, VR128:$src2),
-                    "unpcklpd {$src2, $dst|$dst, $src2}", []>;
+                    "unpcklpd {$src2, $dst|$dst, $src2}",
+                    [(set VR128:$dst,
+                      (v2f64 (vector_shuffle VR128:$src1, VR128:$src2,
+                              UNPCKL_shuffle_mask)))]>;
 def UNPCKLPDrm : PDI<0x14, MRMSrcMem, 
                     (ops VR128:$dst, VR128:$src1, f128mem:$src2),
-                    "unpcklpd {$src2, $dst|$dst, $src2}", []>;
+                    "unpcklpd {$src2, $dst|$dst, $src2}",
+                    [(set VR128:$dst,
+                      (v2f64 (vector_shuffle VR128:$src1, (load addr:$src2),
+                              UNPCKL_shuffle_mask)))]>;
 }
 
 //===----------------------------------------------------------------------===//
@@ -940,35 +968,65 @@
                                 UNPCKL_shuffle_mask)))]>;
 def PUNPCKLQDQrr : PDI<0x6C, MRMSrcReg, 
                        (ops VR128:$dst, VR128:$src1, VR128:$src2),
-                       "punpcklqdq {$src2, $dst|$dst, $src2}", []>;
+                       "punpcklqdq {$src2, $dst|$dst, $src2}",
+                      [(set VR128:$dst,
+                        (v2i64 (vector_shuffle VR128:$src1, VR128:$src2,
+                                UNPCKL_shuffle_mask)))]>;
 def PUNPCKLQDQrm : PDI<0x6C, MRMSrcMem, 
                        (ops VR128:$dst, VR128:$src1, i128mem:$src2),
-                       "punpcklqdq {$src2, $dst|$dst, $src2}", []>;
+                       "punpcklqdq {$src2, $dst|$dst, $src2}",
+                      [(set VR128:$dst,
+                        (v2i64 (vector_shuffle VR128:$src1, (load addr:$src2),
+                                UNPCKL_shuffle_mask)))]>;
 
 def PUNPCKHBWrr : PDI<0x68, MRMSrcReg, 
                       (ops VR128:$dst, VR128:$src1, VR128:$src2),
-                      "punpckhbw {$src2, $dst|$dst, $src2}", []>;
+                      "punpckhbw {$src2, $dst|$dst, $src2}",
+                      [(set VR128:$dst,
+                        (v16i8 (vector_shuffle VR128:$src1, VR128:$src2,
+                                UNPCKH_shuffle_mask)))]>;
 def PUNPCKHBWrm : PDI<0x68, MRMSrcMem, 
                       (ops VR128:$dst, VR128:$src1, i128mem:$src2),
-                      "punpckhbw {$src2, $dst|$dst, $src2}", []>;
+                      "punpckhbw {$src2, $dst|$dst, $src2}",
+                      [(set VR128:$dst,
+                        (v16i8 (vector_shuffle VR128:$src1, (load addr:$src2),
+                                UNPCKH_shuffle_mask)))]>;
 def PUNPCKHWDrr : PDI<0x69, MRMSrcReg, 
                       (ops VR128:$dst, VR128:$src1, VR128:$src2),
-                      "punpckhwd {$src2, $dst|$dst, $src2}", []>;
+                      "punpckhwd {$src2, $dst|$dst, $src2}",
+                      [(set VR128:$dst,
+                        (v8i16 (vector_shuffle VR128:$src1, VR128:$src2,
+                                UNPCKH_shuffle_mask)))]>;
 def PUNPCKHWDrm : PDI<0x69, MRMSrcMem, 
                       (ops VR128:$dst, VR128:$src1, i128mem:$src2),
-                      "punpckhwd {$src2, $dst|$dst, $src2}", []>;
+                      "punpckhwd {$src2, $dst|$dst, $src2}",
+                      [(set VR128:$dst,
+                        (v8i16 (vector_shuffle VR128:$src1, (load addr:$src2),
+                                UNPCKH_shuffle_mask)))]>;
 def PUNPCKHDQrr : PDI<0x6A, MRMSrcReg, 
                       (ops VR128:$dst, VR128:$src1, VR128:$src2),
-                      "punpckhdq {$src2, $dst|$dst, $src2}", []>;
+                      "punpckhdq {$src2, $dst|$dst, $src2}",
+                      [(set VR128:$dst,
+                        (v4i32 (vector_shuffle VR128:$src1, VR128:$src2,
+                                UNPCKH_shuffle_mask)))]>;
 def PUNPCKHDQrm : PDI<0x6A, MRMSrcMem, 
                       (ops VR128:$dst, VR128:$src1, i128mem:$src2),
-                      "punpckhdq {$src2, $dst|$dst, $src2}", []>;
+                      "punpckhdq {$src2, $dst|$dst, $src2}",
+                      [(set VR128:$dst,
+                        (v4i32 (vector_shuffle VR128:$src1, (load addr:$src2),
+                                UNPCKH_shuffle_mask)))]>;
 def PUNPCKHQDQrr : PDI<0x6D, MRMSrcReg, 
                        (ops VR128:$dst, VR128:$src1, VR128:$src2),
-                       "punpckhdq {$src2, $dst|$dst, $src2}", []>;
+                       "punpckhdq {$src2, $dst|$dst, $src2}",
+                      [(set VR128:$dst,
+                        (v2i64 (vector_shuffle VR128:$src1, VR128:$src2,
+                                UNPCKH_shuffle_mask)))]>;
 def PUNPCKHQDQrm : PDI<0x6D, MRMSrcMem, 
                       (ops VR128:$dst, VR128:$src1, i128mem:$src2),
-                      "punpckhqdq {$src2, $dst|$dst, $src2}", []>;
+                      "punpckhqdq {$src2, $dst|$dst, $src2}",
+                      [(set VR128:$dst,
+                        (v2i64 (vector_shuffle VR128:$src1, (load addr:$src2),
+                                UNPCKH_shuffle_mask)))]>;
 }
 
 //===----------------------------------------------------------------------===//
@@ -1147,29 +1205,16 @@
           (v4i32 (PSHUFDrr VR128:$src, PSHUFD_shuffle_mask:$sm))>,
       Requires<[HasSSE2]>;
 
-// Shuffle v2f64 / v2i64
-def : Pat<(vector_shuffle (v2f64 VR128:$src1), (v2f64 VR128:$src2),
-           MOVLHPSorUNPCKLPD_shuffle_mask:$sm),
-          (v2f64 (MOVLHPSrr VR128:$src1, VR128:$src2))>, Requires<[HasSSE2]>;
-def : Pat<(vector_shuffle (v2f64 VR128:$src1), (v2f64 VR128:$src2),
-           MOVHLPS_shuffle_mask:$sm),
-          (v2f64 (MOVHLPSrr VR128:$src1, VR128:$src2))>, Requires<[HasSSE2]>;
-def : Pat<(vector_shuffle (v2f64 VR128:$src1), (v2f64 VR128:$src2),
-           UNPCKHPD_shuffle_mask:$sm),
-          (v2f64 (UNPCKHPDrr VR128:$src1, VR128:$src2))>, Requires<[HasSSE2]>;
-def : Pat<(vector_shuffle (v2f64 VR128:$src1), (loadv2f64 addr:$src2),
-           MOVLHPSorUNPCKLPD_shuffle_mask:$sm),
-          (v2f64 (UNPCKLPDrm VR128:$src1, addr:$src2))>, Requires<[HasSSE2]>;
-
+// Shuffle v2i64
 def : Pat<(vector_shuffle (v2i64 VR128:$src1), (v2i64 VR128:$src2),
-           MOVLHPSorUNPCKLPD_shuffle_mask:$sm),
+           UNPCKL_shuffle_mask:$sm),
           (v2i64 (MOVLHPSrr VR128:$src1, VR128:$src2))>, Requires<[HasSSE2]>;
 def : Pat<(vector_shuffle (v2i64 VR128:$src1), (v2i64 VR128:$src2),
            MOVHLPS_shuffle_mask:$sm),
           (v2i64 (MOVHLPSrr VR128:$src1, VR128:$src2))>, Requires<[HasSSE2]>;
-def : Pat<(vector_shuffle (v2i64 VR128:$src1), (v2i64 VR128:$src2),
-           UNPCKHPD_shuffle_mask:$sm),
-          (v2i64 (UNPCKHPDrr VR128:$src1, VR128:$src2))>, Requires<[HasSSE2]>;
-def : Pat<(vector_shuffle (v2i64 VR128:$src1), (loadv2i64 addr:$src2),
-           MOVLHPSorUNPCKLPD_shuffle_mask:$sm),
+def : Pat<(vector_shuffle (v2i64 VR128:$src1), (load addr:$src2),
+           UNPCKL_shuffle_mask:$sm),
           (v2i64 (UNPCKLPDrm VR128:$src1, addr:$src2))>, Requires<[HasSSE2]>;
+def : Pat<(vector_shuffle (v2i64 VR128:$src1), (load addr:$src2),
+           UNPCKH_shuffle_mask:$sm),
+          (v2i64 (UNPCKHPDrm VR128:$src1, addr:$src2))>, Requires<[HasSSE2]>;





From evan.cheng at apple.com  Mon Mar 27 20:44:16 2006
From: evan.cheng at apple.com (Evan Cheng)
Date: Mon, 27 Mar 2006 20:44:16 -0600
Subject: [llvm-commits] CVS: llvm/lib/Target/X86/README.txt 
Message-ID: <200603280244.UAA12890@zion.cs.uiuc.edu>



Changes in directory llvm/lib/Target/X86:

README.txt updated: 1.74 -> 1.75
---
Log message:

All unpack cases are now being handled.


---
Diffs of the changes:  (+0 -4)

 README.txt |    4 ----
 1 files changed, 4 deletions(-)


Index: llvm/lib/Target/X86/README.txt
diff -u llvm/lib/Target/X86/README.txt:1.74 llvm/lib/Target/X86/README.txt:1.75
--- llvm/lib/Target/X86/README.txt:1.74	Sun Mar 26 13:19:27 2006
+++ llvm/lib/Target/X86/README.txt	Mon Mar 27 20:44:05 2006
@@ -662,7 +662,3 @@
 
 Obviously it would have been better for the first mov (or any op) to store
 directly %esp[0] if there are no other uses.
-
-//===---------------------------------------------------------------------===//
-
-Add more vector shuffle special cases using unpckhps and unpcklps.





From evan.cheng at apple.com  Mon Mar 27 20:49:24 2006
From: evan.cheng at apple.com (Evan Cheng)
Date: Mon, 27 Mar 2006 20:49:24 -0600
Subject: [llvm-commits] CVS: llvm/lib/Target/X86/README.txt 
Message-ID: <200603280249.UAA12918@zion.cs.uiuc.edu>



Changes in directory llvm/lib/Target/X86:

README.txt updated: 1.75 -> 1.76
---
Log message:

Added a couple of entries about movhps and movlhps.


---
Diffs of the changes:  (+26 -0)

 README.txt |   26 ++++++++++++++++++++++++++
 1 files changed, 26 insertions(+)


Index: llvm/lib/Target/X86/README.txt
diff -u llvm/lib/Target/X86/README.txt:1.75 llvm/lib/Target/X86/README.txt:1.76
--- llvm/lib/Target/X86/README.txt:1.75	Mon Mar 27 20:44:05 2006
+++ llvm/lib/Target/X86/README.txt	Mon Mar 27 20:49:12 2006
@@ -662,3 +662,29 @@
 
 Obviously it would have been better for the first mov (or any op) to store
 directly %esp[0] if there are no other uses.
+
+//===---------------------------------------------------------------------===//
+
+Is it really a good idea to use movlhps to move 1 double-precision FP value from
+low quadword of source to high quadword of destination?
+
+e.g.
+
+void test2 (v2sd *b, double X, double Y) {
+  v2sd a = (v2sd) {X, X*Y};
+  *b = a;
+}
+
+	movsd 8(%esp), %xmm0
+	movapd %xmm0, %xmm1
+	mulsd 16(%esp), %xmm1
+	movlhps %xmm1, %xmm0
+	movl 4(%esp), %eax
+	movapd %xmm0, (%eax)
+	ret
+
+icc uses unpcklpd instead.
+
+//===---------------------------------------------------------------------===//
+
+Use movhps and movlhps to update upper 64-bits of a v4sf value.





From lattner at cs.uiuc.edu  Mon Mar 27 21:52:48 2006
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Mon, 27 Mar 2006 21:52:48 -0600
Subject: [llvm-commits] CVS: llvm/include/llvm/IntrinsicsPowerPC.td 
Message-ID: <200603280352.VAA13295@zion.cs.uiuc.edu>



Changes in directory llvm/include/llvm:

IntrinsicsPowerPC.td updated: 1.7 -> 1.8
---
Log message:

These don't directly map to gcc intrinsics any more.


---
Diffs of the changes:  (+14 -12)

 IntrinsicsPowerPC.td |   26 ++++++++++++++------------
 1 files changed, 14 insertions(+), 12 deletions(-)


Index: llvm/include/llvm/IntrinsicsPowerPC.td
diff -u llvm/include/llvm/IntrinsicsPowerPC.td:1.7 llvm/include/llvm/IntrinsicsPowerPC.td:1.8
--- llvm/include/llvm/IntrinsicsPowerPC.td:1.7	Mon Mar 27 20:28:48 2006
+++ llvm/include/llvm/IntrinsicsPowerPC.td	Mon Mar 27 21:52:36 2006
@@ -12,32 +12,34 @@
 //===----------------------------------------------------------------------===//
 
 let TargetPrefix = "ppc" in {  // All intrinsics start with "llvm.ppc.".
-  // Loads.
-  def int_ppc_altivec_lvx : GCCBuiltin<"__builtin_altivec_lvx">,
+  // Loads.  These don't map directly to GCC builtins because they represent the
+  // source address with a single pointer.
+  def int_ppc_altivec_lvx :
               Intrinsic<[llvm_v4i32_ty, llvm_ptr_ty], [IntrReadMem]>;
-  def int_ppc_altivec_lvxl : GCCBuiltin<"__builtin_altivec_lvxl">,
+  def int_ppc_altivec_lvxl :
               Intrinsic<[llvm_v4i32_ty, llvm_ptr_ty], [IntrReadMem]>;
-  def int_ppc_altivec_lvebx : GCCBuiltin<"__builtin_altivec_lvebx">,
+  def int_ppc_altivec_lvebx :
               Intrinsic<[llvm_v16i8_ty, llvm_ptr_ty], [IntrReadMem]>;
-  def int_ppc_altivec_lvehx : GCCBuiltin<"__builtin_altivec_lvehx">,
+  def int_ppc_altivec_lvehx :
               Intrinsic<[llvm_v8i16_ty, llvm_ptr_ty], [IntrReadMem]>;
-  def int_ppc_altivec_lvewx : GCCBuiltin<"__builtin_altivec_lvewx">,
+  def int_ppc_altivec_lvewx :
               Intrinsic<[llvm_v4i32_ty, llvm_ptr_ty], [IntrReadMem]>;
 
-  // Stores.
-  def int_ppc_altivec_stvx : GCCBuiltin<"__builtin_altivec_stvx">,
+  // Stores.  These don't map directly to GCC builtins because they represent the
+  // source address with a single pointer.
+  def int_ppc_altivec_stvx :
               Intrinsic<[llvm_void_ty, llvm_v4i32_ty, llvm_ptr_ty],
                         [IntrWriteMem]>;
-  def int_ppc_altivec_stvxl : GCCBuiltin<"__builtin_altivec_stvxl">,
+  def int_ppc_altivec_stvxl :
               Intrinsic<[llvm_void_ty, llvm_v4i32_ty, llvm_ptr_ty],
                         [IntrWriteMem]>;
-  def int_ppc_altivec_stvebx : GCCBuiltin<"__builtin_altivec_stvebx">,
+  def int_ppc_altivec_stvebx :
               Intrinsic<[llvm_void_ty, llvm_v16i8_ty, llvm_ptr_ty],
                         [IntrWriteMem]>;
-  def int_ppc_altivec_stvehx : GCCBuiltin<"__builtin_altivec_stvehx">,
+  def int_ppc_altivec_stvehx :
               Intrinsic<[llvm_void_ty, llvm_v8i16_ty, llvm_ptr_ty],
                         [IntrWriteMem]>;
-  def int_ppc_altivec_stvewx : GCCBuiltin<"__builtin_altivec_stvewx">,
+  def int_ppc_altivec_stvewx :
               Intrinsic<[llvm_void_ty, llvm_v4i32_ty, llvm_ptr_ty],
                         [IntrWriteMem]>;
 





From jeffc at jolt-lang.org  Mon Mar 27 22:01:39 2006
From: jeffc at jolt-lang.org (Jeff Cohen)
Date: Mon, 27 Mar 2006 22:01:39 -0600
Subject: [llvm-commits] CVS: llvm/win32/VMCore/VMCore.vcproj 
Message-ID: <200603280401.WAA13414@zion.cs.uiuc.edu>



Changes in directory llvm/win32/VMCore:

VMCore.vcproj updated: 1.18 -> 1.19
---
Log message:

Keep Visual Studio informed.

---
Diffs of the changes:  (+8 -2)

 VMCore.vcproj |   10 ++++++++--
 1 files changed, 8 insertions(+), 2 deletions(-)


Index: llvm/win32/VMCore/VMCore.vcproj
diff -u llvm/win32/VMCore/VMCore.vcproj:1.18 llvm/win32/VMCore/VMCore.vcproj:1.19
--- llvm/win32/VMCore/VMCore.vcproj:1.18	Thu Mar 23 20:18:52 2006
+++ llvm/win32/VMCore/VMCore.vcproj	Mon Mar 27 22:01:27 2006
@@ -157,7 +157,7 @@
 						Description="Performing TableGen Step"
 						CommandLine="..\$(IntDir)\TableGen.exe -gen-intrinsic -I ..\..\include $(InputPath) -o $(SolutionDir)llvm\intrinsics.gen
 "
-						AdditionalDependencies="$(ProjectDir)..\$(IntDir)\TableGen.exe"
+						AdditionalDependencies="$(ProjectDir)..\$(IntDir)\TableGen.exe $(InputDir)IntrinsicsX86.td $(InputDir)IntrinsicsPowerPC.td"
 						Outputs="$(SolutionDir)llvm\intrinsics.gen"/>
 				</FileConfiguration>
 				<FileConfiguration
@@ -167,11 +167,17 @@
 						Description="Performing TableGen Step"
 						CommandLine="..\$(IntDir)\TableGen.exe -gen-intrinsic -I ..\..\include $(InputPath) -o $(SolutionDir)llvm\intrinsics.gen
 "
-						AdditionalDependencies="$(ProjectDir)..\$(IntDir)\TableGen.exe"
+						AdditionalDependencies="$(ProjectDir)..\$(IntDir)\TableGen.exe $(InputDir)IntrinsicsX86.td $(InputDir)IntrinsicsPowerPC.td"
 						Outputs="$(SolutionDir)llvm\intrinsics.gen"/>
 				</FileConfiguration>
 			</File>
 			<File
+				RelativePath="..\..\include\llvm\IntrinsicsPowerPC.td">
+			</File>
+			<File
+				RelativePath="..\..\include\llvm\IntrinsicsX86.td">
+			</File>
+			<File
 				RelativePath="..\..\lib\VMCore\LeakDetector.cpp">
 			</File>
 			<File





From natebegeman at mac.com  Mon Mar 27 22:16:12 2006
From: natebegeman at mac.com (Nate Begeman)
Date: Mon, 27 Mar 2006 22:16:12 -0600
Subject: [llvm-commits] CVS: llvm/include/llvm/IntrinsicsPowerPC.td 
Message-ID: <200603280416.WAA13483@zion.cs.uiuc.edu>



Changes in directory llvm/include/llvm:

IntrinsicsPowerPC.td updated: 1.8 -> 1.9
---
Log message:

Add a few more altivec intrinsics


---
Diffs of the changes:  (+24 -1)

 IntrinsicsPowerPC.td |   25 ++++++++++++++++++++++++-
 1 files changed, 24 insertions(+), 1 deletion(-)


Index: llvm/include/llvm/IntrinsicsPowerPC.td
diff -u llvm/include/llvm/IntrinsicsPowerPC.td:1.8 llvm/include/llvm/IntrinsicsPowerPC.td:1.9
--- llvm/include/llvm/IntrinsicsPowerPC.td:1.8	Mon Mar 27 21:52:36 2006
+++ llvm/include/llvm/IntrinsicsPowerPC.td	Mon Mar 27 22:15:58 2006
@@ -131,7 +131,7 @@
               Intrinsic<[llvm_int_ty, llvm_int_ty, llvm_v16i8_ty,llvm_v16i8_ty],
                         [InstrNoMem]>;
 
-  // Saturating adds and subs.
+  // Saturating adds, subs, and multiply-adds
   def int_ppc_altivec_vaddubs : GCCBuiltin<"__builtin_altivec_vaddubs">,
               Intrinsic<[llvm_v16i8_ty, llvm_v16i8_ty, llvm_v16i8_ty],
                         [InstrNoMem]>;
@@ -150,6 +150,12 @@
   def int_ppc_altivec_vaddsws : GCCBuiltin<"__builtin_altivec_vaddsws">,
               Intrinsic<[llvm_v4i32_ty, llvm_v4i32_ty, llvm_v4i32_ty],
                         [InstrNoMem]>;
+  def int_ppc_altivec_vmhaddshs : GCCBuiltin<"__builtin_altivec_vmhaddshs">,
+              Intrinsic<[llvm_v8i16_ty, llvm_v8i16_ty,
+                         llvm_v8i16_ty, llvm_v8i16_ty], [InstrNoMem]>;
+  def int_ppc_altivec_vmhraddshs : GCCBuiltin<"__builtin_altivec_vmhraddshs">,
+              Intrinsic<[llvm_v8i16_ty, llvm_v8i16_ty,
+                         llvm_v8i16_ty, llvm_v8i16_ty], [InstrNoMem]>;
 
   def int_ppc_altivec_vmaddfp : GCCBuiltin<"__builtin_altivec_vmaddfp">,
               Intrinsic<[llvm_v4f32_ty, llvm_v4f32_ty,
@@ -219,6 +225,20 @@
   def int_ppc_altivec_vrfiz : GCCBuiltin<"__builtin_altivec_vrfiz">,
               Intrinsic<[llvm_v4f32_ty, llvm_v4f32_ty], [InstrNoMem]>;
 
+  // Merges
+  def int_ppc_altivec_vmrghh : GCCBuiltin<"__builtin_altivec_vmrghh">,
+              Intrinsic<[llvm_v8i16_ty, llvm_v8i16_ty, llvm_v8i16_ty],
+                        [InstrNoMem]>;
+  def int_ppc_altivec_vmrghw : GCCBuiltin<"__builtin_altivec_vmrghw">,
+              Intrinsic<[llvm_v4i32_ty, llvm_v4i32_ty, llvm_v4i32_ty],
+                        [InstrNoMem]>;
+  def int_ppc_altivec_vmrglh : GCCBuiltin<"__builtin_altivec_vmrglh">,
+              Intrinsic<[llvm_v8i16_ty, llvm_v8i16_ty, llvm_v8i16_ty],
+                        [InstrNoMem]>;
+  def int_ppc_altivec_vmrglw : GCCBuiltin<"__builtin_altivec_vmrglw">,
+              Intrinsic<[llvm_v4i32_ty, llvm_v4i32_ty, llvm_v4i32_ty],
+                        [InstrNoMem]>;
+
   // Left Shifts.
   def int_ppc_altivec_vsldoi : GCCBuiltin<"__builtin_altivec_vsldoi_4si">,
               Intrinsic<[llvm_v4i32_ty, llvm_v4i32_ty, 
@@ -276,6 +296,9 @@
                         [InstrNoMem]>;
 
   // Miscellaneous.
+  def int_ppc_altivec_vperm : GCCBuiltin<"__builtin_altivec_vperm_4si">,
+              Intrinsic<[llvm_v4i32_ty, llvm_v4i32_ty, 
+                         llvm_v4i32_ty, llvm_v16i8_ty], [InstrNoMem]>;
   def int_ppc_altivec_vsel : GCCBuiltin<"__builtin_altivec_vsel_4si">,
               Intrinsic<[llvm_v4i32_ty, llvm_v4i32_ty, 
                          llvm_v4i32_ty, llvm_v4i32_ty], [InstrNoMem]>;





From natebegeman at mac.com  Mon Mar 27 22:16:12 2006
From: natebegeman at mac.com (Nate Begeman)
Date: Mon, 27 Mar 2006 22:16:12 -0600
Subject: [llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCISelLowering.cpp
	PPCInstrAltivec.td README_ALTIVEC.txt 
Message-ID: <200603280416.WAA13491@zion.cs.uiuc.edu>



Changes in directory llvm/lib/Target/PowerPC:

PPCISelLowering.cpp updated: 1.117 -> 1.118
PPCInstrAltivec.td updated: 1.16 -> 1.17
README_ALTIVEC.txt updated: 1.3 -> 1.4
---
Log message:

Add a few more altivec intrinsics


---
Diffs of the changes:  (+28 -6)

 PPCISelLowering.cpp |    4 ++--
 PPCInstrAltivec.td  |   28 ++++++++++++++++++++++++++--
 README_ALTIVEC.txt  |    2 --
 3 files changed, 28 insertions(+), 6 deletions(-)


Index: llvm/lib/Target/PowerPC/PPCISelLowering.cpp
diff -u llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.117 llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.118
--- llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.117	Mon Mar 27 19:43:22 2006
+++ llvm/lib/Target/PowerPC/PPCISelLowering.cpp	Mon Mar 27 22:15:58 2006
@@ -300,8 +300,8 @@
   
   if (OpVal.Val == 0) return false;  // All UNDEF: use implicit def.
   
-  unsigned ValSizeInBytes;
-  uint64_t Value;
+  unsigned ValSizeInBytes = 0;
+  uint64_t Value = 0;
   if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(OpVal)) {
     Value = CN->getValue();
     ValSizeInBytes = MVT::getSizeInBits(CN->getValueType(0))/8;


Index: llvm/lib/Target/PowerPC/PPCInstrAltivec.td
diff -u llvm/lib/Target/PowerPC/PPCInstrAltivec.td:1.16 llvm/lib/Target/PowerPC/PPCInstrAltivec.td:1.17
--- llvm/lib/Target/PowerPC/PPCInstrAltivec.td:1.16	Mon Mar 27 20:29:37 2006
+++ llvm/lib/Target/PowerPC/PPCInstrAltivec.td	Mon Mar 27 22:15:58 2006
@@ -121,7 +121,14 @@
                        [(set VRRC:$vD, (fneg (fsub (fmul VRRC:$vA, VRRC:$vC),
                                                    VRRC:$vB)))]>,
                        Requires<[FPContractions]>;
-
+def VMHADDSHS  : VAForm_1a<32, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB, VRRC:$vC),
+                  "vmhaddshs $vD, $vA, $vB, $vC", VecFP,
+                  [(set VRRC:$vD,
+                   (int_ppc_altivec_vmhaddshs VRRC:$vA, VRRC:$vB, VRRC:$vC))]>;
+def VMHRADDSHS : VAForm_1a<33, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB, VRRC:$vC),
+                  "vmhraddshs $vD, $vA, $vB, $vC", VecFP,
+                  [(set VRRC:$vD,
+                   (int_ppc_altivec_vmhraddshs VRRC:$vA, VRRC:$vB, VRRC:$vC))]>;
 def VPERM   : VAForm_1a<43, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB, VRRC:$vC),
                         "vperm $vD, $vA, $vB, $vC", VecPerm,
                         [(set VRRC:$vD,
@@ -213,6 +220,22 @@
 def VMINFP : VXForm_1<1098, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
                       "vminfp $vD, $vA, $vB", VecFP,
                       []>;
+def VMRGHH : VXForm_1<76, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
+                      "vmrghh $vD, $vA, $vB", VecFP,
+                      [(set VRRC:$vD,
+                       (int_ppc_altivec_vmrghh VRRC:$vA, VRRC:$vB))]>;
+def VMRGHW : VXForm_1<140, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
+                      "vmrghh $vD, $vA, $vB", VecFP,
+                      [(set VRRC:$vD,
+                       (int_ppc_altivec_vmrghw VRRC:$vA, VRRC:$vB))]>;
+def VMRGLH : VXForm_1<332, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
+                      "vmrglh $vD, $vA, $vB", VecFP,
+                      [(set VRRC:$vD,
+                       (int_ppc_altivec_vmrglh VRRC:$vA, VRRC:$vB))]>;
+def VMRGLW : VXForm_1<396, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
+                      "vmrglh $vD, $vA, $vB", VecFP,
+                      [(set VRRC:$vD,
+                       (int_ppc_altivec_vmrglw VRRC:$vA, VRRC:$vB))]>;
 def VREFP  : VXForm_2<266, (ops VRRC:$vD, VRRC:$vB),
                       "vrefp $vD, $vB", VecFP,
                       [(set VRRC:$vD, (int_ppc_altivec_vrefp VRRC:$vB))]>;
@@ -598,7 +621,8 @@
           (VMADDFP VRRC:$A, VRRC:$B, VRRC:$C)>;
 def : Pat<(int_ppc_altivec_vnmsubfp VRRC:$A, VRRC:$B, VRRC:$C),
           (VNMSUBFP VRRC:$A, VRRC:$B, VRRC:$C)>;
-
+def : Pat<(int_ppc_altivec_vperm VRRC:$A, VRRC:$B, VRRC:$C),
+          (VPERM VRRC:$A, VRRC:$B, VRRC:$C)>;
 def : Pat<(vector_shuffle (v4i32 VRRC:$vB), (undef), VSPLT_shuffle_mask:$UIMM),
           (v4i32 (VSPLTW VSPLT_shuffle_mask:$UIMM, VRRC:$vB))>;
 


Index: llvm/lib/Target/PowerPC/README_ALTIVEC.txt
diff -u llvm/lib/Target/PowerPC/README_ALTIVEC.txt:1.3 llvm/lib/Target/PowerPC/README_ALTIVEC.txt:1.4
--- llvm/lib/Target/PowerPC/README_ALTIVEC.txt:1.3	Mon Mar 27 20:29:37 2006
+++ llvm/lib/Target/PowerPC/README_ALTIVEC.txt	Mon Mar 27 22:15:58 2006
@@ -54,13 +54,11 @@
 mf*
 vavg*
 vmax*
-vmhaddshs/vmhraddshs
 vmin*
 vmladduhm
 vmr*
 vmsum*
 vmul*
-vperm
 vpk*
 vsel (some aliases only accessible using builtins)
 vup*





From natebegeman at mac.com  Mon Mar 27 22:18:30 2006
From: natebegeman at mac.com (Nate Begeman)
Date: Mon, 27 Mar 2006 22:18:30 -0600
Subject: [llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCInstrAltivec.td 
Message-ID: <200603280418.WAA13510@zion.cs.uiuc.edu>



Changes in directory llvm/lib/Target/PowerPC:

PPCInstrAltivec.td updated: 1.17 -> 1.18
---
Log message:

Fix a couple typos


---
Diffs of the changes:  (+2 -2)

 PPCInstrAltivec.td |    4 ++--
 1 files changed, 2 insertions(+), 2 deletions(-)


Index: llvm/lib/Target/PowerPC/PPCInstrAltivec.td
diff -u llvm/lib/Target/PowerPC/PPCInstrAltivec.td:1.17 llvm/lib/Target/PowerPC/PPCInstrAltivec.td:1.18
--- llvm/lib/Target/PowerPC/PPCInstrAltivec.td:1.17	Mon Mar 27 22:15:58 2006
+++ llvm/lib/Target/PowerPC/PPCInstrAltivec.td	Mon Mar 27 22:18:18 2006
@@ -225,7 +225,7 @@
                       [(set VRRC:$vD,
                        (int_ppc_altivec_vmrghh VRRC:$vA, VRRC:$vB))]>;
 def VMRGHW : VXForm_1<140, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
-                      "vmrghh $vD, $vA, $vB", VecFP,
+                      "vmrghw $vD, $vA, $vB", VecFP,
                       [(set VRRC:$vD,
                        (int_ppc_altivec_vmrghw VRRC:$vA, VRRC:$vB))]>;
 def VMRGLH : VXForm_1<332, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
@@ -233,7 +233,7 @@
                       [(set VRRC:$vD,
                        (int_ppc_altivec_vmrglh VRRC:$vA, VRRC:$vB))]>;
 def VMRGLW : VXForm_1<396, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
-                      "vmrglh $vD, $vA, $vB", VecFP,
+                      "vmrglw $vD, $vA, $vB", VecFP,
                       [(set VRRC:$vD,
                        (int_ppc_altivec_vmrglw VRRC:$vA, VRRC:$vB))]>;
 def VREFP  : VXForm_2<266, (ops VRRC:$vD, VRRC:$vB),





From evan.cheng at apple.com  Tue Mar 28 00:41:09 2006
From: evan.cheng at apple.com (Evan Cheng)
Date: Tue, 28 Mar 2006 00:41:09 -0600
Subject: [llvm-commits] CVS: llvm/test/Regression/CodeGen/X86/vec_shuffle.ll
Message-ID: <200603280641.AAA14170@zion.cs.uiuc.edu>



Changes in directory llvm/test/Regression/CodeGen/X86:

vec_shuffle.ll updated: 1.2 -> 1.3
---
Log message:

Use movhpd is even better than movlhps.

---
Diffs of the changes:  (+1 -1)

 vec_shuffle.ll |    2 +-
 1 files changed, 1 insertion(+), 1 deletion(-)


Index: llvm/test/Regression/CodeGen/X86/vec_shuffle.ll
diff -u llvm/test/Regression/CodeGen/X86/vec_shuffle.ll:1.2 llvm/test/Regression/CodeGen/X86/vec_shuffle.ll:1.3
--- llvm/test/Regression/CodeGen/X86/vec_shuffle.ll:1.2	Thu Mar 23 20:56:00 2006
+++ llvm/test/Regression/CodeGen/X86/vec_shuffle.ll	Tue Mar 28 00:40:57 2006
@@ -1,5 +1,5 @@
 ; RUN: llvm-as < %s | llc -march=x86 -mattr=+sse2 | grep shufp | wc -l | grep 1
-; RUN: llvm-as < %s | llc -march=x86 -mattr=+sse2 | grep movlhps
+; RUN: llvm-as < %s | llc -march=x86 -mattr=+sse2 | grep movhpd
 
 void %test_v4sf(<4 x float>* %P, float %X, float %Y) {
 	%tmp = insertelement <4 x float> zeroinitializer, float %X, uint 0





From evan.cheng at apple.com  Tue Mar 28 00:50:44 2006
From: evan.cheng at apple.com (Evan Cheng)
Date: Tue, 28 Mar 2006 00:50:44 -0600
Subject: [llvm-commits] CVS: llvm/lib/Target/X86/X86ISelLowering.cpp
	X86ISelLowering.h X86InstrSSE.td 
Message-ID: <200603280650.AAA14210@zion.cs.uiuc.edu>



Changes in directory llvm/lib/Target/X86:

X86ISelLowering.cpp updated: 1.137 -> 1.138
X86ISelLowering.h updated: 1.46 -> 1.47
X86InstrSSE.td updated: 1.36 -> 1.37
---
Log message:

* Prefer using operation of matching types. e.g unpcklpd rather than movlhps.
* Bug fixes.


---
Diffs of the changes:  (+73 -41)

 X86ISelLowering.cpp |   86 +++++++++++++++++++++++++++++++++++++---------------
 X86ISelLowering.h   |    4 ++
 X86InstrSSE.td      |   24 ++++----------
 3 files changed, 73 insertions(+), 41 deletions(-)


Index: llvm/lib/Target/X86/X86ISelLowering.cpp
diff -u llvm/lib/Target/X86/X86ISelLowering.cpp:1.137 llvm/lib/Target/X86/X86ISelLowering.cpp:1.138
--- llvm/lib/Target/X86/X86ISelLowering.cpp:1.137	Mon Mar 27 20:43:26 2006
+++ llvm/lib/Target/X86/X86ISelLowering.cpp	Tue Mar 28 00:50:32 2006
@@ -1456,16 +1456,43 @@
 bool X86::isMOVHLPSMask(SDNode *N) {
   assert(N->getOpcode() == ISD::BUILD_VECTOR);
 
-  if (N->getNumOperands() != 2)
+  if (N->getNumOperands() != 4)
     return false;
 
-  // Expect bit 0 == 1, bit1 == 1
+  // Expect bit0 == 6, bit1 == 7, bit2 == 2, bit3 == 3
   SDOperand Bit0 = N->getOperand(0);
   SDOperand Bit1 = N->getOperand(1);
+  SDOperand Bit2 = N->getOperand(2);
+  SDOperand Bit3 = N->getOperand(3);
   assert(isa<ConstantSDNode>(Bit0) && isa<ConstantSDNode>(Bit1) &&
+         isa<ConstantSDNode>(Bit2) && isa<ConstantSDNode>(Bit3) &&
+         "Invalid VECTOR_SHUFFLE mask!");
+  return (cast<ConstantSDNode>(Bit0)->getValue() == 6 &&
+          cast<ConstantSDNode>(Bit1)->getValue() == 7 &&
+          cast<ConstantSDNode>(Bit2)->getValue() == 2 &&
+          cast<ConstantSDNode>(Bit3)->getValue() == 3);
+}
+
+/// isMOVLHPSMask - Return true if the specified VECTOR_SHUFFLE operand
+/// specifies a shuffle of elements that is suitable for input to MOVHLPS.
+bool X86::isMOVLHPSMask(SDNode *N) {
+  assert(N->getOpcode() == ISD::BUILD_VECTOR);
+
+  if (N->getNumOperands() != 4)
+    return false;
+
+  // Expect bit0 == 0, bit1 == 1, bit2 == 4, bit3 == 5
+  SDOperand Bit0 = N->getOperand(0);
+  SDOperand Bit1 = N->getOperand(1);
+  SDOperand Bit2 = N->getOperand(2);
+  SDOperand Bit3 = N->getOperand(3);
+  assert(isa<ConstantSDNode>(Bit0) && isa<ConstantSDNode>(Bit1) &&
+         isa<ConstantSDNode>(Bit2) && isa<ConstantSDNode>(Bit3) &&
          "Invalid VECTOR_SHUFFLE mask!");
   return (cast<ConstantSDNode>(Bit0)->getValue() == 0 &&
-          cast<ConstantSDNode>(Bit1)->getValue() == 3);
+          cast<ConstantSDNode>(Bit1)->getValue() == 1 &&
+          cast<ConstantSDNode>(Bit2)->getValue() == 4 &&
+          cast<ConstantSDNode>(Bit3)->getValue() == 5);
 }
 
 /// isUNPCKLMask - Return true if the specified VECTOR_SHUFFLE operand
@@ -1556,6 +1583,30 @@
   return Mask;
 }
 
+/// CommuteVectorShuffleIfNeeded - Swap vector_shuffle operands (as well as
+/// values in ther permute mask if needed. Return an empty SDOperand is it is
+/// already well formed.
+static SDOperand CommuteVectorShuffleIfNeeded(SDOperand V1, SDOperand V2,
+                                              SDOperand Mask, MVT::ValueType VT,
+                                              SelectionDAG &DAG) {
+  unsigned NumElems = Mask.getNumOperands();
+  SDOperand Half1 = Mask.getOperand(0);
+  SDOperand Half2 = Mask.getOperand(NumElems/2);
+  if (cast<ConstantSDNode>(Half1)->getValue() >= NumElems &&
+      cast<ConstantSDNode>(Half2)->getValue() <  NumElems) {
+    // Swap the operands and change mask.
+    std::vector<SDOperand> MaskVec;
+    for (unsigned i = NumElems / 2; i != NumElems; ++i)
+      MaskVec.push_back(Mask.getOperand(i));
+    for (unsigned i = 0; i != NumElems / 2; ++i)
+      MaskVec.push_back(Mask.getOperand(i));
+    Mask =
+      DAG.getNode(ISD::BUILD_VECTOR, Mask.getValueType(), MaskVec);
+    return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V2, V1, Mask);
+  }
+  return SDOperand();
+}
+
 /// LowerOperation - Provide custom lowering hooks for some operations.
 ///
 SDOperand X86TargetLowering::LowerOperation(SDOperand Op, SelectionDAG &DAG) {
@@ -2336,11 +2387,10 @@
     MVT::ValueType VT = Op.getValueType();
     unsigned NumElems = PermMask.getNumOperands();
 
-    // All v2f64 cases are handled.
-    if (NumElems == 2) return SDOperand();
-
-    // Handle splat cases.
-    if (X86::isSplatMask(PermMask.Val)) {
+    if (NumElems == 2)
+      return CommuteVectorShuffleIfNeeded(V1, V2, PermMask, VT, DAG);
+    else if (X86::isSplatMask(PermMask.Val)) {
+      // Handle splat cases.
       if (V2.getOpcode() == ISD::UNDEF)
         // Leave the VECTOR_SHUFFLE alone. It matches SHUFP*.
         return SDOperand();
@@ -2350,7 +2400,8 @@
         return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1,
                            DAG.getNode(ISD::UNDEF, V1.getValueType()),
                            PermMask);
-    } else if (X86::isUNPCKLMask(PermMask.Val)) {
+    } else if (X86::isUNPCKLMask(PermMask.Val) ||
+               X86::isUNPCKHMask(PermMask.Val)) {
       // Leave the VECTOR_SHUFFLE alone. It matches {P}UNPCKL*.
       return SDOperand();
     } else if (X86::isPSHUFDMask(PermMask.Val)) {
@@ -2362,21 +2413,8 @@
         return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1,
                            DAG.getNode(ISD::UNDEF, V1.getValueType()),
                            PermMask);
-    } else if (X86::isSHUFPMask(PermMask.Val)) {
-      SDOperand Elt = PermMask.getOperand(0);
-      if (cast<ConstantSDNode>(Elt)->getValue() >= NumElems) {
-        // Swap the operands and change mask.
-        std::vector<SDOperand> MaskVec;
-        for (unsigned i = NumElems / 2; i != NumElems; ++i)
-          MaskVec.push_back(PermMask.getOperand(i));
-        for (unsigned i = 0; i != NumElems / 2; ++i)
-          MaskVec.push_back(PermMask.getOperand(i));
-        PermMask =
-          DAG.getNode(ISD::BUILD_VECTOR, PermMask.getValueType(), MaskVec);
-        return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V2, V1, PermMask);
-      }
-      return SDOperand();
-    }
+    } else if (X86::isSHUFPMask(PermMask.Val))
+      return CommuteVectorShuffleIfNeeded(V1, V2, PermMask, VT, DAG);
 
     assert(0 && "Unexpected VECTOR_SHUFFLE to lower");
     abort();


Index: llvm/lib/Target/X86/X86ISelLowering.h
diff -u llvm/lib/Target/X86/X86ISelLowering.h:1.46 llvm/lib/Target/X86/X86ISelLowering.h:1.47
--- llvm/lib/Target/X86/X86ISelLowering.h:1.46	Mon Mar 27 20:43:26 2006
+++ llvm/lib/Target/X86/X86ISelLowering.h	Tue Mar 28 00:50:32 2006
@@ -188,6 +188,10 @@
    /// specifies a shuffle of elements that is suitable for input to SHUFP*.
    bool isSHUFPMask(SDNode *N);
 
+   /// isMOVLHPSMask - Return true if the specified VECTOR_SHUFFLE operand
+   /// specifies a shuffle of elements that is suitable for input to MOVHLPS.
+   bool isMOVLHPSMask(SDNode *N);
+
    /// isMOVHLPSMask - Return true if the specified VECTOR_SHUFFLE operand
    /// specifies a shuffle of elements that is suitable for input to MOVHLPS.
    bool isMOVHLPSMask(SDNode *N);


Index: llvm/lib/Target/X86/X86InstrSSE.td
diff -u llvm/lib/Target/X86/X86InstrSSE.td:1.36 llvm/lib/Target/X86/X86InstrSSE.td:1.37
--- llvm/lib/Target/X86/X86InstrSSE.td:1.36	Mon Mar 27 20:43:26 2006
+++ llvm/lib/Target/X86/X86InstrSSE.td	Tue Mar 28 00:50:32 2006
@@ -63,6 +63,10 @@
   return X86::isSplatMask(N);
 }]>;
 
+def MOVLHPS_shuffle_mask : PatLeaf<(build_vector), [{
+  return X86::isMOVLHPSMask(N);
+}]>;
+
 def MOVHLPS_shuffle_mask : PatLeaf<(build_vector), [{
   return X86::isMOVHLPSMask(N);
 }]>;
@@ -492,13 +496,13 @@
 def MOVLHPSrr : PSI<0x16, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
                     "movlhps {$src2, $dst|$dst, $src2}",
                     [(set VR128:$dst,
-                      (v2f64 (vector_shuffle VR128:$src1, VR128:$src2,
-                              UNPCKL_shuffle_mask)))]>;
+                      (v4f32 (vector_shuffle VR128:$src1, VR128:$src2,
+                              MOVLHPS_shuffle_mask)))]>;
 
 def MOVHLPSrr : PSI<0x12, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
                     "movlhps {$src2, $dst|$dst, $src2}",
                     [(set VR128:$dst,
-                      (v2f64 (vector_shuffle VR128:$src1, VR128:$src2,
+                      (v4f32 (vector_shuffle VR128:$src1, VR128:$src2,
                               MOVHLPS_shuffle_mask)))]>;
 }
 
@@ -1204,17 +1208,3 @@
 def : Pat<(vector_shuffle (v4i32 VR128:$src), (undef), PSHUFD_shuffle_mask:$sm),
           (v4i32 (PSHUFDrr VR128:$src, PSHUFD_shuffle_mask:$sm))>,
       Requires<[HasSSE2]>;
-
-// Shuffle v2i64
-def : Pat<(vector_shuffle (v2i64 VR128:$src1), (v2i64 VR128:$src2),
-           UNPCKL_shuffle_mask:$sm),
-          (v2i64 (MOVLHPSrr VR128:$src1, VR128:$src2))>, Requires<[HasSSE2]>;
-def : Pat<(vector_shuffle (v2i64 VR128:$src1), (v2i64 VR128:$src2),
-           MOVHLPS_shuffle_mask:$sm),
-          (v2i64 (MOVHLPSrr VR128:$src1, VR128:$src2))>, Requires<[HasSSE2]>;
-def : Pat<(vector_shuffle (v2i64 VR128:$src1), (load addr:$src2),
-           UNPCKL_shuffle_mask:$sm),
-          (v2i64 (UNPCKLPDrm VR128:$src1, addr:$src2))>, Requires<[HasSSE2]>;
-def : Pat<(vector_shuffle (v2i64 VR128:$src1), (load addr:$src2),
-           UNPCKH_shuffle_mask:$sm),
-          (v2i64 (UNPCKHPDrm VR128:$src1, addr:$src2))>, Requires<[HasSSE2]>;





From evan.cheng at apple.com  Tue Mar 28 00:54:01 2006
From: evan.cheng at apple.com (Evan Cheng)
Date: Tue, 28 Mar 2006 00:54:01 -0600
Subject: [llvm-commits] CVS: llvm/lib/Target/X86/X86InstrSSE.td 
Message-ID: <200603280654.AAA14229@zion.cs.uiuc.edu>



Changes in directory llvm/lib/Target/X86:

X86InstrSSE.td updated: 1.37 -> 1.38
---
Log message:

Typo

---
Diffs of the changes:  (+1 -1)

 X86InstrSSE.td |    2 +-
 1 files changed, 1 insertion(+), 1 deletion(-)


Index: llvm/lib/Target/X86/X86InstrSSE.td
diff -u llvm/lib/Target/X86/X86InstrSSE.td:1.37 llvm/lib/Target/X86/X86InstrSSE.td:1.38
--- llvm/lib/Target/X86/X86InstrSSE.td:1.37	Tue Mar 28 00:50:32 2006
+++ llvm/lib/Target/X86/X86InstrSSE.td	Tue Mar 28 00:53:49 2006
@@ -500,7 +500,7 @@
                               MOVLHPS_shuffle_mask)))]>;
 
 def MOVHLPSrr : PSI<0x12, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
-                    "movlhps {$src2, $dst|$dst, $src2}",
+                    "movhlps {$src2, $dst|$dst, $src2}",
                     [(set VR128:$dst,
                       (v4f32 (vector_shuffle VR128:$src1, VR128:$src2,
                               MOVHLPS_shuffle_mask)))]>;





From evan.cheng at apple.com  Tue Mar 28 00:55:57 2006
From: evan.cheng at apple.com (Evan Cheng)
Date: Tue, 28 Mar 2006 00:55:57 -0600
Subject: [llvm-commits] CVS: llvm/lib/Target/X86/README.txt 
Message-ID: <200603280655.AAA14248@zion.cs.uiuc.edu>



Changes in directory llvm/lib/Target/X86:

README.txt updated: 1.76 -> 1.77
---
Log message:

Update

---
Diffs of the changes:  (+2 -23)

 README.txt |   25 ++-----------------------
 1 files changed, 2 insertions(+), 23 deletions(-)


Index: llvm/lib/Target/X86/README.txt
diff -u llvm/lib/Target/X86/README.txt:1.76 llvm/lib/Target/X86/README.txt:1.77
--- llvm/lib/Target/X86/README.txt:1.76	Mon Mar 27 20:49:12 2006
+++ llvm/lib/Target/X86/README.txt	Tue Mar 28 00:55:45 2006
@@ -665,26 +665,5 @@
 
 //===---------------------------------------------------------------------===//
 
-Is it really a good idea to use movlhps to move 1 double-precision FP value from
-low quadword of source to high quadword of destination?
-
-e.g.
-
-void test2 (v2sd *b, double X, double Y) {
-  v2sd a = (v2sd) {X, X*Y};
-  *b = a;
-}
-
-	movsd 8(%esp), %xmm0
-	movapd %xmm0, %xmm1
-	mulsd 16(%esp), %xmm1
-	movlhps %xmm1, %xmm0
-	movl 4(%esp), %eax
-	movapd %xmm0, (%eax)
-	ret
-
-icc uses unpcklpd instead.
-
-//===---------------------------------------------------------------------===//
-
-Use movhps and movlhps to update upper 64-bits of a v4sf value.
+Use movhps to update upper 64-bits of a v4sf value. Also movlps on lower half
+of a v4sf value.





From evan.cheng at apple.com  Tue Mar 28 01:01:40 2006
From: evan.cheng at apple.com (Evan Cheng)
Date: Tue, 28 Mar 2006 01:01:40 -0600
Subject: [llvm-commits] CVS: llvm/lib/Target/X86/X86InstrSSE.td 
Message-ID: <200603280701.BAA14321@zion.cs.uiuc.edu>



Changes in directory llvm/lib/Target/X86:

X86InstrSSE.td updated: 1.38 -> 1.39
---
Log message:

movlps and movlpd should be modeled as two address code.

---
Diffs of the changes:  (+9 -9)

 X86InstrSSE.td |   18 +++++++++---------
 1 files changed, 9 insertions(+), 9 deletions(-)


Index: llvm/lib/Target/X86/X86InstrSSE.td
diff -u llvm/lib/Target/X86/X86InstrSSE.td:1.38 llvm/lib/Target/X86/X86InstrSSE.td:1.39
--- llvm/lib/Target/X86/X86InstrSSE.td:1.38	Tue Mar 28 00:53:49 2006
+++ llvm/lib/Target/X86/X86InstrSSE.td	Tue Mar 28 01:01:28 2006
@@ -467,16 +467,11 @@
 def MOVUPDmr : PDI<0x11, MRMDestMem, (ops f128mem:$dst, VR128:$src),
                    "movupd {$src, $dst|$dst, $src}", []>;
 
-def MOVLPSrm : PSI<0x12, MRMSrcMem, (ops VR128:$dst, f64mem:$src),
-                   "movlps {$src, $dst|$dst, $src}", []>;
-def MOVLPSmr : PSI<0x13, MRMDestMem, (ops f64mem:$dst, VR128:$src),
-                   "movlps {$src, $dst|$dst, $src}", []>;
-def MOVLPDrm : PDI<0x12, MRMSrcMem, (ops VR128:$dst, f64mem:$src),
-                   "movlpd {$src, $dst|$dst, $src}", []>;
-def MOVLPDmr : PDI<0x13, MRMDestMem, (ops f64mem:$dst, VR128:$src),
-                   "movlpd {$src, $dst|$dst, $src}", []>;
-
 let isTwoAddress = 1 in {
+def MOVLPSrm : PSI<0x12, MRMSrcMem, (ops VR128:$dst, VR128:$src1, f64mem:$src2),
+                   "movlps {$src2, $dst|$dst, $src2}", []>;
+def MOVLPDrm : PDI<0x12, MRMSrcMem, (ops VR128:$dst, VR128:$src1, f64mem:$src2),
+                   "movlpd {$src2, $dst|$dst, $src2}", []>;
 def MOVHPSrm : PSI<0x16, MRMSrcMem, (ops VR128:$dst, VR128:$src1, f64mem:$src2),
                    "movhps {$src2, $dst|$dst, $src2}", []>;
 def MOVHPDrm : PDI<0x16, MRMSrcMem, (ops VR128:$dst, VR128:$src1, f64mem:$src2),
@@ -487,6 +482,11 @@
                              UNPCKL_shuffle_mask)))]>;
 }
 
+def MOVLPSmr : PSI<0x13, MRMDestMem, (ops f64mem:$dst, VR128:$src),
+                   "movlps {$src, $dst|$dst, $src}", []>;
+def MOVLPDmr : PDI<0x13, MRMDestMem, (ops f64mem:$dst, VR128:$src),
+                   "movlpd {$src, $dst|$dst, $src}", []>;
+
 def MOVHPSmr : PSI<0x17, MRMDestMem, (ops f64mem:$dst, VR128:$src),
                    "movhps {$src, $dst|$dst, $src}", []>;
 def MOVHPDmr : PDI<0x17, MRMDestMem, (ops f64mem:$dst, VR128:$src),





From evan.cheng at apple.com  Tue Mar 28 02:27:28 2006
From: evan.cheng at apple.com (Evan Cheng)
Date: Tue, 28 Mar 2006 02:27:28 -0600
Subject: [llvm-commits] CVS: llvm/lib/Target/X86/X86ISelLowering.cpp 
Message-ID: <200603280827.CAA20560@zion.cs.uiuc.edu>



Changes in directory llvm/lib/Target/X86:

X86ISelLowering.cpp updated: 1.138 -> 1.139
---
Log message:

Missed X86::isUNPCKHMask

---
Diffs of the changes:  (+2 -1)

 X86ISelLowering.cpp |    3 ++-
 1 files changed, 2 insertions(+), 1 deletion(-)


Index: llvm/lib/Target/X86/X86ISelLowering.cpp
diff -u llvm/lib/Target/X86/X86ISelLowering.cpp:1.138 llvm/lib/Target/X86/X86ISelLowering.cpp:1.139
--- llvm/lib/Target/X86/X86ISelLowering.cpp:1.138	Tue Mar 28 00:50:32 2006
+++ llvm/lib/Target/X86/X86ISelLowering.cpp	Tue Mar 28 02:27:15 2006
@@ -2608,5 +2608,6 @@
           X86::isSplatMask(Mask.Val) ||
           X86::isPSHUFDMask(Mask.Val) ||
           X86::isSHUFPMask(Mask.Val) ||
-          X86::isUNPCKLMask(Mask.Val));
+          X86::isUNPCKLMask(Mask.Val) ||
+          X86::isUNPCKHMask(Mask.Val);
 }





From jlaskey at apple.com  Tue Mar 28 04:17:28 2006
From: jlaskey at apple.com (Jim Laskey)
Date: Tue, 28 Mar 2006 04:17:28 -0600
Subject: [llvm-commits] CVS: llvm/lib/Target/X86/X86ISelLowering.cpp 
Message-ID: <200603281017.EAA14286@zion.cs.uiuc.edu>



Changes in directory llvm/lib/Target/X86:

X86ISelLowering.cpp updated: 1.139 -> 1.140
---
Log message:

Added missing paren on behalf of Ramana Radhakrishnan.


---
Diffs of the changes:  (+1 -1)

 X86ISelLowering.cpp |    2 +-
 1 files changed, 1 insertion(+), 1 deletion(-)


Index: llvm/lib/Target/X86/X86ISelLowering.cpp
diff -u llvm/lib/Target/X86/X86ISelLowering.cpp:1.139 llvm/lib/Target/X86/X86ISelLowering.cpp:1.140
--- llvm/lib/Target/X86/X86ISelLowering.cpp:1.139	Tue Mar 28 02:27:15 2006
+++ llvm/lib/Target/X86/X86ISelLowering.cpp	Tue Mar 28 04:17:11 2006
@@ -2609,5 +2609,5 @@
           X86::isPSHUFDMask(Mask.Val) ||
           X86::isSHUFPMask(Mask.Val) ||
           X86::isUNPCKLMask(Mask.Val) ||
-          X86::isUNPCKHMask(Mask.Val);
+          X86::isUNPCKHMask(Mask.Val));
 }





From jlaskey at apple.com  Tue Mar 28 07:45:32 2006
From: jlaskey at apple.com (Jim Laskey)
Date: Tue, 28 Mar 2006 07:45:32 -0600
Subject: [llvm-commits] 
	CVS: llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
Message-ID: <200603281345.HAA15109@zion.cs.uiuc.edu>



Changes in directory llvm/lib/CodeGen/SelectionDAG:

SelectionDAGISel.cpp updated: 1.210 -> 1.211
---
Log message:

More bulletproofing of llvm.dbg.declare.


---
Diffs of the changes:  (+1 -1)

 SelectionDAGISel.cpp |    2 +-
 1 files changed, 1 insertion(+), 1 deletion(-)


Index: llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.210 llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.211
--- llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.210	Mon Mar 27 18:40:09 2006
+++ llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp	Tue Mar 28 07:45:20 2006
@@ -1390,7 +1390,7 @@
   case Intrinsic::dbg_declare: {
     MachineDebugInfo *DebugInfo = DAG.getMachineDebugInfo();
     DbgDeclareInst &DI = cast<DbgDeclareInst>(I);
-    if (DebugInfo && DebugInfo->Verify(DI.getVariable())) {
+    if (DebugInfo && DI.getVariable() && DebugInfo->Verify(DI.getVariable())) {
       std::vector<SDOperand> Ops;
 
       SDOperand AddressOp  = getValue(DI.getAddress());





From jlaskey at apple.com  Tue Mar 28 07:48:49 2006
From: jlaskey at apple.com (Jim Laskey)
Date: Tue, 28 Mar 2006 07:48:49 -0600
Subject: [llvm-commits] CVS: llvm/lib/Target/IA64/IA64RegisterInfo.cpp
	IA64RegisterInfo.h 
Message-ID: <200603281348.HAA15167@zion.cs.uiuc.edu>



Changes in directory llvm/lib/Target/IA64:

IA64RegisterInfo.cpp updated: 1.15 -> 1.16
IA64RegisterInfo.h updated: 1.5 -> 1.6
---
Log message:

Expose base register for DwarfWriter.  Refactor code accordingly.


---
Diffs of the changes:  (+4 -12)

 IA64RegisterInfo.cpp |   13 ++-----------
 IA64RegisterInfo.h   |    3 ++-
 2 files changed, 4 insertions(+), 12 deletions(-)


Index: llvm/lib/Target/IA64/IA64RegisterInfo.cpp
diff -u llvm/lib/Target/IA64/IA64RegisterInfo.cpp:1.15 llvm/lib/Target/IA64/IA64RegisterInfo.cpp:1.16
--- llvm/lib/Target/IA64/IA64RegisterInfo.cpp:1.15	Mon Mar 27 14:18:45 2006
+++ llvm/lib/Target/IA64/IA64RegisterInfo.cpp	Tue Mar 28 07:48:33 2006
@@ -329,18 +329,9 @@
 
 }
 
-void IA64RegisterInfo::getLocation(MachineFunction &MF, unsigned Index,
-                                   MachineLocation &ML) const {
-  assert(0 && "Needs to be defined for target");
-  MachineFrameInfo *MFI = MF.getFrameInfo();
-  bool FP = hasFP(MF);
-  
-  // FIXME - Needs to handle register variables.
-  // FIXME - Faking that llvm number is same as gcc numbering.
-  ML.set(getDwarfRegNum(FP ? IA64::r5 : IA64::r12),
-         MFI->getObjectOffset(Index) + MFI->getStackSize());
+unsigned IA64RegisterInfo::getFrameRegister(MachineFunction &MF) const {
+  return getDwarfRegNum(hasFP(MF) ? IA64::r5 : IA64::r12);
 }
 
-
 #include "IA64GenRegisterInfo.inc"
 


Index: llvm/lib/Target/IA64/IA64RegisterInfo.h
diff -u llvm/lib/Target/IA64/IA64RegisterInfo.h:1.5 llvm/lib/Target/IA64/IA64RegisterInfo.h:1.6
--- llvm/lib/Target/IA64/IA64RegisterInfo.h:1.5	Thu Mar 23 12:12:57 2006
+++ llvm/lib/Target/IA64/IA64RegisterInfo.h	Tue Mar 28 07:48:33 2006
@@ -49,7 +49,8 @@
   void emitPrologue(MachineFunction &MF) const;
   void emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const;
 
-  void getLocation(MachineFunction &MF, unsigned Index, MachineLocation &ML) const;
+  // Debug information queries.
+  unsigned getFrameRegister(MachineFunction &MF) const;
 };
 
 } // End llvm namespace





From jlaskey at apple.com  Tue Mar 28 07:48:49 2006
From: jlaskey at apple.com (Jim Laskey)
Date: Tue, 28 Mar 2006 07:48:49 -0600
Subject: [llvm-commits] CVS: llvm/include/llvm/Target/MRegisterInfo.h 
Message-ID: <200603281348.HAA15171@zion.cs.uiuc.edu>



Changes in directory llvm/include/llvm/Target:

MRegisterInfo.h updated: 1.72 -> 1.73
---
Log message:

Expose base register for DwarfWriter.  Refactor code accordingly.


---
Diffs of the changes:  (+11 -1)

 MRegisterInfo.h |   12 +++++++++++-
 1 files changed, 11 insertions(+), 1 deletion(-)


Index: llvm/include/llvm/Target/MRegisterInfo.h
diff -u llvm/include/llvm/Target/MRegisterInfo.h:1.72 llvm/include/llvm/Target/MRegisterInfo.h:1.73
--- llvm/include/llvm/Target/MRegisterInfo.h:1.72	Fri Mar 24 10:18:42 2006
+++ llvm/include/llvm/Target/MRegisterInfo.h	Tue Mar 28 07:48:33 2006
@@ -343,10 +343,20 @@
   virtual void emitEpilogue(MachineFunction &MF,
                             MachineBasicBlock &MBB) const = 0;
                             
+  //===--------------------------------------------------------------------===//
+  /// Debug information queries.
+
+  /// getFrameRegister - This method should return the register used as a base
+  /// for values allocated in the current stack frame.  This value should be
+  /// returned as a dwarf register number (getDwarfRegNum.)
+  virtual unsigned getFrameRegister(MachineFunction &MF) const = 0;
+                            
   /// getLocation - This method should return the actual location of a frame
   /// variable given the frame index.  The location is returned in ML.
+  /// Subclasses should override this method for special handling of frame
+  /// variables and call MRegisterInfo::getLocation for the default action.
   virtual void getLocation(MachineFunction &MF, unsigned Index,
-                          MachineLocation &ML) const = 0;
+                           MachineLocation &ML) const;
 };
 
 // This is useful when building DenseMaps keyed on virtual registers





From jlaskey at apple.com  Tue Mar 28 07:48:50 2006
From: jlaskey at apple.com (Jim Laskey)
Date: Tue, 28 Mar 2006 07:48:50 -0600
Subject: [llvm-commits] CVS: llvm/lib/Target/X86/X86RegisterInfo.cpp
	X86RegisterInfo.h 
Message-ID: <200603281348.HAA15177@zion.cs.uiuc.edu>



Changes in directory llvm/lib/Target/X86:

X86RegisterInfo.cpp updated: 1.132 -> 1.133
X86RegisterInfo.h updated: 1.35 -> 1.36
---
Log message:

Expose base register for DwarfWriter.  Refactor code accordingly.


---
Diffs of the changes:  (+4 -11)

 X86RegisterInfo.cpp |   11 ++---------
 X86RegisterInfo.h   |    4 ++--
 2 files changed, 4 insertions(+), 11 deletions(-)


Index: llvm/lib/Target/X86/X86RegisterInfo.cpp
diff -u llvm/lib/Target/X86/X86RegisterInfo.cpp:1.132 llvm/lib/Target/X86/X86RegisterInfo.cpp:1.133
--- llvm/lib/Target/X86/X86RegisterInfo.cpp:1.132	Mon Mar 27 14:18:45 2006
+++ llvm/lib/Target/X86/X86RegisterInfo.cpp	Tue Mar 28 07:48:33 2006
@@ -686,15 +686,8 @@
   }
 }
 
-void X86RegisterInfo::getLocation(MachineFunction &MF, unsigned Index,
-                                  MachineLocation &ML) const {
-  MachineFrameInfo *MFI = MF.getFrameInfo();
-  bool FP = hasFP(MF);
-  
-  // FIXME - Needs to handle register variables.
-  // FIXME - Hardcoding gcc numbering.
-  ML.set(getDwarfRegNum(FP ? X86::EBP : X86::ESP),
-         MFI->getObjectOffset(Index) + MFI->getStackSize());
+unsigned X86RegisterInfo::getFrameRegister(MachineFunction &MF) const {
+  return getDwarfRegNum(hasFP(MF) ? X86::EBP : X86::ESP);
 }
 
 #include "X86GenRegisterInfo.inc"


Index: llvm/lib/Target/X86/X86RegisterInfo.h
diff -u llvm/lib/Target/X86/X86RegisterInfo.h:1.35 llvm/lib/Target/X86/X86RegisterInfo.h:1.36
--- llvm/lib/Target/X86/X86RegisterInfo.h:1.35	Thu Mar 23 12:12:57 2006
+++ llvm/lib/Target/X86/X86RegisterInfo.h	Tue Mar 28 07:48:33 2006
@@ -63,8 +63,8 @@
   void emitPrologue(MachineFunction &MF) const;
   void emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const;
 
-  void getLocation(MachineFunction &MF, unsigned Index,
-                   MachineLocation &ML) const;
+  // Debug information queries.
+  unsigned getFrameRegister(MachineFunction &MF) const;
 };
 
 } // End llvm namespace





From jlaskey at apple.com  Tue Mar 28 07:48:50 2006
From: jlaskey at apple.com (Jim Laskey)
Date: Tue, 28 Mar 2006 07:48:50 -0600
Subject: [llvm-commits] CVS: llvm/lib/Target/SparcV9/SparcV9RegisterInfo.cpp
	SparcV9RegisterInfo.h 
Message-ID: <200603281348.HAA15183@zion.cs.uiuc.edu>



Changes in directory llvm/lib/Target/SparcV9:

SparcV9RegisterInfo.cpp updated: 1.11 -> 1.12
SparcV9RegisterInfo.h updated: 1.10 -> 1.11
---
Log message:

Expose base register for DwarfWriter.  Refactor code accordingly.


---
Diffs of the changes:  (+5 -4)

 SparcV9RegisterInfo.cpp |    4 ++--
 SparcV9RegisterInfo.h   |    5 +++--
 2 files changed, 5 insertions(+), 4 deletions(-)


Index: llvm/lib/Target/SparcV9/SparcV9RegisterInfo.cpp
diff -u llvm/lib/Target/SparcV9/SparcV9RegisterInfo.cpp:1.11 llvm/lib/Target/SparcV9/SparcV9RegisterInfo.cpp:1.12
--- llvm/lib/Target/SparcV9/SparcV9RegisterInfo.cpp:1.11	Thu Mar 23 12:12:57 2006
+++ llvm/lib/Target/SparcV9/SparcV9RegisterInfo.cpp	Tue Mar 28 07:48:33 2006
@@ -318,7 +318,7 @@
 }
 
 
-void SparcV9RegisterInfo::getLocation(MachineFunction &MF, unsigned Index,
-                                      MachineLocation &ML) const {
+unsigned SparcV9RegisterInfo::getFrameRegister(MachineFunction &MF) const {
   abort ();
+  return 0;
 }


Index: llvm/lib/Target/SparcV9/SparcV9RegisterInfo.h
diff -u llvm/lib/Target/SparcV9/SparcV9RegisterInfo.h:1.10 llvm/lib/Target/SparcV9/SparcV9RegisterInfo.h:1.11
--- llvm/lib/Target/SparcV9/SparcV9RegisterInfo.h:1.10	Thu Mar 23 12:12:57 2006
+++ llvm/lib/Target/SparcV9/SparcV9RegisterInfo.h	Tue Mar 28 07:48:33 2006
@@ -44,8 +44,9 @@
   void eliminateFrameIndex (MachineBasicBlock::iterator MI) const;
   void emitPrologue (MachineFunction &MF) const;
   void emitEpilogue (MachineFunction &MF, MachineBasicBlock &MBB) const;
-  void getLocation(MachineFunction &MF, unsigned Index,
-                   MachineLocation &ML) const;
+  
+  // Debug information queries.
+  unsigned getFrameRegister(MachineFunction &MF) const;
 };
 
 } // End llvm namespace





From jlaskey at apple.com  Tue Mar 28 07:48:51 2006
From: jlaskey at apple.com (Jim Laskey)
Date: Tue, 28 Mar 2006 07:48:51 -0600
Subject: [llvm-commits] CVS: llvm/lib/Target/MRegisterInfo.cpp 
Message-ID: <200603281348.HAA15190@zion.cs.uiuc.edu>



Changes in directory llvm/lib/Target:

MRegisterInfo.cpp updated: 1.12 -> 1.13
---
Log message:

Expose base register for DwarfWriter.  Refactor code accordingly.


---
Diffs of the changes:  (+16 -0)

 MRegisterInfo.cpp |   16 ++++++++++++++++
 1 files changed, 16 insertions(+)


Index: llvm/lib/Target/MRegisterInfo.cpp
diff -u llvm/lib/Target/MRegisterInfo.cpp:1.12 llvm/lib/Target/MRegisterInfo.cpp:1.13
--- llvm/lib/Target/MRegisterInfo.cpp:1.12	Wed Feb  1 12:10:56 2006
+++ llvm/lib/Target/MRegisterInfo.cpp	Tue Mar 28 07:48:33 2006
@@ -12,6 +12,11 @@
 //===----------------------------------------------------------------------===//
 
 #include "llvm/Target/MRegisterInfo.h"
+
+#include "llvm/CodeGen/MachineFunction.h"
+#include "llvm/CodeGen/MachineFrameInfo.h"
+#include "llvm/CodeGen/MachineLocation.h"
+
 using namespace llvm;
 
 MRegisterInfo::MRegisterInfo(const TargetRegisterDesc *D, unsigned NR,
@@ -38,3 +43,14 @@
   }
   return Allocatable;
 }
+
+/// getLocation - This method should return the actual location of a frame
+/// variable given the frame index.  The location is returned in ML.
+/// Subclasses should override this method for special handling of frame
+/// variables and then call MRegisterInfo::getLocation for the default action.
+void MRegisterInfo::getLocation(MachineFunction &MF, unsigned Index,
+                        MachineLocation &ML) const {
+  MachineFrameInfo *MFI = MF.getFrameInfo();
+  ML.set(getFrameRegister(MF),
+         MFI->getObjectOffset(Index) + MFI->getStackSize());
+}





From jlaskey at apple.com  Tue Mar 28 07:48:51 2006
From: jlaskey at apple.com (Jim Laskey)
Date: Tue, 28 Mar 2006 07:48:51 -0600
Subject: [llvm-commits] CVS: llvm/lib/Target/Sparc/SparcRegisterInfo.cpp
	SparcRegisterInfo.h 
Message-ID: <200603281348.HAA15191@zion.cs.uiuc.edu>



Changes in directory llvm/lib/Target/Sparc:

SparcRegisterInfo.cpp updated: 1.39 -> 1.40
SparcRegisterInfo.h updated: 1.10 -> 1.11
---
Log message:

Expose base register for DwarfWriter.  Refactor code accordingly.


---
Diffs of the changes:  (+4 -11)

 SparcRegisterInfo.cpp |   11 ++---------
 SparcRegisterInfo.h   |    4 ++--
 2 files changed, 4 insertions(+), 11 deletions(-)


Index: llvm/lib/Target/Sparc/SparcRegisterInfo.cpp
diff -u llvm/lib/Target/Sparc/SparcRegisterInfo.cpp:1.39 llvm/lib/Target/Sparc/SparcRegisterInfo.cpp:1.40
--- llvm/lib/Target/Sparc/SparcRegisterInfo.cpp:1.39	Mon Mar 27 14:18:45 2006
+++ llvm/lib/Target/Sparc/SparcRegisterInfo.cpp	Tue Mar 28 07:48:33 2006
@@ -200,15 +200,8 @@
   BuildMI(MBB, MBBI, SP::RESTORErr, 2, SP::G0).addReg(SP::G0).addReg(SP::G0);
 }
 
-void SparcRegisterInfo::getLocation(MachineFunction &MF, unsigned Index,
-                                  MachineLocation &ML) const {
-  assert(0 && "Needs to be defined for target");
-  MachineFrameInfo *MFI = MF.getFrameInfo();
-  
-  // FIXME - Needs to handle register variables.
-  // FIXME - Faking that llvm number is same as gcc numbering.
-  ML.set(getDwarfRegNum(SP::G1),
-         MFI->getObjectOffset(Index) + MFI->getStackSize());
+unsigned SparcRegisterInfo::getFrameRegister(MachineFunction &MF) const {
+  return getDwarfRegNum(SP::G1);
 }
 
 #include "SparcGenRegisterInfo.inc"


Index: llvm/lib/Target/Sparc/SparcRegisterInfo.h
diff -u llvm/lib/Target/Sparc/SparcRegisterInfo.h:1.10 llvm/lib/Target/Sparc/SparcRegisterInfo.h:1.11
--- llvm/lib/Target/Sparc/SparcRegisterInfo.h:1.10	Thu Mar 23 12:12:57 2006
+++ llvm/lib/Target/Sparc/SparcRegisterInfo.h	Tue Mar 28 07:48:33 2006
@@ -57,8 +57,8 @@
   void emitPrologue(MachineFunction &MF) const;
   void emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const;
   
-  void getLocation(MachineFunction &MF, unsigned Index,
-                   MachineLocation &ML) const;
+  // Debug information queries.
+  unsigned getFrameRegister(MachineFunction &MF) const;
 };
 
 } // end namespace llvm





From jlaskey at apple.com  Tue Mar 28 07:48:51 2006
From: jlaskey at apple.com (Jim Laskey)
Date: Tue, 28 Mar 2006 07:48:51 -0600
Subject: [llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
	PPCRegisterInfo.h 
Message-ID: <200603281348.HAA15205@zion.cs.uiuc.edu>



Changes in directory llvm/lib/Target/PowerPC:

PPCRegisterInfo.cpp updated: 1.51 -> 1.52
PPCRegisterInfo.h updated: 1.11 -> 1.12
---
Log message:

Expose base register for DwarfWriter.  Refactor code accordingly.


---
Diffs of the changes:  (+4 -11)

 PPCRegisterInfo.cpp |   11 ++---------
 PPCRegisterInfo.h   |    4 ++--
 2 files changed, 4 insertions(+), 11 deletions(-)


Index: llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
diff -u llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp:1.51 llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp:1.52
--- llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp:1.51	Mon Mar 27 14:18:45 2006
+++ llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp	Tue Mar 28 07:48:33 2006
@@ -447,15 +447,8 @@
   }
 }
 
-void PPCRegisterInfo::getLocation(MachineFunction &MF, unsigned Index,
-                                  MachineLocation &ML) const {
-  MachineFrameInfo *MFI = MF.getFrameInfo();
-  bool FP = hasFP(MF);
-  
-  // FIXME - Needs to handle register variables.
-  // FIXME - Faking that llvm number is same as gcc numbering.
-  ML.set(getDwarfRegNum(FP ? PPC::R31 : PPC::R1),
-         MFI->getObjectOffset(Index) + MFI->getStackSize());
+unsigned PPCRegisterInfo::getFrameRegister(MachineFunction &MF) const {
+  return getDwarfRegNum(hasFP(MF) ? PPC::R31 : PPC::R1);
 }
 
 #include "PPCGenRegisterInfo.inc"


Index: llvm/lib/Target/PowerPC/PPCRegisterInfo.h
diff -u llvm/lib/Target/PowerPC/PPCRegisterInfo.h:1.11 llvm/lib/Target/PowerPC/PPCRegisterInfo.h:1.12
--- llvm/lib/Target/PowerPC/PPCRegisterInfo.h:1.11	Thu Mar 23 12:12:57 2006
+++ llvm/lib/Target/PowerPC/PPCRegisterInfo.h	Tue Mar 28 07:48:33 2006
@@ -56,8 +56,8 @@
   void emitPrologue(MachineFunction &MF) const;
   void emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const;
 
-  void getLocation(MachineFunction &MF, unsigned Index,
-                   MachineLocation &ML) const;
+  // Debug information queries.
+  unsigned getFrameRegister(MachineFunction &MF) const;
 };
 
 } // end namespace llvm





From jlaskey at apple.com  Tue Mar 28 07:48:51 2006
From: jlaskey at apple.com (Jim Laskey)
Date: Tue, 28 Mar 2006 07:48:51 -0600
Subject: [llvm-commits] CVS: llvm/lib/Target/Alpha/AlphaRegisterInfo.cpp
	AlphaRegisterInfo.h 
Message-ID: <200603281348.HAA15199@zion.cs.uiuc.edu>



Changes in directory llvm/lib/Target/Alpha:

AlphaRegisterInfo.cpp updated: 1.38 -> 1.39
AlphaRegisterInfo.h updated: 1.10 -> 1.11
---
Log message:

Expose base register for DwarfWriter.  Refactor code accordingly.


---
Diffs of the changes:  (+4 -12)

 AlphaRegisterInfo.cpp |   12 ++----------
 AlphaRegisterInfo.h   |    4 ++--
 2 files changed, 4 insertions(+), 12 deletions(-)


Index: llvm/lib/Target/Alpha/AlphaRegisterInfo.cpp
diff -u llvm/lib/Target/Alpha/AlphaRegisterInfo.cpp:1.38 llvm/lib/Target/Alpha/AlphaRegisterInfo.cpp:1.39
--- llvm/lib/Target/Alpha/AlphaRegisterInfo.cpp:1.38	Mon Mar 27 14:18:45 2006
+++ llvm/lib/Target/Alpha/AlphaRegisterInfo.cpp	Tue Mar 28 07:48:33 2006
@@ -354,16 +354,8 @@
      }
 }
 
-void AlphaRegisterInfo::getLocation(MachineFunction &MF, unsigned Index,
-                                    MachineLocation &ML) const {
-  assert(0 && "Needs to be defined for target");
-  MachineFrameInfo *MFI = MF.getFrameInfo();
-  bool FP = hasFP(MF);
-  
-  // FIXME - Needs to handle register variables.
-  // FIXME - Faking that llvm number is same as gcc numbering.
-  ML.set(getDwarfRegNum(FP ? Alpha::R15 : Alpha::R30),
-         MFI->getObjectOffset(Index) + MFI->getStackSize());
+unsigned AlphaRegisterInfo::getFrameRegister(MachineFunction &MF) const {
+  return getDwarfRegNum(hasFP(MF) ? Alpha::R15 : Alpha::R30);
 }
 
 #include "AlphaGenRegisterInfo.inc"


Index: llvm/lib/Target/Alpha/AlphaRegisterInfo.h
diff -u llvm/lib/Target/Alpha/AlphaRegisterInfo.h:1.10 llvm/lib/Target/Alpha/AlphaRegisterInfo.h:1.11
--- llvm/lib/Target/Alpha/AlphaRegisterInfo.h:1.10	Thu Mar 23 12:12:57 2006
+++ llvm/lib/Target/Alpha/AlphaRegisterInfo.h	Tue Mar 28 07:48:33 2006
@@ -53,8 +53,8 @@
   void emitPrologue(MachineFunction &MF) const;
   void emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const;
 
-  void getLocation(MachineFunction &MF, unsigned Index, MachineLocation &ML) const;
-
+   // Debug information queries.
+  unsigned getFrameRegister(MachineFunction &MF) const;
 
   static std::string getPrettyName(unsigned reg);
 };





From jlaskey at apple.com  Tue Mar 28 08:58:45 2006
From: jlaskey at apple.com (Jim Laskey)
Date: Tue, 28 Mar 2006 08:58:45 -0600
Subject: [llvm-commits] CVS: llvm/include/llvm/CodeGen/DwarfWriter.h 
Message-ID: <200603281458.IAA15441@zion.cs.uiuc.edu>



Changes in directory llvm/include/llvm/CodeGen:

DwarfWriter.h updated: 1.31 -> 1.32
---
Log message:

Refactor address attributes.  Add base register to frame info.


---
Diffs of the changes:  (+5 -0)

 DwarfWriter.h |    5 +++++
 1 files changed, 5 insertions(+)


Index: llvm/include/llvm/CodeGen/DwarfWriter.h
diff -u llvm/include/llvm/CodeGen/DwarfWriter.h:1.31 llvm/include/llvm/CodeGen/DwarfWriter.h:1.32
--- llvm/include/llvm/CodeGen/DwarfWriter.h:1.31	Thu Mar 23 17:02:34 2006
+++ llvm/include/llvm/CodeGen/DwarfWriter.h	Tue Mar 28 08:58:32 2006
@@ -41,6 +41,7 @@
 class DIEAbbrev;
 class GlobalVariableDesc;
 class MachineDebugInfo;
+class MachineLocation;
 class MachineFunction;
 class Module;
 class SubprogramDesc;
@@ -321,6 +322,10 @@
   /// entry. 
   void AddSourceLine(DIE *Die, CompileUnitDesc *File, unsigned Line);
 
+  /// AddAddress - Add an address attribute to a die based on the location
+  /// provided.
+  void AddAddress(DIE *Die, unsigned Attribute, MachineLocation &Location);
+
   /// NewType - Create a new type DIE.
   ///
   DIE *NewType(DIE *Context, TypeDesc *TyDesc, CompileUnit *Unit);





From jlaskey at apple.com  Tue Mar 28 08:58:45 2006
From: jlaskey at apple.com (Jim Laskey)
Date: Tue, 28 Mar 2006 08:58:45 -0600
Subject: [llvm-commits] CVS: llvm/lib/CodeGen/DwarfWriter.cpp 
Message-ID: <200603281458.IAA15445@zion.cs.uiuc.edu>



Changes in directory llvm/lib/CodeGen:

DwarfWriter.cpp updated: 1.52 -> 1.53
---
Log message:

Refactor address attributes.  Add base register to frame info.


---
Diffs of the changes:  (+19 -13)

 DwarfWriter.cpp |   32 +++++++++++++++++++-------------
 1 files changed, 19 insertions(+), 13 deletions(-)


Index: llvm/lib/CodeGen/DwarfWriter.cpp
diff -u llvm/lib/CodeGen/DwarfWriter.cpp:1.52 llvm/lib/CodeGen/DwarfWriter.cpp:1.53
--- llvm/lib/CodeGen/DwarfWriter.cpp:1.52	Fri Mar 24 15:10:36 2006
+++ llvm/lib/CodeGen/DwarfWriter.cpp	Tue Mar 28 08:58:32 2006
@@ -1213,6 +1213,21 @@
   }
 }
 
+/// AddAddress - Add an address attribute to a die based on the location
+/// provided.
+void DwarfWriter::AddAddress(DIE *Die, unsigned Attribute,
+                             MachineLocation &Location) {
+  DIEBlock *Block = new DIEBlock();
+  if (Location.isRegister()) {
+    Block->AddUInt(DW_FORM_data1, DW_OP_reg0 + Location.getRegister());
+  } else {
+    Block->AddUInt(DW_FORM_data1, DW_OP_breg0 + Location.getRegister());
+    Block->AddUInt(DW_FORM_sdata, Location.getOffset());
+  }
+  Block->ComputeSize(*this);
+  Die->AddBlock(Attribute, 0, Block);
+}
+
 /// getDieMapSlotFor - Returns the debug information entry map slot for the
 /// specified debug descriptor.
 DIE *&DwarfWriter::getDieMapSlotFor(DebugInfoDesc *DD) {
@@ -1518,7 +1533,6 @@
   return SubprogramDie;
 }
 
-
 /// NewScopeVariable - Create a new scope variable.
 ///
 DIE *DwarfWriter::NewScopeVariable(DebugVariable *DV, CompileUnit *Unit) {
@@ -1545,20 +1559,10 @@
   DIE *Type = NewType(Unit->getDie(), VD->getType(), Unit); 
   VariableDie->AddDIEntry(DW_AT_type, DW_FORM_ref4, Type);
   
-  // Get variable address.
+  // Add variable address.
   MachineLocation Location;
   Asm->TM.getRegisterInfo()->getLocation(*MF, DV->getFrameIndex(), Location);
-  
-  // Add computation for variable.
-  DIEBlock *Block = new DIEBlock();
-  if (Location.isRegister()) {
-    Block->AddUInt(DW_FORM_data1, DW_OP_reg0 + Location.getRegister());
-  } else {
-    Block->AddUInt(DW_FORM_data1, DW_OP_breg0 + Location.getRegister());
-    Block->AddUInt(DW_FORM_sdata, Location.getOffset());
-  }
-  Block->ComputeSize(*this);
-  VariableDie->AddBlock(DW_AT_location, 0, Block);
+  AddAddress(VariableDie, DW_AT_location, Location);
   
   return VariableDie;
 }
@@ -1628,6 +1632,8 @@
                   DWLabel("func_begin", SubprogramCount));
   SPDie->AddLabel(DW_AT_high_pc, DW_FORM_addr,
                   DWLabel("func_end", SubprogramCount));
+  MachineLocation Location(Asm->TM.getRegisterInfo()->getFrameRegister(*MF));
+  AddAddress(SPDie, DW_AT_frame_base, Location);
                   
   ConstructScope(RootScope, SPDie, Unit);
 }





From lattner at cs.uiuc.edu  Tue Mar 28 12:56:35 2006
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Tue, 28 Mar 2006 12:56:35 -0600
Subject: [llvm-commits] CVS: llvm/lib/Target/PowerPC/README_ALTIVEC.txt 
Message-ID: <200603281856.MAA16943@zion.cs.uiuc.edu>



Changes in directory llvm/lib/Target/PowerPC:

README_ALTIVEC.txt updated: 1.4 -> 1.5
---
Log message:

add a note


---
Diffs of the changes:  (+10 -0)

 README_ALTIVEC.txt |   10 ++++++++++
 1 files changed, 10 insertions(+)


Index: llvm/lib/Target/PowerPC/README_ALTIVEC.txt
diff -u llvm/lib/Target/PowerPC/README_ALTIVEC.txt:1.4 llvm/lib/Target/PowerPC/README_ALTIVEC.txt:1.5
--- llvm/lib/Target/PowerPC/README_ALTIVEC.txt:1.4	Mon Mar 27 22:15:58 2006
+++ llvm/lib/Target/PowerPC/README_ALTIVEC.txt	Tue Mar 28 12:56:23 2006
@@ -134,4 +134,14 @@
 2. Identical operations in different types are not getting CSE'd (e.g. 
    { 0U, 0U, 0U, 0U } and {0.0, 0.0, 0.0, 0.0}.
 
+//===----------------------------------------------------------------------===//
+
+Two identical comparisons in predicate and nonpredicate form like this:
+
+a = vec_cmpb(x, y);
+b = vec_any_out(x, y);
+
+Should turn into one "." compare instruction, not a dot and "nondot" form.
+
+//===----------------------------------------------------------------------===//
 





From lattner at cs.uiuc.edu  Tue Mar 28 13:05:01 2006
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Tue, 28 Mar 2006 13:05:01 -0600
Subject: [llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp 
Message-ID: <200603281905.NAA17128@zion.cs.uiuc.edu>



Changes in directory llvm/lib/CodeGen/SelectionDAG:

SelectionDAG.cpp updated: 1.290 -> 1.291
---
Log message:

Add an assertion


---
Diffs of the changes:  (+2 -0)

 SelectionDAG.cpp |    2 ++
 1 files changed, 2 insertions(+)


Index: llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp:1.290 llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp:1.291
--- llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp:1.290	Mon Mar 27 18:40:09 2006
+++ llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp	Tue Mar 28 13:04:49 2006
@@ -634,6 +634,8 @@
 
 SDOperand SelectionDAG::getConstant(uint64_t Val, MVT::ValueType VT) {
   assert(MVT::isInteger(VT) && "Cannot create FP integer constant!");
+  assert(!MVT::isVector(VT) && "Cannot create Vector ConstantSDNodes!");
+  
   // Mask out any bits that are not valid for this constant.
   if (VT != MVT::i64)
     Val &= ((uint64_t)1 << MVT::getSizeInBits(VT)) - 1;





From lattner at cs.uiuc.edu  Tue Mar 28 13:11:17 2006
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Tue, 28 Mar 2006 13:11:17 -0600
Subject: [llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp 
Message-ID: <200603281911.NAA17266@zion.cs.uiuc.edu>



Changes in directory llvm/lib/CodeGen/SelectionDAG:

DAGCombiner.cpp updated: 1.129 -> 1.130
---
Log message:

Don't crash on X^X if X is a vector.  Instead, produce a vector of zeros.


---
Diffs of the changes:  (+10 -2)

 DAGCombiner.cpp |   12 ++++++++++--
 1 files changed, 10 insertions(+), 2 deletions(-)


Index: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.129 llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.130
--- llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.129	Sat Mar 25 16:19:00 2006
+++ llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp	Tue Mar 28 13:11:05 2006
@@ -1396,8 +1396,16 @@
                          DAG.getConstant(N1C->getValue()^N01C->getValue(), VT));
   }
   // fold (xor x, x) -> 0
-  if (N0 == N1)
-    return DAG.getConstant(0, VT);
+  if (N0 == N1) {
+    if (!MVT::isVector(VT)) {
+      return DAG.getConstant(0, VT);
+    } else if (!AfterLegalize || TLI.isOperationLegal(ISD::BUILD_VECTOR, VT)) {
+      // Produce a vector of zeros.
+      SDOperand El = DAG.getConstant(0, MVT::getVectorBaseType(VT));
+      std::vector<SDOperand> Ops(MVT::getVectorNumElements(VT), El);
+      return DAG.getNode(ISD::BUILD_VECTOR, VT, Ops);
+    }
+  }
   // fold (xor (zext x), (zext y)) -> (zext (xor x, y))
   if (N0.getOpcode() == ISD::ZERO_EXTEND && 
       N1.getOpcode() == ISD::ZERO_EXTEND &&





From lattner at cs.uiuc.edu  Tue Mar 28 13:54:23 2006
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Tue, 28 Mar 2006 13:54:23 -0600
Subject: [llvm-commits] CVS: llvm/include/llvm/CodeGen/SelectionDAGNodes.h 
Message-ID: <200603281954.NAA17480@zion.cs.uiuc.edu>



Changes in directory llvm/include/llvm/CodeGen:

SelectionDAGNodes.h updated: 1.124 -> 1.125
---
Log message:

Add a new node


---
Diffs of the changes:  (+9 -0)

 SelectionDAGNodes.h |    9 +++++++++
 1 files changed, 9 insertions(+)


Index: llvm/include/llvm/CodeGen/SelectionDAGNodes.h
diff -u llvm/include/llvm/CodeGen/SelectionDAGNodes.h:1.124 llvm/include/llvm/CodeGen/SelectionDAGNodes.h:1.125
--- llvm/include/llvm/CodeGen/SelectionDAGNodes.h:1.124	Mon Mar 27 18:39:06 2006
+++ llvm/include/llvm/CodeGen/SelectionDAGNodes.h	Tue Mar 28 13:54:11 2006
@@ -189,6 +189,15 @@
     /// element number IDX.
     EXTRACT_VECTOR_ELT,
     
+    /// VVECTOR_SHUFFLE(VEC1, VEC2, SHUFFLEVEC, COUNT,TYPE) - Returns a vector,
+    /// of the same type as VEC1/VEC2.  SHUFFLEVEC is a VBUILD_VECTOR of
+    /// constant int values that indicate which value each result element will
+    /// get.  The elements of VEC1/VEC2 are enumerated in order.  This is quite
+    /// similar to the Altivec 'vperm' instruction, except that the indices must
+    /// be constants and are in terms of the element size of VEC1/VEC2, not in
+    /// terms of bytes.
+    VVECTOR_SHUFFLE,
+
     /// VECTOR_SHUFFLE(VEC1, VEC2, SHUFFLEVEC) - Returns a vector, of the same
     /// type as VEC1/VEC2.  SHUFFLEVEC is a BUILD_VECTOR of constant int values
     /// (regardless of whether its datatype is legal or not) that indicate





From lattner at cs.uiuc.edu  Tue Mar 28 13:54:54 2006
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Tue, 28 Mar 2006 13:54:54 -0600
Subject: [llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp 
Message-ID: <200603281954.NAA17560@zion.cs.uiuc.edu>



Changes in directory llvm/lib/CodeGen/SelectionDAG:

SelectionDAG.cpp updated: 1.291 -> 1.292
---
Log message:

new node


---
Diffs of the changes:  (+1 -0)

 SelectionDAG.cpp |    1 +
 1 files changed, 1 insertion(+)


Index: llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp:1.291 llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp:1.292
--- llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp:1.291	Tue Mar 28 13:04:49 2006
+++ llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp	Tue Mar 28 13:54:42 2006
@@ -2761,6 +2761,7 @@
   case ISD::SCALAR_TO_VECTOR:   return "scalar_to_vector";
   case ISD::VBUILD_VECTOR: return "vbuild_vector";
   case ISD::VECTOR_SHUFFLE: return "vector_shuffle";
+  case ISD::VVECTOR_SHUFFLE: return "vvector_shuffle";
   case ISD::VBIT_CONVERT: return "vbit_convert";
   case ISD::ADDC:        return "addc";
   case ISD::ADDE:        return "adde";





From lattner at cs.uiuc.edu  Tue Mar 28 14:24:55 2006
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Tue, 28 Mar 2006 14:24:55 -0600
Subject: [llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp 
Message-ID: <200603282024.OAA18528@zion.cs.uiuc.edu>



Changes in directory llvm/lib/CodeGen/SelectionDAG:

LegalizeDAG.cpp updated: 1.341 -> 1.342
---
Log message:

Teach Legalize how to pack VVECTOR_SHUFFLE nodes into VECTOR_SHUFFLE nodes.


---
Diffs of the changes:  (+21 -0)

 LegalizeDAG.cpp |   21 +++++++++++++++++++++
 1 files changed, 21 insertions(+)


Index: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.341 llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.342
--- llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.341	Mon Mar 27 18:40:09 2006
+++ llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp	Tue Mar 28 14:24:43 2006
@@ -4532,6 +4532,27 @@
                            Node->getOperand(1), Node->getOperand(2));
     }
     break;
+  case ISD::VVECTOR_SHUFFLE:
+    if (!MVT::isVector(NewVT)) {
+      // Returning a scalar?  Figure out if it is the LHS or RHS and return it.
+      SDOperand EltNum = Node->getOperand(2).getOperand(0);
+      if (cast<ConstantSDNode>(EltNum)->getValue())
+        Result = PackVectorOp(Node->getOperand(1), NewVT);
+      else
+        Result = PackVectorOp(Node->getOperand(0), NewVT);
+    } else {
+      // Otherwise, return a VECTOR_SHUFFLE node.  First convert the index
+      // vector from a VBUILD_VECTOR to a BUILD_VECTOR.
+      std::vector<SDOperand> BuildVecIdx(Node->getOperand(2).Val->op_begin(),
+                                         Node->getOperand(2).Val->op_end()-2);
+      MVT::ValueType BVT = MVT::getIntVectorWithNumElements(BuildVecIdx.size());
+      SDOperand BV = DAG.getNode(ISD::BUILD_VECTOR, BVT, BuildVecIdx);
+      
+      Result = DAG.getNode(ISD::VECTOR_SHUFFLE, NewVT,
+                           PackVectorOp(Node->getOperand(0), NewVT),
+                           PackVectorOp(Node->getOperand(1), NewVT), BV);
+    }
+    break;
   case ISD::VBIT_CONVERT:
     if (Op.getOperand(0).getValueType() != MVT::Vector)
       Result = DAG.getNode(ISD::BIT_CONVERT, NewVT, Op.getOperand(0));





From lattner at cs.uiuc.edu  Tue Mar 28 14:28:49 2006
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Tue, 28 Mar 2006 14:28:49 -0600
Subject: [llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp 
Message-ID: <200603282028.OAA18639@zion.cs.uiuc.edu>



Changes in directory llvm/lib/CodeGen/SelectionDAG:

DAGCombiner.cpp updated: 1.130 -> 1.131
---
Log message:

Turn a series of extract_element's feeding a build_vector into a
vector_shuffle node.  For this:

void test(__m128 *res, __m128 *A, __m128 *B) {
  *res = _mm_unpacklo_ps(*A, *B);
}

we now produce this code:

_test:
        movl 8(%esp), %eax
        movaps (%eax), %xmm0
        movl 12(%esp), %eax
        unpcklps (%eax), %xmm0
        movl 4(%esp), %eax
        movaps %xmm0, (%eax)
        ret

instead of this:

_test:
        subl $76, %esp
        movl 88(%esp), %eax
        movaps (%eax), %xmm0
        movaps %xmm0, (%esp)
        movaps %xmm0, 32(%esp)
        movss 4(%esp), %xmm0
        movss 32(%esp), %xmm1
        unpcklps %xmm0, %xmm1
        movl 84(%esp), %eax
        movaps (%eax), %xmm0
        movaps %xmm0, 16(%esp)
        movaps %xmm0, 48(%esp)
        movss 20(%esp), %xmm0
        movss 48(%esp), %xmm2
        unpcklps %xmm0, %xmm2
        unpcklps %xmm1, %xmm2
        movl 80(%esp), %eax
        movaps %xmm2, (%eax)
        addl $76, %esp
        ret

GCC produces this (with -fomit-frame-pointer):

_test:
        subl    $12, %esp
        movl    20(%esp), %eax
        movaps  (%eax), %xmm0
        movl    24(%esp), %eax
        unpcklps        (%eax), %xmm0
        movl    16(%esp), %eax
        movaps  %xmm0, (%eax)
        addl    $12, %esp
        ret



---
Diffs of the changes:  (+86 -0)

 DAGCombiner.cpp |   86 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++
 1 files changed, 86 insertions(+)


Index: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.130 llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.131
--- llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.130	Tue Mar 28 13:11:05 2006
+++ llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp	Tue Mar 28 14:28:38 2006
@@ -211,6 +211,7 @@
     SDOperand visitSTORE(SDNode *N);
     SDOperand visitINSERT_VECTOR_ELT(SDNode *N);
     SDOperand visitVINSERT_VECTOR_ELT(SDNode *N);
+    SDOperand visitVBUILD_VECTOR(SDNode *N);
 
     SDOperand ReassociateOps(unsigned Opc, SDOperand LHS, SDOperand RHS);
     
@@ -644,6 +645,7 @@
   case ISD::STORE:              return visitSTORE(N);
   case ISD::INSERT_VECTOR_ELT:  return visitINSERT_VECTOR_ELT(N);
   case ISD::VINSERT_VECTOR_ELT: return visitVINSERT_VECTOR_ELT(N);
+  case ISD::VBUILD_VECTOR:      return visitVBUILD_VECTOR(N);
   }
   return SDOperand();
 }
@@ -2341,6 +2343,90 @@
   return SDOperand();
 }
 
+SDOperand DAGCombiner::visitVBUILD_VECTOR(SDNode *N) {
+  unsigned NumInScalars = N->getNumOperands()-2;
+  SDOperand NumElts = N->getOperand(NumInScalars);
+  SDOperand EltType = N->getOperand(NumInScalars+1);
+
+  // Check to see if this is a VBUILD_VECTOR of a bunch of VEXTRACT_VECTOR_ELT
+  // operations.  If so, and if the EXTRACT_ELT vector inputs come from at most
+  // two distinct vectors, turn this into a shuffle node.
+  SDOperand VecIn1, VecIn2;
+  for (unsigned i = 0; i != NumInScalars; ++i) {
+    // Ignore undef inputs.
+    if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue;
+    
+    // If this input is something other than a VEXTRACT_VECTOR_ELT with a
+    // constant index, bail out.
+    if (N->getOperand(i).getOpcode() != ISD::VEXTRACT_VECTOR_ELT ||
+        !isa<ConstantSDNode>(N->getOperand(i).getOperand(1))) {
+      VecIn1 = VecIn2 = SDOperand(0, 0);
+      break;
+    }
+    
+    // If the input vector type disagrees with the result of the vbuild_vector,
+    // we can't make a shuffle.
+    SDOperand ExtractedFromVec = N->getOperand(i).getOperand(0);
+    if (*(ExtractedFromVec.Val->op_end()-2) != NumElts ||
+        *(ExtractedFromVec.Val->op_end()-1) != EltType) {
+      VecIn1 = VecIn2 = SDOperand(0, 0);
+      break;
+    }
+    
+    // Otherwise, remember this.  We allow up to two distinct input vectors.
+    if (ExtractedFromVec == VecIn1 || ExtractedFromVec == VecIn2)
+      continue;
+    
+    if (VecIn1.Val == 0) {
+      VecIn1 = ExtractedFromVec;
+    } else if (VecIn2.Val == 0) {
+      VecIn2 = ExtractedFromVec;
+    } else {
+      // Too many inputs.
+      VecIn1 = VecIn2 = SDOperand(0, 0);
+      break;
+    }
+  }
+  
+  // If everything is good, we can make a shuffle operation.
+  if (VecIn1.Val) {
+    std::vector<SDOperand> BuildVecIndices;
+    for (unsigned i = 0; i != NumInScalars; ++i) {
+      if (N->getOperand(i).getOpcode() == ISD::UNDEF) {
+        BuildVecIndices.push_back(DAG.getNode(ISD::UNDEF, MVT::i32));
+        continue;
+      }
+      
+      SDOperand Extract = N->getOperand(i);
+      
+      // If extracting from the first vector, just use the index directly.
+      if (Extract.getOperand(0) == VecIn1) {
+        BuildVecIndices.push_back(Extract.getOperand(1));
+        continue;
+      }
+
+      // Otherwise, use InIdx + VecSize
+      unsigned Idx = cast<ConstantSDNode>(Extract.getOperand(1))->getValue();
+      BuildVecIndices.push_back(DAG.getConstant(Idx+NumInScalars, MVT::i32));
+    }
+    
+    // Add count and size info.
+    BuildVecIndices.push_back(NumElts);
+    BuildVecIndices.push_back(DAG.getValueType(MVT::i32));
+    
+    // Return the new VVECTOR_SHUFFLE node.
+    std::vector<SDOperand> Ops;
+    Ops.push_back(VecIn1);
+    Ops.push_back(VecIn2.Val ? VecIn2 : VecIn1); // Use V1 twice if no V2.
+    Ops.push_back(DAG.getNode(ISD::VBUILD_VECTOR,MVT::Vector, BuildVecIndices));
+    Ops.push_back(NumElts);
+    Ops.push_back(EltType);
+    return DAG.getNode(ISD::VVECTOR_SHUFFLE, MVT::Vector, Ops);
+  }
+  
+  return SDOperand();
+}
+
 SDOperand DAGCombiner::SimplifySelect(SDOperand N0, SDOperand N1, SDOperand N2){
   assert(N0.getOpcode() ==ISD::SETCC && "First argument must be a SetCC node!");
   





From lattner at cs.uiuc.edu  Tue Mar 28 14:32:24 2006
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Tue, 28 Mar 2006 14:32:24 -0600
Subject: [llvm-commits] CVS: llvm/test/Regression/CodeGen/X86/unpcklps.ll 
Message-ID: <200603282032.OAA18738@zion.cs.uiuc.edu>



Changes in directory llvm/test/Regression/CodeGen/X86:

unpcklps.ll added (r1.1)
---
Log message:

new testcase


---
Diffs of the changes:  (+18 -0)

 unpcklps.ll |   18 ++++++++++++++++++
 1 files changed, 18 insertions(+)


Index: llvm/test/Regression/CodeGen/X86/unpcklps.ll
diff -c /dev/null llvm/test/Regression/CodeGen/X86/unpcklps.ll:1.1
*** /dev/null	Tue Mar 28 14:32:22 2006
--- llvm/test/Regression/CodeGen/X86/unpcklps.ll	Tue Mar 28 14:32:12 2006
***************
*** 0 ****
--- 1,18 ----
+ ; RUN: llvm-as < %s | llc -march=x86 -mcpu=yonah | grep unpcklps &&
+ ; RUN: llvm-as < %s | llc -march=x86 -mcpu=yonah | not grep 'sub.*esp'
+ 
+ void %test(<4 x float>* %res, <4 x float>* %A, <4 x float>* %B) {
+         %tmp = load <4 x float>* %B             ; <<4 x float>> [#uses=2]
+         %tmp3 = load <4 x float>* %A            ; <<4 x float>> [#uses=2]
+         %tmp = extractelement <4 x float> %tmp3, uint 0         ; <float> [#uses=1]
+         %tmp7 = extractelement <4 x float> %tmp, uint 0         ; <float> [#uses=1]
+         %tmp8 = extractelement <4 x float> %tmp3, uint 1                ; <float> [#uses=1]
+         %tmp9 = extractelement <4 x float> %tmp, uint 1         ; <float> [#uses=1]
+         %tmp10 = insertelement <4 x float> undef, float %tmp, uint 0            ; <<4 x float>> [#uses=1]
+         %tmp11 = insertelement <4 x float> %tmp10, float %tmp7, uint 1          ; <<4 x float>> [#uses=1]
+         %tmp12 = insertelement <4 x float> %tmp11, float %tmp8, uint 2          ; <<4 x float>> [#uses=1]
+         %tmp13 = insertelement <4 x float> %tmp12, float %tmp9, uint 3          ; <<4 x float>> [#uses=1]
+         store <4 x float> %tmp13, <4 x float>* %res
+         ret void
+ }
+ 





From lattner at cs.uiuc.edu  Tue Mar 28 16:12:06 2006
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Tue, 28 Mar 2006 16:12:06 -0600
Subject: [llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp 
Message-ID: <200603282212.QAA19812@zion.cs.uiuc.edu>



Changes in directory llvm/lib/CodeGen/SelectionDAG:

DAGCombiner.cpp updated: 1.131 -> 1.132
---
Log message:

Canonicalize VECTOR_SHUFFLE(X, X, Y) -> VECTOR_SHUFFLE(X,undef,Y')


---
Diffs of the changes:  (+30 -0)

 DAGCombiner.cpp |   30 ++++++++++++++++++++++++++++++
 1 files changed, 30 insertions(+)


Index: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.131 llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.132
--- llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.131	Tue Mar 28 14:28:38 2006
+++ llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp	Tue Mar 28 16:11:53 2006
@@ -212,6 +212,7 @@
     SDOperand visitINSERT_VECTOR_ELT(SDNode *N);
     SDOperand visitVINSERT_VECTOR_ELT(SDNode *N);
     SDOperand visitVBUILD_VECTOR(SDNode *N);
+    SDOperand visitVECTOR_SHUFFLE(SDNode *N);
 
     SDOperand ReassociateOps(unsigned Opc, SDOperand LHS, SDOperand RHS);
     
@@ -646,6 +647,7 @@
   case ISD::INSERT_VECTOR_ELT:  return visitINSERT_VECTOR_ELT(N);
   case ISD::VINSERT_VECTOR_ELT: return visitVINSERT_VECTOR_ELT(N);
   case ISD::VBUILD_VECTOR:      return visitVBUILD_VECTOR(N);
+  case ISD::VECTOR_SHUFFLE:     return visitVECTOR_SHUFFLE(N);
   }
   return SDOperand();
 }
@@ -2427,6 +2429,34 @@
   return SDOperand();
 }
 
+SDOperand DAGCombiner::visitVECTOR_SHUFFLE(SDNode *N) {
+  // If the LHS and the RHS are the same node, turn the RHS into an undef.
+  if (N->getOperand(0) == N->getOperand(1)) {
+    // Check the SHUFFLE mask, mapping any inputs from the 2nd operand into the
+    // first operand.
+    std::vector<SDOperand> MappedOps;
+    SDOperand ShufMask = N->getOperand(2);
+    unsigned NumElts = ShufMask.getNumOperands();
+    for (unsigned i = 0, e = ShufMask.getNumOperands(); i != e; ++i) {
+      if (cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue() >= NumElts) {
+        unsigned NewIdx = 
+           cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue() - NumElts;
+        MappedOps.push_back(DAG.getConstant(NewIdx, MVT::i32));
+      } else {
+        MappedOps.push_back(ShufMask.getOperand(i));
+      }
+    }
+    ShufMask = DAG.getNode(ISD::BUILD_VECTOR, ShufMask.getValueType(),
+                           MappedOps);
+    return DAG.getNode(ISD::VECTOR_SHUFFLE, N->getValueType(0),
+                       N->getOperand(0), 
+                       DAG.getNode(ISD::UNDEF, N->getValueType(0)),
+                       ShufMask);
+  }
+ 
+  return SDOperand();
+}
+
 SDOperand DAGCombiner::SimplifySelect(SDOperand N0, SDOperand N1, SDOperand N2){
   assert(N0.getOpcode() ==ISD::SETCC && "First argument must be a SetCC node!");
   





From lattner at cs.uiuc.edu  Tue Mar 28 16:19:59 2006
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Tue, 28 Mar 2006 16:19:59 -0600
Subject: [llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp 
Message-ID: <200603282219.QAA19903@zion.cs.uiuc.edu>



Changes in directory llvm/lib/CodeGen/SelectionDAG:

DAGCombiner.cpp updated: 1.132 -> 1.133
---
Log message:

When building a VVECTOR_SHUFFLE node from extract_element operations, make
sure to build it as SHUFFLE(X, undef, mask), not SHUFFLE(X, X, mask).

The later is not canonical form, and prevents the PPC splat pattern from 
matching.  For a particular splat, we go from generating this:

	li r10, lo16(LCPI1_0)
	lis r11, ha16(LCPI1_0)
	lvx v3, r11, r10
	vperm v3, v2, v2, v3

to generating:

	vspltw v3, v2, 3



---
Diffs of the changes:  (+11 -1)

 DAGCombiner.cpp |   12 +++++++++++-
 1 files changed, 11 insertions(+), 1 deletion(-)


Index: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.132 llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.133
--- llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.132	Tue Mar 28 16:11:53 2006
+++ llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp	Tue Mar 28 16:19:47 2006
@@ -2419,7 +2419,17 @@
     // Return the new VVECTOR_SHUFFLE node.
     std::vector<SDOperand> Ops;
     Ops.push_back(VecIn1);
-    Ops.push_back(VecIn2.Val ? VecIn2 : VecIn1); // Use V1 twice if no V2.
+    if (VecIn2.Val) {
+      Ops.push_back(VecIn2);
+    } else {
+       // Use an undef vbuild_vector as input for the second operand.
+      std::vector<SDOperand> UnOps(NumInScalars,
+                                   DAG.getNode(ISD::UNDEF, 
+                                           cast<VTSDNode>(EltType)->getVT()));
+      UnOps.push_back(NumElts);
+      UnOps.push_back(EltType);
+      Ops.push_back(DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector, UnOps));
+    }
     Ops.push_back(DAG.getNode(ISD::VBUILD_VECTOR,MVT::Vector, BuildVecIndices));
     Ops.push_back(NumElts);
     Ops.push_back(EltType);





From evan.cheng at apple.com  Tue Mar 28 16:26:09 2006
From: evan.cheng at apple.com (Evan Cheng)
Date: Tue, 28 Mar 2006 16:26:09 -0600
Subject: [llvm-commits] CVS: llvm/utils/TableGen/IntrinsicEmitter.cpp 
Message-ID: <200603282226.QAA19970@zion.cs.uiuc.edu>



Changes in directory llvm/utils/TableGen:

IntrinsicEmitter.cpp updated: 1.16 -> 1.17
---
Log message:

Don't sort the names before outputing the intrinsic name table. It causes a
mismatch against the enum table.
This is a part of Sabre's master plan to drive me nuts with subtle bugs that
happens to only affect x86 be. :-)


---
Diffs of the changes:  (+2 -7)

 IntrinsicEmitter.cpp |    9 ++-------
 1 files changed, 2 insertions(+), 7 deletions(-)


Index: llvm/utils/TableGen/IntrinsicEmitter.cpp
diff -u llvm/utils/TableGen/IntrinsicEmitter.cpp:1.16 llvm/utils/TableGen/IntrinsicEmitter.cpp:1.17
--- llvm/utils/TableGen/IntrinsicEmitter.cpp:1.16	Fri Mar 24 13:49:31 2006
+++ llvm/utils/TableGen/IntrinsicEmitter.cpp	Tue Mar 28 16:25:56 2006
@@ -100,16 +100,11 @@
 void IntrinsicEmitter::
 EmitIntrinsicToNameTable(const std::vector<CodeGenIntrinsic> &Ints, 
                          std::ostream &OS) {
-  std::vector<std::string> Names;
-  for (unsigned i = 0, e = Ints.size(); i != e; ++i)
-    Names.push_back(Ints[i].Name);
-  std::sort(Names.begin(), Names.end());
-  
   OS << "// Intrinsic ID to name table\n";
   OS << "#ifdef GET_INTRINSIC_NAME_TABLE\n";
   OS << "  // Note that entry #0 is the invalid intrinsic!\n";
-  for (unsigned i = 0, e = Names.size(); i != e; ++i)
-    OS << "  \"" << Names[i] << "\",\n";
+  for (unsigned i = 0, e = Ints.size(); i != e; ++i)
+    OS << "  \"" << Ints[i].Name << "\",\n";
   OS << "#endif\n\n";
 }
 





From lattner at cs.uiuc.edu  Tue Mar 28 16:28:49 2006
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Tue, 28 Mar 2006 16:28:49 -0600
Subject: [llvm-commits] 
	CVS: llvm-test/SingleSource/UnitTests/Vector/Altivec/casts.c
Message-ID: <200603282228.QAA20041@zion.cs.uiuc.edu>



Changes in directory llvm-test/SingleSource/UnitTests/Vector/Altivec:

casts.c added (r1.1)
---
Log message:

Random testcase from my collection


---
Diffs of the changes:  (+30 -0)

 casts.c |   30 ++++++++++++++++++++++++++++++
 1 files changed, 30 insertions(+)


Index: llvm-test/SingleSource/UnitTests/Vector/Altivec/casts.c
diff -c /dev/null llvm-test/SingleSource/UnitTests/Vector/Altivec/casts.c:1.1
*** /dev/null	Tue Mar 28 16:28:47 2006
--- llvm-test/SingleSource/UnitTests/Vector/Altivec/casts.c	Tue Mar 28 16:28:37 2006
***************
*** 0 ****
--- 1,30 ----
+ #include <altivec.h>
+ #include <stdio.h>
+ 
+ typedef union {
+  float f[4];
+  vector float v;
+ } floatToVector;
+ 
+ 
+ void test(float F, vector float *R) {
+    floatToVector FTV;
+    FTV.f[0] = F;
+    *R = (vector float) vec_splat((vector unsigned int)FTV.v, 0);
+ }
+ 
+ void test2(float F, vector float *R) {
+    *R = (vector float)(F);
+ }
+ void test2a(float F, vector float *X, vector float *R) {
+    *R = (vector float)(F) + *X;
+ }
+ 
+ 
+ int main() {
+   floatToVector X;
+   int i;
+   test(12.34, &X.v);
+ 
+   printf("%f %f %f %f\n", X.f[0], X.f[1], X.f[2], X.f[3]);
+ }





From evan.cheng at apple.com  Tue Mar 28 17:41:45 2006
From: evan.cheng at apple.com (Evan Cheng)
Date: Tue, 28 Mar 2006 17:41:45 -0600
Subject: [llvm-commits] CVS: llvm/lib/Target/X86/X86ISelLowering.cpp 
Message-ID: <200603282341.RAA21932@zion.cs.uiuc.edu>



Changes in directory llvm/lib/Target/X86:

X86ISelLowering.cpp updated: 1.140 -> 1.141
---
Log message:

Fixing buggy code.


---
Diffs of the changes:  (+6 -6)

 X86ISelLowering.cpp |   12 ++++++------
 1 files changed, 6 insertions(+), 6 deletions(-)


Index: llvm/lib/Target/X86/X86ISelLowering.cpp
diff -u llvm/lib/Target/X86/X86ISelLowering.cpp:1.140 llvm/lib/Target/X86/X86ISelLowering.cpp:1.141
--- llvm/lib/Target/X86/X86ISelLowering.cpp:1.140	Tue Mar 28 04:17:11 2006
+++ llvm/lib/Target/X86/X86ISelLowering.cpp	Tue Mar 28 17:41:33 2006
@@ -1571,14 +1571,14 @@
   unsigned NumOperands = N->getNumOperands();
   unsigned Shift = (NumOperands == 4) ? 2 : 1;
   unsigned Mask = 0;
-  unsigned i = NumOperands - 1;
-  do {
-    unsigned Val = cast<ConstantSDNode>(N->getOperand(i))->getValue();
+  for (unsigned i = 0; i < NumOperands; ++i) {
+    unsigned Val
+      = cast<ConstantSDNode>(N->getOperand(NumOperands-i-1))->getValue();
     if (Val >= NumOperands) Val -= NumOperands;
     Mask |= Val;
-    Mask <<= Shift;
-    --i;
-  } while (i != 0);
+    if (i != NumOperands - 1)
+      Mask <<= Shift;
+  }
 
   return Mask;
 }





From evan.cheng at apple.com  Tue Mar 28 17:51:55 2006
From: evan.cheng at apple.com (Evan Cheng)
Date: Tue, 28 Mar 2006 17:51:55 -0600
Subject: [llvm-commits] CVS: llvm/lib/Target/X86/X86InstrSSE.td 
Message-ID: <200603282351.RAA22044@zion.cs.uiuc.edu>



Changes in directory llvm/lib/Target/X86:

X86InstrSSE.td updated: 1.39 -> 1.40
---
Log message:

Added aliases to scalar SSE instructions, e.g. addss, to match x86 intrinsics.
The source operands type are v4sf with upper bits passes through.
Added matching code for these.


---
Diffs of the changes:  (+201 -47)

 X86InstrSSE.td |  248 ++++++++++++++++++++++++++++++++++++++++++++++-----------
 1 files changed, 201 insertions(+), 47 deletions(-)


Index: llvm/lib/Target/X86/X86InstrSSE.td
diff -u llvm/lib/Target/X86/X86InstrSSE.td:1.39 llvm/lib/Target/X86/X86InstrSSE.td:1.40
--- llvm/lib/Target/X86/X86InstrSSE.td:1.39	Tue Mar 28 01:01:28 2006
+++ llvm/lib/Target/X86/X86InstrSSE.td	Tue Mar 28 17:51:43 2006
@@ -174,53 +174,6 @@
                      [(set VR128:$dst, 
                        (v2f64 (scalar_to_vector (loadf64 addr:$src))))]>;
 
-
-// Conversion instructions
-def CVTSS2SIrr: SSI<0x2D, MRMSrcReg, (ops R32:$dst, FR32:$src),
-                   "cvtss2si {$src, $dst|$dst, $src}", []>;
-def CVTSS2SIrm: SSI<0x2D, MRMSrcMem, (ops R32:$dst, f32mem:$src),
-                   "cvtss2si {$src, $dst|$dst, $src}", []>;
-
-def CVTTSS2SIrr: SSI<0x2C, MRMSrcReg, (ops R32:$dst, FR32:$src),
-                   "cvttss2si {$src, $dst|$dst, $src}",
-                   [(set R32:$dst, (fp_to_sint FR32:$src))]>;
-def CVTTSS2SIrm: SSI<0x2C, MRMSrcMem, (ops R32:$dst, f32mem:$src),
-                   "cvttss2si {$src, $dst|$dst, $src}",
-                   [(set R32:$dst, (fp_to_sint (loadf32 addr:$src)))]>;
-def CVTTSD2SIrr: SDI<0x2C, MRMSrcReg, (ops R32:$dst, FR64:$src),
-                   "cvttsd2si {$src, $dst|$dst, $src}",
-                   [(set R32:$dst, (fp_to_sint FR64:$src))]>;
-def CVTTSD2SIrm: SDI<0x2C, MRMSrcMem, (ops R32:$dst, f64mem:$src),
-                   "cvttsd2si {$src, $dst|$dst, $src}",
-                   [(set R32:$dst, (fp_to_sint (loadf64 addr:$src)))]>;
-def CVTSD2SSrr: SDI<0x5A, MRMSrcReg, (ops FR32:$dst, FR64:$src),
-                  "cvtsd2ss {$src, $dst|$dst, $src}",
-                  [(set FR32:$dst, (fround FR64:$src))]>;
-def CVTSD2SSrm: SDI<0x5A, MRMSrcMem, (ops FR32:$dst, f64mem:$src), 
-                  "cvtsd2ss {$src, $dst|$dst, $src}",
-                  [(set FR32:$dst, (fround (loadf64 addr:$src)))]>;
-def CVTSI2SSrr: SSI<0x2A, MRMSrcReg, (ops FR32:$dst, R32:$src),
-                  "cvtsi2ss {$src, $dst|$dst, $src}",
-                  [(set FR32:$dst, (sint_to_fp R32:$src))]>;
-def CVTSI2SSrm: SSI<0x2A, MRMSrcMem, (ops FR32:$dst, i32mem:$src),
-                  "cvtsi2ss {$src, $dst|$dst, $src}",
-                  [(set FR32:$dst, (sint_to_fp (loadi32 addr:$src)))]>;
-def CVTSI2SDrr: SDI<0x2A, MRMSrcReg, (ops FR64:$dst, R32:$src),
-                  "cvtsi2sd {$src, $dst|$dst, $src}",
-                  [(set FR64:$dst, (sint_to_fp R32:$src))]>;
-def CVTSI2SDrm: SDI<0x2A, MRMSrcMem, (ops FR64:$dst, i32mem:$src),
-                  "cvtsi2sd {$src, $dst|$dst, $src}",
-                  [(set FR64:$dst, (sint_to_fp (loadi32 addr:$src)))]>;
-// SSE2 instructions with XS prefix
-def CVTSS2SDrr: I<0x5A, MRMSrcReg, (ops FR64:$dst, FR32:$src),
-                  "cvtss2sd {$src, $dst|$dst, $src}",
-                  [(set FR64:$dst, (fextend FR32:$src))]>, XS,
-                Requires<[HasSSE2]>;
-def CVTSS2SDrm: I<0x5A, MRMSrcMem, (ops FR64:$dst, f32mem:$src),
-                  "cvtss2sd {$src, $dst|$dst, $src}",
-                  [(set FR64:$dst, (fextend (loadf32 addr:$src)))]>, XS,
-                Requires<[HasSSE2]>;
-
 // Arithmetic instructions
 let isTwoAddress = 1 in {
 let isCommutable = 1 in {
@@ -317,6 +270,207 @@
 def MINSDrm : SDI<0x5D, MRMSrcMem, (ops FR64:$dst, f64mem:$src),
                   "minsd {$src, $dst|$dst, $src}", []>;
 
+
+// Aliases to match intrinsics which expect XMM operand(s).
+let isTwoAddress = 1 in {
+let isCommutable = 1 in {
+def Int_ADDSSrr : SSI<0x58, MRMSrcReg, (ops VR128:$dst, VR128:$src1,
+                                        VR128:$src2),
+                "addss {$src2, $dst|$dst, $src2}",
+                [(set VR128:$dst, (int_x86_sse_add_ss VR128:$src1,
+                                   VR128:$src2))]>;
+def Int_ADDSDrr : SDI<0x58, MRMSrcReg, (ops VR128:$dst, VR128:$src1,
+                                        VR128:$src2),
+                "addsd {$src2, $dst|$dst, $src2}",
+                [(set VR128:$dst, (int_x86_sse2_add_sd VR128:$src1,
+                                   VR128:$src2))]>;
+def Int_MULSSrr : SSI<0x59, MRMSrcReg, (ops VR128:$dst, VR128:$src1,
+                                        VR128:$src2),
+                "mulss {$src2, $dst|$dst, $src2}",
+                [(set VR128:$dst, (int_x86_sse_mul_ss VR128:$src1,
+                                   VR128:$src2))]>;
+def Int_MULSDrr : SDI<0x59, MRMSrcReg, (ops VR128:$dst, VR128:$src1,
+                                        VR128:$src2),
+                "mulsd {$src2, $dst|$dst, $src2}",
+                [(set VR128:$dst, (int_x86_sse2_mul_sd VR128:$src1,
+                                   VR128:$src2))]>;
+}
+
+def Int_ADDSSrm : SSI<0x58, MRMSrcMem, (ops VR128:$dst, VR128:$src1,
+                                        f32mem:$src2),
+                "addss {$src2, $dst|$dst, $src2}",
+                [(set VR128:$dst, (int_x86_sse_add_ss VR128:$src1,
+                                   (load addr:$src2)))]>;
+def Int_ADDSDrm : SDI<0x58, MRMSrcMem, (ops VR128:$dst, VR128:$src1,
+                                        f64mem:$src2),
+                "addsd {$src2, $dst|$dst, $src2}",
+                [(set VR128:$dst, (int_x86_sse2_add_sd VR128:$src1,
+                                   (load addr:$src2)))]>;
+def Int_MULSSrm : SSI<0x59, MRMSrcMem, (ops VR128:$dst, VR128:$src1,
+                                        f32mem:$src2),
+                "mulss {$src2, $dst|$dst, $src2}",
+                [(set VR128:$dst, (int_x86_sse_mul_ss VR128:$src1,
+                                   (load addr:$src2)))]>;
+def Int_MULSDrm : SDI<0x59, MRMSrcMem, (ops VR128:$dst, VR128:$src1,
+                                        f64mem:$src2),
+                "mulsd {$src2, $dst|$dst, $src2}",
+                [(set VR128:$dst, (int_x86_sse2_mul_sd VR128:$src1,
+                                   (load addr:$src2)))]>;
+
+def Int_DIVSSrr : SSI<0x5E, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
+                "divss {$src2, $dst|$dst, $src2}",
+                [(set VR128:$dst, (int_x86_sse_div_ss VR128:$src1,
+                                   VR128:$src2))]>;
+def Int_DIVSSrm : SSI<0x5E, MRMSrcMem, (ops VR128:$dst, VR128:$src1, f32mem:$src2),
+                "divss {$src2, $dst|$dst, $src2}",
+                [(set VR128:$dst, (int_x86_sse_div_ss VR128:$src1,
+                                   (load addr:$src2)))]>;
+def Int_DIVSDrr : SDI<0x5E, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
+                "divsd {$src2, $dst|$dst, $src2}",
+                [(set VR128:$dst, (int_x86_sse2_div_sd VR128:$src1,
+                                   VR128:$src2))]>;
+def Int_DIVSDrm : SDI<0x5E, MRMSrcMem, (ops VR128:$dst, VR128:$src1, f64mem:$src2),
+                "divsd {$src2, $dst|$dst, $src2}",
+                [(set VR128:$dst, (int_x86_sse2_div_sd VR128:$src1,
+                                   (load addr:$src2)))]>;
+
+def Int_SUBSSrr : SSI<0x5C, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
+                "subss {$src2, $dst|$dst, $src2}",
+                [(set VR128:$dst, (int_x86_sse_sub_ss VR128:$src1,
+                                   VR128:$src2))]>;
+def Int_SUBSSrm : SSI<0x5C, MRMSrcMem, (ops VR128:$dst, VR128:$src1, f32mem:$src2),
+                "subss {$src2, $dst|$dst, $src2}",
+                [(set VR128:$dst, (int_x86_sse_sub_ss VR128:$src1,
+                                   (load addr:$src2)))]>;
+def Int_SUBSDrr : SDI<0x5C, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
+                "subsd {$src2, $dst|$dst, $src2}",
+                [(set VR128:$dst, (int_x86_sse2_sub_sd VR128:$src1,
+                                   VR128:$src2))]>;
+def Int_SUBSDrm : SDI<0x5C, MRMSrcMem, (ops VR128:$dst, VR128:$src1, f64mem:$src2),
+                "subsd {$src2, $dst|$dst, $src2}",
+                [(set VR128:$dst, (int_x86_sse2_sub_sd VR128:$src1,
+                                   (load addr:$src2)))]>;
+}
+
+def Int_SQRTSSrr : SSI<0x51, MRMSrcReg, (ops VR128:$dst, VR128:$src),
+                 "sqrtss {$src, $dst|$dst, $src}",
+                       [(set VR128:$dst, (int_x86_sse_sqrt_ss VR128:$src))]>;
+def Int_SQRTSSrm : SSI<0x51, MRMSrcMem, (ops VR128:$dst, f32mem:$src),
+                 "sqrtss {$src, $dst|$dst, $src}",
+                       [(set VR128:$dst, (int_x86_sse_sqrt_ss
+                                          (load addr:$src)))]>;
+def Int_SQRTSDrr : SDI<0x51, MRMSrcReg, (ops VR128:$dst, VR128:$src),
+                      "sqrtsd {$src, $dst|$dst, $src}",
+                      [(set VR128:$dst, (int_x86_sse2_sqrt_sd VR128:$src))]>;
+def Int_SQRTSDrm : SDI<0x51, MRMSrcMem, (ops VR128:$dst, f64mem:$src),
+                      "sqrtsd {$src, $dst|$dst, $src}",
+                      [(set VR128:$dst, (int_x86_sse2_sqrt_sd
+                                         (load addr:$src)))]>;
+
+def Int_RSQRTSSrr : SSI<0x52, MRMSrcReg, (ops VR128:$dst, VR128:$src),
+                       "rsqrtss {$src, $dst|$dst, $src}",
+                       [(set VR128:$dst, (int_x86_sse_rsqrt_ss VR128:$src))]>;
+def Int_RSQRTSSrm : SSI<0x52, MRMSrcMem, (ops VR128:$dst, f32mem:$src),
+                       "rsqrtss {$src, $dst|$dst, $src}",
+                       [(set VR128:$dst, (int_x86_sse_rsqrt_ss
+                                          (load addr:$src)))]>;
+def Int_RCPSSrr : SSI<0x53, MRMSrcReg, (ops VR128:$dst, VR128:$src),
+                     "rcpss {$src, $dst|$dst, $src}",
+                     [(set VR128:$dst, (int_x86_sse_rcp_ss VR128:$src))]>;
+def Int_RCPSSrm : SSI<0x53, MRMSrcMem, (ops VR128:$dst, f32mem:$src),
+                     "rcpss {$src, $dst|$dst, $src}",
+                     [(set VR128:$dst, (int_x86_sse_rcp_ss
+                                        (load addr:$src)))]>;
+
+let isTwoAddress = 1 in {
+def Int_MAXSSrr : SSI<0x5F, MRMSrcReg, (ops VR128:$dst, VR128:$src1,
+                                        VR128:$src2),
+                      "maxss {$src2, $dst|$dst, $src2}",
+                      [(set VR128:$dst, (int_x86_sse_max_ss VR128:$src1,
+                                         VR128:$src2))]>;
+def Int_MAXSSrm : SSI<0x5F, MRMSrcMem, (ops VR128:$dst, VR128:$src1,
+                                        f32mem:$src2),
+                      "maxss {$src2, $dst|$dst, $src2}",
+                      [(set VR128:$dst, (int_x86_sse_max_ss VR128:$src1,
+                                         (load addr:$src2)))]>;
+def Int_MAXSDrr : SDI<0x5F, MRMSrcReg, (ops VR128:$dst, VR128:$src1,
+                                        VR128:$src2),
+                      "maxsd {$src2, $dst|$dst, $src2}",
+                      [(set VR128:$dst, (int_x86_sse2_max_sd VR128:$src1,
+                                         VR128:$src2))]>;
+def Int_MAXSDrm : SDI<0x5F, MRMSrcMem, (ops VR128:$dst, VR128:$src1,
+                                        f64mem:$src2),
+                      "maxsd {$src2, $dst|$dst, $src2}",
+                      [(set VR128:$dst, (int_x86_sse2_max_sd VR128:$src1,
+                                         (load addr:$src2)))]>;
+def Int_MINSSrr : SSI<0x5D, MRMSrcReg, (ops VR128:$dst, VR128:$src1,
+                                        VR128:$src2),
+                      "minss {$src2, $dst|$dst, $src2}",
+                      [(set VR128:$dst, (int_x86_sse_min_ss VR128:$src1,
+                                         VR128:$src2))]>;
+def Int_MINSSrm : SSI<0x5D, MRMSrcMem, (ops VR128:$dst, VR128:$src1,
+                                        f32mem:$src2),
+                      "minss {$src2, $dst|$dst, $src2}",
+                      [(set VR128:$dst, (int_x86_sse_min_ss VR128:$src1,
+                                         (load addr:$src2)))]>;
+def Int_MINSDrr : SDI<0x5D, MRMSrcReg, (ops VR128:$dst, VR128:$src1,
+                                        VR128:$src2),
+                      "minsd {$src2, $dst|$dst, $src2}",
+                      [(set VR128:$dst, (int_x86_sse2_min_sd VR128:$src1,
+                                         VR128:$src2))]>;
+def Int_MINSDrm : SDI<0x5D, MRMSrcMem, (ops VR128:$dst, VR128:$src1,
+                                        f64mem:$src2),
+                      "minsd {$src2, $dst|$dst, $src2}",
+                      [(set VR128:$dst, (int_x86_sse2_min_sd VR128:$src1,
+                                         (load addr:$src2)))]>;
+}
+
+// Conversion instructions
+def CVTSS2SIrr: SSI<0x2D, MRMSrcReg, (ops R32:$dst, FR32:$src),
+                   "cvtss2si {$src, $dst|$dst, $src}", []>;
+def CVTSS2SIrm: SSI<0x2D, MRMSrcMem, (ops R32:$dst, f32mem:$src),
+                   "cvtss2si {$src, $dst|$dst, $src}", []>;
+
+def CVTTSS2SIrr: SSI<0x2C, MRMSrcReg, (ops R32:$dst, FR32:$src),
+                   "cvttss2si {$src, $dst|$dst, $src}",
+                   [(set R32:$dst, (fp_to_sint FR32:$src))]>;
+def CVTTSS2SIrm: SSI<0x2C, MRMSrcMem, (ops R32:$dst, f32mem:$src),
+                   "cvttss2si {$src, $dst|$dst, $src}",
+                   [(set R32:$dst, (fp_to_sint (loadf32 addr:$src)))]>;
+def CVTTSD2SIrr: SDI<0x2C, MRMSrcReg, (ops R32:$dst, FR64:$src),
+                   "cvttsd2si {$src, $dst|$dst, $src}",
+                   [(set R32:$dst, (fp_to_sint FR64:$src))]>;
+def CVTTSD2SIrm: SDI<0x2C, MRMSrcMem, (ops R32:$dst, f64mem:$src),
+                   "cvttsd2si {$src, $dst|$dst, $src}",
+                   [(set R32:$dst, (fp_to_sint (loadf64 addr:$src)))]>;
+def CVTSD2SSrr: SDI<0x5A, MRMSrcReg, (ops FR32:$dst, FR64:$src),
+                  "cvtsd2ss {$src, $dst|$dst, $src}",
+                  [(set FR32:$dst, (fround FR64:$src))]>;
+def CVTSD2SSrm: SDI<0x5A, MRMSrcMem, (ops FR32:$dst, f64mem:$src), 
+                  "cvtsd2ss {$src, $dst|$dst, $src}",
+                  [(set FR32:$dst, (fround (loadf64 addr:$src)))]>;
+def CVTSI2SSrr: SSI<0x2A, MRMSrcReg, (ops FR32:$dst, R32:$src),
+                  "cvtsi2ss {$src, $dst|$dst, $src}",
+                  [(set FR32:$dst, (sint_to_fp R32:$src))]>;
+def CVTSI2SSrm: SSI<0x2A, MRMSrcMem, (ops FR32:$dst, i32mem:$src),
+                  "cvtsi2ss {$src, $dst|$dst, $src}",
+                  [(set FR32:$dst, (sint_to_fp (loadi32 addr:$src)))]>;
+def CVTSI2SDrr: SDI<0x2A, MRMSrcReg, (ops FR64:$dst, R32:$src),
+                  "cvtsi2sd {$src, $dst|$dst, $src}",
+                  [(set FR64:$dst, (sint_to_fp R32:$src))]>;
+def CVTSI2SDrm: SDI<0x2A, MRMSrcMem, (ops FR64:$dst, i32mem:$src),
+                  "cvtsi2sd {$src, $dst|$dst, $src}",
+                  [(set FR64:$dst, (sint_to_fp (loadi32 addr:$src)))]>;
+// SSE2 instructions with XS prefix
+def CVTSS2SDrr: I<0x5A, MRMSrcReg, (ops FR64:$dst, FR32:$src),
+                  "cvtss2sd {$src, $dst|$dst, $src}",
+                  [(set FR64:$dst, (fextend FR32:$src))]>, XS,
+                Requires<[HasSSE2]>;
+def CVTSS2SDrm: I<0x5A, MRMSrcMem, (ops FR64:$dst, f32mem:$src),
+                  "cvtss2sd {$src, $dst|$dst, $src}",
+                  [(set FR64:$dst, (fextend (loadf32 addr:$src)))]>, XS,
+                Requires<[HasSSE2]>;
+
 // Comparison instructions
 let isTwoAddress = 1 in {
 def CMPSSrr : SSI<0xC2, MRMSrcReg, 





From lattner at cs.uiuc.edu  Tue Mar 28 18:11:55 2006
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Tue, 28 Mar 2006 18:11:55 -0600
Subject: [llvm-commits] 
	CVS: llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
Message-ID: <200603290011.SAA22403@zion.cs.uiuc.edu>



Changes in directory llvm/lib/CodeGen/SelectionDAG:

SelectionDAGISel.cpp updated: 1.211 -> 1.212
---
Log message:

Bug fixes: handle constantexpr insert/extract element operations
Handle constantpacked vectors with constantexpr elements.

This fixes CodeGen/Generic/vector-constantexpr.ll




---
Diffs of the changes:  (+6 -16)

 SelectionDAGISel.cpp |   22 ++++++----------------
 1 files changed, 6 insertions(+), 16 deletions(-)


Index: llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.211 llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.212
--- llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.211	Tue Mar 28 07:45:20 2006
+++ llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp	Tue Mar 28 18:11:43 2006
@@ -507,8 +507,8 @@
   void visitSetLT(User &I) { visitSetCC(I, ISD::SETLT, ISD::SETULT); }
   void visitSetGT(User &I) { visitSetCC(I, ISD::SETGT, ISD::SETUGT); }
 
-  void visitExtractElement(ExtractElementInst &I);
-  void visitInsertElement(InsertElementInst &I);
+  void visitExtractElement(User &I);
+  void visitInsertElement(User &I);
 
   void visitGetElementPtr(User &I);
   void visitCast(User &I);
@@ -586,18 +586,8 @@
       // the packed constant.
       std::vector<SDOperand> Ops;
       if (ConstantPacked *CP = dyn_cast<ConstantPacked>(C)) {
-        if (MVT::isFloatingPoint(PVT)) {
-          for (unsigned i = 0; i != NumElements; ++i) {
-            const ConstantFP *El = cast<ConstantFP>(CP->getOperand(i));
-            Ops.push_back(DAG.getConstantFP(El->getValue(), PVT));
-          }
-        } else {
-          for (unsigned i = 0; i != NumElements; ++i) {
-            const ConstantIntegral *El = 
-            cast<ConstantIntegral>(CP->getOperand(i));
-            Ops.push_back(DAG.getConstant(El->getRawValue(), PVT));
-          }
-        }
+        for (unsigned i = 0; i != NumElements; ++i)
+          Ops.push_back(getValue(CP->getOperand(i)));
       } else {
         assert(isa<ConstantAggregateZero>(C) && "Unknown packed constant!");
         SDOperand Op;
@@ -1020,7 +1010,7 @@
   }
 }
 
-void SelectionDAGLowering::visitInsertElement(InsertElementInst &I) {
+void SelectionDAGLowering::visitInsertElement(User &I) {
   SDOperand InVec = getValue(I.getOperand(0));
   SDOperand InVal = getValue(I.getOperand(1));
   SDOperand InIdx = DAG.getNode(ISD::ZERO_EXTEND, TLI.getPointerTy(),
@@ -1032,7 +1022,7 @@
                            InVec, InVal, InIdx, Num, Typ));
 }
 
-void SelectionDAGLowering::visitExtractElement(ExtractElementInst &I) {
+void SelectionDAGLowering::visitExtractElement(User &I) {
   SDOperand InVec = getValue(I.getOperand(0));
   SDOperand InIdx = DAG.getNode(ISD::ZERO_EXTEND, TLI.getPointerTy(),
                                 getValue(I.getOperand(1)));





From lattner at cs.uiuc.edu  Tue Mar 28 18:12:20 2006
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Tue, 28 Mar 2006 18:12:20 -0600
Subject: [llvm-commits] 
	CVS: llvm/test/Regression/CodeGen/Generic/vector-constantexpr.ll
Message-ID: <200603290012.SAA22464@zion.cs.uiuc.edu>



Changes in directory llvm/test/Regression/CodeGen/Generic:

vector-constantexpr.ll added (r1.1)
---
Log message:

new testcase


---
Diffs of the changes:  (+10 -0)

 vector-constantexpr.ll |   10 ++++++++++
 1 files changed, 10 insertions(+)


Index: llvm/test/Regression/CodeGen/Generic/vector-constantexpr.ll
diff -c /dev/null llvm/test/Regression/CodeGen/Generic/vector-constantexpr.ll:1.1
*** /dev/null	Tue Mar 28 18:12:18 2006
--- llvm/test/Regression/CodeGen/Generic/vector-constantexpr.ll	Tue Mar 28 18:12:08 2006
***************
*** 0 ****
--- 1,10 ----
+ ; RUN: llvm-as < %s | llc
+ 	
+ void ""(float* %inregs, float* %outregs) {
+         %a_addr.i = alloca <4 x float>          ; <<4 x float>*> [#uses=1]
+         store <4 x float> < float extractelement (<4 x float> undef, uint 3), float extractelement (<4 x float> undef, uint 0), float extractelement (<4 x float> undef, uint 1), float extractelement (<4 x float> undef, uint 2) >, <4 x float>* %a_addr.i
+         ret void
+ }
+ 
+ 
+ 





From lattner at cs.uiuc.edu  Tue Mar 28 18:24:26 2006
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Tue, 28 Mar 2006 18:24:26 -0600
Subject: [llvm-commits] CVS: llvm/lib/Target/PowerPC/README_ALTIVEC.txt 
Message-ID: <200603290024.SAA22572@zion.cs.uiuc.edu>



Changes in directory llvm/lib/Target/PowerPC:

README_ALTIVEC.txt updated: 1.5 -> 1.6
---
Log message:

add a note


---
Diffs of the changes:  (+4 -0)

 README_ALTIVEC.txt |    4 ++++
 1 files changed, 4 insertions(+)


Index: llvm/lib/Target/PowerPC/README_ALTIVEC.txt
diff -u llvm/lib/Target/PowerPC/README_ALTIVEC.txt:1.5 llvm/lib/Target/PowerPC/README_ALTIVEC.txt:1.6
--- llvm/lib/Target/PowerPC/README_ALTIVEC.txt:1.5	Tue Mar 28 12:56:23 2006
+++ llvm/lib/Target/PowerPC/README_ALTIVEC.txt	Tue Mar 28 18:24:13 2006
@@ -145,3 +145,7 @@
 
 //===----------------------------------------------------------------------===//
 
+Instcombine llvm.ppc.altivec.vperm with an immediate into a shuffle operation.
+
+//===----------------------------------------------------------------------===//
+





From evan.cheng at apple.com  Tue Mar 28 19:31:03 2006
From: evan.cheng at apple.com (Evan Cheng)
Date: Tue, 28 Mar 2006 19:31:03 -0600
Subject: [llvm-commits] CVS: llvm/lib/Target/X86/X86ISelLowering.cpp
	X86InstrSSE.td 
Message-ID: <200603290131.TAA23940@zion.cs.uiuc.edu>



Changes in directory llvm/lib/Target/X86:

X86ISelLowering.cpp updated: 1.141 -> 1.142
X86InstrSSE.td updated: 1.40 -> 1.41
---
Log message:

- Only use pshufd for v4i32 vector shuffles.
- Other shuffle related fixes.


---
Diffs of the changes:  (+83 -61)

 X86ISelLowering.cpp |   51 +++++++++++++++++++++-------
 X86InstrSSE.td      |   93 +++++++++++++++++++++++++---------------------------
 2 files changed, 83 insertions(+), 61 deletions(-)


Index: llvm/lib/Target/X86/X86ISelLowering.cpp
diff -u llvm/lib/Target/X86/X86ISelLowering.cpp:1.141 llvm/lib/Target/X86/X86ISelLowering.cpp:1.142
--- llvm/lib/Target/X86/X86ISelLowering.cpp:1.141	Tue Mar 28 17:41:33 2006
+++ llvm/lib/Target/X86/X86ISelLowering.cpp	Tue Mar 28 19:30:51 2006
@@ -1583,15 +1583,21 @@
   return Mask;
 }
 
-/// CommuteVectorShuffleIfNeeded - Swap vector_shuffle operands (as well as
-/// values in ther permute mask if needed. Return an empty SDOperand is it is
-/// already well formed.
-static SDOperand CommuteVectorShuffleIfNeeded(SDOperand V1, SDOperand V2,
-                                              SDOperand Mask, MVT::ValueType VT,
-                                              SelectionDAG &DAG) {
+/// NormalizeVectorShuffle - Swap vector_shuffle operands (as well as
+/// values in ther permute mask if needed. Use V1 as second vector if it is
+/// undef. Return an empty SDOperand is it is already well formed.
+static SDOperand NormalizeVectorShuffle(SDOperand V1, SDOperand V2,
+                                        SDOperand Mask, MVT::ValueType VT,
+                                        SelectionDAG &DAG) {
   unsigned NumElems = Mask.getNumOperands();
   SDOperand Half1 = Mask.getOperand(0);
   SDOperand Half2 = Mask.getOperand(NumElems/2);
+  bool V2Undef = false;
+  if (V2.getOpcode() == ISD::UNDEF) {
+    V2Undef = true;
+    V2 = V1;
+  }
+
   if (cast<ConstantSDNode>(Half1)->getValue() >= NumElems &&
       cast<ConstantSDNode>(Half2)->getValue() <  NumElems) {
     // Swap the operands and change mask.
@@ -1604,6 +1610,10 @@
       DAG.getNode(ISD::BUILD_VECTOR, Mask.getValueType(), MaskVec);
     return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V2, V1, Mask);
   }
+
+  if (V2Undef)
+    return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V1, Mask);
+
   return SDOperand();
 }
 
@@ -2387,8 +2397,26 @@
     MVT::ValueType VT = Op.getValueType();
     unsigned NumElems = PermMask.getNumOperands();
 
-    if (NumElems == 2)
-      return CommuteVectorShuffleIfNeeded(V1, V2, PermMask, VT, DAG);
+    if (X86::isUNPCKLMask(PermMask.Val) ||
+        X86::isUNPCKHMask(PermMask.Val))
+      // Leave the VECTOR_SHUFFLE alone. It matches {P}UNPCKL*.
+      return SDOperand();
+
+    // PSHUFD's 2nd vector must be undef.
+    if (MVT::isInteger(VT) && X86::isPSHUFDMask(PermMask.Val))
+      if (V2.getOpcode() == ISD::UNDEF)
+        return SDOperand();
+      else
+        return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1,
+                           DAG.getNode(ISD::UNDEF, V1.getValueType()),
+                           PermMask);
+
+    if (NumElems == 2 ||
+        X86::isSplatMask(PermMask.Val) ||
+        X86::isSHUFPMask(PermMask.Val)) {
+      return NormalizeVectorShuffle(V1, V2, PermMask, VT, DAG);
+    }
+#if 0
     else if (X86::isSplatMask(PermMask.Val)) {
       // Handle splat cases.
       if (V2.getOpcode() == ISD::UNDEF)
@@ -2400,10 +2428,6 @@
         return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1,
                            DAG.getNode(ISD::UNDEF, V1.getValueType()),
                            PermMask);
-    } else if (X86::isUNPCKLMask(PermMask.Val) ||
-               X86::isUNPCKHMask(PermMask.Val)) {
-      // Leave the VECTOR_SHUFFLE alone. It matches {P}UNPCKL*.
-      return SDOperand();
     } else if (X86::isPSHUFDMask(PermMask.Val)) {
       if (V2.getOpcode() == ISD::UNDEF)
         // Leave the VECTOR_SHUFFLE alone. It matches PSHUFD.
@@ -2414,7 +2438,8 @@
                            DAG.getNode(ISD::UNDEF, V1.getValueType()),
                            PermMask);
     } else if (X86::isSHUFPMask(PermMask.Val))
-      return CommuteVectorShuffleIfNeeded(V1, V2, PermMask, VT, DAG);
+      return NormalizeVectorShuffle(V1, V2, PermMask, VT, DAG);
+#endif
 
     assert(0 && "Unexpected VECTOR_SHUFFLE to lower");
     abort();


Index: llvm/lib/Target/X86/X86InstrSSE.td
diff -u llvm/lib/Target/X86/X86InstrSSE.td:1.40 llvm/lib/Target/X86/X86InstrSSE.td:1.41
--- llvm/lib/Target/X86/X86InstrSSE.td:1.40	Tue Mar 28 17:51:43 2006
+++ llvm/lib/Target/X86/X86InstrSSE.td	Tue Mar 28 19:30:51 2006
@@ -79,9 +79,8 @@
   return X86::isUNPCKHMask(N);
 }]>;
 
-// Only use PSHUF if it is not a splat.
 def PSHUFD_shuffle_mask : PatLeaf<(build_vector), [{
-  return !X86::isSplatMask(N) && X86::isPSHUFDMask(N);
+  return X86::isPSHUFDMask(N);
 }], SHUFFLE_get_shuf_imm>;
 
 def SHUFP_shuffle_mask : PatLeaf<(build_vector), [{
@@ -918,86 +917,92 @@
                      "pshufw {$src2, $src1, $dst|$dst, $src1, $src2}", []>;
 def PSHUFDrr : PDIi8<0x70, MRMDestReg,
                      (ops VR128:$dst, VR128:$src1, i8imm:$src2),
-                     "pshufd {$src2, $src1, $dst|$dst, $src1, $src2}", []>;
+                     "pshufd {$src2, $src1, $dst|$dst, $src1, $src2}",
+                     [(set VR128:$dst, (v4i32 (vector_shuffle
+                                               VR128:$src1, (undef),
+                                               PSHUFD_shuffle_mask:$src2)))]>;
 def PSHUFDrm : PDIi8<0x70, MRMSrcMem,
                      (ops VR128:$dst, i128mem:$src1, i8imm:$src2),
-                     "pshufd {$src2, $src1, $dst|$dst, $src1, $src2}", []>;
+                     "pshufd {$src2, $src1, $dst|$dst, $src1, $src2}",
+                     [(set VR128:$dst, (v4i32 (vector_shuffle
+                                               (load addr:$src1), (undef),
+                                               PSHUFD_shuffle_mask:$src2)))]>;
 
 let isTwoAddress = 1 in {
 def SHUFPSrr : PSIi8<0xC6, MRMSrcReg, 
                      (ops VR128:$dst, VR128:$src1, VR128:$src2, i32i8imm:$src3),
                      "shufps {$src3, $src2, $dst|$dst, $src2, $src3}",
-                    [(set VR128:$dst, (vector_shuffle
-                                       (v4f32 VR128:$src1), (v4f32 VR128:$src2),
-                                       SHUFP_shuffle_mask:$src3))]>;
+                     [(set VR128:$dst, (v4f32 (vector_shuffle
+                                               VR128:$src1, VR128:$src2,
+                                               SHUFP_shuffle_mask:$src3)))]>;
 def SHUFPSrm : PSIi8<0xC6, MRMSrcMem, 
                    (ops VR128:$dst, VR128:$src1, f128mem:$src2, i32i8imm:$src3),
                      "shufps {$src3, $src2, $dst|$dst, $src2, $src3}",
-                    [(set VR128:$dst, (vector_shuffle
-                                       (v4f32 VR128:$src1), (load addr:$src2),
-                                       SHUFP_shuffle_mask:$src3))]>;
+                     [(set VR128:$dst, (v4f32 (vector_shuffle
+                                               VR128:$src1, (load addr:$src2),
+                                               SHUFP_shuffle_mask:$src3)))]>;
 def SHUFPDrr : PDIi8<0xC6, MRMSrcReg, 
                      (ops VR128:$dst, VR128:$src1, VR128:$src2, i8imm:$src3),
                      "shufpd {$src3, $src2, $dst|$dst, $src2, $src3}",
-                    [(set VR128:$dst, (vector_shuffle
-                                       (v2f64 VR128:$src1), (v2f64 VR128:$src2),
-                                       SHUFP_shuffle_mask:$src3))]>;
+                     [(set VR128:$dst, (v2f64 (vector_shuffle
+                                               VR128:$src1, VR128:$src2,
+                                               SHUFP_shuffle_mask:$src3)))]>;
 def SHUFPDrm : PDIi8<0xC6, MRMSrcMem, 
                      (ops VR128:$dst, VR128:$src1, f128mem:$src2, i8imm:$src3),
                      "shufpd {$src3, $src2, $dst|$dst, $src2, $src3}",
-                    [(set VR128:$dst, (vector_shuffle
-                                       (v2f64 VR128:$src1), (load addr:$src2),
-                                       SHUFP_shuffle_mask:$src3))]>;
+                     [(set VR128:$dst, (v2f64 (vector_shuffle
+                                               VR128:$src1, (load addr:$src2),
+                                               SHUFP_shuffle_mask:$src3)))]>;
 
 def UNPCKHPSrr : PSI<0x15, MRMSrcReg, 
                     (ops VR128:$dst, VR128:$src1, VR128:$src2),
                     "unpckhps {$src2, $dst|$dst, $src2}",
-                    [(set VR128:$dst,
-                      (v4f32 (vector_shuffle VR128:$src1, VR128:$src2,
-                              UNPCKH_shuffle_mask)))]>;
+                    [(set VR128:$dst, (v4f32 (vector_shuffle
+                                              VR128:$src1, VR128:$src2,
+                                              UNPCKH_shuffle_mask)))]>;
 def UNPCKHPSrm : PSI<0x15, MRMSrcMem, 
                     (ops VR128:$dst, VR128:$src1, f128mem:$src2),
                     "unpckhps {$src2, $dst|$dst, $src2}",
-                    [(set VR128:$dst,
-                      (v4f32 (vector_shuffle VR128:$src1, (load addr:$src2),
-                              UNPCKH_shuffle_mask)))]>;
+                    [(set VR128:$dst, (v4f32 (vector_shuffle
+                                              VR128:$src1, (load addr:$src2),
+                                              UNPCKH_shuffle_mask)))]>;
 def UNPCKHPDrr : PDI<0x15, MRMSrcReg, 
                     (ops VR128:$dst, VR128:$src1, VR128:$src2),
                     "unpckhpd {$src2, $dst|$dst, $src2}",
-                    [(set VR128:$dst,
-                      (v2f64 (vector_shuffle VR128:$src1, VR128:$src2,
-                              UNPCKH_shuffle_mask)))]>;
+                    [(set VR128:$dst, (v2f64 (vector_shuffle
+                                              VR128:$src1, VR128:$src2,
+                                              UNPCKH_shuffle_mask)))]>;
 def UNPCKHPDrm : PDI<0x15, MRMSrcMem, 
                     (ops VR128:$dst, VR128:$src1, f128mem:$src2),
                     "unpckhpd {$src2, $dst|$dst, $src2}",
-                    [(set VR128:$dst,
-                      (v2f64 (vector_shuffle VR128:$src1, (load addr:$src2),
-                              UNPCKH_shuffle_mask)))]>;
+                    [(set VR128:$dst, (v2f64 (vector_shuffle
+                                              VR128:$src1, (load addr:$src2),
+                                              UNPCKH_shuffle_mask)))]>;
 
 def UNPCKLPSrr : PSI<0x14, MRMSrcReg, 
                     (ops VR128:$dst, VR128:$src1, VR128:$src2),
                     "unpcklps {$src2, $dst|$dst, $src2}",
-                    [(set VR128:$dst,
-                      (v4f32 (vector_shuffle VR128:$src1, VR128:$src2,
-                              UNPCKL_shuffle_mask)))]>;
+                    [(set VR128:$dst, (v4f32 (vector_shuffle
+                                              VR128:$src1, VR128:$src2,
+                                              UNPCKL_shuffle_mask)))]>;
 def UNPCKLPSrm : PSI<0x14, MRMSrcMem, 
                     (ops VR128:$dst, VR128:$src1, f128mem:$src2),
                     "unpcklps {$src2, $dst|$dst, $src2}",
-                    [(set VR128:$dst,
-                      (v4f32 (vector_shuffle VR128:$src1, (load addr:$src2),
-                              UNPCKL_shuffle_mask)))]>;
+                    [(set VR128:$dst, (v4f32 (vector_shuffle
+                                              VR128:$src1, (load addr:$src2),
+                                              UNPCKL_shuffle_mask)))]>;
 def UNPCKLPDrr : PDI<0x14, MRMSrcReg, 
                     (ops VR128:$dst, VR128:$src1, VR128:$src2),
                     "unpcklpd {$src2, $dst|$dst, $src2}",
-                    [(set VR128:$dst,
-                      (v2f64 (vector_shuffle VR128:$src1, VR128:$src2,
-                              UNPCKL_shuffle_mask)))]>;
+                    [(set VR128:$dst, (v2f64 (vector_shuffle
+                                              VR128:$src1, VR128:$src2,
+                                              UNPCKL_shuffle_mask)))]>;
 def UNPCKLPDrm : PDI<0x14, MRMSrcMem, 
                     (ops VR128:$dst, VR128:$src1, f128mem:$src2),
                     "unpcklpd {$src2, $dst|$dst, $src2}",
-                    [(set VR128:$dst,
-                      (v2f64 (vector_shuffle VR128:$src1, (load addr:$src2),
-                              UNPCKL_shuffle_mask)))]>;
+                    [(set VR128:$dst, (v2f64 (vector_shuffle
+                                              VR128:$src1, (load addr:$src2),
+                                              UNPCKL_shuffle_mask)))]>;
 }
 
 //===----------------------------------------------------------------------===//
@@ -1354,11 +1359,3 @@
           (v2f64 (MOVLHPSrr VR128:$src, VR128:$src))>, Requires<[HasSSE2]>;
 def : Pat<(vector_shuffle (v2i64 VR128:$src), (undef), MOVLHPS_splat_mask:$sm),
           (v2i64 (MOVLHPSrr VR128:$src, VR128:$src))>, Requires<[HasSSE2]>;
-
-// Shuffle v4f32 / v4i32, undef. These should only match if splat cases do not.
-def : Pat<(vector_shuffle (v4f32 VR128:$src), (undef), PSHUFD_shuffle_mask:$sm),
-          (v4f32 (PSHUFDrr VR128:$src, PSHUFD_shuffle_mask:$sm))>,
-      Requires<[HasSSE2]>;
-def : Pat<(vector_shuffle (v4i32 VR128:$src), (undef), PSHUFD_shuffle_mask:$sm),
-          (v4i32 (PSHUFDrr VR128:$src, PSHUFD_shuffle_mask:$sm))>,
-      Requires<[HasSSE2]>;





From evan.cheng at apple.com  Tue Mar 28 21:03:58 2006
From: evan.cheng at apple.com (Evan Cheng)
Date: Tue, 28 Mar 2006 21:03:58 -0600
Subject: [llvm-commits] CVS: llvm/lib/Target/X86/README.txt 
Message-ID: <200603290303.VAA24902@zion.cs.uiuc.edu>



Changes in directory llvm/lib/Target/X86:

README.txt updated: 1.77 -> 1.78
---
Log message:

Another entry about shuffles.


---
Diffs of the changes:  (+6 -0)

 README.txt |    6 ++++++
 1 files changed, 6 insertions(+)


Index: llvm/lib/Target/X86/README.txt
diff -u llvm/lib/Target/X86/README.txt:1.77 llvm/lib/Target/X86/README.txt:1.78
--- llvm/lib/Target/X86/README.txt:1.77	Tue Mar 28 00:55:45 2006
+++ llvm/lib/Target/X86/README.txt	Tue Mar 28 21:03:46 2006
@@ -667,3 +667,9 @@
 
 Use movhps to update upper 64-bits of a v4sf value. Also movlps on lower half
 of a v4sf value.
+
+//===---------------------------------------------------------------------===//
+
+Better codegen for vector_shuffles like this { x, 0, 0, 0 } or { x, 0, x, 0}.
+Perhaps use pxor / xorp* to clear a XMM register first?
+





From evan.cheng at apple.com  Tue Mar 28 21:05:01 2006
From: evan.cheng at apple.com (Evan Cheng)
Date: Tue, 28 Mar 2006 21:05:01 -0600
Subject: [llvm-commits] CVS: llvm/lib/Target/X86/X86ISelLowering.cpp
	X86InstrSSE.td 
Message-ID: <200603290305.VAA24942@zion.cs.uiuc.edu>



Changes in directory llvm/lib/Target/X86:

X86ISelLowering.cpp updated: 1.142 -> 1.143
X86InstrSSE.td updated: 1.41 -> 1.42
---
Log message:

- More shuffle related bug fixes.
- Whenever possible use ops of the right packed types for vector shuffles /
  splats.


---
Diffs of the changes:  (+30 -47)

 X86ISelLowering.cpp |   35 +++++------------------------------
 X86InstrSSE.td      |   42 +++++++++++++++++++++++++-----------------
 2 files changed, 30 insertions(+), 47 deletions(-)


Index: llvm/lib/Target/X86/X86ISelLowering.cpp
diff -u llvm/lib/Target/X86/X86ISelLowering.cpp:1.142 llvm/lib/Target/X86/X86ISelLowering.cpp:1.143
--- llvm/lib/Target/X86/X86ISelLowering.cpp:1.142	Tue Mar 28 19:30:51 2006
+++ llvm/lib/Target/X86/X86ISelLowering.cpp	Tue Mar 28 21:04:49 2006
@@ -2403,43 +2403,18 @@
       return SDOperand();
 
     // PSHUFD's 2nd vector must be undef.
-    if (MVT::isInteger(VT) && X86::isPSHUFDMask(PermMask.Val))
-      if (V2.getOpcode() == ISD::UNDEF)
-        return SDOperand();
-      else
+    if (MVT::isInteger(VT) && X86::isPSHUFDMask(PermMask.Val)) {
+      if (V2.getOpcode() != ISD::UNDEF)
         return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1,
-                           DAG.getNode(ISD::UNDEF, V1.getValueType()),
-                           PermMask);
+                           DAG.getNode(ISD::UNDEF, V1.getValueType()),PermMask);
+      return SDOperand();
+    }
 
     if (NumElems == 2 ||
         X86::isSplatMask(PermMask.Val) ||
         X86::isSHUFPMask(PermMask.Val)) {
       return NormalizeVectorShuffle(V1, V2, PermMask, VT, DAG);
     }
-#if 0
-    else if (X86::isSplatMask(PermMask.Val)) {
-      // Handle splat cases.
-      if (V2.getOpcode() == ISD::UNDEF)
-        // Leave the VECTOR_SHUFFLE alone. It matches SHUFP*.
-        return SDOperand();
-      else
-        // Make it match SHUFP* or UNPCKLPD. Second vector is undef since it's
-        // not needed.
-        return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1,
-                           DAG.getNode(ISD::UNDEF, V1.getValueType()),
-                           PermMask);
-    } else if (X86::isPSHUFDMask(PermMask.Val)) {
-      if (V2.getOpcode() == ISD::UNDEF)
-        // Leave the VECTOR_SHUFFLE alone. It matches PSHUFD.
-        return SDOperand();
-      else
-        // Make it match PSHUFD. Second vector is undef since it's not needed.
-        return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1,
-                           DAG.getNode(ISD::UNDEF, V1.getValueType()),
-                           PermMask);
-    } else if (X86::isSHUFPMask(PermMask.Val))
-      return NormalizeVectorShuffle(V1, V2, PermMask, VT, DAG);
-#endif
 
     assert(0 && "Unexpected VECTOR_SHUFFLE to lower");
     abort();


Index: llvm/lib/Target/X86/X86InstrSSE.td
diff -u llvm/lib/Target/X86/X86InstrSSE.td:1.41 llvm/lib/Target/X86/X86InstrSSE.td:1.42
--- llvm/lib/Target/X86/X86InstrSSE.td:1.41	Tue Mar 28 19:30:51 2006
+++ llvm/lib/Target/X86/X86InstrSSE.td	Tue Mar 28 21:04:49 2006
@@ -55,11 +55,7 @@
   return getI8Imm(X86::getShuffleSHUFImmediate(N));
 }]>;
 
-def SHUFP_splat_mask : PatLeaf<(build_vector), [{
-  return X86::isSplatMask(N);
-}], SHUFFLE_get_shuf_imm>;
-
-def MOVLHPS_splat_mask : PatLeaf<(build_vector), [{
+def v2f64_v2i64_splat_mask : PatLeaf<(build_vector), [{
   return X86::isSplatMask(N);
 }]>;
 
@@ -87,6 +83,12 @@
   return X86::isSHUFPMask(N);
 }], SHUFFLE_get_shuf_imm>;
 
+// Only use SHUFP for v4i32 if no other options are available.
+// FIXME: add tblgen hook to reduce the complexity of pattern.
+def SHUFP_v4i32_shuffle_mask : PatLeaf<(build_vector), [{
+  return !X86::isUNPCKHMask(N) && !X86::isPSHUFDMask(N) && X86::isSHUFPMask(N);
+}], SHUFFLE_get_shuf_imm>;
+
 //===----------------------------------------------------------------------===//
 // SSE scalar FP Instructions
 //===----------------------------------------------------------------------===//
@@ -1327,6 +1329,8 @@
       Requires<[HasSSE2]>;
 
 // bit_convert
+def : Pat<(v2i64 (bitconvert (v4i32 VR128:$src))), (v2i64 VR128:$src)>,
+      Requires<[HasSSE2]>;
 def : Pat<(v4i32 (bitconvert (v4f32 VR128:$src))), (v4i32 VR128:$src)>,
       Requires<[HasSSE2]>;
 def : Pat<(v4f32 (bitconvert (v4i32 VR128:$src))), (v4f32 VR128:$src)>,
@@ -1346,16 +1350,20 @@
 def : Pat<(v16i8 (X86zexts2vec R8:$src)),
           (MOVZD128rr (V_SET0_PI), (MOVZX32rr8 R8:$src))>, Requires<[HasSSE2]>;
 
-// Splat v4f32 / v4i32
-def : Pat<(vector_shuffle (v4f32 VR128:$src), (undef), SHUFP_splat_mask:$sm),
-          (v4f32 (SHUFPSrr VR128:$src, VR128:$src, SHUFP_splat_mask:$sm))>,
-      Requires<[HasSSE1]>;
-def : Pat<(vector_shuffle (v4i32 VR128:$src), (undef), SHUFP_splat_mask:$sm),
-          (v4i32 (SHUFPSrr VR128:$src, VR128:$src, SHUFP_splat_mask:$sm))>,
-      Requires<[HasSSE2]>;
-
 // Splat v2f64 / v2i64
-def : Pat<(vector_shuffle (v2f64 VR128:$src), (undef), MOVLHPS_splat_mask:$sm),
-          (v2f64 (MOVLHPSrr VR128:$src, VR128:$src))>, Requires<[HasSSE2]>;
-def : Pat<(vector_shuffle (v2i64 VR128:$src), (undef), MOVLHPS_splat_mask:$sm),
-          (v2i64 (MOVLHPSrr VR128:$src, VR128:$src))>, Requires<[HasSSE2]>;
+def : Pat<(vector_shuffle (v2f64 VR128:$src), (v2f64 VR128:$src),
+           v2f64_v2i64_splat_mask:$sm),
+          (v2f64 (UNPCKLPDrr VR128:$src, VR128:$src))>, Requires<[HasSSE2]>;
+def : Pat<(vector_shuffle (v2i64 VR128:$src), (v2i64 VR128:$src),
+           v2f64_v2i64_splat_mask:$sm),
+          (v2i64 (PUNPCKLQDQrr VR128:$src, VR128:$src))>, Requires<[HasSSE2]>;
+
+// Shuffle v4i32 if others do not match
+def : Pat<(vector_shuffle (v4i32 VR128:$src1), (v4i32 VR128:$src2),
+           SHUFP_shuffle_mask:$sm),
+          (v4i32 (SHUFPSrr VR128:$src1, VR128:$src2,
+                  SHUFP_v4i32_shuffle_mask:$sm))>, Requires<[HasSSE2]>;
+def : Pat<(vector_shuffle (v4i32 VR128:$src1), (load addr:$src2),
+           SHUFP_shuffle_mask:$sm),
+          (v4i32 (SHUFPSrm VR128:$src1, addr:$src2,
+                  SHUFP_v4i32_shuffle_mask:$sm))>, Requires<[HasSSE2]>;





From evan.cheng at apple.com  Wed Mar 29 00:07:27 2006
From: evan.cheng at apple.com (Evan Cheng)
Date: Wed, 29 Mar 2006 00:07:27 -0600
Subject: [llvm-commits] CVS: llvm/include/llvm/IntrinsicsX86.td 
Message-ID: <200603290607.AAA25626@zion.cs.uiuc.edu>



Changes in directory llvm/include/llvm:

IntrinsicsX86.td updated: 1.2 -> 1.3
---
Log message:

Add more SSE intrinsics

---
Diffs of the changes:  (+118 -94)

 IntrinsicsX86.td |  212 ++++++++++++++++++++++++++++++-------------------------
 1 files changed, 118 insertions(+), 94 deletions(-)


Index: llvm/include/llvm/IntrinsicsX86.td
diff -u llvm/include/llvm/IntrinsicsX86.td:1.2 llvm/include/llvm/IntrinsicsX86.td:1.3
--- llvm/include/llvm/IntrinsicsX86.td:1.2	Mon Mar 27 02:23:12 2006
+++ llvm/include/llvm/IntrinsicsX86.td	Wed Mar 29 00:07:16 2006
@@ -18,73 +18,45 @@
 // Arithmetic ops
 let TargetPrefix = "x86" in {  // All intrinsics start with "llvm.x86.".
   def int_x86_sse_add_ss : GCCBuiltin<"__builtin_ia32_addss">,
-              Intrinsic<[llvm_float_ty, llvm_float_ty,
-                         llvm_float_ty], [InstrNoMem]>;
-  def int_x86_sse_add_ps : GCCBuiltin<"__builtin_ia32_addps">,
               Intrinsic<[llvm_v4f32_ty, llvm_v4f32_ty,
                          llvm_v4f32_ty], [InstrNoMem]>;
   def int_x86_sse_sub_ss : GCCBuiltin<"__builtin_ia32_subss">,
-              Intrinsic<[llvm_float_ty, llvm_float_ty,
-                         llvm_float_ty], [InstrNoMem]>;
-  def int_x86_sse_sub_ps : GCCBuiltin<"__builtin_ia32_subps">,
               Intrinsic<[llvm_v4f32_ty, llvm_v4f32_ty,
                          llvm_v4f32_ty], [InstrNoMem]>;
   def int_x86_sse_mul_ss : GCCBuiltin<"__builtin_ia32_mulss">,
-              Intrinsic<[llvm_float_ty, llvm_float_ty,
-                         llvm_float_ty], [InstrNoMem]>;
-  def int_x86_sse_mul_ps : GCCBuiltin<"__builtin_ia32_mulps">,
               Intrinsic<[llvm_v4f32_ty, llvm_v4f32_ty,
                          llvm_v4f32_ty], [InstrNoMem]>;
   def int_x86_sse_div_ss : GCCBuiltin<"__builtin_ia32_divss">,
-              Intrinsic<[llvm_float_ty, llvm_float_ty,
-                         llvm_float_ty], [InstrNoMem]>;
-  def int_x86_sse_div_ps : GCCBuiltin<"__builtin_ia32_divps">,
               Intrinsic<[llvm_v4f32_ty, llvm_v4f32_ty,
                          llvm_v4f32_ty], [InstrNoMem]>;
   def int_x86_sse_sqrt_ss : GCCBuiltin<"__builtin_ia32_sqrtss">,
-              Intrinsic<[llvm_float_ty, llvm_float_ty,
-                         llvm_float_ty], [InstrNoMem]>;
+              Intrinsic<[llvm_v4f32_ty, llvm_v4f32_ty],
+                        [InstrNoMem]>;
   def int_x86_sse_sqrt_ps : GCCBuiltin<"__builtin_ia32_sqrtps">,
-              Intrinsic<[llvm_v4f32_ty, llvm_v4f32_ty,
-                         llvm_v4f32_ty], [InstrNoMem]>;
+              Intrinsic<[llvm_v4f32_ty, llvm_v4f32_ty],
+                        [InstrNoMem]>;
   def int_x86_sse_rcp_ss : GCCBuiltin<"__builtin_ia32_rcpss">,
-              Intrinsic<[llvm_float_ty, llvm_float_ty,
-                         llvm_float_ty], [InstrNoMem]>;
+              Intrinsic<[llvm_v4f32_ty, llvm_v4f32_ty],
+                        [InstrNoMem]>;
   def int_x86_sse_rcp_ps : GCCBuiltin<"__builtin_ia32_rcpps">,
-              Intrinsic<[llvm_v4f32_ty, llvm_v4f32_ty,
-                         llvm_v4f32_ty], [InstrNoMem]>;
+              Intrinsic<[llvm_v4f32_ty, llvm_v4f32_ty],
+                        [InstrNoMem]>;
   def int_x86_sse_rsqrt_ss : GCCBuiltin<"__builtin_ia32_rsqrtss">,
-              Intrinsic<[llvm_float_ty, llvm_float_ty,
-                         llvm_float_ty], [InstrNoMem]>;
+              Intrinsic<[llvm_v4f32_ty, llvm_v4f32_ty],
+                        [InstrNoMem]>;
   def int_x86_sse_rsqrt_ps : GCCBuiltin<"__builtin_ia32_rsqrtps">,
+              Intrinsic<[llvm_v4f32_ty, llvm_v4f32_ty],
+                        [InstrNoMem]>;
+  def int_x86_sse_min_ss : GCCBuiltin<"__builtin_ia32_minss">,
               Intrinsic<[llvm_v4f32_ty, llvm_v4f32_ty,
                          llvm_v4f32_ty], [InstrNoMem]>;
-  def int_x86_sse_min_ss : GCCBuiltin<"__builtin_ia32_minss">,
-              Intrinsic<[llvm_float_ty, llvm_float_ty,
-                         llvm_float_ty], [InstrNoMem]>;
   def int_x86_sse_min_ps : GCCBuiltin<"__builtin_ia32_minps">,
               Intrinsic<[llvm_v4f32_ty, llvm_v4f32_ty,
                          llvm_v4f32_ty], [InstrNoMem]>;
   def int_x86_sse_max_ss : GCCBuiltin<"__builtin_ia32_maxss">,
-              Intrinsic<[llvm_float_ty, llvm_float_ty,
-                         llvm_float_ty], [InstrNoMem]>;
-  def int_x86_sse_max_ps : GCCBuiltin<"__builtin_ia32_maxps">,
               Intrinsic<[llvm_v4f32_ty, llvm_v4f32_ty,
                          llvm_v4f32_ty], [InstrNoMem]>;
-}
-
-// Logical ops
-let TargetPrefix = "x86" in {  // All intrinsics start with "llvm.x86.".
-  def int_x86_sse_and_ps : GCCBuiltin<"__builtin_ia32_andps">,
-              Intrinsic<[llvm_v4f32_ty, llvm_v4f32_ty,
-                         llvm_v4f32_ty], [InstrNoMem]>;
-  def int_x86_sse_andnot_ps : GCCBuiltin<"__builtin_ia32_andnotps">,
-              Intrinsic<[llvm_v4f32_ty, llvm_v4f32_ty,
-                         llvm_v4f32_ty], [InstrNoMem]>;
-  def int_x86_sse_or_ps : GCCBuiltin<"__builtin_ia32_orps">,
-              Intrinsic<[llvm_v4f32_ty, llvm_v4f32_ty,
-                         llvm_v4f32_ty], [InstrNoMem]>;
-  def int_x86_sse_xor_ps : GCCBuiltin<"__builtin_ia32_xorps">,
+  def int_x86_sse_max_ps : GCCBuiltin<"__builtin_ia32_maxps">,
               Intrinsic<[llvm_v4f32_ty, llvm_v4f32_ty,
                          llvm_v4f32_ty], [InstrNoMem]>;
 }
@@ -92,128 +64,128 @@
 // Comparison ops
 let TargetPrefix = "x86" in {  // All intrinsics start with "llvm.x86.".
   def int_x86_sse_cmpeq_ss : GCCBuiltin<"__builtin_ia32_cmpeqss">,
-              Intrinsic<[llvm_float_ty, llvm_float_ty,
+              Intrinsic<[llvm_v4f32_ty, llvm_v4f32_ty,
                          llvm_v4f32_ty], [InstrNoMem]>;
   def int_x86_sse_cmpeq_ps : GCCBuiltin<"__builtin_ia32_cmpeqps">,
               Intrinsic<[llvm_v4f32_ty, llvm_v4f32_ty,
                          llvm_v4f32_ty], [InstrNoMem]>;
   def int_x86_sse_cmplt_ss : GCCBuiltin<"__builtin_ia32_cmpltss">,
-              Intrinsic<[llvm_float_ty, llvm_float_ty,
-                         llvm_float_ty], [InstrNoMem]>;
+              Intrinsic<[llvm_v4f32_ty, llvm_v4f32_ty,
+                         llvm_v4f32_ty], [InstrNoMem]>;
   def int_x86_sse_cmplt_ps : GCCBuiltin<"__builtin_ia32_cmpltps">,
               Intrinsic<[llvm_v4f32_ty, llvm_v4f32_ty,
                          llvm_v4f32_ty], [InstrNoMem]>;
   def int_x86_sse_cmple_ss : GCCBuiltin<"__builtin_ia32_cmpless">,
-              Intrinsic<[llvm_float_ty, llvm_float_ty,
-                         llvm_float_ty], [InstrNoMem]>;
+              Intrinsic<[llvm_v4f32_ty, llvm_v4f32_ty,
+                         llvm_v4f32_ty], [InstrNoMem]>;
   def int_x86_sse_cmple_ps : GCCBuiltin<"__builtin_ia32_cmpleps">,
               Intrinsic<[llvm_v4f32_ty, llvm_v4f32_ty,
                          llvm_v4f32_ty], [InstrNoMem]>;
   def int_x86_sse_cmpgt_ss : GCCBuiltin<"__builtin_ia32_cmpgtss">,
-              Intrinsic<[llvm_float_ty, llvm_float_ty,
-                         llvm_float_ty], [InstrNoMem]>;
+              Intrinsic<[llvm_v4f32_ty, llvm_v4f32_ty,
+                         llvm_v4f32_ty], [InstrNoMem]>;
   def int_x86_sse_cmpgt_ps : GCCBuiltin<"__builtin_ia32_cmpgtps">,
               Intrinsic<[llvm_v4f32_ty, llvm_v4f32_ty,
                          llvm_v4f32_ty], [InstrNoMem]>;
   def int_x86_sse_cmpge_ss : GCCBuiltin<"__builtin_ia32_cmpgess">,
-              Intrinsic<[llvm_float_ty, llvm_float_ty,
-                         llvm_float_ty], [InstrNoMem]>;
+              Intrinsic<[llvm_v4f32_ty, llvm_v4f32_ty,
+                         llvm_v4f32_ty], [InstrNoMem]>;
   def int_x86_sse_cmpge_ps : GCCBuiltin<"__builtin_ia32_cmpgeps">,
               Intrinsic<[llvm_v4f32_ty, llvm_v4f32_ty,
                          llvm_v4f32_ty], [InstrNoMem]>;
   def int_x86_sse_cmpneq_ss : GCCBuiltin<"__builtin_ia32_cmpneqss">,
-              Intrinsic<[llvm_float_ty, llvm_float_ty,
-                         llvm_float_ty], [InstrNoMem]>;
+              Intrinsic<[llvm_v4f32_ty, llvm_v4f32_ty,
+                         llvm_v4f32_ty], [InstrNoMem]>;
   def int_x86_sse_cmpneq_ps : GCCBuiltin<"__builtin_ia32_cmpneqps">,
               Intrinsic<[llvm_v4f32_ty, llvm_v4f32_ty,
                          llvm_v4f32_ty], [InstrNoMem]>;
   def int_x86_sse_cmpnlt_ss : GCCBuiltin<"__builtin_ia32_cmpnltss">,
-              Intrinsic<[llvm_float_ty, llvm_float_ty,
-                         llvm_float_ty], [InstrNoMem]>;
+              Intrinsic<[llvm_v4f32_ty, llvm_v4f32_ty,
+                         llvm_v4f32_ty], [InstrNoMem]>;
   def int_x86_sse_cmpnlt_ps : GCCBuiltin<"__builtin_ia32_cmpnltps">,
               Intrinsic<[llvm_v4f32_ty, llvm_v4f32_ty,
                          llvm_v4f32_ty], [InstrNoMem]>;
   def int_x86_sse_cmpnle_ss : GCCBuiltin<"__builtin_ia32_cmpnless">,
-              Intrinsic<[llvm_float_ty, llvm_float_ty,
-                         llvm_float_ty], [InstrNoMem]>;
+              Intrinsic<[llvm_v4f32_ty, llvm_v4f32_ty,
+                         llvm_v4f32_ty], [InstrNoMem]>;
   def int_x86_sse_cmpnle_ps : GCCBuiltin<"__builtin_ia32_cmpnleps">,
               Intrinsic<[llvm_v4f32_ty, llvm_v4f32_ty,
                          llvm_v4f32_ty], [InstrNoMem]>;
   def int_x86_sse_cmpngt_ss : GCCBuiltin<"__builtin_ia32_cmpngtss">,
-              Intrinsic<[llvm_float_ty, llvm_float_ty,
-                         llvm_float_ty], [InstrNoMem]>;
+              Intrinsic<[llvm_v4f32_ty, llvm_v4f32_ty,
+                         llvm_v4f32_ty], [InstrNoMem]>;
   def int_x86_sse_cmpngt_ps : GCCBuiltin<"__builtin_ia32_cmpngtps">,
               Intrinsic<[llvm_v4f32_ty, llvm_v4f32_ty,
                          llvm_v4f32_ty], [InstrNoMem]>;
   def int_x86_sse_cmpnge_ss : GCCBuiltin<"__builtin_ia32_cmpngess">,
-              Intrinsic<[llvm_float_ty, llvm_float_ty,
-                         llvm_float_ty], [InstrNoMem]>;
+              Intrinsic<[llvm_v4f32_ty, llvm_v4f32_ty,
+                         llvm_v4f32_ty], [InstrNoMem]>;
   def int_x86_sse_cmpnge_ps : GCCBuiltin<"__builtin_ia32_cmpngeps">,
               Intrinsic<[llvm_v4f32_ty, llvm_v4f32_ty,
                          llvm_v4f32_ty], [InstrNoMem]>;
   def int_x86_sse_cmpord_ss : GCCBuiltin<"__builtin_ia32_cmpordss">,
-              Intrinsic<[llvm_float_ty, llvm_float_ty,
-                         llvm_float_ty], [InstrNoMem]>;
+              Intrinsic<[llvm_v4f32_ty, llvm_v4f32_ty,
+                         llvm_v4f32_ty], [InstrNoMem]>;
   def int_x86_sse_cmpord_ps : GCCBuiltin<"__builtin_ia32_cmpordps">,
               Intrinsic<[llvm_v4f32_ty, llvm_v4f32_ty,
                          llvm_v4f32_ty], [InstrNoMem]>;
   def int_x86_sse_cmpunord_ss : GCCBuiltin<"__builtin_ia32_cmpunordss">,
-              Intrinsic<[llvm_float_ty, llvm_float_ty,
-                         llvm_float_ty], [InstrNoMem]>;
+              Intrinsic<[llvm_v4f32_ty, llvm_v4f32_ty,
+                         llvm_v4f32_ty], [InstrNoMem]>;
   def int_x86_sse_cmpunord_ps : GCCBuiltin<"__builtin_ia32_cmpunordps">,
               Intrinsic<[llvm_v4f32_ty, llvm_v4f32_ty,
                          llvm_v4f32_ty], [InstrNoMem]>;
   def int_x86_sse_comieq_ss : GCCBuiltin<"__builtin_ia32_comieq">,
-              Intrinsic<[llvm_int_ty, llvm_float_ty,
-                         llvm_float_ty], [InstrNoMem]>;
+              Intrinsic<[llvm_int_ty, llvm_v4f32_ty,
+                         llvm_v4f32_ty], [InstrNoMem]>;
   def int_x86_sse_comilt_ss : GCCBuiltin<"__builtin_ia32_comilt">,
-              Intrinsic<[llvm_int_ty, llvm_float_ty,
-                         llvm_float_ty], [InstrNoMem]>;
+              Intrinsic<[llvm_int_ty, llvm_v4f32_ty,
+                         llvm_v4f32_ty], [InstrNoMem]>;
   def int_x86_sse_comile_ss : GCCBuiltin<"__Builtin_ia32_comile">,
-              Intrinsic<[llvm_int_ty, llvm_float_ty,
-                         llvm_float_ty], [InstrNoMem]>;
+              Intrinsic<[llvm_int_ty, llvm_v4f32_ty,
+                         llvm_v4f32_ty], [InstrNoMem]>;
   def int_x86_sse_comigt_ss : GCCBuiltin<"__builtin_ia32_comigt">,
-              Intrinsic<[llvm_int_ty, llvm_float_ty,
-                         llvm_float_ty], [InstrNoMem]>;
+              Intrinsic<[llvm_int_ty, llvm_v4f32_ty,
+                         llvm_v4f32_ty], [InstrNoMem]>;
   def int_x86_sse_comige_ss : GCCBuiltin<"__builtin_ia32_comige">,
-              Intrinsic<[llvm_int_ty, llvm_float_ty,
-                         llvm_float_ty], [InstrNoMem]>;
+              Intrinsic<[llvm_int_ty, llvm_v4f32_ty,
+                         llvm_v4f32_ty], [InstrNoMem]>;
   def int_x86_sse_comineq_ss : GCCBuiltin<"__builtin_ia32_comineq">,
-              Intrinsic<[llvm_int_ty, llvm_float_ty,
-                         llvm_float_ty], [InstrNoMem]>;
+              Intrinsic<[llvm_int_ty, llvm_v4f32_ty,
+                         llvm_v4f32_ty], [InstrNoMem]>;
   def int_x86_sse_ucomieq_ss : GCCBuiltin<"__builtin_ia32_ucomieq">,
-              Intrinsic<[llvm_int_ty, llvm_float_ty,
-                         llvm_float_ty], [InstrNoMem]>;
+              Intrinsic<[llvm_int_ty, llvm_v4f32_ty,
+                         llvm_v4f32_ty], [InstrNoMem]>;
   def int_x86_sse_ucomilt_ss : GCCBuiltin<"__builtin_ia32_ucomilt">,
-              Intrinsic<[llvm_int_ty, llvm_float_ty,
-                         llvm_float_ty], [InstrNoMem]>;
+              Intrinsic<[llvm_int_ty, llvm_v4f32_ty,
+                         llvm_v4f32_ty], [InstrNoMem]>;
   def int_x86_sse_ucomile_ss : GCCBuiltin<"__Builtin_ia32_ucomile">,
-              Intrinsic<[llvm_int_ty, llvm_float_ty,
-                         llvm_float_ty], [InstrNoMem]>;
+              Intrinsic<[llvm_int_ty, llvm_v4f32_ty,
+                         llvm_v4f32_ty], [InstrNoMem]>;
   def int_x86_sse_ucomigt_ss : GCCBuiltin<"__builtin_ia32_ucomigt">,
-              Intrinsic<[llvm_int_ty, llvm_float_ty,
-                         llvm_float_ty], [InstrNoMem]>;
+              Intrinsic<[llvm_int_ty, llvm_v4f32_ty,
+                         llvm_v4f32_ty], [InstrNoMem]>;
   def int_x86_sse_ucomige_ss : GCCBuiltin<"__builtin_ia32_ucomige">,
-              Intrinsic<[llvm_int_ty, llvm_float_ty,
-                         llvm_float_ty], [InstrNoMem]>;
+              Intrinsic<[llvm_int_ty, llvm_v4f32_ty,
+                         llvm_v4f32_ty], [InstrNoMem]>;
   def int_x86_sse_ucomineq_ss : GCCBuiltin<"__builtin_ia32_ucomineq">,
-              Intrinsic<[llvm_int_ty, llvm_float_ty,
-                         llvm_float_ty], [InstrNoMem]>;
+              Intrinsic<[llvm_int_ty, llvm_v4f32_ty,
+                         llvm_v4f32_ty], [InstrNoMem]>;
 }
 
 
 // Conversion ops
 let TargetPrefix = "x86" in {  // All intrinsics start with "llvm.x86.".
   def int_x86_sse_cvtss2si : GCCBuiltin<"__builtin_ia32_cvtss2si">,
-              Intrinsic<[llvm_int_ty, llvm_float_ty], [InstrNoMem]>;
+              Intrinsic<[llvm_int_ty, llvm_v4f32_ty], [InstrNoMem]>;
   def int_x86_sse_cvtps2pi : GCCBuiltin<"__builtin_ia32_cvtps2pi">,
               Intrinsic<[llvm_v2i32_ty, llvm_v4i32_ty], [InstrNoMem]>;
   def int_x86_sse_cvttss2si : GCCBuiltin<"__builtin_ia32_cvttss2si">,
-              Intrinsic<[llvm_int_ty, llvm_float_ty], [InstrNoMem]>;
+              Intrinsic<[llvm_int_ty, llvm_v4f32_ty], [InstrNoMem]>;
   def int_x86_sse_cvttps2pi : GCCBuiltin<"__builtin_ia32_cvttps2pi">,
               Intrinsic<[llvm_v2i32_ty, llvm_v4i32_ty], [InstrNoMem]>;
   def int_x86_sse_cvtsi2ss : GCCBuiltin<"__builtin_ia32_cvtsi2ss">,
-              Intrinsic<[llvm_float_ty, llvm_int_ty], [InstrNoMem]>;
+              Intrinsic<[llvm_v4f32_ty, llvm_int_ty], [InstrNoMem]>;
   def int_x86_sse_cvtpi2ps : GCCBuiltin<"__builtin_ia32_cvtpi2ps">,
               Intrinsic<[llvm_v4f32_ty, llvm_v2i32_ty], [InstrNoMem]>;
 }
@@ -250,17 +222,69 @@
               Intrinsic<[llvm_void_ty], [IntrWriteMem]>;
 }
 
+// Control register.
+let TargetPrefix = "x86" in {  // All intrinsics start with "llvm.x86.".
+  def int_x86_sse_stmxcsr : GCCBuiltin<"__builtin_ia32_stmxcsr">,
+              Intrinsic<[llvm_void_ty, llvm_ptr_ty], [IntrWriteMem]>;
+  def int_x86_sse_ldmxcsr : GCCBuiltin<"__builtin_ia32_ldmxcsr">,
+              Intrinsic<[llvm_void_ty, llvm_ptr_ty], [IntrWriteMem]>;
+}
+
 // Misc.
 let TargetPrefix = "x86" in {  // All intrinsics start with "llvm.x86.".
   def int_x86_sse_movmsk_ps : GCCBuiltin<"__builtin_ia32_movmskps">,
               Intrinsic<[llvm_int_ty, llvm_v4f32_ty], [InstrNoMem]>;
-  def int_x86_sse_ldmxcsr : GCCBuiltin<"__builtin_ia32_ldmxcsr">,
-              Intrinsic<[llvm_void_ty, llvm_ptr_ty], [IntrWriteMem]>;
 }
 
 //===----------------------------------------------------------------------===//
 // SSE2
 
+// Arithmetic ops
+let TargetPrefix = "x86" in {  // All intrinsics start with "llvm.x86.".
+  def int_x86_sse2_add_sd : GCCBuiltin<"__builtin_ia32_addsd">,
+              Intrinsic<[llvm_v2f64_ty, llvm_v2f64_ty,
+                         llvm_v2f64_ty], [InstrNoMem]>;
+  def int_x86_sse2_sub_sd : GCCBuiltin<"__builtin_ia32_subsd">,
+              Intrinsic<[llvm_v2f64_ty, llvm_v2f64_ty,
+                         llvm_v2f64_ty], [InstrNoMem]>;
+  def int_x86_sse2_mul_sd : GCCBuiltin<"__builtin_ia32_mulsd">,
+              Intrinsic<[llvm_v2f64_ty, llvm_v2f64_ty,
+                         llvm_v2f64_ty], [InstrNoMem]>;
+  def int_x86_sse2_div_sd : GCCBuiltin<"__builtin_ia32_divsd">,
+              Intrinsic<[llvm_v2f64_ty, llvm_v2f64_ty,
+                         llvm_v2f64_ty], [InstrNoMem]>;
+  def int_x86_sse2_sqrt_sd : GCCBuiltin<"__builtin_ia32_sqrtsd">,
+              Intrinsic<[llvm_v2f64_ty, llvm_v2f64_ty],
+                        [InstrNoMem]>;
+  def int_x86_sse2_sqrt_pd : GCCBuiltin<"__builtin_ia32_sqrtpd">,
+              Intrinsic<[llvm_v2f64_ty, llvm_v2f64_ty],
+                        [InstrNoMem]>;
+  def int_x86_sse2_rcp_sd : GCCBuiltin<"__builtin_ia32_rcpsd">,
+              Intrinsic<[llvm_v2f64_ty, llvm_v2f64_ty],
+                        [InstrNoMem]>;
+  def int_x86_sse2_rcp_pd : GCCBuiltin<"__builtin_ia32_rcppd">,
+              Intrinsic<[llvm_v2f64_ty, llvm_v2f64_ty],
+                        [InstrNoMem]>;
+  def int_x86_sse2_rsqrt_sd : GCCBuiltin<"__builtin_ia32_rsqrtsd">,
+              Intrinsic<[llvm_v2f64_ty, llvm_v2f64_ty],
+                        [InstrNoMem]>;
+  def int_x86_sse2_rsqrt_pd : GCCBuiltin<"__builtin_ia32_rsqrtpd">,
+              Intrinsic<[llvm_v2f64_ty, llvm_v2f64_ty],
+                        [InstrNoMem]>;
+  def int_x86_sse2_min_sd : GCCBuiltin<"__builtin_ia32_minsd">,
+              Intrinsic<[llvm_v2f64_ty, llvm_v2f64_ty,
+                         llvm_v2f64_ty], [InstrNoMem]>;
+  def int_x86_sse2_min_pd : GCCBuiltin<"__builtin_ia32_minpd">,
+              Intrinsic<[llvm_v2f64_ty, llvm_v2f64_ty,
+                         llvm_v2f64_ty], [InstrNoMem]>;
+  def int_x86_sse2_max_sd : GCCBuiltin<"__builtin_ia32_maxsd">,
+              Intrinsic<[llvm_v2f64_ty, llvm_v2f64_ty,
+                         llvm_v2f64_ty], [InstrNoMem]>;
+  def int_x86_sse2_max_pd : GCCBuiltin<"__builtin_ia32_maxpd">,
+              Intrinsic<[llvm_v2f64_ty, llvm_v2f64_ty,
+                         llvm_v2f64_ty], [InstrNoMem]>;
+}
+
 let TargetPrefix = "x86" in {  // All intrinsics start with "llvm.x86.".
   def int_x86_sse2_movmskpd : GCCBuiltin<"__builtin_ia32_movmskpd">,
               Intrinsic<[llvm_int_ty, llvm_v2f64_ty], [InstrNoMem]>;





From evan.cheng at apple.com  Wed Mar 29 12:47:52 2006
From: evan.cheng at apple.com (Evan Cheng)
Date: Wed, 29 Mar 2006 12:47:52 -0600
Subject: [llvm-commits] CVS: llvm/lib/Target/X86/X86InstrSSE.td 
Message-ID: <200603291847.MAA10035@zion.cs.uiuc.edu>



Changes in directory llvm/lib/Target/X86:

X86InstrSSE.td updated: 1.42 -> 1.43
---
Log message:

Floating point logical operation patterns should match bit_convert. Or else
integer vector logical operations would match andp{s|d} instead of pand.


---
Diffs of the changes:  (+53 -29)

 X86InstrSSE.td |   82 ++++++++++++++++++++++++++++++++++++---------------------
 1 files changed, 53 insertions(+), 29 deletions(-)


Index: llvm/lib/Target/X86/X86InstrSSE.td
diff -u llvm/lib/Target/X86/X86InstrSSE.td:1.42 llvm/lib/Target/X86/X86InstrSSE.td:1.43
--- llvm/lib/Target/X86/X86InstrSSE.td:1.42	Tue Mar 28 21:04:49 2006
+++ llvm/lib/Target/X86/X86InstrSSE.td	Wed Mar 29 12:47:40 2006
@@ -45,6 +45,9 @@
 def loadv4i32    : PatFrag<(ops node:$ptr), (v4i32 (load node:$ptr))>;
 def loadv2i64    : PatFrag<(ops node:$ptr), (v2i64 (load node:$ptr))>;
 
+def bc_v4i32 : PatFrag<(ops node:$in), (v4i32 (bitconvert node:$in))>;
+def bc_v2i64 : PatFrag<(ops node:$in), (v2i64 (bitconvert node:$in))>;
+
 def fp32imm0 : PatLeaf<(f32 fpimm), [{
   return N->isExactlyValue(+0.0);
 }]>;
@@ -835,64 +838,85 @@
 let isCommutable = 1 in {
 def ANDPSrr : PSI<0x54, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
                   "andps {$src2, $dst|$dst, $src2}",
-                  [(set VR128:$dst, (v4i32 (and VR128:$src1, VR128:$src2)))]>;
+                  [(set VR128:$dst,
+                    (and (bc_v4i32 (v4f32 VR128:$src1)),
+                     (bc_v4i32 (v4f32 VR128:$src2))))]>;
 def ANDPDrr : PDI<0x54, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
                 "andpd {$src2, $dst|$dst, $src2}",
-                  [(set VR128:$dst, (v2i64 (and VR128:$src1, VR128:$src2)))]>;
+                  [(set VR128:$dst,
+                    (and (bc_v2i64 (v2f64 VR128:$src1)),
+                     (bc_v2i64 (v2f64 VR128:$src2))))]>;
 def ORPSrr  : PSI<0x56, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
                   "orps {$src2, $dst|$dst, $src2}",
-                  [(set VR128:$dst, (v4i32 (or VR128:$src1, VR128:$src2)))]>;
+                  [(set VR128:$dst,
+                    (or (bc_v4i32 (v4f32 VR128:$src1)),
+                     (bc_v4i32 (v4f32 VR128:$src2))))]>;
 def ORPDrr  : PDI<0x56, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
                   "orpd {$src2, $dst|$dst, $src2}",
-                  [(set VR128:$dst, (v2i64 (or VR128:$src1, VR128:$src2)))]>;
+                  [(set VR128:$dst,
+                    (or (bc_v2i64 (v2f64 VR128:$src1)),
+                     (bc_v2i64 (v2f64 VR128:$src2))))]>;
 def XORPSrr : PSI<0x57, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
                   "xorps {$src2, $dst|$dst, $src2}",
-                  [(set VR128:$dst, (v4i32 (xor VR128:$src1, VR128:$src2)))]>;
+                  [(set VR128:$dst,
+                    (xor (bc_v4i32 (v4f32 VR128:$src1)),
+                     (bc_v4i32 (v4f32 VR128:$src2))))]>;
 def XORPDrr : PDI<0x57, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
                   "xorpd {$src2, $dst|$dst, $src2}",
-                  [(set VR128:$dst, (v2i64 (xor VR128:$src1, VR128:$src2)))]>;
+                  [(set VR128:$dst,
+                    (xor (bc_v2i64 (v2f64 VR128:$src1)),
+                     (bc_v2i64 (v2f64 VR128:$src2))))]>;
 }
 def ANDPSrm : PSI<0x54, MRMSrcMem, (ops VR128:$dst, VR128:$src1, f128mem:$src2),
                   "andps {$src2, $dst|$dst, $src2}",
-                  [(set VR128:$dst, (v4i32 (and VR128:$src1,
-                                            (load addr:$src2))))]>;
+                [(set VR128:$dst,
+                  (and (bc_v4i32 (v4f32 VR128:$src1)),
+                   (bc_v4i32 (loadv4f32 addr:$src2))))]>;
 def ANDPDrm : PDI<0x54, MRMSrcMem, (ops VR128:$dst, VR128:$src1, f128mem:$src2),
                   "andpd {$src2, $dst|$dst, $src2}",
-                  [(set VR128:$dst, (v2i64 (and VR128:$src1,
-                                            (load addr:$src2))))]>;
+                [(set VR128:$dst,
+                  (and (bc_v2i64 (v2f64 VR128:$src1)),
+                   (bc_v2i64 (loadv2f64 addr:$src2))))]>;
 def ORPSrm  : PSI<0x56, MRMSrcMem, (ops VR128:$dst, VR128:$src1, f128mem:$src2),
                   "orps {$src2, $dst|$dst, $src2}",
-                  [(set VR128:$dst, (v4i32 (or VR128:$src1,
-                                            (load addr:$src2))))]>;
+                 [(set VR128:$dst,
+                   (or (bc_v4i32 (v4f32 VR128:$src1)),
+                    (bc_v4i32 (loadv4f32 addr:$src2))))]>;
 def ORPDrm  : PDI<0x56, MRMSrcMem, (ops VR128:$dst, VR128:$src1, f128mem:$src2),
                 "orpd {$src2, $dst|$dst, $src2}",
-                  [(set VR128:$dst, (v2i64 (or VR128:$src1,
-                                            (load addr:$src2))))]>;
+                 [(set VR128:$dst,
+                   (or (bc_v2i64 (v2f64 VR128:$src1)),
+                    (bc_v2i64 (loadv2f64 addr:$src2))))]>;
 def XORPSrm : PSI<0x57, MRMSrcMem, (ops VR128:$dst, VR128:$src1, f128mem:$src2),
                   "xorps {$src2, $dst|$dst, $src2}",
-                  [(set VR128:$dst, (v4i32 (xor VR128:$src1,
-                                            (load addr:$src2))))]>;
+                [(set VR128:$dst,
+                  (xor (bc_v4i32 (v4f32 VR128:$src1)),
+                   (bc_v4i32 (loadv4f32 addr:$src2))))]>;
 def XORPDrm : PDI<0x57, MRMSrcMem, (ops VR128:$dst, VR128:$src1, f128mem:$src2),
                   "xorpd {$src2, $dst|$dst, $src2}",
-                  [(set VR128:$dst, (v2i64 (xor VR128:$src1,
-                                            (load addr:$src2))))]>;
+                [(set VR128:$dst,
+                  (xor (bc_v2i64 (v2f64 VR128:$src1)),
+                   (bc_v2i64 (loadv2f64 addr:$src2))))]>;
 def ANDNPSrr : PSI<0x55, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
                   "andnps {$src2, $dst|$dst, $src2}",
-                  [(set VR128:$dst, (v4i32 (and (not VR128:$src1),
-                                            VR128:$src2)))]>;
-def ANDNPSrm : PSI<0x55, MRMSrcMem, (ops VR128:$dst, VR128:$src1, f128mem:$src2),
+                [(set VR128:$dst,
+                  (and (vnot (bc_v4i32 (v4f32 VR128:$src1))),
+                   (bc_v4i32 (v4f32 VR128:$src2))))]>;
+def ANDNPSrm : PSI<0x55, MRMSrcMem, (ops VR128:$dst, VR128:$src1,f128mem:$src2),
                   "andnps {$src2, $dst|$dst, $src2}",
-                  [(set VR128:$dst, (v4i32 (and (not VR128:$src1),
-                                            (load addr:$src2))))]>;
+                  [(set VR128:$dst,
+                    (and (vnot (bc_v4i32 (v4f32 VR128:$src1))),
+                     (bc_v4i32 (loadv4f32 addr:$src2))))]>;
 def ANDNPDrr : PDI<0x55, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
                   "andnpd {$src2, $dst|$dst, $src2}",
-                  [(set VR128:$dst, (v2i64 (and (not VR128:$src1),
-                                            VR128:$src2)))]>;
-
-def ANDNPDrm : PDI<0x55, MRMSrcMem, (ops VR128:$dst, VR128:$src1, f128mem:$src2),
+                [(set VR128:$dst,
+                  (and (vnot (bc_v2i64 (v2f64 VR128:$src1))),
+                   (bc_v2i64 (v2f64 VR128:$src2))))]>;
+def ANDNPDrm : PDI<0x55, MRMSrcMem, (ops VR128:$dst, VR128:$src1,f128mem:$src2),
                   "andnpd {$src2, $dst|$dst, $src2}",
-                  [(set VR128:$dst, (v2i64 (and VR128:$src1,
-                                            (load addr:$src2))))]>;
+                  [(set VR128:$dst,
+                    (and (vnot (bc_v2i64 (v2f64 VR128:$src1))),
+                     (bc_v2i64 (loadv2f64 addr:$src2))))]>;
 }
 
 let isTwoAddress = 1 in {





From evan.cheng at apple.com  Wed Mar 29 13:00:01 2006
From: evan.cheng at apple.com (Evan Cheng)
Date: Wed, 29 Mar 2006 13:00:01 -0600
Subject: [llvm-commits] CVS: llvm/test/Regression/CodeGen/X86/vec_splat.ll 
Message-ID: <200603291900.NAA10108@zion.cs.uiuc.edu>



Changes in directory llvm/test/Regression/CodeGen/X86:

vec_splat.ll updated: 1.1 -> 1.2
---
Log message:

Use unpcklpd for v2f64 splat.


---
Diffs of the changes:  (+1 -1)

 vec_splat.ll |    2 +-
 1 files changed, 1 insertion(+), 1 deletion(-)


Index: llvm/test/Regression/CodeGen/X86/vec_splat.ll
diff -u llvm/test/Regression/CodeGen/X86/vec_splat.ll:1.1 llvm/test/Regression/CodeGen/X86/vec_splat.ll:1.2
--- llvm/test/Regression/CodeGen/X86/vec_splat.ll:1.1	Wed Mar 22 15:39:25 2006
+++ llvm/test/Regression/CodeGen/X86/vec_splat.ll	Wed Mar 29 12:59:48 2006
@@ -1,5 +1,5 @@
 ; RUN: llvm-as < %s | llc -march=x86 -mattr=+sse2 | grep shufps
-; RUN: llvm-as < %s | llc -march=x86 -mattr=+sse2 | grep movlhps
+; RUN: llvm-as < %s | llc -march=x86 -mattr=+sse2 | grep unpcklpd
 
 void %test_v4sf(<4 x float>* %P, <4 x float>* %Q, float %X) {
 	%tmp = insertelement <4 x float> zeroinitializer, float %X, uint 0





From evan.cheng at apple.com  Wed Mar 29 13:02:52 2006
From: evan.cheng at apple.com (Evan Cheng)
Date: Wed, 29 Mar 2006 13:02:52 -0600
Subject: [llvm-commits] CVS: llvm/lib/Target/X86/X86ISelLowering.cpp
	X86InstrSSE.td 
Message-ID: <200603291902.NAA10139@zion.cs.uiuc.edu>



Changes in directory llvm/lib/Target/X86:

X86ISelLowering.cpp updated: 1.143 -> 1.144
X86InstrSSE.td updated: 1.43 -> 1.44
---
Log message:

Need to special case splat after all. Make the second operand of splat
vector_shuffle undef.


---
Diffs of the changes:  (+18 -15)

 X86ISelLowering.cpp |   16 ++++++++--------
 X86InstrSSE.td      |   17 ++++++++++-------
 2 files changed, 18 insertions(+), 15 deletions(-)


Index: llvm/lib/Target/X86/X86ISelLowering.cpp
diff -u llvm/lib/Target/X86/X86ISelLowering.cpp:1.143 llvm/lib/Target/X86/X86ISelLowering.cpp:1.144
--- llvm/lib/Target/X86/X86ISelLowering.cpp:1.143	Tue Mar 28 21:04:49 2006
+++ llvm/lib/Target/X86/X86ISelLowering.cpp	Wed Mar 29 13:02:40 2006
@@ -2397,21 +2397,21 @@
     MVT::ValueType VT = Op.getValueType();
     unsigned NumElems = PermMask.getNumOperands();
 
-    if (X86::isUNPCKLMask(PermMask.Val) ||
-        X86::isUNPCKHMask(PermMask.Val))
-      // Leave the VECTOR_SHUFFLE alone. It matches {P}UNPCKL*.
-      return SDOperand();
-
-    // PSHUFD's 2nd vector must be undef.
-    if (MVT::isInteger(VT) && X86::isPSHUFDMask(PermMask.Val)) {
+    // Splat && PSHUFD's 2nd vector must be undef.
+    if (X86::isSplatMask(PermMask.Val) ||
+        ((MVT::isInteger(VT) && X86::isPSHUFDMask(PermMask.Val)))) {
       if (V2.getOpcode() != ISD::UNDEF)
         return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1,
                            DAG.getNode(ISD::UNDEF, V1.getValueType()),PermMask);
       return SDOperand();
     }
 
+    if (X86::isUNPCKLMask(PermMask.Val) ||
+        X86::isUNPCKHMask(PermMask.Val))
+      // Leave the VECTOR_SHUFFLE alone. It matches {P}UNPCKL*.
+      return SDOperand();
+
     if (NumElems == 2 ||
-        X86::isSplatMask(PermMask.Val) ||
         X86::isSHUFPMask(PermMask.Val)) {
       return NormalizeVectorShuffle(V1, V2, PermMask, VT, DAG);
     }


Index: llvm/lib/Target/X86/X86InstrSSE.td
diff -u llvm/lib/Target/X86/X86InstrSSE.td:1.43 llvm/lib/Target/X86/X86InstrSSE.td:1.44
--- llvm/lib/Target/X86/X86InstrSSE.td:1.43	Wed Mar 29 12:47:40 2006
+++ llvm/lib/Target/X86/X86InstrSSE.td	Wed Mar 29 13:02:40 2006
@@ -58,9 +58,9 @@
   return getI8Imm(X86::getShuffleSHUFImmediate(N));
 }]>;
 
-def v2f64_v2i64_splat_mask : PatLeaf<(build_vector), [{
+def SSE_splat_mask : PatLeaf<(build_vector), [{
   return X86::isSplatMask(N);
-}]>;
+}], SHUFFLE_get_shuf_imm>;
 
 def MOVLHPS_shuffle_mask : PatLeaf<(build_vector), [{
   return X86::isMOVLHPSMask(N);
@@ -1375,13 +1375,16 @@
           (MOVZD128rr (V_SET0_PI), (MOVZX32rr8 R8:$src))>, Requires<[HasSSE2]>;
 
 // Splat v2f64 / v2i64
-def : Pat<(vector_shuffle (v2f64 VR128:$src), (v2f64 VR128:$src),
-           v2f64_v2i64_splat_mask:$sm),
-          (v2f64 (UNPCKLPDrr VR128:$src, VR128:$src))>, Requires<[HasSSE2]>;
-def : Pat<(vector_shuffle (v2i64 VR128:$src), (v2i64 VR128:$src),
-           v2f64_v2i64_splat_mask:$sm),
+def : Pat<(vector_shuffle (v2f64 VR128:$src), (undef), SSE_splat_mask:$sm),
+          (v2f64 (UNPCKLPDrr VR128:$src, VR128:$src))>,   Requires<[HasSSE2]>;
+def : Pat<(vector_shuffle (v2i64 VR128:$src), (undef), SSE_splat_mask:$sm),
           (v2i64 (PUNPCKLQDQrr VR128:$src, VR128:$src))>, Requires<[HasSSE2]>;
 
+// Splat v4f32
+def : Pat<(vector_shuffle (v4f32 VR128:$src), (undef), SSE_splat_mask:$sm),
+          (v4f32 (SHUFPSrr VR128:$src, VR128:$src, SSE_splat_mask:$sm))>,
+      Requires<[HasSSE1]>;
+
 // Shuffle v4i32 if others do not match
 def : Pat<(vector_shuffle (v4i32 VR128:$src1), (v4i32 VR128:$src2),
            SHUFP_shuffle_mask:$sm),





From evan.cheng at apple.com  Wed Mar 29 16:51:40 2006
From: evan.cheng at apple.com (Evan Cheng)
Date: Wed, 29 Mar 2006 16:51:40 -0600
Subject: [llvm-commits] CVS: llvm/test/Regression/CodeGen/X86/vec_shuffle.ll
Message-ID: <200603292251.QAA17737@zion.cs.uiuc.edu>



Changes in directory llvm/test/Regression/CodeGen/X86:

vec_shuffle.ll updated: 1.3 -> 1.4
---
Log message:

Add a pshufhw test case.


---
Diffs of the changes:  (+25 -0)

 vec_shuffle.ll |   25 +++++++++++++++++++++++++
 1 files changed, 25 insertions(+)


Index: llvm/test/Regression/CodeGen/X86/vec_shuffle.ll
diff -u llvm/test/Regression/CodeGen/X86/vec_shuffle.ll:1.3 llvm/test/Regression/CodeGen/X86/vec_shuffle.ll:1.4
--- llvm/test/Regression/CodeGen/X86/vec_shuffle.ll:1.3	Tue Mar 28 00:40:57 2006
+++ llvm/test/Regression/CodeGen/X86/vec_shuffle.ll	Wed Mar 29 16:51:28 2006
@@ -1,5 +1,6 @@
 ; RUN: llvm-as < %s | llc -march=x86 -mattr=+sse2 | grep shufp | wc -l | grep 1
 ; RUN: llvm-as < %s | llc -march=x86 -mattr=+sse2 | grep movhpd
+; RUN: llvm-as < %s | llc -march=x86 -mattr=+sse2 | grep pshufhw
 
 void %test_v4sf(<4 x float>* %P, float %X, float %Y) {
 	%tmp = insertelement <4 x float> zeroinitializer, float %X, uint 0
@@ -16,3 +17,27 @@
 	store <2 x double> %tmp2, <2 x double>* %P
 	ret void
 }
+
+void %test_v8i16(<2 x long>* %res, <2 x long>* %A) {
+	%tmp = load <2 x long>* %A
+	%tmp = cast <2 x long> %tmp to <8 x short>
+	%tmp = extractelement <8 x short> %tmp, uint 0
+	%tmp1 = extractelement <8 x short> %tmp, uint 1
+	%tmp2 = extractelement <8 x short> %tmp, uint 2
+	%tmp3 = extractelement <8 x short> %tmp, uint 3
+	%tmp4 = extractelement <8 x short> %tmp, uint 6
+	%tmp5 = extractelement <8 x short> %tmp, uint 5
+	%tmp6 = extractelement <8 x short> %tmp, uint 4
+	%tmp7 = extractelement <8 x short> %tmp, uint 7
+	%tmp8 = insertelement <8 x short> undef, short %tmp, uint 0
+	%tmp9 = insertelement <8 x short> %tmp8, short %tmp1, uint 1
+	%tmp10 = insertelement <8 x short> %tmp9, short %tmp2, uint 2
+	%tmp11 = insertelement <8 x short> %tmp10, short %tmp3, uint 3
+	%tmp12 = insertelement <8 x short> %tmp11, short %tmp4, uint 4
+	%tmp13 = insertelement <8 x short> %tmp12, short %tmp5, uint 5
+	%tmp14 = insertelement <8 x short> %tmp13, short %tmp6, uint 6
+	%tmp15 = insertelement <8 x short> %tmp14, short %tmp7, uint 7
+	%tmp15 = cast <8 x short> %tmp15 to <2 x long>
+	store <2 x long> %tmp15, <2 x long>* %res
+	ret void
+}





From evan.cheng at apple.com  Wed Mar 29 17:07:26 2006
From: evan.cheng at apple.com (Evan Cheng)
Date: Wed, 29 Mar 2006 17:07:26 -0600
Subject: [llvm-commits] CVS: llvm/lib/Target/X86/X86ISelLowering.cpp
	X86ISelLowering.h X86InstrSSE.td 
Message-ID: <200603292307.RAA17891@zion.cs.uiuc.edu>



Changes in directory llvm/lib/Target/X86:

X86ISelLowering.cpp updated: 1.144 -> 1.145
X86ISelLowering.h updated: 1.47 -> 1.48
X86InstrSSE.td updated: 1.44 -> 1.45
---
Log message:

- Added some SSE2 128-bit packed integer ops.
- Added SSE2 128-bit integer pack with signed saturation ops.
- Added pshufhw and pshuflw ops.


---
Diffs of the changes:  (+314 -25)

 X86ISelLowering.cpp |  106 ++++++++++++++++++++++++-
 X86ISelLowering.h   |   18 ++++
 X86InstrSSE.td      |  215 +++++++++++++++++++++++++++++++++++++++++++++++-----
 3 files changed, 314 insertions(+), 25 deletions(-)


Index: llvm/lib/Target/X86/X86ISelLowering.cpp
diff -u llvm/lib/Target/X86/X86ISelLowering.cpp:1.144 llvm/lib/Target/X86/X86ISelLowering.cpp:1.145
--- llvm/lib/Target/X86/X86ISelLowering.cpp:1.144	Wed Mar 29 13:02:40 2006
+++ llvm/lib/Target/X86/X86ISelLowering.cpp	Wed Mar 29 17:07:14 2006
@@ -1399,10 +1399,67 @@
     return false;
 
   // Check if the value doesn't reference the second vector.
-  for (unsigned i = 1, e = N->getNumOperands(); i != e; ++i) {
+  for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
     assert(isa<ConstantSDNode>(N->getOperand(i)) &&
            "Invalid VECTOR_SHUFFLE mask!");
-    if (cast<ConstantSDNode>(N->getOperand(i))->getValue() >= 4) return false;
+    if (cast<ConstantSDNode>(N->getOperand(i))->getValue() >= 4)
+      return false;
+  }
+
+  return true;
+}
+
+/// isPSHUFHWMask - Return true if the specified VECTOR_SHUFFLE operand
+/// specifies a shuffle of elements that is suitable for input to PSHUFD.
+bool X86::isPSHUFHWMask(SDNode *N) {
+  assert(N->getOpcode() == ISD::BUILD_VECTOR);
+
+  if (N->getNumOperands() != 8)
+    return false;
+
+  // Lower quadword copied in order.
+  for (unsigned i = 0; i != 4; ++i) {
+    assert(isa<ConstantSDNode>(N->getOperand(i)) &&
+           "Invalid VECTOR_SHUFFLE mask!");
+    if (cast<ConstantSDNode>(N->getOperand(i))->getValue() != i)
+      return false;
+  }
+
+  // Upper quadword shuffled.
+  for (unsigned i = 4; i != 8; ++i) {
+    assert(isa<ConstantSDNode>(N->getOperand(i)) &&
+           "Invalid VECTOR_SHUFFLE mask!");
+    unsigned Val = cast<ConstantSDNode>(N->getOperand(i))->getValue();
+    if (Val < 4 || Val > 7)
+      return false;
+  }
+
+  return true;
+}
+
+/// isPSHUFLWMask - Return true if the specified VECTOR_SHUFFLE operand
+/// specifies a shuffle of elements that is suitable for input to PSHUFD.
+bool X86::isPSHUFLWMask(SDNode *N) {
+  assert(N->getOpcode() == ISD::BUILD_VECTOR);
+
+  if (N->getNumOperands() != 8)
+    return false;
+
+  // Upper quadword copied in order.
+  for (unsigned i = 4; i != 8; ++i) {
+    assert(isa<ConstantSDNode>(N->getOperand(i)) &&
+           "Invalid VECTOR_SHUFFLE mask!");
+    if (cast<ConstantSDNode>(N->getOperand(i))->getValue() != i)
+      return false;
+  }
+
+  // Lower quadword shuffled.
+  for (unsigned i = 0; i != 4; ++i) {
+    assert(isa<ConstantSDNode>(N->getOperand(i)) &&
+           "Invalid VECTOR_SHUFFLE mask!");
+    unsigned Val = cast<ConstantSDNode>(N->getOperand(i))->getValue();
+    if (Val > 4)
+      return false;
   }
 
   return true;
@@ -1431,7 +1488,7 @@
   // Each half must refer to only one of the vector.
   SDOperand Elt = N->getOperand(0);
   assert(isa<ConstantSDNode>(Elt) && "Invalid VECTOR_SHUFFLE mask!");
-  for (unsigned i = 1; i != NumElems / 2; ++i) {
+  for (unsigned i = 1; i < NumElems / 2; ++i) {
     assert(isa<ConstantSDNode>(N->getOperand(i)) &&
            "Invalid VECTOR_SHUFFLE mask!");
     if (cast<ConstantSDNode>(N->getOperand(i))->getValue() != 
@@ -1440,7 +1497,7 @@
   }
   Elt = N->getOperand(NumElems / 2);
   assert(isa<ConstantSDNode>(Elt) && "Invalid VECTOR_SHUFFLE mask!");
-  for (unsigned i = NumElems / 2; i != NumElems; ++i) {
+  for (unsigned i = NumElems / 2 + 1; i < NumElems; ++i) {
     assert(isa<ConstantSDNode>(N->getOperand(i)) &&
            "Invalid VECTOR_SHUFFLE mask!");
     if (cast<ConstantSDNode>(N->getOperand(i))->getValue() != 
@@ -1583,6 +1640,40 @@
   return Mask;
 }
 
+/// getShufflePSHUFHWImmediate - Return the appropriate immediate to shuffle
+/// the specified isShuffleMask VECTOR_SHUFFLE mask with PSHUFHW
+/// instructions.
+unsigned X86::getShufflePSHUFHWImmediate(SDNode *N) {
+  unsigned Mask = 0;
+  // 8 nodes, but we only care about the last 4.
+  for (unsigned i = 7; i >= 4; --i) {
+    unsigned Val
+      = cast<ConstantSDNode>(N->getOperand(i))->getValue();
+    Mask |= (Val - 4);
+    if (i != 4)
+      Mask <<= 2;
+  }
+
+  return Mask;
+}
+
+/// getShufflePSHUFLWImmediate - Return the appropriate immediate to shuffle
+/// the specified isShuffleMask VECTOR_SHUFFLE mask with PSHUFLW
+/// instructions.
+unsigned X86::getShufflePSHUFLWImmediate(SDNode *N) {
+  unsigned Mask = 0;
+  // 8 nodes, but we only care about the first 4.
+  for (int i = 3; i >= 0; --i) {
+    unsigned Val
+      = cast<ConstantSDNode>(N->getOperand(i))->getValue();
+    Mask |= Val;
+    if (i != 0)
+      Mask <<= 2;
+  }
+
+  return Mask;
+}
+
 /// NormalizeVectorShuffle - Swap vector_shuffle operands (as well as
 /// values in ther permute mask if needed. Use V1 as second vector if it is
 /// undef. Return an empty SDOperand is it is already well formed.
@@ -2399,7 +2490,10 @@
 
     // Splat && PSHUFD's 2nd vector must be undef.
     if (X86::isSplatMask(PermMask.Val) ||
-        ((MVT::isInteger(VT) && X86::isPSHUFDMask(PermMask.Val)))) {
+        ((MVT::isInteger(VT) &&
+          (X86::isPSHUFDMask(PermMask.Val) ||
+           X86::isPSHUFHWMask(PermMask.Val) ||
+           X86::isPSHUFLWMask(PermMask.Val))))) {
       if (V2.getOpcode() != ISD::UNDEF)
         return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1,
                            DAG.getNode(ISD::UNDEF, V1.getValueType()),PermMask);
@@ -2607,6 +2701,8 @@
   return (Mask.Val->getNumOperands() == 2 ||
           X86::isSplatMask(Mask.Val) ||
           X86::isPSHUFDMask(Mask.Val) ||
+          X86::isPSHUFHWMask(Mask.Val) ||
+          X86::isPSHUFLWMask(Mask.Val) ||
           X86::isSHUFPMask(Mask.Val) ||
           X86::isUNPCKLMask(Mask.Val) ||
           X86::isUNPCKHMask(Mask.Val));


Index: llvm/lib/Target/X86/X86ISelLowering.h
diff -u llvm/lib/Target/X86/X86ISelLowering.h:1.47 llvm/lib/Target/X86/X86ISelLowering.h:1.48
--- llvm/lib/Target/X86/X86ISelLowering.h:1.47	Tue Mar 28 00:50:32 2006
+++ llvm/lib/Target/X86/X86ISelLowering.h	Wed Mar 29 17:07:14 2006
@@ -184,6 +184,14 @@
    /// specifies a shuffle of elements that is suitable for input to PSHUFD.
    bool isPSHUFDMask(SDNode *N);
 
+   /// isPSHUFHWMask - Return true if the specified VECTOR_SHUFFLE operand
+   /// specifies a shuffle of elements that is suitable for input to PSHUFD.
+   bool isPSHUFHWMask(SDNode *N);
+
+   /// isPSHUFLWMask - Return true if the specified VECTOR_SHUFFLE operand
+   /// specifies a shuffle of elements that is suitable for input to PSHUFD.
+   bool isPSHUFLWMask(SDNode *N);
+
    /// isSHUFPMask - Return true if the specified VECTOR_SHUFFLE operand
    /// specifies a shuffle of elements that is suitable for input to SHUFP*.
    bool isSHUFPMask(SDNode *N);
@@ -212,6 +220,16 @@
    /// the specified isShuffleMask VECTOR_SHUFFLE mask with PSHUF* and SHUFP*
    /// instructions.
    unsigned getShuffleSHUFImmediate(SDNode *N);
+
+   /// getShufflePSHUFHWImmediate - Return the appropriate immediate to shuffle
+   /// the specified isShuffleMask VECTOR_SHUFFLE mask with PSHUFHW
+   /// instructions.
+   unsigned getShufflePSHUFHWImmediate(SDNode *N);
+
+   /// getShufflePSHUFKWImmediate - Return the appropriate immediate to shuffle
+   /// the specified isShuffleMask VECTOR_SHUFFLE mask with PSHUFLW
+   /// instructions.
+   unsigned getShufflePSHUFLWImmediate(SDNode *N);
  }
 
   //===----------------------------------------------------------------------===//


Index: llvm/lib/Target/X86/X86InstrSSE.td
diff -u llvm/lib/Target/X86/X86InstrSSE.td:1.44 llvm/lib/Target/X86/X86InstrSSE.td:1.45
--- llvm/lib/Target/X86/X86InstrSSE.td:1.44	Wed Mar 29 13:02:40 2006
+++ llvm/lib/Target/X86/X86InstrSSE.td	Wed Mar 29 17:07:14 2006
@@ -45,6 +45,8 @@
 def loadv4i32    : PatFrag<(ops node:$ptr), (v4i32 (load node:$ptr))>;
 def loadv2i64    : PatFrag<(ops node:$ptr), (v2i64 (load node:$ptr))>;
 
+def bc_v16i8 : PatFrag<(ops node:$in), (v16i8 (bitconvert node:$in))>;
+def bc_v8i16 : PatFrag<(ops node:$in), (v8i16 (bitconvert node:$in))>;
 def bc_v4i32 : PatFrag<(ops node:$in), (v4i32 (bitconvert node:$in))>;
 def bc_v2i64 : PatFrag<(ops node:$in), (v2i64 (bitconvert node:$in))>;
 
@@ -58,6 +60,18 @@
   return getI8Imm(X86::getShuffleSHUFImmediate(N));
 }]>;
 
+// SHUFFLE_get_pshufhw_imm xform function: convert vector_shuffle mask to 
+// PSHUFHW imm.
+def SHUFFLE_get_pshufhw_imm : SDNodeXForm<build_vector, [{
+  return getI8Imm(X86::getShufflePSHUFHWImmediate(N));
+}]>;
+
+// SHUFFLE_get_pshuflw_imm xform function: convert vector_shuffle mask to 
+// PSHUFLW imm.
+def SHUFFLE_get_pshuflw_imm : SDNodeXForm<build_vector, [{
+  return getI8Imm(X86::getShufflePSHUFLWImmediate(N));
+}]>;
+
 def SSE_splat_mask : PatLeaf<(build_vector), [{
   return X86::isSplatMask(N);
 }], SHUFFLE_get_shuf_imm>;
@@ -82,6 +96,14 @@
   return X86::isPSHUFDMask(N);
 }], SHUFFLE_get_shuf_imm>;
 
+def PSHUFHW_shuffle_mask : PatLeaf<(build_vector), [{
+  return X86::isPSHUFHWMask(N);
+}], SHUFFLE_get_pshufhw_imm>;
+
+def PSHUFLW_shuffle_mask : PatLeaf<(build_vector), [{
+  return X86::isPSHUFLWMask(N);
+}], SHUFFLE_get_pshuflw_imm>;
+
 def SHUFP_shuffle_mask : PatLeaf<(build_vector), [{
   return X86::isSHUFPMask(N);
 }], SHUFFLE_get_shuf_imm>;
@@ -935,25 +957,6 @@
 }
 
 // Shuffle and unpack instructions
-def PSHUFWrr : PSIi8<0x70, MRMDestReg,
-                     (ops VR64:$dst, VR64:$src1, i8imm:$src2),
-                     "pshufw {$src2, $src1, $dst|$dst, $src1, $src2}", []>;
-def PSHUFWrm : PSIi8<0x70, MRMSrcMem,
-                     (ops VR64:$dst, i64mem:$src1, i8imm:$src2),
-                     "pshufw {$src2, $src1, $dst|$dst, $src1, $src2}", []>;
-def PSHUFDrr : PDIi8<0x70, MRMDestReg,
-                     (ops VR128:$dst, VR128:$src1, i8imm:$src2),
-                     "pshufd {$src2, $src1, $dst|$dst, $src1, $src2}",
-                     [(set VR128:$dst, (v4i32 (vector_shuffle
-                                               VR128:$src1, (undef),
-                                               PSHUFD_shuffle_mask:$src2)))]>;
-def PSHUFDrm : PDIi8<0x70, MRMSrcMem,
-                     (ops VR128:$dst, i128mem:$src1, i8imm:$src2),
-                     "pshufd {$src2, $src1, $dst|$dst, $src1, $src2}",
-                     [(set VR128:$dst, (v4i32 (vector_shuffle
-                                               (load addr:$src1), (undef),
-                                               PSHUFD_shuffle_mask:$src2)))]>;
-
 let isTwoAddress = 1 in {
 def SHUFPSrr : PSIi8<0xC6, MRMSrcReg, 
                      (ops VR128:$dst, VR128:$src1, VR128:$src2, i32i8imm:$src3),
@@ -1081,6 +1084,10 @@
 def PADDDrr : PDI<0xFE, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
                   "paddd {$src2, $dst|$dst, $src2}",
               [(set VR128:$dst, (v4i32 (add VR128:$src1, VR128:$src2)))]>;
+
+def PADDQrr : PDI<0xD4, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
+                  "paddq {$src2, $dst|$dst, $src2}",
+              [(set VR128:$dst, (v2i64 (add VR128:$src1, VR128:$src2)))]>;
 }
 def PADDBrm : PDI<0xFC, MRMSrcMem, (ops VR128:$dst, VR128:$src1, f128mem:$src2),
                   "paddb {$src2, $dst|$dst, $src2}",
@@ -1094,6 +1101,10 @@
                   "paddd {$src2, $dst|$dst, $src2}",
               [(set VR128:$dst, (v4i32 (add VR128:$src1,
                                         (load addr:$src2))))]>;
+def PADDQrm : PDI<0xD4, MRMSrcMem, (ops VR128:$dst, VR128:$src1, f128mem:$src2),
+                  "paddd {$src2, $dst|$dst, $src2}",
+              [(set VR128:$dst, (v2i64 (add VR128:$src1,
+                                        (load addr:$src2))))]>;
 
 def PSUBBrr : PDI<0xF8, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
                   "psubb {$src2, $dst|$dst, $src2}",
@@ -1104,6 +1115,9 @@
 def PSUBDrr : PDI<0xFA, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
                   "psubd {$src2, $dst|$dst, $src2}",
               [(set VR128:$dst, (v4i32 (sub VR128:$src1, VR128:$src2)))]>;
+def PSUBQrr : PDI<0xFB, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
+                  "psubq {$src2, $dst|$dst, $src2}",
+              [(set VR128:$dst, (v2i64 (sub VR128:$src1, VR128:$src2)))]>;
 
 def PSUBBrm : PDI<0xF8, MRMSrcMem, (ops VR128:$dst, VR128:$src1, f128mem:$src2),
                   "psubb {$src2, $dst|$dst, $src2}",
@@ -1117,8 +1131,146 @@
                   "psubd {$src2, $dst|$dst, $src2}",
               [(set VR128:$dst, (v4i32 (sub VR128:$src1,
                                         (load addr:$src2))))]>;
+def PSUBQrm : PDI<0xFB, MRMSrcMem, (ops VR128:$dst, VR128:$src1, f128mem:$src2),
+                  "psubd {$src2, $dst|$dst, $src2}",
+              [(set VR128:$dst, (v2i64 (sub VR128:$src1,
+                                        (load addr:$src2))))]>;
+}
 
-// Unpack and interleave
+// Logical
+let isTwoAddress = 1 in {
+let isCommutable = 1 in {
+def PANDrr : PDI<0xDB, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
+                 "pand {$src2, $dst|$dst, $src2}",
+                 [(set VR128:$dst, (v2i64 (and VR128:$src1, VR128:$src2)))]>;
+
+def PANDrm : PDI<0xDB, MRMSrcMem, (ops VR128:$dst, VR128:$src1, i128mem:$src2),
+                 "pand {$src2, $dst|$dst, $src2}",
+                 [(set VR128:$dst, (v2i64 (and VR128:$src1,
+                                           (load addr:$src2))))]>;
+def PORrr  : PDI<0xDB, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
+                 "por {$src2, $dst|$dst, $src2}",
+                 [(set VR128:$dst, (v2i64 (or VR128:$src1, VR128:$src2)))]>;
+
+def PORrm  : PDI<0xDB, MRMSrcMem, (ops VR128:$dst, VR128:$src1, i128mem:$src2),
+                 "por {$src2, $dst|$dst, $src2}",
+                 [(set VR128:$dst, (v2i64 (or VR128:$src1,
+                                           (load addr:$src2))))]>;
+def PXORrr : PDI<0xEF, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
+                 "pxor {$src2, $dst|$dst, $src2}",
+                 [(set VR128:$dst, (v2i64 (xor VR128:$src1, VR128:$src2)))]>;
+
+def PXORrm : PDI<0xEF, MRMSrcMem, (ops VR128:$dst, VR128:$src1, i128mem:$src2),
+                 "pxor {$src2, $dst|$dst, $src2}",
+                 [(set VR128:$dst, (v2i64 (xor VR128:$src1,
+                                           (load addr:$src2))))]>;
+}
+
+def PANDNrr : PDI<0xDF, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
+                  "pandn {$src2, $dst|$dst, $src2}",
+                  [(set VR128:$dst, (v2i64 (and (vnot VR128:$src1),
+                                            VR128:$src2)))]>;
+
+def PANDNrm : PDI<0xDF, MRMSrcMem, (ops VR128:$dst, VR128:$src1, i128mem:$src2),
+                 "pandn {$src2, $dst|$dst, $src2}",
+                 [(set VR128:$dst, (v2i64 (and (vnot VR128:$src1),
+                                           (load addr:$src2))))]>;
+}
+
+// Pack instructions
+let isTwoAddress = 1 in {
+def PACKSSWBrr : PDI<0x63, MRMSrcReg, (ops VR128:$dst, VR128:$src1,
+                                       VR128:$src2),
+                 "packsswb {$src2, $dst|$dst, $src2}",
+                 [(set VR128:$dst, (v16i8 (int_x86_sse2_packsswb_128
+                                           (v8i16 VR128:$src1),
+                                           (v8i16 VR128:$src2))))]>;
+def PACKSSWBrm : PDI<0x63, MRMSrcMem, (ops VR128:$dst, VR128:$src1,
+                                       i128mem:$src2),
+                 "packsswb {$src2, $dst|$dst, $src2}",
+                 [(set VR128:$dst, (v16i8 (int_x86_sse2_packsswb_128
+                                           (v8i16 VR128:$src1),
+                                           (loadv8i16 addr:$src2))))]>;
+def PACKSSDWrr : PDI<0x6B, MRMSrcReg, (ops VR128:$dst, VR128:$src1,
+                                       VR128:$src2),
+                 "packsswb {$src2, $dst|$dst, $src2}",
+                 [(set VR128:$dst, (v8i16 (int_x86_sse2_packssdw_128
+                                           (v4i32 VR128:$src1),
+                                           (v4i32 VR128:$src2))))]>;
+def PACKSSDWrm : PDI<0x6B, MRMSrcReg, (ops VR128:$dst, VR128:$src1,
+                                       i128mem:$src2),
+                 "packsswb {$src2, $dst|$dst, $src2}",
+                 [(set VR128:$dst, (v8i16 (int_x86_sse2_packssdw_128
+                                           (v4i32 VR128:$src1),
+                                           (loadv4i32 addr:$src2))))]>;
+def PACKUSWBrr : PDI<0x67, MRMSrcReg, (ops VR128:$dst, VR128:$src1,
+                                       VR128:$src2),
+                     "packuswb {$src2, $dst|$dst, $src2}",
+                 [(set VR128:$dst, (v16i8 (int_x86_sse2_packuswb_128
+                                           (v8i16 VR128:$src1),
+                                           (v8i16 VR128:$src2))))]>;
+def PACKUSWBrm : PDI<0x67, MRMSrcReg, (ops VR128:$dst, VR128:$src1,
+                                       i128mem:$src2),
+                     "packuswb {$src2, $dst|$dst, $src2}",
+                 [(set VR128:$dst, (v16i8 (int_x86_sse2_packuswb_128
+                                           (v8i16 VR128:$src1),
+                                           (loadv8i16 addr:$src2))))]>;
+}
+
+// Shuffle and unpack instructions
+def PSHUFWrr : PSIi8<0x70, MRMDestReg,
+                     (ops VR64:$dst, VR64:$src1, i8imm:$src2),
+                     "pshufw {$src2, $src1, $dst|$dst, $src1, $src2}", []>;
+def PSHUFWrm : PSIi8<0x70, MRMSrcMem,
+                     (ops VR64:$dst, i64mem:$src1, i8imm:$src2),
+                     "pshufw {$src2, $src1, $dst|$dst, $src1, $src2}", []>;
+
+def PSHUFDrr : PDIi8<0x70, MRMDestReg,
+                     (ops VR128:$dst, VR128:$src1, i8imm:$src2),
+                     "pshufd {$src2, $src1, $dst|$dst, $src1, $src2}",
+                     [(set VR128:$dst, (v4i32 (vector_shuffle
+                                               VR128:$src1, (undef),
+                                               PSHUFD_shuffle_mask:$src2)))]>;
+def PSHUFDrm : PDIi8<0x70, MRMSrcMem,
+                     (ops VR128:$dst, i128mem:$src1, i8imm:$src2),
+                     "pshufd {$src2, $src1, $dst|$dst, $src1, $src2}",
+                     [(set VR128:$dst, (v4i32 (vector_shuffle
+                                               (load addr:$src1), (undef),
+                                               PSHUFD_shuffle_mask:$src2)))]>;
+
+// SSE2 with ImmT == Imm8 and XS prefix.
+def PSHUFHWrr : Ii8<0x70, MRMDestReg,
+                    (ops VR128:$dst, VR128:$src1, i8imm:$src2),
+                    "pshufhw {$src2, $src1, $dst|$dst, $src1, $src2}",
+                    [(set VR128:$dst, (v8i16 (vector_shuffle
+                                              VR128:$src1, (undef),
+                                              PSHUFHW_shuffle_mask:$src2)))]>,
+                XS, Requires<[HasSSE2]>;
+def PSHUFHWrm : Ii8<0x70, MRMDestMem,
+                    (ops VR128:$dst, i128mem:$src1, i8imm:$src2),
+                    "pshufhw {$src2, $src1, $dst|$dst, $src1, $src2}",
+                    [(set VR128:$dst, (v8i16 (vector_shuffle
+                                     (bc_v8i16 (loadv2i64 addr:$src1)), (undef),
+                                              PSHUFHW_shuffle_mask:$src2)))]>,
+                XS, Requires<[HasSSE2]>;
+
+// SSE2 with ImmT == Imm8 and XD prefix.
+def PSHUFLWrr : Ii8<0x70, MRMDestReg,
+                    (ops VR128:$dst, VR128:$src1, i32i8imm:$src2),
+                    "pshufLw {$src2, $src1, $dst|$dst, $src1, $src2}",
+                    [(set VR128:$dst, (v8i16 (vector_shuffle
+                                              VR128:$src1, (undef),
+                                              PSHUFLW_shuffle_mask:$src2)))]>,
+                XD, Requires<[HasSSE2]>;
+def PSHUFLWrm : Ii8<0x70, MRMDestMem,
+                    (ops VR128:$dst, i128mem:$src1, i32i8imm:$src2),
+                    "pshufLw {$src2, $src1, $dst|$dst, $src1, $src2}",
+                    [(set VR128:$dst, (v8i16 (vector_shuffle
+                                     (bc_v8i16 (loadv2i64 addr:$src1)), (undef),
+                                              PSHUFLW_shuffle_mask:$src2)))]>,
+                XD, Requires<[HasSSE2]>;
+
+let isTwoAddress = 1 in {
 def PUNPCKLBWrr : PDI<0x60, MRMSrcReg, 
                       (ops VR128:$dst, VR128:$src1, VR128:$src2),
                       "punpcklbw {$src2, $dst|$dst, $src2}",
@@ -1355,6 +1507,29 @@
 // bit_convert
 def : Pat<(v2i64 (bitconvert (v4i32 VR128:$src))), (v2i64 VR128:$src)>,
       Requires<[HasSSE2]>;
+def : Pat<(v2i64 (bitconvert (v8i16 VR128:$src))), (v2i64 VR128:$src)>,
+      Requires<[HasSSE2]>;
+def : Pat<(v2i64 (bitconvert (v16i8 VR128:$src))), (v2i64 VR128:$src)>,
+      Requires<[HasSSE2]>;
+def : Pat<(v4i32 (bitconvert (v2i64 VR128:$src))), (v4i32 VR128:$src)>,
+      Requires<[HasSSE2]>;
+def : Pat<(v4i32 (bitconvert (v8i16 VR128:$src))), (v4i32 VR128:$src)>,
+      Requires<[HasSSE2]>;
+def : Pat<(v4i32 (bitconvert (v16i8 VR128:$src))), (v4i32 VR128:$src)>,
+      Requires<[HasSSE2]>;
+def : Pat<(v8i16 (bitconvert (v2i64 VR128:$src))), (v4i32 VR128:$src)>,
+      Requires<[HasSSE2]>;
+def : Pat<(v8i16 (bitconvert (v4i32 VR128:$src))), (v4i32 VR128:$src)>,
+      Requires<[HasSSE2]>;
+def : Pat<(v8i16 (bitconvert (v16i8 VR128:$src))), (v4i32 VR128:$src)>,
+      Requires<[HasSSE2]>;
+def : Pat<(v16i8 (bitconvert (v2i64 VR128:$src))), (v4i32 VR128:$src)>,
+      Requires<[HasSSE2]>;
+def : Pat<(v16i8 (bitconvert (v4i32 VR128:$src))), (v4i32 VR128:$src)>,
+      Requires<[HasSSE2]>;
+def : Pat<(v16i8 (bitconvert (v8i16 VR128:$src))), (v4i32 VR128:$src)>,
+      Requires<[HasSSE2]>;
+
 def : Pat<(v4i32 (bitconvert (v4f32 VR128:$src))), (v4i32 VR128:$src)>,
       Requires<[HasSSE2]>;
 def : Pat<(v4f32 (bitconvert (v4i32 VR128:$src))), (v4f32 VR128:$src)>,





From evan.cheng at apple.com  Wed Mar 29 17:09:31 2006
From: evan.cheng at apple.com (Evan Cheng)
Date: Wed, 29 Mar 2006 17:09:31 -0600
Subject: [llvm-commits] CVS: llvm/include/llvm/IntrinsicsX86.td 
Message-ID: <200603292309.RAA17919@zion.cs.uiuc.edu>



Changes in directory llvm/include/llvm:

IntrinsicsX86.td updated: 1.3 -> 1.4
---
Log message:

Add SSE2 integer pack with saturation intrinsics.


---
Diffs of the changes:  (+10 -0)

 IntrinsicsX86.td |   10 ++++++++++
 1 files changed, 10 insertions(+)


Index: llvm/include/llvm/IntrinsicsX86.td
diff -u llvm/include/llvm/IntrinsicsX86.td:1.3 llvm/include/llvm/IntrinsicsX86.td:1.4
--- llvm/include/llvm/IntrinsicsX86.td:1.3	Wed Mar 29 00:07:16 2006
+++ llvm/include/llvm/IntrinsicsX86.td	Wed Mar 29 17:09:19 2006
@@ -285,7 +285,17 @@
                          llvm_v2f64_ty], [InstrNoMem]>;
 }
 
+// Misc.
 let TargetPrefix = "x86" in {  // All intrinsics start with "llvm.x86.".
+  def int_x86_sse2_packsswb_128 : GCCBuiltin<"__builtin_ia32_packsswb128">,
+              Intrinsic<[llvm_v16i8_ty, llvm_v8i16_ty,
+                         llvm_v8i16_ty], [InstrNoMem]>;
+  def int_x86_sse2_packssdw_128 : GCCBuiltin<"__builtin_ia32_packssdw128">,
+              Intrinsic<[llvm_v8i16_ty, llvm_v4i32_ty,
+                         llvm_v4i32_ty], [InstrNoMem]>;
+  def int_x86_sse2_packuswb_128 : GCCBuiltin<"__builtin_ia32_packuswb128">,
+              Intrinsic<[llvm_v16i8_ty, llvm_v8i16_ty,
+                         llvm_v8i16_ty], [InstrNoMem]>;
   def int_x86_sse2_movmskpd : GCCBuiltin<"__builtin_ia32_movmskpd">,
               Intrinsic<[llvm_int_ty, llvm_v2f64_ty], [InstrNoMem]>;
 }





From evan.cheng at apple.com  Wed Mar 29 17:53:00 2006
From: evan.cheng at apple.com (Evan Cheng)
Date: Wed, 29 Mar 2006 17:53:00 -0600
Subject: [llvm-commits] CVS: llvm/lib/Target/X86/X86InstrSSE.td 
Message-ID: <200603292353.RAA18073@zion.cs.uiuc.edu>



Changes in directory llvm/lib/Target/X86:

X86InstrSSE.td updated: 1.45 -> 1.46
---
Log message:

Change SSE pack operation definitions to fit what the intrinsics expected.
For example, packsswb actually creates a v16i8 from a pair of v8i16. But since
the intrinsic specification forces the output type to match the operands.


---
Diffs of the changes:  (+20 -20)

 X86InstrSSE.td |   40 ++++++++++++++++++++--------------------
 1 files changed, 20 insertions(+), 20 deletions(-)


Index: llvm/lib/Target/X86/X86InstrSSE.td
diff -u llvm/lib/Target/X86/X86InstrSSE.td:1.45 llvm/lib/Target/X86/X86InstrSSE.td:1.46
--- llvm/lib/Target/X86/X86InstrSSE.td:1.45	Wed Mar 29 17:07:14 2006
+++ llvm/lib/Target/X86/X86InstrSSE.td	Wed Mar 29 17:52:48 2006
@@ -1182,39 +1182,39 @@
 def PACKSSWBrr : PDI<0x63, MRMSrcReg, (ops VR128:$dst, VR128:$src1,
                                        VR128:$src2),
                  "packsswb {$src2, $dst|$dst, $src2}",
-                 [(set VR128:$dst, (v16i8 (int_x86_sse2_packsswb_128
-                                           (v8i16 VR128:$src1),
-                                           (v8i16 VR128:$src2))))]>;
+                 [(set VR128:$dst, (v8i16 (int_x86_sse2_packsswb_128
+                                           VR128:$src1,
+                                           VR128:$src2)))]>;
 def PACKSSWBrm : PDI<0x63, MRMSrcMem, (ops VR128:$dst, VR128:$src1,
                                        i128mem:$src2),
                  "packsswb {$src2, $dst|$dst, $src2}",
-                 [(set VR128:$dst, (v16i8 (int_x86_sse2_packsswb_128
-                                           (v8i16 VR128:$src1),
-                                           (loadv8i16 addr:$src2))))]>;
+                 [(set VR128:$dst, (v8i16 (int_x86_sse2_packsswb_128
+                                           VR128:$src1,
+                                         (bc_v8i16 (loadv2f64 addr:$src2)))))]>;
 def PACKSSDWrr : PDI<0x6B, MRMSrcReg, (ops VR128:$dst, VR128:$src1,
                                        VR128:$src2),
-                 "packsswb {$src2, $dst|$dst, $src2}",
-                 [(set VR128:$dst, (v8i16 (int_x86_sse2_packssdw_128
-                                           (v4i32 VR128:$src1),
-                                           (v4i32 VR128:$src2))))]>;
+                 "packssdw {$src2, $dst|$dst, $src2}",
+                 [(set VR128:$dst, (v4i32 (int_x86_sse2_packssdw_128
+                                           VR128:$src1,
+                                           VR128:$src2)))]>;
 def PACKSSDWrm : PDI<0x6B, MRMSrcReg, (ops VR128:$dst, VR128:$src1,
                                        i128mem:$src2),
-                 "packsswb {$src2, $dst|$dst, $src2}",
-                 [(set VR128:$dst, (v8i16 (int_x86_sse2_packssdw_128
-                                           (v4i32 VR128:$src1),
-                                           (loadv4i32 addr:$src2))))]>;
+                 "packssdw {$src2, $dst|$dst, $src2}",
+                 [(set VR128:$dst, (v4i32 (int_x86_sse2_packssdw_128
+                                           VR128:$src1,
+                                         (bc_v4i32 (loadv2i64 addr:$src2)))))]>;
 def PACKUSWBrr : PDI<0x67, MRMSrcReg, (ops VR128:$dst, VR128:$src1,
                                        VR128:$src2),
                      "packuswb {$src2, $dst|$dst, $src2}",
-                 [(set VR128:$dst, (v16i8 (int_x86_sse2_packuswb_128
-                                           (v8i16 VR128:$src1),
-                                           (v8i16 VR128:$src2))))]>;
+                 [(set VR128:$dst, (v8i16 (int_x86_sse2_packuswb_128
+                                           VR128:$src1,
+                                           VR128:$src2)))]>;
 def PACKUSWBrm : PDI<0x67, MRMSrcReg, (ops VR128:$dst, VR128:$src1,
                                        i128mem:$src2),
                      "packuswb {$src2, $dst|$dst, $src2}",
-                 [(set VR128:$dst, (v16i8 (int_x86_sse2_packuswb_128
-                                           (v8i16 VR128:$src1),
-                                           (loadv8i16 addr:$src2))))]>;
+                 [(set VR128:$dst, (v8i16 (int_x86_sse2_packuswb_128
+                                           VR128:$src1,
+                                         (bc_v8i16 (loadv2i64 addr:$src2)))))]>;
 }
 
 // Shuffle and unpack instructions





From evan.cheng at apple.com  Wed Mar 29 17:53:26 2006
From: evan.cheng at apple.com (Evan Cheng)
Date: Wed, 29 Mar 2006 17:53:26 -0600
Subject: [llvm-commits] CVS: llvm/include/llvm/IntrinsicsX86.td 
Message-ID: <200603292353.RAA18088@zion.cs.uiuc.edu>



Changes in directory llvm/include/llvm:

IntrinsicsX86.td updated: 1.4 -> 1.5
---
Log message:

Change SSE pack operation definitions to fit what the intrinsics expected.
For example, packsswb actually creates a v16i8 from a pair of v8i16. But since
the intrinsic specification forces the output type to match the operands.


---
Diffs of the changes:  (+3 -3)

 IntrinsicsX86.td |    6 +++---
 1 files changed, 3 insertions(+), 3 deletions(-)


Index: llvm/include/llvm/IntrinsicsX86.td
diff -u llvm/include/llvm/IntrinsicsX86.td:1.4 llvm/include/llvm/IntrinsicsX86.td:1.5
--- llvm/include/llvm/IntrinsicsX86.td:1.4	Wed Mar 29 17:09:19 2006
+++ llvm/include/llvm/IntrinsicsX86.td	Wed Mar 29 17:53:14 2006
@@ -288,13 +288,13 @@
 // Misc.
 let TargetPrefix = "x86" in {  // All intrinsics start with "llvm.x86.".
   def int_x86_sse2_packsswb_128 : GCCBuiltin<"__builtin_ia32_packsswb128">,
-              Intrinsic<[llvm_v16i8_ty, llvm_v8i16_ty,
+              Intrinsic<[llvm_v8i16_ty, llvm_v8i16_ty,
                          llvm_v8i16_ty], [InstrNoMem]>;
   def int_x86_sse2_packssdw_128 : GCCBuiltin<"__builtin_ia32_packssdw128">,
-              Intrinsic<[llvm_v8i16_ty, llvm_v4i32_ty,
+              Intrinsic<[llvm_v4i32_ty, llvm_v4i32_ty,
                          llvm_v4i32_ty], [InstrNoMem]>;
   def int_x86_sse2_packuswb_128 : GCCBuiltin<"__builtin_ia32_packuswb128">,
-              Intrinsic<[llvm_v16i8_ty, llvm_v8i16_ty,
+              Intrinsic<[llvm_v8i16_ty, llvm_v8i16_ty,
                          llvm_v8i16_ty], [InstrNoMem]>;
   def int_x86_sse2_movmskpd : GCCBuiltin<"__builtin_ia32_movmskpd">,
               Intrinsic<[llvm_int_ty, llvm_v2f64_ty], [InstrNoMem]>;





From evan.cheng at apple.com  Wed Mar 29 18:33:37 2006
From: evan.cheng at apple.com (Evan Cheng)
Date: Wed, 29 Mar 2006 18:33:37 -0600
Subject: [llvm-commits] CVS: llvm/lib/Target/X86/X86InstrSSE.td 
Message-ID: <200603300033.SAA18236@zion.cs.uiuc.edu>



Changes in directory llvm/lib/Target/X86:

X86InstrSSE.td updated: 1.46 -> 1.47
---
Log message:

Add 128-bit pmovmskb intrinsic support.


---
Diffs of the changes:  (+12 -7)

 X86InstrSSE.td |   19 ++++++++++++-------
 1 files changed, 12 insertions(+), 7 deletions(-)


Index: llvm/lib/Target/X86/X86InstrSSE.td
diff -u llvm/lib/Target/X86/X86InstrSSE.td:1.46 llvm/lib/Target/X86/X86InstrSSE.td:1.47
--- llvm/lib/Target/X86/X86InstrSSE.td:1.46	Wed Mar 29 17:52:48 2006
+++ llvm/lib/Target/X86/X86InstrSSE.td	Wed Mar 29 18:33:26 2006
@@ -686,13 +686,6 @@
                               MOVHLPS_shuffle_mask)))]>;
 }
 
-def MOVMSKPSrr : PSI<0x50, MRMSrcReg, (ops R32:$dst, VR128:$src),
-                     "movmskps {$src, $dst|$dst, $src}",
-                     [(set R32:$dst, (int_x86_sse_movmsk_ps VR128:$src))]>;
-def MOVMSKPDrr : PSI<0x50, MRMSrcReg, (ops R32:$dst, VR128:$src),
-                     "movmskpd {$src, $dst|$dst, $src}",
-                     [(set R32:$dst, (int_x86_sse2_movmskpd VR128:$src))]>;
-
 // Conversion instructions
 def CVTPI2PSrr : PSI<0x2A, MRMSrcReg, (ops VR128:$dst, VR64:$src),
                      "cvtpi2ps {$src, $dst|$dst, $src}", []>;
@@ -1374,6 +1367,18 @@
 // Miscellaneous Instructions
 //===----------------------------------------------------------------------===//
 
+// Mask creation
+def MOVMSKPSrr : PSI<0x50, MRMSrcReg, (ops R32:$dst, VR128:$src),
+                     "movmskps {$src, $dst|$dst, $src}",
+                     [(set R32:$dst, (int_x86_sse_movmsk_ps VR128:$src))]>;
+def MOVMSKPDrr : PSI<0x50, MRMSrcReg, (ops R32:$dst, VR128:$src),
+                     "movmskpd {$src, $dst|$dst, $src}",
+                     [(set R32:$dst, (int_x86_sse2_movmskpd VR128:$src))]>;
+
+def PMOVMSKBrr : PDI<0xD7, MRMSrcReg, (ops R32:$dst, VR128:$src),
+                     "pmovmskb {$src, $dst|$dst, $src}",
+                     [(set R32:$dst, (int_x86_sse2_pmovmskb_128 VR128:$src))]>;
+
 // Prefetching loads
 def PREFETCHT0   : I<0x18, MRM1m, (ops i8mem:$src),
                      "prefetcht0 $src", []>, TB,





From evan.cheng at apple.com  Wed Mar 29 18:33:38 2006
From: evan.cheng at apple.com (Evan Cheng)
Date: Wed, 29 Mar 2006 18:33:38 -0600
Subject: [llvm-commits] CVS: llvm/include/llvm/IntrinsicsX86.td 
Message-ID: <200603300033.SAA18240@zion.cs.uiuc.edu>



Changes in directory llvm/include/llvm:

IntrinsicsX86.td updated: 1.5 -> 1.6
---
Log message:

Add 128-bit pmovmskb intrinsic support.


---
Diffs of the changes:  (+2 -0)

 IntrinsicsX86.td |    2 ++
 1 files changed, 2 insertions(+)


Index: llvm/include/llvm/IntrinsicsX86.td
diff -u llvm/include/llvm/IntrinsicsX86.td:1.5 llvm/include/llvm/IntrinsicsX86.td:1.6
--- llvm/include/llvm/IntrinsicsX86.td:1.5	Wed Mar 29 17:53:14 2006
+++ llvm/include/llvm/IntrinsicsX86.td	Wed Mar 29 18:33:25 2006
@@ -298,4 +298,6 @@
                          llvm_v8i16_ty], [InstrNoMem]>;
   def int_x86_sse2_movmskpd : GCCBuiltin<"__builtin_ia32_movmskpd">,
               Intrinsic<[llvm_int_ty, llvm_v2f64_ty], [InstrNoMem]>;
+  def int_x86_sse2_pmovmskb_128 : GCCBuiltin<"__builtin_ia32_pmovmskb128">,
+              Intrinsic<[llvm_int_ty, llvm_v16i8_ty], [InstrNoMem]>;
 }





From evan.cheng at apple.com  Thu Mar 30 00:21:34 2006
From: evan.cheng at apple.com (Evan Cheng)
Date: Thu, 30 Mar 2006 00:21:34 -0600
Subject: [llvm-commits] CVS: llvm/lib/Target/X86/X86InstrSSE.td 
Message-ID: <200603300621.AAA20097@zion.cs.uiuc.edu>



Changes in directory llvm/lib/Target/X86:

X86InstrSSE.td updated: 1.47 -> 1.48
---
Log message:

Add support for _mm_cmp{cc}_ss and _mm_cmp{cc}_ps intrinsics

---
Diffs of the changes:  (+35 -9)

 X86InstrSSE.td |   44 +++++++++++++++++++++++++++++++++++---------
 1 files changed, 35 insertions(+), 9 deletions(-)


Index: llvm/lib/Target/X86/X86InstrSSE.td
diff -u llvm/lib/Target/X86/X86InstrSSE.td:1.47 llvm/lib/Target/X86/X86InstrSSE.td:1.48
--- llvm/lib/Target/X86/X86InstrSSE.td:1.47	Wed Mar 29 18:33:26 2006
+++ llvm/lib/Target/X86/X86InstrSSE.td	Thu Mar 30 00:21:22 2006
@@ -501,7 +501,8 @@
 let isTwoAddress = 1 in {
 def CMPSSrr : SSI<0xC2, MRMSrcReg, 
                 (ops FR32:$dst, FR32:$src1, FR32:$src, SSECC:$cc),
-                "cmp${cc}ss {$src, $dst|$dst, $src}", []>;
+                "cmp${cc}ss {$src, $dst|$dst, $src}",
+                 []>;
 def CMPSSrm : SSI<0xC2, MRMSrcMem, 
                 (ops FR32:$dst, FR32:$src1, f32mem:$src, SSECC:$cc),
                 "cmp${cc}ss {$src, $dst|$dst, $src}", []>;
@@ -526,6 +527,27 @@
                  "ucomisd {$src2, $src1|$src1, $src2}",
                  [(X86cmp FR64:$src1, (loadf64 addr:$src2))]>;
 
+// Aliases to match intrinsics which expect XMM operand(s).
+let isTwoAddress = 1 in {
+def Int_CMPSSrr : SSI<0xC2, MRMSrcReg, 
+                      (ops VR128:$dst, VR128:$src1, VR128:$src, SSECC:$cc),
+                      "cmp${cc}ss {$src, $dst|$dst, $src}",
+                      [(set VR128:$dst, (int_x86_sse_cmp_ss VR128:$src1,
+                                         VR128:$src, imm:$cc))]>;
+def Int_CMPSSrm : SSI<0xC2, MRMSrcMem, 
+                      (ops VR128:$dst, VR128:$src1, f32mem:$src, SSECC:$cc),
+                      "cmp${cc}ss {$src, $dst|$dst, $src}",
+                      [(set VR128:$dst, (int_x86_sse_cmp_ss VR128:$src1,
+                                         (load addr:$src), imm:$cc))]>;
+def Int_CMPSDrr : SDI<0xC2, MRMSrcReg, 
+                      (ops VR128:$dst, VR128:$src1, VR128:$src, SSECC:$cc),
+                      "cmp${cc}sd {$src, $dst|$dst, $src}", []>;
+def Int_CMPSDrm : SDI<0xC2, MRMSrcMem, 
+                      (ops VR128:$dst, VR128:$src1, f64mem:$src, SSECC:$cc),
+                      "cmp${cc}sd {$src, $dst|$dst, $src}", []>;
+}
+
+
 // Aliases of packed instructions for scalar use. These all have names that
 // start with 'Fs'.
 
@@ -936,17 +958,21 @@
 
 let isTwoAddress = 1 in {
 def CMPPSrr : PSI<0xC2, MRMSrcReg, 
-                (ops VR128:$dst, VR128:$src1, VR128:$src, SSECC:$cc),
-                "cmp${cc}ps {$src, $dst|$dst, $src}", []>;
+                  (ops VR128:$dst, VR128:$src1, VR128:$src, SSECC:$cc),
+                  "cmp${cc}ps {$src, $dst|$dst, $src}",
+                  [(set VR128:$dst, (int_x86_sse_cmp_ps VR128:$src1,
+                                     VR128:$src, imm:$cc))]>;
 def CMPPSrm : PSI<0xC2, MRMSrcMem, 
-                (ops VR128:$dst, VR128:$src1, f128mem:$src, SSECC:$cc),
-                "cmp${cc}ps {$src, $dst|$dst, $src}", []>;
+                  (ops VR128:$dst, VR128:$src1, f128mem:$src, SSECC:$cc),
+                  "cmp${cc}ps {$src, $dst|$dst, $src}",
+                  [(set VR128:$dst, (int_x86_sse_cmp_ps VR128:$src1,
+                                     (load addr:$src), imm:$cc))]>;
 def CMPPDrr : PDI<0xC2, MRMSrcReg, 
-                (ops VR128:$dst, VR128:$src1, VR128:$src, SSECC:$cc),
-                "cmp${cc}pd {$src, $dst|$dst, $src}", []>;
+                  (ops VR128:$dst, VR128:$src1, VR128:$src, SSECC:$cc),
+                  "cmp${cc}pd {$src, $dst|$dst, $src}", []>;
 def CMPPDrm : PDI<0xC2, MRMSrcMem, 
-                (ops VR128:$dst, VR128:$src1, f128mem:$src, SSECC:$cc),
-                "cmp${cc}pd {$src, $dst|$dst, $src}", []>;
+                  (ops VR128:$dst, VR128:$src1, f128mem:$src, SSECC:$cc),
+                  "cmp${cc}pd {$src, $dst|$dst, $src}", []>;
 }
 
 // Shuffle and unpack instructions





From evan.cheng at apple.com  Thu Mar 30 00:21:34 2006
From: evan.cheng at apple.com (Evan Cheng)
Date: Thu, 30 Mar 2006 00:21:34 -0600
Subject: [llvm-commits] CVS: llvm/include/llvm/IntrinsicsX86.td 
Message-ID: <200603300621.AAA20101@zion.cs.uiuc.edu>



Changes in directory llvm/include/llvm:

IntrinsicsX86.td updated: 1.6 -> 1.7
---
Log message:

Add support for _mm_cmp{cc}_ss and _mm_cmp{cc}_ps intrinsics

---
Diffs of the changes:  (+4 -106)

 IntrinsicsX86.td |  110 ++-----------------------------------------------------
 1 files changed, 4 insertions(+), 106 deletions(-)


Index: llvm/include/llvm/IntrinsicsX86.td
diff -u llvm/include/llvm/IntrinsicsX86.td:1.6 llvm/include/llvm/IntrinsicsX86.td:1.7
--- llvm/include/llvm/IntrinsicsX86.td:1.6	Wed Mar 29 18:33:25 2006
+++ llvm/include/llvm/IntrinsicsX86.td	Thu Mar 30 00:21:22 2006
@@ -63,114 +63,12 @@
 
 // Comparison ops
 let TargetPrefix = "x86" in {  // All intrinsics start with "llvm.x86.".
-  def int_x86_sse_cmpeq_ss : GCCBuiltin<"__builtin_ia32_cmpeqss">,
+  def int_x86_sse_cmp_ss :
               Intrinsic<[llvm_v4f32_ty, llvm_v4f32_ty,
-                         llvm_v4f32_ty], [InstrNoMem]>;
-  def int_x86_sse_cmpeq_ps : GCCBuiltin<"__builtin_ia32_cmpeqps">,
+                         llvm_v4f32_ty, llvm_sbyte_ty], [InstrNoMem]>;
+  def int_x86_sse_cmp_ps :
               Intrinsic<[llvm_v4f32_ty, llvm_v4f32_ty,
-                         llvm_v4f32_ty], [InstrNoMem]>;
-  def int_x86_sse_cmplt_ss : GCCBuiltin<"__builtin_ia32_cmpltss">,
-              Intrinsic<[llvm_v4f32_ty, llvm_v4f32_ty,
-                         llvm_v4f32_ty], [InstrNoMem]>;
-  def int_x86_sse_cmplt_ps : GCCBuiltin<"__builtin_ia32_cmpltps">,
-              Intrinsic<[llvm_v4f32_ty, llvm_v4f32_ty,
-                         llvm_v4f32_ty], [InstrNoMem]>;
-  def int_x86_sse_cmple_ss : GCCBuiltin<"__builtin_ia32_cmpless">,
-              Intrinsic<[llvm_v4f32_ty, llvm_v4f32_ty,
-                         llvm_v4f32_ty], [InstrNoMem]>;
-  def int_x86_sse_cmple_ps : GCCBuiltin<"__builtin_ia32_cmpleps">,
-              Intrinsic<[llvm_v4f32_ty, llvm_v4f32_ty,
-                         llvm_v4f32_ty], [InstrNoMem]>;
-  def int_x86_sse_cmpgt_ss : GCCBuiltin<"__builtin_ia32_cmpgtss">,
-              Intrinsic<[llvm_v4f32_ty, llvm_v4f32_ty,
-                         llvm_v4f32_ty], [InstrNoMem]>;
-  def int_x86_sse_cmpgt_ps : GCCBuiltin<"__builtin_ia32_cmpgtps">,
-              Intrinsic<[llvm_v4f32_ty, llvm_v4f32_ty,
-                         llvm_v4f32_ty], [InstrNoMem]>;
-  def int_x86_sse_cmpge_ss : GCCBuiltin<"__builtin_ia32_cmpgess">,
-              Intrinsic<[llvm_v4f32_ty, llvm_v4f32_ty,
-                         llvm_v4f32_ty], [InstrNoMem]>;
-  def int_x86_sse_cmpge_ps : GCCBuiltin<"__builtin_ia32_cmpgeps">,
-              Intrinsic<[llvm_v4f32_ty, llvm_v4f32_ty,
-                         llvm_v4f32_ty], [InstrNoMem]>;
-  def int_x86_sse_cmpneq_ss : GCCBuiltin<"__builtin_ia32_cmpneqss">,
-              Intrinsic<[llvm_v4f32_ty, llvm_v4f32_ty,
-                         llvm_v4f32_ty], [InstrNoMem]>;
-  def int_x86_sse_cmpneq_ps : GCCBuiltin<"__builtin_ia32_cmpneqps">,
-              Intrinsic<[llvm_v4f32_ty, llvm_v4f32_ty,
-                         llvm_v4f32_ty], [InstrNoMem]>;
-  def int_x86_sse_cmpnlt_ss : GCCBuiltin<"__builtin_ia32_cmpnltss">,
-              Intrinsic<[llvm_v4f32_ty, llvm_v4f32_ty,
-                         llvm_v4f32_ty], [InstrNoMem]>;
-  def int_x86_sse_cmpnlt_ps : GCCBuiltin<"__builtin_ia32_cmpnltps">,
-              Intrinsic<[llvm_v4f32_ty, llvm_v4f32_ty,
-                         llvm_v4f32_ty], [InstrNoMem]>;
-  def int_x86_sse_cmpnle_ss : GCCBuiltin<"__builtin_ia32_cmpnless">,
-              Intrinsic<[llvm_v4f32_ty, llvm_v4f32_ty,
-                         llvm_v4f32_ty], [InstrNoMem]>;
-  def int_x86_sse_cmpnle_ps : GCCBuiltin<"__builtin_ia32_cmpnleps">,
-              Intrinsic<[llvm_v4f32_ty, llvm_v4f32_ty,
-                         llvm_v4f32_ty], [InstrNoMem]>;
-  def int_x86_sse_cmpngt_ss : GCCBuiltin<"__builtin_ia32_cmpngtss">,
-              Intrinsic<[llvm_v4f32_ty, llvm_v4f32_ty,
-                         llvm_v4f32_ty], [InstrNoMem]>;
-  def int_x86_sse_cmpngt_ps : GCCBuiltin<"__builtin_ia32_cmpngtps">,
-              Intrinsic<[llvm_v4f32_ty, llvm_v4f32_ty,
-                         llvm_v4f32_ty], [InstrNoMem]>;
-  def int_x86_sse_cmpnge_ss : GCCBuiltin<"__builtin_ia32_cmpngess">,
-              Intrinsic<[llvm_v4f32_ty, llvm_v4f32_ty,
-                         llvm_v4f32_ty], [InstrNoMem]>;
-  def int_x86_sse_cmpnge_ps : GCCBuiltin<"__builtin_ia32_cmpngeps">,
-              Intrinsic<[llvm_v4f32_ty, llvm_v4f32_ty,
-                         llvm_v4f32_ty], [InstrNoMem]>;
-  def int_x86_sse_cmpord_ss : GCCBuiltin<"__builtin_ia32_cmpordss">,
-              Intrinsic<[llvm_v4f32_ty, llvm_v4f32_ty,
-                         llvm_v4f32_ty], [InstrNoMem]>;
-  def int_x86_sse_cmpord_ps : GCCBuiltin<"__builtin_ia32_cmpordps">,
-              Intrinsic<[llvm_v4f32_ty, llvm_v4f32_ty,
-                         llvm_v4f32_ty], [InstrNoMem]>;
-  def int_x86_sse_cmpunord_ss : GCCBuiltin<"__builtin_ia32_cmpunordss">,
-              Intrinsic<[llvm_v4f32_ty, llvm_v4f32_ty,
-                         llvm_v4f32_ty], [InstrNoMem]>;
-  def int_x86_sse_cmpunord_ps : GCCBuiltin<"__builtin_ia32_cmpunordps">,
-              Intrinsic<[llvm_v4f32_ty, llvm_v4f32_ty,
-                         llvm_v4f32_ty], [InstrNoMem]>;
-  def int_x86_sse_comieq_ss : GCCBuiltin<"__builtin_ia32_comieq">,
-              Intrinsic<[llvm_int_ty, llvm_v4f32_ty,
-                         llvm_v4f32_ty], [InstrNoMem]>;
-  def int_x86_sse_comilt_ss : GCCBuiltin<"__builtin_ia32_comilt">,
-              Intrinsic<[llvm_int_ty, llvm_v4f32_ty,
-                         llvm_v4f32_ty], [InstrNoMem]>;
-  def int_x86_sse_comile_ss : GCCBuiltin<"__Builtin_ia32_comile">,
-              Intrinsic<[llvm_int_ty, llvm_v4f32_ty,
-                         llvm_v4f32_ty], [InstrNoMem]>;
-  def int_x86_sse_comigt_ss : GCCBuiltin<"__builtin_ia32_comigt">,
-              Intrinsic<[llvm_int_ty, llvm_v4f32_ty,
-                         llvm_v4f32_ty], [InstrNoMem]>;
-  def int_x86_sse_comige_ss : GCCBuiltin<"__builtin_ia32_comige">,
-              Intrinsic<[llvm_int_ty, llvm_v4f32_ty,
-                         llvm_v4f32_ty], [InstrNoMem]>;
-  def int_x86_sse_comineq_ss : GCCBuiltin<"__builtin_ia32_comineq">,
-              Intrinsic<[llvm_int_ty, llvm_v4f32_ty,
-                         llvm_v4f32_ty], [InstrNoMem]>;
-  def int_x86_sse_ucomieq_ss : GCCBuiltin<"__builtin_ia32_ucomieq">,
-              Intrinsic<[llvm_int_ty, llvm_v4f32_ty,
-                         llvm_v4f32_ty], [InstrNoMem]>;
-  def int_x86_sse_ucomilt_ss : GCCBuiltin<"__builtin_ia32_ucomilt">,
-              Intrinsic<[llvm_int_ty, llvm_v4f32_ty,
-                         llvm_v4f32_ty], [InstrNoMem]>;
-  def int_x86_sse_ucomile_ss : GCCBuiltin<"__Builtin_ia32_ucomile">,
-              Intrinsic<[llvm_int_ty, llvm_v4f32_ty,
-                         llvm_v4f32_ty], [InstrNoMem]>;
-  def int_x86_sse_ucomigt_ss : GCCBuiltin<"__builtin_ia32_ucomigt">,
-              Intrinsic<[llvm_int_ty, llvm_v4f32_ty,
-                         llvm_v4f32_ty], [InstrNoMem]>;
-  def int_x86_sse_ucomige_ss : GCCBuiltin<"__builtin_ia32_ucomige">,
-              Intrinsic<[llvm_int_ty, llvm_v4f32_ty,
-                         llvm_v4f32_ty], [InstrNoMem]>;
-  def int_x86_sse_ucomineq_ss : GCCBuiltin<"__builtin_ia32_ucomineq">,
-              Intrinsic<[llvm_int_ty, llvm_v4f32_ty,
-                         llvm_v4f32_ty], [InstrNoMem]>;
+                         llvm_v4f32_ty, llvm_sbyte_ty], [InstrNoMem]>;
 }
 
 





From evan.cheng at apple.com  Thu Mar 30 01:33:44 2006
From: evan.cheng at apple.com (Evan Cheng)
Date: Thu, 30 Mar 2006 01:33:44 -0600
Subject: [llvm-commits] CVS: llvm/lib/Target/X86/X86InstrSSE.td 
Message-ID: <200603300733.BAA20368@zion.cs.uiuc.edu>



Changes in directory llvm/lib/Target/X86:

X86InstrSSE.td updated: 1.48 -> 1.49
---
Log message:

More logical ops patterns

---
Diffs of the changes:  (+106 -0)

 X86InstrSSE.td |  106 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++
 1 files changed, 106 insertions(+)


Index: llvm/lib/Target/X86/X86InstrSSE.td
diff -u llvm/lib/Target/X86/X86InstrSSE.td:1.48 llvm/lib/Target/X86/X86InstrSSE.td:1.49
--- llvm/lib/Target/X86/X86InstrSSE.td:1.48	Thu Mar 30 00:21:22 2006
+++ llvm/lib/Target/X86/X86InstrSSE.td	Thu Mar 30 01:33:32 2006
@@ -45,6 +45,8 @@
 def loadv4i32    : PatFrag<(ops node:$ptr), (v4i32 (load node:$ptr))>;
 def loadv2i64    : PatFrag<(ops node:$ptr), (v2i64 (load node:$ptr))>;
 
+def bc_v4f32 : PatFrag<(ops node:$in), (v4f32 (bitconvert node:$in))>;
+def bc_v2f64 : PatFrag<(ops node:$in), (v2f64 (bitconvert node:$in))>;
 def bc_v16i8 : PatFrag<(ops node:$in), (v16i8 (bitconvert node:$in))>;
 def bc_v8i16 : PatFrag<(ops node:$in), (v8i16 (bitconvert node:$in))>;
 def bc_v4i32 : PatFrag<(ops node:$in), (v4i32 (bitconvert node:$in))>;
@@ -1600,3 +1602,107 @@
            SHUFP_shuffle_mask:$sm),
           (v4i32 (SHUFPSrm VR128:$src1, addr:$src2,
                   SHUFP_v4i32_shuffle_mask:$sm))>, Requires<[HasSSE2]>;
+
+// Logical ops
+def : Pat<(and (bc_v4i32 (v4f32 VR128:$src1)), (loadv4i32 addr:$src2)),
+          (ANDPSrm VR128:$src1, addr:$src2)>;
+def : Pat<(and (bc_v2i64 (v2f64 VR128:$src1)), (loadv2i64 addr:$src2)),
+          (ANDPDrm VR128:$src1, addr:$src2)>;
+def : Pat<(or  (bc_v4i32 (v4f32 VR128:$src1)), (loadv4i32 addr:$src2)),
+          (ORPSrm VR128:$src1, addr:$src2)>;
+def : Pat<(or  (bc_v2i64 (v2f64 VR128:$src1)), (loadv2i64 addr:$src2)),
+          (ORPDrm VR128:$src1, addr:$src2)>;
+def : Pat<(xor (bc_v4i32 (v4f32 VR128:$src1)), (loadv4i32 addr:$src2)),
+          (XORPSrm VR128:$src1, addr:$src2)>;
+def : Pat<(xor (bc_v2i64 (v2f64 VR128:$src1)), (loadv2i64 addr:$src2)),
+          (XORPDrm VR128:$src1, addr:$src2)>;
+def : Pat<(and (vnot (bc_v4i32 (v4f32 VR128:$src1))), (loadv4i32 addr:$src2)),
+          (ANDNPSrm VR128:$src1, addr:$src2)>;
+def : Pat<(and (vnot (bc_v2i64 (v2f64 VR128:$src1))), (loadv2i64 addr:$src2)),
+          (ANDNPDrm VR128:$src1, addr:$src2)>;
+
+def : Pat<(bc_v4f32 (v4i32 (and VR128:$src1, VR128:$src2))),
+          (ANDPSrr VR128:$src1, VR128:$src2)>;
+def : Pat<(bc_v4f32 (v4i32 (or VR128:$src1, VR128:$src2))),
+          (ORPSrr VR128:$src1, VR128:$src2)>;
+def : Pat<(bc_v4f32 (v4i32 (xor VR128:$src1, VR128:$src2))),
+          (XORPSrr VR128:$src1, VR128:$src2)>;
+def : Pat<(bc_v4f32 (v4i32 (and (vnot VR128:$src1), VR128:$src2))),
+          (ANDNPSrr VR128:$src1, VR128:$src2)>;
+
+def : Pat<(bc_v4f32 (v4i32 (and VR128:$src1, (load addr:$src2)))),
+          (ANDPSrm (v4i32 VR128:$src1), addr:$src2)>;
+def : Pat<(bc_v4f32 (v4i32 (or VR128:$src1, (load addr:$src2)))),
+          (ORPSrm VR128:$src1, addr:$src2)>;
+def : Pat<(bc_v4f32 (v4i32 (xor VR128:$src1, (load addr:$src2)))),
+          (XORPSrm VR128:$src1, addr:$src2)>;
+def : Pat<(bc_v4f32 (v4i32 (and (vnot VR128:$src1), (load addr:$src2)))),
+          (ANDNPSrm VR128:$src1, addr:$src2)>;
+
+def : Pat<(bc_v2f64 (v2i64 (and VR128:$src1, VR128:$src2))),
+          (ANDPDrr VR128:$src1, VR128:$src2)>;
+def : Pat<(bc_v2f64 (v2i64 (or VR128:$src1, VR128:$src2))),
+          (ORPDrr VR128:$src1, VR128:$src2)>;
+def : Pat<(bc_v2f64 (v2i64 (xor VR128:$src1, VR128:$src2))),
+          (XORPDrr VR128:$src1, VR128:$src2)>;
+def : Pat<(bc_v2f64 (v2i64 (and (vnot VR128:$src1), VR128:$src2))),
+          (ANDNPDrr VR128:$src1, VR128:$src2)>;
+
+def : Pat<(bc_v2f64 (v2i64 (and VR128:$src1, (load addr:$src2)))),
+          (ANDPSrm (v2i64 VR128:$src1), addr:$src2)>;
+def : Pat<(bc_v2f64 (v2i64 (or VR128:$src1, (load addr:$src2)))),
+          (ORPSrm VR128:$src1, addr:$src2)>;
+def : Pat<(bc_v2f64 (v2i64 (xor VR128:$src1, (load addr:$src2)))),
+          (XORPSrm VR128:$src1, addr:$src2)>;
+def : Pat<(bc_v2f64 (v2i64 (and (vnot VR128:$src1), (load addr:$src2)))),
+          (ANDNPSrm VR128:$src1, addr:$src2)>;
+
+def : Pat<(v4i32 (and VR128:$src1, VR128:$src2)),
+          (PANDrr VR128:$src1, VR128:$src2)>;
+def : Pat<(v8i16 (and VR128:$src1, VR128:$src2)),
+          (PANDrr VR128:$src1, VR128:$src2)>;
+def : Pat<(v16i8 (and VR128:$src1, VR128:$src2)),
+          (PANDrr VR128:$src1, VR128:$src2)>;
+def : Pat<(v4i32 (or VR128:$src1, VR128:$src2)),
+          (PORrr VR128:$src1, VR128:$src2)>;
+def : Pat<(v8i16 (or VR128:$src1, VR128:$src2)),
+          (PORrr VR128:$src1, VR128:$src2)>;
+def : Pat<(v16i8 (or VR128:$src1, VR128:$src2)),
+          (PORrr VR128:$src1, VR128:$src2)>;
+def : Pat<(v4i32 (xor VR128:$src1, VR128:$src2)),
+          (PXORrr VR128:$src1, VR128:$src2)>;
+def : Pat<(v8i16 (xor VR128:$src1, VR128:$src2)),
+          (PXORrr VR128:$src1, VR128:$src2)>;
+def : Pat<(v16i8 (xor VR128:$src1, VR128:$src2)),
+          (PXORrr VR128:$src1, VR128:$src2)>;
+def : Pat<(v4i32 (and (vnot VR128:$src1), VR128:$src2)),
+          (PANDNrr VR128:$src1, VR128:$src2)>;
+def : Pat<(v8i16 (and (vnot VR128:$src1), VR128:$src2)),
+          (PANDNrr VR128:$src1, VR128:$src2)>;
+def : Pat<(v16i8 (and (vnot VR128:$src1), VR128:$src2)),
+          (PANDNrr VR128:$src1, VR128:$src2)>;
+
+def : Pat<(v4i32 (and VR128:$src1, (load addr:$src2))),
+          (PANDrm VR128:$src1, addr:$src2)>;
+def : Pat<(v8i16 (and VR128:$src1, (load addr:$src2))),
+          (PANDrm VR128:$src1, addr:$src2)>;
+def : Pat<(v16i8 (and VR128:$src1, (load addr:$src2))),
+          (PANDrm VR128:$src1, addr:$src2)>;
+def : Pat<(v4i32 (or VR128:$src1, (load addr:$src2))),
+          (PORrm VR128:$src1, addr:$src2)>;
+def : Pat<(v8i16 (or VR128:$src1, (load addr:$src2))),
+          (PORrm VR128:$src1, addr:$src2)>;
+def : Pat<(v16i8 (or VR128:$src1, (load addr:$src2))),
+          (PORrm VR128:$src1, addr:$src2)>;
+def : Pat<(v4i32 (xor VR128:$src1, (load addr:$src2))),
+          (PXORrm VR128:$src1, addr:$src2)>;
+def : Pat<(v8i16 (xor VR128:$src1, (load addr:$src2))),
+          (PXORrm VR128:$src1, addr:$src2)>;
+def : Pat<(v16i8 (xor VR128:$src1, (load addr:$src2))),
+          (PXORrm VR128:$src1, addr:$src2)>;
+def : Pat<(v4i32 (and (vnot VR128:$src1), (load addr:$src2))),
+          (PANDNrm VR128:$src1, addr:$src2)>;
+def : Pat<(v8i16 (and (vnot VR128:$src1), (load addr:$src2))),
+          (PANDNrm VR128:$src1, addr:$src2)>;
+def : Pat<(v16i8 (and (vnot VR128:$src1), (load addr:$src2))),
+          (PANDNrm VR128:$src1, addr:$src2)>;





From lattner at cs.uiuc.edu  Thu Mar 30 12:52:14 2006
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Thu, 30 Mar 2006 12:52:14 -0600
Subject: [llvm-commits] CVS: llvm/include/llvm/IntrinsicsPowerPC.td 
Message-ID: <200603301852.MAA03748@zion.cs.uiuc.edu>



Changes in directory llvm/include/llvm:

IntrinsicsPowerPC.td updated: 1.9 -> 1.10
---
Log message:

Add vector multiply, multiply sum, pack, unpack, and lvsl/lvsr intrinsics.


---
Diffs of the changes:  (+91 -0)

 IntrinsicsPowerPC.td |   91 +++++++++++++++++++++++++++++++++++++++++++++++++++
 1 files changed, 91 insertions(+)


Index: llvm/include/llvm/IntrinsicsPowerPC.td
diff -u llvm/include/llvm/IntrinsicsPowerPC.td:1.9 llvm/include/llvm/IntrinsicsPowerPC.td:1.10
--- llvm/include/llvm/IntrinsicsPowerPC.td:1.9	Mon Mar 27 22:15:58 2006
+++ llvm/include/llvm/IntrinsicsPowerPC.td	Thu Mar 30 12:52:02 2006
@@ -190,6 +190,53 @@
               Intrinsic<[llvm_v4i32_ty, llvm_v4i32_ty, llvm_v4i32_ty],
                         [InstrNoMem]>;
 
+  // Vector Multiply Sum Instructions.
+  def int_ppc_altivec_vmsummbm : GCCBuiltin<"__builtin_altivec_vmsummbm">,
+            Intrinsic<[llvm_v16i8_ty, llvm_v16i8_ty, llvm_v4i32_ty],
+                      [InstrNoMem]>;
+  def int_ppc_altivec_vmsumshm : GCCBuiltin<"__builtin_altivec_vmsumshm">,
+            Intrinsic<[llvm_v8i16_ty, llvm_v8i16_ty, llvm_v4i32_ty],
+                      [InstrNoMem]>;
+  def int_ppc_altivec_vmsumshs : GCCBuiltin<"__builtin_altivec_vmsumshs">,
+            Intrinsic<[llvm_v8i16_ty, llvm_v8i16_ty, llvm_v4i32_ty],
+                      [InstrNoMem]>;
+  def int_ppc_altivec_vmsumubm : GCCBuiltin<"__builtin_altivec_vmsumubm">,
+            Intrinsic<[llvm_v16i8_ty, llvm_v16i8_ty, llvm_v4i32_ty],
+                      [InstrNoMem]>;
+  def int_ppc_altivec_vmsumuhm : GCCBuiltin<"__builtin_altivec_vmsumuhm">,
+            Intrinsic<[llvm_v8i16_ty, llvm_v8i16_ty, llvm_v4i32_ty],
+                      [InstrNoMem]>;
+  def int_ppc_altivec_vmsumuhs : GCCBuiltin<"__builtin_altivec_vmsumuhs">,
+            Intrinsic<[llvm_v8i16_ty, llvm_v8i16_ty, llvm_v4i32_ty],
+                      [InstrNoMem]>;
+
+  // Vector Multiply Instructions.
+  def int_ppc_altivec_vmulesb : GCCBuiltin<"__builtin_altivec_vmulesb">,
+          Intrinsic<[llvm_v8i16_ty, llvm_v16i8_ty, llvm_v16i8_ty],
+                    [InstrNoMem]>;
+  def int_ppc_altivec_vmulesh : GCCBuiltin<"__builtin_altivec_vmulesh">,
+          Intrinsic<[llvm_v4i32_ty, llvm_v8i16_ty, llvm_v8i16_ty],
+                    [InstrNoMem]>;
+  def int_ppc_altivec_vmuleub : GCCBuiltin<"__builtin_altivec_vmuleub">,
+          Intrinsic<[llvm_v8i16_ty, llvm_v16i8_ty, llvm_v16i8_ty],
+                    [InstrNoMem]>;
+  def int_ppc_altivec_vmuleuh : GCCBuiltin<"__builtin_altivec_vmuleuh">,
+          Intrinsic<[llvm_v4i32_ty, llvm_v8i16_ty, llvm_v8i16_ty],
+                    [InstrNoMem]>;
+
+  def int_ppc_altivec_vmulosb : GCCBuiltin<"__builtin_altivec_vmulosb">,
+          Intrinsic<[llvm_v8i16_ty, llvm_v16i8_ty, llvm_v16i8_ty],
+                    [InstrNoMem]>;
+  def int_ppc_altivec_vmulosh : GCCBuiltin<"__builtin_altivec_vmulosh">,
+          Intrinsic<[llvm_v4i32_ty, llvm_v8i16_ty, llvm_v8i16_ty],
+                    [InstrNoMem]>;
+  def int_ppc_altivec_vmuloub : GCCBuiltin<"__builtin_altivec_vmuloub">,
+          Intrinsic<[llvm_v8i16_ty, llvm_v16i8_ty, llvm_v16i8_ty],
+                    [InstrNoMem]>;
+  def int_ppc_altivec_vmulouh : GCCBuiltin<"__builtin_altivec_vmulouh">,
+          Intrinsic<[llvm_v4i32_ty, llvm_v8i16_ty, llvm_v8i16_ty],
+                    [InstrNoMem]>;
+
   // Vector Sum Instructions.
   def int_ppc_altivec_vsumsws : GCCBuiltin<"__builtin_altivec_vsumsws">,
             Intrinsic<[llvm_v4i32_ty, llvm_v4i32_ty, llvm_v4i32_ty],
@@ -207,6 +254,45 @@
             Intrinsic<[llvm_v4i32_ty, llvm_v16i8_ty, llvm_v4i32_ty],
                       [InstrNoMem]>;
 
+  // Packs.
+  def int_ppc_altivec_vpkpx : GCCBuiltin<"__builtin_altivec_vpkpx">,
+            Intrinsic<[llvm_v8i16_ty, llvm_v4i32_ty, llvm_v4i32_ty],
+                      [InstrNoMem]>;
+  def int_ppc_altivec_vpkshss : GCCBuiltin<"__builtin_altivec_vpkshss">,
+            Intrinsic<[llvm_v16i8_ty, llvm_v8i16_ty, llvm_v8i16_ty],
+                      [InstrNoMem]>;
+  def int_ppc_altivec_vpkshus : GCCBuiltin<"__builtin_altivec_vpkshus">,
+            Intrinsic<[llvm_v16i8_ty, llvm_v8i16_ty, llvm_v8i16_ty],
+                      [InstrNoMem]>;
+  def int_ppc_altivec_vpkswss : GCCBuiltin<"__builtin_altivec_vpkswss">,
+            Intrinsic<[llvm_v4i32_ty, llvm_v16i8_ty, llvm_v16i8_ty],
+                      [InstrNoMem]>;
+  def int_ppc_altivec_vpkswus : GCCBuiltin<"__builtin_altivec_vpkswus">,
+            Intrinsic<[llvm_v4i32_ty, llvm_v16i8_ty, llvm_v16i8_ty],
+                      [InstrNoMem]>;
+  // vpkuhum is lowered to a shuffle.
+  def int_ppc_altivec_vpkuhus : GCCBuiltin<"__builtin_altivec_vpkuhus">,
+            Intrinsic<[llvm_v16i8_ty, llvm_v8i16_ty, llvm_v8i16_ty],
+                      [InstrNoMem]>;
+  // vpkuwum is lowered to a shuffle.
+  def int_ppc_altivec_vpkuwus : GCCBuiltin<"__builtin_altivec_vpkuwus">,
+            Intrinsic<[llvm_v8i16_ty, llvm_v4i32_ty, llvm_v4i32_ty],
+                      [InstrNoMem]>;
+
+  // Unpacks.
+  def int_ppc_altivec_vupkhpx : GCCBuiltin<"__builtin_altivec_vupkhpx">,
+            Intrinsic<[llvm_v4i32_ty, llvm_v8i16_ty], [InstrNoMem]>;
+  def int_ppc_altivec_vupkhsb : GCCBuiltin<"__builtin_altivec_vupkhsb">,
+            Intrinsic<[llvm_v8i16_ty, llvm_v16i8_ty], [InstrNoMem]>;
+  def int_ppc_altivec_vupkhsh : GCCBuiltin<"__builtin_altivec_vupkhsh">,
+            Intrinsic<[llvm_v4i32_ty, llvm_v8i16_ty], [InstrNoMem]>;
+  def int_ppc_altivec_vupklpx : GCCBuiltin<"__builtin_altivec_vupklpx">,
+            Intrinsic<[llvm_v4i32_ty, llvm_v8i16_ty], [InstrNoMem]>;
+  def int_ppc_altivec_vupklsb : GCCBuiltin<"__builtin_altivec_vupklsb">,
+            Intrinsic<[llvm_v8i16_ty, llvm_v16i8_ty], [InstrNoMem]>;
+  def int_ppc_altivec_vupklsh : GCCBuiltin<"__builtin_altivec_vupklsh">,
+            Intrinsic<[llvm_v4i32_ty, llvm_v8i16_ty], [InstrNoMem]>;
+
 
   // FP to integer conversion.
   def int_ppc_altivec_vcfsx : GCCBuiltin<"__builtin_altivec_vcfsx">,
@@ -296,6 +382,11 @@
                         [InstrNoMem]>;
 
   // Miscellaneous.
+  def int_ppc_altivec_lvsl :
+              Intrinsic<[llvm_v16i8_ty, llvm_ptr_ty], [InstrNoMem]>;
+  def int_ppc_altivec_lvsr :
+              Intrinsic<[llvm_v16i8_ty, llvm_ptr_ty], [InstrNoMem]>;
+
   def int_ppc_altivec_vperm : GCCBuiltin<"__builtin_altivec_vperm_4si">,
               Intrinsic<[llvm_v4i32_ty, llvm_v4i32_ty, 
                          llvm_v4i32_ty, llvm_v16i8_ty], [InstrNoMem]>;





From evan.cheng at apple.com  Thu Mar 30 13:55:08 2006
From: evan.cheng at apple.com (Evan Cheng)
Date: Thu, 30 Mar 2006 13:55:08 -0600
Subject: [llvm-commits] CVS: llvm/lib/Target/X86/X86ISelLowering.cpp
	X86InstrSSE.td 
Message-ID: <200603301955.NAA04028@zion.cs.uiuc.edu>



Changes in directory llvm/lib/Target/X86:

X86ISelLowering.cpp updated: 1.145 -> 1.146
X86InstrSSE.td updated: 1.49 -> 1.50
---
Log message:

Make sure all possible shuffles are matched.
Use pshufd, pshuhw, and pshulw to shuffle v4f32 if shufps doesn't match.
Use shufps to shuffle v4f32 if pshufd, pshuhw, and pshulw don't match.


---
Diffs of the changes:  (+89 -30)

 X86ISelLowering.cpp |   53 ++++++++++++++++++++++++++---------------
 X86InstrSSE.td      |   66 +++++++++++++++++++++++++++++++++++++++++++---------
 2 files changed, 89 insertions(+), 30 deletions(-)


Index: llvm/lib/Target/X86/X86ISelLowering.cpp
diff -u llvm/lib/Target/X86/X86ISelLowering.cpp:1.145 llvm/lib/Target/X86/X86ISelLowering.cpp:1.146
--- llvm/lib/Target/X86/X86ISelLowering.cpp:1.145	Wed Mar 29 17:07:14 2006
+++ llvm/lib/Target/X86/X86ISelLowering.cpp	Thu Mar 30 13:54:57 2006
@@ -1486,23 +1486,17 @@
   if (NumElems != 4) return false;
 
   // Each half must refer to only one of the vector.
-  SDOperand Elt = N->getOperand(0);
-  assert(isa<ConstantSDNode>(Elt) && "Invalid VECTOR_SHUFFLE mask!");
-  for (unsigned i = 1; i < NumElems / 2; ++i) {
+  for (unsigned i = 0; i < 2; ++i) {
     assert(isa<ConstantSDNode>(N->getOperand(i)) &&
            "Invalid VECTOR_SHUFFLE mask!");
-    if (cast<ConstantSDNode>(N->getOperand(i))->getValue() != 
-        cast<ConstantSDNode>(Elt)->getValue())
-      return false;
+    unsigned Val = cast<ConstantSDNode>(N->getOperand(i))->getValue();
+    if (Val >= 4) return false;
   }
-  Elt = N->getOperand(NumElems / 2);
-  assert(isa<ConstantSDNode>(Elt) && "Invalid VECTOR_SHUFFLE mask!");
-  for (unsigned i = NumElems / 2 + 1; i < NumElems; ++i) {
+  for (unsigned i = 2; i < 4; ++i) {
     assert(isa<ConstantSDNode>(N->getOperand(i)) &&
            "Invalid VECTOR_SHUFFLE mask!");
-    if (cast<ConstantSDNode>(N->getOperand(i))->getValue() != 
-        cast<ConstantSDNode>(Elt)->getValue())
-      return false;
+    unsigned Val = cast<ConstantSDNode>(N->getOperand(i))->getValue();
+    if (Val < 4) return false;
   }
 
   return true;
@@ -2489,11 +2483,7 @@
     unsigned NumElems = PermMask.getNumOperands();
 
     // Splat && PSHUFD's 2nd vector must be undef.
-    if (X86::isSplatMask(PermMask.Val) ||
-        ((MVT::isInteger(VT) &&
-          (X86::isPSHUFDMask(PermMask.Val) ||
-           X86::isPSHUFHWMask(PermMask.Val) ||
-           X86::isPSHUFLWMask(PermMask.Val))))) {
+    if (X86::isSplatMask(PermMask.Val)) {
       if (V2.getOpcode() != ISD::UNDEF)
         return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1,
                            DAG.getNode(ISD::UNDEF, V1.getValueType()),PermMask);
@@ -2505,9 +2495,34 @@
       // Leave the VECTOR_SHUFFLE alone. It matches {P}UNPCKL*.
       return SDOperand();
 
-    if (NumElems == 2 ||
-        X86::isSHUFPMask(PermMask.Val)) {
+    if (NumElems == 2)
       return NormalizeVectorShuffle(V1, V2, PermMask, VT, DAG);
+
+    // If VT is integer, try PSHUF* first, then SHUFP*.
+    if (MVT::isInteger(VT)) {
+      if (X86::isPSHUFDMask(PermMask.Val) ||
+          X86::isPSHUFHWMask(PermMask.Val) ||
+          X86::isPSHUFLWMask(PermMask.Val)) {
+        if (V2.getOpcode() != ISD::UNDEF)
+          return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1,
+                             DAG.getNode(ISD::UNDEF, V1.getValueType()),PermMask);
+        return SDOperand();
+      }
+
+      if (X86::isSHUFPMask(PermMask.Val))
+        return NormalizeVectorShuffle(V1, V2, PermMask, VT, DAG);
+    } else {
+      // Floating point cases in the other order.
+      if (X86::isSHUFPMask(PermMask.Val))
+        return NormalizeVectorShuffle(V1, V2, PermMask, VT, DAG);
+      if (X86::isPSHUFDMask(PermMask.Val) ||
+          X86::isPSHUFHWMask(PermMask.Val) ||
+          X86::isPSHUFLWMask(PermMask.Val)) {
+        if (V2.getOpcode() != ISD::UNDEF)
+          return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1,
+                             DAG.getNode(ISD::UNDEF, V1.getValueType()),PermMask);
+        return SDOperand();
+      }
     }
 
     assert(0 && "Unexpected VECTOR_SHUFFLE to lower");


Index: llvm/lib/Target/X86/X86InstrSSE.td
diff -u llvm/lib/Target/X86/X86InstrSSE.td:1.49 llvm/lib/Target/X86/X86InstrSSE.td:1.50
--- llvm/lib/Target/X86/X86InstrSSE.td:1.49	Thu Mar 30 01:33:32 2006
+++ llvm/lib/Target/X86/X86InstrSSE.td	Thu Mar 30 13:54:57 2006
@@ -106,14 +106,32 @@
   return X86::isPSHUFLWMask(N);
 }], SHUFFLE_get_pshuflw_imm>;
 
+// Only use PSHUF* for v4f32 if SHUFP does not match.
+def PSHUFD_fp_shuffle_mask : PatLeaf<(build_vector), [{
+  return !X86::isSHUFPMask(N) &&
+          X86::isPSHUFDMask(N);
+}], SHUFFLE_get_shuf_imm>;
+
+def PSHUFHW_fp_shuffle_mask : PatLeaf<(build_vector), [{
+  return !X86::isSHUFPMask(N) &&
+          X86::isPSHUFHWMask(N);
+}], SHUFFLE_get_pshufhw_imm>;
+
+def PSHUFLW_fp_shuffle_mask : PatLeaf<(build_vector), [{
+  return !X86::isSHUFPMask(N) &&
+          X86::isPSHUFLWMask(N);
+}], SHUFFLE_get_pshuflw_imm>;
+
 def SHUFP_shuffle_mask : PatLeaf<(build_vector), [{
   return X86::isSHUFPMask(N);
 }], SHUFFLE_get_shuf_imm>;
 
-// Only use SHUFP for v4i32 if no other options are available.
-// FIXME: add tblgen hook to reduce the complexity of pattern.
-def SHUFP_v4i32_shuffle_mask : PatLeaf<(build_vector), [{
-  return !X86::isUNPCKHMask(N) && !X86::isPSHUFDMask(N) && X86::isSHUFPMask(N);
+// Only use SHUFP for v4i32 if PSHUF* do not match.
+def SHUFP_int_shuffle_mask : PatLeaf<(build_vector), [{
+  return !X86::isPSHUFDMask(N) &&
+         !X86::isPSHUFHWMask(N) &&
+         !X86::isPSHUFLWMask(N) &&
+          X86::isSHUFPMask(N);
 }], SHUFFLE_get_shuf_imm>;
 
 //===----------------------------------------------------------------------===//
@@ -1278,14 +1296,14 @@
 // SSE2 with ImmT == Imm8 and XD prefix.
 def PSHUFLWrr : Ii8<0x70, MRMDestReg,
                     (ops VR128:$dst, VR128:$src1, i32i8imm:$src2),
-                    "pshufLw {$src2, $src1, $dst|$dst, $src1, $src2}",
+                    "pshuflw {$src2, $src1, $dst|$dst, $src1, $src2}",
                     [(set VR128:$dst, (v8i16 (vector_shuffle
                                               VR128:$src1, (undef),
                                               PSHUFLW_shuffle_mask:$src2)))]>,
                 XD, Requires<[HasSSE2]>;
 def PSHUFLWrm : Ii8<0x70, MRMDestMem,
                     (ops VR128:$dst, i128mem:$src1, i32i8imm:$src2),
-                    "pshufLw {$src2, $src1, $dst|$dst, $src1, $src2}",
+                    "pshuflw {$src2, $src1, $dst|$dst, $src1, $src2}",
                     [(set VR128:$dst, (v8i16 (vector_shuffle
                                      (bc_v8i16 (loadv2i64 addr:$src1)), (undef),
                                               PSHUFLW_shuffle_mask:$src2)))]>,
@@ -1593,15 +1611,41 @@
           (v4f32 (SHUFPSrr VR128:$src, VR128:$src, SSE_splat_mask:$sm))>,
       Requires<[HasSSE1]>;
 
-// Shuffle v4i32 if others do not match
+// Shuffle v4i32 with SHUFP* if others do not match.
 def : Pat<(vector_shuffle (v4i32 VR128:$src1), (v4i32 VR128:$src2),
-           SHUFP_shuffle_mask:$sm),
+           SHUFP_int_shuffle_mask:$sm),
           (v4i32 (SHUFPSrr VR128:$src1, VR128:$src2,
-                  SHUFP_v4i32_shuffle_mask:$sm))>, Requires<[HasSSE2]>;
+                  SHUFP_int_shuffle_mask:$sm))>, Requires<[HasSSE2]>;
 def : Pat<(vector_shuffle (v4i32 VR128:$src1), (load addr:$src2),
-           SHUFP_shuffle_mask:$sm),
+           SHUFP_int_shuffle_mask:$sm),
           (v4i32 (SHUFPSrm VR128:$src1, addr:$src2,
-                  SHUFP_v4i32_shuffle_mask:$sm))>, Requires<[HasSSE2]>;
+                  SHUFP_int_shuffle_mask:$sm))>, Requires<[HasSSE2]>;
+
+// Shuffle v4f32 with PSHUF* if others do not match.
+def : Pat<(vector_shuffle (v4f32 VR128:$src1), (undef),
+           PSHUFD_fp_shuffle_mask:$sm),
+          (v4f32 (PSHUFDrr VR128:$src1, PSHUFD_fp_shuffle_mask:$sm))>,
+      Requires<[HasSSE2]>;
+def : Pat<(vector_shuffle (loadv4f32 addr:$src1), (undef),
+           PSHUFD_fp_shuffle_mask:$sm),
+          (v4f32 (PSHUFDrm addr:$src1, PSHUFD_fp_shuffle_mask:$sm))>,
+      Requires<[HasSSE2]>;
+def : Pat<(vector_shuffle (v4f32 VR128:$src1), (undef),
+           PSHUFHW_fp_shuffle_mask:$sm),
+          (v4f32 (PSHUFHWrr VR128:$src1, PSHUFHW_fp_shuffle_mask:$sm))>,
+      Requires<[HasSSE2]>;
+def : Pat<(vector_shuffle (loadv4f32 addr:$src1), (undef),
+           PSHUFHW_fp_shuffle_mask:$sm),
+          (v4f32 (PSHUFHWrm addr:$src1, PSHUFHW_fp_shuffle_mask:$sm))>,
+      Requires<[HasSSE2]>;
+def : Pat<(vector_shuffle (v4f32 VR128:$src1), (undef),
+           PSHUFLW_fp_shuffle_mask:$sm),
+          (v4f32 (PSHUFLWrr VR128:$src1, PSHUFLW_fp_shuffle_mask:$sm))>,
+      Requires<[HasSSE2]>;
+def : Pat<(vector_shuffle (loadv4f32 addr:$src1), (undef),
+           PSHUFLW_fp_shuffle_mask:$sm),
+          (v4f32 (PSHUFLWrm addr:$src1, PSHUFLW_fp_shuffle_mask:$sm))>,
+      Requires<[HasSSE2]>;
 
 // Logical ops
 def : Pat<(and (bc_v4i32 (v4f32 VR128:$src1)), (loadv4i32 addr:$src2)),





From lattner at cs.uiuc.edu  Thu Mar 30 16:01:20 2006
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Thu, 30 Mar 2006 16:01:20 -0600
Subject: [llvm-commits] 
	CVS: llvm/test/Regression/Transforms/InstCombine/2006-03-30-ExtractElement.ll
Message-ID: <200603302201.QAA04695@zion.cs.uiuc.edu>



Changes in directory llvm/test/Regression/Transforms/InstCombine:

2006-03-30-ExtractElement.ll added (r1.1)
---
Log message:

new testcase that crashes instcombine


---
Diffs of the changes:  (+7 -0)

 2006-03-30-ExtractElement.ll |    7 +++++++
 1 files changed, 7 insertions(+)


Index: llvm/test/Regression/Transforms/InstCombine/2006-03-30-ExtractElement.ll
diff -c /dev/null llvm/test/Regression/Transforms/InstCombine/2006-03-30-ExtractElement.ll:1.1
*** /dev/null	Thu Mar 30 16:01:18 2006
--- llvm/test/Regression/Transforms/InstCombine/2006-03-30-ExtractElement.ll	Thu Mar 30 16:01:08 2006
***************
*** 0 ****
--- 1,7 ----
+ ; RUN: llvm-as < %s | opt -instcombine -disable-output
+ 
+ float %test(<4 x float> %V) {
+ 	%V2 = insertelement <4 x float> %V, float 1.0, uint 3
+ 	%R = extractelement <4 x float> %V2, uint 2
+ 	ret float %R
+ }





From lattner at cs.uiuc.edu  Thu Mar 30 16:02:52 2006
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Thu, 30 Mar 2006 16:02:52 -0600
Subject: [llvm-commits] 
	CVS: llvm/lib/Transforms/Scalar/InstructionCombining.cpp
Message-ID: <200603302202.QAA04738@zion.cs.uiuc.edu>



Changes in directory llvm/lib/Transforms/Scalar:

InstructionCombining.cpp updated: 1.453 -> 1.454
---
Log message:

Fix Transforms/InstCombine/2006-03-30-ExtractElement.ll


---
Diffs of the changes:  (+7 -3)

 InstructionCombining.cpp |   10 +++++++---
 1 files changed, 7 insertions(+), 3 deletions(-)


Index: llvm/lib/Transforms/Scalar/InstructionCombining.cpp
diff -u llvm/lib/Transforms/Scalar/InstructionCombining.cpp:1.453 llvm/lib/Transforms/Scalar/InstructionCombining.cpp:1.454
--- llvm/lib/Transforms/Scalar/InstructionCombining.cpp:1.453	Sat Mar 25 15:58:26 2006
+++ llvm/lib/Transforms/Scalar/InstructionCombining.cpp	Thu Mar 30 16:02:40 2006
@@ -6704,9 +6704,13 @@
         if (IE->getOperand(2) == EI.getOperand(1))
           return ReplaceInstUsesWith(EI, IE->getOperand(1));
         // If the inserted and extracted elements are constants, they must not
-        // be the same value, replace with the pre-inserted value.
-        if (isa<Constant>(IE->getOperand(2)) && isa<Constant>(EI.getOperand(1)))
-          return ReplaceInstUsesWith(EI, IE->getOperand(0));
+        // be the same value, extract from the pre-inserted value instead.
+        if (isa<Constant>(IE->getOperand(2)) &&
+            isa<Constant>(EI.getOperand(1))) {
+          AddUsesToWorkList(EI);
+          EI.setOperand(0, IE->getOperand(0));
+          return &EI;
+        }
       }
     }
   return 0;





From lattner at cs.uiuc.edu  Thu Mar 30 16:50:11 2006
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Thu, 30 Mar 2006 16:50:11 -0600
Subject: [llvm-commits] CVS: llvm/test/Regression/TableGen/DagDefSubst.ll 
Message-ID: <200603302250.QAA05038@zion.cs.uiuc.edu>



Changes in directory llvm/test/Regression/TableGen:

DagDefSubst.ll added (r1.1)
---
Log message:

Dag operator should be able to be template params.


---
Diffs of the changes:  (+15 -0)

 DagDefSubst.ll |   15 +++++++++++++++
 1 files changed, 15 insertions(+)


Index: llvm/test/Regression/TableGen/DagDefSubst.ll
diff -c /dev/null llvm/test/Regression/TableGen/DagDefSubst.ll:1.1
*** /dev/null	Thu Mar 30 16:50:09 2006
--- llvm/test/Regression/TableGen/DagDefSubst.ll	Thu Mar 30 16:49:59 2006
***************
*** 0 ****
--- 1,15 ----
+ // RUN: tblgen %s | grep 'dag d = (X Y)' &&
+ // RUN: tblgen %s | grep 'dag e = (Y X)'
+ def X;
+ 
+ class yclass;
+ def Y : yclass;
+ 
+ class C<yclass N> {
+   dag d = (X N);
+   dag e = (N X);
+ }
+ 
+ def VAL : C<Y>;
+ 
+ 





From lattner at cs.uiuc.edu  Thu Mar 30 16:50:52 2006
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Thu, 30 Mar 2006 16:50:52 -0600
Subject: [llvm-commits] CVS: llvm/utils/TableGen/DAGISelEmitter.cpp
	FileParser.y Record.h Record.cpp 
Message-ID: <200603302250.QAA05105@zion.cs.uiuc.edu>



Changes in directory llvm/utils/TableGen:

DAGISelEmitter.cpp updated: 1.190 -> 1.191
FileParser.y updated: 1.40 -> 1.41
Record.h updated: 1.55 -> 1.56
Record.cpp updated: 1.51 -> 1.52
---
Log message:

Implement Regression/TableGen/DagDefSubst.ll


---
Diffs of the changes:  (+45 -41)

 DAGISelEmitter.cpp |   11 +++++++----
 FileParser.y       |   49 ++++++++++++++++++++++++-------------------------
 Record.cpp         |    8 +++++---
 Record.h           |   18 +++++++++---------
 4 files changed, 45 insertions(+), 41 deletions(-)


Index: llvm/utils/TableGen/DAGISelEmitter.cpp
diff -u llvm/utils/TableGen/DAGISelEmitter.cpp:1.190 llvm/utils/TableGen/DAGISelEmitter.cpp:1.191
--- llvm/utils/TableGen/DAGISelEmitter.cpp:1.190	Mon Mar 27 18:41:33 2006
+++ llvm/utils/TableGen/DAGISelEmitter.cpp	Thu Mar 30 16:50:40 2006
@@ -804,7 +804,9 @@
 }
 
 TreePatternNode *TreePattern::ParseTreePattern(DagInit *Dag) {
-  Record *Operator = Dag->getNodeType();
+  DefInit *OpDef = dynamic_cast<DefInit*>(Dag->getOperator());
+  if (!OpDef) error("Pattern has unexpected operator type!");
+  Record *Operator = OpDef->getDef();
   
   if (Operator->isSubClassOf("ValueType")) {
     // If the operator is a ValueType, then this must be "type cast" of a leaf
@@ -817,7 +819,7 @@
     if (DefInit *DI = dynamic_cast<DefInit*>(Arg)) {
       Record *R = DI->getDef();
       if (R->isSubClassOf("SDNode") || R->isSubClassOf("PatFrag")) {
-        Dag->setArg(0, new DagInit(R,
+        Dag->setArg(0, new DagInit(DI,
                                 std::vector<std::pair<Init*, std::string> >()));
         return ParseTreePattern(Dag);
       }
@@ -866,7 +868,7 @@
       // Direct reference to a leaf DagNode or PatFrag?  Turn it into a
       // TreePatternNode if its own.
       if (R->isSubClassOf("SDNode") || R->isSubClassOf("PatFrag")) {
-        Dag->setArg(i, new DagInit(R,
+        Dag->setArg(i, new DagInit(DefI,
                               std::vector<std::pair<Init*, std::string> >()));
         --i;  // Revisit this node...
       } else {
@@ -1043,7 +1045,8 @@
     
     // Parse the operands list.
     DagInit *OpsList = Fragments[i]->getValueAsDag("Operands");
-    if (OpsList->getNodeType()->getName() != "ops")
+    DefInit *OpsOp = dynamic_cast<DefInit*>(OpsList->getOperator());
+    if (!OpsOp || OpsOp->getDef()->getName() != "ops")
       P->error("Operands list should start with '(ops ... '!");
     
     // Copy over the arguments.       


Index: llvm/utils/TableGen/FileParser.y
diff -u llvm/utils/TableGen/FileParser.y:1.40 llvm/utils/TableGen/FileParser.y:1.41
--- llvm/utils/TableGen/FileParser.y:1.40	Tue Jan 31 00:02:35 2006
+++ llvm/utils/TableGen/FileParser.y	Thu Mar 30 16:50:40 2006
@@ -210,7 +210,7 @@
 %type <SubClassRef>  SubClassRef
 %type <SubClassList> ClassList ClassListNE
 %type <IntVal>       OptPrefix
-%type <Initializer>  Value OptValue
+%type <Initializer>  Value OptValue IDValue
 %type <DagValueList> DagArgList DagArgListNE
 %type <FieldList>    ValueList ValueListNE
 %type <BitList>      BitList OptBitList RBitList
@@ -253,7 +253,26 @@
 
 OptValue : /*empty*/ { $$ = 0; } | '=' Value { $$ = $2; };
 
-Value : INTVAL {
+IDValue : ID {
+  if (const RecordVal *RV = (CurRec ? CurRec->getValue(*$1) : 0)) {
+    $$ = new VarInit(*$1, RV->getType());
+  } else if (CurRec && CurRec->isTemplateArg(CurRec->getName()+":"+*$1)) {
+    const RecordVal *RV = CurRec->getValue(CurRec->getName()+":"+*$1);
+    assert(RV && "Template arg doesn't exist??");
+    $$ = new VarInit(CurRec->getName()+":"+*$1, RV->getType());
+  } else if (Record *D = Records.getDef(*$1)) {
+    $$ = new DefInit(D);
+  } else {
+    err() << "Variable not defined: '" << *$1 << "'!\n";
+    exit(1);
+  }
+  
+  delete $1;
+};
+
+Value : IDValue {
+    $$ = $1;
+  } | INTVAL {
     $$ = new IntInit($1);
   } | STRVAL {
     $$ = new StringInit(*$1);
@@ -304,21 +323,6 @@
     
     // Restore the old CurRec
     CurRec = OldRec;
-  } | ID {
-    if (const RecordVal *RV = (CurRec ? CurRec->getValue(*$1) : 0)) {
-      $$ = new VarInit(*$1, RV->getType());
-    } else if (CurRec && CurRec->isTemplateArg(CurRec->getName()+":"+*$1)) {
-      const RecordVal *RV = CurRec->getValue(CurRec->getName()+":"+*$1);
-      assert(RV && "Template arg doesn't exist??");
-      $$ = new VarInit(CurRec->getName()+":"+*$1, RV->getType());
-    } else if (Record *D = Records.getDef(*$1)) {
-      $$ = new DefInit(D);
-    } else {
-      err() << "Variable not defined: '" << *$1 << "'!\n";
-      exit(1);
-    }
-    
-    delete $1;
   } | Value '{' BitList '}' {
     $$ = $1->convertInitializerBitRange(*$3);
     if ($$ == 0) {
@@ -336,14 +340,9 @@
     }
     $$ = new FieldInit($1, *$3);
     delete $3;
-  } | '(' ID DagArgList ')' {
-    Record *D = Records.getDef(*$2);
-    if (D == 0) {
-      err() << "Invalid def '" << *$2 << "'!\n";
-      exit(1);
-    }
-    $$ = new DagInit(D, *$3);
-    delete $2; delete $3;
+  } | '(' IDValue DagArgList ')' {
+    $$ = new DagInit($2, *$3);
+    delete $3;
   } | Value '[' BitList ']' {
     std::reverse($3->begin(), $3->end());
     $$ = $1->convertInitListSlice(*$3);


Index: llvm/utils/TableGen/Record.h
diff -u llvm/utils/TableGen/Record.h:1.55 llvm/utils/TableGen/Record.h:1.56
--- llvm/utils/TableGen/Record.h:1.55	Tue Jan 31 00:02:35 2006
+++ llvm/utils/TableGen/Record.h	Thu Mar 30 16:50:40 2006
@@ -808,17 +808,17 @@
   }
 };
 
-/// DagInit - (def a, b) - Represent a DAG tree value.  DAG inits are required
-/// to have Records for their first value, after that, any legal Init is
-/// possible.
+/// DagInit - (v a, b) - Represent a DAG tree value.  DAG inits are required
+/// to have at least one value then a (possibly empty) list of arguments.  Each
+/// argument can have a name associated with it.
 ///
 class DagInit : public Init {
-  Record *NodeTypeDef;
+  Init *Val;
   std::vector<Init*> Args;
   std::vector<std::string> ArgNames;
 public:
-  DagInit(Record *D, const std::vector<std::pair<Init*, std::string> > &args)
-    : NodeTypeDef(D) {
+  DagInit(Init *V, const std::vector<std::pair<Init*, std::string> > &args)
+    : Val(V) {
     Args.reserve(args.size());
     ArgNames.reserve(args.size());
     for (unsigned i = 0, e = args.size(); i != e; ++i) {
@@ -826,16 +826,16 @@
       ArgNames.push_back(args[i].second);
     }
   }
-  DagInit(Record *D, const std::vector<Init*> &args, 
+  DagInit(Init *V, const std::vector<Init*> &args, 
           const std::vector<std::string> &argNames)
-  : NodeTypeDef(D), Args(args), ArgNames(argNames) {
+  : Val(V), Args(args), ArgNames(argNames) {
   }
   
   virtual Init *convertInitializerTo(RecTy *Ty) {
     return Ty->convertValue(this);
   }
 
-  Record *getNodeType() const { return NodeTypeDef; }
+  Init *getOperator() const { return Val; }
 
   unsigned getNumArgs() const { return Args.size(); }
   Init *getArg(unsigned Num) const {


Index: llvm/utils/TableGen/Record.cpp
diff -u llvm/utils/TableGen/Record.cpp:1.51 llvm/utils/TableGen/Record.cpp:1.52
--- llvm/utils/TableGen/Record.cpp:1.51	Fri Feb 17 21:20:33 2006
+++ llvm/utils/TableGen/Record.cpp	Thu Mar 30 16:50:40 2006
@@ -559,15 +559,17 @@
   for (unsigned i = 0, e = Args.size(); i != e; ++i)
     NewArgs.push_back(Args[i]->resolveReferences(R, RV));
   
-  if (Args != NewArgs)
-    return new DagInit(NodeTypeDef, NewArgs, ArgNames);
+  Init *Op = Val->resolveReferences(R, RV);
+  
+  if (Args != NewArgs || Op != Val)
+    return new DagInit(Op, NewArgs, ArgNames);
     
   return this;
 }
 
 
 void DagInit::print(std::ostream &OS) const {
-  OS << "(" << NodeTypeDef->getName();
+  OS << "(" << *Val;
   if (Args.size()) {
     OS << " " << *Args[0];
     if (!ArgNames[0].empty()) OS << ":$" << ArgNames[0];





From lattner at cs.uiuc.edu  Thu Mar 30 16:51:24 2006
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Thu, 30 Mar 2006 16:51:24 -0600
Subject: [llvm-commits] CVS: llvm/utils/TableGen/FileParser.cpp.cvs
	FileParser.h.cvs FileParser.y.cvs 
Message-ID: <200603302251.QAA05146@zion.cs.uiuc.edu>



Changes in directory llvm/utils/TableGen:

FileParser.cpp.cvs updated: 1.1 -> 1.2
FileParser.h.cvs updated: 1.1 -> 1.2
FileParser.y.cvs updated: 1.1 -> 1.2
---
Log message:

regenerate


---
Diffs of the changes:  (+1207 -1662)

 FileParser.cpp.cvs | 2709 ++++++++++++++++++++++-------------------------------
 FileParser.h.cvs   |  111 --
 FileParser.y.cvs   |   49 
 3 files changed, 1207 insertions(+), 1662 deletions(-)


Index: llvm/utils/TableGen/FileParser.cpp.cvs
diff -u llvm/utils/TableGen/FileParser.cpp.cvs:1.1 llvm/utils/TableGen/FileParser.cpp.cvs:1.2
--- llvm/utils/TableGen/FileParser.cpp.cvs:1.1	Wed Feb 15 01:24:01 2006
+++ llvm/utils/TableGen/FileParser.cpp.cvs	Thu Mar 30 16:51:12 2006
@@ -1,115 +1,38 @@
-/* A Bison parser, made by GNU Bison 1.875.  */
 
-/* Skeleton parser for Yacc-like parsing with Bison,
-   Copyright (C) 1984, 1989, 1990, 2000, 2001, 2002 Free Software Foundation, Inc.
+/*  A Bison parser, made from /Volumes/ProjectsDisk/cvs/llvm/utils/TableGen/FileParser.y
+    by GNU Bison version 1.28  */
 
-   This program is free software; you can redistribute it and/or modify
-   it under the terms of the GNU General Public License as published by
-   the Free Software Foundation; either version 2, or (at your option)
-   any later version.
+#define YYBISON 1  /* Identify Bison output.  */
 
-   This program is distributed in the hope that it will be useful,
-   but WITHOUT ANY WARRANTY; without even the implied warranty of
-   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-   GNU General Public License for more details.
-
-   You should have received a copy of the GNU General Public License
-   along with this program; if not, write to the Free Software
-   Foundation, Inc., 59 Temple Place - Suite 330,
-   Boston, MA 02111-1307, USA.  */
-
-/* As a special exception, when this file is copied by Bison into a
-   Bison output file, you may use that output file without restriction.
-   This special exception was added by the Free Software Foundation
-   in version 1.24 of Bison.  */
-
-/* Written by Richard Stallman by simplifying the original so called
-   ``semantic'' parser.  */
-
-/* All symbols defined below should begin with yy or YY, to avoid
-   infringing on user name space.  This should be done even for local
-   variables, as they might otherwise be expanded by user macros.
-   There are some unavoidable exceptions within include files to
-   define necessary library symbols; they are noted "INFRINGES ON
-   USER NAME SPACE" below.  */
-
-/* Identify Bison output.  */
-#define YYBISON 1
-
-/* Skeleton name.  */
-#define YYSKELETON_NAME "yacc.c"
-
-/* Pure parsers.  */
-#define YYPURE 0
-
-/* Using locations.  */
-#define YYLSP_NEEDED 0
-
-/* If NAME_PREFIX is specified substitute the variables and functions
-   names.  */
 #define yyparse Fileparse
-#define yylex   Filelex
+#define yylex Filelex
 #define yyerror Fileerror
-#define yylval  Filelval
-#define yychar  Filechar
+#define yylval Filelval
+#define yychar Filechar
 #define yydebug Filedebug
 #define yynerrs Filenerrs
+#define	INT	257
+#define	BIT	258
+#define	STRING	259
+#define	BITS	260
+#define	LIST	261
+#define	CODE	262
+#define	DAG	263
+#define	CLASS	264
+#define	DEF	265
+#define	FIELD	266
+#define	LET	267
+#define	IN	268
+#define	SHLTOK	269
+#define	SRATOK	270
+#define	SRLTOK	271
+#define	INTVAL	272
+#define	ID	273
+#define	VARNAME	274
+#define	STRVAL	275
+#define	CODEFRAGMENT	276
 
-
-/* Tokens.  */
-#ifndef YYTOKENTYPE
-# define YYTOKENTYPE
-   /* Put the tokens into the symbol table, so that GDB and other debuggers
-      know about them.  */
-   enum yytokentype {
-     INT = 258,
-     BIT = 259,
-     STRING = 260,
-     BITS = 261,
-     LIST = 262,
-     CODE = 263,
-     DAG = 264,
-     CLASS = 265,
-     DEF = 266,
-     FIELD = 267,
-     LET = 268,
-     IN = 269,
-     SHLTOK = 270,
-     SRATOK = 271,
-     SRLTOK = 272,
-     INTVAL = 273,
-     ID = 274,
-     VARNAME = 275,
-     STRVAL = 276,
-     CODEFRAGMENT = 277
-   };
-#endif
-#define INT 258
-#define BIT 259
-#define STRING 260
-#define BITS 261
-#define LIST 262
-#define CODE 263
-#define DAG 264
-#define CLASS 265
-#define DEF 266
-#define FIELD 267
-#define LET 268
-#define IN 269
-#define SHLTOK 270
-#define SRATOK 271
-#define SRLTOK 272
-#define INTVAL 273
-#define ID 274
-#define VARNAME 275
-#define STRVAL 276
-#define CODEFRAGMENT 277
-
-
-
-
-/* Copy the first part of user declarations.  */
-#line 14 "/home/vadve/criswell/llvm/utils/TableGen/FileParser.y"
+#line 14 "/Volumes/ProjectsDisk/cvs/llvm/utils/TableGen/FileParser.y"
 
 #include "Record.h"
 #include "llvm/ADT/StringExtras.h"
@@ -167,7 +90,7 @@
 }
 
 static void setValue(const std::string &ValName, 
-		     std::vector<unsigned> *BitList, Init *V) {
+                     std::vector<unsigned> *BitList, Init *V) {
   if (!V) return;
 
   RecordVal *RV = CurRec->getValue(ValName);
@@ -284,23 +207,8 @@
 using namespace llvm;
 
 
-
-/* Enabling traces.  */
-#ifndef YYDEBUG
-# define YYDEBUG 0
-#endif
-
-/* Enabling verbose error messages.  */
-#ifdef YYERROR_VERBOSE
-# undef YYERROR_VERBOSE
-# define YYERROR_VERBOSE 1
-#else
-# define YYERROR_VERBOSE 0
-#endif
-
-#if ! defined (YYSTYPE) && ! defined (YYSTYPE_IS_DECLARED)
-#line 189 "/home/vadve/criswell/llvm/utils/TableGen/FileParser.y"
-typedef union YYSTYPE {
+#line 189 "/Volumes/ProjectsDisk/cvs/llvm/utils/TableGen/FileParser.y"
+typedef union {
   std::string*                StrVal;
   int                         IntVal;
   llvm::RecTy*                Ty;
@@ -312,835 +220,543 @@
   std::vector<SubClassRefTy>* SubClassList;
   std::vector<std::pair<llvm::Init*, std::string> >* DagValueList;
 } YYSTYPE;
-/* Line 191 of yacc.c.  */
-#line 316 "FileParser.tab.c"
-# define yystype YYSTYPE /* obsolescent; will be withdrawn */
-# define YYSTYPE_IS_DECLARED 1
-# define YYSTYPE_IS_TRIVIAL 1
-#endif
-
-
-
-/* Copy the second part of user declarations.  */
-
-
-/* Line 214 of yacc.c.  */
-#line 328 "FileParser.tab.c"
-
-#if ! defined (yyoverflow) || YYERROR_VERBOSE
-
-/* The parser invokes alloca or malloc; define the necessary symbols.  */
-
-# if YYSTACK_USE_ALLOCA
-#  define YYSTACK_ALLOC alloca
-# else
-#  ifndef YYSTACK_USE_ALLOCA
-#   if defined (alloca) || defined (_ALLOCA_H)
-#    define YYSTACK_ALLOC alloca
-#   else
-#    ifdef __GNUC__
-#     define YYSTACK_ALLOC __builtin_alloca
-#    endif
-#   endif
-#  endif
-# endif
-
-# ifdef YYSTACK_ALLOC
-   /* Pacify GCC's `empty if-body' warning. */
-#  define YYSTACK_FREE(Ptr) do { /* empty */; } while (0)
-# else
-#  if defined (__STDC__) || defined (__cplusplus)
-#   include <stdlib.h> /* INFRINGES ON USER NAME SPACE */
-#   define YYSIZE_T size_t
-#  endif
-#  define YYSTACK_ALLOC malloc
-#  define YYSTACK_FREE free
-# endif
-#endif /* ! defined (yyoverflow) || YYERROR_VERBOSE */
-
-
-#if (! defined (yyoverflow) \
-     && (! defined (__cplusplus) \
-	 || (YYSTYPE_IS_TRIVIAL)))
-
-/* A type that is properly aligned for any stack member.  */
-union yyalloc
-{
-  short yyss;
-  YYSTYPE yyvs;
-  };
-
-/* The size of the maximum gap between one aligned stack and the next.  */
-# define YYSTACK_GAP_MAXIMUM (sizeof (union yyalloc) - 1)
-
-/* The size of an array large to enough to hold all stacks, each with
-   N elements.  */
-# define YYSTACK_BYTES(N) \
-     ((N) * (sizeof (short) + sizeof (YYSTYPE))				\
-      + YYSTACK_GAP_MAXIMUM)
-
-/* Copy COUNT objects from FROM to TO.  The source and destination do
-   not overlap.  */
-# ifndef YYCOPY
-#  if 1 < __GNUC__
-#   define YYCOPY(To, From, Count) \
-      __builtin_memcpy (To, From, (Count) * sizeof (*(From)))
-#  else
-#   define YYCOPY(To, From, Count)		\
-      do					\
-	{					\
-	  register YYSIZE_T yyi;		\
-	  for (yyi = 0; yyi < (Count); yyi++)	\
-	    (To)[yyi] = (From)[yyi];		\
-	}					\
-      while (0)
-#  endif
-# endif
-
-/* Relocate STACK from its old location to the new one.  The
-   local variables YYSIZE and YYSTACKSIZE give the old and new number of
-   elements in the stack, and YYPTR gives the new location of the
-   stack.  Advance YYPTR to a properly aligned location for the next
-   stack.  */
-# define YYSTACK_RELOCATE(Stack)					\
-    do									\
-      {									\
-	YYSIZE_T yynewbytes;						\
-	YYCOPY (&yyptr->Stack, Stack, yysize);				\
-	Stack = &yyptr->Stack;						\
-	yynewbytes = yystacksize * sizeof (*Stack) + YYSTACK_GAP_MAXIMUM; \
-	yyptr += yynewbytes / sizeof (*yyptr);				\
-      }									\
-    while (0)
+#include <stdio.h>
 
+#ifndef __cplusplus
+#ifndef __STDC__
+#define const
 #endif
-
-#if defined (__STDC__) || defined (__cplusplus)
-   typedef signed char yysigned_char;
-#else
-   typedef short yysigned_char;
 #endif
 
-/* YYFINAL -- State number of the termination state. */
-#define YYFINAL  20
-/* YYLAST -- Last index in YYTABLE.  */
-#define YYLAST   163
-
-/* YYNTOKENS -- Number of terminals. */
-#define YYNTOKENS  38
-/* YYNNTS -- Number of nonterminals. */
-#define YYNNTS  41
-/* YYNRULES -- Number of rules. */
-#define YYNRULES  89
-/* YYNRULES -- Number of states. */
-#define YYNSTATES  160
-
-/* YYTRANSLATE(YYLEX) -- Bison symbol number corresponding to YYLEX.  */
-#define YYUNDEFTOK  2
-#define YYMAXUTOK   277
-
-#define YYTRANSLATE(YYX) 						\
-  ((unsigned int) (YYX) <= YYMAXUTOK ? yytranslate[YYX] : YYUNDEFTOK)
-
-/* YYTRANSLATE[YYLEX] -- Bison symbol number corresponding to YYLEX.  */
-static const unsigned char yytranslate[] =
-{
-       0,     2,     2,     2,     2,     2,     2,     2,     2,     2,
-       2,     2,     2,     2,     2,     2,     2,     2,     2,     2,
-       2,     2,     2,     2,     2,     2,     2,     2,     2,     2,
-       2,     2,     2,     2,     2,     2,     2,     2,     2,     2,
-      32,    33,     2,     2,    34,    36,    31,     2,     2,     2,
-       2,     2,     2,     2,     2,     2,     2,     2,    35,    37,
-      23,    25,    24,    26,     2,     2,     2,     2,     2,     2,
-       2,     2,     2,     2,     2,     2,     2,     2,     2,     2,
-       2,     2,     2,     2,     2,     2,     2,     2,     2,     2,
-       2,    29,     2,    30,     2,     2,     2,     2,     2,     2,
-       2,     2,     2,     2,     2,     2,     2,     2,     2,     2,
-       2,     2,     2,     2,     2,     2,     2,     2,     2,     2,
-       2,     2,     2,    27,     2,    28,     2,     2,     2,     2,
-       2,     2,     2,     2,     2,     2,     2,     2,     2,     2,
-       2,     2,     2,     2,     2,     2,     2,     2,     2,     2,
-       2,     2,     2,     2,     2,     2,     2,     2,     2,     2,
-       2,     2,     2,     2,     2,     2,     2,     2,     2,     2,
-       2,     2,     2,     2,     2,     2,     2,     2,     2,     2,
-       2,     2,     2,     2,     2,     2,     2,     2,     2,     2,
-       2,     2,     2,     2,     2,     2,     2,     2,     2,     2,
-       2,     2,     2,     2,     2,     2,     2,     2,     2,     2,
-       2,     2,     2,     2,     2,     2,     2,     2,     2,     2,
-       2,     2,     2,     2,     2,     2,     2,     2,     2,     2,
-       2,     2,     2,     2,     2,     2,     2,     2,     2,     2,
-       2,     2,     2,     2,     2,     2,     2,     2,     2,     2,
-       2,     2,     2,     2,     2,     2,     1,     2,     3,     4,
-       5,     6,     7,     8,     9,    10,    11,    12,    13,    14,
-      15,    16,    17,    18,    19,    20,    21,    22
-};
 
-#if YYDEBUG
-/* YYPRHS[YYN] -- Index of the first RHS symbol of rule number YYN in
-   YYRHS.  */
-static const unsigned short yyprhs[] =
-{
-       0,     0,     3,     5,     7,     9,    14,    16,    21,    23,
-      25,    27,    28,    30,    31,    34,    36,    38,    40,    42,
-      46,    51,    53,    58,    62,    66,    71,    76,    83,    90,
-      97,    98,   101,   104,   109,   110,   112,   114,   118,   121,
-     125,   131,   136,   138,   139,   143,   144,   146,   148,   152,
-     157,   160,   167,   168,   171,   173,   177,   179,   184,   186,
-     190,   191,   194,   196,   200,   204,   205,   207,   209,   210,
-     212,   214,   216,   217,   221,   222,   223,   230,   234,   236,
-     238,   243,   245,   249,   250,   255,   260,   263,   265,   268
+
+#define	YYFINAL		162
+#define	YYFLAG		-32768
+#define	YYNTBASE	38
+
+#define YYTRANSLATE(x) ((unsigned)(x) <= 276 ? yytranslate[x] : 79)
+
+static const char yytranslate[] = {     0,
+     2,     2,     2,     2,     2,     2,     2,     2,     2,     2,
+     2,     2,     2,     2,     2,     2,     2,     2,     2,     2,
+     2,     2,     2,     2,     2,     2,     2,     2,     2,     2,
+     2,     2,     2,     2,     2,     2,     2,     2,     2,    32,
+    33,     2,     2,    34,    36,    31,     2,     2,     2,     2,
+     2,     2,     2,     2,     2,     2,     2,    35,    37,    23,
+    25,    24,    26,     2,     2,     2,     2,     2,     2,     2,
+     2,     2,     2,     2,     2,     2,     2,     2,     2,     2,
+     2,     2,     2,     2,     2,     2,     2,     2,     2,     2,
+    29,     2,    30,     2,     2,     2,     2,     2,     2,     2,
+     2,     2,     2,     2,     2,     2,     2,     2,     2,     2,
+     2,     2,     2,     2,     2,     2,     2,     2,     2,     2,
+     2,     2,    27,     2,    28,     2,     2,     2,     2,     2,
+     2,     2,     2,     2,     2,     2,     2,     2,     2,     2,
+     2,     2,     2,     2,     2,     2,     2,     2,     2,     2,
+     2,     2,     2,     2,     2,     2,     2,     2,     2,     2,
+     2,     2,     2,     2,     2,     2,     2,     2,     2,     2,
+     2,     2,     2,     2,     2,     2,     2,     2,     2,     2,
+     2,     2,     2,     2,     2,     2,     2,     2,     2,     2,
+     2,     2,     2,     2,     2,     2,     2,     2,     2,     2,
+     2,     2,     2,     2,     2,     2,     2,     2,     2,     2,
+     2,     2,     2,     2,     2,     2,     2,     2,     2,     2,
+     2,     2,     2,     2,     2,     2,     2,     2,     2,     2,
+     2,     2,     2,     2,     2,     2,     2,     2,     2,     2,
+     2,     2,     2,     2,     2,     2,     2,     2,     2,     2,
+     2,     2,     2,     2,     2,     1,     3,     4,     5,     6,
+     7,     8,     9,    10,    11,    12,    13,    14,    15,    16,
+    17,    18,    19,    20,    21,    22
 };
 
-/* YYRHS -- A `-1'-separated list of the rules' RHS. */
-static const yysigned_char yyrhs[] =
-{
-      78,     0,    -1,    19,    -1,     5,    -1,     4,    -1,     6,
-      23,    18,    24,    -1,     3,    -1,     7,    23,    40,    24,
-      -1,     8,    -1,     9,    -1,    39,    -1,    -1,    12,    -1,
-      -1,    25,    43,    -1,    18,    -1,    21,    -1,    22,    -1,
-      26,    -1,    27,    50,    28,    -1,    19,    23,    51,    24,
-      -1,    19,    -1,    43,    27,    48,    28,    -1,    29,    50,
-      30,    -1,    43,    31,    19,    -1,    32,    19,    46,    33,
-      -1,    43,    29,    48,    30,    -1,    15,    32,    43,    34,
-      43,    33,    -1,    16,    32,    43,    34,    43,    33,    -1,
-      17,    32,    43,    34,    43,    33,    -1,    -1,    35,    20,
-      -1,    43,    44,    -1,    45,    34,    43,    44,    -1,    -1,
-      45,    -1,    18,    -1,    18,    36,    18,    -1,    18,    18,
-      -1,    47,    34,    18,    -1,    47,    34,    18,    36,    18,
-      -1,    47,    34,    18,    18,    -1,    47,    -1,    -1,    27,
-      48,    28,    -1,    -1,    51,    -1,    43,    -1,    51,    34,
-      43,    -1,    41,    40,    19,    42,    -1,    52,    37,    -1,
-      13,    19,    49,    25,    43,    37,    -1,    -1,    54,    53,
-      -1,    37,    -1,    27,    54,    28,    -1,    39,    -1,    39,
-      23,    51,    24,    -1,    56,    -1,    57,    34,    56,    -1,
-      -1,    35,    57,    -1,    52,    -1,    59,    34,    52,    -1,
-      23,    59,    24,    -1,    -1,    60,    -1,    19,    -1,    -1,
-      62,    -1,    63,    -1,    63,    -1,    -1,    58,    67,    55,
-      -1,    -1,    -1,    10,    64,    69,    61,    70,    66,    -1,
-      11,    65,    66,    -1,    68,    -1,    71,    -1,    19,    49,
-      25,    43,    -1,    73,    -1,    74,    34,    73,    -1,    -1,
-      13,    76,    74,    14,    -1,    75,    27,    77,    28,    -1,
-      75,    72,    -1,    72,    -1,    77,    72,    -1,    77,    -1
+#if YYDEBUG != 0
+static const short yyprhs[] = {     0,
+     0,     2,     4,     6,    11,    13,    18,    20,    22,    24,
+    25,    27,    28,    31,    33,    35,    37,    39,    41,    43,
+    47,    52,    57,    61,    65,    70,    75,    82,    89,    96,
+    97,   100,   103,   108,   109,   111,   113,   117,   120,   124,
+   130,   135,   137,   138,   142,   143,   145,   147,   151,   156,
+   159,   166,   167,   170,   172,   176,   178,   183,   185,   189,
+   190,   193,   195,   199,   203,   204,   206,   208,   209,   211,
+   213,   215,   216,   220,   221,   222,   229,   233,   235,   237,
+   242,   244,   248,   249,   254,   259,   262,   264,   267
 };
 
-/* YYRLINE[YYN] -- source line where rule number YYN was defined.  */
-static const unsigned short yyrline[] =
-{
-       0,   223,   223,   234,   236,   238,   240,   242,   244,   246,
-     248,   252,   252,   254,   254,   256,   258,   261,   264,   266,
-     279,   307,   322,   329,   332,   339,   347,   355,   361,   367,
-     375,   378,   382,   387,   393,   396,   399,   402,   415,   429,
-     431,   444,   460,   462,   462,   466,   468,   472,   475,   479,
-     489,   491,   497,   497,   498,   498,   500,   502,   506,   511,
-     516,   519,   523,   526,   531,   532,   532,   534,   534,   536,
-     543,   561,   573,   573,   592,   594,   592,   600,   609,   609,
-     611,   616,   616,   619,   619,   622,   625,   629,   629,   631
+static const short yyrhs[] = {    19,
+     0,     5,     0,     4,     0,     6,    23,    18,    24,     0,
+     3,     0,     7,    23,    39,    24,     0,     8,     0,     9,
+     0,    38,     0,     0,    12,     0,     0,    25,    43,     0,
+    19,     0,    42,     0,    18,     0,    21,     0,    22,     0,
+    26,     0,    27,    50,    28,     0,    19,    23,    51,    24,
+     0,    43,    27,    48,    28,     0,    29,    50,    30,     0,
+    43,    31,    19,     0,    32,    42,    46,    33,     0,    43,
+    29,    48,    30,     0,    15,    32,    43,    34,    43,    33,
+     0,    16,    32,    43,    34,    43,    33,     0,    17,    32,
+    43,    34,    43,    33,     0,     0,    35,    20,     0,    43,
+    44,     0,    45,    34,    43,    44,     0,     0,    45,     0,
+    18,     0,    18,    36,    18,     0,    18,    18,     0,    47,
+    34,    18,     0,    47,    34,    18,    36,    18,     0,    47,
+    34,    18,    18,     0,    47,     0,     0,    27,    48,    28,
+     0,     0,    51,     0,    43,     0,    51,    34,    43,     0,
+    40,    39,    19,    41,     0,    52,    37,     0,    13,    19,
+    49,    25,    43,    37,     0,     0,    54,    53,     0,    37,
+     0,    27,    54,    28,     0,    38,     0,    38,    23,    51,
+    24,     0,    56,     0,    57,    34,    56,     0,     0,    35,
+    57,     0,    52,     0,    59,    34,    52,     0,    23,    59,
+    24,     0,     0,    60,     0,    19,     0,     0,    62,     0,
+    63,     0,    63,     0,     0,    58,    67,    55,     0,     0,
+     0,    10,    64,    69,    61,    70,    66,     0,    11,    65,
+    66,     0,    68,     0,    71,     0,    19,    49,    25,    43,
+     0,    73,     0,    74,    34,    73,     0,     0,    13,    76,
+    74,    14,     0,    75,    27,    77,    28,     0,    75,    72,
+     0,    72,     0,    77,    72,     0,    77,     0
 };
+
 #endif
 
-#if YYDEBUG || YYERROR_VERBOSE
-/* YYTNME[SYMBOL-NUM] -- String name of the symbol SYMBOL-NUM.
-   First, the terminals, then, starting at YYNTOKENS, nonterminals. */
-static const char *const yytname[] =
-{
-  "$end", "error", "$undefined", "INT", "BIT", "STRING", "BITS", "LIST", 
-  "CODE", "DAG", "CLASS", "DEF", "FIELD", "LET", "IN", "SHLTOK", "SRATOK", 
-  "SRLTOK", "INTVAL", "ID", "VARNAME", "STRVAL", "CODEFRAGMENT", "'<'", 
-  "'>'", "'='", "'?'", "'{'", "'}'", "'['", "']'", "'.'", "'('", "')'", 
-  "','", "':'", "'-'", "';'", "$accept", "ClassID", "Type", "OptPrefix", 
-  "OptValue", "Value", "OptVarName", "DagArgListNE", "DagArgList", 
-  "RBitList", "BitList", "OptBitList", "ValueList", "ValueListNE", 
-  "Declaration", "BodyItem", "BodyList", "Body", "SubClassRef", 
-  "ClassListNE", "ClassList", "DeclListNE", "TemplateArgList", 
-  "OptTemplateArgList", "OptID", "ObjectName", "ClassName", "DefName", 
-  "ObjectBody", "@1", "ClassInst", "@2", "@3", "DefInst", "Object", 
-  "LETItem", "LETList", "LETCommand", "@4", "ObjectList", "File", 0
+#if YYDEBUG != 0
+static const short yyrline[] = { 0,
+   223,   234,   236,   238,   240,   242,   244,   246,   248,   252,
+   252,   254,   254,   256,   273,   275,   277,   280,   283,   285,
+   298,   326,   333,   336,   343,   346,   354,   360,   366,   374,
+   377,   381,   386,   392,   395,   398,   401,   414,   428,   430,
+   443,   459,   461,   461,   465,   467,   471,   474,   478,   488,
+   490,   496,   496,   497,   497,   499,   501,   505,   510,   515,
+   518,   522,   525,   530,   531,   531,   533,   533,   535,   542,
+   560,   572,   586,   591,   593,   595,   599,   608,   608,   610,
+   615,   615,   618,   618,   621,   624,   628,   628,   630
 };
 #endif
 
-# ifdef YYPRINT
-/* YYTOKNUM[YYLEX-NUM] -- Internal token number corresponding to
-   token YYLEX-NUM.  */
-static const unsigned short yytoknum[] =
-{
-       0,   256,   257,   258,   259,   260,   261,   262,   263,   264,
-     265,   266,   267,   268,   269,   270,   271,   272,   273,   274,
-     275,   276,   277,    60,    62,    61,    63,   123,   125,    91,
-      93,    46,    40,    41,    44,    58,    45,    59
-};
-# endif
 
-/* YYR1[YYN] -- Symbol number of symbol that rule YYN derives.  */
-static const unsigned char yyr1[] =
-{
-       0,    38,    39,    40,    40,    40,    40,    40,    40,    40,
-      40,    41,    41,    42,    42,    43,    43,    43,    43,    43,
-      43,    43,    43,    43,    43,    43,    43,    43,    43,    43,
-      44,    44,    45,    45,    46,    46,    47,    47,    47,    47,
-      47,    47,    48,    49,    49,    50,    50,    51,    51,    52,
-      53,    53,    54,    54,    55,    55,    56,    56,    57,    57,
-      58,    58,    59,    59,    60,    61,    61,    62,    62,    63,
-      64,    65,    67,    66,    69,    70,    68,    71,    72,    72,
-      73,    74,    74,    76,    75,    72,    72,    77,    77,    78
+#if YYDEBUG != 0 || defined (YYERROR_VERBOSE)
+
+static const char * const yytname[] = {   "$","error","$undefined.","INT","BIT",
+"STRING","BITS","LIST","CODE","DAG","CLASS","DEF","FIELD","LET","IN","SHLTOK",
+"SRATOK","SRLTOK","INTVAL","ID","VARNAME","STRVAL","CODEFRAGMENT","'<'","'>'",
+"'='","'?'","'{'","'}'","'['","']'","'.'","'('","')'","','","':'","'-'","';'",
+"ClassID","Type","OptPrefix","OptValue","IDValue","Value","OptVarName","DagArgListNE",
+"DagArgList","RBitList","BitList","OptBitList","ValueList","ValueListNE","Declaration",
+"BodyItem","BodyList","Body","SubClassRef","ClassListNE","ClassList","DeclListNE",
+"TemplateArgList","OptTemplateArgList","OptID","ObjectName","ClassName","DefName",
+"ObjectBody","@1","ClassInst","@2","@3","DefInst","Object","LETItem","LETList",
+"LETCommand","@4","ObjectList","File", NULL
 };
+#endif
 
-/* YYR2[YYN] -- Number of symbols composing right hand side of rule YYN.  */
-static const unsigned char yyr2[] =
-{
-       0,     2,     1,     1,     1,     4,     1,     4,     1,     1,
-       1,     0,     1,     0,     2,     1,     1,     1,     1,     3,
-       4,     1,     4,     3,     3,     4,     4,     6,     6,     6,
-       0,     2,     2,     4,     0,     1,     1,     3,     2,     3,
-       5,     4,     1,     0,     3,     0,     1,     1,     3,     4,
-       2,     6,     0,     2,     1,     3,     1,     4,     1,     3,
-       0,     2,     1,     3,     3,     0,     1,     1,     0,     1,
-       1,     1,     0,     3,     0,     0,     6,     3,     1,     1,
-       4,     1,     3,     0,     4,     4,     2,     1,     2,     1
+static const short yyr1[] = {     0,
+    38,    39,    39,    39,    39,    39,    39,    39,    39,    40,
+    40,    41,    41,    42,    43,    43,    43,    43,    43,    43,
+    43,    43,    43,    43,    43,    43,    43,    43,    43,    44,
+    44,    45,    45,    46,    46,    47,    47,    47,    47,    47,
+    47,    48,    49,    49,    50,    50,    51,    51,    52,    53,
+    53,    54,    54,    55,    55,    56,    56,    57,    57,    58,
+    58,    59,    59,    60,    61,    61,    62,    62,    63,    64,
+    65,    67,    66,    69,    70,    68,    71,    72,    72,    73,
+    74,    74,    76,    75,    72,    72,    77,    77,    78
 };
 
-/* YYDEFACT[STATE-NAME] -- Default rule to reduce with in state
-   STATE-NUM when YYTABLE doesn't specify something else to do.  Zero
-   means the default is an error.  */
-static const unsigned char yydefact[] =
-{
-       0,    68,    68,    83,    78,    79,    87,     0,    89,     0,
-      67,    69,    70,    74,    71,    60,     0,     0,    86,    88,
-       1,    65,     0,    72,    77,    43,    81,     0,     0,    11,
-      66,    75,     2,    56,    58,    61,     0,     0,     0,    84,
-       0,    85,    12,     0,    62,     0,    60,     0,     0,    52,
-      54,    73,    36,    42,     0,     0,    82,     6,     4,     3,
-       0,     0,     8,     9,    10,     0,    64,    11,    76,     0,
-       0,     0,    15,    21,    16,    17,    18,    45,    45,     0,
-      47,     0,    59,    11,    38,     0,     0,    44,    80,     0,
-       0,    13,    63,     0,     0,     0,     0,     0,    46,     0,
-      34,     0,     0,     0,    57,     0,     0,    55,     0,    53,
-      37,    39,     0,     0,     0,    49,     0,     0,     0,     0,
-      19,    23,    30,    35,     0,     0,     0,    24,    48,    43,
-      50,    41,     0,     5,     7,    14,     0,     0,     0,    20,
-       0,    32,     0,    25,    22,    26,     0,    40,     0,     0,
-       0,    31,    30,     0,    27,    28,    29,    33,     0,    51
+static const short yyr2[] = {     0,
+     1,     1,     1,     4,     1,     4,     1,     1,     1,     0,
+     1,     0,     2,     1,     1,     1,     1,     1,     1,     3,
+     4,     4,     3,     3,     4,     4,     6,     6,     6,     0,
+     2,     2,     4,     0,     1,     1,     3,     2,     3,     5,
+     4,     1,     0,     3,     0,     1,     1,     3,     4,     2,
+     6,     0,     2,     1,     3,     1,     4,     1,     3,     0,
+     2,     1,     3,     3,     0,     1,     1,     0,     1,     1,
+     1,     0,     3,     0,     0,     6,     3,     1,     1,     4,
+     1,     3,     0,     4,     4,     2,     1,     2,     1
 };
 
-/* YYDEFGOTO[NTERM-NUM]. */
-static const short yydefgoto[] =
-{
-      -1,    33,    65,    43,   115,    80,   141,   123,   124,    53,
-      54,    38,    97,    98,    44,   109,    83,    51,    34,    35,
-      23,    45,    30,    31,    11,    12,    13,    15,    24,    36,
-       4,    21,    46,     5,     6,    26,    27,     7,    16,     8,
-       9
+static const short yydefact[] = {     0,
+    68,    68,    83,    78,    79,    87,     0,    89,    67,    69,
+    70,    74,    71,    60,     0,     0,    86,    88,    65,     0,
+    72,    77,    43,    81,     0,     0,    10,    66,    75,     1,
+    56,    58,    61,     0,     0,     0,    84,     0,    85,    11,
+     0,    62,     0,    60,     0,     0,    52,    54,    73,    36,
+    42,     0,     0,    82,     5,     3,     2,     0,     0,     7,
+     8,     9,     0,    64,    10,    76,     0,     0,     0,    16,
+    14,    17,    18,    19,    45,    45,     0,    15,    47,     0,
+    59,    10,    38,     0,     0,    44,    80,     0,     0,    12,
+    63,     0,     0,     0,     0,     0,    46,     0,    14,    34,
+     0,     0,     0,    57,     0,     0,    55,     0,    53,    37,
+    39,     0,     0,     0,    49,     0,     0,     0,     0,    20,
+    23,    30,    35,     0,     0,     0,    24,    48,    43,    50,
+    41,     0,     4,     6,    13,     0,     0,     0,    21,     0,
+    32,     0,    25,    22,    26,     0,    40,     0,     0,     0,
+    31,    30,     0,    27,    28,    29,    33,     0,    51,     0,
+     0,     0
 };
 
-/* YYPACT[STATE-NUM] -- Index in YYTABLE of the portion describing
-   STATE-NUM.  */
-#define YYPACT_NINF -82
-static const yysigned_char yypact[] =
-{
-     114,   -12,   -12,   -82,   -82,   -82,   -82,     4,   114,    16,
-     -82,   -82,   -82,   -82,   -82,    -3,    10,   114,   -82,   -82,
-     -82,    12,    17,   -82,   -82,    14,   -82,    -9,    -2,    35,
-     -82,   -82,   -82,    26,   -82,    28,   -14,    46,    42,   -82,
-      10,   -82,   -82,    69,   -82,     3,    -3,    39,    17,   -82,
-     -82,   -82,    -8,    36,    41,    39,   -82,   -82,   -82,   -82,
-      56,    57,   -82,   -82,   -82,    66,   -82,    35,   -82,    52,
-      54,    58,   -82,    72,   -82,   -82,   -82,    39,    39,    87,
-      91,     9,   -82,     6,   -82,   108,   110,   -82,    91,   111,
-      69,   105,   -82,    39,    39,    39,    39,   103,    98,   104,
-      39,    46,    46,   116,   -82,    39,   117,   -82,    96,   -82,
-     -82,    -6,   113,   115,    39,   -82,    65,    73,    74,    29,
-     -82,   -82,    62,   106,   109,   118,   119,   -82,    91,    14,
-     -82,   -82,   120,   -82,   -82,    91,    39,    39,    39,   -82,
-     121,   -82,    39,   -82,   -82,   -82,   122,   -82,    82,    83,
-      90,   -82,    62,    39,   -82,   -82,   -82,   -82,    15,   -82
+static const short yydefgoto[] = {    31,
+    63,    41,   115,    78,    79,   141,   123,   124,    51,    52,
+    36,    96,    97,    42,   109,    82,    49,    32,    33,    21,
+    43,    28,    29,    10,    11,    12,    14,    22,    34,     4,
+    19,    44,     5,     6,    24,    25,     7,    15,     8,   160
 };
 
-/* YYPGOTO[NTERM-NUM].  */
-static const short yypgoto[] =
-{
-     -82,   -42,    53,   -82,   -82,   -55,    -7,   -82,   -82,   -82,
-     -81,    19,    75,   -45,   -61,   -82,   -82,   -82,   102,   -82,
-     -82,   -82,   -82,   -82,   -82,   142,   -82,   -82,   112,   -82,
-     -82,   -82,   -82,   -82,    -4,   123,   -82,   -82,   -82,   134,
-     -82
+static const short yypact[] = {     5,
+     7,     7,-32768,-32768,-32768,-32768,     1,     5,-32768,-32768,
+-32768,-32768,-32768,   -18,    25,     5,-32768,-32768,    23,    30,
+-32768,-32768,    44,-32768,   -11,    -3,    60,-32768,-32768,-32768,
+    54,-32768,    40,    -8,    63,    62,-32768,    25,-32768,-32768,
+    50,-32768,    39,   -18,    16,    30,-32768,-32768,-32768,   -14,
+    45,    65,    16,-32768,-32768,-32768,-32768,    68,    74,-32768,
+-32768,-32768,    80,-32768,    60,-32768,    87,    91,    92,-32768,
+    98,-32768,-32768,-32768,    16,    16,   106,-32768,    76,    41,
+-32768,     8,-32768,   108,   109,-32768,    76,   110,    50,   104,
+-32768,    16,    16,    16,    16,   102,    97,   103,-32768,    16,
+    63,    63,   113,-32768,    16,   115,-32768,    99,-32768,-32768,
+    -9,   111,   114,    16,-32768,    61,    67,    75,    42,-32768,
+-32768,    51,   105,   107,   116,   112,-32768,    76,    44,-32768,
+-32768,   119,-32768,-32768,    76,    16,    16,    16,-32768,   121,
+-32768,    16,-32768,-32768,-32768,   118,-32768,    81,    84,    89,
+-32768,    51,    16,-32768,-32768,-32768,-32768,    33,-32768,   145,
+   146,-32768
 };
 
-/* YYTABLE[YYPACT[STATE-NUM]].  What to do in state STATE-NUM.  If
-   positive, shift that token.  If negative, reduce the rule which
-   number is the opposite.  If zero, do what YYDEFACT says.
-   If YYTABLE_NINF, syntax error.  */
-#define YYTABLE_NINF -1
-static const unsigned char yytable[] =
-{
-      88,    64,    81,    18,    19,    39,    92,    10,     1,     2,
-      84,     3,   131,    49,     1,     2,    20,     3,    42,   106,
-     125,   126,   108,    50,    19,    40,    41,    66,    85,    25,
-     132,    17,    22,   104,   107,    29,    32,    67,   116,   117,
-     118,    37,   101,   105,   102,   122,   103,    42,    64,    47,
-     128,   119,   159,   139,    69,    70,    71,    72,    73,   135,
-      74,    75,    48,   105,    52,    76,    77,    55,    78,    87,
-      86,    79,    57,    58,    59,    60,    61,    62,    63,    89,
-      90,   148,   149,   150,    93,    91,    94,   152,    32,   101,
-      95,   102,   101,   103,   102,    96,   103,   140,   158,   136,
-     101,   101,   102,   102,   103,   103,   100,   137,   138,   101,
-     101,   102,   102,   103,   103,   154,   155,   101,   101,   102,
-     102,   103,   103,   156,     1,     2,   110,     3,   111,   112,
-     114,   120,   105,   130,   121,   127,   129,   133,   147,   134,
-     142,   151,   143,   113,    14,   157,   144,   153,   146,   145,
-      82,    28,     0,    99,     0,     0,     0,     0,    68,     0,
-       0,     0,     0,    56
+static const short yypgoto[] = {   -39,
+    58,-32768,-32768,    71,   -53,    -1,-32768,-32768,-32768,   -34,
+    20,    77,   -44,   -52,-32768,-32768,-32768,   117,-32768,-32768,
+-32768,-32768,-32768,-32768,   148,-32768,-32768,   120,-32768,-32768,
+-32768,-32768,-32768,    -2,   122,-32768,-32768,-32768,   136,-32768
 };
 
-static const short yycheck[] =
-{
-      55,    43,    47,     7,     8,    14,    67,    19,    10,    11,
-      18,    13,    18,    27,    10,    11,     0,    13,    12,    13,
-     101,   102,    83,    37,    28,    34,    28,    24,    36,    19,
-      36,    27,    35,    24,    28,    23,    19,    34,    93,    94,
-      95,    27,    27,    34,    29,   100,    31,    12,    90,    23,
-     105,    96,    37,    24,    15,    16,    17,    18,    19,   114,
-      21,    22,    34,    34,    18,    26,    27,    25,    29,    28,
-      34,    32,     3,     4,     5,     6,     7,     8,     9,    23,
-      23,   136,   137,   138,    32,    19,    32,   142,    19,    27,
-      32,    29,    27,    31,    29,    23,    31,    35,   153,    34,
-      27,    27,    29,    29,    31,    31,    19,    34,    34,    27,
-      27,    29,    29,    31,    31,    33,    33,    27,    27,    29,
-      29,    31,    31,    33,    10,    11,    18,    13,    18,    18,
-      25,    28,    34,    37,    30,    19,    19,    24,    18,    24,
-      34,    20,    33,    90,     2,   152,    28,    25,   129,    30,
-      48,    17,    -1,    78,    -1,    -1,    -1,    -1,    46,    -1,
-      -1,    -1,    -1,    40
+
+#define	YYLAST		164
+
+
+static const short yytable[] = {    87,
+    80,    62,    37,    83,    17,    18,     1,     2,   131,     3,
+     1,     2,    91,     3,     1,     2,    20,     3,    47,    40,
+   106,    84,    38,    18,    39,     9,   132,    16,    48,   108,
+    67,    68,    69,    70,    71,   107,    72,    73,   116,   117,
+   118,    74,    75,    23,    76,    27,   122,    77,    30,    62,
+   119,   128,    55,    56,    57,    58,    59,    60,    61,   101,
+   135,   102,    64,   103,   104,   139,   125,   126,    30,   159,
+    35,    40,    65,    46,   105,   105,    45,   101,    85,   102,
+    50,   103,   148,   149,   150,   140,    53,   101,   152,   102,
+    88,   103,    86,   101,   136,   102,    89,   103,    90,   158,
+   137,   101,   101,   102,   102,   103,   103,   101,   138,   102,
+   101,   103,   102,   154,   103,   101,   155,   102,    92,   103,
+    95,   156,    93,    94,    99,   110,   111,   112,   114,   120,
+   105,   127,   121,   129,   133,   130,   147,   134,   142,   143,
+   151,   145,   153,   144,   161,   162,   113,   100,   146,    13,
+   157,    26,    98,     0,     0,     0,     0,     0,     0,    54,
+     0,     0,    81,    66
 };
 
-/* YYSTOS[STATE-NUM] -- The (internal number of the) accessing
-   symbol of state STATE-NUM.  */
-static const unsigned char yystos[] =
-{
-       0,    10,    11,    13,    68,    71,    72,    75,    77,    78,
-      19,    62,    63,    64,    63,    65,    76,    27,    72,    72,
-       0,    69,    35,    58,    66,    19,    73,    74,    77,    23,
-      60,    61,    19,    39,    56,    57,    67,    27,    49,    14,
-      34,    28,    12,    41,    52,    59,    70,    23,    34,    27,
-      37,    55,    18,    47,    48,    25,    73,     3,     4,     5,
-       6,     7,     8,     9,    39,    40,    24,    34,    66,    15,
-      16,    17,    18,    19,    21,    22,    26,    27,    29,    32,
-      43,    51,    56,    54,    18,    36,    34,    28,    43,    23,
-      23,    19,    52,    32,    32,    32,    23,    50,    51,    50,
-      19,    27,    29,    31,    24,    34,    13,    28,    52,    53,
-      18,    18,    18,    40,    25,    42,    43,    43,    43,    51,
-      28,    30,    43,    45,    46,    48,    48,    19,    43,    19,
-      37,    18,    36,    24,    24,    43,    34,    34,    34,    24,
-      35,    44,    34,    33,    28,    30,    49,    18,    43,    43,
-      43,    20,    43,    25,    33,    33,    33,    44,    43,    37
+static const short yycheck[] = {    53,
+    45,    41,    14,    18,     7,     8,    10,    11,    18,    13,
+    10,    11,    65,    13,    10,    11,    35,    13,    27,    12,
+    13,    36,    34,    26,    28,    19,    36,    27,    37,    82,
+    15,    16,    17,    18,    19,    28,    21,    22,    92,    93,
+    94,    26,    27,    19,    29,    23,   100,    32,    19,    89,
+    95,   105,     3,     4,     5,     6,     7,     8,     9,    27,
+   114,    29,    24,    31,    24,    24,   101,   102,    19,    37,
+    27,    12,    34,    34,    34,    34,    23,    27,    34,    29,
+    18,    31,   136,   137,   138,    35,    25,    27,   142,    29,
+    23,    31,    28,    27,    34,    29,    23,    31,    19,   153,
+    34,    27,    27,    29,    29,    31,    31,    27,    34,    29,
+    27,    31,    29,    33,    31,    27,    33,    29,    32,    31,
+    23,    33,    32,    32,    19,    18,    18,    18,    25,    28,
+    34,    19,    30,    19,    24,    37,    18,    24,    34,    33,
+    20,    30,    25,    28,     0,     0,    89,    77,   129,     2,
+   152,    16,    76,    -1,    -1,    -1,    -1,    -1,    -1,    38,
+    -1,    -1,    46,    44
 };
+/* -*-C-*-  Note some compilers choke on comments on `#line' lines.  */
+#line 3 "/usr/share/bison.simple"
+/* This file comes from bison-1.28.  */
 
-#if ! defined (YYSIZE_T) && defined (__SIZE_TYPE__)
-# define YYSIZE_T __SIZE_TYPE__
-#endif
-#if ! defined (YYSIZE_T) && defined (size_t)
-# define YYSIZE_T size_t
-#endif
-#if ! defined (YYSIZE_T)
-# if defined (__STDC__) || defined (__cplusplus)
-#  include <stddef.h> /* INFRINGES ON USER NAME SPACE */
-#  define YYSIZE_T size_t
-# endif
-#endif
-#if ! defined (YYSIZE_T)
-# define YYSIZE_T unsigned int
+/* Skeleton output parser for bison,
+   Copyright (C) 1984, 1989, 1990 Free Software Foundation, Inc.
+
+   This program is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 2, or (at your option)
+   any later version.
+
+   This program is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
+
+   You should have received a copy of the GNU General Public License
+   along with this program; if not, write to the Free Software
+   Foundation, Inc., 59 Temple Place - Suite 330,
+   Boston, MA 02111-1307, USA.  */
+
+/* As a special exception, when this file is copied by Bison into a
+   Bison output file, you may use that output file without restriction.
+   This special exception was added by the Free Software Foundation
+   in version 1.24 of Bison.  */
+
+/* This is the parser code that is written into each bison parser
+  when the %semantic_parser declaration is not specified in the grammar.
+  It was written by Richard Stallman by simplifying the hairy parser
+  used when %semantic_parser is specified.  */
+
+#ifndef YYSTACK_USE_ALLOCA
+#ifdef alloca
+#define YYSTACK_USE_ALLOCA
+#else /* alloca not defined */
+#ifdef __GNUC__
+#define YYSTACK_USE_ALLOCA
+#define alloca __builtin_alloca
+#else /* not GNU C.  */
+#if (!defined (__STDC__) && defined (sparc)) || defined (__sparc__) || defined (__sparc) || defined (__sgi) || (defined (__sun) && defined (__i386))
+#define YYSTACK_USE_ALLOCA
+#include <alloca.h>
+#else /* not sparc */
+/* We think this test detects Watcom and Microsoft C.  */
+/* This used to test MSDOS, but that is a bad idea
+   since that symbol is in the user namespace.  */
+#if (defined (_MSDOS) || defined (_MSDOS_)) && !defined (__TURBOC__)
+#if 0 /* No need for malloc.h, which pollutes the namespace;
+	 instead, just don't use alloca.  */
+#include <malloc.h>
+#endif
+#else /* not MSDOS, or __TURBOC__ */
+#if defined(_AIX)
+/* I don't know what this was needed for, but it pollutes the namespace.
+   So I turned it off.   rms, 2 May 1997.  */
+/* #include <malloc.h>  */
+ #pragma alloca
+#define YYSTACK_USE_ALLOCA
+#else /* not MSDOS, or __TURBOC__, or _AIX */
+#if 0
+#ifdef __hpux /* haible at ilog.fr says this works for HPUX 9.05 and up,
+		 and on HPUX 10.  Eventually we can turn this on.  */
+#define YYSTACK_USE_ALLOCA
+#define alloca __builtin_alloca
+#endif /* __hpux */
+#endif
+#endif /* not _AIX */
+#endif /* not MSDOS, or __TURBOC__ */
+#endif /* not sparc */
+#endif /* not GNU C */
+#endif /* alloca not defined */
+#endif /* YYSTACK_USE_ALLOCA not defined */
+
+#ifdef YYSTACK_USE_ALLOCA
+#define YYSTACK_ALLOC alloca
+#else
+#define YYSTACK_ALLOC malloc
 #endif
 
+/* Note: there must be only one dollar sign in this file.
+   It is replaced by the list of actions, each action
+   as one case of the switch.  */
+
 #define yyerrok		(yyerrstatus = 0)
 #define yyclearin	(yychar = YYEMPTY)
-#define YYEMPTY		(-2)
+#define YYEMPTY		-2
 #define YYEOF		0
-
 #define YYACCEPT	goto yyacceptlab
-#define YYABORT		goto yyabortlab
+#define YYABORT 	goto yyabortlab
 #define YYERROR		goto yyerrlab1
-
-
-/* Like YYERROR except do call yyerror.  This remains here temporarily
-   to ease the transition to the new meaning of YYERROR, for GCC.
+/* Like YYERROR except do call yyerror.
+   This remains here temporarily to ease the
+   transition to the new meaning of YYERROR, for GCC.
    Once GCC version 2 has supplanted version 1, this can go.  */
-
 #define YYFAIL		goto yyerrlab
-
 #define YYRECOVERING()  (!!yyerrstatus)
-
-#define YYBACKUP(Token, Value)					\
+#define YYBACKUP(token, value) \
 do								\
   if (yychar == YYEMPTY && yylen == 1)				\
-    {								\
-      yychar = (Token);						\
-      yylval = (Value);						\
-      yytoken = YYTRANSLATE (yychar);				\
+    { yychar = (token), yylval = (value);			\
+      yychar1 = YYTRANSLATE (yychar);				\
       YYPOPSTACK;						\
       goto yybackup;						\
     }								\
   else								\
-    { 								\
-      yyerror ("syntax error: cannot back up");\
-      YYERROR;							\
-    }								\
+    { yyerror ("syntax error: cannot back up"); YYERROR; }	\
 while (0)
 
 #define YYTERROR	1
 #define YYERRCODE	256
 
-/* YYLLOC_DEFAULT -- Compute the default location (before the actions
-   are run).  */
-
-#ifndef YYLLOC_DEFAULT
-# define YYLLOC_DEFAULT(Current, Rhs, N)         \
-  Current.first_line   = Rhs[1].first_line;      \
-  Current.first_column = Rhs[1].first_column;    \
-  Current.last_line    = Rhs[N].last_line;       \
-  Current.last_column  = Rhs[N].last_column;
+#ifndef YYPURE
+#define YYLEX		yylex()
 #endif
 
-/* YYLEX -- calling `yylex' with the right arguments.  */
-
+#ifdef YYPURE
+#ifdef YYLSP_NEEDED
 #ifdef YYLEX_PARAM
-# define YYLEX yylex (YYLEX_PARAM)
+#define YYLEX		yylex(&yylval, &yylloc, YYLEX_PARAM)
 #else
-# define YYLEX yylex ()
+#define YYLEX		yylex(&yylval, &yylloc)
 #endif
-
-/* Enable debugging if requested.  */
-#if YYDEBUG
-
-# ifndef YYFPRINTF
-#  include <stdio.h> /* INFRINGES ON USER NAME SPACE */
-#  define YYFPRINTF fprintf
-# endif
-
-# define YYDPRINTF(Args)			\
-do {						\
-  if (yydebug)					\
-    YYFPRINTF Args;				\
-} while (0)
-
-# define YYDSYMPRINT(Args)			\
-do {						\
-  if (yydebug)					\
-    yysymprint Args;				\
-} while (0)
-
-# define YYDSYMPRINTF(Title, Token, Value, Location)		\
-do {								\
-  if (yydebug)							\
-    {								\
-      YYFPRINTF (stderr, "%s ", Title);				\
-      yysymprint (stderr, 					\
-                  Token, Value);	\
-      YYFPRINTF (stderr, "\n");					\
-    }								\
-} while (0)
-
-/*------------------------------------------------------------------.
-| yy_stack_print -- Print the state stack from its BOTTOM up to its |
-| TOP (cinluded).                                                   |
-`------------------------------------------------------------------*/
-
-#if defined (__STDC__) || defined (__cplusplus)
-static void
-yy_stack_print (short *bottom, short *top)
+#else /* not YYLSP_NEEDED */
+#ifdef YYLEX_PARAM
+#define YYLEX		yylex(&yylval, YYLEX_PARAM)
 #else
-static void
-yy_stack_print (bottom, top)
-    short *bottom;
-    short *top;
+#define YYLEX		yylex(&yylval)
+#endif
+#endif /* not YYLSP_NEEDED */
 #endif
-{
-  YYFPRINTF (stderr, "Stack now");
-  for (/* Nothing. */; bottom <= top; ++bottom)
-    YYFPRINTF (stderr, " %d", *bottom);
-  YYFPRINTF (stderr, "\n");
-}
 
-# define YY_STACK_PRINT(Bottom, Top)				\
-do {								\
-  if (yydebug)							\
-    yy_stack_print ((Bottom), (Top));				\
-} while (0)
+/* If nonreentrant, generate the variables here */
 
+#ifndef YYPURE
 
-/*------------------------------------------------.
-| Report that the YYRULE is going to be reduced.  |
-`------------------------------------------------*/
+int	yychar;			/*  the lookahead symbol		*/
+YYSTYPE	yylval;			/*  the semantic value of the		*/
+				/*  lookahead symbol			*/
 
-#if defined (__STDC__) || defined (__cplusplus)
-static void
-yy_reduce_print (int yyrule)
-#else
-static void
-yy_reduce_print (yyrule)
-    int yyrule;
+#ifdef YYLSP_NEEDED
+YYLTYPE yylloc;			/*  location data for the lookahead	*/
+				/*  symbol				*/
 #endif
-{
-  int yyi;
-  unsigned int yylineno = yyrline[yyrule];
-  YYFPRINTF (stderr, "Reducing stack by rule %d (line %u), ",
-             yyrule - 1, yylineno);
-  /* Print the symbols being reduced, and their result.  */
-  for (yyi = yyprhs[yyrule]; 0 <= yyrhs[yyi]; yyi++)
-    YYFPRINTF (stderr, "%s ", yytname [yyrhs[yyi]]);
-  YYFPRINTF (stderr, "-> %s\n", yytname [yyr1[yyrule]]);
-}
 
-# define YY_REDUCE_PRINT(Rule)		\
-do {					\
-  if (yydebug)				\
-    yy_reduce_print (Rule);		\
-} while (0)
-
-/* Nonzero means print parse trace.  It is left uninitialized so that
-   multiple parsers can coexist.  */
-int yydebug;
-#else /* !YYDEBUG */
-# define YYDPRINTF(Args)
-# define YYDSYMPRINT(Args)
-# define YYDSYMPRINTF(Title, Token, Value, Location)
-# define YY_STACK_PRINT(Bottom, Top)
-# define YY_REDUCE_PRINT(Rule)
-#endif /* !YYDEBUG */
+int yynerrs;			/*  number of parse errors so far       */
+#endif  /* not YYPURE */
 
+#if YYDEBUG != 0
+int yydebug;			/*  nonzero means print parse trace	*/
+/* Since this is uninitialized, it does not stop multiple parsers
+   from coexisting.  */
+#endif
+
+/*  YYINITDEPTH indicates the initial size of the parser's stacks	*/
 
-/* YYINITDEPTH -- initial size of the parser's stacks.  */
 #ifndef	YYINITDEPTH
-# define YYINITDEPTH 200
+#define YYINITDEPTH 200
 #endif
 
-/* YYMAXDEPTH -- maximum size the stacks can grow to (effective only
-   if the built-in stack extension method is used).
-
-   Do not make this value too large; the results are undefined if
-   SIZE_MAX < YYSTACK_BYTES (YYMAXDEPTH)
-   evaluated with infinite-precision integer arithmetic.  */
+/*  YYMAXDEPTH is the maximum size the stacks can grow to
+    (effective only if the built-in stack extension method is used).  */
 
 #if YYMAXDEPTH == 0
-# undef YYMAXDEPTH
+#undef YYMAXDEPTH
 #endif
 
 #ifndef YYMAXDEPTH
-# define YYMAXDEPTH 10000
+#define YYMAXDEPTH 10000
 #endif
-
 
+/* Define __yy_memcpy.  Note that the size argument
+   should be passed with type unsigned int, because that is what the non-GCC
+   definitions require.  With GCC, __builtin_memcpy takes an arg
+   of type size_t, but it can handle unsigned int.  */
+
+#if __GNUC__ > 1		/* GNU C and GNU C++ define this.  */
+#define __yy_memcpy(TO,FROM,COUNT)	__builtin_memcpy(TO,FROM,COUNT)
+#else				/* not GNU C or C++ */
+#ifndef __cplusplus
 
-#if YYERROR_VERBOSE
-
-# ifndef yystrlen
-#  if defined (__GLIBC__) && defined (_STRING_H)
-#   define yystrlen strlen
-#  else
-/* Return the length of YYSTR.  */
-static YYSIZE_T
-#   if defined (__STDC__) || defined (__cplusplus)
-yystrlen (const char *yystr)
-#   else
-yystrlen (yystr)
-     const char *yystr;
-#   endif
-{
-  register const char *yys = yystr;
-
-  while (*yys++ != '\0')
-    continue;
-
-  return yys - yystr - 1;
-}
-#  endif
-# endif
-
-# ifndef yystpcpy
-#  if defined (__GLIBC__) && defined (_STRING_H) && defined (_GNU_SOURCE)
-#   define yystpcpy stpcpy
-#  else
-/* Copy YYSRC to YYDEST, returning the address of the terminating '\0' in
-   YYDEST.  */
-static char *
-#   if defined (__STDC__) || defined (__cplusplus)
-yystpcpy (char *yydest, const char *yysrc)
-#   else
-yystpcpy (yydest, yysrc)
-     char *yydest;
-     const char *yysrc;
-#   endif
-{
-  register char *yyd = yydest;
-  register const char *yys = yysrc;
-
-  while ((*yyd++ = *yys++) != '\0')
-    continue;
+/* This is the most reliable way to avoid incompatibilities
+   in available built-in functions on various systems.  */
+static void
+__yy_memcpy (to, from, count)
+     char *to;
+     char *from;
+     unsigned int count;
+{
+  register char *f = from;
+  register char *t = to;
+  register int i = count;
 
-  return yyd - 1;
+  while (i-- > 0)
+    *t++ = *f++;
 }
-#  endif
-# endif
-
-#endif /* !YYERROR_VERBOSE */
 
-
-
-#if YYDEBUG
-/*--------------------------------.
-| Print this symbol on YYOUTPUT.  |
-`--------------------------------*/
+#else /* __cplusplus */
 
-#if defined (__STDC__) || defined (__cplusplus)
-static void
-yysymprint (FILE *yyoutput, int yytype, YYSTYPE *yyvaluep)
-#else
+/* This is the most reliable way to avoid incompatibilities
+   in available built-in functions on various systems.  */
 static void
-yysymprint (yyoutput, yytype, yyvaluep)
-    FILE *yyoutput;
-    int yytype;
-    YYSTYPE *yyvaluep;
-#endif
+__yy_memcpy (char *to, char *from, unsigned int count)
 {
-  /* Pacify ``unused variable'' warnings.  */
-  (void) yyvaluep;
+  register char *t = to;
+  register char *f = from;
+  register int i = count;
 
-  if (yytype < YYNTOKENS)
-    {
-      YYFPRINTF (yyoutput, "token %s (", yytname[yytype]);
-# ifdef YYPRINT
-      YYPRINT (yyoutput, yytoknum[yytype], *yyvaluep);
-# endif
-    }
-  else
-    YYFPRINTF (yyoutput, "nterm %s (", yytname[yytype]);
-
-  switch (yytype)
-    {
-      default:
-        break;
-    }
-  YYFPRINTF (yyoutput, ")");
+  while (i-- > 0)
+    *t++ = *f++;
 }
 
-#endif /* ! YYDEBUG */
-/*-----------------------------------------------.
-| Release the memory associated to this symbol.  |
-`-----------------------------------------------*/
-
-#if defined (__STDC__) || defined (__cplusplus)
-static void
-yydestruct (int yytype, YYSTYPE *yyvaluep)
-#else
-static void
-yydestruct (yytype, yyvaluep)
-    int yytype;
-    YYSTYPE *yyvaluep;
 #endif
-{
-  /* Pacify ``unused variable'' warnings.  */
-  (void) yyvaluep;
-
-  switch (yytype)
-    {
-
-      default:
-        break;
-    }
-}
+#endif
 
+#line 217 "/usr/share/bison.simple"
 
-/* Prevent warnings from -Wmissing-prototypes.  */
+/* The user can define YYPARSE_PARAM as the name of an argument to be passed
+   into yyparse.  The argument should have type void *.
+   It should actually point to an object.
+   Grammar actions can access the variable by casting it
+   to the proper pointer type.  */
 
 #ifdef YYPARSE_PARAM
-# if defined (__STDC__) || defined (__cplusplus)
-int yyparse (void *YYPARSE_PARAM);
-# else
-int yyparse ();
-# endif
-#else /* ! YYPARSE_PARAM */
-#if defined (__STDC__) || defined (__cplusplus)
-int yyparse (void);
-#else
-int yyparse ();
-#endif
-#endif /* ! YYPARSE_PARAM */
-
-
-
-/* The lookahead symbol.  */
-int yychar;
-
-/* The semantic value of the lookahead symbol.  */
-YYSTYPE yylval;
-
-/* Number of syntax errors so far.  */
-int yynerrs;
-
-
-
-/*----------.
-| yyparse.  |
-`----------*/
+#ifdef __cplusplus
+#define YYPARSE_PARAM_ARG void *YYPARSE_PARAM
+#define YYPARSE_PARAM_DECL
+#else /* not __cplusplus */
+#define YYPARSE_PARAM_ARG YYPARSE_PARAM
+#define YYPARSE_PARAM_DECL void *YYPARSE_PARAM;
+#endif /* not __cplusplus */
+#else /* not YYPARSE_PARAM */
+#define YYPARSE_PARAM_ARG
+#define YYPARSE_PARAM_DECL
+#endif /* not YYPARSE_PARAM */
 
+/* Prevent warning if -Wstrict-prototypes.  */
+#ifdef __GNUC__
 #ifdef YYPARSE_PARAM
-# if defined (__STDC__) || defined (__cplusplus)
-int yyparse (void *YYPARSE_PARAM)
-# else
-int yyparse (YYPARSE_PARAM)
-  void *YYPARSE_PARAM;
-# endif
-#else /* ! YYPARSE_PARAM */
-#if defined (__STDC__) || defined (__cplusplus)
-int
-yyparse (void)
+int yyparse (void *);
 #else
-int
-yyparse ()
-
+int yyparse (void);
 #endif
 #endif
+
+int
+yyparse(YYPARSE_PARAM_ARG)
+     YYPARSE_PARAM_DECL
 {
-  
   register int yystate;
   register int yyn;
-  int yyresult;
-  /* Number of tokens to shift before error messages enabled.  */
-  int yyerrstatus;
-  /* Lookahead token as an internal (translated) token number.  */
-  int yytoken = 0;
-
-  /* Three stacks and their tools:
-     `yyss': related to states,
-     `yyvs': related to semantic values,
-     `yyls': related to locations.
-
-     Refer to the stacks thru separate pointers, to allow yyoverflow
-     to reallocate them elsewhere.  */
-
-  /* The state stack.  */
-  short	yyssa[YYINITDEPTH];
-  short *yyss = yyssa;
   register short *yyssp;
-
-  /* The semantic value stack.  */
-  YYSTYPE yyvsa[YYINITDEPTH];
-  YYSTYPE *yyvs = yyvsa;
   register YYSTYPE *yyvsp;
+  int yyerrstatus;	/*  number of tokens to shift before error messages enabled */
+  int yychar1 = 0;		/*  lookahead token as an internal (translated) token number */
+
+  short	yyssa[YYINITDEPTH];	/*  the state stack			*/
+  YYSTYPE yyvsa[YYINITDEPTH];	/*  the semantic value stack		*/
 
+  short *yyss = yyssa;		/*  refer to the stacks thru separate pointers */
+  YYSTYPE *yyvs = yyvsa;	/*  to allow yyoverflow to reallocate them elsewhere */
 
+#ifdef YYLSP_NEEDED
+  YYLTYPE yylsa[YYINITDEPTH];	/*  the location stack			*/
+  YYLTYPE *yyls = yylsa;
+  YYLTYPE *yylsp;
 
+#define YYPOPSTACK   (yyvsp--, yyssp--, yylsp--)
+#else
 #define YYPOPSTACK   (yyvsp--, yyssp--)
+#endif
 
-  YYSIZE_T yystacksize = YYINITDEPTH;
+  int yystacksize = YYINITDEPTH;
+  int yyfree_stacks = 0;
 
-  /* The variables used to return semantic value and location from the
-     action routines.  */
-  YYSTYPE yyval;
+#ifdef YYPURE
+  int yychar;
+  YYSTYPE yylval;
+  int yynerrs;
+#ifdef YYLSP_NEEDED
+  YYLTYPE yylloc;
+#endif
+#endif
 
+  YYSTYPE yyval;		/*  the variable used to return		*/
+				/*  semantic values from the action	*/
+				/*  routines				*/
 
-  /* When reducing, the number of symbols on the RHS of the reduced
-     rule.  */
   int yylen;
 
-  YYDPRINTF ((stderr, "Starting parse\n"));
+#if YYDEBUG != 0
+  if (yydebug)
+    fprintf(stderr, "Starting parse\n");
+#endif
 
   yystate = 0;
   yyerrstatus = 0;
@@ -1152,96 +768,110 @@
      so that they stay on the same level as the state stack.
      The wasted elements are never initialized.  */
 
-  yyssp = yyss;
+  yyssp = yyss - 1;
   yyvsp = yyvs;
+#ifdef YYLSP_NEEDED
+  yylsp = yyls;
+#endif
 
-  goto yysetstate;
-
-/*------------------------------------------------------------.
-| yynewstate -- Push a new state, which is found in yystate.  |
-`------------------------------------------------------------*/
- yynewstate:
-  /* In all cases, when you get here, the value and location stacks
-     have just been pushed. so pushing a state here evens the stacks.
-     */
-  yyssp++;
+/* Push a new state, which is found in  yystate  .  */
+/* In all cases, when you get here, the value and location stacks
+   have just been pushed. so pushing a state here evens the stacks.  */
+yynewstate:
 
- yysetstate:
-  *yyssp = yystate;
+  *++yyssp = yystate;
 
-  if (yyss + yystacksize - 1 <= yyssp)
+  if (yyssp >= yyss + yystacksize - 1)
     {
+      /* Give user a chance to reallocate the stack */
+      /* Use copies of these so that the &'s don't force the real ones into memory. */
+      YYSTYPE *yyvs1 = yyvs;
+      short *yyss1 = yyss;
+#ifdef YYLSP_NEEDED
+      YYLTYPE *yyls1 = yyls;
+#endif
+
       /* Get the current used size of the three stacks, in elements.  */
-      YYSIZE_T yysize = yyssp - yyss + 1;
+      int size = yyssp - yyss + 1;
 
 #ifdef yyoverflow
-      {
-	/* Give user a chance to reallocate the stack. Use copies of
-	   these so that the &'s don't force the real ones into
-	   memory.  */
-	YYSTYPE *yyvs1 = yyvs;
-	short *yyss1 = yyss;
-
-
-	/* Each stack pointer address is followed by the size of the
-	   data in use in that stack, in bytes.  This used to be a
-	   conditional around just the two extra args, but that might
-	   be undefined if yyoverflow is a macro.  */
-	yyoverflow ("parser stack overflow",
-		    &yyss1, yysize * sizeof (*yyssp),
-		    &yyvs1, yysize * sizeof (*yyvsp),
-
-		    &yystacksize);
+      /* Each stack pointer address is followed by the size of
+	 the data in use in that stack, in bytes.  */
+#ifdef YYLSP_NEEDED
+      /* This used to be a conditional around just the two extra args,
+	 but that might be undefined if yyoverflow is a macro.  */
+      yyoverflow("parser stack overflow",
+		 &yyss1, size * sizeof (*yyssp),
+		 &yyvs1, size * sizeof (*yyvsp),
+		 &yyls1, size * sizeof (*yylsp),
+		 &yystacksize);
+#else
+      yyoverflow("parser stack overflow",
+		 &yyss1, size * sizeof (*yyssp),
+		 &yyvs1, size * sizeof (*yyvsp),
+		 &yystacksize);
+#endif
 
-	yyss = yyss1;
-	yyvs = yyvs1;
-      }
+      yyss = yyss1; yyvs = yyvs1;
+#ifdef YYLSP_NEEDED
+      yyls = yyls1;
+#endif
 #else /* no yyoverflow */
-# ifndef YYSTACK_RELOCATE
-      goto yyoverflowlab;
-# else
       /* Extend the stack our own way.  */
-      if (YYMAXDEPTH <= yystacksize)
-	goto yyoverflowlab;
+      if (yystacksize >= YYMAXDEPTH)
+	{
+	  yyerror("parser stack overflow");
+	  if (yyfree_stacks)
+	    {
+	      free (yyss);
+	      free (yyvs);
+#ifdef YYLSP_NEEDED
+	      free (yyls);
+#endif
+	    }
+	  return 2;
+	}
       yystacksize *= 2;
-      if (YYMAXDEPTH < yystacksize)
+      if (yystacksize > YYMAXDEPTH)
 	yystacksize = YYMAXDEPTH;
-
-      {
-	short *yyss1 = yyss;
-	union yyalloc *yyptr =
-	  (union yyalloc *) YYSTACK_ALLOC (YYSTACK_BYTES (yystacksize));
-	if (! yyptr)
-	  goto yyoverflowlab;
-	YYSTACK_RELOCATE (yyss);
-	YYSTACK_RELOCATE (yyvs);
-
-#  undef YYSTACK_RELOCATE
-	if (yyss1 != yyssa)
-	  YYSTACK_FREE (yyss1);
-      }
-# endif
+#ifndef YYSTACK_USE_ALLOCA
+      yyfree_stacks = 1;
+#endif
+      yyss = (short *) YYSTACK_ALLOC (yystacksize * sizeof (*yyssp));
+      __yy_memcpy ((char *)yyss, (char *)yyss1,
+		   size * (unsigned int) sizeof (*yyssp));
+      yyvs = (YYSTYPE *) YYSTACK_ALLOC (yystacksize * sizeof (*yyvsp));
+      __yy_memcpy ((char *)yyvs, (char *)yyvs1,
+		   size * (unsigned int) sizeof (*yyvsp));
+#ifdef YYLSP_NEEDED
+      yyls = (YYLTYPE *) YYSTACK_ALLOC (yystacksize * sizeof (*yylsp));
+      __yy_memcpy ((char *)yyls, (char *)yyls1,
+		   size * (unsigned int) sizeof (*yylsp));
+#endif
 #endif /* no yyoverflow */
 
-      yyssp = yyss + yysize - 1;
-      yyvsp = yyvs + yysize - 1;
-
+      yyssp = yyss + size - 1;
+      yyvsp = yyvs + size - 1;
+#ifdef YYLSP_NEEDED
+      yylsp = yyls + size - 1;
+#endif
 
-      YYDPRINTF ((stderr, "Stack size increased to %lu\n",
-		  (unsigned long int) yystacksize));
+#if YYDEBUG != 0
+      if (yydebug)
+	fprintf(stderr, "Stack size increased to %d\n", yystacksize);
+#endif
 
-      if (yyss + yystacksize - 1 <= yyssp)
+      if (yyssp >= yyss + yystacksize - 1)
 	YYABORT;
     }
 
-  YYDPRINTF ((stderr, "Entering state %d\n", yystate));
+#if YYDEBUG != 0
+  if (yydebug)
+    fprintf(stderr, "Entering state %d\n", yystate);
+#endif
 
   goto yybackup;
-
-/*-----------.
-| yybackup.  |
-`-----------*/
-yybackup:
+ yybackup:
 
 /* Do appropriate processing given the current state.  */
 /* Read a lookahead token if we need one and don't already have one.  */
@@ -1250,217 +880,261 @@
   /* First try to decide what to do without reference to lookahead token.  */
 
   yyn = yypact[yystate];
-  if (yyn == YYPACT_NINF)
+  if (yyn == YYFLAG)
     goto yydefault;
 
   /* Not known => get a lookahead token if don't already have one.  */
 
-  /* YYCHAR is either YYEMPTY or YYEOF or a valid lookahead symbol.  */
+  /* yychar is either YYEMPTY or YYEOF
+     or a valid token in external form.  */
+
   if (yychar == YYEMPTY)
     {
-      YYDPRINTF ((stderr, "Reading a token: "));
+#if YYDEBUG != 0
+      if (yydebug)
+	fprintf(stderr, "Reading a token: ");
+#endif
       yychar = YYLEX;
     }
 
-  if (yychar <= YYEOF)
+  /* Convert token to internal form (in yychar1) for indexing tables with */
+
+  if (yychar <= 0)		/* This means end of input. */
     {
-      yychar = yytoken = YYEOF;
-      YYDPRINTF ((stderr, "Now at end of input.\n"));
+      yychar1 = 0;
+      yychar = YYEOF;		/* Don't call YYLEX any more */
+
+#if YYDEBUG != 0
+      if (yydebug)
+	fprintf(stderr, "Now at end of input.\n");
+#endif
     }
   else
     {
-      yytoken = YYTRANSLATE (yychar);
-      YYDSYMPRINTF ("Next token is", yytoken, &yylval, &yylloc);
+      yychar1 = YYTRANSLATE(yychar);
+
+#if YYDEBUG != 0
+      if (yydebug)
+	{
+	  fprintf (stderr, "Next token is %d (%s", yychar, yytname[yychar1]);
+	  /* Give the individual parser a way to print the precise meaning
+	     of a token, for further debugging info.  */
+#ifdef YYPRINT
+	  YYPRINT (stderr, yychar, yylval);
+#endif
+	  fprintf (stderr, ")\n");
+	}
+#endif
     }
 
-  /* If the proper action on seeing token YYTOKEN is to reduce or to
-     detect an error, take that action.  */
-  yyn += yytoken;
-  if (yyn < 0 || YYLAST < yyn || yycheck[yyn] != yytoken)
+  yyn += yychar1;
+  if (yyn < 0 || yyn > YYLAST || yycheck[yyn] != yychar1)
     goto yydefault;
+
   yyn = yytable[yyn];
-  if (yyn <= 0)
+
+  /* yyn is what to do for this token type in this state.
+     Negative => reduce, -yyn is rule number.
+     Positive => shift, yyn is new state.
+       New state is final state => don't bother to shift,
+       just return success.
+     0, or most negative number => error.  */
+
+  if (yyn < 0)
     {
-      if (yyn == 0 || yyn == YYTABLE_NINF)
+      if (yyn == YYFLAG)
 	goto yyerrlab;
       yyn = -yyn;
       goto yyreduce;
     }
+  else if (yyn == 0)
+    goto yyerrlab;
 
   if (yyn == YYFINAL)
     YYACCEPT;
 
   /* Shift the lookahead token.  */
-  YYDPRINTF ((stderr, "Shifting token %s, ", yytname[yytoken]));
+
+#if YYDEBUG != 0
+  if (yydebug)
+    fprintf(stderr, "Shifting token %d (%s), ", yychar, yytname[yychar1]);
+#endif
 
   /* Discard the token being shifted unless it is eof.  */
   if (yychar != YYEOF)
     yychar = YYEMPTY;
 
   *++yyvsp = yylval;
+#ifdef YYLSP_NEEDED
+  *++yylsp = yylloc;
+#endif
 
-
-  /* Count tokens shifted since error; after three, turn off error
-     status.  */
-  if (yyerrstatus)
-    yyerrstatus--;
+  /* count tokens shifted since error; after three, turn off error status.  */
+  if (yyerrstatus) yyerrstatus--;
 
   yystate = yyn;
   goto yynewstate;
 
-
-/*-----------------------------------------------------------.
-| yydefault -- do the default action for the current state.  |
-`-----------------------------------------------------------*/
+/* Do the default action for the current state.  */
 yydefault:
+
   yyn = yydefact[yystate];
   if (yyn == 0)
     goto yyerrlab;
-  goto yyreduce;
 
-
-/*-----------------------------.
-| yyreduce -- Do a reduction.  |
-`-----------------------------*/
+/* Do a reduction.  yyn is the number of a rule to reduce with.  */
 yyreduce:
-  /* yyn is the number of a rule to reduce with.  */
   yylen = yyr2[yyn];
+  if (yylen > 0)
+    yyval = yyvsp[1-yylen]; /* implement default value of the action */
 
-  /* If YYLEN is nonzero, implement the default value of the action:
-     `$$ = $1'.
+#if YYDEBUG != 0
+  if (yydebug)
+    {
+      int i;
 
-     Otherwise, the following line sets YYVAL to garbage.
-     This behavior is undocumented and Bison
-     users should not rely upon it.  Assigning to YYVAL
-     unconditionally makes the parser a bit smaller, and it avoids a
-     GCC warning that YYVAL may be used uninitialized.  */
-  yyval = yyvsp[1-yylen];
+      fprintf (stderr, "Reducing via rule %d (line %d), ",
+	       yyn, yyrline[yyn]);
 
+      /* Print the symbols being reduced, and their result.  */
+      for (i = yyprhs[yyn]; yyrhs[i] > 0; i++)
+	fprintf (stderr, "%s ", yytname[yyrhs[i]]);
+      fprintf (stderr, " -> %s\n", yytname[yyr1[yyn]]);
+    }
+#endif
 
-  YY_REDUCE_PRINT (yyn);
-  switch (yyn)
-    {
-        case 2:
-#line 223 "/home/vadve/criswell/llvm/utils/TableGen/FileParser.y"
-    {
+
+  switch (yyn) {
+
+case 1:
+#line 223 "/Volumes/ProjectsDisk/cvs/llvm/utils/TableGen/FileParser.y"
+{
     yyval.Rec = Records.getClass(*yyvsp[0].StrVal);
     if (yyval.Rec == 0) {
       err() << "Couldn't find class '" << *yyvsp[0].StrVal << "'!\n";
       exit(1);
     }
     delete yyvsp[0].StrVal;
-  ;}
-    break;
-
-  case 3:
-#line 234 "/home/vadve/criswell/llvm/utils/TableGen/FileParser.y"
-    {                       // string type
+  ;
+    break;}
+case 2:
+#line 234 "/Volumes/ProjectsDisk/cvs/llvm/utils/TableGen/FileParser.y"
+{                       // string type
     yyval.Ty = new StringRecTy();
-  ;}
-    break;
-
-  case 4:
-#line 236 "/home/vadve/criswell/llvm/utils/TableGen/FileParser.y"
-    {                           // bit type
+  ;
+    break;}
+case 3:
+#line 236 "/Volumes/ProjectsDisk/cvs/llvm/utils/TableGen/FileParser.y"
+{                           // bit type
     yyval.Ty = new BitRecTy();
-  ;}
-    break;
-
-  case 5:
-#line 238 "/home/vadve/criswell/llvm/utils/TableGen/FileParser.y"
-    {           // bits<x> type
+  ;
+    break;}
+case 4:
+#line 238 "/Volumes/ProjectsDisk/cvs/llvm/utils/TableGen/FileParser.y"
+{           // bits<x> type
     yyval.Ty = new BitsRecTy(yyvsp[-1].IntVal);
-  ;}
-    break;
-
-  case 6:
-#line 240 "/home/vadve/criswell/llvm/utils/TableGen/FileParser.y"
-    {                           // int type
+  ;
+    break;}
+case 5:
+#line 240 "/Volumes/ProjectsDisk/cvs/llvm/utils/TableGen/FileParser.y"
+{                           // int type
     yyval.Ty = new IntRecTy();
-  ;}
-    break;
-
-  case 7:
-#line 242 "/home/vadve/criswell/llvm/utils/TableGen/FileParser.y"
-    {          // list<x> type
+  ;
+    break;}
+case 6:
+#line 242 "/Volumes/ProjectsDisk/cvs/llvm/utils/TableGen/FileParser.y"
+{          // list<x> type
     yyval.Ty = new ListRecTy(yyvsp[-1].Ty);
-  ;}
-    break;
-
-  case 8:
-#line 244 "/home/vadve/criswell/llvm/utils/TableGen/FileParser.y"
-    {                          // code type
+  ;
+    break;}
+case 7:
+#line 244 "/Volumes/ProjectsDisk/cvs/llvm/utils/TableGen/FileParser.y"
+{                          // code type
     yyval.Ty = new CodeRecTy();
-  ;}
-    break;
-
-  case 9:
-#line 246 "/home/vadve/criswell/llvm/utils/TableGen/FileParser.y"
-    {                           // dag type
+  ;
+    break;}
+case 8:
+#line 246 "/Volumes/ProjectsDisk/cvs/llvm/utils/TableGen/FileParser.y"
+{                           // dag type
     yyval.Ty = new DagRecTy();
-  ;}
-    break;
-
-  case 10:
-#line 248 "/home/vadve/criswell/llvm/utils/TableGen/FileParser.y"
-    {                       // Record Type
+  ;
+    break;}
+case 9:
+#line 248 "/Volumes/ProjectsDisk/cvs/llvm/utils/TableGen/FileParser.y"
+{                       // Record Type
     yyval.Ty = new RecordRecTy(yyvsp[0].Rec);
-  ;}
-    break;
-
-  case 11:
-#line 252 "/home/vadve/criswell/llvm/utils/TableGen/FileParser.y"
-    { yyval.IntVal = 0; ;}
-    break;
-
-  case 12:
-#line 252 "/home/vadve/criswell/llvm/utils/TableGen/FileParser.y"
-    { yyval.IntVal = 1; ;}
-    break;
-
-  case 13:
-#line 254 "/home/vadve/criswell/llvm/utils/TableGen/FileParser.y"
-    { yyval.Initializer = 0; ;}
-    break;
-
-  case 14:
-#line 254 "/home/vadve/criswell/llvm/utils/TableGen/FileParser.y"
-    { yyval.Initializer = yyvsp[0].Initializer; ;}
-    break;
-
-  case 15:
-#line 256 "/home/vadve/criswell/llvm/utils/TableGen/FileParser.y"
-    {
+  ;
+    break;}
+case 10:
+#line 252 "/Volumes/ProjectsDisk/cvs/llvm/utils/TableGen/FileParser.y"
+{ yyval.IntVal = 0; ;
+    break;}
+case 11:
+#line 252 "/Volumes/ProjectsDisk/cvs/llvm/utils/TableGen/FileParser.y"
+{ yyval.IntVal = 1; ;
+    break;}
+case 12:
+#line 254 "/Volumes/ProjectsDisk/cvs/llvm/utils/TableGen/FileParser.y"
+{ yyval.Initializer = 0; ;
+    break;}
+case 13:
+#line 254 "/Volumes/ProjectsDisk/cvs/llvm/utils/TableGen/FileParser.y"
+{ yyval.Initializer = yyvsp[0].Initializer; ;
+    break;}
+case 14:
+#line 256 "/Volumes/ProjectsDisk/cvs/llvm/utils/TableGen/FileParser.y"
+{
+  if (const RecordVal *RV = (CurRec ? CurRec->getValue(*yyvsp[0].StrVal) : 0)) {
+    yyval.Initializer = new VarInit(*yyvsp[0].StrVal, RV->getType());
+  } else if (CurRec && CurRec->isTemplateArg(CurRec->getName()+":"+*yyvsp[0].StrVal)) {
+    const RecordVal *RV = CurRec->getValue(CurRec->getName()+":"+*yyvsp[0].StrVal);
+    assert(RV && "Template arg doesn't exist??");
+    yyval.Initializer = new VarInit(CurRec->getName()+":"+*yyvsp[0].StrVal, RV->getType());
+  } else if (Record *D = Records.getDef(*yyvsp[0].StrVal)) {
+    yyval.Initializer = new DefInit(D);
+  } else {
+    err() << "Variable not defined: '" << *yyvsp[0].StrVal << "'!\n";
+    exit(1);
+  }
+  
+  delete yyvsp[0].StrVal;
+;
+    break;}
+case 15:
+#line 273 "/Volumes/ProjectsDisk/cvs/llvm/utils/TableGen/FileParser.y"
+{
+    yyval.Initializer = yyvsp[0].Initializer;
+  ;
+    break;}
+case 16:
+#line 275 "/Volumes/ProjectsDisk/cvs/llvm/utils/TableGen/FileParser.y"
+{
     yyval.Initializer = new IntInit(yyvsp[0].IntVal);
-  ;}
-    break;
-
-  case 16:
-#line 258 "/home/vadve/criswell/llvm/utils/TableGen/FileParser.y"
-    {
+  ;
+    break;}
+case 17:
+#line 277 "/Volumes/ProjectsDisk/cvs/llvm/utils/TableGen/FileParser.y"
+{
     yyval.Initializer = new StringInit(*yyvsp[0].StrVal);
     delete yyvsp[0].StrVal;
-  ;}
-    break;
-
-  case 17:
-#line 261 "/home/vadve/criswell/llvm/utils/TableGen/FileParser.y"
-    {
+  ;
+    break;}
+case 18:
+#line 280 "/Volumes/ProjectsDisk/cvs/llvm/utils/TableGen/FileParser.y"
+{
     yyval.Initializer = new CodeInit(*yyvsp[0].StrVal);
     delete yyvsp[0].StrVal;
-  ;}
-    break;
-
-  case 18:
-#line 264 "/home/vadve/criswell/llvm/utils/TableGen/FileParser.y"
-    {
+  ;
+    break;}
+case 19:
+#line 283 "/Volumes/ProjectsDisk/cvs/llvm/utils/TableGen/FileParser.y"
+{
     yyval.Initializer = new UnsetInit();
-  ;}
-    break;
-
-  case 19:
-#line 266 "/home/vadve/criswell/llvm/utils/TableGen/FileParser.y"
-    {
+  ;
+    break;}
+case 20:
+#line 285 "/Volumes/ProjectsDisk/cvs/llvm/utils/TableGen/FileParser.y"
+{
     BitsInit *Init = new BitsInit(yyvsp[-1].FieldList->size());
     for (unsigned i = 0, e = yyvsp[-1].FieldList->size(); i != e; ++i) {
       struct Init *Bit = (*yyvsp[-1].FieldList)[i]->convertInitializerTo(new BitRecTy());
@@ -1473,12 +1147,11 @@
     }
     yyval.Initializer = Init;
     delete yyvsp[-1].FieldList;
-  ;}
-    break;
-
-  case 20:
-#line 279 "/home/vadve/criswell/llvm/utils/TableGen/FileParser.y"
-    {
+  ;
+    break;}
+case 21:
+#line 298 "/Volumes/ProjectsDisk/cvs/llvm/utils/TableGen/FileParser.y"
+{
     // This is a CLASS<initvalslist> expression.  This is supposed to synthesize
     // a new anonymous definition, deriving from CLASS<initvalslist> with no
     // body.
@@ -1506,77 +1179,47 @@
     
     // Restore the old CurRec
     CurRec = OldRec;
-  ;}
-    break;
-
-  case 21:
-#line 307 "/home/vadve/criswell/llvm/utils/TableGen/FileParser.y"
-    {
-    if (const RecordVal *RV = (CurRec ? CurRec->getValue(*yyvsp[0].StrVal) : 0)) {
-      yyval.Initializer = new VarInit(*yyvsp[0].StrVal, RV->getType());
-    } else if (CurRec && CurRec->isTemplateArg(CurRec->getName()+":"+*yyvsp[0].StrVal)) {
-      const RecordVal *RV = CurRec->getValue(CurRec->getName()+":"+*yyvsp[0].StrVal);
-      assert(RV && "Template arg doesn't exist??");
-      yyval.Initializer = new VarInit(CurRec->getName()+":"+*yyvsp[0].StrVal, RV->getType());
-    } else if (Record *D = Records.getDef(*yyvsp[0].StrVal)) {
-      yyval.Initializer = new DefInit(D);
-    } else {
-      err() << "Variable not defined: '" << *yyvsp[0].StrVal << "'!\n";
-      exit(1);
-    }
-    
-    delete yyvsp[0].StrVal;
-  ;}
-    break;
-
-  case 22:
-#line 322 "/home/vadve/criswell/llvm/utils/TableGen/FileParser.y"
-    {
+  ;
+    break;}
+case 22:
+#line 326 "/Volumes/ProjectsDisk/cvs/llvm/utils/TableGen/FileParser.y"
+{
     yyval.Initializer = yyvsp[-3].Initializer->convertInitializerBitRange(*yyvsp[-1].BitList);
     if (yyval.Initializer == 0) {
       err() << "Invalid bit range for value '" << *yyvsp[-3].Initializer << "'!\n";
       exit(1);
     }
     delete yyvsp[-1].BitList;
-  ;}
-    break;
-
-  case 23:
-#line 329 "/home/vadve/criswell/llvm/utils/TableGen/FileParser.y"
-    {
+  ;
+    break;}
+case 23:
+#line 333 "/Volumes/ProjectsDisk/cvs/llvm/utils/TableGen/FileParser.y"
+{
     yyval.Initializer = new ListInit(*yyvsp[-1].FieldList);
     delete yyvsp[-1].FieldList;
-  ;}
-    break;
-
-  case 24:
-#line 332 "/home/vadve/criswell/llvm/utils/TableGen/FileParser.y"
-    {
+  ;
+    break;}
+case 24:
+#line 336 "/Volumes/ProjectsDisk/cvs/llvm/utils/TableGen/FileParser.y"
+{
     if (!yyvsp[-2].Initializer->getFieldType(*yyvsp[0].StrVal)) {
       err() << "Cannot access field '" << *yyvsp[0].StrVal << "' of value '" << *yyvsp[-2].Initializer << "!\n";
       exit(1);
     }
     yyval.Initializer = new FieldInit(yyvsp[-2].Initializer, *yyvsp[0].StrVal);
     delete yyvsp[0].StrVal;
-  ;}
-    break;
-
-  case 25:
-#line 339 "/home/vadve/criswell/llvm/utils/TableGen/FileParser.y"
-    {
-    Record *D = Records.getDef(*yyvsp[-2].StrVal);
-    if (D == 0) {
-      err() << "Invalid def '" << *yyvsp[-2].StrVal << "'!\n";
-      exit(1);
-    }
-    yyval.Initializer = new DagInit(D, *yyvsp[-1].DagValueList);
-    delete yyvsp[-2].StrVal; delete yyvsp[-1].DagValueList;
-  ;}
-    break;
-
-  case 26:
-#line 347 "/home/vadve/criswell/llvm/utils/TableGen/FileParser.y"
-    {
+  ;
+    break;}
+case 25:
+#line 343 "/Volumes/ProjectsDisk/cvs/llvm/utils/TableGen/FileParser.y"
+{
+    yyval.Initializer = new DagInit(yyvsp[-2].Initializer, *yyvsp[-1].DagValueList);
+    delete yyvsp[-1].DagValueList;
+  ;
+    break;}
+case 26:
+#line 346 "/Volumes/ProjectsDisk/cvs/llvm/utils/TableGen/FileParser.y"
+{
     std::reverse(yyvsp[-1].BitList->begin(), yyvsp[-1].BitList->end());
     yyval.Initializer = yyvsp[-3].Initializer->convertInitListSlice(*yyvsp[-1].BitList);
     if (yyval.Initializer == 0) {
@@ -1584,97 +1227,86 @@
       exit(1);
     }
     delete yyvsp[-1].BitList;
-  ;}
-    break;
-
-  case 27:
-#line 355 "/home/vadve/criswell/llvm/utils/TableGen/FileParser.y"
-    {
+  ;
+    break;}
+case 27:
+#line 354 "/Volumes/ProjectsDisk/cvs/llvm/utils/TableGen/FileParser.y"
+{
     yyval.Initializer = yyvsp[-3].Initializer->getBinaryOp(Init::SHL, yyvsp[-1].Initializer);
     if (yyval.Initializer == 0) {
       err() << "Cannot shift values '" << *yyvsp[-3].Initializer << "' and '" << *yyvsp[-1].Initializer << "'!\n";
       exit(1);
     }
-  ;}
-    break;
-
-  case 28:
-#line 361 "/home/vadve/criswell/llvm/utils/TableGen/FileParser.y"
-    {
+  ;
+    break;}
+case 28:
+#line 360 "/Volumes/ProjectsDisk/cvs/llvm/utils/TableGen/FileParser.y"
+{
     yyval.Initializer = yyvsp[-3].Initializer->getBinaryOp(Init::SRA, yyvsp[-1].Initializer);
     if (yyval.Initializer == 0) {
       err() << "Cannot shift values '" << *yyvsp[-3].Initializer << "' and '" << *yyvsp[-1].Initializer << "'!\n";
       exit(1);
     }
-  ;}
-    break;
-
-  case 29:
-#line 367 "/home/vadve/criswell/llvm/utils/TableGen/FileParser.y"
-    {
+  ;
+    break;}
+case 29:
+#line 366 "/Volumes/ProjectsDisk/cvs/llvm/utils/TableGen/FileParser.y"
+{
     yyval.Initializer = yyvsp[-3].Initializer->getBinaryOp(Init::SRL, yyvsp[-1].Initializer);
     if (yyval.Initializer == 0) {
       err() << "Cannot shift values '" << *yyvsp[-3].Initializer << "' and '" << *yyvsp[-1].Initializer << "'!\n";
       exit(1);
     }
-  ;}
-    break;
-
-  case 30:
-#line 375 "/home/vadve/criswell/llvm/utils/TableGen/FileParser.y"
-    {
+  ;
+    break;}
+case 30:
+#line 374 "/Volumes/ProjectsDisk/cvs/llvm/utils/TableGen/FileParser.y"
+{
     yyval.StrVal = new std::string();
-  ;}
-    break;
-
-  case 31:
-#line 378 "/home/vadve/criswell/llvm/utils/TableGen/FileParser.y"
-    {
+  ;
+    break;}
+case 31:
+#line 377 "/Volumes/ProjectsDisk/cvs/llvm/utils/TableGen/FileParser.y"
+{
     yyval.StrVal = yyvsp[0].StrVal;
-  ;}
-    break;
-
-  case 32:
-#line 382 "/home/vadve/criswell/llvm/utils/TableGen/FileParser.y"
-    {
+  ;
+    break;}
+case 32:
+#line 381 "/Volumes/ProjectsDisk/cvs/llvm/utils/TableGen/FileParser.y"
+{
     yyval.DagValueList = new std::vector<std::pair<Init*, std::string> >();
     yyval.DagValueList->push_back(std::make_pair(yyvsp[-1].Initializer, *yyvsp[0].StrVal));
     delete yyvsp[0].StrVal;
-  ;}
-    break;
-
-  case 33:
-#line 387 "/home/vadve/criswell/llvm/utils/TableGen/FileParser.y"
-    {
+  ;
+    break;}
+case 33:
+#line 386 "/Volumes/ProjectsDisk/cvs/llvm/utils/TableGen/FileParser.y"
+{
     yyvsp[-3].DagValueList->push_back(std::make_pair(yyvsp[-1].Initializer, *yyvsp[0].StrVal));
     delete yyvsp[0].StrVal;
     yyval.DagValueList = yyvsp[-3].DagValueList;
-  ;}
-    break;
-
-  case 34:
-#line 393 "/home/vadve/criswell/llvm/utils/TableGen/FileParser.y"
-    {
+  ;
+    break;}
+case 34:
+#line 392 "/Volumes/ProjectsDisk/cvs/llvm/utils/TableGen/FileParser.y"
+{
     yyval.DagValueList = new std::vector<std::pair<Init*, std::string> >();
-  ;}
-    break;
-
-  case 35:
-#line 396 "/home/vadve/criswell/llvm/utils/TableGen/FileParser.y"
-    { yyval.DagValueList = yyvsp[0].DagValueList; ;}
-    break;
-
-  case 36:
-#line 399 "/home/vadve/criswell/llvm/utils/TableGen/FileParser.y"
-    {
+  ;
+    break;}
+case 35:
+#line 395 "/Volumes/ProjectsDisk/cvs/llvm/utils/TableGen/FileParser.y"
+{ yyval.DagValueList = yyvsp[0].DagValueList; ;
+    break;}
+case 36:
+#line 398 "/Volumes/ProjectsDisk/cvs/llvm/utils/TableGen/FileParser.y"
+{
     yyval.BitList = new std::vector<unsigned>();
     yyval.BitList->push_back(yyvsp[0].IntVal);
-  ;}
-    break;
-
-  case 37:
-#line 402 "/home/vadve/criswell/llvm/utils/TableGen/FileParser.y"
-    {
+  ;
+    break;}
+case 37:
+#line 401 "/Volumes/ProjectsDisk/cvs/llvm/utils/TableGen/FileParser.y"
+{
     if (yyvsp[-2].IntVal < 0 || yyvsp[0].IntVal < 0) {
       err() << "Invalid range: " << yyvsp[-2].IntVal << "-" << yyvsp[0].IntVal << "!\n";
       exit(1);
@@ -1687,12 +1319,11 @@
       for (int i = yyvsp[-2].IntVal; i >= yyvsp[0].IntVal; --i)
         yyval.BitList->push_back(i);
     }
-  ;}
-    break;
-
-  case 38:
-#line 415 "/home/vadve/criswell/llvm/utils/TableGen/FileParser.y"
-    {
+  ;
+    break;}
+case 38:
+#line 414 "/Volumes/ProjectsDisk/cvs/llvm/utils/TableGen/FileParser.y"
+{
     yyvsp[0].IntVal = -yyvsp[0].IntVal;
     if (yyvsp[-1].IntVal < 0 || yyvsp[0].IntVal < 0) {
       err() << "Invalid range: " << yyvsp[-1].IntVal << "-" << yyvsp[0].IntVal << "!\n";
@@ -1706,19 +1337,17 @@
       for (int i = yyvsp[-1].IntVal; i >= yyvsp[0].IntVal; --i)
         yyval.BitList->push_back(i);
     }
-  ;}
-    break;
-
-  case 39:
-#line 429 "/home/vadve/criswell/llvm/utils/TableGen/FileParser.y"
-    {
+  ;
+    break;}
+case 39:
+#line 428 "/Volumes/ProjectsDisk/cvs/llvm/utils/TableGen/FileParser.y"
+{
     (yyval.BitList=yyvsp[-2].BitList)->push_back(yyvsp[0].IntVal);
-  ;}
-    break;
-
-  case 40:
-#line 431 "/home/vadve/criswell/llvm/utils/TableGen/FileParser.y"
-    {
+  ;
+    break;}
+case 40:
+#line 430 "/Volumes/ProjectsDisk/cvs/llvm/utils/TableGen/FileParser.y"
+{
     if (yyvsp[-2].IntVal < 0 || yyvsp[0].IntVal < 0) {
       err() << "Invalid range: " << yyvsp[-2].IntVal << "-" << yyvsp[0].IntVal << "!\n";
       exit(1);
@@ -1731,12 +1360,11 @@
       for (int i = yyvsp[-2].IntVal; i >= yyvsp[0].IntVal; --i)
         yyval.BitList->push_back(i);
     }
-  ;}
-    break;
-
-  case 41:
-#line 444 "/home/vadve/criswell/llvm/utils/TableGen/FileParser.y"
-    {
+  ;
+    break;}
+case 41:
+#line 443 "/Volumes/ProjectsDisk/cvs/llvm/utils/TableGen/FileParser.y"
+{
     yyvsp[0].IntVal = -yyvsp[0].IntVal;
     if (yyvsp[-1].IntVal < 0 || yyvsp[0].IntVal < 0) {
       err() << "Invalid range: " << yyvsp[-1].IntVal << "-" << yyvsp[0].IntVal << "!\n";
@@ -1750,56 +1378,48 @@
       for (int i = yyvsp[-1].IntVal; i >= yyvsp[0].IntVal; --i)
         yyval.BitList->push_back(i);
     }
-  ;}
-    break;
-
-  case 42:
-#line 460 "/home/vadve/criswell/llvm/utils/TableGen/FileParser.y"
-    { yyval.BitList = yyvsp[0].BitList; std::reverse(yyvsp[0].BitList->begin(), yyvsp[0].BitList->end()); ;}
-    break;
-
-  case 43:
-#line 462 "/home/vadve/criswell/llvm/utils/TableGen/FileParser.y"
-    { yyval.BitList = 0; ;}
-    break;
-
-  case 44:
-#line 462 "/home/vadve/criswell/llvm/utils/TableGen/FileParser.y"
-    { yyval.BitList = yyvsp[-1].BitList; ;}
-    break;
-
-  case 45:
-#line 466 "/home/vadve/criswell/llvm/utils/TableGen/FileParser.y"
-    {
+  ;
+    break;}
+case 42:
+#line 459 "/Volumes/ProjectsDisk/cvs/llvm/utils/TableGen/FileParser.y"
+{ yyval.BitList = yyvsp[0].BitList; std::reverse(yyvsp[0].BitList->begin(), yyvsp[0].BitList->end()); ;
+    break;}
+case 43:
+#line 461 "/Volumes/ProjectsDisk/cvs/llvm/utils/TableGen/FileParser.y"
+{ yyval.BitList = 0; ;
+    break;}
+case 44:
+#line 461 "/Volumes/ProjectsDisk/cvs/llvm/utils/TableGen/FileParser.y"
+{ yyval.BitList = yyvsp[-1].BitList; ;
+    break;}
+case 45:
+#line 465 "/Volumes/ProjectsDisk/cvs/llvm/utils/TableGen/FileParser.y"
+{
     yyval.FieldList = new std::vector<Init*>();
-  ;}
-    break;
-
-  case 46:
-#line 468 "/home/vadve/criswell/llvm/utils/TableGen/FileParser.y"
-    {
+  ;
+    break;}
+case 46:
+#line 467 "/Volumes/ProjectsDisk/cvs/llvm/utils/TableGen/FileParser.y"
+{
     yyval.FieldList = yyvsp[0].FieldList;
-  ;}
-    break;
-
-  case 47:
-#line 472 "/home/vadve/criswell/llvm/utils/TableGen/FileParser.y"
-    {
+  ;
+    break;}
+case 47:
+#line 471 "/Volumes/ProjectsDisk/cvs/llvm/utils/TableGen/FileParser.y"
+{
     yyval.FieldList = new std::vector<Init*>();
     yyval.FieldList->push_back(yyvsp[0].Initializer);
-  ;}
-    break;
-
-  case 48:
-#line 475 "/home/vadve/criswell/llvm/utils/TableGen/FileParser.y"
-    {
+  ;
+    break;}
+case 48:
+#line 474 "/Volumes/ProjectsDisk/cvs/llvm/utils/TableGen/FileParser.y"
+{
     (yyval.FieldList = yyvsp[-2].FieldList)->push_back(yyvsp[0].Initializer);
-  ;}
-    break;
-
-  case 49:
-#line 479 "/home/vadve/criswell/llvm/utils/TableGen/FileParser.y"
-    {
+  ;
+    break;}
+case 49:
+#line 478 "/Volumes/ProjectsDisk/cvs/llvm/utils/TableGen/FileParser.y"
+{
   std::string DecName = *yyvsp[-1].StrVal;
   if (ParsingTemplateArgs)
     DecName = CurRec->getName() + ":" + DecName;
@@ -1807,114 +1427,99 @@
   addValue(RecordVal(DecName, yyvsp[-2].Ty, yyvsp[-3].IntVal));
   setValue(DecName, 0, yyvsp[0].Initializer);
   yyval.StrVal = new std::string(DecName);
-;}
-    break;
-
-  case 50:
-#line 489 "/home/vadve/criswell/llvm/utils/TableGen/FileParser.y"
-    {
+;
+    break;}
+case 50:
+#line 488 "/Volumes/ProjectsDisk/cvs/llvm/utils/TableGen/FileParser.y"
+{
   delete yyvsp[-1].StrVal;
-;}
-    break;
-
-  case 51:
-#line 491 "/home/vadve/criswell/llvm/utils/TableGen/FileParser.y"
-    {
+;
+    break;}
+case 51:
+#line 490 "/Volumes/ProjectsDisk/cvs/llvm/utils/TableGen/FileParser.y"
+{
   setValue(*yyvsp[-4].StrVal, yyvsp[-3].BitList, yyvsp[-1].Initializer);
   delete yyvsp[-4].StrVal;
   delete yyvsp[-3].BitList;
-;}
-    break;
-
-  case 56:
-#line 500 "/home/vadve/criswell/llvm/utils/TableGen/FileParser.y"
-    {
+;
+    break;}
+case 56:
+#line 499 "/Volumes/ProjectsDisk/cvs/llvm/utils/TableGen/FileParser.y"
+{
     yyval.SubClassRef = new SubClassRefTy(yyvsp[0].Rec, new std::vector<Init*>());
-  ;}
-    break;
-
-  case 57:
-#line 502 "/home/vadve/criswell/llvm/utils/TableGen/FileParser.y"
-    {
+  ;
+    break;}
+case 57:
+#line 501 "/Volumes/ProjectsDisk/cvs/llvm/utils/TableGen/FileParser.y"
+{
     yyval.SubClassRef = new SubClassRefTy(yyvsp[-3].Rec, yyvsp[-1].FieldList);
-  ;}
-    break;
-
-  case 58:
-#line 506 "/home/vadve/criswell/llvm/utils/TableGen/FileParser.y"
-    {
+  ;
+    break;}
+case 58:
+#line 505 "/Volumes/ProjectsDisk/cvs/llvm/utils/TableGen/FileParser.y"
+{
     yyval.SubClassList = new std::vector<SubClassRefTy>();
     yyval.SubClassList->push_back(*yyvsp[0].SubClassRef);
     delete yyvsp[0].SubClassRef;
-  ;}
-    break;
-
-  case 59:
-#line 511 "/home/vadve/criswell/llvm/utils/TableGen/FileParser.y"
-    {
+  ;
+    break;}
+case 59:
+#line 510 "/Volumes/ProjectsDisk/cvs/llvm/utils/TableGen/FileParser.y"
+{
     (yyval.SubClassList=yyvsp[-2].SubClassList)->push_back(*yyvsp[0].SubClassRef);
     delete yyvsp[0].SubClassRef;
-  ;}
-    break;
-
-  case 60:
-#line 516 "/home/vadve/criswell/llvm/utils/TableGen/FileParser.y"
-    {
+  ;
+    break;}
+case 60:
+#line 515 "/Volumes/ProjectsDisk/cvs/llvm/utils/TableGen/FileParser.y"
+{
     yyval.SubClassList = new std::vector<SubClassRefTy>();
-  ;}
-    break;
-
-  case 61:
-#line 519 "/home/vadve/criswell/llvm/utils/TableGen/FileParser.y"
-    {
+  ;
+    break;}
+case 61:
+#line 518 "/Volumes/ProjectsDisk/cvs/llvm/utils/TableGen/FileParser.y"
+{
     yyval.SubClassList = yyvsp[0].SubClassList;
-  ;}
-    break;
-
-  case 62:
-#line 523 "/home/vadve/criswell/llvm/utils/TableGen/FileParser.y"
-    {
+  ;
+    break;}
+case 62:
+#line 522 "/Volumes/ProjectsDisk/cvs/llvm/utils/TableGen/FileParser.y"
+{
   CurRec->addTemplateArg(*yyvsp[0].StrVal);
   delete yyvsp[0].StrVal;
-;}
-    break;
-
-  case 63:
-#line 526 "/home/vadve/criswell/llvm/utils/TableGen/FileParser.y"
-    {
+;
+    break;}
+case 63:
+#line 525 "/Volumes/ProjectsDisk/cvs/llvm/utils/TableGen/FileParser.y"
+{
   CurRec->addTemplateArg(*yyvsp[0].StrVal);
   delete yyvsp[0].StrVal;
-;}
-    break;
-
-  case 64:
-#line 531 "/home/vadve/criswell/llvm/utils/TableGen/FileParser.y"
-    {;}
-    break;
-
-  case 67:
-#line 534 "/home/vadve/criswell/llvm/utils/TableGen/FileParser.y"
-    { yyval.StrVal = yyvsp[0].StrVal; ;}
-    break;
-
-  case 68:
-#line 534 "/home/vadve/criswell/llvm/utils/TableGen/FileParser.y"
-    { yyval.StrVal = new std::string(); ;}
-    break;
-
-  case 69:
-#line 536 "/home/vadve/criswell/llvm/utils/TableGen/FileParser.y"
-    {
+;
+    break;}
+case 64:
+#line 530 "/Volumes/ProjectsDisk/cvs/llvm/utils/TableGen/FileParser.y"
+{;
+    break;}
+case 67:
+#line 533 "/Volumes/ProjectsDisk/cvs/llvm/utils/TableGen/FileParser.y"
+{ yyval.StrVal = yyvsp[0].StrVal; ;
+    break;}
+case 68:
+#line 533 "/Volumes/ProjectsDisk/cvs/llvm/utils/TableGen/FileParser.y"
+{ yyval.StrVal = new std::string(); ;
+    break;}
+case 69:
+#line 535 "/Volumes/ProjectsDisk/cvs/llvm/utils/TableGen/FileParser.y"
+{
   static unsigned AnonCounter = 0;
   if (yyvsp[0].StrVal->empty())
     *yyvsp[0].StrVal = "anonymous."+utostr(AnonCounter++);
   yyval.StrVal = yyvsp[0].StrVal;
-;}
-    break;
-
-  case 70:
-#line 543 "/home/vadve/criswell/llvm/utils/TableGen/FileParser.y"
-    {
+;
+    break;}
+case 70:
+#line 542 "/Volumes/ProjectsDisk/cvs/llvm/utils/TableGen/FileParser.y"
+{
   // If a class of this name already exists, it must be a forward ref.
   if ((CurRec = Records.getClass(*yyvsp[0].StrVal))) {
     // If the body was previously defined, this is an error.
@@ -1930,12 +1535,11 @@
     Records.addClass(CurRec);
   }
   delete yyvsp[0].StrVal;
-;}
-    break;
-
-  case 71:
-#line 561 "/home/vadve/criswell/llvm/utils/TableGen/FileParser.y"
-    {
+;
+    break;}
+case 71:
+#line 560 "/Volumes/ProjectsDisk/cvs/llvm/utils/TableGen/FileParser.y"
+{
   CurRec = new Record(*yyvsp[0].StrVal);
   delete yyvsp[0].StrVal;
   
@@ -1945,12 +1549,11 @@
     exit(1);
   }
   Records.addDef(CurRec);
-;}
-    break;
-
-  case 72:
-#line 573 "/home/vadve/criswell/llvm/utils/TableGen/FileParser.y"
-    {
+;
+    break;}
+case 72:
+#line 572 "/Volumes/ProjectsDisk/cvs/llvm/utils/TableGen/FileParser.y"
+{
            for (unsigned i = 0, e = yyvsp[0].SubClassList->size(); i != e; ++i) {
              addSubClass((*yyvsp[0].SubClassList)[i].first, *(*yyvsp[0].SubClassList)[i].second);
              // Delete the template arg values for the class
@@ -1964,294 +1567,304 @@
                setValue(LetStack[i][j].Name,
                         LetStack[i][j].HasBits ? &LetStack[i][j].Bits : 0,
                         LetStack[i][j].Value);
-         ;}
-    break;
-
-  case 73:
-#line 587 "/home/vadve/criswell/llvm/utils/TableGen/FileParser.y"
-    {
+         ;
+    break;}
+case 73:
+#line 586 "/Volumes/ProjectsDisk/cvs/llvm/utils/TableGen/FileParser.y"
+{
            yyval.Rec = CurRec;
            CurRec = 0;
-         ;}
-    break;
-
-  case 74:
-#line 592 "/home/vadve/criswell/llvm/utils/TableGen/FileParser.y"
-    {
+         ;
+    break;}
+case 74:
+#line 591 "/Volumes/ProjectsDisk/cvs/llvm/utils/TableGen/FileParser.y"
+{
                 ParsingTemplateArgs = true;
-            ;}
-    break;
-
-  case 75:
-#line 594 "/home/vadve/criswell/llvm/utils/TableGen/FileParser.y"
-    {
+            ;
+    break;}
+case 75:
+#line 593 "/Volumes/ProjectsDisk/cvs/llvm/utils/TableGen/FileParser.y"
+{
                 ParsingTemplateArgs = false;
-            ;}
-    break;
-
-  case 76:
-#line 596 "/home/vadve/criswell/llvm/utils/TableGen/FileParser.y"
-    {
+            ;
+    break;}
+case 76:
+#line 595 "/Volumes/ProjectsDisk/cvs/llvm/utils/TableGen/FileParser.y"
+{
         yyval.Rec = yyvsp[0].Rec;
-     ;}
-    break;
-
-  case 77:
-#line 600 "/home/vadve/criswell/llvm/utils/TableGen/FileParser.y"
-    {
+     ;
+    break;}
+case 77:
+#line 599 "/Volumes/ProjectsDisk/cvs/llvm/utils/TableGen/FileParser.y"
+{
   yyvsp[0].Rec->resolveReferences();
 
   // If ObjectBody has template arguments, it's an error.
   assert(yyvsp[0].Rec->getTemplateArgs().empty() && "How'd this get template args?");
   yyval.Rec = yyvsp[0].Rec;
-;}
-    break;
-
-  case 80:
-#line 611 "/home/vadve/criswell/llvm/utils/TableGen/FileParser.y"
-    {
+;
+    break;}
+case 80:
+#line 610 "/Volumes/ProjectsDisk/cvs/llvm/utils/TableGen/FileParser.y"
+{
   LetStack.back().push_back(LetRecord(*yyvsp[-3].StrVal, yyvsp[-2].BitList, yyvsp[0].Initializer));
   delete yyvsp[-3].StrVal; delete yyvsp[-2].BitList;
-;}
-    break;
-
-  case 83:
-#line 619 "/home/vadve/criswell/llvm/utils/TableGen/FileParser.y"
-    { LetStack.push_back(std::vector<LetRecord>()); ;}
-    break;
-
-  case 85:
-#line 622 "/home/vadve/criswell/llvm/utils/TableGen/FileParser.y"
-    {
+;
+    break;}
+case 83:
+#line 618 "/Volumes/ProjectsDisk/cvs/llvm/utils/TableGen/FileParser.y"
+{ LetStack.push_back(std::vector<LetRecord>()); ;
+    break;}
+case 85:
+#line 621 "/Volumes/ProjectsDisk/cvs/llvm/utils/TableGen/FileParser.y"
+{
     LetStack.pop_back();
-  ;}
-    break;
-
-  case 86:
-#line 625 "/home/vadve/criswell/llvm/utils/TableGen/FileParser.y"
-    {
+  ;
+    break;}
+case 86:
+#line 624 "/Volumes/ProjectsDisk/cvs/llvm/utils/TableGen/FileParser.y"
+{
     LetStack.pop_back();
-  ;}
-    break;
-
-  case 87:
-#line 629 "/home/vadve/criswell/llvm/utils/TableGen/FileParser.y"
-    {;}
-    break;
-
-  case 88:
-#line 629 "/home/vadve/criswell/llvm/utils/TableGen/FileParser.y"
-    {;}
-    break;
-
-  case 89:
-#line 631 "/home/vadve/criswell/llvm/utils/TableGen/FileParser.y"
-    {;}
-    break;
-
-
-    }
-
-/* Line 999 of yacc.c.  */
-#line 2056 "FileParser.tab.c"
+  ;
+    break;}
+case 87:
+#line 628 "/Volumes/ProjectsDisk/cvs/llvm/utils/TableGen/FileParser.y"
+{;
+    break;}
+case 88:
+#line 628 "/Volumes/ProjectsDisk/cvs/llvm/utils/TableGen/FileParser.y"
+{;
+    break;}
+case 89:
+#line 630 "/Volumes/ProjectsDisk/cvs/llvm/utils/TableGen/FileParser.y"
+{;
+    break;}
+}
+   /* the action file gets copied in in place of this dollarsign */
+#line 543 "/usr/share/bison.simple"
 
   yyvsp -= yylen;
   yyssp -= yylen;
+#ifdef YYLSP_NEEDED
+  yylsp -= yylen;
+#endif
 
-
-  YY_STACK_PRINT (yyss, yyssp);
+#if YYDEBUG != 0
+  if (yydebug)
+    {
+      short *ssp1 = yyss - 1;
+      fprintf (stderr, "state stack now");
+      while (ssp1 != yyssp)
+	fprintf (stderr, " %d", *++ssp1);
+      fprintf (stderr, "\n");
+    }
+#endif
 
   *++yyvsp = yyval;
 
+#ifdef YYLSP_NEEDED
+  yylsp++;
+  if (yylen == 0)
+    {
+      yylsp->first_line = yylloc.first_line;
+      yylsp->first_column = yylloc.first_column;
+      yylsp->last_line = (yylsp-1)->last_line;
+      yylsp->last_column = (yylsp-1)->last_column;
+      yylsp->text = 0;
+    }
+  else
+    {
+      yylsp->last_line = (yylsp+yylen-1)->last_line;
+      yylsp->last_column = (yylsp+yylen-1)->last_column;
+    }
+#endif
 
-  /* Now `shift' the result of the reduction.  Determine what state
-     that goes to, based on the state we popped back to and the rule
-     number reduced by.  */
+  /* Now "shift" the result of the reduction.
+     Determine what state that goes to,
+     based on the state we popped back to
+     and the rule number reduced by.  */
 
   yyn = yyr1[yyn];
 
-  yystate = yypgoto[yyn - YYNTOKENS] + *yyssp;
-  if (0 <= yystate && yystate <= YYLAST && yycheck[yystate] == *yyssp)
+  yystate = yypgoto[yyn - YYNTBASE] + *yyssp;
+  if (yystate >= 0 && yystate <= YYLAST && yycheck[yystate] == *yyssp)
     yystate = yytable[yystate];
   else
-    yystate = yydefgoto[yyn - YYNTOKENS];
+    yystate = yydefgoto[yyn - YYNTBASE];
 
   goto yynewstate;
 
+yyerrlab:   /* here on detecting error */
 
-/*------------------------------------.
-| yyerrlab -- here on detecting error |
-`------------------------------------*/
-yyerrlab:
-  /* If not already recovering from an error, report this error.  */
-  if (!yyerrstatus)
+  if (! yyerrstatus)
+    /* If not already recovering from an error, report this error.  */
     {
       ++yynerrs;
-#if YYERROR_VERBOSE
+
+#ifdef YYERROR_VERBOSE
       yyn = yypact[yystate];
 
-      if (YYPACT_NINF < yyn && yyn < YYLAST)
+      if (yyn > YYFLAG && yyn < YYLAST)
 	{
-	  YYSIZE_T yysize = 0;
-	  int yytype = YYTRANSLATE (yychar);
-	  char *yymsg;
-	  int yyx, yycount;
-
-	  yycount = 0;
-	  /* Start YYX at -YYN if negative to avoid negative indexes in
-	     YYCHECK.  */
-	  for (yyx = yyn < 0 ? -yyn : 0;
-	       yyx < (int) (sizeof (yytname) / sizeof (char *)); yyx++)
-	    if (yycheck[yyx + yyn] == yyx && yyx != YYTERROR)
-	      yysize += yystrlen (yytname[yyx]) + 15, yycount++;
-	  yysize += yystrlen ("syntax error, unexpected ") + 1;
-	  yysize += yystrlen (yytname[yytype]);
-	  yymsg = (char *) YYSTACK_ALLOC (yysize);
-	  if (yymsg != 0)
+	  int size = 0;
+	  char *msg;
+	  int x, count;
+
+	  count = 0;
+	  /* Start X at -yyn if nec to avoid negative indexes in yycheck.  */
+	  for (x = (yyn < 0 ? -yyn : 0);
+	       x < (sizeof(yytname) / sizeof(char *)); x++)
+	    if (yycheck[x + yyn] == x)
+	      size += strlen(yytname[x]) + 15, count++;
+	  msg = (char *) malloc(size + 15);
+	  if (msg != 0)
 	    {
-	      char *yyp = yystpcpy (yymsg, "syntax error, unexpected ");
-	      yyp = yystpcpy (yyp, yytname[yytype]);
+	      strcpy(msg, "parse error");
 
-	      if (yycount < 5)
+	      if (count < 5)
 		{
-		  yycount = 0;
-		  for (yyx = yyn < 0 ? -yyn : 0;
-		       yyx < (int) (sizeof (yytname) / sizeof (char *));
-		       yyx++)
-		    if (yycheck[yyx + yyn] == yyx && yyx != YYTERROR)
+		  count = 0;
+		  for (x = (yyn < 0 ? -yyn : 0);
+		       x < (sizeof(yytname) / sizeof(char *)); x++)
+		    if (yycheck[x + yyn] == x)
 		      {
-			const char *yyq = ! yycount ? ", expecting " : " or ";
-			yyp = yystpcpy (yyp, yyq);
-			yyp = yystpcpy (yyp, yytname[yyx]);
-			yycount++;
+			strcat(msg, count == 0 ? ", expecting `" : " or `");
+			strcat(msg, yytname[x]);
+			strcat(msg, "'");
+			count++;
 		      }
 		}
-	      yyerror (yymsg);
-	      YYSTACK_FREE (yymsg);
+	      yyerror(msg);
+	      free(msg);
 	    }
 	  else
-	    yyerror ("syntax error; also virtual memory exhausted");
+	    yyerror ("parse error; also virtual memory exceeded");
 	}
       else
 #endif /* YYERROR_VERBOSE */
-	yyerror ("syntax error");
+	yyerror("parse error");
     }
 
-
+  goto yyerrlab1;
+yyerrlab1:   /* here on error raised explicitly by an action */
 
   if (yyerrstatus == 3)
     {
-      /* If just tried and failed to reuse lookahead token after an
-	 error, discard it.  */
+      /* if just tried and failed to reuse lookahead token after an error, discard it.  */
 
-      /* Return failure if at end of input.  */
+      /* return failure if at end of input */
       if (yychar == YYEOF)
-        {
-	  /* Pop the error token.  */
-          YYPOPSTACK;
-	  /* Pop the rest of the stack.  */
-	  while (yyss < yyssp)
-	    {
-	      YYDSYMPRINTF ("Error: popping", yystos[*yyssp], yyvsp, yylsp);
-	      yydestruct (yystos[*yyssp], yyvsp);
-	      YYPOPSTACK;
-	    }
-	  YYABORT;
-        }
+	YYABORT;
 
-      YYDSYMPRINTF ("Error: discarding", yytoken, &yylval, &yylloc);
-      yydestruct (yytoken, &yylval);
-      yychar = YYEMPTY;
+#if YYDEBUG != 0
+      if (yydebug)
+	fprintf(stderr, "Discarding token %d (%s).\n", yychar, yytname[yychar1]);
+#endif
 
+      yychar = YYEMPTY;
     }
 
-  /* Else will try to reuse lookahead token after shifting the error
-     token.  */
-  goto yyerrlab1;
+  /* Else will try to reuse lookahead token
+     after shifting the error token.  */
 
+  yyerrstatus = 3;		/* Each real token shifted decrements this */
 
-/*----------------------------------------------------.
-| yyerrlab1 -- error raised explicitly by an action.  |
-`----------------------------------------------------*/
-yyerrlab1:
-  yyerrstatus = 3;	/* Each real token shifted decrements this.  */
+  goto yyerrhandle;
+
+yyerrdefault:  /* current state does not do anything special for the error token. */
+
+#if 0
+  /* This is wrong; only states that explicitly want error tokens
+     should shift them.  */
+  yyn = yydefact[yystate];  /* If its default is to accept any token, ok.  Otherwise pop it.*/
+  if (yyn) goto yydefault;
+#endif
 
-  for (;;)
+yyerrpop:   /* pop the current state because it cannot handle the error token */
+
+  if (yyssp == yyss) YYABORT;
+  yyvsp--;
+  yystate = *--yyssp;
+#ifdef YYLSP_NEEDED
+  yylsp--;
+#endif
+
+#if YYDEBUG != 0
+  if (yydebug)
     {
-      yyn = yypact[yystate];
-      if (yyn != YYPACT_NINF)
-	{
-	  yyn += YYTERROR;
-	  if (0 <= yyn && yyn <= YYLAST && yycheck[yyn] == YYTERROR)
-	    {
-	      yyn = yytable[yyn];
-	      if (0 < yyn)
-		break;
-	    }
-	}
+      short *ssp1 = yyss - 1;
+      fprintf (stderr, "Error: state stack now");
+      while (ssp1 != yyssp)
+	fprintf (stderr, " %d", *++ssp1);
+      fprintf (stderr, "\n");
+    }
+#endif
 
-      /* Pop the current state because it cannot handle the error token.  */
-      if (yyssp == yyss)
-	YYABORT;
+yyerrhandle:
 
-      YYDSYMPRINTF ("Error: popping", yystos[*yyssp], yyvsp, yylsp);
-      yydestruct (yystos[yystate], yyvsp);
-      yyvsp--;
-      yystate = *--yyssp;
+  yyn = yypact[yystate];
+  if (yyn == YYFLAG)
+    goto yyerrdefault;
+
+  yyn += YYTERROR;
+  if (yyn < 0 || yyn > YYLAST || yycheck[yyn] != YYTERROR)
+    goto yyerrdefault;
 
-      YY_STACK_PRINT (yyss, yyssp);
+  yyn = yytable[yyn];
+  if (yyn < 0)
+    {
+      if (yyn == YYFLAG)
+	goto yyerrpop;
+      yyn = -yyn;
+      goto yyreduce;
     }
+  else if (yyn == 0)
+    goto yyerrpop;
 
   if (yyn == YYFINAL)
     YYACCEPT;
 
-  YYDPRINTF ((stderr, "Shifting error token, "));
+#if YYDEBUG != 0
+  if (yydebug)
+    fprintf(stderr, "Shifting error token, ");
+#endif
 
   *++yyvsp = yylval;
-
+#ifdef YYLSP_NEEDED
+  *++yylsp = yylloc;
+#endif
 
   yystate = yyn;
   goto yynewstate;
 
+ yyacceptlab:
+  /* YYACCEPT comes here.  */
+  if (yyfree_stacks)
+    {
+      free (yyss);
+      free (yyvs);
+#ifdef YYLSP_NEEDED
+      free (yyls);
+#endif
+    }
+  return 0;
 
-/*-------------------------------------.
-| yyacceptlab -- YYACCEPT comes here.  |
-`-------------------------------------*/
-yyacceptlab:
-  yyresult = 0;
-  goto yyreturn;
-
-/*-----------------------------------.
-| yyabortlab -- YYABORT comes here.  |
-`-----------------------------------*/
-yyabortlab:
-  yyresult = 1;
-  goto yyreturn;
-
-#ifndef yyoverflow
-/*----------------------------------------------.
-| yyoverflowlab -- parser overflow comes here.  |
-`----------------------------------------------*/
-yyoverflowlab:
-  yyerror ("parser stack overflow");
-  yyresult = 2;
-  /* Fall through.  */
-#endif
-
-yyreturn:
-#ifndef yyoverflow
-  if (yyss != yyssa)
-    YYSTACK_FREE (yyss);
+ yyabortlab:
+  /* YYABORT comes here.  */
+  if (yyfree_stacks)
+    {
+      free (yyss);
+      free (yyvs);
+#ifdef YYLSP_NEEDED
+      free (yyls);
 #endif
-  return yyresult;
+    }
+  return 1;
 }
-
-
-#line 633 "/home/vadve/criswell/llvm/utils/TableGen/FileParser.y"
+#line 632 "/Volumes/ProjectsDisk/cvs/llvm/utils/TableGen/FileParser.y"
 
 
 int yyerror(const char *ErrorMsg) {
   err() << "Error parsing: " << ErrorMsg << "\n";
   exit(1);
 }
-


Index: llvm/utils/TableGen/FileParser.h.cvs
diff -u llvm/utils/TableGen/FileParser.h.cvs:1.1 llvm/utils/TableGen/FileParser.h.cvs:1.2
--- llvm/utils/TableGen/FileParser.h.cvs:1.1	Wed Feb 15 01:24:01 2006
+++ llvm/utils/TableGen/FileParser.h.cvs	Thu Mar 30 16:51:12 2006
@@ -1,83 +1,4 @@
-/* A Bison parser, made by GNU Bison 1.875.  */
-
-/* Skeleton parser for Yacc-like parsing with Bison,
-   Copyright (C) 1984, 1989, 1990, 2000, 2001, 2002 Free Software Foundation, Inc.
-
-   This program is free software; you can redistribute it and/or modify
-   it under the terms of the GNU General Public License as published by
-   the Free Software Foundation; either version 2, or (at your option)
-   any later version.
-
-   This program is distributed in the hope that it will be useful,
-   but WITHOUT ANY WARRANTY; without even the implied warranty of
-   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-   GNU General Public License for more details.
-
-   You should have received a copy of the GNU General Public License
-   along with this program; if not, write to the Free Software
-   Foundation, Inc., 59 Temple Place - Suite 330,
-   Boston, MA 02111-1307, USA.  */
-
-/* As a special exception, when this file is copied by Bison into a
-   Bison output file, you may use that output file without restriction.
-   This special exception was added by the Free Software Foundation
-   in version 1.24 of Bison.  */
-
-/* Tokens.  */
-#ifndef YYTOKENTYPE
-# define YYTOKENTYPE
-   /* Put the tokens into the symbol table, so that GDB and other debuggers
-      know about them.  */
-   enum yytokentype {
-     INT = 258,
-     BIT = 259,
-     STRING = 260,
-     BITS = 261,
-     LIST = 262,
-     CODE = 263,
-     DAG = 264,
-     CLASS = 265,
-     DEF = 266,
-     FIELD = 267,
-     LET = 268,
-     IN = 269,
-     SHLTOK = 270,
-     SRATOK = 271,
-     SRLTOK = 272,
-     INTVAL = 273,
-     ID = 274,
-     VARNAME = 275,
-     STRVAL = 276,
-     CODEFRAGMENT = 277
-   };
-#endif
-#define INT 258
-#define BIT 259
-#define STRING 260
-#define BITS 261
-#define LIST 262
-#define CODE 263
-#define DAG 264
-#define CLASS 265
-#define DEF 266
-#define FIELD 267
-#define LET 268
-#define IN 269
-#define SHLTOK 270
-#define SRATOK 271
-#define SRLTOK 272
-#define INTVAL 273
-#define ID 274
-#define VARNAME 275
-#define STRVAL 276
-#define CODEFRAGMENT 277
-
-
-
-
-#if ! defined (YYSTYPE) && ! defined (YYSTYPE_IS_DECLARED)
-#line 189 "/home/vadve/criswell/llvm/utils/TableGen/FileParser.y"
-typedef union YYSTYPE {
+typedef union {
   std::string*                StrVal;
   int                         IntVal;
   llvm::RecTy*                Ty;
@@ -89,14 +10,26 @@
   std::vector<SubClassRefTy>* SubClassList;
   std::vector<std::pair<llvm::Init*, std::string> >* DagValueList;
 } YYSTYPE;
-/* Line 1240 of yacc.c.  */
-#line 93 "FileParser.tab.h"
-# define yystype YYSTYPE /* obsolescent; will be withdrawn */
-# define YYSTYPE_IS_DECLARED 1
-# define YYSTYPE_IS_TRIVIAL 1
-#endif
-
-extern YYSTYPE Filelval;
-
+#define	INT	257
+#define	BIT	258
+#define	STRING	259
+#define	BITS	260
+#define	LIST	261
+#define	CODE	262
+#define	DAG	263
+#define	CLASS	264
+#define	DEF	265
+#define	FIELD	266
+#define	LET	267
+#define	IN	268
+#define	SHLTOK	269
+#define	SRATOK	270
+#define	SRLTOK	271
+#define	INTVAL	272
+#define	ID	273
+#define	VARNAME	274
+#define	STRVAL	275
+#define	CODEFRAGMENT	276
 
 
+extern YYSTYPE Filelval;


Index: llvm/utils/TableGen/FileParser.y.cvs
diff -u llvm/utils/TableGen/FileParser.y.cvs:1.1 llvm/utils/TableGen/FileParser.y.cvs:1.2
--- llvm/utils/TableGen/FileParser.y.cvs:1.1	Wed Feb 15 01:24:01 2006
+++ llvm/utils/TableGen/FileParser.y.cvs	Thu Mar 30 16:51:12 2006
@@ -210,7 +210,7 @@
 %type <SubClassRef>  SubClassRef
 %type <SubClassList> ClassList ClassListNE
 %type <IntVal>       OptPrefix
-%type <Initializer>  Value OptValue
+%type <Initializer>  Value OptValue IDValue
 %type <DagValueList> DagArgList DagArgListNE
 %type <FieldList>    ValueList ValueListNE
 %type <BitList>      BitList OptBitList RBitList
@@ -253,7 +253,26 @@
 
 OptValue : /*empty*/ { $$ = 0; } | '=' Value { $$ = $2; };
 
-Value : INTVAL {
+IDValue : ID {
+  if (const RecordVal *RV = (CurRec ? CurRec->getValue(*$1) : 0)) {
+    $$ = new VarInit(*$1, RV->getType());
+  } else if (CurRec && CurRec->isTemplateArg(CurRec->getName()+":"+*$1)) {
+    const RecordVal *RV = CurRec->getValue(CurRec->getName()+":"+*$1);
+    assert(RV && "Template arg doesn't exist??");
+    $$ = new VarInit(CurRec->getName()+":"+*$1, RV->getType());
+  } else if (Record *D = Records.getDef(*$1)) {
+    $$ = new DefInit(D);
+  } else {
+    err() << "Variable not defined: '" << *$1 << "'!\n";
+    exit(1);
+  }
+  
+  delete $1;
+};
+
+Value : IDValue {
+    $$ = $1;
+  } | INTVAL {
     $$ = new IntInit($1);
   } | STRVAL {
     $$ = new StringInit(*$1);
@@ -304,21 +323,6 @@
     
     // Restore the old CurRec
     CurRec = OldRec;
-  } | ID {
-    if (const RecordVal *RV = (CurRec ? CurRec->getValue(*$1) : 0)) {
-      $$ = new VarInit(*$1, RV->getType());
-    } else if (CurRec && CurRec->isTemplateArg(CurRec->getName()+":"+*$1)) {
-      const RecordVal *RV = CurRec->getValue(CurRec->getName()+":"+*$1);
-      assert(RV && "Template arg doesn't exist??");
-      $$ = new VarInit(CurRec->getName()+":"+*$1, RV->getType());
-    } else if (Record *D = Records.getDef(*$1)) {
-      $$ = new DefInit(D);
-    } else {
-      err() << "Variable not defined: '" << *$1 << "'!\n";
-      exit(1);
-    }
-    
-    delete $1;
   } | Value '{' BitList '}' {
     $$ = $1->convertInitializerBitRange(*$3);
     if ($$ == 0) {
@@ -336,14 +340,9 @@
     }
     $$ = new FieldInit($1, *$3);
     delete $3;
-  } | '(' ID DagArgList ')' {
-    Record *D = Records.getDef(*$2);
-    if (D == 0) {
-      err() << "Invalid def '" << *$2 << "'!\n";
-      exit(1);
-    }
-    $$ = new DagInit(D, *$3);
-    delete $2; delete $3;
+  } | '(' IDValue DagArgList ')' {
+    $$ = new DagInit($2, *$3);
+    delete $3;
   } | Value '[' BitList ']' {
     std::reverse($3->begin(), $3->end());
     $$ = $1->convertInitListSlice(*$3);





From lattner at cs.uiuc.edu  Thu Mar 30 17:07:49 2006
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Thu, 30 Mar 2006 17:07:49 -0600
Subject: [llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCInstrAltivec.td 
Message-ID: <200603302307.RAA05367@zion.cs.uiuc.edu>



Changes in directory llvm/lib/Target/PowerPC:

PPCInstrAltivec.td updated: 1.18 -> 1.19
---
Log message:

Add a bunch of new instructions for intrinsics.


---
Diffs of the changes:  (+87 -6)

 PPCInstrAltivec.td |   93 +++++++++++++++++++++++++++++++++++++++++++++++++----
 1 files changed, 87 insertions(+), 6 deletions(-)


Index: llvm/lib/Target/PowerPC/PPCInstrAltivec.td
diff -u llvm/lib/Target/PowerPC/PPCInstrAltivec.td:1.18 llvm/lib/Target/PowerPC/PPCInstrAltivec.td:1.19
--- llvm/lib/Target/PowerPC/PPCInstrAltivec.td:1.18	Mon Mar 27 22:18:18 2006
+++ llvm/lib/Target/PowerPC/PPCInstrAltivec.td	Thu Mar 30 17:07:36 2006
@@ -84,12 +84,14 @@
                    [(set VRRC:$vD, (int_ppc_altivec_lvxl xoaddr:$src))]>;
 }
 
-def LVSL : XForm_1<31,   6, (ops VRRC:$vD,  GPRC:$base, GPRC:$rA),
-                   "lvsl $vD, $base, $rA", LdStGeneral,
-                   []>, PPC970_Unit_LSU;
-def LVSR : XForm_1<31,  38, (ops VRRC:$vD,  GPRC:$base, GPRC:$rA),
-                   "lvsl $vD, $base, $rA", LdStGeneral,
-                   []>, PPC970_Unit_LSU;
+def LVSL : XForm_1<31,   6, (ops VRRC:$vD, memrr:$src),
+                   "lvsl $vD, $src", LdStGeneral,
+                   [(set VRRC:$vD, (int_ppc_altivec_lvsl xoaddr:$src))]>,
+                   PPC970_Unit_LSU;
+def LVSR : XForm_1<31,  38, (ops VRRC:$vD, memrr:$src),
+                   "lvsl $vD, $src", LdStGeneral,
+                   [(set VRRC:$vD, (int_ppc_altivec_lvsr xoaddr:$src))]>,
+                   PPC970_Unit_LSU;
 
 let isStore = 1, noResults = 1, PPC970_Unit = 2 in {   // Stores.
 def STVEBX: XForm_8<31, 135, (ops VRRC:$rS, memrr:$dst),
@@ -236,6 +238,29 @@
                       "vmrglw $vD, $vA, $vB", VecFP,
                       [(set VRRC:$vD,
                        (int_ppc_altivec_vmrglw VRRC:$vA, VRRC:$vB))]>;
+
+def VMULESB : VXForm_1<776, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
+                       "vmulesb $vD, $vA, $vB", VecFP,
+                       [(set VRRC:$vD,
+                            (int_ppc_altivec_vmulesb VRRC:$vA, VRRC:$vB))]>;
+def VMULESH : VXForm_1<840, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
+                       "vmulesh $vD, $vA, $vB", VecFP,
+                       [(set VRRC:$vD,
+                            (int_ppc_altivec_vmulesh VRRC:$vA, VRRC:$vB))]>;
+def VMULEUB : VXForm_1<520, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
+                       "vmuleub $vD, $vA, $vB", VecFP,
+                       [(set VRRC:$vD,
+                            (int_ppc_altivec_vmuleub VRRC:$vA, VRRC:$vB))]>;
+def VMULEUH : VXForm_1<584, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
+                       "vmuleuh $vD, $vA, $vB", VecFP,
+                       [(set VRRC:$vD,
+                            (int_ppc_altivec_vmuleuh VRRC:$vA, VRRC:$vB))]>;
+def VMULOSB : VXForm_1<264, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
+                       "vmulosb $vD, $vA, $vB", VecFP,
+                       [(set VRRC:$vD,
+                            (int_ppc_altivec_vmulosb VRRC:$vA, VRRC:$vB))]>;
+                       
+                       
 def VREFP  : VXForm_2<266, (ops VRRC:$vD, VRRC:$vB),
                       "vrefp $vD, $vB", VecFP,
                       [(set VRRC:$vD, (int_ppc_altivec_vrefp VRRC:$vB))]>;
@@ -414,6 +439,62 @@
                        "vspltisw $vD, $SIMM", VecPerm,
                        [(set VRRC:$vD, (v4f32 vecspltisw:$SIMM))]>;
 
+// Vector Pack.
+def VPKPX   : VXForm_1<782, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
+                       "vpkpx $vD, $vA, $vB", VecFP,
+                       [(set VRRC:$vD,
+                            (int_ppc_altivec_vpkpx VRRC:$vA, VRRC:$vB))]>;
+def VPKSHSS : VXForm_1<398, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
+                       "vpkshss $vD, $vA, $vB", VecFP,
+                       [(set VRRC:$vD,
+                            (int_ppc_altivec_vpkshss VRRC:$vA, VRRC:$vB))]>;
+def VPKSHUS : VXForm_1<270, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
+                       "vpkshus $vD, $vA, $vB", VecFP,
+                       [(set VRRC:$vD,
+                            (int_ppc_altivec_vpkshus VRRC:$vA, VRRC:$vB))]>;
+def VPKSWSS : VXForm_1<462, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
+                       "vpkswss $vD, $vA, $vB", VecFP,
+                       [(set VRRC:$vD,
+                            (int_ppc_altivec_vpkswss VRRC:$vA, VRRC:$vB))]>;
+def VPKSWUS : VXForm_1<334, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
+                       "vpkswus $vD, $vA, $vB", VecFP,
+                       [(set VRRC:$vD,
+                            (int_ppc_altivec_vpkswus VRRC:$vA, VRRC:$vB))]>;
+def VPKUHUM : VXForm_1<14, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
+                       "vpkuhum $vD, $vA, $vB", VecFP,
+                       [/*TODO*/]>;
+def VPKUHUS : VXForm_1<142, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
+                       "vpkuhus $vD, $vA, $vB", VecFP,
+                       [(set VRRC:$vD,
+                            (int_ppc_altivec_vpkuhus VRRC:$vA, VRRC:$vB))]>;
+def VPKUWUM : VXForm_1<78, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
+                       "vpkuwum $vD, $vA, $vB", VecFP,
+                       [/*TODO*/]>;
+def VPKUWUS : VXForm_1<206, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
+                       "vpkuwus $vD, $vA, $vB", VecFP,
+                       [(set VRRC:$vD,
+                            (int_ppc_altivec_vpkuwus VRRC:$vA, VRRC:$vB))]>;
+
+// Vector Unpack.
+def VUPKHPX : VXForm_2<846, (ops VRRC:$vD, VRRC:$vB),
+                       "vupkhpx $vD, $vB", VecFP,
+                       [(set VRRC:$vD, (int_ppc_altivec_vupkhpx VRRC:$vB))]>;
+def VUPKHSB : VXForm_2<526, (ops VRRC:$vD, VRRC:$vB),
+                       "vupkhsb $vD, $vB", VecFP,
+                       [(set VRRC:$vD, (int_ppc_altivec_vupkhsb VRRC:$vB))]>;
+def VUPKHSH : VXForm_2<590, (ops VRRC:$vD, VRRC:$vB),
+                       "vupkhsh $vD, $vB", VecFP,
+                       [(set VRRC:$vD, (int_ppc_altivec_vupkhsh VRRC:$vB))]>;
+def VUPKLPX : VXForm_2<974, (ops VRRC:$vD, VRRC:$vB),
+                       "vupklpx $vD, $vB", VecFP,
+                       [(set VRRC:$vD, (int_ppc_altivec_vupklpx VRRC:$vB))]>;
+def VUPKLSB : VXForm_2<654, (ops VRRC:$vD, VRRC:$vB),
+                       "vupklsb $vD, $vB", VecFP,
+                       [(set VRRC:$vD, (int_ppc_altivec_vupklsb VRRC:$vB))]>;
+def VUPKLSH : VXForm_2<718, (ops VRRC:$vD, VRRC:$vB),
+                       "vupklsh $vD, $vB", VecFP,
+                       [(set VRRC:$vD, (int_ppc_altivec_vupklsh VRRC:$vB))]>;
+
 
 // Altivec Comparisons.
 





From lattner at cs.uiuc.edu  Thu Mar 30 17:21:39 2006
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Thu, 30 Mar 2006 17:21:39 -0600
Subject: [llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCInstrAltivec.td 
Message-ID: <200603302321.RAA05474@zion.cs.uiuc.edu>



Changes in directory llvm/lib/Target/PowerPC:

PPCInstrAltivec.td updated: 1.19 -> 1.20
---
Log message:

Use a new tblgen feature to significantly shrinkify instruction definitions that
directly correspond to intrinsics.


---
Diffs of the changes:  (+46 -108)

 PPCInstrAltivec.td |  154 +++++++++++++++--------------------------------------
 1 files changed, 46 insertions(+), 108 deletions(-)


Index: llvm/lib/Target/PowerPC/PPCInstrAltivec.td
diff -u llvm/lib/Target/PowerPC/PPCInstrAltivec.td:1.19 llvm/lib/Target/PowerPC/PPCInstrAltivec.td:1.20
--- llvm/lib/Target/PowerPC/PPCInstrAltivec.td:1.19	Thu Mar 30 17:07:36 2006
+++ llvm/lib/Target/PowerPC/PPCInstrAltivec.td	Thu Mar 30 17:21:27 2006
@@ -61,6 +61,19 @@
 }
 
 //===----------------------------------------------------------------------===//
+// Helpers for defining instructions that directly correspond to intrinsics.
+
+// VX1_Int - A VXForm_1 intrinsic definition.
+class VX1_Int<bits<11> xo, string asmstr, Intrinsic IntID>
+  : VXForm_1<xo, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB), asmstr, VecFP,
+             [(set VRRC:$vD, (IntID VRRC:$vA, VRRC:$vB))]>;
+
+// VX2_Int - A VXForm_2 intrinsic definition.
+class VX2_Int<bits<11> xo, string asmstr, Intrinsic IntID>
+  : VXForm_2<xo, (ops VRRC:$vD, VRRC:$vB), asmstr, VecFP,
+             [(set VRRC:$vD, (IntID VRRC:$vB))]>;
+
+//===----------------------------------------------------------------------===//
 // Instruction Definitions.
 
 def IMPLICIT_DEF_VRRC : Pseudo<(ops VRRC:$rD), "; $rD = IMPLICIT_DEF_VRRC",
@@ -222,71 +235,31 @@
 def VMINFP : VXForm_1<1098, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
                       "vminfp $vD, $vA, $vB", VecFP,
                       []>;
-def VMRGHH : VXForm_1<76, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
-                      "vmrghh $vD, $vA, $vB", VecFP,
-                      [(set VRRC:$vD,
-                       (int_ppc_altivec_vmrghh VRRC:$vA, VRRC:$vB))]>;
-def VMRGHW : VXForm_1<140, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
-                      "vmrghw $vD, $vA, $vB", VecFP,
-                      [(set VRRC:$vD,
-                       (int_ppc_altivec_vmrghw VRRC:$vA, VRRC:$vB))]>;
-def VMRGLH : VXForm_1<332, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
-                      "vmrglh $vD, $vA, $vB", VecFP,
-                      [(set VRRC:$vD,
-                       (int_ppc_altivec_vmrglh VRRC:$vA, VRRC:$vB))]>;
-def VMRGLW : VXForm_1<396, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
-                      "vmrglw $vD, $vA, $vB", VecFP,
-                      [(set VRRC:$vD,
-                       (int_ppc_altivec_vmrglw VRRC:$vA, VRRC:$vB))]>;
 
-def VMULESB : VXForm_1<776, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
-                       "vmulesb $vD, $vA, $vB", VecFP,
-                       [(set VRRC:$vD,
-                            (int_ppc_altivec_vmulesb VRRC:$vA, VRRC:$vB))]>;
-def VMULESH : VXForm_1<840, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
-                       "vmulesh $vD, $vA, $vB", VecFP,
-                       [(set VRRC:$vD,
-                            (int_ppc_altivec_vmulesh VRRC:$vA, VRRC:$vB))]>;
-def VMULEUB : VXForm_1<520, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
-                       "vmuleub $vD, $vA, $vB", VecFP,
-                       [(set VRRC:$vD,
-                            (int_ppc_altivec_vmuleub VRRC:$vA, VRRC:$vB))]>;
-def VMULEUH : VXForm_1<584, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
-                       "vmuleuh $vD, $vA, $vB", VecFP,
-                       [(set VRRC:$vD,
-                            (int_ppc_altivec_vmuleuh VRRC:$vA, VRRC:$vB))]>;
-def VMULOSB : VXForm_1<264, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
-                       "vmulosb $vD, $vA, $vB", VecFP,
-                       [(set VRRC:$vD,
-                            (int_ppc_altivec_vmulosb VRRC:$vA, VRRC:$vB))]>;
-                       
+
+def VMRGHH : VX1_Int<76 , "vmrghh $vD, $vA, $vB", int_ppc_altivec_vmrghh>;
+def VMRGHW : VX1_Int<140, "vmrghw $vD, $vA, $vB", int_ppc_altivec_vmrghw>;
+def VMRGLH : VX1_Int<332, "vmrglh $vD, $vA, $vB", int_ppc_altivec_vmrglh>;
+def VMRGLW : VX1_Int<396, "vmrglw $vD, $vA, $vB", int_ppc_altivec_vmrglw>;
+
+def VMULESB : VX1_Int<776, "vmulesb $vD, $vA, $vB", int_ppc_altivec_vmulesb>;
+def VMULESH : VX1_Int<840, "vmulesh $vD, $vA, $vB", int_ppc_altivec_vmulesh>;
+def VMULEUB : VX1_Int<520, "vmuleub $vD, $vA, $vB", int_ppc_altivec_vmuleub>;
+def VMULEUH : VX1_Int<584, "vmuleuh $vD, $vA, $vB", int_ppc_altivec_vmuleuh>;
+def VMULOSB : VX1_Int<264, "vmulosb $vD, $vA, $vB", int_ppc_altivec_vmulosb>;
                        
-def VREFP  : VXForm_2<266, (ops VRRC:$vD, VRRC:$vB),
-                      "vrefp $vD, $vB", VecFP,
-                      [(set VRRC:$vD, (int_ppc_altivec_vrefp VRRC:$vB))]>;
-def VRFIM  : VXForm_2<714, (ops VRRC:$vD, VRRC:$vB),
-                      "vrfim $vD, $vB", VecFP,
-                      [(set VRRC:$vD, (int_ppc_altivec_vrfim VRRC:$vB))]>;
-def VRFIN  : VXForm_2<522, (ops VRRC:$vD, VRRC:$vB),
-                      "vrfin $vD, $vB", VecFP,
-                      [(set VRRC:$vD, (int_ppc_altivec_vrfin VRRC:$vB))]>;
-def VRFIP  : VXForm_2<650, (ops VRRC:$vD, VRRC:$vB),
-                      "vrfip $vD, $vB", VecFP,
-                      [(set VRRC:$vD, (int_ppc_altivec_vrfip VRRC:$vB))]>;
-def VRFIZ  : VXForm_2<586, (ops VRRC:$vD, VRRC:$vB),
-                      "vrfiz $vD, $vB", VecFP,
-                      [(set VRRC:$vD, (int_ppc_altivec_vrfiz VRRC:$vB))]>;
-def VRSQRTEFP : VXForm_2<330, (ops VRRC:$vD, VRRC:$vB),
-                         "vrsqrtefp $vD, $vB", VecFP,
-                         [(set VRRC:$vD,(int_ppc_altivec_vrsqrtefp VRRC:$vB))]>;
-def VSUBCUW : VXForm_1<74, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
-                       "vsubcuw $vD, $vA, $vB", VecFP,
-                       [(set VRRC:$vD,
-                             (int_ppc_altivec_vsubcuw VRRC:$vA, VRRC:$vB))]>;
-def VSUBFP : VXForm_1<74, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
-                      "vsubfp $vD, $vA, $vB", VecFP,
+def VREFP     : VX2_Int<266, "vrefp $vD, $vB",     int_ppc_altivec_vrefp>;
+def VRFIM     : VX2_Int<714, "vrfim $vD, $vB",     int_ppc_altivec_vrfim>;
+def VRFIN     : VX2_Int<522, "vrfin $vD, $vB",     int_ppc_altivec_vrfin>;
+def VRFIP     : VX2_Int<650, "vrfip $vD, $vB",     int_ppc_altivec_vrfip>;
+def VRFIZ     : VX2_Int<586, "vrfiz $vD, $vB",     int_ppc_altivec_vrfiz>;
+def VRSQRTEFP : VX2_Int<330, "vrsqrtefp $vD, $vB", int_ppc_altivec_vrsqrtefp>;
+
+def VSUBCUW : VX1_Int<74, "vsubcuw $vD, $vA, $vB", int_ppc_altivec_vsubcuw>;
+
+def VSUBFP  : VXForm_1<74, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
+                      "vsubfp $vD, $vA, $vB", VecGeneral,
                       [(set VRRC:$vD, (fsub VRRC:$vA, VRRC:$vB))]>;
-                  
 def VSUBUBM : VXForm_1<1024, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
                       "vsububm $vD, $vA, $vB", VecGeneral,
                       [(set VRRC:$vD, (sub (v16i8 VRRC:$vA), VRRC:$vB))]>;
@@ -297,52 +270,17 @@
                       "vsubuwm $vD, $vA, $vB", VecGeneral,
                       [(set VRRC:$vD, (sub (v4i32 VRRC:$vA), VRRC:$vB))]>;
                       
-def VSUBSBS : VXForm_1<1792, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
-                       "vsubsbs $vD, $vA, $vB", VecFP,
-                       [(set VRRC:$vD,
-                             (int_ppc_altivec_vsubsbs VRRC:$vA, VRRC:$vB))]>;
-def VSUBSHS : VXForm_1<1856, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
-                       "vsubshs $vD, $vA, $vB", VecFP,
-                       [(set VRRC:$vD,
-                             (int_ppc_altivec_vsubshs VRRC:$vA, VRRC:$vB))]>;
-def VSUBSWS : VXForm_1<1920, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
-                       "vsubsws $vD, $vA, $vB", VecFP,
-                       [(set VRRC:$vD,
-                             (int_ppc_altivec_vsubsws VRRC:$vA, VRRC:$vB))]>;
-                             
-def VSUBUBS : VXForm_1<1536, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
-                       "vsububs $vD, $vA, $vB", VecFP,
-                       [(set VRRC:$vD,
-                             (int_ppc_altivec_vsububs VRRC:$vA, VRRC:$vB))]>;
-def VSUBUHS : VXForm_1<1600, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
-                       "vsubuhs $vD, $vA, $vB", VecFP,
-                       [(set VRRC:$vD,
-                             (int_ppc_altivec_vsubuhs VRRC:$vA, VRRC:$vB))]>;
-def VSUBUWS : VXForm_1<1664, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
-                       "vsubuws $vD, $vA, $vB", VecFP,
-                       [(set VRRC:$vD,
-                             (int_ppc_altivec_vsubuws VRRC:$vA, VRRC:$vB))]>;
-
-def VSUMSWS : VXForm_1<1928, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
-                       "vsumsws $vD, $vA, $vB", VecFP,
-                       [(set VRRC:$vD,
-                             (int_ppc_altivec_vsumsws VRRC:$vA, VRRC:$vB))]>;
-def VSUM2SWS: VXForm_1<1672, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
-                       "vsum2sws $vD, $vA, $vB", VecFP,
-                       [(set VRRC:$vD,
-                             (int_ppc_altivec_vsum2sws VRRC:$vA, VRRC:$vB))]>;
-def VSUM4SBS: VXForm_1<1672, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
-                       "vsum4sbs $vD, $vA, $vB", VecFP,
-                       [(set VRRC:$vD,
-                             (int_ppc_altivec_vsum4sbs VRRC:$vA, VRRC:$vB))]>;
-def VSUM4SHS: VXForm_1<1608, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
-                       "vsum4shs $vD, $vA, $vB", VecFP,
-                       [(set VRRC:$vD,
-                             (int_ppc_altivec_vsum4shs VRRC:$vA, VRRC:$vB))]>;
-def VSUM4UBS: VXForm_1<1544, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
-                       "vsum4ubs $vD, $vA, $vB", VecFP,
-                       [(set VRRC:$vD,
-                             (int_ppc_altivec_vsum4ubs VRRC:$vA, VRRC:$vB))]>;
+def VSUBSBS : VX1_Int<1792, "vsubsbs $vD, $vA, $vB", int_ppc_altivec_vsubsbs>;
+def VSUBSHS : VX1_Int<1856, "vsubshs $vD, $vA, $vB", int_ppc_altivec_vsubshs>;
+def VSUBSWS : VX1_Int<1920, "vsubsws $vD, $vA, $vB", int_ppc_altivec_vsubsws>;
+def VSUBUBS : VX1_Int<1536, "vsububs $vD, $vA, $vB", int_ppc_altivec_vsububs>;
+def VSUBUHS : VX1_Int<1600, "vsubuhs $vD, $vA, $vB", int_ppc_altivec_vsubuhs>;
+def VSUBUWS : VX1_Int<1664, "vsubuws $vD, $vA, $vB", int_ppc_altivec_vsubuws>;
+def VSUMSWS : VX1_Int<1928, "vsumsws $vD, $vA, $vB", int_ppc_altivec_vsumsws>;
+def VSUM2SWS: VX1_Int<1672, "vsum2sws $vD, $vA, $vB", int_ppc_altivec_vsum2sws>;
+def VSUM4SBS: VX1_Int<1672, "vsum4sbs $vD, $vA, $vB", int_ppc_altivec_vsum4sbs>;
+def VSUM4SHS: VX1_Int<1608, "vsum4shs $vD, $vA, $vB", int_ppc_altivec_vsum4shs>;
+def VSUM4UBS: VX1_Int<1544, "vsum4ubs $vD, $vA, $vB", int_ppc_altivec_vsum4ubs>;
 
 def VNOR : VXForm_1<1284, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
                     "vnor $vD, $vA, $vB", VecFP,





From lattner at cs.uiuc.edu  Thu Mar 30 17:33:10 2006
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Thu, 30 Mar 2006 17:33:10 -0600
Subject: [llvm-commits] CVS: llvm/include/llvm/IntrinsicsPowerPC.td 
Message-ID: <200603302333.RAA05547@zion.cs.uiuc.edu>



Changes in directory llvm/include/llvm:

IntrinsicsPowerPC.td updated: 1.10 -> 1.11
---
Log message:

fix incorrect prototypes


---
Diffs of the changes:  (+12 -12)

 IntrinsicsPowerPC.td |   24 ++++++++++++------------
 1 files changed, 12 insertions(+), 12 deletions(-)


Index: llvm/include/llvm/IntrinsicsPowerPC.td
diff -u llvm/include/llvm/IntrinsicsPowerPC.td:1.10 llvm/include/llvm/IntrinsicsPowerPC.td:1.11
--- llvm/include/llvm/IntrinsicsPowerPC.td:1.10	Thu Mar 30 12:52:02 2006
+++ llvm/include/llvm/IntrinsicsPowerPC.td	Thu Mar 30 17:32:58 2006
@@ -192,23 +192,23 @@
 
   // Vector Multiply Sum Instructions.
   def int_ppc_altivec_vmsummbm : GCCBuiltin<"__builtin_altivec_vmsummbm">,
-            Intrinsic<[llvm_v16i8_ty, llvm_v16i8_ty, llvm_v4i32_ty],
-                      [InstrNoMem]>;
+            Intrinsic<[llvm_v4i32_ty, llvm_v16i8_ty, llvm_v16i8_ty,
+                       llvm_v4i32_ty], [InstrNoMem]>;
   def int_ppc_altivec_vmsumshm : GCCBuiltin<"__builtin_altivec_vmsumshm">,
-            Intrinsic<[llvm_v8i16_ty, llvm_v8i16_ty, llvm_v4i32_ty],
-                      [InstrNoMem]>;
+            Intrinsic<[llvm_v4i32_ty, llvm_v8i16_ty, llvm_v8i16_ty,
+                       llvm_v4i32_ty], [InstrNoMem]>;
   def int_ppc_altivec_vmsumshs : GCCBuiltin<"__builtin_altivec_vmsumshs">,
-            Intrinsic<[llvm_v8i16_ty, llvm_v8i16_ty, llvm_v4i32_ty],
-                      [InstrNoMem]>;
+            Intrinsic<[llvm_v4i32_ty, llvm_v8i16_ty, llvm_v8i16_ty, 
+                       llvm_v4i32_ty], [InstrNoMem]>;
   def int_ppc_altivec_vmsumubm : GCCBuiltin<"__builtin_altivec_vmsumubm">,
-            Intrinsic<[llvm_v16i8_ty, llvm_v16i8_ty, llvm_v4i32_ty],
-                      [InstrNoMem]>;
+            Intrinsic<[llvm_v4i32_ty, llvm_v16i8_ty, llvm_v16i8_ty, 
+                       llvm_v4i32_ty], [InstrNoMem]>;
   def int_ppc_altivec_vmsumuhm : GCCBuiltin<"__builtin_altivec_vmsumuhm">,
-            Intrinsic<[llvm_v8i16_ty, llvm_v8i16_ty, llvm_v4i32_ty],
-                      [InstrNoMem]>;
+            Intrinsic<[llvm_v4i32_ty, llvm_v8i16_ty, llvm_v8i16_ty,
+                       llvm_v4i32_ty], [InstrNoMem]>;
   def int_ppc_altivec_vmsumuhs : GCCBuiltin<"__builtin_altivec_vmsumuhs">,
-            Intrinsic<[llvm_v8i16_ty, llvm_v8i16_ty, llvm_v4i32_ty],
-                      [InstrNoMem]>;
+            Intrinsic<[llvm_v4i32_ty, llvm_v8i16_ty, llvm_v8i16_ty,
+                       llvm_v4i32_ty], [InstrNoMem]>;
 
   // Vector Multiply Instructions.
   def int_ppc_altivec_vmulesb : GCCBuiltin<"__builtin_altivec_vmulesb">,





From lattner at cs.uiuc.edu  Thu Mar 30 17:39:18 2006
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Thu, 30 Mar 2006 17:39:18 -0600
Subject: [llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCInstrAltivec.td 
Message-ID: <200603302339.RAA05622@zion.cs.uiuc.edu>



Changes in directory llvm/lib/Target/PowerPC:

PPCInstrAltivec.td updated: 1.20 -> 1.21
---
Log message:

Add the rest of the vmul instructions and the vmulsum* instructions.


---
Diffs of the changes:  (+15 -1)

 PPCInstrAltivec.td |   16 +++++++++++++++-
 1 files changed, 15 insertions(+), 1 deletion(-)


Index: llvm/lib/Target/PowerPC/PPCInstrAltivec.td
diff -u llvm/lib/Target/PowerPC/PPCInstrAltivec.td:1.20 llvm/lib/Target/PowerPC/PPCInstrAltivec.td:1.21
--- llvm/lib/Target/PowerPC/PPCInstrAltivec.td:1.20	Thu Mar 30 17:21:27 2006
+++ llvm/lib/Target/PowerPC/PPCInstrAltivec.td	Thu Mar 30 17:39:06 2006
@@ -63,6 +63,11 @@
 //===----------------------------------------------------------------------===//
 // Helpers for defining instructions that directly correspond to intrinsics.
 
+// VA1a_Int - A VAForm_1a intrinsic definition.
+class VA1a_Int<bits<6> xo, string asmstr, Intrinsic IntID>
+  : VAForm_1a<xo, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB, VRRC:$vC), asmstr, VecFP,
+                       [(set VRRC:$vD, (IntID VRRC:$vA, VRRC:$vB, VRRC:$vC))]>;
+
 // VX1_Int - A VXForm_1 intrinsic definition.
 class VX1_Int<bits<11> xo, string asmstr, Intrinsic IntID>
   : VXForm_1<xo, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB), asmstr, VecFP,
@@ -236,17 +241,26 @@
                       "vminfp $vD, $vA, $vB", VecFP,
                       []>;
 
-
 def VMRGHH : VX1_Int<76 , "vmrghh $vD, $vA, $vB", int_ppc_altivec_vmrghh>;
 def VMRGHW : VX1_Int<140, "vmrghw $vD, $vA, $vB", int_ppc_altivec_vmrghw>;
 def VMRGLH : VX1_Int<332, "vmrglh $vD, $vA, $vB", int_ppc_altivec_vmrglh>;
 def VMRGLW : VX1_Int<396, "vmrglw $vD, $vA, $vB", int_ppc_altivec_vmrglw>;
 
+def VMSUMMBM : VA1a_Int<37, "vmsummbm $vD, $vA, $vB, $vC", int_ppc_altivec_vmsummbm>;
+def VMSUMSHM : VA1a_Int<40, "vmsumshm $vD, $vA, $vB, $vC", int_ppc_altivec_vmsumshm>;
+def VMSUMSHS : VA1a_Int<41, "vmsumshs $vD, $vA, $vB, $vC", int_ppc_altivec_vmsumshs>;
+def VMSUMUBM : VA1a_Int<36, "vmsumubm $vD, $vA, $vB, $vC", int_ppc_altivec_vmsumubm>;
+def VMSUMUHM : VA1a_Int<38, "vmsumuhm $vD, $vA, $vB, $vC", int_ppc_altivec_vmsumuhm>;
+def VMSUMUHS : VA1a_Int<39, "vmsumuhs $vD, $vA, $vB, $vC", int_ppc_altivec_vmsumuhs>;
+
 def VMULESB : VX1_Int<776, "vmulesb $vD, $vA, $vB", int_ppc_altivec_vmulesb>;
 def VMULESH : VX1_Int<840, "vmulesh $vD, $vA, $vB", int_ppc_altivec_vmulesh>;
 def VMULEUB : VX1_Int<520, "vmuleub $vD, $vA, $vB", int_ppc_altivec_vmuleub>;
 def VMULEUH : VX1_Int<584, "vmuleuh $vD, $vA, $vB", int_ppc_altivec_vmuleuh>;
 def VMULOSB : VX1_Int<264, "vmulosb $vD, $vA, $vB", int_ppc_altivec_vmulosb>;
+def VMULOSH : VX1_Int<328, "vmulosh $vD, $vA, $vB", int_ppc_altivec_vmulosh>;
+def VMULOUB : VX1_Int<  8, "vmuloub $vD, $vA, $vB", int_ppc_altivec_vmuloub>;
+def VMULOUH : VX1_Int< 72, "vmulouh $vD, $vA, $vB", int_ppc_altivec_vmulouh>;
                        
 def VREFP     : VX2_Int<266, "vrefp $vD, $vB",     int_ppc_altivec_vrefp>;
 def VRFIM     : VX2_Int<714, "vrfim $vD, $vB",     int_ppc_altivec_vrfim>;





From lattner at cs.uiuc.edu  Thu Mar 30 18:28:35 2006
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Thu, 30 Mar 2006 18:28:35 -0600
Subject: [llvm-commits] CVS: llvm/include/llvm/Target/TargetLowering.h 
Message-ID: <200603310028.SAA06308@zion.cs.uiuc.edu>



Changes in directory llvm/include/llvm/Target:

TargetLowering.h updated: 1.63 -> 1.64
---
Log message:

Add a method useful for decimating vectors.


---
Diffs of the changes:  (+10 -0)

 TargetLowering.h |   10 ++++++++++
 1 files changed, 10 insertions(+)


Index: llvm/include/llvm/Target/TargetLowering.h
diff -u llvm/include/llvm/Target/TargetLowering.h:1.63 llvm/include/llvm/Target/TargetLowering.h:1.64
--- llvm/include/llvm/Target/TargetLowering.h:1.63	Wed Mar 22 16:07:06 2006
+++ llvm/include/llvm/Target/TargetLowering.h	Thu Mar 30 18:28:23 2006
@@ -173,6 +173,16 @@
     return TransformToType[VT];
   }
 
+  /// getPackedTypeBreakdown - Packed types are broken down into some number of
+  /// legal scalar types.  For example, <8 x float> maps to 2 MVT::v2f32 values
+  /// with Altivec or SSE1, or 8 promoted MVT::f64 values with the X86 FP stack.
+  /// Similarly, <2 x long> turns into 4 MVT::i32 values with both PPC and X86.
+  ///
+  /// This method returns the number and type of the resultant breakdown.
+  ///
+  MVT::ValueType getPackedTypeBreakdown(const PackedType *PTy, 
+                                        unsigned &NE) const;
+  
   typedef std::vector<double>::const_iterator legal_fpimm_iterator;
   legal_fpimm_iterator legal_fpimm_begin() const {
     return LegalFPImmediates.begin();





From lattner at cs.uiuc.edu  Thu Mar 30 18:29:08 2006
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Thu, 30 Mar 2006 18:29:08 -0600
Subject: [llvm-commits] CVS: llvm/lib/Target/TargetLowering.cpp 
Message-ID: <200603310029.SAA06369@zion.cs.uiuc.edu>



Changes in directory llvm/lib/Target:

TargetLowering.cpp updated: 1.48 -> 1.49
---
Log message:

Implement TargetLowering::getPackedTypeBreakdown


---
Diffs of the changes:  (+41 -0)

 TargetLowering.cpp |   41 +++++++++++++++++++++++++++++++++++++++++
 1 files changed, 41 insertions(+)


Index: llvm/lib/Target/TargetLowering.cpp
diff -u llvm/lib/Target/TargetLowering.cpp:1.48 llvm/lib/Target/TargetLowering.cpp:1.49
--- llvm/lib/Target/TargetLowering.cpp:1.48	Thu Mar 23 17:24:51 2006
+++ llvm/lib/Target/TargetLowering.cpp	Thu Mar 30 18:28:56 2006
@@ -14,6 +14,7 @@
 #include "llvm/Target/TargetLowering.h"
 #include "llvm/Target/TargetMachine.h"
 #include "llvm/Target/MRegisterInfo.h"
+#include "llvm/DerivedTypes.h"
 #include "llvm/CodeGen/SelectionDAG.h"
 #include "llvm/ADT/StringExtras.h"
 #include "llvm/Support/MathExtras.h"
@@ -141,6 +142,46 @@
   return NULL;
 }
 
+/// getPackedTypeBreakdown - Packed types are broken down into some number of
+/// legal scalar types.  For example, <8 x float> maps to 2 MVT::v2f32 values
+/// with Altivec or SSE1, or 8 promoted MVT::f64 values with the X86 FP stack.
+///
+/// This method returns the number and type of the resultant breakdown.
+///
+MVT::ValueType TargetLowering::getPackedTypeBreakdown(const PackedType *PTy, 
+                                                      unsigned &NumVals) const {
+  // Figure out the right, legal destination reg to copy into.
+  unsigned NumElts = PTy->getNumElements();
+  MVT::ValueType EltTy = getValueType(PTy->getElementType());
+  
+  unsigned NumVectorRegs = 1;
+  
+  // Divide the input until we get to a supported size.  This will always
+  // end with a scalar if the target doesn't support vectors.
+  while (NumElts > 1 && !isTypeLegal(getVectorType(EltTy, NumElts))) {
+    NumElts >>= 1;
+    NumVectorRegs <<= 1;
+  }
+  
+  MVT::ValueType VT;
+  if (NumElts == 1)
+    VT = EltTy;
+  else
+    VT = getVectorType(EltTy, NumElts);
+
+  MVT::ValueType DestVT = getTypeToTransformTo(VT);
+  if (DestVT < VT) {
+    // Value is expanded, e.g. i64 -> i16.
+    NumVals = NumVectorRegs*(MVT::getSizeInBits(VT)/MVT::getSizeInBits(DestVT));
+  } else {
+    // Otherwise, promotion or legal types use the same number of registers as
+    // the vector decimated to the appropriate level.
+    NumVals = NumVectorRegs;
+  }
+  
+  return DestVT;
+}
+
 //===----------------------------------------------------------------------===//
 //  Optimization Methods
 //===----------------------------------------------------------------------===//





From evan.cheng at apple.com  Thu Mar 30 18:30:41 2006
From: evan.cheng at apple.com (Evan Cheng)
Date: Thu, 30 Mar 2006 18:30:41 -0600
Subject: [llvm-commits] CVS: llvm/lib/Target/X86/X86ISelLowering.cpp 
Message-ID: <200603310030.SAA06394@zion.cs.uiuc.edu>



Changes in directory llvm/lib/Target/X86:

X86ISelLowering.cpp updated: 1.146 -> 1.147
---
Log message:

Ok for vector_shuffle mask to contain undef elements.


---
Diffs of the changes:  (+120 -56)

 X86ISelLowering.cpp |  176 +++++++++++++++++++++++++++++++++++-----------------
 1 files changed, 120 insertions(+), 56 deletions(-)


Index: llvm/lib/Target/X86/X86ISelLowering.cpp
diff -u llvm/lib/Target/X86/X86ISelLowering.cpp:1.146 llvm/lib/Target/X86/X86ISelLowering.cpp:1.147
--- llvm/lib/Target/X86/X86ISelLowering.cpp:1.146	Thu Mar 30 13:54:57 2006
+++ llvm/lib/Target/X86/X86ISelLowering.cpp	Thu Mar 30 18:30:29 2006
@@ -1400,9 +1400,10 @@
 
   // Check if the value doesn't reference the second vector.
   for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
-    assert(isa<ConstantSDNode>(N->getOperand(i)) &&
-           "Invalid VECTOR_SHUFFLE mask!");
-    if (cast<ConstantSDNode>(N->getOperand(i))->getValue() >= 4)
+    SDOperand Arg = N->getOperand(i);
+    if (Arg.getOpcode() == ISD::UNDEF) continue;
+    assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
+    if (cast<ConstantSDNode>(Arg)->getValue() >= 4)
       return false;
   }
 
@@ -1419,17 +1420,19 @@
 
   // Lower quadword copied in order.
   for (unsigned i = 0; i != 4; ++i) {
-    assert(isa<ConstantSDNode>(N->getOperand(i)) &&
-           "Invalid VECTOR_SHUFFLE mask!");
-    if (cast<ConstantSDNode>(N->getOperand(i))->getValue() != i)
+    SDOperand Arg = N->getOperand(i);
+    if (Arg.getOpcode() == ISD::UNDEF) continue;
+    assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
+    if (cast<ConstantSDNode>(Arg)->getValue() != i)
       return false;
   }
 
   // Upper quadword shuffled.
   for (unsigned i = 4; i != 8; ++i) {
-    assert(isa<ConstantSDNode>(N->getOperand(i)) &&
-           "Invalid VECTOR_SHUFFLE mask!");
-    unsigned Val = cast<ConstantSDNode>(N->getOperand(i))->getValue();
+    SDOperand Arg = N->getOperand(i);
+    if (Arg.getOpcode() == ISD::UNDEF) continue;
+    assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
+    unsigned Val = cast<ConstantSDNode>(Arg)->getValue();
     if (Val < 4 || Val > 7)
       return false;
   }
@@ -1447,17 +1450,19 @@
 
   // Upper quadword copied in order.
   for (unsigned i = 4; i != 8; ++i) {
-    assert(isa<ConstantSDNode>(N->getOperand(i)) &&
-           "Invalid VECTOR_SHUFFLE mask!");
-    if (cast<ConstantSDNode>(N->getOperand(i))->getValue() != i)
+    SDOperand Arg = N->getOperand(i);
+    if (Arg.getOpcode() == ISD::UNDEF) continue;
+    assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
+    if (cast<ConstantSDNode>(Arg)->getValue() != i)
       return false;
   }
 
   // Lower quadword shuffled.
   for (unsigned i = 0; i != 4; ++i) {
-    assert(isa<ConstantSDNode>(N->getOperand(i)) &&
-           "Invalid VECTOR_SHUFFLE mask!");
-    unsigned Val = cast<ConstantSDNode>(N->getOperand(i))->getValue();
+    SDOperand Arg = N->getOperand(i);
+    if (Arg.getOpcode() == ISD::UNDEF) continue;
+    assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
+    unsigned Val = cast<ConstantSDNode>(Arg)->getValue();
     if (Val > 4)
       return false;
   }
@@ -1487,15 +1492,17 @@
 
   // Each half must refer to only one of the vector.
   for (unsigned i = 0; i < 2; ++i) {
-    assert(isa<ConstantSDNode>(N->getOperand(i)) &&
-           "Invalid VECTOR_SHUFFLE mask!");
-    unsigned Val = cast<ConstantSDNode>(N->getOperand(i))->getValue();
+    SDOperand Arg = N->getOperand(i);
+    if (Arg.getOpcode() == ISD::UNDEF) continue;
+    assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
+    unsigned Val = cast<ConstantSDNode>(Arg)->getValue();
     if (Val >= 4) return false;
   }
   for (unsigned i = 2; i < 4; ++i) {
-    assert(isa<ConstantSDNode>(N->getOperand(i)) &&
-           "Invalid VECTOR_SHUFFLE mask!");
-    unsigned Val = cast<ConstantSDNode>(N->getOperand(i))->getValue();
+    SDOperand Arg = N->getOperand(i);
+    if (Arg.getOpcode() == ISD::UNDEF) continue;
+    assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
+    unsigned Val = cast<ConstantSDNode>(Arg)->getValue();
     if (Val < 4) return false;
   }
 
@@ -1515,13 +1522,32 @@
   SDOperand Bit1 = N->getOperand(1);
   SDOperand Bit2 = N->getOperand(2);
   SDOperand Bit3 = N->getOperand(3);
-  assert(isa<ConstantSDNode>(Bit0) && isa<ConstantSDNode>(Bit1) &&
-         isa<ConstantSDNode>(Bit2) && isa<ConstantSDNode>(Bit3) &&
-         "Invalid VECTOR_SHUFFLE mask!");
-  return (cast<ConstantSDNode>(Bit0)->getValue() == 6 &&
-          cast<ConstantSDNode>(Bit1)->getValue() == 7 &&
-          cast<ConstantSDNode>(Bit2)->getValue() == 2 &&
-          cast<ConstantSDNode>(Bit3)->getValue() == 3);
+
+  if (Bit0.getOpcode() != ISD::UNDEF) {
+    assert(isa<ConstantSDNode>(Bit0) && "Invalid VECTOR_SHUFFLE mask!");
+    if (cast<ConstantSDNode>(Bit0)->getValue() != 6)
+      return false;
+  }
+
+  if (Bit1.getOpcode() != ISD::UNDEF) {
+    assert(isa<ConstantSDNode>(Bit1) && "Invalid VECTOR_SHUFFLE mask!");
+    if (cast<ConstantSDNode>(Bit1)->getValue() != 7)
+      return false;
+  }
+
+  if (Bit2.getOpcode() != ISD::UNDEF) {
+    assert(isa<ConstantSDNode>(Bit2) && "Invalid VECTOR_SHUFFLE mask!");
+    if (cast<ConstantSDNode>(Bit2)->getValue() != 2)
+      return false;
+  }
+
+  if (Bit3.getOpcode() != ISD::UNDEF) {
+    assert(isa<ConstantSDNode>(Bit3) && "Invalid VECTOR_SHUFFLE mask!");
+    if (cast<ConstantSDNode>(Bit3)->getValue() != 3)
+      return false;
+  }
+
+  return true;
 }
 
 /// isMOVLHPSMask - Return true if the specified VECTOR_SHUFFLE operand
@@ -1537,13 +1563,32 @@
   SDOperand Bit1 = N->getOperand(1);
   SDOperand Bit2 = N->getOperand(2);
   SDOperand Bit3 = N->getOperand(3);
-  assert(isa<ConstantSDNode>(Bit0) && isa<ConstantSDNode>(Bit1) &&
-         isa<ConstantSDNode>(Bit2) && isa<ConstantSDNode>(Bit3) &&
-         "Invalid VECTOR_SHUFFLE mask!");
-  return (cast<ConstantSDNode>(Bit0)->getValue() == 0 &&
-          cast<ConstantSDNode>(Bit1)->getValue() == 1 &&
-          cast<ConstantSDNode>(Bit2)->getValue() == 4 &&
-          cast<ConstantSDNode>(Bit3)->getValue() == 5);
+
+  if (Bit0.getOpcode() != ISD::UNDEF) {
+    assert(isa<ConstantSDNode>(Bit0) && "Invalid VECTOR_SHUFFLE mask!");
+    if (cast<ConstantSDNode>(Bit0)->getValue() != 0)
+      return false;
+  }
+
+  if (Bit1.getOpcode() != ISD::UNDEF) {
+    assert(isa<ConstantSDNode>(Bit1) && "Invalid VECTOR_SHUFFLE mask!");
+    if (cast<ConstantSDNode>(Bit1)->getValue() != 1)
+      return false;
+  }
+
+  if (Bit2.getOpcode() != ISD::UNDEF) {
+    assert(isa<ConstantSDNode>(Bit2) && "Invalid VECTOR_SHUFFLE mask!");
+    if (cast<ConstantSDNode>(Bit2)->getValue() != 4)
+      return false;
+  }
+
+  if (Bit3.getOpcode() != ISD::UNDEF) {
+    assert(isa<ConstantSDNode>(Bit3) && "Invalid VECTOR_SHUFFLE mask!");
+    if (cast<ConstantSDNode>(Bit3)->getValue() != 5)
+      return false;
+  }
+
+  return true;
 }
 
 /// isUNPCKLMask - Return true if the specified VECTOR_SHUFFLE operand
@@ -1558,12 +1603,18 @@
   for (unsigned i = 0, j = 0; i != NumElems; i += 2, ++j) {
     SDOperand BitI  = N->getOperand(i);
     SDOperand BitI1 = N->getOperand(i+1);
-    assert(isa<ConstantSDNode>(BitI) && isa<ConstantSDNode>(BitI1) &&
-           "Invalid VECTOR_SHUFFLE mask!");
-    if (cast<ConstantSDNode>(BitI)->getValue()  != j)
-      return false;
-    if (cast<ConstantSDNode>(BitI1)->getValue() != j + NumElems)
-      return false;
+
+    if (BitI.getOpcode() != ISD::UNDEF) {
+      assert(isa<ConstantSDNode>(BitI) && "Invalid VECTOR_SHUFFLE mask!");
+      if (cast<ConstantSDNode>(BitI)->getValue() != j)
+        return false;
+    }
+
+    if (BitI1.getOpcode() != ISD::UNDEF) {
+      assert(isa<ConstantSDNode>(BitI1) && "Invalid VECTOR_SHUFFLE mask!");
+      if (cast<ConstantSDNode>(BitI)->getValue() != j + NumElems)
+        return false;
+    }
   }
 
   return true;
@@ -1581,12 +1632,18 @@
   for (unsigned i = 0, j = 0; i != NumElems; i += 2, ++j) {
     SDOperand BitI  = N->getOperand(i);
     SDOperand BitI1 = N->getOperand(i+1);
-    assert(isa<ConstantSDNode>(BitI) && isa<ConstantSDNode>(BitI1) &&
-           "Invalid VECTOR_SHUFFLE mask!");
-    if (cast<ConstantSDNode>(BitI)->getValue()  != j + NumElems/2)
-      return false;
-    if (cast<ConstantSDNode>(BitI1)->getValue() != j + NumElems/2 + NumElems)
-      return false;
+
+    if (BitI.getOpcode() != ISD::UNDEF) {
+      assert(isa<ConstantSDNode>(BitI) && "Invalid VECTOR_SHUFFLE mask!");
+      if (cast<ConstantSDNode>(BitI)->getValue() != j + NumElems/2)
+        return false;
+    }
+
+    if (BitI1.getOpcode() != ISD::UNDEF) {
+      assert(isa<ConstantSDNode>(BitI1) && "Invalid VECTOR_SHUFFLE mask!");
+      if (cast<ConstantSDNode>(BitI)->getValue() != j + NumElems/2 + NumElems)
+        return false;
+    }
   }
 
   return true;
@@ -1606,9 +1663,10 @@
   SDOperand Elt = N->getOperand(0);
   assert(isa<ConstantSDNode>(Elt) && "Invalid VECTOR_SHUFFLE mask!");
   for (unsigned i = 1, e = N->getNumOperands(); i != e; ++i) {
-    assert(isa<ConstantSDNode>(N->getOperand(i)) &&
-           "Invalid VECTOR_SHUFFLE mask!");
-    if (N->getOperand(i) != Elt) return false;
+    SDOperand Arg = N->getOperand(i);
+    if (Arg.getOpcode() == ISD::UNDEF) continue;
+    assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
+    if (Arg != Elt) return false;
   }
 
   // Make sure it is a splat of the first vector operand.
@@ -1623,8 +1681,10 @@
   unsigned Shift = (NumOperands == 4) ? 2 : 1;
   unsigned Mask = 0;
   for (unsigned i = 0; i < NumOperands; ++i) {
-    unsigned Val
-      = cast<ConstantSDNode>(N->getOperand(NumOperands-i-1))->getValue();
+    unsigned Val = 0;
+    SDOperand Arg = N->getOperand(NumOperands-i-1);
+    if (Arg.getOpcode() != ISD::UNDEF)
+      Val = cast<ConstantSDNode>(Arg)->getValue();
     if (Val >= NumOperands) Val -= NumOperands;
     Mask |= Val;
     if (i != NumOperands - 1)
@@ -1641,8 +1701,10 @@
   unsigned Mask = 0;
   // 8 nodes, but we only care about the last 4.
   for (unsigned i = 7; i >= 4; --i) {
-    unsigned Val
-      = cast<ConstantSDNode>(N->getOperand(i))->getValue();
+    unsigned Val = 0;
+    SDOperand Arg = N->getOperand(i);
+    if (Arg.getOpcode() != ISD::UNDEF)
+      Val = cast<ConstantSDNode>(Arg)->getValue();
     Mask |= (Val - 4);
     if (i != 4)
       Mask <<= 2;
@@ -1658,8 +1720,10 @@
   unsigned Mask = 0;
   // 8 nodes, but we only care about the first 4.
   for (int i = 3; i >= 0; --i) {
-    unsigned Val
-      = cast<ConstantSDNode>(N->getOperand(i))->getValue();
+    unsigned Val = 0;
+    SDOperand Arg = N->getOperand(i);
+    if (Arg.getOpcode() != ISD::UNDEF)
+      Val = cast<ConstantSDNode>(Arg)->getValue();
     Mask |= Val;
     if (i != 0)
       Mask <<= 2;





From evan.cheng at apple.com  Thu Mar 30 18:34:09 2006
From: evan.cheng at apple.com (Evan Cheng)
Date: Thu, 30 Mar 2006 18:34:09 -0600
Subject: [llvm-commits] CVS: llvm/lib/Target/X86/X86ISelLowering.cpp 
Message-ID: <200603310034.SAA06464@zion.cs.uiuc.edu>



Changes in directory llvm/lib/Target/X86:

X86ISelLowering.cpp updated: 1.147 -> 1.148
---
Log message:

Typo


---
Diffs of the changes:  (+2 -2)

 X86ISelLowering.cpp |    4 ++--
 1 files changed, 2 insertions(+), 2 deletions(-)


Index: llvm/lib/Target/X86/X86ISelLowering.cpp
diff -u llvm/lib/Target/X86/X86ISelLowering.cpp:1.147 llvm/lib/Target/X86/X86ISelLowering.cpp:1.148
--- llvm/lib/Target/X86/X86ISelLowering.cpp:1.147	Thu Mar 30 18:30:29 2006
+++ llvm/lib/Target/X86/X86ISelLowering.cpp	Thu Mar 30 18:33:57 2006
@@ -1612,7 +1612,7 @@
 
     if (BitI1.getOpcode() != ISD::UNDEF) {
       assert(isa<ConstantSDNode>(BitI1) && "Invalid VECTOR_SHUFFLE mask!");
-      if (cast<ConstantSDNode>(BitI)->getValue() != j + NumElems)
+      if (cast<ConstantSDNode>(BitI1)->getValue() != j + NumElems)
         return false;
     }
   }
@@ -1641,7 +1641,7 @@
 
     if (BitI1.getOpcode() != ISD::UNDEF) {
       assert(isa<ConstantSDNode>(BitI1) && "Invalid VECTOR_SHUFFLE mask!");
-      if (cast<ConstantSDNode>(BitI)->getValue() != j + NumElems/2 + NumElems)
+      if (cast<ConstantSDNode>(BitI1)->getValue() != j + NumElems/2 + NumElems)
         return false;
     }
   }





From lattner at cs.uiuc.edu  Thu Mar 30 18:46:38 2006
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Thu, 30 Mar 2006 18:46:38 -0600
Subject: [llvm-commits] CVS: llvm/include/llvm/Target/TargetLowering.h 
Message-ID: <200603310046.SAA06667@zion.cs.uiuc.edu>



Changes in directory llvm/include/llvm/Target:

TargetLowering.h updated: 1.64 -> 1.65
---
Log message:

Modify the TargetLowering::getPackedTypeBreakdown method to also return the
unpromoted element type.



---
Diffs of the changes:  (+6 -3)

 TargetLowering.h |    9 ++++++---
 1 files changed, 6 insertions(+), 3 deletions(-)


Index: llvm/include/llvm/Target/TargetLowering.h
diff -u llvm/include/llvm/Target/TargetLowering.h:1.64 llvm/include/llvm/Target/TargetLowering.h:1.65
--- llvm/include/llvm/Target/TargetLowering.h:1.64	Thu Mar 30 18:28:23 2006
+++ llvm/include/llvm/Target/TargetLowering.h	Thu Mar 30 18:46:26 2006
@@ -178,10 +178,13 @@
   /// with Altivec or SSE1, or 8 promoted MVT::f64 values with the X86 FP stack.
   /// Similarly, <2 x long> turns into 4 MVT::i32 values with both PPC and X86.
   ///
-  /// This method returns the number and type of the resultant breakdown.
+  /// This method returns the number of registers needed, and the VT for each
+  /// register.  It also returns the VT of the PackedType elements before they
+  /// are promoted/expanded.
   ///
-  MVT::ValueType getPackedTypeBreakdown(const PackedType *PTy, 
-                                        unsigned &NE) const;
+  unsigned getPackedTypeBreakdown(const PackedType *PTy, 
+                                  MVT::ValueType &PTyElementVT,
+                                  MVT::ValueType &PTyLegalElementVT) const;
   
   typedef std::vector<double>::const_iterator legal_fpimm_iterator;
   legal_fpimm_iterator legal_fpimm_begin() const {





From lattner at cs.uiuc.edu  Thu Mar 30 18:46:48 2006
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Thu, 30 Mar 2006 18:46:48 -0600
Subject: [llvm-commits] CVS: llvm/lib/Target/TargetLowering.cpp 
Message-ID: <200603310046.SAA06676@zion.cs.uiuc.edu>



Changes in directory llvm/lib/Target:

TargetLowering.cpp updated: 1.49 -> 1.50
---
Log message:

Modify the TargetLowering::getPackedTypeBreakdown method to also return the
unpromoted element type.



---
Diffs of the changes:  (+7 -4)

 TargetLowering.cpp |   11 +++++++----
 1 files changed, 7 insertions(+), 4 deletions(-)


Index: llvm/lib/Target/TargetLowering.cpp
diff -u llvm/lib/Target/TargetLowering.cpp:1.49 llvm/lib/Target/TargetLowering.cpp:1.50
--- llvm/lib/Target/TargetLowering.cpp:1.49	Thu Mar 30 18:28:56 2006
+++ llvm/lib/Target/TargetLowering.cpp	Thu Mar 30 18:46:36 2006
@@ -148,11 +148,13 @@
 ///
 /// This method returns the number and type of the resultant breakdown.
 ///
-MVT::ValueType TargetLowering::getPackedTypeBreakdown(const PackedType *PTy, 
-                                                      unsigned &NumVals) const {
+unsigned TargetLowering::getPackedTypeBreakdown(const PackedType *PTy, 
+                                                MVT::ValueType &PTyElementVT,
+                                      MVT::ValueType &PTyLegalElementVT) const {
   // Figure out the right, legal destination reg to copy into.
   unsigned NumElts = PTy->getNumElements();
   MVT::ValueType EltTy = getValueType(PTy->getElementType());
+  PTyElementVT = EltTy;
   
   unsigned NumVectorRegs = 1;
   
@@ -170,13 +172,14 @@
     VT = getVectorType(EltTy, NumElts);
 
   MVT::ValueType DestVT = getTypeToTransformTo(VT);
+  PTyLegalElementVT = DestVT;
   if (DestVT < VT) {
     // Value is expanded, e.g. i64 -> i16.
-    NumVals = NumVectorRegs*(MVT::getSizeInBits(VT)/MVT::getSizeInBits(DestVT));
+    return NumVectorRegs*(MVT::getSizeInBits(VT)/MVT::getSizeInBits(DestVT));
   } else {
     // Otherwise, promotion or legal types use the same number of registers as
     // the vector decimated to the appropriate level.
-    NumVals = NumVectorRegs;
+    return NumVectorRegs;
   }
   
   return DestVT;





From evan.cheng at apple.com  Thu Mar 30 19:28:03 2006
From: evan.cheng at apple.com (Evan Cheng)
Date: Thu, 30 Mar 2006 19:28:03 -0600
Subject: [llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp 
Message-ID: <200603310128.TAA06967@zion.cs.uiuc.edu>



Changes in directory llvm/lib/CodeGen/SelectionDAG:

LegalizeDAG.cpp updated: 1.342 -> 1.343
---
Log message:

Expand INSERT_VECTOR_ELT to store vec, sp; store elt, sp+k; vec = load sp;


---
Diffs of the changes:  (+24 -1)

 LegalizeDAG.cpp |   25 ++++++++++++++++++++++++-
 1 files changed, 24 insertions(+), 1 deletion(-)


Index: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.342 llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.343
--- llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.342	Tue Mar 28 14:24:43 2006
+++ llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp	Thu Mar 30 19:27:51 2006
@@ -798,7 +798,30 @@
       // with a "move to register" or "extload into register" instruction, then
       // permute it into place, if the idx is a constant and if the idx is
       // supported by the target.
-      assert(0 && "INSERT_VECTOR_ELT expand not supported yet!");
+      SDOperand StackPtr = CreateStackTemporary(Tmp1.getValueType());
+      // Store the vector.
+      SDOperand Ch = DAG.getNode(ISD::STORE, MVT::Other, DAG.getEntryNode(),
+                                 Tmp1, StackPtr, DAG.getSrcValue(NULL));
+
+      // Truncate or zero extend offset to target pointer type.
+      MVT::ValueType IntPtr = TLI.getPointerTy();
+      if (Tmp3.getValueType() > IntPtr)
+        Tmp3 = DAG.getNode(ISD::TRUNCATE, IntPtr, Tmp3);
+      else
+        Tmp3 = DAG.getNode(ISD::ZERO_EXTEND, IntPtr, Tmp3);
+
+      // Add the offset to the index.
+      unsigned EltSize = MVT::getSizeInBits(Result.getValueType())/8;
+      Tmp3 = DAG.getNode(ISD::MUL, Tmp3.getValueType(), Tmp3,
+                         DAG.getConstant(EltSize, Tmp3.getValueType()));
+      SDOperand StackPtr2 =
+        DAG.getNode(ISD::ADD, Tmp3.getValueType(), Tmp3, StackPtr);
+      // Store the scalar value.
+      Ch = DAG.getNode(ISD::STORE, MVT::Other, Ch,
+                       Tmp2, StackPtr2, DAG.getSrcValue(NULL));
+      // Load the updated vector.
+      Result = DAG.getLoad(Result.getValueType(), Ch, StackPtr,
+                           DAG.getSrcValue(NULL));
       break;
     }
     }





From evan.cheng at apple.com  Thu Mar 30 19:30:51 2006
From: evan.cheng at apple.com (Evan Cheng)
Date: Thu, 30 Mar 2006 19:30:51 -0600
Subject: [llvm-commits] CVS: llvm/lib/Target/X86/X86ISelLowering.cpp 
Message-ID: <200603310130.TAA07006@zion.cs.uiuc.edu>



Changes in directory llvm/lib/Target/X86:

X86ISelLowering.cpp updated: 1.148 -> 1.149
---
Log message:

Expand all INSERT_VECTOR_ELT (obviously bad) for now.


---
Diffs of the changes:  (+1 -0)

 X86ISelLowering.cpp |    1 +
 1 files changed, 1 insertion(+)


Index: llvm/lib/Target/X86/X86ISelLowering.cpp
diff -u llvm/lib/Target/X86/X86ISelLowering.cpp:1.148 llvm/lib/Target/X86/X86ISelLowering.cpp:1.149
--- llvm/lib/Target/X86/X86ISelLowering.cpp:1.148	Thu Mar 30 18:33:57 2006
+++ llvm/lib/Target/X86/X86ISelLowering.cpp	Thu Mar 30 19:30:39 2006
@@ -257,6 +257,7 @@
     setOperationAction(ISD::LOAD, (MVT::ValueType)VT, Expand);
     setOperationAction(ISD::VECTOR_SHUFFLE, (MVT::ValueType)VT, Expand);
     setOperationAction(ISD::EXTRACT_VECTOR_ELT, (MVT::ValueType)VT, Expand);
+    setOperationAction(ISD::INSERT_VECTOR_ELT, (MVT::ValueType)VT, Expand);
   }
 
   if (Subtarget->hasMMX()) {





From lattner at cs.uiuc.edu  Thu Mar 30 19:49:07 2006
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Thu, 30 Mar 2006 19:49:07 -0600
Subject: [llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCISelLowering.cpp 
Message-ID: <200603310149.TAA07325@zion.cs.uiuc.edu>



Changes in directory llvm/lib/Target/PowerPC:

PPCISelLowering.cpp updated: 1.118 -> 1.119
---
Log message:

Mark INSERT_VECTOR_ELT as expand


---
Diffs of the changes:  (+1 -0)

 PPCISelLowering.cpp |    1 +
 1 files changed, 1 insertion(+)


Index: llvm/lib/Target/PowerPC/PPCISelLowering.cpp
diff -u llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.118 llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.119
--- llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.118	Mon Mar 27 22:15:58 2006
+++ llvm/lib/Target/PowerPC/PPCISelLowering.cpp	Thu Mar 30 19:48:55 2006
@@ -178,6 +178,7 @@
     setOperationAction(ISD::MUL , (MVT::ValueType)VT, Expand);
     setOperationAction(ISD::VECTOR_SHUFFLE, (MVT::ValueType)VT, Expand);
     setOperationAction(ISD::EXTRACT_VECTOR_ELT, (MVT::ValueType)VT, Expand);
+    setOperationAction(ISD::INSERT_VECTOR_ELT, (MVT::ValueType)VT, Expand);
     setOperationAction(ISD::BUILD_VECTOR, (MVT::ValueType)VT, Expand);
   }
 





From lattner at cs.uiuc.edu  Thu Mar 30 19:50:20 2006
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Thu, 30 Mar 2006 19:50:20 -0600
Subject: [llvm-commits] CVS: llvm/lib/Target/TargetLowering.cpp 
Message-ID: <200603310150.TAA07407@zion.cs.uiuc.edu>



Changes in directory llvm/lib/Target:

TargetLowering.cpp updated: 1.50 -> 1.51
---
Log message:

Was returning the wrong type.


---
Diffs of the changes:  (+5 -4)

 TargetLowering.cpp |    9 +++++----
 1 files changed, 5 insertions(+), 4 deletions(-)


Index: llvm/lib/Target/TargetLowering.cpp
diff -u llvm/lib/Target/TargetLowering.cpp:1.50 llvm/lib/Target/TargetLowering.cpp:1.51
--- llvm/lib/Target/TargetLowering.cpp:1.50	Thu Mar 30 18:46:36 2006
+++ llvm/lib/Target/TargetLowering.cpp	Thu Mar 30 19:50:09 2006
@@ -154,7 +154,6 @@
   // Figure out the right, legal destination reg to copy into.
   unsigned NumElts = PTy->getNumElements();
   MVT::ValueType EltTy = getValueType(PTy->getElementType());
-  PTyElementVT = EltTy;
   
   unsigned NumVectorRegs = 1;
   
@@ -166,10 +165,12 @@
   }
   
   MVT::ValueType VT;
-  if (NumElts == 1)
+  if (NumElts == 1) {
     VT = EltTy;
-  else
-    VT = getVectorType(EltTy, NumElts);
+  } else {
+    VT = getVectorType(EltTy, NumElts); 
+  }
+  PTyElementVT = VT;
 
   MVT::ValueType DestVT = getTypeToTransformTo(VT);
   PTyLegalElementVT = DestVT;





From lattner at cs.uiuc.edu  Thu Mar 30 20:07:07 2006
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Thu, 30 Mar 2006 20:07:07 -0600
Subject: [llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
	SelectionDAG.cpp SelectionDAGISel.cpp 
Message-ID: <200603310207.UAA07869@zion.cs.uiuc.edu>



Changes in directory llvm/lib/CodeGen/SelectionDAG:

LegalizeDAG.cpp updated: 1.343 -> 1.344
SelectionDAG.cpp updated: 1.292 -> 1.293
SelectionDAGISel.cpp updated: 1.212 -> 1.213
---
Log message:

Significantly improve handling of vectors that are live across basic blocks,
handling cases where the vector elements need promotion, expansion, and when
the vector type itself needs to be decimated.



---
Diffs of the changes:  (+101 -52)

 LegalizeDAG.cpp      |    5 -
 SelectionDAG.cpp     |    3 -
 SelectionDAGISel.cpp |  145 ++++++++++++++++++++++++++++++++++-----------------
 3 files changed, 101 insertions(+), 52 deletions(-)


Index: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.343 llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.344
--- llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.343	Thu Mar 30 19:27:51 2006
+++ llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp	Thu Mar 30 20:06:55 2006
@@ -4497,9 +4497,6 @@
 /// type for the result.
 SDOperand SelectionDAGLegalize::PackVectorOp(SDOperand Op, 
                                              MVT::ValueType NewVT) {
-  // FIXME: THIS IS A TEMPORARY HACK
-  if (Op.getValueType() == NewVT) return Op;
-    
   assert(Op.getValueType() == MVT::Vector && "Bad PackVectorOp invocation!");
   SDNode *Node = Op.Val;
   
@@ -4536,7 +4533,7 @@
     break;
   }
   case ISD::VBUILD_VECTOR:
-    if (!MVT::isVector(NewVT)) {
+    if (Node->getOperand(0).getValueType() == NewVT) {
       // Returning a scalar?
       Result = Node->getOperand(0);
     } else {


Index: llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp:1.292 llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp:1.293
--- llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp:1.292	Tue Mar 28 13:54:42 2006
+++ llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp	Thu Mar 30 20:06:56 2006
@@ -1162,8 +1162,7 @@
     break;
   case ISD::BIT_CONVERT:
     // Basic sanity checking.
-    assert((Operand.getValueType() == MVT::Vector ||   // FIXME: This is a hack.
-           MVT::getSizeInBits(VT) == MVT::getSizeInBits(Operand.getValueType()))
+    assert(MVT::getSizeInBits(VT) == MVT::getSizeInBits(Operand.getValueType())
            && "Cannot BIT_CONVERT between two different types!");
     if (VT == Operand.getValueType()) return Operand;  // noop conversion.
     if (OpOpcode == ISD::BIT_CONVERT)  // bitconv(bitconv(x)) -> bitconv(x)


Index: llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.212 llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.213
--- llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.212	Tue Mar 28 18:11:43 2006
+++ llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp	Thu Mar 30 20:06:56 2006
@@ -264,8 +264,16 @@
     for (BasicBlock::iterator I = BB->begin();
          (PN = dyn_cast<PHINode>(I)); ++I)
       if (!PN->use_empty()) {
-        unsigned NumElements =
-          TLI.getNumElements(TLI.getValueType(PN->getType()));
+        MVT::ValueType VT = TLI.getValueType(PN->getType());
+        unsigned NumElements;
+        if (VT != MVT::Vector)
+          NumElements = TLI.getNumElements(VT);
+        else {
+          MVT::ValueType VT1,VT2;
+          NumElements = 
+            TLI.getPackedTypeBreakdown(cast<PackedType>(PN->getType()),
+                                       VT1, VT2);
+        }
         unsigned PHIReg = ValueMap[PN];
         assert(PHIReg &&"PHI node does not have an assigned virtual register!");
         for (unsigned i = 0; i != NumElements; ++i)
@@ -622,32 +630,61 @@
   unsigned InReg = VMI->second;
   
   // If this type is not legal, make it so now.
-  if (VT == MVT::Vector) {
-    // FIXME: We only handle legal vectors right now.  We need a VBUILD_VECTOR
-    const PackedType *PTy = cast<PackedType>(VTy);
-    unsigned NumElements = PTy->getNumElements();
-    MVT::ValueType PVT = TLI.getValueType(PTy->getElementType());
-    MVT::ValueType TVT = MVT::getVectorType(PVT, NumElements);
-    assert(TLI.isTypeLegal(TVT) &&
-           "FIXME: Cannot handle illegal vector types here yet!");
-    VT = TVT;
-  }
+  if (VT != MVT::Vector) {
+    MVT::ValueType DestVT = TLI.getTypeToTransformTo(VT);
   
-  MVT::ValueType DestVT = TLI.getTypeToTransformTo(VT);
-  
-  N = DAG.getCopyFromReg(DAG.getEntryNode(), InReg, DestVT);
-  if (DestVT < VT) {
-    // Source must be expanded.  This input value is actually coming from the
-    // register pair VMI->second and VMI->second+1.
-    N = DAG.getNode(ISD::BUILD_PAIR, VT, N,
-                    DAG.getCopyFromReg(DAG.getEntryNode(), InReg+1, DestVT));
-  } else {
-    if (DestVT > VT) { // Promotion case
+    N = DAG.getCopyFromReg(DAG.getEntryNode(), InReg, DestVT);
+    if (DestVT < VT) {
+      // Source must be expanded.  This input value is actually coming from the
+      // register pair VMI->second and VMI->second+1.
+      N = DAG.getNode(ISD::BUILD_PAIR, VT, N,
+                      DAG.getCopyFromReg(DAG.getEntryNode(), InReg+1, DestVT));
+    } else if (DestVT > VT) { // Promotion case
       if (MVT::isFloatingPoint(VT))
         N = DAG.getNode(ISD::FP_ROUND, VT, N);
       else
         N = DAG.getNode(ISD::TRUNCATE, VT, N);
     }
+  } else {
+    // Otherwise, if this is a vector, make it available as a generic vector
+    // here.
+    MVT::ValueType PTyElementVT, PTyLegalElementVT;
+    unsigned NE = TLI.getPackedTypeBreakdown(cast<PackedType>(VTy),PTyElementVT,
+                                             PTyLegalElementVT);
+
+    // Build a VBUILD_VECTOR with the input registers.
+    std::vector<SDOperand> Ops;
+    if (PTyElementVT == PTyLegalElementVT) {
+      // If the value types are legal, just VBUILD the CopyFromReg nodes.
+      for (unsigned i = 0; i != NE; ++i)
+        Ops.push_back(DAG.getCopyFromReg(DAG.getEntryNode(), InReg++, 
+                                         PTyElementVT));
+    } else if (PTyElementVT < PTyLegalElementVT) {
+      // If the register was promoted, use TRUNCATE of FP_ROUND as appropriate.
+      for (unsigned i = 0; i != NE; ++i) {
+        SDOperand Op = DAG.getCopyFromReg(DAG.getEntryNode(), InReg++, 
+                                          PTyElementVT);
+        if (MVT::isFloatingPoint(PTyElementVT))
+          Op = DAG.getNode(ISD::FP_ROUND, PTyElementVT, Op);
+        else
+          Op = DAG.getNode(ISD::TRUNCATE, PTyElementVT, Op);
+        Ops.push_back(Op);
+      }
+    } else {
+      // If the register was expanded, use BUILD_PAIR.
+      assert((NE & 1) == 0 && "Must expand into a multiple of 2 elements!");
+      for (unsigned i = 0; i != NE/2; ++i) {
+        SDOperand Op0 = DAG.getCopyFromReg(DAG.getEntryNode(), InReg++, 
+                                           PTyElementVT);
+        SDOperand Op1 = DAG.getCopyFromReg(DAG.getEntryNode(), InReg++, 
+                                           PTyElementVT);
+        Ops.push_back(DAG.getNode(ISD::BUILD_PAIR, VT, Op0, Op1));
+      }
+    }
+    
+    Ops.push_back(DAG.getConstant(NE, MVT::i32));
+    Ops.push_back(DAG.getValueType(PTyLegalElementVT));
+    N = DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector, Ops);
   }
   
   return N;
@@ -2589,31 +2626,47 @@
   if (SrcVT == DestVT) {
     return DAG.getCopyToReg(SDL.getRoot(), Reg, Op);
   } else if (SrcVT == MVT::Vector) {
-    // FIXME: THIS DOES NOT SUPPORT PROMOTED/EXPANDED ELEMENTS!
-
-    // Figure out the right, legal destination reg to copy into.
-    const PackedType *PTy = cast<PackedType>(V->getType());
-    unsigned NumElts = PTy->getNumElements();
-    MVT::ValueType EltTy = TLI.getValueType(PTy->getElementType());
-    
-    unsigned NumVectorRegs = 1;
-
-    // Divide the input until we get to a supported size.  This will always
-    // end with a scalar if the target doesn't support vectors.
-    while (NumElts > 1 && !TLI.isTypeLegal(getVectorType(EltTy, NumElts))) {
-      NumElts >>= 1;
-      NumVectorRegs <<= 1;
+    // Handle copies from generic vectors to registers.
+    MVT::ValueType PTyElementVT, PTyLegalElementVT;
+    unsigned NE = TLI.getPackedTypeBreakdown(cast<PackedType>(V->getType()),
+                                             PTyElementVT, PTyLegalElementVT);
+    
+    // Insert a VBIT_CONVERT of the input vector to a "N x PTyElementVT" 
+    // MVT::Vector type.
+    Op = DAG.getNode(ISD::VBIT_CONVERT, MVT::Vector, Op,
+                     DAG.getConstant(NE, MVT::i32), 
+                     DAG.getValueType(PTyElementVT));
+
+    // Loop over all of the elements of the resultant vector,
+    // VEXTRACT_VECTOR_ELT'ing them, converting them to PTyLegalElementVT, then
+    // copying them into output registers.
+    std::vector<SDOperand> OutChains;
+    SDOperand Root = SDL.getRoot();
+    for (unsigned i = 0; i != NE; ++i) {
+      SDOperand Elt = DAG.getNode(ISD::VEXTRACT_VECTOR_ELT, PTyElementVT,
+                                  Op, DAG.getConstant(i, MVT::i32));
+      if (PTyElementVT == PTyLegalElementVT) {
+        // Elements are legal.
+        OutChains.push_back(DAG.getCopyToReg(Root, Reg++, Elt));
+      } else if (PTyLegalElementVT > PTyElementVT) {
+        // Elements are promoted.
+        if (MVT::isFloatingPoint(PTyLegalElementVT))
+          Elt = DAG.getNode(ISD::FP_EXTEND, PTyLegalElementVT, Elt);
+        else
+          Elt = DAG.getNode(ISD::ANY_EXTEND, PTyLegalElementVT, Elt);
+        OutChains.push_back(DAG.getCopyToReg(Root, Reg++, Elt));
+      } else {
+        // Elements are expanded.
+        // The src value is expanded into multiple registers.
+        SDOperand Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, PTyLegalElementVT,
+                                   Elt, DAG.getConstant(0, MVT::i32));
+        SDOperand Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, PTyLegalElementVT,
+                                   Elt, DAG.getConstant(1, MVT::i32));
+        OutChains.push_back(DAG.getCopyToReg(Root, Reg++, Lo));
+        OutChains.push_back(DAG.getCopyToReg(Root, Reg++, Hi));
+      }
     }
-    
-    MVT::ValueType VT;
-    if (NumElts == 1)
-      VT = EltTy;
-    else
-      VT = getVectorType(EltTy, NumElts);
-    
-    // FIXME: THIS ASSUMES THAT THE INPUT VECTOR WILL BE LEGAL!
-    Op = DAG.getNode(ISD::BIT_CONVERT, VT, Op);
-    return DAG.getCopyToReg(SDL.getRoot(), Reg, Op);
+    return DAG.getNode(ISD::TokenFactor, MVT::Other, OutChains);
   } else if (SrcVT < DestVT) {
     // The src value is promoted to the register.
     if (MVT::isFloatingPoint(SrcVT))





From lattner at cs.uiuc.edu  Thu Mar 30 20:11:58 2006
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Thu, 30 Mar 2006 20:11:58 -0600
Subject: [llvm-commits] 
	CVS: llvm-test/SingleSource/UnitTests/Vector/sumarray-dbl.c
	helpers.h 
Message-ID: <200603310211.UAA08051@zion.cs.uiuc.edu>



Changes in directory llvm-test/SingleSource/UnitTests/Vector:

sumarray-dbl.c added (r1.1)
helpers.h updated: 1.3 -> 1.4
---
Log message:

new testcase, which requires expansion of cross-block values.


---
Diffs of the changes:  (+36 -0)

 helpers.h      |   14 ++++++++++++++
 sumarray-dbl.c |   22 ++++++++++++++++++++++
 2 files changed, 36 insertions(+)


Index: llvm-test/SingleSource/UnitTests/Vector/sumarray-dbl.c
diff -c /dev/null llvm-test/SingleSource/UnitTests/Vector/sumarray-dbl.c:1.1
*** /dev/null	Thu Mar 30 20:11:56 2006
--- llvm-test/SingleSource/UnitTests/Vector/sumarray-dbl.c	Thu Mar 30 20:11:46 2006
***************
*** 0 ****
--- 1,22 ----
+ #include "helpers.h"
+ 
+ union Array {
+   v8sd  Vectors[100];
+   double Floats[800];
+ };
+ 
+ union Array TheArray;
+ 
+ void main() {
+   int i;
+   v8sd sum = { 0, 0, 0, 0, 0, 0, 0, 0};
+   D8V sumV;
+   for (i = 0; i < 800; ++i)
+     TheArray.Floats[i] = i*12.345;
+ 
+   for (i = 0; i < 100; ++i)
+     sum += TheArray.Vectors[i];
+ 
+   sumV.V = sum;
+   printD8V(&sumV);
+ }


Index: llvm-test/SingleSource/UnitTests/Vector/helpers.h
diff -u llvm-test/SingleSource/UnitTests/Vector/helpers.h:1.3 llvm-test/SingleSource/UnitTests/Vector/helpers.h:1.4
--- llvm-test/SingleSource/UnitTests/Vector/helpers.h:1.3	Thu Mar 23 19:18:59 2006
+++ llvm-test/SingleSource/UnitTests/Vector/helpers.h	Thu Mar 30 20:11:46 2006
@@ -3,6 +3,10 @@
 typedef float  v4sf __attribute__ ((__vector_size__ (16)));
 typedef double v2sd __attribute__ ((__vector_size__ (16)));
 
+// These require legalization.
+typedef float  v8sf __attribute__ ((__vector_size__ (32)));
+typedef double v8sd __attribute__ ((__vector_size__ (64)));
+
 typedef union {
   v4sf V;
   float A[4];
@@ -13,6 +17,11 @@
   double A[2];
 } DV;
 
+typedef union {
+  v8sd V;
+  double A[8];
+} D8V;
+
 static void printFV(FV *F) {
 	printf("%f %f %f %f\n", F->A[0], F->A[1], F->A[2], F->A[3]);
 }
@@ -20,3 +29,8 @@
 static void printDV(DV *D) {
 	printf("%g %g\n", D->A[0], D->A[1]);
 }
+
+static void printD8V(D8V *D) {
+	printf("%g %g %g %g %g %g %g %g\n", D->A[0], D->A[1], D->A[2], D->A[3],
+                                            D->A[4], D->A[5], D->A[6], D->A[7]);
+}





From lattner at cs.uiuc.edu  Thu Mar 30 20:12:30 2006
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Thu, 30 Mar 2006 20:12:30 -0600
Subject: [llvm-commits] 
	CVS: llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
Message-ID: <200603310212.UAA08088@zion.cs.uiuc.edu>



Changes in directory llvm/lib/CodeGen/SelectionDAG:

SelectionDAGISel.cpp updated: 1.213 -> 1.214
---
Log message:

Make sure to pass enough values to phi nodes when we are dealing with
decimated vectors.  This fixes UnitTests/Vector/sumarray-dbl.c


---
Diffs of the changes:  (+10 -2)

 SelectionDAGISel.cpp |   12 ++++++++++--
 1 files changed, 10 insertions(+), 2 deletions(-)


Index: llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.213 llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.214
--- llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.213	Thu Mar 30 20:06:56 2006
+++ llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp	Thu Mar 30 20:12:18 2006
@@ -2805,8 +2805,16 @@
 
         // Remember that this register needs to added to the machine PHI node as
         // the input for this MBB.
-        unsigned NumElements =
-          TLI.getNumElements(TLI.getValueType(PN->getType()));
+        MVT::ValueType VT = TLI.getValueType(PN->getType());
+        unsigned NumElements;
+        if (VT != MVT::Vector)
+          NumElements = TLI.getNumElements(VT);
+        else {
+          MVT::ValueType VT1,VT2;
+          NumElements = 
+            TLI.getPackedTypeBreakdown(cast<PackedType>(PN->getType()),
+                                       VT1, VT2);
+        }
         for (unsigned i = 0, e = NumElements; i != e; ++i)
           PHINodesToUpdate.push_back(std::make_pair(MBBI++, Reg+i));
       }





From lattner at cs.uiuc.edu  Thu Mar 30 22:25:10 2006
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Thu, 30 Mar 2006 22:25:10 -0600
Subject: [llvm-commits] CVS: llvm/utils/TableGen/IntrinsicEmitter.cpp 
Message-ID: <200603310425.WAA10474@zion.cs.uiuc.edu>



Changes in directory llvm/utils/TableGen:

IntrinsicEmitter.cpp updated: 1.17 -> 1.18
---
Log message:

When emitting code for the verifier, instead of emitting each case statement
independently, batch up checks so that identically typed intrinsics share
verifier code.  This dramatically reduces the size of the verifier function,
which should help avoid GCC running out of memory compiling Verifier.cpp.


---
Diffs of the changes:  (+42 -9)

 IntrinsicEmitter.cpp |   51 ++++++++++++++++++++++++++++++++++++++++++---------
 1 files changed, 42 insertions(+), 9 deletions(-)


Index: llvm/utils/TableGen/IntrinsicEmitter.cpp
diff -u llvm/utils/TableGen/IntrinsicEmitter.cpp:1.17 llvm/utils/TableGen/IntrinsicEmitter.cpp:1.18
--- llvm/utils/TableGen/IntrinsicEmitter.cpp:1.17	Tue Mar 28 16:25:56 2006
+++ llvm/utils/TableGen/IntrinsicEmitter.cpp	Thu Mar 30 22:24:58 2006
@@ -127,22 +127,55 @@
   }
 }
 
+/// RecordListComparator - Provide a determinstic comparator for lists of
+/// records.
+namespace {
+  struct RecordListComparator {
+    bool operator()(const std::vector<Record*> &LHS,
+                    const std::vector<Record*> &RHS) const {
+      unsigned i = 0;
+      do {
+        if (i == RHS.size()) return false;  // RHS is shorter than LHS.
+        if (LHS[i] != RHS[i])
+          return LHS[i]->getName() < RHS[i]->getName();
+      } while (++i != LHS.size());
+      
+      return i != RHS.size();
+    }
+  };
+}
+
 void IntrinsicEmitter::EmitVerifier(const std::vector<CodeGenIntrinsic> &Ints, 
                                     std::ostream &OS) {
   OS << "// Verifier::visitIntrinsicFunctionCall code.\n";
   OS << "#ifdef GET_INTRINSIC_VERIFIER\n";
   OS << "  switch (ID) {\n";
   OS << "  default: assert(0 && \"Invalid intrinsic!\");\n";
-  for (unsigned i = 0, e = Ints.size(); i != e; ++i) {
-    OS << "  case Intrinsic::" << Ints[i].EnumName << ":\t\t// "
-       << Ints[i].Name << "\n";
-    OS << "    Assert1(FTy->getNumParams() == " << Ints[i].ArgTypes.size()-1
-       << ",\n"
+  
+  // This checking can emit a lot of very common code.  To reduce the amount of
+  // code that we emit, batch up cases that have identical types.  This avoids
+  // problems where GCC can run out of memory compiling Verifier.cpp.
+  typedef std::map<std::vector<Record*>, std::vector<unsigned>, 
+    RecordListComparator> MapTy;
+  MapTy UniqueArgInfos;
+  
+  // Compute the unique argument type info.
+  for (unsigned i = 0, e = Ints.size(); i != e; ++i)
+    UniqueArgInfos[Ints[i].ArgTypeDefs].push_back(i);
+
+  // Loop through the array, emitting one comparison for each batch.
+  for (MapTy::iterator I = UniqueArgInfos.begin(),
+       E = UniqueArgInfos.end(); I != E; ++I) {
+    for (unsigned i = 0, e = I->second.size(); i != e; ++i) {
+      OS << "  case Intrinsic::" << Ints[I->second[i]].EnumName << ":\t\t// "
+         << Ints[I->second[i]].Name << "\n";
+    }
+    const std::vector<Record*> &ArgTypes = I->first;
+    OS << "    Assert1(FTy->getNumParams() == " << ArgTypes.size()-1 << ",\n"
        << "            \"Illegal # arguments for intrinsic function!\", IF);\n";
-    EmitTypeVerify(OS, "FTy->getReturnType()", Ints[i].ArgTypeDefs[0]);
-    for (unsigned j = 1; j != Ints[i].ArgTypes.size(); ++j)
-      EmitTypeVerify(OS, "FTy->getParamType(" + utostr(j-1) + ")",
-                     Ints[i].ArgTypeDefs[j]);
+    EmitTypeVerify(OS, "FTy->getReturnType()", ArgTypes[0]);
+    for (unsigned j = 1; j != ArgTypes.size(); ++j)
+      EmitTypeVerify(OS, "FTy->getParamType(" + utostr(j-1) + ")", ArgTypes[j]);
     OS << "    break;\n";
   }
   OS << "  }\n";





From lattner at cs.uiuc.edu  Thu Mar 30 22:46:59 2006
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Thu, 30 Mar 2006 22:46:59 -0600
Subject: [llvm-commits] CVS: llvm/lib/VMCore/Verifier.cpp 
Message-ID: <200603310446.WAA10617@zion.cs.uiuc.edu>



Changes in directory llvm/lib/VMCore:

Verifier.cpp updated: 1.150 -> 1.151
---
Log message:

Add a new method to verify intrinsic function prototypes.


---
Diffs of the changes:  (+60 -2)

 Verifier.cpp |   62 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++--
 1 files changed, 60 insertions(+), 2 deletions(-)


Index: llvm/lib/VMCore/Verifier.cpp
diff -u llvm/lib/VMCore/Verifier.cpp:1.150 llvm/lib/VMCore/Verifier.cpp:1.151
--- llvm/lib/VMCore/Verifier.cpp:1.150	Thu Mar  9 16:06:04 2006
+++ llvm/lib/VMCore/Verifier.cpp	Thu Mar 30 22:46:47 2006
@@ -55,6 +55,7 @@
 #include "llvm/Analysis/Dominators.h"
 #include "llvm/Support/CFG.h"
 #include "llvm/Support/InstVisitor.h"
+#include "llvm/ADT/StringExtras.h"
 #include "llvm/ADT/STLExtras.h"
 #include <algorithm>
 #include <iostream>
@@ -196,6 +197,7 @@
     void visitUserOp2(Instruction &I) { visitUserOp1(I); }
     void visitIntrinsicFunctionCall(Intrinsic::ID ID, CallInst &CI);
 
+    void VerifyIntrinsicPrototype(Function *F, ...);
 
     void WriteValue(const Value *V) {
       if (!V) return;
@@ -436,8 +438,7 @@
 /// a pass, if any exist, it's an error.
 ///
 void Verifier::visitUserOp1(Instruction &I) {
-  Assert1(0, "User-defined operators should not live outside of a pass!",
-          &I);
+  Assert1(0, "User-defined operators should not live outside of a pass!", &I);
 }
 
 /// visitPHINode - Ensure that a PHI node is well formed.
@@ -684,6 +685,63 @@
 #undef GET_INTRINSIC_VERIFIER
 }
 
+/// VerifyIntrinsicPrototype - TableGen emits calls to this function into
+/// Intrinsics.gen.  This implements a little state machine that verifies the
+/// prototype of intrinsics.
+void Verifier::VerifyIntrinsicPrototype(Function *F, ...) {
+  va_list VA;
+  va_start(VA, F);
+  
+  const FunctionType *FTy = F->getFunctionType();
+  
+  // Note that "arg#0" is the return type.
+  for (unsigned ArgNo = 0; 1; ++ArgNo) {
+    int TypeID = va_arg(VA, int);
+
+    if (TypeID == -1) {
+      if (ArgNo != FTy->getNumParams()+1)
+        CheckFailed("Intrinsic prototype has too many arguments!", F);
+      break;
+    }
+
+    if (ArgNo == FTy->getNumParams()+1) {
+      CheckFailed("Intrinsic prototype has too few arguments!", F);
+      break;
+    }
+    
+    const Type *Ty;
+    if (ArgNo == 0) 
+      Ty = FTy->getReturnType();
+    else
+      Ty = FTy->getParamType(ArgNo-1);
+    
+    if (Ty->getTypeID() != TypeID) {
+      if (ArgNo == 0)
+        CheckFailed("Intrinsic prototype has incorrect result type!", F);
+      else
+        CheckFailed("Intrinsic parameter #" + utostr(ArgNo-1) + " is wrong!",F);
+      break;
+    }
+
+    // If this is a packed argument, verify the number and type of elements.
+    if (TypeID == Type::PackedTyID) {
+      const PackedType *PTy = cast<PackedType>(Ty);
+      if (va_arg(VA, int) != PTy->getElementType()->getTypeID()) {
+        CheckFailed("Intrinsic prototype has incorrect vector element type!",F);
+        break;
+      }
+
+      if ((unsigned)va_arg(VA, int) != PTy->getNumElements()) {
+        CheckFailed("Intrinsic prototype has incorrect number of "
+                    "vector elements!",F);
+        break;
+      }
+    }
+  }
+
+  va_end(VA);
+}
+
 
 //===----------------------------------------------------------------------===//
 //  Implement the public interfaces to this file...





From lattner at cs.uiuc.edu  Thu Mar 30 22:48:38 2006
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Thu, 30 Mar 2006 22:48:38 -0600
Subject: [llvm-commits] CVS: llvm/utils/TableGen/IntrinsicEmitter.cpp 
Message-ID: <200603310448.WAA10678@zion.cs.uiuc.edu>



Changes in directory llvm/utils/TableGen:

IntrinsicEmitter.cpp updated: 1.18 -> 1.19
---
Log message:

Final bugfix for PR724: http://llvm.cs.uiuc.edu/PR724 .  GCC won't inline varargs functions, so use one to
validate the prototype of intrinsic functions.  This prevents GCC from going
crazy and inlining too much stuff, eventually running out of memory.



---
Diffs of the changes:  (+9 -17)

 IntrinsicEmitter.cpp |   26 +++++++++-----------------
 1 files changed, 9 insertions(+), 17 deletions(-)


Index: llvm/utils/TableGen/IntrinsicEmitter.cpp
diff -u llvm/utils/TableGen/IntrinsicEmitter.cpp:1.18 llvm/utils/TableGen/IntrinsicEmitter.cpp:1.19
--- llvm/utils/TableGen/IntrinsicEmitter.cpp:1.18	Thu Mar 30 22:24:58 2006
+++ llvm/utils/TableGen/IntrinsicEmitter.cpp	Thu Mar 30 22:48:26 2006
@@ -108,22 +108,14 @@
   OS << "#endif\n\n";
 }
 
-static void EmitTypeVerify(std::ostream &OS, const std::string &Val,
-                           Record *ArgType) {
-  OS << "    Assert1(" << Val << "->getTypeID() == "
-     << ArgType->getValueAsString("TypeVal") << ",\n"
-     << "            \"Illegal intrinsic type!\", IF);\n";
+static void EmitTypeVerify(std::ostream &OS, Record *ArgType) {
+  OS << "(int)" << ArgType->getValueAsString("TypeVal") << ", ";
 
   // If this is a packed type, check that the subtype and size are correct.
   if (ArgType->isSubClassOf("LLVMPackedType")) {
     Record *SubType = ArgType->getValueAsDef("ElTy");
-    OS << "    Assert1(cast<PackedType>(" << Val
-       << ")->getElementType()->getTypeID() == "
-       << SubType->getValueAsString("TypeVal") << ",\n"
-       << "            \"Illegal intrinsic type!\", IF);\n";
-    OS << "    Assert1(cast<PackedType>(" << Val << ")->getNumElements() == "
-       << ArgType->getValueAsInt("NumElts") << ",\n"
-       << "            \"Illegal intrinsic type!\", IF);\n";
+    OS << "(int)" << SubType->getValueAsString("TypeVal") << ", "
+       << ArgType->getValueAsInt("NumElts") << ", ";
   }
 }
 
@@ -170,12 +162,12 @@
       OS << "  case Intrinsic::" << Ints[I->second[i]].EnumName << ":\t\t// "
          << Ints[I->second[i]].Name << "\n";
     }
+    
     const std::vector<Record*> &ArgTypes = I->first;
-    OS << "    Assert1(FTy->getNumParams() == " << ArgTypes.size()-1 << ",\n"
-       << "            \"Illegal # arguments for intrinsic function!\", IF);\n";
-    EmitTypeVerify(OS, "FTy->getReturnType()", ArgTypes[0]);
-    for (unsigned j = 1; j != ArgTypes.size(); ++j)
-      EmitTypeVerify(OS, "FTy->getParamType(" + utostr(j-1) + ")", ArgTypes[j]);
+    OS << "    VerifyIntrinsicPrototype(IF, ";
+    for (unsigned j = 0; j != ArgTypes.size(); ++j)
+      EmitTypeVerify(OS, ArgTypes[j]);
+    OS << "-1);\n";
     OS << "    break;\n";
   }
   OS << "  }\n";





From lattner at cs.uiuc.edu  Thu Mar 30 22:53:33 2006
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Thu, 30 Mar 2006 22:53:33 -0600
Subject: [llvm-commits] CVS: llvm/lib/Target/PowerPC/README_ALTIVEC.txt 
Message-ID: <200603310453.WAA10810@zion.cs.uiuc.edu>



Changes in directory llvm/lib/Target/PowerPC:

README_ALTIVEC.txt updated: 1.6 -> 1.7
---
Log message:

These are done


---
Diffs of the changes:  (+0 -5)

 README_ALTIVEC.txt |    5 -----
 1 files changed, 5 deletions(-)


Index: llvm/lib/Target/PowerPC/README_ALTIVEC.txt
diff -u llvm/lib/Target/PowerPC/README_ALTIVEC.txt:1.6 llvm/lib/Target/PowerPC/README_ALTIVEC.txt:1.7
--- llvm/lib/Target/PowerPC/README_ALTIVEC.txt:1.6	Tue Mar 28 18:24:13 2006
+++ llvm/lib/Target/PowerPC/README_ALTIVEC.txt	Thu Mar 30 22:53:21 2006
@@ -50,18 +50,13 @@
 Missing intrinsics:
 
 ds*
-lvsl/lvsr
 mf*
 vavg*
 vmax*
 vmin*
 vmladduhm
 vmr*
-vmsum*
-vmul*
-vpk*
 vsel (some aliases only accessible using builtins)
-vup*
 
 //===----------------------------------------------------------------------===//
 





From lattner at cs.uiuc.edu  Thu Mar 30 23:13:39 2006
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Thu, 30 Mar 2006 23:13:39 -0600
Subject: [llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCISelLowering.cpp
	PPCISelLowering.h PPCInstrAltivec.td PPCInstrInfo.td 
Message-ID: <200603310513.XAA10966@zion.cs.uiuc.edu>



Changes in directory llvm/lib/Target/PowerPC:

PPCISelLowering.cpp updated: 1.119 -> 1.120
PPCISelLowering.h updated: 1.36 -> 1.37
PPCInstrAltivec.td updated: 1.21 -> 1.22
PPCInstrInfo.td updated: 1.213 -> 1.214
---
Log message:

Lower vector compares to VCMP nodes, just like we lower vector comparison
predicates to VCMPo nodes.


---
Diffs of the changes:  (+72 -43)

 PPCISelLowering.cpp |   53 +++++++++++++++++++++++++++++++++++++---------------
 PPCISelLowering.h   |    6 +++++
 PPCInstrAltivec.td  |   51 ++++++++++++++++++++++++--------------------------
 PPCInstrInfo.td     |    5 ++--
 4 files changed, 72 insertions(+), 43 deletions(-)


Index: llvm/lib/Target/PowerPC/PPCISelLowering.cpp
diff -u llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.119 llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.120
--- llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.119	Thu Mar 30 19:48:55 2006
+++ llvm/lib/Target/PowerPC/PPCISelLowering.cpp	Thu Mar 30 23:13:27 2006
@@ -235,6 +235,7 @@
   case PPCISD::CALL:          return "PPCISD::CALL";
   case PPCISD::RET_FLAG:      return "PPCISD::RET_FLAG";
   case PPCISD::MFCR:          return "PPCISD::MFCR";
+  case PPCISD::VCMP:          return "PPCISD::VCMP";
   case PPCISD::VCMPo:         return "PPCISD::VCMPo";
   }
 }
@@ -752,31 +753,53 @@
     return DAG.getNode(PPCISD::VPERM, V1.getValueType(), V1, V2, VPermMask);
   }
   case ISD::INTRINSIC_WO_CHAIN: {
-    bool HasChain = Op.getOperand(0).getValueType() == MVT::Other;
-    unsigned IntNo=cast<ConstantSDNode>(Op.getOperand(HasChain))->getValue();
+    unsigned IntNo=cast<ConstantSDNode>(Op.getOperand(0))->getValue();
     
     // If this is a lowered altivec predicate compare, CompareOpc is set to the
     // opcode number of the comparison.
     int CompareOpc = -1;
+    bool isDot = false;
     switch (IntNo) {
     default: return SDOperand();    // Don't custom lower most intrinsics.
-    case Intrinsic::ppc_altivec_vcmpbfp_p:  CompareOpc = 966; break;
-    case Intrinsic::ppc_altivec_vcmpeqfp_p: CompareOpc = 198; break;
-    case Intrinsic::ppc_altivec_vcmpequb_p: CompareOpc =   6; break;
-    case Intrinsic::ppc_altivec_vcmpequh_p: CompareOpc =  70; break;
-    case Intrinsic::ppc_altivec_vcmpequw_p: CompareOpc = 134; break;
-    case Intrinsic::ppc_altivec_vcmpgefp_p: CompareOpc = 454; break;
-    case Intrinsic::ppc_altivec_vcmpgtfp_p: CompareOpc = 710; break;
-    case Intrinsic::ppc_altivec_vcmpgtsb_p: CompareOpc = 774; break;
-    case Intrinsic::ppc_altivec_vcmpgtsh_p: CompareOpc = 838; break;
-    case Intrinsic::ppc_altivec_vcmpgtsw_p: CompareOpc = 902; break;
-    case Intrinsic::ppc_altivec_vcmpgtub_p: CompareOpc = 518; break;
-    case Intrinsic::ppc_altivec_vcmpgtuh_p: CompareOpc = 582; break;
-    case Intrinsic::ppc_altivec_vcmpgtuw_p: CompareOpc = 646; break;
+    // Comparison predicates.
+    case Intrinsic::ppc_altivec_vcmpbfp_p:  CompareOpc = 966; isDot = 1; break;
+    case Intrinsic::ppc_altivec_vcmpeqfp_p: CompareOpc = 198; isDot = 1; break;
+    case Intrinsic::ppc_altivec_vcmpequb_p: CompareOpc =   6; isDot = 1; break;
+    case Intrinsic::ppc_altivec_vcmpequh_p: CompareOpc =  70; isDot = 1; break;
+    case Intrinsic::ppc_altivec_vcmpequw_p: CompareOpc = 134; isDot = 1; break;
+    case Intrinsic::ppc_altivec_vcmpgefp_p: CompareOpc = 454; isDot = 1; break;
+    case Intrinsic::ppc_altivec_vcmpgtfp_p: CompareOpc = 710; isDot = 1; break;
+    case Intrinsic::ppc_altivec_vcmpgtsb_p: CompareOpc = 774; isDot = 1; break;
+    case Intrinsic::ppc_altivec_vcmpgtsh_p: CompareOpc = 838; isDot = 1; break;
+    case Intrinsic::ppc_altivec_vcmpgtsw_p: CompareOpc = 902; isDot = 1; break;
+    case Intrinsic::ppc_altivec_vcmpgtub_p: CompareOpc = 518; isDot = 1; break;
+    case Intrinsic::ppc_altivec_vcmpgtuh_p: CompareOpc = 582; isDot = 1; break;
+    case Intrinsic::ppc_altivec_vcmpgtuw_p: CompareOpc = 646; isDot = 1; break;
+
+    // Normal Comparisons.
+    case Intrinsic::ppc_altivec_vcmpbfp:    CompareOpc = 966; isDot = 0; break;
+    case Intrinsic::ppc_altivec_vcmpeqfp:   CompareOpc = 198; isDot = 0; break;
+    case Intrinsic::ppc_altivec_vcmpequb:   CompareOpc =   6; isDot = 0; break;
+    case Intrinsic::ppc_altivec_vcmpequh:   CompareOpc =  70; isDot = 0; break;
+    case Intrinsic::ppc_altivec_vcmpequw:   CompareOpc = 134; isDot = 0; break;
+    case Intrinsic::ppc_altivec_vcmpgefp:   CompareOpc = 454; isDot = 0; break;
+    case Intrinsic::ppc_altivec_vcmpgtfp:   CompareOpc = 710; isDot = 0; break;
+    case Intrinsic::ppc_altivec_vcmpgtsb:   CompareOpc = 774; isDot = 0; break;
+    case Intrinsic::ppc_altivec_vcmpgtsh:   CompareOpc = 838; isDot = 0; break;
+    case Intrinsic::ppc_altivec_vcmpgtsw:   CompareOpc = 902; isDot = 0; break;
+    case Intrinsic::ppc_altivec_vcmpgtub:   CompareOpc = 518; isDot = 0; break;
+    case Intrinsic::ppc_altivec_vcmpgtuh:   CompareOpc = 582; isDot = 0; break;
+    case Intrinsic::ppc_altivec_vcmpgtuw:   CompareOpc = 646; isDot = 0; break;
     }
     
     assert(CompareOpc>0 && "We only lower altivec predicate compares so far!");
 
+    // If this is a non-dot comparison, make the VCMP node.
+    if (!isDot)
+      return DAG.getNode(PPCISD::VCMP, Op.getOperand(2).getValueType(),
+                         Op.getOperand(1), Op.getOperand(2),
+                         DAG.getConstant(CompareOpc, MVT::i32));
+    
     // Create the PPCISD altivec 'dot' comparison node.
     std::vector<SDOperand> Ops;
     std::vector<MVT::ValueType> VTs;


Index: llvm/lib/Target/PowerPC/PPCISelLowering.h
diff -u llvm/lib/Target/PowerPC/PPCISelLowering.h:1.36 llvm/lib/Target/PowerPC/PPCISelLowering.h:1.37
--- llvm/lib/Target/PowerPC/PPCISelLowering.h:1.36	Mon Mar 27 19:43:22 2006
+++ llvm/lib/Target/PowerPC/PPCISelLowering.h	Thu Mar 30 23:13:27 2006
@@ -85,6 +85,12 @@
       /// This copies the bits corresponding to the specified CRREG into the
       /// resultant GPR.  Bits corresponding to other CR regs are undefined.
       MFCR,
+
+      /// RESVEC = VCMP(LHS, RHS, OPC) - Represents one of the altivec VCMP*
+      /// instructions.  For lack of better number, we use the opcode number
+      /// encoding for the OPC field to identify the compare.  For example, 838
+      /// is VCMPGTSH.
+      VCMP,
       
       /// RESVEC, OUTFLAG = VCMPo(LHS, RHS, OPC) - Represents one of the
       /// altivec VCMP*o instructions.  For lack of better number, we use the 


Index: llvm/lib/Target/PowerPC/PPCInstrAltivec.td
diff -u llvm/lib/Target/PowerPC/PPCInstrAltivec.td:1.21 llvm/lib/Target/PowerPC/PPCInstrAltivec.td:1.22
--- llvm/lib/Target/PowerPC/PPCInstrAltivec.td:1.21	Thu Mar 30 17:39:06 2006
+++ llvm/lib/Target/PowerPC/PPCInstrAltivec.td	Thu Mar 30 23:13:27 2006
@@ -453,32 +453,32 @@
 // f32 element comparisons.
 def VCMPBFP   : VXRForm_1<966, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
                           "vcmpbfp $vD, $vA, $vB", VecFPCompare,
-                          [(set VRRC:$vD, 
-                                (int_ppc_altivec_vcmpbfp VRRC:$vA, VRRC:$vB))]>;
+                          [(set VRRC:$vD, (v4f32
+                                (PPCvcmp VRRC:$vA, VRRC:$vB, 966)))]>;
 def VCMPBFPo  : VXRForm_1<966, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
                           "vcmpbfp. $vD, $vA, $vB", VecFPCompare,
                           [(set VRRC:$vD, (v4f32
                                 (PPCvcmp_o VRRC:$vA, VRRC:$vB, 966)))]>, isVDOT;
 def VCMPEQFP  : VXRForm_1<198, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
                          "vcmpeqfp $vD, $vA, $vB", VecFPCompare,
-                         [(set VRRC:$vD, 
-                               (int_ppc_altivec_vcmpeqfp VRRC:$vA, VRRC:$vB))]>;
+                         [(set VRRC:$vD, (v4f32
+                               (PPCvcmp VRRC:$vA, VRRC:$vB, 198)))]>;
 def VCMPEQFPo : VXRForm_1<198, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
                          "vcmpeqfp. $vD, $vA, $vB", VecFPCompare,
                          [(set VRRC:$vD, (v4f32
                                 (PPCvcmp_o VRRC:$vA, VRRC:$vB, 198)))]>, isVDOT;
 def VCMPGEFP  : VXRForm_1<454, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
                          "vcmpgefp $vD, $vA, $vB", VecFPCompare,
-                         [(set VRRC:$vD, 
-                               (int_ppc_altivec_vcmpgefp VRRC:$vA, VRRC:$vB))]>;
+                         [(set VRRC:$vD, (v4f32
+                               (PPCvcmp VRRC:$vA, VRRC:$vB, 454)))]>;
 def VCMPGEFPo : VXRForm_1<454, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
                          "vcmpgefp. $vD, $vA, $vB", VecFPCompare,
                          [(set VRRC:$vD, (v4f32
                                 (PPCvcmp_o VRRC:$vA, VRRC:$vB, 454)))]>, isVDOT;
 def VCMPGTFP  : VXRForm_1<710, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
                          "vcmpgtfp $vD, $vA, $vB", VecFPCompare,
-                         [(set VRRC:$vD, 
-                               (int_ppc_altivec_vcmpgtfp VRRC:$vA, VRRC:$vB))]>;
+                         [(set VRRC:$vD, (v4f32
+                               (PPCvcmp VRRC:$vA, VRRC:$vB, 710)))]>;
 def VCMPGTFPo : VXRForm_1<710, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
                          "vcmpgtfp. $vD, $vA, $vB", VecFPCompare,
                          [(set VRRC:$vD, (v4f32
@@ -487,24 +487,24 @@
 // i8 element comparisons.
 def VCMPEQUB  : VXRForm_1<6, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
                          "vcmpequb $vD, $vA, $vB", VecFPCompare,
-                         [(set VRRC:$vD, 
-                               (int_ppc_altivec_vcmpequb VRRC:$vA, VRRC:$vB))]>;
+                         [(set VRRC:$vD, (v16i8
+                               (PPCvcmp VRRC:$vA, VRRC:$vB, 6)))]>;
 def VCMPEQUBo : VXRForm_1<6, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
                          "vcmpequb. $vD, $vA, $vB", VecFPCompare,
                          [(set VRRC:$vD, (v16i8
                                 (PPCvcmp_o VRRC:$vA, VRRC:$vB, 6)))]>, isVDOT;
 def VCMPGTSB  : VXRForm_1<774, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
                          "vcmpgtsb $vD, $vA, $vB", VecFPCompare,
-                         [(set VRRC:$vD, 
-                               (int_ppc_altivec_vcmpgtsb VRRC:$vA, VRRC:$vB))]>;
+                         [(set VRRC:$vD, (v16i8
+                               (PPCvcmp VRRC:$vA, VRRC:$vB, 774)))]>;
 def VCMPGTSBo : VXRForm_1<774, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
                          "vcmpgtsb. $vD, $vA, $vB", VecFPCompare,
                          [(set VRRC:$vD, (v16i8
                                 (PPCvcmp_o VRRC:$vA, VRRC:$vB, 774)))]>, isVDOT;
 def VCMPGTUB  : VXRForm_1<518, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
                          "vcmpgtub $vD, $vA, $vB", VecFPCompare,
-                         [(set VRRC:$vD, 
-                               (int_ppc_altivec_vcmpgtub VRRC:$vA, VRRC:$vB))]>;
+                         [(set VRRC:$vD, (v16i8
+                               (PPCvcmp VRRC:$vA, VRRC:$vB, 518)))]>;
 def VCMPGTUBo : VXRForm_1<518, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
                          "vcmpgtub. $vD, $vA, $vB", VecFPCompare,
                          [(set VRRC:$vD, (v16i8 
@@ -513,24 +513,24 @@
 // i16 element comparisons.
 def VCMPEQUH  : VXRForm_1<70, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
                          "vcmpequh $vD, $vA, $vB", VecFPCompare,
-                         [(set VRRC:$vD, 
-                               (int_ppc_altivec_vcmpequh VRRC:$vA, VRRC:$vB))]>;
+                         [(set VRRC:$vD, (v8i16 
+                               (PPCvcmp VRRC:$vA, VRRC:$vB, 70)))]>;
 def VCMPEQUHo : VXRForm_1<70, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
                          "vcmpequh. $vD, $vA, $vB", VecFPCompare,
                          [(set VRRC:$vD, (v8i16 
                                 (PPCvcmp_o VRRC:$vA, VRRC:$vB, 70)))]>, isVDOT;
 def VCMPGTSH  : VXRForm_1<838, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
                          "vcmpgtsh $vD, $vA, $vB", VecFPCompare,
-                         [(set VRRC:$vD, 
-                               (int_ppc_altivec_vcmpgtsh VRRC:$vA, VRRC:$vB))]>;
+                         [(set VRRC:$vD, (v8i16 
+                               (PPCvcmp VRRC:$vA, VRRC:$vB, 838)))]>;
 def VCMPGTSHo : VXRForm_1<838, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
                          "vcmpgtsh. $vD, $vA, $vB", VecFPCompare,
                          [(set VRRC:$vD, (v8i16 
                                 (PPCvcmp_o VRRC:$vA, VRRC:$vB, 838)))]>, isVDOT;
 def VCMPGTUH  : VXRForm_1<582, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
                          "vcmpgtuh $vD, $vA, $vB", VecFPCompare,
-                         [(set VRRC:$vD, 
-                               (int_ppc_altivec_vcmpgtuh VRRC:$vA, VRRC:$vB))]>;
+                         [(set VRRC:$vD, (v8i16 
+                               (PPCvcmp VRRC:$vA, VRRC:$vB, 582)))]>;
 def VCMPGTUHo : VXRForm_1<582, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
                          "vcmpgtuh. $vD, $vA, $vB", VecFPCompare,
                          [(set VRRC:$vD, (v8i16 
@@ -539,24 +539,23 @@
 // i32 element comparisons.
 def VCMPEQUW  : VXRForm_1<134, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
                          "vcmpequw $vD, $vA, $vB", VecFPCompare,
-                         [(set VRRC:$vD, 
-                               (int_ppc_altivec_vcmpequw VRRC:$vA, VRRC:$vB))]>;
+                         [(set VRRC:$vD, (PPCvcmp VRRC:$vA, VRRC:$vB, 134))]>;
 def VCMPEQUWo : VXRForm_1<134, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
                          "vcmpequw. $vD, $vA, $vB", VecFPCompare,
                          [(set VRRC:$vD, (v4i32
                                 (PPCvcmp_o VRRC:$vA, VRRC:$vB, 134)))]>, isVDOT;
 def VCMPGTSW  : VXRForm_1<902, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
                          "vcmpgtsw $vD, $vA, $vB", VecFPCompare,
-                         [(set VRRC:$vD, 
-                               (int_ppc_altivec_vcmpgtsw VRRC:$vA, VRRC:$vB))]>;
+                         [(set VRRC:$vD, (v4i32
+                               (PPCvcmp VRRC:$vA, VRRC:$vB, 902)))]>;
 def VCMPGTSWo : VXRForm_1<902, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
                          "vcmpgtsw. $vD, $vA, $vB", VecFPCompare,
                          [(set VRRC:$vD, (v4i32
                                 (PPCvcmp_o VRRC:$vA, VRRC:$vB, 902)))]>, isVDOT;
 def VCMPGTUW  : VXRForm_1<646, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
                          "vcmpgtuw $vD, $vA, $vB", VecFPCompare,
-                         [(set VRRC:$vD, 
-                               (int_ppc_altivec_vcmpgtuw VRRC:$vA, VRRC:$vB))]>;
+                         [(set VRRC:$vD, (v4i32
+                               (PPCvcmp VRRC:$vA, VRRC:$vB, 646)))]>;
 def VCMPGTUWo : VXRForm_1<646, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
                          "vcmpgtuw. $vD, $vA, $vB", VecFPCompare,
                          [(set VRRC:$vD, (v4i32


Index: llvm/lib/Target/PowerPC/PPCInstrInfo.td
diff -u llvm/lib/Target/PowerPC/PPCInstrInfo.td:1.213 llvm/lib/Target/PowerPC/PPCInstrInfo.td:1.214
--- llvm/lib/Target/PowerPC/PPCInstrInfo.td:1.213	Mon Mar 27 19:43:22 2006
+++ llvm/lib/Target/PowerPC/PPCInstrInfo.td	Thu Mar 30 23:13:27 2006
@@ -30,7 +30,7 @@
   SDTCisVT<3, v16i8>, SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>
 ]>;
 
-def SDT_PPCvcmp_o : SDTypeProfile<1, 3, [
+def SDT_PPCvcmp : SDTypeProfile<1, 3, [
   SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>, SDTCisVT<3, i32>
 ]>;
 
@@ -71,7 +71,8 @@
 def retflag       : SDNode<"PPCISD::RET_FLAG", SDT_PPCRetFlag,
 	                   [SDNPHasChain, SDNPOptInFlag]>;
 
-def PPCvcmp_o     : SDNode<"PPCISD::VCMPo", SDT_PPCvcmp_o, [SDNPOutFlag]>;
+def PPCvcmp       : SDNode<"PPCISD::VCMP" , SDT_PPCvcmp, []>;
+def PPCvcmp_o     : SDNode<"PPCISD::VCMPo", SDT_PPCvcmp, [SDNPOutFlag]>;
 
 //===----------------------------------------------------------------------===//
 // PowerPC specific transformation functions and pattern fragments.





From lattner at cs.uiuc.edu  Thu Mar 30 23:26:08 2006
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Thu, 30 Mar 2006 23:26:08 -0600
Subject: [llvm-commits] CVS: llvm/utils/TableGen/DAGISelEmitter.cpp 
Message-ID: <200603310526.XAA11075@zion.cs.uiuc.edu>



Changes in directory llvm/utils/TableGen:

DAGISelEmitter.cpp updated: 1.191 -> 1.192
---
Log message:

Allow bits init values to be used in patterns, turn them into ints.


---
Diffs of the changes:  (+19 -0)

 DAGISelEmitter.cpp |   19 +++++++++++++++++++
 1 files changed, 19 insertions(+)


Index: llvm/utils/TableGen/DAGISelEmitter.cpp
diff -u llvm/utils/TableGen/DAGISelEmitter.cpp:1.191 llvm/utils/TableGen/DAGISelEmitter.cpp:1.192
--- llvm/utils/TableGen/DAGISelEmitter.cpp:1.191	Thu Mar 30 16:50:40 2006
+++ llvm/utils/TableGen/DAGISelEmitter.cpp	Thu Mar 30 23:25:56 2006
@@ -830,6 +830,15 @@
       New = new TreePatternNode(II);
       if (!Dag->getArgName(0).empty())
         error("Constant int argument should not have a name!");
+    } else if (BitsInit *BI = dynamic_cast<BitsInit*>(Arg)) {
+      // Turn this into an IntInit.
+      Init *II = BI->convertInitializerTo(new IntRecTy());
+      if (II == 0 || !dynamic_cast<IntInit*>(II))
+        error("Bits value must be constants!");
+      
+      New = new TreePatternNode(dynamic_cast<IntInit*>(II));
+      if (!Dag->getArgName(0).empty())
+        error("Constant int argument should not have a name!");
     } else {
       Arg->dump();
       error("Unknown leaf value for tree pattern!");
@@ -888,6 +897,16 @@
       if (!Dag->getArgName(i).empty())
         error("Constant int argument should not have a name!");
       Children.push_back(Node);
+    } else if (BitsInit *BI = dynamic_cast<BitsInit*>(Arg)) {
+      // Turn this into an IntInit.
+      Init *II = BI->convertInitializerTo(new IntRecTy());
+      if (II == 0 || !dynamic_cast<IntInit*>(II))
+        error("Bits value must be constants!");
+      
+      TreePatternNode *Node = new TreePatternNode(dynamic_cast<IntInit*>(II));
+      if (!Dag->getArgName(i).empty())
+        error("Constant int argument should not have a name!");
+      Children.push_back(Node);
     } else {
       std::cerr << '"';
       Arg->dump();





From lattner at cs.uiuc.edu  Thu Mar 30 23:33:10 2006
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Thu, 30 Mar 2006 23:33:10 -0600
Subject: [llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCInstrAltivec.td 
Message-ID: <200603310533.XAA11156@zion.cs.uiuc.edu>



Changes in directory llvm/lib/Target/PowerPC:

PPCInstrAltivec.td updated: 1.22 -> 1.23
---
Log message:

Compactify comparisons.


---
Diffs of the changes:  (+34 -104)

 PPCInstrAltivec.td |  138 +++++++++++++----------------------------------------
 1 files changed, 34 insertions(+), 104 deletions(-)


Index: llvm/lib/Target/PowerPC/PPCInstrAltivec.td
diff -u llvm/lib/Target/PowerPC/PPCInstrAltivec.td:1.22 llvm/lib/Target/PowerPC/PPCInstrAltivec.td:1.23
--- llvm/lib/Target/PowerPC/PPCInstrAltivec.td:1.22	Thu Mar 30 23:13:27 2006
+++ llvm/lib/Target/PowerPC/PPCInstrAltivec.td	Thu Mar 30 23:32:57 2006
@@ -450,116 +450,46 @@
 
 // Altivec Comparisons.
 
-// f32 element comparisons.
-def VCMPBFP   : VXRForm_1<966, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
-                          "vcmpbfp $vD, $vA, $vB", VecFPCompare,
-                          [(set VRRC:$vD, (v4f32
-                                (PPCvcmp VRRC:$vA, VRRC:$vB, 966)))]>;
-def VCMPBFPo  : VXRForm_1<966, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
-                          "vcmpbfp. $vD, $vA, $vB", VecFPCompare,
-                          [(set VRRC:$vD, (v4f32
-                                (PPCvcmp_o VRRC:$vA, VRRC:$vB, 966)))]>, isVDOT;
-def VCMPEQFP  : VXRForm_1<198, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
-                         "vcmpeqfp $vD, $vA, $vB", VecFPCompare,
-                         [(set VRRC:$vD, (v4f32
-                               (PPCvcmp VRRC:$vA, VRRC:$vB, 198)))]>;
-def VCMPEQFPo : VXRForm_1<198, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
-                         "vcmpeqfp. $vD, $vA, $vB", VecFPCompare,
-                         [(set VRRC:$vD, (v4f32
-                                (PPCvcmp_o VRRC:$vA, VRRC:$vB, 198)))]>, isVDOT;
-def VCMPGEFP  : VXRForm_1<454, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
-                         "vcmpgefp $vD, $vA, $vB", VecFPCompare,
-                         [(set VRRC:$vD, (v4f32
-                               (PPCvcmp VRRC:$vA, VRRC:$vB, 454)))]>;
-def VCMPGEFPo : VXRForm_1<454, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
-                         "vcmpgefp. $vD, $vA, $vB", VecFPCompare,
-                         [(set VRRC:$vD, (v4f32
-                                (PPCvcmp_o VRRC:$vA, VRRC:$vB, 454)))]>, isVDOT;
-def VCMPGTFP  : VXRForm_1<710, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
-                         "vcmpgtfp $vD, $vA, $vB", VecFPCompare,
-                         [(set VRRC:$vD, (v4f32
-                               (PPCvcmp VRRC:$vA, VRRC:$vB, 710)))]>;
-def VCMPGTFPo : VXRForm_1<710, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
-                         "vcmpgtfp. $vD, $vA, $vB", VecFPCompare,
-                         [(set VRRC:$vD, (v4f32
-                                (PPCvcmp_o VRRC:$vA, VRRC:$vB, 710)))]>, isVDOT;
+class VCMP<bits<10> xo, string asmstr, ValueType Ty>
+  : VXRForm_1<xo, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB), asmstr, VecFPCompare,
+              [(set VRRC:$vD, (Ty (PPCvcmp VRRC:$vA, VRRC:$vB, xo)))]>;
+class VCMPo<bits<10> xo, string asmstr, ValueType Ty>
+  : VXRForm_1<xo, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB), asmstr, VecFPCompare,
+              [(set VRRC:$vD, (Ty (PPCvcmp_o VRRC:$vA, VRRC:$vB, xo)))]>,isVDOT;
+
+// f32 element comparisons.0
+def VCMPBFP   : VCMP <966, "vcmpbfp $vD, $vA, $vB"  , v4f32>;
+def VCMPBFPo  : VCMPo<966, "vcmpbfp. $vD, $vA, $vB" , v4f32>;
+def VCMPEQFP  : VCMP <198, "vcmpeqfp $vD, $vA, $vB" , v4f32>;
+def VCMPEQFPo : VCMPo<198, "vcmpeqfp. $vD, $vA, $vB", v4f32>;
+def VCMPGEFP  : VCMP <454, "vcmpgefp $vD, $vA, $vB" , v4f32>;
+def VCMPGEFPo : VCMPo<454, "vcmpgefp. $vD, $vA, $vB", v4f32>;
+def VCMPGTFP  : VCMP <710, "vcmpgtfp $vD, $vA, $vB" , v4f32>;
+def VCMPGTFPo : VCMPo<710, "vcmpgtfp. $vD, $vA, $vB", v4f32>;
 
 // i8 element comparisons.
-def VCMPEQUB  : VXRForm_1<6, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
-                         "vcmpequb $vD, $vA, $vB", VecFPCompare,
-                         [(set VRRC:$vD, (v16i8
-                               (PPCvcmp VRRC:$vA, VRRC:$vB, 6)))]>;
-def VCMPEQUBo : VXRForm_1<6, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
-                         "vcmpequb. $vD, $vA, $vB", VecFPCompare,
-                         [(set VRRC:$vD, (v16i8
-                                (PPCvcmp_o VRRC:$vA, VRRC:$vB, 6)))]>, isVDOT;
-def VCMPGTSB  : VXRForm_1<774, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
-                         "vcmpgtsb $vD, $vA, $vB", VecFPCompare,
-                         [(set VRRC:$vD, (v16i8
-                               (PPCvcmp VRRC:$vA, VRRC:$vB, 774)))]>;
-def VCMPGTSBo : VXRForm_1<774, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
-                         "vcmpgtsb. $vD, $vA, $vB", VecFPCompare,
-                         [(set VRRC:$vD, (v16i8
-                                (PPCvcmp_o VRRC:$vA, VRRC:$vB, 774)))]>, isVDOT;
-def VCMPGTUB  : VXRForm_1<518, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
-                         "vcmpgtub $vD, $vA, $vB", VecFPCompare,
-                         [(set VRRC:$vD, (v16i8
-                               (PPCvcmp VRRC:$vA, VRRC:$vB, 518)))]>;
-def VCMPGTUBo : VXRForm_1<518, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
-                         "vcmpgtub. $vD, $vA, $vB", VecFPCompare,
-                         [(set VRRC:$vD, (v16i8 
-                                (PPCvcmp_o VRRC:$vA, VRRC:$vB, 518)))]>, isVDOT;
+def VCMPEQUB  : VCMP <  6, "vcmpequb $vD, $vA, $vB" , v16i8>;
+def VCMPEQUBo : VCMPo<  6, "vcmpequb. $vD, $vA, $vB", v16i8>;
+def VCMPGTSB  : VCMP <774, "vcmpgtsb $vD, $vA, $vB" , v16i8>;
+def VCMPGTSBo : VCMPo<774, "vcmpgtsb. $vD, $vA, $vB", v16i8>;
+def VCMPGTUB  : VCMP <518, "vcmpgtub $vD, $vA, $vB" , v16i8>;
+def VCMPGTUBo : VCMPo<518, "vcmpgtub. $vD, $vA, $vB", v16i8>;
 
 // i16 element comparisons.
-def VCMPEQUH  : VXRForm_1<70, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
-                         "vcmpequh $vD, $vA, $vB", VecFPCompare,
-                         [(set VRRC:$vD, (v8i16 
-                               (PPCvcmp VRRC:$vA, VRRC:$vB, 70)))]>;
-def VCMPEQUHo : VXRForm_1<70, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
-                         "vcmpequh. $vD, $vA, $vB", VecFPCompare,
-                         [(set VRRC:$vD, (v8i16 
-                                (PPCvcmp_o VRRC:$vA, VRRC:$vB, 70)))]>, isVDOT;
-def VCMPGTSH  : VXRForm_1<838, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
-                         "vcmpgtsh $vD, $vA, $vB", VecFPCompare,
-                         [(set VRRC:$vD, (v8i16 
-                               (PPCvcmp VRRC:$vA, VRRC:$vB, 838)))]>;
-def VCMPGTSHo : VXRForm_1<838, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
-                         "vcmpgtsh. $vD, $vA, $vB", VecFPCompare,
-                         [(set VRRC:$vD, (v8i16 
-                                (PPCvcmp_o VRRC:$vA, VRRC:$vB, 838)))]>, isVDOT;
-def VCMPGTUH  : VXRForm_1<582, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
-                         "vcmpgtuh $vD, $vA, $vB", VecFPCompare,
-                         [(set VRRC:$vD, (v8i16 
-                               (PPCvcmp VRRC:$vA, VRRC:$vB, 582)))]>;
-def VCMPGTUHo : VXRForm_1<582, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
-                         "vcmpgtuh. $vD, $vA, $vB", VecFPCompare,
-                         [(set VRRC:$vD, (v8i16 
-                                (PPCvcmp_o VRRC:$vA, VRRC:$vB, 582)))]>, isVDOT;
+def VCMPEQUH  : VCMP < 70, "vcmpequh $vD, $vA, $vB" , v8i16>;
+def VCMPEQUHo : VCMPo< 70, "vcmpequh. $vD, $vA, $vB", v8i16>;
+def VCMPGTSH  : VCMP <838, "vcmpgtsh $vD, $vA, $vB" , v8i16>;
+def VCMPGTSHo : VCMPo<838, "vcmpgtsh. $vD, $vA, $vB", v8i16>;
+def VCMPGTUH  : VCMP <582, "vcmpgtuh $vD, $vA, $vB" , v8i16>;
+def VCMPGTUHo : VCMPo<582, "vcmpgtuh. $vD, $vA, $vB", v8i16>;
 
 // i32 element comparisons.
-def VCMPEQUW  : VXRForm_1<134, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
-                         "vcmpequw $vD, $vA, $vB", VecFPCompare,
-                         [(set VRRC:$vD, (PPCvcmp VRRC:$vA, VRRC:$vB, 134))]>;
-def VCMPEQUWo : VXRForm_1<134, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
-                         "vcmpequw. $vD, $vA, $vB", VecFPCompare,
-                         [(set VRRC:$vD, (v4i32
-                                (PPCvcmp_o VRRC:$vA, VRRC:$vB, 134)))]>, isVDOT;
-def VCMPGTSW  : VXRForm_1<902, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
-                         "vcmpgtsw $vD, $vA, $vB", VecFPCompare,
-                         [(set VRRC:$vD, (v4i32
-                               (PPCvcmp VRRC:$vA, VRRC:$vB, 902)))]>;
-def VCMPGTSWo : VXRForm_1<902, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
-                         "vcmpgtsw. $vD, $vA, $vB", VecFPCompare,
-                         [(set VRRC:$vD, (v4i32
-                                (PPCvcmp_o VRRC:$vA, VRRC:$vB, 902)))]>, isVDOT;
-def VCMPGTUW  : VXRForm_1<646, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
-                         "vcmpgtuw $vD, $vA, $vB", VecFPCompare,
-                         [(set VRRC:$vD, (v4i32
-                               (PPCvcmp VRRC:$vA, VRRC:$vB, 646)))]>;
-def VCMPGTUWo : VXRForm_1<646, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
-                         "vcmpgtuw. $vD, $vA, $vB", VecFPCompare,
-                         [(set VRRC:$vD, (v4i32
-                                (PPCvcmp_o VRRC:$vA, VRRC:$vB, 646)))]>, isVDOT;
+def VCMPEQUW  : VCMP <134, "vcmpequw $vD, $vA, $vB" , v4i32>;
+def VCMPEQUWo : VCMPo<134, "vcmpequw. $vD, $vA, $vB", v4i32>;
+def VCMPGTSW  : VCMP <902, "vcmpgtsw $vD, $vA, $vB" , v4i32>;
+def VCMPGTSWo : VCMPo<902, "vcmpgtsw. $vD, $vA, $vB", v4i32>;
+def VCMPGTUW  : VCMP <646, "vcmpgtuw $vD, $vA, $vB" , v4i32>;
+def VCMPGTUWo : VCMPo<646, "vcmpgtuw. $vD, $vA, $vB", v4i32>;
                       
 def V_SET0 : VXForm_setzero<1220, (ops VRRC:$vD),
                       "vxor $vD, $vD, $vD", VecFP,





From lattner at cs.uiuc.edu  Thu Mar 30 23:38:44 2006
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Thu, 30 Mar 2006 23:38:44 -0600
Subject: [llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCInstrAltivec.td 
Message-ID: <200603310538.XAA11254@zion.cs.uiuc.edu>



Changes in directory llvm/lib/Target/PowerPC:

PPCInstrAltivec.td updated: 1.23 -> 1.24
---
Log message:

compactify some more instruction definitions



---
Diffs of the changes:  (+15 -61)

 PPCInstrAltivec.td |   76 ++++++++++-------------------------------------------
 1 files changed, 15 insertions(+), 61 deletions(-)


Index: llvm/lib/Target/PowerPC/PPCInstrAltivec.td
diff -u llvm/lib/Target/PowerPC/PPCInstrAltivec.td:1.23 llvm/lib/Target/PowerPC/PPCInstrAltivec.td:1.24
--- llvm/lib/Target/PowerPC/PPCInstrAltivec.td:1.23	Thu Mar 30 23:32:57 2006
+++ llvm/lib/Target/PowerPC/PPCInstrAltivec.td	Thu Mar 30 23:38:32 2006
@@ -306,35 +306,13 @@
                       "vxor $vD, $vA, $vB", VecFP,
                       [(set VRRC:$vD, (xor (v4i32 VRRC:$vA), VRRC:$vB))]>;
 
-def VRLB   : VXForm_1<4, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
-                      "vrlb $vD, $vA, $vB", VecFP,
-                      [(set VRRC:$vD,
-                             (int_ppc_altivec_vrlb VRRC:$vA, VRRC:$vB))]>;
-def VRLH   : VXForm_1<68, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
-                      "vrlh $vD, $vA, $vB", VecFP,
-                      [(set VRRC:$vD,
-                             (int_ppc_altivec_vrlh VRRC:$vA, VRRC:$vB))]>;
-def VRLW   : VXForm_1<132, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
-                      "vrlw $vD, $vA, $vB", VecFP,
-                      [(set VRRC:$vD,
-                             (int_ppc_altivec_vrlw VRRC:$vA, VRRC:$vB))]>;
-
-def VSLO   : VXForm_1<1036, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
-                      "vslo $vD, $vA, $vB", VecFP,
-                      [(set VRRC:$vD,
-                             (int_ppc_altivec_vslo VRRC:$vA, VRRC:$vB))]>;
-def VSLB   : VXForm_1<260, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
-                      "vslb $vD, $vA, $vB", VecFP,
-                      [(set VRRC:$vD,
-                             (int_ppc_altivec_vslb VRRC:$vA, VRRC:$vB))]>;
-def VSLH   : VXForm_1<324, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
-                      "vslh $vD, $vA, $vB", VecFP,
-                      [(set VRRC:$vD,
-                             (int_ppc_altivec_vslh VRRC:$vA, VRRC:$vB))]>;
-def VSLW   : VXForm_1<388, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
-                      "vslw $vD, $vA, $vB", VecFP,
-                      [(set VRRC:$vD,
-                             (int_ppc_altivec_vslw VRRC:$vA, VRRC:$vB))]>;
+def VRLB   : VX1_Int<   4, "vrlb $vD, $vA, $vB", int_ppc_altivec_vrlb>;
+def VRLH   : VX1_Int<  68, "vrlh $vD, $vA, $vB", int_ppc_altivec_vrlh>;
+def VRLW   : VX1_Int< 132, "vrlw $vD, $vA, $vB", int_ppc_altivec_vrlw>;
+def VSLO   : VX1_Int<1036, "vslo $vD, $vA, $vB", int_ppc_altivec_vslo>;
+def VSLB   : VX1_Int< 260, "vslb $vD, $vA, $vB", int_ppc_altivec_vslb>;
+def VSLH   : VX1_Int< 324, "vslh $vD, $vA, $vB", int_ppc_altivec_vslh>;
+def VSLW   : VX1_Int< 388, "vslw $vD, $vA, $vB", int_ppc_altivec_vslw>;
 
 def VSPLTB : VXForm_1<524, (ops VRRC:$vD, u5imm:$UIMM, VRRC:$vB),
                       "vspltb $vD, $vB, $UIMM", VecPerm,
@@ -347,38 +325,14 @@
                       [(set VRRC:$vD, (vector_shuffle (v4f32 VRRC:$vB), (undef),
                                       VSPLT_shuffle_mask:$UIMM))]>;
 
-def VSR    : VXForm_1<708, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
-                      "vsr $vD, $vA, $vB", VecFP,
-                      [(set VRRC:$vD,
-                             (int_ppc_altivec_vsr VRRC:$vA, VRRC:$vB))]>;
-def VSRO   : VXForm_1<1100, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
-                      "vsro $vD, $vA, $vB", VecFP,
-                      [(set VRRC:$vD,
-                             (int_ppc_altivec_vsro VRRC:$vA, VRRC:$vB))]>;
-def VSRAB  : VXForm_1<772, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
-                      "vsrab $vD, $vA, $vB", VecFP,
-                      [(set VRRC:$vD,
-                             (int_ppc_altivec_vsrab VRRC:$vA, VRRC:$vB))]>;
-def VSRAH  : VXForm_1<836, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
-                      "vsrah $vD, $vA, $vB", VecFP,
-                      [(set VRRC:$vD,
-                             (int_ppc_altivec_vsrah VRRC:$vA, VRRC:$vB))]>;
-def VSRAW  : VXForm_1<900, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
-                      "vsraw $vD, $vA, $vB", VecFP,
-                      [(set VRRC:$vD,
-                             (int_ppc_altivec_vsraw VRRC:$vA, VRRC:$vB))]>;
-def VSRB   : VXForm_1<516, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
-                      "vsrb $vD, $vA, $vB", VecFP,
-                      [(set VRRC:$vD,
-                             (int_ppc_altivec_vsrb VRRC:$vA, VRRC:$vB))]>;
-def VSRH   : VXForm_1<580, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
-                      "vsrh $vD, $vA, $vB", VecFP,
-                      [(set VRRC:$vD,
-                             (int_ppc_altivec_vsrh VRRC:$vA, VRRC:$vB))]>;
-def VSRW   : VXForm_1<644, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
-                      "vsrw $vD, $vA, $vB", VecFP,
-                      [(set VRRC:$vD,
-                             (int_ppc_altivec_vsrw VRRC:$vA, VRRC:$vB))]>;
+def VSR    : VX1_Int< 708, "vsr $vD, $vA, $vB"  , int_ppc_altivec_vsr>;
+def VSRO   : VX1_Int<1100, "vsro $vD, $vA, $vB" , int_ppc_altivec_vsro>;
+def VSRAB  : VX1_Int< 772, "vsrab $vD, $vA, $vB", int_ppc_altivec_vsrab>;
+def VSRAH  : VX1_Int< 836, "vsrah $vD, $vA, $vB", int_ppc_altivec_vsrah>;
+def VSRAW  : VX1_Int< 900, "vsraw $vD, $vA, $vB", int_ppc_altivec_vsraw>;
+def VSRB   : VX1_Int< 516, "vsrb $vD, $vA, $vB" , int_ppc_altivec_vsrb>;
+def VSRH   : VX1_Int< 580, "vsrh $vD, $vA, $vB" , int_ppc_altivec_vsrh>;
+def VSRW   : VX1_Int< 644, "vsrw $vD, $vA, $vB" , int_ppc_altivec_vsrw>;
 
 
 def VSPLTISB : VXForm_3<780, (ops VRRC:$vD, s5imm:$SIMM),





From lattner at cs.uiuc.edu  Fri Mar 31 00:02:00 2006
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Fri, 31 Mar 2006 00:02:00 -0600
Subject: [llvm-commits] 
	CVS: llvm/test/Regression/CodeGen/PowerPC/vcmp-fold.ll
Message-ID: <200603310602.AAA11483@zion.cs.uiuc.edu>



Changes in directory llvm/test/Regression/CodeGen/PowerPC:

vcmp-fold.ll added (r1.1)
---
Log message:

new testcase


---
Diffs of the changes:  (+21 -0)

 vcmp-fold.ll |   21 +++++++++++++++++++++
 1 files changed, 21 insertions(+)


Index: llvm/test/Regression/CodeGen/PowerPC/vcmp-fold.ll
diff -c /dev/null llvm/test/Regression/CodeGen/PowerPC/vcmp-fold.ll:1.1
*** /dev/null	Fri Mar 31 00:01:58 2006
--- llvm/test/Regression/CodeGen/PowerPC/vcmp-fold.ll	Fri Mar 31 00:01:48 2006
***************
*** 0 ****
--- 1,21 ----
+ ; This should fold the "vcmpbfp." and "vcmpbfp" instructions into a single 
+ ; "vcmpbfp.".
+ ; RUN: llvm-as < %s | llc -march=ppc32 -mcpu=g5 | grep vcmpbfp | wc -l | grep 1
+ 
+ void %test(<4 x float>* %x, <4 x float>* %y, int* %P) {
+ entry:
+ 	%tmp = load <4 x float>* %x		; <<4 x float>> [#uses=1]
+ 	%tmp2 = load <4 x float>* %y		; <<4 x float>> [#uses=1]
+ 	%tmp = call int %llvm.ppc.altivec.vcmpbfp.p( int 1, <4 x float> %tmp, <4 x float> %tmp2 )		; <int> [#uses=1]
+ 	%tmp4 = load <4 x float>* %x		; <<4 x float>> [#uses=1]
+ 	%tmp6 = load <4 x float>* %y		; <<4 x float>> [#uses=1]
+ 	%tmp = call <4 x int> %llvm.ppc.altivec.vcmpbfp( <4 x float> %tmp4, <4 x float> %tmp6 )		; <<4 x int>> [#uses=1]
+ 	%tmp7 = cast <4 x int> %tmp to <4 x float>		; <<4 x float>> [#uses=1]
+ 	store <4 x float> %tmp7, <4 x float>* %x
+ 	store int %tmp, int* %P
+ 	ret void
+ }
+ 
+ declare int %llvm.ppc.altivec.vcmpbfp.p(int, <4 x float>, <4 x float>)
+ 
+ declare <4 x int> %llvm.ppc.altivec.vcmpbfp(<4 x float>, <4 x float>)





From lattner at cs.uiuc.edu  Fri Mar 31 00:02:19 2006
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Fri, 31 Mar 2006 00:02:19 -0600
Subject: [llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCISelLowering.cpp
	README_ALTIVEC.txt 
Message-ID: <200603310602.AAA11495@zion.cs.uiuc.edu>



Changes in directory llvm/lib/Target/PowerPC:

PPCISelLowering.cpp updated: 1.120 -> 1.121
README_ALTIVEC.txt updated: 1.7 -> 1.8
---
Log message:

Implement an item from the readme, folding vcmp/vcmp. instructions with
identical instructions into a single instruction.  For example, for:

void test(vector float *x, vector float *y, int *P) {
  int v = vec_any_out(*x, *y);
  *x = (vector float)vec_cmpb(*x, *y);
  *P = v;
}

we now generate:

_test:
        mfspr r2, 256
        oris r6, r2, 49152
        mtspr 256: http://llvm.cs.uiuc.edu/PR256 , r6
        lvx v0, 0, r4
        lvx v1, 0, r3
        vcmpbfp. v0, v1, v0
        mfcr r4, 2
        stvx v0, 0, r3
        rlwinm r3, r4, 27, 31, 31
        xori r3, r3, 1
        stw r3, 0(r5)
        mtspr 256: http://llvm.cs.uiuc.edu/PR256 , r2
        blr

instead of:

_test:
        mfspr r2, 256
        oris r6, r2, 57344
        mtspr 256: http://llvm.cs.uiuc.edu/PR256 , r6
        lvx v0, 0, r4
        lvx v1, 0, r3
        vcmpbfp. v2, v1, v0
        mfcr r4, 2
***     vcmpbfp v0, v1, v0
        rlwinm r4, r4, 27, 31, 31
        stvx v0, 0, r3
        xori r3, r4, 1
        stw r3, 0(r5)
        mtspr 256: http://llvm.cs.uiuc.edu/PR256 , r2
        blr

Testcase here: CodeGen/PowerPC/vcmp-fold.ll



---
Diffs of the changes:  (+29 -9)

 PPCISelLowering.cpp |   29 +++++++++++++++++++++++++++++
 README_ALTIVEC.txt  |    9 ---------
 2 files changed, 29 insertions(+), 9 deletions(-)


Index: llvm/lib/Target/PowerPC/PPCISelLowering.cpp
diff -u llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.120 llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.121
--- llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.120	Thu Mar 30 23:13:27 2006
+++ llvm/lib/Target/PowerPC/PPCISelLowering.cpp	Fri Mar 31 00:02:07 2006
@@ -1368,6 +1368,35 @@
       return Val;
     }
     break;
+  case PPCISD::VCMP: {
+    // If a VCMPo node already exists with exactly the same operands as this
+    // node, use its result instead of this node (VCMPo computes both a CR6 and
+    // a normal output).
+    //
+    if (!N->getOperand(0).hasOneUse() &&
+        !N->getOperand(1).hasOneUse() &&
+        !N->getOperand(2).hasOneUse()) {
+      
+      // Scan all of the users of the LHS, looking for VCMPo's that match.
+      SDNode *VCMPoNode = 0;
+      
+      SDNode *LHSN = N->getOperand(0).Val;
+      for (SDNode::use_iterator UI = LHSN->use_begin(), E = LHSN->use_end();
+           UI != E; ++UI)
+        if ((*UI)->getOpcode() == PPCISD::VCMPo &&
+            (*UI)->getOperand(1) == N->getOperand(1) &&
+            (*UI)->getOperand(2) == N->getOperand(2) &&
+            (*UI)->getOperand(0) == N->getOperand(0)) {
+          VCMPoNode = *UI;
+          break;
+        }
+      
+      // If there are non-zero uses of the flag value, use the VCMPo node!
+      if (!VCMPoNode->hasNUsesOfValue(0, 1))
+        return SDOperand(VCMPoNode, 0);
+    }
+    break;
+  }
   }
   
   return SDOperand();


Index: llvm/lib/Target/PowerPC/README_ALTIVEC.txt
diff -u llvm/lib/Target/PowerPC/README_ALTIVEC.txt:1.7 llvm/lib/Target/PowerPC/README_ALTIVEC.txt:1.8
--- llvm/lib/Target/PowerPC/README_ALTIVEC.txt:1.7	Thu Mar 30 22:53:21 2006
+++ llvm/lib/Target/PowerPC/README_ALTIVEC.txt	Fri Mar 31 00:02:07 2006
@@ -131,15 +131,6 @@
 
 //===----------------------------------------------------------------------===//
 
-Two identical comparisons in predicate and nonpredicate form like this:
-
-a = vec_cmpb(x, y);
-b = vec_any_out(x, y);
-
-Should turn into one "." compare instruction, not a dot and "nondot" form.
-
-//===----------------------------------------------------------------------===//
-
 Instcombine llvm.ppc.altivec.vperm with an immediate into a shuffle operation.
 
 //===----------------------------------------------------------------------===//





From lattner at cs.uiuc.edu  Fri Mar 31 00:05:05 2006
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Fri, 31 Mar 2006 00:05:05 -0600
Subject: [llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCISelLowering.cpp 
Message-ID: <200603310605.AAA11589@zion.cs.uiuc.edu>



Changes in directory llvm/lib/Target/PowerPC:

PPCISelLowering.cpp updated: 1.121 -> 1.122
---
Log message:

note to self: *save* file, then check it in


---
Diffs of the changes:  (+1 -1)

 PPCISelLowering.cpp |    2 +-
 1 files changed, 1 insertion(+), 1 deletion(-)


Index: llvm/lib/Target/PowerPC/PPCISelLowering.cpp
diff -u llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.121 llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.122
--- llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.121	Fri Mar 31 00:02:07 2006
+++ llvm/lib/Target/PowerPC/PPCISelLowering.cpp	Fri Mar 31 00:04:53 2006
@@ -1392,7 +1392,7 @@
         }
       
       // If there are non-zero uses of the flag value, use the VCMPo node!
-      if (!VCMPoNode->hasNUsesOfValue(0, 1))
+      if (VCMPoNode && !VCMPoNode->hasNUsesOfValue(0, 1))
         return SDOperand(VCMPoNode, 0);
     }
     break;





From jeffc at jolt-lang.org  Fri Mar 31 01:22:17 2006
From: jeffc at jolt-lang.org (Jeff Cohen)
Date: Fri, 31 Mar 2006 01:22:17 -0600
Subject: [llvm-commits] CVS: llvm/lib/VMCore/Verifier.cpp 
Message-ID: <200603310722.BAA11843@zion.cs.uiuc.edu>



Changes in directory llvm/lib/VMCore:

Verifier.cpp updated: 1.151 -> 1.152
---
Log message:

Fix build breakage.

---
Diffs of the changes:  (+1 -0)

 Verifier.cpp |    1 +
 1 files changed, 1 insertion(+)


Index: llvm/lib/VMCore/Verifier.cpp
diff -u llvm/lib/VMCore/Verifier.cpp:1.151 llvm/lib/VMCore/Verifier.cpp:1.152
--- llvm/lib/VMCore/Verifier.cpp:1.151	Thu Mar 30 22:46:47 2006
+++ llvm/lib/VMCore/Verifier.cpp	Fri Mar 31 01:22:05 2006
@@ -60,6 +60,7 @@
 #include <algorithm>
 #include <iostream>
 #include <sstream>
+#include <cstdarg>
 using namespace llvm;
 
 namespace {  // Anonymous namespace for class





From lattner at cs.uiuc.edu  Fri Mar 31 11:37:34 2006
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Fri, 31 Mar 2006 11:37:34 -0600
Subject: [llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp 
Message-ID: <200603311737.LAA28156@zion.cs.uiuc.edu>



Changes in directory llvm/lib/CodeGen/SelectionDAG:

LegalizeDAG.cpp updated: 1.344 -> 1.345
---
Log message:

Scalarized vector stores need not be legal, e.g. if the vector element type
needs to be promoted or expanded.  Relegalize the scalar store once created.
This fixes CodeGen/Generic/vector.ll:test1 on non-SSE x86 targets.


---
Diffs of the changes:  (+3 -0)

 LegalizeDAG.cpp |    3 +++
 1 files changed, 3 insertions(+)


Index: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.344 llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.345
--- llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.344	Thu Mar 30 20:06:55 2006
+++ llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp	Fri Mar 31 11:37:22 2006
@@ -1477,6 +1477,9 @@
           Tmp3 = PackVectorOp(Node->getOperand(1), EVT);
           Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp3, Tmp2, 
                                           Node->getOperand(3));
+          // The scalarized value type may not be legal, e.g. it might require
+          // promotion or expansion.  Relegalize the scalar store.
+          Result = LegalizeOp(Result);
           break;
         } else {
           SplitVectorOp(Node->getOperand(1), Lo, Hi);





From lattner at cs.uiuc.edu  Fri Mar 31 11:56:03 2006
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Fri, 31 Mar 2006 11:56:03 -0600
Subject: [llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp 
Message-ID: <200603311756.LAA28411@zion.cs.uiuc.edu>



Changes in directory llvm/lib/CodeGen/SelectionDAG:

LegalizeDAG.cpp updated: 1.345 -> 1.346
---
Log message:

Implement PromoteOp for VEXTRACT_VECTOR_ELT.  Thsi fixes 
Generic/vector.ll:test_extract_elt on non-sse X86 systems.



---
Diffs of the changes:  (+54 -42)

 LegalizeDAG.cpp |   96 +++++++++++++++++++++++++++++++-------------------------
 1 files changed, 54 insertions(+), 42 deletions(-)


Index: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.345 llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.346
--- llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.345	Fri Mar 31 11:37:22 2006
+++ llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp	Fri Mar 31 11:55:51 2006
@@ -184,6 +184,8 @@
   void ExpandShiftParts(unsigned NodeOp, SDOperand Op, SDOperand Amt,
                         SDOperand &Lo, SDOperand &Hi);
 
+  SDOperand LowerVEXTRACT_VECTOR_ELT(SDOperand Op);
+  
   SDOperand getIntPtrConstant(uint64_t Val) {
     return DAG.getConstant(Val, TLI.getPointerTy());
   }
@@ -910,49 +912,9 @@
     }
     break;
 
-  case ISD::VEXTRACT_VECTOR_ELT: {
-    // We know that operand #0 is the Vec vector.  If the index is a constant
-    // or if the invec is a supported hardware type, we can use it.  Otherwise,
-    // lower to a store then an indexed load.
-    Tmp1 = Node->getOperand(0);
-    Tmp2 = LegalizeOp(Node->getOperand(1));
-    
-    SDNode *InVal = Tmp1.Val;
-    unsigned NumElems = cast<ConstantSDNode>(*(InVal->op_end()-2))->getValue();
-    MVT::ValueType EVT = cast<VTSDNode>(*(InVal->op_end()-1))->getVT();
-    
-    // Figure out if there is a Packed type corresponding to this Vector
-    // type.  If so, convert to the packed type.
-    MVT::ValueType TVT = MVT::getVectorType(EVT, NumElems);
-    if (TVT != MVT::Other && TLI.isTypeLegal(TVT)) {
-      // Turn this into a packed extract_vector_elt operation.
-      Tmp1 = PackVectorOp(Tmp1, TVT);
-      Result = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, Node->getValueType(0),
-                           Tmp1, Tmp2);
-      break;
-    } else if (NumElems == 1) {
-      // This must be an access of the only element.
-      Result = PackVectorOp(Tmp1, EVT);
-      break;
-    } else if (ConstantSDNode *CIdx = dyn_cast<ConstantSDNode>(Tmp2)) {
-      SDOperand Lo, Hi;
-      SplitVectorOp(Tmp1, Lo, Hi);
-      if (CIdx->getValue() < NumElems/2) {
-        Tmp1 = Lo;
-      } else {
-        Tmp1 = Hi;
-        Tmp2 = DAG.getConstant(CIdx->getValue() - NumElems/2,
-                               Tmp2.getValueType());
-      }
-
-      // It's now an extract from the appropriate high or low part.
-      Result = LegalizeOp(DAG.UpdateNodeOperands(Result, Tmp1, Tmp2));
-    } else {
-      // FIXME: IMPLEMENT STORE/LOAD lowering.  Need alignment of stack slot!!
-      assert(0 && "unimp!");
-    }
+  case ISD::VEXTRACT_VECTOR_ELT: 
+    Result = LegalizeOp(LowerVEXTRACT_VECTOR_ELT(Op));
     break;
-  }
     
   case ISD::CALLSEQ_START: {
     SDNode *CallEnd = FindCallEndFromCallStart(Node);
@@ -2999,6 +2961,9 @@
       break;
     }
     break;
+  case ISD::VEXTRACT_VECTOR_ELT:
+    Result = PromoteOp(LowerVEXTRACT_VECTOR_ELT(Op));
+    break;
   }
 
   assert(Result.Val && "Didn't set a result!");
@@ -3011,6 +2976,53 @@
   return Result;
 }
 
+/// LowerVEXTRACT_VECTOR_ELT - Lower a VEXTRACT_VECTOR_ELT operation into a
+/// EXTRACT_VECTOR_ELT operation, to memory operations, or to scalar code based
+/// on the vector type.  The return type of this matches the element type of the
+/// vector, which may not be legal for the target.
+SDOperand SelectionDAGLegalize::LowerVEXTRACT_VECTOR_ELT(SDOperand Op) {
+  // We know that operand #0 is the Vec vector.  If the index is a constant
+  // or if the invec is a supported hardware type, we can use it.  Otherwise,
+  // lower to a store then an indexed load.
+  SDOperand Vec = Op.getOperand(0);
+  SDOperand Idx = LegalizeOp(Op.getOperand(1));
+  
+  SDNode *InVal = Vec.Val;
+  unsigned NumElems = cast<ConstantSDNode>(*(InVal->op_end()-2))->getValue();
+  MVT::ValueType EVT = cast<VTSDNode>(*(InVal->op_end()-1))->getVT();
+  
+  // Figure out if there is a Packed type corresponding to this Vector
+  // type.  If so, convert to the packed type.
+  MVT::ValueType TVT = MVT::getVectorType(EVT, NumElems);
+  if (TVT != MVT::Other && TLI.isTypeLegal(TVT)) {
+    // Turn this into a packed extract_vector_elt operation.
+    Vec = PackVectorOp(Vec, TVT);
+    return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, Op.getValueType(), Vec, Idx);
+  } else if (NumElems == 1) {
+    // This must be an access of the only element.  Return it.
+    return PackVectorOp(Vec, EVT);
+  } else if (ConstantSDNode *CIdx = dyn_cast<ConstantSDNode>(Idx)) {
+    SDOperand Lo, Hi;
+    SplitVectorOp(Vec, Lo, Hi);
+    if (CIdx->getValue() < NumElems/2) {
+      Vec = Lo;
+    } else {
+      Vec = Hi;
+      Idx = DAG.getConstant(CIdx->getValue() - NumElems/2, Idx.getValueType());
+    }
+    
+    // It's now an extract from the appropriate high or low part.  Recurse.
+    Op = DAG.UpdateNodeOperands(Op, Vec, Idx);
+    return LowerVEXTRACT_VECTOR_ELT(Op);
+  } else {
+    // Variable index case for extract element.
+    // FIXME: IMPLEMENT STORE/LOAD lowering.  Need alignment of stack slot!!
+    assert(0 && "unimp!");
+    return SDOperand();
+  }
+}
+
+
 /// LegalizeSetCCOperands - Attempts to create a legal LHS and RHS for a SETCC
 /// with condition CC on the current target.  This usually involves legalizing
 /// or promoting the arguments.  In the case where LHS and RHS must be expanded,





From lattner at cs.uiuc.edu  Fri Mar 31 11:59:28 2006
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Fri, 31 Mar 2006 11:59:28 -0600
Subject: [llvm-commits] CVS: llvm/test/Regression/CodeGen/Generic/vector.ll 
Message-ID: <200603311759.LAA28484@zion.cs.uiuc.edu>



Changes in directory llvm/test/Regression/CodeGen/Generic:

vector.ll updated: 1.7 -> 1.8
---
Log message:

Make this test harder, always check generic x86 and SSE-enabled x86.


---
Diffs of the changes:  (+10 -1)

 vector.ll |   11 ++++++++++-
 1 files changed, 10 insertions(+), 1 deletion(-)


Index: llvm/test/Regression/CodeGen/Generic/vector.ll
diff -u llvm/test/Regression/CodeGen/Generic/vector.ll:1.7 llvm/test/Regression/CodeGen/Generic/vector.ll:1.8
--- llvm/test/Regression/CodeGen/Generic/vector.ll:1.7	Thu Mar 23 15:15:57 2006
+++ llvm/test/Regression/CodeGen/Generic/vector.ll	Fri Mar 31 11:59:16 2006
@@ -1,13 +1,16 @@
 ; Test that vectors are scalarized/lowered correctly.
 ; RUN: llvm-as < %s | llc && 
 ; RUN: llvm-as < %s | llc -march=ppc32 -mcpu=g5 &&
-; RUN: llvm-as < %s | llc -march=ppc32 -mcpu=g3
+; RUN: llvm-as < %s | llc -march=ppc32 -mcpu=g3 &&
+; RUN: llvm-as < %s | llc -march=x86 -mcpu=i386 &&
+; RUN: llvm-as < %s | llc -march=x86 -mcpu=yonah
 
 %f1 = type <1 x float>
 %f2 = type <2 x float>
 %f4 = type <4 x float>
 %i4 = type <4 x int>
 %f8 = type <8 x float>
+%d8 = type <8 x double>
 
 implementation
 
@@ -99,6 +102,12 @@
   ret float %R
 }
 
+double %test_extract_elt2(%d8 *%P) {
+  %p = load %d8* %P
+  %R = extractelement %d8 %p, uint 3
+  ret double %R
+}
+
 void %test_cast_1(<4 x float>* %b, <4 x int>* %a) {
   %tmp = load <4 x float>* %b
   %tmp2 = add <4 x float> %tmp, <float 1.0, float 2.0, float 3.0, float 4.0>





From lattner at cs.uiuc.edu  Fri Mar 31 12:06:30 2006
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Fri, 31 Mar 2006 12:06:30 -0600
Subject: [llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp 
Message-ID: <200603311806.MAA28638@zion.cs.uiuc.edu>



Changes in directory llvm/lib/CodeGen/SelectionDAG:

DAGCombiner.cpp updated: 1.133 -> 1.134
---
Log message:

Delete dead loads in the dag.  This allows us to compile 
vector.ll:test_extract_elt2 into:

_test_extract_elt2:
        lfd f1, 32(r3)
        blr

instead of:

_test_extract_elt2:
        lfd f0, 56(r3)
        lfd f0, 48(r3)
        lfd f0, 40(r3)
        lfd f1, 32(r3)
        lfd f0, 24(r3)
        lfd f0, 16(r3)
        lfd f0, 8(r3)
        lfd f0, 0(r3)
        blr



---
Diffs of the changes:  (+5 -0)

 DAGCombiner.cpp |    5 +++++
 1 files changed, 5 insertions(+)


Index: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.133 llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.134
--- llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.133	Tue Mar 28 16:19:47 2006
+++ llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp	Fri Mar 31 12:06:18 2006
@@ -2261,6 +2261,11 @@
   SDOperand Chain    = N->getOperand(0);
   SDOperand Ptr      = N->getOperand(1);
   SDOperand SrcValue = N->getOperand(2);
+
+  // If there are no uses of the loaded value, change uses of the chain value
+  // into uses of the chain input (i.e. delete the dead load).
+  if (N->hasNUsesOfValue(0, 0))
+    return CombineTo(N, DAG.getNode(ISD::UNDEF, N->getValueType(0)), Chain);
   
   // If this load is directly stored, replace the load value with the stored
   // value.





From lattner at cs.uiuc.edu  Fri Mar 31 12:10:53 2006
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Fri, 31 Mar 2006 12:10:53 -0600
Subject: [llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp 
Message-ID: <200603311810.MAA28719@zion.cs.uiuc.edu>



Changes in directory llvm/lib/CodeGen/SelectionDAG:

DAGCombiner.cpp updated: 1.134 -> 1.135
---
Log message:

Remove dead *extloads.  This allows us to codegen vector.ll:test_extract_elt
to:

test_extract_elt:
        alloc r3 = ar.pfs,0,1,0,0
        adds r8 = 12, r32
        ;;
        ldfs f8 = [r8]
        mov ar.pfs = r3
        br.ret.sptk.many rp

instead of:

test_extract_elt:
        alloc r3 = ar.pfs,0,1,0,0
        adds r8 = 28, r32
        adds r9 = 24, r32
        adds r10 = 20, r32
        adds r11 = 16, r32
        ;;
        ldfs f6 = [r8]
        ;;
        ldfs f6 = [r9]
        adds r8 = 12, r32
        adds r9 = 8, r32
        adds r14 = 4, r32
        ;;
        ldfs f6 = [r10]
        ;;
        ldfs f6 = [r11]
        ldfs f8 = [r8]
        ;;
        ldfs f6 = [r9]
        ;;
        ldfs f6 = [r14]
        ;;
        ldfs f6 = [r32]
        mov ar.pfs = r3
        br.ret.sptk.many rp



---
Diffs of the changes:  (+19 -0)

 DAGCombiner.cpp |   19 +++++++++++++++++++
 1 files changed, 19 insertions(+)


Index: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.134 llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.135
--- llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.134	Fri Mar 31 12:06:18 2006
+++ llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp	Fri Mar 31 12:10:41 2006
@@ -208,6 +208,7 @@
     SDOperand visitBRCOND(SDNode *N);
     SDOperand visitBR_CC(SDNode *N);
     SDOperand visitLOAD(SDNode *N);
+    SDOperand visitXEXTLOAD(SDNode *N);
     SDOperand visitSTORE(SDNode *N);
     SDOperand visitINSERT_VECTOR_ELT(SDNode *N);
     SDOperand visitVINSERT_VECTOR_ELT(SDNode *N);
@@ -643,6 +644,9 @@
   case ISD::BRCOND:             return visitBRCOND(N);
   case ISD::BR_CC:              return visitBR_CC(N);
   case ISD::LOAD:               return visitLOAD(N);
+  case ISD::EXTLOAD:
+  case ISD::SEXTLOAD:
+  case ISD::ZEXTLOAD:           return visitXEXTLOAD(N);
   case ISD::STORE:              return visitSTORE(N);
   case ISD::INSERT_VECTOR_ELT:  return visitINSERT_VECTOR_ELT(N);
   case ISD::VINSERT_VECTOR_ELT: return visitVINSERT_VECTOR_ELT(N);
@@ -2278,6 +2282,21 @@
   return SDOperand();
 }
 
+/// visitXEXTLOAD - Handle EXTLOAD/ZEXTLOAD/SEXTLOAD.
+SDOperand DAGCombiner::visitXEXTLOAD(SDNode *N) {
+  SDOperand Chain    = N->getOperand(0);
+  SDOperand Ptr      = N->getOperand(1);
+  SDOperand SrcValue = N->getOperand(2);
+  SDOperand EVT      = N->getOperand(3);
+  
+  // If there are no uses of the loaded value, change uses of the chain value
+  // into uses of the chain input (i.e. delete the dead load).
+  if (N->hasNUsesOfValue(0, 0))
+    return CombineTo(N, DAG.getNode(ISD::UNDEF, N->getValueType(0)), Chain);
+  
+  return SDOperand();
+}
+
 SDOperand DAGCombiner::visitSTORE(SDNode *N) {
   SDOperand Chain    = N->getOperand(0);
   SDOperand Value    = N->getOperand(1);





From lattner at cs.uiuc.edu  Fri Mar 31 12:20:58 2006
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Fri, 31 Mar 2006 12:20:58 -0600
Subject: [llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp 
Message-ID: <200603311820.MAA28834@zion.cs.uiuc.edu>



Changes in directory llvm/lib/CodeGen/SelectionDAG:

LegalizeDAG.cpp updated: 1.346 -> 1.347
---
Log message:

Do not endian swap the operands to a store if the operands came from a vector.

This fixes UnitTests/Vector/simple.c with altivec.


---
Diffs of the changes:  (+3 -3)

 LegalizeDAG.cpp |    6 +++---
 1 files changed, 3 insertions(+), 3 deletions(-)


Index: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.346 llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.347
--- llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.346	Fri Mar 31 11:55:51 2006
+++ llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp	Fri Mar 31 12:20:46 2006
@@ -1450,10 +1450,10 @@
       } else {
         ExpandOp(Node->getOperand(1), Lo, Hi);
         IncrementSize = MVT::getSizeInBits(Hi.getValueType())/8;
-      }
 
-      if (!TLI.isLittleEndian())
-        std::swap(Lo, Hi);
+        if (!TLI.isLittleEndian())
+          std::swap(Lo, Hi);
+      }
 
       Lo = DAG.getNode(ISD::STORE, MVT::Other, Tmp1, Lo, Tmp2,
                        Node->getOperand(3));





From lattner at cs.uiuc.edu  Fri Mar 31 12:22:49 2006
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Fri, 31 Mar 2006 12:22:49 -0600
Subject: [llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp 
Message-ID: <200603311822.MAA28904@zion.cs.uiuc.edu>



Changes in directory llvm/lib/CodeGen/SelectionDAG:

LegalizeDAG.cpp updated: 1.347 -> 1.348
---
Log message:

Do not endian swap split vector loads.  This fixes UnitTests/Vector/sumarray-dbl on PPC.

Now all UnitTests/Vector/* tests pass on PPC.


---
Diffs of the changes:  (+0 -2)

 LegalizeDAG.cpp |    2 --
 1 files changed, 2 deletions(-)


Index: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.347 llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.348
--- llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.347	Fri Mar 31 12:20:46 2006
+++ llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp	Fri Mar 31 12:22:37 2006
@@ -4453,8 +4453,6 @@
     
     // Remember that we legalized the chain.
     AddLegalizedOperand(Op.getValue(1), LegalizeOp(TF));
-    if (!TLI.isLittleEndian())
-      std::swap(Lo, Hi);
     break;
   }
   case ISD::VBIT_CONVERT: {





From lattner at cs.uiuc.edu  Fri Mar 31 12:25:26 2006
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Fri, 31 Mar 2006 12:25:26 -0600
Subject: [llvm-commits] 
	CVS: llvm/lib/Transforms/Scalar/InstructionCombining.cpp
Message-ID: <200603311825.MAA28981@zion.cs.uiuc.edu>



Changes in directory llvm/lib/Transforms/Scalar:

InstructionCombining.cpp updated: 1.454 -> 1.455
---
Log message:

extractelement(undef,x) -> undef


---
Diffs of the changes:  (+8 -6)

 InstructionCombining.cpp |   14 ++++++++------
 1 files changed, 8 insertions(+), 6 deletions(-)


Index: llvm/lib/Transforms/Scalar/InstructionCombining.cpp
diff -u llvm/lib/Transforms/Scalar/InstructionCombining.cpp:1.454 llvm/lib/Transforms/Scalar/InstructionCombining.cpp:1.455
--- llvm/lib/Transforms/Scalar/InstructionCombining.cpp:1.454	Thu Mar 30 16:02:40 2006
+++ llvm/lib/Transforms/Scalar/InstructionCombining.cpp	Fri Mar 31 12:25:14 2006
@@ -6655,12 +6655,14 @@
 }
 
 Instruction *InstCombiner::visitExtractElementInst(ExtractElementInst &EI) {
-  if (ConstantAggregateZero *C = 
-      dyn_cast<ConstantAggregateZero>(EI.getOperand(0))) {
-    // If packed val is constant 0, replace extract with scalar 0
-    const Type *Ty = cast<PackedType>(C->getType())->getElementType();
-    return ReplaceInstUsesWith(EI, Constant::getNullValue(Ty));
-  }
+  // If packed val is undef, replace extract with scalar undef.
+  if (isa<UndefValue>(EI.getOperand(0)))
+    return ReplaceInstUsesWith(EI, UndefValue::get(EI.getType()));
+
+  // If packed val is constant 0, replace extract with scalar 0.
+  if (isa<ConstantAggregateZero>(EI.getOperand(0)))
+    return ReplaceInstUsesWith(EI, Constant::getNullValue(EI.getType()));
+  
   if (ConstantPacked *C = dyn_cast<ConstantPacked>(EI.getOperand(0))) {
     // If packed val is constant with uniform operands, replace EI
     // with that operand





From lattner at cs.uiuc.edu  Fri Mar 31 12:31:52 2006
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Fri, 31 Mar 2006 12:31:52 -0600
Subject: [llvm-commits] CVS: llvm/lib/VMCore/ConstantFolding.cpp 
Message-ID: <200603311831.MAA29065@zion.cs.uiuc.edu>



Changes in directory llvm/lib/VMCore:

ConstantFolding.cpp updated: 1.83 -> 1.84
---
Log message:

constant fold extractelement with undef operands.


---
Diffs of the changes:  (+7 -1)

 ConstantFolding.cpp |    8 +++++++-
 1 files changed, 7 insertions(+), 1 deletion(-)


Index: llvm/lib/VMCore/ConstantFolding.cpp
diff -u llvm/lib/VMCore/ConstantFolding.cpp:1.83 llvm/lib/VMCore/ConstantFolding.cpp:1.84
--- llvm/lib/VMCore/ConstantFolding.cpp:1.83	Tue Jan 17 14:07:22 2006
+++ llvm/lib/VMCore/ConstantFolding.cpp	Fri Mar 31 12:31:40 2006
@@ -726,11 +726,17 @@
 
 Constant *llvm::ConstantFoldExtractElementInstruction(const Constant *Val,
                                                       const Constant *Idx) {
+  if (isa<UndefValue>(Val))  // ee(undef, x) -> undef
+    return UndefValue::get(cast<PackedType>(Val->getType())->getElementType());
+  
   if (const ConstantPacked *CVal = dyn_cast<ConstantPacked>(Val)) {
     if (const ConstantUInt *CIdx = dyn_cast<ConstantUInt>(Idx)) {
       return const_cast<Constant*>(CVal->getOperand(CIdx->getValue()));
+    } else if (isa<UndefValue>(Idx)) {
+      // ee({w,x,y,z}, undef) -> w (an arbitrary value).
+      return const_cast<Constant*>(CVal->getOperand(0));
     }
-  } 
+  }
   return 0;
 }
 





From lattner at cs.uiuc.edu  Fri Mar 31 13:00:34 2006
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Fri, 31 Mar 2006 13:00:34 -0600
Subject: [llvm-commits] CVS: llvm/lib/Target/PowerPC/README_ALTIVEC.txt 
Message-ID: <200603311900.NAA29222@zion.cs.uiuc.edu>



Changes in directory llvm/lib/Target/PowerPC:

README_ALTIVEC.txt updated: 1.8 -> 1.9
---
Log message:

add a note


---
Diffs of the changes:  (+2 -0)

 README_ALTIVEC.txt |    2 ++
 1 files changed, 2 insertions(+)


Index: llvm/lib/Target/PowerPC/README_ALTIVEC.txt
diff -u llvm/lib/Target/PowerPC/README_ALTIVEC.txt:1.8 llvm/lib/Target/PowerPC/README_ALTIVEC.txt:1.9
--- llvm/lib/Target/PowerPC/README_ALTIVEC.txt:1.8	Fri Mar 31 00:02:07 2006
+++ llvm/lib/Target/PowerPC/README_ALTIVEC.txt	Fri Mar 31 13:00:22 2006
@@ -135,3 +135,5 @@
 
 //===----------------------------------------------------------------------===//
 
+Handle VECTOR_SHUFFLE nodes with the appropriate shuffle mask with vsldoi,
+vpkuhum and vpkuwum.





From evan.cheng at apple.com  Fri Mar 31 13:21:27 2006
From: evan.cheng at apple.com (Evan Cheng)
Date: Fri, 31 Mar 2006 13:21:27 -0600
Subject: [llvm-commits] CVS: llvm/lib/Target/TargetSelectionDAG.td 
Message-ID: <200603311921.NAA29369@zion.cs.uiuc.edu>



Changes in directory llvm/lib/Target:

TargetSelectionDAG.td updated: 1.62 -> 1.63
---
Log message:

Add vector_extract and vector_insert nodes.


---
Diffs of the changes:  (+4 -0)

 TargetSelectionDAG.td |    4 ++++
 1 files changed, 4 insertions(+)


Index: llvm/lib/Target/TargetSelectionDAG.td
diff -u llvm/lib/Target/TargetSelectionDAG.td:1.62 llvm/lib/Target/TargetSelectionDAG.td:1.63
--- llvm/lib/Target/TargetSelectionDAG.td:1.62	Mon Mar 27 18:40:33 2006
+++ llvm/lib/Target/TargetSelectionDAG.td	Fri Mar 31 13:21:16 2006
@@ -310,6 +310,10 @@
 def build_vector : SDNode<"ISD::BUILD_VECTOR", SDTypeProfile<1, 0, []>, []>;
 def scalar_to_vector : SDNode<"ISD::SCALAR_TO_VECTOR", SDTypeProfile<1, 1, []>,
                               []>;
+def vector_extract : SDNode<"ISD::EXTRACT_VECTOR_ELT",
+    SDTypeProfile<1, 2, []>, []>;
+def vector_insert : SDNode<"ISD::INSERT_VECTOR_ELT",
+    SDTypeProfile<1, 3, []>, []>;
 
 // Nodes for intrinsics, you should use the intrinsic itself and let tblgen use
 // these internally.  Don't reference these directly.





From evan.cheng at apple.com  Fri Mar 31 13:23:05 2006
From: evan.cheng at apple.com (Evan Cheng)
Date: Fri, 31 Mar 2006 13:23:05 -0600
Subject: [llvm-commits] CVS: llvm/lib/Target/X86/X86ISelLowering.cpp
	X86ISelLowering.h X86InstrSSE.td 
Message-ID: <200603311923.NAA29389@zion.cs.uiuc.edu>



Changes in directory llvm/lib/Target/X86:

X86ISelLowering.cpp updated: 1.149 -> 1.150
X86ISelLowering.h updated: 1.48 -> 1.49
X86InstrSSE.td updated: 1.50 -> 1.51
---
Log message:

Add support to use pextrw and pinsrw to extract and insert a word element
from a 128-bit vector.


---
Diffs of the changes:  (+69 -4)

 X86ISelLowering.cpp |   38 ++++++++++++++++++++++++++++++++++++--
 X86ISelLowering.h   |    4 ++++
 X86InstrSSE.td      |   31 +++++++++++++++++++++++++++++--
 3 files changed, 69 insertions(+), 4 deletions(-)


Index: llvm/lib/Target/X86/X86ISelLowering.cpp
diff -u llvm/lib/Target/X86/X86ISelLowering.cpp:1.149 llvm/lib/Target/X86/X86ISelLowering.cpp:1.150
--- llvm/lib/Target/X86/X86ISelLowering.cpp:1.149	Thu Mar 30 19:30:39 2006
+++ llvm/lib/Target/X86/X86ISelLowering.cpp	Fri Mar 31 13:22:53 2006
@@ -255,9 +255,9 @@
     setOperationAction(ISD::SUB , (MVT::ValueType)VT, Expand);
     setOperationAction(ISD::MUL , (MVT::ValueType)VT, Expand);
     setOperationAction(ISD::LOAD, (MVT::ValueType)VT, Expand);
-    setOperationAction(ISD::VECTOR_SHUFFLE, (MVT::ValueType)VT, Expand);
+    setOperationAction(ISD::VECTOR_SHUFFLE,     (MVT::ValueType)VT, Expand);
     setOperationAction(ISD::EXTRACT_VECTOR_ELT, (MVT::ValueType)VT, Expand);
-    setOperationAction(ISD::INSERT_VECTOR_ELT, (MVT::ValueType)VT, Expand);
+    setOperationAction(ISD::INSERT_VECTOR_ELT,  (MVT::ValueType)VT, Expand);
   }
 
   if (Subtarget->hasMMX()) {
@@ -316,6 +316,8 @@
     setOperationAction(ISD::VECTOR_SHUFFLE,   MVT::v8i16, Custom);
     setOperationAction(ISD::VECTOR_SHUFFLE,   MVT::v4i32, Custom);
     setOperationAction(ISD::VECTOR_SHUFFLE,   MVT::v2i64, Custom);
+    setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8i16, Custom);
+    setOperationAction(ISD::INSERT_VECTOR_ELT,  MVT::v8i16, Custom);
   }
 
   computeRegisterProperties();
@@ -2657,6 +2659,37 @@
 
     return SDOperand();
   }
+  case ISD::EXTRACT_VECTOR_ELT: {
+    // Transform it so it match pextrw which produces a 32-bit result.
+    MVT::ValueType VT = Op.getValueType();
+    if (MVT::getSizeInBits(VT) == 16) {
+      MVT::ValueType EVT = (MVT::ValueType)(VT+1);
+      SDOperand Extract = DAG.getNode(X86ISD::PEXTRW, EVT,
+                                      Op.getOperand(0), Op.getOperand(1));
+      SDOperand Assert  = DAG.getNode(ISD::AssertZext, EVT, Extract,
+                                      DAG.getValueType(VT));
+      return DAG.getNode(ISD::TRUNCATE, VT, Assert);
+    }
+
+    return SDOperand();
+  }
+  case ISD::INSERT_VECTOR_ELT: {
+    // Transform it so it match pinsrw which expects a 16-bit value in a R32
+    // as its second argument.
+    MVT::ValueType VT = Op.getValueType();
+    MVT::ValueType BaseVT = MVT::getVectorBaseType(VT);
+    if (MVT::getSizeInBits(BaseVT) == 16) {
+      SDOperand N1 = Op.getOperand(1);
+      SDOperand N2 = Op.getOperand(2);
+      if (N1.getValueType() != MVT::i32)
+        N1 = DAG.getNode(ISD::ANY_EXTEND, MVT::i32, N1);
+      if (N2.getValueType() != MVT::i32)
+        N2 = DAG.getConstant(cast<ConstantSDNode>(N2)->getValue(), MVT::i32);
+      return DAG.getNode(ISD::INSERT_VECTOR_ELT, VT, Op.getOperand(0), N1, N2);
+    }
+
+    return SDOperand();
+  }
   }
 }
 
@@ -2692,6 +2725,7 @@
   case X86ISD::Wrapper:            return "X86ISD::Wrapper";
   case X86ISD::S2VEC:              return "X86ISD::S2VEC";
   case X86ISD::ZEXT_S2VEC:         return "X86ISD::ZEXT_S2VEC";
+  case X86ISD::PEXTRW:             return "X86ISD::PEXTRW";
   }
 }
 


Index: llvm/lib/Target/X86/X86ISelLowering.h
diff -u llvm/lib/Target/X86/X86ISelLowering.h:1.48 llvm/lib/Target/X86/X86ISelLowering.h:1.49
--- llvm/lib/Target/X86/X86ISelLowering.h:1.48	Wed Mar 29 17:07:14 2006
+++ llvm/lib/Target/X86/X86ISelLowering.h	Fri Mar 31 13:22:53 2006
@@ -153,6 +153,10 @@
       /// ZEXT_S2VEC - SCALAR_TO_VECTOR with zero extension. The destination base
       /// does not have to match the operand type.
       ZEXT_S2VEC,
+
+      /// PEXTRW - Extract a 16-bit value from a vector and zero extend it to
+      /// i32, corresponds to X86::PINSRW.
+      PEXTRW,
     };
 
     // X86 specific condition code. These correspond to X86_*_COND in


Index: llvm/lib/Target/X86/X86InstrSSE.td
diff -u llvm/lib/Target/X86/X86InstrSSE.td:1.50 llvm/lib/Target/X86/X86InstrSSE.td:1.51
--- llvm/lib/Target/X86/X86InstrSSE.td:1.50	Thu Mar 30 13:54:57 2006
+++ llvm/lib/Target/X86/X86InstrSSE.td	Fri Mar 31 13:22:53 2006
@@ -28,8 +28,8 @@
 def X86zexts2vec : SDNode<"X86ISD::ZEXT_S2VEC",
                           SDTypeProfile<1, 1, []>, []>;
 
-def SDTUnpckl : SDTypeProfile<1, 2,
-                              [SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>]>;
+def X86pextrw  : SDNode<"X86ISD::PEXTRW",
+                        SDTypeProfile<1, 2, []>, []>;
 
 //===----------------------------------------------------------------------===//
 // SSE pattern fragments
@@ -1409,6 +1409,33 @@
                                 UNPCKH_shuffle_mask)))]>;
 }
 
+// Extract / Insert
+def PEXTRWrr : PDIi8<0xC5, MRMSrcReg,
+                     (ops R32:$dst, VR128:$src1, i32i8imm:$src2),
+                     "pextrw {$src2, $src1, $dst|$dst, $src1, $src2}",
+                     [(set R32:$dst, (X86pextrw (v8i16 VR128:$src1),
+                                      (i32 imm:$src2)))]>;
+def PEXTRWrm : PDIi8<0xC5, MRMSrcMem,
+                     (ops R32:$dst, i128mem:$src1, i32i8imm:$src2),
+                     "pextrw {$src2, $src1, $dst|$dst, $src1, $src2}",
+                     [(set R32:$dst, (X86pextrw (loadv8i16 addr:$src1),
+                                      (i32 imm:$src2)))]>;
+
+let isTwoAddress = 1 in {
+def PINSRWrr : PDIi8<0xC4, MRMSrcReg,
+                     (ops VR128:$dst, VR128:$src1, R32:$src2, i32i8imm:$src3),
+                     "pinsrw {$src3, $src2, $dst|$dst, $src2, $src3}",
+                     [(set VR128:$dst, (v8i16 (vector_insert (v8i16 VR128:$src1),
+                               R32:$src2, (i32 imm:$src3))))]>;
+def PINSRWrm : PDIi8<0xC4, MRMSrcMem,
+                     (ops VR128:$dst, VR128:$src1, i16mem:$src2, i32i8imm:$src3),
+                     "pinsrw {$src3, $src2, $dst|$dst, $src2, $src3}",
+                     [(set VR128:$dst,
+                       (v8i16 (vector_insert (v8i16 VR128:$src1),
+                               (i32 (anyext (loadi16 addr:$src2))),
+                               (i32 imm:$src3))))]>;
+}
+
 //===----------------------------------------------------------------------===//
 // Miscellaneous Instructions
 //===----------------------------------------------------------------------===//





From lattner at cs.uiuc.edu  Fri Mar 31 13:49:10 2006
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Fri, 31 Mar 2006 13:49:10 -0600
Subject: [llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCISelLowering.cpp 
Message-ID: <200603311949.NAA29552@zion.cs.uiuc.edu>



Changes in directory llvm/lib/Target/PowerPC:

PPCISelLowering.cpp updated: 1.122 -> 1.123
---
Log message:

Add, sub and shuffle are legal for all vector types


---
Diffs of the changes:  (+9 -8)

 PPCISelLowering.cpp |   17 +++++++++--------
 1 files changed, 9 insertions(+), 8 deletions(-)


Index: llvm/lib/Target/PowerPC/PPCISelLowering.cpp
diff -u llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.122 llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.123
--- llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.122	Fri Mar 31 00:04:53 2006
+++ llvm/lib/Target/PowerPC/PPCISelLowering.cpp	Fri Mar 31 13:48:58 2006
@@ -171,12 +171,16 @@
   
   // First set operation action for all vector types to expand. Then we
   // will selectively turn on ones that can be effectively codegen'd.
-  for (unsigned VT = (unsigned)MVT::Vector + 1;
-       VT != (unsigned)MVT::LAST_VALUETYPE; VT++) {
-    setOperationAction(ISD::ADD , (MVT::ValueType)VT, Expand);
-    setOperationAction(ISD::SUB , (MVT::ValueType)VT, Expand);
+  for (unsigned VT = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
+       VT != (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++VT) {
+    // Add and sub are legal for all supported VT's.
+    setOperationAction(ISD::ADD , (MVT::ValueType)VT, Legal);
+    setOperationAction(ISD::SUB , (MVT::ValueType)VT, Legal);
+    setOperationAction(ISD::VECTOR_SHUFFLE, (MVT::ValueType)VT, Legal);
+    
     setOperationAction(ISD::MUL , (MVT::ValueType)VT, Expand);
-    setOperationAction(ISD::VECTOR_SHUFFLE, (MVT::ValueType)VT, Expand);
+    setOperationAction(ISD::DIV , (MVT::ValueType)VT, Expand);
+    setOperationAction(ISD::REM , (MVT::ValueType)VT, Expand);
     setOperationAction(ISD::EXTRACT_VECTOR_ELT, (MVT::ValueType)VT, Expand);
     setOperationAction(ISD::INSERT_VECTOR_ELT, (MVT::ValueType)VT, Expand);
     setOperationAction(ISD::BUILD_VECTOR, (MVT::ValueType)VT, Expand);
@@ -188,10 +192,7 @@
     addRegisterClass(MVT::v8i16, PPC::VRRCRegisterClass);
     addRegisterClass(MVT::v16i8, PPC::VRRCRegisterClass);
     
-    setOperationAction(ISD::ADD        , MVT::v4f32, Legal);
-    setOperationAction(ISD::SUB        , MVT::v4f32, Legal);
     setOperationAction(ISD::MUL        , MVT::v4f32, Legal);
-    setOperationAction(ISD::ADD        , MVT::v4i32, Legal);
 
     setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4i32, Custom);
     setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4f32, Custom);





From lattner at cs.uiuc.edu  Fri Mar 31 13:52:48 2006
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Fri, 31 Mar 2006 13:52:48 -0600
Subject: [llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCISelLowering.cpp 
Message-ID: <200603311952.NAA29627@zion.cs.uiuc.edu>



Changes in directory llvm/lib/Target/PowerPC:

PPCISelLowering.cpp updated: 1.123 -> 1.124
---
Log message:

Rearrange code a bit 


---
Diffs of the changes:  (+25 -21)

 PPCISelLowering.cpp |   46 +++++++++++++++++++++++++---------------------
 1 files changed, 25 insertions(+), 21 deletions(-)


Index: llvm/lib/Target/PowerPC/PPCISelLowering.cpp
diff -u llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.123 llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.124
--- llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.123	Fri Mar 31 13:48:58 2006
+++ llvm/lib/Target/PowerPC/PPCISelLowering.cpp	Fri Mar 31 13:52:36 2006
@@ -168,34 +168,38 @@
     setOperationAction(ISD::SRL, MVT::i64, Custom);
     setOperationAction(ISD::SRA, MVT::i64, Custom);
   }
-  
-  // First set operation action for all vector types to expand. Then we
-  // will selectively turn on ones that can be effectively codegen'd.
-  for (unsigned VT = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
-       VT != (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++VT) {
-    // Add and sub are legal for all supported VT's.
-    setOperationAction(ISD::ADD , (MVT::ValueType)VT, Legal);
-    setOperationAction(ISD::SUB , (MVT::ValueType)VT, Legal);
-    setOperationAction(ISD::VECTOR_SHUFFLE, (MVT::ValueType)VT, Legal);
-    
-    setOperationAction(ISD::MUL , (MVT::ValueType)VT, Expand);
-    setOperationAction(ISD::DIV , (MVT::ValueType)VT, Expand);
-    setOperationAction(ISD::REM , (MVT::ValueType)VT, Expand);
-    setOperationAction(ISD::EXTRACT_VECTOR_ELT, (MVT::ValueType)VT, Expand);
-    setOperationAction(ISD::INSERT_VECTOR_ELT, (MVT::ValueType)VT, Expand);
-    setOperationAction(ISD::BUILD_VECTOR, (MVT::ValueType)VT, Expand);
-  }
 
   if (TM.getSubtarget<PPCSubtarget>().hasAltivec()) {
+    // First set operation action for all vector types to expand. Then we
+    // will selectively turn on ones that can be effectively codegen'd.
+    for (unsigned VT = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
+         VT != (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++VT) {
+      // add/sub/and/or/xor are legal for all supported vector VT's.
+      setOperationAction(ISD::ADD , (MVT::ValueType)VT, Legal);
+      setOperationAction(ISD::SUB , (MVT::ValueType)VT, Legal);
+      setOperationAction(ISD::AND , (MVT::ValueType)VT, Legal);
+      setOperationAction(ISD::OR  , (MVT::ValueType)VT, Legal);
+      setOperationAction(ISD::XOR , (MVT::ValueType)VT, Legal);
+      
+      // We can custom expand all VECTOR_SHUFFLEs to VPERM.
+      setOperationAction(ISD::VECTOR_SHUFFLE, (MVT::ValueType)VT, Custom);
+      
+      setOperationAction(ISD::MUL , (MVT::ValueType)VT, Expand);
+      setOperationAction(ISD::SDIV, (MVT::ValueType)VT, Expand);
+      setOperationAction(ISD::SREM, (MVT::ValueType)VT, Expand);
+      setOperationAction(ISD::UDIV, (MVT::ValueType)VT, Expand);
+      setOperationAction(ISD::UREM, (MVT::ValueType)VT, Expand);
+      setOperationAction(ISD::EXTRACT_VECTOR_ELT, (MVT::ValueType)VT, Expand);
+      setOperationAction(ISD::INSERT_VECTOR_ELT, (MVT::ValueType)VT, Expand);
+      setOperationAction(ISD::BUILD_VECTOR, (MVT::ValueType)VT, Expand);
+    }
+
     addRegisterClass(MVT::v4f32, PPC::VRRCRegisterClass);
     addRegisterClass(MVT::v4i32, PPC::VRRCRegisterClass);
     addRegisterClass(MVT::v8i16, PPC::VRRCRegisterClass);
     addRegisterClass(MVT::v16i8, PPC::VRRCRegisterClass);
     
-    setOperationAction(ISD::MUL        , MVT::v4f32, Legal);
-
-    setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4i32, Custom);
-    setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4f32, Custom);
+    setOperationAction(ISD::MUL, MVT::v4f32, Legal);
 
     setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4f32, Custom);
     setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i32, Custom);





From lattner at cs.uiuc.edu  Fri Mar 31 14:00:47 2006
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Fri, 31 Mar 2006 14:00:47 -0600
Subject: [llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCInstrAltivec.td 
Message-ID: <200603312000.OAA29739@zion.cs.uiuc.edu>



Changes in directory llvm/lib/Target/PowerPC:

PPCInstrAltivec.td updated: 1.24 -> 1.25
---
Log message:

Add vperm support for all datatypes


---
Diffs of the changes:  (+13 -19)

 PPCInstrAltivec.td |   32 +++++++++++++-------------------
 1 files changed, 13 insertions(+), 19 deletions(-)


Index: llvm/lib/Target/PowerPC/PPCInstrAltivec.td
diff -u llvm/lib/Target/PowerPC/PPCInstrAltivec.td:1.24 llvm/lib/Target/PowerPC/PPCInstrAltivec.td:1.25
--- llvm/lib/Target/PowerPC/PPCInstrAltivec.td:1.24	Thu Mar 30 23:38:32 2006
+++ llvm/lib/Target/PowerPC/PPCInstrAltivec.td	Fri Mar 31 14:00:35 2006
@@ -141,27 +141,18 @@
                        [(set VRRC:$vD, (fneg (fsub (fmul VRRC:$vA, VRRC:$vC),
                                                    VRRC:$vB)))]>,
                        Requires<[FPContractions]>;
-def VMHADDSHS  : VAForm_1a<32, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB, VRRC:$vC),
-                  "vmhaddshs $vD, $vA, $vB, $vC", VecFP,
-                  [(set VRRC:$vD,
-                   (int_ppc_altivec_vmhaddshs VRRC:$vA, VRRC:$vB, VRRC:$vC))]>;
-def VMHRADDSHS : VAForm_1a<33, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB, VRRC:$vC),
-                  "vmhraddshs $vD, $vA, $vB, $vC", VecFP,
-                  [(set VRRC:$vD,
-                   (int_ppc_altivec_vmhraddshs VRRC:$vA, VRRC:$vB, VRRC:$vC))]>;
-def VPERM   : VAForm_1a<43, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB, VRRC:$vC),
-                        "vperm $vD, $vA, $vB, $vC", VecPerm,
-                        [(set VRRC:$vD,
-                             (PPCvperm (v4f32 VRRC:$vA), VRRC:$vB, VRRC:$vC))]>;
+def VMHADDSHS  : VA1a_Int<32, "vmhaddshs $vD, $vA, $vB, $vC",
+                          int_ppc_altivec_vmhaddshs>;
+def VMHRADDSHS : VA1a_Int<33, "vmhraddshs $vD, $vA, $vB, $vC", 
+                          int_ppc_altivec_vmhraddshs>;
+def VPERM   : VA1a_Int<43, "vperm $vD, $vA, $vB, $vC", int_ppc_altivec_vperm>;
+def VPERM   : VA1a_Int<42, "vsel $vD, $vA, $vB, $vC",  int_ppc_altivec_vsel>;
+
 def VSLDOI  : VAForm_2<44, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB, u5imm:$SH),
                        "vsldoi $vD, $vA, $vB, $SH", VecFP,
                        [(set VRRC:$vD,
                              (int_ppc_altivec_vsldoi VRRC:$vA, VRRC:$vB,
                                                      imm:$SH))]>;
-def VSEL   : VAForm_1a<42, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB, VRRC:$vC),
-                       "vsel $vD, $vA, $vB, $vC", VecFP,
-                       [(set VRRC:$vD,
-                         (int_ppc_altivec_vsel VRRC:$vA, VRRC:$vB, VRRC:$vC))]>;
 
 // VX-Form instructions.  AltiVec arithmetic ops.
 def VADDCUW : VXForm_1<384, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
@@ -537,11 +528,14 @@
           (VMADDFP VRRC:$A, VRRC:$B, VRRC:$C)>;
 def : Pat<(int_ppc_altivec_vnmsubfp VRRC:$A, VRRC:$B, VRRC:$C),
           (VNMSUBFP VRRC:$A, VRRC:$B, VRRC:$C)>;
-def : Pat<(int_ppc_altivec_vperm VRRC:$A, VRRC:$B, VRRC:$C),
-          (VPERM VRRC:$A, VRRC:$B, VRRC:$C)>;
 def : Pat<(vector_shuffle (v4i32 VRRC:$vB), (undef), VSPLT_shuffle_mask:$UIMM),
           (v4i32 (VSPLTW VSPLT_shuffle_mask:$UIMM, VRRC:$vB))>;
 
 def : Pat<(PPCvperm (v4i32 VRRC:$vA), VRRC:$vB, VRRC:$vC),
           (v4i32 (VPERM VRRC:$vA, VRRC:$vB, VRRC:$vC))>;
-
+def : Pat<(PPCvperm (v4f32 VRRC:$vA), VRRC:$vB, VRRC:$vC),
+          (v4f32 (VPERM VRRC:$vA, VRRC:$vB, VRRC:$vC))>;
+def : Pat<(PPCvperm (v8i16 VRRC:$vA), VRRC:$vB, VRRC:$vC),
+          (v8i16 (VPERM VRRC:$vA, VRRC:$vB, VRRC:$vC))>;
+def : Pat<(PPCvperm (v16i8 VRRC:$vA), VRRC:$vB, VRRC:$vC),
+          (v16i8 (VPERM VRRC:$vA, VRRC:$vB, VRRC:$vC))>;





From lattner at cs.uiuc.edu  Fri Mar 31 15:19:18 2006
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Fri, 31 Mar 2006 15:19:18 -0600
Subject: [llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCInstrAltivec.td 
Message-ID: <200603312119.PAA30190@zion.cs.uiuc.edu>



Changes in directory llvm/lib/Target/PowerPC:

PPCInstrAltivec.td updated: 1.25 -> 1.26
---
Log message:

fix a pasto


---
Diffs of the changes:  (+1 -1)

 PPCInstrAltivec.td |    2 +-
 1 files changed, 1 insertion(+), 1 deletion(-)


Index: llvm/lib/Target/PowerPC/PPCInstrAltivec.td
diff -u llvm/lib/Target/PowerPC/PPCInstrAltivec.td:1.25 llvm/lib/Target/PowerPC/PPCInstrAltivec.td:1.26
--- llvm/lib/Target/PowerPC/PPCInstrAltivec.td:1.25	Fri Mar 31 14:00:35 2006
+++ llvm/lib/Target/PowerPC/PPCInstrAltivec.td	Fri Mar 31 15:19:06 2006
@@ -146,7 +146,7 @@
 def VMHRADDSHS : VA1a_Int<33, "vmhraddshs $vD, $vA, $vB, $vC", 
                           int_ppc_altivec_vmhraddshs>;
 def VPERM   : VA1a_Int<43, "vperm $vD, $vA, $vB, $vC", int_ppc_altivec_vperm>;
-def VPERM   : VA1a_Int<42, "vsel $vD, $vA, $vB, $vC",  int_ppc_altivec_vsel>;
+def VSEL    : VA1a_Int<42, "vsel $vD, $vA, $vB, $vC",  int_ppc_altivec_vsel>;
 
 def VSLDOI  : VAForm_2<44, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB, u5imm:$SH),
                        "vsldoi $vD, $vA, $vB, $SH", VecFP,





From evan.cheng at apple.com  Fri Mar 31 15:28:59 2006
From: evan.cheng at apple.com (Evan Cheng)
Date: Fri, 31 Mar 2006 15:28:59 -0600
Subject: [llvm-commits] CVS: llvm/include/llvm/IntrinsicsX86.td 
Message-ID: <200603312128.PAA30242@zion.cs.uiuc.edu>



Changes in directory llvm/include/llvm:

IntrinsicsX86.td updated: 1.7 -> 1.8
---
Log message:

Added haddp{s|d} and hsubp{s|d} intrinsics.


---
Diffs of the changes:  (+19 -0)

 IntrinsicsX86.td |   19 +++++++++++++++++++
 1 files changed, 19 insertions(+)


Index: llvm/include/llvm/IntrinsicsX86.td
diff -u llvm/include/llvm/IntrinsicsX86.td:1.7 llvm/include/llvm/IntrinsicsX86.td:1.8
--- llvm/include/llvm/IntrinsicsX86.td:1.7	Thu Mar 30 00:21:22 2006
+++ llvm/include/llvm/IntrinsicsX86.td	Fri Mar 31 15:28:46 2006
@@ -199,3 +199,22 @@
   def int_x86_sse2_pmovmskb_128 : GCCBuiltin<"__builtin_ia32_pmovmskb128">,
               Intrinsic<[llvm_int_ty, llvm_v16i8_ty], [InstrNoMem]>;
 }
+
+//===----------------------------------------------------------------------===//
+// SSE3
+
+// Horizontal ops.
+let TargetPrefix = "x86" in {  // All intrinsics start with "llvm.x86.".
+  def int_x86_sse3_hadd_ps : GCCBuiltin<"__builtin_ia32_haddps">,
+              Intrinsic<[llvm_v4f32_ty, llvm_v4f32_ty,
+                         llvm_v4f32_ty], [InstrNoMem]>;
+  def int_x86_sse3_hadd_pd : GCCBuiltin<"__builtin_ia32_haddpd">,
+              Intrinsic<[llvm_v2f64_ty, llvm_v2f64_ty,
+                         llvm_v2f64_ty], [InstrNoMem]>;
+  def int_x86_sse3_hsub_ps : GCCBuiltin<"__builtin_ia32_hsubps">,
+              Intrinsic<[llvm_v4f32_ty, llvm_v4f32_ty,
+                         llvm_v4f32_ty], [InstrNoMem]>;
+  def int_x86_sse3_hsub_pd : GCCBuiltin<"__builtin_ia32_hsubpd">,
+              Intrinsic<[llvm_v2f64_ty, llvm_v2f64_ty,
+                         llvm_v2f64_ty], [InstrNoMem]>;
+}





From evan.cheng at apple.com  Fri Mar 31 15:29:46 2006
From: evan.cheng at apple.com (Evan Cheng)
Date: Fri, 31 Mar 2006 15:29:46 -0600
Subject: [llvm-commits] CVS: llvm/lib/Target/X86/X86InstrSSE.td 
Message-ID: <200603312129.PAA30258@zion.cs.uiuc.edu>



Changes in directory llvm/lib/Target/X86:

X86InstrSSE.td updated: 1.51 -> 1.52
---
Log message:

Added support for SSE3 horizontal ops: haddp{s|d} and hsub{s|d}.


---
Diffs of the changes:  (+43 -0)

 X86InstrSSE.td |   43 +++++++++++++++++++++++++++++++++++++++++++
 1 files changed, 43 insertions(+)


Index: llvm/lib/Target/X86/X86InstrSSE.td
diff -u llvm/lib/Target/X86/X86InstrSSE.td:1.51 llvm/lib/Target/X86/X86InstrSSE.td:1.52
--- llvm/lib/Target/X86/X86InstrSSE.td:1.51	Fri Mar 31 13:22:53 2006
+++ llvm/lib/Target/X86/X86InstrSSE.td	Fri Mar 31 15:29:33 2006
@@ -145,6 +145,8 @@
 // PDI - SSE2 instructions with TB and OpSize prefixes.
 // PSIi8 - SSE1 instructions with ImmT == Imm8 and TB prefix.
 // PDIi8 - SSE2 instructions with ImmT == Imm8 and TB and OpSize prefixes.
+// S3SI - SSE3 instructions with XD prefix.
+// S3DI - SSE3 instructions with TB and OpSize prefixes.
 class SSI<bits<8> o, Format F, dag ops, string asm, list<dag> pattern>
       : I<o, F, ops, asm, pattern>, XS, Requires<[HasSSE1]>;
 class SDI<bits<8> o, Format F, dag ops, string asm, list<dag> pattern>
@@ -161,6 +163,27 @@
       : X86Inst<o, F, Imm8, ops, asm>, TB, OpSize, Requires<[HasSSE2]> {
   let Pattern = pattern;
 }
+class S3SI<bits<8> o, Format F, dag ops, string asm, list<dag> pattern>
+      : I<o, F, ops, asm, pattern>, XD, Requires<[HasSSE3]>;
+class S3DI<bits<8> o, Format F, dag ops, string asm, list<dag> pattern>
+      : I<o, F, ops, asm, pattern>, TB, OpSize, Requires<[HasSSE3]>;
+
+//===----------------------------------------------------------------------===//
+// Helpers for defining instructions that directly correspond to intrinsics.
+class S3S_Intrr<bits<8> o, string asm, Intrinsic IntId>
+  : S3SI<o, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2), asm,
+         [(set VR128:$dst, (v4f32 (IntId VR128:$src1, VR128:$src2)))]>;
+class S3S_Intrm<bits<8> o, string asm, Intrinsic IntId>
+  : S3SI<o, MRMSrcMem, (ops VR128:$dst, VR128:$src1, f128mem:$src2), asm,
+         [(set VR128:$dst, (v4f32 (IntId VR128:$src1,
+                                   (loadv4f32 addr:$src2))))]>;
+class S3D_Intrr<bits<8> o, string asm, Intrinsic IntId>
+  : S3DI<o, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2), asm,
+         [(set VR128:$dst, (v2f64 (IntId VR128:$src1, VR128:$src2)))]>;
+class S3D_Intrm<bits<8> o, string asm, Intrinsic IntId>
+  : S3DI<o, MRMSrcMem, (ops VR128:$dst, VR128:$src1, f128mem:$src2), asm,
+         [(set VR128:$dst, (v2f64 (IntId VR128:$src1,
+                                   (loadv2f64 addr:$src2))))]>;
 
 // Some 'special' instructions
 def IMPLICIT_DEF_FR32 : I<0, Pseudo, (ops FR32:$dst),
@@ -1073,6 +1096,26 @@
                                               UNPCKL_shuffle_mask)))]>;
 }
 
+// Horizontal ops
+let isTwoAddress = 1 in {
+def HADDPSrr : S3S_Intrr<0x7C, "haddps {$src2, $dst|$dst, $src2}",
+                          int_x86_sse3_hadd_ps>;
+def HADDPSrm : S3S_Intrm<0x7C, "haddps {$src2, $dst|$dst, $src2}",
+                          int_x86_sse3_hadd_ps>;
+def HADDPDrr : S3D_Intrr<0x7C, "haddpd {$src2, $dst|$dst, $src2}",
+                          int_x86_sse3_hadd_pd>;
+def HADDPDrm : S3D_Intrm<0x7C, "haddpd {$src2, $dst|$dst, $src2}",
+                          int_x86_sse3_hadd_pd>;
+def HSUBPSrr : S3S_Intrr<0x7C, "hsubps {$src2, $dst|$dst, $src2}",
+                          int_x86_sse3_hsub_ps>;
+def HSUBPSrm : S3S_Intrm<0x7C, "hsubps {$src2, $dst|$dst, $src2}",
+                          int_x86_sse3_hsub_ps>;
+def HSUBPDrr : S3D_Intrr<0x7C, "hsubpd {$src2, $dst|$dst, $src2}",
+                          int_x86_sse3_hsub_pd>;
+def HSUBPDrm : S3D_Intrm<0x7C, "hsubpd {$src2, $dst|$dst, $src2}",
+                          int_x86_sse3_hsub_pd>;
+}
+
 //===----------------------------------------------------------------------===//
 // SSE integer instructions
 //===----------------------------------------------------------------------===//





From lattner at cs.uiuc.edu  Fri Mar 31 15:53:13 2006
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Fri, 31 Mar 2006 15:53:13 -0600
Subject: [llvm-commits] CVS: llvm/test/Regression/TableGen/strconcat.td 
Message-ID: <200603312153.PAA30745@zion.cs.uiuc.edu>



Changes in directory llvm/test/Regression/TableGen:

strconcat.td added (r1.1)
---
Log message:

new testcase


---
Diffs of the changes:  (+7 -0)

 strconcat.td |    7 +++++++
 1 files changed, 7 insertions(+)


Index: llvm/test/Regression/TableGen/strconcat.td
diff -c /dev/null llvm/test/Regression/TableGen/strconcat.td:1.1
*** /dev/null	Fri Mar 31 15:53:11 2006
--- llvm/test/Regression/TableGen/strconcat.td	Fri Mar 31 15:53:01 2006
***************
*** 0 ****
--- 1,7 ----
+ // RUN: tblgen %s | grep fufoo
+ 
+ class Y<string S> {
+   string T = !strconcat(S, "foo");
+ }
+ 
+ def Z : Y<"fu">;





From lattner at cs.uiuc.edu  Fri Mar 31 15:54:01 2006
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Fri, 31 Mar 2006 15:54:01 -0600
Subject: [llvm-commits] CVS: llvm/utils/TableGen/FileLexer.l FileParser.y
	Record.cpp Record.h 
Message-ID: <200603312154.PAA31054@zion.cs.uiuc.edu>



Changes in directory llvm/utils/TableGen:

FileLexer.l updated: 1.28 -> 1.29
FileParser.y updated: 1.41 -> 1.42
Record.cpp updated: 1.52 -> 1.53
Record.h updated: 1.56 -> 1.57
---
Log message:

Generalize the previous binary operator support and add a string concatenation
operation.  This implements Regression/TableGen/strconcat.td.


---
Diffs of the changes:  (+109 -38)

 FileLexer.l  |    1 
 FileParser.y |   22 ++++-----------
 Record.cpp   |   84 ++++++++++++++++++++++++++++++++++++++++++++++++-----------
 Record.h     |   40 +++++++++++++++++++++++-----
 4 files changed, 109 insertions(+), 38 deletions(-)


Index: llvm/utils/TableGen/FileLexer.l
diff -u llvm/utils/TableGen/FileLexer.l:1.28 llvm/utils/TableGen/FileLexer.l:1.29
--- llvm/utils/TableGen/FileLexer.l:1.28	Fri Mar  3 13:34:28 2006
+++ llvm/utils/TableGen/FileLexer.l	Fri Mar 31 15:53:49 2006
@@ -202,6 +202,7 @@
 !sra           { return SRATOK; }
 !srl           { return SRLTOK; }
 !shl           { return SHLTOK; }
+!strconcat     { return STRCONCATTOK; }
 
 
 {Identifier}   { Filelval.StrVal = new std::string(yytext, yytext+yyleng);


Index: llvm/utils/TableGen/FileParser.y
diff -u llvm/utils/TableGen/FileParser.y:1.41 llvm/utils/TableGen/FileParser.y:1.42
--- llvm/utils/TableGen/FileParser.y:1.41	Thu Mar 30 16:50:40 2006
+++ llvm/utils/TableGen/FileParser.y	Fri Mar 31 15:53:49 2006
@@ -200,7 +200,7 @@
 };
 
 %token INT BIT STRING BITS LIST CODE DAG CLASS DEF FIELD LET IN
-%token SHLTOK SRATOK SRLTOK
+%token SHLTOK SRATOK SRLTOK STRCONCATTOK
 %token <IntVal>      INTVAL
 %token <StrVal>      ID VARNAME STRVAL CODEFRAGMENT
 
@@ -352,23 +352,13 @@
     }
     delete $3;
   } | SHLTOK '(' Value ',' Value ')' {
-    $$ = $3->getBinaryOp(Init::SHL, $5);
-    if ($$ == 0) {
-      err() << "Cannot shift values '" << *$3 << "' and '" << *$5 << "'!\n";
-      exit(1);
-    }
+    $$ = (new BinOpInit(BinOpInit::SHL, $3, $5))->Fold();
   } | SRATOK '(' Value ',' Value ')' {
-    $$ = $3->getBinaryOp(Init::SRA, $5);
-    if ($$ == 0) {
-      err() << "Cannot shift values '" << *$3 << "' and '" << *$5 << "'!\n";
-      exit(1);
-    }
+    $$ = (new BinOpInit(BinOpInit::SRA, $3, $5))->Fold();
   } | SRLTOK '(' Value ',' Value ')' {
-    $$ = $3->getBinaryOp(Init::SRL, $5);
-    if ($$ == 0) {
-      err() << "Cannot shift values '" << *$3 << "' and '" << *$5 << "'!\n";
-      exit(1);
-    }
+    $$ = (new BinOpInit(BinOpInit::SRL, $3, $5))->Fold();
+  } | STRCONCATTOK '(' Value ',' Value ')' {
+    $$ = (new BinOpInit(BinOpInit::STRCONCAT, $3, $5))->Fold();
   };
 
 OptVarName : /* empty */ {


Index: llvm/utils/TableGen/Record.cpp
diff -u llvm/utils/TableGen/Record.cpp:1.52 llvm/utils/TableGen/Record.cpp:1.53
--- llvm/utils/TableGen/Record.cpp:1.52	Thu Mar 30 16:50:40 2006
+++ llvm/utils/TableGen/Record.cpp	Fri Mar 31 15:53:49 2006
@@ -7,6 +7,7 @@
 //
 //===----------------------------------------------------------------------===//
 //
+// Implement the tablegen record classes.
 //
 //===----------------------------------------------------------------------===//
 
@@ -125,6 +126,19 @@
   return 0;
 }
 
+Init *StringRecTy::convertValue(BinOpInit *BO) {
+  if (BO->getOpcode() == BinOpInit::STRCONCAT) {
+    Init *L = BO->getLHS()->convertInitializerTo(this);
+    Init *R = BO->getRHS()->convertInitializerTo(this);
+    if (L == 0 || R == 0) return 0;
+    if (L != BO->getLHS() || R != BO->getRHS())
+      return new BinOpInit(BinOpInit::STRCONCAT, L, R);
+    return BO;
+  }
+  return 0;
+}
+
+
 Init *StringRecTy::convertValue(TypedInit *TI) {
   if (dynamic_cast<StringRecTy*>(TI->getType()))
     return TI;  // Accept variable if already of the right type!
@@ -299,21 +313,6 @@
   return this;
 }
 
-Init *IntInit::getBinaryOp(BinaryOp Op, Init *RHS) {
-  IntInit *RHSi = dynamic_cast<IntInit*>(RHS);
-  if (RHSi == 0) return 0;
-
-  int NewValue;
-  switch (Op) {
-  default: assert(0 && "Unknown binop");
-  case SHL: NewValue = Value << RHSi->getValue(); break;
-  case SRA: NewValue = Value >> RHSi->getValue(); break;
-  case SRL: NewValue = (unsigned)Value >> (unsigned)RHSi->getValue(); break;
-  }
-  return new IntInit(NewValue);
-}
-
-
 Init *IntInit::convertInitializerBitRange(const std::vector<unsigned> &Bits) {
   BitsInit *BI = new BitsInit(Bits.size());
 
@@ -368,6 +367,61 @@
   OS << "]";
 }
 
+Init *BinOpInit::Fold() {
+  switch (getOpcode()) {
+  default: assert(0 && "Unknown binop");
+  case STRCONCAT: {
+    StringInit *LHSs = dynamic_cast<StringInit*>(LHS);
+    StringInit *RHSs = dynamic_cast<StringInit*>(RHS);
+    if (LHSs && RHSs)
+      return new StringInit(LHSs->getValue() + RHSs->getValue());
+    break;
+  }
+  case SHL:
+  case SRA:
+  case SRL: {
+    IntInit *LHSi = dynamic_cast<IntInit*>(LHS);
+    IntInit *RHSi = dynamic_cast<IntInit*>(RHS);
+    if (LHSi && RHSi) {
+      int LHSv = LHSi->getValue(), RHSv = RHSi->getValue();
+      int Result;
+      switch (getOpcode()) {
+      default: assert(0 && "Bad opcode!");
+      case SHL: Result = LHSv << RHSv; break;
+      case SRA: Result = LHSv >> RHSv; break;
+      case SRL: Result = (unsigned)LHSv >> (unsigned)RHSv; break;
+      }
+      return new IntInit(Result);
+    }
+    break;
+  }
+  }
+  return this;
+}
+
+Init *BinOpInit::resolveReferences(Record &R, const RecordVal *RV) {
+  Init *lhs = LHS->resolveReferences(R, RV);
+  Init *rhs = RHS->resolveReferences(R, RV);
+  
+  if (LHS != lhs || RHS != rhs)
+    return (new BinOpInit(getOpcode(), lhs, rhs))->Fold();
+  return Fold();
+}
+
+void BinOpInit::print(std::ostream &OS) const {
+  switch (Opc) {
+  case SHL: OS << "!shl"; break;
+  case SRA: OS << "!sra"; break;
+  case SRL: OS << "!srl"; break;
+  case STRCONCAT: OS << "!strconcat"; break;
+  }
+  OS << "(";
+  LHS->print(OS);
+  OS << ", ";
+  RHS->print(OS);
+  OS << ")";
+}
+
 Init *TypedInit::convertInitializerBitRange(const std::vector<unsigned> &Bits) {
   BitsRecTy *T = dynamic_cast<BitsRecTy*>(getType());
   if (T == 0) return 0;  // Cannot subscript a non-bits variable...


Index: llvm/utils/TableGen/Record.h
diff -u llvm/utils/TableGen/Record.h:1.56 llvm/utils/TableGen/Record.h:1.57
--- llvm/utils/TableGen/Record.h:1.56	Thu Mar 30 16:50:40 2006
+++ llvm/utils/TableGen/Record.h	Fri Mar 31 15:53:49 2006
@@ -42,6 +42,7 @@
 class StringInit;
 class CodeInit;
 class ListInit;
+class BinOpInit;
 class DefInit;
 class DagInit;
 class TypedInit;
@@ -75,6 +76,7 @@
   virtual Init *convertValue(   IntInit *II) { return 0; }
   virtual Init *convertValue(StringInit *SI) { return 0; }
   virtual Init *convertValue(  ListInit *LI) { return 0; }
+  virtual Init *convertValue( BinOpInit *UI) { return 0; }
   virtual Init *convertValue(  CodeInit *CI) { return 0; }
   virtual Init *convertValue(VarBitInit *VB) { return 0; }
   virtual Init *convertValue(   DefInit *DI) { return 0; }
@@ -231,6 +233,7 @@
   virtual Init *convertValue(   IntInit *II) { return 0; }
   virtual Init *convertValue(StringInit *SI) { return (Init*)SI; }
   virtual Init *convertValue(  ListInit *LI) { return 0; }
+  virtual Init *convertValue( BinOpInit *BO);
   virtual Init *convertValue(  CodeInit *CI) { return 0; }
   virtual Init *convertValue(VarBitInit *VB) { return 0; }
   virtual Init *convertValue(   DefInit *DI) { return 0; }
@@ -465,11 +468,6 @@
     return 0;
   }
 
-  enum BinaryOp { SHL, SRA, SRL };
-  virtual Init *getBinaryOp(BinaryOp Op, Init *RHS) {
-    return 0;
-  }
-
   /// resolveReferences - This method is used by classes that refer to other
   /// variables which may not be defined at the time they expression is formed.
   /// If a value is set for the variable later, this method will be called on
@@ -570,8 +568,6 @@
   }
   virtual Init *convertInitializerBitRange(const std::vector<unsigned> &Bits);
 
-  virtual Init *getBinaryOp(BinaryOp Op, Init *RHS);
-
   virtual void print(std::ostream &OS) const { OS << Value; }
 };
 
@@ -639,6 +635,36 @@
   virtual void print(std::ostream &OS) const;
 };
 
+/// BinOpInit - !op (X, Y) - Combine two inits.
+///
+class BinOpInit : public Init {
+public:
+  enum BinaryOp { SHL, SRA, SRL, STRCONCAT };
+private:
+  BinaryOp Opc;
+  Init *LHS, *RHS;
+public:
+  BinOpInit(BinaryOp opc, Init *lhs, Init *rhs) : Opc(opc), LHS(lhs), RHS(rhs) {
+  }
+  
+  BinaryOp getOpcode() const { return Opc; }
+  Init *getLHS() const { return LHS; }
+  Init *getRHS() const { return RHS; }
+
+  // Fold - If possible, fold this to a simpler init.  Return this if not
+  // possible to fold.
+  Init *Fold();
+
+  virtual Init *convertInitializerTo(RecTy *Ty) {
+    return Ty->convertValue(this);
+  }
+  
+  virtual Init *resolveReferences(Record &R, const RecordVal *RV);
+  
+  virtual void print(std::ostream &OS) const;
+};
+
+
 
 /// TypedInit - This is the common super-class of types that have a specific,
 /// explicit, type.





From lattner at cs.uiuc.edu  Fri Mar 31 15:54:23 2006
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Fri, 31 Mar 2006 15:54:23 -0600
Subject: [llvm-commits] CVS: llvm/utils/TableGen/FileLexer.cpp.cvs
	FileLexer.l.cvs FileParser.cpp.cvs FileParser.h.cvs
	FileParser.y.cvs 
Message-ID: <200603312154.PAA31100@zion.cs.uiuc.edu>



Changes in directory llvm/utils/TableGen:

FileLexer.cpp.cvs updated: 1.4 -> 1.5
FileLexer.l.cvs updated: 1.3 -> 1.4
FileParser.cpp.cvs updated: 1.2 -> 1.3
FileParser.h.cvs updated: 1.2 -> 1.3
FileParser.y.cvs updated: 1.2 -> 1.3
---
Log message:

regenerate


---
Diffs of the changes:  (+418 -420)

 FileLexer.cpp.cvs  |  260 +++++++++++++------------
 FileLexer.l.cvs    |    1 
 FileParser.cpp.cvs |  533 ++++++++++++++++++++++++++---------------------------
 FileParser.h.cvs   |   11 -
 FileParser.y.cvs   |   22 --
 5 files changed, 418 insertions(+), 409 deletions(-)


Index: llvm/utils/TableGen/FileLexer.cpp.cvs
diff -u llvm/utils/TableGen/FileLexer.cpp.cvs:1.4 llvm/utils/TableGen/FileLexer.cpp.cvs:1.5
--- llvm/utils/TableGen/FileLexer.cpp.cvs:1.4	Fri Mar  3 13:34:28 2006
+++ llvm/utils/TableGen/FileLexer.cpp.cvs	Fri Mar 31 15:54:11 2006
@@ -21,7 +21,7 @@
 /* A lexical scanner generated by flex */
 
 /* Scanner skeleton version:
- * $Header: /var/cvs/llvm/llvm/utils/TableGen/FileLexer.cpp.cvs,v 1.4 2006/03/03 19:34:28 lattner Exp $
+ * $Header: /var/cvs/llvm/llvm/utils/TableGen/FileLexer.cpp.cvs,v 1.5 2006/03/31 21:54:11 lattner Exp $
  */
 
 #define FLEX_SCANNER
@@ -306,39 +306,40 @@
 	*yy_cp = '\0'; \
 	yy_c_buf_p = yy_cp;
 
-#define YY_NUM_RULES 31
-#define YY_END_OF_BUFFER 32
-static yyconst short int yy_acclist[129] =
+#define YY_NUM_RULES 32
+#define YY_END_OF_BUFFER 33
+static yyconst short int yy_acclist[130] =
     {   0,
-       25,   25,   32,   30,   31,   23,   30,   31,   23,   31,
-       30,   31,   30,   31,   30,   31,   30,   31,   30,   31,
-       22,   30,   31,   22,   30,   31,   19,   30,   31,   30,
-       31,   19,   30,   31,   19,   30,   31,   19,   30,   31,
-       19,   30,   31,   19,   30,   31,   19,   30,   31,   19,
-       30,   31,   25,   31,   26,   31,   28,   31,   23,   21,
-       20,   22,   24,    1,   19,   19,   19,   19,   19,   19,
-       19,   15,   19,   19,   19,   19,   25,   26,   26,   29,
-       28,   27,   28,   20,    1,   22,   22,    5,   19,   19,
-       19,   10,   19,   12,   19,   19,   19,    4,   19,   14,
-
-       19,   19,   19,   18,   16,   17,    3,    6,   19,   19,
-        9,   19,   19,   19,    8,   19,   19,   11,   19,   13,
-       19,   19,   19,   19,    7,   19,   19,    2
+       26,   26,   33,   31,   32,   24,   31,   32,   24,   32,
+       31,   32,   31,   32,   31,   32,   31,   32,   31,   32,
+       23,   31,   32,   23,   31,   32,   20,   31,   32,   31,
+       32,   20,   31,   32,   20,   31,   32,   20,   31,   32,
+       20,   31,   32,   20,   31,   32,   20,   31,   32,   20,
+       31,   32,   26,   32,   27,   32,   29,   32,   24,   22,
+       21,   23,   25,    1,   20,   20,   20,   20,   20,   20,
+       20,   15,   20,   20,   20,   20,   26,   27,   27,   30,
+       29,   28,   29,   21,    1,   23,   23,    5,   20,   20,
+       20,   10,   20,   12,   20,   20,   20,    4,   20,   14,
+
+       20,   20,   20,   18,   16,   17,    3,    6,   20,   20,
+        9,   20,   20,   20,    8,   20,   20,   11,   20,   13,
+       20,   20,   20,   20,    7,   20,   20,   19,    2
     } ;
 
-static yyconst short int yy_accept[101] =
+static yyconst short int yy_accept[109] =
     {   0,
         1,    1,    1,    2,    3,    4,    6,    9,   11,   13,
        15,   17,   19,   21,   24,   27,   30,   32,   35,   38,
        41,   44,   47,   50,   53,   55,   57,   59,   60,   60,
        60,   61,   62,   63,   64,   65,   65,   65,   66,   66,
        67,   68,   69,   70,   71,   72,   74,   75,   76,   77,
-       78,   79,   80,   81,   82,   83,   84,   84,   84,   85,
-       86,   87,   88,   88,   88,   90,   91,   92,   94,   96,
-       97,   98,  100,  102,  103,  104,  105,  106,  107,  107,
-      108,  110,  111,  113,  114,  115,  117,  118,  120,  122,
-      123,  124,  125,  127,  128,  128,  128,  128,  129,  129
+       78,   79,   80,   81,   82,   83,   84,   84,   84,   84,
+       85,   86,   87,   88,   88,   88,   90,   91,   92,   94,
+       96,   97,   98,  100,  102,  103,  104,  105,  106,  107,
+      107,  107,  108,  110,  111,  113,  114,  115,  117,  118,
+      118,  120,  122,  123,  124,  124,  125,  127,  127,  128,
 
+      128,  128,  128,  128,  129,  129,  130,  130
     } ;
 
 static yyconst int yy_ec[256] =
@@ -381,98 +382,100 @@
         6,    6,    6,    6,    1,    1
     } ;
 
-static yyconst short int yy_base[113] =
+static yyconst short int yy_base[121] =
     {   0,
-        0,    0,   29,   30,  199,  200,   39,   42,  167,  191,
-        0,   36,   42,   42,   45,    0,  161,  169,   33,   41,
-      168,  165,   42,  160,    0,   57,   61,   70,   45,  185,
-      200,    0,   66,  200,    0,   69,    0,    0,  154,  157,
-      170,  166,  162,  162,  162,   62,  151,  151,  151,    0,
-       75,   76,  200,   79,  200,   80,  153,   73,    0,    0,
-       81,    0,  143,  161,  146,  145,  153,    0,    0,  147,
-      146,    0,    0,  140,  145,  200,  200,  200,  134,  200,
-        0,  138,    0,  147,  134,    0,  138,    0,    0,  120,
-       97,   77,    0,   93,   95,   60,   45,  200,  200,  101,
+        0,    0,   29,   30,  207,  208,   39,   42,  175,  199,
+        0,   36,   42,   42,   45,    0,  169,  177,   33,   41,
+      176,  173,   42,  168,    0,   57,   61,   70,   45,  193,
+      208,    0,   67,  208,    0,   70,    0,    0,  162,  165,
+      178,  174,  170,  170,  170,   63,  159,  159,  159,    0,
+       76,   77,  208,   80,  208,   81,  161,   74,  157,    0,
+        0,   82,    0,  150,  168,  153,  152,  160,    0,    0,
+      154,  153,    0,    0,  147,  152,  208,  208,  208,  157,
+      140,  208,    0,  144,    0,  153,  140,    0,  144,  142,
+        0,    0,  149,  145,  140,  145,    0,  122,   94,  104,
 
-      107,  109,  112,  118,  124,  130,  133,  139,  142,  147,
-      153,  159
+       96,   68,   60,  208,   45,  208,  208,  102,  108,  110,
+      113,  119,  125,  131,  134,  140,  143,  148,  154,  160
     } ;
 
-static yyconst short int yy_def[113] =
+static yyconst short int yy_def[121] =
     {   0,
-       99,    1,  100,  100,   99,   99,   99,   99,   99,  101,
-      102,   99,   99,   99,   99,  103,   99,  103,  103,  103,
-      103,  103,  103,  103,  104,  105,  106,   99,   99,  101,
-       99,  107,   99,   99,  108,   99,  109,  103,  110,  103,
-      103,  103,  103,  103,  103,  103,  103,  103,  103,  104,
-      105,  105,   99,  106,   99,  106,   99,   99,  107,  108,
-       99,  109,  110,  111,  103,  103,  103,  103,  103,  103,
-      103,  103,  103,  103,  103,   99,   99,   99,  110,   99,
-      103,  103,  103,  103,  103,  103,  103,  103,  103,  103,
-      103,  103,  103,  103,   99,  112,  112,   99,    0,   99,
+      107,    1,  108,  108,  107,  107,  107,  107,  107,  109,
+      110,  107,  107,  107,  107,  111,  107,  111,  111,  111,
+      111,  111,  111,  111,  112,  113,  114,  107,  107,  109,
+      107,  115,  107,  107,  116,  107,  117,  111,  118,  111,
+      111,  111,  111,  111,  111,  111,  111,  111,  111,  112,
+      113,  113,  107,  114,  107,  114,  107,  107,  107,  115,
+      116,  107,  117,  118,  119,  111,  111,  111,  111,  111,
+      111,  111,  111,  111,  111,  111,  107,  107,  107,  107,
+      118,  107,  111,  111,  111,  111,  111,  111,  111,  107,
+      111,  111,  111,  111,  107,  111,  111,  107,  111,  107,
 
-       99,   99,   99,   99,   99,   99,   99,   99,   99,   99,
-       99,   99
+      107,  107,  120,  107,  120,  107,    0,  107,  107,  107,
+      107,  107,  107,  107,  107,  107,  107,  107,  107,  107
     } ;
 
-static yyconst short int yy_nxt[237] =
+static yyconst short int yy_nxt[245] =
     {   0,
         6,    7,    8,    7,    9,   10,   11,    6,   12,   13,
        14,   15,   15,   16,   16,   17,    6,   16,   18,   19,
        20,   16,   21,   16,   16,   22,   23,   16,   16,   16,
        24,   16,   16,   16,    6,    6,   26,   26,   27,   27,
        28,   28,   28,   28,   28,   28,   33,   33,   33,   34,
-       98,   35,   33,   33,   33,   33,   33,   33,   43,   41,
-       36,   42,   44,   47,   52,   98,   53,   48,   55,   57,
-       56,   28,   28,   28,   58,   37,   33,   33,   33,   61,
-       61,   71,   99,   52,   99,   53,   99,   99,   99,   56,
-       77,   61,   61,   72,   95,   95,   95,   95,   94,   78,
-
-       96,   25,   25,   25,   25,   25,   25,   30,   30,   30,
-       30,   30,   30,   32,   32,   38,   38,   38,   50,   50,
-       93,   50,   50,   50,   51,   51,   51,   51,   51,   51,
-       54,   54,   54,   54,   54,   54,   59,   59,   59,   60,
-       92,   60,   60,   60,   60,   62,   62,   63,   63,   63,
-       63,   63,   63,   79,   79,   79,   79,   79,   79,   97,
-       97,   97,   97,   97,   97,   91,   90,   89,   88,   64,
-       87,   86,   85,   84,   83,   82,   81,   80,   64,   76,
-       75,   74,   73,   70,   69,   68,   67,   66,   65,   64,
-       31,   49,   46,   45,   40,   39,   31,   29,   99,    5,
-
-       99,   99,   99,   99,   99,   99,   99,   99,   99,   99,
-       99,   99,   99,   99,   99,   99,   99,   99,   99,   99,
-       99,   99,   99,   99,   99,   99,   99,   99,   99,   99,
-       99,   99,   99,   99,   99,   99
+      106,   35,   33,   33,   33,   33,   33,   33,   43,   41,
+       36,   42,   44,   47,   52,  106,   53,   48,   55,   57,
+       56,   28,   28,   28,   58,   37,   59,   33,   33,   33,
+       62,   62,   72,  107,   52,  107,   53,  107,  107,  107,
+       56,   78,   62,   62,   73,  101,  101,  101,  101,  104,
+
+       79,  103,   25,   25,   25,   25,   25,   25,   30,   30,
+       30,   30,   30,   30,   32,   32,   38,   38,   38,   50,
+       50,  102,   50,   50,   50,   51,   51,   51,   51,   51,
+       51,   54,   54,   54,   54,   54,   54,   60,   60,   60,
+       61,  100,   61,   61,   61,   61,   63,   63,   64,   64,
+       64,   64,   64,   64,   81,   81,   81,   81,   81,   81,
+      105,  105,  105,  105,  105,  105,   99,   98,   97,   96,
+       95,   94,   93,   92,   91,   65,   90,   89,   88,   87,
+       86,   85,   84,   83,   82,   65,   80,   77,   76,   75,
+       74,   71,   70,   69,   68,   67,   66,   65,   31,   49,
+
+       46,   45,   40,   39,   31,   29,  107,    5,  107,  107,
+      107,  107,  107,  107,  107,  107,  107,  107,  107,  107,
+      107,  107,  107,  107,  107,  107,  107,  107,  107,  107,
+      107,  107,  107,  107,  107,  107,  107,  107,  107,  107,
+      107,  107,  107,  107
     } ;
 
-static yyconst short int yy_chk[237] =
+static yyconst short int yy_chk[245] =
     {   0,
         1,    1,    1,    1,    1,    1,    1,    1,    1,    1,
         1,    1,    1,    1,    1,    1,    1,    1,    1,    1,
         1,    1,    1,    1,    1,    1,    1,    1,    1,    1,
         1,    1,    1,    1,    1,    1,    3,    4,    3,    4,
         7,    7,    7,    8,    8,    8,   12,   12,   12,   13,
-       97,   13,   14,   14,   14,   15,   15,   15,   20,   19,
-       14,   19,   20,   23,   26,   96,   26,   23,   27,   29,
-       27,   28,   28,   28,   29,   14,   33,   33,   33,   36,
-       36,   46,   51,   52,   51,   52,   54,   56,   54,   56,
-       58,   61,   61,   46,   94,   94,   95,   95,   92,   58,
-
-       95,  100,  100,  100,  100,  100,  100,  101,  101,  101,
-      101,  101,  101,  102,  102,  103,  103,  103,  104,  104,
-       91,  104,  104,  104,  105,  105,  105,  105,  105,  105,
-      106,  106,  106,  106,  106,  106,  107,  107,  107,  108,
-       90,  108,  108,  108,  108,  109,  109,  110,  110,  110,
-      110,  110,  110,  111,  111,  111,  111,  111,  111,  112,
-      112,  112,  112,  112,  112,   87,   85,   84,   82,   79,
-       75,   74,   71,   70,   67,   66,   65,   64,   63,   57,
-       49,   48,   47,   45,   44,   43,   42,   41,   40,   39,
-       30,   24,   22,   21,   18,   17,   10,    9,    5,   99,
-
-       99,   99,   99,   99,   99,   99,   99,   99,   99,   99,
-       99,   99,   99,   99,   99,   99,   99,   99,   99,   99,
-       99,   99,   99,   99,   99,   99,   99,   99,   99,   99,
-       99,   99,   99,   99,   99,   99
+      105,   13,   14,   14,   14,   15,   15,   15,   20,   19,
+       14,   19,   20,   23,   26,  103,   26,   23,   27,   29,
+       27,   28,   28,   28,   29,   14,   29,   33,   33,   33,
+       36,   36,   46,   51,   52,   51,   52,   54,   56,   54,
+       56,   58,   62,   62,   46,   99,   99,  101,  101,  102,
+
+       58,  101,  108,  108,  108,  108,  108,  108,  109,  109,
+      109,  109,  109,  109,  110,  110,  111,  111,  111,  112,
+      112,  100,  112,  112,  112,  113,  113,  113,  113,  113,
+      113,  114,  114,  114,  114,  114,  114,  115,  115,  115,
+      116,   98,  116,  116,  116,  116,  117,  117,  118,  118,
+      118,  118,  118,  118,  119,  119,  119,  119,  119,  119,
+      120,  120,  120,  120,  120,  120,   96,   95,   94,   93,
+       90,   89,   87,   86,   84,   81,   80,   76,   75,   72,
+       71,   68,   67,   66,   65,   64,   59,   57,   49,   48,
+       47,   45,   44,   43,   42,   41,   40,   39,   30,   24,
+
+       22,   21,   18,   17,   10,    9,    5,  107,  107,  107,
+      107,  107,  107,  107,  107,  107,  107,  107,  107,  107,
+      107,  107,  107,  107,  107,  107,  107,  107,  107,  107,
+      107,  107,  107,  107,  107,  107,  107,  107,  107,  107,
+      107,  107,  107,  107
     } ;
 
 static yy_state_type yy_state_buf[YY_BUF_SIZE + 2], *yy_state_ptr;
@@ -648,7 +651,7 @@
 
 using namespace llvm;
 
-#line 652 "Lexer.cpp"
+#line 655 "Lexer.cpp"
 
 /* Macros after this point can all be overridden by user definitions in
  * section 1.
@@ -802,7 +805,7 @@
 #line 180 "/Volumes/ProjectsDisk/cvs/llvm/utils/TableGen/FileLexer.l"
 
 
-#line 806 "Lexer.cpp"
+#line 809 "Lexer.cpp"
 
 	if ( yy_init )
 		{
@@ -850,14 +853,14 @@
 			while ( yy_chk[yy_base[yy_current_state] + yy_c] != yy_current_state )
 				{
 				yy_current_state = (int) yy_def[yy_current_state];
-				if ( yy_current_state >= 100 )
+				if ( yy_current_state >= 108 )
 					yy_c = yy_meta[(unsigned int) yy_c];
 				}
 			yy_current_state = yy_nxt[yy_base[yy_current_state] + (unsigned int) yy_c];
 			*yy_state_ptr++ = yy_current_state;
 			++yy_cp;
 			}
-		while ( yy_current_state != 99 );
+		while ( yy_current_state != 107 );
 
 yy_find_action:
 		yy_current_state = *--yy_state_ptr;
@@ -986,77 +989,82 @@
 	YY_BREAK
 case 19:
 YY_RULE_SETUP
-#line 207 "/Volumes/ProjectsDisk/cvs/llvm/utils/TableGen/FileLexer.l"
+#line 205 "/Volumes/ProjectsDisk/cvs/llvm/utils/TableGen/FileLexer.l"
+{ return STRCONCATTOK; }
+	YY_BREAK
+case 20:
+YY_RULE_SETUP
+#line 208 "/Volumes/ProjectsDisk/cvs/llvm/utils/TableGen/FileLexer.l"
 { Filelval.StrVal = new std::string(yytext, yytext+yyleng);
                  return ID; }
 	YY_BREAK
-case 20:
+case 21:
 YY_RULE_SETUP
-#line 209 "/Volumes/ProjectsDisk/cvs/llvm/utils/TableGen/FileLexer.l"
+#line 210 "/Volumes/ProjectsDisk/cvs/llvm/utils/TableGen/FileLexer.l"
 { Filelval.StrVal = new std::string(yytext+1, yytext+yyleng);
                  return VARNAME; } 
 	YY_BREAK
-case 21:
+case 22:
 YY_RULE_SETUP
-#line 212 "/Volumes/ProjectsDisk/cvs/llvm/utils/TableGen/FileLexer.l"
+#line 213 "/Volumes/ProjectsDisk/cvs/llvm/utils/TableGen/FileLexer.l"
 { Filelval.StrVal = new std::string(yytext+1, yytext+yyleng-1);
                  return STRVAL; }
 	YY_BREAK
-case 22:
-YY_RULE_SETUP
-#line 215 "/Volumes/ProjectsDisk/cvs/llvm/utils/TableGen/FileLexer.l"
-{ Filelval.IntVal = ParseInt(Filetext); return INTVAL; }
-	YY_BREAK
 case 23:
 YY_RULE_SETUP
-#line 217 "/Volumes/ProjectsDisk/cvs/llvm/utils/TableGen/FileLexer.l"
-{ /* Ignore whitespace */ }
+#line 216 "/Volumes/ProjectsDisk/cvs/llvm/utils/TableGen/FileLexer.l"
+{ Filelval.IntVal = ParseInt(Filetext); return INTVAL; }
 	YY_BREAK
 case 24:
 YY_RULE_SETUP
-#line 220 "/Volumes/ProjectsDisk/cvs/llvm/utils/TableGen/FileLexer.l"
-{ BEGIN(comment); CommentDepth++; }
+#line 218 "/Volumes/ProjectsDisk/cvs/llvm/utils/TableGen/FileLexer.l"
+{ /* Ignore whitespace */ }
 	YY_BREAK
 case 25:
 YY_RULE_SETUP
 #line 221 "/Volumes/ProjectsDisk/cvs/llvm/utils/TableGen/FileLexer.l"
-{} /* eat anything that's not a '*' or '/' */
+{ BEGIN(comment); CommentDepth++; }
 	YY_BREAK
 case 26:
 YY_RULE_SETUP
 #line 222 "/Volumes/ProjectsDisk/cvs/llvm/utils/TableGen/FileLexer.l"
-{} /* eat up '*'s not followed by '/'s */
+{} /* eat anything that's not a '*' or '/' */
 	YY_BREAK
 case 27:
 YY_RULE_SETUP
 #line 223 "/Volumes/ProjectsDisk/cvs/llvm/utils/TableGen/FileLexer.l"
-{ ++CommentDepth; }
+{} /* eat up '*'s not followed by '/'s */
 	YY_BREAK
 case 28:
 YY_RULE_SETUP
 #line 224 "/Volumes/ProjectsDisk/cvs/llvm/utils/TableGen/FileLexer.l"
-{} /* eat up /'s not followed by *'s */
+{ ++CommentDepth; }
 	YY_BREAK
 case 29:
 YY_RULE_SETUP
 #line 225 "/Volumes/ProjectsDisk/cvs/llvm/utils/TableGen/FileLexer.l"
+{} /* eat up /'s not followed by *'s */
+	YY_BREAK
+case 30:
+YY_RULE_SETUP
+#line 226 "/Volumes/ProjectsDisk/cvs/llvm/utils/TableGen/FileLexer.l"
 { if (!--CommentDepth) { BEGIN(INITIAL); } }
 	YY_BREAK
 case YY_STATE_EOF(comment):
-#line 226 "/Volumes/ProjectsDisk/cvs/llvm/utils/TableGen/FileLexer.l"
+#line 227 "/Volumes/ProjectsDisk/cvs/llvm/utils/TableGen/FileLexer.l"
 { err() << "Unterminated comment!\n"; exit(1); }
 	YY_BREAK
-case 30:
+case 31:
 YY_RULE_SETUP
-#line 228 "/Volumes/ProjectsDisk/cvs/llvm/utils/TableGen/FileLexer.l"
+#line 229 "/Volumes/ProjectsDisk/cvs/llvm/utils/TableGen/FileLexer.l"
 { return Filetext[0]; }
 	YY_BREAK
-case 31:
+case 32:
 YY_RULE_SETUP
-#line 230 "/Volumes/ProjectsDisk/cvs/llvm/utils/TableGen/FileLexer.l"
+#line 231 "/Volumes/ProjectsDisk/cvs/llvm/utils/TableGen/FileLexer.l"
 YY_FATAL_ERROR( "flex scanner jammed" );
 	YY_BREAK
-#line 1060 "Lexer.cpp"
+#line 1068 "Lexer.cpp"
 			case YY_STATE_EOF(INITIAL):
 				yyterminate();
 
@@ -1345,7 +1353,7 @@
 		while ( yy_chk[yy_base[yy_current_state] + yy_c] != yy_current_state )
 			{
 			yy_current_state = (int) yy_def[yy_current_state];
-			if ( yy_current_state >= 100 )
+			if ( yy_current_state >= 108 )
 				yy_c = yy_meta[(unsigned int) yy_c];
 			}
 		yy_current_state = yy_nxt[yy_base[yy_current_state] + (unsigned int) yy_c];
@@ -1375,11 +1383,11 @@
 	while ( yy_chk[yy_base[yy_current_state] + yy_c] != yy_current_state )
 		{
 		yy_current_state = (int) yy_def[yy_current_state];
-		if ( yy_current_state >= 100 )
+		if ( yy_current_state >= 108 )
 			yy_c = yy_meta[(unsigned int) yy_c];
 		}
 	yy_current_state = yy_nxt[yy_base[yy_current_state] + (unsigned int) yy_c];
-	yy_is_jam = (yy_current_state == 99);
+	yy_is_jam = (yy_current_state == 107);
 	if ( ! yy_is_jam )
 		*yy_state_ptr++ = yy_current_state;
 
@@ -1940,6 +1948,6 @@
 	return 0;
 	}
 #endif
-#line 230 "/Volumes/ProjectsDisk/cvs/llvm/utils/TableGen/FileLexer.l"
+#line 231 "/Volumes/ProjectsDisk/cvs/llvm/utils/TableGen/FileLexer.l"
 
 


Index: llvm/utils/TableGen/FileLexer.l.cvs
diff -u llvm/utils/TableGen/FileLexer.l.cvs:1.3 llvm/utils/TableGen/FileLexer.l.cvs:1.4
--- llvm/utils/TableGen/FileLexer.l.cvs:1.3	Fri Mar  3 13:34:28 2006
+++ llvm/utils/TableGen/FileLexer.l.cvs	Fri Mar 31 15:54:11 2006
@@ -202,6 +202,7 @@
 !sra           { return SRATOK; }
 !srl           { return SRLTOK; }
 !shl           { return SHLTOK; }
+!strconcat     { return STRCONCATTOK; }
 
 
 {Identifier}   { Filelval.StrVal = new std::string(yytext, yytext+yyleng);


Index: llvm/utils/TableGen/FileParser.cpp.cvs
diff -u llvm/utils/TableGen/FileParser.cpp.cvs:1.2 llvm/utils/TableGen/FileParser.cpp.cvs:1.3
--- llvm/utils/TableGen/FileParser.cpp.cvs:1.2	Thu Mar 30 16:51:12 2006
+++ llvm/utils/TableGen/FileParser.cpp.cvs	Fri Mar 31 15:54:11 2006
@@ -26,11 +26,12 @@
 #define	SHLTOK	269
 #define	SRATOK	270
 #define	SRLTOK	271
-#define	INTVAL	272
-#define	ID	273
-#define	VARNAME	274
-#define	STRVAL	275
-#define	CODEFRAGMENT	276
+#define	STRCONCATTOK	272
+#define	INTVAL	273
+#define	ID	274
+#define	VARNAME	275
+#define	STRVAL	276
+#define	CODEFRAGMENT	277
 
 #line 14 "/Volumes/ProjectsDisk/cvs/llvm/utils/TableGen/FileParser.y"
 
@@ -230,26 +231,26 @@
 
 
 
-#define	YYFINAL		162
+#define	YYFINAL		168
 #define	YYFLAG		-32768
-#define	YYNTBASE	38
+#define	YYNTBASE	39
 
-#define YYTRANSLATE(x) ((unsigned)(x) <= 276 ? yytranslate[x] : 79)
+#define YYTRANSLATE(x) ((unsigned)(x) <= 277 ? yytranslate[x] : 80)
 
 static const char yytranslate[] = {     0,
      2,     2,     2,     2,     2,     2,     2,     2,     2,     2,
      2,     2,     2,     2,     2,     2,     2,     2,     2,     2,
      2,     2,     2,     2,     2,     2,     2,     2,     2,     2,
-     2,     2,     2,     2,     2,     2,     2,     2,     2,    32,
-    33,     2,     2,    34,    36,    31,     2,     2,     2,     2,
-     2,     2,     2,     2,     2,     2,     2,    35,    37,    23,
-    25,    24,    26,     2,     2,     2,     2,     2,     2,     2,
+     2,     2,     2,     2,     2,     2,     2,     2,     2,    33,
+    34,     2,     2,    35,    37,    32,     2,     2,     2,     2,
+     2,     2,     2,     2,     2,     2,     2,    36,    38,    24,
+    26,    25,    27,     2,     2,     2,     2,     2,     2,     2,
      2,     2,     2,     2,     2,     2,     2,     2,     2,     2,
      2,     2,     2,     2,     2,     2,     2,     2,     2,     2,
-    29,     2,    30,     2,     2,     2,     2,     2,     2,     2,
+    30,     2,    31,     2,     2,     2,     2,     2,     2,     2,
      2,     2,     2,     2,     2,     2,     2,     2,     2,     2,
      2,     2,     2,     2,     2,     2,     2,     2,     2,     2,
-     2,     2,    27,     2,    28,     2,     2,     2,     2,     2,
+     2,     2,    28,     2,    29,     2,     2,     2,     2,     2,
      2,     2,     2,     2,     2,     2,     2,     2,     2,     2,
      2,     2,     2,     2,     2,     2,     2,     2,     2,     2,
      2,     2,     2,     2,     2,     2,     2,     2,     2,     2,
@@ -264,7 +265,7 @@
      2,     2,     2,     2,     2,     2,     2,     2,     2,     2,
      2,     2,     2,     2,     2,     1,     3,     4,     5,     6,
      7,     8,     9,    10,    11,    12,    13,    14,    15,    16,
-    17,    18,    19,    20,    21,    22
+    17,    18,    19,    20,    21,    22,    23
 };
 
 #if YYDEBUG != 0
@@ -272,42 +273,43 @@
      0,     2,     4,     6,    11,    13,    18,    20,    22,    24,
     25,    27,    28,    31,    33,    35,    37,    39,    41,    43,
     47,    52,    57,    61,    65,    70,    75,    82,    89,    96,
-    97,   100,   103,   108,   109,   111,   113,   117,   120,   124,
-   130,   135,   137,   138,   142,   143,   145,   147,   151,   156,
-   159,   166,   167,   170,   172,   176,   178,   183,   185,   189,
-   190,   193,   195,   199,   203,   204,   206,   208,   209,   211,
-   213,   215,   216,   220,   221,   222,   229,   233,   235,   237,
-   242,   244,   248,   249,   254,   259,   262,   264,   267
+   103,   104,   107,   110,   115,   116,   118,   120,   124,   127,
+   131,   137,   142,   144,   145,   149,   150,   152,   154,   158,
+   163,   166,   173,   174,   177,   179,   183,   185,   190,   192,
+   196,   197,   200,   202,   206,   210,   211,   213,   215,   216,
+   218,   220,   222,   223,   227,   228,   229,   236,   240,   242,
+   244,   249,   251,   255,   256,   261,   266,   269,   271,   274
 };
 
-static const short yyrhs[] = {    19,
-     0,     5,     0,     4,     0,     6,    23,    18,    24,     0,
-     3,     0,     7,    23,    39,    24,     0,     8,     0,     9,
-     0,    38,     0,     0,    12,     0,     0,    25,    43,     0,
-    19,     0,    42,     0,    18,     0,    21,     0,    22,     0,
-    26,     0,    27,    50,    28,     0,    19,    23,    51,    24,
-     0,    43,    27,    48,    28,     0,    29,    50,    30,     0,
-    43,    31,    19,     0,    32,    42,    46,    33,     0,    43,
-    29,    48,    30,     0,    15,    32,    43,    34,    43,    33,
-     0,    16,    32,    43,    34,    43,    33,     0,    17,    32,
-    43,    34,    43,    33,     0,     0,    35,    20,     0,    43,
-    44,     0,    45,    34,    43,    44,     0,     0,    45,     0,
-    18,     0,    18,    36,    18,     0,    18,    18,     0,    47,
-    34,    18,     0,    47,    34,    18,    36,    18,     0,    47,
-    34,    18,    18,     0,    47,     0,     0,    27,    48,    28,
-     0,     0,    51,     0,    43,     0,    51,    34,    43,     0,
-    40,    39,    19,    41,     0,    52,    37,     0,    13,    19,
-    49,    25,    43,    37,     0,     0,    54,    53,     0,    37,
-     0,    27,    54,    28,     0,    38,     0,    38,    23,    51,
-    24,     0,    56,     0,    57,    34,    56,     0,     0,    35,
-    57,     0,    52,     0,    59,    34,    52,     0,    23,    59,
-    24,     0,     0,    60,     0,    19,     0,     0,    62,     0,
-    63,     0,    63,     0,     0,    58,    67,    55,     0,     0,
-     0,    10,    64,    69,    61,    70,    66,     0,    11,    65,
-    66,     0,    68,     0,    71,     0,    19,    49,    25,    43,
-     0,    73,     0,    74,    34,    73,     0,     0,    13,    76,
-    74,    14,     0,    75,    27,    77,    28,     0,    75,    72,
-     0,    72,     0,    77,    72,     0,    77,     0
+static const short yyrhs[] = {    20,
+     0,     5,     0,     4,     0,     6,    24,    19,    25,     0,
+     3,     0,     7,    24,    40,    25,     0,     8,     0,     9,
+     0,    39,     0,     0,    12,     0,     0,    26,    44,     0,
+    20,     0,    43,     0,    19,     0,    22,     0,    23,     0,
+    27,     0,    28,    51,    29,     0,    20,    24,    52,    25,
+     0,    44,    28,    49,    29,     0,    30,    51,    31,     0,
+    44,    32,    20,     0,    33,    43,    47,    34,     0,    44,
+    30,    49,    31,     0,    15,    33,    44,    35,    44,    34,
+     0,    16,    33,    44,    35,    44,    34,     0,    17,    33,
+    44,    35,    44,    34,     0,    18,    33,    44,    35,    44,
+    34,     0,     0,    36,    21,     0,    44,    45,     0,    46,
+    35,    44,    45,     0,     0,    46,     0,    19,     0,    19,
+    37,    19,     0,    19,    19,     0,    48,    35,    19,     0,
+    48,    35,    19,    37,    19,     0,    48,    35,    19,    19,
+     0,    48,     0,     0,    28,    49,    29,     0,     0,    52,
+     0,    44,     0,    52,    35,    44,     0,    41,    40,    20,
+    42,     0,    53,    38,     0,    13,    20,    50,    26,    44,
+    38,     0,     0,    55,    54,     0,    38,     0,    28,    55,
+    29,     0,    39,     0,    39,    24,    52,    25,     0,    57,
+     0,    58,    35,    57,     0,     0,    36,    58,     0,    53,
+     0,    60,    35,    53,     0,    24,    60,    25,     0,     0,
+    61,     0,    20,     0,     0,    63,     0,    64,     0,    64,
+     0,     0,    59,    68,    56,     0,     0,     0,    10,    65,
+    70,    62,    71,    67,     0,    11,    66,    67,     0,    69,
+     0,    72,     0,    20,    50,    26,    44,     0,    74,     0,
+    75,    35,    74,     0,     0,    13,    77,    75,    14,     0,
+    76,    28,    78,    29,     0,    76,    73,     0,    73,     0,
+    78,    73,     0,    78,     0
 };
 
 #endif
@@ -316,13 +318,13 @@
 static const short yyrline[] = { 0,
    223,   234,   236,   238,   240,   242,   244,   246,   248,   252,
    252,   254,   254,   256,   273,   275,   277,   280,   283,   285,
-   298,   326,   333,   336,   343,   346,   354,   360,   366,   374,
-   377,   381,   386,   392,   395,   398,   401,   414,   428,   430,
-   443,   459,   461,   461,   465,   467,   471,   474,   478,   488,
-   490,   496,   496,   497,   497,   499,   501,   505,   510,   515,
-   518,   522,   525,   530,   531,   531,   533,   533,   535,   542,
-   560,   572,   586,   591,   593,   595,   599,   608,   608,   610,
-   615,   615,   618,   618,   621,   624,   628,   628,   630
+   298,   326,   333,   336,   343,   346,   354,   356,   358,   360,
+   364,   367,   371,   376,   382,   385,   388,   391,   404,   418,
+   420,   433,   449,   451,   451,   455,   457,   461,   464,   468,
+   478,   480,   486,   486,   487,   487,   489,   491,   495,   500,
+   505,   508,   512,   515,   520,   521,   521,   523,   523,   525,
+   532,   550,   562,   576,   581,   583,   585,   589,   598,   598,
+   600,   605,   605,   608,   608,   611,   614,   618,   618,   620
 };
 #endif
 
@@ -331,137 +333,139 @@
 
 static const char * const yytname[] = {   "$","error","$undefined.","INT","BIT",
 "STRING","BITS","LIST","CODE","DAG","CLASS","DEF","FIELD","LET","IN","SHLTOK",
-"SRATOK","SRLTOK","INTVAL","ID","VARNAME","STRVAL","CODEFRAGMENT","'<'","'>'",
-"'='","'?'","'{'","'}'","'['","']'","'.'","'('","')'","','","':'","'-'","';'",
-"ClassID","Type","OptPrefix","OptValue","IDValue","Value","OptVarName","DagArgListNE",
-"DagArgList","RBitList","BitList","OptBitList","ValueList","ValueListNE","Declaration",
-"BodyItem","BodyList","Body","SubClassRef","ClassListNE","ClassList","DeclListNE",
-"TemplateArgList","OptTemplateArgList","OptID","ObjectName","ClassName","DefName",
-"ObjectBody","@1","ClassInst","@2","@3","DefInst","Object","LETItem","LETList",
-"LETCommand","@4","ObjectList","File", NULL
+"SRATOK","SRLTOK","STRCONCATTOK","INTVAL","ID","VARNAME","STRVAL","CODEFRAGMENT",
+"'<'","'>'","'='","'?'","'{'","'}'","'['","']'","'.'","'('","')'","','","':'",
+"'-'","';'","ClassID","Type","OptPrefix","OptValue","IDValue","Value","OptVarName",
+"DagArgListNE","DagArgList","RBitList","BitList","OptBitList","ValueList","ValueListNE",
+"Declaration","BodyItem","BodyList","Body","SubClassRef","ClassListNE","ClassList",
+"DeclListNE","TemplateArgList","OptTemplateArgList","OptID","ObjectName","ClassName",
+"DefName","ObjectBody","@1","ClassInst","@2","@3","DefInst","Object","LETItem",
+"LETList","LETCommand","@4","ObjectList","File", NULL
 };
 #endif
 
 static const short yyr1[] = {     0,
-    38,    39,    39,    39,    39,    39,    39,    39,    39,    40,
-    40,    41,    41,    42,    43,    43,    43,    43,    43,    43,
-    43,    43,    43,    43,    43,    43,    43,    43,    43,    44,
-    44,    45,    45,    46,    46,    47,    47,    47,    47,    47,
-    47,    48,    49,    49,    50,    50,    51,    51,    52,    53,
-    53,    54,    54,    55,    55,    56,    56,    57,    57,    58,
-    58,    59,    59,    60,    61,    61,    62,    62,    63,    64,
-    65,    67,    66,    69,    70,    68,    71,    72,    72,    73,
-    74,    74,    76,    75,    72,    72,    77,    77,    78
+    39,    40,    40,    40,    40,    40,    40,    40,    40,    41,
+    41,    42,    42,    43,    44,    44,    44,    44,    44,    44,
+    44,    44,    44,    44,    44,    44,    44,    44,    44,    44,
+    45,    45,    46,    46,    47,    47,    48,    48,    48,    48,
+    48,    48,    49,    50,    50,    51,    51,    52,    52,    53,
+    54,    54,    55,    55,    56,    56,    57,    57,    58,    58,
+    59,    59,    60,    60,    61,    62,    62,    63,    63,    64,
+    65,    66,    68,    67,    70,    71,    69,    72,    73,    73,
+    74,    75,    75,    77,    76,    73,    73,    78,    78,    79
 };
 
 static const short yyr2[] = {     0,
      1,     1,     1,     4,     1,     4,     1,     1,     1,     0,
      1,     0,     2,     1,     1,     1,     1,     1,     1,     3,
-     4,     4,     3,     3,     4,     4,     6,     6,     6,     0,
-     2,     2,     4,     0,     1,     1,     3,     2,     3,     5,
-     4,     1,     0,     3,     0,     1,     1,     3,     4,     2,
-     6,     0,     2,     1,     3,     1,     4,     1,     3,     0,
-     2,     1,     3,     3,     0,     1,     1,     0,     1,     1,
-     1,     0,     3,     0,     0,     6,     3,     1,     1,     4,
-     1,     3,     0,     4,     4,     2,     1,     2,     1
+     4,     4,     3,     3,     4,     4,     6,     6,     6,     6,
+     0,     2,     2,     4,     0,     1,     1,     3,     2,     3,
+     5,     4,     1,     0,     3,     0,     1,     1,     3,     4,
+     2,     6,     0,     2,     1,     3,     1,     4,     1,     3,
+     0,     2,     1,     3,     3,     0,     1,     1,     0,     1,
+     1,     1,     0,     3,     0,     0,     6,     3,     1,     1,
+     4,     1,     3,     0,     4,     4,     2,     1,     2,     1
 };
 
 static const short yydefact[] = {     0,
-    68,    68,    83,    78,    79,    87,     0,    89,    67,    69,
-    70,    74,    71,    60,     0,     0,    86,    88,    65,     0,
-    72,    77,    43,    81,     0,     0,    10,    66,    75,     1,
-    56,    58,    61,     0,     0,     0,    84,     0,    85,    11,
-     0,    62,     0,    60,     0,     0,    52,    54,    73,    36,
-    42,     0,     0,    82,     5,     3,     2,     0,     0,     7,
-     8,     9,     0,    64,    10,    76,     0,     0,     0,    16,
-    14,    17,    18,    19,    45,    45,     0,    15,    47,     0,
-    59,    10,    38,     0,     0,    44,    80,     0,     0,    12,
-    63,     0,     0,     0,     0,     0,    46,     0,    14,    34,
-     0,     0,     0,    57,     0,     0,    55,     0,    53,    37,
-    39,     0,     0,     0,    49,     0,     0,     0,     0,    20,
-    23,    30,    35,     0,     0,     0,    24,    48,    43,    50,
-    41,     0,     4,     6,    13,     0,     0,     0,    21,     0,
-    32,     0,    25,    22,    26,     0,    40,     0,     0,     0,
-    31,    30,     0,    27,    28,    29,    33,     0,    51,     0,
-     0,     0
+    69,    69,    84,    79,    80,    88,     0,    90,    68,    70,
+    71,    75,    72,    61,     0,     0,    87,    89,    66,     0,
+    73,    78,    44,    82,     0,     0,    10,    67,    76,     1,
+    57,    59,    62,     0,     0,     0,    85,     0,    86,    11,
+     0,    63,     0,    61,     0,     0,    53,    55,    74,    37,
+    43,     0,     0,    83,     5,     3,     2,     0,     0,     7,
+     8,     9,     0,    65,    10,    77,     0,     0,     0,     0,
+    16,    14,    17,    18,    19,    46,    46,     0,    15,    48,
+     0,    60,    10,    39,     0,     0,    45,    81,     0,     0,
+    12,    64,     0,     0,     0,     0,     0,     0,    47,     0,
+    14,    35,     0,     0,     0,    58,     0,     0,    56,     0,
+    54,    38,    40,     0,     0,     0,    50,     0,     0,     0,
+     0,     0,    20,    23,    31,    36,     0,     0,     0,    24,
+    49,    44,    51,    42,     0,     4,     6,    13,     0,     0,
+     0,     0,    21,     0,    33,     0,    25,    22,    26,     0,
+    41,     0,     0,     0,     0,    32,    31,     0,    27,    28,
+    29,    30,    34,     0,    52,     0,     0,     0
 };
 
 static const short yydefgoto[] = {    31,
-    63,    41,   115,    78,    79,   141,   123,   124,    51,    52,
-    36,    96,    97,    42,   109,    82,    49,    32,    33,    21,
+    63,    41,   117,    79,    80,   145,   126,   127,    51,    52,
+    36,    98,    99,    42,   111,    83,    49,    32,    33,    21,
     43,    28,    29,    10,    11,    12,    14,    22,    34,     4,
-    19,    44,     5,     6,    24,    25,     7,    15,     8,   160
+    19,    44,     5,     6,    24,    25,     7,    15,     8,   166
 };
 
-static const short yypact[] = {     5,
-     7,     7,-32768,-32768,-32768,-32768,     1,     5,-32768,-32768,
--32768,-32768,-32768,   -18,    25,     5,-32768,-32768,    23,    30,
--32768,-32768,    44,-32768,   -11,    -3,    60,-32768,-32768,-32768,
-    54,-32768,    40,    -8,    63,    62,-32768,    25,-32768,-32768,
-    50,-32768,    39,   -18,    16,    30,-32768,-32768,-32768,   -14,
-    45,    65,    16,-32768,-32768,-32768,-32768,    68,    74,-32768,
--32768,-32768,    80,-32768,    60,-32768,    87,    91,    92,-32768,
-    98,-32768,-32768,-32768,    16,    16,   106,-32768,    76,    41,
--32768,     8,-32768,   108,   109,-32768,    76,   110,    50,   104,
--32768,    16,    16,    16,    16,   102,    97,   103,-32768,    16,
-    63,    63,   113,-32768,    16,   115,-32768,    99,-32768,-32768,
-    -9,   111,   114,    16,-32768,    61,    67,    75,    42,-32768,
--32768,    51,   105,   107,   116,   112,-32768,    76,    44,-32768,
--32768,   119,-32768,-32768,    76,    16,    16,    16,-32768,   121,
--32768,    16,-32768,-32768,-32768,   118,-32768,    81,    84,    89,
--32768,    51,    16,-32768,-32768,-32768,-32768,    33,-32768,   145,
-   146,-32768
+static const short yypact[] = {    67,
+   -14,   -14,-32768,-32768,-32768,-32768,    19,    67,-32768,-32768,
+-32768,-32768,-32768,    -3,    63,    67,-32768,-32768,    60,    65,
+-32768,-32768,     7,-32768,   -11,    -6,    79,-32768,-32768,-32768,
+    71,-32768,     4,   -16,    82,    73,-32768,    63,-32768,-32768,
+    61,-32768,    11,    -3,    -2,    65,-32768,-32768,-32768,     0,
+    72,    98,    -2,-32768,-32768,-32768,-32768,   105,   106,-32768,
+-32768,-32768,   111,-32768,    79,-32768,    99,   100,   101,   102,
+-32768,   112,-32768,-32768,-32768,    -2,    -2,   117,-32768,    96,
+    23,-32768,    32,-32768,   119,   120,-32768,    96,   121,    61,
+   115,-32768,    -2,    -2,    -2,    -2,    -2,   113,   108,   114,
+-32768,    -2,    82,    82,   124,-32768,    -2,   126,-32768,   109,
+-32768,-32768,    15,   123,   125,    -2,-32768,    27,    62,    68,
+    74,    25,-32768,-32768,    43,   116,   118,   127,   122,-32768,
+    96,     7,-32768,-32768,   130,-32768,-32768,    96,    -2,    -2,
+    -2,    -2,-32768,   133,-32768,    -2,-32768,-32768,-32768,   129,
+-32768,    80,    83,    88,    91,-32768,    43,    -2,-32768,-32768,
+-32768,-32768,-32768,    44,-32768,   157,   158,-32768
 };
 
 static const short yypgoto[] = {   -39,
-    58,-32768,-32768,    71,   -53,    -1,-32768,-32768,-32768,   -34,
-    20,    77,   -44,   -52,-32768,-32768,-32768,   117,-32768,-32768,
--32768,-32768,-32768,-32768,   148,-32768,-32768,   120,-32768,-32768,
--32768,-32768,-32768,    -2,   122,-32768,-32768,-32768,   136,-32768
+    69,-32768,-32768,    84,   -53,     3,-32768,-32768,-32768,   -93,
+    29,    86,   -44,   -27,-32768,-32768,-32768,   128,-32768,-32768,
+-32768,-32768,-32768,-32768,   162,-32768,-32768,   131,-32768,-32768,
+-32768,-32768,-32768,     1,   132,-32768,-32768,-32768,   149,-32768
 };
 
 
-#define	YYLAST		164
+#define	YYLAST		175
 
 
-static const short yytable[] = {    87,
-    80,    62,    37,    83,    17,    18,     1,     2,   131,     3,
-     1,     2,    91,     3,     1,     2,    20,     3,    47,    40,
-   106,    84,    38,    18,    39,     9,   132,    16,    48,   108,
-    67,    68,    69,    70,    71,   107,    72,    73,   116,   117,
-   118,    74,    75,    23,    76,    27,   122,    77,    30,    62,
-   119,   128,    55,    56,    57,    58,    59,    60,    61,   101,
-   135,   102,    64,   103,   104,   139,   125,   126,    30,   159,
-    35,    40,    65,    46,   105,   105,    45,   101,    85,   102,
-    50,   103,   148,   149,   150,   140,    53,   101,   152,   102,
-    88,   103,    86,   101,   136,   102,    89,   103,    90,   158,
-   137,   101,   101,   102,   102,   103,   103,   101,   138,   102,
-   101,   103,   102,   154,   103,   101,   155,   102,    92,   103,
-    95,   156,    93,    94,    99,   110,   111,   112,   114,   120,
-   105,   127,   121,   129,   133,   130,   147,   134,   142,   143,
-   151,   145,   153,   144,   161,   162,   113,   100,   146,    13,
-   157,    26,    98,     0,     0,     0,     0,     0,     0,    54,
-     0,     0,    81,    66
+static const short yytable[] = {    88,
+    81,    62,    37,     1,     2,     9,     3,    17,    18,   128,
+   129,    47,    67,    68,    69,    70,    71,    72,    84,    73,
+    74,    48,    39,    38,    75,    76,    18,    77,     1,     2,
+    78,     3,    20,   134,    35,    64,    85,    92,    46,   118,
+   119,   120,   121,    40,   108,    65,    16,   106,   125,   143,
+    62,   135,   122,   131,   103,   110,   104,   107,   105,   107,
+   109,   139,   138,    55,    56,    57,    58,    59,    60,    61,
+   103,   103,   104,   104,   105,   105,     1,     2,   144,     3,
+    30,   165,    23,    27,    30,   152,   153,   154,   155,   103,
+    40,   104,   157,   105,    45,   103,   140,   104,    53,   105,
+    50,   103,   141,   104,   164,   105,    86,   103,   142,   104,
+   103,   105,   104,   159,   105,   103,   160,   104,   103,   105,
+   104,   161,   105,   103,   162,   104,    87,   105,    89,    90,
+    91,    93,    94,    95,    96,    97,   101,   112,   113,   114,
+   116,   123,   107,   130,   124,   132,   133,   136,   151,   137,
+   146,   147,   149,   156,   158,   148,   167,   168,   115,   163,
+   150,   102,   100,    13,    26,     0,     0,     0,     0,    54,
+     0,     0,     0,    82,    66
 };
 
 static const short yycheck[] = {    53,
-    45,    41,    14,    18,     7,     8,    10,    11,    18,    13,
-    10,    11,    65,    13,    10,    11,    35,    13,    27,    12,
-    13,    36,    34,    26,    28,    19,    36,    27,    37,    82,
-    15,    16,    17,    18,    19,    28,    21,    22,    92,    93,
-    94,    26,    27,    19,    29,    23,   100,    32,    19,    89,
-    95,   105,     3,     4,     5,     6,     7,     8,     9,    27,
-   114,    29,    24,    31,    24,    24,   101,   102,    19,    37,
-    27,    12,    34,    34,    34,    34,    23,    27,    34,    29,
-    18,    31,   136,   137,   138,    35,    25,    27,   142,    29,
-    23,    31,    28,    27,    34,    29,    23,    31,    19,   153,
-    34,    27,    27,    29,    29,    31,    31,    27,    34,    29,
-    27,    31,    29,    33,    31,    27,    33,    29,    32,    31,
-    23,    33,    32,    32,    19,    18,    18,    18,    25,    28,
-    34,    19,    30,    19,    24,    37,    18,    24,    34,    33,
-    20,    30,    25,    28,     0,     0,    89,    77,   129,     2,
-   152,    16,    76,    -1,    -1,    -1,    -1,    -1,    -1,    38,
-    -1,    -1,    46,    44
+    45,    41,    14,    10,    11,    20,    13,     7,     8,   103,
+   104,    28,    15,    16,    17,    18,    19,    20,    19,    22,
+    23,    38,    29,    35,    27,    28,    26,    30,    10,    11,
+    33,    13,    36,    19,    28,    25,    37,    65,    35,    93,
+    94,    95,    96,    12,    13,    35,    28,    25,   102,    25,
+    90,    37,    97,   107,    28,    83,    30,    35,    32,    35,
+    29,    35,   116,     3,     4,     5,     6,     7,     8,     9,
+    28,    28,    30,    30,    32,    32,    10,    11,    36,    13,
+    20,    38,    20,    24,    20,   139,   140,   141,   142,    28,
+    12,    30,   146,    32,    24,    28,    35,    30,    26,    32,
+    19,    28,    35,    30,   158,    32,    35,    28,    35,    30,
+    28,    32,    30,    34,    32,    28,    34,    30,    28,    32,
+    30,    34,    32,    28,    34,    30,    29,    32,    24,    24,
+    20,    33,    33,    33,    33,    24,    20,    19,    19,    19,
+    26,    29,    35,    20,    31,    20,    38,    25,    19,    25,
+    35,    34,    31,    21,    26,    29,     0,     0,    90,   157,
+   132,    78,    77,     2,    16,    -1,    -1,    -1,    -1,    38,
+    -1,    -1,    -1,    46,    44
 };
 /* -*-C-*-  Note some compilers choke on comments on `#line' lines.  */
 #line 3 "/usr/share/bison.simple"
@@ -1232,80 +1236,74 @@
 case 27:
 #line 354 "/Volumes/ProjectsDisk/cvs/llvm/utils/TableGen/FileParser.y"
 {
-    yyval.Initializer = yyvsp[-3].Initializer->getBinaryOp(Init::SHL, yyvsp[-1].Initializer);
-    if (yyval.Initializer == 0) {
-      err() << "Cannot shift values '" << *yyvsp[-3].Initializer << "' and '" << *yyvsp[-1].Initializer << "'!\n";
-      exit(1);
-    }
+    yyval.Initializer = (new BinOpInit(BinOpInit::SHL, yyvsp[-3].Initializer, yyvsp[-1].Initializer))->Fold();
   ;
     break;}
 case 28:
-#line 360 "/Volumes/ProjectsDisk/cvs/llvm/utils/TableGen/FileParser.y"
+#line 356 "/Volumes/ProjectsDisk/cvs/llvm/utils/TableGen/FileParser.y"
 {
-    yyval.Initializer = yyvsp[-3].Initializer->getBinaryOp(Init::SRA, yyvsp[-1].Initializer);
-    if (yyval.Initializer == 0) {
-      err() << "Cannot shift values '" << *yyvsp[-3].Initializer << "' and '" << *yyvsp[-1].Initializer << "'!\n";
-      exit(1);
-    }
+    yyval.Initializer = (new BinOpInit(BinOpInit::SRA, yyvsp[-3].Initializer, yyvsp[-1].Initializer))->Fold();
   ;
     break;}
 case 29:
-#line 366 "/Volumes/ProjectsDisk/cvs/llvm/utils/TableGen/FileParser.y"
+#line 358 "/Volumes/ProjectsDisk/cvs/llvm/utils/TableGen/FileParser.y"
 {
-    yyval.Initializer = yyvsp[-3].Initializer->getBinaryOp(Init::SRL, yyvsp[-1].Initializer);
-    if (yyval.Initializer == 0) {
-      err() << "Cannot shift values '" << *yyvsp[-3].Initializer << "' and '" << *yyvsp[-1].Initializer << "'!\n";
-      exit(1);
-    }
+    yyval.Initializer = (new BinOpInit(BinOpInit::SRL, yyvsp[-3].Initializer, yyvsp[-1].Initializer))->Fold();
   ;
     break;}
 case 30:
-#line 374 "/Volumes/ProjectsDisk/cvs/llvm/utils/TableGen/FileParser.y"
+#line 360 "/Volumes/ProjectsDisk/cvs/llvm/utils/TableGen/FileParser.y"
 {
-    yyval.StrVal = new std::string();
+    yyval.Initializer = (new BinOpInit(BinOpInit::STRCONCAT, yyvsp[-3].Initializer, yyvsp[-1].Initializer))->Fold();
   ;
     break;}
 case 31:
-#line 377 "/Volumes/ProjectsDisk/cvs/llvm/utils/TableGen/FileParser.y"
+#line 364 "/Volumes/ProjectsDisk/cvs/llvm/utils/TableGen/FileParser.y"
 {
-    yyval.StrVal = yyvsp[0].StrVal;
+    yyval.StrVal = new std::string();
   ;
     break;}
 case 32:
-#line 381 "/Volumes/ProjectsDisk/cvs/llvm/utils/TableGen/FileParser.y"
+#line 367 "/Volumes/ProjectsDisk/cvs/llvm/utils/TableGen/FileParser.y"
+{
+    yyval.StrVal = yyvsp[0].StrVal;
+  ;
+    break;}
+case 33:
+#line 371 "/Volumes/ProjectsDisk/cvs/llvm/utils/TableGen/FileParser.y"
 {
     yyval.DagValueList = new std::vector<std::pair<Init*, std::string> >();
     yyval.DagValueList->push_back(std::make_pair(yyvsp[-1].Initializer, *yyvsp[0].StrVal));
     delete yyvsp[0].StrVal;
   ;
     break;}
-case 33:
-#line 386 "/Volumes/ProjectsDisk/cvs/llvm/utils/TableGen/FileParser.y"
+case 34:
+#line 376 "/Volumes/ProjectsDisk/cvs/llvm/utils/TableGen/FileParser.y"
 {
     yyvsp[-3].DagValueList->push_back(std::make_pair(yyvsp[-1].Initializer, *yyvsp[0].StrVal));
     delete yyvsp[0].StrVal;
     yyval.DagValueList = yyvsp[-3].DagValueList;
   ;
     break;}
-case 34:
-#line 392 "/Volumes/ProjectsDisk/cvs/llvm/utils/TableGen/FileParser.y"
+case 35:
+#line 382 "/Volumes/ProjectsDisk/cvs/llvm/utils/TableGen/FileParser.y"
 {
     yyval.DagValueList = new std::vector<std::pair<Init*, std::string> >();
   ;
     break;}
-case 35:
-#line 395 "/Volumes/ProjectsDisk/cvs/llvm/utils/TableGen/FileParser.y"
+case 36:
+#line 385 "/Volumes/ProjectsDisk/cvs/llvm/utils/TableGen/FileParser.y"
 { yyval.DagValueList = yyvsp[0].DagValueList; ;
     break;}
-case 36:
-#line 398 "/Volumes/ProjectsDisk/cvs/llvm/utils/TableGen/FileParser.y"
+case 37:
+#line 388 "/Volumes/ProjectsDisk/cvs/llvm/utils/TableGen/FileParser.y"
 {
     yyval.BitList = new std::vector<unsigned>();
     yyval.BitList->push_back(yyvsp[0].IntVal);
   ;
     break;}
-case 37:
-#line 401 "/Volumes/ProjectsDisk/cvs/llvm/utils/TableGen/FileParser.y"
+case 38:
+#line 391 "/Volumes/ProjectsDisk/cvs/llvm/utils/TableGen/FileParser.y"
 {
     if (yyvsp[-2].IntVal < 0 || yyvsp[0].IntVal < 0) {
       err() << "Invalid range: " << yyvsp[-2].IntVal << "-" << yyvsp[0].IntVal << "!\n";
@@ -1321,8 +1319,8 @@
     }
   ;
     break;}
-case 38:
-#line 414 "/Volumes/ProjectsDisk/cvs/llvm/utils/TableGen/FileParser.y"
+case 39:
+#line 404 "/Volumes/ProjectsDisk/cvs/llvm/utils/TableGen/FileParser.y"
 {
     yyvsp[0].IntVal = -yyvsp[0].IntVal;
     if (yyvsp[-1].IntVal < 0 || yyvsp[0].IntVal < 0) {
@@ -1339,14 +1337,14 @@
     }
   ;
     break;}
-case 39:
-#line 428 "/Volumes/ProjectsDisk/cvs/llvm/utils/TableGen/FileParser.y"
+case 40:
+#line 418 "/Volumes/ProjectsDisk/cvs/llvm/utils/TableGen/FileParser.y"
 {
     (yyval.BitList=yyvsp[-2].BitList)->push_back(yyvsp[0].IntVal);
   ;
     break;}
-case 40:
-#line 430 "/Volumes/ProjectsDisk/cvs/llvm/utils/TableGen/FileParser.y"
+case 41:
+#line 420 "/Volumes/ProjectsDisk/cvs/llvm/utils/TableGen/FileParser.y"
 {
     if (yyvsp[-2].IntVal < 0 || yyvsp[0].IntVal < 0) {
       err() << "Invalid range: " << yyvsp[-2].IntVal << "-" << yyvsp[0].IntVal << "!\n";
@@ -1362,8 +1360,8 @@
     }
   ;
     break;}
-case 41:
-#line 443 "/Volumes/ProjectsDisk/cvs/llvm/utils/TableGen/FileParser.y"
+case 42:
+#line 433 "/Volumes/ProjectsDisk/cvs/llvm/utils/TableGen/FileParser.y"
 {
     yyvsp[0].IntVal = -yyvsp[0].IntVal;
     if (yyvsp[-1].IntVal < 0 || yyvsp[0].IntVal < 0) {
@@ -1380,45 +1378,45 @@
     }
   ;
     break;}
-case 42:
-#line 459 "/Volumes/ProjectsDisk/cvs/llvm/utils/TableGen/FileParser.y"
+case 43:
+#line 449 "/Volumes/ProjectsDisk/cvs/llvm/utils/TableGen/FileParser.y"
 { yyval.BitList = yyvsp[0].BitList; std::reverse(yyvsp[0].BitList->begin(), yyvsp[0].BitList->end()); ;
     break;}
-case 43:
-#line 461 "/Volumes/ProjectsDisk/cvs/llvm/utils/TableGen/FileParser.y"
+case 44:
+#line 451 "/Volumes/ProjectsDisk/cvs/llvm/utils/TableGen/FileParser.y"
 { yyval.BitList = 0; ;
     break;}
-case 44:
-#line 461 "/Volumes/ProjectsDisk/cvs/llvm/utils/TableGen/FileParser.y"
+case 45:
+#line 451 "/Volumes/ProjectsDisk/cvs/llvm/utils/TableGen/FileParser.y"
 { yyval.BitList = yyvsp[-1].BitList; ;
     break;}
-case 45:
-#line 465 "/Volumes/ProjectsDisk/cvs/llvm/utils/TableGen/FileParser.y"
+case 46:
+#line 455 "/Volumes/ProjectsDisk/cvs/llvm/utils/TableGen/FileParser.y"
 {
     yyval.FieldList = new std::vector<Init*>();
   ;
     break;}
-case 46:
-#line 467 "/Volumes/ProjectsDisk/cvs/llvm/utils/TableGen/FileParser.y"
+case 47:
+#line 457 "/Volumes/ProjectsDisk/cvs/llvm/utils/TableGen/FileParser.y"
 {
     yyval.FieldList = yyvsp[0].FieldList;
   ;
     break;}
-case 47:
-#line 471 "/Volumes/ProjectsDisk/cvs/llvm/utils/TableGen/FileParser.y"
+case 48:
+#line 461 "/Volumes/ProjectsDisk/cvs/llvm/utils/TableGen/FileParser.y"
 {
     yyval.FieldList = new std::vector<Init*>();
     yyval.FieldList->push_back(yyvsp[0].Initializer);
   ;
     break;}
-case 48:
-#line 474 "/Volumes/ProjectsDisk/cvs/llvm/utils/TableGen/FileParser.y"
+case 49:
+#line 464 "/Volumes/ProjectsDisk/cvs/llvm/utils/TableGen/FileParser.y"
 {
     (yyval.FieldList = yyvsp[-2].FieldList)->push_back(yyvsp[0].Initializer);
   ;
     break;}
-case 49:
-#line 478 "/Volumes/ProjectsDisk/cvs/llvm/utils/TableGen/FileParser.y"
+case 50:
+#line 468 "/Volumes/ProjectsDisk/cvs/llvm/utils/TableGen/FileParser.y"
 {
   std::string DecName = *yyvsp[-1].StrVal;
   if (ParsingTemplateArgs)
@@ -1429,87 +1427,87 @@
   yyval.StrVal = new std::string(DecName);
 ;
     break;}
-case 50:
-#line 488 "/Volumes/ProjectsDisk/cvs/llvm/utils/TableGen/FileParser.y"
+case 51:
+#line 478 "/Volumes/ProjectsDisk/cvs/llvm/utils/TableGen/FileParser.y"
 {
   delete yyvsp[-1].StrVal;
 ;
     break;}
-case 51:
-#line 490 "/Volumes/ProjectsDisk/cvs/llvm/utils/TableGen/FileParser.y"
+case 52:
+#line 480 "/Volumes/ProjectsDisk/cvs/llvm/utils/TableGen/FileParser.y"
 {
   setValue(*yyvsp[-4].StrVal, yyvsp[-3].BitList, yyvsp[-1].Initializer);
   delete yyvsp[-4].StrVal;
   delete yyvsp[-3].BitList;
 ;
     break;}
-case 56:
-#line 499 "/Volumes/ProjectsDisk/cvs/llvm/utils/TableGen/FileParser.y"
+case 57:
+#line 489 "/Volumes/ProjectsDisk/cvs/llvm/utils/TableGen/FileParser.y"
 {
     yyval.SubClassRef = new SubClassRefTy(yyvsp[0].Rec, new std::vector<Init*>());
   ;
     break;}
-case 57:
-#line 501 "/Volumes/ProjectsDisk/cvs/llvm/utils/TableGen/FileParser.y"
+case 58:
+#line 491 "/Volumes/ProjectsDisk/cvs/llvm/utils/TableGen/FileParser.y"
 {
     yyval.SubClassRef = new SubClassRefTy(yyvsp[-3].Rec, yyvsp[-1].FieldList);
   ;
     break;}
-case 58:
-#line 505 "/Volumes/ProjectsDisk/cvs/llvm/utils/TableGen/FileParser.y"
+case 59:
+#line 495 "/Volumes/ProjectsDisk/cvs/llvm/utils/TableGen/FileParser.y"
 {
     yyval.SubClassList = new std::vector<SubClassRefTy>();
     yyval.SubClassList->push_back(*yyvsp[0].SubClassRef);
     delete yyvsp[0].SubClassRef;
   ;
     break;}
-case 59:
-#line 510 "/Volumes/ProjectsDisk/cvs/llvm/utils/TableGen/FileParser.y"
+case 60:
+#line 500 "/Volumes/ProjectsDisk/cvs/llvm/utils/TableGen/FileParser.y"
 {
     (yyval.SubClassList=yyvsp[-2].SubClassList)->push_back(*yyvsp[0].SubClassRef);
     delete yyvsp[0].SubClassRef;
   ;
     break;}
-case 60:
-#line 515 "/Volumes/ProjectsDisk/cvs/llvm/utils/TableGen/FileParser.y"
+case 61:
+#line 505 "/Volumes/ProjectsDisk/cvs/llvm/utils/TableGen/FileParser.y"
 {
     yyval.SubClassList = new std::vector<SubClassRefTy>();
   ;
     break;}
-case 61:
-#line 518 "/Volumes/ProjectsDisk/cvs/llvm/utils/TableGen/FileParser.y"
+case 62:
+#line 508 "/Volumes/ProjectsDisk/cvs/llvm/utils/TableGen/FileParser.y"
 {
     yyval.SubClassList = yyvsp[0].SubClassList;
   ;
     break;}
-case 62:
-#line 522 "/Volumes/ProjectsDisk/cvs/llvm/utils/TableGen/FileParser.y"
+case 63:
+#line 512 "/Volumes/ProjectsDisk/cvs/llvm/utils/TableGen/FileParser.y"
 {
   CurRec->addTemplateArg(*yyvsp[0].StrVal);
   delete yyvsp[0].StrVal;
 ;
     break;}
-case 63:
-#line 525 "/Volumes/ProjectsDisk/cvs/llvm/utils/TableGen/FileParser.y"
+case 64:
+#line 515 "/Volumes/ProjectsDisk/cvs/llvm/utils/TableGen/FileParser.y"
 {
   CurRec->addTemplateArg(*yyvsp[0].StrVal);
   delete yyvsp[0].StrVal;
 ;
     break;}
-case 64:
-#line 530 "/Volumes/ProjectsDisk/cvs/llvm/utils/TableGen/FileParser.y"
+case 65:
+#line 520 "/Volumes/ProjectsDisk/cvs/llvm/utils/TableGen/FileParser.y"
 {;
     break;}
-case 67:
-#line 533 "/Volumes/ProjectsDisk/cvs/llvm/utils/TableGen/FileParser.y"
+case 68:
+#line 523 "/Volumes/ProjectsDisk/cvs/llvm/utils/TableGen/FileParser.y"
 { yyval.StrVal = yyvsp[0].StrVal; ;
     break;}
-case 68:
-#line 533 "/Volumes/ProjectsDisk/cvs/llvm/utils/TableGen/FileParser.y"
+case 69:
+#line 523 "/Volumes/ProjectsDisk/cvs/llvm/utils/TableGen/FileParser.y"
 { yyval.StrVal = new std::string(); ;
     break;}
-case 69:
-#line 535 "/Volumes/ProjectsDisk/cvs/llvm/utils/TableGen/FileParser.y"
+case 70:
+#line 525 "/Volumes/ProjectsDisk/cvs/llvm/utils/TableGen/FileParser.y"
 {
   static unsigned AnonCounter = 0;
   if (yyvsp[0].StrVal->empty())
@@ -1517,8 +1515,8 @@
   yyval.StrVal = yyvsp[0].StrVal;
 ;
     break;}
-case 70:
-#line 542 "/Volumes/ProjectsDisk/cvs/llvm/utils/TableGen/FileParser.y"
+case 71:
+#line 532 "/Volumes/ProjectsDisk/cvs/llvm/utils/TableGen/FileParser.y"
 {
   // If a class of this name already exists, it must be a forward ref.
   if ((CurRec = Records.getClass(*yyvsp[0].StrVal))) {
@@ -1537,8 +1535,8 @@
   delete yyvsp[0].StrVal;
 ;
     break;}
-case 71:
-#line 560 "/Volumes/ProjectsDisk/cvs/llvm/utils/TableGen/FileParser.y"
+case 72:
+#line 550 "/Volumes/ProjectsDisk/cvs/llvm/utils/TableGen/FileParser.y"
 {
   CurRec = new Record(*yyvsp[0].StrVal);
   delete yyvsp[0].StrVal;
@@ -1551,8 +1549,8 @@
   Records.addDef(CurRec);
 ;
     break;}
-case 72:
-#line 572 "/Volumes/ProjectsDisk/cvs/llvm/utils/TableGen/FileParser.y"
+case 73:
+#line 562 "/Volumes/ProjectsDisk/cvs/llvm/utils/TableGen/FileParser.y"
 {
            for (unsigned i = 0, e = yyvsp[0].SubClassList->size(); i != e; ++i) {
              addSubClass((*yyvsp[0].SubClassList)[i].first, *(*yyvsp[0].SubClassList)[i].second);
@@ -1569,33 +1567,33 @@
                         LetStack[i][j].Value);
          ;
     break;}
-case 73:
-#line 586 "/Volumes/ProjectsDisk/cvs/llvm/utils/TableGen/FileParser.y"
+case 74:
+#line 576 "/Volumes/ProjectsDisk/cvs/llvm/utils/TableGen/FileParser.y"
 {
            yyval.Rec = CurRec;
            CurRec = 0;
          ;
     break;}
-case 74:
-#line 591 "/Volumes/ProjectsDisk/cvs/llvm/utils/TableGen/FileParser.y"
+case 75:
+#line 581 "/Volumes/ProjectsDisk/cvs/llvm/utils/TableGen/FileParser.y"
 {
                 ParsingTemplateArgs = true;
             ;
     break;}
-case 75:
-#line 593 "/Volumes/ProjectsDisk/cvs/llvm/utils/TableGen/FileParser.y"
+case 76:
+#line 583 "/Volumes/ProjectsDisk/cvs/llvm/utils/TableGen/FileParser.y"
 {
                 ParsingTemplateArgs = false;
             ;
     break;}
-case 76:
-#line 595 "/Volumes/ProjectsDisk/cvs/llvm/utils/TableGen/FileParser.y"
+case 77:
+#line 585 "/Volumes/ProjectsDisk/cvs/llvm/utils/TableGen/FileParser.y"
 {
         yyval.Rec = yyvsp[0].Rec;
      ;
     break;}
-case 77:
-#line 599 "/Volumes/ProjectsDisk/cvs/llvm/utils/TableGen/FileParser.y"
+case 78:
+#line 589 "/Volumes/ProjectsDisk/cvs/llvm/utils/TableGen/FileParser.y"
 {
   yyvsp[0].Rec->resolveReferences();
 
@@ -1604,39 +1602,39 @@
   yyval.Rec = yyvsp[0].Rec;
 ;
     break;}
-case 80:
-#line 610 "/Volumes/ProjectsDisk/cvs/llvm/utils/TableGen/FileParser.y"
+case 81:
+#line 600 "/Volumes/ProjectsDisk/cvs/llvm/utils/TableGen/FileParser.y"
 {
   LetStack.back().push_back(LetRecord(*yyvsp[-3].StrVal, yyvsp[-2].BitList, yyvsp[0].Initializer));
   delete yyvsp[-3].StrVal; delete yyvsp[-2].BitList;
 ;
     break;}
-case 83:
-#line 618 "/Volumes/ProjectsDisk/cvs/llvm/utils/TableGen/FileParser.y"
+case 84:
+#line 608 "/Volumes/ProjectsDisk/cvs/llvm/utils/TableGen/FileParser.y"
 { LetStack.push_back(std::vector<LetRecord>()); ;
     break;}
-case 85:
-#line 621 "/Volumes/ProjectsDisk/cvs/llvm/utils/TableGen/FileParser.y"
+case 86:
+#line 611 "/Volumes/ProjectsDisk/cvs/llvm/utils/TableGen/FileParser.y"
 {
     LetStack.pop_back();
   ;
     break;}
-case 86:
-#line 624 "/Volumes/ProjectsDisk/cvs/llvm/utils/TableGen/FileParser.y"
+case 87:
+#line 614 "/Volumes/ProjectsDisk/cvs/llvm/utils/TableGen/FileParser.y"
 {
     LetStack.pop_back();
   ;
     break;}
-case 87:
-#line 628 "/Volumes/ProjectsDisk/cvs/llvm/utils/TableGen/FileParser.y"
-{;
-    break;}
 case 88:
-#line 628 "/Volumes/ProjectsDisk/cvs/llvm/utils/TableGen/FileParser.y"
+#line 618 "/Volumes/ProjectsDisk/cvs/llvm/utils/TableGen/FileParser.y"
 {;
     break;}
 case 89:
-#line 630 "/Volumes/ProjectsDisk/cvs/llvm/utils/TableGen/FileParser.y"
+#line 618 "/Volumes/ProjectsDisk/cvs/llvm/utils/TableGen/FileParser.y"
+{;
+    break;}
+case 90:
+#line 620 "/Volumes/ProjectsDisk/cvs/llvm/utils/TableGen/FileParser.y"
 {;
     break;}
 }
@@ -1861,7 +1859,7 @@
     }
   return 1;
 }
-#line 632 "/Volumes/ProjectsDisk/cvs/llvm/utils/TableGen/FileParser.y"
+#line 622 "/Volumes/ProjectsDisk/cvs/llvm/utils/TableGen/FileParser.y"
 
 
 int yyerror(const char *ErrorMsg) {


Index: llvm/utils/TableGen/FileParser.h.cvs
diff -u llvm/utils/TableGen/FileParser.h.cvs:1.2 llvm/utils/TableGen/FileParser.h.cvs:1.3
--- llvm/utils/TableGen/FileParser.h.cvs:1.2	Thu Mar 30 16:51:12 2006
+++ llvm/utils/TableGen/FileParser.h.cvs	Fri Mar 31 15:54:11 2006
@@ -25,11 +25,12 @@
 #define	SHLTOK	269
 #define	SRATOK	270
 #define	SRLTOK	271
-#define	INTVAL	272
-#define	ID	273
-#define	VARNAME	274
-#define	STRVAL	275
-#define	CODEFRAGMENT	276
+#define	STRCONCATTOK	272
+#define	INTVAL	273
+#define	ID	274
+#define	VARNAME	275
+#define	STRVAL	276
+#define	CODEFRAGMENT	277
 
 
 extern YYSTYPE Filelval;


Index: llvm/utils/TableGen/FileParser.y.cvs
diff -u llvm/utils/TableGen/FileParser.y.cvs:1.2 llvm/utils/TableGen/FileParser.y.cvs:1.3
--- llvm/utils/TableGen/FileParser.y.cvs:1.2	Thu Mar 30 16:51:12 2006
+++ llvm/utils/TableGen/FileParser.y.cvs	Fri Mar 31 15:54:11 2006
@@ -200,7 +200,7 @@
 };
 
 %token INT BIT STRING BITS LIST CODE DAG CLASS DEF FIELD LET IN
-%token SHLTOK SRATOK SRLTOK
+%token SHLTOK SRATOK SRLTOK STRCONCATTOK
 %token <IntVal>      INTVAL
 %token <StrVal>      ID VARNAME STRVAL CODEFRAGMENT
 
@@ -352,23 +352,13 @@
     }
     delete $3;
   } | SHLTOK '(' Value ',' Value ')' {
-    $$ = $3->getBinaryOp(Init::SHL, $5);
-    if ($$ == 0) {
-      err() << "Cannot shift values '" << *$3 << "' and '" << *$5 << "'!\n";
-      exit(1);
-    }
+    $$ = (new BinOpInit(BinOpInit::SHL, $3, $5))->Fold();
   } | SRATOK '(' Value ',' Value ')' {
-    $$ = $3->getBinaryOp(Init::SRA, $5);
-    if ($$ == 0) {
-      err() << "Cannot shift values '" << *$3 << "' and '" << *$5 << "'!\n";
-      exit(1);
-    }
+    $$ = (new BinOpInit(BinOpInit::SRA, $3, $5))->Fold();
   } | SRLTOK '(' Value ',' Value ')' {
-    $$ = $3->getBinaryOp(Init::SRL, $5);
-    if ($$ == 0) {
-      err() << "Cannot shift values '" << *$3 << "' and '" << *$5 << "'!\n";
-      exit(1);
-    }
+    $$ = (new BinOpInit(BinOpInit::SRL, $3, $5))->Fold();
+  } | STRCONCATTOK '(' Value ',' Value ')' {
+    $$ = (new BinOpInit(BinOpInit::STRCONCAT, $3, $5))->Fold();
   };
 
 OptVarName : /* empty */ {





From evan.cheng at apple.com  Fri Mar 31 15:55:36 2006
From: evan.cheng at apple.com (Evan Cheng)
Date: Fri, 31 Mar 2006 15:55:36 -0600
Subject: [llvm-commits] CVS: llvm/lib/Target/X86/X86ISelLowering.cpp
	X86ISelLowering.h X86InstrSSE.td 
Message-ID: <200603312155.PAA31245@zion.cs.uiuc.edu>



Changes in directory llvm/lib/Target/X86:

X86ISelLowering.cpp updated: 1.150 -> 1.151
X86ISelLowering.h updated: 1.49 -> 1.50
X86InstrSSE.td updated: 1.52 -> 1.53
---
Log message:

Use a X86 target specific node X86ISD::PINSRW instead of a mal-formed 
INSERT_VECTOR_ELT to insert a 16-bit value in a 128-bit vector.


---
Diffs of the changes:  (+12 -6)

 X86ISelLowering.cpp |    3 ++-
 X86ISelLowering.h   |    6 +++++-
 X86InstrSSE.td      |    9 +++++----
 3 files changed, 12 insertions(+), 6 deletions(-)


Index: llvm/lib/Target/X86/X86ISelLowering.cpp
diff -u llvm/lib/Target/X86/X86ISelLowering.cpp:1.150 llvm/lib/Target/X86/X86ISelLowering.cpp:1.151
--- llvm/lib/Target/X86/X86ISelLowering.cpp:1.150	Fri Mar 31 13:22:53 2006
+++ llvm/lib/Target/X86/X86ISelLowering.cpp	Fri Mar 31 15:55:24 2006
@@ -2685,7 +2685,7 @@
         N1 = DAG.getNode(ISD::ANY_EXTEND, MVT::i32, N1);
       if (N2.getValueType() != MVT::i32)
         N2 = DAG.getConstant(cast<ConstantSDNode>(N2)->getValue(), MVT::i32);
-      return DAG.getNode(ISD::INSERT_VECTOR_ELT, VT, Op.getOperand(0), N1, N2);
+      return DAG.getNode(X86ISD::PINSRW, VT, Op.getOperand(0), N1, N2);
     }
 
     return SDOperand();
@@ -2726,6 +2726,7 @@
   case X86ISD::S2VEC:              return "X86ISD::S2VEC";
   case X86ISD::ZEXT_S2VEC:         return "X86ISD::ZEXT_S2VEC";
   case X86ISD::PEXTRW:             return "X86ISD::PEXTRW";
+  case X86ISD::PINSRW:             return "X86ISD::PINSRW";
   }
 }
 


Index: llvm/lib/Target/X86/X86ISelLowering.h
diff -u llvm/lib/Target/X86/X86ISelLowering.h:1.49 llvm/lib/Target/X86/X86ISelLowering.h:1.50
--- llvm/lib/Target/X86/X86ISelLowering.h:1.49	Fri Mar 31 13:22:53 2006
+++ llvm/lib/Target/X86/X86ISelLowering.h	Fri Mar 31 15:55:24 2006
@@ -155,8 +155,12 @@
       ZEXT_S2VEC,
 
       /// PEXTRW - Extract a 16-bit value from a vector and zero extend it to
-      /// i32, corresponds to X86::PINSRW.
+      /// i32, corresponds to X86::PEXTRW.
       PEXTRW,
+
+      /// PINSRW - Insert the lower 16-bits of a 32-bit value to a vector,
+      /// corresponds to X86::PINSRW.
+      PINSRW,
     };
 
     // X86 specific condition code. These correspond to X86_*_COND in


Index: llvm/lib/Target/X86/X86InstrSSE.td
diff -u llvm/lib/Target/X86/X86InstrSSE.td:1.52 llvm/lib/Target/X86/X86InstrSSE.td:1.53
--- llvm/lib/Target/X86/X86InstrSSE.td:1.52	Fri Mar 31 15:29:33 2006
+++ llvm/lib/Target/X86/X86InstrSSE.td	Fri Mar 31 15:55:24 2006
@@ -27,9 +27,10 @@
                         SDTypeProfile<1, 1, []>, []>;
 def X86zexts2vec : SDNode<"X86ISD::ZEXT_S2VEC",
                           SDTypeProfile<1, 1, []>, []>;
-
 def X86pextrw  : SDNode<"X86ISD::PEXTRW",
                         SDTypeProfile<1, 2, []>, []>;
+def X86pinsrw  : SDNode<"X86ISD::PINSRW",
+                        SDTypeProfile<1, 3, []>, []>;
 
 //===----------------------------------------------------------------------===//
 // SSE pattern fragments
@@ -1468,13 +1469,13 @@
 def PINSRWrr : PDIi8<0xC4, MRMSrcReg,
                      (ops VR128:$dst, VR128:$src1, R32:$src2, i32i8imm:$src3),
                      "pinsrw {$src3, $src2, $dst|$dst, $src2, $src3}",
-                     [(set VR128:$dst, (v8i16 (vector_insert (v8i16 VR128:$src1),
-                               R32:$src2, (i32 imm:$src3))))]>;
+                     [(set VR128:$dst, (v8i16 (X86pinsrw (v8i16 VR128:$src1),
+                                               R32:$src2, (i32 imm:$src3))))]>;
 def PINSRWrm : PDIi8<0xC4, MRMSrcMem,
                      (ops VR128:$dst, VR128:$src1, i16mem:$src2, i32i8imm:$src3),
                      "pinsrw {$src3, $src2, $dst|$dst, $src2, $src3}",
                      [(set VR128:$dst,
-                       (v8i16 (vector_insert (v8i16 VR128:$src1),
+                       (v8i16 (X86pinsrw (v8i16 VR128:$src1),
                                (i32 (anyext (loadi16 addr:$src2))),
                                (i32 imm:$src3))))]>;
 }





From lattner at cs.uiuc.edu  Fri Mar 31 15:57:48 2006
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Fri, 31 Mar 2006 15:57:48 -0600
Subject: [llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCInstrAltivec.td 
Message-ID: <200603312157.PAA31328@zion.cs.uiuc.edu>



Changes in directory llvm/lib/Target/PowerPC:

PPCInstrAltivec.td updated: 1.26 -> 1.27
---
Log message:

Fix 80 column violations :)


---
Diffs of the changes:  (+13 -14)

 PPCInstrAltivec.td |   27 +++++++++++++--------------
 1 files changed, 13 insertions(+), 14 deletions(-)


Index: llvm/lib/Target/PowerPC/PPCInstrAltivec.td
diff -u llvm/lib/Target/PowerPC/PPCInstrAltivec.td:1.26 llvm/lib/Target/PowerPC/PPCInstrAltivec.td:1.27
--- llvm/lib/Target/PowerPC/PPCInstrAltivec.td:1.26	Fri Mar 31 15:19:06 2006
+++ llvm/lib/Target/PowerPC/PPCInstrAltivec.td	Fri Mar 31 15:57:36 2006
@@ -64,8 +64,9 @@
 // Helpers for defining instructions that directly correspond to intrinsics.
 
 // VA1a_Int - A VAForm_1a intrinsic definition.
-class VA1a_Int<bits<6> xo, string asmstr, Intrinsic IntID>
-  : VAForm_1a<xo, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB, VRRC:$vC), asmstr, VecFP,
+class VA1a_Int<bits<6> xo, string opc, Intrinsic IntID>
+  : VAForm_1a<xo, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB, VRRC:$vC),
+              !strconcat(opc, " $vD, $vA, $vB, $vC"), VecFP,
                        [(set VRRC:$vD, (IntID VRRC:$vA, VRRC:$vB, VRRC:$vC))]>;
 
 // VX1_Int - A VXForm_1 intrinsic definition.
@@ -141,12 +142,10 @@
                        [(set VRRC:$vD, (fneg (fsub (fmul VRRC:$vA, VRRC:$vC),
                                                    VRRC:$vB)))]>,
                        Requires<[FPContractions]>;
-def VMHADDSHS  : VA1a_Int<32, "vmhaddshs $vD, $vA, $vB, $vC",
-                          int_ppc_altivec_vmhaddshs>;
-def VMHRADDSHS : VA1a_Int<33, "vmhraddshs $vD, $vA, $vB, $vC", 
-                          int_ppc_altivec_vmhraddshs>;
-def VPERM   : VA1a_Int<43, "vperm $vD, $vA, $vB, $vC", int_ppc_altivec_vperm>;
-def VSEL    : VA1a_Int<42, "vsel $vD, $vA, $vB, $vC",  int_ppc_altivec_vsel>;
+def VMHADDSHS  : VA1a_Int<32, "vmhaddshs",  int_ppc_altivec_vmhaddshs>;
+def VMHRADDSHS : VA1a_Int<33, "vmhraddshs", int_ppc_altivec_vmhraddshs>;
+def VPERM      : VA1a_Int<43, "vperm",      int_ppc_altivec_vperm>;
+def VSEL       : VA1a_Int<42, "vsel",       int_ppc_altivec_vsel>;
 
 def VSLDOI  : VAForm_2<44, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB, u5imm:$SH),
                        "vsldoi $vD, $vA, $vB, $SH", VecFP,
@@ -237,12 +236,12 @@
 def VMRGLH : VX1_Int<332, "vmrglh $vD, $vA, $vB", int_ppc_altivec_vmrglh>;
 def VMRGLW : VX1_Int<396, "vmrglw $vD, $vA, $vB", int_ppc_altivec_vmrglw>;
 
-def VMSUMMBM : VA1a_Int<37, "vmsummbm $vD, $vA, $vB, $vC", int_ppc_altivec_vmsummbm>;
-def VMSUMSHM : VA1a_Int<40, "vmsumshm $vD, $vA, $vB, $vC", int_ppc_altivec_vmsumshm>;
-def VMSUMSHS : VA1a_Int<41, "vmsumshs $vD, $vA, $vB, $vC", int_ppc_altivec_vmsumshs>;
-def VMSUMUBM : VA1a_Int<36, "vmsumubm $vD, $vA, $vB, $vC", int_ppc_altivec_vmsumubm>;
-def VMSUMUHM : VA1a_Int<38, "vmsumuhm $vD, $vA, $vB, $vC", int_ppc_altivec_vmsumuhm>;
-def VMSUMUHS : VA1a_Int<39, "vmsumuhs $vD, $vA, $vB, $vC", int_ppc_altivec_vmsumuhs>;
+def VMSUMMBM : VA1a_Int<37, "vmsummbm", int_ppc_altivec_vmsummbm>;
+def VMSUMSHM : VA1a_Int<40, "vmsumshm", int_ppc_altivec_vmsumshm>;
+def VMSUMSHS : VA1a_Int<41, "vmsumshs", int_ppc_altivec_vmsumshs>;
+def VMSUMUBM : VA1a_Int<36, "vmsumubm", int_ppc_altivec_vmsumubm>;
+def VMSUMUHM : VA1a_Int<38, "vmsumuhm", int_ppc_altivec_vmsumuhm>;
+def VMSUMUHS : VA1a_Int<39, "vmsumuhs", int_ppc_altivec_vmsumuhs>;
 
 def VMULESB : VX1_Int<776, "vmulesb $vD, $vA, $vB", int_ppc_altivec_vmulesb>;
 def VMULESH : VX1_Int<840, "vmulesh $vD, $vA, $vB", int_ppc_altivec_vmulesh>;





From lattner at cs.uiuc.edu  Fri Mar 31 16:16:30 2006
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Fri, 31 Mar 2006 16:16:30 -0600
Subject: [llvm-commits] 
	CVS: llvm/test/Regression/CodeGen/Generic/vector-identity-shuffle.ll
Message-ID: <200603312216.QAA32250@zion.cs.uiuc.edu>



Changes in directory llvm/test/Regression/CodeGen/Generic:

vector-identity-shuffle.ll added (r1.1)
---
Log message:

An identity shuffle shouldn't generate any permute code.


---
Diffs of the changes:  (+16 -0)

 vector-identity-shuffle.ll |   16 ++++++++++++++++
 1 files changed, 16 insertions(+)


Index: llvm/test/Regression/CodeGen/Generic/vector-identity-shuffle.ll
diff -c /dev/null llvm/test/Regression/CodeGen/Generic/vector-identity-shuffle.ll:1.1
*** /dev/null	Fri Mar 31 16:16:29 2006
--- llvm/test/Regression/CodeGen/Generic/vector-identity-shuffle.ll	Fri Mar 31 16:16:19 2006
***************
*** 0 ****
--- 1,16 ----
+ ; RUN: llvm-as < %s | llc -march=ppc32 -mcpu=g5 | grep _test &&
+ ; RUN: llvm-as < %s | llc -march=ppc32 -mcpu=g5 | not grep vperm
+ 
+ void %test(<4 x float> *%tmp2.i) {
+ 	%tmp2.i = load <4x float>* %tmp2.i
+        %xFloat0.48 = extractelement <4 x float> %tmp2.i, uint 0                ; <float> [#uses=1]
+         %inFloat0.49 = insertelement <4 x float> undef, float %xFloat0.48, uint 0               ; <<4 x float>> [#uses=1]
+         %xFloat1.50 = extractelement <4 x float> %tmp2.i, uint 1                ; <float> [#uses=1]
+         %inFloat1.52 = insertelement <4 x float> %inFloat0.49, float %xFloat1.50, uint 1                ; <<4 x float>> [#uses=1]
+         %xFloat2.53 = extractelement <4 x float> %tmp2.i, uint 2                ; <float> [#uses=1]
+         %inFloat2.55 = insertelement <4 x float> %inFloat1.52, float %xFloat2.53, uint 2                ; <<4 x float>> [#uses=1]
+         %xFloat3.56 = extractelement <4 x float> %tmp2.i, uint 3                ; <float> [#uses=1]
+         %inFloat3.58 = insertelement <4 x float> %inFloat2.55, float %xFloat3.56, uint 3                ; <<4 x float>> [#uses=4]
+ 	store <4 x float> %inFloat3.58, <4x float>* %tmp2.i
+ 	ret void
+ }





From lattner at cs.uiuc.edu  Fri Mar 31 16:16:56 2006
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Fri, 31 Mar 2006 16:16:56 -0600
Subject: [llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp 
Message-ID: <200603312216.QAA32285@zion.cs.uiuc.edu>



Changes in directory llvm/lib/CodeGen/SelectionDAG:

DAGCombiner.cpp updated: 1.135 -> 1.136
---
Log message:

Delete identity shuffles, implementing CodeGen/Generic/vector-identity-shuffle.ll


---
Diffs of the changes:  (+56 -2)

 DAGCombiner.cpp |   58 ++++++++++++++++++++++++++++++++++++++++++++++++++++++--
 1 files changed, 56 insertions(+), 2 deletions(-)


Index: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.135 llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.136
--- llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.135	Fri Mar 31 12:10:41 2006
+++ llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp	Fri Mar 31 16:16:43 2006
@@ -214,6 +214,7 @@
     SDOperand visitVINSERT_VECTOR_ELT(SDNode *N);
     SDOperand visitVBUILD_VECTOR(SDNode *N);
     SDOperand visitVECTOR_SHUFFLE(SDNode *N);
+    SDOperand visitVVECTOR_SHUFFLE(SDNode *N);
 
     SDOperand ReassociateOps(unsigned Opc, SDOperand LHS, SDOperand RHS);
     
@@ -652,6 +653,7 @@
   case ISD::VINSERT_VECTOR_ELT: return visitVINSERT_VECTOR_ELT(N);
   case ISD::VBUILD_VECTOR:      return visitVBUILD_VECTOR(N);
   case ISD::VECTOR_SHUFFLE:     return visitVECTOR_SHUFFLE(N);
+  case ISD::VVECTOR_SHUFFLE:    return visitVVECTOR_SHUFFLE(N);
   }
   return SDOperand();
 }
@@ -2464,13 +2466,36 @@
 }
 
 SDOperand DAGCombiner::visitVECTOR_SHUFFLE(SDNode *N) {
+  SDOperand ShufMask = N->getOperand(2);
+  unsigned NumElts = ShufMask.getNumOperands();
+
+  // If the shuffle mask is an identity operation on the LHS, return the LHS.
+  bool isIdentity = true;
+  for (unsigned i = 0; i != NumElts; ++i) {
+    if (ShufMask.getOperand(i).getOpcode() != ISD::UNDEF &&
+        cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue() != i) {
+      isIdentity = false;
+      break;
+    }
+  }
+  if (isIdentity) return N->getOperand(0);
+
+  // If the shuffle mask is an identity operation on the RHS, return the RHS.
+  isIdentity = true;
+  for (unsigned i = 0; i != NumElts; ++i) {
+    if (ShufMask.getOperand(i).getOpcode() != ISD::UNDEF &&
+        cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue() != i+NumElts) {
+      isIdentity = false;
+      break;
+    }
+  }
+  if (isIdentity) return N->getOperand(1);
+  
   // If the LHS and the RHS are the same node, turn the RHS into an undef.
   if (N->getOperand(0) == N->getOperand(1)) {
     // Check the SHUFFLE mask, mapping any inputs from the 2nd operand into the
     // first operand.
     std::vector<SDOperand> MappedOps;
-    SDOperand ShufMask = N->getOperand(2);
-    unsigned NumElts = ShufMask.getNumOperands();
     for (unsigned i = 0, e = ShufMask.getNumOperands(); i != e; ++i) {
       if (cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue() >= NumElts) {
         unsigned NewIdx = 
@@ -2491,6 +2516,35 @@
   return SDOperand();
 }
 
+SDOperand DAGCombiner::visitVVECTOR_SHUFFLE(SDNode *N) {
+  SDOperand ShufMask = N->getOperand(2);
+  unsigned NumElts = ShufMask.getNumOperands()-2;
+  
+  // If the shuffle mask is an identity operation on the LHS, return the LHS.
+  bool isIdentity = true;
+  for (unsigned i = 0; i != NumElts; ++i) {
+    if (ShufMask.getOperand(i).getOpcode() != ISD::UNDEF &&
+        cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue() != i) {
+      isIdentity = false;
+      break;
+    }
+  }
+  if (isIdentity) return N->getOperand(0);
+  
+  // If the shuffle mask is an identity operation on the RHS, return the RHS.
+  isIdentity = true;
+  for (unsigned i = 0; i != NumElts; ++i) {
+    if (ShufMask.getOperand(i).getOpcode() != ISD::UNDEF &&
+        cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue() != i+NumElts) {
+      isIdentity = false;
+      break;
+    }
+  }
+  if (isIdentity) return N->getOperand(1);
+
+  return SDOperand();
+}
+
 SDOperand DAGCombiner::SimplifySelect(SDOperand N0, SDOperand N1, SDOperand N2){
   assert(N0.getOpcode() ==ISD::SETCC && "First argument must be a SetCC node!");
   





From alenhar2 at cs.uiuc.edu  Fri Mar 31 16:28:04 2006
From: alenhar2 at cs.uiuc.edu (Andrew Lenharth)
Date: Fri, 31 Mar 2006 16:28:04 -0600
Subject: [llvm-commits] 
	CVS: llvm-poolalloc/lib/PoolAllocate/TransformFunctionBody.cpp
Message-ID: <200603312228.QAA25450@apoc.cs.uiuc.edu>



Changes in directory llvm-poolalloc/lib/PoolAllocate:

TransformFunctionBody.cpp updated: 1.50 -> 1.51
---
Log message:

fall back on the complete call graph to get indirect targets if needed

---
Diffs of the changes:  (+9 -0)

 TransformFunctionBody.cpp |    9 +++++++++
 1 files changed, 9 insertions(+)


Index: llvm-poolalloc/lib/PoolAllocate/TransformFunctionBody.cpp
diff -u llvm-poolalloc/lib/PoolAllocate/TransformFunctionBody.cpp:1.50 llvm-poolalloc/lib/PoolAllocate/TransformFunctionBody.cpp:1.51
--- llvm-poolalloc/lib/PoolAllocate/TransformFunctionBody.cpp:1.50	Wed Jan 25 16:07:36 2006
+++ llvm-poolalloc/lib/PoolAllocate/TransformFunctionBody.cpp	Fri Mar 31 16:27:40 2006
@@ -509,6 +509,15 @@
       ECGraphs.getSomeCalleeForCallSite(cast<CallInst>(OrigInst)) :
       ECGraphs.getSomeCalleeForCallSite(cast<InvokeInst>(OrigInst));
 
+    if (!CF) 
+      for (EquivClassGraphs::callee_iterator I = ECGraphs.callee_begin(OrigInst), 
+	     E = ECGraphs.callee_end(OrigInst); I != E; ++I)
+	if (I->second) {
+	  CF = I->second;
+	  break;
+	}
+        
+
     if (!CF) {
       // FIXME: Unknown callees for a call-site. Warn and ignore.
       std::cerr << "\n***\n*** WARNING (FuncTransform::visitCallSite): "





From evan.cheng at apple.com  Fri Mar 31 16:33:54 2006
From: evan.cheng at apple.com (Evan Cheng)
Date: Fri, 31 Mar 2006 16:33:54 -0600
Subject: [llvm-commits] CVS: llvm/lib/Target/TargetData.cpp 
Message-ID: <200603312233.QAA32567@zion.cs.uiuc.edu>



Changes in directory llvm/lib/Target:

TargetData.cpp updated: 1.58 -> 1.59
---
Log message:

TargetData.cpp::getTypeInfo() was returning alignment of element type as the
alignment of a packed type. This is obviously wrong. Added a workaround that
returns the size of the packed type as its alignment. The correct fix would
be to return a target dependent alignment value provided via TargetLowering
(or some other interface).


---
Diffs of the changes:  (+3 -0)

 TargetData.cpp |    3 +++
 1 files changed, 3 insertions(+)


Index: llvm/lib/Target/TargetData.cpp
diff -u llvm/lib/Target/TargetData.cpp:1.58 llvm/lib/Target/TargetData.cpp:1.59
--- llvm/lib/Target/TargetData.cpp:1.58	Fri Jan 13 18:07:34 2006
+++ llvm/lib/Target/TargetData.cpp	Fri Mar 31 16:33:42 2006
@@ -215,6 +215,9 @@
     getTypeInfo(PTy->getElementType(), TD, Size, Alignment);
     unsigned AlignedSize = (Size + Alignment - 1)/Alignment*Alignment;
     Size = AlignedSize*PTy->getNumElements();
+    // FIXME: The alignments of specific packed types are target dependent.
+    // For now, just set it to be equal to Size.
+    Alignment = Size;
     return;
   }
   case Type::StructTyID: {





From lattner at cs.uiuc.edu  Fri Mar 31 16:34:17 2006
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Fri, 31 Mar 2006 16:34:17 -0600
Subject: [llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCInstrAltivec.td 
Message-ID: <200603312234.QAA32577@zion.cs.uiuc.edu>



Changes in directory llvm/lib/Target/PowerPC:

PPCInstrAltivec.td updated: 1.27 -> 1.28
---
Log message:

Pull operand asm string into base class, shrinkifying intrinsic definitions.

No functionality change.


---
Diffs of the changes:  (+58 -77)

 PPCInstrAltivec.td |  135 ++++++++++++++++++++++-------------------------------
 1 files changed, 58 insertions(+), 77 deletions(-)


Index: llvm/lib/Target/PowerPC/PPCInstrAltivec.td
diff -u llvm/lib/Target/PowerPC/PPCInstrAltivec.td:1.27 llvm/lib/Target/PowerPC/PPCInstrAltivec.td:1.28
--- llvm/lib/Target/PowerPC/PPCInstrAltivec.td:1.27	Fri Mar 31 15:57:36 2006
+++ llvm/lib/Target/PowerPC/PPCInstrAltivec.td	Fri Mar 31 16:34:05 2006
@@ -70,13 +70,15 @@
                        [(set VRRC:$vD, (IntID VRRC:$vA, VRRC:$vB, VRRC:$vC))]>;
 
 // VX1_Int - A VXForm_1 intrinsic definition.
-class VX1_Int<bits<11> xo, string asmstr, Intrinsic IntID>
-  : VXForm_1<xo, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB), asmstr, VecFP,
+class VX1_Int<bits<11> xo, string opc, Intrinsic IntID>
+  : VXForm_1<xo, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
+             !strconcat(opc, " $vD, $vA, $vB"), VecFP,
              [(set VRRC:$vD, (IntID VRRC:$vA, VRRC:$vB))]>;
 
 // VX2_Int - A VXForm_2 intrinsic definition.
-class VX2_Int<bits<11> xo, string asmstr, Intrinsic IntID>
-  : VXForm_2<xo, (ops VRRC:$vD, VRRC:$vB), asmstr, VecFP,
+class VX2_Int<bits<11> xo, string opc, Intrinsic IntID>
+  : VXForm_2<xo, (ops VRRC:$vD, VRRC:$vB),
+             !strconcat(opc, " $vD, $vB"), VecFP,
              [(set VRRC:$vD, (IntID VRRC:$vB))]>;
 
 //===----------------------------------------------------------------------===//
@@ -231,10 +233,10 @@
                       "vminfp $vD, $vA, $vB", VecFP,
                       []>;
 
-def VMRGHH : VX1_Int<76 , "vmrghh $vD, $vA, $vB", int_ppc_altivec_vmrghh>;
-def VMRGHW : VX1_Int<140, "vmrghw $vD, $vA, $vB", int_ppc_altivec_vmrghw>;
-def VMRGLH : VX1_Int<332, "vmrglh $vD, $vA, $vB", int_ppc_altivec_vmrglh>;
-def VMRGLW : VX1_Int<396, "vmrglw $vD, $vA, $vB", int_ppc_altivec_vmrglw>;
+def VMRGHH : VX1_Int<76 , "vmrghh", int_ppc_altivec_vmrghh>;
+def VMRGHW : VX1_Int<140, "vmrghw", int_ppc_altivec_vmrghw>;
+def VMRGLH : VX1_Int<332, "vmrglh", int_ppc_altivec_vmrglh>;
+def VMRGLW : VX1_Int<396, "vmrglw", int_ppc_altivec_vmrglw>;
 
 def VMSUMMBM : VA1a_Int<37, "vmsummbm", int_ppc_altivec_vmsummbm>;
 def VMSUMSHM : VA1a_Int<40, "vmsumshm", int_ppc_altivec_vmsumshm>;
@@ -243,23 +245,23 @@
 def VMSUMUHM : VA1a_Int<38, "vmsumuhm", int_ppc_altivec_vmsumuhm>;
 def VMSUMUHS : VA1a_Int<39, "vmsumuhs", int_ppc_altivec_vmsumuhs>;
 
-def VMULESB : VX1_Int<776, "vmulesb $vD, $vA, $vB", int_ppc_altivec_vmulesb>;
-def VMULESH : VX1_Int<840, "vmulesh $vD, $vA, $vB", int_ppc_altivec_vmulesh>;
-def VMULEUB : VX1_Int<520, "vmuleub $vD, $vA, $vB", int_ppc_altivec_vmuleub>;
-def VMULEUH : VX1_Int<584, "vmuleuh $vD, $vA, $vB", int_ppc_altivec_vmuleuh>;
-def VMULOSB : VX1_Int<264, "vmulosb $vD, $vA, $vB", int_ppc_altivec_vmulosb>;
-def VMULOSH : VX1_Int<328, "vmulosh $vD, $vA, $vB", int_ppc_altivec_vmulosh>;
-def VMULOUB : VX1_Int<  8, "vmuloub $vD, $vA, $vB", int_ppc_altivec_vmuloub>;
-def VMULOUH : VX1_Int< 72, "vmulouh $vD, $vA, $vB", int_ppc_altivec_vmulouh>;
+def VMULESB : VX1_Int<776, "vmulesb", int_ppc_altivec_vmulesb>;
+def VMULESH : VX1_Int<840, "vmulesh", int_ppc_altivec_vmulesh>;
+def VMULEUB : VX1_Int<520, "vmuleub", int_ppc_altivec_vmuleub>;
+def VMULEUH : VX1_Int<584, "vmuleuh", int_ppc_altivec_vmuleuh>;
+def VMULOSB : VX1_Int<264, "vmulosb", int_ppc_altivec_vmulosb>;
+def VMULOSH : VX1_Int<328, "vmulosh", int_ppc_altivec_vmulosh>;
+def VMULOUB : VX1_Int<  8, "vmuloub", int_ppc_altivec_vmuloub>;
+def VMULOUH : VX1_Int< 72, "vmulouh", int_ppc_altivec_vmulouh>;
                        
-def VREFP     : VX2_Int<266, "vrefp $vD, $vB",     int_ppc_altivec_vrefp>;
-def VRFIM     : VX2_Int<714, "vrfim $vD, $vB",     int_ppc_altivec_vrfim>;
-def VRFIN     : VX2_Int<522, "vrfin $vD, $vB",     int_ppc_altivec_vrfin>;
-def VRFIP     : VX2_Int<650, "vrfip $vD, $vB",     int_ppc_altivec_vrfip>;
-def VRFIZ     : VX2_Int<586, "vrfiz $vD, $vB",     int_ppc_altivec_vrfiz>;
-def VRSQRTEFP : VX2_Int<330, "vrsqrtefp $vD, $vB", int_ppc_altivec_vrsqrtefp>;
+def VREFP     : VX2_Int<266, "vrefp",     int_ppc_altivec_vrefp>;
+def VRFIM     : VX2_Int<714, "vrfim",     int_ppc_altivec_vrfim>;
+def VRFIN     : VX2_Int<522, "vrfin",     int_ppc_altivec_vrfin>;
+def VRFIP     : VX2_Int<650, "vrfip",     int_ppc_altivec_vrfip>;
+def VRFIZ     : VX2_Int<586, "vrfiz",     int_ppc_altivec_vrfiz>;
+def VRSQRTEFP : VX2_Int<330, "vrsqrtefp", int_ppc_altivec_vrsqrtefp>;
 
-def VSUBCUW : VX1_Int<74, "vsubcuw $vD, $vA, $vB", int_ppc_altivec_vsubcuw>;
+def VSUBCUW : VX1_Int<74, "vsubcuw", int_ppc_altivec_vsubcuw>;
 
 def VSUBFP  : VXForm_1<74, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
                       "vsubfp $vD, $vA, $vB", VecGeneral,
@@ -274,17 +276,17 @@
                       "vsubuwm $vD, $vA, $vB", VecGeneral,
                       [(set VRRC:$vD, (sub (v4i32 VRRC:$vA), VRRC:$vB))]>;
                       
-def VSUBSBS : VX1_Int<1792, "vsubsbs $vD, $vA, $vB", int_ppc_altivec_vsubsbs>;
-def VSUBSHS : VX1_Int<1856, "vsubshs $vD, $vA, $vB", int_ppc_altivec_vsubshs>;
-def VSUBSWS : VX1_Int<1920, "vsubsws $vD, $vA, $vB", int_ppc_altivec_vsubsws>;
-def VSUBUBS : VX1_Int<1536, "vsububs $vD, $vA, $vB", int_ppc_altivec_vsububs>;
-def VSUBUHS : VX1_Int<1600, "vsubuhs $vD, $vA, $vB", int_ppc_altivec_vsubuhs>;
-def VSUBUWS : VX1_Int<1664, "vsubuws $vD, $vA, $vB", int_ppc_altivec_vsubuws>;
-def VSUMSWS : VX1_Int<1928, "vsumsws $vD, $vA, $vB", int_ppc_altivec_vsumsws>;
-def VSUM2SWS: VX1_Int<1672, "vsum2sws $vD, $vA, $vB", int_ppc_altivec_vsum2sws>;
-def VSUM4SBS: VX1_Int<1672, "vsum4sbs $vD, $vA, $vB", int_ppc_altivec_vsum4sbs>;
-def VSUM4SHS: VX1_Int<1608, "vsum4shs $vD, $vA, $vB", int_ppc_altivec_vsum4shs>;
-def VSUM4UBS: VX1_Int<1544, "vsum4ubs $vD, $vA, $vB", int_ppc_altivec_vsum4ubs>;
+def VSUBSBS : VX1_Int<1792, "vsubsbs" , int_ppc_altivec_vsubsbs>;
+def VSUBSHS : VX1_Int<1856, "vsubshs" , int_ppc_altivec_vsubshs>;
+def VSUBSWS : VX1_Int<1920, "vsubsws" , int_ppc_altivec_vsubsws>;
+def VSUBUBS : VX1_Int<1536, "vsububs" , int_ppc_altivec_vsububs>;
+def VSUBUHS : VX1_Int<1600, "vsubuhs" , int_ppc_altivec_vsubuhs>;
+def VSUBUWS : VX1_Int<1664, "vsubuws" , int_ppc_altivec_vsubuws>;
+def VSUMSWS : VX1_Int<1928, "vsumsws" , int_ppc_altivec_vsumsws>;
+def VSUM2SWS: VX1_Int<1672, "vsum2sws", int_ppc_altivec_vsum2sws>;
+def VSUM4SBS: VX1_Int<1672, "vsum4sbs", int_ppc_altivec_vsum4sbs>;
+def VSUM4SHS: VX1_Int<1608, "vsum4shs", int_ppc_altivec_vsum4shs>;
+def VSUM4UBS: VX1_Int<1544, "vsum4ubs", int_ppc_altivec_vsum4ubs>;
 
 def VNOR : VXForm_1<1284, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
                     "vnor $vD, $vA, $vB", VecFP,
@@ -296,13 +298,13 @@
                       "vxor $vD, $vA, $vB", VecFP,
                       [(set VRRC:$vD, (xor (v4i32 VRRC:$vA), VRRC:$vB))]>;
 
-def VRLB   : VX1_Int<   4, "vrlb $vD, $vA, $vB", int_ppc_altivec_vrlb>;
-def VRLH   : VX1_Int<  68, "vrlh $vD, $vA, $vB", int_ppc_altivec_vrlh>;
-def VRLW   : VX1_Int< 132, "vrlw $vD, $vA, $vB", int_ppc_altivec_vrlw>;
-def VSLO   : VX1_Int<1036, "vslo $vD, $vA, $vB", int_ppc_altivec_vslo>;
-def VSLB   : VX1_Int< 260, "vslb $vD, $vA, $vB", int_ppc_altivec_vslb>;
-def VSLH   : VX1_Int< 324, "vslh $vD, $vA, $vB", int_ppc_altivec_vslh>;
-def VSLW   : VX1_Int< 388, "vslw $vD, $vA, $vB", int_ppc_altivec_vslw>;
+def VRLB   : VX1_Int<   4, "vrlb", int_ppc_altivec_vrlb>;
+def VRLH   : VX1_Int<  68, "vrlh", int_ppc_altivec_vrlh>;
+def VRLW   : VX1_Int< 132, "vrlw", int_ppc_altivec_vrlw>;
+def VSLO   : VX1_Int<1036, "vslo", int_ppc_altivec_vslo>;
+def VSLB   : VX1_Int< 260, "vslb", int_ppc_altivec_vslb>;
+def VSLH   : VX1_Int< 324, "vslh", int_ppc_altivec_vslh>;
+def VSLW   : VX1_Int< 388, "vslw", int_ppc_altivec_vslw>;
 
 def VSPLTB : VXForm_1<524, (ops VRRC:$vD, u5imm:$UIMM, VRRC:$vB),
                       "vspltb $vD, $vB, $UIMM", VecPerm,
@@ -315,14 +317,14 @@
                       [(set VRRC:$vD, (vector_shuffle (v4f32 VRRC:$vB), (undef),
                                       VSPLT_shuffle_mask:$UIMM))]>;
 
-def VSR    : VX1_Int< 708, "vsr $vD, $vA, $vB"  , int_ppc_altivec_vsr>;
-def VSRO   : VX1_Int<1100, "vsro $vD, $vA, $vB" , int_ppc_altivec_vsro>;
-def VSRAB  : VX1_Int< 772, "vsrab $vD, $vA, $vB", int_ppc_altivec_vsrab>;
-def VSRAH  : VX1_Int< 836, "vsrah $vD, $vA, $vB", int_ppc_altivec_vsrah>;
-def VSRAW  : VX1_Int< 900, "vsraw $vD, $vA, $vB", int_ppc_altivec_vsraw>;
-def VSRB   : VX1_Int< 516, "vsrb $vD, $vA, $vB" , int_ppc_altivec_vsrb>;
-def VSRH   : VX1_Int< 580, "vsrh $vD, $vA, $vB" , int_ppc_altivec_vsrh>;
-def VSRW   : VX1_Int< 644, "vsrw $vD, $vA, $vB" , int_ppc_altivec_vsrw>;
+def VSR    : VX1_Int< 708, "vsr"  , int_ppc_altivec_vsr>;
+def VSRO   : VX1_Int<1100, "vsro" , int_ppc_altivec_vsro>;
+def VSRAB  : VX1_Int< 772, "vsrab", int_ppc_altivec_vsrab>;
+def VSRAH  : VX1_Int< 836, "vsrah", int_ppc_altivec_vsrah>;
+def VSRAW  : VX1_Int< 900, "vsraw", int_ppc_altivec_vsraw>;
+def VSRB   : VX1_Int< 516, "vsrb" , int_ppc_altivec_vsrb>;
+def VSRH   : VX1_Int< 580, "vsrh" , int_ppc_altivec_vsrh>;
+def VSRW   : VX1_Int< 644, "vsrw" , int_ppc_altivec_vsrw>;
 
 
 def VSPLTISB : VXForm_3<780, (ops VRRC:$vD, s5imm:$SIMM),
@@ -336,40 +338,19 @@
                        [(set VRRC:$vD, (v4f32 vecspltisw:$SIMM))]>;
 
 // Vector Pack.
-def VPKPX   : VXForm_1<782, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
-                       "vpkpx $vD, $vA, $vB", VecFP,
-                       [(set VRRC:$vD,
-                            (int_ppc_altivec_vpkpx VRRC:$vA, VRRC:$vB))]>;
-def VPKSHSS : VXForm_1<398, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
-                       "vpkshss $vD, $vA, $vB", VecFP,
-                       [(set VRRC:$vD,
-                            (int_ppc_altivec_vpkshss VRRC:$vA, VRRC:$vB))]>;
-def VPKSHUS : VXForm_1<270, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
-                       "vpkshus $vD, $vA, $vB", VecFP,
-                       [(set VRRC:$vD,
-                            (int_ppc_altivec_vpkshus VRRC:$vA, VRRC:$vB))]>;
-def VPKSWSS : VXForm_1<462, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
-                       "vpkswss $vD, $vA, $vB", VecFP,
-                       [(set VRRC:$vD,
-                            (int_ppc_altivec_vpkswss VRRC:$vA, VRRC:$vB))]>;
-def VPKSWUS : VXForm_1<334, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
-                       "vpkswus $vD, $vA, $vB", VecFP,
-                       [(set VRRC:$vD,
-                            (int_ppc_altivec_vpkswus VRRC:$vA, VRRC:$vB))]>;
+def VPKPX   : VX1_Int<782, "vpkpx", int_ppc_altivec_vpkpx>;
+def VPKSHSS : VX1_Int<398, "vpkshss", int_ppc_altivec_vpkshss>;
+def VPKSHUS : VX1_Int<270, "vpkshus", int_ppc_altivec_vpkshus>;
+def VPKSWSS : VX1_Int<462, "vpkswss", int_ppc_altivec_vpkswss>;
+def VPKSWUS : VX1_Int<334, "vpkswus", int_ppc_altivec_vpkswus>;
 def VPKUHUM : VXForm_1<14, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
                        "vpkuhum $vD, $vA, $vB", VecFP,
                        [/*TODO*/]>;
-def VPKUHUS : VXForm_1<142, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
-                       "vpkuhus $vD, $vA, $vB", VecFP,
-                       [(set VRRC:$vD,
-                            (int_ppc_altivec_vpkuhus VRRC:$vA, VRRC:$vB))]>;
+def VPKUHUS : VX1_Int<142, "vpkuhus", int_ppc_altivec_vpkuhus>;
 def VPKUWUM : VXForm_1<78, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
                        "vpkuwum $vD, $vA, $vB", VecFP,
                        [/*TODO*/]>;
-def VPKUWUS : VXForm_1<206, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
-                       "vpkuwus $vD, $vA, $vB", VecFP,
-                       [(set VRRC:$vD,
-                            (int_ppc_altivec_vpkuwus VRRC:$vA, VRRC:$vB))]>;
+def VPKUWUS : VX1_Int<206, "vpkuwus", int_ppc_altivec_vpkuwus>;
 
 // Vector Unpack.
 def VUPKHPX : VXForm_2<846, (ops VRRC:$vD, VRRC:$vB),





From evan.cheng at apple.com  Fri Mar 31 16:35:27 2006
From: evan.cheng at apple.com (Evan Cheng)
Date: Fri, 31 Mar 2006 16:35:27 -0600
Subject: [llvm-commits] CVS: llvm/lib/Target/README.txt 
Message-ID: <200603312235.QAA32594@zion.cs.uiuc.edu>



Changes in directory llvm/lib/Target:

README.txt updated: 1.25 -> 1.26
---
Log message:

An entry about packed type alignments.


---
Diffs of the changes:  (+4 -0)

 README.txt |    4 ++++
 1 files changed, 4 insertions(+)


Index: llvm/lib/Target/README.txt
diff -u llvm/lib/Target/README.txt:1.25 llvm/lib/Target/README.txt:1.26
--- llvm/lib/Target/README.txt:1.25	Fri Mar 24 13:59:17 2006
+++ llvm/lib/Target/README.txt	Fri Mar 31 16:35:14 2006
@@ -149,4 +149,8 @@
 
 where c1/c2 are constants.
 
+//===---------------------------------------------------------------------===//
 
+For packed types, TargetData.cpp::getTypeInfo() returns alignment that is equal
+to the type size. It works but can be overly conservative as the alignment of
+specific packed types are target dependent.





From lattner at cs.uiuc.edu  Fri Mar 31 16:42:08 2006
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Fri, 31 Mar 2006 16:42:08 -0600
Subject: [llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCInstrAltivec.td 
Message-ID: <200603312242.QAA32681@zion.cs.uiuc.edu>



Changes in directory llvm/lib/Target/PowerPC:

PPCInstrAltivec.td updated: 1.28 -> 1.29
---
Log message:

Shrinkify some more intrinsic definitions.


---
Diffs of the changes:  (+17 -52)

 PPCInstrAltivec.td |   69 +++++++++++++----------------------------------------
 1 files changed, 17 insertions(+), 52 deletions(-)


Index: llvm/lib/Target/PowerPC/PPCInstrAltivec.td
diff -u llvm/lib/Target/PowerPC/PPCInstrAltivec.td:1.28 llvm/lib/Target/PowerPC/PPCInstrAltivec.td:1.29
--- llvm/lib/Target/PowerPC/PPCInstrAltivec.td:1.28	Fri Mar 31 16:34:05 2006
+++ llvm/lib/Target/PowerPC/PPCInstrAltivec.td	Fri Mar 31 16:41:56 2006
@@ -156,10 +156,6 @@
                                                      imm:$SH))]>;
 
 // VX-Form instructions.  AltiVec arithmetic ops.
-def VADDCUW : VXForm_1<384, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
-                       "vaddcuw $vD, $vA, $vB", VecFP,
-                       [(set VRRC:$vD,
-                             (int_ppc_altivec_vaddcuw VRRC:$vA, VRRC:$vB))]>;
 def VADDFP : VXForm_1<10, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
                       "vaddfp $vD, $vA, $vB", VecFP,
                       [(set VRRC:$vD, (fadd VRRC:$vA, VRRC:$vB))]>;
@@ -174,31 +170,15 @@
                       "vadduwm $vD, $vA, $vB", VecGeneral,
                       [(set VRRC:$vD, (add (v4i32 VRRC:$vA), VRRC:$vB))]>;
                       
-def VADDSBS : VXForm_1<768, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
-                       "vaddsbs $vD, $vA, $vB", VecFP,
-                       [(set VRRC:$vD,
-                             (int_ppc_altivec_vaddsbs VRRC:$vA, VRRC:$vB))]>;
-def VADDSHS : VXForm_1<832, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
-                       "vaddshs $vD, $vA, $vB", VecFP,
-                       [(set VRRC:$vD,
-                             (int_ppc_altivec_vaddshs VRRC:$vA, VRRC:$vB))]>;
-def VADDSWS : VXForm_1<896, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
-                       "vaddsws $vD, $vA, $vB", VecFP,
-                       [(set VRRC:$vD,
-                             (int_ppc_altivec_vaddsws VRRC:$vA, VRRC:$vB))]>;
+def VADDCUW : VX1_Int<384, "vaddcuw", int_ppc_altivec_vaddcuw>;
+def VADDSBS : VX1_Int<768, "vaddsbs", int_ppc_altivec_vaddsbs>;
+def VADDSHS : VX1_Int<832, "vaddshs", int_ppc_altivec_vaddshs>;
+def VADDSWS : VX1_Int<896, "vaddsws", int_ppc_altivec_vaddsws>;
+def VADDUBS : VX1_Int<512, "vaddubs", int_ppc_altivec_vaddubs>;
+def VADDUHS : VX1_Int<576, "vadduhs", int_ppc_altivec_vadduhs>;
+def VADDUWS : VX1_Int<640, "vadduws", int_ppc_altivec_vadduws>;
+                             
                              
-def VADDUBS : VXForm_1<512, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
-                       "vaddubs $vD, $vA, $vB", VecFP,
-                       [(set VRRC:$vD,
-                             (int_ppc_altivec_vaddubs VRRC:$vA, VRRC:$vB))]>;
-def VADDUHS : VXForm_1<576, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
-                       "vadduhs $vD, $vA, $vB", VecFP,
-                       [(set VRRC:$vD,
-                             (int_ppc_altivec_vadduhs VRRC:$vA, VRRC:$vB))]>;
-def VADDUWS : VXForm_1<640, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
-                       "vadduws $vD, $vA, $vB", VecFP,
-                       [(set VRRC:$vD,
-                             (int_ppc_altivec_vadduws VRRC:$vA, VRRC:$vB))]>;
 def VAND : VXForm_1<1028, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
                     "vand $vD, $vA, $vB", VecFP,
                     [(set VRRC:$vD, (and (v4i32 VRRC:$vA), VRRC:$vB))]>;
@@ -220,12 +200,9 @@
 def VCTUXS : VXForm_1<906, (ops VRRC:$vD, u5imm:$UIMM, VRRC:$vB),
                       "vctuxs $vD, $vB, $UIMM", VecFP,
                       []>;
-def VEXPTEFP : VXForm_2<394, (ops VRRC:$vD, VRRC:$vB),
-                        "vexptefp $vD, $vB", VecFP,
-                        [(set VRRC:$vD, (int_ppc_altivec_vexptefp VRRC:$vB))]>;
-def VLOGEFP  : VXForm_2<458, (ops VRRC:$vD, VRRC:$vB),
-                        "vlogefp $vD, $vB", VecFP,
-                        [(set VRRC:$vD, (int_ppc_altivec_vlogefp VRRC:$vB))]>;
+def VEXPTEFP : VX2_Int<394, "vexptefp", int_ppc_altivec_vexptefp>;
+def VLOGEFP  : VX2_Int<458, "vlogefp",  int_ppc_altivec_vlogefp>;
+
 def VMAXFP : VXForm_1<1034, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
                       "vmaxfp $vD, $vA, $vB", VecFP,
                       []>;
@@ -353,24 +330,12 @@
 def VPKUWUS : VX1_Int<206, "vpkuwus", int_ppc_altivec_vpkuwus>;
 
 // Vector Unpack.
-def VUPKHPX : VXForm_2<846, (ops VRRC:$vD, VRRC:$vB),
-                       "vupkhpx $vD, $vB", VecFP,
-                       [(set VRRC:$vD, (int_ppc_altivec_vupkhpx VRRC:$vB))]>;
-def VUPKHSB : VXForm_2<526, (ops VRRC:$vD, VRRC:$vB),
-                       "vupkhsb $vD, $vB", VecFP,
-                       [(set VRRC:$vD, (int_ppc_altivec_vupkhsb VRRC:$vB))]>;
-def VUPKHSH : VXForm_2<590, (ops VRRC:$vD, VRRC:$vB),
-                       "vupkhsh $vD, $vB", VecFP,
-                       [(set VRRC:$vD, (int_ppc_altivec_vupkhsh VRRC:$vB))]>;
-def VUPKLPX : VXForm_2<974, (ops VRRC:$vD, VRRC:$vB),
-                       "vupklpx $vD, $vB", VecFP,
-                       [(set VRRC:$vD, (int_ppc_altivec_vupklpx VRRC:$vB))]>;
-def VUPKLSB : VXForm_2<654, (ops VRRC:$vD, VRRC:$vB),
-                       "vupklsb $vD, $vB", VecFP,
-                       [(set VRRC:$vD, (int_ppc_altivec_vupklsb VRRC:$vB))]>;
-def VUPKLSH : VXForm_2<718, (ops VRRC:$vD, VRRC:$vB),
-                       "vupklsh $vD, $vB", VecFP,
-                       [(set VRRC:$vD, (int_ppc_altivec_vupklsh VRRC:$vB))]>;
+def VUPKHPX : VX2_Int<846, "vupkhpx", int_ppc_altivec_vupkhpx>;
+def VUPKHSB : VX2_Int<526, "vupkhsb", int_ppc_altivec_vupkhsb>;
+def VUPKHSH : VX2_Int<590, "vupkhsh", int_ppc_altivec_vupkhsh>;
+def VUPKLPX : VX2_Int<974, "vupklpx", int_ppc_altivec_vupklpx>;
+def VUPKLSB : VX2_Int<654, "vupklsb", int_ppc_altivec_vupklsb>;
+def VUPKLSH : VX2_Int<718, "vupklsh", int_ppc_altivec_vupklsh>;
 
 
 // Altivec Comparisons.





From lattner at cs.uiuc.edu  Fri Mar 31 17:02:08 2006
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Fri, 31 Mar 2006 17:02:08 -0600
Subject: [llvm-commits] 
	CVS: llvm/lib/Transforms/Scalar/InstructionCombining.cpp
Message-ID: <200603312302.RAA00377@zion.cs.uiuc.edu>



Changes in directory llvm/lib/Transforms/Scalar:

InstructionCombining.cpp updated: 1.455 -> 1.456
---
Log message:

If we can look through vector operations to find the scalar version of an 
extract_element'd value, do so.


---
Diffs of the changes:  (+40 -0)

 InstructionCombining.cpp |   40 ++++++++++++++++++++++++++++++++++++++++
 1 files changed, 40 insertions(+)


Index: llvm/lib/Transforms/Scalar/InstructionCombining.cpp
diff -u llvm/lib/Transforms/Scalar/InstructionCombining.cpp:1.455 llvm/lib/Transforms/Scalar/InstructionCombining.cpp:1.456
--- llvm/lib/Transforms/Scalar/InstructionCombining.cpp:1.455	Fri Mar 31 12:25:14 2006
+++ llvm/lib/Transforms/Scalar/InstructionCombining.cpp	Fri Mar 31 17:01:56 2006
@@ -6654,7 +6654,41 @@
   return false;
 }
 
+/// FindScalarElement - Given a vector and an element number, see if the scalar
+/// value is already around as a register, for example if it were inserted then
+/// extracted from the vector.
+static Value *FindScalarElement(Value *V, unsigned EltNo) {
+  assert(isa<PackedType>(V->getType()) && "Not looking at a vector?");
+  const PackedType *PTy = cast<PackedType>(V->getType());
+  if (EltNo >= PTy->getNumElements())  // Out of range access.
+    return UndefValue::get(PTy->getElementType());
+  
+  if (isa<UndefValue>(V))
+    return UndefValue::get(PTy->getElementType());
+  else if (isa<ConstantAggregateZero>(V))
+    return Constant::getNullValue(PTy->getElementType());
+  else if (ConstantPacked *CP = dyn_cast<ConstantPacked>(V))
+    return CP->getOperand(EltNo);
+  else if (InsertElementInst *III = dyn_cast<InsertElementInst>(V)) {
+    // If this is an insert to a variable element, we don't know what it is.
+    if (!isa<ConstantUInt>(III->getOperand(2))) return 0;
+    unsigned IIElt = cast<ConstantUInt>(III->getOperand(2))->getValue();
+    
+    // If this is an insert to the element we are looking for, return the
+    // inserted value.
+    if (EltNo == IIElt) return III->getOperand(1);
+    
+    // Otherwise, the insertelement doesn't modify the value, recurse on its
+    // vector input.
+    return FindScalarElement(III->getOperand(0), EltNo);
+  }
+  
+  // Otherwise, we don't know.
+  return 0;
+}
+
 Instruction *InstCombiner::visitExtractElementInst(ExtractElementInst &EI) {
+
   // If packed val is undef, replace extract with scalar undef.
   if (isa<UndefValue>(EI.getOperand(0)))
     return ReplaceInstUsesWith(EI, UndefValue::get(EI.getType()));
@@ -6676,6 +6710,12 @@
       return ReplaceInstUsesWith(EI, op0);
   }
   
+  // If extracting a specified index from the vector, see if we can recursively
+  // find a previously computed scalar that was inserted into the vector.
+  if (ConstantUInt *IdxC = dyn_cast<ConstantUInt>(EI.getOperand(1)))
+    if (Value *Elt = FindScalarElement(EI.getOperand(0), IdxC->getValue()))
+      return ReplaceInstUsesWith(EI, Elt);
+  
   if (Instruction *I = dyn_cast<Instruction>(EI.getOperand(0)))
     if (I->hasOneUse()) {
       // Push extractelement into predecessor operation if legal and





From lattner at cs.uiuc.edu  Fri Mar 31 22:08:41 2006
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Fri, 31 Mar 2006 22:08:41 -0600
Subject: [llvm-commits] CVS: llvm/lib/Target/README.txt 
Message-ID: <200604010408.WAA02745@zion.cs.uiuc.edu>



Changes in directory llvm/lib/Target:

README.txt updated: 1.26 -> 1.27
---
Log message:

ADd a note


---
Diffs of the changes:  (+12 -0)

 README.txt |   12 ++++++++++++
 1 files changed, 12 insertions(+)


Index: llvm/lib/Target/README.txt
diff -u llvm/lib/Target/README.txt:1.26 llvm/lib/Target/README.txt:1.27
--- llvm/lib/Target/README.txt:1.26	Fri Mar 31 16:35:14 2006
+++ llvm/lib/Target/README.txt	Fri Mar 31 22:08:29 2006
@@ -154,3 +154,15 @@
 For packed types, TargetData.cpp::getTypeInfo() returns alignment that is equal
 to the type size. It works but can be overly conservative as the alignment of
 specific packed types are target dependent.
+
+//===---------------------------------------------------------------------===//
+
+We should add 'unaligned load/store' nodes, and produce them from code like
+this:
+
+v4sf example(float *P) {
+  return (v4sf){P[0], P[1], P[2], P[3] };
+}
+
+//===---------------------------------------------------------------------===//
+





From lattner at cs.uiuc.edu  Fri Mar 31 22:47:29 2006
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Fri, 31 Mar 2006 22:47:29 -0600
Subject: [llvm-commits] 
	CVS: llvm/test/Regression/Transforms/IndVarsSimplify/2006-03-31-NegativeStride.ll
Message-ID: <200604010447.WAA03627@zion.cs.uiuc.edu>



Changes in directory llvm/test/Regression/Transforms/IndVarsSimplify:

2006-03-31-NegativeStride.ll added (r1.1)
---
Log message:

new testcase for PR726: http://llvm.cs.uiuc.edu/PR726 


---
Diffs of the changes:  (+21 -0)

 2006-03-31-NegativeStride.ll |   21 +++++++++++++++++++++
 1 files changed, 21 insertions(+)


Index: llvm/test/Regression/Transforms/IndVarsSimplify/2006-03-31-NegativeStride.ll
diff -c /dev/null llvm/test/Regression/Transforms/IndVarsSimplify/2006-03-31-NegativeStride.ll:1.1
*** /dev/null	Fri Mar 31 22:47:27 2006
--- llvm/test/Regression/Transforms/IndVarsSimplify/2006-03-31-NegativeStride.ll	Fri Mar 31 22:47:17 2006
***************
*** 0 ****
--- 1,21 ----
+ ; RUN: llvm-as < %s | opt -indvars | llvm-dis | grep 'ret int 27'
+ 
+ ; Make sure to compute the right exit value based on negative strides.
+ ; PR726
+ 
+ int %test() {
+ entry:
+         br label %cond_true
+ 
+ cond_true:              ; preds = %cond_true, %entry
+         %a.0.0 = phi int [ 10, %entry ], [ %tmp4, %cond_true ]          ; <int> [#uses=2]
+         %b.0.0 = phi int [ 0, %entry ], [ %tmp2, %cond_true ]           ; <int> [#uses=1]
+         %tmp2 = add int %b.0.0, %a.0.0          ; <int> [#uses=2]
+         %tmp4 = add int %a.0.0, -1              ; <int> [#uses=2]
+         %tmp = setgt int %tmp4, 7               ; <bool> [#uses=1]
+         br bool %tmp, label %cond_true, label %bb7
+ 
+ bb7:            ; preds = %cond_true
+         ret int %tmp2
+ }
+ 





From lattner at cs.uiuc.edu  Fri Mar 31 22:49:04 2006
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Fri, 31 Mar 2006 22:49:04 -0600
Subject: [llvm-commits] 
	CVS: llvm/include/llvm/Analysis/ScalarEvolutionExpander.h
	ScalarEvolutionExpressions.h 
Message-ID: <200604010449.WAA03690@zion.cs.uiuc.edu>



Changes in directory llvm/include/llvm/Analysis:

ScalarEvolutionExpander.h updated: 1.4 -> 1.5
ScalarEvolutionExpressions.h updated: 1.6 -> 1.7
---
Log message:

Fix Transforms/IndVarsSimplify/2006-03-31-NegativeStride.ll and
PR726: http://llvm.cs.uiuc.edu/PR726  by performing consistent signed division, not consistent unsigned
division when evaluating scev's.  Do not touch udivs.


---
Diffs of the changes:  (+12 -12)

 ScalarEvolutionExpander.h    |    2 +-
 ScalarEvolutionExpressions.h |   22 +++++++++++-----------
 2 files changed, 12 insertions(+), 12 deletions(-)


Index: llvm/include/llvm/Analysis/ScalarEvolutionExpander.h
diff -u llvm/include/llvm/Analysis/ScalarEvolutionExpander.h:1.4 llvm/include/llvm/Analysis/ScalarEvolutionExpander.h:1.5
--- llvm/include/llvm/Analysis/ScalarEvolutionExpander.h:1.4	Sat Feb  4 03:51:33 2006
+++ llvm/include/llvm/Analysis/ScalarEvolutionExpander.h	Fri Mar 31 22:48:52 2006
@@ -136,7 +136,7 @@
 
     Value *visitMulExpr(SCEVMulExpr *S);
 
-    Value *visitUDivExpr(SCEVUDivExpr *S) {
+    Value *visitSDivExpr(SCEVSDivExpr *S) {
       const Type *Ty = S->getType();
       Value *LHS = expandInTy(S->getLHS(), Ty);
       Value *RHS = expandInTy(S->getRHS(), Ty);


Index: llvm/include/llvm/Analysis/ScalarEvolutionExpressions.h
diff -u llvm/include/llvm/Analysis/ScalarEvolutionExpressions.h:1.6 llvm/include/llvm/Analysis/ScalarEvolutionExpressions.h:1.7
--- llvm/include/llvm/Analysis/ScalarEvolutionExpressions.h:1.6	Thu Apr 21 15:16:32 2005
+++ llvm/include/llvm/Analysis/ScalarEvolutionExpressions.h	Fri Mar 31 22:48:52 2006
@@ -23,7 +23,7 @@
   enum SCEVTypes {
     // These should be ordered in terms of increasing complexity to make the
     // folders simpler.
-    scConstant, scTruncate, scZeroExtend, scAddExpr, scMulExpr, scUDivExpr,
+    scConstant, scTruncate, scZeroExtend, scAddExpr, scMulExpr, scSDivExpr,
     scAddRecExpr, scUnknown, scCouldNotCompute
   };
 
@@ -293,16 +293,16 @@
 
 
   //===--------------------------------------------------------------------===//
-  /// SCEVUDivExpr - This class represents a binary unsigned division operation.
+  /// SCEVSDivExpr - This class represents a binary unsigned division operation.
   ///
-  class SCEVUDivExpr : public SCEV {
+  class SCEVSDivExpr : public SCEV {
     SCEVHandle LHS, RHS;
-    SCEVUDivExpr(const SCEVHandle &lhs, const SCEVHandle &rhs)
-      : SCEV(scUDivExpr), LHS(lhs), RHS(rhs) {}
+    SCEVSDivExpr(const SCEVHandle &lhs, const SCEVHandle &rhs)
+      : SCEV(scSDivExpr), LHS(lhs), RHS(rhs) {}
 
-    virtual ~SCEVUDivExpr();
+    virtual ~SCEVSDivExpr();
   public:
-    /// get method - This just gets and returns a new SCEVUDiv object.
+    /// get method - This just gets and returns a new SCEVSDiv object.
     ///
     static SCEVHandle get(const SCEVHandle &LHS, const SCEVHandle &RHS);
 
@@ -334,9 +334,9 @@
     void print(std::ostream &OS) const;
 
     /// Methods for support type inquiry through isa, cast, and dyn_cast:
-    static inline bool classof(const SCEVUDivExpr *S) { return true; }
+    static inline bool classof(const SCEVSDivExpr *S) { return true; }
     static inline bool classof(const SCEV *S) {
-      return S->getSCEVType() == scUDivExpr;
+      return S->getSCEVType() == scSDivExpr;
     }
   };
 
@@ -496,8 +496,8 @@
         return ((SC*)this)->visitAddExpr((SCEVAddExpr*)S);
       case scMulExpr:
         return ((SC*)this)->visitMulExpr((SCEVMulExpr*)S);
-      case scUDivExpr:
-        return ((SC*)this)->visitUDivExpr((SCEVUDivExpr*)S);
+      case scSDivExpr:
+        return ((SC*)this)->visitSDivExpr((SCEVSDivExpr*)S);
       case scAddRecExpr:
         return ((SC*)this)->visitAddRecExpr((SCEVAddRecExpr*)S);
       case scUnknown:





From lattner at cs.uiuc.edu  Fri Mar 31 22:49:05 2006
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Fri, 31 Mar 2006 22:49:05 -0600
Subject: [llvm-commits] CVS: llvm/lib/Analysis/ScalarEvolution.cpp 
Message-ID: <200604010449.WAA03694@zion.cs.uiuc.edu>



Changes in directory llvm/lib/Analysis:

ScalarEvolution.cpp updated: 1.45 -> 1.46
---
Log message:

Fix Transforms/IndVarsSimplify/2006-03-31-NegativeStride.ll and
PR726: http://llvm.cs.uiuc.edu/PR726  by performing consistent signed division, not consistent unsigned
division when evaluating scev's.  Do not touch udivs.


---
Diffs of the changes:  (+27 -27)

 ScalarEvolution.cpp |   54 ++++++++++++++++++++++++++--------------------------
 1 files changed, 27 insertions(+), 27 deletions(-)


Index: llvm/lib/Analysis/ScalarEvolution.cpp
diff -u llvm/lib/Analysis/ScalarEvolution.cpp:1.45 llvm/lib/Analysis/ScalarEvolution.cpp:1.46
--- llvm/lib/Analysis/ScalarEvolution.cpp:1.45	Sun Jan 22 17:19:18 2006
+++ llvm/lib/Analysis/ScalarEvolution.cpp	Fri Mar 31 22:48:52 2006
@@ -294,22 +294,22 @@
 }
 
 
-// SCEVUDivs - Only allow the creation of one SCEVUDivExpr for any particular
+// SCEVSDivs - Only allow the creation of one SCEVSDivExpr for any particular
 // input.  Don't use a SCEVHandle here, or else the object will never be
 // deleted!
-static std::map<std::pair<SCEV*, SCEV*>, SCEVUDivExpr*> SCEVUDivs;
+static std::map<std::pair<SCEV*, SCEV*>, SCEVSDivExpr*> SCEVSDivs;
 
-SCEVUDivExpr::~SCEVUDivExpr() {
-  SCEVUDivs.erase(std::make_pair(LHS, RHS));
+SCEVSDivExpr::~SCEVSDivExpr() {
+  SCEVSDivs.erase(std::make_pair(LHS, RHS));
 }
 
-void SCEVUDivExpr::print(std::ostream &OS) const {
-  OS << "(" << *LHS << " /u " << *RHS << ")";
+void SCEVSDivExpr::print(std::ostream &OS) const {
+  OS << "(" << *LHS << " /s " << *RHS << ")";
 }
 
-const Type *SCEVUDivExpr::getType() const {
+const Type *SCEVSDivExpr::getType() const {
   const Type *Ty = LHS->getType();
-  if (Ty->isSigned()) Ty = Ty->getUnsignedVersion();
+  if (Ty->isUnsigned()) Ty = Ty->getSignedVersion();
   return Ty;
 }
 
@@ -540,7 +540,7 @@
   for (unsigned i = 1, e = getNumOperands(); i != e; ++i) {
     SCEVHandle BC = PartialFact(It, i);
     Divisor *= i;
-    SCEVHandle Val = SCEVUDivExpr::get(SCEVMulExpr::get(BC, getOperand(i)),
+    SCEVHandle Val = SCEVSDivExpr::get(SCEVMulExpr::get(BC, getOperand(i)),
                                        SCEVUnknown::getIntegerSCEV(Divisor,Ty));
     Result = SCEVAddExpr::get(Result, Val);
   }
@@ -982,20 +982,20 @@
   return Result;
 }
 
-SCEVHandle SCEVUDivExpr::get(const SCEVHandle &LHS, const SCEVHandle &RHS) {
+SCEVHandle SCEVSDivExpr::get(const SCEVHandle &LHS, const SCEVHandle &RHS) {
   if (SCEVConstant *RHSC = dyn_cast<SCEVConstant>(RHS)) {
     if (RHSC->getValue()->equalsInt(1))
-      return LHS;                            // X /u 1 --> x
+      return LHS;                            // X /s 1 --> x
     if (RHSC->getValue()->isAllOnesValue())
-      return SCEV::getNegativeSCEV(LHS);           // X /u -1  -->  -x
+      return SCEV::getNegativeSCEV(LHS);           // X /s -1  -->  -x
 
     if (SCEVConstant *LHSC = dyn_cast<SCEVConstant>(LHS)) {
       Constant *LHSCV = LHSC->getValue();
       Constant *RHSCV = RHSC->getValue();
-      if (LHSCV->getType()->isSigned())
+      if (LHSCV->getType()->isUnsigned())
         LHSCV = ConstantExpr::getCast(LHSCV,
-                                      LHSCV->getType()->getUnsignedVersion());
-      if (RHSCV->getType()->isSigned())
+                                      LHSCV->getType()->getSignedVersion());
+      if (RHSCV->getType()->isUnsigned())
         RHSCV = ConstantExpr::getCast(RHSCV, LHSCV->getType());
       return SCEVUnknown::get(ConstantExpr::getDiv(LHSCV, RHSCV));
     }
@@ -1003,8 +1003,8 @@
 
   // FIXME: implement folding of (X*4)/4 when we know X*4 doesn't overflow.
 
-  SCEVUDivExpr *&Result = SCEVUDivs[std::make_pair(LHS, RHS)];
-  if (Result == 0) Result = new SCEVUDivExpr(LHS, RHS);
+  SCEVSDivExpr *&Result = SCEVSDivs[std::make_pair(LHS, RHS)];
+  if (Result == 0) Result = new SCEVSDivExpr(LHS, RHS);
   return Result;
 }
 
@@ -1356,8 +1356,8 @@
       return SCEVMulExpr::get(getSCEV(I->getOperand(0)),
                               getSCEV(I->getOperand(1)));
     case Instruction::Div:
-      if (V->getType()->isInteger() && V->getType()->isUnsigned())
-        return SCEVUDivExpr::get(getSCEV(I->getOperand(0)),
+      if (V->getType()->isInteger() && V->getType()->isSigned())
+        return SCEVSDivExpr::get(getSCEV(I->getOperand(0)),
                                  getSCEV(I->getOperand(1)));
       break;
 
@@ -1376,10 +1376,10 @@
 
     case Instruction::Shr:
       if (ConstantUInt *SA = dyn_cast<ConstantUInt>(I->getOperand(1)))
-        if (V->getType()->isUnsigned()) {
+        if (V->getType()->isSigned()) {
           Constant *X = ConstantInt::get(V->getType(), 1);
           X = ConstantExpr::getShl(X, SA);
-          return SCEVUDivExpr::get(getSCEV(I->getOperand(0)), getSCEV(X));
+          return SCEVSDivExpr::get(getSCEV(I->getOperand(0)), getSCEV(X));
         }
       break;
 
@@ -1982,14 +1982,14 @@
     return Comm;
   }
 
-  if (SCEVUDivExpr *UDiv = dyn_cast<SCEVUDivExpr>(V)) {
-    SCEVHandle LHS = getSCEVAtScope(UDiv->getLHS(), L);
+  if (SCEVSDivExpr *Div = dyn_cast<SCEVSDivExpr>(V)) {
+    SCEVHandle LHS = getSCEVAtScope(Div->getLHS(), L);
     if (LHS == UnknownValue) return LHS;
-    SCEVHandle RHS = getSCEVAtScope(UDiv->getRHS(), L);
+    SCEVHandle RHS = getSCEVAtScope(Div->getRHS(), L);
     if (RHS == UnknownValue) return RHS;
-    if (LHS == UDiv->getLHS() && RHS == UDiv->getRHS())
-      return UDiv;   // must be loop invariant
-    return SCEVUDivExpr::get(LHS, RHS);
+    if (LHS == Div->getLHS() && RHS == Div->getRHS())
+      return Div;   // must be loop invariant
+    return SCEVSDivExpr::get(LHS, RHS);
   }
 
   // If this is a loop recurrence for a loop that does not contain L, then we





From lattner at cs.uiuc.edu  Sat Apr  1 02:03:03 2006
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Sat, 1 Apr 2006 02:03:03 -0600
Subject: [llvm-commits] 
	CVS: llvm/test/Regression/Transforms/InstCombine/xor.ll
Message-ID: <200604010803.CAA04718@zion.cs.uiuc.edu>



Changes in directory llvm/test/Regression/Transforms/InstCombine:

xor.ll updated: 1.16 -> 1.17
---
Log message:

new testcases


---
Diffs of the changes:  (+15 -0)

 xor.ll |   15 +++++++++++++++
 1 files changed, 15 insertions(+)


Index: llvm/test/Regression/Transforms/InstCombine/xor.ll
diff -u llvm/test/Regression/Transforms/InstCombine/xor.ll:1.16 llvm/test/Regression/Transforms/InstCombine/xor.ll:1.17
--- llvm/test/Regression/Transforms/InstCombine/xor.ll:1.16	Sun Feb 26 19:43:02 2006
+++ llvm/test/Regression/Transforms/InstCombine/xor.ll	Sat Apr  1 02:02:51 2006
@@ -166,3 +166,18 @@
         %tmp.4 = setne int %tmp.2, %c
         ret bool %tmp.4
 }
+
+int %test25(int %g, int %h) {
+	%h2 = xor int %h, -1
+        %tmp2 = and int %h2, %g
+        %tmp4 = xor int %tmp2, %g  ; (h2&g)^g -> ~h2 & g -> h & g
+        ret int %tmp4
+}
+
+int %test26(int %a, int %b) {
+	%b2 = xor int %b, -1
+        %tmp2 = xor int %a, %b2
+        %tmp4 = and int %tmp2, %a  ; (a^b2)&a -> ~b2 & a -> b & a
+        ret int %tmp4
+}
+





From lattner at cs.uiuc.edu  Sat Apr  1 02:04:07 2006
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Sat, 1 Apr 2006 02:04:07 -0600
Subject: [llvm-commits] 
	CVS: llvm/lib/Transforms/Scalar/InstructionCombining.cpp
Message-ID: <200604010804.CAA04755@zion.cs.uiuc.edu>



Changes in directory llvm/lib/Transforms/Scalar:

InstructionCombining.cpp updated: 1.456 -> 1.457
---
Log message:

Fold A^(B&A) -> (B&A)^A
Fold (B&A)^A == ~B & A

This implements InstCombine/xor.ll:test2[56]



---
Diffs of the changes:  (+46 -7)

 InstructionCombining.cpp |   53 ++++++++++++++++++++++++++++++++++++++++-------
 1 files changed, 46 insertions(+), 7 deletions(-)


Index: llvm/lib/Transforms/Scalar/InstructionCombining.cpp
diff -u llvm/lib/Transforms/Scalar/InstructionCombining.cpp:1.456 llvm/lib/Transforms/Scalar/InstructionCombining.cpp:1.457
--- llvm/lib/Transforms/Scalar/InstructionCombining.cpp:1.456	Fri Mar 31 17:01:56 2006
+++ llvm/lib/Transforms/Scalar/InstructionCombining.cpp	Sat Apr  1 02:03:55 2006
@@ -2508,6 +2508,30 @@
     if (match(Op1, m_Or(m_Value(A), m_Value(B))))
       if (A == Op0 || B == Op0)    // A & (A | ?)  --> A
         return ReplaceInstUsesWith(I, Op0);
+    
+    if (Op0->hasOneUse() &&
+        match(Op0, m_Xor(m_Value(A), m_Value(B)))) {
+      if (A == Op1) {                                // (A^B)&A -> A&(A^B)
+        I.swapOperands();     // Simplify below
+        std::swap(Op0, Op1);
+      } else if (B == Op1) {                         // (A^B)&B -> B&(B^A)
+        cast<BinaryOperator>(Op0)->swapOperands();
+        I.swapOperands();     // Simplify below
+        std::swap(Op0, Op1);
+      }
+    }
+    if (Op1->hasOneUse() &&
+        match(Op1, m_Xor(m_Value(A), m_Value(B)))) {
+      if (B == Op0) {                                // B&(A^B) -> B&(B^A)
+        cast<BinaryOperator>(Op1)->swapOperands();
+        std::swap(A, B);
+      }
+      if (A == Op0) {                                // A&(A^B) -> A & ~B
+        Instruction *NotB = BinaryOperator::createNot(B, "tmp");
+        InsertNewInstBefore(NotB, I);
+        return BinaryOperator::createAnd(A, NotB);
+      }
+    }
   }
   
 
@@ -2943,14 +2967,14 @@
       return ReplaceInstUsesWith(I,
                                 ConstantIntegral::getAllOnesValue(I.getType()));
 
-  if (Instruction *Op1I = dyn_cast<Instruction>(Op1))
+  if (BinaryOperator *Op1I = dyn_cast<BinaryOperator>(Op1))
     if (Op1I->getOpcode() == Instruction::Or) {
       if (Op1I->getOperand(0) == Op0) {              // B^(B|A) == (A|B)^B
-        cast<BinaryOperator>(Op1I)->swapOperands();
+        Op1I->swapOperands();
         I.swapOperands();
         std::swap(Op0, Op1);
       } else if (Op1I->getOperand(1) == Op0) {       // B^(A|B) == (A|B)^B
-        I.swapOperands();
+        I.swapOperands();     // Simplified below.
         std::swap(Op0, Op1);
       }
     } else if (Op1I->getOpcode() == Instruction::Xor) {
@@ -2958,15 +2982,22 @@
         return ReplaceInstUsesWith(I, Op1I->getOperand(1));
       else if (Op0 == Op1I->getOperand(1))                   // A^(B^A) == B
         return ReplaceInstUsesWith(I, Op1I->getOperand(0));
+    } else if (Op1I->getOpcode() == Instruction::And && Op1I->hasOneUse()) {
+      if (Op1I->getOperand(0) == Op0)                      // A^(A&B) -> A^(B&A)
+        Op1I->swapOperands();
+      if (Op0 == Op1I->getOperand(1)) {                    // A^(B&A) -> (B&A)^A
+        I.swapOperands();     // Simplified below.
+        std::swap(Op0, Op1);
+      }
     }
 
-  if (Instruction *Op0I = dyn_cast<Instruction>(Op0))
+  if (BinaryOperator *Op0I = dyn_cast<BinaryOperator>(Op0))
     if (Op0I->getOpcode() == Instruction::Or && Op0I->hasOneUse()) {
       if (Op0I->getOperand(0) == Op1)                // (B|A)^B == (A|B)^B
-        cast<BinaryOperator>(Op0I)->swapOperands();
+        Op0I->swapOperands();
       if (Op0I->getOperand(1) == Op1) {              // (A|B)^B == A & ~B
-        Value *NotB = InsertNewInstBefore(BinaryOperator::createNot(Op1,
-                                                     Op1->getName()+".not"), I);
+        Instruction *NotB = BinaryOperator::createNot(Op1, "tmp");
+        InsertNewInstBefore(NotB, I);
         return BinaryOperator::createAnd(Op0I->getOperand(0), NotB);
       }
     } else if (Op0I->getOpcode() == Instruction::Xor) {
@@ -2974,6 +3005,14 @@
         return ReplaceInstUsesWith(I, Op0I->getOperand(1));
       else if (Op1 == Op0I->getOperand(1))                   // (B^A)^A == B
         return ReplaceInstUsesWith(I, Op0I->getOperand(0));
+    } else if (Op0I->getOpcode() == Instruction::And && Op0I->hasOneUse()) {
+      if (Op0I->getOperand(0) == Op1)                      // (A&B)^A -> (B&A)^A
+        Op0I->swapOperands();
+      if (Op0I->getOperand(1) == Op1) {                    // (B&A)^A == ~B & A
+        Instruction *N = BinaryOperator::createNot(Op0I->getOperand(0), "tmp");
+        InsertNewInstBefore(N, I);
+        return BinaryOperator::createAnd(N, Op1);
+      }
     }
 
   // (setcc1 A, B) ^ (setcc2 A, B) --> (setcc3 A, B)





From lattner at cs.uiuc.edu  Sat Apr  1 16:04:53 2006
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Sat, 1 Apr 2006 16:04:53 -0600
Subject: [llvm-commits] 
	CVS: llvm/test/Regression/Transforms/InstCombine/2006-04-01-InfLoop.ll
Message-ID: <200604012204.QAA21367@zion.cs.uiuc.edu>



Changes in directory llvm/test/Regression/Transforms/InstCombine:

2006-04-01-InfLoop.ll added (r1.1)
---
Log message:

New testcase that caused instcombine to infinitely loop (with my recent
patch), distilled from Applications/JM/ldecod


---
Diffs of the changes:  (+441 -0)

 2006-04-01-InfLoop.ll |  441 ++++++++++++++++++++++++++++++++++++++++++++++++++
 1 files changed, 441 insertions(+)


Index: llvm/test/Regression/Transforms/InstCombine/2006-04-01-InfLoop.ll
diff -c /dev/null llvm/test/Regression/Transforms/InstCombine/2006-04-01-InfLoop.ll:1.1
*** /dev/null	Sat Apr  1 16:04:50 2006
--- llvm/test/Regression/Transforms/InstCombine/2006-04-01-InfLoop.ll	Sat Apr  1 16:04:40 2006
***************
*** 0 ****
--- 1,441 ----
+ ; RUN: llvm-as < %s | opt -instcombine -disable-output
+ 
+ 	%struct.DecRefPicMarking_s = type { int, int, int, int, int, %struct.DecRefPicMarking_s* }
+ 	%struct.datapartition = type { %typedef.Bitstream*, %typedef.DecodingEnvironment, int (%struct.syntaxelement*, %struct.img_par*, %struct.inp_par*, %struct.datapartition*)* }
+ 	%struct.img_par = type { int, uint, uint, int, int*, int, int, int, int, int, int, int, int, int, int, int, int, int, int, int, int, int, int, int, [16 x [16 x ushort]], [6 x [32 x int]], [16 x [16 x int]], [4 x [12 x [4 x [4 x int]]]], [16 x int], int**, int*, int***, int**, int, int, int, int, %typedef.Slice*, %struct.macroblock*, int, int, int, int, int, int, int**, %struct.DecRefPicMarking_s*, int, int, int, int, int, int, int, uint, int, int, int, uint, uint, uint, uint, int, [3 x int], int, uint, int, uint, int, int, int, uint, uint, int, int, int, int, uint, uint, int***, int***, int****, int, int, uint, int, int, int, int, uint, uint, uint, uint, uint, uint, uint, int, int, int, int, int, int, int, int, int, int, int, uint, int, int, int, int, int, int, int, int, int, int, int, int, int, int, int, %struct.timeb, %struct.timeb, int, int, int, int, int, uint, int, int }
+ 	%struct.inp_par = type { [100 x sbyte], [100 x sbyte], [100 x sbyte], int, int, int, int, int, int, int }
+ 	%struct.macroblock = type { int, int, int, %struct.macroblock*, %struct.macroblock*, int, [2 x [4 x [4 x [2 x int]]]], int, long, long, int, int, [4 x int], [4 x int], int, int, int, int, int, int, int, int, int, int, int, int, int, int, int, int, int }
+ 	%struct.pix_pos = type { int, int, int, int, int, int }
+ 	%struct.storable_picture = type { uint, int, int, int, int, [50 x [6 x [33 x long]]], [50 x [6 x [33 x long]]], [50 x [6 x [33 x long]]], [50 x [6 x [33 x long]]], uint, int, int, int, int, int, int, int, short, int, int, int, int, int, int, int, uint, uint, ushort**, ushort***, ubyte*, short**, sbyte***, long***, long***, short****, ubyte**, ubyte**, %struct.storable_picture*, %struct.storable_picture*, %struct.storable_picture*, int, int, int, int, int, int, int, int, int, int, int, int, int, [2 x int], int, %struct.DecRefPicMarking_s*, int }
+ 	%struct.syntaxelement = type { int, int, int, int, int, uint, int, int, void (int, int, int*, int*)*, void (%struct.syntaxelement*, %struct.inp_par*, %struct.img_par*, %typedef.DecodingEnvironment*)* }
+ 	%struct.timeb = type { int, ushort, short, short }
+ 	%typedef.BiContextType = type { ushort, ubyte }
+ 	%typedef.Bitstream = type { int, int, int, int, ubyte*, int }
+ 	%typedef.DecodingEnvironment = type { uint, uint, uint, uint, int, ubyte*, int* }
+ 	%typedef.MotionInfoContexts = type { [4 x [11 x %typedef.BiContextType]], [2 x [9 x %typedef.BiContextType]], [2 x [10 x %typedef.BiContextType]], [2 x [6 x %typedef.BiContextType]], [4 x %typedef.BiContextType], [4 x %typedef.BiContextType], [3 x %typedef.BiContextType] }
+ 	%typedef.Slice = type { int, int, int, int, uint, int, int, int, int, %struct.datapartition*, %typedef.MotionInfoContexts*, %typedef.TextureInfoContexts*, int, int*, int*, int*, int, int*, int*, int*, int (%struct.img_par*, %struct.inp_par*)*, int, int, int, int }
+ 	%typedef.TextureInfoContexts = type { [2 x %typedef.BiContextType], [4 x %typedef.BiContextType], [3 x [4 x %typedef.BiContextType]], [10 x [4 x %typedef.BiContextType]], [10 x [15 x %typedef.BiContextType]], [10 x [15 x %typedef.BiContextType]], [10 x [5 x %typedef.BiContextType]], [10 x [5 x %typedef.BiContextType]], [10 x [15 x %typedef.BiContextType]], [10 x [15 x %typedef.BiContextType]] }
+ %dec_picture = external global %struct.storable_picture*		; <%struct.storable_picture**> [#uses=1]
+ %last_dquant = external global int		; <int*> [#uses=1]
+ 
+ implementation   ; Functions:
+ 
+ void %readCBP_CABAC(%struct.syntaxelement* %se, %struct.inp_par* %inp, %struct.img_par* %img.1, %typedef.DecodingEnvironment* %dep_dp) {
+ entry:
+ 	%block_a = alloca %struct.pix_pos		; <%struct.pix_pos*> [#uses=5]
+ 	%tmp.1 = getelementptr %struct.img_par* %img.1, int 0, uint 37		; <%typedef.Slice**> [#uses=1]
+ 	%tmp.2 = load %typedef.Slice** %tmp.1		; <%typedef.Slice*> [#uses=1]
+ 	%tmp.3 = getelementptr %typedef.Slice* %tmp.2, int 0, uint 11		; <%typedef.TextureInfoContexts**> [#uses=1]
+ 	%tmp.4 = load %typedef.TextureInfoContexts** %tmp.3		; <%typedef.TextureInfoContexts*> [#uses=3]
+ 	%tmp.6 = getelementptr %struct.img_par* %img.1, int 0, uint 38		; <%struct.macroblock**> [#uses=1]
+ 	%tmp.7 = load %struct.macroblock** %tmp.6		; <%struct.macroblock*> [#uses=1]
+ 	%tmp.9 = getelementptr %struct.img_par* %img.1, int 0, uint 1		; <uint*> [#uses=1]
+ 	%tmp.10 = load uint* %tmp.9		; <uint> [#uses=1]
+ 	%tmp.11 = cast uint %tmp.10 to int		; <int> [#uses=1]
+ 	%tmp.12 = getelementptr %struct.macroblock* %tmp.7, int %tmp.11		; <%struct.macroblock*> [#uses=18]
+ 	br label %loopentry.0
+ 
+ loopentry.0:		; preds = %loopexit.1, %entry
+ 	%mask.1 = phi int [ undef, %entry ], [ %mask.0, %loopexit.1 ]		; <int> [#uses=1]
+ 	%cbp_bit.1 = phi int [ undef, %entry ], [ %cbp_bit.0, %loopexit.1 ]		; <int> [#uses=1]
+ 	%cbp.2 = phi int [ 0, %entry ], [ %cbp.1, %loopexit.1 ]		; <int> [#uses=5]
+ 	%curr_cbp_ctx.1 = phi int [ undef, %entry ], [ %curr_cbp_ctx.0, %loopexit.1 ]		; <int> [#uses=1]
+ 	%b.2 = phi int [ undef, %entry ], [ %b.1, %loopexit.1 ]		; <int> [#uses=1]
+ 	%a.2 = phi int [ undef, %entry ], [ %a.1, %loopexit.1 ]		; <int> [#uses=1]
+ 	%mb_y.0 = phi int [ 0, %entry ], [ %tmp.152, %loopexit.1 ]		; <int> [#uses=7]
+ 	%mb_x.0 = phi int [ undef, %entry ], [ %mb_x.1, %loopexit.1 ]		; <int> [#uses=0]
+ 	%tmp.14 = setle int %mb_y.0, 3		; <bool> [#uses=2]
+ 	%tmp.15 = cast bool %tmp.14 to int		; <int> [#uses=0]
+ 	br bool %tmp.14, label %no_exit.0, label %loopexit.0
+ 
+ no_exit.0:		; preds = %loopentry.0
+ 	br label %loopentry.1
+ 
+ loopentry.1:		; preds = %endif.7, %no_exit.0
+ 	%mask.0 = phi int [ %mask.1, %no_exit.0 ], [ %tmp.131, %endif.7 ]		; <int> [#uses=1]
+ 	%cbp_bit.0 = phi int [ %cbp_bit.1, %no_exit.0 ], [ %tmp.142, %endif.7 ]		; <int> [#uses=1]
+ 	%cbp.1 = phi int [ %cbp.2, %no_exit.0 ], [ %cbp.0, %endif.7 ]		; <int> [#uses=5]
+ 	%curr_cbp_ctx.0 = phi int [ %curr_cbp_ctx.1, %no_exit.0 ], [ %tmp.125, %endif.7 ]		; <int> [#uses=1]
+ 	%b.1 = phi int [ %b.2, %no_exit.0 ], [ %b.0, %endif.7 ]		; <int> [#uses=1]
+ 	%a.1 = phi int [ %a.2, %no_exit.0 ], [ %a.0, %endif.7 ]		; <int> [#uses=1]
+ 	%mb_x.1 = phi int [ 0, %no_exit.0 ], [ %tmp.150, %endif.7 ]		; <int> [#uses=9]
+ 	%tmp.17 = setle int %mb_x.1, 3		; <bool> [#uses=2]
+ 	%tmp.18 = cast bool %tmp.17 to int		; <int> [#uses=0]
+ 	br bool %tmp.17, label %no_exit.1, label %loopexit.1
+ 
+ no_exit.1:		; preds = %loopentry.1
+ 	%tmp.20 = getelementptr %struct.macroblock* %tmp.12, int 0, uint 12		; <[4 x int]*> [#uses=1]
+ 	%tmp.22 = div int %mb_x.1, 2		; <int> [#uses=1]
+ 	%tmp.24 = add int %tmp.22, %mb_y.0		; <int> [#uses=1]
+ 	%tmp.25 = getelementptr [4 x int]* %tmp.20, int 0, int %tmp.24		; <int*> [#uses=1]
+ 	%tmp.26 = load int* %tmp.25		; <int> [#uses=1]
+ 	%tmp.27 = seteq int %tmp.26, 11		; <bool> [#uses=2]
+ 	%tmp.28 = cast bool %tmp.27 to int		; <int> [#uses=0]
+ 	br bool %tmp.27, label %then.0, label %else.0
+ 
+ then.0:		; preds = %no_exit.1
+ 	br label %endif.0
+ 
+ else.0:		; preds = %no_exit.1
+ 	br label %endif.0
+ 
+ endif.0:		; preds = %else.0, %then.0
+ 	%tmp.30 = seteq int %mb_y.0, 0		; <bool> [#uses=2]
+ 	%tmp.31 = cast bool %tmp.30 to int		; <int> [#uses=0]
+ 	br bool %tmp.30, label %then.1, label %else.1
+ 
+ then.1:		; preds = %endif.0
+ 	%tmp.33 = getelementptr %struct.macroblock* %tmp.12, int 0, uint 3		; <%struct.macroblock**> [#uses=1]
+ 	%tmp.34 = load %struct.macroblock** %tmp.33		; <%struct.macroblock*> [#uses=1]
+ 	%tmp.35 = cast %struct.macroblock* %tmp.34 to sbyte*		; <sbyte*> [#uses=1]
+ 	%tmp.36 = seteq sbyte* %tmp.35, null		; <bool> [#uses=2]
+ 	%tmp.37 = cast bool %tmp.36 to int		; <int> [#uses=0]
+ 	br bool %tmp.36, label %then.2, label %else.2
+ 
+ then.2:		; preds = %then.1
+ 	br label %endif.1
+ 
+ else.2:		; preds = %then.1
+ 	%tmp.39 = getelementptr %struct.macroblock* %tmp.12, int 0, uint 3		; <%struct.macroblock**> [#uses=1]
+ 	%tmp.40 = load %struct.macroblock** %tmp.39		; <%struct.macroblock*> [#uses=1]
+ 	%tmp.41 = getelementptr %struct.macroblock* %tmp.40, int 0, uint 5		; <int*> [#uses=1]
+ 	%tmp.42 = load int* %tmp.41		; <int> [#uses=1]
+ 	%tmp.43 = seteq int %tmp.42, 14		; <bool> [#uses=2]
+ 	%tmp.44 = cast bool %tmp.43 to int		; <int> [#uses=0]
+ 	br bool %tmp.43, label %then.3, label %else.3
+ 
+ then.3:		; preds = %else.2
+ 	br label %endif.1
+ 
+ else.3:		; preds = %else.2
+ 	%tmp.46 = getelementptr %struct.macroblock* %tmp.12, int 0, uint 3		; <%struct.macroblock**> [#uses=1]
+ 	%tmp.47 = load %struct.macroblock** %tmp.46		; <%struct.macroblock*> [#uses=1]
+ 	%tmp.48 = getelementptr %struct.macroblock* %tmp.47, int 0, uint 7		; <int*> [#uses=1]
+ 	%tmp.49 = load int* %tmp.48		; <int> [#uses=1]
+ 	%tmp.51 = div int %mb_x.1, 2		; <int> [#uses=1]
+ 	%tmp.52 = add int %tmp.51, 2		; <int> [#uses=1]
+ 	%tmp.53 = cast int %tmp.52 to ubyte		; <ubyte> [#uses=1]
+ 	%tmp.54 = shr int %tmp.49, ubyte %tmp.53		; <int> [#uses=1]
+ 	%tmp.55 = cast int %tmp.54 to uint		; <uint> [#uses=1]
+ 	%tmp.57 = xor uint %tmp.55, 1		; <uint> [#uses=1]
+ 	%tmp.58 = cast uint %tmp.57 to int		; <int> [#uses=1]
+ 	%tmp.59 = and int %tmp.58, 1		; <int> [#uses=1]
+ 	br label %endif.1
+ 
+ else.1:		; preds = %endif.0
+ 	%tmp.62 = div int %mb_x.1, 2		; <int> [#uses=1]
+ 	%tmp.63 = cast int %tmp.62 to ubyte		; <ubyte> [#uses=1]
+ 	%tmp.64 = shr int %cbp.1, ubyte %tmp.63		; <int> [#uses=1]
+ 	%tmp.65 = cast int %tmp.64 to uint		; <uint> [#uses=1]
+ 	%tmp.67 = xor uint %tmp.65, 1		; <uint> [#uses=1]
+ 	%tmp.68 = cast uint %tmp.67 to int		; <int> [#uses=1]
+ 	%tmp.69 = and int %tmp.68, 1		; <int> [#uses=1]
+ 	br label %endif.1
+ 
+ endif.1:		; preds = %else.1, %else.3, %then.3, %then.2
+ 	%b.0 = phi int [ 0, %then.2 ], [ 0, %then.3 ], [ %tmp.59, %else.3 ], [ %tmp.69, %else.1 ]		; <int> [#uses=2]
+ 	%tmp.71 = seteq int %mb_x.1, 0		; <bool> [#uses=2]
+ 	%tmp.72 = cast bool %tmp.71 to int		; <int> [#uses=0]
+ 	br bool %tmp.71, label %then.4, label %else.4
+ 
+ then.4:		; preds = %endif.1
+ 	%tmp.74 = getelementptr %struct.img_par* %img.1, int 0, uint 1		; <uint*> [#uses=1]
+ 	%tmp.75 = load uint* %tmp.74		; <uint> [#uses=1]
+ 	%tmp.76 = cast uint %tmp.75 to int		; <int> [#uses=1]
+ 	call void %getLuma4x4Neighbour( int %tmp.76, int %mb_x.1, int %mb_y.0, int -1, int 0, %struct.pix_pos* %block_a )
+ 	%tmp.79 = getelementptr %struct.pix_pos* %block_a, int 0, uint 0		; <int*> [#uses=1]
+ 	%tmp.80 = load int* %tmp.79		; <int> [#uses=1]
+ 	%tmp.81 = setne int %tmp.80, 0		; <bool> [#uses=2]
+ 	%tmp.82 = cast bool %tmp.81 to int		; <int> [#uses=0]
+ 	br bool %tmp.81, label %then.5, label %else.5
+ 
+ then.5:		; preds = %then.4
+ 	%tmp.84 = getelementptr %struct.img_par* %img.1, int 0, uint 38		; <%struct.macroblock**> [#uses=1]
+ 	%tmp.85 = load %struct.macroblock** %tmp.84		; <%struct.macroblock*> [#uses=1]
+ 	%tmp.86 = getelementptr %struct.pix_pos* %block_a, int 0, uint 1		; <int*> [#uses=1]
+ 	%tmp.87 = load int* %tmp.86		; <int> [#uses=1]
+ 	%tmp.88 = getelementptr %struct.macroblock* %tmp.85, int %tmp.87		; <%struct.macroblock*> [#uses=1]
+ 	%tmp.89 = getelementptr %struct.macroblock* %tmp.88, int 0, uint 5		; <int*> [#uses=1]
+ 	%tmp.90 = load int* %tmp.89		; <int> [#uses=1]
+ 	%tmp.91 = seteq int %tmp.90, 14		; <bool> [#uses=2]
+ 	%tmp.92 = cast bool %tmp.91 to int		; <int> [#uses=0]
+ 	br bool %tmp.91, label %then.6, label %else.6
+ 
+ then.6:		; preds = %then.5
+ 	br label %endif.4
+ 
+ else.6:		; preds = %then.5
+ 	%tmp.94 = getelementptr %struct.img_par* %img.1, int 0, uint 38		; <%struct.macroblock**> [#uses=1]
+ 	%tmp.95 = load %struct.macroblock** %tmp.94		; <%struct.macroblock*> [#uses=1]
+ 	%tmp.96 = getelementptr %struct.pix_pos* %block_a, int 0, uint 1		; <int*> [#uses=1]
+ 	%tmp.97 = load int* %tmp.96		; <int> [#uses=1]
+ 	%tmp.98 = getelementptr %struct.macroblock* %tmp.95, int %tmp.97		; <%struct.macroblock*> [#uses=1]
+ 	%tmp.99 = getelementptr %struct.macroblock* %tmp.98, int 0, uint 7		; <int*> [#uses=1]
+ 	%tmp.100 = load int* %tmp.99		; <int> [#uses=1]
+ 	%tmp.101 = getelementptr %struct.pix_pos* %block_a, int 0, uint 3		; <int*> [#uses=1]
+ 	%tmp.102 = load int* %tmp.101		; <int> [#uses=1]
+ 	%tmp.103 = div int %tmp.102, 2		; <int> [#uses=1]
+ 	%tmp.104 = mul int %tmp.103, 2		; <int> [#uses=1]
+ 	%tmp.105 = add int %tmp.104, 1		; <int> [#uses=1]
+ 	%tmp.106 = cast int %tmp.105 to ubyte		; <ubyte> [#uses=1]
+ 	%tmp.107 = shr int %tmp.100, ubyte %tmp.106		; <int> [#uses=1]
+ 	%tmp.108 = cast int %tmp.107 to uint		; <uint> [#uses=1]
+ 	%tmp.110 = xor uint %tmp.108, 1		; <uint> [#uses=1]
+ 	%tmp.111 = cast uint %tmp.110 to int		; <int> [#uses=1]
+ 	%tmp.112 = and int %tmp.111, 1		; <int> [#uses=1]
+ 	br label %endif.4
+ 
+ else.5:		; preds = %then.4
+ 	br label %endif.4
+ 
+ else.4:		; preds = %endif.1
+ 	%tmp.115 = cast int %mb_y.0 to ubyte		; <ubyte> [#uses=1]
+ 	%tmp.116 = shr int %cbp.1, ubyte %tmp.115		; <int> [#uses=1]
+ 	%tmp.117 = cast int %tmp.116 to uint		; <uint> [#uses=1]
+ 	%tmp.119 = xor uint %tmp.117, 1		; <uint> [#uses=1]
+ 	%tmp.120 = cast uint %tmp.119 to int		; <int> [#uses=1]
+ 	%tmp.121 = and int %tmp.120, 1		; <int> [#uses=1]
+ 	br label %endif.4
+ 
+ endif.4:		; preds = %else.4, %else.5, %else.6, %then.6
+ 	%a.0 = phi int [ 0, %then.6 ], [ %tmp.112, %else.6 ], [ 0, %else.5 ], [ %tmp.121, %else.4 ]		; <int> [#uses=2]
+ 	%tmp.123 = mul int %b.0, 2		; <int> [#uses=1]
+ 	%tmp.125 = add int %tmp.123, %a.0		; <int> [#uses=2]
+ 	%tmp.127 = div int %mb_x.1, 2		; <int> [#uses=1]
+ 	%tmp.129 = add int %tmp.127, %mb_y.0		; <int> [#uses=1]
+ 	%tmp.130 = cast int %tmp.129 to ubyte		; <ubyte> [#uses=1]
+ 	%tmp.131 = shl int 1, ubyte %tmp.130		; <int> [#uses=2]
+ 	%tmp.135 = getelementptr %typedef.TextureInfoContexts* %tmp.4, int 0, uint 2		; <[3 x [4 x %typedef.BiContextType]]*> [#uses=1]
+ 	%tmp.136 = getelementptr [3 x [4 x %typedef.BiContextType]]* %tmp.135, int 0, int 0		; <[4 x %typedef.BiContextType]*> [#uses=1]
+ 	%tmp.137 = getelementptr [4 x %typedef.BiContextType]* %tmp.136, int 0, int 0		; <%typedef.BiContextType*> [#uses=1]
+ 	%tmp.139 = cast int %tmp.125 to uint		; <uint> [#uses=1]
+ 	%tmp.140 = cast uint %tmp.139 to int		; <int> [#uses=1]
+ 	%tmp.141 = getelementptr %typedef.BiContextType* %tmp.137, int %tmp.140		; <%typedef.BiContextType*> [#uses=1]
+ 	%tmp.132 = call uint %biari_decode_symbol( %typedef.DecodingEnvironment* %dep_dp, %typedef.BiContextType* %tmp.141 )		; <uint> [#uses=1]
+ 	%tmp.142 = cast uint %tmp.132 to int		; <int> [#uses=2]
+ 	%tmp.144 = setne int %tmp.142, 0		; <bool> [#uses=2]
+ 	%tmp.145 = cast bool %tmp.144 to int		; <int> [#uses=0]
+ 	br bool %tmp.144, label %then.7, label %endif.7
+ 
+ then.7:		; preds = %endif.4
+ 	%tmp.148 = add int %cbp.1, %tmp.131		; <int> [#uses=1]
+ 	br label %endif.7
+ 
+ endif.7:		; preds = %then.7, %endif.4
+ 	%cbp.0 = phi int [ %tmp.148, %then.7 ], [ %cbp.1, %endif.4 ]		; <int> [#uses=1]
+ 	%tmp.150 = add int %mb_x.1, 2		; <int> [#uses=1]
+ 	br label %loopentry.1
+ 
+ loopexit.1:		; preds = %loopentry.1
+ 	%tmp.152 = add int %mb_y.0, 2		; <int> [#uses=1]
+ 	br label %loopentry.0
+ 
+ loopexit.0:		; preds = %loopentry.0
+ 	%tmp.153 = load %struct.storable_picture** %dec_picture		; <%struct.storable_picture*> [#uses=1]
+ 	%tmp.154 = getelementptr %struct.storable_picture* %tmp.153, int 0, uint 45		; <int*> [#uses=1]
+ 	%tmp.155 = load int* %tmp.154		; <int> [#uses=1]
+ 	%tmp.156 = setne int %tmp.155, 0		; <bool> [#uses=2]
+ 	%tmp.157 = cast bool %tmp.156 to int		; <int> [#uses=0]
+ 	br bool %tmp.156, label %then.8, label %endif.8
+ 
+ then.8:		; preds = %loopexit.0
+ 	%tmp.159 = getelementptr %struct.macroblock* %tmp.12, int 0, uint 3		; <%struct.macroblock**> [#uses=1]
+ 	%tmp.160 = load %struct.macroblock** %tmp.159		; <%struct.macroblock*> [#uses=1]
+ 	%tmp.161 = cast %struct.macroblock* %tmp.160 to sbyte*		; <sbyte*> [#uses=1]
+ 	%tmp.162 = setne sbyte* %tmp.161, null		; <bool> [#uses=2]
+ 	%tmp.163 = cast bool %tmp.162 to int		; <int> [#uses=0]
+ 	br bool %tmp.162, label %then.9, label %endif.9
+ 
+ then.9:		; preds = %then.8
+ 	%tmp.165 = getelementptr %struct.macroblock* %tmp.12, int 0, uint 3		; <%struct.macroblock**> [#uses=1]
+ 	%tmp.166 = load %struct.macroblock** %tmp.165		; <%struct.macroblock*> [#uses=1]
+ 	%tmp.167 = getelementptr %struct.macroblock* %tmp.166, int 0, uint 5		; <int*> [#uses=1]
+ 	%tmp.168 = load int* %tmp.167		; <int> [#uses=1]
+ 	%tmp.169 = seteq int %tmp.168, 14		; <bool> [#uses=2]
+ 	%tmp.170 = cast bool %tmp.169 to int		; <int> [#uses=0]
+ 	br bool %tmp.169, label %then.10, label %else.7
+ 
+ then.10:		; preds = %then.9
+ 	br label %endif.9
+ 
+ else.7:		; preds = %then.9
+ 	%tmp.172 = getelementptr %struct.macroblock* %tmp.12, int 0, uint 3		; <%struct.macroblock**> [#uses=1]
+ 	%tmp.173 = load %struct.macroblock** %tmp.172		; <%struct.macroblock*> [#uses=1]
+ 	%tmp.174 = getelementptr %struct.macroblock* %tmp.173, int 0, uint 7		; <int*> [#uses=1]
+ 	%tmp.175 = load int* %tmp.174		; <int> [#uses=1]
+ 	%tmp.176 = setgt int %tmp.175, 15		; <bool> [#uses=1]
+ 	%tmp.177 = cast bool %tmp.176 to int		; <int> [#uses=1]
+ 	br label %endif.9
+ 
+ endif.9:		; preds = %else.7, %then.10, %then.8
+ 	%b.4 = phi int [ 1, %then.10 ], [ %tmp.177, %else.7 ], [ 0, %then.8 ]		; <int> [#uses=1]
+ 	%tmp.179 = getelementptr %struct.macroblock* %tmp.12, int 0, uint 4		; <%struct.macroblock**> [#uses=1]
+ 	%tmp.180 = load %struct.macroblock** %tmp.179		; <%struct.macroblock*> [#uses=1]
+ 	%tmp.181 = cast %struct.macroblock* %tmp.180 to sbyte*		; <sbyte*> [#uses=1]
+ 	%tmp.182 = setne sbyte* %tmp.181, null		; <bool> [#uses=2]
+ 	%tmp.183 = cast bool %tmp.182 to int		; <int> [#uses=0]
+ 	br bool %tmp.182, label %then.11, label %endif.11
+ 
+ then.11:		; preds = %endif.9
+ 	%tmp.185 = getelementptr %struct.macroblock* %tmp.12, int 0, uint 4		; <%struct.macroblock**> [#uses=1]
+ 	%tmp.186 = load %struct.macroblock** %tmp.185		; <%struct.macroblock*> [#uses=1]
+ 	%tmp.187 = getelementptr %struct.macroblock* %tmp.186, int 0, uint 5		; <int*> [#uses=1]
+ 	%tmp.188 = load int* %tmp.187		; <int> [#uses=1]
+ 	%tmp.189 = seteq int %tmp.188, 14		; <bool> [#uses=2]
+ 	%tmp.190 = cast bool %tmp.189 to int		; <int> [#uses=0]
+ 	br bool %tmp.189, label %then.12, label %else.8
+ 
+ then.12:		; preds = %then.11
+ 	br label %endif.11
+ 
+ else.8:		; preds = %then.11
+ 	%tmp.192 = getelementptr %struct.macroblock* %tmp.12, int 0, uint 4		; <%struct.macroblock**> [#uses=1]
+ 	%tmp.193 = load %struct.macroblock** %tmp.192		; <%struct.macroblock*> [#uses=1]
+ 	%tmp.194 = getelementptr %struct.macroblock* %tmp.193, int 0, uint 7		; <int*> [#uses=1]
+ 	%tmp.195 = load int* %tmp.194		; <int> [#uses=1]
+ 	%tmp.196 = setgt int %tmp.195, 15		; <bool> [#uses=1]
+ 	%tmp.197 = cast bool %tmp.196 to int		; <int> [#uses=1]
+ 	br label %endif.11
+ 
+ endif.11:		; preds = %else.8, %then.12, %endif.9
+ 	%a.4 = phi int [ 1, %then.12 ], [ %tmp.197, %else.8 ], [ 0, %endif.9 ]		; <int> [#uses=1]
+ 	%tmp.199 = mul int %b.4, 2		; <int> [#uses=1]
+ 	%tmp.201 = add int %tmp.199, %a.4		; <int> [#uses=1]
+ 	%tmp.205 = getelementptr %typedef.TextureInfoContexts* %tmp.4, int 0, uint 2		; <[3 x [4 x %typedef.BiContextType]]*> [#uses=1]
+ 	%tmp.206 = getelementptr [3 x [4 x %typedef.BiContextType]]* %tmp.205, int 0, int 1		; <[4 x %typedef.BiContextType]*> [#uses=1]
+ 	%tmp.207 = getelementptr [4 x %typedef.BiContextType]* %tmp.206, int 0, int 0		; <%typedef.BiContextType*> [#uses=1]
+ 	%tmp.209 = cast int %tmp.201 to uint		; <uint> [#uses=1]
+ 	%tmp.210 = cast uint %tmp.209 to int		; <int> [#uses=1]
+ 	%tmp.211 = getelementptr %typedef.BiContextType* %tmp.207, int %tmp.210		; <%typedef.BiContextType*> [#uses=1]
+ 	%tmp.202 = call uint %biari_decode_symbol( %typedef.DecodingEnvironment* %dep_dp, %typedef.BiContextType* %tmp.211 )		; <uint> [#uses=1]
+ 	%tmp.212 = cast uint %tmp.202 to int		; <int> [#uses=1]
+ 	%tmp.214 = setne int %tmp.212, 0		; <bool> [#uses=2]
+ 	%tmp.215 = cast bool %tmp.214 to int		; <int> [#uses=0]
+ 	br bool %tmp.214, label %then.13, label %endif.8
+ 
+ then.13:		; preds = %endif.11
+ 	%tmp.217 = getelementptr %struct.macroblock* %tmp.12, int 0, uint 3		; <%struct.macroblock**> [#uses=1]
+ 	%tmp.218 = load %struct.macroblock** %tmp.217		; <%struct.macroblock*> [#uses=1]
+ 	%tmp.219 = cast %struct.macroblock* %tmp.218 to sbyte*		; <sbyte*> [#uses=1]
+ 	%tmp.220 = setne sbyte* %tmp.219, null		; <bool> [#uses=2]
+ 	%tmp.221 = cast bool %tmp.220 to int		; <int> [#uses=0]
+ 	br bool %tmp.220, label %then.14, label %endif.14
+ 
+ then.14:		; preds = %then.13
+ 	%tmp.223 = getelementptr %struct.macroblock* %tmp.12, int 0, uint 3		; <%struct.macroblock**> [#uses=1]
+ 	%tmp.224 = load %struct.macroblock** %tmp.223		; <%struct.macroblock*> [#uses=1]
+ 	%tmp.225 = getelementptr %struct.macroblock* %tmp.224, int 0, uint 5		; <int*> [#uses=1]
+ 	%tmp.226 = load int* %tmp.225		; <int> [#uses=1]
+ 	%tmp.227 = seteq int %tmp.226, 14		; <bool> [#uses=2]
+ 	%tmp.228 = cast bool %tmp.227 to int		; <int> [#uses=0]
+ 	br bool %tmp.227, label %then.15, label %else.9
+ 
+ then.15:		; preds = %then.14
+ 	br label %endif.14
+ 
+ else.9:		; preds = %then.14
+ 	%tmp.230 = getelementptr %struct.macroblock* %tmp.12, int 0, uint 3		; <%struct.macroblock**> [#uses=1]
+ 	%tmp.231 = load %struct.macroblock** %tmp.230		; <%struct.macroblock*> [#uses=1]
+ 	%tmp.232 = getelementptr %struct.macroblock* %tmp.231, int 0, uint 7		; <int*> [#uses=1]
+ 	%tmp.233 = load int* %tmp.232		; <int> [#uses=1]
+ 	%tmp.234 = setgt int %tmp.233, 15		; <bool> [#uses=2]
+ 	%tmp.235 = cast bool %tmp.234 to int		; <int> [#uses=0]
+ 	br bool %tmp.234, label %then.16, label %endif.14
+ 
+ then.16:		; preds = %else.9
+ 	%tmp.237 = getelementptr %struct.macroblock* %tmp.12, int 0, uint 3		; <%struct.macroblock**> [#uses=1]
+ 	%tmp.238 = load %struct.macroblock** %tmp.237		; <%struct.macroblock*> [#uses=1]
+ 	%tmp.239 = getelementptr %struct.macroblock* %tmp.238, int 0, uint 7		; <int*> [#uses=1]
+ 	%tmp.240 = load int* %tmp.239		; <int> [#uses=1]
+ 	%tmp.242 = shr int %tmp.240, ubyte 4		; <int> [#uses=1]
+ 	%tmp.243 = seteq int %tmp.242, 2		; <bool> [#uses=1]
+ 	%tmp.244 = cast bool %tmp.243 to int		; <int> [#uses=1]
+ 	br label %endif.14
+ 
+ endif.14:		; preds = %then.16, %else.9, %then.15, %then.13
+ 	%b.5 = phi int [ 1, %then.15 ], [ %tmp.244, %then.16 ], [ 0, %else.9 ], [ 0, %then.13 ]		; <int> [#uses=1]
+ 	%tmp.246 = getelementptr %struct.macroblock* %tmp.12, int 0, uint 4		; <%struct.macroblock**> [#uses=1]
+ 	%tmp.247 = load %struct.macroblock** %tmp.246		; <%struct.macroblock*> [#uses=1]
+ 	%tmp.248 = cast %struct.macroblock* %tmp.247 to sbyte*		; <sbyte*> [#uses=1]
+ 	%tmp.249 = setne sbyte* %tmp.248, null		; <bool> [#uses=2]
+ 	%tmp.250 = cast bool %tmp.249 to int		; <int> [#uses=0]
+ 	br bool %tmp.249, label %then.17, label %endif.17
+ 
+ then.17:		; preds = %endif.14
+ 	%tmp.252 = getelementptr %struct.macroblock* %tmp.12, int 0, uint 4		; <%struct.macroblock**> [#uses=1]
+ 	%tmp.253 = load %struct.macroblock** %tmp.252		; <%struct.macroblock*> [#uses=1]
+ 	%tmp.254 = getelementptr %struct.macroblock* %tmp.253, int 0, uint 5		; <int*> [#uses=1]
+ 	%tmp.255 = load int* %tmp.254		; <int> [#uses=1]
+ 	%tmp.256 = seteq int %tmp.255, 14		; <bool> [#uses=2]
+ 	%tmp.257 = cast bool %tmp.256 to int		; <int> [#uses=0]
+ 	br bool %tmp.256, label %then.18, label %else.10
+ 
+ then.18:		; preds = %then.17
+ 	br label %endif.17
+ 
+ else.10:		; preds = %then.17
+ 	%tmp.259 = getelementptr %struct.macroblock* %tmp.12, int 0, uint 4		; <%struct.macroblock**> [#uses=1]
+ 	%tmp.260 = load %struct.macroblock** %tmp.259		; <%struct.macroblock*> [#uses=1]
+ 	%tmp.261 = getelementptr %struct.macroblock* %tmp.260, int 0, uint 7		; <int*> [#uses=1]
+ 	%tmp.262 = load int* %tmp.261		; <int> [#uses=1]
+ 	%tmp.263 = setgt int %tmp.262, 15		; <bool> [#uses=2]
+ 	%tmp.264 = cast bool %tmp.263 to int		; <int> [#uses=0]
+ 	br bool %tmp.263, label %then.19, label %endif.17
+ 
+ then.19:		; preds = %else.10
+ 	%tmp.266 = getelementptr %struct.macroblock* %tmp.12, int 0, uint 4		; <%struct.macroblock**> [#uses=1]
+ 	%tmp.267 = load %struct.macroblock** %tmp.266		; <%struct.macroblock*> [#uses=1]
+ 	%tmp.268 = getelementptr %struct.macroblock* %tmp.267, int 0, uint 7		; <int*> [#uses=1]
+ 	%tmp.269 = load int* %tmp.268		; <int> [#uses=1]
+ 	%tmp.271 = shr int %tmp.269, ubyte 4		; <int> [#uses=1]
+ 	%tmp.272 = seteq int %tmp.271, 2		; <bool> [#uses=1]
+ 	%tmp.273 = cast bool %tmp.272 to int		; <int> [#uses=1]
+ 	br label %endif.17
+ 
+ endif.17:		; preds = %then.19, %else.10, %then.18, %endif.14
+ 	%a.5 = phi int [ 1, %then.18 ], [ %tmp.273, %then.19 ], [ 0, %else.10 ], [ 0, %endif.14 ]		; <int> [#uses=1]
+ 	%tmp.275 = mul int %b.5, 2		; <int> [#uses=1]
+ 	%tmp.277 = add int %tmp.275, %a.5		; <int> [#uses=1]
+ 	%tmp.281 = getelementptr %typedef.TextureInfoContexts* %tmp.4, int 0, uint 2		; <[3 x [4 x %typedef.BiContextType]]*> [#uses=1]
+ 	%tmp.282 = getelementptr [3 x [4 x %typedef.BiContextType]]* %tmp.281, int 0, int 2		; <[4 x %typedef.BiContextType]*> [#uses=1]
+ 	%tmp.283 = getelementptr [4 x %typedef.BiContextType]* %tmp.282, int 0, int 0		; <%typedef.BiContextType*> [#uses=1]
+ 	%tmp.285 = cast int %tmp.277 to uint		; <uint> [#uses=1]
+ 	%tmp.286 = cast uint %tmp.285 to int		; <int> [#uses=1]
+ 	%tmp.287 = getelementptr %typedef.BiContextType* %tmp.283, int %tmp.286		; <%typedef.BiContextType*> [#uses=1]
+ 	%tmp.278 = call uint %biari_decode_symbol( %typedef.DecodingEnvironment* %dep_dp, %typedef.BiContextType* %tmp.287 )		; <uint> [#uses=1]
+ 	%tmp.288 = cast uint %tmp.278 to int		; <int> [#uses=1]
+ 	%tmp.290 = seteq int %tmp.288, 1		; <bool> [#uses=2]
+ 	%tmp.291 = cast bool %tmp.290 to int		; <int> [#uses=0]
+ 	br bool %tmp.290, label %cond_true, label %cond_false
+ 
+ cond_true:		; preds = %endif.17
+ 	%tmp.293 = add int %cbp.2, 32		; <int> [#uses=1]
+ 	br label %cond_continue
+ 
+ cond_false:		; preds = %endif.17
+ 	%tmp.295 = add int %cbp.2, 16		; <int> [#uses=1]
+ 	br label %cond_continue
+ 
+ cond_continue:		; preds = %cond_false, %cond_true
+ 	%mem_tmp.0 = phi int [ %tmp.293, %cond_true ], [ %tmp.295, %cond_false ]		; <int> [#uses=1]
+ 	br label %endif.8
+ 
+ endif.8:		; preds = %cond_continue, %endif.11, %loopexit.0
+ 	%cbp.3 = phi int [ %mem_tmp.0, %cond_continue ], [ %cbp.2, %endif.11 ], [ %cbp.2, %loopexit.0 ]		; <int> [#uses=2]
+ 	%tmp.298 = getelementptr %struct.syntaxelement* %se, int 0, uint 1		; <int*> [#uses=1]
+ 	store int %cbp.3, int* %tmp.298
+ 	%tmp.301 = seteq int %cbp.3, 0		; <bool> [#uses=2]
+ 	%tmp.302 = cast bool %tmp.301 to int		; <int> [#uses=0]
+ 	br bool %tmp.301, label %then.20, label %return
+ 
+ then.20:		; preds = %endif.8
+ 	store int 0, int* %last_dquant
+ 	ret void
+ 
+ return:		; preds = %endif.8
+ 	ret void
+ }
+ 
+ declare uint %biari_decode_symbol(%typedef.DecodingEnvironment*, %typedef.BiContextType*)
+ 
+ declare void %getLuma4x4Neighbour(int, int, int, int, int, %struct.pix_pos*)





From lattner at cs.uiuc.edu  Sat Apr  1 16:05:14 2006
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Sat, 1 Apr 2006 16:05:14 -0600
Subject: [llvm-commits] 
	CVS: llvm/lib/Transforms/Scalar/InstructionCombining.cpp
Message-ID: <200604012205.QAA21380@zion.cs.uiuc.edu>



Changes in directory llvm/lib/Transforms/Scalar:

InstructionCombining.cpp updated: 1.457 -> 1.458
---
Log message:

Fix InstCombine/2006-04-01-InfLoop.ll


---
Diffs of the changes:  (+2 -1)

 InstructionCombining.cpp |    3 ++-
 1 files changed, 2 insertions(+), 1 deletion(-)


Index: llvm/lib/Transforms/Scalar/InstructionCombining.cpp
diff -u llvm/lib/Transforms/Scalar/InstructionCombining.cpp:1.457 llvm/lib/Transforms/Scalar/InstructionCombining.cpp:1.458
--- llvm/lib/Transforms/Scalar/InstructionCombining.cpp:1.457	Sat Apr  1 02:03:55 2006
+++ llvm/lib/Transforms/Scalar/InstructionCombining.cpp	Sat Apr  1 16:05:01 2006
@@ -3008,7 +3008,8 @@
     } else if (Op0I->getOpcode() == Instruction::And && Op0I->hasOneUse()) {
       if (Op0I->getOperand(0) == Op1)                      // (A&B)^A -> (B&A)^A
         Op0I->swapOperands();
-      if (Op0I->getOperand(1) == Op1) {                    // (B&A)^A == ~B & A
+      if (Op0I->getOperand(1) == Op1 &&                    // (B&A)^A == ~B & A
+          !isa<ConstantInt>(Op1)) {  // Canonical form is (B&C)^C
         Instruction *N = BinaryOperator::createNot(Op0I->getOperand(0), "tmp");
         InsertNewInstBefore(N, I);
         return BinaryOperator::createAnd(N, Op1);





From lattner at cs.uiuc.edu  Sat Apr  1 16:42:00 2006
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Sat, 1 Apr 2006 16:42:00 -0600
Subject: [llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCInstrAltivec.td 
Message-ID: <200604012242.QAA21503@zion.cs.uiuc.edu>



Changes in directory llvm/lib/Target/PowerPC:

PPCInstrAltivec.td updated: 1.29 -> 1.30
---
Log message:

Implement vnot using VNOR instead of using 'vspltisb v0, -1' and vxor


---
Diffs of the changes:  (+4 -0)

 PPCInstrAltivec.td |    4 ++++
 1 files changed, 4 insertions(+)


Index: llvm/lib/Target/PowerPC/PPCInstrAltivec.td
diff -u llvm/lib/Target/PowerPC/PPCInstrAltivec.td:1.29 llvm/lib/Target/PowerPC/PPCInstrAltivec.td:1.30
--- llvm/lib/Target/PowerPC/PPCInstrAltivec.td:1.29	Fri Mar 31 16:41:56 2006
+++ llvm/lib/Target/PowerPC/PPCInstrAltivec.td	Sat Apr  1 16:41:47 2006
@@ -445,6 +445,10 @@
 def : Pat<(v4i32 vecspltisw:$invec), (v4i32 (VSPLTISW vecspltisw:$invec))>;
 
 // Logical Operations
+def : Pat<(v16i8 (vnot VRRC:$vA)), (v16i8 (VNOR VRRC:$vA, VRRC:$vA))>;
+def : Pat<(v8i16 (vnot VRRC:$vA)), (v8i16 (VNOR VRRC:$vA, VRRC:$vA))>;
+def : Pat<(v4i32 (vnot VRRC:$vA)), (v4i32 (VNOR VRRC:$vA, VRRC:$vA))>;
+
 def : Pat<(v16i8 (and VRRC:$A, VRRC:$B)), (v16i8 (VAND VRRC:$A, VRRC:$B))>;
 def : Pat<(v8i16 (and VRRC:$A, VRRC:$B)), (v8i16 (VAND VRRC:$A, VRRC:$B))>;
 def : Pat<(v16i8 (or  VRRC:$A, VRRC:$B)), (v16i8 (VOR  VRRC:$A, VRRC:$B))>;





From lattner at cs.uiuc.edu  Sat Apr  1 17:17:24 2006
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Sat, 1 Apr 2006 17:17:24 -0600
Subject: [llvm-commits] CVS: llvm/lib/Transforms/Utils/ValueMapper.cpp 
Message-ID: <200604012317.RAA21815@zion.cs.uiuc.edu>



Changes in directory llvm/lib/Transforms/Utils:

ValueMapper.cpp updated: 1.22 -> 1.23
---
Log message:

add valuemapper support for inline asm


---
Diffs of the changes:  (+1 -1)

 ValueMapper.cpp |    2 +-
 1 files changed, 1 insertion(+), 1 deletion(-)


Index: llvm/lib/Transforms/Utils/ValueMapper.cpp
diff -u llvm/lib/Transforms/Utils/ValueMapper.cpp:1.22 llvm/lib/Transforms/Utils/ValueMapper.cpp:1.23
--- llvm/lib/Transforms/Utils/ValueMapper.cpp:1.22	Sun Mar 26 23:50:18 2006
+++ llvm/lib/Transforms/Utils/ValueMapper.cpp	Sat Apr  1 17:17:11 2006
@@ -24,7 +24,7 @@
 
   // Global values do not need to be seeded into the ValueMap if they are using
   // the identity mapping.
-  if (isa<GlobalValue>(V))
+  if (isa<GlobalValue>(V) || isa<InlineAsm>(V))
     return VMSlot = const_cast<Value*>(V);
 
   if (Constant *C = const_cast<Constant*>(dyn_cast<Constant>(V))) {





From lattner at cs.uiuc.edu  Sat Apr  1 18:24:12 2006
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Sat, 1 Apr 2006 18:24:12 -0600
Subject: [llvm-commits] 
	CVS: llvm/test/Regression/CodeGen/PowerPC/2006-04-01-FloatDoubleExtend.ll
Message-ID: <200604020024.SAA22394@zion.cs.uiuc.edu>



Changes in directory llvm/test/Regression/CodeGen/PowerPC:

2006-04-01-FloatDoubleExtend.ll added (r1.1)
---
Log message:

New testcase that crashes the compiler.


---
Diffs of the changes:  (+7 -0)

 2006-04-01-FloatDoubleExtend.ll |    7 +++++++
 1 files changed, 7 insertions(+)


Index: llvm/test/Regression/CodeGen/PowerPC/2006-04-01-FloatDoubleExtend.ll
diff -c /dev/null llvm/test/Regression/CodeGen/PowerPC/2006-04-01-FloatDoubleExtend.ll:1.1
*** /dev/null	Sat Apr  1 18:24:09 2006
--- llvm/test/Regression/CodeGen/PowerPC/2006-04-01-FloatDoubleExtend.ll	Sat Apr  1 18:23:59 2006
***************
*** 0 ****
--- 1,7 ----
+ ; RUN: llvm-as < %s | llc -march=ppc32
+ 
+ double %CalcSpeed(float %tmp127) {
+ 	%tmp145 = cast float %tmp127 to double		; <double> [#uses=1]
+ 	%tmp150 = call double asm "frsqrte $0,$1", "=f,f"( double %tmp145 )		; <double> [#uses=0]
+ 	ret double %tmp150
+ }





From lattner at cs.uiuc.edu  Sat Apr  1 18:24:58 2006
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Sat, 1 Apr 2006 18:24:58 -0600
Subject: [llvm-commits] 
	CVS: llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
Message-ID: <200604020024.SAA22427@zion.cs.uiuc.edu>



Changes in directory llvm/lib/CodeGen/SelectionDAG:

SelectionDAGISel.cpp updated: 1.214 -> 1.215
---
Log message:

Prefer larger register classes over smaller ones when a register occurs in
multiple register classes.  This fixes PowerPC/2006-04-01-FloatDoubleExtend.ll


---
Diffs of the changes:  (+21 -7)

 SelectionDAGISel.cpp |   28 +++++++++++++++++++++-------
 1 files changed, 21 insertions(+), 7 deletions(-)


Index: llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.214 llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.215
--- llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.214	Thu Mar 30 20:12:18 2006
+++ llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp	Sat Apr  1 18:24:45 2006
@@ -1663,21 +1663,30 @@
 static const TargetRegisterClass *
 isAllocatableRegister(unsigned Reg, MachineFunction &MF,
                       const TargetLowering &TLI, const MRegisterInfo *MRI) {
+  MVT::ValueType FoundVT = MVT::Other;
+  const TargetRegisterClass *FoundRC = 0;
   for (MRegisterInfo::regclass_iterator RCI = MRI->regclass_begin(),
        E = MRI->regclass_end(); RCI != E; ++RCI) {
+    MVT::ValueType ThisVT = MVT::Other;
+
     const TargetRegisterClass *RC = *RCI;
     // If none of the the value types for this register class are valid, we 
     // can't use it.  For example, 64-bit reg classes on 32-bit targets.
-    bool isLegal = false;
     for (TargetRegisterClass::vt_iterator I = RC->vt_begin(), E = RC->vt_end();
          I != E; ++I) {
       if (TLI.isTypeLegal(*I)) {
-        isLegal = true;
-        break;
+        // If we have already found this register in a different register class,
+        // choose the one with the largest VT specified.  For example, on
+        // PowerPC, we favor f64 register classes over f32.
+        if (FoundVT == MVT::Other || 
+            MVT::getSizeInBits(FoundVT) < MVT::getSizeInBits(*I)) {
+          ThisVT = *I;
+          break;
+        }
       }
     }
     
-    if (!isLegal) continue;
+    if (ThisVT == MVT::Other) continue;
     
     // NOTE: This isn't ideal.  In particular, this might allocate the
     // frame pointer in functions that need it (due to them not being taken
@@ -1685,10 +1694,15 @@
     // yet).  This is a slight code pessimization, but should still work.
     for (TargetRegisterClass::iterator I = RC->allocation_order_begin(MF),
          E = RC->allocation_order_end(MF); I != E; ++I)
-      if (*I == Reg)
-        return RC;
+      if (*I == Reg) {
+        // We found a matching register class.  Keep looking at others in case
+        // we find one with larger registers that this physreg is also in.
+        FoundRC = RC;
+        FoundVT = ThisVT;
+        break;
+      }
   }
-  return 0;
+  return FoundRC;
 }    
 
 RegsForValue SelectionDAGLowering::





From lattner at cs.uiuc.edu  Sat Apr  1 18:43:49 2006
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Sat, 1 Apr 2006 18:43:49 -0600
Subject: [llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCISelLowering.cpp 
Message-ID: <200604020043.SAA22592@zion.cs.uiuc.edu>



Changes in directory llvm/lib/Target/PowerPC:

PPCISelLowering.cpp updated: 1.124 -> 1.125
---
Log message:

Custom lower all BUILD_VECTOR's so that we can compile vec_splat_u8(8) into
"vspltisb v0, 8" instead of a constant pool load.


---
Diffs of the changes:  (+2 -0)

 PPCISelLowering.cpp |    2 ++
 1 files changed, 2 insertions(+)


Index: llvm/lib/Target/PowerPC/PPCISelLowering.cpp
diff -u llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.124 llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.125
--- llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.124	Fri Mar 31 13:52:36 2006
+++ llvm/lib/Target/PowerPC/PPCISelLowering.cpp	Sat Apr  1 18:43:36 2006
@@ -204,6 +204,8 @@
     setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4f32, Custom);
     setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i32, Custom);
     
+    setOperationAction(ISD::BUILD_VECTOR, MVT::v16i8, Custom);
+    setOperationAction(ISD::BUILD_VECTOR, MVT::v8i16, Custom);
     setOperationAction(ISD::BUILD_VECTOR, MVT::v4i32, Custom);
     setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom);
   }





From lattner at cs.uiuc.edu  Sat Apr  1 19:38:41 2006
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Sat, 1 Apr 2006 19:38:41 -0600
Subject: [llvm-commits] CVS: llvm/lib/VMCore/ConstantFolding.cpp 
Message-ID: <200604020138.TAA25686@zion.cs.uiuc.edu>



Changes in directory llvm/lib/VMCore:

ConstantFolding.cpp updated: 1.84 -> 1.85
---
Log message:

Constant fold casts from things like <4 x int> -> <4 x uint>, likewise int<->fp.


---
Diffs of the changes:  (+108 -0)

 ConstantFolding.cpp |  108 ++++++++++++++++++++++++++++++++++++++++++++++++++++
 1 files changed, 108 insertions(+)


Index: llvm/lib/VMCore/ConstantFolding.cpp
diff -u llvm/lib/VMCore/ConstantFolding.cpp:1.84 llvm/lib/VMCore/ConstantFolding.cpp:1.85
--- llvm/lib/VMCore/ConstantFolding.cpp:1.84	Fri Mar 31 12:31:40 2006
+++ llvm/lib/VMCore/ConstantFolding.cpp	Sat Apr  1 19:38:28 2006
@@ -24,6 +24,7 @@
 #include "llvm/DerivedTypes.h"
 #include "llvm/Function.h"
 #include "llvm/Support/GetElementPtrTypeIterator.h"
+#include "llvm/Support/MathExtras.h"
 #include <limits>
 #include <cmath>
 using namespace llvm;
@@ -621,6 +622,81 @@
   return S ? S : 8;  // Treat pointers at 8 bytes
 }
 
+/// CastConstantPacked - Convert the specified ConstantPacked node to the
+/// specified packed type.  At this point, we know that the elements of the
+/// input packed constant are all simple integer or FP values.
+static Constant *CastConstantPacked(ConstantPacked *CP,
+                                    const PackedType *DstTy) {
+  unsigned SrcNumElts = CP->getType()->getNumElements();
+  unsigned DstNumElts = DstTy->getNumElements();
+  const Type *SrcEltTy = CP->getType()->getElementType();
+  const Type *DstEltTy = DstTy->getElementType();
+  
+  // If both vectors have the same number of elements (thus, the elements
+  // are the same size), perform the conversion now.
+  if (SrcNumElts == DstNumElts) {
+    std::vector<Constant*> Result;
+    
+    // If the src and dest elements are both integers, just cast each one
+    // which will do the appropriate bit-convert.
+    if (SrcEltTy->isIntegral() && DstEltTy->isIntegral()) {
+      for (unsigned i = 0; i != SrcNumElts; ++i)
+        Result.push_back(ConstantExpr::getCast(CP->getOperand(i),
+                                               DstEltTy));
+      return ConstantPacked::get(Result);
+    }
+    
+    if (SrcEltTy->isIntegral()) {
+      // Otherwise, this is an int-to-fp cast.
+      assert(DstEltTy->isFloatingPoint());
+      if (DstEltTy->getTypeID() == Type::DoubleTyID) {
+        for (unsigned i = 0; i != SrcNumElts; ++i) {
+          double V =
+            BitsToDouble(cast<ConstantInt>(CP->getOperand(i))->getRawValue());
+          Result.push_back(ConstantFP::get(Type::DoubleTy, V));
+        }
+        return ConstantPacked::get(Result);
+      }
+      assert(DstEltTy == Type::FloatTy && "Unknown fp type!");
+      for (unsigned i = 0; i != SrcNumElts; ++i) {
+        float V =
+        BitsToFloat(cast<ConstantInt>(CP->getOperand(i))->getRawValue());
+        Result.push_back(ConstantFP::get(Type::FloatTy, V));
+      }
+      return ConstantPacked::get(Result);
+    }
+    
+    // Otherwise, this is an fp-to-int cast.
+    assert(SrcEltTy->isFloatingPoint() && DstEltTy->isIntegral());
+    
+    if (SrcEltTy->getTypeID() == Type::DoubleTyID) {
+      for (unsigned i = 0; i != SrcNumElts; ++i) {
+        uint64_t V =
+          DoubleToBits(cast<ConstantFP>(CP->getOperand(i))->getValue());
+        Constant *C = ConstantUInt::get(Type::ULongTy, V);
+        Result.push_back(ConstantExpr::getCast(C, DstEltTy));
+      }
+      return ConstantPacked::get(Result);
+    }
+
+    assert(SrcEltTy->getTypeID() == Type::FloatTyID);
+    for (unsigned i = 0; i != SrcNumElts; ++i) {
+      unsigned V = FloatToBits(cast<ConstantFP>(CP->getOperand(i))->getValue());
+      Constant *C = ConstantUInt::get(Type::UIntTy, V);
+      Result.push_back(ConstantExpr::getCast(C, DstEltTy));
+    }
+    return ConstantPacked::get(Result);
+  }
+  
+  // Otherwise, this is a cast that changes element count and size.  Handle
+  // casts which shrink the elements here.
+  
+  // FIXME: We need to know endianness to do this!
+  
+  return 0;
+}
+
+
 Constant *llvm::ConstantFoldCastInstruction(const Constant *V,
                                             const Type *DestTy) {
   if (V->getType() == DestTy) return (Constant*)V;
@@ -688,6 +764,38 @@
       if (ElTy == DPTy->getElementType())
         return ConstantExpr::getGetElementPtr(const_cast<Constant*>(V),IdxList);
     }
+      
+  // Handle casts from one packed constant to another.  We know that the src and
+  // dest type have the same size.
+  if (const PackedType *DestPTy = dyn_cast<PackedType>(DestTy)) {
+    if (const PackedType *SrcTy = dyn_cast<PackedType>(V->getType())) {
+      assert(DestPTy->getElementType()->getPrimitiveSizeInBits() * 
+                 DestPTy->getNumElements()  ==
+             SrcTy->getElementType()->getPrimitiveSizeInBits() * 
+             SrcTy->getNumElements() && "Not cast between same sized vectors!");
+      if (isa<ConstantAggregateZero>(V))
+        return Constant::getNullValue(DestTy);
+      if (isa<UndefValue>(V))
+        return UndefValue::get(DestTy);
+      if (const ConstantPacked *CP = dyn_cast<ConstantPacked>(V)) {
+        // This is a cast from a ConstantPacked of one type to a ConstantPacked
+        // of another type.  Check to see if all elements of the input are
+        // simple.
+        bool AllSimpleConstants = true;
+        for (unsigned i = 0, e = CP->getNumOperands(); i != e; ++i) {
+          if (!isa<ConstantInt>(CP->getOperand(i)) &&
+              !isa<ConstantFP>(CP->getOperand(i))) {
+            AllSimpleConstants = false;
+            break;
+          }
+        }
+            
+        // If all of the elements are simple constants, we can fold this.
+        if (AllSimpleConstants)
+          return CastConstantPacked(const_cast<ConstantPacked*>(CP), DestPTy);
+      }
+    }
+  }
 
   ConstRules &Rules = ConstRules::get(V, V);
 





From lattner at cs.uiuc.edu  Sat Apr  1 19:47:31 2006
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Sat, 1 Apr 2006 19:47:31 -0600
Subject: [llvm-commits] CVS: llvm/lib/Target/README.txt 
Message-ID: <200604020147.TAA25748@zion.cs.uiuc.edu>



Changes in directory llvm/lib/Target:

README.txt updated: 1.27 -> 1.28
---
Log message:

New note


---
Diffs of the changes:  (+6 -0)

 README.txt |    6 ++++++
 1 files changed, 6 insertions(+)


Index: llvm/lib/Target/README.txt
diff -u llvm/lib/Target/README.txt:1.27 llvm/lib/Target/README.txt:1.28
--- llvm/lib/Target/README.txt:1.27	Fri Mar 31 22:08:29 2006
+++ llvm/lib/Target/README.txt	Sat Apr  1 19:47:20 2006
@@ -166,3 +166,9 @@
 
 //===---------------------------------------------------------------------===//
 
+We should constant fold packed type casts at the LLVM level, regardless of the
+cast.  Currently we cannot fold some casts because we don't have TargetData
+information in the constant folder, so we don't know the endianness of the 
+target!
+
+//===---------------------------------------------------------------------===//





From lattner at cs.uiuc.edu  Sat Apr  1 20:29:05 2006
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Sat, 1 Apr 2006 20:29:05 -0600
Subject: [llvm-commits] CVS: llvm/include/llvm/CodeGen/SelectionDAGNodes.h 
Message-ID: <200604020229.UAA25901@zion.cs.uiuc.edu>



Changes in directory llvm/include/llvm/CodeGen:

SelectionDAGNodes.h updated: 1.125 -> 1.126
---
Log message:

simplify this method



---
Diffs of the changes:  (+1 -3)

 SelectionDAGNodes.h |    4 +---
 1 files changed, 1 insertion(+), 3 deletions(-)


Index: llvm/include/llvm/CodeGen/SelectionDAGNodes.h
diff -u llvm/include/llvm/CodeGen/SelectionDAGNodes.h:1.125 llvm/include/llvm/CodeGen/SelectionDAGNodes.h:1.126
--- llvm/include/llvm/CodeGen/SelectionDAGNodes.h:1.125	Tue Mar 28 13:54:11 2006
+++ llvm/include/llvm/CodeGen/SelectionDAGNodes.h	Sat Apr  1 20:28:52 2006
@@ -1076,9 +1076,7 @@
 
   bool isNullValue() const { return Value == 0; }
   bool isAllOnesValue() const {
-    int NumBits = MVT::getSizeInBits(getValueType(0));
-    if (NumBits == 64) return Value+1 == 0;
-    return Value == (1ULL << NumBits)-1;
+    return Value == MVT::getIntVTBitMask(getValueType(0));
   }
 
   static bool classof(const ConstantSDNode *) { return true; }





From lattner at cs.uiuc.edu  Sat Apr  1 20:41:31 2006
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Sat, 1 Apr 2006 20:41:31 -0600
Subject: [llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp 
Message-ID: <200604020241.UAA26052@zion.cs.uiuc.edu>



Changes in directory llvm/lib/CodeGen/SelectionDAG:

SelectionDAG.cpp updated: 1.293 -> 1.294
---
Log message:

Add some missing node names


---
Diffs of the changes:  (+9 -0)

 SelectionDAG.cpp |    9 +++++++++
 1 files changed, 9 insertions(+)


Index: llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp:1.293 llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp:1.294
--- llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp:1.293	Thu Mar 30 20:06:56 2006
+++ llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp	Sat Apr  1 20:41:18 2006
@@ -2749,6 +2749,15 @@
   case ISD::VADD:   return "vadd";
   case ISD::VSUB:   return "vsub";
   case ISD::VMUL:   return "vmul";
+    
+  case ISD::VADD:   return "vadd";
+  case ISD::VSUB:   return "vsub";
+  case ISD::VMUL:   return "vmul";
+  case ISD::VSDIV:  return "vsdiv";
+  case ISD::VUDIV:  return "vudiv";
+  case ISD::VAND:   return "vand";
+  case ISD::VOR:    return "vor";
+  case ISD::VXOR:   return "vxor";
 
   case ISD::SETCC:       return "setcc";
   case ISD::SELECT:      return "select";





From lattner at cs.uiuc.edu  Sat Apr  1 20:51:40 2006
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Sat, 1 Apr 2006 20:51:40 -0600
Subject: [llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp 
Message-ID: <200604020251.UAA26145@zion.cs.uiuc.edu>



Changes in directory llvm/lib/CodeGen/SelectionDAG:

SelectionDAG.cpp updated: 1.294 -> 1.295
---
Log message:

These entries already exist


---
Diffs of the changes:  (+0 -4)

 SelectionDAG.cpp |    4 ----
 1 files changed, 4 deletions(-)


Index: llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp:1.294 llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp:1.295
--- llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp:1.294	Sat Apr  1 20:41:18 2006
+++ llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp	Sat Apr  1 20:51:27 2006
@@ -2749,10 +2749,6 @@
   case ISD::VADD:   return "vadd";
   case ISD::VSUB:   return "vsub";
   case ISD::VMUL:   return "vmul";
-    
-  case ISD::VADD:   return "vadd";
-  case ISD::VSUB:   return "vsub";
-  case ISD::VMUL:   return "vmul";
   case ISD::VSDIV:  return "vsdiv";
   case ISD::VUDIV:  return "vudiv";
   case ISD::VAND:   return "vand";





From lattner at cs.uiuc.edu  Sat Apr  1 20:53:55 2006
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Sat, 1 Apr 2006 20:53:55 -0600
Subject: [llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp 
Message-ID: <200604020253.UAA26206@zion.cs.uiuc.edu>



Changes in directory llvm/lib/CodeGen/SelectionDAG:

DAGCombiner.cpp updated: 1.136 -> 1.137
---
Log message:

Implement constant folding of bit_convert of arbitrary constant vbuild_vector nodes.


---
Diffs of the changes:  (+139 -2)

 DAGCombiner.cpp |  141 +++++++++++++++++++++++++++++++++++++++++++++++++++++++-
 1 files changed, 139 insertions(+), 2 deletions(-)


Index: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.136 llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.137
--- llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.136	Fri Mar 31 16:16:43 2006
+++ llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp	Sat Apr  1 20:53:43 2006
@@ -190,6 +190,7 @@
     SDOperand visitSIGN_EXTEND_INREG(SDNode *N);
     SDOperand visitTRUNCATE(SDNode *N);
     SDOperand visitBIT_CONVERT(SDNode *N);
+    SDOperand visitVBIT_CONVERT(SDNode *N);
     SDOperand visitFADD(SDNode *N);
     SDOperand visitFSUB(SDNode *N);
     SDOperand visitFMUL(SDNode *N);
@@ -224,7 +225,7 @@
                                SDOperand N3, ISD::CondCode CC);
     SDOperand SimplifySetCC(MVT::ValueType VT, SDOperand N0, SDOperand N1,
                             ISD::CondCode Cond, bool foldBooleans = true);
-    
+    SDOperand ConstantFoldVBIT_CONVERTofVBUILD_VECTOR(SDNode *, MVT::ValueType);
     SDOperand BuildSDIV(SDNode *N);
     SDOperand BuildUDIV(SDNode *N);    
 public:
@@ -627,6 +628,7 @@
   case ISD::SIGN_EXTEND_INREG:  return visitSIGN_EXTEND_INREG(N);
   case ISD::TRUNCATE:           return visitTRUNCATE(N);
   case ISD::BIT_CONVERT:        return visitBIT_CONVERT(N);
+  case ISD::VBIT_CONVERT:       return visitVBIT_CONVERT(N);
   case ISD::FADD:               return visitFADD(N);
   case ISD::FSUB:               return visitFSUB(N);
   case ISD::FMUL:               return visitFMUL(N);
@@ -1940,7 +1942,7 @@
   
   if (N0.getOpcode() == ISD::BIT_CONVERT)  // conv(conv(x,t1),t2) -> conv(x,t2)
     return DAG.getNode(ISD::BIT_CONVERT, VT, N0.getOperand(0));
-  
+
   // fold (conv (load x)) -> (load (conv*)x)
   // FIXME: These xforms need to know that the resultant load doesn't need a 
   // higher alignment than the original!
@@ -1956,6 +1958,141 @@
   return SDOperand();
 }
 
+SDOperand DAGCombiner::visitVBIT_CONVERT(SDNode *N) {
+  SDOperand N0 = N->getOperand(0);
+  MVT::ValueType VT = N->getValueType(0);
+
+  // If the input is a VBUILD_VECTOR with all constant elements, fold this now.
+  // First check to see if this is all constant.
+  if (N0.getOpcode() == ISD::VBUILD_VECTOR && N0.Val->hasOneUse() &&
+      VT == MVT::Vector) {
+    bool isSimple = true;
+    for (unsigned i = 0, e = N0.getNumOperands()-2; i != e; ++i)
+      if (N0.getOperand(i).getOpcode() != ISD::UNDEF &&
+          N0.getOperand(i).getOpcode() != ISD::Constant &&
+          N0.getOperand(i).getOpcode() != ISD::ConstantFP) {
+        isSimple = false; 
+        break;
+      }
+        
+    if (isSimple) {
+      MVT::ValueType DestEltVT = cast<VTSDNode>(N->getOperand(2))->getVT();
+      return ConstantFoldVBIT_CONVERTofVBUILD_VECTOR(N0.Val, DestEltVT);
+    }
+  }
+  
+  return SDOperand();
+}
+
+/// ConstantFoldVBIT_CONVERTofVBUILD_VECTOR - We know that BV is a vbuild_vector
+/// node with Constant, ConstantFP or Undef operands.  DstEltVT indicates the 
+/// destination element value type.
+SDOperand DAGCombiner::
+ConstantFoldVBIT_CONVERTofVBUILD_VECTOR(SDNode *BV, MVT::ValueType DstEltVT) {
+  MVT::ValueType SrcEltVT = BV->getOperand(0).getValueType();
+  
+  // If this is already the right type, we're done.
+  if (SrcEltVT == DstEltVT) return SDOperand(BV, 0);
+  
+  unsigned SrcBitSize = MVT::getSizeInBits(SrcEltVT);
+  unsigned DstBitSize = MVT::getSizeInBits(DstEltVT);
+  
+  // If this is a conversion of N elements of one type to N elements of another
+  // type, convert each element.  This handles FP<->INT cases.
+  if (SrcBitSize == DstBitSize) {
+    std::vector<SDOperand> Ops;
+    for (unsigned i = 0, e = BV->getNumOperands()-2; i != e; ++i)
+      Ops.push_back(DAG.getNode(ISD::BIT_CONVERT, DstEltVT, BV->getOperand(i)));
+    Ops.push_back(*(BV->op_end()-2)); // Add num elements.
+    Ops.push_back(DAG.getValueType(DstEltVT));
+    return DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector, Ops);
+  }
+  
+  // Otherwise, we're growing or shrinking the elements.  To avoid having to
+  // handle annoying details of growing/shrinking FP values, we convert them to
+  // int first.
+  if (MVT::isFloatingPoint(SrcEltVT)) {
+    // Convert the input float vector to a int vector where the elements are the
+    // same sizes.
+    assert((SrcEltVT == MVT::f32 || SrcEltVT == MVT::f64) && "Unknown FP VT!");
+    MVT::ValueType IntVT = SrcEltVT == MVT::f32 ? MVT::i32 : MVT::i64;
+    BV = ConstantFoldVBIT_CONVERTofVBUILD_VECTOR(BV, IntVT).Val;
+    SrcEltVT = IntVT;
+  }
+  
+  // Now we know the input is an integer vector.  If the output is a FP type,
+  // convert to integer first, then to FP of the right size.
+  if (MVT::isFloatingPoint(DstEltVT)) {
+    assert((DstEltVT == MVT::f32 || DstEltVT == MVT::f64) && "Unknown FP VT!");
+    MVT::ValueType TmpVT = DstEltVT == MVT::f32 ? MVT::i32 : MVT::i64;
+    SDNode *Tmp = ConstantFoldVBIT_CONVERTofVBUILD_VECTOR(BV, TmpVT).Val;
+    
+    // Next, convert to FP elements of the same size.
+    return ConstantFoldVBIT_CONVERTofVBUILD_VECTOR(Tmp, DstEltVT);
+  }
+  
+  // Okay, we know the src/dst types are both integers of differing types.
+  // Handling growing first.
+  assert(MVT::isInteger(SrcEltVT) && MVT::isInteger(DstEltVT));
+  if (SrcBitSize < DstBitSize) {
+    unsigned NumInputsPerOutput = DstBitSize/SrcBitSize;
+    
+    std::vector<SDOperand> Ops;
+    for (unsigned i = 0, e = BV->getNumOperands()-2; i != e;
+         i += NumInputsPerOutput) {
+      bool isLE = TLI.isLittleEndian();
+      uint64_t NewBits = 0;
+      bool EltIsUndef = true;
+      for (unsigned j = 0; j != NumInputsPerOutput; ++j) {
+        // Shift the previously computed bits over.
+        NewBits <<= SrcBitSize;
+        SDOperand Op = BV->getOperand(i+ (isLE ? (NumInputsPerOutput-j-1) : j));
+        if (Op.getOpcode() == ISD::UNDEF) continue;
+        EltIsUndef = false;
+        
+        NewBits |= cast<ConstantSDNode>(Op)->getValue();
+      }
+      
+      if (EltIsUndef)
+        Ops.push_back(DAG.getNode(ISD::UNDEF, DstEltVT));
+      else
+        Ops.push_back(DAG.getConstant(NewBits, DstEltVT));
+    }
+
+    Ops.push_back(DAG.getConstant(Ops.size(), MVT::i32)); // Add num elements.
+    Ops.push_back(DAG.getValueType(DstEltVT));            // Add element size.
+    return DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector, Ops);
+  }
+  
+  // Finally, this must be the case where we are shrinking elements: each input
+  // turns into multiple outputs.
+  unsigned NumOutputsPerInput = SrcBitSize/DstBitSize;
+  std::vector<SDOperand> Ops;
+  for (unsigned i = 0, e = BV->getNumOperands()-2; i != e; ++i) {
+    if (BV->getOperand(i).getOpcode() == ISD::UNDEF) {
+      for (unsigned j = 0; j != NumOutputsPerInput; ++j)
+        Ops.push_back(DAG.getNode(ISD::UNDEF, DstEltVT));
+      continue;
+    }
+    uint64_t OpVal = cast<ConstantSDNode>(BV->getOperand(i))->getValue();
+
+    for (unsigned j = 0; j != NumOutputsPerInput; ++j) {
+      unsigned ThisVal = OpVal & ((1ULL << DstBitSize)-1);
+      OpVal >>= DstBitSize;
+      Ops.push_back(DAG.getConstant(ThisVal, DstEltVT));
+    }
+
+    // For big endian targets, swap the order of the pieces of each element.
+    if (!TLI.isLittleEndian())
+      std::reverse(Ops.end()-NumOutputsPerInput, Ops.end());
+  }
+  Ops.push_back(DAG.getConstant(Ops.size(), MVT::i32)); // Add num elements.
+  Ops.push_back(DAG.getValueType(DstEltVT));            // Add element size.
+  return DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector, Ops);
+}
+
+
+
 SDOperand DAGCombiner::visitFADD(SDNode *N) {
   SDOperand N0 = N->getOperand(0);
   SDOperand N1 = N->getOperand(1);





From lattner at cs.uiuc.edu  Sat Apr  1 21:07:40 2006
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Sat, 1 Apr 2006 21:07:40 -0600
Subject: [llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
	SelectionDAGISel.cpp 
Message-ID: <200604020307.VAA26342@zion.cs.uiuc.edu>



Changes in directory llvm/lib/CodeGen/SelectionDAG:

LegalizeDAG.cpp updated: 1.348 -> 1.349
SelectionDAGISel.cpp updated: 1.215 -> 1.216
---
Log message:

Add a new -view-legalize-dags command line option


---
Diffs of the changes:  (+13 -3)

 LegalizeDAG.cpp      |   13 ++++++++++++-
 SelectionDAGISel.cpp |    3 +--
 2 files changed, 13 insertions(+), 3 deletions(-)


Index: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.348 llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.349
--- llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.348	Fri Mar 31 12:22:37 2006
+++ llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp	Sat Apr  1 21:07:27 2006
@@ -14,16 +14,25 @@
 #include "llvm/CodeGen/SelectionDAG.h"
 #include "llvm/CodeGen/MachineFunction.h"
 #include "llvm/CodeGen/MachineFrameInfo.h"
-#include "llvm/Support/MathExtras.h"
 #include "llvm/Target/TargetLowering.h"
 #include "llvm/Target/TargetData.h"
 #include "llvm/Target/TargetOptions.h"
 #include "llvm/CallingConv.h"
 #include "llvm/Constants.h"
+#include "llvm/Support/MathExtras.h"
+#include "llvm/Support/CommandLine.h"
 #include <iostream>
 #include <map>
 using namespace llvm;
 
+#ifndef NDEBUG
+static cl::opt<bool>
+ViewLegalizeDAGs("view-legalize-dags", cl::Hidden,
+                 cl::desc("Pop up a window to show dags before legalize"));
+#else
+static const bool ViewLegalizeDAGs = 0;
+#endif
+
 //===----------------------------------------------------------------------===//
 /// SelectionDAGLegalize - This takes an arbitrary SelectionDAG as input and
 /// hacks on it until the target machine can handle it.  This involves
@@ -4628,6 +4637,8 @@
 // SelectionDAG::Legalize - This is the entry point for the file.
 //
 void SelectionDAG::Legalize() {
+  if (ViewLegalizeDAGs) viewGraph();
+
   /// run - This is the main entry point to this class.
   ///
   SelectionDAGLegalize(*this).LegalizeDAG();


Index: llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.215 llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.216
--- llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.215	Sat Apr  1 18:24:45 2006
+++ llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp	Sat Apr  1 21:07:27 2006
@@ -54,8 +54,7 @@
 ViewSchedDAGs("view-sched-dags", cl::Hidden,
           cl::desc("Pop up a window to show sched dags as they are processed"));
 #else
-static const bool ViewISelDAGs = 0;
-static const bool ViewSchedDAGs = 0;
+static const bool ViewISelDAGs = 0, ViewSchedDAGs = 0;
 #endif
 
 // Scheduling heuristics





From lattner at cs.uiuc.edu  Sat Apr  1 21:26:10 2006
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Sat, 1 Apr 2006 21:26:10 -0600
Subject: [llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp 
Message-ID: <200604020326.VAA26437@zion.cs.uiuc.edu>



Changes in directory llvm/lib/CodeGen/SelectionDAG:

DAGCombiner.cpp updated: 1.137 -> 1.138
---
Log message:

Constant fold all of the vector binops.  This allows us to compile this:

"vector unsigned char mergeLowHigh = (vector unsigned char) 
( 8, 9, 10, 11, 16, 17, 18, 19, 12, 13, 14, 15, 20, 21, 22, 23 );
vector unsigned char mergeHighLow = vec_xor( mergeLowHigh, vec_splat_u8(8));"

aka:

void %test2(<16 x sbyte>* %P) {
  store <16 x sbyte> cast (<4 x int> xor (<4 x int> cast (<16 x ubyte> < ubyte 8, ubyte 9, ubyte 10, ubyte 11, ubyte 16, ubyte 17, ubyte 18, ubyte 19, ubyte 12, ubyte 13, ubyte 14, ubyte 15, ubyte 20, ubyte 21, ubyte 22, ubyte 23 > to <4 x int>), <4 x int> cast (<16 x sbyte> < sbyte 8, sbyte 8, sbyte 8, sbyte 8, sbyte 8, sbyte 8, sbyte 8, sbyte 8, sbyte 8, sbyte 8, sbyte 8, sbyte 8, sbyte 8, sbyte 8, sbyte 8, sbyte 8 > to <4 x int>)) to <16 x sbyte>), <16 x sbyte> * %P
  ret void
}

into this:

_test2:
        mfspr r2, 256
        oris r4, r2, 32768
        mtspr 256: http://llvm.cs.uiuc.edu/PR256 , r4
        li r4, lo16(LCPI2_0)
        lis r5, ha16(LCPI2_0)
        lvx v0, r5, r4
        stvx v0, 0, r3
        mtspr 256: http://llvm.cs.uiuc.edu/PR256 , r2
        blr

instead of this:

_test2:
        mfspr r2, 256
        oris r4, r2, 49152
        mtspr 256: http://llvm.cs.uiuc.edu/PR256 , r4
        li r4, lo16(LCPI2_0)
        lis r5, ha16(LCPI2_0)
        vspltisb v0, 8
        lvx v1, r5, r4
        vxor v0, v1, v0
        stvx v0, 0, r3
        mtspr 256: http://llvm.cs.uiuc.edu/PR256 , r2
        blr

... which occurs here:
http://developer.apple.com/hardware/ve/calcspeed.html



---
Diffs of the changes:  (+49 -0)

 DAGCombiner.cpp |   49 +++++++++++++++++++++++++++++++++++++++++++++++++
 1 files changed, 49 insertions(+)


Index: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.137 llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.138
--- llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.137	Sat Apr  1 20:53:43 2006
+++ llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp	Sat Apr  1 21:25:57 2006
@@ -176,6 +176,7 @@
     SDOperand visitAND(SDNode *N);
     SDOperand visitOR(SDNode *N);
     SDOperand visitXOR(SDNode *N);
+    SDOperand visitVBinOp(SDNode *N, ISD::NodeType IntOp, ISD::NodeType FPOp);
     SDOperand visitSHL(SDNode *N);
     SDOperand visitSRA(SDNode *N);
     SDOperand visitSRL(SDNode *N);
@@ -656,6 +657,14 @@
   case ISD::VBUILD_VECTOR:      return visitVBUILD_VECTOR(N);
   case ISD::VECTOR_SHUFFLE:     return visitVECTOR_SHUFFLE(N);
   case ISD::VVECTOR_SHUFFLE:    return visitVVECTOR_SHUFFLE(N);
+  case ISD::VADD:               return visitVBinOp(N, ISD::ADD , ISD::FADD);
+  case ISD::VSUB:               return visitVBinOp(N, ISD::SUB , ISD::FSUB);
+  case ISD::VMUL:               return visitVBinOp(N, ISD::MUL , ISD::FMUL);
+  case ISD::VSDIV:              return visitVBinOp(N, ISD::SDIV, ISD::FDIV);
+  case ISD::VUDIV:              return visitVBinOp(N, ISD::UDIV, ISD::UDIV);
+  case ISD::VAND:               return visitVBinOp(N, ISD::AND , ISD::AND);
+  case ISD::VOR:                return visitVBinOp(N, ISD::OR  , ISD::OR);
+  case ISD::VXOR:               return visitVBinOp(N, ISD::XOR , ISD::XOR);
   }
   return SDOperand();
 }
@@ -2682,6 +2691,46 @@
   return SDOperand();
 }
 
+/// visitVBinOp - Visit a binary vector operation, like VADD.  IntOp indicates
+/// the scalar operation of the vop if it is operating on an integer vector
+/// (e.g. ADD) and FPOp indicates the FP version (e.g. FADD).
+SDOperand DAGCombiner::visitVBinOp(SDNode *N, ISD::NodeType IntOp, 
+                                   ISD::NodeType FPOp) {
+  MVT::ValueType EltType = cast<VTSDNode>(*(N->op_end()-1))->getVT();
+  ISD::NodeType ScalarOp = MVT::isInteger(EltType) ? IntOp : FPOp;
+  SDOperand LHS = N->getOperand(0);
+  SDOperand RHS = N->getOperand(1);
+  
+  // If the LHS and RHS are VBUILD_VECTOR nodes, see if we can constant fold
+  // this operation.
+  if (LHS.getOpcode() == ISD::VBUILD_VECTOR && 
+      RHS.getOpcode() == ISD::VBUILD_VECTOR) {
+    std::vector<SDOperand> Ops;
+    for (unsigned i = 0, e = LHS.getNumOperands()-2; i != e; ++i) {
+      SDOperand LHSOp = LHS.getOperand(i);
+      SDOperand RHSOp = RHS.getOperand(i);
+      // If these two elements can't be folded, bail out.
+      if ((LHSOp.getOpcode() != ISD::UNDEF &&
+           LHSOp.getOpcode() != ISD::Constant &&
+           LHSOp.getOpcode() != ISD::ConstantFP) ||
+          (RHSOp.getOpcode() != ISD::UNDEF &&
+           RHSOp.getOpcode() != ISD::Constant &&
+           RHSOp.getOpcode() != ISD::ConstantFP))
+        break;
+      Ops.push_back(DAG.getNode(ScalarOp, EltType, LHSOp, RHSOp));
+      assert((Ops.back().getOpcode() == ISD::UNDEF ||
+              Ops.back().getOpcode() == ISD::Constant ||
+              Ops.back().getOpcode() == ISD::ConstantFP) &&
+             "Scalar binop didn't fold!");
+    }
+    Ops.push_back(*(LHS.Val->op_end()-2));
+    Ops.push_back(*(LHS.Val->op_end()-1));
+    return DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector, Ops);
+  }
+  
+  return SDOperand();
+}
+
 SDOperand DAGCombiner::SimplifySelect(SDOperand N0, SDOperand N1, SDOperand N2){
   assert(N0.getOpcode() ==ISD::SETCC && "First argument must be a SetCC node!");
   





From lattner at cs.uiuc.edu  Sat Apr  1 21:35:14 2006
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Sat, 1 Apr 2006 21:35:14 -0600
Subject: [llvm-commits] CVS: llvm/lib/Transforms/Utils/Local.cpp 
Message-ID: <200604020335.VAA26576@zion.cs.uiuc.edu>



Changes in directory llvm/lib/Transforms/Utils:

Local.cpp updated: 1.53 -> 1.54
---
Log message:

Adjust to change in Intrinsics.gen interface.



---
Diffs of the changes:  (+1 -0)

 Local.cpp |    1 +
 1 files changed, 1 insertion(+)


Index: llvm/lib/Transforms/Utils/Local.cpp
diff -u llvm/lib/Transforms/Utils/Local.cpp:1.53 llvm/lib/Transforms/Utils/Local.cpp:1.54
--- llvm/lib/Transforms/Utils/Local.cpp:1.53	Thu Mar  9 16:38:10 2006
+++ llvm/lib/Transforms/Utils/Local.cpp	Sat Apr  1 21:35:01 2006
@@ -308,6 +308,7 @@
 
   if (CallInst *CI = dyn_cast<CallInst>(I))
     if (Function *F = CI->getCalledFunction()) {
+      unsigned IntrinsicID = F->getIntrinsicID();
 #define GET_SIDE_EFFECT_INFO
 #include "llvm/Intrinsics.gen"
 #undef GET_SIDE_EFFECT_INFO





From lattner at cs.uiuc.edu  Sat Apr  1 21:35:42 2006
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Sat, 1 Apr 2006 21:35:42 -0600
Subject: [llvm-commits] CVS: llvm/utils/TableGen/IntrinsicEmitter.cpp 
Message-ID: <200604020335.VAA26635@zion.cs.uiuc.edu>



Changes in directory llvm/utils/TableGen:

IntrinsicEmitter.cpp updated: 1.19 -> 1.20
---
Log message:

Adjust the Intrinsics.gen interface a little bit


---
Diffs of the changes:  (+2 -2)

 IntrinsicEmitter.cpp |    4 ++--
 1 files changed, 2 insertions(+), 2 deletions(-)


Index: llvm/utils/TableGen/IntrinsicEmitter.cpp
diff -u llvm/utils/TableGen/IntrinsicEmitter.cpp:1.19 llvm/utils/TableGen/IntrinsicEmitter.cpp:1.20
--- llvm/utils/TableGen/IntrinsicEmitter.cpp:1.19	Thu Mar 30 22:48:26 2006
+++ llvm/utils/TableGen/IntrinsicEmitter.cpp	Sat Apr  1 21:35:30 2006
@@ -214,9 +214,9 @@
 
 void IntrinsicEmitter::
 EmitSideEffectInfo(const std::vector<CodeGenIntrinsic> &Ints, std::ostream &OS){
-  OS << "// isInstructionTriviallyDead code.\n";
+  OS << "// Return true if doesn't access or only reads memory.\n";
   OS << "#ifdef GET_SIDE_EFFECT_INFO\n";
-  OS << "  switch (F->getIntrinsicID()) {\n";
+  OS << "  switch (IntrinsicID) {\n";
   OS << "  default: break;\n";
   for (unsigned i = 0, e = Ints.size(); i != e; ++i) {
     switch (Ints[i].ModRef) {





From lattner at cs.uiuc.edu  Sat Apr  1 21:41:26 2006
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Sat, 1 Apr 2006 21:41:26 -0600
Subject: [llvm-commits] 
	CVS: llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
Message-ID: <200604020341.VAA26713@zion.cs.uiuc.edu>



Changes in directory llvm/lib/CodeGen/SelectionDAG:

SelectionDAGISel.cpp updated: 1.216 -> 1.217
---
Log message:

Intrinsics that just load from memory can be treated like loads: they don't 
have to serialize against each other.  This allows us to schedule lvx's 
across each other, for example.


---
Diffs of the changes:  (+25 -4)

 SelectionDAGISel.cpp |   29 +++++++++++++++++++++++++----
 1 files changed, 25 insertions(+), 4 deletions(-)


Index: llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.216 llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.217
--- llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.216	Sat Apr  1 21:07:27 2006
+++ llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp	Sat Apr  1 21:41:14 2006
@@ -1236,16 +1236,32 @@
   return false;
 }
 
+// IntrinsicOnlyReadsMemory - Return true if the specified intrinsic doesn't
+// have any side-effects or if it only reads memory.
+static bool IntrinsicOnlyReadsMemory(unsigned IntrinsicID) {
+#define GET_SIDE_EFFECT_INFO
+#include "llvm/Intrinsics.gen"
+#undef GET_SIDE_EFFECT_INFO
+  return false;
+}
+
 /// visitTargetIntrinsic - Lower a call of a target intrinsic to an INTRINSIC
 /// node.
 void SelectionDAGLowering::visitTargetIntrinsic(CallInst &I, 
                                                 unsigned Intrinsic) {
   bool HasChain = !IntrinsicCannotAccessMemory(Intrinsic);
+  bool OnlyLoad = HasChain && IntrinsicOnlyReadsMemory(Intrinsic);
   
   // Build the operand list.
   std::vector<SDOperand> Ops;
-  if (HasChain)   // If this intrinsic has side-effects, chainify it.
-    Ops.push_back(getRoot());
+  if (HasChain) {  // If this intrinsic has side-effects, chainify it.
+    if (OnlyLoad) {
+      // We don't need to serialize loads against other loads.
+      Ops.push_back(DAG.getRoot());
+    } else { 
+      Ops.push_back(getRoot());
+    }
+  }
   
   // Add the intrinsic ID as an integer operand.
   Ops.push_back(DAG.getConstant(Intrinsic, TLI.getPointerTy()));
@@ -1295,8 +1311,13 @@
   else
     Result = DAG.getNode(ISD::INTRINSIC_VOID, VTs, Ops);
 
-  if (HasChain)
-    DAG.setRoot(Result.getValue(Result.Val->getNumValues()-1));
+  if (HasChain) {
+    SDOperand Chain = Result.getValue(Result.Val->getNumValues()-1);
+    if (OnlyLoad)
+      PendingLoads.push_back(Chain);
+    else
+      DAG.setRoot(Chain);
+  }
   if (I.getType() != Type::VoidTy) {
     if (const PackedType *PTy = dyn_cast<PackedType>(I.getType())) {
       MVT::ValueType EVT = TLI.getValueType(PTy->getElementType());





From lattner at cs.uiuc.edu  Sat Apr  1 21:57:44 2006
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Sat, 1 Apr 2006 21:57:44 -0600
Subject: [llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp 
Message-ID: <200604020357.VAA26884@zion.cs.uiuc.edu>



Changes in directory llvm/lib/CodeGen/SelectionDAG:

LegalizeDAG.cpp updated: 1.349 -> 1.350
---
Log message:

Implement the Expand action for binary vector operations to break the binop
into elements and operate on each piece.  This allows generic vector integer
multiplies to work on PPC, though the generated code is horrible.


---
Diffs of the changes:  (+18 -1)

 LegalizeDAG.cpp |   19 ++++++++++++++++++-
 1 files changed, 18 insertions(+), 1 deletion(-)


Index: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.349 llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.350
--- llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.349	Sat Apr  1 21:07:27 2006
+++ llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp	Sat Apr  1 21:57:31 2006
@@ -1916,12 +1916,29 @@
     Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
       
     switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
-    default: assert(0 && "Operation not supported");
+    default: assert(0 && "BinOp legalize operation not supported");
     case TargetLowering::Legal: break;
     case TargetLowering::Custom:
       Tmp1 = TLI.LowerOperation(Result, DAG);
       if (Tmp1.Val) Result = Tmp1;
       break;
+    case TargetLowering::Expand: {
+      assert(MVT::isVector(Node->getValueType(0)) &&
+             "Cannot expand this binary operator!");
+      // Expand the operation into a bunch of nasty scalar code.
+      std::vector<SDOperand> Ops;
+      MVT::ValueType EltVT = MVT::getVectorBaseType(Node->getValueType(0));
+      MVT::ValueType PtrVT = TLI.getPointerTy();
+      for (unsigned i = 0, e = MVT::getVectorNumElements(Node->getValueType(0));
+           i != e; ++i) {
+        SDOperand Idx = DAG.getConstant(i, PtrVT);
+        SDOperand LHS = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, EltVT, Tmp1, Idx);
+        SDOperand RHS = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, EltVT, Tmp2, Idx);
+        Ops.push_back(DAG.getNode(Node->getOpcode(), EltVT, LHS, RHS));
+      }
+      Result = DAG.getNode(ISD::BUILD_VECTOR, Node->getValueType(0), Ops);
+      break;
+    }
     }
     break;
     





From lattner at cs.uiuc.edu  Sat Apr  1 21:59:23 2006
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Sat, 1 Apr 2006 21:59:23 -0600
Subject: [llvm-commits] CVS: llvm/lib/Target/PowerPC/README_ALTIVEC.txt 
Message-ID: <200604020359.VAA26945@zion.cs.uiuc.edu>



Changes in directory llvm/lib/Target/PowerPC:

README_ALTIVEC.txt updated: 1.9 -> 1.10
---
Log message:

add a note


---
Diffs of the changes:  (+11 -0)

 README_ALTIVEC.txt |   11 +++++++++++
 1 files changed, 11 insertions(+)


Index: llvm/lib/Target/PowerPC/README_ALTIVEC.txt
diff -u llvm/lib/Target/PowerPC/README_ALTIVEC.txt:1.9 llvm/lib/Target/PowerPC/README_ALTIVEC.txt:1.10
--- llvm/lib/Target/PowerPC/README_ALTIVEC.txt:1.9	Fri Mar 31 13:00:22 2006
+++ llvm/lib/Target/PowerPC/README_ALTIVEC.txt	Sat Apr  1 21:59:11 2006
@@ -137,3 +137,14 @@
 
 Handle VECTOR_SHUFFLE nodes with the appropriate shuffle mask with vsldoi,
 vpkuhum and vpkuwum.
+
+//===----------------------------------------------------------------------===//
+
+Implement multiply for vector integer types, to avoid the horrible scalarized
+code produced by legalize.
+
+void test(vector int *X, vector int *Y) {
+  *X = *X * *Y;
+}
+
+//===----------------------------------------------------------------------===//





From lattner at cs.uiuc.edu  Sat Apr  1 23:06:17 2006
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Sat, 1 Apr 2006 23:06:17 -0600
Subject: [llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp 
Message-ID: <200604020506.XAA27332@zion.cs.uiuc.edu>



Changes in directory llvm/lib/CodeGen/SelectionDAG:

LegalizeDAG.cpp updated: 1.350 -> 1.351
---
Log message:

Implement promotion for EXTRACT_VECTOR_ELT, allowing v16i8 multiplies to work with PowerPC.



---
Diffs of the changes:  (+27 -16)

 LegalizeDAG.cpp |   43 +++++++++++++++++++++++++++----------------
 1 files changed, 27 insertions(+), 16 deletions(-)


Index: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.350 llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.351
--- llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.350	Sat Apr  1 21:57:31 2006
+++ llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp	Sat Apr  1 23:06:04 2006
@@ -194,6 +194,7 @@
                         SDOperand &Lo, SDOperand &Hi);
 
   SDOperand LowerVEXTRACT_VECTOR_ELT(SDOperand Op);
+  SDOperand ExpandEXTRACT_VECTOR_ELT(SDOperand Op);
   
   SDOperand getIntPtrConstant(uint64_t Val) {
     return DAG.getConstant(Val, TLI.getPointerTy());
@@ -901,24 +902,10 @@
         break;
       }
       // FALLTHROUGH
-    case TargetLowering::Expand: {
-      // If the target doesn't support this, store the value to a temporary
-      // stack slot, then LOAD the scalar element back out.
-      SDOperand StackPtr = CreateStackTemporary(Tmp1.getValueType());
-      SDOperand Ch = DAG.getNode(ISD::STORE, MVT::Other, DAG.getEntryNode(),
-                                 Tmp1, StackPtr, DAG.getSrcValue(NULL));
-      
-      // Add the offset to the index.
-      unsigned EltSize = MVT::getSizeInBits(Result.getValueType())/8;
-      Tmp2 = DAG.getNode(ISD::MUL, Tmp2.getValueType(), Tmp2,
-                         DAG.getConstant(EltSize, Tmp2.getValueType()));
-      StackPtr = DAG.getNode(ISD::ADD, Tmp2.getValueType(), Tmp2, StackPtr);
-      
-      Result = DAG.getLoad(Result.getValueType(), Ch, StackPtr,
-                              DAG.getSrcValue(NULL));
+    case TargetLowering::Expand:
+      Result = ExpandEXTRACT_VECTOR_ELT(Result);
       break;
     }
-    }
     break;
 
   case ISD::VEXTRACT_VECTOR_ELT: 
@@ -2990,6 +2977,9 @@
   case ISD::VEXTRACT_VECTOR_ELT:
     Result = PromoteOp(LowerVEXTRACT_VECTOR_ELT(Op));
     break;
+  case ISD::EXTRACT_VECTOR_ELT:
+    Result = PromoteOp(ExpandEXTRACT_VECTOR_ELT(Op));
+    break;
   }
 
   assert(Result.Val && "Didn't set a result!");
@@ -3048,6 +3038,27 @@
   }
 }
 
+/// ExpandEXTRACT_VECTOR_ELT - Expand an EXTRACT_VECTOR_ELT operation into
+/// memory traffic.
+SDOperand SelectionDAGLegalize::ExpandEXTRACT_VECTOR_ELT(SDOperand Op) {
+  SDOperand Vector = Op.getOperand(0);
+  SDOperand Idx    = Op.getOperand(1);
+  
+  // If the target doesn't support this, store the value to a temporary
+  // stack slot, then LOAD the scalar element back out.
+  SDOperand StackPtr = CreateStackTemporary(Vector.getValueType());
+  SDOperand Ch = DAG.getNode(ISD::STORE, MVT::Other, DAG.getEntryNode(),
+                             Vector, StackPtr, DAG.getSrcValue(NULL));
+  
+  // Add the offset to the index.
+  unsigned EltSize = MVT::getSizeInBits(Op.getValueType())/8;
+  Idx = DAG.getNode(ISD::MUL, Idx.getValueType(), Idx,
+                    DAG.getConstant(EltSize, Idx.getValueType()));
+  StackPtr = DAG.getNode(ISD::ADD, Idx.getValueType(), Idx, StackPtr);
+  
+  return DAG.getLoad(Op.getValueType(), Ch, StackPtr, DAG.getSrcValue(NULL));
+}
+
 
 /// LegalizeSetCCOperands - Attempts to create a legal LHS and RHS for a SETCC
 /// with condition CC on the current target.  This usually involves legalizing





From jeffc at jolt-lang.org  Sat Apr  1 23:21:06 2006
From: jeffc at jolt-lang.org (Jeff Cohen)
Date: Sat, 1 Apr 2006 23:21:06 -0600
Subject: [llvm-commits] CVS: llvm/win32/VMCore/VMCore.vcproj 
Message-ID: <200604020521.XAA27381@zion.cs.uiuc.edu>



Changes in directory llvm/win32/VMCore:

VMCore.vcproj updated: 1.19 -> 1.20
---
Log message:

Fix tablegen related dependencies in Visual Studio.

---
Diffs of the changes:  (+8 -8)

 VMCore.vcproj |   16 ++++++++--------
 1 files changed, 8 insertions(+), 8 deletions(-)


Index: llvm/win32/VMCore/VMCore.vcproj
diff -u llvm/win32/VMCore/VMCore.vcproj:1.19 llvm/win32/VMCore/VMCore.vcproj:1.20
--- llvm/win32/VMCore/VMCore.vcproj:1.19	Mon Mar 27 22:01:27 2006
+++ llvm/win32/VMCore/VMCore.vcproj	Sat Apr  1 23:20:52 2006
@@ -157,7 +157,7 @@
 						Description="Performing TableGen Step"
 						CommandLine="..\$(IntDir)\TableGen.exe -gen-intrinsic -I ..\..\include $(InputPath) -o $(SolutionDir)llvm\intrinsics.gen
 "
-						AdditionalDependencies="$(ProjectDir)..\$(IntDir)\TableGen.exe $(InputDir)IntrinsicsX86.td $(InputDir)IntrinsicsPowerPC.td"
+						AdditionalDependencies="$(ProjectDir)..\$(IntDir)\TableGen.exe;$(InputDir)IntrinsicsX86.td;$(InputDir)IntrinsicsPowerPC.td"
 						Outputs="$(SolutionDir)llvm\intrinsics.gen"/>
 				</FileConfiguration>
 				<FileConfiguration
@@ -167,17 +167,11 @@
 						Description="Performing TableGen Step"
 						CommandLine="..\$(IntDir)\TableGen.exe -gen-intrinsic -I ..\..\include $(InputPath) -o $(SolutionDir)llvm\intrinsics.gen
 "
-						AdditionalDependencies="$(ProjectDir)..\$(IntDir)\TableGen.exe $(InputDir)IntrinsicsX86.td $(InputDir)IntrinsicsPowerPC.td"
+						AdditionalDependencies="$(ProjectDir)..\$(IntDir)\TableGen.exe;$(InputDir)IntrinsicsX86.td;$(InputDir)IntrinsicsPowerPC.td"
 						Outputs="$(SolutionDir)llvm\intrinsics.gen"/>
 				</FileConfiguration>
 			</File>
 			<File
-				RelativePath="..\..\include\llvm\IntrinsicsPowerPC.td">
-			</File>
-			<File
-				RelativePath="..\..\include\llvm\IntrinsicsX86.td">
-			</File>
-			<File
 				RelativePath="..\..\lib\VMCore\LeakDetector.cpp">
 			</File>
 			<File
@@ -279,6 +273,12 @@
 				RelativePath="..\..\include\llvm\Intrinsics.h">
 			</File>
 			<File
+				RelativePath="..\..\include\llvm\IntrinsicsPowerPC.td">
+			</File>
+			<File
+				RelativePath="..\..\include\llvm\IntrinsicsX86.td">
+			</File>
+			<File
 				RelativePath="..\..\include\llvm\Linker.h">
 			</File>
 			<File





From jeffc at jolt-lang.org  Sat Apr  1 23:21:06 2006
From: jeffc at jolt-lang.org (Jeff Cohen)
Date: Sat, 1 Apr 2006 23:21:06 -0600
Subject: [llvm-commits] CVS: llvm/win32/x86/x86.vcproj 
Message-ID: <200604020521.XAA27385@zion.cs.uiuc.edu>



Changes in directory llvm/win32/x86:

x86.vcproj updated: 1.22 -> 1.23
---
Log message:

Fix tablegen related dependencies in Visual Studio.

---
Diffs of the changes:  (+19 -2)

 x86.vcproj |   21 +++++++++++++++++++--
 1 files changed, 19 insertions(+), 2 deletions(-)


Index: llvm/win32/x86/x86.vcproj
diff -u llvm/win32/x86/x86.vcproj:1.22 llvm/win32/x86/x86.vcproj:1.23
--- llvm/win32/x86/x86.vcproj:1.22	Fri Mar  3 20:19:46 2006
+++ llvm/win32/x86/x86.vcproj	Sat Apr  1 23:20:53 2006
@@ -124,7 +124,8 @@
 ..\$(IntDir)\TableGen.exe -gen-asm-writer -I ..\..\lib\Target\X86 -I ..\..\include $(InputPath) -o X86GenAsmWriter.inc
 ..\$(IntDir)\TableGen.exe -gen-asm-writer -asmwriternum=1 -I ..\..\lib\Target\X86 -I ..\..\include $(InputPath) -o X86GenAsmWriter1.inc
 ..\$(IntDir)\TableGen.exe -gen-dag-isel -I ..\..\lib\Target\X86 -I ..\..\include $(InputPath) -o X86GenDAGISel.inc
-..\$(IntDir)\TableGen.exe -gen-subtarget -I ..\..\lib\Target\X86 -I ..\..\include $(InputPath) -o X86GenSubtarget.inc"
+..\$(IntDir)\TableGen.exe -gen-subtarget -I ..\..\lib\Target\X86 -I ..\..\include $(InputPath) -o X86GenSubtarget.inc
+"
 						AdditionalDependencies="$(InputDir)X86InstrInfo.td;$(InputDir)X86RegisterInfo.td;$(InputDir)..\Target.td;$(ProjectDir)..\$(IntDir)\TableGen.exe"
 						Outputs="X86GenRegisterNames.inc;X86GenRegisterInfo.h.inc;X86GenRegisterInfo.inc;X86GenInstrNames.inc;X86GenInstrInfo.inc;X86GenAsmWriter.inc;X86GenAsmWriter1.inc;X86GenDAGISel.inc;X86GenSubtarget.inc"/>
 				</FileConfiguration>
@@ -141,7 +142,8 @@
 ..\$(IntDir)\TableGen.exe -gen-asm-writer -I ..\..\lib\Target\X86 -I ..\..\include $(InputPath) -o X86GenAsmWriter.inc
 ..\$(IntDir)\TableGen.exe -gen-asm-writer -asmwriternum=1 -I ..\..\lib\Target\X86 -I ..\..\include $(InputPath) -o X86GenAsmWriter1.inc
 ..\$(IntDir)\TableGen.exe -gen-dag-isel -I ..\..\lib\Target\X86 -I ..\..\include $(InputPath) -o X86GenDAGISel.inc
-..\$(IntDir)\TableGen.exe -gen-subtarget -I ..\..\lib\Target\X86 -I ..\..\include $(InputPath) -o X86GenSubtarget.inc"
+..\$(IntDir)\TableGen.exe -gen-subtarget -I ..\..\lib\Target\X86 -I ..\..\include $(InputPath) -o X86GenSubtarget.inc
+"
 						AdditionalDependencies="$(InputDir)X86InstrInfo.td;$(InputDir)X86RegisterInfo.td;$(InputDir)..\Target.td;$(ProjectDir)..\$(IntDir)\TableGen.exe"
 						Outputs="X86GenRegisterNames.inc;X86GenRegisterInfo.h.inc;X86GenRegisterInfo.inc;X86GenInstrNames.inc;X86GenInstrInfo.inc;X86GenAsmWriter.inc;X86GenAsmWriter1.inc;X86GenDAGISel.inc;X86GenSubtarget.inc"/>
 				</FileConfiguration>
@@ -194,6 +196,12 @@
 				RelativePath="..\..\lib\Target\Target.td">
 			</File>
 			<File
+				RelativePath="..\..\lib\Target\TargetSchedule.td">
+			</File>
+			<File
+				RelativePath="..\..\lib\Target\TargetSelectionDAG.td">
+			</File>
+			<File
 				RelativePath="..\..\lib\Target\X86\X86.h">
 			</File>
 			<File
@@ -203,12 +211,21 @@
 				RelativePath="..\..\lib\Target\X86\X86InstrBuilder.h">
 			</File>
 			<File
+				RelativePath="..\..\lib\Target\X86\X86InstrFPStack.td">
+			</File>
+			<File
 				RelativePath="..\..\lib\Target\X86\X86InstrInfo.h">
 			</File>
 			<File
 				RelativePath="..\..\lib\Target\X86\X86InstrInfo.td">
 			</File>
 			<File
+				RelativePath="..\..\lib\Target\X86\X86InstrMMX.td">
+			</File>
+			<File
+				RelativePath="..\..\lib\Target\X86\X86InstrSSE.td">
+			</File>
+			<File
 				RelativePath="..\..\lib\Target\X86\X86IntelAsmPrinter.h">
 			</File>
 			<File





From lattner at cs.uiuc.edu  Sat Apr  1 23:29:07 2006
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Sat, 1 Apr 2006 23:29:07 -0600
Subject: [llvm-commits] CVS: llvm/lib/Target/PowerPC/README_ALTIVEC.txt 
Message-ID: <200604020529.XAA27537@zion.cs.uiuc.edu>



Changes in directory llvm/lib/Target/PowerPC:

README_ALTIVEC.txt updated: 1.10 -> 1.11
---
Log message:

Remove done item


---
Diffs of the changes:  (+0 -5)

 README_ALTIVEC.txt |    5 -----
 1 files changed, 5 deletions(-)


Index: llvm/lib/Target/PowerPC/README_ALTIVEC.txt
diff -u llvm/lib/Target/PowerPC/README_ALTIVEC.txt:1.10 llvm/lib/Target/PowerPC/README_ALTIVEC.txt:1.11
--- llvm/lib/Target/PowerPC/README_ALTIVEC.txt:1.10	Sat Apr  1 21:59:11 2006
+++ llvm/lib/Target/PowerPC/README_ALTIVEC.txt	Sat Apr  1 23:28:54 2006
@@ -112,11 +112,6 @@
 
 //===----------------------------------------------------------------------===//
 
-We should instcombine the lvx/stvx intrinsics into loads/stores if we know that
-the loaded address is 16-byte aligned.
-
-//===----------------------------------------------------------------------===//
-
 Instead of writting a pattern for type-agnostic operations (e.g. gen-zero, load,
 store, and, ...) in every supported type, make legalize do the work.  We should
 have a canonical type that we want operations changed to (e.g. v4i32 for





From lattner at cs.uiuc.edu  Sat Apr  1 23:30:38 2006
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Sat, 1 Apr 2006 23:30:38 -0600
Subject: [llvm-commits] 
	CVS: llvm/lib/Transforms/Scalar/InstructionCombining.cpp
Message-ID: <200604020530.XAA27595@zion.cs.uiuc.edu>



Changes in directory llvm/lib/Transforms/Scalar:

InstructionCombining.cpp updated: 1.458 -> 1.459
---
Log message:

Turn altivec lvx/stvx intrinsics into loads and stores.  This allows the
elimination of one load from this:

int AreSecondAndThirdElementsBothNegative( vector float *in ) {
#define QNaN 0x7FC00000
const vector unsigned int testData = (vector unsigned int)( QNaN, 0, 0, QNaN );
vector float test = vec_ld( 0, (float*) &testData );
return ! vec_any_ge( test, *in );
}

Now generating:

_AreSecondAndThirdElementsBothNegative:
        mfspr r2, 256
        oris r4, r2, 49152
        mtspr 256: http://llvm.cs.uiuc.edu/PR256 , r4
        li r4, lo16(LCPI1_0)
        lis r5, ha16(LCPI1_0)
        addi r6, r1, -16
        lvx v0, r5, r4
        stvx v0, 0, r6
        lvx v1, 0, r3
        vcmpgefp. v0, v0, v1
        mfcr r3, 2
        rlwinm r3, r3, 27, 31, 31
        xori r3, r3, 1
        cntlzw r3, r3
        srwi r3, r3, 5
        mtspr 256: http://llvm.cs.uiuc.edu/PR256 , r2
        blr



---
Diffs of the changes:  (+22 -0)

 InstructionCombining.cpp |   22 ++++++++++++++++++++++
 1 files changed, 22 insertions(+)


Index: llvm/lib/Transforms/Scalar/InstructionCombining.cpp
diff -u llvm/lib/Transforms/Scalar/InstructionCombining.cpp:1.458 llvm/lib/Transforms/Scalar/InstructionCombining.cpp:1.459
--- llvm/lib/Transforms/Scalar/InstructionCombining.cpp:1.458	Sat Apr  1 16:05:01 2006
+++ llvm/lib/Transforms/Scalar/InstructionCombining.cpp	Sat Apr  1 23:30:25 2006
@@ -5437,6 +5437,28 @@
   } else {
     switch (II->getIntrinsicID()) {
     default: break;
+    case Intrinsic::ppc_altivec_lvx:
+    case Intrinsic::ppc_altivec_lvxl:
+      // Turn lvx -> load if the pointer is known aligned.
+      if (GetKnownAlignment(II->getOperand(1), TD) >= 16) {
+        Instruction *Ptr = new CastInst(II->getOperand(1), 
+                                        PointerType::get(II->getType()), "tmp");
+        InsertNewInstBefore(Ptr, CI);
+        return new LoadInst(Ptr);
+      }
+      break;
+    case Intrinsic::ppc_altivec_stvx:
+    case Intrinsic::ppc_altivec_stvxl:
+      // Turn stvx -> store if the pointer is known aligned.
+      if (GetKnownAlignment(II->getOperand(2), TD) >= 16) {
+        const Type *OpTy = II->getOperand(1)->getType();
+        Instruction *Ptr = new CastInst(II->getOperand(2), 
+                                        PointerType::get(OpTy), "tmp");
+        InsertNewInstBefore(Ptr, CI);
+        return new StoreInst(II->getOperand(1), Ptr);
+      }
+      break;
+      
     case Intrinsic::stackrestore: {
       // If the save is right next to the restore, remove the restore.  This can
       // happen when variable allocas are DCE'd.





From lattner at cs.uiuc.edu  Sat Apr  1 23:37:24 2006
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Sat, 1 Apr 2006 23:37:24 -0600
Subject: [llvm-commits] 
	CVS: llvm/lib/Transforms/Scalar/InstructionCombining.cpp
Message-ID: <200604020537.XAA27765@zion.cs.uiuc.edu>



Changes in directory llvm/lib/Transforms/Scalar:

InstructionCombining.cpp updated: 1.459 -> 1.460
---
Log message:

Allow transforming this:

        %tmp = cast <4 x uint>* %testData to <4 x int>*         ; <<4 x int>*> [#uses=1]
        %tmp = load <4 x int>* %tmp             ; <<4 x int>> [#uses=1]

to this:

        %tmp = load <4 x uint>* %testData               ; <<4 x uint>> [#uses=1]
        %tmp = cast <4 x uint> %tmp to <4 x int>                ; <<4 x int>> [#uses=1]



---
Diffs of the changes:  (+4 -2)

 InstructionCombining.cpp |    6 ++++--
 1 files changed, 4 insertions(+), 2 deletions(-)


Index: llvm/lib/Transforms/Scalar/InstructionCombining.cpp
diff -u llvm/lib/Transforms/Scalar/InstructionCombining.cpp:1.459 llvm/lib/Transforms/Scalar/InstructionCombining.cpp:1.460
--- llvm/lib/Transforms/Scalar/InstructionCombining.cpp:1.459	Sat Apr  1 23:30:25 2006
+++ llvm/lib/Transforms/Scalar/InstructionCombining.cpp	Sat Apr  1 23:37:12 2006
@@ -6234,7 +6234,8 @@
   if (const PointerType *SrcTy = dyn_cast<PointerType>(CastOp->getType())) {
     const Type *SrcPTy = SrcTy->getElementType();
 
-    if (DestPTy->isInteger() || isa<PointerType>(DestPTy)) {
+    if (DestPTy->isInteger() || isa<PointerType>(DestPTy) || 
+        isa<PackedType>(DestPTy)) {
       // If the source is an array, the code below will not succeed.  Check to
       // see if a trivial 'gep P, 0, 0' will help matters.  Only do this for
       // constants.
@@ -6247,7 +6248,8 @@
             SrcPTy = SrcTy->getElementType();
           }
 
-      if ((SrcPTy->isInteger() || isa<PointerType>(SrcPTy)) &&
+      if ((SrcPTy->isInteger() || isa<PointerType>(SrcPTy) || 
+           isa<PackedType>(SrcPTy)) &&
           // Do not allow turning this into a load of an integer, which is then
           // casted to a pointer, this pessimizes pointer analysis a lot.
           (isa<PointerType>(SrcPTy) == isa<PointerType>(LI.getType())) &&





From lattner at cs.uiuc.edu  Sat Apr  1 23:40:41 2006
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Sat, 1 Apr 2006 23:40:41 -0600
Subject: [llvm-commits] CVS: llvm/lib/VMCore/Type.cpp 
Message-ID: <200604020540.XAA27884@zion.cs.uiuc.edu>



Changes in directory llvm/lib/VMCore:

Type.cpp updated: 1.137 -> 1.138
---
Log message:

vector casts never reinterpret bits


---
Diffs of the changes:  (+5 -0)

 Type.cpp |    5 +++++
 1 files changed, 5 insertions(+)


Index: llvm/lib/VMCore/Type.cpp
diff -u llvm/lib/VMCore/Type.cpp:1.137 llvm/lib/VMCore/Type.cpp:1.138
--- llvm/lib/VMCore/Type.cpp:1.137	Wed Nov 16 00:09:47 2005
+++ llvm/lib/VMCore/Type.cpp	Sat Apr  1 23:40:28 2006
@@ -75,6 +75,11 @@
 //
 bool Type::isLosslesslyConvertibleTo(const Type *Ty) const {
   if (this == Ty) return true;
+  
+  // Packed type conversions are always bitwise.
+  if (isa<PackedType>(this) && isa<PackedType>(Ty))
+    return true;
+  
   if ((!isPrimitiveType()    && !isa<PointerType>(this)) ||
       (!isa<PointerType>(Ty) && !Ty->isPrimitiveType())) return false;
 





From lattner at cs.uiuc.edu  Sat Apr  1 23:43:26 2006
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Sat, 1 Apr 2006 23:43:26 -0600
Subject: [llvm-commits] 
	CVS: llvm/lib/Transforms/Scalar/InstructionCombining.cpp
Message-ID: <200604020543.XAA27979@zion.cs.uiuc.edu>



Changes in directory llvm/lib/Transforms/Scalar:

InstructionCombining.cpp updated: 1.460 -> 1.461
---
Log message:

vector casts of casts are eliminable.  Transform this:

        %tmp = cast <4 x uint> %tmp to <4 x int>                ; <<4 x int>> [#uses=1]
        %tmp = cast <4 x int> %tmp to <4 x float>               ; <<4 x float>> [#uses=1]

into:

        %tmp = cast <4 x uint> %tmp to <4 x float>              ; <<4 x float>> [#uses=1]



---
Diffs of the changes:  (+4 -0)

 InstructionCombining.cpp |    4 ++++
 1 files changed, 4 insertions(+)


Index: llvm/lib/Transforms/Scalar/InstructionCombining.cpp
diff -u llvm/lib/Transforms/Scalar/InstructionCombining.cpp:1.460 llvm/lib/Transforms/Scalar/InstructionCombining.cpp:1.461
--- llvm/lib/Transforms/Scalar/InstructionCombining.cpp:1.460	Sat Apr  1 23:37:12 2006
+++ llvm/lib/Transforms/Scalar/InstructionCombining.cpp	Sat Apr  1 23:43:13 2006
@@ -4539,6 +4539,10 @@
       SrcTy->getPrimitiveSize() < MidTy->getPrimitiveSize())
     return true;
   
+  // Packed type conversions don't modify bits.
+  if (isa<PackedType>(SrcTy) && isa<PackedType>(MidTy) &&isa<PackedType>(DstTy))
+    return true;
+  
   return false;
 }
 





From lattner at cs.uiuc.edu  Sun Apr  2 00:11:23 2006
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Sun, 2 Apr 2006 00:11:23 -0600
Subject: [llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp 
Message-ID: <200604020611.AAA28446@zion.cs.uiuc.edu>



Changes in directory llvm/lib/CodeGen/SelectionDAG:

DAGCombiner.cpp updated: 1.138 -> 1.139
---
Log message:

Add a little dag combine to compile this:

int %AreSecondAndThirdElementsBothNegative(<4 x float>* %in) {
entry:
        %tmp1 = load <4 x float>* %in           ; <<4 x float>> [#uses=1]
        %tmp = tail call int %llvm.ppc.altivec.vcmpgefp.p( int 1, <4 x float> < float 0x7FF8000000000000, float 0.000000e+00, float 0.000000e+00, float 0x7FF8000000000000 >, <4 x float> %tmp1 )           ; <int> [#uses=1]
        %tmp = seteq int %tmp, 0                ; <bool> [#uses=1]
        %tmp3 = cast bool %tmp to int           ; <int> [#uses=1]
        ret int %tmp3
}

into this:

_AreSecondAndThirdElementsBothNegative:
        mfspr r2, 256
        oris r4, r2, 49152
        mtspr 256: http://llvm.cs.uiuc.edu/PR256 , r4
        li r4, lo16(LCPI1_0)
        lis r5, ha16(LCPI1_0)
        lvx v0, 0, r3
        lvx v1, r5, r4
        vcmpgefp. v0, v1, v0
        mfcr r3, 2
        rlwinm r3, r3, 27, 31, 31
        mtspr 256: http://llvm.cs.uiuc.edu/PR256 , r2
        blr

instead of this:

_AreSecondAndThirdElementsBothNegative:
        mfspr r2, 256
        oris r4, r2, 49152
        mtspr 256: http://llvm.cs.uiuc.edu/PR256 , r4
        li r4, lo16(LCPI1_0)
        lis r5, ha16(LCPI1_0)
        lvx v0, 0, r3
        lvx v1, r5, r4
        vcmpgefp. v0, v1, v0
        mfcr r3, 2
        rlwinm r3, r3, 27, 31, 31
        xori r3, r3, 1
        cntlzw r3, r3
        srwi r3, r3, 5
        mtspr 256: http://llvm.cs.uiuc.edu/PR256 , r2
        blr



---
Diffs of the changes:  (+33 -0)

 DAGCombiner.cpp |   33 +++++++++++++++++++++++++++++++++
 1 files changed, 33 insertions(+)


Index: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.138 llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.139
--- llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.138	Sat Apr  1 21:25:57 2006
+++ llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp	Sun Apr  2 00:11:11 2006
@@ -1601,6 +1601,39 @@
     return DAG.getNode(ISD::SRL, VT, N0.getOperand(0), 
                        DAG.getConstant(c1 + c2, N1.getValueType()));
   }
+  
+  // fold (srl (ctlz x), "5") -> x  iff x has one bit set (the low bit).
+  if (N1C && N0.getOpcode() == ISD::CTLZ && 
+      N1C->getValue() == Log2_32(MVT::getSizeInBits(VT))) {
+    uint64_t KnownZero, KnownOne, Mask = MVT::getIntVTBitMask(VT);
+    TLI.ComputeMaskedBits(N0.getOperand(0), Mask, KnownZero, KnownOne);
+    
+    // If any of the input bits are KnownOne, then the input couldn't be all
+    // zeros, thus the result of the srl will always be zero.
+    if (KnownOne) return DAG.getConstant(0, VT);
+    
+    // If all of the bits input the to ctlz node are known to be zero, then
+    // the result of the ctlz is "32" and the result of the shift is one.
+    uint64_t UnknownBits = ~KnownZero & Mask;
+    if (UnknownBits == 0) return DAG.getConstant(1, VT);
+    
+    // Otherwise, check to see if there is exactly one bit input to the ctlz.
+    if ((UnknownBits & (UnknownBits-1)) == 0) {
+      // Okay, we know that only that the single bit specified by UnknownBits
+      // could be set on input to the CTLZ node.  If this bit is set, the SRL
+      // will return 0, if it is clear, it returns 1.  Change the CTLZ/SRL pair
+      // to an SRL,XOR pair, which is likely to simplify more.
+      unsigned ShAmt = CountTrailingZeros_64(UnknownBits);
+      SDOperand Op = N0.getOperand(0);
+      if (ShAmt) {
+        Op = DAG.getNode(ISD::SRL, VT, Op,
+                         DAG.getConstant(ShAmt, TLI.getShiftAmountTy()));
+        AddToWorkList(Op.Val);
+      }
+      return DAG.getNode(ISD::XOR, VT, Op, DAG.getConstant(1, VT));
+    }
+  }
+  
   return SDOperand();
 }
 





From lattner at cs.uiuc.edu  Sun Apr  2 00:15:21 2006
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Sun, 2 Apr 2006 00:15:21 -0600
Subject: [llvm-commits] CVS: llvm/lib/Target/TargetLowering.cpp 
Message-ID: <200604020615.AAA28514@zion.cs.uiuc.edu>



Changes in directory llvm/lib/Target:

TargetLowering.cpp updated: 1.51 -> 1.52
---
Log message:

Allow targets to compute masked bits for intrinsics.


---
Diffs of the changes:  (+9 -4)

 TargetLowering.cpp |   13 +++++++++----
 1 files changed, 9 insertions(+), 4 deletions(-)


Index: llvm/lib/Target/TargetLowering.cpp
diff -u llvm/lib/Target/TargetLowering.cpp:1.51 llvm/lib/Target/TargetLowering.cpp:1.52
--- llvm/lib/Target/TargetLowering.cpp:1.51	Thu Mar 30 19:50:09 2006
+++ llvm/lib/Target/TargetLowering.cpp	Sun Apr  2 00:15:09 2006
@@ -619,9 +619,10 @@
   }
   case ISD::ADD:
   case ISD::SUB:
-    // Just use ComputeMaskedBits to compute output bits, there are no
-    // simplifications that can be done here, and sub always demands all input
-    // bits.
+  case ISD::INTRINSIC_WO_CHAIN:
+  case ISD::INTRINSIC_W_CHAIN:
+  case ISD::INTRINSIC_VOID:
+    // Just use ComputeMaskedBits to compute output bits.
     ComputeMaskedBits(Op, DemandedMask, KnownZero, KnownOne, Depth);
     break;
   }
@@ -916,8 +917,12 @@
   }
   default:
     // Allow the target to implement this method for its nodes.
-    if (Op.getOpcode() >= ISD::BUILTIN_OP_END)
+    if (Op.getOpcode() >= ISD::BUILTIN_OP_END) {
+  case ISD::INTRINSIC_WO_CHAIN:
+  case ISD::INTRINSIC_W_CHAIN:
+  case ISD::INTRINSIC_VOID:
       computeMaskedBitsForTargetNode(Op, Mask, KnownZero, KnownOne);
+    }
     return;
   }
 }





From lattner at cs.uiuc.edu  Sun Apr  2 00:19:59 2006
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Sun, 2 Apr 2006 00:19:59 -0600
Subject: [llvm-commits] CVS: llvm/lib/Target/TargetLowering.cpp 
Message-ID: <200604020619.AAA28555@zion.cs.uiuc.edu>



Changes in directory llvm/lib/Target:

TargetLowering.cpp updated: 1.52 -> 1.53
---
Log message:

relax assertion


---
Diffs of the changes:  (+4 -1)

 TargetLowering.cpp |    5 ++++-
 1 files changed, 4 insertions(+), 1 deletion(-)


Index: llvm/lib/Target/TargetLowering.cpp
diff -u llvm/lib/Target/TargetLowering.cpp:1.52 llvm/lib/Target/TargetLowering.cpp:1.53
--- llvm/lib/Target/TargetLowering.cpp:1.52	Sun Apr  2 00:15:09 2006
+++ llvm/lib/Target/TargetLowering.cpp	Sun Apr  2 00:19:46 2006
@@ -935,7 +935,10 @@
                                                     uint64_t &KnownZero, 
                                                     uint64_t &KnownOne,
                                                     unsigned Depth) const {
-  assert(Op.getOpcode() >= ISD::BUILTIN_OP_END &&
+  assert((Op.getOpcode() >= ISD::BUILTIN_OP_END ||
+          Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN ||
+          Op.getOpcode() == ISD::INTRINSIC_W_CHAIN ||
+          Op.getOpcode() == ISD::INTRINSIC_VOID) &&
          "Should use MaskedValueIsZero if you don't know whether Op"
          " is a target node!");
   KnownZero = 0;





From lattner at cs.uiuc.edu  Sun Apr  2 00:26:20 2006
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Sun, 2 Apr 2006 00:26:20 -0600
Subject: [llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCISelLowering.cpp
	PPCISelLowering.h 
Message-ID: <200604020626.AAA28628@zion.cs.uiuc.edu>



Changes in directory llvm/lib/Target/PowerPC:

PPCISelLowering.cpp updated: 1.125 -> 1.126
PPCISelLowering.h updated: 1.37 -> 1.38
---
Log message:

Inform the dag combiner that the predicate compares only return a low bit.


---
Diffs of the changes:  (+39 -1)

 PPCISelLowering.cpp |   35 ++++++++++++++++++++++++++++++++++-
 PPCISelLowering.h   |    5 +++++
 2 files changed, 39 insertions(+), 1 deletion(-)


Index: llvm/lib/Target/PowerPC/PPCISelLowering.cpp
diff -u llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.125 llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.126
--- llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.125	Sat Apr  1 18:43:36 2006
+++ llvm/lib/Target/PowerPC/PPCISelLowering.cpp	Sun Apr  2 00:26:07 2006
@@ -760,7 +760,7 @@
     return DAG.getNode(PPCISD::VPERM, V1.getValueType(), V1, V2, VPermMask);
   }
   case ISD::INTRINSIC_WO_CHAIN: {
-    unsigned IntNo=cast<ConstantSDNode>(Op.getOperand(0))->getValue();
+    unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getValue();
     
     // If this is a lowered altivec predicate compare, CompareOpc is set to the
     // opcode number of the comparison.
@@ -1409,6 +1409,39 @@
   return SDOperand();
 }
 
+void PPCTargetLowering::computeMaskedBitsForTargetNode(const SDOperand Op,
+                                                       uint64_t Mask,
+                                                       uint64_t &KnownZero, 
+                                                       uint64_t &KnownOne,
+                                                       unsigned Depth) const {
+  KnownZero = 0;
+  KnownOne = 0;
+  switch (Op.getOpcode()) {
+  default: break;
+  case ISD::INTRINSIC_WO_CHAIN: {
+    switch (cast<ConstantSDNode>(Op.getOperand(0))->getValue()) {
+    default: break;
+    case Intrinsic::ppc_altivec_vcmpbfp_p:
+    case Intrinsic::ppc_altivec_vcmpeqfp_p:
+    case Intrinsic::ppc_altivec_vcmpequb_p:
+    case Intrinsic::ppc_altivec_vcmpequh_p:
+    case Intrinsic::ppc_altivec_vcmpequw_p:
+    case Intrinsic::ppc_altivec_vcmpgefp_p:
+    case Intrinsic::ppc_altivec_vcmpgtfp_p:
+    case Intrinsic::ppc_altivec_vcmpgtsb_p:
+    case Intrinsic::ppc_altivec_vcmpgtsh_p:
+    case Intrinsic::ppc_altivec_vcmpgtsw_p:
+    case Intrinsic::ppc_altivec_vcmpgtub_p:
+    case Intrinsic::ppc_altivec_vcmpgtuh_p:
+    case Intrinsic::ppc_altivec_vcmpgtuw_p:
+      KnownZero = ~1U;  // All bits but the low one are known to be zero.
+      break;
+    }        
+  }
+  }
+}
+
+
 /// getConstraintType - Given a constraint letter, return the type of
 /// constraint it is for this target.
 PPCTargetLowering::ConstraintType 


Index: llvm/lib/Target/PowerPC/PPCISelLowering.h
diff -u llvm/lib/Target/PowerPC/PPCISelLowering.h:1.37 llvm/lib/Target/PowerPC/PPCISelLowering.h:1.38
--- llvm/lib/Target/PowerPC/PPCISelLowering.h:1.37	Thu Mar 30 23:13:27 2006
+++ llvm/lib/Target/PowerPC/PPCISelLowering.h	Sun Apr  2 00:26:07 2006
@@ -133,6 +133,11 @@
     
     virtual SDOperand PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const;
 
+    virtual void computeMaskedBitsForTargetNode(const SDOperand Op,
+                                                uint64_t Mask,
+                                                uint64_t &KnownZero, 
+                                                uint64_t &KnownOne,
+                                                unsigned Depth = 0) const;
     /// LowerArguments - This hook must be implemented to indicate how we should
     /// lower the arguments for the specified function, into the specified DAG.
     virtual std::vector<SDOperand>





From lattner at cs.uiuc.edu  Sun Apr  2 01:20:12 2006
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Sun, 2 Apr 2006 01:20:12 -0600
Subject: [llvm-commits] CVS: llvm/lib/Target/PowerPC/README.txt 
Message-ID: <200604020720.BAA28812@zion.cs.uiuc.edu>



Changes in directory llvm/lib/Target/PowerPC:

README.txt updated: 1.83 -> 1.84
---
Log message:

add a note


---
Diffs of the changes:  (+9 -0)

 README.txt |    9 +++++++++
 1 files changed, 9 insertions(+)


Index: llvm/lib/Target/PowerPC/README.txt
diff -u llvm/lib/Target/PowerPC/README.txt:1.83 llvm/lib/Target/PowerPC/README.txt:1.84
--- llvm/lib/Target/PowerPC/README.txt:1.83	Mon Mar 27 01:04:16 2006
+++ llvm/lib/Target/PowerPC/README.txt	Sun Apr  2 01:20:00 2006
@@ -551,3 +551,12 @@
 
 ===-------------------------------------------------------------------------===
 
+extract_vector_elt of an arbitrary constant vector can be done with the 
+following instructions:
+
+vTemp = vec_splat(v0,2);    // 2 is the element the src is in.
+vec_ste(&destloc,0,vTemp);
+
+We can do an arbitrary non-constant value by using lvsr/perm/ste.
+
+===-------------------------------------------------------------------------===





From reid at x10sys.com  Sun Apr  2 09:34:38 2006
From: reid at x10sys.com (Reid Spencer)
Date: Sun, 2 Apr 2006 09:34:38 -0500
Subject: [llvm-commits] CVS: llvm/runtime/Makefile 
Message-ID: <200604021434.JAA04969@zion.cs.uiuc.edu>



Changes in directory llvm/runtime:

Makefile updated: 1.24 -> 1.25
---
Log message:

For PR722: http://llvm.cs.uiuc.edu/PR722 :
Change the check for llvm-gcc from using LLVMGCCDIR to LLVMGCC. This checks
for the actual tool rather than the directory in which the tool resides. In
the case of this bug, it is possible that the directory exists but that the
tools in that directory do not. This fix should avoid the makefile from
erroneously proceeding without the actual tools being available.


---
Diffs of the changes:  (+4 -4)

 Makefile |    8 ++++----
 1 files changed, 4 insertions(+), 4 deletions(-)


Index: llvm/runtime/Makefile
diff -u llvm/runtime/Makefile:1.24 llvm/runtime/Makefile:1.25
--- llvm/runtime/Makefile:1.24	Thu Jan 13 10:51:19 2005
+++ llvm/runtime/Makefile	Sun Apr  2 09:34:26 2006
@@ -10,15 +10,15 @@
 LEVEL = ..
 include $(LEVEL)/Makefile.config
 
-ifneq ($(wildcard $(LLVMGCCDIR)),)
+ifneq ($(wildcard $(LLVMGCC)),)
 PARALLEL_DIRS  := GCCLibraries  libdummy libprofile libtrace GC
 else
 PARALLEL_DIRS  := 
 install all ::
-	@echo '********' Warning: Your LLVMGCCDIR is set incorrectly.  Double-check 
+	@echo '********' Warning: Your LLVMGCCDIR is set incorrectly.  Check 
 	@echo '********' Warning: llvm/Makefile.config to make sure it matches
-	@echo '********' Warning: the directory where the C front-end is installed,
-	@echo '********' Warning: and re-run configure if it does not.
+	@echo '********' Warning: the directory where the C front-end is
+	@echo '********' Warning: installed,and re-run configure if it does not.
 endif
 
 # Disable libprofile: a faulty libtool is generated by autoconf which breaks the





From alenhar2 at cs.uiuc.edu  Sun Apr  2 15:14:20 2006
From: alenhar2 at cs.uiuc.edu (Andrew Lenharth)
Date: Sun, 2 Apr 2006 15:14:20 -0500
Subject: [llvm-commits] CVS: llvm/lib/Target/Alpha/AlphaISelLowering.cpp 
Message-ID: <200604022014.PAA11478@apoc.cs.uiuc.edu>



Changes in directory llvm/lib/Target/Alpha:

AlphaISelLowering.cpp updated: 1.41 -> 1.42
---
Log message:

This will be needed soon

---
Diffs of the changes:  (+146 -1)

 AlphaISelLowering.cpp |  147 +++++++++++++++++++++++++++++++++++++++++++++++++-
 1 files changed, 146 insertions(+), 1 deletion(-)


Index: llvm/lib/Target/Alpha/AlphaISelLowering.cpp
diff -u llvm/lib/Target/Alpha/AlphaISelLowering.cpp:1.41 llvm/lib/Target/Alpha/AlphaISelLowering.cpp:1.42
--- llvm/lib/Target/Alpha/AlphaISelLowering.cpp:1.41	Thu Mar 16 19:40:33 2006
+++ llvm/lib/Target/Alpha/AlphaISelLowering.cpp	Sun Apr  2 15:13:57 2006
@@ -25,6 +25,151 @@
 #include <iostream>
 
 using namespace llvm;
+//Shamelessly adapted from PPC32
+// Structure used to return the necessary information to codegen an SDIV as
+// a multiply.
+struct ms {
+  int64_t m; // magic number
+  int64_t s; // shift amount
+};
+
+struct mu {
+  uint64_t m; // magic number
+  int64_t a;          // add indicator
+  int64_t s;          // shift amount
+};
+
+/// magic - calculate the magic numbers required to codegen an integer sdiv as
+/// a sequence of multiply and shifts.  Requires that the divisor not be 0, 1,
+/// or -1.
+static struct ms magic(int64_t d) {
+  int64_t p;
+  uint64_t ad, anc, delta, q1, r1, q2, r2, t;
+  const uint64_t two63 = 9223372036854775808ULL; // 2^63
+  struct ms mag;
+
+  ad = llabs(d);
+  t = two63 + ((uint64_t)d >> 63);
+  anc = t - 1 - t%ad;   // absolute value of nc
+  p = 63;               // initialize p
+  q1 = two63/anc;       // initialize q1 = 2p/abs(nc)
+  r1 = two63 - q1*anc;  // initialize r1 = rem(2p,abs(nc))
+  q2 = two63/ad;        // initialize q2 = 2p/abs(d)
+  r2 = two63 - q2*ad;   // initialize r2 = rem(2p,abs(d))
+  do {
+    p = p + 1;
+    q1 = 2*q1;        // update q1 = 2p/abs(nc)
+    r1 = 2*r1;        // update r1 = rem(2p/abs(nc))
+    if (r1 >= anc) {  // must be unsigned comparison
+      q1 = q1 + 1;
+      r1 = r1 - anc;
+    }
+    q2 = 2*q2;        // update q2 = 2p/abs(d)
+    r2 = 2*r2;        // update r2 = rem(2p/abs(d))
+    if (r2 >= ad) {   // must be unsigned comparison
+      q2 = q2 + 1;
+      r2 = r2 - ad;
+    }
+    delta = ad - r2;
+  } while (q1 < delta || (q1 == delta && r1 == 0));
+
+  mag.m = q2 + 1;
+  if (d < 0) mag.m = -mag.m; // resulting magic number
+  mag.s = p - 64;            // resulting shift
+  return mag;
+}
+
+/// magicu - calculate the magic numbers required to codegen an integer udiv as
+/// a sequence of multiply, add and shifts.  Requires that the divisor not be 0.
+static struct mu magicu(uint64_t d)
+{
+  int64_t p;
+  uint64_t nc, delta, q1, r1, q2, r2;
+  struct mu magu;
+  magu.a = 0;               // initialize "add" indicator
+  nc = - 1 - (-d)%d;
+  p = 63;                   // initialize p
+  q1 = 0x8000000000000000ull/nc;       // initialize q1 = 2p/nc
+  r1 = 0x8000000000000000ull - q1*nc;  // initialize r1 = rem(2p,nc)
+  q2 = 0x7FFFFFFFFFFFFFFFull/d;        // initialize q2 = (2p-1)/d
+  r2 = 0x7FFFFFFFFFFFFFFFull - q2*d;   // initialize r2 = rem((2p-1),d)
+  do {
+    p = p + 1;
+    if (r1 >= nc - r1 ) {
+      q1 = 2*q1 + 1;  // update q1
+      r1 = 2*r1 - nc; // update r1
+    }
+    else {
+      q1 = 2*q1; // update q1
+      r1 = 2*r1; // update r1
+    }
+    if (r2 + 1 >= d - r2) {
+      if (q2 >= 0x7FFFFFFFFFFFFFFFull) magu.a = 1;
+      q2 = 2*q2 + 1;     // update q2
+      r2 = 2*r2 + 1 - d; // update r2
+    }
+    else {
+      if (q2 >= 0x8000000000000000ull) magu.a = 1;
+      q2 = 2*q2;     // update q2
+      r2 = 2*r2 + 1; // update r2
+    }
+    delta = d - 1 - r2;
+  } while (p < 64 && (q1 < delta || (q1 == delta && r1 == 0)));
+  magu.m = q2 + 1; // resulting magic number
+  magu.s = p - 64;  // resulting shift
+  return magu;
+}
+
+/// BuildSDIVSequence - Given an ISD::SDIV node expressing a divide by constant,
+/// return a DAG expression to select that will generate the same value by
+/// multiplying by a magic number.  See:
+/// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html>
+static SDOperand BuildSDIVSequence(SDOperand N, SelectionDAG* ISelDAG) {
+  int64_t d = (int64_t)cast<ConstantSDNode>(N.getOperand(1))->getSignExtended();
+  ms magics = magic(d);
+  // Multiply the numerator (operand 0) by the magic value
+  SDOperand Q = ISelDAG->getNode(ISD::MULHS, MVT::i64, N.getOperand(0),
+                                 ISelDAG->getConstant(magics.m, MVT::i64));
+  // If d > 0 and m < 0, add the numerator
+  if (d > 0 && magics.m < 0)
+    Q = ISelDAG->getNode(ISD::ADD, MVT::i64, Q, N.getOperand(0));
+  // If d < 0 and m > 0, subtract the numerator.
+  if (d < 0 && magics.m > 0)
+    Q = ISelDAG->getNode(ISD::SUB, MVT::i64, Q, N.getOperand(0));
+  // Shift right algebraic if shift value is nonzero
+  if (magics.s > 0)
+    Q = ISelDAG->getNode(ISD::SRA, MVT::i64, Q,
+                         ISelDAG->getConstant(magics.s, MVT::i64));
+  // Extract the sign bit and add it to the quotient
+  SDOperand T =
+    ISelDAG->getNode(ISD::SRL, MVT::i64, Q, ISelDAG->getConstant(63, MVT::i64));
+  return ISelDAG->getNode(ISD::ADD, MVT::i64, Q, T);
+}
+
+/// BuildUDIVSequence - Given an ISD::UDIV node expressing a divide by constant,
+/// return a DAG expression to select that will generate the same value by
+/// multiplying by a magic number.  See:
+/// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html>
+static SDOperand BuildUDIVSequence(SDOperand N, SelectionDAG* ISelDAG) {
+  unsigned d =
+    (unsigned)cast<ConstantSDNode>(N.getOperand(1))->getSignExtended();
+  mu magics = magicu(d);
+  // Multiply the numerator (operand 0) by the magic value
+  SDOperand Q = ISelDAG->getNode(ISD::MULHU, MVT::i64, N.getOperand(0),
+                                 ISelDAG->getConstant(magics.m, MVT::i64));
+  if (magics.a == 0) {
+    Q = ISelDAG->getNode(ISD::SRL, MVT::i64, Q,
+                         ISelDAG->getConstant(magics.s, MVT::i64));
+  } else {
+    SDOperand NPQ = ISelDAG->getNode(ISD::SUB, MVT::i64, N.getOperand(0), Q);
+    NPQ = ISelDAG->getNode(ISD::SRL, MVT::i64, NPQ,
+                           ISelDAG->getConstant(1, MVT::i64));
+    NPQ = ISelDAG->getNode(ISD::ADD, MVT::i64, NPQ, Q);
+    Q = ISelDAG->getNode(ISD::SRL, MVT::i64, NPQ,
+                           ISelDAG->getConstant(magics.s-1, MVT::i64));
+  }
+  return Q;
+}
 
 /// AddLiveIn - This helper function adds the specified physical register to the
 /// MachineFunction as a live in value.  It also creates a corresponding virtual
@@ -283,7 +428,7 @@
     break;
   }
 
-  //return the arguments
+  //return the arguments+
   return ArgValues;
 }
 





From alenhar2 at cs.uiuc.edu  Sun Apr  2 16:08:51 2006
From: alenhar2 at cs.uiuc.edu (Andrew Lenharth)
Date: Sun, 2 Apr 2006 16:08:51 -0500
Subject: [llvm-commits] CVS: llvm/lib/Target/Alpha/AlphaISelLowering.cpp 
Message-ID: <200604022108.QAA06290@zion.cs.uiuc.edu>



Changes in directory llvm/lib/Target/Alpha:

AlphaISelLowering.cpp updated: 1.42 -> 1.43
---
Log message:

This makes McCat/12-IOtest go 8x faster or so

---
Diffs of the changes:  (+14 -2)

 AlphaISelLowering.cpp |   16 ++++++++++++++--
 1 files changed, 14 insertions(+), 2 deletions(-)


Index: llvm/lib/Target/Alpha/AlphaISelLowering.cpp
diff -u llvm/lib/Target/Alpha/AlphaISelLowering.cpp:1.42 llvm/lib/Target/Alpha/AlphaISelLowering.cpp:1.43
--- llvm/lib/Target/Alpha/AlphaISelLowering.cpp:1.42	Sun Apr  2 15:13:57 2006
+++ llvm/lib/Target/Alpha/AlphaISelLowering.cpp	Sun Apr  2 16:08:39 2006
@@ -585,10 +585,22 @@
 		       DAG.getNode(AlphaISD::GlobalBaseReg, MVT::i64));
   }
 
-  case ISD::SDIV:
-  case ISD::UDIV:
   case ISD::UREM:
   case ISD::SREM:
+    //Expand only on constant case
+    if (Op.getOperand(1).getOpcode() == ISD::Constant) {
+      MVT::ValueType VT = Op.Val->getValueType(0);
+      unsigned Opc = Op.Val->getOpcode() == ISD::UREM ? ISD::UDIV : ISD::SDIV;
+      SDOperand Tmp1 = Op.Val->getOpcode() == ISD::UREM ?
+	BuildUDIVSequence(Op, &DAG) :
+	BuildSDIVSequence(Op, &DAG);
+      Tmp1 = DAG.getNode(ISD::MUL, VT, Tmp1, Op.getOperand(1));
+      Tmp1 = DAG.getNode(ISD::SUB, VT, Op.getOperand(0), Tmp1);
+      return Tmp1;
+    }
+    //fall through
+  case ISD::SDIV:
+  case ISD::UDIV:
     if (MVT::isInteger(Op.getValueType())) {
       const char* opstr = 0;
       switch(Op.getOpcode()) {





From alenhar2 at cs.uiuc.edu  Sun Apr  2 16:43:08 2006
From: alenhar2 at cs.uiuc.edu (Andrew Lenharth)
Date: Sun, 2 Apr 2006 16:43:08 -0500
Subject: [llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp 
Message-ID: <200604022143.QAA13324@apoc.cs.uiuc.edu>



Changes in directory llvm/lib/CodeGen/SelectionDAG:

DAGCombiner.cpp updated: 1.139 -> 1.140
---
Log message:

This should be a win of every arch

---
Diffs of the changes:  (+26 -1)

 DAGCombiner.cpp |   27 ++++++++++++++++++++++++++-
 1 files changed, 26 insertions(+), 1 deletion(-)


Index: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.139 llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.140
--- llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.139	Sun Apr  2 00:11:11 2006
+++ llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp	Sun Apr  2 16:42:45 2006
@@ -818,7 +818,32 @@
                             DAG.getConstant(Log2_64(-N1C->getSignExtended()),
                                             TLI.getShiftAmountTy())));
   }
-  
+
+  //These two might be better as:
+  // mul x, ((1 << c) + cn) -> (x << c) + (x * cn)
+  // where TargetInfo tells us cn is a cheap constant to multiply by
+
+  // fold (mul x, (1 << c) + 1) -> (x << c) + x
+  //FIXME: there should be a target hint to allow other constants based on 
+  //       expense of mul
+  if (N1C && isPowerOf2_64(N1C->getSignExtended() - 1)) {
+    return DAG.getNode(ISD::ADD, VT, 
+		       DAG.getNode(ISD::SHL, VT, N0,
+			   DAG.getConstant(Log2_64(N1C->getSignExtended() - 1),
+						   TLI.getShiftAmountTy())),
+		       N0);
+  }
+  // fold (mul x, (1 << c) - 1) -> (x << c) - x
+  //FIXME: there should be a target hint to allow other constants based on 
+  //       the expense of mul
+  if (N1C && isPowerOf2_64(N1C->getSignExtended() + 1)) {
+    return DAG.getNode(ISD::SUB, VT, 
+		       DAG.getNode(ISD::SHL, VT, N0,
+			   DAG.getConstant(Log2_64(N1C->getSignExtended() + 1),
+					   TLI.getShiftAmountTy())),
+		       N0);
+  }
+
   // (mul (shl X, c1), c2) -> (mul X, c2 << c1)
   if (N1C && N0.getOpcode() == ISD::SHL && 
       isa<ConstantSDNode>(N0.getOperand(1))) {





From alenhar2 at cs.uiuc.edu  Sun Apr  2 16:47:24 2006
From: alenhar2 at cs.uiuc.edu (Andrew Lenharth)
Date: Sun, 2 Apr 2006 16:47:24 -0500
Subject: [llvm-commits] CVS: llvm/test/Regression/CodeGen/Alpha/mul5.ll 
Message-ID: <200604022147.QAA13355@apoc.cs.uiuc.edu>



Changes in directory llvm/test/Regression/CodeGen/Alpha:

mul5.ll added (r1.1)
---
Log message:

Make sure mul by constant 5 is turned into a s4addq

---
Diffs of the changes:  (+16 -0)

 mul5.ll |   16 ++++++++++++++++
 1 files changed, 16 insertions(+)


Index: llvm/test/Regression/CodeGen/Alpha/mul5.ll
diff -c /dev/null llvm/test/Regression/CodeGen/Alpha/mul5.ll:1.1
*** /dev/null	Sun Apr  2 16:47:17 2006
--- llvm/test/Regression/CodeGen/Alpha/mul5.ll	Sun Apr  2 16:47:07 2006
***************
*** 0 ****
--- 1,16 ----
+ ; Make sure this testcase does not use mulq
+ ; RUN: llvm-as < %s | llc -march=alpha | grep -i 'mul' |wc -l |grep 0
+ 
+ implementation   ; Functions:
+ 
+ ulong %foo(ulong %x) {
+ entry:
+ 	%tmp.1 = mul ulong %x, 5		; <ulong> [#uses=1]
+ 	ret ulong %tmp.1
+ }
+ 
+ long %bar(long %x) {
+ entry:
+ 	%tmp.1 = mul long %x, 5		; <long> [#uses=1]
+ 	ret long %tmp.1
+ }





From alenhar2 at cs.uiuc.edu  Sun Apr  2 22:16:22 2006
From: alenhar2 at cs.uiuc.edu (Andrew Lenharth)
Date: Sun, 2 Apr 2006 22:16:22 -0500
Subject: [llvm-commits] CVS: llvm/test/Regression/CodeGen/Alpha/mul5.ll 
Message-ID: <200604030316.WAA07782@zion.cs.uiuc.edu>



Changes in directory llvm/test/Regression/CodeGen/Alpha:

mul5.ll updated: 1.1 -> 1.2
---
Log message:

test some more mul by constant removal

---
Diffs of the changes:  (+13 -2)

 mul5.ll |   15 +++++++++++++--
 1 files changed, 13 insertions(+), 2 deletions(-)


Index: llvm/test/Regression/CodeGen/Alpha/mul5.ll
diff -u llvm/test/Regression/CodeGen/Alpha/mul5.ll:1.1 llvm/test/Regression/CodeGen/Alpha/mul5.ll:1.2
--- llvm/test/Regression/CodeGen/Alpha/mul5.ll:1.1	Sun Apr  2 16:47:07 2006
+++ llvm/test/Regression/CodeGen/Alpha/mul5.ll	Sun Apr  2 22:16:09 2006
@@ -3,9 +3,20 @@
 
 implementation   ; Functions:
 
-ulong %foo(ulong %x) {
+ulong %foo1(ulong %x) {
 entry:
-	%tmp.1 = mul ulong %x, 5		; <ulong> [#uses=1]
+	%tmp.1 = mul ulong %x, 9		; <ulong> [#uses=1]
+	ret ulong %tmp.1
+}
+ulong %foo3(ulong %x) {
+entry:
+        %tmp.1 = mul ulong %x, 259
+	ret ulong %tmp.1
+}
+
+ulong %foo1n(ulong %x) {
+entry:
+        %tmp.1 = mul ulong %x, 511
 	ret ulong %tmp.1
 }
 





From alenhar2 at cs.uiuc.edu  Sun Apr  2 22:17:03 2006
From: alenhar2 at cs.uiuc.edu (Andrew Lenharth)
Date: Sun, 2 Apr 2006 22:17:03 -0500
Subject: [llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp 
Message-ID: <200604030317.WAA07809@zion.cs.uiuc.edu>



Changes in directory llvm/lib/CodeGen/SelectionDAG:

DAGCombiner.cpp updated: 1.140 -> 1.141
---
Log message:

back this out

---
Diffs of the changes:  (+0 -25)

 DAGCombiner.cpp |   25 -------------------------
 1 files changed, 25 deletions(-)


Index: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.140 llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.141
--- llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.140	Sun Apr  2 16:42:45 2006
+++ llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp	Sun Apr  2 22:16:50 2006
@@ -819,31 +819,6 @@
                                             TLI.getShiftAmountTy())));
   }
 
-  //These two might be better as:
-  // mul x, ((1 << c) + cn) -> (x << c) + (x * cn)
-  // where TargetInfo tells us cn is a cheap constant to multiply by
-
-  // fold (mul x, (1 << c) + 1) -> (x << c) + x
-  //FIXME: there should be a target hint to allow other constants based on 
-  //       expense of mul
-  if (N1C && isPowerOf2_64(N1C->getSignExtended() - 1)) {
-    return DAG.getNode(ISD::ADD, VT, 
-		       DAG.getNode(ISD::SHL, VT, N0,
-			   DAG.getConstant(Log2_64(N1C->getSignExtended() - 1),
-						   TLI.getShiftAmountTy())),
-		       N0);
-  }
-  // fold (mul x, (1 << c) - 1) -> (x << c) - x
-  //FIXME: there should be a target hint to allow other constants based on 
-  //       the expense of mul
-  if (N1C && isPowerOf2_64(N1C->getSignExtended() + 1)) {
-    return DAG.getNode(ISD::SUB, VT, 
-		       DAG.getNode(ISD::SHL, VT, N0,
-			   DAG.getConstant(Log2_64(N1C->getSignExtended() + 1),
-					   TLI.getShiftAmountTy())),
-		       N0);
-  }
-
   // (mul (shl X, c1), c2) -> (mul X, c2 << c1)
   if (N1C && N0.getOpcode() == ISD::SHL && 
       isa<ConstantSDNode>(N0.getOperand(1))) {





From alenhar2 at cs.uiuc.edu  Sun Apr  2 22:19:10 2006
From: alenhar2 at cs.uiuc.edu (Andrew Lenharth)
Date: Sun, 2 Apr 2006 22:19:10 -0500
Subject: [llvm-commits] CVS: llvm/lib/Target/Alpha/AlphaISelDAGToDAG.cpp
	AlphaISelLowering.cpp AlphaInstrInfo.td 
Message-ID: <200604030319.WAA07846@zion.cs.uiuc.edu>



Changes in directory llvm/lib/Target/Alpha:

AlphaISelDAGToDAG.cpp updated: 1.36 -> 1.37
AlphaISelLowering.cpp updated: 1.43 -> 1.44
AlphaInstrInfo.td updated: 1.117 -> 1.118
---
Log message:

mul by const conversion sequences.  more coming soon

---
Diffs of the changes:  (+61 -2)

 AlphaISelDAGToDAG.cpp |   12 ++++++++++++
 AlphaISelLowering.cpp |    2 +-
 AlphaInstrInfo.td     |   49 ++++++++++++++++++++++++++++++++++++++++++++++++-
 3 files changed, 61 insertions(+), 2 deletions(-)


Index: llvm/lib/Target/Alpha/AlphaISelDAGToDAG.cpp
diff -u llvm/lib/Target/Alpha/AlphaISelDAGToDAG.cpp:1.36 llvm/lib/Target/Alpha/AlphaISelDAGToDAG.cpp:1.37
--- llvm/lib/Target/Alpha/AlphaISelDAGToDAG.cpp:1.36	Sat Mar 25 00:47:10 2006
+++ llvm/lib/Target/Alpha/AlphaISelDAGToDAG.cpp	Sun Apr  2 22:18:59 2006
@@ -71,6 +71,18 @@
       return build;
     }
 
+    static uint64_t getNearPower2(uint64_t x) {
+      if (!x) return 0;
+      unsigned at = CountLeadingZeros_64(x);
+      uint64_t complow = 1 << (63 - at);
+      uint64_t comphigh = 1 << (64 - at);
+      //std::cerr << x << ":" << complow << ":" << comphigh << "\n";
+      if (abs(complow - x) < abs(comphigh - x))
+        return complow;
+      else
+        return comphigh;
+    }
+
     static bool isFPZ(SDOperand N) {
       ConstantFPSDNode *CN = dyn_cast<ConstantFPSDNode>(N);
       return (CN && (CN->isExactlyValue(+0.0) || CN->isExactlyValue(-0.0)));


Index: llvm/lib/Target/Alpha/AlphaISelLowering.cpp
diff -u llvm/lib/Target/Alpha/AlphaISelLowering.cpp:1.43 llvm/lib/Target/Alpha/AlphaISelLowering.cpp:1.44
--- llvm/lib/Target/Alpha/AlphaISelLowering.cpp:1.43	Sun Apr  2 16:08:39 2006
+++ llvm/lib/Target/Alpha/AlphaISelLowering.cpp	Sun Apr  2 22:18:59 2006
@@ -229,7 +229,7 @@
   setOperationAction(ISD::UREM     , MVT::i64, Custom);
   setOperationAction(ISD::SDIV     , MVT::i64, Custom);
   setOperationAction(ISD::UDIV     , MVT::i64, Custom);
-  
+
   setOperationAction(ISD::MEMMOVE  , MVT::Other, Expand);
   setOperationAction(ISD::MEMSET   , MVT::Other, Expand);
   setOperationAction(ISD::MEMCPY   , MVT::Other, Expand);


Index: llvm/lib/Target/Alpha/AlphaInstrInfo.td
diff -u llvm/lib/Target/Alpha/AlphaInstrInfo.td:1.117 llvm/lib/Target/Alpha/AlphaInstrInfo.td:1.118
--- llvm/lib/Target/Alpha/AlphaInstrInfo.td:1.117	Thu Mar  9 11:56:33 2006
+++ llvm/lib/Target/Alpha/AlphaInstrInfo.td	Sun Apr  2 22:18:59 2006
@@ -57,6 +57,9 @@
 def iZAPX : SDNodeXForm<imm, [{ // get imm to ZAPi
   return getI64Imm(get_zapImm((uint64_t)N->getValue()));
 }]>;
+def nearP2X : SDNodeXForm<imm, [{
+  return getI64Imm(Log2_64(getNearPower2((uint64_t)N->getValue())));
+}]>;
 
 def immUExt8  : PatLeaf<(imm), [{ //imm fits in 8 bit zero extended field
   return (uint64_t)N->getValue() == (uint8_t)N->getValue();
@@ -80,6 +83,31 @@
 def immFPZ  : PatLeaf<(fpimm), [{ //the only fpconstant nodes are +/- 0.0
   return true;
 }]>;
+def immRem1 : PatLeaf<(imm), [{
+  return (int64_t)getNearPower2((uint64_t)N->getValue()) - (int64_t)N->getValue() == -1;
+}]>;
+def immRem3 : PatLeaf<(imm), [{
+  return (int64_t)getNearPower2((uint64_t)N->getValue()) - (int64_t)N->getValue() == -3;
+}]>;
+def immRem5 : PatLeaf<(imm), [{
+  return (int64_t)getNearPower2((uint64_t)N->getValue()) - (int64_t)N->getValue() == -5;
+}]>;
+def immRem1n : PatLeaf<(imm), [{
+  return (int64_t)getNearPower2((uint64_t)N->getValue()) - N->getValue() == 1;
+}]>;
+def immRem3n : PatLeaf<(imm), [{
+  return (int64_t)getNearPower2((uint64_t)N->getValue()) - N->getValue() == 3;
+}]>;
+def immRem5n : PatLeaf<(imm), [{
+  return (int64_t)getNearPower2((uint64_t)N->getValue()) - N->getValue() == 5;
+}]>;
+def immUExt8ME : PatLeaf<(imm), [{ //use this imm for mulqi
+  int64_t d = (int64_t)getNearPower2((uint64_t)N->getValue()) - N->getValue();
+  switch (abs(d)) {
+    case 1: case 3: case 5: return false; 
+    default: return (uint64_t)N->getValue() == (uint8_t)N->getValue();
+  };
+}]>;
 
 def intop : PatFrag<(ops node:$op), (sext_inreg node:$op, i32)>;
 def add4  : PatFrag<(ops node:$op1, node:$op2),
@@ -252,7 +280,7 @@
 def MULQ     : OForm< 0x13, 0x20, "mulq $RA,$RB,$RC",
                       [(set GPRC:$RC, (mul GPRC:$RA, GPRC:$RB))], s_imul>;
 def MULQi    : OFormL<0x13, 0x20, "mulq $RA,$L,$RC",
-                      [(set GPRC:$RC, (mul GPRC:$RA, immUExt8:$L))], s_imul>;
+                      [(set GPRC:$RC, (mul GPRC:$RA, immUExt8ME:$L))], s_imul>;
 def ORNOT    : OForm< 0x11, 0x28, "ornot $RA,$RB,$RC",
                       [(set GPRC:$RC, (or GPRC:$RA, (not GPRC:$RB)))], s_ilog>;
 def ORNOTi   : OFormL<0x11, 0x28, "ornot $RA,$L,$RC", 
@@ -876,3 +904,22 @@
 def : Pat<(mulhs GPRC:$RA, GPRC:$RB),
           (SUBQ (UMULH GPRC:$RA, GPRC:$RB), (ADDQ (CMOVGE GPRC:$RB, R31, GPRC:$RA), 
                                                  (CMOVGE GPRC:$RA, R31, GPRC:$RB)))>;
+
+//Stupid crazy arithmetic stuff:
+def : Pat<(mul GPRC:$RA, 5), (S4ADDQ GPRC:$RA, GPRC:$RA)>;
+def : Pat<(mul GPRC:$RA, 3), (S4SUBQ GPRC:$RA, GPRC:$RA)>;
+
+def : Pat<(mul GPRC:$RA, immRem1:$imm), 
+          (ADDQ (SL GPRC:$RA, (nearP2X immRem1:$imm)), GPRC:$RA)>;
+def : Pat<(mul GPRC:$RA, immRem3:$imm),
+          (ADDQ (SL GPRC:$RA, (nearP2X immRem3:$imm)), (S4SUBQ GPRC:$RA, GPRC:$RA))>;
+def : Pat<(mul GPRC:$RA, immRem5:$imm),
+          (ADDQ (SL GPRC:$RA, (nearP2X immRem5:$imm)), (S4ADDQ GPRC:$RA, GPRC:$RA))>;
+
+def : Pat<(mul GPRC:$RA, immRem1n:$imm), 
+          (SUBQ (SL GPRC:$RA, (nearP2X immRem1n:$imm)), GPRC:$RA)>;
+def : Pat<(mul GPRC:$RA, immRem3n:$imm),
+          (SUBQ (SL GPRC:$RA, (nearP2X immRem3n:$imm)), (S4SUBQ GPRC:$RA, GPRC:$RA))>;
+def : Pat<(mul GPRC:$RA, immRem5n:$imm),
+          (SUBQ (SL GPRC:$RA, (nearP2X immRem5n:$imm)), (S4ADDQ GPRC:$RA, GPRC:$RA))>;
+





From alenhar2 at cs.uiuc.edu  Sun Apr  2 23:14:52 2006
From: alenhar2 at cs.uiuc.edu (Andrew Lenharth)
Date: Sun, 2 Apr 2006 23:14:52 -0500
Subject: [llvm-commits] CVS: llvm/test/Regression/CodeGen/Alpha/mul5.ll 
Message-ID: <200604030414.XAA08029@zion.cs.uiuc.edu>



Changes in directory llvm/test/Regression/CodeGen/Alpha:

mul5.ll updated: 1.2 -> 1.3
---
Log message:

test powers of 2

---
Diffs of the changes:  (+18 -0)

 mul5.ll |   18 ++++++++++++++++++
 1 files changed, 18 insertions(+)


Index: llvm/test/Regression/CodeGen/Alpha/mul5.ll
diff -u llvm/test/Regression/CodeGen/Alpha/mul5.ll:1.2 llvm/test/Regression/CodeGen/Alpha/mul5.ll:1.3
--- llvm/test/Regression/CodeGen/Alpha/mul5.ll:1.2	Sun Apr  2 22:16:09 2006
+++ llvm/test/Regression/CodeGen/Alpha/mul5.ll	Sun Apr  2 23:14:39 2006
@@ -14,12 +14,30 @@
 	ret ulong %tmp.1
 }
 
+ulong %foo4l(ulong %x) {
+entry:
+        %tmp.1 = mul ulong %x, 260
+	ret ulong %tmp.1
+}
+
+ulong %foo4ln(ulong %x) {
+entry:
+        %tmp.1 = mul ulong %x, 252
+	ret ulong %tmp.1
+}
+
 ulong %foo1n(ulong %x) {
 entry:
         %tmp.1 = mul ulong %x, 511
 	ret ulong %tmp.1
 }
 
+ulong %foo8l(ulong %x) {
+entry:
+        %tmp.1 = mul ulong %x, 768
+        ret ulong %tmp.1
+}
+
 long %bar(long %x) {
 entry:
 	%tmp.1 = mul long %x, 5		; <long> [#uses=1]





From alenhar2 at cs.uiuc.edu  Sun Apr  2 23:19:30 2006
From: alenhar2 at cs.uiuc.edu (Andrew Lenharth)
Date: Sun, 2 Apr 2006 23:19:30 -0500
Subject: [llvm-commits] CVS: llvm/lib/Target/Alpha/AlphaISelDAGToDAG.cpp
	AlphaInstrInfo.td 
Message-ID: <200604030419.XAA08079@zion.cs.uiuc.edu>



Changes in directory llvm/lib/Target/Alpha:

AlphaISelDAGToDAG.cpp updated: 1.37 -> 1.38
AlphaInstrInfo.td updated: 1.118 -> 1.119
---
Log message:

support x * (c1 + c2) where c1 and c2 are pow2s.  special case for c2 == 4

---
Diffs of the changes:  (+32 -10)

 AlphaISelDAGToDAG.cpp |    2 +-
 AlphaInstrInfo.td     |   40 +++++++++++++++++++++++++++++++---------
 2 files changed, 32 insertions(+), 10 deletions(-)


Index: llvm/lib/Target/Alpha/AlphaISelDAGToDAG.cpp
diff -u llvm/lib/Target/Alpha/AlphaISelDAGToDAG.cpp:1.37 llvm/lib/Target/Alpha/AlphaISelDAGToDAG.cpp:1.38
--- llvm/lib/Target/Alpha/AlphaISelDAGToDAG.cpp:1.37	Sun Apr  2 22:18:59 2006
+++ llvm/lib/Target/Alpha/AlphaISelDAGToDAG.cpp	Sun Apr  2 23:19:17 2006
@@ -77,7 +77,7 @@
       uint64_t complow = 1 << (63 - at);
       uint64_t comphigh = 1 << (64 - at);
       //std::cerr << x << ":" << complow << ":" << comphigh << "\n";
-      if (abs(complow - x) < abs(comphigh - x))
+      if (abs(complow - x) <= abs(comphigh - x))
         return complow;
       else
         return comphigh;


Index: llvm/lib/Target/Alpha/AlphaInstrInfo.td
diff -u llvm/lib/Target/Alpha/AlphaInstrInfo.td:1.118 llvm/lib/Target/Alpha/AlphaInstrInfo.td:1.119
--- llvm/lib/Target/Alpha/AlphaInstrInfo.td:1.118	Sun Apr  2 22:18:59 2006
+++ llvm/lib/Target/Alpha/AlphaInstrInfo.td	Sun Apr  2 23:19:17 2006
@@ -60,6 +60,10 @@
 def nearP2X : SDNodeXForm<imm, [{
   return getI64Imm(Log2_64(getNearPower2((uint64_t)N->getValue())));
 }]>;
+def nearP2RemX : SDNodeXForm<imm, [{
+  uint64_t x = abs(N->getValue() - getNearPower2((uint64_t)N->getValue()));
+  return getI64Imm(Log2_64(x));
+}]>;
 
 def immUExt8  : PatLeaf<(imm), [{ //imm fits in 8 bit zero extended field
   return (uint64_t)N->getValue() == (uint8_t)N->getValue();
@@ -84,26 +88,39 @@
   return true;
 }]>;
 def immRem1 : PatLeaf<(imm), [{
-  return (int64_t)getNearPower2((uint64_t)N->getValue()) - (int64_t)N->getValue() == -1;
+  return N->getValue() - getNearPower2((uint64_t)N->getValue()) == 1;
 }]>;
 def immRem3 : PatLeaf<(imm), [{
-  return (int64_t)getNearPower2((uint64_t)N->getValue()) - (int64_t)N->getValue() == -3;
+  return N->getValue() - getNearPower2((uint64_t)N->getValue()) == 3;
+}]>;
+def immRem4 : PatLeaf<(imm), [{
+  return N->getValue() - getNearPower2((uint64_t)N->getValue()) == 4;
 }]>;
 def immRem5 : PatLeaf<(imm), [{
-  return (int64_t)getNearPower2((uint64_t)N->getValue()) - (int64_t)N->getValue() == -5;
+  return N->getValue() - getNearPower2((uint64_t)N->getValue()) == 5;
 }]>;
 def immRem1n : PatLeaf<(imm), [{
-  return (int64_t)getNearPower2((uint64_t)N->getValue()) - N->getValue() == 1;
+  return getNearPower2((uint64_t)N->getValue()) - N->getValue() == 1;
 }]>;
 def immRem3n : PatLeaf<(imm), [{
-  return (int64_t)getNearPower2((uint64_t)N->getValue()) - N->getValue() == 3;
+  return getNearPower2((uint64_t)N->getValue()) - N->getValue() == 3;
+}]>;
+def immRem4n : PatLeaf<(imm), [{
+  return getNearPower2((uint64_t)N->getValue()) - N->getValue() == 4;
 }]>;
 def immRem5n : PatLeaf<(imm), [{
-  return (int64_t)getNearPower2((uint64_t)N->getValue()) - N->getValue() == 5;
+  return getNearPower2((uint64_t)N->getValue()) - N->getValue() == 5;
+}]>;
+def immRemP2n : PatLeaf<(imm), [{
+  return isPowerOf2_64(getNearPower2((uint64_t)N->getValue()) - N->getValue());
+}]>;
+def immRemP2 : PatLeaf<(imm), [{
+  return isPowerOf2_64(N->getValue() - getNearPower2((uint64_t)N->getValue()));
 }]>;
 def immUExt8ME : PatLeaf<(imm), [{ //use this imm for mulqi
-  int64_t d = (int64_t)getNearPower2((uint64_t)N->getValue()) - N->getValue();
-  switch (abs(d)) {
+  int64_t d =  abs((int64_t)N->getValue() - (int64_t)getNearPower2((uint64_t)N->getValue()));
+  if (isPowerOf2_64(d)) return false;
+  switch (d) {
     case 1: case 3: case 5: return false; 
     default: return (uint64_t)N->getValue() == (uint8_t)N->getValue();
   };
@@ -915,6 +932,10 @@
           (ADDQ (SL GPRC:$RA, (nearP2X immRem3:$imm)), (S4SUBQ GPRC:$RA, GPRC:$RA))>;
 def : Pat<(mul GPRC:$RA, immRem5:$imm),
           (ADDQ (SL GPRC:$RA, (nearP2X immRem5:$imm)), (S4ADDQ GPRC:$RA, GPRC:$RA))>;
+def : Pat<(mul GPRC:$RA, immRem4:$imm),
+          (S4ADDQ GPRC:$RA, (SL GPRC:$RA, (nearP2X immRem4:$imm)))>;
+def : Pat<(mul GPRC:$RA, immRemP2:$imm),
+          (ADDQ (SL GPRC:$RA, (nearP2X immRemP2:$imm)), (SLi GPRC:$RA, (nearP2RemX immRemP2:$imm)))>;
 
 def : Pat<(mul GPRC:$RA, immRem1n:$imm), 
           (SUBQ (SL GPRC:$RA, (nearP2X immRem1n:$imm)), GPRC:$RA)>;
@@ -922,4 +943,5 @@
           (SUBQ (SL GPRC:$RA, (nearP2X immRem3n:$imm)), (S4SUBQ GPRC:$RA, GPRC:$RA))>;
 def : Pat<(mul GPRC:$RA, immRem5n:$imm),
           (SUBQ (SL GPRC:$RA, (nearP2X immRem5n:$imm)), (S4ADDQ GPRC:$RA, GPRC:$RA))>;
-
+def : Pat<(mul GPRC:$RA, immRemP2n:$imm),
+          (SUBQ (SL GPRC:$RA, (nearP2X immRemP2n:$imm)), (SLi GPRC:$RA, (nearP2RemX immRemP2n:$imm)))>;