From lattner at cs.uiuc.edu Mon Apr 3 10:43:20 2006 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Mon, 3 Apr 2006 10:43:20 -0500 Subject: [llvm-commits] CVS: llvm/include/llvm/IntrinsicsPowerPC.td Message-ID: <200604031543.KAA23606@zion.cs.uiuc.edu> Changes in directory llvm/include/llvm: IntrinsicsPowerPC.td updated: 1.11 -> 1.12 --- Log message: Add some classes to make it easier to define intrinsics. Add min/max intrinsics. --- Diffs of the changes: (+87 -45) IntrinsicsPowerPC.td | 132 +++++++++++++++++++++++++++++++++------------------ 1 files changed, 87 insertions(+), 45 deletions(-) Index: llvm/include/llvm/IntrinsicsPowerPC.td diff -u llvm/include/llvm/IntrinsicsPowerPC.td:1.11 llvm/include/llvm/IntrinsicsPowerPC.td:1.12 --- llvm/include/llvm/IntrinsicsPowerPC.td:1.11 Thu Mar 30 17:32:58 2006 +++ llvm/include/llvm/IntrinsicsPowerPC.td Mon Apr 3 10:43:07 2006 @@ -11,6 +11,54 @@ // //===----------------------------------------------------------------------===// +//===----------------------------------------------------------------------===// +// Definitions for all PowerPC intrinsics. +// + +let TargetPrefix = "ppc" in { // All PPC intrinsics start with "llvm.ppc.". + /// PowerPC_Vec_Intrinsic - Base class for all altivec intrinsics. + class PowerPC_Vec_Intrinsic types, + list properties> + : GCCBuiltin, + Intrinsic; +} + +//===----------------------------------------------------------------------===// +// PowerPC Altivec Intrinsic Class Definitions. +// + +/// PowerPC_Vec_FFF_Intrinsic - A PowerPC intrinsic that takes two v4f32 +/// vectors and returns one. These intrinsics have no side effects. +class PowerPC_Vec_FFF_Intrinsic + : PowerPC_Vec_Intrinsic; + +/// PowerPC_Vec_BBB_Intrinsic - A PowerPC intrinsic that takes two v16f8 +/// vectors and returns one. These intrinsics have no side effects. +class PowerPC_Vec_BBB_Intrinsic + : PowerPC_Vec_Intrinsic; + +/// PowerPC_Vec_HHH_Intrinsic - A PowerPC intrinsic that takes two v8i16 +/// vectors and returns one. These intrinsics have no side effects. +class PowerPC_Vec_HHH_Intrinsic + : PowerPC_Vec_Intrinsic; + +/// PowerPC_Vec_WWW_Intrinsic - A PowerPC intrinsic that takes two v4i32 +/// vectors and returns one. These intrinsics have no side effects. +class PowerPC_Vec_WWW_Intrinsic + : PowerPC_Vec_Intrinsic; + + +//===----------------------------------------------------------------------===// +// PowerPC Altivec Intrinsic Definitions. + let TargetPrefix = "ppc" in { // All intrinsics start with "llvm.ppc.". // Loads. These don't map directly to GCC builtins because they represent the // source address with a single pointer. @@ -130,26 +178,46 @@ def int_ppc_altivec_vcmpgtub_p : GCCBuiltin<"__builtin_altivec_vcmpgtub_p">, Intrinsic<[llvm_int_ty, llvm_int_ty, llvm_v16i8_ty,llvm_v16i8_ty], [InstrNoMem]>; +} - // Saturating adds, subs, and multiply-adds - def int_ppc_altivec_vaddubs : GCCBuiltin<"__builtin_altivec_vaddubs">, - Intrinsic<[llvm_v16i8_ty, llvm_v16i8_ty, llvm_v16i8_ty], - [InstrNoMem]>; - def int_ppc_altivec_vaddsbs : GCCBuiltin<"__builtin_altivec_vaddsbs">, - Intrinsic<[llvm_v16i8_ty, llvm_v16i8_ty, llvm_v16i8_ty], - [InstrNoMem]>; - def int_ppc_altivec_vadduhs : GCCBuiltin<"__builtin_altivec_vadduhs">, - Intrinsic<[llvm_v8i16_ty, llvm_v8i16_ty, llvm_v8i16_ty], - [InstrNoMem]>; - def int_ppc_altivec_vaddshs : GCCBuiltin<"__builtin_altivec_vaddshs">, - Intrinsic<[llvm_v8i16_ty, llvm_v8i16_ty, llvm_v8i16_ty], - [InstrNoMem]>; - def int_ppc_altivec_vadduws : GCCBuiltin<"__builtin_altivec_vadduws">, - Intrinsic<[llvm_v4i32_ty, llvm_v4i32_ty, llvm_v4i32_ty], - [InstrNoMem]>; - def int_ppc_altivec_vaddsws : GCCBuiltin<"__builtin_altivec_vaddsws">, - Intrinsic<[llvm_v4i32_ty, llvm_v4i32_ty, llvm_v4i32_ty], - [InstrNoMem]>; +// Vector maximum. +def int_ppc_altivec_vmaxfp : PowerPC_Vec_FFF_Intrinsic<"vmaxfp">; +def int_ppc_altivec_vmaxsb : PowerPC_Vec_BBB_Intrinsic<"vmaxsb">; +def int_ppc_altivec_vmaxsh : PowerPC_Vec_HHH_Intrinsic<"vmaxsh">; +def int_ppc_altivec_vmaxsw : PowerPC_Vec_WWW_Intrinsic<"vmaxsw">; +def int_ppc_altivec_vmaxub : PowerPC_Vec_BBB_Intrinsic<"vmaxub">; +def int_ppc_altivec_vmaxuh : PowerPC_Vec_HHH_Intrinsic<"vmaxuh">; +def int_ppc_altivec_vmaxuw : PowerPC_Vec_WWW_Intrinsic<"vmaxuw">; + +// Vector minimum. +def int_ppc_altivec_vminfp : PowerPC_Vec_FFF_Intrinsic<"vminfp">; +def int_ppc_altivec_vminsb : PowerPC_Vec_BBB_Intrinsic<"vminsb">; +def int_ppc_altivec_vminsh : PowerPC_Vec_HHH_Intrinsic<"vminsh">; +def int_ppc_altivec_vminsw : PowerPC_Vec_WWW_Intrinsic<"vminsw">; +def int_ppc_altivec_vminub : PowerPC_Vec_BBB_Intrinsic<"vminub">; +def int_ppc_altivec_vminuh : PowerPC_Vec_HHH_Intrinsic<"vminuh">; +def int_ppc_altivec_vminuw : PowerPC_Vec_WWW_Intrinsic<"vminuw">; + +// Saturating adds. +def int_ppc_altivec_vaddubs : PowerPC_Vec_BBB_Intrinsic<"vaddubs">; +def int_ppc_altivec_vaddsbs : PowerPC_Vec_BBB_Intrinsic<"vaddsbs">; +def int_ppc_altivec_vadduhs : PowerPC_Vec_HHH_Intrinsic<"vadduhs">; +def int_ppc_altivec_vaddshs : PowerPC_Vec_HHH_Intrinsic<"vaddshs">; +def int_ppc_altivec_vadduws : PowerPC_Vec_WWW_Intrinsic<"vadduws">; +def int_ppc_altivec_vaddsws : PowerPC_Vec_WWW_Intrinsic<"vaddsws">; +def int_ppc_altivec_vaddcuw : PowerPC_Vec_WWW_Intrinsic<"vaddcuw">; + +// Saturating subs. +def int_ppc_altivec_vsububs : PowerPC_Vec_BBB_Intrinsic<"vsububs">; +def int_ppc_altivec_vsubsbs : PowerPC_Vec_BBB_Intrinsic<"vsubsbs">; +def int_ppc_altivec_vsubuhs : PowerPC_Vec_HHH_Intrinsic<"vsubuhs">; +def int_ppc_altivec_vsubshs : PowerPC_Vec_HHH_Intrinsic<"vsubshs">; +def int_ppc_altivec_vsubuws : PowerPC_Vec_WWW_Intrinsic<"vsubuws">; +def int_ppc_altivec_vsubsws : PowerPC_Vec_WWW_Intrinsic<"vsubsws">; +def int_ppc_altivec_vsubcuw : PowerPC_Vec_WWW_Intrinsic<"vsubcuw">; + +let TargetPrefix = "ppc" in { // All PPC intrinsics start with "llvm.ppc.". + // Saturating multiply-adds. def int_ppc_altivec_vmhaddshs : GCCBuiltin<"__builtin_altivec_vmhaddshs">, Intrinsic<[llvm_v8i16_ty, llvm_v8i16_ty, llvm_v8i16_ty, llvm_v8i16_ty], [InstrNoMem]>; @@ -160,35 +228,9 @@ def int_ppc_altivec_vmaddfp : GCCBuiltin<"__builtin_altivec_vmaddfp">, Intrinsic<[llvm_v4f32_ty, llvm_v4f32_ty, llvm_v4f32_ty, llvm_v4f32_ty], [InstrNoMem]>; - def int_ppc_altivec_vaddcuw : GCCBuiltin<"__builtin_altivec_vaddcuw">, - Intrinsic<[llvm_v4i32_ty, llvm_v4i32_ty, llvm_v4i32_ty], - [InstrNoMem]>; - - def int_ppc_altivec_vsububs : GCCBuiltin<"__builtin_altivec_vsububs">, - Intrinsic<[llvm_v16i8_ty, llvm_v16i8_ty, llvm_v16i8_ty], - [InstrNoMem]>; - def int_ppc_altivec_vsubsbs : GCCBuiltin<"__builtin_altivec_vsubsbs">, - Intrinsic<[llvm_v16i8_ty, llvm_v16i8_ty, llvm_v16i8_ty], - [InstrNoMem]>; - def int_ppc_altivec_vsubuhs : GCCBuiltin<"__builtin_altivec_vsubuhs">, - Intrinsic<[llvm_v8i16_ty, llvm_v8i16_ty, llvm_v8i16_ty], - [InstrNoMem]>; - def int_ppc_altivec_vsubshs : GCCBuiltin<"__builtin_altivec_vsubshs">, - Intrinsic<[llvm_v8i16_ty, llvm_v8i16_ty, llvm_v8i16_ty], - [InstrNoMem]>; - def int_ppc_altivec_vsubuws : GCCBuiltin<"__builtin_altivec_vsubuws">, - Intrinsic<[llvm_v4i32_ty, llvm_v4i32_ty, llvm_v4i32_ty], - [InstrNoMem]>; - def int_ppc_altivec_vsubsws : GCCBuiltin<"__builtin_altivec_vsubsws">, - Intrinsic<[llvm_v4i32_ty, llvm_v4i32_ty, llvm_v4i32_ty], - [InstrNoMem]>; - def int_ppc_altivec_vnmsubfp : GCCBuiltin<"__builtin_altivec_vnmsubfp">, Intrinsic<[llvm_v4f32_ty, llvm_v4f32_ty, llvm_v4f32_ty, llvm_v4f32_ty], [InstrNoMem]>; - def int_ppc_altivec_vsubcuw : GCCBuiltin<"__builtin_altivec_vsubcuw">, - Intrinsic<[llvm_v4i32_ty, llvm_v4i32_ty, llvm_v4i32_ty], - [InstrNoMem]>; // Vector Multiply Sum Instructions. def int_ppc_altivec_vmsummbm : GCCBuiltin<"__builtin_altivec_vmsummbm">, From lattner at cs.uiuc.edu Mon Apr 3 10:58:40 2006 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Mon, 3 Apr 2006 10:58:40 -0500 Subject: [llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCInstrAltivec.td Message-ID: <200604031558.KAA24269@zion.cs.uiuc.edu> Changes in directory llvm/lib/Target/PowerPC: PPCInstrAltivec.td updated: 1.30 -> 1.31 --- Log message: Add the full set of min/max instructions --- Diffs of the changes: (+14 -6) PPCInstrAltivec.td | 20 ++++++++++++++------ 1 files changed, 14 insertions(+), 6 deletions(-) Index: llvm/lib/Target/PowerPC/PPCInstrAltivec.td diff -u llvm/lib/Target/PowerPC/PPCInstrAltivec.td:1.30 llvm/lib/Target/PowerPC/PPCInstrAltivec.td:1.31 --- llvm/lib/Target/PowerPC/PPCInstrAltivec.td:1.30 Sat Apr 1 16:41:47 2006 +++ llvm/lib/Target/PowerPC/PPCInstrAltivec.td Mon Apr 3 10:58:28 2006 @@ -203,12 +203,20 @@ def VEXPTEFP : VX2_Int<394, "vexptefp", int_ppc_altivec_vexptefp>; def VLOGEFP : VX2_Int<458, "vlogefp", int_ppc_altivec_vlogefp>; -def VMAXFP : VXForm_1<1034, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB), - "vmaxfp $vD, $vA, $vB", VecFP, - []>; -def VMINFP : VXForm_1<1098, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB), - "vminfp $vD, $vA, $vB", VecFP, - []>; +def VMAXFP : VX1_Int<1034, "vmaxfp", int_ppc_altivec_vmaxfp>; +def VMAXSB : VX1_Int< 258, "vmaxsb", int_ppc_altivec_vmaxsb>; +def VMAXSH : VX1_Int< 322, "vmaxsh", int_ppc_altivec_vmaxsh>; +def VMAXSW : VX1_Int< 386, "vmaxsw", int_ppc_altivec_vmaxsw>; +def VMAXUB : VX1_Int< 2, "vmaxub", int_ppc_altivec_vmaxub>; +def VMAXUH : VX1_Int< 66, "vmaxuh", int_ppc_altivec_vmaxuh>; +def VMAXUW : VX1_Int< 130, "vmaxuw", int_ppc_altivec_vmaxuw>; +def VMINFP : VX1_Int<1098, "vminfp", int_ppc_altivec_vminfp>; +def VMINSB : VX1_Int< 770, "vminsb", int_ppc_altivec_vminsb>; +def VMINSH : VX1_Int< 834, "vminsh", int_ppc_altivec_vminsh>; +def VMINSW : VX1_Int< 896, "vminsw", int_ppc_altivec_vminsw>; +def VMINUB : VX1_Int< 514, "vminub", int_ppc_altivec_vminub>; +def VMINUH : VX1_Int< 578, "vminuh", int_ppc_altivec_vminuh>; +def VMINUW : VX1_Int< 642, "vminuw", int_ppc_altivec_vminuw>; def VMRGHH : VX1_Int<76 , "vmrghh", int_ppc_altivec_vmrghh>; def VMRGHW : VX1_Int<140, "vmrghw", int_ppc_altivec_vmrghw>; From lattner at cs.uiuc.edu Mon Apr 3 12:20:19 2006 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Mon, 3 Apr 2006 12:20:19 -0500 Subject: [llvm-commits] CVS: llvm/include/llvm/IntrinsicsPowerPC.td Message-ID: <200604031720.MAA25156@zion.cs.uiuc.edu> Changes in directory llvm/include/llvm: IntrinsicsPowerPC.td updated: 1.12 -> 1.13 --- Log message: shrinkify intrinsics more by using some local classes --- Diffs of the changes: (+32 -60) IntrinsicsPowerPC.td | 92 +++++++++++++++++---------------------------------- 1 files changed, 32 insertions(+), 60 deletions(-) Index: llvm/include/llvm/IntrinsicsPowerPC.td diff -u llvm/include/llvm/IntrinsicsPowerPC.td:1.12 llvm/include/llvm/IntrinsicsPowerPC.td:1.13 --- llvm/include/llvm/IntrinsicsPowerPC.td:1.12 Mon Apr 3 10:43:07 2006 +++ llvm/include/llvm/IntrinsicsPowerPC.td Mon Apr 3 12:20:06 2006 @@ -27,6 +27,12 @@ // PowerPC Altivec Intrinsic Class Definitions. // +/// PowerPC_Vec_FF_Intrinsic - A PowerPC intrinsic that takes one v4f32 +/// vector and returns one. These intrinsics have no side effects. +class PowerPC_Vec_FF_Intrinsic + : PowerPC_Vec_Intrinsic; + /// PowerPC_Vec_FFF_Intrinsic - A PowerPC intrinsic that takes two v4f32 /// vectors and returns one. These intrinsics have no side effects. class PowerPC_Vec_FFF_Intrinsic @@ -371,58 +377,29 @@ def int_ppc_altivec_vsldoi : GCCBuiltin<"__builtin_altivec_vsldoi_4si">, Intrinsic<[llvm_v4i32_ty, llvm_v4i32_ty, llvm_v4i32_ty, llvm_int_ty], [InstrNoMem]>; - def int_ppc_altivec_vslo : GCCBuiltin<"__builtin_altivec_vslo">, - Intrinsic<[llvm_v4i32_ty, llvm_v4i32_ty, llvm_v4i32_ty], - [InstrNoMem]>; - - def int_ppc_altivec_vslb : GCCBuiltin<"__builtin_altivec_vslb">, - Intrinsic<[llvm_v16i8_ty, llvm_v16i8_ty, llvm_v16i8_ty], - [InstrNoMem]>; - def int_ppc_altivec_vslh : GCCBuiltin<"__builtin_altivec_vslh">, - Intrinsic<[llvm_v8i16_ty, llvm_v8i16_ty, llvm_v8i16_ty], - [InstrNoMem]>; - def int_ppc_altivec_vslw : GCCBuiltin<"__builtin_altivec_vslw">, - Intrinsic<[llvm_v4i32_ty, llvm_v4i32_ty, llvm_v4i32_ty], - [InstrNoMem]>; - - // Right Shifts. - def int_ppc_altivec_vsr : GCCBuiltin<"__builtin_altivec_vsr">, - Intrinsic<[llvm_v4i32_ty, llvm_v4i32_ty, llvm_v4i32_ty], - [InstrNoMem]>; - def int_ppc_altivec_vsro : GCCBuiltin<"__builtin_altivec_vsro">, - Intrinsic<[llvm_v4i32_ty, llvm_v4i32_ty, llvm_v4i32_ty], - [InstrNoMem]>; - - def int_ppc_altivec_vsrb : GCCBuiltin<"__builtin_altivec_vsrb">, - Intrinsic<[llvm_v16i8_ty, llvm_v16i8_ty, llvm_v16i8_ty], - [InstrNoMem]>; - def int_ppc_altivec_vsrh : GCCBuiltin<"__builtin_altivec_vsrh">, - Intrinsic<[llvm_v8i16_ty, llvm_v8i16_ty, llvm_v8i16_ty], - [InstrNoMem]>; - def int_ppc_altivec_vsrw : GCCBuiltin<"__builtin_altivec_vsrw">, - Intrinsic<[llvm_v4i32_ty, llvm_v4i32_ty, llvm_v4i32_ty], - [InstrNoMem]>; - def int_ppc_altivec_vsrab : GCCBuiltin<"__builtin_altivec_vsrab">, - Intrinsic<[llvm_v16i8_ty, llvm_v16i8_ty, llvm_v16i8_ty], - [InstrNoMem]>; - def int_ppc_altivec_vsrah : GCCBuiltin<"__builtin_altivec_vsrah">, - Intrinsic<[llvm_v8i16_ty, llvm_v8i16_ty, llvm_v8i16_ty], - [InstrNoMem]>; - def int_ppc_altivec_vsraw : GCCBuiltin<"__builtin_altivec_vsraw">, - Intrinsic<[llvm_v4i32_ty, llvm_v4i32_ty, llvm_v4i32_ty], - [InstrNoMem]>; - - // Rotates. - def int_ppc_altivec_vrlb : GCCBuiltin<"__builtin_altivec_vrlb">, - Intrinsic<[llvm_v16i8_ty, llvm_v16i8_ty, llvm_v16i8_ty], - [InstrNoMem]>; - def int_ppc_altivec_vrlh : GCCBuiltin<"__builtin_altivec_vrlh">, - Intrinsic<[llvm_v8i16_ty, llvm_v8i16_ty, llvm_v8i16_ty], - [InstrNoMem]>; - def int_ppc_altivec_vrlw : GCCBuiltin<"__builtin_altivec_vrlw">, - Intrinsic<[llvm_v4i32_ty, llvm_v4i32_ty, llvm_v4i32_ty], - [InstrNoMem]>; +} +def int_ppc_altivec_vslo : PowerPC_Vec_WWW_Intrinsic<"vslo">; +def int_ppc_altivec_vslb : PowerPC_Vec_BBB_Intrinsic<"vslb">; +def int_ppc_altivec_vslh : PowerPC_Vec_HHH_Intrinsic<"vslh">; +def int_ppc_altivec_vslw : PowerPC_Vec_WWW_Intrinsic<"vslw">; + +// Right Shifts. +def int_ppc_altivec_vsr : PowerPC_Vec_WWW_Intrinsic<"vsr">; +def int_ppc_altivec_vsro : PowerPC_Vec_WWW_Intrinsic<"vsro">; + +def int_ppc_altivec_vsrb : PowerPC_Vec_BBB_Intrinsic<"vsrb">; +def int_ppc_altivec_vsrh : PowerPC_Vec_HHH_Intrinsic<"vsrh">; +def int_ppc_altivec_vsrw : PowerPC_Vec_WWW_Intrinsic<"vsrw">; +def int_ppc_altivec_vsrab : PowerPC_Vec_BBB_Intrinsic<"vsrab">; +def int_ppc_altivec_vsrah : PowerPC_Vec_HHH_Intrinsic<"vsrah">; +def int_ppc_altivec_vsraw : PowerPC_Vec_WWW_Intrinsic<"vsraw">; + +// Rotates. +def int_ppc_altivec_vrlb : PowerPC_Vec_BBB_Intrinsic<"vrlb">; +def int_ppc_altivec_vrlh : PowerPC_Vec_HHH_Intrinsic<"vrlh">; +def int_ppc_altivec_vrlw : PowerPC_Vec_WWW_Intrinsic<"vrlw">; +let TargetPrefix = "ppc" in { // All PPC intrinsics start with "llvm.ppc.". // Miscellaneous. def int_ppc_altivec_lvsl : Intrinsic<[llvm_v16i8_ty, llvm_ptr_ty], [InstrNoMem]>; @@ -435,14 +412,9 @@ def int_ppc_altivec_vsel : GCCBuiltin<"__builtin_altivec_vsel_4si">, Intrinsic<[llvm_v4i32_ty, llvm_v4i32_ty, llvm_v4i32_ty, llvm_v4i32_ty], [InstrNoMem]>; - - def int_ppc_altivec_vexptefp : GCCBuiltin<"__builtin_altivec_vexptefp">, - Intrinsic<[llvm_v4f32_ty, llvm_v4f32_ty], [InstrNoMem]>; - def int_ppc_altivec_vlogefp : GCCBuiltin<"__builtin_altivec_vlogefp">, - Intrinsic<[llvm_v4f32_ty, llvm_v4f32_ty], [InstrNoMem]>; - def int_ppc_altivec_vrefp : GCCBuiltin<"__builtin_altivec_vrefp">, - Intrinsic<[llvm_v4f32_ty, llvm_v4f32_ty], [InstrNoMem]>; - def int_ppc_altivec_vrsqrtefp : GCCBuiltin<"__builtin_altivec_vrsqrtefp">, - Intrinsic<[llvm_v4f32_ty, llvm_v4f32_ty], [InstrNoMem]>; } +def int_ppc_altivec_vexptefp : PowerPC_Vec_FF_Intrinsic<"vexptefp">; +def int_ppc_altivec_vlogefp : PowerPC_Vec_FF_Intrinsic<"vlogefp">; +def int_ppc_altivec_vrefp : PowerPC_Vec_FF_Intrinsic<"vrefp">; +def int_ppc_altivec_vrsqrtefp : PowerPC_Vec_FF_Intrinsic<"vrsqrtefp">; From lattner at cs.uiuc.edu Mon Apr 3 12:22:02 2006 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Mon, 3 Apr 2006 12:22:02 -0500 Subject: [llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Message-ID: <200604031722.MAA25219@zion.cs.uiuc.edu> Changes in directory llvm/lib/CodeGen/SelectionDAG: DAGCombiner.cpp updated: 1.141 -> 1.142 --- Log message: Add a missing check, which broke a bunch of vector tests. --- Diffs of the changes: (+6 -3) DAGCombiner.cpp | 9 ++++++--- 1 files changed, 6 insertions(+), 3 deletions(-) Index: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp diff -u llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.141 llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.142 --- llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.141 Sun Apr 2 22:16:50 2006 +++ llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Mon Apr 3 12:21:50 2006 @@ -2756,9 +2756,12 @@ Ops.back().getOpcode() == ISD::ConstantFP) && "Scalar binop didn't fold!"); } - Ops.push_back(*(LHS.Val->op_end()-2)); - Ops.push_back(*(LHS.Val->op_end()-1)); - return DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector, Ops); + + if (Ops.size() == LHS.getNumOperands()-2) { + Ops.push_back(*(LHS.Val->op_end()-2)); + Ops.push_back(*(LHS.Val->op_end()-1)); + return DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector, Ops); + } } return SDOperand(); From lattner at cs.uiuc.edu Mon Apr 3 12:29:41 2006 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Mon, 3 Apr 2006 12:29:41 -0500 Subject: [llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Message-ID: <200604031729.MAA25380@zion.cs.uiuc.edu> Changes in directory llvm/lib/CodeGen/SelectionDAG: DAGCombiner.cpp updated: 1.142 -> 1.143 --- Log message: Add a missing check, this fixes UnitTests/Vector/sumarray.c --- Diffs of the changes: (+2 -2) DAGCombiner.cpp | 4 ++-- 1 files changed, 2 insertions(+), 2 deletions(-) Index: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp diff -u llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.142 llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.143 --- llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.142 Mon Apr 3 12:21:50 2006 +++ llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Mon Apr 3 12:29:28 2006 @@ -2017,8 +2017,8 @@ break; } - if (isSimple) { - MVT::ValueType DestEltVT = cast(N->getOperand(2))->getVT(); + MVT::ValueType DestEltVT = cast(N->getOperand(2))->getVT(); + if (isSimple && !MVT::isVector(DestEltVT)) { return ConstantFoldVBIT_CONVERTofVBUILD_VECTOR(N0.Val, DestEltVT); } } From lattner at cs.uiuc.edu Mon Apr 3 14:29:02 2006 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Mon, 3 Apr 2006 14:29:02 -0500 Subject: [llvm-commits] CVS: llvm/lib/Target/TargetData.cpp Message-ID: <200604031929.OAA26597@zion.cs.uiuc.edu> Changes in directory llvm/lib/Target: TargetData.cpp updated: 1.59 -> 1.60 --- Log message: Align vectors to the size in bytes, not bits. --- Diffs of the changes: (+1 -1) TargetData.cpp | 2 +- 1 files changed, 1 insertion(+), 1 deletion(-) Index: llvm/lib/Target/TargetData.cpp diff -u llvm/lib/Target/TargetData.cpp:1.59 llvm/lib/Target/TargetData.cpp:1.60 --- llvm/lib/Target/TargetData.cpp:1.59 Fri Mar 31 16:33:42 2006 +++ llvm/lib/Target/TargetData.cpp Mon Apr 3 14:28:50 2006 @@ -217,7 +217,7 @@ Size = AlignedSize*PTy->getNumElements(); // FIXME: The alignments of specific packed types are target dependent. // For now, just set it to be equal to Size. - Alignment = Size; + Alignment = (Size+7)/8; return; } case Type::StructTyID: { From evan.cheng at apple.com Mon Apr 3 15:53:41 2006 From: evan.cheng at apple.com (Evan Cheng) Date: Mon, 3 Apr 2006 15:53:41 -0500 Subject: [llvm-commits] CVS: llvm/lib/Target/X86/X86ISelLowering.cpp X86InstrInfo.cpp X86InstrInfo.td X86InstrSSE.td Message-ID: <200604032053.PAA27754@zion.cs.uiuc.edu> Changes in directory llvm/lib/Target/X86: X86ISelLowering.cpp updated: 1.151 -> 1.152 X86InstrInfo.cpp updated: 1.47 -> 1.48 X86InstrInfo.td updated: 1.259 -> 1.260 X86InstrSSE.td updated: 1.53 -> 1.54 --- Log message: - More efficient extract_vector_elt with shuffle and movss, movsd, movd, etc. - Some bug fixes and naming inconsistency fixes. --- Diffs of the changes: (+151 -70) X86ISelLowering.cpp | 62 +++++++++++++++++++-- X86InstrInfo.cpp | 6 +- X86InstrInfo.td | 1 X86InstrSSE.td | 152 ++++++++++++++++++++++++++++++---------------------- 4 files changed, 151 insertions(+), 70 deletions(-) Index: llvm/lib/Target/X86/X86ISelLowering.cpp diff -u llvm/lib/Target/X86/X86ISelLowering.cpp:1.151 llvm/lib/Target/X86/X86ISelLowering.cpp:1.152 --- llvm/lib/Target/X86/X86ISelLowering.cpp:1.151 Fri Mar 31 15:55:24 2006 +++ llvm/lib/Target/X86/X86ISelLowering.cpp Mon Apr 3 15:53:28 2006 @@ -280,6 +280,7 @@ setOperationAction(ISD::LOAD, MVT::v4f32, Legal); setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom); setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4f32, Custom); + setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom); } if (Subtarget->hasSSE2()) { @@ -316,7 +317,9 @@ setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v8i16, Custom); setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4i32, Custom); setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i64, Custom); + setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f64, Custom); setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8i16, Custom); + setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4i32, Custom); setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom); } @@ -1484,11 +1487,20 @@ // Dest { 2, 1 } <= shuffle( Dest { 1, 0 }, Src { 3, 2 } // Expect bit 0 == 1, bit1 == 2 SDOperand Bit0 = N->getOperand(0); + if (Bit0.getOpcode() != ISD::UNDEF) { + assert(isa(Bit0) && "Invalid VECTOR_SHUFFLE mask!"); + if (cast(Bit0)->getValue() != 1) + return false; + } + SDOperand Bit1 = N->getOperand(1); - assert(isa(Bit0) && isa(Bit1) && - "Invalid VECTOR_SHUFFLE mask!"); - return (cast(Bit0)->getValue() == 1 && - cast(Bit1)->getValue() == 2); + if (Bit1.getOpcode() != ISD::UNDEF) { + assert(isa(Bit1) && "Invalid VECTOR_SHUFFLE mask!"); + if (cast(Bit1)->getValue() != 2) + return false; + } + + return true; } if (NumElems != 4) return false; @@ -2660,15 +2672,55 @@ return SDOperand(); } case ISD::EXTRACT_VECTOR_ELT: { - // Transform it so it match pextrw which produces a 32-bit result. + if (!isa(Op.getOperand(1))) + return SDOperand(); + MVT::ValueType VT = Op.getValueType(); if (MVT::getSizeInBits(VT) == 16) { + // Transform it so it match pextrw which produces a 32-bit result. MVT::ValueType EVT = (MVT::ValueType)(VT+1); SDOperand Extract = DAG.getNode(X86ISD::PEXTRW, EVT, Op.getOperand(0), Op.getOperand(1)); SDOperand Assert = DAG.getNode(ISD::AssertZext, EVT, Extract, DAG.getValueType(VT)); return DAG.getNode(ISD::TRUNCATE, VT, Assert); + } else if (MVT::getSizeInBits(VT) == 32) { + SDOperand Vec = Op.getOperand(0); + unsigned Idx = cast(Op.getOperand(1))->getValue(); + if (Idx == 0) + return Op; + + // TODO: if Idex == 2, we can use unpckhps + // SHUFPS the element to the lowest double word, then movss. + MVT::ValueType MaskVT = MVT::getIntVectorWithNumElements(4); + SDOperand IdxNode = DAG.getConstant((Idx < 2) ? Idx : Idx+4, + MVT::getVectorBaseType(MaskVT)); + std::vector IdxVec; + IdxVec.push_back(DAG.getConstant(Idx, MVT::getVectorBaseType(MaskVT))); + IdxVec.push_back(DAG.getNode(ISD::UNDEF, MVT::getVectorBaseType(MaskVT))); + IdxVec.push_back(DAG.getNode(ISD::UNDEF, MVT::getVectorBaseType(MaskVT))); + IdxVec.push_back(DAG.getNode(ISD::UNDEF, MVT::getVectorBaseType(MaskVT))); + SDOperand Mask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT, IdxVec); + Vec = DAG.getNode(ISD::VECTOR_SHUFFLE, Vec.getValueType(), + Vec, Vec, Mask); + return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, VT, Vec, + DAG.getConstant(0, MVT::i32)); + } else if (MVT::getSizeInBits(VT) == 64) { + SDOperand Vec = Op.getOperand(0); + unsigned Idx = cast(Op.getOperand(1))->getValue(); + if (Idx == 0) + return Op; + + // UNPCKHPD the element to the lowest double word, then movsd. + MVT::ValueType MaskVT = MVT::getIntVectorWithNumElements(4); + std::vector IdxVec; + IdxVec.push_back(DAG.getConstant(1, MVT::getVectorBaseType(MaskVT))); + IdxVec.push_back(DAG.getNode(ISD::UNDEF, MVT::getVectorBaseType(MaskVT))); + SDOperand Mask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT, IdxVec); + Vec = DAG.getNode(ISD::VECTOR_SHUFFLE, Vec.getValueType(), + Vec, DAG.getNode(ISD::UNDEF, Vec.getValueType()), Mask); + return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, VT, Vec, + DAG.getConstant(0, MVT::i32)); } return SDOperand(); Index: llvm/lib/Target/X86/X86InstrInfo.cpp diff -u llvm/lib/Target/X86/X86InstrInfo.cpp:1.47 llvm/lib/Target/X86/X86InstrInfo.cpp:1.48 --- llvm/lib/Target/X86/X86InstrInfo.cpp:1.47 Fri Mar 24 17:15:12 2006 +++ llvm/lib/Target/X86/X86InstrInfo.cpp Mon Apr 3 15:53:28 2006 @@ -31,8 +31,10 @@ oc == X86::FpMOV || oc == X86::MOVSSrr || oc == X86::MOVSDrr || oc == X86::FsMOVAPSrr || oc == X86::FsMOVAPDrr || oc == X86::MOVAPSrr || oc == X86::MOVAPDrr || - oc == X86::MOVSS128rr || oc == X86::MOVSD128rr || - oc == X86::MOVD128rr || oc == X86::MOVQ128rr) { + oc == X86::MOVSS2PSrr || oc == X86::MOVSD2PDrr || + oc == X86::MOVPS2SSrr || oc == X86::MOVPD2SDrr || + oc == X86::MOVDI2PDIrr || oc == X86::MOVQI2PQIrr || + oc == X86::MOVPDI2DIrr) { assert(MI.getNumOperands() == 2 && MI.getOperand(0).isRegister() && MI.getOperand(1).isRegister() && Index: llvm/lib/Target/X86/X86InstrInfo.td diff -u llvm/lib/Target/X86/X86InstrInfo.td:1.259 llvm/lib/Target/X86/X86InstrInfo.td:1.260 --- llvm/lib/Target/X86/X86InstrInfo.td:1.259 Sat Mar 25 03:45:48 2006 +++ llvm/lib/Target/X86/X86InstrInfo.td Mon Apr 3 15:53:28 2006 @@ -284,6 +284,7 @@ def loadi8 : PatFrag<(ops node:$ptr), (i8 (load node:$ptr))>; def loadi16 : PatFrag<(ops node:$ptr), (i16 (load node:$ptr))>; def loadi32 : PatFrag<(ops node:$ptr), (i32 (load node:$ptr))>; +def loadi64 : PatFrag<(ops node:$ptr), (i64 (load node:$ptr))>; def loadf32 : PatFrag<(ops node:$ptr), (f32 (load node:$ptr))>; def loadf64 : PatFrag<(ops node:$ptr), (f64 (load node:$ptr))>; Index: llvm/lib/Target/X86/X86InstrSSE.td diff -u llvm/lib/Target/X86/X86InstrSSE.td:1.53 llvm/lib/Target/X86/X86InstrSSE.td:1.54 --- llvm/lib/Target/X86/X86InstrSSE.td:1.53 Fri Mar 31 15:55:24 2006 +++ llvm/lib/Target/X86/X86InstrSSE.td Mon Apr 3 15:53:28 2006 @@ -226,24 +226,6 @@ "movsd {$src, $dst|$dst, $src}", [(store FR64:$src, addr:$dst)]>; -// FR32 / FR64 to 128-bit vector conversion. -def MOVSS128rr : SSI<0x10, MRMSrcReg, (ops VR128:$dst, FR32:$src), - "movss {$src, $dst|$dst, $src}", - [(set VR128:$dst, - (v4f32 (scalar_to_vector FR32:$src)))]>; -def MOVSS128rm : SSI<0x10, MRMSrcMem, (ops VR128:$dst, f32mem:$src), - "movss {$src, $dst|$dst, $src}", - [(set VR128:$dst, - (v4f32 (scalar_to_vector (loadf32 addr:$src))))]>; -def MOVSD128rr : SDI<0x10, MRMSrcReg, (ops VR128:$dst, FR64:$src), - "movsd {$src, $dst|$dst, $src}", - [(set VR128:$dst, - (v2f64 (scalar_to_vector FR64:$src)))]>; -def MOVSD128rm : SDI<0x10, MRMSrcMem, (ops VR128:$dst, f64mem:$src), - "movsd {$src, $dst|$dst, $src}", - [(set VR128:$dst, - (v2f64 (scalar_to_vector (loadf64 addr:$src))))]>; - // Arithmetic instructions let isTwoAddress = 1 in { let isCommutable = 1 in { @@ -1122,18 +1104,6 @@ //===----------------------------------------------------------------------===// // Move Instructions -def MOVD128rr : PDI<0x6E, MRMSrcReg, (ops VR128:$dst, R32:$src), - "movd {$src, $dst|$dst, $src}", - [(set VR128:$dst, - (v4i32 (scalar_to_vector R32:$src)))]>; -def MOVD128rm : PDI<0x6E, MRMSrcMem, (ops VR128:$dst, i32mem:$src), - "movd {$src, $dst|$dst, $src}", - [(set VR128:$dst, - (v4i32 (scalar_to_vector (loadi32 addr:$src))))]>; - -def MOVD128mr : PDI<0x7E, MRMDestMem, (ops i32mem:$dst, VR128:$src), - "movd {$src, $dst|$dst, $src}", []>; - def MOVDQArr : PDI<0x6F, MRMSrcReg, (ops VR128:$dst, VR128:$src), "movdqa {$src, $dst|$dst, $src}", []>; def MOVDQArm : PDI<0x6F, MRMSrcMem, (ops VR128:$dst, i128mem:$src), @@ -1143,18 +1113,6 @@ "movdqa {$src, $dst|$dst, $src}", [(store (v4i32 VR128:$src), addr:$dst)]>; -// SSE2 instructions with XS prefix -def MOVQ128rr : I<0x7E, MRMSrcReg, (ops VR128:$dst, VR64:$src), - "movq {$src, $dst|$dst, $src}", - [(set VR128:$dst, - (v2i64 (scalar_to_vector VR64:$src)))]>, XS, - Requires<[HasSSE2]>; -def MOVQ128rm : I<0x7E, MRMSrcMem, (ops VR128:$dst, i64mem:$src), - "movq {$src, $dst|$dst, $src}", []>, XS, - Requires<[HasSSE2]>; -def MOVQ128mr : PDI<0xD6, MRMSrcMem, (ops i64mem:$dst, VR128:$src), - "movq {$src, $dst|$dst, $src}", []>; - // 128-bit Integer Arithmetic let isTwoAddress = 1 in { let isCommutable = 1 in { @@ -1549,32 +1507,102 @@ "pcmpeqd $dst, $dst", [(set VR128:$dst, (v2f64 immAllOnesV))]>; -// Scalar to 128-bit vector with zero extension. +// FR32 / FR64 to 128-bit vector conversion. +def MOVSS2PSrr : SSI<0x10, MRMSrcReg, (ops VR128:$dst, FR32:$src), + "movss {$src, $dst|$dst, $src}", + [(set VR128:$dst, + (v4f32 (scalar_to_vector FR32:$src)))]>; +def MOVSS2PSrm : SSI<0x10, MRMSrcMem, (ops VR128:$dst, f32mem:$src), + "movss {$src, $dst|$dst, $src}", + [(set VR128:$dst, + (v4f32 (scalar_to_vector (loadf32 addr:$src))))]>; +def MOVSD2PDrr : SDI<0x10, MRMSrcReg, (ops VR128:$dst, FR64:$src), + "movsd {$src, $dst|$dst, $src}", + [(set VR128:$dst, + (v2f64 (scalar_to_vector FR64:$src)))]>; +def MOVSD2PDrm : SDI<0x10, MRMSrcMem, (ops VR128:$dst, f64mem:$src), + "movsd {$src, $dst|$dst, $src}", + [(set VR128:$dst, + (v2f64 (scalar_to_vector (loadf64 addr:$src))))]>; + +def MOVDI2PDIrr : PDI<0x6E, MRMSrcReg, (ops VR128:$dst, R32:$src), + "movd {$src, $dst|$dst, $src}", + [(set VR128:$dst, + (v4i32 (scalar_to_vector R32:$src)))]>; +def MOVDI2PDIrm : PDI<0x6E, MRMSrcMem, (ops VR128:$dst, i32mem:$src), + "movd {$src, $dst|$dst, $src}", + [(set VR128:$dst, + (v4i32 (scalar_to_vector (loadi32 addr:$src))))]>; +// SSE2 instructions with XS prefix +def MOVQI2PQIrr : I<0x7E, MRMSrcReg, (ops VR128:$dst, VR64:$src), + "movq {$src, $dst|$dst, $src}", + [(set VR128:$dst, + (v2i64 (scalar_to_vector VR64:$src)))]>, XS, + Requires<[HasSSE2]>; +def MOVQI2PQIrm : I<0x7E, MRMSrcMem, (ops VR128:$dst, i64mem:$src), + "movq {$src, $dst|$dst, $src}", + [(set VR128:$dst, + (v2i64 (scalar_to_vector (loadi64 addr:$src))))]>, XS, + Requires<[HasSSE2]>; +// FIXME: may not be able to eliminate this movss with coalescing the src and +// dest register classes are different. We really want to write this pattern +// like this: +// def : Pat<(f32 (vector_extract (v4f32 VR128:$src), (i32 0))), +// (f32 FR32:$src)>; +def MOVPS2SSrr : SSI<0x10, MRMSrcReg, (ops FR32:$dst, VR128:$src), + "movss {$src, $dst|$dst, $src}", + [(set FR32:$dst, (vector_extract (v4f32 VR128:$src), + (i32 0)))]>; +def MOVPS2SSmr : SSI<0x10, MRMDestMem, (ops f32mem:$dst, VR128:$src), + "movss {$src, $dst|$dst, $src}", + [(store (f32 (vector_extract (v4f32 VR128:$src), + (i32 0))), addr:$dst)]>; +def MOVPD2SDrr : SDI<0x10, MRMSrcReg, (ops FR64:$dst, VR128:$src), + "movsd {$src, $dst|$dst, $src}", + [(set FR64:$dst, (vector_extract (v2f64 VR128:$src), + (i32 0)))]>; +def MOVPD2SDmr : SDI<0x10, MRMDestMem, (ops f64mem:$dst, VR128:$src), + "movsd {$src, $dst|$dst, $src}", + [(store (f64 (vector_extract (v2f64 VR128:$src), + (i32 0))), addr:$dst)]>; +def MOVPDI2DIrr : PDI<0x7E, MRMSrcReg, (ops R32:$dst, VR128:$src), + "movd {$src, $dst|$dst, $src}", + [(set R32:$dst, (vector_extract (v4i32 VR128:$src), + (i32 0)))]>; +def MOVPDI2DImr : PDI<0x7E, MRMDestMem, (ops i32mem:$dst, VR128:$src), + "movd {$src, $dst|$dst, $src}", + [(store (i32 (vector_extract (v4i32 VR128:$src), + (i32 0))), addr:$dst)]>; + +// Move to lower bits of a VR128, leaving upper bits alone. // Three operand (but two address) aliases. let isTwoAddress = 1 in { -def MOVZSS128rr : SSI<0x10, MRMSrcReg, (ops VR128:$dst, VR128:$src1, FR32:$src2), +def MOVLSS2PSrr : SSI<0x10, MRMSrcReg, (ops VR128:$dst, VR128:$src1, FR32:$src2), "movss {$src2, $dst|$dst, $src2}", []>; -def MOVZSD128rr : SDI<0x10, MRMSrcReg, (ops VR128:$dst, VR128:$src1, FR64:$src2), +def MOVLSD2PDrr : SDI<0x10, MRMSrcReg, (ops VR128:$dst, VR128:$src1, FR64:$src2), "movsd {$src2, $dst|$dst, $src2}", []>; -def MOVZD128rr : PDI<0x6E, MRMSrcReg, (ops VR128:$dst, VR128:$src1, R32:$src2), +def MOVLDI2PDIrr : PDI<0x6E, MRMSrcReg, (ops VR128:$dst, VR128:$src1, R32:$src2), "movd {$src2, $dst|$dst, $src2}", []>; -def MOVZQ128rr : I<0x7E, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR64:$src2), - "movq {$src2, $dst|$dst, $src2}", []>; } +// Move to lower bits of a VR128 and zeroing upper bits. // Loading from memory automatically zeroing upper bits. -def MOVZSS128rm : SSI<0x10, MRMSrcMem, (ops VR128:$dst, f32mem:$src), +def MOVZSS2PSrm : SSI<0x10, MRMSrcMem, (ops VR128:$dst, f32mem:$src), "movss {$src, $dst|$dst, $src}", [(set VR128:$dst, (v4f32 (X86zexts2vec (loadf32 addr:$src))))]>; -def MOVZSD128rm : SDI<0x10, MRMSrcMem, (ops VR128:$dst, f64mem:$src), +def MOVZSD2PDrm : SDI<0x10, MRMSrcMem, (ops VR128:$dst, f64mem:$src), "movsd {$src, $dst|$dst, $src}", [(set VR128:$dst, (v2f64 (X86zexts2vec (loadf64 addr:$src))))]>; -def MOVZD128rm : PDI<0x6E, MRMSrcMem, (ops VR128:$dst, i32mem:$src), - "movd {$src, $dst|$dst, $src}", - [(set VR128:$dst, - (v4i32 (X86zexts2vec (loadi32 addr:$src))))]>; +def MOVZDI2PDIrm : PDI<0x6E, MRMSrcMem, (ops VR128:$dst, i32mem:$src), + "movd {$src, $dst|$dst, $src}", + [(set VR128:$dst, + (v4i32 (X86zexts2vec (loadi32 addr:$src))))]>; +def MOVZQI2PQIrm : PDI<0x7E, MRMSrcMem, (ops VR128:$dst, i64mem:$src), + "movd {$src, $dst|$dst, $src}", + [(set VR128:$dst, + (v2i64 (X86zexts2vec (loadi64 addr:$src))))]>; //===----------------------------------------------------------------------===// // Non-Instruction Patterns @@ -1621,9 +1649,9 @@ // Scalar to v8i16 / v16i8. The source may be a R32, but only the lower 8 or // 16-bits matter. -def : Pat<(v8i16 (X86s2vec R32:$src)), (MOVD128rr R32:$src)>, +def : Pat<(v8i16 (X86s2vec R32:$src)), (MOVDI2PDIrr R32:$src)>, Requires<[HasSSE2]>; -def : Pat<(v16i8 (X86s2vec R32:$src)), (MOVD128rr R32:$src)>, +def : Pat<(v16i8 (X86s2vec R32:$src)), (MOVDI2PDIrr R32:$src)>, Requires<[HasSSE2]>; // bit_convert @@ -1659,17 +1687,15 @@ // Zeroing a VR128 then do a MOVS* to the lower bits. def : Pat<(v2f64 (X86zexts2vec FR64:$src)), - (MOVZSD128rr (V_SET0_PD), FR64:$src)>, Requires<[HasSSE2]>; + (MOVLSD2PDrr (V_SET0_PD), FR64:$src)>, Requires<[HasSSE2]>; def : Pat<(v4f32 (X86zexts2vec FR32:$src)), - (MOVZSS128rr (V_SET0_PS), FR32:$src)>, Requires<[HasSSE2]>; -def : Pat<(v2i64 (X86zexts2vec VR64:$src)), - (MOVZQ128rr (V_SET0_PI), VR64:$src)>, Requires<[HasSSE2]>; + (MOVLSS2PSrr (V_SET0_PS), FR32:$src)>, Requires<[HasSSE2]>; def : Pat<(v4i32 (X86zexts2vec R32:$src)), - (MOVZD128rr (V_SET0_PI), R32:$src)>, Requires<[HasSSE2]>; + (MOVLDI2PDIrr (V_SET0_PI), R32:$src)>, Requires<[HasSSE2]>; def : Pat<(v8i16 (X86zexts2vec R16:$src)), - (MOVZD128rr (V_SET0_PI), (MOVZX32rr16 R16:$src))>, Requires<[HasSSE2]>; + (MOVLDI2PDIrr (V_SET0_PI), (MOVZX32rr16 R16:$src))>, Requires<[HasSSE2]>; def : Pat<(v16i8 (X86zexts2vec R8:$src)), - (MOVZD128rr (V_SET0_PI), (MOVZX32rr8 R8:$src))>, Requires<[HasSSE2]>; + (MOVLDI2PDIrr (V_SET0_PI), (MOVZX32rr8 R8:$src))>, Requires<[HasSSE2]>; // Splat v2f64 / v2i64 def : Pat<(vector_shuffle (v2f64 VR128:$src), (undef), SSE_splat_mask:$sm), From lattner at cs.uiuc.edu Mon Apr 3 16:38:52 2006 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Mon, 3 Apr 2006 16:38:52 -0500 Subject: [llvm-commits] CVS: llvm/include/llvm/CodeGen/MachineFrameInfo.h Message-ID: <200604032138.QAA28575@zion.cs.uiuc.edu> Changes in directory llvm/include/llvm/CodeGen: MachineFrameInfo.h updated: 1.14 -> 1.15 --- Log message: Keep track of max stack alignment as objects are added. Remove an obsolete method. --- Diffs of the changes: (+3 -5) MachineFrameInfo.h | 8 +++----- 1 files changed, 3 insertions(+), 5 deletions(-) Index: llvm/include/llvm/CodeGen/MachineFrameInfo.h diff -u llvm/include/llvm/CodeGen/MachineFrameInfo.h:1.14 llvm/include/llvm/CodeGen/MachineFrameInfo.h:1.15 --- llvm/include/llvm/CodeGen/MachineFrameInfo.h:1.14 Sun Nov 6 11:40:18 2005 +++ llvm/include/llvm/CodeGen/MachineFrameInfo.h Mon Apr 3 16:38:39 2006 @@ -210,16 +210,14 @@ /// a postive identifier to represent it. /// int CreateStackObject(unsigned Size, unsigned Alignment) { + // Keep track of the maximum alignment. + if (MaxAlignment < Alignment) MaxAlignment = Alignment; + assert(Size != 0 && "Cannot allocate zero size stack objects!"); Objects.push_back(StackObject(Size, Alignment, -1)); return Objects.size()-NumFixedObjects-1; } - /// CreateStackObject - Create a stack object for a value of the specified - /// LLVM type. - /// - int CreateStackObject(const Type *Ty, const TargetData &TD); - /// CreateVariableSizedObject - Notify the MachineFrameInfo object that a /// variable sized object has been created. This must be created whenever a /// variable sized object is created, whether or not the index returned is From lattner at cs.uiuc.edu Mon Apr 3 16:39:16 2006 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Mon, 3 Apr 2006 16:39:16 -0500 Subject: [llvm-commits] CVS: llvm/lib/CodeGen/MachineFunction.cpp Message-ID: <200604032139.QAA28613@zion.cs.uiuc.edu> Changes in directory llvm/lib/CodeGen: MachineFunction.cpp updated: 1.86 -> 1.87 --- Log message: Remove unused method --- Diffs of the changes: (+0 -8) MachineFunction.cpp | 8 -------- 1 files changed, 8 deletions(-) Index: llvm/lib/CodeGen/MachineFunction.cpp diff -u llvm/lib/CodeGen/MachineFunction.cpp:1.86 llvm/lib/CodeGen/MachineFunction.cpp:1.87 --- llvm/lib/CodeGen/MachineFunction.cpp:1.86 Wed Feb 8 22:46:04 2006 +++ llvm/lib/CodeGen/MachineFunction.cpp Mon Apr 3 16:39:03 2006 @@ -297,14 +297,6 @@ // MachineFrameInfo implementation //===----------------------------------------------------------------------===// -/// CreateStackObject - Create a stack object for a value of the specified type. -/// -int MachineFrameInfo::CreateStackObject(const Type *Ty, const TargetData &TD) { - return CreateStackObject((unsigned)TD.getTypeSize(Ty), - TD.getTypeAlignment(Ty)); -} - - void MachineFrameInfo::print(const MachineFunction &MF, std::ostream &OS) const{ int ValOffset = MF.getTarget().getFrameInfo()->getOffsetOfLocalArea(); From lattner at cs.uiuc.edu Mon Apr 3 16:40:09 2006 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Mon, 3 Apr 2006 16:40:09 -0500 Subject: [llvm-commits] CVS: llvm/lib/CodeGen/PrologEpilogInserter.cpp Message-ID: <200604032140.QAA28653@zion.cs.uiuc.edu> Changes in directory llvm/lib/CodeGen: PrologEpilogInserter.cpp updated: 1.51 -> 1.52 --- Log message: The stack alignment is now computed dynamically, just verify it is correct. --- Diffs of the changes: (+2 -1) PrologEpilogInserter.cpp | 3 ++- 1 files changed, 2 insertions(+), 1 deletion(-) Index: llvm/lib/CodeGen/PrologEpilogInserter.cpp diff -u llvm/lib/CodeGen/PrologEpilogInserter.cpp:1.51 llvm/lib/CodeGen/PrologEpilogInserter.cpp:1.52 --- llvm/lib/CodeGen/PrologEpilogInserter.cpp:1.51 Sun Nov 6 11:43:20 2005 +++ llvm/lib/CodeGen/PrologEpilogInserter.cpp Mon Apr 3 16:39:57 2006 @@ -321,7 +321,8 @@ // Remember the required stack alignment in case targets need it to perform // dynamic stack alignment. - FFI->setMaxAlignment(MaxAlign); + assert(FFI->getMaxAlignment() == MaxAlign && + "Stack alignment calculation broken!"); } From lattner at cs.uiuc.edu Mon Apr 3 17:03:42 2006 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Mon, 3 Apr 2006 17:03:42 -0500 Subject: [llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp Message-ID: <200604032203.RAA29362@zion.cs.uiuc.edu> Changes in directory llvm/lib/Target/PowerPC: PPCRegisterInfo.cpp updated: 1.52 -> 1.53 --- Log message: Force use of a frame-pointer if there is anything on the stack that is aligned more than the OS keeps the stack aligned. --- Diffs of the changes: (+18 -7) PPCRegisterInfo.cpp | 25 ++++++++++++++++++------- 1 files changed, 18 insertions(+), 7 deletions(-) Index: llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp diff -u llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp:1.52 llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp:1.53 --- llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp:1.52 Tue Mar 28 07:48:33 2006 +++ llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp Mon Apr 3 17:03:29 2006 @@ -196,8 +196,16 @@ // pointer register. This is true if the function has variable sized allocas or // if frame pointer elimination is disabled. // -static bool hasFP(MachineFunction &MF) { - return NoFramePointerElim || MF.getFrameInfo()->hasVarSizedObjects(); +static bool hasFP(const MachineFunction &MF) { + const MachineFrameInfo *MFI = MF.getFrameInfo(); + unsigned TargetAlign = MF.getTarget().getFrameInfo()->getStackAlignment(); + + // If frame pointers are forced, if there are variable sized stack objects, + // or if there is an object on the stack that requires more alignment than is + // normally provided, use a frame pointer. + // + return NoFramePointerElim || MFI->hasVarSizedObjects() || + MFI->getMaxAlignment() > TargetAlign; } void PPCRegisterInfo:: @@ -331,9 +339,12 @@ MachineBasicBlock &MBB = MF.front(); // Prolog goes in entry BB MachineBasicBlock::iterator MBBI = MBB.begin(); MachineFrameInfo *MFI = MF.getFrameInfo(); + + // Do we have a frame pointer for this function? + bool HasFP = hasFP(MF); - // Scan the first few instructions of the prolog, looking for an UPDATE_VRSAVE - // instruction. If we find it, process it. + // Scan the prolog, looking for an UPDATE_VRSAVE instruction. If we find it, + // process it. for (unsigned i = 0; MBBI != MBB.end(); ++i, ++MBBI) { if (MBBI->getOpcode() == PPC::UPDATE_VRSAVE) { HandleVRSaveUpdate(MBBI, MF.getUsedPhysregs()); @@ -364,7 +375,7 @@ // If we are a leaf function, and use up to 224 bytes of stack space, // and don't have a frame pointer, then we do not need to adjust the stack // pointer (we fit in the Red Zone). - if ((NumBytes == 0) || (NumBytes <= 224 && !hasFP(MF) && !MFI->hasCalls() && + if ((NumBytes == 0) || (NumBytes <= 224 && !HasFP && !MFI->hasCalls() && MaxAlign <= TargetAlign)) { MFI->setStackSize(0); return; @@ -374,7 +385,7 @@ // of the stack and round the size to a multiple of the alignment. unsigned Align = std::max(TargetAlign, MaxAlign); unsigned GPRSize = 4; - unsigned Size = hasFP(MF) ? GPRSize + GPRSize : GPRSize; + unsigned Size = HasFP ? GPRSize + GPRSize : GPRSize; NumBytes = (NumBytes+Size+Align-1)/Align*Align; // Update frame info to pretend that this is part of the stack... @@ -407,7 +418,7 @@ } // If there is a frame pointer, copy R1 (SP) into R31 (FP) - if (hasFP(MF)) { + if (HasFP) { BuildMI(MBB, MBBI, PPC::STW, 3) .addReg(PPC::R31).addSImm(GPRSize).addReg(PPC::R1); BuildMI(MBB, MBBI, PPC::OR4, 2, PPC::R31).addReg(PPC::R1).addReg(PPC::R1); From evan.cheng at apple.com Mon Apr 3 17:31:06 2006 From: evan.cheng at apple.com (Evan Cheng) Date: Mon, 3 Apr 2006 17:31:06 -0500 Subject: [llvm-commits] CVS: llvm/lib/Target/X86/X86ISelLowering.cpp X86InstrSSE.td Message-ID: <200604032231.RAA30260@zion.cs.uiuc.edu> Changes in directory llvm/lib/Target/X86: X86ISelLowering.cpp updated: 1.152 -> 1.153 X86InstrSSE.td updated: 1.54 -> 1.55 --- Log message: Use movlpd to: store lower f64 extracted from v2f64. Use movhpd to: store upper f64 extracted from v2f64. --- Diffs of the changes: (+10 -6) X86ISelLowering.cpp | 2 ++ X86InstrSSE.td | 14 ++++++++------ 2 files changed, 10 insertions(+), 6 deletions(-) Index: llvm/lib/Target/X86/X86ISelLowering.cpp diff -u llvm/lib/Target/X86/X86ISelLowering.cpp:1.152 llvm/lib/Target/X86/X86ISelLowering.cpp:1.153 --- llvm/lib/Target/X86/X86ISelLowering.cpp:1.152 Mon Apr 3 15:53:28 2006 +++ llvm/lib/Target/X86/X86ISelLowering.cpp Mon Apr 3 17:30:54 2006 @@ -2712,6 +2712,8 @@ return Op; // UNPCKHPD the element to the lowest double word, then movsd. + // Note if the lower 64 bits of the result of the UNPCKHPD is then stored + // to a f64mem, the whole operation is folded into a single MOVHPDmr. MVT::ValueType MaskVT = MVT::getIntVectorWithNumElements(4); std::vector IdxVec; IdxVec.push_back(DAG.getConstant(1, MVT::getVectorBaseType(MaskVT))); Index: llvm/lib/Target/X86/X86InstrSSE.td diff -u llvm/lib/Target/X86/X86InstrSSE.td:1.54 llvm/lib/Target/X86/X86InstrSSE.td:1.55 --- llvm/lib/Target/X86/X86InstrSSE.td:1.54 Mon Apr 3 15:53:28 2006 +++ llvm/lib/Target/X86/X86InstrSSE.td Mon Apr 3 17:30:54 2006 @@ -713,12 +713,18 @@ def MOVLPSmr : PSI<0x13, MRMDestMem, (ops f64mem:$dst, VR128:$src), "movlps {$src, $dst|$dst, $src}", []>; def MOVLPDmr : PDI<0x13, MRMDestMem, (ops f64mem:$dst, VR128:$src), - "movlpd {$src, $dst|$dst, $src}", []>; + "movlpd {$src, $dst|$dst, $src}", + [(store (f64 (vector_extract (v2f64 VR128:$src), + (i32 0))), addr:$dst)]>; def MOVHPSmr : PSI<0x17, MRMDestMem, (ops f64mem:$dst, VR128:$src), "movhps {$src, $dst|$dst, $src}", []>; def MOVHPDmr : PDI<0x17, MRMDestMem, (ops f64mem:$dst, VR128:$src), - "movhpd {$src, $dst|$dst, $src}", []>; + "movhpd {$src, $dst|$dst, $src}", + [(store (f64 (vector_extract + (v2f64 (vector_shuffle VR128:$src, (undef), + UNPCKH_shuffle_mask)), (i32 0))), + addr:$dst)]>; let isTwoAddress = 1 in { def MOVLHPSrr : PSI<0x16, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2), @@ -1561,10 +1567,6 @@ "movsd {$src, $dst|$dst, $src}", [(set FR64:$dst, (vector_extract (v2f64 VR128:$src), (i32 0)))]>; -def MOVPD2SDmr : SDI<0x10, MRMDestMem, (ops f64mem:$dst, VR128:$src), - "movsd {$src, $dst|$dst, $src}", - [(store (f64 (vector_extract (v2f64 VR128:$src), - (i32 0))), addr:$dst)]>; def MOVPDI2DIrr : PDI<0x7E, MRMSrcReg, (ops R32:$dst, VR128:$src), "movd {$src, $dst|$dst, $src}", [(set R32:$dst, (vector_extract (v4i32 VR128:$src), From lattner at cs.uiuc.edu Mon Apr 3 18:15:02 2006 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Mon, 3 Apr 2006 18:15:02 -0500 Subject: [llvm-commits] CVS: llvm/lib/Target/TargetData.cpp Message-ID: <200604032315.SAA31754@zion.cs.uiuc.edu> Changes in directory llvm/lib/Target: TargetData.cpp updated: 1.60 -> 1.61 --- Log message: revert previous patch --- Diffs of the changes: (+1 -1) TargetData.cpp | 2 +- 1 files changed, 1 insertion(+), 1 deletion(-) Index: llvm/lib/Target/TargetData.cpp diff -u llvm/lib/Target/TargetData.cpp:1.60 llvm/lib/Target/TargetData.cpp:1.61 --- llvm/lib/Target/TargetData.cpp:1.60 Mon Apr 3 14:28:50 2006 +++ llvm/lib/Target/TargetData.cpp Mon Apr 3 18:14:49 2006 @@ -217,7 +217,7 @@ Size = AlignedSize*PTy->getNumElements(); // FIXME: The alignments of specific packed types are target dependent. // For now, just set it to be equal to Size. - Alignment = (Size+7)/8; + Alignment = Size; return; } case Type::StructTyID: { From evan.cheng at apple.com Mon Apr 3 18:49:29 2006 From: evan.cheng at apple.com (Evan Cheng) Date: Mon, 3 Apr 2006 18:49:29 -0500 Subject: [llvm-commits] CVS: llvm/lib/Target/X86/X86InstrSSE.td Message-ID: <200604032349.SAA32130@zion.cs.uiuc.edu> Changes in directory llvm/lib/Target/X86: X86InstrSSE.td updated: 1.55 -> 1.56 --- Log message: Some SSE1 intrinsics: min, max, sqrt, etc. --- Diffs of the changes: (+91 -78) X86InstrSSE.td | 169 ++++++++++++++++++++++++++++++--------------------------- 1 files changed, 91 insertions(+), 78 deletions(-) Index: llvm/lib/Target/X86/X86InstrSSE.td diff -u llvm/lib/Target/X86/X86InstrSSE.td:1.55 llvm/lib/Target/X86/X86InstrSSE.td:1.56 --- llvm/lib/Target/X86/X86InstrSSE.td:1.55 Mon Apr 3 17:30:54 2006 +++ llvm/lib/Target/X86/X86InstrSSE.td Mon Apr 3 18:49:17 2006 @@ -171,6 +171,45 @@ //===----------------------------------------------------------------------===// // Helpers for defining instructions that directly correspond to intrinsics. +class SS_Intrr o, string asm, Intrinsic IntId, ValueType Ty> + : SSI; +class SS_Intrm o, string asm, Intrinsic IntId, ValueType Ty> + : SSI; +class SD_Intrr o, string asm, Intrinsic IntId, ValueType Ty> + : SDI; +class SD_Intrm o, string asm, Intrinsic IntId, ValueType Ty> + : SDI; + +class PS_Intr o, string asm, Intrinsic IntId> + : PSI; +class PS_Intm o, string asm, Intrinsic IntId> + : PSI; +class PD_Intr o, string asm, Intrinsic IntId> + : PDI; +class PD_Intm o, string asm, Intrinsic IntId> + : PDI; + +class PS_Intrr o, string asm, Intrinsic IntId> + : PSI; +class PS_Intrm o, string asm, Intrinsic IntId> + : PSI; +class PD_Intrr o, string asm, Intrinsic IntId> + : PDI; +class PD_Intrm o, string asm, Intrinsic IntId> + : PDI; + class S3S_Intrr o, string asm, Intrinsic IntId> : S3SI; @@ -435,46 +474,22 @@ (load addr:$src)))]>; let isTwoAddress = 1 in { -def Int_MAXSSrr : SSI<0x5F, MRMSrcReg, (ops VR128:$dst, VR128:$src1, - VR128:$src2), - "maxss {$src2, $dst|$dst, $src2}", - [(set VR128:$dst, (int_x86_sse_max_ss VR128:$src1, - VR128:$src2))]>; -def Int_MAXSSrm : SSI<0x5F, MRMSrcMem, (ops VR128:$dst, VR128:$src1, - f32mem:$src2), - "maxss {$src2, $dst|$dst, $src2}", - [(set VR128:$dst, (int_x86_sse_max_ss VR128:$src1, - (load addr:$src2)))]>; -def Int_MAXSDrr : SDI<0x5F, MRMSrcReg, (ops VR128:$dst, VR128:$src1, - VR128:$src2), - "maxsd {$src2, $dst|$dst, $src2}", - [(set VR128:$dst, (int_x86_sse2_max_sd VR128:$src1, - VR128:$src2))]>; -def Int_MAXSDrm : SDI<0x5F, MRMSrcMem, (ops VR128:$dst, VR128:$src1, - f64mem:$src2), - "maxsd {$src2, $dst|$dst, $src2}", - [(set VR128:$dst, (int_x86_sse2_max_sd VR128:$src1, - (load addr:$src2)))]>; -def Int_MINSSrr : SSI<0x5D, MRMSrcReg, (ops VR128:$dst, VR128:$src1, - VR128:$src2), - "minss {$src2, $dst|$dst, $src2}", - [(set VR128:$dst, (int_x86_sse_min_ss VR128:$src1, - VR128:$src2))]>; -def Int_MINSSrm : SSI<0x5D, MRMSrcMem, (ops VR128:$dst, VR128:$src1, - f32mem:$src2), - "minss {$src2, $dst|$dst, $src2}", - [(set VR128:$dst, (int_x86_sse_min_ss VR128:$src1, - (load addr:$src2)))]>; -def Int_MINSDrr : SDI<0x5D, MRMSrcReg, (ops VR128:$dst, VR128:$src1, - VR128:$src2), - "minsd {$src2, $dst|$dst, $src2}", - [(set VR128:$dst, (int_x86_sse2_min_sd VR128:$src1, - VR128:$src2))]>; -def Int_MINSDrm : SDI<0x5D, MRMSrcMem, (ops VR128:$dst, VR128:$src1, - f64mem:$src2), - "minsd {$src2, $dst|$dst, $src2}", - [(set VR128:$dst, (int_x86_sse2_min_sd VR128:$src1, - (load addr:$src2)))]>; +def Int_MAXSSrr : SS_Intrr<0x5F, "maxss {$src2, $dst|$dst, $src2}", + int_x86_sse_max_ss, v4f32>; +def Int_MAXSSrm : SS_Intrm<0x5F, "maxss {$src2, $dst|$dst, $src2}", + int_x86_sse_max_ss, v4f32>; +def Int_MAXSDrr : SD_Intrr<0x5F, "maxsd {$src2, $dst|$dst, $src2}", + int_x86_sse2_max_sd, v2f64>; +def Int_MAXSDrm : SD_Intrm<0x5F, "maxsd {$src2, $dst|$dst, $src2}", + int_x86_sse2_max_sd, v2f64>; +def Int_MINSSrr : SS_Intrr<0x5D, "minss {$src2, $dst|$dst, $src2}", + int_x86_sse_min_ss, v4f32>; +def Int_MINSSrm : SS_Intrm<0x5D, "minss {$src2, $dst|$dst, $src2}", + int_x86_sse_min_ss, v4f32>; +def Int_MINSDrr : SD_Intrr<0x5D, "minsd {$src2, $dst|$dst, $src2}", + int_x86_sse2_min_sd, v2f64>; +def Int_MINSDrm : SD_Intrm<0x5D, "minsd {$src2, $dst|$dst, $src2}", + int_x86_sse2_min_sd, v2f64>; } // Conversion instructions @@ -863,44 +878,42 @@ (load addr:$src2))))]>; } -def SQRTPSrr : PSI<0x51, MRMSrcReg, (ops VR128:$dst, VR128:$src), - "sqrtps {$src, $dst|$dst, $src}", - [(set VR128:$dst, (v4f32 (fsqrt VR128:$src)))]>; -def SQRTPSrm : PSI<0x51, MRMSrcMem, (ops VR128:$dst, f128mem:$src), - "sqrtps {$src, $dst|$dst, $src}", - [(set VR128:$dst, (v4f32 (fsqrt (load addr:$src))))]>; -def SQRTPDrr : PDI<0x51, MRMSrcReg, (ops VR128:$dst, VR128:$src), - "sqrtpd {$src, $dst|$dst, $src}", - [(set VR128:$dst, (v2f64 (fsqrt VR128:$src)))]>; -def SQRTPDrm : PDI<0x51, MRMSrcMem, (ops VR128:$dst, f128mem:$src), - "sqrtpd {$src, $dst|$dst, $src}", - [(set VR128:$dst, (v2f64 (fsqrt (load addr:$src))))]>; - -def RSQRTPSrr : PSI<0x52, MRMSrcReg, (ops VR128:$dst, VR128:$src), - "rsqrtps {$src, $dst|$dst, $src}", []>; -def RSQRTPSrm : PSI<0x52, MRMSrcMem, (ops VR128:$dst, f128mem:$src), - "rsqrtps {$src, $dst|$dst, $src}", []>; -def RCPPSrr : PSI<0x53, MRMSrcReg, (ops VR128:$dst, VR128:$src), - "rcpps {$src, $dst|$dst, $src}", []>; -def RCPPSrm : PSI<0x53, MRMSrcMem, (ops VR128:$dst, f128mem:$src), - "rcpps {$src, $dst|$dst, $src}", []>; - -def MAXPSrr : PSI<0x5F, MRMSrcReg, (ops VR128:$dst, VR128:$src), - "maxps {$src, $dst|$dst, $src}", []>; -def MAXPSrm : PSI<0x5F, MRMSrcMem, (ops VR128:$dst, f128mem:$src), - "maxps {$src, $dst|$dst, $src}", []>; -def MAXPDrr : PDI<0x5F, MRMSrcReg, (ops VR128:$dst, VR128:$src), - "maxpd {$src, $dst|$dst, $src}", []>; -def MAXPDrm : PDI<0x5F, MRMSrcMem, (ops VR128:$dst, f128mem:$src), - "maxpd {$src, $dst|$dst, $src}", []>; -def MINPSrr : PSI<0x5D, MRMSrcReg, (ops VR128:$dst, VR128:$src), - "minps {$src, $dst|$dst, $src}", []>; -def MINPSrm : PSI<0x5D, MRMSrcMem, (ops VR128:$dst, f128mem:$src), - "minps {$src, $dst|$dst, $src}", []>; -def MINPDrr : PDI<0x5D, MRMSrcReg, (ops VR128:$dst, VR128:$src), - "minpd {$src, $dst|$dst, $src}", []>; -def MINPDrm : PDI<0x5D, MRMSrcMem, (ops VR128:$dst, f128mem:$src), - "minpd {$src, $dst|$dst, $src}", []>; +def SQRTPSrr : PS_Intr<0x51, "sqrtps {$src, $dst|$dst, $src}", + int_x86_sse_sqrt_ps>; +def SQRTPSrm : PS_Intm<0x51, "sqrtps {$src, $dst|$dst, $src}", + int_x86_sse_sqrt_ps>; +def SQRTPDrr : PD_Intr<0x51, "sqrtpd {$src, $dst|$dst, $src}", + int_x86_sse2_sqrt_pd>; +def SQRTPDrm : PD_Intm<0x51, "sqrtpd {$src, $dst|$dst, $src}", + int_x86_sse2_sqrt_pd>; + +def RSQRTPSrr : PS_Intr<0x52, "rsqrtps {$src, $dst|$dst, $src}", + int_x86_sse_rsqrt_ps>; +def RSQRTPSrm : PS_Intm<0x52, "rsqrtps {$src, $dst|$dst, $src}", + int_x86_sse_rsqrt_ps>; +def RCPPSrr : PS_Intr<0x53, "rcpps {$src, $dst|$dst, $src}", + int_x86_sse_rcp_ps>; +def RCPPSrm : PS_Intm<0x53, "rcpps {$src, $dst|$dst, $src}", + int_x86_sse_rcp_ps>; + +let isTwoAddress = 1 in { +def MAXPSrr : PS_Intrr<0x5F, "maxps {$src2, $dst|$dst, $src2}", + int_x86_sse_max_ps>; +def MAXPSrm : PS_Intrm<0x5F, "maxps {$src2, $dst|$dst, $src2}", + int_x86_sse_max_ps>; +def MAXPDrr : PD_Intrr<0x5F, "maxpd {$src2, $dst|$dst, $src2}", + int_x86_sse2_max_pd>; +def MAXPDrm : PD_Intrm<0x5F, "maxpd {$src2, $dst|$dst, $src2}", + int_x86_sse2_max_pd>; +def MINPSrr : PS_Intrr<0x5D, "minps {$src2, $dst|$dst, $src2}", + int_x86_sse_min_ps>; +def MINPSrm : PS_Intrm<0x5D, "minps {$src2, $dst|$dst, $src2}", + int_x86_sse_min_ps>; +def MINPDrr : PD_Intrr<0x5D, "minpd {$src2, $dst|$dst, $src2}", + int_x86_sse2_min_pd>; +def MINPDrm : PD_Intrm<0x5D, "minpd {$src2, $dst|$dst, $src2}", + int_x86_sse2_min_pd>; +} // Logical let isTwoAddress = 1 in { From lattner at cs.uiuc.edu Mon Apr 3 18:55:56 2006 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Mon, 3 Apr 2006 18:55:56 -0500 Subject: [llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCISelLowering.cpp Message-ID: <200604032355.SAA32203@zion.cs.uiuc.edu> Changes in directory llvm/lib/Target/PowerPC: PPCISelLowering.cpp updated: 1.126 -> 1.127 --- Log message: Make sure to mark unsupported SCALAR_TO_VECTOR operations as expand. --- Diffs of the changes: (+5 -1) PPCISelLowering.cpp | 6 +++++- 1 files changed, 5 insertions(+), 1 deletion(-) Index: llvm/lib/Target/PowerPC/PPCISelLowering.cpp diff -u llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.126 llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.127 --- llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.126 Sun Apr 2 00:26:07 2006 +++ llvm/lib/Target/PowerPC/PPCISelLowering.cpp Mon Apr 3 18:55:43 2006 @@ -182,7 +182,7 @@ setOperationAction(ISD::XOR , (MVT::ValueType)VT, Legal); // We can custom expand all VECTOR_SHUFFLEs to VPERM. - setOperationAction(ISD::VECTOR_SHUFFLE, (MVT::ValueType)VT, Custom); + setOperationAction(ISD::VECTOR_SHUFFLE, (MVT::ValueType)VT, Promote); setOperationAction(ISD::MUL , (MVT::ValueType)VT, Expand); setOperationAction(ISD::SDIV, (MVT::ValueType)VT, Expand); @@ -192,8 +192,12 @@ setOperationAction(ISD::EXTRACT_VECTOR_ELT, (MVT::ValueType)VT, Expand); setOperationAction(ISD::INSERT_VECTOR_ELT, (MVT::ValueType)VT, Expand); setOperationAction(ISD::BUILD_VECTOR, (MVT::ValueType)VT, Expand); + + setOperationAction(ISD::SCALAR_TO_VECTOR, (MVT::ValueType)VT, Expand); } + setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v16i8, Custom); + addRegisterClass(MVT::v4f32, PPC::VRRCRegisterClass); addRegisterClass(MVT::v4i32, PPC::VRRCRegisterClass); addRegisterClass(MVT::v8i16, PPC::VRRCRegisterClass); From lattner at cs.uiuc.edu Mon Apr 3 18:58:17 2006 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Mon, 3 Apr 2006 18:58:17 -0500 Subject: [llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCISelLowering.cpp Message-ID: <200604032358.SAA32311@zion.cs.uiuc.edu> Changes in directory llvm/lib/Target/PowerPC: PPCISelLowering.cpp updated: 1.127 -> 1.128 --- Log message: Revert accidentally committed hunks. --- Diffs of the changes: (+1 -3) PPCISelLowering.cpp | 4 +--- 1 files changed, 1 insertion(+), 3 deletions(-) Index: llvm/lib/Target/PowerPC/PPCISelLowering.cpp diff -u llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.127 llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.128 --- llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.127 Mon Apr 3 18:55:43 2006 +++ llvm/lib/Target/PowerPC/PPCISelLowering.cpp Mon Apr 3 18:58:04 2006 @@ -182,7 +182,7 @@ setOperationAction(ISD::XOR , (MVT::ValueType)VT, Legal); // We can custom expand all VECTOR_SHUFFLEs to VPERM. - setOperationAction(ISD::VECTOR_SHUFFLE, (MVT::ValueType)VT, Promote); + setOperationAction(ISD::VECTOR_SHUFFLE, (MVT::ValueType)VT, Custom); setOperationAction(ISD::MUL , (MVT::ValueType)VT, Expand); setOperationAction(ISD::SDIV, (MVT::ValueType)VT, Expand); @@ -196,8 +196,6 @@ setOperationAction(ISD::SCALAR_TO_VECTOR, (MVT::ValueType)VT, Expand); } - setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v16i8, Custom); - addRegisterClass(MVT::v4f32, PPC::VRRCRegisterClass); addRegisterClass(MVT::v4i32, PPC::VRRCRegisterClass); addRegisterClass(MVT::v8i16, PPC::VRRCRegisterClass); From lattner at cs.uiuc.edu Mon Apr 3 19:05:26 2006 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Mon, 3 Apr 2006 19:05:26 -0500 Subject: [llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCInstrAltivec.td Message-ID: <200604040005.TAA32449@zion.cs.uiuc.edu> Changes in directory llvm/lib/Target/PowerPC: PPCInstrAltivec.td updated: 1.31 -> 1.32 --- Log message: Plug in the byte and short splats --- Diffs of the changes: (+4 -2) PPCInstrAltivec.td | 6 ++++-- 1 files changed, 4 insertions(+), 2 deletions(-) Index: llvm/lib/Target/PowerPC/PPCInstrAltivec.td diff -u llvm/lib/Target/PowerPC/PPCInstrAltivec.td:1.31 llvm/lib/Target/PowerPC/PPCInstrAltivec.td:1.32 --- llvm/lib/Target/PowerPC/PPCInstrAltivec.td:1.31 Mon Apr 3 10:58:28 2006 +++ llvm/lib/Target/PowerPC/PPCInstrAltivec.td Mon Apr 3 19:05:13 2006 @@ -293,10 +293,12 @@ def VSPLTB : VXForm_1<524, (ops VRRC:$vD, u5imm:$UIMM, VRRC:$vB), "vspltb $vD, $vB, $UIMM", VecPerm, - []>; + [(set VRRC:$vD, (vector_shuffle (v16i8 VRRC:$vB), (undef), + VSPLT_shuffle_mask:$UIMM))]>; def VSPLTH : VXForm_1<588, (ops VRRC:$vD, u5imm:$UIMM, VRRC:$vB), "vsplth $vD, $vB, $UIMM", VecPerm, - []>; + [(set VRRC:$vD, (vector_shuffle (v8i16 VRRC:$vB), (undef), + VSPLT_shuffle_mask:$UIMM))]>; def VSPLTW : VXForm_1<652, (ops VRRC:$vD, u5imm:$UIMM, VRRC:$vB), "vspltw $vD, $vB, $UIMM", VecPerm, [(set VRRC:$vD, (vector_shuffle (v4f32 VRRC:$vB), (undef), From evan.cheng at apple.com Mon Apr 3 19:11:06 2006 From: evan.cheng at apple.com (Evan Cheng) Date: Mon, 3 Apr 2006 19:11:06 -0500 Subject: [llvm-commits] CVS: llvm/lib/Target/X86/X86InstrSSE.td Message-ID: <200604040011.TAA32485@zion.cs.uiuc.edu> Changes in directory llvm/lib/Target/X86: X86InstrSSE.td updated: 1.56 -> 1.57 --- Log message: Compact some intrinsic definitions. --- Diffs of the changes: (+84 -123) X86InstrSSE.td | 207 +++++++++++++++++++++++---------------------------------- 1 files changed, 84 insertions(+), 123 deletions(-) Index: llvm/lib/Target/X86/X86InstrSSE.td diff -u llvm/lib/Target/X86/X86InstrSSE.td:1.56 llvm/lib/Target/X86/X86InstrSSE.td:1.57 --- llvm/lib/Target/X86/X86InstrSSE.td:1.56 Mon Apr 3 18:49:17 2006 +++ llvm/lib/Target/X86/X86InstrSSE.td Mon Apr 3 19:10:53 2006 @@ -171,18 +171,31 @@ //===----------------------------------------------------------------------===// // Helpers for defining instructions that directly correspond to intrinsics. -class SS_Intrr o, string asm, Intrinsic IntId, ValueType Ty> +class SS_Intr o, string asm, Intrinsic IntId> + : SSI; +class SS_Intm o, string asm, Intrinsic IntId> + : SSI; +class SD_Intr o, string asm, Intrinsic IntId> + : SDI; +class SD_Intm o, string asm, Intrinsic IntId> + : SDI; + +class SS_Intrr o, string asm, Intrinsic IntId> : SSI; -class SS_Intrm o, string asm, Intrinsic IntId, ValueType Ty> + [(set VR128:$dst, (v4f32 (IntId VR128:$src1, VR128:$src2)))]>; +class SS_Intrm o, string asm, Intrinsic IntId> : SSI; -class SD_Intrr o, string asm, Intrinsic IntId, ValueType Ty> + [(set VR128:$dst, (v4f32 (IntId VR128:$src1, (load addr:$src2))))]>; +class SD_Intrr o, string asm, Intrinsic IntId> : SDI; -class SD_Intrm o, string asm, Intrinsic IntId, ValueType Ty> + [(set VR128:$dst, (v2f64 (IntId VR128:$src1, VR128:$src2)))]>; +class SD_Intrm o, string asm, Intrinsic IntId> : SDI; + [(set VR128:$dst, (v2f64 (IntId VR128:$src1, (load addr:$src2))))]>; class PS_Intr o, string asm, Intrinsic IntId> : PSI; -def Int_ADDSDrr : SDI<0x58, MRMSrcReg, (ops VR128:$dst, VR128:$src1, - VR128:$src2), - "addsd {$src2, $dst|$dst, $src2}", - [(set VR128:$dst, (int_x86_sse2_add_sd VR128:$src1, - VR128:$src2))]>; -def Int_MULSSrr : SSI<0x59, MRMSrcReg, (ops VR128:$dst, VR128:$src1, - VR128:$src2), - "mulss {$src2, $dst|$dst, $src2}", - [(set VR128:$dst, (int_x86_sse_mul_ss VR128:$src1, - VR128:$src2))]>; -def Int_MULSDrr : SDI<0x59, MRMSrcReg, (ops VR128:$dst, VR128:$src1, - VR128:$src2), - "mulsd {$src2, $dst|$dst, $src2}", - [(set VR128:$dst, (int_x86_sse2_mul_sd VR128:$src1, - VR128:$src2))]>; -} - -def Int_ADDSSrm : SSI<0x58, MRMSrcMem, (ops VR128:$dst, VR128:$src1, - f32mem:$src2), - "addss {$src2, $dst|$dst, $src2}", - [(set VR128:$dst, (int_x86_sse_add_ss VR128:$src1, - (load addr:$src2)))]>; -def Int_ADDSDrm : SDI<0x58, MRMSrcMem, (ops VR128:$dst, VR128:$src1, - f64mem:$src2), - "addsd {$src2, $dst|$dst, $src2}", - [(set VR128:$dst, (int_x86_sse2_add_sd VR128:$src1, - (load addr:$src2)))]>; -def Int_MULSSrm : SSI<0x59, MRMSrcMem, (ops VR128:$dst, VR128:$src1, - f32mem:$src2), - "mulss {$src2, $dst|$dst, $src2}", - [(set VR128:$dst, (int_x86_sse_mul_ss VR128:$src1, - (load addr:$src2)))]>; -def Int_MULSDrm : SDI<0x59, MRMSrcMem, (ops VR128:$dst, VR128:$src1, - f64mem:$src2), - "mulsd {$src2, $dst|$dst, $src2}", - [(set VR128:$dst, (int_x86_sse2_mul_sd VR128:$src1, - (load addr:$src2)))]>; - -def Int_DIVSSrr : SSI<0x5E, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2), - "divss {$src2, $dst|$dst, $src2}", - [(set VR128:$dst, (int_x86_sse_div_ss VR128:$src1, - VR128:$src2))]>; -def Int_DIVSSrm : SSI<0x5E, MRMSrcMem, (ops VR128:$dst, VR128:$src1, f32mem:$src2), - "divss {$src2, $dst|$dst, $src2}", - [(set VR128:$dst, (int_x86_sse_div_ss VR128:$src1, - (load addr:$src2)))]>; -def Int_DIVSDrr : SDI<0x5E, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2), - "divsd {$src2, $dst|$dst, $src2}", - [(set VR128:$dst, (int_x86_sse2_div_sd VR128:$src1, - VR128:$src2))]>; -def Int_DIVSDrm : SDI<0x5E, MRMSrcMem, (ops VR128:$dst, VR128:$src1, f64mem:$src2), - "divsd {$src2, $dst|$dst, $src2}", - [(set VR128:$dst, (int_x86_sse2_div_sd VR128:$src1, - (load addr:$src2)))]>; - -def Int_SUBSSrr : SSI<0x5C, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2), - "subss {$src2, $dst|$dst, $src2}", - [(set VR128:$dst, (int_x86_sse_sub_ss VR128:$src1, - VR128:$src2))]>; -def Int_SUBSSrm : SSI<0x5C, MRMSrcMem, (ops VR128:$dst, VR128:$src1, f32mem:$src2), - "subss {$src2, $dst|$dst, $src2}", - [(set VR128:$dst, (int_x86_sse_sub_ss VR128:$src1, - (load addr:$src2)))]>; -def Int_SUBSDrr : SDI<0x5C, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2), - "subsd {$src2, $dst|$dst, $src2}", - [(set VR128:$dst, (int_x86_sse2_sub_sd VR128:$src1, - VR128:$src2))]>; -def Int_SUBSDrm : SDI<0x5C, MRMSrcMem, (ops VR128:$dst, VR128:$src1, f64mem:$src2), - "subsd {$src2, $dst|$dst, $src2}", - [(set VR128:$dst, (int_x86_sse2_sub_sd VR128:$src1, - (load addr:$src2)))]>; -} - -def Int_SQRTSSrr : SSI<0x51, MRMSrcReg, (ops VR128:$dst, VR128:$src), - "sqrtss {$src, $dst|$dst, $src}", - [(set VR128:$dst, (int_x86_sse_sqrt_ss VR128:$src))]>; -def Int_SQRTSSrm : SSI<0x51, MRMSrcMem, (ops VR128:$dst, f32mem:$src), - "sqrtss {$src, $dst|$dst, $src}", - [(set VR128:$dst, (int_x86_sse_sqrt_ss - (load addr:$src)))]>; -def Int_SQRTSDrr : SDI<0x51, MRMSrcReg, (ops VR128:$dst, VR128:$src), - "sqrtsd {$src, $dst|$dst, $src}", - [(set VR128:$dst, (int_x86_sse2_sqrt_sd VR128:$src))]>; -def Int_SQRTSDrm : SDI<0x51, MRMSrcMem, (ops VR128:$dst, f64mem:$src), - "sqrtsd {$src, $dst|$dst, $src}", - [(set VR128:$dst, (int_x86_sse2_sqrt_sd - (load addr:$src)))]>; - -def Int_RSQRTSSrr : SSI<0x52, MRMSrcReg, (ops VR128:$dst, VR128:$src), - "rsqrtss {$src, $dst|$dst, $src}", - [(set VR128:$dst, (int_x86_sse_rsqrt_ss VR128:$src))]>; -def Int_RSQRTSSrm : SSI<0x52, MRMSrcMem, (ops VR128:$dst, f32mem:$src), - "rsqrtss {$src, $dst|$dst, $src}", - [(set VR128:$dst, (int_x86_sse_rsqrt_ss - (load addr:$src)))]>; -def Int_RCPSSrr : SSI<0x53, MRMSrcReg, (ops VR128:$dst, VR128:$src), - "rcpss {$src, $dst|$dst, $src}", - [(set VR128:$dst, (int_x86_sse_rcp_ss VR128:$src))]>; -def Int_RCPSSrm : SSI<0x53, MRMSrcMem, (ops VR128:$dst, f32mem:$src), - "rcpss {$src, $dst|$dst, $src}", - [(set VR128:$dst, (int_x86_sse_rcp_ss - (load addr:$src)))]>; +def Int_ADDSSrr : SS_Intrr<0x58, "addss {$src2, $dst|$dst, $src2}", + int_x86_sse_add_ss>; +def Int_ADDSDrr : SD_Intrr<0x58, "addsd {$src2, $dst|$dst, $src2}", + int_x86_sse2_add_sd>; +def Int_MULSSrr : SS_Intrr<0x59, "mulss {$src2, $dst|$dst, $src2}", + int_x86_sse_mul_ss>; +def Int_MULSDrr : SD_Intrr<0x59, "mulsd {$src2, $dst|$dst, $src2}", + int_x86_sse2_mul_sd>; +} + +def Int_ADDSSrm : SS_Intrm<0x58, "addss {$src2, $dst|$dst, $src2}", + int_x86_sse_add_ss>; +def Int_ADDSDrm : SD_Intrm<0x58, "addsd {$src2, $dst|$dst, $src2}", + int_x86_sse2_add_sd>; +def Int_MULSSrm : SS_Intrm<0x59, "mulss {$src2, $dst|$dst, $src2}", + int_x86_sse_mul_ss>; +def Int_MULSDrm : SD_Intrm<0x59, "mulsd {$src2, $dst|$dst, $src2}", + int_x86_sse2_mul_sd>; + +def Int_DIVSSrr : SS_Intrr<0x5E, "divss {$src2, $dst|$dst, $src2}", + int_x86_sse_div_ss>; +def Int_DIVSSrm : SS_Intrm<0x5E, "divss {$src2, $dst|$dst, $src2}", + int_x86_sse_div_ss>; +def Int_DIVSDrr : SD_Intrr<0x5E, "divsd {$src2, $dst|$dst, $src2}", + int_x86_sse2_div_sd>; +def Int_DIVSDrm : SD_Intrm<0x5E, "divsd {$src2, $dst|$dst, $src2}", + int_x86_sse2_div_sd>; + +def Int_SUBSSrr : SS_Intrr<0x5C, "subss {$src2, $dst|$dst, $src2}", + int_x86_sse_sub_ss>; +def Int_SUBSSrm : SS_Intrm<0x5C, "subss {$src2, $dst|$dst, $src2}", + int_x86_sse_sub_ss>; +def Int_SUBSDrr : SD_Intrr<0x5C, "subsd {$src2, $dst|$dst, $src2}", + int_x86_sse2_sub_sd>; +def Int_SUBSDrm : SD_Intrm<0x5C, "subsd {$src2, $dst|$dst, $src2}", + int_x86_sse2_sub_sd>; +} + +def Int_SQRTSSrr : SS_Intr<0x51, "sqrtss {$src, $dst|$dst, $src}", + int_x86_sse_sqrt_ss>; +def Int_SQRTSSrm : SS_Intm<0x51, "sqrtss {$src, $dst|$dst, $src}", + int_x86_sse_sqrt_ss>; +def Int_SQRTSDrr : SD_Intr<0x51, "sqrtsd {$src, $dst|$dst, $src}", + int_x86_sse2_sqrt_sd>; +def Int_SQRTSDrm : SD_Intm<0x51, "sqrtsd {$src, $dst|$dst, $src}", + int_x86_sse2_sqrt_sd>; + +def Int_RSQRTSSrr : SS_Intr<0x52, "rsqrtss {$src, $dst|$dst, $src}", + int_x86_sse_rsqrt_ss>; +def Int_RSQRTSSrm : SS_Intm<0x52, "rsqrtss {$src, $dst|$dst, $src}", + int_x86_sse_rsqrt_ss>; +def Int_RCPSSrr : SS_Intr<0x53, "rcpss {$src, $dst|$dst, $src}", + int_x86_sse_rcp_ss>; +def Int_RCPSSrm : SS_Intm<0x53, "rcpss {$src, $dst|$dst, $src}", + int_x86_sse_rcp_ss>; let isTwoAddress = 1 in { def Int_MAXSSrr : SS_Intrr<0x5F, "maxss {$src2, $dst|$dst, $src2}", - int_x86_sse_max_ss, v4f32>; + int_x86_sse_max_ss>; def Int_MAXSSrm : SS_Intrm<0x5F, "maxss {$src2, $dst|$dst, $src2}", - int_x86_sse_max_ss, v4f32>; + int_x86_sse_max_ss>; def Int_MAXSDrr : SD_Intrr<0x5F, "maxsd {$src2, $dst|$dst, $src2}", - int_x86_sse2_max_sd, v2f64>; + int_x86_sse2_max_sd>; def Int_MAXSDrm : SD_Intrm<0x5F, "maxsd {$src2, $dst|$dst, $src2}", - int_x86_sse2_max_sd, v2f64>; + int_x86_sse2_max_sd>; def Int_MINSSrr : SS_Intrr<0x5D, "minss {$src2, $dst|$dst, $src2}", - int_x86_sse_min_ss, v4f32>; + int_x86_sse_min_ss>; def Int_MINSSrm : SS_Intrm<0x5D, "minss {$src2, $dst|$dst, $src2}", - int_x86_sse_min_ss, v4f32>; + int_x86_sse_min_ss>; def Int_MINSDrr : SD_Intrr<0x5D, "minsd {$src2, $dst|$dst, $src2}", - int_x86_sse2_min_sd, v2f64>; + int_x86_sse2_min_sd>; def Int_MINSDrm : SD_Intrm<0x5D, "minsd {$src2, $dst|$dst, $src2}", - int_x86_sse2_min_sd, v2f64>; + int_x86_sse2_min_sd>; } // Conversion instructions From lattner at cs.uiuc.edu Mon Apr 3 19:25:23 2006 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Mon, 3 Apr 2006 19:25:23 -0500 Subject: [llvm-commits] CVS: llvm/include/llvm/Target/TargetLowering.h Message-ID: <200604040025.TAA32573@zion.cs.uiuc.edu> Changes in directory llvm/include/llvm/Target: TargetLowering.h updated: 1.65 -> 1.66 --- Log message: Allow targets to have fine grained control over which types various ops get promoted to, if they desire. --- Diffs of the changes: (+29 -5) TargetLowering.h | 34 +++++++++++++++++++++++++++++----- 1 files changed, 29 insertions(+), 5 deletions(-) Index: llvm/include/llvm/Target/TargetLowering.h diff -u llvm/include/llvm/Target/TargetLowering.h:1.65 llvm/include/llvm/Target/TargetLowering.h:1.66 --- llvm/include/llvm/Target/TargetLowering.h:1.65 Thu Mar 30 18:46:26 2006 +++ llvm/include/llvm/Target/TargetLowering.h Mon Apr 3 19:25:10 2006 @@ -24,9 +24,7 @@ #include "llvm/Type.h" #include "llvm/CodeGen/SelectionDAGNodes.h" -#include "llvm/CodeGen/ValueTypes.h" -#include "llvm/Support/DataTypes.h" -#include +#include namespace llvm { class Value; @@ -172,7 +170,7 @@ MVT::ValueType getTypeToTransformTo(MVT::ValueType VT) const { return TransformToType[VT]; } - + /// getPackedTypeBreakdown - Packed types are broken down into some number of /// legal scalar types. For example, <8 x float> maps to 2 MVT::v2f32 values /// with Altivec or SSE1, or 8 promoted MVT::f64 values with the X86 FP stack. @@ -223,6 +221,16 @@ MVT::ValueType getTypeToPromoteTo(unsigned Op, MVT::ValueType VT) const { assert(getOperationAction(Op, VT) == Promote && "This operation isn't promoted!"); + + // See if this has an explicit type specified. + std::map, + MVT::ValueType>::const_iterator PTTI = + PromoteToType.find(std::make_pair(Op, VT)); + if (PTTI != PromoteToType.end()) return PTTI->second; + + assert((MVT::isInteger(VT) || MVT::isFloatingPoint(VT)) && + "Cannot autopromote this type, add it with AddPromotedToType."); + MVT::ValueType NVT = VT; do { NVT = (MVT::ValueType)(NVT+1); @@ -484,6 +492,15 @@ OpActions[Op] &= ~(3ULL << VT*2); OpActions[Op] |= (uint64_t)Action << VT*2; } + + /// AddPromotedToType - If Opc/OrigVT is specified as being promoted, the + /// promotion code defaults to trying a larger integer/fp until it can find + /// one that works. If that default is insufficient, this method can be used + /// by the target to override the default. + void AddPromotedToType(unsigned Opc, MVT::ValueType OrigVT, + MVT::ValueType DestVT) { + PromoteToType[std::make_pair(Opc, OrigVT)] = DestVT; + } /// addLegalFPImmediate - Indicate that this target can instruction select /// the specified FP immediate natively. @@ -629,7 +646,6 @@ private: std::vector LegalAddressScales; -private: TargetMachine &TM; const TargetData &TD; @@ -715,6 +731,14 @@ /// which sets a bit in this array. unsigned char TargetDAGCombineArray[156/(sizeof(unsigned char)*8)]; + /// PromoteToType - For operations that must be promoted to a specific type, + /// this holds the destination type. This map should be sparse, so don't hold + /// it as an array. + /// + /// Targets add entries to this map with AddPromotedToType(..), clients access + /// this with getTypeToPromoteTo(..). + std::map, MVT::ValueType> PromoteToType; + protected: /// When lowering %llvm.memset this field specifies the maximum number of /// store operations that may be substituted for the call to memset. Targets From llvm at cs.uiuc.edu Mon Apr 3 19:43:03 2006 From: llvm at cs.uiuc.edu (LLVM) Date: Mon, 3 Apr 2006 19:43:03 -0500 Subject: [llvm-commits] CVS: llvm-test/SingleSource/UnitTests/Vector/SSE/ Message-ID: <200604040043.TAA32755@zion.cs.uiuc.edu> Changes in directory llvm-test/SingleSource/UnitTests/Vector/SSE: --- Log message: Directory /var/cvs/llvm/llvm-test/SingleSource/UnitTests/Vector/SSE added to the repository --- Diffs of the changes: (+0 -0) 0 files changed From evan.cheng at apple.com Mon Apr 3 19:48:08 2006 From: evan.cheng at apple.com (Evan Cheng) Date: Mon, 3 Apr 2006 19:48:08 -0500 Subject: [llvm-commits] CVS: llvm-test/SingleSource/UnitTests/Vector/Makefile Message-ID: <200604040048.TAA00331@zion.cs.uiuc.edu> Changes in directory llvm-test/SingleSource/UnitTests/Vector: Makefile updated: 1.2 -> 1.3 --- Log message: Added some Altivec and SSE examples from: Introduction to Parallel Computing A practical guide with examples in C Oxford Texts in Applied and Engineering Mathematics No. 9 Oxford University Press, February 2004 ISBN: 0-19-851576-6 (hardback), 0-19-851577-4 (paperback) http://people.inf.ethz.ch/arbenz/book/ --- Diffs of the changes: (+4 -0) Makefile | 4 ++++ 1 files changed, 4 insertions(+) Index: llvm-test/SingleSource/UnitTests/Vector/Makefile diff -u llvm-test/SingleSource/UnitTests/Vector/Makefile:1.2 llvm-test/SingleSource/UnitTests/Vector/Makefile:1.3 --- llvm-test/SingleSource/UnitTests/Vector/Makefile:1.2 Sun Mar 26 23:54:42 2006 +++ llvm-test/SingleSource/UnitTests/Vector/Makefile Mon Apr 3 19:47:54 2006 @@ -9,6 +9,10 @@ DIRS += Altivec endif +ifeq ($(ARCH),x86) +DIRS += SSE +endif + include $(LEVEL)/SingleSource/Makefile.singlesrc From evan.cheng at apple.com Mon Apr 3 19:48:09 2006 From: evan.cheng at apple.com (Evan Cheng) Date: Mon, 3 Apr 2006 19:48:09 -0500 Subject: [llvm-commits] CVS: llvm-test/SingleSource/UnitTests/Vector/Altivec/alti.expandfft.c alti.isamax.c alti.sdot.c alti.stepfft.c Message-ID: <200604040048.TAA00343@zion.cs.uiuc.edu> Changes in directory llvm-test/SingleSource/UnitTests/Vector/Altivec: alti.expandfft.c added (r1.1) alti.isamax.c added (r1.1) alti.sdot.c added (r1.1) alti.stepfft.c added (r1.1) --- Log message: Added some Altivec and SSE examples from: Introduction to Parallel Computing A practical guide with examples in C Oxford Texts in Applied and Engineering Mathematics No. 9 Oxford University Press, February 2004 ISBN: 0-19-851576-6 (hardback), 0-19-851577-4 (paperback) http://people.inf.ethz.ch/arbenz/book/ --- Diffs of the changes: (+725 -0) alti.expandfft.c | 287 +++++++++++++++++++++++++++++++++++++++++++++++++++++++ alti.isamax.c | 131 +++++++++++++++++++++++++ alti.sdot.c | 103 +++++++++++++++++++ alti.stepfft.c | 204 +++++++++++++++++++++++++++++++++++++++ 4 files changed, 725 insertions(+) Index: llvm-test/SingleSource/UnitTests/Vector/Altivec/alti.expandfft.c diff -c /dev/null llvm-test/SingleSource/UnitTests/Vector/Altivec/alti.expandfft.c:1.1 *** /dev/null Mon Apr 3 19:48:04 2006 --- llvm-test/SingleSource/UnitTests/Vector/Altivec/alti.expandfft.c Mon Apr 3 19:47:54 2006 *************** *** 0 **** --- 1,287 ---- + #include + #include + #include + #include + #define N 1048576 + #define N2 N/2 + main() + { + /* + Example of Apple Altivec coded binary radix FFT + using intrinsics from Petersen and Arbenz "Intro. + to Parallel Computing," Section 3.6 + + This is an expanded version of a generic work-space + FFT: steps are in-line. cfft2(n,x,y,w,sign) takes complex + n-array "x" (Fortran real,aimag,real,aimag,... order) + and writes its DFT in "y". Both input "x" and the + original contents of "y" are destroyed. Initialization + for array "w" (size n/2 complex of twiddle factors + (exp(twopi*i*k/n), for k=0..n/2-1)) is computed once + by cffti(n,w). + + WPP, SAM. Math. ETHZ, 1 June, 2002 + */ + + int first,i,icase,it,ln2,n; + int nits=1000000; + static float seed = 331.0; + float error,fnm1,sign,z0,z1,ggl(); + float *x,*y,*z,*w; + double t1,mflops; + void cffti(),cfft2(); + /* allocate storage for x,y,z,w on 4-word bndr. */ + x = (float *) malloc(8*N); + y = (float *) malloc(8*N); + z = (float *) malloc(8*N); + w = (float *) malloc(4*N); + n = 2; + for(ln2=1;ln2<21;ln2++){ + first = 1; + for(icase=0;icase<2;icase++){ + if(first){ + for(i=0;i<2*n;i+=2){ + z0 = ggl(&seed); /* real part of array */ + z1 = ggl(&seed); /* imaginary part of array */ + x[i] = z0; + z[i] = z0; /* copy of initial real data */ + x[i+1] = z1; + z[i+1] = z1; /* copy of initial imag. data */ + } + } else { + for(i=0;i<2*n;i+=2){ + z0 = 0; /* real part of array */ + z1 = 0; /* imaginary part of array */ + x[i] = z0; + z[i] = z0; /* copy of initial real data */ + x[i+1] = z1; + z[i+1] = z1; /* copy of initial imag. data */ + } + } + /* initialize sine/cosine tables */ + cffti(n,w); + /* transform forward, back */ + if(first){ + sign = 1.0; + cfft2(n,x,y,w,sign); + sign = -1.0; + cfft2(n,y,x,w,sign); + /* results should be same as initial multiplied by n */ + fnm1 = 1.0/((float) n); + error = 0.0; + for(i=0;i<2*n;i+=2){ + error += (z[i] - fnm1*x[i])*(z[i] - fnm1*x[i]) + + (z[i+1] - fnm1*x[i+1])*(z[i+1] - fnm1*x[i+1]); + } + error = sqrt(fnm1*error); + printf(" for n=%d, fwd/bck error=%e\n",n,error); + first = 0; + } else { + t1 = ((double)clock())/((double) CLOCKS_PER_SEC); + for(it=0;it y */ + for(j=0;j + float ggl(float *ds) + { + + /* generate u(0,1) distributed random numbers. + Seed ds must be saved between calls. ggl is + essentially the same as the IMSL routine RNUM. + + W. Petersen and M. Troyer, 24 Oct. 2002, ETHZ: + a modification of a fortran version from + I. Vattulainen, Tampere Univ. of Technology, + Finland, 1992 */ + + double t,d2=0.2147483647e10; + t = (float) *ds; + t = fmod(0.16807e5*t,d2); + *ds = (float) t; + return((float) ((t-1.0e0)/(d2-1.0e0))); + } Index: llvm-test/SingleSource/UnitTests/Vector/Altivec/alti.isamax.c diff -c /dev/null llvm-test/SingleSource/UnitTests/Vector/Altivec/alti.isamax.c:1.1 *** /dev/null Mon Apr 3 19:48:09 2006 --- llvm-test/SingleSource/UnitTests/Vector/Altivec/alti.isamax.c Mon Apr 3 19:47:54 2006 *************** *** 0 **** --- 1,131 ---- + #include + #include + #include + #define N 1027 + main() + { + /* + Mac G-4 unit step isamax for arbitrary N code + This is an Altivec version of isamax0 from Section 3.5.7 + in Arbenz and Petersen, "Intro. to Parallel Computing" + Oxford Univ. Press, 2004 + wpp 5/8/2002 + */ + float x[N]; + float xb; + int err,flag,i,im,k,ki,kl,ib,n0,n; + int isamax(int,float *); + static float seed = 331.0; + float ggl(float*); + flag = 0; // error flag + kl = 3; + n0 = 1; + for(k=0;k<5;k++){ + for(ki=0;ki xb){ + xb = fabs(x[i]); + ib = i; + } + } + im = isamax(n,x); + err = ib - im; + if(err != 0){ + printf(" err in isamax: n = %d, ib = %d, im = %d\n",n,ib,im); + flag = 1; + } + } + n0 *= 4; // increase n + kl = 4; // for n > 1, 3 steps of increase in n + } + if(flag==0) printf(" All n tests pass\n"); + } + #define NS 12 + int isamax(int n, float *x) + { + float rbig,*xp; + int i,ii,nres,nsegs,ibig,irbig; + vector float V0,V1,V6; + vector bool int V3; + vector float V2 = (vector float) (0.0,1.0,2.0,3.0); + vector float V7 = (vector float) (0.0,1.0,2.0,3.0); + const vector float incr_4 = (vector float) (4.0,4.0,4.0,4.0); + const vector float minus0 = (vector float) (-0.0,-0.0,-0.0,-0.0); + float big,xbig[4],indx[4]; + // n < NS done in scalar mode + if(n < NS){ + ibig = 0; + rbig = 0.0; + for(i=0;i rbig){ + rbig = fabs(x[i]); + ibig = i; + } + } + return(ibig); + } + // n >= NS case done with altivec + nsegs = (n >> 2) - 1; + nres = n - ((nsegs+1) << 2); // nres = n mod 4 + V2 = vec_add(V2,incr_4); // increment next index + xp = x; + V0 = vec_ld(0,xp); xp += 4; // first four + V1 = vec_ld(0,xp); xp += 4; // next four + V0 = vec_abs(V0); // absolute value of first four + for(i=0;i> 2) << 2); + big = 0.0; + ibig = 0.0; + for(i=0;i big){ + big = fabs(x[ii]); + ibig = ii; + } + ii++; + } + for(i=0;i<4;i++){ + if(xbig[i] > big){ + big = xbig[i]; + ibig = (int) indx[i]; + } + } + return(ibig); + } + #undef NS + #include + float ggl(float *ds) + { + + /* generate u(0,1) distributed random numbers. + Seed ds must be saved between calls. ggl is + essentially the same as the IMSL routine RNUM. + + W. Petersen and M. Troyer, 24 Oct. 2002, ETHZ: + a modification of a fortran version from + I. Vattulainen, Tampere Univ. of Technology, + Finland, 1992 */ + + double t,d2=0.2147483647e10; + t = (float) *ds; + t = fmod(0.16807e5*t,d2); + *ds = (float) t; + return((float) ((t-1.0e0)/(d2-1.0e0))); + } + Index: llvm-test/SingleSource/UnitTests/Vector/Altivec/alti.sdot.c diff -c /dev/null llvm-test/SingleSource/UnitTests/Vector/Altivec/alti.sdot.c:1.1 *** /dev/null Mon Apr 3 19:48:09 2006 --- llvm-test/SingleSource/UnitTests/Vector/Altivec/alti.sdot.c Mon Apr 3 19:47:54 2006 *************** *** 0 **** --- 1,103 ---- + #include + #include + #include + #define N 1027 + main() + { + /* Mac G-4 sdot for arbitrary N wpp 6/8/2002 */ + float x[N],y[N],tres,res,eps; + int flag,i,k,ki,kl,n0,n; + static float seed = 331.0; + float sdot(int,float *,float *); + float ggl(float *); + eps = FLT_EPSILON; /* machine eps */ + n0 = 1; kl = 3; + flag = 0; + for(k=0;k<5;k++){ + for(ki=0;ki ((float) n)*eps){ + flag = 1; + printf(" n = %d, test sdot value = %e, sdot value = %e\n", + n,tres,res); + } + } + n0 *= 4; + kl = 4; + } + if(flag == 0) printf(" All n tests passed\n"); + } + #define NS 12 + float sdot(int n, float *x, float *y) + { + float sum,*xp,*yp; + int i,ii,nres,nsegs; + vector float V7 = (vector float)(0.0,0.0,0.0,0.0); + vector float V0,V1; + float psum[4]; + // n < NS done in scalar mode + if(n < NS){ + sum = x[0]*y[0]; + for(i=1;i= NS case done with altivec + xp = x; + yp = y; + V0 = vec_ld(0,xp); xp += 4; // increment next index + V1 = vec_ld(0,yp); yp += 4; // increment next index + nsegs = (n >> 2) - 1; + nres = n - ((nsegs+1) << 2); // nres = n mod 4 + for(i=0;i 0){ + ii = ((n >> 2) << 2); + sum = x[ii]*y[ii]; + ii++; + for(i=1;i + float ggl(float *ds) + { + + /* generate u(0,1) distributed random numbers. + Seed ds must be saved between calls. ggl is + essentially the same as the IMSL routine RNUM. + + W. Petersen and M. Troyer, 24 Oct. 2002, ETHZ: + a modification of a fortran version from + I. Vattulainen, Tampere Univ. of Technology, + Finland, 1992 */ + + double t,d2=0.2147483647e10; + t = (float) *ds; + t = fmod(0.16807e5*t,d2); + *ds = (float) t; + return((float) ((t-1.0e0)/(d2-1.0e0))); + } Index: llvm-test/SingleSource/UnitTests/Vector/Altivec/alti.stepfft.c diff -c /dev/null llvm-test/SingleSource/UnitTests/Vector/Altivec/alti.stepfft.c:1.1 *** /dev/null Mon Apr 3 19:48:09 2006 --- llvm-test/SingleSource/UnitTests/Vector/Altivec/alti.stepfft.c Mon Apr 3 19:47:54 2006 *************** *** 0 **** --- 1,204 ---- + #include + #include + #include + #include + #define N 128 + #define N2 N/2 + main() + { + /* SSE version of cfft2 - uses Apple intrinsics + W. Petersen, SAM. Math. ETHZ 2 May, 2002 */ + int first,i,icase,it,n; + int nits=1000; /* number of iterations for timing test */ + float error,fnm1,sign,z0,z1,ggl(); + static float seed = 331.0; + float *x,*y,*z,*w; + float t1,ln2,mflops; + void cffti(),cfft2(); + /* allocate storage for x,y,z,w on 4-word bndr. */ + x = (float *)malloc(8*N); + y = (float *)malloc(8*N); + z = (float *)malloc(8*N); + w = (float *)malloc(4*N); + first = 1; + for(icase=0;icase<2;icase++){ + if(first){ + for(i=0;i<2*N;i+=2){ + z0 = ggl(&seed); /* real part of array */ + z1 = ggl(&seed); /* imaginary part of array */ + x[i] = z0; + z[i] = z0; /* copy of initial real data */ + x[i+1] = z1; + z[i+1] = z1; /* copy of initial imag. data */ + } + } else { + for(i=0;i<2*N;i+=2){ + z0 = 0; /* real part of array */ + z1 = 0; /* imaginary part of array */ + x[i] = z0; + z[i] = z0; /* copy of initial real data */ + x[i+1] = z1; + z[i+1] = z1; /* copy of initial imag. data */ + } + } + /* initialize sine/cosine tables */ + n = N; + cffti(n,w); + /* transform forward, back */ + if(first){ + sign = 1.0; + cfft2(n,x,y,w,sign); + sign = -1.0; + cfft2(n,y,x,w,sign); + /* results should be same as initial multiplied by N */ + fnm1 = 1.0/((float) n); + error = 0.0; + for(i=0;i<2*N;i+=2){ + error += (z[i] - fnm1*x[i])*(z[i] - fnm1*x[i]) + + (z[i+1] - fnm1*x[i+1])*(z[i+1] - fnm1*x[i+1]); + } + error = sqrt(fnm1*error); + printf(" for n=%d, fwd/bck error=%e\n",N,error); + first = 0; + } else { + t1 = ((float)clock())/((float) CLOCKS_PER_SEC); + for(it=0;it=2 case */ + wr[0] = rp; wr[1] = rp; wr[2] = rp; wr[3] = rp; + wu[0] = up; wu[1] = up; wu[2] = up; wu[3] = up; + v6 = vec_ld(0,wr); + v7 = vec_ld(0,wu); + v7 = vec_xor(v7,vminus); + for(k=0; k + float ggl(float *ds) + { + + /* generate u(0,1) distributed random numbers. + Seed ds must be saved between calls. ggl is + essentially the same as the IMSL routine RNUM. + + W. Petersen and M. Troyer, 24 Oct. 2002, ETHZ: + a modification of a fortran version from + I. Vattulainen, Tampere Univ. of Technology, + Finland, 1992 */ + + double t,d2=0.2147483647e10; + t = (float) *ds; + t = fmod(0.16807e5*t,d2); + *ds = (float) t; + return((float) ((t-1.0e0)/(d2-1.0e0))); + } From evan.cheng at apple.com Mon Apr 3 19:48:08 2006 From: evan.cheng at apple.com (Evan Cheng) Date: Mon, 3 Apr 2006 19:48:08 -0500 Subject: [llvm-commits] CVS: llvm-test/SingleSource/UnitTests/Vector/SSE/Makefile sse.expandfft.c sse.isamax.c sse.stepfft.c Message-ID: <200604040048.TAA00329@zion.cs.uiuc.edu> Changes in directory llvm-test/SingleSource/UnitTests/Vector/SSE: Makefile added (r1.1) sse.expandfft.c added (r1.1) sse.isamax.c added (r1.1) sse.stepfft.c added (r1.1) --- Log message: Added some Altivec and SSE examples from: Introduction to Parallel Computing A practical guide with examples in C Oxford Texts in Applied and Engineering Mathematics No. 9 Oxford University Press, February 2004 ISBN: 0-19-851576-6 (hardback), 0-19-851577-4 (paperback) http://people.inf.ethz.ch/arbenz/book/ --- Diffs of the changes: (+585 -0) Makefile | 8 + sse.expandfft.c | 263 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++ sse.isamax.c | 119 +++++++++++++++++++++++++ sse.stepfft.c | 195 +++++++++++++++++++++++++++++++++++++++++ 4 files changed, 585 insertions(+) Index: llvm-test/SingleSource/UnitTests/Vector/SSE/Makefile diff -c /dev/null llvm-test/SingleSource/UnitTests/Vector/SSE/Makefile:1.1 *** /dev/null Mon Apr 3 19:48:04 2006 --- llvm-test/SingleSource/UnitTests/Vector/SSE/Makefile Mon Apr 3 19:47:54 2006 *************** *** 0 **** --- 1,8 ---- + # SingleSource/UnitTests/Vector/SSE/Makefile + + DIRS = + LEVEL = ../../../.. + include $(LEVEL)/SingleSource/Makefile.singlesrc + + TARGET_CFLAGS += -msse3 + LCCFLAGS += -msse3 Index: llvm-test/SingleSource/UnitTests/Vector/SSE/sse.expandfft.c diff -c /dev/null llvm-test/SingleSource/UnitTests/Vector/SSE/sse.expandfft.c:1.1 *** /dev/null Mon Apr 3 19:48:08 2006 --- llvm-test/SingleSource/UnitTests/Vector/SSE/sse.expandfft.c Mon Apr 3 19:47:54 2006 *************** *** 0 **** --- 1,263 ---- + #include + #include + #include + #include + #include "xmmintrin.h" + #define N 256 + #define N2 N/2 + main() + { + /* + SSE version of cfft2 - uses Intel intrinsics. + Expanded version + + wpp, SAM. Math. ETHZ 21 May, 2002 + */ + int first,i,icase,it,n; + float error,fnm1,seed,sign,z0,z1,ggl(); + float *x,*y,*z,*w; + float t1,ln2,mflops; + void cffti(),cfft2(); + /* allocate storage for x,y,z,w on 4-word bndr. */ + x = (float *)_mm_malloc(8*N, 16); + y = (float *)_mm_malloc(8*N, 16); + z = (float *)_mm_malloc(8*N, 16); + w = (float *)_mm_malloc(4*N, 16); + first = 1; + seed = 331.0; + for(icase=0;icase<2;icase++){ + if(first){ + for(i=0;i<2*N;i+=2){ + z0 = ggl(&seed); /* real part of array */ + z1 = ggl(&seed); /* imaginary part of array */ + x[i] = z0; + z[i] = z0; /* copy of initial real data */ + x[i+1] = z1; + z[i+1] = z1; /* copy of initial imag. data */ + } + } else { + for(i=0;i<2*N;i+=2){ + z0 = 0; /* real part of array */ + z1 = 0; /* imaginary part of array */ + x[i] = z0; + z[i] = z0; /* copy of initial real data */ + x[i+1] = z1; + z[i+1] = z1; /* copy of initial imag. data */ + } + } + /* initialize sine/cosine tables */ + n = N; + cffti(n,w); + /* transform forward, back */ + if(first){ + sign = 1.0; + cfft2(n,x,y,w,sign); + sign = -1.0; + cfft2(n,y,x,w,sign); + /* results should be same as initial multiplied by N */ + fnm1 = 1.0/((float) n); + error = 0.0; + for(i=0;i<2*N;i+=2){ + error += (z[i] - fnm1*x[i])*(z[i] - fnm1*x[i]) + + (z[i+1] - fnm1*x[i+1])*(z[i+1] - fnm1*x[i+1]); + } + error = sqrt(fnm1*error); + printf(" for n=%d, fwd/bck error=%e\n",N,error); + first = 0; + } else { + t1 = ((float)clock())/((float) CLOCKS_PER_SEC); + for(it=0;it<1000;it++){ + sign = +1.0; + cfft2(n,x,y,w,sign); + sign = -1.0; + cfft2(n,y,x,w,sign); + } + t1 = ((float)clock())/((float) CLOCKS_PER_SEC) - t1; + t1 = t1/2000.0; + ln2 = 10.0; // reset this for different N + mflops = 5.0*((float) N)*ln2/((1.e+6)*t1); + printf(" for n=%d, t1=%e, mflops=%e\n",n,t1,mflops); + } + } + } + void cfft2(n,x,y,w,sign) + int n; + float x[][2],y[][2],w[][2],sign; + { + int jb, jc, jw, k, k2, lj, m, j, mj, mj2, pass, tgle; + float (*a)[2],(*b)[2],(*c)[2],(*d)[2]; + float (*aa)[2],(*bb)[2],(*cb)[2],(*dd)[2]; + float rp,up,wr[4],wu[4]; + __m128 V0,V1,V2,V3,V4,V5,V6,V7; + __m128 V8,V9,V10,V11,V12,V13,V14,V15; + + if(n<=1){ + y[0][0] = x[0][0]; + y[0][1] = x[0][1]; + return; + } + m = (int) (log((float) n)/log(1.99)); + mj = 1; + mj2 = 2; + lj = n/2; + // first pass thru data: x -> y + a = (void *)&x[0][0]; + b = (void *)&x[n/2][0]; + c = (void *)&y[0][0]; + d = (void *)&y[1][0]; + for(j=0;j + float ggl(float *ds) + { + /* generate u(0,1) distributed random numbers. + Seed ds must be saved between calls. ggl is + essentially the same as the IMSL routine RNUM. + + W. Petersen and M. Troyer, 24 Oct. 2002, ETHZ: + a modification of a fortran version from + I. Vattulainen, Tampere Univ. of Technology, + Finland, 1992 */ + + double t,d2=0.2147483647e10; + t = (float) *ds; + t = fmod(0.16807e5*t,d2); + *ds = (float) t; + return((float) ((t-1.0e0)/(d2-1.0e0))); + } + Index: llvm-test/SingleSource/UnitTests/Vector/SSE/sse.isamax.c diff -c /dev/null llvm-test/SingleSource/UnitTests/Vector/SSE/sse.isamax.c:1.1 *** /dev/null Mon Apr 3 19:48:08 2006 --- llvm-test/SingleSource/UnitTests/Vector/SSE/sse.isamax.c Mon Apr 3 19:47:54 2006 *************** *** 0 **** --- 1,119 ---- + #include + #include + #include + #include "xmmintrin.h" + #define N 20 + main() + { + /* + SSE unit step isamax with alignment code. From Section + 3.5.7 of Petersen and Arbenz "Intro. to Parallel Computing," + Oxford Univ. Press, 2004. + + wpp 31/7/2002 + */ + float x[N]; + int i,im; + int isamax0(int,float *); + for(i=0;i bbig){ + bbig = fabs(x[i]); + iebig = i; + } + } + return(iebig); + } + // n >= NS case done in SSE mode + V7 = _mm_set_ps(3.0,2.0,1.0,0.0); + V2 = _mm_set_ps(3.0,2.0,1.0,0.0); + V6 = _mm_set_ps1(-0.0); + offset4 = _mm_set_ps1(4.0); + align = ((unsigned int) x >> 2) & 0x03; + if(align == 1){ // bres = 3 case + bbig = fabsf(x[0]); ibbig = 0; + bres = 3.0; nn = n - 3; + for(i=1;i<3;i++){ + if(fabsf(x[i]) > bbig){ + bbig = fabsf(x[i]); ibbig = i; + } + } + } else if(align == 2){ // bres = 2 case + bbig = fabsf(x[0]); ibbig = 0; + bres = 2.0; nn = n - 2; + if(fabsf(x[1]) > bbig){ + bbig = fabsf(x[1]); ibbig = 1; + } + } else if(align == 1){ // bres = 1 case + bbig = fabsf(x[0]); ibbig = 0; + bres = 1.0; nn = n - 1; + } else { // bres = 0 case + bbig = 0.0; ibbig = 0; nn = n; + bres = 0.0; + } + xp = x + (int) bres; + nsegs = (nn >> 2) - 2; + eres = nn - 4*(nsegs+2); + V0 = _mm_load_ps(xp); xp += 4; // first four in 4/time seq. + V1 = _mm_load_ps(xp); xp += 4; // next four in 4/time seq. + V0 = _mm_andnot_ps(V6,V0); // take absolute value + for(i=0;i 0){ + V0 = _mm_max_ps(V0,V1); + V3 = _mm_and_ps(V2,V3); + V7 = _mm_max_ps(V7,V3); + } + V1 = _mm_load_ps(xp); xp += 4; // bottom load next four + } + // finish up the last segment of 4 + V1 = _mm_andnot_ps(V6,V1); // take absolute value + V3 = _mm_cmpnle_ps(V1,V0); // compare old max of 4 to new + mb = _mm_movemask_ps(V3); // any of 4 bigger? + V2 = _mm_add_ps(V2,offset4); // add offset + if(mb > 0){ + V0 = _mm_max_ps(V0,V1); + V3 = _mm_and_ps(V2,V3); + V7 = _mm_max_ps(V7,V3); + } + // Now finish up: segment maxima are in V0, indices in V7 + _mm_store_ps(xbig,V0); + _mm_store_ps(indx,V7); + if(eres>0){ + for(i=0;i ebig){ + ebig = xbig[i]; + iebig = (int) indx[i]; + } + } + return(iebig); + } + #undef NS Index: llvm-test/SingleSource/UnitTests/Vector/SSE/sse.stepfft.c diff -c /dev/null llvm-test/SingleSource/UnitTests/Vector/SSE/sse.stepfft.c:1.1 *** /dev/null Mon Apr 3 19:48:08 2006 --- llvm-test/SingleSource/UnitTests/Vector/SSE/sse.stepfft.c Mon Apr 3 19:47:54 2006 *************** *** 0 **** --- 1,195 ---- + #include + #include + #include + #include + #include "xmmintrin.h" + #define N 1024 + #define N2 N/2 + main() + { + /* + SSE version of cfft2 - uses INTEL intrinsics + W. Petersen, SAM. Math. ETHZ 2 May, 2002 + */ + int first,i,icase,it,n; + float seed,error,fnm1,sign,z0,z1,ggl(); + float *x,*y,*z,*w; + float t1,ln2,mflops; + void cffti(),cfft2(); + /* allocate storage for x,y,z,w on 4-word bndr. */ + x = (float *)_mm_malloc(8*N, 16); + y = (float *)_mm_malloc(8*N, 16); + z = (float *)_mm_malloc(8*N, 16); + w = (float *)_mm_malloc(4*N, 16); + first = 1; + seed = 331.0; + for(icase=0;icase<2;icase++){ + if(first){ + for(i=0;i<2*N;i+=2){ + z0 = ggl(&seed); /* real part of array */ + z1 = ggl(&seed); /* imaginary part of array */ + x[i] = z0; + z[i] = z0; /* copy of initial real data */ + x[i+1] = z1; + z[i+1] = z1; /* copy of initial imag. data */ + } + } else { + for(i=0;i<2*N;i+=2){ + z0 = 0; /* real part of array */ + z1 = 0; /* imaginary part of array */ + x[i] = z0; + z[i] = z0; /* copy of initial real data */ + x[i+1] = z1; + z[i+1] = z1; /* copy of initial imag. data */ + } + } + /* initialize sine/cosine tables */ + n = N; + cffti(n,w); + /* transform forward, back */ + if(first){ + sign = 1.0; + cfft2(n,x,y,w,sign); + sign = -1.0; + cfft2(n,y,x,w,sign); + /* results should be same as initial multiplied by N */ + fnm1 = 1.0/((float) n); + error = 0.0; + for(i=0;i<2*N;i+=2){ + error += (z[i] - fnm1*x[i])*(z[i] - fnm1*x[i]) + + (z[i+1] - fnm1*x[i+1])*(z[i+1] - fnm1*x[i+1]); + } + error = sqrt(fnm1*error); + printf(" for n=%d, fwd/bck error=%e\n",N,error); + first = 0; + } else { + t1 = ((float)clock())/((float) CLOCKS_PER_SEC); + for(it=0;it<10000;it++){ + sign = +1.0; + cfft2(n,x,y,w,sign); + sign = -1.0; + cfft2(n,y,x,w,sign); + } + t1 = ((float)clock())/((float) CLOCKS_PER_SEC) - t1; + t1 = t1/20000.0; + ln2 = 10.0; /* reset this for different N */ + mflops = 5.0*((float) N)*ln2/((1.e+6)*t1); + printf(" for n=%d, t1=%e, mflops=%e\n",n,t1,mflops); + } + } + } + void cfft2(n,x,y,w,sign) + int n; + float x[][2],y[][2],w[][2],sign; + { + int jb, m, j, mj, tgle; + void ccopy(),step(); + m = (int) (log((float) n)/log(1.99)); + mj = 1; + tgle = 1; /* toggling switch for work array */ + step(n,mj,&x[0][0],&x[n/2][0],&y[0][0],&y[mj][0],w,sign); + for(j=0;j + float ggl(float *ds) + { + + /* generate u(0,1) distributed random numbers. + Seed ds must be saved between calls. ggl is + essentially the same as the IMSL routine RNUM. + + W. Petersen and M. Troyer, 24 Oct. 2002, ETHZ: + a modification of a fortran version from + I. Vattulainen, Tampere Univ. of Technology, + Finland, 1992 */ + + double t,d2=0.2147483647e10; + t = (float) *ds; + t = fmod(0.16807e5*t,d2); + *ds = (float) t; + return((float) ((t-1.0e0)/(d2-1.0e0))); + } + void step(n,mj,a,b,c,d,w,sign) + int n, mj; + float a[][2],b[][2],c[][2],d[][2],w[][2],sign; + { + int j,k,jc,jw,l,lj,mj2,mseg; + float rp,up,wr[4],wu[4]; + __m128 xmm0,xmm1,xmm2,xmm3,xmm4,xmm5,xmm6,xmm7; + + mj2 = 2*mj; + lj = n/mj2; + + for(j=0; j=2 case */ + /* _mm_prefetch((char *)&a[jw][0],_MM_HINT_NTA); */ + /* _mm_prefetch((char *)&b[jw][0],_MM_HINT_NTA); */ + wr[0] = rp; wr[1] = rp; wr[2] = rp; wr[3] = rp; + wu[0] = -up; wu[1] = up; wu[2] = -up; wu[3] = up; + xmm6 = _mm_load_ps(wr); + xmm7 = _mm_load_ps(wu); + for(k=0; k Changes in directory llvm/lib/CodeGen/SelectionDAG: SelectionDAG.cpp updated: 1.295 -> 1.296 --- Log message: Constant fold bitconvert(undef) --- Diffs of the changes: (+2 -0) SelectionDAG.cpp | 2 ++ 1 files changed, 2 insertions(+) Index: llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp diff -u llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp:1.295 llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp:1.296 --- llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp:1.295 Sat Apr 1 20:51:27 2006 +++ llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp Mon Apr 3 20:02:22 2006 @@ -1167,6 +1167,8 @@ if (VT == Operand.getValueType()) return Operand; // noop conversion. if (OpOpcode == ISD::BIT_CONVERT) // bitconv(bitconv(x)) -> bitconv(x) return getNode(ISD::BIT_CONVERT, VT, Operand.getOperand(0)); + if (OpOpcode == ISD::UNDEF) + return getNode(ISD::UNDEF, VT); break; case ISD::SCALAR_TO_VECTOR: assert(MVT::isVector(VT) && !MVT::isVector(Operand.getValueType()) && From lattner at cs.uiuc.edu Mon Apr 3 20:40:19 2006 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Mon, 3 Apr 2006 20:40:19 -0500 Subject: [llvm-commits] CVS: llvm/include/llvm/IntrinsicsPowerPC.td Message-ID: <200604040140.UAA00975@zion.cs.uiuc.edu> Changes in directory llvm/include/llvm: IntrinsicsPowerPC.td updated: 1.13 -> 1.14 --- Log message: Fix the types for these intrinsics. --- Diffs of the changes: (+6 -6) IntrinsicsPowerPC.td | 12 ++++++------ 1 files changed, 6 insertions(+), 6 deletions(-) Index: llvm/include/llvm/IntrinsicsPowerPC.td diff -u llvm/include/llvm/IntrinsicsPowerPC.td:1.13 llvm/include/llvm/IntrinsicsPowerPC.td:1.14 --- llvm/include/llvm/IntrinsicsPowerPC.td:1.13 Mon Apr 3 12:20:06 2006 +++ llvm/include/llvm/IntrinsicsPowerPC.td Mon Apr 3 20:40:06 2006 @@ -122,23 +122,23 @@ [InstrNoMem]>; def int_ppc_altivec_vcmpequh : GCCBuiltin<"__builtin_altivec_vcmpequh">, - Intrinsic<[llvm_v4i32_ty, llvm_v8i16_ty, llvm_v8i16_ty], + Intrinsic<[llvm_v8i16_ty, llvm_v8i16_ty, llvm_v8i16_ty], [InstrNoMem]>; def int_ppc_altivec_vcmpgtsh : GCCBuiltin<"__builtin_altivec_vcmpgtsh">, - Intrinsic<[llvm_v4i32_ty, llvm_v8i16_ty, llvm_v8i16_ty], + Intrinsic<[llvm_v8i16_ty, llvm_v8i16_ty, llvm_v8i16_ty], [InstrNoMem]>; def int_ppc_altivec_vcmpgtuh : GCCBuiltin<"__builtin_altivec_vcmpgtuh">, - Intrinsic<[llvm_v4i32_ty, llvm_v8i16_ty, llvm_v8i16_ty], + Intrinsic<[llvm_v8i16_ty, llvm_v8i16_ty, llvm_v8i16_ty], [InstrNoMem]>; def int_ppc_altivec_vcmpequb : GCCBuiltin<"__builtin_altivec_vcmpequb">, - Intrinsic<[llvm_v4i32_ty, llvm_v16i8_ty, llvm_v16i8_ty], + Intrinsic<[llvm_v16i8_ty, llvm_v16i8_ty, llvm_v16i8_ty], [InstrNoMem]>; def int_ppc_altivec_vcmpgtsb : GCCBuiltin<"__builtin_altivec_vcmpgtsb">, - Intrinsic<[llvm_v4i32_ty, llvm_v16i8_ty, llvm_v16i8_ty], + Intrinsic<[llvm_v16i8_ty, llvm_v16i8_ty, llvm_v16i8_ty], [InstrNoMem]>; def int_ppc_altivec_vcmpgtub : GCCBuiltin<"__builtin_altivec_vcmpgtub">, - Intrinsic<[llvm_v4i32_ty, llvm_v16i8_ty, llvm_v16i8_ty], + Intrinsic<[llvm_v16i8_ty, llvm_v16i8_ty, llvm_v16i8_ty], [InstrNoMem]>; // Predicate Comparisons. The first operand specifies interpretation of CR6. From evan.cheng at apple.com Mon Apr 3 22:04:22 2006 From: evan.cheng at apple.com (Evan Cheng) Date: Mon, 3 Apr 2006 22:04:22 -0500 Subject: [llvm-commits] CVS: llvm/lib/Target/X86/X86InstrSSE.td Message-ID: <200604040304.WAA01415@zion.cs.uiuc.edu> Changes in directory llvm/lib/Target/X86: X86InstrSSE.td updated: 1.57 -> 1.58 --- Log message: cmpps / cmppd encoding bug --- Diffs of the changes: (+16 -16) X86InstrSSE.td | 32 ++++++++++++++++---------------- 1 files changed, 16 insertions(+), 16 deletions(-) Index: llvm/lib/Target/X86/X86InstrSSE.td diff -u llvm/lib/Target/X86/X86InstrSSE.td:1.57 llvm/lib/Target/X86/X86InstrSSE.td:1.58 --- llvm/lib/Target/X86/X86InstrSSE.td:1.57 Mon Apr 3 19:10:53 2006 +++ llvm/lib/Target/X86/X86InstrSSE.td Mon Apr 3 22:04:07 2006 @@ -963,22 +963,22 @@ } let isTwoAddress = 1 in { -def CMPPSrr : PSI<0xC2, MRMSrcReg, - (ops VR128:$dst, VR128:$src1, VR128:$src, SSECC:$cc), - "cmp${cc}ps {$src, $dst|$dst, $src}", - [(set VR128:$dst, (int_x86_sse_cmp_ps VR128:$src1, - VR128:$src, imm:$cc))]>; -def CMPPSrm : PSI<0xC2, MRMSrcMem, - (ops VR128:$dst, VR128:$src1, f128mem:$src, SSECC:$cc), - "cmp${cc}ps {$src, $dst|$dst, $src}", - [(set VR128:$dst, (int_x86_sse_cmp_ps VR128:$src1, - (load addr:$src), imm:$cc))]>; -def CMPPDrr : PDI<0xC2, MRMSrcReg, - (ops VR128:$dst, VR128:$src1, VR128:$src, SSECC:$cc), - "cmp${cc}pd {$src, $dst|$dst, $src}", []>; -def CMPPDrm : PDI<0xC2, MRMSrcMem, - (ops VR128:$dst, VR128:$src1, f128mem:$src, SSECC:$cc), - "cmp${cc}pd {$src, $dst|$dst, $src}", []>; +def CMPPSrr : PSIi8<0xC2, MRMSrcReg, + (ops VR128:$dst, VR128:$src1, VR128:$src, SSECC:$cc), + "cmp${cc}ps {$src, $dst|$dst, $src}", + [(set VR128:$dst, (int_x86_sse_cmp_ps VR128:$src1, + VR128:$src, imm:$cc))]>; +def CMPPSrm : PSIi8<0xC2, MRMSrcMem, + (ops VR128:$dst, VR128:$src1, f128mem:$src, SSECC:$cc), + "cmp${cc}ps {$src, $dst|$dst, $src}", + [(set VR128:$dst, (int_x86_sse_cmp_ps VR128:$src1, + (load addr:$src), imm:$cc))]>; +def CMPPDrr : PDIi8<0xC2, MRMSrcReg, + (ops VR128:$dst, VR128:$src1, VR128:$src, SSECC:$cc), + "cmp${cc}pd {$src, $dst|$dst, $src}", []>; +def CMPPDrm : PDIi8<0xC2, MRMSrcMem, + (ops VR128:$dst, VR128:$src1, f128mem:$src, SSECC:$cc), + "cmp${cc}pd {$src, $dst|$dst, $src}", []>; } // Shuffle and unpack instructions From lattner at cs.uiuc.edu Tue Apr 4 01:08:38 2006 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Tue, 4 Apr 2006 01:08:38 -0500 Subject: [llvm-commits] CVS: llvm-test/SingleSource/UnitTests/Vector/Altivec/alti.expandfft.c alti.isamax.c alti.sdot.c alti.stepfft.c Message-ID: <200604040608.BAA02233@zion.cs.uiuc.edu> Changes in directory llvm-test/SingleSource/UnitTests/Vector/Altivec: alti.expandfft.c updated: 1.1 -> 1.2 alti.isamax.c updated: 1.1 -> 1.2 alti.sdot.c updated: 1.1 -> 1.2 alti.stepfft.c updated: 1.1 -> 1.2 --- Log message: adjust these to allow them to compile. --- Diffs of the changes: (+8 -1) alti.expandfft.c | 6 +++++- alti.isamax.c | 1 + alti.sdot.c | 1 + alti.stepfft.c | 1 + 4 files changed, 8 insertions(+), 1 deletion(-) Index: llvm-test/SingleSource/UnitTests/Vector/Altivec/alti.expandfft.c diff -u llvm-test/SingleSource/UnitTests/Vector/Altivec/alti.expandfft.c:1.1 llvm-test/SingleSource/UnitTests/Vector/Altivec/alti.expandfft.c:1.2 --- llvm-test/SingleSource/UnitTests/Vector/Altivec/alti.expandfft.c:1.1 Mon Apr 3 19:47:54 2006 +++ llvm-test/SingleSource/UnitTests/Vector/Altivec/alti.expandfft.c Tue Apr 4 01:08:25 2006 @@ -2,8 +2,13 @@ #include #include #include +#include +#include #define N 1048576 #define N2 N/2 +void cfft2(unsigned int n,float x[][2],float y[][2],float w[][2], float sign); +void cffti(int n, float w[][2]); + main() { /* @@ -29,7 +34,6 @@ float error,fnm1,sign,z0,z1,ggl(); float *x,*y,*z,*w; double t1,mflops; - void cffti(),cfft2(); /* allocate storage for x,y,z,w on 4-word bndr. */ x = (float *) malloc(8*N); y = (float *) malloc(8*N); Index: llvm-test/SingleSource/UnitTests/Vector/Altivec/alti.isamax.c diff -u llvm-test/SingleSource/UnitTests/Vector/Altivec/alti.isamax.c:1.1 llvm-test/SingleSource/UnitTests/Vector/Altivec/alti.isamax.c:1.2 --- llvm-test/SingleSource/UnitTests/Vector/Altivec/alti.isamax.c:1.1 Mon Apr 3 19:47:54 2006 +++ llvm-test/SingleSource/UnitTests/Vector/Altivec/alti.isamax.c Tue Apr 4 01:08:25 2006 @@ -1,6 +1,7 @@ #include #include #include +#include #define N 1027 main() { Index: llvm-test/SingleSource/UnitTests/Vector/Altivec/alti.sdot.c diff -u llvm-test/SingleSource/UnitTests/Vector/Altivec/alti.sdot.c:1.1 llvm-test/SingleSource/UnitTests/Vector/Altivec/alti.sdot.c:1.2 --- llvm-test/SingleSource/UnitTests/Vector/Altivec/alti.sdot.c:1.1 Mon Apr 3 19:47:54 2006 +++ llvm-test/SingleSource/UnitTests/Vector/Altivec/alti.sdot.c Tue Apr 4 01:08:25 2006 @@ -1,4 +1,5 @@ #include +#include #include #include #define N 1027 Index: llvm-test/SingleSource/UnitTests/Vector/Altivec/alti.stepfft.c diff -u llvm-test/SingleSource/UnitTests/Vector/Altivec/alti.stepfft.c:1.1 llvm-test/SingleSource/UnitTests/Vector/Altivec/alti.stepfft.c:1.2 --- llvm-test/SingleSource/UnitTests/Vector/Altivec/alti.stepfft.c:1.1 Mon Apr 3 19:47:54 2006 +++ llvm-test/SingleSource/UnitTests/Vector/Altivec/alti.stepfft.c Tue Apr 4 01:08:25 2006 @@ -2,6 +2,7 @@ #include #include #include +#include #define N 128 #define N2 N/2 main() From lattner at cs.uiuc.edu Tue Apr 4 01:11:55 2006 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Tue, 4 Apr 2006 01:11:55 -0500 Subject: [llvm-commits] CVS: llvm/lib/Analysis/ScalarEvolution.cpp Message-ID: <200604040611.BAA02297@zion.cs.uiuc.edu> Changes in directory llvm/lib/Analysis: ScalarEvolution.cpp updated: 1.46 -> 1.47 --- Log message: Signed shr by a constant is not the same as sdiv by 2^k --- Diffs of the changes: (+0 -9) ScalarEvolution.cpp | 9 --------- 1 files changed, 9 deletions(-) Index: llvm/lib/Analysis/ScalarEvolution.cpp diff -u llvm/lib/Analysis/ScalarEvolution.cpp:1.46 llvm/lib/Analysis/ScalarEvolution.cpp:1.47 --- llvm/lib/Analysis/ScalarEvolution.cpp:1.46 Fri Mar 31 22:48:52 2006 +++ llvm/lib/Analysis/ScalarEvolution.cpp Tue Apr 4 01:11:42 2006 @@ -1374,15 +1374,6 @@ } break; - case Instruction::Shr: - if (ConstantUInt *SA = dyn_cast(I->getOperand(1))) - if (V->getType()->isSigned()) { - Constant *X = ConstantInt::get(V->getType(), 1); - X = ConstantExpr::getShl(X, SA); - return SCEVSDivExpr::get(getSCEV(I->getOperand(0)), getSCEV(X)); - } - break; - case Instruction::Cast: return createNodeForCast(cast(I)); From lattner at cs.uiuc.edu Tue Apr 4 01:50:37 2006 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Tue, 4 Apr 2006 01:50:37 -0500 Subject: [llvm-commits] CVS: llvm-test/SingleSource/UnitTests/Vector/multiplies.c helpers.h Message-ID: <200604040650.BAA02464@zion.cs.uiuc.edu> Changes in directory llvm-test/SingleSource/UnitTests/Vector: multiplies.c added (r1.1) helpers.h updated: 1.4 -> 1.5 --- Log message: new testcase for multiplies --- Diffs of the changes: (+50 -0) helpers.h | 16 ++++++++++++++++ multiplies.c | 34 ++++++++++++++++++++++++++++++++++ 2 files changed, 50 insertions(+) Index: llvm-test/SingleSource/UnitTests/Vector/multiplies.c diff -c /dev/null llvm-test/SingleSource/UnitTests/Vector/multiplies.c:1.1 *** /dev/null Tue Apr 4 01:50:34 2006 --- llvm-test/SingleSource/UnitTests/Vector/multiplies.c Tue Apr 4 01:50:24 2006 *************** *** 0 **** --- 1,34 ---- + #include "helpers.h" + + #define ARRAYSIZE 100000 + double TheArray[ARRAYSIZE]; + + #define ProcessArray(VECTY) { \ + VECTY V = (VECTY)((v4i32){0,0,0,0}); \ + VECTY *AP = (VECTY*)TheArray; \ + IV vu; \ + for (j = 0; j < 1000; ++j) \ + for (i = 0; i != sizeof(TheArray)/sizeof(VECTY); ++i) \ + V *= AP[i]; \ + vu.V = (v4i32)V; \ + printIV(&vu); \ + } + + + int main(int argc, char **Argv) { + unsigned i, j; + for (i = 0; i < ARRAYSIZE; ++i) + TheArray[i] = i*12.345; + + ProcessArray(v16i8); + ProcessArray(v8i16); + ProcessArray(v4i32); + ProcessArray(v2i64); + + // These break native gcc. :( + #if 0 + ProcessArray(v4f32); + ProcessArray(v2f64); + #endif + } + Index: llvm-test/SingleSource/UnitTests/Vector/helpers.h diff -u llvm-test/SingleSource/UnitTests/Vector/helpers.h:1.4 llvm-test/SingleSource/UnitTests/Vector/helpers.h:1.5 --- llvm-test/SingleSource/UnitTests/Vector/helpers.h:1.4 Thu Mar 30 20:11:46 2006 +++ llvm-test/SingleSource/UnitTests/Vector/helpers.h Tue Apr 4 01:50:24 2006 @@ -7,6 +7,18 @@ typedef float v8sf __attribute__ ((__vector_size__ (32))); typedef double v8sd __attribute__ ((__vector_size__ (64))); +typedef int v2i64 __attribute__ ((__vector_size__ (16))); +typedef int v4i32 __attribute__ ((__vector_size__ (16))); +typedef short v8i16 __attribute__ ((__vector_size__ (16))); +typedef char v16i8 __attribute__ ((__vector_size__ (16))); +typedef float v4f32 __attribute__ ((__vector_size__ (16))); +typedef double v2f64 __attribute__ ((__vector_size__ (16))); + +typedef union { + v4i32 V; + int A[4]; +} IV; + typedef union { v4sf V; float A[4]; @@ -22,6 +34,10 @@ double A[8]; } D8V; +static void printIV(IV *F) { + printf("%u %u %u %u\n", F->A[0], F->A[1], F->A[2], F->A[3]); +} + static void printFV(FV *F) { printf("%f %f %f %f\n", F->A[0], F->A[1], F->A[2], F->A[3]); } From lattner at cs.uiuc.edu Tue Apr 4 12:20:58 2006 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Tue, 4 Apr 2006 12:20:58 -0500 Subject: [llvm-commits] CVS: llvm/test/Regression/CodeGen/PowerPC/vec_spat.ll Message-ID: <200604041720.MAA14966@zion.cs.uiuc.edu> Changes in directory llvm/test/Regression/CodeGen/PowerPC: vec_spat.ll updated: 1.2 -> 1.3 --- Log message: new testcase --- Diffs of the changes: (+17 -2) vec_spat.ll | 19 +++++++++++++++++-- 1 files changed, 17 insertions(+), 2 deletions(-) Index: llvm/test/Regression/CodeGen/PowerPC/vec_spat.ll diff -u llvm/test/Regression/CodeGen/PowerPC/vec_spat.ll:1.2 llvm/test/Regression/CodeGen/PowerPC/vec_spat.ll:1.3 --- llvm/test/Regression/CodeGen/PowerPC/vec_spat.ll:1.2 Sat Mar 25 00:11:56 2006 +++ llvm/test/Regression/CodeGen/PowerPC/vec_spat.ll Tue Apr 4 12:20:45 2006 @@ -1,7 +1,8 @@ ; Test that vectors are scalarized/lowered correctly. ; RUN: llvm-as < %s | llc -march=ppc32 -mcpu=g5 | grep vspltw | wc -l | grep 2 && -; RUN: llvm-as < %s | llc -march=ppc32 -mcpu=g3 | grep stfs | wc -l | grep 4 -; RUN: llvm-as < %s | llc -march=ppc32 -mcpu=g5 | grep vsplti | wc -l | grep 2 +; RUN: llvm-as < %s | llc -march=ppc32 -mcpu=g3 | grep stfs | wc -l | grep 4 && +; RUN: llvm-as < %s | llc -march=ppc32 -mcpu=g5 | grep vsplti | wc -l | grep 2 && +; RUN: llvm-as < %s | llc -march=ppc32 -mcpu=g5 | grep vsplth | wc -l | grep 1 %f4 = type <4 x float> %i4 = type <4 x int> @@ -44,3 +45,17 @@ ret void } +void %splat_h(short %tmp, <16 x ubyte>* %dst) { + %tmp = insertelement <8 x short> undef, short %tmp, uint 0 + %tmp72 = insertelement <8 x short> %tmp, short %tmp, uint 1 + %tmp73 = insertelement <8 x short> %tmp72, short %tmp, uint 2 + %tmp74 = insertelement <8 x short> %tmp73, short %tmp, uint 3 + %tmp75 = insertelement <8 x short> %tmp74, short %tmp, uint 4 + %tmp76 = insertelement <8 x short> %tmp75, short %tmp, uint 5 + %tmp77 = insertelement <8 x short> %tmp76, short %tmp, uint 6 + %tmp78 = insertelement <8 x short> %tmp77, short %tmp, uint 7 + %tmp78 = cast <8 x short> %tmp78 to <16 x ubyte> + store <16 x ubyte> %tmp78, <16 x ubyte>* %dst + ret void +} + From lattner at cs.uiuc.edu Tue Apr 4 12:21:35 2006 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Tue, 4 Apr 2006 12:21:35 -0500 Subject: [llvm-commits] CVS: llvm/include/llvm/Target/TargetLowering.h Message-ID: <200604041721.MAA15001@zion.cs.uiuc.edu> Changes in directory llvm/include/llvm/Target: TargetLowering.h updated: 1.66 -> 1.67 --- Log message: Move isShuffleLegal from TLI to Legalize. --- Diffs of the changes: (+8 -17) TargetLowering.h | 25 ++++++++----------------- 1 files changed, 8 insertions(+), 17 deletions(-) Index: llvm/include/llvm/Target/TargetLowering.h diff -u llvm/include/llvm/Target/TargetLowering.h:1.66 llvm/include/llvm/Target/TargetLowering.h:1.67 --- llvm/include/llvm/Target/TargetLowering.h:1.66 Mon Apr 3 19:25:10 2006 +++ llvm/include/llvm/Target/TargetLowering.h Tue Apr 4 12:21:22 2006 @@ -191,6 +191,14 @@ legal_fpimm_iterator legal_fpimm_end() const { return LegalFPImmediates.end(); } + + /// isShuffleMaskLegal - Targets can use this to indicate that they only + /// support *some* VECTOR_SHUFFLE operations, those with specific masks. + /// By default, if a target supports the VECTOR_SHUFFLE node, all mask values + /// are assumed to be legal. + virtual bool isShuffleMaskLegal(SDOperand Mask, MVT::ValueType VT) const { + return true; + } /// getOperationAction - Return how this operation should be treated: either /// it is legal, needs to be promoted to a larger size, needs to be @@ -207,15 +215,6 @@ getOperationAction(Op, VT) == Custom; } - - /// isVectorShuffleLegal - Return true if a vector shuffle is legal with the - /// specified mask and type. Targets can specify exactly which masks they - /// support and the code generator is tasked with not creating illegal masks. - bool isShuffleLegal(MVT::ValueType VT, SDOperand Mask) const { - return isOperationLegal(ISD::VECTOR_SHUFFLE, VT) && - isShuffleMaskLegal(Mask, VT); - } - /// getTypeToPromoteTo - If the action for this operation is to promote, this /// method returns the ValueType to promote to. MVT::ValueType getTypeToPromoteTo(unsigned Op, MVT::ValueType VT) const { @@ -515,14 +514,6 @@ TargetDAGCombineArray[NT >> 3] |= 1 << (NT&7); } - /// isShuffleMaskLegal - Targets can use this to indicate that they only - /// support *some* VECTOR_SHUFFLE operations, those with specific masks. - /// By default, if a target supports the VECTOR_SHUFFLE node, all mask values - /// are assumed to be legal. - virtual bool isShuffleMaskLegal(SDOperand Mask, MVT::ValueType VT) const { - return true; - } - public: //===--------------------------------------------------------------------===// From lattner at cs.uiuc.edu Tue Apr 4 12:23:39 2006 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Tue, 4 Apr 2006 12:23:39 -0500 Subject: [llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp Message-ID: <200604041723.MAA15091@zion.cs.uiuc.edu> Changes in directory llvm/lib/CodeGen/SelectionDAG: LegalizeDAG.cpp updated: 1.351 -> 1.352 --- Log message: * Add supprot for SCALAR_TO_VECTOR operations where the input needs to be promoted/expanded (e.g. SCALAR_TO_VECTOR from i8/i16 on PPC). * Add support for targets to request that VECTOR_SHUFFLE nodes be promoted to a canonical type, for example, we only want v16i8 shuffles on PPC. * Move isShuffleLegal out of TLI into Legalize. * Teach isShuffleLegal to allow shuffles that need to be promoted. --- Diffs of the changes: (+102 -21) LegalizeDAG.cpp | 123 ++++++++++++++++++++++++++++++++++++++++++++++---------- 1 files changed, 102 insertions(+), 21 deletions(-) Index: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp diff -u llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.351 llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.352 --- llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.351 Sat Apr 1 23:06:04 2006 +++ llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp Tue Apr 4 12:23:26 2006 @@ -165,6 +165,17 @@ /// we know that this type is legal for the target. SDOperand PackVectorOp(SDOperand O, MVT::ValueType PackedVT); + /// isShuffleLegal - Return true if a vector shuffle is legal with the + /// specified mask and type. Targets can specify exactly which masks they + /// support and the code generator is tasked with not creating illegal masks. + /// + /// Note that this will also return true for shuffles that are promoted to a + /// different type. + /// + /// If this is a legal shuffle, this method returns the (possibly promoted) + /// build_vector Mask. If it's not a legal shuffle, it returns null. + SDNode *isShuffleLegal(MVT::ValueType VT, SDOperand Mask) const; + bool LegalizeAllNodesNotLeadingTo(SDNode *N, SDNode *Dest); void LegalizeSetCCOperands(SDOperand &LHS, SDOperand &RHS, SDOperand &CC); @@ -178,6 +189,7 @@ SDOperand ExpandBIT_CONVERT(MVT::ValueType DestVT, SDOperand SrcOp); SDOperand ExpandBUILD_VECTOR(SDNode *Node); + SDOperand ExpandSCALAR_TO_VECTOR(SDNode *Node); SDOperand ExpandLegalINT_TO_FP(bool isSigned, SDOperand LegalOp, MVT::ValueType DestVT); @@ -202,6 +214,51 @@ }; } +/// isVectorShuffleLegal - Return true if a vector shuffle is legal with the +/// specified mask and type. Targets can specify exactly which masks they +/// support and the code generator is tasked with not creating illegal masks. +/// +/// Note that this will also return true for shuffles that are promoted to a +/// different type. +SDNode *SelectionDAGLegalize::isShuffleLegal(MVT::ValueType VT, + SDOperand Mask) const { + switch (TLI.getOperationAction(ISD::VECTOR_SHUFFLE, VT)) { + default: return 0; + case TargetLowering::Legal: + case TargetLowering::Custom: + break; + case TargetLowering::Promote: { + // If this is promoted to a different type, convert the shuffle mask and + // ask if it is legal in the promoted type! + MVT::ValueType NVT = TLI.getTypeToPromoteTo(ISD::VECTOR_SHUFFLE, VT); + + // If we changed # elements, change the shuffle mask. + unsigned NumEltsGrowth = + MVT::getVectorNumElements(NVT) / MVT::getVectorNumElements(VT); + assert(NumEltsGrowth && "Cannot promote to vector type with fewer elts!"); + if (NumEltsGrowth > 1) { + // Renumber the elements. + std::vector Ops; + for (unsigned i = 0, e = Mask.getNumOperands(); i != e; ++i) { + SDOperand InOp = Mask.getOperand(i); + for (unsigned j = 0; j != NumEltsGrowth; ++j) { + if (InOp.getOpcode() == ISD::UNDEF) + Ops.push_back(DAG.getNode(ISD::UNDEF, MVT::i32)); + else { + unsigned InEltNo = cast(InOp)->getValue(); + Ops.push_back(DAG.getConstant(InEltNo*NumEltsGrowth+j, MVT::i32)); + } + } + } + Mask = DAG.getNode(ISD::BUILD_VECTOR, NVT, Ops); + } + VT = NVT; + break; + } + } + return TLI.isShuffleMaskLegal(Mask, VT) ? Mask.Val : 0; +} + /// getScalarizedOpcode - Return the scalar opcode that corresponds to the /// specified vector opcode. static unsigned getScalarizedOpcode(unsigned VecOp, MVT::ValueType VT) { @@ -839,6 +896,11 @@ } break; case ISD::SCALAR_TO_VECTOR: + if (!TLI.isTypeLegal(Node->getOperand(0).getValueType())) { + Result = LegalizeOp(ExpandSCALAR_TO_VECTOR(Node)); + break; + } + Tmp1 = LegalizeOp(Node->getOperand(0)); // InVal Result = DAG.UpdateNodeOperands(Result, Tmp1); switch (TLI.getOperationAction(ISD::SCALAR_TO_VECTOR, @@ -853,35 +915,43 @@ break; } // FALLTHROUGH - case TargetLowering::Expand: { - // If the target doesn't support this, store the value to a temporary - // stack slot, then EXTLOAD the vector back out. - // TODO: If a target doesn't support this, create a stack slot for the - // whole vector, then store into it, then load the whole vector. - SDOperand StackPtr = - CreateStackTemporary(Node->getOperand(0).getValueType()); - SDOperand Ch = DAG.getNode(ISD::STORE, MVT::Other, DAG.getEntryNode(), - Node->getOperand(0), StackPtr, - DAG.getSrcValue(NULL)); - Result = DAG.getExtLoad(ISD::EXTLOAD, Node->getValueType(0), Ch, StackPtr, - DAG.getSrcValue(NULL), - Node->getOperand(0).getValueType()); + case TargetLowering::Expand: + Result = LegalizeOp(ExpandSCALAR_TO_VECTOR(Node)); break; } - } break; case ISD::VECTOR_SHUFFLE: - assert(TLI.isShuffleLegal(Result.getValueType(), Node->getOperand(2)) && - "vector shuffle should not be created if not legal!"); Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the input vectors, Tmp2 = LegalizeOp(Node->getOperand(1)); // but not the shuffle mask. Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2)); // Allow targets to custom lower the SHUFFLEs they support. - if (TLI.getOperationAction(ISD::VECTOR_SHUFFLE, Result.getValueType()) - == TargetLowering::Custom) { + switch (TLI.getOperationAction(ISD::VECTOR_SHUFFLE,Result.getValueType())) { + default: assert(0 && "Unknown operation action!"); + case TargetLowering::Legal: + assert(isShuffleLegal(Result.getValueType(), Node->getOperand(2)) && + "vector shuffle should not be created if not legal!"); + break; + case TargetLowering::Custom: Tmp1 = TLI.LowerOperation(Result, DAG); if (Tmp1.Val) Result = Tmp1; + break; + case TargetLowering::Promote: { + // Change base type to a different vector type. + MVT::ValueType OVT = Node->getValueType(0); + MVT::ValueType NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT); + + // Cast the two input vectors. + Tmp1 = DAG.getNode(ISD::BIT_CONVERT, NVT, Tmp1); + Tmp2 = DAG.getNode(ISD::BIT_CONVERT, NVT, Tmp2); + + // Convert the shuffle mask to the right # elements. + Tmp3 = SDOperand(isShuffleLegal(OVT, Node->getOperand(2)), 0); + assert(Tmp3.Val && "Shuffle not legal?"); + Result = DAG.getNode(ISD::VECTOR_SHUFFLE, NVT, Tmp1, Tmp2, Tmp3); + Result = DAG.getNode(ISD::BIT_CONVERT, OVT, Result); + break; + } } break; @@ -3197,6 +3267,17 @@ return DAG.getLoad(DestVT, Store, FIPtr, DAG.getSrcValue(0)); } +SDOperand SelectionDAGLegalize::ExpandSCALAR_TO_VECTOR(SDNode *Node) { + // Create a vector sized/aligned stack slot, store the value to element #0, + // then load the whole vector back out. + SDOperand StackPtr = CreateStackTemporary(Node->getValueType(0)); + SDOperand Ch = DAG.getNode(ISD::STORE, MVT::Other, DAG.getEntryNode(), + Node->getOperand(0), StackPtr, + DAG.getSrcValue(NULL)); + return DAG.getLoad(Node->getValueType(0), Ch, StackPtr,DAG.getSrcValue(NULL)); +} + + /// ExpandBUILD_VECTOR - Expand a BUILD_VECTOR node on targets that don't /// support the operation, but do support the resultant packed vector type. SDOperand SelectionDAGLegalize::ExpandBUILD_VECTOR(SDNode *Node) { @@ -3274,7 +3355,7 @@ SDOperand SplatMask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT, ZeroVec); // If the target supports VECTOR_SHUFFLE and this shuffle mask, use it. - if (TLI.isShuffleLegal(Node->getValueType(0), SplatMask)) { + if (isShuffleLegal(Node->getValueType(0), SplatMask)) { // Get the splatted value into the low element of a vector register. SDOperand LowValVec = DAG.getNode(ISD::SCALAR_TO_VECTOR, Node->getValueType(0), SplatValue); @@ -3304,8 +3385,8 @@ SDOperand ShuffleMask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT, MaskVec); // If the target supports VECTOR_SHUFFLE and this shuffle mask, use it. - if (TLI.isShuffleLegal(Node->getValueType(0), ShuffleMask) && - TLI.isOperationLegal(ISD::SCALAR_TO_VECTOR, Node->getValueType(0))) { + if (TLI.isOperationLegal(ISD::SCALAR_TO_VECTOR, Node->getValueType(0)) && + isShuffleLegal(Node->getValueType(0), ShuffleMask)) { std::vector Ops; for(std::map >::iterator I=Values.begin(), E = Values.end(); I != E; ++I) { From lattner at cs.uiuc.edu Tue Apr 4 12:25:43 2006 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Tue, 4 Apr 2006 12:25:43 -0500 Subject: [llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCISelLowering.cpp PPCISelLowering.h PPCInstrAltivec.td Message-ID: <200604041725.MAA15182@zion.cs.uiuc.edu> Changes in directory llvm/lib/Target/PowerPC: PPCISelLowering.cpp updated: 1.128 -> 1.129 PPCISelLowering.h updated: 1.38 -> 1.39 PPCInstrAltivec.td updated: 1.32 -> 1.33 --- Log message: Ask legalize to promote all vector shuffles to be v16i8 instead of having to handle all 4 PPC vector types. This simplifies the matching code and allows us to eliminate a bunch of patterns. This also adds cases we were missing, such as CodeGen/PowerPC/vec_splat.ll:splat_h. --- Diffs of the changes: (+68 -45) PPCISelLowering.cpp | 56 ++++++++++++++++++++++++++++++++++++---------------- PPCISelLowering.h | 4 +-- PPCInstrAltivec.td | 53 +++++++++++++++++++++++++------------------------ 3 files changed, 68 insertions(+), 45 deletions(-) Index: llvm/lib/Target/PowerPC/PPCISelLowering.cpp diff -u llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.128 llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.129 --- llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.128 Mon Apr 3 18:58:04 2006 +++ llvm/lib/Target/PowerPC/PPCISelLowering.cpp Tue Apr 4 12:25:31 2006 @@ -181,8 +181,9 @@ setOperationAction(ISD::OR , (MVT::ValueType)VT, Legal); setOperationAction(ISD::XOR , (MVT::ValueType)VT, Legal); - // We can custom expand all VECTOR_SHUFFLEs to VPERM. - setOperationAction(ISD::VECTOR_SHUFFLE, (MVT::ValueType)VT, Custom); + // We promote all shuffles to v16i8. + setOperationAction(ISD::VECTOR_SHUFFLE, (MVT::ValueType)VT, Promote); + AddPromotedToType(ISD::VECTOR_SHUFFLE, (MVT::ValueType)VT, MVT::v16i8); setOperationAction(ISD::MUL , (MVT::ValueType)VT, Expand); setOperationAction(ISD::SDIV, (MVT::ValueType)VT, Expand); @@ -196,6 +197,10 @@ setOperationAction(ISD::SCALAR_TO_VECTOR, (MVT::ValueType)VT, Expand); } + // We can custom expand all VECTOR_SHUFFLEs to VPERM, others we can handle + // with merges, splats, etc. + setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v16i8, Custom); + addRegisterClass(MVT::v4f32, PPC::VRRCRegisterClass); addRegisterClass(MVT::v4i32, PPC::VRRCRegisterClass); addRegisterClass(MVT::v8i16, PPC::VRRCRegisterClass); @@ -266,33 +271,47 @@ /// isSplatShuffleMask - Return true if the specified VECTOR_SHUFFLE operand /// specifies a splat of a single element that is suitable for input to /// VSPLTB/VSPLTH/VSPLTW. -bool PPC::isSplatShuffleMask(SDNode *N) { - assert(N->getOpcode() == ISD::BUILD_VECTOR); - - // We can only splat 8-bit, 16-bit, and 32-bit quantities. - if (N->getNumOperands() != 4 && N->getNumOperands() != 8 && - N->getNumOperands() != 16) - return false; +bool PPC::isSplatShuffleMask(SDNode *N, unsigned EltSize) { + assert(N->getOpcode() == ISD::BUILD_VECTOR && + N->getNumOperands() == 16 && + (EltSize == 1 || EltSize == 2 || EltSize == 4)); // This is a splat operation if each element of the permute is the same, and // if the value doesn't reference the second vector. + unsigned ElementBase = 0; SDOperand Elt = N->getOperand(0); + if (ConstantSDNode *EltV = dyn_cast(Elt)) + ElementBase = EltV->getValue(); + else + return false; // FIXME: Handle UNDEF elements too! + + if (cast(Elt)->getValue() >= 16) + return false; + + // Check that they are consequtive. + for (unsigned i = 1; i != EltSize; ++i) { + if (!isa(N->getOperand(i)) || + cast(N->getOperand(i))->getValue() != i+ElementBase) + return false; + } + assert(isa(Elt) && "Invalid VECTOR_SHUFFLE mask!"); - for (unsigned i = 1, e = N->getNumOperands(); i != e; ++i) { + for (unsigned i = EltSize, e = 16; i != e; i += EltSize) { assert(isa(N->getOperand(i)) && "Invalid VECTOR_SHUFFLE mask!"); - if (N->getOperand(i) != Elt) return false; + for (unsigned j = 0; j != EltSize; ++j) + if (N->getOperand(i+j) != N->getOperand(j)) + return false; } - // Make sure it is a splat of the first vector operand. - return cast(Elt)->getValue() < N->getNumOperands(); + return true; } /// getVSPLTImmediate - Return the appropriate VSPLT* immediate to splat the /// specified isSplatShuffleMask VECTOR_SHUFFLE mask. -unsigned PPC::getVSPLTImmediate(SDNode *N) { - assert(isSplatShuffleMask(N)); - return cast(N->getOperand(0))->getValue(); +unsigned PPC::getVSPLTImmediate(SDNode *N, unsigned EltSize) { + assert(isSplatShuffleMask(N, EltSize)); + return cast(N->getOperand(0))->getValue() / EltSize; } /// isVecSplatImm - Return true if this is a build_vector of constants which @@ -734,7 +753,10 @@ // Cases that are handled by instructions that take permute immediates // (such as vsplt*) should be left as VECTOR_SHUFFLE nodes so they can be // selected by the instruction selector. - if (PPC::isSplatShuffleMask(PermMask.Val) && V2.getOpcode() == ISD::UNDEF) + if (V2.getOpcode() == ISD::UNDEF && + (PPC::isSplatShuffleMask(PermMask.Val, 1) || + PPC::isSplatShuffleMask(PermMask.Val, 2) || + PPC::isSplatShuffleMask(PermMask.Val, 4))) break; // TODO: Handle more cases, and also handle cases that are cheaper to do as Index: llvm/lib/Target/PowerPC/PPCISelLowering.h diff -u llvm/lib/Target/PowerPC/PPCISelLowering.h:1.38 llvm/lib/Target/PowerPC/PPCISelLowering.h:1.39 --- llvm/lib/Target/PowerPC/PPCISelLowering.h:1.38 Sun Apr 2 00:26:07 2006 +++ llvm/lib/Target/PowerPC/PPCISelLowering.h Tue Apr 4 12:25:31 2006 @@ -105,11 +105,11 @@ /// isSplatShuffleMask - Return true if the specified VECTOR_SHUFFLE operand /// specifies a splat of a single element that is suitable for input to /// VSPLTB/VSPLTH/VSPLTW. - bool isSplatShuffleMask(SDNode *N); + bool isSplatShuffleMask(SDNode *N, unsigned EltSize); /// getVSPLTImmediate - Return the appropriate VSPLT* immediate to splat the /// specified isSplatShuffleMask VECTOR_SHUFFLE mask. - unsigned getVSPLTImmediate(SDNode *N); + unsigned getVSPLTImmediate(SDNode *N, unsigned EltSize); /// isVecSplatImm - Return true if this is a build_vector of constants which /// can be formed by using a vspltis[bhw] instruction. The ByteSize field Index: llvm/lib/Target/PowerPC/PPCInstrAltivec.td diff -u llvm/lib/Target/PowerPC/PPCInstrAltivec.td:1.32 llvm/lib/Target/PowerPC/PPCInstrAltivec.td:1.33 --- llvm/lib/Target/PowerPC/PPCInstrAltivec.td:1.32 Mon Apr 3 19:05:13 2006 +++ llvm/lib/Target/PowerPC/PPCInstrAltivec.td Tue Apr 4 12:25:31 2006 @@ -15,14 +15,25 @@ // Altivec transformation functions and pattern fragments. // -// VSPLT_get_imm xform function: convert vector_shuffle mask to VSPLT* imm. -def VSPLT_get_imm : SDNodeXForm; - -def VSPLT_shuffle_mask : PatLeaf<(build_vector), [{ - return PPC::isSplatShuffleMask(N); -}], VSPLT_get_imm>; +def VSPLTB_shuffle_mask : PatLeaf<(build_vector), [{ + return PPC::isSplatShuffleMask(N, 1); +}], VSPLTB_get_imm>; +def VSPLTH_get_imm : SDNodeXForm; +def VSPLTH_shuffle_mask : PatLeaf<(build_vector), [{ + return PPC::isSplatShuffleMask(N, 2); +}], VSPLTH_get_imm>; +def VSPLTW_get_imm : SDNodeXForm; +def VSPLTW_shuffle_mask : PatLeaf<(build_vector), [{ + return PPC::isSplatShuffleMask(N, 4); +}], VSPLTW_get_imm>; // VSPLTISB_get_imm xform function: convert build_vector to VSPLTISB imm. @@ -55,11 +66,6 @@ return PPC::isVecSplatImm(N, 4); }], VSPLTISW_get_imm>; -class isVDOT { // vector dot instruction. - list Defs = [CR6]; - bit RC = 1; -} - //===----------------------------------------------------------------------===// // Helpers for defining instructions that directly correspond to intrinsics. @@ -294,15 +300,15 @@ def VSPLTB : VXForm_1<524, (ops VRRC:$vD, u5imm:$UIMM, VRRC:$vB), "vspltb $vD, $vB, $UIMM", VecPerm, [(set VRRC:$vD, (vector_shuffle (v16i8 VRRC:$vB), (undef), - VSPLT_shuffle_mask:$UIMM))]>; + VSPLTB_shuffle_mask:$UIMM))]>; def VSPLTH : VXForm_1<588, (ops VRRC:$vD, u5imm:$UIMM, VRRC:$vB), "vsplth $vD, $vB, $UIMM", VecPerm, - [(set VRRC:$vD, (vector_shuffle (v8i16 VRRC:$vB), (undef), - VSPLT_shuffle_mask:$UIMM))]>; + [(set VRRC:$vD, (vector_shuffle (v16i8 VRRC:$vB), (undef), + VSPLTH_shuffle_mask:$UIMM))]>; def VSPLTW : VXForm_1<652, (ops VRRC:$vD, u5imm:$UIMM, VRRC:$vB), "vspltw $vD, $vB, $UIMM", VecPerm, - [(set VRRC:$vD, (vector_shuffle (v4f32 VRRC:$vB), (undef), - VSPLT_shuffle_mask:$UIMM))]>; + [(set VRRC:$vD, (vector_shuffle (v16i8 VRRC:$vB), (undef), + VSPLTW_shuffle_mask:$UIMM))]>; def VSR : VX1_Int< 708, "vsr" , int_ppc_altivec_vsr>; def VSRO : VX1_Int<1100, "vsro" , int_ppc_altivec_vsro>; @@ -355,7 +361,10 @@ [(set VRRC:$vD, (Ty (PPCvcmp VRRC:$vA, VRRC:$vB, xo)))]>; class VCMPo xo, string asmstr, ValueType Ty> : VXRForm_1,isVDOT; + [(set VRRC:$vD, (Ty (PPCvcmp_o VRRC:$vA, VRRC:$vB, xo)))]> { + let Defs = [CR6]; + let RC = 1; +} // f32 element comparisons.0 def VCMPBFP : VCMP <966, "vcmpbfp $vD, $vA, $vB" , v4f32>; @@ -487,14 +496,6 @@ (VMADDFP VRRC:$A, VRRC:$B, VRRC:$C)>; def : Pat<(int_ppc_altivec_vnmsubfp VRRC:$A, VRRC:$B, VRRC:$C), (VNMSUBFP VRRC:$A, VRRC:$B, VRRC:$C)>; -def : Pat<(vector_shuffle (v4i32 VRRC:$vB), (undef), VSPLT_shuffle_mask:$UIMM), - (v4i32 (VSPLTW VSPLT_shuffle_mask:$UIMM, VRRC:$vB))>; -def : Pat<(PPCvperm (v4i32 VRRC:$vA), VRRC:$vB, VRRC:$vC), - (v4i32 (VPERM VRRC:$vA, VRRC:$vB, VRRC:$vC))>; -def : Pat<(PPCvperm (v4f32 VRRC:$vA), VRRC:$vB, VRRC:$vC), - (v4f32 (VPERM VRRC:$vA, VRRC:$vB, VRRC:$vC))>; -def : Pat<(PPCvperm (v8i16 VRRC:$vA), VRRC:$vB, VRRC:$vC), - (v8i16 (VPERM VRRC:$vA, VRRC:$vB, VRRC:$vC))>; def : Pat<(PPCvperm (v16i8 VRRC:$vA), VRRC:$vB, VRRC:$vC), (v16i8 (VPERM VRRC:$vA, VRRC:$vB, VRRC:$vC))>; From lattner at cs.uiuc.edu Tue Apr 4 12:38:43 2006 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Tue, 4 Apr 2006 12:38:43 -0500 Subject: [llvm-commits] CVS: llvm/test/Regression/CodeGen/Alpha/2006-04-04-zextload.ll Message-ID: <200604041738.MAA15445@zion.cs.uiuc.edu> Changes in directory llvm/test/Regression/CodeGen/Alpha: 2006-04-04-zextload.ll added (r1.1) --- Log message: New testcase --- Diffs of the changes: (+36 -0) 2006-04-04-zextload.ll | 36 ++++++++++++++++++++++++++++++++++++ 1 files changed, 36 insertions(+) Index: llvm/test/Regression/CodeGen/Alpha/2006-04-04-zextload.ll diff -c /dev/null llvm/test/Regression/CodeGen/Alpha/2006-04-04-zextload.ll:1.1 *** /dev/null Tue Apr 4 12:38:41 2006 --- llvm/test/Regression/CodeGen/Alpha/2006-04-04-zextload.ll Tue Apr 4 12:38:31 2006 *************** *** 0 **** --- 1,36 ---- + ; RUN: llvm-as < %s | llc -march=alpha + + target endian = little + target pointersize = 64 + target triple = "alphaev67-unknown-linux-gnu" + %llvm.dbg.compile_unit.type = type { uint, { }*, uint, uint, sbyte*, sbyte*, sbyte* } + %struct._Callback_list = type { %struct._Callback_list*, void (uint, %struct.ios_base*, int)*, int, int } + %struct._Impl = type { int, %struct.facet**, ulong, %struct.facet**, sbyte** } + %struct._Words = type { sbyte*, long } + "struct.__codecvt_abstract_base" = type { %struct.facet } + "struct.basic_streambuf >" = type { int (...)**, sbyte*, sbyte*, sbyte*, sbyte*, sbyte*, sbyte*, %struct.locale } + %struct.facet = type { int (...)**, int } + %struct.ios_base = type { int (...)**, long, long, uint, uint, uint, %struct._Callback_list*, %struct._Words, [8 x %struct._Words], int, %struct._Words*, %struct.locale } + %struct.locale = type { %struct._Impl* } + "struct.ostreambuf_iterator >" = type { "struct.basic_streambuf >"*, bool } + %llvm.dbg.compile_unit1047 = external global %llvm.dbg.compile_unit.type ; <%llvm.dbg.compile_unit.type*> [#uses=1] + + implementation ; Functions: + + void %_ZNKSt7num_putIcSt19ostreambuf_iteratorIcSt11char_traitsIcEEE15_M_insert_floatIdEES3_S3_RSt8ios_baseccT_() { + entry: + %tmp234 = seteq sbyte 0, 0 ; [#uses=1] + br bool %tmp234, label %cond_next243, label %cond_true235 + + cond_true235: ; preds = %entry + ret void + + cond_next243: ; preds = %entry + %tmp428 = load long* null ; [#uses=1] + %tmp428 = cast long %tmp428 to uint ; [#uses=1] + %tmp429 = alloca sbyte, uint %tmp428 ; [#uses=0] + call void %llvm.dbg.stoppoint( uint 1146, uint 0, { }* cast (%llvm.dbg.compile_unit.type* %llvm.dbg.compile_unit1047 to { }*) ) + unreachable + } + + declare void %llvm.dbg.stoppoint(uint, uint, { }*) From lattner at cs.uiuc.edu Tue Apr 4 12:39:30 2006 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Tue, 4 Apr 2006 12:39:30 -0500 Subject: [llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Message-ID: <200604041739.MAA15551@zion.cs.uiuc.edu> Changes in directory llvm/lib/CodeGen/SelectionDAG: DAGCombiner.cpp updated: 1.143 -> 1.144 --- Log message: Do not create ZEXTLOAD's unless we are before legalize or the operation is legal. --- Diffs of the changes: (+2 -1) DAGCombiner.cpp | 3 ++- 1 files changed, 2 insertions(+), 1 deletion(-) Index: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp diff -u llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.143 llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.144 --- llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.143 Mon Apr 3 12:29:28 2006 +++ llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Tue Apr 4 12:39:18 2006 @@ -1193,7 +1193,8 @@ LoadedVT = N0.getOpcode() == ISD::LOAD ? VT : cast(N0.getOperand(3))->getVT(); - if (EVT != MVT::Other && LoadedVT > EVT) { + if (EVT != MVT::Other && LoadedVT > EVT && + (!AfterLegalize || TLI.isOperationLegal(ISD::ZEXTLOAD, EVT))) { MVT::ValueType PtrType = N0.getOperand(1).getValueType(); // For big endian targets, we need to add an offset to the pointer to load // the correct bytes. For little endian systems, we merely need to read From lattner at cs.uiuc.edu Tue Apr 4 12:40:09 2006 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Tue, 4 Apr 2006 12:40:09 -0500 Subject: [llvm-commits] CVS: llvm/include/llvm/CodeGen/MachineFrameInfo.h Message-ID: <200604041740.MAA15596@zion.cs.uiuc.edu> Changes in directory llvm/include/llvm/CodeGen: MachineFrameInfo.h updated: 1.15 -> 1.16 --- Log message: Make sure to consider alignment of variable sized objects. This, along with the previous dag combiner fix, fixes CodeGen/Alpha/2006-04-04-zextload.ll --- Diffs of the changes: (+1 -0) MachineFrameInfo.h | 1 + 1 files changed, 1 insertion(+) Index: llvm/include/llvm/CodeGen/MachineFrameInfo.h diff -u llvm/include/llvm/CodeGen/MachineFrameInfo.h:1.15 llvm/include/llvm/CodeGen/MachineFrameInfo.h:1.16 --- llvm/include/llvm/CodeGen/MachineFrameInfo.h:1.15 Mon Apr 3 16:38:39 2006 +++ llvm/include/llvm/CodeGen/MachineFrameInfo.h Tue Apr 4 12:39:56 2006 @@ -225,6 +225,7 @@ /// int CreateVariableSizedObject() { HasVarSizedObjects = true; + if (MaxAlignment < 1) MaxAlignment = 1; Objects.push_back(StackObject(0, 1, -1)); return Objects.size()-NumFixedObjects-1; } From lattner at cs.uiuc.edu Tue Apr 4 13:25:21 2006 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Tue, 4 Apr 2006 13:25:21 -0500 Subject: [llvm-commits] CVS: llvm-www/pubs/2006-04-04-CGO-GraphColoring.html 2006-04-04-CGO-GraphColoring.pdf index.html Message-ID: <200604041825.NAA15932@zion.cs.uiuc.edu> Changes in directory llvm-www/pubs: 2006-04-04-CGO-GraphColoring.html added (r1.1) 2006-04-04-CGO-GraphColoring.pdf added (r1.1) index.html updated: 1.35 -> 1.36 --- Log message: Add a new paper that uses LLVM. --- Diffs of the changes: (+49 -0) 2006-04-04-CGO-GraphColoring.html | 47 ++++++++++++++++++++++++++++++++++++++ 2006-04-04-CGO-GraphColoring.pdf | 0 index.html | 2 + 3 files changed, 49 insertions(+) Index: llvm-www/pubs/2006-04-04-CGO-GraphColoring.html diff -c /dev/null llvm-www/pubs/2006-04-04-CGO-GraphColoring.html:1.1 *** /dev/null Tue Apr 4 13:25:19 2006 --- llvm-www/pubs/2006-04-04-CGO-GraphColoring.html Tue Apr 4 13:25:09 2006 *************** *** 0 **** --- 1,47 ---- + + + + + + Tailoring Graph-coloring Register Allocation For Runtime Compilation + + + +
+ Tailoring Graph-coloring Register Allocation For Runtime Compilation +
+
+ Keith D. Cooper and Anshuman Dasgupta +
+ +

Abstract:

+
+ Just-in-time compilers are invoked during application + execution and therefore need to ensure fast compilation + times. Consequently, runtime compiler designers are averse + to implementing compile-time intensive optimization algorithms. Instead, they tend to select faster but less effective + transformations. In this paper, we explore this trade-off for + an important optimization ???? global register allocation. We + present a graph-coloring register allocator that has been + redesigned for runtime compilation. Compared to Chaitin-Briggs [7], a standard graph-coloring technique, the reformulated algorithm requires considerably less allocation + time and produces allocations that are only marginally + worse than those of Chaitin-Briggs. Our experimental results indicate that the allocator performs better than the + linear-scan and Chaitin-Briggs allocators on most benchmarks in a runtime compilation environment. By increasing + allocation efficiency and preserving optimization quality, + the presented algorithm increases the suitability and profitability of a graph-coloring register allocation strategy for + a runtime compiler. +
+ +

Published:

+
+ "Tailoring Graph-coloring Register Allocation For Runtime Compilation", Keith D. Cooper and Anshuman Dasgupta.
+ Proceedings of the 2006 International Symposium on Code Generation and Optimization (CGO'06), New York, New York, 2006. +
+ +

Download:

+ + + + Index: llvm-www/pubs/2006-04-04-CGO-GraphColoring.pdf Index: llvm-www/pubs/index.html diff -u llvm-www/pubs/index.html:1.35 llvm-www/pubs/index.html:1.36 --- llvm-www/pubs/index.html:1.35 Fri Dec 16 12:33:09 2005 +++ llvm-www/pubs/index.html Tue Apr 4 13:25:09 2006 @@ -34,6 +34,8 @@
    +
  1. "Tailoring Graph-coloring Register Allocation For Runtime Compilation"
    Keith D. Cooper and Anshuman Dasgupta
    Proc. of the 2006 International Symposium on Code Generation and Optimization (CGO'06), New York, New York, 2006.
  2. +
  3. "How Successful is Data Structure Analysis in Isolating and Analyzing Linked Data Structures?"
    Patrick Meredith, Balpreet Pankaj, Swarup Sahoo, Chris Lattner and Vikram Adve
    Technical Report #UIUCDCS-R-2005-2658, Computer Science Dept., Univ. of Illinois, Dec. 2005.
  4. From evan.cheng at apple.com Tue Apr 4 13:37:55 2006 From: evan.cheng at apple.com (Evan Cheng) Date: Tue, 4 Apr 2006 13:37:55 -0500 Subject: [llvm-commits] CVS: llvm-test/SingleSource/UnitTests/Vector/SSE/sse.expandfft.c Message-ID: <200604041837.NAA15977@zion.cs.uiuc.edu> Changes in directory llvm-test/SingleSource/UnitTests/Vector/SSE: sse.expandfft.c updated: 1.1 -> 1.2 --- Log message: Eliminate timing printout. Dump more info for more meaningful comparison. --- Diffs of the changes: (+10 -6) sse.expandfft.c | 16 ++++++++++------ 1 files changed, 10 insertions(+), 6 deletions(-) Index: llvm-test/SingleSource/UnitTests/Vector/SSE/sse.expandfft.c diff -u llvm-test/SingleSource/UnitTests/Vector/SSE/sse.expandfft.c:1.1 llvm-test/SingleSource/UnitTests/Vector/SSE/sse.expandfft.c:1.2 --- llvm-test/SingleSource/UnitTests/Vector/SSE/sse.expandfft.c:1.1 Mon Apr 3 19:47:54 2006 +++ llvm-test/SingleSource/UnitTests/Vector/SSE/sse.expandfft.c Tue Apr 4 13:37:42 2006 @@ -65,18 +65,22 @@ printf(" for n=%d, fwd/bck error=%e\n",N,error); first = 0; } else { - t1 = ((float)clock())/((float) CLOCKS_PER_SEC); + unsigned j = 0; for(it=0;it<1000;it++){ sign = +1.0; cfft2(n,x,y,w,sign); sign = -1.0; cfft2(n,y,x,w,sign); } - t1 = ((float)clock())/((float) CLOCKS_PER_SEC) - t1; - t1 = t1/2000.0; - ln2 = 10.0; // reset this for different N - mflops = 5.0*((float) N)*ln2/((1.e+6)*t1); - printf(" for n=%d, t1=%e, mflops=%e\n",n,t1,mflops); + printf(" for n=%d\n",n); + for (i = 0; i Changes in directory llvm/lib/Target/X86: X86InstrSSE.td updated: 1.58 -> 1.59 --- Log message: PSHUF* encoding bugs. --- Diffs of the changes: (+6 -6) X86InstrSSE.td | 12 ++++++------ 1 files changed, 6 insertions(+), 6 deletions(-) Index: llvm/lib/Target/X86/X86InstrSSE.td diff -u llvm/lib/Target/X86/X86InstrSSE.td:1.58 llvm/lib/Target/X86/X86InstrSSE.td:1.59 --- llvm/lib/Target/X86/X86InstrSSE.td:1.58 Mon Apr 3 22:04:07 2006 +++ llvm/lib/Target/X86/X86InstrSSE.td Tue Apr 4 13:40:36 2006 @@ -1239,14 +1239,14 @@ } // Shuffle and unpack instructions -def PSHUFWrr : PSIi8<0x70, MRMDestReg, +def PSHUFWrr : PSIi8<0x70, MRMSrcReg, (ops VR64:$dst, VR64:$src1, i8imm:$src2), "pshufw {$src2, $src1, $dst|$dst, $src1, $src2}", []>; def PSHUFWrm : PSIi8<0x70, MRMSrcMem, (ops VR64:$dst, i64mem:$src1, i8imm:$src2), "pshufw {$src2, $src1, $dst|$dst, $src1, $src2}", []>; -def PSHUFDrr : PDIi8<0x70, MRMDestReg, +def PSHUFDrr : PDIi8<0x70, MRMSrcReg, (ops VR128:$dst, VR128:$src1, i8imm:$src2), "pshufd {$src2, $src1, $dst|$dst, $src1, $src2}", [(set VR128:$dst, (v4i32 (vector_shuffle @@ -1260,14 +1260,14 @@ PSHUFD_shuffle_mask:$src2)))]>; // SSE2 with ImmT == Imm8 and XS prefix. -def PSHUFHWrr : Ii8<0x70, MRMDestReg, +def PSHUFHWrr : Ii8<0x70, MRMSrcReg, (ops VR128:$dst, VR128:$src1, i8imm:$src2), "pshufhw {$src2, $src1, $dst|$dst, $src1, $src2}", [(set VR128:$dst, (v8i16 (vector_shuffle VR128:$src1, (undef), PSHUFHW_shuffle_mask:$src2)))]>, XS, Requires<[HasSSE2]>; -def PSHUFHWrm : Ii8<0x70, MRMDestMem, +def PSHUFHWrm : Ii8<0x70, MRMSrcMem, (ops VR128:$dst, i128mem:$src1, i8imm:$src2), "pshufhw {$src2, $src1, $dst|$dst, $src1, $src2}", [(set VR128:$dst, (v8i16 (vector_shuffle @@ -1276,14 +1276,14 @@ XS, Requires<[HasSSE2]>; // SSE2 with ImmT == Imm8 and XD prefix. -def PSHUFLWrr : Ii8<0x70, MRMDestReg, +def PSHUFLWrr : Ii8<0x70, MRMSrcReg, (ops VR128:$dst, VR128:$src1, i32i8imm:$src2), "pshuflw {$src2, $src1, $dst|$dst, $src1, $src2}", [(set VR128:$dst, (v8i16 (vector_shuffle VR128:$src1, (undef), PSHUFLW_shuffle_mask:$src2)))]>, XD, Requires<[HasSSE2]>; -def PSHUFLWrm : Ii8<0x70, MRMDestMem, +def PSHUFLWrm : Ii8<0x70, MRMSrcMem, (ops VR128:$dst, i128mem:$src1, i32i8imm:$src2), "pshuflw {$src2, $src1, $dst|$dst, $src1, $src2}", [(set VR128:$dst, (v8i16 (vector_shuffle From evan.cheng at apple.com Tue Apr 4 13:51:43 2006 From: evan.cheng at apple.com (Evan Cheng) Date: Tue, 4 Apr 2006 13:51:43 -0500 Subject: [llvm-commits] CVS: llvm-test/SingleSource/UnitTests/Vector/SSE/sse.expandfft.c Message-ID: <200604041851.NAA16045@zion.cs.uiuc.edu> Changes in directory llvm-test/SingleSource/UnitTests/Vector/SSE: sse.expandfft.c updated: 1.2 -> 1.3 --- Log message: Bump up the size of the test. --- Diffs of the changes: (+3 -3) sse.expandfft.c | 6 +++--- 1 files changed, 3 insertions(+), 3 deletions(-) Index: llvm-test/SingleSource/UnitTests/Vector/SSE/sse.expandfft.c diff -u llvm-test/SingleSource/UnitTests/Vector/SSE/sse.expandfft.c:1.2 llvm-test/SingleSource/UnitTests/Vector/SSE/sse.expandfft.c:1.3 --- llvm-test/SingleSource/UnitTests/Vector/SSE/sse.expandfft.c:1.2 Tue Apr 4 13:37:42 2006 +++ llvm-test/SingleSource/UnitTests/Vector/SSE/sse.expandfft.c Tue Apr 4 13:51:30 2006 @@ -3,7 +3,7 @@ #include #include #include "xmmintrin.h" -#define N 256 +#define N 1024 #define N2 N/2 main() { @@ -65,8 +65,8 @@ printf(" for n=%d, fwd/bck error=%e\n",N,error); first = 0; } else { - unsigned j = 0; - for(it=0;it<1000;it++){ + unsigned j = 0; + for(it=0;it<20000;it++){ sign = +1.0; cfft2(n,x,y,w,sign); sign = -1.0; From evan.cheng at apple.com Tue Apr 4 13:52:39 2006 From: evan.cheng at apple.com (Evan Cheng) Date: Tue, 4 Apr 2006 13:52:39 -0500 Subject: [llvm-commits] CVS: llvm-test/SingleSource/UnitTests/Vector/SSE/sse.stepfft.c Message-ID: <200604041852.NAA16067@zion.cs.uiuc.edu> Changes in directory llvm-test/SingleSource/UnitTests/Vector/SSE: sse.stepfft.c updated: 1.1 -> 1.2 --- Log message: - Remove calls to clock() and timing printfs. - Print out more data for comparisons. - Bump up the test size. --- Diffs of the changes: (+11 -7) sse.stepfft.c | 18 +++++++++++------- 1 files changed, 11 insertions(+), 7 deletions(-) Index: llvm-test/SingleSource/UnitTests/Vector/SSE/sse.stepfft.c diff -u llvm-test/SingleSource/UnitTests/Vector/SSE/sse.stepfft.c:1.1 llvm-test/SingleSource/UnitTests/Vector/SSE/sse.stepfft.c:1.2 --- llvm-test/SingleSource/UnitTests/Vector/SSE/sse.stepfft.c:1.1 Mon Apr 3 19:47:54 2006 +++ llvm-test/SingleSource/UnitTests/Vector/SSE/sse.stepfft.c Tue Apr 4 13:52:26 2006 @@ -63,18 +63,22 @@ printf(" for n=%d, fwd/bck error=%e\n",N,error); first = 0; } else { - t1 = ((float)clock())/((float) CLOCKS_PER_SEC); - for(it=0;it<10000;it++){ + unsigned j = 0; + for(it=0;it<20000;it++){ sign = +1.0; cfft2(n,x,y,w,sign); sign = -1.0; cfft2(n,y,x,w,sign); } - t1 = ((float)clock())/((float) CLOCKS_PER_SEC) - t1; - t1 = t1/20000.0; - ln2 = 10.0; /* reset this for different N */ - mflops = 5.0*((float) N)*ln2/((1.e+6)*t1); - printf(" for n=%d, t1=%e, mflops=%e\n",n,t1,mflops); + printf(" for n=%d\n",n); + for (i = 0; i Changes in directory llvm-test/SingleSource/UnitTests/Vector/Altivec: alti.expandfft.c updated: 1.2 -> 1.3 alti.stepfft.c updated: 1.2 -> 1.3 --- Log message: Remove calls to clock() and timing info printf's. --- Diffs of the changes: (+0 -11) alti.expandfft.c | 5 ----- alti.stepfft.c | 6 ------ 2 files changed, 11 deletions(-) Index: llvm-test/SingleSource/UnitTests/Vector/Altivec/alti.expandfft.c diff -u llvm-test/SingleSource/UnitTests/Vector/Altivec/alti.expandfft.c:1.2 llvm-test/SingleSource/UnitTests/Vector/Altivec/alti.expandfft.c:1.3 --- llvm-test/SingleSource/UnitTests/Vector/Altivec/alti.expandfft.c:1.2 Tue Apr 4 01:08:25 2006 +++ llvm-test/SingleSource/UnitTests/Vector/Altivec/alti.expandfft.c Tue Apr 4 13:56:15 2006 @@ -81,17 +81,12 @@ printf(" for n=%d, fwd/bck error=%e\n",n,error); first = 0; } else { - t1 = ((double)clock())/((double) CLOCKS_PER_SEC); for(it=0;it Changes in directory llvm/include/llvm: Type.h updated: 1.83 -> 1.84 --- Log message: How could this ever have worked? --- Diffs of the changes: (+1 -1) Type.h | 2 +- 1 files changed, 1 insertion(+), 1 deletion(-) Index: llvm/include/llvm/Type.h diff -u llvm/include/llvm/Type.h:1.83 llvm/include/llvm/Type.h:1.84 --- llvm/include/llvm/Type.h:1.83 Tue Feb 7 00:17:10 2006 +++ llvm/include/llvm/Type.h Tue Apr 4 14:05:42 2006 @@ -34,7 +34,7 @@ #ifndef LLVM_TYPE_H #define LLVM_TYPE_H -#include "AbstractTypeUser.h" +#include "llvm/AbstractTypeUser.h" #include "llvm/Support/Casting.h" #include "llvm/Support/DataTypes.h" #include "llvm/ADT/GraphTraits.h" From evan.cheng at apple.com Tue Apr 4 14:12:43 2006 From: evan.cheng at apple.com (Evan Cheng) Date: Tue, 4 Apr 2006 14:12:43 -0500 Subject: [llvm-commits] CVS: llvm/lib/Target/X86/X86InstrSSE.td X86RegisterInfo.cpp Message-ID: <200604041912.OAA16302@zion.cs.uiuc.edu> Changes in directory llvm/lib/Target/X86: X86InstrSSE.td updated: 1.59 -> 1.60 X86RegisterInfo.cpp updated: 1.133 -> 1.134 --- Log message: Minor fixes + naming changes. --- Diffs of the changes: (+157 -156) X86InstrSSE.td | 309 ++++++++++++++++++++++++++-------------------------- X86RegisterInfo.cpp | 4 2 files changed, 157 insertions(+), 156 deletions(-) Index: llvm/lib/Target/X86/X86InstrSSE.td diff -u llvm/lib/Target/X86/X86InstrSSE.td:1.59 llvm/lib/Target/X86/X86InstrSSE.td:1.60 --- llvm/lib/Target/X86/X86InstrSSE.td:1.59 Tue Apr 4 13:40:36 2006 +++ llvm/lib/Target/X86/X86InstrSSE.td Tue Apr 4 14:12:30 2006 @@ -335,45 +335,46 @@ [(set FR64:$dst, (fsub FR64:$src1, (loadf64 addr:$src2)))]>; } -def SQRTSSrr : SSI<0x51, MRMSrcReg, (ops FR32:$dst, FR32:$src), - "sqrtss {$src, $dst|$dst, $src}", - [(set FR32:$dst, (fsqrt FR32:$src))]>; -def SQRTSSrm : SSI<0x51, MRMSrcMem, (ops FR32:$dst, f32mem:$src), +def SQRTSSr : SSI<0x51, MRMSrcReg, (ops FR32:$dst, FR32:$src), + "sqrtss {$src, $dst|$dst, $src}", + [(set FR32:$dst, (fsqrt FR32:$src))]>; +def SQRTSSm : SSI<0x51, MRMSrcMem, (ops FR32:$dst, f32mem:$src), "sqrtss {$src, $dst|$dst, $src}", [(set FR32:$dst, (fsqrt (loadf32 addr:$src)))]>; -def SQRTSDrr : SDI<0x51, MRMSrcReg, (ops FR64:$dst, FR64:$src), +def SQRTSDr : SDI<0x51, MRMSrcReg, (ops FR64:$dst, FR64:$src), "sqrtsd {$src, $dst|$dst, $src}", [(set FR64:$dst, (fsqrt FR64:$src))]>; -def SQRTSDrm : SDI<0x51, MRMSrcMem, (ops FR64:$dst, f64mem:$src), +def SQRTSDm : SDI<0x51, MRMSrcMem, (ops FR64:$dst, f64mem:$src), "sqrtsd {$src, $dst|$dst, $src}", [(set FR64:$dst, (fsqrt (loadf64 addr:$src)))]>; -def RSQRTSSrr : SSI<0x52, MRMSrcReg, (ops FR32:$dst, FR32:$src), +def RSQRTSSr : SSI<0x52, MRMSrcReg, (ops FR32:$dst, FR32:$src), "rsqrtss {$src, $dst|$dst, $src}", []>; -def RSQRTSSrm : SSI<0x52, MRMSrcMem, (ops FR32:$dst, f32mem:$src), +def RSQRTSSm : SSI<0x52, MRMSrcMem, (ops FR32:$dst, f32mem:$src), "rsqrtss {$src, $dst|$dst, $src}", []>; -def RCPSSrr : SSI<0x53, MRMSrcReg, (ops FR32:$dst, FR32:$src), - "rcpss {$src, $dst|$dst, $src}", []>; -def RCPSSrm : SSI<0x53, MRMSrcMem, (ops FR32:$dst, f32mem:$src), - "rcpss {$src, $dst|$dst, $src}", []>; - -def MAXSSrr : SSI<0x5F, MRMSrcReg, (ops FR32:$dst, FR32:$src), - "maxss {$src, $dst|$dst, $src}", []>; -def MAXSSrm : SSI<0x5F, MRMSrcMem, (ops FR32:$dst, f32mem:$src), - "maxss {$src, $dst|$dst, $src}", []>; -def MAXSDrr : SDI<0x5F, MRMSrcReg, (ops FR64:$dst, FR64:$src), - "maxsd {$src, $dst|$dst, $src}", []>; -def MAXSDrm : SDI<0x5F, MRMSrcMem, (ops FR64:$dst, f64mem:$src), - "maxsd {$src, $dst|$dst, $src}", []>; -def MINSSrr : SSI<0x5D, MRMSrcReg, (ops FR32:$dst, FR32:$src), - "minss {$src, $dst|$dst, $src}", []>; -def MINSSrm : SSI<0x5D, MRMSrcMem, (ops FR32:$dst, f32mem:$src), - "minss {$src, $dst|$dst, $src}", []>; -def MINSDrr : SDI<0x5D, MRMSrcReg, (ops FR64:$dst, FR64:$src), - "minsd {$src, $dst|$dst, $src}", []>; -def MINSDrm : SDI<0x5D, MRMSrcMem, (ops FR64:$dst, f64mem:$src), - "minsd {$src, $dst|$dst, $src}", []>; +def RCPSSr : SSI<0x53, MRMSrcReg, (ops FR32:$dst, FR32:$src), + "rcpss {$src, $dst|$dst, $src}", []>; +def RCPSSm : SSI<0x53, MRMSrcMem, (ops FR32:$dst, f32mem:$src), + "rcpss {$src, $dst|$dst, $src}", []>; +let isTwoAddress = 1 in { +def MAXSSrr : SSI<0x5F, MRMSrcReg, (ops FR32:$dst, FR32:$src1, FR32:$src2), + "maxss {$src2, $dst|$dst, $src2}", []>; +def MAXSSrm : SSI<0x5F, MRMSrcMem, (ops FR32:$dst, FR32:$src1, f32mem:$src2), + "maxss {$src2, $dst|$dst, $src2}", []>; +def MAXSDrr : SDI<0x5F, MRMSrcReg, (ops FR64:$dst, FR32:$src1, FR64:$src2), + "maxsd {$src2, $dst|$dst, $src2}", []>; +def MAXSDrm : SDI<0x5F, MRMSrcMem, (ops FR64:$dst, FR32:$src1, f64mem:$src2), + "maxsd {$src2, $dst|$dst, $src2}", []>; +def MINSSrr : SSI<0x5D, MRMSrcReg, (ops FR32:$dst, FR32:$src1, FR32:$src2), + "minss {$src2, $dst|$dst, $src2}", []>; +def MINSSrm : SSI<0x5D, MRMSrcMem, (ops FR32:$dst, FR32:$src1, f32mem:$src2), + "minss {$src2, $dst|$dst, $src2}", []>; +def MINSDrr : SDI<0x5D, MRMSrcReg, (ops FR64:$dst, FR32:$src1, FR64:$src2), + "minsd {$src2, $dst|$dst, $src2}", []>; +def MINSDrm : SDI<0x5D, MRMSrcMem, (ops FR64:$dst, FR32:$src1, f64mem:$src2), + "minsd {$src2, $dst|$dst, $src2}", []>; +} // Aliases to match intrinsics which expect XMM operand(s). let isTwoAddress = 1 in { @@ -416,23 +417,23 @@ int_x86_sse2_sub_sd>; } -def Int_SQRTSSrr : SS_Intr<0x51, "sqrtss {$src, $dst|$dst, $src}", - int_x86_sse_sqrt_ss>; -def Int_SQRTSSrm : SS_Intm<0x51, "sqrtss {$src, $dst|$dst, $src}", - int_x86_sse_sqrt_ss>; -def Int_SQRTSDrr : SD_Intr<0x51, "sqrtsd {$src, $dst|$dst, $src}", - int_x86_sse2_sqrt_sd>; -def Int_SQRTSDrm : SD_Intm<0x51, "sqrtsd {$src, $dst|$dst, $src}", - int_x86_sse2_sqrt_sd>; - -def Int_RSQRTSSrr : SS_Intr<0x52, "rsqrtss {$src, $dst|$dst, $src}", - int_x86_sse_rsqrt_ss>; -def Int_RSQRTSSrm : SS_Intm<0x52, "rsqrtss {$src, $dst|$dst, $src}", - int_x86_sse_rsqrt_ss>; -def Int_RCPSSrr : SS_Intr<0x53, "rcpss {$src, $dst|$dst, $src}", - int_x86_sse_rcp_ss>; -def Int_RCPSSrm : SS_Intm<0x53, "rcpss {$src, $dst|$dst, $src}", - int_x86_sse_rcp_ss>; +def Int_SQRTSSr : SS_Intr<0x51, "sqrtss {$src, $dst|$dst, $src}", + int_x86_sse_sqrt_ss>; +def Int_SQRTSSm : SS_Intm<0x51, "sqrtss {$src, $dst|$dst, $src}", + int_x86_sse_sqrt_ss>; +def Int_SQRTSDr : SD_Intr<0x51, "sqrtsd {$src, $dst|$dst, $src}", + int_x86_sse2_sqrt_sd>; +def Int_SQRTSDm : SD_Intm<0x51, "sqrtsd {$src, $dst|$dst, $src}", + int_x86_sse2_sqrt_sd>; + +def Int_RSQRTSSr : SS_Intr<0x52, "rsqrtss {$src, $dst|$dst, $src}", + int_x86_sse_rsqrt_ss>; +def Int_RSQRTSSm : SS_Intm<0x52, "rsqrtss {$src, $dst|$dst, $src}", + int_x86_sse_rsqrt_ss>; +def Int_RCPSSr : SS_Intr<0x53, "rcpss {$src, $dst|$dst, $src}", + int_x86_sse_rcp_ss>; +def Int_RCPSSm : SS_Intm<0x53, "rcpss {$src, $dst|$dst, $src}", + int_x86_sse_rcp_ss>; let isTwoAddress = 1 in { def Int_MAXSSrr : SS_Intrr<0x5F, "maxss {$src2, $dst|$dst, $src2}", @@ -460,43 +461,43 @@ "cvtss2si {$src, $dst|$dst, $src}", []>; def CVTTSS2SIrr: SSI<0x2C, MRMSrcReg, (ops R32:$dst, FR32:$src), - "cvttss2si {$src, $dst|$dst, $src}", - [(set R32:$dst, (fp_to_sint FR32:$src))]>; + "cvttss2si {$src, $dst|$dst, $src}", + [(set R32:$dst, (fp_to_sint FR32:$src))]>; def CVTTSS2SIrm: SSI<0x2C, MRMSrcMem, (ops R32:$dst, f32mem:$src), - "cvttss2si {$src, $dst|$dst, $src}", - [(set R32:$dst, (fp_to_sint (loadf32 addr:$src)))]>; + "cvttss2si {$src, $dst|$dst, $src}", + [(set R32:$dst, (fp_to_sint (loadf32 addr:$src)))]>; def CVTTSD2SIrr: SDI<0x2C, MRMSrcReg, (ops R32:$dst, FR64:$src), - "cvttsd2si {$src, $dst|$dst, $src}", - [(set R32:$dst, (fp_to_sint FR64:$src))]>; + "cvttsd2si {$src, $dst|$dst, $src}", + [(set R32:$dst, (fp_to_sint FR64:$src))]>; def CVTTSD2SIrm: SDI<0x2C, MRMSrcMem, (ops R32:$dst, f64mem:$src), - "cvttsd2si {$src, $dst|$dst, $src}", - [(set R32:$dst, (fp_to_sint (loadf64 addr:$src)))]>; + "cvttsd2si {$src, $dst|$dst, $src}", + [(set R32:$dst, (fp_to_sint (loadf64 addr:$src)))]>; def CVTSD2SSrr: SDI<0x5A, MRMSrcReg, (ops FR32:$dst, FR64:$src), - "cvtsd2ss {$src, $dst|$dst, $src}", - [(set FR32:$dst, (fround FR64:$src))]>; + "cvtsd2ss {$src, $dst|$dst, $src}", + [(set FR32:$dst, (fround FR64:$src))]>; def CVTSD2SSrm: SDI<0x5A, MRMSrcMem, (ops FR32:$dst, f64mem:$src), - "cvtsd2ss {$src, $dst|$dst, $src}", - [(set FR32:$dst, (fround (loadf64 addr:$src)))]>; + "cvtsd2ss {$src, $dst|$dst, $src}", + [(set FR32:$dst, (fround (loadf64 addr:$src)))]>; def CVTSI2SSrr: SSI<0x2A, MRMSrcReg, (ops FR32:$dst, R32:$src), "cvtsi2ss {$src, $dst|$dst, $src}", [(set FR32:$dst, (sint_to_fp R32:$src))]>; def CVTSI2SSrm: SSI<0x2A, MRMSrcMem, (ops FR32:$dst, i32mem:$src), - "cvtsi2ss {$src, $dst|$dst, $src}", - [(set FR32:$dst, (sint_to_fp (loadi32 addr:$src)))]>; + "cvtsi2ss {$src, $dst|$dst, $src}", + [(set FR32:$dst, (sint_to_fp (loadi32 addr:$src)))]>; def CVTSI2SDrr: SDI<0x2A, MRMSrcReg, (ops FR64:$dst, R32:$src), - "cvtsi2sd {$src, $dst|$dst, $src}", - [(set FR64:$dst, (sint_to_fp R32:$src))]>; + "cvtsi2sd {$src, $dst|$dst, $src}", + [(set FR64:$dst, (sint_to_fp R32:$src))]>; def CVTSI2SDrm: SDI<0x2A, MRMSrcMem, (ops FR64:$dst, i32mem:$src), - "cvtsi2sd {$src, $dst|$dst, $src}", - [(set FR64:$dst, (sint_to_fp (loadi32 addr:$src)))]>; + "cvtsi2sd {$src, $dst|$dst, $src}", + [(set FR64:$dst, (sint_to_fp (loadi32 addr:$src)))]>; // SSE2 instructions with XS prefix def CVTSS2SDrr: I<0x5A, MRMSrcReg, (ops FR64:$dst, FR32:$src), - "cvtss2sd {$src, $dst|$dst, $src}", - [(set FR64:$dst, (fextend FR32:$src))]>, XS, + "cvtss2sd {$src, $dst|$dst, $src}", + [(set FR64:$dst, (fextend FR32:$src))]>, XS, Requires<[HasSSE2]>; def CVTSS2SDrm: I<0x5A, MRMSrcMem, (ops FR64:$dst, f32mem:$src), - "cvtss2sd {$src, $dst|$dst, $src}", - [(set FR64:$dst, (fextend (loadf32 addr:$src)))]>, XS, + "cvtss2sd {$src, $dst|$dst, $src}", + [(set FR64:$dst, (fextend (loadf32 addr:$src)))]>, XS, Requires<[HasSSE2]>; // Comparison instructions @@ -717,62 +718,62 @@ } // Conversion instructions -def CVTPI2PSrr : PSI<0x2A, MRMSrcReg, (ops VR128:$dst, VR64:$src), - "cvtpi2ps {$src, $dst|$dst, $src}", []>; -def CVTPI2PSrm : PSI<0x2A, MRMSrcMem, (ops VR128:$dst, i64mem:$src), - "cvtpi2ps {$src, $dst|$dst, $src}", []>; -def CVTPI2PDrr : PDI<0x2A, MRMSrcReg, (ops VR128:$dst, VR64:$src), - "cvtpi2pd {$src, $dst|$dst, $src}", []>; -def CVTPI2PDrm : PDI<0x2A, MRMSrcMem, (ops VR128:$dst, i64mem:$src), - "cvtpi2pd {$src, $dst|$dst, $src}", []>; +def CVTPI2PSr : PSI<0x2A, MRMSrcReg, (ops VR128:$dst, VR64:$src), + "cvtpi2ps {$src, $dst|$dst, $src}", []>; +def CVTPI2PSm : PSI<0x2A, MRMSrcMem, (ops VR128:$dst, i64mem:$src), + "cvtpi2ps {$src, $dst|$dst, $src}", []>; +def CVTPI2PDr : PDI<0x2A, MRMSrcReg, (ops VR128:$dst, VR64:$src), + "cvtpi2pd {$src, $dst|$dst, $src}", []>; +def CVTPI2PDm : PDI<0x2A, MRMSrcMem, (ops VR128:$dst, i64mem:$src), + "cvtpi2pd {$src, $dst|$dst, $src}", []>; // SSE2 instructions without OpSize prefix -def CVTDQ2PSrr : I<0x5B, MRMSrcReg, (ops VR128:$dst, VR128:$src), - "cvtdq2ps {$src, $dst|$dst, $src}", []>, TB, - Requires<[HasSSE2]>; -def CVTDQ2PSrm : I<0x5B, MRMSrcMem, (ops VR128:$dst, i128mem:$src), - "cvtdq2ps {$src, $dst|$dst, $src}", []>, TB, - Requires<[HasSSE2]>; +def CVTDQ2PSr : I<0x5B, MRMSrcReg, (ops VR128:$dst, VR128:$src), + "cvtdq2ps {$src, $dst|$dst, $src}", []>, TB, + Requires<[HasSSE2]>; +def CVTDQ2PSm : I<0x5B, MRMSrcMem, (ops VR128:$dst, i128mem:$src), + "cvtdq2ps {$src, $dst|$dst, $src}", []>, TB, + Requires<[HasSSE2]>; // SSE2 instructions with XS prefix -def CVTDQ2PDrr : I<0xE6, MRMSrcReg, (ops VR128:$dst, VR64:$src), - "cvtdq2pd {$src, $dst|$dst, $src}", []>, - XS, Requires<[HasSSE2]>; -def CVTDQ2PDrm : I<0xE6, MRMSrcMem, (ops VR128:$dst, i64mem:$src), - "cvtdq2pd {$src, $dst|$dst, $src}", []>, - XS, Requires<[HasSSE2]>; +def CVTDQ2PDr : I<0xE6, MRMSrcReg, (ops VR128:$dst, VR64:$src), + "cvtdq2pd {$src, $dst|$dst, $src}", []>, + XS, Requires<[HasSSE2]>; +def CVTDQ2PDm : I<0xE6, MRMSrcMem, (ops VR128:$dst, i64mem:$src), + "cvtdq2pd {$src, $dst|$dst, $src}", []>, + XS, Requires<[HasSSE2]>; -def CVTPS2PIrr : PSI<0x2D, MRMSrcReg, (ops VR64:$dst, VR128:$src), +def CVTPS2PIr : PSI<0x2D, MRMSrcReg, (ops VR64:$dst, VR128:$src), "cvtps2pi {$src, $dst|$dst, $src}", []>; -def CVTPS2PIrm : PSI<0x2D, MRMSrcMem, (ops VR64:$dst, f64mem:$src), +def CVTPS2PIm : PSI<0x2D, MRMSrcMem, (ops VR64:$dst, f64mem:$src), "cvtps2pi {$src, $dst|$dst, $src}", []>; -def CVTPD2PIrr : PDI<0x2D, MRMSrcReg, (ops VR64:$dst, VR128:$src), +def CVTPD2PIr : PDI<0x2D, MRMSrcReg, (ops VR64:$dst, VR128:$src), "cvtpd2pi {$src, $dst|$dst, $src}", []>; -def CVTPD2PIrm : PDI<0x2D, MRMSrcMem, (ops VR64:$dst, f128mem:$src), +def CVTPD2PIm : PDI<0x2D, MRMSrcMem, (ops VR64:$dst, f128mem:$src), "cvtpd2pi {$src, $dst|$dst, $src}", []>; -def CVTPS2DQrr : PDI<0x5B, MRMSrcReg, (ops VR128:$dst, VR128:$src), - "cvtps2dq {$src, $dst|$dst, $src}", []>; -def CVTPS2DQrm : PDI<0x5B, MRMSrcMem, (ops VR128:$dst, f128mem:$src), - "cvtps2dq {$src, $dst|$dst, $src}", []>; +def CVTPS2DQr : PDI<0x5B, MRMSrcReg, (ops VR128:$dst, VR128:$src), + "cvtps2dq {$src, $dst|$dst, $src}", []>; +def CVTPS2DQm : PDI<0x5B, MRMSrcMem, (ops VR128:$dst, f128mem:$src), + "cvtps2dq {$src, $dst|$dst, $src}", []>; // SSE2 packed instructions with XD prefix -def CVTPD2DQrr : SDI<0xE6, MRMSrcReg, (ops VR128:$dst, VR128:$src), - "cvtpd2dq {$src, $dst|$dst, $src}", []>; -def CVTPD2DQrm : SDI<0xE6, MRMSrcMem, (ops VR128:$dst, f128mem:$src), - "cvtpd2dq {$src, $dst|$dst, $src}", []>; +def CVTPD2DQr : SDI<0xE6, MRMSrcReg, (ops VR128:$dst, VR128:$src), + "cvtpd2dq {$src, $dst|$dst, $src}", []>; +def CVTPD2DQm : SDI<0xE6, MRMSrcMem, (ops VR128:$dst, f128mem:$src), + "cvtpd2dq {$src, $dst|$dst, $src}", []>; // SSE2 instructions without OpSize prefix -def CVTPS2PDrr : I<0x5A, MRMSrcReg, (ops VR128:$dst, VR128:$src), - "cvtps2pd {$src, $dst|$dst, $src}", []>, TB, - Requires<[HasSSE2]>; -def CVTPS2PDrm : I<0x5A, MRMSrcReg, (ops VR128:$dst, f64mem:$src), - "cvtps2pd {$src, $dst|$dst, $src}", []>, TB, - Requires<[HasSSE2]>; - -def CVTPD2PSrr : PDI<0x5A, MRMSrcReg, (ops VR128:$dst, VR128:$src), - "cvtpd2ps {$src, $dst|$dst, $src}", []>; -def CVTPD2PSrm : PDI<0x5A, MRMSrcReg, (ops VR128:$dst, f128mem:$src), - "cvtpd2ps {$src, $dst|$dst, $src}", []>; +def CVTPS2PDr : I<0x5A, MRMSrcReg, (ops VR128:$dst, VR128:$src), + "cvtps2pd {$src, $dst|$dst, $src}", []>, TB, + Requires<[HasSSE2]>; +def CVTPS2PDm : I<0x5A, MRMSrcReg, (ops VR128:$dst, f64mem:$src), + "cvtps2pd {$src, $dst|$dst, $src}", []>, TB, + Requires<[HasSSE2]>; + +def CVTPD2PSr : PDI<0x5A, MRMSrcReg, (ops VR128:$dst, VR128:$src), + "cvtpd2ps {$src, $dst|$dst, $src}", []>; +def CVTPD2PSm : PDI<0x5A, MRMSrcReg, (ops VR128:$dst, f128mem:$src), + "cvtpd2ps {$src, $dst|$dst, $src}", []>; // Arithmetic let isTwoAddress = 1 in { @@ -839,23 +840,23 @@ (load addr:$src2))))]>; } -def SQRTPSrr : PS_Intr<0x51, "sqrtps {$src, $dst|$dst, $src}", - int_x86_sse_sqrt_ps>; -def SQRTPSrm : PS_Intm<0x51, "sqrtps {$src, $dst|$dst, $src}", - int_x86_sse_sqrt_ps>; -def SQRTPDrr : PD_Intr<0x51, "sqrtpd {$src, $dst|$dst, $src}", - int_x86_sse2_sqrt_pd>; -def SQRTPDrm : PD_Intm<0x51, "sqrtpd {$src, $dst|$dst, $src}", - int_x86_sse2_sqrt_pd>; - -def RSQRTPSrr : PS_Intr<0x52, "rsqrtps {$src, $dst|$dst, $src}", - int_x86_sse_rsqrt_ps>; -def RSQRTPSrm : PS_Intm<0x52, "rsqrtps {$src, $dst|$dst, $src}", - int_x86_sse_rsqrt_ps>; -def RCPPSrr : PS_Intr<0x53, "rcpps {$src, $dst|$dst, $src}", - int_x86_sse_rcp_ps>; -def RCPPSrm : PS_Intm<0x53, "rcpps {$src, $dst|$dst, $src}", - int_x86_sse_rcp_ps>; +def SQRTPSr : PS_Intr<0x51, "sqrtps {$src, $dst|$dst, $src}", + int_x86_sse_sqrt_ps>; +def SQRTPSm : PS_Intm<0x51, "sqrtps {$src, $dst|$dst, $src}", + int_x86_sse_sqrt_ps>; +def SQRTPDr : PD_Intr<0x51, "sqrtpd {$src, $dst|$dst, $src}", + int_x86_sse2_sqrt_pd>; +def SQRTPDm : PD_Intm<0x51, "sqrtpd {$src, $dst|$dst, $src}", + int_x86_sse2_sqrt_pd>; + +def RSQRTPSr : PS_Intr<0x52, "rsqrtps {$src, $dst|$dst, $src}", + int_x86_sse_rsqrt_ps>; +def RSQRTPSm : PS_Intm<0x52, "rsqrtps {$src, $dst|$dst, $src}", + int_x86_sse_rsqrt_ps>; +def RCPPSr : PS_Intr<0x53, "rcpps {$src, $dst|$dst, $src}", + int_x86_sse_rcp_ps>; +def RCPPSm : PS_Intm<0x53, "rcpps {$src, $dst|$dst, $src}", + int_x86_sse_rcp_ps>; let isTwoAddress = 1 in { def MAXPSrr : PS_Intrr<0x5F, "maxps {$src2, $dst|$dst, $src2}", @@ -1239,20 +1240,20 @@ } // Shuffle and unpack instructions -def PSHUFWrr : PSIi8<0x70, MRMSrcReg, +def PSHUFWri : PSIi8<0x70, MRMSrcReg, (ops VR64:$dst, VR64:$src1, i8imm:$src2), "pshufw {$src2, $src1, $dst|$dst, $src1, $src2}", []>; -def PSHUFWrm : PSIi8<0x70, MRMSrcMem, +def PSHUFWmi : PSIi8<0x70, MRMSrcMem, (ops VR64:$dst, i64mem:$src1, i8imm:$src2), "pshufw {$src2, $src1, $dst|$dst, $src1, $src2}", []>; -def PSHUFDrr : PDIi8<0x70, MRMSrcReg, +def PSHUFDri : PDIi8<0x70, MRMSrcReg, (ops VR128:$dst, VR128:$src1, i8imm:$src2), "pshufd {$src2, $src1, $dst|$dst, $src1, $src2}", [(set VR128:$dst, (v4i32 (vector_shuffle VR128:$src1, (undef), PSHUFD_shuffle_mask:$src2)))]>; -def PSHUFDrm : PDIi8<0x70, MRMSrcMem, +def PSHUFDmi : PDIi8<0x70, MRMSrcMem, (ops VR128:$dst, i128mem:$src1, i8imm:$src2), "pshufd {$src2, $src1, $dst|$dst, $src1, $src2}", [(set VR128:$dst, (v4i32 (vector_shuffle @@ -1260,14 +1261,14 @@ PSHUFD_shuffle_mask:$src2)))]>; // SSE2 with ImmT == Imm8 and XS prefix. -def PSHUFHWrr : Ii8<0x70, MRMSrcReg, +def PSHUFHWri : Ii8<0x70, MRMSrcReg, (ops VR128:$dst, VR128:$src1, i8imm:$src2), "pshufhw {$src2, $src1, $dst|$dst, $src1, $src2}", [(set VR128:$dst, (v8i16 (vector_shuffle VR128:$src1, (undef), PSHUFHW_shuffle_mask:$src2)))]>, XS, Requires<[HasSSE2]>; -def PSHUFHWrm : Ii8<0x70, MRMSrcMem, +def PSHUFHWmi : Ii8<0x70, MRMSrcMem, (ops VR128:$dst, i128mem:$src1, i8imm:$src2), "pshufhw {$src2, $src1, $dst|$dst, $src1, $src2}", [(set VR128:$dst, (v8i16 (vector_shuffle @@ -1276,14 +1277,14 @@ XS, Requires<[HasSSE2]>; // SSE2 with ImmT == Imm8 and XD prefix. -def PSHUFLWrr : Ii8<0x70, MRMSrcReg, +def PSHUFLWri : Ii8<0x70, MRMSrcReg, (ops VR128:$dst, VR128:$src1, i32i8imm:$src2), "pshuflw {$src2, $src1, $dst|$dst, $src1, $src2}", [(set VR128:$dst, (v8i16 (vector_shuffle VR128:$src1, (undef), PSHUFLW_shuffle_mask:$src2)))]>, XD, Requires<[HasSSE2]>; -def PSHUFLWrm : Ii8<0x70, MRMSrcMem, +def PSHUFLWmi : Ii8<0x70, MRMSrcMem, (ops VR128:$dst, i128mem:$src1, i32i8imm:$src2), "pshuflw {$src2, $src1, $dst|$dst, $src1, $src2}", [(set VR128:$dst, (v8i16 (vector_shuffle @@ -1392,24 +1393,24 @@ } // Extract / Insert -def PEXTRWrr : PDIi8<0xC5, MRMSrcReg, - (ops R32:$dst, VR128:$src1, i32i8imm:$src2), - "pextrw {$src2, $src1, $dst|$dst, $src1, $src2}", - [(set R32:$dst, (X86pextrw (v8i16 VR128:$src1), - (i32 imm:$src2)))]>; -def PEXTRWrm : PDIi8<0xC5, MRMSrcMem, - (ops R32:$dst, i128mem:$src1, i32i8imm:$src2), - "pextrw {$src2, $src1, $dst|$dst, $src1, $src2}", - [(set R32:$dst, (X86pextrw (loadv8i16 addr:$src1), - (i32 imm:$src2)))]>; +def PEXTRWr : PDIi8<0xC5, MRMSrcReg, + (ops R32:$dst, VR128:$src1, i32i8imm:$src2), + "pextrw {$src2, $src1, $dst|$dst, $src1, $src2}", + [(set R32:$dst, (X86pextrw (v8i16 VR128:$src1), + (i32 imm:$src2)))]>; +def PEXTRWm : PDIi8<0xC5, MRMSrcMem, + (ops R32:$dst, i128mem:$src1, i32i8imm:$src2), + "pextrw {$src2, $src1, $dst|$dst, $src1, $src2}", + [(set R32:$dst, (X86pextrw (loadv8i16 addr:$src1), + (i32 imm:$src2)))]>; let isTwoAddress = 1 in { -def PINSRWrr : PDIi8<0xC4, MRMSrcReg, +def PINSRWr : PDIi8<0xC4, MRMSrcReg, (ops VR128:$dst, VR128:$src1, R32:$src2, i32i8imm:$src3), "pinsrw {$src3, $src2, $dst|$dst, $src2, $src3}", [(set VR128:$dst, (v8i16 (X86pinsrw (v8i16 VR128:$src1), R32:$src2, (i32 imm:$src3))))]>; -def PINSRWrm : PDIi8<0xC4, MRMSrcMem, +def PINSRWm : PDIi8<0xC4, MRMSrcMem, (ops VR128:$dst, VR128:$src1, i16mem:$src2, i32i8imm:$src3), "pinsrw {$src3, $src2, $dst|$dst, $src2, $src3}", [(set VR128:$dst, @@ -1697,27 +1698,27 @@ // Shuffle v4f32 with PSHUF* if others do not match. def : Pat<(vector_shuffle (v4f32 VR128:$src1), (undef), PSHUFD_fp_shuffle_mask:$sm), - (v4f32 (PSHUFDrr VR128:$src1, PSHUFD_fp_shuffle_mask:$sm))>, + (v4f32 (PSHUFDri VR128:$src1, PSHUFD_fp_shuffle_mask:$sm))>, Requires<[HasSSE2]>; def : Pat<(vector_shuffle (loadv4f32 addr:$src1), (undef), PSHUFD_fp_shuffle_mask:$sm), - (v4f32 (PSHUFDrm addr:$src1, PSHUFD_fp_shuffle_mask:$sm))>, + (v4f32 (PSHUFDmi addr:$src1, PSHUFD_fp_shuffle_mask:$sm))>, Requires<[HasSSE2]>; def : Pat<(vector_shuffle (v4f32 VR128:$src1), (undef), PSHUFHW_fp_shuffle_mask:$sm), - (v4f32 (PSHUFHWrr VR128:$src1, PSHUFHW_fp_shuffle_mask:$sm))>, + (v4f32 (PSHUFHWri VR128:$src1, PSHUFHW_fp_shuffle_mask:$sm))>, Requires<[HasSSE2]>; def : Pat<(vector_shuffle (loadv4f32 addr:$src1), (undef), PSHUFHW_fp_shuffle_mask:$sm), - (v4f32 (PSHUFHWrm addr:$src1, PSHUFHW_fp_shuffle_mask:$sm))>, + (v4f32 (PSHUFHWmi addr:$src1, PSHUFHW_fp_shuffle_mask:$sm))>, Requires<[HasSSE2]>; def : Pat<(vector_shuffle (v4f32 VR128:$src1), (undef), PSHUFLW_fp_shuffle_mask:$sm), - (v4f32 (PSHUFLWrr VR128:$src1, PSHUFLW_fp_shuffle_mask:$sm))>, + (v4f32 (PSHUFLWri VR128:$src1, PSHUFLW_fp_shuffle_mask:$sm))>, Requires<[HasSSE2]>; def : Pat<(vector_shuffle (loadv4f32 addr:$src1), (undef), PSHUFLW_fp_shuffle_mask:$sm), - (v4f32 (PSHUFLWrm addr:$src1, PSHUFLW_fp_shuffle_mask:$sm))>, + (v4f32 (PSHUFLWmi addr:$src1, PSHUFLW_fp_shuffle_mask:$sm))>, Requires<[HasSSE2]>; // Logical ops Index: llvm/lib/Target/X86/X86RegisterInfo.cpp diff -u llvm/lib/Target/X86/X86RegisterInfo.cpp:1.133 llvm/lib/Target/X86/X86RegisterInfo.cpp:1.134 --- llvm/lib/Target/X86/X86RegisterInfo.cpp:1.133 Tue Mar 28 07:48:33 2006 +++ llvm/lib/Target/X86/X86RegisterInfo.cpp Tue Apr 4 14:12:30 2006 @@ -429,8 +429,8 @@ case X86::CVTSD2SSrr:return MakeRMInst(X86::CVTSD2SSrm, FrameIndex, MI); case X86::CVTSI2SSrr:return MakeRMInst(X86::CVTSI2SSrm, FrameIndex, MI); case X86::CVTSI2SDrr:return MakeRMInst(X86::CVTSI2SDrm, FrameIndex, MI); - case X86::SQRTSSrr: return MakeRMInst(X86::SQRTSSrm, FrameIndex, MI); - case X86::SQRTSDrr: return MakeRMInst(X86::SQRTSDrm, FrameIndex, MI); + case X86::SQRTSSr: return MakeRMInst(X86::SQRTSSm, FrameIndex, MI); + case X86::SQRTSDr: return MakeRMInst(X86::SQRTSDm, FrameIndex, MI); case X86::UCOMISSrr: return MakeRMInst(X86::UCOMISSrm, FrameIndex, MI); case X86::UCOMISDrr: return MakeRMInst(X86::UCOMISDrm, FrameIndex, MI); case X86::ADDSSrr: return MakeRMInst(X86::ADDSSrm, FrameIndex, MI); From evan.cheng at apple.com Tue Apr 4 16:48:43 2006 From: evan.cheng at apple.com (Evan Cheng) Date: Tue, 4 Apr 2006 16:48:43 -0500 Subject: [llvm-commits] CVS: llvm/include/llvm/Intrinsics.td IntrinsicsX86.td Message-ID: <200604042148.QAA17141@zion.cs.uiuc.edu> Changes in directory llvm/include/llvm: Intrinsics.td updated: 1.31 -> 1.32 IntrinsicsX86.td updated: 1.8 -> 1.9 --- Log message: Added intrinsics to match __builtin_ia32_pslldqi128 and __builtin_ia32_psrldqi128. --- Diffs of the changes: (+11 -0) Intrinsics.td | 1 + IntrinsicsX86.td | 10 ++++++++++ 2 files changed, 11 insertions(+) Index: llvm/include/llvm/Intrinsics.td diff -u llvm/include/llvm/Intrinsics.td:1.31 llvm/include/llvm/Intrinsics.td:1.32 --- llvm/include/llvm/Intrinsics.td:1.31 Mon Mar 27 18:15:44 2006 +++ llvm/include/llvm/Intrinsics.td Tue Apr 4 16:48:31 2006 @@ -82,6 +82,7 @@ def llvm_v16i8_ty : LLVMPackedType; // 16 x sbyte def llvm_v8i16_ty : LLVMPackedType; // 8 x short +def llvm_v2i64_ty : LLVMPackedType; // 2 x long def llvm_v2i32_ty : LLVMPackedType; // 2 x int def llvm_v4i32_ty : LLVMPackedType; // 4 x int def llvm_v4f32_ty : LLVMPackedType; // 4 x float Index: llvm/include/llvm/IntrinsicsX86.td diff -u llvm/include/llvm/IntrinsicsX86.td:1.8 llvm/include/llvm/IntrinsicsX86.td:1.9 --- llvm/include/llvm/IntrinsicsX86.td:1.8 Fri Mar 31 15:28:46 2006 +++ llvm/include/llvm/IntrinsicsX86.td Tue Apr 4 16:48:31 2006 @@ -183,6 +183,16 @@ llvm_v2f64_ty], [InstrNoMem]>; } +// Integer shift ops. +let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.". + def int_x86_sse2_psll_dq : GCCBuiltin<"__builtin_ia32_pslldqi128">, + Intrinsic<[llvm_v2i64_ty, llvm_v2i64_ty, + llvm_int_ty], [InstrNoMem]>; + def int_x86_sse2_psrl_dq : GCCBuiltin<"__builtin_ia32_psrldqi128">, + Intrinsic<[llvm_v2i64_ty, llvm_v2i64_ty, + llvm_int_ty], [InstrNoMem]>; +} + // Misc. let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.". def int_x86_sse2_packsswb_128 : GCCBuiltin<"__builtin_ia32_packsswb128">, From evan.cheng at apple.com Tue Apr 4 16:49:52 2006 From: evan.cheng at apple.com (Evan Cheng) Date: Tue, 4 Apr 2006 16:49:52 -0500 Subject: [llvm-commits] CVS: llvm/lib/Target/X86/X86InstrSSE.td Message-ID: <200604042149.QAA17160@zion.cs.uiuc.edu> Changes in directory llvm/lib/Target/X86: X86InstrSSE.td updated: 1.60 -> 1.61 --- Log message: Added pslldq and psrldq. --- Diffs of the changes: (+18 -0) X86InstrSSE.td | 18 ++++++++++++++++++ 1 files changed, 18 insertions(+) Index: llvm/lib/Target/X86/X86InstrSSE.td diff -u llvm/lib/Target/X86/X86InstrSSE.td:1.60 llvm/lib/Target/X86/X86InstrSSE.td:1.61 --- llvm/lib/Target/X86/X86InstrSSE.td:1.60 Tue Apr 4 14:12:30 2006 +++ llvm/lib/Target/X86/X86InstrSSE.td Tue Apr 4 16:49:39 2006 @@ -57,6 +57,11 @@ return N->isExactlyValue(+0.0); }]>; +def PSxLDQ_imm : SDNodeXForm> 3 + return getI32Imm(N->getValue() >> 3); +}]>; + // SHUFFLE_get_shuf_imm xform function: convert vector_shuffle mask to PSHUF*, // SHUFP* etc. imm. def SHUFFLE_get_shuf_imm : SDNodeXForm; } +let isTwoAddress = 1 in { +def PSLLDQri : PDIi8<0x73, MRM7r, (ops VR128:$dst, VR128:$src1, i32i8imm:$src2), + "pslldq {$src2, $dst|$dst, $src2}", []>; +def PSRLDQri : PDIi8<0x73, MRM7r, (ops VR128:$dst, VR128:$src1, i32i8imm:$src2), + "psrldq {$src2, $dst|$dst, $src2}", []>; +} + // Logical let isTwoAddress = 1 in { let isCommutable = 1 in { @@ -1721,6 +1733,12 @@ (v4f32 (PSHUFLWmi addr:$src1, PSHUFLW_fp_shuffle_mask:$sm))>, Requires<[HasSSE2]>; +// 128-bit logical shifts +def : Pat<(int_x86_sse2_psll_dq VR128:$src1, imm:$src2), + (v2i64 (PSLLDQri VR128:$src1, (PSxLDQ_imm imm:$src2)))>; +def : Pat<(int_x86_sse2_psrl_dq VR128:$src1, imm:$src2), + (v2i64 (PSRLDQri VR128:$src1, (PSxLDQ_imm imm:$src2)))>; + // Logical ops def : Pat<(and (bc_v4i32 (v4f32 VR128:$src1)), (loadv4i32 addr:$src2)), (ANDPSrm VR128:$src1, addr:$src2)>; From lattner at cs.uiuc.edu Tue Apr 4 17:28:48 2006 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Tue, 4 Apr 2006 17:28:48 -0500 Subject: [llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCISelLowering.cpp Message-ID: <200604042228.RAA17327@zion.cs.uiuc.edu> Changes in directory llvm/lib/Target/PowerPC: PPCISelLowering.cpp updated: 1.129 -> 1.130 --- Log message: Fix some broken logic that would cause us to codegen {2147483647,2147483647,2147483647,2147483647} as 'vspltisb v0, -1'. --- Diffs of the changes: (+2 -2) PPCISelLowering.cpp | 4 ++-- 1 files changed, 2 insertions(+), 2 deletions(-) Index: llvm/lib/Target/PowerPC/PPCISelLowering.cpp diff -u llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.129 llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.130 --- llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.129 Tue Apr 4 12:25:31 2006 +++ llvm/lib/Target/PowerPC/PPCISelLowering.cpp Tue Apr 4 17:28:35 2006 @@ -353,8 +353,8 @@ ValSizeInBytes >>= 1; // If the top half equals the bottom half, we're still ok. - if (((Value >> (ValSizeInBytes*8)) & ((8 << ValSizeInBytes)-1)) != - (Value & ((8 << ValSizeInBytes)-1))) + if (((Value >> (ValSizeInBytes*8)) & (1 << (8*ValSizeInBytes)-1)) != + (Value & (1 << (8*ValSizeInBytes)-1))) return false; } From lattner at cs.uiuc.edu Tue Apr 4 17:44:08 2006 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Tue, 4 Apr 2006 17:44:08 -0500 Subject: [llvm-commits] CVS: llvm/lib/Target/PowerPC/README_ALTIVEC.txt Message-ID: <200604042244.RAA17460@zion.cs.uiuc.edu> Changes in directory llvm/lib/Target/PowerPC: README_ALTIVEC.txt updated: 1.11 -> 1.12 --- Log message: add a note --- Diffs of the changes: (+13 -2) README_ALTIVEC.txt | 15 +++++++++++++-- 1 files changed, 13 insertions(+), 2 deletions(-) Index: llvm/lib/Target/PowerPC/README_ALTIVEC.txt diff -u llvm/lib/Target/PowerPC/README_ALTIVEC.txt:1.11 llvm/lib/Target/PowerPC/README_ALTIVEC.txt:1.12 --- llvm/lib/Target/PowerPC/README_ALTIVEC.txt:1.11 Sat Apr 1 23:28:54 2006 +++ llvm/lib/Target/PowerPC/README_ALTIVEC.txt Tue Apr 4 17:43:55 2006 @@ -52,8 +52,6 @@ ds* mf* vavg* -vmax* -vmin* vmladduhm vmr* vsel (some aliases only accessible using builtins) @@ -64,6 +62,19 @@ //===----------------------------------------------------------------------===// +Codegen the constant here with something better than a constant pool load. + +void %test_f(<4 x float>* %P, <4 x float>* %Q, float %X) { + %tmp = load <4 x float>* %Q + %tmp = cast <4 x float> %tmp to <4 x int> + %tmp1 = and <4 x int> %tmp, < int 2147483647, int 2147483647, int 2147483647, int 2147483647 > + %tmp2 = cast <4 x int> %tmp1 to <4 x float> + store <4 x float> %tmp2, <4 x float>* %P + ret void +} + +//===----------------------------------------------------------------------===// + For functions that use altivec AND have calls, we are VRSAVE'ing all call clobbered regs. From lattner at cs.uiuc.edu Tue Apr 4 18:13:36 2006 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Tue, 4 Apr 2006 18:13:36 -0500 Subject: [llvm-commits] CVS: llvm/include/llvm/IntrinsicsPowerPC.td Message-ID: <200604042313.SAA17685@zion.cs.uiuc.edu> Changes in directory llvm/include/llvm: IntrinsicsPowerPC.td updated: 1.14 -> 1.15 --- Log message: add average intrinsics. --- Diffs of the changes: (+8 -0) IntrinsicsPowerPC.td | 8 ++++++++ 1 files changed, 8 insertions(+) Index: llvm/include/llvm/IntrinsicsPowerPC.td diff -u llvm/include/llvm/IntrinsicsPowerPC.td:1.14 llvm/include/llvm/IntrinsicsPowerPC.td:1.15 --- llvm/include/llvm/IntrinsicsPowerPC.td:1.14 Mon Apr 3 20:40:06 2006 +++ llvm/include/llvm/IntrinsicsPowerPC.td Tue Apr 4 18:13:21 2006 @@ -186,6 +186,14 @@ [InstrNoMem]>; } +// Vector average. +def int_ppc_altivec_vavgsb : PowerPC_Vec_BBB_Intrinsic<"vavgsb">; +def int_ppc_altivec_vavgsh : PowerPC_Vec_HHH_Intrinsic<"vavgsh">; +def int_ppc_altivec_vavgsw : PowerPC_Vec_WWW_Intrinsic<"vavgsw">; +def int_ppc_altivec_vavgub : PowerPC_Vec_BBB_Intrinsic<"vavgub">; +def int_ppc_altivec_vavguh : PowerPC_Vec_HHH_Intrinsic<"vavguh">; +def int_ppc_altivec_vavguw : PowerPC_Vec_WWW_Intrinsic<"vavguw">; + // Vector maximum. def int_ppc_altivec_vmaxfp : PowerPC_Vec_FFF_Intrinsic<"vmaxfp">; def int_ppc_altivec_vmaxsb : PowerPC_Vec_BBB_Intrinsic<"vmaxsb">; From lattner at cs.uiuc.edu Tue Apr 4 18:14:13 2006 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Tue, 4 Apr 2006 18:14:13 -0500 Subject: [llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCInstrAltivec.td Message-ID: <200604042314.SAA17749@zion.cs.uiuc.edu> Changes in directory llvm/lib/Target/PowerPC: PPCInstrAltivec.td updated: 1.33 -> 1.34 --- Log message: add average intrinsics --- Diffs of the changes: (+7 -0) PPCInstrAltivec.td | 7 +++++++ 1 files changed, 7 insertions(+) Index: llvm/lib/Target/PowerPC/PPCInstrAltivec.td diff -u llvm/lib/Target/PowerPC/PPCInstrAltivec.td:1.33 llvm/lib/Target/PowerPC/PPCInstrAltivec.td:1.34 --- llvm/lib/Target/PowerPC/PPCInstrAltivec.td:1.33 Tue Apr 4 12:25:31 2006 +++ llvm/lib/Target/PowerPC/PPCInstrAltivec.td Tue Apr 4 18:14:00 2006 @@ -209,6 +209,13 @@ def VEXPTEFP : VX2_Int<394, "vexptefp", int_ppc_altivec_vexptefp>; def VLOGEFP : VX2_Int<458, "vlogefp", int_ppc_altivec_vlogefp>; +def VAVGSB : VX1_Int<1282, "vavgsb", int_ppc_altivec_vavgsb>; +def VAVGSH : VX1_Int<1346, "vavgsh", int_ppc_altivec_vavgsh>; +def VAVGSW : VX1_Int<1410, "vavgsw", int_ppc_altivec_vavgsw>; +def VAVGUB : VX1_Int<1026, "vavgub", int_ppc_altivec_vavgub>; +def VAVGUH : VX1_Int<1090, "vavguh", int_ppc_altivec_vavguh>; +def VAVGUW : VX1_Int<1154, "vavguw", int_ppc_altivec_vavguw>; + def VMAXFP : VX1_Int<1034, "vmaxfp", int_ppc_altivec_vmaxfp>; def VMAXSB : VX1_Int< 258, "vmaxsb", int_ppc_altivec_vmaxsb>; def VMAXSH : VX1_Int< 322, "vmaxsh", int_ppc_altivec_vmaxsh>; From lattner at cs.uiuc.edu Tue Apr 4 18:24:38 2006 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Tue, 4 Apr 2006 18:24:38 -0500 Subject: [llvm-commits] CVS: llvm/include/llvm/IntrinsicsPowerPC.td Message-ID: <200604042324.SAA17887@zion.cs.uiuc.edu> Changes in directory llvm/include/llvm: IntrinsicsPowerPC.td updated: 1.15 -> 1.16 --- Log message: Add FP -> Int Conversions --- Diffs of the changes: (+7 -1) IntrinsicsPowerPC.td | 8 +++++++- 1 files changed, 7 insertions(+), 1 deletion(-) Index: llvm/include/llvm/IntrinsicsPowerPC.td diff -u llvm/include/llvm/IntrinsicsPowerPC.td:1.15 llvm/include/llvm/IntrinsicsPowerPC.td:1.16 --- llvm/include/llvm/IntrinsicsPowerPC.td:1.15 Tue Apr 4 18:13:21 2006 +++ llvm/include/llvm/IntrinsicsPowerPC.td Tue Apr 4 18:24:25 2006 @@ -350,13 +350,19 @@ Intrinsic<[llvm_v4i32_ty, llvm_v8i16_ty], [InstrNoMem]>; - // FP to integer conversion. + // FP <-> integer conversion. def int_ppc_altivec_vcfsx : GCCBuiltin<"__builtin_altivec_vcfsx">, Intrinsic<[llvm_v4f32_ty, llvm_v4i32_ty, llvm_int_ty], [InstrNoMem]>; def int_ppc_altivec_vcfux : GCCBuiltin<"__builtin_altivec_vcfux">, Intrinsic<[llvm_v4f32_ty, llvm_v4i32_ty, llvm_int_ty], [InstrNoMem]>; + def int_ppc_altivec_vctsxs : GCCBuiltin<"__builtin_altivec_vctsxs">, + Intrinsic<[llvm_v4i32_ty, llvm_v4f32_ty, llvm_int_ty], + [InstrNoMem]>; + def int_ppc_altivec_vctuxs : GCCBuiltin<"__builtin_altivec_vctuxs">, + Intrinsic<[llvm_v4i32_ty, llvm_v4f32_ty, llvm_int_ty], + [InstrNoMem]>; def int_ppc_altivec_vrfim : GCCBuiltin<"__builtin_altivec_vrfim">, Intrinsic<[llvm_v4f32_ty, llvm_v4f32_ty], [InstrNoMem]>; From lattner at cs.uiuc.edu Tue Apr 4 18:25:15 2006 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Tue, 4 Apr 2006 18:25:15 -0500 Subject: [llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCInstrAltivec.td Message-ID: <200604042325.SAA17956@zion.cs.uiuc.edu> Changes in directory llvm/lib/Target/PowerPC: PPCInstrAltivec.td updated: 1.34 -> 1.35 --- Log message: Add FP -> Int Conversions --- Diffs of the changes: (+4 -2) PPCInstrAltivec.td | 6 ++++-- 1 files changed, 4 insertions(+), 2 deletions(-) Index: llvm/lib/Target/PowerPC/PPCInstrAltivec.td diff -u llvm/lib/Target/PowerPC/PPCInstrAltivec.td:1.34 llvm/lib/Target/PowerPC/PPCInstrAltivec.td:1.35 --- llvm/lib/Target/PowerPC/PPCInstrAltivec.td:1.34 Tue Apr 4 18:14:00 2006 +++ llvm/lib/Target/PowerPC/PPCInstrAltivec.td Tue Apr 4 18:25:02 2006 @@ -202,10 +202,12 @@ (int_ppc_altivec_vcfux VRRC:$vB, imm:$UIMM))]>; def VCTSXS : VXForm_1<970, (ops VRRC:$vD, u5imm:$UIMM, VRRC:$vB), "vctsxs $vD, $vB, $UIMM", VecFP, - []>; + [(set VRRC:$vD, + (int_ppc_altivec_vctsxs VRRC:$vB, imm:$UIMM))]>; def VCTUXS : VXForm_1<906, (ops VRRC:$vD, u5imm:$UIMM, VRRC:$vB), "vctuxs $vD, $vB, $UIMM", VecFP, - []>; + [(set VRRC:$vD, + (int_ppc_altivec_vctuxs VRRC:$vB, imm:$UIMM))]>; def VEXPTEFP : VX2_Int<394, "vexptefp", int_ppc_altivec_vexptefp>; def VLOGEFP : VX2_Int<458, "vlogefp", int_ppc_altivec_vlogefp>; From lattner at cs.uiuc.edu Tue Apr 4 18:43:56 2006 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Tue, 4 Apr 2006 18:43:56 -0500 Subject: [llvm-commits] CVS: llvm/include/llvm/IntrinsicsPowerPC.td Message-ID: <200604042343.SAA18156@zion.cs.uiuc.edu> Changes in directory llvm/include/llvm: IntrinsicsPowerPC.td updated: 1.16 -> 1.17 --- Log message: Add missing byte merges. --- Diffs of the changes: (+6 -0) IntrinsicsPowerPC.td | 6 ++++++ 1 files changed, 6 insertions(+) Index: llvm/include/llvm/IntrinsicsPowerPC.td diff -u llvm/include/llvm/IntrinsicsPowerPC.td:1.16 llvm/include/llvm/IntrinsicsPowerPC.td:1.17 --- llvm/include/llvm/IntrinsicsPowerPC.td:1.16 Tue Apr 4 18:24:25 2006 +++ llvm/include/llvm/IntrinsicsPowerPC.td Tue Apr 4 18:43:44 2006 @@ -374,12 +374,18 @@ Intrinsic<[llvm_v4f32_ty, llvm_v4f32_ty], [InstrNoMem]>; // Merges + def int_ppc_altivec_vmrghb : GCCBuiltin<"__builtin_altivec_vmrghb">, + Intrinsic<[llvm_v16i8_ty, llvm_v16i8_ty, llvm_v16i8_ty], + [InstrNoMem]>; def int_ppc_altivec_vmrghh : GCCBuiltin<"__builtin_altivec_vmrghh">, Intrinsic<[llvm_v8i16_ty, llvm_v8i16_ty, llvm_v8i16_ty], [InstrNoMem]>; def int_ppc_altivec_vmrghw : GCCBuiltin<"__builtin_altivec_vmrghw">, Intrinsic<[llvm_v4i32_ty, llvm_v4i32_ty, llvm_v4i32_ty], [InstrNoMem]>; + def int_ppc_altivec_vmrglb : GCCBuiltin<"__builtin_altivec_vmrglb">, + Intrinsic<[llvm_v16i8_ty, llvm_v16i8_ty, llvm_v16i8_ty], + [InstrNoMem]>; def int_ppc_altivec_vmrglh : GCCBuiltin<"__builtin_altivec_vmrglh">, Intrinsic<[llvm_v8i16_ty, llvm_v8i16_ty, llvm_v8i16_ty], [InstrNoMem]>; From lattner at cs.uiuc.edu Tue Apr 4 18:44:09 2006 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Tue, 4 Apr 2006 18:44:09 -0500 Subject: [llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCInstrAltivec.td Message-ID: <200604042344.SAA18166@zion.cs.uiuc.edu> Changes in directory llvm/lib/Target/PowerPC: PPCInstrAltivec.td updated: 1.35 -> 1.36 --- Log message: Add missing byte merges. --- Diffs of the changes: (+2 -0) PPCInstrAltivec.td | 2 ++ 1 files changed, 2 insertions(+) Index: llvm/lib/Target/PowerPC/PPCInstrAltivec.td diff -u llvm/lib/Target/PowerPC/PPCInstrAltivec.td:1.35 llvm/lib/Target/PowerPC/PPCInstrAltivec.td:1.36 --- llvm/lib/Target/PowerPC/PPCInstrAltivec.td:1.35 Tue Apr 4 18:25:02 2006 +++ llvm/lib/Target/PowerPC/PPCInstrAltivec.td Tue Apr 4 18:43:56 2006 @@ -233,8 +233,10 @@ def VMINUH : VX1_Int< 578, "vminuh", int_ppc_altivec_vminuh>; def VMINUW : VX1_Int< 642, "vminuw", int_ppc_altivec_vminuw>; +def VMRGHB : VX1_Int<12 , "vmrghb", int_ppc_altivec_vmrghb>; def VMRGHH : VX1_Int<76 , "vmrghh", int_ppc_altivec_vmrghh>; def VMRGHW : VX1_Int<140, "vmrghw", int_ppc_altivec_vmrghw>; +def VMRGLB : VX1_Int<268, "vmrglb", int_ppc_altivec_vmrglb>; def VMRGLH : VX1_Int<332, "vmrglh", int_ppc_altivec_vmrglh>; def VMRGLW : VX1_Int<396, "vmrglw", int_ppc_altivec_vmrglw>; From lattner at cs.uiuc.edu Tue Apr 4 18:45:24 2006 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Tue, 4 Apr 2006 18:45:24 -0500 Subject: [llvm-commits] CVS: llvm/lib/Target/PowerPC/README_ALTIVEC.txt Message-ID: <200604042345.SAA18207@zion.cs.uiuc.edu> Changes in directory llvm/lib/Target/PowerPC: README_ALTIVEC.txt updated: 1.12 -> 1.13 --- Log message: add a note --- Diffs of the changes: (+4 -2) README_ALTIVEC.txt | 6 ++++-- 1 files changed, 4 insertions(+), 2 deletions(-) Index: llvm/lib/Target/PowerPC/README_ALTIVEC.txt diff -u llvm/lib/Target/PowerPC/README_ALTIVEC.txt:1.12 llvm/lib/Target/PowerPC/README_ALTIVEC.txt:1.13 --- llvm/lib/Target/PowerPC/README_ALTIVEC.txt:1.12 Tue Apr 4 17:43:55 2006 +++ llvm/lib/Target/PowerPC/README_ALTIVEC.txt Tue Apr 4 18:45:11 2006 @@ -51,9 +51,7 @@ ds* mf* -vavg* vmladduhm -vmr* vsel (some aliases only accessible using builtins) //===----------------------------------------------------------------------===// @@ -154,3 +152,7 @@ } //===----------------------------------------------------------------------===// + +Lower "merges" in the front-end to shuffles, reconstruct in the backend. + +//===----------------------------------------------------------------------===// From lattner at cs.uiuc.edu Tue Apr 4 19:03:16 2006 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Tue, 4 Apr 2006 19:03:16 -0500 Subject: [llvm-commits] CVS: llvm/include/llvm/IntrinsicsPowerPC.td Message-ID: <200604050003.TAA18373@zion.cs.uiuc.edu> Changes in directory llvm/include/llvm: IntrinsicsPowerPC.td updated: 1.17 -> 1.18 --- Log message: Add m[tf]vscr intrinsics. --- Diffs of the changes: (+7 -0) IntrinsicsPowerPC.td | 7 +++++++ 1 files changed, 7 insertions(+) Index: llvm/include/llvm/IntrinsicsPowerPC.td diff -u llvm/include/llvm/IntrinsicsPowerPC.td:1.17 llvm/include/llvm/IntrinsicsPowerPC.td:1.18 --- llvm/include/llvm/IntrinsicsPowerPC.td:1.17 Tue Apr 4 18:43:44 2006 +++ llvm/include/llvm/IntrinsicsPowerPC.td Tue Apr 4 19:03:03 2006 @@ -66,6 +66,13 @@ // PowerPC Altivec Intrinsic Definitions. let TargetPrefix = "ppc" in { // All intrinsics start with "llvm.ppc.". + // VSCR access. + def int_ppc_altivec_mfvscr : GCCBuiltin<"__builtin_altivec_mfvscr">, + Intrinsic<[llvm_v8i16_ty], [IntrReadMem]>; + def int_ppc_altivec_mtvscr : GCCBuiltin<"__builtin_altivec_mtvscr">, + Intrinsic<[llvm_void_ty, llvm_v4i32_ty], [IntrWriteMem]>; + + // Loads. These don't map directly to GCC builtins because they represent the // source address with a single pointer. def int_ppc_altivec_lvx : From lattner at cs.uiuc.edu Tue Apr 4 19:04:10 2006 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Tue, 4 Apr 2006 19:04:10 -0500 Subject: [llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCInstrAltivec.td PPCInstrFormats.td Message-ID: <200604050004.TAA18437@zion.cs.uiuc.edu> Changes in directory llvm/lib/Target/PowerPC: PPCInstrAltivec.td updated: 1.36 -> 1.37 PPCInstrFormats.td updated: 1.71 -> 1.72 --- Log message: Add m[tf]vscr instructions. --- Diffs of the changes: (+34 -0) PPCInstrAltivec.td | 7 +++++++ PPCInstrFormats.td | 27 +++++++++++++++++++++++++++ 2 files changed, 34 insertions(+) Index: llvm/lib/Target/PowerPC/PPCInstrAltivec.td diff -u llvm/lib/Target/PowerPC/PPCInstrAltivec.td:1.36 llvm/lib/Target/PowerPC/PPCInstrAltivec.td:1.37 --- llvm/lib/Target/PowerPC/PPCInstrAltivec.td:1.36 Tue Apr 4 18:43:56 2006 +++ llvm/lib/Target/PowerPC/PPCInstrAltivec.td Tue Apr 4 19:03:57 2006 @@ -93,6 +93,13 @@ def IMPLICIT_DEF_VRRC : Pseudo<(ops VRRC:$rD), "; $rD = IMPLICIT_DEF_VRRC", [(set VRRC:$rD, (v4f32 (undef)))]>; +def MFVSCR : VXForm_4<1540, (ops VRRC:$vD), + "mfvcr $vD", LdStGeneral, + [(set VRRC:$vD, (int_ppc_altivec_mfvscr))]>; +def MTVSCR : VXForm_5<1604, (ops VRRC:$vB), + "mtvcr $vB", LdStGeneral, + [(int_ppc_altivec_mtvscr VRRC:$vB)]>; + let isLoad = 1, PPC970_Unit = 2 in { // Loads. def LVEBX: XForm_1<31, 7, (ops VRRC:$vD, memrr:$src), "lvebx $vD, $src", LdStGeneral, Index: llvm/lib/Target/PowerPC/PPCInstrFormats.td diff -u llvm/lib/Target/PowerPC/PPCInstrFormats.td:1.71 llvm/lib/Target/PowerPC/PPCInstrFormats.td:1.72 --- llvm/lib/Target/PowerPC/PPCInstrFormats.td:1.71 Sun Mar 26 21:34:17 2006 +++ llvm/lib/Target/PowerPC/PPCInstrFormats.td Tue Apr 4 19:03:57 2006 @@ -697,6 +697,33 @@ let Inst{21-31} = xo; } +/// VXForm_4 - VX instructions with "VD,0,0" register fields, like mfvscr. +class VXForm_4 xo, dag OL, string asmstr, + InstrItinClass itin, list pattern> + : I<4, OL, asmstr, itin> { + bits<5> VD; + + let Pattern = pattern; + + let Inst{6-10} = VD; + let Inst{11-15} = 0; + let Inst{16-20} = 0; + let Inst{21-31} = xo; +} + +/// VXForm_5 - VX instructions with "0,0,VB" register fields, like mtvscr. +class VXForm_5 xo, dag OL, string asmstr, + InstrItinClass itin, list pattern> + : I<4, OL, asmstr, itin> { + bits<5> VB; + + let Pattern = pattern; + + let Inst{6-10} = 0; + let Inst{11-15} = 0; + let Inst{16-20} = VB; + let Inst{21-31} = xo; +} // E-4 VXR-Form class VXRForm_1 xo, dag OL, string asmstr, From lattner at cs.uiuc.edu Tue Apr 4 19:49:26 2006 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Tue, 4 Apr 2006 19:49:26 -0500 Subject: [llvm-commits] CVS: llvm/include/llvm/IntrinsicsPowerPC.td Message-ID: <200604050049.TAA18604@zion.cs.uiuc.edu> Changes in directory llvm/include/llvm: IntrinsicsPowerPC.td updated: 1.18 -> 1.19 --- Log message: correct the type of two intrinsics, add int_ppc_altivec_vmladduhm --- Diffs of the changes: (+7 -2) IntrinsicsPowerPC.td | 9 +++++++-- 1 files changed, 7 insertions(+), 2 deletions(-) Index: llvm/include/llvm/IntrinsicsPowerPC.td diff -u llvm/include/llvm/IntrinsicsPowerPC.td:1.18 llvm/include/llvm/IntrinsicsPowerPC.td:1.19 --- llvm/include/llvm/IntrinsicsPowerPC.td:1.18 Tue Apr 4 19:03:03 2006 +++ llvm/include/llvm/IntrinsicsPowerPC.td Tue Apr 4 19:49:14 2006 @@ -317,6 +317,11 @@ Intrinsic<[llvm_v4i32_ty, llvm_v16i8_ty, llvm_v4i32_ty], [InstrNoMem]>; + // Other multiplies. + def int_ppc_altivec_vmladduhm : GCCBuiltin<"__builtin_altivec_vmladduhm">, + Intrinsic<[llvm_v8i16_ty, llvm_v8i16_ty, llvm_v8i16_ty, + llvm_v8i16_ty], [InstrNoMem]>; + // Packs. def int_ppc_altivec_vpkpx : GCCBuiltin<"__builtin_altivec_vpkpx">, Intrinsic<[llvm_v8i16_ty, llvm_v4i32_ty, llvm_v4i32_ty], @@ -328,10 +333,10 @@ Intrinsic<[llvm_v16i8_ty, llvm_v8i16_ty, llvm_v8i16_ty], [InstrNoMem]>; def int_ppc_altivec_vpkswss : GCCBuiltin<"__builtin_altivec_vpkswss">, - Intrinsic<[llvm_v4i32_ty, llvm_v16i8_ty, llvm_v16i8_ty], + Intrinsic<[llvm_v16i8_ty, llvm_v4i32_ty, llvm_v4i32_ty], [InstrNoMem]>; def int_ppc_altivec_vpkswus : GCCBuiltin<"__builtin_altivec_vpkswus">, - Intrinsic<[llvm_v4i32_ty, llvm_v16i8_ty, llvm_v16i8_ty], + Intrinsic<[llvm_v16i8_ty, llvm_v4i32_ty, llvm_v4i32_ty], [InstrNoMem]>; // vpkuhum is lowered to a shuffle. def int_ppc_altivec_vpkuhus : GCCBuiltin<"__builtin_altivec_vpkuhus">, From lattner at cs.uiuc.edu Tue Apr 4 19:50:01 2006 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Tue, 4 Apr 2006 19:50:01 -0500 Subject: [llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCInstrAltivec.td README_ALTIVEC.txt Message-ID: <200604050050.TAA18672@zion.cs.uiuc.edu> Changes in directory llvm/lib/Target/PowerPC: PPCInstrAltivec.td updated: 1.37 -> 1.38 README_ALTIVEC.txt updated: 1.13 -> 1.14 --- Log message: add vmladduhm --- Diffs of the changes: (+2 -2) PPCInstrAltivec.td | 2 ++ README_ALTIVEC.txt | 2 -- 2 files changed, 2 insertions(+), 2 deletions(-) Index: llvm/lib/Target/PowerPC/PPCInstrAltivec.td diff -u llvm/lib/Target/PowerPC/PPCInstrAltivec.td:1.37 llvm/lib/Target/PowerPC/PPCInstrAltivec.td:1.38 --- llvm/lib/Target/PowerPC/PPCInstrAltivec.td:1.37 Tue Apr 4 19:03:57 2006 +++ llvm/lib/Target/PowerPC/PPCInstrAltivec.td Tue Apr 4 19:49:48 2006 @@ -157,8 +157,10 @@ [(set VRRC:$vD, (fneg (fsub (fmul VRRC:$vA, VRRC:$vC), VRRC:$vB)))]>, Requires<[FPContractions]>; + def VMHADDSHS : VA1a_Int<32, "vmhaddshs", int_ppc_altivec_vmhaddshs>; def VMHRADDSHS : VA1a_Int<33, "vmhraddshs", int_ppc_altivec_vmhraddshs>; +def VMLADDUHM : VA1a_Int<34, "vmladduhm", int_ppc_altivec_vmladduhm>; def VPERM : VA1a_Int<43, "vperm", int_ppc_altivec_vperm>; def VSEL : VA1a_Int<42, "vsel", int_ppc_altivec_vsel>; Index: llvm/lib/Target/PowerPC/README_ALTIVEC.txt diff -u llvm/lib/Target/PowerPC/README_ALTIVEC.txt:1.13 llvm/lib/Target/PowerPC/README_ALTIVEC.txt:1.14 --- llvm/lib/Target/PowerPC/README_ALTIVEC.txt:1.13 Tue Apr 4 18:45:11 2006 +++ llvm/lib/Target/PowerPC/README_ALTIVEC.txt Tue Apr 4 19:49:48 2006 @@ -50,8 +50,6 @@ Missing intrinsics: ds* -mf* -vmladduhm vsel (some aliases only accessible using builtins) //===----------------------------------------------------------------------===// From lattner at cs.uiuc.edu Tue Apr 4 20:16:06 2006 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Tue, 4 Apr 2006 20:16:06 -0500 Subject: [llvm-commits] CVS: llvm/include/llvm/IntrinsicsPowerPC.td Message-ID: <200604050116.UAA18854@zion.cs.uiuc.edu> Changes in directory llvm/include/llvm: IntrinsicsPowerPC.td updated: 1.19 -> 1.20 --- Log message: Get the types right, third time is the charm. Add vsl. --- Diffs of the changes: (+5 -2) IntrinsicsPowerPC.td | 7 +++++-- 1 files changed, 5 insertions(+), 2 deletions(-) Index: llvm/include/llvm/IntrinsicsPowerPC.td diff -u llvm/include/llvm/IntrinsicsPowerPC.td:1.19 llvm/include/llvm/IntrinsicsPowerPC.td:1.20 --- llvm/include/llvm/IntrinsicsPowerPC.td:1.19 Tue Apr 4 19:49:14 2006 +++ llvm/include/llvm/IntrinsicsPowerPC.td Tue Apr 4 20:15:54 2006 @@ -336,7 +336,7 @@ Intrinsic<[llvm_v16i8_ty, llvm_v4i32_ty, llvm_v4i32_ty], [InstrNoMem]>; def int_ppc_altivec_vpkswus : GCCBuiltin<"__builtin_altivec_vpkswus">, - Intrinsic<[llvm_v16i8_ty, llvm_v4i32_ty, llvm_v4i32_ty], + Intrinsic<[llvm_v8i16_ty, llvm_v4i32_ty, llvm_v4i32_ty], [InstrNoMem]>; // vpkuhum is lowered to a shuffle. def int_ppc_altivec_vpkuhus : GCCBuiltin<"__builtin_altivec_vpkuhus">, @@ -344,7 +344,7 @@ [InstrNoMem]>; // vpkuwum is lowered to a shuffle. def int_ppc_altivec_vpkuwus : GCCBuiltin<"__builtin_altivec_vpkuwus">, - Intrinsic<[llvm_v8i16_ty, llvm_v4i32_ty, llvm_v4i32_ty], + Intrinsic<[llvm_v16i8_ty, llvm_v4i32_ty, llvm_v4i32_ty], [InstrNoMem]>; // Unpacks. @@ -410,7 +410,10 @@ Intrinsic<[llvm_v4i32_ty, llvm_v4i32_ty, llvm_v4i32_ty, llvm_int_ty], [InstrNoMem]>; } + +def int_ppc_altivec_vsl : PowerPC_Vec_WWW_Intrinsic<"vsl">; def int_ppc_altivec_vslo : PowerPC_Vec_WWW_Intrinsic<"vslo">; + def int_ppc_altivec_vslb : PowerPC_Vec_BBB_Intrinsic<"vslb">; def int_ppc_altivec_vslh : PowerPC_Vec_HHH_Intrinsic<"vslh">; def int_ppc_altivec_vslw : PowerPC_Vec_WWW_Intrinsic<"vslw">; From lattner at cs.uiuc.edu Tue Apr 4 20:16:35 2006 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Tue, 4 Apr 2006 20:16:35 -0500 Subject: [llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCInstrAltivec.td Message-ID: <200604050116.UAA18915@zion.cs.uiuc.edu> Changes in directory llvm/lib/Target/PowerPC: PPCInstrAltivec.td updated: 1.38 -> 1.39 --- Log message: add vsl --- Diffs of the changes: (+2 -0) PPCInstrAltivec.td | 2 ++ 1 files changed, 2 insertions(+) Index: llvm/lib/Target/PowerPC/PPCInstrAltivec.td diff -u llvm/lib/Target/PowerPC/PPCInstrAltivec.td:1.38 llvm/lib/Target/PowerPC/PPCInstrAltivec.td:1.39 --- llvm/lib/Target/PowerPC/PPCInstrAltivec.td:1.38 Tue Apr 4 19:49:48 2006 +++ llvm/lib/Target/PowerPC/PPCInstrAltivec.td Tue Apr 4 20:16:22 2006 @@ -312,6 +312,8 @@ def VRLB : VX1_Int< 4, "vrlb", int_ppc_altivec_vrlb>; def VRLH : VX1_Int< 68, "vrlh", int_ppc_altivec_vrlh>; def VRLW : VX1_Int< 132, "vrlw", int_ppc_altivec_vrlw>; + +def VSL : VX1_Int< 452, "vsl" , int_ppc_altivec_vsl >; def VSLO : VX1_Int<1036, "vslo", int_ppc_altivec_vslo>; def VSLB : VX1_Int< 260, "vslb", int_ppc_altivec_vslb>; def VSLH : VX1_Int< 324, "vslh", int_ppc_altivec_vslh>; From evan.cheng at apple.com Tue Apr 4 20:45:10 2006 From: evan.cheng at apple.com (Evan Cheng) Date: Tue, 4 Apr 2006 20:45:10 -0500 Subject: [llvm-commits] CVS: llvm/test/Regression/CodeGen/X86/vec_shuffle.ll Message-ID: <200604050145.UAA18988@zion.cs.uiuc.edu> Changes in directory llvm/test/Regression/CodeGen/X86: vec_shuffle.ll updated: 1.4 -> 1.5 --- Log message: Add a new shuffle test case that requires pshuflw / pshufhw pair. --- Diffs of the changes: (+27 -2) vec_shuffle.ll | 29 +++++++++++++++++++++++++++-- 1 files changed, 27 insertions(+), 2 deletions(-) Index: llvm/test/Regression/CodeGen/X86/vec_shuffle.ll diff -u llvm/test/Regression/CodeGen/X86/vec_shuffle.ll:1.4 llvm/test/Regression/CodeGen/X86/vec_shuffle.ll:1.5 --- llvm/test/Regression/CodeGen/X86/vec_shuffle.ll:1.4 Wed Mar 29 16:51:28 2006 +++ llvm/test/Regression/CodeGen/X86/vec_shuffle.ll Tue Apr 4 20:44:57 2006 @@ -1,6 +1,7 @@ ; RUN: llvm-as < %s | llc -march=x86 -mattr=+sse2 | grep shufp | wc -l | grep 1 -; RUN: llvm-as < %s | llc -march=x86 -mattr=+sse2 | grep movhpd -; RUN: llvm-as < %s | llc -march=x86 -mattr=+sse2 | grep pshufhw +; RUN: llvm-as < %s | llc -march=x86 -mattr=+sse2 | grep movhpd | wc -l | grep 1 +; RUN: llvm-as < %s | llc -march=x86 -mattr=+sse2 | grep pshufhw | wc -l | grep 2 +; RUN: llvm-as < %s | llc -march=x86 -mattr=+sse2 | grep pshuflw | wc -l | grep 1 void %test_v4sf(<4 x float>* %P, float %X, float %Y) { %tmp = insertelement <4 x float> zeroinitializer, float %X, uint 0 @@ -41,3 +42,27 @@ store <2 x long> %tmp15, <2 x long>* %res ret void } + +void %test_v8i16_2(<2 x long>* %res, <2 x long>* %A) { + %tmp = load <2 x long>* %A + %tmp = cast <2 x long> %tmp to <8 x short> + %tmp0 = extractelement <8 x short> %tmp, uint 0 + %tmp1 = extractelement <8 x short> %tmp, uint 1 + %tmp2 = extractelement <8 x short> %tmp, uint 2 + %tmp3 = extractelement <8 x short> %tmp, uint 3 + %tmp4 = extractelement <8 x short> %tmp, uint 4 + %tmp5 = extractelement <8 x short> %tmp, uint 5 + %tmp6 = extractelement <8 x short> %tmp, uint 6 + %tmp7 = extractelement <8 x short> %tmp, uint 7 + %tmp8 = insertelement <8 x short> undef, short %tmp2, uint 0 + %tmp9 = insertelement <8 x short> %tmp8, short %tmp1, uint 1 + %tmp10 = insertelement <8 x short> %tmp9, short %tmp0, uint 2 + %tmp11 = insertelement <8 x short> %tmp10, short %tmp3, uint 3 + %tmp12 = insertelement <8 x short> %tmp11, short %tmp6, uint 4 + %tmp13 = insertelement <8 x short> %tmp12, short %tmp5, uint 5 + %tmp14 = insertelement <8 x short> %tmp13, short %tmp4, uint 6 + %tmp15 = insertelement <8 x short> %tmp14, short %tmp7, uint 7 + %tmp15 = cast <8 x short> %tmp15 to <2 x long> + store <2 x long> %tmp15, <2 x long>* %res + ret void +} From evan.cheng at apple.com Tue Apr 4 20:47:50 2006 From: evan.cheng at apple.com (Evan Cheng) Date: Tue, 4 Apr 2006 20:47:50 -0500 Subject: [llvm-commits] CVS: llvm/lib/Target/X86/X86ISelLowering.cpp Message-ID: <200604050147.UAA19005@zion.cs.uiuc.edu> Changes in directory llvm/lib/Target/X86: X86ISelLowering.cpp updated: 1.153 -> 1.154 --- Log message: Handle v8i16 shuffle that must be broken into a pair of pshufhw / pshuflw. --- Diffs of the changes: (+55 -2) X86ISelLowering.cpp | 57 ++++++++++++++++++++++++++++++++++++++++++++++++++-- 1 files changed, 55 insertions(+), 2 deletions(-) Index: llvm/lib/Target/X86/X86ISelLowering.cpp diff -u llvm/lib/Target/X86/X86ISelLowering.cpp:1.153 llvm/lib/Target/X86/X86ISelLowering.cpp:1.154 --- llvm/lib/Target/X86/X86ISelLowering.cpp:1.153 Mon Apr 3 17:30:54 2006 +++ llvm/lib/Target/X86/X86ISelLowering.cpp Tue Apr 4 20:47:37 2006 @@ -1417,7 +1417,7 @@ } /// isPSHUFHWMask - Return true if the specified VECTOR_SHUFFLE operand -/// specifies a shuffle of elements that is suitable for input to PSHUFD. +/// specifies a shuffle of elements that is suitable for input to PSHUFHW. bool X86::isPSHUFHWMask(SDNode *N) { assert(N->getOpcode() == ISD::BUILD_VECTOR); @@ -1447,7 +1447,7 @@ } /// isPSHUFLWMask - Return true if the specified VECTOR_SHUFFLE operand -/// specifies a shuffle of elements that is suitable for input to PSHUFD. +/// specifies a shuffle of elements that is suitable for input to PSHUFLW. bool X86::isPSHUFLWMask(SDNode *N) { assert(N->getOpcode() == ISD::BUILD_VECTOR); @@ -1781,6 +1781,38 @@ return SDOperand(); } +/// isPSHUFHW_PSHUFLWMask - true if the specified VECTOR_SHUFFLE operand +/// specifies a 8 element shuffle that can be broken into a pair of +/// PSHUFHW and PSHUFLW. +static bool isPSHUFHW_PSHUFLWMask(SDNode *N) { + assert(N->getOpcode() == ISD::BUILD_VECTOR); + + if (N->getNumOperands() != 8) + return false; + + // Lower quadword shuffled. + for (unsigned i = 0; i != 4; ++i) { + SDOperand Arg = N->getOperand(i); + if (Arg.getOpcode() == ISD::UNDEF) continue; + assert(isa(Arg) && "Invalid VECTOR_SHUFFLE mask!"); + unsigned Val = cast(Arg)->getValue(); + if (Val > 4) + return false; + } + + // Upper quadword shuffled. + for (unsigned i = 4; i != 8; ++i) { + SDOperand Arg = N->getOperand(i); + if (Arg.getOpcode() == ISD::UNDEF) continue; + assert(isa(Arg) && "Invalid VECTOR_SHUFFLE mask!"); + unsigned Val = cast(Arg)->getValue(); + if (Val < 4 || Val > 7) + return false; + } + + return true; +} + /// LowerOperation - Provide custom lowering hooks for some operations. /// SDOperand X86TargetLowering::LowerOperation(SDOperand Op, SelectionDAG &DAG) { @@ -2590,6 +2622,26 @@ if (X86::isSHUFPMask(PermMask.Val)) return NormalizeVectorShuffle(V1, V2, PermMask, VT, DAG); + + // Handle v8i16 shuffle high / low shuffle node pair. + if (VT == MVT::v8i16 && isPSHUFHW_PSHUFLWMask(PermMask.Val)) { + MVT::ValueType MaskVT = MVT::getIntVectorWithNumElements(NumElems); + MVT::ValueType BaseVT = MVT::getVectorBaseType(MaskVT); + std::vector MaskVec; + for (unsigned i = 0; i != 4; ++i) + MaskVec.push_back(PermMask.getOperand(i)); + for (unsigned i = 4; i != 8; ++i) + MaskVec.push_back(DAG.getConstant(i, BaseVT)); + SDOperand Mask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT, MaskVec); + V1 = DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V2, Mask); + MaskVec.clear(); + for (unsigned i = 0; i != 4; ++i) + MaskVec.push_back(DAG.getConstant(i, BaseVT)); + for (unsigned i = 4; i != 8; ++i) + MaskVec.push_back(PermMask.getOperand(i)); + Mask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT, MaskVec); + return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V2, Mask); + } } else { // Floating point cases in the other order. if (X86::isSHUFPMask(PermMask.Val)) @@ -2872,6 +2924,7 @@ X86::isPSHUFDMask(Mask.Val) || X86::isPSHUFHWMask(Mask.Val) || X86::isPSHUFLWMask(Mask.Val) || + isPSHUFHW_PSHUFLWMask(Mask.Val) || X86::isSHUFPMask(Mask.Val) || X86::isUNPCKLMask(Mask.Val) || X86::isUNPCKHMask(Mask.Val)); From alenhar2 at cs.uiuc.edu Tue Apr 4 21:42:48 2006 From: alenhar2 at cs.uiuc.edu (Andrew Lenharth) Date: Tue, 4 Apr 2006 21:42:48 -0500 Subject: [llvm-commits] CVS: llvm/lib/Analysis/DataStructure/Local.cpp Message-ID: <200604050242.VAA19171@zion.cs.uiuc.edu> Changes in directory llvm/lib/Analysis/DataStructure: Local.cpp updated: 1.143 -> 1.144 --- Log message: revert this, this is safe, if conservative. leave a note to that effect --- Diffs of the changes: (+7 -9) Local.cpp | 16 +++++++--------- 1 files changed, 7 insertions(+), 9 deletions(-) Index: llvm/lib/Analysis/DataStructure/Local.cpp diff -u llvm/lib/Analysis/DataStructure/Local.cpp:1.143 llvm/lib/Analysis/DataStructure/Local.cpp:1.144 --- llvm/lib/Analysis/DataStructure/Local.cpp:1.143 Wed Mar 15 13:03:16 2006 +++ llvm/lib/Analysis/DataStructure/Local.cpp Tue Apr 4 21:42:36 2006 @@ -546,17 +546,15 @@ case Intrinsic::vaend: return; // noop case Intrinsic::memcpy_i32: - case Intrinsic::memcpy_i64: { - //write first location - if (DSNode *N = getValueDest(**CS.arg_begin()).getNode()) - N->setModifiedMarker(); - //and read second pointer - if (DSNode *N = getValueDest(**(CS.arg_begin() + 1)).getNode()) - N->setReadMarker(); - return; - } + case Intrinsic::memcpy_i64: case Intrinsic::memmove_i32: case Intrinsic::memmove_i64: { + //This is over aggressive. What these functions do is not make the + // targets pointers alias, but rather merge the out edges of the graphs + // for the pointers according to the type merging of the graphs. + //Simply merging the two graphs is a crude approximation to this. + //I might be wrong though. + // Merge the first & second arguments, and mark the memory read and // modified. DSNodeHandle RetNH = getValueDest(**CS.arg_begin()); From alenhar2 at cs.uiuc.edu Tue Apr 4 22:31:58 2006 From: alenhar2 at cs.uiuc.edu (Andrew Lenharth) Date: Tue, 4 Apr 2006 22:31:58 -0500 Subject: [llvm-commits] CVS: llvm/test/Regression/Analysis/DSGraph/2004-02-13-memcpy.ll Message-ID: <200604050331.WAA19443@zion.cs.uiuc.edu> Changes in directory llvm/test/Regression/Analysis/DSGraph: 2004-02-13-memcpy.ll updated: 1.3 -> 1.4 --- Log message: make this test less exacting --- Diffs of the changes: (+1 -1) 2004-02-13-memcpy.ll | 2 +- 1 files changed, 1 insertion(+), 1 deletion(-) Index: llvm/test/Regression/Analysis/DSGraph/2004-02-13-memcpy.ll diff -u llvm/test/Regression/Analysis/DSGraph/2004-02-13-memcpy.ll:1.3 llvm/test/Regression/Analysis/DSGraph/2004-02-13-memcpy.ll:1.4 --- llvm/test/Regression/Analysis/DSGraph/2004-02-13-memcpy.ll:1.3 Wed Mar 15 13:02:54 2006 +++ llvm/test/Regression/Analysis/DSGraph/2004-02-13-memcpy.ll Tue Apr 4 22:31:45 2006 @@ -1,5 +1,5 @@ ; RUN: analyze %s -datastructure-gc -dsgc-check-flags=Xn:SMR -; RUN: analyze %s -datastructure-gc -dsgc-check-flags=X:SM +; RUN: analyze %s -datastructure-gc -dsgc-check-flags=X:SMR declare void %llvm.memcpy.i32(sbyte*, sbyte*, uint, uint) declare void %llvm.memmove.i32(sbyte*, sbyte*, uint, uint) From evan.cheng at apple.com Tue Apr 4 23:41:48 2006 From: evan.cheng at apple.com (Evan Cheng) Date: Tue, 4 Apr 2006 23:41:48 -0500 Subject: [llvm-commits] CVS: llvm/test/Regression/CodeGen/X86/vec_shuffle.ll Message-ID: <200604050441.XAA19652@zion.cs.uiuc.edu> Changes in directory llvm/test/Regression/CodeGen/X86: vec_shuffle.ll updated: 1.5 -> 1.6 --- Log message: Separate out to 2 test cases --- Diffs of the changes: (+1 -26) vec_shuffle.ll | 27 +-------------------------- 1 files changed, 1 insertion(+), 26 deletions(-) Index: llvm/test/Regression/CodeGen/X86/vec_shuffle.ll diff -u llvm/test/Regression/CodeGen/X86/vec_shuffle.ll:1.5 llvm/test/Regression/CodeGen/X86/vec_shuffle.ll:1.6 --- llvm/test/Regression/CodeGen/X86/vec_shuffle.ll:1.5 Tue Apr 4 20:44:57 2006 +++ llvm/test/Regression/CodeGen/X86/vec_shuffle.ll Tue Apr 4 23:40:55 2006 @@ -1,7 +1,6 @@ ; RUN: llvm-as < %s | llc -march=x86 -mattr=+sse2 | grep shufp | wc -l | grep 1 ; RUN: llvm-as < %s | llc -march=x86 -mattr=+sse2 | grep movhpd | wc -l | grep 1 -; RUN: llvm-as < %s | llc -march=x86 -mattr=+sse2 | grep pshufhw | wc -l | grep 2 -; RUN: llvm-as < %s | llc -march=x86 -mattr=+sse2 | grep pshuflw | wc -l | grep 1 +; RUN: llvm-as < %s | llc -march=x86 -mattr=+sse2 | grep pshufhw | wc -l | grep 1 void %test_v4sf(<4 x float>* %P, float %X, float %Y) { %tmp = insertelement <4 x float> zeroinitializer, float %X, uint 0 @@ -42,27 +41,3 @@ store <2 x long> %tmp15, <2 x long>* %res ret void } - -void %test_v8i16_2(<2 x long>* %res, <2 x long>* %A) { - %tmp = load <2 x long>* %A - %tmp = cast <2 x long> %tmp to <8 x short> - %tmp0 = extractelement <8 x short> %tmp, uint 0 - %tmp1 = extractelement <8 x short> %tmp, uint 1 - %tmp2 = extractelement <8 x short> %tmp, uint 2 - %tmp3 = extractelement <8 x short> %tmp, uint 3 - %tmp4 = extractelement <8 x short> %tmp, uint 4 - %tmp5 = extractelement <8 x short> %tmp, uint 5 - %tmp6 = extractelement <8 x short> %tmp, uint 6 - %tmp7 = extractelement <8 x short> %tmp, uint 7 - %tmp8 = insertelement <8 x short> undef, short %tmp2, uint 0 - %tmp9 = insertelement <8 x short> %tmp8, short %tmp1, uint 1 - %tmp10 = insertelement <8 x short> %tmp9, short %tmp0, uint 2 - %tmp11 = insertelement <8 x short> %tmp10, short %tmp3, uint 3 - %tmp12 = insertelement <8 x short> %tmp11, short %tmp6, uint 4 - %tmp13 = insertelement <8 x short> %tmp12, short %tmp5, uint 5 - %tmp14 = insertelement <8 x short> %tmp13, short %tmp4, uint 6 - %tmp15 = insertelement <8 x short> %tmp14, short %tmp7, uint 7 - %tmp15 = cast <8 x short> %tmp15 to <2 x long> - store <2 x long> %tmp15, <2 x long>* %res - ret void -} From jeffc at jolt-lang.org Wed Apr 5 00:20:11 2006 From: jeffc at jolt-lang.org (Jeff Cohen) Date: Wed, 5 Apr 2006 00:20:11 -0500 Subject: [llvm-commits] CVS: llvm/win32/x86/x86.vcproj Message-ID: <200604050520.AAA19789@zion.cs.uiuc.edu> Changes in directory llvm/win32/x86: x86.vcproj updated: 1.23 -> 1.24 --- Log message: Fix more tablegen depedency issues in Visual Studio. --- Diffs of the changes: (+2 -2) x86.vcproj | 4 ++-- 1 files changed, 2 insertions(+), 2 deletions(-) Index: llvm/win32/x86/x86.vcproj diff -u llvm/win32/x86/x86.vcproj:1.23 llvm/win32/x86/x86.vcproj:1.24 --- llvm/win32/x86/x86.vcproj:1.23 Sat Apr 1 23:20:53 2006 +++ llvm/win32/x86/x86.vcproj Wed Apr 5 00:19:18 2006 @@ -126,7 +126,7 @@ ..\$(IntDir)\TableGen.exe -gen-dag-isel -I ..\..\lib\Target\X86 -I ..\..\include $(InputPath) -o X86GenDAGISel.inc ..\$(IntDir)\TableGen.exe -gen-subtarget -I ..\..\lib\Target\X86 -I ..\..\include $(InputPath) -o X86GenSubtarget.inc " - AdditionalDependencies="$(InputDir)X86InstrInfo.td;$(InputDir)X86RegisterInfo.td;$(InputDir)..\Target.td;$(ProjectDir)..\$(IntDir)\TableGen.exe" + AdditionalDependencies="$(InputDir)X86InstrInfo.td;$(InputDir)X86RegisterInfo.td;$(InputDir)X86InstrFPStack.td;$(InputDir)X86InstrMMX.td;$(InputDir)X86InstrSSE.td;$(InputDir)..\Target.td;$(InputDir)..\TargetSchedule.td;$(InputDir)..\TargetScheduleDAG.td;$(ProjectDir)..\$(IntDir)\TableGen.exe" Outputs="X86GenRegisterNames.inc;X86GenRegisterInfo.h.inc;X86GenRegisterInfo.inc;X86GenInstrNames.inc;X86GenInstrInfo.inc;X86GenAsmWriter.inc;X86GenAsmWriter1.inc;X86GenDAGISel.inc;X86GenSubtarget.inc"/> From evan.cheng at apple.com Wed Apr 5 01:07:23 2006 From: evan.cheng at apple.com (Evan Cheng) Date: Wed, 5 Apr 2006 01:07:23 -0500 Subject: [llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp Message-ID: <200604050607.BAA19985@zion.cs.uiuc.edu> Changes in directory llvm/lib/CodeGen/SelectionDAG: LegalizeDAG.cpp updated: 1.352 -> 1.353 --- Log message: Exapnd a VECTOR_SHUFFLE to a BUILD_VECTOR if target asks for it to be expanded or custom lowering fails. --- Diffs of the changes: (+30 -2) LegalizeDAG.cpp | 32 ++++++++++++++++++++++++++++++-- 1 files changed, 30 insertions(+), 2 deletions(-) Index: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp diff -u llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.352 llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.353 --- llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.352 Tue Apr 4 12:23:26 2006 +++ llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp Wed Apr 5 01:07:11 2006 @@ -933,9 +933,37 @@ "vector shuffle should not be created if not legal!"); break; case TargetLowering::Custom: - Tmp1 = TLI.LowerOperation(Result, DAG); - if (Tmp1.Val) Result = Tmp1; + Tmp3 = TLI.LowerOperation(Result, DAG); + if (Tmp3.Val) { + Result = Tmp3; + break; + } + // FALLTHROUGH + case TargetLowering::Expand: { + MVT::ValueType VT = Node->getValueType(0); + MVT::ValueType EltVT = MVT::getVectorBaseType(VT); + MVT::ValueType PtrVT = TLI.getPointerTy(); + SDOperand Mask = Node->getOperand(2); + unsigned NumElems = Mask.getNumOperands(); + std::vector Ops; + for (unsigned i = 0; i != NumElems; ++i) { + SDOperand Arg = Mask.getOperand(i); + if (Arg.getOpcode() == ISD::UNDEF) { + Ops.push_back(DAG.getNode(ISD::UNDEF, EltVT)); + } else { + assert(isa(Arg) && "Invalid VECTOR_SHUFFLE mask!"); + unsigned Idx = cast(Arg)->getValue(); + if (Idx < NumElems) + Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, EltVT, Tmp1, + DAG.getConstant(Idx, PtrVT))); + else + Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, EltVT, Tmp2, + DAG.getConstant(Idx - NumElems, PtrVT))); + } + } + Result = DAG.getNode(ISD::BUILD_VECTOR, VT, Ops); break; + } case TargetLowering::Promote: { // Change base type to a different vector type. MVT::ValueType OVT = Node->getValueType(0); From evan.cheng at apple.com Wed Apr 5 01:08:26 2006 From: evan.cheng at apple.com (Evan Cheng) Date: Wed, 5 Apr 2006 01:08:26 -0500 Subject: [llvm-commits] CVS: llvm/lib/Target/X86/X86ISelLowering.cpp Message-ID: <200604050608.BAA20006@zion.cs.uiuc.edu> Changes in directory llvm/lib/Target/X86: X86ISelLowering.cpp updated: 1.154 -> 1.155 --- Log message: Fallthrough to expand if a VECTOR_SHUFFLE cannot be custom lowered. --- Diffs of the changes: (+14 -15) X86ISelLowering.cpp | 29 ++++++++++++++--------------- 1 files changed, 14 insertions(+), 15 deletions(-) Index: llvm/lib/Target/X86/X86ISelLowering.cpp diff -u llvm/lib/Target/X86/X86ISelLowering.cpp:1.154 llvm/lib/Target/X86/X86ISelLowering.cpp:1.155 --- llvm/lib/Target/X86/X86ISelLowering.cpp:1.154 Tue Apr 4 20:47:37 2006 +++ llvm/lib/Target/X86/X86ISelLowering.cpp Wed Apr 5 01:08:13 2006 @@ -1750,9 +1750,11 @@ /// NormalizeVectorShuffle - Swap vector_shuffle operands (as well as /// values in ther permute mask if needed. Use V1 as second vector if it is /// undef. Return an empty SDOperand is it is already well formed. -static SDOperand NormalizeVectorShuffle(SDOperand V1, SDOperand V2, - SDOperand Mask, MVT::ValueType VT, - SelectionDAG &DAG) { +static SDOperand NormalizeVectorShuffle(SDOperand Op, SelectionDAG &DAG) { + SDOperand V1 = Op.getOperand(0); + SDOperand V2 = Op.getOperand(1); + SDOperand Mask = Op.getOperand(2); + MVT::ValueType VT = Op.getValueType(); unsigned NumElems = Mask.getNumOperands(); SDOperand Half1 = Mask.getOperand(0); SDOperand Half2 = Mask.getOperand(NumElems/2); @@ -1778,7 +1780,7 @@ if (V2Undef) return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V1, Mask); - return SDOperand(); + return Op; } /// isPSHUFHW_PSHUFLWMask - true if the specified VECTOR_SHUFFLE operand @@ -2598,16 +2600,16 @@ if (V2.getOpcode() != ISD::UNDEF) return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, DAG.getNode(ISD::UNDEF, V1.getValueType()),PermMask); - return SDOperand(); + return Op; } if (X86::isUNPCKLMask(PermMask.Val) || X86::isUNPCKHMask(PermMask.Val)) // Leave the VECTOR_SHUFFLE alone. It matches {P}UNPCKL*. - return SDOperand(); + return Op; if (NumElems == 2) - return NormalizeVectorShuffle(V1, V2, PermMask, VT, DAG); + return NormalizeVectorShuffle(Op, DAG); // If VT is integer, try PSHUF* first, then SHUFP*. if (MVT::isInteger(VT)) { @@ -2617,11 +2619,11 @@ if (V2.getOpcode() != ISD::UNDEF) return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, DAG.getNode(ISD::UNDEF, V1.getValueType()),PermMask); - return SDOperand(); + return Op; } if (X86::isSHUFPMask(PermMask.Val)) - return NormalizeVectorShuffle(V1, V2, PermMask, VT, DAG); + return NormalizeVectorShuffle(Op, DAG); // Handle v8i16 shuffle high / low shuffle node pair. if (VT == MVT::v8i16 && isPSHUFHW_PSHUFLWMask(PermMask.Val)) { @@ -2645,19 +2647,18 @@ } else { // Floating point cases in the other order. if (X86::isSHUFPMask(PermMask.Val)) - return NormalizeVectorShuffle(V1, V2, PermMask, VT, DAG); + return NormalizeVectorShuffle(Op, DAG); if (X86::isPSHUFDMask(PermMask.Val) || X86::isPSHUFHWMask(PermMask.Val) || X86::isPSHUFLWMask(PermMask.Val)) { if (V2.getOpcode() != ISD::UNDEF) return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, DAG.getNode(ISD::UNDEF, V1.getValueType()),PermMask); - return SDOperand(); + return Op; } } - assert(0 && "Unexpected VECTOR_SHUFFLE to lower"); - abort(); + return SDOperand(); } case ISD::BUILD_VECTOR: { // All one's are handled with pcmpeqd. @@ -2922,8 +2923,6 @@ return (Mask.Val->getNumOperands() == 2 || X86::isSplatMask(Mask.Val) || X86::isPSHUFDMask(Mask.Val) || - X86::isPSHUFHWMask(Mask.Val) || - X86::isPSHUFLWMask(Mask.Val) || isPSHUFHW_PSHUFLWMask(Mask.Val) || X86::isSHUFPMask(Mask.Val) || X86::isUNPCKLMask(Mask.Val) || From evan.cheng at apple.com Wed Apr 5 01:09:39 2006 From: evan.cheng at apple.com (Evan Cheng) Date: Wed, 5 Apr 2006 01:09:39 -0500 Subject: [llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCISelLowering.cpp Message-ID: <200604050609.BAA20018@zion.cs.uiuc.edu> Changes in directory llvm/lib/Target/PowerPC: PPCISelLowering.cpp updated: 1.130 -> 1.131 --- Log message: Fallthrough to expand if a VECTOR_SHUFFLE cannot be custom lowered. --- Diffs of the changes: (+1 -1) PPCISelLowering.cpp | 2 +- 1 files changed, 1 insertion(+), 1 deletion(-) Index: llvm/lib/Target/PowerPC/PPCISelLowering.cpp diff -u llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.130 llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.131 --- llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.130 Tue Apr 4 17:28:35 2006 +++ llvm/lib/Target/PowerPC/PPCISelLowering.cpp Wed Apr 5 01:09:26 2006 @@ -757,7 +757,7 @@ (PPC::isSplatShuffleMask(PermMask.Val, 1) || PPC::isSplatShuffleMask(PermMask.Val, 2) || PPC::isSplatShuffleMask(PermMask.Val, 4))) - break; + return Op; // TODO: Handle more cases, and also handle cases that are cheaper to do as // multiple such instructions than as a constant pool load/vperm pair. From evan.cheng at apple.com Wed Apr 5 01:11:32 2006 From: evan.cheng at apple.com (Evan Cheng) Date: Wed, 5 Apr 2006 01:11:32 -0500 Subject: [llvm-commits] CVS: llvm/lib/Target/X86/X86ISelLowering.cpp Message-ID: <200604050611.BAA20059@zion.cs.uiuc.edu> Changes in directory llvm/lib/Target/X86: X86ISelLowering.cpp updated: 1.155 -> 1.156 --- Log message: Bogus assert --- Diffs of the changes: (+8 -5) X86ISelLowering.cpp | 13 ++++++++----- 1 files changed, 8 insertions(+), 5 deletions(-) Index: llvm/lib/Target/X86/X86ISelLowering.cpp diff -u llvm/lib/Target/X86/X86ISelLowering.cpp:1.155 llvm/lib/Target/X86/X86ISelLowering.cpp:1.156 --- llvm/lib/Target/X86/X86ISelLowering.cpp:1.155 Wed Apr 5 01:08:13 2006 +++ llvm/lib/Target/X86/X86ISelLowering.cpp Wed Apr 5 01:11:20 2006 @@ -2842,14 +2842,17 @@ uint64_t &KnownZero, uint64_t &KnownOne, unsigned Depth) const { - unsigned Opc = Op.getOpcode(); - KnownZero = KnownOne = 0; // Don't know anything. + assert((Opc >= ISD::BUILTIN_OP_END || + Opc == ISD::INTRINSIC_WO_CHAIN || + Opc == ISD::INTRINSIC_W_CHAIN || + Opc == ISD::INTRINSIC_VOID) && + "Should use MaskedValueIsZero if you don't know whether Op" + " is a target node!"); + KnownZero = KnownOne = 0; // Don't know anything. switch (Opc) { - default: - assert(Opc >= ISD::BUILTIN_OP_END && "Expected a target specific node"); - break; + default: break; case X86ISD::SETCC: KnownZero |= (MVT::getIntVTBitMask(Op.getValueType()) ^ 1ULL); break; From lattner at cs.uiuc.edu Wed Apr 5 01:54:26 2006 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Wed, 5 Apr 2006 01:54:26 -0500 Subject: [llvm-commits] CVS: llvm/test/Regression/CodeGen/X86/2006-04-04-CrossBlockCrash.ll Message-ID: <200604050654.BAA20247@zion.cs.uiuc.edu> Changes in directory llvm/test/Regression/CodeGen/X86: 2006-04-04-CrossBlockCrash.ll added (r1.1) --- Log message: new testcase --- Diffs of the changes: (+55 -0) 2006-04-04-CrossBlockCrash.ll | 55 ++++++++++++++++++++++++++++++++++++++++++ 1 files changed, 55 insertions(+) Index: llvm/test/Regression/CodeGen/X86/2006-04-04-CrossBlockCrash.ll diff -c /dev/null llvm/test/Regression/CodeGen/X86/2006-04-04-CrossBlockCrash.ll:1.1 *** /dev/null Wed Apr 5 01:54:24 2006 --- llvm/test/Regression/CodeGen/X86/2006-04-04-CrossBlockCrash.ll Wed Apr 5 01:54:14 2006 *************** *** 0 **** --- 1,55 ---- + ; RUN: llvm-as < %s | llc -march=x86 -mcpu=yonah + + target endian = little + target pointersize = 32 + target triple = "i686-apple-darwin8.6.1" + %struct.GLTColor4 = type { float, float, float, float } + %struct.GLTCoord3 = type { float, float, float } + %struct.__GLIContextRec = type { { %struct.anon, { [24 x [16 x float]], [24 x [16 x float]] }, %struct.GLTColor4, { float, float, float, float, %struct.GLTCoord3, float } }, { float, float, float, float, float, float, float, float, [4 x uint], [4 x uint], [4 x uint] } } + %struct.__GLvertex = type { %struct.GLTColor4, %struct.GLTColor4, %struct.GLTColor4, %struct.GLTColor4, %struct.GLTColor4, %struct.GLTCoord3, float, %struct.GLTColor4, float, float, float, ubyte, ubyte, ubyte, ubyte, [4 x float], [2 x sbyte*], uint, uint, [16 x %struct.GLTColor4] } + %struct.anon = type { float, float, float, float, float, float, float, float } + + implementation ; Functions: + + declare <4 x float> %llvm.x86.sse.cmp.ps(<4 x float>, <4 x float>, sbyte) + + declare <4 x int> %llvm.x86.sse2.packssdw.128(<4 x int>, <4 x int>) + + declare int %llvm.x86.sse2.pmovmskb.128(<16 x sbyte>) + + void %gleLLVMVecInterpolateClip() { + entry: + br bool false, label %cond_false, label %cond_false183 + + cond_false: ; preds = %entry + br bool false, label %cond_false183, label %cond_true69 + + cond_true69: ; preds = %cond_false + ret void + + cond_false183: ; preds = %cond_false, %entry + %vuizmsk.0.1 = phi <4 x int> [ < int -1, int -1, int -1, int 0 >, %entry ], [ < int -1, int 0, int 0, int 0 >, %cond_false ] ; <<4 x int>> [#uses=2] + %tmp192 = extractelement <4 x int> %vuizmsk.0.1, uint 2 ; [#uses=1] + %tmp193 = extractelement <4 x int> %vuizmsk.0.1, uint 3 ; [#uses=2] + %tmp195 = insertelement <4 x int> zeroinitializer, int %tmp192, uint 1 ; <<4 x int>> [#uses=1] + %tmp196 = insertelement <4 x int> %tmp195, int %tmp193, uint 2 ; <<4 x int>> [#uses=1] + %tmp197 = insertelement <4 x int> %tmp196, int %tmp193, uint 3 ; <<4 x int>> [#uses=1] + %tmp336 = and <4 x int> zeroinitializer, %tmp197 ; <<4 x int>> [#uses=1] + %tmp337 = cast <4 x int> %tmp336 to <4 x float> ; <<4 x float>> [#uses=1] + %tmp378 = tail call <4 x float> %llvm.x86.sse.cmp.ps( <4 x float> %tmp337, <4 x float> zeroinitializer, sbyte 1 ) ; <<4 x float>> [#uses=1] + %tmp379 = cast <4 x float> %tmp378 to <4 x int> ; <<4 x int>> [#uses=1] + %tmp388 = tail call <4 x int> %llvm.x86.sse2.packssdw.128( <4 x int> zeroinitializer, <4 x int> %tmp379 ) ; <<4 x int>> [#uses=1] + %tmp392 = cast <4 x int> %tmp388 to <8 x short> ; <<8 x short>> [#uses=1] + %tmp399 = extractelement <8 x short> %tmp392, uint 7 ; [#uses=1] + %tmp423 = insertelement <8 x short> zeroinitializer, short %tmp399, uint 7 ; <<8 x short>> [#uses=1] + %tmp427 = cast <8 x short> %tmp423 to <16 x sbyte> ; <<16 x sbyte>> [#uses=1] + %tmp428 = tail call int %llvm.x86.sse2.pmovmskb.128( <16 x sbyte> %tmp427 ) ; [#uses=1] + %tmp432 = cast int %tmp428 to sbyte ; [#uses=1] + %tmp = and sbyte %tmp432, 42 ; [#uses=1] + %tmp436 = cast sbyte %tmp to ubyte ; [#uses=1] + %tmp446 = cast ubyte %tmp436 to uint ; [#uses=1] + %tmp447 = shl uint %tmp446, ubyte 24 ; [#uses=1] + %tmp449 = or uint 0, %tmp447 ; [#uses=1] + store uint %tmp449, uint* null + ret void + } From lattner at cs.uiuc.edu Wed Apr 5 01:54:55 2006 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Wed, 5 Apr 2006 01:54:55 -0500 Subject: [llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp Message-ID: <200604050654.BAA20257@zion.cs.uiuc.edu> Changes in directory llvm/lib/CodeGen/SelectionDAG: SelectionDAGISel.cpp updated: 1.217 -> 1.218 --- Log message: Make a vector live across blocks have the correct Vec type. This fixes CodeGen/X86/2006-04-04-CrossBlockCrash.ll --- Diffs of the changes: (+9 -1) SelectionDAGISel.cpp | 10 +++++++++- 1 files changed, 9 insertions(+), 1 deletion(-) Index: llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp diff -u llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.217 llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.218 --- llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.217 Sat Apr 1 21:41:14 2006 +++ llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp Wed Apr 5 01:54:42 2006 @@ -648,7 +648,8 @@ // Otherwise, if this is a vector, make it available as a generic vector // here. MVT::ValueType PTyElementVT, PTyLegalElementVT; - unsigned NE = TLI.getPackedTypeBreakdown(cast(VTy),PTyElementVT, + const PackedType *PTy = cast(VTy); + unsigned NE = TLI.getPackedTypeBreakdown(PTy, PTyElementVT, PTyLegalElementVT); // Build a VBUILD_VECTOR with the input registers. @@ -684,6 +685,13 @@ Ops.push_back(DAG.getConstant(NE, MVT::i32)); Ops.push_back(DAG.getValueType(PTyLegalElementVT)); N = DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector, Ops); + + // Finally, use a VBIT_CONVERT to make this available as the appropriate + // vector type. + N = DAG.getNode(ISD::VBIT_CONVERT, MVT::Vector, N, + DAG.getConstant(PTy->getNumElements(), + MVT::i32), + DAG.getValueType(TLI.getValueType(PTy->getElementType()))); } return N; From evan.cheng at apple.com Wed Apr 5 02:20:19 2006 From: evan.cheng at apple.com (Evan Cheng) Date: Wed, 5 Apr 2006 02:20:19 -0500 Subject: [llvm-commits] CVS: llvm/lib/Target/X86/X86ISelLowering.cpp X86ISelLowering.h X86InstrSSE.td Message-ID: <200604050720.CAA24631@zion.cs.uiuc.edu> Changes in directory llvm/lib/Target/X86: X86ISelLowering.cpp updated: 1.156 -> 1.157 X86ISelLowering.h updated: 1.50 -> 1.51 X86InstrSSE.td updated: 1.61 -> 1.62 --- Log message: Handle canonical form of e.g. vector_shuffle v1, v1, <0, 4, 1, 5, 2, 6, 3, 7> This is turned into vector_shuffle v1, , <0, 0, 1, 1, 2, 2, 3, 3> by dag combiner. It would match a {p}unpckl on x86. --- Diffs of the changes: (+56 -0) X86ISelLowering.cpp | 33 +++++++++++++++++++++++++++++++++ X86ISelLowering.h | 5 +++++ X86InstrSSE.td | 18 ++++++++++++++++++ 3 files changed, 56 insertions(+) Index: llvm/lib/Target/X86/X86ISelLowering.cpp diff -u llvm/lib/Target/X86/X86ISelLowering.cpp:1.156 llvm/lib/Target/X86/X86ISelLowering.cpp:1.157 --- llvm/lib/Target/X86/X86ISelLowering.cpp:1.156 Wed Apr 5 01:11:20 2006 +++ llvm/lib/Target/X86/X86ISelLowering.cpp Wed Apr 5 02:20:06 2006 @@ -1664,6 +1664,37 @@ return true; } +/// isUNPCKL_v_undef_Mask - Special case of isUNPCKLMask for canonical form +/// of vector_shuffle v, v, <0, 4, 1, 5>, i.e. vector_shuffle v, undef, +/// <0, 0, 1, 1> +bool X86::isUNPCKL_v_undef_Mask(SDNode *N) { + assert(N->getOpcode() == ISD::BUILD_VECTOR); + + unsigned NumElems = N->getNumOperands(); + if (NumElems != 4 && NumElems != 8 && NumElems != 16) + return false; + + for (unsigned i = 0, j = 0; i != NumElems; i += 2, ++j) { + SDOperand BitI = N->getOperand(i); + SDOperand BitI1 = N->getOperand(i+1); + + if (BitI.getOpcode() != ISD::UNDEF) { + assert(isa(BitI) && "Invalid VECTOR_SHUFFLE mask!"); + if (cast(BitI)->getValue() != j) + return false; + } + + if (BitI1.getOpcode() != ISD::UNDEF) { + assert(isa(BitI1) && "Invalid VECTOR_SHUFFLE mask!"); + if (cast(BitI1)->getValue() != j) + return false; + } + } + + return true; +} + + /// isSplatMask - Return true if the specified VECTOR_SHUFFLE operand specifies /// a splat of a single element. bool X86::isSplatMask(SDNode *N) { @@ -2604,6 +2635,7 @@ } if (X86::isUNPCKLMask(PermMask.Val) || + X86::isUNPCKL_v_undef_Mask(PermMask.Val) || X86::isUNPCKHMask(PermMask.Val)) // Leave the VECTOR_SHUFFLE alone. It matches {P}UNPCKL*. return Op; @@ -2929,5 +2961,6 @@ isPSHUFHW_PSHUFLWMask(Mask.Val) || X86::isSHUFPMask(Mask.Val) || X86::isUNPCKLMask(Mask.Val) || + X86::isUNPCKL_v_undef_Mask(Mask.Val) || X86::isUNPCKHMask(Mask.Val)); } Index: llvm/lib/Target/X86/X86ISelLowering.h diff -u llvm/lib/Target/X86/X86ISelLowering.h:1.50 llvm/lib/Target/X86/X86ISelLowering.h:1.51 --- llvm/lib/Target/X86/X86ISelLowering.h:1.50 Fri Mar 31 15:55:24 2006 +++ llvm/lib/Target/X86/X86ISelLowering.h Wed Apr 5 02:20:06 2006 @@ -220,6 +220,11 @@ /// specifies a shuffle of elements that is suitable for input to UNPCKH. bool isUNPCKHMask(SDNode *N); + /// isUNPCKL_v_undef_Mask - Special case of isUNPCKLMask for canonical form + /// of vector_shuffle v, v, <0, 4, 1, 5>, i.e. vector_shuffle v, undef, + /// <0, 0, 1, 1> + bool isUNPCKL_v_undef_Mask(SDNode *N); + /// isSplatMask - Return true if the specified VECTOR_SHUFFLE operand /// specifies a splat of a single element. bool isSplatMask(SDNode *N); Index: llvm/lib/Target/X86/X86InstrSSE.td diff -u llvm/lib/Target/X86/X86InstrSSE.td:1.61 llvm/lib/Target/X86/X86InstrSSE.td:1.62 --- llvm/lib/Target/X86/X86InstrSSE.td:1.61 Tue Apr 4 16:49:39 2006 +++ llvm/lib/Target/X86/X86InstrSSE.td Wed Apr 5 02:20:06 2006 @@ -100,6 +100,10 @@ return X86::isUNPCKHMask(N); }]>; +def UNPCKL_v_undef_shuffle_mask : PatLeaf<(build_vector), [{ + return X86::isUNPCKL_v_undef_Mask(N); +}]>; + def PSHUFD_shuffle_mask : PatLeaf<(build_vector), [{ return X86::isPSHUFDMask(N); }], SHUFFLE_get_shuf_imm>; @@ -1733,6 +1737,20 @@ (v4f32 (PSHUFLWmi addr:$src1, PSHUFLW_fp_shuffle_mask:$sm))>, Requires<[HasSSE2]>; +// vector_shuffle v1, , <0, 0, 1, 1, ...> +def : Pat<(v4f32 (vector_shuffle VR128:$src, (undef), + UNPCKL_v_undef_shuffle_mask)), + (UNPCKLPSrr VR128:$src, VR128:$src)>, Requires<[HasSSE2]>; +def : Pat<(v16i8 (vector_shuffle VR128:$src, (undef), + UNPCKL_v_undef_shuffle_mask)), + (PUNPCKLBWrr VR128:$src, VR128:$src)>, Requires<[HasSSE2]>; +def : Pat<(v8i16 (vector_shuffle VR128:$src, (undef), + UNPCKL_v_undef_shuffle_mask)), + (PUNPCKLWDrr VR128:$src, VR128:$src)>, Requires<[HasSSE2]>; +def : Pat<(v4i32 (vector_shuffle VR128:$src, (undef), + UNPCKL_v_undef_shuffle_mask)), + (PUNPCKLDQrr VR128:$src, VR128:$src)>, Requires<[HasSSE1]>; + // 128-bit logical shifts def : Pat<(int_x86_sse2_psll_dq VR128:$src1, imm:$src2), (v2i64 (PSLLDQri VR128:$src1, (PSxLDQ_imm imm:$src2)))>; From lattner at cs.uiuc.edu Wed Apr 5 12:39:03 2006 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Wed, 5 Apr 2006 12:39:03 -0500 Subject: [llvm-commits] CVS: llvm/test/Regression/CodeGen/PowerPC/2006-04-05-splat-ish.ll Message-ID: <200604051739.MAA00414@zion.cs.uiuc.edu> Changes in directory llvm/test/Regression/CodeGen/PowerPC: 2006-04-05-splat-ish.ll added (r1.1) --- Log message: new testcase that was miscompiled to vspltisb --- Diffs of the changes: (+8 -0) 2006-04-05-splat-ish.ll | 8 ++++++++ 1 files changed, 8 insertions(+) Index: llvm/test/Regression/CodeGen/PowerPC/2006-04-05-splat-ish.ll diff -c /dev/null llvm/test/Regression/CodeGen/PowerPC/2006-04-05-splat-ish.ll:1.1 *** /dev/null Wed Apr 5 12:39:00 2006 --- llvm/test/Regression/CodeGen/PowerPC/2006-04-05-splat-ish.ll Wed Apr 5 12:38:50 2006 *************** *** 0 **** --- 1,8 ---- + ; RUN: llvm-as < %s | llc -march=ppc32 -mcpu=g5 | grep 'vspltish v.*, 10' + + void %test(<8 x short>* %P) { + %tmp = load <8 x short>* %P ; <<8 x short>> [#uses=1] + %tmp1 = add <8 x short> %tmp, < short 10, short 10, short 10, short 10, short 10, short 10, short 10, short 10 > ; <<8 x short>> [#uses=1] + store <8 x short> %tmp1, <8 x short>* %P + ret void + } From lattner at cs.uiuc.edu Wed Apr 5 12:39:38 2006 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Wed, 5 Apr 2006 12:39:38 -0500 Subject: [llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCISelLowering.cpp Message-ID: <200604051739.MAA00504@zion.cs.uiuc.edu> Changes in directory llvm/lib/Target/PowerPC: PPCISelLowering.cpp updated: 1.131 -> 1.132 --- Log message: Fix CodeGen/PowerPC/2006-04-05-splat-ish.ll --- Diffs of the changes: (+2 -2) PPCISelLowering.cpp | 4 ++-- 1 files changed, 2 insertions(+), 2 deletions(-) Index: llvm/lib/Target/PowerPC/PPCISelLowering.cpp diff -u llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.131 llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.132 --- llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.131 Wed Apr 5 01:09:26 2006 +++ llvm/lib/Target/PowerPC/PPCISelLowering.cpp Wed Apr 5 12:39:25 2006 @@ -353,8 +353,8 @@ ValSizeInBytes >>= 1; // If the top half equals the bottom half, we're still ok. - if (((Value >> (ValSizeInBytes*8)) & (1 << (8*ValSizeInBytes)-1)) != - (Value & (1 << (8*ValSizeInBytes)-1))) + if (((Value >> (ValSizeInBytes*8)) & ((1 << (8*ValSizeInBytes))-1)) != + (Value & ((1 << (8*ValSizeInBytes))-1))) return false; } From lattner at cs.uiuc.edu Wed Apr 5 15:15:37 2006 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Wed, 5 Apr 2006 15:15:37 -0500 Subject: [llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCInstrAltivec.td Message-ID: <200604052015.PAA01221@zion.cs.uiuc.edu> Changes in directory llvm/lib/Target/PowerPC: PPCInstrAltivec.td updated: 1.39 -> 1.40 --- Log message: Fix a typo --- Diffs of the changes: (+1 -1) PPCInstrAltivec.td | 2 +- 1 files changed, 1 insertion(+), 1 deletion(-) Index: llvm/lib/Target/PowerPC/PPCInstrAltivec.td diff -u llvm/lib/Target/PowerPC/PPCInstrAltivec.td:1.39 llvm/lib/Target/PowerPC/PPCInstrAltivec.td:1.40 --- llvm/lib/Target/PowerPC/PPCInstrAltivec.td:1.39 Tue Apr 4 20:16:22 2006 +++ llvm/lib/Target/PowerPC/PPCInstrAltivec.td Wed Apr 5 15:15:25 2006 @@ -123,7 +123,7 @@ [(set VRRC:$vD, (int_ppc_altivec_lvsl xoaddr:$src))]>, PPC970_Unit_LSU; def LVSR : XForm_1<31, 38, (ops VRRC:$vD, memrr:$src), - "lvsl $vD, $src", LdStGeneral, + "lvsr $vD, $src", LdStGeneral, [(set VRRC:$vD, (int_ppc_altivec_lvsr xoaddr:$src))]>, PPC970_Unit_LSU; From lattner at cs.uiuc.edu Wed Apr 5 17:18:14 2006 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Wed, 5 Apr 2006 17:18:14 -0500 Subject: [llvm-commits] CVS: llvm/include/llvm/IntrinsicsPowerPC.td Message-ID: <200604052218.RAA02604@zion.cs.uiuc.edu> Changes in directory llvm/include/llvm: IntrinsicsPowerPC.td updated: 1.20 -> 1.21 --- Log message: add altivec ds* intrinsics --- Diffs of the changes: (+18 -0) IntrinsicsPowerPC.td | 18 ++++++++++++++++++ 1 files changed, 18 insertions(+) Index: llvm/include/llvm/IntrinsicsPowerPC.td diff -u llvm/include/llvm/IntrinsicsPowerPC.td:1.20 llvm/include/llvm/IntrinsicsPowerPC.td:1.21 --- llvm/include/llvm/IntrinsicsPowerPC.td:1.20 Tue Apr 4 20:15:54 2006 +++ llvm/include/llvm/IntrinsicsPowerPC.td Wed Apr 5 17:18:01 2006 @@ -66,6 +66,24 @@ // PowerPC Altivec Intrinsic Definitions. let TargetPrefix = "ppc" in { // All intrinsics start with "llvm.ppc.". + // Data Stream Control. + def int_ppc_altivec_dss : GCCBuiltin<"__builtin_altivec_dss">, + Intrinsic<[llvm_void_ty, llvm_int_ty], [IntrWriteMem]>; + def int_ppc_altivec_dssall : GCCBuiltin<"__builtin_altivec_dssall">, + Intrinsic<[llvm_void_ty], [IntrWriteMem]>; + def int_ppc_altivec_dst : GCCBuiltin<"__builtin_altivec_dst">, + Intrinsic<[llvm_void_ty, llvm_ptr_ty, llvm_int_ty, llvm_int_ty], + [IntrWriteMem]>; + def int_ppc_altivec_dstt : GCCBuiltin<"__builtin_altivec_dstt">, + Intrinsic<[llvm_void_ty, llvm_ptr_ty, llvm_int_ty, llvm_int_ty], + [IntrWriteMem]>; + def int_ppc_altivec_dstst : GCCBuiltin<"__builtin_altivec_dstst">, + Intrinsic<[llvm_void_ty, llvm_ptr_ty, llvm_int_ty, llvm_int_ty], + [IntrWriteMem]>; + def int_ppc_altivec_dststt : GCCBuiltin<"__builtin_altivec_dststt">, + Intrinsic<[llvm_void_ty, llvm_ptr_ty, llvm_int_ty, llvm_int_ty], + [IntrWriteMem]>; + // VSCR access. def int_ppc_altivec_mfvscr : GCCBuiltin<"__builtin_altivec_mfvscr">, Intrinsic<[llvm_v8i16_ty], [IntrReadMem]>; From lattner at cs.uiuc.edu Wed Apr 5 17:27:27 2006 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Wed, 5 Apr 2006 17:27:27 -0500 Subject: [llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCInstrAltivec.td PPCInstrFormats.td README_ALTIVEC.txt Message-ID: <200604052227.RAA02688@zion.cs.uiuc.edu> Changes in directory llvm/lib/Target/PowerPC: PPCInstrAltivec.td updated: 1.40 -> 1.41 PPCInstrFormats.td updated: 1.72 -> 1.73 README_ALTIVEC.txt updated: 1.14 -> 1.15 --- Log message: Add all of the data stream intrinsics and instructions. woo --- Diffs of the changes: (+43 -7) PPCInstrAltivec.td | 21 +++++++++++++++++++++ PPCInstrFormats.td | 22 ++++++++++++++++++++++ README_ALTIVEC.txt | 7 ------- 3 files changed, 43 insertions(+), 7 deletions(-) Index: llvm/lib/Target/PowerPC/PPCInstrAltivec.td diff -u llvm/lib/Target/PowerPC/PPCInstrAltivec.td:1.40 llvm/lib/Target/PowerPC/PPCInstrAltivec.td:1.41 --- llvm/lib/Target/PowerPC/PPCInstrAltivec.td:1.40 Wed Apr 5 15:15:25 2006 +++ llvm/lib/Target/PowerPC/PPCInstrAltivec.td Wed Apr 5 17:27:14 2006 @@ -93,6 +93,15 @@ def IMPLICIT_DEF_VRRC : Pseudo<(ops VRRC:$rD), "; $rD = IMPLICIT_DEF_VRRC", [(set VRRC:$rD, (v4f32 (undef)))]>; +let noResults = 1 in { +def DSS : DSS_Form<822, (ops u5imm:$A, u5imm:$STRM,u5imm:$ZERO1,u5imm:$ZERO2), + "dss $STRM, $A", LdStGeneral /*FIXME*/, []>; +def DST : DSS_Form<342, (ops u5imm:$T, u5imm:$STRM, GPRC:$rA, GPRC:$rB), + "dst $rA, $rB, $STRM, $T", LdStGeneral /*FIXME*/, []>; +def DSTST : DSS_Form<374, (ops u5imm:$T, u5imm:$STRM, GPRC:$rA, GPRC:$rB), + "dstst $rA, $rB, $STRM, $T", LdStGeneral /*FIXME*/, []>; +} + def MFVSCR : VXForm_4<1540, (ops VRRC:$vD), "mfvcr $vD", LdStGeneral, [(set VRRC:$vD, (int_ppc_altivec_mfvscr))]>; @@ -431,6 +440,18 @@ // Additional Altivec Patterns // +// DS* intrinsics. +def : Pat<(int_ppc_altivec_dss imm:$STRM), (DSS 0, imm:$STRM, 0, 0)>; +def : Pat<(int_ppc_altivec_dssall), (DSS 1, 0, 0, 0)>; +def : Pat<(int_ppc_altivec_dst GPRC:$rA, GPRC:$rB, imm:$STRM), + (DST 0, imm:$STRM, GPRC:$rA, GPRC:$rB)>; +def : Pat<(int_ppc_altivec_dstt GPRC:$rA, GPRC:$rB, imm:$STRM), + (DST 1, imm:$STRM, GPRC:$rA, GPRC:$rB)>; +def : Pat<(int_ppc_altivec_dstst GPRC:$rA, GPRC:$rB, imm:$STRM), + (DSTST 0, imm:$STRM, GPRC:$rA, GPRC:$rB)>; +def : Pat<(int_ppc_altivec_dststt GPRC:$rA, GPRC:$rB, imm:$STRM), + (DSTST 1, imm:$STRM, GPRC:$rA, GPRC:$rB)>; + // Undef/Zero. def : Pat<(v16i8 (undef)), (v16i8 (IMPLICIT_DEF_VRRC))>; def : Pat<(v8i16 (undef)), (v8i16 (IMPLICIT_DEF_VRRC))>; Index: llvm/lib/Target/PowerPC/PPCInstrFormats.td diff -u llvm/lib/Target/PowerPC/PPCInstrFormats.td:1.72 llvm/lib/Target/PowerPC/PPCInstrFormats.td:1.73 --- llvm/lib/Target/PowerPC/PPCInstrFormats.td:1.72 Tue Apr 4 19:03:57 2006 +++ llvm/lib/Target/PowerPC/PPCInstrFormats.td Wed Apr 5 17:27:14 2006 @@ -325,6 +325,26 @@ : XForm_base_r3xo { } +// DSS_Form - Form X instruction, used for altivec dss* instructions. +class DSS_Form xo, dag OL, string asmstr, + InstrItinClass itin, list pattern> + : I<31, OL, asmstr, itin> { + bits<1> T; + bits<2> STRM; + bits<5> A; + bits<5> B; + + let Pattern = pattern; + + let Inst{6} = T; + let Inst{7-8} = 0; + let Inst{9-10} = STRM; + let Inst{11-15} = A; + let Inst{16-20} = B; + let Inst{21-30} = xo; + let Inst{31} = 0; +} + // 1.7.7 XL-Form class XLForm_1 opcode, bits<10> xo, dag OL, string asmstr, InstrItinClass itin> @@ -589,6 +609,8 @@ let Inst{31} = RC; } + + // E-1 VA-Form // VAForm_1 - DACB ordering. Index: llvm/lib/Target/PowerPC/README_ALTIVEC.txt diff -u llvm/lib/Target/PowerPC/README_ALTIVEC.txt:1.14 llvm/lib/Target/PowerPC/README_ALTIVEC.txt:1.15 --- llvm/lib/Target/PowerPC/README_ALTIVEC.txt:1.14 Tue Apr 4 19:49:48 2006 +++ llvm/lib/Target/PowerPC/README_ALTIVEC.txt Wed Apr 5 17:27:14 2006 @@ -47,13 +47,6 @@ //===----------------------------------------------------------------------===// -Missing intrinsics: - -ds* -vsel (some aliases only accessible using builtins) - -//===----------------------------------------------------------------------===// - FABS/FNEG can be codegen'd with the appropriate and/xor of -0.0. //===----------------------------------------------------------------------===// From evan.cheng at apple.com Wed Apr 5 18:37:31 2006 From: evan.cheng at apple.com (Evan Cheng) Date: Wed, 5 Apr 2006 18:37:31 -0500 Subject: [llvm-commits] CVS: llvm/include/llvm/IntrinsicsX86.td Message-ID: <200604052337.SAA02900@zion.cs.uiuc.edu> Changes in directory llvm/include/llvm: IntrinsicsX86.td updated: 1.9 -> 1.10 --- Log message: Added comi and ucomi SSE intrinsics. --- Diffs of the changes: (+83 -1) IntrinsicsX86.td | 84 ++++++++++++++++++++++++++++++++++++++++++++++++++++++- 1 files changed, 83 insertions(+), 1 deletion(-) Index: llvm/include/llvm/IntrinsicsX86.td diff -u llvm/include/llvm/IntrinsicsX86.td:1.9 llvm/include/llvm/IntrinsicsX86.td:1.10 --- llvm/include/llvm/IntrinsicsX86.td:1.9 Tue Apr 4 16:48:31 2006 +++ llvm/include/llvm/IntrinsicsX86.td Wed Apr 5 18:37:18 2006 @@ -69,6 +69,42 @@ def int_x86_sse_cmp_ps : Intrinsic<[llvm_v4f32_ty, llvm_v4f32_ty, llvm_v4f32_ty, llvm_sbyte_ty], [InstrNoMem]>; + def int_x86_sse_comieq_ss : GCCBuiltin<"__builtin_ia32_comieq">, + Intrinsic<[llvm_int_ty, llvm_v4f32_ty, + llvm_v4f32_ty], [InstrNoMem]>; + def int_x86_sse_comilt_ss : GCCBuiltin<"__builtin_ia32_comilt">, + Intrinsic<[llvm_int_ty, llvm_v4f32_ty, + llvm_v4f32_ty], [InstrNoMem]>; + def int_x86_sse_comile_ss : GCCBuiltin<"__builtin_ia32_comile">, + Intrinsic<[llvm_int_ty, llvm_v4f32_ty, + llvm_v4f32_ty], [InstrNoMem]>; + def int_x86_sse_comigt_ss : GCCBuiltin<"__builtin_ia32_comigt">, + Intrinsic<[llvm_int_ty, llvm_v4f32_ty, + llvm_v4f32_ty], [InstrNoMem]>; + def int_x86_sse_comige_ss : GCCBuiltin<"__builtin_ia32_comige">, + Intrinsic<[llvm_int_ty, llvm_v4f32_ty, + llvm_v4f32_ty], [InstrNoMem]>; + def int_x86_sse_comineq_ss : GCCBuiltin<"__builtin_ia32_comineq">, + Intrinsic<[llvm_int_ty, llvm_v4f32_ty, + llvm_v4f32_ty], [InstrNoMem]>; + def int_x86_sse_ucomieq_ss : GCCBuiltin<"__builtin_ia32_ucomieq">, + Intrinsic<[llvm_int_ty, llvm_v4f32_ty, + llvm_v4f32_ty], [InstrNoMem]>; + def int_x86_sse_ucomilt_ss : GCCBuiltin<"__builtin_ia32_ucomilt">, + Intrinsic<[llvm_int_ty, llvm_v4f32_ty, + llvm_v4f32_ty], [InstrNoMem]>; + def int_x86_sse_ucomile_ss : GCCBuiltin<"__builtin_ia32_ucomile">, + Intrinsic<[llvm_int_ty, llvm_v4f32_ty, + llvm_v4f32_ty], [InstrNoMem]>; + def int_x86_sse_ucomigt_ss : GCCBuiltin<"__builtin_ia32_ucomigt">, + Intrinsic<[llvm_int_ty, llvm_v4f32_ty, + llvm_v4f32_ty], [InstrNoMem]>; + def int_x86_sse_ucomige_ss : GCCBuiltin<"__builtin_ia32_ucomige">, + Intrinsic<[llvm_int_ty, llvm_v4f32_ty, + llvm_v4f32_ty], [InstrNoMem]>; + def int_x86_sse_ucomineq_ss : GCCBuiltin<"__builtin_ia32_ucomineq">, + Intrinsic<[llvm_int_ty, llvm_v4f32_ty, + llvm_v4f32_ty], [InstrNoMem]>; } @@ -137,7 +173,7 @@ //===----------------------------------------------------------------------===// // SSE2 -// Arithmetic ops +// FP arithmetic ops let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.". def int_x86_sse2_add_sd : GCCBuiltin<"__builtin_ia32_addsd">, Intrinsic<[llvm_v2f64_ty, llvm_v2f64_ty, @@ -183,6 +219,52 @@ llvm_v2f64_ty], [InstrNoMem]>; } +// FP comparison ops +let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.". + def int_x86_sse2_cmp_sd : + Intrinsic<[llvm_v2f64_ty, llvm_v2f64_ty, + llvm_v2f64_ty, llvm_sbyte_ty], [InstrNoMem]>; + def int_x86_sse2_cmp_pd : + Intrinsic<[llvm_v2f64_ty, llvm_v2f64_ty, + llvm_v2f64_ty, llvm_sbyte_ty], [InstrNoMem]>; + def int_x86_sse2_comieq_sd : GCCBuiltin<"__builtin_ia32_comisdeq">, + Intrinsic<[llvm_int_ty, llvm_v2f64_ty, + llvm_v2f64_ty], [InstrNoMem]>; + def int_x86_sse2_comilt_sd : GCCBuiltin<"__builtin_ia32_comisdlt">, + Intrinsic<[llvm_int_ty, llvm_v2f64_ty, + llvm_v2f64_ty], [InstrNoMem]>; + def int_x86_sse2_comile_sd : GCCBuiltin<"__builtin_ia32_comisdle">, + Intrinsic<[llvm_int_ty, llvm_v2f64_ty, + llvm_v2f64_ty], [InstrNoMem]>; + def int_x86_sse2_comigt_sd : GCCBuiltin<"__builtin_ia32_comisdgt">, + Intrinsic<[llvm_int_ty, llvm_v2f64_ty, + llvm_v2f64_ty], [InstrNoMem]>; + def int_x86_sse2_comige_sd : GCCBuiltin<"__builtin_ia32_comisdge">, + Intrinsic<[llvm_int_ty, llvm_v2f64_ty, + llvm_v2f64_ty], [InstrNoMem]>; + def int_x86_sse2_comineq_sd : GCCBuiltin<"__builtin_ia32_comisdneq">, + Intrinsic<[llvm_int_ty, llvm_v2f64_ty, + llvm_v2f64_ty], [InstrNoMem]>; + def int_x86_sse2_ucomieq_sd : GCCBuiltin<"__builtin_ia32_ucomisdeq">, + Intrinsic<[llvm_int_ty, llvm_v2f64_ty, + llvm_v2f64_ty], [InstrNoMem]>; + def int_x86_sse2_ucomilt_sd : GCCBuiltin<"__builtin_ia32_ucomisdlt">, + Intrinsic<[llvm_int_ty, llvm_v2f64_ty, + llvm_v2f64_ty], [InstrNoMem]>; + def int_x86_sse2_ucomile_sd : GCCBuiltin<"__builtin_ia32_ucomisdle">, + Intrinsic<[llvm_int_ty, llvm_v2f64_ty, + llvm_v2f64_ty], [InstrNoMem]>; + def int_x86_sse2_ucomigt_sd : GCCBuiltin<"__builtin_ia32_ucomisdgt">, + Intrinsic<[llvm_int_ty, llvm_v2f64_ty, + llvm_v2f64_ty], [InstrNoMem]>; + def int_x86_sse2_ucomige_sd : GCCBuiltin<"__builtin_ia32_ucomisdge">, + Intrinsic<[llvm_int_ty, llvm_v2f64_ty, + llvm_v2f64_ty], [InstrNoMem]>; + def int_x86_sse2_ucomineq_sd : GCCBuiltin<"__builtin_ia32_ucomisdneq">, + Intrinsic<[llvm_int_ty, llvm_v2f64_ty, + llvm_v2f64_ty], [InstrNoMem]>; +} + // Integer shift ops. let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.". def int_x86_sse2_psll_dq : GCCBuiltin<"__builtin_ia32_pslldqi128">, From evan.cheng at apple.com Wed Apr 5 18:38:58 2006 From: evan.cheng at apple.com (Evan Cheng) Date: Wed, 5 Apr 2006 18:38:58 -0500 Subject: [llvm-commits] CVS: llvm/lib/Target/X86/X86ISelLowering.cpp X86ISelLowering.h X86InstrSSE.td Message-ID: <200604052338.SAA02920@zion.cs.uiuc.edu> Changes in directory llvm/lib/Target/X86: X86ISelLowering.cpp updated: 1.157 -> 1.158 X86ISelLowering.h updated: 1.51 -> 1.52 X86InstrSSE.td updated: 1.62 -> 1.63 --- Log message: Support for comi / ucomi intrinsics. --- Diffs of the changes: (+158 -10) X86ISelLowering.cpp | 133 +++++++++++++++++++++++++++++++++++++++++++++++++--- X86ISelLowering.h | 2 X86InstrSSE.td | 33 ++++++++++++ 3 files changed, 158 insertions(+), 10 deletions(-) Index: llvm/lib/Target/X86/X86ISelLowering.cpp diff -u llvm/lib/Target/X86/X86ISelLowering.cpp:1.157 llvm/lib/Target/X86/X86ISelLowering.cpp:1.158 --- llvm/lib/Target/X86/X86ISelLowering.cpp:1.157 Wed Apr 5 02:20:06 2006 +++ llvm/lib/Target/X86/X86ISelLowering.cpp Wed Apr 5 18:38:46 2006 @@ -19,6 +19,7 @@ #include "llvm/CallingConv.h" #include "llvm/Constants.h" #include "llvm/Function.h" +#include "llvm/Intrinsics.h" #include "llvm/ADT/VectorExtras.h" #include "llvm/Analysis/ScalarEvolutionExpressions.h" #include "llvm/CodeGen/MachineFrameInfo.h" @@ -323,6 +324,9 @@ setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom); } + // We want to custom lower some of our intrinsics. + setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom); + computeRegisterProperties(); // FIXME: These should be based on subtarget info. Plus, the values should @@ -1185,9 +1189,8 @@ /// specific condition code. It returns a false if it cannot do a direct /// translation. X86CC is the translated CondCode. Flip is set to true if the /// the order of comparison operands should be flipped. -static bool translateX86CC(SDOperand CC, bool isFP, unsigned &X86CC, - bool &Flip) { - ISD::CondCode SetCCOpcode = cast(CC)->get(); +static bool translateX86CC(ISD::CondCode SetCCOpcode, bool isFP, + unsigned &X86CC, bool &Flip) { Flip = false; X86CC = X86ISD::COND_INVALID; if (!isFP) { @@ -1237,6 +1240,11 @@ return X86CC != X86ISD::COND_INVALID; } +static bool translateX86CC(SDOperand CC, bool isFP, unsigned &X86CC, + bool &Flip) { + return translateX86CC(cast(CC)->get(), isFP, X86CC, Flip); +} + /// hasFPCMov - is there a floating point cmov for the specific X86 condition /// code. Current x86 isa includes the following FP cmov instructions: /// fcmovb, fcomvbe, fcomve, fcmovu, fcmovae, fcmova, fcmovne, fcmovnu. @@ -2146,7 +2154,9 @@ // If the X86ISD::SETCC has more than one use, then it's probably better // to use a test instead of duplicating the X86ISD::CMP (for register // pressure reason). - if (Op0.getOperand(1).getOpcode() == X86ISD::CMP) { + unsigned CmpOpc = Op0.getOperand(1).getOpcode(); + if (CmpOpc == X86ISD::CMP || CmpOpc == X86ISD::COMI || + CmpOpc == X86ISD::UCOMI) { if (!Op0.hasOneUse()) { std::vector Tys; for (unsigned i = 0; i < Op0.Val->getNumValues(); ++i) @@ -2160,7 +2170,7 @@ CC = Op0.getOperand(0); Cond = Op0.getOperand(1); // Make a copy as flag result cannot be used by more than one. - Cond = DAG.getNode(X86ISD::CMP, MVT::Flag, + Cond = DAG.getNode(CmpOpc, MVT::Flag, Cond.getOperand(0), Cond.getOperand(1)); addTest = isFPStack && !hasFPCMov(cast(CC)->getSignExtended()); @@ -2201,7 +2211,9 @@ // If the X86ISD::SETCC has more than one use, then it's probably better // to use a test instead of duplicating the X86ISD::CMP (for register // pressure reason). - if (Cond.getOperand(1).getOpcode() == X86ISD::CMP) { + unsigned CmpOpc = Cond.getOperand(1).getOpcode(); + if (CmpOpc == X86ISD::CMP || CmpOpc == X86ISD::COMI || + CmpOpc == X86ISD::UCOMI) { if (!Cond.hasOneUse()) { std::vector Tys; for (unsigned i = 0; i < Cond.Val->getNumValues(); ++i) @@ -2215,7 +2227,7 @@ CC = Cond.getOperand(0); Cond = Cond.getOperand(1); // Make a copy as flag result cannot be used by more than one. - Cond = DAG.getNode(X86ISD::CMP, MVT::Flag, + Cond = DAG.getNode(CmpOpc, MVT::Flag, Cond.getOperand(0), Cond.getOperand(1)); } else addTest = true; @@ -2829,6 +2841,111 @@ return SDOperand(); } + case ISD::INTRINSIC_WO_CHAIN: { + unsigned IntNo = cast(Op.getOperand(0))->getValue(); + switch (IntNo) { + default: return SDOperand(); // Don't custom lower most intrinsics. + // Comparison intrinsics. + case Intrinsic::x86_sse_comieq_ss: + case Intrinsic::x86_sse_comilt_ss: + case Intrinsic::x86_sse_comile_ss: + case Intrinsic::x86_sse_comigt_ss: + case Intrinsic::x86_sse_comige_ss: + case Intrinsic::x86_sse_comineq_ss: + case Intrinsic::x86_sse_ucomieq_ss: + case Intrinsic::x86_sse_ucomilt_ss: + case Intrinsic::x86_sse_ucomile_ss: + case Intrinsic::x86_sse_ucomigt_ss: + case Intrinsic::x86_sse_ucomige_ss: + case Intrinsic::x86_sse_ucomineq_ss: + case Intrinsic::x86_sse2_comieq_sd: + case Intrinsic::x86_sse2_comilt_sd: + case Intrinsic::x86_sse2_comile_sd: + case Intrinsic::x86_sse2_comigt_sd: + case Intrinsic::x86_sse2_comige_sd: + case Intrinsic::x86_sse2_comineq_sd: + case Intrinsic::x86_sse2_ucomieq_sd: + case Intrinsic::x86_sse2_ucomilt_sd: + case Intrinsic::x86_sse2_ucomile_sd: + case Intrinsic::x86_sse2_ucomigt_sd: + case Intrinsic::x86_sse2_ucomige_sd: + case Intrinsic::x86_sse2_ucomineq_sd: { + unsigned Opc; + ISD::CondCode CC; + switch (IntNo) { + default: break; + case Intrinsic::x86_sse_comieq_ss: + case Intrinsic::x86_sse2_comieq_sd: + Opc = X86ISD::COMI; + CC = ISD::SETEQ; + break; + case Intrinsic::x86_sse_comilt_ss: + case Intrinsic::x86_sse2_comilt_sd: + Opc = X86ISD::COMI; + CC = ISD::SETLT; + break; + case Intrinsic::x86_sse_comile_ss: + case Intrinsic::x86_sse2_comile_sd: + Opc = X86ISD::COMI; + CC = ISD::SETLE; + break; + case Intrinsic::x86_sse_comigt_ss: + case Intrinsic::x86_sse2_comigt_sd: + Opc = X86ISD::COMI; + CC = ISD::SETGT; + break; + case Intrinsic::x86_sse_comige_ss: + case Intrinsic::x86_sse2_comige_sd: + Opc = X86ISD::COMI; + CC = ISD::SETGE; + break; + case Intrinsic::x86_sse_comineq_ss: + case Intrinsic::x86_sse2_comineq_sd: + Opc = X86ISD::COMI; + CC = ISD::SETNE; + break; + case Intrinsic::x86_sse_ucomieq_ss: + case Intrinsic::x86_sse2_ucomieq_sd: + Opc = X86ISD::UCOMI; + CC = ISD::SETEQ; + break; + case Intrinsic::x86_sse_ucomilt_ss: + case Intrinsic::x86_sse2_ucomilt_sd: + Opc = X86ISD::UCOMI; + CC = ISD::SETLT; + break; + case Intrinsic::x86_sse_ucomile_ss: + case Intrinsic::x86_sse2_ucomile_sd: + Opc = X86ISD::UCOMI; + CC = ISD::SETLE; + break; + case Intrinsic::x86_sse_ucomigt_ss: + case Intrinsic::x86_sse2_ucomigt_sd: + Opc = X86ISD::UCOMI; + CC = ISD::SETGT; + break; + case Intrinsic::x86_sse_ucomige_ss: + case Intrinsic::x86_sse2_ucomige_sd: + Opc = X86ISD::UCOMI; + CC = ISD::SETGE; + break; + case Intrinsic::x86_sse_ucomineq_ss: + case Intrinsic::x86_sse2_ucomineq_sd: + Opc = X86ISD::UCOMI; + CC = ISD::SETNE; + break; + } + bool Flip; + unsigned X86CC; + translateX86CC(CC, true, X86CC, Flip); + SDOperand Cond = DAG.getNode(Opc, MVT::Flag, Op.getOperand(Flip?2:1), + Op.getOperand(Flip?1:2)); + SDOperand SetCC = DAG.getNode(X86ISD::SETCC, MVT::i8, + DAG.getConstant(X86CC, MVT::i8), Cond); + return DAG.getNode(ISD::ANY_EXTEND, MVT::i32, SetCC); + } + } + } } } @@ -2853,6 +2970,8 @@ case X86ISD::RDTSC_DAG: return "X86ISD::RDTSC_DAG"; case X86ISD::CMP: return "X86ISD::CMP"; case X86ISD::TEST: return "X86ISD::TEST"; + case X86ISD::COMI: return "X86ISD::COMI"; + case X86ISD::UCOMI: return "X86ISD::UCOMI"; case X86ISD::SETCC: return "X86ISD::SETCC"; case X86ISD::CMOV: return "X86ISD::CMOV"; case X86ISD::BRCOND: return "X86ISD::BRCOND"; Index: llvm/lib/Target/X86/X86ISelLowering.h diff -u llvm/lib/Target/X86/X86ISelLowering.h:1.51 llvm/lib/Target/X86/X86ISelLowering.h:1.52 --- llvm/lib/Target/X86/X86ISelLowering.h:1.51 Wed Apr 5 02:20:06 2006 +++ llvm/lib/Target/X86/X86ISelLowering.h Wed Apr 5 18:38:46 2006 @@ -106,7 +106,7 @@ RDTSC_DAG, /// X86 compare and logical compare instructions. - CMP, TEST, + CMP, TEST, COMI, UCOMI, /// X86 SetCC. Operand 1 is condition code, and operand 2 is the flag /// operand produced by a CMP instruction. Index: llvm/lib/Target/X86/X86InstrSSE.td diff -u llvm/lib/Target/X86/X86InstrSSE.td:1.62 llvm/lib/Target/X86/X86InstrSSE.td:1.63 --- llvm/lib/Target/X86/X86InstrSSE.td:1.62 Wed Apr 5 02:20:06 2006 +++ llvm/lib/Target/X86/X86InstrSSE.td Wed Apr 5 18:38:46 2006 @@ -19,10 +19,14 @@ def X86loadp : SDNode<"X86ISD::LOAD_PACK", SDTLoad, [SDNPHasChain]>; -def X86fand : SDNode<"X86ISD::FAND", SDTFPBinOp, +def X86fand : SDNode<"X86ISD::FAND", SDTFPBinOp, [SDNPCommutative, SDNPAssociative]>; -def X86fxor : SDNode<"X86ISD::FXOR", SDTFPBinOp, +def X86fxor : SDNode<"X86ISD::FXOR", SDTFPBinOp, [SDNPCommutative, SDNPAssociative]>; +def X86comi : SDNode<"X86ISD::COMI", SDTX86CmpTest, + [SDNPOutFlag]>; +def X86ucomi : SDNode<"X86ISD::UCOMI", SDTX86CmpTest, + [SDNPOutFlag]>; def X86s2vec : SDNode<"X86ISD::S2VEC", SDTypeProfile<1, 1, []>, []>; def X86zexts2vec : SDNode<"X86ISD::ZEXT_S2VEC", @@ -559,6 +563,31 @@ "cmp${cc}sd {$src, $dst|$dst, $src}", []>; } +def Int_UCOMISSrr: PSI<0x2E, MRMSrcReg, (ops VR128:$src1, VR128:$src2), + "ucomiss {$src2, $src1|$src1, $src2}", + [(X86ucomi (v4f32 VR128:$src1), VR128:$src2)]>; +def Int_UCOMISSrm: PSI<0x2E, MRMSrcMem, (ops VR128:$src1, f128mem:$src2), + "ucomiss {$src2, $src1|$src1, $src2}", + [(X86ucomi (v4f32 VR128:$src1), (loadv4f32 addr:$src2))]>; +def Int_UCOMISDrr: PDI<0x2E, MRMSrcReg, (ops VR128:$src1, VR128:$src2), + "ucomisd {$src2, $src1|$src1, $src2}", + [(X86ucomi (v2f64 VR128:$src1), (v2f64 VR128:$src2))]>; +def Int_UCOMISDrm: PDI<0x2E, MRMSrcMem, (ops VR128:$src1, f128mem:$src2), + "ucomisd {$src2, $src1|$src1, $src2}", + [(X86ucomi (v2f64 VR128:$src1), (loadv2f64 addr:$src2))]>; + +def Int_COMISSrr: PSI<0x2F, MRMSrcReg, (ops VR128:$src1, VR128:$src2), + "comiss {$src2, $src1|$src1, $src2}", + [(X86comi (v4f32 VR128:$src1), VR128:$src2)]>; +def Int_COMISSrm: PSI<0x2F, MRMSrcMem, (ops VR128:$src1, f128mem:$src2), + "comiss {$src2, $src1|$src1, $src2}", + [(X86comi (v4f32 VR128:$src1), (loadv4f32 addr:$src2))]>; +def Int_COMISDrr: PDI<0x2F, MRMSrcReg, (ops VR128:$src1, VR128:$src2), + "comisd {$src2, $src1|$src1, $src2}", + [(X86comi (v2f64 VR128:$src1), (v2f64 VR128:$src2))]>; +def Int_COMISDrm: PDI<0x2F, MRMSrcMem, (ops VR128:$src1, f128mem:$src2), + "comisd {$src2, $src1|$src1, $src2}", + [(X86comi (v2f64 VR128:$src1), (loadv2f64 addr:$src2))]>; // Aliases of packed instructions for scalar use. These all have names that // start with 'Fs'. From evan.cheng at apple.com Wed Apr 5 18:46:17 2006 From: evan.cheng at apple.com (Evan Cheng) Date: Wed, 5 Apr 2006 18:46:17 -0500 Subject: [llvm-commits] CVS: llvm/lib/Target/X86/README.txt Message-ID: <200604052346.SAA02950@zion.cs.uiuc.edu> Changes in directory llvm/lib/Target/X86: README.txt updated: 1.78 -> 1.79 --- Log message: An entry about comi / ucomi intrinsics. --- Diffs of the changes: (+31 -0) README.txt | 31 +++++++++++++++++++++++++++++++ 1 files changed, 31 insertions(+) Index: llvm/lib/Target/X86/README.txt diff -u llvm/lib/Target/X86/README.txt:1.78 llvm/lib/Target/X86/README.txt:1.79 --- llvm/lib/Target/X86/README.txt:1.78 Tue Mar 28 21:03:46 2006 +++ llvm/lib/Target/X86/README.txt Wed Apr 5 18:46:04 2006 @@ -673,3 +673,34 @@ Better codegen for vector_shuffles like this { x, 0, 0, 0 } or { x, 0, x, 0}. Perhaps use pxor / xorp* to clear a XMM register first? +//===---------------------------------------------------------------------===// + +Adding to the list of cmp / test poor codegen issues: + +int test(__m128 *A, __m128 *B) { + if (_mm_comige_ss(*A, *B)) + return 3; + else + return 4; +} + +_test: + movl 8(%esp), %eax + movaps (%eax), %xmm0 + movl 4(%esp), %eax + movaps (%eax), %xmm1 + comiss %xmm0, %xmm1 + setae %al + movzbl %al, %ecx + movl $3, %eax + movl $4, %edx + cmpl $0, %ecx + cmove %edx, %eax + ret + +Note the setae, movzbl, cmpl, cmove can be replaced with a single cmovae. There +are a number of issues. 1) We are introducing a setcc between the result of the +intrisic call and select. 2) The intrinsic is expected to produce a i32 value +so a any extend (which becomes a zero extend) is added. + +We probably need some kind of target DAG combine hook to fix this. From evan.cheng at apple.com Wed Apr 5 20:49:33 2006 From: evan.cheng at apple.com (Evan Cheng) Date: Wed, 5 Apr 2006 20:49:33 -0500 Subject: [llvm-commits] CVS: llvm/lib/Target/X86/X86InstrSSE.td Message-ID: <200604060149.UAA03952@zion.cs.uiuc.edu> Changes in directory llvm/lib/Target/X86: X86InstrSSE.td updated: 1.63 -> 1.64 --- Log message: POR encoded as PAND, yikes. --- Diffs of the changes: (+2 -2) X86InstrSSE.td | 4 ++-- 1 files changed, 2 insertions(+), 2 deletions(-) Index: llvm/lib/Target/X86/X86InstrSSE.td diff -u llvm/lib/Target/X86/X86InstrSSE.td:1.63 llvm/lib/Target/X86/X86InstrSSE.td:1.64 --- llvm/lib/Target/X86/X86InstrSSE.td:1.63 Wed Apr 5 18:38:46 2006 +++ llvm/lib/Target/X86/X86InstrSSE.td Wed Apr 5 20:49:20 2006 @@ -1215,11 +1215,11 @@ "pand {$src2, $dst|$dst, $src2}", [(set VR128:$dst, (v2i64 (and VR128:$src1, (load addr:$src2))))]>; -def PORrr : PDI<0xDB, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2), +def PORrr : PDI<0xEB, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2), "por {$src2, $dst|$dst, $src2}", [(set VR128:$dst, (v2i64 (or VR128:$src1, VR128:$src2)))]>; -def PORrm : PDI<0xDB, MRMSrcMem, (ops VR128:$dst, VR128:$src1, i128mem:$src2), +def PORrm : PDI<0xEB, MRMSrcMem, (ops VR128:$dst, VR128:$src1, i128mem:$src2), "por {$src2, $dst|$dst, $src2}", [(set VR128:$dst, (v2i64 (or VR128:$src1, (load addr:$src2))))]>; From lattner at cs.uiuc.edu Thu Apr 6 01:30:28 2006 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Thu, 6 Apr 2006 01:30:28 -0500 Subject: [llvm-commits] CVS: llvm/Makefile.rules Message-ID: <200604060630.BAA06005@zion.cs.uiuc.edu> Changes in directory llvm: Makefile.rules updated: 1.354 -> 1.355 --- Log message: Add support for building the LLVM libraries and tools as a Mac OS/X universal binary, by specifying UNIVERSAL=1 on the make command line. --- Diffs of the changes: (+7 -0) Makefile.rules | 7 +++++++ 1 files changed, 7 insertions(+) Index: llvm/Makefile.rules diff -u llvm/Makefile.rules:1.354 llvm/Makefile.rules:1.355 --- llvm/Makefile.rules:1.354 Fri Mar 24 01:36:57 2006 +++ llvm/Makefile.rules Thu Apr 6 01:30:15 2006 @@ -360,6 +360,13 @@ CompileCommonOpts := -D_REENTRANT -D_HPUX_SOURCE endif +# If we are building a universal binary on Mac OS/X, pass extra options. This is +# useful to people that want to link the LLVM libraries into their universal apps. +ifdef UNIVERSAL + CompileCommonOpts += -arch i386 -arch ppc -isysroot /Developer/SDKs/MACOSX10.4u.sdk/ + DISABLE_AUTO_DEPENDENCIES=1 +endif + LD.Flags += -L$(LibDir) -L$(LLVMLibDir) CPP.BaseFlags += -D_GNU_SOURCE -D__STDC_LIMIT_MACROS # All -I flags should go here, so that they don't confuse llvm-config. From lattner at cs.uiuc.edu Thu Apr 6 12:23:29 2006 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Thu, 6 Apr 2006 12:23:29 -0500 Subject: [llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCISelLowering.cpp PPCISelLowering.h PPCInstrAltivec.td Message-ID: <200604061723.MAA18672@zion.cs.uiuc.edu> Changes in directory llvm/lib/Target/PowerPC: PPCISelLowering.cpp updated: 1.132 -> 1.133 PPCISelLowering.h updated: 1.39 -> 1.40 PPCInstrAltivec.td updated: 1.41 -> 1.42 --- Log message: Compile the vpkuhum/vpkuwum intrinsics into vpkuhum/vpkuwum instead of into vperm with a perm mask lvx'd from the constant pool. --- Diffs of the changes: (+75 -2) PPCISelLowering.cpp | 54 ++++++++++++++++++++++++++++++++++++++++++++++++++++ PPCISelLowering.h | 8 +++++++ PPCInstrAltivec.td | 15 ++++++++++++-- 3 files changed, 75 insertions(+), 2 deletions(-) Index: llvm/lib/Target/PowerPC/PPCISelLowering.cpp diff -u llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.132 llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.133 --- llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.132 Wed Apr 5 12:39:25 2006 +++ llvm/lib/Target/PowerPC/PPCISelLowering.cpp Thu Apr 6 12:23:16 2006 @@ -267,6 +267,56 @@ return false; } +/// isConstantOrUndef - Op is either an undef node or a ConstantSDNode. Return +/// true if Op is undef or if it matches the specified value. +static bool isConstantOrUndef(SDOperand Op, unsigned Val) { + return Op.getOpcode() == ISD::UNDEF || + cast(Op)->getValue() == Val; +} + +/// isVPKUHUMShuffleMask - Return true if this is the shuffle mask for a +/// VPKUHUM instruction. +bool PPC::isVPKUHUMShuffleMask(SDNode *N) { + return isConstantOrUndef(N->getOperand( 0), 1) && + isConstantOrUndef(N->getOperand( 1), 3) && + isConstantOrUndef(N->getOperand( 2), 5) && + isConstantOrUndef(N->getOperand( 3), 7) && + isConstantOrUndef(N->getOperand( 4), 9) && + isConstantOrUndef(N->getOperand( 5), 11) && + isConstantOrUndef(N->getOperand( 6), 13) && + isConstantOrUndef(N->getOperand( 7), 15) && + isConstantOrUndef(N->getOperand( 8), 17) && + isConstantOrUndef(N->getOperand( 9), 19) && + isConstantOrUndef(N->getOperand(10), 21) && + isConstantOrUndef(N->getOperand(11), 23) && + isConstantOrUndef(N->getOperand(12), 25) && + isConstantOrUndef(N->getOperand(13), 27) && + isConstantOrUndef(N->getOperand(14), 29) && + isConstantOrUndef(N->getOperand(15), 31); +} + +/// isVPKUWUMShuffleMask - Return true if this is the shuffle mask for a +/// VPKUWUM instruction. +bool PPC::isVPKUWUMShuffleMask(SDNode *N) { + return isConstantOrUndef(N->getOperand( 0), 2) && + isConstantOrUndef(N->getOperand( 1), 3) && + isConstantOrUndef(N->getOperand( 2), 6) && + isConstantOrUndef(N->getOperand( 3), 7) && + isConstantOrUndef(N->getOperand( 4), 10) && + isConstantOrUndef(N->getOperand( 5), 11) && + isConstantOrUndef(N->getOperand( 6), 14) && + isConstantOrUndef(N->getOperand( 7), 15) && + isConstantOrUndef(N->getOperand( 8), 18) && + isConstantOrUndef(N->getOperand( 9), 19) && + isConstantOrUndef(N->getOperand(10), 22) && + isConstantOrUndef(N->getOperand(11), 23) && + isConstantOrUndef(N->getOperand(12), 26) && + isConstantOrUndef(N->getOperand(13), 27) && + isConstantOrUndef(N->getOperand(14), 30) && + isConstantOrUndef(N->getOperand(15), 31); +} + + /// isSplatShuffleMask - Return true if the specified VECTOR_SHUFFLE operand /// specifies a splat of a single element that is suitable for input to @@ -759,6 +809,10 @@ PPC::isSplatShuffleMask(PermMask.Val, 4))) return Op; + if (PPC::isVPKUWUMShuffleMask(PermMask.Val) || + PPC::isVPKUHUMShuffleMask(PermMask.Val)) + return Op; + // TODO: Handle more cases, and also handle cases that are cheaper to do as // multiple such instructions than as a constant pool load/vperm pair. Index: llvm/lib/Target/PowerPC/PPCISelLowering.h diff -u llvm/lib/Target/PowerPC/PPCISelLowering.h:1.39 llvm/lib/Target/PowerPC/PPCISelLowering.h:1.40 --- llvm/lib/Target/PowerPC/PPCISelLowering.h:1.39 Tue Apr 4 12:25:31 2006 +++ llvm/lib/Target/PowerPC/PPCISelLowering.h Thu Apr 6 12:23:16 2006 @@ -102,6 +102,14 @@ /// Define some predicates that are used for node matching. namespace PPC { + /// isVPKUHUMShuffleMask - Return true if this is the shuffle mask for a + /// VPKUHUM instruction. + bool isVPKUHUMShuffleMask(SDNode *N); + + /// isVPKUWUMShuffleMask - Return true if this is the shuffle mask for a + /// VPKUWUM instruction. + bool isVPKUWUMShuffleMask(SDNode *N); + /// isSplatShuffleMask - Return true if the specified VECTOR_SHUFFLE operand /// specifies a splat of a single element that is suitable for input to /// VSPLTB/VSPLTH/VSPLTW. Index: llvm/lib/Target/PowerPC/PPCInstrAltivec.td diff -u llvm/lib/Target/PowerPC/PPCInstrAltivec.td:1.41 llvm/lib/Target/PowerPC/PPCInstrAltivec.td:1.42 --- llvm/lib/Target/PowerPC/PPCInstrAltivec.td:1.41 Wed Apr 5 17:27:14 2006 +++ llvm/lib/Target/PowerPC/PPCInstrAltivec.td Thu Apr 6 12:23:16 2006 @@ -15,6 +15,15 @@ // Altivec transformation functions and pattern fragments. // +/// VPKUHUM_shuffle_mask/VPKUWUM_shuffle_mask - Return true if this is a valid +/// shuffle mask for the VPKUHUM or VPKUWUM instructions. +def VPKUHUM_shuffle_mask : PatLeaf<(build_vector), [{ + return PPC::isVPKUHUMShuffleMask(N); +}]>; +def VPKUWUM_shuffle_mask : PatLeaf<(build_vector), [{ + return PPC::isVPKUWUMShuffleMask(N); +}]>; + // VSPLT*_get_imm xform function: convert vector_shuffle mask to VSPLT* imm. def VSPLTB_get_imm : SDNodeXForm; def VPKUHUM : VXForm_1<14, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB), "vpkuhum $vD, $vA, $vB", VecFP, - [/*TODO*/]>; + [(set VRRC:$vD, (vector_shuffle (v16i8 VRRC:$vA), + VRRC:$vB, VPKUHUM_shuffle_mask))]>; def VPKUHUS : VX1_Int<142, "vpkuhus", int_ppc_altivec_vpkuhus>; def VPKUWUM : VXForm_1<78, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB), "vpkuwum $vD, $vA, $vB", VecFP, - [/*TODO*/]>; + [(set VRRC:$vD, (vector_shuffle (v16i8 VRRC:$vA), + VRRC:$vB, VPKUWUM_shuffle_mask))]>; def VPKUWUS : VX1_Int<206, "vpkuwus", int_ppc_altivec_vpkuwus>; // Vector Unpack. From lattner at cs.uiuc.edu Thu Apr 6 13:26:26 2006 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Thu, 6 Apr 2006 13:26:26 -0500 Subject: [llvm-commits] CVS: llvm/test/Regression/CodeGen/PowerPC/vec_shuffle.ll Message-ID: <200604061826.NAA18971@zion.cs.uiuc.edu> Changes in directory llvm/test/Regression/CodeGen/PowerPC: vec_shuffle.ll added (r1.1) --- Log message: new testcase --- Diffs of the changes: (+86 -0) vec_shuffle.ll | 86 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++ 1 files changed, 86 insertions(+) Index: llvm/test/Regression/CodeGen/PowerPC/vec_shuffle.ll diff -c /dev/null llvm/test/Regression/CodeGen/PowerPC/vec_shuffle.ll:1.1 *** /dev/null Thu Apr 6 13:26:23 2006 --- llvm/test/Regression/CodeGen/PowerPC/vec_shuffle.ll Thu Apr 6 13:26:13 2006 *************** *** 0 **** --- 1,86 ---- + ; RUN: llvm-as < %s | llc -march=ppc32 -mcpu=g5 | grep vsldoi | wc -l | grep 2 + + void %VSLDOI_xy(<8 x short>* %A, <8 x short>* %B) { + entry: + %tmp = load <8 x short>* %A ; <<8 x short>> [#uses=1] + %tmp2 = load <8 x short>* %B ; <<8 x short>> [#uses=1] + %tmp = cast <8 x short> %tmp to <16 x sbyte> ; <<16 x sbyte>> [#uses=11] + %tmp2 = cast <8 x short> %tmp2 to <16 x sbyte> ; <<16 x sbyte>> [#uses=5] + %tmp = extractelement <16 x sbyte> %tmp, uint 5 ; [#uses=1] + %tmp3 = extractelement <16 x sbyte> %tmp, uint 6 ; [#uses=1] + %tmp4 = extractelement <16 x sbyte> %tmp, uint 7 ; [#uses=1] + %tmp5 = extractelement <16 x sbyte> %tmp, uint 8 ; [#uses=1] + %tmp6 = extractelement <16 x sbyte> %tmp, uint 9 ; [#uses=1] + %tmp7 = extractelement <16 x sbyte> %tmp, uint 10 ; [#uses=1] + %tmp8 = extractelement <16 x sbyte> %tmp, uint 11 ; [#uses=1] + %tmp9 = extractelement <16 x sbyte> %tmp, uint 12 ; [#uses=1] + %tmp10 = extractelement <16 x sbyte> %tmp, uint 13 ; [#uses=1] + %tmp11 = extractelement <16 x sbyte> %tmp, uint 14 ; [#uses=1] + %tmp12 = extractelement <16 x sbyte> %tmp, uint 15 ; [#uses=1] + %tmp13 = extractelement <16 x sbyte> %tmp2, uint 0 ; [#uses=1] + %tmp14 = extractelement <16 x sbyte> %tmp2, uint 1 ; [#uses=1] + %tmp15 = extractelement <16 x sbyte> %tmp2, uint 2 ; [#uses=1] + %tmp16 = extractelement <16 x sbyte> %tmp2, uint 3 ; [#uses=1] + %tmp17 = extractelement <16 x sbyte> %tmp2, uint 4 ; [#uses=1] + %tmp18 = insertelement <16 x sbyte> undef, sbyte %tmp, uint 0 ; <<16 x sbyte>> [#uses=1] + %tmp19 = insertelement <16 x sbyte> %tmp18, sbyte %tmp3, uint 1 ; <<16 x sbyte>> [#uses=1] + %tmp20 = insertelement <16 x sbyte> %tmp19, sbyte %tmp4, uint 2 ; <<16 x sbyte>> [#uses=1] + %tmp21 = insertelement <16 x sbyte> %tmp20, sbyte %tmp5, uint 3 ; <<16 x sbyte>> [#uses=1] + %tmp22 = insertelement <16 x sbyte> %tmp21, sbyte %tmp6, uint 4 ; <<16 x sbyte>> [#uses=1] + %tmp23 = insertelement <16 x sbyte> %tmp22, sbyte %tmp7, uint 5 ; <<16 x sbyte>> [#uses=1] + %tmp24 = insertelement <16 x sbyte> %tmp23, sbyte %tmp8, uint 6 ; <<16 x sbyte>> [#uses=1] + %tmp25 = insertelement <16 x sbyte> %tmp24, sbyte %tmp9, uint 7 ; <<16 x sbyte>> [#uses=1] + %tmp26 = insertelement <16 x sbyte> %tmp25, sbyte %tmp10, uint 8 ; <<16 x sbyte>> [#uses=1] + %tmp27 = insertelement <16 x sbyte> %tmp26, sbyte %tmp11, uint 9 ; <<16 x sbyte>> [#uses=1] + %tmp28 = insertelement <16 x sbyte> %tmp27, sbyte %tmp12, uint 10 ; <<16 x sbyte>> [#uses=1] + %tmp29 = insertelement <16 x sbyte> %tmp28, sbyte %tmp13, uint 11 ; <<16 x sbyte>> [#uses=1] + %tmp30 = insertelement <16 x sbyte> %tmp29, sbyte %tmp14, uint 12 ; <<16 x sbyte>> [#uses=1] + %tmp31 = insertelement <16 x sbyte> %tmp30, sbyte %tmp15, uint 13 ; <<16 x sbyte>> [#uses=1] + %tmp32 = insertelement <16 x sbyte> %tmp31, sbyte %tmp16, uint 14 ; <<16 x sbyte>> [#uses=1] + %tmp33 = insertelement <16 x sbyte> %tmp32, sbyte %tmp17, uint 15 ; <<16 x sbyte>> [#uses=1] + %tmp33 = cast <16 x sbyte> %tmp33 to <8 x short> ; <<8 x short>> [#uses=1] + store <8 x short> %tmp33, <8 x short>* %A + ret void + } + + void %VSLDOI_xx(<8 x short>* %A, <8 x short>* %B) { + %tmp = load <8 x short>* %A ; <<8 x short>> [#uses=1] + %tmp2 = load <8 x short>* %A ; <<8 x short>> [#uses=1] + %tmp = cast <8 x short> %tmp to <16 x sbyte> ; <<16 x sbyte>> [#uses=11] + %tmp2 = cast <8 x short> %tmp2 to <16 x sbyte> ; <<16 x sbyte>> [#uses=5] + %tmp = extractelement <16 x sbyte> %tmp, uint 5 ; [#uses=1] + %tmp3 = extractelement <16 x sbyte> %tmp, uint 6 ; [#uses=1] + %tmp4 = extractelement <16 x sbyte> %tmp, uint 7 ; [#uses=1] + %tmp5 = extractelement <16 x sbyte> %tmp, uint 8 ; [#uses=1] + %tmp6 = extractelement <16 x sbyte> %tmp, uint 9 ; [#uses=1] + %tmp7 = extractelement <16 x sbyte> %tmp, uint 10 ; [#uses=1] + %tmp8 = extractelement <16 x sbyte> %tmp, uint 11 ; [#uses=1] + %tmp9 = extractelement <16 x sbyte> %tmp, uint 12 ; [#uses=1] + %tmp10 = extractelement <16 x sbyte> %tmp, uint 13 ; [#uses=1] + %tmp11 = extractelement <16 x sbyte> %tmp, uint 14 ; [#uses=1] + %tmp12 = extractelement <16 x sbyte> %tmp, uint 15 ; [#uses=1] + %tmp13 = extractelement <16 x sbyte> %tmp2, uint 0 ; [#uses=1] + %tmp14 = extractelement <16 x sbyte> %tmp2, uint 1 ; [#uses=1] + %tmp15 = extractelement <16 x sbyte> %tmp2, uint 2 ; [#uses=1] + %tmp16 = extractelement <16 x sbyte> %tmp2, uint 3 ; [#uses=1] + %tmp17 = extractelement <16 x sbyte> %tmp2, uint 4 ; [#uses=1] + %tmp18 = insertelement <16 x sbyte> undef, sbyte %tmp, uint 0 ; <<16 x sbyte>> [#uses=1] + %tmp19 = insertelement <16 x sbyte> %tmp18, sbyte %tmp3, uint 1 ; <<16 x sbyte>> [#uses=1] + %tmp20 = insertelement <16 x sbyte> %tmp19, sbyte %tmp4, uint 2 ; <<16 x sbyte>> [#uses=1] + %tmp21 = insertelement <16 x sbyte> %tmp20, sbyte %tmp5, uint 3 ; <<16 x sbyte>> [#uses=1] + %tmp22 = insertelement <16 x sbyte> %tmp21, sbyte %tmp6, uint 4 ; <<16 x sbyte>> [#uses=1] + %tmp23 = insertelement <16 x sbyte> %tmp22, sbyte %tmp7, uint 5 ; <<16 x sbyte>> [#uses=1] + %tmp24 = insertelement <16 x sbyte> %tmp23, sbyte %tmp8, uint 6 ; <<16 x sbyte>> [#uses=1] + %tmp25 = insertelement <16 x sbyte> %tmp24, sbyte %tmp9, uint 7 ; <<16 x sbyte>> [#uses=1] + %tmp26 = insertelement <16 x sbyte> %tmp25, sbyte %tmp10, uint 8 ; <<16 x sbyte>> [#uses=1] + %tmp27 = insertelement <16 x sbyte> %tmp26, sbyte %tmp11, uint 9 ; <<16 x sbyte>> [#uses=1] + %tmp28 = insertelement <16 x sbyte> %tmp27, sbyte %tmp12, uint 10 ; <<16 x sbyte>> [#uses=1] + %tmp29 = insertelement <16 x sbyte> %tmp28, sbyte %tmp13, uint 11 ; <<16 x sbyte>> [#uses=1] + %tmp30 = insertelement <16 x sbyte> %tmp29, sbyte %tmp14, uint 12 ; <<16 x sbyte>> [#uses=1] + %tmp31 = insertelement <16 x sbyte> %tmp30, sbyte %tmp15, uint 13 ; <<16 x sbyte>> [#uses=1] + %tmp32 = insertelement <16 x sbyte> %tmp31, sbyte %tmp16, uint 14 ; <<16 x sbyte>> [#uses=1] + %tmp33 = insertelement <16 x sbyte> %tmp32, sbyte %tmp17, uint 15 ; <<16 x sbyte>> [#uses=1] + %tmp33 = cast <16 x sbyte> %tmp33 to <8 x short> ; <<8 x short>> [#uses=1] + store <8 x short> %tmp33, <8 x short>* %A + ret void + } From lattner at cs.uiuc.edu Thu Apr 6 13:26:40 2006 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Thu, 6 Apr 2006 13:26:40 -0500 Subject: [llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCISelLowering.cpp PPCISelLowering.h PPCInstrAltivec.td README_ALTIVEC.txt Message-ID: <200604061826.NAA18987@zion.cs.uiuc.edu> Changes in directory llvm/lib/Target/PowerPC: PPCISelLowering.cpp updated: 1.133 -> 1.134 PPCISelLowering.h updated: 1.40 -> 1.41 PPCInstrAltivec.td updated: 1.42 -> 1.43 README_ALTIVEC.txt updated: 1.15 -> 1.16 --- Log message: Support pattern matching vsldoi(x,y) and vsldoi(x,x), which allows the f.e. to lower it and LLVM to have one fewer intrinsic. This implements CodeGen/PowerPC/vec_shuffle.ll --- Diffs of the changes: (+97 -41) PPCISelLowering.cpp | 95 +++++++++++++++++++++++++++++++++------------------- PPCISelLowering.h | 8 ++++ PPCInstrAltivec.td | 30 ++++++++++++++-- README_ALTIVEC.txt | 5 -- 4 files changed, 97 insertions(+), 41 deletions(-) Index: llvm/lib/Target/PowerPC/PPCISelLowering.cpp diff -u llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.133 llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.134 --- llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.133 Thu Apr 6 12:23:16 2006 +++ llvm/lib/Target/PowerPC/PPCISelLowering.cpp Thu Apr 6 13:26:28 2006 @@ -277,46 +277,73 @@ /// isVPKUHUMShuffleMask - Return true if this is the shuffle mask for a /// VPKUHUM instruction. bool PPC::isVPKUHUMShuffleMask(SDNode *N) { - return isConstantOrUndef(N->getOperand( 0), 1) && - isConstantOrUndef(N->getOperand( 1), 3) && - isConstantOrUndef(N->getOperand( 2), 5) && - isConstantOrUndef(N->getOperand( 3), 7) && - isConstantOrUndef(N->getOperand( 4), 9) && - isConstantOrUndef(N->getOperand( 5), 11) && - isConstantOrUndef(N->getOperand( 6), 13) && - isConstantOrUndef(N->getOperand( 7), 15) && - isConstantOrUndef(N->getOperand( 8), 17) && - isConstantOrUndef(N->getOperand( 9), 19) && - isConstantOrUndef(N->getOperand(10), 21) && - isConstantOrUndef(N->getOperand(11), 23) && - isConstantOrUndef(N->getOperand(12), 25) && - isConstantOrUndef(N->getOperand(13), 27) && - isConstantOrUndef(N->getOperand(14), 29) && - isConstantOrUndef(N->getOperand(15), 31); + for (unsigned i = 0; i != 16; ++i) + if (!isConstantOrUndef(N->getOperand(i), i*2+1)) + return false; + return true; } /// isVPKUWUMShuffleMask - Return true if this is the shuffle mask for a /// VPKUWUM instruction. bool PPC::isVPKUWUMShuffleMask(SDNode *N) { - return isConstantOrUndef(N->getOperand( 0), 2) && - isConstantOrUndef(N->getOperand( 1), 3) && - isConstantOrUndef(N->getOperand( 2), 6) && - isConstantOrUndef(N->getOperand( 3), 7) && - isConstantOrUndef(N->getOperand( 4), 10) && - isConstantOrUndef(N->getOperand( 5), 11) && - isConstantOrUndef(N->getOperand( 6), 14) && - isConstantOrUndef(N->getOperand( 7), 15) && - isConstantOrUndef(N->getOperand( 8), 18) && - isConstantOrUndef(N->getOperand( 9), 19) && - isConstantOrUndef(N->getOperand(10), 22) && - isConstantOrUndef(N->getOperand(11), 23) && - isConstantOrUndef(N->getOperand(12), 26) && - isConstantOrUndef(N->getOperand(13), 27) && - isConstantOrUndef(N->getOperand(14), 30) && - isConstantOrUndef(N->getOperand(15), 31); + for (unsigned i = 0; i != 16; i += 2) + if (!isConstantOrUndef(N->getOperand(i ), i*2+2) || + !isConstantOrUndef(N->getOperand(i+1), i*2+3)) + return false; + return true; } +/// isVSLDOIShuffleMask - If this is a vsldoi shuffle mask, return the shift +/// amount, otherwise return -1. +int PPC::isVSLDOIShuffleMask(SDNode *N) { + assert(N->getNumOperands() == 16 && "PPC only supports shuffles by bytes!"); + // Find the first non-undef value in the shuffle mask. + unsigned i; + for (i = 0; i != 16 && N->getOperand(i).getOpcode() == ISD::UNDEF; ++i) + /*search*/; + + if (i == 16) return -1; // all undef. + + // Otherwise, check to see if the rest of the elements are consequtively + // numbered from this value. + unsigned ShiftAmt = cast(N->getOperand(i))->getValue(); + if (ShiftAmt < i) return -1; + ShiftAmt -= i; + + // Check the rest of the elements to see if they are consequtive. + for (++i; i != 16; ++i) + if (!isConstantOrUndef(N->getOperand(i), ShiftAmt+i)) + return -1; + + return ShiftAmt; +} +/// isVSLDOIRotateShuffleMask - If this is a vsldoi rotate shuffle mask, +/// return the shift amount, otherwise return -1. Note that vlsdoi(x,x) will +/// result in the shuffle being changed to shuffle(x,undef, ...) with +/// transformed byte numbers. +int PPC::isVSLDOIRotateShuffleMask(SDNode *N) { + assert(N->getNumOperands() == 16 && "PPC only supports shuffles by bytes!"); + // Find the first non-undef value in the shuffle mask. + unsigned i; + for (i = 0; i != 16 && N->getOperand(i).getOpcode() == ISD::UNDEF; ++i) + /*search*/; + + if (i == 16) return -1; // all undef. + + // Otherwise, check to see if the rest of the elements are consequtively + // numbered from this value. + unsigned ShiftAmt = cast(N->getOperand(i))->getValue(); + if (ShiftAmt < i) return -1; + ShiftAmt -= i; + + // Check the rest of the elements to see if they are consequtive. + for (++i; i != 16; ++i) + if (!isConstantOrUndef(N->getOperand(i), (ShiftAmt+i) & 15)) + return -1; + + return ShiftAmt; +} /// isSplatShuffleMask - Return true if the specified VECTOR_SHUFFLE operand /// specifies a splat of a single element that is suitable for input to @@ -810,7 +837,9 @@ return Op; if (PPC::isVPKUWUMShuffleMask(PermMask.Val) || - PPC::isVPKUHUMShuffleMask(PermMask.Val)) + PPC::isVPKUHUMShuffleMask(PermMask.Val) || + PPC::isVSLDOIShuffleMask(PermMask.Val) != -1 || + PPC::isVSLDOIRotateShuffleMask(PermMask.Val) != -1) return Op; // TODO: Handle more cases, and also handle cases that are cheaper to do as Index: llvm/lib/Target/PowerPC/PPCISelLowering.h diff -u llvm/lib/Target/PowerPC/PPCISelLowering.h:1.40 llvm/lib/Target/PowerPC/PPCISelLowering.h:1.41 --- llvm/lib/Target/PowerPC/PPCISelLowering.h:1.40 Thu Apr 6 12:23:16 2006 +++ llvm/lib/Target/PowerPC/PPCISelLowering.h Thu Apr 6 13:26:28 2006 @@ -110,6 +110,14 @@ /// VPKUWUM instruction. bool isVPKUWUMShuffleMask(SDNode *N); + /// isVSLDOIShuffleMask - If this is a vsldoi shuffle mask, return the shift + /// amount, otherwise return -1. + int isVSLDOIShuffleMask(SDNode *N); + + /// isVSLDOIRotateShuffleMask - If this is a vsldoi rotate shuffle mask, + /// return the shift amount, otherwise return -1. This matches vsldoi(x,x). + int isVSLDOIRotateShuffleMask(SDNode *N); + /// isSplatShuffleMask - Return true if the specified VECTOR_SHUFFLE operand /// specifies a splat of a single element that is suitable for input to /// VSPLTB/VSPLTH/VSPLTW. Index: llvm/lib/Target/PowerPC/PPCInstrAltivec.td diff -u llvm/lib/Target/PowerPC/PPCInstrAltivec.td:1.42 llvm/lib/Target/PowerPC/PPCInstrAltivec.td:1.43 --- llvm/lib/Target/PowerPC/PPCInstrAltivec.td:1.42 Thu Apr 6 12:23:16 2006 +++ llvm/lib/Target/PowerPC/PPCInstrAltivec.td Thu Apr 6 13:26:28 2006 @@ -24,6 +24,23 @@ return PPC::isVPKUWUMShuffleMask(N); }]>; +def VSLDOI_get_imm : SDNodeXForm; +def VSLDOI_shuffle_mask : PatLeaf<(build_vector), [{ + return PPC::isVSLDOIShuffleMask(N) != -1; +}], VSLDOI_get_imm>; + +/// VSLDOI_rotate* - These are used to match vsldoi(X,X), which is turned into +/// vector_shuffle(X,undef,mask) by the dag combiner. +def VSLDOI_rotate_get_imm : SDNodeXForm; +def VSLDOI_rotate_shuffle_mask : PatLeaf<(build_vector), [{ + return PPC::isVSLDOIRotateShuffleMask(N) != -1; +}], VSLDOI_rotate_get_imm>; + + // VSPLT*_get_imm xform function: convert vector_shuffle mask to VSPLT* imm. def VSPLTB_get_imm : SDNodeXForm; def VSEL : VA1a_Int<42, "vsel", int_ppc_altivec_vsel>; +// Shuffles. def VSLDOI : VAForm_2<44, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB, u5imm:$SH), "vsldoi $vD, $vA, $vB, $SH", VecFP, - [(set VRRC:$vD, - (int_ppc_altivec_vsldoi VRRC:$vA, VRRC:$vB, - imm:$SH))]>; + [(set VRRC:$vD, + (vector_shuffle (v16i8 VRRC:$vA), VRRC:$vB, + VSLDOI_shuffle_mask:$SH))]>; // VX-Form instructions. AltiVec arithmetic ops. def VADDFP : VXForm_1<10, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB), @@ -504,6 +522,12 @@ def : Pat<(v4f32 (bitconvert (v8i16 VRRC:$src))), (v4f32 VRRC:$src)>; def : Pat<(v4f32 (bitconvert (v4i32 VRRC:$src))), (v4f32 VRRC:$src)>; +// Shuffles. + +// Match vsldoi(x,x) +def:Pat<(vector_shuffle (v16i8 VRRC:$vA),undef, VSLDOI_rotate_shuffle_mask:$in), + (VSLDOI VRRC:$vA, VRRC:$vA, VSLDOI_rotate_shuffle_mask:$in)>; + // Immediate vector formation with vsplti*. def : Pat<(v16i8 vecspltisb:$invec), (v16i8 (VSPLTISB vecspltisb:$invec))>; def : Pat<(v16i8 vecspltish:$invec), (v16i8 (VSPLTISH vecspltish:$invec))>; Index: llvm/lib/Target/PowerPC/README_ALTIVEC.txt diff -u llvm/lib/Target/PowerPC/README_ALTIVEC.txt:1.15 llvm/lib/Target/PowerPC/README_ALTIVEC.txt:1.16 --- llvm/lib/Target/PowerPC/README_ALTIVEC.txt:1.15 Wed Apr 5 17:27:14 2006 +++ llvm/lib/Target/PowerPC/README_ALTIVEC.txt Thu Apr 6 13:26:28 2006 @@ -130,11 +130,6 @@ //===----------------------------------------------------------------------===// -Handle VECTOR_SHUFFLE nodes with the appropriate shuffle mask with vsldoi, -vpkuhum and vpkuwum. - -//===----------------------------------------------------------------------===// - Implement multiply for vector integer types, to avoid the horrible scalarized code produced by legalize. From lattner at cs.uiuc.edu Thu Apr 6 13:29:30 2006 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Thu, 6 Apr 2006 13:29:30 -0500 Subject: [llvm-commits] CVS: llvm/include/llvm/IntrinsicsPowerPC.td Message-ID: <200604061829.NAA19049@zion.cs.uiuc.edu> Changes in directory llvm/include/llvm: IntrinsicsPowerPC.td updated: 1.21 -> 1.22 --- Log message: this is no longer an intrinsic. --- Diffs of the changes: (+0 -5) IntrinsicsPowerPC.td | 5 ----- 1 files changed, 5 deletions(-) Index: llvm/include/llvm/IntrinsicsPowerPC.td diff -u llvm/include/llvm/IntrinsicsPowerPC.td:1.21 llvm/include/llvm/IntrinsicsPowerPC.td:1.22 --- llvm/include/llvm/IntrinsicsPowerPC.td:1.21 Wed Apr 5 17:18:01 2006 +++ llvm/include/llvm/IntrinsicsPowerPC.td Thu Apr 6 13:29:17 2006 @@ -422,11 +422,6 @@ def int_ppc_altivec_vmrglw : GCCBuiltin<"__builtin_altivec_vmrglw">, Intrinsic<[llvm_v4i32_ty, llvm_v4i32_ty, llvm_v4i32_ty], [InstrNoMem]>; - - // Left Shifts. - def int_ppc_altivec_vsldoi : GCCBuiltin<"__builtin_altivec_vsldoi_4si">, - Intrinsic<[llvm_v4i32_ty, llvm_v4i32_ty, - llvm_v4i32_ty, llvm_int_ty], [InstrNoMem]>; } def int_ppc_altivec_vsl : PowerPC_Vec_WWW_Intrinsic<"vsl">; From lattner at cs.uiuc.edu Thu Apr 6 14:19:29 2006 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Thu, 6 Apr 2006 14:19:29 -0500 Subject: [llvm-commits] CVS: llvm/lib/Transforms/Scalar/InstructionCombining.cpp Message-ID: <200604061919.OAA19324@zion.cs.uiuc.edu> Changes in directory llvm/lib/Transforms/Scalar: InstructionCombining.cpp updated: 1.461 -> 1.462 --- Log message: Lower vperm(x,y, mask) -> shuffle(x,y,mask) if mask is constant. This allows us to compile oh-so-realistic stuff like this: vec_vperm(A, B, (vector unsigned char){14}); to: vspltb v0, v0, 14 instead of: vspltisb v0, 14 vperm v0, v2, v1, v0 --- Diffs of the changes: (+58 -8) InstructionCombining.cpp | 66 +++++++++++++++++++++++++++++++++++++++++------ 1 files changed, 58 insertions(+), 8 deletions(-) Index: llvm/lib/Transforms/Scalar/InstructionCombining.cpp diff -u llvm/lib/Transforms/Scalar/InstructionCombining.cpp:1.461 llvm/lib/Transforms/Scalar/InstructionCombining.cpp:1.462 --- llvm/lib/Transforms/Scalar/InstructionCombining.cpp:1.461 Sat Apr 1 23:43:13 2006 +++ llvm/lib/Transforms/Scalar/InstructionCombining.cpp Thu Apr 6 14:19:17 2006 @@ -165,6 +165,9 @@ Value *InsertCastBefore(Value *V, const Type *Ty, Instruction &Pos) { if (V->getType() == Ty) return V; + if (Constant *CV = dyn_cast(V)) + return ConstantExpr::getCast(CV, Ty); + Instruction *C = new CastInst(V, Ty, V->getName(), &Pos); WorkList.push_back(C); return C; @@ -5445,9 +5448,8 @@ case Intrinsic::ppc_altivec_lvxl: // Turn lvx -> load if the pointer is known aligned. if (GetKnownAlignment(II->getOperand(1), TD) >= 16) { - Instruction *Ptr = new CastInst(II->getOperand(1), - PointerType::get(II->getType()), "tmp"); - InsertNewInstBefore(Ptr, CI); + Value *Ptr = InsertCastBefore(II->getOperand(1), + PointerType::get(II->getType()), CI); return new LoadInst(Ptr); } break; @@ -5455,14 +5457,62 @@ case Intrinsic::ppc_altivec_stvxl: // Turn stvx -> store if the pointer is known aligned. if (GetKnownAlignment(II->getOperand(2), TD) >= 16) { - const Type *OpTy = II->getOperand(1)->getType(); - Instruction *Ptr = new CastInst(II->getOperand(2), - PointerType::get(OpTy), "tmp"); - InsertNewInstBefore(Ptr, CI); + const Type *OpPtrTy = PointerType::get(II->getOperand(1)->getType()); + Value *Ptr = InsertCastBefore(II->getOperand(2), OpPtrTy, CI); return new StoreInst(II->getOperand(1), Ptr); } break; - + case Intrinsic::ppc_altivec_vperm: + // Turn vperm(V1,V2,mask) -> shuffle(V1,V2,mask) if mask is a constant. + if (ConstantPacked *Mask = dyn_cast(II->getOperand(3))) { + assert(Mask->getNumOperands() == 16 && "Bad type for intrinsic!"); + + // Check that all of the elements are integer constants or undefs. + bool AllEltsOk = true; + for (unsigned i = 0; i != 16; ++i) { + if (!isa(Mask->getOperand(i)) && + !isa(Mask->getOperand(i))) { + AllEltsOk = false; + break; + } + } + + if (AllEltsOk) { + // Cast the input vectors to byte vectors. + Value *Op0 = InsertCastBefore(II->getOperand(1), Mask->getType(), CI); + Value *Op1 = InsertCastBefore(II->getOperand(2), Mask->getType(), CI); + Value *Result = UndefValue::get(Op0->getType()); + + // Only extract each element once. + Value *ExtractedElts[32]; + memset(ExtractedElts, 0, sizeof(ExtractedElts)); + + for (unsigned i = 0; i != 16; ++i) { + if (isa(Mask->getOperand(i))) + continue; + unsigned Idx =cast(Mask->getOperand(i))->getRawValue(); + Idx &= 31; // Match the hardware behavior. + + if (ExtractedElts[Idx] == 0) { + Instruction *Elt = + new ExtractElementInst(Idx < 16 ? Op0 : Op1, + ConstantUInt::get(Type::UIntTy, Idx&15), + "tmp"); + InsertNewInstBefore(Elt, CI); + ExtractedElts[Idx] = Elt; + } + + // Insert this value into the result vector. + Result = new InsertElementInst(Result, ExtractedElts[Idx], + ConstantUInt::get(Type::UIntTy, i), + "tmp"); + InsertNewInstBefore(cast(Result), CI); + } + return new CastInst(Result, CI.getType()); + } + } + break; + case Intrinsic::stackrestore: { // If the save is right next to the restore, remove the restore. This can // happen when variable allocas are DCE'd. From lattner at cs.uiuc.edu Thu Apr 6 14:19:51 2006 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Thu, 6 Apr 2006 14:19:51 -0500 Subject: [llvm-commits] CVS: llvm/lib/Target/PowerPC/README_ALTIVEC.txt Message-ID: <200604061919.OAA19358@zion.cs.uiuc.edu> Changes in directory llvm/lib/Target/PowerPC: README_ALTIVEC.txt updated: 1.16 -> 1.17 --- Log message: remove two done items --- Diffs of the changes: (+0 -10) README_ALTIVEC.txt | 10 ---------- 1 files changed, 10 deletions(-) Index: llvm/lib/Target/PowerPC/README_ALTIVEC.txt diff -u llvm/lib/Target/PowerPC/README_ALTIVEC.txt:1.16 llvm/lib/Target/PowerPC/README_ALTIVEC.txt:1.17 --- llvm/lib/Target/PowerPC/README_ALTIVEC.txt:1.16 Thu Apr 6 13:26:28 2006 +++ llvm/lib/Target/PowerPC/README_ALTIVEC.txt Thu Apr 6 14:19:38 2006 @@ -69,12 +69,6 @@ //===----------------------------------------------------------------------===// -VSPLTW and friends are expanded by the FE into insert/extract element ops. Make -sure that the dag combiner puts them back together in the appropriate -vector_shuffle node and that this gets pattern matched appropriately. - -//===----------------------------------------------------------------------===// - Implement passing/returning vectors by value. //===----------------------------------------------------------------------===// @@ -126,10 +120,6 @@ //===----------------------------------------------------------------------===// -Instcombine llvm.ppc.altivec.vperm with an immediate into a shuffle operation. - -//===----------------------------------------------------------------------===// - Implement multiply for vector integer types, to avoid the horrible scalarized code produced by legalize. From lattner at cs.uiuc.edu Thu Apr 6 14:21:15 2006 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Thu, 6 Apr 2006 14:21:15 -0500 Subject: [llvm-commits] CVS: llvm/test/Regression/CodeGen/PowerPC/vec_shuffle.ll Message-ID: <200604061921.OAA19396@zion.cs.uiuc.edu> Changes in directory llvm/test/Regression/CodeGen/PowerPC: vec_shuffle.ll updated: 1.1 -> 1.2 --- Log message: test vperm promotion --- Diffs of the changes: (+16 -0) vec_shuffle.ll | 16 ++++++++++++++++ 1 files changed, 16 insertions(+) Index: llvm/test/Regression/CodeGen/PowerPC/vec_shuffle.ll diff -u llvm/test/Regression/CodeGen/PowerPC/vec_shuffle.ll:1.1 llvm/test/Regression/CodeGen/PowerPC/vec_shuffle.ll:1.2 --- llvm/test/Regression/CodeGen/PowerPC/vec_shuffle.ll:1.1 Thu Apr 6 13:26:13 2006 +++ llvm/test/Regression/CodeGen/PowerPC/vec_shuffle.ll Thu Apr 6 14:21:02 2006 @@ -1,4 +1,5 @@ ; RUN: llvm-as < %s | llc -march=ppc32 -mcpu=g5 | grep vsldoi | wc -l | grep 2 +; RUN: llvm-as < %s | opt -instcombine | llc -march=ppc32 -mcpu=g5 | not grep vperm void %VSLDOI_xy(<8 x short>* %A, <8 x short>* %B) { entry: @@ -84,3 +85,18 @@ store <8 x short> %tmp33, <8 x short>* %A ret void } + +void %VPERM_promote(<8 x short>* %A, <8 x short>* %B) { +entry: + %tmp = load <8 x short>* %A ; <<8 x short>> [#uses=1] + %tmp = cast <8 x short> %tmp to <4 x int> ; <<4 x int>> [#uses=1] + %tmp2 = load <8 x short>* %B ; <<8 x short>> [#uses=1] + %tmp2 = cast <8 x short> %tmp2 to <4 x int> ; <<4 x int>> [#uses=1] + %tmp3 = call <4 x int> %llvm.ppc.altivec.vperm( <4 x int> %tmp, <4 x int> %tmp2, <16 x sbyte> < sbyte 14, sbyte 14, sbyte 14, sbyte 14, sbyte 14, sbyte 14, sbyte 14, sbyte 14, sbyte 14, sbyte 14, sbyte 14, sbyte 14, sbyte 14, sbyte 14, sbyte 14, sbyte 14 > ) ; <<4 x int>> [#uses=1] + %tmp3 = cast <4 x int> %tmp3 to <8 x short> ; <<8 x short>> [#uses=1] + store <8 x short> %tmp3, <8 x short>* %A + ret void +} + +declare <4 x int> %llvm.ppc.altivec.vperm(<4 x int>, <4 x int>, <16 x sbyte>) + From lattner at cs.uiuc.edu Thu Apr 6 15:20:05 2006 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Thu, 6 Apr 2006 15:20:05 -0500 Subject: [llvm-commits] CVS: llvm/utils/TableGen/DAGISelEmitter.cpp Message-ID: <200604062020.PAA19841@zion.cs.uiuc.edu> Changes in directory llvm/utils/TableGen: DAGISelEmitter.cpp updated: 1.192 -> 1.193 --- Log message: rename a method, to avoid confusion with llvm intrinsics. --- Diffs of the changes: (+3 -4) DAGISelEmitter.cpp | 7 +++---- 1 files changed, 3 insertions(+), 4 deletions(-) Index: llvm/utils/TableGen/DAGISelEmitter.cpp diff -u llvm/utils/TableGen/DAGISelEmitter.cpp:1.192 llvm/utils/TableGen/DAGISelEmitter.cpp:1.193 --- llvm/utils/TableGen/DAGISelEmitter.cpp:1.192 Thu Mar 30 23:25:56 2006 +++ llvm/utils/TableGen/DAGISelEmitter.cpp Thu Apr 6 15:19:52 2006 @@ -542,11 +542,11 @@ return FragTree; } -/// getIntrinsicType - Check to see if the specified record has an intrinsic +/// getImplicitType - Check to see if the specified record has an implicit /// type which should be applied to it. This infer the type of register /// references from the register file information, for example. /// -static std::vector getIntrinsicType(Record *R, bool NotRegisters, +static std::vector getImplicitType(Record *R, bool NotRegisters, TreePattern &TP) { // Some common return values std::vector Unknown(1, MVT::isUnknown); @@ -598,8 +598,7 @@ if (isLeaf()) { if (DefInit *DI = dynamic_cast(getLeafValue())) { // If it's a regclass or something else known, include the type. - return UpdateNodeType(getIntrinsicType(DI->getDef(), NotRegisters, TP), - TP); + return UpdateNodeType(getImplicitType(DI->getDef(), NotRegisters, TP),TP); } else if (IntInit *II = dynamic_cast(getLeafValue())) { // Int inits are always integers. :) bool MadeChange = UpdateNodeType(MVT::isInt, TP); From lattner at cs.uiuc.edu Thu Apr 6 15:37:04 2006 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Thu, 6 Apr 2006 15:37:04 -0500 Subject: [llvm-commits] CVS: llvm/utils/TableGen/DAGISelEmitter.cpp Message-ID: <200604062037.PAA19933@zion.cs.uiuc.edu> Changes in directory llvm/utils/TableGen: DAGISelEmitter.cpp updated: 1.193 -> 1.194 --- Log message: Infer element types for shuffle masks --- Diffs of the changes: (+20 -0) DAGISelEmitter.cpp | 20 ++++++++++++++++++++ 1 files changed, 20 insertions(+) Index: llvm/utils/TableGen/DAGISelEmitter.cpp diff -u llvm/utils/TableGen/DAGISelEmitter.cpp:1.193 llvm/utils/TableGen/DAGISelEmitter.cpp:1.194 --- llvm/utils/TableGen/DAGISelEmitter.cpp:1.193 Thu Apr 6 15:19:52 2006 +++ llvm/utils/TableGen/DAGISelEmitter.cpp Thu Apr 6 15:36:51 2006 @@ -672,6 +672,26 @@ // must have void types. if (NI.getNumResults() == 0) MadeChange |= UpdateNodeType(MVT::isVoid, TP); + + // If this is a vector_shuffle operation, apply types to the build_vector + // operation. The types of the integers don't matter, but this ensures they + // won't get checked. + if (getOperator()->getName() == "vector_shuffle" && + getChild(2)->getOperator()->getName() == "build_vector") { + TreePatternNode *BV = getChild(2); + const std::vector &LegalVTs + = ISE.getTargetInfo().getLegalValueTypes(); + MVT::ValueType LegalIntVT = MVT::Other; + for (unsigned i = 0, e = LegalVTs.size(); i != e; ++i) + if (MVT::isInteger(LegalVTs[i]) && !MVT::isVector(LegalVTs[i])) { + LegalIntVT = LegalVTs[i]; + break; + } + assert(LegalIntVT != MVT::Other && "No legal integer VT?"); + + for (unsigned i = 0, e = BV->getNumChildren(); i != e; ++i) + MadeChange |= BV->getChild(i)->UpdateNodeType(LegalIntVT, TP); + } return MadeChange; } else if (getOperator()->isSubClassOf("Instruction")) { const DAGInstruction &Inst = ISE.getInstruction(getOperator()); From lattner at cs.uiuc.edu Thu Apr 6 16:12:07 2006 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Thu, 6 Apr 2006 16:12:07 -0500 Subject: [llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCISelLowering.cpp PPCISelLowering.h PPCInstrAltivec.td README_ALTIVEC.txt Message-ID: <200604062112.QAA20113@zion.cs.uiuc.edu> Changes in directory llvm/lib/Target/PowerPC: PPCISelLowering.cpp updated: 1.134 -> 1.135 PPCISelLowering.h updated: 1.41 -> 1.42 PPCInstrAltivec.td updated: 1.43 -> 1.44 README_ALTIVEC.txt updated: 1.17 -> 1.18 --- Log message: Pattern match vmrg* instructions, which are now lowered by the CFE into shuffles. --- Diffs of the changes: (+101 -12) PPCISelLowering.cpp | 52 +++++++++++++++++++++++++++++++++++++++++++++++++--- PPCISelLowering.h | 8 ++++++++ PPCInstrAltivec.td | 50 ++++++++++++++++++++++++++++++++++++++++++++------ README_ALTIVEC.txt | 3 --- 4 files changed, 101 insertions(+), 12 deletions(-) Index: llvm/lib/Target/PowerPC/PPCISelLowering.cpp diff -u llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.134 llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.135 --- llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.134 Thu Apr 6 13:26:28 2006 +++ llvm/lib/Target/PowerPC/PPCISelLowering.cpp Thu Apr 6 16:11:54 2006 @@ -293,10 +293,50 @@ return true; } +/// isVMRGLShuffleMask - Return true if this is a shuffle mask suitable for +/// a VRGL* instruction with the specified unit size (1,2 or 4 bytes). +bool PPC::isVMRGLShuffleMask(SDNode *N, unsigned UnitSize) { + assert(N->getOpcode() == ISD::BUILD_VECTOR && + N->getNumOperands() == 16 && "PPC only supports shuffles by bytes!"); + assert((UnitSize == 1 || UnitSize == 2 || UnitSize == 4) && + "Unsupported merge size!"); + + for (unsigned i = 0; i != 8/UnitSize; ++i) // Step over units + for (unsigned j = 0; j != UnitSize; ++j) { // Step over bytes within unit + if (!isConstantOrUndef(N->getOperand(i*UnitSize*2+j), + 8+j+i*UnitSize) || + !isConstantOrUndef(N->getOperand(i*UnitSize*2+UnitSize+j), + 24+j+i*UnitSize)) + return false; + } + return true; +} + +/// isVMRGHShuffleMask - Return true if this is a shuffle mask suitable for +/// a VRGH* instruction with the specified unit size (1,2 or 4 bytes). +bool PPC::isVMRGHShuffleMask(SDNode *N, unsigned UnitSize) { + assert(N->getOpcode() == ISD::BUILD_VECTOR && + N->getNumOperands() == 16 && "PPC only supports shuffles by bytes!"); + assert((UnitSize == 1 || UnitSize == 2 || UnitSize == 4) && + "Unsupported merge size!"); + + for (unsigned i = 0; i != 8/UnitSize; ++i) // Step over units + for (unsigned j = 0; j != UnitSize; ++j) { // Step over bytes within unit + if (!isConstantOrUndef(N->getOperand(i*UnitSize*2+j), + 0+j+i*UnitSize) || + !isConstantOrUndef(N->getOperand(i*UnitSize*2+UnitSize+j), + 16+j+i*UnitSize)) + return false; + } + return true; +} + + /// isVSLDOIShuffleMask - If this is a vsldoi shuffle mask, return the shift /// amount, otherwise return -1. int PPC::isVSLDOIShuffleMask(SDNode *N) { - assert(N->getNumOperands() == 16 && "PPC only supports shuffles by bytes!"); + assert(N->getOpcode() == ISD::BUILD_VECTOR && + N->getNumOperands() == 16 && "PPC only supports shuffles by bytes!"); // Find the first non-undef value in the shuffle mask. unsigned i; for (i = 0; i != 16 && N->getOperand(i).getOpcode() == ISD::UNDEF; ++i) @@ -833,13 +873,19 @@ if (V2.getOpcode() == ISD::UNDEF && (PPC::isSplatShuffleMask(PermMask.Val, 1) || PPC::isSplatShuffleMask(PermMask.Val, 2) || - PPC::isSplatShuffleMask(PermMask.Val, 4))) + PPC::isSplatShuffleMask(PermMask.Val, 4) || + PPC::isVSLDOIRotateShuffleMask(PermMask.Val) != -1)) return Op; if (PPC::isVPKUWUMShuffleMask(PermMask.Val) || PPC::isVPKUHUMShuffleMask(PermMask.Val) || PPC::isVSLDOIShuffleMask(PermMask.Val) != -1 || - PPC::isVSLDOIRotateShuffleMask(PermMask.Val) != -1) + PPC::isVMRGLShuffleMask(PermMask.Val, 1) || + PPC::isVMRGLShuffleMask(PermMask.Val, 2) || + PPC::isVMRGLShuffleMask(PermMask.Val, 4) || + PPC::isVMRGHShuffleMask(PermMask.Val, 1) || + PPC::isVMRGHShuffleMask(PermMask.Val, 2) || + PPC::isVMRGHShuffleMask(PermMask.Val, 4)) return Op; // TODO: Handle more cases, and also handle cases that are cheaper to do as Index: llvm/lib/Target/PowerPC/PPCISelLowering.h diff -u llvm/lib/Target/PowerPC/PPCISelLowering.h:1.41 llvm/lib/Target/PowerPC/PPCISelLowering.h:1.42 --- llvm/lib/Target/PowerPC/PPCISelLowering.h:1.41 Thu Apr 6 13:26:28 2006 +++ llvm/lib/Target/PowerPC/PPCISelLowering.h Thu Apr 6 16:11:54 2006 @@ -109,6 +109,14 @@ /// isVPKUWUMShuffleMask - Return true if this is the shuffle mask for a /// VPKUWUM instruction. bool isVPKUWUMShuffleMask(SDNode *N); + + /// isVMRGLShuffleMask - Return true if this is a shuffle mask suitable for + /// a VRGL* instruction with the specified unit size (1,2 or 4 bytes). + bool isVMRGLShuffleMask(SDNode *N, unsigned UnitSize); + + /// isVMRGHShuffleMask - Return true if this is a shuffle mask suitable for + /// a VRGH* instruction with the specified unit size (1,2 or 4 bytes). + bool isVMRGHShuffleMask(SDNode *N, unsigned UnitSize); /// isVSLDOIShuffleMask - If this is a vsldoi shuffle mask, return the shift /// amount, otherwise return -1. Index: llvm/lib/Target/PowerPC/PPCInstrAltivec.td diff -u llvm/lib/Target/PowerPC/PPCInstrAltivec.td:1.43 llvm/lib/Target/PowerPC/PPCInstrAltivec.td:1.44 --- llvm/lib/Target/PowerPC/PPCInstrAltivec.td:1.43 Thu Apr 6 13:26:28 2006 +++ llvm/lib/Target/PowerPC/PPCInstrAltivec.td Thu Apr 6 16:11:54 2006 @@ -24,6 +24,26 @@ return PPC::isVPKUWUMShuffleMask(N); }]>; +def VMRGLB_shuffle_mask : PatLeaf<(build_vector), [{ + return PPC::isVMRGLShuffleMask(N, 1); +}]>; +def VMRGLH_shuffle_mask : PatLeaf<(build_vector), [{ + return PPC::isVMRGLShuffleMask(N, 2); +}]>; +def VMRGLW_shuffle_mask : PatLeaf<(build_vector), [{ + return PPC::isVMRGLShuffleMask(N, 4); +}]>; +def VMRGHB_shuffle_mask : PatLeaf<(build_vector), [{ + return PPC::isVMRGHShuffleMask(N, 1); +}]>; +def VMRGHH_shuffle_mask : PatLeaf<(build_vector), [{ + return PPC::isVMRGHShuffleMask(N, 2); +}]>; +def VMRGHW_shuffle_mask : PatLeaf<(build_vector), [{ + return PPC::isVMRGHShuffleMask(N, 4); +}]>; + + def VSLDOI_get_imm : SDNodeXForm; @@ -278,12 +298,30 @@ def VMINUH : VX1_Int< 578, "vminuh", int_ppc_altivec_vminuh>; def VMINUW : VX1_Int< 642, "vminuw", int_ppc_altivec_vminuw>; -def VMRGHB : VX1_Int<12 , "vmrghb", int_ppc_altivec_vmrghb>; -def VMRGHH : VX1_Int<76 , "vmrghh", int_ppc_altivec_vmrghh>; -def VMRGHW : VX1_Int<140, "vmrghw", int_ppc_altivec_vmrghw>; -def VMRGLB : VX1_Int<268, "vmrglb", int_ppc_altivec_vmrglb>; -def VMRGLH : VX1_Int<332, "vmrglh", int_ppc_altivec_vmrglh>; -def VMRGLW : VX1_Int<396, "vmrglw", int_ppc_altivec_vmrglw>; +def VMRGHB : VXForm_1< 12, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB), + "vmrghb $vD, $vA, $vB", VecFP, + [(set VRRC:$vD, (vector_shuffle (v16i8 VRRC:$vA), + VRRC:$vB, VMRGHB_shuffle_mask))]>; +def VMRGHH : VXForm_1< 76, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB), + "vmrghh $vD, $vA, $vB", VecFP, + [(set VRRC:$vD, (vector_shuffle (v16i8 VRRC:$vA), + VRRC:$vB, VMRGHH_shuffle_mask))]>; +def VMRGHW : VXForm_1<140, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB), + "vmrghw $vD, $vA, $vB", VecFP, + [(set VRRC:$vD, (vector_shuffle (v16i8 VRRC:$vA), + VRRC:$vB, VMRGHW_shuffle_mask))]>; +def VMRGLB : VXForm_1<268, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB), + "vmrglb $vD, $vA, $vB", VecFP, + [(set VRRC:$vD, (vector_shuffle (v16i8 VRRC:$vA), + VRRC:$vB, VMRGLB_shuffle_mask))]>; +def VMRGLH : VXForm_1<332, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB), + "vmrglh $vD, $vA, $vB", VecFP, + [(set VRRC:$vD, (vector_shuffle (v16i8 VRRC:$vA), + VRRC:$vB, VMRGLH_shuffle_mask))]>; +def VMRGLW : VXForm_1<396, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB), + "vmrglw $vD, $vA, $vB", VecFP, + [(set VRRC:$vD, (vector_shuffle (v16i8 VRRC:$vA), + VRRC:$vB, VMRGLW_shuffle_mask))]>; def VMSUMMBM : VA1a_Int<37, "vmsummbm", int_ppc_altivec_vmsummbm>; def VMSUMSHM : VA1a_Int<40, "vmsumshm", int_ppc_altivec_vmsumshm>; Index: llvm/lib/Target/PowerPC/README_ALTIVEC.txt diff -u llvm/lib/Target/PowerPC/README_ALTIVEC.txt:1.17 llvm/lib/Target/PowerPC/README_ALTIVEC.txt:1.18 --- llvm/lib/Target/PowerPC/README_ALTIVEC.txt:1.17 Thu Apr 6 14:19:38 2006 +++ llvm/lib/Target/PowerPC/README_ALTIVEC.txt Thu Apr 6 16:11:54 2006 @@ -129,6 +129,3 @@ //===----------------------------------------------------------------------===// -Lower "merges" in the front-end to shuffles, reconstruct in the backend. - -//===----------------------------------------------------------------------===// From lattner at cs.uiuc.edu Thu Apr 6 16:13:01 2006 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Thu, 6 Apr 2006 16:13:01 -0500 Subject: [llvm-commits] CVS: llvm/include/llvm/IntrinsicsPowerPC.td Message-ID: <200604062113.QAA20176@zion.cs.uiuc.edu> Changes in directory llvm/include/llvm: IntrinsicsPowerPC.td updated: 1.22 -> 1.23 --- Log message: These intrinsics are now lowered by the FE. --- Diffs of the changes: (+0 -20) IntrinsicsPowerPC.td | 20 -------------------- 1 files changed, 20 deletions(-) Index: llvm/include/llvm/IntrinsicsPowerPC.td diff -u llvm/include/llvm/IntrinsicsPowerPC.td:1.22 llvm/include/llvm/IntrinsicsPowerPC.td:1.23 --- llvm/include/llvm/IntrinsicsPowerPC.td:1.22 Thu Apr 6 13:29:17 2006 +++ llvm/include/llvm/IntrinsicsPowerPC.td Thu Apr 6 16:12:48 2006 @@ -402,26 +402,6 @@ Intrinsic<[llvm_v4f32_ty, llvm_v4f32_ty], [InstrNoMem]>; def int_ppc_altivec_vrfiz : GCCBuiltin<"__builtin_altivec_vrfiz">, Intrinsic<[llvm_v4f32_ty, llvm_v4f32_ty], [InstrNoMem]>; - - // Merges - def int_ppc_altivec_vmrghb : GCCBuiltin<"__builtin_altivec_vmrghb">, - Intrinsic<[llvm_v16i8_ty, llvm_v16i8_ty, llvm_v16i8_ty], - [InstrNoMem]>; - def int_ppc_altivec_vmrghh : GCCBuiltin<"__builtin_altivec_vmrghh">, - Intrinsic<[llvm_v8i16_ty, llvm_v8i16_ty, llvm_v8i16_ty], - [InstrNoMem]>; - def int_ppc_altivec_vmrghw : GCCBuiltin<"__builtin_altivec_vmrghw">, - Intrinsic<[llvm_v4i32_ty, llvm_v4i32_ty, llvm_v4i32_ty], - [InstrNoMem]>; - def int_ppc_altivec_vmrglb : GCCBuiltin<"__builtin_altivec_vmrglb">, - Intrinsic<[llvm_v16i8_ty, llvm_v16i8_ty, llvm_v16i8_ty], - [InstrNoMem]>; - def int_ppc_altivec_vmrglh : GCCBuiltin<"__builtin_altivec_vmrglh">, - Intrinsic<[llvm_v8i16_ty, llvm_v8i16_ty, llvm_v8i16_ty], - [InstrNoMem]>; - def int_ppc_altivec_vmrglw : GCCBuiltin<"__builtin_altivec_vmrglw">, - Intrinsic<[llvm_v4i32_ty, llvm_v4i32_ty, llvm_v4i32_ty], - [InstrNoMem]>; } def int_ppc_altivec_vsl : PowerPC_Vec_WWW_Intrinsic<"vsl">; From lattner at cs.uiuc.edu Thu Apr 6 16:19:49 2006 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Thu, 6 Apr 2006 16:19:49 -0500 Subject: [llvm-commits] CVS: llvm/test/Regression/CodeGen/PowerPC/vec_shuffle.ll Message-ID: <200604062119.QAA20226@zion.cs.uiuc.edu> Changes in directory llvm/test/Regression/CodeGen/PowerPC: vec_shuffle.ll updated: 1.2 -> 1.3 --- Log message: Add tests for vmrg[hl]* --- Diffs of the changes: (+164 -2) vec_shuffle.ll | 166 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++- 1 files changed, 164 insertions(+), 2 deletions(-) Index: llvm/test/Regression/CodeGen/PowerPC/vec_shuffle.ll diff -u llvm/test/Regression/CodeGen/PowerPC/vec_shuffle.ll:1.2 llvm/test/Regression/CodeGen/PowerPC/vec_shuffle.ll:1.3 --- llvm/test/Regression/CodeGen/PowerPC/vec_shuffle.ll:1.2 Thu Apr 6 14:21:02 2006 +++ llvm/test/Regression/CodeGen/PowerPC/vec_shuffle.ll Thu Apr 6 16:19:37 2006 @@ -1,5 +1,7 @@ -; RUN: llvm-as < %s | llc -march=ppc32 -mcpu=g5 | grep vsldoi | wc -l | grep 2 -; RUN: llvm-as < %s | opt -instcombine | llc -march=ppc32 -mcpu=g5 | not grep vperm +; RUN: llvm-as < %s | opt -instcombine | llc -march=ppc32 -mcpu=g5 | not grep vperm && +; RUN: llvm-as < %s | llc -march=ppc32 -mcpu=g5 | grep vsldoi | wc -l | grep 2 && +; RUN: llvm-as < %s | llc -march=ppc32 -mcpu=g5 | grep vmrgh | wc -l | grep 3 && +; RUN: llvm-as < %s | llc -march=ppc32 -mcpu=g5 | grep vmrgl | wc -l | grep 3 void %VSLDOI_xy(<8 x short>* %A, <8 x short>* %B) { entry: @@ -100,3 +102,163 @@ declare <4 x int> %llvm.ppc.altivec.vperm(<4 x int>, <4 x int>, <16 x sbyte>) + +void %tb_l(<16 x sbyte>* %A, <16 x sbyte>* %B) { +entry: + %tmp = load <16 x sbyte>* %A ; <<16 x sbyte>> [#uses=8] + %tmp2 = load <16 x sbyte>* %B ; <<16 x sbyte>> [#uses=8] + %tmp = extractelement <16 x sbyte> %tmp, uint 8 ; [#uses=1] + %tmp3 = extractelement <16 x sbyte> %tmp2, uint 8 ; [#uses=1] + %tmp4 = extractelement <16 x sbyte> %tmp, uint 9 ; [#uses=1] + %tmp5 = extractelement <16 x sbyte> %tmp2, uint 9 ; [#uses=1] + %tmp6 = extractelement <16 x sbyte> %tmp, uint 10 ; [#uses=1] + %tmp7 = extractelement <16 x sbyte> %tmp2, uint 10 ; [#uses=1] + %tmp8 = extractelement <16 x sbyte> %tmp, uint 11 ; [#uses=1] + %tmp9 = extractelement <16 x sbyte> %tmp2, uint 11 ; [#uses=1] + %tmp10 = extractelement <16 x sbyte> %tmp, uint 12 ; [#uses=1] + %tmp11 = extractelement <16 x sbyte> %tmp2, uint 12 ; [#uses=1] + %tmp12 = extractelement <16 x sbyte> %tmp, uint 13 ; [#uses=1] + %tmp13 = extractelement <16 x sbyte> %tmp2, uint 13 ; [#uses=1] + %tmp14 = extractelement <16 x sbyte> %tmp, uint 14 ; [#uses=1] + %tmp15 = extractelement <16 x sbyte> %tmp2, uint 14 ; [#uses=1] + %tmp16 = extractelement <16 x sbyte> %tmp, uint 15 ; [#uses=1] + %tmp17 = extractelement <16 x sbyte> %tmp2, uint 15 ; [#uses=1] + %tmp18 = insertelement <16 x sbyte> undef, sbyte %tmp, uint 0 ; <<16 x sbyte>> [#uses=1] + %tmp19 = insertelement <16 x sbyte> %tmp18, sbyte %tmp3, uint 1 ; <<16 x sbyte>> [#uses=1] + %tmp20 = insertelement <16 x sbyte> %tmp19, sbyte %tmp4, uint 2 ; <<16 x sbyte>> [#uses=1] + %tmp21 = insertelement <16 x sbyte> %tmp20, sbyte %tmp5, uint 3 ; <<16 x sbyte>> [#uses=1] + %tmp22 = insertelement <16 x sbyte> %tmp21, sbyte %tmp6, uint 4 ; <<16 x sbyte>> [#uses=1] + %tmp23 = insertelement <16 x sbyte> %tmp22, sbyte %tmp7, uint 5 ; <<16 x sbyte>> [#uses=1] + %tmp24 = insertelement <16 x sbyte> %tmp23, sbyte %tmp8, uint 6 ; <<16 x sbyte>> [#uses=1] + %tmp25 = insertelement <16 x sbyte> %tmp24, sbyte %tmp9, uint 7 ; <<16 x sbyte>> [#uses=1] + %tmp26 = insertelement <16 x sbyte> %tmp25, sbyte %tmp10, uint 8 ; <<16 x sbyte>> [#uses=1] + %tmp27 = insertelement <16 x sbyte> %tmp26, sbyte %tmp11, uint 9 ; <<16 x sbyte>> [#uses=1] + %tmp28 = insertelement <16 x sbyte> %tmp27, sbyte %tmp12, uint 10 ; <<16 x sbyte>> [#uses=1] + %tmp29 = insertelement <16 x sbyte> %tmp28, sbyte %tmp13, uint 11 ; <<16 x sbyte>> [#uses=1] + %tmp30 = insertelement <16 x sbyte> %tmp29, sbyte %tmp14, uint 12 ; <<16 x sbyte>> [#uses=1] + %tmp31 = insertelement <16 x sbyte> %tmp30, sbyte %tmp15, uint 13 ; <<16 x sbyte>> [#uses=1] + %tmp32 = insertelement <16 x sbyte> %tmp31, sbyte %tmp16, uint 14 ; <<16 x sbyte>> [#uses=1] + %tmp33 = insertelement <16 x sbyte> %tmp32, sbyte %tmp17, uint 15 ; <<16 x sbyte>> [#uses=1] + store <16 x sbyte> %tmp33, <16 x sbyte>* %A + ret void +} + +void %th_l(<8 x short>* %A, <8 x short>* %B) { +entry: + %tmp = load <8 x short>* %A ; <<8 x short>> [#uses=4] + %tmp2 = load <8 x short>* %B ; <<8 x short>> [#uses=4] + %tmp = extractelement <8 x short> %tmp, uint 4 ; [#uses=1] + %tmp3 = extractelement <8 x short> %tmp2, uint 4 ; [#uses=1] + %tmp4 = extractelement <8 x short> %tmp, uint 5 ; [#uses=1] + %tmp5 = extractelement <8 x short> %tmp2, uint 5 ; [#uses=1] + %tmp6 = extractelement <8 x short> %tmp, uint 6 ; [#uses=1] + %tmp7 = extractelement <8 x short> %tmp2, uint 6 ; [#uses=1] + %tmp8 = extractelement <8 x short> %tmp, uint 7 ; [#uses=1] + %tmp9 = extractelement <8 x short> %tmp2, uint 7 ; [#uses=1] + %tmp10 = insertelement <8 x short> undef, short %tmp, uint 0 ; <<8 x short>> [#uses=1] + %tmp11 = insertelement <8 x short> %tmp10, short %tmp3, uint 1 ; <<8 x short>> [#uses=1] + %tmp12 = insertelement <8 x short> %tmp11, short %tmp4, uint 2 ; <<8 x short>> [#uses=1] + %tmp13 = insertelement <8 x short> %tmp12, short %tmp5, uint 3 ; <<8 x short>> [#uses=1] + %tmp14 = insertelement <8 x short> %tmp13, short %tmp6, uint 4 ; <<8 x short>> [#uses=1] + %tmp15 = insertelement <8 x short> %tmp14, short %tmp7, uint 5 ; <<8 x short>> [#uses=1] + %tmp16 = insertelement <8 x short> %tmp15, short %tmp8, uint 6 ; <<8 x short>> [#uses=1] + %tmp17 = insertelement <8 x short> %tmp16, short %tmp9, uint 7 ; <<8 x short>> [#uses=1] + store <8 x short> %tmp17, <8 x short>* %A + ret void +} + +void %tw_l(<4 x int>* %A, <4 x int>* %B) { +entry: + %tmp = load <4 x int>* %A ; <<4 x int>> [#uses=2] + %tmp2 = load <4 x int>* %B ; <<4 x int>> [#uses=2] + %tmp = extractelement <4 x int> %tmp, uint 2 ; [#uses=1] + %tmp3 = extractelement <4 x int> %tmp2, uint 2 ; [#uses=1] + %tmp4 = extractelement <4 x int> %tmp, uint 3 ; [#uses=1] + %tmp5 = extractelement <4 x int> %tmp2, uint 3 ; [#uses=1] + %tmp6 = insertelement <4 x int> undef, int %tmp, uint 0 ; <<4 x int>> [#uses=1] + %tmp7 = insertelement <4 x int> %tmp6, int %tmp3, uint 1 ; <<4 x int>> [#uses=1] + %tmp8 = insertelement <4 x int> %tmp7, int %tmp4, uint 2 ; <<4 x int>> [#uses=1] + %tmp9 = insertelement <4 x int> %tmp8, int %tmp5, uint 3 ; <<4 x int>> [#uses=1] + store <4 x int> %tmp9, <4 x int>* %A + ret void +} + +void %tb_h(<16 x sbyte>* %A, <16 x sbyte>* %B) { +entry: + %tmp = load <16 x sbyte>* %A ; <<16 x sbyte>> [#uses=8] + %tmp2 = load <16 x sbyte>* %B ; <<16 x sbyte>> [#uses=8] + %tmp = extractelement <16 x sbyte> %tmp, uint 0 ; [#uses=1] + %tmp3 = extractelement <16 x sbyte> %tmp2, uint 0 ; [#uses=1] + %tmp4 = extractelement <16 x sbyte> %tmp, uint 1 ; [#uses=1] + %tmp5 = extractelement <16 x sbyte> %tmp2, uint 1 ; [#uses=1] + %tmp6 = extractelement <16 x sbyte> %tmp, uint 2 ; [#uses=1] + %tmp7 = extractelement <16 x sbyte> %tmp2, uint 2 ; [#uses=1] + %tmp8 = extractelement <16 x sbyte> %tmp, uint 3 ; [#uses=1] + %tmp9 = extractelement <16 x sbyte> %tmp2, uint 3 ; [#uses=1] + %tmp10 = extractelement <16 x sbyte> %tmp, uint 4 ; [#uses=1] + %tmp11 = extractelement <16 x sbyte> %tmp2, uint 4 ; [#uses=1] + %tmp12 = extractelement <16 x sbyte> %tmp, uint 5 ; [#uses=1] + %tmp13 = extractelement <16 x sbyte> %tmp2, uint 5 ; [#uses=1] + %tmp14 = extractelement <16 x sbyte> %tmp, uint 6 ; [#uses=1] + %tmp15 = extractelement <16 x sbyte> %tmp2, uint 6 ; [#uses=1] + %tmp16 = extractelement <16 x sbyte> %tmp, uint 7 ; [#uses=1] + %tmp17 = extractelement <16 x sbyte> %tmp2, uint 7 ; [#uses=1] + %tmp18 = insertelement <16 x sbyte> undef, sbyte %tmp, uint 0 ; <<16 x sbyte>> [#uses=1] + %tmp19 = insertelement <16 x sbyte> %tmp18, sbyte %tmp3, uint 1 ; <<16 x sbyte>> [#uses=1] + %tmp20 = insertelement <16 x sbyte> %tmp19, sbyte %tmp4, uint 2 ; <<16 x sbyte>> [#uses=1] + %tmp21 = insertelement <16 x sbyte> %tmp20, sbyte %tmp5, uint 3 ; <<16 x sbyte>> [#uses=1] + %tmp22 = insertelement <16 x sbyte> %tmp21, sbyte %tmp6, uint 4 ; <<16 x sbyte>> [#uses=1] + %tmp23 = insertelement <16 x sbyte> %tmp22, sbyte %tmp7, uint 5 ; <<16 x sbyte>> [#uses=1] + %tmp24 = insertelement <16 x sbyte> %tmp23, sbyte %tmp8, uint 6 ; <<16 x sbyte>> [#uses=1] + %tmp25 = insertelement <16 x sbyte> %tmp24, sbyte %tmp9, uint 7 ; <<16 x sbyte>> [#uses=1] + %tmp26 = insertelement <16 x sbyte> %tmp25, sbyte %tmp10, uint 8 ; <<16 x sbyte>> [#uses=1] + %tmp27 = insertelement <16 x sbyte> %tmp26, sbyte %tmp11, uint 9 ; <<16 x sbyte>> [#uses=1] + %tmp28 = insertelement <16 x sbyte> %tmp27, sbyte %tmp12, uint 10 ; <<16 x sbyte>> [#uses=1] + %tmp29 = insertelement <16 x sbyte> %tmp28, sbyte %tmp13, uint 11 ; <<16 x sbyte>> [#uses=1] + %tmp30 = insertelement <16 x sbyte> %tmp29, sbyte %tmp14, uint 12 ; <<16 x sbyte>> [#uses=1] + %tmp31 = insertelement <16 x sbyte> %tmp30, sbyte %tmp15, uint 13 ; <<16 x sbyte>> [#uses=1] + %tmp32 = insertelement <16 x sbyte> %tmp31, sbyte %tmp16, uint 14 ; <<16 x sbyte>> [#uses=1] + %tmp33 = insertelement <16 x sbyte> %tmp32, sbyte %tmp17, uint 15 ; <<16 x sbyte>> [#uses=1] + store <16 x sbyte> %tmp33, <16 x sbyte>* %A + ret void +} + +void %th_h(<8 x short>* %A, <8 x short>* %B) { +entry: + %tmp = load <8 x short>* %A ; <<8 x short>> [#uses=4] + %tmp2 = load <8 x short>* %B ; <<8 x short>> [#uses=4] + %tmp = extractelement <8 x short> %tmp, uint 0 ; [#uses=1] + %tmp3 = extractelement <8 x short> %tmp2, uint 0 ; [#uses=1] + %tmp4 = extractelement <8 x short> %tmp, uint 1 ; [#uses=1] + %tmp5 = extractelement <8 x short> %tmp2, uint 1 ; [#uses=1] + %tmp6 = extractelement <8 x short> %tmp, uint 2 ; [#uses=1] + %tmp7 = extractelement <8 x short> %tmp2, uint 2 ; [#uses=1] + %tmp8 = extractelement <8 x short> %tmp, uint 3 ; [#uses=1] + %tmp9 = extractelement <8 x short> %tmp2, uint 3 ; [#uses=1] + %tmp10 = insertelement <8 x short> undef, short %tmp, uint 0 ; <<8 x short>> [#uses=1] + %tmp11 = insertelement <8 x short> %tmp10, short %tmp3, uint 1 ; <<8 x short>> [#uses=1] + %tmp12 = insertelement <8 x short> %tmp11, short %tmp4, uint 2 ; <<8 x short>> [#uses=1] + %tmp13 = insertelement <8 x short> %tmp12, short %tmp5, uint 3 ; <<8 x short>> [#uses=1] + %tmp14 = insertelement <8 x short> %tmp13, short %tmp6, uint 4 ; <<8 x short>> [#uses=1] + %tmp15 = insertelement <8 x short> %tmp14, short %tmp7, uint 5 ; <<8 x short>> [#uses=1] + %tmp16 = insertelement <8 x short> %tmp15, short %tmp8, uint 6 ; <<8 x short>> [#uses=1] + %tmp17 = insertelement <8 x short> %tmp16, short %tmp9, uint 7 ; <<8 x short>> [#uses=1] + store <8 x short> %tmp17, <8 x short>* %A + ret void +} + +void %tw_h(<4 x int>* %A, <4 x int>* %B) { +entry: + %tmp = load <4 x int>* %A ; <<4 x int>> [#uses=2] + %tmp2 = load <4 x int>* %B ; <<4 x int>> [#uses=2] + %tmp = extractelement <4 x int> %tmp, uint 0 ; [#uses=1] + %tmp3 = extractelement <4 x int> %tmp2, uint 0 ; [#uses=1] + %tmp4 = extractelement <4 x int> %tmp, uint 1 ; [#uses=1] + %tmp5 = extractelement <4 x int> %tmp2, uint 1 ; [#uses=1] + %tmp6 = insertelement <4 x int> undef, int %tmp, uint 0 ; <<4 x int>> [#uses=1] + %tmp7 = insertelement <4 x int> %tmp6, int %tmp3, uint 1 ; <<4 x int>> [#uses=1] + %tmp8 = insertelement <4 x int> %tmp7, int %tmp4, uint 2 ; <<4 x int>> [#uses=1] + %tmp9 = insertelement <4 x int> %tmp8, int %tmp5, uint 3 ; <<4 x int>> [#uses=1] + store <4 x int> %tmp9, <4 x int>* %A + ret void +} From alenhar2 at cs.uiuc.edu Thu Apr 6 16:26:45 2006 From: alenhar2 at cs.uiuc.edu (Andrew Lenharth) Date: Thu, 6 Apr 2006 16:26:45 -0500 Subject: [llvm-commits] CVS: llvm/lib/Target/Alpha/AlphaISelLowering.cpp Message-ID: <200604062126.QAA20268@zion.cs.uiuc.edu> Changes in directory llvm/lib/Target/Alpha: AlphaISelLowering.cpp updated: 1.44 -> 1.45 --- Log message: fix some linking problems with the new gcc --- Diffs of the changes: (+3 -1) AlphaISelLowering.cpp | 4 +++- 1 files changed, 3 insertions(+), 1 deletion(-) Index: llvm/lib/Target/Alpha/AlphaISelLowering.cpp diff -u llvm/lib/Target/Alpha/AlphaISelLowering.cpp:1.44 llvm/lib/Target/Alpha/AlphaISelLowering.cpp:1.45 --- llvm/lib/Target/Alpha/AlphaISelLowering.cpp:1.44 Sun Apr 2 22:18:59 2006 +++ llvm/lib/Target/Alpha/AlphaISelLowering.cpp Thu Apr 6 16:26:32 2006 @@ -571,7 +571,7 @@ GlobalValue *GV = GSDN->getGlobal(); SDOperand GA = DAG.getTargetGlobalAddress(GV, MVT::i64, GSDN->getOffset()); - if (!GV->hasWeakLinkage() && !GV->isExternal()) { + if (!GV->hasWeakLinkage() && !GV->isExternal() && !GV->hasLinkOnceLinkage()) { SDOperand Hi = DAG.getNode(AlphaISD::GPRelHi, MVT::i64, GA, DAG.getNode(AlphaISD::GlobalBaseReg, MVT::i64)); SDOperand Lo = DAG.getNode(AlphaISD::GPRelLo, MVT::i64, GA, Hi); @@ -602,6 +602,8 @@ case ISD::SDIV: case ISD::UDIV: if (MVT::isInteger(Op.getValueType())) { + if (Op.getOperand(1).getOpcode() == ISD::Constant) + return Op.getOpcode() == ISD::SDIV ? BuildSDIVSequence(Op, &DAG) : BuildUDIVSequence(Op, &DAG); const char* opstr = 0; switch(Op.getOpcode()) { case ISD::UREM: opstr = "__remqu"; break; From reid at x10sys.com Thu Apr 6 17:00:49 2006 From: reid at x10sys.com (Reid Spencer) Date: Thu, 6 Apr 2006 17:00:49 -0500 Subject: [llvm-commits] CVS: llvm/autoconf/configure.ac Message-ID: <200604062200.RAA20721@zion.cs.uiuc.edu> Changes in directory llvm/autoconf: configure.ac updated: 1.213 -> 1.214 --- Log message: For support of new GCC v4, obtain the full and major versions of the llvm-gcc command. This will help distinguish which version is being used so the makefiles can accommodate. --- Diffs of the changes: (+4 -0) configure.ac | 4 ++++ 1 files changed, 4 insertions(+) Index: llvm/autoconf/configure.ac diff -u llvm/autoconf/configure.ac:1.213 llvm/autoconf/configure.ac:1.214 --- llvm/autoconf/configure.ac:1.213 Thu Mar 23 17:21:29 2006 +++ llvm/autoconf/configure.ac Thu Apr 6 17:00:36 2006 @@ -592,6 +592,10 @@ AC_SUBST(LLVMCC1PLUS,$llvmcc1pluspath) llvmgccdir=`echo "$llvmcc1path" | sed 's,/libexec/.*,,'` AC_SUBST(LLVMGCCDIR,$llvmgccdir) + llvmgccversion=[`"$LLVMGCC" -v 2>&1 | grep '^gcc version' | sed 's/^gcc version \([0-9.]*\).*/\1/'`] + llvmgccmajvers=[`echo $llvmgccversion | sed 's/^\([0-9]\).*/\1/'`] + AC_SUBST(LLVMGCC_VERSION,$llvmgccversion) + AC_SUBST(LLVMGCC_MAJVERS,$llvmgccmajvers) fi dnl Propagate the shared library extension that the libltdl checks did to From reid at x10sys.com Thu Apr 6 17:00:49 2006 From: reid at x10sys.com (Reid Spencer) Date: Thu, 6 Apr 2006 17:00:49 -0500 Subject: [llvm-commits] CVS: llvm/configure Makefile.config.in Message-ID: <200604062200.RAA20727@zion.cs.uiuc.edu> Changes in directory llvm: configure updated: 1.215 -> 1.216 Makefile.config.in updated: 1.53 -> 1.54 --- Log message: For support of new GCC v4, obtain the full and major versions of the llvm-gcc command. This will help distinguish which version is being used so the makefiles can accommodate. --- Diffs of the changes: (+11 -1) Makefile.config.in | 2 ++ configure | 10 +++++++++- 2 files changed, 11 insertions(+), 1 deletion(-) Index: llvm/configure diff -u llvm/configure:1.215 llvm/configure:1.216 --- llvm/configure:1.215 Thu Mar 23 17:21:29 2006 +++ llvm/configure Thu Apr 6 17:00:36 2006 @@ -476,7 +476,7 @@ # include #endif" -ac_subst_vars='SHELL PATH_SEPARATOR PACKAGE_NAME PACKAGE_TARNAME PACKAGE_VERSION PACKAGE_STRING PACKAGE_BUGREPORT exec_prefix prefix program_transform_name bindir sbindir libexecdir datadir sysconfdir sharedstatedir localstatedir libdir includedir oldincludedir infodir mandir build_alias host_alias target_alias DEFS ECHO_C ECHO_N ECHO_T LIBS LLVM_COPYRIGHT subdirs build build_cpu build_vendor build_os host host_cpu host_vendor host_os target target_cpu target_vendor target_os OS LLVM_ON_UNIX LLVM_ON_WIN32 ARCH ENDIAN CC CFLAGS LDFLAGS CPPFLAGS ac_ct_CC EXEEXT OBJEXT ENABLE_OPTIMIZED DEBUG_RUNTIME JIT TARGET_HAS_JIT ENABLE_DOXYGEN ENABLE_THREADS TARGETS_TO_BUILD CPP CXX CXXFLAGS ac_ct_CXX LEX LEXLIB LEX_OUTPUT_ROOT FLEX YACC BISON ifGNUmake LN_S CMP CP DATE FIND GREP MKDIR MV RANLIB ac_ct_RANLIB RM SED TAR GRAPHVIZ GV PERL HAVE_PERL INSTALL_PROGRAM INSTALL_SCRIPT INSTALL_DATA BZIP2 DOT DOXYGEN ETAGS GROFF GZIP POD2HTML POD2MAN RUNTEST TCLSH ZIP EGREP INSTALL_LTDL_TRUE INSTAL! L_LTDL_FALSE CONVENIENCE_LTDL_TRUE CONVENIENCE_LTDL_FALSE LIBADD_DL ECHO AR ac_ct_AR STRIP ac_ct_STRIP CXXCPP F77 FFLAGS ac_ct_F77 LIBTOOL ETAGSFLAGS LLVMGCC LLVMGXX ALLOCA MMAP_FILE LLVMCC1 LLVMCC1PLUS LLVMGCCDIR SHLIBEXT LLVM_PREFIX LLVM_BINDIR LLVM_LIBDIR LLVM_DATADIR LLVM_DOCSDIR LLVM_ETCDIR LLVM_INCLUDEDIR LLVM_INFODIR LLVM_MANDIR LLVM_CONFIGTIME LIBOBJS LTLIBOBJS' +ac_subst_vars='SHELL PATH_SEPARATOR PACKAGE_NAME PACKAGE_TARNAME PACKAGE_VERSION PACKAGE_STRING PACKAGE_BUGREPORT exec_prefix prefix program_transform_name bindir sbindir libexecdir datadir sysconfdir sharedstatedir localstatedir libdir includedir oldincludedir infodir mandir build_alias host_alias target_alias DEFS ECHO_C ECHO_N ECHO_T LIBS LLVM_COPYRIGHT subdirs build build_cpu build_vendor build_os host host_cpu host_vendor host_os target target_cpu target_vendor target_os OS LLVM_ON_UNIX LLVM_ON_WIN32 ARCH ENDIAN CC CFLAGS LDFLAGS CPPFLAGS ac_ct_CC EXEEXT OBJEXT ENABLE_OPTIMIZED DEBUG_RUNTIME JIT TARGET_HAS_JIT ENABLE_DOXYGEN ENABLE_THREADS TARGETS_TO_BUILD CPP CXX CXXFLAGS ac_ct_CXX LEX LEXLIB LEX_OUTPUT_ROOT FLEX YACC BISON ifGNUmake LN_S CMP CP DATE FIND GREP MKDIR MV RANLIB ac_ct_RANLIB RM SED TAR GRAPHVIZ GV PERL HAVE_PERL INSTALL_PROGRAM INSTALL_SCRIPT INSTALL_DATA BZIP2 DOT DOXYGEN ETAGS GROFF GZIP POD2HTML POD2MAN RUNTEST TCLSH ZIP EGREP INSTALL_LTDL_TRUE INSTAL! L_LTDL_FALSE CONVENIENCE_LTDL_TRUE CONVENIENCE_LTDL_FALSE LIBADD_DL ECHO AR ac_ct_AR STRIP ac_ct_STRIP CXXCPP F77 FFLAGS ac_ct_F77 LIBTOOL ETAGSFLAGS LLVMGCC LLVMGXX ALLOCA MMAP_FILE LLVMCC1 LLVMCC1PLUS LLVMGCCDIR LLVMGCC_VERSION LLVMGCC_MAJVERS SHLIBEXT LLVM_PREFIX LLVM_BINDIR LLVM_LIBDIR LLVM_DATADIR LLVM_DOCSDIR LLVM_ETCDIR LLVM_INCLUDEDIR LLVM_INFODIR LLVM_MANDIR LLVM_CONFIGTIME LIBOBJS LTLIBOBJS' ac_subst_files='' # Initialize some variables set by options. @@ -30696,6 +30696,12 @@ llvmgccdir=`echo "$llvmcc1path" | sed 's,/libexec/.*,,'` LLVMGCCDIR=$llvmgccdir + llvmgccversion=`"$LLVMGCC" -v 2>&1 | grep '^gcc version' | sed 's/^gcc version \([0-9.]*\).*/\1/'` + llvmgccmajvers=`echo $llvmgccversion | sed 's/^\([0-9]\).*/\1/'` + LLVMGCC_VERSION=$llvmgccversion + + LLVMGCC_MAJVERS=$llvmgccmajvers + fi SHLIBEXT=$libltdl_cv_shlibext @@ -31584,6 +31590,8 @@ s, at LLVMCC1@,$LLVMCC1,;t t s, at LLVMCC1PLUS@,$LLVMCC1PLUS,;t t s, at LLVMGCCDIR@,$LLVMGCCDIR,;t t +s, at LLVMGCC_VERSION@,$LLVMGCC_VERSION,;t t +s, at LLVMGCC_MAJVERS@,$LLVMGCC_MAJVERS,;t t s, at SHLIBEXT@,$SHLIBEXT,;t t s, at LLVM_PREFIX@,$LLVM_PREFIX,;t t s, at LLVM_BINDIR@,$LLVM_BINDIR,;t t Index: llvm/Makefile.config.in diff -u llvm/Makefile.config.in:1.53 llvm/Makefile.config.in:1.54 --- llvm/Makefile.config.in:1.53 Thu Mar 23 17:21:29 2006 +++ llvm/Makefile.config.in Thu Apr 6 17:00:36 2006 @@ -167,6 +167,8 @@ LLVMGXX := @LLVMGXX@ LLVMCC1 := @LLVMCC1@ LLVMCC1PLUS := @LLVMCC1PLUS@ +LLVMGCC_VERSION := @LLVMGCC_VERSION@ +LLVMGCC_MAJVERS := @LLVMGCC_MAJVERS@ # Path to directory where object files should be stored during a build. # Set OBJ_ROOT to "." if you do not want to use a separate place for From lattner at cs.uiuc.edu Thu Apr 6 17:02:23 2006 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Thu, 6 Apr 2006 17:02:23 -0500 Subject: [llvm-commits] CVS: llvm/test/Regression/CodeGen/PowerPC/vec_shuffle.ll Message-ID: <200604062202.RAA20794@zion.cs.uiuc.edu> Changes in directory llvm/test/Regression/CodeGen/PowerPC: vec_shuffle.ll updated: 1.3 -> 1.4 --- Log message: Add vmrg(x,x) tests --- Diffs of the changes: (+156 -2) vec_shuffle.ll | 158 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++- 1 files changed, 156 insertions(+), 2 deletions(-) Index: llvm/test/Regression/CodeGen/PowerPC/vec_shuffle.ll diff -u llvm/test/Regression/CodeGen/PowerPC/vec_shuffle.ll:1.3 llvm/test/Regression/CodeGen/PowerPC/vec_shuffle.ll:1.4 --- llvm/test/Regression/CodeGen/PowerPC/vec_shuffle.ll:1.3 Thu Apr 6 16:19:37 2006 +++ llvm/test/Regression/CodeGen/PowerPC/vec_shuffle.ll Thu Apr 6 17:02:11 2006 @@ -1,7 +1,7 @@ ; RUN: llvm-as < %s | opt -instcombine | llc -march=ppc32 -mcpu=g5 | not grep vperm && ; RUN: llvm-as < %s | llc -march=ppc32 -mcpu=g5 | grep vsldoi | wc -l | grep 2 && -; RUN: llvm-as < %s | llc -march=ppc32 -mcpu=g5 | grep vmrgh | wc -l | grep 3 && -; RUN: llvm-as < %s | llc -march=ppc32 -mcpu=g5 | grep vmrgl | wc -l | grep 3 +; RUN: llvm-as < %s | llc -march=ppc32 -mcpu=g5 | grep vmrgh | wc -l | grep 6 && +; RUN: llvm-as < %s | llc -march=ppc32 -mcpu=g5 | grep vmrgl | wc -l | grep 6 void %VSLDOI_xy(<8 x short>* %A, <8 x short>* %B) { entry: @@ -262,3 +262,157 @@ store <4 x int> %tmp9, <4 x int>* %A ret void } + +void %VMRG_UNARY_tb_l(<16 x sbyte>* %A, <16 x sbyte>* %B) { +entry: + %tmp = load <16 x sbyte>* %A ; <<16 x sbyte>> [#uses=16] + %tmp = extractelement <16 x sbyte> %tmp, uint 8 ; [#uses=1] + %tmp3 = extractelement <16 x sbyte> %tmp, uint 8 ; [#uses=1] + %tmp4 = extractelement <16 x sbyte> %tmp, uint 9 ; [#uses=1] + %tmp5 = extractelement <16 x sbyte> %tmp, uint 9 ; [#uses=1] + %tmp6 = extractelement <16 x sbyte> %tmp, uint 10 ; [#uses=1] + %tmp7 = extractelement <16 x sbyte> %tmp, uint 10 ; [#uses=1] + %tmp8 = extractelement <16 x sbyte> %tmp, uint 11 ; [#uses=1] + %tmp9 = extractelement <16 x sbyte> %tmp, uint 11 ; [#uses=1] + %tmp10 = extractelement <16 x sbyte> %tmp, uint 12 ; [#uses=1] + %tmp11 = extractelement <16 x sbyte> %tmp, uint 12 ; [#uses=1] + %tmp12 = extractelement <16 x sbyte> %tmp, uint 13 ; [#uses=1] + %tmp13 = extractelement <16 x sbyte> %tmp, uint 13 ; [#uses=1] + %tmp14 = extractelement <16 x sbyte> %tmp, uint 14 ; [#uses=1] + %tmp15 = extractelement <16 x sbyte> %tmp, uint 14 ; [#uses=1] + %tmp16 = extractelement <16 x sbyte> %tmp, uint 15 ; [#uses=1] + %tmp17 = extractelement <16 x sbyte> %tmp, uint 15 ; [#uses=1] + %tmp18 = insertelement <16 x sbyte> undef, sbyte %tmp, uint 0 ; <<16 x sbyte>> [#uses=1] + %tmp19 = insertelement <16 x sbyte> %tmp18, sbyte %tmp3, uint 1 ; <<16 x sbyte>> [#uses=1] + %tmp20 = insertelement <16 x sbyte> %tmp19, sbyte %tmp4, uint 2 ; <<16 x sbyte>> [#uses=1] + %tmp21 = insertelement <16 x sbyte> %tmp20, sbyte %tmp5, uint 3 ; <<16 x sbyte>> [#uses=1] + %tmp22 = insertelement <16 x sbyte> %tmp21, sbyte %tmp6, uint 4 ; <<16 x sbyte>> [#uses=1] + %tmp23 = insertelement <16 x sbyte> %tmp22, sbyte %tmp7, uint 5 ; <<16 x sbyte>> [#uses=1] + %tmp24 = insertelement <16 x sbyte> %tmp23, sbyte %tmp8, uint 6 ; <<16 x sbyte>> [#uses=1] + %tmp25 = insertelement <16 x sbyte> %tmp24, sbyte %tmp9, uint 7 ; <<16 x sbyte>> [#uses=1] + %tmp26 = insertelement <16 x sbyte> %tmp25, sbyte %tmp10, uint 8 ; <<16 x sbyte>> [#uses=1] + %tmp27 = insertelement <16 x sbyte> %tmp26, sbyte %tmp11, uint 9 ; <<16 x sbyte>> [#uses=1] + %tmp28 = insertelement <16 x sbyte> %tmp27, sbyte %tmp12, uint 10 ; <<16 x sbyte>> [#uses=1] + %tmp29 = insertelement <16 x sbyte> %tmp28, sbyte %tmp13, uint 11 ; <<16 x sbyte>> [#uses=1] + %tmp30 = insertelement <16 x sbyte> %tmp29, sbyte %tmp14, uint 12 ; <<16 x sbyte>> [#uses=1] + %tmp31 = insertelement <16 x sbyte> %tmp30, sbyte %tmp15, uint 13 ; <<16 x sbyte>> [#uses=1] + %tmp32 = insertelement <16 x sbyte> %tmp31, sbyte %tmp16, uint 14 ; <<16 x sbyte>> [#uses=1] + %tmp33 = insertelement <16 x sbyte> %tmp32, sbyte %tmp17, uint 15 ; <<16 x sbyte>> [#uses=1] + store <16 x sbyte> %tmp33, <16 x sbyte>* %A + ret void +} + +void %VMRG_UNARY_th_l(<8 x short>* %A, <8 x short>* %B) { +entry: + %tmp = load <8 x short>* %A ; <<8 x short>> [#uses=8] + %tmp = extractelement <8 x short> %tmp, uint 4 ; [#uses=1] + %tmp3 = extractelement <8 x short> %tmp, uint 4 ; [#uses=1] + %tmp4 = extractelement <8 x short> %tmp, uint 5 ; [#uses=1] + %tmp5 = extractelement <8 x short> %tmp, uint 5 ; [#uses=1] + %tmp6 = extractelement <8 x short> %tmp, uint 6 ; [#uses=1] + %tmp7 = extractelement <8 x short> %tmp, uint 6 ; [#uses=1] + %tmp8 = extractelement <8 x short> %tmp, uint 7 ; [#uses=1] + %tmp9 = extractelement <8 x short> %tmp, uint 7 ; [#uses=1] + %tmp10 = insertelement <8 x short> undef, short %tmp, uint 0 ; <<8 x short>> [#uses=1] + %tmp11 = insertelement <8 x short> %tmp10, short %tmp3, uint 1 ; <<8 x short>> [#uses=1] + %tmp12 = insertelement <8 x short> %tmp11, short %tmp4, uint 2 ; <<8 x short>> [#uses=1] + %tmp13 = insertelement <8 x short> %tmp12, short %tmp5, uint 3 ; <<8 x short>> [#uses=1] + %tmp14 = insertelement <8 x short> %tmp13, short %tmp6, uint 4 ; <<8 x short>> [#uses=1] + %tmp15 = insertelement <8 x short> %tmp14, short %tmp7, uint 5 ; <<8 x short>> [#uses=1] + %tmp16 = insertelement <8 x short> %tmp15, short %tmp8, uint 6 ; <<8 x short>> [#uses=1] + %tmp17 = insertelement <8 x short> %tmp16, short %tmp9, uint 7 ; <<8 x short>> [#uses=1] + store <8 x short> %tmp17, <8 x short>* %A + ret void +} + +void %VMRG_UNARY_tw_l(<4 x int>* %A, <4 x int>* %B) { +entry: + %tmp = load <4 x int>* %A ; <<4 x int>> [#uses=4] + %tmp = extractelement <4 x int> %tmp, uint 2 ; [#uses=1] + %tmp3 = extractelement <4 x int> %tmp, uint 2 ; [#uses=1] + %tmp4 = extractelement <4 x int> %tmp, uint 3 ; [#uses=1] + %tmp5 = extractelement <4 x int> %tmp, uint 3 ; [#uses=1] + %tmp6 = insertelement <4 x int> undef, int %tmp, uint 0 ; <<4 x int>> [#uses=1] + %tmp7 = insertelement <4 x int> %tmp6, int %tmp3, uint 1 ; <<4 x int>> [#uses=1] + %tmp8 = insertelement <4 x int> %tmp7, int %tmp4, uint 2 ; <<4 x int>> [#uses=1] + %tmp9 = insertelement <4 x int> %tmp8, int %tmp5, uint 3 ; <<4 x int>> [#uses=1] + store <4 x int> %tmp9, <4 x int>* %A + ret void +} + +void %VMRG_UNARY_tb_h(<16 x sbyte>* %A, <16 x sbyte>* %B) { +entry: + %tmp = load <16 x sbyte>* %A ; <<16 x sbyte>> [#uses=16] + %tmp = extractelement <16 x sbyte> %tmp, uint 0 ; [#uses=1] + %tmp3 = extractelement <16 x sbyte> %tmp, uint 0 ; [#uses=1] + %tmp4 = extractelement <16 x sbyte> %tmp, uint 1 ; [#uses=1] + %tmp5 = extractelement <16 x sbyte> %tmp, uint 1 ; [#uses=1] + %tmp6 = extractelement <16 x sbyte> %tmp, uint 2 ; [#uses=1] + %tmp7 = extractelement <16 x sbyte> %tmp, uint 2 ; [#uses=1] + %tmp8 = extractelement <16 x sbyte> %tmp, uint 3 ; [#uses=1] + %tmp9 = extractelement <16 x sbyte> %tmp, uint 3 ; [#uses=1] + %tmp10 = extractelement <16 x sbyte> %tmp, uint 4 ; [#uses=1] + %tmp11 = extractelement <16 x sbyte> %tmp, uint 4 ; [#uses=1] + %tmp12 = extractelement <16 x sbyte> %tmp, uint 5 ; [#uses=1] + %tmp13 = extractelement <16 x sbyte> %tmp, uint 5 ; [#uses=1] + %tmp14 = extractelement <16 x sbyte> %tmp, uint 6 ; [#uses=1] + %tmp15 = extractelement <16 x sbyte> %tmp, uint 6 ; [#uses=1] + %tmp16 = extractelement <16 x sbyte> %tmp, uint 7 ; [#uses=1] + %tmp17 = extractelement <16 x sbyte> %tmp, uint 7 ; [#uses=1] + %tmp18 = insertelement <16 x sbyte> undef, sbyte %tmp, uint 0 ; <<16 x sbyte>> [#uses=1] + %tmp19 = insertelement <16 x sbyte> %tmp18, sbyte %tmp3, uint 1 ; <<16 x sbyte>> [#uses=1] + %tmp20 = insertelement <16 x sbyte> %tmp19, sbyte %tmp4, uint 2 ; <<16 x sbyte>> [#uses=1] + %tmp21 = insertelement <16 x sbyte> %tmp20, sbyte %tmp5, uint 3 ; <<16 x sbyte>> [#uses=1] + %tmp22 = insertelement <16 x sbyte> %tmp21, sbyte %tmp6, uint 4 ; <<16 x sbyte>> [#uses=1] + %tmp23 = insertelement <16 x sbyte> %tmp22, sbyte %tmp7, uint 5 ; <<16 x sbyte>> [#uses=1] + %tmp24 = insertelement <16 x sbyte> %tmp23, sbyte %tmp8, uint 6 ; <<16 x sbyte>> [#uses=1] + %tmp25 = insertelement <16 x sbyte> %tmp24, sbyte %tmp9, uint 7 ; <<16 x sbyte>> [#uses=1] + %tmp26 = insertelement <16 x sbyte> %tmp25, sbyte %tmp10, uint 8 ; <<16 x sbyte>> [#uses=1] + %tmp27 = insertelement <16 x sbyte> %tmp26, sbyte %tmp11, uint 9 ; <<16 x sbyte>> [#uses=1] + %tmp28 = insertelement <16 x sbyte> %tmp27, sbyte %tmp12, uint 10 ; <<16 x sbyte>> [#uses=1] + %tmp29 = insertelement <16 x sbyte> %tmp28, sbyte %tmp13, uint 11 ; <<16 x sbyte>> [#uses=1] + %tmp30 = insertelement <16 x sbyte> %tmp29, sbyte %tmp14, uint 12 ; <<16 x sbyte>> [#uses=1] + %tmp31 = insertelement <16 x sbyte> %tmp30, sbyte %tmp15, uint 13 ; <<16 x sbyte>> [#uses=1] + %tmp32 = insertelement <16 x sbyte> %tmp31, sbyte %tmp16, uint 14 ; <<16 x sbyte>> [#uses=1] + %tmp33 = insertelement <16 x sbyte> %tmp32, sbyte %tmp17, uint 15 ; <<16 x sbyte>> [#uses=1] + store <16 x sbyte> %tmp33, <16 x sbyte>* %A + ret void +} + +void %VMRG_UNARY_th_h(<8 x short>* %A, <8 x short>* %B) { +entry: + %tmp = load <8 x short>* %A ; <<8 x short>> [#uses=8] + %tmp = extractelement <8 x short> %tmp, uint 0 ; [#uses=1] + %tmp3 = extractelement <8 x short> %tmp, uint 0 ; [#uses=1] + %tmp4 = extractelement <8 x short> %tmp, uint 1 ; [#uses=1] + %tmp5 = extractelement <8 x short> %tmp, uint 1 ; [#uses=1] + %tmp6 = extractelement <8 x short> %tmp, uint 2 ; [#uses=1] + %tmp7 = extractelement <8 x short> %tmp, uint 2 ; [#uses=1] + %tmp8 = extractelement <8 x short> %tmp, uint 3 ; [#uses=1] + %tmp9 = extractelement <8 x short> %tmp, uint 3 ; [#uses=1] + %tmp10 = insertelement <8 x short> undef, short %tmp, uint 0 ; <<8 x short>> [#uses=1] + %tmp11 = insertelement <8 x short> %tmp10, short %tmp3, uint 1 ; <<8 x short>> [#uses=1] + %tmp12 = insertelement <8 x short> %tmp11, short %tmp4, uint 2 ; <<8 x short>> [#uses=1] + %tmp13 = insertelement <8 x short> %tmp12, short %tmp5, uint 3 ; <<8 x short>> [#uses=1] + %tmp14 = insertelement <8 x short> %tmp13, short %tmp6, uint 4 ; <<8 x short>> [#uses=1] + %tmp15 = insertelement <8 x short> %tmp14, short %tmp7, uint 5 ; <<8 x short>> [#uses=1] + %tmp16 = insertelement <8 x short> %tmp15, short %tmp8, uint 6 ; <<8 x short>> [#uses=1] + %tmp17 = insertelement <8 x short> %tmp16, short %tmp9, uint 7 ; <<8 x short>> [#uses=1] + store <8 x short> %tmp17, <8 x short>* %A + ret void +} + +void %VMRG_UNARY_tw_h(<4 x int>* %A, <4 x int>* %B) { +entry: + %tmp = load <4 x int>* %A ; <<4 x int>> [#uses=4] + %tmp = extractelement <4 x int> %tmp, uint 0 ; [#uses=1] + %tmp3 = extractelement <4 x int> %tmp, uint 0 ; [#uses=1] + %tmp4 = extractelement <4 x int> %tmp, uint 1 ; [#uses=1] + %tmp5 = extractelement <4 x int> %tmp, uint 1 ; [#uses=1] + %tmp6 = insertelement <4 x int> undef, int %tmp, uint 0 ; <<4 x int>> [#uses=1] + %tmp7 = insertelement <4 x int> %tmp6, int %tmp3, uint 1 ; <<4 x int>> [#uses=1] + %tmp8 = insertelement <4 x int> %tmp7, int %tmp4, uint 2 ; <<4 x int>> [#uses=1] + %tmp9 = insertelement <4 x int> %tmp8, int %tmp5, uint 3 ; <<4 x int>> [#uses=1] + store <4 x int> %tmp9, <4 x int>* %A + ret void +} From lattner at cs.uiuc.edu Thu Apr 6 17:02:54 2006 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Thu, 6 Apr 2006 17:02:54 -0500 Subject: [llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCISelLowering.cpp PPCISelLowering.h PPCInstrAltivec.td Message-ID: <200604062202.RAA20831@zion.cs.uiuc.edu> Changes in directory llvm/lib/Target/PowerPC: PPCISelLowering.cpp updated: 1.135 -> 1.136 PPCISelLowering.h updated: 1.42 -> 1.43 PPCInstrAltivec.td updated: 1.44 -> 1.45 --- Log message: Add support for matching vmrg(x,x) patterns --- Diffs of the changes: (+81 -41) PPCISelLowering.cpp | 72 ++++++++++++++++++++++++++++------------------------ PPCISelLowering.h | 4 +- PPCInstrAltivec.td | 46 ++++++++++++++++++++++++++++----- 3 files changed, 81 insertions(+), 41 deletions(-) Index: llvm/lib/Target/PowerPC/PPCISelLowering.cpp diff -u llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.135 llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.136 --- llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.135 Thu Apr 6 16:11:54 2006 +++ llvm/lib/Target/PowerPC/PPCISelLowering.cpp Thu Apr 6 17:02:42 2006 @@ -293,9 +293,10 @@ return true; } -/// isVMRGLShuffleMask - Return true if this is a shuffle mask suitable for -/// a VRGL* instruction with the specified unit size (1,2 or 4 bytes). -bool PPC::isVMRGLShuffleMask(SDNode *N, unsigned UnitSize) { +/// isVMerge - Common function, used to match vmrg* shuffles. +/// +static bool isVMerge(SDNode *N, unsigned UnitSize, + unsigned LHSStart, unsigned RHSStart) { assert(N->getOpcode() == ISD::BUILD_VECTOR && N->getNumOperands() == 16 && "PPC only supports shuffles by bytes!"); assert((UnitSize == 1 || UnitSize == 2 || UnitSize == 4) && @@ -304,31 +305,28 @@ for (unsigned i = 0; i != 8/UnitSize; ++i) // Step over units for (unsigned j = 0; j != UnitSize; ++j) { // Step over bytes within unit if (!isConstantOrUndef(N->getOperand(i*UnitSize*2+j), - 8+j+i*UnitSize) || + LHSStart+j+i*UnitSize) || !isConstantOrUndef(N->getOperand(i*UnitSize*2+UnitSize+j), - 24+j+i*UnitSize)) + RHSStart+j+i*UnitSize)) return false; } - return true; + return true; +} + +/// isVMRGLShuffleMask - Return true if this is a shuffle mask suitable for +/// a VRGL* instruction with the specified unit size (1,2 or 4 bytes). +bool PPC::isVMRGLShuffleMask(SDNode *N, unsigned UnitSize, bool isUnary) { + if (!isUnary) + return isVMerge(N, UnitSize, 8, 24); + return isVMerge(N, UnitSize, 8, 8); } /// isVMRGHShuffleMask - Return true if this is a shuffle mask suitable for /// a VRGH* instruction with the specified unit size (1,2 or 4 bytes). -bool PPC::isVMRGHShuffleMask(SDNode *N, unsigned UnitSize) { - assert(N->getOpcode() == ISD::BUILD_VECTOR && - N->getNumOperands() == 16 && "PPC only supports shuffles by bytes!"); - assert((UnitSize == 1 || UnitSize == 2 || UnitSize == 4) && - "Unsupported merge size!"); - - for (unsigned i = 0; i != 8/UnitSize; ++i) // Step over units - for (unsigned j = 0; j != UnitSize; ++j) { // Step over bytes within unit - if (!isConstantOrUndef(N->getOperand(i*UnitSize*2+j), - 0+j+i*UnitSize) || - !isConstantOrUndef(N->getOperand(i*UnitSize*2+UnitSize+j), - 16+j+i*UnitSize)) - return false; - } - return true; +bool PPC::isVMRGHShuffleMask(SDNode *N, unsigned UnitSize, bool isUnary) { + if (!isUnary) + return isVMerge(N, UnitSize, 0, 16); + return isVMerge(N, UnitSize, 0, 0); } @@ -870,22 +868,30 @@ // Cases that are handled by instructions that take permute immediates // (such as vsplt*) should be left as VECTOR_SHUFFLE nodes so they can be // selected by the instruction selector. - if (V2.getOpcode() == ISD::UNDEF && - (PPC::isSplatShuffleMask(PermMask.Val, 1) || - PPC::isSplatShuffleMask(PermMask.Val, 2) || - PPC::isSplatShuffleMask(PermMask.Val, 4) || - PPC::isVSLDOIRotateShuffleMask(PermMask.Val) != -1)) - return Op; + if (V2.getOpcode() == ISD::UNDEF) { + if (PPC::isSplatShuffleMask(PermMask.Val, 1) || + PPC::isSplatShuffleMask(PermMask.Val, 2) || + PPC::isSplatShuffleMask(PermMask.Val, 4) || + PPC::isVSLDOIRotateShuffleMask(PermMask.Val) != -1 || + PPC::isVMRGLShuffleMask(PermMask.Val, 1, true) || + PPC::isVMRGLShuffleMask(PermMask.Val, 2, true) || + PPC::isVMRGLShuffleMask(PermMask.Val, 4, true) || + PPC::isVMRGHShuffleMask(PermMask.Val, 1, true) || + PPC::isVMRGHShuffleMask(PermMask.Val, 2, true) || + PPC::isVMRGHShuffleMask(PermMask.Val, 4, true)) { + return Op; + } + } if (PPC::isVPKUWUMShuffleMask(PermMask.Val) || PPC::isVPKUHUMShuffleMask(PermMask.Val) || PPC::isVSLDOIShuffleMask(PermMask.Val) != -1 || - PPC::isVMRGLShuffleMask(PermMask.Val, 1) || - PPC::isVMRGLShuffleMask(PermMask.Val, 2) || - PPC::isVMRGLShuffleMask(PermMask.Val, 4) || - PPC::isVMRGHShuffleMask(PermMask.Val, 1) || - PPC::isVMRGHShuffleMask(PermMask.Val, 2) || - PPC::isVMRGHShuffleMask(PermMask.Val, 4)) + PPC::isVMRGLShuffleMask(PermMask.Val, 1, false) || + PPC::isVMRGLShuffleMask(PermMask.Val, 2, false) || + PPC::isVMRGLShuffleMask(PermMask.Val, 4, false) || + PPC::isVMRGHShuffleMask(PermMask.Val, 1, false) || + PPC::isVMRGHShuffleMask(PermMask.Val, 2, false) || + PPC::isVMRGHShuffleMask(PermMask.Val, 4, false)) return Op; // TODO: Handle more cases, and also handle cases that are cheaper to do as Index: llvm/lib/Target/PowerPC/PPCISelLowering.h diff -u llvm/lib/Target/PowerPC/PPCISelLowering.h:1.42 llvm/lib/Target/PowerPC/PPCISelLowering.h:1.43 --- llvm/lib/Target/PowerPC/PPCISelLowering.h:1.42 Thu Apr 6 16:11:54 2006 +++ llvm/lib/Target/PowerPC/PPCISelLowering.h Thu Apr 6 17:02:42 2006 @@ -112,11 +112,11 @@ /// isVMRGLShuffleMask - Return true if this is a shuffle mask suitable for /// a VRGL* instruction with the specified unit size (1,2 or 4 bytes). - bool isVMRGLShuffleMask(SDNode *N, unsigned UnitSize); + bool isVMRGLShuffleMask(SDNode *N, unsigned UnitSize, bool isUnary); /// isVMRGHShuffleMask - Return true if this is a shuffle mask suitable for /// a VRGH* instruction with the specified unit size (1,2 or 4 bytes). - bool isVMRGHShuffleMask(SDNode *N, unsigned UnitSize); + bool isVMRGHShuffleMask(SDNode *N, unsigned UnitSize, bool isUnary); /// isVSLDOIShuffleMask - If this is a vsldoi shuffle mask, return the shift /// amount, otherwise return -1. Index: llvm/lib/Target/PowerPC/PPCInstrAltivec.td diff -u llvm/lib/Target/PowerPC/PPCInstrAltivec.td:1.44 llvm/lib/Target/PowerPC/PPCInstrAltivec.td:1.45 --- llvm/lib/Target/PowerPC/PPCInstrAltivec.td:1.44 Thu Apr 6 16:11:54 2006 +++ llvm/lib/Target/PowerPC/PPCInstrAltivec.td Thu Apr 6 17:02:42 2006 @@ -25,22 +25,41 @@ }]>; def VMRGLB_shuffle_mask : PatLeaf<(build_vector), [{ - return PPC::isVMRGLShuffleMask(N, 1); + return PPC::isVMRGLShuffleMask(N, 1, false); }]>; def VMRGLH_shuffle_mask : PatLeaf<(build_vector), [{ - return PPC::isVMRGLShuffleMask(N, 2); + return PPC::isVMRGLShuffleMask(N, 2, false); }]>; def VMRGLW_shuffle_mask : PatLeaf<(build_vector), [{ - return PPC::isVMRGLShuffleMask(N, 4); + return PPC::isVMRGLShuffleMask(N, 4, false); }]>; def VMRGHB_shuffle_mask : PatLeaf<(build_vector), [{ - return PPC::isVMRGHShuffleMask(N, 1); + return PPC::isVMRGHShuffleMask(N, 1, false); }]>; def VMRGHH_shuffle_mask : PatLeaf<(build_vector), [{ - return PPC::isVMRGHShuffleMask(N, 2); + return PPC::isVMRGHShuffleMask(N, 2, false); }]>; def VMRGHW_shuffle_mask : PatLeaf<(build_vector), [{ - return PPC::isVMRGHShuffleMask(N, 4); + return PPC::isVMRGHShuffleMask(N, 4, false); +}]>; + +def VMRGLB_unary_shuffle_mask : PatLeaf<(build_vector), [{ + return PPC::isVMRGLShuffleMask(N, 1, true); +}]>; +def VMRGLH_unary_shuffle_mask : PatLeaf<(build_vector), [{ + return PPC::isVMRGLShuffleMask(N, 2, true); +}]>; +def VMRGLW_unary_shuffle_mask : PatLeaf<(build_vector), [{ + return PPC::isVMRGLShuffleMask(N, 4, true); +}]>; +def VMRGHB_unary_shuffle_mask : PatLeaf<(build_vector), [{ + return PPC::isVMRGHShuffleMask(N, 1, true); +}]>; +def VMRGHH_unary_shuffle_mask : PatLeaf<(build_vector), [{ + return PPC::isVMRGHShuffleMask(N, 2, true); +}]>; +def VMRGHW_unary_shuffle_mask : PatLeaf<(build_vector), [{ + return PPC::isVMRGHShuffleMask(N, 4, true); }]>; @@ -566,6 +585,21 @@ def:Pat<(vector_shuffle (v16i8 VRRC:$vA),undef, VSLDOI_rotate_shuffle_mask:$in), (VSLDOI VRRC:$vA, VRRC:$vA, VSLDOI_rotate_shuffle_mask:$in)>; +// Match vmrg*(x,x) +def:Pat<(vector_shuffle (v16i8 VRRC:$vA), undef, VMRGLB_unary_shuffle_mask:$in), + (VMRGLB VRRC:$vA, VRRC:$vA)>; +def:Pat<(vector_shuffle (v16i8 VRRC:$vA), undef, VMRGLH_unary_shuffle_mask:$in), + (VMRGLH VRRC:$vA, VRRC:$vA)>; +def:Pat<(vector_shuffle (v16i8 VRRC:$vA), undef, VMRGLW_unary_shuffle_mask:$in), + (VMRGLW VRRC:$vA, VRRC:$vA)>; +def:Pat<(vector_shuffle (v16i8 VRRC:$vA), undef, VMRGHB_unary_shuffle_mask:$in), + (VMRGHB VRRC:$vA, VRRC:$vA)>; +def:Pat<(vector_shuffle (v16i8 VRRC:$vA), undef, VMRGHH_unary_shuffle_mask:$in), + (VMRGHH VRRC:$vA, VRRC:$vA)>; +def:Pat<(vector_shuffle (v16i8 VRRC:$vA), undef, VMRGHW_unary_shuffle_mask:$in), + (VMRGHW VRRC:$vA, VRRC:$vA)>; + + // Immediate vector formation with vsplti*. def : Pat<(v16i8 vecspltisb:$invec), (v16i8 (VSPLTISB vecspltisb:$invec))>; def : Pat<(v16i8 vecspltish:$invec), (v16i8 (VSPLTISH vecspltish:$invec))>; From reid at x10sys.com Thu Apr 6 17:16:03 2006 From: reid at x10sys.com (Reid Spencer) Date: Thu, 6 Apr 2006 17:16:03 -0500 Subject: [llvm-commits] CVS: llvm/runtime/Makefile Message-ID: <200604062216.RAA20914@zion.cs.uiuc.edu> Changes in directory llvm/runtime: Makefile updated: 1.25 -> 1.26 --- Log message: Avoid building the runtime libraries if llvm-gcc version 4 is detected. --- Diffs of the changes: (+8 -0) Makefile | 8 ++++++++ 1 files changed, 8 insertions(+) Index: llvm/runtime/Makefile diff -u llvm/runtime/Makefile:1.25 llvm/runtime/Makefile:1.26 --- llvm/runtime/Makefile:1.25 Sun Apr 2 09:34:26 2006 +++ llvm/runtime/Makefile Thu Apr 6 17:15:51 2006 @@ -10,6 +10,13 @@ LEVEL = .. include $(LEVEL)/Makefile.config +ifneq ($(LLVMGCC_MAJVERS),3) +PARALLEL_DIRS := +install all:: + $(Echo) "Warning: The runtime libraries only need to be built with" + $(Echo) "Warning: llvm-gcc version 3. They are automatically included" + $(Echo) "Warning: with llvm-gcc version 4 and beyond" +else ifneq ($(wildcard $(LLVMGCC)),) PARALLEL_DIRS := GCCLibraries libdummy libprofile libtrace GC else @@ -26,6 +33,7 @@ ifeq ($(ARCH), Sparc) PARALLEL_DIRS := $(filter-out libprofile, $(PARALLEL_DIRS)) endif +endif include $(LEVEL)/Makefile.common From reid at x10sys.com Thu Apr 6 17:16:04 2006 From: reid at x10sys.com (Reid Spencer) Date: Thu, 6 Apr 2006 17:16:04 -0500 Subject: [llvm-commits] CVS: llvm/Makefile Message-ID: <200604062216.RAA20918@zion.cs.uiuc.edu> Changes in directory llvm: Makefile updated: 1.51 -> 1.52 --- Log message: Avoid building the runtime libraries if llvm-gcc version 4 is detected. --- Diffs of the changes: (+11 -6) Makefile | 17 +++++++++++------ 1 files changed, 11 insertions(+), 6 deletions(-) Index: llvm/Makefile diff -u llvm/Makefile:1.51 llvm/Makefile:1.52 --- llvm/Makefile:1.51 Wed Aug 24 23:59:49 2005 +++ llvm/Makefile Thu Apr 6 17:15:50 2006 @@ -9,19 +9,24 @@ LEVEL = . DIRS = lib/System lib/Support utils lib +include $(LEVEL)/Makefile.common + ifeq ($(MAKECMDGOALS),tools-only) -DIRS += tools + DIRS += tools else ifneq ($(MAKECMDGOALS),libs-only) - DIRS += tools runtime docs - OPTIONAL_DIRS = examples projects + DIRS += tools + ifeq ($(LLVMGCC_MAJVERS),3) + DIRS += runtime + else + $(warning Skipping runtime libraries, llvm-gcc 4 detected.) + endif + DIRS += docs endif + OPTIONAL_DIRS = examples projects endif - EXTRA_DIST := test llvm.spec include -include $(LEVEL)/Makefile.common - # Specify options to pass to configure script when we're # running the dist-check target DIST_CHECK_CONFIG_OPTIONS = --with-llvmgccdir=$(LLVMGCCDIR) From reid at x10sys.com Thu Apr 6 17:22:21 2006 From: reid at x10sys.com (Reid Spencer) Date: Thu, 6 Apr 2006 17:22:21 -0500 Subject: [llvm-commits] CVS: llvm/test/Makefile Message-ID: <200604062222.RAA20956@zion.cs.uiuc.edu> Changes in directory llvm/test: Makefile updated: 1.84 -> 1.85 --- Log message: Add the variable llvmgccmajvers to the site.exp file. This will contain the major version number of llvm-gcc, as configured. --- Diffs of the changes: (+1 -0) Makefile | 1 + 1 files changed, 1 insertion(+) Index: llvm/test/Makefile diff -u llvm/test/Makefile:1.84 llvm/test/Makefile:1.85 --- llvm/test/Makefile:1.84 Tue Jul 12 19:35:12 2005 +++ llvm/test/Makefile Thu Apr 6 17:22:08 2006 @@ -46,6 +46,7 @@ @echo "set objdir $(LLVM_OBJ_ROOT)/test" >>site.tmp @echo 'set llvmgcc "PATH=\"$(LLVMToolDir):$(PATH)\" \"$(LLVMGCC)\""' >> site.tmp @echo 'set llvmgxx "PATH=\"$(LLVMToolDir):$(PATH)\" \"$(LLVMGCC)\""' >> site.tmp + @echo 'set llvmgccmajvers "$(LLVMGCC_MAJVERS)"' >> site.tmp @echo '## All variables above are generated by configure. Do Not Edit ## ' >>site.tmp @test ! -f site.exp || \ sed '1,/^## All variables above are.*##/ d' site.exp >> site.tmp From lattner at cs.uiuc.edu Thu Apr 6 17:28:11 2006 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Thu, 6 Apr 2006 17:28:11 -0500 Subject: [llvm-commits] CVS: llvm/test/Regression/CodeGen/PowerPC/vec_shuffle.ll Message-ID: <200604062228.RAA21104@zion.cs.uiuc.edu> Changes in directory llvm/test/Regression/CodeGen/PowerPC: vec_shuffle.ll updated: 1.4 -> 1.5 --- Log message: Add testcases for vpku[hw]um(x,x) --- Diffs of the changes: (+71 -1) vec_shuffle.ll | 72 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++- 1 files changed, 71 insertions(+), 1 deletion(-) Index: llvm/test/Regression/CodeGen/PowerPC/vec_shuffle.ll diff -u llvm/test/Regression/CodeGen/PowerPC/vec_shuffle.ll:1.4 llvm/test/Regression/CodeGen/PowerPC/vec_shuffle.ll:1.5 --- llvm/test/Regression/CodeGen/PowerPC/vec_shuffle.ll:1.4 Thu Apr 6 17:02:11 2006 +++ llvm/test/Regression/CodeGen/PowerPC/vec_shuffle.ll Thu Apr 6 17:27:59 2006 @@ -1,7 +1,9 @@ ; RUN: llvm-as < %s | opt -instcombine | llc -march=ppc32 -mcpu=g5 | not grep vperm && ; RUN: llvm-as < %s | llc -march=ppc32 -mcpu=g5 | grep vsldoi | wc -l | grep 2 && ; RUN: llvm-as < %s | llc -march=ppc32 -mcpu=g5 | grep vmrgh | wc -l | grep 6 && -; RUN: llvm-as < %s | llc -march=ppc32 -mcpu=g5 | grep vmrgl | wc -l | grep 6 +; RUN: llvm-as < %s | llc -march=ppc32 -mcpu=g5 | grep vmrgl | wc -l | grep 6 && +; RUN: llvm-as < %s | llc -march=ppc32 -mcpu=g5 | grep vpkuhum | wc -l | grep 1 && +; RUN: llvm-as < %s | llc -march=ppc32 -mcpu=g5 | grep vpkuwum | wc -l | grep 1 void %VSLDOI_xy(<8 x short>* %A, <8 x short>* %B) { entry: @@ -416,3 +418,71 @@ store <4 x int> %tmp9, <4 x int>* %A ret void } + +void %VPCKUHUM_unary(<8 x short>* %A, <8 x short>* %B) { +entry: + %tmp = load <8 x short>* %A ; <<8 x short>> [#uses=2] + %tmp = cast <8 x short> %tmp to <16 x sbyte> ; <<16 x sbyte>> [#uses=8] + %tmp3 = cast <8 x short> %tmp to <16 x sbyte> ; <<16 x sbyte>> [#uses=8] + %tmp = extractelement <16 x sbyte> %tmp, uint 1 ; [#uses=1] + %tmp4 = extractelement <16 x sbyte> %tmp, uint 3 ; [#uses=1] + %tmp5 = extractelement <16 x sbyte> %tmp, uint 5 ; [#uses=1] + %tmp6 = extractelement <16 x sbyte> %tmp, uint 7 ; [#uses=1] + %tmp7 = extractelement <16 x sbyte> %tmp, uint 9 ; [#uses=1] + %tmp8 = extractelement <16 x sbyte> %tmp, uint 11 ; [#uses=1] + %tmp9 = extractelement <16 x sbyte> %tmp, uint 13 ; [#uses=1] + %tmp10 = extractelement <16 x sbyte> %tmp, uint 15 ; [#uses=1] + %tmp11 = extractelement <16 x sbyte> %tmp3, uint 1 ; [#uses=1] + %tmp12 = extractelement <16 x sbyte> %tmp3, uint 3 ; [#uses=1] + %tmp13 = extractelement <16 x sbyte> %tmp3, uint 5 ; [#uses=1] + %tmp14 = extractelement <16 x sbyte> %tmp3, uint 7 ; [#uses=1] + %tmp15 = extractelement <16 x sbyte> %tmp3, uint 9 ; [#uses=1] + %tmp16 = extractelement <16 x sbyte> %tmp3, uint 11 ; [#uses=1] + %tmp17 = extractelement <16 x sbyte> %tmp3, uint 13 ; [#uses=1] + %tmp18 = extractelement <16 x sbyte> %tmp3, uint 15 ; [#uses=1] + %tmp19 = insertelement <16 x sbyte> undef, sbyte %tmp, uint 0 ; <<16 x sbyte>> [#uses=1] + %tmp20 = insertelement <16 x sbyte> %tmp19, sbyte %tmp4, uint 1 ; <<16 x sbyte>> [#uses=1] + %tmp21 = insertelement <16 x sbyte> %tmp20, sbyte %tmp5, uint 2 ; <<16 x sbyte>> [#uses=1] + %tmp22 = insertelement <16 x sbyte> %tmp21, sbyte %tmp6, uint 3 ; <<16 x sbyte>> [#uses=1] + %tmp23 = insertelement <16 x sbyte> %tmp22, sbyte %tmp7, uint 4 ; <<16 x sbyte>> [#uses=1] + %tmp24 = insertelement <16 x sbyte> %tmp23, sbyte %tmp8, uint 5 ; <<16 x sbyte>> [#uses=1] + %tmp25 = insertelement <16 x sbyte> %tmp24, sbyte %tmp9, uint 6 ; <<16 x sbyte>> [#uses=1] + %tmp26 = insertelement <16 x sbyte> %tmp25, sbyte %tmp10, uint 7 ; <<16 x sbyte>> [#uses=1] + %tmp27 = insertelement <16 x sbyte> %tmp26, sbyte %tmp11, uint 8 ; <<16 x sbyte>> [#uses=1] + %tmp28 = insertelement <16 x sbyte> %tmp27, sbyte %tmp12, uint 9 ; <<16 x sbyte>> [#uses=1] + %tmp29 = insertelement <16 x sbyte> %tmp28, sbyte %tmp13, uint 10 ; <<16 x sbyte>> [#uses=1] + %tmp30 = insertelement <16 x sbyte> %tmp29, sbyte %tmp14, uint 11 ; <<16 x sbyte>> [#uses=1] + %tmp31 = insertelement <16 x sbyte> %tmp30, sbyte %tmp15, uint 12 ; <<16 x sbyte>> [#uses=1] + %tmp32 = insertelement <16 x sbyte> %tmp31, sbyte %tmp16, uint 13 ; <<16 x sbyte>> [#uses=1] + %tmp33 = insertelement <16 x sbyte> %tmp32, sbyte %tmp17, uint 14 ; <<16 x sbyte>> [#uses=1] + %tmp34 = insertelement <16 x sbyte> %tmp33, sbyte %tmp18, uint 15 ; <<16 x sbyte>> [#uses=1] + %tmp34 = cast <16 x sbyte> %tmp34 to <8 x short> ; <<8 x short>> [#uses=1] + store <8 x short> %tmp34, <8 x short>* %A + ret void +} + +void %VPCKUWUM_unary(<4 x int>* %A, <4 x int>* %B) { +entry: + %tmp = load <4 x int>* %A ; <<4 x int>> [#uses=2] + %tmp = cast <4 x int> %tmp to <8 x short> ; <<8 x short>> [#uses=4] + %tmp3 = cast <4 x int> %tmp to <8 x short> ; <<8 x short>> [#uses=4] + %tmp = extractelement <8 x short> %tmp, uint 1 ; [#uses=1] + %tmp4 = extractelement <8 x short> %tmp, uint 3 ; [#uses=1] + %tmp5 = extractelement <8 x short> %tmp, uint 5 ; [#uses=1] + %tmp6 = extractelement <8 x short> %tmp, uint 7 ; [#uses=1] + %tmp7 = extractelement <8 x short> %tmp3, uint 1 ; [#uses=1] + %tmp8 = extractelement <8 x short> %tmp3, uint 3 ; [#uses=1] + %tmp9 = extractelement <8 x short> %tmp3, uint 5 ; [#uses=1] + %tmp10 = extractelement <8 x short> %tmp3, uint 7 ; [#uses=1] + %tmp11 = insertelement <8 x short> undef, short %tmp, uint 0 ; <<8 x short>> [#uses=1] + %tmp12 = insertelement <8 x short> %tmp11, short %tmp4, uint 1 ; <<8 x short>> [#uses=1] + %tmp13 = insertelement <8 x short> %tmp12, short %tmp5, uint 2 ; <<8 x short>> [#uses=1] + %tmp14 = insertelement <8 x short> %tmp13, short %tmp6, uint 3 ; <<8 x short>> [#uses=1] + %tmp15 = insertelement <8 x short> %tmp14, short %tmp7, uint 4 ; <<8 x short>> [#uses=1] + %tmp16 = insertelement <8 x short> %tmp15, short %tmp8, uint 5 ; <<8 x short>> [#uses=1] + %tmp17 = insertelement <8 x short> %tmp16, short %tmp9, uint 6 ; <<8 x short>> [#uses=1] + %tmp18 = insertelement <8 x short> %tmp17, short %tmp10, uint 7 ; <<8 x short>> [#uses=1] + %tmp18 = cast <8 x short> %tmp18 to <4 x int> ; <<4 x int>> [#uses=1] + store <4 x int> %tmp18, <4 x int>* %A + ret void +} From lattner at cs.uiuc.edu Thu Apr 6 17:28:49 2006 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Thu, 6 Apr 2006 17:28:49 -0500 Subject: [llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCISelLowering.cpp PPCISelLowering.h PPCInstrAltivec.td Message-ID: <200604062228.RAA21142@zion.cs.uiuc.edu> Changes in directory llvm/lib/Target/PowerPC: PPCISelLowering.cpp updated: 1.136 -> 1.137 PPCISelLowering.h updated: 1.43 -> 1.44 PPCInstrAltivec.td updated: 1.45 -> 1.46 --- Log message: Match vpku[hw]um(x,x). Convert vsldoi(x,x) to work the same way other (x,x) cases work. --- Diffs of the changes: (+74 -66) PPCISelLowering.cpp | 91 ++++++++++++++++++++++++++-------------------------- PPCISelLowering.h | 10 +---- PPCInstrAltivec.td | 39 ++++++++++++++-------- 3 files changed, 74 insertions(+), 66 deletions(-) Index: llvm/lib/Target/PowerPC/PPCISelLowering.cpp diff -u llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.136 llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.137 --- llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.136 Thu Apr 6 17:02:42 2006 +++ llvm/lib/Target/PowerPC/PPCISelLowering.cpp Thu Apr 6 17:28:36 2006 @@ -276,20 +276,36 @@ /// isVPKUHUMShuffleMask - Return true if this is the shuffle mask for a /// VPKUHUM instruction. -bool PPC::isVPKUHUMShuffleMask(SDNode *N) { - for (unsigned i = 0; i != 16; ++i) - if (!isConstantOrUndef(N->getOperand(i), i*2+1)) - return false; +bool PPC::isVPKUHUMShuffleMask(SDNode *N, bool isUnary) { + if (!isUnary) { + for (unsigned i = 0; i != 16; ++i) + if (!isConstantOrUndef(N->getOperand(i), i*2+1)) + return false; + } else { + for (unsigned i = 0; i != 8; ++i) + if (!isConstantOrUndef(N->getOperand(i), i*2+1) || + !isConstantOrUndef(N->getOperand(i+8), i*2+1)) + return false; + } return true; } /// isVPKUWUMShuffleMask - Return true if this is the shuffle mask for a /// VPKUWUM instruction. -bool PPC::isVPKUWUMShuffleMask(SDNode *N) { - for (unsigned i = 0; i != 16; i += 2) - if (!isConstantOrUndef(N->getOperand(i ), i*2+2) || - !isConstantOrUndef(N->getOperand(i+1), i*2+3)) - return false; +bool PPC::isVPKUWUMShuffleMask(SDNode *N, bool isUnary) { + if (!isUnary) { + for (unsigned i = 0; i != 16; i += 2) + if (!isConstantOrUndef(N->getOperand(i ), i*2+2) || + !isConstantOrUndef(N->getOperand(i+1), i*2+3)) + return false; + } else { + for (unsigned i = 0; i != 8; i += 2) + if (!isConstantOrUndef(N->getOperand(i ), i*2+2) || + !isConstantOrUndef(N->getOperand(i+1), i*2+3) || + !isConstantOrUndef(N->getOperand(i+8), i*2+2) || + !isConstantOrUndef(N->getOperand(i+9), i*2+3)) + return false; + } return true; } @@ -332,7 +348,7 @@ /// isVSLDOIShuffleMask - If this is a vsldoi shuffle mask, return the shift /// amount, otherwise return -1. -int PPC::isVSLDOIShuffleMask(SDNode *N) { +int PPC::isVSLDOIShuffleMask(SDNode *N, bool isUnary) { assert(N->getOpcode() == ISD::BUILD_VECTOR && N->getNumOperands() == 16 && "PPC only supports shuffles by bytes!"); // Find the first non-undef value in the shuffle mask. @@ -348,37 +364,17 @@ if (ShiftAmt < i) return -1; ShiftAmt -= i; - // Check the rest of the elements to see if they are consequtive. - for (++i; i != 16; ++i) - if (!isConstantOrUndef(N->getOperand(i), ShiftAmt+i)) - return -1; - - return ShiftAmt; -} - -/// isVSLDOIRotateShuffleMask - If this is a vsldoi rotate shuffle mask, -/// return the shift amount, otherwise return -1. Note that vlsdoi(x,x) will -/// result in the shuffle being changed to shuffle(x,undef, ...) with -/// transformed byte numbers. -int PPC::isVSLDOIRotateShuffleMask(SDNode *N) { - assert(N->getNumOperands() == 16 && "PPC only supports shuffles by bytes!"); - // Find the first non-undef value in the shuffle mask. - unsigned i; - for (i = 0; i != 16 && N->getOperand(i).getOpcode() == ISD::UNDEF; ++i) - /*search*/; - - if (i == 16) return -1; // all undef. - - // Otherwise, check to see if the rest of the elements are consequtively - // numbered from this value. - unsigned ShiftAmt = cast(N->getOperand(i))->getValue(); - if (ShiftAmt < i) return -1; - ShiftAmt -= i; - - // Check the rest of the elements to see if they are consequtive. - for (++i; i != 16; ++i) - if (!isConstantOrUndef(N->getOperand(i), (ShiftAmt+i) & 15)) - return -1; + if (!isUnary) { + // Check the rest of the elements to see if they are consequtive. + for (++i; i != 16; ++i) + if (!isConstantOrUndef(N->getOperand(i), ShiftAmt+i)) + return -1; + } else { + // Check the rest of the elements to see if they are consequtive. + for (++i; i != 16; ++i) + if (!isConstantOrUndef(N->getOperand(i), (ShiftAmt+i) & 15)) + return -1; + } return ShiftAmt; } @@ -872,7 +868,9 @@ if (PPC::isSplatShuffleMask(PermMask.Val, 1) || PPC::isSplatShuffleMask(PermMask.Val, 2) || PPC::isSplatShuffleMask(PermMask.Val, 4) || - PPC::isVSLDOIRotateShuffleMask(PermMask.Val) != -1 || + PPC::isVPKUWUMShuffleMask(PermMask.Val, true) || + PPC::isVPKUHUMShuffleMask(PermMask.Val, true) || + PPC::isVSLDOIShuffleMask(PermMask.Val, true) != -1 || PPC::isVMRGLShuffleMask(PermMask.Val, 1, true) || PPC::isVMRGLShuffleMask(PermMask.Val, 2, true) || PPC::isVMRGLShuffleMask(PermMask.Val, 4, true) || @@ -883,9 +881,12 @@ } } - if (PPC::isVPKUWUMShuffleMask(PermMask.Val) || - PPC::isVPKUHUMShuffleMask(PermMask.Val) || - PPC::isVSLDOIShuffleMask(PermMask.Val) != -1 || + // Altivec has a variety of "shuffle immediates" that take two vector inputs + // and produce a fixed permutation. If any of these match, do not lower to + // VPERM. + if (PPC::isVPKUWUMShuffleMask(PermMask.Val, false) || + PPC::isVPKUHUMShuffleMask(PermMask.Val, false) || + PPC::isVSLDOIShuffleMask(PermMask.Val, false) != -1 || PPC::isVMRGLShuffleMask(PermMask.Val, 1, false) || PPC::isVMRGLShuffleMask(PermMask.Val, 2, false) || PPC::isVMRGLShuffleMask(PermMask.Val, 4, false) || Index: llvm/lib/Target/PowerPC/PPCISelLowering.h diff -u llvm/lib/Target/PowerPC/PPCISelLowering.h:1.43 llvm/lib/Target/PowerPC/PPCISelLowering.h:1.44 --- llvm/lib/Target/PowerPC/PPCISelLowering.h:1.43 Thu Apr 6 17:02:42 2006 +++ llvm/lib/Target/PowerPC/PPCISelLowering.h Thu Apr 6 17:28:36 2006 @@ -104,11 +104,11 @@ namespace PPC { /// isVPKUHUMShuffleMask - Return true if this is the shuffle mask for a /// VPKUHUM instruction. - bool isVPKUHUMShuffleMask(SDNode *N); + bool isVPKUHUMShuffleMask(SDNode *N, bool isUnary); /// isVPKUWUMShuffleMask - Return true if this is the shuffle mask for a /// VPKUWUM instruction. - bool isVPKUWUMShuffleMask(SDNode *N); + bool isVPKUWUMShuffleMask(SDNode *N, bool isUnary); /// isVMRGLShuffleMask - Return true if this is a shuffle mask suitable for /// a VRGL* instruction with the specified unit size (1,2 or 4 bytes). @@ -120,11 +120,7 @@ /// isVSLDOIShuffleMask - If this is a vsldoi shuffle mask, return the shift /// amount, otherwise return -1. - int isVSLDOIShuffleMask(SDNode *N); - - /// isVSLDOIRotateShuffleMask - If this is a vsldoi rotate shuffle mask, - /// return the shift amount, otherwise return -1. This matches vsldoi(x,x). - int isVSLDOIRotateShuffleMask(SDNode *N); + int isVSLDOIShuffleMask(SDNode *N, bool isUnary); /// isSplatShuffleMask - Return true if the specified VECTOR_SHUFFLE operand /// specifies a splat of a single element that is suitable for input to Index: llvm/lib/Target/PowerPC/PPCInstrAltivec.td diff -u llvm/lib/Target/PowerPC/PPCInstrAltivec.td:1.45 llvm/lib/Target/PowerPC/PPCInstrAltivec.td:1.46 --- llvm/lib/Target/PowerPC/PPCInstrAltivec.td:1.45 Thu Apr 6 17:02:42 2006 +++ llvm/lib/Target/PowerPC/PPCInstrAltivec.td Thu Apr 6 17:28:36 2006 @@ -18,12 +18,20 @@ /// VPKUHUM_shuffle_mask/VPKUWUM_shuffle_mask - Return true if this is a valid /// shuffle mask for the VPKUHUM or VPKUWUM instructions. def VPKUHUM_shuffle_mask : PatLeaf<(build_vector), [{ - return PPC::isVPKUHUMShuffleMask(N); + return PPC::isVPKUHUMShuffleMask(N, false); }]>; def VPKUWUM_shuffle_mask : PatLeaf<(build_vector), [{ - return PPC::isVPKUWUMShuffleMask(N); + return PPC::isVPKUWUMShuffleMask(N, false); }]>; +def VPKUHUM_unary_shuffle_mask : PatLeaf<(build_vector), [{ + return PPC::isVPKUHUMShuffleMask(N, true); +}]>; +def VPKUWUM_unary_shuffle_mask : PatLeaf<(build_vector), [{ + return PPC::isVPKUWUMShuffleMask(N, true); +}]>; + + def VMRGLB_shuffle_mask : PatLeaf<(build_vector), [{ return PPC::isVMRGLShuffleMask(N, 1, false); }]>; @@ -64,20 +72,20 @@ def VSLDOI_get_imm : SDNodeXForm; def VSLDOI_shuffle_mask : PatLeaf<(build_vector), [{ - return PPC::isVSLDOIShuffleMask(N) != -1; + return PPC::isVSLDOIShuffleMask(N, false) != -1; }], VSLDOI_get_imm>; -/// VSLDOI_rotate* - These are used to match vsldoi(X,X), which is turned into +/// VSLDOI_unary* - These are used to match vsldoi(X,X), which is turned into /// vector_shuffle(X,undef,mask) by the dag combiner. -def VSLDOI_rotate_get_imm : SDNodeXForm; -def VSLDOI_rotate_shuffle_mask : PatLeaf<(build_vector), [{ - return PPC::isVSLDOIRotateShuffleMask(N) != -1; -}], VSLDOI_rotate_get_imm>; +def VSLDOI_unary_shuffle_mask : PatLeaf<(build_vector), [{ + return PPC::isVSLDOIShuffleMask(N, true) != -1; +}], VSLDOI_unary_get_imm>; // VSPLT*_get_imm xform function: convert vector_shuffle mask to VSPLT* imm. @@ -581,9 +589,13 @@ // Shuffles. -// Match vsldoi(x,x) -def:Pat<(vector_shuffle (v16i8 VRRC:$vA),undef, VSLDOI_rotate_shuffle_mask:$in), - (VSLDOI VRRC:$vA, VRRC:$vA, VSLDOI_rotate_shuffle_mask:$in)>; +// Match vsldoi(x,x), vpkuwum(x,x), vpkuhum(x,x) +def:Pat<(vector_shuffle (v16i8 VRRC:$vA), undef, VSLDOI_unary_shuffle_mask:$in), + (VSLDOI VRRC:$vA, VRRC:$vA, VSLDOI_unary_shuffle_mask:$in)>; +def:Pat<(vector_shuffle (v16i8 VRRC:$vA), undef,VPKUWUM_unary_shuffle_mask:$in), + (VPKUWUM VRRC:$vA, VRRC:$vA)>; +def:Pat<(vector_shuffle (v16i8 VRRC:$vA), undef,VPKUHUM_unary_shuffle_mask:$in), + (VPKUHUM VRRC:$vA, VRRC:$vA)>; // Match vmrg*(x,x) def:Pat<(vector_shuffle (v16i8 VRRC:$vA), undef, VMRGLB_unary_shuffle_mask:$in), @@ -599,7 +611,6 @@ def:Pat<(vector_shuffle (v16i8 VRRC:$vA), undef, VMRGHW_unary_shuffle_mask:$in), (VMRGHW VRRC:$vA, VRRC:$vA)>; - // Immediate vector formation with vsplti*. def : Pat<(v16i8 vecspltisb:$invec), (v16i8 (VSPLTISB vecspltisb:$invec))>; def : Pat<(v16i8 vecspltish:$invec), (v16i8 (VSPLTISH vecspltish:$invec))>; From alenhar2 at cs.uiuc.edu Thu Apr 6 17:59:21 2006 From: alenhar2 at cs.uiuc.edu (Andrew Lenharth) Date: Thu, 6 Apr 2006 17:59:21 -0500 Subject: [llvm-commits] CVS: llvm/lib/VMCore/ConstantRange.cpp Message-ID: <200604062259.RAA18551@apoc.cs.uiuc.edu> Changes in directory llvm/lib/VMCore: ConstantRange.cpp (r1.14) removed --- Log message: Move this to lib/Analysis. This reduces Core size, yay. --- Diffs of the changes: (+0 -0) 0 files changed From lattner at cs.uiuc.edu Thu Apr 6 18:12:32 2006 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Thu, 6 Apr 2006 18:12:32 -0500 Subject: [llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCISelLowering.cpp Message-ID: <200604062312.SAA00991@zion.cs.uiuc.edu> Changes in directory llvm/lib/Target/PowerPC: PPCISelLowering.cpp updated: 1.137 -> 1.138 --- Log message: Make sure to return the result in the right type. --- Diffs of the changes: (+6 -4) PPCISelLowering.cpp | 10 ++++++---- 1 files changed, 6 insertions(+), 4 deletions(-) Index: llvm/lib/Target/PowerPC/PPCISelLowering.cpp diff -u llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.137 llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.138 --- llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.137 Thu Apr 6 17:28:36 2006 +++ llvm/lib/Target/PowerPC/PPCISelLowering.cpp Thu Apr 6 18:12:19 2006 @@ -962,10 +962,12 @@ assert(CompareOpc>0 && "We only lower altivec predicate compares so far!"); // If this is a non-dot comparison, make the VCMP node. - if (!isDot) - return DAG.getNode(PPCISD::VCMP, Op.getOperand(2).getValueType(), - Op.getOperand(1), Op.getOperand(2), - DAG.getConstant(CompareOpc, MVT::i32)); + if (!isDot) { + SDOperand Tmp = DAG.getNode(PPCISD::VCMP, Op.getOperand(2).getValueType(), + Op.getOperand(1), Op.getOperand(2), + DAG.getConstant(CompareOpc, MVT::i32)); + return DAG.getNode(ISD::BIT_CONVERT, Op.getValueType(), Tmp); + } // Create the PPCISD altivec 'dot' comparison node. std::vector Ops; From lattner at cs.uiuc.edu Thu Apr 6 18:16:31 2006 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Thu, 6 Apr 2006 18:16:31 -0500 Subject: [llvm-commits] CVS: llvm/lib/Target/PowerPC/README_ALTIVEC.txt Message-ID: <200604062316.SAA01061@zion.cs.uiuc.edu> Changes in directory llvm/lib/Target/PowerPC: README_ALTIVEC.txt updated: 1.18 -> 1.19 --- Log message: Add an item --- Diffs of the changes: (+6 -1) README_ALTIVEC.txt | 7 ++++++- 1 files changed, 6 insertions(+), 1 deletion(-) Index: llvm/lib/Target/PowerPC/README_ALTIVEC.txt diff -u llvm/lib/Target/PowerPC/README_ALTIVEC.txt:1.18 llvm/lib/Target/PowerPC/README_ALTIVEC.txt:1.19 --- llvm/lib/Target/PowerPC/README_ALTIVEC.txt:1.18 Thu Apr 6 16:11:54 2006 +++ llvm/lib/Target/PowerPC/README_ALTIVEC.txt Thu Apr 6 18:16:19 2006 @@ -9,7 +9,7 @@ second should be a xor/stvx: void foo(void) { - int x[8] __attribute__((aligned(128))) = { 1, 1, 1, 1, 1, 1, 1, 1 }; + int x[8] __attribute__((aligned(128))) = { 1, 1, 1, 17, 1, 1, 1, 1 }; bar (x); } @@ -129,3 +129,8 @@ //===----------------------------------------------------------------------===// +There are a wide variety of vector_shuffle operations that we can do with a pair +of instructions (e.g. a vsldoi + vpkuhum). We should pattern match these, but +there are a huge number of these. + +//===----------------------------------------------------------------------===// From alenhar2 at cs.uiuc.edu Thu Apr 6 18:18:58 2006 From: alenhar2 at cs.uiuc.edu (Andrew Lenharth) Date: Thu, 6 Apr 2006 18:18:58 -0500 Subject: [llvm-commits] CVS: llvm/lib/Target/Alpha/AlphaISelLowering.cpp Message-ID: <200604062318.SAA01102@zion.cs.uiuc.edu> Changes in directory llvm/lib/Target/Alpha: AlphaISelLowering.cpp updated: 1.45 -> 1.46 --- Log message: This may be overconservative, but it lets the new cfe compile --- Diffs of the changes: (+2 -1) AlphaISelLowering.cpp | 3 ++- 1 files changed, 2 insertions(+), 1 deletion(-) Index: llvm/lib/Target/Alpha/AlphaISelLowering.cpp diff -u llvm/lib/Target/Alpha/AlphaISelLowering.cpp:1.45 llvm/lib/Target/Alpha/AlphaISelLowering.cpp:1.46 --- llvm/lib/Target/Alpha/AlphaISelLowering.cpp:1.45 Thu Apr 6 16:26:32 2006 +++ llvm/lib/Target/Alpha/AlphaISelLowering.cpp Thu Apr 6 18:18:45 2006 @@ -571,7 +571,8 @@ GlobalValue *GV = GSDN->getGlobal(); SDOperand GA = DAG.getTargetGlobalAddress(GV, MVT::i64, GSDN->getOffset()); - if (!GV->hasWeakLinkage() && !GV->isExternal() && !GV->hasLinkOnceLinkage()) { + // if (!GV->hasWeakLinkage() && !GV->isExternal() && !GV->hasLinkOnceLinkage()) { + if (GV->hasInternalLinkage()) { SDOperand Hi = DAG.getNode(AlphaISD::GPRelHi, MVT::i64, GA, DAG.getNode(AlphaISD::GlobalBaseReg, MVT::i64)); SDOperand Lo = DAG.getNode(AlphaISD::GPRelLo, MVT::i64, GA, Hi); From evan.cheng at apple.com Thu Apr 6 18:20:56 2006 From: evan.cheng at apple.com (Evan Cheng) Date: Thu, 6 Apr 2006 18:20:56 -0500 Subject: [llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Message-ID: <200604062320.SAA01127@zion.cs.uiuc.edu> Changes in directory llvm/lib/CodeGen/SelectionDAG: DAGCombiner.cpp updated: 1.144 -> 1.145 --- Log message: 1. If both vector operands of a vector_shuffle are undef, turn it into an undef. 2. A shuffle mask element can also be an undef. --- Diffs of the changes: (+6 -3) DAGCombiner.cpp | 9 ++++++--- 1 files changed, 6 insertions(+), 3 deletions(-) Index: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp diff -u llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.144 llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.145 --- llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.144 Tue Apr 4 12:39:18 2006 +++ llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Thu Apr 6 18:20:43 2006 @@ -2673,16 +2673,19 @@ // If the LHS and the RHS are the same node, turn the RHS into an undef. if (N->getOperand(0) == N->getOperand(1)) { + if (N->getOperand(0).getOpcode() == ISD::UNDEF) + return DAG.getNode(ISD::UNDEF, N->getValueType(0)); // Check the SHUFFLE mask, mapping any inputs from the 2nd operand into the // first operand. std::vector MappedOps; for (unsigned i = 0, e = ShufMask.getNumOperands(); i != e; ++i) { - if (cast(ShufMask.getOperand(i))->getValue() >= NumElts) { + if (ShufMask.getOperand(i).getOpcode() == ISD::UNDEF || + cast(ShufMask.getOperand(i))->getValue() < NumElts) { + MappedOps.push_back(ShufMask.getOperand(i)); + } else { unsigned NewIdx = cast(ShufMask.getOperand(i))->getValue() - NumElts; MappedOps.push_back(DAG.getConstant(NewIdx, MVT::i32)); - } else { - MappedOps.push_back(ShufMask.getOperand(i)); } } ShufMask = DAG.getNode(ISD::BUILD_VECTOR, ShufMask.getValueType(), From evan.cheng at apple.com Thu Apr 6 18:21:37 2006 From: evan.cheng at apple.com (Evan Cheng) Date: Thu, 6 Apr 2006 18:21:37 -0500 Subject: [llvm-commits] CVS: llvm/lib/Target/X86/README.txt Message-ID: <200604062321.SAA01146@zion.cs.uiuc.edu> Changes in directory llvm/lib/Target/X86: README.txt updated: 1.79 -> 1.80 --- Log message: New entries. --- Diffs of the changes: (+56 -0) README.txt | 56 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++ 1 files changed, 56 insertions(+) Index: llvm/lib/Target/X86/README.txt diff -u llvm/lib/Target/X86/README.txt:1.79 llvm/lib/Target/X86/README.txt:1.80 --- llvm/lib/Target/X86/README.txt:1.79 Wed Apr 5 18:46:04 2006 +++ llvm/lib/Target/X86/README.txt Thu Apr 6 18:21:24 2006 @@ -704,3 +704,59 @@ so a any extend (which becomes a zero extend) is added. We probably need some kind of target DAG combine hook to fix this. + +//===---------------------------------------------------------------------===// + +How to decide when to use the "floating point version" of logical ops? Here are +some code fragments: + + movaps LCPI5_5, %xmm2 + divps %xmm1, %xmm2 + mulps %xmm2, %xmm3 + mulps 8656(%ecx), %xmm3 + addps 8672(%ecx), %xmm3 + andps LCPI5_6, %xmm2 + andps LCPI5_1, %xmm3 + por %xmm2, %xmm3 + movdqa %xmm3, (%edi) + + movaps LCPI5_5, %xmm1 + divps %xmm0, %xmm1 + mulps %xmm1, %xmm3 + mulps 8656(%ecx), %xmm3 + addps 8672(%ecx), %xmm3 + andps LCPI5_6, %xmm1 + andps LCPI5_1, %xmm3 + orps %xmm1, %xmm3 + movaps %xmm3, 112(%esp) + movaps %xmm3, (%ebx) + +Due to some minor source change, the later case ended up using orps and movaps +instead of por and movdqa. Does it matter? + +//===---------------------------------------------------------------------===// + +Use movddup to splat a v2f64 directly from a memory source. e.g. + +#include + +void test(__m128d *r, double A) { + *r = _mm_set1_pd(A); +} + +llc: + +_test: + movsd 8(%esp), %xmm0 + unpcklpd %xmm0, %xmm0 + movl 4(%esp), %eax + movapd %xmm0, (%eax) + ret + +icc: + +_test: + movl 4(%esp), %eax + movddup 8(%esp), %xmm0 + movapd %xmm0, (%eax) + ret From evan.cheng at apple.com Thu Apr 6 18:24:09 2006 From: evan.cheng at apple.com (Evan Cheng) Date: Thu, 6 Apr 2006 18:24:09 -0500 Subject: [llvm-commits] CVS: llvm/lib/Target/X86/X86ISelLowering.cpp X86ISelLowering.h X86InstrSSE.td Message-ID: <200604062324.SAA01173@zion.cs.uiuc.edu> Changes in directory llvm/lib/Target/X86: X86ISelLowering.cpp updated: 1.158 -> 1.159 X86ISelLowering.h updated: 1.52 -> 1.53 X86InstrSSE.td updated: 1.64 -> 1.65 --- Log message: - movlp{s|d} and movhp{s|d} support. - Normalize shuffle nodes so result vector lower half elements come from the first vector, the rest come from the second vector. (Except for the exceptions :-). - Other minor fixes. --- Diffs of the changes: (+206 -66) X86ISelLowering.cpp | 234 ++++++++++++++++++++++++++++++++++++++-------------- X86ISelLowering.h | 8 + X86InstrSSE.td | 30 +++++- 3 files changed, 206 insertions(+), 66 deletions(-) Index: llvm/lib/Target/X86/X86ISelLowering.cpp diff -u llvm/lib/Target/X86/X86ISelLowering.cpp:1.158 llvm/lib/Target/X86/X86ISelLowering.cpp:1.159 --- llvm/lib/Target/X86/X86ISelLowering.cpp:1.158 Wed Apr 5 18:38:46 2006 +++ llvm/lib/Target/X86/X86ISelLowering.cpp Thu Apr 6 18:23:56 2006 @@ -1404,6 +1404,16 @@ (GV->isExternal() && !GV->hasNotBeenReadFromBytecode())); } +/// isUndefOrInRange - Op is either an undef node or a ConstantSDNode. Return +/// true if Op is undef or if its value falls within the specified range (L, H). +static bool isUndefOrInRange(SDOperand Op, unsigned Low, unsigned Hi) { + if (Op.getOpcode() == ISD::UNDEF) + return true; + + unsigned Val = cast(Op)->getValue(); + return (Val >= Low && Val <= Hi); +} + /// isPSHUFDMask - Return true if the specified VECTOR_SHUFFLE operand /// specifies a shuffle of elements that is suitable for input to PSHUFD. bool X86::isPSHUFDMask(SDNode *N) { @@ -1491,24 +1501,17 @@ unsigned NumElems = N->getNumOperands(); if (NumElems == 2) { - // The only case that ought be handled by SHUFPD is + // The only cases that ought be handled by SHUFPD is // Dest { 2, 1 } <= shuffle( Dest { 1, 0 }, Src { 3, 2 } + // Dest { 3, 0 } <= shuffle( Dest { 1, 0 }, Src { 3, 2 } // Expect bit 0 == 1, bit1 == 2 SDOperand Bit0 = N->getOperand(0); - if (Bit0.getOpcode() != ISD::UNDEF) { - assert(isa(Bit0) && "Invalid VECTOR_SHUFFLE mask!"); - if (cast(Bit0)->getValue() != 1) - return false; - } - SDOperand Bit1 = N->getOperand(1); - if (Bit1.getOpcode() != ISD::UNDEF) { - assert(isa(Bit1) && "Invalid VECTOR_SHUFFLE mask!"); - if (cast(Bit1)->getValue() != 2) - return false; - } - - return true; + if (isUndefOrInRange(Bit0, 0, 0) && isUndefOrInRange(Bit1, 3, 3)) + return true; + if (isUndefOrInRange(Bit0, 1, 1) && isUndefOrInRange(Bit1, 2, 2)) + return true; + return false; } if (NumElems != 4) return false; @@ -1614,6 +1617,62 @@ return true; } +/// isMOVLPMask - Return true if the specified VECTOR_SHUFFLE operand +/// specifies a shuffle of elements that is suitable for input to MOVLP{S|D}. +bool X86::isMOVLPMask(SDNode *N) { + assert(N->getOpcode() == ISD::BUILD_VECTOR); + + unsigned NumElems = N->getNumOperands(); + if (NumElems != 2 && NumElems != 4) + return false; + + for (unsigned i = 0; i < NumElems/2; ++i) { + SDOperand Arg = N->getOperand(i); + if (Arg.getOpcode() == ISD::UNDEF) continue; + assert(isa(Arg) && "Invalid VECTOR_SHUFFLE mask!"); + unsigned Val = cast(Arg)->getValue(); + if (Val != i + NumElems) return false; + } + + for (unsigned i = NumElems/2; i < NumElems; ++i) { + SDOperand Arg = N->getOperand(i); + if (Arg.getOpcode() == ISD::UNDEF) continue; + assert(isa(Arg) && "Invalid VECTOR_SHUFFLE mask!"); + unsigned Val = cast(Arg)->getValue(); + if (Val != i) return false; + } + + return true; +} + +/// isMOVHPMask - Return true if the specified VECTOR_SHUFFLE operand +/// specifies a shuffle of elements that is suitable for input to MOVHP{S|D}. +bool X86::isMOVHPMask(SDNode *N) { + assert(N->getOpcode() == ISD::BUILD_VECTOR); + + unsigned NumElems = N->getNumOperands(); + if (NumElems != 2 && NumElems != 4) + return false; + + for (unsigned i = 0; i < NumElems/2; ++i) { + SDOperand Arg = N->getOperand(i); + if (Arg.getOpcode() == ISD::UNDEF) continue; + assert(isa(Arg) && "Invalid VECTOR_SHUFFLE mask!"); + unsigned Val = cast(Arg)->getValue(); + if (Val != i) return false; + } + + for (unsigned i = 0; i < NumElems/2; ++i) { + SDOperand Arg = N->getOperand(i + NumElems/2); + if (Arg.getOpcode() == ISD::UNDEF) continue; + assert(isa(Arg) && "Invalid VECTOR_SHUFFLE mask!"); + unsigned Val = cast(Arg)->getValue(); + if (Val != i + NumElems) return false; + } + + return true; +} + /// isUNPCKLMask - Return true if the specified VECTOR_SHUFFLE operand /// specifies a shuffle of elements that is suitable for input to UNPCKL. bool X86::isUNPCKLMask(SDNode *N) { @@ -1786,42 +1845,6 @@ return Mask; } -/// NormalizeVectorShuffle - Swap vector_shuffle operands (as well as -/// values in ther permute mask if needed. Use V1 as second vector if it is -/// undef. Return an empty SDOperand is it is already well formed. -static SDOperand NormalizeVectorShuffle(SDOperand Op, SelectionDAG &DAG) { - SDOperand V1 = Op.getOperand(0); - SDOperand V2 = Op.getOperand(1); - SDOperand Mask = Op.getOperand(2); - MVT::ValueType VT = Op.getValueType(); - unsigned NumElems = Mask.getNumOperands(); - SDOperand Half1 = Mask.getOperand(0); - SDOperand Half2 = Mask.getOperand(NumElems/2); - bool V2Undef = false; - if (V2.getOpcode() == ISD::UNDEF) { - V2Undef = true; - V2 = V1; - } - - if (cast(Half1)->getValue() >= NumElems && - cast(Half2)->getValue() < NumElems) { - // Swap the operands and change mask. - std::vector MaskVec; - for (unsigned i = NumElems / 2; i != NumElems; ++i) - MaskVec.push_back(Mask.getOperand(i)); - for (unsigned i = 0; i != NumElems / 2; ++i) - MaskVec.push_back(Mask.getOperand(i)); - Mask = - DAG.getNode(ISD::BUILD_VECTOR, Mask.getValueType(), MaskVec); - return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V2, V1, Mask); - } - - if (V2Undef) - return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V1, Mask); - - return Op; -} - /// isPSHUFHW_PSHUFLWMask - true if the specified VECTOR_SHUFFLE operand /// specifies a 8 element shuffle that can be broken into a pair of /// PSHUFHW and PSHUFLW. @@ -1854,6 +1877,81 @@ return true; } +/// CommuteVectorShuffle - Swap vector_shuffle operandsas well as +/// values in ther permute mask. +static SDOperand CommuteVectorShuffle(SDOperand Op, SelectionDAG &DAG) { + SDOperand V1 = Op.getOperand(0); + SDOperand V2 = Op.getOperand(1); + SDOperand Mask = Op.getOperand(2); + MVT::ValueType VT = Op.getValueType(); + MVT::ValueType MaskVT = Mask.getValueType(); + MVT::ValueType EltVT = MVT::getVectorBaseType(MaskVT); + unsigned NumElems = Mask.getNumOperands(); + std::vector MaskVec; + + for (unsigned i = 0; i != NumElems; ++i) { + SDOperand Arg = Mask.getOperand(i); + if (Arg.getOpcode() == ISD::UNDEF) continue; + assert(isa(Arg) && "Invalid VECTOR_SHUFFLE mask!"); + unsigned Val = cast(Arg)->getValue(); + if (Val < NumElems) + MaskVec.push_back(DAG.getConstant(Val + NumElems, EltVT)); + else + MaskVec.push_back(DAG.getConstant(Val - NumElems, EltVT)); + } + + Mask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT, MaskVec); + return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V2, V1, Mask); +} + +/// isScalarLoadToVector - Returns true if the node is a scalar load that +/// is promoted to a vector. +static inline bool isScalarLoadToVector(SDOperand Op) { + if (Op.getOpcode() == ISD::SCALAR_TO_VECTOR) { + Op = Op.getOperand(0); + return (Op.getOpcode() == ISD::LOAD); + } + return false; +} + +/// ShouldXformedToMOVLP - Return true if the node should be transformed to +/// match movlp{d|s}. The lower half elements should come from V1 (and in +/// order), and the upper half elements should come from the upper half of +/// V2 (not necessarily in order). And since V1 will become the source of +/// the MOVLP, it must be a scalar load. +static bool ShouldXformedToMOVLP(SDOperand V1, SDOperand V2, SDOperand Mask) { + if (isScalarLoadToVector(V1)) { + unsigned NumElems = Mask.getNumOperands(); + for (unsigned i = 0, e = NumElems/2; i != e; ++i) + if (!isUndefOrInRange(Mask.getOperand(i), i, i)) + return false; + for (unsigned i = NumElems/2; i != NumElems; ++i) + if (!isUndefOrInRange(Mask.getOperand(i), + NumElems+NumElems/2, NumElems*2-1)) + return false; + return true; + } + + return false; +} + +/// isLowerFromV2UpperFromV1 - Returns true if the shuffle mask is except +/// the reverse of what x86 shuffles want. x86 shuffles requires the lower +/// half elements to come from vector 1 (which would equal the dest.) and +/// the upper half to come from vector 2. +static bool isLowerFromV2UpperFromV1(SDOperand Op) { + assert(Op.getOpcode() == ISD::BUILD_VECTOR); + + unsigned NumElems = Op.getNumOperands(); + for (unsigned i = 0, e = NumElems/2; i != e; ++i) + if (!isUndefOrInRange(Op.getOperand(i), NumElems, NumElems*2-1)) + return false; + for (unsigned i = NumElems/2; i != NumElems; ++i) + if (!isUndefOrInRange(Op.getOperand(i), 0, NumElems-1)) + return false; + return true; +} + /// LowerOperation - Provide custom lowering hooks for some operations. /// SDOperand X86TargetLowering::LowerOperation(SDOperand Op, SelectionDAG &DAG) { @@ -2638,23 +2736,35 @@ MVT::ValueType VT = Op.getValueType(); unsigned NumElems = PermMask.getNumOperands(); - // Splat && PSHUFD's 2nd vector must be undef. - if (X86::isSplatMask(PermMask.Val)) { - if (V2.getOpcode() != ISD::UNDEF) - return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, - DAG.getNode(ISD::UNDEF, V1.getValueType()),PermMask); + if (X86::isSplatMask(PermMask.Val)) return Op; + + // Normalize the node to match x86 shuffle ops if needed + if (V2.getOpcode() != ISD::UNDEF) { + bool DoSwap = false; + + if (ShouldXformedToMOVLP(V1, V2, PermMask)) + DoSwap = true; + else if (isLowerFromV2UpperFromV1(PermMask)) + DoSwap = true; + + if (DoSwap) { + Op = CommuteVectorShuffle(Op, DAG); + V1 = Op.getOperand(0); + V2 = Op.getOperand(1); + PermMask = Op.getOperand(2); + } } + if (NumElems == 2) + return Op; + if (X86::isUNPCKLMask(PermMask.Val) || X86::isUNPCKL_v_undef_Mask(PermMask.Val) || X86::isUNPCKHMask(PermMask.Val)) // Leave the VECTOR_SHUFFLE alone. It matches {P}UNPCKL*. return Op; - if (NumElems == 2) - return NormalizeVectorShuffle(Op, DAG); - // If VT is integer, try PSHUF* first, then SHUFP*. if (MVT::isInteger(VT)) { if (X86::isPSHUFDMask(PermMask.Val) || @@ -2667,7 +2777,7 @@ } if (X86::isSHUFPMask(PermMask.Val)) - return NormalizeVectorShuffle(Op, DAG); + return Op; // Handle v8i16 shuffle high / low shuffle node pair. if (VT == MVT::v8i16 && isPSHUFHW_PSHUFLWMask(PermMask.Val)) { @@ -2691,7 +2801,7 @@ } else { // Floating point cases in the other order. if (X86::isSHUFPMask(PermMask.Val)) - return NormalizeVectorShuffle(Op, DAG); + return Op; if (X86::isPSHUFDMask(PermMask.Val) || X86::isPSHUFHWMask(PermMask.Val) || X86::isPSHUFLWMask(PermMask.Val)) { @@ -2870,8 +2980,8 @@ case Intrinsic::x86_sse2_ucomigt_sd: case Intrinsic::x86_sse2_ucomige_sd: case Intrinsic::x86_sse2_ucomineq_sd: { - unsigned Opc; - ISD::CondCode CC; + unsigned Opc = 0; + ISD::CondCode CC = ISD::SETCC_INVALID; switch (IntNo) { default: break; case Intrinsic::x86_sse_comieq_ss: Index: llvm/lib/Target/X86/X86ISelLowering.h diff -u llvm/lib/Target/X86/X86ISelLowering.h:1.52 llvm/lib/Target/X86/X86ISelLowering.h:1.53 --- llvm/lib/Target/X86/X86ISelLowering.h:1.52 Wed Apr 5 18:38:46 2006 +++ llvm/lib/Target/X86/X86ISelLowering.h Thu Apr 6 18:23:56 2006 @@ -212,6 +212,14 @@ /// specifies a shuffle of elements that is suitable for input to MOVHLPS. bool isMOVHLPSMask(SDNode *N); + /// isMOVLPMask - Return true if the specified VECTOR_SHUFFLE operand + /// specifies a shuffle of elements that is suitable for input to MOVLP{S|D}. + bool isMOVLPMask(SDNode *N); + + /// isMOVHPMask - Return true if the specified VECTOR_SHUFFLE operand + /// specifies a shuffle of elements that is suitable for input to MOVHP{S|D}. + bool isMOVHPMask(SDNode *N); + /// isUNPCKLMask - Return true if the specified VECTOR_SHUFFLE operand /// specifies a shuffle of elements that is suitable for input to UNPCKL. bool isUNPCKLMask(SDNode *N); Index: llvm/lib/Target/X86/X86InstrSSE.td diff -u llvm/lib/Target/X86/X86InstrSSE.td:1.64 llvm/lib/Target/X86/X86InstrSSE.td:1.65 --- llvm/lib/Target/X86/X86InstrSSE.td:1.64 Wed Apr 5 20:49:20 2006 +++ llvm/lib/Target/X86/X86InstrSSE.td Thu Apr 6 18:23:56 2006 @@ -96,6 +96,14 @@ return X86::isMOVHLPSMask(N); }]>; +def MOVHP_shuffle_mask : PatLeaf<(build_vector), [{ + return X86::isMOVHPMask(N); +}]>; + +def MOVLP_shuffle_mask : PatLeaf<(build_vector), [{ + return X86::isMOVLPMask(N); +}]>; + def UNPCKL_shuffle_mask : PatLeaf<(build_vector), [{ return X86::isUNPCKLMask(N); }]>; @@ -712,17 +720,29 @@ let isTwoAddress = 1 in { def MOVLPSrm : PSI<0x12, MRMSrcMem, (ops VR128:$dst, VR128:$src1, f64mem:$src2), - "movlps {$src2, $dst|$dst, $src2}", []>; + "movlps {$src2, $dst|$dst, $src2}", + [(set VR128:$dst, + (v4f32 (vector_shuffle VR128:$src1, + (bc_v4f32 (v2f64 (scalar_to_vector (loadf64 addr:$src2)))), + MOVLP_shuffle_mask)))]>; def MOVLPDrm : PDI<0x12, MRMSrcMem, (ops VR128:$dst, VR128:$src1, f64mem:$src2), - "movlpd {$src2, $dst|$dst, $src2}", []>; + "movlpd {$src2, $dst|$dst, $src2}", + [(set VR128:$dst, + (v2f64 (vector_shuffle VR128:$src1, + (scalar_to_vector (loadf64 addr:$src2)), + MOVLP_shuffle_mask)))]>; def MOVHPSrm : PSI<0x16, MRMSrcMem, (ops VR128:$dst, VR128:$src1, f64mem:$src2), - "movhps {$src2, $dst|$dst, $src2}", []>; + "movhps {$src2, $dst|$dst, $src2}", + [(set VR128:$dst, + (v4f32 (vector_shuffle VR128:$src1, + (bc_v4f32 (v2f64 (scalar_to_vector (loadf64 addr:$src2)))), + MOVHP_shuffle_mask)))]>; def MOVHPDrm : PDI<0x16, MRMSrcMem, (ops VR128:$dst, VR128:$src1, f64mem:$src2), "movhpd {$src2, $dst|$dst, $src2}", [(set VR128:$dst, (v2f64 (vector_shuffle VR128:$src1, (scalar_to_vector (loadf64 addr:$src2)), - UNPCKL_shuffle_mask)))]>; + MOVHP_shuffle_mask)))]>; } def MOVLPSmr : PSI<0x13, MRMDestMem, (ops f64mem:$dst, VR128:$src), @@ -1706,6 +1726,8 @@ Requires<[HasSSE2]>; def : Pat<(v4f32 (bitconvert (v4i32 VR128:$src))), (v4f32 VR128:$src)>, Requires<[HasSSE2]>; +def : Pat<(v4f32 (bitconvert (v2f64 VR128:$src))), (v4f32 VR128:$src)>, + Requires<[HasSSE2]>; // Zeroing a VR128 then do a MOVS* to the lower bits. def : Pat<(v2f64 (X86zexts2vec FR64:$src)), From evan.cheng at apple.com Thu Apr 6 18:25:53 2006 From: evan.cheng at apple.com (Evan Cheng) Date: Thu, 6 Apr 2006 18:25:53 -0500 Subject: [llvm-commits] CVS: llvm/include/llvm/IntrinsicsX86.td Message-ID: <200604062325.SAA01196@zion.cs.uiuc.edu> Changes in directory llvm/include/llvm: IntrinsicsX86.td updated: 1.10 -> 1.11 --- Log message: Remove int_x86_sse_loadh_ps and int_x86_sse_loadl_ps. These are now lowered by the frontend to shuffles. --- Diffs of the changes: (+0 -4) IntrinsicsX86.td | 4 ---- 1 files changed, 4 deletions(-) Index: llvm/include/llvm/IntrinsicsX86.td diff -u llvm/include/llvm/IntrinsicsX86.td:1.10 llvm/include/llvm/IntrinsicsX86.td:1.11 --- llvm/include/llvm/IntrinsicsX86.td:1.10 Wed Apr 5 18:37:18 2006 +++ llvm/include/llvm/IntrinsicsX86.td Thu Apr 6 18:25:41 2006 @@ -126,10 +126,6 @@ // SIMD load ops let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.". - def int_x86_sse_loadh_ps : GCCBuiltin<"__builtin_ia32_loadhps">, - Intrinsic<[llvm_v4f32_ty, llvm_ptr_ty], [IntrReadMem]>; - def int_x86_sse_loadl_ps : GCCBuiltin<"__builtin_ia32_loadlps">, - Intrinsic<[llvm_v4f32_ty, llvm_ptr_ty], [IntrReadMem]>; def int_x86_sse_loadu_ps : GCCBuiltin<"__builtin_ia32_loadups">, Intrinsic<[llvm_v4f32_ty, llvm_ptr_ty], [IntrReadMem]>; } From evan.cheng at apple.com Thu Apr 6 18:53:42 2006 From: evan.cheng at apple.com (Evan Cheng) Date: Thu, 6 Apr 2006 18:53:42 -0500 Subject: [llvm-commits] CVS: llvm/lib/Target/X86/X86InstrSSE.td Message-ID: <200604062353.SAA01367@zion.cs.uiuc.edu> Changes in directory llvm/lib/Target/X86: X86InstrSSE.td updated: 1.65 -> 1.66 --- Log message: A MOVPS2SSmr, i.e. _mm_store_ss, encoding bug. Also MOVPDI2DIrr. --- Diffs of the changes: (+2 -2) X86InstrSSE.td | 4 ++-- 1 files changed, 2 insertions(+), 2 deletions(-) Index: llvm/lib/Target/X86/X86InstrSSE.td diff -u llvm/lib/Target/X86/X86InstrSSE.td:1.65 llvm/lib/Target/X86/X86InstrSSE.td:1.66 --- llvm/lib/Target/X86/X86InstrSSE.td:1.65 Thu Apr 6 18:23:56 2006 +++ llvm/lib/Target/X86/X86InstrSSE.td Thu Apr 6 18:53:29 2006 @@ -1599,7 +1599,7 @@ "movss {$src, $dst|$dst, $src}", [(set FR32:$dst, (vector_extract (v4f32 VR128:$src), (i32 0)))]>; -def MOVPS2SSmr : SSI<0x10, MRMDestMem, (ops f32mem:$dst, VR128:$src), +def MOVPS2SSmr : SSI<0x11, MRMDestMem, (ops f32mem:$dst, VR128:$src), "movss {$src, $dst|$dst, $src}", [(store (f32 (vector_extract (v4f32 VR128:$src), (i32 0))), addr:$dst)]>; @@ -1607,7 +1607,7 @@ "movsd {$src, $dst|$dst, $src}", [(set FR64:$dst, (vector_extract (v2f64 VR128:$src), (i32 0)))]>; -def MOVPDI2DIrr : PDI<0x7E, MRMSrcReg, (ops R32:$dst, VR128:$src), +def MOVPDI2DIrr : PDI<0x6E, MRMSrcReg, (ops R32:$dst, VR128:$src), "movd {$src, $dst|$dst, $src}", [(set R32:$dst, (vector_extract (v4i32 VR128:$src), (i32 0)))]>; From evan.cheng at apple.com Thu Apr 6 20:27:55 2006 From: evan.cheng at apple.com (Evan Cheng) Date: Thu, 6 Apr 2006 20:27:55 -0500 Subject: [llvm-commits] CVS: llvm/lib/Linker/LinkModules.cpp Message-ID: <200604070127.UAA01694@zion.cs.uiuc.edu> Changes in directory llvm/lib/Linker: LinkModules.cpp updated: 1.111 -> 1.112 --- Log message: Add code to RemapOperand() to handle Instruction::ExtractElement and Instruction::InsertElement. --- Diffs of the changes: (+12 -0) LinkModules.cpp | 12 ++++++++++++ 1 files changed, 12 insertions(+) Index: llvm/lib/Linker/LinkModules.cpp diff -u llvm/lib/Linker/LinkModules.cpp:1.111 llvm/lib/Linker/LinkModules.cpp:1.112 --- llvm/lib/Linker/LinkModules.cpp:1.111 Mon Jan 23 22:14:29 2006 +++ llvm/lib/Linker/LinkModules.cpp Thu Apr 6 20:27:42 2006 @@ -305,6 +305,18 @@ ValueMap))); Result = ConstantExpr::getGetElementPtr(cast(Ptr), Indices); + } else if (CE->getOpcode() == Instruction::ExtractElement) { + Value *Ptr = RemapOperand(CE->getOperand(0), ValueMap); + Value *Idx = RemapOperand(CE->getOperand(1), ValueMap); + Result = ConstantExpr::getExtractElement(cast(Ptr), + cast(Idx)); + } else if (CE->getOpcode() == Instruction::InsertElement) { + Value *Ptr = RemapOperand(CE->getOperand(0), ValueMap); + Value *Elt = RemapOperand(CE->getOperand(1), ValueMap); + Value *Idx = RemapOperand(CE->getOperand(2), ValueMap); + Result = ConstantExpr::getInsertElement(cast(Ptr), + cast(Elt), + cast(Idx)); } else if (CE->getNumOperands() == 1) { // Cast instruction assert(CE->getOpcode() == Instruction::Cast); From lattner at cs.uiuc.edu Thu Apr 6 23:41:56 2006 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Thu, 6 Apr 2006 23:41:56 -0500 Subject: [llvm-commits] CVS: llvm/lib/Transforms/Utils/ValueMapper.cpp Message-ID: <200604070441.XAA02341@zion.cs.uiuc.edu> Changes in directory llvm/lib/Transforms/Utils: ValueMapper.cpp updated: 1.23 -> 1.24 --- Log message: Fix inlining of insert/extract element constantexprs --- Diffs of the changes: (+9 -0) ValueMapper.cpp | 9 +++++++++ 1 files changed, 9 insertions(+) Index: llvm/lib/Transforms/Utils/ValueMapper.cpp diff -u llvm/lib/Transforms/Utils/ValueMapper.cpp:1.23 llvm/lib/Transforms/Utils/ValueMapper.cpp:1.24 --- llvm/lib/Transforms/Utils/ValueMapper.cpp:1.23 Sat Apr 1 17:17:11 2006 +++ llvm/lib/Transforms/Utils/ValueMapper.cpp Thu Apr 6 23:41:03 2006 @@ -85,6 +85,15 @@ Constant *MV2 = cast(MapValue(CE->getOperand(1), VM)); Constant *MV3 = cast(MapValue(CE->getOperand(2), VM)); return VMSlot = ConstantExpr::getSelect(MV1, MV2, MV3); + } else if (CE->getOpcode() == Instruction::InsertElement) { + Constant *MV1 = cast(MapValue(CE->getOperand(0), VM)); + Constant *MV2 = cast(MapValue(CE->getOperand(1), VM)); + Constant *MV3 = cast(MapValue(CE->getOperand(2), VM)); + return VMSlot = ConstantExpr::getInsertElement(MV1, MV2, MV3); + } else if (CE->getOpcode() == Instruction::ExtractElement) { + Constant *MV1 = cast(MapValue(CE->getOperand(0), VM)); + Constant *MV2 = cast(MapValue(CE->getOperand(1), VM)); + return VMSlot = ConstantExpr::getExtractElement(MV1, MV2); } else { assert(CE->getNumOperands() == 2 && "Must be binary operator?"); Constant *MV1 = cast(MapValue(CE->getOperand(0), VM)); From lattner at cs.uiuc.edu Thu Apr 6 23:44:59 2006 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Thu, 6 Apr 2006 23:44:59 -0500 Subject: [llvm-commits] CVS: llvm/lib/VMCore/ConstantFolding.cpp Message-ID: <200604070444.XAA02399@zion.cs.uiuc.edu> Changes in directory llvm/lib/VMCore: ConstantFolding.cpp updated: 1.85 -> 1.86 --- Log message: Constant fold extractelement(zero, x) -> zero --- Diffs of the changes: (+3 -0) ConstantFolding.cpp | 3 +++ 1 files changed, 3 insertions(+) Index: llvm/lib/VMCore/ConstantFolding.cpp diff -u llvm/lib/VMCore/ConstantFolding.cpp:1.85 llvm/lib/VMCore/ConstantFolding.cpp:1.86 --- llvm/lib/VMCore/ConstantFolding.cpp:1.85 Sat Apr 1 19:38:28 2006 +++ llvm/lib/VMCore/ConstantFolding.cpp Thu Apr 6 23:44:06 2006 @@ -836,6 +836,9 @@ const Constant *Idx) { if (isa(Val)) // ee(undef, x) -> undef return UndefValue::get(cast(Val->getType())->getElementType()); + if (Val->isNullValue()) // ee(zero, x) -> zero + return Constant::getNullValue( + cast(Val->getType())->getElementType()); if (const ConstantPacked *CVal = dyn_cast(Val)) { if (const ConstantUInt *CIdx = dyn_cast(Idx)) { From lattner at cs.uiuc.edu Fri Apr 7 00:00:55 2006 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Fri, 7 Apr 2006 00:00:55 -0500 Subject: [llvm-commits] CVS: llvm/lib/Bytecode/Reader/Reader.cpp Message-ID: <200604070500.AAA02508@zion.cs.uiuc.edu> Changes in directory llvm/lib/Bytecode/Reader: Reader.cpp updated: 1.190 -> 1.191 --- Log message: We have an assertion that checks that we do not encode null values into the .bc file if they are supposed to be implicit. This is cool, except that it checked *after* constant expr folding: improving constant expr folding could cause the .bc reader to assert out on old .bc files. Move the check so that it checks all simple constants, but no constantexprs. --- Diffs of the changes: (+32 -28) Reader.cpp | 60 ++++++++++++++++++++++++++++++++---------------------------- 1 files changed, 32 insertions(+), 28 deletions(-) Index: llvm/lib/Bytecode/Reader/Reader.cpp diff -u llvm/lib/Bytecode/Reader/Reader.cpp:1.190 llvm/lib/Bytecode/Reader/Reader.cpp:1.191 --- llvm/lib/Bytecode/Reader/Reader.cpp:1.190 Mon Mar 13 07:07:37 2006 +++ llvm/lib/Bytecode/Reader/Reader.cpp Fri Apr 7 00:00:02 2006 @@ -544,10 +544,6 @@ /// or FunctionValues data members of this class. unsigned BytecodeReader::insertValue(Value *Val, unsigned type, ValueTable &ValueTab) { - assert((!isa(Val) || !cast(Val)->isNullValue()) || - !hasImplicitNull(type) && - "Cannot read null values from bytecode!"); - if (ValueTab.size() <= type) ValueTab.resize(type+1); @@ -1506,14 +1502,15 @@ // Ok, not an ConstantExpr. We now know how to read the given type... const Type *Ty = getType(TypeID); + Constant *Result = 0; switch (Ty->getTypeID()) { case Type::BoolTyID: { unsigned Val = read_vbr_uint(); if (Val != 0 && Val != 1) error("Invalid boolean value read."); - Constant* Result = ConstantBool::get(Val == 1); + Result = ConstantBool::get(Val == 1); if (Handler) Handler->handleConstantValue(Result); - return Result; + break; } case Type::UByteTyID: // Unsigned integer types... @@ -1522,43 +1519,42 @@ unsigned Val = read_vbr_uint(); if (!ConstantUInt::isValueValidForType(Ty, Val)) error("Invalid unsigned byte/short/int read."); - Constant* Result = ConstantUInt::get(Ty, Val); + Result = ConstantUInt::get(Ty, Val); if (Handler) Handler->handleConstantValue(Result); - return Result; + break; } - case Type::ULongTyID: { - Constant* Result = ConstantUInt::get(Ty, read_vbr_uint64()); + case Type::ULongTyID: + Result = ConstantUInt::get(Ty, read_vbr_uint64()); if (Handler) Handler->handleConstantValue(Result); - return Result; - } - + break; + case Type::SByteTyID: // Signed integer types... case Type::ShortTyID: - case Type::IntTyID: { - case Type::LongTyID: + case Type::IntTyID: + case Type::LongTyID: { int64_t Val = read_vbr_int64(); if (!ConstantSInt::isValueValidForType(Ty, Val)) error("Invalid signed byte/short/int/long read."); - Constant* Result = ConstantSInt::get(Ty, Val); + Result = ConstantSInt::get(Ty, Val); if (Handler) Handler->handleConstantValue(Result); - return Result; + break; } case Type::FloatTyID: { float Val; read_float(Val); - Constant* Result = ConstantFP::get(Ty, Val); + Result = ConstantFP::get(Ty, Val); if (Handler) Handler->handleConstantValue(Result); - return Result; + break; } case Type::DoubleTyID: { double Val; read_double(Val); - Constant* Result = ConstantFP::get(Ty, Val); + Result = ConstantFP::get(Ty, Val); if (Handler) Handler->handleConstantValue(Result); - return Result; + break; } case Type::ArrayTyID: { @@ -1570,9 +1566,9 @@ while (NumElements--) // Read all of the elements of the constant. Elements.push_back(getConstantValue(TypeSlot, read_vbr_uint())); - Constant* Result = ConstantArray::get(AT, Elements); + Result = ConstantArray::get(AT, Elements); if (Handler) Handler->handleConstantArray(AT, Elements, TypeSlot, Result); - return Result; + break; } case Type::StructTyID: { @@ -1584,9 +1580,9 @@ Elements.push_back(getConstantValue(ST->getElementType(i), read_vbr_uint())); - Constant* Result = ConstantStruct::get(ST, Elements); + Result = ConstantStruct::get(ST, Elements); if (Handler) Handler->handleConstantStruct(ST, Elements, Result); - return Result; + break; } case Type::PackedTyID: { @@ -1598,9 +1594,9 @@ while (NumElements--) // Read all of the elements of the constant. Elements.push_back(getConstantValue(TypeSlot, read_vbr_uint())); - Constant* Result = ConstantPacked::get(PT, Elements); + Result = ConstantPacked::get(PT, Elements); if (Handler) Handler->handleConstantPacked(PT, Elements, TypeSlot, Result); - return Result; + break; } case Type::PointerTyID: { // ConstantPointerRef value (backwards compat). @@ -1624,7 +1620,15 @@ Ty->getDescription()); break; } - return 0; + + // Check that we didn't read a null constant if they are implicit for this + // type plane. Do not do this check for constantexprs, as they may be folded + // to a null value in a way that isn't predicted when a .bc file is initially + // produced. + assert((!isa(Result) || !cast(Result)->isNullValue()) || + !hasImplicitNull(TypeID) && + "Cannot read null values from bytecode!"); + return Result; } /// Resolve references for constants. This function resolves the forward From evan.cheng at apple.com Fri Apr 7 00:36:38 2006 From: evan.cheng at apple.com (Evan Cheng) Date: Fri, 7 Apr 2006 00:36:38 -0500 Subject: [llvm-commits] CVS: llvm/test/Regression/CodeGen/X86/vec_shuffle-2.ll Message-ID: <200604070536.AAA02614@zion.cs.uiuc.edu> Changes in directory llvm/test/Regression/CodeGen/X86: vec_shuffle-2.ll added (r1.1) --- Log message: Added more shuffle tests --- Diffs of the changes: (+46 -0) vec_shuffle-2.ll | 46 ++++++++++++++++++++++++++++++++++++++++++++++ 1 files changed, 46 insertions(+) Index: llvm/test/Regression/CodeGen/X86/vec_shuffle-2.ll diff -c /dev/null llvm/test/Regression/CodeGen/X86/vec_shuffle-2.ll:1.1 *** /dev/null Fri Apr 7 00:35:55 2006 --- llvm/test/Regression/CodeGen/X86/vec_shuffle-2.ll Fri Apr 7 00:35:45 2006 *************** *** 0 **** --- 1,46 ---- + ; RUN: llvm-as < %s | llc -march=x86 -mattr=+sse2 | grep pshufhw | wc -l | grep 1 + ; RUN: llvm-as < %s | llc -march=x86 -mattr=+sse2 | grep pshuflw | wc -l | grep 1 + ; RUN: llvm-as < %s | llc -march=x86 -mattr=+sse2 | grep movhps | wc -l | grep 1 + + void %test_pshuf(<2 x long>* %res, <2 x long>* %A) { + %tmp = load <2 x long>* %A + %tmp = cast <2 x long> %tmp to <8 x short> + %tmp0 = extractelement <8 x short> %tmp, uint 0 + %tmp1 = extractelement <8 x short> %tmp, uint 1 + %tmp2 = extractelement <8 x short> %tmp, uint 2 + %tmp3 = extractelement <8 x short> %tmp, uint 3 + %tmp4 = extractelement <8 x short> %tmp, uint 4 + %tmp5 = extractelement <8 x short> %tmp, uint 5 + %tmp6 = extractelement <8 x short> %tmp, uint 6 + %tmp7 = extractelement <8 x short> %tmp, uint 7 + %tmp8 = insertelement <8 x short> undef, short %tmp2, uint 0 + %tmp9 = insertelement <8 x short> %tmp8, short %tmp1, uint 1 + %tmp10 = insertelement <8 x short> %tmp9, short %tmp0, uint 2 + %tmp11 = insertelement <8 x short> %tmp10, short %tmp3, uint 3 + %tmp12 = insertelement <8 x short> %tmp11, short %tmp6, uint 4 + %tmp13 = insertelement <8 x short> %tmp12, short %tmp5, uint 5 + %tmp14 = insertelement <8 x short> %tmp13, short %tmp4, uint 6 + %tmp15 = insertelement <8 x short> %tmp14, short %tmp7, uint 7 + %tmp15 = cast <8 x short> %tmp15 to <2 x long> + store <2 x long> %tmp15, <2 x long>* %res + ret void + } + + void %testh_movhps(<4 x float>* %r, <2 x int>* %A) { + %tmp = load <4 x float>* %r + %tmp = cast <2 x int>* %A to double* + %tmp = load double* %tmp + %tmp = insertelement <2 x double> undef, double %tmp, uint 0 + %tmp5 = insertelement <2 x double> %tmp, double undef, uint 1 + %tmp6 = cast <2 x double> %tmp5 to <4 x float> + %tmp = extractelement <4 x float> %tmp, uint 0 + %tmp7 = extractelement <4 x float> %tmp, uint 1 + %tmp8 = extractelement <4 x float> %tmp6, uint 0 + %tmp9 = extractelement <4 x float> %tmp6, uint 1 + %tmp10 = insertelement <4 x float> undef, float %tmp, uint 0 + %tmp11 = insertelement <4 x float> %tmp10, float %tmp7, uint 1 + %tmp12 = insertelement <4 x float> %tmp11, float %tmp8, uint 2 + %tmp13 = insertelement <4 x float> %tmp12, float %tmp9, uint 3 + store <4 x float> %tmp13, <4 x float>* %r + ret void + } From evan.cheng at apple.com Fri Apr 7 03:10:22 2006 From: evan.cheng at apple.com (Evan Cheng) Date: Fri, 7 Apr 2006 03:10:22 -0500 Subject: [llvm-commits] CVS: llvm/Makefile.rules Message-ID: <200604070810.DAA13153@zion.cs.uiuc.edu> Changes in directory llvm: Makefile.rules updated: 1.355 -> 1.356 --- Log message: Temporary workaround for a Mac OSX specific issue. --- Diffs of the changes: (+5 -0) Makefile.rules | 5 +++++ 1 files changed, 5 insertions(+) Index: llvm/Makefile.rules diff -u llvm/Makefile.rules:1.355 llvm/Makefile.rules:1.356 --- llvm/Makefile.rules:1.355 Thu Apr 6 01:30:15 2006 +++ llvm/Makefile.rules Fri Apr 7 03:10:09 2006 @@ -367,6 +367,11 @@ DISABLE_AUTO_DEPENDENCIES=1 endif +# Temporary workaround for a Mac OSX specific issue. +ifdef NO_CXA_ATEXIT + CompileCommonOpts += -fno-use-cxa-atexit +endif + LD.Flags += -L$(LibDir) -L$(LLVMLibDir) CPP.BaseFlags += -D_GNU_SOURCE -D__STDC_LIMIT_MACROS # All -I flags should go here, so that they don't confuse llvm-config. From evan.cheng at apple.com Fri Apr 7 03:32:09 2006 From: evan.cheng at apple.com (Evan Cheng) Date: Fri, 7 Apr 2006 03:32:09 -0500 Subject: [llvm-commits] CVS: llvm/Makefile.rules Message-ID: <200604070832.DAA13250@zion.cs.uiuc.edu> Changes in directory llvm: Makefile.rules updated: 1.356 -> 1.357 --- Log message: A saner workaround. I hope. --- Diffs of the changes: (+5 -3) Makefile.rules | 8 +++++--- 1 files changed, 5 insertions(+), 3 deletions(-) Index: llvm/Makefile.rules diff -u llvm/Makefile.rules:1.356 llvm/Makefile.rules:1.357 --- llvm/Makefile.rules:1.356 Fri Apr 7 03:10:09 2006 +++ llvm/Makefile.rules Fri Apr 7 03:31:56 2006 @@ -367,9 +367,11 @@ DISABLE_AUTO_DEPENDENCIES=1 endif -# Temporary workaround for a Mac OSX specific issue. -ifdef NO_CXA_ATEXIT - CompileCommonOpts += -fno-use-cxa-atexit +# Temporary workaround for a Mac OSX / x86 compatibility issue. +ifeq ($(OS),Darwin) +ifeq ($(ARCH),x86) + CXX.Flags += -fno-use-cxa-atexit +endif endif LD.Flags += -L$(LibDir) -L$(LLVMLibDir) From reid at x10sys.com Fri Apr 7 10:55:32 2006 From: reid at x10sys.com (Reid Spencer) Date: Fri, 7 Apr 2006 10:55:32 -0500 Subject: [llvm-commits] CVS: llvm/.cvsignore Message-ID: <200604071555.KAA15101@zion.cs.uiuc.edu> Changes in directory llvm: .cvsignore updated: 1.4 -> 1.5 --- Log message: Ignore stuff built by "make dist". --- Diffs of the changes: (+2 -0) .cvsignore | 2 ++ 1 files changed, 2 insertions(+) Index: llvm/.cvsignore diff -u llvm/.cvsignore:1.4 llvm/.cvsignore:1.5 --- llvm/.cvsignore:1.4 Sat Jun 18 18:01:25 2005 +++ llvm/.cvsignore Fri Apr 7 10:55:18 2006 @@ -5,3 +5,5 @@ cvs.out autom4te.cache configure.out +LLVM-* +_distcheckdir From reid at x10sys.com Fri Apr 7 10:58:30 2006 From: reid at x10sys.com (Reid Spencer) Date: Fri, 7 Apr 2006 10:58:30 -0500 Subject: [llvm-commits] CVS: llvm/Makefile Message-ID: <200604071558.KAA15116@zion.cs.uiuc.edu> Changes in directory llvm: Makefile updated: 1.52 -> 1.53 --- Log message: For PR723: http://llvm.cs.uiuc.edu/PR723 : Print out something at the end of the build that indicates what kind of build has just completed. --- Diffs of the changes: (+10 -0) Makefile | 10 ++++++++++ 1 files changed, 10 insertions(+) Index: llvm/Makefile diff -u llvm/Makefile:1.52 llvm/Makefile:1.53 --- llvm/Makefile:1.52 Thu Apr 6 17:15:50 2006 +++ llvm/Makefile Fri Apr 7 10:58:18 2006 @@ -74,3 +74,13 @@ $(Echo) Regenerating $* $(Verb) cd $(LLVM_OBJ_ROOT) && $(ConfigStatusScript) $* .PRECIOUS: $(FilesToConfigPATH) + +#NOTE: THis needs to remain as the last target definition in this file so +#that it gets executed last. +all:: + $(Echo) '*****' Completed $(BuildMode)$(AssertMode) Build +ifeq ($(BuildMode),Debug) + $(Echo) '*****' Note: Debug build can be 10 times slower than an + $(Echo) '*****' optimized build. Use 'make ENABLE_OPTIMIZED=1' to + $(Echo) '*****' make an optimized build. +endif From reid at x10sys.com Fri Apr 7 10:59:53 2006 From: reid at x10sys.com (Reid Spencer) Date: Fri, 7 Apr 2006 10:59:53 -0500 Subject: [llvm-commits] CVS: llvm/Makefile.config.in Message-ID: <200604071559.KAA15131@zion.cs.uiuc.edu> Changes in directory llvm: Makefile.config.in updated: 1.54 -> 1.55 --- Log message: For PR723: http://llvm.cs.uiuc.edu/PR723 : - Provide for the include of ENABLE_ASSERTIONS flag from the configuration. - Enhance the documentation for ENABLE_OPTIMIZED --- Diffs of the changes: (+8 -2) Makefile.config.in | 10 ++++++++-- 1 files changed, 8 insertions(+), 2 deletions(-) Index: llvm/Makefile.config.in diff -u llvm/Makefile.config.in:1.54 llvm/Makefile.config.in:1.55 --- llvm/Makefile.config.in:1.54 Thu Apr 6 17:00:36 2006 +++ llvm/Makefile.config.in Fri Apr 7 10:59:41 2006 @@ -178,11 +178,17 @@ # These are options that can either be enabled here, or can be enabled on the # make command line (ie, make ENABLE_PROFILING=1): -# When ENABLE_OPTIMIZED is enabled, Release builds of all of the LLVM code are -# turned on, and Debug builds are turned off. +# When ENABLE_OPTIMIZED is enabled, LLVM code is optimized and output is put +# into the "Release" directories. Otherwise, LLVM code is not optimized and +# output is put in the "Debug" directories. #ENABLE_OPTIMIZED = 1 @ENABLE_OPTIMIZED@ +# When ENABLE_ASSERTIONS is enabled, builds of all of the LLVM code will include +# assertion checks, otherwise they are not included. +#ENABLE_ASSERTIONS = 1 + at ENABLE_ASSERTIONS@ + # When DEBUG_RUNTIME is enabled, the runtime libraries will retain debug # symbols. #DEBUG_RUNTIME = 1 From reid at x10sys.com Fri Apr 7 11:02:05 2006 From: reid at x10sys.com (Reid Spencer) Date: Fri, 7 Apr 2006 11:02:05 -0500 Subject: [llvm-commits] CVS: llvm/autoconf/configure.ac Message-ID: <200604071602.LAA15230@zion.cs.uiuc.edu> Changes in directory llvm/autoconf: configure.ac updated: 1.214 -> 1.215 --- Log message: For PR723: http://llvm.cs.uiuc.edu/PR723 : Support detection of a "CVS" directory at configure time to distinguish whether this is a release build or a "from tree" build. This knowledge is used to set the defaults for --enable-optimzied and --enable-assertions options. --- Diffs of the changes: (+28 -2) configure.ac | 30 ++++++++++++++++++++++++++++-- 1 files changed, 28 insertions(+), 2 deletions(-) Index: llvm/autoconf/configure.ac diff -u llvm/autoconf/configure.ac:1.214 llvm/autoconf/configure.ac:1.215 --- llvm/autoconf/configure.ac:1.214 Thu Apr 6 17:00:36 2006 +++ llvm/autoconf/configure.ac Fri Apr 7 11:01:51 2006 @@ -184,6 +184,23 @@ dnl Check for the endianness of the target AC_C_BIGENDIAN(AC_SUBST([ENDIAN],[big]),AC_SUBST([ENDIAN],[little])) +dnl Check to see if there's a "CVS" directory indicating that this build is +dnl being done from a CVS checkout. This sets up several defaults for the +dnl command line switches. When we build with a CVS directory, we get a +dnl debug with assertions turned on. Without, we assume a source release and we +dnl get an optimized build without assertions. See --enable-optimized and +dnl --enable-assertions below +if test -d "CVS" ; then + cvsbuild="yes" + optimize="no" + asserts="yes" + AC_SUBST(CVSBUILD,[[CVSBUILD=1]]) +else + cvsbuild="no" + optimize="yes" + asserts="no" +fi + dnl===-----------------------------------------------------------------------=== dnl=== dnl=== SECTION 3: Command line arguments for the configure script. @@ -191,14 +208,23 @@ dnl===-----------------------------------------------------------------------=== dnl --enable-optimized : check whether they want to do an optimized build: -AC_ARG_ENABLE(optimized, - AS_HELP_STRING([--enable-optimized,Compile with optimizations enabled (default is NO)]),,enableval=no) +AC_ARG_ENABLE(optimized, AS_HELP_STRING( + [--enable-optimized,Compile with optimizations enabled (default is NO)]),,enableval=$optimize) if test ${enableval} = "no" ; then AC_SUBST(ENABLE_OPTIMIZED,[[]]) else AC_SUBST(ENABLE_OPTIMIZED,[[ENABLE_OPTIMIZED=1]]) fi +dnl --enable-assertions : check whether they want to turn on assertions or not: +AC_ARG_ENABLE(assertions,AS_HELP_STRING( + [--enable-assertions,Compile with assertion checks enabled (default is NO)]),, enableval=$asserts) +if test ${enableval} = "no" ; then + AC_SUBST(ENABLE_ASSERTIONS,[[]]) +else + AC_SUBST(ENABLE_ASSERTIONS,[[ENABLE_ASSERTIONS=1]]) +fi + dnl --enable-debug-runtime : should runtime libraries have debug symbols? AC_ARG_ENABLE(debug-runtime, AS_HELP_STRING([--enable-debug-runtime,Build runtime libs with debug symbols (default is NO)]),,enableval=no) From reid at x10sys.com Fri Apr 7 11:02:05 2006 From: reid at x10sys.com (Reid Spencer) Date: Fri, 7 Apr 2006 11:02:05 -0500 Subject: [llvm-commits] CVS: llvm/configure Message-ID: <200604071602.LAA15226@zion.cs.uiuc.edu> Changes in directory llvm: configure updated: 1.216 -> 1.217 --- Log message: For PR723: http://llvm.cs.uiuc.edu/PR723 : Support detection of a "CVS" directory at configure time to distinguish whether this is a release build or a "from tree" build. This knowledge is used to set the defaults for --enable-optimzied and --enable-assertions options. --- Diffs of the changes: (+61 -31) configure | 92 +++++++++++++++++++++++++++++++++++++++++--------------------- 1 files changed, 61 insertions(+), 31 deletions(-) Index: llvm/configure diff -u llvm/configure:1.216 llvm/configure:1.217 --- llvm/configure:1.216 Thu Apr 6 17:00:36 2006 +++ llvm/configure Fri Apr 7 11:01:51 2006 @@ -476,7 +476,7 @@ # include #endif" -ac_subst_vars='SHELL PATH_SEPARATOR PACKAGE_NAME PACKAGE_TARNAME PACKAGE_VERSION PACKAGE_STRING PACKAGE_BUGREPORT exec_prefix prefix program_transform_name bindir sbindir libexecdir datadir sysconfdir sharedstatedir localstatedir libdir includedir oldincludedir infodir mandir build_alias host_alias target_alias DEFS ECHO_C ECHO_N ECHO_T LIBS LLVM_COPYRIGHT subdirs build build_cpu build_vendor build_os host host_cpu host_vendor host_os target target_cpu target_vendor target_os OS LLVM_ON_UNIX LLVM_ON_WIN32 ARCH ENDIAN CC CFLAGS LDFLAGS CPPFLAGS ac_ct_CC EXEEXT OBJEXT ENABLE_OPTIMIZED DEBUG_RUNTIME JIT TARGET_HAS_JIT ENABLE_DOXYGEN ENABLE_THREADS TARGETS_TO_BUILD CPP CXX CXXFLAGS ac_ct_CXX LEX LEXLIB LEX_OUTPUT_ROOT FLEX YACC BISON ifGNUmake LN_S CMP CP DATE FIND GREP MKDIR MV RANLIB ac_ct_RANLIB RM SED TAR GRAPHVIZ GV PERL HAVE_PERL INSTALL_PROGRAM INSTALL_SCRIPT INSTALL_DATA BZIP2 DOT DOXYGEN ETAGS GROFF GZIP POD2HTML POD2MAN RUNTEST TCLSH ZIP EGREP INSTALL_LTDL_TRUE INSTAL! L_LTDL_FALSE CONVENIENCE_LTDL_TRUE CONVENIENCE_LTDL_FALSE LIBADD_DL ECHO AR ac_ct_AR STRIP ac_ct_STRIP CXXCPP F77 FFLAGS ac_ct_F77 LIBTOOL ETAGSFLAGS LLVMGCC LLVMGXX ALLOCA MMAP_FILE LLVMCC1 LLVMCC1PLUS LLVMGCCDIR LLVMGCC_VERSION LLVMGCC_MAJVERS SHLIBEXT LLVM_PREFIX LLVM_BINDIR LLVM_LIBDIR LLVM_DATADIR LLVM_DOCSDIR LLVM_ETCDIR LLVM_INCLUDEDIR LLVM_INFODIR LLVM_MANDIR LLVM_CONFIGTIME LIBOBJS LTLIBOBJS' +ac_subst_vars='SHELL PATH_SEPARATOR PACKAGE_NAME PACKAGE_TARNAME PACKAGE_VERSION PACKAGE_STRING PACKAGE_BUGREPORT exec_prefix prefix program_transform_name bindir sbindir libexecdir datadir sysconfdir sharedstatedir localstatedir libdir includedir oldincludedir infodir mandir build_alias host_alias target_alias DEFS ECHO_C ECHO_N ECHO_T LIBS LLVM_COPYRIGHT subdirs build build_cpu build_vendor build_os host host_cpu host_vendor host_os target target_cpu target_vendor target_os OS LLVM_ON_UNIX LLVM_ON_WIN32 ARCH ENDIAN CC CFLAGS LDFLAGS CPPFLAGS ac_ct_CC EXEEXT OBJEXT CVSBUILD ENABLE_OPTIMIZED ENABLE_ASSERTIONS DEBUG_RUNTIME JIT TARGET_HAS_JIT ENABLE_DOXYGEN ENABLE_THREADS TARGETS_TO_BUILD CPP CXX CXXFLAGS ac_ct_CXX LEX LEXLIB LEX_OUTPUT_ROOT FLEX YACC BISON ifGNUmake LN_S CMP CP DATE FIND GREP MKDIR MV RANLIB ac_ct_RANLIB RM SED TAR GRAPHVIZ GV PERL HAVE_PERL INSTALL_PROGRAM INSTALL_SCRIPT INSTALL_DATA BZIP2 DOT DOXYGEN ETAGS GROFF GZIP POD2HTML POD2MAN RUNTEST TCLSH ZIP EGR! EP INSTALL_LTDL_TRUE INSTALL_LTDL_FALSE CONVENIENCE_LTDL_TRUE CONVENIENCE_LTDL_FALSE LIBADD_DL ECHO AR ac_ct_AR STRIP ac_ct_STRIP CXXCPP F77 FFLAGS ac_ct_F77 LIBTOOL ETAGSFLAGS LLVMGCC LLVMGXX ALLOCA MMAP_FILE LLVMCC1 LLVMCC1PLUS LLVMGCCDIR LLVMGCC_VERSION LLVMGCC_MAJVERS SHLIBEXT LLVM_PREFIX LLVM_BINDIR LLVM_LIBDIR LLVM_DATADIR LLVM_DOCSDIR LLVM_ETCDIR LLVM_INCLUDEDIR LLVM_INFODIR LLVM_MANDIR LLVM_CONFIGTIME LIBOBJS LTLIBOBJS' ac_subst_files='' # Initialize some variables set by options. @@ -1035,6 +1035,7 @@ --disable-FEATURE do not include FEATURE (same as --enable-FEATURE=no) --enable-FEATURE[=ARG] include FEATURE [ARG=yes] --enable-optimized + --enable-assertions --enable-debug-runtime --enable-jit Enable Just In Time Compiling (default is YES) --enable-doxygen Build doxygen documentation (default is NO) @@ -2967,13 +2968,25 @@ esac +if test -d "CVS" ; then + cvsbuild="yes" + optimize="no" + asserts="yes" + CVSBUILD=CVSBUILD=1 + +else + cvsbuild="no" + optimize="yes" + asserts="no" +fi + # Check whether --enable-optimized or --disable-optimized was given. if test "${enable_optimized+set}" = set; then enableval="$enable_optimized" else - enableval=no + enableval=$optimize fi; if test ${enableval} = "no" ; then ENABLE_OPTIMIZED= @@ -2983,6 +2996,21 @@ fi +# Check whether --enable-assertions or --disable-assertions was given. +if test "${enable_assertions+set}" = set; then + enableval="$enable_assertions" + +else + enableval=$asserts +fi; +if test ${enableval} = "no" ; then + ENABLE_ASSERTIONS= + +else + ENABLE_ASSERTIONS=ENABLE_ASSERTIONS=1 + +fi + # Check whether --enable-debug-runtime or --disable-debug-runtime was given. if test "${enable_debug_runtime+set}" = set; then enableval="$enable_debug_runtime" @@ -8439,7 +8467,7 @@ lt_dlunknown=0; lt_dlno_uscore=1; lt_dlneed_uscore=2 lt_status=$lt_dlunknown cat > conftest.$ac_ext < conftest.$ac_ext + echo '#line 10461 "configure"' > conftest.$ac_ext if { (eval echo "$as_me:$LINENO: \"$ac_compile\"") >&5 (eval $ac_compile) 2>&5 ac_status=$? @@ -10915,7 +10943,7 @@ # Provide some information about the compiler. -echo "$as_me:10918:" \ +echo "$as_me:10946:" \ "checking for Fortran 77 compiler version" >&5 ac_compiler=`set X $ac_compile; echo $2` { (eval echo "$as_me:$LINENO: \"$ac_compiler --version &5\"") >&5 @@ -11972,11 +12000,11 @@ -e 's:.*FLAGS}? :&$lt_compiler_flag :; t' \ -e 's: [^ ]*conftest\.: $lt_compiler_flag&:; t' \ -e 's:$: $lt_compiler_flag:'` - (eval echo "\"\$as_me:11975: $lt_compile\"" >&5) + (eval echo "\"\$as_me:12003: $lt_compile\"" >&5) (eval "$lt_compile" 2>conftest.err) ac_status=$? cat conftest.err >&5 - echo "$as_me:11979: \$? = $ac_status" >&5 + echo "$as_me:12007: \$? = $ac_status" >&5 if (exit $ac_status) && test -s "$ac_outfile"; then # The compiler can only warn and ignore the option if not recognized # So say no if there are warnings @@ -12215,11 +12243,11 @@ -e 's:.*FLAGS}? :&$lt_compiler_flag :; t' \ -e 's: [^ ]*conftest\.: $lt_compiler_flag&:; t' \ -e 's:$: $lt_compiler_flag:'` - (eval echo "\"\$as_me:12218: $lt_compile\"" >&5) + (eval echo "\"\$as_me:12246: $lt_compile\"" >&5) (eval "$lt_compile" 2>conftest.err) ac_status=$? cat conftest.err >&5 - echo "$as_me:12222: \$? = $ac_status" >&5 + echo "$as_me:12250: \$? = $ac_status" >&5 if (exit $ac_status) && test -s "$ac_outfile"; then # The compiler can only warn and ignore the option if not recognized # So say no if there are warnings @@ -12275,11 +12303,11 @@ -e 's:.*FLAGS}? :&$lt_compiler_flag :; t' \ -e 's: [^ ]*conftest\.: $lt_compiler_flag&:; t' \ -e 's:$: $lt_compiler_flag:'` - (eval echo "\"\$as_me:12278: $lt_compile\"" >&5) + (eval echo "\"\$as_me:12306: $lt_compile\"" >&5) (eval "$lt_compile" 2>out/conftest.err) ac_status=$? cat out/conftest.err >&5 - echo "$as_me:12282: \$? = $ac_status" >&5 + echo "$as_me:12310: \$? = $ac_status" >&5 if (exit $ac_status) && test -s out/conftest2.$ac_objext then # The compiler can only warn and ignore the option if not recognized @@ -14460,7 +14488,7 @@ lt_dlunknown=0; lt_dlno_uscore=1; lt_dlneed_uscore=2 lt_status=$lt_dlunknown cat > conftest.$ac_ext < conftest.$ac_ext <&5) + (eval echo "\"\$as_me:16782: $lt_compile\"" >&5) (eval "$lt_compile" 2>conftest.err) ac_status=$? cat conftest.err >&5 - echo "$as_me:16758: \$? = $ac_status" >&5 + echo "$as_me:16786: \$? = $ac_status" >&5 if (exit $ac_status) && test -s "$ac_outfile"; then # The compiler can only warn and ignore the option if not recognized # So say no if there are warnings @@ -16811,11 +16839,11 @@ -e 's:.*FLAGS}? :&$lt_compiler_flag :; t' \ -e 's: [^ ]*conftest\.: $lt_compiler_flag&:; t' \ -e 's:$: $lt_compiler_flag:'` - (eval echo "\"\$as_me:16814: $lt_compile\"" >&5) + (eval echo "\"\$as_me:16842: $lt_compile\"" >&5) (eval "$lt_compile" 2>out/conftest.err) ac_status=$? cat out/conftest.err >&5 - echo "$as_me:16818: \$? = $ac_status" >&5 + echo "$as_me:16846: \$? = $ac_status" >&5 if (exit $ac_status) && test -s out/conftest2.$ac_objext then # The compiler can only warn and ignore the option if not recognized @@ -18172,7 +18200,7 @@ lt_dlunknown=0; lt_dlno_uscore=1; lt_dlneed_uscore=2 lt_status=$lt_dlunknown cat > conftest.$ac_ext < conftest.$ac_ext <&5) + (eval echo "\"\$as_me:19138: $lt_compile\"" >&5) (eval "$lt_compile" 2>conftest.err) ac_status=$? cat conftest.err >&5 - echo "$as_me:19114: \$? = $ac_status" >&5 + echo "$as_me:19142: \$? = $ac_status" >&5 if (exit $ac_status) && test -s "$ac_outfile"; then # The compiler can only warn and ignore the option if not recognized # So say no if there are warnings @@ -19167,11 +19195,11 @@ -e 's:.*FLAGS}? :&$lt_compiler_flag :; t' \ -e 's: [^ ]*conftest\.: $lt_compiler_flag&:; t' \ -e 's:$: $lt_compiler_flag:'` - (eval echo "\"\$as_me:19170: $lt_compile\"" >&5) + (eval echo "\"\$as_me:19198: $lt_compile\"" >&5) (eval "$lt_compile" 2>out/conftest.err) ac_status=$? cat out/conftest.err >&5 - echo "$as_me:19174: \$? = $ac_status" >&5 + echo "$as_me:19202: \$? = $ac_status" >&5 if (exit $ac_status) && test -s out/conftest2.$ac_objext then # The compiler can only warn and ignore the option if not recognized @@ -21206,11 +21234,11 @@ -e 's:.*FLAGS}? :&$lt_compiler_flag :; t' \ -e 's: [^ ]*conftest\.: $lt_compiler_flag&:; t' \ -e 's:$: $lt_compiler_flag:'` - (eval echo "\"\$as_me:21209: $lt_compile\"" >&5) + (eval echo "\"\$as_me:21237: $lt_compile\"" >&5) (eval "$lt_compile" 2>conftest.err) ac_status=$? cat conftest.err >&5 - echo "$as_me:21213: \$? = $ac_status" >&5 + echo "$as_me:21241: \$? = $ac_status" >&5 if (exit $ac_status) && test -s "$ac_outfile"; then # The compiler can only warn and ignore the option if not recognized # So say no if there are warnings @@ -21449,11 +21477,11 @@ -e 's:.*FLAGS}? :&$lt_compiler_flag :; t' \ -e 's: [^ ]*conftest\.: $lt_compiler_flag&:; t' \ -e 's:$: $lt_compiler_flag:'` - (eval echo "\"\$as_me:21452: $lt_compile\"" >&5) + (eval echo "\"\$as_me:21480: $lt_compile\"" >&5) (eval "$lt_compile" 2>conftest.err) ac_status=$? cat conftest.err >&5 - echo "$as_me:21456: \$? = $ac_status" >&5 + echo "$as_me:21484: \$? = $ac_status" >&5 if (exit $ac_status) && test -s "$ac_outfile"; then # The compiler can only warn and ignore the option if not recognized # So say no if there are warnings @@ -21509,11 +21537,11 @@ -e 's:.*FLAGS}? :&$lt_compiler_flag :; t' \ -e 's: [^ ]*conftest\.: $lt_compiler_flag&:; t' \ -e 's:$: $lt_compiler_flag:'` - (eval echo "\"\$as_me:21512: $lt_compile\"" >&5) + (eval echo "\"\$as_me:21540: $lt_compile\"" >&5) (eval "$lt_compile" 2>out/conftest.err) ac_status=$? cat out/conftest.err >&5 - echo "$as_me:21516: \$? = $ac_status" >&5 + echo "$as_me:21544: \$? = $ac_status" >&5 if (exit $ac_status) && test -s out/conftest2.$ac_objext then # The compiler can only warn and ignore the option if not recognized @@ -23694,7 +23722,7 @@ lt_dlunknown=0; lt_dlno_uscore=1; lt_dlneed_uscore=2 lt_status=$lt_dlunknown cat > conftest.$ac_ext < conftest.$ac_ext < Changes in directory llvm: Makefile.rules updated: 1.357 -> 1.358 --- Log message: For PR723: http://llvm.cs.uiuc.edu/PR723 : 1. Don't force debug builds to have assertion checking turned on always. Let the default (on) be taken, or overridden by the command line 2. Create two new BuildModes based on assertion checking: Release+Assert and Debug-Assert. 3. Ensure that when building a distribution we get a release build with assertions enabled, regardless of the tree's configuration. 4. (unrelated) Fix library name generation for llvm-config usage. --- Diffs of the changes: (+13 -10) Makefile.rules | 23 +++++++++++++---------- 1 files changed, 13 insertions(+), 10 deletions(-) Index: llvm/Makefile.rules diff -u llvm/Makefile.rules:1.357 llvm/Makefile.rules:1.358 --- llvm/Makefile.rules:1.357 Fri Apr 7 03:31:56 2006 +++ llvm/Makefile.rules Fri Apr 7 11:06:18 2006 @@ -219,17 +219,21 @@ C.Flags := -g LD.Flags := -g KEEP_SYMBOLS := 1 - # Assertions default to ON for debug builds. - ENABLE_ASSERTIONS := 1 endif endif -# If this is a debug build or if ENABLE_ASSERTIONS=1 is specified on the make -# command line, enable assertions. +# If ENABLE_ASSERTIONS=1 is specified (make command line or configured), +# then enable assertions by defining the appropriate preprocessor symbols. ifdef ENABLE_ASSERTIONS + ifdef ENABLE_OPTIMIZED + BuildMode := $(BuildMode)+Asserts + endif CXX.Flags += -D_DEBUG C.Flags += -D_DEBUG else + ifndef ENABLE_OPTIMIZED + BuildMode := $(BuildMode)-Asserts + endif CXX.Flags += -DNDEBUG C.Flags += -DNDEBUG endif @@ -580,10 +584,9 @@ #--------------------------------------------------------- ifeq ($(firstword $(LLVMLIBS)),config) LLVM_CONFIG := $(LLVM_SRC_ROOT)/utils/llvm-config/llvm-config -LLVMLIBS := $(shell $(LLVM_CONFIG) $(wordlist 2,9999,$(LLVMLIBS))) -LLVMLIBS := $(patsubst $(PROJ_libdir)/%,%,$(LLVMLIBS)) +LLVMLIBS := $(shell $(LLVM_CONFIG) --libnames $(wordlist 2,9999,$(LLVMLIBS))) +LLVMLIBS := $(patsubst lib%.a,%.a,$(LLVMLIBS)) LLVMLIBS := $(patsubst %.o,%,$(LLVMLIBS)) -LLVMLIBS := $(patsubst -l%,%.a,$(LLVMLIBS)) endif ifeq ($(LLVMLIBS),JIT) @@ -1529,7 +1532,7 @@ $(EchoCmd) Removing old $(DistDir) ; \ $(RM) -rf $(DistDir); \ $(EchoCmd) Making 'all' to verify build ; \ - $(MAKE) all ; \ + $(MAKE) ENABLE_OPTIMIZED=1 ENABLE_ASSERTIONS=1 all ; \ fi $(Echo) Building Distribution Directory $(DistDir) $(Verb) $(MKDIR) $(DistDir) @@ -1590,8 +1593,8 @@ if test "$$subdir" \!= "." ; then \ new_distdir="$(DistDir)/$$subdir" ; \ test -d "$$new_distdir" || $(MKDIR) "$$new_distdir" || exit 1; \ - ( cd $$subdir && $(MAKE) DistDir="$$new_distdir" distdir ) || \ - exit 1; \ + ( cd $$subdir && $(MAKE) ENABLE_OPTIMIZED=1 ENABLE_ASSERTIONS=1 \ + DistDir="$$new_distdir" distdir ) || exit 1; \ fi; \ done $(Verb) if test "$(DistDir)" = "$(TopDistDir)" ; then \ From reid at x10sys.com Fri Apr 7 11:07:50 2006 From: reid at x10sys.com (Reid Spencer) Date: Fri, 7 Apr 2006 11:07:50 -0500 Subject: [llvm-commits] CVS: llvm/llvm.spec Message-ID: <200604071607.LAA15266@zion.cs.uiuc.edu> Changes in directory llvm: llvm.spec updated: 1.4 -> 1.5 --- Log message: For PR723: http://llvm.cs.uiuc.edu/PR723 : Configure with the --enable-optimized and --enable-assertions option to ensure that binary RPM packages are built with the options required by the feature request. --- Diffs of the changes: (+5 -1) llvm.spec | 5 +++++ 1 files changed, 5 insertions(+) Index: llvm/llvm.spec diff -u llvm/llvm.spec:1.4 llvm/llvm.spec:1.5 --- llvm/llvm.spec:1.4 Wed May 18 15:23:20 2005 +++ llvm/llvm.spec Fri Apr 7 11:07:37 2006 @@ -29,7 +29,9 @@ --bindir=%{_bindir} \ --datadir=%{_datadir} \ --includedir=%{_includedir} \ ---libdir=%{_libdir} +--libdir=%{_libdir} \ +--enable-optimized \ +--enable-assertions \ make %install @@ -53,6 +55,8 @@ %{_includedir}/llvm %changelog +* Fri Apr 07 2006 Reid Spencer +- Make the build be optimized+assertions * Fri May 13 2005 Reid Spencer - Minor adjustments for the 1.5 release * Mon Feb 09 2003 Brian R. Gaeke From lattner at cs.uiuc.edu Fri Apr 7 11:22:12 2006 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Fri, 7 Apr 2006 11:22:12 -0500 Subject: [llvm-commits] CVS: llvm/Makefile Message-ID: <200604071622.LAA15385@zion.cs.uiuc.edu> Changes in directory llvm: Makefile updated: 1.53 -> 1.54 --- Log message: THis -> This --- Diffs of the changes: (+3 -2) Makefile | 5 +++-- 1 files changed, 3 insertions(+), 2 deletions(-) Index: llvm/Makefile diff -u llvm/Makefile:1.53 llvm/Makefile:1.54 --- llvm/Makefile:1.53 Fri Apr 7 10:58:18 2006 +++ llvm/Makefile Fri Apr 7 11:21:59 2006 @@ -75,8 +75,8 @@ $(Verb) cd $(LLVM_OBJ_ROOT) && $(ConfigStatusScript) $* .PRECIOUS: $(FilesToConfigPATH) -#NOTE: THis needs to remain as the last target definition in this file so -#that it gets executed last. +# NOTE: This needs to remain as the last target definition in this file so +# that it gets executed last. all:: $(Echo) '*****' Completed $(BuildMode)$(AssertMode) Build ifeq ($(BuildMode),Debug) @@ -84,3 +84,4 @@ $(Echo) '*****' optimized build. Use 'make ENABLE_OPTIMIZED=1' to $(Echo) '*****' make an optimized build. endif + From jlaskey at apple.com Fri Apr 7 11:35:03 2006 From: jlaskey at apple.com (Jim Laskey) Date: Fri, 7 Apr 2006 11:35:03 -0500 Subject: [llvm-commits] CVS: llvm/include/llvm/CodeGen/DwarfWriter.h MachineDebugInfo.h MachineFrameInfo.h MachineLocation.h Message-ID: <200604071635.LAA15485@zion.cs.uiuc.edu> Changes in directory llvm/include/llvm/CodeGen: DwarfWriter.h updated: 1.32 -> 1.33 MachineDebugInfo.h updated: 1.32 -> 1.33 MachineFrameInfo.h updated: 1.16 -> 1.17 MachineLocation.h updated: 1.1 -> 1.2 --- Log message: Foundation for call frame information. --- Diffs of the changes: (+100 -13) DwarfWriter.h | 31 +++++++++++++++++++++++++------ MachineDebugInfo.h | 24 +++++++++++++++++++----- MachineFrameInfo.h | 18 ++++++++++++++++++ MachineLocation.h | 40 ++++++++++++++++++++++++++++++++++++++-- 4 files changed, 100 insertions(+), 13 deletions(-) Index: llvm/include/llvm/CodeGen/DwarfWriter.h diff -u llvm/include/llvm/CodeGen/DwarfWriter.h:1.32 llvm/include/llvm/CodeGen/DwarfWriter.h:1.33 --- llvm/include/llvm/CodeGen/DwarfWriter.h:1.32 Tue Mar 28 08:58:32 2006 +++ llvm/include/llvm/CodeGen/DwarfWriter.h Fri Apr 7 11:34:45 2006 @@ -41,10 +41,13 @@ class DIEAbbrev; class GlobalVariableDesc; class MachineDebugInfo; -class MachineLocation; class MachineFunction; +class MachineLocation; +class MachineMove; class Module; +class MRegisterInfo; class SubprogramDesc; +class TargetData; class Type; class TypeDesc; @@ -81,6 +84,12 @@ /// AsmPrinter *Asm; + /// TD - Target data. + const TargetData &TD; + + /// RI - Register Information. + const MRegisterInfo *RI; + /// M - Current module. /// Module *M; @@ -324,7 +333,8 @@ /// AddAddress - Add an address attribute to a die based on the location /// provided. - void AddAddress(DIE *Die, unsigned Attribute, MachineLocation &Location); + void AddAddress(DIE *Die, unsigned Attribute, + const MachineLocation &Location); /// NewType - Create a new type DIE. /// @@ -375,6 +385,11 @@ /// void SizeAndOffsets(); + /// EmitFrameMoves - Emit frame instructions to describe the layout of the + /// frame. + void EmitFrameMoves(const char *BaseLabel, unsigned BaseLabelID, + std::vector &Moves); + /// EmitDebugInfo - Emit the debug info section. /// void EmitDebugInfo() const; @@ -387,10 +402,14 @@ /// void EmitDebugLines() const; - /// EmitDebugFrame - Emit info into a debug frame section. + /// EmitInitialDebugFrame - Emit common frame info into a debug frame section. /// - void EmitDebugFrame(); - + void EmitInitialDebugFrame(); + + /// EmitFunctionDebugFrame - Emit per function frame info into a debug frame + /// section. + void EmitFunctionDebugFrame(); + /// EmitDebugPubNames - Emit info into a debug pubnames section. /// void EmitDebugPubNames(); @@ -439,7 +458,7 @@ /// SetDebugInfo - Set DebugInfo when it's known that pass manager has /// created it. Set by the target AsmPrinter. - void SetDebugInfo(MachineDebugInfo *DI) { DebugInfo = DI; } + void SetDebugInfo(MachineDebugInfo *DI); //===--------------------------------------------------------------------===// // Main entry points. Index: llvm/include/llvm/CodeGen/MachineDebugInfo.h diff -u llvm/include/llvm/CodeGen/MachineDebugInfo.h:1.32 llvm/include/llvm/CodeGen/MachineDebugInfo.h:1.33 --- llvm/include/llvm/CodeGen/MachineDebugInfo.h:1.32 Sun Mar 26 16:45:20 2006 +++ llvm/include/llvm/CodeGen/MachineDebugInfo.h Fri Apr 7 11:34:45 2006 @@ -47,6 +47,8 @@ class Constant; class DebugInfoDesc; class GlobalVariable; +class MachineFunction; +class MachineMove; class Module; class PointerType; class StructType; @@ -574,7 +576,7 @@ void setName(const std::string &N) { Name = N; } void setFile(CompileUnitDesc *U) { File = U; } void setLine(unsigned L) { Line = L; } - void setTypeDesc(TypeDesc *T) { TyDesc = T; } + void setType(TypeDesc *T) { TyDesc = T; } void setIsStatic(bool IS) { IsStatic = IS; } void setIsDefinition(bool ID) { IsDefinition = ID; } @@ -940,6 +942,10 @@ // RootScope - Top level scope for the current function. // DebugScope *RootScope; + + // FrameMoves - List of moves done by a function's prolog. Used to construct + // frame maps by debug consumers. + std::vector FrameMoves; public: MachineDebugInfo(); @@ -953,6 +959,14 @@ /// bool doFinalization(); + /// BeginFunction - Begin gathering function debug information. + /// + void BeginFunction(MachineFunction *MF); + + /// EndFunction - Discard function debug information. + /// + void EndFunction(); + /// getDescFor - Convert a Value to a debug information descriptor. /// // FIXME - use new Value type when available. @@ -1060,10 +1074,10 @@ /// getOrCreateScope - Returns the scope associated with the given descriptor. /// DebugScope *getOrCreateScope(DebugInfoDesc *ScopeDesc); - - /// ClearScopes - Delete the scope and variable info after a function is - /// completed. - void ClearScopes(); + + /// getFrameMoves - Returns a reference to a list of moves done in the current + /// function's prologue. Used to construct frame maps for debug comsumers. + std::vector &getFrameMoves() { return FrameMoves; } }; // End class MachineDebugInfo Index: llvm/include/llvm/CodeGen/MachineFrameInfo.h diff -u llvm/include/llvm/CodeGen/MachineFrameInfo.h:1.16 llvm/include/llvm/CodeGen/MachineFrameInfo.h:1.17 --- llvm/include/llvm/CodeGen/MachineFrameInfo.h:1.16 Tue Apr 4 12:39:56 2006 +++ llvm/include/llvm/CodeGen/MachineFrameInfo.h Fri Apr 7 11:34:45 2006 @@ -44,6 +44,7 @@ class TargetData; class TargetRegisterClass; class Type; +class MachineDebugInfo; class MachineFunction; class MachineFrameInfo { @@ -106,12 +107,21 @@ /// insertion. /// unsigned MaxCallFrameSize; + + /// DebugInfo - This field is set (via setMachineDebugInfo) by a debug info + /// consumer (ex. DwarfWriter) to indicate that frame layout information + /// should be acquired. Typically, it's the responsibility of the target's + /// MRegisterInfo prologue/epilogue emitting code to inform MachineDebugInfo + /// of frame layouts. + MachineDebugInfo *DebugInfo; + public: MachineFrameInfo() { NumFixedObjects = StackSize = MaxAlignment = 0; HasVarSizedObjects = false; HasCalls = false; MaxCallFrameSize = 0; + DebugInfo = 0; } /// hasStackObjects - Return true if there are any stack objects in this @@ -230,6 +240,14 @@ return Objects.size()-NumFixedObjects-1; } + /// getMachineDebugInfo - Used by a prologue/epilogue emitter (MRegisterInfo) + /// to provide frame layout information. + MachineDebugInfo *getMachineDebugInfo() const { return DebugInfo; } + + /// setMachineDebugInfo - Used by a debug consumer (DwarfWriter) to indicate + /// that frame layout information should be gathered. + void setMachineDebugInfo(MachineDebugInfo *DI) { DebugInfo = DI; } + /// print - Used by the MachineFunction printer to print information about /// stack objects. Implemented in MachineFunction.cpp /// Index: llvm/include/llvm/CodeGen/MachineLocation.h diff -u llvm/include/llvm/CodeGen/MachineLocation.h:1.1 llvm/include/llvm/CodeGen/MachineLocation.h:1.2 --- llvm/include/llvm/CodeGen/MachineLocation.h:1.1 Thu Mar 23 12:01:12 2006 +++ llvm/include/llvm/CodeGen/MachineLocation.h Fri Apr 7 11:34:45 2006 @@ -8,7 +8,13 @@ //===----------------------------------------------------------------------===// // The MachineLocation class is used to represent a simple location in a machine // frame. Locations will be one of two forms; a register or an address formed -// from a base address plus an offset. +// from a base address plus an offset. Register indirection can be specified by +// using an offset of zero. +// +// The MachineMove class is used to represent abstract move operations in the +// prolog/epilog of a compiled function. A collection of these objects can be +// used by a debug consumer to track the location of values when unwinding stack +// frames. //===----------------------------------------------------------------------===// @@ -24,6 +30,11 @@ int Offset; // Displacement if not register. public: + enum { + // The target register number for an abstract frame pointer. The value is + // an arbitrary value greater than MRegisterInfo::FirstVirtualRegister. + VirtualFP = ~0U + }; MachineLocation() : IsRegister(false) , Register(0) @@ -37,7 +48,7 @@ MachineLocation(unsigned R, int O) : IsRegister(false) , Register(R) - , Offset(0) + , Offset(O) {} // Accessors @@ -57,6 +68,31 @@ Register = R; Offset = O; } + +#ifndef NDEBUG + void dump(); +#endif +}; + +class MachineMove { +private: + unsigned LabelID; // Label ID number for post-instruction + // address when result of move takes + // effect. + const MachineLocation Destination; // Move to location. + const MachineLocation Source; // Move from location. + +public: + MachineMove(unsigned ID, MachineLocation &D, MachineLocation &S) + : LabelID(ID) + , Destination(D) + , Source(S) + {} + + // Accessors + unsigned getLabelID() const { return LabelID; } + const MachineLocation &getDestination() const { return Destination; } + const MachineLocation &getSource() const { return Source; } }; } // End llvm namespace From jlaskey at apple.com Fri Apr 7 11:35:04 2006 From: jlaskey at apple.com (Jim Laskey) Date: Fri, 7 Apr 2006 11:35:04 -0500 Subject: [llvm-commits] CVS: llvm/lib/Target/IA64/IA64RegisterInfo.cpp IA64RegisterInfo.h Message-ID: <200604071635.LAA15491@zion.cs.uiuc.edu> Changes in directory llvm/lib/Target/IA64: IA64RegisterInfo.cpp updated: 1.16 -> 1.17 IA64RegisterInfo.h updated: 1.6 -> 1.7 --- Log message: Foundation for call frame information. --- Diffs of the changes: (+7 -1) IA64RegisterInfo.cpp | 7 ++++++- IA64RegisterInfo.h | 1 + 2 files changed, 7 insertions(+), 1 deletion(-) Index: llvm/lib/Target/IA64/IA64RegisterInfo.cpp diff -u llvm/lib/Target/IA64/IA64RegisterInfo.cpp:1.16 llvm/lib/Target/IA64/IA64RegisterInfo.cpp:1.17 --- llvm/lib/Target/IA64/IA64RegisterInfo.cpp:1.16 Tue Mar 28 07:48:33 2006 +++ llvm/lib/Target/IA64/IA64RegisterInfo.cpp Fri Apr 7 11:34:45 2006 @@ -329,8 +329,13 @@ } +unsigned IA64RegisterInfo::getRARegister() const { + assert(0 && "What is the return address register"); + return 0; +} + unsigned IA64RegisterInfo::getFrameRegister(MachineFunction &MF) const { - return getDwarfRegNum(hasFP(MF) ? IA64::r5 : IA64::r12); + return hasFP(MF) ? IA64::r5 : IA64::r12; } #include "IA64GenRegisterInfo.inc" Index: llvm/lib/Target/IA64/IA64RegisterInfo.h diff -u llvm/lib/Target/IA64/IA64RegisterInfo.h:1.6 llvm/lib/Target/IA64/IA64RegisterInfo.h:1.7 --- llvm/lib/Target/IA64/IA64RegisterInfo.h:1.6 Tue Mar 28 07:48:33 2006 +++ llvm/lib/Target/IA64/IA64RegisterInfo.h Fri Apr 7 11:34:45 2006 @@ -50,6 +50,7 @@ void emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const; // Debug information queries. + unsigned getRARegister() const; unsigned getFrameRegister(MachineFunction &MF) const; }; From jlaskey at apple.com Fri Apr 7 11:35:05 2006 From: jlaskey at apple.com (Jim Laskey) Date: Fri, 7 Apr 2006 11:35:05 -0500 Subject: [llvm-commits] CVS: llvm/lib/Target/MRegisterInfo.cpp Message-ID: <200604071635.LAA15509@zion.cs.uiuc.edu> Changes in directory llvm/lib/Target: MRegisterInfo.cpp updated: 1.13 -> 1.14 --- Log message: Foundation for call frame information. --- Diffs of the changes: (+15 -0) MRegisterInfo.cpp | 15 +++++++++++++++ 1 files changed, 15 insertions(+) Index: llvm/lib/Target/MRegisterInfo.cpp diff -u llvm/lib/Target/MRegisterInfo.cpp:1.13 llvm/lib/Target/MRegisterInfo.cpp:1.14 --- llvm/lib/Target/MRegisterInfo.cpp:1.13 Tue Mar 28 07:48:33 2006 +++ llvm/lib/Target/MRegisterInfo.cpp Fri Apr 7 11:34:45 2006 @@ -44,6 +44,13 @@ return Allocatable; } +/// getStackDirection - This method should return the factor by which stacks +/// grow. The tyical value is -4 which is the grows negatively in 4 byte +/// increments. +int MRegisterInfo::getStackDirection() const { + return -sizeof(int32_t); +} + /// getLocation - This method should return the actual location of a frame /// variable given the frame index. The location is returned in ML. /// Subclasses should override this method for special handling of frame @@ -54,3 +61,11 @@ ML.set(getFrameRegister(MF), MFI->getObjectOffset(Index) + MFI->getStackSize()); } + +/// getInitialFrameState - Returns a list of machine moves that are assumed +/// on entry to a function. +void +MRegisterInfo::getInitialFrameState(std::vector &Moves) const { + // Default is to do nothing. +} + From jlaskey at apple.com Fri Apr 7 11:35:06 2006 From: jlaskey at apple.com (Jim Laskey) Date: Fri, 7 Apr 2006 11:35:06 -0500 Subject: [llvm-commits] CVS: llvm/lib/Target/Alpha/AlphaRegisterInfo.cpp AlphaRegisterInfo.h Message-ID: <200604071635.LAA15517@zion.cs.uiuc.edu> Changes in directory llvm/lib/Target/Alpha: AlphaRegisterInfo.cpp updated: 1.39 -> 1.40 AlphaRegisterInfo.h updated: 1.11 -> 1.12 --- Log message: Foundation for call frame information. --- Diffs of the changes: (+8 -2) AlphaRegisterInfo.cpp | 7 ++++++- AlphaRegisterInfo.h | 3 ++- 2 files changed, 8 insertions(+), 2 deletions(-) Index: llvm/lib/Target/Alpha/AlphaRegisterInfo.cpp diff -u llvm/lib/Target/Alpha/AlphaRegisterInfo.cpp:1.39 llvm/lib/Target/Alpha/AlphaRegisterInfo.cpp:1.40 --- llvm/lib/Target/Alpha/AlphaRegisterInfo.cpp:1.39 Tue Mar 28 07:48:33 2006 +++ llvm/lib/Target/Alpha/AlphaRegisterInfo.cpp Fri Apr 7 11:34:45 2006 @@ -354,8 +354,13 @@ } } +unsigned AlphaRegisterInfo::getRARegister() const { + assert(0 && "What is the return address register"); + return 0; +} + unsigned AlphaRegisterInfo::getFrameRegister(MachineFunction &MF) const { - return getDwarfRegNum(hasFP(MF) ? Alpha::R15 : Alpha::R30); + return hasFP(MF) ? Alpha::R15 : Alpha::R30; } #include "AlphaGenRegisterInfo.inc" Index: llvm/lib/Target/Alpha/AlphaRegisterInfo.h diff -u llvm/lib/Target/Alpha/AlphaRegisterInfo.h:1.11 llvm/lib/Target/Alpha/AlphaRegisterInfo.h:1.12 --- llvm/lib/Target/Alpha/AlphaRegisterInfo.h:1.11 Tue Mar 28 07:48:33 2006 +++ llvm/lib/Target/Alpha/AlphaRegisterInfo.h Fri Apr 7 11:34:45 2006 @@ -53,7 +53,8 @@ void emitPrologue(MachineFunction &MF) const; void emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const; - // Debug information queries. + // Debug information queries. + unsigned getRARegister() const; unsigned getFrameRegister(MachineFunction &MF) const; static std::string getPrettyName(unsigned reg); From jlaskey at apple.com Fri Apr 7 11:35:05 2006 From: jlaskey at apple.com (Jim Laskey) Date: Fri, 7 Apr 2006 11:35:05 -0500 Subject: [llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp PPCRegisterInfo.h Message-ID: <200604071635.LAA15505@zion.cs.uiuc.edu> Changes in directory llvm/lib/Target/PowerPC: PPCRegisterInfo.cpp updated: 1.53 -> 1.54 PPCRegisterInfo.h updated: 1.12 -> 1.13 --- Log message: Foundation for call frame information. --- Diffs of the changes: (+31 -2) PPCRegisterInfo.cpp | 31 +++++++++++++++++++++++++++++-- PPCRegisterInfo.h | 2 ++ 2 files changed, 31 insertions(+), 2 deletions(-) Index: llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp diff -u llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp:1.53 llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp:1.54 --- llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp:1.53 Mon Apr 3 17:03:29 2006 +++ llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp Fri Apr 7 11:34:45 2006 @@ -19,9 +19,11 @@ #include "llvm/Type.h" #include "llvm/CodeGen/ValueTypes.h" #include "llvm/CodeGen/MachineInstrBuilder.h" +#include "llvm/CodeGen/MachineDebugInfo.h" #include "llvm/CodeGen/MachineFunction.h" #include "llvm/CodeGen/MachineFrameInfo.h" #include "llvm/CodeGen/MachineLocation.h" +#include "llvm/CodeGen/SelectionDAGNodes.h" #include "llvm/Target/TargetFrameInfo.h" #include "llvm/Target/TargetMachine.h" #include "llvm/Target/TargetOptions.h" @@ -339,6 +341,7 @@ MachineBasicBlock &MBB = MF.front(); // Prolog goes in entry BB MachineBasicBlock::iterator MBBI = MBB.begin(); MachineFrameInfo *MFI = MF.getFrameInfo(); + MachineDebugInfo *DebugInfo = MFI->getMachineDebugInfo(); // Do we have a frame pointer for this function? bool HasFP = hasFP(MF); @@ -390,13 +393,13 @@ // Update frame info to pretend that this is part of the stack... MFI->setStackSize(NumBytes); + int NegNumbytes = -NumBytes; // Adjust stack pointer: r1 -= numbytes. if (NumBytes <= 32768) { BuildMI(MBB, MBBI, PPC::STWU, 3) .addReg(PPC::R1).addSImm(-NumBytes).addReg(PPC::R1); } else { - int NegNumbytes = -NumBytes; BuildMI(MBB, MBBI, PPC::LIS, 1, PPC::R0).addSImm(NegNumbytes >> 16); BuildMI(MBB, MBBI, PPC::ORI, 2, PPC::R0) .addReg(PPC::R0).addImm(NegNumbytes & 0xFFFF); @@ -404,6 +407,18 @@ .addReg(PPC::R1).addReg(PPC::R1).addReg(PPC::R0); } + if (DebugInfo) { + std::vector &Moves = DebugInfo->getFrameMoves(); + unsigned LabelID = DebugInfo->NextLabelID(); + + // Show update of SP. + MachineLocation Dst(MachineLocation::VirtualFP); + MachineLocation Src(MachineLocation::VirtualFP, NegNumbytes); + Moves.push_back(new MachineMove(LabelID, Dst, Src)); + + BuildMI(MBB, MBBI, PPC::DWARF_LABEL, 1).addSImm(LabelID); + } + // If there is a preferred stack alignment, align R1 now // FIXME: If this ever matters, this could be made more efficient by folding // this into the code above, so that we don't issue two store+update @@ -458,8 +473,20 @@ } } +unsigned PPCRegisterInfo::getRARegister() const { + return PPC::LR; +} + unsigned PPCRegisterInfo::getFrameRegister(MachineFunction &MF) const { - return getDwarfRegNum(hasFP(MF) ? PPC::R31 : PPC::R1); + return hasFP(MF) ? PPC::R31 : PPC::R1; +} + +void PPCRegisterInfo::getInitialFrameState(std::vector &Moves) + const { + // Initial state is the frame pointer is R1. + MachineLocation Dst(MachineLocation::VirtualFP); + MachineLocation Src(PPC::R1, 0); + Moves.push_back(new MachineMove(0, Dst, Src)); } #include "PPCGenRegisterInfo.inc" Index: llvm/lib/Target/PowerPC/PPCRegisterInfo.h diff -u llvm/lib/Target/PowerPC/PPCRegisterInfo.h:1.12 llvm/lib/Target/PowerPC/PPCRegisterInfo.h:1.13 --- llvm/lib/Target/PowerPC/PPCRegisterInfo.h:1.12 Tue Mar 28 07:48:33 2006 +++ llvm/lib/Target/PowerPC/PPCRegisterInfo.h Fri Apr 7 11:34:45 2006 @@ -57,7 +57,9 @@ void emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const; // Debug information queries. + unsigned getRARegister() const; unsigned getFrameRegister(MachineFunction &MF) const; + void getInitialFrameState(std::vector &Moves) const; }; } // end namespace llvm From jlaskey at apple.com Fri Apr 7 11:35:06 2006 From: jlaskey at apple.com (Jim Laskey) Date: Fri, 7 Apr 2006 11:35:06 -0500 Subject: [llvm-commits] CVS: llvm/lib/Target/X86/X86RegisterInfo.cpp X86RegisterInfo.h Message-ID: <200604071635.LAA15531@zion.cs.uiuc.edu> Changes in directory llvm/lib/Target/X86: X86RegisterInfo.cpp updated: 1.134 -> 1.135 X86RegisterInfo.h updated: 1.36 -> 1.37 --- Log message: Foundation for call frame information. --- Diffs of the changes: (+6 -1) X86RegisterInfo.cpp | 6 +++++- X86RegisterInfo.h | 1 + 2 files changed, 6 insertions(+), 1 deletion(-) Index: llvm/lib/Target/X86/X86RegisterInfo.cpp diff -u llvm/lib/Target/X86/X86RegisterInfo.cpp:1.134 llvm/lib/Target/X86/X86RegisterInfo.cpp:1.135 --- llvm/lib/Target/X86/X86RegisterInfo.cpp:1.134 Tue Apr 4 14:12:30 2006 +++ llvm/lib/Target/X86/X86RegisterInfo.cpp Fri Apr 7 11:34:46 2006 @@ -686,8 +686,12 @@ } } +unsigned X86RegisterInfo::getRARegister() const { + return X86::ST0; // use a non-register register +} + unsigned X86RegisterInfo::getFrameRegister(MachineFunction &MF) const { - return getDwarfRegNum(hasFP(MF) ? X86::EBP : X86::ESP); + return hasFP(MF) ? X86::EBP : X86::ESP; } #include "X86GenRegisterInfo.inc" Index: llvm/lib/Target/X86/X86RegisterInfo.h diff -u llvm/lib/Target/X86/X86RegisterInfo.h:1.36 llvm/lib/Target/X86/X86RegisterInfo.h:1.37 --- llvm/lib/Target/X86/X86RegisterInfo.h:1.36 Tue Mar 28 07:48:33 2006 +++ llvm/lib/Target/X86/X86RegisterInfo.h Fri Apr 7 11:34:46 2006 @@ -64,6 +64,7 @@ void emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const; // Debug information queries. + unsigned getRARegister() const; unsigned getFrameRegister(MachineFunction &MF) const; }; From jlaskey at apple.com Fri Apr 7 11:35:06 2006 From: jlaskey at apple.com (Jim Laskey) Date: Fri, 7 Apr 2006 11:35:06 -0500 Subject: [llvm-commits] CVS: llvm/lib/Target/SparcV9/SparcV9RegisterInfo.cpp SparcV9RegisterInfo.h Message-ID: <200604071635.LAA15525@zion.cs.uiuc.edu> Changes in directory llvm/lib/Target/SparcV9: SparcV9RegisterInfo.cpp updated: 1.12 -> 1.13 SparcV9RegisterInfo.h updated: 1.11 -> 1.12 --- Log message: Foundation for call frame information. --- Diffs of the changes: (+11 -0) SparcV9RegisterInfo.cpp | 9 +++++++++ SparcV9RegisterInfo.h | 2 ++ 2 files changed, 11 insertions(+) Index: llvm/lib/Target/SparcV9/SparcV9RegisterInfo.cpp diff -u llvm/lib/Target/SparcV9/SparcV9RegisterInfo.cpp:1.12 llvm/lib/Target/SparcV9/SparcV9RegisterInfo.cpp:1.13 --- llvm/lib/Target/SparcV9/SparcV9RegisterInfo.cpp:1.12 Tue Mar 28 07:48:33 2006 +++ llvm/lib/Target/SparcV9/SparcV9RegisterInfo.cpp Fri Apr 7 11:34:45 2006 @@ -317,6 +317,15 @@ abort (); } +int SparcV9RegisterInfo::getDwarfRegNum(unsigned RegNum) const { + abort (); + return 0; +} + +unsigned SparcV9RegisterInfo::getRARegister() const { + abort (); + return 0; +} unsigned SparcV9RegisterInfo::getFrameRegister(MachineFunction &MF) const { abort (); Index: llvm/lib/Target/SparcV9/SparcV9RegisterInfo.h diff -u llvm/lib/Target/SparcV9/SparcV9RegisterInfo.h:1.11 llvm/lib/Target/SparcV9/SparcV9RegisterInfo.h:1.12 --- llvm/lib/Target/SparcV9/SparcV9RegisterInfo.h:1.11 Tue Mar 28 07:48:33 2006 +++ llvm/lib/Target/SparcV9/SparcV9RegisterInfo.h Fri Apr 7 11:34:45 2006 @@ -46,6 +46,8 @@ void emitEpilogue (MachineFunction &MF, MachineBasicBlock &MBB) const; // Debug information queries. + int getDwarfRegNum(unsigned RegNum) const; + unsigned getRARegister() const; unsigned getFrameRegister(MachineFunction &MF) const; }; From jlaskey at apple.com Fri Apr 7 11:35:05 2006 From: jlaskey at apple.com (Jim Laskey) Date: Fri, 7 Apr 2006 11:35:05 -0500 Subject: [llvm-commits] CVS: llvm/include/llvm/Target/MRegisterInfo.h Message-ID: <200604071635.LAA15511@zion.cs.uiuc.edu> Changes in directory llvm/include/llvm/Target: MRegisterInfo.h updated: 1.73 -> 1.74 --- Log message: Foundation for call frame information. --- Diffs of the changes: (+20 -2) MRegisterInfo.h | 22 ++++++++++++++++++++-- 1 files changed, 20 insertions(+), 2 deletions(-) Index: llvm/include/llvm/Target/MRegisterInfo.h diff -u llvm/include/llvm/Target/MRegisterInfo.h:1.73 llvm/include/llvm/Target/MRegisterInfo.h:1.74 --- llvm/include/llvm/Target/MRegisterInfo.h:1.73 Tue Mar 28 07:48:33 2006 +++ llvm/include/llvm/Target/MRegisterInfo.h Fri Apr 7 11:34:45 2006 @@ -27,6 +27,7 @@ class MachineFunction; class MachineInstr; class MachineLocation; +class MachineMove; class TargetRegisterClass; /// TargetRegisterDesc - This record contains all of the information known about @@ -345,18 +346,35 @@ //===--------------------------------------------------------------------===// /// Debug information queries. + + /// getDwarfRegNum - Map a target register to an equivalent dwarf register + /// number. Returns -1 if there is no equivalent value. + virtual int getDwarfRegNum(unsigned RegNum) const = 0; /// getFrameRegister - This method should return the register used as a base - /// for values allocated in the current stack frame. This value should be - /// returned as a dwarf register number (getDwarfRegNum.) + /// for values allocated in the current stack frame. virtual unsigned getFrameRegister(MachineFunction &MF) const = 0; + + /// getRARegister - This method should return the register where the return + /// address can be found. + virtual unsigned getRARegister() const = 0; + /// getStackDirection - This method should return the factor by which stacks + /// grow. The tyical value is -4 which is the grows negatively in 4 byte + /// increments. + virtual int getStackDirection() const; + /// getLocation - This method should return the actual location of a frame /// variable given the frame index. The location is returned in ML. /// Subclasses should override this method for special handling of frame /// variables and call MRegisterInfo::getLocation for the default action. virtual void getLocation(MachineFunction &MF, unsigned Index, MachineLocation &ML) const; + + /// getInitialFrameState - Returns a list of machine moves that are assumed + /// on entry to all functions. Note that LabelID is ignored (assumed to be + /// the beginning of the function.) + virtual void getInitialFrameState(std::vector &Moves) const; }; // This is useful when building DenseMaps keyed on virtual registers From jlaskey at apple.com Fri Apr 7 11:35:06 2006 From: jlaskey at apple.com (Jim Laskey) Date: Fri, 7 Apr 2006 11:35:06 -0500 Subject: [llvm-commits] CVS: llvm/lib/Target/Sparc/SparcRegisterInfo.cpp SparcRegisterInfo.h Message-ID: <200604071635.LAA15537@zion.cs.uiuc.edu> Changes in directory llvm/lib/Target/Sparc: SparcRegisterInfo.cpp updated: 1.40 -> 1.41 SparcRegisterInfo.h updated: 1.11 -> 1.12 --- Log message: Foundation for call frame information. --- Diffs of the changes: (+8 -1) SparcRegisterInfo.cpp | 8 +++++++- SparcRegisterInfo.h | 1 + 2 files changed, 8 insertions(+), 1 deletion(-) Index: llvm/lib/Target/Sparc/SparcRegisterInfo.cpp diff -u llvm/lib/Target/Sparc/SparcRegisterInfo.cpp:1.40 llvm/lib/Target/Sparc/SparcRegisterInfo.cpp:1.41 --- llvm/lib/Target/Sparc/SparcRegisterInfo.cpp:1.40 Tue Mar 28 07:48:33 2006 +++ llvm/lib/Target/Sparc/SparcRegisterInfo.cpp Fri Apr 7 11:34:45 2006 @@ -200,8 +200,14 @@ BuildMI(MBB, MBBI, SP::RESTORErr, 2, SP::G0).addReg(SP::G0).addReg(SP::G0); } +unsigned SparcRegisterInfo::getRARegister() const { + assert(0 && "What is the return address register"); + return 0; +} + unsigned SparcRegisterInfo::getFrameRegister(MachineFunction &MF) const { - return getDwarfRegNum(SP::G1); + assert(0 && "What is the frame register"); + return SP::G1; } #include "SparcGenRegisterInfo.inc" Index: llvm/lib/Target/Sparc/SparcRegisterInfo.h diff -u llvm/lib/Target/Sparc/SparcRegisterInfo.h:1.11 llvm/lib/Target/Sparc/SparcRegisterInfo.h:1.12 --- llvm/lib/Target/Sparc/SparcRegisterInfo.h:1.11 Tue Mar 28 07:48:33 2006 +++ llvm/lib/Target/Sparc/SparcRegisterInfo.h Fri Apr 7 11:34:45 2006 @@ -58,6 +58,7 @@ void emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const; // Debug information queries. + unsigned getRARegister() const; unsigned getFrameRegister(MachineFunction &MF) const; }; From jlaskey at apple.com Fri Apr 7 11:35:04 2006 From: jlaskey at apple.com (Jim Laskey) Date: Fri, 7 Apr 2006 11:35:04 -0500 Subject: [llvm-commits] CVS: llvm/lib/CodeGen/DwarfWriter.cpp MachineDebugInfo.cpp PrologEpilogInserter.cpp Message-ID: <200604071635.LAA15499@zion.cs.uiuc.edu> Changes in directory llvm/lib/CodeGen: DwarfWriter.cpp updated: 1.53 -> 1.54 MachineDebugInfo.cpp updated: 1.36 -> 1.37 PrologEpilogInserter.cpp updated: 1.52 -> 1.53 --- Log message: Foundation for call frame information. --- Diffs of the changes: (+153 -43) DwarfWriter.cpp | 153 +++++++++++++++++++++++++++++++++++++---------- MachineDebugInfo.cpp | 37 +++++++---- PrologEpilogInserter.cpp | 6 + 3 files changed, 153 insertions(+), 43 deletions(-) Index: llvm/lib/CodeGen/DwarfWriter.cpp diff -u llvm/lib/CodeGen/DwarfWriter.cpp:1.53 llvm/lib/CodeGen/DwarfWriter.cpp:1.54 --- llvm/lib/CodeGen/DwarfWriter.cpp:1.53 Tue Mar 28 08:58:32 2006 +++ llvm/lib/CodeGen/DwarfWriter.cpp Fri Apr 7 11:34:45 2006 @@ -18,6 +18,7 @@ #include "llvm/Type.h" #include "llvm/CodeGen/AsmPrinter.h" #include "llvm/CodeGen/MachineDebugInfo.h" +#include "llvm/CodeGen/MachineFrameInfo.h" #include "llvm/CodeGen/MachineLocation.h" #include "llvm/Support/Dwarf.h" #include "llvm/Support/CommandLine.h" @@ -1073,8 +1074,6 @@ if (Asm->Data64bitsDirective) { O << Asm->Data64bitsDirective << "0x" << std::hex << Value << std::dec; } else { - const TargetData &TD = Asm->TM.getTargetData(); - if (TD.isBigEndian()) { EmitInt32(unsigned(Value >> 32)); O << "\n"; EmitInt32(unsigned(Value)); @@ -1216,12 +1215,14 @@ /// AddAddress - Add an address attribute to a die based on the location /// provided. void DwarfWriter::AddAddress(DIE *Die, unsigned Attribute, - MachineLocation &Location) { + const MachineLocation &Location) { DIEBlock *Block = new DIEBlock(); if (Location.isRegister()) { - Block->AddUInt(DW_FORM_data1, DW_OP_reg0 + Location.getRegister()); + Block->AddUInt(DW_FORM_data1, + DW_OP_reg0 + RI->getDwarfRegNum(Location.getRegister())); } else { - Block->AddUInt(DW_FORM_data1, DW_OP_breg0 + Location.getRegister()); + Block->AddUInt(DW_FORM_data1, + DW_OP_breg0 + RI->getDwarfRegNum(Location.getRegister())); Block->AddUInt(DW_FORM_sdata, Location.getOffset()); } Block->ComputeSize(*this); @@ -1358,8 +1359,7 @@ // Now normalize offset to the field. Offset -= FieldOffset; - // Maybe we need to work from the other. - const TargetData &TD = Asm->TM.getTargetData(); + // Maybe we need to work from the other end. if (TD.isLittleEndian()) Offset = FieldSize - (Offset + Size); Member->AddUInt(DW_AT_byte_size, 0, FieldSize >> 3); @@ -1515,8 +1515,11 @@ DIE *SubprogramDie = new DIE(DW_TAG_subprogram); SubprogramDie->AddString (DW_AT_name, DW_FORM_string, Name); - SubprogramDie->AddDIEntry (DW_AT_type, DW_FORM_ref4, Type); - SubprogramDie->AddUInt (DW_AT_external, DW_FORM_flag, IsExternal); + if (Type) { + SubprogramDie->AddDIEntry (DW_AT_type, DW_FORM_ref4, Type); + } + SubprogramDie->AddUInt (DW_AT_external, DW_FORM_flag, IsExternal); + SubprogramDie->AddUInt (DW_AT_prototyped, DW_FORM_flag, 1); // Add source line info if available. AddSourceLine(SubprogramDie, UnitDesc, SPD->getLine()); @@ -1561,7 +1564,7 @@ // Add variable address. MachineLocation Location; - Asm->TM.getRegisterInfo()->getLocation(*MF, DV->getFrameIndex(), Location); + RI->getLocation(*MF, DV->getFrameIndex(), Location); AddAddress(VariableDie, DW_AT_location, Location); return VariableDie; @@ -1621,18 +1624,20 @@ // Get the compile unit context. CompileUnitDesc *UnitDesc = static_cast(SPD->getContext()); - CompileUnit *Unit = FindCompileUnit(UnitDesc); + CompileUnit *Unit = FindCompileUnit(UnitDesc); + + // Generate the mangled name. + std::string MangledName = Asm->Mang->getValueName(MF->getFunction()); // Get the subprogram die. DIE *SPDie = Unit->getDieMapSlotFor(SPD); assert(SPDie && "Missing subprogram descriptor"); // Add the function bounds. - SPDie->AddLabel(DW_AT_low_pc, DW_FORM_addr, - DWLabel("func_begin", SubprogramCount)); + SPDie->AddObjectLabel(DW_AT_low_pc, DW_FORM_addr, MangledName); SPDie->AddLabel(DW_AT_high_pc, DW_FORM_addr, DWLabel("func_end", SubprogramCount)); - MachineLocation Location(Asm->TM.getRegisterInfo()->getFrameRegister(*MF)); + MachineLocation Location(RI->getFrameRegister(*MF)); AddAddress(SPDie, DW_AT_frame_base, Location); ConstructScope(RootScope, SPDie, Unit); @@ -1792,6 +1797,50 @@ } } +/// EmitFrameMoves - Emit frame instructions to describe the layout of the +/// frame. +void DwarfWriter::EmitFrameMoves(const char *BaseLabel, unsigned BaseLabelID, + std::vector &Moves) { + for (unsigned i = 0, N = Moves.size(); i < N; ++i) { + MachineMove *Move = Moves[i]; + unsigned LabelID = Move->getLabelID(); + const MachineLocation &Dst = Move->getDestination(); + const MachineLocation &Src = Move->getSource(); + + // Advance row if new location. + if (BaseLabel && LabelID && BaseLabelID != LabelID) { + EmitULEB128Bytes(DW_CFA_advance_loc4); + EOL("DW_CFA_advance_loc4"); + EmitDifference("loc", LabelID, BaseLabel, BaseLabelID); + EOL(""); + + BaseLabelID = LabelID; + BaseLabel = "loc"; + } + + // If advancing cfa. + if (Dst.isRegister() && Dst.getRegister() == MachineLocation::VirtualFP) { + if (!Src.isRegister()) { + if (Src.getRegister() == MachineLocation::VirtualFP) { + EmitULEB128Bytes(DW_CFA_def_cfa_offset); + EOL("DW_CFA_def_cfa_offset"); + } else { + EmitULEB128Bytes(DW_CFA_def_cfa); + EOL("DW_CFA_def_cfa"); + + EmitULEB128Bytes(RI->getDwarfRegNum(Src.getRegister())); + EOL("Register"); + } + + EmitULEB128Bytes(Src.getOffset() / RI->getStackDirection()); + EOL("Offset"); + } else { + } + } else { + } + } +} + /// EmitDebugInfo - Emit the debug info section. /// void DwarfWriter::EmitDebugInfo() const { @@ -1999,10 +2048,10 @@ O << "\n"; } -/// EmitDebugFrame - Emit visible names into a debug frame section. +/// EmitInitialDebugFrame - Emit common frame info into a debug frame section. /// -void DwarfWriter::EmitDebugFrame() { - // Start the dwarf pubnames section. +void DwarfWriter::EmitInitialDebugFrame() { + // Start the dwarf frame section. Asm->SwitchSection(DwarfFrameSection, 0); EmitDifference("frame_common_end", 0, @@ -2014,20 +2063,49 @@ EmitInt8(DW_CIE_VERSION); EOL("CIE Version"); EmitString(""); EOL("CIE Augmentation"); EmitULEB128Bytes(1); EOL("CIE Code Alignment Factor"); - // FIXME - needs to change based on stack direction. - EmitSLEB128Bytes(-sizeof(int32_t)); EOL("CIE Data Alignment Factor"); - // FIXME - hard coded for PPC (LR). - EmitInt8(0x41); EOL("CIE RA Column Hardcoded (PPC LR)"); - // FIXME - hard coded for PPC 0(SP). - EmitULEB128Bytes(DW_CFA_def_cfa); EOL("DW_CFA_def_cfa"); - EmitULEB128Bytes(1); EOL("PPC Register SP"); - EmitULEB128Bytes(0); EOL("PPC offset 0 as in 0(SP)"); + EmitSLEB128Bytes(RI->getStackDirection()); EOL("CIE Data Alignment Factor"); + EmitInt8(RI->getDwarfRegNum(RI->getRARegister())); EOL("CIE RA Column"); + + std::vector Moves; + RI->getInitialFrameState(Moves); + EmitFrameMoves(NULL, 0, Moves); + for (unsigned i = 0, N = Moves.size(); i < N; ++i) delete Moves[i]; + EmitAlign(2); EmitLabel("frame_common_end", 0); O << "\n"; } +/// EmitFunctionDebugFrame - Emit per function frame info into a debug frame +/// section. +void DwarfWriter::EmitFunctionDebugFrame() { + // Start the dwarf frame section. + Asm->SwitchSection(DwarfFrameSection, 0); + + EmitDifference("frame_end", SubprogramCount, + "frame_begin", SubprogramCount); + EOL("Length of Frame Information Entry"); + + EmitLabel("frame_begin", SubprogramCount); + + EmitReference("section_frame", 0); EOL("FDE CIE offset"); + + EmitReference("func_begin", SubprogramCount); EOL("FDE initial location"); + EmitDifference("func_end", SubprogramCount, + "func_begin", SubprogramCount); + EOL("FDE address range"); + + std::vector &Moves = DebugInfo->getFrameMoves(); + + EmitFrameMoves("func_begin", SubprogramCount, Moves); + + EmitAlign(2); + EmitLabel("frame_end", SubprogramCount); + + O << "\n"; +} + /// EmitDebugPubNames - Emit visible names into a debug pubnames section. /// void DwarfWriter::EmitDebugPubNames() { @@ -2208,6 +2286,9 @@ if (!didInitial) { EmitInitial(); + // Emit common frame information. + EmitInitialDebugFrame(); + // Create all the compile unit DIEs. ConstructCompileUnitDIEs(); @@ -2231,6 +2312,8 @@ DwarfWriter::DwarfWriter(std::ostream &OS, AsmPrinter *A) : O(OS) , Asm(A) +, TD(Asm->TM.getTargetData()) +, RI(Asm->TM.getRegisterInfo()) , M(NULL) , MF(NULL) , DebugInfo(NULL) @@ -2267,6 +2350,12 @@ } } +/// SetDebugInfo - Set DebugInfo when it's known that pass manager has +/// created it. Set by the target AsmPrinter. +void DwarfWriter::SetDebugInfo(MachineDebugInfo *DI) { + DebugInfo = DI; +} + /// BeginModule - Emit all Dwarf sections that should come prior to the content. /// void DwarfWriter::BeginModule(Module *M) { @@ -2300,9 +2389,6 @@ // Emit source line correspondence into a debug line section. EmitDebugLines(); - // Emit info into a debug frame section. - EmitDebugFrame(); - // Emit info into a debug pubnames section. EmitDebugPubNames(); @@ -2327,6 +2413,9 @@ void DwarfWriter::BeginFunction(MachineFunction *MF) { this->MF = MF; + // Begin accumulating function debug information. + DebugInfo->BeginFunction(MF); + if (!ShouldEmitDwarf()) return; EOL("Dwarf Begin Function"); @@ -2335,7 +2424,6 @@ EmitLabel("func_begin", ++SubprogramCount); } - /// EndFunction - Gather and emit post-function debug information. /// void DwarfWriter::EndFunction() { @@ -2348,5 +2436,10 @@ // Construct scopes for subprogram. ConstructRootScope(DebugInfo->getRootScope()); - DebugInfo->ClearScopes(); + + // Emit function frame information. + EmitFunctionDebugFrame(); + + // Clear function debug information. + DebugInfo->EndFunction(); } Index: llvm/lib/CodeGen/MachineDebugInfo.cpp diff -u llvm/lib/CodeGen/MachineDebugInfo.cpp:1.36 llvm/lib/CodeGen/MachineDebugInfo.cpp:1.37 --- llvm/lib/CodeGen/MachineDebugInfo.cpp:1.36 Mon Mar 27 19:30:18 2006 +++ llvm/lib/CodeGen/MachineDebugInfo.cpp Fri Apr 7 11:34:45 2006 @@ -10,6 +10,7 @@ #include "llvm/CodeGen/MachineDebugInfo.h" #include "llvm/Constants.h" +#include "llvm/CodeGen/MachineLocation.h" #include "llvm/DerivedTypes.h" #include "llvm/GlobalVariable.h" #include "llvm/Intrinsics.h" @@ -1424,9 +1425,8 @@ , LabelID(0) , ScopeMap() , RootScope(NULL) -{ - -} +, FrameMoves() +{} MachineDebugInfo::~MachineDebugInfo() { } @@ -1443,6 +1443,27 @@ return false; } +/// BeginFunction - Begin gathering function debug information. +/// +void MachineDebugInfo::BeginFunction(MachineFunction *MF) { + // Coming soon. +} + +/// MachineDebugInfo::EndFunction - Discard function debug information. +/// +void MachineDebugInfo::EndFunction() { + // Clean up scope information. + if (RootScope) { + delete RootScope; + ScopeMap.clear(); + RootScope = NULL; + } + + // Clean up frame info. + for (unsigned i = 0, N = FrameMoves.size(); i < N; ++i) delete FrameMoves[i]; + FrameMoves.clear(); +} + /// getDescFor - Convert a Value to a debug information descriptor. /// // FIXME - use new Value type when available. @@ -1565,14 +1586,4 @@ return Slot; } -/// ClearScopes - Delete the scope and variable info after a function is -/// completed. -void MachineDebugInfo::ClearScopes() { - if (RootScope) { - delete RootScope; - ScopeMap.clear(); - RootScope = NULL; - } -} - Index: llvm/lib/CodeGen/PrologEpilogInserter.cpp diff -u llvm/lib/CodeGen/PrologEpilogInserter.cpp:1.52 llvm/lib/CodeGen/PrologEpilogInserter.cpp:1.53 --- llvm/lib/CodeGen/PrologEpilogInserter.cpp:1.52 Mon Apr 3 16:39:57 2006 +++ llvm/lib/CodeGen/PrologEpilogInserter.cpp Fri Apr 7 11:34:45 2006 @@ -36,6 +36,12 @@ /// frame indexes with appropriate references. /// bool runOnMachineFunction(MachineFunction &Fn) { + // Get MachineDebugInfo so that we can track the construction of the + // frame. + if (MachineDebugInfo *DI = getAnalysisToUpdate()) { + Fn.getFrameInfo()->setMachineDebugInfo(DI); + } + // Scan the function for modified caller saved registers and insert spill // code for any caller saved registers that are modified. Also calculate // the MaxCallFrameSize and HasCalls variables for the function's frame From lattner at cs.uiuc.edu Fri Apr 7 13:41:29 2006 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Fri, 7 Apr 2006 13:41:29 -0500 Subject: [llvm-commits] CVS: llvm/runtime/Makefile Message-ID: <200604071841.NAA16123@zion.cs.uiuc.edu> Changes in directory llvm/runtime: Makefile updated: 1.26 -> 1.27 --- Log message: add a newline at the end of the file --- Diffs of the changes: (+2 -1) Makefile | 3 ++- 1 files changed, 2 insertions(+), 1 deletion(-) Index: llvm/runtime/Makefile diff -u llvm/runtime/Makefile:1.26 llvm/runtime/Makefile:1.27 --- llvm/runtime/Makefile:1.26 Thu Apr 6 17:15:51 2006 +++ llvm/runtime/Makefile Fri Apr 7 13:41:16 2006 @@ -13,7 +13,7 @@ ifneq ($(LLVMGCC_MAJVERS),3) PARALLEL_DIRS := install all:: - $(Echo) "Warning: The runtime libraries only need to be built with" + $(Echo) "Warning: These runtime libraries only need to be built with" $(Echo) "Warning: llvm-gcc version 3. They are automatically included" $(Echo) "Warning: with llvm-gcc version 4 and beyond" else @@ -40,3 +40,4 @@ # Install target for libraries: Copy into $LLVMGCCDIR/bytecode-libs # install:: + From reid at x10sys.com Fri Apr 7 13:53:35 2006 From: reid at x10sys.com (Reid Spencer) Date: Fri, 7 Apr 2006 13:53:35 -0500 Subject: [llvm-commits] CVS: llvm-test/autoconf/m4/external_benchmark.m4 Message-ID: <200604071853.NAA16200@zion.cs.uiuc.edu> Changes in directory llvm-test/autoconf/m4: external_benchmark.m4 updated: 1.2 -> 1.3 --- Log message: For PR646: http://llvm.cs.uiuc.edu/PR646 : 1. Provide a --with-externals=DIR option to configure to specify the base directory for the external tests. Default its setting to the old default: /home/vadve/shared/benchmarks 2. Change the EXTERNAL_BENCHMARK macro invocations in configure.ac to use the value of LLVM_EXTERNALS (directory from --with-externals, or its default). 3. Change EXTERNAL_BENCHMARK macro to use AC_ARG_WITH instead of AC_ARG_ENABLE since these options specify a location rather than enablement of a feature. 4. Move the EXTERNAL_BENCHMARK macro invocations from the end of the file to just after the --with-externals definition so that it is clear that these --with-x options are related. --- Diffs of the changes: (+3 -4) external_benchmark.m4 | 7 +++---- 1 files changed, 3 insertions(+), 4 deletions(-) Index: llvm-test/autoconf/m4/external_benchmark.m4 diff -u llvm-test/autoconf/m4/external_benchmark.m4:1.2 llvm-test/autoconf/m4/external_benchmark.m4:1.3 --- llvm-test/autoconf/m4/external_benchmark.m4:1.2 Wed Dec 29 13:13:43 2004 +++ llvm-test/autoconf/m4/external_benchmark.m4 Fri Apr 7 13:53:21 2006 @@ -5,10 +5,9 @@ dnl $2 full path to benchmark source AC_DEFUN([EXTERNAL_BENCHMARK], [m4_define([allcapsname],translit($1,a-z,A-Z)) - AC_ARG_ENABLE($1, - AS_HELP_STRING([--enable-$1=ARG], - [Use $1 as a benchmark (srcs in DIR)]), - checkresult=$enableval, + AC_ARG_WITH($1, + AS_HELP_STRING([--with-$1=DIR],[Use $1 as a benchmark (srcs in DIR)]), + checkresult=$withval, checkresult=auto) AC_MSG_CHECKING([for $1 benchmark sources]) case "$checkresult" in From reid at x10sys.com Fri Apr 7 13:53:36 2006 From: reid at x10sys.com (Reid Spencer) Date: Fri, 7 Apr 2006 13:53:36 -0500 Subject: [llvm-commits] CVS: llvm-test/autoconf/configure.ac Message-ID: <200604071853.NAA16204@zion.cs.uiuc.edu> Changes in directory llvm-test/autoconf: configure.ac updated: 1.30 -> 1.31 --- Log message: For PR646: http://llvm.cs.uiuc.edu/PR646 : 1. Provide a --with-externals=DIR option to configure to specify the base directory for the external tests. Default its setting to the old default: /home/vadve/shared/benchmarks 2. Change the EXTERNAL_BENCHMARK macro invocations in configure.ac to use the value of LLVM_EXTERNALS (directory from --with-externals, or its default). 3. Change EXTERNAL_BENCHMARK macro to use AC_ARG_WITH instead of AC_ARG_ENABLE since these options specify a location rather than enablement of a feature. 4. Move the EXTERNAL_BENCHMARK macro invocations from the end of the file to just after the --with-externals definition so that it is clear that these --with-x options are related. --- Diffs of the changes: (+23 -11) configure.ac | 34 +++++++++++++++++++++++----------- 1 files changed, 23 insertions(+), 11 deletions(-) Index: llvm-test/autoconf/configure.ac diff -u llvm-test/autoconf/configure.ac:1.30 llvm-test/autoconf/configure.ac:1.31 --- llvm-test/autoconf/configure.ac:1.30 Wed Dec 21 20:10:25 2005 +++ llvm-test/autoconf/configure.ac Fri Apr 7 13:53:21 2006 @@ -49,10 +49,31 @@ dnl ************************************************************************** dnl Location of LLVM source code -AC_ARG_WITH(llvmsrc,AS_HELP_STRING(--with-llvmsrc,Location of LLVM Source Code),AC_SUBST(LLVM_SRC,[$withval]),AC_SUBST(LLVM_SRC,[`cd ${srcdir}/../..; pwd`])) +AC_ARG_WITH(llvmsrc, + AS_HELP_STRING([--with-llvmsrc=DIR],Location of LLVM Source Code), + AC_SUBST(LLVM_SRC,[$withval]), + AC_SUBST(LLVM_SRC,[`cd ${srcdir}/../..; pwd`])) dnl Location of LLVM object code -AC_ARG_WITH(llvmobj,AS_HELP_STRING(--with-llvmobj,Location of LLVM Object Code),AC_SUBST(LLVM_OBJ,[$withval]),AC_SUBST(LLVM_OBJ,[`cd ../..; pwd`])) +AC_ARG_WITH(llvmobj, + AS_HELP_STRING([--with-llvmobj],Location of LLVM Object Code), + AC_SUBST(LLVM_OBJ,[$withval]), + AC_SUBST(LLVM_OBJ,[`cd ../..; pwd`])) + +dnl Location of the parent directory of the external tests +AC_ARG_WITH(externals, + AS_HELP_STRING([--with-externals=DIR],Location of External Test code), + AC_SUBST(LLVM_EXTERNALS,[$withval]), + AC_SUBST(LLVM_EXTERNALS,[/home/vadve/shared/benchmarks])) + +dnl Configure the default locations of the external benchmarks +EXTERNAL_BENCHMARK(spec95,${LLVM_EXTERNALS}/spec95/benchspec) +EXTERNAL_BENCHMARK(spec2000,${LLVM_EXTERNALS}/speccpu2000/benchspec) +EXTERNAL_BENCHMARK(povray,${LLVM_EXTERNALS}/povray31) +EXTERNAL_BENCHMARK(namd,${LLVM_EXTERNALS}/spec_namd) +EXTERNAL_BENCHMARK(sweep3d,${LLVM_EXTERNALS}/sweep3d) +EXTERNAL_BENCHMARK(fpgrowth,${LLVM_EXTERNALS}/fpgrowth) +EXTERNAL_BENCHMARK(alp,${LLVM_EXTERNALS}/alp) dnl LLC Diff Option AC_ARG_ENABLE(llc_diffs, @@ -108,14 +129,5 @@ AC_CHECK_FUNC([re_comp],[AC_SUBST(HAVE_RE_COMP,[HAVE_RE_COMP:=1])], [AC_SUBST(HAVE_RE_COMP,[[]])]) -dnl Configure the default locations of the external benchmarks -EXTERNAL_BENCHMARK(spec95,/home/vadve/shared/benchmarks/spec95/benchspec) -EXTERNAL_BENCHMARK(spec2000,/home/vadve/shared/benchmarks/speccpu2000/benchspec) -EXTERNAL_BENCHMARK(povray,/home/vadve/shared/benchmarks/povray31) -EXTERNAL_BENCHMARK(namd,/home/vadve/shared/benchmarks/spec_namd) -EXTERNAL_BENCHMARK(sweep3d,/home/vadve/criswell/umt2k) -EXTERNAL_BENCHMARK(fpgrowth,/home/vadve/shared/benchmarks/fpgrowth) -EXTERNAL_BENCHMARK(alp,/home/vadve/shared/benchmarks/ALP) - dnl Create the output files AC_OUTPUT From reid at x10sys.com Fri Apr 7 13:53:34 2006 From: reid at x10sys.com (Reid Spencer) Date: Fri, 7 Apr 2006 13:53:34 -0500 Subject: [llvm-commits] CVS: llvm-test/configure Message-ID: <200604071853.NAA16196@zion.cs.uiuc.edu> Changes in directory llvm-test: configure updated: 1.31 -> 1.32 --- Log message: For PR646: http://llvm.cs.uiuc.edu/PR646 : 1. Provide a --with-externals=DIR option to configure to specify the base directory for the external tests. Default its setting to the old default: /home/vadve/shared/benchmarks 2. Change the EXTERNAL_BENCHMARK macro invocations in configure.ac to use the value of LLVM_EXTERNALS (directory from --with-externals, or its default). 3. Change EXTERNAL_BENCHMARK macro to use AC_ARG_WITH instead of AC_ARG_ENABLE since these options specify a location rather than enablement of a feature. 4. Move the EXTERNAL_BENCHMARK macro invocations from the end of the file to just after the --with-externals definition so that it is clear that these --with-x options are related. --- Diffs of the changes: (+591 -571) configure | 1162 +++++++++++++++++++++++++++++++------------------------------- 1 files changed, 591 insertions(+), 571 deletions(-) Index: llvm-test/configure diff -u llvm-test/configure:1.31 llvm-test/configure:1.32 --- llvm-test/configure:1.31 Wed Dec 21 20:10:25 2005 +++ llvm-test/configure Fri Apr 7 13:53:21 2006 @@ -465,7 +465,7 @@ # include #endif" -ac_subst_vars='SHELL PATH_SEPARATOR PACKAGE_NAME PACKAGE_TARNAME PACKAGE_VERSION PACKAGE_STRING PACKAGE_BUGREPORT exec_prefix prefix program_transform_name bindir sbindir libexecdir datadir sysconfdir sharedstatedir localstatedir libdir includedir oldincludedir infodir mandir build_alias host_alias target_alias DEFS ECHO_C ECHO_N ECHO_T LIBS LLVM_SRC LLVM_OBJ DISABLE_LLC_DIFFS CXX CXXFLAGS LDFLAGS CPPFLAGS ac_ct_CXX EXEEXT OBJEXT CC CFLAGS ac_ct_CC CPP ifGNUmake LEX LEXLIB LEX_OUTPUT_ROOT FLEX YACC BISON build build_cpu build_vendor build_os host host_cpu host_vendor host_os EGREP LN_S ECHO AR ac_ct_AR RANLIB ac_ct_RANLIB STRIP ac_ct_STRIP CXXCPP F77 FFLAGS ac_ct_F77 LIBTOOL USE_F2C F2C F2C_BIN F2C_DIR F2C_INC F2C_LIB USE_F95 F95 F95_BIN F95_DIR F95_INC F95_LIB HAVE_RE_COMP SPEC95_ROOT USE_SPEC95 SPEC2000_ROOT USE_SPEC2000 POVRAY_ROOT USE_POVRAY NAMD_ROOT USE_NAMD SWEEP3D_ROOT USE_SWEEP3D FPGROWTH_ROOT USE_FPGROWTH ALP_ROOT USE_ALP LIBOBJS LTLIBOBJS' +ac_subst_vars='SHELL PATH_SEPARATOR PACKAGE_NAME PACKAGE_TARNAME PACKAGE_VERSION PACKAGE_STRING PACKAGE_BUGREPORT exec_prefix prefix program_transform_name bindir sbindir libexecdir datadir sysconfdir sharedstatedir localstatedir libdir includedir oldincludedir infodir mandir build_alias host_alias target_alias DEFS ECHO_C ECHO_N ECHO_T LIBS LLVM_SRC LLVM_OBJ LLVM_EXTERNALS SPEC95_ROOT USE_SPEC95 SPEC2000_ROOT USE_SPEC2000 POVRAY_ROOT USE_POVRAY NAMD_ROOT USE_NAMD SWEEP3D_ROOT USE_SWEEP3D FPGROWTH_ROOT USE_FPGROWTH ALP_ROOT USE_ALP DISABLE_LLC_DIFFS CXX CXXFLAGS LDFLAGS CPPFLAGS ac_ct_CXX EXEEXT OBJEXT CC CFLAGS ac_ct_CC CPP ifGNUmake LEX LEXLIB LEX_OUTPUT_ROOT FLEX YACC BISON build build_cpu build_vendor build_os host host_cpu host_vendor host_os EGREP LN_S ECHO AR ac_ct_AR RANLIB ac_ct_RANLIB STRIP ac_ct_STRIP CXXCPP F77 FFLAGS ac_ct_F77 LIBTOOL USE_F2C F2C F2C_BIN F2C_DIR F2C_INC F2C_LIB USE_F95 F95 F95_BIN F95_DIR F95_INC F95_LIB HAVE_RE_COMP LIBOBJS LTLIBOBJS' ac_subst_files='' # Initialize some variables set by options. @@ -1030,19 +1030,20 @@ --enable-fast-install[=PKGS] optimize for fast installation [default=yes] --disable-libtool-lock avoid locking (might break parallel builds) - --enable-spec95=ARG Use spec95 as a benchmark (srcs in DIR) - --enable-spec2000=ARG Use spec2000 as a benchmark (srcs in DIR) - --enable-povray=ARG Use povray as a benchmark (srcs in DIR) - --enable-namd=ARG Use namd as a benchmark (srcs in DIR) - --enable-sweep3d=ARG Use sweep3d as a benchmark (srcs in DIR) - --enable-fpgrowth=ARG Use fpgrowth as a benchmark (srcs in DIR) - --enable-alp=ARG Use alp as a benchmark (srcs in DIR) Optional Packages: --with-PACKAGE[=ARG] use PACKAGE [ARG=yes] --without-PACKAGE do not use PACKAGE (same as --with-PACKAGE=no) - --with-llvmsrc Location of LLVM Source Code + --with-llvmsrc=DIR Location of LLVM Source Code --with-llvmobj Location of LLVM Object Code + --with-externals=DIR Location of External Test code + --with-spec95=DIR Use spec95 as a benchmark (srcs in DIR) + --with-spec2000=DIR Use spec2000 as a benchmark (srcs in DIR) + --with-povray=DIR Use povray as a benchmark (srcs in DIR) + --with-namd=DIR Use namd as a benchmark (srcs in DIR) + --with-sweep3d=DIR Use sweep3d as a benchmark (srcs in DIR) + --with-fpgrowth=DIR Use fpgrowth as a benchmark (srcs in DIR) + --with-alp=DIR Use alp as a benchmark (srcs in DIR) --with-gnu-ld assume the C compiler uses GNU ld [default=no] --with-pic try to use only PIC/non-PIC objects [default=use both] @@ -1679,6 +1680,354 @@ fi; + +# Check whether --with-externals or --without-externals was given. +if test "${with_externals+set}" = set; then + withval="$with_externals" + LLVM_EXTERNALS=$withval + +else + LLVM_EXTERNALS=/home/vadve/shared/benchmarks + +fi; + + + +# Check whether --with-spec95 or --without-spec95 was given. +if test "${with_spec95+set}" = set; then + withval="$with_spec95" + checkresult=$withval +else + checkresult=auto +fi; +echo "$as_me:$LINENO: checking for spec95 benchmark sources" >&5 +echo $ECHO_N "checking for spec95 benchmark sources... $ECHO_C" >&6 +case "$checkresult" in +auto|yes) + defaultdir=${LLVM_EXTERNALS}/spec95/benchspec + if test -d "$defaultdir" + then + SPEC95_ROOT=$defaultdir + + USE_SPEC95=USE_SPEC95=1 + + checkresult="yes, found in $defaultdir" + else + checkresult=no + fi + ;; +no) + + + checkresult=no + ;; +*) if test -d "$checkresult" + then + SPEC95_ROOT="$checkresult" + + USE_SPEC95=USE_SPEC95=1 + + checkresult="yes, in $checkresult" + else + + + checkresult="no, not found in $checkresult" + fi + ;; +esac +echo "$as_me:$LINENO: result: $checkresult" >&5 +echo "${ECHO_T}$checkresult" >&6 + + + + +# Check whether --with-spec2000 or --without-spec2000 was given. +if test "${with_spec2000+set}" = set; then + withval="$with_spec2000" + checkresult=$withval +else + checkresult=auto +fi; +echo "$as_me:$LINENO: checking for spec2000 benchmark sources" >&5 +echo $ECHO_N "checking for spec2000 benchmark sources... $ECHO_C" >&6 +case "$checkresult" in +auto|yes) + defaultdir=${LLVM_EXTERNALS}/speccpu2000/benchspec + if test -d "$defaultdir" + then + SPEC2000_ROOT=$defaultdir + + USE_SPEC2000=USE_SPEC2000=1 + + checkresult="yes, found in $defaultdir" + else + checkresult=no + fi + ;; +no) + + + checkresult=no + ;; +*) if test -d "$checkresult" + then + SPEC2000_ROOT="$checkresult" + + USE_SPEC2000=USE_SPEC2000=1 + + checkresult="yes, in $checkresult" + else + + + checkresult="no, not found in $checkresult" + fi + ;; +esac +echo "$as_me:$LINENO: result: $checkresult" >&5 +echo "${ECHO_T}$checkresult" >&6 + + + + +# Check whether --with-povray or --without-povray was given. +if test "${with_povray+set}" = set; then + withval="$with_povray" + checkresult=$withval +else + checkresult=auto +fi; +echo "$as_me:$LINENO: checking for povray benchmark sources" >&5 +echo $ECHO_N "checking for povray benchmark sources... $ECHO_C" >&6 +case "$checkresult" in +auto|yes) + defaultdir=${LLVM_EXTERNALS}/povray31 + if test -d "$defaultdir" + then + POVRAY_ROOT=$defaultdir + + USE_POVRAY=USE_POVRAY=1 + + checkresult="yes, found in $defaultdir" + else + checkresult=no + fi + ;; +no) + + + checkresult=no + ;; +*) if test -d "$checkresult" + then + POVRAY_ROOT="$checkresult" + + USE_POVRAY=USE_POVRAY=1 + + checkresult="yes, in $checkresult" + else + + + checkresult="no, not found in $checkresult" + fi + ;; +esac +echo "$as_me:$LINENO: result: $checkresult" >&5 +echo "${ECHO_T}$checkresult" >&6 + + + + +# Check whether --with-namd or --without-namd was given. +if test "${with_namd+set}" = set; then + withval="$with_namd" + checkresult=$withval +else + checkresult=auto +fi; +echo "$as_me:$LINENO: checking for namd benchmark sources" >&5 +echo $ECHO_N "checking for namd benchmark sources... $ECHO_C" >&6 +case "$checkresult" in +auto|yes) + defaultdir=${LLVM_EXTERNALS}/spec_namd + if test -d "$defaultdir" + then + NAMD_ROOT=$defaultdir + + USE_NAMD=USE_NAMD=1 + + checkresult="yes, found in $defaultdir" + else + checkresult=no + fi + ;; +no) + + + checkresult=no + ;; +*) if test -d "$checkresult" + then + NAMD_ROOT="$checkresult" + + USE_NAMD=USE_NAMD=1 + + checkresult="yes, in $checkresult" + else + + + checkresult="no, not found in $checkresult" + fi + ;; +esac +echo "$as_me:$LINENO: result: $checkresult" >&5 +echo "${ECHO_T}$checkresult" >&6 + + + + +# Check whether --with-sweep3d or --without-sweep3d was given. +if test "${with_sweep3d+set}" = set; then + withval="$with_sweep3d" + checkresult=$withval +else + checkresult=auto +fi; +echo "$as_me:$LINENO: checking for sweep3d benchmark sources" >&5 +echo $ECHO_N "checking for sweep3d benchmark sources... $ECHO_C" >&6 +case "$checkresult" in +auto|yes) + defaultdir=${LLVM_EXTERNALS}/sweep3d + if test -d "$defaultdir" + then + SWEEP3D_ROOT=$defaultdir + + USE_SWEEP3D=USE_SWEEP3D=1 + + checkresult="yes, found in $defaultdir" + else + checkresult=no + fi + ;; +no) + + + checkresult=no + ;; +*) if test -d "$checkresult" + then + SWEEP3D_ROOT="$checkresult" + + USE_SWEEP3D=USE_SWEEP3D=1 + + checkresult="yes, in $checkresult" + else + + + checkresult="no, not found in $checkresult" + fi + ;; +esac +echo "$as_me:$LINENO: result: $checkresult" >&5 +echo "${ECHO_T}$checkresult" >&6 + + + + +# Check whether --with-fpgrowth or --without-fpgrowth was given. +if test "${with_fpgrowth+set}" = set; then + withval="$with_fpgrowth" + checkresult=$withval +else + checkresult=auto +fi; +echo "$as_me:$LINENO: checking for fpgrowth benchmark sources" >&5 +echo $ECHO_N "checking for fpgrowth benchmark sources... $ECHO_C" >&6 +case "$checkresult" in +auto|yes) + defaultdir=${LLVM_EXTERNALS}/fpgrowth + if test -d "$defaultdir" + then + FPGROWTH_ROOT=$defaultdir + + USE_FPGROWTH=USE_FPGROWTH=1 + + checkresult="yes, found in $defaultdir" + else + checkresult=no + fi + ;; +no) + + + checkresult=no + ;; +*) if test -d "$checkresult" + then + FPGROWTH_ROOT="$checkresult" + + USE_FPGROWTH=USE_FPGROWTH=1 + + checkresult="yes, in $checkresult" + else + + + checkresult="no, not found in $checkresult" + fi + ;; +esac +echo "$as_me:$LINENO: result: $checkresult" >&5 +echo "${ECHO_T}$checkresult" >&6 + + + + +# Check whether --with-alp or --without-alp was given. +if test "${with_alp+set}" = set; then + withval="$with_alp" + checkresult=$withval +else + checkresult=auto +fi; +echo "$as_me:$LINENO: checking for alp benchmark sources" >&5 +echo $ECHO_N "checking for alp benchmark sources... $ECHO_C" >&6 +case "$checkresult" in +auto|yes) + defaultdir=${LLVM_EXTERNALS}/alp + if test -d "$defaultdir" + then + ALP_ROOT=$defaultdir + + USE_ALP=USE_ALP=1 + + checkresult="yes, found in $defaultdir" + else + checkresult=no + fi + ;; +no) + + + checkresult=no + ;; +*) if test -d "$checkresult" + then + ALP_ROOT="$checkresult" + + USE_ALP=USE_ALP=1 + + checkresult="yes, in $checkresult" + else + + + checkresult="no, not found in $checkresult" + fi + ;; +esac +echo "$as_me:$LINENO: result: $checkresult" >&5 +echo "${ECHO_T}$checkresult" >&6 + + + # Check whether --enable-llc_diffs or --disable-llc_diffs was given. if test "${enable_llc_diffs+set}" = set; then enableval="$enable_llc_diffs" @@ -3988,7 +4337,7 @@ ;; *-*-irix6*) # Find out which ABI we are using. - echo '#line 3991 "configure"' > conftest.$ac_ext + echo '#line 4340 "configure"' > conftest.$ac_ext if { (eval echo "$as_me:$LINENO: \"$ac_compile\"") >&5 (eval $ac_compile) 2>&5 ac_status=$? @@ -4862,7 +5211,7 @@ # Provide some information about the compiler. -echo "$as_me:4865:" \ +echo "$as_me:5214:" \ "checking for Fortran 77 compiler version" >&5 ac_compiler=`set X $ac_compile; echo $2` { (eval echo "$as_me:$LINENO: \"$ac_compiler --version &5\"") >&5 @@ -5919,11 +6268,11 @@ -e 's:.*FLAGS}? :&$lt_compiler_flag :; t' \ -e 's: [^ ]*conftest\.: $lt_compiler_flag&:; t' \ -e 's:$: $lt_compiler_flag:'` - (eval echo "\"\$as_me:5922: $lt_compile\"" >&5) + (eval echo "\"\$as_me:6271: $lt_compile\"" >&5) (eval "$lt_compile" 2>conftest.err) ac_status=$? cat conftest.err >&5 - echo "$as_me:5926: \$? = $ac_status" >&5 + echo "$as_me:6275: \$? = $ac_status" >&5 if (exit $ac_status) && test -s "$ac_outfile"; then # The compiler can only warn and ignore the option if not recognized # So say no if there are warnings @@ -6162,11 +6511,11 @@ -e 's:.*FLAGS}? :&$lt_compiler_flag :; t' \ -e 's: [^ ]*conftest\.: $lt_compiler_flag&:; t' \ -e 's:$: $lt_compiler_flag:'` - (eval echo "\"\$as_me:6165: $lt_compile\"" >&5) + (eval echo "\"\$as_me:6514: $lt_compile\"" >&5) (eval "$lt_compile" 2>conftest.err) ac_status=$? cat conftest.err >&5 - echo "$as_me:6169: \$? = $ac_status" >&5 + echo "$as_me:6518: \$? = $ac_status" >&5 if (exit $ac_status) && test -s "$ac_outfile"; then # The compiler can only warn and ignore the option if not recognized # So say no if there are warnings @@ -6222,11 +6571,11 @@ -e 's:.*FLAGS}? :&$lt_compiler_flag :; t' \ -e 's: [^ ]*conftest\.: $lt_compiler_flag&:; t' \ -e 's:$: $lt_compiler_flag:'` - (eval echo "\"\$as_me:6225: $lt_compile\"" >&5) + (eval echo "\"\$as_me:6574: $lt_compile\"" >&5) (eval "$lt_compile" 2>out/conftest.err) ac_status=$? cat out/conftest.err >&5 - echo "$as_me:6229: \$? = $ac_status" >&5 + echo "$as_me:6578: \$? = $ac_status" >&5 if (exit $ac_status) && test -s out/conftest2.$ac_objext then # The compiler can only warn and ignore the option if not recognized @@ -8407,7 +8756,7 @@ lt_dlunknown=0; lt_dlno_uscore=1; lt_dlneed_uscore=2 lt_status=$lt_dlunknown cat > conftest.$ac_ext < conftest.$ac_ext <&5) + (eval echo "\"\$as_me:11050: $lt_compile\"" >&5) (eval "$lt_compile" 2>conftest.err) ac_status=$? cat conftest.err >&5 - echo "$as_me:10705: \$? = $ac_status" >&5 + echo "$as_me:11054: \$? = $ac_status" >&5 if (exit $ac_status) && test -s "$ac_outfile"; then # The compiler can only warn and ignore the option if not recognized # So say no if there are warnings @@ -10758,11 +11107,11 @@ -e 's:.*FLAGS}? :&$lt_compiler_flag :; t' \ -e 's: [^ ]*conftest\.: $lt_compiler_flag&:; t' \ -e 's:$: $lt_compiler_flag:'` - (eval echo "\"\$as_me:10761: $lt_compile\"" >&5) + (eval echo "\"\$as_me:11110: $lt_compile\"" >&5) (eval "$lt_compile" 2>out/conftest.err) ac_status=$? cat out/conftest.err >&5 - echo "$as_me:10765: \$? = $ac_status" >&5 + echo "$as_me:11114: \$? = $ac_status" >&5 if (exit $ac_status) && test -s out/conftest2.$ac_objext then # The compiler can only warn and ignore the option if not recognized @@ -12119,7 +12468,7 @@ lt_dlunknown=0; lt_dlno_uscore=1; lt_dlneed_uscore=2 lt_status=$lt_dlunknown cat > conftest.$ac_ext < conftest.$ac_ext <&5) + (eval echo "\"\$as_me:13406: $lt_compile\"" >&5) (eval "$lt_compile" 2>conftest.err) ac_status=$? cat conftest.err >&5 - echo "$as_me:13061: \$? = $ac_status" >&5 + echo "$as_me:13410: \$? = $ac_status" >&5 if (exit $ac_status) && test -s "$ac_outfile"; then # The compiler can only warn and ignore the option if not recognized # So say no if there are warnings @@ -13114,11 +13463,11 @@ -e 's:.*FLAGS}? :&$lt_compiler_flag :; t' \ -e 's: [^ ]*conftest\.: $lt_compiler_flag&:; t' \ -e 's:$: $lt_compiler_flag:'` - (eval echo "\"\$as_me:13117: $lt_compile\"" >&5) + (eval echo "\"\$as_me:13466: $lt_compile\"" >&5) (eval "$lt_compile" 2>out/conftest.err) ac_status=$? cat out/conftest.err >&5 - echo "$as_me:13121: \$? = $ac_status" >&5 + echo "$as_me:13470: \$? = $ac_status" >&5 if (exit $ac_status) && test -s out/conftest2.$ac_objext then # The compiler can only warn and ignore the option if not recognized @@ -15153,11 +15502,11 @@ -e 's:.*FLAGS}? :&$lt_compiler_flag :; t' \ -e 's: [^ ]*conftest\.: $lt_compiler_flag&:; t' \ -e 's:$: $lt_compiler_flag:'` - (eval echo "\"\$as_me:15156: $lt_compile\"" >&5) + (eval echo "\"\$as_me:15505: $lt_compile\"" >&5) (eval "$lt_compile" 2>conftest.err) ac_status=$? cat conftest.err >&5 - echo "$as_me:15160: \$? = $ac_status" >&5 + echo "$as_me:15509: \$? = $ac_status" >&5 if (exit $ac_status) && test -s "$ac_outfile"; then # The compiler can only warn and ignore the option if not recognized # So say no if there are warnings @@ -15396,11 +15745,11 @@ -e 's:.*FLAGS}? :&$lt_compiler_flag :; t' \ -e 's: [^ ]*conftest\.: $lt_compiler_flag&:; t' \ -e 's:$: $lt_compiler_flag:'` - (eval echo "\"\$as_me:15399: $lt_compile\"" >&5) + (eval echo "\"\$as_me:15748: $lt_compile\"" >&5) (eval "$lt_compile" 2>conftest.err) ac_status=$? cat conftest.err >&5 - echo "$as_me:15403: \$? = $ac_status" >&5 + echo "$as_me:15752: \$? = $ac_status" >&5 if (exit $ac_status) && test -s "$ac_outfile"; then # The compiler can only warn and ignore the option if not recognized # So say no if there are warnings @@ -15456,11 +15805,11 @@ -e 's:.*FLAGS}? :&$lt_compiler_flag :; t' \ -e 's: [^ ]*conftest\.: $lt_compiler_flag&:; t' \ -e 's:$: $lt_compiler_flag:'` - (eval echo "\"\$as_me:15459: $lt_compile\"" >&5) + (eval echo "\"\$as_me:15808: $lt_compile\"" >&5) (eval "$lt_compile" 2>out/conftest.err) ac_status=$? cat out/conftest.err >&5 - echo "$as_me:15463: \$? = $ac_status" >&5 + echo "$as_me:15812: \$? = $ac_status" >&5 if (exit $ac_status) && test -s out/conftest2.$ac_objext then # The compiler can only warn and ignore the option if not recognized @@ -17641,7 +17990,7 @@ lt_dlunknown=0; lt_dlno_uscore=1; lt_dlneed_uscore=2 lt_status=$lt_dlunknown cat > conftest.$ac_ext < conftest.$ac_ext <&5 echo $ECHO_N "checking for sys/wait.h that is POSIX.1 compatible... $ECHO_C" >&6 if test "${ac_cv_header_sys_wait_h+set}" = set; then - echo $ECHO_N "(cached) $ECHO_C" >&6 -else - cat >conftest.$ac_ext <<_ACEOF -/* confdefs.h. */ -_ACEOF -cat confdefs.h >>conftest.$ac_ext -cat >>conftest.$ac_ext <<_ACEOF -/* end confdefs.h. */ -#include -#include -#ifndef WEXITSTATUS -# define WEXITSTATUS(stat_val) ((unsigned)(stat_val) >> 8) -#endif -#ifndef WIFEXITED -# define WIFEXITED(stat_val) (((stat_val) & 255) == 0) -#endif - -int -main () -{ - int s; - wait (&s); - s = WIFEXITED (s) ? WEXITSTATUS (s) : 1; - ; - return 0; -} -_ACEOF -rm -f conftest.$ac_objext -if { (eval echo "$as_me:$LINENO: \"$ac_compile\"") >&5 - (eval $ac_compile) 2>conftest.er1 - ac_status=$? - grep -v '^ *+' conftest.er1 >conftest.err - rm -f conftest.er1 - cat conftest.err >&5 - echo "$as_me:$LINENO: \$? = $ac_status" >&5 - (exit $ac_status); } && - { ac_try='test -z "$ac_c_werror_flag" - || test ! -s conftest.err' - { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5 - (eval $ac_try) 2>&5 - ac_status=$? - echo "$as_me:$LINENO: \$? = $ac_status" >&5 - (exit $ac_status); }; } && - { ac_try='test -s conftest.$ac_objext' - { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5 - (eval $ac_try) 2>&5 - ac_status=$? - echo "$as_me:$LINENO: \$? = $ac_status" >&5 - (exit $ac_status); }; }; then - ac_cv_header_sys_wait_h=yes -else - echo "$as_me: failed program was:" >&5 -sed 's/^/| /' conftest.$ac_ext >&5 - -ac_cv_header_sys_wait_h=no -fi -rm -f conftest.err conftest.$ac_objext conftest.$ac_ext -fi -echo "$as_me:$LINENO: result: $ac_cv_header_sys_wait_h" >&5 -echo "${ECHO_T}$ac_cv_header_sys_wait_h" >&6 -if test $ac_cv_header_sys_wait_h = yes; then - -cat >>confdefs.h <<\_ACEOF -#define HAVE_SYS_WAIT_H 1 -_ACEOF - -fi - - -echo "$as_me:$LINENO: checking for compiler -Wl,-R option" >&5 -echo $ECHO_N "checking for compiler -Wl,-R option... $ECHO_C" >&6 -if test "${llvm_cv_link_use_r+set}" = set; then - echo $ECHO_N "(cached) $ECHO_C" >&6 -else - ac_ext=c -ac_cpp='$CPP $CPPFLAGS' -ac_compile='$CC -c $CFLAGS $CPPFLAGS conftest.$ac_ext >&5' -ac_link='$CC -o conftest$ac_exeext $CFLAGS $CPPFLAGS $LDFLAGS conftest.$ac_ext $LIBS >&5' -ac_compiler_gnu=$ac_cv_c_compiler_gnu - - oldcflags="$CFLAGS" - CFLAGS="$CFLAGS -Wl,-R." - cat >conftest.$ac_ext <<_ACEOF -/* confdefs.h. */ -_ACEOF -cat confdefs.h >>conftest.$ac_ext -cat >>conftest.$ac_ext <<_ACEOF -/* end confdefs.h. */ - -int -main () -{ -int main() { return 0; } - ; - return 0; -} -_ACEOF -rm -f conftest.$ac_objext conftest$ac_exeext -if { (eval echo "$as_me:$LINENO: \"$ac_link\"") >&5 - (eval $ac_link) 2>conftest.er1 - ac_status=$? - grep -v '^ *+' conftest.er1 >conftest.err - rm -f conftest.er1 - cat conftest.err >&5 - echo "$as_me:$LINENO: \$? = $ac_status" >&5 - (exit $ac_status); } && - { ac_try='test -z "$ac_c_werror_flag" - || test ! -s conftest.err' - { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5 - (eval $ac_try) 2>&5 - ac_status=$? - echo "$as_me:$LINENO: \$? = $ac_status" >&5 - (exit $ac_status); }; } && - { ac_try='test -s conftest$ac_exeext' - { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5 - (eval $ac_try) 2>&5 - ac_status=$? - echo "$as_me:$LINENO: \$? = $ac_status" >&5 - (exit $ac_status); }; }; then - llvm_cv_link_use_r=yes -else - echo "$as_me: failed program was:" >&5 -sed 's/^/| /' conftest.$ac_ext >&5 - -llvm_cv_link_use_r=no -fi -rm -f conftest.err conftest.$ac_objext \ - conftest$ac_exeext conftest.$ac_ext - CFLAGS="$oldcflags" - ac_ext=c -ac_cpp='$CPP $CPPFLAGS' -ac_compile='$CC -c $CFLAGS $CPPFLAGS conftest.$ac_ext >&5' -ac_link='$CC -o conftest$ac_exeext $CFLAGS $CPPFLAGS $LDFLAGS conftest.$ac_ext $LIBS >&5' -ac_compiler_gnu=$ac_cv_c_compiler_gnu - - -fi -echo "$as_me:$LINENO: result: $llvm_cv_link_use_r" >&5 -echo "${ECHO_T}$llvm_cv_link_use_r" >&6 -if test "$llvm_cv_link_use_r" = yes ; then - -cat >>confdefs.h <<\_ACEOF -#define HAVE_LINK_R 1 -_ACEOF - - fi - - -echo "$as_me:$LINENO: checking for re_comp" >&5 -echo $ECHO_N "checking for re_comp... $ECHO_C" >&6 -if test "${ac_cv_func_re_comp+set}" = set; then - echo $ECHO_N "(cached) $ECHO_C" >&6 -else - cat >conftest.$ac_ext <<_ACEOF -/* confdefs.h. */ -_ACEOF -cat confdefs.h >>conftest.$ac_ext -cat >>conftest.$ac_ext <<_ACEOF -/* end confdefs.h. */ -/* Define re_comp to an innocuous variant, in case declares re_comp. - For example, HP-UX 11i declares gettimeofday. */ -#define re_comp innocuous_re_comp - -/* System header to define __stub macros and hopefully few prototypes, - which can conflict with char re_comp (); below. - Prefer to if __STDC__ is defined, since - exists even on freestanding compilers. */ - -#ifdef __STDC__ -# include -#else -# include -#endif - -#undef re_comp - -/* Override any gcc2 internal prototype to avoid an error. */ -#ifdef __cplusplus -extern "C" -{ -#endif -/* We use char because int might match the return type of a gcc2 - builtin and then its argument prototype would still apply. */ -char re_comp (); -/* The GNU C library defines this for functions which it implements - to always fail with ENOSYS. Some functions are actually named - something starting with __ and the normal name is an alias. */ -#if defined (__stub_re_comp) || defined (__stub___re_comp) -choke me -#else -char (*f) () = re_comp; + echo $ECHO_N "(cached) $ECHO_C" >&6 +else + cat >conftest.$ac_ext <<_ACEOF +/* confdefs.h. */ +_ACEOF +cat confdefs.h >>conftest.$ac_ext +cat >>conftest.$ac_ext <<_ACEOF +/* end confdefs.h. */ +#include +#include +#ifndef WEXITSTATUS +# define WEXITSTATUS(stat_val) ((unsigned)(stat_val) >> 8) #endif -#ifdef __cplusplus -} +#ifndef WIFEXITED +# define WIFEXITED(stat_val) (((stat_val) & 255) == 0) #endif int main () { -return f != re_comp; + int s; + wait (&s); + s = WIFEXITED (s) ? WEXITSTATUS (s) : 1; ; return 0; } _ACEOF -rm -f conftest.$ac_objext conftest$ac_exeext -if { (eval echo "$as_me:$LINENO: \"$ac_link\"") >&5 - (eval $ac_link) 2>conftest.er1 +rm -f conftest.$ac_objext +if { (eval echo "$as_me:$LINENO: \"$ac_compile\"") >&5 + (eval $ac_compile) 2>conftest.er1 ac_status=$? grep -v '^ *+' conftest.er1 >conftest.err rm -f conftest.er1 @@ -19694,361 +19866,208 @@ ac_status=$? echo "$as_me:$LINENO: \$? = $ac_status" >&5 (exit $ac_status); }; } && - { ac_try='test -s conftest$ac_exeext' + { ac_try='test -s conftest.$ac_objext' { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5 (eval $ac_try) 2>&5 ac_status=$? echo "$as_me:$LINENO: \$? = $ac_status" >&5 (exit $ac_status); }; }; then - ac_cv_func_re_comp=yes + ac_cv_header_sys_wait_h=yes else echo "$as_me: failed program was:" >&5 sed 's/^/| /' conftest.$ac_ext >&5 -ac_cv_func_re_comp=no -fi -rm -f conftest.err conftest.$ac_objext \ - conftest$ac_exeext conftest.$ac_ext -fi -echo "$as_me:$LINENO: result: $ac_cv_func_re_comp" >&5 -echo "${ECHO_T}$ac_cv_func_re_comp" >&6 -if test $ac_cv_func_re_comp = yes; then - HAVE_RE_COMP=HAVE_RE_COMP:=1 - -else - HAVE_RE_COMP= - +ac_cv_header_sys_wait_h=no fi +rm -f conftest.err conftest.$ac_objext conftest.$ac_ext +fi +echo "$as_me:$LINENO: result: $ac_cv_header_sys_wait_h" >&5 +echo "${ECHO_T}$ac_cv_header_sys_wait_h" >&6 +if test $ac_cv_header_sys_wait_h = yes; then +cat >>confdefs.h <<\_ACEOF +#define HAVE_SYS_WAIT_H 1 +_ACEOF +fi - # Check whether --enable-spec95 or --disable-spec95 was given. -if test "${enable_spec95+set}" = set; then - enableval="$enable_spec95" - checkresult=$enableval -else - checkresult=auto -fi; -echo "$as_me:$LINENO: checking for spec95 benchmark sources" >&5 -echo $ECHO_N "checking for spec95 benchmark sources... $ECHO_C" >&6 -case "$checkresult" in -auto|yes) - defaultdir=/home/vadve/shared/benchmarks/spec95/benchspec - if test -d "$defaultdir" - then - SPEC95_ROOT=$defaultdir - - USE_SPEC95=USE_SPEC95=1 - - checkresult="yes, found in $defaultdir" - else - checkresult=no - fi - ;; -no) - - - checkresult=no - ;; -*) if test -d "$checkresult" - then - SPEC95_ROOT="$checkresult" - - USE_SPEC95=USE_SPEC95=1 - - checkresult="yes, in $checkresult" - else - - - checkresult="no, not found in $checkresult" - fi - ;; -esac -echo "$as_me:$LINENO: result: $checkresult" >&5 -echo "${ECHO_T}$checkresult" >&6 - - - - # Check whether --enable-spec2000 or --disable-spec2000 was given. -if test "${enable_spec2000+set}" = set; then - enableval="$enable_spec2000" - checkresult=$enableval -else - checkresult=auto -fi; -echo "$as_me:$LINENO: checking for spec2000 benchmark sources" >&5 -echo $ECHO_N "checking for spec2000 benchmark sources... $ECHO_C" >&6 -case "$checkresult" in -auto|yes) - defaultdir=/home/vadve/shared/benchmarks/speccpu2000/benchspec - if test -d "$defaultdir" - then - SPEC2000_ROOT=$defaultdir - - USE_SPEC2000=USE_SPEC2000=1 - - checkresult="yes, found in $defaultdir" - else - checkresult=no - fi - ;; -no) - - - checkresult=no - ;; -*) if test -d "$checkresult" - then - SPEC2000_ROOT="$checkresult" - - USE_SPEC2000=USE_SPEC2000=1 - - checkresult="yes, in $checkresult" - else - - - checkresult="no, not found in $checkresult" - fi - ;; -esac -echo "$as_me:$LINENO: result: $checkresult" >&5 -echo "${ECHO_T}$checkresult" >&6 - - - - # Check whether --enable-povray or --disable-povray was given. -if test "${enable_povray+set}" = set; then - enableval="$enable_povray" - checkresult=$enableval -else - checkresult=auto -fi; -echo "$as_me:$LINENO: checking for povray benchmark sources" >&5 -echo $ECHO_N "checking for povray benchmark sources... $ECHO_C" >&6 -case "$checkresult" in -auto|yes) - defaultdir=/home/vadve/shared/benchmarks/povray31 - if test -d "$defaultdir" - then - POVRAY_ROOT=$defaultdir - - USE_POVRAY=USE_POVRAY=1 - - checkresult="yes, found in $defaultdir" - else - checkresult=no - fi - ;; -no) - - - checkresult=no - ;; -*) if test -d "$checkresult" - then - POVRAY_ROOT="$checkresult" - - USE_POVRAY=USE_POVRAY=1 - - checkresult="yes, in $checkresult" - else - - - checkresult="no, not found in $checkresult" - fi - ;; -esac -echo "$as_me:$LINENO: result: $checkresult" >&5 -echo "${ECHO_T}$checkresult" >&6 - - - - # Check whether --enable-namd or --disable-namd was given. -if test "${enable_namd+set}" = set; then - enableval="$enable_namd" - checkresult=$enableval -else - checkresult=auto -fi; -echo "$as_me:$LINENO: checking for namd benchmark sources" >&5 -echo $ECHO_N "checking for namd benchmark sources... $ECHO_C" >&6 -case "$checkresult" in -auto|yes) - defaultdir=/home/vadve/shared/benchmarks/spec_namd - if test -d "$defaultdir" - then - NAMD_ROOT=$defaultdir - - USE_NAMD=USE_NAMD=1 - - checkresult="yes, found in $defaultdir" - else - checkresult=no - fi - ;; -no) - - - checkresult=no - ;; -*) if test -d "$checkresult" - then - NAMD_ROOT="$checkresult" - - USE_NAMD=USE_NAMD=1 - - checkresult="yes, in $checkresult" - else - - - checkresult="no, not found in $checkresult" - fi - ;; -esac -echo "$as_me:$LINENO: result: $checkresult" >&5 -echo "${ECHO_T}$checkresult" >&6 - - - - # Check whether --enable-sweep3d or --disable-sweep3d was given. -if test "${enable_sweep3d+set}" = set; then - enableval="$enable_sweep3d" - checkresult=$enableval -else - checkresult=auto -fi; -echo "$as_me:$LINENO: checking for sweep3d benchmark sources" >&5 -echo $ECHO_N "checking for sweep3d benchmark sources... $ECHO_C" >&6 -case "$checkresult" in -auto|yes) - defaultdir=/home/vadve/criswell/umt2k - if test -d "$defaultdir" - then - SWEEP3D_ROOT=$defaultdir - - USE_SWEEP3D=USE_SWEEP3D=1 - - checkresult="yes, found in $defaultdir" - else - checkresult=no - fi - ;; -no) - - - checkresult=no - ;; -*) if test -d "$checkresult" - then - SWEEP3D_ROOT="$checkresult" - - USE_SWEEP3D=USE_SWEEP3D=1 - - checkresult="yes, in $checkresult" - else - - - checkresult="no, not found in $checkresult" - fi - ;; -esac -echo "$as_me:$LINENO: result: $checkresult" >&5 -echo "${ECHO_T}$checkresult" >&6 - - - - # Check whether --enable-fpgrowth or --disable-fpgrowth was given. -if test "${enable_fpgrowth+set}" = set; then - enableval="$enable_fpgrowth" - checkresult=$enableval -else - checkresult=auto -fi; -echo "$as_me:$LINENO: checking for fpgrowth benchmark sources" >&5 -echo $ECHO_N "checking for fpgrowth benchmark sources... $ECHO_C" >&6 -case "$checkresult" in -auto|yes) - defaultdir=/home/vadve/shared/benchmarks/fpgrowth - if test -d "$defaultdir" - then - FPGROWTH_ROOT=$defaultdir - - USE_FPGROWTH=USE_FPGROWTH=1 - checkresult="yes, found in $defaultdir" - else - checkresult=no - fi - ;; -no) +echo "$as_me:$LINENO: checking for compiler -Wl,-R option" >&5 +echo $ECHO_N "checking for compiler -Wl,-R option... $ECHO_C" >&6 +if test "${llvm_cv_link_use_r+set}" = set; then + echo $ECHO_N "(cached) $ECHO_C" >&6 +else + ac_ext=c +ac_cpp='$CPP $CPPFLAGS' +ac_compile='$CC -c $CFLAGS $CPPFLAGS conftest.$ac_ext >&5' +ac_link='$CC -o conftest$ac_exeext $CFLAGS $CPPFLAGS $LDFLAGS conftest.$ac_ext $LIBS >&5' +ac_compiler_gnu=$ac_cv_c_compiler_gnu + oldcflags="$CFLAGS" + CFLAGS="$CFLAGS -Wl,-R." + cat >conftest.$ac_ext <<_ACEOF +/* confdefs.h. */ +_ACEOF +cat confdefs.h >>conftest.$ac_ext +cat >>conftest.$ac_ext <<_ACEOF +/* end confdefs.h. */ - checkresult=no - ;; -*) if test -d "$checkresult" - then - FPGROWTH_ROOT="$checkresult" +int +main () +{ +int main() { return 0; } + ; + return 0; +} +_ACEOF +rm -f conftest.$ac_objext conftest$ac_exeext +if { (eval echo "$as_me:$LINENO: \"$ac_link\"") >&5 + (eval $ac_link) 2>conftest.er1 + ac_status=$? + grep -v '^ *+' conftest.er1 >conftest.err + rm -f conftest.er1 + cat conftest.err >&5 + echo "$as_me:$LINENO: \$? = $ac_status" >&5 + (exit $ac_status); } && + { ac_try='test -z "$ac_c_werror_flag" + || test ! -s conftest.err' + { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5 + (eval $ac_try) 2>&5 + ac_status=$? + echo "$as_me:$LINENO: \$? = $ac_status" >&5 + (exit $ac_status); }; } && + { ac_try='test -s conftest$ac_exeext' + { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5 + (eval $ac_try) 2>&5 + ac_status=$? + echo "$as_me:$LINENO: \$? = $ac_status" >&5 + (exit $ac_status); }; }; then + llvm_cv_link_use_r=yes +else + echo "$as_me: failed program was:" >&5 +sed 's/^/| /' conftest.$ac_ext >&5 - USE_FPGROWTH=USE_FPGROWTH=1 +llvm_cv_link_use_r=no +fi +rm -f conftest.err conftest.$ac_objext \ + conftest$ac_exeext conftest.$ac_ext + CFLAGS="$oldcflags" + ac_ext=c +ac_cpp='$CPP $CPPFLAGS' +ac_compile='$CC -c $CFLAGS $CPPFLAGS conftest.$ac_ext >&5' +ac_link='$CC -o conftest$ac_exeext $CFLAGS $CPPFLAGS $LDFLAGS conftest.$ac_ext $LIBS >&5' +ac_compiler_gnu=$ac_cv_c_compiler_gnu - checkresult="yes, in $checkresult" - else +fi +echo "$as_me:$LINENO: result: $llvm_cv_link_use_r" >&5 +echo "${ECHO_T}$llvm_cv_link_use_r" >&6 +if test "$llvm_cv_link_use_r" = yes ; then - checkresult="no, not found in $checkresult" - fi - ;; -esac -echo "$as_me:$LINENO: result: $checkresult" >&5 -echo "${ECHO_T}$checkresult" >&6 +cat >>confdefs.h <<\_ACEOF +#define HAVE_LINK_R 1 +_ACEOF + fi - # Check whether --enable-alp or --disable-alp was given. -if test "${enable_alp+set}" = set; then - enableval="$enable_alp" - checkresult=$enableval +echo "$as_me:$LINENO: checking for re_comp" >&5 +echo $ECHO_N "checking for re_comp... $ECHO_C" >&6 +if test "${ac_cv_func_re_comp+set}" = set; then + echo $ECHO_N "(cached) $ECHO_C" >&6 else - checkresult=auto -fi; -echo "$as_me:$LINENO: checking for alp benchmark sources" >&5 -echo $ECHO_N "checking for alp benchmark sources... $ECHO_C" >&6 -case "$checkresult" in -auto|yes) - defaultdir=/home/vadve/shared/benchmarks/ALP - if test -d "$defaultdir" - then - ALP_ROOT=$defaultdir - - USE_ALP=USE_ALP=1 + cat >conftest.$ac_ext <<_ACEOF +/* confdefs.h. */ +_ACEOF +cat confdefs.h >>conftest.$ac_ext +cat >>conftest.$ac_ext <<_ACEOF +/* end confdefs.h. */ +/* Define re_comp to an innocuous variant, in case declares re_comp. + For example, HP-UX 11i declares gettimeofday. */ +#define re_comp innocuous_re_comp - checkresult="yes, found in $defaultdir" - else - checkresult=no - fi - ;; -no) +/* System header to define __stub macros and hopefully few prototypes, + which can conflict with char re_comp (); below. + Prefer to if __STDC__ is defined, since + exists even on freestanding compilers. */ +#ifdef __STDC__ +# include +#else +# include +#endif - checkresult=no - ;; -*) if test -d "$checkresult" - then - ALP_ROOT="$checkresult" +#undef re_comp - USE_ALP=USE_ALP=1 +/* Override any gcc2 internal prototype to avoid an error. */ +#ifdef __cplusplus +extern "C" +{ +#endif +/* We use char because int might match the return type of a gcc2 + builtin and then its argument prototype would still apply. */ +char re_comp (); +/* The GNU C library defines this for functions which it implements + to always fail with ENOSYS. Some functions are actually named + something starting with __ and the normal name is an alias. */ +#if defined (__stub_re_comp) || defined (__stub___re_comp) +choke me +#else +char (*f) () = re_comp; +#endif +#ifdef __cplusplus +} +#endif - checkresult="yes, in $checkresult" - else +int +main () +{ +return f != re_comp; + ; + return 0; +} +_ACEOF +rm -f conftest.$ac_objext conftest$ac_exeext +if { (eval echo "$as_me:$LINENO: \"$ac_link\"") >&5 + (eval $ac_link) 2>conftest.er1 + ac_status=$? + grep -v '^ *+' conftest.er1 >conftest.err + rm -f conftest.er1 + cat conftest.err >&5 + echo "$as_me:$LINENO: \$? = $ac_status" >&5 + (exit $ac_status); } && + { ac_try='test -z "$ac_c_werror_flag" + || test ! -s conftest.err' + { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5 + (eval $ac_try) 2>&5 + ac_status=$? + echo "$as_me:$LINENO: \$? = $ac_status" >&5 + (exit $ac_status); }; } && + { ac_try='test -s conftest$ac_exeext' + { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5 + (eval $ac_try) 2>&5 + ac_status=$? + echo "$as_me:$LINENO: \$? = $ac_status" >&5 + (exit $ac_status); }; }; then + ac_cv_func_re_comp=yes +else + echo "$as_me: failed program was:" >&5 +sed 's/^/| /' conftest.$ac_ext >&5 +ac_cv_func_re_comp=no +fi +rm -f conftest.err conftest.$ac_objext \ + conftest$ac_exeext conftest.$ac_ext +fi +echo "$as_me:$LINENO: result: $ac_cv_func_re_comp" >&5 +echo "${ECHO_T}$ac_cv_func_re_comp" >&6 +if test $ac_cv_func_re_comp = yes; then + HAVE_RE_COMP=HAVE_RE_COMP:=1 - checkresult="no, not found in $checkresult" - fi - ;; -esac -echo "$as_me:$LINENO: result: $checkresult" >&5 -echo "${ECHO_T}$checkresult" >&6 +else + HAVE_RE_COMP= +fi cat >confcache <<\_ACEOF @@ -20732,6 +20751,21 @@ s, at LIBS@,$LIBS,;t t s, at LLVM_SRC@,$LLVM_SRC,;t t s, at LLVM_OBJ@,$LLVM_OBJ,;t t +s, at LLVM_EXTERNALS@,$LLVM_EXTERNALS,;t t +s, at SPEC95_ROOT@,$SPEC95_ROOT,;t t +s, at USE_SPEC95@,$USE_SPEC95,;t t +s, at SPEC2000_ROOT@,$SPEC2000_ROOT,;t t +s, at USE_SPEC2000@,$USE_SPEC2000,;t t +s, at POVRAY_ROOT@,$POVRAY_ROOT,;t t +s, at USE_POVRAY@,$USE_POVRAY,;t t +s, at NAMD_ROOT@,$NAMD_ROOT,;t t +s, at USE_NAMD@,$USE_NAMD,;t t +s, at SWEEP3D_ROOT@,$SWEEP3D_ROOT,;t t +s, at USE_SWEEP3D@,$USE_SWEEP3D,;t t +s, at FPGROWTH_ROOT@,$FPGROWTH_ROOT,;t t +s, at USE_FPGROWTH@,$USE_FPGROWTH,;t t +s, at ALP_ROOT@,$ALP_ROOT,;t t +s, at USE_ALP@,$USE_ALP,;t t s, at DISABLE_LLC_DIFFS@,$DISABLE_LLC_DIFFS,;t t s, at CXX@,$CXX,;t t s, at CXXFLAGS@,$CXXFLAGS,;t t @@ -20786,20 +20820,6 @@ s, at F95_INC@,$F95_INC,;t t s, at F95_LIB@,$F95_LIB,;t t s, at HAVE_RE_COMP@,$HAVE_RE_COMP,;t t -s, at SPEC95_ROOT@,$SPEC95_ROOT,;t t -s, at USE_SPEC95@,$USE_SPEC95,;t t -s, at SPEC2000_ROOT@,$SPEC2000_ROOT,;t t -s, at USE_SPEC2000@,$USE_SPEC2000,;t t -s, at POVRAY_ROOT@,$POVRAY_ROOT,;t t -s, at USE_POVRAY@,$USE_POVRAY,;t t -s, at NAMD_ROOT@,$NAMD_ROOT,;t t -s, at USE_NAMD@,$USE_NAMD,;t t -s, at SWEEP3D_ROOT@,$SWEEP3D_ROOT,;t t -s, at USE_SWEEP3D@,$USE_SWEEP3D,;t t -s, at FPGROWTH_ROOT@,$FPGROWTH_ROOT,;t t -s, at USE_FPGROWTH@,$USE_FPGROWTH,;t t -s, at ALP_ROOT@,$ALP_ROOT,;t t -s, at USE_ALP@,$USE_ALP,;t t s, at LIBOBJS@,$LIBOBJS,;t t s, at LTLIBOBJS@,$LTLIBOBJS,;t t CEOF From llvm at cs.uiuc.edu Fri Apr 7 14:53:32 2006 From: llvm at cs.uiuc.edu (LLVM) Date: Fri, 7 Apr 2006 14:53:32 -0500 Subject: [llvm-commits] CVS: llvm/make/ Message-ID: <200604071953.OAA16614@zion.cs.uiuc.edu> Changes in directory llvm/make: --- Log message: Directory /var/cvs/llvm/llvm/make added to the repository --- Diffs of the changes: (+0 -0) 0 files changed From jlaskey at apple.com Fri Apr 7 15:44:55 2006 From: jlaskey at apple.com (Jim Laskey) Date: Fri, 7 Apr 2006 15:44:55 -0500 Subject: [llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp Message-ID: <200604072044.PAA17311@zion.cs.uiuc.edu> Changes in directory llvm/lib/Target/PowerPC: PPCAsmPrinter.cpp updated: 1.162 -> 1.163 --- Log message: Make sure that debug labels are defined within the same section and after the entry point of a function. --- Diffs of the changes: (+3 -3) PPCAsmPrinter.cpp | 6 +++--- 1 files changed, 3 insertions(+), 3 deletions(-) Index: llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp diff -u llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp:1.162 llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp:1.163 --- llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp:1.162 Sat Mar 25 00:12:06 2006 +++ llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp Fri Apr 7 15:44:42 2006 @@ -511,9 +511,6 @@ SetupMachineFunction(MF); O << "\n\n"; - // Emit pre-function debug information. - DW.BeginFunction(&MF); - // Print out constants referenced by the function EmitConstantPool(MF.getConstantPool()); @@ -539,6 +536,9 @@ EmitAlignment(4, F); O << CurrentFnName << ":\n"; + // Emit pre-function debug information. + DW.BeginFunction(&MF); + // Print out code for the function. for (MachineFunction::const_iterator I = MF.begin(), E = MF.end(); I != E; ++I) { From jlaskey at apple.com Fri Apr 7 15:44:56 2006 From: jlaskey at apple.com (Jim Laskey) Date: Fri, 7 Apr 2006 15:44:56 -0500 Subject: [llvm-commits] CVS: llvm/lib/Target/X86/X86ATTAsmPrinter.cpp X86IntelAsmPrinter.cpp Message-ID: <200604072044.PAA17317@zion.cs.uiuc.edu> Changes in directory llvm/lib/Target/X86: X86ATTAsmPrinter.cpp updated: 1.32 -> 1.33 X86IntelAsmPrinter.cpp updated: 1.25 -> 1.26 --- Log message: Make sure that debug labels are defined within the same section and after the entry point of a function. --- Diffs of the changes: (+10 -10) X86ATTAsmPrinter.cpp | 10 +++++----- X86IntelAsmPrinter.cpp | 10 +++++----- 2 files changed, 10 insertions(+), 10 deletions(-) Index: llvm/lib/Target/X86/X86ATTAsmPrinter.cpp diff -u llvm/lib/Target/X86/X86ATTAsmPrinter.cpp:1.32 llvm/lib/Target/X86/X86ATTAsmPrinter.cpp:1.33 --- llvm/lib/Target/X86/X86ATTAsmPrinter.cpp:1.32 Thu Mar 23 12:09:44 2006 +++ llvm/lib/Target/X86/X86ATTAsmPrinter.cpp Fri Apr 7 15:44:42 2006 @@ -35,11 +35,6 @@ SetupMachineFunction(MF); O << "\n\n"; - if (forDarwin) { - // Emit pre-function debug information. - DW.BeginFunction(&MF); - } - // Print out constants referenced by the function EmitConstantPool(MF.getConstantPool()); @@ -73,6 +68,11 @@ } O << CurrentFnName << ":\n"; + if (forDarwin) { + // Emit pre-function debug information. + DW.BeginFunction(&MF); + } + // Print out code for the function. for (MachineFunction::const_iterator I = MF.begin(), E = MF.end(); I != E; ++I) { Index: llvm/lib/Target/X86/X86IntelAsmPrinter.cpp diff -u llvm/lib/Target/X86/X86IntelAsmPrinter.cpp:1.25 llvm/lib/Target/X86/X86IntelAsmPrinter.cpp:1.26 --- llvm/lib/Target/X86/X86IntelAsmPrinter.cpp:1.25 Thu Mar 23 12:09:44 2006 +++ llvm/lib/Target/X86/X86IntelAsmPrinter.cpp Fri Apr 7 15:44:42 2006 @@ -34,11 +34,6 @@ SetupMachineFunction(MF); O << "\n\n"; - if (forDarwin) { - // Emit pre-function debug information. - DW.BeginFunction(&MF); - } - // Print out constants referenced by the function EmitConstantPool(MF.getConstantPool()); @@ -49,6 +44,11 @@ if (HasDotTypeDotSizeDirective) O << "\t.type\t" << CurrentFnName << ", @function\n"; O << CurrentFnName << ":\n"; + + if (forDarwin) { + // Emit pre-function debug information. + DW.BeginFunction(&MF); + } // Print out code for the function. for (MachineFunction::const_iterator I = MF.begin(), E = MF.end(); From jlaskey at apple.com Fri Apr 7 15:44:57 2006 From: jlaskey at apple.com (Jim Laskey) Date: Fri, 7 Apr 2006 15:44:57 -0500 Subject: [llvm-commits] CVS: llvm/lib/CodeGen/DwarfWriter.cpp Message-ID: <200604072044.PAA17325@zion.cs.uiuc.edu> Changes in directory llvm/lib/CodeGen: DwarfWriter.cpp updated: 1.54 -> 1.55 --- Log message: Make sure that debug labels are defined within the same section and after the entry point of a function. --- Diffs of the changes: (+5 -8) DwarfWriter.cpp | 13 +++++-------- 1 files changed, 5 insertions(+), 8 deletions(-) Index: llvm/lib/CodeGen/DwarfWriter.cpp diff -u llvm/lib/CodeGen/DwarfWriter.cpp:1.54 llvm/lib/CodeGen/DwarfWriter.cpp:1.55 --- llvm/lib/CodeGen/DwarfWriter.cpp:1.54 Fri Apr 7 11:34:45 2006 +++ llvm/lib/CodeGen/DwarfWriter.cpp Fri Apr 7 15:44:42 2006 @@ -1626,15 +1626,13 @@ CompileUnitDesc *UnitDesc = static_cast(SPD->getContext()); CompileUnit *Unit = FindCompileUnit(UnitDesc); - // Generate the mangled name. - std::string MangledName = Asm->Mang->getValueName(MF->getFunction()); - // Get the subprogram die. DIE *SPDie = Unit->getDieMapSlotFor(SPD); assert(SPDie && "Missing subprogram descriptor"); // Add the function bounds. - SPDie->AddObjectLabel(DW_AT_low_pc, DW_FORM_addr, MangledName); + SPDie->AddLabel(DW_AT_low_pc, DW_FORM_addr, + DWLabel("func_begin", SubprogramCount)); SPDie->AddLabel(DW_AT_high_pc, DW_FORM_addr, DWLabel("func_end", SubprogramCount)); MachineLocation Location(RI->getFrameRegister(*MF)); @@ -2408,8 +2406,8 @@ EmitDebugMacInfo(); } -/// BeginFunction - Gather pre-function debug information. -/// +/// BeginFunction - Gather pre-function debug information. Assumes being +/// emitted immediately after the function entry point. void DwarfWriter::BeginFunction(MachineFunction *MF) { this->MF = MF; @@ -2419,8 +2417,7 @@ if (!ShouldEmitDwarf()) return; EOL("Dwarf Begin Function"); - // Define begin label for subprogram. - Asm->SwitchSection(TextSection, 0); + // Assumes in correct section after the entry point. EmitLabel("func_begin", ++SubprogramCount); } From jlaskey at apple.com Fri Apr 7 15:44:57 2006 From: jlaskey at apple.com (Jim Laskey) Date: Fri, 7 Apr 2006 15:44:57 -0500 Subject: [llvm-commits] CVS: llvm/include/llvm/CodeGen/DwarfWriter.h Message-ID: <200604072044.PAA17321@zion.cs.uiuc.edu> Changes in directory llvm/include/llvm/CodeGen: DwarfWriter.h updated: 1.33 -> 1.34 --- Log message: Make sure that debug labels are defined within the same section and after the entry point of a function. --- Diffs of the changes: (+2 -2) DwarfWriter.h | 4 ++-- 1 files changed, 2 insertions(+), 2 deletions(-) Index: llvm/include/llvm/CodeGen/DwarfWriter.h diff -u llvm/include/llvm/CodeGen/DwarfWriter.h:1.33 llvm/include/llvm/CodeGen/DwarfWriter.h:1.34 --- llvm/include/llvm/CodeGen/DwarfWriter.h:1.33 Fri Apr 7 11:34:45 2006 +++ llvm/include/llvm/CodeGen/DwarfWriter.h Fri Apr 7 15:44:42 2006 @@ -472,8 +472,8 @@ /// void EndModule(); - /// BeginFunction - Gather pre-function debug information. - /// + /// BeginFunction - Gather pre-function debug information. Assumes being + /// emitted immediately after the function entry point. void BeginFunction(MachineFunction *MF); /// EndFunction - Gather and emit post-function debug information. From evan.cheng at apple.com Fri Apr 7 16:18:52 2006 From: evan.cheng at apple.com (Evan Cheng) Date: Fri, 7 Apr 2006 16:18:52 -0500 Subject: [llvm-commits] CVS: llvm/include/llvm/IntrinsicsX86.td Message-ID: <200604072118.QAA17515@zion.cs.uiuc.edu> Changes in directory llvm/include/llvm: IntrinsicsX86.td updated: 1.11 -> 1.12 --- Log message: Remove int_x86_sse_storeh_ps and int_x86_sse_storel_ps. These are now lowered by the frontend. --- Diffs of the changes: (+0 -4) IntrinsicsX86.td | 4 ---- 1 files changed, 4 deletions(-) Index: llvm/include/llvm/IntrinsicsX86.td diff -u llvm/include/llvm/IntrinsicsX86.td:1.11 llvm/include/llvm/IntrinsicsX86.td:1.12 --- llvm/include/llvm/IntrinsicsX86.td:1.11 Thu Apr 6 18:25:41 2006 +++ llvm/include/llvm/IntrinsicsX86.td Fri Apr 7 16:18:40 2006 @@ -132,10 +132,6 @@ // SIMD store ops let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.". - def int_x86_sse_storeh_ps : GCCBuiltin<"__builtin_ia32_storehps">, - Intrinsic<[llvm_ptr_ty, llvm_v4f32_ty], [IntrWriteMem]>; - def int_x86_sse_storel_ps : GCCBuiltin<"__builtin_ia32_storelps">, - Intrinsic<[llvm_ptr_ty, llvm_v4f32_ty], [IntrWriteMem]>; def int_x86_sse_storeu_ps : GCCBuiltin<"__builtin_ia32_storeups">, Intrinsic<[llvm_ptr_ty, llvm_v4f32_ty], [IntrWriteMem]>; } From evan.cheng at apple.com Fri Apr 7 16:20:06 2006 From: evan.cheng at apple.com (Evan Cheng) Date: Fri, 7 Apr 2006 16:20:06 -0500 Subject: [llvm-commits] CVS: llvm/lib/Target/X86/README.txt Message-ID: <200604072120.QAA17557@zion.cs.uiuc.edu> Changes in directory llvm/lib/Target/X86: README.txt updated: 1.80 -> 1.81 --- Log message: Keep track of an Mac OS X / x86 ABI bug. --- Diffs of the changes: (+5 -0) README.txt | 5 +++++ 1 files changed, 5 insertions(+) Index: llvm/lib/Target/X86/README.txt diff -u llvm/lib/Target/X86/README.txt:1.80 llvm/lib/Target/X86/README.txt:1.81 --- llvm/lib/Target/X86/README.txt:1.80 Thu Apr 6 18:21:24 2006 +++ llvm/lib/Target/X86/README.txt Fri Apr 7 16:19:53 2006 @@ -760,3 +760,8 @@ movddup 8(%esp), %xmm0 movapd %xmm0, (%eax) ret + +//===---------------------------------------------------------------------===// + +A Mac OS X IA-32 specific ABI bug wrt returning value > 8 bytes: +http://llvm.org/bugs/show_bug.cgi?id=729 From evan.cheng at apple.com Fri Apr 7 16:21:11 2006 From: evan.cheng at apple.com (Evan Cheng) Date: Fri, 7 Apr 2006 16:21:11 -0500 Subject: [llvm-commits] CVS: llvm/lib/Target/X86/X86InstrSSE.td Message-ID: <200604072121.QAA17574@zion.cs.uiuc.edu> Changes in directory llvm/lib/Target/X86: X86InstrSSE.td updated: 1.66 -> 1.67 --- Log message: Added patterns for MOVHPSmr and MOVLPSmr. --- Diffs of the changes: (+42 -4) X86InstrSSE.td | 46 ++++++++++++++++++++++++++++++++++++++++++---- 1 files changed, 42 insertions(+), 4 deletions(-) Index: llvm/lib/Target/X86/X86InstrSSE.td diff -u llvm/lib/Target/X86/X86InstrSSE.td:1.66 llvm/lib/Target/X86/X86InstrSSE.td:1.67 --- llvm/lib/Target/X86/X86InstrSSE.td:1.66 Thu Apr 6 18:53:29 2006 +++ llvm/lib/Target/X86/X86InstrSSE.td Fri Apr 7 16:20:58 2006 @@ -746,14 +746,23 @@ } def MOVLPSmr : PSI<0x13, MRMDestMem, (ops f64mem:$dst, VR128:$src), - "movlps {$src, $dst|$dst, $src}", []>; + "movlps {$src, $dst|$dst, $src}", + [(store (f64 (vector_extract (bc_v2f64 (v4f32 VR128:$src)), + (i32 0))), addr:$dst)]>; def MOVLPDmr : PDI<0x13, MRMDestMem, (ops f64mem:$dst, VR128:$src), "movlpd {$src, $dst|$dst, $src}", [(store (f64 (vector_extract (v2f64 VR128:$src), (i32 0))), addr:$dst)]>; +// v2f64 extract element 1 is always custom lowered to unpack high to low +// and extract element 0 so the non-store version isn't too horrible. def MOVHPSmr : PSI<0x17, MRMDestMem, (ops f64mem:$dst, VR128:$src), - "movhps {$src, $dst|$dst, $src}", []>; + "movhps {$src, $dst|$dst, $src}", + [(store (f64 (vector_extract + (v2f64 (vector_shuffle + (bc_v2f64 (v4f32 VR128:$src)), (undef), + UNPCKH_shuffle_mask)), (i32 0))), + addr:$dst)]>; def MOVHPDmr : PDI<0x17, MRMDestMem, (ops f64mem:$dst, VR128:$src), "movhpd {$src, $dst|$dst, $src}", [(store (f64 (vector_extract @@ -1703,31 +1712,60 @@ Requires<[HasSSE2]>; def : Pat<(v2i64 (bitconvert (v16i8 VR128:$src))), (v2i64 VR128:$src)>, Requires<[HasSSE2]>; +def : Pat<(v2i64 (bitconvert (v2f64 VR128:$src))), (v2i64 VR128:$src)>, + Requires<[HasSSE2]>; +def : Pat<(v2i64 (bitconvert (v4f32 VR128:$src))), (v2i64 VR128:$src)>, + Requires<[HasSSE2]>; def : Pat<(v4i32 (bitconvert (v2i64 VR128:$src))), (v4i32 VR128:$src)>, Requires<[HasSSE2]>; def : Pat<(v4i32 (bitconvert (v8i16 VR128:$src))), (v4i32 VR128:$src)>, Requires<[HasSSE2]>; def : Pat<(v4i32 (bitconvert (v16i8 VR128:$src))), (v4i32 VR128:$src)>, Requires<[HasSSE2]>; +def : Pat<(v4i32 (bitconvert (v2f64 VR128:$src))), (v4i32 VR128:$src)>, + Requires<[HasSSE2]>; +def : Pat<(v4i32 (bitconvert (v4f32 VR128:$src))), (v4i32 VR128:$src)>, + Requires<[HasSSE2]>; def : Pat<(v8i16 (bitconvert (v2i64 VR128:$src))), (v4i32 VR128:$src)>, Requires<[HasSSE2]>; def : Pat<(v8i16 (bitconvert (v4i32 VR128:$src))), (v4i32 VR128:$src)>, Requires<[HasSSE2]>; def : Pat<(v8i16 (bitconvert (v16i8 VR128:$src))), (v4i32 VR128:$src)>, Requires<[HasSSE2]>; +def : Pat<(v8i16 (bitconvert (v2f64 VR128:$src))), (v8i16 VR128:$src)>, + Requires<[HasSSE2]>; +def : Pat<(v8i16 (bitconvert (v4f32 VR128:$src))), (v8i16 VR128:$src)>, + Requires<[HasSSE2]>; def : Pat<(v16i8 (bitconvert (v2i64 VR128:$src))), (v4i32 VR128:$src)>, Requires<[HasSSE2]>; def : Pat<(v16i8 (bitconvert (v4i32 VR128:$src))), (v4i32 VR128:$src)>, Requires<[HasSSE2]>; def : Pat<(v16i8 (bitconvert (v8i16 VR128:$src))), (v4i32 VR128:$src)>, Requires<[HasSSE2]>; - -def : Pat<(v4i32 (bitconvert (v4f32 VR128:$src))), (v4i32 VR128:$src)>, +def : Pat<(v16i8 (bitconvert (v2f64 VR128:$src))), (v16i8 VR128:$src)>, + Requires<[HasSSE2]>; +def : Pat<(v16i8 (bitconvert (v4f32 VR128:$src))), (v16i8 VR128:$src)>, + Requires<[HasSSE2]>; +def : Pat<(v4f32 (bitconvert (v2i64 VR128:$src))), (v4f32 VR128:$src)>, Requires<[HasSSE2]>; def : Pat<(v4f32 (bitconvert (v4i32 VR128:$src))), (v4f32 VR128:$src)>, Requires<[HasSSE2]>; +def : Pat<(v4f32 (bitconvert (v8i16 VR128:$src))), (v4f32 VR128:$src)>, + Requires<[HasSSE2]>; +def : Pat<(v4f32 (bitconvert (v16i8 VR128:$src))), (v4f32 VR128:$src)>, + Requires<[HasSSE2]>; def : Pat<(v4f32 (bitconvert (v2f64 VR128:$src))), (v4f32 VR128:$src)>, Requires<[HasSSE2]>; +def : Pat<(v2f64 (bitconvert (v2i64 VR128:$src))), (v2f64 VR128:$src)>, + Requires<[HasSSE2]>; +def : Pat<(v2f64 (bitconvert (v4i32 VR128:$src))), (v2f64 VR128:$src)>, + Requires<[HasSSE2]>; +def : Pat<(v2f64 (bitconvert (v8i16 VR128:$src))), (v2f64 VR128:$src)>, + Requires<[HasSSE2]>; +def : Pat<(v2f64 (bitconvert (v16i8 VR128:$src))), (v2f64 VR128:$src)>, + Requires<[HasSSE2]>; +def : Pat<(v2f64 (bitconvert (v4f32 VR128:$src))), (v2f64 VR128:$src)>, + Requires<[HasSSE2]>; // Zeroing a VR128 then do a MOVS* to the lower bits. def : Pat<(v2f64 (X86zexts2vec FR64:$src)), From alenhar2 at cs.uiuc.edu Fri Apr 7 16:27:22 2006 From: alenhar2 at cs.uiuc.edu (Andrew Lenharth) Date: Fri, 7 Apr 2006 16:27:22 -0500 Subject: [llvm-commits] CVS: llvm-poolalloc/lib/PoolAllocate/PointerCompress.cpp Message-ID: <200604072127.QAA17620@zion.cs.uiuc.edu> Changes in directory llvm-poolalloc/lib/PoolAllocate: PointerCompress.cpp updated: 1.68 -> 1.69 --- Log message: some fixes and a crazy hack --- Diffs of the changes: (+33 -4) PointerCompress.cpp | 37 +++++++++++++++++++++++++++++++++---- 1 files changed, 33 insertions(+), 4 deletions(-) Index: llvm-poolalloc/lib/PoolAllocate/PointerCompress.cpp diff -u llvm-poolalloc/lib/PoolAllocate/PointerCompress.cpp:1.68 llvm-poolalloc/lib/PoolAllocate/PointerCompress.cpp:1.69 --- llvm-poolalloc/lib/PoolAllocate/PointerCompress.cpp:1.68 Thu Feb 23 21:34:29 2006 +++ llvm-poolalloc/lib/PoolAllocate/PointerCompress.cpp Fri Apr 7 16:27:10 2006 @@ -49,6 +49,10 @@ cl::opt DisablePoolBaseASR("disable-ptrcomp-poolbase-aggregation", cl::desc("Don't optimize pool base loads")); + cl::opt + ADLFix("adl-pc", + cl::desc("Enable Andrew's fixes/hacks")); + Statistic<> NumCompressed("pointercompress", "Number of pools pointer compressed"); @@ -231,6 +235,13 @@ ComputeCompressedType(const Type *OrigTy, unsigned NodeOffset, std::map &Nodes) { if (const PointerType *PTY = dyn_cast(OrigTy)) { + if (ADLFix) { + DSNode *PointeeNode = getNode()->getLink(NodeOffset).getNode(); + if (PointeeNode == getNode()) + return MEMUINTTYPE; + return OrigTy; + } + // Okay, we have a pointer. Check to see if the node pointed to is actually // compressed! //DSNode *PointeeNode = getNode()->getLink(NodeOffset).getNode(); @@ -927,7 +938,7 @@ // If this is one of the functions we know about, just materialize the // compressed pointer as a real pointer, and pass it. - if (Callee->getName() == "printf") { + if (Callee->getName() == "printf" || Callee->getName() == "sprintf") { for (unsigned i = 1, e = CI.getNumOperands(); i != e; ++i) if (isa(CI.getOperand(i)->getType()) && getPoolInfo(CI.getOperand(i))) @@ -944,7 +955,20 @@ CI.setOperand(2, SrcPtr); return; } - } else if (Callee->getName() == "llvm.memset") { + } else if (Callee->getName() == "fwrite") { + if (const CompressedPoolInfo *DestPI = getPoolInfo(CI.getOperand(1))) { + std::vector Ops; + Ops.push_back(getTransformedValue(CI.getOperand(1))); + Value *BasePtr = DestPI->EmitPoolBaseLoad(CI); + Value *SrcPtr = new GetElementPtrInst(BasePtr, Ops, + CI.getOperand(1)->getName()+".pp", &CI); + SrcPtr = new CastInst(SrcPtr, CI.getOperand(1)->getType(), "", &CI); + CI.setOperand(1, SrcPtr); + return; + } + } else if (Callee->getName() == "llvm.memset" || + Callee->getName() == "llvm.memset.i32" || + Callee->getName() == "llvm.memset.i64") { if (const CompressedPoolInfo *DestPI = getPoolInfo(CI.getOperand(1))) { std::vector Ops; Ops.push_back(getTransformedValue(CI.getOperand(1))); @@ -955,7 +979,9 @@ CI.setOperand(1, SrcPtr); return; } - } else if (Callee->getName() == "llvm.memcpy") { + } else if (Callee->getName() == "llvm.memcpy" || + Callee->getName() == "llvm.memcpy.i32" || + Callee->getName() == "llvm.memcpy.i64") { bool doret = false; if (const CompressedPoolInfo *DestPI = getPoolInfo(CI.getOperand(1))) { std::vector Ops; @@ -1022,7 +1048,10 @@ // Find the arguments we need to compress. unsigned NumPoolArgs = FI ? FI->ArgNodes.size() : 0; - for (unsigned i = 1, e = CI.getNumOperands(); i != e; ++i) + //only search non-vararg arguments + //FIXME: suspect hack to prevent crashing on user-defined vaarg functions + unsigned NumSearch = FI ? FI->F.arg_size() + 1: CI.getNumOperands(); + for (unsigned i = 1, e = NumSearch; i != e; ++i) if (isa(CI.getOperand(i)->getType()) && i > NumPoolArgs) { Argument *FormalArg = next(FI->F.arg_begin(), i-1-NumPoolArgs); From reid at x10sys.com Fri Apr 7 16:45:36 2006 From: reid at x10sys.com (Reid Spencer) Date: Fri, 7 Apr 2006 16:45:36 -0500 Subject: [llvm-commits] CVS: llvm/runtime/Makefile Message-ID: <200604072145.QAA17698@zion.cs.uiuc.edu> Changes in directory llvm/runtime: Makefile updated: 1.27 -> 1.28 --- Log message: Invert the tests on LLVMGCC_MAJVERS to check for value 4 instead of value 3. This ensures that if llvm-gcc isn't available and consequently the value of LLVMGCC_MAJVERS is blank, that the old (include runtime) behavior will persist. --- Diffs of the changes: (+1 -1) Makefile | 2 +- 1 files changed, 1 insertion(+), 1 deletion(-) Index: llvm/runtime/Makefile diff -u llvm/runtime/Makefile:1.27 llvm/runtime/Makefile:1.28 --- llvm/runtime/Makefile:1.27 Fri Apr 7 13:41:16 2006 +++ llvm/runtime/Makefile Fri Apr 7 16:45:23 2006 @@ -10,7 +10,7 @@ LEVEL = .. include $(LEVEL)/Makefile.config -ifneq ($(LLVMGCC_MAJVERS),3) +ifeq ($(LLVMGCC_MAJVERS),4) PARALLEL_DIRS := install all:: $(Echo) "Warning: These runtime libraries only need to be built with" From reid at x10sys.com Fri Apr 7 16:45:36 2006 From: reid at x10sys.com (Reid Spencer) Date: Fri, 7 Apr 2006 16:45:36 -0500 Subject: [llvm-commits] CVS: llvm/Makefile Message-ID: <200604072145.QAA17702@zion.cs.uiuc.edu> Changes in directory llvm: Makefile updated: 1.54 -> 1.55 --- Log message: Invert the tests on LLVMGCC_MAJVERS to check for value 4 instead of value 3. This ensures that if llvm-gcc isn't available and consequently the value of LLVMGCC_MAJVERS is blank, that the old (include runtime) behavior will persist. --- Diffs of the changes: (+1 -1) Makefile | 2 +- 1 files changed, 1 insertion(+), 1 deletion(-) Index: llvm/Makefile diff -u llvm/Makefile:1.54 llvm/Makefile:1.55 --- llvm/Makefile:1.54 Fri Apr 7 11:21:59 2006 +++ llvm/Makefile Fri Apr 7 16:45:23 2006 @@ -16,7 +16,7 @@ else ifneq ($(MAKECMDGOALS),libs-only) DIRS += tools - ifeq ($(LLVMGCC_MAJVERS),3) + ifneq ($(LLVMGCC_MAJVERS),4) DIRS += runtime else $(warning Skipping runtime libraries, llvm-gcc 4 detected.) From evan.cheng at apple.com Fri Apr 7 16:52:28 2006 From: evan.cheng at apple.com (Evan Cheng) Date: Fri, 7 Apr 2006 16:52:28 -0500 Subject: [llvm-commits] CVS: llvm/test/Regression/CodeGen/X86/vec_shuffle-2.ll Message-ID: <200604072152.QAA17730@zion.cs.uiuc.edu> Changes in directory llvm/test/Regression/CodeGen/X86: vec_shuffle-2.ll updated: 1.1 -> 1.2 --- Log message: Doh! --- Diffs of the changes: (+2 -2) vec_shuffle-2.ll | 4 ++-- 1 files changed, 2 insertions(+), 2 deletions(-) Index: llvm/test/Regression/CodeGen/X86/vec_shuffle-2.ll diff -u llvm/test/Regression/CodeGen/X86/vec_shuffle-2.ll:1.1 llvm/test/Regression/CodeGen/X86/vec_shuffle-2.ll:1.2 --- llvm/test/Regression/CodeGen/X86/vec_shuffle-2.ll:1.1 Fri Apr 7 00:35:45 2006 +++ llvm/test/Regression/CodeGen/X86/vec_shuffle-2.ll Fri Apr 7 16:52:15 2006 @@ -2,7 +2,7 @@ ; RUN: llvm-as < %s | llc -march=x86 -mattr=+sse2 | grep pshuflw | wc -l | grep 1 ; RUN: llvm-as < %s | llc -march=x86 -mattr=+sse2 | grep movhps | wc -l | grep 1 -void %test_pshuf(<2 x long>* %res, <2 x long>* %A) { +void %test1(<2 x long>* %res, <2 x long>* %A) { %tmp = load <2 x long>* %A %tmp = cast <2 x long> %tmp to <8 x short> %tmp0 = extractelement <8 x short> %tmp, uint 0 @@ -26,7 +26,7 @@ ret void } -void %testh_movhps(<4 x float>* %r, <2 x int>* %A) { +void %test2(<4 x float>* %r, <2 x int>* %A) { %tmp = load <4 x float>* %r %tmp = cast <2 x int>* %A to double* %tmp = load double* %tmp From evan.cheng at apple.com Fri Apr 7 16:53:18 2006 From: evan.cheng at apple.com (Evan Cheng) Date: Fri, 7 Apr 2006 16:53:18 -0500 Subject: [llvm-commits] CVS: llvm/lib/Target/X86/X86ISelLowering.cpp Message-ID: <200604072153.QAA17748@zion.cs.uiuc.edu> Changes in directory llvm/lib/Target/X86: X86ISelLowering.cpp updated: 1.159 -> 1.160 --- Log message: Code clean up. --- Diffs of the changes: (+51 -141) X86ISelLowering.cpp | 192 +++++++++++++--------------------------------------- 1 files changed, 51 insertions(+), 141 deletions(-) Index: llvm/lib/Target/X86/X86ISelLowering.cpp diff -u llvm/lib/Target/X86/X86ISelLowering.cpp:1.159 llvm/lib/Target/X86/X86ISelLowering.cpp:1.160 --- llvm/lib/Target/X86/X86ISelLowering.cpp:1.159 Thu Apr 6 18:23:56 2006 +++ llvm/lib/Target/X86/X86ISelLowering.cpp Fri Apr 7 16:53:05 2006 @@ -1405,13 +1405,21 @@ } /// isUndefOrInRange - Op is either an undef node or a ConstantSDNode. Return -/// true if Op is undef or if its value falls within the specified range (L, H). +/// true if Op is undef or if its value falls within the specified range (L, H]. static bool isUndefOrInRange(SDOperand Op, unsigned Low, unsigned Hi) { if (Op.getOpcode() == ISD::UNDEF) return true; unsigned Val = cast(Op)->getValue(); - return (Val >= Low && Val <= Hi); + return (Val >= Low && Val < Hi); +} + +/// isUndefOrEqual - Op is either an undef node or a ConstantSDNode. Return +/// true if Op is undef or if its value equal to the specified value. +static bool isUndefOrEqual(SDOperand Op, unsigned Val) { + if (Op.getOpcode() == ISD::UNDEF) + return true; + return cast(Op)->getValue() == Val; } /// isPSHUFDMask - Return true if the specified VECTOR_SHUFFLE operand @@ -1473,23 +1481,14 @@ return false; // Upper quadword copied in order. - for (unsigned i = 4; i != 8; ++i) { - SDOperand Arg = N->getOperand(i); - if (Arg.getOpcode() == ISD::UNDEF) continue; - assert(isa(Arg) && "Invalid VECTOR_SHUFFLE mask!"); - if (cast(Arg)->getValue() != i) + for (unsigned i = 4; i != 8; ++i) + if (!isUndefOrEqual(N->getOperand(i), i)) return false; - } // Lower quadword shuffled. - for (unsigned i = 0; i != 4; ++i) { - SDOperand Arg = N->getOperand(i); - if (Arg.getOpcode() == ISD::UNDEF) continue; - assert(isa(Arg) && "Invalid VECTOR_SHUFFLE mask!"); - unsigned Val = cast(Arg)->getValue(); - if (Val > 4) + for (unsigned i = 0; i != 4; ++i) + if (!isUndefOrInRange(N->getOperand(i), 0, 4)) return false; - } return true; } @@ -1507,9 +1506,9 @@ // Expect bit 0 == 1, bit1 == 2 SDOperand Bit0 = N->getOperand(0); SDOperand Bit1 = N->getOperand(1); - if (isUndefOrInRange(Bit0, 0, 0) && isUndefOrInRange(Bit1, 3, 3)) + if (isUndefOrEqual(Bit0, 0) && isUndefOrEqual(Bit1, 3)) return true; - if (isUndefOrInRange(Bit0, 1, 1) && isUndefOrInRange(Bit1, 2, 2)) + if (isUndefOrEqual(Bit0, 1) && isUndefOrEqual(Bit1, 2)) return true; return false; } @@ -1544,36 +1543,10 @@ return false; // Expect bit0 == 6, bit1 == 7, bit2 == 2, bit3 == 3 - SDOperand Bit0 = N->getOperand(0); - SDOperand Bit1 = N->getOperand(1); - SDOperand Bit2 = N->getOperand(2); - SDOperand Bit3 = N->getOperand(3); - - if (Bit0.getOpcode() != ISD::UNDEF) { - assert(isa(Bit0) && "Invalid VECTOR_SHUFFLE mask!"); - if (cast(Bit0)->getValue() != 6) - return false; - } - - if (Bit1.getOpcode() != ISD::UNDEF) { - assert(isa(Bit1) && "Invalid VECTOR_SHUFFLE mask!"); - if (cast(Bit1)->getValue() != 7) - return false; - } - - if (Bit2.getOpcode() != ISD::UNDEF) { - assert(isa(Bit2) && "Invalid VECTOR_SHUFFLE mask!"); - if (cast(Bit2)->getValue() != 2) - return false; - } - - if (Bit3.getOpcode() != ISD::UNDEF) { - assert(isa(Bit3) && "Invalid VECTOR_SHUFFLE mask!"); - if (cast(Bit3)->getValue() != 3) - return false; - } - - return true; + return isUndefOrEqual(N->getOperand(0), 6) && + isUndefOrEqual(N->getOperand(1), 7) && + isUndefOrEqual(N->getOperand(2), 2) && + isUndefOrEqual(N->getOperand(3), 3); } /// isMOVLHPSMask - Return true if the specified VECTOR_SHUFFLE operand @@ -1585,36 +1558,10 @@ return false; // Expect bit0 == 0, bit1 == 1, bit2 == 4, bit3 == 5 - SDOperand Bit0 = N->getOperand(0); - SDOperand Bit1 = N->getOperand(1); - SDOperand Bit2 = N->getOperand(2); - SDOperand Bit3 = N->getOperand(3); - - if (Bit0.getOpcode() != ISD::UNDEF) { - assert(isa(Bit0) && "Invalid VECTOR_SHUFFLE mask!"); - if (cast(Bit0)->getValue() != 0) - return false; - } - - if (Bit1.getOpcode() != ISD::UNDEF) { - assert(isa(Bit1) && "Invalid VECTOR_SHUFFLE mask!"); - if (cast(Bit1)->getValue() != 1) - return false; - } - - if (Bit2.getOpcode() != ISD::UNDEF) { - assert(isa(Bit2) && "Invalid VECTOR_SHUFFLE mask!"); - if (cast(Bit2)->getValue() != 4) - return false; - } - - if (Bit3.getOpcode() != ISD::UNDEF) { - assert(isa(Bit3) && "Invalid VECTOR_SHUFFLE mask!"); - if (cast(Bit3)->getValue() != 5) - return false; - } - - return true; + return isUndefOrEqual(N->getOperand(0), 0) && + isUndefOrEqual(N->getOperand(1), 1) && + isUndefOrEqual(N->getOperand(2), 4) && + isUndefOrEqual(N->getOperand(3), 5); } /// isMOVLPMask - Return true if the specified VECTOR_SHUFFLE operand @@ -1626,21 +1573,13 @@ if (NumElems != 2 && NumElems != 4) return false; - for (unsigned i = 0; i < NumElems/2; ++i) { - SDOperand Arg = N->getOperand(i); - if (Arg.getOpcode() == ISD::UNDEF) continue; - assert(isa(Arg) && "Invalid VECTOR_SHUFFLE mask!"); - unsigned Val = cast(Arg)->getValue(); - if (Val != i + NumElems) return false; - } + for (unsigned i = 0; i < NumElems/2; ++i) + if (!isUndefOrEqual(N->getOperand(i), i + NumElems)) + return false; - for (unsigned i = NumElems/2; i < NumElems; ++i) { - SDOperand Arg = N->getOperand(i); - if (Arg.getOpcode() == ISD::UNDEF) continue; - assert(isa(Arg) && "Invalid VECTOR_SHUFFLE mask!"); - unsigned Val = cast(Arg)->getValue(); - if (Val != i) return false; - } + for (unsigned i = NumElems/2; i < NumElems; ++i) + if (!isUndefOrEqual(N->getOperand(i), i)) + return false; return true; } @@ -1654,20 +1593,14 @@ if (NumElems != 2 && NumElems != 4) return false; - for (unsigned i = 0; i < NumElems/2; ++i) { - SDOperand Arg = N->getOperand(i); - if (Arg.getOpcode() == ISD::UNDEF) continue; - assert(isa(Arg) && "Invalid VECTOR_SHUFFLE mask!"); - unsigned Val = cast(Arg)->getValue(); - if (Val != i) return false; - } + for (unsigned i = 0; i < NumElems/2; ++i) + if (!isUndefOrEqual(N->getOperand(i), i)) + return false; for (unsigned i = 0; i < NumElems/2; ++i) { SDOperand Arg = N->getOperand(i + NumElems/2); - if (Arg.getOpcode() == ISD::UNDEF) continue; - assert(isa(Arg) && "Invalid VECTOR_SHUFFLE mask!"); - unsigned Val = cast(Arg)->getValue(); - if (Val != i + NumElems) return false; + if (!isUndefOrEqual(Arg, i + NumElems)) + return false; } return true; @@ -1685,18 +1618,10 @@ for (unsigned i = 0, j = 0; i != NumElems; i += 2, ++j) { SDOperand BitI = N->getOperand(i); SDOperand BitI1 = N->getOperand(i+1); - - if (BitI.getOpcode() != ISD::UNDEF) { - assert(isa(BitI) && "Invalid VECTOR_SHUFFLE mask!"); - if (cast(BitI)->getValue() != j) - return false; - } - - if (BitI1.getOpcode() != ISD::UNDEF) { - assert(isa(BitI1) && "Invalid VECTOR_SHUFFLE mask!"); - if (cast(BitI1)->getValue() != j + NumElems) - return false; - } + if (!isUndefOrEqual(BitI, j)) + return false; + if (!isUndefOrEqual(BitI1, j + NumElems)) + return false; } return true; @@ -1714,18 +1639,10 @@ for (unsigned i = 0, j = 0; i != NumElems; i += 2, ++j) { SDOperand BitI = N->getOperand(i); SDOperand BitI1 = N->getOperand(i+1); - - if (BitI.getOpcode() != ISD::UNDEF) { - assert(isa(BitI) && "Invalid VECTOR_SHUFFLE mask!"); - if (cast(BitI)->getValue() != j + NumElems/2) - return false; - } - - if (BitI1.getOpcode() != ISD::UNDEF) { - assert(isa(BitI1) && "Invalid VECTOR_SHUFFLE mask!"); - if (cast(BitI1)->getValue() != j + NumElems/2 + NumElems) - return false; - } + if (!isUndefOrEqual(BitI, j + NumElems/2)) + return false; + if (!isUndefOrEqual(BitI1, j + NumElems/2 + NumElems)) + return false; } return true; @@ -1745,17 +1662,10 @@ SDOperand BitI = N->getOperand(i); SDOperand BitI1 = N->getOperand(i+1); - if (BitI.getOpcode() != ISD::UNDEF) { - assert(isa(BitI) && "Invalid VECTOR_SHUFFLE mask!"); - if (cast(BitI)->getValue() != j) - return false; - } - - if (BitI1.getOpcode() != ISD::UNDEF) { - assert(isa(BitI1) && "Invalid VECTOR_SHUFFLE mask!"); - if (cast(BitI1)->getValue() != j) - return false; - } + if (!isUndefOrEqual(BitI, j)) + return false; + if (!isUndefOrEqual(BitI1, j)) + return false; } return true; @@ -1923,11 +1833,11 @@ if (isScalarLoadToVector(V1)) { unsigned NumElems = Mask.getNumOperands(); for (unsigned i = 0, e = NumElems/2; i != e; ++i) - if (!isUndefOrInRange(Mask.getOperand(i), i, i)) + if (!isUndefOrEqual(Mask.getOperand(i), i)) return false; for (unsigned i = NumElems/2; i != NumElems; ++i) if (!isUndefOrInRange(Mask.getOperand(i), - NumElems+NumElems/2, NumElems*2-1)) + NumElems+NumElems/2, NumElems*2)) return false; return true; } @@ -1944,10 +1854,10 @@ unsigned NumElems = Op.getNumOperands(); for (unsigned i = 0, e = NumElems/2; i != e; ++i) - if (!isUndefOrInRange(Op.getOperand(i), NumElems, NumElems*2-1)) + if (!isUndefOrInRange(Op.getOperand(i), NumElems, NumElems*2)) return false; for (unsigned i = NumElems/2; i != NumElems; ++i) - if (!isUndefOrInRange(Op.getOperand(i), 0, NumElems-1)) + if (!isUndefOrInRange(Op.getOperand(i), 0, NumElems)) return false; return true; } From lattner at cs.uiuc.edu Fri Apr 7 19:13:54 2006 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Fri, 7 Apr 2006 19:13:54 -0500 Subject: [llvm-commits] CVS: llvm/docs/LangRef.html Message-ID: <200604080013.TAA18981@zion.cs.uiuc.edu> Changes in directory llvm/docs: LangRef.html updated: 1.143 -> 1.144 --- Log message: Description for the new shufflevector instruction I'm adding. --- Diffs of the changes: (+60 -1) LangRef.html | 61 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++- 1 files changed, 60 insertions(+), 1 deletion(-) Index: llvm/docs/LangRef.html diff -u llvm/docs/LangRef.html:1.143 llvm/docs/LangRef.html:1.144 --- llvm/docs/LangRef.html:1.143 Fri Mar 24 01:16:10 2006 +++ llvm/docs/LangRef.html Fri Apr 7 19:13:41 2006 @@ -111,6 +111,7 @@
  5. 'vselect' Instruction
  6. 'extractelement' Instruction
  7. 'insertelement' Instruction
  8. +
  9. 'shufflevector' Instruction
  10. 'call' Instruction
  11. 'va_arg' Instruction
@@ -1135,6 +1136,12 @@
Perform the insertelement operation on constants. + +
shufflevector ( VEC1, VEC2, IDXMASK )
+ +
Perform the shufflevector + operation on constants. +
OPCODE ( LHS, RHS )
Perform the specified operation of the LHS and RHS constants. OPCODE may @@ -2608,6 +2615,58 @@ + + + +
+ +
Syntax:
+ +
+  <result> = shufflevector <n x <ty>> <v1>, <n x <ty>> <v2>, <n x uint> <mask>    ; yields <n x <ty>>
+
+ +
Overview:
+ +

+The 'shufflevector' instruction constructs a permutation of elements +from two input vectors, returning a vector of the same type. +

+ +
Arguments:
+ +

+The first two operands of a 'shufflevector' instruction are vectors +with types that match each other and types that match the result of the +instruction. The third argument is a shuffle mask, which has the same number +of elements as the other vector type, but whose element type is always 'uint'. +

+ +

+The shuffle mask operand is required to be a constant vector with either +constant integer or undef values. +

+ +
Semantics:
+ +

+The elements of the two input vectors are numbered from left to right across +both of the vectors. The shuffle mask operand specifies, for each element of +the result vector, which element of the two input registers the result element +gets. The element selector may be undef (meaning "don't care") and the second +operand may be undef if performing a shuffle from only one vector. +

+ +
Example:
+ +
+  %result = shufflevector <4 x int> %v1, <4 x int> %v2, <4 x uint>     ; yields <4 x int>
+  %result = shufflevector <4 x int> %v1, <4 x int> undef, <4 x uint>   ; yields <4 x int> - Identity shuffle.
+
+
+
@@ -3733,7 +3792,7 @@ Chris Lattner
The LLVM Compiler Infrastructure
- Last modified: $Date: 2006/03/24 07:16:10 $ + Last modified: $Date: 2006/04/08 00:13:41 $ From jlaskey at apple.com Fri Apr 7 19:36:12 2006 From: jlaskey at apple.com (Jim Laskey) Date: Fri, 7 Apr 2006 19:36:12 -0500 Subject: [llvm-commits] CVS: llvm/lib/CodeGen/DwarfWriter.cpp Message-ID: <200604080036.TAA19095@zion.cs.uiuc.edu> Changes in directory llvm/lib/CodeGen: DwarfWriter.cpp updated: 1.55 -> 1.56 --- Log message: Remove section change in function end, preventing override of function's real section. --- Diffs of the changes: (+0 -1) DwarfWriter.cpp | 1 - 1 files changed, 1 deletion(-) Index: llvm/lib/CodeGen/DwarfWriter.cpp diff -u llvm/lib/CodeGen/DwarfWriter.cpp:1.55 llvm/lib/CodeGen/DwarfWriter.cpp:1.56 --- llvm/lib/CodeGen/DwarfWriter.cpp:1.55 Fri Apr 7 15:44:42 2006 +++ llvm/lib/CodeGen/DwarfWriter.cpp Fri Apr 7 19:35:59 2006 @@ -2428,7 +2428,6 @@ EOL("Dwarf End Function"); // Define end label for subprogram. - Asm->SwitchSection(TextSection, 0); EmitLabel("func_end", SubprogramCount); // Construct scopes for subprogram. From jeffc at jolt-lang.org Fri Apr 7 19:43:18 2006 From: jeffc at jolt-lang.org (Jeff Cohen) Date: Fri, 7 Apr 2006 19:43:18 -0500 Subject: [llvm-commits] CVS: llvm/win32/Analysis/Analysis.vcproj Message-ID: <200604080043.TAA19155@zion.cs.uiuc.edu> Changes in directory llvm/win32/Analysis: Analysis.vcproj updated: 1.18 -> 1.19 --- Log message: Get Visual Studio building again. --- Diffs of the changes: (+3 -0) Analysis.vcproj | 3 +++ 1 files changed, 3 insertions(+) Index: llvm/win32/Analysis/Analysis.vcproj diff -u llvm/win32/Analysis/Analysis.vcproj:1.18 llvm/win32/Analysis/Analysis.vcproj:1.19 --- llvm/win32/Analysis/Analysis.vcproj:1.18 Sun Jan 29 22:07:07 2006 +++ llvm/win32/Analysis/Analysis.vcproj Fri Apr 7 19:43:03 2006 @@ -130,6 +130,9 @@ RelativePath="..\..\lib\Analysis\ConstantFolding.cpp"> + + Changes in directory llvm/win32/VMCore: VMCore.vcproj updated: 1.20 -> 1.21 --- Log message: Get Visual Studio building again. --- Diffs of the changes: (+0 -3) VMCore.vcproj | 3 --- 1 files changed, 3 deletions(-) Index: llvm/win32/VMCore/VMCore.vcproj diff -u llvm/win32/VMCore/VMCore.vcproj:1.20 llvm/win32/VMCore/VMCore.vcproj:1.21 --- llvm/win32/VMCore/VMCore.vcproj:1.20 Sat Apr 1 23:20:52 2006 +++ llvm/win32/VMCore/VMCore.vcproj Fri Apr 7 19:43:03 2006 @@ -122,9 +122,6 @@ RelativePath="..\..\lib\VMCore\ConstantFolding.cpp"> - - Changes in directory llvm/include/llvm: IntrinsicsX86.td updated: 1.12 -> 1.13 --- Log message: Fix int_x86_sse_stmxcsr and int_x86_sse_ldmxcsr. Not directly translated from gcc builtins. They are not lowered into these intrinsics which take a ptr argument. --- Diffs of the changes: (+2 -2) IntrinsicsX86.td | 4 ++-- 1 files changed, 2 insertions(+), 2 deletions(-) Index: llvm/include/llvm/IntrinsicsX86.td diff -u llvm/include/llvm/IntrinsicsX86.td:1.12 llvm/include/llvm/IntrinsicsX86.td:1.13 --- llvm/include/llvm/IntrinsicsX86.td:1.12 Fri Apr 7 16:18:40 2006 +++ llvm/include/llvm/IntrinsicsX86.td Fri Apr 7 19:47:01 2006 @@ -150,9 +150,9 @@ // Control register. let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.". - def int_x86_sse_stmxcsr : GCCBuiltin<"__builtin_ia32_stmxcsr">, + def int_x86_sse_stmxcsr : Intrinsic<[llvm_void_ty, llvm_ptr_ty], [IntrWriteMem]>; - def int_x86_sse_ldmxcsr : GCCBuiltin<"__builtin_ia32_ldmxcsr">, + def int_x86_sse_ldmxcsr : Intrinsic<[llvm_void_ty, llvm_ptr_ty], [IntrWriteMem]>; } From evan.cheng at apple.com Fri Apr 7 19:47:57 2006 From: evan.cheng at apple.com (Evan Cheng) Date: Fri, 7 Apr 2006 19:47:57 -0500 Subject: [llvm-commits] CVS: llvm/lib/Target/X86/X86InstrSSE.td Message-ID: <200604080047.TAA19211@zion.cs.uiuc.edu> Changes in directory llvm/lib/Target/X86: X86InstrSSE.td updated: 1.67 -> 1.68 --- Log message: ldmxcsr and stmxcsr. --- Diffs of the changes: (+6 -2) X86InstrSSE.td | 8 ++++++-- 1 files changed, 6 insertions(+), 2 deletions(-) Index: llvm/lib/Target/X86/X86InstrSSE.td diff -u llvm/lib/Target/X86/X86InstrSSE.td:1.67 llvm/lib/Target/X86/X86InstrSSE.td:1.68 --- llvm/lib/Target/X86/X86InstrSSE.td:1.67 Fri Apr 7 16:20:58 2006 +++ llvm/lib/Target/X86/X86InstrSSE.td Fri Apr 7 19:47:44 2006 @@ -1538,9 +1538,13 @@ def SFENCE : I<0xAE, MRM7m, (ops), "sfence", []>, TB, Requires<[HasSSE1]>; -// Load MXCSR register +// MXCSR register def LDMXCSR : I<0xAE, MRM2m, (ops i32mem:$src), - "ldmxcsr {$src|$src}", []>, TB, Requires<[HasSSE1]>; + "ldmxcsr $src", + [(int_x86_sse_ldmxcsr addr:$src)]>, TB, Requires<[HasSSE1]>; +def STMXCSR : I<0xAE, MRM3m, (ops i32mem:$dst), + "stmxcsr $dst", + [(int_x86_sse_stmxcsr addr:$dst)]>, TB, Requires<[HasSSE1]>; //===----------------------------------------------------------------------===// // Alias Instructions From lattner at cs.uiuc.edu Fri Apr 7 20:15:34 2006 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Fri, 7 Apr 2006 20:15:34 -0500 Subject: [llvm-commits] CVS: llvm/include/llvm/Constants.h Instruction.def Instructions.h Message-ID: <200604080115.UAA19392@zion.cs.uiuc.edu> Changes in directory llvm/include/llvm: Constants.h updated: 1.78 -> 1.79 Instruction.def updated: 1.18 -> 1.19 Instructions.h updated: 1.31 -> 1.32 --- Log message: Add a new shufflevector instruction --- Diffs of the changes: (+70 -19) Constants.h | 15 +++++------- Instruction.def | 7 +++-- Instructions.h | 67 ++++++++++++++++++++++++++++++++++++++++++++++++++------ 3 files changed, 70 insertions(+), 19 deletions(-) Index: llvm/include/llvm/Constants.h diff -u llvm/include/llvm/Constants.h:1.78 llvm/include/llvm/Constants.h:1.79 --- llvm/include/llvm/Constants.h:1.78 Tue Feb 7 00:17:10 2006 +++ llvm/include/llvm/Constants.h Fri Apr 7 20:15:18 2006 @@ -524,6 +524,8 @@ Constant *Idx); static Constant *getInsertElementTy(const Type *Ty, Constant *Val, Constant *Elt, Constant *Idx); + static Constant *getShuffleVectorTy(const Type *Ty, Constant *V1, + Constant *V2, Constant *Mask); public: // Static methods to construct a ConstantExpr of different kinds. Note that @@ -591,15 +593,10 @@ static Constant *getGetElementPtr(Constant *C, const std::vector &IdxList); - /// Extractelement form. - /// - static Constant *getExtractElement(Constant *Val, Constant *Idx); - - /// Insertelement form. - /// - static Constant *getInsertElement(Constant *Val, Constant *Elt, - Constant *Idx); - + static Constant *getExtractElement(Constant *Vec, Constant *Idx); + static Constant *getInsertElement(Constant *Vec, Constant *Elt,Constant *Idx); + static Constant *getShuffleVector(Constant *V1, Constant *V2, Constant *Mask); + /// isNullValue - Return true if this is the value that would be returned by /// getNullValue. virtual bool isNullValue() const { return false; } Index: llvm/include/llvm/Instruction.def diff -u llvm/include/llvm/Instruction.def:1.18 llvm/include/llvm/Instruction.def:1.19 --- llvm/include/llvm/Instruction.def:1.18 Tue Jan 17 14:05:59 2006 +++ llvm/include/llvm/Instruction.def Fri Apr 7 20:15:18 2006 @@ -135,9 +135,10 @@ HANDLE_OTHER_INST(35, UserOp1, Instruction) // May be used internally in a pass HANDLE_OTHER_INST(36, UserOp2, Instruction) HANDLE_OTHER_INST(37, VAArg , VAArgInst ) // vaarg instruction -HANDLE_OTHER_INST(38, ExtractElement, ExtractElementInst) // extract packed element -HANDLE_OTHER_INST(39, InsertElement, InsertElementInst) // insert element into packed vector - LAST_OTHER_INST(39) +HANDLE_OTHER_INST(38, ExtractElement, ExtractElementInst)// extract from vector. +HANDLE_OTHER_INST(39, InsertElement, InsertElementInst) // insert into vector +HANDLE_OTHER_INST(40, ShuffleVector, ShuffleVectorInst) // shuffle two vectors. + LAST_OTHER_INST(40) #undef FIRST_TERM_INST #undef HANDLE_TERM_INST Index: llvm/include/llvm/Instructions.h diff -u llvm/include/llvm/Instructions.h:1.31 llvm/include/llvm/Instructions.h:1.32 --- llvm/include/llvm/Instructions.h:1.31 Tue Jan 17 14:05:59 2006 +++ llvm/include/llvm/Instructions.h Fri Apr 7 20:15:18 2006 @@ -733,10 +733,10 @@ } public: - ExtractElementInst(Value *Val, Value *Index, - const std::string &Name = "", Instruction *InsertBefore = 0); - ExtractElementInst(Value *Val, Value *Index, - const std::string &Name, BasicBlock *InsertAtEnd); + ExtractElementInst(Value *Vec, Value *Idx, const std::string &Name = "", + Instruction *InsertBefore = 0); + ExtractElementInst(Value *Vec, Value *Idx, const std::string &Name, + BasicBlock *InsertAtEnd); virtual ExtractElementInst *clone() const; @@ -780,9 +780,9 @@ } public: - InsertElementInst(Value *Val, Value *Elt, Value *Index, - const std::string &Name = "", Instruction *InsertBefore = 0); - InsertElementInst(Value *Val, Value *Elt, Value *Index, + InsertElementInst(Value *Vec, Value *NewElt, Value *Idx, + const std::string &Name = "",Instruction *InsertBefore = 0); + InsertElementInst(Value *Vec, Value *NewElt, Value *Idx, const std::string &Name, BasicBlock *InsertAtEnd); virtual InsertElementInst *clone() const; @@ -811,6 +811,59 @@ }; //===----------------------------------------------------------------------===// +// ShuffleVectorInst Class +//===----------------------------------------------------------------------===// + +/// ShuffleVectorInst - This instruction constructs a fixed permutation of two +/// input vectors. +/// +class ShuffleVectorInst : public Instruction { + Use Ops[3]; + ShuffleVectorInst(const ShuffleVectorInst &IE) : + Instruction(IE.getType(), ShuffleVector, Ops, 3) { + Ops[0].init(IE.Ops[0], this); + Ops[1].init(IE.Ops[1], this); + Ops[2].init(IE.Ops[2], this); + } + +public: + ShuffleVectorInst(Value *V1, Value *V2, Value *Mask, + const std::string &Name = "", Instruction *InsertBefor = 0); + ShuffleVectorInst(Value *V1, Value *V2, Value *Mask, + const std::string &Name, BasicBlock *InsertAtEnd); + + /// isValidOperands - Return true if a value shufflevector instruction can be + /// formed with the specified operands. + static bool isValidOperands(const Value *V1, const Value *V2, + const Value *Mask); + + virtual ShuffleVectorInst *clone() const; + + virtual bool mayWriteToMemory() const { return false; } + + /// Transparently provide more efficient getOperand methods. + Value *getOperand(unsigned i) const { + assert(i < 3 && "getOperand() out of range!"); + return Ops[i]; + } + void setOperand(unsigned i, Value *Val) { + assert(i < 3 && "setOperand() out of range!"); + Ops[i] = Val; + } + unsigned getNumOperands() const { return 3; } + + // Methods for support type inquiry through isa, cast, and dyn_cast: + static inline bool classof(const ShuffleVectorInst *) { return true; } + static inline bool classof(const Instruction *I) { + return I->getOpcode() == Instruction::ShuffleVector; + } + static inline bool classof(const Value *V) { + return isa(V) && classof(cast(V)); + } +}; + + +//===----------------------------------------------------------------------===// // PHINode Class //===----------------------------------------------------------------------===// From lattner at cs.uiuc.edu Fri Apr 7 20:15:34 2006 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Fri, 7 Apr 2006 20:15:34 -0500 Subject: [llvm-commits] CVS: llvm/include/llvm/Support/InstVisitor.h Message-ID: <200604080115.UAA19386@zion.cs.uiuc.edu> Changes in directory llvm/include/llvm/Support: InstVisitor.h updated: 1.38 -> 1.39 --- Log message: Add a new shufflevector instruction --- Diffs of the changes: (+1 -0) InstVisitor.h | 1 + 1 files changed, 1 insertion(+) Index: llvm/include/llvm/Support/InstVisitor.h diff -u llvm/include/llvm/Support/InstVisitor.h:1.38 llvm/include/llvm/Support/InstVisitor.h:1.39 --- llvm/include/llvm/Support/InstVisitor.h:1.38 Tue Jan 17 14:06:13 2006 +++ llvm/include/llvm/Support/InstVisitor.h Fri Apr 7 20:15:18 2006 @@ -177,6 +177,7 @@ RetTy visitVAArgInst(VAArgInst &I) { DELEGATE(Instruction); } RetTy visitExtractElementInst(ExtractElementInst &I) { DELEGATE(Instruction); } RetTy visitInsertElementInst(InsertElementInst &I) { DELEGATE(Instruction); } + RetTy visitShuffleVectorInst(ShuffleVectorInst &I) { DELEGATE(Instruction); } // Next level propagators... if the user does not overload a specific // instruction type, they can overload one of these to get the whole class From lattner at cs.uiuc.edu Fri Apr 7 20:17:55 2006 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Fri, 7 Apr 2006 20:17:55 -0500 Subject: [llvm-commits] CVS: llvm/test/Feature/instructions.ll Message-ID: <200604080117.UAA19508@zion.cs.uiuc.edu> Changes in directory llvm/test/Feature: instructions.ll updated: 1.2 -> 1.3 --- Log message: new testcase for shufflevector --- Diffs of the changes: (+12 -0) instructions.ll | 12 ++++++++++++ 1 files changed, 12 insertions(+) Index: llvm/test/Feature/instructions.ll diff -u llvm/test/Feature/instructions.ll:1.2 llvm/test/Feature/instructions.ll:1.3 --- llvm/test/Feature/instructions.ll:1.2 Tue Jan 17 14:07:30 2006 +++ llvm/test/Feature/instructions.ll Fri Apr 7 20:17:42 2006 @@ -11,3 +11,15 @@ %R = insertelement <4 x uint> %V, uint 0, uint 0 ret <4 x uint> %R } + +<4 x uint> %test_shufflevector(<4 x uint> %V) { + %R = shufflevector <4 x uint> %V, <4 x uint> %V, + <4 x uint> < uint 1, uint undef, uint 7, uint 2> + ret <4 x uint> %R +} + +<4 x float> %test_shufflevector(<4 x float> %V) { + %R = shufflevector <4 x float> %V, <4 x float> undef, + <4 x uint> < uint 1, uint undef, uint 7, uint 2> + ret <4 x float> %R +} From lattner at cs.uiuc.edu Fri Apr 7 20:18:12 2006 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Fri, 7 Apr 2006 20:18:12 -0500 Subject: [llvm-commits] CVS: llvm/lib/Bytecode/Reader/Reader.cpp Message-ID: <200604080118.UAA19541@zion.cs.uiuc.edu> Changes in directory llvm/lib/Bytecode/Reader: Reader.cpp updated: 1.191 -> 1.192 --- Log message: Add shufflevector reading support --- Diffs of the changes: (+22 -0) Reader.cpp | 22 ++++++++++++++++++++++ 1 files changed, 22 insertions(+) Index: llvm/lib/Bytecode/Reader/Reader.cpp diff -u llvm/lib/Bytecode/Reader/Reader.cpp:1.191 llvm/lib/Bytecode/Reader/Reader.cpp:1.192 --- llvm/lib/Bytecode/Reader/Reader.cpp:1.191 Fri Apr 7 00:00:02 2006 +++ llvm/lib/Bytecode/Reader/Reader.cpp Fri Apr 7 20:17:59 2006 @@ -734,6 +734,20 @@ getValue(Type::UIntTyID, Oprnds[2])); break; } + case Instruction::ShuffleVector: { + const PackedType *PackedTy = dyn_cast(InstTy); + if (!PackedTy || Oprnds.size() != 3) + throw std::string("Invalid shufflevector instruction!"); + Value *V1 = getValue(iType, Oprnds[0]); + Value *V2 = getValue(iType, Oprnds[1]); + const PackedType *EltTy = + PackedType::get(Type::UIntTy, PackedTy->getNumElements()); + Value *V3 = getValue(getTypeSlot(EltTy), Oprnds[2]); + if (!ShuffleVectorInst::isValidOperands(V1, V2, V3)) + throw std::string("Invalid shufflevector instruction!"); + Result = new ShuffleVectorInst(V1, V2, V3); + break; + } case Instruction::Cast: Result = new CastInst(getValue(iType, Oprnds[0]), getSanitizedType(Oprnds[1])); @@ -1493,6 +1507,14 @@ ConstantExpr::getInsertElement(ArgVec[0], ArgVec[1], ArgVec[2]); if (Handler) Handler->handleConstantExpression(Opcode, ArgVec, Result); return Result; + } else if (Opcode == Instruction::ShuffleVector) { + if (ArgVec.size() != 3 || + !ShuffleVectorInst::isValidOperands(ArgVec[0], ArgVec[1], ArgVec[2])) + error("shufflevector constant expr must have three arguments."); + Constant *Result = + ConstantExpr::getShuffleVector(ArgVec[0], ArgVec[1], ArgVec[2]); + if (Handler) Handler->handleConstantExpression(Opcode, ArgVec, Result); + return Result; } else { // All other 2-operand expressions Constant* Result = ConstantExpr::get(Opcode, ArgVec[0], ArgVec[1]); if (Handler) Handler->handleConstantExpression(Opcode, ArgVec, Result); From lattner at cs.uiuc.edu Fri Apr 7 20:18:30 2006 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Fri, 7 Apr 2006 20:18:30 -0500 Subject: [llvm-commits] CVS: llvm/lib/VMCore/AsmWriter.cpp ConstantFolding.cpp ConstantFolding.h Constants.cpp Instruction.cpp Instructions.cpp Verifier.cpp Message-ID: <200604080118.UAA19590@zion.cs.uiuc.edu> Changes in directory llvm/lib/VMCore: AsmWriter.cpp updated: 1.196 -> 1.197 ConstantFolding.cpp updated: 1.86 -> 1.87 ConstantFolding.h updated: 1.47 -> 1.48 Constants.cpp updated: 1.148 -> 1.149 Instruction.cpp updated: 1.50 -> 1.51 Instructions.cpp updated: 1.32 -> 1.33 Verifier.cpp updated: 1.152 -> 1.153 --- Log message: Add shufflevector support, todo, implement better constant folding. --- Diffs of the changes: (+134 -8) AsmWriter.cpp | 3 +- ConstantFolding.cpp | 8 ++++++ ConstantFolding.h | 3 ++ Constants.cpp | 40 ++++++++++++++++++++++++++++++++- Instruction.cpp | 1 Instructions.cpp | 63 +++++++++++++++++++++++++++++++++++++++++++++++----- Verifier.cpp | 24 +++++++++++++++++++ 7 files changed, 134 insertions(+), 8 deletions(-) Index: llvm/lib/VMCore/AsmWriter.cpp diff -u llvm/lib/VMCore/AsmWriter.cpp:1.196 llvm/lib/VMCore/AsmWriter.cpp:1.197 --- llvm/lib/VMCore/AsmWriter.cpp:1.196 Wed Mar 1 16:17:00 2006 +++ llvm/lib/VMCore/AsmWriter.cpp Fri Apr 7 20:18:18 2006 @@ -1237,7 +1237,8 @@ // Shift Left & Right print both types even for Ubyte LHS, and select prints // types even if all operands are bools. - if (isa(I) || isa(I) || isa(I)) { + if (isa(I) || isa(I) || isa(I) || + isa(I)) { PrintAllTypes = true; } else { for (unsigned i = 1, E = I.getNumOperands(); i != E; ++i) { Index: llvm/lib/VMCore/ConstantFolding.cpp diff -u llvm/lib/VMCore/ConstantFolding.cpp:1.86 llvm/lib/VMCore/ConstantFolding.cpp:1.87 --- llvm/lib/VMCore/ConstantFolding.cpp:1.86 Thu Apr 6 23:44:06 2006 +++ llvm/lib/VMCore/ConstantFolding.cpp Fri Apr 7 20:18:18 2006 @@ -908,6 +908,14 @@ return 0; } +Constant *llvm::ConstantFoldShuffleVectorInstruction(const Constant *V1, + const Constant *V2, + const Constant *Mask) { + // TODO: + return 0; +} + + /// isZeroSizedType - This type is zero sized if its an array or structure of /// zero sized types. The only leaf zero sized type is an empty structure. static bool isMaybeZeroSizedType(const Type *Ty) { Index: llvm/lib/VMCore/ConstantFolding.h diff -u llvm/lib/VMCore/ConstantFolding.h:1.47 llvm/lib/VMCore/ConstantFolding.h:1.48 --- llvm/lib/VMCore/ConstantFolding.h:1.47 Tue Jan 17 14:07:22 2006 +++ llvm/lib/VMCore/ConstantFolding.h Fri Apr 7 20:18:18 2006 @@ -36,6 +36,9 @@ Constant *ConstantFoldInsertElementInstruction(const Constant *Val, const Constant *Elt, const Constant *Idx); + Constant *ConstantFoldShuffleVectorInstruction(const Constant *V1, + const Constant *V2, + const Constant *Mask); Constant *ConstantFoldBinaryInstruction(unsigned Opcode, const Constant *V1, const Constant *V2); Constant *ConstantFoldGetElementPtr(const Constant *C, Index: llvm/lib/VMCore/Constants.cpp diff -u llvm/lib/VMCore/Constants.cpp:1.148 llvm/lib/VMCore/Constants.cpp:1.149 --- llvm/lib/VMCore/Constants.cpp:1.148 Fri Mar 10 18:13:10 2006 +++ llvm/lib/VMCore/Constants.cpp Fri Apr 7 20:18:18 2006 @@ -376,6 +376,21 @@ } }; +/// ShuffleVectorConstantExpr - This class is private to +/// Constants.cpp, and is used behind the scenes to implement +/// shufflevector constant exprs. +class ShuffleVectorConstantExpr : public ConstantExpr { + Use Ops[3]; +public: + ShuffleVectorConstantExpr(Constant *C1, Constant *C2, Constant *C3) + : ConstantExpr(C1->getType(), Instruction::ShuffleVector, + Ops, 3) { + Ops[0].init(C1, this); + Ops[1].init(C2, this); + Ops[2].init(C3, this); + } +}; + /// GetElementPtrConstantExpr - This class is private to Constants.cpp, and is /// used behind the scenes to implement getelementpr constant exprs. struct GetElementPtrConstantExpr : public ConstantExpr { @@ -1175,7 +1190,10 @@ if (V.first == Instruction::InsertElement) return new InsertElementConstantExpr(V.second[0], V.second[1], V.second[2]); - + if (V.first == Instruction::ShuffleVector) + return new ShuffleVectorConstantExpr(V.second[0], V.second[1], + V.second[2]); + assert(V.first == Instruction::GetElementPtr && "Invalid ConstantExpr!"); std::vector IdxList(V.second.begin()+1, V.second.end()); @@ -1464,6 +1482,26 @@ Val, Elt, Idx); } +Constant *ConstantExpr::getShuffleVectorTy(const Type *ReqTy, Constant *V1, + Constant *V2, Constant *Mask) { + if (Constant *FC = ConstantFoldShuffleVectorInstruction(V1, V2, Mask)) + return FC; // Fold a few common cases... + // Look up the constant in the table first to ensure uniqueness + std::vector ArgVec(1, V1); + ArgVec.push_back(V2); + ArgVec.push_back(Mask); + const ExprMapKeyType &Key = std::make_pair(Instruction::ShuffleVector,ArgVec); + return ExprConstants.getOrCreate(ReqTy, Key); +} + +Constant *ConstantExpr::getShuffleVector(Constant *V1, Constant *V2, + Constant *Mask) { + assert(ShuffleVectorInst::isValidOperands(V1, V2, Mask) && + "Invalid shuffle vector constant expr operands!"); + return getShuffleVectorTy(V1->getType(), V1, V2, Mask); +} + + // destroyConstant - Remove the constant from the constant table... // void ConstantExpr::destroyConstant() { Index: llvm/lib/VMCore/Instruction.cpp diff -u llvm/lib/VMCore/Instruction.cpp:1.50 llvm/lib/VMCore/Instruction.cpp:1.51 --- llvm/lib/VMCore/Instruction.cpp:1.50 Tue Jan 17 14:07:22 2006 +++ llvm/lib/VMCore/Instruction.cpp Fri Apr 7 20:18:18 2006 @@ -122,6 +122,7 @@ case VAArg: return "va_arg"; case ExtractElement: return "extractelement"; case InsertElement: return "insertelement"; + case ShuffleVector: return "shufflevector"; default: return " "; } Index: llvm/lib/VMCore/Instructions.cpp diff -u llvm/lib/VMCore/Instructions.cpp:1.32 llvm/lib/VMCore/Instructions.cpp:1.33 --- llvm/lib/VMCore/Instructions.cpp:1.32 Sat Mar 25 15:54:21 2006 +++ llvm/lib/VMCore/Instructions.cpp Fri Apr 7 20:18:18 2006 @@ -800,7 +800,8 @@ //===----------------------------------------------------------------------===// ExtractElementInst::ExtractElementInst(Value *Val, Value *Index, - const std::string &Name, Instruction *InsertBef) + const std::string &Name, + Instruction *InsertBef) : Instruction(cast(Val->getType())->getElementType(), ExtractElement, Ops, 2, Name, InsertBef) { Ops[0].init(Val, this); @@ -808,7 +809,8 @@ } ExtractElementInst::ExtractElementInst(Value *Val, Value *Index, - const std::string &Name, BasicBlock *InsertAE) + const std::string &Name, + BasicBlock *InsertAE) : Instruction(cast(Val->getType())->getElementType(), ExtractElement, Ops, 2, Name, InsertAE) { Ops[0].init(Val, this); @@ -820,7 +822,8 @@ //===----------------------------------------------------------------------===// InsertElementInst::InsertElementInst(Value *Val, Value *Elt, Value *Index, - const std::string &Name, Instruction *InsertBef) + const std::string &Name, + Instruction *InsertBef) : Instruction(Val->getType(), InsertElement, Ops, 3, Name, InsertBef) { Ops[0].init(Val, this); Ops[1].init(Elt, this); @@ -828,7 +831,8 @@ } InsertElementInst::InsertElementInst(Value *Val, Value *Elt, Value *Index, - const std::string &Name, BasicBlock *InsertAE) + const std::string &Name, + BasicBlock *InsertAE) : Instruction(Val->getType(), InsertElement, Ops, 3, Name, InsertAE) { Ops[0].init(Val, this); Ops[1].init(Elt, this); @@ -836,6 +840,46 @@ } //===----------------------------------------------------------------------===// +// ShuffleVectorInst Implementation +//===----------------------------------------------------------------------===// + +ShuffleVectorInst::ShuffleVectorInst(Value *V1, Value *V2, Value *Mask, + const std::string &Name, + Instruction *InsertBefore) + : Instruction(V1->getType(), ShuffleVector, Ops, 3, Name, InsertBefore) { + assert(isValidOperands(V1, V2, Mask) && + "Invalid shuffle vector instruction operands!"); + Ops[0].init(V1, this); + Ops[1].init(V2, this); + Ops[2].init(Mask, this); +} + +ShuffleVectorInst::ShuffleVectorInst(Value *V1, Value *V2, Value *Mask, + const std::string &Name, + BasicBlock *InsertAtEnd) + : Instruction(V1->getType(), ShuffleVector, Ops, 3, Name, InsertAtEnd) { + assert(isValidOperands(V1, V2, Mask) && + "Invalid shuffle vector instruction operands!"); + + Ops[0].init(V1, this); + Ops[1].init(V2, this); + Ops[2].init(Mask, this); +} + +bool ShuffleVectorInst::isValidOperands(const Value *V1, const Value *V2, + const Value *Mask) { + if (!isa(V1->getType())) return false; + if (V1->getType() != V2->getType()) return false; + if (!isa(Mask->getType()) || + cast(Mask->getType())->getElementType() != Type::UIntTy || + cast(Mask->getType())->getNumElements() != + cast(V1->getType())->getNumElements()) + return false; + return true; +} + + +//===----------------------------------------------------------------------===// // BinaryOperator Class //===----------------------------------------------------------------------===// @@ -1202,8 +1246,15 @@ ShiftInst *ShiftInst::clone() const { return new ShiftInst(*this); } SelectInst *SelectInst::clone() const { return new SelectInst(*this); } VAArgInst *VAArgInst::clone() const { return new VAArgInst(*this); } -ExtractElementInst *ExtractElementInst::clone() const {return new ExtractElementInst(*this); } -InsertElementInst *InsertElementInst::clone() const {return new InsertElementInst(*this); } +ExtractElementInst *ExtractElementInst::clone() const { + return new ExtractElementInst(*this); +} +InsertElementInst *InsertElementInst::clone() const { + return new InsertElementInst(*this); +} +ShuffleVectorInst *ShuffleVectorInst::clone() const { + return new ShuffleVectorInst(*this); +} PHINode *PHINode::clone() const { return new PHINode(*this); } ReturnInst *ReturnInst::clone() const { return new ReturnInst(*this); } BranchInst *BranchInst::clone() const { return new BranchInst(*this); } Index: llvm/lib/VMCore/Verifier.cpp diff -u llvm/lib/VMCore/Verifier.cpp:1.152 llvm/lib/VMCore/Verifier.cpp:1.153 --- llvm/lib/VMCore/Verifier.cpp:1.152 Fri Mar 31 01:22:05 2006 +++ llvm/lib/VMCore/Verifier.cpp Fri Apr 7 20:18:18 2006 @@ -184,6 +184,7 @@ void visitShiftInst(ShiftInst &SI); void visitExtractElementInst(ExtractElementInst &EI); void visitInsertElementInst(InsertElementInst &EI); + void visitShuffleVectorInst(ShuffleVectorInst &EI); void visitVAArgInst(VAArgInst &VAA) { visitInstruction(VAA); } void visitCallInst(CallInst &CI); void visitGetElementPtrInst(GetElementPtrInst &GEP); @@ -562,6 +563,29 @@ visitInstruction(IE); } +void Verifier::visitShuffleVectorInst(ShuffleVectorInst &SV) { + Assert1(ShuffleVectorInst::isValidOperands(SV.getOperand(0), SV.getOperand(1), + SV.getOperand(2)), + "Invalid shufflevector operands!", &SV); + Assert1(SV.getType() == SV.getOperand(0)->getType(), + "Result of shufflevector must match first operand type!", &SV); + + // Check to see if Mask is valid. + if (const ConstantPacked *MV = dyn_cast(SV.getOperand(2))) { + for (unsigned i = 0, e = MV->getNumOperands(); i != e; ++i) { + Assert1(isa(MV->getOperand(i)) || + isa(MV->getOperand(i)), + "Invalid shufflevector shuffle mask!", &SV); + } + } else { + Assert1(isa(SV.getOperand(2)) || + isa(SV.getOperand(2)), + "Invalid shufflevector shuffle mask!", &SV); + } + + visitInstruction(SV); +} + void Verifier::visitGetElementPtrInst(GetElementPtrInst &GEP) { const Type *ElTy = GetElementPtrInst::getIndexedType(GEP.getOperand(0)->getType(), From lattner at cs.uiuc.edu Fri Apr 7 20:18:48 2006 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Fri, 7 Apr 2006 20:18:48 -0500 Subject: [llvm-commits] CVS: llvm/lib/AsmParser/Lexer.l llvmAsmParser.y Message-ID: <200604080118.UAA19623@zion.cs.uiuc.edu> Changes in directory llvm/lib/AsmParser: Lexer.l updated: 1.72 -> 1.73 llvmAsmParser.y updated: 1.250 -> 1.251 --- Log message: Parse shufflevector --- Diffs of the changes: (+7 -1) Lexer.l | 1 + llvmAsmParser.y | 7 ++++++- 2 files changed, 7 insertions(+), 1 deletion(-) Index: llvm/lib/AsmParser/Lexer.l diff -u llvm/lib/AsmParser/Lexer.l:1.72 llvm/lib/AsmParser/Lexer.l:1.73 --- llvm/lib/AsmParser/Lexer.l:1.72 Wed Feb 15 01:02:59 2006 +++ llvm/lib/AsmParser/Lexer.l Fri Apr 7 20:18:35 2006 @@ -277,6 +277,7 @@ extractelement { RET_TOK(OtherOpVal, ExtractElement, EXTRACTELEMENT); } insertelement { RET_TOK(OtherOpVal, InsertElement, INSERTELEMENT); } +shufflevector { RET_TOK(OtherOpVal, ShuffleVector, SHUFFLEVECTOR); } {VarID} { Index: llvm/lib/AsmParser/llvmAsmParser.y diff -u llvm/lib/AsmParser/llvmAsmParser.y:1.250 llvm/lib/AsmParser/llvmAsmParser.y:1.251 --- llvm/lib/AsmParser/llvmAsmParser.y:1.250 Sat Mar 4 01:53:16 2006 +++ llvm/lib/AsmParser/llvmAsmParser.y Fri Apr 7 20:18:35 2006 @@ -998,7 +998,7 @@ // Other Operators %type ShiftOps %token PHI_TOK CAST SELECT SHL SHR VAARG -%token EXTRACTELEMENT INSERTELEMENT +%token EXTRACTELEMENT INSERTELEMENT SHUFFLEVECTOR %token VAARG_old VANEXT_old //OBSOLETE @@ -2260,6 +2260,11 @@ ThrowException("Third operand of insertelement must be uint!"); $$ = new InsertElementInst($2, $4, $6); } + | SHUFFLEVECTOR ResolvedVal ',' ResolvedVal ',' ResolvedVal { + if (!ShuffleVectorInst::isValidOperands($2, $4, $6)) + ThrowException("Invalid shufflevector operands!"); + $$ = new ShuffleVectorInst($2, $4, $6); + } | PHI_TOK PHIList { const Type *Ty = $2->front().first->getType(); if (!Ty->isFirstClassType()) From lattner at cs.uiuc.edu Fri Apr 7 20:19:10 2006 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Fri, 7 Apr 2006 20:19:10 -0500 Subject: [llvm-commits] CVS: llvm/lib/AsmParser/Lexer.cpp.cvs Lexer.l.cvs llvmAsmParser.cpp.cvs llvmAsmParser.h.cvs llvmAsmParser.y.cvs Message-ID: <200604080119.UAA19711@zion.cs.uiuc.edu> Changes in directory llvm/lib/AsmParser: Lexer.cpp.cvs updated: 1.3 -> 1.4 Lexer.l.cvs updated: 1.2 -> 1.3 llvmAsmParser.cpp.cvs updated: 1.2 -> 1.3 llvmAsmParser.h.cvs updated: 1.1 -> 1.2 llvmAsmParser.y.cvs updated: 1.2 -> 1.3 --- Log message: regenerate --- Diffs of the changes: (+1115 -1088) Lexer.cpp.cvs | 866 ++++++++++++++++----------------- Lexer.l.cvs | 1 llvmAsmParser.cpp.cvs | 1294 +++++++++++++++++++++++++------------------------- llvmAsmParser.h.cvs | 5 llvmAsmParser.y.cvs | 11 5 files changed, 1115 insertions(+), 1062 deletions(-) Index: llvm/lib/AsmParser/Lexer.cpp.cvs diff -u llvm/lib/AsmParser/Lexer.cpp.cvs:1.3 llvm/lib/AsmParser/Lexer.cpp.cvs:1.4 --- llvm/lib/AsmParser/Lexer.cpp.cvs:1.3 Wed Feb 15 01:22:58 2006 +++ llvm/lib/AsmParser/Lexer.cpp.cvs Fri Apr 7 20:18:56 2006 @@ -20,7 +20,7 @@ /* A lexical scanner generated by flex */ /* Scanner skeleton version: - * $Header: /var/cvs/llvm/llvm/lib/AsmParser/Lexer.cpp.cvs,v 1.3 2006/02/15 07:22:58 lattner Exp $ + * $Header: /var/cvs/llvm/llvm/lib/AsmParser/Lexer.cpp.cvs,v 1.4 2006/04/08 01:18:56 lattner Exp $ */ #define FLEX_SCANNER @@ -308,33 +308,33 @@ *yy_cp = '\0'; \ yy_c_buf_p = yy_cp; -#define YY_NUM_RULES 106 -#define YY_END_OF_BUFFER 107 -static yyconst short int yy_acclist[184] = +#define YY_NUM_RULES 107 +#define YY_END_OF_BUFFER 108 +static yyconst short int yy_acclist[185] = { 0, - 107, 105, 106, 104, 105, 106, 104, 106, 105, 106, - 105, 106, 105, 106, 105, 106, 105, 106, 105, 106, - 97, 105, 106, 97, 105, 106, 1, 105, 106, 105, - 106, 105, 106, 105, 106, 105, 106, 105, 106, 105, - 106, 105, 106, 105, 106, 105, 106, 105, 106, 105, - 106, 105, 106, 105, 106, 105, 106, 105, 106, 105, - 106, 105, 106, 105, 106, 105, 106, 105, 106, 105, - 106, 96, 94, 93, 93, 100, 98, 102, 97, 1, - 80, 37, 62, 20, 96, 93, 93, 101, 102, 17, - 102, 103, 56, 61, 35, 30, 38, 59, 3, 47, - - 58, 22, 70, 60, 79, 74, 75, 57, 63, 95, - 102, 102, 42, 71, 72, 87, 88, 49, 19, 99, - 23, 4, 54, 48, 41, 11, 102, 32, 2, 5, + 108, 106, 107, 105, 106, 107, 105, 107, 106, 107, + 106, 107, 106, 107, 106, 107, 106, 107, 106, 107, + 98, 106, 107, 98, 106, 107, 1, 106, 107, 106, + 107, 106, 107, 106, 107, 106, 107, 106, 107, 106, + 107, 106, 107, 106, 107, 106, 107, 106, 107, 106, + 107, 106, 107, 106, 107, 106, 107, 106, 107, 106, + 107, 106, 107, 106, 107, 106, 107, 106, 107, 106, + 107, 97, 95, 94, 94, 101, 99, 103, 98, 1, + 80, 37, 62, 20, 97, 94, 94, 102, 103, 17, + 103, 104, 56, 61, 35, 30, 38, 59, 3, 47, + + 58, 22, 70, 60, 79, 74, 75, 57, 63, 96, + 103, 103, 42, 71, 72, 87, 88, 49, 19, 100, + 23, 4, 54, 48, 41, 11, 103, 32, 2, 5, 51, 53, 43, 65, 69, 67, 68, 66, 64, 45, 89, 44, 50, 18, 77, 86, 40, 52, 27, 21, 39, 7, 82, 29, 85, 34, 55, 73, 81, 24, 25, 83, 46, 78, 76, 6, 26, 33, 8, 14, - 9, 10, 31, 12, 36, 28, 84, 90, 92, 13, - 91, 15, 16 + 9, 10, 31, 12, 36, 28, 84, 90, 92, 93, + 13, 91, 15, 16 } ; -static yyconst short int yy_accept[444] = +static yyconst short int yy_accept[455] = { 0, 1, 1, 1, 2, 4, 7, 9, 11, 13, 15, 17, 19, 21, 24, 27, 30, 32, 34, 36, 38, @@ -354,37 +354,38 @@ 100, 100, 100, 100, 100, 100, 100, 101, 101, 101, 101, 101, 101, 101, 101, 101, 102, 103, 103, 103, 104, 104, 105, 106, 106, 106, 106, 106, 106, 107, - 107, 108, 108, 108, 109, 109, 109, 109, 109, 109, + 107, 108, 108, 108, 108, 109, 109, 109, 109, 109, 109, 109, 109, 109, 109, 109, 109, 109, 109, 109, - 109, 109, 109, 109, 109, 110, 110, 111, 112, 112, + 109, 109, 109, 109, 109, 109, 110, 110, 111, 112, - 112, 112, 113, 113, 113, 113, 113, 114, 115, 116, + 112, 112, 112, 113, 113, 113, 113, 113, 114, 115, 116, 116, 116, 116, 116, 116, 116, 116, 116, 116, - 116, 116, 117, 117, 117, 117, 117, 117, 117, 117, - 117, 117, 118, 119, 119, 119, 120, 120, 120, 121, + 116, 116, 116, 117, 117, 117, 117, 117, 117, 117, + 117, 117, 117, 118, 119, 119, 119, 120, 120, 120, 121, 121, 121, 121, 121, 121, 121, 121, 121, 121, - 121, 122, 122, 122, 123, 124, 124, 125, 125, 125, - 125, 125, 125, 125, 125, 125, 125, 126, 126, 127, - 127, 128, 129, 129, 129, 130, 130, 130, 130, 130, - 130, 130, 130, 130, 130, 131, 131, 132, 132, 132, - 132, 132, 132, 132, 133, 133, 133, 133, 133, 133, - - 133, 134, 134, 134, 135, 136, 137, 138, 139, 140, - 141, 141, 142, 142, 142, 142, 143, 144, 145, 145, - 145, 145, 145, 145, 146, 146, 146, 146, 147, 147, - 148, 148, 148, 148, 149, 150, 151, 151, 151, 152, - 152, 153, 153, 153, 153, 154, 154, 155, 156, 157, - 158, 158, 158, 159, 159, 160, 161, 162, 162, 162, - 163, 164, 165, 166, 166, 166, 166, 166, 167, 168, - 168, 168, 168, 168, 168, 168, 168, 168, 169, 169, - 169, 169, 169, 169, 169, 170, 171, 171, 171, 171, - 171, 172, 173, 173, 173, 173, 173, 174, 174, 175, + 121, 121, 121, 122, 122, 122, 123, 124, 124, 125, + 125, 125, 125, 125, 125, 125, 125, 125, 125, 126, + 126, 127, 127, 128, 129, 129, 129, 130, 130, 130, + 130, 130, 130, 130, 130, 130, 130, 131, 131, 132, + 132, 132, 132, 132, 132, 132, 133, 133, 133, 133, + + 133, 133, 133, 134, 134, 134, 135, 136, 137, 138, + 139, 140, 141, 141, 141, 142, 142, 142, 142, 143, + 144, 145, 145, 145, 145, 145, 145, 146, 146, 146, + 146, 147, 147, 148, 148, 148, 148, 149, 150, 151, + 151, 151, 152, 152, 153, 153, 153, 153, 154, 154, + 155, 156, 157, 158, 158, 158, 159, 159, 159, 160, + 161, 162, 162, 162, 163, 164, 165, 166, 166, 166, + 166, 166, 167, 168, 168, 168, 168, 168, 168, 168, + 168, 168, 169, 169, 169, 169, 169, 169, 169, 169, + 170, 171, 171, 171, 171, 171, 172, 173, 173, 173, + 173, 173, 173, 174, 174, 175, 175, 175, 175, 175, 175, 175, 175, 175, 175, 175, 175, 175, 175, 175, - 175, 175, 175, 175, 176, 176, 176, 176, 176, 176, - 176, 176, 177, 177, 178, 178, 178, 178, 178, 178, - 178, 178, 178, 179, 179, 180, 181, 181, 182, 183, - 183, 184, 184 + 175, 175, 176, 176, 176, 176, 176, 176, 176, 176, + 177, 177, 177, 178, 178, 178, 178, 178, 178, 178, + 178, 178, 178, 179, 179, 180, 181, 182, 182, 183, + 184, 184, 185, 185 } ; static yyconst int yy_ec[256] = @@ -428,113 +429,115 @@ 3 } ; -static yyconst short int yy_base[448] = +static yyconst short int yy_base[459] = { 0, - 0, 0, 926, 927, 927, 927, 921, 912, 34, 36, + 0, 0, 948, 949, 949, 949, 943, 934, 34, 36, 38, 42, 46, 50, 0, 52, 57, 54, 68, 62, 80, 82, 76, 94, 98, 40, 83, 88, 56, 125, - 108, 154, 109, 87, 110, 111, 919, 927, 910, 927, + 108, 154, 109, 87, 110, 111, 941, 949, 932, 949, 0, 119, 134, 142, 145, 124, 159, 166, 179, 0, - 55, 180, 147, 153, 119, 150, 183, 156, 909, 175, + 55, 180, 147, 153, 119, 150, 183, 156, 931, 175, 191, 192, 196, 90, 146, 200, 199, 201, 202, 204, 205, 211, 212, 210, 218, 217, 221, 227, 236, 230, - 214, 239, 241, 908, 243, 247, 248, 225, 249, 250, - 251, 253, 258, 262, 267, 270, 907, 274, 259, 275, + 214, 239, 241, 930, 243, 247, 248, 225, 249, 250, + 251, 253, 258, 262, 267, 270, 929, 274, 259, 279, - 279, 263, 284, 41, 285, 286, 288, 84, 294, 906, - 0, 308, 310, 905, 318, 330, 0, 904, 300, 304, - 903, 314, 902, 282, 901, 320, 324, 331, 900, 332, - 312, 333, 336, 899, 337, 342, 338, 341, 344, 345, - 352, 349, 356, 353, 346, 360, 363, 364, 367, 370, - 371, 373, 374, 375, 377, 898, 897, 378, 31, 896, - 379, 895, 894, 404, 392, 395, 380, 408, 893, 383, - 892, 388, 399, 891, 398, 416, 422, 386, 391, 426, - 424, 427, 428, 429, 432, 430, 440, 434, 436, 437, - 442, 446, 443, 455, 890, 444, 927, 458, 475, 461, - - 465, 477, 466, 472, 468, 478, 889, 888, 887, 480, - 481, 484, 486, 482, 488, 490, 491, 496, 494, 498, - 492, 886, 502, 506, 507, 500, 508, 510, 513, 514, - 518, 885, 884, 519, 520, 883, 522, 525, 0, 527, - 526, 523, 531, 534, 538, 540, 541, 544, 545, 552, - 882, 556, 555, 881, 880, 558, 879, 560, 562, 550, - 568, 566, 569, 574, 575, 576, 878, 577, 877, 578, - 581, 876, 582, 581, 875, 585, 588, 584, 596, 597, - 594, 598, 599, 601, 874, 607, 873, 604, 609, 610, - 612, 615, 618, 872, 617, 619, 622, 630, 631, 633, - - 871, 620, 623, 870, 869, 868, 867, 866, 865, 864, - 637, 863, 636, 641, 643, 862, 861, 860, 644, 649, - 645, 650, 651, 859, 654, 655, 657, 858, 658, 857, - 659, 660, 661, 856, 855, 854, 665, 663, 853, 666, - 852, 672, 675, 680, 851, 687, 850, 849, 848, 847, - 678, 679, 846, 688, 845, 844, 843, 689, 691, 842, - 839, 829, 828, 690, 693, 692, 695, 827, 825, 697, - 701, 704, 700, 707, 708, 711, 714, 824, 715, 716, - 725, 719, 726, 727, 823, 822, 729, 731, 732, 733, - 819, 818, 734, 739, 735, 737, 817, 740, 816, 745, - - 741, 751, 752, 757, 758, 759, 760, 761, 762, 763, - 765, 767, 770, 812, 769, 771, 774, 783, 773, 777, - 784, 811, 785, 810, 787, 791, 793, 795, 797, 799, - 802, 803, 805, 804, 625, 542, 806, 387, 255, 809, - 219, 927, 843, 845, 182, 849, 139 + 282, 263, 284, 41, 285, 288, 295, 84, 293, 928, + 0, 310, 313, 927, 320, 332, 0, 926, 304, 306, + 925, 317, 924, 321, 923, 325, 333, 313, 922, 286, + 335, 337, 338, 921, 339, 341, 342, 346, 343, 347, + 344, 350, 360, 356, 358, 363, 366, 361, 368, 364, + 371, 374, 376, 380, 381, 920, 919, 383, 31, 918, + 384, 917, 916, 408, 385, 386, 388, 412, 915, 399, + 914, 390, 393, 403, 913, 396, 389, 422, 425, 426, + 428, 430, 431, 432, 434, 438, 436, 439, 440, 441, + 442, 447, 451, 457, 450, 912, 448, 949, 462, 474, + + 393, 476, 479, 467, 480, 468, 481, 911, 910, 909, + 482, 483, 486, 488, 490, 492, 493, 494, 495, 499, + 496, 502, 908, 504, 509, 507, 510, 511, 513, 518, + 517, 521, 907, 906, 520, 522, 905, 523, 526, 0, + 530, 528, 543, 524, 542, 545, 546, 529, 548, 553, + 557, 556, 904, 560, 559, 903, 902, 561, 901, 564, + 567, 571, 573, 572, 576, 579, 580, 581, 900, 582, + 899, 583, 587, 898, 587, 590, 897, 588, 594, 593, + 534, 601, 602, 603, 604, 606, 896, 609, 895, 611, + 607, 612, 615, 617, 618, 894, 623, 624, 625, 630, + + 635, 636, 893, 629, 631, 892, 891, 890, 889, 888, + 887, 886, 637, 641, 885, 643, 642, 648, 884, 883, + 882, 646, 649, 650, 653, 659, 881, 660, 661, 662, + 880, 664, 879, 663, 666, 667, 878, 877, 876, 668, + 671, 875, 672, 874, 678, 681, 686, 873, 685, 872, + 871, 870, 869, 682, 684, 868, 693, 695, 867, 866, + 865, 696, 698, 864, 863, 862, 861, 697, 700, 699, + 704, 860, 857, 706, 708, 711, 707, 714, 715, 719, + 718, 848, 722, 723, 726, 733, 725, 735, 737, 847, + 845, 736, 739, 741, 743, 843, 842, 742, 744, 750, + + 745, 759, 841, 749, 840, 754, 746, 761, 767, 768, + 770, 771, 772, 773, 774, 775, 776, 778, 780, 781, + 782, 838, 784, 787, 792, 793, 786, 798, 799, 835, + 800, 803, 834, 804, 806, 808, 810, 814, 815, 819, + 820, 821, 832, 822, 831, 830, 826, 824, 296, 255, + 825, 219, 949, 861, 863, 182, 867, 139 } ; -static yyconst short int yy_def[448] = +static yyconst short int yy_def[459] = { 0, - 442, 1, 442, 442, 442, 442, 443, 444, 445, 442, - 444, 444, 444, 444, 446, 444, 444, 444, 444, 444, - 444, 444, 444, 444, 444, 444, 444, 444, 444, 444, - 444, 444, 444, 444, 444, 444, 443, 442, 444, 442, - 447, 447, 442, 442, 444, 444, 444, 444, 444, 446, - 444, 444, 444, 444, 444, 444, 444, 444, 444, 444, - 444, 444, 444, 444, 444, 444, 444, 444, 444, 444, - 444, 444, 444, 444, 444, 444, 444, 444, 444, 444, - 444, 444, 444, 444, 444, 444, 444, 444, 444, 444, - 444, 444, 444, 444, 444, 444, 444, 444, 444, 444, - - 444, 444, 444, 444, 444, 444, 444, 444, 444, 442, - 447, 447, 442, 444, 444, 444, 49, 444, 444, 444, - 444, 444, 444, 444, 444, 444, 444, 444, 444, 444, - 444, 444, 444, 444, 444, 444, 444, 444, 444, 444, - 444, 444, 444, 444, 444, 444, 444, 444, 444, 444, - 444, 444, 444, 444, 444, 444, 444, 444, 444, 444, - 444, 444, 444, 49, 444, 444, 444, 444, 444, 444, - 444, 444, 444, 444, 444, 444, 444, 444, 444, 444, - 444, 444, 444, 444, 444, 444, 444, 444, 444, 444, - 444, 444, 444, 444, 444, 444, 442, 442, 442, 442, - - 444, 444, 444, 444, 444, 444, 444, 444, 444, 444, - 444, 444, 444, 444, 444, 444, 444, 444, 444, 444, - 444, 444, 444, 444, 444, 444, 444, 444, 444, 444, - 444, 444, 444, 444, 444, 444, 444, 444, 164, 444, - 444, 444, 444, 444, 444, 444, 444, 444, 444, 444, - 444, 444, 444, 444, 444, 444, 444, 444, 444, 444, - 444, 444, 444, 444, 444, 444, 444, 444, 444, 444, - 442, 444, 444, 444, 444, 444, 444, 444, 444, 444, - 444, 444, 444, 444, 444, 444, 444, 444, 444, 444, - 444, 444, 444, 444, 444, 444, 444, 444, 444, 444, - - 444, 444, 444, 444, 444, 444, 444, 444, 444, 444, - 444, 444, 444, 444, 444, 444, 444, 444, 444, 444, - 444, 444, 444, 444, 444, 444, 444, 444, 444, 444, - 444, 444, 444, 444, 444, 444, 444, 444, 444, 444, - 444, 444, 444, 444, 444, 444, 444, 444, 444, 444, - 444, 444, 444, 444, 444, 444, 444, 444, 444, 444, - 444, 444, 444, 444, 444, 444, 444, 444, 444, 444, - 444, 444, 444, 444, 444, 444, 444, 444, 444, 444, - 444, 444, 444, 444, 444, 444, 444, 444, 444, 444, - 444, 444, 444, 444, 444, 444, 444, 444, 444, 444, - - 444, 444, 444, 444, 444, 444, 444, 444, 444, 444, - 444, 444, 444, 444, 444, 444, 444, 444, 444, 444, - 444, 444, 444, 444, 444, 444, 444, 444, 444, 444, - 444, 444, 444, 444, 444, 444, 444, 444, 444, 444, - 444, 0, 442, 442, 442, 442, 442 + 453, 1, 453, 453, 453, 453, 454, 455, 456, 453, + 455, 455, 455, 455, 457, 455, 455, 455, 455, 455, + 455, 455, 455, 455, 455, 455, 455, 455, 455, 455, + 455, 455, 455, 455, 455, 455, 454, 453, 455, 453, + 458, 458, 453, 453, 455, 455, 455, 455, 455, 457, + 455, 455, 455, 455, 455, 455, 455, 455, 455, 455, + 455, 455, 455, 455, 455, 455, 455, 455, 455, 455, + 455, 455, 455, 455, 455, 455, 455, 455, 455, 455, + 455, 455, 455, 455, 455, 455, 455, 455, 455, 455, + 455, 455, 455, 455, 455, 455, 455, 455, 455, 455, + + 455, 455, 455, 455, 455, 455, 455, 455, 455, 453, + 458, 458, 453, 455, 455, 455, 49, 455, 455, 455, + 455, 455, 455, 455, 455, 455, 455, 455, 455, 455, + 455, 455, 455, 455, 455, 455, 455, 455, 455, 455, + 455, 455, 455, 455, 455, 455, 455, 455, 455, 455, + 455, 455, 455, 455, 455, 455, 455, 455, 455, 455, + 455, 455, 455, 49, 455, 455, 455, 455, 455, 455, + 455, 455, 455, 455, 455, 455, 455, 455, 455, 455, + 455, 455, 455, 455, 455, 455, 455, 455, 455, 455, + 455, 455, 455, 455, 455, 455, 455, 453, 453, 453, + + 453, 455, 455, 455, 455, 455, 455, 455, 455, 455, + 455, 455, 455, 455, 455, 455, 455, 455, 455, 455, + 455, 455, 455, 455, 455, 455, 455, 455, 455, 455, + 455, 455, 455, 455, 455, 455, 455, 455, 455, 164, + 455, 455, 455, 455, 455, 455, 455, 455, 455, 455, + 455, 455, 455, 455, 455, 455, 455, 455, 455, 455, + 455, 455, 455, 455, 455, 455, 455, 455, 455, 455, + 455, 455, 453, 455, 455, 455, 455, 455, 455, 455, + 455, 455, 455, 455, 455, 455, 455, 455, 455, 455, + 455, 455, 455, 455, 455, 455, 455, 455, 455, 455, + + 455, 455, 455, 455, 455, 455, 455, 455, 455, 455, + 455, 455, 455, 455, 455, 455, 455, 455, 455, 455, + 455, 455, 455, 455, 455, 455, 455, 455, 455, 455, + 455, 455, 455, 455, 455, 455, 455, 455, 455, 455, + 455, 455, 455, 455, 455, 455, 455, 455, 455, 455, + 455, 455, 455, 455, 455, 455, 455, 455, 455, 455, + 455, 455, 455, 455, 455, 455, 455, 455, 455, 455, + 455, 455, 455, 455, 455, 455, 455, 455, 455, 455, + 455, 455, 455, 455, 455, 455, 455, 455, 455, 455, + 455, 455, 455, 455, 455, 455, 455, 455, 455, 455, + + 455, 455, 455, 455, 455, 455, 455, 455, 455, 455, + 455, 455, 455, 455, 455, 455, 455, 455, 455, 455, + 455, 455, 455, 455, 455, 455, 455, 455, 455, 455, + 455, 455, 455, 455, 455, 455, 455, 455, 455, 455, + 455, 455, 455, 455, 455, 455, 455, 455, 455, 455, + 455, 455, 0, 453, 453, 453, 453, 453 } ; -static yyconst short int yy_nxt[969] = +static yyconst short int yy_nxt[991] = { 0, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 4, 15, 8, 8, 8, 16, 17, 18, 19, @@ -542,13 +545,13 @@ 28, 8, 29, 30, 31, 32, 33, 34, 35, 8, 36, 42, 40, 43, 43, 44, 44, 45, 45, 40, 46, 40, 40, 40, 47, 48, 48, 40, 47, 48, - 48, 40, 237, 40, 188, 40, 40, 40, 40, 81, + 48, 40, 238, 40, 189, 40, 40, 40, 40, 81, 60, 51, 61, 40, 118, 82, 87, 56, 52, 40, 53, 57, 54, 62, 49, 55, 58, 40, 63, 59, 66, 40, 64, 40, 40, 40, 68, 65, 40, 40, 67, 40, 71, 73, 74, 40, 69, 107, 72, 40, - 75, 85, 70, 83, 78, 84, 195, 86, 76, 40, + 75, 85, 70, 83, 78, 84, 196, 86, 76, 40, 40, 40, 40, 77, 96, 105, 134, 79, 112, 112, 40, 109, 114, 80, 88, 40, 40, 97, 106, 108, 98, 111, 89, 43, 43, 90, 123, 99, 91, 92, @@ -565,86 +568,88 @@ 144, 40, 145, 146, 147, 150, 148, 40, 157, 153, 40, 151, 40, 154, 40, 155, 156, 159, 40, 40, 40, 40, 40, 164, 40, 158, 40, 160, 166, 40, - 40, 161, 172, 40, 40, 162, 167, 169, 40, 174, - 170, 40, 163, 171, 168, 40, 40, 173, 165, 180, - 40, 175, 183, 40, 176, 40, 40, 40, 178, 40, - - 189, 190, 177, 184, 194, 40, 206, 182, 185, 179, - 192, 40, 193, 191, 181, 40, 186, 112, 112, 198, - 198, 187, 203, 40, 199, 40, 196, 115, 115, 40, - 199, 40, 116, 204, 205, 40, 200, 201, 116, 202, - 202, 40, 40, 40, 40, 211, 207, 40, 40, 40, - 208, 210, 40, 40, 214, 40, 40, 40, 216, 212, - 40, 217, 213, 40, 40, 209, 215, 40, 221, 222, - 224, 40, 225, 218, 40, 40, 223, 219, 40, 220, - 226, 40, 40, 227, 40, 40, 40, 229, 40, 40, - 40, 40, 232, 228, 40, 230, 233, 40, 40, 40, - - 242, 234, 40, 40, 236, 231, 40, 238, 248, 40, - 40, 254, 235, 239, 239, 247, 253, 239, 239, 40, - 239, 239, 239, 239, 239, 239, 240, 40, 243, 241, - 244, 249, 250, 40, 245, 40, 246, 40, 40, 40, - 40, 40, 251, 40, 252, 40, 255, 40, 40, 259, - 261, 40, 264, 40, 40, 40, 258, 40, 256, 268, - 260, 257, 266, 263, 262, 267, 40, 198, 198, 265, - 271, 271, 199, 270, 202, 202, 40, 40, 199, 40, - 269, 200, 200, 40, 271, 271, 202, 202, 40, 40, - 273, 40, 40, 40, 272, 40, 274, 40, 276, 40, - - 278, 40, 40, 40, 281, 40, 275, 40, 280, 40, - 279, 40, 284, 40, 285, 277, 286, 40, 40, 40, - 282, 40, 289, 283, 40, 40, 287, 290, 288, 40, - 40, 40, 291, 40, 40, 293, 40, 40, 40, 294, - 292, 303, 40, 295, 296, 40, 298, 301, 297, 40, - 302, 40, 40, 40, 305, 40, 40, 299, 307, 300, - 309, 40, 304, 40, 311, 312, 40, 40, 306, 40, - 313, 40, 308, 40, 319, 310, 314, 40, 316, 40, - 40, 315, 317, 318, 320, 40, 40, 40, 40, 40, - 271, 271, 40, 40, 321, 40, 40, 324, 328, 40, - - 329, 322, 327, 330, 331, 40, 323, 40, 40, 40, - 40, 326, 40, 333, 325, 40, 332, 334, 40, 338, - 40, 40, 335, 40, 340, 339, 40, 337, 40, 40, - 40, 40, 336, 40, 40, 341, 40, 342, 345, 347, - 348, 40, 40, 344, 40, 346, 343, 40, 40, 352, - 349, 350, 40, 351, 40, 40, 40, 353, 354, 355, - 40, 40, 40, 357, 360, 40, 40, 359, 40, 40, - 40, 40, 40, 362, 40, 356, 40, 40, 358, 364, - 368, 370, 366, 40, 361, 365, 40, 367, 363, 40, - 40, 40, 373, 372, 369, 374, 375, 371, 40, 40, - - 40, 40, 40, 40, 40, 376, 40, 378, 40, 379, - 377, 40, 40, 380, 381, 40, 382, 383, 40, 40, - 384, 387, 40, 386, 388, 40, 40, 40, 389, 385, - 40, 392, 395, 390, 391, 394, 40, 40, 40, 397, - 40, 396, 40, 40, 40, 40, 40, 393, 40, 399, - 40, 40, 40, 403, 407, 400, 40, 405, 404, 401, - 398, 406, 40, 40, 408, 409, 402, 411, 40, 40, - 40, 40, 40, 40, 40, 410, 40, 417, 40, 412, - 40, 40, 40, 415, 40, 40, 416, 421, 40, 418, - 422, 424, 414, 419, 40, 40, 40, 413, 40, 420, - - 425, 428, 40, 426, 40, 430, 40, 427, 40, 423, - 40, 431, 429, 40, 40, 40, 40, 40, 436, 432, - 40, 40, 40, 40, 434, 433, 440, 40, 40, 40, - 40, 435, 439, 40, 40, 40, 40, 438, 40, 40, - 40, 441, 437, 37, 37, 37, 37, 39, 39, 50, - 40, 50, 50, 40, 40, 40, 40, 40, 40, 40, + 40, 161, 173, 40, 40, 162, 167, 169, 40, 175, + 170, 40, 163, 171, 168, 40, 172, 174, 165, 181, + 40, 176, 184, 40, 177, 40, 40, 40, 179, 40, + + 190, 191, 178, 185, 40, 211, 40, 40, 186, 180, + 183, 195, 193, 192, 194, 40, 187, 40, 182, 112, + 112, 188, 199, 199, 40, 197, 204, 200, 40, 115, + 115, 40, 40, 200, 116, 205, 40, 206, 201, 202, + 116, 203, 203, 40, 40, 207, 40, 210, 40, 40, + 40, 208, 40, 40, 40, 40, 215, 40, 40, 209, + 222, 40, 217, 213, 214, 216, 218, 40, 212, 40, + 223, 40, 40, 225, 40, 40, 220, 40, 219, 40, + 224, 221, 40, 227, 226, 40, 228, 40, 230, 231, + 229, 40, 40, 233, 40, 40, 40, 40, 234, 40, + + 40, 40, 273, 273, 40, 232, 235, 40, 243, 237, + 40, 249, 239, 250, 40, 253, 236, 240, 240, 241, + 242, 240, 240, 40, 240, 240, 240, 240, 240, 240, + 252, 248, 244, 40, 245, 251, 40, 40, 246, 40, + 247, 40, 40, 40, 254, 40, 256, 40, 257, 40, + 40, 40, 40, 40, 261, 255, 263, 266, 40, 40, + 260, 40, 40, 264, 258, 259, 262, 268, 40, 265, + 269, 199, 199, 270, 267, 271, 200, 272, 40, 40, + 201, 201, 200, 273, 273, 203, 203, 40, 203, 203, + 40, 40, 40, 40, 40, 274, 276, 40, 275, 40, + + 278, 40, 280, 40, 40, 40, 40, 40, 283, 277, + 40, 286, 281, 40, 288, 40, 282, 279, 40, 287, + 40, 40, 40, 284, 40, 291, 285, 292, 40, 40, + 290, 40, 40, 40, 40, 40, 289, 40, 295, 40, + 40, 40, 293, 294, 296, 40, 297, 298, 300, 299, + 303, 336, 304, 40, 40, 306, 40, 40, 301, 40, + 302, 305, 307, 312, 40, 309, 311, 40, 40, 313, + 40, 40, 40, 314, 316, 40, 308, 315, 40, 310, + 317, 319, 40, 40, 40, 318, 320, 40, 321, 323, + 40, 40, 40, 40, 40, 322, 273, 273, 40, 40, + + 324, 40, 327, 331, 40, 40, 333, 330, 325, 332, + 334, 326, 40, 40, 40, 40, 329, 40, 40, 328, + 40, 337, 40, 40, 341, 335, 40, 342, 40, 40, + 338, 343, 340, 344, 40, 40, 40, 339, 348, 345, + 40, 40, 40, 351, 350, 347, 40, 40, 40, 346, + 352, 349, 40, 40, 40, 353, 354, 40, 355, 40, + 40, 40, 358, 357, 40, 356, 359, 363, 361, 364, + 40, 40, 40, 40, 40, 40, 360, 40, 40, 40, + 362, 366, 40, 40, 374, 368, 372, 365, 370, 40, + 369, 371, 40, 40, 367, 40, 40, 40, 377, 376, + + 373, 378, 379, 380, 40, 375, 40, 40, 40, 40, + 40, 40, 382, 383, 381, 40, 384, 40, 40, 40, + 385, 386, 40, 387, 388, 40, 40, 389, 392, 40, + 40, 393, 391, 40, 40, 394, 40, 40, 390, 397, + 395, 396, 401, 400, 40, 403, 40, 40, 40, 402, + 40, 398, 40, 40, 40, 40, 40, 40, 399, 405, + 40, 40, 406, 409, 411, 40, 410, 407, 412, 404, + 40, 413, 40, 415, 416, 408, 414, 418, 40, 40, + 417, 40, 40, 40, 40, 40, 40, 40, 421, 40, + 425, 40, 40, 40, 419, 40, 423, 40, 40, 424, + + 429, 430, 426, 40, 40, 422, 427, 433, 420, 40, + 40, 40, 428, 435, 40, 40, 431, 40, 434, 40, + 436, 40, 437, 440, 432, 40, 40, 438, 441, 439, + 40, 40, 40, 40, 442, 40, 40, 40, 447, 444, + 443, 40, 40, 40, 451, 40, 40, 446, 445, 40, + 450, 40, 40, 40, 40, 449, 40, 452, 40, 40, + 448, 37, 37, 37, 37, 39, 39, 50, 40, 50, + 50, 40, 40, 40, 40, 40, 40, 40, 40, 40, 40, 40, 40, 40, 40, 40, 40, 40, 40, 40, 40, 40, 40, 40, 40, 40, 40, 40, 40, 40, + 40, 40, 40, 40, 40, 40, 40, 40, 40, 40, 40, 40, 40, 40, 40, 40, 40, 40, 40, 40, - 40, 40, 40, 40, 40, 40, 40, 40, 40, 40, - 40, 40, 40, 40, 40, 40, 40, 197, 40, 40, - 40, 40, 110, 40, 38, 442, 3, 442, 442, 442, - 442, 442, 442, 442, 442, 442, 442, 442, 442, 442, - 442, 442, 442, 442, 442, 442, 442, 442, 442, 442, - 442, 442, 442, 442, 442, 442, 442, 442, 442, 442, - 442, 442, 442, 442, 442, 442, 442, 442 + 40, 40, 40, 40, 40, 40, 40, 40, 40, 198, + 40, 40, 40, 40, 110, 40, 38, 453, 3, 453, + 453, 453, 453, 453, 453, 453, 453, 453, 453, 453, + 453, 453, 453, 453, 453, 453, 453, 453, 453, 453, + 453, 453, 453, 453, 453, 453, 453, 453, 453, 453, + 453, 453, 453, 453, 453, 453, 453, 453, 453, 453 } ; -static yyconst short int yy_chk[969] = +static yyconst short int yy_chk[991] = { 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, @@ -661,97 +666,99 @@ 24, 28, 21, 27, 25, 27, 108, 28, 24, 31, 33, 35, 36, 24, 31, 33, 64, 25, 42, 42, 55, 36, 46, 25, 30, 46, 30, 31, 33, 35, - 31, 447, 30, 43, 43, 30, 55, 31, 30, 30, + 31, 458, 30, 43, 43, 30, 55, 31, 30, 30, 44, 44, 44, 45, 45, 45, 45, 65, 53, 30, 30, 56, 30, 32, 54, 32, 53, 58, 47, 47, 47, 32, 56, 47, 48, 48, 48, 48, 32, 47, - 32, 65, 32, 54, 445, 58, 60, 32, 49, 49, + 32, 65, 32, 54, 456, 58, 60, 32, 49, 49, 49, 52, 49, 49, 57, 49, 49, 49, 49, 49, 49, 60, 61, 62, 52, 57, 52, 63, 60, 61, 67, 66, 68, 69, 63, 70, 71, 67, 62, 66, 62, 74, 72, 73, 70, 81, 63, 68, 76, 75, - 441, 69, 77, 67, 68, 75, 88, 77, 78, 71, + 452, 69, 77, 67, 68, 75, 88, 77, 78, 71, 72, 80, 73, 74, 74, 76, 74, 79, 81, 77, 82, 76, 83, 78, 85, 79, 80, 83, 86, 87, - 89, 90, 91, 88, 92, 82, 439, 85, 90, 93, + 89, 90, 91, 88, 92, 82, 450, 85, 90, 93, 99, 86, 92, 94, 102, 87, 90, 91, 95, 94, - 91, 96, 87, 91, 90, 98, 100, 93, 89, 99, - 101, 95, 102, 124, 96, 103, 105, 106, 98, 107, + 91, 96, 87, 91, 90, 98, 91, 93, 89, 99, + 100, 95, 102, 101, 96, 103, 105, 130, 98, 106, - 105, 105, 96, 103, 107, 109, 124, 101, 103, 98, - 106, 119, 106, 105, 100, 120, 103, 112, 112, 113, - 113, 103, 119, 131, 113, 122, 109, 115, 115, 115, - 113, 126, 115, 120, 122, 127, 116, 116, 115, 116, - 116, 116, 128, 130, 132, 131, 126, 133, 135, 137, - 127, 130, 138, 136, 135, 139, 140, 145, 137, 132, - 142, 138, 133, 141, 144, 128, 136, 143, 141, 142, - 144, 146, 145, 138, 147, 148, 143, 139, 149, 140, - 146, 150, 151, 147, 152, 153, 154, 149, 155, 158, - 161, 167, 152, 148, 170, 150, 153, 178, 438, 172, - - 167, 154, 179, 165, 158, 151, 166, 161, 172, 175, - 173, 179, 155, 164, 164, 170, 178, 164, 164, 168, - 164, 164, 164, 164, 164, 164, 165, 176, 168, 166, - 168, 173, 175, 177, 168, 181, 168, 180, 182, 183, - 184, 186, 176, 185, 177, 188, 180, 189, 190, 184, - 186, 187, 189, 191, 193, 196, 183, 192, 181, 193, - 185, 182, 191, 188, 187, 192, 194, 198, 198, 190, - 200, 200, 198, 196, 201, 201, 201, 203, 198, 205, - 194, 199, 199, 204, 199, 199, 202, 202, 202, 206, - 204, 210, 211, 214, 203, 212, 205, 213, 210, 215, - - 212, 216, 217, 221, 215, 219, 206, 218, 214, 220, - 213, 226, 218, 223, 219, 211, 220, 224, 225, 227, - 216, 228, 224, 217, 229, 230, 221, 225, 223, 231, - 234, 235, 226, 237, 242, 228, 238, 241, 240, 229, - 227, 242, 243, 230, 231, 244, 235, 240, 234, 245, - 241, 246, 247, 436, 244, 248, 249, 237, 245, 238, - 246, 260, 243, 250, 248, 249, 253, 252, 244, 256, - 250, 258, 245, 259, 260, 247, 252, 262, 256, 261, - 263, 253, 258, 259, 261, 264, 265, 266, 268, 270, - 271, 271, 274, 273, 262, 278, 276, 265, 273, 277, - - 274, 263, 270, 276, 277, 281, 264, 279, 280, 282, - 283, 268, 284, 279, 266, 288, 278, 280, 286, 284, - 289, 290, 281, 291, 288, 286, 292, 283, 295, 293, - 296, 302, 282, 297, 303, 289, 435, 290, 293, 296, - 297, 298, 299, 292, 300, 295, 291, 313, 311, 302, - 298, 299, 314, 300, 315, 319, 321, 303, 311, 313, - 320, 322, 323, 315, 321, 325, 326, 320, 327, 329, - 331, 332, 333, 323, 338, 314, 337, 340, 319, 326, - 332, 337, 329, 342, 322, 327, 343, 331, 325, 351, - 352, 344, 342, 340, 333, 343, 344, 338, 346, 354, - - 358, 364, 359, 366, 365, 346, 367, 352, 370, 354, - 351, 373, 371, 358, 359, 372, 364, 365, 374, 375, - 366, 371, 376, 370, 372, 377, 379, 380, 373, 367, - 382, 376, 380, 374, 375, 379, 381, 383, 384, 382, - 387, 381, 388, 389, 390, 393, 395, 377, 396, 384, - 394, 398, 401, 390, 396, 387, 400, 394, 393, 388, - 383, 395, 402, 403, 398, 400, 389, 402, 404, 405, - 406, 407, 408, 409, 410, 401, 411, 408, 412, 403, - 415, 413, 416, 406, 419, 417, 407, 412, 420, 409, - 413, 416, 405, 410, 418, 421, 423, 404, 425, 411, - - 417, 420, 426, 418, 427, 423, 428, 419, 429, 415, - 430, 425, 421, 431, 432, 434, 433, 437, 430, 426, - 440, 424, 422, 414, 428, 427, 437, 399, 397, 392, - 391, 429, 434, 386, 385, 378, 369, 432, 368, 363, - 362, 440, 431, 443, 443, 443, 443, 444, 444, 446, - 361, 446, 446, 360, 357, 356, 355, 353, 350, 349, - 348, 347, 345, 341, 339, 336, 335, 334, 330, 328, - 324, 318, 317, 316, 312, 310, 309, 308, 307, 306, - 305, 304, 301, 294, 287, 285, 275, 272, 269, 267, - 257, 255, 254, 251, 236, 233, 232, 222, 209, 208, - - 207, 195, 174, 171, 169, 163, 162, 160, 157, 156, - 134, 129, 125, 123, 121, 118, 114, 110, 97, 84, - 59, 39, 37, 8, 7, 3, 442, 442, 442, 442, - 442, 442, 442, 442, 442, 442, 442, 442, 442, 442, - 442, 442, 442, 442, 442, 442, 442, 442, 442, 442, - 442, 442, 442, 442, 442, 442, 442, 442, 442, 442, - 442, 442, 442, 442, 442, 442, 442, 442 + 105, 105, 96, 103, 109, 130, 107, 449, 103, 98, + 101, 107, 106, 105, 106, 119, 103, 120, 100, 112, + 112, 103, 113, 113, 128, 109, 119, 113, 122, 115, + 115, 115, 124, 113, 115, 120, 126, 122, 116, 116, + 115, 116, 116, 116, 127, 124, 131, 128, 132, 133, + 135, 126, 136, 137, 139, 141, 135, 138, 140, 127, + 141, 142, 137, 132, 133, 136, 138, 144, 131, 145, + 142, 143, 148, 144, 146, 150, 139, 147, 138, 149, + 143, 140, 151, 146, 145, 152, 147, 153, 149, 150, + 148, 154, 155, 152, 158, 161, 165, 166, 153, 167, + + 177, 172, 201, 201, 173, 151, 154, 176, 167, 158, + 170, 172, 161, 173, 174, 177, 155, 164, 164, 165, + 166, 164, 164, 168, 164, 164, 164, 164, 164, 164, + 176, 170, 168, 178, 168, 174, 179, 180, 168, 181, + 168, 182, 183, 184, 178, 185, 180, 187, 181, 186, + 188, 189, 190, 191, 185, 179, 187, 190, 192, 197, + 184, 195, 193, 188, 182, 183, 186, 192, 194, 189, + 193, 199, 199, 194, 191, 195, 199, 197, 204, 206, + 200, 200, 199, 200, 200, 202, 202, 202, 203, 203, + 203, 205, 207, 211, 212, 204, 206, 213, 205, 214, + + 211, 215, 213, 216, 217, 218, 219, 221, 216, 207, + 220, 219, 214, 222, 221, 224, 215, 212, 226, 220, + 225, 227, 228, 217, 229, 225, 218, 226, 231, 230, + 224, 235, 232, 236, 238, 244, 222, 239, 229, 242, + 248, 241, 227, 228, 230, 281, 231, 232, 236, 235, + 241, 281, 242, 245, 243, 244, 246, 247, 238, 249, + 239, 243, 245, 248, 250, 246, 247, 252, 251, 249, + 255, 254, 258, 250, 252, 260, 245, 251, 261, 246, + 254, 258, 262, 264, 263, 255, 260, 265, 261, 263, + 266, 267, 268, 270, 272, 262, 273, 273, 275, 278, + + 264, 276, 267, 275, 280, 279, 278, 272, 265, 276, + 279, 266, 282, 283, 284, 285, 270, 286, 291, 268, + 288, 282, 290, 292, 286, 280, 293, 288, 294, 295, + 283, 290, 285, 291, 297, 298, 299, 284, 295, 292, + 304, 300, 305, 299, 298, 294, 301, 302, 313, 293, + 300, 297, 314, 317, 316, 301, 302, 322, 304, 318, + 323, 324, 314, 313, 325, 305, 316, 323, 318, 324, + 326, 328, 329, 330, 334, 332, 317, 335, 336, 340, + 322, 326, 341, 343, 340, 329, 335, 325, 332, 345, + 330, 334, 346, 354, 328, 355, 349, 347, 345, 343, + + 336, 346, 347, 349, 357, 341, 358, 362, 368, 363, + 370, 369, 355, 357, 354, 371, 358, 374, 377, 375, + 362, 363, 376, 368, 369, 378, 379, 370, 375, 381, + 380, 376, 374, 383, 384, 377, 387, 385, 371, 380, + 378, 379, 385, 384, 386, 387, 388, 392, 389, 386, + 393, 381, 394, 398, 395, 399, 401, 407, 383, 389, + 404, 400, 392, 395, 399, 406, 398, 393, 400, 388, + 402, 401, 408, 404, 406, 394, 402, 408, 409, 410, + 407, 411, 412, 413, 414, 415, 416, 417, 411, 418, + 415, 419, 420, 421, 409, 423, 413, 427, 424, 414, + + 419, 420, 416, 425, 426, 412, 417, 424, 410, 428, + 429, 431, 418, 426, 432, 434, 421, 435, 425, 436, + 427, 437, 428, 432, 423, 438, 439, 429, 434, 431, + 440, 441, 442, 444, 435, 448, 451, 447, 440, 437, + 436, 446, 445, 443, 448, 433, 430, 439, 438, 422, + 444, 405, 403, 397, 396, 442, 391, 451, 390, 382, + 441, 454, 454, 454, 454, 455, 455, 457, 373, 457, + 457, 372, 367, 366, 365, 364, 361, 360, 359, 356, + 353, 352, 351, 350, 348, 344, 342, 339, 338, 337, + 333, 331, 327, 321, 320, 319, 315, 312, 311, 310, + + 309, 308, 307, 306, 303, 296, 289, 287, 277, 274, + 271, 269, 259, 257, 256, 253, 237, 234, 233, 223, + 210, 209, 208, 196, 175, 171, 169, 163, 162, 160, + 157, 156, 134, 129, 125, 123, 121, 118, 114, 110, + 97, 84, 59, 39, 37, 8, 7, 3, 453, 453, + 453, 453, 453, 453, 453, 453, 453, 453, 453, 453, + 453, 453, 453, 453, 453, 453, 453, 453, 453, 453, + 453, 453, 453, 453, 453, 453, 453, 453, 453, 453, + 453, 453, 453, 453, 453, 453, 453, 453, 453, 453 } ; static yy_state_type yy_state_buf[YY_BUF_SIZE + 2], *yy_state_ptr; @@ -768,7 +775,7 @@ #define YY_MORE_ADJ 0 #define YY_RESTORE_YY_MORE_OFFSET char *yytext; -#line 1 "/Users/sabre/cvs/llvm/lib/AsmParser/Lexer.l" +#line 1 "/Volumes/Projects/cvs/llvm/lib/AsmParser/Lexer.l" #define INITIAL 0 /*===-- Lexer.l - Scanner for llvm assembly files --------------*- C++ -*--===// // @@ -783,7 +790,7 @@ // //===----------------------------------------------------------------------===*/ #define YY_NEVER_INTERACTIVE 1 -#line 28 "/Users/sabre/cvs/llvm/lib/AsmParser/Lexer.l" +#line 28 "/Volumes/Projects/cvs/llvm/lib/AsmParser/Lexer.l" #include "ParserInternals.h" #include "llvm/Module.h" #include @@ -909,7 +916,7 @@ /* HexIntConstant - Hexadecimal constant generated by the CFE to avoid forcing * it to deal with 64 bit numbers. */ -#line 913 "Lexer.cpp" +#line 920 "Lexer.cpp" /* Macros after this point can all be overridden by user definitions in * section 1. @@ -1060,10 +1067,10 @@ register char *yy_cp, *yy_bp; register int yy_act; -#line 179 "/Users/sabre/cvs/llvm/lib/AsmParser/Lexer.l" +#line 179 "/Volumes/Projects/cvs/llvm/lib/AsmParser/Lexer.l" -#line 1067 "Lexer.cpp" +#line 1074 "Lexer.cpp" if ( yy_init ) { @@ -1111,14 +1118,14 @@ while ( yy_chk[yy_base[yy_current_state] + yy_c] != yy_current_state ) { yy_current_state = (int) yy_def[yy_current_state]; - if ( yy_current_state >= 443 ) + if ( yy_current_state >= 454 ) yy_c = yy_meta[(unsigned int) yy_c]; } yy_current_state = yy_nxt[yy_base[yy_current_state] + (unsigned int) yy_c]; *yy_state_ptr++ = yy_current_state; ++yy_cp; } - while ( yy_current_state != 442 ); + while ( yy_current_state != 453 ); yy_find_action: yy_current_state = *--yy_state_ptr; @@ -1156,476 +1163,481 @@ { /* beginning of action switch */ case 1: YY_RULE_SETUP -#line 181 "/Users/sabre/cvs/llvm/lib/AsmParser/Lexer.l" +#line 181 "/Volumes/Projects/cvs/llvm/lib/AsmParser/Lexer.l" { /* Ignore comments for now */ } YY_BREAK case 2: YY_RULE_SETUP -#line 183 "/Users/sabre/cvs/llvm/lib/AsmParser/Lexer.l" +#line 183 "/Volumes/Projects/cvs/llvm/lib/AsmParser/Lexer.l" { return BEGINTOK; } YY_BREAK case 3: YY_RULE_SETUP -#line 184 "/Users/sabre/cvs/llvm/lib/AsmParser/Lexer.l" +#line 184 "/Volumes/Projects/cvs/llvm/lib/AsmParser/Lexer.l" { return ENDTOK; } YY_BREAK case 4: YY_RULE_SETUP -#line 185 "/Users/sabre/cvs/llvm/lib/AsmParser/Lexer.l" +#line 185 "/Volumes/Projects/cvs/llvm/lib/AsmParser/Lexer.l" { return TRUETOK; } YY_BREAK case 5: YY_RULE_SETUP -#line 186 "/Users/sabre/cvs/llvm/lib/AsmParser/Lexer.l" +#line 186 "/Volumes/Projects/cvs/llvm/lib/AsmParser/Lexer.l" { return FALSETOK; } YY_BREAK case 6: YY_RULE_SETUP -#line 187 "/Users/sabre/cvs/llvm/lib/AsmParser/Lexer.l" +#line 187 "/Volumes/Projects/cvs/llvm/lib/AsmParser/Lexer.l" { return DECLARE; } YY_BREAK case 7: YY_RULE_SETUP -#line 188 "/Users/sabre/cvs/llvm/lib/AsmParser/Lexer.l" +#line 188 "/Volumes/Projects/cvs/llvm/lib/AsmParser/Lexer.l" { return GLOBAL; } YY_BREAK case 8: YY_RULE_SETUP -#line 189 "/Users/sabre/cvs/llvm/lib/AsmParser/Lexer.l" +#line 189 "/Volumes/Projects/cvs/llvm/lib/AsmParser/Lexer.l" { return CONSTANT; } YY_BREAK case 9: YY_RULE_SETUP -#line 190 "/Users/sabre/cvs/llvm/lib/AsmParser/Lexer.l" +#line 190 "/Volumes/Projects/cvs/llvm/lib/AsmParser/Lexer.l" { return INTERNAL; } YY_BREAK case 10: YY_RULE_SETUP -#line 191 "/Users/sabre/cvs/llvm/lib/AsmParser/Lexer.l" +#line 191 "/Volumes/Projects/cvs/llvm/lib/AsmParser/Lexer.l" { return LINKONCE; } YY_BREAK case 11: YY_RULE_SETUP -#line 192 "/Users/sabre/cvs/llvm/lib/AsmParser/Lexer.l" +#line 192 "/Volumes/Projects/cvs/llvm/lib/AsmParser/Lexer.l" { return WEAK; } YY_BREAK case 12: YY_RULE_SETUP -#line 193 "/Users/sabre/cvs/llvm/lib/AsmParser/Lexer.l" +#line 193 "/Volumes/Projects/cvs/llvm/lib/AsmParser/Lexer.l" { return APPENDING; } YY_BREAK case 13: YY_RULE_SETUP -#line 194 "/Users/sabre/cvs/llvm/lib/AsmParser/Lexer.l" +#line 194 "/Volumes/Projects/cvs/llvm/lib/AsmParser/Lexer.l" { return EXTERNAL; } /* Deprecated, turn into external */ YY_BREAK case 14: YY_RULE_SETUP -#line 195 "/Users/sabre/cvs/llvm/lib/AsmParser/Lexer.l" +#line 195 "/Volumes/Projects/cvs/llvm/lib/AsmParser/Lexer.l" { return EXTERNAL; } YY_BREAK case 15: YY_RULE_SETUP -#line 196 "/Users/sabre/cvs/llvm/lib/AsmParser/Lexer.l" +#line 196 "/Volumes/Projects/cvs/llvm/lib/AsmParser/Lexer.l" { return IMPLEMENTATION; } YY_BREAK case 16: YY_RULE_SETUP -#line 197 "/Users/sabre/cvs/llvm/lib/AsmParser/Lexer.l" +#line 197 "/Volumes/Projects/cvs/llvm/lib/AsmParser/Lexer.l" { return ZEROINITIALIZER; } YY_BREAK case 17: YY_RULE_SETUP -#line 198 "/Users/sabre/cvs/llvm/lib/AsmParser/Lexer.l" +#line 198 "/Volumes/Projects/cvs/llvm/lib/AsmParser/Lexer.l" { return DOTDOTDOT; } YY_BREAK case 18: YY_RULE_SETUP -#line 199 "/Users/sabre/cvs/llvm/lib/AsmParser/Lexer.l" +#line 199 "/Volumes/Projects/cvs/llvm/lib/AsmParser/Lexer.l" { return UNDEF; } YY_BREAK case 19: YY_RULE_SETUP -#line 200 "/Users/sabre/cvs/llvm/lib/AsmParser/Lexer.l" +#line 200 "/Volumes/Projects/cvs/llvm/lib/AsmParser/Lexer.l" { return NULL_TOK; } YY_BREAK case 20: YY_RULE_SETUP -#line 201 "/Users/sabre/cvs/llvm/lib/AsmParser/Lexer.l" +#line 201 "/Volumes/Projects/cvs/llvm/lib/AsmParser/Lexer.l" { return TO; } YY_BREAK case 21: YY_RULE_SETUP -#line 202 "/Users/sabre/cvs/llvm/lib/AsmParser/Lexer.l" +#line 202 "/Volumes/Projects/cvs/llvm/lib/AsmParser/Lexer.l" { RET_TOK(TermOpVal, Unwind, UNWIND); } YY_BREAK case 22: YY_RULE_SETUP -#line 203 "/Users/sabre/cvs/llvm/lib/AsmParser/Lexer.l" +#line 203 "/Volumes/Projects/cvs/llvm/lib/AsmParser/Lexer.l" { return NOT; } /* Deprecated, turned into XOR */ YY_BREAK case 23: YY_RULE_SETUP -#line 204 "/Users/sabre/cvs/llvm/lib/AsmParser/Lexer.l" +#line 204 "/Volumes/Projects/cvs/llvm/lib/AsmParser/Lexer.l" { return TAIL; } YY_BREAK case 24: YY_RULE_SETUP -#line 205 "/Users/sabre/cvs/llvm/lib/AsmParser/Lexer.l" +#line 205 "/Volumes/Projects/cvs/llvm/lib/AsmParser/Lexer.l" { return TARGET; } YY_BREAK case 25: YY_RULE_SETUP -#line 206 "/Users/sabre/cvs/llvm/lib/AsmParser/Lexer.l" +#line 206 "/Volumes/Projects/cvs/llvm/lib/AsmParser/Lexer.l" { return TRIPLE; } YY_BREAK case 26: YY_RULE_SETUP -#line 207 "/Users/sabre/cvs/llvm/lib/AsmParser/Lexer.l" +#line 207 "/Volumes/Projects/cvs/llvm/lib/AsmParser/Lexer.l" { return DEPLIBS; } YY_BREAK case 27: YY_RULE_SETUP -#line 208 "/Users/sabre/cvs/llvm/lib/AsmParser/Lexer.l" +#line 208 "/Volumes/Projects/cvs/llvm/lib/AsmParser/Lexer.l" { return ENDIAN; } YY_BREAK case 28: YY_RULE_SETUP -#line 209 "/Users/sabre/cvs/llvm/lib/AsmParser/Lexer.l" +#line 209 "/Volumes/Projects/cvs/llvm/lib/AsmParser/Lexer.l" { return POINTERSIZE; } YY_BREAK case 29: YY_RULE_SETUP -#line 210 "/Users/sabre/cvs/llvm/lib/AsmParser/Lexer.l" +#line 210 "/Volumes/Projects/cvs/llvm/lib/AsmParser/Lexer.l" { return LITTLE; } YY_BREAK case 30: YY_RULE_SETUP -#line 211 "/Users/sabre/cvs/llvm/lib/AsmParser/Lexer.l" +#line 211 "/Volumes/Projects/cvs/llvm/lib/AsmParser/Lexer.l" { return BIG; } YY_BREAK case 31: YY_RULE_SETUP -#line 212 "/Users/sabre/cvs/llvm/lib/AsmParser/Lexer.l" +#line 212 "/Volumes/Projects/cvs/llvm/lib/AsmParser/Lexer.l" { return VOLATILE; } YY_BREAK case 32: YY_RULE_SETUP -#line 213 "/Users/sabre/cvs/llvm/lib/AsmParser/Lexer.l" +#line 213 "/Volumes/Projects/cvs/llvm/lib/AsmParser/Lexer.l" { return ALIGN; } YY_BREAK case 33: YY_RULE_SETUP -#line 214 "/Users/sabre/cvs/llvm/lib/AsmParser/Lexer.l" +#line 214 "/Volumes/Projects/cvs/llvm/lib/AsmParser/Lexer.l" { return SECTION; } YY_BREAK case 34: YY_RULE_SETUP -#line 215 "/Users/sabre/cvs/llvm/lib/AsmParser/Lexer.l" +#line 215 "/Volumes/Projects/cvs/llvm/lib/AsmParser/Lexer.l" { return MODULE; } YY_BREAK case 35: YY_RULE_SETUP -#line 216 "/Users/sabre/cvs/llvm/lib/AsmParser/Lexer.l" +#line 216 "/Volumes/Projects/cvs/llvm/lib/AsmParser/Lexer.l" { return ASM_TOK; } YY_BREAK case 36: YY_RULE_SETUP -#line 217 "/Users/sabre/cvs/llvm/lib/AsmParser/Lexer.l" +#line 217 "/Volumes/Projects/cvs/llvm/lib/AsmParser/Lexer.l" { return SIDEEFFECT; } YY_BREAK case 37: YY_RULE_SETUP -#line 219 "/Users/sabre/cvs/llvm/lib/AsmParser/Lexer.l" +#line 219 "/Volumes/Projects/cvs/llvm/lib/AsmParser/Lexer.l" { return CC_TOK; } YY_BREAK case 38: YY_RULE_SETUP -#line 220 "/Users/sabre/cvs/llvm/lib/AsmParser/Lexer.l" +#line 220 "/Volumes/Projects/cvs/llvm/lib/AsmParser/Lexer.l" { return CCC_TOK; } YY_BREAK case 39: YY_RULE_SETUP -#line 221 "/Users/sabre/cvs/llvm/lib/AsmParser/Lexer.l" +#line 221 "/Volumes/Projects/cvs/llvm/lib/AsmParser/Lexer.l" { return FASTCC_TOK; } YY_BREAK case 40: YY_RULE_SETUP -#line 222 "/Users/sabre/cvs/llvm/lib/AsmParser/Lexer.l" +#line 222 "/Volumes/Projects/cvs/llvm/lib/AsmParser/Lexer.l" { return COLDCC_TOK; } YY_BREAK case 41: YY_RULE_SETUP -#line 224 "/Users/sabre/cvs/llvm/lib/AsmParser/Lexer.l" +#line 224 "/Volumes/Projects/cvs/llvm/lib/AsmParser/Lexer.l" { llvmAsmlval.PrimType = Type::VoidTy ; return VOID; } YY_BREAK case 42: YY_RULE_SETUP -#line 225 "/Users/sabre/cvs/llvm/lib/AsmParser/Lexer.l" +#line 225 "/Volumes/Projects/cvs/llvm/lib/AsmParser/Lexer.l" { llvmAsmlval.PrimType = Type::BoolTy ; return BOOL; } YY_BREAK case 43: YY_RULE_SETUP -#line 226 "/Users/sabre/cvs/llvm/lib/AsmParser/Lexer.l" +#line 226 "/Volumes/Projects/cvs/llvm/lib/AsmParser/Lexer.l" { llvmAsmlval.PrimType = Type::SByteTy ; return SBYTE; } YY_BREAK case 44: YY_RULE_SETUP -#line 227 "/Users/sabre/cvs/llvm/lib/AsmParser/Lexer.l" +#line 227 "/Volumes/Projects/cvs/llvm/lib/AsmParser/Lexer.l" { llvmAsmlval.PrimType = Type::UByteTy ; return UBYTE; } YY_BREAK case 45: YY_RULE_SETUP -#line 228 "/Users/sabre/cvs/llvm/lib/AsmParser/Lexer.l" +#line 228 "/Volumes/Projects/cvs/llvm/lib/AsmParser/Lexer.l" { llvmAsmlval.PrimType = Type::ShortTy ; return SHORT; } YY_BREAK case 46: YY_RULE_SETUP -#line 229 "/Users/sabre/cvs/llvm/lib/AsmParser/Lexer.l" +#line 229 "/Volumes/Projects/cvs/llvm/lib/AsmParser/Lexer.l" { llvmAsmlval.PrimType = Type::UShortTy; return USHORT; } YY_BREAK case 47: YY_RULE_SETUP -#line 230 "/Users/sabre/cvs/llvm/lib/AsmParser/Lexer.l" +#line 230 "/Volumes/Projects/cvs/llvm/lib/AsmParser/Lexer.l" { llvmAsmlval.PrimType = Type::IntTy ; return INT; } YY_BREAK case 48: YY_RULE_SETUP -#line 231 "/Users/sabre/cvs/llvm/lib/AsmParser/Lexer.l" +#line 231 "/Volumes/Projects/cvs/llvm/lib/AsmParser/Lexer.l" { llvmAsmlval.PrimType = Type::UIntTy ; return UINT; } YY_BREAK case 49: YY_RULE_SETUP -#line 232 "/Users/sabre/cvs/llvm/lib/AsmParser/Lexer.l" +#line 232 "/Volumes/Projects/cvs/llvm/lib/AsmParser/Lexer.l" { llvmAsmlval.PrimType = Type::LongTy ; return LONG; } YY_BREAK case 50: YY_RULE_SETUP -#line 233 "/Users/sabre/cvs/llvm/lib/AsmParser/Lexer.l" +#line 233 "/Volumes/Projects/cvs/llvm/lib/AsmParser/Lexer.l" { llvmAsmlval.PrimType = Type::ULongTy ; return ULONG; } YY_BREAK case 51: YY_RULE_SETUP -#line 234 "/Users/sabre/cvs/llvm/lib/AsmParser/Lexer.l" +#line 234 "/Volumes/Projects/cvs/llvm/lib/AsmParser/Lexer.l" { llvmAsmlval.PrimType = Type::FloatTy ; return FLOAT; } YY_BREAK case 52: YY_RULE_SETUP -#line 235 "/Users/sabre/cvs/llvm/lib/AsmParser/Lexer.l" +#line 235 "/Volumes/Projects/cvs/llvm/lib/AsmParser/Lexer.l" { llvmAsmlval.PrimType = Type::DoubleTy; return DOUBLE; } YY_BREAK case 53: YY_RULE_SETUP -#line 236 "/Users/sabre/cvs/llvm/lib/AsmParser/Lexer.l" +#line 236 "/Volumes/Projects/cvs/llvm/lib/AsmParser/Lexer.l" { llvmAsmlval.PrimType = Type::LabelTy ; return LABEL; } YY_BREAK case 54: YY_RULE_SETUP -#line 237 "/Users/sabre/cvs/llvm/lib/AsmParser/Lexer.l" +#line 237 "/Volumes/Projects/cvs/llvm/lib/AsmParser/Lexer.l" { return TYPE; } YY_BREAK case 55: YY_RULE_SETUP -#line 238 "/Users/sabre/cvs/llvm/lib/AsmParser/Lexer.l" +#line 238 "/Volumes/Projects/cvs/llvm/lib/AsmParser/Lexer.l" { return OPAQUE; } YY_BREAK case 56: YY_RULE_SETUP -#line 240 "/Users/sabre/cvs/llvm/lib/AsmParser/Lexer.l" +#line 240 "/Volumes/Projects/cvs/llvm/lib/AsmParser/Lexer.l" { RET_TOK(BinaryOpVal, Add, ADD); } YY_BREAK case 57: YY_RULE_SETUP -#line 241 "/Users/sabre/cvs/llvm/lib/AsmParser/Lexer.l" +#line 241 "/Volumes/Projects/cvs/llvm/lib/AsmParser/Lexer.l" { RET_TOK(BinaryOpVal, Sub, SUB); } YY_BREAK case 58: YY_RULE_SETUP -#line 242 "/Users/sabre/cvs/llvm/lib/AsmParser/Lexer.l" +#line 242 "/Volumes/Projects/cvs/llvm/lib/AsmParser/Lexer.l" { RET_TOK(BinaryOpVal, Mul, MUL); } YY_BREAK case 59: YY_RULE_SETUP -#line 243 "/Users/sabre/cvs/llvm/lib/AsmParser/Lexer.l" +#line 243 "/Volumes/Projects/cvs/llvm/lib/AsmParser/Lexer.l" { RET_TOK(BinaryOpVal, Div, DIV); } YY_BREAK case 60: YY_RULE_SETUP -#line 244 "/Users/sabre/cvs/llvm/lib/AsmParser/Lexer.l" +#line 244 "/Volumes/Projects/cvs/llvm/lib/AsmParser/Lexer.l" { RET_TOK(BinaryOpVal, Rem, REM); } YY_BREAK case 61: YY_RULE_SETUP -#line 245 "/Users/sabre/cvs/llvm/lib/AsmParser/Lexer.l" +#line 245 "/Volumes/Projects/cvs/llvm/lib/AsmParser/Lexer.l" { RET_TOK(BinaryOpVal, And, AND); } YY_BREAK case 62: YY_RULE_SETUP -#line 246 "/Users/sabre/cvs/llvm/lib/AsmParser/Lexer.l" +#line 246 "/Volumes/Projects/cvs/llvm/lib/AsmParser/Lexer.l" { RET_TOK(BinaryOpVal, Or , OR ); } YY_BREAK case 63: YY_RULE_SETUP -#line 247 "/Users/sabre/cvs/llvm/lib/AsmParser/Lexer.l" +#line 247 "/Volumes/Projects/cvs/llvm/lib/AsmParser/Lexer.l" { RET_TOK(BinaryOpVal, Xor, XOR); } YY_BREAK case 64: YY_RULE_SETUP -#line 248 "/Users/sabre/cvs/llvm/lib/AsmParser/Lexer.l" +#line 248 "/Volumes/Projects/cvs/llvm/lib/AsmParser/Lexer.l" { RET_TOK(BinaryOpVal, SetNE, SETNE); } YY_BREAK case 65: YY_RULE_SETUP -#line 249 "/Users/sabre/cvs/llvm/lib/AsmParser/Lexer.l" +#line 249 "/Volumes/Projects/cvs/llvm/lib/AsmParser/Lexer.l" { RET_TOK(BinaryOpVal, SetEQ, SETEQ); } YY_BREAK case 66: YY_RULE_SETUP -#line 250 "/Users/sabre/cvs/llvm/lib/AsmParser/Lexer.l" +#line 250 "/Volumes/Projects/cvs/llvm/lib/AsmParser/Lexer.l" { RET_TOK(BinaryOpVal, SetLT, SETLT); } YY_BREAK case 67: YY_RULE_SETUP -#line 251 "/Users/sabre/cvs/llvm/lib/AsmParser/Lexer.l" +#line 251 "/Volumes/Projects/cvs/llvm/lib/AsmParser/Lexer.l" { RET_TOK(BinaryOpVal, SetGT, SETGT); } YY_BREAK case 68: YY_RULE_SETUP -#line 252 "/Users/sabre/cvs/llvm/lib/AsmParser/Lexer.l" +#line 252 "/Volumes/Projects/cvs/llvm/lib/AsmParser/Lexer.l" { RET_TOK(BinaryOpVal, SetLE, SETLE); } YY_BREAK case 69: YY_RULE_SETUP -#line 253 "/Users/sabre/cvs/llvm/lib/AsmParser/Lexer.l" +#line 253 "/Volumes/Projects/cvs/llvm/lib/AsmParser/Lexer.l" { RET_TOK(BinaryOpVal, SetGE, SETGE); } YY_BREAK case 70: YY_RULE_SETUP -#line 255 "/Users/sabre/cvs/llvm/lib/AsmParser/Lexer.l" +#line 255 "/Volumes/Projects/cvs/llvm/lib/AsmParser/Lexer.l" { RET_TOK(OtherOpVal, PHI, PHI_TOK); } YY_BREAK case 71: YY_RULE_SETUP -#line 256 "/Users/sabre/cvs/llvm/lib/AsmParser/Lexer.l" +#line 256 "/Volumes/Projects/cvs/llvm/lib/AsmParser/Lexer.l" { RET_TOK(OtherOpVal, Call, CALL); } YY_BREAK case 72: YY_RULE_SETUP -#line 257 "/Users/sabre/cvs/llvm/lib/AsmParser/Lexer.l" +#line 257 "/Volumes/Projects/cvs/llvm/lib/AsmParser/Lexer.l" { RET_TOK(OtherOpVal, Cast, CAST); } YY_BREAK case 73: YY_RULE_SETUP -#line 258 "/Users/sabre/cvs/llvm/lib/AsmParser/Lexer.l" +#line 258 "/Volumes/Projects/cvs/llvm/lib/AsmParser/Lexer.l" { RET_TOK(OtherOpVal, Select, SELECT); } YY_BREAK case 74: YY_RULE_SETUP -#line 259 "/Users/sabre/cvs/llvm/lib/AsmParser/Lexer.l" +#line 259 "/Volumes/Projects/cvs/llvm/lib/AsmParser/Lexer.l" { RET_TOK(OtherOpVal, Shl, SHL); } YY_BREAK case 75: YY_RULE_SETUP -#line 260 "/Users/sabre/cvs/llvm/lib/AsmParser/Lexer.l" +#line 260 "/Volumes/Projects/cvs/llvm/lib/AsmParser/Lexer.l" { RET_TOK(OtherOpVal, Shr, SHR); } YY_BREAK case 76: YY_RULE_SETUP -#line 261 "/Users/sabre/cvs/llvm/lib/AsmParser/Lexer.l" +#line 261 "/Volumes/Projects/cvs/llvm/lib/AsmParser/Lexer.l" { return VANEXT_old; } YY_BREAK case 77: YY_RULE_SETUP -#line 262 "/Users/sabre/cvs/llvm/lib/AsmParser/Lexer.l" +#line 262 "/Volumes/Projects/cvs/llvm/lib/AsmParser/Lexer.l" { return VAARG_old; } YY_BREAK case 78: YY_RULE_SETUP -#line 263 "/Users/sabre/cvs/llvm/lib/AsmParser/Lexer.l" +#line 263 "/Volumes/Projects/cvs/llvm/lib/AsmParser/Lexer.l" { RET_TOK(OtherOpVal, VAArg , VAARG); } YY_BREAK case 79: YY_RULE_SETUP -#line 264 "/Users/sabre/cvs/llvm/lib/AsmParser/Lexer.l" +#line 264 "/Volumes/Projects/cvs/llvm/lib/AsmParser/Lexer.l" { RET_TOK(TermOpVal, Ret, RET); } YY_BREAK case 80: YY_RULE_SETUP -#line 265 "/Users/sabre/cvs/llvm/lib/AsmParser/Lexer.l" +#line 265 "/Volumes/Projects/cvs/llvm/lib/AsmParser/Lexer.l" { RET_TOK(TermOpVal, Br, BR); } YY_BREAK case 81: YY_RULE_SETUP -#line 266 "/Users/sabre/cvs/llvm/lib/AsmParser/Lexer.l" +#line 266 "/Volumes/Projects/cvs/llvm/lib/AsmParser/Lexer.l" { RET_TOK(TermOpVal, Switch, SWITCH); } YY_BREAK case 82: YY_RULE_SETUP -#line 267 "/Users/sabre/cvs/llvm/lib/AsmParser/Lexer.l" +#line 267 "/Volumes/Projects/cvs/llvm/lib/AsmParser/Lexer.l" { RET_TOK(TermOpVal, Invoke, INVOKE); } YY_BREAK case 83: YY_RULE_SETUP -#line 268 "/Users/sabre/cvs/llvm/lib/AsmParser/Lexer.l" +#line 268 "/Volumes/Projects/cvs/llvm/lib/AsmParser/Lexer.l" { RET_TOK(TermOpVal, Unwind, UNWIND); } YY_BREAK case 84: YY_RULE_SETUP -#line 269 "/Users/sabre/cvs/llvm/lib/AsmParser/Lexer.l" +#line 269 "/Volumes/Projects/cvs/llvm/lib/AsmParser/Lexer.l" { RET_TOK(TermOpVal, Unreachable, UNREACHABLE); } YY_BREAK case 85: YY_RULE_SETUP -#line 271 "/Users/sabre/cvs/llvm/lib/AsmParser/Lexer.l" +#line 271 "/Volumes/Projects/cvs/llvm/lib/AsmParser/Lexer.l" { RET_TOK(MemOpVal, Malloc, MALLOC); } YY_BREAK case 86: YY_RULE_SETUP -#line 272 "/Users/sabre/cvs/llvm/lib/AsmParser/Lexer.l" +#line 272 "/Volumes/Projects/cvs/llvm/lib/AsmParser/Lexer.l" { RET_TOK(MemOpVal, Alloca, ALLOCA); } YY_BREAK case 87: YY_RULE_SETUP -#line 273 "/Users/sabre/cvs/llvm/lib/AsmParser/Lexer.l" +#line 273 "/Volumes/Projects/cvs/llvm/lib/AsmParser/Lexer.l" { RET_TOK(MemOpVal, Free, FREE); } YY_BREAK case 88: YY_RULE_SETUP -#line 274 "/Users/sabre/cvs/llvm/lib/AsmParser/Lexer.l" +#line 274 "/Volumes/Projects/cvs/llvm/lib/AsmParser/Lexer.l" { RET_TOK(MemOpVal, Load, LOAD); } YY_BREAK case 89: YY_RULE_SETUP -#line 275 "/Users/sabre/cvs/llvm/lib/AsmParser/Lexer.l" +#line 275 "/Volumes/Projects/cvs/llvm/lib/AsmParser/Lexer.l" { RET_TOK(MemOpVal, Store, STORE); } YY_BREAK case 90: YY_RULE_SETUP -#line 276 "/Users/sabre/cvs/llvm/lib/AsmParser/Lexer.l" +#line 276 "/Volumes/Projects/cvs/llvm/lib/AsmParser/Lexer.l" { RET_TOK(MemOpVal, GetElementPtr, GETELEMENTPTR); } YY_BREAK case 91: YY_RULE_SETUP -#line 278 "/Users/sabre/cvs/llvm/lib/AsmParser/Lexer.l" +#line 278 "/Volumes/Projects/cvs/llvm/lib/AsmParser/Lexer.l" { RET_TOK(OtherOpVal, ExtractElement, EXTRACTELEMENT); } YY_BREAK case 92: YY_RULE_SETUP -#line 279 "/Users/sabre/cvs/llvm/lib/AsmParser/Lexer.l" +#line 279 "/Volumes/Projects/cvs/llvm/lib/AsmParser/Lexer.l" { RET_TOK(OtherOpVal, InsertElement, INSERTELEMENT); } YY_BREAK case 93: YY_RULE_SETUP -#line 282 "/Users/sabre/cvs/llvm/lib/AsmParser/Lexer.l" +#line 280 "/Volumes/Projects/cvs/llvm/lib/AsmParser/Lexer.l" +{ RET_TOK(OtherOpVal, ShuffleVector, SHUFFLEVECTOR); } + YY_BREAK +case 94: +YY_RULE_SETUP +#line 283 "/Volumes/Projects/cvs/llvm/lib/AsmParser/Lexer.l" { UnEscapeLexed(yytext+1); llvmAsmlval.StrVal = strdup(yytext+1); // Skip % return VAR_ID; } YY_BREAK -case 94: +case 95: YY_RULE_SETUP -#line 287 "/Users/sabre/cvs/llvm/lib/AsmParser/Lexer.l" +#line 288 "/Volumes/Projects/cvs/llvm/lib/AsmParser/Lexer.l" { yytext[strlen(yytext)-1] = 0; // nuke colon UnEscapeLexed(yytext); @@ -1633,9 +1645,9 @@ return LABELSTR; } YY_BREAK -case 95: +case 96: YY_RULE_SETUP -#line 293 "/Users/sabre/cvs/llvm/lib/AsmParser/Lexer.l" +#line 294 "/Volumes/Projects/cvs/llvm/lib/AsmParser/Lexer.l" { yytext[strlen(yytext)-2] = 0; // nuke colon, end quote UnEscapeLexed(yytext+1); @@ -1643,9 +1655,9 @@ return LABELSTR; } YY_BREAK -case 96: +case 97: YY_RULE_SETUP -#line 300 "/Users/sabre/cvs/llvm/lib/AsmParser/Lexer.l" +#line 301 "/Volumes/Projects/cvs/llvm/lib/AsmParser/Lexer.l" { // Note that we cannot unescape a string constant here! The // string constant might contain a \00 which would not be // understood by the string stuff. It is valid to make a @@ -1656,14 +1668,14 @@ return STRINGCONSTANT; } YY_BREAK -case 97: +case 98: YY_RULE_SETUP -#line 311 "/Users/sabre/cvs/llvm/lib/AsmParser/Lexer.l" +#line 312 "/Volumes/Projects/cvs/llvm/lib/AsmParser/Lexer.l" { llvmAsmlval.UInt64Val = atoull(yytext); return EUINT64VAL; } YY_BREAK -case 98: +case 99: YY_RULE_SETUP -#line 312 "/Users/sabre/cvs/llvm/lib/AsmParser/Lexer.l" +#line 313 "/Volumes/Projects/cvs/llvm/lib/AsmParser/Lexer.l" { uint64_t Val = atoull(yytext+1); // +1: we have bigger negative range @@ -1673,17 +1685,17 @@ return ESINT64VAL; } YY_BREAK -case 99: +case 100: YY_RULE_SETUP -#line 320 "/Users/sabre/cvs/llvm/lib/AsmParser/Lexer.l" +#line 321 "/Volumes/Projects/cvs/llvm/lib/AsmParser/Lexer.l" { llvmAsmlval.UInt64Val = HexIntToVal(yytext+3); return yytext[0] == 's' ? ESINT64VAL : EUINT64VAL; } YY_BREAK -case 100: +case 101: YY_RULE_SETUP -#line 325 "/Users/sabre/cvs/llvm/lib/AsmParser/Lexer.l" +#line 326 "/Volumes/Projects/cvs/llvm/lib/AsmParser/Lexer.l" { uint64_t Val = atoull(yytext+1); if ((unsigned)Val != Val) @@ -1692,9 +1704,9 @@ return UINTVAL; } YY_BREAK -case 101: +case 102: YY_RULE_SETUP -#line 332 "/Users/sabre/cvs/llvm/lib/AsmParser/Lexer.l" +#line 333 "/Volumes/Projects/cvs/llvm/lib/AsmParser/Lexer.l" { uint64_t Val = atoull(yytext+2); // +1: we have bigger negative range @@ -1704,18 +1716,18 @@ return SINTVAL; } YY_BREAK -case 102: +case 103: YY_RULE_SETUP -#line 341 "/Users/sabre/cvs/llvm/lib/AsmParser/Lexer.l" +#line 342 "/Volumes/Projects/cvs/llvm/lib/AsmParser/Lexer.l" { llvmAsmlval.FPVal = atof(yytext); return FPVAL; } YY_BREAK -case 103: +case 104: YY_RULE_SETUP -#line 342 "/Users/sabre/cvs/llvm/lib/AsmParser/Lexer.l" +#line 343 "/Volumes/Projects/cvs/llvm/lib/AsmParser/Lexer.l" { llvmAsmlval.FPVal = HexToFP(yytext); return FPVAL; } YY_BREAK case YY_STATE_EOF(INITIAL): -#line 344 "/Users/sabre/cvs/llvm/lib/AsmParser/Lexer.l" +#line 345 "/Volumes/Projects/cvs/llvm/lib/AsmParser/Lexer.l" { /* Make sure to free the internal buffers for flex when we are * done reading our input! @@ -1724,22 +1736,22 @@ return EOF; } YY_BREAK -case 104: +case 105: YY_RULE_SETUP -#line 352 "/Users/sabre/cvs/llvm/lib/AsmParser/Lexer.l" +#line 353 "/Volumes/Projects/cvs/llvm/lib/AsmParser/Lexer.l" { /* Ignore whitespace */ } YY_BREAK -case 105: +case 106: YY_RULE_SETUP -#line 353 "/Users/sabre/cvs/llvm/lib/AsmParser/Lexer.l" +#line 354 "/Volumes/Projects/cvs/llvm/lib/AsmParser/Lexer.l" { return yytext[0]; } YY_BREAK -case 106: +case 107: YY_RULE_SETUP -#line 355 "/Users/sabre/cvs/llvm/lib/AsmParser/Lexer.l" +#line 356 "/Volumes/Projects/cvs/llvm/lib/AsmParser/Lexer.l" YY_FATAL_ERROR( "flex scanner jammed" ); YY_BREAK -#line 1743 "Lexer.cpp" +#line 1755 "Lexer.cpp" case YY_END_OF_BUFFER: { @@ -2026,7 +2038,7 @@ while ( yy_chk[yy_base[yy_current_state] + yy_c] != yy_current_state ) { yy_current_state = (int) yy_def[yy_current_state]; - if ( yy_current_state >= 443 ) + if ( yy_current_state >= 454 ) yy_c = yy_meta[(unsigned int) yy_c]; } yy_current_state = yy_nxt[yy_base[yy_current_state] + (unsigned int) yy_c]; @@ -2056,11 +2068,11 @@ while ( yy_chk[yy_base[yy_current_state] + yy_c] != yy_current_state ) { yy_current_state = (int) yy_def[yy_current_state]; - if ( yy_current_state >= 443 ) + if ( yy_current_state >= 454 ) yy_c = yy_meta[(unsigned int) yy_c]; } yy_current_state = yy_nxt[yy_base[yy_current_state] + (unsigned int) yy_c]; - yy_is_jam = (yy_current_state == 442); + yy_is_jam = (yy_current_state == 453); if ( ! yy_is_jam ) *yy_state_ptr++ = yy_current_state; @@ -2621,6 +2633,6 @@ return 0; } #endif -#line 355 "/Users/sabre/cvs/llvm/lib/AsmParser/Lexer.l" +#line 356 "/Volumes/Projects/cvs/llvm/lib/AsmParser/Lexer.l" Index: llvm/lib/AsmParser/Lexer.l.cvs diff -u llvm/lib/AsmParser/Lexer.l.cvs:1.2 llvm/lib/AsmParser/Lexer.l.cvs:1.3 --- llvm/lib/AsmParser/Lexer.l.cvs:1.2 Wed Feb 15 01:02:59 2006 +++ llvm/lib/AsmParser/Lexer.l.cvs Fri Apr 7 20:18:56 2006 @@ -277,6 +277,7 @@ extractelement { RET_TOK(OtherOpVal, ExtractElement, EXTRACTELEMENT); } insertelement { RET_TOK(OtherOpVal, InsertElement, INSERTELEMENT); } +shufflevector { RET_TOK(OtherOpVal, ShuffleVector, SHUFFLEVECTOR); } {VarID} { Index: llvm/lib/AsmParser/llvmAsmParser.cpp.cvs diff -u llvm/lib/AsmParser/llvmAsmParser.cpp.cvs:1.2 llvm/lib/AsmParser/llvmAsmParser.cpp.cvs:1.3 --- llvm/lib/AsmParser/llvmAsmParser.cpp.cvs:1.2 Sat Mar 4 01:53:40 2006 +++ llvm/lib/AsmParser/llvmAsmParser.cpp.cvs Fri Apr 7 20:18:56 2006 @@ -1,5 +1,5 @@ -/* A Bison parser, made from /Users/sabre/llvm/lib/AsmParser/llvmAsmParser.y +/* A Bison parser, made from /Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y by GNU Bison version 1.28 */ #define YYBISON 1 /* Identify Bison output. */ @@ -107,10 +107,11 @@ #define VAARG 350 #define EXTRACTELEMENT 351 #define INSERTELEMENT 352 -#define VAARG_old 353 -#define VANEXT_old 354 +#define SHUFFLEVECTOR 353 +#define VAARG_old 354 +#define VANEXT_old 355 -#line 14 "/Users/sabre/llvm/lib/AsmParser/llvmAsmParser.y" +#line 14 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" #include "ParserInternals.h" #include "llvm/CallingConv.h" @@ -207,8 +208,8 @@ } // Look for intrinsic functions and CallInst that need to be upgraded - for (Module::iterator FI = CurrentModule->begin(),FE = CurrentModule->end(); - FI != FE; ) + for (Module::iterator FI = CurrentModule->begin(), + FE = CurrentModule->end(); FI != FE; ) UpgradeCallsToIntrinsic(FI++); Values.clear(); // Clear out function local definitions @@ -986,7 +987,7 @@ } -#line 890 "/Users/sabre/llvm/lib/AsmParser/llvmAsmParser.y" +#line 890 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" typedef union { llvm::Module *ModuleVal; llvm::Function *FunctionVal; @@ -1036,26 +1037,26 @@ -#define YYFINAL 473 +#define YYFINAL 479 #define YYFLAG -32768 -#define YYNTBASE 115 +#define YYNTBASE 116 -#define YYTRANSLATE(x) ((unsigned)(x) <= 354 ? yytranslate[x] : 186) +#define YYTRANSLATE(x) ((unsigned)(x) <= 355 ? yytranslate[x] : 187) static const char yytranslate[] = { 0, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, - 2, 2, 2, 2, 2, 2, 2, 2, 2, 104, - 105, 113, 2, 102, 2, 2, 2, 2, 2, 2, - 2, 2, 2, 2, 2, 2, 2, 2, 2, 109, - 101, 110, 2, 2, 2, 2, 2, 2, 2, 2, + 2, 2, 2, 2, 2, 2, 2, 2, 2, 105, + 106, 114, 2, 103, 2, 2, 2, 2, 2, 2, + 2, 2, 2, 2, 2, 2, 2, 2, 2, 110, + 102, 111, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, - 106, 103, 108, 2, 2, 2, 2, 2, 114, 2, + 107, 104, 109, 2, 2, 2, 2, 2, 115, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, - 2, 2, 2, 2, 2, 2, 2, 2, 2, 107, - 2, 2, 111, 2, 112, 2, 2, 2, 2, 2, + 2, 2, 2, 2, 2, 2, 2, 2, 2, 108, + 2, 2, 112, 2, 113, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, @@ -1078,7 +1079,7 @@ 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, 80, 81, 82, 83, 84, 85, 86, 87, 88, 89, 90, 91, 92, 93, 94, 95, 96, - 97, 98, 99, 100 + 97, 98, 99, 100, 101 }; #if YYDEBUG != 0 @@ -1105,8 +1106,8 @@ 533, 543, 553, 562, 576, 578, 580, 587, 593, 596, 603, 611, 613, 617, 619, 620, 623, 625, 631, 637, 643, 646, 651, 656, 663, 668, 673, 678, 683, 690, - 693, 701, 703, 706, 707, 709, 710, 714, 721, 725, - 732, 735, 740, 747 + 697, 700, 708, 710, 713, 714, 716, 717, 721, 728, + 732, 739, 742, 747, 754 }; static const short yyrhs[] = { 5, @@ -1115,77 +1116,77 @@ 0, 78, 0, 79, 0, 80, 0, 81, 0, 82, 0, 83, 0, 84, 0, 94, 0, 95, 0, 16, 0, 14, 0, 12, 0, 10, 0, 17, 0, 15, - 0, 13, 0, 11, 0, 121, 0, 122, 0, 18, - 0, 19, 0, 155, 101, 0, 0, 41, 0, 42, + 0, 13, 0, 11, 0, 122, 0, 123, 0, 18, + 0, 19, 0, 156, 102, 0, 0, 41, 0, 42, 0, 43, 0, 44, 0, 0, 0, 62, 0, 63, 0, 64, 0, 61, 4, 0, 0, 54, 4, 0, - 0, 102, 54, 4, 0, 34, 24, 0, 0, 130, - 0, 0, 102, 133, 132, 0, 130, 0, 54, 4, - 0, 136, 0, 8, 0, 138, 0, 8, 0, 138, + 0, 103, 54, 4, 0, 34, 24, 0, 0, 131, + 0, 0, 103, 134, 133, 0, 131, 0, 54, 4, + 0, 137, 0, 8, 0, 139, 0, 8, 0, 139, 0, 9, 0, 10, 0, 11, 0, 12, 0, 13, 0, 14, 0, 15, 0, 16, 0, 17, 0, 18, - 0, 19, 0, 20, 0, 21, 0, 45, 0, 137, - 0, 169, 0, 103, 4, 0, 135, 104, 140, 105, - 0, 106, 4, 107, 138, 108, 0, 109, 4, 107, - 138, 110, 0, 111, 139, 112, 0, 111, 112, 0, - 138, 113, 0, 138, 0, 139, 102, 138, 0, 139, - 0, 139, 102, 37, 0, 37, 0, 0, 136, 106, - 143, 108, 0, 136, 106, 108, 0, 136, 114, 24, - 0, 136, 109, 143, 110, 0, 136, 111, 143, 112, - 0, 136, 111, 112, 0, 136, 38, 0, 136, 39, - 0, 136, 169, 0, 136, 142, 0, 136, 26, 0, - 121, 116, 0, 122, 4, 0, 9, 27, 0, 9, - 28, 0, 124, 7, 0, 92, 104, 141, 36, 136, - 105, 0, 90, 104, 141, 183, 105, 0, 93, 104, - 141, 102, 141, 102, 141, 105, 0, 117, 104, 141, - 102, 141, 105, 0, 118, 104, 141, 102, 141, 105, - 0, 119, 104, 141, 102, 141, 105, 0, 120, 104, - 141, 102, 141, 105, 0, 97, 104, 141, 102, 141, - 105, 0, 143, 102, 141, 0, 141, 0, 32, 0, - 33, 0, 146, 0, 146, 164, 0, 146, 165, 0, - 146, 59, 58, 150, 0, 146, 25, 0, 147, 0, - 147, 125, 20, 134, 0, 147, 165, 0, 147, 59, - 58, 150, 0, 0, 147, 125, 126, 144, 141, 148, - 132, 0, 0, 147, 125, 47, 144, 136, 149, 132, - 0, 147, 48, 152, 0, 147, 55, 101, 153, 0, - 0, 24, 0, 53, 0, 52, 0, 50, 101, 151, - 0, 51, 101, 4, 0, 49, 101, 24, 0, 106, - 154, 108, 0, 154, 102, 24, 0, 24, 0, 0, - 22, 0, 24, 0, 155, 0, 0, 136, 156, 0, - 158, 102, 157, 0, 157, 0, 158, 0, 158, 102, - 37, 0, 37, 0, 0, 127, 134, 155, 104, 159, - 105, 131, 128, 0, 29, 0, 111, 0, 126, 160, - 161, 0, 30, 0, 112, 0, 172, 163, 0, 0, - 31, 166, 160, 0, 0, 60, 0, 3, 0, 4, + 0, 19, 0, 20, 0, 21, 0, 45, 0, 138, + 0, 170, 0, 104, 4, 0, 136, 105, 141, 106, + 0, 107, 4, 108, 139, 109, 0, 110, 4, 108, + 139, 111, 0, 112, 140, 113, 0, 112, 113, 0, + 139, 114, 0, 139, 0, 140, 103, 139, 0, 140, + 0, 140, 103, 37, 0, 37, 0, 0, 137, 107, + 144, 109, 0, 137, 107, 109, 0, 137, 115, 24, + 0, 137, 110, 144, 111, 0, 137, 112, 144, 113, + 0, 137, 112, 113, 0, 137, 38, 0, 137, 39, + 0, 137, 170, 0, 137, 143, 0, 137, 26, 0, + 122, 117, 0, 123, 4, 0, 9, 27, 0, 9, + 28, 0, 125, 7, 0, 92, 105, 142, 36, 137, + 106, 0, 90, 105, 142, 184, 106, 0, 93, 105, + 142, 103, 142, 103, 142, 106, 0, 118, 105, 142, + 103, 142, 106, 0, 119, 105, 142, 103, 142, 106, + 0, 120, 105, 142, 103, 142, 106, 0, 121, 105, + 142, 103, 142, 106, 0, 97, 105, 142, 103, 142, + 106, 0, 144, 103, 142, 0, 142, 0, 32, 0, + 33, 0, 147, 0, 147, 165, 0, 147, 166, 0, + 147, 59, 58, 151, 0, 147, 25, 0, 148, 0, + 148, 126, 20, 135, 0, 148, 166, 0, 148, 59, + 58, 151, 0, 0, 148, 126, 127, 145, 142, 149, + 133, 0, 0, 148, 126, 47, 145, 137, 150, 133, + 0, 148, 48, 153, 0, 148, 55, 102, 154, 0, + 0, 24, 0, 53, 0, 52, 0, 50, 102, 152, + 0, 51, 102, 4, 0, 49, 102, 24, 0, 107, + 155, 109, 0, 155, 103, 24, 0, 24, 0, 0, + 22, 0, 24, 0, 156, 0, 0, 137, 157, 0, + 159, 103, 158, 0, 158, 0, 159, 0, 159, 103, + 37, 0, 37, 0, 0, 128, 135, 156, 105, 160, + 106, 132, 129, 0, 29, 0, 112, 0, 127, 161, + 162, 0, 30, 0, 113, 0, 173, 164, 0, 0, + 31, 167, 161, 0, 0, 60, 0, 3, 0, 4, 0, 7, 0, 27, 0, 28, 0, 38, 0, 39, - 0, 26, 0, 109, 143, 110, 0, 142, 0, 58, - 167, 24, 102, 24, 0, 115, 0, 155, 0, 169, - 0, 168, 0, 136, 170, 0, 172, 173, 0, 162, - 173, 0, 174, 125, 175, 0, 174, 177, 0, 0, - 23, 0, 65, 171, 0, 65, 8, 0, 66, 21, - 170, 0, 66, 9, 170, 102, 21, 170, 102, 21, - 170, 0, 67, 123, 170, 102, 21, 170, 106, 176, - 108, 0, 67, 123, 170, 102, 21, 170, 106, 108, - 0, 68, 127, 134, 170, 104, 180, 105, 36, 21, - 170, 69, 21, 170, 0, 69, 0, 70, 0, 176, - 123, 168, 102, 21, 170, 0, 123, 168, 102, 21, - 170, 0, 125, 182, 0, 136, 106, 170, 102, 170, - 108, 0, 178, 102, 106, 170, 102, 170, 108, 0, - 171, 0, 179, 102, 171, 0, 179, 0, 0, 57, - 56, 0, 56, 0, 117, 136, 170, 102, 170, 0, - 118, 136, 170, 102, 170, 0, 119, 136, 170, 102, - 170, 0, 46, 171, 0, 120, 171, 102, 171, 0, - 92, 171, 36, 136, 0, 93, 171, 102, 171, 102, - 171, 0, 96, 171, 102, 136, 0, 99, 171, 102, - 136, 0, 100, 171, 102, 136, 0, 97, 171, 102, - 171, 0, 98, 171, 102, 171, 102, 171, 0, 91, - 178, 0, 181, 127, 134, 170, 104, 180, 105, 0, - 185, 0, 102, 179, 0, 0, 35, 0, 0, 85, - 136, 129, 0, 85, 136, 102, 15, 170, 129, 0, - 86, 136, 129, 0, 86, 136, 102, 15, 170, 129, - 0, 87, 171, 0, 184, 88, 136, 170, 0, 184, - 89, 171, 102, 136, 170, 0, 90, 136, 170, 183, - 0 + 0, 26, 0, 110, 144, 111, 0, 143, 0, 58, + 168, 24, 103, 24, 0, 116, 0, 156, 0, 170, + 0, 169, 0, 137, 171, 0, 173, 174, 0, 163, + 174, 0, 175, 126, 176, 0, 175, 178, 0, 0, + 23, 0, 65, 172, 0, 65, 8, 0, 66, 21, + 171, 0, 66, 9, 171, 103, 21, 171, 103, 21, + 171, 0, 67, 124, 171, 103, 21, 171, 107, 177, + 109, 0, 67, 124, 171, 103, 21, 171, 107, 109, + 0, 68, 128, 135, 171, 105, 181, 106, 36, 21, + 171, 69, 21, 171, 0, 69, 0, 70, 0, 177, + 124, 169, 103, 21, 171, 0, 124, 169, 103, 21, + 171, 0, 126, 183, 0, 137, 107, 171, 103, 171, + 109, 0, 179, 103, 107, 171, 103, 171, 109, 0, + 172, 0, 180, 103, 172, 0, 180, 0, 0, 57, + 56, 0, 56, 0, 118, 137, 171, 103, 171, 0, + 119, 137, 171, 103, 171, 0, 120, 137, 171, 103, + 171, 0, 46, 172, 0, 121, 172, 103, 172, 0, + 92, 172, 36, 137, 0, 93, 172, 103, 172, 103, + 172, 0, 96, 172, 103, 137, 0, 100, 172, 103, + 137, 0, 101, 172, 103, 137, 0, 97, 172, 103, + 172, 0, 98, 172, 103, 172, 103, 172, 0, 99, + 172, 103, 172, 103, 172, 0, 91, 179, 0, 182, + 128, 135, 171, 105, 181, 106, 0, 186, 0, 103, + 180, 0, 0, 35, 0, 0, 85, 137, 130, 0, + 85, 137, 103, 15, 171, 130, 0, 86, 137, 130, + 0, 86, 137, 103, 15, 171, 130, 0, 87, 172, + 0, 185, 88, 137, 171, 0, 185, 89, 172, 103, + 137, 171, 0, 90, 137, 171, 184, 0 }; #endif @@ -1214,8 +1215,8 @@ 1990, 1993, 2007, 2011, 2064, 2067, 2073, 2081, 2091, 2098, 2103, 2110, 2114, 2120, 2120, 2122, 2125, 2131, 2143, 2154, 2164, 2176, 2183, 2190, 2197, 2202, 2221, 2243, 2251, 2263, - 2277, 2334, 2340, 2342, 2346, 2349, 2355, 2359, 2363, 2367, - 2371, 2378, 2388, 2401 + 2268, 2282, 2339, 2345, 2347, 2351, 2354, 2360, 2364, 2368, + 2372, 2376, 2383, 2393, 2406 }; #endif @@ -1233,47 +1234,48 @@ "CCC_TOK","FASTCC_TOK","COLDCC_TOK","RET","BR","SWITCH","INVOKE","UNWIND","UNREACHABLE", "ADD","SUB","MUL","DIV","REM","AND","OR","XOR","SETLE","SETGE","SETLT","SETGT", "SETEQ","SETNE","MALLOC","ALLOCA","FREE","LOAD","STORE","GETELEMENTPTR","PHI_TOK", -"CAST","SELECT","SHL","SHR","VAARG","EXTRACTELEMENT","INSERTELEMENT","VAARG_old", -"VANEXT_old","'='","','","'\\\\'","'('","')'","'['","'x'","']'","'<'","'>'", -"'{'","'}'","'*'","'c'","INTVAL","EINT64VAL","ArithmeticOps","LogicalOps","SetCondOps", -"ShiftOps","SIntType","UIntType","IntType","FPType","OptAssign","OptLinkage", -"OptCallingConv","OptAlign","OptCAlign","SectionString","OptSection","GlobalVarAttributes", -"GlobalVarAttribute","TypesV","UpRTypesV","Types","PrimType","UpRTypes","TypeListI", -"ArgTypeListI","ConstVal","ConstExpr","ConstVector","GlobalType","Module","FunctionList", -"ConstPool","@1","@2","AsmBlock","BigOrLittle","TargetDefinition","LibrariesDefinition", -"LibList","Name","OptName","ArgVal","ArgListH","ArgList","FunctionHeaderH","BEGIN", -"FunctionHeader","END","Function","FunctionProto","@3","OptSideEffect","ConstValueRef", -"SymbolicValueRef","ValueRef","ResolvedVal","BasicBlockList","BasicBlock","InstructionList", -"BBTerminatorInst","JumpTable","Inst","PHIList","ValueRefList","ValueRefListE", -"OptTailCall","InstVal","IndexList","OptVolatile","MemoryInst", NULL +"CAST","SELECT","SHL","SHR","VAARG","EXTRACTELEMENT","INSERTELEMENT","SHUFFLEVECTOR", +"VAARG_old","VANEXT_old","'='","','","'\\\\'","'('","')'","'['","'x'","']'", +"'<'","'>'","'{'","'}'","'*'","'c'","INTVAL","EINT64VAL","ArithmeticOps","LogicalOps", +"SetCondOps","ShiftOps","SIntType","UIntType","IntType","FPType","OptAssign", +"OptLinkage","OptCallingConv","OptAlign","OptCAlign","SectionString","OptSection", +"GlobalVarAttributes","GlobalVarAttribute","TypesV","UpRTypesV","Types","PrimType", +"UpRTypes","TypeListI","ArgTypeListI","ConstVal","ConstExpr","ConstVector","GlobalType", +"Module","FunctionList","ConstPool","@1","@2","AsmBlock","BigOrLittle","TargetDefinition", +"LibrariesDefinition","LibList","Name","OptName","ArgVal","ArgListH","ArgList", +"FunctionHeaderH","BEGIN","FunctionHeader","END","Function","FunctionProto", +"@3","OptSideEffect","ConstValueRef","SymbolicValueRef","ValueRef","ResolvedVal", +"BasicBlockList","BasicBlock","InstructionList","BBTerminatorInst","JumpTable", +"Inst","PHIList","ValueRefList","ValueRefListE","OptTailCall","InstVal","IndexList", +"OptVolatile","MemoryInst", NULL }; #endif static const short yyr1[] = { 0, - 115, 115, 116, 116, 117, 117, 117, 117, 117, 118, - 118, 118, 119, 119, 119, 119, 119, 119, 120, 120, - 121, 121, 121, 121, 122, 122, 122, 122, 123, 123, - 124, 124, 125, 125, 126, 126, 126, 126, 126, 127, - 127, 127, 127, 127, 128, 128, 129, 129, 130, 131, - 131, 132, 132, 133, 133, 134, 134, 135, 135, 136, - 137, 137, 137, 137, 137, 137, 137, 137, 137, 137, - 137, 137, 137, 138, 138, 138, 138, 138, 138, 138, - 138, 138, 138, 139, 139, 140, 140, 140, 140, 141, - 141, 141, 141, 141, 141, 141, 141, 141, 141, 141, - 141, 141, 141, 141, 141, 142, 142, 142, 142, 142, - 142, 142, 142, 143, 143, 144, 144, 145, 146, 146, - 146, 146, 146, 147, 147, 147, 148, 147, 149, 147, - 147, 147, 147, 150, 151, 151, 152, 152, 152, 153, - 154, 154, 154, 155, 155, 156, 156, 157, 158, 158, - 159, 159, 159, 159, 160, 161, 161, 162, 163, 163, - 164, 166, 165, 167, 167, 168, 168, 168, 168, 168, - 168, 168, 168, 168, 168, 168, 169, 169, 170, 170, - 171, 172, 172, 173, 174, 174, 174, 175, 175, 175, - 175, 175, 175, 175, 175, 175, 176, 176, 177, 178, - 178, 179, 179, 180, 180, 181, 181, 182, 182, 182, - 182, 182, 182, 182, 182, 182, 182, 182, 182, 182, - 182, 182, 183, 183, 184, 184, 185, 185, 185, 185, - 185, 185, 185, 185 + 116, 116, 117, 117, 118, 118, 118, 118, 118, 119, + 119, 119, 120, 120, 120, 120, 120, 120, 121, 121, + 122, 122, 122, 122, 123, 123, 123, 123, 124, 124, + 125, 125, 126, 126, 127, 127, 127, 127, 127, 128, + 128, 128, 128, 128, 129, 129, 130, 130, 131, 132, + 132, 133, 133, 134, 134, 135, 135, 136, 136, 137, + 138, 138, 138, 138, 138, 138, 138, 138, 138, 138, + 138, 138, 138, 139, 139, 139, 139, 139, 139, 139, + 139, 139, 139, 140, 140, 141, 141, 141, 141, 142, + 142, 142, 142, 142, 142, 142, 142, 142, 142, 142, + 142, 142, 142, 142, 142, 143, 143, 143, 143, 143, + 143, 143, 143, 144, 144, 145, 145, 146, 147, 147, + 147, 147, 147, 148, 148, 148, 149, 148, 150, 148, + 148, 148, 148, 151, 152, 152, 153, 153, 153, 154, + 155, 155, 155, 156, 156, 157, 157, 158, 159, 159, + 160, 160, 160, 160, 161, 162, 162, 163, 164, 164, + 165, 167, 166, 168, 168, 169, 169, 169, 169, 169, + 169, 169, 169, 169, 169, 169, 170, 170, 171, 171, + 172, 173, 173, 174, 175, 175, 175, 176, 176, 176, + 176, 176, 176, 176, 176, 176, 177, 177, 178, 179, + 179, 180, 180, 181, 181, 182, 182, 183, 183, 183, + 183, 183, 183, 183, 183, 183, 183, 183, 183, 183, + 183, 183, 183, 184, 184, 185, 185, 186, 186, 186, + 186, 186, 186, 186, 186 }; static const short yyr2[] = { 0, @@ -1298,9 +1300,9 @@ 2, 2, 2, 3, 2, 0, 1, 2, 2, 3, 9, 9, 8, 13, 1, 1, 6, 5, 2, 6, 7, 1, 3, 1, 0, 2, 1, 5, 5, 5, - 2, 4, 4, 6, 4, 4, 4, 4, 6, 2, - 7, 1, 2, 0, 1, 0, 3, 6, 3, 6, - 2, 4, 6, 4 + 2, 4, 4, 6, 4, 4, 4, 4, 6, 6, + 2, 7, 1, 2, 0, 1, 0, 3, 6, 3, + 6, 2, 4, 6, 4 }; static const short yydefact[] = { 133, @@ -1312,375 +1314,373 @@ 44, 1, 2, 57, 61, 62, 63, 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 0, 0, 0, 0, 177, 0, 0, 56, 75, 60, 178, 76, - 156, 157, 158, 226, 185, 0, 0, 0, 143, 132, + 156, 157, 158, 227, 185, 0, 0, 0, 143, 132, 126, 124, 116, 117, 0, 0, 77, 0, 0, 59, - 82, 84, 0, 0, 89, 83, 225, 0, 207, 0, + 82, 84, 0, 0, 89, 83, 226, 0, 207, 0, 0, 0, 0, 40, 195, 196, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 0, 0, 0, 0, 0, 0, 0, 19, 20, 0, - 0, 0, 0, 0, 0, 0, 0, 0, 184, 40, - 199, 0, 222, 139, 136, 135, 137, 138, 142, 0, - 129, 61, 62, 63, 64, 65, 66, 67, 68, 69, - 70, 71, 0, 0, 0, 0, 127, 0, 0, 0, - 81, 154, 88, 86, 0, 0, 211, 206, 189, 188, - 0, 0, 24, 28, 23, 27, 22, 26, 21, 25, - 29, 30, 0, 0, 47, 47, 231, 0, 0, 220, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 184, + 40, 199, 0, 223, 139, 136, 135, 137, 138, 142, + 0, 129, 61, 62, 63, 64, 65, 66, 67, 68, + 69, 70, 71, 0, 0, 0, 0, 127, 0, 0, + 0, 81, 154, 88, 86, 0, 0, 211, 206, 189, + 188, 0, 0, 24, 28, 23, 27, 22, 26, 21, + 25, 29, 30, 0, 0, 47, 47, 232, 0, 0, + 221, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 140, 52, 103, + 104, 3, 4, 101, 102, 105, 100, 96, 97, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 140, 52, 103, 104, 3, - 4, 101, 102, 105, 100, 96, 97, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, 0, 99, - 98, 52, 58, 58, 85, 153, 147, 150, 151, 0, - 0, 78, 166, 167, 168, 173, 169, 170, 171, 172, - 164, 0, 175, 180, 179, 181, 0, 190, 0, 0, - 0, 227, 0, 229, 224, 0, 0, 0, 0, 0, + 0, 99, 98, 52, 58, 58, 85, 153, 147, 150, + 151, 0, 0, 78, 166, 167, 168, 173, 169, 170, + 171, 172, 164, 0, 175, 180, 179, 181, 0, 190, + 0, 0, 0, 228, 0, 230, 225, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 141, 0, 130, 0, 0, 0, 0, 91, 115, - 0, 0, 95, 0, 92, 0, 0, 0, 0, 128, - 79, 80, 146, 148, 0, 50, 87, 165, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 234, 0, 0, - 213, 0, 215, 218, 0, 216, 217, 0, 0, 0, - 212, 0, 232, 0, 0, 0, 54, 52, 224, 0, - 0, 0, 0, 90, 93, 94, 0, 0, 0, 0, - 152, 149, 51, 45, 0, 174, 0, 0, 205, 47, - 48, 47, 202, 223, 0, 0, 0, 0, 208, 209, - 210, 205, 0, 49, 55, 53, 0, 0, 0, 0, - 114, 0, 0, 0, 0, 0, 155, 0, 0, 0, - 204, 0, 0, 228, 230, 0, 0, 0, 214, 219, - 0, 233, 107, 0, 0, 0, 0, 0, 0, 0, - 46, 176, 0, 0, 0, 203, 200, 0, 221, 106, - 0, 113, 109, 110, 111, 112, 0, 193, 0, 0, - 0, 201, 0, 191, 0, 192, 0, 0, 108, 0, - 0, 0, 0, 0, 0, 198, 0, 0, 197, 194, - 0, 0, 0 + 0, 0, 0, 0, 141, 0, 130, 0, 0, 0, + 0, 91, 115, 0, 0, 95, 0, 92, 0, 0, + 0, 0, 128, 79, 80, 146, 148, 0, 50, 87, + 165, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 235, 0, 0, 213, 0, 215, 218, 0, 0, 216, + 217, 0, 0, 0, 212, 0, 233, 0, 0, 0, + 54, 52, 225, 0, 0, 0, 0, 90, 93, 94, + 0, 0, 0, 0, 152, 149, 51, 45, 0, 174, + 0, 0, 205, 47, 48, 47, 202, 224, 0, 0, + 0, 0, 0, 208, 209, 210, 205, 0, 49, 55, + 53, 0, 0, 0, 0, 114, 0, 0, 0, 0, + 0, 155, 0, 0, 0, 204, 0, 0, 229, 231, + 0, 0, 0, 214, 219, 220, 0, 234, 107, 0, + 0, 0, 0, 0, 0, 0, 46, 176, 0, 0, + 0, 203, 200, 0, 222, 106, 0, 113, 109, 110, + 111, 112, 0, 193, 0, 0, 0, 201, 0, 191, + 0, 192, 0, 0, 108, 0, 0, 0, 0, 0, + 0, 198, 0, 0, 197, 194, 0, 0, 0 }; static const short yydefgoto[] = { 73, - 232, 246, 247, 248, 249, 173, 174, 203, 175, 20, - 10, 29, 407, 282, 357, 374, 304, 358, 74, 75, - 186, 77, 78, 103, 185, 310, 273, 311, 95, 471, - 1, 2, 252, 227, 50, 157, 41, 90, 160, 79, - 324, 258, 259, 260, 30, 83, 11, 36, 12, 13, - 23, 329, 274, 80, 276, 383, 14, 32, 33, 149, - 450, 85, 210, 411, 412, 150, 151, 338, 152, 153 + 234, 248, 249, 250, 251, 174, 175, 204, 176, 20, + 10, 29, 412, 284, 361, 378, 307, 362, 74, 75, + 187, 77, 78, 103, 186, 313, 275, 314, 95, 477, + 1, 2, 254, 229, 50, 158, 41, 90, 161, 79, + 327, 260, 261, 262, 30, 83, 11, 36, 12, 13, + 23, 332, 276, 80, 278, 387, 14, 32, 33, 150, + 456, 85, 211, 416, 417, 151, 152, 341, 153, 154 }; static const short yypact[] = {-32768, - 30, 99,-32768,-32768,-32768,-32768,-32768,-32768, -47, 46, - 33,-32768,-32768, -13,-32768,-32768, 75, -32, 26, 21, - -3,-32768, 46, 63, 100,-32768,-32768,-32768, 974, -21, --32768,-32768, 105,-32768,-32768,-32768,-32768, 10, 27, 32, --32768, 38, 63, 974, 103, 103,-32768,-32768,-32768,-32768, --32768,-32768,-32768, 18,-32768,-32768,-32768,-32768,-32768,-32768, --32768,-32768,-32768,-32768,-32768,-32768,-32768,-32768, 135, 148, - 155, 490,-32768, 105, 67,-32768,-32768, -64,-32768,-32768, --32768,-32768,-32768, 1136,-32768, 149, 85, 172, 154,-32768, --32768,-32768,-32768,-32768, 1012, 1050,-32768, 73, 76,-32768, --32768, -64, -17, 80, 784,-32768,-32768, 1012,-32768, 129, - 1088, 23, 221, 46,-32768,-32768,-32768,-32768,-32768,-32768, + 107, 362,-32768,-32768,-32768,-32768,-32768,-32768, -37, 78, + 23,-32768,-32768, -12,-32768,-32768, 75, 2, 32, -6, + 27,-32768, 78, 85, 140,-32768,-32768,-32768, 957, -20, +-32768,-32768, 121,-32768,-32768,-32768,-32768, 45, 53, 70, +-32768, 68, 85, 957, 31, 31,-32768,-32768,-32768,-32768, +-32768,-32768,-32768, 76,-32768,-32768,-32768,-32768,-32768,-32768, +-32768,-32768,-32768,-32768,-32768,-32768,-32768,-32768, 178, 179, + 182, 67,-32768, 121, 88,-32768,-32768, 16,-32768,-32768, +-32768,-32768,-32768, 1120,-32768, 170, 100, 184, 173,-32768, +-32768,-32768,-32768,-32768, 995, 1033,-32768, 91, 92,-32768, +-32768, 16, -42, 96, 767,-32768,-32768, 995,-32768, 147, + 1071, 22, 223, 78,-32768,-32768,-32768,-32768,-32768,-32768, -32768,-32768,-32768,-32768,-32768,-32768,-32768,-32768,-32768,-32768, - 1012, 1012, 1012, 1012, 1012, 1012, 1012,-32768,-32768, 1012, - 1012, 1012, 1012, 1012, 1012, 1012, 1012, 1012,-32768, 46, --32768, 60,-32768,-32768,-32768,-32768,-32768,-32768,-32768, -14, --32768, 123, 153, 182, 159, 186, 162, 187, 164, 188, - 189, 190, 166, 194, 193, 372,-32768, 1012, 1012, 1012, --32768, 822,-32768, 101, 102, 622,-32768,-32768, 18,-32768, - 622, 622,-32768,-32768,-32768,-32768,-32768,-32768,-32768,-32768, --32768,-32768, 622, 974, 104, 107,-32768, 622, 98, 108, - 169, 109, 110, 118, 119, 120, 121, 622, 622, 622, - 122, 974, 1012, 1012, 201,-32768, 124,-32768,-32768,-32768, --32768,-32768,-32768,-32768,-32768,-32768,-32768, 136, 137, 138, - 141, 860, 1050, 531, 215, 142, 143, 144, 146,-32768, --32768, 124, -75, -53, -64,-32768, 105,-32768, 150, 139, - 898,-32768,-32768,-32768,-32768,-32768,-32768,-32768,-32768,-32768, - 191, 1050,-32768,-32768,-32768,-32768, 151,-32768, 152, 622, - 5,-32768, 16,-32768, 158, 622, 156, 1012, 1012, 1012, - 1012, 1012, 1012, 1012, 161, 165, 168, 1012, 622, 622, - 170,-32768, -18,-32768, 1050, 1050, 1050, 1050,-32768,-32768, - -11, -65,-32768, -16,-32768, 1050, 1050, 1050, 1050,-32768, --32768,-32768,-32768,-32768, 936, 222,-32768,-32768, 233, -10, - 245, 250, 171, 622, 269, 622, 1012,-32768, 178, 622, --32768, 179,-32768,-32768, 180,-32768,-32768, 622, 622, 622, --32768, 181,-32768, 1012, 259, 280,-32768, 124, 158, 255, - 184, 192, 1050,-32768,-32768,-32768, 197, 198, 199, 200, --32768,-32768,-32768, 238, 202,-32768, 622, 622, 1012, 204, --32768, 204,-32768, 205, 622, 206, 1012, 1012,-32768,-32768, --32768, 1012, 622,-32768,-32768,-32768, 207, 1012, 1050, 1050, --32768, 1050, 1050, 1050, 1050, 289,-32768, 271, 218, 223, - 205, 216, 270,-32768,-32768, 1012, 219, 622,-32768,-32768, - 225,-32768,-32768, 228, 226, 230, 231, 232, 235, 236, --32768,-32768, 321, 12, 308,-32768,-32768, 237,-32768,-32768, - 1050,-32768,-32768,-32768,-32768,-32768, 622,-32768, 682, 66, - 328,-32768, 246,-32768, 248,-32768, 682, 622,-32768, 332, - 253, 287, 622, 336, 340,-32768, 622, 622,-32768,-32768, - 363, 364,-32768 + 995, 995, 995, 995, 995, 995, 995,-32768,-32768, 995, + 995, 995, 995, 995, 995, 995, 995, 995, 995,-32768, + 78,-32768, 47,-32768,-32768,-32768,-32768,-32768,-32768,-32768, + 24,-32768, 41, 154, 203, 156, 204, 160, 205, 164, + 206, 207, 215, 166, 209, 216, 425,-32768, 995, 995, + 995,-32768, 805,-32768, 108, 118, 604,-32768,-32768, 76, +-32768, 604, 604,-32768,-32768,-32768,-32768,-32768,-32768,-32768, +-32768,-32768,-32768, 604, 957, 122, 123,-32768, 604, 120, + 125, 208, 138, 139, 143, 144, 145, 146, 149, 604, + 604, 604, 150, 957, 995, 995, 219,-32768, 151,-32768, +-32768,-32768,-32768,-32768,-32768,-32768,-32768,-32768,-32768, 153, + 155, 157, 159, 843, 1033, 548, 226, 161, 165, 168, + 169,-32768,-32768, 151, -75, -3, 16,-32768, 121,-32768, + 152, 163, 881,-32768,-32768,-32768,-32768,-32768,-32768,-32768, +-32768,-32768, 196, 1033,-32768,-32768,-32768,-32768, 162,-32768, + 172, 604, -5,-32768, 5,-32768, 175, 604, 176, 995, + 995, 995, 995, 995, 995, 995, 995, 181, 183, 185, + 995, 604, 604, 186,-32768, -22,-32768, 1033, 1033, 1033, + 1033,-32768,-32768, 25, -46,-32768, 7,-32768, 1033, 1033, + 1033, 1033,-32768,-32768,-32768,-32768,-32768, 919, 242,-32768, +-32768, 261, -41, 266, 273, 190, 604, 292, 604, 995, +-32768, 194, 604,-32768, 195,-32768,-32768, 197, 198,-32768, +-32768, 604, 604, 604,-32768, 200,-32768, 995, 283, 305, +-32768, 151, 175, 274, 210, 213, 1033,-32768,-32768,-32768, + 224, 228, 230, 231,-32768,-32768,-32768, 257, 232,-32768, + 604, 604, 995, 234,-32768, 234,-32768, 236, 604, 237, + 995, 995, 995,-32768,-32768,-32768, 995, 604,-32768,-32768, +-32768, 220, 995, 1033, 1033,-32768, 1033, 1033, 1033, 1033, + 338,-32768, 319, 244, 238, 236, 243, 294,-32768,-32768, + 995, 246, 604,-32768,-32768,-32768, 250,-32768,-32768, 253, + 258, 254, 256, 259, 260, 262,-32768,-32768, 342, 13, + 328,-32768,-32768, 263,-32768,-32768, 1033,-32768,-32768,-32768, +-32768,-32768, 604,-32768, 664, 83, 348,-32768, 264,-32768, + 268,-32768, 664, 604,-32768, 352, 280, 308, 604, 364, + 366,-32768, 604, 604,-32768,-32768, 388, 389,-32768 }; static const short yypgoto[] = {-32768, --32768, 281, 282, 283, 284, -112, -111, -415,-32768, 339, - 359, -102,-32768, -201, 54,-32768, -243,-32768, -40,-32768, - -29,-32768, -66, 276,-32768, -89, 208, -230, 337,-32768, --32768,-32768,-32768,-32768, 342,-32768,-32768,-32768,-32768, 1, --32768, 57,-32768,-32768, 365,-32768,-32768,-32768,-32768, 384, --32768,-32768, -356, -31, 140, -90,-32768, 375,-32768,-32768, --32768,-32768,-32768, 53, -1,-32768,-32768, 34,-32768,-32768 +-32768, 306, 307, 312, 313, -112, -110, -398,-32768, 365, + 379, -101,-32768, -199, 71,-32768, -249,-32768, -40,-32768, + -29,-32768, -65, 296,-32768, -90, 225, -229, 361,-32768, +-32768,-32768,-32768,-32768, 368,-32768,-32768,-32768,-32768, 0, +-32768, 80,-32768,-32768, 390,-32768,-32768,-32768,-32768, 410, +-32768,-32768, -332, -31, 132, -89,-32768, 401,-32768,-32768, +-32768,-32768,-32768, 79, 19,-32768,-32768, 60,-32768,-32768 }; -#define YYLAST 1236 +#define YYLAST 1221 static const short yytable[] = { 76, - 201, 202, 21, 92, 284, 102, 177, 81, 320, 31, - 24, 204, 312, 314, 76, 355, 34, 187, 449, 334, - 190, 193, 194, 195, 196, 197, 198, 199, 200, -118, - 336, 191, 321, 21, 457, 356, 363, 106, 102, -58, - 44, 330, 207, 192, 365, 211, 212, 222, 106, 213, - 214, 215, 216, 217, 3, 31, 322, 221, 335, 106, - 4, 5, 6, 7, 8, 161, 176, 45, 42, 335, - 5, 6, 7, 8, 104, 193, 194, 195, 196, 197, - 198, 199, 200, 43, 180, 363, 49, 225, 9, 82, - 363, 363, 455, 226, 181, 366, 364, 47, 35, 376, - 461, 205, 206, 51, 208, 209, 25, 26, 27, 28, - 86, 253, 254, 255, 396, 218, 219, 220, -34, 448, - 15, -59, 16, 38, 39, 40, 15, 87, 16, 4, - -34, -34, 88, 301, 93, 94, 155, 156, 97, -34, - -34, -34, -34, 89, 251, -34, 17, 223, 224, 228, - 229, 98, 257, 18, 275, -24, -24, 19, 99, 275, - 275, -23, -23, 280, -22, -22, -21, -21, 230, 231, - 105, 275, 154, 456, 76, 158, 275, 159, 414, 178, - 415, 299, 179, 182, 188, -28, 275, 275, 275, -27, - -26, -25, 76, 300, 255, -31, -32, 233, 342, 234, - 344, 345, 261, 286, 288, 281, 262, 351, 283, 287, - 289, 290, 176, 176, 176, 359, 360, 361, 362, 291, - 292, 293, 294, 298, 302, 303, 367, 368, 369, 370, - 193, 194, 195, 196, 197, 198, 199, 200, 315, 305, - 306, 307, 176, 326, 308, 316, 317, 318, 275, 319, - 328, 325, 331, 332, 275, 355, 375, 323, 341, 337, - 343, 340, 348, 346, 347, 377, 349, 275, 275, 350, - 378, 354, 381, 401, 379, 176, 176, 176, 176, 385, - 387, 388, 394, 395, 392, 399, 176, 176, 176, 176, - 398, 406, 431, 400, 432, 257, 419, 420, 402, 403, - 404, 405, 275, 408, 275, 413, 416, 418, 275, 425, - 426, 423, 427, 428, 429, 430, 275, 275, 275, 433, - 435, 201, 202, 335, 393, 436, 437, 441, 434, 439, - 277, 278, 440, 176, 442, 443, 444, 201, 202, 445, - 446, 447, 279, 451, 452, 275, 275, 285, 458, 460, - 459, 453, 463, 275, 464, 465, 467, 295, 296, 297, - 468, 275, 472, 473, 145, 146, 147, 148, 424, 176, - 176, 84, 176, 176, 176, 176, 52, 53, 46, 373, - 184, 372, 96, 250, 91, 22, 275, 48, 37, 384, - 421, 0, 397, 15, 0, 16, 0, 235, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, 0, 236, - 237, 176, 0, 0, 0, 275, 0, 0, 0, 333, - 0, 0, 0, 0, 0, 339, 275, 0, 0, 0, - 0, 275, 0, 0, 0, 275, 275, 0, 352, 353, - 0, 0, 117, 118, 119, 120, 121, 122, 123, 124, - 125, 126, 127, 128, 129, 130, 0, 0, 0, 0, - 0, 238, 0, 239, 240, 138, 139, 0, 241, 0, - 0, 0, 0, 380, 0, 382, 0, 242, 0, 386, - 243, 0, 244, 0, 0, 245, 0, 389, 390, 391, - 0, 0, 0, 0, 52, 53, 0, 100, 55, 56, - 57, 58, 59, 60, 61, 62, 63, 64, 65, 66, - 67, 15, 0, 16, 0, 0, 409, 410, 0, 0, - 0, 0, 0, 0, 417, 0, 0, 0, 0, 0, - 0, 0, 422, 0, 68, 52, 53, 0, 100, 162, - 163, 164, 165, 166, 167, 168, 169, 170, 171, 172, - 66, 67, 15, 0, 16, 0, 0, 438, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 68, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 454, 0, 0, 0, - 0, 0, 69, 0, 0, 70, 0, 462, 71, 0, - 72, 101, 466, 0, 0, 0, 469, 470, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 263, 264, 52, 53, 265, 0, - 0, 0, 0, 69, 0, 0, 70, 0, 0, 71, - 0, 72, 313, 15, 0, 16, 0, 266, 267, 268, - 0, 0, 0, 0, 0, 0, 0, 0, 0, 269, - 270, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, 0, 271, - 0, 0, 0, 0, 263, 264, 0, 0, 265, 0, - 0, 0, 117, 118, 119, 120, 121, 122, 123, 124, - 125, 126, 127, 128, 129, 130, 0, 266, 267, 268, - 0, 238, 0, 239, 240, 138, 139, 0, 241, 269, - 270, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 272, 0, 0, 0, 0, 0, 0, 0, 0, 271, + 202, 21, 203, 92, 323, 178, 102, 286, 81, 337, + 31, 359, 205, 44, 76, 315, 317, 34, 188, 339, + 24, 191, 194, 195, 196, 197, 198, 199, 200, 201, + 192, 360, 21, 324, 5, 6, 7, 8, 106, 102, + 45, 455, 193, 208, 333, 31, 212, 213, 338, 224, + 214, 215, 216, 217, 218, 219, 367, 463, 338, 223, + 181, 367, 93, 94, 369, 162, 177, 230, 231, 380, + 182, 52, 53, 104, 100, 55, 56, 57, 58, 59, + 60, 61, 62, 63, 64, 65, 66, 67, 15, 43, + 16, 82, 194, 195, 196, 197, 198, 199, 200, 201, + 35, 206, 207, 42, 209, 210, -118, 325, 49, 367, + 106, 68, 401, 255, 256, 257, 220, 221, 222, 370, + -58, 454, 461, 38, 39, 40, 227, 367, 47, 106, + 467, 3, 228, 368, 225, 226, 304, 4, 25, 26, + 27, 28, 15, 51, 16, 253, 86, 5, 6, 7, + 8, 156, 157, 259, 87, 277, -24, -24, -23, -23, + 277, 277, -22, -22, 282, 9, -21, -21, 232, 233, + 69, 88, 277, 70, 89, 76, 71, 277, 72, 101, + -59, 97, 98, 302, 419, 99, 420, 159, 277, 277, + 277, 462, 105, 155, 76, 303, 160, 257, 179, 180, + 183, 345, 189, 347, 348, 349, -28, -27, -26, -25, + 263, 355, 235, -31, 177, 177, 177, 363, 364, 365, + 366, -32, 236, 264, 283, 285, 288, 289, 371, 372, + 373, 374, 194, 195, 196, 197, 198, 199, 200, 201, + 291, 292, 305, 290, 177, 293, 294, 295, 296, 318, + 277, 297, 301, 306, 328, 331, 277, 308, 326, 309, + 344, 310, 346, 311, 334, 319, 350, 351, 329, 320, + 277, 277, 321, 322, 335, 359, 406, 340, 177, 177, + 177, 177, 343, 352, 379, 353, 381, 354, 358, 177, + 177, 177, 177, 382, 383, 385, 389, 391, 259, 392, + 393, 424, 425, 426, 397, 277, 399, 277, 400, 403, + 411, 277, 404, 431, 432, 405, 433, 434, 435, 436, + 277, 277, 277, 279, 280, 429, 407, 202, 398, 203, + 408, 442, 409, 410, 413, 281, 418, 177, 421, 423, + 287, 437, 438, 202, 440, 203, 439, 338, 441, 277, + 277, 298, 299, 300, 443, 445, 459, 277, 446, 448, + 447, 449, 453, 457, 450, 451, 277, 452, 464, 465, + 466, 458, 469, 430, 177, 177, 471, 177, 177, 177, + 177, -34, 470, 15, 473, 16, 474, 478, 479, 146, + 147, 277, 4, -34, -34, 148, 149, 84, 46, 377, + 185, 252, -34, -34, -34, -34, 96, 376, -34, 17, + 91, 22, 48, 336, 37, 427, 18, 177, 388, 342, + 19, 277, 402, 0, 0, 0, 0, 0, 0, 52, + 53, 0, 277, 356, 357, 0, 0, 277, 0, 0, + 0, 277, 277, 0, 0, 0, 15, 0, 16, 0, + 237, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 238, 239, 0, 0, 0, 0, 384, 0, + 386, 0, 0, 0, 390, 0, 0, 0, 0, 0, + 0, 0, 0, 394, 395, 396, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 117, 118, 119, 120, 121, + 122, 123, 124, 125, 126, 127, 128, 129, 130, 0, + 0, 0, 414, 415, 240, 0, 241, 242, 138, 139, + 422, 243, 0, 0, 0, 0, 0, 0, 0, 428, + 0, 244, 0, 0, 245, 0, 246, 0, 0, 247, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 117, 118, 119, 120, 121, 122, 123, 124, - 125, 126, 127, 128, 129, 130, 0, 0, 0, 0, - 0, 238, 0, 239, 240, 138, 139, 0, 241, 0, - 0, 0, 0, 0, 0, 0, 0, 0, 52, 53, - 272, 100, 55, 56, 57, 58, 59, 60, 61, 62, - 63, 64, 65, 66, 67, 15, 0, 16, 0, 0, + 0, 0, 52, 53, 444, 100, 163, 164, 165, 166, + 167, 168, 169, 170, 171, 172, 173, 66, 67, 15, + 0, 16, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 460, 0, 0, 0, 0, 0, + 0, 0, 68, 0, 0, 468, 0, 0, 0, 0, + 472, 0, 0, 0, 475, 476, 265, 266, 52, 53, + 267, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 15, 0, 16, 0, 268, + 269, 270, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 271, 272, 0, 0, 0, 0, 0, 0, 0, + 0, 69, 0, 0, 70, 0, 0, 71, 0, 72, + 316, 273, 0, 0, 0, 0, 265, 266, 0, 0, + 267, 0, 0, 0, 117, 118, 119, 120, 121, 122, + 123, 124, 125, 126, 127, 128, 129, 130, 0, 268, + 269, 270, 0, 240, 0, 241, 242, 138, 139, 0, + 243, 271, 272, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 274, 0, 0, 0, 0, 0, 0, + 0, 273, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 117, 118, 119, 120, 121, 122, + 123, 124, 125, 126, 127, 128, 129, 130, 0, 0, + 0, 0, 0, 240, 0, 241, 242, 138, 139, 0, + 243, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 52, 53, 274, 100, 55, 56, 57, 58, 59, + 60, 61, 62, 63, 64, 65, 66, 67, 15, 0, + 16, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 184, 0, 0, 0, 0, 0, 52, + 53, 68, 100, 55, 56, 57, 58, 59, 60, 61, + 62, 63, 64, 65, 66, 67, 15, 0, 16, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 183, 0, 0, 0, 0, 0, 52, 53, 68, 100, - 55, 56, 57, 58, 59, 60, 61, 62, 63, 64, - 65, 66, 67, 15, 0, 16, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, 256, 0, - 0, 0, 0, 0, 52, 53, 68, 100, 162, 163, - 164, 165, 166, 167, 168, 169, 170, 171, 172, 66, - 67, 15, 0, 16, 0, 0, 69, 0, 0, 70, - 0, 0, 71, 0, 72, 0, 0, 0, 0, 0, - 0, 0, 52, 53, 68, 100, 55, 56, 57, 58, - 59, 60, 61, 62, 63, 64, 65, 66, 67, 15, - 0, 16, 0, 0, 69, 0, 0, 70, 0, 0, - 71, 0, 72, 0, 327, 0, 0, 0, 0, 0, - 52, 53, 68, 100, 55, 56, 57, 58, 59, 60, - 61, 62, 63, 64, 65, 66, 67, 15, 0, 16, - 0, 0, 69, 0, 0, 70, 0, 309, 71, 0, - 72, 0, 371, 0, 0, 0, 0, 0, 52, 53, - 68, 54, 55, 56, 57, 58, 59, 60, 61, 62, - 63, 64, 65, 66, 67, 15, 0, 16, 0, 0, + 0, 258, 0, 0, 0, 0, 0, 52, 53, 68, + 100, 163, 164, 165, 166, 167, 168, 169, 170, 171, + 172, 173, 66, 67, 15, 0, 16, 0, 0, 0, + 69, 0, 0, 70, 0, 0, 71, 0, 72, 0, + 0, 0, 0, 0, 0, 52, 53, 68, 100, 55, + 56, 57, 58, 59, 60, 61, 62, 63, 64, 65, + 66, 67, 15, 0, 16, 0, 0, 0, 69, 0, + 0, 70, 0, 0, 71, 0, 72, 330, 0, 0, + 0, 0, 0, 52, 53, 68, 100, 55, 56, 57, + 58, 59, 60, 61, 62, 63, 64, 65, 66, 67, + 15, 0, 16, 0, 0, 0, 69, 0, 0, 70, + 0, 312, 71, 0, 72, 375, 0, 0, 0, 0, + 0, 52, 53, 68, 54, 55, 56, 57, 58, 59, + 60, 61, 62, 63, 64, 65, 66, 67, 15, 0, + 16, 0, 0, 0, 69, 0, 0, 70, 0, 0, + 71, 0, 72, 0, 0, 0, 0, 0, 0, 52, + 53, 68, 100, 55, 56, 57, 58, 59, 60, 61, + 62, 63, 64, 65, 66, 67, 15, 0, 16, 0, + 0, 0, 69, 0, 0, 70, 0, 0, 71, 0, + 72, 0, 0, 0, 0, 0, 0, 52, 53, 68, + 100, 163, 164, 165, 166, 167, 168, 169, 170, 171, + 172, 173, 66, 67, 15, 0, 16, 0, 0, 0, 69, 0, 0, 70, 0, 0, 71, 0, 72, 0, - 0, 0, 0, 0, 0, 0, 52, 53, 68, 100, - 55, 56, 57, 58, 59, 60, 61, 62, 63, 64, - 65, 66, 67, 15, 0, 16, 0, 0, 69, 0, + 0, 0, 0, 0, 0, 52, 53, 68, 190, 55, + 56, 57, 58, 59, 60, 61, 62, 63, 64, 65, + 66, 67, 15, 0, 16, 0, 0, 0, 69, 0, 0, 70, 0, 0, 71, 0, 72, 0, 0, 0, - 0, 0, 0, 0, 52, 53, 68, 100, 162, 163, - 164, 165, 166, 167, 168, 169, 170, 171, 172, 66, - 67, 15, 0, 16, 0, 0, 69, 0, 0, 70, - 0, 0, 71, 0, 72, 0, 0, 0, 0, 0, - 0, 0, 52, 53, 68, 189, 55, 56, 57, 58, - 59, 60, 61, 62, 63, 64, 65, 66, 67, 15, - 0, 16, 0, 0, 69, 0, 0, 70, 0, 0, - 71, 0, 72, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 68, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 68, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 69, 0, 0, 70, 0, 0, 71, 0, - 72, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 107, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 108, 0, 0, 0, 0, 0, 0, 0, 0, - 69, 109, 110, 70, 0, 0, 71, 0, 72, 0, - 111, 112, 113, 114, 115, 116, 117, 118, 119, 120, - 121, 122, 123, 124, 125, 126, 127, 128, 129, 130, - 131, 132, 133, 0, 0, 134, 135, 136, 137, 138, - 139, 140, 141, 142, 143, 144 + 0, 0, 0, 0, 0, 0, 69, 0, 0, 70, + 0, 0, 71, 0, 72, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 107, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 108, 0, 0, 0, 0, + 0, 0, 0, 0, 69, 109, 110, 70, 0, 0, + 71, 0, 72, 0, 111, 112, 113, 114, 115, 116, + 117, 118, 119, 120, 121, 122, 123, 124, 125, 126, + 127, 128, 129, 130, 131, 132, 133, 0, 0, 134, + 135, 136, 137, 138, 139, 140, 141, 142, 143, 144, + 145 }; static const short yycheck[] = { 29, - 113, 113, 2, 44, 206, 72, 96, 29, 252, 23, - 58, 114, 243, 244, 44, 34, 30, 108, 434, 15, - 111, 10, 11, 12, 13, 14, 15, 16, 17, 0, - 15, 9, 108, 33, 450, 54, 102, 113, 105, 104, - 20, 272, 133, 21, 110, 136, 137, 150, 113, 140, - 141, 142, 143, 144, 25, 23, 110, 148, 54, 113, - 31, 41, 42, 43, 44, 95, 96, 47, 101, 54, - 41, 42, 43, 44, 74, 10, 11, 12, 13, 14, - 15, 16, 17, 58, 102, 102, 24, 102, 59, 111, - 102, 102, 449, 108, 112, 112, 108, 101, 112, 110, - 457, 131, 132, 4, 134, 135, 61, 62, 63, 64, - 101, 178, 179, 180, 358, 145, 146, 147, 20, 108, - 22, 104, 24, 49, 50, 51, 22, 101, 24, 31, - 32, 33, 101, 224, 32, 33, 52, 53, 4, 41, - 42, 43, 44, 106, 176, 47, 48, 88, 89, 27, - 28, 4, 182, 55, 186, 3, 4, 59, 4, 191, - 192, 3, 4, 204, 3, 4, 3, 4, 3, 4, - 104, 203, 24, 108, 204, 4, 208, 24, 380, 107, - 382, 222, 107, 104, 56, 4, 218, 219, 220, 4, - 4, 4, 222, 223, 261, 7, 7, 4, 289, 7, - 291, 292, 102, 106, 36, 102, 105, 298, 102, 102, - 102, 102, 242, 243, 244, 305, 306, 307, 308, 102, - 102, 102, 102, 102, 24, 102, 316, 317, 318, 319, - 10, 11, 12, 13, 14, 15, 16, 17, 24, 104, - 104, 104, 272, 105, 104, 104, 104, 104, 280, 104, - 60, 102, 102, 102, 286, 34, 24, 257, 288, 102, - 290, 106, 102, 293, 294, 21, 102, 299, 300, 102, - 21, 102, 4, 363, 104, 305, 306, 307, 308, 102, - 102, 102, 24, 4, 104, 102, 316, 317, 318, 319, - 36, 54, 4, 102, 24, 325, 387, 388, 102, 102, - 102, 102, 334, 102, 336, 102, 102, 102, 340, 399, - 400, 105, 402, 403, 404, 405, 348, 349, 350, 102, - 105, 434, 434, 54, 354, 416, 108, 102, 106, 105, - 191, 192, 105, 363, 105, 105, 105, 450, 450, 105, - 105, 21, 203, 36, 108, 377, 378, 208, 21, 102, - 105, 441, 21, 385, 102, 69, 21, 218, 219, 220, - 21, 393, 0, 0, 84, 84, 84, 84, 398, 399, - 400, 33, 402, 403, 404, 405, 5, 6, 20, 326, - 105, 325, 46, 176, 43, 2, 418, 23, 14, 337, - 392, -1, 359, 22, -1, 24, -1, 26, -1, -1, - -1, -1, -1, -1, -1, -1, -1, -1, -1, 38, - 39, 441, -1, -1, -1, 447, -1, -1, -1, 280, - -1, -1, -1, -1, -1, 286, 458, -1, -1, -1, - -1, 463, -1, -1, -1, 467, 468, -1, 299, 300, - -1, -1, 71, 72, 73, 74, 75, 76, 77, 78, - 79, 80, 81, 82, 83, 84, -1, -1, -1, -1, - -1, 90, -1, 92, 93, 94, 95, -1, 97, -1, - -1, -1, -1, 334, -1, 336, -1, 106, -1, 340, - 109, -1, 111, -1, -1, 114, -1, 348, 349, 350, - -1, -1, -1, -1, 5, 6, -1, 8, 9, 10, - 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, - 21, 22, -1, 24, -1, -1, 377, 378, -1, -1, - -1, -1, -1, -1, 385, -1, -1, -1, -1, -1, - -1, -1, 393, -1, 45, 5, 6, -1, 8, 9, - 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, - 20, 21, 22, -1, 24, -1, -1, 418, -1, -1, - -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, - -1, -1, -1, -1, -1, 45, -1, -1, -1, -1, - -1, -1, -1, -1, -1, -1, 447, -1, -1, -1, - -1, -1, 103, -1, -1, 106, -1, 458, 109, -1, - 111, 112, 463, -1, -1, -1, 467, 468, -1, -1, + 113, 2, 113, 44, 254, 96, 72, 207, 29, 15, + 23, 34, 114, 20, 44, 245, 246, 30, 108, 15, + 58, 111, 10, 11, 12, 13, 14, 15, 16, 17, + 9, 54, 33, 109, 41, 42, 43, 44, 114, 105, + 47, 440, 21, 133, 274, 23, 136, 137, 54, 151, + 140, 141, 142, 143, 144, 145, 103, 456, 54, 149, + 103, 103, 32, 33, 111, 95, 96, 27, 28, 111, + 113, 5, 6, 74, 8, 9, 10, 11, 12, 13, + 14, 15, 16, 17, 18, 19, 20, 21, 22, 58, + 24, 112, 10, 11, 12, 13, 14, 15, 16, 17, + 113, 131, 132, 102, 134, 135, 0, 111, 24, 103, + 114, 45, 362, 179, 180, 181, 146, 147, 148, 113, + 105, 109, 455, 49, 50, 51, 103, 103, 102, 114, + 463, 25, 109, 109, 88, 89, 226, 31, 61, 62, + 63, 64, 22, 4, 24, 177, 102, 41, 42, 43, + 44, 52, 53, 183, 102, 187, 3, 4, 3, 4, + 192, 193, 3, 4, 205, 59, 3, 4, 3, 4, + 104, 102, 204, 107, 107, 205, 110, 209, 112, 113, + 105, 4, 4, 224, 384, 4, 386, 4, 220, 221, + 222, 109, 105, 24, 224, 225, 24, 263, 108, 108, + 105, 291, 56, 293, 294, 295, 4, 4, 4, 4, + 103, 301, 4, 7, 244, 245, 246, 308, 309, 310, + 311, 7, 7, 106, 103, 103, 107, 103, 319, 320, + 321, 322, 10, 11, 12, 13, 14, 15, 16, 17, + 103, 103, 24, 36, 274, 103, 103, 103, 103, 24, + 282, 103, 103, 103, 103, 60, 288, 105, 259, 105, + 290, 105, 292, 105, 103, 105, 296, 297, 106, 105, + 302, 303, 105, 105, 103, 34, 367, 103, 308, 309, + 310, 311, 107, 103, 24, 103, 21, 103, 103, 319, + 320, 321, 322, 21, 105, 4, 103, 103, 328, 103, + 103, 391, 392, 393, 105, 337, 24, 339, 4, 36, + 54, 343, 103, 404, 405, 103, 407, 408, 409, 410, + 352, 353, 354, 192, 193, 106, 103, 440, 358, 440, + 103, 421, 103, 103, 103, 204, 103, 367, 103, 103, + 209, 4, 24, 456, 107, 456, 103, 54, 106, 381, + 382, 220, 221, 222, 109, 106, 447, 389, 106, 106, + 103, 106, 21, 36, 106, 106, 398, 106, 21, 106, + 103, 109, 21, 403, 404, 405, 69, 407, 408, 409, + 410, 20, 103, 22, 21, 24, 21, 0, 0, 84, + 84, 423, 31, 32, 33, 84, 84, 33, 20, 329, + 105, 177, 41, 42, 43, 44, 46, 328, 47, 48, + 43, 2, 23, 282, 14, 397, 55, 447, 340, 288, + 59, 453, 363, -1, -1, -1, -1, -1, -1, 5, + 6, -1, 464, 302, 303, -1, -1, 469, -1, -1, + -1, 473, 474, -1, -1, -1, 22, -1, 24, -1, + 26, -1, -1, -1, -1, -1, -1, -1, -1, -1, + -1, -1, 38, 39, -1, -1, -1, -1, 337, -1, + 339, -1, -1, -1, 343, -1, -1, -1, -1, -1, + -1, -1, -1, 352, 353, 354, -1, -1, -1, -1, + -1, -1, -1, -1, -1, 71, 72, 73, 74, 75, + 76, 77, 78, 79, 80, 81, 82, 83, 84, -1, + -1, -1, 381, 382, 90, -1, 92, 93, 94, 95, + 389, 97, -1, -1, -1, -1, -1, -1, -1, 398, + -1, 107, -1, -1, 110, -1, 112, -1, -1, 115, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, - 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ThrowException("Value too large for type!"); @@ -2234,7 +2234,7 @@ ; break;} case 4: -#line 1019 "/Users/sabre/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1019 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { if (yyvsp[0].UInt64Val > (uint64_t)INT64_MAX) // Outside of my range! ThrowException("Value too large for type!"); @@ -2242,55 +2242,55 @@ ; break;} case 33: -#line 1042 "/Users/sabre/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1042 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { yyval.StrVal = yyvsp[-1].StrVal; ; break;} case 34: -#line 1045 "/Users/sabre/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1045 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { yyval.StrVal = 0; ; break;} case 35: -#line 1049 "/Users/sabre/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1049 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { yyval.Linkage = GlobalValue::InternalLinkage; ; break;} case 36: -#line 1050 "/Users/sabre/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1050 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { yyval.Linkage = GlobalValue::LinkOnceLinkage; ; break;} case 37: -#line 1051 "/Users/sabre/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1051 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { yyval.Linkage = GlobalValue::WeakLinkage; ; break;} case 38: -#line 1052 "/Users/sabre/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1052 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { yyval.Linkage = GlobalValue::AppendingLinkage; ; break;} case 39: -#line 1053 "/Users/sabre/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1053 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { yyval.Linkage = GlobalValue::ExternalLinkage; ; break;} case 40: -#line 1055 "/Users/sabre/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1055 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { yyval.UIntVal = CallingConv::C; ; break;} case 41: -#line 1056 "/Users/sabre/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1056 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { yyval.UIntVal = CallingConv::C; ; break;} case 42: -#line 1057 "/Users/sabre/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1057 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { yyval.UIntVal = CallingConv::Fast; ; break;} case 43: -#line 1058 "/Users/sabre/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1058 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { yyval.UIntVal = CallingConv::Cold; ; break;} case 44: -#line 1059 "/Users/sabre/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1059 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { if ((unsigned)yyvsp[0].UInt64Val != yyvsp[0].UInt64Val) ThrowException("Calling conv too large!"); @@ -2298,11 +2298,11 @@ ; break;} case 45: -#line 1067 "/Users/sabre/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1067 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { yyval.UIntVal = 0; ; break;} case 46: -#line 1068 "/Users/sabre/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1068 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { yyval.UIntVal = yyvsp[0].UInt64Val; if (yyval.UIntVal != 0 && !isPowerOf2_32(yyval.UIntVal)) @@ -2310,11 +2310,11 @@ ; break;} case 47: -#line 1073 "/Users/sabre/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1073 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { yyval.UIntVal = 0; ; break;} case 48: -#line 1074 "/Users/sabre/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1074 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { yyval.UIntVal = yyvsp[0].UInt64Val; if (yyval.UIntVal != 0 && !isPowerOf2_32(yyval.UIntVal)) @@ -2322,7 +2322,7 @@ ; break;} case 49: -#line 1081 "/Users/sabre/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1081 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { for (unsigned i = 0, e = strlen(yyvsp[0].StrVal); i != e; ++i) if (yyvsp[0].StrVal[i] == '"' || yyvsp[0].StrVal[i] == '\\') @@ -2331,30 +2331,30 @@ ; break;} case 50: -#line 1088 "/Users/sabre/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1088 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { yyval.StrVal = 0; ; break;} case 51: -#line 1089 "/Users/sabre/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1089 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { yyval.StrVal = yyvsp[0].StrVal; ; break;} case 52: -#line 1094 "/Users/sabre/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1094 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" {; break;} case 53: -#line 1095 "/Users/sabre/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1095 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" {; break;} case 54: -#line 1096 "/Users/sabre/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1096 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { CurGV->setSection(yyvsp[0].StrVal); free(yyvsp[0].StrVal); ; break;} case 55: -#line 1100 "/Users/sabre/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1100 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { if (yyvsp[0].UInt64Val != 0 && !isPowerOf2_32(yyvsp[0].UInt64Val)) ThrowException("Alignment must be a power of two!"); @@ -2362,15 +2362,15 @@ ; break;} case 57: -#line 1113 "/Users/sabre/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1113 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { yyval.TypeVal = new PATypeHolder(yyvsp[0].PrimType); ; break;} case 59: -#line 1114 "/Users/sabre/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1114 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { yyval.TypeVal = new PATypeHolder(yyvsp[0].PrimType); ; break;} case 60: -#line 1116 "/Users/sabre/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1116 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { if (!UpRefs.empty()) ThrowException("Invalid upreference in type: " + (*yyvsp[0].TypeVal)->getDescription()); @@ -2378,25 +2378,25 @@ ; break;} case 74: -#line 1127 "/Users/sabre/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1127 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { yyval.TypeVal = new PATypeHolder(OpaqueType::get()); ; break;} case 75: -#line 1130 "/Users/sabre/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1130 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { yyval.TypeVal = new PATypeHolder(yyvsp[0].PrimType); ; break;} case 76: -#line 1133 "/Users/sabre/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1133 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { // Named types are also simple types... yyval.TypeVal = new PATypeHolder(getTypeVal(yyvsp[0].ValIDVal)); ; break;} case 77: -#line 1139 "/Users/sabre/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1139 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { // Type UpReference if (yyvsp[0].UInt64Val > (uint64_t)~0U) ThrowException("Value out of range!"); OpaqueType *OT = OpaqueType::get(); // Use temporary placeholder @@ -2406,7 +2406,7 @@ ; break;} case 78: -#line 1146 "/Users/sabre/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1146 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { // Function derived type? std::vector Params; for (std::list::iterator I = yyvsp[-1].TypeList->begin(), @@ -2421,14 +2421,14 @@ ; break;} case 79: -#line 1158 "/Users/sabre/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1158 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { // Sized array type? yyval.TypeVal = new PATypeHolder(HandleUpRefs(ArrayType::get(*yyvsp[-1].TypeVal, (unsigned)yyvsp[-3].UInt64Val))); delete yyvsp[-1].TypeVal; ; break;} case 80: -#line 1162 "/Users/sabre/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1162 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { // Packed array type? const llvm::Type* ElemTy = yyvsp[-1].TypeVal->get(); if ((unsigned)yyvsp[-3].UInt64Val != yyvsp[-3].UInt64Val) @@ -2442,7 +2442,7 @@ ; break;} case 81: -#line 1173 "/Users/sabre/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1173 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { // Structure type? std::vector Elements; for (std::list::iterator I = yyvsp[-1].TypeList->begin(), @@ -2454,51 +2454,51 @@ ; break;} case 82: -#line 1182 "/Users/sabre/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1182 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { // Empty structure type? yyval.TypeVal = new PATypeHolder(StructType::get(std::vector())); ; break;} case 83: -#line 1185 "/Users/sabre/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1185 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { // Pointer type? yyval.TypeVal = new PATypeHolder(HandleUpRefs(PointerType::get(*yyvsp[-1].TypeVal))); delete yyvsp[-1].TypeVal; ; break;} case 84: -#line 1193 "/Users/sabre/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1193 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { yyval.TypeList = new std::list(); yyval.TypeList->push_back(*yyvsp[0].TypeVal); delete yyvsp[0].TypeVal; ; break;} case 85: -#line 1197 "/Users/sabre/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1197 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { (yyval.TypeList=yyvsp[-2].TypeList)->push_back(*yyvsp[0].TypeVal); delete yyvsp[0].TypeVal; ; break;} case 87: -#line 1203 "/Users/sabre/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1203 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { (yyval.TypeList=yyvsp[-2].TypeList)->push_back(Type::VoidTy); ; break;} case 88: -#line 1206 "/Users/sabre/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1206 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { (yyval.TypeList = new std::list())->push_back(Type::VoidTy); ; break;} case 89: -#line 1209 "/Users/sabre/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1209 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { yyval.TypeList = new std::list(); ; break;} case 90: -#line 1219 "/Users/sabre/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1219 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { // Nonempty unsized arr const ArrayType *ATy = dyn_cast(yyvsp[-3].TypeVal->get()); if (ATy == 0) @@ -2526,7 +2526,7 @@ ; break;} case 91: -#line 1244 "/Users/sabre/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1244 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { const ArrayType *ATy = dyn_cast(yyvsp[-2].TypeVal->get()); if (ATy == 0) @@ -2542,7 +2542,7 @@ ; break;} case 92: -#line 1257 "/Users/sabre/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1257 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { const ArrayType *ATy = dyn_cast(yyvsp[-2].TypeVal->get()); if (ATy == 0) @@ -2574,7 +2574,7 @@ ; break;} case 93: -#line 1286 "/Users/sabre/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1286 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { // Nonempty unsized arr const PackedType *PTy = dyn_cast(yyvsp[-3].TypeVal->get()); if (PTy == 0) @@ -2602,7 +2602,7 @@ ; break;} case 94: -#line 1311 "/Users/sabre/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1311 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { const StructType *STy = dyn_cast(yyvsp[-3].TypeVal->get()); if (STy == 0) @@ -2625,7 +2625,7 @@ ; break;} case 95: -#line 1331 "/Users/sabre/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1331 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { const StructType *STy = dyn_cast(yyvsp[-2].TypeVal->get()); if (STy == 0) @@ -2640,7 +2640,7 @@ ; break;} case 96: -#line 1343 "/Users/sabre/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1343 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { const PointerType *PTy = dyn_cast(yyvsp[-1].TypeVal->get()); if (PTy == 0) @@ -2652,14 +2652,14 @@ ; break;} case 97: -#line 1352 "/Users/sabre/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1352 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { yyval.ConstVal = UndefValue::get(yyvsp[-1].TypeVal->get()); delete yyvsp[-1].TypeVal; ; break;} case 98: -#line 1356 "/Users/sabre/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1356 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { const PointerType *Ty = dyn_cast(yyvsp[-1].TypeVal->get()); if (Ty == 0) @@ -2721,7 +2721,7 @@ ; break;} case 99: -#line 1415 "/Users/sabre/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1415 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { if (yyvsp[-1].TypeVal->get() != yyvsp[0].ConstVal->getType()) ThrowException("Mismatched types for constant expression!"); @@ -2730,7 +2730,7 @@ ; break;} case 100: -#line 1421 "/Users/sabre/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1421 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { const Type *Ty = yyvsp[-1].TypeVal->get(); if (isa(Ty) || Ty == Type::LabelTy || isa(Ty)) @@ -2740,7 +2740,7 @@ ; break;} case 101: -#line 1429 "/Users/sabre/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1429 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { // integral constants if (!ConstantSInt::isValueValidForType(yyvsp[-1].PrimType, yyvsp[0].SInt64Val)) ThrowException("Constant value doesn't fit in type!"); @@ -2748,7 +2748,7 @@ ; break;} case 102: -#line 1434 "/Users/sabre/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1434 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { // integral constants if (!ConstantUInt::isValueValidForType(yyvsp[-1].PrimType, yyvsp[0].UInt64Val)) ThrowException("Constant value doesn't fit in type!"); @@ -2756,19 +2756,19 @@ ; break;} case 103: -#line 1439 "/Users/sabre/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1439 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { // Boolean constants yyval.ConstVal = ConstantBool::True; ; break;} case 104: -#line 1442 "/Users/sabre/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1442 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { // Boolean constants yyval.ConstVal = ConstantBool::False; ; break;} case 105: -#line 1445 "/Users/sabre/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1445 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { // Float & Double constants if (!ConstantFP::isValueValidForType(yyvsp[-1].PrimType, yyvsp[0].FPVal)) ThrowException("Floating point constant invalid for type!!"); @@ -2776,7 +2776,7 @@ ; break;} case 106: -#line 1452 "/Users/sabre/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1452 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { if (!yyvsp[-3].ConstVal->getType()->isFirstClassType()) ThrowException("cast constant expression from a non-primitive type: '" + @@ -2789,7 +2789,7 @@ ; break;} case 107: -#line 1462 "/Users/sabre/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1462 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { if (!isa(yyvsp[-2].ConstVal->getType())) ThrowException("GetElementPtr requires a pointer operand!"); @@ -2823,7 +2823,7 @@ ; break;} case 108: -#line 1493 "/Users/sabre/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1493 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { if (yyvsp[-5].ConstVal->getType() != Type::BoolTy) ThrowException("Select condition must be of boolean type!"); @@ -2833,7 +2833,7 @@ ; break;} case 109: -#line 1500 "/Users/sabre/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1500 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { if (yyvsp[-3].ConstVal->getType() != yyvsp[-1].ConstVal->getType()) ThrowException("Binary operator types must match!"); @@ -2857,7 +2857,7 @@ ; break;} case 110: -#line 1521 "/Users/sabre/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1521 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { if (yyvsp[-3].ConstVal->getType() != yyvsp[-1].ConstVal->getType()) ThrowException("Logical operator types must match!"); @@ -2870,7 +2870,7 @@ ; break;} case 111: -#line 1531 "/Users/sabre/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1531 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { if (yyvsp[-3].ConstVal->getType() != yyvsp[-1].ConstVal->getType()) ThrowException("setcc operand types must match!"); @@ -2878,7 +2878,7 @@ ; break;} case 112: -#line 1536 "/Users/sabre/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1536 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { if (yyvsp[-1].ConstVal->getType() != Type::UByteTy) ThrowException("Shift count for shift constant must be unsigned byte!"); @@ -2888,7 +2888,7 @@ ; break;} case 113: -#line 1543 "/Users/sabre/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1543 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { if (!isa(yyvsp[-3].ConstVal->getType())) ThrowException("First operand of extractelement must be " @@ -2899,60 +2899,60 @@ ; break;} case 114: -#line 1553 "/Users/sabre/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1553 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { (yyval.ConstVector = yyvsp[-2].ConstVector)->push_back(yyvsp[0].ConstVal); ; break;} case 115: -#line 1556 "/Users/sabre/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1556 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { yyval.ConstVector = new std::vector(); yyval.ConstVector->push_back(yyvsp[0].ConstVal); ; break;} case 116: -#line 1563 "/Users/sabre/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1563 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { yyval.BoolVal = false; ; break;} case 117: -#line 1563 "/Users/sabre/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1563 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { yyval.BoolVal = true; ; break;} case 118: -#line 1573 "/Users/sabre/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1573 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { yyval.ModuleVal = ParserResult = yyvsp[0].ModuleVal; CurModule.ModuleDone(); ; break;} case 119: -#line 1580 "/Users/sabre/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1580 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { yyval.ModuleVal = yyvsp[-1].ModuleVal; CurFun.FunctionDone(); ; break;} case 120: -#line 1584 "/Users/sabre/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1584 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { yyval.ModuleVal = yyvsp[-1].ModuleVal; ; break;} case 121: -#line 1587 "/Users/sabre/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1587 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { yyval.ModuleVal = yyvsp[-3].ModuleVal; ; break;} case 122: -#line 1590 "/Users/sabre/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1590 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { yyval.ModuleVal = yyvsp[-1].ModuleVal; ; break;} case 123: -#line 1593 "/Users/sabre/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1593 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { yyval.ModuleVal = CurModule.CurrentModule; // Emit an error if there are any unresolved types left. @@ -2966,7 +2966,7 @@ ; break;} case 124: -#line 1606 "/Users/sabre/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1606 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { // Eagerly resolve types. This is not an optimization, this is a // requirement that is due to the fact that we could have this: @@ -2989,30 +2989,30 @@ ; break;} case 125: -#line 1626 "/Users/sabre/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1626 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { // Function prototypes can be in const pool ; break;} case 126: -#line 1628 "/Users/sabre/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1628 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { // Asm blocks can be in the const pool ; break;} case 127: -#line 1630 "/Users/sabre/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1630 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { if (yyvsp[0].ConstVal == 0) ThrowException("Global value initializer is not a constant!"); CurGV = ParseGlobalVariable(yyvsp[-3].StrVal, yyvsp[-2].Linkage, yyvsp[-1].BoolVal, yyvsp[0].ConstVal->getType(), yyvsp[0].ConstVal); ; break;} case 128: -#line 1633 "/Users/sabre/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1633 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { CurGV = 0; ; break;} case 129: -#line 1636 "/Users/sabre/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1636 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { CurGV = ParseGlobalVariable(yyvsp[-3].StrVal, GlobalValue::ExternalLinkage, yyvsp[-1].BoolVal, *yyvsp[0].TypeVal, 0); @@ -3020,28 +3020,28 @@ ; break;} case 130: -#line 1640 "/Users/sabre/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1640 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { CurGV = 0; ; break;} case 131: -#line 1643 "/Users/sabre/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1643 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { ; break;} case 132: -#line 1645 "/Users/sabre/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1645 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { ; break;} case 133: -#line 1647 "/Users/sabre/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1647 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { ; break;} case 134: -#line 1651 "/Users/sabre/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1651 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { const std::string &AsmSoFar = CurModule.CurrentModule->getModuleInlineAsm(); char *EndStr = UnEscapeLexed(yyvsp[0].StrVal, true); @@ -3055,21 +3055,21 @@ ; break;} case 135: -#line 1663 "/Users/sabre/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1663 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { yyval.Endianness = Module::BigEndian; ; break;} case 136: -#line 1664 "/Users/sabre/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1664 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { yyval.Endianness = Module::LittleEndian; ; break;} case 137: -#line 1666 "/Users/sabre/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1666 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { CurModule.CurrentModule->setEndianness(yyvsp[0].Endianness); ; break;} case 138: -#line 1669 "/Users/sabre/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1669 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { if (yyvsp[0].UInt64Val == 32) CurModule.CurrentModule->setPointerSize(Module::Pointer32); @@ -3080,37 +3080,37 @@ ; break;} case 139: -#line 1677 "/Users/sabre/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1677 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { CurModule.CurrentModule->setTargetTriple(yyvsp[0].StrVal); free(yyvsp[0].StrVal); ; break;} case 141: -#line 1684 "/Users/sabre/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1684 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { CurModule.CurrentModule->addLibrary(yyvsp[0].StrVal); free(yyvsp[0].StrVal); ; break;} case 142: -#line 1688 "/Users/sabre/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1688 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { CurModule.CurrentModule->addLibrary(yyvsp[0].StrVal); free(yyvsp[0].StrVal); ; break;} case 143: -#line 1692 "/Users/sabre/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1692 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { ; break;} case 147: -#line 1701 "/Users/sabre/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1701 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { yyval.StrVal = 0; ; break;} case 148: -#line 1703 "/Users/sabre/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1703 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { if (*yyvsp[-1].TypeVal == Type::VoidTy) ThrowException("void typed arguments are invalid!"); @@ -3118,7 +3118,7 @@ ; break;} case 149: -#line 1709 "/Users/sabre/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1709 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { yyval.ArgList = yyvsp[-2].ArgList; yyvsp[-2].ArgList->push_back(*yyvsp[0].ArgVal); @@ -3126,7 +3126,7 @@ ; break;} case 150: -#line 1714 "/Users/sabre/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1714 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { yyval.ArgList = new std::vector >(); yyval.ArgList->push_back(*yyvsp[0].ArgVal); @@ -3134,13 +3134,13 @@ ; break;} case 151: -#line 1720 "/Users/sabre/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1720 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { yyval.ArgList = yyvsp[0].ArgList; ; break;} case 152: -#line 1723 "/Users/sabre/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1723 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { yyval.ArgList = yyvsp[-2].ArgList; yyval.ArgList->push_back(std::pair >(); yyval.ArgList->push_back(std::make_pair(new PATypeHolder(Type::VoidTy), (char*)0)); ; break;} case 154: -#line 1732 "/Users/sabre/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1732 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { yyval.ArgList = 0; ; break;} case 155: -#line 1737 "/Users/sabre/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1737 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { UnEscapeLexed(yyvsp[-5].StrVal); std::string FunctionName(yyvsp[-5].StrVal); @@ -3248,7 +3248,7 @@ ; break;} case 158: -#line 1824 "/Users/sabre/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1824 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { yyval.FunctionVal = CurFun.CurrentFunction; @@ -3258,84 +3258,84 @@ ; break;} case 161: -#line 1834 "/Users/sabre/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1834 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { yyval.FunctionVal = yyvsp[-1].FunctionVal; ; break;} case 162: -#line 1838 "/Users/sabre/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1838 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { CurFun.isDeclare = true; ; break;} case 163: -#line 1838 "/Users/sabre/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1838 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { yyval.FunctionVal = CurFun.CurrentFunction; CurFun.FunctionDone(); ; break;} case 164: -#line 1847 "/Users/sabre/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1847 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { yyval.BoolVal = false; ; break;} case 165: -#line 1850 "/Users/sabre/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1850 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { yyval.BoolVal = true; ; break;} case 166: -#line 1854 "/Users/sabre/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1854 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { // A reference to a direct constant yyval.ValIDVal = ValID::create(yyvsp[0].SInt64Val); ; break;} case 167: -#line 1857 "/Users/sabre/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1857 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { yyval.ValIDVal = ValID::create(yyvsp[0].UInt64Val); ; break;} case 168: -#line 1860 "/Users/sabre/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1860 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { // Perhaps it's an FP constant? yyval.ValIDVal = ValID::create(yyvsp[0].FPVal); ; break;} case 169: -#line 1863 "/Users/sabre/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1863 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { yyval.ValIDVal = ValID::create(ConstantBool::True); ; break;} case 170: -#line 1866 "/Users/sabre/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1866 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { yyval.ValIDVal = ValID::create(ConstantBool::False); ; break;} case 171: -#line 1869 "/Users/sabre/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1869 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { yyval.ValIDVal = ValID::createNull(); ; break;} case 172: -#line 1872 "/Users/sabre/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1872 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { yyval.ValIDVal = ValID::createUndef(); ; break;} case 173: -#line 1875 "/Users/sabre/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1875 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { // A vector zero constant. yyval.ValIDVal = ValID::createZeroInit(); ; break;} case 174: -#line 1878 "/Users/sabre/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1878 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { // Nonempty unsized packed vector const Type *ETy = (*yyvsp[-1].ConstVector)[0]->getType(); int NumElements = yyvsp[-1].ConstVector->size(); @@ -3362,13 +3362,13 @@ ; break;} case 175: -#line 1902 "/Users/sabre/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1902 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { yyval.ValIDVal = ValID::create(yyvsp[0].ConstVal); ; break;} case 176: -#line 1905 "/Users/sabre/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1905 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { char *End = UnEscapeLexed(yyvsp[-2].StrVal, true); std::string AsmStr = std::string(yyvsp[-2].StrVal, End); @@ -3380,37 +3380,37 @@ ; break;} case 177: -#line 1918 "/Users/sabre/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1918 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { // Is it an integer reference...? yyval.ValIDVal = ValID::create(yyvsp[0].SIntVal); ; break;} case 178: -#line 1921 "/Users/sabre/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1921 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { // Is it a named reference...? yyval.ValIDVal = ValID::create(yyvsp[0].StrVal); ; break;} case 181: -#line 1932 "/Users/sabre/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1932 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { yyval.ValueVal = getVal(*yyvsp[-1].TypeVal, yyvsp[0].ValIDVal); delete yyvsp[-1].TypeVal; ; break;} case 182: -#line 1936 "/Users/sabre/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1936 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { yyval.FunctionVal = yyvsp[-1].FunctionVal; ; break;} case 183: -#line 1939 "/Users/sabre/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1939 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { // Do not allow functions with 0 basic blocks yyval.FunctionVal = yyvsp[-1].FunctionVal; ; break;} case 184: -#line 1947 "/Users/sabre/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1947 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { setValueName(yyvsp[0].TermInstVal, yyvsp[-1].StrVal); InsertValue(yyvsp[0].TermInstVal); @@ -3421,14 +3421,14 @@ ; break;} case 185: -#line 1956 "/Users/sabre/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1956 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { yyvsp[-1].BasicBlockVal->getInstList().push_back(yyvsp[0].InstVal); yyval.BasicBlockVal = yyvsp[-1].BasicBlockVal; ; break;} case 186: -#line 1960 "/Users/sabre/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1960 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { yyval.BasicBlockVal = CurBB = getBBVal(ValID::create((int)CurFun.NextBBNum++), true); @@ -3441,7 +3441,7 @@ ; break;} case 187: -#line 1970 "/Users/sabre/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1970 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { yyval.BasicBlockVal = CurBB = getBBVal(ValID::create(yyvsp[0].StrVal), true); @@ -3454,31 +3454,31 @@ ; break;} case 188: -#line 1981 "/Users/sabre/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1981 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { // Return with a result... yyval.TermInstVal = new ReturnInst(yyvsp[0].ValueVal); ; break;} case 189: -#line 1984 "/Users/sabre/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1984 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { // Return with no result... yyval.TermInstVal = new ReturnInst(); ; break;} case 190: -#line 1987 "/Users/sabre/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1987 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { // Unconditional Branch... yyval.TermInstVal = new BranchInst(getBBVal(yyvsp[0].ValIDVal)); ; break;} case 191: -#line 1990 "/Users/sabre/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1990 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { yyval.TermInstVal = new BranchInst(getBBVal(yyvsp[-3].ValIDVal), getBBVal(yyvsp[0].ValIDVal), getVal(Type::BoolTy, yyvsp[-6].ValIDVal)); ; break;} case 192: -#line 1993 "/Users/sabre/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1993 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { SwitchInst *S = new SwitchInst(getVal(yyvsp[-7].PrimType, yyvsp[-6].ValIDVal), getBBVal(yyvsp[-3].ValIDVal), yyvsp[-1].JumpTable->size()); yyval.TermInstVal = S; @@ -3495,14 +3495,14 @@ ; break;} case 193: -#line 2007 "/Users/sabre/llvm/lib/AsmParser/llvmAsmParser.y" +#line 2007 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { SwitchInst *S = new SwitchInst(getVal(yyvsp[-6].PrimType, yyvsp[-5].ValIDVal), getBBVal(yyvsp[-2].ValIDVal), 0); yyval.TermInstVal = S; ; break;} case 194: -#line 2012 "/Users/sabre/llvm/lib/AsmParser/llvmAsmParser.y" +#line 2012 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { const PointerType *PFTy; const FunctionType *Ty; @@ -3557,19 +3557,19 @@ ; break;} case 195: -#line 2064 "/Users/sabre/llvm/lib/AsmParser/llvmAsmParser.y" +#line 2064 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { yyval.TermInstVal = new UnwindInst(); ; break;} case 196: -#line 2067 "/Users/sabre/llvm/lib/AsmParser/llvmAsmParser.y" +#line 2067 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { yyval.TermInstVal = new UnreachableInst(); ; break;} case 197: -#line 2073 "/Users/sabre/llvm/lib/AsmParser/llvmAsmParser.y" +#line 2073 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { yyval.JumpTable = yyvsp[-5].JumpTable; Constant *V = cast(getValNonImprovising(yyvsp[-4].PrimType, yyvsp[-3].ValIDVal)); @@ -3580,7 +3580,7 @@ ; break;} case 198: -#line 2081 "/Users/sabre/llvm/lib/AsmParser/llvmAsmParser.y" +#line 2081 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { yyval.JumpTable = new std::vector >(); Constant *V = cast(getValNonImprovising(yyvsp[-4].PrimType, yyvsp[-3].ValIDVal)); @@ -3592,7 +3592,7 @@ ; break;} case 199: -#line 2091 "/Users/sabre/llvm/lib/AsmParser/llvmAsmParser.y" +#line 2091 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { // Is this definition named?? if so, assign the name... setValueName(yyvsp[0].InstVal, yyvsp[-1].StrVal); @@ -3601,7 +3601,7 @@ ; break;} case 200: -#line 2098 "/Users/sabre/llvm/lib/AsmParser/llvmAsmParser.y" +#line 2098 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { // Used for PHI nodes yyval.PHIList = new std::list >(); yyval.PHIList->push_back(std::make_pair(getVal(*yyvsp[-5].TypeVal, yyvsp[-3].ValIDVal), getBBVal(yyvsp[-1].ValIDVal))); @@ -3609,7 +3609,7 @@ ; break;} case 201: -#line 2103 "/Users/sabre/llvm/lib/AsmParser/llvmAsmParser.y" +#line 2103 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { yyval.PHIList = yyvsp[-6].PHIList; yyvsp[-6].PHIList->push_back(std::make_pair(getVal(yyvsp[-6].PHIList->front().first->getType(), yyvsp[-3].ValIDVal), @@ -3617,37 +3617,37 @@ ; break;} case 202: -#line 2110 "/Users/sabre/llvm/lib/AsmParser/llvmAsmParser.y" +#line 2110 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { // Used for call statements, and memory insts... yyval.ValueList = new std::vector(); yyval.ValueList->push_back(yyvsp[0].ValueVal); ; break;} case 203: -#line 2114 "/Users/sabre/llvm/lib/AsmParser/llvmAsmParser.y" +#line 2114 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { yyval.ValueList = yyvsp[-2].ValueList; yyvsp[-2].ValueList->push_back(yyvsp[0].ValueVal); ; break;} case 205: -#line 2120 "/Users/sabre/llvm/lib/AsmParser/llvmAsmParser.y" +#line 2120 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { yyval.ValueList = 0; ; break;} case 206: -#line 2122 "/Users/sabre/llvm/lib/AsmParser/llvmAsmParser.y" +#line 2122 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { yyval.BoolVal = true; ; break;} case 207: -#line 2125 "/Users/sabre/llvm/lib/AsmParser/llvmAsmParser.y" +#line 2125 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { yyval.BoolVal = false; ; break;} case 208: -#line 2131 "/Users/sabre/llvm/lib/AsmParser/llvmAsmParser.y" +#line 2131 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { if (!(*yyvsp[-3].TypeVal)->isInteger() && !(*yyvsp[-3].TypeVal)->isFloatingPoint() && !isa((*yyvsp[-3].TypeVal).get())) @@ -3662,7 +3662,7 @@ ; break;} case 209: -#line 2143 "/Users/sabre/llvm/lib/AsmParser/llvmAsmParser.y" +#line 2143 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { if (!(*yyvsp[-3].TypeVal)->isIntegral()) { if (!isa(yyvsp[-3].TypeVal->get()) || @@ -3676,7 +3676,7 @@ ; break;} case 210: -#line 2154 "/Users/sabre/llvm/lib/AsmParser/llvmAsmParser.y" +#line 2154 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { if(isa((*yyvsp[-3].TypeVal).get())) { ThrowException( @@ -3689,7 +3689,7 @@ ; break;} case 211: -#line 2164 "/Users/sabre/llvm/lib/AsmParser/llvmAsmParser.y" +#line 2164 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { std::cerr << "WARNING: Use of eliminated 'not' instruction:" << " Replacing with 'xor'.\n"; @@ -3704,7 +3704,7 @@ ; break;} case 212: -#line 2176 "/Users/sabre/llvm/lib/AsmParser/llvmAsmParser.y" +#line 2176 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { if (yyvsp[0].ValueVal->getType() != Type::UByteTy) ThrowException("Shift amount must be ubyte!"); @@ -3714,7 +3714,7 @@ ; break;} case 213: -#line 2183 "/Users/sabre/llvm/lib/AsmParser/llvmAsmParser.y" +#line 2183 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { if (!yyvsp[0].TypeVal->get()->isFirstClassType()) ThrowException("cast instruction to a non-primitive type: '" + @@ -3724,7 +3724,7 @@ ; break;} case 214: -#line 2190 "/Users/sabre/llvm/lib/AsmParser/llvmAsmParser.y" +#line 2190 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { if (yyvsp[-4].ValueVal->getType() != Type::BoolTy) ThrowException("select condition must be boolean!"); @@ -3734,7 +3734,7 @@ ; break;} case 215: -#line 2197 "/Users/sabre/llvm/lib/AsmParser/llvmAsmParser.y" +#line 2197 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { NewVarArgs = true; yyval.InstVal = new VAArgInst(yyvsp[-2].ValueVal, *yyvsp[0].TypeVal); @@ -3742,7 +3742,7 @@ ; break;} case 216: -#line 2202 "/Users/sabre/llvm/lib/AsmParser/llvmAsmParser.y" +#line 2202 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { ObsoleteVarArgs = true; const Type* ArgTy = yyvsp[-2].ValueVal->getType(); @@ -3764,7 +3764,7 @@ ; break;} case 217: -#line 2221 "/Users/sabre/llvm/lib/AsmParser/llvmAsmParser.y" +#line 2221 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { ObsoleteVarArgs = true; const Type* ArgTy = yyvsp[-2].ValueVal->getType(); @@ -3789,7 +3789,7 @@ ; break;} case 218: -#line 2243 "/Users/sabre/llvm/lib/AsmParser/llvmAsmParser.y" +#line 2243 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { if (!isa(yyvsp[-2].ValueVal->getType())) ThrowException("First operand of extractelement must be " @@ -3800,7 +3800,7 @@ ; break;} case 219: -#line 2251 "/Users/sabre/llvm/lib/AsmParser/llvmAsmParser.y" +#line 2251 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { if (!isa(yyvsp[-4].ValueVal->getType())) ThrowException("First operand of insertelement must be " @@ -3815,7 +3815,15 @@ ; break;} case 220: -#line 2263 "/Users/sabre/llvm/lib/AsmParser/llvmAsmParser.y" +#line 2263 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +{ + if (!ShuffleVectorInst::isValidOperands(yyvsp[-4].ValueVal, yyvsp[-2].ValueVal, yyvsp[0].ValueVal)) + ThrowException("Invalid shufflevector operands!"); + yyval.InstVal = new ShuffleVectorInst(yyvsp[-4].ValueVal, yyvsp[-2].ValueVal, yyvsp[0].ValueVal); + ; + break;} +case 221: +#line 2268 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { const Type *Ty = yyvsp[0].PHIList->front().first->getType(); if (!Ty->isFirstClassType()) @@ -3831,8 +3839,8 @@ delete yyvsp[0].PHIList; // Free the list... ; break;} -case 221: -#line 2277 "/Users/sabre/llvm/lib/AsmParser/llvmAsmParser.y" +case 222: +#line 2282 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { const PointerType *PFTy; const FunctionType *Ty; @@ -3891,66 +3899,66 @@ delete yyvsp[-1].ValueList; ; break;} -case 222: -#line 2334 "/Users/sabre/llvm/lib/AsmParser/llvmAsmParser.y" +case 223: +#line 2339 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { yyval.InstVal = yyvsp[0].InstVal; ; break;} -case 223: -#line 2340 "/Users/sabre/llvm/lib/AsmParser/llvmAsmParser.y" +case 224: +#line 2345 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { yyval.ValueList = yyvsp[0].ValueList; ; break;} -case 224: -#line 2342 "/Users/sabre/llvm/lib/AsmParser/llvmAsmParser.y" +case 225: +#line 2347 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { yyval.ValueList = new std::vector(); ; break;} -case 225: -#line 2346 "/Users/sabre/llvm/lib/AsmParser/llvmAsmParser.y" +case 226: +#line 2351 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { yyval.BoolVal = true; ; break;} -case 226: -#line 2349 "/Users/sabre/llvm/lib/AsmParser/llvmAsmParser.y" +case 227: +#line 2354 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { yyval.BoolVal = false; ; break;} -case 227: -#line 2355 "/Users/sabre/llvm/lib/AsmParser/llvmAsmParser.y" +case 228: +#line 2360 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { yyval.InstVal = new MallocInst(*yyvsp[-1].TypeVal, 0, yyvsp[0].UIntVal); delete yyvsp[-1].TypeVal; ; break;} -case 228: -#line 2359 "/Users/sabre/llvm/lib/AsmParser/llvmAsmParser.y" +case 229: +#line 2364 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { yyval.InstVal = new MallocInst(*yyvsp[-4].TypeVal, getVal(yyvsp[-2].PrimType, yyvsp[-1].ValIDVal), yyvsp[0].UIntVal); delete yyvsp[-4].TypeVal; ; break;} -case 229: -#line 2363 "/Users/sabre/llvm/lib/AsmParser/llvmAsmParser.y" +case 230: +#line 2368 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { yyval.InstVal = new AllocaInst(*yyvsp[-1].TypeVal, 0, yyvsp[0].UIntVal); delete yyvsp[-1].TypeVal; ; break;} -case 230: -#line 2367 "/Users/sabre/llvm/lib/AsmParser/llvmAsmParser.y" +case 231: +#line 2372 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { yyval.InstVal = new AllocaInst(*yyvsp[-4].TypeVal, getVal(yyvsp[-2].PrimType, yyvsp[-1].ValIDVal), yyvsp[0].UIntVal); delete yyvsp[-4].TypeVal; ; break;} -case 231: -#line 2371 "/Users/sabre/llvm/lib/AsmParser/llvmAsmParser.y" +case 232: +#line 2376 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { if (!isa(yyvsp[0].ValueVal->getType())) ThrowException("Trying to free nonpointer type " + @@ -3958,8 +3966,8 @@ yyval.InstVal = new FreeInst(yyvsp[0].ValueVal); ; break;} -case 232: -#line 2378 "/Users/sabre/llvm/lib/AsmParser/llvmAsmParser.y" +case 233: +#line 2383 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { if (!isa(yyvsp[-1].TypeVal->get())) ThrowException("Can't load from nonpointer type: " + @@ -3971,8 +3979,8 @@ delete yyvsp[-1].TypeVal; ; break;} -case 233: -#line 2388 "/Users/sabre/llvm/lib/AsmParser/llvmAsmParser.y" +case 234: +#line 2393 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { const PointerType *PT = dyn_cast(yyvsp[-1].TypeVal->get()); if (!PT) @@ -3987,8 +3995,8 @@ delete yyvsp[-1].TypeVal; ; break;} -case 234: -#line 2401 "/Users/sabre/llvm/lib/AsmParser/llvmAsmParser.y" +case 235: +#line 2406 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { if (!isa(yyvsp[-2].TypeVal->get())) ThrowException("getelementptr insn requires pointer operand!"); @@ -4233,7 +4241,7 @@ } return 1; } -#line 2424 "/Users/sabre/llvm/lib/AsmParser/llvmAsmParser.y" +#line 2429 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" int yyerror(const char *ErrorMsg) { std::string where Index: llvm/lib/AsmParser/llvmAsmParser.h.cvs diff -u llvm/lib/AsmParser/llvmAsmParser.h.cvs:1.1 llvm/lib/AsmParser/llvmAsmParser.h.cvs:1.2 --- llvm/lib/AsmParser/llvmAsmParser.h.cvs:1.1 Wed Feb 15 01:22:58 2006 +++ llvm/lib/AsmParser/llvmAsmParser.h.cvs Fri Apr 7 20:18:56 2006 @@ -133,8 +133,9 @@ #define VAARG 350 #define EXTRACTELEMENT 351 #define INSERTELEMENT 352 -#define VAARG_old 353 -#define VANEXT_old 354 +#define SHUFFLEVECTOR 353 +#define VAARG_old 354 +#define VANEXT_old 355 extern YYSTYPE llvmAsmlval; Index: llvm/lib/AsmParser/llvmAsmParser.y.cvs diff -u llvm/lib/AsmParser/llvmAsmParser.y.cvs:1.2 llvm/lib/AsmParser/llvmAsmParser.y.cvs:1.3 --- llvm/lib/AsmParser/llvmAsmParser.y.cvs:1.2 Sat Mar 4 01:53:41 2006 +++ llvm/lib/AsmParser/llvmAsmParser.y.cvs Fri Apr 7 20:18:56 2006 @@ -107,8 +107,8 @@ } // Look for intrinsic functions and CallInst that need to be upgraded - for (Module::iterator FI = CurrentModule->begin(),FE = CurrentModule->end(); - FI != FE; ) + for (Module::iterator FI = CurrentModule->begin(), + FE = CurrentModule->end(); FI != FE; ) UpgradeCallsToIntrinsic(FI++); Values.clear(); // Clear out function local definitions @@ -998,7 +998,7 @@ // Other Operators %type ShiftOps %token PHI_TOK CAST SELECT SHL SHR VAARG -%token EXTRACTELEMENT INSERTELEMENT +%token EXTRACTELEMENT INSERTELEMENT SHUFFLEVECTOR %token VAARG_old VANEXT_old //OBSOLETE @@ -2260,6 +2260,11 @@ ThrowException("Third operand of insertelement must be uint!"); $$ = new InsertElementInst($2, $4, $6); } + | SHUFFLEVECTOR ResolvedVal ',' ResolvedVal ',' ResolvedVal { + if (!ShuffleVectorInst::isValidOperands($2, $4, $6)) + ThrowException("Invalid shufflevector operands!"); + $$ = new ShuffleVectorInst($2, $4, $6); + } | PHI_TOK PHIList { const Type *Ty = $2->front().first->getType(); if (!Ty->isFirstClassType()) From lattner at cs.uiuc.edu Fri Apr 7 20:19:27 2006 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Fri, 7 Apr 2006 20:19:27 -0500 Subject: [llvm-commits] CVS: llvm/lib/Transforms/Scalar/SCCP.cpp Message-ID: <200604080119.UAA19752@zion.cs.uiuc.edu> Changes in directory llvm/lib/Transforms/Scalar: SCCP.cpp updated: 1.129 -> 1.130 --- Log message: Add supprot for shufflevector --- Diffs of the changes: (+25 -0) SCCP.cpp | 25 +++++++++++++++++++++++++ 1 files changed, 25 insertions(+) Index: llvm/lib/Transforms/Scalar/SCCP.cpp diff -u llvm/lib/Transforms/Scalar/SCCP.cpp:1.129 llvm/lib/Transforms/Scalar/SCCP.cpp:1.130 --- llvm/lib/Transforms/Scalar/SCCP.cpp:1.129 Tue Feb 7 20:38:11 2006 +++ llvm/lib/Transforms/Scalar/SCCP.cpp Fri Apr 7 20:19:12 2006 @@ -330,6 +330,7 @@ void visitShiftInst(ShiftInst &I) { visitBinaryOperator(I); } void visitExtractElementInst(ExtractElementInst &I); void visitInsertElementInst(InsertElementInst &I); + void visitShuffleVectorInst(ShuffleVectorInst &I); // Instructions that cannot be folded away... void visitStoreInst (Instruction &I); @@ -782,6 +783,30 @@ IdxState.getConstant())); } +void SCCPSolver::visitShuffleVectorInst(ShuffleVectorInst &I) { + LatticeVal &V1State = getValueState(I.getOperand(0)); + LatticeVal &V2State = getValueState(I.getOperand(1)); + LatticeVal &MaskState = getValueState(I.getOperand(2)); + + if (MaskState.isUndefined() || + (V1State.isUndefined() && V2State.isUndefined())) + return; // Undefined output if mask or both inputs undefined. + + if (V1State.isOverdefined() || V2State.isOverdefined() || + MaskState.isOverdefined()) { + markOverdefined(&I); + } else { + // A mix of constant/undef inputs. + Constant *V1 = V1State.isConstant() ? + V1State.getConstant() : UndefValue::get(I.getType()); + Constant *V2 = V2State.isConstant() ? + V2State.getConstant() : UndefValue::get(I.getType()); + Constant *Mask = MaskState.isConstant() ? + MaskState.getConstant() : UndefValue::get(I.getOperand(2)->getType()); + markConstant(&I, ConstantExpr::getShuffleVector(V1, V2, Mask)); + } +} + // Handle getelementptr instructions... if all operands are constants then we // can turn this into a getelementptr ConstantExpr. // From lattner at cs.uiuc.edu Fri Apr 7 20:19:27 2006 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Fri, 7 Apr 2006 20:19:27 -0500 Subject: [llvm-commits] CVS: llvm/lib/Transforms/Utils/Local.cpp ValueMapper.cpp Message-ID: <200604080119.UAA19758@zion.cs.uiuc.edu> Changes in directory llvm/lib/Transforms/Utils: Local.cpp updated: 1.54 -> 1.55 ValueMapper.cpp updated: 1.24 -> 1.25 --- Log message: Add supprot for shufflevector --- Diffs of the changes: (+10 -0) Local.cpp | 5 +++++ ValueMapper.cpp | 5 +++++ 2 files changed, 10 insertions(+) Index: llvm/lib/Transforms/Utils/Local.cpp diff -u llvm/lib/Transforms/Utils/Local.cpp:1.54 llvm/lib/Transforms/Utils/Local.cpp:1.55 --- llvm/lib/Transforms/Utils/Local.cpp:1.54 Sat Apr 1 21:35:01 2006 +++ llvm/lib/Transforms/Utils/Local.cpp Fri Apr 7 20:19:12 2006 @@ -107,6 +107,11 @@ case Instruction::InsertElement: if (Constant *Op2 = dyn_cast(I->getOperand(2))) return ConstantExpr::getInsertElement(Op0, Op1, Op2); + return 0; + case Instruction::ShuffleVector: + if (Constant *Op2 = dyn_cast(I->getOperand(2))) + return ConstantExpr::getShuffleVector(Op0, Op1, Op2); + return 0; case Instruction::GetElementPtr: std::vector IdxList; IdxList.reserve(I->getNumOperands()-1); Index: llvm/lib/Transforms/Utils/ValueMapper.cpp diff -u llvm/lib/Transforms/Utils/ValueMapper.cpp:1.24 llvm/lib/Transforms/Utils/ValueMapper.cpp:1.25 --- llvm/lib/Transforms/Utils/ValueMapper.cpp:1.24 Thu Apr 6 23:41:03 2006 +++ llvm/lib/Transforms/Utils/ValueMapper.cpp Fri Apr 7 20:19:12 2006 @@ -94,6 +94,11 @@ Constant *MV1 = cast(MapValue(CE->getOperand(0), VM)); Constant *MV2 = cast(MapValue(CE->getOperand(1), VM)); return VMSlot = ConstantExpr::getExtractElement(MV1, MV2); + } else if (CE->getOpcode() == Instruction::ShuffleVector) { + Constant *MV1 = cast(MapValue(CE->getOperand(0), VM)); + Constant *MV2 = cast(MapValue(CE->getOperand(1), VM)); + Constant *MV3 = cast(CE->getOperand(2)); + return VMSlot = ConstantExpr::getShuffleVector(MV1, MV2, MV3); } else { assert(CE->getNumOperands() == 2 && "Must be binary operator?"); Constant *MV1 = cast(MapValue(CE->getOperand(0), VM)); From lattner at cs.uiuc.edu Fri Apr 7 20:19:37 2006 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Fri, 7 Apr 2006 20:19:37 -0500 Subject: [llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp Message-ID: <200604080119.UAA19789@zion.cs.uiuc.edu> Changes in directory llvm/lib/CodeGen/SelectionDAG: SelectionDAGISel.cpp updated: 1.218 -> 1.219 --- Log message: Stub out shufflevector --- Diffs of the changes: (+1 -0) SelectionDAGISel.cpp | 1 + 1 files changed, 1 insertion(+) Index: llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp diff -u llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.218 llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.219 --- llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.218 Wed Apr 5 01:54:42 2006 +++ llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp Fri Apr 7 20:19:25 2006 @@ -516,6 +516,7 @@ void visitExtractElement(User &I); void visitInsertElement(User &I); + void visitShuffleVector(User &I) { assert(0 && "ShuffleVector not impl!"); } void visitGetElementPtr(User &I); void visitCast(User &I); From lattner at cs.uiuc.edu Fri Apr 7 20:19:59 2006 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Fri, 7 Apr 2006 20:19:59 -0500 Subject: [llvm-commits] CVS: llvm/lib/Linker/LinkModules.cpp Message-ID: <200604080119.UAA19823@zion.cs.uiuc.edu> Changes in directory llvm/lib/Linker: LinkModules.cpp updated: 1.112 -> 1.113 --- Log message: Add shufflevector support --- Diffs of the changes: (+6 -0) LinkModules.cpp | 6 ++++++ 1 files changed, 6 insertions(+) Index: llvm/lib/Linker/LinkModules.cpp diff -u llvm/lib/Linker/LinkModules.cpp:1.112 llvm/lib/Linker/LinkModules.cpp:1.113 --- llvm/lib/Linker/LinkModules.cpp:1.112 Thu Apr 6 20:27:42 2006 +++ llvm/lib/Linker/LinkModules.cpp Fri Apr 7 20:19:47 2006 @@ -317,6 +317,12 @@ Result = ConstantExpr::getInsertElement(cast(Ptr), cast(Elt), cast(Idx)); + } else if (CE->getOpcode() == Instruction::ShuffleVector) { + Value *V1 = RemapOperand(CE->getOperand(0), ValueMap); + Value *V2 = RemapOperand(CE->getOperand(1), ValueMap); + Result = ConstantExpr::getShuffleVector(cast(V1), + cast(V2), + cast(CE->getOperand(2))); } else if (CE->getNumOperands() == 1) { // Cast instruction assert(CE->getOpcode() == Instruction::Cast); From reid at x10sys.com Fri Apr 7 20:41:39 2006 From: reid at x10sys.com (Reid Spencer) Date: Fri, 7 Apr 2006 20:41:39 -0500 Subject: [llvm-commits] CVS: llvm/configure Message-ID: <200604080141.UAA19921@zion.cs.uiuc.edu> Changes in directory llvm: configure updated: 1.217 -> 1.218 --- Log message: Ensure that the automatic "CVS build" detection works for both objdir == srcdir and objdir != srcdir. --- Diffs of the changes: (+1 -1) configure | 2 +- 1 files changed, 1 insertion(+), 1 deletion(-) Index: llvm/configure diff -u llvm/configure:1.217 llvm/configure:1.218 --- llvm/configure:1.217 Fri Apr 7 11:01:51 2006 +++ llvm/configure Fri Apr 7 20:41:26 2006 @@ -2968,7 +2968,7 @@ esac -if test -d "CVS" ; then +if test -d "CVS" -o -d "${srcdir}/CVS"; then cvsbuild="yes" optimize="no" asserts="yes" From reid at x10sys.com Fri Apr 7 20:41:39 2006 From: reid at x10sys.com (Reid Spencer) Date: Fri, 7 Apr 2006 20:41:39 -0500 Subject: [llvm-commits] CVS: llvm/autoconf/configure.ac Message-ID: <200604080141.UAA19925@zion.cs.uiuc.edu> Changes in directory llvm/autoconf: configure.ac updated: 1.215 -> 1.216 --- Log message: Ensure that the automatic "CVS build" detection works for both objdir == srcdir and objdir != srcdir. --- Diffs of the changes: (+1 -1) configure.ac | 2 +- 1 files changed, 1 insertion(+), 1 deletion(-) Index: llvm/autoconf/configure.ac diff -u llvm/autoconf/configure.ac:1.215 llvm/autoconf/configure.ac:1.216 --- llvm/autoconf/configure.ac:1.215 Fri Apr 7 11:01:51 2006 +++ llvm/autoconf/configure.ac Fri Apr 7 20:41:26 2006 @@ -190,7 +190,7 @@ dnl debug with assertions turned on. Without, we assume a source release and we dnl get an optimized build without assertions. See --enable-optimized and dnl --enable-assertions below -if test -d "CVS" ; then +if test -d "CVS" -o -d "${srcdir}/CVS"; then cvsbuild="yes" optimize="no" asserts="yes" From evan.cheng at apple.com Fri Apr 7 20:46:50 2006 From: evan.cheng at apple.com (Evan Cheng) Date: Fri, 7 Apr 2006 20:46:50 -0500 Subject: [llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp Message-ID: <200604080146.UAA19948@zion.cs.uiuc.edu> Changes in directory llvm/lib/CodeGen/SelectionDAG: LegalizeDAG.cpp updated: 1.353 -> 1.354 --- Log message: INSERT_VECTOR_ELT lowering bug: store vector to $esp store element to $esp + sizeof(VT) * index load vector from $esp The bug is VT is the type of the vector element, not the type of the vector! --- Diffs of the changes: (+11 -14) LegalizeDAG.cpp | 25 +++++++++++-------------- 1 files changed, 11 insertions(+), 14 deletions(-) Index: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp diff -u llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.353 llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.354 --- llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.353 Wed Apr 5 01:07:11 2006 +++ llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp Fri Apr 7 20:46:37 2006 @@ -867,30 +867,27 @@ // with a "move to register" or "extload into register" instruction, then // permute it into place, if the idx is a constant and if the idx is // supported by the target. - SDOperand StackPtr = CreateStackTemporary(Tmp1.getValueType()); + MVT::ValueType VT = Tmp1.getValueType(); + MVT::ValueType EltVT = Tmp2.getValueType(); + MVT::ValueType IdxVT = Tmp3.getValueType(); + MVT::ValueType PtrVT = TLI.getPointerTy(); + SDOperand StackPtr = CreateStackTemporary(VT); // Store the vector. SDOperand Ch = DAG.getNode(ISD::STORE, MVT::Other, DAG.getEntryNode(), Tmp1, StackPtr, DAG.getSrcValue(NULL)); // Truncate or zero extend offset to target pointer type. - MVT::ValueType IntPtr = TLI.getPointerTy(); - if (Tmp3.getValueType() > IntPtr) - Tmp3 = DAG.getNode(ISD::TRUNCATE, IntPtr, Tmp3); - else - Tmp3 = DAG.getNode(ISD::ZERO_EXTEND, IntPtr, Tmp3); - + unsigned CastOpc = (IdxVT > PtrVT) ? ISD::TRUNCATE : ISD::ZERO_EXTEND; + Tmp3 = DAG.getNode(CastOpc, PtrVT, Tmp3); // Add the offset to the index. - unsigned EltSize = MVT::getSizeInBits(Result.getValueType())/8; - Tmp3 = DAG.getNode(ISD::MUL, Tmp3.getValueType(), Tmp3, - DAG.getConstant(EltSize, Tmp3.getValueType())); - SDOperand StackPtr2 = - DAG.getNode(ISD::ADD, Tmp3.getValueType(), Tmp3, StackPtr); + unsigned EltSize = MVT::getSizeInBits(EltVT)/8; + Tmp3 = DAG.getNode(ISD::MUL, IdxVT, Tmp3,DAG.getConstant(EltSize, IdxVT)); + SDOperand StackPtr2 = DAG.getNode(ISD::ADD, IdxVT, Tmp3, StackPtr); // Store the scalar value. Ch = DAG.getNode(ISD::STORE, MVT::Other, Ch, Tmp2, StackPtr2, DAG.getSrcValue(NULL)); // Load the updated vector. - Result = DAG.getLoad(Result.getValueType(), Ch, StackPtr, - DAG.getSrcValue(NULL)); + Result = DAG.getLoad(VT, Ch, StackPtr, DAG.getSrcValue(NULL)); break; } } From reid at x10sys.com Fri Apr 7 20:57:23 2006 From: reid at x10sys.com (Reid Spencer) Date: Fri, 7 Apr 2006 20:57:23 -0500 Subject: [llvm-commits] CVS: llvm/Makefile Message-ID: <200604080157.UAA20007@zion.cs.uiuc.edu> Changes in directory llvm: Makefile updated: 1.55 -> 1.56 --- Log message: Don't build projects/examples if libs-only was specified. --- Diffs of the changes: (+1 -1) Makefile | 2 +- 1 files changed, 1 insertion(+), 1 deletion(-) Index: llvm/Makefile diff -u llvm/Makefile:1.55 llvm/Makefile:1.56 --- llvm/Makefile:1.55 Fri Apr 7 16:45:23 2006 +++ llvm/Makefile Fri Apr 7 20:57:10 2006 @@ -22,8 +22,8 @@ $(warning Skipping runtime libraries, llvm-gcc 4 detected.) endif DIRS += docs + OPTIONAL_DIRS = examples projects endif - OPTIONAL_DIRS = examples projects endif EXTRA_DIST := test llvm.spec include From reid at x10sys.com Fri Apr 7 21:14:49 2006 From: reid at x10sys.com (Reid Spencer) Date: Fri, 7 Apr 2006 21:14:49 -0500 Subject: [llvm-commits] CVS: llvm/Makefile Message-ID: <200604080214.VAA20098@zion.cs.uiuc.edu> Changes in directory llvm: Makefile updated: 1.56 -> 1.57 --- Log message: Fix recursion: 1. Make setting OPTIONAL_DIRS use immediate assignment 2. Include Makefile.config before ifeq tests and then Makefile.rules later instead of Makefile.common up front. This ensures that the variable values are set before the ifeq statements in Makefile.rules are evaluated. With this, recursion into projects/examples is corrected. --- Diffs of the changes: (+4 -2) Makefile | 6 ++++-- 1 files changed, 4 insertions(+), 2 deletions(-) Index: llvm/Makefile diff -u llvm/Makefile:1.56 llvm/Makefile:1.57 --- llvm/Makefile:1.56 Fri Apr 7 20:57:10 2006 +++ llvm/Makefile Fri Apr 7 21:14:37 2006 @@ -9,7 +9,7 @@ LEVEL = . DIRS = lib/System lib/Support utils lib -include $(LEVEL)/Makefile.common +include $(LEVEL)/Makefile.config ifeq ($(MAKECMDGOALS),tools-only) DIRS += tools @@ -21,12 +21,14 @@ else $(warning Skipping runtime libraries, llvm-gcc 4 detected.) endif + OPTIONAL_DIRS := examples projects DIRS += docs - OPTIONAL_DIRS = examples projects endif endif EXTRA_DIST := test llvm.spec include +include $(LLVM_SRC_ROOT)/Makefile.rules + # Specify options to pass to configure script when we're # running the dist-check target DIST_CHECK_CONFIG_OPTIONS = --with-llvmgccdir=$(LLVMGCCDIR) From lattner at cs.uiuc.edu Fri Apr 7 22:53:47 2006 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Fri, 7 Apr 2006 22:53:47 -0500 Subject: [llvm-commits] CVS: llvm/lib/AsmParser/llvmAsmParser.y Message-ID: <200604080353.WAA20415@zion.cs.uiuc.edu> Changes in directory llvm/lib/AsmParser: llvmAsmParser.y updated: 1.251 -> 1.252 --- Log message: Add insertelement and shufflevector constantexpr support --- Diffs of the changes: (+9 -0) llvmAsmParser.y | 9 +++++++++ 1 files changed, 9 insertions(+) Index: llvm/lib/AsmParser/llvmAsmParser.y diff -u llvm/lib/AsmParser/llvmAsmParser.y:1.251 llvm/lib/AsmParser/llvmAsmParser.y:1.252 --- llvm/lib/AsmParser/llvmAsmParser.y:1.251 Fri Apr 7 20:18:35 2006 +++ llvm/lib/AsmParser/llvmAsmParser.y Fri Apr 7 22:53:34 2006 @@ -1547,8 +1547,17 @@ if ($5->getType() != Type::UIntTy) ThrowException("Second operand of extractelement must be uint!"); $$ = ConstantExpr::getExtractElement($3, $5); + } + | INSERTELEMENT '(' ConstVal ',' ConstVal ',' ConstVal ')' { + $$ = ConstantExpr::getInsertElement($3, $5, $7); + } + | SHUFFLEVECTOR '(' ConstVal ',' ConstVal ',' ConstVal ')' { + if (!ShuffleVectorInst::isValidOperands($3, $5, $7)) + ThrowException("Invalid shufflevector operands!"); + $$ = ConstantExpr::getShuffleVector($3, $5, $7); }; + // ConstVector - A list of comma separated constants. ConstVector : ConstVector ',' ConstVal { ($$ = $1)->push_back($3); From lattner at cs.uiuc.edu Fri Apr 7 22:55:29 2006 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Fri, 7 Apr 2006 22:55:29 -0500 Subject: [llvm-commits] CVS: llvm/lib/AsmParser/llvmAsmParser.cpp.cvs llvmAsmParser.y.cvs Message-ID: <200604080355.WAA20459@zion.cs.uiuc.edu> Changes in directory llvm/lib/AsmParser: llvmAsmParser.cpp.cvs updated: 1.3 -> 1.4 llvmAsmParser.y.cvs updated: 1.3 -> 1.4 --- Log message: regenerate --- Diffs of the changes: (+778 -731) llvmAsmParser.cpp.cvs | 1474 ++++++++++++++++++++++++++------------------------ llvmAsmParser.y.cvs | 13 2 files changed, 778 insertions(+), 709 deletions(-) Index: llvm/lib/AsmParser/llvmAsmParser.cpp.cvs diff -u llvm/lib/AsmParser/llvmAsmParser.cpp.cvs:1.3 llvm/lib/AsmParser/llvmAsmParser.cpp.cvs:1.4 --- llvm/lib/AsmParser/llvmAsmParser.cpp.cvs:1.3 Fri Apr 7 20:18:56 2006 +++ llvm/lib/AsmParser/llvmAsmParser.cpp.cvs Fri Apr 7 22:55:17 2006 @@ -1,5 +1,5 @@ -/* A Bison parser, made from /Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y +/* A Bison parser, made from /Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y by GNU Bison version 1.28 */ #define YYBISON 1 /* Identify Bison output. */ @@ -111,7 +111,7 @@ #define VAARG_old 354 #define VANEXT_old 355 -#line 14 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +#line 14 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" #include "ParserInternals.h" #include "llvm/CallingConv.h" @@ -987,7 +987,7 @@ } -#line 890 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +#line 890 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" typedef union { llvm::Module *ModuleVal; llvm::Function *FunctionVal; @@ -1037,7 +1037,7 @@ -#define YYFINAL 479 +#define YYFINAL 495 #define YYFLAG -32768 #define YYNTBASE 116 @@ -1095,19 +1095,19 @@ 174, 178, 181, 184, 186, 190, 192, 196, 198, 199, 204, 208, 212, 217, 222, 226, 229, 232, 235, 238, 241, 244, 247, 250, 253, 256, 263, 269, 278, 285, - 292, 299, 306, 313, 317, 319, 321, 323, 325, 328, - 331, 336, 339, 341, 346, 349, 354, 355, 363, 364, - 372, 376, 381, 382, 384, 386, 388, 392, 396, 400, - 404, 408, 410, 411, 413, 415, 417, 418, 421, 425, - 427, 429, 433, 435, 436, 445, 447, 449, 453, 455, - 457, 460, 461, 465, 466, 468, 470, 472, 474, 476, - 478, 480, 482, 484, 488, 490, 496, 498, 500, 502, - 504, 507, 510, 513, 517, 520, 521, 523, 526, 529, - 533, 543, 553, 562, 576, 578, 580, 587, 593, 596, - 603, 611, 613, 617, 619, 620, 623, 625, 631, 637, - 643, 646, 651, 656, 663, 668, 673, 678, 683, 690, - 697, 700, 708, 710, 713, 714, 716, 717, 721, 728, - 732, 739, 742, 747, 754 + 292, 299, 306, 313, 322, 331, 335, 337, 339, 341, + 343, 346, 349, 354, 357, 359, 364, 367, 372, 373, + 381, 382, 390, 394, 399, 400, 402, 404, 406, 410, + 414, 418, 422, 426, 428, 429, 431, 433, 435, 436, + 439, 443, 445, 447, 451, 453, 454, 463, 465, 467, + 471, 473, 475, 478, 479, 483, 484, 486, 488, 490, + 492, 494, 496, 498, 500, 502, 506, 508, 514, 516, + 518, 520, 522, 525, 528, 531, 535, 538, 539, 541, + 544, 547, 551, 561, 571, 580, 594, 596, 598, 605, + 611, 614, 621, 629, 631, 635, 637, 638, 641, 643, + 649, 655, 661, 664, 669, 674, 681, 686, 691, 696, + 701, 708, 715, 718, 726, 728, 731, 732, 734, 735, + 739, 746, 750, 757, 760, 765, 772 }; static const short yyrhs[] = { 5, @@ -1142,51 +1142,53 @@ 103, 142, 106, 0, 119, 105, 142, 103, 142, 106, 0, 120, 105, 142, 103, 142, 106, 0, 121, 105, 142, 103, 142, 106, 0, 97, 105, 142, 103, 142, - 106, 0, 144, 103, 142, 0, 142, 0, 32, 0, - 33, 0, 147, 0, 147, 165, 0, 147, 166, 0, - 147, 59, 58, 151, 0, 147, 25, 0, 148, 0, - 148, 126, 20, 135, 0, 148, 166, 0, 148, 59, - 58, 151, 0, 0, 148, 126, 127, 145, 142, 149, - 133, 0, 0, 148, 126, 47, 145, 137, 150, 133, - 0, 148, 48, 153, 0, 148, 55, 102, 154, 0, - 0, 24, 0, 53, 0, 52, 0, 50, 102, 152, - 0, 51, 102, 4, 0, 49, 102, 24, 0, 107, - 155, 109, 0, 155, 103, 24, 0, 24, 0, 0, - 22, 0, 24, 0, 156, 0, 0, 137, 157, 0, - 159, 103, 158, 0, 158, 0, 159, 0, 159, 103, - 37, 0, 37, 0, 0, 128, 135, 156, 105, 160, - 106, 132, 129, 0, 29, 0, 112, 0, 127, 161, - 162, 0, 30, 0, 113, 0, 173, 164, 0, 0, - 31, 167, 161, 0, 0, 60, 0, 3, 0, 4, - 0, 7, 0, 27, 0, 28, 0, 38, 0, 39, - 0, 26, 0, 110, 144, 111, 0, 143, 0, 58, - 168, 24, 103, 24, 0, 116, 0, 156, 0, 170, - 0, 169, 0, 137, 171, 0, 173, 174, 0, 163, - 174, 0, 175, 126, 176, 0, 175, 178, 0, 0, - 23, 0, 65, 172, 0, 65, 8, 0, 66, 21, - 171, 0, 66, 9, 171, 103, 21, 171, 103, 21, - 171, 0, 67, 124, 171, 103, 21, 171, 107, 177, - 109, 0, 67, 124, 171, 103, 21, 171, 107, 109, - 0, 68, 128, 135, 171, 105, 181, 106, 36, 21, - 171, 69, 21, 171, 0, 69, 0, 70, 0, 177, - 124, 169, 103, 21, 171, 0, 124, 169, 103, 21, - 171, 0, 126, 183, 0, 137, 107, 171, 103, 171, - 109, 0, 179, 103, 107, 171, 103, 171, 109, 0, - 172, 0, 180, 103, 172, 0, 180, 0, 0, 57, - 56, 0, 56, 0, 118, 137, 171, 103, 171, 0, - 119, 137, 171, 103, 171, 0, 120, 137, 171, 103, - 171, 0, 46, 172, 0, 121, 172, 103, 172, 0, - 92, 172, 36, 137, 0, 93, 172, 103, 172, 103, - 172, 0, 96, 172, 103, 137, 0, 100, 172, 103, - 137, 0, 101, 172, 103, 137, 0, 97, 172, 103, - 172, 0, 98, 172, 103, 172, 103, 172, 0, 99, - 172, 103, 172, 103, 172, 0, 91, 179, 0, 182, - 128, 135, 171, 105, 181, 106, 0, 186, 0, 103, - 180, 0, 0, 35, 0, 0, 85, 137, 130, 0, - 85, 137, 103, 15, 171, 130, 0, 86, 137, 130, - 0, 86, 137, 103, 15, 171, 130, 0, 87, 172, - 0, 185, 88, 137, 171, 0, 185, 89, 172, 103, - 137, 171, 0, 90, 137, 171, 184, 0 + 106, 0, 98, 105, 142, 103, 142, 103, 142, 106, + 0, 99, 105, 142, 103, 142, 103, 142, 106, 0, + 144, 103, 142, 0, 142, 0, 32, 0, 33, 0, + 147, 0, 147, 165, 0, 147, 166, 0, 147, 59, + 58, 151, 0, 147, 25, 0, 148, 0, 148, 126, + 20, 135, 0, 148, 166, 0, 148, 59, 58, 151, + 0, 0, 148, 126, 127, 145, 142, 149, 133, 0, + 0, 148, 126, 47, 145, 137, 150, 133, 0, 148, + 48, 153, 0, 148, 55, 102, 154, 0, 0, 24, + 0, 53, 0, 52, 0, 50, 102, 152, 0, 51, + 102, 4, 0, 49, 102, 24, 0, 107, 155, 109, + 0, 155, 103, 24, 0, 24, 0, 0, 22, 0, + 24, 0, 156, 0, 0, 137, 157, 0, 159, 103, + 158, 0, 158, 0, 159, 0, 159, 103, 37, 0, + 37, 0, 0, 128, 135, 156, 105, 160, 106, 132, + 129, 0, 29, 0, 112, 0, 127, 161, 162, 0, + 30, 0, 113, 0, 173, 164, 0, 0, 31, 167, + 161, 0, 0, 60, 0, 3, 0, 4, 0, 7, + 0, 27, 0, 28, 0, 38, 0, 39, 0, 26, + 0, 110, 144, 111, 0, 143, 0, 58, 168, 24, + 103, 24, 0, 116, 0, 156, 0, 170, 0, 169, + 0, 137, 171, 0, 173, 174, 0, 163, 174, 0, + 175, 126, 176, 0, 175, 178, 0, 0, 23, 0, + 65, 172, 0, 65, 8, 0, 66, 21, 171, 0, + 66, 9, 171, 103, 21, 171, 103, 21, 171, 0, + 67, 124, 171, 103, 21, 171, 107, 177, 109, 0, + 67, 124, 171, 103, 21, 171, 107, 109, 0, 68, + 128, 135, 171, 105, 181, 106, 36, 21, 171, 69, + 21, 171, 0, 69, 0, 70, 0, 177, 124, 169, + 103, 21, 171, 0, 124, 169, 103, 21, 171, 0, + 126, 183, 0, 137, 107, 171, 103, 171, 109, 0, + 179, 103, 107, 171, 103, 171, 109, 0, 172, 0, + 180, 103, 172, 0, 180, 0, 0, 57, 56, 0, + 56, 0, 118, 137, 171, 103, 171, 0, 119, 137, + 171, 103, 171, 0, 120, 137, 171, 103, 171, 0, + 46, 172, 0, 121, 172, 103, 172, 0, 92, 172, + 36, 137, 0, 93, 172, 103, 172, 103, 172, 0, + 96, 172, 103, 137, 0, 100, 172, 103, 137, 0, + 101, 172, 103, 137, 0, 97, 172, 103, 172, 0, + 98, 172, 103, 172, 103, 172, 0, 99, 172, 103, + 172, 103, 172, 0, 91, 179, 0, 182, 128, 135, + 171, 105, 181, 106, 0, 186, 0, 103, 180, 0, + 0, 35, 0, 0, 85, 137, 130, 0, 85, 137, + 103, 15, 171, 130, 0, 86, 137, 130, 0, 86, + 137, 103, 15, 171, 130, 0, 87, 172, 0, 185, + 88, 137, 171, 0, 185, 89, 172, 103, 137, 171, + 0, 90, 137, 171, 184, 0 }; #endif @@ -1204,19 +1206,19 @@ 1173, 1182, 1185, 1193, 1197, 1202, 1203, 1206, 1209, 1219, 1244, 1257, 1286, 1311, 1331, 1343, 1352, 1356, 1415, 1421, 1429, 1434, 1439, 1442, 1445, 1452, 1462, 1493, 1500, 1521, - 1531, 1536, 1543, 1553, 1556, 1563, 1563, 1573, 1580, 1584, - 1587, 1590, 1593, 1606, 1626, 1628, 1630, 1633, 1636, 1640, - 1643, 1645, 1647, 1651, 1663, 1664, 1666, 1669, 1677, 1682, - 1684, 1688, 1692, 1700, 1700, 1701, 1701, 1703, 1709, 1714, - 1720, 1723, 1728, 1732, 1736, 1822, 1822, 1824, 1832, 1832, - 1834, 1838, 1838, 1847, 1850, 1854, 1857, 1860, 1863, 1866, - 1869, 1872, 1875, 1878, 1902, 1905, 1918, 1921, 1926, 1926, - 1932, 1936, 1939, 1947, 1956, 1960, 1970, 1981, 1984, 1987, - 1990, 1993, 2007, 2011, 2064, 2067, 2073, 2081, 2091, 2098, - 2103, 2110, 2114, 2120, 2120, 2122, 2125, 2131, 2143, 2154, - 2164, 2176, 2183, 2190, 2197, 2202, 2221, 2243, 2251, 2263, - 2268, 2282, 2339, 2345, 2347, 2351, 2354, 2360, 2364, 2368, - 2372, 2376, 2383, 2393, 2406 + 1531, 1536, 1543, 1551, 1554, 1562, 1565, 1572, 1572, 1582, + 1589, 1593, 1596, 1599, 1602, 1615, 1635, 1637, 1639, 1642, + 1645, 1649, 1652, 1654, 1656, 1660, 1672, 1673, 1675, 1678, + 1686, 1691, 1693, 1697, 1701, 1709, 1709, 1710, 1710, 1712, + 1718, 1723, 1729, 1732, 1737, 1741, 1745, 1831, 1831, 1833, + 1841, 1841, 1843, 1847, 1847, 1856, 1859, 1863, 1866, 1869, + 1872, 1875, 1878, 1881, 1884, 1887, 1911, 1914, 1927, 1930, + 1935, 1935, 1941, 1945, 1948, 1956, 1965, 1969, 1979, 1990, + 1993, 1996, 1999, 2002, 2016, 2020, 2073, 2076, 2082, 2090, + 2100, 2107, 2112, 2119, 2123, 2129, 2129, 2131, 2134, 2140, + 2152, 2163, 2173, 2185, 2192, 2199, 2206, 2211, 2230, 2252, + 2260, 2272, 2277, 2291, 2348, 2354, 2356, 2360, 2363, 2369, + 2373, 2377, 2381, 2385, 2392, 2402, 2415 }; #endif @@ -1263,19 +1265,19 @@ 139, 139, 139, 140, 140, 141, 141, 141, 141, 142, 142, 142, 142, 142, 142, 142, 142, 142, 142, 142, 142, 142, 142, 142, 142, 143, 143, 143, 143, 143, - 143, 143, 143, 144, 144, 145, 145, 146, 147, 147, - 147, 147, 147, 148, 148, 148, 149, 148, 150, 148, - 148, 148, 148, 151, 152, 152, 153, 153, 153, 154, - 155, 155, 155, 156, 156, 157, 157, 158, 159, 159, - 160, 160, 160, 160, 161, 162, 162, 163, 164, 164, - 165, 167, 166, 168, 168, 169, 169, 169, 169, 169, - 169, 169, 169, 169, 169, 169, 170, 170, 171, 171, - 172, 173, 173, 174, 175, 175, 175, 176, 176, 176, - 176, 176, 176, 176, 176, 176, 177, 177, 178, 179, - 179, 180, 180, 181, 181, 182, 182, 183, 183, 183, + 143, 143, 143, 143, 143, 144, 144, 145, 145, 146, + 147, 147, 147, 147, 147, 148, 148, 148, 149, 148, + 150, 148, 148, 148, 148, 151, 152, 152, 153, 153, + 153, 154, 155, 155, 155, 156, 156, 157, 157, 158, + 159, 159, 160, 160, 160, 160, 161, 162, 162, 163, + 164, 164, 165, 167, 166, 168, 168, 169, 169, 169, + 169, 169, 169, 169, 169, 169, 169, 169, 170, 170, + 171, 171, 172, 173, 173, 174, 175, 175, 175, 176, + 176, 176, 176, 176, 176, 176, 176, 176, 177, 177, + 178, 179, 179, 180, 180, 181, 181, 182, 182, 183, 183, 183, 183, 183, 183, 183, 183, 183, 183, 183, - 183, 183, 183, 184, 184, 185, 185, 186, 186, 186, - 186, 186, 186, 186, 186 + 183, 183, 183, 183, 183, 184, 184, 185, 185, 186, + 186, 186, 186, 186, 186, 186, 186 }; static const short yyr2[] = { 0, @@ -1290,397 +1292,419 @@ 3, 2, 2, 1, 3, 1, 3, 1, 0, 4, 3, 3, 4, 4, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 6, 5, 8, 6, 6, - 6, 6, 6, 3, 1, 1, 1, 1, 2, 2, - 4, 2, 1, 4, 2, 4, 0, 7, 0, 7, - 3, 4, 0, 1, 1, 1, 3, 3, 3, 3, - 3, 1, 0, 1, 1, 1, 0, 2, 3, 1, - 1, 3, 1, 0, 8, 1, 1, 3, 1, 1, - 2, 0, 3, 0, 1, 1, 1, 1, 1, 1, - 1, 1, 1, 3, 1, 5, 1, 1, 1, 1, - 2, 2, 2, 3, 2, 0, 1, 2, 2, 3, - 9, 9, 8, 13, 1, 1, 6, 5, 2, 6, - 7, 1, 3, 1, 0, 2, 1, 5, 5, 5, - 2, 4, 4, 6, 4, 4, 4, 4, 6, 6, - 2, 7, 1, 2, 0, 1, 0, 3, 6, 3, - 6, 2, 4, 6, 4 + 6, 6, 6, 8, 8, 3, 1, 1, 1, 1, + 2, 2, 4, 2, 1, 4, 2, 4, 0, 7, + 0, 7, 3, 4, 0, 1, 1, 1, 3, 3, + 3, 3, 3, 1, 0, 1, 1, 1, 0, 2, + 3, 1, 1, 3, 1, 0, 8, 1, 1, 3, + 1, 1, 2, 0, 3, 0, 1, 1, 1, 1, + 1, 1, 1, 1, 1, 3, 1, 5, 1, 1, + 1, 1, 2, 2, 2, 3, 2, 0, 1, 2, + 2, 3, 9, 9, 8, 13, 1, 1, 6, 5, + 2, 6, 7, 1, 3, 1, 0, 2, 1, 5, + 5, 5, 2, 4, 4, 6, 4, 4, 4, 4, + 6, 6, 2, 7, 1, 2, 0, 1, 0, 3, + 6, 3, 6, 2, 4, 6, 4 }; -static const short yydefact[] = { 133, - 39, 123, 122, 162, 35, 36, 37, 38, 0, 40, - 186, 119, 120, 186, 144, 145, 0, 0, 0, 39, - 0, 125, 40, 0, 0, 41, 42, 43, 0, 0, - 187, 183, 34, 159, 160, 161, 182, 0, 0, 0, - 131, 0, 0, 0, 0, 0, 33, 163, 134, 121, +static const short yydefact[] = { 135, + 39, 125, 124, 164, 35, 36, 37, 38, 0, 40, + 188, 121, 122, 188, 146, 147, 0, 0, 0, 39, + 0, 127, 40, 0, 0, 41, 42, 43, 0, 0, + 189, 185, 34, 161, 162, 163, 184, 0, 0, 0, + 133, 0, 0, 0, 0, 0, 33, 165, 136, 123, 44, 1, 2, 57, 61, 62, 63, 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 0, 0, - 0, 0, 177, 0, 0, 56, 75, 60, 178, 76, - 156, 157, 158, 227, 185, 0, 0, 0, 143, 132, - 126, 124, 116, 117, 0, 0, 77, 0, 0, 59, - 82, 84, 0, 0, 89, 83, 226, 0, 207, 0, - 0, 0, 0, 40, 195, 196, 5, 6, 7, 8, + 0, 0, 179, 0, 0, 56, 75, 60, 180, 76, + 158, 159, 160, 229, 187, 0, 0, 0, 145, 134, + 128, 126, 118, 119, 0, 0, 77, 0, 0, 59, + 82, 84, 0, 0, 89, 83, 228, 0, 209, 0, + 0, 0, 0, 40, 197, 198, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 0, 0, 0, 0, 0, 0, 0, 19, 20, 0, - 0, 0, 0, 0, 0, 0, 0, 0, 0, 184, - 40, 199, 0, 223, 139, 136, 135, 137, 138, 142, - 0, 129, 61, 62, 63, 64, 65, 66, 67, 68, - 69, 70, 71, 0, 0, 0, 0, 127, 0, 0, - 0, 81, 154, 88, 86, 0, 0, 211, 206, 189, - 188, 0, 0, 24, 28, 23, 27, 22, 26, 21, - 25, 29, 30, 0, 0, 47, 47, 232, 0, 0, - 221, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 140, 52, 103, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 186, + 40, 201, 0, 225, 141, 138, 137, 139, 140, 144, + 0, 131, 61, 62, 63, 64, 65, 66, 67, 68, + 69, 70, 71, 0, 0, 0, 0, 129, 0, 0, + 0, 81, 156, 88, 86, 0, 0, 213, 208, 191, + 190, 0, 0, 24, 28, 23, 27, 22, 26, 21, + 25, 29, 30, 0, 0, 47, 47, 234, 0, 0, + 223, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 142, 52, 103, 104, 3, 4, 101, 102, 105, 100, 96, 97, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 99, 98, 52, 58, 58, 85, 153, 147, 150, - 151, 0, 0, 78, 166, 167, 168, 173, 169, 170, - 171, 172, 164, 0, 175, 180, 179, 181, 0, 190, - 0, 0, 0, 228, 0, 230, 225, 0, 0, 0, + 0, 0, 0, 99, 98, 52, 58, 58, 85, 155, + 149, 152, 153, 0, 0, 78, 168, 169, 170, 175, + 171, 172, 173, 174, 166, 0, 177, 182, 181, 183, + 0, 192, 0, 0, 0, 230, 0, 232, 227, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 141, 0, 130, 0, 0, 0, - 0, 91, 115, 0, 0, 95, 0, 92, 0, 0, - 0, 0, 128, 79, 80, 146, 148, 0, 50, 87, - 165, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 235, 0, 0, 213, 0, 215, 218, 0, 0, 216, - 217, 0, 0, 0, 212, 0, 233, 0, 0, 0, - 54, 52, 225, 0, 0, 0, 0, 90, 93, 94, - 0, 0, 0, 0, 152, 149, 51, 45, 0, 174, - 0, 0, 205, 47, 48, 47, 202, 224, 0, 0, - 0, 0, 0, 208, 209, 210, 205, 0, 49, 55, - 53, 0, 0, 0, 0, 114, 0, 0, 0, 0, - 0, 155, 0, 0, 0, 204, 0, 0, 229, 231, - 0, 0, 0, 214, 219, 220, 0, 234, 107, 0, - 0, 0, 0, 0, 0, 0, 46, 176, 0, 0, - 0, 203, 200, 0, 222, 106, 0, 113, 109, 110, - 111, 112, 0, 193, 0, 0, 0, 201, 0, 191, - 0, 192, 0, 0, 108, 0, 0, 0, 0, 0, - 0, 198, 0, 0, 197, 194, 0, 0, 0 + 0, 0, 0, 0, 0, 0, 143, 0, 132, 0, + 0, 0, 0, 0, 0, 91, 117, 0, 0, 95, + 0, 92, 0, 0, 0, 0, 130, 79, 80, 148, + 150, 0, 50, 87, 167, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 237, 0, 0, 215, 0, 217, + 220, 0, 0, 218, 219, 0, 0, 0, 214, 0, + 235, 0, 0, 0, 54, 52, 227, 0, 0, 0, + 0, 0, 0, 90, 93, 94, 0, 0, 0, 0, + 154, 151, 51, 45, 0, 176, 0, 0, 207, 47, + 48, 47, 204, 226, 0, 0, 0, 0, 0, 210, + 211, 212, 207, 0, 49, 55, 53, 0, 0, 0, + 0, 0, 0, 116, 0, 0, 0, 0, 0, 157, + 0, 0, 0, 206, 0, 0, 231, 233, 0, 0, + 0, 216, 221, 222, 0, 236, 107, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 46, 178, 0, 0, + 0, 205, 202, 0, 224, 106, 0, 113, 0, 0, + 109, 110, 111, 112, 0, 195, 0, 0, 0, 203, + 0, 0, 0, 193, 0, 194, 0, 0, 108, 114, + 115, 0, 0, 0, 0, 0, 0, 200, 0, 0, + 199, 196, 0, 0, 0 }; static const short yydefgoto[] = { 73, - 234, 248, 249, 250, 251, 174, 175, 204, 176, 20, - 10, 29, 412, 284, 361, 378, 307, 362, 74, 75, - 187, 77, 78, 103, 186, 313, 275, 314, 95, 477, - 1, 2, 254, 229, 50, 158, 41, 90, 161, 79, - 327, 260, 261, 262, 30, 83, 11, 36, 12, 13, - 23, 332, 276, 80, 278, 387, 14, 32, 33, 150, - 456, 85, 211, 416, 417, 151, 152, 341, 153, 154 + 234, 250, 251, 252, 253, 174, 175, 204, 176, 20, + 10, 29, 420, 286, 365, 384, 309, 366, 74, 75, + 177, 77, 78, 103, 186, 317, 277, 318, 95, 493, + 1, 2, 256, 229, 50, 158, 41, 90, 161, 79, + 331, 262, 263, 264, 30, 83, 11, 36, 12, 13, + 23, 336, 278, 80, 280, 393, 14, 32, 33, 150, + 468, 85, 211, 424, 425, 151, 152, 345, 153, 154 }; static const short yypact[] = {-32768, - 107, 362,-32768,-32768,-32768,-32768,-32768,-32768, -37, 78, - 23,-32768,-32768, -12,-32768,-32768, 75, 2, 32, -6, - 27,-32768, 78, 85, 140,-32768,-32768,-32768, 957, -20, --32768,-32768, 121,-32768,-32768,-32768,-32768, 45, 53, 70, --32768, 68, 85, 957, 31, 31,-32768,-32768,-32768,-32768, --32768,-32768,-32768, 76,-32768,-32768,-32768,-32768,-32768,-32768, --32768,-32768,-32768,-32768,-32768,-32768,-32768,-32768, 178, 179, - 182, 67,-32768, 121, 88,-32768,-32768, 16,-32768,-32768, --32768,-32768,-32768, 1120,-32768, 170, 100, 184, 173,-32768, --32768,-32768,-32768,-32768, 995, 1033,-32768, 91, 92,-32768, --32768, 16, -42, 96, 767,-32768,-32768, 995,-32768, 147, - 1071, 22, 223, 78,-32768,-32768,-32768,-32768,-32768,-32768, + 181, 364,-32768,-32768,-32768,-32768,-32768,-32768, 6, -1, + 60,-32768,-32768, -14,-32768,-32768, 47, -22, 72, 45, + 33,-32768, -1, 125, 157,-32768,-32768,-32768, 1050, -21, +-32768,-32768, 22,-32768,-32768,-32768,-32768, 61, 67, 68, +-32768, 55, 125, 1050, -6, -6,-32768,-32768,-32768,-32768, +-32768,-32768,-32768, 66,-32768,-32768,-32768,-32768,-32768,-32768, +-32768,-32768,-32768,-32768,-32768,-32768,-32768,-32768, 168, 170, + 171, 566,-32768, 22, 73,-32768,-32768, -24,-32768,-32768, +-32768,-32768,-32768, 1213,-32768, 149, 57, 173, 155,-32768, +-32768,-32768,-32768,-32768, 1088, 1126,-32768, 74, 75,-32768, +-32768, -24, -82, 79, 860,-32768,-32768, 1088,-32768, 124, + 1164, 14, 128, -1,-32768,-32768,-32768,-32768,-32768,-32768, -32768,-32768,-32768,-32768,-32768,-32768,-32768,-32768,-32768,-32768, - 995, 995, 995, 995, 995, 995, 995,-32768,-32768, 995, - 995, 995, 995, 995, 995, 995, 995, 995, 995,-32768, - 78,-32768, 47,-32768,-32768,-32768,-32768,-32768,-32768,-32768, - 24,-32768, 41, 154, 203, 156, 204, 160, 205, 164, - 206, 207, 215, 166, 209, 216, 425,-32768, 995, 995, - 995,-32768, 805,-32768, 108, 118, 604,-32768,-32768, 76, --32768, 604, 604,-32768,-32768,-32768,-32768,-32768,-32768,-32768, --32768,-32768,-32768, 604, 957, 122, 123,-32768, 604, 120, - 125, 208, 138, 139, 143, 144, 145, 146, 149, 604, - 604, 604, 150, 957, 995, 995, 219,-32768, 151,-32768, --32768,-32768,-32768,-32768,-32768,-32768,-32768,-32768,-32768, 153, - 155, 157, 159, 843, 1033, 548, 226, 161, 165, 168, - 169,-32768,-32768, 151, -75, -3, 16,-32768, 121,-32768, - 152, 163, 881,-32768,-32768,-32768,-32768,-32768,-32768,-32768, --32768,-32768, 196, 1033,-32768,-32768,-32768,-32768, 162,-32768, - 172, 604, -5,-32768, 5,-32768, 175, 604, 176, 995, - 995, 995, 995, 995, 995, 995, 995, 181, 183, 185, - 995, 604, 604, 186,-32768, -22,-32768, 1033, 1033, 1033, - 1033,-32768,-32768, 25, -46,-32768, 7,-32768, 1033, 1033, - 1033, 1033,-32768,-32768,-32768,-32768,-32768, 919, 242,-32768, --32768, 261, -41, 266, 273, 190, 604, 292, 604, 995, --32768, 194, 604,-32768, 195,-32768,-32768, 197, 198,-32768, --32768, 604, 604, 604,-32768, 200,-32768, 995, 283, 305, --32768, 151, 175, 274, 210, 213, 1033,-32768,-32768,-32768, - 224, 228, 230, 231,-32768,-32768,-32768, 257, 232,-32768, - 604, 604, 995, 234,-32768, 234,-32768, 236, 604, 237, - 995, 995, 995,-32768,-32768,-32768, 995, 604,-32768,-32768, --32768, 220, 995, 1033, 1033,-32768, 1033, 1033, 1033, 1033, - 338,-32768, 319, 244, 238, 236, 243, 294,-32768,-32768, - 995, 246, 604,-32768,-32768,-32768, 250,-32768,-32768, 253, - 258, 254, 256, 259, 260, 262,-32768,-32768, 342, 13, - 328,-32768,-32768, 263,-32768,-32768, 1033,-32768,-32768,-32768, --32768,-32768, 604,-32768, 664, 83, 348,-32768, 264,-32768, - 268,-32768, 664, 604,-32768, 352, 280, 308, 604, 364, - 366,-32768, 604, 604,-32768,-32768, 388, 389,-32768 + 1088, 1088, 1088, 1088, 1088, 1088, 1088,-32768,-32768, 1088, + 1088, 1088, 1088, 1088, 1088, 1088, 1088, 1088, 1088,-32768, + -1,-32768, 40,-32768,-32768,-32768,-32768,-32768,-32768,-32768, + -9,-32768, 106, 143, 183, 148, 190, 152, 194, 154, + 196, 178, 195, 156, 197, 198, 425,-32768, 1088, 1088, + 1088,-32768, 898,-32768, 100, 98, 660,-32768,-32768, 66, +-32768, 660, 660,-32768,-32768,-32768,-32768,-32768,-32768,-32768, +-32768,-32768,-32768, 660, 1050, 104, 105,-32768, 660, 102, + 108, 177, 111, 112, 123, 130, 132, 133, 134, 660, + 660, 660, 135, 1050, 1088, 1088, 203,-32768, 136,-32768, +-32768,-32768,-32768,-32768,-32768,-32768,-32768,-32768,-32768, 137, + 138, 139, 140, 141, 142, 936, 1126, 604, 217, 145, + 146, 147, 150,-32768,-32768, 136, 18, -86, -24,-32768, + 22,-32768, 151, 153, 974,-32768,-32768,-32768,-32768,-32768, +-32768,-32768,-32768,-32768, 193, 1126,-32768,-32768,-32768,-32768, + 158,-32768, 159, 660, -5,-32768, 5,-32768, 172, 660, + 165, 1088, 1088, 1088, 1088, 1088, 1088, 1088, 1088, 174, + 175, 179, 1088, 660, 660, 180,-32768, -20,-32768, 1126, + 1126, 1126, 1126, 1126, 1126,-32768,-32768, -8, -81,-32768, + -36,-32768, 1126, 1126, 1126, 1126,-32768,-32768,-32768,-32768, +-32768, 1012, 222,-32768,-32768, 233, -18, 237, 239, 176, + 660, 269, 660, 1088,-32768, 185, 660,-32768, 186,-32768, +-32768, 187, 189,-32768,-32768, 660, 660, 660,-32768, 191, +-32768, 1088, 252, 276,-32768, 136, 172, 248, 201, 202, + 204, 205, 1126,-32768,-32768,-32768, 206, 207, 208, 209, +-32768,-32768,-32768, 232, 210,-32768, 660, 660, 1088, 211, +-32768, 211,-32768, 223, 660, 224, 1088, 1088, 1088,-32768, +-32768,-32768, 1088, 660,-32768,-32768,-32768, 192, 1088, 1126, + 1126, 1126, 1126,-32768, 1126, 1126, 1126, 1126, 293,-32768, + 275, 225, 199, 223, 214, 280,-32768,-32768, 1088, 220, + 660,-32768,-32768,-32768, 229,-32768,-32768, 230, 227, 231, + 238, 240, 236, 241, 243, 244,-32768,-32768, 323, 41, + 309,-32768,-32768, 242,-32768,-32768, 1126,-32768, 1126, 1126, +-32768,-32768,-32768,-32768, 660,-32768, 757, 59, 325,-32768, + 246, 247, 249,-32768, 251,-32768, 757, 660,-32768,-32768, +-32768, 336, 256, 295, 660, 346, 350,-32768, 660, 660, +-32768,-32768, 372, 376,-32768 }; static const short yypgoto[] = {-32768, --32768, 306, 307, 312, 313, -112, -110, -398,-32768, 365, - 379, -101,-32768, -199, 71,-32768, -249,-32768, -40,-32768, - -29,-32768, -65, 296,-32768, -90, 225, -229, 361,-32768, --32768,-32768,-32768,-32768, 368,-32768,-32768,-32768,-32768, 0, --32768, 80,-32768,-32768, 390,-32768,-32768,-32768,-32768, 410, --32768,-32768, -332, -31, 132, -89,-32768, 401,-32768,-32768, --32768,-32768,-32768, 79, 19,-32768,-32768, 60,-32768,-32768 +-32768, 297, 298, 299, 301, -112, -110, -426,-32768, 344, + 359, -103,-32768, -202, 54,-32768, -243,-32768, -38,-32768, + -29,-32768, -55, 287,-32768, -94, 216, -229, 348,-32768, +-32768,-32768,-32768,-32768, 355,-32768,-32768,-32768,-32768, 10, +-32768, 69,-32768,-32768, 379,-32768,-32768,-32768,-32768, 397, +-32768,-32768, -399, -56, 169, -104,-32768, 389,-32768,-32768, +-32768,-32768,-32768, 70, 1,-32768,-32768, 43,-32768,-32768 }; -#define YYLAST 1221 +#define YYLAST 1314 static const short yytable[] = { 76, - 202, 21, 203, 92, 323, 178, 102, 286, 81, 337, - 31, 359, 205, 44, 76, 315, 317, 34, 188, 339, - 24, 191, 194, 195, 196, 197, 198, 199, 200, 201, - 192, 360, 21, 324, 5, 6, 7, 8, 106, 102, - 45, 455, 193, 208, 333, 31, 212, 213, 338, 224, - 214, 215, 216, 217, 218, 219, 367, 463, 338, 223, - 181, 367, 93, 94, 369, 162, 177, 230, 231, 380, - 182, 52, 53, 104, 100, 55, 56, 57, 58, 59, - 60, 61, 62, 63, 64, 65, 66, 67, 15, 43, - 16, 82, 194, 195, 196, 197, 198, 199, 200, 201, - 35, 206, 207, 42, 209, 210, -118, 325, 49, 367, - 106, 68, 401, 255, 256, 257, 220, 221, 222, 370, - -58, 454, 461, 38, 39, 40, 227, 367, 47, 106, - 467, 3, 228, 368, 225, 226, 304, 4, 25, 26, - 27, 28, 15, 51, 16, 253, 86, 5, 6, 7, - 8, 156, 157, 259, 87, 277, -24, -24, -23, -23, - 277, 277, -22, -22, 282, 9, -21, -21, 232, 233, - 69, 88, 277, 70, 89, 76, 71, 277, 72, 101, - -59, 97, 98, 302, 419, 99, 420, 159, 277, 277, - 277, 462, 105, 155, 76, 303, 160, 257, 179, 180, - 183, 345, 189, 347, 348, 349, -28, -27, -26, -25, - 263, 355, 235, -31, 177, 177, 177, 363, 364, 365, - 366, -32, 236, 264, 283, 285, 288, 289, 371, 372, - 373, 374, 194, 195, 196, 197, 198, 199, 200, 201, - 291, 292, 305, 290, 177, 293, 294, 295, 296, 318, - 277, 297, 301, 306, 328, 331, 277, 308, 326, 309, - 344, 310, 346, 311, 334, 319, 350, 351, 329, 320, - 277, 277, 321, 322, 335, 359, 406, 340, 177, 177, - 177, 177, 343, 352, 379, 353, 381, 354, 358, 177, - 177, 177, 177, 382, 383, 385, 389, 391, 259, 392, - 393, 424, 425, 426, 397, 277, 399, 277, 400, 403, - 411, 277, 404, 431, 432, 405, 433, 434, 435, 436, - 277, 277, 277, 279, 280, 429, 407, 202, 398, 203, - 408, 442, 409, 410, 413, 281, 418, 177, 421, 423, - 287, 437, 438, 202, 440, 203, 439, 338, 441, 277, - 277, 298, 299, 300, 443, 445, 459, 277, 446, 448, - 447, 449, 453, 457, 450, 451, 277, 452, 464, 465, - 466, 458, 469, 430, 177, 177, 471, 177, 177, 177, - 177, -34, 470, 15, 473, 16, 474, 478, 479, 146, - 147, 277, 4, -34, -34, 148, 149, 84, 46, 377, - 185, 252, -34, -34, -34, -34, 96, 376, -34, 17, - 91, 22, 48, 336, 37, 427, 18, 177, 388, 342, - 19, 277, 402, 0, 0, 0, 0, 0, 0, 52, - 53, 0, 277, 356, 357, 0, 0, 277, 0, 0, - 0, 277, 277, 0, 0, 0, 15, 0, 16, 0, - 237, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 238, 239, 0, 0, 0, 0, 384, 0, - 386, 0, 0, 0, 390, 0, 0, 0, 0, 0, - 0, 0, 0, 394, 395, 396, 0, 0, 0, 0, + 202, 178, 203, 188, 288, 92, 191, 81, 31, 341, + 205, 21, 327, 363, 76, 34, 102, 319, 321, 343, + 181, 373, 192, 467, 329, 93, 94, 106, 208, 375, + 182, 212, 213, 364, 193, 214, 215, 216, 217, 218, + 219, 477, 21, 15, 223, 16, 337, 224, 342, 102, + 194, 195, 196, 197, 198, 199, 200, 201, 342, 25, + 26, 27, 28, 24, 44, 162, 373, 475, 194, 195, + 196, 197, 198, 199, 200, 201, 376, 483, 187, 42, + -58, 187, 31, 104, 373, 5, 6, 7, 8, 106, + 82, 45, 386, 227, 373, 38, 39, 40, 35, 228, + 374, 206, 207, 187, 209, 210, 187, 187, 156, 157, + 187, 187, 187, 187, 187, 187, 220, 221, 222, 187, + 255, 306, 407, 257, 258, 259, 328, 225, 226, 43, + 279, 106, 230, 231, 47, 279, 279, 194, 195, 196, + 197, 198, 199, 200, 201, -24, -24, 279, 49, 466, + -23, -23, 279, 261, -22, -22, -21, -21, 232, 233, + 51, 89, 86, 279, 279, 279, 284, 476, 87, 88, + -59, 97, 155, 98, 99, 76, 159, 105, 160, 189, + -120, 179, 180, 183, -31, 304, -28, 427, 349, 428, + 351, 352, 353, -27, 76, 305, 187, -26, 359, -25, + 235, -32, 265, 266, 236, 3, 285, 287, 290, 259, + 291, 4, 292, 293, 294, 367, 368, 369, 370, 371, + 372, 5, 6, 7, 8, 295, 307, 279, 377, 378, + 379, 380, 296, 279, 297, 298, 299, 303, 308, 9, + 322, 310, 311, 312, 313, 314, 315, 279, 279, 323, + 324, 325, 335, 332, 326, 363, 385, 387, 333, 388, + 338, 339, 348, 187, 350, 187, 187, 187, 354, 355, + 330, 347, 391, 187, 344, 405, 356, 357, 414, 406, + 389, 358, 362, 409, 279, 419, 279, 395, 397, 398, + 279, 399, 432, 433, 434, 403, 447, 437, 448, 279, + 279, 279, 261, 410, 411, 450, 412, 413, 415, 416, + 417, 418, 421, 426, 187, 439, 440, 441, 442, 451, + 443, 444, 445, 446, 452, 429, 431, 449, 453, 457, + 279, 279, 404, 342, 455, 456, 458, 202, 279, 203, + 459, 461, 460, 465, 469, 478, 462, 279, 463, 464, + 470, 479, 480, 482, 481, 202, 485, 203, 486, 187, + 281, 282, 471, 487, 472, 473, 489, 187, 187, 187, + 490, 494, 283, 187, 279, 495, 84, 289, 46, 438, + 146, 147, 148, -34, 149, 15, 383, 16, 300, 301, + 302, 185, 254, 96, 4, -34, -34, 91, 22, 187, + 382, 48, 37, 435, -34, -34, -34, -34, 279, 408, + -34, 17, 0, 394, 0, 0, 0, 0, 18, 0, + 0, 279, 19, 0, 0, 0, 0, 0, 279, 52, + 53, 0, 279, 279, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 15, 0, 16, 0, + 237, 0, 340, 0, 0, 0, 0, 0, 346, 0, + 0, 0, 238, 239, 0, 0, 0, 0, 0, 0, + 0, 0, 360, 361, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 117, 118, 119, 120, 121, - 122, 123, 124, 125, 126, 127, 128, 129, 130, 0, - 0, 0, 414, 415, 240, 0, 241, 242, 138, 139, - 422, 243, 0, 0, 0, 0, 0, 0, 0, 428, - 0, 244, 0, 0, 245, 0, 246, 0, 0, 247, + 122, 123, 124, 125, 126, 127, 128, 129, 130, 390, + 0, 392, 0, 0, 240, 396, 241, 242, 138, 139, + 0, 243, 244, 245, 400, 401, 402, 0, 0, 0, + 0, 246, 0, 0, 247, 0, 248, 0, 0, 249, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 422, 423, 0, 0, 0, + 0, 0, 0, 430, 0, 0, 0, 0, 0, 0, + 52, 53, 436, 100, 55, 56, 57, 58, 59, 60, + 61, 62, 63, 64, 65, 66, 67, 15, 0, 16, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 454, + 0, 0, 0, 0, 0, 0, 0, 0, 52, 53, + 68, 100, 163, 164, 165, 166, 167, 168, 169, 170, + 171, 172, 173, 66, 67, 15, 0, 16, 0, 0, + 0, 0, 0, 474, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 484, 0, 68, 0, + 0, 0, 0, 488, 0, 0, 0, 491, 492, 0, + 0, 0, 267, 268, 52, 53, 269, 0, 0, 69, + 0, 0, 70, 0, 0, 71, 0, 72, 101, 0, + 0, 15, 0, 16, 0, 270, 271, 272, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 273, 274, 0, + 0, 0, 0, 0, 0, 0, 0, 69, 0, 0, + 70, 0, 0, 71, 0, 72, 320, 275, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 117, 118, 119, 120, 121, 122, 123, 124, 125, 126, + 127, 128, 129, 130, 0, 0, 0, 0, 0, 240, + 0, 241, 242, 138, 139, 0, 243, 244, 245, 267, + 268, 0, 0, 269, 0, 0, 0, 0, 0, 276, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 52, 53, 444, 100, 163, 164, 165, 166, - 167, 168, 169, 170, 171, 172, 173, 66, 67, 15, + 0, 0, 270, 271, 272, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 273, 274, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 275, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 117, 118, 119, + 120, 121, 122, 123, 124, 125, 126, 127, 128, 129, + 130, 0, 0, 0, 0, 0, 240, 0, 241, 242, + 138, 139, 0, 243, 244, 245, 0, 0, 0, 0, + 0, 0, 0, 0, 52, 53, 276, 100, 55, 56, + 57, 58, 59, 60, 61, 62, 63, 64, 65, 66, + 67, 15, 0, 16, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 184, 0, 0, 0, + 0, 0, 52, 53, 68, 100, 55, 56, 57, 58, + 59, 60, 61, 62, 63, 64, 65, 66, 67, 15, 0, 16, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 460, 0, 0, 0, 0, 0, - 0, 0, 68, 0, 0, 468, 0, 0, 0, 0, - 472, 0, 0, 0, 475, 476, 265, 266, 52, 53, - 267, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 15, 0, 16, 0, 268, - 269, 270, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 271, 272, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 260, 0, 0, 0, 0, 0, + 52, 53, 68, 100, 163, 164, 165, 166, 167, 168, + 169, 170, 171, 172, 173, 66, 67, 15, 0, 16, + 0, 0, 0, 69, 0, 0, 70, 0, 0, 71, + 0, 72, 0, 0, 0, 0, 0, 0, 52, 53, + 68, 100, 55, 56, 57, 58, 59, 60, 61, 62, + 63, 64, 65, 66, 67, 15, 0, 16, 0, 0, 0, 69, 0, 0, 70, 0, 0, 71, 0, 72, - 316, 273, 0, 0, 0, 0, 265, 266, 0, 0, - 267, 0, 0, 0, 117, 118, 119, 120, 121, 122, - 123, 124, 125, 126, 127, 128, 129, 130, 0, 268, - 269, 270, 0, 240, 0, 241, 242, 138, 139, 0, - 243, 271, 272, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 274, 0, 0, 0, 0, 0, 0, - 0, 273, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 117, 118, 119, 120, 121, 122, - 123, 124, 125, 126, 127, 128, 129, 130, 0, 0, - 0, 0, 0, 240, 0, 241, 242, 138, 139, 0, - 243, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 52, 53, 274, 100, 55, 56, 57, 58, 59, - 60, 61, 62, 63, 64, 65, 66, 67, 15, 0, - 16, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 184, 0, 0, 0, 0, 0, 52, - 53, 68, 100, 55, 56, 57, 58, 59, 60, 61, - 62, 63, 64, 65, 66, 67, 15, 0, 16, 0, - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 258, 0, 0, 0, 0, 0, 52, 53, 68, - 100, 163, 164, 165, 166, 167, 168, 169, 170, 171, - 172, 173, 66, 67, 15, 0, 16, 0, 0, 0, - 69, 0, 0, 70, 0, 0, 71, 0, 72, 0, - 0, 0, 0, 0, 0, 52, 53, 68, 100, 55, - 56, 57, 58, 59, 60, 61, 62, 63, 64, 65, - 66, 67, 15, 0, 16, 0, 0, 0, 69, 0, - 0, 70, 0, 0, 71, 0, 72, 330, 0, 0, - 0, 0, 0, 52, 53, 68, 100, 55, 56, 57, - 58, 59, 60, 61, 62, 63, 64, 65, 66, 67, - 15, 0, 16, 0, 0, 0, 69, 0, 0, 70, - 0, 312, 71, 0, 72, 375, 0, 0, 0, 0, - 0, 52, 53, 68, 54, 55, 56, 57, 58, 59, - 60, 61, 62, 63, 64, 65, 66, 67, 15, 0, - 16, 0, 0, 0, 69, 0, 0, 70, 0, 0, - 71, 0, 72, 0, 0, 0, 0, 0, 0, 52, - 53, 68, 100, 55, 56, 57, 58, 59, 60, 61, - 62, 63, 64, 65, 66, 67, 15, 0, 16, 0, - 0, 0, 69, 0, 0, 70, 0, 0, 71, 0, - 72, 0, 0, 0, 0, 0, 0, 52, 53, 68, - 100, 163, 164, 165, 166, 167, 168, 169, 170, 171, - 172, 173, 66, 67, 15, 0, 16, 0, 0, 0, - 69, 0, 0, 70, 0, 0, 71, 0, 72, 0, - 0, 0, 0, 0, 0, 52, 53, 68, 190, 55, - 56, 57, 58, 59, 60, 61, 62, 63, 64, 65, - 66, 67, 15, 0, 16, 0, 0, 0, 69, 0, - 0, 70, 0, 0, 71, 0, 72, 0, 0, 0, - 0, 0, 0, 0, 0, 68, 0, 0, 0, 0, + 334, 0, 0, 0, 0, 0, 52, 53, 68, 100, + 55, 56, 57, 58, 59, 60, 61, 62, 63, 64, + 65, 66, 67, 15, 0, 16, 0, 0, 0, 69, + 0, 0, 70, 0, 316, 71, 0, 72, 381, 0, + 0, 0, 0, 0, 52, 53, 68, 54, 55, 56, + 57, 58, 59, 60, 61, 62, 63, 64, 65, 66, + 67, 15, 0, 16, 0, 0, 0, 69, 0, 0, + 70, 0, 0, 71, 0, 72, 0, 0, 0, 0, + 0, 0, 52, 53, 68, 100, 55, 56, 57, 58, + 59, 60, 61, 62, 63, 64, 65, 66, 67, 15, + 0, 16, 0, 0, 0, 69, 0, 0, 70, 0, + 0, 71, 0, 72, 0, 0, 0, 0, 0, 0, + 52, 53, 68, 100, 163, 164, 165, 166, 167, 168, + 169, 170, 171, 172, 173, 66, 67, 15, 0, 16, + 0, 0, 0, 69, 0, 0, 70, 0, 0, 71, + 0, 72, 0, 0, 0, 0, 0, 0, 52, 53, + 68, 190, 55, 56, 57, 58, 59, 60, 61, 62, + 63, 64, 65, 66, 67, 15, 0, 16, 0, 0, + 0, 69, 0, 0, 70, 0, 0, 71, 0, 72, + 0, 0, 0, 0, 0, 0, 0, 0, 68, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 69, 0, 0, 70, - 0, 0, 71, 0, 72, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 107, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 108, 0, 0, 0, 0, - 0, 0, 0, 0, 69, 109, 110, 70, 0, 0, - 71, 0, 72, 0, 111, 112, 113, 114, 115, 116, - 117, 118, 119, 120, 121, 122, 123, 124, 125, 126, - 127, 128, 129, 130, 131, 132, 133, 0, 0, 134, - 135, 136, 137, 138, 139, 140, 141, 142, 143, 144, - 145 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 69, + 0, 0, 70, 0, 0, 71, 0, 72, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 107, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 108, 0, + 0, 0, 0, 0, 0, 0, 0, 69, 109, 110, + 70, 0, 0, 71, 0, 72, 0, 111, 112, 113, + 114, 115, 116, 117, 118, 119, 120, 121, 122, 123, + 124, 125, 126, 127, 128, 129, 130, 131, 132, 133, + 0, 0, 134, 135, 136, 137, 138, 139, 140, 141, + 142, 143, 144, 145 }; static const short yycheck[] = { 29, - 113, 2, 113, 44, 254, 96, 72, 207, 29, 15, - 23, 34, 114, 20, 44, 245, 246, 30, 108, 15, - 58, 111, 10, 11, 12, 13, 14, 15, 16, 17, - 9, 54, 33, 109, 41, 42, 43, 44, 114, 105, - 47, 440, 21, 133, 274, 23, 136, 137, 54, 151, - 140, 141, 142, 143, 144, 145, 103, 456, 54, 149, - 103, 103, 32, 33, 111, 95, 96, 27, 28, 111, - 113, 5, 6, 74, 8, 9, 10, 11, 12, 13, - 14, 15, 16, 17, 18, 19, 20, 21, 22, 58, - 24, 112, 10, 11, 12, 13, 14, 15, 16, 17, - 113, 131, 132, 102, 134, 135, 0, 111, 24, 103, - 114, 45, 362, 179, 180, 181, 146, 147, 148, 113, - 105, 109, 455, 49, 50, 51, 103, 103, 102, 114, - 463, 25, 109, 109, 88, 89, 226, 31, 61, 62, - 63, 64, 22, 4, 24, 177, 102, 41, 42, 43, - 44, 52, 53, 183, 102, 187, 3, 4, 3, 4, - 192, 193, 3, 4, 205, 59, 3, 4, 3, 4, - 104, 102, 204, 107, 107, 205, 110, 209, 112, 113, - 105, 4, 4, 224, 384, 4, 386, 4, 220, 221, - 222, 109, 105, 24, 224, 225, 24, 263, 108, 108, - 105, 291, 56, 293, 294, 295, 4, 4, 4, 4, - 103, 301, 4, 7, 244, 245, 246, 308, 309, 310, - 311, 7, 7, 106, 103, 103, 107, 103, 319, 320, - 321, 322, 10, 11, 12, 13, 14, 15, 16, 17, - 103, 103, 24, 36, 274, 103, 103, 103, 103, 24, - 282, 103, 103, 103, 103, 60, 288, 105, 259, 105, - 290, 105, 292, 105, 103, 105, 296, 297, 106, 105, - 302, 303, 105, 105, 103, 34, 367, 103, 308, 309, - 310, 311, 107, 103, 24, 103, 21, 103, 103, 319, - 320, 321, 322, 21, 105, 4, 103, 103, 328, 103, - 103, 391, 392, 393, 105, 337, 24, 339, 4, 36, - 54, 343, 103, 404, 405, 103, 407, 408, 409, 410, - 352, 353, 354, 192, 193, 106, 103, 440, 358, 440, - 103, 421, 103, 103, 103, 204, 103, 367, 103, 103, - 209, 4, 24, 456, 107, 456, 103, 54, 106, 381, - 382, 220, 221, 222, 109, 106, 447, 389, 106, 106, - 103, 106, 21, 36, 106, 106, 398, 106, 21, 106, - 103, 109, 21, 403, 404, 405, 69, 407, 408, 409, - 410, 20, 103, 22, 21, 24, 21, 0, 0, 84, - 84, 423, 31, 32, 33, 84, 84, 33, 20, 329, - 105, 177, 41, 42, 43, 44, 46, 328, 47, 48, - 43, 2, 23, 282, 14, 397, 55, 447, 340, 288, - 59, 453, 363, -1, -1, -1, -1, -1, -1, 5, - 6, -1, 464, 302, 303, -1, -1, 469, -1, -1, - -1, 473, 474, -1, -1, -1, 22, -1, 24, -1, - 26, -1, -1, -1, -1, -1, -1, -1, -1, -1, - -1, -1, 38, 39, -1, -1, -1, -1, 337, -1, - 339, -1, -1, -1, 343, -1, -1, -1, -1, -1, - -1, -1, -1, 352, 353, 354, -1, -1, -1, -1, + 113, 96, 113, 108, 207, 44, 111, 29, 23, 15, + 114, 2, 256, 34, 44, 30, 72, 247, 248, 15, + 103, 103, 9, 450, 111, 32, 33, 114, 133, 111, + 113, 136, 137, 54, 21, 140, 141, 142, 143, 144, + 145, 468, 33, 22, 149, 24, 276, 151, 54, 105, + 10, 11, 12, 13, 14, 15, 16, 17, 54, 61, + 62, 63, 64, 58, 20, 95, 103, 467, 10, 11, + 12, 13, 14, 15, 16, 17, 113, 477, 108, 102, + 105, 111, 23, 74, 103, 41, 42, 43, 44, 114, + 112, 47, 111, 103, 103, 49, 50, 51, 113, 109, + 109, 131, 132, 133, 134, 135, 136, 137, 52, 53, + 140, 141, 142, 143, 144, 145, 146, 147, 148, 149, + 177, 226, 366, 179, 180, 181, 109, 88, 89, 58, + 187, 114, 27, 28, 102, 192, 193, 10, 11, 12, + 13, 14, 15, 16, 17, 3, 4, 204, 24, 109, + 3, 4, 209, 183, 3, 4, 3, 4, 3, 4, + 4, 107, 102, 220, 221, 222, 205, 109, 102, 102, + 105, 4, 24, 4, 4, 205, 4, 105, 24, 56, + 0, 108, 108, 105, 7, 224, 4, 390, 293, 392, + 295, 296, 297, 4, 224, 225, 226, 4, 303, 4, + 4, 7, 103, 106, 7, 25, 103, 103, 107, 265, + 103, 31, 36, 103, 103, 310, 311, 312, 313, 314, + 315, 41, 42, 43, 44, 103, 24, 284, 323, 324, + 325, 326, 103, 290, 103, 103, 103, 103, 103, 59, + 24, 105, 105, 105, 105, 105, 105, 304, 305, 105, + 105, 105, 60, 103, 105, 34, 24, 21, 106, 21, + 103, 103, 292, 293, 294, 295, 296, 297, 298, 299, + 261, 107, 4, 303, 103, 24, 103, 103, 373, 4, + 105, 103, 103, 36, 341, 54, 343, 103, 103, 103, + 347, 103, 397, 398, 399, 105, 4, 106, 24, 356, + 357, 358, 332, 103, 103, 107, 103, 103, 103, 103, + 103, 103, 103, 103, 344, 410, 411, 412, 413, 106, + 415, 416, 417, 418, 429, 103, 103, 103, 109, 103, + 387, 388, 362, 54, 106, 106, 106, 450, 395, 450, + 103, 106, 103, 21, 36, 21, 106, 404, 106, 106, + 109, 106, 106, 103, 106, 468, 21, 468, 103, 389, + 192, 193, 457, 69, 459, 460, 21, 397, 398, 399, + 21, 0, 204, 403, 431, 0, 33, 209, 20, 409, + 84, 84, 84, 20, 84, 22, 333, 24, 220, 221, + 222, 105, 177, 46, 31, 32, 33, 43, 2, 429, + 332, 23, 14, 403, 41, 42, 43, 44, 465, 367, + 47, 48, -1, 344, -1, -1, -1, -1, 55, -1, + -1, 478, 59, -1, -1, -1, -1, -1, 485, 5, + 6, -1, 489, 490, -1, -1, -1, -1, -1, -1, + -1, -1, -1, -1, -1, -1, 22, -1, 24, -1, + 26, -1, 284, -1, -1, -1, -1, -1, 290, -1, + -1, -1, 38, 39, -1, -1, -1, -1, -1, -1, + -1, -1, 304, 305, -1, -1, -1, -1, -1, -1, + -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 71, 72, 73, 74, 75, - 76, 77, 78, 79, 80, 81, 82, 83, 84, -1, - -1, -1, 381, 382, 90, -1, 92, 93, 94, 95, - 389, 97, -1, -1, -1, -1, -1, -1, -1, 398, + 76, 77, 78, 79, 80, 81, 82, 83, 84, 341, + -1, 343, -1, -1, 90, 347, 92, 93, 94, 95, + -1, 97, 98, 99, 356, 357, 358, -1, -1, -1, -1, 107, -1, -1, 110, -1, 112, -1, -1, 115, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, - -1, -1, 5, 6, 423, 8, 9, 10, 11, 12, + -1, -1, -1, -1, -1, 387, 388, -1, -1, -1, + -1, -1, -1, 395, -1, -1, -1, -1, -1, -1, + 5, 6, 404, 8, 9, 10, 11, 12, 13, 14, + 15, 16, 17, 18, 19, 20, 21, 22, -1, 24, + -1, -1, -1, -1, -1, -1, -1, -1, -1, 431, + -1, -1, -1, -1, -1, -1, -1, -1, 5, 6, + 45, 8, 9, 10, 11, 12, 13, 14, 15, 16, + 17, 18, 19, 20, 21, 22, -1, 24, -1, -1, + -1, -1, -1, 465, -1, -1, -1, -1, -1, -1, + -1, -1, -1, -1, -1, -1, 478, -1, 45, -1, + -1, -1, -1, 485, -1, -1, -1, 489, 490, -1, + -1, -1, 3, 4, 5, 6, 7, -1, -1, 104, + -1, -1, 107, -1, -1, 110, -1, 112, 113, -1, + -1, 22, -1, 24, -1, 26, 27, 28, -1, -1, + -1, -1, -1, -1, -1, -1, -1, 38, 39, -1, + -1, -1, -1, -1, -1, -1, -1, 104, -1, -1, + 107, -1, -1, 110, -1, 112, 113, 58, -1, -1, + -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, + 71, 72, 73, 74, 75, 76, 77, 78, 79, 80, + 81, 82, 83, 84, -1, -1, -1, -1, -1, 90, + -1, 92, 93, 94, 95, -1, 97, 98, 99, 3, + 4, -1, -1, 7, -1, -1, -1, -1, -1, 110, + -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, + -1, -1, 26, 27, 28, -1, -1, -1, -1, -1, + -1, -1, -1, -1, 38, 39, -1, -1, -1, -1, + -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, + -1, -1, -1, -1, 58, -1, -1, -1, -1, -1, + -1, -1, -1, -1, -1, -1, -1, 71, 72, 73, + 74, 75, 76, 77, 78, 79, 80, 81, 82, 83, + 84, -1, -1, -1, -1, -1, 90, -1, 92, 93, + 94, 95, -1, 97, 98, 99, -1, -1, -1, -1, + -1, -1, -1, -1, 5, 6, 110, 8, 9, 10, + 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, + 21, 22, -1, 24, -1, -1, -1, -1, -1, -1, + -1, -1, -1, -1, -1, -1, 37, -1, -1, -1, + -1, -1, 5, 6, 45, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, -1, 24, -1, -1, -1, -1, -1, -1, -1, -1, - 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110, -1, 112, -1, -1, -1, -1, -1, -1, 5, - 6, 45, 8, 9, 10, 11, 12, 13, 14, 15, - 16, 17, 18, 19, 20, 21, 22, -1, 24, -1, - -1, -1, 104, -1, -1, 107, -1, -1, 110, -1, - 112, -1, -1, -1, -1, -1, -1, 5, 6, 45, - 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, - 18, 19, 20, 21, 22, -1, 24, -1, -1, -1, - 104, -1, -1, 107, -1, -1, 110, -1, 112, -1, - -1, -1, -1, -1, -1, 5, 6, 45, 8, 9, - 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, - 20, 21, 22, -1, 24, -1, -1, -1, 104, -1, - -1, 107, -1, -1, 110, -1, 112, -1, -1, -1, - -1, -1, -1, -1, -1, 45, -1, -1, -1, -1, + 37, -1, -1, -1, -1, -1, 5, 6, 45, 8, + 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, + 19, 20, 21, 22, -1, 24, -1, -1, -1, 104, + -1, -1, 107, -1, 109, 110, -1, 112, 37, -1, + -1, -1, -1, -1, 5, 6, 45, 8, 9, 10, + 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, + 21, 22, -1, 24, -1, -1, -1, 104, -1, -1, + 107, -1, -1, 110, -1, 112, -1, -1, -1, -1, + -1, -1, 5, 6, 45, 8, 9, 10, 11, 12, + 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, + -1, 24, -1, -1, -1, 104, -1, -1, 107, -1, + -1, 110, -1, 112, -1, -1, -1, -1, -1, -1, + 5, 6, 45, 8, 9, 10, 11, 12, 13, 14, + 15, 16, 17, 18, 19, 20, 21, 22, -1, 24, + -1, -1, -1, 104, -1, -1, 107, -1, -1, 110, + -1, 112, -1, -1, -1, -1, -1, -1, 5, 6, + 45, 8, 9, 10, 11, 12, 13, 14, 15, 16, + 17, 18, 19, 20, 21, 22, -1, 24, -1, -1, + -1, 104, -1, -1, 107, -1, -1, 110, -1, 112, + -1, -1, -1, -1, -1, -1, -1, -1, 45, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, - -1, -1, -1, -1, -1, -1, 104, -1, -1, 107, - -1, -1, 110, -1, 112, -1, -1, -1, -1, -1, - -1, -1, -1, -1, 35, -1, -1, -1, -1, -1, - -1, -1, -1, -1, -1, 46, -1, -1, -1, -1, - -1, -1, -1, -1, 104, 56, 57, 107, -1, -1, - 110, -1, 112, -1, 65, 66, 67, 68, 69, 70, - 71, 72, 73, 74, 75, 76, 77, 78, 79, 80, - 81, 82, 83, 84, 85, 86, 87, -1, -1, 90, - 91, 92, 93, 94, 95, 96, 97, 98, 99, 100, - 101 + -1, -1, -1, -1, -1, -1, -1, -1, -1, 104, + -1, -1, 107, -1, -1, 110, -1, 112, -1, -1, + -1, -1, -1, -1, -1, -1, -1, 35, -1, -1, + -1, -1, -1, -1, -1, -1, -1, -1, 46, -1, + -1, -1, -1, -1, -1, -1, -1, 104, 56, 57, + 107, -1, -1, 110, -1, 112, -1, 65, 66, 67, + 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, + 78, 79, 80, 81, 82, 83, 84, 85, 86, 87, + -1, -1, 90, 91, 92, 93, 94, 95, 96, 97, + 98, 99, 100, 101 }; /* -*-C-*- Note some compilers choke on comments on `#line' lines. */ #line 3 "/usr/share/bison.simple" @@ -2226,7 +2250,7 @@ switch (yyn) { case 2: -#line 1011 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1011 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { if (yyvsp[0].UIntVal > (uint32_t)INT32_MAX) // Outside of my range! ThrowException("Value too large for type!"); @@ -2234,7 +2258,7 @@ ; break;} case 4: -#line 1019 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1019 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { if (yyvsp[0].UInt64Val > (uint64_t)INT64_MAX) // Outside of my range! ThrowException("Value too large for type!"); @@ -2242,55 +2266,55 @@ ; break;} case 33: -#line 1042 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1042 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { yyval.StrVal = yyvsp[-1].StrVal; ; break;} case 34: -#line 1045 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1045 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { yyval.StrVal = 0; ; break;} case 35: -#line 1049 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1049 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { yyval.Linkage = GlobalValue::InternalLinkage; ; break;} case 36: -#line 1050 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1050 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { yyval.Linkage = GlobalValue::LinkOnceLinkage; ; break;} case 37: -#line 1051 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1051 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { yyval.Linkage = GlobalValue::WeakLinkage; ; break;} case 38: -#line 1052 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1052 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { yyval.Linkage = GlobalValue::AppendingLinkage; ; break;} case 39: -#line 1053 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1053 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { yyval.Linkage = GlobalValue::ExternalLinkage; ; break;} case 40: -#line 1055 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1055 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { yyval.UIntVal = CallingConv::C; ; break;} case 41: -#line 1056 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1056 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { yyval.UIntVal = CallingConv::C; ; break;} case 42: -#line 1057 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1057 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { yyval.UIntVal = CallingConv::Fast; ; break;} case 43: -#line 1058 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1058 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { yyval.UIntVal = CallingConv::Cold; ; break;} case 44: -#line 1059 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1059 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { if ((unsigned)yyvsp[0].UInt64Val != yyvsp[0].UInt64Val) ThrowException("Calling conv too large!"); @@ -2298,11 +2322,11 @@ ; break;} case 45: -#line 1067 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1067 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { yyval.UIntVal = 0; ; break;} case 46: -#line 1068 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1068 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { yyval.UIntVal = yyvsp[0].UInt64Val; if (yyval.UIntVal != 0 && !isPowerOf2_32(yyval.UIntVal)) @@ -2310,11 +2334,11 @@ ; break;} case 47: -#line 1073 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1073 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { yyval.UIntVal = 0; ; break;} case 48: -#line 1074 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1074 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { yyval.UIntVal = yyvsp[0].UInt64Val; if (yyval.UIntVal != 0 && !isPowerOf2_32(yyval.UIntVal)) @@ -2322,7 +2346,7 @@ ; break;} case 49: -#line 1081 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1081 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { for (unsigned i = 0, e = strlen(yyvsp[0].StrVal); i != e; ++i) if (yyvsp[0].StrVal[i] == '"' || yyvsp[0].StrVal[i] == '\\') @@ -2331,30 +2355,30 @@ ; break;} case 50: -#line 1088 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1088 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { yyval.StrVal = 0; ; break;} case 51: -#line 1089 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1089 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { yyval.StrVal = yyvsp[0].StrVal; ; break;} case 52: -#line 1094 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1094 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" {; break;} case 53: -#line 1095 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1095 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" {; break;} case 54: -#line 1096 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1096 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { CurGV->setSection(yyvsp[0].StrVal); free(yyvsp[0].StrVal); ; break;} case 55: -#line 1100 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1100 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { if (yyvsp[0].UInt64Val != 0 && !isPowerOf2_32(yyvsp[0].UInt64Val)) ThrowException("Alignment must be a power of two!"); @@ -2362,15 +2386,15 @@ ; break;} case 57: -#line 1113 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1113 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { yyval.TypeVal = new PATypeHolder(yyvsp[0].PrimType); ; break;} case 59: -#line 1114 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1114 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { yyval.TypeVal = new PATypeHolder(yyvsp[0].PrimType); ; break;} case 60: -#line 1116 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1116 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { if (!UpRefs.empty()) ThrowException("Invalid upreference in type: " + (*yyvsp[0].TypeVal)->getDescription()); @@ -2378,25 +2402,25 @@ ; break;} case 74: -#line 1127 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1127 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { yyval.TypeVal = new PATypeHolder(OpaqueType::get()); ; break;} case 75: -#line 1130 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1130 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { yyval.TypeVal = new PATypeHolder(yyvsp[0].PrimType); ; break;} case 76: -#line 1133 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1133 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { // Named types are also simple types... yyval.TypeVal = new PATypeHolder(getTypeVal(yyvsp[0].ValIDVal)); ; break;} case 77: -#line 1139 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1139 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { // Type UpReference if (yyvsp[0].UInt64Val > (uint64_t)~0U) ThrowException("Value out of range!"); OpaqueType *OT = OpaqueType::get(); // Use temporary placeholder @@ -2406,7 +2430,7 @@ ; break;} case 78: -#line 1146 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1146 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { // Function derived type? std::vector Params; for (std::list::iterator I = yyvsp[-1].TypeList->begin(), @@ -2421,14 +2445,14 @@ ; break;} case 79: -#line 1158 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1158 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { // Sized array type? yyval.TypeVal = new PATypeHolder(HandleUpRefs(ArrayType::get(*yyvsp[-1].TypeVal, (unsigned)yyvsp[-3].UInt64Val))); delete yyvsp[-1].TypeVal; ; break;} case 80: -#line 1162 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1162 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { // Packed array type? const llvm::Type* ElemTy = yyvsp[-1].TypeVal->get(); if ((unsigned)yyvsp[-3].UInt64Val != yyvsp[-3].UInt64Val) @@ -2442,7 +2466,7 @@ ; break;} case 81: -#line 1173 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1173 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { // Structure type? std::vector Elements; for (std::list::iterator I = yyvsp[-1].TypeList->begin(), @@ -2454,51 +2478,51 @@ ; break;} case 82: -#line 1182 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1182 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { // Empty structure type? yyval.TypeVal = new PATypeHolder(StructType::get(std::vector())); ; break;} case 83: -#line 1185 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1185 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { // Pointer type? yyval.TypeVal = new PATypeHolder(HandleUpRefs(PointerType::get(*yyvsp[-1].TypeVal))); delete yyvsp[-1].TypeVal; ; break;} case 84: -#line 1193 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1193 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { yyval.TypeList = new std::list(); yyval.TypeList->push_back(*yyvsp[0].TypeVal); delete yyvsp[0].TypeVal; ; break;} case 85: -#line 1197 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1197 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { (yyval.TypeList=yyvsp[-2].TypeList)->push_back(*yyvsp[0].TypeVal); delete yyvsp[0].TypeVal; ; break;} case 87: -#line 1203 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1203 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { (yyval.TypeList=yyvsp[-2].TypeList)->push_back(Type::VoidTy); ; break;} case 88: -#line 1206 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1206 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { (yyval.TypeList = new std::list())->push_back(Type::VoidTy); ; break;} case 89: -#line 1209 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1209 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { yyval.TypeList = new std::list(); ; break;} case 90: -#line 1219 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1219 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { // Nonempty unsized arr const ArrayType *ATy = dyn_cast(yyvsp[-3].TypeVal->get()); if (ATy == 0) @@ -2526,7 +2550,7 @@ ; break;} case 91: -#line 1244 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1244 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { const ArrayType *ATy = dyn_cast(yyvsp[-2].TypeVal->get()); if (ATy == 0) @@ -2542,7 +2566,7 @@ ; break;} case 92: -#line 1257 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1257 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { const ArrayType *ATy = dyn_cast(yyvsp[-2].TypeVal->get()); if (ATy == 0) @@ -2574,7 +2598,7 @@ ; break;} case 93: -#line 1286 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1286 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { // Nonempty unsized arr const PackedType *PTy = dyn_cast(yyvsp[-3].TypeVal->get()); if (PTy == 0) @@ -2602,7 +2626,7 @@ ; break;} case 94: -#line 1311 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1311 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { const StructType *STy = dyn_cast(yyvsp[-3].TypeVal->get()); if (STy == 0) @@ -2625,7 +2649,7 @@ ; break;} case 95: -#line 1331 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1331 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { const StructType *STy = dyn_cast(yyvsp[-2].TypeVal->get()); if (STy == 0) @@ -2640,7 +2664,7 @@ ; break;} case 96: -#line 1343 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1343 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { const PointerType *PTy = dyn_cast(yyvsp[-1].TypeVal->get()); if (PTy == 0) @@ -2652,14 +2676,14 @@ ; break;} case 97: -#line 1352 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1352 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { yyval.ConstVal = UndefValue::get(yyvsp[-1].TypeVal->get()); delete yyvsp[-1].TypeVal; ; break;} case 98: -#line 1356 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1356 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { const PointerType *Ty = dyn_cast(yyvsp[-1].TypeVal->get()); if (Ty == 0) @@ -2721,7 +2745,7 @@ ; break;} case 99: -#line 1415 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1415 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { if (yyvsp[-1].TypeVal->get() != yyvsp[0].ConstVal->getType()) ThrowException("Mismatched types for constant expression!"); @@ -2730,7 +2754,7 @@ ; break;} case 100: -#line 1421 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1421 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { const Type *Ty = yyvsp[-1].TypeVal->get(); if (isa(Ty) || Ty == Type::LabelTy || isa(Ty)) @@ -2740,7 +2764,7 @@ ; break;} case 101: -#line 1429 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1429 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { // integral constants if (!ConstantSInt::isValueValidForType(yyvsp[-1].PrimType, yyvsp[0].SInt64Val)) ThrowException("Constant value doesn't fit in type!"); @@ -2748,7 +2772,7 @@ ; break;} case 102: -#line 1434 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1434 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { // integral constants if (!ConstantUInt::isValueValidForType(yyvsp[-1].PrimType, yyvsp[0].UInt64Val)) ThrowException("Constant value doesn't fit in type!"); @@ -2756,19 +2780,19 @@ ; break;} case 103: -#line 1439 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1439 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { // Boolean constants yyval.ConstVal = ConstantBool::True; ; break;} case 104: -#line 1442 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1442 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { // Boolean constants yyval.ConstVal = ConstantBool::False; ; break;} case 105: -#line 1445 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1445 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { // Float & Double constants if (!ConstantFP::isValueValidForType(yyvsp[-1].PrimType, yyvsp[0].FPVal)) ThrowException("Floating point constant invalid for type!!"); @@ -2776,7 +2800,7 @@ ; break;} case 106: -#line 1452 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1452 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { if (!yyvsp[-3].ConstVal->getType()->isFirstClassType()) ThrowException("cast constant expression from a non-primitive type: '" + @@ -2789,7 +2813,7 @@ ; break;} case 107: -#line 1462 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1462 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { if (!isa(yyvsp[-2].ConstVal->getType())) ThrowException("GetElementPtr requires a pointer operand!"); @@ -2823,7 +2847,7 @@ ; break;} case 108: -#line 1493 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1493 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { if (yyvsp[-5].ConstVal->getType() != Type::BoolTy) ThrowException("Select condition must be of boolean type!"); @@ -2833,7 +2857,7 @@ ; break;} case 109: -#line 1500 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1500 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { if (yyvsp[-3].ConstVal->getType() != yyvsp[-1].ConstVal->getType()) ThrowException("Binary operator types must match!"); @@ -2857,7 +2881,7 @@ ; break;} case 110: -#line 1521 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1521 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { if (yyvsp[-3].ConstVal->getType() != yyvsp[-1].ConstVal->getType()) ThrowException("Logical operator types must match!"); @@ -2870,7 +2894,7 @@ ; break;} case 111: -#line 1531 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1531 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { if (yyvsp[-3].ConstVal->getType() != yyvsp[-1].ConstVal->getType()) ThrowException("setcc operand types must match!"); @@ -2878,7 +2902,7 @@ ; break;} case 112: -#line 1536 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1536 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { if (yyvsp[-1].ConstVal->getType() != Type::UByteTy) ThrowException("Shift count for shift constant must be unsigned byte!"); @@ -2888,7 +2912,7 @@ ; break;} case 113: -#line 1543 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1543 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { if (!isa(yyvsp[-3].ConstVal->getType())) ThrowException("First operand of extractelement must be " @@ -2899,60 +2923,74 @@ ; break;} case 114: -#line 1553 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1551 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { - (yyval.ConstVector = yyvsp[-2].ConstVector)->push_back(yyvsp[0].ConstVal); + yyval.ConstVal = ConstantExpr::getInsertElement(yyvsp[-5].ConstVal, yyvsp[-3].ConstVal, yyvsp[-1].ConstVal); ; break;} case 115: -#line 1556 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1554 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +{ + if (!ShuffleVectorInst::isValidOperands(yyvsp[-5].ConstVal, yyvsp[-3].ConstVal, yyvsp[-1].ConstVal)) + ThrowException("Invalid shufflevector operands!"); + yyval.ConstVal = ConstantExpr::getShuffleVector(yyvsp[-5].ConstVal, yyvsp[-3].ConstVal, yyvsp[-1].ConstVal); + ; + break;} +case 116: +#line 1562 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +{ + (yyval.ConstVector = yyvsp[-2].ConstVector)->push_back(yyvsp[0].ConstVal); + ; + break;} +case 117: +#line 1565 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { yyval.ConstVector = new std::vector(); yyval.ConstVector->push_back(yyvsp[0].ConstVal); ; break;} -case 116: -#line 1563 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +case 118: +#line 1572 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { yyval.BoolVal = false; ; break;} -case 117: -#line 1563 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +case 119: +#line 1572 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { yyval.BoolVal = true; ; break;} -case 118: -#line 1573 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +case 120: +#line 1582 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { yyval.ModuleVal = ParserResult = yyvsp[0].ModuleVal; CurModule.ModuleDone(); ; break;} -case 119: -#line 1580 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +case 121: +#line 1589 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { yyval.ModuleVal = yyvsp[-1].ModuleVal; CurFun.FunctionDone(); ; break;} -case 120: -#line 1584 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +case 122: +#line 1593 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { yyval.ModuleVal = yyvsp[-1].ModuleVal; ; break;} -case 121: -#line 1587 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +case 123: +#line 1596 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { yyval.ModuleVal = yyvsp[-3].ModuleVal; ; break;} -case 122: -#line 1590 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +case 124: +#line 1599 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { yyval.ModuleVal = yyvsp[-1].ModuleVal; ; break;} -case 123: -#line 1593 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +case 125: +#line 1602 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { yyval.ModuleVal = CurModule.CurrentModule; // Emit an error if there are any unresolved types left. @@ -2965,8 +3003,8 @@ } ; break;} -case 124: -#line 1606 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +case 126: +#line 1615 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { // Eagerly resolve types. This is not an optimization, this is a // requirement that is due to the fact that we could have this: @@ -2988,60 +3026,60 @@ delete yyvsp[0].TypeVal; ; break;} -case 125: -#line 1626 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +case 127: +#line 1635 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { // Function prototypes can be in const pool ; break;} -case 126: -#line 1628 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +case 128: +#line 1637 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { // Asm blocks can be in the const pool ; break;} -case 127: -#line 1630 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +case 129: +#line 1639 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { if (yyvsp[0].ConstVal == 0) ThrowException("Global value initializer is not a constant!"); CurGV = ParseGlobalVariable(yyvsp[-3].StrVal, yyvsp[-2].Linkage, yyvsp[-1].BoolVal, yyvsp[0].ConstVal->getType(), yyvsp[0].ConstVal); ; break;} -case 128: -#line 1633 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +case 130: +#line 1642 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { CurGV = 0; ; break;} -case 129: -#line 1636 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +case 131: +#line 1645 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { CurGV = ParseGlobalVariable(yyvsp[-3].StrVal, GlobalValue::ExternalLinkage, yyvsp[-1].BoolVal, *yyvsp[0].TypeVal, 0); delete yyvsp[0].TypeVal; ; break;} -case 130: -#line 1640 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +case 132: +#line 1649 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { CurGV = 0; ; break;} -case 131: -#line 1643 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +case 133: +#line 1652 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { ; break;} -case 132: -#line 1645 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +case 134: +#line 1654 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { ; break;} -case 133: -#line 1647 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +case 135: +#line 1656 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { ; break;} -case 134: -#line 1651 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +case 136: +#line 1660 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { const std::string &AsmSoFar = CurModule.CurrentModule->getModuleInlineAsm(); char *EndStr = UnEscapeLexed(yyvsp[0].StrVal, true); @@ -3054,22 +3092,22 @@ CurModule.CurrentModule->setModuleInlineAsm(AsmSoFar+"\n"+NewAsm); ; break;} -case 135: -#line 1663 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +case 137: +#line 1672 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { yyval.Endianness = Module::BigEndian; ; break;} -case 136: -#line 1664 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +case 138: +#line 1673 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { yyval.Endianness = Module::LittleEndian; ; break;} -case 137: -#line 1666 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +case 139: +#line 1675 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { CurModule.CurrentModule->setEndianness(yyvsp[0].Endianness); ; break;} -case 138: -#line 1669 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +case 140: +#line 1678 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { if (yyvsp[0].UInt64Val == 32) CurModule.CurrentModule->setPointerSize(Module::Pointer32); @@ -3079,89 +3117,89 @@ ThrowException("Invalid pointer size: '" + utostr(yyvsp[0].UInt64Val) + "'!"); ; break;} -case 139: -#line 1677 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +case 141: +#line 1686 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { CurModule.CurrentModule->setTargetTriple(yyvsp[0].StrVal); free(yyvsp[0].StrVal); ; break;} -case 141: -#line 1684 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +case 143: +#line 1693 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { CurModule.CurrentModule->addLibrary(yyvsp[0].StrVal); free(yyvsp[0].StrVal); ; break;} -case 142: -#line 1688 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +case 144: +#line 1697 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { CurModule.CurrentModule->addLibrary(yyvsp[0].StrVal); free(yyvsp[0].StrVal); ; break;} -case 143: -#line 1692 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +case 145: +#line 1701 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { ; break;} -case 147: -#line 1701 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +case 149: +#line 1710 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { yyval.StrVal = 0; ; break;} -case 148: -#line 1703 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +case 150: +#line 1712 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { if (*yyvsp[-1].TypeVal == Type::VoidTy) ThrowException("void typed arguments are invalid!"); yyval.ArgVal = new std::pair(yyvsp[-1].TypeVal, yyvsp[0].StrVal); ; break;} -case 149: -#line 1709 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +case 151: +#line 1718 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { yyval.ArgList = yyvsp[-2].ArgList; yyvsp[-2].ArgList->push_back(*yyvsp[0].ArgVal); delete yyvsp[0].ArgVal; ; break;} -case 150: -#line 1714 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +case 152: +#line 1723 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { yyval.ArgList = new std::vector >(); yyval.ArgList->push_back(*yyvsp[0].ArgVal); delete yyvsp[0].ArgVal; ; break;} -case 151: -#line 1720 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +case 153: +#line 1729 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { yyval.ArgList = yyvsp[0].ArgList; ; break;} -case 152: -#line 1723 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +case 154: +#line 1732 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { yyval.ArgList = yyvsp[-2].ArgList; yyval.ArgList->push_back(std::pair(new PATypeHolder(Type::VoidTy), 0)); ; break;} -case 153: -#line 1728 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +case 155: +#line 1737 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { yyval.ArgList = new std::vector >(); yyval.ArgList->push_back(std::make_pair(new PATypeHolder(Type::VoidTy), (char*)0)); ; break;} -case 154: -#line 1732 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +case 156: +#line 1741 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { yyval.ArgList = 0; ; break;} -case 155: -#line 1737 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +case 157: +#line 1746 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { UnEscapeLexed(yyvsp[-5].StrVal); std::string FunctionName(yyvsp[-5].StrVal); @@ -3247,8 +3285,8 @@ } ; break;} -case 158: -#line 1824 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +case 160: +#line 1833 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { yyval.FunctionVal = CurFun.CurrentFunction; @@ -3257,85 +3295,85 @@ yyval.FunctionVal->setLinkage(yyvsp[-2].Linkage); ; break;} -case 161: -#line 1834 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +case 163: +#line 1843 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { yyval.FunctionVal = yyvsp[-1].FunctionVal; ; break;} -case 162: -#line 1838 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +case 164: +#line 1847 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { CurFun.isDeclare = true; ; break;} -case 163: -#line 1838 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +case 165: +#line 1847 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { yyval.FunctionVal = CurFun.CurrentFunction; CurFun.FunctionDone(); ; break;} -case 164: -#line 1847 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +case 166: +#line 1856 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { yyval.BoolVal = false; ; break;} -case 165: -#line 1850 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +case 167: +#line 1859 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { yyval.BoolVal = true; ; break;} -case 166: -#line 1854 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +case 168: +#line 1863 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { // A reference to a direct constant yyval.ValIDVal = ValID::create(yyvsp[0].SInt64Val); ; break;} -case 167: -#line 1857 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +case 169: +#line 1866 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { yyval.ValIDVal = ValID::create(yyvsp[0].UInt64Val); ; break;} -case 168: -#line 1860 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +case 170: +#line 1869 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { // Perhaps it's an FP constant? yyval.ValIDVal = ValID::create(yyvsp[0].FPVal); ; break;} -case 169: -#line 1863 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +case 171: +#line 1872 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { yyval.ValIDVal = ValID::create(ConstantBool::True); ; break;} -case 170: -#line 1866 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +case 172: +#line 1875 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { yyval.ValIDVal = ValID::create(ConstantBool::False); ; break;} -case 171: -#line 1869 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +case 173: +#line 1878 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { yyval.ValIDVal = ValID::createNull(); ; break;} -case 172: -#line 1872 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +case 174: +#line 1881 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { yyval.ValIDVal = ValID::createUndef(); ; break;} -case 173: -#line 1875 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +case 175: +#line 1884 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { // A vector zero constant. yyval.ValIDVal = ValID::createZeroInit(); ; break;} -case 174: -#line 1878 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +case 176: +#line 1887 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { // Nonempty unsized packed vector const Type *ETy = (*yyvsp[-1].ConstVector)[0]->getType(); int NumElements = yyvsp[-1].ConstVector->size(); @@ -3361,14 +3399,14 @@ delete PTy; delete yyvsp[-1].ConstVector; ; break;} -case 175: -#line 1902 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +case 177: +#line 1911 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { yyval.ValIDVal = ValID::create(yyvsp[0].ConstVal); ; break;} -case 176: -#line 1905 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +case 178: +#line 1914 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { char *End = UnEscapeLexed(yyvsp[-2].StrVal, true); std::string AsmStr = std::string(yyvsp[-2].StrVal, End); @@ -3379,38 +3417,38 @@ free(yyvsp[0].StrVal); ; break;} -case 177: -#line 1918 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +case 179: +#line 1927 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { // Is it an integer reference...? yyval.ValIDVal = ValID::create(yyvsp[0].SIntVal); ; break;} -case 178: -#line 1921 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +case 180: +#line 1930 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { // Is it a named reference...? yyval.ValIDVal = ValID::create(yyvsp[0].StrVal); ; break;} -case 181: -#line 1932 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +case 183: +#line 1941 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { yyval.ValueVal = getVal(*yyvsp[-1].TypeVal, yyvsp[0].ValIDVal); delete yyvsp[-1].TypeVal; ; break;} -case 182: -#line 1936 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +case 184: +#line 1945 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { yyval.FunctionVal = yyvsp[-1].FunctionVal; ; break;} -case 183: -#line 1939 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +case 185: +#line 1948 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { // Do not allow functions with 0 basic blocks yyval.FunctionVal = yyvsp[-1].FunctionVal; ; break;} -case 184: -#line 1947 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +case 186: +#line 1956 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { setValueName(yyvsp[0].TermInstVal, yyvsp[-1].StrVal); InsertValue(yyvsp[0].TermInstVal); @@ -3420,15 +3458,15 @@ yyval.BasicBlockVal = yyvsp[-2].BasicBlockVal; ; break;} -case 185: -#line 1956 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +case 187: +#line 1965 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { yyvsp[-1].BasicBlockVal->getInstList().push_back(yyvsp[0].InstVal); yyval.BasicBlockVal = yyvsp[-1].BasicBlockVal; ; break;} -case 186: -#line 1960 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +case 188: +#line 1969 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { yyval.BasicBlockVal = CurBB = getBBVal(ValID::create((int)CurFun.NextBBNum++), true); @@ -3440,8 +3478,8 @@ BBL.splice(BBL.end(), BBL, yyval.BasicBlockVal); ; break;} -case 187: -#line 1970 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +case 189: +#line 1979 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { yyval.BasicBlockVal = CurBB = getBBVal(ValID::create(yyvsp[0].StrVal), true); @@ -3453,32 +3491,32 @@ BBL.splice(BBL.end(), BBL, yyval.BasicBlockVal); ; break;} -case 188: -#line 1981 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +case 190: +#line 1990 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { // Return with a result... yyval.TermInstVal = new ReturnInst(yyvsp[0].ValueVal); ; break;} -case 189: -#line 1984 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +case 191: +#line 1993 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { // Return with no result... yyval.TermInstVal = new ReturnInst(); ; break;} -case 190: -#line 1987 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +case 192: +#line 1996 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { // Unconditional Branch... yyval.TermInstVal = new BranchInst(getBBVal(yyvsp[0].ValIDVal)); ; break;} -case 191: -#line 1990 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +case 193: +#line 1999 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { yyval.TermInstVal = new BranchInst(getBBVal(yyvsp[-3].ValIDVal), getBBVal(yyvsp[0].ValIDVal), getVal(Type::BoolTy, yyvsp[-6].ValIDVal)); ; break;} -case 192: -#line 1993 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +case 194: +#line 2002 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { SwitchInst *S = new SwitchInst(getVal(yyvsp[-7].PrimType, yyvsp[-6].ValIDVal), getBBVal(yyvsp[-3].ValIDVal), yyvsp[-1].JumpTable->size()); yyval.TermInstVal = S; @@ -3494,15 +3532,15 @@ delete yyvsp[-1].JumpTable; ; break;} -case 193: -#line 2007 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +case 195: +#line 2016 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { SwitchInst *S = new SwitchInst(getVal(yyvsp[-6].PrimType, yyvsp[-5].ValIDVal), getBBVal(yyvsp[-2].ValIDVal), 0); yyval.TermInstVal = S; ; break;} -case 194: -#line 2012 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +case 196: +#line 2021 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { const PointerType *PFTy; const FunctionType *Ty; @@ -3556,20 +3594,20 @@ delete yyvsp[-7].ValueList; ; break;} -case 195: -#line 2064 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +case 197: +#line 2073 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { yyval.TermInstVal = new UnwindInst(); ; break;} -case 196: -#line 2067 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +case 198: +#line 2076 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { yyval.TermInstVal = new UnreachableInst(); ; break;} -case 197: -#line 2073 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +case 199: +#line 2082 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { yyval.JumpTable = yyvsp[-5].JumpTable; Constant *V = cast(getValNonImprovising(yyvsp[-4].PrimType, yyvsp[-3].ValIDVal)); @@ -3579,8 +3617,8 @@ yyval.JumpTable->push_back(std::make_pair(V, getBBVal(yyvsp[0].ValIDVal))); ; break;} -case 198: -#line 2081 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +case 200: +#line 2090 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { yyval.JumpTable = new std::vector >(); Constant *V = cast(getValNonImprovising(yyvsp[-4].PrimType, yyvsp[-3].ValIDVal)); @@ -3591,8 +3629,8 @@ yyval.JumpTable->push_back(std::make_pair(V, getBBVal(yyvsp[0].ValIDVal))); ; break;} -case 199: -#line 2091 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +case 201: +#line 2100 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { // Is this definition named?? if so, assign the name... setValueName(yyvsp[0].InstVal, yyvsp[-1].StrVal); @@ -3600,54 +3638,54 @@ yyval.InstVal = yyvsp[0].InstVal; ; break;} -case 200: -#line 2098 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +case 202: +#line 2107 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { // Used for PHI nodes yyval.PHIList = new std::list >(); yyval.PHIList->push_back(std::make_pair(getVal(*yyvsp[-5].TypeVal, yyvsp[-3].ValIDVal), getBBVal(yyvsp[-1].ValIDVal))); delete yyvsp[-5].TypeVal; ; break;} -case 201: -#line 2103 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +case 203: +#line 2112 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { yyval.PHIList = yyvsp[-6].PHIList; yyvsp[-6].PHIList->push_back(std::make_pair(getVal(yyvsp[-6].PHIList->front().first->getType(), yyvsp[-3].ValIDVal), getBBVal(yyvsp[-1].ValIDVal))); ; break;} -case 202: -#line 2110 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +case 204: +#line 2119 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { // Used for call statements, and memory insts... yyval.ValueList = new std::vector(); yyval.ValueList->push_back(yyvsp[0].ValueVal); ; break;} -case 203: -#line 2114 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +case 205: +#line 2123 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { yyval.ValueList = yyvsp[-2].ValueList; yyvsp[-2].ValueList->push_back(yyvsp[0].ValueVal); ; break;} -case 205: -#line 2120 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +case 207: +#line 2129 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { yyval.ValueList = 0; ; break;} -case 206: -#line 2122 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +case 208: +#line 2131 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { yyval.BoolVal = true; ; break;} -case 207: -#line 2125 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +case 209: +#line 2134 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { yyval.BoolVal = false; ; break;} -case 208: -#line 2131 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +case 210: +#line 2140 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { if (!(*yyvsp[-3].TypeVal)->isInteger() && !(*yyvsp[-3].TypeVal)->isFloatingPoint() && !isa((*yyvsp[-3].TypeVal).get())) @@ -3661,8 +3699,8 @@ delete yyvsp[-3].TypeVal; ; break;} -case 209: -#line 2143 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +case 211: +#line 2152 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { if (!(*yyvsp[-3].TypeVal)->isIntegral()) { if (!isa(yyvsp[-3].TypeVal->get()) || @@ -3675,8 +3713,8 @@ delete yyvsp[-3].TypeVal; ; break;} -case 210: -#line 2154 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +case 212: +#line 2163 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { if(isa((*yyvsp[-3].TypeVal).get())) { ThrowException( @@ -3688,8 +3726,8 @@ delete yyvsp[-3].TypeVal; ; break;} -case 211: -#line 2164 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +case 213: +#line 2173 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { std::cerr << "WARNING: Use of eliminated 'not' instruction:" << " Replacing with 'xor'.\n"; @@ -3703,8 +3741,8 @@ ThrowException("Could not create a xor instruction!"); ; break;} -case 212: -#line 2176 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +case 214: +#line 2185 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { if (yyvsp[0].ValueVal->getType() != Type::UByteTy) ThrowException("Shift amount must be ubyte!"); @@ -3713,8 +3751,8 @@ yyval.InstVal = new ShiftInst(yyvsp[-3].OtherOpVal, yyvsp[-2].ValueVal, yyvsp[0].ValueVal); ; break;} -case 213: -#line 2183 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +case 215: +#line 2192 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { if (!yyvsp[0].TypeVal->get()->isFirstClassType()) ThrowException("cast instruction to a non-primitive type: '" + @@ -3723,8 +3761,8 @@ delete yyvsp[0].TypeVal; ; break;} -case 214: -#line 2190 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +case 216: +#line 2199 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { if (yyvsp[-4].ValueVal->getType() != Type::BoolTy) ThrowException("select condition must be boolean!"); @@ -3733,16 +3771,16 @@ yyval.InstVal = new SelectInst(yyvsp[-4].ValueVal, yyvsp[-2].ValueVal, yyvsp[0].ValueVal); ; break;} -case 215: -#line 2197 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +case 217: +#line 2206 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { NewVarArgs = true; yyval.InstVal = new VAArgInst(yyvsp[-2].ValueVal, *yyvsp[0].TypeVal); delete yyvsp[0].TypeVal; ; break;} -case 216: -#line 2202 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +case 218: +#line 2211 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { ObsoleteVarArgs = true; const Type* ArgTy = yyvsp[-2].ValueVal->getType(); @@ -3763,8 +3801,8 @@ delete yyvsp[0].TypeVal; ; break;} -case 217: -#line 2221 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +case 219: +#line 2230 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { ObsoleteVarArgs = true; const Type* ArgTy = yyvsp[-2].ValueVal->getType(); @@ -3788,8 +3826,8 @@ delete yyvsp[0].TypeVal; ; break;} -case 218: -#line 2243 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +case 220: +#line 2252 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { if (!isa(yyvsp[-2].ValueVal->getType())) ThrowException("First operand of extractelement must be " @@ -3799,8 +3837,8 @@ yyval.InstVal = new ExtractElementInst(yyvsp[-2].ValueVal, yyvsp[0].ValueVal); ; break;} -case 219: -#line 2251 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +case 221: +#line 2260 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { if (!isa(yyvsp[-4].ValueVal->getType())) ThrowException("First operand of insertelement must be " @@ -3814,16 +3852,16 @@ yyval.InstVal = new InsertElementInst(yyvsp[-4].ValueVal, yyvsp[-2].ValueVal, yyvsp[0].ValueVal); ; break;} -case 220: -#line 2263 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +case 222: +#line 2272 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { - if (!ShuffleVectorInst::isValidOperands(yyvsp[-4].ValueVal, yyvsp[-2].ValueVal, yyvsp[0].ValueVal)) - ThrowException("Invalid shufflevector operands!"); + if (!ShuffleVectorInst::isValidOperands(yyvsp[-4].ValueVal, yyvsp[-2].ValueVal, yyvsp[0].ValueVal)) + ThrowException("Invalid shufflevector operands!"); yyval.InstVal = new ShuffleVectorInst(yyvsp[-4].ValueVal, yyvsp[-2].ValueVal, yyvsp[0].ValueVal); ; break;} -case 221: -#line 2268 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +case 223: +#line 2277 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { const Type *Ty = yyvsp[0].PHIList->front().first->getType(); if (!Ty->isFirstClassType()) @@ -3839,8 +3877,8 @@ delete yyvsp[0].PHIList; // Free the list... ; break;} -case 222: -#line 2282 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +case 224: +#line 2291 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { const PointerType *PFTy; const FunctionType *Ty; @@ -3899,66 +3937,66 @@ delete yyvsp[-1].ValueList; ; break;} -case 223: -#line 2339 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +case 225: +#line 2348 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { yyval.InstVal = yyvsp[0].InstVal; ; break;} -case 224: -#line 2345 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +case 226: +#line 2354 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { yyval.ValueList = yyvsp[0].ValueList; ; break;} -case 225: -#line 2347 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +case 227: +#line 2356 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { yyval.ValueList = new std::vector(); ; break;} -case 226: -#line 2351 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +case 228: +#line 2360 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { yyval.BoolVal = true; ; break;} -case 227: -#line 2354 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +case 229: +#line 2363 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { yyval.BoolVal = false; ; break;} -case 228: -#line 2360 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +case 230: +#line 2369 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { yyval.InstVal = new MallocInst(*yyvsp[-1].TypeVal, 0, yyvsp[0].UIntVal); delete yyvsp[-1].TypeVal; ; break;} -case 229: -#line 2364 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +case 231: +#line 2373 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { yyval.InstVal = new MallocInst(*yyvsp[-4].TypeVal, getVal(yyvsp[-2].PrimType, yyvsp[-1].ValIDVal), yyvsp[0].UIntVal); delete yyvsp[-4].TypeVal; ; break;} -case 230: -#line 2368 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +case 232: +#line 2377 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { yyval.InstVal = new AllocaInst(*yyvsp[-1].TypeVal, 0, yyvsp[0].UIntVal); delete yyvsp[-1].TypeVal; ; break;} -case 231: -#line 2372 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +case 233: +#line 2381 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { yyval.InstVal = new AllocaInst(*yyvsp[-4].TypeVal, getVal(yyvsp[-2].PrimType, yyvsp[-1].ValIDVal), yyvsp[0].UIntVal); delete yyvsp[-4].TypeVal; ; break;} -case 232: -#line 2376 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +case 234: +#line 2385 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { if (!isa(yyvsp[0].ValueVal->getType())) ThrowException("Trying to free nonpointer type " + @@ -3966,8 +4004,8 @@ yyval.InstVal = new FreeInst(yyvsp[0].ValueVal); ; break;} -case 233: -#line 2383 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +case 235: +#line 2392 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { if (!isa(yyvsp[-1].TypeVal->get())) ThrowException("Can't load from nonpointer type: " + @@ -3979,8 +4017,8 @@ delete yyvsp[-1].TypeVal; ; break;} -case 234: -#line 2393 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +case 236: +#line 2402 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { const PointerType *PT = dyn_cast(yyvsp[-1].TypeVal->get()); if (!PT) @@ -3995,8 +4033,8 @@ delete yyvsp[-1].TypeVal; ; break;} -case 235: -#line 2406 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +case 237: +#line 2415 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { if (!isa(yyvsp[-2].TypeVal->get())) ThrowException("getelementptr insn requires pointer operand!"); @@ -4241,7 +4279,7 @@ } return 1; } -#line 2429 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +#line 2438 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" int yyerror(const char *ErrorMsg) { std::string where Index: llvm/lib/AsmParser/llvmAsmParser.y.cvs diff -u llvm/lib/AsmParser/llvmAsmParser.y.cvs:1.3 llvm/lib/AsmParser/llvmAsmParser.y.cvs:1.4 --- llvm/lib/AsmParser/llvmAsmParser.y.cvs:1.3 Fri Apr 7 20:18:56 2006 +++ llvm/lib/AsmParser/llvmAsmParser.y.cvs Fri Apr 7 22:55:17 2006 @@ -1547,8 +1547,17 @@ if ($5->getType() != Type::UIntTy) ThrowException("Second operand of extractelement must be uint!"); $$ = ConstantExpr::getExtractElement($3, $5); + } + | INSERTELEMENT '(' ConstVal ',' ConstVal ',' ConstVal ')' { + $$ = ConstantExpr::getInsertElement($3, $5, $7); + } + | SHUFFLEVECTOR '(' ConstVal ',' ConstVal ',' ConstVal ')' { + if (!ShuffleVectorInst::isValidOperands($3, $5, $7)) + ThrowException("Invalid shufflevector operands!"); + $$ = ConstantExpr::getShuffleVector($3, $5, $7); }; + // ConstVector - A list of comma separated constants. ConstVector : ConstVector ',' ConstVal { ($$ = $1)->push_back($3); @@ -2261,8 +2270,8 @@ $$ = new InsertElementInst($2, $4, $6); } | SHUFFLEVECTOR ResolvedVal ',' ResolvedVal ',' ResolvedVal { - if (!ShuffleVectorInst::isValidOperands($2, $4, $6)) - ThrowException("Invalid shufflevector operands!"); + if (!ShuffleVectorInst::isValidOperands($2, $4, $6)) + ThrowException("Invalid shufflevector operands!"); $$ = new ShuffleVectorInst($2, $4, $6); } | PHI_TOK PHIList { From lattner at cs.uiuc.edu Fri Apr 7 23:05:06 2006 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Fri, 7 Apr 2006 23:05:06 -0500 Subject: [llvm-commits] CVS: llvm/include/llvm/Instructions.h Message-ID: <200604080405.XAA20572@zion.cs.uiuc.edu> Changes in directory llvm/include/llvm: Instructions.h updated: 1.32 -> 1.33 --- Log message: Add methods to check insert/extract element instructions for validity --- Diffs of the changes: (+10 -1) Instructions.h | 11 ++++++++++- 1 files changed, 10 insertions(+), 1 deletion(-) Index: llvm/include/llvm/Instructions.h diff -u llvm/include/llvm/Instructions.h:1.32 llvm/include/llvm/Instructions.h:1.33 --- llvm/include/llvm/Instructions.h:1.32 Fri Apr 7 20:15:18 2006 +++ llvm/include/llvm/Instructions.h Fri Apr 7 23:04:54 2006 @@ -738,6 +738,10 @@ ExtractElementInst(Value *Vec, Value *Idx, const std::string &Name, BasicBlock *InsertAtEnd); + /// isValidOperands - Return true if an extractelement instruction can be + /// formed with the specified operands. + static bool isValidOperands(const Value *Vec, const Value *Idx); + virtual ExtractElementInst *clone() const; virtual bool mayWriteToMemory() const { return false; } @@ -785,6 +789,11 @@ InsertElementInst(Value *Vec, Value *NewElt, Value *Idx, const std::string &Name, BasicBlock *InsertAtEnd); + /// isValidOperands - Return true if an insertelement instruction can be + /// formed with the specified operands. + static bool isValidOperands(const Value *Vec, const Value *NewElt, + const Value *Idx); + virtual InsertElementInst *clone() const; virtual bool mayWriteToMemory() const { return false; } @@ -832,7 +841,7 @@ ShuffleVectorInst(Value *V1, Value *V2, Value *Mask, const std::string &Name, BasicBlock *InsertAtEnd); - /// isValidOperands - Return true if a value shufflevector instruction can be + /// isValidOperands - Return true if a shufflevector instruction can be /// formed with the specified operands. static bool isValidOperands(const Value *V1, const Value *V2, const Value *Mask); From lattner at cs.uiuc.edu Fri Apr 7 23:06:01 2006 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Fri, 7 Apr 2006 23:06:01 -0500 Subject: [llvm-commits] CVS: llvm/lib/VMCore/Instructions.cpp Message-ID: <200604080406.XAA20638@zion.cs.uiuc.edu> Changes in directory llvm/lib/VMCore: Instructions.cpp updated: 1.33 -> 1.34 --- Log message: Add methods to check insertelement/extractelement instructions for validity, check validity when instructions are created. --- Diffs of the changes: (+37 -6) Instructions.cpp | 43 +++++++++++++++++++++++++++++++++++++------ 1 files changed, 37 insertions(+), 6 deletions(-) Index: llvm/lib/VMCore/Instructions.cpp diff -u llvm/lib/VMCore/Instructions.cpp:1.33 llvm/lib/VMCore/Instructions.cpp:1.34 --- llvm/lib/VMCore/Instructions.cpp:1.33 Fri Apr 7 20:18:18 2006 +++ llvm/lib/VMCore/Instructions.cpp Fri Apr 7 23:05:48 2006 @@ -804,6 +804,8 @@ Instruction *InsertBef) : Instruction(cast(Val->getType())->getElementType(), ExtractElement, Ops, 2, Name, InsertBef) { + assert(isValidOperands(Val, Index) && + "Invalid extractelement instruction operands!"); Ops[0].init(Val, this); Ops[1].init(Index, this); } @@ -813,32 +815,61 @@ BasicBlock *InsertAE) : Instruction(cast(Val->getType())->getElementType(), ExtractElement, Ops, 2, Name, InsertAE) { + assert(isValidOperands(Val, Index) && + "Invalid extractelement instruction operands!"); + Ops[0].init(Val, this); Ops[1].init(Index, this); } +bool ExtractElementInst::isValidOperands(const Value *Val, const Value *Index) { + if (!isa(Val->getType()) || Index->getType() != Type::UIntTy) + return false; + return true; +} + + //===----------------------------------------------------------------------===// // InsertElementInst Implementation //===----------------------------------------------------------------------===// -InsertElementInst::InsertElementInst(Value *Val, Value *Elt, Value *Index, +InsertElementInst::InsertElementInst(Value *Vec, Value *Elt, Value *Index, const std::string &Name, Instruction *InsertBef) - : Instruction(Val->getType(), InsertElement, Ops, 3, Name, InsertBef) { - Ops[0].init(Val, this); + : Instruction(Vec->getType(), InsertElement, Ops, 3, Name, InsertBef) { + assert(isValidOperands(Vec, Elt, Index) && + "Invalid insertelement instruction operands!"); + Ops[0].init(Vec, this); Ops[1].init(Elt, this); Ops[2].init(Index, this); } -InsertElementInst::InsertElementInst(Value *Val, Value *Elt, Value *Index, +InsertElementInst::InsertElementInst(Value *Vec, Value *Elt, Value *Index, const std::string &Name, BasicBlock *InsertAE) - : Instruction(Val->getType(), InsertElement, Ops, 3, Name, InsertAE) { - Ops[0].init(Val, this); + : Instruction(Vec->getType(), InsertElement, Ops, 3, Name, InsertAE) { + assert(isValidOperands(Vec, Elt, Index) && + "Invalid insertelement instruction operands!"); + + Ops[0].init(Vec, this); Ops[1].init(Elt, this); Ops[2].init(Index, this); } +bool InsertElementInst::isValidOperands(const Value *Vec, const Value *Elt, + const Value *Index) { + if (!isa(Vec->getType())) + return false; // First operand of insertelement must be packed type. + + if (Elt->getType() != cast(Vec->getType())->getElementType()) + return false;// Second operand of insertelement must be packed element type. + + if (Index->getType() != Type::UIntTy) + return false; // Third operand of insertelement must be uint. + return true; +} + + //===----------------------------------------------------------------------===// // ShuffleVectorInst Implementation //===----------------------------------------------------------------------===// From lattner at cs.uiuc.edu Fri Apr 7 23:08:05 2006 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Fri, 7 Apr 2006 23:08:05 -0500 Subject: [llvm-commits] CVS: llvm/lib/VMCore/Verifier.cpp Message-ID: <200604080408.XAA20723@zion.cs.uiuc.edu> Changes in directory llvm/lib/VMCore: Verifier.cpp updated: 1.153 -> 1.154 --- Log message: Use the isValidOperands helper instead of duplicating checking code --- Diffs of the changes: (+7 -16) Verifier.cpp | 23 +++++++---------------- 1 files changed, 7 insertions(+), 16 deletions(-) Index: llvm/lib/VMCore/Verifier.cpp diff -u llvm/lib/VMCore/Verifier.cpp:1.153 llvm/lib/VMCore/Verifier.cpp:1.154 --- llvm/lib/VMCore/Verifier.cpp:1.153 Fri Apr 7 20:18:18 2006 +++ llvm/lib/VMCore/Verifier.cpp Fri Apr 7 23:07:52 2006 @@ -540,26 +540,17 @@ } void Verifier::visitExtractElementInst(ExtractElementInst &EI) { - Assert1(isa(EI.getOperand(0)->getType()), - "First operand to extractelement must be packed type!", &EI); - Assert1(EI.getOperand(1)->getType() == Type::UIntTy, - "Second operand to extractelement must be uint type!", &EI); - Assert1(EI.getType() == - cast(EI.getOperand(0)->getType())->getElementType(), - "Extractelement return type must match " - "first operand element type!", &EI); + Assert1(ExtractElementInst::isValidOperands(EI.getOperand(0), + EI.getOperand(1)), + "Invalid extractelement operands!", &EI); visitInstruction(EI); } void Verifier::visitInsertElementInst(InsertElementInst &IE) { - Assert1(isa(IE.getOperand(0)->getType()), - "First operand to insertelement must be packed type!", &IE); - Assert1(IE.getOperand(1)->getType() == - cast(IE.getOperand(0)->getType())->getElementType(), - "Second operand to insertelement must match " - "first operand element type!", &IE); - Assert1(IE.getOperand(2)->getType() == Type::UIntTy, - "Third operand to insertelement must be uint type!", &IE); + Assert1(InsertElementInst::isValidOperands(IE.getOperand(0), + IE.getOperand(1), + IE.getOperand(2)), + "Invalid insertelement operands!", &IE); visitInstruction(IE); } From lattner at cs.uiuc.edu Fri Apr 7 23:08:45 2006 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Fri, 7 Apr 2006 23:08:45 -0500 Subject: [llvm-commits] CVS: llvm/lib/AsmParser/llvmAsmParser.y Message-ID: <200604080408.XAA20759@zion.cs.uiuc.edu> Changes in directory llvm/lib/AsmParser: llvmAsmParser.y updated: 1.252 -> 1.253 --- Log message: Use isValidOperands instead of duplicating or eliding checks. --- Diffs of the changes: (+8 -19) llvmAsmParser.y | 27 ++++++++------------------- 1 files changed, 8 insertions(+), 19 deletions(-) Index: llvm/lib/AsmParser/llvmAsmParser.y diff -u llvm/lib/AsmParser/llvmAsmParser.y:1.252 llvm/lib/AsmParser/llvmAsmParser.y:1.253 --- llvm/lib/AsmParser/llvmAsmParser.y:1.252 Fri Apr 7 22:53:34 2006 +++ llvm/lib/AsmParser/llvmAsmParser.y Fri Apr 7 23:08:32 2006 @@ -1541,14 +1541,13 @@ $$ = ConstantExpr::get($1, $3, $5); } | EXTRACTELEMENT '(' ConstVal ',' ConstVal ')' { - if (!isa($3->getType())) - ThrowException("First operand of extractelement must be " - "packed type!"); - if ($5->getType() != Type::UIntTy) - ThrowException("Second operand of extractelement must be uint!"); + if (!ExtractElementInst::isValidOperands($3, $5)) + ThrowException("Invalid extractelement operands!"); $$ = ConstantExpr::getExtractElement($3, $5); } | INSERTELEMENT '(' ConstVal ',' ConstVal ',' ConstVal ')' { + if (!InsertElementInst::isValidOperands($3, $5, $7)) + ThrowException("Invalid insertelement operands!"); $$ = ConstantExpr::getInsertElement($3, $5, $7); } | SHUFFLEVECTOR '(' ConstVal ',' ConstVal ',' ConstVal ')' { @@ -2250,23 +2249,13 @@ delete $4; } | EXTRACTELEMENT ResolvedVal ',' ResolvedVal { - if (!isa($2->getType())) - ThrowException("First operand of extractelement must be " - "packed type!"); - if ($4->getType() != Type::UIntTy) - ThrowException("Second operand of extractelement must be uint!"); + if (!ExtractElementInst::isValidOperands($2, $4)) + ThrowException("Invalid extractelement operands!"); $$ = new ExtractElementInst($2, $4); } | INSERTELEMENT ResolvedVal ',' ResolvedVal ',' ResolvedVal { - if (!isa($2->getType())) - ThrowException("First operand of insertelement must be " - "packed type!"); - if ($4->getType() != - cast($2->getType())->getElementType()) - ThrowException("Second operand of insertelement must be " - "packed element type!"); - if ($6->getType() != Type::UIntTy) - ThrowException("Third operand of insertelement must be uint!"); + if (!InsertElementInst::isValidOperands($2, $4, $6)) + ThrowException("Invalid insertelement operands!"); $$ = new InsertElementInst($2, $4, $6); } | SHUFFLEVECTOR ResolvedVal ',' ResolvedVal ',' ResolvedVal { From lattner at cs.uiuc.edu Fri Apr 7 23:09:15 2006 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Fri, 7 Apr 2006 23:09:15 -0500 Subject: [llvm-commits] CVS: llvm/lib/AsmParser/llvmAsmParser.cpp.cvs llvmAsmParser.y.cvs Message-ID: <200604080409.XAA20839@zion.cs.uiuc.edu> Changes in directory llvm/lib/AsmParser: llvmAsmParser.cpp.cvs updated: 1.4 -> 1.5 llvmAsmParser.y.cvs updated: 1.4 -> 1.5 --- Log message: Regenerate --- Diffs of the changes: (+143 -165) llvmAsmParser.cpp.cvs | 281 ++++++++++++++++++++++++-------------------------- llvmAsmParser.y.cvs | 27 +--- 2 files changed, 143 insertions(+), 165 deletions(-) Index: llvm/lib/AsmParser/llvmAsmParser.cpp.cvs diff -u llvm/lib/AsmParser/llvmAsmParser.cpp.cvs:1.4 llvm/lib/AsmParser/llvmAsmParser.cpp.cvs:1.5 --- llvm/lib/AsmParser/llvmAsmParser.cpp.cvs:1.4 Fri Apr 7 22:55:17 2006 +++ llvm/lib/AsmParser/llvmAsmParser.cpp.cvs Fri Apr 7 23:09:02 2006 @@ -1206,19 +1206,19 @@ 1173, 1182, 1185, 1193, 1197, 1202, 1203, 1206, 1209, 1219, 1244, 1257, 1286, 1311, 1331, 1343, 1352, 1356, 1415, 1421, 1429, 1434, 1439, 1442, 1445, 1452, 1462, 1493, 1500, 1521, - 1531, 1536, 1543, 1551, 1554, 1562, 1565, 1572, 1572, 1582, - 1589, 1593, 1596, 1599, 1602, 1615, 1635, 1637, 1639, 1642, - 1645, 1649, 1652, 1654, 1656, 1660, 1672, 1673, 1675, 1678, - 1686, 1691, 1693, 1697, 1701, 1709, 1709, 1710, 1710, 1712, - 1718, 1723, 1729, 1732, 1737, 1741, 1745, 1831, 1831, 1833, - 1841, 1841, 1843, 1847, 1847, 1856, 1859, 1863, 1866, 1869, - 1872, 1875, 1878, 1881, 1884, 1887, 1911, 1914, 1927, 1930, - 1935, 1935, 1941, 1945, 1948, 1956, 1965, 1969, 1979, 1990, - 1993, 1996, 1999, 2002, 2016, 2020, 2073, 2076, 2082, 2090, - 2100, 2107, 2112, 2119, 2123, 2129, 2129, 2131, 2134, 2140, - 2152, 2163, 2173, 2185, 2192, 2199, 2206, 2211, 2230, 2252, - 2260, 2272, 2277, 2291, 2348, 2354, 2356, 2360, 2363, 2369, - 2373, 2377, 2381, 2385, 2392, 2402, 2415 + 1531, 1536, 1543, 1548, 1553, 1561, 1564, 1571, 1571, 1581, + 1588, 1592, 1595, 1598, 1601, 1614, 1634, 1636, 1638, 1641, + 1644, 1648, 1651, 1653, 1655, 1659, 1671, 1672, 1674, 1677, + 1685, 1690, 1692, 1696, 1700, 1708, 1708, 1709, 1709, 1711, + 1717, 1722, 1728, 1731, 1736, 1740, 1744, 1830, 1830, 1832, + 1840, 1840, 1842, 1846, 1846, 1855, 1858, 1862, 1865, 1868, + 1871, 1874, 1877, 1880, 1883, 1886, 1910, 1913, 1926, 1929, + 1934, 1934, 1940, 1944, 1947, 1955, 1964, 1968, 1978, 1989, + 1992, 1995, 1998, 2001, 2015, 2019, 2072, 2075, 2081, 2089, + 2099, 2106, 2111, 2118, 2122, 2128, 2128, 2130, 2133, 2139, + 2151, 2162, 2172, 2184, 2191, 2198, 2205, 2210, 2229, 2251, + 2256, 2261, 2266, 2280, 2337, 2343, 2345, 2349, 2352, 2358, + 2362, 2366, 2370, 2374, 2381, 2391, 2404 }; #endif @@ -2914,22 +2914,21 @@ case 113: #line 1543 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { - if (!isa(yyvsp[-3].ConstVal->getType())) - ThrowException("First operand of extractelement must be " - "packed type!"); - if (yyvsp[-1].ConstVal->getType() != Type::UIntTy) - ThrowException("Second operand of extractelement must be uint!"); + if (!ExtractElementInst::isValidOperands(yyvsp[-3].ConstVal, yyvsp[-1].ConstVal)) + ThrowException("Invalid extractelement operands!"); yyval.ConstVal = ConstantExpr::getExtractElement(yyvsp[-3].ConstVal, yyvsp[-1].ConstVal); ; break;} case 114: -#line 1551 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1548 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { + if (!InsertElementInst::isValidOperands(yyvsp[-5].ConstVal, yyvsp[-3].ConstVal, yyvsp[-1].ConstVal)) + ThrowException("Invalid insertelement operands!"); yyval.ConstVal = ConstantExpr::getInsertElement(yyvsp[-5].ConstVal, yyvsp[-3].ConstVal, yyvsp[-1].ConstVal); ; break;} case 115: -#line 1554 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1553 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { if (!ShuffleVectorInst::isValidOperands(yyvsp[-5].ConstVal, yyvsp[-3].ConstVal, yyvsp[-1].ConstVal)) ThrowException("Invalid shufflevector operands!"); @@ -2937,60 +2936,60 @@ ; break;} case 116: -#line 1562 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1561 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { (yyval.ConstVector = yyvsp[-2].ConstVector)->push_back(yyvsp[0].ConstVal); ; break;} case 117: -#line 1565 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1564 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { yyval.ConstVector = new std::vector(); yyval.ConstVector->push_back(yyvsp[0].ConstVal); ; break;} case 118: -#line 1572 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1571 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { yyval.BoolVal = false; ; break;} case 119: -#line 1572 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1571 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { yyval.BoolVal = true; ; break;} case 120: -#line 1582 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1581 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { yyval.ModuleVal = ParserResult = yyvsp[0].ModuleVal; CurModule.ModuleDone(); ; break;} case 121: -#line 1589 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1588 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { yyval.ModuleVal = yyvsp[-1].ModuleVal; CurFun.FunctionDone(); ; break;} case 122: -#line 1593 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1592 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { yyval.ModuleVal = yyvsp[-1].ModuleVal; ; break;} case 123: -#line 1596 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1595 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { yyval.ModuleVal = yyvsp[-3].ModuleVal; ; break;} case 124: -#line 1599 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1598 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { yyval.ModuleVal = yyvsp[-1].ModuleVal; ; break;} case 125: -#line 1602 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1601 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { yyval.ModuleVal = CurModule.CurrentModule; // Emit an error if there are any unresolved types left. @@ -3004,7 +3003,7 @@ ; break;} case 126: -#line 1615 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1614 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { // Eagerly resolve types. This is not an optimization, this is a // requirement that is due to the fact that we could have this: @@ -3027,30 +3026,30 @@ ; break;} case 127: -#line 1635 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1634 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { // Function prototypes can be in const pool ; break;} case 128: -#line 1637 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1636 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { // Asm blocks can be in the const pool ; break;} case 129: -#line 1639 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1638 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { if (yyvsp[0].ConstVal == 0) ThrowException("Global value initializer is not a constant!"); CurGV = ParseGlobalVariable(yyvsp[-3].StrVal, yyvsp[-2].Linkage, yyvsp[-1].BoolVal, yyvsp[0].ConstVal->getType(), yyvsp[0].ConstVal); ; break;} case 130: -#line 1642 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1641 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { CurGV = 0; ; break;} case 131: -#line 1645 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1644 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { CurGV = ParseGlobalVariable(yyvsp[-3].StrVal, GlobalValue::ExternalLinkage, yyvsp[-1].BoolVal, *yyvsp[0].TypeVal, 0); @@ -3058,28 +3057,28 @@ ; break;} case 132: -#line 1649 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1648 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { CurGV = 0; ; break;} case 133: -#line 1652 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1651 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { ; break;} case 134: -#line 1654 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1653 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { ; break;} case 135: -#line 1656 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1655 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { ; break;} case 136: -#line 1660 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1659 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { const std::string &AsmSoFar = CurModule.CurrentModule->getModuleInlineAsm(); char *EndStr = UnEscapeLexed(yyvsp[0].StrVal, true); @@ -3093,21 +3092,21 @@ ; break;} case 137: -#line 1672 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1671 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { yyval.Endianness = Module::BigEndian; ; break;} case 138: -#line 1673 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1672 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { yyval.Endianness = Module::LittleEndian; ; break;} case 139: -#line 1675 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1674 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { CurModule.CurrentModule->setEndianness(yyvsp[0].Endianness); ; break;} case 140: -#line 1678 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1677 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { if (yyvsp[0].UInt64Val == 32) CurModule.CurrentModule->setPointerSize(Module::Pointer32); @@ -3118,37 +3117,37 @@ ; break;} case 141: -#line 1686 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1685 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { CurModule.CurrentModule->setTargetTriple(yyvsp[0].StrVal); free(yyvsp[0].StrVal); ; break;} case 143: -#line 1693 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1692 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { CurModule.CurrentModule->addLibrary(yyvsp[0].StrVal); free(yyvsp[0].StrVal); ; break;} case 144: -#line 1697 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1696 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { CurModule.CurrentModule->addLibrary(yyvsp[0].StrVal); free(yyvsp[0].StrVal); ; break;} case 145: -#line 1701 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1700 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { ; break;} case 149: -#line 1710 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1709 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { yyval.StrVal = 0; ; break;} case 150: -#line 1712 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1711 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { if (*yyvsp[-1].TypeVal == Type::VoidTy) ThrowException("void typed arguments are invalid!"); @@ -3156,7 +3155,7 @@ ; break;} case 151: -#line 1718 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1717 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { yyval.ArgList = yyvsp[-2].ArgList; yyvsp[-2].ArgList->push_back(*yyvsp[0].ArgVal); @@ -3164,7 +3163,7 @@ ; break;} case 152: -#line 1723 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1722 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { yyval.ArgList = new std::vector >(); yyval.ArgList->push_back(*yyvsp[0].ArgVal); @@ -3172,13 +3171,13 @@ ; break;} case 153: -#line 1729 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1728 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { yyval.ArgList = yyvsp[0].ArgList; ; break;} case 154: -#line 1732 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1731 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { yyval.ArgList = yyvsp[-2].ArgList; yyval.ArgList->push_back(std::pair >(); yyval.ArgList->push_back(std::make_pair(new PATypeHolder(Type::VoidTy), (char*)0)); ; break;} case 156: -#line 1741 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1740 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { yyval.ArgList = 0; ; break;} case 157: -#line 1746 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1745 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { UnEscapeLexed(yyvsp[-5].StrVal); std::string FunctionName(yyvsp[-5].StrVal); @@ -3286,7 +3285,7 @@ ; break;} case 160: -#line 1833 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1832 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { yyval.FunctionVal = CurFun.CurrentFunction; @@ -3296,84 +3295,84 @@ ; break;} case 163: -#line 1843 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1842 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { yyval.FunctionVal = yyvsp[-1].FunctionVal; ; break;} case 164: -#line 1847 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1846 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { CurFun.isDeclare = true; ; break;} case 165: -#line 1847 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1846 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { yyval.FunctionVal = CurFun.CurrentFunction; CurFun.FunctionDone(); ; break;} case 166: -#line 1856 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1855 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { yyval.BoolVal = false; ; break;} case 167: -#line 1859 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1858 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { yyval.BoolVal = true; ; break;} case 168: -#line 1863 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1862 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { // A reference to a direct constant yyval.ValIDVal = ValID::create(yyvsp[0].SInt64Val); ; break;} case 169: -#line 1866 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1865 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { yyval.ValIDVal = ValID::create(yyvsp[0].UInt64Val); ; break;} case 170: -#line 1869 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1868 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { // Perhaps it's an FP constant? yyval.ValIDVal = ValID::create(yyvsp[0].FPVal); ; break;} case 171: -#line 1872 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1871 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { yyval.ValIDVal = ValID::create(ConstantBool::True); ; break;} case 172: -#line 1875 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1874 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { yyval.ValIDVal = ValID::create(ConstantBool::False); ; break;} case 173: -#line 1878 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1877 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { yyval.ValIDVal = ValID::createNull(); ; break;} case 174: -#line 1881 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1880 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { yyval.ValIDVal = ValID::createUndef(); ; break;} case 175: -#line 1884 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1883 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { // A vector zero constant. yyval.ValIDVal = ValID::createZeroInit(); ; break;} case 176: -#line 1887 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1886 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { // Nonempty unsized packed vector const Type *ETy = (*yyvsp[-1].ConstVector)[0]->getType(); int NumElements = yyvsp[-1].ConstVector->size(); @@ -3400,13 +3399,13 @@ ; break;} case 177: -#line 1911 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1910 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { yyval.ValIDVal = ValID::create(yyvsp[0].ConstVal); ; break;} case 178: -#line 1914 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1913 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { char *End = UnEscapeLexed(yyvsp[-2].StrVal, true); std::string AsmStr = std::string(yyvsp[-2].StrVal, End); @@ -3418,37 +3417,37 @@ ; break;} case 179: -#line 1927 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1926 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { // Is it an integer reference...? yyval.ValIDVal = ValID::create(yyvsp[0].SIntVal); ; break;} case 180: -#line 1930 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1929 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { // Is it a named reference...? yyval.ValIDVal = ValID::create(yyvsp[0].StrVal); ; break;} case 183: -#line 1941 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1940 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { yyval.ValueVal = getVal(*yyvsp[-1].TypeVal, yyvsp[0].ValIDVal); delete yyvsp[-1].TypeVal; ; break;} case 184: -#line 1945 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1944 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { yyval.FunctionVal = yyvsp[-1].FunctionVal; ; break;} case 185: -#line 1948 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1947 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { // Do not allow functions with 0 basic blocks yyval.FunctionVal = yyvsp[-1].FunctionVal; ; break;} case 186: -#line 1956 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1955 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { setValueName(yyvsp[0].TermInstVal, yyvsp[-1].StrVal); InsertValue(yyvsp[0].TermInstVal); @@ -3459,14 +3458,14 @@ ; break;} case 187: -#line 1965 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1964 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { yyvsp[-1].BasicBlockVal->getInstList().push_back(yyvsp[0].InstVal); yyval.BasicBlockVal = yyvsp[-1].BasicBlockVal; ; break;} case 188: -#line 1969 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1968 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { yyval.BasicBlockVal = CurBB = getBBVal(ValID::create((int)CurFun.NextBBNum++), true); @@ -3479,7 +3478,7 @@ ; break;} case 189: -#line 1979 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1978 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { yyval.BasicBlockVal = CurBB = getBBVal(ValID::create(yyvsp[0].StrVal), true); @@ -3492,31 +3491,31 @@ ; break;} case 190: -#line 1990 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1989 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { // Return with a result... yyval.TermInstVal = new ReturnInst(yyvsp[0].ValueVal); ; break;} case 191: -#line 1993 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1992 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { // Return with no result... yyval.TermInstVal = new ReturnInst(); ; break;} case 192: -#line 1996 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1995 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { // Unconditional Branch... yyval.TermInstVal = new BranchInst(getBBVal(yyvsp[0].ValIDVal)); ; break;} case 193: -#line 1999 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1998 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { yyval.TermInstVal = new BranchInst(getBBVal(yyvsp[-3].ValIDVal), getBBVal(yyvsp[0].ValIDVal), getVal(Type::BoolTy, yyvsp[-6].ValIDVal)); ; break;} case 194: -#line 2002 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +#line 2001 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { SwitchInst *S = new SwitchInst(getVal(yyvsp[-7].PrimType, yyvsp[-6].ValIDVal), getBBVal(yyvsp[-3].ValIDVal), yyvsp[-1].JumpTable->size()); yyval.TermInstVal = S; @@ -3533,14 +3532,14 @@ ; break;} case 195: -#line 2016 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +#line 2015 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { SwitchInst *S = new SwitchInst(getVal(yyvsp[-6].PrimType, yyvsp[-5].ValIDVal), getBBVal(yyvsp[-2].ValIDVal), 0); yyval.TermInstVal = S; ; break;} case 196: -#line 2021 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +#line 2020 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { const PointerType *PFTy; const FunctionType *Ty; @@ -3595,19 +3594,19 @@ ; break;} case 197: -#line 2073 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +#line 2072 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { yyval.TermInstVal = new UnwindInst(); ; break;} case 198: -#line 2076 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +#line 2075 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { yyval.TermInstVal = new UnreachableInst(); ; break;} case 199: -#line 2082 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +#line 2081 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { yyval.JumpTable = yyvsp[-5].JumpTable; Constant *V = cast(getValNonImprovising(yyvsp[-4].PrimType, yyvsp[-3].ValIDVal)); @@ -3618,7 +3617,7 @@ ; break;} case 200: -#line 2090 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +#line 2089 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { yyval.JumpTable = new std::vector >(); Constant *V = cast(getValNonImprovising(yyvsp[-4].PrimType, yyvsp[-3].ValIDVal)); @@ -3630,7 +3629,7 @@ ; break;} case 201: -#line 2100 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +#line 2099 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { // Is this definition named?? if so, assign the name... setValueName(yyvsp[0].InstVal, yyvsp[-1].StrVal); @@ -3639,7 +3638,7 @@ ; break;} case 202: -#line 2107 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +#line 2106 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { // Used for PHI nodes yyval.PHIList = new std::list >(); yyval.PHIList->push_back(std::make_pair(getVal(*yyvsp[-5].TypeVal, yyvsp[-3].ValIDVal), getBBVal(yyvsp[-1].ValIDVal))); @@ -3647,7 +3646,7 @@ ; break;} case 203: -#line 2112 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +#line 2111 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { yyval.PHIList = yyvsp[-6].PHIList; yyvsp[-6].PHIList->push_back(std::make_pair(getVal(yyvsp[-6].PHIList->front().first->getType(), yyvsp[-3].ValIDVal), @@ -3655,37 +3654,37 @@ ; break;} case 204: -#line 2119 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +#line 2118 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { // Used for call statements, and memory insts... yyval.ValueList = new std::vector(); yyval.ValueList->push_back(yyvsp[0].ValueVal); ; break;} case 205: -#line 2123 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +#line 2122 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { yyval.ValueList = yyvsp[-2].ValueList; yyvsp[-2].ValueList->push_back(yyvsp[0].ValueVal); ; break;} case 207: -#line 2129 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +#line 2128 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { yyval.ValueList = 0; ; break;} case 208: -#line 2131 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +#line 2130 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { yyval.BoolVal = true; ; break;} case 209: -#line 2134 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +#line 2133 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { yyval.BoolVal = false; ; break;} case 210: -#line 2140 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +#line 2139 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { if (!(*yyvsp[-3].TypeVal)->isInteger() && !(*yyvsp[-3].TypeVal)->isFloatingPoint() && !isa((*yyvsp[-3].TypeVal).get())) @@ -3700,7 +3699,7 @@ ; break;} case 211: -#line 2152 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +#line 2151 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { if (!(*yyvsp[-3].TypeVal)->isIntegral()) { if (!isa(yyvsp[-3].TypeVal->get()) || @@ -3714,7 +3713,7 @@ ; break;} case 212: -#line 2163 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +#line 2162 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { if(isa((*yyvsp[-3].TypeVal).get())) { ThrowException( @@ -3727,7 +3726,7 @@ ; break;} case 213: -#line 2173 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +#line 2172 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { std::cerr << "WARNING: Use of eliminated 'not' instruction:" << " Replacing with 'xor'.\n"; @@ -3742,7 +3741,7 @@ ; break;} case 214: -#line 2185 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +#line 2184 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { if (yyvsp[0].ValueVal->getType() != Type::UByteTy) ThrowException("Shift amount must be ubyte!"); @@ -3752,7 +3751,7 @@ ; break;} case 215: -#line 2192 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +#line 2191 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { if (!yyvsp[0].TypeVal->get()->isFirstClassType()) ThrowException("cast instruction to a non-primitive type: '" + @@ -3762,7 +3761,7 @@ ; break;} case 216: -#line 2199 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +#line 2198 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { if (yyvsp[-4].ValueVal->getType() != Type::BoolTy) ThrowException("select condition must be boolean!"); @@ -3772,7 +3771,7 @@ ; break;} case 217: -#line 2206 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +#line 2205 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { NewVarArgs = true; yyval.InstVal = new VAArgInst(yyvsp[-2].ValueVal, *yyvsp[0].TypeVal); @@ -3780,7 +3779,7 @@ ; break;} case 218: -#line 2211 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +#line 2210 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { ObsoleteVarArgs = true; const Type* ArgTy = yyvsp[-2].ValueVal->getType(); @@ -3802,7 +3801,7 @@ ; break;} case 219: -#line 2230 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +#line 2229 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { ObsoleteVarArgs = true; const Type* ArgTy = yyvsp[-2].ValueVal->getType(); @@ -3827,33 +3826,23 @@ ; break;} case 220: -#line 2252 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +#line 2251 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { - if (!isa(yyvsp[-2].ValueVal->getType())) - ThrowException("First operand of extractelement must be " - "packed type!"); - if (yyvsp[0].ValueVal->getType() != Type::UIntTy) - ThrowException("Second operand of extractelement must be uint!"); + if (!ExtractElementInst::isValidOperands(yyvsp[-2].ValueVal, yyvsp[0].ValueVal)) + ThrowException("Invalid extractelement operands!"); yyval.InstVal = new ExtractElementInst(yyvsp[-2].ValueVal, yyvsp[0].ValueVal); ; break;} case 221: -#line 2260 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +#line 2256 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { - if (!isa(yyvsp[-4].ValueVal->getType())) - ThrowException("First operand of insertelement must be " - "packed type!"); - if (yyvsp[-2].ValueVal->getType() != - cast(yyvsp[-4].ValueVal->getType())->getElementType()) - ThrowException("Second operand of insertelement must be " - "packed element type!"); - if (yyvsp[0].ValueVal->getType() != Type::UIntTy) - ThrowException("Third operand of insertelement must be uint!"); + if (!InsertElementInst::isValidOperands(yyvsp[-4].ValueVal, yyvsp[-2].ValueVal, yyvsp[0].ValueVal)) + ThrowException("Invalid insertelement operands!"); yyval.InstVal = new InsertElementInst(yyvsp[-4].ValueVal, yyvsp[-2].ValueVal, yyvsp[0].ValueVal); ; break;} case 222: -#line 2272 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +#line 2261 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { if (!ShuffleVectorInst::isValidOperands(yyvsp[-4].ValueVal, yyvsp[-2].ValueVal, yyvsp[0].ValueVal)) ThrowException("Invalid shufflevector operands!"); @@ -3861,7 +3850,7 @@ ; break;} case 223: -#line 2277 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +#line 2266 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { const Type *Ty = yyvsp[0].PHIList->front().first->getType(); if (!Ty->isFirstClassType()) @@ -3878,7 +3867,7 @@ ; break;} case 224: -#line 2291 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +#line 2280 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { const PointerType *PFTy; const FunctionType *Ty; @@ -3938,65 +3927,65 @@ ; break;} case 225: -#line 2348 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +#line 2337 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { yyval.InstVal = yyvsp[0].InstVal; ; break;} case 226: -#line 2354 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +#line 2343 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { yyval.ValueList = yyvsp[0].ValueList; ; break;} case 227: -#line 2356 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +#line 2345 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { yyval.ValueList = new std::vector(); ; break;} case 228: -#line 2360 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +#line 2349 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { yyval.BoolVal = true; ; break;} case 229: -#line 2363 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +#line 2352 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { yyval.BoolVal = false; ; break;} case 230: -#line 2369 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +#line 2358 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { yyval.InstVal = new MallocInst(*yyvsp[-1].TypeVal, 0, yyvsp[0].UIntVal); delete yyvsp[-1].TypeVal; ; break;} case 231: -#line 2373 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +#line 2362 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { yyval.InstVal = new MallocInst(*yyvsp[-4].TypeVal, getVal(yyvsp[-2].PrimType, yyvsp[-1].ValIDVal), yyvsp[0].UIntVal); delete yyvsp[-4].TypeVal; ; break;} case 232: -#line 2377 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +#line 2366 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { yyval.InstVal = new AllocaInst(*yyvsp[-1].TypeVal, 0, yyvsp[0].UIntVal); delete yyvsp[-1].TypeVal; ; break;} case 233: -#line 2381 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +#line 2370 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { yyval.InstVal = new AllocaInst(*yyvsp[-4].TypeVal, getVal(yyvsp[-2].PrimType, yyvsp[-1].ValIDVal), yyvsp[0].UIntVal); delete yyvsp[-4].TypeVal; ; break;} case 234: -#line 2385 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +#line 2374 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { if (!isa(yyvsp[0].ValueVal->getType())) ThrowException("Trying to free nonpointer type " + @@ -4005,7 +3994,7 @@ ; break;} case 235: -#line 2392 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +#line 2381 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { if (!isa(yyvsp[-1].TypeVal->get())) ThrowException("Can't load from nonpointer type: " + @@ -4018,7 +4007,7 @@ ; break;} case 236: -#line 2402 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +#line 2391 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { const PointerType *PT = dyn_cast(yyvsp[-1].TypeVal->get()); if (!PT) @@ -4034,7 +4023,7 @@ ; break;} case 237: -#line 2415 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +#line 2404 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { if (!isa(yyvsp[-2].TypeVal->get())) ThrowException("getelementptr insn requires pointer operand!"); @@ -4279,7 +4268,7 @@ } return 1; } -#line 2438 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +#line 2427 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" int yyerror(const char *ErrorMsg) { std::string where Index: llvm/lib/AsmParser/llvmAsmParser.y.cvs diff -u llvm/lib/AsmParser/llvmAsmParser.y.cvs:1.4 llvm/lib/AsmParser/llvmAsmParser.y.cvs:1.5 --- llvm/lib/AsmParser/llvmAsmParser.y.cvs:1.4 Fri Apr 7 22:55:17 2006 +++ llvm/lib/AsmParser/llvmAsmParser.y.cvs Fri Apr 7 23:09:02 2006 @@ -1541,14 +1541,13 @@ $$ = ConstantExpr::get($1, $3, $5); } | EXTRACTELEMENT '(' ConstVal ',' ConstVal ')' { - if (!isa($3->getType())) - ThrowException("First operand of extractelement must be " - "packed type!"); - if ($5->getType() != Type::UIntTy) - ThrowException("Second operand of extractelement must be uint!"); + if (!ExtractElementInst::isValidOperands($3, $5)) + ThrowException("Invalid extractelement operands!"); $$ = ConstantExpr::getExtractElement($3, $5); } | INSERTELEMENT '(' ConstVal ',' ConstVal ',' ConstVal ')' { + if (!InsertElementInst::isValidOperands($3, $5, $7)) + ThrowException("Invalid insertelement operands!"); $$ = ConstantExpr::getInsertElement($3, $5, $7); } | SHUFFLEVECTOR '(' ConstVal ',' ConstVal ',' ConstVal ')' { @@ -2250,23 +2249,13 @@ delete $4; } | EXTRACTELEMENT ResolvedVal ',' ResolvedVal { - if (!isa($2->getType())) - ThrowException("First operand of extractelement must be " - "packed type!"); - if ($4->getType() != Type::UIntTy) - ThrowException("Second operand of extractelement must be uint!"); + if (!ExtractElementInst::isValidOperands($2, $4)) + ThrowException("Invalid extractelement operands!"); $$ = new ExtractElementInst($2, $4); } | INSERTELEMENT ResolvedVal ',' ResolvedVal ',' ResolvedVal { - if (!isa($2->getType())) - ThrowException("First operand of insertelement must be " - "packed type!"); - if ($4->getType() != - cast($2->getType())->getElementType()) - ThrowException("Second operand of insertelement must be " - "packed element type!"); - if ($6->getType() != Type::UIntTy) - ThrowException("Third operand of insertelement must be uint!"); + if (!InsertElementInst::isValidOperands($2, $4, $6)) + ThrowException("Invalid insertelement operands!"); $$ = new InsertElementInst($2, $4, $6); } | SHUFFLEVECTOR ResolvedVal ',' ResolvedVal ',' ResolvedVal { From lattner at cs.uiuc.edu Fri Apr 7 23:09:32 2006 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Fri, 7 Apr 2006 23:09:32 -0500 Subject: [llvm-commits] CVS: llvm/lib/Bytecode/Reader/Reader.cpp Message-ID: <200604080409.XAA20849@zion.cs.uiuc.edu> Changes in directory llvm/lib/Bytecode/Reader: Reader.cpp updated: 1.192 -> 1.193 --- Log message: use isValidOperands instead of duplicating checks --- Diffs of the changes: (+24 -13) Reader.cpp | 37 ++++++++++++++++++++++++------------- 1 files changed, 24 insertions(+), 13 deletions(-) Index: llvm/lib/Bytecode/Reader/Reader.cpp diff -u llvm/lib/Bytecode/Reader/Reader.cpp:1.192 llvm/lib/Bytecode/Reader/Reader.cpp:1.193 --- llvm/lib/Bytecode/Reader/Reader.cpp:1.192 Fri Apr 7 20:17:59 2006 +++ llvm/lib/Bytecode/Reader/Reader.cpp Fri Apr 7 23:09:19 2006 @@ -719,19 +719,27 @@ case Instruction::ExtractElement: { if (Oprnds.size() != 2) throw std::string("Invalid extractelement instruction!"); - Result = new ExtractElementInst(getValue(iType, Oprnds[0]), - getValue(Type::UIntTyID, Oprnds[1])); + Value *V1 = getValue(iType, Oprnds[0]); + Value *V2 = getValue(Type::UIntTyID, Oprnds[1]); + + if (!ExtractElementInst::isValidOperands(V1, V2)) + throw std::string("Invalid extractelement instruction!"); + + Result = new ExtractElementInst(V1, V2); break; } case Instruction::InsertElement: { const PackedType *PackedTy = dyn_cast(InstTy); if (!PackedTy || Oprnds.size() != 3) throw std::string("Invalid insertelement instruction!"); - Result = - new InsertElementInst(getValue(iType, Oprnds[0]), - getValue(getTypeSlot(PackedTy->getElementType()), - Oprnds[1]), - getValue(Type::UIntTyID, Oprnds[2])); + + Value *V1 = getValue(iType, Oprnds[0]); + Value *V2 = getValue(getTypeSlot(PackedTy->getElementType()), Oprnds[1]); + Value *V3 = getValue(Type::UIntTyID, Oprnds[2]); + + if (!InsertElementInst::isValidOperands(V1, V2, V3)) + throw std::string("Invalid insertelement instruction!"); + Result = new InsertElementInst(V1, V2, V3); break; } case Instruction::ShuffleVector: { @@ -1495,22 +1503,25 @@ if (Handler) Handler->handleConstantExpression(Opcode, ArgVec, Result); return Result; } else if (Opcode == Instruction::ExtractElement) { - if (ArgVec.size() != 2) - error("ExtractElement instruction must have two arguments."); + if (ArgVec.size() != 2 || + !ExtractElementInst::isValidOperands(ArgVec[0], ArgVec[1])) + error("Invalid extractelement constand expr arguments"); Constant* Result = ConstantExpr::getExtractElement(ArgVec[0], ArgVec[1]); if (Handler) Handler->handleConstantExpression(Opcode, ArgVec, Result); return Result; } else if (Opcode == Instruction::InsertElement) { - if (ArgVec.size() != 3) - error("InsertElement instruction must have three arguments."); - Constant* Result = + if (ArgVec.size() != 3 || + !InsertElementInst::isValidOperands(ArgVec[0], ArgVec[1], ArgVec[2])) + error("Invalid insertelement constand expr arguments"); + + Constant *Result = ConstantExpr::getInsertElement(ArgVec[0], ArgVec[1], ArgVec[2]); if (Handler) Handler->handleConstantExpression(Opcode, ArgVec, Result); return Result; } else if (Opcode == Instruction::ShuffleVector) { if (ArgVec.size() != 3 || !ShuffleVectorInst::isValidOperands(ArgVec[0], ArgVec[1], ArgVec[2])) - error("shufflevector constant expr must have three arguments."); + error("Invalid shufflevector constant expr arguments."); Constant *Result = ConstantExpr::getShuffleVector(ArgVec[0], ArgVec[1], ArgVec[2]); if (Handler) Handler->handleConstantExpression(Opcode, ArgVec, Result); From lattner at cs.uiuc.edu Fri Apr 7 23:13:30 2006 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Fri, 7 Apr 2006 23:13:30 -0500 Subject: [llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp Message-ID: <200604080413.XAA20920@zion.cs.uiuc.edu> Changes in directory llvm/lib/CodeGen/SelectionDAG: LegalizeDAG.cpp updated: 1.354 -> 1.355 --- Log message: add a sanity check: LegalizeOp should return a value that is the same type as its input. --- Diffs of the changes: (+3 -0) LegalizeDAG.cpp | 3 +++ 1 files changed, 3 insertions(+) Index: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp diff -u llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.354 llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.355 --- llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.354 Fri Apr 7 20:46:37 2006 +++ llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp Fri Apr 7 23:13:17 2006 @@ -2688,6 +2688,9 @@ } } + assert(Result.getValueType() == Op.getValueType() && + "Bad legalization!"); + // Make sure that the generated code is itself legal. if (Result != Op) Result = LegalizeOp(Result); From lattner at cs.uiuc.edu Fri Apr 7 23:15:37 2006 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Fri, 7 Apr 2006 23:15:37 -0500 Subject: [llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp SelectionDAGISel.cpp Message-ID: <200604080415.XAA20998@zion.cs.uiuc.edu> Changes in directory llvm/lib/CodeGen/SelectionDAG: DAGCombiner.cpp updated: 1.145 -> 1.146 SelectionDAGISel.cpp updated: 1.219 -> 1.220 --- Log message: Codegen shufflevector as VVECTOR_SHUFFLE --- Diffs of the changes: (+25 -2) DAGCombiner.cpp | 13 ++++++++++++- SelectionDAGISel.cpp | 14 +++++++++++++- 2 files changed, 25 insertions(+), 2 deletions(-) Index: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp diff -u llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.145 llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.146 --- llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.145 Thu Apr 6 18:20:43 2006 +++ llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Fri Apr 7 23:15:24 2006 @@ -1447,6 +1447,12 @@ AddToWorkList(XORNode.Val); return DAG.getNode(N0.getOpcode(), VT, XORNode, N0.getOperand(1)); } + + // Simplify the expression using non-local knowledge. + if (!MVT::isVector(VT) && + SimplifyDemandedBits(SDOperand(N, 0))) + return SDOperand(); + return SDOperand(); } @@ -2044,8 +2050,10 @@ // type, convert each element. This handles FP<->INT cases. if (SrcBitSize == DstBitSize) { std::vector Ops; - for (unsigned i = 0, e = BV->getNumOperands()-2; i != e; ++i) + for (unsigned i = 0, e = BV->getNumOperands()-2; i != e; ++i) { Ops.push_back(DAG.getNode(ISD::BIT_CONVERT, DstEltVT, BV->getOperand(i))); + AddToWorkList(Ops.back().Val); + } Ops.push_back(*(BV->op_end()-2)); // Add num elements. Ops.push_back(DAG.getValueType(DstEltVT)); return DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector, Ops); @@ -2635,6 +2643,7 @@ UnOps.push_back(NumElts); UnOps.push_back(EltType); Ops.push_back(DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector, UnOps)); + AddToWorkList(Ops.back().Val); } Ops.push_back(DAG.getNode(ISD::VBUILD_VECTOR,MVT::Vector, BuildVecIndices)); Ops.push_back(NumElts); @@ -2690,6 +2699,7 @@ } ShufMask = DAG.getNode(ISD::BUILD_VECTOR, ShufMask.getValueType(), MappedOps); + AddToWorkList(ShufMask.Val); return DAG.getNode(ISD::VECTOR_SHUFFLE, N->getValueType(0), N->getOperand(0), DAG.getNode(ISD::UNDEF, N->getValueType(0)), @@ -2755,6 +2765,7 @@ RHSOp.getOpcode() != ISD::ConstantFP)) break; Ops.push_back(DAG.getNode(ScalarOp, EltType, LHSOp, RHSOp)); + AddToWorkList(Ops.back().Val); assert((Ops.back().getOpcode() == ISD::UNDEF || Ops.back().getOpcode() == ISD::Constant || Ops.back().getOpcode() == ISD::ConstantFP) && Index: llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp diff -u llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.219 llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.220 --- llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.219 Fri Apr 7 20:19:25 2006 +++ llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp Fri Apr 7 23:15:24 2006 @@ -516,7 +516,7 @@ void visitExtractElement(User &I); void visitInsertElement(User &I); - void visitShuffleVector(User &I) { assert(0 && "ShuffleVector not impl!"); } + void visitShuffleVector(User &I); void visitGetElementPtr(User &I); void visitCast(User &I); @@ -1076,6 +1076,18 @@ TLI.getValueType(I.getType()), InVec, InIdx)); } +void SelectionDAGLowering::visitShuffleVector(User &I) { + SDOperand V1 = getValue(I.getOperand(0)); + SDOperand V2 = getValue(I.getOperand(1)); + SDOperand Mask = getValue(I.getOperand(2)); + + SDOperand Num = *(V1.Val->op_end()-2); + SDOperand Typ = *(V2.Val->op_end()-1); + setValue(&I, DAG.getNode(ISD::VVECTOR_SHUFFLE, MVT::Vector, + V1, V2, Mask, Num, Typ)); +} + + void SelectionDAGLowering::visitGetElementPtr(User &I) { SDOperand N = getValue(I.getOperand(0)); const Type *Ty = I.getOperand(0)->getType(); From lattner at cs.uiuc.edu Fri Apr 7 23:39:31 2006 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Fri, 7 Apr 2006 23:39:31 -0500 Subject: [llvm-commits] CVS: llvm/docs/LangRef.html Message-ID: <200604080439.XAA21134@zion.cs.uiuc.edu> Changes in directory llvm/docs: LangRef.html updated: 1.144 -> 1.145 --- Log message: use the right escapes --- Diffs of the changes: (+3 -3) LangRef.html | 6 +++--- 1 files changed, 3 insertions(+), 3 deletions(-) Index: llvm/docs/LangRef.html diff -u llvm/docs/LangRef.html:1.144 llvm/docs/LangRef.html:1.145 --- llvm/docs/LangRef.html:1.144 Fri Apr 7 19:13:41 2006 +++ llvm/docs/LangRef.html Fri Apr 7 23:39:19 2006 @@ -2662,8 +2662,8 @@
Example:
-  %result = shufflevector <4 x int> %v1, <4 x int> %v2, <4 x uint>     ; yields <4 x int>
-  %result = shufflevector <4 x int> %v1, <4 x int> undef, <4 x uint>   ; yields <4 x int> - Identity shuffle.
+  %result = shufflevector <4 x int> %v1, <4 x int> %v2, <4 x uint> <uint 0, uint 4, uint 1, uint 5>    ; yields <4 x int>
+  %result = shufflevector <4 x int> %v1, <4 x int> undef, <4 x uint> <uint 0, uint 1, uint 2, uint 3>  ; yields <4 x int> - Identity shuffle.
 
@@ -3792,7 +3792,7 @@ Chris Lattner
The LLVM Compiler Infrastructure
- Last modified: $Date: 2006/04/08 00:13:41 $ + Last modified: $Date: 2006/04/08 04:39:19 $ From lattner at cs.uiuc.edu Fri Apr 7 23:41:06 2006 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Fri, 7 Apr 2006 23:41:06 -0500 Subject: [llvm-commits] CVS: llvm/docs/LangRef.html Message-ID: <200604080441.XAA21192@zion.cs.uiuc.edu> Changes in directory llvm/docs: LangRef.html updated: 1.145 -> 1.146 --- Log message: Wrap long lines, fix verification error --- Diffs of the changes: (+6 -4) LangRef.html | 10 ++++++---- 1 files changed, 6 insertions(+), 4 deletions(-) Index: llvm/docs/LangRef.html diff -u llvm/docs/LangRef.html:1.145 llvm/docs/LangRef.html:1.146 --- llvm/docs/LangRef.html:1.145 Fri Apr 7 23:39:19 2006 +++ llvm/docs/LangRef.html Fri Apr 7 23:40:53 2006 @@ -585,7 +585,7 @@
@@ -2662,8 +2662,10 @@
Example:
-  %result = shufflevector <4 x int> %v1, <4 x int> %v2, <4 x uint> <uint 0, uint 4, uint 1, uint 5>    ; yields <4 x int>
-  %result = shufflevector <4 x int> %v1, <4 x int> undef, <4 x uint> <uint 0, uint 1, uint 2, uint 3>  ; yields <4 x int> - Identity shuffle.
+  %result = shufflevector <4 x int> %v1, <4 x int> %v2, 
+                          <4 x uint> <uint 0, uint 4, uint 1, uint 5>    ; yields <4 x int>
+  %result = shufflevector <4 x int> %v1, <4 x int> undef, 
+                          <4 x uint> <uint 0, uint 1, uint 2, uint 3>  ; yields <4 x int> - Identity shuffle.
 
@@ -3792,7 +3794,7 @@ Chris Lattner
The LLVM Compiler Infrastructure
- Last modified: $Date: 2006/04/08 04:39:19 $ + Last modified: $Date: 2006/04/08 04:40:53 $ From lattner at cs.uiuc.edu Sat Apr 8 00:10:00 2006 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Sat, 8 Apr 2006 00:10:00 -0500 Subject: [llvm-commits] CVS: llvm/lib/VMCore/Constants.cpp Message-ID: <200604080510.AAA21376@zion.cs.uiuc.edu> Changes in directory llvm/lib/VMCore: Constants.cpp updated: 1.149 -> 1.150 --- Log message: Add constant replacement for insertelement/vectorshuffle constant exprs --- Diffs of the changes: (+16 -0) Constants.cpp | 16 ++++++++++++++++ 1 files changed, 16 insertions(+) Index: llvm/lib/VMCore/Constants.cpp diff -u llvm/lib/VMCore/Constants.cpp:1.149 llvm/lib/VMCore/Constants.cpp:1.150 --- llvm/lib/VMCore/Constants.cpp:1.149 Fri Apr 7 20:18:18 2006 +++ llvm/lib/VMCore/Constants.cpp Sat Apr 8 00:09:48 2006 @@ -1702,6 +1702,22 @@ if (C1 == From) C1 = To; if (C2 == From) C2 = To; Replacement = ConstantExpr::getExtractElement(C1, C2); + } else if (getOpcode() == Instruction::InsertElement) { + Constant *C1 = getOperand(0); + Constant *C2 = getOperand(1); + Constant *C3 = getOperand(1); + if (C1 == From) C1 = To; + if (C2 == From) C2 = To; + if (C3 == From) C3 = To; + Replacement = ConstantExpr::getInsertElement(C1, C2, C3); + } else if (getOpcode() == Instruction::ShuffleVector) { + Constant *C1 = getOperand(0); + Constant *C2 = getOperand(1); + Constant *C3 = getOperand(2); + if (C1 == From) C1 = To; + if (C2 == From) C2 = To; + if (C3 == From) C3 = To; + Replacement = ConstantExpr::getShuffleVector(C1, C2, C3); } else if (getNumOperands() == 2) { Constant *C1 = getOperand(0); Constant *C2 = getOperand(1); From lattner at cs.uiuc.edu Sat Apr 8 00:34:37 2006 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Sat, 8 Apr 2006 00:34:37 -0500 Subject: [llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp LegalizeDAG.cpp Message-ID: <200604080534.AAA21471@zion.cs.uiuc.edu> Changes in directory llvm/lib/CodeGen/SelectionDAG: DAGCombiner.cpp updated: 1.146 -> 1.147 LegalizeDAG.cpp updated: 1.355 -> 1.356 --- Log message: Canonicalize vvector_shuffle(x,x) -> vvector_shuffle(x,undef) to enable patterns to match again :) --- Diffs of the changes: (+50 -2) DAGCombiner.cpp | 36 ++++++++++++++++++++++++++++++++++++ LegalizeDAG.cpp | 16 ++++++++++++++-- 2 files changed, 50 insertions(+), 2 deletions(-) Index: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp diff -u llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.146 llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.147 --- llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.146 Fri Apr 7 23:15:24 2006 +++ llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Sat Apr 8 00:34:25 2006 @@ -2735,6 +2735,42 @@ } if (isIdentity) return N->getOperand(1); + // If the LHS and the RHS are the same node, turn the RHS into an undef. + if (N->getOperand(0) == N->getOperand(1)) { + // Check the SHUFFLE mask, mapping any inputs from the 2nd operand into the + // first operand. + std::vector MappedOps; + for (unsigned i = 0; i != NumElts; ++i) { + if (ShufMask.getOperand(i).getOpcode() == ISD::UNDEF || + cast(ShufMask.getOperand(i))->getValue() < NumElts) { + MappedOps.push_back(ShufMask.getOperand(i)); + } else { + unsigned NewIdx = + cast(ShufMask.getOperand(i))->getValue() - NumElts; + MappedOps.push_back(DAG.getConstant(NewIdx, MVT::i32)); + } + } + // Add the type/#elts values. + MappedOps.push_back(ShufMask.getOperand(NumElts)); + MappedOps.push_back(ShufMask.getOperand(NumElts+1)); + + ShufMask = DAG.getNode(ISD::VBUILD_VECTOR, ShufMask.getValueType(), + MappedOps); + AddToWorkList(ShufMask.Val); + + // Build the undef vector. + SDOperand UDVal = DAG.getNode(ISD::UNDEF, MappedOps[0].getValueType()); + for (unsigned i = 0; i != NumElts; ++i) + MappedOps[i] = UDVal; + MappedOps[NumElts ] = *(N->getOperand(0).Val->op_end()-2); + MappedOps[NumElts+1] = *(N->getOperand(0).Val->op_end()-1); + UDVal = DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector, MappedOps); + + return DAG.getNode(ISD::VVECTOR_SHUFFLE, MVT::Vector, + N->getOperand(0), UDVal, ShufMask, + MappedOps[NumElts], MappedOps[NumElts+1]); + } + return SDOperand(); } Index: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp diff -u llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.355 llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.356 --- llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.355 Fri Apr 7 23:13:17 2006 +++ llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp Sat Apr 8 00:34:25 2006 @@ -4697,8 +4697,20 @@ Result = Node->getOperand(0); } else { // Returning a BUILD_VECTOR? - std::vector Ops(Node->op_begin(), Node->op_end()-2); - Result = DAG.getNode(ISD::BUILD_VECTOR, NewVT, Ops); + + // If all elements of the build_vector are undefs, return an undef. + bool AllUndef = true; + for (unsigned i = 0, e = Node->getNumOperands()-2; i != e; ++i) + if (Node->getOperand(i).getOpcode() != ISD::UNDEF) { + AllUndef = false; + break; + } + if (AllUndef) { + Result = DAG.getNode(ISD::UNDEF, NewVT); + } else { + std::vector Ops(Node->op_begin(), Node->op_end()-2); + Result = DAG.getNode(ISD::BUILD_VECTOR, NewVT, Ops); + } } break; case ISD::VINSERT_VECTOR_ELT: From reid at x10sys.com Sat Apr 8 00:38:15 2006 From: reid at x10sys.com (Reid Spencer) Date: Sat, 8 Apr 2006 00:38:15 -0500 Subject: [llvm-commits] CVS: llvm/lib/Target/Alpha/AlphaISelDAGToDAG.cpp Message-ID: <200604080538.AAA21490@zion.cs.uiuc.edu> Changes in directory llvm/lib/Target/Alpha: AlphaISelDAGToDAG.cpp updated: 1.38 -> 1.39 --- Log message: Initialize SDOperand values because the gcc 4.0.2 compiler complains about them. --- Diffs of the changes: (+2 -2) AlphaISelDAGToDAG.cpp | 4 ++-- 1 files changed, 2 insertions(+), 2 deletions(-) Index: llvm/lib/Target/Alpha/AlphaISelDAGToDAG.cpp diff -u llvm/lib/Target/Alpha/AlphaISelDAGToDAG.cpp:1.38 llvm/lib/Target/Alpha/AlphaISelDAGToDAG.cpp:1.39 --- llvm/lib/Target/Alpha/AlphaISelDAGToDAG.cpp:1.38 Sun Apr 2 23:19:17 2006 +++ llvm/lib/Target/Alpha/AlphaISelDAGToDAG.cpp Sat Apr 8 00:38:03 2006 @@ -226,7 +226,7 @@ case ISD::RET: { SDOperand Chain; Select(Chain, N->getOperand(0)); // Token chain. - SDOperand InFlag; + SDOperand InFlag(0,0); if (N->getNumOperands() == 2) { SDOperand Val; @@ -420,7 +420,7 @@ SDNode *N = Op.Val; SDOperand Chain; SDOperand Addr = N->getOperand(1); - SDOperand InFlag; // Null incoming flag value. + SDOperand InFlag(0,0); // Null incoming flag value. Select(Chain, N->getOperand(0)); std::vector CallOperands; From jlaskey at apple.com Sat Apr 8 01:05:09 2006 From: jlaskey at apple.com (Jim Laskey) Date: Sat, 8 Apr 2006 01:05:09 -0500 Subject: [llvm-commits] CVS: llvm/Xcode/LLVM.xcodeproj/project.pbxproj Message-ID: <200604080605.BAA21667@zion.cs.uiuc.edu> Changes in directory llvm/Xcode/LLVM.xcodeproj: project.pbxproj updated: 1.19 -> 1.20 --- Log message: Misc. project changes. html + build config changes supplied by Devang. --- Diffs of the changes: (+109 -112) project.pbxproj | 221 +++++++++++++++++++++++++++----------------------------- 1 files changed, 109 insertions(+), 112 deletions(-) Index: llvm/Xcode/LLVM.xcodeproj/project.pbxproj diff -u llvm/Xcode/LLVM.xcodeproj/project.pbxproj:1.19 llvm/Xcode/LLVM.xcodeproj/project.pbxproj:1.20 --- llvm/Xcode/LLVM.xcodeproj/project.pbxproj:1.19 Fri Jan 27 07:24:20 2006 +++ llvm/Xcode/LLVM.xcodeproj/project.pbxproj Sat Apr 8 01:04:56 2006 @@ -78,6 +78,7 @@ /* End PBXContainerItemProxy section */ /* Begin PBXFileReference section */ + CF1ACC9709C9DE4400D3C5EB /* IntrinsicInst.cpp */ = {isa = PBXFileReference; fileEncoding = 4; lastKnownFileType = sourcecode.cpp.cpp; name = IntrinsicInst.cpp; path = ../lib/VMCore/IntrinsicInst.cpp; sourceTree = ""; }; CF26835B09178F5500C5F253 /* TargetInstrItineraries.h */ = {isa = PBXFileReference; fileEncoding = 4; lastKnownFileType = sourcecode.c.h; path = TargetInstrItineraries.h; sourceTree = ""; }; CF490CD50903C9260072DB1C /* PPC.h */ = {isa = PBXFileReference; fileEncoding = 4; lastKnownFileType = sourcecode.c.h; path = PPC.h; sourceTree = ""; }; CF490CD60903C9260072DB1C /* PPCAsmPrinter.cpp */ = {isa = PBXFileReference; fileEncoding = 4; lastKnownFileType = sourcecode.cpp.cpp; path = PPCAsmPrinter.cpp; sourceTree = ""; }; @@ -112,6 +113,35 @@ CF490D890906A78C0072DB1C /* PPC.td */ = {isa = PBXFileReference; fileEncoding = 4; lastKnownFileType = text; path = PPC.td; sourceTree = ""; }; CF490E2F0907BBF80072DB1C /* SubtargetEmitter.h */ = {isa = PBXFileReference; fileEncoding = 4; lastKnownFileType = sourcecode.c.h; path = SubtargetEmitter.h; sourceTree = ""; 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- path = SparcV8; - sourceTree = ""; - }; DE66EFC908ABEE5F00323D32 /* SparcV9 */ = { isa = PBXGroup; children = ( @@ -1704,6 +1697,9 @@ DE66F09308ABEE6000323D32 /* X86 */ = { isa = PBXGroup; children = ( + CFF0DE6309BF6C360031957F /* X86InstrFPStack.td */, + CFF0DE6409BF6C360031957F /* X86InstrMMX.td */, + CFF0DE6509BF6C360031957F /* X86InstrSSE.td */, DE66F0BC08ABEE6000323D32 /* X86.h */, DE66F0BD08ABEE6000323D32 /* X86.td */, DE66F0BE08ABEE6000323D32 /* X86AsmPrinter.cpp */, @@ -1719,10 +1715,8 @@ DE66F0CF08ABEE6100323D32 /* X86InstrInfo.td */, DE66F0D008ABEE6100323D32 /* X86IntelAsmPrinter.cpp */, DE66F0D108ABEE6100323D32 /* X86IntelAsmPrinter.h */, - DE66F0D208ABEE6100323D32 /* X86ISelPattern.cpp */, DE66F0D508ABEE6100323D32 /* X86JITInfo.cpp */, DE66F0D608ABEE6100323D32 /* X86JITInfo.h */, - DE66F0D708ABEE6100323D32 /* X86PeepholeOpt.cpp */, DE66F0D808ABEE6100323D32 /* X86RegisterInfo.cpp */, DE66F0D908ABEE6100323D32 /* X86RegisterInfo.h */, DE66F0DA08ABEE6100323D32 /* X86RegisterInfo.td */, @@ -1886,6 +1880,8 @@ DE66F26408ABF03100323D32 /* Instructions.h */, DE66F26508ABF03100323D32 /* IntrinsicInst.h */, DE66F26608ABF03100323D32 /* Intrinsics.h */, + CF65223409CA39B800C4B521 /* Intrinsics.gen */, + CF8D62FA09C2226F006017BA /* Intrinsics.td */, DE66F26708ABF03100323D32 /* Linker.h */, DE66F26808ABF03100323D32 /* Module.h */, DE66F26908ABF03200323D32 /* ModuleProvider.h */, @@ -2026,6 +2022,7 @@ DE66F24008ABF03100323D32 /* MachineFunctionPass.h */, DE66F24108ABF03100323D32 /* MachineInstr.h */, DE66F24208ABF03100323D32 /* MachineInstrBuilder.h */, + CF6527D909D1A53400C4B521 /* MachineLocation.h */, DE66F24308ABF03100323D32 /* MachineRelocation.h */, DE66F24408ABF03100323D32 /* Passes.h */, DE66F24508ABF03100323D32 /* SchedGraphCommon.h */, @@ -2452,7 +2449,7 @@ ); }; buildToolPath = /usr/bin/make; - buildWorkingDirectory = /Volumes/Big2/llvm/llvm/lib; + buildWorkingDirectory = "$(SRCROOT)/../lib"; dependencies = ( ); name = "LLVM lib"; @@ -2479,7 +2476,7 @@ ); }; buildToolPath = /usr/bin/make; - buildWorkingDirectory = /Volumes/Big2/llvm/llvm/tools/llc; + buildWorkingDirectory = "$(SRCROOT)/../tools/llc"; dependencies = ( ); name = "LLVM llc"; From lattner at cs.uiuc.edu Sat Apr 8 01:47:06 2006 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Sat, 8 Apr 2006 01:47:06 -0500 Subject: [llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCISelLowering.cpp PPCISelLowering.h PPCInstrAltivec.td Message-ID: <200604080647.BAA21951@zion.cs.uiuc.edu> Changes in directory llvm/lib/Target/PowerPC: PPCISelLowering.cpp updated: 1.138 -> 1.139 PPCISelLowering.h updated: 1.44 -> 1.45 PPCInstrAltivec.td updated: 1.46 -> 1.47 --- Log message: Change the interface to the predicate that determines if vsplti* can be used. No functionality changes. --- Diffs of the changes: (+28 -32) PPCISelLowering.cpp | 33 +++++++++++++++++---------------- PPCISelLowering.h | 9 +++++---- PPCInstrAltivec.td | 18 ++++++------------ 3 files changed, 28 insertions(+), 32 deletions(-) Index: llvm/lib/Target/PowerPC/PPCISelLowering.cpp diff -u llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.138 llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.139 --- llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.138 Thu Apr 6 18:12:19 2006 +++ llvm/lib/Target/PowerPC/PPCISelLowering.cpp Sat Apr 8 01:46:53 2006 @@ -425,10 +425,11 @@ return cast(N->getOperand(0))->getValue() / EltSize; } -/// isVecSplatImm - Return true if this is a build_vector of constants which -/// can be formed by using a vspltis[bhw] instruction. The ByteSize field -/// indicates the number of bytes of each element [124] -> [bhw]. -bool PPC::isVecSplatImm(SDNode *N, unsigned ByteSize, char *Val) { +/// get_VSPLI_elt - If this is a build_vector of constants which can be formed +/// by using a vspltis[bhw] instruction of the specified element size, return +/// the constant being splatted. The ByteSize field indicates the number of +/// bytes of each element [124] -> [bhw]. +SDOperand PPC::get_VSPLI_elt(SDNode *N, unsigned ByteSize, SelectionDAG &DAG) { SDOperand OpVal(0, 0); // Check to see if this buildvec has a single non-undef value in its elements. for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) { @@ -436,10 +437,10 @@ if (OpVal.Val == 0) OpVal = N->getOperand(i); else if (OpVal != N->getOperand(i)) - return false; + return SDOperand(); } - if (OpVal.Val == 0) return false; // All UNDEF: use implicit def. + if (OpVal.Val == 0) return SDOperand(); // All UNDEF: use implicit def. unsigned ValSizeInBytes = 0; uint64_t Value = 0; @@ -455,7 +456,7 @@ // If the splat value is larger than the element value, then we can never do // this splat. The only case that we could fit the replicated bits into our // immediate field for would be zero, and we prefer to use vxor for it. - if (ValSizeInBytes < ByteSize) return false; + if (ValSizeInBytes < ByteSize) return SDOperand(); // If the element value is larger than the splat value, cut it in half and // check to see if the two halves are equal. Continue doing this until we @@ -466,7 +467,7 @@ // If the top half equals the bottom half, we're still ok. if (((Value >> (ValSizeInBytes*8)) & ((1 << (8*ValSizeInBytes))-1)) != (Value & ((1 << (8*ValSizeInBytes))-1))) - return false; + return SDOperand(); } // Properly sign extend the value. @@ -474,12 +475,12 @@ int MaskVal = ((int)Value << ShAmt) >> ShAmt; // If this is zero, don't match, zero matches ISD::isBuildVectorAllZeros. - if (MaskVal == 0) return false; + if (MaskVal == 0) return SDOperand(); - if (Val) *Val = MaskVal; - - // Finally, if this value fits in a 5 bit sext field, return true. - return ((MaskVal << (32-5)) >> (32-5)) == MaskVal; + // Finally, if this value fits in a 5 bit sext field, return it + if (((MaskVal << (32-5)) >> (32-5)) == MaskVal) + return DAG.getTargetConstant(MaskVal, MVT::i32); + return SDOperand(); } @@ -849,9 +850,9 @@ if (ISD::isBuildVectorAllZeros(Op.Val)) return Op; - if (PPC::isVecSplatImm(Op.Val, 1) || // vspltisb - PPC::isVecSplatImm(Op.Val, 2) || // vspltish - PPC::isVecSplatImm(Op.Val, 4)) // vspltisw + if (PPC::get_VSPLI_elt(Op.Val, 1, DAG).Val || // vspltisb + PPC::get_VSPLI_elt(Op.Val, 2, DAG).Val || // vspltish + PPC::get_VSPLI_elt(Op.Val, 4, DAG).Val) // vspltisw return Op; return SDOperand(); Index: llvm/lib/Target/PowerPC/PPCISelLowering.h diff -u llvm/lib/Target/PowerPC/PPCISelLowering.h:1.44 llvm/lib/Target/PowerPC/PPCISelLowering.h:1.45 --- llvm/lib/Target/PowerPC/PPCISelLowering.h:1.44 Thu Apr 6 17:28:36 2006 +++ llvm/lib/Target/PowerPC/PPCISelLowering.h Sat Apr 8 01:46:53 2006 @@ -131,10 +131,11 @@ /// specified isSplatShuffleMask VECTOR_SHUFFLE mask. unsigned getVSPLTImmediate(SDNode *N, unsigned EltSize); - /// isVecSplatImm - Return true if this is a build_vector of constants which - /// can be formed by using a vspltis[bhw] instruction. The ByteSize field - /// indicates the number of bytes of each element [124] -> [bhw]. - bool isVecSplatImm(SDNode *N, unsigned ByteSize, char *Val = 0); + /// get_VSPLI_elt - If this is a build_vector of constants which can be + /// formed by using a vspltis[bhw] instruction of the specified element + /// size, return the constant being splatted. The ByteSize field indicates + /// the number of bytes of each element [124] -> [bhw]. + SDOperand get_VSPLI_elt(SDNode *N, unsigned ByteSize, SelectionDAG &DAG); } class PPCTargetLowering : public TargetLowering { Index: llvm/lib/Target/PowerPC/PPCInstrAltivec.td diff -u llvm/lib/Target/PowerPC/PPCInstrAltivec.td:1.46 llvm/lib/Target/PowerPC/PPCInstrAltivec.td:1.47 --- llvm/lib/Target/PowerPC/PPCInstrAltivec.td:1.46 Thu Apr 6 17:28:36 2006 +++ llvm/lib/Target/PowerPC/PPCInstrAltivec.td Sat Apr 8 01:46:53 2006 @@ -111,32 +111,26 @@ // VSPLTISB_get_imm xform function: convert build_vector to VSPLTISB imm. def VSPLTISB_get_imm : SDNodeXForm; def vecspltisb : PatLeaf<(build_vector), [{ - return PPC::isVecSplatImm(N, 1); + return PPC::get_VSPLI_elt(N, 1, *CurDAG).Val != 0; }], VSPLTISB_get_imm>; // VSPLTISH_get_imm xform function: convert build_vector to VSPLTISH imm. def VSPLTISH_get_imm : SDNodeXForm; def vecspltish : PatLeaf<(build_vector), [{ - return PPC::isVecSplatImm(N, 2); + return PPC::get_VSPLI_elt(N, 2, *CurDAG).Val != 0; }], VSPLTISH_get_imm>; // VSPLTISW_get_imm xform function: convert build_vector to VSPLTISW imm. def VSPLTISW_get_imm : SDNodeXForm; def vecspltisw : PatLeaf<(build_vector), [{ - return PPC::isVecSplatImm(N, 4); + return PPC::get_VSPLI_elt(N, 4, *CurDAG).Val != 0; }], VSPLTISW_get_imm>; //===----------------------------------------------------------------------===// From lattner at cs.uiuc.edu Sat Apr 8 02:13:59 2006 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Sat, 8 Apr 2006 02:13:59 -0500 Subject: [llvm-commits] CVS: llvm/test/Regression/CodeGen/PowerPC/vec_shuffle.ll vec_spat.ll Message-ID: <200604080713.CAA24684@zion.cs.uiuc.edu> Changes in directory llvm/test/Regression/CodeGen/PowerPC: vec_shuffle.ll updated: 1.5 -> 1.6 vec_spat.ll updated: 1.3 -> 1.4 --- Log message: add new testcase --- Diffs of the changes: (+27 -1) vec_shuffle.ll | 16 ++++++++++++++++ vec_spat.ll | 12 +++++++++++- 2 files changed, 27 insertions(+), 1 deletion(-) Index: llvm/test/Regression/CodeGen/PowerPC/vec_shuffle.ll diff -u llvm/test/Regression/CodeGen/PowerPC/vec_shuffle.ll:1.5 llvm/test/Regression/CodeGen/PowerPC/vec_shuffle.ll:1.6 --- llvm/test/Regression/CodeGen/PowerPC/vec_shuffle.ll:1.5 Thu Apr 6 17:27:59 2006 +++ llvm/test/Regression/CodeGen/PowerPC/vec_shuffle.ll Sat Apr 8 02:13:46 2006 @@ -253,6 +253,21 @@ entry: %tmp = load <4 x int>* %A ; <<4 x int>> [#uses=2] %tmp2 = load <4 x int>* %B ; <<4 x int>> [#uses=2] + %tmp = extractelement <4 x int> %tmp2, uint 0 ; [#uses=1] + %tmp3 = extractelement <4 x int> %tmp, uint 0 ; [#uses=1] + %tmp4 = extractelement <4 x int> %tmp2, uint 1 ; [#uses=1] + %tmp5 = extractelement <4 x int> %tmp, uint 1 ; [#uses=1] + %tmp6 = insertelement <4 x int> undef, int %tmp, uint 0 ; <<4 x int>> [#uses=1] + %tmp7 = insertelement <4 x int> %tmp6, int %tmp3, uint 1 ; <<4 x int>> [#uses=1] + %tmp8 = insertelement <4 x int> %tmp7, int %tmp4, uint 2 ; <<4 x int>> [#uses=1] + %tmp9 = insertelement <4 x int> %tmp8, int %tmp5, uint 3 ; <<4 x int>> [#uses=1] + store <4 x int> %tmp9, <4 x int>* %A + ret void +} + +void %tw_h_flop(<4 x int>* %A, <4 x int>* %B) { + %tmp = load <4 x int>* %A ; <<4 x int>> [#uses=2] + %tmp2 = load <4 x int>* %B ; <<4 x int>> [#uses=2] %tmp = extractelement <4 x int> %tmp, uint 0 ; [#uses=1] %tmp3 = extractelement <4 x int> %tmp2, uint 0 ; [#uses=1] %tmp4 = extractelement <4 x int> %tmp, uint 1 ; [#uses=1] @@ -265,6 +280,7 @@ ret void } + void %VMRG_UNARY_tb_l(<16 x sbyte>* %A, <16 x sbyte>* %B) { entry: %tmp = load <16 x sbyte>* %A ; <<16 x sbyte>> [#uses=16] Index: llvm/test/Regression/CodeGen/PowerPC/vec_spat.ll diff -u llvm/test/Regression/CodeGen/PowerPC/vec_spat.ll:1.3 llvm/test/Regression/CodeGen/PowerPC/vec_spat.ll:1.4 --- llvm/test/Regression/CodeGen/PowerPC/vec_spat.ll:1.3 Tue Apr 4 12:20:45 2006 +++ llvm/test/Regression/CodeGen/PowerPC/vec_spat.ll Sat Apr 8 02:13:46 2006 @@ -1,7 +1,7 @@ ; Test that vectors are scalarized/lowered correctly. ; RUN: llvm-as < %s | llc -march=ppc32 -mcpu=g5 | grep vspltw | wc -l | grep 2 && ; RUN: llvm-as < %s | llc -march=ppc32 -mcpu=g3 | grep stfs | wc -l | grep 4 && -; RUN: llvm-as < %s | llc -march=ppc32 -mcpu=g5 | grep vsplti | wc -l | grep 2 && +; RUN: llvm-as < %s | llc -march=ppc32 -mcpu=g5 | grep vsplti | wc -l | grep 3 && ; RUN: llvm-as < %s | llc -march=ppc32 -mcpu=g5 | grep vsplth | wc -l | grep 1 %f4 = type <4 x float> @@ -59,3 +59,13 @@ ret void } +void %spltish(<16 x ubyte>* %A, <16 x ubyte>* %B) { + ; Gets converted to 16 x ubyte + %tmp = load <16 x ubyte>* %B + %tmp = cast <16 x ubyte> %tmp to <16 x sbyte> + %tmp4 = sub <16 x sbyte> %tmp, cast (<8 x short> < short 15, short 15, short 15, short 15, short 15, short 15, short 15, short 15 > to <16 x sbyte>) + %tmp4 = cast <16 x sbyte> %tmp4 to <16 x ubyte> + store <16 x ubyte> %tmp4, <16 x ubyte>* %A + ret void +} + From lattner at cs.uiuc.edu Sat Apr 8 02:14:39 2006 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Sat, 8 Apr 2006 02:14:39 -0500 Subject: [llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCISelLowering.cpp Message-ID: <200604080714.CAA24980@zion.cs.uiuc.edu> Changes in directory llvm/lib/Target/PowerPC: PPCISelLowering.cpp updated: 1.139 -> 1.140 --- Log message: Implement PowerPC/CodeGen/vec_splat.ll:spltish to use vsplish instead of a constant pool load. --- Diffs of the changes: (+57 -0) PPCISelLowering.cpp | 57 ++++++++++++++++++++++++++++++++++++++++++++++++++++ 1 files changed, 57 insertions(+) Index: llvm/lib/Target/PowerPC/PPCISelLowering.cpp diff -u llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.139 llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.140 --- llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.139 Sat Apr 8 01:46:53 2006 +++ llvm/lib/Target/PowerPC/PPCISelLowering.cpp Sat Apr 8 02:14:26 2006 @@ -431,6 +431,63 @@ /// bytes of each element [124] -> [bhw]. SDOperand PPC::get_VSPLI_elt(SDNode *N, unsigned ByteSize, SelectionDAG &DAG) { SDOperand OpVal(0, 0); + + // If ByteSize of the splat is bigger than the element size of the + // build_vector, then we have a case where we are checking for a splat where + // multiple elements of the buildvector are folded together into a single + // logical element of the splat (e.g. "vsplish 1" to splat {0,1}*8). + unsigned EltSize = 16/N->getNumOperands(); + if (EltSize < ByteSize) { + unsigned Multiple = ByteSize/EltSize; // Number of BV entries per spltval. + SDOperand UniquedVals[4]; + assert(Multiple > 1 && Multiple <= 4 && "How can this happen?"); + + // See if all of the elements in the buildvector agree across. + for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) { + if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue; + // If the element isn't a constant, bail fully out. + if (!isa(N->getOperand(i))) return SDOperand(); + + + if (UniquedVals[i&(Multiple-1)].Val == 0) + UniquedVals[i&(Multiple-1)] = N->getOperand(i); + else if (UniquedVals[i&(Multiple-1)] != N->getOperand(i)) + return SDOperand(); // no match. + } + + // Okay, if we reached this point, UniquedVals[0..Multiple-1] contains + // either constant or undef values that are identical for each chunk. See + // if these chunks can form into a larger vspltis*. + + // Check to see if all of the leading entries are either 0 or -1. If + // neither, then this won't fit into the immediate field. + bool LeadingZero = true; + bool LeadingOnes = true; + for (unsigned i = 0; i != Multiple-1; ++i) { + if (UniquedVals[i].Val == 0) continue; // Must have been undefs. + + LeadingZero &= cast(UniquedVals[i])->isNullValue(); + LeadingOnes &= cast(UniquedVals[i])->isAllOnesValue(); + } + // Finally, check the least significant entry. + if (LeadingZero) { + if (UniquedVals[Multiple-1].Val == 0) + return DAG.getTargetConstant(0, MVT::i32); // 0,0,0,undef + int Val = cast(UniquedVals[Multiple-1])->getValue(); + if (Val < 16) + return DAG.getTargetConstant(Val, MVT::i32); // 0,0,0,4 -> vspltisw(4) + } + if (LeadingOnes) { + if (UniquedVals[Multiple-1].Val == 0) + return DAG.getTargetConstant(~0U, MVT::i32); // -1,-1,-1,undef + int Val =cast(UniquedVals[Multiple-1])->getSignExtended(); + if (Val >= -16) // -1,-1,-1,-2 -> vspltisw(-2) + return DAG.getTargetConstant(Val, MVT::i32); + } + + return SDOperand(); + } + // Check to see if this buildvec has a single non-undef value in its elements. for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) { if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue; From natebegeman at mac.com Sat Apr 8 14:47:10 2006 From: natebegeman at mac.com (Nate Begeman) Date: Sat, 8 Apr 2006 14:47:10 -0500 Subject: [llvm-commits] CVS: llvm/lib/Target/Alpha/AlphaTargetMachine.cpp Message-ID: <200604081947.OAA03546@zion.cs.uiuc.edu> Changes in directory llvm/lib/Target/Alpha: AlphaTargetMachine.cpp updated: 1.22 -> 1.23 --- Log message: Disable switch lowering for targets based on the selection dag isel, letting the code generator handle them directly. --- Diffs of the changes: (+0 -6) AlphaTargetMachine.cpp | 6 ------ 1 files changed, 6 deletions(-) Index: llvm/lib/Target/Alpha/AlphaTargetMachine.cpp diff -u llvm/lib/Target/Alpha/AlphaTargetMachine.cpp:1.22 llvm/lib/Target/Alpha/AlphaTargetMachine.cpp:1.23 --- llvm/lib/Target/Alpha/AlphaTargetMachine.cpp:1.22 Wed Mar 22 23:43:15 2006 +++ llvm/lib/Target/Alpha/AlphaTargetMachine.cpp Sat Apr 8 14:46:55 2006 @@ -81,9 +81,6 @@ // FIXME: Implement the invoke/unwind instructions! PM.add(createLowerInvokePass()); - // FIXME: Implement the switch instruction in the instruction selector! - PM.add(createLowerSwitchPass()); - // Make sure that no unreachable blocks are instruction selected. PM.add(createUnreachableBlockEliminationPass()); @@ -119,9 +116,6 @@ // FIXME: Implement the invoke/unwind instructions! PM.add(createLowerInvokePass()); - // FIXME: Implement the switch instruction in the instruction selector! - PM.add(createLowerSwitchPass()); - // Make sure that no unreachable blocks are instruction selected. PM.add(createUnreachableBlockEliminationPass()); From natebegeman at mac.com Sat Apr 8 14:47:10 2006 From: natebegeman at mac.com (Nate Begeman) Date: Sat, 8 Apr 2006 14:47:10 -0500 Subject: [llvm-commits] CVS: llvm/lib/Target/IA64/IA64TargetMachine.cpp Message-ID: <200604081947.OAA03550@zion.cs.uiuc.edu> Changes in directory llvm/lib/Target/IA64: IA64TargetMachine.cpp updated: 1.13 -> 1.14 --- Log message: Disable switch lowering for targets based on the selection dag isel, letting the code generator handle them directly. --- Diffs of the changes: (+0 -3) IA64TargetMachine.cpp | 3 --- 1 files changed, 3 deletions(-) Index: llvm/lib/Target/IA64/IA64TargetMachine.cpp diff -u llvm/lib/Target/IA64/IA64TargetMachine.cpp:1.13 llvm/lib/Target/IA64/IA64TargetMachine.cpp:1.14 --- llvm/lib/Target/IA64/IA64TargetMachine.cpp:1.13 Wed Mar 22 23:43:15 2006 +++ llvm/lib/Target/IA64/IA64TargetMachine.cpp Sat Apr 8 14:46:55 2006 @@ -96,9 +96,6 @@ PM.add(createLowerInvokePass(704, 16)); // on ia64 linux, jmpbufs are 704 // bytes and must be 16byte aligned - // FIXME: Implement the switch instruction in the instruction selector! - PM.add(createLowerSwitchPass()); - // Make sure that no unreachable blocks are instruction selected. PM.add(createUnreachableBlockEliminationPass()); From natebegeman at mac.com Sat Apr 8 14:47:11 2006 From: natebegeman at mac.com (Nate Begeman) Date: Sat, 8 Apr 2006 14:47:11 -0500 Subject: [llvm-commits] CVS: llvm/lib/Target/X86/X86TargetMachine.cpp Message-ID: <200604081947.OAA03554@zion.cs.uiuc.edu> Changes in directory llvm/lib/Target/X86: X86TargetMachine.cpp updated: 1.111 -> 1.112 --- Log message: Disable switch lowering for targets based on the selection dag isel, letting the code generator handle them directly. --- Diffs of the changes: (+0 -10) X86TargetMachine.cpp | 10 ---------- 1 files changed, 10 deletions(-) Index: llvm/lib/Target/X86/X86TargetMachine.cpp diff -u llvm/lib/Target/X86/X86TargetMachine.cpp:1.111 llvm/lib/Target/X86/X86TargetMachine.cpp:1.112 --- llvm/lib/Target/X86/X86TargetMachine.cpp:1.111 Sun Mar 26 19:32:24 2006 +++ llvm/lib/Target/X86/X86TargetMachine.cpp Sat Apr 8 14:46:55 2006 @@ -36,8 +36,6 @@ cl::opt DisableOutput("disable-x86-llc-output", cl::Hidden, cl::desc("Disable the X86 asm printer, for use " "when profiling the code generator.")); - cl::opt DisableLowerSwitch("disable-lower-switch", cl::Hidden, - cl::desc("Disable the LowerSwitch pass")); // Register the target. RegisterTarget X("x86", " IA-32 (Pentium and above)"); } @@ -100,10 +98,6 @@ // FIXME: Implement the invoke/unwind instructions! PM.add(createLowerInvokePass()); - // FIXME: Implement the switch instruction in the instruction selector! - if (!DisableLowerSwitch) - PM.add(createLowerSwitchPass()); - // Make sure that no unreachable blocks are instruction selected. PM.add(createUnreachableBlockEliminationPass()); @@ -169,10 +163,6 @@ // FIXME: Implement the invoke/unwind instructions! PM.add(createLowerInvokePass()); - // FIXME: Implement the switch instruction in the instruction selector! - if (!DisableLowerSwitch) - PM.add(createLowerSwitchPass()); - // Make sure that no unreachable blocks are instruction selected. PM.add(createUnreachableBlockEliminationPass()); From natebegeman at mac.com Sat Apr 8 14:47:11 2006 From: natebegeman at mac.com (Nate Begeman) Date: Sat, 8 Apr 2006 14:47:11 -0500 Subject: [llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCTargetMachine.cpp Message-ID: <200604081947.OAA03558@zion.cs.uiuc.edu> Changes in directory llvm/lib/Target/PowerPC: PPCTargetMachine.cpp updated: 1.85 -> 1.86 --- Log message: Disable switch lowering for targets based on the selection dag isel, letting the code generator handle them directly. --- Diffs of the changes: (+0 -6) PPCTargetMachine.cpp | 6 ------ 1 files changed, 6 deletions(-) Index: llvm/lib/Target/PowerPC/PPCTargetMachine.cpp diff -u llvm/lib/Target/PowerPC/PPCTargetMachine.cpp:1.85 llvm/lib/Target/PowerPC/PPCTargetMachine.cpp:1.86 --- llvm/lib/Target/PowerPC/PPCTargetMachine.cpp:1.85 Wed Mar 22 23:43:15 2006 +++ llvm/lib/Target/PowerPC/PPCTargetMachine.cpp Sat Apr 8 14:46:55 2006 @@ -93,9 +93,6 @@ // Clean up after other passes, e.g. merging critical edges. if (!Fast) PM.add(createCFGSimplificationPass()); - // FIXME: Implement the switch instruction in the instruction selector! - PM.add(createLowerSwitchPass()); - // Make sure that no unreachable blocks are instruction selected. PM.add(createUnreachableBlockEliminationPass()); @@ -147,9 +144,6 @@ // Clean up after other passes, e.g. merging critical edges. PM.add(createCFGSimplificationPass()); - // FIXME: Implement the switch instruction in the instruction selector! - PM.add(createLowerSwitchPass()); - // Make sure that no unreachable blocks are instruction selected. PM.add(createUnreachableBlockEliminationPass()); From natebegeman at mac.com Sat Apr 8 14:47:11 2006 From: natebegeman at mac.com (Nate Begeman) Date: Sat, 8 Apr 2006 14:47:11 -0500 Subject: [llvm-commits] CVS: llvm/lib/Target/Sparc/SparcTargetMachine.cpp Message-ID: <200604081947.OAA03562@zion.cs.uiuc.edu> Changes in directory llvm/lib/Target/Sparc: SparcTargetMachine.cpp updated: 1.43 -> 1.44 --- Log message: Disable switch lowering for targets based on the selection dag isel, letting the code generator handle them directly. --- Diffs of the changes: (+0 -3) SparcTargetMachine.cpp | 3 --- 1 files changed, 3 deletions(-) Index: llvm/lib/Target/Sparc/SparcTargetMachine.cpp diff -u llvm/lib/Target/Sparc/SparcTargetMachine.cpp:1.43 llvm/lib/Target/Sparc/SparcTargetMachine.cpp:1.44 --- llvm/lib/Target/Sparc/SparcTargetMachine.cpp:1.43 Wed Mar 22 23:43:15 2006 +++ llvm/lib/Target/Sparc/SparcTargetMachine.cpp Sat Apr 8 14:46:55 2006 @@ -72,9 +72,6 @@ // FIXME: implement the invoke/unwind instructions! PM.add(createLowerInvokePass()); - // FIXME: implement the switch instruction in the instruction selector. - PM.add(createLowerSwitchPass()); - // Print LLVM code input to instruction selector: if (PrintMachineCode) PM.add(new PrintFunctionPass()); From lattner at cs.uiuc.edu Sat Apr 8 16:16:29 2006 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Sat, 8 Apr 2006 16:16:29 -0500 Subject: [llvm-commits] CVS: llvm-test/Makefile.programs Message-ID: <200604082116.QAA04018@zion.cs.uiuc.edu> Changes in directory llvm-test: Makefile.programs updated: 1.202 -> 1.203 --- Log message: switch back to fastcc for x86 llcbeta --- Diffs of the changes: (+1 -1) Makefile.programs | 2 +- 1 files changed, 1 insertion(+), 1 deletion(-) Index: llvm-test/Makefile.programs diff -u llvm-test/Makefile.programs:1.202 llvm-test/Makefile.programs:1.203 --- llvm-test/Makefile.programs:1.202 Sun Mar 26 19:34:00 2006 +++ llvm-test/Makefile.programs Sat Apr 8 16:16:16 2006 @@ -197,7 +197,7 @@ LLCBETAOPTION := -sched=simple endif ifeq ($(ARCH),x86) -LLCBETAOPTION := -disable-lower-switch +LLCBETAOPTION := -enable-x86-fastcc endif ifeq ($(ARCH),Sparc) LLCBETAOPTION := -enable-sparc-v9-insts From lattner at cs.uiuc.edu Sat Apr 8 17:16:13 2006 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Sat, 8 Apr 2006 17:16:13 -0500 Subject: [llvm-commits] CVS: llvm/include/llvm/CodeGen/SelectionDAGNodes.h Message-ID: <200604082216.RAA04227@zion.cs.uiuc.edu> Changes in directory llvm/include/llvm/CodeGen: SelectionDAGNodes.h updated: 1.126 -> 1.127 --- Log message: Add a new VSELECT node. --- Diffs of the changes: (+5 -0) SelectionDAGNodes.h | 5 +++++ 1 files changed, 5 insertions(+) Index: llvm/include/llvm/CodeGen/SelectionDAGNodes.h diff -u llvm/include/llvm/CodeGen/SelectionDAGNodes.h:1.126 llvm/include/llvm/CodeGen/SelectionDAGNodes.h:1.127 --- llvm/include/llvm/CodeGen/SelectionDAGNodes.h:1.126 Sat Apr 1 20:28:52 2006 +++ llvm/include/llvm/CodeGen/SelectionDAGNodes.h Sat Apr 8 17:16:01 2006 @@ -230,6 +230,11 @@ VADD, VSUB, VMUL, VSDIV, VUDIV, VAND, VOR, VXOR, + /// VSELECT(COND,LHS,RHS, COUNT,TYPE) - Select for MVT::Vector values. + /// COND is a boolean value. This node return LHS if COND is true, RHS if + /// COND is false. + VSELECT, + /// SCALAR_TO_VECTOR(VAL) - This represents the operation of loading a /// scalar value into the low element of the resultant vector type. The top /// elements of the vector are undefined. From lattner at cs.uiuc.edu Sat Apr 8 17:23:09 2006 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Sat, 8 Apr 2006 17:23:09 -0500 Subject: [llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp SelectionDAG.cpp SelectionDAGISel.cpp Message-ID: <200604082223.RAA04307@zion.cs.uiuc.edu> Changes in directory llvm/lib/CodeGen/SelectionDAG: LegalizeDAG.cpp updated: 1.356 -> 1.357 SelectionDAG.cpp updated: 1.296 -> 1.297 SelectionDAGISel.cpp updated: 1.220 -> 1.221 --- Log message: Add code generator support for VSELECT --- Diffs of the changes: (+22 -10) LegalizeDAG.cpp | 5 +++++ SelectionDAG.cpp | 17 +++++++++-------- SelectionDAGISel.cpp | 10 ++++++++-- 3 files changed, 22 insertions(+), 10 deletions(-) Index: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp diff -u llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.356 llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.357 --- llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.356 Sat Apr 8 00:34:25 2006 +++ llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp Sat Apr 8 17:22:57 2006 @@ -4773,6 +4773,11 @@ assert(0 && "Cast from unsupported vector type not implemented yet!"); } } + case ISD::VSELECT: + Result = DAG.getNode(ISD::SELECT, NewVT, Op.getOperand(0), + PackVectorOp(Op.getOperand(1), NewVT), + PackVectorOp(Op.getOperand(2), NewVT)); + break; } if (TLI.isTypeLegal(NewVT)) Index: llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp diff -u llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp:1.296 llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp:1.297 --- llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp:1.296 Mon Apr 3 20:02:22 2006 +++ llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp Sat Apr 8 17:22:57 2006 @@ -2760,15 +2760,16 @@ case ISD::SETCC: return "setcc"; case ISD::SELECT: return "select"; case ISD::SELECT_CC: return "select_cc"; - case ISD::INSERT_VECTOR_ELT: return "insert_vector_elt"; - case ISD::VINSERT_VECTOR_ELT: return "vinsert_vector_elt"; - case ISD::EXTRACT_VECTOR_ELT: return "extract_vector_elt"; + case ISD::VSELECT: return "vselect"; + case ISD::INSERT_VECTOR_ELT: return "insert_vector_elt"; + case ISD::VINSERT_VECTOR_ELT: return "vinsert_vector_elt"; + case ISD::EXTRACT_VECTOR_ELT: return "extract_vector_elt"; case ISD::VEXTRACT_VECTOR_ELT: return "vextract_vector_elt"; - case ISD::SCALAR_TO_VECTOR: return "scalar_to_vector"; - case ISD::VBUILD_VECTOR: return "vbuild_vector"; - case ISD::VECTOR_SHUFFLE: return "vector_shuffle"; - case ISD::VVECTOR_SHUFFLE: return "vvector_shuffle"; - case ISD::VBIT_CONVERT: return "vbit_convert"; + case ISD::SCALAR_TO_VECTOR: return "scalar_to_vector"; + case ISD::VBUILD_VECTOR: return "vbuild_vector"; + case ISD::VECTOR_SHUFFLE: return "vector_shuffle"; + case ISD::VVECTOR_SHUFFLE: return "vvector_shuffle"; + case ISD::VBIT_CONVERT: return "vbit_convert"; case ISD::ADDC: return "addc"; case ISD::ADDE: return "adde"; case ISD::SUBC: return "subc"; Index: llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp diff -u llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.220 llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.221 --- llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.220 Fri Apr 7 23:15:24 2006 +++ llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp Sat Apr 8 17:22:57 2006 @@ -992,8 +992,14 @@ SDOperand Cond = getValue(I.getOperand(0)); SDOperand TrueVal = getValue(I.getOperand(1)); SDOperand FalseVal = getValue(I.getOperand(2)); - setValue(&I, DAG.getNode(ISD::SELECT, TrueVal.getValueType(), Cond, - TrueVal, FalseVal)); + if (!isa(I.getType())) { + setValue(&I, DAG.getNode(ISD::SELECT, TrueVal.getValueType(), Cond, + TrueVal, FalseVal)); + } else { + setValue(&I, DAG.getNode(ISD::VSELECT, MVT::Vector, Cond, TrueVal, FalseVal, + *(TrueVal.Val->op_end()-2), + *(TrueVal.Val->op_end()-1))); + } } void SelectionDAGLowering::visitCast(User &I) { From lattner at cs.uiuc.edu Sat Apr 8 17:45:21 2006 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Sat, 8 Apr 2006 17:45:21 -0500 Subject: [llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp PPCISelLowering.cpp PPCInstrInfo.td Message-ID: <200604082245.RAA04485@zion.cs.uiuc.edu> Changes in directory llvm/lib/Target/PowerPC: PPCISelDAGToDAG.cpp updated: 1.178 -> 1.179 PPCISelLowering.cpp updated: 1.140 -> 1.141 PPCInstrInfo.td updated: 1.214 -> 1.215 --- Log message: Add VRRC select support --- Diffs of the changes: (+8 -2) PPCISelDAGToDAG.cpp | 5 ++++- PPCISelLowering.cpp | 3 ++- PPCInstrInfo.td | 2 ++ 3 files changed, 8 insertions(+), 2 deletions(-) Index: llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp diff -u llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp:1.178 llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp:1.179 --- llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp:1.178 Sun Mar 26 04:06:40 2006 +++ llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp Sat Apr 8 17:45:08 2006 @@ -1219,8 +1219,11 @@ SelectCCOp = PPC::SELECT_CC_Int; else if (N->getValueType(0) == MVT::f32) SelectCCOp = PPC::SELECT_CC_F4; - else + else if (N->getValueType(0) == MVT::f64) SelectCCOp = PPC::SELECT_CC_F8; + else + SelectCCOp = PPC::SELECT_CC_VRRC; + SDOperand N2, N3; Select(N2, N->getOperand(2)); Select(N3, N->getOperand(3)); Index: llvm/lib/Target/PowerPC/PPCISelLowering.cpp diff -u llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.140 llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.141 --- llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.140 Sat Apr 8 02:14:26 2006 +++ llvm/lib/Target/PowerPC/PPCISelLowering.cpp Sat Apr 8 17:45:08 2006 @@ -1484,7 +1484,8 @@ MachineBasicBlock *BB) { assert((MI->getOpcode() == PPC::SELECT_CC_Int || MI->getOpcode() == PPC::SELECT_CC_F4 || - MI->getOpcode() == PPC::SELECT_CC_F8) && + MI->getOpcode() == PPC::SELECT_CC_F8 || + MI->getOpcode() == PPC::SELECT_CC_VRRC) && "Unexpected instr type to insert"); // To "insert" a SELECT_CC instruction, we actually have to insert the diamond Index: llvm/lib/Target/PowerPC/PPCInstrInfo.td diff -u llvm/lib/Target/PowerPC/PPCInstrInfo.td:1.214 llvm/lib/Target/PowerPC/PPCInstrInfo.td:1.215 --- llvm/lib/Target/PowerPC/PPCInstrInfo.td:1.214 Thu Mar 30 23:13:27 2006 +++ llvm/lib/Target/PowerPC/PPCInstrInfo.td Sat Apr 8 17:45:08 2006 @@ -247,6 +247,8 @@ i32imm:$BROPC), "; SELECT_CC PSEUDO!", []>; def SELECT_CC_F8 : Pseudo<(ops F8RC:$dst, CRRC:$cond, F8RC:$T, F8RC:$F, i32imm:$BROPC), "; SELECT_CC PSEUDO!", []>; + def SELECT_CC_VRRC: Pseudo<(ops VRRC:$dst, CRRC:$cond, VRRC:$T, VRRC:$F, + i32imm:$BROPC), "; SELECT_CC PSEUDO!", []>; } let isTerminator = 1, noResults = 1, PPC970_Unit = 7 in { From lattner at cs.uiuc.edu Sat Apr 8 17:59:28 2006 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Sat, 8 Apr 2006 17:59:28 -0500 Subject: [llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCISelLowering.cpp Message-ID: <200604082259.RAA04582@zion.cs.uiuc.edu> Changes in directory llvm/lib/Target/PowerPC: PPCISelLowering.cpp updated: 1.141 -> 1.142 --- Log message: properly mark vector selects as expanded to select_cc --- Diffs of the changes: (+4 -0) PPCISelLowering.cpp | 4 ++++ 1 files changed, 4 insertions(+) Index: llvm/lib/Target/PowerPC/PPCISelLowering.cpp diff -u llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.141 llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.142 --- llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.141 Sat Apr 8 17:45:08 2006 +++ llvm/lib/Target/PowerPC/PPCISelLowering.cpp Sat Apr 8 17:59:15 2006 @@ -87,6 +87,10 @@ setOperationAction(ISD::SELECT, MVT::i32, Expand); setOperationAction(ISD::SELECT, MVT::f32, Expand); setOperationAction(ISD::SELECT, MVT::f64, Expand); + setOperationAction(ISD::SELECT, MVT::v4f32, Expand); + setOperationAction(ISD::SELECT, MVT::v4i32, Expand); + setOperationAction(ISD::SELECT, MVT::v8i16, Expand); + setOperationAction(ISD::SELECT, MVT::v16i8, Expand); // PowerPC wants to turn select_cc of FP into fsel when possible. setOperationAction(ISD::SELECT_CC, MVT::f32, Custom); From lattner at cs.uiuc.edu Sat Apr 8 18:07:17 2006 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Sat, 8 Apr 2006 18:07:17 -0500 Subject: [llvm-commits] CVS: llvm/docs/LangRef.html Message-ID: <200604082307.SAA04690@zion.cs.uiuc.edu> Changes in directory llvm/docs: LangRef.html updated: 1.146 -> 1.147 --- Log message: Move the vector instructions to their own subsection. --- Diffs of the changes: (+490 -467) LangRef.html | 957 ++++++++++++++++++++++++++++++----------------------------- 1 files changed, 490 insertions(+), 467 deletions(-) Index: llvm/docs/LangRef.html diff -u llvm/docs/LangRef.html:1.146 llvm/docs/LangRef.html:1.147 --- llvm/docs/LangRef.html:1.146 Fri Apr 7 23:40:53 2006 +++ llvm/docs/LangRef.html Sat Apr 8 18:07:04 2006 @@ -91,6 +91,16 @@
  • 'shr' Instruction
  • +
  • Vector Operations +
      +
    1. 'extractelement' Instruction
    2. +
    3. 'insertelement' Instruction
    4. +
    5. 'shufflevector' Instruction
    6. +
    7. 'vsetint' Instruction
    8. +
    9. 'vsetfp' Instruction
    10. +
    11. 'vselect' Instruction
    12. +
    +
  • Memory Access Operations
    1. 'malloc' Instruction
    2. @@ -106,12 +116,6 @@
    3. 'phi' Instruction
    4. 'cast .. to' Instruction
    5. 'select' Instruction
    6. -
    7. 'vsetint' Instruction
    8. -
    9. 'vsetfp' Instruction
    10. -
    11. 'vselect' Instruction
    12. -
    13. 'extractelement' Instruction
    14. -
    15. 'insertelement' Instruction
    16. -
    17. 'shufflevector' Instruction
    18. 'call' Instruction
    19. 'va_arg' Instruction
    @@ -1896,21 +1900,23 @@
    -

    A key design point of an SSA-based representation is how it -represents memory. In LLVM, no memory locations are in SSA form, which -makes things very simple. This section describes how to read, write, -allocate, and free memory in LLVM.

    +

    LLVM supports several instructions to represent vector operations in a +target-independent manner. This instructions cover the element-access and +vector-specific operations needed to process vectors effectively. While LLVM +does directly support these vector operations, many sophisticated algorithms +will want to use target-specific intrinsics to take full advantage of a specific +target.

    @@ -1918,48 +1924,45 @@
    Syntax:
    -  <result> = malloc <type>[, uint <NumElements>][, align <alignment>]     ; yields {type*}:result
    +  <result> = extractelement <n x <ty>> <val>, uint <idx>    ; yields <ty>
     
    Overview:
    -

    The 'malloc' instruction allocates memory from the system -heap and returns a pointer to it.

    +

    +The 'extractelement' instruction extracts a single scalar +element from a packed vector at a specified index. +

    -
    Arguments:
    -

    The 'malloc' instruction allocates -sizeof(<type>)*NumElements -bytes of memory from the operating system and returns a pointer of the -appropriate type to the program. If "NumElements" is specified, it is the -number of elements allocated. If an alignment is specified, the value result -of the allocation is guaranteed to be aligned to at least that boundary. If -not specified, or if zero, the target can choose to align the allocation on any -convenient boundary.

    +
    Arguments:
    -

    'type' must be a sized type.

    +

    +The first operand of an 'extractelement' instruction is a +value of packed type. The second operand is +an index indicating the position from which to extract the element. +The index may be a variable.

    Semantics:
    -

    Memory is allocated using the system "malloc" function, and -a pointer is returned.

    +

    +The result is a scalar of the same type as the element type of +val. Its value is the value at position idx of +val. If idx exceeds the length of val, the +results are undefined. +

    Example:
    -  %array  = malloc [4 x ubyte ]                    ; yields {[%4 x ubyte]*}:array
    -
    -  %size   = add uint 2, 2                          ; yields {uint}:size = uint 4
    -  %array1 = malloc ubyte, uint 4                   ; yields {ubyte*}:array1
    -  %array2 = malloc [12 x ubyte], uint %size        ; yields {[12 x ubyte]*}:array2
    -  %array3 = malloc int, uint 4, align 1024         ; yields {int*}:array3
    -  %array4 = malloc int, align 1024                 ; yields {int*}:array4
    +  %result = extractelement <4 x int> %vec, uint 0    ; yields int
     
    +
    @@ -1967,36 +1970,45 @@
    Syntax:
    -  free <type> <value>                              ; yields {void}
    +  <result> = insertelement <n x <ty>> <val>, <ty> <elt>, uint <idx>    ; yields <n x <ty>>
     
    Overview:
    -

    The 'free' instruction returns memory back to the unused -memory heap to be reallocated in the future.

    +

    +The 'insertelement' instruction inserts a scalar +element into a packed vector at a specified index. +

    +
    Arguments:
    -

    'value' shall be a pointer value that points to a value -that was allocated with the 'malloc' -instruction.

    +

    +The first operand of an 'insertelement' instruction is a +value of packed type. The second operand is a +scalar value whose type must equal the element type of the first +operand. The third operand is an index indicating the position at +which to insert the value. The index may be a variable.

    Semantics:
    -

    Access to the memory pointed to by the pointer is no longer defined -after this instruction executes.

    +

    +The result is a packed vector of the same type as val. Its +element values are those of val except at position +idx, where it gets the value elt. If idx +exceeds the length of val, the results are undefined. +

    Example:
    -  %array  = malloc [4 x ubyte]                    ; yields {[4 x ubyte]*}:array
    -            free   [4 x ubyte]* %array
    +  %result = insertelement <4 x int> %vec, int 1, uint 0    ; yields <4 x int>
     
    @@ -2004,243 +2016,255 @@
    Syntax:
    -  <result> = alloca <type>[, uint <NumElements>][, align <alignment>]     ; yields {type*}:result
    +  <result> = shufflevector <n x <ty>> <v1>, <n x <ty>> <v2>, <n x uint> <mask>    ; yields <n x <ty>>
     
    Overview:
    -

    The 'alloca' instruction allocates memory on the current -stack frame of the procedure that is live until the current function -returns to its caller.

    +

    +The 'shufflevector' instruction constructs a permutation of elements +from two input vectors, returning a vector of the same type. +

    Arguments:
    -

    The 'alloca' instruction allocates sizeof(<type>)*NumElements -bytes of memory on the runtime stack, returning a pointer of the -appropriate type to the program. If "NumElements" is specified, it is the -number of elements allocated. If an alignment is specified, the value result -of the allocation is guaranteed to be aligned to at least that boundary. If -not specified, or if zero, the target can choose to align the allocation on any -convenient boundary.

    +

    +The first two operands of a 'shufflevector' instruction are vectors +with types that match each other and types that match the result of the +instruction. The third argument is a shuffle mask, which has the same number +of elements as the other vector type, but whose element type is always 'uint'. +

    -

    'type' may be any sized type.

    +

    +The shuffle mask operand is required to be a constant vector with either +constant integer or undef values. +

    Semantics:
    -

    Memory is allocated; a pointer is returned. 'alloca'd -memory is automatically released when the function returns. The 'alloca' -instruction is commonly used to represent automatic variables that must -have an address available. When the function returns (either with the ret or unwind -instructions), the memory is reclaimed.

    +

    +The elements of the two input vectors are numbered from left to right across +both of the vectors. The shuffle mask operand specifies, for each element of +the result vector, which element of the two input registers the result element +gets. The element selector may be undef (meaning "don't care") and the second +operand may be undef if performing a shuffle from only one vector. +

    Example:
    -  %ptr = alloca int                              ; yields {int*}:ptr
    -  %ptr = alloca int, uint 4                      ; yields {int*}:ptr
    -  %ptr = alloca int, uint 4, align 1024          ; yields {int*}:ptr
    -  %ptr = alloca int, align 1024                  ; yields {int*}:ptr
    +  %result = shufflevector <4 x int> %v1, <4 x int> %v2, 
    +                          <4 x uint> <uint 0, uint 4, uint 1, uint 5>    ; yields <4 x int>
    +  %result = shufflevector <4 x int> %v1, <4 x int> undef, 
    +                          <4 x uint> <uint 0, uint 1, uint 2, uint 3>  ; yields <4 x int> - Identity shuffle.
     
    + -
    'load' +
    Syntax:
    -
      <result> = load <ty>* <pointer>
    <result> = volatile load <ty>* <pointer>
    -
    Overview:
    -

    The 'load' instruction is used to read from memory.

    -
    Arguments:
    -

    The argument to the 'load' instruction specifies the memory -address from which to load. The pointer must point to a first class type. If the load is -marked as volatile, then the optimizer is not allowed to modify -the number or order of execution of this load with other -volatile load and store -instructions.

    -
    Semantics:
    -

    The location of memory pointed to is loaded.

    -
    Examples:
    -
      %ptr = alloca int                               ; yields {int*}:ptr
    -  store int 3, int* %ptr                          ; yields {void}
    -  %val = load int* %ptr                           ; yields {int}:val = int 3
    -
    -
    - - -
    Syntax:
    -
      store <ty> <value>, <ty>* <pointer>                   ; yields {void}
    -  volatile store <ty> <value>, <ty>* <pointer>                   ; yields {void}
    +
    <result> = vsetint <op>, <n x <ty>> <var1>, <var2>   ; yields <n x bool>
     
    +
    Overview:
    -

    The 'store' instruction is used to write to memory.

    + +

    The 'vsetint' instruction takes two integer vectors and +returns a vector of boolean values representing, at each position, the +result of the comparison between the values at that position in the +two operands.

    +
    Arguments:
    -

    There are two arguments to the 'store' instruction: a value -to store and an address in which to store it. The type of the '<pointer>' -operand must be a pointer to the type of the '<value>' -operand. If the store is marked as volatile, then the -optimizer is not allowed to modify the number or order of execution of -this store with other volatile load and store instructions.

    + +

    The arguments to a 'vsetint' instruction are a comparison +operation and two value arguments. The value arguments must be of integral packed type, +and they must have identical types. The operation argument must be +one of eq, ne, slt, sgt, +sle, sge, ult, ugt, ule, +uge, true, and false. The result is a +packed bool value with the same length as each operand.

    +
    Semantics:
    -

    The contents of memory are updated to contain '<value>' -at the location specified by the '<pointer>' operand.

    + +

    The following table shows the semantics of 'vsetint'. For +each position of the result, the comparison is done on the +corresponding positions of the two value arguments. Note that the +signedness of the comparison depends on the comparison opcode and +not on the signedness of the value operands. E.g., vsetint +slt <4 x unsigned> %x, %y does an elementwise signed +comparison of %x and %y.

    + + + + + + + + + + + + + + + + + +
    OperationResult is true iffComparison is
    eqvar1 == var2--
    nevar1 != var2--
    sltvar1 < var2signed
    sgtvar1 > var2signed
    slevar1 <= var2signed
    sgevar1 >= var2signed
    ultvar1 < var2unsigned
    ugtvar1 > var2unsigned
    ulevar1 <= var2unsigned
    ugevar1 >= var2unsigned
    truealways--
    falsenever--
    +
    Example:
    -
      %ptr = alloca int                               ; yields {int*}:ptr
    -  store int 3, int* %ptr                          ; yields {void}
    -  %val = load int* %ptr                           ; yields {int}:val = int 3
    +
      <result> = vsetint eq <2 x int> <int 0, int 1>, <int 1, int 0>      ; yields {<2 x bool>}:result = false, false
    +  <result> = vsetint ne <2 x int> <int 0, int 1>, <int 1, int 0>      ; yields {<2 x bool>}:result = true, true
    +  <result> = vsetint slt <2 x int> <int 0, int 1>, <int 1, int 0>      ; yields {<2 x bool>}:result = true, false
    +  <result> = vsetint sgt <2 x int> <int 0, int 1>, <int 1, int 0>      ; yields {<2 x bool>}:result = false, true
    +  <result> = vsetint sle <2 x int> <int 0, int 1>, <int 1, int 0>      ; yields {<2 x bool>}:result = true, false
    +  <result> = vsetint sge <2 x int> <int 0, int 1>, <int 1, int 0>      ; yields {<2 x bool>}:result = false, true
     
    - - + +
    Syntax:
    -
    -  <result> = getelementptr <ty>* <ptrval>{, <ty> <idx>}*
    +
    <result> = vsetfp <op>, <n x <ty>> <var1>, <var2>   ; yields <n x bool>
     
    Overview:
    -

    -The 'getelementptr' instruction is used to get the address of a -subelement of an aggregate data structure.

    +

    The 'vsetfp' instruction takes two floating point vector +arguments and returns a vector of boolean values representing, at each +position, the result of the comparison between the values at that +position in the two operands.

    Arguments:
    -

    This instruction takes a list of integer constants that indicate what -elements of the aggregate object to index to. The actual types of the arguments -provided depend on the type of the first pointer argument. The -'getelementptr' instruction is used to index down through the type -levels of a structure or to a specific index in an array. When indexing into a -structure, only uint -integer constants are allowed. When indexing into an array or pointer, -int and long indexes are allowed of any sign.

    +

    The arguments to a 'vsetfp' instruction are a comparison +operation and two value arguments. The value arguments must be of floating point packed +type, and they must have identical types. The operation argument must +be one of eq, ne, lt, gt, +le, ge, oeq, one, olt, +ogt, ole, oge, ueq, une, +ult, ugt, ule, uge, o, +u, true, and false. The result is a packed +bool value with the same length as each operand.

    -

    For example, let's consider a C code fragment and how it gets -compiled to LLVM:

    +
    Semantics:
    -
    -  struct RT {
    -    char A;
    -    int B[10][20];
    -    char C;
    -  };
    -  struct ST {
    -    int X;
    -    double Y;
    -    struct RT Z;
    -  };
    +

    The following table shows the semantics of 'vsetfp' for +floating point types. If either operand is a floating point Not a +Number (NaN) value, the operation is unordered, and the value in the +first column below is produced at that position. Otherwise, the +operation is ordered, and the value in the second column is +produced.

    - int *foo(struct ST *s) { - return &s[1].Z.B[5][13]; - } + + + + + + + + + + + + + + + + + + + + + + + + + + +
    OperationIf unorderedOtherwise true iff
    equndefinedvar1 == var2
    neundefinedvar1 != var2
    ltundefinedvar1 < var2
    gtundefinedvar1 > var2
    leundefinedvar1 <= var2
    geundefinedvar1 >= var2
    oeqfalsevar1 == var2
    onefalsevar1 != var2
    oltfalsevar1 < var2
    ogtfalsevar1 > var2
    olefalsevar1 <= var2
    ogefalsevar1 >= var2
    ueqtruevar1 == var2
    unetruevar1 != var2
    ulttruevar1 < var2
    ugttruevar1 > var2
    uletruevar1 <= var2
    ugetruevar1 >= var2
    ofalsealways
    utruenever
    truetruealways
    falsefalsenever
    + +
    Example:
    +
      <result> = vsetfp eq <2 x float> <float 0.0, float 1.0>, <float 1.0, float 0.0>      ; yields {<2 x bool>}:result = false, false
    +  <result> = vsetfp ne <2 x float> <float 0.0, float 1.0>, <float 1.0, float 0.0>      ; yields {<2 x bool>}:result = true, true
    +  <result> = vsetfp lt <2 x float> <float 0.0, float 1.0>, <float 1.0, float 0.0>      ; yields {<2 x bool>}:result = true, false
    +  <result> = vsetfp gt <2 x float> <float 0.0, float 1.0>, <float 1.0, float 0.0>      ; yields {<2 x bool>}:result = false, true
    +  <result> = vsetfp le <2 x float> <float 0.0, float 1.0>, <float 1.0, float 0.0>      ; yields {<2 x bool>}:result = true, false
    +  <result> = vsetfp ge <2 x float> <float 0.0, float 1.0>, <float 1.0, float 0.0>      ; yields {<2 x bool>}:result = false, true
     
    +
    -

    The LLVM code generated by the GCC frontend is:

    + + -
    -  %RT = type { sbyte, [10 x [20 x int]], sbyte }
    -  %ST = type { int, double, %RT }
    +
    - implementation +
    Syntax:
    - int* %foo(%ST* %s) { - entry: - %reg = getelementptr %ST* %s, int 1, uint 2, uint 1, int 5, int 13 - ret int* %reg - } +
    +  <result> = vselect <n x bool> <cond>, <n x <ty>> <val1>, <n x <ty>> <val2> ; yields <n x <ty>>
     
    -
    Semantics:
    +
    Overview:
    -

    The index types specified for the 'getelementptr' instruction depend -on the pointer type that is being indexed into. Pointer -and array types require uint, int, -ulong, or long values, and structure -types require uint constants.

    +

    +The 'vselect' instruction chooses one value at each position +of a vector based on a condition. +

    -

    In the example above, the first index is indexing into the '%ST*' -type, which is a pointer, yielding a '%ST' = '{ int, double, %RT -}' type, a structure. The second index indexes into the third element of -the structure, yielding a '%RT' = '{ sbyte, [10 x [20 x int]], -sbyte }' type, another structure. The third index indexes into the second -element of the structure, yielding a '[10 x [20 x int]]' type, an -array. The two dimensions of the array are subscripted into, yielding an -'int' type. The 'getelementptr' instruction returns a pointer -to this element, thus computing a value of 'int*' type.

    -

    Note that it is perfectly legal to index partially through a -structure, returning a pointer to an inner element. Because of this, -the LLVM code for the given testcase is equivalent to:

    +
    Arguments:
    -
    -  int* %foo(%ST* %s) {
    -    %t1 = getelementptr %ST* %s, int 1                        ; yields %ST*:%t1
    -    %t2 = getelementptr %ST* %t1, int 0, uint 2               ; yields %RT*:%t2
    -    %t3 = getelementptr %RT* %t2, int 0, uint 1               ; yields [10 x [20 x int]]*:%t3
    -    %t4 = getelementptr [10 x [20 x int]]* %t3, int 0, int 5  ; yields [20 x int]*:%t4
    -    %t5 = getelementptr [20 x int]* %t4, int 0, int 13        ; yields int*:%t5
    -    ret int* %t5
    -  }
    -
    +

    +The 'vselect' instruction requires a packed bool value indicating the +condition at each vector position, and two values of the same packed +type. All three operands must have the same length. The type of the +result is the same as the type of the two value operands.

    -

    Note that it is undefined to access an array out of bounds: array and -pointer indexes must always be within the defined bounds of the array type. -The one exception for this rules is zero length arrays. These arrays are -defined to be accessible as variable length arrays, which requires access -beyond the zero'th element.

    +
    Semantics:
    + +

    +At each position where the bool vector is true, that position +of the result gets its value from the first value argument; otherwise, +it gets its value from the second value argument. +

    Example:
    -    ; yields [12 x ubyte]*:aptr
    -    %aptr = getelementptr {int, [12 x ubyte]}* %sptr, long 0, uint 1
    +  %X = vselect bool <2 x bool> <bool true, bool false>, <2 x ubyte> <ubyte 17, ubyte 17>, 
    +    <2 x ubyte> <ubyte 42, ubyte 42>      ; yields <2 x ubyte>:17, 42
     
    -
    + + + - -
    -

    The instructions in this category are the "miscellaneous" -instructions, which defy better classification.

    + - - +
    -
    Syntax:
    -
      <result> = phi <ty> [ <val0>, <label0>], ...
    -
    Overview:
    -

    The 'phi' instruction is used to implement the φ node in -the SSA graph representing the function.

    -
    Arguments:
    -

    The type of the incoming values are specified with the first type -field. After this, the 'phi' instruction takes a list of pairs -as arguments, with one pair for each predecessor basic block of the -current block. Only values of first class -type may be used as the value arguments to the PHI node. Only labels -may be used as the label arguments.

    -

    There must be no non-phi instructions between the start of a basic -block and the PHI instructions: i.e. PHI instructions must be first in -a basic block.

    -
    Semantics:
    -

    At runtime, the 'phi' instruction logically takes on the -value specified by the parameter, depending on which basic block we -came from in the last terminator instruction.

    -
    Example:
    -
    Loop:       ; Infinite loop that counts from 0 on up...
    %indvar = phi uint [ 0, %LoopHeader ], [ %nextindvar, %Loop ]
    %nextindvar = add uint %indvar, 1
    br label %Loop
    + +

    A key design point of an SSA-based representation is how it +represents memory. In LLVM, no memory locations are in SSA form, which +makes things very simple. This section describes how to read, write, +allocate, and free memory in LLVM.

    +
    @@ -2248,58 +2272,48 @@
    Syntax:
    -  <result> = cast <ty> <value> to <ty2>             ; yields ty2
    +  <result> = malloc <type>[, uint <NumElements>][, align <alignment>]     ; yields {type*}:result
     
    Overview:
    -

    -The 'cast' instruction is used as the primitive means to convert -integers to floating point, change data type sizes, and break type safety (by -casting pointers). -

    - +

    The 'malloc' instruction allocates memory from the system +heap and returns a pointer to it.

    Arguments:
    -

    -The 'cast' instruction takes a value to cast, which must be a first -class value, and a type to cast it to, which must also be a first class type. -

    - -
    Semantics:
    +

    The 'malloc' instruction allocates +sizeof(<type>)*NumElements +bytes of memory from the operating system and returns a pointer of the +appropriate type to the program. If "NumElements" is specified, it is the +number of elements allocated. If an alignment is specified, the value result +of the allocation is guaranteed to be aligned to at least that boundary. If +not specified, or if zero, the target can choose to align the allocation on any +convenient boundary.

    -

    -This instruction follows the C rules for explicit casts when determining how the -data being cast must change to fit in its new container. -

    +

    'type' must be a sized type.

    -

    -When casting to bool, any value that would be considered true in the context of -a C 'if' condition is converted to the boolean 'true' values, -all else are 'false'. -

    +
    Semantics:
    -

    -When extending an integral value from a type of one signness to another (for -example 'sbyte' to 'ulong'), the value is sign-extended if the -source value is signed, and zero-extended if the source value is -unsigned. bool values are always zero extended into either zero or -one. -

    +

    Memory is allocated using the system "malloc" function, and +a pointer is returned.

    Example:
    -  %X = cast int 257 to ubyte              ; yields ubyte:1
    -  %Y = cast int 123 to bool               ; yields bool:true
    +  %array  = malloc [4 x ubyte ]                    ; yields {[%4 x ubyte]*}:array
    +
    +  %size   = add uint 2, 2                          ; yields {uint}:size = uint 4
    +  %array1 = malloc ubyte, uint 4                   ; yields {ubyte*}:array1
    +  %array2 = malloc [12 x ubyte], uint %size        ; yields {[12 x ubyte]*}:array2
    +  %array3 = malloc int, uint 4, align 1024         ; yields {int*}:array3
    +  %array4 = malloc int, align 1024                 ; yields {int*}:array4
     
    @@ -2307,271 +2321,280 @@
    Syntax:
    -  <result> = select bool <cond>, <ty> <val1>, <ty> <val2>             ; yields ty
    +  free <type> <value>                              ; yields {void}
     
    Overview:
    -

    -The 'select' instruction is used to choose one value based on a -condition, without branching. -

    - +

    The 'free' instruction returns memory back to the unused +memory heap to be reallocated in the future.

    Arguments:
    -

    -The 'select' instruction requires a boolean value indicating the condition, and two values of the same first class type. -

    +

    'value' shall be a pointer value that points to a value +that was allocated with the 'malloc' +instruction.

    Semantics:
    -

    -If the boolean condition evaluates to true, the instruction returns the first -value argument; otherwise, it returns the second value argument. -

    +

    Access to the memory pointed to by the pointer is no longer defined +after this instruction executes.

    Example:
    -  %X = select bool true, ubyte 17, ubyte 42          ; yields ubyte:17
    +  %array  = malloc [4 x ubyte]                    ; yields {[4 x ubyte]*}:array
    +            free   [4 x ubyte]* %array
     
    - + +
    +
    Syntax:
    -
    <result> = vsetint <op>, <n x <ty>> <var1>, <var2>   ; yields <n x bool>
    +
    +
    +  <result> = alloca <type>[, uint <NumElements>][, align <alignment>]     ; yields {type*}:result
     
    Overview:
    -

    The 'vsetint' instruction takes two integer vectors and -returns a vector of boolean values representing, at each position, the -result of the comparison between the values at that position in the -two operands.

    +

    The 'alloca' instruction allocates memory on the current +stack frame of the procedure that is live until the current function +returns to its caller.

    Arguments:
    -

    The arguments to a 'vsetint' instruction are a comparison -operation and two value arguments. The value arguments must be of integral packed type, -and they must have identical types. The operation argument must be -one of eq, ne, slt, sgt, -sle, sge, ult, ugt, ule, -uge, true, and false. The result is a -packed bool value with the same length as each operand.

    +

    The 'alloca' instruction allocates sizeof(<type>)*NumElements +bytes of memory on the runtime stack, returning a pointer of the +appropriate type to the program. If "NumElements" is specified, it is the +number of elements allocated. If an alignment is specified, the value result +of the allocation is guaranteed to be aligned to at least that boundary. If +not specified, or if zero, the target can choose to align the allocation on any +convenient boundary.

    -
    Semantics:
    +

    'type' may be any sized type.

    -

    The following table shows the semantics of 'vsetint'. For -each position of the result, the comparison is done on the -corresponding positions of the two value arguments. Note that the -signedness of the comparison depends on the comparison opcode and -not on the signedness of the value operands. E.g., vsetint -slt <4 x unsigned> %x, %y does an elementwise signed -comparison of %x and %y.

    +
    Semantics:
    - - - - - - - - - - - - - - - - -
    OperationResult is true iffComparison is
    eqvar1 == var2--
    nevar1 != var2--
    sltvar1 < var2signed
    sgtvar1 > var2signed
    slevar1 <= var2signed
    sgevar1 >= var2signed
    ultvar1 < var2unsigned
    ugtvar1 > var2unsigned
    ulevar1 <= var2unsigned
    ugevar1 >= var2unsigned
    truealways--
    falsenever--
    +

    Memory is allocated; a pointer is returned. 'alloca'd +memory is automatically released when the function returns. The 'alloca' +instruction is commonly used to represent automatic variables that must +have an address available. When the function returns (either with the ret or unwind +instructions), the memory is reclaimed.

    Example:
    -
      <result> = vsetint eq <2 x int> <int 0, int 1>, <int 1, int 0>      ; yields {<2 x bool>}:result = false, false
    -  <result> = vsetint ne <2 x int> <int 0, int 1>, <int 1, int 0>      ; yields {<2 x bool>}:result = true, true
    -  <result> = vsetint slt <2 x int> <int 0, int 1>, <int 1, int 0>      ; yields {<2 x bool>}:result = true, false
    -  <result> = vsetint sgt <2 x int> <int 0, int 1>, <int 1, int 0>      ; yields {<2 x bool>}:result = false, true
    -  <result> = vsetint sle <2 x int> <int 0, int 1>, <int 1, int 0>      ; yields {<2 x bool>}:result = true, false
    -  <result> = vsetint sge <2 x int> <int 0, int 1>, <int 1, int 0>      ; yields {<2 x bool>}:result = false, true
    +
    +
    +  %ptr = alloca int                              ; yields {int*}:ptr
    +  %ptr = alloca int, uint 4                      ; yields {int*}:ptr
    +  %ptr = alloca int, uint 4, align 1024          ; yields {int*}:ptr
    +  %ptr = alloca int, align 1024                  ; yields {int*}:ptr
     
    -
    'vsetfp' +
    Syntax:
    -
    <result> = vsetfp <op>, <n x <ty>> <var1>, <var2>   ; yields <n x bool>
    -
    - +
      <result> = load <ty>* <pointer>
    <result> = volatile load <ty>* <pointer>
    Overview:
    - -

    The 'vsetfp' instruction takes two floating point vector -arguments and returns a vector of boolean values representing, at each -position, the result of the comparison between the values at that -position in the two operands.

    - +

    The 'load' instruction is used to read from memory.

    Arguments:
    - -

    The arguments to a 'vsetfp' instruction are a comparison -operation and two value arguments. The value arguments must be of floating point packed -type, and they must have identical types. The operation argument must -be one of eq, ne, lt, gt, -le, ge, oeq, one, olt, -ogt, ole, oge, ueq, une, -ult, ugt, ule, uge, o, -u, true, and false. The result is a packed -bool value with the same length as each operand.

    - +

    The argument to the 'load' instruction specifies the memory +address from which to load. The pointer must point to a first class type. If the load is +marked as volatile, then the optimizer is not allowed to modify +the number or order of execution of this load with other +volatile load and store +instructions.

    Semantics:
    - -

    The following table shows the semantics of 'vsetfp' for -floating point types. If either operand is a floating point Not a -Number (NaN) value, the operation is unordered, and the value in the -first column below is produced at that position. Otherwise, the -operation is ordered, and the value in the second column is -produced.

    - - - - - - - - - - - - - - - - - - - - - - - - - - - -
    OperationIf unorderedOtherwise true iff
    equndefinedvar1 == var2
    neundefinedvar1 != var2
    ltundefinedvar1 < var2
    gtundefinedvar1 > var2
    leundefinedvar1 <= var2
    geundefinedvar1 >= var2
    oeqfalsevar1 == var2
    onefalsevar1 != var2
    oltfalsevar1 < var2
    ogtfalsevar1 > var2
    olefalsevar1 <= var2
    ogefalsevar1 >= var2
    ueqtruevar1 == var2
    unetruevar1 != var2
    ulttruevar1 < var2
    ugttruevar1 > var2
    uletruevar1 <= var2
    ugetruevar1 >= var2
    ofalsealways
    utruenever
    truetruealways
    falsefalsenever
    - +

    The location of memory pointed to is loaded.

    +
    Examples:
    +
      %ptr = alloca int                               ; yields {int*}:ptr
    +  store int 3, int* %ptr                          ; yields {void}
    +  %val = load int* %ptr                           ; yields {int}:val = int 3
    +
    +
    + + +
    Syntax:
    +
      store <ty> <value>, <ty>* <pointer>                   ; yields {void}
    +  volatile store <ty> <value>, <ty>* <pointer>                   ; yields {void}
    +
    +
    Overview:
    +

    The 'store' instruction is used to write to memory.

    +
    Arguments:
    +

    There are two arguments to the 'store' instruction: a value +to store and an address in which to store it. The type of the '<pointer>' +operand must be a pointer to the type of the '<value>' +operand. If the store is marked as volatile, then the +optimizer is not allowed to modify the number or order of execution of +this store with other volatile load and store instructions.

    +
    Semantics:
    +

    The contents of memory are updated to contain '<value>' +at the location specified by the '<pointer>' operand.

    Example:
    -
      <result> = vsetfp eq <2 x float> <float 0.0, float 1.0>, <float 1.0, float 0.0>      ; yields {<2 x bool>}:result = false, false
    -  <result> = vsetfp ne <2 x float> <float 0.0, float 1.0>, <float 1.0, float 0.0>      ; yields {<2 x bool>}:result = true, true
    -  <result> = vsetfp lt <2 x float> <float 0.0, float 1.0>, <float 1.0, float 0.0>      ; yields {<2 x bool>}:result = true, false
    -  <result> = vsetfp gt <2 x float> <float 0.0, float 1.0>, <float 1.0, float 0.0>      ; yields {<2 x bool>}:result = false, true
    -  <result> = vsetfp le <2 x float> <float 0.0, float 1.0>, <float 1.0, float 0.0>      ; yields {<2 x bool>}:result = true, false
    -  <result> = vsetfp ge <2 x float> <float 0.0, float 1.0>, <float 1.0, float 0.0>      ; yields {<2 x bool>}:result = false, true
    +
      %ptr = alloca int                               ; yields {int*}:ptr
    +  store int 3, int* %ptr                          ; yields {void}
    +  %val = load int* %ptr                           ; yields {int}:val = int 3
     
    -
    -
    -
    Syntax:
    -
    -  <result> = vselect <n x bool> <cond>, <n x <ty>> <val1>, <n x <ty>> <val2> ; yields <n x <ty>>
    +  <result> = getelementptr <ty>* <ptrval>{, <ty> <idx>}*
     
    Overview:

    -The 'vselect' instruction chooses one value at each position -of a vector based on a condition. -

    - +The 'getelementptr' instruction is used to get the address of a +subelement of an aggregate data structure.

    Arguments:
    -

    -The 'vselect' instruction requires a packed bool value indicating the -condition at each vector position, and two values of the same packed -type. All three operands must have the same length. The type of the -result is the same as the type of the two value operands.

    - -
    Semantics:
    - -

    -At each position where the bool vector is true, that position -of the result gets its value from the first value argument; otherwise, -it gets its value from the second value argument. -

    +

    This instruction takes a list of integer constants that indicate what +elements of the aggregate object to index to. The actual types of the arguments +provided depend on the type of the first pointer argument. The +'getelementptr' instruction is used to index down through the type +levels of a structure or to a specific index in an array. When indexing into a +structure, only uint +integer constants are allowed. When indexing into an array or pointer, +int and long indexes are allowed of any sign.

    -
    Example:
    +

    For example, let's consider a C code fragment and how it gets +compiled to LLVM:

    -  %X = vselect bool <2 x bool> <bool true, bool false>, <2 x ubyte> <ubyte 17, ubyte 17>, 
    -    <2 x ubyte> <ubyte 42, ubyte 42>      ; yields <2 x ubyte>:17, 42
    +  struct RT {
    +    char A;
    +    int B[10][20];
    +    char C;
    +  };
    +  struct ST {
    +    int X;
    +    double Y;
    +    struct RT Z;
    +  };
    +
    +  int *foo(struct ST *s) {
    +    return &s[1].Z.B[5][13];
    +  }
     
    -
    - - +

    The LLVM code generated by the GCC frontend is:

    -
    +
    +  %RT = type { sbyte, [10 x [20 x int]], sbyte }
    +  %ST = type { int, double, %RT }
     
    -
    Syntax:
    + implementation -
    -  <result> = extractelement <n x <ty>> <val>, uint <idx>    ; yields <ty>
    +  int* %foo(%ST* %s) {
    +  entry:
    +    %reg = getelementptr %ST* %s, int 1, uint 2, uint 1, int 5, int 13
    +    ret int* %reg
    +  }
     
    -
    Overview:
    - -

    -The 'extractelement' instruction extracts a single scalar -element from a packed vector at a specified index. -

    +
    Semantics:
    +

    The index types specified for the 'getelementptr' instruction depend +on the pointer type that is being indexed into. Pointer +and array types require uint, int, +ulong, or long values, and structure +types require uint constants.

    -
    Arguments:
    +

    In the example above, the first index is indexing into the '%ST*' +type, which is a pointer, yielding a '%ST' = '{ int, double, %RT +}' type, a structure. The second index indexes into the third element of +the structure, yielding a '%RT' = '{ sbyte, [10 x [20 x int]], +sbyte }' type, another structure. The third index indexes into the second +element of the structure, yielding a '[10 x [20 x int]]' type, an +array. The two dimensions of the array are subscripted into, yielding an +'int' type. The 'getelementptr' instruction returns a pointer +to this element, thus computing a value of 'int*' type.

    -

    -The first operand of an 'extractelement' instruction is a -value of packed type. The second operand is -an index indicating the position from which to extract the element. -The index may be a variable.

    +

    Note that it is perfectly legal to index partially through a +structure, returning a pointer to an inner element. Because of this, +the LLVM code for the given testcase is equivalent to:

    -
    Semantics:
    +
    +  int* %foo(%ST* %s) {
    +    %t1 = getelementptr %ST* %s, int 1                        ; yields %ST*:%t1
    +    %t2 = getelementptr %ST* %t1, int 0, uint 2               ; yields %RT*:%t2
    +    %t3 = getelementptr %RT* %t2, int 0, uint 1               ; yields [10 x [20 x int]]*:%t3
    +    %t4 = getelementptr [10 x [20 x int]]* %t3, int 0, int 5  ; yields [20 x int]*:%t4
    +    %t5 = getelementptr [20 x int]* %t4, int 0, int 13        ; yields int*:%t5
    +    ret int* %t5
    +  }
    +
    -

    -The result is a scalar of the same type as the element type of -val. Its value is the value at position idx of -val. If idx exceeds the length of val, the -results are undefined. -

    +

    Note that it is undefined to access an array out of bounds: array and +pointer indexes must always be within the defined bounds of the array type. +The one exception for this rules is zero length arrays. These arrays are +defined to be accessible as variable length arrays, which requires access +beyond the zero'th element.

    Example:
    -  %result = extractelement <4 x int> %vec, uint 0    ; yields int
    +    ; yields [12 x ubyte]*:aptr
    +    %aptr = getelementptr {int, [12 x ubyte]}* %sptr, long 0, uint 1
     
    -
    +
    + + +
    +

    The instructions in this category are the "miscellaneous" +instructions, which defy better classification.

    +
    + + +
    +
    Syntax:
    +
      <result> = phi <ty> [ <val0>, <label0>], ...
    +
    Overview:
    +

    The 'phi' instruction is used to implement the φ node in +the SSA graph representing the function.

    +
    Arguments:
    +

    The type of the incoming values are specified with the first type +field. After this, the 'phi' instruction takes a list of pairs +as arguments, with one pair for each predecessor basic block of the +current block. Only values of first class +type may be used as the value arguments to the PHI node. Only labels +may be used as the label arguments.

    +

    There must be no non-phi instructions between the start of a basic +block and the PHI instructions: i.e. PHI instructions must be first in +a basic block.

    +
    Semantics:
    +

    At runtime, the 'phi' instruction logically takes on the +value specified by the parameter, depending on which basic block we +came from in the last terminator instruction.

    +
    Example:
    +
    Loop:       ; Infinite loop that counts from 0 on up...
    %indvar = phi uint [ 0, %LoopHeader ], [ %nextindvar, %Loop ]
    %nextindvar = add uint %indvar, 1
    br label %Loop
    +
    @@ -2579,45 +2602,58 @@
    Syntax:
    -  <result> = insertelement <n x <ty>> <val>, <ty> <elt>, uint <idx>    ; yields <n x <ty>>
    +  <result> = cast <ty> <value> to <ty2>             ; yields ty2
     
    Overview:

    -The 'insertelement' instruction inserts a scalar -element into a packed vector at a specified index. +The 'cast' instruction is used as the primitive means to convert +integers to floating point, change data type sizes, and break type safety (by +casting pointers).

    Arguments:

    -The first operand of an 'insertelement' instruction is a -value of packed type. The second operand is a -scalar value whose type must equal the element type of the first -operand. The third operand is an index indicating the position at -which to insert the value. The index may be a variable.

    +The 'cast' instruction takes a value to cast, which must be a first +class value, and a type to cast it to, which must also be a first class type. +

    Semantics:

    -The result is a packed vector of the same type as val. Its -element values are those of val except at position -idx, where it gets the value elt. If idx -exceeds the length of val, the results are undefined. +This instruction follows the C rules for explicit casts when determining how the +data being cast must change to fit in its new container. +

    + +

    +When casting to bool, any value that would be considered true in the context of +a C 'if' condition is converted to the boolean 'true' values, +all else are 'false'. +

    + +

    +When extending an integral value from a type of one signness to another (for +example 'sbyte' to 'ulong'), the value is sign-extended if the +source value is signed, and zero-extended if the source value is +unsigned. bool values are always zero extended into either zero or +one.

    Example:
    -  %result = insertelement <4 x int> %vec, int 1, uint 0    ; yields <4 x int>
    +  %X = cast int 257 to ubyte              ; yields ubyte:1
    +  %Y = cast int 123 to bool               ; yields bool:true
     
    @@ -2625,47 +2661,34 @@
    Syntax:
    -  <result> = shufflevector <n x <ty>> <v1>, <n x <ty>> <v2>, <n x uint> <mask>    ; yields <n x <ty>>
    +  <result> = select bool <cond>, <ty> <val1>, <ty> <val2>             ; yields ty
     
    Overview:

    -The 'shufflevector' instruction constructs a permutation of elements -from two input vectors, returning a vector of the same type. +The 'select' instruction is used to choose one value based on a +condition, without branching.

    -
    Arguments:
    -

    -The first two operands of a 'shufflevector' instruction are vectors -with types that match each other and types that match the result of the -instruction. The third argument is a shuffle mask, which has the same number -of elements as the other vector type, but whose element type is always 'uint'. -

    +
    Arguments:

    -The shuffle mask operand is required to be a constant vector with either -constant integer or undef values. +The 'select' instruction requires a boolean value indicating the condition, and two values of the same first class type.

    Semantics:

    -The elements of the two input vectors are numbered from left to right across -both of the vectors. The shuffle mask operand specifies, for each element of -the result vector, which element of the two input registers the result element -gets. The element selector may be undef (meaning "don't care") and the second -operand may be undef if performing a shuffle from only one vector. +If the boolean condition evaluates to true, the instruction returns the first +value argument; otherwise, it returns the second value argument.

    Example:
    -  %result = shufflevector <4 x int> %v1, <4 x int> %v2, 
    -                          <4 x uint> <uint 0, uint 4, uint 1, uint 5>    ; yields <4 x int>
    -  %result = shufflevector <4 x int> %v1, <4 x int> undef, 
    -                          <4 x uint> <uint 0, uint 1, uint 2, uint 3>  ; yields <4 x int> - Identity shuffle.
    +  %X = select bool true, ubyte 17, ubyte 42          ; yields ubyte:17
     
    @@ -3794,7 +3817,7 @@ Chris Lattner
    The LLVM Compiler Infrastructure
    - Last modified: $Date: 2006/04/08 04:40:53 $ + Last modified: $Date: 2006/04/08 23:07:04 $ From reid at x10sys.com Sun Apr 9 02:18:13 2006 From: reid at x10sys.com (Reid Spencer) Date: Sun, 9 Apr 2006 02:18:13 -0500 Subject: [llvm-commits] CVS: llvm-test/Makefile.rules Message-ID: <200604090718.CAA10296@zion.cs.uiuc.edu> Changes in directory llvm-test: Makefile.rules updated: 1.9 -> 1.10 --- Log message: Make sure the CONFIGURATION variable is set correctly in light of changes in LLVM's Makefile.rules. Basically when Assertion checking is on, it needs to be set to Release+Asserts, or when off to Debug-Asserts, as is the case for LLVM. --- Diffs of the changes: (+13 -0) Makefile.rules | 13 +++++++++++++ 1 files changed, 13 insertions(+) Index: llvm-test/Makefile.rules diff -u llvm-test/Makefile.rules:1.9 llvm-test/Makefile.rules:1.10 --- llvm-test/Makefile.rules:1.9 Tue Feb 28 12:22:24 2006 +++ llvm-test/Makefile.rules Sun Apr 9 02:18:00 2006 @@ -104,6 +104,7 @@ @${ECHO} "Build Object Dir : " $(PROJ_OBJ_DIR) @${ECHO} "LLVM Source Root: " $(LLVM_SRC_ROOT) @${ECHO} "LLVM Object Root: " $(LLVM_OBJ_ROOT) + @${ECHO} "CONFIGURATION : " $(CONFIGURATION) ########################################################################### # Suffixes and implicit rules: @@ -147,6 +148,18 @@ endif endif +# If ENABLE_ASSERTIONS=1 is specified (make command line or configured), +# then adjust the CONFIGURATION name appropriately (to match LLVM makefiles) +ifdef ENABLE_ASSERTIONS + ifdef ENABLE_OPTIMIZED + CONFIGURATION := $(CONFIGURATION)+Asserts + endif +else + ifndef ENABLE_OPTIMIZED + CONFIGURATION := $(CONFIGURATION)-Asserts + endif +endif + # # Enable this for profiling support with 'gprof' # This automatically enables optimized builds. From lattner at cs.uiuc.edu Sun Apr 9 02:18:35 2006 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Sun, 9 Apr 2006 02:18:35 -0500 Subject: [llvm-commits] CVS: llvm-test/SingleSource/UnitTests/Makefile Message-ID: <200604090718.CAA10398@zion.cs.uiuc.edu> Changes in directory llvm-test/SingleSource/UnitTests: Makefile updated: 1.6 -> 1.7 --- Log message: Don't run vector tests if we just have llvmgcc3 --- Diffs of the changes: (+9 -2) Makefile | 11 +++++++++-- 1 files changed, 9 insertions(+), 2 deletions(-) Index: llvm-test/SingleSource/UnitTests/Makefile diff -u llvm-test/SingleSource/UnitTests/Makefile:1.6 llvm-test/SingleSource/UnitTests/Makefile:1.7 --- llvm-test/SingleSource/UnitTests/Makefile:1.6 Wed Mar 22 00:14:10 2006 +++ llvm-test/SingleSource/UnitTests/Makefile Sun Apr 9 02:18:21 2006 @@ -1,6 +1,13 @@ # SingleSource/UnitTests/Makefile - -DIRS = Vector SetjmpLongjmp LEVEL = ../.. +include $(LEVEL)/Makefile.config + +DIRS := SetjmpLongjmp + +# llvm-gcc3 does not support any vector tests. +ifneq ($(LLVMGCC_MAJVERS),3) +DIRS += Vector +endif + include $(LEVEL)/SingleSource/Makefile.singlesrc From reid at x10sys.com Sun Apr 9 15:42:28 2006 From: reid at x10sys.com (Reid Spencer) Date: Sun, 9 Apr 2006 15:42:28 -0500 Subject: [llvm-commits] CVS: llvm/autoconf/configure.ac Message-ID: <200604092042.PAA07708@zion.cs.uiuc.edu> Changes in directory llvm/autoconf: configure.ac updated: 1.216 -> 1.217 --- Log message: Change the assertions defaults: 1. Assertions now default to on for all builds 2. If you want them disabled you must (a) --disable-assertions to configure or DISABLE_ASSERTIONS=1 to make. --- Diffs of the changes: (+4 -6) configure.ac | 10 ++++------ 1 files changed, 4 insertions(+), 6 deletions(-) Index: llvm/autoconf/configure.ac diff -u llvm/autoconf/configure.ac:1.216 llvm/autoconf/configure.ac:1.217 --- llvm/autoconf/configure.ac:1.216 Fri Apr 7 20:41:26 2006 +++ llvm/autoconf/configure.ac Sun Apr 9 15:42:14 2006 @@ -193,12 +193,10 @@ if test -d "CVS" -o -d "${srcdir}/CVS"; then cvsbuild="yes" optimize="no" - asserts="yes" AC_SUBST(CVSBUILD,[[CVSBUILD=1]]) else cvsbuild="no" optimize="yes" - asserts="no" fi dnl===-----------------------------------------------------------------------=== @@ -218,11 +216,11 @@ dnl --enable-assertions : check whether they want to turn on assertions or not: AC_ARG_ENABLE(assertions,AS_HELP_STRING( - [--enable-assertions,Compile with assertion checks enabled (default is NO)]),, enableval=$asserts) -if test ${enableval} = "no" ; then - AC_SUBST(ENABLE_ASSERTIONS,[[]]) + [--enable-assertions,Compile with assertion checks enabled (default is YES)]),, enableval="yes") +if test ${enableval} = "yes" ; then + AC_SUBST(DISABLE_ASSERTIONS,[[]]) else - AC_SUBST(ENABLE_ASSERTIONS,[[ENABLE_ASSERTIONS=1]]) + AC_SUBST(DISABLE_ASSERTIONS,[[DISABLE_ASSERTIONS=1]]) fi dnl --enable-debug-runtime : should runtime libraries have debug symbols? From reid at x10sys.com Sun Apr 9 15:42:28 2006 From: reid at x10sys.com (Reid Spencer) Date: Sun, 9 Apr 2006 15:42:28 -0500 Subject: [llvm-commits] CVS: llvm/configure Makefile.config.in Message-ID: <200604092042.PAA07704@zion.cs.uiuc.edu> Changes in directory llvm: configure updated: 1.218 -> 1.219 Makefile.config.in updated: 1.55 -> 1.56 --- Log message: Change the assertions defaults: 1. Assertions now default to on for all builds 2. If you want them disabled you must (a) --disable-assertions to configure or DISABLE_ASSERTIONS=1 to make. --- Diffs of the changes: (+37 -39) Makefile.config.in | 4 +- configure | 72 +++++++++++++++++++++++++---------------------------- 2 files changed, 37 insertions(+), 39 deletions(-) Index: llvm/configure diff -u llvm/configure:1.218 llvm/configure:1.219 --- llvm/configure:1.218 Fri Apr 7 20:41:26 2006 +++ llvm/configure Sun Apr 9 15:42:14 2006 @@ -476,7 +476,7 @@ # include #endif" -ac_subst_vars='SHELL PATH_SEPARATOR PACKAGE_NAME PACKAGE_TARNAME PACKAGE_VERSION PACKAGE_STRING PACKAGE_BUGREPORT exec_prefix prefix program_transform_name bindir sbindir libexecdir datadir sysconfdir sharedstatedir localstatedir libdir includedir oldincludedir infodir mandir build_alias host_alias target_alias DEFS ECHO_C ECHO_N ECHO_T LIBS LLVM_COPYRIGHT subdirs build build_cpu build_vendor build_os host host_cpu host_vendor host_os target target_cpu target_vendor target_os OS LLVM_ON_UNIX LLVM_ON_WIN32 ARCH ENDIAN CC CFLAGS LDFLAGS CPPFLAGS ac_ct_CC EXEEXT OBJEXT CVSBUILD ENABLE_OPTIMIZED ENABLE_ASSERTIONS DEBUG_RUNTIME JIT TARGET_HAS_JIT ENABLE_DOXYGEN ENABLE_THREADS TARGETS_TO_BUILD CPP CXX CXXFLAGS ac_ct_CXX LEX LEXLIB LEX_OUTPUT_ROOT FLEX YACC BISON ifGNUmake LN_S CMP CP DATE FIND GREP MKDIR MV RANLIB ac_ct_RANLIB RM SED TAR GRAPHVIZ GV PERL HAVE_PERL INSTALL_PROGRAM INSTALL_SCRIPT INSTALL_DATA BZIP2 DOT DOXYGEN ETAGS GROFF GZIP POD2HTML POD2MAN RUNTEST TCLSH ZIP EGR! EP INSTALL_LTDL_TRUE INSTALL_LTDL_FALSE CONVENIENCE_LTDL_TRUE CONVENIENCE_LTDL_FALSE LIBADD_DL ECHO AR ac_ct_AR STRIP ac_ct_STRIP CXXCPP F77 FFLAGS ac_ct_F77 LIBTOOL ETAGSFLAGS LLVMGCC LLVMGXX ALLOCA MMAP_FILE LLVMCC1 LLVMCC1PLUS LLVMGCCDIR LLVMGCC_VERSION LLVMGCC_MAJVERS SHLIBEXT LLVM_PREFIX LLVM_BINDIR LLVM_LIBDIR LLVM_DATADIR LLVM_DOCSDIR LLVM_ETCDIR LLVM_INCLUDEDIR LLVM_INFODIR LLVM_MANDIR LLVM_CONFIGTIME LIBOBJS LTLIBOBJS' +ac_subst_vars='SHELL PATH_SEPARATOR PACKAGE_NAME PACKAGE_TARNAME PACKAGE_VERSION PACKAGE_STRING PACKAGE_BUGREPORT exec_prefix prefix program_transform_name bindir sbindir libexecdir datadir sysconfdir sharedstatedir localstatedir libdir includedir oldincludedir infodir mandir build_alias host_alias target_alias DEFS ECHO_C ECHO_N ECHO_T LIBS LLVM_COPYRIGHT subdirs build build_cpu build_vendor build_os host host_cpu host_vendor host_os target target_cpu target_vendor target_os OS LLVM_ON_UNIX LLVM_ON_WIN32 ARCH ENDIAN CC CFLAGS LDFLAGS CPPFLAGS ac_ct_CC EXEEXT OBJEXT CVSBUILD ENABLE_OPTIMIZED DISABLE_ASSERTIONS DEBUG_RUNTIME JIT TARGET_HAS_JIT ENABLE_DOXYGEN ENABLE_THREADS TARGETS_TO_BUILD CPP CXX CXXFLAGS ac_ct_CXX LEX LEXLIB LEX_OUTPUT_ROOT FLEX YACC BISON ifGNUmake LN_S CMP CP DATE FIND GREP MKDIR MV RANLIB ac_ct_RANLIB RM SED TAR GRAPHVIZ GV PERL HAVE_PERL INSTALL_PROGRAM INSTALL_SCRIPT INSTALL_DATA BZIP2 DOT DOXYGEN ETAGS GROFF GZIP POD2HTML POD2MAN RUNTEST TCLSH ZIP EG! REP INSTALL_LTDL_TRUE INSTALL_LTDL_FALSE CONVENIENCE_LTDL_TRUE CONVENIENCE_LTDL_FALSE LIBADD_DL ECHO AR ac_ct_AR STRIP ac_ct_STRIP CXXCPP F77 FFLAGS ac_ct_F77 LIBTOOL ETAGSFLAGS LLVMGCC LLVMGXX ALLOCA MMAP_FILE LLVMCC1 LLVMCC1PLUS LLVMGCCDIR LLVMGCC_VERSION LLVMGCC_MAJVERS SHLIBEXT LLVM_PREFIX LLVM_BINDIR LLVM_LIBDIR LLVM_DATADIR LLVM_DOCSDIR LLVM_ETCDIR LLVM_INCLUDEDIR LLVM_INFODIR LLVM_MANDIR LLVM_CONFIGTIME LIBOBJS LTLIBOBJS' ac_subst_files='' # Initialize some variables set by options. @@ -2971,13 +2971,11 @@ if test -d "CVS" -o -d "${srcdir}/CVS"; then cvsbuild="yes" optimize="no" - asserts="yes" CVSBUILD=CVSBUILD=1 else cvsbuild="no" optimize="yes" - asserts="no" fi @@ -3001,13 +2999,13 @@ enableval="$enable_assertions" else - enableval=$asserts + enableval="yes" fi; -if test ${enableval} = "no" ; then - ENABLE_ASSERTIONS= +if test ${enableval} = "yes" ; then + DISABLE_ASSERTIONS= else - ENABLE_ASSERTIONS=ENABLE_ASSERTIONS=1 + DISABLE_ASSERTIONS=DISABLE_ASSERTIONS=1 fi @@ -8467,7 +8465,7 @@ lt_dlunknown=0; lt_dlno_uscore=1; lt_dlneed_uscore=2 lt_status=$lt_dlunknown cat > conftest.$ac_ext < conftest.$ac_ext + echo '#line 10459 "configure"' > conftest.$ac_ext if { (eval echo "$as_me:$LINENO: \"$ac_compile\"") >&5 (eval $ac_compile) 2>&5 ac_status=$? @@ -10943,7 +10941,7 @@ # Provide some information about the compiler. -echo "$as_me:10946:" \ +echo "$as_me:10944:" \ "checking for Fortran 77 compiler version" >&5 ac_compiler=`set X $ac_compile; echo $2` { (eval echo "$as_me:$LINENO: \"$ac_compiler --version &5\"") >&5 @@ -12000,11 +11998,11 @@ -e 's:.*FLAGS}? :&$lt_compiler_flag :; t' \ -e 's: [^ ]*conftest\.: $lt_compiler_flag&:; t' \ -e 's:$: $lt_compiler_flag:'` - (eval echo "\"\$as_me:12003: $lt_compile\"" >&5) + (eval echo "\"\$as_me:12001: $lt_compile\"" >&5) (eval "$lt_compile" 2>conftest.err) ac_status=$? cat conftest.err >&5 - echo "$as_me:12007: \$? = $ac_status" >&5 + echo "$as_me:12005: \$? = $ac_status" >&5 if (exit $ac_status) && test -s "$ac_outfile"; then # The compiler can only warn and ignore the option if not recognized # So say no if there are warnings @@ -12243,11 +12241,11 @@ -e 's:.*FLAGS}? :&$lt_compiler_flag :; t' \ -e 's: [^ ]*conftest\.: $lt_compiler_flag&:; t' \ -e 's:$: $lt_compiler_flag:'` - (eval echo "\"\$as_me:12246: $lt_compile\"" >&5) + (eval echo "\"\$as_me:12244: $lt_compile\"" >&5) (eval "$lt_compile" 2>conftest.err) ac_status=$? cat conftest.err >&5 - echo "$as_me:12250: \$? = $ac_status" >&5 + echo "$as_me:12248: \$? = $ac_status" >&5 if (exit $ac_status) && test -s "$ac_outfile"; then # The compiler can only warn and ignore the option if not recognized # So say no if there are warnings @@ -12303,11 +12301,11 @@ -e 's:.*FLAGS}? :&$lt_compiler_flag :; t' \ -e 's: [^ ]*conftest\.: $lt_compiler_flag&:; t' \ -e 's:$: $lt_compiler_flag:'` - (eval echo "\"\$as_me:12306: $lt_compile\"" >&5) + (eval echo "\"\$as_me:12304: $lt_compile\"" >&5) (eval "$lt_compile" 2>out/conftest.err) ac_status=$? cat out/conftest.err >&5 - echo "$as_me:12310: \$? = $ac_status" >&5 + echo "$as_me:12308: \$? = $ac_status" >&5 if (exit $ac_status) && test -s out/conftest2.$ac_objext then # The compiler can only warn and ignore the option if not recognized @@ -14488,7 +14486,7 @@ lt_dlunknown=0; lt_dlno_uscore=1; lt_dlneed_uscore=2 lt_status=$lt_dlunknown cat > conftest.$ac_ext < conftest.$ac_ext <&5) + (eval echo "\"\$as_me:16780: $lt_compile\"" >&5) (eval "$lt_compile" 2>conftest.err) ac_status=$? cat conftest.err >&5 - echo "$as_me:16786: \$? = $ac_status" >&5 + echo "$as_me:16784: \$? = $ac_status" >&5 if (exit $ac_status) && test -s "$ac_outfile"; then # The compiler can only warn and ignore the option if not recognized # So say no if there are warnings @@ -16839,11 +16837,11 @@ -e 's:.*FLAGS}? :&$lt_compiler_flag :; t' \ -e 's: [^ ]*conftest\.: $lt_compiler_flag&:; t' \ -e 's:$: $lt_compiler_flag:'` - (eval echo "\"\$as_me:16842: $lt_compile\"" >&5) + (eval echo "\"\$as_me:16840: $lt_compile\"" >&5) (eval "$lt_compile" 2>out/conftest.err) ac_status=$? cat out/conftest.err >&5 - echo "$as_me:16846: \$? = $ac_status" >&5 + echo "$as_me:16844: \$? = $ac_status" >&5 if (exit $ac_status) && test -s out/conftest2.$ac_objext then # The compiler can only warn and ignore the option if not recognized @@ -18200,7 +18198,7 @@ lt_dlunknown=0; lt_dlno_uscore=1; lt_dlneed_uscore=2 lt_status=$lt_dlunknown cat > conftest.$ac_ext < conftest.$ac_ext <&5) + (eval echo "\"\$as_me:19136: $lt_compile\"" >&5) (eval "$lt_compile" 2>conftest.err) ac_status=$? cat conftest.err >&5 - echo "$as_me:19142: \$? = $ac_status" >&5 + echo "$as_me:19140: \$? = $ac_status" >&5 if (exit $ac_status) && test -s "$ac_outfile"; then # The compiler can only warn and ignore the option if not recognized # So say no if there are warnings @@ -19195,11 +19193,11 @@ -e 's:.*FLAGS}? :&$lt_compiler_flag :; t' \ -e 's: [^ ]*conftest\.: $lt_compiler_flag&:; t' \ -e 's:$: $lt_compiler_flag:'` - (eval echo "\"\$as_me:19198: $lt_compile\"" >&5) + (eval echo "\"\$as_me:19196: $lt_compile\"" >&5) (eval "$lt_compile" 2>out/conftest.err) ac_status=$? cat out/conftest.err >&5 - echo "$as_me:19202: \$? = $ac_status" >&5 + echo "$as_me:19200: \$? = $ac_status" >&5 if (exit $ac_status) && test -s out/conftest2.$ac_objext then # The compiler can only warn and ignore the option if not recognized @@ -21234,11 +21232,11 @@ -e 's:.*FLAGS}? :&$lt_compiler_flag :; t' \ -e 's: [^ ]*conftest\.: $lt_compiler_flag&:; t' \ -e 's:$: $lt_compiler_flag:'` - (eval echo "\"\$as_me:21237: $lt_compile\"" >&5) + (eval echo "\"\$as_me:21235: $lt_compile\"" >&5) (eval "$lt_compile" 2>conftest.err) ac_status=$? cat conftest.err >&5 - echo "$as_me:21241: \$? = $ac_status" >&5 + echo "$as_me:21239: \$? = $ac_status" >&5 if (exit $ac_status) && test -s "$ac_outfile"; then # The compiler can only warn and ignore the option if not recognized # So say no if there are warnings @@ -21477,11 +21475,11 @@ -e 's:.*FLAGS}? :&$lt_compiler_flag :; t' \ -e 's: [^ ]*conftest\.: $lt_compiler_flag&:; t' \ -e 's:$: $lt_compiler_flag:'` - (eval echo "\"\$as_me:21480: $lt_compile\"" >&5) + (eval echo "\"\$as_me:21478: $lt_compile\"" >&5) (eval "$lt_compile" 2>conftest.err) ac_status=$? cat conftest.err >&5 - echo "$as_me:21484: \$? = $ac_status" >&5 + echo "$as_me:21482: \$? = $ac_status" >&5 if (exit $ac_status) && test -s "$ac_outfile"; then # The compiler can only warn and ignore the option if not recognized # So say no if there are warnings @@ -21537,11 +21535,11 @@ -e 's:.*FLAGS}? :&$lt_compiler_flag :; t' \ -e 's: [^ ]*conftest\.: $lt_compiler_flag&:; t' \ -e 's:$: $lt_compiler_flag:'` - (eval echo "\"\$as_me:21540: $lt_compile\"" >&5) + (eval echo "\"\$as_me:21538: $lt_compile\"" >&5) (eval "$lt_compile" 2>out/conftest.err) ac_status=$? cat out/conftest.err >&5 - echo "$as_me:21544: \$? = $ac_status" >&5 + echo "$as_me:21542: \$? = $ac_status" >&5 if (exit $ac_status) && test -s out/conftest2.$ac_objext then # The compiler can only warn and ignore the option if not recognized @@ -23722,7 +23720,7 @@ lt_dlunknown=0; lt_dlno_uscore=1; lt_dlneed_uscore=2 lt_status=$lt_dlunknown cat > conftest.$ac_ext < conftest.$ac_ext < Changes in directory llvm-test: Makefile.rules updated: 1.10 -> 1.11 --- Log message: Adjust to reversed logic in LLVM's Makefile.rules. We now use the make variable DISABLE_ASSERTIONS instead of ENABLE_ASSERTIONS. --- Diffs of the changes: (+1 -7) Makefile.rules | 8 +------- 1 files changed, 1 insertion(+), 7 deletions(-) Index: llvm-test/Makefile.rules diff -u llvm-test/Makefile.rules:1.10 llvm-test/Makefile.rules:1.11 --- llvm-test/Makefile.rules:1.10 Sun Apr 9 02:18:00 2006 +++ llvm-test/Makefile.rules Sun Apr 9 15:43:17 2006 @@ -150,14 +150,8 @@ # If ENABLE_ASSERTIONS=1 is specified (make command line or configured), # then adjust the CONFIGURATION name appropriately (to match LLVM makefiles) -ifdef ENABLE_ASSERTIONS - ifdef ENABLE_OPTIMIZED - CONFIGURATION := $(CONFIGURATION)+Asserts - endif -else - ifndef ENABLE_OPTIMIZED +ifdef DISABLE_ASSERTIONS CONFIGURATION := $(CONFIGURATION)-Asserts - endif endif # From reid at x10sys.com Sun Apr 9 18:39:56 2006 From: reid at x10sys.com (Reid Spencer) Date: Sun, 9 Apr 2006 18:39:56 -0500 Subject: [llvm-commits] CVS: llvm/Makefile.config.in Message-ID: <200604092339.SAA08372@zion.cs.uiuc.edu> Changes in directory llvm: Makefile.config.in updated: 1.56 -> 1.57 --- Log message: Fix a comment. --- Diffs of the changes: (+2 -2) Makefile.config.in | 4 ++-- 1 files changed, 2 insertions(+), 2 deletions(-) Index: llvm/Makefile.config.in diff -u llvm/Makefile.config.in:1.56 llvm/Makefile.config.in:1.57 --- llvm/Makefile.config.in:1.56 Sun Apr 9 15:42:14 2006 +++ llvm/Makefile.config.in Sun Apr 9 18:39:43 2006 @@ -184,8 +184,8 @@ #ENABLE_OPTIMIZED = 1 @ENABLE_OPTIMIZED@ -# When ENABLE_ASSERTIONS is enabled, builds of all of the LLVM code will include -# assertion checks, otherwise they are not included. +# When DISABLE_ASSERTIONS is enabled, builds of all of the LLVM code will +# exclude assertion checks, otherwise they are included. #DISABLE_ASSERTIONS = 1 @DISABLE_ASSERTIONS@ From reid at x10sys.com Sun Apr 9 18:41:26 2006 From: reid at x10sys.com (Reid Spencer) Date: Sun, 9 Apr 2006 18:41:26 -0500 Subject: [llvm-commits] CVS: llvm/Makefile.rules Message-ID: <200604092341.SAA08394@zion.cs.uiuc.edu> Changes in directory llvm: Makefile.rules updated: 1.358 -> 1.359 --- Log message: Check for DISABLE_ASSERTIONS, not ENABLE_ASSERTIONS --- Diffs of the changes: (+5 -9) Makefile.rules | 14 +++++--------- 1 files changed, 5 insertions(+), 9 deletions(-) Index: llvm/Makefile.rules diff -u llvm/Makefile.rules:1.358 llvm/Makefile.rules:1.359 --- llvm/Makefile.rules:1.358 Fri Apr 7 11:06:18 2006 +++ llvm/Makefile.rules Sun Apr 9 18:41:14 2006 @@ -224,18 +224,13 @@ # If ENABLE_ASSERTIONS=1 is specified (make command line or configured), # then enable assertions by defining the appropriate preprocessor symbols. -ifdef ENABLE_ASSERTIONS - ifdef ENABLE_OPTIMIZED - BuildMode := $(BuildMode)+Asserts - endif - CXX.Flags += -D_DEBUG - C.Flags += -D_DEBUG -else - ifndef ENABLE_OPTIMIZED +ifdef DISABLE_ASSERTIONS BuildMode := $(BuildMode)-Asserts - endif CXX.Flags += -DNDEBUG C.Flags += -DNDEBUG +else + CXX.Flags += -D_DEBUG + C.Flags += -D_DEBUG endif CXX.Flags += $(CXXFLAGS) @@ -1699,3 +1694,4 @@ $(Echo) "LexFiles : " '$(LexFiles)' $(Echo) "Module : " '$(Module)' $(Echo) "FilesToConfig: " '$(FilesToConfigPATH)' + $(Echo) "SubDirs : " '$(SubDirs)' From reid at x10sys.com Sun Apr 9 18:45:50 2006 From: reid at x10sys.com (Reid Spencer) Date: Sun, 9 Apr 2006 18:45:50 -0500 Subject: [llvm-commits] CVS: llvm/docs/GettingStarted.html MakefileGuide.html Message-ID: <200604092345.SAA08483@zion.cs.uiuc.edu> Changes in directory llvm/docs: GettingStarted.html updated: 1.127 -> 1.128 MakefileGuide.html updated: 1.30 -> 1.31 --- Log message: Update docs for ENABLE_ASSERTIONS -> DISABLE_ASSERTIONS --- Diffs of the changes: (+9 -8) GettingStarted.html | 6 +++--- MakefileGuide.html | 11 ++++++----- 2 files changed, 9 insertions(+), 8 deletions(-) Index: llvm/docs/GettingStarted.html diff -u llvm/docs/GettingStarted.html:1.127 llvm/docs/GettingStarted.html:1.128 --- llvm/docs/GettingStarted.html:1.127 Mon Mar 20 19:10:57 2006 +++ llvm/docs/GettingStarted.html Sun Apr 9 18:45:37 2006 @@ -955,9 +955,9 @@ Perform a Release (Optimized) build.

    -

    gmake ENABLE_OPTIMIZED=1 ENABLE_ASSERTIONS=1 +
    gmake ENABLE_OPTIMIZED=1 DISABLE_ASSERTIONS=1
    - Perform a Release (Optimized) build with assertions enabled. + Perform a Release (Optimized) build without assertions enabled.

    gmake ENABLE_PROFILING=1 @@ -1551,7 +1551,7 @@ Chris Lattner
    Reid Spencer
    The LLVM Compiler Infrastructure
    - Last modified: $Date: 2006/03/21 01:10:57 $ + Last modified: $Date: 2006/04/09 23:45:37 $ Index: llvm/docs/MakefileGuide.html diff -u llvm/docs/MakefileGuide.html:1.30 llvm/docs/MakefileGuide.html:1.31 --- llvm/docs/MakefileGuide.html:1.30 Thu Mar 23 00:19:04 2006 +++ llvm/docs/MakefileGuide.html Sun Apr 9 18:45:38 2006 @@ -632,10 +632,11 @@ to the compilers and linkers to ensure that profile data can be collected from the tools built. Use the gprof tool to analyze the output from the profiled tools (gmon.out).
  • -
    ENABLE_ASSERTIONS
    -
    If set to any value, causes the build to enable assertions, even if - building a release or profile build. This is slower than a release build - but far faster than a debug build.
    +
    DISABLE_ASSERTIONS
    +
    If set to any value, causes the build to disable assertions, even if + building a release or profile build. This will exclude all assertion check + code from the build. LLVM will execute faster, but with little help when + things go wrong.
    EXPERIMENTAL_DIRS
    Specify a set of directories that should be built, but if they fail, it should not cause the build to fail. Note that this should only be used @@ -999,7 +1000,7 @@ Reid Spencer
    The LLVM Compiler Infrastructure
    - Last modified: $Date: 2006/03/23 06:19:04 $ + Last modified: $Date: 2006/04/09 23:45:38 $